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module buffer_test();
localparam B = 1024;
reg CLOCK_50, rst;
reg [31:0] counter;
reg new_sample_val;
wire [31:0] pitch_shift_out;
wire pitch_shift_val;
// make reset
initial begin
CLOCK_50 = 1'b0;
rst = 1'b0;
counter = 32'b0;
new_sample_val = 1'b0;
#50
rst = 1'b1;
#100
rst = 1'b0;
end
// make clock
always begin
#10
CLOCK_50 = !CLOCK_50;
end
always begin
#50
counter = counter + 1;
new_sample_val = 1'b1;
#10
new_sample_val = 1'b0;
end
buffer #(B) b1
(
//inputs
.clk(CLOCK_50),
.rst(rst),
.delta(8'b01000000), // 1 in fixed3.5
.new_sample_val(new_sample_val),
.new_sample_data(counter),
.out_sel(1'b0),
.delta_mode(1'b0),
//outputs
.pitch_shift_out(pitch_shift_out),
.pitch_shift_val(pitch_shift_val)
);
endmodule |
module EBABWrapper
(
/*AUTOARG*/
// Outputs
bus_byte_enable, bus_read, bus_write, bus_write_data, bus_addr,
// Inputs
clk, rst, out_sel, delta_mode_left, delta_mode_right, bus_ack,
bus_read_data, delta_left, delta_right, triangle_wave_max_left,
triangle_wave_max_right
);
input clk, rst, out_sel, delta_mode_left, delta_mode_right;
input bus_ack; // Avalon bus raises this when done
input [31:0] bus_read_data; // data from Avalon bus
input [31:0] delta_left, delta_right;
input [9:0] triangle_wave_max_left, triangle_wave_max_right;
output reg [3:0] bus_byte_enable; // four bit byte read/write mask
output reg bus_read; // high when requesting data
output reg bus_write; // high when writing data
output reg [31:0] bus_write_data; // data to send to Avalog bus
output reg [31:0] bus_addr; // Avalon address
wire [31:0] audio_base_address = 32'h00003040; // Avalon address
wire [31:0] audio_fifo_address = 32'h00003044; // Avalon address +4
wire [31:0] audio_data_left_address = 32'h00003048; // Avalon address +8
wire [31:0] audio_data_right_address = 32'h0000304c; // Avalon address +12
reg [3:0] state;
reg [7:0] fifo_space; // current free words in audio interface
// audio input/output from audio module FIFO
reg [31:0] right_audio_input, left_audio_input;
reg audio_input_valid;
wire [31:0] right_audio_output, left_audio_output, pitch_shift_out[0:1], filter_out[0:1];
wire pitch_shift_val[0:1], audio_out_val[0:1];
assign left_audio_output = (audio_out_val[0]) ? filter_out[0] : left_audio_output;
assign right_audio_output = (audio_out_val[1]) ? filter_out[1] : right_audio_output;
buffer #(1024) left_buffer
(
// inputs
.clk(clk),
.rst(rst),
.delta(delta_left),
.new_sample_val(audio_input_valid),
.new_sample_data(right_audio_input),
.out_sel(1'b1),
.delta_mode(delta_mode_left),
.triangle_wave_max(triangle_wave_max_left),
// outputs
.pitch_shift_out(pitch_shift_out[0]),
.pitch_shift_val(pitch_shift_val[0])
);
buffer #(1024) right_buffer
(
// inputs
.clk(clk),
.rst(rst),
.delta(delta_right),
.new_sample_val(audio_input_valid),
.new_sample_data(right_audio_input),
.out_sel(1'b1),
.delta_mode(delta_mode_right),
.triangle_wave_max(triangle_wave_max_right),
// outputs
.pitch_shift_out(pitch_shift_out[1]),
.pitch_shift_val(pitch_shift_val[1])
);
IIR6_32bit_fixed filter_left(
.audio_out (filter_out[0]),
.audio_in (pitch_shift_out[0]),
.scale (3'd3),
.b1 (32'h226C),
.b2 (32'hCE8B),
.b3 (32'h2045B),
.b4 (32'h2B07A),
.b5 (32'h2045B),
.b6 (32'hCE8B),
.b7 (32'h226C),
.a2 (32'h21DC9D38),
.a3 (32'hC2BABD8C),
.a4 (32'h3C58991F),
.a5 (32'hDDFDB62D),
.a6 (32'hA5FA11C),
.a7 (32'hFEAA19B2),
.clk(clk),
.data_val(pitch_shift_val[0]),
.rst(rst),
.audio_out_val(audio_out_val[0])
) ; //end filter
IIR6_32bit_fixed filter_right(
.audio_out (filter_out[1]),
.audio_in (pitch_shift_out[1]),
.scale (3'd3),
.b1 (32'h226C),
.b2 (32'hCE8B),
.b3 (32'h2045B),
.b4 (32'h2B07A),
.b5 (32'h2045B),
.b6 (32'hCE8B),
.b7 (32'h226C),
.a2 (32'h21DC9D38),
.a3 (32'hC2BABD8C),
.a4 (32'h3C58991F),
.a5 (32'hDDFDB62D),
.a6 (32'hA5FA11C),
.a7 (32'hFEAA19B2),
.clk(clk),
.data_val(pitch_shift_val[1]),
.rst(rst),
.audio_out_val(audio_out_val[1])
) ; //end filter
always @(posedge clk) begin //CLOCK_50
// reset state machine and read/write controls
if (rst) begin
state <= 0;
bus_read <= 0; // set to one if a read opeation from bus
bus_write <= 0; // set to one if a write operation to bus
end
// === writing stereo to the audio FIFO ==========
// set up read FIFO available space
if (state==4'd0) begin
bus_addr <= audio_fifo_address;
bus_read <= 1'b1;
bus_byte_enable <= 4'b1111;
state <= 4'd1; // wait for read ACK
end
// wait for read ACK and read the fifo available
// bus ACK is high when data is available
if (state==4'd1 && bus_ack==1) begin
state <= 4'd2; //4'd2
// FIFO write space is in high byte
fifo_space <= (bus_read_data>>24);
// end the read
bus_read <= 1'b0;
end
// When there is room in the FIFO
// -- start write to fifo for each channel
// -- first the left channel
if (state==4'd2 && fifo_space>8'd2) begin //
state <= 4'd3;
bus_write_data <= left_audio_output;
bus_addr <= audio_data_left_address;
bus_byte_enable <= 4'b1111;
bus_write <= 1'b1;
end
// if no space, try again later
else if (state==4'd2 && fifo_space<=8'd2) begin
state <= 4'b0;
end
// detect bus-transaction-complete ACK
// for left channel write
// You MUST do this check
if (state==4'd3 && bus_ack==1) begin
state <= 4'd4; // include right channel
//state <= 4'd0; // left channel only, write only.
//state <= 4'd6; // read/write left channel only
bus_write <= 0;
end
// -- now the right channel
if (state==4'd4) begin //
state <= 4'd5;
// loop back audio input data
bus_write_data <= right_audio_output;
bus_addr <= audio_data_right_address;
bus_write <= 1'b1;
end
// detect bus-transaction-complete ACK
// for right channel write
// You MUST do this check
if (state==4'd5 && bus_ack==1) begin
// state <= 4'd0; // for write only function
state <= 4'd6; // for read/write function
bus_write <= 0;
end
// === reading stereo from the audio FIFO ==========
// set up read FIFO for available read values
if (state==4'd6 ) begin
bus_addr <= audio_fifo_address;
bus_read <= 1'b1;
bus_byte_enable <= 4'b1111;
state <= 4'd7; // wait for read ACK
end
// wait for read ACK and read the fifo available
// bus ACK is high when data is available
if (state==4'd7 && bus_ack==1) begin
state <= 4'd8; //4'dxx
// FIFO read space is in low byte
// which is zero when empty
fifo_space <= bus_read_data & 8'hff;
// end the read
bus_read <= 1'b0;
end
// When there is data in the read FIFO
// -- read it from both channels
// -- first the left channel
if (state==4'd8 && fifo_space>8'd0) begin //
state <= 4'd9;
bus_addr <= audio_data_left_address;
bus_byte_enable <= 4'b1111;
bus_read <= 1'b1;
end
// if no data, try again later
else if (state==4'd8 && fifo_space<=8'd0) begin
state <= 4'b0;
end
// detect bus-transaction-complete ACK
// for left channel read
// You MUST do this check
if (state==4'd9 && bus_ack==1) begin
state <= 4'd10; // include right channel
left_audio_input <= bus_read_data;
bus_read <= 0;
end
// When there is data in the read FIFO
// -- read it from both channels
// -- now right channel
if (state==4'd10) begin //
state <= 4'd11;
bus_addr <= audio_data_right_address;
bus_byte_enable <= 4'b1111;
bus_read <= 1'b1;
end
// detect bus-transaction-complete ACK
// for right channel read
// You MUST do this check
if (state==4'd11 && bus_ack==1) begin
state <= 4'd12; // back to beginning
right_audio_input <= bus_read_data;
// set the data-ready strobe
audio_input_valid <= 1'b1;
bus_read <= 0;
end
// end data-ready strobe
if (state==4'd12) begin
state <= 4'd0; // back to beginning
audio_input_valid <= 1'b0;
end
end // always @(posedge state_clock)
endmodule // EBABWrapper |
module DE1_SoC_Computer
(
////////////////////////////////////
// FPGA Pins
////////////////////////////////////
// Clock pins
CLOCK_50,
CLOCK2_50,
CLOCK3_50,
CLOCK4_50,
// ADC
ADC_CS_N,
ADC_DIN,
ADC_DOUT,
ADC_SCLK,
// Audio
AUD_ADCDAT,
AUD_ADCLRCK,
AUD_BCLK,
AUD_DACDAT,
AUD_DACLRCK,
AUD_XCK,
// SDRAM
DRAM_ADDR,
DRAM_BA,
DRAM_CAS_N,
DRAM_CKE,
DRAM_CLK,
DRAM_CS_N,
DRAM_DQ,
DRAM_LDQM,
DRAM_RAS_N,
DRAM_UDQM,
DRAM_WE_N,
// I2C Bus for Configuration of the Audio and Video-In Chips
FPGA_I2C_SCLK,
FPGA_I2C_SDAT,
// 40-Pin Headers
GPIO_0,
GPIO_1,
// Seven Segment Displays
HEX0,
HEX1,
HEX2,
HEX3,
HEX4,
HEX5,
// IR
IRDA_RXD,
IRDA_TXD,
// Pushbuttons
KEY,
// LEDs
LEDR,
// PS2 Ports
PS2_CLK,
PS2_DAT,
PS2_CLK2,
PS2_DAT2,
// Slider Switches
SW,
// Video-In
TD_CLK27,
TD_DATA,
TD_HS,
TD_RESET_N,
TD_VS,
// VGA
VGA_B,
VGA_BLANK_N,
VGA_CLK,
VGA_G,
VGA_HS,
VGA_R,
VGA_SYNC_N,
VGA_VS,
////////////////////////////////////
// HPS Pins
////////////////////////////////////
// DDR3 SDRAM
HPS_DDR3_ADDR,
HPS_DDR3_BA,
HPS_DDR3_CAS_N,
HPS_DDR3_CKE,
HPS_DDR3_CK_N,
HPS_DDR3_CK_P,
HPS_DDR3_CS_N,
HPS_DDR3_DM,
HPS_DDR3_DQ,
HPS_DDR3_DQS_N,
HPS_DDR3_DQS_P,
HPS_DDR3_ODT,
HPS_DDR3_RAS_N,
HPS_DDR3_RESET_N,
HPS_DDR3_RZQ,
HPS_DDR3_WE_N,
// Ethernet
HPS_ENET_GTX_CLK,
HPS_ENET_INT_N,
HPS_ENET_MDC,
HPS_ENET_MDIO,
HPS_ENET_RX_CLK,
HPS_ENET_RX_DATA,
HPS_ENET_RX_DV,
HPS_ENET_TX_DATA,
HPS_ENET_TX_EN,
// Flash
HPS_FLASH_DATA,
HPS_FLASH_DCLK,
HPS_FLASH_NCSO,
// Accelerometer
HPS_GSENSOR_INT,
// General Purpose I/O
HPS_GPIO,
// I2C
HPS_I2C_CONTROL,
HPS_I2C1_SCLK,
HPS_I2C1_SDAT,
HPS_I2C2_SCLK,
HPS_I2C2_SDAT,
// Pushbutton
HPS_KEY,
// LED
HPS_LED,
// SD Card
HPS_SD_CLK,
HPS_SD_CMD,
HPS_SD_DATA,
// SPI
HPS_SPIM_CLK,
HPS_SPIM_MISO,
HPS_SPIM_MOSI,
HPS_SPIM_SS,
// UART
HPS_UART_RX,
HPS_UART_TX,
// USB
HPS_CONV_USB_N,
HPS_USB_CLKOUT,
HPS_USB_DATA,
HPS_USB_DIR,
HPS_USB_NXT,
HPS_USB_STP
);
////////////////////////////////////
// FPGA Pins
////////////////////////////////////
// Clock pins
input CLOCK_50;
input CLOCK2_50;
input CLOCK3_50;
input CLOCK4_50;
// ADC
inout ADC_CS_N;
output ADC_DIN;
input ADC_DOUT;
output ADC_SCLK;
// Audio
input AUD_ADCDAT;
inout AUD_ADCLRCK;
inout AUD_BCLK;
output AUD_DACDAT;
inout AUD_DACLRCK;
output AUD_XCK;
// SDRAM
output [12:0] DRAM_ADDR;
output [1:0] DRAM_BA;
output DRAM_CAS_N;
output DRAM_CKE;
output DRAM_CLK;
output DRAM_CS_N;
inout [15:0] DRAM_DQ;
output DRAM_LDQM;
output DRAM_RAS_N;
output DRAM_UDQM;
output DRAM_WE_N;
// I2C Bus for Configuration of the Audio and Video-In Chips
output FPGA_I2C_SCLK;
inout FPGA_I2C_SDAT;
// 40-pin headers
inout [35:0] GPIO_0;
inout [35:0] GPIO_1;
// Seven Segment Displays
output [6:0] HEX0;
output [6:0] HEX1;
output [6:0] HEX2;
output [6:0] HEX3;
output [6:0] HEX4;
output [6:0] HEX5;
// IR
input IRDA_RXD;
output IRDA_TXD;
// Pushbuttons
input [3:0] KEY;
// LEDs
output [9:0] LEDR;
// PS2 Ports
inout PS2_CLK;
inout PS2_DAT;
inout PS2_CLK2;
inout PS2_DAT2;
// Slider Switches
input [9:0] SW;
// Video-In
input TD_CLK27;
input [7:0] TD_DATA;
input TD_HS;
output TD_RESET_N;
input TD_VS;
// VGA
output [7:0] VGA_B;
output VGA_BLANK_N;
output VGA_CLK;
output [7:0] VGA_G;
output VGA_HS;
output [7:0] VGA_R;
output VGA_SYNC_N;
output VGA_VS;
////////////////////////////////////
// HPS Pins
////////////////////////////////////
// DDR3 SDRAM
output [14:0] HPS_DDR3_ADDR;
output [2:0] HPS_DDR3_BA;
output HPS_DDR3_CAS_N;
output HPS_DDR3_CKE;
output HPS_DDR3_CK_N;
output HPS_DDR3_CK_P;
output HPS_DDR3_CS_N;
output [3:0] HPS_DDR3_DM;
inout [31:0] HPS_DDR3_DQ;
inout [3:0] HPS_DDR3_DQS_N;
inout [3:0] HPS_DDR3_DQS_P;
output HPS_DDR3_ODT;
output HPS_DDR3_RAS_N;
output HPS_DDR3_RESET_N;
input HPS_DDR3_RZQ;
output HPS_DDR3_WE_N;
// Ethernet
output HPS_ENET_GTX_CLK;
inout HPS_ENET_INT_N;
output HPS_ENET_MDC;
inout HPS_ENET_MDIO;
input HPS_ENET_RX_CLK;
input [3:0] HPS_ENET_RX_DATA;
input HPS_ENET_RX_DV;
output [3:0] HPS_ENET_TX_DATA;
output HPS_ENET_TX_EN;
// Flash
inout [3:0] HPS_FLASH_DATA;
output HPS_FLASH_DCLK;
output HPS_FLASH_NCSO;
// Accelerometer
inout HPS_GSENSOR_INT;
// General Purpose I/O
inout [1:0] HPS_GPIO;
// I2C
inout HPS_I2C_CONTROL;
inout HPS_I2C1_SCLK;
inout HPS_I2C1_SDAT;
inout HPS_I2C2_SCLK;
inout HPS_I2C2_SDAT;
// Pushbutton
inout HPS_KEY;
// LED
inout HPS_LED;
// SD Card
output HPS_SD_CLK;
inout HPS_SD_CMD;
inout [3:0] HPS_SD_DATA;
// SPI
output HPS_SPIM_CLK;
input HPS_SPIM_MISO;
output HPS_SPIM_MOSI;
inout HPS_SPIM_SS;
// UART
input HPS_UART_RX;
output HPS_UART_TX;
// USB
inout HPS_CONV_USB_N;
input HPS_USB_CLKOUT;
inout [70] HPS_USB_DATA;
input HPS_USB_DIR;
input HPS_USB_NXT;
output HPS_USB_STP;
//=======================================================
// REG/WIRE declarations
//=======================================================
assign HEX4 = 7'b1111111;
assign HEX5 = 7'b1111111;
assign HEX3 = 7'b1111111;
assign HEX2 = 7'b1111111;
assign HEX1 = 7'b1111111;
//=======================================================
// Bus controller for AVALON bus-master
//=======================================================
// computes DDS for sine wave and fills audio FIFO
// reads audio FIFO and loops it back
// MUST configure (in Qsys) Audio Config module
// -- Line in to ADC
// -- uncheck both bypass options
wire [31:0] bus_addr; // Avalon address
wire [3:0] bus_byte_enable; // four bit byte read/write mask
wire bus_read; // high when requesting data
wire bus_write; // high when writing data
wire [31:0] bus_write_data; // data to send to Avalog bus
wire bus_ack; // Avalon bus raises this when done
wire [31:0] bus_read_data; // data from Avalon bus
wire rst, hps_rst;
assign rst = ~KEY[0] || hps_rst;
wire [31:0] delta_left;
wire [31:0] delta_right;
wire delta_mode_left, delta_mode_right;
wire [9:0] triangle_wave_max_left, triangle_wave_max_right;
EBABWrapper ebab_wrapper
(
// Outputs
.bus_byte_enable(bus_byte_enable),
.bus_read(bus_read),
.bus_write(bus_write),
.bus_write_data(bus_write_data),
.bus_addr(bus_addr),
// Inputs
.clk(CLOCK_50),
.rst(rst | hps_rst),
.bus_ack(bus_ack),
.bus_read_data(bus_read_data),
.delta_left(delta_left),
.delta_right(delta_right),
.out_sel(SW[9]),
.delta_mode_left(delta_mode_left),
.delta_mode_right(delta_mode_right),
.triangle_wave_max_right(triangle_wave_max_right),
.triangle_wave_max_left(triangle_wave_max_left)
);
Computer_System The_System
(
////////////////////////////////////
// FPGA Side
////////////////////////////////////
// Global signals
.system_pll_ref_clk_clk (CLOCK_50),
.system_pll_ref_reset_reset (1'b0),
// AV Config
.av_config_SCLK (FPGA_I2C_SCLK),
.av_config_SDAT (FPGA_I2C_SDAT),
// Audio Subsystem
.audio_pll_ref_clk_clk (CLOCK3_50),
.audio_pll_ref_reset_reset (1'b0),
.audio_clk_clk (AUD_XCK),
.audio_ADCDAT (AUD_ADCDAT),
.audio_ADCLRCK (AUD_ADCLRCK),
.audio_BCLK (AUD_BCLK),
.audio_DACDAT (AUD_DACDAT),
.audio_DACLRCK (AUD_DACLRCK),
// HPS slaves
.reset_slave_external_connection_export (hps_rst),
.delta_left_slave_external_connection_export (delta_left),
.delta_right_slave_external_connection_export (delta_right),
.triangle_wave_max_left_slave_external_connection_export (triangle_wave_max_left),
.triangle_wave_max_right_slave_external_connection_export (triangle_wave_max_right),
.delta_mode_right_slave_external_connection_export (delta_mode_right),
.delta_mode_left_slave_external_connection_export (delta_mode_left),
// bus-master state machine interface
.bus_master_audio_external_interface_address (bus_addr),
.bus_master_audio_external_interface_byte_enable (bus_byte_enable),
.bus_master_audio_external_interface_read (bus_read),
.bus_master_audio_external_interface_write (bus_write),
.bus_master_audio_external_interface_write_data (bus_write_data),
.bus_master_audio_external_interface_acknowledge (bus_ack),
.bus_master_audio_external_interface_read_data (bus_read_data),
// VGA Subsystem
.vga_pll_ref_clk_clk (CLOCK2_50),
.vga_pll_ref_reset_reset (1'b0),
.vga_CLK (VGA_CLK),
.vga_BLANK (VGA_BLANK_N),
.vga_SYNC (VGA_SYNC_N),
.vga_HS (VGA_HS),
.vga_VS (VGA_VS),
.vga_R (VGA_R),
.vga_G (VGA_G),
.vga_B (VGA_B),
// SDRAM
.sdram_clk_clk (DRAM_CLK),
.sdram_addr (DRAM_ADDR),
.sdram_ba (DRAM_BA),
.sdram_cas_n (DRAM_CAS_N),
.sdram_cke (DRAM_CKE),
.sdram_cs_n (DRAM_CS_N),
.sdram_dq (DRAM_DQ),
.sdram_dqm ({DRAM_UDQM,DRAM_LDQM}),
.sdram_ras_n (DRAM_RAS_N),
.sdram_we_n (DRAM_WE_N),
////////////////////////////////////
// HPS Side
////////////////////////////////////
// DDR3 SDRAM
.memory_mem_a (HPS_DDR3_ADDR),
.memory_mem_ba (HPS_DDR3_BA),
.memory_mem_ck (HPS_DDR3_CK_P),
.memory_mem_ck_n (HPS_DDR3_CK_N),
.memory_mem_cke (HPS_DDR3_CKE),
.memory_mem_cs_n (HPS_DDR3_CS_N),
.memory_mem_ras_n (HPS_DDR3_RAS_N),
.memory_mem_cas_n (HPS_DDR3_CAS_N),
.memory_mem_we_n (HPS_DDR3_WE_N),
.memory_mem_reset_n (HPS_DDR3_RESET_N),
.memory_mem_dq (HPS_DDR3_DQ),
.memory_mem_dqs (HPS_DDR3_DQS_P),
.memory_mem_dqs_n (HPS_DDR3_DQS_N),
.memory_mem_odt (HPS_DDR3_ODT),
.memory_mem_dm (HPS_DDR3_DM),
.memory_oct_rzqin (HPS_DDR3_RZQ),
// Ethernet
.hps_io_hps_io_gpio_inst_GPIO35 (HPS_ENET_INT_N),
.hps_io_hps_io_emac1_inst_TX_CLK (HPS_ENET_GTX_CLK),
.hps_io_hps_io_emac1_inst_TXD0 (HPS_ENET_TX_DATA[0]),
.hps_io_hps_io_emac1_inst_TXD1 (HPS_ENET_TX_DATA[1]),
.hps_io_hps_io_emac1_inst_TXD2 (HPS_ENET_TX_DATA[2]),
.hps_io_hps_io_emac1_inst_TXD3 (HPS_ENET_TX_DATA[3]),
.hps_io_hps_io_emac1_inst_RXD0 (HPS_ENET_RX_DATA[0]),
.hps_io_hps_io_emac1_inst_MDIO (HPS_ENET_MDIO),
.hps_io_hps_io_emac1_inst_MDC (HPS_ENET_MDC),
.hps_io_hps_io_emac1_inst_RX_CTL (HPS_ENET_RX_DV),
.hps_io_hps_io_emac1_inst_TX_CTL (HPS_ENET_TX_EN),
.hps_io_hps_io_emac1_inst_RX_CLK (HPS_ENET_RX_CLK),
.hps_io_hps_io_emac1_inst_RXD1 (HPS_ENET_RX_DATA[1]),
.hps_io_hps_io_emac1_inst_RXD2 (HPS_ENET_RX_DATA[2]),
.hps_io_hps_io_emac1_inst_RXD3 (HPS_ENET_RX_DATA[3]),
// Flash
.hps_io_hps_io_qspi_inst_IO0 (HPS_FLASH_DATA[0]),
.hps_io_hps_io_qspi_inst_IO1 (HPS_FLASH_DATA[1]),
.hps_io_hps_io_qspi_inst_IO2 (HPS_FLASH_DATA[2]),
.hps_io_hps_io_qspi_inst_IO3 (HPS_FLASH_DATA[3]),
.hps_io_hps_io_qspi_inst_SS0 (HPS_FLASH_NCSO),
.hps_io_hps_io_qspi_inst_CLK (HPS_FLASH_DCLK),
// Accelerometer
.hps_io_hps_io_gpio_inst_GPIO61 (HPS_GSENSOR_INT),
//.adc_sclk (ADC_SCLK),
//.adc_cs_n (ADC_CS_N),
//.adc_dout (ADC_DOUT),
//.adc_din (ADC_DIN),
// General Purpose I/O
.hps_io_hps_io_gpio_inst_GPIO40 (HPS_GPIO[0]),
.hps_io_hps_io_gpio_inst_GPIO41 (HPS_GPIO[1]),
// I2C
.hps_io_hps_io_gpio_inst_GPIO48 (HPS_I2C_CONTROL),
.hps_io_hps_io_i2c0_inst_SDA (HPS_I2C1_SDAT),
.hps_io_hps_io_i2c0_inst_SCL (HPS_I2C1_SCLK),
.hps_io_hps_io_i2c1_inst_SDA (HPS_I2C2_SDAT),
.hps_io_hps_io_i2c1_inst_SCL (HPS_I2C2_SCLK),
// Pushbutton
.hps_io_hps_io_gpio_inst_GPIO54 (HPS_KEY),
// LED
.hps_io_hps_io_gpio_inst_GPIO53 (HPS_LED),
// SD Card
.hps_io_hps_io_sdio_inst_CMD (HPS_SD_CMD),
.hps_io_hps_io_sdio_inst_D0 (HPS_SD_DATA[0]),
.hps_io_hps_io_sdio_inst_D1 (HPS_SD_DATA[1]),
.hps_io_hps_io_sdio_inst_CLK (HPS_SD_CLK),
.hps_io_hps_io_sdio_inst_D2 (HPS_SD_DATA[2]),
.hps_io_hps_io_sdio_inst_D3 (HPS_SD_DATA[3]),
// SPI
.hps_io_hps_io_spim1_inst_CLK (HPS_SPIM_CLK),
.hps_io_hps_io_spim1_inst_MOSI (HPS_SPIM_MOSI),
.hps_io_hps_io_spim1_inst_MISO (HPS_SPIM_MISO),
.hps_io_hps_io_spim1_inst_SS0 (HPS_SPIM_SS),
// UART
.hps_io_hps_io_uart0_inst_RX (HPS_UART_RX),
.hps_io_hps_io_uart0_inst_TX (HPS_UART_TX),
// USB
.hps_io_hps_io_gpio_inst_GPIO09 (HPS_CONV_USB_N),
.hps_io_hps_io_usb1_inst_D0 (HPS_USB_DATA[0]),
.hps_io_hps_io_usb1_inst_D1 (HPS_USB_DATA[1]),
.hps_io_hps_io_usb1_inst_D2 (HPS_USB_DATA[2]),
.hps_io_hps_io_usb1_inst_D3 (HPS_USB_DATA[3]),
.hps_io_hps_io_usb1_inst_D4 (HPS_USB_DATA[4]),
.hps_io_hps_io_usb1_inst_D5 (HPS_USB_DATA[5]),
.hps_io_hps_io_usb1_inst_D6 (HPS_USB_DATA[6]),
.hps_io_hps_io_usb1_inst_D7 (HPS_USB_DATA[7]),
.hps_io_hps_io_usb1_inst_CLK (HPS_USB_CLKOUT),
.hps_io_hps_io_usb1_inst_STP (HPS_USB_STP),
.hps_io_hps_io_usb1_inst_DIR (HPS_USB_DIR),
.hps_io_hps_io_usb1_inst_NXT (HPS_USB_NXT)
);
endmodule // DE1_SoC_Computer |
module butter_test();
reg rst, CLOCK_50;
reg [31:0] counter;
reg audio_input_ready;
// DDS update signal for testing
reg [31:0] dds_accum;
// DDS LUT
reg [31:0] sine_out;
wire [31:0] my_out;
// make reset
initial begin
counter = 32'b0;
CLOCK_50 = 1'b0;
audio_input_ready = 1'b0;
dds_accum = 32'd0;
sine_out = 32'h7fff_ffff;
rst = 1'b0;
#50
rst = 1'b1;
#100
rst = 1'b0;
end
// make clock
always begin
#10
CLOCK_50 = !CLOCK_50;
end
always begin
#1000000
sine_out = ~sine_out;
end
always begin
#20813
audio_input_ready = 1;
#20
audio_input_ready = 0;
end
// update phase accumulator
// sync to audio data rate (48kHz) using audio_input_ready signal
/*always @(posedge CLOCK_50) begin //CLOCK_50
// Fout = (sample_rate)/(2^32)*(constant)
// then Fout=48000/(2^32)*(44739242) = 500 Hz
if (audio_input_ready) dds_accum <= dds_accum + 32'd44739242;
end*/
// DDS sine wave ROM
//sync_rom sineTable(CLOCK_50, dds_accum[31:24], sine_out);
//Filter: cutoff=0.145833
IIR6_32bit_fixed filter(
.audio_out (my_out),
.audio_in (sine_out),
.scale (3'd3),
.b1 (32'h226C),
.b2 (32'hCE8B),
.b3 (32'h2045B),
.b4 (32'h2B07A),
.b5 (32'h2045B),
.b6 (32'hCE8B),
.b7 (32'h226C),
.a2 (32'h21DC9D38),
.a3 (32'hC2BABD8C),
.a4 (32'h3C58991F),
.a5 (32'hDDFDB62D),
.a6 (32'hA5FA11C),
.a7 (32'hFEAA19B2),
.clk(CLOCK_50),
.data_val(audio_input_ready),
.rst(rst),
.audio_out_val(audio_out_val)
); //end filter
endmodule |
module sync_rom (clock, address, sine);
input clock;
input [7:0] address;
output [15:0] sine;
reg signed [15:0] sine;
always@(posedge clock)
begin
case(address)
8'h00: sine = 16'h0000;
8'h01: sine = 16'h0192;
8'h02: sine = 16'h0323;
8'h03: sine = 16'h04b5;
8'h04: sine = 16'h0645;
8'h05: sine = 16'h07d5;
8'h06: sine = 16'h0963;
8'h07: sine = 16'h0af0;
8'h08: sine = 16'h0c7c;
8'h09: sine = 16'h0e05;
8'h0a: sine = 16'h0f8c;
8'h0b: sine = 16'h1111;
8'h0c: sine = 16'h1293;
8'h0d: sine = 16'h1413;
8'h0e: sine = 16'h158f;
8'h0f: sine = 16'h1708;
8'h10: sine = 16'h187d;
8'h11: sine = 16'h19ef;
8'h12: sine = 16'h1b5c;
8'h13: sine = 16'h1cc5;
8'h14: sine = 16'h1e2a;
8'h15: sine = 16'h1f8b;
8'h16: sine = 16'h20e6;
8'h17: sine = 16'h223c;
8'h18: sine = 16'h238d;
8'h19: sine = 16'h24d9;
8'h1a: sine = 16'h261f;
8'h1b: sine = 16'h275f;
8'h1c: sine = 16'h2899;
8'h1d: sine = 16'h29cc;
8'h1e: sine = 16'h2afa;
8'h1f: sine = 16'h2c20;
8'h20: sine = 16'h2d40;
8'h21: sine = 16'h2e59;
8'h22: sine = 16'h2f6b;
8'h23: sine = 16'h3075;
8'h24: sine = 16'h3178;
8'h25: sine = 16'h3273;
8'h26: sine = 16'h3366;
8'h27: sine = 16'h3452;
8'h28: sine = 16'h3535;
8'h29: sine = 16'h3611;
8'h2a: sine = 16'h36e4;
8'h2b: sine = 16'h37ae;
8'h2c: sine = 16'h3870;
8'h2d: sine = 16'h3929;
8'h2e: sine = 16'h39da;
8'h2f: sine = 16'h3a81;
8'h30: sine = 16'h3b1f;
8'h31: sine = 16'h3bb5;
8'h32: sine = 16'h3c41;
8'h33: sine = 16'h3cc4;
8'h34: sine = 16'h3d3d;
8'h35: sine = 16'h3dad;
8'h36: sine = 16'h3e14;
8'h37: sine = 16'h3e70;
8'h38: sine = 16'h3ec4;
8'h39: sine = 16'h3f0d;
8'h3a: sine = 16'h3f4d;
8'h3b: sine = 16'h3f83;
8'h3c: sine = 16'h3fb0;
8'h3d: sine = 16'h3fd2;
8'h3e: sine = 16'h3feb;
8'h3f: sine = 16'h3ffa;
8'h40: sine = 16'h3fff;
8'h41: sine = 16'h3ffa;
8'h42: sine = 16'h3feb;
8'h43: sine = 16'h3fd2;
8'h44: sine = 16'h3fb0;
8'h45: sine = 16'h3f83;
8'h46: sine = 16'h3f4d;
8'h47: sine = 16'h3f0d;
8'h48: sine = 16'h3ec4;
8'h49: sine = 16'h3e70;
8'h4a: sine = 16'h3e14;
8'h4b: sine = 16'h3dad;
8'h4c: sine = 16'h3d3d;
8'h4d: sine = 16'h3cc4;
8'h4e: sine = 16'h3c41;
8'h4f: sine = 16'h3bb5;
8'h50: sine = 16'h3b1f;
8'h51: sine = 16'h3a81;
8'h52: sine = 16'h39da;
8'h53: sine = 16'h3929;
8'h54: sine = 16'h3870;
8'h55: sine = 16'h37ae;
8'h56: sine = 16'h36e4;
8'h57: sine = 16'h3611;
8'h58: sine = 16'h3535;
8'h59: sine = 16'h3452;
8'h5a: sine = 16'h3366;
8'h5b: sine = 16'h3273;
8'h5c: sine = 16'h3178;
8'h5d: sine = 16'h3075;
8'h5e: sine = 16'h2f6b;
8'h5f: sine = 16'h2e59;
8'h60: sine = 16'h2d40;
8'h61: sine = 16'h2c20;
8'h62: sine = 16'h2afa;
8'h63: sine = 16'h29cc;
8'h64: sine = 16'h2899;
8'h65: sine = 16'h275f;
8'h66: sine = 16'h261f;
8'h67: sine = 16'h24d9;
8'h68: sine = 16'h238d;
8'h69: sine = 16'h223c;
8'h6a: sine = 16'h20e6;
8'h6b: sine = 16'h1f8b;
8'h6c: sine = 16'h1e2a;
8'h6d: sine = 16'h1cc5;
8'h6e: sine = 16'h1b5c;
8'h6f: sine = 16'h19ef;
8'h70: sine = 16'h187d;
8'h71: sine = 16'h1708;
8'h72: sine = 16'h158f;
8'h73: sine = 16'h1413;
8'h74: sine = 16'h1293;
8'h75: sine = 16'h1111;
8'h76: sine = 16'h0f8c;
8'h77: sine = 16'h0e05;
8'h78: sine = 16'h0c7c;
8'h79: sine = 16'h0af0;
8'h7a: sine = 16'h0963;
8'h7b: sine = 16'h07d5;
8'h7c: sine = 16'h0645;
8'h7d: sine = 16'h04b5;
8'h7e: sine = 16'h0323;
8'h7f: sine = 16'h0192;
8'h80: sine = 16'h0000;
8'h81: sine = 16'hfe6e;
8'h82: sine = 16'hfcdd;
8'h83: sine = 16'hfb4b;
8'h84: sine = 16'hf9bb;
8'h85: sine = 16'hf82b;
8'h86: sine = 16'hf69d;
8'h87: sine = 16'hf510;
8'h88: sine = 16'hf384;
8'h89: sine = 16'hf1fb;
8'h8a: sine = 16'hf074;
8'h8b: sine = 16'heeef;
8'h8c: sine = 16'hed6d;
8'h8d: sine = 16'hebed;
8'h8e: sine = 16'hea71;
8'h8f: sine = 16'he8f8;
8'h90: sine = 16'he783;
8'h91: sine = 16'he611;
8'h92: sine = 16'he4a4;
8'h93: sine = 16'he33b;
8'h94: sine = 16'he1d6;
8'h95: sine = 16'he075;
8'h96: sine = 16'hdf1a;
8'h97: sine = 16'hddc4;
8'h98: sine = 16'hdc73;
8'h99: sine = 16'hdb27;
8'h9a: sine = 16'hd9e1;
8'h9b: sine = 16'hd8a1;
8'h9c: sine = 16'hd767;
8'h9d: sine = 16'hd634;
8'h9e: sine = 16'hd506;
8'h9f: sine = 16'hd3e0;
8'ha0: sine = 16'hd2c0;
8'ha1: sine = 16'hd1a7;
8'ha2: sine = 16'hd095;
8'ha3: sine = 16'hcf8b;
8'ha4: sine = 16'hce88;
8'ha5: sine = 16'hcd8d;
8'ha6: sine = 16'hcc9a;
8'ha7: sine = 16'hcbae;
8'ha8: sine = 16'hcacb;
8'ha9: sine = 16'hc9ef;
8'haa: sine = 16'hc91c;
8'hab: sine = 16'hc852;
8'hac: sine = 16'hc790;
8'had: sine = 16'hc6d7;
8'hae: sine = 16'hc626;
8'haf: sine = 16'hc57f;
8'hb0: sine = 16'hc4e1;
8'hb1: sine = 16'hc44b;
8'hb2: sine = 16'hc3bf;
8'hb3: sine = 16'hc33c;
8'hb4: sine = 16'hc2c3;
8'hb5: sine = 16'hc253;
8'hb6: sine = 16'hc1ec;
8'hb7: sine = 16'hc190;
8'hb8: sine = 16'hc13c;
8'hb9: sine = 16'hc0f3;
8'hba: sine = 16'hc0b3;
8'hbb: sine = 16'hc07d;
8'hbc: sine = 16'hc050;
8'hbd: sine = 16'hc02e;
8'hbe: sine = 16'hc015;
8'hbf: sine = 16'hc006;
8'hc0: sine = 16'hc001;
8'hc1: sine = 16'hc006;
8'hc2: sine = 16'hc015;
8'hc3: sine = 16'hc02e;
8'hc4: sine = 16'hc050;
8'hc5: sine = 16'hc07d;
8'hc6: sine = 16'hc0b3;
8'hc7: sine = 16'hc0f3;
8'hc8: sine = 16'hc13c;
8'hc9: sine = 16'hc190;
8'hca: sine = 16'hc1ec;
8'hcb: sine = 16'hc253;
8'hcc: sine = 16'hc2c3;
8'hcd: sine = 16'hc33c;
8'hce: sine = 16'hc3bf;
8'hcf: sine = 16'hc44b;
8'hd0: sine = 16'hc4e1;
8'hd1: sine = 16'hc57f;
8'hd2: sine = 16'hc626;
8'hd3: sine = 16'hc6d7;
8'hd4: sine = 16'hc790;
8'hd5: sine = 16'hc852;
8'hd6: sine = 16'hc91c;
8'hd7: sine = 16'hc9ef;
8'hd8: sine = 16'hcacb;
8'hd9: sine = 16'hcbae;
8'hda: sine = 16'hcc9a;
8'hdb: sine = 16'hcd8d;
8'hdc: sine = 16'hce88;
8'hdd: sine = 16'hcf8b;
8'hde: sine = 16'hd095;
8'hdf: sine = 16'hd1a7;
8'he0: sine = 16'hd2c0;
8'he1: sine = 16'hd3e0;
8'he2: sine = 16'hd506;
8'he3: sine = 16'hd634;
8'he4: sine = 16'hd767;
8'he5: sine = 16'hd8a1;
8'he6: sine = 16'hd9e1;
8'he7: sine = 16'hdb27;
8'he8: sine = 16'hdc73;
8'he9: sine = 16'hddc4;
8'hea: sine = 16'hdf1a;
8'heb: sine = 16'he075;
8'hec: sine = 16'he1d6;
8'hed: sine = 16'he33b;
8'hee: sine = 16'he4a4;
8'hef: sine = 16'he611;
8'hf0: sine = 16'he783;
8'hf1: sine = 16'he8f8;
8'hf2: sine = 16'hea71;
8'hf3: sine = 16'hebed;
8'hf4: sine = 16'hed6d;
8'hf5: sine = 16'heeef;
8'hf6: sine = 16'hf074;
8'hf7: sine = 16'hf1fb;
8'hf8: sine = 16'hf384;
8'hf9: sine = 16'hf510;
8'hfa: sine = 16'hf69d;
8'hfb: sine = 16'hf82b;
8'hfc: sine = 16'hf9bb;
8'hfd: sine = 16'hfb4b;
8'hfe: sine = 16'hfcdd;
8'hff: sine = 16'hfe6e;
endcase
end
endmodule |
module RAM_512_18
#(parameter B = 1024)
(
output signed [31:0] q,
input signed [31:0] data,
input [($clog2(B)-1):0] wraddress, rdaddress,
input wren, rden, clock
);
reg [8:0] read_address_reg;
reg signed [31:0] mem [(B-1):0] /*synthesis ramstyle = M10K" */;
reg rden_reg;
always @(posedge clock) begin
if (wren)
mem[wraddress] <= data;
end
always @(posedge clock) begin
read_address_reg <= rdaddress;
rden_reg <= rden;
end
assign q = (rden_reg) ? mem[read_address_reg] : 0;
endmodule |
module buffer
#(parameter B=1024)
(
// inputs
clk,
rst,
delta,
new_sample_val,
new_sample_data,
out_sel,
delta_mode, // indicates whether to use fixed or varying delta
triangle_wave_max,
// outputs
pitch_shift_out,
pitch_shift_val
);
input clk, rst, new_sample_val, out_sel, delta_mode;
input [9:0] triangle_wave_max;
//input output_filter_ack;
// pitch-shift amount
input [31:0] delta; // 3.29 format
// audio in
input signed [31:0] new_sample_data;
reg signed [31:0] new_sample_data_reg;
// enables
reg rb1_rden, rb2_rden, rb1_wren, rb2_wren;
// fractional index for pitch shifting (see MATLAB model)
reg [$clog2(B)+28:0] rb1_index; //$clog2(B).29 format
reg [$clog2(B)+28:0] rb2_index;
// actual read address
reg [$clog2(B)-1:0] rb1_read_addr;
reg [$clog2(B)-1:0] rb2_read_addr;
// write address
reg [$clog2(B)-1:0] rb1_write_addr;
reg [$clog2(B)-1:0] rb2_write_addr;
// read data
wire signed [31:0] rb1_read_out;
wire signed [31:0] rb2_read_out;
// state 0 = waiting for new sample
// state 1 =
reg [2:0] state;
// needed for two delta modes
wire [31:0] delta_effective; //or reg?
reg [9:0] delta_rom_addr;
reg [9:0] delta_counter;
wire [31:0] delta_rom_out;
// output interface for next unit
output signed [31:0] pitch_shift_out;
output signed [31:0] pitch_shift_val;
assign pitch_shift_out = (out_sel) ? rb1_read_out
: ((rb1_read_out >>> 1) + (rb2_read_out >>> 1));
assign pitch_shift_val = (state == 3'd2) ? 1'b1 : 1'b0;
// delta_mode = 1 => use input delta
assign delta_effective = (delta_mode) ? delta : delta_rom_out;
RAM_512_18 #(B) rb1
(
.clock(clk),
.q(rb1_read_out),
.rdaddress(rb1_read_addr),
.data(new_sample_data_reg),
.wraddress(rb1_write_addr),
.wren(rb1_wren),
.rden(rb1_rden)
);
RAM_512_18 #(B) rb2
(
.clock(clk),
.q(rb2_read_out),
.rdaddress(rb2_read_addr),
.data(new_sample_data_reg),
.wraddress(rb1_write_addr),
.wren(rb2_wren),
.rden(rb2_rden)
);
// ROM for time varying delta
delta_rom d1 (.clock(clk),
.address(delta_rom_addr),
.delta_out(delta_rom_out));
always @ (posedge clk) begin
if (rst) begin
state <= 3'd0;
rb1_index <= 0;
rb2_index <= 0;
rb1_write_addr <= 0;
rb2_write_addr <= (B/2);
rb1_read_addr <= 0;
rb2_read_addr <= 0;
new_sample_data_reg <= 0;
rb1_rden <= 0;
rb2_rden <= 0;
rb1_wren <= 0;
rb2_wren <= 0;
delta_counter <= 0;
delta_rom_addr <= 0;
end
else if ((state == 3'd0) && new_sample_val) begin
new_sample_data_reg <= new_sample_data;
// increment write addr, modulo rb size
rb1_write_addr <= (rb1_write_addr == (B - 1)) ? 0 : (rb1_write_addr + 1);
rb2_write_addr <= (rb2_write_addr == (B - 1)) ? 0 : (rb2_write_addr + 1);
// update fractional index, modulo rb size
rb1_index <= (rb1_index + delta_effective);
rb2_index <= (rb2_index + delta_effective);
// only take integer part for read address
rb1_read_addr <= rb1_index[$clog2(B)+28 : 29];
rb2_read_addr <= rb2_index[$clog2(B)+28 : 29];
rb1_rden <= 1;
rb2_rden <= 1;
rb1_wren <= 1;
rb2_wren <= 1;
state <= 3'd1;
end
else if ((state == 3'd1)) begin
// done writing
rb1_wren <= 0;
rb2_wren <= 0;
state <= 3'd2;
end
else if ((state == 3'd2)) begin
// done reading
// read_buffer_val is set to one (combinational above)
rb1_rden <= 0;
rb2_rden <= 0;
state <= 3'd0;
// stay on each delta sample for 188 reads (total period of 1sec), then
// go to next address in ROM, restart from address 0 when necessary
delta_counter <= (delta_counter == triangle_wave_max) ? 10'd0
: (delta_counter + 10'd1);
delta_rom_addr <= (delta_counter == triangle_wave_max) ?
((delta_rom_addr == 10'd513 ) ? 10'd0
: (delta_rom_addr + 10'd1)) : delta_rom_addr;
end
else begin
// don't do anything
rb1_rden <= 0;
rb2_rden <= 0;
rb1_wren <= 0;
rb2_wren <= 0;
end
end
endmodule |
module project_top();
reg rst, clk;
wire [31:0] bus_addr; // Avalon address
wire [3:0] bus_byte_enable; // four bit byte read/write mask
wire bus_read; // high when requesting data
wire bus_write; // high when writing data
wire [31:0] bus_write_data; // data to send to Avalog bus
reg bus_ack; // Avalon bus raises this when done
reg [31:0] bus_read_data; // data from Avalon bus
reg [31:0] counter;
wire [31:0] audio_fifo_address = 32'h00003044; // Avalon address +4
wire [31:0] audio_left_address = 32'h00003048; // Avalon address +8
wire [31:0] audio_right_address = 32'h0000304c; // Avalon address +12
// make reset
initial begin
bus_read_data = 32'b0;
counter = 32'b0;
clk = 1'b0;
rst = 1'b0;
#50
rst = 1'b1;
#100
rst = 1'b0;
end
// make clock
always begin
#10
clk = !clk;
end
always @(posedge clk) begin
// fake bus acjs
bus_ack <= bus_write | bus_read;
end
always @(posedge bus_read) begin
// fake bus reads
if (bus_addr == audio_fifo_address) begin
bus_read_data <= (8'd3 << 24) | 8'd2; // allow reads and writes
end
else if ((bus_addr == audio_right_address)) begin
counter <= counter + 1;
bus_read_data <= counter;
end
end
EBABWrapper ebab_wrapper
(
// Outputs
.bus_byte_enable(bus_byte_enable),
.bus_read(bus_read),
.bus_write(bus_write),
.bus_write_data(bus_write_data),
.bus_addr(bus_addr),
// Inputs
.clk(clk),
.rst(rst),
.bus_ack(bus_ack),
.bus_read_data(bus_read_data)
);
endmodule |
module delta_rom (clock, address, delta_out);
input clock;
input [9:0] address;
output [31:0] delta_out;
reg [31:0] delta_out;
always@(posedge clock)
begin
case(address)
10'd0: delta_out = 32'b00010000000000000000000000000000;
10'd1: delta_out = 32'b00010000001000000000000000000000;
10'd2: delta_out = 32'b00010000010000000000000000000000;
10'd3: delta_out = 32'b00010000011000000000000000000000;
10'd4: delta_out = 32'b00010000100000000000000000000000;
10'd5: delta_out = 32'b00010000101000000000000000000000;
10'd6: delta_out = 32'b00010000110000000000000000000000;
10'd7: delta_out = 32'b00010000111000000000000000000000;
10'd8: delta_out = 32'b00010001000000000000000000000000;
10'd9: delta_out = 32'b00010001001000000000000000000000;
10'd10: delta_out = 32'b00010001010000000000000000000000;
10'd11: delta_out = 32'b00010001011000000000000000000000;
10'd12: delta_out = 32'b00010001100000000000000000000000;
10'd13: delta_out = 32'b00010001101000000000000000000000;
10'd14: delta_out = 32'b00010001110000000000000000000000;
10'd15: delta_out = 32'b00010001111000000000000000000000;
10'd16: delta_out = 32'b00010010000000000000000000000000;
10'd17: delta_out = 32'b00010010001000000000000000000000;
10'd18: delta_out = 32'b00010010010000000000000000000000;
10'd19: delta_out = 32'b00010010011000000000000000000000;
10'd20: delta_out = 32'b00010010100000000000000000000000;
10'd21: delta_out = 32'b00010010101000000000000000000000;
10'd22: delta_out = 32'b00010010110000000000000000000000;
10'd23: delta_out = 32'b00010010111000000000000000000000;
10'd24: delta_out = 32'b00010011000000000000000000000000;
10'd25: delta_out = 32'b00010011001000000000000000000000;
10'd26: delta_out = 32'b00010011010000000000000000000000;
10'd27: delta_out = 32'b00010011011000000000000000000000;
10'd28: delta_out = 32'b00010011100000000000000000000000;
10'd29: delta_out = 32'b00010011101000000000000000000000;
10'd30: delta_out = 32'b00010011110000000000000000000000;
10'd31: delta_out = 32'b00010011111000000000000000000000;
10'd32: delta_out = 32'b00010100000000000000000000000000;
10'd33: delta_out = 32'b00010100001000000000000000000000;
10'd34: delta_out = 32'b00010100010000000000000000000000;
10'd35: delta_out = 32'b00010100011000000000000000000000;
10'd36: delta_out = 32'b00010100100000000000000000000000;
10'd37: delta_out = 32'b00010100101000000000000000000000;
10'd38: delta_out = 32'b00010100110000000000000000000000;
10'd39: delta_out = 32'b00010100111000000000000000000000;
10'd40: delta_out = 32'b00010101000000000000000000000000;
10'd41: delta_out = 32'b00010101001000000000000000000000;
10'd42: delta_out = 32'b00010101010000000000000000000000;
10'd43: delta_out = 32'b00010101011000000000000000000000;
10'd44: delta_out = 32'b00010101100000000000000000000000;
10'd45: delta_out = 32'b00010101101000000000000000000000;
10'd46: delta_out = 32'b00010101110000000000000000000000;
10'd47: delta_out = 32'b00010101111000000000000000000000;
10'd48: delta_out = 32'b00010110000000000000000000000000;
10'd49: delta_out = 32'b00010110001000000000000000000000;
10'd50: delta_out = 32'b00010110010000000000000000000000;
10'd51: delta_out = 32'b00010110011000000000000000000000;
10'd52: delta_out = 32'b00010110100000000000000000000000;
10'd53: delta_out = 32'b00010110101000000000000000000000;
10'd54: delta_out = 32'b00010110110000000000000000000000;
10'd55: delta_out = 32'b00010110111000000000000000000000;
10'd56: delta_out = 32'b00010111000000000000000000000000;
10'd57: delta_out = 32'b00010111001000000000000000000000;
10'd58: delta_out = 32'b00010111010000000000000000000000;
10'd59: delta_out = 32'b00010111011000000000000000000000;
10'd60: delta_out = 32'b00010111100000000000000000000000;
10'd61: delta_out = 32'b00010111101000000000000000000000;
10'd62: delta_out = 32'b00010111110000000000000000000000;
10'd63: delta_out = 32'b00010111111000000000000000000000;
10'd64: delta_out = 32'b00011000000000000000000000000000;
10'd65: delta_out = 32'b00011000001000000000000000000000;
10'd66: delta_out = 32'b00011000010000000000000000000000;
10'd67: delta_out = 32'b00011000011000000000000000000000;
10'd68: delta_out = 32'b00011000100000000000000000000000;
10'd69: delta_out = 32'b00011000101000000000000000000000;
10'd70: delta_out = 32'b00011000110000000000000000000000;
10'd71: delta_out = 32'b00011000111000000000000000000000;
10'd72: delta_out = 32'b00011001000000000000000000000000;
10'd73: delta_out = 32'b00011001001000000000000000000000;
10'd74: delta_out = 32'b00011001010000000000000000000000;
10'd75: delta_out = 32'b00011001011000000000000000000000;
10'd76: delta_out = 32'b00011001100000000000000000000000;
10'd77: delta_out = 32'b00011001101000000000000000000000;
10'd78: delta_out = 32'b00011001110000000000000000000000;
10'd79: delta_out = 32'b00011001111000000000000000000000;
10'd80: delta_out = 32'b00011010000000000000000000000000;
10'd81: delta_out = 32'b00011010001000000000000000000000;
10'd82: delta_out = 32'b00011010010000000000000000000000;
10'd83: delta_out = 32'b00011010011000000000000000000000;
10'd84: delta_out = 32'b00011010100000000000000000000000;
10'd85: delta_out = 32'b00011010101000000000000000000000;
10'd86: delta_out = 32'b00011010110000000000000000000000;
10'd87: delta_out = 32'b00011010111000000000000000000000;
10'd88: delta_out = 32'b00011011000000000000000000000000;
10'd89: delta_out = 32'b00011011001000000000000000000000;
10'd90: delta_out = 32'b00011011010000000000000000000000;
10'd91: delta_out = 32'b00011011011000000000000000000000;
10'd92: delta_out = 32'b00011011100000000000000000000000;
10'd93: delta_out = 32'b00011011101000000000000000000000;
10'd94: delta_out = 32'b00011011110000000000000000000000;
10'd95: delta_out = 32'b00011011111000000000000000000000;
10'd96: delta_out = 32'b00011100000000000000000000000000;
10'd97: delta_out = 32'b00011100001000000000000000000000;
10'd98: delta_out = 32'b00011100010000000000000000000000;
10'd99: delta_out = 32'b00011100011000000000000000000000;
10'd100: delta_out = 32'b00011100100000000000000000000000;
10'd101: delta_out = 32'b00011100101000000000000000000000;
10'd102: delta_out = 32'b00011100110000000000000000000000;
10'd103: delta_out = 32'b00011100111000000000000000000000;
10'd104: delta_out = 32'b00011101000000000000000000000000;
10'd105: delta_out = 32'b00011101001000000000000000000000;
10'd106: delta_out = 32'b00011101010000000000000000000000;
10'd107: delta_out = 32'b00011101011000000000000000000000;
10'd108: delta_out = 32'b00011101100000000000000000000000;
10'd109: delta_out = 32'b00011101101000000000000000000000;
10'd110: delta_out = 32'b00011101110000000000000000000000;
10'd111: delta_out = 32'b00011101111000000000000000000000;
10'd112: delta_out = 32'b00011110000000000000000000000000;
10'd113: delta_out = 32'b00011110001000000000000000000000;
10'd114: delta_out = 32'b00011110010000000000000000000000;
10'd115: delta_out = 32'b00011110011000000000000000000000;
10'd116: delta_out = 32'b00011110100000000000000000000000;
10'd117: delta_out = 32'b00011110101000000000000000000000;
10'd118: delta_out = 32'b00011110110000000000000000000000;
10'd119: delta_out = 32'b00011110111000000000000000000000;
10'd120: delta_out = 32'b00011111000000000000000000000000;
10'd121: delta_out = 32'b00011111001000000000000000000000;
10'd122: delta_out = 32'b00011111010000000000000000000000;
10'd123: delta_out = 32'b00011111011000000000000000000000;
10'd124: delta_out = 32'b00011111100000000000000000000000;
10'd125: delta_out = 32'b00011111101000000000000000000000;
10'd126: delta_out = 32'b00011111110000000000000000000000;
10'd127: delta_out = 32'b00011111111000000000000000000000;
10'd128: delta_out = 32'b00100000000000000000000000000000;
10'd129: delta_out = 32'b00100000001000000000000000000000;
10'd130: delta_out = 32'b00100000010000000000000000000000;
10'd131: delta_out = 32'b00100000011000000000000000000000;
10'd132: delta_out = 32'b00100000100000000000000000000000;
10'd133: delta_out = 32'b00100000101000000000000000000000;
10'd134: delta_out = 32'b00100000110000000000000000000000;
10'd135: delta_out = 32'b00100000111000000000000000000000;
10'd136: delta_out = 32'b00100001000000000000000000000000;
10'd137: delta_out = 32'b00100001001000000000000000000000;
10'd138: delta_out = 32'b00100001010000000000000000000000;
10'd139: delta_out = 32'b00100001011000000000000000000000;
10'd140: delta_out = 32'b00100001100000000000000000000000;
10'd141: delta_out = 32'b00100001101000000000000000000000;
10'd142: delta_out = 32'b00100001110000000000000000000000;
10'd143: delta_out = 32'b00100001111000000000000000000000;
10'd144: delta_out = 32'b00100010000000000000000000000000;
10'd145: delta_out = 32'b00100010001000000000000000000000;
10'd146: delta_out = 32'b00100010010000000000000000000000;
10'd147: delta_out = 32'b00100010011000000000000000000000;
10'd148: delta_out = 32'b00100010100000000000000000000000;
10'd149: delta_out = 32'b00100010101000000000000000000000;
10'd150: delta_out = 32'b00100010110000000000000000000000;
10'd151: delta_out = 32'b00100010111000000000000000000000;
10'd152: delta_out = 32'b00100011000000000000000000000000;
10'd153: delta_out = 32'b00100011001000000000000000000000;
10'd154: delta_out = 32'b00100011010000000000000000000000;
10'd155: delta_out = 32'b00100011011000000000000000000000;
10'd156: delta_out = 32'b00100011100000000000000000000000;
10'd157: delta_out = 32'b00100011101000000000000000000000;
10'd158: delta_out = 32'b00100011110000000000000000000000;
10'd159: delta_out = 32'b00100011111000000000000000000000;
10'd160: delta_out = 32'b00100100000000000000000000000000;
10'd161: delta_out = 32'b00100100001000000000000000000000;
10'd162: delta_out = 32'b00100100010000000000000000000000;
10'd163: delta_out = 32'b00100100011000000000000000000000;
10'd164: delta_out = 32'b00100100100000000000000000000000;
10'd165: delta_out = 32'b00100100101000000000000000000000;
10'd166: delta_out = 32'b00100100110000000000000000000000;
10'd167: delta_out = 32'b00100100111000000000000000000000;
10'd168: delta_out = 32'b00100101000000000000000000000000;
10'd169: delta_out = 32'b00100101001000000000000000000000;
10'd170: delta_out = 32'b00100101010000000000000000000000;
10'd171: delta_out = 32'b00100101011000000000000000000000;
10'd172: delta_out = 32'b00100101100000000000000000000000;
10'd173: delta_out = 32'b00100101101000000000000000000000;
10'd174: delta_out = 32'b00100101110000000000000000000000;
10'd175: delta_out = 32'b00100101111000000000000000000000;
10'd176: delta_out = 32'b00100110000000000000000000000000;
10'd177: delta_out = 32'b00100110001000000000000000000000;
10'd178: delta_out = 32'b00100110010000000000000000000000;
10'd179: delta_out = 32'b00100110011000000000000000000000;
10'd180: delta_out = 32'b00100110100000000000000000000000;
10'd181: delta_out = 32'b00100110101000000000000000000000;
10'd182: delta_out = 32'b00100110110000000000000000000000;
10'd183: delta_out = 32'b00100110111000000000000000000000;
10'd184: delta_out = 32'b00100111000000000000000000000000;
10'd185: delta_out = 32'b00100111001000000000000000000000;
10'd186: delta_out = 32'b00100111010000000000000000000000;
10'd187: delta_out = 32'b00100111011000000000000000000000;
10'd188: delta_out = 32'b00100111100000000000000000000000;
10'd189: delta_out = 32'b00100111101000000000000000000000;
10'd190: delta_out = 32'b00100111110000000000000000000000;
10'd191: delta_out = 32'b00100111111000000000000000000000;
10'd192: delta_out = 32'b00101000000000000000000000000000;
10'd193: delta_out = 32'b00101000001000000000000000000000;
10'd194: delta_out = 32'b00101000010000000000000000000000;
10'd195: delta_out = 32'b00101000011000000000000000000000;
10'd196: delta_out = 32'b00101000100000000000000000000000;
10'd197: delta_out = 32'b00101000101000000000000000000000;
10'd198: delta_out = 32'b00101000110000000000000000000000;
10'd199: delta_out = 32'b00101000111000000000000000000000;
10'd200: delta_out = 32'b00101001000000000000000000000000;
10'd201: delta_out = 32'b00101001001000000000000000000000;
10'd202: delta_out = 32'b00101001010000000000000000000000;
10'd203: delta_out = 32'b00101001011000000000000000000000;
10'd204: delta_out = 32'b00101001100000000000000000000000;
10'd205: delta_out = 32'b00101001101000000000000000000000;
10'd206: delta_out = 32'b00101001110000000000000000000000;
10'd207: delta_out = 32'b00101001111000000000000000000000;
10'd208: delta_out = 32'b00101010000000000000000000000000;
10'd209: delta_out = 32'b00101010001000000000000000000000;
10'd210: delta_out = 32'b00101010010000000000000000000000;
10'd211: delta_out = 32'b00101010011000000000000000000000;
10'd212: delta_out = 32'b00101010100000000000000000000000;
10'd213: delta_out = 32'b00101010101000000000000000000000;
10'd214: delta_out = 32'b00101010110000000000000000000000;
10'd215: delta_out = 32'b00101010111000000000000000000000;
10'd216: delta_out = 32'b00101011000000000000000000000000;
10'd217: delta_out = 32'b00101011001000000000000000000000;
10'd218: delta_out = 32'b00101011010000000000000000000000;
10'd219: delta_out = 32'b00101011011000000000000000000000;
10'd220: delta_out = 32'b00101011100000000000000000000000;
10'd221: delta_out = 32'b00101011101000000000000000000000;
10'd222: delta_out = 32'b00101011110000000000000000000000;
10'd223: delta_out = 32'b00101011111000000000000000000000;
10'd224: delta_out = 32'b00101100000000000000000000000000;
10'd225: delta_out = 32'b00101100001000000000000000000000;
10'd226: delta_out = 32'b00101100010000000000000000000000;
10'd227: delta_out = 32'b00101100011000000000000000000000;
10'd228: delta_out = 32'b00101100100000000000000000000000;
10'd229: delta_out = 32'b00101100101000000000000000000000;
10'd230: delta_out = 32'b00101100110000000000000000000000;
10'd231: delta_out = 32'b00101100111000000000000000000000;
10'd232: delta_out = 32'b00101101000000000000000000000000;
10'd233: delta_out = 32'b00101101001000000000000000000000;
10'd234: delta_out = 32'b00101101010000000000000000000000;
10'd235: delta_out = 32'b00101101011000000000000000000000;
10'd236: delta_out = 32'b00101101100000000000000000000000;
10'd237: delta_out = 32'b00101101101000000000000000000000;
10'd238: delta_out = 32'b00101101110000000000000000000000;
10'd239: delta_out = 32'b00101101111000000000000000000000;
10'd240: delta_out = 32'b00101110000000000000000000000000;
10'd241: delta_out = 32'b00101110001000000000000000000000;
10'd242: delta_out = 32'b00101110010000000000000000000000;
10'd243: delta_out = 32'b00101110011000000000000000000000;
10'd244: delta_out = 32'b00101110100000000000000000000000;
10'd245: delta_out = 32'b00101110101000000000000000000000;
10'd246: delta_out = 32'b00101110110000000000000000000000;
10'd247: delta_out = 32'b00101110111000000000000000000000;
10'd248: delta_out = 32'b00101111000000000000000000000000;
10'd249: delta_out = 32'b00101111001000000000000000000000;
10'd250: delta_out = 32'b00101111010000000000000000000000;
10'd251: delta_out = 32'b00101111011000000000000000000000;
10'd252: delta_out = 32'b00101111100000000000000000000000;
10'd253: delta_out = 32'b00101111101000000000000000000000;
10'd254: delta_out = 32'b00101111110000000000000000000000;
10'd255: delta_out = 32'b00101111111000000000000000000000;
10'd256: delta_out = 32'b00110000000000000000000000000000;
10'd257: delta_out = 32'b00101111111000000000000000000000;
10'd258: delta_out = 32'b00101111110000000000000000000000;
10'd259: delta_out = 32'b00101111101000000000000000000000;
10'd260: delta_out = 32'b00101111100000000000000000000000;
10'd261: delta_out = 32'b00101111011000000000000000000000;
10'd262: delta_out = 32'b00101111010000000000000000000000;
10'd263: delta_out = 32'b00101111001000000000000000000000;
10'd264: delta_out = 32'b00101111000000000000000000000000;
10'd265: delta_out = 32'b00101110111000000000000000000000;
10'd266: delta_out = 32'b00101110110000000000000000000000;
10'd267: delta_out = 32'b00101110101000000000000000000000;
10'd268: delta_out = 32'b00101110100000000000000000000000;
10'd269: delta_out = 32'b00101110011000000000000000000000;
10'd270: delta_out = 32'b00101110010000000000000000000000;
10'd271: delta_out = 32'b00101110001000000000000000000000;
10'd272: delta_out = 32'b00101110000000000000000000000000;
10'd273: delta_out = 32'b00101101111000000000000000000000;
10'd274: delta_out = 32'b00101101110000000000000000000000;
10'd275: delta_out = 32'b00101101101000000000000000000000;
10'd276: delta_out = 32'b00101101100000000000000000000000;
10'd277: delta_out = 32'b00101101011000000000000000000000;
10'd278: delta_out = 32'b00101101010000000000000000000000;
10'd279: delta_out = 32'b00101101001000000000000000000000;
10'd280: delta_out = 32'b00101101000000000000000000000000;
10'd281: delta_out = 32'b00101100111000000000000000000000;
10'd282: delta_out = 32'b00101100110000000000000000000000;
10'd283: delta_out = 32'b00101100101000000000000000000000;
10'd284: delta_out = 32'b00101100100000000000000000000000;
10'd285: delta_out = 32'b00101100011000000000000000000000;
10'd286: delta_out = 32'b00101100010000000000000000000000;
10'd287: delta_out = 32'b00101100001000000000000000000000;
10'd288: delta_out = 32'b00101100000000000000000000000000;
10'd289: delta_out = 32'b00101011111000000000000000000000;
10'd290: delta_out = 32'b00101011110000000000000000000000;
10'd291: delta_out = 32'b00101011101000000000000000000000;
10'd292: delta_out = 32'b00101011100000000000000000000000;
10'd293: delta_out = 32'b00101011011000000000000000000000;
10'd294: delta_out = 32'b00101011010000000000000000000000;
10'd295: delta_out = 32'b00101011001000000000000000000000;
10'd296: delta_out = 32'b00101011000000000000000000000000;
10'd297: delta_out = 32'b00101010111000000000000000000000;
10'd298: delta_out = 32'b00101010110000000000000000000000;
10'd299: delta_out = 32'b00101010101000000000000000000000;
10'd300: delta_out = 32'b00101010100000000000000000000000;
10'd301: delta_out = 32'b00101010011000000000000000000000;
10'd302: delta_out = 32'b00101010010000000000000000000000;
10'd303: delta_out = 32'b00101010001000000000000000000000;
10'd304: delta_out = 32'b00101010000000000000000000000000;
10'd305: delta_out = 32'b00101001111000000000000000000000;
10'd306: delta_out = 32'b00101001110000000000000000000000;
10'd307: delta_out = 32'b00101001101000000000000000000000;
10'd308: delta_out = 32'b00101001100000000000000000000000;
10'd309: delta_out = 32'b00101001011000000000000000000000;
10'd310: delta_out = 32'b00101001010000000000000000000000;
10'd311: delta_out = 32'b00101001001000000000000000000000;
10'd312: delta_out = 32'b00101001000000000000000000000000;
10'd313: delta_out = 32'b00101000111000000000000000000000;
10'd314: delta_out = 32'b00101000110000000000000000000000;
10'd315: delta_out = 32'b00101000101000000000000000000000;
10'd316: delta_out = 32'b00101000100000000000000000000000;
10'd317: delta_out = 32'b00101000011000000000000000000000;
10'd318: delta_out = 32'b00101000010000000000000000000000;
10'd319: delta_out = 32'b00101000001000000000000000000000;
10'd320: delta_out = 32'b00101000000000000000000000000000;
10'd321: delta_out = 32'b00100111111000000000000000000000;
10'd322: delta_out = 32'b00100111110000000000000000000000;
10'd323: delta_out = 32'b00100111101000000000000000000000;
10'd324: delta_out = 32'b00100111100000000000000000000000;
10'd325: delta_out = 32'b00100111011000000000000000000000;
10'd326: delta_out = 32'b00100111010000000000000000000000;
10'd327: delta_out = 32'b00100111001000000000000000000000;
10'd328: delta_out = 32'b00100111000000000000000000000000;
10'd329: delta_out = 32'b00100110111000000000000000000000;
10'd330: delta_out = 32'b00100110110000000000000000000000;
10'd331: delta_out = 32'b00100110101000000000000000000000;
10'd332: delta_out = 32'b00100110100000000000000000000000;
10'd333: delta_out = 32'b00100110011000000000000000000000;
10'd334: delta_out = 32'b00100110010000000000000000000000;
10'd335: delta_out = 32'b00100110001000000000000000000000;
10'd336: delta_out = 32'b00100110000000000000000000000000;
10'd337: delta_out = 32'b00100101111000000000000000000000;
10'd338: delta_out = 32'b00100101110000000000000000000000;
10'd339: delta_out = 32'b00100101101000000000000000000000;
10'd340: delta_out = 32'b00100101100000000000000000000000;
10'd341: delta_out = 32'b00100101011000000000000000000000;
10'd342: delta_out = 32'b00100101010000000000000000000000;
10'd343: delta_out = 32'b00100101001000000000000000000000;
10'd344: delta_out = 32'b00100101000000000000000000000000;
10'd345: delta_out = 32'b00100100111000000000000000000000;
10'd346: delta_out = 32'b00100100110000000000000000000000;
10'd347: delta_out = 32'b00100100101000000000000000000000;
10'd348: delta_out = 32'b00100100100000000000000000000000;
10'd349: delta_out = 32'b00100100011000000000000000000000;
10'd350: delta_out = 32'b00100100010000000000000000000000;
10'd351: delta_out = 32'b00100100001000000000000000000000;
10'd352: delta_out = 32'b00100100000000000000000000000000;
10'd353: delta_out = 32'b00100011111000000000000000000000;
10'd354: delta_out = 32'b00100011110000000000000000000000;
10'd355: delta_out = 32'b00100011101000000000000000000000;
10'd356: delta_out = 32'b00100011100000000000000000000000;
10'd357: delta_out = 32'b00100011011000000000000000000000;
10'd358: delta_out = 32'b00100011010000000000000000000000;
10'd359: delta_out = 32'b00100011001000000000000000000000;
10'd360: delta_out = 32'b00100011000000000000000000000000;
10'd361: delta_out = 32'b00100010111000000000000000000000;
10'd362: delta_out = 32'b00100010110000000000000000000000;
10'd363: delta_out = 32'b00100010101000000000000000000000;
10'd364: delta_out = 32'b00100010100000000000000000000000;
10'd365: delta_out = 32'b00100010011000000000000000000000;
10'd366: delta_out = 32'b00100010010000000000000000000000;
10'd367: delta_out = 32'b00100010001000000000000000000000;
10'd368: delta_out = 32'b00100010000000000000000000000000;
10'd369: delta_out = 32'b00100001111000000000000000000000;
10'd370: delta_out = 32'b00100001110000000000000000000000;
10'd371: delta_out = 32'b00100001101000000000000000000000;
10'd372: delta_out = 32'b00100001100000000000000000000000;
10'd373: delta_out = 32'b00100001011000000000000000000000;
10'd374: delta_out = 32'b00100001010000000000000000000000;
10'd375: delta_out = 32'b00100001001000000000000000000000;
10'd376: delta_out = 32'b00100001000000000000000000000000;
10'd377: delta_out = 32'b00100000111000000000000000000000;
10'd378: delta_out = 32'b00100000110000000000000000000000;
10'd379: delta_out = 32'b00100000101000000000000000000000;
10'd380: delta_out = 32'b00100000100000000000000000000000;
10'd381: delta_out = 32'b00100000011000000000000000000000;
10'd382: delta_out = 32'b00100000010000000000000000000000;
10'd383: delta_out = 32'b00100000001000000000000000000000;
10'd384: delta_out = 32'b00100000000000000000000000000000;
10'd385: delta_out = 32'b00011111111000000000000000000000;
10'd386: delta_out = 32'b00011111110000000000000000000000;
10'd387: delta_out = 32'b00011111101000000000000000000000;
10'd388: delta_out = 32'b00011111100000000000000000000000;
10'd389: delta_out = 32'b00011111011000000000000000000000;
10'd390: delta_out = 32'b00011111010000000000000000000000;
10'd391: delta_out = 32'b00011111001000000000000000000000;
10'd392: delta_out = 32'b00011111000000000000000000000000;
10'd393: delta_out = 32'b00011110111000000000000000000000;
10'd394: delta_out = 32'b00011110110000000000000000000000;
10'd395: delta_out = 32'b00011110101000000000000000000000;
10'd396: delta_out = 32'b00011110100000000000000000000000;
10'd397: delta_out = 32'b00011110011000000000000000000000;
10'd398: delta_out = 32'b00011110010000000000000000000000;
10'd399: delta_out = 32'b00011110001000000000000000000000;
10'd400: delta_out = 32'b00011110000000000000000000000000;
10'd401: delta_out = 32'b00011101111000000000000000000000;
10'd402: delta_out = 32'b00011101110000000000000000000000;
10'd403: delta_out = 32'b00011101101000000000000000000000;
10'd404: delta_out = 32'b00011101100000000000000000000000;
10'd405: delta_out = 32'b00011101011000000000000000000000;
10'd406: delta_out = 32'b00011101010000000000000000000000;
10'd407: delta_out = 32'b00011101001000000000000000000000;
10'd408: delta_out = 32'b00011101000000000000000000000000;
10'd409: delta_out = 32'b00011100111000000000000000000000;
10'd410: delta_out = 32'b00011100110000000000000000000000;
10'd411: delta_out = 32'b00011100101000000000000000000000;
10'd412: delta_out = 32'b00011100100000000000000000000000;
10'd413: delta_out = 32'b00011100011000000000000000000000;
10'd414: delta_out = 32'b00011100010000000000000000000000;
10'd415: delta_out = 32'b00011100001000000000000000000000;
10'd416: delta_out = 32'b00011100000000000000000000000000;
10'd417: delta_out = 32'b00011011111000000000000000000000;
10'd418: delta_out = 32'b00011011110000000000000000000000;
10'd419: delta_out = 32'b00011011101000000000000000000000;
10'd420: delta_out = 32'b00011011100000000000000000000000;
10'd421: delta_out = 32'b00011011011000000000000000000000;
10'd422: delta_out = 32'b00011011010000000000000000000000;
10'd423: delta_out = 32'b00011011001000000000000000000000;
10'd424: delta_out = 32'b00011011000000000000000000000000;
10'd425: delta_out = 32'b00011010111000000000000000000000;
10'd426: delta_out = 32'b00011010110000000000000000000000;
10'd427: delta_out = 32'b00011010101000000000000000000000;
10'd428: delta_out = 32'b00011010100000000000000000000000;
10'd429: delta_out = 32'b00011010011000000000000000000000;
10'd430: delta_out = 32'b00011010010000000000000000000000;
10'd431: delta_out = 32'b00011010001000000000000000000000;
10'd432: delta_out = 32'b00011010000000000000000000000000;
10'd433: delta_out = 32'b00011001111000000000000000000000;
10'd434: delta_out = 32'b00011001110000000000000000000000;
10'd435: delta_out = 32'b00011001101000000000000000000000;
10'd436: delta_out = 32'b00011001100000000000000000000000;
10'd437: delta_out = 32'b00011001011000000000000000000000;
10'd438: delta_out = 32'b00011001010000000000000000000000;
10'd439: delta_out = 32'b00011001001000000000000000000000;
10'd440: delta_out = 32'b00011001000000000000000000000000;
10'd441: delta_out = 32'b00011000111000000000000000000000;
10'd442: delta_out = 32'b00011000110000000000000000000000;
10'd443: delta_out = 32'b00011000101000000000000000000000;
10'd444: delta_out = 32'b00011000100000000000000000000000;
10'd445: delta_out = 32'b00011000011000000000000000000000;
10'd446: delta_out = 32'b00011000010000000000000000000000;
10'd447: delta_out = 32'b00011000001000000000000000000000;
10'd448: delta_out = 32'b00011000000000000000000000000000;
10'd449: delta_out = 32'b00010111111000000000000000000000;
10'd450: delta_out = 32'b00010111110000000000000000000000;
10'd451: delta_out = 32'b00010111101000000000000000000000;
10'd452: delta_out = 32'b00010111100000000000000000000000;
10'd453: delta_out = 32'b00010111011000000000000000000000;
10'd454: delta_out = 32'b00010111010000000000000000000000;
10'd455: delta_out = 32'b00010111001000000000000000000000;
10'd456: delta_out = 32'b00010111000000000000000000000000;
10'd457: delta_out = 32'b00010110111000000000000000000000;
10'd458: delta_out = 32'b00010110110000000000000000000000;
10'd459: delta_out = 32'b00010110101000000000000000000000;
10'd460: delta_out = 32'b00010110100000000000000000000000;
10'd461: delta_out = 32'b00010110011000000000000000000000;
10'd462: delta_out = 32'b00010110010000000000000000000000;
10'd463: delta_out = 32'b00010110001000000000000000000000;
10'd464: delta_out = 32'b00010110000000000000000000000000;
10'd465: delta_out = 32'b00010101111000000000000000000000;
10'd466: delta_out = 32'b00010101110000000000000000000000;
10'd467: delta_out = 32'b00010101101000000000000000000000;
10'd468: delta_out = 32'b00010101100000000000000000000000;
10'd469: delta_out = 32'b00010101011000000000000000000000;
10'd470: delta_out = 32'b00010101010000000000000000000000;
10'd471: delta_out = 32'b00010101001000000000000000000000;
10'd472: delta_out = 32'b00010101000000000000000000000000;
10'd473: delta_out = 32'b00010100111000000000000000000000;
10'd474: delta_out = 32'b00010100110000000000000000000000;
10'd475: delta_out = 32'b00010100101000000000000000000000;
10'd476: delta_out = 32'b00010100100000000000000000000000;
10'd477: delta_out = 32'b00010100011000000000000000000000;
10'd478: delta_out = 32'b00010100010000000000000000000000;
10'd479: delta_out = 32'b00010100001000000000000000000000;
10'd480: delta_out = 32'b00010100000000000000000000000000;
10'd481: delta_out = 32'b00010011111000000000000000000000;
10'd482: delta_out = 32'b00010011110000000000000000000000;
10'd483: delta_out = 32'b00010011101000000000000000000000;
10'd484: delta_out = 32'b00010011100000000000000000000000;
10'd485: delta_out = 32'b00010011011000000000000000000000;
10'd486: delta_out = 32'b00010011010000000000000000000000;
10'd487: delta_out = 32'b00010011001000000000000000000000;
10'd488: delta_out = 32'b00010011000000000000000000000000;
10'd489: delta_out = 32'b00010010111000000000000000000000;
10'd490: delta_out = 32'b00010010110000000000000000000000;
10'd491: delta_out = 32'b00010010101000000000000000000000;
10'd492: delta_out = 32'b00010010100000000000000000000000;
10'd493: delta_out = 32'b00010010011000000000000000000000;
10'd494: delta_out = 32'b00010010010000000000000000000000;
10'd495: delta_out = 32'b00010010001000000000000000000000;
10'd496: delta_out = 32'b00010010000000000000000000000000;
10'd497: delta_out = 32'b00010001111000000000000000000000;
10'd498: delta_out = 32'b00010001110000000000000000000000;
10'd499: delta_out = 32'b00010001101000000000000000000000;
10'd500: delta_out = 32'b00010001100000000000000000000000;
10'd501: delta_out = 32'b00010001011000000000000000000000;
10'd502: delta_out = 32'b00010001010000000000000000000000;
10'd503: delta_out = 32'b00010001001000000000000000000000;
10'd504: delta_out = 32'b00010001000000000000000000000000;
10'd505: delta_out = 32'b00010000111000000000000000000000;
10'd506: delta_out = 32'b00010000110000000000000000000000;
10'd507: delta_out = 32'b00010000101000000000000000000000;
10'd508: delta_out = 32'b00010000100000000000000000000000;
10'd509: delta_out = 32'b00010000011000000000000000000000;
10'd510: delta_out = 32'b00010000010000000000000000000000;
10'd511: delta_out = 32'b00010000001000000000000000000000;
10'd512: delta_out = 32'b00010000000000000000000000000000;
10'd513: delta_out = 32'b00001111111000000000000000000000;
endcase
end
endmodule |
module IIR6_32bit_fixed (audio_out, audio_in,
scale,
b1, b2, b3, b4, b5, b6, b7,
a2, a3, a4, a5, a6, a7,
clk, data_val, rst, audio_out_val);
// The filter is a "Direct Form II Transposed"
//
// a(1)*y(n) = b(1)*x(n) + b(2)*x(n-1) + ... + b(nb+1)*x(n-nb)
// - a(2)*y(n-1) - ... - a(na+1)*y(n-na)
//
// If a(1) is not equal to 1, FILTER normalizes the filter
// coefficients by a(1).
//
// one audio sample, 16 bit, 2's complement
output reg signed [31:0] audio_out;
output reg signed audio_out_val;
// one audio sample, 16 bit, 2's complement
input wire signed [31:0] audio_in;
// shift factor for output
input wire [2:0] scale;
// filter coefficients
input wire signed [31:0] b1, b2, b3, b4, b5, b6, b7, a2, a3, a4, a5, a6, a7;
input wire clk, data_val, rst;
/// filter vars
wire signed [31:0] f1_mac_new, f1_coeff_x_value;
reg signed [31:0] f1_coeff, f1_mac_old, f1_value;
// input to filter
reg signed [31:0] x_n;
// input history x(n-1), x(n-2)
reg signed [31:0] x_n1, x_n2, x_n3, x_n4, x_n5, x_n6;
// output history: y_n is the new filter output, BUT it is
// immediately stored in f1_y_n1 for the next loop through
// the filter state machine
reg signed [31:0] f1_y_n1, f1_y_n2, f1_y_n3, f1_y_n4, f1_y_n5, f1_y_n6;
// MAC operation
signed_mult f1_c_x_v (.out(f1_coeff_x_value), .a(f1_coeff), .b(f1_value));
assign f1_mac_new = f1_mac_old + f1_coeff_x_value;
// state variable
reg [3:0] state;
///////////////////////////////////////////////////////////////////
//Run the filter state machine FAST so that it completes in one
//audio cycle
always @ (posedge clk)
begin
if (rst) begin
state <= 4'd15; //turn off the state machine
f1_value <= 0;
f1_coeff <= 0;
f1_mac_old <= 0;
x_n <= 0;
x_n1 <= 0;
x_n2 <= 0;
x_n3 <= 0;
x_n4 <= 0;
x_n5 <= 0;
x_n6 <= 0;
f1_y_n1 <= 0;
f1_y_n2 <= 0;
f1_y_n3 <= 0;
f1_y_n4 <= 0;
f1_y_n5 <= 0;
f1_y_n6 <= 0;
audio_out_val <= 0;
end
else begin
case (state)
1:
begin
// set up b1*x(n)
f1_mac_old <= 32'd0;
f1_coeff <= b1;
f1_value <= (audio_in >>> 1);
//register input
x_n <= (audio_in >>> 1);
// next state
state <= 4'd2;
end
2:
begin
// set up b2*x(n-1)
f1_mac_old <= f1_mac_new;
f1_coeff <= b2;
f1_value <= x_n1;
// next state
state <= 4'd3;
end
3:
begin
// set up b3*x(n-2)
f1_mac_old <= f1_mac_new;
f1_coeff <= b3;
f1_value <= x_n2;
// next state
state <= 4'd4;
end
4:
begin
// set up b4*x(n-3)
f1_mac_old <= f1_mac_new;
f1_coeff <= b4;
f1_value <= x_n3;
// next state
state <= 4'd5;
end
5:
begin
// set up b5*x(n-4)
f1_mac_old <= f1_mac_new;
f1_coeff <= b5;
f1_value <= x_n4;
// next state
state <= 4'd6;
end
6:
begin
// set up b6*x(n-5)
f1_mac_old <= f1_mac_new;
f1_coeff <= b6;
f1_value <= x_n5;
// next state
state <= 4'd7;
end
7:
begin
// set up b7*x(n-6)
f1_mac_old <= f1_mac_new;
f1_coeff <= b7;
f1_value <= x_n6;
// next state
state <= 4'd8;
end
8:
begin
// set up -a2*y(n-1)
f1_mac_old <= f1_mac_new;
f1_coeff <= a2;
f1_value <= f1_y_n1;
//next state
state <= 4'd9;
end
9:
begin
// set up -a3*y(n-2)
f1_mac_old <= f1_mac_new;
f1_coeff <= a3;
f1_value <= f1_y_n2;
//next state
state <= 4'd10;
end
4'd10:
begin
// set up -a4*y(n-3)
f1_mac_old <= f1_mac_new;
f1_coeff <= a4;
f1_value <= f1_y_n3;
//next state
state <= 4'd11;
end
4'd11:
begin
// set up -a5*y(n-4)
f1_mac_old <= f1_mac_new;
f1_coeff <= a5;
f1_value <= f1_y_n4;
//next state
state <= 4'd12;
end
4'd12:
begin
// set up -a6*y(n-5)
f1_mac_old <= f1_mac_new;
f1_coeff <= a6;
f1_value <= f1_y_n5;
//next state
state <= 4'd13;
end
13:
begin
// set up -a7*y(n-6)
f1_mac_old <= f1_mac_new;
f1_coeff <= a7;
f1_value <= f1_y_n6;
//next state
state <= 4'd14;
end
14:
begin
// get the output
// and put it in the LAST output var
// for the next pass thru the state machine
//mult by four because of coeff scaling
// to prevent overflow
f1_y_n1 <= f1_mac_new<<scale;
audio_out <= f1_y_n1;
audio_out_val <= 1'b1;
// update output history
f1_y_n2 <= f1_y_n1;
f1_y_n3 <= f1_y_n2;
f1_y_n4 <= f1_y_n3;
f1_y_n5 <= f1_y_n4;
f1_y_n6 <= f1_y_n5;
// update input history
x_n1 <= x_n;
x_n2 <= x_n1;
x_n3 <= x_n2;
x_n4 <= x_n3;
x_n5 <= x_n4;
x_n6 <= x_n5;
//next state
state <= 4'd15;
end
15:
begin
// wait for data valid signal
audio_out_val <= 1'b0;
if (data_val)
begin
state <= 4'd1;
end
end
default:
begin
// default state is end state
state <= 4'd15;
end
endcase
end
end
endmodule |
module signed_mult (out, a, b);
output [31:0] out;
input signed [31:0] a;
input signed [31:0] b;
wire signed [31:0] out;
wire signed [63:0] mult_out;
assign mult_out = a * b;
//assign out = mult_out[33:17];
assign out = {mult_out[63], mult_out[59:30]};
endmodule |
module cache(clk,
rst,
i_p_addr,
i_p_byte_en,
i_p_writedata,
i_p_read,
i_p_write,
o_p_readdata,
o_p_readdata_valid,
o_p_waitrequest,
o_m_addr,
o_m_byte_en,
o_m_writedata,
o_m_read,
o_m_write,
i_m_readdata,
i_m_readdata_valid,
i_m_waitrequest,
cnt_r,
cnt_w,
cnt_hit_r,
cnt_hit_w,
cnt_wb_r,
cnt_wb_w);
parameter cache_entry = 14;
input wire clk, rst;
input wire [24:0] i_p_addr;
input wire [3:0] i_p_byte_en;
input wire [31:0] i_p_writedata;
input wire i_p_read, i_p_write;
output reg [31:0] o_p_readdata;
output reg o_p_readdata_valid;
output wire o_p_waitrequest;
output reg [25:0] o_m_addr;
output wire [3:0] o_m_byte_en;
output reg [127:0] o_m_writedata;
output reg o_m_read, o_m_write;
input wire [127:0] i_m_readdata;
input wire i_m_readdata_valid;
input wire i_m_waitrequest;
output reg [31:0] cnt_r;
output reg [31:0] cnt_w;
output reg [31:0] cnt_hit_r;
output reg [31:0] cnt_hit_w;
output reg [31:0] cnt_wb_r;
output reg [31:0] cnt_wb_w;
wire [3:0] hit;
wire [3:0] modify;
wire [3:0] miss;
wire [3:0] valid;
wire [127:0] readdata0, readdata1, readdata2, readdata3;
wire [127:0] writedata;
wire write0, write1, write2, write3;
wire [3:0] word_en;
wire [3:0] byte_en;
wire [22:0] addr;
wire [22:0] wb_addr0, wb_addr1, wb_addr2, wb_addr3;
wire [7:0] r_cm_data;
wire [1:0] hit_num;
reg [2:0] state;
reg [127:0] writedata_buf;
reg [24:0] write_addr_buf;
reg [3:0] byte_en_buf;
reg write_buf, read_buf;
reg [3:0] write_set;
reg [3:0] fetch_write;
reg [7:0] w_cm_data;
reg w_cm;
localparam IDLE = 0;
localparam COMP = 1;
localparam HIT = 2;
localparam FETCH1 = 3;
localparam FETCH2 = 4;
localparam FETCH3 = 5;
localparam WB1 = 6;
localparam WB2 = 7;
`ifdef SIM
integer i;
initial begin
for(i = 0; i <=(2**cache_entry-1); i=i+1) begin
ram_hot.mem[i] = 0;
end
end
`endif
simple_ram #(.width(8), .widthad(cache_entry)) ram_hot(clk, addr[cache_entry-1:0], w_cm, w_cm_data, addr[cache_entry-1:0], r_cm_data);
set #(.cache_entry(cache_entry))
set0(.clk(clk),
.rst(rst),
.entry(addr[cache_entry-1:0]),
.o_tag(addr[22:cache_entry]),
.writedata(writedata),
.byte_en(byte_en),
.write(write0),
.word_en(word_en), // 4word r/w change
.readdata(readdata0),
.wb_addr(wb_addr0),
.hit(hit[0]),
.modify(modify[0]),
.miss(miss[0]),
.valid(valid[0]),
.read_miss(read_buf));
set #(.cache_entry(cache_entry))
set1(.clk(clk),
.rst(rst),
.entry(addr[cache_entry-1:0]),
.o_tag(addr[22:cache_entry]),
.writedata(writedata),
.byte_en(byte_en),
.write(write1),
.word_en(word_en), // 4word r/w change
.readdata(readdata1),
.wb_addr(wb_addr1),
.hit(hit[1]),
.modify(modify[1]),
.miss(miss[1]),
.valid(valid[1]),
.read_miss(read_buf));
set #(.cache_entry(cache_entry))
set2(.clk(clk),
.rst(rst),
.entry(addr[cache_entry-1:0]),
.o_tag(addr[22:cache_entry]),
.writedata(writedata),
.byte_en(byte_en),
.write(write2),
.word_en(word_en), // 4word r/w change
.readdata(readdata2),
.wb_addr(wb_addr2),
.hit(hit[2]),
.modify(modify[2]),
.miss(miss[2]),
.valid(valid[2]),
.read_miss(read_buf));
set #(.cache_entry(cache_entry))
set3(.clk(clk),
.rst(rst),
.entry(addr[cache_entry-1:0]),
.o_tag(addr[22:cache_entry]),
.writedata(writedata),
.byte_en(byte_en),
.write(write3),
.word_en(word_en), // 4word r/w change
.readdata(readdata3),
.wb_addr(wb_addr3),
.hit(hit[3]),
.modify(modify[3]),
.miss(miss[3]),
.valid(valid[3]),
.read_miss(read_buf));
assign writedata = (|fetch_write) ? i_m_readdata : writedata_buf; //128bit
assign write0 = (fetch_write[0]) ? i_m_readdata_valid : write_set[0];
assign write1 = (fetch_write[1]) ? i_m_readdata_valid : write_set[1];
assign write2 = (fetch_write[2]) ? i_m_readdata_valid : write_set[2];
assign write3 = (fetch_write[3]) ? i_m_readdata_valid : write_set[3];
assign addr = (o_p_waitrequest) ? write_addr_buf[24:2] : i_p_addr[24:2]; // set module input addr is 23bit
assign byte_en = (|fetch_write) ? 4'b1111 : byte_en_buf;
assign o_p_waitrequest = (state != IDLE);
assign o_m_byte_en = 4'b1111;
assign hit_num = (hit[0]) ? 0 : (hit[1]) ? 1 : (hit[2]) ? 2 : 3;
assign word_en = (|fetch_write) ? 4'b1111 :
(write_addr_buf[1:0] == 2'b00) ? 4'b0001 :
(write_addr_buf[1:0] == 2'b01) ? 4'b0010 :
(write_addr_buf[1:0] == 2'b10) ? 4'b0100 : 4'b1000;
always @(posedge clk) begin
if(rst) begin
o_p_readdata_valid <= 0;
{o_m_read, o_m_write} <= 0;
o_m_addr <= 0;
write_addr_buf <= 0;
byte_en_buf <= 0;
writedata_buf <= 0;
{write_buf, read_buf} <= 0;
write_set <= 0;
fetch_write <= 0;
{cnt_r, cnt_w} <= 0;
{cnt_hit_r, cnt_hit_w} <= 0;
{cnt_wb_r, cnt_wb_w} <= 0;
state <= IDLE;
end
else begin
case (state)
IDLE: begin
write_set <= 0;
o_p_readdata_valid <= 0;
writedata_buf <= {i_p_writedata, i_p_writedata, i_p_writedata, i_p_writedata};
write_addr_buf <= i_p_addr;
byte_en_buf <= i_p_byte_en;
write_buf <= i_p_write;
read_buf <= i_p_read;
if(i_p_read) begin
state <= COMP;
cnt_r <= cnt_r + 1;
end else if(i_p_write) begin
state <= COMP;
cnt_w <= cnt_w + 1;
end
end
COMP: begin
if((|hit) && write_buf) begin
state <= HIT;
write_set <= hit;
cnt_hit_w <= cnt_hit_w + 1;
w_cm_data <= (r_cm_data[1:0] == hit_num) ? {r_cm_data[1:0], r_cm_data[7:2]} :
(r_cm_data[3:2] == hit_num) ? {r_cm_data[3:2], r_cm_data[7:4], r_cm_data[1:0]} :
(r_cm_data[5:4] == hit_num) ? {r_cm_data[5:4], r_cm_data[7:6], r_cm_data[3:0]} : r_cm_data;
w_cm <= 1;
end else if((|hit) && read_buf) begin
case(write_addr_buf[1:0])
2'b00: o_p_readdata <= (hit[0]) ? readdata0[31:0] : (hit[1]) ? readdata1[31:0] : (hit[2]) ? readdata2[31:0] : readdata3[31:0];
2'b01: o_p_readdata <= (hit[0]) ? readdata0[63:32] : (hit[1]) ? readdata1[63:32] : (hit[2]) ? readdata2[63:32] : readdata3[63:32];
2'b10: o_p_readdata <= (hit[0]) ? readdata0[95:64] : (hit[1]) ? readdata1[95:64] : (hit[2]) ? readdata2[95:64] : readdata3[95:64];
2'b11: o_p_readdata <= (hit[0]) ? readdata0[127:96] : (hit[1]) ? readdata1[127:96] : (hit[2]) ? readdata2[127:96] : readdata3[127:96];
endcase
o_p_readdata_valid <= 1;
w_cm_data <= (r_cm_data[1:0] == hit_num) ? {r_cm_data[1:0], r_cm_data[7:2]} :
(r_cm_data[3:2] == hit_num) ? {r_cm_data[3:2], r_cm_data[7:4], r_cm_data[1:0]} :
(r_cm_data[5:4] == hit_num) ? {r_cm_data[5:4], r_cm_data[7:6], r_cm_data[3:0]} : r_cm_data;
w_cm <= 1;
cnt_hit_r <= cnt_hit_r + 1;
state <= IDLE;
end else if(!(&valid) || miss[r_cm_data[1:0]]) begin
state <= FETCH1;
if(!valid[0]) begin
fetch_write <= 4'b0001;
w_cm_data <= 8'b11100100;
w_cm <= 1;
end else if(!valid[1]) begin
fetch_write <= 4'b0010;
w_cm_data <= (r_cm_data[1:0] == 2'b01) ? {r_cm_data[1:0], r_cm_data[7:2]} :
(r_cm_data[3:2] == 2'b01) ? {r_cm_data[3:2], r_cm_data[7:4], r_cm_data[1:0]} :
(r_cm_data[5:4] == 2'b01) ? {r_cm_data[5:4], r_cm_data[7:6], r_cm_data[3:0]} : r_cm_data;
w_cm <= 1;
end else if(!valid[2]) begin
fetch_write <= 4'b0100;
w_cm_data <= (r_cm_data[1:0] == 2'b10) ? {r_cm_data[1:0], r_cm_data[7:2]} :
(r_cm_data[3:2] == 2'b10) ? {r_cm_data[3:2], r_cm_data[7:4], r_cm_data[1:0]} :
(r_cm_data[5:4] == 2'b10) ? {r_cm_data[5:4], r_cm_data[7:6], r_cm_data[3:0]} : r_cm_data;
w_cm <= 1;
end else if(!valid[3]) begin
fetch_write <= 4'b1000;
w_cm_data <= (r_cm_data[1:0] == 2'b11) ? {r_cm_data[1:0], r_cm_data[7:2]} :
(r_cm_data[3:2] == 2'b11) ? {r_cm_data[3:2], r_cm_data[7:4], r_cm_data[1:0]} :
(r_cm_data[5:4] == 2'b11) ? {r_cm_data[5:4], r_cm_data[7:6], r_cm_data[3:0]} : r_cm_data;
w_cm <= 1;
end else if(miss[r_cm_data[1:0]]) begin
if(r_cm_data[1:0] == 2'b00) fetch_write <= 4'b0001;
else if(r_cm_data[1:0] == 2'b01) fetch_write <= 4'b0010;
else if(r_cm_data[1:0] == 2'b10) fetch_write <= 4'b0100;
else if(r_cm_data[1:0] == 2'b11) fetch_write <= 4'b1000;
w_cm_data <= {r_cm_data[1:0], r_cm_data[7:2]};
w_cm <= 1;
end
o_m_addr <= {write_addr_buf[24:2], 3'b000};
o_m_read <= 1;
end else begin
state <= WB1;
if(r_cm_data[1:0] == 2'b00) fetch_write <= 4'b0001;
else if(r_cm_data[1:0] == 2'b01) fetch_write <= 4'b0010;
else if(r_cm_data[1:0] == 2'b10) fetch_write <= 4'b0100;
else if(r_cm_data[1:0] == 2'b11) fetch_write <= 4'b1000;
w_cm_data <= {r_cm_data[1:0], r_cm_data[7:2]};
w_cm <= 1;
if(read_buf) cnt_wb_r <= cnt_wb_r + 1;
else if(write_buf) cnt_wb_w <= cnt_wb_w + 1;
end
end
HIT: begin
w_cm <= 0;
write_set <= 0;
state <= IDLE;
end //1/13
FETCH1: begin
w_cm <= 0;
if(!i_m_waitrequest) begin
o_m_read <= 0;
state <= FETCH2;
end
end
FETCH2: begin
if(i_m_readdata_valid) begin
fetch_write <= 0; //add 3/9
if(write_buf) begin
state <= FETCH3;
write_set <= fetch_write;
end else if(read_buf) begin
state <= IDLE;
o_p_readdata_valid <= 1;
case(write_addr_buf[1:0])
2'b00: o_p_readdata <= i_m_readdata[ 31: 0];
2'b01: o_p_readdata <= i_m_readdata[ 63:32];
2'b10: o_p_readdata <= i_m_readdata[ 95:64];
2'b11: o_p_readdata <= i_m_readdata[127:96];
endcase
end
end
end
FETCH3: begin
state <= IDLE;
write_set <= 0;
end
WB1: begin
w_cm <= 0;
o_m_addr <= (fetch_write[0]) ? {wb_addr0, 3'b000} :
(fetch_write[1]) ? {wb_addr1, 3'b000} :
(fetch_write[2]) ? {wb_addr2, 3'b000} : {wb_addr3, 3'b000};
o_m_writedata <= (fetch_write[0]) ? readdata0 :
(fetch_write[1]) ? readdata1 :
(fetch_write[2]) ? readdata2 : readdata3;
o_m_write <= 1;
state <= WB2;
end
WB2: begin
if(!i_m_waitrequest) begin
o_m_write <= 0;
o_m_addr <= {write_addr_buf[24:2], 3'b000};
o_m_read <= 1;
state <= FETCH1;
end
end
endcase // case (state)
end
end
endmodule // cache |
module set(clk,
rst,
entry,
o_tag,
writedata,
byte_en,
write,
word_en,
readdata,
wb_addr,
hit,
modify,
miss,
valid,
read_miss);
parameter cache_entry = 14;
input wire clk, rst;
input wire [cache_entry-1:0] entry;
input wire [22-cache_entry:0] o_tag;
input wire [127:0] writedata;
input wire [3:0] byte_en;
input wire write;
input wire [3:0] word_en;
input wire read_miss;
output wire [127:0] readdata;
output wire [22:0] wb_addr;
output wire hit, modify, miss, valid;
wire [22-cache_entry:0] i_tag;
wire dirty;
wire [24-cache_entry:0] write_tag_data;
assign hit = valid && (o_tag == i_tag);
assign modify = valid && (o_tag != i_tag) && dirty;
assign miss = !valid || ((o_tag != i_tag) && !dirty);
assign wb_addr = {i_tag, entry};
//write -> [3:0] write, writedata/readdata 32bit -> 128bit
simple_ram #(.width(8), .widthad(cache_entry)) ram11_3(clk, entry, write && word_en[3] && byte_en[3], writedata[127:120], entry, readdata[127:120]);
simple_ram #(.width(8), .widthad(cache_entry)) ram11_2(clk, entry, write && word_en[3] && byte_en[2], writedata[119:112], entry, readdata[119:112]);
simple_ram #(.width(8), .widthad(cache_entry)) ram11_1(clk, entry, write && word_en[3] && byte_en[1], writedata[111:104], entry, readdata[111:104]);
simple_ram #(.width(8), .widthad(cache_entry)) ram11_0(clk, entry, write && word_en[3] && byte_en[0], writedata[103:96], entry, readdata[103:96]);
simple_ram #(.width(8), .widthad(cache_entry)) ram10_3(clk, entry, write && word_en[2] && byte_en[3], writedata[95:88], entry, readdata[95:88]);
simple_ram #(.width(8), .widthad(cache_entry)) ram10_2(clk, entry, write && word_en[2] && byte_en[2], writedata[87:80], entry, readdata[87:80]);
simple_ram #(.width(8), .widthad(cache_entry)) ram10_1(clk, entry, write && word_en[2] && byte_en[1], writedata[79:72], entry, readdata[79:72]);
simple_ram #(.width(8), .widthad(cache_entry)) ram10_0(clk, entry, write && word_en[2] && byte_en[0], writedata[71:64], entry, readdata[71:64]);
simple_ram #(.width(8), .widthad(cache_entry)) ram01_3(clk, entry, write && word_en[1] && byte_en[3], writedata[63:56], entry, readdata[63:56]);
simple_ram #(.width(8), .widthad(cache_entry)) ram01_2(clk, entry, write && word_en[1] && byte_en[2], writedata[55:48], entry, readdata[55:48]);
simple_ram #(.width(8), .widthad(cache_entry)) ram01_1(clk, entry, write && word_en[1] && byte_en[1], writedata[47:40], entry, readdata[47:40]);
simple_ram #(.width(8), .widthad(cache_entry)) ram01_0(clk, entry, write && word_en[1] && byte_en[0], writedata[39:32], entry, readdata[39:32]);
simple_ram #(.width(8), .widthad(cache_entry)) ram00_3(clk, entry, write && word_en[0] && byte_en[3], writedata[31:24], entry, readdata[31:24]);
simple_ram #(.width(8), .widthad(cache_entry)) ram00_2(clk, entry, write && word_en[0] && byte_en[2], writedata[23:16], entry, readdata[23:16]);
simple_ram #(.width(8), .widthad(cache_entry)) ram00_1(clk, entry, write && word_en[0] && byte_en[1], writedata[15: 8], entry, readdata[15:8]);
simple_ram #(.width(8), .widthad(cache_entry)) ram00_0(clk, entry, write && word_en[0] && byte_en[0], writedata[ 7: 0], entry, readdata[ 7:0]);
assign write_tag_data = (read_miss) ? {1'b0, 1'b1, o_tag} : (modify || miss ) ? {1'b1, 1'b1, o_tag} : {1'b1, 1'b1, i_tag};
simple_ram #(.width(25-cache_entry), .widthad(cache_entry)) ram_tag(clk, entry, write, write_tag_data, entry, {dirty, valid, i_tag});
`ifdef SIM
integer i;
initial begin
for(i = 0; i <=(2**cache_entry-1); i=i+1) begin
ram_tag.mem[i] = 0;
end
end
`endif
endmodule |
module cache(clk,
rst,
i_p_addr,
i_p_byte_en,
i_p_writedata,
i_p_read,
i_p_write,
o_p_readdata,
o_p_readdata_valid,
o_p_waitrequest,
o_m_addr,
o_m_byte_en,
o_m_writedata,
o_m_read,
o_m_write,
i_m_readdata,
i_m_readdata_valid,
i_m_waitrequest,
cnt_r,
cnt_w,
cnt_hit_r,
cnt_hit_w,
cnt_wb_r,
cnt_wb_w);
parameter cache_entry = 9;
input wire clk, rst;
input wire [24:0] i_p_addr;
input wire [3:0] i_p_byte_en;
input wire [31:0] i_p_writedata;
input wire i_p_read, i_p_write;
output reg [31:0] o_p_readdata;
output reg o_p_readdata_valid;
output wire o_p_waitrequest;
output reg [25:0] o_m_addr;
output wire [3:0] o_m_byte_en;
output reg [127:0] o_m_writedata;
output reg o_m_read, o_m_write;
input wire [127:0] i_m_readdata;
input wire i_m_readdata_valid;
input wire i_m_waitrequest;
output reg [31:0] cnt_r;
output reg [31:0] cnt_w;
output reg [31:0] cnt_hit_r;
output reg [31:0] cnt_hit_w;
output reg [31:0] cnt_wb_r;
output reg [31:0] cnt_wb_w;
wire [7:0] hit;
wire [7:0] modify;
wire [7:0] miss;
wire [7:0] valid;
wire [127:0] readdata0, readdata1, readdata2, readdata3;
wire [127:0] readdata4, readdata5, readdata6, readdata7;
wire [127:0] writedata;
wire write0, write1, write2, write3;
wire write4, write5, write6, write7;
wire [3:0] word_en;
wire [3:0] byte_en;
wire [22:0] addr;
wire [22:0] wb_addr0, wb_addr1, wb_addr2, wb_addr3;
wire [22:0] wb_addr4, wb_addr5, wb_addr6, wb_addr7;
wire [7:0] r_cm_data;
wire [3:0] hit_num;
wire [3:0] invalid_num;
reg [2:0] state;
reg [127:0] writedata_buf;
reg [24:0] write_addr_buf;
reg [3:0] byte_en_buf;
reg write_buf, read_buf;
reg [7:0] write_set;
reg [7:0] fetch_write;
reg [7:0] w_cm_data;
reg w_cm;
// reg [2:0] replace;
wire [2:0] replace;
localparam IDLE = 0;
localparam COMP = 1;
localparam HIT = 2;
localparam FETCH1 = 3;
localparam FETCH2 = 4;
localparam FETCH3 = 5;
localparam WB1 = 6;
localparam WB2 = 7;
`ifdef SIM
integer i;
initial begin
for(i = 0; i <=(2**cache_entry-1); i=i+1) begin
ram_hot.mem[i] = 0;
end
end
`endif
simple_ram #(.width(8), .widthad(cache_entry)) ram_hot(clk, addr[cache_entry-1:0], w_cm, w_cm_data, addr[cache_entry-1:0], r_cm_data);
set #(.cache_entry(cache_entry))
set0(.clk(clk),
.rst(rst),
.entry(addr[cache_entry-1:0]),
.o_tag(addr[22:cache_entry]),
.writedata(writedata),
.byte_en(byte_en),
.write(write0),
.word_en(word_en), // 4word r/w change
.readdata(readdata0),
.wb_addr(wb_addr0),
.hit(hit[0]),
.modify(modify[0]),
.miss(miss[0]),
.valid(valid[0]),
.read_miss(read_buf));
set #(.cache_entry(cache_entry))
set1(.clk(clk),
.rst(rst),
.entry(addr[cache_entry-1:0]),
.o_tag(addr[22:cache_entry]),
.writedata(writedata),
.byte_en(byte_en),
.write(write1),
.word_en(word_en), // 4word r/w change
.readdata(readdata1),
.wb_addr(wb_addr1),
.hit(hit[1]),
.modify(modify[1]),
.miss(miss[1]),
.valid(valid[1]),
.read_miss(read_buf));
set #(.cache_entry(cache_entry))
set2(.clk(clk),
.rst(rst),
.entry(addr[cache_entry-1:0]),
.o_tag(addr[22:cache_entry]),
.writedata(writedata),
.byte_en(byte_en),
.write(write2),
.word_en(word_en), // 4word r/w change
.readdata(readdata2),
.wb_addr(wb_addr2),
.hit(hit[2]),
.modify(modify[2]),
.miss(miss[2]),
.valid(valid[2]),
.read_miss(read_buf));
set #(.cache_entry(cache_entry))
set3(.clk(clk),
.rst(rst),
.entry(addr[cache_entry-1:0]),
.o_tag(addr[22:cache_entry]),
.writedata(writedata),
.byte_en(byte_en),
.write(write3),
.word_en(word_en), // 4word r/w change
.readdata(readdata3),
.wb_addr(wb_addr3),
.hit(hit[3]),
.modify(modify[3]),
.miss(miss[3]),
.valid(valid[3]),
.read_miss(read_buf));
set #(.cache_entry(cache_entry))
set4(.clk(clk),
.rst(rst),
.entry(addr[cache_entry-1:0]),
.o_tag(addr[22:cache_entry]),
.writedata(writedata),
.byte_en(byte_en),
.write(write4),
.word_en(word_en), // 4word r/w change
.readdata(readdata4),
.wb_addr(wb_addr4),
.hit(hit[4]),
.modify(modify[4]),
.miss(miss[4]),
.valid(valid[4]),
.read_miss(read_buf));
set #(.cache_entry(cache_entry))
set5(.clk(clk),
.rst(rst),
.entry(addr[cache_entry-1:0]),
.o_tag(addr[22:cache_entry]),
.writedata(writedata),
.byte_en(byte_en),
.write(write5),
.word_en(word_en), // 4word r/w change
.readdata(readdata5),
.wb_addr(wb_addr5),
.hit(hit[5]),
.modify(modify[5]),
.miss(miss[5]),
.valid(valid[5]),
.read_miss(read_buf));
set #(.cache_entry(cache_entry))
set6(.clk(clk),
.rst(rst),
.entry(addr[cache_entry-1:0]),
.o_tag(addr[22:cache_entry]),
.writedata(writedata),
.byte_en(byte_en),
.write(write6),
.word_en(word_en), // 4word r/w change
.readdata(readdata6),
.wb_addr(wb_addr6),
.hit(hit[6]),
.modify(modify[6]),
.miss(miss[6]),
.valid(valid[6]),
.read_miss(read_buf));
set #(.cache_entry(cache_entry))
set7(.clk(clk),
.rst(rst),
.entry(addr[cache_entry-1:0]),
.o_tag(addr[22:cache_entry]),
.writedata(writedata),
.byte_en(byte_en),
.write(write7),
.word_en(word_en), // 4word r/w change
.readdata(readdata7),
.wb_addr(wb_addr7),
.hit(hit[7]),
.modify(modify[7]),
.miss(miss[7]),
.valid(valid[7]),
.read_miss(read_buf));
assign writedata = (|fetch_write) ? i_m_readdata : writedata_buf; //128bit
assign write0 = (fetch_write[0]) ? i_m_readdata_valid : write_set[0];
assign write1 = (fetch_write[1]) ? i_m_readdata_valid : write_set[1];
assign write2 = (fetch_write[2]) ? i_m_readdata_valid : write_set[2];
assign write3 = (fetch_write[3]) ? i_m_readdata_valid : write_set[3];
assign write4 = (fetch_write[4]) ? i_m_readdata_valid : write_set[4];
assign write5 = (fetch_write[5]) ? i_m_readdata_valid : write_set[5];
assign write6 = (fetch_write[6]) ? i_m_readdata_valid : write_set[6];
assign write7 = (fetch_write[7]) ? i_m_readdata_valid : write_set[7];
assign addr = (o_p_waitrequest) ? write_addr_buf[24:2] : i_p_addr[24:2]; // set module input addr is 23bit
assign byte_en = (|fetch_write) ? 4'b1111 : byte_en_buf;
assign o_p_waitrequest = (state != IDLE);
assign o_m_byte_en = 4'b1111;
assign hit_num = (hit[0]) ? 0 :
(hit[1]) ? 1 :
(hit[2]) ? 2 :
(hit[3]) ? 3 :
(hit[4]) ? 4 :
(hit[5]) ? 5 :
(hit[6]) ? 6 : 7;
assign invalid_num = (!valid[0]) ? 0 :
(!valid[1]) ? 1 :
(!valid[2]) ? 2 :
(!valid[3]) ? 3 :
(!valid[4]) ? 4 :
(!valid[5]) ? 5 :
(!valid[6]) ? 6 : 7;
assign word_en = (|fetch_write) ? 4'b1111 :
(write_addr_buf[1:0] == 2'b00) ? 4'b0001 :
(write_addr_buf[1:0] == 2'b01) ? 4'b0010 :
(write_addr_buf[1:0] == 2'b10) ? 4'b0100 : 4'b1000;
assign replace = (r_cm_data[6]) ? ((r_cm_data[4]) ? ((r_cm_data[0]) ? 7 : 6) : ((r_cm_data[1]) ? 5 : 4)) :
((r_cm_data[5]) ? ((r_cm_data[2]) ? 3 : 2) : ((r_cm_data[3]) ? 1 : 0));
always @(posedge clk) begin
if(hit) begin
case(hit_num)
0: w_cm_data <= {3'b011, r_cm_data[4], 1'b1, r_cm_data[2:0]};
1: w_cm_data <= {3'b011, r_cm_data[4], 1'b0, r_cm_data[2:0]};
2: w_cm_data <= {3'b010, r_cm_data[4:3], 1'b1, r_cm_data[1:0]};
3: w_cm_data <= {3'b010, r_cm_data[4:3], 1'b0, r_cm_data[1:0]};
4: w_cm_data <= {2'b00, r_cm_data[5], 1'b1, r_cm_data[3:2], 1'b1, r_cm_data[0]};
5: w_cm_data <= {2'b00, r_cm_data[5], 1'b1, r_cm_data[3:2], 1'b0, r_cm_data[0]};
6: w_cm_data <= {2'b00, r_cm_data[5], 1'b0, r_cm_data[3:1], 1'b1};
7: w_cm_data <= {2'b00, r_cm_data[5], 1'b0, r_cm_data[3:1], 1'b0};
endcase
end else if(!(&valid)) begin
case(invalid_num)
0: w_cm_data <= {3'b011, r_cm_data[4], 1'b1, r_cm_data[2:0]};
1: w_cm_data <= {3'b011, r_cm_data[4], 1'b0, r_cm_data[2:0]};
2: w_cm_data <= {3'b010, r_cm_data[4:3], 1'b1, r_cm_data[1:0]};
3: w_cm_data <= {3'b010, r_cm_data[4:3], 1'b0, r_cm_data[1:0]};
4: w_cm_data <= {2'b00, r_cm_data[5], 1'b1, r_cm_data[3:2], 1'b1, r_cm_data[0]};
5: w_cm_data <= {2'b00, r_cm_data[5], 1'b1, r_cm_data[3:2], 1'b0, r_cm_data[0]};
6: w_cm_data <= {2'b00, r_cm_data[5], 1'b0, r_cm_data[3:1], 1'b1};
7: w_cm_data <= {2'b00, r_cm_data[5], 1'b0, r_cm_data[3:1], 1'b0};
endcase
end else begin
case(replace)
0: w_cm_data <= {3'b011, r_cm_data[4], 1'b1, r_cm_data[2:0]};
1: w_cm_data <= {3'b011, r_cm_data[4], 1'b0, r_cm_data[2:0]};
2: w_cm_data <= {3'b010, r_cm_data[4:3], 1'b1, r_cm_data[1:0]};
3: w_cm_data <= {3'b010, r_cm_data[4:3], 1'b0, r_cm_data[1:0]};
4: w_cm_data <= {2'b00, r_cm_data[5], 1'b1, r_cm_data[3:2], 1'b1, r_cm_data[0]};
5: w_cm_data <= {2'b00, r_cm_data[5], 1'b1, r_cm_data[3:2], 1'b0, r_cm_data[0]};
6: w_cm_data <= {2'b00, r_cm_data[5], 1'b0, r_cm_data[3:1], 1'b1};
7: w_cm_data <= {2'b00, r_cm_data[5], 1'b0, r_cm_data[3:1], 1'b0};
endcase
end
end
always @(posedge clk) begin
if(rst) begin
o_p_readdata_valid <= 0;
{o_m_read, o_m_write} <= 0;
o_m_addr <= 0;
write_addr_buf <= 0;
byte_en_buf <= 0;
writedata_buf <= 0;
{write_buf, read_buf} <= 0;
write_set <= 0;
fetch_write <= 0;
w_cm <= 0;
{cnt_r, cnt_w} <= 0;
{cnt_hit_r, cnt_hit_w} <= 0;
{cnt_wb_r, cnt_wb_w} <= 0;
state <= IDLE;
end
else begin
case (state)
IDLE: begin
write_set <= 0;
o_p_readdata_valid <= 0;
writedata_buf <= {i_p_writedata, i_p_writedata, i_p_writedata, i_p_writedata};
write_addr_buf <= i_p_addr;
byte_en_buf <= i_p_byte_en;
write_buf <= i_p_write;
read_buf <= i_p_read;
if(i_p_read) begin
state <= COMP;
cnt_r <= cnt_r + 1;
end else if(i_p_write) begin
state <= COMP;
cnt_w <= cnt_w + 1;
end
end
COMP: begin
if((|hit) && write_buf) begin
state <= HIT;
w_cm <= 1;
write_set <= hit;
cnt_hit_w <= cnt_hit_w + 1;
end else if((|hit) && read_buf) begin
state <= IDLE;
w_cm <= 1;
o_p_readdata_valid <= 1;
cnt_hit_r <= cnt_hit_r + 1;
case(write_addr_buf[1:0])
2'b00: begin
o_p_readdata <= (hit[0]) ? readdata0[31:0] :
(hit[1]) ? readdata1[31:0] :
(hit[2]) ? readdata2[31:0] :
(hit[3]) ? readdata3[31:0] :
(hit[4]) ? readdata4[31:0] :
(hit[5]) ? readdata5[31:0] :
(hit[6]) ? readdata6[31:0] : readdata7[31:0];
end
2'b01: begin
o_p_readdata <= (hit[0]) ? readdata0[63:32] :
(hit[1]) ? readdata1[63:32] :
(hit[2]) ? readdata2[63:32] :
(hit[3]) ? readdata3[63:32] :
(hit[4]) ? readdata4[63:32] :
(hit[5]) ? readdata5[63:32] :
(hit[6]) ? readdata6[63:32] : readdata7[63:32];
end
2'b10: begin
o_p_readdata <= (hit[0]) ? readdata0[95:64] :
(hit[1]) ? readdata1[95:64] :
(hit[2]) ? readdata2[95:64] :
(hit[3]) ? readdata3[95:64] :
(hit[4]) ? readdata4[95:64] :
(hit[5]) ? readdata5[95:64] :
(hit[6]) ? readdata6[95:64] : readdata7[95:64];
end
2'b11: begin
o_p_readdata <= (hit[0]) ? readdata0[127:96] :
(hit[1]) ? readdata1[127:96] :
(hit[2]) ? readdata2[127:96] :
(hit[3]) ? readdata3[127:96] :
(hit[4]) ? readdata4[127:96] :
(hit[5]) ? readdata5[127:96] :
(hit[6]) ? readdata6[127:96] : readdata7[127:96];
end
endcase
end else if(!(&valid)) begin
state <= FETCH1;
w_cm <= 1;
o_m_addr <= {write_addr_buf[24:2], 3'b000};
o_m_read <= 1;
case(invalid_num)
0: fetch_write <= 8'b00000001;
1: fetch_write <= 8'b00000010;
2: fetch_write <= 8'b00000100;
3: fetch_write <= 8'b00001000;
4: fetch_write <= 8'b00010000;
5: fetch_write <= 8'b00100000;
6: fetch_write <= 8'b01000000;
7: fetch_write <= 8'b10000000;
endcase
end else if(miss[replace]) begin
state <= FETCH1;
w_cm <= 1;
o_m_addr <= {write_addr_buf[24:2], 3'b000};
o_m_read <= 1;
case(replace)
0: fetch_write <= 8'b00000001;
1: fetch_write <= 8'b00000010;
2: fetch_write <= 8'b00000100;
3: fetch_write <= 8'b00001000;
4: fetch_write <= 8'b00010000;
5: fetch_write <= 8'b00100000;
6: fetch_write <= 8'b01000000;
7: fetch_write <= 8'b10000000;
endcase
end else begin
state <= WB1;
w_cm <= 1;
case(replace)
0: fetch_write <= 8'b00000001;
1: fetch_write <= 8'b00000010;
2: fetch_write <= 8'b00000100;
3: fetch_write <= 8'b00001000;
4: fetch_write <= 8'b00010000;
5: fetch_write <= 8'b00100000;
6: fetch_write <= 8'b01000000;
7: fetch_write <= 8'b10000000;
endcase
if(read_buf) cnt_wb_r <= cnt_wb_r + 1;
else if(write_buf) cnt_wb_w <= cnt_wb_w + 1;
end
end
HIT: begin
w_cm <= 0;
write_set <= 0;
state <= IDLE;
end
FETCH1: begin
w_cm <= 0;
if(!i_m_waitrequest) begin
o_m_read <= 0;
state <= FETCH2;
end
end
FETCH2: begin
if(i_m_readdata_valid) begin
fetch_write <= 0; //add 3/9
if(write_buf) begin
state <= FETCH3;
write_set <= fetch_write;
end else if(read_buf) begin
state <= IDLE;
o_p_readdata_valid <= 1;
case(write_addr_buf[1:0])
2'b00: o_p_readdata <= i_m_readdata[ 31: 0];
2'b01: o_p_readdata <= i_m_readdata[ 63:32];
2'b10: o_p_readdata <= i_m_readdata[ 95:64];
2'b11: o_p_readdata <= i_m_readdata[127:96];
endcase
end
end
end
FETCH3: begin
state <= IDLE;
write_set <= 0;
end
WB1: begin
w_cm <= 0;
o_m_addr <= (fetch_write[0]) ? {wb_addr0, 3'b000} :
(fetch_write[1]) ? {wb_addr1, 3'b000} :
(fetch_write[2]) ? {wb_addr2, 3'b000} :
(fetch_write[3]) ? {wb_addr3, 3'b000} :
(fetch_write[4]) ? {wb_addr4, 3'b000} :
(fetch_write[5]) ? {wb_addr5, 3'b000} :
(fetch_write[6]) ? {wb_addr6, 3'b000} : {wb_addr7, 3'b000};
o_m_writedata <= (fetch_write[0]) ? readdata0 :
(fetch_write[1]) ? readdata1 :
(fetch_write[2]) ? readdata2 :
(fetch_write[3]) ? readdata3 :
(fetch_write[4]) ? readdata4 :
(fetch_write[5]) ? readdata5 :
(fetch_write[6]) ? readdata6 : readdata7;
o_m_write <= 1;
state <= WB2;
end
WB2: begin
if(!i_m_waitrequest) begin
o_m_write <= 0;
o_m_addr <= {write_addr_buf[24:2], 3'b000};
o_m_read <= 1;
state <= FETCH1;
end
end
endcase // case (state)
end
end
endmodule // cache |
module cache(clk,
rst,
i_p_addr,
i_p_byte_en,
i_p_writedata,
i_p_read,
i_p_write,
o_p_readdata,
o_p_readdata_valid,
o_p_waitrequest,
o_m_addr,
o_m_byte_en,
o_m_writedata,
o_m_read,
o_m_write,
i_m_readdata,
i_m_readdata_valid,
i_m_waitrequest,
cnt_r,
cnt_w,
cnt_hit_r,
cnt_hit_w,
cnt_wb_r,
cnt_wb_w,
cache_config,
change);
parameter cache_entry = 9;
input wire clk, rst;
input wire [24:0] i_p_addr;
input wire [3:0] i_p_byte_en;
input wire [31:0] i_p_writedata;
input wire i_p_read, i_p_write;
output reg [31:0] o_p_readdata;
output reg o_p_readdata_valid;
output wire o_p_waitrequest;
output reg [25:0] o_m_addr;
output wire [3:0] o_m_byte_en;
output reg [127:0] o_m_writedata;
output reg o_m_read, o_m_write;
input wire [127:0] i_m_readdata;
input wire i_m_readdata_valid;
input wire i_m_waitrequest;
output reg [31:0] cnt_r;
output reg [31:0] cnt_w;
output reg [31:0] cnt_hit_r;
output reg [31:0] cnt_hit_w;
output reg [31:0] cnt_wb_r;
output reg [31:0] cnt_wb_w;
input wire [3:0] cache_config;
input wire change;
wire [7:0] hit;
wire [7:0] modify;
wire [7:0] miss;
wire [7:0] valid;
wire [127:0] readdata0, readdata1, readdata2, readdata3;
wire [127:0] readdata4, readdata5, readdata6, readdata7;
wire [127:0] writedata;
wire write0, write1, write2, write3;
wire write4, write5, write6, write7;
wire [3:0] word_en;
wire [3:0] byte_en;
wire [22:0] addr;
wire [22:0] wb_addr0, wb_addr1, wb_addr2, wb_addr3;
wire [22:0] wb_addr4, wb_addr5, wb_addr6, wb_addr7;
wire [7:0] r_cm_data;
wire [3:0] hit_num;
wire [3:0] invalid_num;
reg [3:0] state;
reg [127:0] writedata_buf;
reg [24:0] write_addr_buf;
reg [3:0] byte_en_buf;
reg write_buf, read_buf;
reg [7:0] write_set;
reg [7:0] fetch_write;
reg [7:0] w_cm_data;
reg w_cm;
wire [2:0] replace;
reg [1:0] flash;
reg [3:0] phase;
reg [cache_entry:0] flash_cnt;
wire [7:0] dirty;
reg [3:0] current_config;
localparam IDLE = 0;
localparam COMP = 1;
localparam HIT = 2;
localparam FETCH1 = 3;
localparam FETCH2 = 4;
localparam FETCH3 = 5;
localparam WB1 = 6;
localparam WB2 = 7;
localparam FLASH = 8;
`ifdef SIM
integer i;
initial begin
for(i = 0; i <=(2**cache_entry-1); i=i+1) begin
ram_hot.mem[i] = 0;
end
end
`endif
simple_ram #(.width(8), .widthad(cache_entry)) ram_hot(clk, addr[cache_entry-1:0], w_cm, w_cm_data, addr[cache_entry-1:0], r_cm_data);
config_ctrl #(.cache_entry(cache_entry))
config_ctrl(.clk(clk),
.rst(rst),
.entry(addr[cache_entry-1:0]),
.o_tag(addr[22:cache_entry]),
.writedata(writedata),
.byte_en(byte_en),
.word_en(word_en),
.write({write7, write6, write5, write4, write3, write2, write1, write0}),
.readdata0(readdata0),
.readdata1(readdata1),
.readdata2(readdata2),
.readdata3(readdata3),
.readdata4(readdata4),
.readdata5(readdata5),
.readdata6(readdata6),
.readdata7(readdata7),
.wb_addr0(wb_addr0),
.wb_addr1(wb_addr1),
.wb_addr2(wb_addr2),
.wb_addr3(wb_addr3),
.wb_addr4(wb_addr4),
.wb_addr5(wb_addr5),
.wb_addr6(wb_addr6),
.wb_addr7(wb_addr7),
.hit(hit),
.miss(miss),
.dirty(dirty),
.valid(valid),
.read_miss(read_buf),
.flash(flash),
.c_fig(current_config)
);
assign writedata = (|fetch_write) ? i_m_readdata : writedata_buf; //128bit
assign write0 = (fetch_write[0]) ? i_m_readdata_valid : write_set[0];
assign write1 = (fetch_write[1]) ? i_m_readdata_valid : write_set[1];
assign write2 = (fetch_write[2]) ? i_m_readdata_valid : write_set[2];
assign write3 = (fetch_write[3]) ? i_m_readdata_valid : write_set[3];
assign write4 = (fetch_write[4]) ? i_m_readdata_valid : write_set[4];
assign write5 = (fetch_write[5]) ? i_m_readdata_valid : write_set[5];
assign write6 = (fetch_write[6]) ? i_m_readdata_valid : write_set[6];
assign write7 = (fetch_write[7]) ? i_m_readdata_valid : write_set[7];
assign addr = (state == FLASH) ? {write_addr_buf[24:cache_entry+2], flash_cnt[cache_entry-1:0]} :
(o_p_waitrequest) ? write_addr_buf[24:2] : i_p_addr[24:2]; // set module input addr is 23bit
assign byte_en = (|fetch_write) ? 4'b1111 : byte_en_buf;
assign o_p_waitrequest = (state != IDLE);
assign o_m_byte_en = 4'b1111;
assign hit_num = (hit[0]) ? 0 :
(hit[1]) ? 1 :
(hit[2]) ? 2 :
(hit[3]) ? 3 :
(hit[4]) ? 4 :
(hit[5]) ? 5 :
(hit[6]) ? 6 : 7;
assign invalid_num = (!valid[0]) ? 0 :
(!valid[1]) ? 1 :
(!valid[2]) ? 2 :
(!valid[3]) ? 3 :
(!valid[4]) ? 4 :
(!valid[5]) ? 5 :
(!valid[6]) ? 6 : 7;
assign word_en = (|fetch_write) ? 4'b1111 :
(write_addr_buf[1:0] == 2'b00) ? 4'b0001 :
(write_addr_buf[1:0] == 2'b01) ? 4'b0010 :
(write_addr_buf[1:0] == 2'b10) ? 4'b0100 : 4'b1000;
assign replace = (current_config) ? {1'b0, r_cm_data[1:0]} :
(r_cm_data[6]) ? ((r_cm_data[4]) ? ((r_cm_data[0]) ? 7 : 6) : ((r_cm_data[1]) ? 5 : 4)) :
((r_cm_data[5]) ? ((r_cm_data[2]) ? 3 : 2) : ((r_cm_data[3]) ? 1 : 0));
always @(posedge clk) begin
if(current_config == 4'b0000) begin
if(hit) begin
case(hit_num)
0: w_cm_data <= {3'b011, r_cm_data[4], 1'b1, r_cm_data[2:0]};
1: w_cm_data <= {3'b011, r_cm_data[4], 1'b0, r_cm_data[2:0]};
2: w_cm_data <= {3'b010, r_cm_data[4:3], 1'b1, r_cm_data[1:0]};
3: w_cm_data <= {3'b010, r_cm_data[4:3], 1'b0, r_cm_data[1:0]};
4: w_cm_data <= {2'b00, r_cm_data[5], 1'b1, r_cm_data[3:2], 1'b1, r_cm_data[0]};
5: w_cm_data <= {2'b00, r_cm_data[5], 1'b1, r_cm_data[3:2], 1'b0, r_cm_data[0]};
6: w_cm_data <= {2'b00, r_cm_data[5], 1'b0, r_cm_data[3:1], 1'b1};
7: w_cm_data <= {2'b00, r_cm_data[5], 1'b0, r_cm_data[3:1], 1'b0};
endcase
end else if(!(&valid)) begin
case(invalid_num)
// 0: w_cm_data <= {3'b011, r_cm_data[4], 1'b1, r_cm_data[2:0]};
0: w_cm_data <= 8'b01101000;
1: w_cm_data <= {3'b011, r_cm_data[4], 1'b0, r_cm_data[2:0]};
2: w_cm_data <= {3'b010, r_cm_data[4:3], 1'b1, r_cm_data[1:0]};
3: w_cm_data <= {3'b010, r_cm_data[4:3], 1'b0, r_cm_data[1:0]};
4: w_cm_data <= {2'b00, r_cm_data[5], 1'b1, r_cm_data[3:2], 1'b1, r_cm_data[0]};
5: w_cm_data <= {2'b00, r_cm_data[5], 1'b1, r_cm_data[3:2], 1'b0, r_cm_data[0]};
6: w_cm_data <= {2'b00, r_cm_data[5], 1'b0, r_cm_data[3:1], 1'b1};
7: w_cm_data <= {2'b00, r_cm_data[5], 1'b0, r_cm_data[3:1], 1'b0};
endcase
end else begin
case(replace)
0: w_cm_data <= {3'b011, r_cm_data[4], 1'b1, r_cm_data[2:0]};
1: w_cm_data <= {3'b011, r_cm_data[4], 1'b0, r_cm_data[2:0]};
2: w_cm_data <= {3'b010, r_cm_data[4:3], 1'b1, r_cm_data[1:0]};
3: w_cm_data <= {3'b010, r_cm_data[4:3], 1'b0, r_cm_data[1:0]};
4: w_cm_data <= {2'b00, r_cm_data[5], 1'b1, r_cm_data[3:2], 1'b1, r_cm_data[0]};
5: w_cm_data <= {2'b00, r_cm_data[5], 1'b1, r_cm_data[3:2], 1'b0, r_cm_data[0]};
6: w_cm_data <= {2'b00, r_cm_data[5], 1'b0, r_cm_data[3:1], 1'b1};
7: w_cm_data <= {2'b00, r_cm_data[5], 1'b0, r_cm_data[3:1], 1'b0};
endcase
end
end else if(current_config == 4'b0001) begin
if(hit) begin
w_cm_data <= (r_cm_data[1:0] == hit_num) ? {r_cm_data[1:0], r_cm_data[7:2]} :
(r_cm_data[3:2] == hit_num) ? {r_cm_data[3:2], r_cm_data[7:4], r_cm_data[1:0]} :
(r_cm_data[5:4] == hit_num) ? {r_cm_data[5:4], r_cm_data[7:6], r_cm_data[3:0]} : r_cm_data;
end else if(!(&valid)) begin
if(!valid[0]) w_cm_data <= 8'b00111001;
else begin
w_cm_data <= (r_cm_data[1:0] == invalid_num) ? {r_cm_data[1:0], r_cm_data[7:2]} :
(r_cm_data[3:2] == invalid_num) ? {r_cm_data[3:2], r_cm_data[7:4], r_cm_data[1:0]} :
(r_cm_data[5:4] == invalid_num) ? {r_cm_data[5:4], r_cm_data[7:6], r_cm_data[3:0]} : r_cm_data;
end
end else begin
w_cm_data <= {r_cm_data[1:0], r_cm_data[7:2]};
end
end else if(current_config == 4'b0010) begin
if(hit) begin
w_cm_data <= (r_cm_data[1:0] == hit_num) ? {r_cm_data[7:4], r_cm_data[1:0], r_cm_data[3:2]} : r_cm_data;
end else if(!(&valid)) begin
if(!valid[0]) w_cm_data <= 8'b11100001;
else begin
w_cm_data <= (r_cm_data[1:0] == invalid_num) ? {r_cm_data[7:4], r_cm_data[1:0], r_cm_data[3:2]} : r_cm_data;
end
end else begin
w_cm_data <= {r_cm_data[7:4], r_cm_data[1:0], r_cm_data[3:2]};
end
end
end
always @(posedge clk) begin
if(rst) begin
o_p_readdata_valid <= 0;
{o_m_read, o_m_write} <= 0;
o_m_addr <= 0;
write_addr_buf <= 0;
byte_en_buf <= 0;
writedata_buf <= 0;
{write_buf, read_buf} <= 0;
write_set <= 0;
fetch_write <= 0;
flash <= 0;
phase <= 0;
flash_cnt <= 0;
current_config <= 0; // default cache config is 4way
w_cm <= 0;
{cnt_r, cnt_w} <= 0;
{cnt_hit_r, cnt_hit_w} <= 0;
{cnt_wb_r, cnt_wb_w} <= 0;
state <= IDLE;
end
else begin
case (state)
IDLE: begin
write_set <= 0;
o_p_readdata_valid <= 0;
writedata_buf <= {i_p_writedata, i_p_writedata, i_p_writedata, i_p_writedata};
write_addr_buf <= i_p_addr;
byte_en_buf <= i_p_byte_en;
write_buf <= i_p_write;
read_buf <= i_p_read;
if(i_p_read) begin
state <= COMP;
cnt_r <= cnt_r + 1;
end else if(i_p_write) begin
state <= COMP;
cnt_w <= cnt_w + 1;
end else if(change) begin
state <= FLASH;
flash <= 2'b10;
phase <= 0;
end
end
COMP: begin
if((|hit) && write_buf) begin
state <= HIT;
w_cm <= 1;
write_set <= hit;
cnt_hit_w <= cnt_hit_w + 1;
end else if((|hit) && read_buf) begin
state <= IDLE;
w_cm <= 1;
o_p_readdata_valid <= 1;
cnt_hit_r <= cnt_hit_r + 1;
case(write_addr_buf[1:0])
2'b00: begin
o_p_readdata <= (hit[0]) ? readdata0[31:0] :
(hit[1]) ? readdata1[31:0] :
(hit[2]) ? readdata2[31:0] :
(hit[3]) ? readdata3[31:0] :
(hit[4]) ? readdata4[31:0] :
(hit[5]) ? readdata5[31:0] :
(hit[6]) ? readdata6[31:0] : readdata7[31:0];
end
2'b01: begin
o_p_readdata <= (hit[0]) ? readdata0[63:32] :
(hit[1]) ? readdata1[63:32] :
(hit[2]) ? readdata2[63:32] :
(hit[3]) ? readdata3[63:32] :
(hit[4]) ? readdata4[63:32] :
(hit[5]) ? readdata5[63:32] :
(hit[6]) ? readdata6[63:32] : readdata7[63:32];
end
2'b10: begin
o_p_readdata <= (hit[0]) ? readdata0[95:64] :
(hit[1]) ? readdata1[95:64] :
(hit[2]) ? readdata2[95:64] :
(hit[3]) ? readdata3[95:64] :
(hit[4]) ? readdata4[95:64] :
(hit[5]) ? readdata5[95:64] :
(hit[6]) ? readdata6[95:64] : readdata7[95:64];
end
2'b11: begin
o_p_readdata <= (hit[0]) ? readdata0[127:96] :
(hit[1]) ? readdata1[127:96] :
(hit[2]) ? readdata2[127:96] :
(hit[3]) ? readdata3[127:96] :
(hit[4]) ? readdata4[127:96] :
(hit[5]) ? readdata5[127:96] :
(hit[6]) ? readdata6[127:96] : readdata7[127:96];
end
endcase
end else if(!(&valid)) begin
state <= FETCH1;
w_cm <= 1;
o_m_addr <= {write_addr_buf[24:2], 3'b000};
o_m_read <= 1;
case(invalid_num)
0: fetch_write <= 8'b00000001;
1: fetch_write <= 8'b00000010;
2: fetch_write <= 8'b00000100;
3: fetch_write <= 8'b00001000;
4: fetch_write <= 8'b00010000;
5: fetch_write <= 8'b00100000;
6: fetch_write <= 8'b01000000;
7: fetch_write <= 8'b10000000;
endcase
end else if(miss[replace]) begin
state <= FETCH1;
w_cm <= 1;
o_m_addr <= {write_addr_buf[24:2], 3'b000};
o_m_read <= 1;
case(replace)
0: fetch_write <= 8'b00000001;
1: fetch_write <= 8'b00000010;
2: fetch_write <= 8'b00000100;
3: fetch_write <= 8'b00001000;
4: fetch_write <= 8'b00010000;
5: fetch_write <= 8'b00100000;
6: fetch_write <= 8'b01000000;
7: fetch_write <= 8'b10000000;
endcase
end else begin
state <= WB1;
w_cm <= 1;
case(replace)
0: fetch_write <= 8'b00000001;
1: fetch_write <= 8'b00000010;
2: fetch_write <= 8'b00000100;
3: fetch_write <= 8'b00001000;
4: fetch_write <= 8'b00010000;
5: fetch_write <= 8'b00100000;
6: fetch_write <= 8'b01000000;
7: fetch_write <= 8'b10000000;
endcase
if(read_buf) cnt_wb_r <= cnt_wb_r + 1;
else if(write_buf) cnt_wb_w <= cnt_wb_w + 1;
end
end
HIT: begin
w_cm <= 0;
write_set <= 0;
state <= IDLE;
end
FETCH1: begin
w_cm <= 0;
if(!i_m_waitrequest) begin
o_m_read <= 0;
state <= FETCH2;
end
end
FETCH2: begin
if(i_m_readdata_valid) begin
fetch_write <= 0; //add 3/9
if(write_buf) begin
state <= FETCH3;
write_set <= fetch_write;
end else if(read_buf) begin
state <= IDLE;
o_p_readdata_valid <= 1;
case(write_addr_buf[1:0])
2'b00: o_p_readdata <= i_m_readdata[ 31: 0];
2'b01: o_p_readdata <= i_m_readdata[ 63:32];
2'b10: o_p_readdata <= i_m_readdata[ 95:64];
2'b11: o_p_readdata <= i_m_readdata[127:96];
endcase
end
end
end
FETCH3: begin
state <= IDLE;
write_set <= 0;
end
WB1: begin
w_cm <= 0;
o_m_addr <= (fetch_write[0]) ? {wb_addr0, 3'b000} :
(fetch_write[1]) ? {wb_addr1, 3'b000} :
(fetch_write[2]) ? {wb_addr2, 3'b000} :
(fetch_write[3]) ? {wb_addr3, 3'b000} :
(fetch_write[4]) ? {wb_addr4, 3'b000} :
(fetch_write[5]) ? {wb_addr5, 3'b000} :
(fetch_write[6]) ? {wb_addr6, 3'b000} : {wb_addr7, 3'b000};
o_m_writedata <= (fetch_write[0]) ? readdata0 :
(fetch_write[1]) ? readdata1 :
(fetch_write[2]) ? readdata2 :
(fetch_write[3]) ? readdata3 :
(fetch_write[4]) ? readdata4 :
(fetch_write[5]) ? readdata5 :
(fetch_write[6]) ? readdata6 : readdata7;
o_m_write <= 1;
state <= WB2;
end
WB2: begin
if(!i_m_waitrequest) begin
o_m_write <= 0;
o_m_addr <= {write_addr_buf[24:2], 3'b000};
o_m_read <= 1;
state <= FETCH1;
end
end
FLASH: begin
if(!i_m_waitrequest) begin
if(flash_cnt[cache_entry] && !change) begin
state <= IDLE;
flash <= 0;
o_m_write <= 0;
flash_cnt <= 0;
current_config <= cache_config;
end else if(flash_cnt[cache_entry]) begin
flash <= 0;
o_m_write <= 0;
end else begin
phase <= (phase == 10) ? 0 : phase + 1;
case(phase)
0: o_m_write <= 0;
1: begin
if(dirty[0]) begin
o_m_addr <= {wb_addr0, 3'b000};
o_m_writedata <= readdata0;
o_m_write <= 1;
end else begin
o_m_write <= 0;
end
end
2: begin
if(dirty[1]) begin
o_m_addr <= {wb_addr1, 3'b000};
o_m_writedata <= readdata1;
o_m_write <= 1;
end else begin
o_m_write <= 0;
end
end
3: begin
if(dirty[2]) begin
o_m_addr <= {wb_addr2, 3'b000};
o_m_writedata <= readdata2;
o_m_write <= 1;
end else begin
o_m_write <= 0;
end
end
4: begin
if(dirty[3]) begin
o_m_addr <= {wb_addr3, 3'b000};
o_m_writedata <= readdata3;
o_m_write <= 1;
end else begin
o_m_write <= 0;
end
end
5: begin
if(dirty[4]) begin
o_m_addr <= {wb_addr4, 3'b000};
o_m_writedata <= readdata0;
o_m_write <= 1;
end else begin
o_m_write <= 0;
end
end
6: begin
if(dirty[5]) begin
o_m_addr <= {wb_addr5, 3'b000};
o_m_writedata <= readdata1;
o_m_write <= 1;
end else begin
o_m_write <= 0;
end
end
7: begin
if(dirty[6]) begin
o_m_addr <= {wb_addr6, 3'b000};
o_m_writedata <= readdata2;
o_m_write <= 1;
end else begin
o_m_write <= 0;
end
end
8: begin
if(dirty[7]) begin
o_m_addr <= {wb_addr7, 3'b000};
o_m_writedata <= readdata3;
o_m_write <= 1;
end else begin
o_m_write <= 0;
end
end
9: begin
o_m_write <= 0;
flash <= 2'b11;
end
10: begin
flash <= 2'b10;
flash_cnt <= flash_cnt + 1;
end
endcase
end
end
end
endcase // case (state)
end
end
endmodule // cache |
module config_ctrl(clk,
rst,
entry,
o_tag,
writedata,
byte_en,
word_en,
write,
readdata0,
readdata1,
readdata2,
readdata3,
readdata4,
readdata5,
readdata6,
readdata7,
wb_addr0,
wb_addr1,
wb_addr2,
wb_addr3,
wb_addr4,
wb_addr5,
wb_addr6,
wb_addr7,
hit,
miss,
dirty,
valid,
read_miss,
flash,
c_fig);
parameter cache_entry = 14;
input wire clk, rst;
input wire [cache_entry-1:0] entry;
input wire [22-cache_entry:0] o_tag;
input wire [127:0] writedata;
input wire [3:0] byte_en;
input wire [3:0] word_en;
input wire [7:0] write;
input wire read_miss;
input wire [1:0] flash;
input wire [3:0] c_fig;
output wire [127:0] readdata0, readdata1, readdata2, readdata3;
output wire [127:0] readdata4, readdata5, readdata6, readdata7;
output wire [22:0] wb_addr0, wb_addr1, wb_addr2, wb_addr3;
output wire [22:0] wb_addr4, wb_addr5, wb_addr6, wb_addr7;
output wire [7:0] hit, miss, dirty, valid;
wire [7:0] s_hit;
wire [7:0] s_miss;
wire [7:0] s_dirty;
wire [7:0] s_valid;
wire [127:0] s_readdata0, s_readdata1, s_readdata2, s_readdata3;
wire [127:0] s_readdata4, s_readdata5, s_readdata6, s_readdata7;
wire [22:0] s_wb_addr0, s_wb_addr1, s_wb_addr2, s_wb_addr3;
wire [22:0] s_wb_addr4, s_wb_addr5, s_wb_addr6, s_wb_addr7;
assign hit = (c_fig == 0) ? s_hit :
(c_fig == 4'b0001) ? ((o_tag[0]) ? {4'b0000, s_hit[7], s_hit[5], s_hit[3], s_hit[1]} :
{4'b0000, s_hit[6], s_hit[4], s_hit[2], s_hit[0]}) :
(c_fig == 4'b0010) ? ((o_tag[1:0] == 2'b00) ? {6'b000000, s_hit[4], s_hit[0]} :
(o_tag[1:0] == 2'b01) ? {6'b000000, s_hit[5], s_hit[1]} :
(o_tag[1:0] == 2'b10) ? {6'b000000, s_hit[6], s_hit[2]} :
{6'b000000, s_hit[7], s_hit[3]}) : 8'b00000000;
assign miss = (c_fig == 0) ? s_miss :
(c_fig == 4'b0001) ? ((o_tag[0]) ? {4'b0000, s_miss[7], s_miss[5], s_miss[3], s_miss[1]} :
{4'b0000, s_miss[6], s_miss[4], s_miss[2], s_miss[0]}) :
(c_fig == 4'b0010) ? ((o_tag[1:0] == 2'b00) ? {6'b000000, s_miss[4], s_miss[0]} :
(o_tag[1:0] == 2'b01) ? {6'b000000, s_miss[5], s_miss[1]} :
(o_tag[1:0] == 2'b10) ? {6'b000000, s_miss[6], s_miss[2]} :
{6'b000000, s_miss[7], s_miss[3]}) : 8'b00000000;
assign dirty = s_dirty;
assign valid = (c_fig == 0) ? s_valid :
(c_fig == 4'b0001) ? ((o_tag[0]) ? {4'b1111, s_valid[7], s_valid[5], s_valid[3], s_valid[1]} :
{4'b1111, s_valid[6], s_valid[4], s_valid[2], s_valid[0]}) :
(c_fig == 4'b0010) ? ((o_tag[1:0] == 2'b00) ? {6'b111111, s_valid[4], s_valid[0]} :
(o_tag[1:0] == 2'b01) ? {6'b111111, s_valid[5], s_valid[1]} :
(o_tag[1:0] == 2'b10) ? {6'b111111, s_valid[6], s_valid[2]} :
{6'b111111, s_valid[7], s_valid[3]}) : 8'b00000000;
assign readdata0 = ((c_fig == 0) || flash[1]) ? s_readdata0 :
(c_fig == 4'b0001) ? ((o_tag[0]) ? s_readdata1 : s_readdata0) :
(c_fig == 4'b0010) ? ((o_tag[1:0] == 2'b00) ? s_readdata0 :
(o_tag[1:0] == 2'b01) ? s_readdata1 :
(o_tag[1:0] == 2'b10) ? s_readdata2 : s_readdata3) : s_readdata0;
assign readdata1 = ((c_fig == 0) || flash[1]) ? s_readdata1 :
(c_fig == 4'b0001) ? ((o_tag[0]) ? s_readdata3 : s_readdata2) :
(c_fig == 4'b0010) ? ((o_tag[1:0] == 2'b00) ? s_readdata4 :
(o_tag[1:0] == 2'b01) ? s_readdata5 :
(o_tag[1:0] == 2'b10) ? s_readdata6 : s_readdata7) : s_readdata1;
assign readdata2 = ((c_fig == 0) || flash[1]) ? s_readdata2 :
(c_fig == 4'b0001) ? ((o_tag[0]) ? s_readdata5 : s_readdata4) : readdata2;
assign readdata3 = ((c_fig == 0) || flash[1]) ? s_readdata3 :
(c_fig == 4'b0001) ? ((o_tag[0]) ? s_readdata7 : s_readdata6) : readdata3;
assign readdata4 = s_readdata4;
assign readdata5 = s_readdata5;
assign readdata6 = s_readdata6;
assign readdata7 = s_readdata7;
assign wb_addr0 = ((c_fig == 0) || flash[1]) ? s_wb_addr0 :
(c_fig == 4'b0001) ? ((o_tag[0]) ? s_wb_addr1 : s_wb_addr0) :
(c_fig == 4'b0010) ? ((o_tag[1:0] == 2'b00) ? s_wb_addr0 :
(o_tag[1:0] == 2'b01) ? s_wb_addr1 :
(o_tag[1:0] == 2'b10) ? s_wb_addr2 : s_wb_addr3) : s_wb_addr0;
assign wb_addr1 = ((c_fig == 0) || flash[1]) ? s_wb_addr1 :
(c_fig == 4'b0001) ? ((o_tag[0]) ? s_wb_addr3 : s_wb_addr2) :
(c_fig == 4'b0010) ? ((o_tag[1:0] == 2'b00) ? s_wb_addr4 :
(o_tag[1:0] == 2'b01) ? s_wb_addr5 :
(o_tag[1:0] == 2'b10) ? s_wb_addr6 : s_wb_addr7) : s_wb_addr1;
assign wb_addr2 = ((c_fig == 0) || flash[1]) ? s_wb_addr2 :
(c_fig == 4'b0001) ? ((o_tag[0]) ? s_wb_addr5 : s_wb_addr4) : wb_addr2;
assign wb_addr3 = ((c_fig == 0) || flash[1]) ? s_wb_addr3 :
(c_fig == 4'b0001) ? ((o_tag[0]) ? s_wb_addr7 : s_wb_addr6) : wb_addr3;
assign wb_addr4 = s_wb_addr4;
assign wb_addr5 = s_wb_addr5;
assign wb_addr6 = s_wb_addr6;
assign wb_addr7 = s_wb_addr7;
wire [7:0] s_write;
assign s_write = (c_fig == 0) ? write :
(c_fig == 4'b0001) ? ((o_tag[0]) ? {write[3], 1'b0, write[2], 1'b0, write[1], 1'b0, write[0], 1'b0} :
{1'b0, write[3], 1'b0, write[2], 1'b0, write[1], 1'b0, write[0]}) :
(c_fig == 4'b0010) ? ((o_tag[1:0] == 2'b00) ? {3'b000, write[1], 3'b000, write[0]} :
(o_tag[1:0] == 2'b01) ? {2'b00, write[1], 3'b000, write[0], 1'b0} :
(o_tag[1:0] == 2'b10) ? {1'b0, write[1], 3'b000, write[0], 2'b00} : {write[1], 3'b000, write[0], 3'b000}) : 8'b00000000;
set #(.cache_entry(cache_entry))
set0(.clk(clk),
.rst(rst),
.entry(entry),
.o_tag(o_tag),
.writedata(writedata),
.byte_en(byte_en),
.word_en(word_en), // 4word r/w change
.write(s_write[0]),
.readdata(s_readdata0),
.wb_addr(s_wb_addr0),
.hit(s_hit[0]),
.miss(s_miss[0]),
.dirty(s_dirty[0]),
.valid(s_valid[0]),
.read_miss(read_miss),
.flash(flash[0]));
set #(.cache_entry(cache_entry))
set1(.clk(clk),
.rst(rst),
.entry(entry),
.o_tag(o_tag),
.writedata(writedata),
.byte_en(byte_en),
.word_en(word_en), // 4word r/w change
.write(s_write[1]),
.readdata(s_readdata1),
.wb_addr(s_wb_addr1),
.hit(s_hit[1]),
.miss(s_miss[1]),
.dirty(s_dirty[1]),
.valid(s_valid[1]),
.read_miss(read_miss),
.flash(flash[0]));
set #(.cache_entry(cache_entry))
set2(.clk(clk),
.rst(rst),
.entry(entry),
.o_tag(o_tag),
.writedata(writedata),
.byte_en(byte_en),
.word_en(word_en), // 4word r/w change
.write(s_write[2]),
.readdata(s_readdata2),
.wb_addr(s_wb_addr2),
.hit(s_hit[2]),
.miss(s_miss[2]),
.dirty(s_dirty[2]),
.valid(s_valid[2]),
.read_miss(read_miss),
.flash(flash[0]));
set #(.cache_entry(cache_entry))
set3(.clk(clk),
.rst(rst),
.entry(entry),
.o_tag(o_tag),
.writedata(writedata),
.byte_en(byte_en),
.word_en(word_en), // 4word r/w change
.write(s_write[3]),
.readdata(s_readdata3),
.wb_addr(s_wb_addr3),
.hit(s_hit[3]),
.miss(s_miss[3]),
.dirty(s_dirty[3]),
.valid(s_valid[3]),
.read_miss(read_miss),
.flash(flash[0]));
set #(.cache_entry(cache_entry))
set4(.clk(clk),
.rst(rst),
.entry(entry),
.o_tag(o_tag),
.writedata(writedata),
.byte_en(byte_en),
.word_en(word_en), // 4word r/w change
.write(s_write[4]),
.readdata(s_readdata4),
.wb_addr(s_wb_addr4),
.hit(s_hit[4]),
.miss(s_miss[4]),
.dirty(s_dirty[4]),
.valid(s_valid[4]),
.read_miss(read_miss),
.flash(flash[0]));
set #(.cache_entry(cache_entry))
set5(.clk(clk),
.rst(rst),
.entry(entry),
.o_tag(o_tag),
.writedata(writedata),
.byte_en(byte_en),
.word_en(word_en), // 4word r/w change
.write(s_write[5]),
.readdata(s_readdata5),
.wb_addr(s_wb_addr5),
.hit(s_hit[5]),
.miss(s_miss[5]),
.dirty(s_dirty[5]),
.valid(s_valid[5]),
.read_miss(read_miss),
.flash(flash[0]));
set #(.cache_entry(cache_entry))
set6(.clk(clk),
.rst(rst),
.entry(entry),
.o_tag(o_tag),
.writedata(writedata),
.byte_en(byte_en),
.word_en(word_en), // 4word r/w change
.write(s_write[6]),
.readdata(s_readdata6),
.wb_addr(s_wb_addr6),
.hit(s_hit[6]),
.miss(s_miss[6]),
.dirty(s_dirty[6]),
.valid(s_valid[6]),
.read_miss(read_miss),
.flash(flash[0]));
set #(.cache_entry(cache_entry))
set7(.clk(clk),
.rst(rst),
.entry(entry),
.o_tag(o_tag),
.writedata(writedata),
.byte_en(byte_en),
.word_en(word_en), // 4word r/w change
.write(s_write[7]),
.readdata(s_readdata7),
.wb_addr(s_wb_addr7),
.hit(s_hit[7]),
.miss(s_miss[7]),
.dirty(s_dirty[7]),
.valid(s_valid[7]),
.read_miss(read_miss),
.flash(flash[0]));
endmodule // config_ctrl |
module simple_ram
#(parameter width = 1,
parameter widthad = 1
)
(
input clk,
input [widthad-1:0] wraddress,
input wren,
input [width-1:0] data,
input [widthad-1:0] rdaddress,
output reg [width-1:0] q
);
reg [width-1:0] mem [(2**widthad)-1:0];
always @(posedge clk) begin
if(wren) mem[wraddress] <= data;
q <= mem[rdaddress];
end
endmodule |
module uart(
input clk, // The master clock for this module
input rst, // Synchronous reset.
input rx, // Incoming serial line
output tx, // Outgoing serial line
input transmit, // Signal to transmit
input [7:0] tx_byte, // Byte to transmit
output received, // Indicated that a byte has been received.
output [7:0] rx_byte, // Byte received
output is_receiving, // Low when receive line is idle.
output is_transmitting, // Low when transmit line is idle.
output recv_error // Indicates error in receiving packet.
);
parameter CLOCK_DIVIDE = 1302; // clock rate (50Mhz) / (baud rate (9600) * 4)
// States for the receiving state machine.
// These are just constants, not parameters to override.
parameter RX_IDLE = 0;
parameter RX_CHECK_START = 1;
parameter RX_READ_BITS = 2;
parameter RX_CHECK_STOP = 3;
parameter RX_DELAY_RESTART = 4;
parameter RX_ERROR = 5;
parameter RX_RECEIVED = 6;
// States for the transmitting state machine.
// Constants - do not override.
parameter TX_IDLE = 0;
parameter TX_SENDING = 1;
parameter TX_DELAY_RESTART = 2;
reg [10:0] rx_clk_divider = CLOCK_DIVIDE;
reg [10:0] tx_clk_divider = CLOCK_DIVIDE;
reg [2:0] recv_state = RX_IDLE;
reg [5:0] rx_countdown;
reg [3:0] rx_bits_remaining;
reg [7:0] rx_data;
reg tx_out = 1'b1;
reg [1:0] tx_state = TX_IDLE;
reg [5:0] tx_countdown;
reg [3:0] tx_bits_remaining;
reg [7:0] tx_data;
assign received = recv_state == RX_RECEIVED;
assign recv_error = recv_state == RX_ERROR;
assign is_receiving = recv_state != RX_IDLE;
assign rx_byte = rx_data;
assign tx = tx_out;
assign is_transmitting = tx_state != TX_IDLE;
always @(posedge clk) begin
if (rst) begin
recv_state = RX_IDLE;
tx_state = TX_IDLE;
end
// The clk_divider counter counts down from
// the CLOCK_DIVIDE constant. Whenever it
// reaches 0, 1/16 of the bit period has elapsed.
// Countdown timers for the receiving and transmitting
// state machines are decremented.
rx_clk_divider = rx_clk_divider - 1;
if (!rx_clk_divider) begin
rx_clk_divider = CLOCK_DIVIDE;
rx_countdown = rx_countdown - 1;
end
tx_clk_divider = tx_clk_divider - 1;
if (!tx_clk_divider) begin
tx_clk_divider = CLOCK_DIVIDE;
tx_countdown = tx_countdown - 1;
end
// Receive state machine
case (recv_state)
RX_IDLE: begin
// A low pulse on the receive line indicates the
// start of data.
if (!rx) begin
// Wait half the period - should resume in the
// middle of this first pulse.
rx_clk_divider = CLOCK_DIVIDE;
rx_countdown = 2;
recv_state = RX_CHECK_START;
end
end
RX_CHECK_START: begin
if (!rx_countdown) begin
// Check the pulse is still there
if (!rx) begin
// Pulse still there - good
// Wait the bit period to resume half-way
// through the first bit.
rx_countdown = 4;
rx_bits_remaining = 8;
recv_state = RX_READ_BITS;
end else begin
// Pulse lasted less than half the period -
// not a valid transmission.
recv_state = RX_ERROR;
end
end
end
RX_READ_BITS: begin
if (!rx_countdown) begin
// Should be half-way through a bit pulse here.
// Read this bit in, wait for the next if we
// have more to get.
rx_data = {rx, rx_data[7:1]};
rx_countdown = 4;
rx_bits_remaining = rx_bits_remaining - 1;
recv_state = rx_bits_remaining ? RX_READ_BITS : RX_CHECK_STOP;
end
end
RX_CHECK_STOP: begin
if (!rx_countdown) begin
// Should resume half-way through the stop bit
// This should be high - if not, reject the
// transmission and signal an error.
recv_state = rx ? RX_RECEIVED : RX_ERROR;
end
end
RX_DELAY_RESTART: begin
// Waits a set number of cycles before accepting
// another transmission.
recv_state = rx_countdown ? RX_DELAY_RESTART : RX_IDLE;
end
RX_ERROR: begin
// There was an error receiving.
// Raises the recv_error flag for one clock
// cycle while in this state and then waits
// 2 bit periods before accepting another
// transmission.
rx_countdown = 8;
recv_state = RX_DELAY_RESTART;
end
RX_RECEIVED: begin
// Successfully received a byte.
// Raises the received flag for one clock
// cycle while in this state.
recv_state = RX_IDLE;
end
endcase
// Transmit state machine
case (tx_state)
TX_IDLE: begin
if (transmit) begin
// If the transmit flag is raised in the idle
// state, start transmitting the current content
// of the tx_byte input.
tx_data = tx_byte;
// Send the initial, low pulse of 1 bit period
// to signal the start, followed by the data
tx_clk_divider = CLOCK_DIVIDE;
tx_countdown = 4;
tx_out = 0;
tx_bits_remaining = 8;
tx_state = TX_SENDING;
end
end
TX_SENDING: begin
if (!tx_countdown) begin
if (tx_bits_remaining) begin
tx_bits_remaining = tx_bits_remaining - 1;
tx_out = tx_data[0];
tx_data = {1'b0, tx_data[7:1]};
tx_countdown = 4;
tx_state = TX_SENDING;
end else begin
// Set delay to send out 2 stop bits.
tx_out = 1;
tx_countdown = 8;
tx_state = TX_DELAY_RESTART;
end
end
end
TX_DELAY_RESTART: begin
// Wait until tx_countdown reaches the end before
// we send another transmission. This covers the
// "stop bit" delay.
tx_state = tx_countdown ? TX_DELAY_RESTART : TX_IDLE;
end
endcase
end
endmodule |
module testbench;
reg clk = 1;
reg resetn = 0;
wire trap;
always #5 clk = ~clk;
initial begin
if ($test$plusargs("vcd")) begin
$dumpfile("testbench.vcd");
$dumpvars(0, testbench);
end
repeat (100) @(posedge clk);
resetn <= 1;
repeat (1000) @(posedge clk);
$finish;
end
wire mem_valid;
wire mem_instr;
reg mem_ready;
wire [31:0] mem_addr;
wire [31:0] mem_wdata;
wire [3:0] mem_wstrb;
reg [31:0] mem_rdata;
always @(posedge clk) begin
if (mem_valid && mem_ready) begin
if (mem_instr)
$display("ifetch 0x%08x: 0x%08x", mem_addr, mem_rdata);
else if (mem_wstrb)
$display("write 0x%08x: 0x%08x (wstrb=%b)", mem_addr, mem_wdata, mem_wstrb);
else
$display("read 0x%08x: 0x%08x", mem_addr, mem_rdata);
end
end
picorv32 #(
) uut (
.clk (clk ),
.resetn (resetn ),
.trap (trap ),
.mem_valid (mem_valid ),
.mem_instr (mem_instr ),
.mem_ready (mem_ready ),
.mem_addr (mem_addr ),
.mem_wdata (mem_wdata ),
.mem_wstrb (mem_wstrb ),
.mem_rdata (mem_rdata )
);
reg [31:0] memory [0:255];
initial begin
memory[0] = 32'h 3fc00093; // li x1,1020
memory[1] = 32'h 0000a023; // sw x0,0(x1)
memory[2] = 32'h 0000a103; // loop: lw x2,0(x1)
memory[3] = 32'h 00110113; // addi x2,x2,1
memory[4] = 32'h 0020a023; // sw x2,0(x1)
memory[5] = 32'h ff5ff06f; // j <loop>
end
always @(posedge clk) begin
mem_ready <= 0;
if (mem_valid && !mem_ready) begin
if (mem_addr < 1024) begin
mem_ready <= 1;
mem_rdata <= memory[mem_addr >> 2];
if (mem_wstrb[0]) memory[mem_addr >> 2][ 7: 0] <= mem_wdata[ 7: 0];
if (mem_wstrb[1]) memory[mem_addr >> 2][15: 8] <= mem_wdata[15: 8];
if (mem_wstrb[2]) memory[mem_addr >> 2][23:16] <= mem_wdata[23:16];
if (mem_wstrb[3]) memory[mem_addr >> 2][31:24] <= mem_wdata[31:24];
end
/* add memory-mapped IO here */
end
end
endmodule |
module testbench #(
parameter AXI_TEST = 0,
parameter VERBOSE = 0
);
reg clk = 1;
reg resetn = 0;
wire trap;
always #5 clk = ~clk;
initial begin
repeat (100) @(posedge clk);
resetn <= 1;
end
initial begin
if ($test$plusargs("vcd")) begin
$dumpfile("testbench.vcd");
$dumpvars(0, testbench);
end
repeat (1000000) @(posedge clk);
$display("TIMEOUT");
$finish;
end
wire trace_valid;
wire [35:0] trace_data;
integer trace_file;
initial begin
if ($test$plusargs("trace")) begin
trace_file = $fopen("testbench.trace", "w");
repeat (10) @(posedge clk);
while (!trap) begin
@(posedge clk);
if (trace_valid)
$fwrite(trace_file, "%x\n", trace_data);
end
$fclose(trace_file);
$display("Finished writing testbench.trace.");
end
end
picorv32_wrapper #(
.AXI_TEST (AXI_TEST),
.VERBOSE (VERBOSE)
) top (
.clk(clk),
.resetn(resetn),
.trap(trap),
.trace_valid(trace_valid),
.trace_data(trace_data)
);
endmodule |
module picorv32_wrapper #(
parameter AXI_TEST = 0,
parameter VERBOSE = 0
) (
input clk,
input resetn,
output trap,
output trace_valid,
output [35:0] trace_data
);
wire tests_passed;
reg [31:0] irq = 0;
reg [15:0] count_cycle = 0;
always @(posedge clk) count_cycle <= resetn ? count_cycle + 1 : 0;
always @* begin
irq = 0;
irq[4] = &count_cycle[12:0];
irq[5] = &count_cycle[15:0];
end
wire mem_axi_awvalid;
wire mem_axi_awready;
wire [31:0] mem_axi_awaddr;
wire [ 2:0] mem_axi_awprot;
wire mem_axi_wvalid;
wire mem_axi_wready;
wire [31:0] mem_axi_wdata;
wire [ 3:0] mem_axi_wstrb;
wire mem_axi_bvalid;
wire mem_axi_bready;
wire mem_axi_arvalid;
wire mem_axi_arready;
wire [31:0] mem_axi_araddr;
wire [ 2:0] mem_axi_arprot;
wire mem_axi_rvalid;
wire mem_axi_rready;
wire [31:0] mem_axi_rdata;
axi4_memory #(
.AXI_TEST (AXI_TEST),
.VERBOSE (VERBOSE)
) mem (
.clk (clk ),
.mem_axi_awvalid (mem_axi_awvalid ),
.mem_axi_awready (mem_axi_awready ),
.mem_axi_awaddr (mem_axi_awaddr ),
.mem_axi_awprot (mem_axi_awprot ),
.mem_axi_wvalid (mem_axi_wvalid ),
.mem_axi_wready (mem_axi_wready ),
.mem_axi_wdata (mem_axi_wdata ),
.mem_axi_wstrb (mem_axi_wstrb ),
.mem_axi_bvalid (mem_axi_bvalid ),
.mem_axi_bready (mem_axi_bready ),
.mem_axi_arvalid (mem_axi_arvalid ),
.mem_axi_arready (mem_axi_arready ),
.mem_axi_araddr (mem_axi_araddr ),
.mem_axi_arprot (mem_axi_arprot ),
.mem_axi_rvalid (mem_axi_rvalid ),
.mem_axi_rready (mem_axi_rready ),
.mem_axi_rdata (mem_axi_rdata ),
.tests_passed (tests_passed )
);
`ifdef RISCV_FORMAL
wire rvfi_valid;
wire [63:0] rvfi_order;
wire [31:0] rvfi_insn;
wire rvfi_trap;
wire rvfi_halt;
wire rvfi_intr;
wire [4:0] rvfi_rs1_addr;
wire [4:0] rvfi_rs2_addr;
wire [31:0] rvfi_rs1_rdata;
wire [31:0] rvfi_rs2_rdata;
wire [4:0] rvfi_rd_addr;
wire [31:0] rvfi_rd_wdata;
wire [31:0] rvfi_pc_rdata;
wire [31:0] rvfi_pc_wdata;
wire [31:0] rvfi_mem_addr;
wire [3:0] rvfi_mem_rmask;
wire [3:0] rvfi_mem_wmask;
wire [31:0] rvfi_mem_rdata;
wire [31:0] rvfi_mem_wdata;
`endif
picorv32_axi #(
`ifndef SYNTH_TEST
`ifdef SP_TEST
.ENABLE_REGS_DUALPORT(0),
`endif
`ifdef COMPRESSED_ISA
.COMPRESSED_ISA(1),
`endif
.ENABLE_MUL(1),
.ENABLE_DIV(1),
.ENABLE_IRQ(1),
.ENABLE_TRACE(1)
`endif
) uut (
.clk (clk ),
.resetn (resetn ),
.trap (trap ),
.mem_axi_awvalid(mem_axi_awvalid),
.mem_axi_awready(mem_axi_awready),
.mem_axi_awaddr (mem_axi_awaddr ),
.mem_axi_awprot (mem_axi_awprot ),
.mem_axi_wvalid (mem_axi_wvalid ),
.mem_axi_wready (mem_axi_wready ),
.mem_axi_wdata (mem_axi_wdata ),
.mem_axi_wstrb (mem_axi_wstrb ),
.mem_axi_bvalid (mem_axi_bvalid ),
.mem_axi_bready (mem_axi_bready ),
.mem_axi_arvalid(mem_axi_arvalid),
.mem_axi_arready(mem_axi_arready),
.mem_axi_araddr (mem_axi_araddr ),
.mem_axi_arprot (mem_axi_arprot ),
.mem_axi_rvalid (mem_axi_rvalid ),
.mem_axi_rready (mem_axi_rready ),
.mem_axi_rdata (mem_axi_rdata ),
.irq (irq ),
`ifdef RISCV_FORMAL
.rvfi_valid (rvfi_valid ),
.rvfi_order (rvfi_order ),
.rvfi_insn (rvfi_insn ),
.rvfi_trap (rvfi_trap ),
.rvfi_halt (rvfi_halt ),
.rvfi_intr (rvfi_intr ),
.rvfi_rs1_addr (rvfi_rs1_addr ),
.rvfi_rs2_addr (rvfi_rs2_addr ),
.rvfi_rs1_rdata (rvfi_rs1_rdata ),
.rvfi_rs2_rdata (rvfi_rs2_rdata ),
.rvfi_rd_addr (rvfi_rd_addr ),
.rvfi_rd_wdata (rvfi_rd_wdata ),
.rvfi_pc_rdata (rvfi_pc_rdata ),
.rvfi_pc_wdata (rvfi_pc_wdata ),
.rvfi_mem_addr (rvfi_mem_addr ),
.rvfi_mem_rmask (rvfi_mem_rmask ),
.rvfi_mem_wmask (rvfi_mem_wmask ),
.rvfi_mem_rdata (rvfi_mem_rdata ),
.rvfi_mem_wdata (rvfi_mem_wdata ),
`endif
.trace_valid (trace_valid ),
.trace_data (trace_data )
);
`ifdef RISCV_FORMAL
picorv32_rvfimon rvfi_monitor (
.clock (clk ),
.reset (!resetn ),
.rvfi_valid (rvfi_valid ),
.rvfi_order (rvfi_order ),
.rvfi_insn (rvfi_insn ),
.rvfi_trap (rvfi_trap ),
.rvfi_halt (rvfi_halt ),
.rvfi_intr (rvfi_intr ),
.rvfi_rs1_addr (rvfi_rs1_addr ),
.rvfi_rs2_addr (rvfi_rs2_addr ),
.rvfi_rs1_rdata (rvfi_rs1_rdata),
.rvfi_rs2_rdata (rvfi_rs2_rdata),
.rvfi_rd_addr (rvfi_rd_addr ),
.rvfi_rd_wdata (rvfi_rd_wdata ),
.rvfi_pc_rdata (rvfi_pc_rdata ),
.rvfi_pc_wdata (rvfi_pc_wdata ),
.rvfi_mem_addr (rvfi_mem_addr ),
.rvfi_mem_rmask (rvfi_mem_rmask),
.rvfi_mem_wmask (rvfi_mem_wmask),
.rvfi_mem_rdata (rvfi_mem_rdata),
.rvfi_mem_wdata (rvfi_mem_wdata)
);
`endif
reg [1023:0] firmware_file;
initial begin
if (!$value$plusargs("firmware=%s", firmware_file))
firmware_file = "firmware/firmware.hex";
$readmemh(firmware_file, mem.memory);
end
integer cycle_counter;
always @(posedge clk) begin
cycle_counter <= resetn ? cycle_counter + 1 : 0;
if (resetn && trap) begin
`ifndef VERILATOR
repeat (10) @(posedge clk);
`endif
$display("TRAP after %1d clock cycles", cycle_counter);
if (tests_passed) begin
$display("ALL TESTS PASSED.");
$finish;
end else begin
$display("ERROR!");
if ($test$plusargs("noerror"))
$finish;
$stop;
end
end
end
endmodule |
module axi4_memory #(
parameter AXI_TEST = 0,
parameter VERBOSE = 0
) (
/* verilator lint_off MULTIDRIVEN */
input clk,
input mem_axi_awvalid,
output reg mem_axi_awready,
input [31:0] mem_axi_awaddr,
input [ 2:0] mem_axi_awprot,
input mem_axi_wvalid,
output reg mem_axi_wready,
input [31:0] mem_axi_wdata,
input [ 3:0] mem_axi_wstrb,
output reg mem_axi_bvalid,
input mem_axi_bready,
input mem_axi_arvalid,
output reg mem_axi_arready,
input [31:0] mem_axi_araddr,
input [ 2:0] mem_axi_arprot,
output reg mem_axi_rvalid,
input mem_axi_rready,
output reg [31:0] mem_axi_rdata,
output reg tests_passed
);
reg [31:0] memory [0:128*1024/4-1] /* verilator public */;
reg verbose;
initial verbose = $test$plusargs("verbose") || VERBOSE;
reg axi_test;
initial axi_test = $test$plusargs("axi_test") || AXI_TEST;
initial begin
mem_axi_awready = 0;
mem_axi_wready = 0;
mem_axi_bvalid = 0;
mem_axi_arready = 0;
mem_axi_rvalid = 0;
tests_passed = 0;
end
reg [63:0] xorshift64_state = 64'd88172645463325252;
task xorshift64_next;
begin
// see page 4 of Marsaglia, George (July 2003). "Xorshift RNGs". Journal of Statistical Software 8 (14).
xorshift64_state = xorshift64_state ^ (xorshift64_state << 13);
xorshift64_state = xorshift64_state ^ (xorshift64_state >> 7);
xorshift64_state = xorshift64_state ^ (xorshift64_state << 17);
end
endtask
reg [2:0] fast_axi_transaction = ~0;
reg [4:0] async_axi_transaction = ~0;
reg [4:0] delay_axi_transaction = 0;
always @(posedge clk) begin
if (axi_test) begin
xorshift64_next;
{fast_axi_transaction, async_axi_transaction, delay_axi_transaction} <= xorshift64_state;
end
end
reg latched_raddr_en = 0;
reg latched_waddr_en = 0;
reg latched_wdata_en = 0;
reg fast_raddr = 0;
reg fast_waddr = 0;
reg fast_wdata = 0;
reg [31:0] latched_raddr;
reg [31:0] latched_waddr;
reg [31:0] latched_wdata;
reg [ 3:0] latched_wstrb;
reg latched_rinsn;
task handle_axi_arvalid; begin
mem_axi_arready <= 1;
latched_raddr = mem_axi_araddr;
latched_rinsn = mem_axi_arprot[2];
latched_raddr_en = 1;
fast_raddr <= 1;
end endtask
task handle_axi_awvalid; begin
mem_axi_awready <= 1;
latched_waddr = mem_axi_awaddr;
latched_waddr_en = 1;
fast_waddr <= 1;
end endtask
task handle_axi_wvalid; begin
mem_axi_wready <= 1;
latched_wdata = mem_axi_wdata;
latched_wstrb = mem_axi_wstrb;
latched_wdata_en = 1;
fast_wdata <= 1;
end endtask
task handle_axi_rvalid; begin
if (verbose)
$display("RD: ADDR=%08x DATA=%08x%s", latched_raddr, memory[latched_raddr >> 2], latched_rinsn ? " INSN" : "");
if (latched_raddr < 128*1024) begin
mem_axi_rdata <= memory[latched_raddr >> 2];
mem_axi_rvalid <= 1;
latched_raddr_en = 0;
end else begin
$display("OUT-OF-BOUNDS MEMORY READ FROM %08x", latched_raddr);
$finish;
end
end endtask
task handle_axi_bvalid; begin
if (verbose)
$display("WR: ADDR=%08x DATA=%08x STRB=%04b", latched_waddr, latched_wdata, latched_wstrb);
if (latched_waddr < 128*1024) begin
if (latched_wstrb[0]) memory[latched_waddr >> 2][ 7: 0] <= latched_wdata[ 7: 0];
if (latched_wstrb[1]) memory[latched_waddr >> 2][15: 8] <= latched_wdata[15: 8];
if (latched_wstrb[2]) memory[latched_waddr >> 2][23:16] <= latched_wdata[23:16];
if (latched_wstrb[3]) memory[latched_waddr >> 2][31:24] <= latched_wdata[31:24];
end else
if (latched_waddr == 32'h1000_0000) begin
if (verbose) begin
if (32 <= latched_wdata && latched_wdata < 128)
$display("OUT: '%c'", latched_wdata[7:0]);
else
$display("OUT: %3d", latched_wdata);
end else begin
$write("%c", latched_wdata[7:0]);
`ifndef VERILATOR
$fflush();
`endif
end
end else
if (latched_waddr == 32'h2000_0000) begin
if (latched_wdata == 123456789)
tests_passed = 1;
end else begin
$display("OUT-OF-BOUNDS MEMORY WRITE TO %08x", latched_waddr);
$finish;
end
mem_axi_bvalid <= 1;
latched_waddr_en = 0;
latched_wdata_en = 0;
end endtask
always @(negedge clk) begin
if (mem_axi_arvalid && !(latched_raddr_en || fast_raddr) && async_axi_transaction[0]) handle_axi_arvalid;
if (mem_axi_awvalid && !(latched_waddr_en || fast_waddr) && async_axi_transaction[1]) handle_axi_awvalid;
if (mem_axi_wvalid && !(latched_wdata_en || fast_wdata) && async_axi_transaction[2]) handle_axi_wvalid;
if (!mem_axi_rvalid && latched_raddr_en && async_axi_transaction[3]) handle_axi_rvalid;
if (!mem_axi_bvalid && latched_waddr_en && latched_wdata_en && async_axi_transaction[4]) handle_axi_bvalid;
end
always @(posedge clk) begin
mem_axi_arready <= 0;
mem_axi_awready <= 0;
mem_axi_wready <= 0;
fast_raddr <= 0;
fast_waddr <= 0;
fast_wdata <= 0;
if (mem_axi_rvalid && mem_axi_rready) begin
mem_axi_rvalid <= 0;
end
if (mem_axi_bvalid && mem_axi_bready) begin
mem_axi_bvalid <= 0;
end
if (mem_axi_arvalid && mem_axi_arready && !fast_raddr) begin
latched_raddr = mem_axi_araddr;
latched_rinsn = mem_axi_arprot[2];
latched_raddr_en = 1;
end
if (mem_axi_awvalid && mem_axi_awready && !fast_waddr) begin
latched_waddr = mem_axi_awaddr;
latched_waddr_en = 1;
end
if (mem_axi_wvalid && mem_axi_wready && !fast_wdata) begin
latched_wdata = mem_axi_wdata;
latched_wstrb = mem_axi_wstrb;
latched_wdata_en = 1;
end
if (mem_axi_arvalid && !(latched_raddr_en || fast_raddr) && !delay_axi_transaction[0]) handle_axi_arvalid;
if (mem_axi_awvalid && !(latched_waddr_en || fast_waddr) && !delay_axi_transaction[1]) handle_axi_awvalid;
if (mem_axi_wvalid && !(latched_wdata_en || fast_wdata) && !delay_axi_transaction[2]) handle_axi_wvalid;
if (!mem_axi_rvalid && latched_raddr_en && !delay_axi_transaction[3]) handle_axi_rvalid;
if (!mem_axi_bvalid && latched_waddr_en && latched_wdata_en && !delay_axi_transaction[4]) handle_axi_bvalid;
end
endmodule |
module picorv32_wrapper #(
parameter VERBOSE = 0
) (
input wb_clk,
input wb_rst,
output trap,
output trace_valid,
output [35:0] trace_data
);
wire tests_passed;
reg [31:0] irq = 0;
wire mem_instr;
reg [15:0] count_cycle = 0;
always @(posedge wb_clk) count_cycle <= !wb_rst ? count_cycle + 1 : 0;
always @* begin
irq = 0;
irq[4] = &count_cycle[12:0];
irq[5] = &count_cycle[15:0];
end
wire [31:0] wb_m2s_adr;
wire [31:0] wb_m2s_dat;
wire [3:0] wb_m2s_sel;
wire wb_m2s_we;
wire wb_m2s_cyc;
wire wb_m2s_stb;
wire [31:0] wb_s2m_dat;
wire wb_s2m_ack;
wb_ram #(
.depth (128*1024),
.VERBOSE (VERBOSE)
) ram ( // Wishbone interface
.wb_clk_i(wb_clk),
.wb_rst_i(wb_rst),
.wb_adr_i(wb_m2s_adr),
.wb_dat_i(wb_m2s_dat),
.wb_stb_i(wb_m2s_stb),
.wb_cyc_i(wb_m2s_cyc),
.wb_dat_o(wb_s2m_dat),
.wb_ack_o(wb_s2m_ack),
.wb_sel_i(wb_m2s_sel),
.wb_we_i(wb_m2s_we),
.mem_instr(mem_instr),
.tests_passed(tests_passed)
);
picorv32_wb #(
`ifndef SYNTH_TEST
`ifdef SP_TEST
.ENABLE_REGS_DUALPORT(0),
`endif
`ifdef COMPRESSED_ISA
.COMPRESSED_ISA(1),
`endif
.ENABLE_MUL(1),
.ENABLE_DIV(1),
.ENABLE_IRQ(1),
.ENABLE_TRACE(1)
`endif
) uut (
.trap (trap),
.irq (irq),
.trace_valid (trace_valid),
.trace_data (trace_data),
.mem_instr(mem_instr),
.wb_clk_i(wb_clk),
.wb_rst_i(wb_rst),
.wbm_adr_o(wb_m2s_adr),
.wbm_dat_i(wb_s2m_dat),
.wbm_stb_o(wb_m2s_stb),
.wbm_ack_i(wb_s2m_ack),
.wbm_cyc_o(wb_m2s_cyc),
.wbm_dat_o(wb_m2s_dat),
.wbm_we_o(wb_m2s_we),
.wbm_sel_o(wb_m2s_sel)
);
reg [1023:0] firmware_file;
initial begin
if (!$value$plusargs("firmware=%s", firmware_file))
firmware_file = "firmware/firmware.hex";
$readmemh(firmware_file, ram.mem);
end
integer cycle_counter;
always @(posedge wb_clk) begin
cycle_counter <= !wb_rst ? cycle_counter + 1 : 0;
if (!wb_rst && trap) begin
`ifndef VERILATOR
repeat (10) @(posedge wb_clk);
`endif
$display("TRAP after %1d clock cycles", cycle_counter);
if (tests_passed) begin
$display("ALL TESTS PASSED.");
$finish;
end else begin
$display("ERROR!");
if ($test$plusargs("noerror"))
$finish;
$stop;
end
end
end
endmodule |
module wb_ram #(
parameter depth = 256,
parameter memfile = "",
parameter VERBOSE = 0
) (
input wb_clk_i,
input wb_rst_i,
input [31:0] wb_adr_i,
input [31:0] wb_dat_i,
input [3:0] wb_sel_i,
input wb_we_i,
input wb_cyc_i,
input wb_stb_i,
output reg wb_ack_o,
output reg [31:0] wb_dat_o,
input mem_instr,
output reg tests_passed
);
reg verbose;
initial verbose = $test$plusargs("verbose") || VERBOSE;
initial tests_passed = 0;
reg [31:0] adr_r;
wire valid = wb_cyc_i & wb_stb_i;
always @(posedge wb_clk_i) begin
adr_r <= wb_adr_i;
// Ack generation
wb_ack_o <= valid & !wb_ack_o;
if (wb_rst_i)
begin
adr_r <= {32{1'b0}};
wb_ack_o <= 1'b0;
end
end
wire ram_we = wb_we_i & valid & wb_ack_o;
wire [31:0] waddr = adr_r[31:2];
wire [31:0] raddr = wb_adr_i[31:2];
wire [3:0] we = {4{ram_we}} & wb_sel_i;
wire [$clog2(depth/4)-1:0] raddr2 = raddr[$clog2(depth/4)-1:0];
wire [$clog2(depth/4)-1:0] waddr2 = waddr[$clog2(depth/4)-1:0];
reg [31:0] mem [0:depth/4-1] /* verilator public */;
always @(posedge wb_clk_i) begin
if (ram_we) begin
if (verbose)
$display("WR: ADDR=%08x DATA=%08x STRB=%04b",
adr_r, wb_dat_i, we);
if (adr_r[31:0] == 32'h1000_0000)
if (verbose) begin
if (32 <= wb_dat_i[7:0] && wb_dat_i[7:0] < 128)
$display("OUT: '%c'", wb_dat_i[7:0]);
else
$display("OUT: %3d", wb_dat_i[7:0]);
end else begin
$write("%c", wb_dat_i[7:0]);
`ifndef VERILATOR
$fflush();
`endif
end
else
if (adr_r[31:0] == 32'h2000_0000)
if (wb_dat_i[31:0] == 123456789)
tests_passed = 1;
end
end
always @(posedge wb_clk_i) begin
if (waddr2 < 128 * 1024 / 4) begin
if (we[0])
mem[waddr2][7:0] <= wb_dat_i[7:0];
if (we[1])
mem[waddr2][15:8] <= wb_dat_i[15:8];
if (we[2])
mem[waddr2][23:16] <= wb_dat_i[23:16];
if (we[3])
mem[waddr2][31:24] <= wb_dat_i[31:24];
end
if (valid & wb_ack_o & !ram_we)
if (verbose)
$display("RD: ADDR=%08x DATA=%08x%s", adr_r, mem[raddr2], mem_instr ? " INSN" : "");
wb_dat_o <= mem[raddr2];
end
initial begin
if (memfile != "")
$readmemh(memfile, mem);
end
endmodule |
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