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module enigma_top
(input i_Clk, // Main Clock
input i_UART_RX, // UART RX Data
output o_UART_TX, // UART TX Data
output o_LED_1,
output o_LED_2,
output o_LED_3,
output o_LED_4,
// Segment1 is upper digit, Segment2 is lower digit
output o_Segment1_A,
output o_Segment1_B,
output o_Segment1_C,
output o_Segment1_D,
output o_Segment1_E,
output o_Segment1_F,
output o_Segment1_G,
//
output o_Segment2_A,
output o_Segment2_B,
output o_Segment2_C,
output o_Segment2_D,
output o_Segment2_E,
output o_Segment2_F,
output o_Segment2_G
);
wire w_RX_DV;
wire [7:0] w_RX_Byte;
wire w_TX_Active, w_TX_Serial;
wire o_ready;
wire o_valid;
wire [7:0] outputData;
// 25,000,000 / 115,200 = 217
uart_rx #(.CLKS_PER_BIT(217)) UART_RX_Inst
(.i_Clock(i_Clk),
.i_Rx_Serial(i_UART_RX),
.o_Rx_DV(w_RX_DV),
.o_Rx_Byte(w_RX_Byte));
state_machine st(.i_clock(i_Clk),.i_ready(w_RX_DV),.i_inputData(w_RX_Byte),.o_ready(o_ready),.o_outputData(outputData),.o_valid(o_valid));
uart_tx #(.CLKS_PER_BIT(217)) UART_TX_Inst
(.i_Clock(i_Clk),
.i_Tx_DV(o_ready),
.i_Tx_Byte(outputData),
.o_Tx_Active(w_TX_Active),
.o_Tx_Serial(w_TX_Serial),
.o_Tx_Done());
// Drive UART line high when transmitter is not active
assign o_UART_TX = w_TX_Active ? w_TX_Serial : 1'b1;
hex_to_7seg upper_digit
(.i_Clk(i_Clk),
.i_Value(outputData[7:4]),
.o_Segment_A(o_Segment1_A),
.o_Segment_B(o_Segment1_B),
.o_Segment_C(o_Segment1_C),
.o_Segment_D(o_Segment1_D),
.o_Segment_E(o_Segment1_E),
.o_Segment_F(o_Segment1_F),
.o_Segment_G(o_Segment1_G));
hex_to_7seg lower_digit
(.i_Clk(i_Clk),
.i_Value(outputData[3:0]),
.o_Segment_A(o_Segment2_A),
.o_Segment_B(o_Segment2_B),
.o_Segment_C(o_Segment2_C),
.o_Segment_D(o_Segment2_D),
.o_Segment_E(o_Segment2_E),
.o_Segment_F(o_Segment2_F),
.o_Segment_G(o_Segment2_G));
assign o_LED_1 = 1'b0;
assign o_LED_2 = 1'b0;
assign o_LED_3 = o_valid;
assign o_LED_4 = 1'b0;
endmodule |
module test();
reg i_ready = 0;
reg [7:0] inputData;
reg r_Clock = 0;
wire o_ready;
wire [7:0] outputData;
integer i;
state_machine st(.i_clock(r_Clock),.i_ready(i_ready),.i_inputData(inputData),.o_ready(o_ready),.o_outputData(outputData));
always
#(5) r_Clock <= !r_Clock;
always @(posedge o_ready)
begin
$display("data is [%c]",outputData);
end
initial
begin
$dumpfile("enigma.vcd");
$dumpvars(0,test);
inputData = "A";
for (i = 0; i < 20; i = i + 1)
begin
#10
i_ready = 1;
#30
i_ready = 0;
end
#260
$finish;
end
endmodule |
module rotorEncode #(parameter REVERSE = 0) (code, rotor_type, val);
input [4:0] code;
output reg [4:0] val;
input [2:0] rotor_type;
parameter MEM_INIT_FILE = "rotors.mem";
reg [4:0] rotor_data[0:415];
initial
if (MEM_INIT_FILE != "")
$readmemh(MEM_INIT_FILE, rotor_data);
always @*
val = rotor_data[((REVERSE) ? 208 : 0) + rotor_type*26 + code];
endmodule |
module hex_to_7seg
(
input i_Clk,
input [3:0] i_Value,
output o_Segment_A,
output o_Segment_B,
output o_Segment_C,
output o_Segment_D,
output o_Segment_E,
output o_Segment_F,
output o_Segment_G
);
reg [6:0] out = 7'b0000000;
always @(posedge i_Clk)
begin
case (i_Value)
4'b0000 : out <= 7'b0000001;
4'b0001 : out <= 7'b1001111;
4'b0010 : out <= 7'b0010010;
4'b0011 : out <= 7'b0000110;
4'b0100 : out <= 7'b1001100;
4'b0101 : out <= 7'b0100100;
4'b0110 : out <= 7'b0100000;
4'b0111 : out <= 7'b0001111;
4'b1000 : out <= 7'b0000000;
4'b1001 : out <= 7'b0000100;
4'b1010 : out <= 7'b0001000;
4'b1011 : out <= 7'b1100000;
4'b1100 : out <= 7'b0110001;
4'b1101 : out <= 7'b1000010;
4'b1110 : out <= 7'b0110000;
4'b1111 : out <= 7'b0111000;
endcase
end
assign o_Segment_A = out[6];
assign o_Segment_B = out[5];
assign o_Segment_C = out[4];
assign o_Segment_D = out[3];
assign o_Segment_E = out[2];
assign o_Segment_F = out[1];
assign o_Segment_G = out[0];
endmodule |
module decodeASCII(code, ascii);
input [4:0] code;
output [7:0] ascii;
assign ascii = 8'h41 + code;
endmodule |
module uart_rx
(
input i_Clock,
input i_Rx_Serial,
output o_Rx_DV,
output [7:0] o_Rx_Byte
);
parameter CLKS_PER_BIT = 87;
parameter s_IDLE = 3'b000;
parameter s_RX_START_BIT = 3'b001;
parameter s_RX_DATA_BITS = 3'b010;
parameter s_RX_STOP_BIT = 3'b011;
parameter s_CLEANUP = 3'b100;
reg r_Rx_Data_R = 1'b1;
reg r_Rx_Data = 1'b1;
reg [7:0] r_Clock_Count = 0;
reg [2:0] r_Bit_Index = 0; //8 bits total
reg [7:0] r_Rx_Byte = 0;
reg r_Rx_DV = 0;
reg [2:0] r_SM_Main = 0;
// Purpose: Double-register the incoming data.
// This allows it to be used in the UART RX Clock Domain.
// (It removes problems caused by metastability)
always @(posedge i_Clock)
begin
r_Rx_Data_R <= i_Rx_Serial;
r_Rx_Data <= r_Rx_Data_R;
end
// Purpose: Control RX state machine
always @(posedge i_Clock)
begin
case (r_SM_Main)
s_IDLE :
begin
r_Rx_DV <= 1'b0;
r_Clock_Count <= 0;
r_Bit_Index <= 0;
if (r_Rx_Data == 1'b0) // Start bit detected
r_SM_Main <= s_RX_START_BIT;
else
r_SM_Main <= s_IDLE;
end
// Check middle of start bit to make sure it's still low
s_RX_START_BIT :
begin
if (r_Clock_Count == (CLKS_PER_BIT-1)/2)
begin
if (r_Rx_Data == 1'b0)
begin
r_Clock_Count <= 0; // reset counter, found the middle
r_SM_Main <= s_RX_DATA_BITS;
end
else
r_SM_Main <= s_IDLE;
end
else
begin
r_Clock_Count <= r_Clock_Count + 1;
r_SM_Main <= s_RX_START_BIT;
end
end // case: s_RX_START_BIT
// Wait CLKS_PER_BIT-1 clock cycles to sample serial data
s_RX_DATA_BITS :
begin
if (r_Clock_Count < CLKS_PER_BIT-1)
begin
r_Clock_Count <= r_Clock_Count + 1;
r_SM_Main <= s_RX_DATA_BITS;
end
else
begin
r_Clock_Count <= 0;
r_Rx_Byte[r_Bit_Index] <= r_Rx_Data;
// Check if we have received all bits
if (r_Bit_Index < 7)
begin
r_Bit_Index <= r_Bit_Index + 1;
r_SM_Main <= s_RX_DATA_BITS;
end
else
begin
r_Bit_Index <= 0;
r_SM_Main <= s_RX_STOP_BIT;
end
end
end // case: s_RX_DATA_BITS
// Receive Stop bit. Stop bit = 1
s_RX_STOP_BIT :
begin
// Wait CLKS_PER_BIT-1 clock cycles for Stop bit to finish
if (r_Clock_Count < CLKS_PER_BIT-1)
begin
r_Clock_Count <= r_Clock_Count + 1;
r_SM_Main <= s_RX_STOP_BIT;
end
else
begin
r_Rx_DV <= 1'b1;
r_Clock_Count <= 0;
r_SM_Main <= s_CLEANUP;
end
end // case: s_RX_STOP_BIT
// Stay here 1 clock
s_CLEANUP :
begin
r_SM_Main <= s_IDLE;
r_Rx_DV <= 1'b0;
end
default :
r_SM_Main <= s_IDLE;
endcase
end
assign o_Rx_DV = r_Rx_DV;
assign o_Rx_Byte = r_Rx_Byte;
endmodule // uart_rx |
module encodeASCII(ascii, code, valid);
input [7:0] ascii;
output [4:0] code;
output valid;
assign valid = ((ascii < 8'h41 || ascii > 8'h5A) && (ascii < 8'h61 || ascii > 8'h7A)) ? 0 : 1;
assign code = (ascii > 8'h5A) ? ascii - 8'h61 : ascii - 8'h41;
endmodule |
module rotor (
input clock,
output reg [4:0] rotor1,
output reg [4:0] rotor2,
output reg [4:0] rotor3,
input reset,
input rotate,
input [2:0] rotor_type_2,
input [2:0] rotor_type_3,
input [4:0] rotor_start_1,
input [4:0] rotor_start_2,
input [4:0] rotor_start_3
);
wire knock1;
wire knock2;
reg prev_rotate = 1'b0;
reg prev_knock1 = 1'b0;
reg prev_knock2 = 1'b0;
checkKnockpoints checker3(.position(rotor3), .knockpoint(knock1), .rotor_type(rotor_type_3));
checkKnockpoints checker2(.position(rotor2), .knockpoint(knock2), .rotor_type(rotor_type_2));
always @(posedge clock)
begin
if (reset)
begin
rotor1 <= rotor_start_1;
rotor2 <= rotor_start_2;
rotor3 <= rotor_start_3;
prev_rotate <= 0;
prev_knock1 <= 0;
prev_knock2 <= 0;
end
else
begin
if ((prev_rotate==0) && (rotate==1)) rotor3 <= (rotor3 == 25) ? 0 : rotor3 + 1;
if ((prev_knock1==0) && (knock1==1)) rotor2 <= (rotor2 == 25) ? 0 : rotor2 + 1;
if ((prev_knock2==0) && (knock2==1)) rotor1 <= (rotor1 == 25) ? 0 : rotor1 + 1;
prev_rotate <= rotate;
prev_knock1 <= knock1;
prev_knock2 <= knock2;
end
end
endmodule |
module state_machine(
input i_clock,
input i_ready,
input [7:0] i_inputData,
output reg o_ready,
output reg [7:0] o_outputData,
output reg o_valid
);
reg [2:0] rotor_type_3 = 3'b010;
reg [2:0] rotor_type_2 = 3'b001;
reg [2:0] rotor_type_1 = 3'b000;
reg [4:0] rotor_start_3 = 5'b00000;
reg [4:0] rotor_start_2 = 5'b00000;
reg [4:0] rotor_start_1 = 5'b00000;
reg [4:0] ring_position_3 = 5'b00000;
reg [4:0] ring_position_2 = 5'b00000;
reg [4:0] ring_position_1 = 5'b00000;
reg reflector_type = 1'b0;
wire [4:0] rotor1;
wire [4:0] rotor2;
wire [4:0] rotor3;
reg reset = 1'b1;
reg rotate = 1'b0;
wire [4:0] value0;
wire [4:0] value1;
wire [4:0] value2;
wire [4:0] value3;
wire [4:0] value4;
wire [4:0] value5;
wire [4:0] value6;
wire [4:0] value7;
wire [4:0] value8;
parameter STATE_RESET = 2'b00;
parameter STATE_IDLE = 2'b01;
parameter STATE_ENCODE = 2'b10;
parameter STATE_CHECKKEY= 2'b11;
reg [1:0] state = STATE_RESET;
wire [4:0] inputCode;
wire valid;
wire [7:0] final_ascii;
encodeASCII encode(.ascii(i_inputData), .code(inputCode), .valid(valid));
rotor rotorcontrol(.clock(i_clock),.rotor1(rotor1),.rotor2(rotor2),.rotor3(rotor3),.reset(reset),.rotate(rotate),
.rotor_type_2(rotor_type_2),.rotor_type_3(rotor_type_3),
.rotor_start_1(rotor_start_1),.rotor_start_2(rotor_start_2),.rotor_start_3(rotor_start_3)
);
plugboardEncode plugboard(.code(inputCode),.val(value0));
encode #(.REVERSE(0)) rot3Encode(.inputValue(value0),.rotor(rotor3),.outputValue(value1),.rotor_type(rotor_type_3),.ring_position(ring_position_3));
encode #(.REVERSE(0)) rot2Encode(.inputValue(value1),.rotor(rotor2),.outputValue(value2),.rotor_type(rotor_type_2),.ring_position(ring_position_2));
encode #(.REVERSE(0)) rot1Encode(.inputValue(value2),.rotor(rotor1),.outputValue(value3),.rotor_type(rotor_type_1),.ring_position(ring_position_1));
reflectorEncode reflector(.code(value3),.val(value4),.reflector_type(reflector_type));
encode #(.REVERSE(1)) rot1EncodeRev(.inputValue(value4),.rotor(rotor1),.outputValue(value5),.rotor_type(rotor_type_1),.ring_position(ring_position_1));
encode #(.REVERSE(1)) rot2EncodeRev(.inputValue(value5),.rotor(rotor2),.outputValue(value6),.rotor_type(rotor_type_2),.ring_position(ring_position_2));
encode #(.REVERSE(1)) rot3EncodeRev(.inputValue(value6),.rotor(rotor3),.outputValue(value7),.rotor_type(rotor_type_3),.ring_position(ring_position_3));
plugboardEncode plugboard2(.code(value7),.val(value8));
decodeASCII decode(.code(value8), .ascii(final_ascii));
always @(posedge i_clock)
begin
case (state)
STATE_RESET :
begin
reset <= 1'b0;
state <= STATE_IDLE;
o_ready <= 1'b0;
o_outputData <= 8'b00000000;
o_valid <= 1'b0;
rotate <= 1'b1;
end
STATE_IDLE :
begin
o_ready <= 1'b0;
state <= i_ready ? STATE_CHECKKEY : STATE_IDLE;
o_valid <= valid;
rotate <= 1'b0;
end
STATE_CHECKKEY :
begin
o_ready <= 1'b0;
rotate <= 1'b0;
if (valid)
begin
state <= STATE_ENCODE;
end
else
begin
case(i_inputData)
8'd27:
begin
reset <= 1'b1;
state <= STATE_RESET;
o_ready <= 1'b1;
o_outputData <= 8'd10;
end
8'd13:
begin
state <= STATE_IDLE;
o_ready <= 1'b1;
o_outputData <= 8'd13;
end
default:
state <= STATE_IDLE;
endcase
end
o_valid <= valid;
end
STATE_ENCODE :
begin
rotate <= 1'b1;
o_ready <= 1'b1;
o_outputData <= final_ascii;
state <= STATE_IDLE;
end
endcase
end
endmodule |
module reflectorEncode (code, val, reflector_type);
input [4:0] code;
output reg [4:0] val;
input reflector_type;
always @*
begin
if (reflector_type == 1'b0)
begin
// Reflector B
case (code)
0 : val = "Y" - 8'h41;
1 : val = "R" - 8'h41;
2 : val = "U" - 8'h41;
3 : val = "H" - 8'h41;
4 : val = "Q" - 8'h41;
5 : val = "S" - 8'h41;
6 : val = "L" - 8'h41;
7 : val = "D" - 8'h41;
8 : val = "P" - 8'h41;
9 : val = "X" - 8'h41;
10: val = "N" - 8'h41;
11: val = "G" - 8'h41;
12: val = "O" - 8'h41;
13: val = "K" - 8'h41;
14: val = "M" - 8'h41;
15: val = "I" - 8'h41;
16: val = "E" - 8'h41;
17: val = "B" - 8'h41;
18: val = "F" - 8'h41;
19: val = "Z" - 8'h41;
20: val = "C" - 8'h41;
21: val = "W" - 8'h41;
22: val = "V" - 8'h41;
23: val = "J" - 8'h41;
24: val = "A" - 8'h41;
25: val = "T" - 8'h41;
endcase
end
else
begin
// Reflector C
case (code)
0 : val = "F" - 8'h41;
1 : val = "V" - 8'h41;
2 : val = "P" - 8'h41;
3 : val = "J" - 8'h41;
4 : val = "I" - 8'h41;
5 : val = "A" - 8'h41;
6 : val = "O" - 8'h41;
7 : val = "Y" - 8'h41;
8 : val = "E" - 8'h41;
9 : val = "D" - 8'h41;
10: val = "R" - 8'h41;
11: val = "Z" - 8'h41;
12: val = "X" - 8'h41;
13: val = "W" - 8'h41;
14: val = "G" - 8'h41;
15: val = "C" - 8'h41;
16: val = "T" - 8'h41;
17: val = "K" - 8'h41;
18: val = "U" - 8'h41;
19: val = "Q" - 8'h41;
20: val = "S" - 8'h41;
21: val = "B" - 8'h41;
22: val = "N" - 8'h41;
23: val = "M" - 8'h41;
24: val = "H" - 8'h41;
25: val = "L" - 8'h41;
endcase
end
end
endmodule |
module plugboardEncode(input [4:0] code, output [4:0] val);
assign val = code;
endmodule |
module checkKnockpoints (position, knockpoint, rotor_type);
input [4:0] position;
output reg knockpoint;
input [2:0] rotor_type;
always @*
begin
knockpoint = 0;
case(rotor_type)
0 : if (position==16+1) knockpoint = 1;
1 : if (position== 4+1) knockpoint = 1;
2 : if (position==21+1) knockpoint = 1;
3 : if (position== 9+1) knockpoint = 1;
//4 : if (position==25+1) knockpoint = 1;
4 : if (position==0) knockpoint = 1;
5 : if (position==12+1) knockpoint = 1; else if(position==0) knockpoint = 1;
6 : if (position==12+1) knockpoint = 1; else if(position==0) knockpoint = 1;
7 : if (position==12+1) knockpoint = 1; else if(position==0) knockpoint = 1;
endcase
end
endmodule |
module uart_tx
(
input i_Clock,
input i_Tx_DV,
input [7:0] i_Tx_Byte,
output o_Tx_Active,
output reg o_Tx_Serial,
output o_Tx_Done
);
parameter CLKS_PER_BIT = 87;
parameter s_IDLE = 3'b000;
parameter s_TX_START_BIT = 3'b001;
parameter s_TX_DATA_BITS = 3'b010;
parameter s_TX_STOP_BIT = 3'b011;
parameter s_CLEANUP = 3'b100;
reg [2:0] r_SM_Main = 3'b000;
reg [7:0] r_Clock_Count = 8'b00000000;
reg [2:0] r_Bit_Index = 3'b000;
reg [7:0] r_Tx_Data = 8'b00000000;
reg r_Tx_Done = 0;
reg r_Tx_Active = 0;
always @(posedge i_Clock)
begin
case (r_SM_Main)
s_IDLE :
begin
o_Tx_Serial <= 1'b1; // Drive Line High for Idle
r_Tx_Done <= 1'b0;
r_Clock_Count <= 8'b00000000;
r_Bit_Index <= 3'b000;
if (i_Tx_DV == 1'b1)
begin
r_Tx_Active <= 1'b1;
r_Tx_Data <= i_Tx_Byte;
r_SM_Main <= s_TX_START_BIT;
end
else
r_SM_Main <= s_IDLE;
end // case: s_IDLE
// Send out Start Bit. Start bit = 0
s_TX_START_BIT :
begin
o_Tx_Serial <= 1'b0;
// Wait CLKS_PER_BIT-1 clock cycles for start bit to finish
if (r_Clock_Count < CLKS_PER_BIT-1)
begin
r_Clock_Count <= r_Clock_Count + 1;
r_SM_Main <= s_TX_START_BIT;
end
else
begin
r_Clock_Count <= 0;
r_SM_Main <= s_TX_DATA_BITS;
end
end // case: s_TX_START_BIT
// Wait CLKS_PER_BIT-1 clock cycles for data bits to finish
s_TX_DATA_BITS :
begin
o_Tx_Serial <= r_Tx_Data[r_Bit_Index];
if (r_Clock_Count < CLKS_PER_BIT-1)
begin
r_Clock_Count <= r_Clock_Count + 1;
r_SM_Main <= s_TX_DATA_BITS;
end
else
begin
r_Clock_Count <= 0;
// Check if we have sent out all bits
if (r_Bit_Index < 7)
begin
r_Bit_Index <= r_Bit_Index + 1;
r_SM_Main <= s_TX_DATA_BITS;
end
else
begin
r_Bit_Index <= 0;
r_SM_Main <= s_TX_STOP_BIT;
end
end
end // case: s_TX_DATA_BITS
// Send out Stop bit. Stop bit = 1
s_TX_STOP_BIT :
begin
o_Tx_Serial <= 1'b1;
// Wait CLKS_PER_BIT-1 clock cycles for Stop bit to finish
if (r_Clock_Count < CLKS_PER_BIT-1)
begin
r_Clock_Count <= r_Clock_Count + 1;
r_SM_Main <= s_TX_STOP_BIT;
end
else
begin
r_Tx_Done <= 1'b1;
r_Clock_Count <= 0;
r_SM_Main <= s_CLEANUP;
r_Tx_Active <= 1'b0;
end
end // case: s_Tx_STOP_BIT
// Stay here 1 clock
s_CLEANUP :
begin
r_Tx_Done <= 1'b1;
r_SM_Main <= s_IDLE;
end
default :
r_SM_Main <= s_IDLE;
endcase
end
assign o_Tx_Active = r_Tx_Active;
assign o_Tx_Done = r_Tx_Done;
endmodule |
module calculate_val #(
parameter INPUT = 1
) (
input [4:0] value,
input [4:0] rotor,
output reg [4:0] out,
input [4:0] ring_position
);
reg signed [6:0] val = 7'b0000000;
always @*
begin
if (INPUT==1)
val = value - ring_position + rotor;
else
val = value + ring_position - rotor;
if (val < 0 ) val = val + 7'd26;
if (val > 7'd25) val = val - 7'd26;
out = val[4:0];
end
endmodule |
module encode #(
parameter REVERSE = 0
) (
input [4:0] inputValue,
input [4:0] rotor,
output [4:0] outputValue,
input [2:0] rotor_type,
input [4:0] ring_position
);
wire [4:0] calculated_input;
wire [4:0] outval;
calculate_val #(.INPUT(1)) cinput(.value(inputValue),.rotor(rotor),.out(calculated_input),.ring_position(ring_position));
rotorEncode #(.REVERSE(REVERSE)) rotEncode(.code(calculated_input),.val(outval),.rotor_type(rotor_type));
calculate_val #(.INPUT(0)) coutput(.value(outval),.rotor(rotor),.out(outputValue),.ring_position(ring_position));
endmodule |
module i2c_sender_verilog( input clk, inout siod, output sioc,
output taken, input send, input [7:0] id,
input [7:0] rega, input [7:0] value);
reg unsigned [7:0] divider = 8'b00000001;
reg [31:0] busy_sr = {32{1'b0}};
reg [31:0] data_sr = {32{1'b1}};
reg sioc_temp;
reg taken_temp;
reg siod_temp;
assign siod = siod_temp;
assign sioc = sioc_temp;
assign taken = taken_temp;
always@(busy_sr,data_sr[31])
begin
if(busy_sr[11:10] == 2'b10 || busy_sr[20:19] == 2'b10 || busy_sr[29:28] == 2'b10)
begin
siod_temp <= 1'bZ;
end
else
begin
siod_temp <= data_sr[31];
end
end
always@(posedge clk)
begin
taken_temp <= 1'b0;
if(busy_sr[31] == 0)
begin
sioc_temp <= 1;
if(send == 1)
begin
if(divider == 8'b000000000)
begin
data_sr <= 3'b100 & id & 1'b0 & rega & 1'b0 & value & 1'b0 & 2'b01;
busy_sr <= 3'b111 & 9'b111111111 & & 9'b111111111 & 9'b111111111 & 2'b11;
taken_temp <= 1'b1;
end
else
begin
divider <= divider + 1;
end
end
end
else
begin
if(busy_sr[31:29] == 3'b111 && busy_sr[2:0] == 3'b111)
begin
sioc_temp <= 1;
end
else if(busy_sr[31:29] == 3'b111 && busy_sr[2:0] == 3'b110)
begin
sioc_temp = 1;
end
else if (busy_sr[31:29] == 3'b111 && busy_sr[2:0] == 3'b100)
begin
sioc_temp = 0;
end
else if (busy_sr[31:29] == 3'b111 && busy_sr[2:0] == 3'b111 && (divider[7:6] == 2'b01 || divider[7:6] == 2'b10 || divider[7:6] == 2'b11))
begin
sioc_temp = 1;
end
else if (busy_sr[31:29] == 3'b111 && busy_sr[2:0] == 3'b111 && divider[7:6] == 2'b00)
begin
sioc_temp = 0;
end
else if (busy_sr[31:29] == 3'b100 && busy_sr[2:0] == 3'b000)
begin
sioc_temp = 1;
end
else if(busy_sr[31:29] == 3'b000 && busy_sr[2:0] == 3'b000)
begin
sioc_temp = 1;
end
else
begin
if(divider[7:6] == 2'b00 || divider[7:6] == 2'b11)
begin
sioc_temp = 0;
end
else if (divider[7:6] == 2'b01 || divider[7:6] == 2'b10)
begin
sioc_temp = 1;
end
end
if(divider == 8'b11111111)
begin
busy_sr = busy_sr[30:0] & 1'b0;
data_sr = data_sr[30:0] & 1'b1;
divider <= {8{1'b0}};
end
else
begin
divider <= divider + 1;
end
end
end
endmodule |
module debounce(input clk, input i, output o);
reg unsigned [23:0] c;
reg out_temp;
always @(posedge clk)begin
if(i == 1)begin
if(c==24'hFFFFFF)begin
out_temp <= 1'b1;
end
else begin
out_temp <= 1'b0;
end
c <= c+1'b1;
end
else begin
c <= {24{1'b0}};
out_temp <= 1'b0;
end
end
assign o = out_temp;
endmodule |
module ov7670_registers_verilog(input clk, input resend, input advance, output [15:0] command, output finished);
reg [15:0] sreg;
reg finished_temp;
reg [7:0] address = {8{1'b0}};
assign command = sreg;
assign finished = finished_temp;
always@(sreg)
begin
if(sreg == 16'b1111111111111111)
begin
finished_temp <= 1;
end
else
begin
finished_temp <= 0;
end
end
always@(posedge clk)
begin
if(resend == 1)
begin
address <= {8{1'b0}};
end
else if(advance == 1)
begin
address <= address+1;
end
case (address)
0 : sreg <= 4'h1280;
1 : sreg <= 4'h1280;
2 : sreg <= 4'h1204;
3 : sreg <= 4'h1100;
4 : sreg <= 4'h0C00;
5 : sreg <= 4'h3E00;
6 : sreg <= 4'h8C00;
7 : sreg <= 4'h0400;
8 : sreg <= 4'h4010;
9 : sreg <= 4'h3A04;
10 : sreg <= 4'h1438;
11 : sreg <= 4'h4FB3;
12 : sreg <= 4'h50B3;
13 : sreg <= 4'h5100;
14 : sreg <= 4'h523D;
15 : sreg <= 4'h53A7;
16 : sreg <= 4'h54E4;
17 : sreg <= 4'h589E;
18 : sreg <= 4'h3DC0;
19 : sreg <= 4'h1100;
20 : sreg <= 4'h1711;
21 : sreg <= 4'h1861;
22 : sreg <= 4'h32A4;
23 : sreg <= 4'h1903;
24 : sreg <= 4'h1A7B;
25 : sreg <= 4'h030A;
26 : sreg <= 4'h0E61;
27 : sreg <= 4'h0F4B;
28 : sreg <= 4'h1602;
29 : sreg <= 4'h1E37;
30 : sreg <= 4'h2102;
31 : sreg <= 4'h2291;
32 : sreg <= 4'h2907;
33 : sreg <= 4'h330B;
34 : sreg <= 4'h350B;
35 : sreg <= 4'h371B;
36 : sreg <= 4'h3871;
37 : sreg <= 4'h392A;
38 : sreg <= 4'h3C78;
39 : sreg <= 4'h4D40;
39 : sreg <= 4'h4D40;
40 : sreg <= 4'h4E20;
41 : sreg <= 4'h6900;
42 : sreg <= 4'h7410;
43 : sreg <= 4'h7410;
44 : sreg <= 4'h8D4F;
45 : sreg <= 4'h8E00;
46 : sreg <= 4'h8F00;
47 : sreg <= 4'h9000;
48 : sreg <= 4'h9100;
49 : sreg <= 4'h9600;
50 : sreg <= 4'h9A00;
51 : sreg <= 4'hB084;
52 : sreg <= 4'hB10C;
53 : sreg <= 4'hB20E;
54 : sreg <= 4'hB382;
55 : sreg <= 4'hB80A;
default : sreg <= 4'hFFFF;
endcase
end
endmodule |
module vga(input clk25,
output [3:0] vga_red,
output [3:0] vga_green,
output [3:0] vga_blue,
output vga_hsync,
output vga_vsync,
output [18:0] frame_addr,
input [11:0] frame_pixel);
parameter hRez = 640;
parameter hStartSync = 640+16;
parameter hEndSync = 640+16+96;
parameter hMaxCount = 800;
parameter vRez = 480;
parameter vStartSync = 480+10;
parameter vEndSync = 480+10+2;
parameter vMaxCount = 480+10+2+33;
parameter hsync_active = 0;
parameter vsync_active = 0;
reg unsigned [9:0] hCounter = {10{1'b0}};
reg unsigned [9:0] vCounter = {10{1'b0}};
reg unsigned [18:0] address = {19{1'b0}};
reg unsigned [18:0] address_temp = {19{1'b0}};
reg blank = 1;
reg [3:0] vga_red_temp;
reg [3:0] vga_blue_temp;
reg [3:0] vga_green_temp;
reg vga_hsync_temp;
reg vga_vsync_temp;
always @(posedge clk25)
begin
if (hCounter == hMaxCount-1)
begin
hCounter <= {10{1'b0}};
if(vCounter == vMaxCount-1)
begin
vCounter <= {10{1'b0}};
end
else
begin
vCounter <= vCounter+1;
end
end
else
begin
hCounter <= hCounter+1;
end
if(blank == 0)
begin
vga_red_temp <= frame_pixel[11:8];
vga_green_temp <= frame_pixel[7:4];
vga_blue_temp <= frame_pixel[3:0];
end
else
begin
vga_red_temp <= {4{1'b0}};
vga_green_temp <= {4{1'b0}};
vga_blue_temp <= {4{1'b0}};
end
if(vCounter >= vRez)
begin
address <= {19{1'b0}};
blank <= 1;
end
else
begin
if(hCounter < 640)
begin
blank <= 0;
address <= address+1'b1;
end
else
begin
blank <= 1;
end
end
if(hCounter > hStartSync && hCounter <= hEndSync)
begin
vga_hsync_temp <= hsync_active;
end
else
begin
vga_hsync_temp <= !hsync_active;
end
if(vCounter >= vStartSync && vCounter < vEndSync)
begin
vga_vsync_temp <= vsync_active;
end
else
begin
vga_vsync_temp <= !vsync_active;
end
end
assign frame_addr = address;
assign vga_red = vga_red_temp;
assign vga_blue = vga_blue_temp;
assign vga_green = vga_green_temp;
assign vga_hsync = vga_hsync_temp;
assign vga_vsync = vga_vsync_temp;
endmodule |
module ov7670_controller_verilog(input clk, input resend, output config_finished, output sioc, inout siod, output reset, output pwdn, output xclk);
reg sys_clk = 0;
wire [15:0] command;
wire finished = 0;
wire taken = 0;
reg send;
reg [7:0] camera_address = 2'h42;
assign config_finished = finished;
assign reset = 1;
assign pwdn = 0;
assign xclk = sys_clk;
always@(finished)
begin
send = ~finished;
end
always@(posedge clk)
begin
sys_clk = ~sys_clk;
end
ov7670_registers_verilog orv(.clk(clk),.advance(taken), .command(command), .finished(finished), .resend(resend));
i2c_sender_verilog isv(.clk(clk), .taken(taken), .siod(siod), .sioc(sioc), .send(send), .id(camera_address), .rega(command[15:8]), .value(command[7:0]));
endmodule |
module ov7670_capture_verilog(input pclk,
input vsync,
input href,
input [7:0] d,
output [18:0] addr,
output [11:0] dout,
output we);
reg [15:0] d_latch = {16{1'b0}};
reg [18:0] address = {19{1'b0}};
reg unsigned [18:0] address_next = {19{1'b0}};
reg [1:0] wr_hold = {2{1'b0}};
reg [11:0] dout_temp;
reg we_temp;
assign addr = address;
assign dout = dout_temp;
assign we = we_temp;
always@ (posedge pclk)
begin
if(vsync == 1)
begin
address <= {19{1'b0}};
address_next <= {19{1'b0}};
wr_hold <= {2{1'b0}};
end
else
begin
dout_temp <= {d_latch[15:12],d_latch[10:7],d_latch[4:1]};
address <= address_next;
we_temp <= wr_hold[1];
wr_hold <= {wr_hold[0], (href && !wr_hold[0])};
d_latch <= {d_latch [7:0], d};
if(wr_hold[1] == 1)
begin
address_next <= address_next+1;
end
end
end
endmodule |
module clocking_verilog(input clk_in, output clk_out);
wire clk_in;
reg clk_out;
always @ (posedge clk_in)
begin
clk_out <= !clk_out ;
end
endmodule |
module OV7670_top_verilog(input clk100, output OV7670_SIOC, inout OV7670_SIOD, output OV7670_RESET,
output OV7670_PWDN, input OV7670_VSYNC, input OV7670_HREF, input OV7670_PCLK,
output OV7670_XCLK, input [7:0] OV7670_D, output [7:0] LED, output [3:0] vga_red,
output [3:0] vga_green, output [3:0] vga_blue, output vga_hsync, output vga_vsync, input btn);
wire [18:0] frame_addr;
wire [11:0] frame_pixel;
wire [18:0] capture_addr;
wire [11:0] capture_data;
wire capture_we;
wire resend;
wire config_finished;
reg clk_feedback;
reg clk50u;
wire clk50;
reg clk25u;
wire clk25;
reg buffered_pclk;
assign LED = 8'b00000000 & config_finished;
debounce db1(.clk(clk50),.i(btn),.o(resend));
vga vg1(.clk25(clk25),.vga_red(vga_red),.vga_green(vga_green),.vga_blue(vga_blue),.vga_hsync(vga_hsync),.vga_vsync(vga_vsync),.frame_addr(frame_addr),.frame_pixel(frame_pixel));
frame_buffer fb1(.clka(OV7670_PCLK),.wea(capture_we),.addra(capture_addr),.dina(capture_data),.clkb(clk50),.addrb(frame_addr),.doutb(frame_pixel));
ov7670_capture_verilog cap1(.pclk(OV7670_PCLK),.vsync(OV7670_VSYNC),.href(OV7670_HREF),.d(OV7670_D),.addr(capture_addr),.dout(capture_data),.we(capture_we));
ov7670_controller_verilog con1(.clk(clk50),.sioc(OV7670_SIOC),.resend(resend),.config_finished(config_finished),.siod(OV7670_SIOD),.pwdn(OV7670_PWDN),.reset(OV7670_RESET),.xclk(OV7670_XCLK));
clocking_verilog clk1(.clk_in(clk100),.clk_out(clk50));
clocking_verilog clk2(.clk_in(clk50),.clk_out(clk25));
endmodule |
module AXI4_Interconnect(clk, rst,
M1_ACLK, M1_ARESET, Master_1_Set, Master_1_Release,
M1_ARID, M1_ARADDR, M1_ARBURST, M1_ARVALID, M1_ARREADY, M1_ARLEN, M1_ARSIZE, // Read Address Channel
M1_RID, M1_RDATA, M1_RLAST, M1_RVALID, M1_RREADY, M1_RRESP, // Read Data Channel
M1_AWID, M1_AWADDR, M1_AWBURST, M1_AWVALID, M1_AWREADY, M1_AWLEN, M1_AWSIZE, // Write Address Channel
M1_WID, M1_WDATA, M1_WLAST, M1_WVALID, M1_WREADY, // Write Data Channel
M1_BID, M1_BRESP, M1_BVALID, M1_BREADY, // Write Response Channel
M2_ACLK, M2_ARESET, Master_2_Set, Master_2_Release,
M2_ARID, M2_ARADDR, M2_ARBURST, M2_ARVALID, M2_ARREADY, M2_ARLEN, M2_ARSIZE, // Read Address Channel
M2_RID, M2_RDATA, M2_RLAST, M2_RVALID, M2_RREADY, M2_RRESP, // Read Data Channel
M2_AWID, M2_AWADDR, M2_AWBURST, M2_AWVALID, M2_AWREADY, M2_AWLEN, M2_AWSIZE, // Write Address Channel
M2_WID, M2_WDATA, M2_WLAST, M2_WVALID, M2_WREADY, // Write Data Channel
M2_BID, M2_BRESP, M2_BVALID, M2_BREADY, // Write Response Channel
S_ACLK, S_ARESET,
S_ARID, S_ARADDR, S_ARBURST, S_ARVALID, S_ARREADY, S_ARLEN, S_ARSIZE, // Read Address Channel
S_RID, S_RDATA, S_RLAST, S_RVALID, S_RREADY, S_RRESP, // Read Data Channel
S_AWID, S_AWADDR, S_AWBURST, S_AWVALID, S_AWREADY, S_AWLEN, S_AWSIZE, // Write Address Channel
S_WID, S_WDATA, S_WLAST, S_WVALID, S_WREADY, // Write Data Channel
S_BID, S_BRESP, S_BVALID, S_BREADY); // Write Response Channel
parameter memWidth = 8;
parameter memDepth = 32;
parameter addressLength = 5; // Calculated by taking (log2) of "memDepth"
input clk;
input rst;
/////////// Interconnect's Circular Arbitration Ports ///////////
output [0:0] Master_1_Set;
input [0:0] Master_1_Release;
output [0:0] Master_2_Set;
input [0:0] Master_2_Release;
/////////// Master 1 Ports ///////////
output M1_ACLK;
output M1_ARESET;
input [3:0] M1_ARID;
input [addressLength-1:0] M1_ARADDR; // Read Address Channel
input [1:0] M1_ARBURST;
input [0:0] M1_ARVALID;
output [0:0] M1_ARREADY;
input [7:0] M1_ARLEN;
input [2:0] M1_ARSIZE;
output [3:0] M1_RID;
output [memWidth-1:0] M1_RDATA; // Read Data Channel
output [0:0] M1_RLAST;
output [0:0] M1_RVALID;
input [0:0] M1_RREADY;
output [1:0] M1_RRESP;
input [3:0] M1_AWID;
input [addressLength-1:0] M1_AWADDR; // Write Address Channel
input [1:0] M1_AWBURST;
input [0:0] M1_AWVALID;
output [0:0] M1_AWREADY;
input [7:0] M1_AWLEN;
input [2:0] M1_AWSIZE;
input [3:0] M1_WID;
input [memWidth-1:0] M1_WDATA; // Write Data Channel
input [0:0] M1_WVALID;
output [0:0] M1_WREADY;
input [0:0] M1_WLAST;
output [3:0] M1_BID;
output [1:0] M1_BRESP; // Write Response Channel
output [0:0] M1_BVALID;
input [0:0] M1_BREADY;
/////////// Master 2 Ports ///////////
output M2_ACLK;
output M2_ARESET;
input [3:0] M2_ARID;
input [addressLength-1:0] M2_ARADDR; // Read Address Channel
input [1:0] M2_ARBURST;
input [0:0] M2_ARVALID;
output [0:0] M2_ARREADY;
input [7:0] M2_ARLEN;
input [2:0] M2_ARSIZE;
output [3:0] M2_RID;
output [memWidth-1:0] M2_RDATA; // Read Data Channel
output [0:0] M2_RLAST;
output [0:0] M2_RVALID;
input [0:0] M2_RREADY;
output [1:0] M2_RRESP;
input [3:0] M2_AWID;
input [addressLength-1:0] M2_AWADDR; // Write Address Channel
input [1:0] M2_AWBURST;
input [0:0] M2_AWVALID;
output [0:0] M2_AWREADY;
input [7:0] M2_AWLEN;
input [2:0] M2_AWSIZE;
input [3:0] M2_WID;
input [memWidth-1:0] M2_WDATA; // Write Data Channel
input [0:0] M2_WVALID;
output [0:0] M2_WREADY;
input [0:0] M2_WLAST;
output [3:0] M2_BID;
output [1:0] M2_BRESP; // Write Response Channel
output [0:0] M2_BVALID;
input [0:0] M2_BREADY;
// Slave Wires
output S_ACLK;
output S_ARESET;
output [3:0] S_ARID;
output [addressLength-1:0] S_ARADDR; // Read Address Channel
output [1:0] S_ARBURST;
output [0:0] S_ARVALID;
input [0:0] S_ARREADY;
output [7:0] S_ARLEN;
output [2:0] S_ARSIZE;
input [3:0] S_RID;
input [memWidth-1:0] S_RDATA; // Read Data Channel
input [0:0] S_RLAST;
input [0:0] S_RVALID;
output [0:0] S_RREADY;
input [1:0] S_RRESP;
output [3:0] S_AWID;
output [addressLength-1:0] S_AWADDR; // Write Address Channel
output [1:0] S_AWBURST;
output [0:0] S_AWVALID;
input [0:0] S_AWREADY;
output [7:0] S_AWLEN;
output [2:0] S_AWSIZE;
output [3:0] S_WID;
output [memWidth-1:0] S_WDATA; // Write Data Channel
output [0:0] S_WVALID;
input [0:0] S_WREADY;
output [0:0] S_WLAST;
input [3:0] S_BID;
input [1:0] S_BRESP; // Write Response Channel
input [0:0] S_BVALID;
output [0:0] S_BREADY;
/////////// Round Robin Arbitration Signals & Logic ///////////
localparam totalMasters = 3; // For two Masters (not using '0' index for Masters, hence actual Masters + 1).
reg [(totalMasters-1):0] masterIndex = 3'bZ; // Keeps track of all the Masters.
reg [(totalMasters-1):0] currentMaster = 3'bZ; // Master that currently has the access to the slave.
reg [0:0] setMastersAccess [0:(totalMasters-1)]; // Array of outgoing signals (one for each Master).
reg [0:0] releaseMastersAccess [0:(totalMasters-1)]; // Array of incoming signals (one from each Master).
reg [(totalMasters-1):0] Master_1 = 3'b001; // Master 1 ID
reg [(totalMasters-1):0] Master_2 = 3'b010; // Master 2 ID
//reg [(totalMasters-1):0] Master_3 = 3'b011; // Master 3 ID
//reg [(totalMasters-1):0] Master_4 = 3'b100; // Master 4 ID
//reg [(totalMasters-1):0] Master_5 = 3'b101; // Master 5 ID
assign Master_1_Set = setMastersAccess[1]; // Sending the access signals to Master 1.
assign Master_2_Set = setMastersAccess[2]; // Sending the access signals to Master 2.
always @ (posedge clk)
begin
if (rst != 1'b0)
begin
releaseMastersAccess[1] <= Master_1_Release; // Reading release signals from Master 1.
releaseMastersAccess[2] <= Master_2_Release; // Reading release signals from Master 2.
end
end
always @ (posedge clk)
begin
if (rst == 1'b0) // Setting all output signals to low on reset (active low)
begin
setMastersAccess[1] <= 1'bZ;
setMastersAccess[2] <= 1'bZ;
masterIndex <= 1; // Prioritizing Master 1 to have first access to the Slave when starting.
currentMaster <= Master_1; // Doesn't need to be set now to grant priority. It just removes clashes
//currentMaster <= 3'bZ; // in the signals when simulating. The wavedform will look clean.
end
end
always @ (posedge clk)
begin
if (rst != 1'b0)
begin
if (releaseMastersAccess[masterIndex] == 1'b0)
begin
setMastersAccess[masterIndex] <= 1'b1; // Signal the Master that its their turn.
currentMaster <= masterIndex; // Allow the interconnection between the Master and the Slave
end
else if (releaseMastersAccess[masterIndex] == 1'b1) // If the current Master no longer needs the access,
begin // then grant access to the next Master.
setMastersAccess[masterIndex] <= 1'b0; // Signal the current Master that their turn is
// indeed over.
//currentMaster <= 3'bZ; // Remove the interconnection between the Master and the Slave
if (masterIndex < (totalMasters - 1))
begin
masterIndex <= masterIndex + 1; // Move onto the next Master...
currentMaster <= masterIndex + 1;
end
else
begin
masterIndex <= 1;
currentMaster <= 1;
end
end
end
end
/////////// Master and Slave's Clock & Reset are always Assigned/Enabled ///////////
assign S_ACLK = clk;
assign S_ARESET = rst;
assign M1_ACLK = clk;
assign M1_ARESET = rst;
assign M2_ACLK = clk;
assign M2_ARESET = rst;
/////////// Master 1 and Master 2's Connection to Slave ///////////
/////////// Read Address Channel ///////////
assign S_ARID = (currentMaster == Master_1) ? M1_ARID : (currentMaster == Master_2) ? M2_ARID : 4'bZ;
assign S_ARADDR = (currentMaster == Master_1) ? M1_ARADDR : (currentMaster == Master_2) ? M2_ARADDR : 5'bZ;
assign S_ARBURST = (currentMaster == Master_1) ? M1_ARBURST : (currentMaster == Master_2) ? M2_ARBURST : 2'bZ;
assign S_ARVALID = (currentMaster == Master_1) ? M1_ARVALID : (currentMaster == Master_2) ? M2_ARVALID : 1'bZ;
assign S_ARLEN = (currentMaster == Master_1) ? M1_ARLEN : (currentMaster == Master_2) ? M2_ARLEN : 8'bZ;
assign S_ARSIZE = (currentMaster == Master_1) ? M1_ARSIZE : (currentMaster == Master_2) ? M2_ARSIZE : 3'bZ;
assign M1_ARREADY = (currentMaster == Master_1) ? S_ARREADY : 1'bZ;
assign M2_ARREADY = (currentMaster == Master_2) ? S_ARREADY : 1'bZ;
/////////// Read Data Channel ///////////
assign M1_RID = (currentMaster == Master_1) ? S_RID : 4'bZ;
assign M1_RDATA = (currentMaster == Master_1) ? S_RDATA : 8'bZ;
assign M1_RLAST = (currentMaster == Master_1) ? S_RLAST : 1'bZ;
assign M1_RVALID = (currentMaster == Master_1) ? S_RVALID : 1'bZ;
assign M1_RRESP = (currentMaster == Master_1) ? S_RRESP : 2'bZ;
assign M2_RID = (currentMaster == Master_2) ? S_RID : 4'bZ;
assign M2_RDATA = (currentMaster == Master_2) ? S_RDATA : 8'bZ;
assign M2_RLAST = (currentMaster == Master_2) ? S_RLAST : 1'bZ;
assign M2_RVALID = (currentMaster == Master_2) ? S_RVALID : 1'bZ;
assign M2_RRESP = (currentMaster == Master_2) ? S_RRESP : 2'bZ;
assign S_RREADY = (currentMaster == Master_1) ? M1_RREADY : (currentMaster == Master_2) ? M2_RREADY : 1'bZ;
/////////// Write Address Channel ///////////
assign S_AWID = (currentMaster == Master_1) ? M1_AWID : (currentMaster == Master_2) ? M2_AWID : 4'bZ;
assign S_AWADDR = (currentMaster == Master_1) ? M1_AWADDR : (currentMaster == Master_2) ? M2_AWADDR : 5'bZ;
assign S_AWBURST = (currentMaster == Master_1) ? M1_AWBURST : (currentMaster == Master_2) ? M2_AWBURST : 2'bZ;
assign S_AWVALID = (currentMaster == Master_1) ? M1_AWVALID : (currentMaster == Master_2) ? M2_AWVALID : 1'bZ;
assign S_AWLEN = (currentMaster == Master_1) ? M1_AWLEN : (currentMaster == Master_2) ? M2_AWLEN : 8'bZ;
assign S_AWSIZE = (currentMaster == Master_1) ? M1_AWSIZE : (currentMaster == Master_2) ? M2_AWSIZE : 3'bZ;
assign M1_AWREADY = (currentMaster == Master_1) ? S_AWREADY : 1'bZ;
assign M2_AWREADY = (currentMaster == Master_2) ? S_AWREADY : 1'bZ;
/////////// Write Data Channel ///////////
assign S_WID = (currentMaster == Master_1) ? M1_WID : (currentMaster == Master_2) ? M2_WID : 4'bZ;
assign S_WDATA = (currentMaster == Master_1) ? M1_WDATA : (currentMaster == Master_2) ? M2_WDATA : 8'bZ;
assign S_WVALID = (currentMaster == Master_1) ? M1_WVALID : (currentMaster == Master_2) ? M2_WVALID : 1'bZ;
assign S_WLAST = (currentMaster == Master_1) ? M1_WLAST : (currentMaster == Master_2) ? M2_WLAST : 1'bZ;
assign M1_WREADY = (currentMaster == Master_1) ? S_WREADY : 1'bZ;
assign M2_WREADY = (currentMaster == Master_2) ? S_WREADY : 1'bZ;
/////////// Write Response Channel ///////////
assign M1_BID = (currentMaster == Master_1) ? S_BID : 4'bZ;
assign M1_BRESP = (currentMaster == Master_1) ? S_BRESP : 2'bZ;
assign M1_BVALID = (currentMaster == Master_1) ? S_BVALID : 1'bZ;
assign M2_BID = (currentMaster == Master_2) ? S_BID : 4'bZ;
assign M2_BRESP = (currentMaster == Master_2) ? S_BRESP : 2'bZ;
assign M2_BVALID = (currentMaster == Master_2) ? S_BVALID : 1'bZ;
assign S_BREADY = (currentMaster == Master_1) ? M1_BREADY : (currentMaster == Master_2) ? M2_BREADY : 1'bZ;
endmodule |
module AXI4_BRAM_Controller(ACLK, ARESET,
ARID, ARADDR, ARBURST, ARVALID, ARREADY, ARLEN, ARSIZE, // Read Address Channel
RID, RDATA, RLAST, RVALID, RREADY, RRESP, // Read Data Channel
AWID, AWADDR, AWBURST, AWVALID, AWREADY, AWLEN, AWSIZE, // Write Address Channel
WID, WDATA, WLAST, WVALID, WREADY, // Write Data Channel
BID, BRESP, BVALID, BREADY); // Write Response Channel
parameter memWidth = 8;
parameter memDepth = 32;
parameter addressLength = 5; // Calculated by taking (log2) of "memDepth"
parameter readAddressStart = 0;
parameter readAddressEnd = 9;
input ACLK;
input ARESET;
input [3:0] ARID;
input [addressLength-1:0] ARADDR; // Read Address Channel
input [1:0] ARBURST;
input [0:0] ARVALID;
output reg [0:0] ARREADY;
input [7:0] ARLEN; // ARLEN contains the number of beats minus one. Slave uses this information to generate response data beats matching ARLEN + 1
input [2:0] ARSIZE;
output reg [3:0] RID;
output reg [memWidth-1:0] RDATA; // Read Data Channel
output reg [0:0] RLAST;
output reg [0:0] RVALID;
input [0:0] RREADY;
output reg [1:0] RRESP;
input [3:0] AWID;
input [addressLength-1:0] AWADDR; // Write Address Channel
input [1:0] AWBURST;
input [0:0] AWVALID;
output reg [0:0] AWREADY;
input [7:0] AWLEN;
input [2:0] AWSIZE;
input [3:0] WID;
input [memWidth-1:0] WDATA; // Write Data Channel
input [0:0] WVALID;
output reg [0:0] WREADY;
input [0:0] WLAST;
output reg [3:0] BID;
output reg [1:0] BRESP; // Write Response Channel
output reg [0:0] BVALID;
input [0:0] BREADY;
/* Handshake Logic
Data Transfer Logic
Etc..... */
reg [0:0] readEnable = 1'bZ;
reg [0:0] writeEnable = 1'bZ;
reg [addressLength-1:0] readAddressBRAM;
reg [addressLength-1:0] writeAddressBRAM;
reg [3:0] readTransactionID = 4'bZ;
reg [0:0] readAddressChannelEnabled = 1'bZ;
reg [0:0] readChannelEnabled = 1'bZ;
reg [3:0] writeTransactionID = 4'bZ;
reg [0:0] writeAddressChannelEnabled = 1'bZ;
reg [0:0] writeChannelEnabled = 1'bZ;
reg [0:0] writeResponseChannelEnabled = 1'bZ;
reg [2:0] readBurstTypeState = 3'bZ;
reg [2:0] writeBurstTypeState = 3'bZ;
reg [1:0] readStatusRRESP = 2'bZ;
reg [1:0] writeStatusBRESP = 2'bZ;
reg [0:0] firstTimeInitBRAMAddress = 1'bZ;
reg [memWidth-1:0] BRAM [0:memDepth-1]; // BRAM used for storing the data.
initial
begin//"../"
$readmemh("../initMem.txt", BRAM, readAddressStart, readAddressEnd); // Initialize the BRAM.
end
generate // Maps all the elements of the above array to a wire. Only possible way to dump the
genvar index; // values of array into a VCD file.
for(index=0; index<10; index=index+1)
begin: register
wire [7:0] wireOfBRAM;
assign wireOfBRAM = BRAM[index];
end
endgenerate
always @ (posedge ACLK)
begin
if (ARESET != 1'b0)
begin
if (readEnable == 1'b1)
begin
RDATA <= BRAM[readAddressBRAM]; // Read from the BRAM
end
else
begin
RDATA <= 8'bZ;
end
if (writeEnable == 1'b1)
begin
BRAM[writeAddressBRAM] <= WDATA; // Write to the BRAM
end
end
end
always @ (posedge ACLK)
begin
if (ARESET == 1'b0) // Setting all output signals to low on reset (active low)
begin
ARREADY <= 1'bZ;
RVALID <= 1'bZ;
BVALID <= 1'bZ;
RID <= 4'bZ;
RDATA <= 8'bZ;
RLAST <= 1'bZ;
RVALID <= 1'bZ;
RRESP <= 2'bZ;
AWREADY <= 1'bZ;
WREADY <= 1'bZ;
BID <= 4'bZ;
BRESP <= 2'bZ;
BVALID <= 1'bZ;
readEnable <= 1'b0;
writeEnable <= 1'b0;
readAddressBRAM <= 5'bZ;
writeAddressBRAM <= 5'bZ;
readTransactionID <= 4'bz;
writeTransactionID <= 4'bz;
readAddressChannelEnabled <= 1'b1;
writeAddressChannelEnabled <= 1'b1;
end
end
always @ (posedge ACLK)
begin
if (ARESET != 1'b0)
begin
if (readAddressChannelEnabled == 1'b1)
begin
ARREADY <= 1'b1;
RID <= 4'bZ;
RRESP <= 2'bZ;
RLAST <= 1'b0;
if ((ARVALID == 1'b1) && (ARSIZE == 3'b000)) // Size of '0' means the size of each Beat is 1 Byte or 8 bits.
begin
readTransactionID <= ARID;
readAddressBRAM <= ARADDR;
readBurstTypeState <= ARBURST;
readEnable <= 1'b1;
RVALID <= 1'b1;
RLAST <= 1'b0;
readAddressChannelEnabled <= 1'b0;
readChannelEnabled <= 1'b1;
end
end
end
end
always @ (posedge ACLK)
begin
if (ARESET != 1'b0)
begin
if (readChannelEnabled == 1'b1)
begin
ARREADY <= 1'b0;
RID <= readTransactionID;
RRESP <= 2'b00; // OKAY Response
case (readBurstTypeState) // Switching through the three Burst types.
2'b00: // FIXED Burst Type
begin
if (RREADY == 1'b1)
begin
readAddressBRAM <= ARADDR;
RLAST <= 1'b0;
end
end
2'b01: // INCREMENT Burst Type
begin
if (RREADY == 1'b1)
begin
readAddressBRAM <= readAddressBRAM + 1;
if (readAddressBRAM >= ARADDR + ARLEN)
begin
readAddressChannelEnabled <= 1'b1;
RVALID <= 1'b0;
RLAST <= 1'b1;
readEnable <= 1'b0;
readAddressBRAM <= 5'bZ;
readChannelEnabled <= 1'b0;
end
end
end
2'b10: // WRAP Burst Type
begin
if (RREADY == 1'b1)
begin
readAddressBRAM <= readAddressBRAM + 1;
if (readAddressBRAM >= ARADDR + ARLEN)
begin
readAddressBRAM <= ARADDR;
end
end
end
endcase
end
end
end
always @ (posedge ACLK)
begin
if (ARESET != 1'b0)
begin
if (writeAddressChannelEnabled == 1'b1)
begin
AWREADY <= 1'b1;
BID <= 4'bZ;
BVALID <= 1'b0;
BRESP <= 2'bZ;
if ((AWVALID == 1'b1) && (AWSIZE == 3'b000))
begin
firstTimeInitBRAMAddress <= 1'b1;
WREADY <= 1'b1;
writeTransactionID <= AWID;
writeBurstTypeState <= AWBURST;
writeEnable <= 1'b1;
writeAddressChannelEnabled <= 1'b0;
writeChannelEnabled = 1'b1;
AWREADY <= 1'b0;
end
end
end
end
always @ (posedge ACLK)
begin
if (ARESET != 1'b0)
begin
if (writeChannelEnabled == 1'b1)
begin
if ((firstTimeInitBRAMAddress == 1'b1) && (WVALID == 1'b1))
begin
writeAddressBRAM <= AWADDR;
firstTimeInitBRAMAddress <= 1'b0;
end
case (writeBurstTypeState)
2'b00: // FIXED Burst Type
begin
writeAddressBRAM <= AWADDR;
end
2'b01: // INCREMENT Burst Type
begin
if ((WVALID == 1'b1) && (WID == writeTransactionID))
begin
if (writeAddressBRAM < AWADDR + AWLEN)
begin
writeAddressBRAM <= writeAddressBRAM + 1;
end
end
if (writeAddressBRAM >= AWADDR + AWLEN)
begin
writeResponseChannelEnabled <= 1'b1;
writeStatusBRESP <= 2'b00; // Write Response = Okay/Successfull
//writeStatusBRESP <= 2'b10; // Write Response = Slave Error
WREADY <= 1'b0;
writeEnable <= 1'b0;
writeAddressBRAM <= 5'bZ;
writeChannelEnabled <= 1'b0;
end
end
2'b10: // WRAP Burst Type
begin
if ((WVALID == 1'b1) && (WID == writeTransactionID))
begin
if (writeAddressBRAM < AWADDR + AWLEN)
begin
writeAddressBRAM <= writeAddressBRAM + 1;
end
end
if (writeAddressBRAM >= AWADDR + AWLEN)
begin
writeAddressBRAM <= AWADDR;
end
end
endcase
end
end
end
always @ (posedge ACLK)
begin
if (ARESET != 1'b0)
begin
if (writeResponseChannelEnabled == 1'b1)
begin
BID <= writeTransactionID;
BVALID <= 1'b1;
if (BREADY == 1'b1)
begin
writeAddressChannelEnabled <= 1'b1;
BRESP <= writeStatusBRESP;
writeResponseChannelEnabled <= 1'b0;
end
end
end
end
endmodule |
module AXI4_Poly_Add(ACLK, ARESET, SET_ACCESS, RELEASE_ACCESS,
ARID, ARADDR, ARBURST, ARVALID, ARREADY, ARLEN, ARSIZE, // Read Address Channel
RID, RDATA, RLAST, RVALID, RREADY, RRESP, // Read Data Channel
AWID, AWADDR, AWBURST, AWVALID, AWREADY, AWLEN, AWSIZE, // Write Address Channel
WID, WDATA, WLAST, WVALID, WREADY, // Write Data Channel
BID, BRESP, BVALID, BREADY); // Write Response Channel
parameter memWidth = 8;
parameter memDepth = 32;
parameter addressLength = 5; // Calculated by taking (log2) of "memDepth"
input ACLK;
input ARESET;
input [0:0] SET_ACCESS;
output reg [0:0] RELEASE_ACCESS = 1'bZ;
output reg [3:0] ARID;
output reg [addressLength-1:0] ARADDR; // Read Address Channel
output reg [1:0] ARBURST;
output reg [0:0] ARVALID;
input [0:0] ARREADY;
output reg [7:0] ARLEN;
output reg [2:0] ARSIZE;
input [3:0] RID;
input [memWidth-1:0] RDATA; // Read Data Channel
input [0:0] RLAST;
input [0:0] RVALID;
output reg [0:0] RREADY;
input [1:0] RRESP;
output reg [3:0] AWID;
output reg [addressLength-1:0] AWADDR; // Write Address Channel
output reg [1:0] AWBURST;
output reg [0:0] AWVALID;
input [0:0] AWREADY;
output reg [7:0] AWLEN;
output reg [2:0] AWSIZE;
output reg [3:0] WID;
output reg [memWidth-1:0] WDATA; // Write Data Channel
output reg [0:0] WVALID;
input [0:0] WREADY;
output reg [0:0] WLAST;
input [3:0] BID;
input [1:0] BRESP; // Write Response Channel
input [0:0] BVALID;
output reg [0:0] BREADY;
/* Handshake Logic
Data Transfer Logic
Etc..... */
/* Will read co-efficients of a polynomial from the BRAM,
add a scalar quantity to each of the co-efficients,
then write back the new co-efficients into the BRAM. */
reg [7:0] coefficientsPoly [0:3];
reg [addressLength-1:0] readAddressARRAY;
reg [addressLength-1:0] writeAddressARRAY;
reg [3:0] readTransactionID = 4'bZ;
reg [0:0] readAddressChannelEnabled = 1'bZ;
reg [0:0] readChannelEnabled = 1'bZ;
reg [3:0] writeTransactionID = 4'bZ;
reg [0:0] writeAddressChannelEnabled = 1'bZ;
reg [0:0] writeChannelEnabled = 1'bZ;
reg [0:0] writeResponseChannelEnabled = 1'bZ;
reg [0:0] performOperations = 1'bZ;
reg [1:0] writeStatusBRESP = 1'bZ;
reg [0:0] resetReleaseAccess = 1'bZ;
reg [0:0] doReadAddressStall = 1'bZ;
reg [0:0] doWriteDataStall = 1'bZ;
integer delayReadCyclesCounter = 0;
integer delayWriteCyclesCounter = 0;
reg [0:0] firstTimeInitArrayAddress = 1'bZ;
integer arrayIndex = 0; // For iterating through the array when modifying it arithmetically.
generate // Maps all the elements of the above array to a wire. Only possible way to dump the
genvar index; // values of array into a VCD file.
for(index=0; index<4; index=index+1)
begin: register
wire [7:0] wireOfPoly;
assign wireOfPoly = coefficientsPoly[index];
end
endgenerate
always @ (posedge ACLK)
begin
if (ARESET == 1'b0)// || (RELEASE_ACCESS == 1'b1)) // Setting all output signals to low on reset (active low)
begin
ARID <= 4'bZ;
ARADDR <= 5'bZ;
ARBURST <= 2'bZ;
ARVALID <= 1'bZ;
ARLEN <= 8'bZ;
ARSIZE <= 3'bZ;
RREADY <= 1'bZ;
coefficientsPoly[0] <= 8'bZ;
coefficientsPoly[1] <= 8'bZ;
coefficientsPoly[2] <= 8'bZ;
coefficientsPoly[3] <= 8'bZ;
AWID <= 4'bZ;
AWADDR <= 5'bZ;
AWBURST <= 2'bZ;
AWVALID <= 1'bZ;
AWLEN <= 8'bZ;
AWSIZE <= 3'bZ;
WID <= 4'bZ;
WDATA <= 8'bZ;
WVALID <= 1'bZ;
WLAST <= 1'bZ;
BREADY <= 1'bZ;
readAddressARRAY <= 5'bZ;
writeAddressARRAY <= 5'bZ;
readTransactionID <= 4'b0000; // Starting with ARID of zero and incrementing it after each whole transaction.
writeTransactionID <= 4'b0000; // Starting with AWID of zero and incrementing it after each whole transaction.
doReadAddressStall <= 1'b1; // Enable this to start with Read Transaction.
RELEASE_ACCESS <= 1'b0;
//writeAddressChannelEnabled <= 1'b1; // Enable this to start with Write Transaction.
end
end
always @ (posedge ACLK)
begin
if ((ARESET != 1'b0) && (SET_ACCESS == 1'b1))
begin
if (doReadAddressStall == 1'b1) // Stalling for 1 clock cycles before starting the read address transaction.
begin
//if (delayReadCyclesCounter >= 1) // Don't need the Delays when using Interconnect Arbitration.
//begin
// readAddressChannelEnabled <= 1'b1;
// delayReadCyclesCounter <= 0;
// doReadAddressStall <= 1'b0;
//end
//else
//begin
// delayReadCyclesCounter <= delayReadCyclesCounter + 1;
//end
readAddressChannelEnabled <= 1'b1;
BREADY <= 1'b0;
doReadAddressStall <= 1'b0;
end
end
end
always @ (posedge ACLK)
begin
if ((ARESET != 1'b0) && (SET_ACCESS == 1'b1))
begin
if (doWriteDataStall == 1'b1) // Stalling for 1 clock cycle before starting the write data transaction.
begin
//if (delayWriteCyclesCounter >= 1) // Don't need the Delays when using Interconnect Arbitration.
//begin
// doWriteDataStall <= 1'b0;
// delayWriteCyclesCounter <= 0;
//end
//else
//begin
// delayWriteCyclesCounter <= delayWriteCyclesCounter + 1;
//end
AWVALID <= 1'b0;
WID <= writeTransactionID;
WVALID <= 1'b1;
WLAST <= 1'b0;
writeAddressARRAY <= 0;
writeChannelEnabled <= 1'b1;
doWriteDataStall <= 1'b0;
end
end
end
always @ (posedge ACLK)
begin
if ((ARESET != 1'b0) && (SET_ACCESS == 1'b1))
begin
if (readAddressChannelEnabled == 1'b1)
begin
ARID <= readTransactionID;
ARADDR <= 5'b00000;
ARLEN <= 8'b00000011; // ARLEN + 1 Beats in a single burst requested.
ARSIZE <= 3'b000; // Size of each Beat = 1 Byte. There are specific codes for each size.
ARBURST <= 2'b01; // 00 -> FIXED, 01 -> INCREMENT, 10 -> WRAP.
ARVALID <= 1'b1;
if (ARREADY == 1'b1)
begin
firstTimeInitArrayAddress <= 1'b1;
RREADY <= 1'b1;
readChannelEnabled <= 1'b1;
readAddressChannelEnabled <= 1'b0;
end
end
end
end
always @ (posedge ACLK)
begin
if ((ARESET != 1'b0) && (SET_ACCESS == 1'b1))
begin
if (readChannelEnabled == 1'b1)
begin
ARVALID <= 1'b0;
if ((firstTimeInitArrayAddress == 1'b1) && (RVALID == 1'b1))
begin
readAddressARRAY <= 0;
firstTimeInitArrayAddress <= 1'b0;
end
coefficientsPoly[readAddressARRAY] <= RDATA; // Store the incoming data from the Slave.
case (ARBURST)
2'b00: // FIXED Burst Type
begin
readAddressARRAY <= readAddressARRAY;
end
2'b01: // INCREMENT Burst Type
begin
if ((RVALID == 1'b1) && (RRESP == 2'b00) && (RID == readTransactionID))
begin
if (readAddressARRAY < ARLEN)
begin
readAddressARRAY <= readAddressARRAY + 1;
end
end
if (readAddressARRAY >= ARLEN)
begin
//readAddressChannelEnabled <= 1'b1; // Enable this for multiple seperate read transactions.
performOperations <= 1'b1;
ARID <= 4'bZ;
ARADDR <= 5'bZ;
ARLEN <= 8'bZ;
ARSIZE <= 3'bZ;
ARBURST <= 2'bZ;
RREADY <= 1'b0;
readAddressARRAY <= 5'bZ;
readChannelEnabled <= 1'b0;
readTransactionID <= readTransactionID + 1;
end
end
2'b10: // WRAP Burst Type
begin
if ((RVALID == 1'b1) && (RRESP == 2'b00) && (RID == readTransactionID))
begin
if (readAddressARRAY < ARLEN)
begin
readAddressARRAY <= readAddressARRAY + 1;
end
end
if (readAddressARRAY >= ARLEN)
begin
readAddressARRAY <= 0;
end
end
endcase
end
end
end
always @ (posedge ACLK) // I was working on write channel and streamlining it...
begin
if ((ARESET != 1'b0) && (SET_ACCESS == 1'b1))
begin
if (writeAddressChannelEnabled == 1'b1)
begin
AWID <= writeTransactionID;
AWADDR <= 5'b00000;
AWLEN <= 8'b00000011; // AWLEN + 1 Beats in a single burst requested.
AWSIZE <= 3'b000; // Size of each Beat = 1 Byte. There are specific codes for each size.
AWBURST <= 2'b01; // 00 -> FIXED, 01 -> INCREMENT, 10 -> WRAP.
AWVALID <= 1'b1;
WLAST <= 1'b0;
if (AWREADY == 1'b1)
begin
doWriteDataStall <= 1'b1;
writeAddressChannelEnabled <= 1'b0;
end
end
end
end
always @ (posedge ACLK)
begin
if ((ARESET != 1'b0) && (SET_ACCESS == 1'b1))
begin
if (writeChannelEnabled == 1'b1)
begin
AWVALID <= 1'b0;
WDATA <= coefficientsPoly[writeAddressARRAY];
case (AWBURST)
2'b00: // FIXED Burst Type
begin
readAddressARRAY <= readAddressARRAY;
end
2'b01: // INCREMENT Burst Type
begin
if (WREADY == 1'b1)
begin
writeAddressARRAY <= writeAddressARRAY + 1;
if (writeAddressARRAY >= AWLEN)
begin
writeResponseChannelEnabled <= 1'b1;
WLAST <= 1'b1;
WVALID <= 1'b0;
writeAddressARRAY <= 5'bZ;
writeChannelEnabled <= 1'b0;
end
end
end
2'b10: // WRAP Burst Type
begin
if (WREADY == 1'b1)
begin
writeAddressARRAY <= writeAddressARRAY + 1;
if (writeAddressARRAY >= AWLEN)
begin
writeAddressARRAY <= 0;
end
end
end
endcase
end
end
end
always @ (posedge ACLK)
begin
if ((ARESET != 1'b0) && (SET_ACCESS == 1'b1))
begin
if (writeResponseChannelEnabled == 1'b1)
begin
AWID <= 4'bZ;
AWADDR <= 5'bZ;
AWLEN <= 8'bZ;
AWSIZE <= 3'bZ;
AWBURST <= 2'bZ;
WID <= 4'bZ;
WDATA <= 8'bZ;
WLAST <= 1'b0;
BREADY <= 1'b1;
if ((BVALID == 1'b1) && (BID == writeTransactionID))
begin
//writeAddressChannelEnabled <= 1'b1; // For repeated Write Transactions.
doReadAddressStall <= 1'b1; // (Default) For Read -> Write Transactions and so on.
writeStatusBRESP <= BRESP;
WDATA <= 8'bZ;
writeTransactionID <= writeTransactionID + 1;
RELEASE_ACCESS <= 1'b1; // Signal the Interconnect for the end of Slave Access turn.
resetReleaseAccess <= 1'b1; // Lower the Release signal again for the next Slave Access turn.
writeResponseChannelEnabled <= 1'b0;
end
end
end
end
always @ (posedge ACLK)
begin
if (ARESET != 1'b0)
begin
if (resetReleaseAccess == 1'b1)
begin
RELEASE_ACCESS <= 1'b0;
resetReleaseAccess <= 1'b0;
end
end
end
always @ (posedge ACLK) // Custom Mathematical Operation on the Polynomial's Coefficients
begin
if ((performOperations == 1'b1) && (SET_ACCESS == 1'b1))
begin
for (arrayIndex=0; arrayIndex<4; arrayIndex=arrayIndex+1)
begin
coefficientsPoly[arrayIndex] <= coefficientsPoly[arrayIndex] + 2;
end
writeAddressChannelEnabled <= 1'b1;
performOperations <= 1'b0;
end
end
endmodule |
module usbserial_tbx (
input pin_clk,
inout pin_usb_p,
inout pin_usb_n,
output pin_pu,
output pin_led,
output [3:0] debug
);
wire clk_48mhz;
wire clk_locked;
// Use an icepll generated pll
pll pll48( .clock_in(pin_clk), .clock_out(clk_48mhz), .locked( clk_locked ) );
// LED
reg [22:0] ledCounter;
always @(posedge clk_48mhz) begin
ledCounter <= ledCounter + 1;
end
assign pin_led = ledCounter[ 22 ];
// Generate reset signal
reg [5:0] reset_cnt = 0;
wire reset = ~reset_cnt[5];
always @(posedge clk_48mhz)
if ( clk_locked )
reset_cnt <= reset_cnt + reset;
// uart pipeline in
wire [7:0] uart_in_data;
wire uart_in_valid;
wire uart_in_ready;
// assign debug = { uart_in_valid, uart_in_ready, reset, clk_48mhz };
wire usb_p_tx;
wire usb_n_tx;
wire usb_p_rx;
wire usb_n_rx;
wire usb_tx_en;
// usb uart - this instanciates the entire USB device.
usb_uart uart (
.clk_48mhz (clk_48mhz),
.reset (reset),
// pins
.pin_usb_p( pin_usb_p ),
.pin_usb_n( pin_usb_n ),
// uart pipeline in
.uart_in_data( uart_in_data ),
.uart_in_valid( uart_in_valid ),
.uart_in_ready( uart_in_ready ),
.uart_out_data( uart_in_data ),
.uart_out_valid( uart_in_valid ),
.uart_out_ready( uart_in_ready )
//.debug( debug )
);
// USB Host Detect Pull Up
assign pin_pu = 1'b1;
endmodule |
module MUXF7_L
(
input wire I0, I1,
input wire S,
output wire LO
);
assign LO = (S) ? I1 : I0;
endmodule |
module LUT6_D
#(
parameter [63:0] INIT = 64'h0000000000000000
)
(
input wire I0, I1, I2, I3, I4, I5,
output wire LO,
output wire O
);
wire [5:0] _w_idx = { I5, I4, I3, I2, I1, I0 };
assign LO = INIT[_w_idx];
assign O = INIT[_w_idx];
endmodule |
module SRLC16E
#(
parameter [15:0] INIT = 16'h0,
parameter [0:0] IS_CLK_INVERTED = 1'b0
)
(
// Clock
input wire CLK,
// Clock enable
input wire CE,
// Bit output position
input wire A0, A1, A2, A3,
// Data in
input wire D,
// Data out
output wire Q,
// Cascading data out
output wire Q15
);
// 32-bit shift register
reg [15:0] _r_srl;
// Bit position
wire [3:0] _w_addr = { A3, A2, A1, A0 };
// Power-up value
initial begin
_r_srl = INIT;
end
// Shifter logic
generate
if (IS_CLK_INVERTED) begin : GEN_CLK_NEG
always @(negedge CLK) begin : SHIFTER_16B
if (CE) begin
_r_srl <= { _r_srl[14:0], D };
end
end
end
else begin : GEN_CLK_POS
always @(posedge CLK) begin : SHIFTER_16B
if (CE) begin
_r_srl <= { _r_srl[14:0], D };
end
end
end
endgenerate
// Data out
assign Q = _r_srl[_w_addr];
// Cascading data out
assign Q15 = _r_srl[15];
endmodule |
module FDCE
#(
parameter [0:0] IS_C_INVERTED = 1'b0,
parameter [0:0] IS_D_INVERTED = 1'b0,
parameter [0:0] IS_CLR_INVERTED = 1'b0,
parameter [0:0] INIT = 1'b0
)
(
// Clock
input wire C,
// Clock enable
input wire CE,
// Asynchronous clear
input wire CLR,
// Data in
input wire D,
// Data out
output wire Q
);
reg _r_Q;
wire _w_CLR = CLR ^ IS_CLR_INVERTED;
wire _w_D = D ^ IS_D_INVERTED;
initial begin : INIT_STATE
_r_Q = INIT[0];
end
generate
if (IS_C_INVERTED) begin : GEN_CLK_NEG
always @(negedge C or posedge _w_CLR) begin
if (_w_CLR) begin
_r_Q <= 1'b0;
end
else if (CE) begin
_r_Q <= _w_D;
end
end
end
else begin : GEN_CLK_POS
always @(posedge C or posedge _w_CLR) begin
if (_w_CLR) begin
_r_Q <= 1'b0;
end
else if (CE) begin
_r_Q <= _w_D;
end
end
end
endgenerate
assign Q = _r_Q;
endmodule |
module LUT2
#(
parameter [3:0] INIT = 4'b0000
)
(
input wire I0, I1,
output wire O
);
wire [1:0] _w_idx = { I1, I0 };
assign O = INIT[_w_idx];
endmodule |
module MUXF7
(
input wire I0, I1,
input wire S,
output wire O
);
assign O = (S) ? I1 : I0;
endmodule |
module RAM32X1S
#(
parameter [31:0] INIT = 32'h0,
parameter [0:0] IS_WCLK_INVERTED = 1'b0
)
(
// Write clock
input wire WCLK,
// Write enable
input wire WE,
// Read / Write address
input wire A0,
input wire A1,
input wire A2,
input wire A3,
input wire A4,
// Data in
input wire D,
// Data out
output wire O
);
// Read / Write address
wire [4:0] _w_A = { A4, A3, A2, A1, A0 };
// 32 x 1-bit Select RAM
reg [31:0] _r_mem;
// Power-up value
initial begin : INIT_STATE
_r_mem = INIT;
end
// Synchronous memory write
generate
if (IS_WCLK_INVERTED) begin : GEN_WCLK_NEG
always @(negedge WCLK) begin : MEM_WRITE
if (WE) begin
_r_mem[_w_A] <= D;
end
end
end
else begin : GEN_WCLK_POS
always @(posedge WCLK) begin : MEM_WRITE
if (WE) begin
_r_mem[_w_A] <= D;
end
end
end
endgenerate
// Asynchronous memory read
assign O = _r_mem[_w_A];
endmodule |
module RAM64M
#(
parameter [63:0] INIT_A = 64'h0,
parameter [63:0] INIT_B = 64'h0,
parameter [63:0] INIT_C = 64'h0,
parameter [63:0] INIT_D = 64'h0,
parameter [0:0] IS_WCLK_INVERTED = 1'b0
)
(
// Write clock
input wire WCLK,
// Write enable
input wire WE,
// Port A
input wire [5:0] ADDRA,
input wire DIA,
output wire DOA,
// Port B
input wire [5:0] ADDRB,
input wire DIB,
output wire DOB,
// Port C
input wire [5:0] ADDRC,
input wire DIC,
output wire DOC,
// Port D
input wire [5:0] ADDRD,
input wire DID,
output wire DOD
);
// 64 x 4-bit Select RAM
reg [63:0] _r_mem_a;
reg [63:0] _r_mem_b;
reg [63:0] _r_mem_c;
reg [63:0] _r_mem_d;
// Power-up value
initial begin : INIT_STATE
_r_mem_a = INIT_A;
_r_mem_b = INIT_B;
_r_mem_c = INIT_C;
_r_mem_d = INIT_D;
end
// Synchronous memory write
generate
if (IS_WCLK_INVERTED) begin : GEN_WCLK_NEG
always @(negedge WCLK) begin : MEM_WRITE
if (WE) begin
_r_mem_a[ADDRD] <= DIA;
_r_mem_b[ADDRD] <= DIB;
_r_mem_c[ADDRD] <= DIC;
_r_mem_d[ADDRD] <= DID;
end
end
end
else begin : GEN_WCLK_POS
always @(posedge WCLK) begin : MEM_WRITE
if (WE) begin
_r_mem_a[ADDRD] <= DIA;
_r_mem_b[ADDRD] <= DIB;
_r_mem_c[ADDRD] <= DIC;
_r_mem_d[ADDRD] <= DID;
end
end
end
endgenerate
// Asynchronous memory read
assign DOA = _r_mem_a[ADDRA];
assign DOB = _r_mem_b[ADDRB];
assign DOC = _r_mem_c[ADDRC];
assign DOD = _r_mem_d[ADDRD];
endmodule |
module LUT1
#(
parameter [1:0] INIT = 2'b00
)
(
input wire I0,
output wire O
);
assign O = INIT[I0];
endmodule |
module RAM32X1D
#(
parameter [31:0] INIT = 32'h0,
parameter [0:0] IS_WCLK_INVERTED = 1'b0
)
(
// Write clock
input wire WCLK,
// Write enable
input wire WE,
// Read / Write address
input wire A0,
input wire A1,
input wire A2,
input wire A3,
input wire A4,
// Read address
input wire DPRA0,
input wire DPRA1,
input wire DPRA2,
input wire DPRA3,
input wire DPRA4,
// Data in
input wire D,
// Data out
output wire SPO,
output wire DPO
);
// Read / Write address
wire [4:0] _w_A = { A4, A3, A2, A1, A0 };
// Read address
wire [4:0] _w_DPRA = { DPRA4, DPRA3, DPRA2, DPRA1, DPRA0 };
// 32 x 1-bit Select RAM
reg [31:0] _r_mem;
// Power-up value
initial begin : INIT_STATE
_r_mem = INIT;
end
// Synchronous memory write
generate
if (IS_WCLK_INVERTED) begin : GEN_WCLK_NEG
always @(negedge WCLK) begin : MEM_WRITE
if (WE) begin
_r_mem[_w_A] <= D;
end
end
end
else begin : GEN_WCLK_POS
always @(posedge WCLK) begin : MEM_WRITE
if (WE) begin
_r_mem[_w_A] <= D;
end
end
end
endgenerate
// Asynchronous memory read
assign SPO = _r_mem[_w_A];
assign DPO = _r_mem[_w_DPRA];
endmodule |
module BUFG
(
input I,
output O /* verilator clocker */
);
assign O = I;
endmodule |
module RAM128X1D
#(
parameter [127:0] INIT = 128'h0,
parameter [0:0] IS_WCLK_INVERTED = 1'b0
)
(
// Write clock
input wire WCLK,
// Write enable
input wire WE,
// Read / Write address
input wire [6:0] A,
// Read address
input wire [6:0] DPRA,
// Data in
input wire D,
// Data out
output wire SPO,
output wire DPO
);
// 128 x 1-bit Select RAM
reg [127:0] _r_mem;
// Power-up value
initial begin : INIT_STATE
_r_mem = INIT;
end
// Synchronous memory write
generate
if (IS_WCLK_INVERTED) begin : GEN_WCLK_NEG
always @(negedge WCLK) begin : MEM_WRITE
if (WE) begin
_r_mem[A] <= D;
end
end
end
else begin : GEN_WCLK_POS
always @(posedge WCLK) begin : MEM_WRITE
if (WE) begin
_r_mem[A] <= D;
end
end
end
endgenerate
// Asynchronous memory read
assign SPO = _r_mem[A];
assign DPO = _r_mem[DPRA];
endmodule |
module LUT4
#(
parameter [15:0] INIT = 16'h0000
)
(
input wire I0, I1, I2, I3,
output wire O
);
wire [3:0] _w_idx = { I3, I2, I1, I0 };
assign O = INIT[_w_idx];
endmodule |
module MUXF9
(
input wire I0, I1,
input wire S,
output wire O
);
assign O = (S) ? I1 : I0;
endmodule |
module RAM512X1S
#(
parameter [511:0] INIT = 512'h0,
parameter [0:0] IS_WCLK_INVERTED = 1'b0
)
(
// Write clock
input wire WCLK,
// Write enable
input wire WE,
// Read / Write address
input wire [8:0] A,
// Data in
input wire D,
// Data out
output wire O
);
// 512 x 1-bit Select RAM
reg [511:0] _r_mem;
// Power-up value
initial begin : INIT_STATE
_r_mem = INIT;
end
// Synchronous memory write
generate
if (IS_WCLK_INVERTED) begin : GEN_WCLK_NEG
always @(negedge WCLK) begin : MEM_WRITE
if (WE) begin
_r_mem[A] <= D;
end
end
end
else begin : GEN_WCLK_POS
always @(posedge WCLK) begin : MEM_WRITE
if (WE) begin
_r_mem[A] <= D;
end
end
end
endgenerate
// Asynchronous memory read
assign O = _r_mem[A];
endmodule |
module LUT6_2
#(
parameter [63:0] INIT = 64'h0000000000000000
)
(
input wire I0, I1, I2, I3, I4, I5,
output wire O5,
output wire O6
);
wire [5:0] _w_idx_5 = { 1'b0, I4, I3, I2, I1, I0 };
wire [5:0] _w_idx_6 = { I5, I4, I3, I2, I1, I0 };
assign O5 = INIT[_w_idx_5];
assign O6 = INIT[_w_idx_6];
endmodule |
module RAM64X1S
#(
parameter [63:0] INIT = 64'h0,
parameter [0:0] IS_WCLK_INVERTED = 1'b0
)
(
// Write clock
input wire WCLK,
// Write enable
input wire WE,
// Read / Write address
input wire A0,
input wire A1,
input wire A2,
input wire A3,
input wire A4,
input wire A5,
// Data in
input wire D,
// Data out
output wire O
);
// Read / Write address
wire [5:0] _w_A = { A5, A4, A3, A2, A1, A0 };
// 64 x 1-bit Select RAM
reg [63:0] _r_mem;
// Power-up value
initial begin : INIT_STATE
_r_mem = INIT;
end
// Synchronous memory write
generate
if (IS_WCLK_INVERTED) begin : GEN_WCLK_NEG
always @(negedge WCLK) begin : MEM_WRITE
if (WE) begin
_r_mem[_w_A] <= D;
end
end
end
else begin : GEN_WCLK_POS
always @(posedge WCLK) begin : MEM_WRITE
if (WE) begin
_r_mem[_w_A] <= D;
end
end
end
endgenerate
// Asynchronous memory read
assign O = _r_mem[_w_A];
endmodule |
module GND
(
output wire G
);
assign G = 1'b0;
endmodule |
module MUXF8_L
(
input wire I0, I1,
input wire S,
output wire LO
);
assign LO = (S) ? I1 : I0;
endmodule |
module RAM64X1D
#(
parameter [63:0] INIT = 64'h0,
parameter [0:0] IS_WCLK_INVERTED = 1'b0
)
(
// Write clock
input wire WCLK,
// Write enable
input wire WE,
// Read / Write address
input wire A0,
input wire A1,
input wire A2,
input wire A3,
input wire A4,
input wire A5,
// Read address
input wire DPRA0,
input wire DPRA1,
input wire DPRA2,
input wire DPRA3,
input wire DPRA4,
input wire DPRA5,
// Data in
input wire D,
// Data out
output wire SPO,
output wire DPO
);
// Read / Write address
wire [5:0] _w_A = { A5, A4, A3, A2, A1, A0 };
// Read address
wire [5:0] _w_DPRA = { DPRA5, DPRA4, DPRA3, DPRA2, DPRA1, DPRA0 };
// 64 x 1-bit Select RAM
reg [63:0] _r_mem;
// Power-up value
initial begin : INIT_STATE
_r_mem = INIT;
end
// Synchronous memory write
generate
if (IS_WCLK_INVERTED) begin : GEN_WCLK_NEG
always @(negedge WCLK) begin : MEM_WRITE
if (WE) begin
_r_mem[_w_A] <= D;
end
end
end
else begin : GEN_WCLK_POS
always @(posedge WCLK) begin : MEM_WRITE
if (WE) begin
_r_mem[_w_A] <= D;
end
end
end
endgenerate
// Asynchronous memory read
assign SPO = _r_mem[_w_A];
assign DPO = _r_mem[_w_DPRA];
endmodule |
module ODDRE1
#(
parameter [0:0] IS_C_INVERTED = 1'b0,
parameter [0:0] IS_D1_INVERTED = 1'b0,
parameter [0:0] IS_D2_INVERTED = 1'b0,
parameter SIM_DEVICE = "ULTRASCALE",
parameter [0:0] SRVAL = 1'b0
)
(
input C,
input D1,
input D2,
input SR,
output Q
);
wire w_CLK = C ^ IS_C_INVERTED;
wire w_D1 = D1 ^ IS_D1_INVERTED;
wire w_D2 = D2 ^ IS_D2_INVERTED;
wire w_SR;
reg [2:0] r_SR_cdc;
reg r_Q_p;
reg r_D2_p;
reg r_Q_n;
generate
/* verilator lint_off WIDTH */
if ((SIM_DEVICE == "EVEREST") || (SIM_DEVICE == "EVEREST_ES1") || (SIM_DEVICE == "EVEREST_ES2")) begin
/* verilator lint_on WIDTH */
assign w_SR = SR;
end
else begin
always @(posedge w_CLK) begin
r_SR_cdc <= { r_SR_cdc[1:0], SR };
end
assign w_SR = |{ SR, r_SR_cdc };
end
endgenerate
always @(posedge w_CLK) begin
if (w_SR) begin
r_Q_p <= SRVAL ^ r_Q_n;
r_D2_p <= SRVAL;
end
else begin
r_Q_p <= w_D1 ^ r_Q_n;
r_D2_p <= w_D2;
end
end
always @(negedge w_CLK) begin
if (w_SR) begin
r_Q_n <= SRVAL ^ r_Q_p;
end
else begin
r_Q_n <= r_D2_p ^ r_Q_p;
end
end
assign Q = r_Q_p ^ r_Q_n;
endmodule |
module LUT5_L
#(
parameter [31:0] INIT = 32'h00000000
)
(
input wire I0, I1, I2, I3, I4,
output wire LO
);
wire [4:0] _w_idx = { I4, I3, I2, I1, I0 };
assign LO = INIT[_w_idx];
endmodule |
module LDCE
#(
parameter INIT = 1'b0
)
(
// Asynchronous clear
input wire CLR,
// Latch
input wire G,
// Latch enable
input wire GE,
// Data in
input wire D,
// Data out
output wire Q
);
reg _r_Q;
initial begin : INIT_STATE
_r_Q = INIT[0];
end
always @(CLR or G or GE or D) begin : LATCH
if (CLR) begin
_r_Q = 1'b0;
end
else if (G & GE) begin
_r_Q = D;
end
end
assign Q = _r_Q;
endmodule |
module RAM32M16
#(
parameter [63:0] INIT_A = 64'h0,
parameter [63:0] INIT_B = 64'h0,
parameter [63:0] INIT_C = 64'h0,
parameter [63:0] INIT_D = 64'h0,
parameter [63:0] INIT_E = 64'h0,
parameter [63:0] INIT_F = 64'h0,
parameter [63:0] INIT_G = 64'h0,
parameter [63:0] INIT_H = 64'h0,
parameter [0:0] IS_WCLK_INVERTED = 1'b0
)
(
// Write clock
input wire WCLK,
// Write enable
input wire WE,
// Port A
input wire [4:0] ADDRA,
input wire [1:0] DIA,
output wire [1:0] DOA,
// Port B
input wire [4:0] ADDRB,
input wire [1:0] DIB,
output wire [1:0] DOB,
// Port C
input wire [4:0] ADDRC,
input wire [1:0] DIC,
output wire [1:0] DOC,
// Port D
input wire [4:0] ADDRD,
input wire [1:0] DID,
output wire [1:0] DOD,
// Port E
input wire [4:0] ADDRE,
input wire [1:0] DIE,
output wire [1:0] DOE,
// Port F
input wire [4:0] ADDRF,
input wire [1:0] DIF,
output wire [1:0] DOF,
// Port G
input wire [4:0] ADDRG,
input wire [1:0] DIG,
output wire [1:0] DOG,
// Port H
input wire [4:0] ADDRH,
input wire [1:0] DIH,
output wire [1:0] DOH
);
// 64 x 8-bit Select RAM
reg [63:0] _r_mem_a;
reg [63:0] _r_mem_b;
reg [63:0] _r_mem_c;
reg [63:0] _r_mem_d;
reg [63:0] _r_mem_e;
reg [63:0] _r_mem_f;
reg [63:0] _r_mem_g;
reg [63:0] _r_mem_h;
// Power-up value
initial begin : INIT_STATE
_r_mem_a = INIT_A;
_r_mem_b = INIT_B;
_r_mem_c = INIT_C;
_r_mem_d = INIT_D;
_r_mem_e = INIT_E;
_r_mem_f = INIT_F;
_r_mem_g = INIT_G;
_r_mem_h = INIT_H;
end
// Synchronous memory write
generate
if (IS_WCLK_INVERTED) begin : GEN_WCLK_NEG
always @(negedge WCLK) begin : MEM_WRITE
if (WE) begin
_r_mem_a[{ ADDRH, 1'b0 } +: 2] <= DIA;
_r_mem_b[{ ADDRH, 1'b0 } +: 2] <= DIB;
_r_mem_c[{ ADDRH, 1'b0 } +: 2] <= DIC;
_r_mem_d[{ ADDRH, 1'b0 } +: 2] <= DID;
_r_mem_e[{ ADDRH, 1'b0 } +: 2] <= DIE;
_r_mem_f[{ ADDRH, 1'b0 } +: 2] <= DIF;
_r_mem_g[{ ADDRH, 1'b0 } +: 2] <= DIG;
_r_mem_h[{ ADDRH, 1'b0 } +: 2] <= DIH;
end
end
end
else begin : GEN_WCLK_POS
always @(posedge WCLK) begin : MEM_WRITE
if (WE) begin
_r_mem_a[{ ADDRH, 1'b0 } +: 2] <= DIA;
_r_mem_b[{ ADDRH, 1'b0 } +: 2] <= DIB;
_r_mem_c[{ ADDRH, 1'b0 } +: 2] <= DIC;
_r_mem_d[{ ADDRH, 1'b0 } +: 2] <= DID;
_r_mem_e[{ ADDRH, 1'b0 } +: 2] <= DIE;
_r_mem_f[{ ADDRH, 1'b0 } +: 2] <= DIF;
_r_mem_g[{ ADDRH, 1'b0 } +: 2] <= DIG;
_r_mem_h[{ ADDRH, 1'b0 } +: 2] <= DIH;
end
end
end
endgenerate
// Asynchronous memory read
assign DOA = _r_mem_a[{ ADDRA, 1'b0 } +: 2];
assign DOB = _r_mem_b[{ ADDRB, 1'b0 } +: 2];
assign DOC = _r_mem_c[{ ADDRC, 1'b0 } +: 2];
assign DOD = _r_mem_d[{ ADDRD, 1'b0 } +: 2];
assign DOE = _r_mem_e[{ ADDRE, 1'b0 } +: 2];
assign DOF = _r_mem_f[{ ADDRF, 1'b0 } +: 2];
assign DOG = _r_mem_g[{ ADDRG, 1'b0 } +: 2];
assign DOH = _r_mem_h[{ ADDRH, 1'b0 } +: 2];
endmodule |
module LDPE
#(
parameter INIT = 1'b0
)
(
// Asynchronous preset
input wire PRE,
// Latch
input wire G,
// Latch enable
input wire GE,
// Data in
input wire D,
// Data out
output wire Q
);
reg _r_Q;
initial begin : INIT_STATE
_r_Q = INIT[0];
end
always @(PRE or G or GE or D) begin : LATCH
if (PRE) begin
_r_Q = 1'b1;
end
else if (G & GE) begin
_r_Q = D;
end
end
assign Q = _r_Q;
endmodule |
module BUFGCE_DIV
#(
parameter integer BUFGCE_DIVIDE = 1,
parameter CE_TYPE = "SYNC",
parameter HARDSYNC_CLR = "FALSE",
parameter [0:0] IS_CE_INVERTED = 1'b0,
parameter [0:0] IS_CLR_INVERTED = 1'b0,
parameter [0:0] IS_I_INVERTED = 1'b0
)
(
input I,
input CE,
input CLR,
output reg O /* verilator clocker */
);
wire w_CLK = I ^ IS_I_INVERTED;
wire w_CE;
wire w_CLR;
wire [2:0] w_DIV = BUFGCE_DIVIDE[2:0] - 3'd1;
reg [2:0] r_CE_cdc;
reg [2:0] r_CLR_cdc;
reg [2:0] r_clk_div;
initial begin
r_CE_cdc = 3'b000;
r_CLR_cdc = 3'b000;
r_clk_div = 3'd0;
end
always @(negedge w_CLK) begin
if (HARDSYNC_CLR == "FALSE") begin
r_CLR_cdc <= 3'b0;
end
else begin
r_CLR_cdc <= {r_CLR_cdc[1:0], CLR ^ IS_CLR_INVERTED };
end
end
assign w_CLR = (HARDSYNC_CLR == "FALSE") ? CLR ^ IS_CLR_INVERTED
: (HARDSYNC_CLR == "TRUE") ? r_CLR_cdc[2]
: 1'b0;
always @(posedge w_CLR or negedge w_CLK) begin
if (w_CLR) begin
r_CE_cdc <= 3'b000;
end
else begin
r_CE_cdc <= { r_CE_cdc[1:0], CE ^ IS_CE_INVERTED };
end
end
assign w_CE = (CE_TYPE == "SYNC") ? r_CE_cdc[0]
: (CE_TYPE == "HARDSYNC") ? r_CE_cdc[2]
: 1'b0;
always @(posedge I) begin
if (w_CLR) begin
r_clk_div <= (w_DIV[2:1] == 2'b10) ? 3'd1 : 3'd0;
end
else if (w_CE | O) begin
if (w_DIV[2:1] == 2'b10) begin
r_clk_div <= (r_clk_div == (w_DIV + 3'd1)) ? 3'd1 : r_clk_div + 3'd1;
end
else begin
r_clk_div <= (r_clk_div == w_DIV) ? 3'd0 : r_clk_div + 3'd1;
end
end
end
always @(*) begin
casez (w_DIV)
3'b000 : O = I & w_CE;
3'b001 : O = r_clk_div[0];
3'b01? : O = r_clk_div[1];
3'b1?? : O = r_clk_div[2];
endcase
end
endmodule |
module MUXF7_D
(
input wire I0, I1,
input wire S,
output wire LO,
output wire O
);
assign LO = (S) ? I1 : I0;
assign O = (S) ? I1 : I0;
endmodule |
module IBUFDS_GTE3
#(
parameter [0:0] REFCLK_EN_TX_PATH = 1'b0,
parameter [1:0] REFCLK_HROW_CK_SEL = 2'b00,
parameter [1:0] REFCLK_ICNTL_RX = 2'b00
)
(
// Clock input
input I,
input IB,
// Clock enable
input CEB,
// Clock outputs
output O /* verilator clocker */,
output reg ODIV2 /* verilator clocker */
);
reg r_IDIV2;
initial begin
r_IDIV2 = 1'b0;
end
always @ (posedge I) begin
r_IDIV2 <= (CEB) ? 1'b0 : ~r_IDIV2;
end
always @(*) begin
case (REFCLK_HROW_CK_SEL)
2'b00 : ODIV2 = (REFCLK_EN_TX_PATH | CEB) ? 1'b0 : I;
2'b01 : ODIV2 = r_IDIV2;
default : ODIV2 = 1'b0;
endcase
end
assign O = (REFCLK_EN_TX_PATH | CEB) ? 1'b0 : I;
endmodule |
module SRLC32E
#(
parameter [31:0] INIT = 32'h0,
parameter [0:0] IS_CLK_INVERTED = 1'b0
)
(
// Clock
input wire CLK,
// Clock enable
input wire CE,
// Bit output position
input wire [4:0] A,
// Data in
input wire D,
// Data out
output wire Q,
// Cascading data out
output wire Q31
);
// 32-bit shift register
reg [31:0] _r_srl;
// Power-up value
initial begin
_r_srl = INIT;
end
// Shifter logic
generate
if (IS_CLK_INVERTED) begin : GEN_CLK_NEG
always @(negedge CLK) begin : SHIFTER_32B
if (CE) begin
_r_srl <= { _r_srl[30:0], D };
end
end
end
else begin : GEN_CLK_POS
always @(posedge CLK) begin : SHIFTER_32B
if (CE) begin
_r_srl <= { _r_srl[30:0], D };
end
end
end
endgenerate
// Data out
assign Q = _r_srl[A];
// Cascading data out
assign Q31 = _r_srl[31];
endmodule |
module VCC
(
output wire P
);
assign P = 1'b1;
endmodule |
module CFGLUT5
#(
parameter [31:0] INIT = 32'h00000000,
parameter [0:0] IS_CLK_INVERTED = 1'b0
)
(
// Clock
input wire CLK,
// Clock enable
input wire CE,
// LUT inputs
input wire I0, I1, I2, I3, I4,
// LUT configuration data input
input wire CDI,
// LUT configuration data output
output wire CDO,
// LUT4 output
output wire O5,
// LUT5 output
output wire O6
);
reg [31:0] _r_sreg;
initial begin : INIT_STATE
_r_sreg = INIT;
end
generate
if (IS_CLK_INVERTED) begin : GEN_CLK_NEG
always @(negedge CLK) begin
if (CE) begin
_r_sreg <= { _r_sreg[30:0], CDI };
end
end
end
else begin : GEN_CLK_POS
always @(posedge CLK) begin
if (CE) begin
_r_sreg <= { _r_sreg[30:0], CDI };
end
end
end
endgenerate
assign O6 = _r_sreg[{ I4, I3, I2, I1, I0 }];
assign O5 = _r_sreg[{ 1'b0, I3, I2, I1, I0 }];
assign CDO = _r_sreg[31];
endmodule |
module MUXF8
(
input wire I0, I1,
input wire S,
output wire O
);
assign O = (S) ? I1 : I0;
endmodule |
module FDSE
#(
parameter [0:0] IS_C_INVERTED = 1'b0,
parameter [0:0] IS_D_INVERTED = 1'b0,
parameter [0:0] IS_S_INVERTED = 1'b0,
parameter [0:0] INIT = 1'b1
)
(
// Clock
input wire C,
// Clock enable
input wire CE,
// Synchronous set
input wire S,
// Data in
input wire D,
// Data out
output wire Q
);
reg _r_Q;
wire _w_D = D ^ IS_D_INVERTED;
wire _w_S = S ^ IS_S_INVERTED;
initial begin : INIT_STATE
_r_Q = INIT[0];
end
generate
if (IS_C_INVERTED) begin : GEN_CLK_NEG
always @(negedge C) begin
if (_w_S) begin
_r_Q <= 1'b1;
end
else if (CE) begin
_r_Q <= _w_D;
end
end
end
else begin : GEN_CLK_POS
always @(posedge C) begin
if (_w_S) begin
_r_Q <= 1'b1;
end
else if (CE) begin
_r_Q <= _w_D;
end
end
end
endgenerate
assign Q = _r_Q;
endmodule |
module MUXF8_D
(
input wire I0, I1,
input wire S,
output wire LO,
output wire O
);
assign LO = (S) ? I1 : I0;
assign O = (S) ? I1 : I0;
endmodule |
module LUT3
#(
parameter [7:0] INIT = 8'b00000000
)
(
input wire I0, I1, I2,
output wire O
);
wire [2:0] _w_idx = { I2, I1, I0 };
assign O = INIT[_w_idx];
endmodule |
module LUT5
#(
parameter [31:0] INIT = 32'h00000000
)
(
input wire I0, I1, I2, I3, I4,
output wire O
);
wire [4:0] _w_idx = { I4, I3, I2, I1, I0 };
assign O = INIT[_w_idx];
endmodule |
module BUFG_GT
(
input I,
input [2:0] DIV,
input CE,
input CEMASK,
input CLR,
input CLRMASK,
output O /* verilator clocker */
);
reg [1:0] r_CE_cdc;
wire w_CE_msk;
reg r_CE_msk;
reg [1:0] r_CLR_cdc;
wire w_CLR_msk;
reg [2:0] r_clk_div;
/* verilator lint_off MULTIDRIVEN */
reg r_O;
/* verilator lint_on MULTIDRIVEN */
initial begin
r_CE_cdc = 2'b00;
r_CE_msk = 1'b0;
r_CLR_cdc = 2'b00;
r_clk_div = 3'd0;
end
always @(posedge I) begin
r_CE_cdc <= { r_CE_cdc[0], CE };
end
assign w_CE_msk = r_CE_cdc[1] | CEMASK;
always @(negedge I) begin
if (w_CLR_msk) begin
r_CE_msk <= 1'b0;
end
else begin
r_CE_msk <= w_CE_msk;
end
end
always @(posedge CLR or posedge I) begin
if (CLR) begin
r_CLR_cdc <= 2'b11;
end
else begin
r_CLR_cdc <= { r_CLR_cdc[0], 1'b0 };
end
end
assign w_CLR_msk = r_CLR_cdc[1] & ~CLRMASK;
always @(posedge I) begin
if (w_CLR_msk) begin
r_clk_div <= (DIV[2:1] == 2'b10) ? 3'd1 : 3'd0;
end
else if (r_CE_msk | O) begin
if (DIV[2:1] == 2'b10) begin
r_clk_div <= (r_clk_div == (DIV + 3'd1)) ? 3'd1 : r_clk_div + 3'd1;
end
else begin
r_clk_div <= (r_clk_div == DIV) ? 3'd0 : r_clk_div + 3'd1;
end
end
end
always @(posedge I) begin
casez (DIV)
3'b000 : r_O <= r_CE_msk;
3'b001 : r_O <= r_clk_div[0];
3'b01? : r_O <= r_clk_div[1];
3'b1?? : r_O <= r_clk_div[2];
endcase
end
always @(negedge I) begin
if (DIV == 3'b000) begin
r_O <= 1'b0;
end
end
assign O = r_O;
endmodule |
module IBUFDS
#(
parameter CAPACITANCE = "DONT_CARE",
parameter DIFF_TERM = "FALSE",
parameter DQS_BIAS = "FALSE",
parameter IBUF_DELAY_VALUE = "0",
parameter IBUF_LOW_PWR = "TRUE",
parameter IFD_DELAY_VALUE = "AUTO",
parameter IOSTANDARD = "DEFAULT"
)
(
// Clock input
input I,
input IB,
// Clock outputs
output O /* verilator clocker */
);
assign O = I;
endmodule |
module CARRY8
#(
parameter CARRY_TYPE = "SINGLE_CY8" // "SINGLE_CY8", "DUAL_CY4"
)
(
// Carry cascade input
input wire CI,
// Second carry input (in DUAL_CY4 mode)
input wire CI_TOP,
// Carry MUX data input
input wire [7:0] DI,
// Carry MUX select line
input wire [7:0] S,
// Carry out of each stage of the chain
output wire [7:0] CO,
// Carry chain XOR general data out
output wire [7:0] O
);
wire _w_CO0 = (S[0]) ? CI : DI[0];
wire _w_CO1 = (S[1]) ? _w_CO0 : DI[1];
wire _w_CO2 = (S[2]) ? _w_CO1 : DI[2];
wire _w_CO3 = (S[3]) ? _w_CO2 : DI[3];
wire _w_CI = (CARRY_TYPE == "DUAL_CY4") ? CI_TOP : _w_CO3;
wire _w_CO4 = (S[4]) ? _w_CI : DI[4];
wire _w_CO5 = (S[5]) ? _w_CO4 : DI[5];
wire _w_CO6 = (S[6]) ? _w_CO5 : DI[6];
wire _w_CO7 = (S[7]) ? _w_CO6 : DI[7];
assign CO = { _w_CO7, _w_CO6, _w_CO5, _w_CO4, _w_CO3, _w_CO2, _w_CO1, _w_CO0 };
assign O = S ^ { _w_CO6, _w_CO5, _w_CO4, _w_CI, _w_CO2, _w_CO1, _w_CO0, CI };
endmodule |
module FDRE
#(
parameter [0:0] IS_C_INVERTED = 1'b0,
parameter [0:0] IS_D_INVERTED = 1'b0,
parameter [0:0] IS_R_INVERTED = 1'b0,
parameter [0:0] INIT = 1'b0
)
(
// Clock
input wire C,
// Clock enable
input wire CE,
// Synchronous reset
input wire R,
// Data in
input wire D,
// Data out
output wire Q
);
reg _r_Q;
wire _w_D = D ^ IS_D_INVERTED;
wire _w_R = R ^ IS_R_INVERTED;
initial begin : INIT_STATE
_r_Q = INIT[0];
end
generate
if (IS_C_INVERTED) begin : GEN_CLK_NEG
always @(negedge C) begin
if (_w_R) begin
_r_Q <= 1'b0;
end
else if (CE) begin
_r_Q <= _w_D;
end
end
end
else begin : GEN_CLK_POS
always @(posedge C) begin
if (_w_R) begin
_r_Q <= 1'b0;
end
else if (CE) begin
_r_Q <= _w_D;
end
end
end
endgenerate
assign Q = _r_Q;
endmodule |
module FDPE
#(
parameter [0:0] IS_C_INVERTED = 1'b0,
parameter [0:0] IS_D_INVERTED = 1'b0,
parameter [0:0] IS_PRE_INVERTED = 1'b0,
parameter [0:0] INIT = 1'b0
)
(
// Clock
input wire C,
// Clock enable
input wire CE,
// Asynchronous preset
input wire PRE,
// Data in
input wire D,
// Data out
output wire Q
);
reg _r_Q;
wire _w_PRE = PRE ^ IS_PRE_INVERTED;
wire _w_D = D ^ IS_D_INVERTED;
initial begin : INIT_STATE
_r_Q = INIT[0];
end
generate
if (IS_C_INVERTED) begin : GEN_CLK_NEG
always @(negedge C or posedge _w_PRE) begin
if (_w_PRE) begin
_r_Q <= 1'b1;
end
else if (CE) begin
_r_Q <= _w_D;
end
end
end
else begin : GEN_CLK_POS
always @(posedge C or posedge _w_PRE) begin
if (_w_PRE) begin
_r_Q <= 1'b1;
end
else if (CE) begin
_r_Q <= _w_D;
end
end
end
endgenerate
assign Q = _r_Q;
endmodule |
module SRL16E
#(
parameter [15:0] INIT = 16'h0,
parameter [0:0] IS_CLK_INVERTED = 1'b0
)
(
// Clock
input wire CLK,
// Clock enable
input wire CE,
// Bit output position
input wire A0, A1, A2, A3,
// Data in
input wire D,
// Data out
output wire Q
);
wire [3:0] _w_addr = { A3, A2, A1, A0 };
// 16-bit shift register
reg [15:0] _r_srl;
// Power-up value
initial begin
_r_srl = INIT;
end
// Shifter logic
generate
if (IS_CLK_INVERTED) begin : GEN_CLK_NEG
always @(negedge CLK) begin : SHIFTER_16B
if (CE) begin
_r_srl <= { _r_srl[14:0], D };
end
end
end
else begin : GEN_CLK_POS
always @(posedge CLK) begin : SHIFTER_16B
if (CE) begin
_r_srl <= { _r_srl[14:0], D };
end
end
end
endgenerate
// Data out
assign Q = _r_srl[_w_addr];
endmodule |
module LUT5_D
#(
parameter [31:0] INIT = 32'h00000000
)
(
input wire I0, I1, I2, I3, I4,
output wire LO,
output wire O
);
wire [4:0] _w_idx = { I4, I3, I2, I1, I0 };
assign LO = INIT[_w_idx];
assign O = INIT[_w_idx];
endmodule |
module CARRY4
(
// Carry cascade input
input wire CI,
//
input wire CYINIT,
// Carry MUX data input
input wire [3:0] DI,
// Carry MUX select line
input wire [3:0] S,
// Carry out of each stage of the chain
output wire [3:0] CO,
// Carry chain XOR general data out
output wire [3:0] O
);
wire _w_CO0 = S[0] ? CI | CYINIT : DI[0];
wire _w_CO1 = S[1] ? _w_CO0 : DI[1];
wire _w_CO2 = S[2] ? _w_CO1 : DI[2];
wire _w_CO3 = S[3] ? _w_CO2 : DI[3];
assign CO = { _w_CO3, _w_CO2, _w_CO1, _w_CO0 };
assign O = S ^ { _w_CO2, _w_CO1, _w_CO0, CI | CYINIT };
endmodule |
module mult_pipe2 #(
parameter SIZE = 16,
parameter LVL = 2
)
( a, b, clk, pdt) ;
/*
* parameter 'SIZE' is the width of multiplier/multiplicand;.Application Notes 10-5
* parameter '' is the intended number of stages of the
* pipelined multiplier;
* which is typically the smallest integer greater than or equal
* to base 2 logarithm of 'SIZE'
*/
input [SIZE-1 : 0] a;
input [SIZE-1 : 0] b;
input clk;
output wire [2*SIZE-1 : 0] pdt;
reg [SIZE-1 : 0] a_int, b_int;
reg [2*SIZE-1 : 0] pdt_int [LVL-1 : 0];
integer i;
assign pdt = pdt_int [LVL-1];
always @ (posedge clk)
begin
// registering input of the multiplier
a_int <= a;
b_int <= b;
for(i=1; i <LVL ; i = i + 1)
pdt_int[i] <= pdt_int [i-1];
pdt_int[0] <= a_int * b_int;
end // always @ (posedge clk)
endmodule // pipelined_multiplier |
module psum_spad(clk, addr, we, data_port);
// 24 * 16bit
input clk;
input [4:0] addr;
input we; // write enable signal, 0: Read; 1: Write
inout [15:0] data_port;
reg [15:0] data_out;
reg [15:0] mem [23:0]; // 24 * 16bit
assign data_port = !we ? data_out : 16'bz;
always @ (posedge clk)
begin
if (we)
mem[addr] <= data_port;
else
begin
data_out <= mem[addr];
end
end
endmodule |
module dual_clock_fifo #(
parameter ADDR_WIDTH = 3,
parameter DATA_WIDTH = 16
)
(
input wire wr_rst_i,
input wire wr_clk_i,
input wire wr_en_i,
input wire [DATA_WIDTH-1:0] wr_data_i,
input wire rd_rst_i,
input wire rd_clk_i,
input wire rd_en_i,
output reg [DATA_WIDTH-1:0] rd_data_o,
output reg full_o,
output reg empty_o
);
reg [ADDR_WIDTH-1:0] wr_addr;
reg [ADDR_WIDTH-1:0] wr_addr_gray;
reg [ADDR_WIDTH-1:0] wr_addr_gray_rd;
reg [ADDR_WIDTH-1:0] wr_addr_gray_rd_r;
reg [ADDR_WIDTH-1:0] rd_addr;
reg [ADDR_WIDTH-1:0] rd_addr_gray;
reg [ADDR_WIDTH-1:0] rd_addr_gray_wr;
reg [ADDR_WIDTH-1:0] rd_addr_gray_wr_r;
function [ADDR_WIDTH-1:0] gray_conv;
input [ADDR_WIDTH-1:0] in;
begin
gray_conv = {in[ADDR_WIDTH-1],
in[ADDR_WIDTH-2:0] ^ in[ADDR_WIDTH-1:1]};
end
endfunction
always @(posedge wr_clk_i) begin
if (wr_rst_i) begin
wr_addr <= 0;
wr_addr_gray <= 0;
end else if (wr_en_i) begin
wr_addr <= wr_addr + 1'b1;
wr_addr_gray <= gray_conv(wr_addr + 1'b1);
end
end
// synchronize read address to write clock domain
always @(posedge wr_clk_i) begin
rd_addr_gray_wr <= rd_addr_gray;
rd_addr_gray_wr_r <= rd_addr_gray_wr;
end
always @(posedge wr_clk_i)
if (wr_rst_i)
full_o <= 0;
else if (wr_en_i)
full_o <= gray_conv(wr_addr + 2) == rd_addr_gray_wr_r;
else
full_o <= full_o & (gray_conv(wr_addr + 1'b1) == rd_addr_gray_wr_r);
always @(posedge rd_clk_i) begin
if (rd_rst_i) begin
rd_addr <= 0;
rd_addr_gray <= 0;
end else if (rd_en_i) begin
rd_addr <= rd_addr + 1'b1;
rd_addr_gray <= gray_conv(rd_addr + 1'b1);
end
end
// synchronize write address to read clock domain
always @(posedge rd_clk_i) begin
wr_addr_gray_rd <= wr_addr_gray;
wr_addr_gray_rd_r <= wr_addr_gray_rd;
end
always @(posedge rd_clk_i)
if (rd_rst_i)
empty_o <= 1'b1;
else if (rd_en_i)
empty_o <= gray_conv(rd_addr + 1) == wr_addr_gray_rd_r;
else
empty_o <= empty_o & (gray_conv(rd_addr) == wr_addr_gray_rd_r);
// generate dual clocked memory
reg [DATA_WIDTH-1:0] mem[(1<<ADDR_WIDTH)-1:0];
always @(posedge rd_clk_i)
if (rd_en_i)
rd_data_o <= mem[rd_addr];
always @(posedge wr_clk_i)
if (wr_en_i)
mem[wr_addr] <= wr_data_i;
endmodule |
module clacc_mem (ipf_valid, ipf_data, ipf_addr, clk);
input ipf_valid;
input [13:0] ipf_addr;
input [7:0] ipf_data;
input clk;
reg [7:0] ipf_M [0:16383];
integer i;
initial begin
for (i=0; i<=16383; i=i+1) ipf_M[i] = 0;
end
always@(negedge clk)
if (ipf_valid) ipf_M[ ipf_addr ] <= ipf_data;
endmodule |
module counter_5to3(x, y);
input [4:0] x;
output [2:0] y;
assign y[2:0] = (x[4:0] == 5'b00000) ? 3'b000 :
( x[4:0] == 5'b00001) ? 3'b001 :
( x[4:0] == 5'b00010) ? 3'b001 :
( x[4:0] == 5'b00100) ? 3'b001 :
( x[4:0] == 5'b01000) ? 3'b001 :
( x[4:0] == 5'b10000) ? 3'b001 :
( x[4:0] == 5'b00011) ? 3'b010 :
( x[4:0] == 5'b00110) ? 3'b010 :
( x[4:0] == 5'b01100) ? 3'b010 :
( x[4:0] == 5'b11000) ? 3'b010 :
( x[4:0] == 5'b00101) ? 3'b010 :
( x[4:0] == 5'b01010) ? 3'b010 :
( x[4:0] == 5'b10100) ? 3'b010 :
( x[4:0] == 5'b01001) ? 3'b010 :
( x[4:0] == 5'b10010) ? 3'b010 :
( x[4:0] == 5'b10001) ? 3'b010 :
( x[4:0] == 5'b11100) ? 3'b011 :
( x[4:0] == 5'b11001) ? 3'b011 :
( x[4:0] == 5'b10011) ? 3'b011 :
( x[4:0] == 5'b00111) ? 3'b011 :
( x[4:0] == 5'b11010) ? 3'b011 :
( x[4:0] == 5'b10101) ? 3'b011 :
( x[4:0] == 5'b01011) ? 3'b011 :
( x[4:0] == 5'b10110) ? 3'b011 :
( x[4:0] == 5'b01101) ? 3'b011 :
( x[4:0] == 5'b01110) ? 3'b011 :
( x[4:0] == 5'b01111) ? 3'b100 :
( x[4:0] == 5'b10111) ? 3'b100 :
( x[4:0] == 5'b11011) ? 3'b100 :
( x[4:0] == 5'b11101) ? 3'b100 :
( x[4:0] == 5'b11110) ? 3'b100 :
( x[4:0] == 5'b11111) ? 3'b101 : 3'b111;
endmodule |
module bs_mult_slice(clk, xy, pin, cin, rin, x, y, pout, cout, rout, lastbit);
input clk;
input xy, pin, cin, rin, x, y, lastbit;
output pout, cout, rout;
wire [2:0] cout_int;
reg cout;
reg rout;
wire a, b;
reg pin_delay;
reg x_delay;
reg y_delay;
reg cout1_delay;
assign a = x_delay & y;
assign b = x & y_delay;
assign pout = (rin == 1'b1) ? xy : cout_int[0];
counter_5to3 I0(.x({a, b, pin_delay, cin, cout1_delay}), .y(cout_int));
always @ (posedge clk)
begin
if(lastbit)
begin
x_delay <= 1'b0;
y_delay <= 1'b0;
pin_delay <= 1'b0;
cout1_delay <= 1'b0;
cout <= 1'b0;
rout <= 1'b0;
end
else
begin
if(rin)
begin
x_delay <= x;
y_delay <= y;
end
pin_delay <= pin;
cout1_delay <= cout_int[1];
cout <= cout_int[2];
rout <= rin;
end
end
endmodule |
module filter_spad(clk, addr, we, data_port);
// 224 * 16bit
input clk;
input [7:0] addr;
input we; // write enable signal, 0: Read; 1: Write
inout [15:0] data_port;
reg [15:0] data_out;
reg [15:0] mem [223:0]; // 12 * 16bit
assign data_port = !we ? data_out : 16'bz;
always @ (posedge clk)
begin
if (we)
mem[addr] <= data_port;
else
begin
data_out <= mem[addr];
end
end
endmodule |
module ifmap_spad(clk, addr, we, data_port);
// 12 * 16bit
input clk;
input [3:0] addr;
input we; // write enable signal, 0: Read; 1: Write
inout [15:0] data_port;
reg [15:0] data_out;
reg [15:0] mem [11:0]; // 12 * 16bit
assign data_port = !we ? data_out : 16'bz;
always @ (posedge clk)
begin
if (we)
mem[addr] <= data_port;
else
begin
data_out <= mem[addr];
end
end
endmodule |
module bs_adder(x, y, clk, z, rst);
input x, y, clk, rst;
output reg z;
reg cin_int;
wire sum_int;
fa I0(.x(x), .y(y), .cin(cin_int), .cout(cout_int), .sum(sum_int));
always @ (posedge clk)
begin
if(rst)
begin
cin_int <= 1'b0;
z <= 1'b0;
end
else
begin
cin_int <= cout_int;
z <= sum_int;
end
end
endmodule |
module bs_mult(clk, x, y, p, firstbit, lastbit);
input clk;
input x, y, firstbit, lastbit;
output p;
assign xy = x & y;
wire [29:0] pout;
wire [30:0] rout;
wire [30:0] cout;
bs_mult_slice I0(.clk(clk), .xy(xy), .pin(pout[0]), .cin(1'b0),
.rin(firstbit), .x(x), .y(y), .pout(p), .cout(cout[0]),
.rout(rout[0]), .lastbit(lastbit));
bs_mult_slice I1(.clk(clk), .xy(xy), .pin(pout[1]), .cin(cout[0]),
.rin(rout[0]), .x(x), .y(y), .pout(pout[0]), .cout(cout[1]),
.rout(rout[1]), .lastbit(lastbit));
bs_mult_slice I2(.clk(clk), .xy(xy), .pin(pout[2]), .cin(cout[1]),
.rin(rout[1]), .x(x), .y(y), .pout(pout[1]), .cout(cout[2]),
.rout(rout[2]), .lastbit(lastbit));
bs_mult_slice I3(.clk(clk), .xy(xy), .pin(pout[3]), .cin(cout[2]),
.rin(rout[2]), .x(x), .y(y), .pout(pout[2]), .cout(cout[3]),
.rout(rout[3]), .lastbit(lastbit));
bs_mult_slice I4(.clk(clk), .xy(xy), .pin(pout[4]), .cin(cout[3]),
.rin(rout[3]), .x(x), .y(y), .pout(pout[3]), .cout(cout[4]),
.rout(rout[4]), .lastbit(lastbit));
bs_mult_slice I5(.clk(clk), .xy(xy), .pin(pout[5]), .cin(cout[4]),
.rin(rout[4]), .x(x), .y(y), .pout(pout[4]), .cout(cout[5]),
.rout(rout[5]), .lastbit(lastbit));
bs_mult_slice I6(.clk(clk), .xy(xy), .pin(pout[6]), .cin(cout[5]),
.rin(rout[5]), .x(x), .y(y), .pout(pout[5]), .cout(cout[6]),
.rout(rout[6]), .lastbit(lastbit));
bs_mult_slice I7(.clk(clk), .xy(xy), .pin(pout[7]), .cin(cout[6]),
.rin(rout[6]), .x(x), .y(y), .pout(pout[6]), .cout(cout[7]),
.rout(rout[7]), .lastbit(lastbit));
bs_mult_slice I8(.clk(clk), .xy(xy), .pin(pout[8]), .cin(cout[7]),
.rin(rout[7]), .x(x), .y(y), .pout(pout[7]), .cout(cout[8]),
.rout(rout[8]), .lastbit(lastbit));
bs_mult_slice I9(.clk(clk), .xy(xy), .pin(pout[9]), .cin(cout[8]),
.rin(rout[8]), .x(x), .y(y), .pout(pout[8]), .cout(cout[9]),
.rout(rout[9]), .lastbit(lastbit));
bs_mult_slice I10(.clk(clk), .xy(xy), .pin(pout[10]), .cin(cout[9]),
.rin(rout[9]), .x(x), .y(y), .pout(pout[9]), .cout(cout[10]),
.rout(rout[10]), .lastbit(lastbit));
bs_mult_slice I11(.clk(clk), .xy(xy), .pin(pout[11]), .cin(cout[10]),
.rin(rout[10]), .x(x), .y(y), .pout(pout[10]), .cout(cout[11]),
.rout(rout[11]), .lastbit(lastbit));
bs_mult_slice I12(.clk(clk), .xy(xy), .pin(pout[12]), .cin(cout[11]),
.rin(rout[11]), .x(x), .y(y), .pout(pout[11]), .cout(cout[12]),
.rout(rout[12]), .lastbit(lastbit));
bs_mult_slice I13(.clk(clk), .xy(xy), .pin(pout[13]), .cin(cout[12]),
.rin(rout[12]), .x(x), .y(y), .pout(pout[12]), .cout(cout[13]),
.rout(rout[13]), .lastbit(lastbit));
bs_mult_slice I14(.clk(clk), .xy(xy), .pin(pout[14]), .cin(cout[13]),
.rin(rout[13]), .x(x), .y(y), .pout(pout[13]), .cout(cout[14]),
.rout(rout[14]), .lastbit(lastbit));
bs_mult_slice I15(.clk(clk), .xy(xy), .pin(pout[15]), .cin(cout[14]),
.rin(rout[14]), .x(x), .y(y), .pout(pout[14]), .cout(cout[15]),
.rout(rout[15]), .lastbit(lastbit));
bs_mult_slice I16(.clk(clk), .xy(xy), .pin(pout[16]), .cin(cout[15]),
.rin(rout[15]), .x(x), .y(y), .pout(pout[15]), .cout(cout[16]),
.rout(rout[16]), .lastbit(lastbit));
bs_mult_slice I17(.clk(clk), .xy(xy), .pin(pout[17]), .cin(cout[16]),
.rin(rout[16]), .x(x), .y(y), .pout(pout[16]), .cout(cout[17]),
.rout(rout[17]), .lastbit(lastbit));
bs_mult_slice I18(.clk(clk), .xy(xy), .pin(pout[18]), .cin(cout[17]),
.rin(rout[17]), .x(x), .y(y), .pout(pout[17]), .cout(cout[18]),
.rout(rout[18]), .lastbit(lastbit));
bs_mult_slice I19(.clk(clk), .xy(xy), .pin(pout[19]), .cin(cout[18]),
.rin(rout[18]), .x(x), .y(y), .pout(pout[18]), .cout(cout[19]),
.rout(rout[19]), .lastbit(lastbit));
bs_mult_slice I20(.clk(clk), .xy(xy), .pin(pout[20]), .cin(cout[19]),
.rin(rout[19]), .x(x), .y(y), .pout(pout[19]), .cout(cout[20]),
.rout(rout[20]), .lastbit(lastbit));
bs_mult_slice I21(.clk(clk), .xy(xy), .pin(pout[21]), .cin(cout[20]),
.rin(rout[20]), .x(x), .y(y), .pout(pout[20]), .cout(cout[21]),
.rout(rout[21]), .lastbit(lastbit));
bs_mult_slice I22(.clk(clk), .xy(xy), .pin(pout[22]), .cin(cout[21]),
.rin(rout[21]), .x(x), .y(y), .pout(pout[21]), .cout(cout[22]),
.rout(rout[22]), .lastbit(lastbit));
bs_mult_slice I23(.clk(clk), .xy(xy), .pin(pout[23]), .cin(cout[22]),
.rin(rout[22]), .x(x), .y(y), .pout(pout[22]), .cout(cout[23]),
.rout(rout[23]), .lastbit(lastbit));
bs_mult_slice I24(.clk(clk), .xy(xy), .pin(pout[24]), .cin(cout[23]),
.rin(rout[23]), .x(x), .y(y), .pout(pout[23]), .cout(cout[24]),
.rout(rout[24]), .lastbit(lastbit));
bs_mult_slice I25(.clk(clk), .xy(xy), .pin(pout[25]), .cin(cout[24]),
.rin(rout[24]), .x(x), .y(y), .pout(pout[24]), .cout(cout[25]),
.rout(rout[25]), .lastbit(lastbit));
bs_mult_slice I26(.clk(clk), .xy(xy), .pin(pout[26]), .cin(cout[25]),
.rin(rout[25]), .x(x), .y(y), .pout(pout[25]), .cout(cout[26]),
.rout(rout[26]), .lastbit(lastbit));
bs_mult_slice I27(.clk(clk), .xy(xy), .pin(pout[27]), .cin(cout[26]),
.rin(rout[26]), .x(x), .y(y), .pout(pout[26]), .cout(cout[27]),
.rout(rout[27]), .lastbit(lastbit));
bs_mult_slice I28(.clk(clk), .xy(xy), .pin(pout[28]), .cin(cout[27]),
.rin(rout[27]), .x(x), .y(y), .pout(pout[27]), .cout(cout[28]),
.rout(rout[28]), .lastbit(lastbit));
bs_mult_slice I29(.clk(clk), .xy(xy), .pin(pout[29]), .cin(cout[28]),
.rin(rout[28]), .x(x), .y(y), .pout(pout[28]), .cout(cout[29]),
.rout(rout[29]), .lastbit(lastbit));
wire pin_last = (rout[30] == 1)? xy : cout[30] ;
bs_mult_slice I30(.clk(clk), .xy(xy), .pin(pin_last), .cin(cout[29]),
.rin(rout[29]), .x(x), .y(y), .pout(pout[29]), .cout(cout[30]),
.rout(rout[30]), .lastbit(lastbit));
endmodule |
module ha(x, y, cout, sum);
input x, y;
output cout, sum;
assign sum = x ^ y;
assign cout = x & y;
endmodule |
module fa(x, y, cin, cout, sum);
input x, y, cin;
output cout, sum;
wire cout_int, cout_int2;
wire sum_int;
ha I0(.x(x), .y(y), .cout(cout_int), .sum(sum_int));
ha I1(.x(sum_int), .y(cin), .cout(cout_int2), .sum(sum));
assign cout = cout_int | cout_int2;
endmodule |
module multiplier(
input_a,
input_b,
input_a_stb,
input_b_stb,
output_z_ack,
clk,
rst,
output_z,
output_z_stb,
input_a_ack,
input_b_ack);
input clk;
input rst;
input [31:0] input_a;
input input_a_stb;
output input_a_ack;
input [31:0] input_b;
input input_b_stb;
output input_b_ack;
output reg [31:0] output_z;
output output_z_stb;
input output_z_ack;
reg s_output_z_stb;
// reg [31:0] output_z;
reg s_input_a_ack;
reg s_input_b_ack;
reg [3:0] state;
parameter get_a = 4'd0,
get_b = 4'd1,
unpack = 4'd2,
special_cases = 4'd3,
normalise_a = 4'd4,
normalise_b = 4'd5,
multiply_0 = 4'd6,
multiply_1 = 4'd7,
normalise_1 = 4'd8,
normalise_2 = 4'd9,
round = 4'd10,
pack = 4'd11,
put_z = 4'd12;
reg [31:0] a, b, z;
reg [23:0] a_m, b_m, z_m;
reg [9:0] a_e, b_e, z_e;
reg a_s, b_s, z_s;
reg guard, round_bit, sticky;
reg [49:0] product;
always @(posedge clk)
begin
case(state)
get_a:
begin
s_input_a_ack <= 1;
if (s_input_a_ack && input_a_stb) begin
a <= input_a;
s_input_a_ack <= 0;
state <= get_b;
end
end
get_b:
begin
s_input_b_ack <= 1;
if (s_input_b_ack && input_b_stb) begin
b <= input_b;
s_input_b_ack <= 0;
state <= unpack;
end
end
unpack:
begin
a_m <= a[22 : 0];
b_m <= b[22 : 0];
a_e <= a[30 : 23] - 127;
b_e <= b[30 : 23] - 127;
a_s <= a[31];
b_s <= b[31];
state <= special_cases;
end
special_cases:
begin
//if a is NaN or b is NaN return NaN
if ((a_e == 128 && a_m != 0) || (b_e == 128 && b_m != 0)) begin
z[31] <= 1;
z[30:23] <= 255;
z[22] <= 1;
z[21:0] <= 0;
state <= put_z;
//if a is inf return inf
end else if (a_e == 128) begin
z[31] <= a_s ^ b_s;
z[30:23] <= 255;
z[22:0] <= 0;
//if b is zero return NaN
if (($signed(b_e) == -127) && (b_m == 0)) begin
z[31] <= 1;
z[30:23] <= 255;
z[22] <= 1;
z[21:0] <= 0;
end
state <= put_z;
//if b is inf return inf
end else if (b_e == 128) begin
z[31] <= a_s ^ b_s;
z[30:23] <= 255;
z[22:0] <= 0;
//if a is zero return NaN
if (($signed(a_e) == -127) && (a_m == 0)) begin
z[31] <= 1;
z[30:23] <= 255;
z[22] <= 1;
z[21:0] <= 0;
end
state <= put_z;
//if a is zero return zero
end else if (($signed(a_e) == -127) && (a_m == 0)) begin
z[31] <= a_s ^ b_s;
z[30:23] <= 0;
z[22:0] <= 0;
state <= put_z;
//if b is zero return zero
end else if (($signed(b_e) == -127) && (b_m == 0)) begin
z[31] <= a_s ^ b_s;
z[30:23] <= 0;
z[22:0] <= 0;
state <= put_z;
end else begin
//Denormalised Number
if ($signed(a_e) == -127) begin
a_e <= -126;
end else begin
a_m[23] <= 1;
end
//Denormalised Number
if ($signed(b_e) == -127) begin
b_e <= -126;
end else begin
b_m[23] <= 1;
end
state <= normalise_a;
end
end
normalise_a:
begin
if (a_m[23]) begin
state <= normalise_b;
end else begin
a_m <= a_m << 1;
a_e <= a_e - 1;
end
end
normalise_b:
begin
if (b_m[23]) begin
state <= multiply_0;
end else begin
b_m <= b_m << 1;
b_e <= b_e - 1;
end
end
multiply_0:
begin
z_s <= a_s ^ b_s;
z_e <= a_e + b_e + 1;
product <= a_m * b_m * 4;
state <= multiply_1;
end
multiply_1:
begin
z_m <= product[49:26];
guard <= product[25];
round_bit <= product[24];
sticky <= (product[23:0] != 0);
state <= normalise_1;
end
normalise_1:
begin
if (z_m[23] == 0) begin
z_e <= z_e - 1;
z_m <= z_m << 1;
z_m[0] <= guard;
guard <= round_bit;
round_bit <= 0;
end else begin
state <= normalise_2;
end
end
normalise_2:
begin
if ($signed(z_e) < -126) begin
z_e <= z_e + 1;
z_m <= z_m >> 1;
guard <= z_m[0];
round_bit <= guard;
sticky <= sticky | round_bit;
end else begin
state <= round;
end
end
round:
begin
if (guard && (round_bit | sticky | z_m[0])) begin
z_m <= z_m + 1;
if (z_m == 24'hffffff) begin
z_e <=z_e + 1;
end
end
state <= pack;
end
pack:
begin
z[22 : 0] <= z_m[22:0];
z[30 : 23] <= z_e[7:0] + 127;
z[31] <= z_s;
if ($signed(z_e) == -126 && z_m[23] == 0) begin
z[30 : 23] <= 0;
end
//if overflow occurs, return inf
if ($signed(z_e) > 127) begin
z[22 : 0] <= 0;
z[30 : 23] <= 255;
z[31] <= z_s;
end
state <= put_z;
end
put_z:
begin
s_output_z_stb <= 1;
output_z <= z;
if (s_output_z_stb && output_z_ack) begin
s_output_z_stb <= 0;
state <= get_a;
end
end
endcase
if (rst == 1) begin
state <= get_a;
s_input_a_ack <= 0;
s_input_b_ack <= 0;
s_output_z_stb <= 0;
output_z <= 0;
a <= 0;
b <= 0;
z <= 0;
a_m <= 0;
b_m <= 0;
z_m <= 0;
a_e <= 0;
b_e <= 0;
z_m <= 0;
end
end
assign input_a_ack = s_input_a_ack;
assign input_b_ack = s_input_b_ack;
assign output_z_stb = s_output_z_stb;
// assign output_z = output_z;
endmodule |
module adder(
input_a,
input_b,
input_a_stb,
input_b_stb,
output_z_ack,
clk,
rst,
output_z,
output_z_stb,
input_a_ack,
input_b_ack);
input clk;
input rst;
input [31:0] input_a;
input input_a_stb;
output input_a_ack;
input [31:0] input_b;
input input_b_stb;
output input_b_ack;
output reg [31:0] output_z;
output output_z_stb;
input output_z_ack;
reg s_output_z_stb;
// reg [31:0] output_z;
reg s_input_a_ack;
reg s_input_b_ack;
reg [3:0] state;
parameter get_a = 4'd0,
get_b = 4'd1,
unpack = 4'd2,
special_cases = 4'd3,
align = 4'd4,
add_0 = 4'd5,
add_1 = 4'd6,
normalise_1 = 4'd7,
normalise_2 = 4'd8,
round = 4'd9,
pack = 4'd10,
put_z = 4'd11;
reg [31:0] a, b, z;
reg [26:0] a_m, b_m;
reg [23:0] z_m;
reg [9:0] a_e, b_e, z_e;
reg a_s, b_s, z_s;
reg guard, round_bit, sticky;
reg [27:0] sum;
always @(posedge clk or negedge rst)
begin
if (rst == 1) begin
state <= get_a;
s_input_a_ack <= 0;
s_input_b_ack <= 0;
s_output_z_stb <= 0;
output_z <= 0;
a <= 0;
b <= 0;
z <= 0;
a_m <= 0;
b_m <= 0;
z_m <= 0;
a_e <= 0;
b_e <= 0;
z_m <= 0;
end
else begin
case(state)
get_a:
begin
s_input_a_ack <= 1;
if (s_input_a_ack && input_a_stb) begin
a <= input_a;
s_input_a_ack <= 0;
state <= get_b;
end
end
get_b:
begin
s_input_b_ack <= 1;
if (s_input_b_ack && input_b_stb) begin
b <= input_b;
s_input_b_ack <= 0;
state <= unpack;
end
end
unpack:
begin
a_m <= {a[22 : 0], 3'd0};
b_m <= {b[22 : 0], 3'd0};
a_e <= a[30 : 23] - 127;
b_e <= b[30 : 23] - 127;
a_s <= a[31];
b_s <= b[31];
state <= special_cases;
end
special_cases:
begin
//if a is NaN or b is NaN return NaN
if ((a_e == 128 && a_m != 0) || (b_e == 128 && b_m != 0)) begin
z[31] <= 1;
z[30:23] <= 255;
z[22] <= 1;
z[21:0] <= 0;
state <= put_z;
//if a is inf return inf
end else if (a_e == 128) begin
z[31] <= a_s;
z[30:23] <= 255;
z[22:0] <= 0;
//if a is inf and signs don't match return nan
if ((b_e == 128) && (a_s != b_s)) begin
z[31] <= b_s;
z[30:23] <= 255;
z[22] <= 1;
z[21:0] <= 0;
end
state <= put_z;
//if b is inf return inf
end else if (b_e == 128) begin
z[31] <= b_s;
z[30:23] <= 255;
z[22:0] <= 0;
state <= put_z;
//if a is zero return b
end else if ((($signed(a_e) == -127) && (a_m == 0)) && (($signed(b_e) == -127) && (b_m == 0))) begin
z[31] <= a_s & b_s;
z[30:23] <= b_e[7:0] + 127;
z[22:0] <= b_m[26:3];
state <= put_z;
//if a is zero return b
end else if (($signed(a_e) == -127) && (a_m == 0)) begin
z[31] <= b_s;
z[30:23] <= b_e[7:0] + 127;
z[22:0] <= b_m[26:3];
state <= put_z;
//if b is zero return a
end else if (($signed(b_e) == -127) && (b_m == 0)) begin
z[31] <= a_s;
z[30:23] <= a_e[7:0] + 127;
z[22:0] <= a_m[26:3];
state <= put_z;
end else begin
//Denormalised Number
if ($signed(a_e) == -127) begin
a_e <= -126;
end else begin
a_m[26] <= 1;
end
//Denormalised Number
if ($signed(b_e) == -127) begin
b_e <= -126;
end else begin
b_m[26] <= 1;
end
state <= align;
end
end
align:
begin
if ($signed(a_e) > $signed(b_e)) begin
b_e <= b_e + 1;
b_m <= b_m >> 1;
b_m[0] <= b_m[0] | b_m[1];
end else if ($signed(a_e) < $signed(b_e)) begin
a_e <= a_e + 1;
a_m <= a_m >> 1;
a_m[0] <= a_m[0] | a_m[1];
end else begin
state <= add_0;
end
end
add_0:
begin
z_e <= a_e;
if (a_s == b_s) begin
sum <= a_m + b_m;
z_s <= a_s;
end else begin
if (a_m >= b_m) begin
sum <= a_m - b_m;
z_s <= a_s;
end else begin
sum <= b_m - a_m;
z_s <= b_s;
end
end
state <= add_1;
end
add_1:
begin
if (sum[27]) begin
z_m <= sum[27:4];
guard <= sum[3];
round_bit <= sum[2];
sticky <= sum[1] | sum[0];
z_e <= z_e + 1;
end else begin
z_m <= sum[26:3];
guard <= sum[2];
round_bit <= sum[1];
sticky <= sum[0];
end
state <= normalise_1;
end
normalise_1:
begin
if (z_m[23] == 0 && $signed(z_e) > -126) begin
z_e <= z_e - 1;
z_m <= z_m << 1;
z_m[0] <= guard;
guard <= round_bit;
round_bit <= 0;
end else begin
state <= normalise_2;
end
end
normalise_2:
begin
if ($signed(z_e) < -126) begin
z_e <= z_e + 1;
z_m <= z_m >> 1;
guard <= z_m[0];
round_bit <= guard;
sticky <= sticky | round_bit;
end else begin
state <= round;
end
end
round:
begin
if (guard && (round_bit | sticky | z_m[0])) begin
z_m <= z_m + 1;
if (z_m == 24'hffffff) begin
z_e <=z_e + 1;
end
end
state <= pack;
end
pack:
begin
z[22 : 0] <= z_m[22:0];
z[30 : 23] <= z_e[7:0] + 127;
z[31] <= z_s;
if ($signed(z_e) == -126 && z_m[23] == 0) begin
z[30 : 23] <= 0;
end
//if overflow occurs, return inf
if ($signed(z_e) > 127) begin
z[22 : 0] <= 0;
z[30 : 23] <= 255;
z[31] <= z_s;
end
state <= put_z;
end
put_z:
begin
s_output_z_stb <= 1;
output_z <= z;
if (s_output_z_stb && output_z_ack) begin
s_output_z_stb <= 0;
state <= get_a;
end
end
endcase
end
end
assign input_a_ack = s_input_a_ack;
assign input_b_ack = s_input_b_ack;
assign output_z_stb = s_output_z_stb;
// assign output_z = output_z;
endmodule |
module exponential (
input wire Clock,
input wire Reset,
input wire Str,
input wire [`DATALENGTH-1:0] Datain,
output reg Ack,
output reg [`DATALENGTH-1:0] DataOut
);
wire [`DATALENGTH-1:0] one, oversix, half;
//reg [`DATALENGTH-1:0] T0R,T1R,T2R,TsR,TdR,TcR, DoR;
reg [`DATALENGTH-1:0] Count;
reg [`DATALENGTH-1:0] T0;
wire [`DATALENGTH-1:0] T1,T2,Ts,Td,Tc,To,Tsh;
wire wa_add_1,wb_add_1,wz_add_1;
wire wa_add_2,wb_add_2,wz_add_2;
wire wa_add_3,wb_add_3,wz_add_3;
wire wa_mul_1,wb_mul_1,wz_mul_1;
wire wa_mul_2,wb_mul_2,wz_mul_2;
wire wa_sh_1,wb_sh_1,wz_sh_1;
wire wa_div_1,wb_div_1,wz_div_1;
assign one = 32'h3f800000;
assign oversix = 32'h3e2aaaab ;
assign half = 32'h3f000000;
adder A1 (
one,
T0,
Str,
Str,
Str,
Clock,
Reset,
T1,
wz_add_1,
wa_add_1,
wb_add_1);
multiplier Ms (
T0,
T0,
wa_add_1,
wb_add_1,
wz_add_1,
Clock,
Reset,
Ts,
wz_mul_1,
wa_mul_1,
wb_mul_1);
multiplier Msh (
half,
Ts,
wa_mul_1,
wb_mul_1,
wz_mul_1,
Clock,
Reset,
Tsh,
wz_sh_1,
wa_sh_1,
wb_sh_1);
adder A2 (
T1,
Tsh,
wa_sh_1,
wb_sh_1,
wz_sh_1,
Clock,
Reset,
T2,
wz_add_2,
wa_add_2,
wb_add_2);
multiplier Mc (
Ts,
Ts,
wa_add_2,
wb_add_2,
wz_add_2,
Clock,
Reset,
Tc,
wz_mul_2,
wa_mul_2,
wb_mul_2);
multiplier Dm (
Tc,
oversix,
wa_mul_2,
wb_mul_2,
wz_mul_2,
Clock,
Reset,
Td,
wz_div_1,
wa_div_1,
wb_div_1
);
adder A3 (
Td,
T2,
wa_div_1,
wb_div_1,
wz_div_1,
Clock,
Reset,
To,
wz_add_3,
wa_add_3,
wb_add_3);
integer i;
always @(posedge Clock or negedge Reset) begin
if(Reset) begin
T0 <= 0;
DataOut <= 0;
Ack <= 0;
Count <= 0;
// T1 <= 0;
// T2 <= 0;
// Ts <= 0;
// Tc <= 0;
// Td <= 0;
end else begin
if (Str) begin
T0 <= Datain;
DataOut <= To;
if (Count == 140)
Ack <= 1;
Count <= Count +1;
end
else
T0 <= 32'hz;
// T1R <= T1;
// TsR <= Ts;
// T2R <= T2;
// TcR <= Tc;
// T1 <= T0 + 1 ;
// Ts <= T0 * T0;
// T2 <= T1 + (Ts >> 2);
// Tc <= Ts* T0;
// DataOut <= T2 + (Tc /6);
end
end
endmodule |
module adder_tb();
reg clk;
reg rst;
reg [31:0] input_a;
reg [31:0] input_b;
reg input_a_stb;
reg input_b_stb;
reg output_z_ack;
wire input_a_ack;
wire input_b_ack;
wire output_z_stb;
wire [31:0] output_z;
initial begin
clk = 1;
rst = 1;
input_a_stb = 0;
input_b_stb = 0;
output_z_ack = 0;
#10
rst = 0;
////////////////////////////
input_a_stb = 1;
input_b_stb = 1;
output_z_ack = 1;
// #5
input_a = 32'h3f800000;
input_b = 32'h3f800000;
#32
// input_a_stb = 0;
// input_b_stb = 0;
// output_z_ack = 0;
// #10
////////////////////////////
// input_a_stb = 0;
// input_b_stb = 0;
// output_z_ack = 0;
// ////////////////////////////
// #10
// input_a_stb = 1;
// input_b_stb = 1;
// output_z_ack = 1;
// #5
input_a = 32'h3f000000;
input_b = 32'h3f000000;
#32
input_a = 32'h3f000000;
input_b = 32'hbf000000;
end
adder DUT (
input_a,
input_b,
input_a_stb,
input_b_stb,
output_z_ack,
clk,
rst,
output_z,
output_z_stb,
input_a_ack,
input_b_ack);
always
#1 clk = ~clk;
endmodule // adder_tb |
module exponential_tb ();
reg Clock;
reg Reset;
reg Str;
reg [`DATALENGTH-1:0] Datain;
wire [`DATALENGTH-1:0] DataOut;
wire Ack;
exponential DUT (Clock, Reset,Str, Datain ,Ack, DataOut);
initial begin
Clock = 0;
Reset = 1;
Str = 0;
#10
Reset = 0;
Str = 1;
Datain = 32'h3f800000;
#50
$finish;
end
always
#1 Clock = ~Clock;
endmodule |
module softmax(
input wire Clock,
input wire Reset,
input wire Start,
input wire [`DATALENGTH-1:0] Datain,
input wire [`INPUTMAX:0] N,
output reg [`DATALENGTH-1:0] Dataout
);
integer m;
// reg [`DATALENGTH-1:0] Dataout;
reg [`DATALENGTH-1:0] InputBuffer[2**`INPUTMAX - 1:0];
reg [`DATALENGTH-1:0] DivBuffer[2**`INPUTMAX - 1:0];
reg [`DATALENGTH-1:0] OutputBuffer[2**`INPUTMAX -1 :0];
reg [`DATALENGTH-1:0] Acc;
reg [`DATALENGTH-1:0] Arg;
wire [`DATALENGTH-1:0] Acc_w;
reg [3:0]Str;
wire [`DATALENGTH-1:0] InputBuffer_w[2**`INPUTMAX -1 :0];
wire [`DATALENGTH-1:0] OutputBuffer_w[2**`INPUTMAX -1 :0];
wire [3:0]Ack;
reg Str_Add_a;
reg Str_Add_b;
reg Str_Add_z;
wire Ack_add1;
wire Ack_add2;
wire Ack_add3;
reg Ack_div1;
reg Ack_div2;
reg Ack_div3;
wire [3:0]Ack_div_a;
wire [3:0]Ack_div_b;
wire [3:0]Ack_div_z;
reg [`INPUTMAX:0] Counter;
reg [`INPUTMAX:0] C,C_add;
reg [2:0] NextState;
genvar i;
generate
for (i = 0; i <= 2**`INPUTMAX -1; i = i +1) begin
exponential exp (
Clock,
Reset,
Str[i],
InputBuffer[i],
Ack[i],
InputBuffer_w[i]
) ;
end
endgenerate
// genvar j;
// generate
// for (j = 0; j < `NUMBER; j= j+1) begin
adder add (
Arg,
Acc,
Str_Add_a,
Str_Add_b,
Str_Add_z,
Clock,
Reset,
Acc_w,
Ack_add3,
Ack_add1,
Ack_add2
) ;
// end
// endgenerate
genvar k;
generate
for (k = 0; k <= 2**`INPUTMAX -1; k= k+1) begin
divider div (
DivBuffer[k],
Acc,
Ack_div1,
Ack_div2,
Ack_div3,
Clock,
Reset,
OutputBuffer_w[k],
Ack_div_z[k],
Ack_div_a[k],
Ack_div_a[k]
) ;
end
endgenerate
always @(posedge Clock or negedge Reset) begin
if (Reset) begin
// reset
for (m = 0; m <= 2**`INPUTMAX -1;m = m+1)begin
InputBuffer[m] <= 0;
OutputBuffer[m] <= 0;
DivBuffer[m] <= 0;
end
Counter <= 0;
C <= 0;
Arg <= 0;
C_add <= 0;
Dataout <= 0;
Acc <= 0;
Str <= 0;
Ack_div1 <=0;
Ack_div2 <=0;
Ack_div3 <=0;
Str_Add_a <= 0;
Str_Add_b <= 0;
Str_Add_z <= 0;
NextState <= `IDLE;
end
else begin
case(NextState)
`IDLE: begin
if (Start)
NextState <= `INPUTSTREAM;
else
NextState <= `IDLE;
end
`INPUTSTREAM: begin
if (Counter <= N) begin
InputBuffer[Counter] <= Datain;
Counter <= Counter + 1;
NextState <= `INPUTSTREAM;
end
else begin
NextState <= `EXP;
Str <= 4'b1111;
end
end
`EXP: begin
if(Ack == 4'b1111)begin
for (m = 0; m <= N;m = m+1)
DivBuffer[m] <= InputBuffer_w[m];
NextState <= `ADD;
Str_Add_a <= 1 ;
Str_Add_b <= 1 ;
Str_Add_z <= 1 ;
end
else begin
NextState <= `EXP;
end
end
`ADD: begin
if (Ack_add2 || Ack_add1 || Ack_add3) begin
C_add <= C_add + 1;
end
if (C < 2**`INPUTMAX+1 ) begin
Arg <= DivBuffer[C];
if (C_add == 4) begin
Acc <= Acc_w;
C <= C+1;
C_add <= 0;
end
NextState <= `ADD;
end
else begin
Str_Add_a <= 1 ;
Str_Add_b <= 1 ;
Str_Add_z <= 1 ;
NextState <= `DIV;
end
end
`DIV: begin
Ack_div1 <= 1;
Ack_div2 <= 1;
Ack_div3 <= 1;
if (Ack_div_z == 4'b1111) begin
for (m = 0; m < N;m = m+1)begin
OutputBuffer[m] <= OutputBuffer_w[m];
end
NextState <= `OUTPUTSTREAM;
end
else
NextState <= `DIV;
end
`OUTPUTSTREAM: begin
Counter <= Counter - 1;
if (Counter != 0) begin
Dataout <= OutputBuffer[Counter];
NextState <= `OUTPUTSTREAM;
end
else begin
NextState <= `IDLE;
end
end
default: begin
NextState <= `IDLE;
end
endcase
end
end
endmodule |
module softmax_tb(
);
reg Clock;
reg Reset;
reg Start;
reg [`DATALENGTH-1:0] Datain;
reg [`INPUTMAX-1:0] N;
wire [`DATALENGTH-1:0] Dataout;
softmax DUT (Clock, Reset, Start, Datain,N, Dataout);
initial begin
Clock = 1;
Reset = 1;
N = 3;
#10
Start = 1;
Reset = 0;
Datain = 32'h3f800000;
#2
Datain = 32'h3f800000;
#2
Datain = 32'h3f800000;
#2
Datain = 32'h3f800000;
Start = 0;
#2000
$finish;
end
always
#1 Clock = ~Clock;
endmodule |
module core(clk, rst); // Top-level entity(except core-tb)
input clk, rst;
wire write_r, read_r, PC_en, ac_ena, ram_ena, rom_ena;
wire ram_write, ram_read, rom_read, ad_sel;
wire [1:0] fetch;
wire [7:0] data, addr;
wire [7:0] accum_out, alu_out;
wire [7:0] ir_ad, pc_ad;
wire [4:0] reg_ad;
wire [2:0] ins;
ram RAM1(.data(data), .addr(addr), .ena(ram_ena), .read(ram_read), .write(ram_write)); //module ram(data, addr, ena, read, write);
rom ROM1(.data(data), .addr(addr), .ena(rom_ena), .read(rom_read)); //module rom(data, addr, read, ena);
addr_mux MUX1(.addr(addr), .sel(ad_sel), .ir_ad(ir_ad), .pc_ad(pc_ad)); //module addr_mux(addr, sel, ir_ad, pc_ad);
counter PC1(.pc_addr(pc_ad), .clock(clk), .rst(rst), .en(PC_en)); //module counter(pc_addr, clock, rst, en);
accum ACCUM1(.out(accum_out), .in(alu_out), .ena(ac_ena), .clk(clk), .rst(rst)); //module accum( in, out, ena, clk, rst);
alu ALU1(.alu_out(alu_out), .alu_in(data), .accum(accum_out), .op(ins)); // module alu(alu_out, alu_in, accum, op);
reg_32 REG1(.in(alu_out), .data(data), .write(write_r), .read(read_r), .addr({ins,reg_ad}), .clk(clk)); //module reg_32(in, data, write, read, addr, clk);
//reg_32 REG1(.in(alu_out), .data(data), .write(write_r), .read(read_r), .addr(reg_ad), .clk(clk)); //module reg_32(in, data, write, read, addr, clk);
ins_reg IR1(.data(data), .fetch(fetch), .clk(clk), .rst(rst), .ins(ins), .ad1(reg_ad), .ad2(ir_ad)); //module ins_reg(data, fetch, clk, rst, ins, ad1, ad2);
//module machine(ins, clk, rst, write_r, read_r, PC_en, fetch, ac_ena, ram_ena, rom_ena,ram_write, ram_read, rom_read, ad_sel);
controller CONTROLLER1(.ins(ins),
.clk(clk),
.rst(rst),
.write_r(write_r),
.read_r(read_r),
.PC_en(PC_en),
.fetch(fetch),
.ac_ena(ac_ena),
.ram_ena(ram_ena),
.rom_ena(rom_ena),
.ram_write(ram_write),
.ram_read(ram_read),
.rom_read(rom_read),
.ad_sel(ad_sel)
);
endmodule |
module reg_32(in, data, write, read, addr, clk);
input write, read, clk;
input [7:0] in;
input [7:0] addr; //!Warning: addr should be reduced to 5 bits width, not 8 bits width.
//input [4:0] addr;
output [7:0] data;
reg [7:0] R[31:0]; //32Byte
wire [4:0] r_addr;
assign r_addr = addr[4:0];
assign data = (read)? R[r_addr]:8'hzz; //read enable
always @(posedge clk) begin //write, clk posedge
if(write) R[r_addr] <= in;
end
endmodule |
module machine(ins, clk, rst, write_r, read_r, PC_en, fetch, ac_ena, ram_ena, rom_ena,ram_write, ram_read, rom_read, ad_sel);
input clk, rst; // clock, reset
input [2:0] ins; // instructions, 3 bits, 8 types
// Enable signals
output reg write_r, read_r, PC_en, ac_ena, ram_ena, rom_ena;
// ROM: where instructions are storaged. Read only.
// RAM: where data is storaged, readable and writable.
output reg ram_write, ram_read, rom_read, ad_sel;
output reg [1:0] fetch; // 01: to fetch from RAM/ROM; 10: to fetch from REG
// State code(current state)
reg [3:0] state; // current state
reg [3:0] next_state; // next state
// instruction code
parameter NOP=3'b000, // no operation
LDO=3'b001, // load ROM to register
LDA=3'b010, // load RAM to register
STO=3'b011, // Store intermediate results to accumulator
PRE=3'b100, // Prefetch Data from Address
ADD=3'b101, // Adds the contents of the memory address or integer to the accumulator
LDM=3'b110, // Load Multiple
HLT=3'b111; // Halt
// state code
parameter Sidle=4'hf,
S0=4'd0,
S1=4'd1,
S2=4'd2,
S3=4'd3,
S4=4'd4,
S5=4'd5,
S6=4'd6,
S7=4'd7,
S8=4'd8,
S9=4'd9,
S10=4'd10,
S11=4'd11,
S12=4'd12;
//PART A: D flip latch; State register
always @(posedge clk or negedge rst)
begin
if(!rst) state<=Sidle;
//current_state <= Sidle;
else state<=next_state;
//current_state <= next_state;
end
//PART B: Next-state combinational logic
always @*
begin
case(state)
S1: begin
if (ins==NOP) next_state=S0;
else if (ins==HLT) next_state=S2;
else if (ins==PRE | ins==ADD) next_state=S9;
else if (ins==LDM) next_state=S11;
else next_state=S3;
end
S4: begin
if (ins==LDA | ins==LDO) next_state=S5;
//else if (ins==STO) next_state=S7;
else next_state=S7; // ---Note: there are only 3 long instrucions. So, all the cases included. if (counter_A==2*b11)
end
Sidle: next_state=S0;
S0: next_state=S1;
S2: next_state=S2;
S3: next_state=S4;
S5: next_state=S6;
S6: next_state=S0;
S7: next_state=S8;
S8: next_state=S0;
S9: next_state=S10;
S10: next_state=S0;
S11: next_state=S12;
S12: next_state=S0;
default: next_state=Sidle;
endcase
// assign style
// TODO
end
// another style
//PART C: Output combinational logic
always@*
begin
case(state)
// --Note: for each statement, we concentrate on the current state, not next_state
// because it is combinational logic.
Sidle: begin
write_r=1'b0;
read_r=1'b0;
PC_en=1'b0; //** not so sure, log: change 1 to 0
ac_ena=1'b0;
ram_ena=1'b0;
rom_ena=1'b0;
ram_write=1'b0;
ram_read=1'b0;
rom_read=1'b0;
ad_sel=1'b0;
fetch=2'b00;
end
S0: begin // load IR
write_r=0;
read_r=0;
PC_en=0;
ac_ena=0;
ram_ena=0;
rom_ena=1;
ram_write=0;
ram_read=0;
rom_read=1;
ad_sel=0;
fetch=2'b01;
//write_r, read_r, PC_en, ac_ena, ram_ena, rom_ena;
//ram_write, ram_read, rom_read, ad_sel;
// fetch=2'b01; // fetch ins+reg_addr from ROM
// rom_read=1;
// rom_ena=1;
end
S1: begin
write_r=0;
read_r=0;
PC_en=1; //PC+1
ac_ena=0;
ram_ena=0;
rom_ena=0;
ram_write=0;
ram_read=0;
rom_read=0;
ad_sel=0;
fetch=2'b00;
//
// PC_en=1;
// ad_sel=0; // **not so sure, sel=0, select pc_addr(where next ins located)
end
S2: begin
write_r=0;
read_r=0;
PC_en=0;
ac_ena=0;
ram_ena=0;
rom_ena=0;
ram_write=0;
ram_read=0;
rom_read=0;
ad_sel=0;
fetch=2'b00;
end
S3: begin
write_r=0;
read_r=0;
PC_en=0;
ac_ena=0;
ram_ena=0;
rom_ena=1;
ram_write=0;
ram_read=0;
rom_read=1;
ad_sel=0;
fetch=2'b01;
// fetch=2'b01;
// rom_read=1;
// rom_ena=1;
end
S4: begin
write_r=0;
read_r=0;
PC_en=1;
ac_ena=0;
ram_ena=0;
rom_ena=0;
ram_write=0;
ram_read=0;
rom_read=0;
ad_sel=0;
fetch=2'b00;
// PC_en=1;
// ad_sel=0;
end
S5: begin
if (ins==LDO)
begin
write_r=1;
read_r=0;
PC_en=0;
ac_ena=0;
ram_ena=0;
rom_ena=1;
ram_write=0;
ram_read=0;
rom_read=1;
ad_sel=1; // ! Attention, don't forget
fetch=2'b00;
end
else // ins==LDA
begin
write_r=1;
read_r=0;
PC_en=0;
ac_ena=0;
ram_ena=1;
rom_ena=0;
ram_write=0;
ram_read=1;
rom_read=0;
ad_sel=1;
fetch=2'b00;
end
// write_r=1;
// ram_ena=1;
end
S6: begin // same as s5
if (ins==LDO)
begin
write_r=1;
read_r=0;
PC_en=0;
ac_ena=0;
ram_ena=0;
rom_ena=1;
ram_write=0;
ram_read=0;
rom_read=1;
ad_sel=1;
fetch=2'b00;
end
else
begin
write_r=1;
read_r=0;
PC_en=0;
ac_ena=0;
ram_ena=1;
rom_ena=0;
ram_write=0;
ram_read=1;
rom_read=0;
ad_sel=1;
fetch=2'b00;
end
end
S7: begin // STO, reg->ram. step1. read REG
write_r=0;
read_r=1;
PC_en=0;
ac_ena=0;
ram_ena=0;
rom_ena=0;
ram_write=0;
ram_read=0;
rom_read=0;
ad_sel=0;
fetch=2'b01;
//read_r=1;
end
S8: begin // STO, step2, write RAM
write_r=0;
read_r=0;
PC_en=0;
ac_ena=0;
ram_ena=1;
rom_ena=0;
ram_write=1;
ram_read=0;
rom_read=0;
ad_sel=1;
fetch=2'b10; //fetch=2'b10, ram_ena=1, ram_write=1, ad_sel=1;
// ram_ena=1;
// ram_write=1;
end
S9: begin
if (ins==PRE) // REG->ACCUM
begin
write_r=0;
read_r=1;
PC_en=0;
ac_ena=0;
ram_ena=0;
rom_ena=0;
ram_write=0;
ram_read=0;
rom_read=0;
ad_sel=0;
fetch=2'b01;
end
else // ins==ADD, same as PRE
begin
write_r=0;
read_r=1;
PC_en=0;
ac_ena=0;
ram_ena=0;
rom_ena=0;
ram_write=0;
ram_read=0;
rom_read=0;
ad_sel=0;
fetch=2'b01;
end
end
S10: begin
write_r=0;
read_r=0;
PC_en=0;
ac_ena=1;
ram_ena=0;
rom_ena=0;
ram_write=0;
ram_read=0;
rom_read=0;
ad_sel=0;
fetch=2'b01;
//ac_ena=1;
end
S11: begin // LDM, step1, write reg
write_r=1;
read_r=0;
PC_en=0;
ac_ena=1;
ram_ena=0;
rom_ena=0;
ram_write=0;
ram_read=0;
rom_read=0;
ad_sel=0;
fetch=2'b00;
//write_r=1;
end
S12: begin // same as s11
write_r=1;
read_r=0;
PC_en=0;
ac_ena=1;
ram_ena=0;
rom_ena=0;
ram_write=0;
ram_read=0;
rom_read=0;
ad_sel=0;
fetch=2'b00;
end
default: begin
write_r=0;
read_r=0;
PC_en=0;
ac_ena=0;
ram_ena=0;
rom_ena=0;
ram_write=0;
ram_read=0;
rom_read=0;
ad_sel=0;
fetch=2'b00;
end
endcase
end
endmodule |
module ram(data, addr, ena, read, write);
input ena, read, write;
input [7:0] addr;
inout [7:0] data;
reg [7:0] ram[255:0];
assign data = (read&&ena)? ram[addr]:8'hzz; // read data from RAM
always @(posedge write) begin // write data to RAM
ram[addr] <= data;
end
endmodule |
module counter(pc_addr, clock, rst, en);
input clock, rst, en;
output reg [7:0] pc_addr;
always @(posedge clock or negedge rst) begin
if(!rst) begin
pc_addr <= 8'd0;
end
else begin
if(en) pc_addr <= pc_addr+1;
else pc_addr <= pc_addr;
end
end
endmodule |
module rom(data, addr, read, ena);
input read, ena;
input [7:0] addr;
output [7:0] data;
reg [7:0] memory[255:0];
// note: Decimal number in the bracket
initial begin
memory[0] = 8'b000_00000; //NOP
// [ins] [target_reg_addr] [from_rom_addr]
memory[1] = 8'b001_00001; //LDO s1
memory[2] = 8'b010_00001; //rom(65) //rom[65] -> reg[1]
memory[3] = 8'b001_00010; //LDO s2
memory[4] = 8'b010_00010; //rom(66)
memory[5] = 8'b001_00011; //LDO s3
memory[6] = 8'b010_00011; //rom(67)
memory[7] = 8'b100_00001; //PRE s1
memory[8] = 8'b101_00010; //ADD s2
memory[9] = 8'b110_00001; //LDM s1
memory[10] = 8'b011_00001; //STO s1
memory[11] = 8'b000_00001; //ram(1)
memory[12] = 8'b010_00010; //LDA s2
memory[13] = 8'b000_00001; //ram(1)
memory[14] = 8'b100_00011; //PRE s3
memory[15] = 8'b101_00010; //ADD s2
memory[16] = 8'b110_00011; //LDM s3
memory[17] = 8'b011_00011; //STO s3
memory[18] = 8'b000_00010; //ram(2)
memory[19] = 8'b111_00000; //HLT
memory[65] = 8'b001_00101; //37
memory[66] = 8'b010_11001; //89
memory[67] = 8'b001_10101; //53
end
assign data = (read&&ena)? memory[addr]:8'hzz;
endmodule |
module accum( in, out, ena, clk, rst); // a register, to storage result after computing
input clk,rst,ena;
input [7:0] in;
output reg [7:0] out;
always @(posedge clk or negedge rst) begin
if(!rst) out <= 8'd0;
else begin
if(ena) out <= in;
else out <= out;
end
end
endmodule |
module core_tb_00 ;
reg rst ;
reg clk ;
core
DUT (
.rst (rst ) ,
.clk (clk ) );
// "Clock Pattern" : dutyCycle = 50
// Start Time = 0 ps, End Time = 10 ns, Period = 100 ps
initial
begin
clk = 1'b0 ;
# 150 ;
// 50 ps, single loop till start period.
repeat(99)
begin
clk = 1'b1 ;
#50 clk = 1'b0 ;
#50 ;
// 9950 ps, repeat pattern in loop.
end
clk = 1'b1 ;
# 50 ;
// dumped values till 10 ns
end
// "Constant Pattern"
// Start Time = 0 ps, End Time = 10 ns, Period = 0 ps
initial
begin
rst = 1'b0 ;
# 100;
rst=1'b1;
# 9000 ;
// dumped values till 10 ns
end
initial
#20000 $stop;
endmodule |
module ins_reg(data, fetch, clk, rst, ins, ad1, ad2); // instruction register
input clk, rst;
input [1:0] fetch;
input [7:0] data;
output [2:0] ins;
output [4:0] ad1;
output [7:0] ad2;
reg [7:0] ins_p1, ins_p2;
reg [2:0] state;
assign ins = ins_p1[7:5]; //hign 3 bits, instructions
assign ad1 = ins_p1[4:0]; //low 5 bits, register address
assign ad2 = ins_p2;
always @(posedge clk or negedge rst) begin
if(!rst) begin
ins_p1 <= 8'd0;
ins_p2 <= 8'd0;
end
else begin
if(fetch==2'b01) begin //fetch==2'b01 operation1, to fetch data from REG
ins_p1 <= data;
ins_p2 <= ins_p2;
end
else if(fetch==2'b10) begin //fetch==2'b10 operation2, to fetch data from RAM/ROM
ins_p1 <= ins_p1;
ins_p2 <= data;
end
else begin
ins_p1 <= ins_p1;
ins_p2 <= ins_p2;
end
end
end
endmodule |
module addr_mux(addr, sel, ir_ad, pc_ad);
// Address multiplexer
// to choose address of instruction register or address of program counter
input [7:0] ir_ad, pc_ad;
input sel;
output [7:0] addr;
assign addr = (sel)? ir_ad:pc_ad;
endmodule |