module
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|
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module alu(alu_out, alu_in, accum, op);// arithmetic logic unit
// to perform arithmetic and logic operations.
input [2:0] op;
input [7:0] alu_in,accum;
output reg [7:0] alu_out;
parameter NOP=3'b000,
LDO=3'b001,
LDA=3'b010,
STO=3'b011,
PRE=3'b100,
ADD=3'b101,
LDM=3'b110,
HLT=3'b111;
always @(*) begin
casez(op)
NOP: alu_out = accum;
HLT: alu_out = accum;
LDO: alu_out = alu_in;
LDA: alu_out = alu_in;
STO: alu_out = accum;
PRE: alu_out = alu_in;
ADD: alu_out = accum+alu_in;
LDM: alu_out = accum;
default: alu_out = 8'bzzzz_zzzz;
endcase
end
endmodule
|
module random (
input clock,
output reg [30:0] lfsr
);
always @(posedge clock) begin
lfsr <= {lfsr[29:0], lfsr[30] ^~ lfsr[27]};
end
endmodule
|
module row (
input clock,
input [0:0] shiftin,
output [0:0] shiftout
);
altshift_taps ALTSHIFT_TAPS_component (
.clock (clock),
.shiftin (shiftin),
.shiftout (shiftout)
);
defparam
ALTSHIFT_TAPS_component.intended_device_family = "Cyclone V",
ALTSHIFT_TAPS_component.lpm_hint = "RAM_BLOCK_TYPE=M10K",
ALTSHIFT_TAPS_component.lpm_type = "altshift_taps",
ALTSHIFT_TAPS_component.number_of_taps = 1,
ALTSHIFT_TAPS_component.tap_distance = 2198,
ALTSHIFT_TAPS_component.width = 1;
endmodule
|
module ring (
input clock,
input enable,
input shiftin,
output shiftout,
input [31:0] status
);
reg [21:0] counter = 0;
always @(posedge clock) begin
if (enable)
counter <= ~|counter ? 2472795 : counter - 1'b1;
end
altsyncram altsyncram_component (
.address_a (counter),
.address_b (counter),
.clock0 (clock),
.data_a (shiftin),
.wren_a (enable),
.q_b (shiftout),
.aclr0 (1'b0),
.aclr1 (1'b0),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_b (1'b1),
.eccstatus (),
.q_a (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_b (1'b0));
defparam
altsyncram_component.address_aclr_b = "NONE",
altsyncram_component.address_reg_b = "CLOCK0",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_input_b = "BYPASS",
altsyncram_component.clock_enable_output_b = "BYPASS",
altsyncram_component.init_file = "./roms/initial.hex",
altsyncram_component.intended_device_family = "Cyclone V",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 2472800,
altsyncram_component.numwords_b = 2472800,
altsyncram_component.operation_mode = "DUAL_PORT",
altsyncram_component.outdata_aclr_b = "NONE",
altsyncram_component.outdata_reg_b = "CLOCK0",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.ram_block_type = "M10K",
altsyncram_component.read_during_write_mode_mixed_ports = "OLD_DATA",
altsyncram_component.widthad_a = 22,
altsyncram_component.widthad_b = 22,
altsyncram_component.width_a = 1,
altsyncram_component.width_b = 1,
altsyncram_component.width_byteena_a = 1;
endmodule
|
module DE10STDrsyocto(
/////////////////////////////////////////////// CLOCK ////////////////////////////////////////////////
input CLOCK2_50,
input CLOCK3_50,
input CLOCK4_50,
input CLOCK_50,
/////////////////////////////////////////////// KEY /////////////////////////////////////////////////
input [3:0] KEY,
/////////////////////////////////////////////// SW ///////////////////////////////////////////////////
input [9:0] SW,
//////////////////////////////////////////////// Seg7 ////////////////////////////////////////////////
`ifdef USE_HEX
output [6:0] HEX0,
output [6:0] HEX1,
output [6:0] HEX2,
output [6:0] HEX3,
output [6:0] HEX4,
output [6:0] HEX5,
`endif
////////////////////////////////////////////////// SDRAM /////////////////////////////////////////////
`ifdef USE_SDRAM
output [12:0] DRAM_ADDR,
output [1:0] DRAM_BA,
output DRAM_CAS_N,
output DRAM_CKE,
output DRAM_CLK,
output DRAM_CS_N,
inout [15:0] DRAM_DQ,
output DRAM_LDQM,
output DRAM_RAS_N,
output DRAM_UDQM,
output DRAM_WE_N,
`endif
///////////////////////l/////////////////////////// Video-In ///////////////////////////////////////////
`ifdef USE_VIDEO_IN
input TD_CLK27,
input [7:0] TD_DATA,
input TD_HS,
output TD_RESET_N,
input TD_VS,
`endif
///////////////////////////////////////////////// VGA /////////////////////////////////////////////////
`ifdef USE_VGA
output VGA_BLANK_N,
output [7:0] VGA_B,
output VGA_CLK,
output [7:0] VGA_G,
output VGA_HS,
output [7:0] VGA_R,
output VGA_SYNC_N,
output VGA_VS,
`endif
////////////////////////////////////////////////// Audio //////////////////////////////////////////////
`ifdef USE_AUDO
input AUD_ADCDAT,
inout AUD_ADCLRCK,
inout AUD_BCLK,
output AUD_DACDAT,
inout AUD_DACLRCK,
output AUD_XCK,
`endif
///////////////////////////////////////////////// PS2 /////////////////////////////////////////////////
`ifdef USE_PS2
inout PS2_CLK,
inout PS2_CLK2,
inout PS2_DAT,
inout PS2_DAT2,
`endif
////////////////////////////////////////////////// ADC ////////////////////////////////////////////////
`ifdef USE_ADC
output ADC_CONVST,
output ADC_DIN,
input ADC_DOUT,
output ADC_SCLK,
`endif
////////////////////////////// I2C for Audio and Video-In /////////////////////////////////////////////
`ifdef USE_PS2_VIDO_IF
output FPGA_I2C_SCLK,
inout FPGA_I2C_SDAT,
`endif
//////////////////////////////////////////////// HPS //////////////////////////////////////////////////
`ifdef USE_HPS
inout HPS_CONV_USB_N,
output [14:0] HPS_DDR3_ADDR,
output [2:0] HPS_DDR3_BA,
output HPS_DDR3_CAS_N,
output HPS_DDR3_CKE,
output HPS_DDR3_CK_N,
output HPS_DDR3_CK_P,
output HPS_DDR3_CS_N,
output [3:0] HPS_DDR3_DM,
inout [31:0] HPS_DDR3_DQ,
inout [3:0] HPS_DDR3_DQS_N,
inout [3:0] HPS_DDR3_DQS_P,
output HPS_DDR3_ODT,
output HPS_DDR3_RAS_N,
output HPS_DDR3_RESET_N,
input HPS_DDR3_RZQ,
output HPS_DDR3_WE_N,
output HPS_ENET_GTX_CLK,
inout HPS_ENET_INT_N,
output HPS_ENET_MDC,
inout HPS_ENET_MDIO,
input HPS_ENET_RX_CLK,
input [3:0] HPS_ENET_RX_DATA,
input HPS_ENET_RX_DV,
output [3:0] HPS_ENET_TX_DATA,
output HPS_ENET_TX_EN,
inout [3:0] HPS_FLASH_DATA,
output HPS_FLASH_DCLK,
output HPS_FLASH_NCSO,
inout HPS_GSENSOR_INT,
inout HPS_I2C1_SCLK,
inout HPS_I2C1_SDAT,
inout HPS_I2C2_SCLK,
inout HPS_I2C2_SDAT,
inout HPS_I2C_CONTROL,
inout HPS_KEY,
inout HPS_LCM_BK,
inout HPS_LCM_D_C,
inout HPS_LCM_RST_N,
output HPS_LCM_SPIM_CLK,
input HPS_LCM_SPIM_MISO,
output HPS_LCM_SPIM_MOSI,
output HPS_LCM_SPIM_SS,
inout HPS_LED,
inout HPS_LTC_GPIO,
output HPS_SD_CLK,
inout HPS_SD_CMD,
inout [3:0] HPS_SD_DATA,
output HPS_SPIM_CLK,
input HPS_SPIM_MISO,
output HPS_SPIM_MOSI,
output HPS_SPIM_SS,
input HPS_UART_RX,
output HPS_UART_TX,
input HPS_USB_CLKOUT,
inout [7:0] HPS_USB_DATA,
input HPS_USB_DIR,
input HPS_USB_NXT,
output HPS_USB_STP,
`endif
//////////////////////////////////////////////// IR ///////////////////////////////////////////////////
`ifdef IR_LED
input IRDA_RXD,
output IRDA_TXD,
`endif
//////////////////////////////////////////////// LED /////////////////////////////////////////////////
output [9:0] LEDR,
/////////////////////////////////// 40 Pin 2.55mm I/O Connector //////////////////////////////////////
inout [35:0] GPIO
);
//====================================================================================================
// REG/WIRE declarations
//====================================================================================================
//// IO Buffer Temp I2c 1 & 3
wire scl1_o_e, sda1_o_e, scl1_o, sda1_o,
scl3_o_e, sda3_o_e, scl3_o, sda3_o;
//// IO Buffer Temp SPI 0
//wire spi0_clk, spi0_mosi, spi0_miso,spi0_ss_0_n;
//// IO Buffer Temp UART 1
wire uart1_rx,uart1_tx;
//// IO Buffer Temp CAN 0
wire can0_rx, can0_tx;
//====================================================================================================
// BASE Platform Designer module
//====================================================================================================
base_hps u0 (
/////////////////////////////////////////////// CLOCKS ////////////////////////////////////////////////
.clk_clk (CLOCK_50),
///////////////////////////////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////// HPS ///////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////////////////////////////
///////////////////////////////////// Onboard DDR3 1GB Memmory //////////////////////////////////////
.hps_0_ddr_mem_a ( HPS_DDR3_ADDR),
.hps_0_ddr_mem_ba ( HPS_DDR3_BA),
.hps_0_ddr_mem_ck ( HPS_DDR3_CK_P),
.hps_0_ddr_mem_ck_n ( HPS_DDR3_CK_N),
.hps_0_ddr_mem_cke ( HPS_DDR3_CKE),
.hps_0_ddr_mem_cs_n ( HPS_DDR3_CS_N),
.hps_0_ddr_mem_ras_n ( HPS_DDR3_RAS_N),
.hps_0_ddr_mem_cas_n ( HPS_DDR3_CAS_N),
.hps_0_ddr_mem_we_n ( HPS_DDR3_WE_N),
.hps_0_ddr_mem_reset_n ( HPS_DDR3_RESET_N),
.hps_0_ddr_mem_dq ( HPS_DDR3_DQ),
.hps_0_ddr_mem_dqs ( HPS_DDR3_DQS_P),
.hps_0_ddr_mem_dqs_n ( HPS_DDR3_DQS_N),
.hps_0_ddr_mem_odt ( HPS_DDR3_ODT),
.hps_0_ddr_mem_dm ( HPS_DDR3_DM),
.hps_0_ddr_oct_rzqin ( HPS_DDR3_RZQ),
///////////////////////////////////////// HPS Ethernet 1 ////////////////////////////////////////////
.hps_0_io_hps_io_emac1_inst_TX_CLK ( HPS_ENET_GTX_CLK),
.hps_0_io_hps_io_emac1_inst_TXD0 ( HPS_ENET_TX_DATA[0] ),
.hps_0_io_hps_io_emac1_inst_TXD1 ( HPS_ENET_TX_DATA[1] ),
.hps_0_io_hps_io_emac1_inst_TXD2 ( HPS_ENET_TX_DATA[2] ),
.hps_0_io_hps_io_emac1_inst_TXD3 ( HPS_ENET_TX_DATA[3] ),
.hps_0_io_hps_io_emac1_inst_RXD0 ( HPS_ENET_RX_DATA[0] ),
.hps_0_io_hps_io_emac1_inst_MDIO ( HPS_ENET_MDIO ),
.hps_0_io_hps_io_emac1_inst_MDC ( HPS_ENET_MDC ),
.hps_0_io_hps_io_emac1_inst_RX_CTL ( HPS_ENET_RX_DV),
.hps_0_io_hps_io_emac1_inst_TX_CTL ( HPS_ENET_TX_EN),
.hps_0_io_hps_io_emac1_inst_RX_CLK ( HPS_ENET_RX_CLK),
.hps_0_io_hps_io_emac1_inst_RXD1 ( HPS_ENET_RX_DATA[1] ),
.hps_0_io_hps_io_emac1_inst_RXD2 ( HPS_ENET_RX_DATA[2] ),
.hps_0_io_hps_io_emac1_inst_RXD3 ( HPS_ENET_RX_DATA[3] ),
/////////////////////////////////////// SD Card Boot drive ///////////////////////////////////////////
.hps_0_io_hps_io_sdio_inst_CMD ( HPS_SD_CMD ),
.hps_0_io_hps_io_sdio_inst_D0 ( HPS_SD_DATA[0] ),
.hps_0_io_hps_io_sdio_inst_D1 ( HPS_SD_DATA[1] ),
.hps_0_io_hps_io_sdio_inst_CLK ( HPS_SD_CLK ),
.hps_0_io_hps_io_sdio_inst_D2 ( HPS_SD_DATA[2] ),
.hps_0_io_hps_io_sdio_inst_D3 ( HPS_SD_DATA[3] ),
////////////////////////////////////////// USB HOST //////////////////////////////////////////////
.hps_0_io_hps_io_usb1_inst_D0 ( HPS_USB_DATA[0] ),
.hps_0_io_hps_io_usb1_inst_D1 ( HPS_USB_DATA[1] ),
.hps_0_io_hps_io_usb1_inst_D2 ( HPS_USB_DATA[2] ),
.hps_0_io_hps_io_usb1_inst_D3 ( HPS_USB_DATA[3] ),
.hps_0_io_hps_io_usb1_inst_D4 ( HPS_USB_DATA[4] ),
.hps_0_io_hps_io_usb1_inst_D5 ( HPS_USB_DATA[5] ),
.hps_0_io_hps_io_usb1_inst_D6 ( HPS_USB_DATA[6] ),
.hps_0_io_hps_io_usb1_inst_D7 ( HPS_USB_DATA[7] ),
.hps_0_io_hps_io_usb1_inst_CLK ( HPS_USB_CLKOUT ),
.hps_0_io_hps_io_usb1_inst_STP ( HPS_USB_STP ),
.hps_0_io_hps_io_usb1_inst_DIR ( HPS_USB_DIR ),
.hps_0_io_hps_io_usb1_inst_NXT ( HPS_USB_NXT ),
//////////////////////////////////////// UART 0 (Console) ///////////////////////////////////////////
.hps_0_io_hps_io_uart0_inst_RX ( HPS_UART_RX ),
.hps_0_io_hps_io_uart0_inst_TX ( HPS_UART_TX ),
//////////////////////////////////////////////////////////////////////////////////////////////////////
/////////////////////////////// HPS Hard IP to FPGA Mapping /////////////////////////////////////
///////////////////////////////////////////// HPS UART 1 /////////////////////////////////////////////
.hps_0_uart1_cts (),
.hps_0_uart1_dsr (),
.hps_0_uart1_dcd (),
.hps_0_uart1_ri (),
.hps_0_uart1_dtr (),
.hps_0_uart1_rts (),
.hps_0_uart1_out1_n (),
.hps_0_uart1_out2_n (),
.hps_0_uart1_rxd (uart1_rx),
.hps_0_uart1_txd (uart1_tx),
///////////////////////////////////////////////// I2C1 ///////////////////////////////////////////////
.hps_0_i2c1_clk_clk (scl1_o_e),
.hps_0_i2c1_scl_in_clk (scl1_o),
.hps_0_i2c1_out_data (sda1_o_e),
.hps_0_i2c1_sda (sda1_o),
////////////////////////////////////////////////// I2C3 //////////////////////////////////////////////
.hps_0_i2c3_scl_in_clk (scl3_o_e),
.hps_0_i2c3_clk_clk (scl3_o),
.hps_0_i2c3_out_data (sda3_o_e),
.hps_0_i2c3_sda (sda3_o),
//////////////////////////////////////////////// CAN0 ////////////////////////////////////////////////
.hps_0_can0_rxd (can0_rx),
.hps_0_can0_txd (can0_tx),
//////////////////////////////////////////////// SPI0 Master ////////////////////////////////////////
// .hps_0_spim0_sclk_out_clk (spi0_clk),
// .hps_0_spim0_txd (spi0_mosi),
// .hps_0_spim0_rxd (spi0_miso),
// .hps_0_spim0_ss_in_n (1'b1),
// .hps_0_spim0_ssi_oe_n (spim0_ssi_oe_n),
// .hps_0_spim0_ss_0_n (spi0_ss_0_n),
// .hps_0_spim0_ss_1_n (),
// .hps_0_spim0_ss_2_n (),
// .hps_0_spim0_ss_3_n (),
////////////////////////////////////////////////// SPIO LCD ////////////////////////////////////////////
.hps_0_io_hps_io_spim0_inst_CLK (HPS_LCM_SPIM_CLK),
.hps_0_io_hps_io_spim0_inst_MOSI (HPS_LCM_SPIM_MOSI),
.hps_0_io_hps_io_spim0_inst_MISO (HPS_LCM_SPIM_MISO),
.hps_0_io_hps_io_spim0_inst_SS0 (HPS_LCM_SPIM_SS),
///////////////////////////////////////////////////////////////////////////////////////////////////////
////////////////////////////////// On Board Compunents ////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////// HPS LED & KEY ///////////////////////////////////////////
.hps_0_io_hps_io_gpio_inst_GPIO53 ( HPS_LED),
.hps_0_io_hps_io_gpio_inst_GPIO54 ( HPS_KEY),
////////////////////////////////////////////// HPS GPIO /////////////////////////////////////////////
.hps_0_io_hps_io_gpio_inst_GPIO09 (HPS_CONV_USB_N),
.hps_0_io_hps_io_gpio_inst_GPIO35 (HPS_ENET_INT_N),
.hps_0_io_hps_io_gpio_inst_GPIO37 (HPS_LCM_BK),
.hps_0_io_hps_io_gpio_inst_GPIO41 (HPS_LCM_D_C),
.hps_0_io_hps_io_gpio_inst_GPIO44 (HPS_LCM_RST_N),
.hps_0_io_hps_io_gpio_inst_GPIO48 (HPS_I2C_CONTROL),
.hps_0_io_hps_io_gpio_inst_GPIO61 (HPS_GSENSOR_INT),
////////////////////////////////// G-Sensor: I2C0 (Terasic Docu I2C1) ////////////////////////////////
.hps_0_io_hps_io_i2c0_inst_SDA (HPS_I2C1_SDAT),
.hps_0_io_hps_io_i2c0_inst_SCL (HPS_I2C1_SCLK),
/////////////////////////////////// onboard LEDs, Switches and Keys ///////////////////////////////////
.led_pio_external_connection_export (LEDR), // LEDR
.pb_pio_external_connection_export (KEY),
.sw_pio_external_connection_export (SW),
////////////////////////////////// 24 Bit seven sigment HEX Display ///////////////////////////////////
.de10std7sig_hex_io0_readdata (HEX0),
.de10std7sig_hex_io1_readdata (HEX1),
.de10std7sig_hex_io2_readdata (HEX2),
.de10std7sig_hex_io3_readdata (HEX3),
.de10std7sig_hex_io4_readdata (HEX4),
.de10std7sig_hex_io5_readdata (HEX5),
////////////////////////////////// ADC: Analog Devices LTC2308 ////////////////////////////////
.ltc2308_io_convst_writeresponsevalid_n (ADC_CONVST),
.ltc2308_io_sck_writeresponsevalid_n (ADC_SCLK),
.ltc2308_io_sdi_writeresponsevalid_n (ADC_DIN),
.ltc2308_io_sdo_beginbursttransfer (ADC_DOUT),
////////////////////////////////// HPS -> FPGA GPIO ///////////////////////////////////
.hps_0_h2f_gp_gp_in (32'hACDCACDC),
.hps_0_h2f_gp_gp_out (),
/////////////////// USER CLOCK TEST ////////////////////////////
.hps_0_h2f_user0_clock_clk (GPIO[34]),
.hps_0_h2f_user2_clock_clk (GPIO[35])
);
//////////////////////////////////////////////////////////////////////////////////////////////////////
/////////////////////////////// HPS Hard IP to FPGA Mapping /////////////////////////////////////
/////////////////////////////// IO Buffer /////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////// DE10 STANDARD ///////////////////////////////////////////
//////////////////////////////////////////// USER GPIO PORT /////////////////////////////////////////
//////////////////////////////////// (40 Pin Wannenstecker 2,54mm) //////////////////////////////////
///////////////////////////////////////////////////
// PIN | --- mapped func --- | GPIO //
// 1 | UART1 TX | 0 //
// 2 | UART1 RX | 1 //
// 3 | I2C1 SCL | 2 //
// 4 | I2C1 SDA | 3 //
// 5 | CAN0 TX | 4 //
// 6 | CAN0 RX | 5 //
// 7 | | 6 //
// 8 | | 7 //
// 9 | | 8 //
// 10 | | 9 //
// 11 --- VDD 5V ------ | //
// 12 --- GND ------ | //
// 13 | I2C2 SCL | 10 //
// 14 | I2C2 SDA | 11 //
// 15 | | 12 //
// 16 | | 13 //
// 17 | | 14 //
// 18 | | 15 //
// 19 | | 16 //
// 20 | | 17 //
// 21 | | 18 //
// 22 | | 19 //
// 23 | | 20 //
// 24 | | 21 //
// 25 | | 22 //
// 26 | | 23 //
// 27 | | 24 //
// 28 | | 25 //
// 29 --- VCC 3V3 ------ | //
// 30 --- GND ------ | //
// 31 | | 26 //
// 32 | | 27 //
// 33 | | 28 //
// 34 | | 29 //
// 35 | | 30 //
// 36 | | 31 //
// 37 | | 32 //
// 38 | | 33 //
// 39 | | 34 //
// 40 | | 35 //
///////////////////////////////////////////////////
//////////////////////////////////////// IO Buffer SPI 0 /////////////////////////////////////////////
// // SPI0 -> CS
// ALT_IOBUF spi0_ss_iobuf (.i(spi0_ss_0_n), .oe(1'b1), .o(), .io(GPIO[6])); // AH
////// // SPI0 -> MOSI
// ALT_IOBUF spi0_mosi_iobuf (.i(spi0_mosi), .oe(1'b1), .o(), .io(GPIO[18])); // AF
////// // SPI0 -> MISO
// ALT_IOBUF spi0_miso_iobuf (.i(1'b0), .oe(1'b0), .o(spi0_miso), .io(GPIO[27])); // AE
////// // SPI0 -> CLK
// ALT_IOBUF spi0_clk_iobuf (.i(spi0_clk), .oe(1'b1), .o(), .io(GPIO[23])); // AD
////
////////////////////////////////////////// IO Buffer I2C 1 and 3 /////////////////////////////////////
// // I2C1 -> SCL
ALT_IOBUF i2c1_scl_iobuf (.i(1'b0),.oe(scl1_o_e),.o(scl1_o),.io(GPIO[2])); // Y
//// // I2C1 -> SDA
ALT_IOBUF i2c1_sda_iobuf (.i(1'b0),.oe(sda1_o_e),.o(sda1_o),.io(GPIO[3])); // AK
//// // I2C3 -> SCL
ALT_IOBUF i2c3_scl_iobuf (.i(1'b0),.oe(scl3_o_e),.o(scl3_o),.io(GPIO[10])); // AG
//// // I2C3 -> SDA
ALT_IOBUF i2c3_sda_iobuf (.i(1'b0),.oe(sda3_o_e),.o(sda3_o),.io(GPIO[11])); // AG
////
//////////////////////////////////////////// IO Buffer UART1 //////////////////////////////////////////
//// // UART1 -> RX
ALT_IOBUF uart1_rx_iobuf (.i(1'b0), .oe(1'b0), .o(uart1_rx), .io(GPIO[1])); // W
//// // UART1 -> TX
ALT_IOBUF uart1_tx_iobuf (.i(uart1_tx), .oe(1'b1), .o(), .io(GPIO[0])); // AK
////
//////////////////////////////////////////// IO Buffer CAN0 ///////////////////////////////////////////
// CAN0 -> RX
ALT_IOBUF can0_rx_iobuf (.i(1'b0), .oe(1'b0), .o(can0_rx), .io(GPIO[5])); // AJ
// CAN0 -> TX
ALT_IOBUF can0_tx_iobuf (.i(can0_tx), .oe(1'b1), .o(), .io(GPIO[4])); // AJ
//
//
endmodule
|
module DE10NANOrsyocto(
////////////////////////////////////////////////// ADC ////////////////////////////////////////////////
`ifdef USE_ADC
output ADC_CONVST,
output ADC_SCK,
output ADC_SDI,
input ADC_SDO,
`endif
//////////////////////////////////////////////// ARDUINO //////////////////////////////////////////////
`ifdef USE_ADUINO
inout [15:0] ARDUINO_IO,
inout ARDUINO_RESET_N,
`endif
///////////////////////////////////////////////// HDMI ////////////////////////////////////////////////
`ifdef USE_HDMI
inout HDMI_I2C_SCL,
inout HDMI_I2C_SDA,
inout HDMI_I2S,
inout HDMI_LRCLK,
inout HDMI_MCLK,
inout HDMI_SCLK,
output HDMI_TX_CLK,
output HDMI_TX_DE,
output [23:0] HDMI_TX_D,
output HDMI_TX_HS,
input HDMI_TX_INT,
output HDMI_TX_VS,
`endif
////////////////////////////////////////////////// HPS ////////////////////////////////////////////////
`ifdef USE_HPS
//inout HPS_CONV_USB_N,
output [14:0] HPS_DDR3_ADDR,
output [2:0] HPS_DDR3_BA,
output HPS_DDR3_CAS_N,
output HPS_DDR3_CKE,
output HPS_DDR3_CK_N,
output HPS_DDR3_CK_P,
output HPS_DDR3_CS_N,
output [3:0] HPS_DDR3_DM,
inout [31:0] HPS_DDR3_DQ,
inout [3:0] HPS_DDR3_DQS_N,
inout [3:0] HPS_DDR3_DQS_P,
output HPS_DDR3_ODT,
output HPS_DDR3_RAS_N,
output HPS_DDR3_RESET_N,
input HPS_DDR3_RZQ,
output HPS_DDR3_WE_N,
output HPS_ENET_GTX_CLK,
inout HPS_ENET_INT_N,
output HPS_ENET_MDC,
inout HPS_ENET_MDIO,
input HPS_ENET_RX_CLK,
input [3:0] HPS_ENET_RX_DATA,
input HPS_ENET_RX_DV,
output [3:0] HPS_ENET_TX_DATA,
output HPS_ENET_TX_EN,
inout HPS_I2C1_SCLK,
inout HPS_I2C1_SDAT,
inout HPS_KEY,
inout HPS_LED,
//inout HPS_LTC_GPIO,
output HPS_SD_CLK,
inout HPS_SD_CMD,
inout [3:0] HPS_SD_DATA,
// output HPS_SPIM_CLK,
// input HPS_SPIM_MISO,
// output HPS_SPIM_MOSI,
// inout HPS_SPIM_SS,
input HPS_UART_RX,
output HPS_UART_TX,
input HPS_USB_CLKOUT,
inout [7:0] HPS_USB_DATA,
input HPS_USB_DIR,
input HPS_USB_NXT,
output HPS_USB_STP,
`endif
//////////////////////////////////////////////// GPIO 0 ///////////////////////////////////////////////
`ifdef USE_GPIO0
inout [35:0] GPI0GPIO,
`endif
//////////////////////////////////////////////// GPIO 1 ///////////////////////////////////////////////
`ifdef USE_GPIO1
inout [35:0] GPI1GPIO,
`endif
////////////////////////////////////////////////// KEY ////////////////////////////////////////////////
input [1:0] KEY,
////////////////////////////////////////////////// LED ////////////////////////////////////////////////
output [7:0] LED,
////////////////////////////////////////////////// SW ////////////////////////////////////////////////
input [3:0] SW,
//////////////////////////////////////////////// CLOCK ////////////////////////////////////////////////
input FPGA_CLK1_50,
input FPGA_CLK2_50,
input FPGA_CLK3_50
);
//====================================================================================================
// REG/WIRE declarations
//====================================================================================================
//// IO Buffer Temp I2c 1 & 3
wire scl1_o_e, sda1_o_e, scl1_o, sda1_o,
scl3_o_e, sda3_o_e, scl3_o, sda3_o;
//// IO Buffer Temp SPI 0
wire spi0_clk, spi0_mosi, spi0_miso,spi0_ss_0_n;
//// IO Buffer Temp UART 1
wire uart1_rx,uart1_tx;
//// IO Buffer Temp CAN 0
wire can0_rx, can0_tx;
base_hps u0 (
/////////////////////////////////////////////// CLOCKS ////////////////////////////////////////////////
.clk_clk ( FPGA_CLK1_50 ),
///////////////////////////////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////// HPS ///////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////////////////////////////
///////////////////////////////////// Onboard DDR3 1GB Memmory //////////////////////////////////////
.hps_0_ddr_mem_a ( HPS_DDR3_ADDR),
.hps_0_ddr_mem_ba ( HPS_DDR3_BA),
.hps_0_ddr_mem_ck ( HPS_DDR3_CK_P),
.hps_0_ddr_mem_ck_n ( HPS_DDR3_CK_N),
.hps_0_ddr_mem_cke ( HPS_DDR3_CKE),
.hps_0_ddr_mem_cs_n ( HPS_DDR3_CS_N),
.hps_0_ddr_mem_ras_n ( HPS_DDR3_RAS_N),
.hps_0_ddr_mem_cas_n ( HPS_DDR3_CAS_N),
.hps_0_ddr_mem_we_n ( HPS_DDR3_WE_N),
.hps_0_ddr_mem_reset_n ( HPS_DDR3_RESET_N),
.hps_0_ddr_mem_dq ( HPS_DDR3_DQ),
.hps_0_ddr_mem_dqs ( HPS_DDR3_DQS_P),
.hps_0_ddr_mem_dqs_n ( HPS_DDR3_DQS_N),
.hps_0_ddr_mem_odt ( HPS_DDR3_ODT),
.hps_0_ddr_mem_dm ( HPS_DDR3_DM),
.hps_0_ddr_oct_rzqin ( HPS_DDR3_RZQ),
///////////////////////////////////////// HPS Ethernet 1 ////////////////////////////////////////////
.hps_0_io_hps_io_emac1_inst_TX_CLK ( HPS_ENET_GTX_CLK),
.hps_0_io_hps_io_emac1_inst_TXD0 ( HPS_ENET_TX_DATA[0] ),
.hps_0_io_hps_io_emac1_inst_TXD1 ( HPS_ENET_TX_DATA[1] ),
.hps_0_io_hps_io_emac1_inst_TXD2 ( HPS_ENET_TX_DATA[2] ),
.hps_0_io_hps_io_emac1_inst_TXD3 ( HPS_ENET_TX_DATA[3] ),
.hps_0_io_hps_io_emac1_inst_RXD0 ( HPS_ENET_RX_DATA[0] ),
.hps_0_io_hps_io_emac1_inst_MDIO ( HPS_ENET_MDIO ),
.hps_0_io_hps_io_emac1_inst_MDC ( HPS_ENET_MDC ),
.hps_0_io_hps_io_emac1_inst_RX_CTL ( HPS_ENET_RX_DV),
.hps_0_io_hps_io_emac1_inst_TX_CTL ( HPS_ENET_TX_EN),
.hps_0_io_hps_io_emac1_inst_RX_CLK ( HPS_ENET_RX_CLK),
.hps_0_io_hps_io_emac1_inst_RXD1 ( HPS_ENET_RX_DATA[1] ),
.hps_0_io_hps_io_emac1_inst_RXD2 ( HPS_ENET_RX_DATA[2] ),
.hps_0_io_hps_io_emac1_inst_RXD3 ( HPS_ENET_RX_DATA[3] ),
/////////////////////////////////////// SD Card Boot drive ///////////////////////////////////////////
.hps_0_io_hps_io_sdio_inst_CMD ( HPS_SD_CMD ),
.hps_0_io_hps_io_sdio_inst_D0 ( HPS_SD_DATA[0] ),
.hps_0_io_hps_io_sdio_inst_D1 ( HPS_SD_DATA[1] ),
.hps_0_io_hps_io_sdio_inst_CLK ( HPS_SD_CLK ),
.hps_0_io_hps_io_sdio_inst_D2 ( HPS_SD_DATA[2] ),
.hps_0_io_hps_io_sdio_inst_D3 ( HPS_SD_DATA[3] ),
////////////////////////////////////////// USB HOST //////////////////////////////////////////////
.hps_0_io_hps_io_usb1_inst_D0 ( HPS_USB_DATA[0] ),
.hps_0_io_hps_io_usb1_inst_D1 ( HPS_USB_DATA[1] ),
.hps_0_io_hps_io_usb1_inst_D2 ( HPS_USB_DATA[2] ),
.hps_0_io_hps_io_usb1_inst_D3 ( HPS_USB_DATA[3] ),
.hps_0_io_hps_io_usb1_inst_D4 ( HPS_USB_DATA[4] ),
.hps_0_io_hps_io_usb1_inst_D5 ( HPS_USB_DATA[5] ),
.hps_0_io_hps_io_usb1_inst_D6 ( HPS_USB_DATA[6] ),
.hps_0_io_hps_io_usb1_inst_D7 ( HPS_USB_DATA[7] ),
.hps_0_io_hps_io_usb1_inst_CLK ( HPS_USB_CLKOUT ),
.hps_0_io_hps_io_usb1_inst_STP ( HPS_USB_STP ),
.hps_0_io_hps_io_usb1_inst_DIR ( HPS_USB_DIR ),
.hps_0_io_hps_io_usb1_inst_NXT ( HPS_USB_NXT ),
//////////////////////////////////////// UART 0 (Console) ///////////////////////////////////////////
.hps_0_io_hps_io_uart0_inst_RX ( HPS_UART_RX ),
.hps_0_io_hps_io_uart0_inst_TX ( HPS_UART_TX ),
//////////////////////////////////////////////////////////////////////////////////////////////////////
/////////////////////////////// HPS Hard IP to FPGA Mapping /////////////////////////////////////
///////////////////////////////////////////// HPS UART 1 /////////////////////////////////////////////
.hps_0_uart1_cts (),
.hps_0_uart1_dsr (),
.hps_0_uart1_dcd (),
.hps_0_uart1_ri (),
.hps_0_uart1_dtr (),
.hps_0_uart1_rts (),
.hps_0_uart1_out1_n (),
.hps_0_uart1_out2_n (),
.hps_0_uart1_rxd (uart1_rx),
.hps_0_uart1_txd (uart1_tx),
///////////////////////////////////////////////// I2C1 ///////////////////////////////////////////////
.hps_0_i2c1_clk_clk (scl1_o_e),
.hps_0_i2c1_scl_in_clk (scl1_o),
.hps_0_i2c1_out_data (sda1_o_e),
.hps_0_i2c1_sda (sda1_o),
////////////////////////////////////////////////// I2C3 //////////////////////////////////////////////
.hps_0_i2c3_scl_in_clk (scl3_o_e),
.hps_0_i2c3_clk_clk (scl3_o),
.hps_0_i2c3_out_data (sda3_o_e),
.hps_0_i2c3_sda (sda3_o),
//////////////////////////////////////////////// CAN0 ////////////////////////////////////////////////
.hps_0_can0_rxd (can0_rx),
.hps_0_can0_txd (can0_tx),
//////////////////////////////////////////////// SPI0 Master ////////////////////////////////////////
.hps_0_spim0_sclk_out_clk (spi0_clk),
.hps_0_spim0_txd (spi0_mosi),
.hps_0_spim0_rxd (spi0_miso),
.hps_0_spim0_ss_in_n (1'b1),
.hps_0_spim0_ssi_oe_n (spim0_ssi_oe_n),
.hps_0_spim0_ss_0_n (spi0_ss_0_n),
.hps_0_spim0_ss_1_n (),
.hps_0_spim0_ss_2_n (),
.hps_0_spim0_ss_3_n (),
///////////////////////////////////////////////////////////////////////////////////////////////////////
////////////////////////////////// On Board Compunents ////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////// Analog Devices LTC2308 ////////////////////////////////
.adc_ltc2308_conduit_end_CONVST (ADC_CONVST),
.adc_ltc2308_conduit_end_SCK (ADC_SCK),
.adc_ltc2308_conduit_end_SDI (ADC_SDI),
.adc_ltc2308_conduit_end_SDO (ADC_SDO),
/////////////////////////////////////////// HPS LED & KEY ///////////////////////////////////////////
.hps_0_io_hps_io_gpio_inst_GPIO53 ( HPS_LED),
.hps_0_io_hps_io_gpio_inst_GPIO54 ( HPS_KEY),
////////////////////////////////// G-Sensor: I2C0 (Terasic Docu I2C1) ////////////////////////////////
.hps_0_io_hps_io_i2c0_inst_SDA (HPS_I2C1_SDAT),
.hps_0_io_hps_io_i2c0_inst_SCL (HPS_I2C1_SCLK),
/////////////////////////////////// onboard LEDs, Switches and Keys ///////////////////////////////////
.led_pio_external_connection_export (LED),
.pb_pio_external_connection_export (KEY),
.sw_pio_external_connection_export (SW),
////////////////////////////////// HPS -> FPGA GPIO ///////////////////////////////////
// 32-Bit direct access registry between HPS and FPGA
.hps_0_h2f_gp_gp_in (32'hACDCACDC), // FPGA to HPS -->
.hps_0_h2f_gp_gp_out () // HPS to FPGA <--
);
//////////////////////////// DE10 NANO //////////////////////////////
//////////// Arduino Shild IF ///////////////
///////////////////////////////////////////
// PIN | Uno func-> mapped func //
// D0 | TXD -> UART1 RX //
// D1 | RXD -> UART1 TX //
// D2 | INT0 -> I2C3 SDA //
// D3 | INT1 -> I2C3 SCL //
// D4 | T0 -> //
// D5 | T1 -> //
// D6 | AIN0 -> //
// D7 | AIN1 -> //
// D8 | CLKO -> CAN0 TX //
// D9 | OC1A -> CAN0 RX //
// D10 | SS -> SPIO CS //
// D11 | MOSI -> SPIO MOSI //
// D12 | MISO -> SPIO MISO //
// D13 | SCK -> SPIO CLK //
// | GND //
// | AREF //
// | I2C -> I2C1 SDA //
// | I2C -> I2C1 SCL //
///////////////////////////////////////////
////////////////////////////////////////// IO Buffer SPI 0 /////////////////////////////////////////////
// SPI0 -> CS
ALT_IOBUF spi0_ss_iobuf (.i(spi0_ss_0_n), .oe(1'b1), .o(), .io(ARDUINO_IO[10]));
// SPI0 -> MOSI
ALT_IOBUF spi0_mosi_iobuf (.i(spi0_mosi), .oe(1'b1), .o(), .io(ARDUINO_IO[11]));
// SPI0 -> MISO
ALT_IOBUF spi0_miso_iobuf (.i(1'b0), .oe(1'b0), .o(spi0_miso), .io(ARDUINO_IO[12]));
// SPI0 -> CLK
ALT_IOBUF spi0_clk_iobuf (.i(spi0_clk), .oe(1'b1), .o(), .io(ARDUINO_IO[13]));
////////////////////////////////////////// IO Buffer I2C 1 and 3 //////////////////////////////////////
// I2C1 -> SCL
ALT_IOBUF i2c1_scl_iobuf (.i(1'b0),.oe(scl1_o_e),.o(scl1_o),.io(ARDUINO_IO[15]));
// I2C1 -> SDA
ALT_IOBUF i2c1_sda_iobuf (.i(1'b0),.oe(sda1_o_e),.o(sda1_o),.io(ARDUINO_IO[14]));
// I2C3 -> SCL
ALT_IOBUF i2c3_scl_iobuf (.i(1'b0),.oe(scl3_o_e),.o(scl3_o),.io(ARDUINO_IO[3]));
// I2C3 -> SDA
ALT_IOBUF i2c3_sda_iobuf (.i(1'b0),.oe(sda3_o_e),.o(sda3_o),.io(ARDUINO_IO[2]));
////////////////////////////////////////// IO Buffer UART1 //////////////////////////////////////////
// UART1 -> RX
ALT_IOBUF uart1_rx_iobuf (.i(1'b0), .oe(1'b0), .o(uart1_rx), .io(ARDUINO_IO[1]));
// UART1 -> TX
ALT_IOBUF uart1_tx_iobuf (.i(uart1_tx), .oe(1'b1), .o(), .io(ARDUINO_IO[0]));
////////////////////////////////////////// IO Buffer CAN0 ///////////////////////////////////////////
// CANO -> RX
ALT_IOBUF can0_rx_iobuf (.i(1'b0), .oe(1'b0), .o(can0_rx), .io(ARDUINO_IO[9]));
// CAN-> TX
ALT_IOBUF can0_tx_iobuf (.i(can0_tx), .oe(1'b1), .o(), .io(ARDUINO_IO[8]));
endmodule
|
module s27 (
G1,
G2,
clk_net,
reset_net,
G3,
G0,
G17);
// Start PIs
input G1;
input G2;
input clk_net;
input reset_net;
input G3;
input G0;
// Start POs
output G17;
// Start wires
wire G1;
wire net_5;
wire net_15;
wire net_27;
wire G17;
wire reset_net;
wire net_14;
wire G3;
wire net_26;
wire clk_net;
wire net_13;
wire G2;
wire net_19;
wire net_3;
wire net_22;
wire net_16;
wire net_6;
wire net_24;
wire net_11;
wire net_1;
wire net_23;
wire net_18;
wire net_12;
wire net_2;
wire net_10;
wire net_8;
wire net_9;
wire net_25;
wire net_21;
wire net_7;
wire net_20;
wire G0;
wire net_4;
wire net_17;
// Start cells
CLKBUF_X2 inst_19 ( .A(net_17), .Z(net_18) );
DFFR_X2 inst_14 ( .RN(net_12), .D(net_10), .QN(net_3), .CK(net_27) );
INV_X1 inst_12 ( .A(net_16), .ZN(G17) );
INV_X4 inst_8 ( .ZN(net_5), .A(net_1) );
NOR2_X4 inst_2 ( .ZN(net_11), .A2(net_9), .A1(net_6) );
NOR2_X4 inst_1 ( .A1(net_14), .ZN(net_8), .A2(G3) );
CLKBUF_X2 inst_21 ( .A(net_19), .Z(net_20) );
CLKBUF_X2 inst_25 ( .A(net_23), .Z(net_24) );
NAND2_X2 inst_7 ( .ZN(net_7), .A1(net_4), .A2(net_3) );
CLKBUF_X2 inst_20 ( .A(net_18), .Z(net_19) );
INV_X1 inst_13 ( .ZN(net_12), .A(reset_net) );
CLKBUF_X2 inst_27 ( .A(net_25), .Z(net_26) );
CLKBUF_X2 inst_26 ( .A(net_17), .Z(net_25) );
NOR3_X4 inst_0 ( .ZN(net_16), .A1(net_11), .A3(net_8), .A2(net_5) );
CLKBUF_X2 inst_18 ( .A(clk_net), .Z(net_17) );
DFFR_X2 inst_15 ( .D(net_16), .RN(net_12), .QN(net_2), .CK(net_19) );
DFFR_X2 inst_16 ( .D(net_13), .RN(net_12), .QN(net_1), .CK(net_24) );
CLKBUF_X2 inst_24 ( .A(net_22), .Z(net_23) );
NOR2_X2 inst_3 ( .ZN(net_14), .A1(net_2), .A2(G0) );
NOR2_X2 inst_6 ( .A1(net_16), .A2(net_15), .ZN(net_13) );
INV_X4 inst_9 ( .ZN(net_9), .A(net_7) );
NOR2_X2 inst_5 ( .ZN(net_10), .A2(net_9), .A1(G2) );
INV_X2 inst_10 ( .ZN(net_4), .A(G1) );
NOR2_X2 inst_4 ( .ZN(net_6), .A1(net_2), .A2(G0) );
CLKBUF_X2 inst_23 ( .A(net_21), .Z(net_22) );
INV_X2 inst_11 ( .ZN(net_15), .A(G0) );
CLKBUF_X2 inst_28 ( .A(net_26), .Z(net_27) );
CLKBUF_X2 inst_22 ( .A(net_20), .Z(net_21) );
endmodule
|
module s349 (
B0,
A1,
B1,
A2,
A3,
blif_clk_net,
START,
B3,
A0,
blif_reset_net,
B2,
P7,
P5,
CNTVCON2,
P2,
P1,
CNTVCO2,
P0,
P6,
READY,
P3,
P4);
// Start PIs
input B0;
input A1;
input B1;
input A2;
input A3;
input blif_clk_net;
input START;
input B3;
input A0;
input blif_reset_net;
input B2;
// Start POs
output P7;
output P5;
output CNTVCON2;
output P2;
output P1;
output CNTVCO2;
output P0;
output P6;
output READY;
output P3;
output P4;
// Start wires
wire net_166;
wire net_107;
wire net_47;
wire net_179;
wire net_176;
wire net_159;
wire net_61;
wire net_137;
wire net_132;
wire net_54;
wire net_105;
wire net_62;
wire P3;
wire net_6;
wire net_129;
wire net_119;
wire net_98;
wire net_23;
wire P5;
wire net_117;
wire net_12;
wire B1;
wire net_151;
wire net_74;
wire net_53;
wire net_93;
wire net_168;
wire net_135;
wire net_130;
wire net_147;
wire net_127;
wire net_14;
wire P1;
wire net_113;
wire net_26;
wire net_76;
wire blif_clk_net;
wire net_101;
wire net_32;
wire net_111;
wire net_90;
wire net_40;
wire net_100;
wire net_85;
wire net_69;
wire net_124;
wire net_161;
wire net_141;
wire net_160;
wire net_83;
wire net_115;
wire B3;
wire net_4;
wire net_95;
wire net_17;
wire net_173;
wire net_78;
wire A1;
wire net_27;
wire net_164;
wire net_56;
wire net_87;
wire net_0;
wire net_155;
wire net_35;
wire net_16;
wire net_22;
wire net_181;
wire net_39;
wire net_157;
wire net_144;
wire net_102;
wire net_2;
wire net_59;
wire net_9;
wire net_42;
wire net_120;
wire A3;
wire net_109;
wire net_80;
wire net_65;
wire blif_reset_net;
wire net_50;
wire net_162;
wire net_96;
wire net_66;
wire net_38;
wire net_44;
wire net_167;
wire net_136;
wire net_134;
wire net_19;
wire net_89;
wire net_45;
wire net_126;
wire B0;
wire net_34;
wire net_108;
wire net_178;
wire net_150;
wire net_63;
wire P2;
wire net_152;
wire net_116;
wire net_30;
wire net_175;
wire net_91;
wire net_106;
wire net_24;
wire net_55;
wire net_99;
wire net_46;
wire net_140;
wire net_118;
wire P7;
wire net_148;
wire net_104;
wire net_146;
wire net_72;
wire net_122;
wire net_25;
wire net_7;
wire net_70;
wire P4;
wire net_172;
wire net_5;
wire net_52;
wire net_165;
wire net_128;
wire P0;
wire net_138;
wire net_13;
wire P6;
wire net_94;
wire net_11;
wire CNTVCON2;
wire net_18;
wire net_123;
wire net_131;
wire net_114;
wire CNTVCO2;
wire net_170;
wire net_29;
wire net_68;
wire net_149;
wire net_142;
wire net_77;
wire net_20;
wire net_31;
wire net_36;
wire net_49;
wire net_158;
wire net_15;
wire net_41;
wire net_57;
wire A2;
wire net_71;
wire net_153;
wire START;
wire net_156;
wire net_3;
wire net_84;
wire net_174;
wire net_154;
wire net_112;
wire net_1;
wire net_92;
wire net_103;
wire net_139;
wire net_43;
wire net_10;
wire net_180;
wire net_28;
wire net_169;
wire net_21;
wire net_51;
wire net_171;
wire net_79;
wire net_143;
wire net_97;
wire net_88;
wire net_182;
wire net_145;
wire net_60;
wire net_81;
wire net_163;
wire net_58;
wire B2;
wire net_67;
wire net_82;
wire net_64;
wire net_37;
wire net_110;
wire net_121;
wire net_73;
wire net_33;
wire net_48;
wire net_177;
wire net_8;
wire net_75;
wire net_86;
wire net_133;
wire READY;
wire A0;
wire net_125;
// Start cells
CLKBUF_X2 inst_145 ( .A(net_133), .Z(net_134) );
INV_X4 inst_103 ( .ZN(net_64), .A(net_52) );
DFFR_X2 inst_125 ( .RN(net_102), .D(net_73), .QN(net_6), .CK(net_179) );
DFFR_X1 inst_138 ( .D(net_103), .RN(net_102), .QN(net_2), .CK(net_150) );
CLKBUF_X2 inst_159 ( .A(net_147), .Z(net_148) );
NOR2_X2 inst_15 ( .ZN(net_85), .A2(net_77), .A1(START) );
DFFR_X2 inst_134 ( .RN(net_102), .D(net_87), .QN(net_13), .CK(net_146) );
CLKBUF_X2 inst_179 ( .A(blif_clk_net), .Z(net_168) );
NAND3_X2 inst_24 ( .A2(net_100), .ZN(net_99), .A3(net_95), .A1(net_61) );
INV_X2 inst_114 ( .A(net_42), .ZN(P1) );
OR2_X2 inst_6 ( .A2(net_113), .ZN(net_90), .A1(net_89) );
DFFR_X2 inst_131 ( .RN(net_102), .D(net_86), .QN(net_9), .CK(net_159) );
INV_X4 inst_76 ( .A(net_128), .ZN(net_126) );
CLKBUF_X2 inst_180 ( .A(net_168), .Z(net_169) );
CLKBUF_X2 inst_160 ( .A(net_148), .Z(net_149) );
CLKBUF_X2 inst_150 ( .A(net_138), .Z(net_139) );
NAND2_X4 inst_33 ( .ZN(net_112), .A1(net_52), .A2(net_2) );
CLKBUF_X2 inst_172 ( .A(net_137), .Z(net_161) );
INV_X4 inst_83 ( .ZN(net_56), .A(net_3) );
NAND2_X2 inst_47 ( .ZN(net_39), .A1(net_38), .A2(READY) );
NAND3_X2 inst_19 ( .ZN(net_71), .A3(net_70), .A2(net_46), .A1(P5) );
INV_X1 inst_123 ( .ZN(net_102), .A(blif_reset_net) );
INV_X2 inst_121 ( .ZN(net_111), .A(net_65) );
OR2_X4 inst_2 ( .ZN(net_40), .A2(READY), .A1(B3) );
NOR3_X2 inst_8 ( .ZN(net_80), .A1(net_78), .A3(net_51), .A2(START) );
INV_X2 inst_118 ( .ZN(net_70), .A(net_68) );
INV_X4 inst_86 ( .ZN(net_100), .A(START) );
CLKBUF_X2 inst_153 ( .A(net_141), .Z(net_142) );
NAND3_X2 inst_20 ( .A3(net_117), .ZN(net_116), .A1(net_113), .A2(P6) );
NAND3_X2 inst_27 ( .A3(net_109), .A1(net_108), .ZN(net_103), .A2(net_100) );
NAND2_X4 inst_38 ( .A1(net_105), .ZN(net_94), .A2(net_89) );
INV_X4 inst_100 ( .ZN(net_45), .A(net_32) );
NAND2_X2 inst_52 ( .ZN(net_57), .A1(net_35), .A2(net_34) );
INV_X4 inst_90 ( .ZN(net_17), .A(net_2) );
AND2_X4 inst_140 ( .A1(net_121), .ZN(net_118), .A2(net_0) );
NAND2_X4 inst_40 ( .A1(net_104), .ZN(net_97), .A2(net_66) );
CLKBUF_X2 inst_162 ( .A(net_148), .Z(net_151) );
CLKBUF_X2 inst_167 ( .A(net_146), .Z(net_156) );
INV_X4 inst_93 ( .ZN(net_18), .A(net_16) );
INV_X4 inst_81 ( .ZN(net_24), .A(net_10) );
INV_X4 inst_95 ( .ZN(net_23), .A(net_18) );
XNOR2_X2 inst_1 ( .ZN(net_79), .A(net_78), .B(net_27) );
MUX2_X2 inst_72 ( .S(net_123), .Z(net_83), .A(net_60), .B(net_38) );
CLKBUF_X3 inst_139 ( .A(net_121), .Z(P0) );
CLKBUF_X2 inst_155 ( .A(net_143), .Z(net_144) );
NAND2_X2 inst_59 ( .A2(net_128), .ZN(net_109), .A1(net_20) );
DFFR_X2 inst_135 ( .RN(net_102), .D(net_96), .QN(net_0), .CK(net_142) );
NAND2_X2 inst_44 ( .A2(net_121), .ZN(net_53), .A1(net_33) );
NAND2_X2 inst_55 ( .ZN(net_60), .A1(net_44), .A2(net_43) );
CLKBUF_X2 inst_174 ( .A(net_162), .Z(net_163) );
INV_X2 inst_115 ( .ZN(net_19), .A(P5) );
NAND2_X4 inst_37 ( .A1(net_114), .A2(net_112), .ZN(net_105) );
CLKBUF_X2 inst_148 ( .A(net_136), .Z(net_137) );
CLKBUF_X2 inst_164 ( .A(net_152), .Z(net_153) );
CLKBUF_X2 inst_191 ( .A(net_154), .Z(net_180) );
OR2_X2 inst_5 ( .ZN(net_35), .A2(READY), .A1(B0) );
CLKBUF_X2 inst_157 ( .A(net_145), .Z(net_146) );
INV_X4 inst_84 ( .ZN(net_38), .A(net_12) );
NAND2_X2 inst_51 ( .ZN(net_66), .A1(net_56), .A2(net_53) );
CLKBUF_X2 inst_142 ( .A(net_130), .Z(net_131) );
INV_X4 inst_80 ( .ZN(net_16), .A(net_8) );
CLKBUF_X2 inst_173 ( .A(net_161), .Z(net_162) );
INV_X2 inst_105 ( .A(net_128), .ZN(net_127) );
MUX2_X2 inst_68 ( .S(net_122), .Z(net_72), .B(net_33), .A(A3) );
INV_X4 inst_78 ( .ZN(net_120), .A(P0) );
NAND2_X2 inst_42 ( .ZN(net_48), .A1(net_27), .A2(net_23) );
CLKBUF_X2 inst_175 ( .A(net_139), .Z(net_164) );
NAND2_X2 inst_53 ( .ZN(net_58), .A1(net_41), .A2(net_39) );
CLKBUF_X2 inst_177 ( .A(net_165), .Z(net_166) );
CLKBUF_X2 inst_183 ( .A(net_171), .Z(net_172) );
DFFR_X2 inst_133 ( .QN(net_121), .RN(net_102), .D(net_88), .CK(net_132) );
NAND3_X2 inst_26 ( .A2(net_125), .ZN(net_108), .A3(net_107), .A1(net_106) );
CLKBUF_X2 inst_151 ( .A(net_139), .Z(net_140) );
INV_X2 inst_112 ( .A(net_38), .ZN(P2) );
NAND2_X2 inst_64 ( .ZN(net_115), .A2(net_94), .A1(net_90) );
INV_X2 inst_107 ( .A(net_114), .ZN(net_113) );
NAND2_X2 inst_67 ( .A1(net_126), .ZN(net_98), .A2(net_97) );
CLKBUF_X2 inst_181 ( .A(net_169), .Z(net_170) );
DFFR_X2 inst_127 ( .RN(net_102), .D(net_80), .QN(net_8), .CK(net_172) );
MUX2_X2 inst_70 ( .S(net_122), .Z(net_74), .B(net_21), .A(A1) );
CLKBUF_X2 inst_186 ( .A(net_174), .Z(net_175) );
DFFR_X2 inst_129 ( .RN(net_102), .D(net_85), .QN(net_10), .CK(net_163) );
INV_X4 inst_92 ( .A(net_15), .ZN(P5) );
NAND2_X4 inst_29 ( .A1(net_118), .ZN(net_68), .A2(net_30) );
CLKBUF_X2 inst_189 ( .A(net_158), .Z(net_178) );
NAND3_X4 inst_17 ( .ZN(net_49), .A2(net_24), .A3(net_16), .A1(net_9) );
NOR2_X2 inst_11 ( .ZN(net_51), .A2(net_49), .A1(net_26) );
CLKBUF_X2 inst_146 ( .A(net_134), .Z(net_135) );
CLKBUF_X2 inst_188 ( .A(net_176), .Z(net_177) );
NOR2_X2 inst_14 ( .A1(net_129), .ZN(net_81), .A2(net_70) );
CLKBUF_X2 inst_187 ( .A(net_175), .Z(net_176) );
INV_X2 inst_122 ( .A(net_94), .ZN(net_92) );
NAND2_X4 inst_31 ( .ZN(net_128), .A2(net_122), .A1(net_49) );
NAND3_X2 inst_25 ( .ZN(net_101), .A2(net_100), .A3(net_98), .A1(net_63) );
DFFR_X2 inst_126 ( .RN(net_102), .D(net_75), .QN(net_4), .CK(net_177) );
CLKBUF_X2 inst_158 ( .A(net_138), .Z(net_147) );
CLKBUF_X2 inst_141 ( .A(blif_clk_net), .Z(net_130) );
NAND2_X2 inst_62 ( .A1(net_128), .ZN(net_82), .A2(net_57) );
INV_X2 inst_110 ( .A(net_56), .ZN(P7) );
MUX2_X2 inst_74 ( .S(net_124), .Z(net_87), .B(net_69), .A(net_59) );
NAND2_X2 inst_57 ( .A2(net_128), .ZN(net_62), .A1(net_54) );
NAND2_X4 inst_35 ( .ZN(net_89), .A1(net_64), .A2(net_17) );
INV_X4 inst_99 ( .A(net_49), .ZN(READY) );
NAND2_X2 inst_48 ( .ZN(net_43), .A1(net_42), .A2(READY) );
MUX2_X2 inst_69 ( .S(net_122), .Z(net_73), .B(net_28), .A(A2) );
NAND2_X2 inst_46 ( .ZN(net_37), .A1(net_36), .A2(READY) );
INV_X4 inst_82 ( .ZN(net_21), .A(net_5) );
DFFR_X2 inst_136 ( .RN(net_102), .D(net_99), .QN(net_1), .CK(net_140) );
NAND2_X4 inst_30 ( .A1(net_121), .ZN(net_29), .A2(net_28) );
INV_X4 inst_102 ( .ZN(net_46), .A(net_45) );
INV_X2 inst_108 ( .ZN(net_33), .A(net_7) );
CLKBUF_X2 inst_165 ( .A(net_153), .Z(net_154) );
NAND2_X4 inst_32 ( .ZN(net_129), .A1(net_45), .A2(net_15) );
NAND3_X2 inst_22 ( .A2(net_127), .A3(net_116), .A1(net_115), .ZN(net_95) );
CLKBUF_X2 inst_144 ( .A(net_131), .Z(net_133) );
NAND2_X4 inst_34 ( .ZN(net_119), .A2(net_68), .A1(net_47) );
NOR2_X2 inst_12 ( .ZN(net_78), .A1(net_25), .A2(READY) );
NAND2_X2 inst_56 ( .A2(net_128), .ZN(net_61), .A1(net_19) );
MUX2_X2 inst_71 ( .S(net_122), .Z(net_75), .B(net_30), .A(A0) );
NAND3_X2 inst_21 ( .A2(net_126), .ZN(net_93), .A3(net_91), .A1(net_71) );
INV_X4 inst_104 ( .ZN(net_67), .A(net_66) );
NAND2_X2 inst_60 ( .ZN(net_69), .A2(net_68), .A1(net_55) );
CLKBUF_X2 inst_169 ( .A(net_157), .Z(net_158) );
CLKBUF_X2 inst_168 ( .A(net_156), .Z(net_157) );
INV_X4 inst_97 ( .ZN(net_25), .A(net_23) );
CLKBUF_X2 inst_161 ( .A(net_149), .Z(net_150) );
DFFR_X2 inst_124 ( .RN(net_102), .D(net_72), .QN(net_7), .CK(net_182) );
NAND3_X2 inst_18 ( .ZN(net_122), .A2(net_18), .A3(net_10), .A1(net_9) );
NOR2_X2 inst_16 ( .ZN(net_86), .A2(net_79), .A1(START) );
INV_X4 inst_88 ( .ZN(net_15), .A(net_1) );
OR2_X4 inst_3 ( .ZN(net_41), .A2(READY), .A1(B2) );
CLKBUF_X2 inst_156 ( .A(net_144), .Z(net_145) );
NOR2_X2 inst_9 ( .A2(net_48), .A1(net_14), .ZN(CNTVCO2) );
INV_X2 inst_113 ( .A(net_36), .ZN(P3) );
CLKBUF_X2 inst_170 ( .A(net_158), .Z(net_159) );
NAND2_X2 inst_50 ( .ZN(net_55), .A1(net_54), .A2(net_31) );
DFFR_X2 inst_137 ( .RN(net_102), .D(net_101), .QN(net_3), .CK(net_137) );
NAND2_X4 inst_41 ( .A2(net_110), .ZN(net_106), .A1(net_97) );
DFFR_X2 inst_130 ( .RN(net_102), .D(net_83), .QN(net_11), .CK(net_160) );
INV_X4 inst_91 ( .A(net_24), .ZN(net_14) );
DFFR_X2 inst_132 ( .RN(net_102), .D(net_84), .QN(net_12), .CK(net_155) );
CLKBUF_X2 inst_143 ( .A(net_131), .Z(net_132) );
CLKBUF_X2 inst_176 ( .A(net_164), .Z(net_165) );
CLKBUF_X2 inst_152 ( .A(net_138), .Z(net_141) );
NAND2_X2 inst_58 ( .A2(net_128), .ZN(net_63), .A1(net_56) );
NAND2_X4 inst_36 ( .A2(net_129), .A1(net_119), .ZN(net_114) );
CLKBUF_X2 inst_147 ( .A(net_135), .Z(net_136) );
INV_X4 inst_87 ( .ZN(net_42), .A(net_11) );
NAND2_X2 inst_61 ( .A2(net_125), .ZN(net_76), .A1(net_42) );
NAND2_X2 inst_45 ( .A1(net_120), .ZN(net_34), .A2(READY) );
INV_X4 inst_96 ( .ZN(net_27), .A(net_9) );
INV_X4 inst_101 ( .ZN(net_52), .A(net_29) );
XNOR2_X2 inst_0 ( .ZN(net_77), .A(net_50), .B(net_24) );
CLKBUF_X2 inst_184 ( .A(net_142), .Z(net_173) );
NOR2_X2 inst_10 ( .ZN(net_50), .A1(net_48), .A2(READY) );
OR2_X4 inst_4 ( .ZN(net_44), .A2(READY), .A1(B1) );
NAND2_X2 inst_65 ( .ZN(net_110), .A2(net_94), .A1(net_67) );
CLKBUF_X2 inst_178 ( .A(net_166), .Z(net_167) );
INV_X4 inst_89 ( .ZN(net_54), .A(net_0) );
NAND2_X4 inst_28 ( .A2(net_121), .ZN(net_22), .A1(net_21) );
INV_X2 inst_111 ( .A(net_54), .ZN(P4) );
NAND2_X2 inst_66 ( .ZN(net_107), .A2(net_92), .A1(net_65) );
INV_X2 inst_117 ( .ZN(net_26), .A(net_25) );
INV_X4 inst_98 ( .ZN(net_32), .A(net_22) );
CLKBUF_X2 inst_190 ( .A(net_178), .Z(net_179) );
NAND2_X2 inst_63 ( .ZN(net_88), .A2(net_82), .A1(net_76) );
OR2_X2 inst_7 ( .A2(net_113), .ZN(net_91), .A1(net_81) );
CLKBUF_X2 inst_185 ( .A(net_173), .Z(net_174) );
CLKBUF_X2 inst_182 ( .A(net_170), .Z(net_171) );
NAND2_X2 inst_49 ( .ZN(net_47), .A1(net_32), .A2(net_1) );
INV_X2 inst_120 ( .ZN(net_117), .A(net_64) );
CLKBUF_X2 inst_154 ( .A(net_138), .Z(net_143) );
NOR2_X2 inst_13 ( .ZN(net_65), .A1(net_56), .A2(net_53) );
INV_X2 inst_119 ( .ZN(CNTVCON2), .A(CNTVCO2) );
INV_X8 inst_75 ( .A(net_128), .ZN(net_123) );
CLKBUF_X2 inst_192 ( .A(net_180), .Z(net_181) );
CLKBUF_X2 inst_166 ( .A(net_154), .Z(net_155) );
INV_X2 inst_116 ( .ZN(net_20), .A(P6) );
CLKBUF_X2 inst_163 ( .A(net_151), .Z(net_152) );
INV_X4 inst_85 ( .ZN(net_30), .A(net_4) );
NAND2_X2 inst_54 ( .ZN(net_59), .A1(net_40), .A2(net_37) );
INV_X4 inst_79 ( .ZN(net_36), .A(net_13) );
INV_X2 inst_109 ( .ZN(net_28), .A(net_6) );
INV_X2 inst_106 ( .A(net_128), .ZN(net_125) );
CLKBUF_X2 inst_193 ( .A(net_181), .Z(net_182) );
CLKBUF_X2 inst_149 ( .A(net_130), .Z(net_138) );
NAND2_X2 inst_43 ( .A2(net_121), .ZN(net_31), .A1(net_30) );
NAND2_X4 inst_39 ( .A2(net_111), .ZN(net_104), .A1(net_94) );
DFFR_X2 inst_128 ( .RN(net_102), .D(net_74), .QN(net_5), .CK(net_167) );
MUX2_X2 inst_73 ( .S(net_123), .Z(net_84), .A(net_58), .B(net_36) );
NAND3_X2 inst_23 ( .A2(net_100), .ZN(net_96), .A3(net_93), .A1(net_62) );
CLKBUF_X2 inst_171 ( .A(net_132), .Z(net_160) );
INV_X4 inst_77 ( .A(net_128), .ZN(net_124) );
INV_X4 inst_94 ( .A(net_17), .ZN(P6) );
endmodule
|
module s386 (
v4,
v3,
v5,
v1,
v0,
blif_clk_net,
v2,
v6,
blif_reset_net,
v13_D_11,
v13_D_6,
v13_D_10,
v13_D_12,
v13_D_7,
v13_D_8,
v13_D_9);
// Start PIs
input v4;
input v3;
input v5;
input v1;
input v0;
input blif_clk_net;
input v2;
input v6;
input blif_reset_net;
// Start POs
output v13_D_11;
output v13_D_6;
output v13_D_10;
output v13_D_12;
output v13_D_7;
output v13_D_8;
output v13_D_9;
// Start wires
wire net_166;
wire net_107;
wire net_47;
wire net_159;
wire v13_D_7;
wire net_61;
wire net_137;
wire net_132;
wire net_54;
wire net_105;
wire net_62;
wire net_6;
wire net_129;
wire net_119;
wire net_98;
wire net_23;
wire net_117;
wire net_12;
wire net_151;
wire net_74;
wire v13_D_12;
wire net_53;
wire net_93;
wire net_168;
wire net_135;
wire net_130;
wire net_147;
wire net_127;
wire net_14;
wire net_113;
wire net_26;
wire net_76;
wire blif_clk_net;
wire net_101;
wire net_32;
wire net_111;
wire net_90;
wire net_40;
wire net_100;
wire net_85;
wire net_69;
wire net_124;
wire net_161;
wire net_141;
wire net_160;
wire v1;
wire net_83;
wire net_115;
wire v2;
wire net_4;
wire net_95;
wire net_17;
wire net_78;
wire net_27;
wire net_164;
wire net_56;
wire net_87;
wire v13_D_11;
wire net_0;
wire net_155;
wire net_35;
wire v6;
wire net_16;
wire net_22;
wire net_39;
wire net_157;
wire net_144;
wire net_102;
wire v3;
wire net_2;
wire net_59;
wire net_9;
wire net_42;
wire net_120;
wire net_109;
wire net_80;
wire net_65;
wire blif_reset_net;
wire net_50;
wire net_162;
wire net_96;
wire net_66;
wire net_38;
wire net_44;
wire net_167;
wire net_136;
wire net_134;
wire net_19;
wire net_89;
wire net_45;
wire net_126;
wire net_34;
wire net_108;
wire v13_D_6;
wire net_150;
wire net_63;
wire net_152;
wire net_116;
wire net_30;
wire net_91;
wire net_24;
wire net_55;
wire net_99;
wire net_106;
wire net_46;
wire net_140;
wire net_118;
wire net_148;
wire net_104;
wire net_146;
wire v13_D_8;
wire net_72;
wire net_122;
wire net_25;
wire v0;
wire net_7;
wire net_70;
wire net_5;
wire net_52;
wire net_165;
wire net_128;
wire v5;
wire net_138;
wire net_13;
wire net_94;
wire net_11;
wire net_18;
wire net_123;
wire net_131;
wire net_114;
wire net_29;
wire net_68;
wire net_149;
wire net_142;
wire v13_D_10;
wire net_77;
wire net_20;
wire net_31;
wire net_36;
wire net_49;
wire net_158;
wire v4;
wire net_15;
wire net_41;
wire net_57;
wire net_71;
wire net_153;
wire net_156;
wire net_3;
wire net_84;
wire net_154;
wire net_1;
wire net_92;
wire net_112;
wire net_103;
wire net_139;
wire net_43;
wire net_10;
wire net_28;
wire net_169;
wire net_21;
wire net_51;
wire net_79;
wire net_143;
wire net_97;
wire net_88;
wire net_145;
wire net_60;
wire net_81;
wire net_163;
wire net_58;
wire v13_D_9;
wire net_67;
wire net_82;
wire net_64;
wire net_37;
wire net_110;
wire net_121;
wire net_73;
wire net_33;
wire net_48;
wire net_8;
wire net_75;
wire net_86;
wire net_133;
wire net_125;
// Start cells
DFFR_X2 inst_145 ( .QN(net_146), .RN(net_97), .D(net_90), .CK(net_165) );
INV_X4 inst_103 ( .ZN(net_43), .A(v1) );
INV_X4 inst_125 ( .ZN(net_24), .A(net_19) );
INV_X2 inst_138 ( .A(net_133), .ZN(net_132) );
CLKBUF_X2 inst_159 ( .A(net_151), .Z(net_152) );
NOR2_X2 inst_15 ( .A2(net_139), .ZN(net_13), .A1(net_12) );
INV_X4 inst_134 ( .ZN(net_94), .A(net_87) );
NAND4_X2 inst_24 ( .A3(net_74), .ZN(net_64), .A2(net_63), .A4(net_62), .A1(net_2) );
INV_X4 inst_114 ( .A(net_143), .ZN(net_14) );
NOR4_X2 inst_6 ( .A3(net_75), .A4(net_73), .A2(net_40), .A1(net_17), .ZN(v13_D_9) );
INV_X4 inst_131 ( .A(net_46), .ZN(net_32) );
NAND2_X2 inst_76 ( .A2(net_142), .ZN(net_122), .A1(net_51) );
CLKBUF_X2 inst_160 ( .A(net_152), .Z(net_153) );
AND4_X2 inst_150 ( .A3(net_146), .A4(net_129), .ZN(net_44), .A2(net_43), .A1(v4) );
NAND3_X2 inst_33 ( .ZN(net_102), .A2(net_74), .A1(net_68), .A3(net_65) );
CLKBUF_X2 inst_172 ( .A(net_164), .Z(net_165) );
NAND2_X2 inst_83 ( .A1(net_111), .ZN(net_78), .A2(net_31) );
NAND2_X4 inst_47 ( .ZN(net_85), .A2(net_31), .A1(net_24) );
NOR2_X2 inst_19 ( .ZN(net_49), .A1(net_23), .A2(net_14) );
INV_X4 inst_123 ( .ZN(net_25), .A(net_18) );
INV_X4 inst_121 ( .ZN(net_15), .A(net_14) );
OR2_X2 inst_2 ( .A2(net_147), .A1(net_143), .ZN(net_9) );
NOR3_X2 inst_8 ( .ZN(net_119), .A3(net_116), .A2(net_114), .A1(net_49) );
INV_X4 inst_118 ( .ZN(net_77), .A(net_75) );
NAND2_X2 inst_86 ( .ZN(net_110), .A2(net_72), .A1(net_52) );
AND2_X4 inst_153 ( .A2(net_148), .A1(net_147), .ZN(net_6) );
NOR2_X2 inst_20 ( .A1(net_132), .ZN(net_59), .A2(net_41) );
NAND3_X4 inst_27 ( .ZN(net_90), .A2(net_88), .A1(net_82), .A3(net_66) );
NAND3_X2 inst_38 ( .ZN(net_130), .A1(net_67), .A3(net_37), .A2(net_33) );
INV_X4 inst_100 ( .A(net_134), .ZN(net_133) );
NAND2_X4 inst_52 ( .A1(net_112), .ZN(net_106), .A2(net_68) );
NAND2_X2 inst_90 ( .A2(net_121), .A1(net_120), .ZN(net_112) );
INV_X2 inst_140 ( .ZN(net_0), .A(v2) );
NAND3_X2 inst_40 ( .ZN(net_81), .A3(net_48), .A2(net_39), .A1(net_30) );
CLKBUF_X2 inst_162 ( .A(net_154), .Z(net_155) );
CLKBUF_X2 inst_167 ( .A(blif_clk_net), .Z(net_160) );
NAND2_X2 inst_93 ( .A2(net_100), .A1(net_80), .ZN(v13_D_11) );
NAND2_X2 inst_81 ( .ZN(net_72), .A1(net_71), .A2(net_57) );
INV_X4 inst_95 ( .A(net_144), .ZN(net_138) );
OR2_X4 inst_1 ( .ZN(net_28), .A1(net_27), .A2(net_26) );
NAND2_X2 inst_72 ( .ZN(net_55), .A1(net_54), .A2(net_53) );
INV_X2 inst_139 ( .A(net_117), .ZN(net_116) );
AND2_X2 inst_155 ( .ZN(net_124), .A2(net_31), .A1(v1) );
NAND2_X2 inst_59 ( .ZN(net_141), .A1(net_19), .A2(net_7) );
INV_X4 inst_135 ( .ZN(net_95), .A(net_93) );
NAND3_X2 inst_44 ( .A1(net_103), .ZN(net_96), .A3(net_92), .A2(net_91) );
NAND2_X2 inst_55 ( .ZN(net_140), .A1(net_131), .A2(v2) );
CLKBUF_X2 inst_174 ( .A(net_166), .Z(net_167) );
INV_X4 inst_115 ( .A(net_146), .ZN(net_16) );
NAND3_X2 inst_37 ( .A2(net_147), .A1(net_105), .ZN(net_67), .A3(v4) );
DFFR_X2 inst_148 ( .QN(net_147), .RN(net_97), .D(net_95), .CK(net_156) );
CLKBUF_X2 inst_164 ( .A(net_154), .Z(net_157) );
NOR4_X2 inst_5 ( .A2(net_77), .A1(net_76), .A3(net_63), .ZN(v13_D_12), .A4(v0) );
CLKBUF_X2 inst_157 ( .A(net_149), .Z(net_150) );
NAND2_X2 inst_84 ( .A1(net_122), .ZN(net_109), .A2(net_71) );
NAND2_X4 inst_51 ( .A1(net_126), .ZN(net_120), .A2(net_31) );
INV_X2 inst_142 ( .ZN(net_40), .A(net_39) );
NAND2_X2 inst_80 ( .ZN(net_88), .A1(net_74), .A2(net_56) );
CLKBUF_X2 inst_173 ( .A(net_155), .Z(net_166) );
INV_X4 inst_105 ( .A(net_148), .ZN(net_34) );
NAND2_X2 inst_68 ( .ZN(net_121), .A2(net_65), .A1(v1) );
NAND2_X2 inst_78 ( .A1(net_134), .ZN(net_70), .A2(net_42) );
NAND3_X2 inst_42 ( .A1(net_110), .A3(net_92), .A2(net_91), .ZN(net_87) );
CLKBUF_X2 inst_175 ( .A(net_167), .Z(net_168) );
NAND2_X2 inst_53 ( .A2(net_145), .ZN(net_3), .A1(v1) );
INV_X4 inst_133 ( .A(net_85), .ZN(net_56) );
NAND4_X2 inst_26 ( .A4(net_102), .A1(net_101), .ZN(net_89), .A3(net_88), .A2(net_64) );
AND4_X2 inst_151 ( .A1(net_75), .A4(net_62), .A3(net_47), .ZN(v13_D_10), .A2(v1) );
INV_X4 inst_112 ( .ZN(net_75), .A(net_5) );
NAND2_X2 inst_64 ( .A2(net_143), .A1(net_140), .ZN(net_105) );
INV_X4 inst_107 ( .ZN(net_12), .A(v3) );
NAND2_X2 inst_67 ( .ZN(net_45), .A2(net_25), .A1(net_16) );
INV_X4 inst_127 ( .ZN(net_65), .A(net_36) );
NAND2_X2 inst_70 ( .A2(net_129), .ZN(net_48), .A1(net_28) );
INV_X4 inst_129 ( .ZN(net_38), .A(net_24) );
NAND2_X2 inst_92 ( .ZN(net_100), .A2(net_99), .A1(net_77) );
NAND3_X2 inst_29 ( .A2(net_136), .ZN(net_21), .A3(net_6), .A1(net_1) );
NOR2_X2 inst_17 ( .A1(net_147), .ZN(net_54), .A2(net_31) );
NOR2_X4 inst_11 ( .A1(net_131), .ZN(net_129), .A2(v3) );
DFFR_X2 inst_146 ( .QN(net_145), .RN(net_97), .D(net_89), .CK(net_161) );
NOR2_X2 inst_14 ( .A2(net_143), .ZN(net_125), .A1(net_63) );
INV_X4 inst_122 ( .ZN(net_68), .A(net_16) );
NAND3_X2 inst_31 ( .ZN(net_37), .A1(net_13), .A3(net_10), .A2(net_9) );
NAND4_X2 inst_25 ( .A2(net_115), .ZN(net_107), .A1(net_65), .A4(net_31), .A3(v0) );
INV_X4 inst_126 ( .A(net_147), .ZN(net_22) );
CLKBUF_X2 inst_158 ( .A(net_150), .Z(net_151) );
INV_X2 inst_141 ( .A(net_71), .ZN(net_17) );
NAND2_X2 inst_62 ( .A2(net_125), .A1(net_114), .ZN(net_33) );
INV_X4 inst_110 ( .ZN(net_5), .A(net_2) );
NAND2_X2 inst_74 ( .ZN(net_57), .A1(net_35), .A2(net_21) );
NAND2_X2 inst_57 ( .ZN(net_11), .A2(net_3), .A1(v0) );
NAND3_X2 inst_35 ( .A3(net_65), .ZN(net_60), .A2(net_54), .A1(v5) );
INV_X4 inst_99 ( .A(net_135), .ZN(net_134) );
NAND2_X4 inst_48 ( .A1(net_118), .ZN(net_113), .A2(net_85) );
NAND2_X2 inst_69 ( .ZN(net_47), .A1(net_46), .A2(net_4) );
NAND2_X4 inst_46 ( .A2(net_143), .A1(net_139), .ZN(net_36) );
NAND2_X2 inst_82 ( .ZN(net_126), .A2(net_70), .A1(net_43) );
INV_X4 inst_136 ( .ZN(net_98), .A(net_96) );
NAND3_X2 inst_30 ( .A1(net_147), .A2(net_129), .ZN(net_117), .A3(net_26) );
INV_X4 inst_102 ( .ZN(net_63), .A(v5) );
INV_X4 inst_108 ( .A(net_145), .ZN(net_2) );
CLKBUF_X2 inst_165 ( .A(net_157), .Z(net_158) );
NAND3_X2 inst_32 ( .A1(net_147), .ZN(net_142), .A2(net_135), .A3(net_34) );
NOR2_X2 inst_22 ( .A2(net_116), .ZN(net_79), .A1(net_59) );
DFFR_X2 inst_144 ( .QN(net_143), .RN(net_97), .D(net_86), .CK(net_169) );
NAND3_X2 inst_34 ( .A1(net_133), .ZN(net_50), .A3(net_18), .A2(v2) );
NOR2_X4 inst_12 ( .A2(net_146), .ZN(net_115), .A1(net_22) );
NAND2_X2 inst_56 ( .A2(net_143), .ZN(net_10), .A1(v2) );
NAND2_X2 inst_71 ( .ZN(net_76), .A2(net_62), .A1(net_46) );
NOR2_X2 inst_21 ( .ZN(net_73), .A1(net_69), .A2(net_44) );
INV_X4 inst_104 ( .ZN(net_74), .A(v0) );
NAND2_X2 inst_60 ( .A1(net_31), .ZN(net_29), .A2(net_5) );
CLKBUF_X2 inst_169 ( .A(net_155), .Z(net_162) );
CLKBUF_X2 inst_168 ( .A(net_160), .Z(net_161) );
INV_X4 inst_97 ( .A(net_138), .ZN(net_137) );
CLKBUF_X2 inst_161 ( .A(net_153), .Z(net_154) );
INV_X4 inst_124 ( .A(net_68), .ZN(net_46) );
NOR2_X2 inst_18 ( .ZN(net_62), .A2(net_36), .A1(net_8) );
NOR2_X2 inst_16 ( .ZN(net_53), .A1(net_36), .A2(v5) );
NAND2_X2 inst_88 ( .A1(net_130), .ZN(net_108), .A2(net_31) );
OR2_X2 inst_3 ( .ZN(net_52), .A2(net_51), .A1(net_15) );
CLKBUF_X2 inst_156 ( .A(blif_clk_net), .Z(net_149) );
NOR3_X2 inst_9 ( .A1(net_119), .ZN(net_86), .A3(net_85), .A2(net_84) );
INV_X4 inst_113 ( .ZN(net_8), .A(net_6) );
CLKBUF_X2 inst_170 ( .A(net_162), .Z(net_163) );
NAND2_X4 inst_50 ( .A2(net_124), .A1(net_123), .ZN(net_82) );
INV_X2 inst_137 ( .A(net_137), .ZN(net_136) );
NAND3_X2 inst_41 ( .ZN(net_104), .A1(net_78), .A3(net_55), .A2(net_50) );
INV_X4 inst_130 ( .ZN(net_39), .A(net_25) );
NAND2_X2 inst_91 ( .A2(net_107), .A1(net_106), .ZN(net_99) );
INV_X4 inst_132 ( .ZN(net_92), .A(net_38) );
INV_X1 inst_143 ( .ZN(net_97), .A(blif_reset_net) );
CLKBUF_X2 inst_176 ( .A(net_168), .Z(net_169) );
AND3_X1 inst_152 ( .A1(net_92), .A2(net_91), .A3(net_83), .ZN(v13_D_6) );
NAND2_X2 inst_58 ( .A2(net_146), .A1(net_145), .ZN(net_19) );
NAND3_X2 inst_36 ( .ZN(net_66), .A2(net_65), .A1(net_45), .A3(net_11) );
DFFR_X2 inst_147 ( .QN(net_148), .RN(net_97), .D(net_94), .CK(net_151) );
NAND2_X2 inst_87 ( .ZN(net_83), .A2(net_81), .A1(net_60) );
NAND2_X2 inst_61 ( .A1(net_71), .ZN(net_30), .A2(net_0) );
NAND2_X4 inst_45 ( .ZN(net_7), .A1(net_6), .A2(v0) );
INV_X4 inst_96 ( .ZN(net_139), .A(net_138) );
INV_X4 inst_101 ( .A(net_138), .ZN(net_131) );
OR2_X4 inst_0 ( .A1(net_147), .A2(net_143), .ZN(net_41) );
NOR3_X2 inst_10 ( .A1(net_85), .A2(net_84), .A3(net_79), .ZN(v13_D_7) );
NOR4_X2 inst_4 ( .A1(net_76), .A2(net_75), .A3(net_74), .ZN(v13_D_8), .A4(v6) );
NAND2_X2 inst_65 ( .A2(net_114), .ZN(net_35), .A1(net_34) );
NAND2_X2 inst_89 ( .A2(net_109), .A1(net_108), .ZN(net_103) );
NAND3_X2 inst_28 ( .A3(net_147), .A1(net_26), .ZN(net_20), .A2(net_12) );
INV_X4 inst_111 ( .A(net_34), .ZN(net_31) );
NAND2_X2 inst_66 ( .ZN(net_42), .A1(net_41), .A2(net_20) );
INV_X4 inst_117 ( .ZN(net_27), .A(net_14) );
INV_X4 inst_98 ( .A(net_136), .ZN(net_135) );
NAND2_X2 inst_63 ( .A2(net_128), .A1(net_127), .ZN(net_51) );
NOR3_X2 inst_7 ( .A1(net_132), .A2(net_74), .ZN(net_69), .A3(net_68) );
NAND2_X4 inst_49 ( .A1(net_113), .ZN(net_101), .A2(v1) );
INV_X4 inst_120 ( .ZN(net_91), .A(net_84) );
AND2_X2 inst_154 ( .ZN(net_1), .A2(v2), .A1(v3) );
NOR2_X2 inst_13 ( .A1(net_147), .A2(net_138), .ZN(net_114) );
INV_X4 inst_119 ( .ZN(net_71), .A(net_14) );
NAND2_X2 inst_75 ( .ZN(net_58), .A1(net_36), .A2(net_29) );
CLKBUF_X2 inst_166 ( .A(net_158), .Z(net_159) );
INV_X4 inst_116 ( .ZN(net_18), .A(net_8) );
CLKBUF_X2 inst_163 ( .A(net_155), .Z(net_156) );
NAND2_X2 inst_85 ( .ZN(net_123), .A2(net_61), .A1(net_38) );
NAND2_X2 inst_54 ( .ZN(net_84), .A2(net_43), .A1(v0) );
NAND2_X2 inst_79 ( .A1(net_117), .ZN(net_111), .A2(net_27) );
INV_X4 inst_109 ( .ZN(net_128), .A(net_34) );
INV_X4 inst_106 ( .ZN(net_26), .A(v4) );
DFFR_X2 inst_149 ( .QN(net_144), .D(net_98), .RN(net_97), .CK(net_159) );
NAND3_X2 inst_43 ( .A1(net_104), .ZN(net_93), .A3(net_92), .A2(net_91) );
NAND3_X2 inst_39 ( .ZN(net_80), .A2(net_74), .A3(net_58), .A1(net_32) );
INV_X4 inst_128 ( .ZN(net_23), .A(net_22) );
NAND2_X2 inst_73 ( .A1(net_141), .ZN(net_118), .A2(net_65) );
NOR2_X1 inst_23 ( .A2(net_147), .A1(net_137), .ZN(net_127) );
CLKBUF_X2 inst_171 ( .A(net_163), .Z(net_164) );
NAND2_X2 inst_77 ( .A1(net_115), .ZN(net_61), .A2(net_53) );
NAND2_X1 inst_94 ( .ZN(net_4), .A2(v0), .A1(v5) );
endmodule
|
module c499 (
nid20,
nid6,
nid21,
nic7,
nid0,
nid11,
nid13,
nr,
nic0,
nid1,
nic4,
nid10,
nid31,
nid3,
nic1,
nid22,
nic3,
nid26,
nid23,
nid16,
nid17,
nid27,
nid9,
nic2,
nid7,
nic5,
nid30,
nic6,
nid14,
nid29,
nid8,
nid12,
nid5,
nid15,
nid25,
nid18,
nid28,
nid24,
nid4,
nid19,
nid2,
nod24,
nod6,
nod23,
nod31,
nod14,
nod11,
nod19,
nod28,
nod12,
nod5,
nod13,
nod3,
nod21,
nod29,
nod1,
nod7,
nod17,
nod30,
nod18,
nod4,
nod10,
nod15,
nod0,
nod16,
nod20,
nod27,
nod2,
nod9,
nod25,
nod8,
nod26,
nod22);
// Start PIs
input nid20;
input nid6;
input nid21;
input nic7;
input nid0;
input nid11;
input nid13;
input nr;
input nic0;
input nid1;
input nic4;
input nid10;
input nid31;
input nid3;
input nic1;
input nid22;
input nic3;
input nid26;
input nid23;
input nid16;
input nid17;
input nid27;
input nid9;
input nic2;
input nid7;
input nic5;
input nid30;
input nic6;
input nid14;
input nid29;
input nid8;
input nid12;
input nid5;
input nid15;
input nid25;
input nid18;
input nid28;
input nid24;
input nid4;
input nid19;
input nid2;
// Start POs
output nod24;
output nod6;
output nod23;
output nod31;
output nod14;
output nod11;
output nod19;
output nod28;
output nod12;
output nod5;
output nod13;
output nod3;
output nod21;
output nod29;
output nod1;
output nod7;
output nod17;
output nod30;
output nod18;
output nod4;
output nod10;
output nod15;
output nod0;
output nod16;
output nod20;
output nod27;
output nod2;
output nod9;
output nod25;
output nod8;
output nod26;
output nod22;
// Start wires
wire net_107;
wire net_47;
wire nod23;
wire net_61;
wire net_137;
wire nid21;
wire net_132;
wire net_54;
wire net_105;
wire net_62;
wire net_6;
wire nid13;
wire net_129;
wire net_119;
wire net_98;
wire nod30;
wire net_23;
wire net_117;
wire net_12;
wire net_74;
wire net_53;
wire net_93;
wire net_135;
wire nid3;
wire net_130;
wire nic3;
wire nod26;
wire nid26;
wire nid23;
wire net_127;
wire net_14;
wire nid9;
wire net_113;
wire net_26;
wire net_76;
wire nid7;
wire net_101;
wire net_32;
wire nic6;
wire net_111;
wire net_90;
wire net_40;
wire nod7;
wire net_100;
wire nod4;
wire net_85;
wire net_69;
wire net_124;
wire nid5;
wire nid15;
wire nid25;
wire nid18;
wire net_141;
wire nid28;
wire net_83;
wire net_115;
wire net_4;
wire nid2;
wire net_95;
wire net_17;
wire net_78;
wire net_27;
wire nid20;
wire net_56;
wire net_87;
wire nod19;
wire net_0;
wire nod28;
wire nid0;
wire net_35;
wire net_22;
wire net_16;
wire nic0;
wire nod17;
wire net_39;
wire net_102;
wire net_2;
wire net_59;
wire net_9;
wire net_42;
wire net_120;
wire nic1;
wire net_109;
wire net_80;
wire net_65;
wire nod25;
wire net_50;
wire nod8;
wire net_96;
wire net_66;
wire net_38;
wire net_44;
wire nod11;
wire net_136;
wire net_134;
wire nod13;
wire net_19;
wire nid29;
wire net_89;
wire net_45;
wire net_126;
wire nod1;
wire net_34;
wire net_108;
wire nod15;
wire net_63;
wire nid6;
wire net_116;
wire net_30;
wire net_91;
wire nod21;
wire nod3;
wire net_106;
wire net_99;
wire net_24;
wire net_55;
wire net_46;
wire net_140;
wire net_118;
wire nr;
wire net_104;
wire nic4;
wire nid10;
wire nod16;
wire net_72;
wire net_122;
wire net_25;
wire net_70;
wire net_7;
wire nod9;
wire nod22;
wire nid17;
wire nid27;
wire nod6;
wire net_5;
wire net_52;
wire net_128;
wire net_138;
wire nic5;
wire nod12;
wire net_13;
wire nid30;
wire net_94;
wire nid12;
wire nod18;
wire net_11;
wire net_18;
wire net_123;
wire net_131;
wire net_114;
wire net_29;
wire net_68;
wire nod27;
wire net_142;
wire net_77;
wire net_20;
wire net_31;
wire net_36;
wire net_49;
wire net_15;
wire net_57;
wire nod31;
wire net_41;
wire net_71;
wire nic7;
wire nod5;
wire nid11;
wire net_3;
wire net_84;
wire nod29;
wire net_112;
wire net_92;
wire net_1;
wire net_103;
wire nid1;
wire net_139;
wire nod10;
wire net_43;
wire net_10;
wire nid31;
wire net_28;
wire net_21;
wire net_51;
wire net_79;
wire nid22;
wire net_143;
wire net_97;
wire nod24;
wire nid16;
wire net_88;
wire net_60;
wire nod14;
wire nic2;
wire net_81;
wire net_58;
wire nid14;
wire nid8;
wire net_82;
wire net_67;
wire net_64;
wire net_37;
wire net_110;
wire net_121;
wire net_73;
wire nod0;
wire nod20;
wire net_33;
wire net_48;
wire net_86;
wire net_75;
wire net_8;
wire nid24;
wire nid4;
wire net_133;
wire nod2;
wire nid19;
wire net_125;
// Start cells
NAND2_X1 inst_145 ( .A1(net_139), .A2(net_135), .ZN(net_104) );
XNOR2_X1 inst_103 ( .B(net_121), .ZN(nod10), .A(nid10) );
NAND2_X1 inst_125 ( .ZN(net_2), .A2(nr), .A1(nic7) );
NAND2_X1 inst_138 ( .A1(net_120), .A2(net_100), .ZN(net_96) );
NAND2_X1 inst_159 ( .A2(net_133), .ZN(net_127), .A1(net_110) );
XOR2_X1 inst_15 ( .Z(net_29), .A(nid20), .B(nid16) );
NAND2_X1 inst_134 ( .A2(net_95), .A1(net_93), .ZN(net_77) );
XOR2_X1 inst_24 ( .Z(net_38), .A(nid23), .B(nid19) );
NOR2_X1 inst_114 ( .ZN(net_116), .A2(net_94), .A1(net_93) );
XOR2_X1 inst_6 ( .Z(net_15), .A(nid6), .B(nid2) );
NAND2_X1 inst_131 ( .A1(net_117), .ZN(net_90), .A2(net_72) );
XNOR2_X1 inst_76 ( .B(net_126), .ZN(nod7), .A(nid7) );
NAND2_X1 inst_160 ( .A2(net_135), .ZN(net_129), .A1(net_128) );
NAND2_X1 inst_150 ( .A2(net_116), .ZN(net_111), .A1(net_110) );
XNOR2_X1 inst_33 ( .ZN(net_40), .B(net_27), .A(net_17) );
INV_X1 inst_172 ( .A(net_110), .ZN(net_89) );
XNOR2_X1 inst_83 ( .B(net_106), .ZN(nod29), .A(nid29) );
XNOR2_X1 inst_47 ( .ZN(net_47), .B(net_38), .A(net_37) );
XOR2_X1 inst_19 ( .Z(net_33), .A(nid30), .B(nid26) );
NAND2_X1 inst_123 ( .ZN(net_0), .A2(nr), .A1(nic0) );
NAND3_X1 inst_121 ( .A2(net_120), .ZN(net_94), .A3(net_86), .A1(net_83) );
XOR2_X1 inst_2 ( .Z(net_11), .A(nid8), .B(nid12) );
XOR2_X1 inst_8 ( .Z(net_17), .A(nid7), .B(nid3) );
NAND3_X1 inst_118 ( .A1(net_89), .ZN(net_81), .A2(net_80), .A3(net_76) );
XNOR2_X1 inst_86 ( .B(net_113), .ZN(nod26), .A(nid26) );
NAND2_X1 inst_153 ( .ZN(net_118), .A1(net_117), .A2(net_116) );
XOR2_X1 inst_20 ( .Z(net_34), .A(nid21), .B(nid20) );
XNOR2_X1 inst_27 ( .ZN(net_18), .A(nid17), .B(nid16) );
XNOR2_X1 inst_38 ( .ZN(net_58), .B(net_39), .A(net_20) );
XNOR2_X1 inst_100 ( .B(net_109), .ZN(nod13), .A(nid13) );
XNOR2_X1 inst_52 ( .ZN(net_59), .A(net_58), .B(net_51) );
XNOR2_X1 inst_90 ( .B(net_130), .ZN(nod22), .A(nid22) );
NAND2_X1 inst_140 ( .A2(net_114), .A1(net_110), .ZN(net_98) );
XNOR2_X1 inst_40 ( .ZN(net_49), .A(net_34), .B(net_9) );
NAND2_X1 inst_162 ( .A2(net_138), .ZN(net_132), .A1(net_131) );
NAND2_X1 inst_167 ( .ZN(net_141), .A1(net_139), .A2(net_124) );
XNOR2_X1 inst_93 ( .B(net_142), .ZN(nod2), .A(nid2) );
XNOR2_X1 inst_81 ( .B(net_102), .ZN(nod30), .A(nid30) );
XNOR2_X1 inst_95 ( .B(net_107), .ZN(nod18), .A(nid18) );
XOR2_X1 inst_1 ( .Z(net_10), .A(nid31), .B(nid30) );
XNOR2_X1 inst_72 ( .B(net_139), .A(net_120), .ZN(net_74) );
NAND2_X1 inst_139 ( .A1(net_128), .A2(net_100), .ZN(net_97) );
NAND2_X1 inst_155 ( .A2(net_138), .ZN(net_121), .A1(net_120) );
XNOR2_X1 inst_59 ( .ZN(net_67), .A(net_59), .B(net_1) );
NAND2_X1 inst_135 ( .ZN(net_85), .A2(net_84), .A1(net_78) );
XNOR2_X1 inst_44 ( .ZN(net_45), .A(net_33), .B(net_23) );
XNOR2_X1 inst_55 ( .ZN(net_63), .A(net_56), .B(net_54) );
INV_X1 inst_174 ( .ZN(net_139), .A(net_83) );
NOR2_X1 inst_115 ( .ZN(net_133), .A1(net_95), .A2(net_92) );
XNOR2_X1 inst_37 ( .ZN(net_54), .A(net_31), .B(net_18) );
NAND2_X1 inst_148 ( .A1(net_122), .ZN(net_108), .A2(net_105) );
NAND2_X1 inst_164 ( .ZN(net_136), .A2(net_135), .A1(net_131) );
XOR2_X1 inst_5 ( .Z(net_14), .A(nid9), .B(nid8) );
NAND2_X1 inst_157 ( .A1(net_128), .ZN(net_125), .A2(net_124) );
XNOR2_X1 inst_84 ( .B(net_108), .ZN(nod28), .A(nid28) );
XNOR2_X1 inst_51 ( .ZN(net_57), .A(net_56), .B(net_48) );
NAND2_X1 inst_142 ( .A1(net_131), .ZN(net_101), .A2(net_100) );
XNOR2_X1 inst_80 ( .B(net_99), .ZN(nod31), .A(nid31) );
INV_X1 inst_173 ( .A(net_120), .ZN(net_82) );
XNOR2_X1 inst_105 ( .B(net_129), .ZN(nod0), .A(nid0) );
XNOR2_X1 inst_68 ( .ZN(net_120), .B(net_70), .A(net_44) );
XNOR2_X1 inst_78 ( .B(net_101), .ZN(nod5), .A(nid5) );
XNOR2_X1 inst_42 ( .ZN(net_60), .A(net_35), .B(net_24) );
INV_X1 inst_175 ( .A(net_122), .ZN(net_72) );
XNOR2_X1 inst_53 ( .ZN(net_61), .B(net_60), .A(net_52) );
NAND2_X1 inst_133 ( .A2(net_90), .A1(net_88), .ZN(net_76) );
XNOR2_X1 inst_26 ( .ZN(net_8), .A(nid11), .B(nid10) );
NAND2_X1 inst_151 ( .A2(net_116), .ZN(net_113), .A1(net_112) );
NOR2_X1 inst_112 ( .ZN(net_135), .A2(net_91), .A1(net_88) );
XNOR2_X1 inst_64 ( .ZN(net_80), .B(net_67), .A(net_45) );
OR3_X4 inst_107 ( .A2(net_122), .A1(net_117), .ZN(net_79), .A3(net_75) );
XNOR2_X1 inst_67 ( .ZN(net_117), .B(net_65), .A(net_43) );
NAND2_X1 inst_127 ( .ZN(net_4), .A2(nr), .A1(nic5) );
XNOR2_X1 inst_70 ( .ZN(net_122), .B(net_71), .A(net_41) );
NAND2_X1 inst_129 ( .ZN(net_6), .A2(nr), .A1(nic1) );
XNOR2_X1 inst_92 ( .B(net_137), .ZN(nod20), .A(nid20) );
XNOR2_X1 inst_29 ( .ZN(net_24), .A(nid7), .B(nid6) );
XOR2_X1 inst_17 ( .Z(net_31), .A(nid19), .B(nid18) );
XOR2_X1 inst_11 ( .Z(net_21), .A(nid9), .B(nid13) );
NAND2_X1 inst_146 ( .A1(net_117), .ZN(net_106), .A2(net_105) );
XOR2_X1 inst_14 ( .Z(net_28), .A(nid13), .B(nid12) );
NAND3_X1 inst_122 ( .A2(net_112), .ZN(net_91), .A1(net_89), .A3(net_85) );
XNOR2_X1 inst_31 ( .ZN(net_27), .A(nid15), .B(nid11) );
XOR2_X1 inst_25 ( .Z(net_39), .A(nid3), .B(nid2) );
NAND2_X1 inst_126 ( .ZN(net_3), .A2(nr), .A1(nic3) );
NAND2_X1 inst_158 ( .A1(net_139), .ZN(net_126), .A2(net_100) );
NAND2_X1 inst_141 ( .A1(net_110), .A2(net_105), .ZN(net_99) );
XNOR2_X1 inst_62 ( .ZN(net_70), .A(net_63), .B(net_7) );
NOR3_X1 inst_110 ( .ZN(net_100), .A1(net_89), .A2(net_88), .A3(net_87) );
XNOR2_X1 inst_74 ( .B(net_132), .ZN(nod9), .A(nid9) );
XNOR2_X1 inst_57 ( .ZN(net_65), .A(net_53), .B(net_4) );
XNOR2_X1 inst_35 ( .ZN(net_42), .A(net_30), .B(net_11) );
XNOR2_X1 inst_99 ( .B(net_103), .ZN(nod14), .A(nid14) );
XNOR2_X1 inst_48 ( .ZN(net_50), .A(net_49), .B(net_48) );
XNOR2_X1 inst_69 ( .ZN(net_83), .B(net_64), .A(net_40) );
XNOR2_X1 inst_46 ( .ZN(net_51), .A(net_14), .B(net_8) );
XNOR2_X1 inst_82 ( .B(net_104), .ZN(nod3), .A(nid3) );
NAND2_X1 inst_136 ( .ZN(net_86), .A2(net_81), .A1(net_79) );
XNOR2_X1 inst_30 ( .ZN(net_26), .A(nid29), .B(nid28) );
XNOR2_X1 inst_102 ( .B(net_140), .ZN(nod11), .A(nid11) );
OR2_X4 inst_108 ( .A2(net_117), .ZN(net_88), .A1(net_72) );
NAND2_X1 inst_165 ( .ZN(net_137), .A2(net_133), .A1(net_122) );
XNOR2_X1 inst_32 ( .ZN(net_52), .B(net_28), .A(net_12) );
XOR2_X1 inst_22 ( .Z(net_36), .A(nid5), .B(nid1) );
NAND2_X1 inst_144 ( .A2(net_124), .A1(net_120), .ZN(net_103) );
XNOR2_X1 inst_34 ( .ZN(net_41), .B(net_29), .A(net_19) );
XOR2_X1 inst_12 ( .Z(net_22), .A(nid29), .B(nid25) );
XNOR2_X1 inst_56 ( .ZN(net_64), .A(net_50), .B(net_3) );
XNOR2_X1 inst_71 ( .ZN(net_131), .B(net_66), .A(net_46) );
XOR2_X1 inst_21 ( .Z(net_35), .A(nid5), .B(nid4) );
XNOR2_X1 inst_104 ( .B(net_136), .ZN(nod1), .A(nid1) );
XNOR2_X1 inst_60 ( .ZN(net_68), .A(net_61), .B(net_2) );
NAND2_X1 inst_169 ( .ZN(net_143), .A2(net_138), .A1(net_128) );
NAND2_X1 inst_168 ( .ZN(net_142), .A2(net_135), .A1(net_120) );
XNOR2_X1 inst_97 ( .B(net_119), .ZN(nod16), .A(nid16) );
NAND2_X1 inst_161 ( .A2(net_133), .ZN(net_130), .A1(net_112) );
NAND2_X1 inst_124 ( .ZN(net_1), .A2(nr), .A1(nic6) );
XOR2_X1 inst_18 ( .Z(net_32), .A(nid25), .B(nid24) );
XOR2_X1 inst_16 ( .Z(net_30), .A(nid4), .B(nid0) );
XNOR2_X1 inst_88 ( .B(net_123), .ZN(nod24), .A(nid24) );
XOR2_X1 inst_3 ( .Z(net_12), .A(nid15), .B(nid14) );
NAND2_X1 inst_156 ( .ZN(net_123), .A1(net_122), .A2(net_116) );
XOR2_X1 inst_9 ( .Z(net_19), .A(nid28), .B(nid24) );
NOR2_X1 inst_113 ( .ZN(net_105), .A1(net_93), .A2(net_92) );
INV_X1 inst_170 ( .ZN(net_112), .A(net_80) );
XNOR2_X1 inst_50 ( .ZN(net_55), .B(net_54), .A(net_49) );
NAND2_X1 inst_137 ( .ZN(net_87), .A2(net_85), .A1(net_80) );
XNOR2_X1 inst_41 ( .ZN(net_56), .A(net_32), .B(net_25) );
NAND2_X1 inst_130 ( .ZN(net_7), .A2(nr), .A1(nic2) );
XNOR2_X1 inst_91 ( .B(net_134), .ZN(nod21), .A(nid21) );
NAND2_X1 inst_132 ( .A1(net_131), .ZN(net_93), .A2(net_73) );
NAND2_X1 inst_143 ( .A1(net_112), .A2(net_105), .ZN(net_102) );
NAND2_X1 inst_152 ( .A1(net_117), .ZN(net_115), .A2(net_114) );
XNOR2_X1 inst_58 ( .ZN(net_66), .A(net_57), .B(net_6) );
XNOR2_X1 inst_36 ( .ZN(net_48), .B(net_26), .A(net_10) );
NAND2_X1 inst_147 ( .A2(net_114), .A1(net_112), .ZN(net_107) );
XNOR2_X1 inst_87 ( .B(net_118), .ZN(nod25), .A(nid25) );
XNOR2_X1 inst_61 ( .ZN(net_69), .A(net_55), .B(net_0) );
XNOR2_X1 inst_45 ( .ZN(net_46), .A(net_36), .B(net_21) );
XNOR2_X1 inst_96 ( .B(net_115), .ZN(nod17), .A(nid17) );
XNOR2_X1 inst_101 ( .B(net_125), .ZN(nod12), .A(nid12) );
XOR2_X1 inst_0 ( .Z(net_9), .A(nid23), .B(nid22) );
XOR2_X1 inst_10 ( .Z(net_20), .A(nid1), .B(nid0) );
XOR2_X1 inst_4 ( .Z(net_13), .A(nid21), .B(nid17) );
XNOR2_X1 inst_65 ( .ZN(net_128), .B(net_69), .A(net_42) );
XNOR2_X1 inst_89 ( .B(net_127), .ZN(nod23), .A(nid23) );
XNOR2_X1 inst_28 ( .ZN(net_23), .A(nid22), .B(nid18) );
NOR3_X1 inst_111 ( .ZN(net_124), .A2(net_90), .A1(net_89), .A3(net_87) );
XNOR2_X1 inst_66 ( .ZN(net_110), .B(net_68), .A(net_47) );
NOR2_X1 inst_117 ( .ZN(net_138), .A2(net_91), .A1(net_90) );
XNOR2_X1 inst_98 ( .B(net_141), .ZN(nod15), .A(nid15) );
XNOR2_X1 inst_63 ( .ZN(net_71), .A(net_62), .B(net_5) );
XOR2_X1 inst_7 ( .Z(net_16), .A(nid14), .B(nid10) );
XNOR2_X1 inst_49 ( .ZN(net_53), .A(net_52), .B(net_51) );
NAND3_X1 inst_120 ( .A1(net_139), .ZN(net_92), .A3(net_86), .A2(net_82) );
NAND2_X1 inst_154 ( .A1(net_122), .ZN(net_119), .A2(net_114) );
XOR2_X1 inst_13 ( .Z(net_25), .A(nid27), .B(nid26) );
NAND3_X1 inst_119 ( .ZN(net_84), .A1(net_83), .A2(net_82), .A3(net_77) );
XNOR2_X1 inst_75 ( .B(net_143), .ZN(nod8), .A(nid8) );
NAND2_X1 inst_166 ( .ZN(net_140), .A1(net_139), .A2(net_138) );
NOR2_X1 inst_116 ( .ZN(net_114), .A1(net_95), .A2(net_94) );
NAND2_X1 inst_163 ( .ZN(net_134), .A2(net_133), .A1(net_117) );
XNOR2_X1 inst_85 ( .B(net_111), .ZN(nod27), .A(nid27) );
XNOR2_X1 inst_54 ( .ZN(net_62), .B(net_60), .A(net_58) );
XNOR2_X1 inst_79 ( .B(net_97), .ZN(nod4), .A(nid4) );
OR2_X4 inst_109 ( .A2(net_131), .ZN(net_95), .A1(net_73) );
OR3_X4 inst_106 ( .A1(net_131), .A2(net_128), .ZN(net_78), .A3(net_74) );
NAND2_X1 inst_149 ( .A1(net_131), .A2(net_124), .ZN(net_109) );
XNOR2_X1 inst_43 ( .ZN(net_44), .B(net_16), .A(net_15) );
XNOR2_X1 inst_39 ( .ZN(net_43), .A(net_22), .B(net_13) );
NAND2_X1 inst_128 ( .ZN(net_5), .A2(nr), .A1(nic4) );
XNOR2_X1 inst_73 ( .B(net_112), .A(net_110), .ZN(net_75) );
XOR2_X1 inst_23 ( .Z(net_37), .A(nid31), .B(nid27) );
INV_X1 inst_171 ( .A(net_128), .ZN(net_73) );
XNOR2_X1 inst_77 ( .B(net_96), .ZN(nod6), .A(nid6) );
XNOR2_X1 inst_94 ( .B(net_98), .ZN(nod19), .A(nid19) );
endmodule
|
module c3_path (
nx1,
nx3,
nx2,
nx4,
nx33,
nx44,
nx12);
// Start PIs
input nx1;
input nx3;
input nx2;
input nx4;
// Start POs
output nx33;
output nx44;
output nx12;
// Start wires
wire nx1;
wire nx3;
wire nx33;
wire nx44;
wire nx12;
wire nx2;
wire nx4;
// Start cells
BUF_X1 inst_2 ( .Z(nx44), .A(nx4) );
INV_X1 inst_1 ( .ZN(nx33), .A(nx3) );
NAND2_X1 inst_0 ( .ZN(nx12), .A2(nx2), .A1(nx1) );
endmodule
|
module c1355 (
n43gat,
n190gat,
n99gat,
n78gat,
n85gat,
n232gat,
n211gat,
n226gat,
n155gat,
n176gat,
n162gat,
n64gat,
n230gat,
n92gat,
n228gat,
n127gat,
n22gat,
n1gat,
n113gat,
n183gat,
n148gat,
n29gat,
n197gat,
n134gat,
n204gat,
n218gat,
n227gat,
n8gat,
n169gat,
n225gat,
n36gat,
n57gat,
n231gat,
n106gat,
n233gat,
n50gat,
n15gat,
n71gat,
n120gat,
n229gat,
n141gat,
n1328gat,
n1348gat,
n1338gat,
n1331gat,
n1339gat,
n1344gat,
n1346gat,
n1353gat,
n1337gat,
n1333gat,
n1347gat,
n1340gat,
n1354gat,
n1351gat,
n1355gat,
n1352gat,
n1343gat,
n1329gat,
n1332gat,
n1336gat,
n1324gat,
n1335gat,
n1334gat,
n1349gat,
n1330gat,
n1327gat,
n1341gat,
n1326gat,
n1345gat,
n1342gat,
n1350gat,
n1325gat);
// Start PIs
input n43gat;
input n190gat;
input n99gat;
input n78gat;
input n85gat;
input n232gat;
input n211gat;
input n226gat;
input n155gat;
input n176gat;
input n162gat;
input n64gat;
input n230gat;
input n92gat;
input n228gat;
input n127gat;
input n22gat;
input n1gat;
input n113gat;
input n183gat;
input n148gat;
input n29gat;
input n197gat;
input n134gat;
input n204gat;
input n218gat;
input n227gat;
input n8gat;
input n169gat;
input n225gat;
input n36gat;
input n57gat;
input n231gat;
input n106gat;
input n233gat;
input n50gat;
input n15gat;
input n71gat;
input n120gat;
input n229gat;
input n141gat;
// Start POs
output n1328gat;
output n1348gat;
output n1338gat;
output n1331gat;
output n1339gat;
output n1344gat;
output n1346gat;
output n1353gat;
output n1337gat;
output n1333gat;
output n1347gat;
output n1340gat;
output n1354gat;
output n1351gat;
output n1355gat;
output n1352gat;
output n1343gat;
output n1329gat;
output n1332gat;
output n1336gat;
output n1324gat;
output n1335gat;
output n1334gat;
output n1349gat;
output n1330gat;
output n1327gat;
output n1341gat;
output n1326gat;
output n1345gat;
output n1342gat;
output n1350gat;
output n1325gat;
// Start wires
wire n43gat;
wire net_107;
wire net_47;
wire n190gat;
wire n1328gat;
wire n99gat;
wire net_61;
wire net_137;
wire n1338gat;
wire net_132;
wire net_54;
wire net_105;
wire net_62;
wire net_6;
wire n176gat;
wire net_129;
wire net_119;
wire net_98;
wire net_23;
wire net_117;
wire net_12;
wire net_74;
wire net_53;
wire net_93;
wire n1353gat;
wire net_135;
wire net_130;
wire n1347gat;
wire net_147;
wire net_127;
wire net_14;
wire n1351gat;
wire net_113;
wire net_26;
wire n204gat;
wire net_76;
wire net_101;
wire net_32;
wire net_111;
wire n1332gat;
wire n1329gat;
wire net_90;
wire net_40;
wire net_100;
wire n8gat;
wire net_85;
wire net_69;
wire n225gat;
wire net_124;
wire n57gat;
wire net_141;
wire n1330gat;
wire net_83;
wire net_115;
wire n1345gat;
wire n120gat;
wire net_4;
wire net_95;
wire net_17;
wire net_78;
wire net_27;
wire net_56;
wire net_87;
wire net_0;
wire n232gat;
wire net_35;
wire n211gat;
wire net_22;
wire net_16;
wire n64gat;
wire net_39;
wire n228gat;
wire n92gat;
wire net_144;
wire net_102;
wire net_2;
wire net_59;
wire net_9;
wire net_42;
wire n22gat;
wire net_120;
wire n1337gat;
wire net_109;
wire net_80;
wire net_65;
wire net_50;
wire n183gat;
wire n1354gat;
wire n1340gat;
wire net_96;
wire net_66;
wire net_38;
wire net_44;
wire n197gat;
wire net_136;
wire net_134;
wire net_19;
wire n1352gat;
wire net_89;
wire net_45;
wire net_126;
wire n1336gat;
wire n1324gat;
wire net_34;
wire net_108;
wire n1334gat;
wire n50gat;
wire n15gat;
wire net_63;
wire n1342gat;
wire n229gat;
wire n141gat;
wire n1348gat;
wire net_116;
wire net_30;
wire n78gat;
wire n1331gat;
wire net_91;
wire net_106;
wire net_99;
wire net_24;
wire net_55;
wire net_46;
wire net_140;
wire net_118;
wire net_104;
wire net_146;
wire net_72;
wire net_122;
wire net_25;
wire net_70;
wire net_7;
wire n1333gat;
wire n113gat;
wire net_5;
wire net_52;
wire n148gat;
wire net_128;
wire n1355gat;
wire net_138;
wire net_13;
wire n218gat;
wire net_94;
wire net_11;
wire n169gat;
wire net_18;
wire net_123;
wire n36gat;
wire n1335gat;
wire net_131;
wire net_114;
wire n1349gat;
wire n1327gat;
wire net_29;
wire n231gat;
wire net_68;
wire n1341gat;
wire net_142;
wire net_77;
wire n71gat;
wire net_20;
wire net_31;
wire n1350gat;
wire net_36;
wire net_49;
wire net_15;
wire net_57;
wire net_41;
wire net_71;
wire n85gat;
wire n226gat;
wire n155gat;
wire net_3;
wire net_84;
wire n162gat;
wire net_112;
wire net_92;
wire net_1;
wire net_103;
wire n1339gat;
wire net_139;
wire n230gat;
wire n127gat;
wire net_43;
wire n1344gat;
wire net_10;
wire n1346gat;
wire net_28;
wire net_21;
wire net_51;
wire net_79;
wire n1gat;
wire net_143;
wire net_97;
wire net_88;
wire n29gat;
wire net_145;
wire net_60;
wire n134gat;
wire net_81;
wire net_58;
wire n227gat;
wire n1343gat;
wire net_82;
wire net_67;
wire net_64;
wire net_37;
wire net_110;
wire net_121;
wire net_73;
wire net_33;
wire net_48;
wire net_86;
wire net_75;
wire net_8;
wire n1326gat;
wire n106gat;
wire n233gat;
wire net_133;
wire net_125;
wire n1325gat;
// Start cells
NAND2_X1 inst_145 ( .A1(net_112), .ZN(net_104), .A2(net_103) );
XNOR2_X1 inst_103 ( .B(net_147), .ZN(n1324gat), .A(n1gat) );
NAND3_X1 inst_125 ( .A2(net_105), .ZN(net_99), .A3(net_91), .A1(net_86) );
NAND2_X1 inst_138 ( .ZN(net_92), .A2(net_90), .A1(net_77) );
NAND2_X1 inst_159 ( .A1(net_138), .ZN(net_128), .A2(net_127) );
XOR2_X1 inst_15 ( .Z(net_28), .A(n120gat), .B(n113gat) );
NAND2_X1 inst_134 ( .A1(net_116), .ZN(net_100), .A2(net_73) );
AND2_X4 inst_179 ( .A2(net_94), .A1(net_93), .ZN(net_76) );
XNOR2_X1 inst_24 ( .ZN(net_13), .A(n92gat), .B(n85gat) );
NOR2_X1 inst_114 ( .ZN(net_103), .A2(net_95), .A1(net_94) );
XOR2_X1 inst_6 ( .Z(net_15), .A(n99gat), .B(n71gat) );
NAND2_X1 inst_131 ( .ZN(net_5), .A2(n233gat), .A1(n228gat) );
XNOR2_X1 inst_76 ( .B(net_122), .ZN(n1351gat), .A(n190gat) );
NAND2_X1 inst_160 ( .A1(net_136), .A2(net_134), .ZN(net_129) );
NAND2_X1 inst_150 ( .A2(net_115), .ZN(net_114), .A1(net_112) );
XNOR2_X1 inst_33 ( .ZN(net_40), .A(net_32), .B(net_20) );
INV_X1 inst_172 ( .A(net_145), .ZN(net_75) );
XNOR2_X1 inst_83 ( .B(net_98), .ZN(n1344gat), .A(n141gat) );
XNOR2_X1 inst_47 ( .ZN(net_47), .B(net_22), .A(net_12) );
XOR2_X1 inst_19 ( .Z(net_35), .A(n50gat), .B(n43gat) );
NAND3_X1 inst_123 ( .A1(net_118), .ZN(net_87), .A2(net_86), .A3(net_82) );
NAND3_X1 inst_121 ( .A2(net_112), .ZN(net_83), .A3(net_82), .A1(net_73) );
XOR2_X1 inst_2 ( .Z(net_10), .A(n85gat), .B(n57gat) );
XOR2_X1 inst_8 ( .Z(net_17), .A(n29gat), .B(n1gat) );
NOR2_X1 inst_118 ( .ZN(net_134), .A1(net_111), .A2(net_99) );
XNOR2_X1 inst_86 ( .B(net_104), .ZN(n1341gat), .A(n120gat) );
NAND2_X1 inst_153 ( .ZN(net_121), .A2(net_120), .A1(net_116) );
XOR2_X1 inst_20 ( .Z(net_36), .A(n204gat), .B(n176gat) );
XNOR2_X1 inst_27 ( .ZN(net_22), .A(n162gat), .B(n134gat) );
XNOR2_X1 inst_38 ( .ZN(net_60), .A(net_34), .B(net_19) );
XNOR2_X1 inst_100 ( .B(net_132), .ZN(n1327gat), .A(n22gat) );
XNOR2_X1 inst_52 ( .ZN(net_59), .B(net_58), .A(net_52) );
XNOR2_X1 inst_90 ( .B(net_128), .ZN(n1337gat), .A(n92gat) );
NAND2_X1 inst_140 ( .A2(net_115), .A1(net_105), .ZN(net_96) );
XNOR2_X1 inst_40 ( .ZN(net_44), .A(net_39), .B(net_9) );
NAND2_X1 inst_162 ( .A2(net_142), .ZN(net_132), .A1(net_131) );
NAND2_X1 inst_167 ( .ZN(net_141), .A2(net_140), .A1(net_138) );
XNOR2_X1 inst_93 ( .B(net_137), .ZN(n1334gat), .A(n71gat) );
XNOR2_X1 inst_81 ( .B(net_108), .ZN(n1346gat), .A(n155gat) );
XNOR2_X1 inst_95 ( .B(net_146), .ZN(n1332gat), .A(n57gat) );
XOR2_X1 inst_1 ( .Z(net_9), .A(n92gat), .B(n64gat) );
XNOR2_X1 inst_72 ( .B(net_119), .ZN(n1355gat), .A(n218gat) );
NAND2_X1 inst_139 ( .ZN(net_95), .A2(net_90), .A1(net_78) );
NAND2_X1 inst_155 ( .ZN(net_123), .A2(net_120), .A1(net_105) );
XNOR2_X1 inst_59 ( .ZN(net_67), .A(net_57), .B(net_3) );
NAND2_X1 inst_135 ( .A1(net_118), .ZN(net_111), .A2(net_74) );
XNOR2_X1 inst_44 ( .ZN(net_58), .B(net_21), .A(net_8) );
XNOR2_X1 inst_55 ( .ZN(net_63), .B(net_56), .A(net_54) );
INV_X1 inst_174 ( .A(net_131), .ZN(net_72) );
NOR2_X1 inst_115 ( .ZN(net_142), .A1(net_100), .A2(net_99) );
XNOR2_X1 inst_37 ( .ZN(net_43), .A(net_37), .B(net_30) );
NAND2_X1 inst_148 ( .A1(net_112), .ZN(net_109), .A2(net_107) );
NAND2_X1 inst_164 ( .A1(net_138), .ZN(net_135), .A2(net_134) );
XOR2_X1 inst_5 ( .Z(net_14), .A(n99gat), .B(n106gat) );
NAND2_X1 inst_157 ( .A1(net_136), .A2(net_127), .ZN(net_125) );
XNOR2_X1 inst_84 ( .B(net_101), .ZN(n1343gat), .A(n134gat) );
XNOR2_X1 inst_51 ( .ZN(net_57), .B(net_56), .A(net_49) );
NAND2_X1 inst_142 ( .A2(net_107), .A1(net_105), .ZN(net_98) );
XNOR2_X1 inst_80 ( .B(net_97), .ZN(n1347gat), .A(n162gat) );
INV_X1 inst_173 ( .ZN(net_112), .A(net_86) );
OR3_X4 inst_105 ( .A2(net_136), .A1(net_131), .ZN(net_89), .A3(net_79) );
XNOR2_X1 inst_68 ( .ZN(net_74), .B(net_71), .A(net_41) );
XNOR2_X1 inst_78 ( .B(net_114), .ZN(n1349gat), .A(n176gat) );
XNOR2_X1 inst_42 ( .ZN(net_54), .B(net_38), .A(net_28) );
INV_X1 inst_175 ( .ZN(net_116), .A(net_74) );
XNOR2_X1 inst_53 ( .ZN(net_61), .A(net_60), .B(net_51) );
INV_X1 inst_177 ( .ZN(net_105), .A(net_84) );
NAND2_X1 inst_133 ( .ZN(net_7), .A2(n233gat), .A1(n231gat) );
XNOR2_X1 inst_26 ( .ZN(net_21), .A(n22gat), .B(n15gat) );
NAND2_X1 inst_151 ( .ZN(net_117), .A1(net_116), .A2(net_115) );
NOR2_X1 inst_112 ( .ZN(net_115), .A1(net_94), .A2(net_92) );
XNOR2_X1 inst_64 ( .ZN(net_145), .B(net_69), .A(net_42) );
NOR2_X1 inst_107 ( .A1(net_116), .A2(net_105), .ZN(net_82) );
XNOR2_X1 inst_67 ( .ZN(net_131), .B(net_64), .A(net_40) );
NAND2_X1 inst_127 ( .ZN(net_1), .A2(n233gat), .A1(n229gat) );
XNOR2_X1 inst_70 ( .ZN(net_138), .B(net_67), .A(net_44) );
NAND2_X1 inst_129 ( .ZN(net_3), .A2(n233gat), .A1(n226gat) );
XNOR2_X1 inst_92 ( .B(net_133), .ZN(n1335gat), .A(n78gat) );
XNOR2_X1 inst_29 ( .ZN(net_30), .A(n197gat), .B(n169gat) );
XOR2_X1 inst_17 ( .Z(net_32), .A(n50gat), .B(n22gat) );
XOR2_X1 inst_11 ( .Z(net_24), .A(n218gat), .B(n211gat) );
NAND2_X1 inst_146 ( .ZN(net_106), .A1(net_105), .A2(net_103) );
XOR2_X1 inst_14 ( .Z(net_27), .A(n155gat), .B(n127gat) );
NAND3_X1 inst_122 ( .A2(net_116), .ZN(net_85), .A1(net_84), .A3(net_80) );
XNOR2_X1 inst_31 ( .ZN(net_33), .A(n176gat), .B(n169gat) );
XNOR2_X1 inst_25 ( .ZN(net_18), .A(n211gat), .B(n183gat) );
NAND2_X1 inst_126 ( .ZN(net_0), .A2(n233gat), .A1(n225gat) );
NAND2_X1 inst_158 ( .A2(net_134), .A1(net_131), .ZN(net_126) );
NAND2_X1 inst_141 ( .A1(net_118), .A2(net_107), .ZN(net_97) );
XNOR2_X1 inst_62 ( .ZN(net_70), .A(net_63), .B(net_6) );
NOR2_X1 inst_110 ( .ZN(net_79), .A1(net_78), .A2(net_77) );
XNOR2_X1 inst_74 ( .B(net_113), .ZN(n1353gat), .A(n204gat) );
XNOR2_X1 inst_57 ( .ZN(net_65), .A(net_53), .B(net_4) );
XNOR2_X1 inst_35 ( .ZN(net_42), .A(net_17), .B(net_10) );
XNOR2_X1 inst_99 ( .B(net_144), .ZN(n1328gat), .A(n29gat) );
XNOR2_X1 inst_48 ( .ZN(net_50), .A(net_49), .B(net_48) );
XNOR2_X1 inst_69 ( .ZN(net_73), .B(net_65), .A(net_47) );
XNOR2_X1 inst_46 ( .ZN(net_48), .B(net_31), .A(net_26) );
XNOR2_X1 inst_82 ( .B(net_109), .ZN(n1345gat), .A(n148gat) );
NAND2_X1 inst_136 ( .A1(net_136), .ZN(net_94), .A2(net_72) );
XNOR2_X1 inst_30 ( .ZN(net_31), .A(n148gat), .B(n141gat) );
XNOR2_X1 inst_102 ( .B(net_139), .ZN(n1325gat), .A(n8gat) );
NOR2_X1 inst_108 ( .A2(net_118), .A1(net_112), .ZN(net_80) );
NAND2_X1 inst_165 ( .A2(net_140), .ZN(net_137), .A1(net_136) );
XNOR2_X1 inst_32 ( .ZN(net_52), .A(net_35), .B(net_29) );
XOR2_X1 inst_22 ( .Z(net_38), .A(n134gat), .B(n127gat) );
NAND2_X1 inst_144 ( .A1(net_116), .A2(net_103), .ZN(net_102) );
XNOR2_X1 inst_34 ( .ZN(net_41), .A(net_27), .B(net_18) );
XOR2_X1 inst_12 ( .Z(net_25), .A(n204gat), .B(n197gat) );
XNOR2_X1 inst_56 ( .ZN(net_64), .A(net_50), .B(net_5) );
XNOR2_X1 inst_71 ( .ZN(net_84), .B(net_68), .A(net_43) );
XOR2_X1 inst_21 ( .Z(net_37), .A(n141gat), .B(n113gat) );
OR3_X4 inst_104 ( .A2(net_145), .A1(net_138), .ZN(net_88), .A3(net_76) );
XNOR2_X1 inst_60 ( .ZN(net_68), .A(net_59), .B(net_1) );
NAND2_X1 inst_169 ( .A1(net_145), .ZN(net_144), .A2(net_134) );
NAND2_X1 inst_168 ( .ZN(net_143), .A2(net_142), .A1(net_136) );
XNOR2_X1 inst_97 ( .B(net_129), .ZN(n1330gat), .A(n43gat) );
NAND2_X1 inst_161 ( .A1(net_145), .ZN(net_130), .A2(net_127) );
NAND3_X1 inst_124 ( .A1(net_112), .ZN(net_110), .A3(net_91), .A2(net_84) );
XOR2_X1 inst_18 ( .Z(net_34), .A(n64gat), .B(n57gat) );
XOR2_X1 inst_16 ( .Z(net_29), .A(n36gat), .B(n29gat) );
XNOR2_X1 inst_88 ( .B(net_124), .ZN(n1339gat), .A(n106gat) );
XOR2_X1 inst_3 ( .Z(net_11), .A(n190gat), .B(n183gat) );
NAND2_X1 inst_156 ( .A1(net_131), .A2(net_127), .ZN(net_124) );
XOR2_X1 inst_9 ( .Z(net_19), .A(n78gat), .B(n71gat) );
NOR2_X1 inst_113 ( .ZN(net_107), .A2(net_95), .A1(net_93) );
NAND2_X1 inst_170 ( .ZN(net_146), .A1(net_145), .A2(net_140) );
XNOR2_X1 inst_50 ( .ZN(net_55), .A(net_54), .B(net_48) );
NAND2_X1 inst_137 ( .ZN(net_91), .A2(net_89), .A1(net_88) );
XNOR2_X1 inst_41 ( .ZN(net_51), .A(net_14), .B(net_13) );
NAND2_X1 inst_130 ( .ZN(net_4), .A2(n233gat), .A1(n232gat) );
XNOR2_X1 inst_91 ( .B(net_130), .ZN(n1336gat), .A(n85gat) );
NAND2_X1 inst_132 ( .ZN(net_6), .A2(n233gat), .A1(n227gat) );
NAND2_X1 inst_143 ( .A1(net_118), .A2(net_103), .ZN(net_101) );
INV_X1 inst_176 ( .ZN(net_118), .A(net_73) );
NAND2_X1 inst_152 ( .A2(net_120), .ZN(net_119), .A1(net_118) );
XNOR2_X1 inst_58 ( .ZN(net_66), .A(net_61), .B(net_2) );
XNOR2_X1 inst_36 ( .ZN(net_49), .A(net_25), .B(net_24) );
NAND2_X1 inst_147 ( .A1(net_116), .ZN(net_108), .A2(net_107) );
XNOR2_X1 inst_87 ( .B(net_106), .ZN(n1340gat), .A(n113gat) );
XNOR2_X1 inst_61 ( .ZN(net_69), .A(net_55), .B(net_0) );
XNOR2_X1 inst_45 ( .ZN(net_46), .B(net_16), .A(net_15) );
XNOR2_X1 inst_96 ( .B(net_126), .ZN(n1331gat), .A(n50gat) );
XNOR2_X1 inst_101 ( .B(net_143), .ZN(n1326gat), .A(n15gat) );
XOR2_X1 inst_0 ( .Z(net_8), .A(n8gat), .B(n1gat) );
XOR2_X1 inst_10 ( .Z(net_20), .A(n78gat), .B(n106gat) );
XOR2_X1 inst_4 ( .Z(net_12), .A(n218gat), .B(n190gat) );
XNOR2_X1 inst_65 ( .ZN(net_86), .B(net_66), .A(net_45) );
AND2_X4 inst_178 ( .A1(net_138), .ZN(net_77), .A2(net_75) );
XNOR2_X1 inst_89 ( .B(net_125), .ZN(n1338gat), .A(n99gat) );
XNOR2_X1 inst_28 ( .ZN(net_23), .A(n148gat), .B(n120gat) );
NOR2_X1 inst_111 ( .ZN(net_120), .A1(net_93), .A2(net_92) );
XNOR2_X1 inst_66 ( .ZN(net_136), .B(net_70), .A(net_46) );
NOR2_X1 inst_117 ( .ZN(net_140), .A2(net_110), .A1(net_100) );
XNOR2_X1 inst_98 ( .B(net_135), .ZN(n1329gat), .A(n36gat) );
XNOR2_X1 inst_63 ( .ZN(net_71), .A(net_62), .B(net_7) );
XOR2_X1 inst_7 ( .Z(net_16), .A(n43gat), .B(n15gat) );
XNOR2_X1 inst_49 ( .ZN(net_53), .A(net_52), .B(net_51) );
NAND3_X1 inst_120 ( .A1(net_105), .ZN(net_81), .A3(net_80), .A2(net_74) );
NAND2_X1 inst_154 ( .ZN(net_122), .A1(net_118), .A2(net_115) );
XOR2_X1 inst_13 ( .Z(net_26), .A(n162gat), .B(n155gat) );
NAND4_X1 inst_119 ( .ZN(net_90), .A2(net_87), .A1(net_85), .A3(net_83), .A4(net_81) );
XNOR2_X1 inst_75 ( .B(net_123), .ZN(n1352gat), .A(n197gat) );
NAND2_X1 inst_166 ( .A2(net_142), .ZN(net_139), .A1(net_138) );
NOR2_X1 inst_116 ( .ZN(net_127), .A1(net_111), .A2(net_110) );
NAND2_X1 inst_163 ( .A2(net_140), .ZN(net_133), .A1(net_131) );
XNOR2_X1 inst_85 ( .B(net_102), .ZN(n1342gat), .A(n127gat) );
XNOR2_X1 inst_54 ( .ZN(net_62), .A(net_60), .B(net_58) );
XNOR2_X1 inst_79 ( .B(net_96), .ZN(n1348gat), .A(n169gat) );
NOR2_X1 inst_109 ( .A2(net_138), .ZN(net_78), .A1(net_75) );
OR2_X4 inst_106 ( .A2(net_136), .ZN(net_93), .A1(net_72) );
NAND2_X1 inst_149 ( .A2(net_120), .ZN(net_113), .A1(net_112) );
XNOR2_X1 inst_43 ( .ZN(net_45), .A(net_36), .B(net_23) );
XNOR2_X1 inst_39 ( .ZN(net_56), .B(net_33), .A(net_11) );
NAND2_X1 inst_128 ( .ZN(net_2), .A2(n233gat), .A1(n230gat) );
XNOR2_X1 inst_73 ( .B(net_121), .ZN(n1354gat), .A(n211gat) );
XOR2_X1 inst_23 ( .Z(net_39), .A(n8gat), .B(n36gat) );
NAND2_X1 inst_171 ( .ZN(net_147), .A1(net_145), .A2(net_142) );
XNOR2_X1 inst_77 ( .B(net_117), .ZN(n1350gat), .A(n183gat) );
XNOR2_X1 inst_94 ( .B(net_141), .ZN(n1333gat), .A(n64gat) );
endmodule
|
module c432 (
n43gat,
n17gat,
n34gat,
n27gat,
n82gat,
n99gat,
n21gat,
n66gat,
n102gat,
n47gat,
n92gat,
n14gat,
n95gat,
n105gat,
n30gat,
n1gat,
n40gat,
n37gat,
n4gat,
n112gat,
n76gat,
n56gat,
n115gat,
n53gat,
n86gat,
n69gat,
n8gat,
n79gat,
n73gat,
n11gat,
n60gat,
n50gat,
n108gat,
n63gat,
n24gat,
n89gat,
n432gat,
n430gat,
n421gat,
n370gat,
n329gat,
n223gat,
n431gat);
// Start PIs
input n43gat;
input n17gat;
input n34gat;
input n27gat;
input n82gat;
input n99gat;
input n21gat;
input n66gat;
input n102gat;
input n47gat;
input n92gat;
input n14gat;
input n95gat;
input n105gat;
input n30gat;
input n1gat;
input n40gat;
input n37gat;
input n4gat;
input n112gat;
input n76gat;
input n56gat;
input n115gat;
input n53gat;
input n86gat;
input n69gat;
input n8gat;
input n79gat;
input n73gat;
input n11gat;
input n60gat;
input n50gat;
input n108gat;
input n63gat;
input n24gat;
input n89gat;
// Start POs
output n432gat;
output n430gat;
output n421gat;
output n370gat;
output n329gat;
output n223gat;
output n431gat;
// Start wires
wire n43gat;
wire net_107;
wire net_47;
wire n34gat;
wire n82gat;
wire n99gat;
wire net_61;
wire net_54;
wire n66gat;
wire net_105;
wire net_62;
wire net_6;
wire net_119;
wire net_98;
wire net_23;
wire net_117;
wire net_12;
wire n102gat;
wire net_74;
wire net_53;
wire net_93;
wire n105gat;
wire n30gat;
wire n40gat;
wire n37gat;
wire n112gat;
wire n432gat;
wire n56gat;
wire net_14;
wire net_113;
wire net_26;
wire net_76;
wire net_101;
wire net_32;
wire net_111;
wire net_90;
wire net_40;
wire net_100;
wire n8gat;
wire net_85;
wire net_69;
wire net_124;
wire net_83;
wire net_115;
wire n63gat;
wire net_4;
wire net_95;
wire net_17;
wire net_78;
wire n17gat;
wire net_27;
wire n370gat;
wire net_56;
wire net_87;
wire net_0;
wire net_35;
wire net_22;
wire net_16;
wire net_39;
wire n92gat;
wire net_102;
wire net_2;
wire net_59;
wire n14gat;
wire net_9;
wire net_42;
wire net_120;
wire n95gat;
wire net_109;
wire net_80;
wire net_65;
wire net_50;
wire net_96;
wire net_66;
wire net_38;
wire net_44;
wire n421gat;
wire net_19;
wire n53gat;
wire net_89;
wire net_45;
wire n69gat;
wire net_126;
wire net_34;
wire n79gat;
wire net_108;
wire n50gat;
wire net_63;
wire n89gat;
wire n430gat;
wire n27gat;
wire net_116;
wire net_30;
wire net_91;
wire net_106;
wire net_99;
wire net_24;
wire net_55;
wire net_46;
wire net_118;
wire net_104;
wire n47gat;
wire net_72;
wire net_122;
wire net_25;
wire net_7;
wire net_70;
wire n4gat;
wire n431gat;
wire n76gat;
wire net_5;
wire net_52;
wire net_13;
wire net_94;
wire net_11;
wire net_18;
wire n73gat;
wire net_123;
wire n11gat;
wire net_114;
wire n60gat;
wire net_29;
wire net_68;
wire net_77;
wire net_20;
wire net_31;
wire net_36;
wire net_49;
wire net_15;
wire net_41;
wire net_57;
wire n21gat;
wire net_71;
wire net_3;
wire net_84;
wire net_112;
wire net_92;
wire net_1;
wire net_103;
wire net_43;
wire net_10;
wire net_28;
wire net_21;
wire net_51;
wire net_79;
wire n1gat;
wire net_97;
wire net_88;
wire net_60;
wire n115gat;
wire net_81;
wire net_58;
wire n86gat;
wire n329gat;
wire net_67;
wire net_82;
wire n223gat;
wire net_64;
wire net_37;
wire net_110;
wire net_121;
wire net_73;
wire net_33;
wire net_48;
wire net_86;
wire net_8;
wire net_75;
wire n108gat;
wire net_125;
wire n24gat;
// Start cells
INV_X1 inst_103 ( .ZN(net_3), .A(n79gat) );
INV_X1 inst_125 ( .A(net_113), .ZN(net_108) );
XNOR2_X1 inst_15 ( .ZN(net_81), .A(net_65), .B(n329gat) );
OR2_X4 inst_24 ( .A1(net_48), .ZN(net_26), .A2(n1gat) );
INV_X1 inst_114 ( .ZN(net_14), .A(n73gat) );
XNOR2_X1 inst_6 ( .ZN(net_45), .A(net_27), .B(n223gat) );
AND3_X4 inst_131 ( .ZN(net_55), .A3(net_44), .A2(net_6), .A1(n43gat) );
NAND2_X1 inst_76 ( .ZN(net_61), .A1(net_60), .A2(net_56) );
NOR3_X1 inst_33 ( .ZN(net_119), .A3(net_118), .A2(net_111), .A1(net_106) );
NAND2_X1 inst_83 ( .ZN(net_72), .A2(n329gat), .A1(n112gat) );
NAND4_X1 inst_47 ( .ZN(net_85), .A4(net_82), .A3(net_42), .A2(net_13), .A1(n95gat) );
OR3_X4 inst_19 ( .A2(net_30), .A3(net_29), .A1(net_28), .ZN(n223gat) );
INV_X1 inst_123 ( .A(net_116), .ZN(net_106) );
INV_X1 inst_121 ( .ZN(net_21), .A(net_20) );
XNOR2_X1 inst_2 ( .ZN(net_44), .A(net_24), .B(n223gat) );
XNOR2_X1 inst_8 ( .ZN(net_49), .A(net_19), .B(n223gat) );
INV_X1 inst_118 ( .ZN(net_16), .A(n115gat) );
NAND2_X1 inst_86 ( .ZN(net_95), .A2(n370gat), .A1(n115gat) );
OR3_X4 inst_20 ( .ZN(net_60), .A1(net_46), .A3(net_45), .A2(n21gat) );
NOR4_X1 inst_27 ( .ZN(net_64), .A1(net_63), .A3(net_62), .A2(net_61), .A4(net_52) );
NOR2_X1 inst_38 ( .ZN(net_29), .A1(net_11), .A2(n102gat) );
INV_X1 inst_100 ( .ZN(net_0), .A(n69gat) );
NAND4_X1 inst_52 ( .ZN(net_90), .A4(net_78), .A3(net_49), .A2(net_4), .A1(n30gat) );
NAND2_X1 inst_90 ( .ZN(net_99), .A2(n370gat), .A1(n14gat) );
NOR2_X1 inst_40 ( .A1(net_51), .ZN(net_20), .A2(n76gat) );
NAND2_X1 inst_93 ( .ZN(net_102), .A2(n370gat), .A1(n40gat) );
NAND2_X1 inst_81 ( .ZN(net_70), .A2(n329gat), .A1(n34gat) );
NAND2_X1 inst_95 ( .ZN(net_112), .A1(net_111), .A2(net_105) );
XNOR2_X1 inst_1 ( .ZN(net_42), .A(net_30), .B(n223gat) );
NAND2_X1 inst_72 ( .ZN(net_36), .A2(n223gat), .A1(n50gat) );
NAND4_X1 inst_59 ( .ZN(net_114), .A1(net_101), .A4(net_69), .A3(net_32), .A2(n43gat) );
NOR2_X1 inst_44 ( .ZN(net_123), .A2(net_114), .A1(net_108) );
NAND4_X1 inst_55 ( .ZN(net_116), .A1(net_98), .A4(net_66), .A3(net_33), .A2(n82gat) );
INV_X1 inst_115 ( .ZN(net_15), .A(n53gat) );
NOR2_X1 inst_37 ( .ZN(net_30), .A1(net_1), .A2(n89gat) );
XNOR2_X1 inst_5 ( .ZN(net_50), .A(net_21), .B(n223gat) );
NAND2_X1 inst_84 ( .ZN(net_73), .A2(n329gat), .A1(n99gat) );
NAND4_X1 inst_51 ( .ZN(net_89), .A4(net_77), .A3(net_41), .A2(net_9), .A1(n56gat) );
NAND2_X1 inst_80 ( .ZN(net_69), .A2(n329gat), .A1(n47gat) );
INV_X1 inst_105 ( .ZN(net_5), .A(n112gat) );
NAND2_X1 inst_68 ( .ZN(net_32), .A2(n223gat), .A1(n37gat) );
NAND2_X1 inst_78 ( .ZN(net_67), .A2(n329gat), .A1(n8gat) );
NOR2_X1 inst_42 ( .ZN(net_56), .A1(net_55), .A2(net_54) );
NAND4_X1 inst_53 ( .A4(net_94), .A1(net_87), .A2(net_86), .A3(net_85), .ZN(n370gat) );
AND2_X2 inst_133 ( .A1(net_125), .A2(net_104), .ZN(n421gat) );
NOR4_X1 inst_26 ( .ZN(net_25), .A1(net_24), .A2(net_23), .A3(net_22), .A4(net_20) );
INV_X1 inst_112 ( .ZN(net_12), .A(n60gat) );
NAND3_X1 inst_64 ( .ZN(net_93), .A1(net_90), .A2(net_89), .A3(net_88) );
INV_X1 inst_107 ( .ZN(net_7), .A(n43gat) );
NAND2_X1 inst_67 ( .ZN(net_31), .A2(n223gat), .A1(n1gat) );
AND3_X4 inst_127 ( .ZN(net_63), .A3(net_40), .A2(net_14), .A1(n69gat) );
NAND2_X1 inst_70 ( .ZN(net_34), .A2(n223gat), .A1(n11gat) );
AND3_X4 inst_129 ( .ZN(net_58), .A3(net_42), .A2(net_2), .A1(n95gat) );
NAND2_X1 inst_92 ( .ZN(net_101), .A2(n370gat), .A1(n53gat) );
NOR4_X1 inst_29 ( .ZN(net_91), .A4(net_79), .A1(net_48), .A3(net_47), .A2(n14gat) );
XNOR2_X1 inst_17 ( .ZN(net_83), .A(net_63), .B(n329gat) );
XNOR2_X1 inst_11 ( .ZN(net_77), .A(net_54), .B(n329gat) );
XNOR2_X1 inst_14 ( .ZN(net_80), .A(net_60), .B(n329gat) );
INV_X1 inst_122 ( .ZN(net_53), .A(net_52) );
NOR4_X1 inst_31 ( .ZN(net_94), .A2(net_93), .A3(net_92), .A4(net_91), .A1(net_84) );
OR2_X4 inst_25 ( .A1(net_46), .ZN(net_27), .A2(n11gat) );
INV_X1 inst_126 ( .ZN(net_110), .A(net_109) );
NAND4_X1 inst_62 ( .ZN(net_105), .A1(net_95), .A4(net_72), .A3(net_35), .A2(n108gat) );
INV_X1 inst_110 ( .ZN(net_10), .A(n24gat) );
NAND2_X1 inst_74 ( .ZN(net_38), .A2(n223gat), .A1(n89gat) );
NAND4_X1 inst_57 ( .ZN(net_107), .A1(net_100), .A4(net_68), .A3(net_36), .A2(n56gat) );
NOR3_X1 inst_35 ( .A2(net_124), .ZN(net_122), .A3(net_115), .A1(net_112) );
INV_X1 inst_99 ( .ZN(net_46), .A(n17gat) );
NAND4_X1 inst_48 ( .ZN(net_86), .A4(net_75), .A3(net_43), .A2(net_16), .A1(n108gat) );
NAND2_X1 inst_69 ( .ZN(net_33), .A2(n223gat), .A1(n76gat) );
NAND4_X1 inst_46 ( .ZN(net_28), .A1(net_27), .A3(net_26), .A4(net_25), .A2(net_18) );
NAND2_X1 inst_82 ( .ZN(net_71), .A2(n329gat), .A1(n21gat) );
NOR4_X1 inst_30 ( .ZN(net_92), .A4(net_80), .A1(net_46), .A3(net_45), .A2(n27gat) );
INV_X1 inst_102 ( .ZN(net_2), .A(n99gat) );
INV_X1 inst_108 ( .ZN(net_8), .A(n56gat) );
NOR3_X1 inst_32 ( .ZN(net_52), .A1(net_48), .A3(net_47), .A2(n8gat) );
OR3_X2 inst_22 ( .A2(net_124), .A3(net_123), .A1(net_120), .ZN(n430gat) );
NOR3_X1 inst_34 ( .ZN(net_126), .A1(net_121), .A2(net_120), .A3(net_118) );
XNOR2_X1 inst_12 ( .ZN(net_78), .A(net_62), .B(n329gat) );
NAND4_X1 inst_56 ( .ZN(net_104), .A1(net_99), .A4(net_67), .A3(net_31), .A2(n4gat) );
NAND2_X1 inst_71 ( .ZN(net_35), .A2(n223gat), .A1(n102gat) );
OR3_X4 inst_21 ( .ZN(net_65), .A1(net_51), .A3(net_50), .A2(n86gat) );
INV_X1 inst_104 ( .ZN(net_4), .A(n40gat) );
NAND4_X1 inst_60 ( .ZN(net_113), .A1(net_102), .A4(net_70), .A3(net_39), .A2(n30gat) );
NAND2_X1 inst_97 ( .ZN(net_115), .A1(net_114), .A2(net_107) );
INV_X1 inst_124 ( .ZN(net_120), .A(net_107) );
OR4_X1 inst_18 ( .A1(net_126), .A4(net_123), .A2(net_119), .A3(net_110), .ZN(n432gat) );
XNOR2_X1 inst_16 ( .ZN(net_82), .A(net_58), .B(n329gat) );
NAND2_X1 inst_88 ( .ZN(net_97), .A2(n370gat), .A1(n79gat) );
XNOR2_X1 inst_3 ( .ZN(net_41), .A(net_23), .B(n223gat) );
XNOR2_X1 inst_9 ( .ZN(net_75), .A(net_57), .B(n329gat) );
INV_X1 inst_113 ( .ZN(net_13), .A(n105gat) );
NAND4_X1 inst_50 ( .ZN(net_88), .A4(net_76), .A3(net_44), .A2(net_15), .A1(n43gat) );
NOR2_X1 inst_41 ( .ZN(net_24), .A1(net_7), .A2(n37gat) );
AND3_X4 inst_130 ( .ZN(net_57), .A3(net_43), .A2(net_5), .A1(n108gat) );
NAND2_X1 inst_91 ( .ZN(net_100), .A2(n370gat), .A1(n66gat) );
AND3_X4 inst_132 ( .ZN(net_62), .A3(net_49), .A2(net_17), .A1(n30gat) );
NAND4_X1 inst_58 ( .ZN(net_121), .A1(net_97), .A4(net_74), .A3(net_37), .A2(n69gat) );
NOR2_X1 inst_36 ( .ZN(net_22), .A1(net_0), .A2(n63gat) );
NAND2_X1 inst_87 ( .ZN(net_96), .A2(n370gat), .A1(n105gat) );
NAND4_X1 inst_61 ( .ZN(net_109), .A1(net_103), .A4(net_71), .A3(net_34), .A2(n17gat) );
NOR2_X1 inst_45 ( .ZN(net_117), .A1(net_116), .A2(net_115) );
NAND2_X1 inst_96 ( .ZN(net_118), .A2(net_114), .A1(net_113) );
INV_X1 inst_101 ( .ZN(net_1), .A(n95gat) );
XNOR2_X1 inst_0 ( .ZN(net_40), .A(net_22), .B(n223gat) );
XNOR2_X1 inst_10 ( .ZN(net_76), .A(net_55), .B(n329gat) );
XNOR2_X1 inst_4 ( .ZN(net_43), .A(net_29), .B(n223gat) );
NAND3_X1 inst_65 ( .ZN(net_125), .A3(net_122), .A2(net_121), .A1(net_116) );
NAND2_X1 inst_89 ( .ZN(net_98), .A2(n370gat), .A1(n92gat) );
NOR4_X1 inst_28 ( .ZN(net_84), .A4(net_81), .A1(net_51), .A3(net_50), .A2(n92gat) );
INV_X1 inst_111 ( .ZN(net_11), .A(n108gat) );
NAND2_X1 inst_66 ( .ZN(net_18), .A2(net_10), .A1(n30gat) );
INV_X1 inst_117 ( .ZN(net_48), .A(n4gat) );
NAND2_X1 inst_98 ( .ZN(net_124), .A2(net_113), .A1(net_109) );
NAND3_X2 inst_63 ( .A2(net_65), .A1(net_64), .A3(net_59), .ZN(n329gat) );
XNOR2_X1 inst_7 ( .ZN(net_47), .A(net_26), .B(n223gat) );
NAND4_X1 inst_49 ( .ZN(net_87), .A4(net_83), .A3(net_40), .A2(net_3), .A1(n69gat) );
INV_X1 inst_120 ( .ZN(net_19), .A(net_18) );
XNOR2_X1 inst_13 ( .ZN(net_79), .A(net_53), .B(n329gat) );
INV_X1 inst_119 ( .ZN(net_17), .A(n34gat) );
NAND2_X1 inst_75 ( .ZN(net_39), .A2(n223gat), .A1(n24gat) );
INV_X1 inst_116 ( .ZN(net_51), .A(n82gat) );
NAND2_X1 inst_85 ( .ZN(net_74), .A2(n329gat), .A1(n73gat) );
NAND4_X1 inst_54 ( .ZN(net_111), .A1(net_96), .A4(net_73), .A3(net_38), .A2(n95gat) );
NAND2_X1 inst_79 ( .ZN(net_68), .A2(n329gat), .A1(n60gat) );
INV_X1 inst_109 ( .ZN(net_9), .A(n66gat) );
INV_X1 inst_106 ( .ZN(net_6), .A(n47gat) );
NOR2_X1 inst_43 ( .ZN(net_59), .A1(net_58), .A2(net_57) );
NOR2_X1 inst_39 ( .ZN(net_23), .A1(net_8), .A2(n50gat) );
AND3_X4 inst_128 ( .ZN(net_54), .A3(net_41), .A2(net_12), .A1(n56gat) );
NAND2_X1 inst_73 ( .ZN(net_37), .A2(n223gat), .A1(n63gat) );
OR3_X2 inst_23 ( .A3(net_126), .A2(net_124), .A1(net_117), .ZN(n431gat) );
NAND2_X1 inst_77 ( .ZN(net_66), .A2(n329gat), .A1(n86gat) );
NAND2_X1 inst_94 ( .ZN(net_103), .A2(n370gat), .A1(n27gat) );
endmodule
|
module s400 (
TEST,
FM,
blif_clk_net,
CLR,
blif_reset_net,
YLW1,
RED2,
GRN1,
RED1,
YLW2,
GRN2);
// Start PIs
input TEST;
input FM;
input blif_clk_net;
input CLR;
input blif_reset_net;
// Start POs
output YLW1;
output RED2;
output GRN1;
output RED1;
output YLW2;
output GRN2;
// Start wires
wire net_166;
wire net_107;
wire net_47;
wire net_179;
wire GRN1;
wire net_176;
wire net_159;
wire net_61;
wire net_137;
wire net_132;
wire net_54;
wire net_105;
wire net_62;
wire net_6;
wire net_129;
wire net_119;
wire net_98;
wire net_23;
wire net_117;
wire net_12;
wire net_151;
wire net_74;
wire net_53;
wire net_93;
wire net_210;
wire net_205;
wire net_168;
wire net_135;
wire net_130;
wire net_147;
wire net_127;
wire net_14;
wire net_113;
wire net_26;
wire net_76;
wire blif_clk_net;
wire net_101;
wire net_32;
wire net_187;
wire net_111;
wire net_90;
wire net_40;
wire net_100;
wire net_85;
wire net_69;
wire net_124;
wire net_161;
wire CLR;
wire net_141;
wire net_160;
wire net_83;
wire net_115;
wire RED1;
wire net_4;
wire net_95;
wire net_17;
wire net_173;
wire net_78;
wire net_27;
wire net_164;
wire net_56;
wire net_87;
wire net_0;
wire net_155;
wire net_35;
wire net_191;
wire net_16;
wire net_22;
wire net_181;
wire net_193;
wire net_39;
wire net_157;
wire net_144;
wire net_102;
wire net_2;
wire net_59;
wire net_9;
wire net_42;
wire net_120;
wire net_201;
wire net_109;
wire net_80;
wire net_65;
wire blif_reset_net;
wire net_50;
wire net_162;
wire YLW1;
wire FM;
wire net_96;
wire net_66;
wire net_38;
wire net_44;
wire net_167;
wire net_207;
wire net_199;
wire net_136;
wire net_134;
wire net_19;
wire net_89;
wire net_45;
wire net_126;
wire net_185;
wire net_34;
wire net_108;
wire net_183;
wire TEST;
wire net_178;
wire net_208;
wire net_150;
wire net_63;
wire net_212;
wire net_152;
wire net_30;
wire net_116;
wire net_189;
wire net_175;
wire net_91;
wire net_24;
wire net_55;
wire net_99;
wire net_106;
wire net_186;
wire net_46;
wire net_140;
wire net_118;
wire net_148;
wire net_104;
wire net_146;
wire net_72;
wire net_122;
wire net_25;
wire net_7;
wire net_70;
wire net_194;
wire net_172;
wire net_5;
wire net_52;
wire net_165;
wire net_128;
wire net_138;
wire net_13;
wire net_184;
wire net_94;
wire net_11;
wire net_18;
wire net_123;
wire net_131;
wire net_114;
wire net_196;
wire net_170;
wire net_29;
wire net_68;
wire net_214;
wire net_149;
wire net_142;
wire net_77;
wire net_20;
wire net_31;
wire net_36;
wire net_49;
wire net_158;
wire net_15;
wire net_41;
wire net_57;
wire net_198;
wire net_71;
wire net_209;
wire net_153;
wire net_156;
wire net_3;
wire net_84;
wire net_174;
wire net_154;
wire net_1;
wire net_92;
wire net_112;
wire net_103;
wire net_213;
wire net_139;
wire net_43;
wire YLW2;
wire net_10;
wire net_180;
wire net_28;
wire net_169;
wire net_21;
wire net_51;
wire net_171;
wire net_79;
wire net_143;
wire net_97;
wire net_190;
wire net_88;
wire net_182;
wire net_192;
wire net_145;
wire net_60;
wire net_197;
wire net_204;
wire net_81;
wire RED2;
wire net_163;
wire net_58;
wire GRN2;
wire net_67;
wire net_82;
wire net_64;
wire net_202;
wire net_37;
wire net_188;
wire net_110;
wire net_121;
wire net_73;
wire net_200;
wire net_48;
wire net_33;
wire net_177;
wire net_8;
wire net_75;
wire net_86;
wire net_211;
wire net_133;
wire net_206;
wire net_203;
wire net_195;
wire net_125;
// Start cells
AND4_X4 inst_145 ( .ZN(net_86), .A1(net_80), .A4(net_73), .A2(net_47), .A3(net_37) );
INV_X2 inst_103 ( .A(net_136), .ZN(net_135) );
DFFR_X2 inst_125 ( .RN(net_118), .D(net_43), .QN(net_6), .CK(net_209) );
CLKBUF_X2 inst_207 ( .A(net_172), .Z(net_201) );
DFFR_X1 inst_138 ( .RN(net_118), .D(net_97), .QN(RED2), .CK(net_177) );
CLKBUF_X2 inst_159 ( .A(net_152), .Z(net_153) );
CLKBUF_X2 inst_218 ( .A(net_211), .Z(net_212) );
NOR3_X2 inst_15 ( .A1(net_132), .A2(net_112), .ZN(net_75), .A3(net_54) );
CLKBUF_X2 inst_197 ( .A(net_190), .Z(net_191) );
DFFR_X1 inst_134 ( .RN(net_118), .D(net_72), .Q(YLW2), .CK(net_200) );
CLKBUF_X2 inst_179 ( .A(net_172), .Z(net_173) );
NOR2_X4 inst_24 ( .A1(net_130), .ZN(net_100), .A2(net_29) );
INV_X2 inst_114 ( .ZN(net_15), .A(net_10) );
XNOR2_X1 inst_6 ( .ZN(net_101), .A(net_100), .B(net_99) );
CLKBUF_X2 inst_194 ( .A(net_187), .Z(net_188) );
DFFR_X2 inst_131 ( .RN(net_118), .D(net_103), .QN(net_12), .CK(net_173) );
NAND2_X2 inst_76 ( .A1(net_141), .ZN(net_110), .A2(net_109) );
CLKBUF_X2 inst_214 ( .A(net_207), .Z(net_208) );
CLKBUF_X2 inst_180 ( .A(net_145), .Z(net_174) );
CLKBUF_X2 inst_160 ( .A(net_153), .Z(net_154) );
CLKBUF_X2 inst_150 ( .A(blif_clk_net), .Z(net_144) );
NOR2_X2 inst_33 ( .A1(net_126), .A2(net_76), .ZN(net_69) );
CLKBUF_X2 inst_172 ( .A(net_165), .Z(net_166) );
INV_X4 inst_83 ( .ZN(net_16), .A(net_0) );
NAND3_X2 inst_47 ( .ZN(net_102), .A1(net_100), .A2(net_99), .A3(net_66) );
NOR3_X2 inst_19 ( .ZN(net_105), .A3(net_104), .A1(net_90), .A2(net_83) );
INV_X1 inst_123 ( .ZN(net_118), .A(blif_reset_net) );
INV_X2 inst_121 ( .A(net_100), .ZN(net_93) );
XNOR2_X2 inst_2 ( .ZN(net_54), .A(net_53), .B(net_40) );
OR3_X2 inst_8 ( .A2(net_66), .ZN(net_50), .A1(net_49), .A3(net_48) );
INV_X2 inst_118 ( .ZN(net_33), .A(net_32) );
INV_X4 inst_86 ( .ZN(net_29), .A(net_16) );
CLKBUF_X2 inst_153 ( .A(net_145), .Z(net_147) );
NOR3_X2 inst_20 ( .ZN(net_106), .A3(net_104), .A1(net_94), .A2(net_89) );
NOR2_X2 inst_27 ( .ZN(net_80), .A1(net_2), .A2(CLR) );
NOR2_X2 inst_38 ( .A2(net_129), .ZN(net_92), .A1(net_56) );
INV_X4 inst_100 ( .ZN(net_112), .A(net_109) );
NAND2_X4 inst_52 ( .ZN(net_136), .A1(net_131), .A2(net_70) );
INV_X4 inst_90 ( .ZN(net_58), .A(net_19) );
DFFR_X1 inst_140 ( .RN(net_118), .D(net_107), .QN(net_9), .CK(net_160) );
CLKBUF_X2 inst_209 ( .A(net_202), .Z(net_203) );
CLKBUF_X2 inst_211 ( .A(net_189), .Z(net_205) );
NOR2_X1 inst_40 ( .A2(net_90), .ZN(net_89), .A1(net_88) );
CLKBUF_X2 inst_162 ( .A(net_155), .Z(net_156) );
CLKBUF_X2 inst_167 ( .A(net_155), .Z(net_161) );
INV_X4 inst_93 ( .ZN(net_99), .A(net_1) );
INV_X4 inst_81 ( .ZN(net_70), .A(net_12) );
INV_X4 inst_95 ( .A(net_57), .ZN(net_45) );
XNOR2_X2 inst_1 ( .A(net_51), .ZN(net_30), .B(FM) );
NAND2_X2 inst_72 ( .A2(net_128), .ZN(net_104), .A1(net_45) );
DFFR_X1 inst_139 ( .RN(net_118), .D(net_96), .QN(YLW1), .CK(net_146) );
CLKBUF_X2 inst_155 ( .A(net_148), .Z(net_149) );
NAND2_X2 inst_59 ( .ZN(net_48), .A1(net_16), .A2(net_1) );
DFFR_X1 inst_135 ( .RN(net_118), .D(net_79), .Q(RED1), .CK(net_193) );
CLKBUF_X2 inst_196 ( .A(net_189), .Z(net_190) );
NAND3_X2 inst_44 ( .A3(net_80), .A2(net_58), .A1(net_51), .ZN(net_41) );
NAND2_X4 inst_55 ( .A1(net_125), .ZN(net_98), .A2(net_28) );
CLKBUF_X2 inst_174 ( .A(net_167), .Z(net_168) );
INV_X2 inst_115 ( .ZN(net_88), .A(net_10) );
NOR2_X2 inst_37 ( .A1(net_130), .ZN(net_125), .A2(net_1) );
CLKBUF_X2 inst_210 ( .A(net_203), .Z(net_204) );
AND2_X2 inst_148 ( .ZN(net_53), .A2(net_34), .A1(net_26) );
CLKBUF_X2 inst_164 ( .A(net_157), .Z(net_158) );
CLKBUF_X2 inst_191 ( .A(net_184), .Z(net_185) );
XNOR2_X2 inst_5 ( .ZN(net_108), .A(net_102), .B(net_58) );
CLKBUF_X2 inst_157 ( .A(net_150), .Z(net_151) );
INV_X4 inst_84 ( .ZN(net_66), .A(net_2) );
NAND2_X4 inst_51 ( .A2(net_140), .ZN(net_137), .A1(net_131) );
DFFR_X1 inst_142 ( .RN(net_118), .D(net_114), .QN(net_0), .CK(net_154) );
INV_X4 inst_80 ( .ZN(net_49), .A(net_5) );
CLKBUF_X2 inst_173 ( .A(net_166), .Z(net_167) );
INV_X2 inst_105 ( .A(net_133), .ZN(net_132) );
CLKBUF_X2 inst_213 ( .A(net_206), .Z(net_207) );
NAND2_X2 inst_68 ( .ZN(net_84), .A1(net_81), .A2(net_67) );
CLKBUF_X2 inst_216 ( .A(net_195), .Z(net_210) );
INV_X4 inst_78 ( .ZN(net_87), .A(net_9) );
NAND4_X2 inst_42 ( .A1(net_66), .ZN(net_63), .A4(net_62), .A2(net_51), .A3(net_17) );
CLKBUF_X2 inst_175 ( .A(net_168), .Z(net_169) );
NAND2_X4 inst_53 ( .A2(net_137), .A1(net_136), .ZN(net_119) );
CLKBUF_X2 inst_205 ( .A(net_156), .Z(net_199) );
CLKBUF_X2 inst_177 ( .A(net_170), .Z(net_171) );
CLKBUF_X2 inst_183 ( .A(net_176), .Z(net_177) );
DFFR_X2 inst_133 ( .RN(net_118), .D(net_106), .QN(net_10), .CK(net_164) );
NOR2_X2 inst_26 ( .ZN(net_81), .A1(net_5), .A2(CLR) );
CLKBUF_X2 inst_151 ( .A(net_144), .Z(net_145) );
INV_X2 inst_112 ( .ZN(net_13), .A(net_11) );
NAND2_X2 inst_64 ( .ZN(net_55), .A2(net_41), .A1(net_39) );
INV_X2 inst_107 ( .A(net_129), .ZN(net_128) );
NAND2_X2 inst_67 ( .ZN(net_73), .A2(net_65), .A1(net_49) );
CLKBUF_X2 inst_181 ( .A(net_165), .Z(net_175) );
DFFR_X2 inst_127 ( .RN(net_118), .D(net_78), .QN(net_8), .CK(net_198) );
NAND2_X2 inst_70 ( .ZN(net_91), .A2(net_84), .A1(net_63) );
CLKBUF_X2 inst_186 ( .A(net_179), .Z(net_180) );
DFFR_X2 inst_129 ( .QN(net_124), .RN(net_118), .D(net_77), .CK(net_196) );
INV_X4 inst_92 ( .A(net_29), .ZN(net_28) );
NOR2_X2 inst_29 ( .A2(net_34), .ZN(net_27), .A1(net_26) );
CLKBUF_X2 inst_189 ( .A(net_182), .Z(net_183) );
NOR3_X2 inst_17 ( .ZN(net_78), .A3(net_76), .A1(net_53), .A2(net_27) );
NOR3_X2 inst_11 ( .ZN(net_64), .A1(net_51), .A3(net_48), .A2(net_19) );
AND3_X2 inst_146 ( .A3(net_122), .ZN(net_114), .A1(net_111), .A2(net_109) );
CLKBUF_X2 inst_188 ( .A(net_167), .Z(net_182) );
NOR3_X2 inst_14 ( .ZN(net_72), .A3(net_60), .A1(net_33), .A2(net_21) );
CLKBUF_X2 inst_202 ( .A(net_195), .Z(net_196) );
CLKBUF_X2 inst_206 ( .A(net_199), .Z(net_200) );
CLKBUF_X2 inst_187 ( .A(net_180), .Z(net_181) );
INV_X1 inst_122 ( .ZN(net_26), .A(net_8) );
NOR2_X2 inst_31 ( .ZN(net_44), .A1(net_42), .A2(net_30) );
NOR2_X2 inst_25 ( .A2(net_127), .A1(net_124), .ZN(net_34) );
DFFR_X2 inst_126 ( .QN(net_127), .RN(net_118), .D(net_69), .CK(net_204) );
CLKBUF_X2 inst_158 ( .A(net_150), .Z(net_152) );
DFFR_X1 inst_141 ( .RN(net_118), .D(net_117), .QN(net_1), .CK(net_156) );
NAND2_X2 inst_62 ( .A2(net_133), .ZN(net_76), .A1(net_45) );
CLKBUF_X2 inst_200 ( .A(net_174), .Z(net_194) );
INV_X2 inst_110 ( .ZN(net_139), .A(net_125) );
NAND2_X2 inst_74 ( .ZN(net_96), .A1(net_95), .A2(net_85) );
NAND2_X2 inst_57 ( .ZN(net_140), .A2(net_11), .A1(net_10) );
NOR2_X2 inst_35 ( .A1(net_136), .ZN(net_90), .A2(net_11) );
INV_X4 inst_99 ( .A(net_66), .ZN(net_31) );
NAND3_X2 inst_48 ( .A2(net_139), .A1(net_138), .ZN(net_121), .A3(net_93) );
NAND2_X2 inst_69 ( .ZN(net_85), .A1(net_84), .A2(net_68) );
NAND3_X2 inst_46 ( .A2(net_109), .ZN(net_79), .A1(net_50), .A3(net_46) );
INV_X4 inst_82 ( .ZN(net_17), .A(CLR) );
DFFR_X1 inst_136 ( .RN(net_118), .D(net_82), .Q(GRN2), .CK(net_191) );
NOR2_X2 inst_30 ( .ZN(net_43), .A1(net_42), .A2(net_22) );
INV_X4 inst_102 ( .ZN(net_115), .A(net_111) );
INV_X2 inst_108 ( .ZN(net_143), .A(net_128) );
CLKBUF_X2 inst_165 ( .A(net_158), .Z(net_159) );
NOR2_X2 inst_32 ( .ZN(net_61), .A2(net_60), .A1(net_57) );
NOR3_X2 inst_22 ( .A1(net_115), .ZN(net_113), .A2(net_112), .A3(net_108) );
DFFR_X1 inst_144 ( .RN(net_118), .D(net_113), .QN(net_3), .CK(net_174) );
NOR2_X2 inst_34 ( .A2(net_131), .ZN(net_71), .A1(net_70) );
NOR3_X2 inst_12 ( .A2(net_58), .ZN(net_52), .A3(net_38), .A1(net_18) );
CLKBUF_X2 inst_195 ( .A(net_188), .Z(net_189) );
NAND2_X4 inst_56 ( .A1(net_121), .ZN(net_111), .A2(net_36) );
NAND2_X2 inst_71 ( .ZN(net_95), .A2(net_91), .A1(net_88) );
NOR3_X2 inst_21 ( .A3(net_143), .A1(net_142), .A2(net_112), .ZN(net_107) );
INV_X2 inst_104 ( .A(net_136), .ZN(net_134) );
NAND2_X2 inst_60 ( .A1(net_51), .ZN(net_37), .A2(net_36) );
CLKBUF_X2 inst_215 ( .A(net_208), .Z(net_209) );
CLKBUF_X2 inst_169 ( .A(net_162), .Z(net_163) );
CLKBUF_X2 inst_168 ( .A(net_161), .Z(net_162) );
INV_X4 inst_97 ( .ZN(net_35), .A(net_28) );
CLKBUF_X2 inst_161 ( .A(net_144), .Z(net_155) );
DFFR_X2 inst_124 ( .RN(net_118), .D(net_44), .QN(net_4), .CK(net_214) );
NOR3_X2 inst_18 ( .A1(net_134), .A3(net_104), .ZN(net_103), .A2(net_71) );
NOR3_X2 inst_16 ( .ZN(net_77), .A3(net_76), .A1(net_34), .A2(net_24) );
CLKBUF_X2 inst_208 ( .A(net_201), .Z(net_202) );
INV_X4 inst_88 ( .ZN(net_18), .A(net_17) );
CLKBUF_X2 inst_220 ( .A(net_213), .Z(net_214) );
XNOR2_X2 inst_3 ( .ZN(net_142), .A(net_94), .B(net_87) );
CLKBUF_X2 inst_156 ( .A(net_149), .Z(net_150) );
OR2_X4 inst_9 ( .ZN(net_60), .A1(net_35), .A2(net_1) );
INV_X2 inst_113 ( .ZN(net_14), .A(CLR) );
CLKBUF_X2 inst_170 ( .A(net_163), .Z(net_164) );
CLKBUF_X2 inst_198 ( .A(net_158), .Z(net_192) );
NAND2_X4 inst_50 ( .A1(net_133), .ZN(net_131), .A2(net_6) );
DFFR_X1 inst_137 ( .RN(net_118), .D(net_86), .Q(GRN1), .CK(net_181) );
CLKBUF_X2 inst_199 ( .A(net_192), .Z(net_193) );
NOR2_X1 inst_41 ( .ZN(net_122), .A2(net_100), .A1(net_92) );
DFFR_X2 inst_130 ( .RN(net_118), .D(net_91), .QN(net_5), .CK(net_186) );
INV_X4 inst_91 ( .A(net_58), .ZN(net_36) );
DFFR_X2 inst_132 ( .RN(net_118), .D(net_105), .QN(net_11), .CK(net_169) );
DFFR_X1 inst_143 ( .RN(net_118), .D(net_116), .QN(net_2), .CK(net_151) );
CLKBUF_X2 inst_176 ( .A(net_146), .Z(net_170) );
CLKBUF_X2 inst_152 ( .A(net_145), .Z(net_146) );
NAND2_X2 inst_58 ( .ZN(net_38), .A1(net_29), .A2(net_1) );
NOR2_X2 inst_36 ( .A2(net_135), .ZN(net_83), .A1(net_13) );
AND2_X4 inst_147 ( .ZN(net_32), .A2(net_14), .A1(net_2) );
INV_X4 inst_87 ( .ZN(net_57), .A(net_17) );
NAND2_X2 inst_61 ( .ZN(net_39), .A2(net_32), .A1(net_23) );
CLKBUF_X2 inst_203 ( .A(net_179), .Z(net_197) );
NAND3_X2 inst_45 ( .ZN(net_46), .A3(net_31), .A1(net_25), .A2(net_20) );
INV_X4 inst_96 ( .A(net_36), .ZN(net_25) );
CLKBUF_X2 inst_212 ( .A(net_205), .Z(net_206) );
INV_X4 inst_101 ( .ZN(net_62), .A(net_38) );
XOR2_X2 inst_0 ( .Z(net_22), .B(net_6), .A(TEST) );
CLKBUF_X2 inst_184 ( .A(net_174), .Z(net_178) );
NOR4_X2 inst_10 ( .ZN(net_82), .A1(net_81), .A3(net_80), .A2(net_61), .A4(net_59) );
XNOR2_X2 inst_4 ( .ZN(net_141), .A(net_98), .B(net_66) );
NAND2_X2 inst_65 ( .ZN(net_67), .A1(net_66), .A2(net_64) );
CLKBUF_X2 inst_178 ( .A(net_171), .Z(net_172) );
INV_X4 inst_89 ( .A(net_49), .ZN(net_20) );
NOR2_X2 inst_28 ( .A2(net_126), .A1(net_123), .ZN(net_24) );
INV_X2 inst_111 ( .A(net_124), .ZN(net_123) );
NAND2_X2 inst_66 ( .ZN(net_68), .A1(net_62), .A2(net_55) );
INV_X2 inst_117 ( .A(net_58), .ZN(net_23) );
INV_X4 inst_98 ( .A(net_109), .ZN(net_42) );
CLKBUF_X2 inst_190 ( .A(net_183), .Z(net_184) );
NAND2_X2 inst_63 ( .A2(net_62), .A1(net_51), .ZN(net_47) );
OR3_X4 inst_7 ( .A2(net_81), .A1(net_80), .ZN(net_74), .A3(net_52) );
CLKBUF_X2 inst_204 ( .A(net_162), .Z(net_198) );
CLKBUF_X2 inst_185 ( .A(net_178), .Z(net_179) );
CLKBUF_X2 inst_182 ( .A(net_175), .Z(net_176) );
NAND2_X4 inst_49 ( .ZN(net_133), .A1(net_120), .A2(net_40) );
INV_X2 inst_120 ( .ZN(net_65), .A(net_64) );
CLKBUF_X2 inst_154 ( .A(net_147), .Z(net_148) );
NOR3_X2 inst_13 ( .ZN(net_59), .A1(net_58), .A2(net_57), .A3(net_56) );
INV_X2 inst_119 ( .ZN(net_56), .A(net_35) );
NAND2_X2 inst_75 ( .ZN(net_97), .A2(net_95), .A1(net_74) );
CLKBUF_X2 inst_192 ( .A(net_185), .Z(net_186) );
CLKBUF_X2 inst_166 ( .A(net_159), .Z(net_160) );
INV_X2 inst_116 ( .ZN(net_21), .A(net_20) );
CLKBUF_X2 inst_163 ( .A(net_155), .Z(net_157) );
INV_X4 inst_85 ( .ZN(net_40), .A(net_7) );
NAND2_X4 inst_54 ( .ZN(net_130), .A1(net_119), .A2(net_87) );
INV_X4 inst_79 ( .ZN(net_19), .A(net_3) );
INV_X2 inst_109 ( .A(net_127), .ZN(net_126) );
INV_X2 inst_106 ( .A(net_130), .ZN(net_129) );
CLKBUF_X2 inst_219 ( .A(net_212), .Z(net_213) );
CLKBUF_X2 inst_201 ( .A(net_194), .Z(net_195) );
CLKBUF_X2 inst_193 ( .A(net_170), .Z(net_187) );
AND2_X2 inst_149 ( .ZN(net_94), .A2(net_90), .A1(net_15) );
NAND3_X2 inst_43 ( .A2(net_127), .A3(net_124), .ZN(net_120), .A1(net_8) );
NOR2_X2 inst_39 ( .ZN(net_116), .A2(net_115), .A1(net_110) );
DFFR_X2 inst_128 ( .RN(net_118), .D(net_75), .QN(net_7), .CK(net_197) );
NAND2_X2 inst_73 ( .ZN(net_138), .A1(net_129), .A2(net_66) );
CLKBUF_X2 inst_217 ( .A(net_210), .Z(net_211) );
NOR3_X2 inst_23 ( .ZN(net_117), .A1(net_115), .A2(net_112), .A3(net_101) );
CLKBUF_X2 inst_171 ( .A(net_163), .Z(net_165) );
INV_X4 inst_77 ( .ZN(net_51), .A(net_4) );
INV_X4 inst_94 ( .ZN(net_109), .A(net_57) );
endmodule
|
module c1908 (
n227,
n902,
n217,
n237,
n143,
n131,
n110,
n134,
n952,
n221,
n900,
n140,
n113,
n234,
n146,
n122,
n472,
n104,
n107,
n128,
n953,
n101,
n125,
n224,
n116,
n210,
n475,
n119,
n478,
n898,
n214,
n137,
n469,
n66,
n72,
n69,
n54,
n18,
n24,
n75,
n60,
n39,
n45,
n42,
n30,
n63,
n57,
n9,
n21,
n51,
n33,
n6,
n15,
n12,
n3,
n27,
n48,
n36);
// Start PIs
input n227;
input n902;
input n217;
input n237;
input n143;
input n131;
input n110;
input n134;
input n952;
input n221;
input n900;
input n140;
input n113;
input n234;
input n146;
input n122;
input n472;
input n104;
input n107;
input n128;
input n953;
input n101;
input n125;
input n224;
input n116;
input n210;
input n475;
input n119;
input n478;
input n898;
input n214;
input n137;
input n469;
// Start POs
output n66;
output n72;
output n69;
output n54;
output n18;
output n24;
output n75;
output n60;
output n39;
output n45;
output n42;
output n30;
output n63;
output n57;
output n9;
output n21;
output n51;
output n33;
output n6;
output n15;
output n12;
output n3;
output n27;
output n48;
output n36;
// Start wires
wire net_166;
wire net_107;
wire net_47;
wire net_179;
wire net_176;
wire net_159;
wire net_61;
wire net_137;
wire net_132;
wire net_54;
wire n18;
wire net_105;
wire net_62;
wire net_6;
wire net_129;
wire net_119;
wire net_98;
wire net_23;
wire net_117;
wire net_12;
wire net_151;
wire net_74;
wire net_53;
wire net_93;
wire n63;
wire net_168;
wire net_135;
wire n27;
wire net_130;
wire n113;
wire net_147;
wire net_127;
wire net_14;
wire n146;
wire net_113;
wire net_26;
wire net_76;
wire n128;
wire n101;
wire net_101;
wire net_32;
wire net_187;
wire net_111;
wire net_90;
wire net_40;
wire n116;
wire net_100;
wire n210;
wire n475;
wire net_85;
wire net_69;
wire net_124;
wire net_161;
wire n119;
wire net_141;
wire net_160;
wire net_83;
wire n21;
wire net_115;
wire net_4;
wire n36;
wire net_95;
wire net_17;
wire net_173;
wire net_78;
wire net_27;
wire net_164;
wire n69;
wire net_56;
wire net_87;
wire net_0;
wire net_155;
wire net_35;
wire net_191;
wire n143;
wire net_22;
wire net_16;
wire net_181;
wire n131;
wire net_193;
wire net_39;
wire net_157;
wire net_144;
wire net_102;
wire net_2;
wire net_59;
wire net_9;
wire n952;
wire n57;
wire net_42;
wire n9;
wire net_120;
wire net_109;
wire n12;
wire net_80;
wire net_65;
wire net_50;
wire net_162;
wire n234;
wire net_96;
wire net_66;
wire net_38;
wire net_44;
wire net_167;
wire n122;
wire net_136;
wire net_134;
wire n107;
wire net_19;
wire net_89;
wire net_45;
wire net_126;
wire n45;
wire net_185;
wire net_34;
wire net_108;
wire n478;
wire net_183;
wire net_178;
wire net_150;
wire net_63;
wire n137;
wire n227;
wire n902;
wire n72;
wire net_152;
wire net_116;
wire net_30;
wire net_189;
wire n54;
wire net_175;
wire net_91;
wire n237;
wire n75;
wire net_106;
wire net_99;
wire net_24;
wire net_55;
wire net_186;
wire n39;
wire n60;
wire net_46;
wire net_140;
wire net_118;
wire net_148;
wire net_104;
wire n42;
wire net_146;
wire n134;
wire net_72;
wire net_122;
wire n221;
wire net_25;
wire net_70;
wire n900;
wire n51;
wire net_7;
wire n140;
wire n48;
wire net_194;
wire net_172;
wire net_5;
wire net_52;
wire net_165;
wire net_128;
wire n472;
wire n104;
wire net_138;
wire net_13;
wire net_184;
wire net_94;
wire net_11;
wire net_18;
wire net_123;
wire net_131;
wire net_114;
wire n30;
wire net_196;
wire net_170;
wire net_29;
wire net_68;
wire net_149;
wire net_142;
wire net_77;
wire n898;
wire n214;
wire net_20;
wire net_31;
wire n3;
wire n469;
wire net_36;
wire net_49;
wire net_158;
wire net_15;
wire net_41;
wire net_57;
wire n217;
wire net_71;
wire net_153;
wire net_156;
wire net_3;
wire net_84;
wire net_174;
wire net_154;
wire net_112;
wire net_92;
wire net_1;
wire net_103;
wire net_139;
wire n110;
wire net_43;
wire net_10;
wire net_180;
wire net_28;
wire net_169;
wire net_21;
wire net_51;
wire net_171;
wire net_79;
wire n15;
wire net_143;
wire net_97;
wire net_190;
wire n66;
wire net_88;
wire net_182;
wire net_192;
wire net_145;
wire net_60;
wire n953;
wire net_81;
wire n24;
wire net_163;
wire net_58;
wire n125;
wire net_82;
wire net_67;
wire n224;
wire net_64;
wire net_37;
wire net_188;
wire net_110;
wire net_121;
wire net_73;
wire net_33;
wire net_48;
wire net_177;
wire net_86;
wire net_75;
wire net_8;
wire net_133;
wire n6;
wire n33;
wire net_195;
wire net_125;
// Start cells
NAND3_X1 inst_145 ( .A3(net_142), .A2(net_121), .ZN(net_120), .A1(net_119) );
NOR2_X1 inst_103 ( .ZN(net_60), .A1(net_59), .A2(net_58) );
NOR2_X1 inst_125 ( .ZN(net_162), .A2(net_153), .A1(net_152) );
AND4_X1 inst_207 ( .A1(net_121), .ZN(net_115), .A3(net_114), .A4(net_113), .A2(net_94) );
NAND4_X1 inst_138 ( .ZN(net_149), .A2(net_121), .A3(net_114), .A1(net_111), .A4(net_100) );
NAND2_X1 inst_159 ( .ZN(net_101), .A2(net_21), .A1(n214) );
AND2_X4 inst_218 ( .A1(net_114), .ZN(net_107), .A2(net_94) );
XOR2_X1 inst_15 ( .Z(net_82), .A(net_75), .B(n469) );
INV_X1 inst_197 ( .ZN(net_143), .A(net_88) );
NOR2_X1 inst_134 ( .A2(net_195), .A1(net_194), .ZN(n57) );
NAND2_X1 inst_179 ( .ZN(net_157), .A2(net_144), .A1(net_143) );
XOR2_X1 inst_24 ( .A(net_156), .Z(n12), .B(n110) );
NOR2_X1 inst_114 ( .A2(net_130), .ZN(net_118), .A1(net_88) );
XOR2_X1 inst_6 ( .Z(net_13), .A(n137), .B(n134) );
INV_X1 inst_194 ( .ZN(net_85), .A(net_80) );
NOR2_X1 inst_131 ( .A1(net_194), .A2(net_187), .ZN(n54) );
OR2_X4 inst_76 ( .A1(net_121), .ZN(net_110), .A2(net_31) );
AND2_X4 inst_214 ( .A1(net_59), .A2(net_58), .ZN(net_57) );
NAND2_X1 inst_180 ( .ZN(net_160), .A2(net_144), .A1(net_142) );
NAND2_X1 inst_160 ( .ZN(net_22), .A2(net_2), .A1(n953) );
NAND3_X1 inst_150 ( .ZN(net_181), .A3(net_180), .A1(n902), .A2(n472) );
XNOR2_X1 inst_33 ( .ZN(net_36), .A(net_7), .B(n110) );
NAND2_X1 inst_172 ( .ZN(net_126), .A1(net_108), .A2(net_107) );
NOR4_X1 inst_83 ( .ZN(net_183), .A4(net_175), .A2(net_170), .A1(net_115), .A3(net_112) );
XNOR2_X1 inst_47 ( .ZN(net_65), .B(net_43), .A(net_10) );
XOR2_X1 inst_19 ( .A(net_145), .Z(n18), .B(n116) );
NOR2_X1 inst_123 ( .ZN(net_144), .A2(net_128), .A1(net_89) );
NOR2_X1 inst_121 ( .ZN(net_146), .A1(net_126), .A2(net_103) );
XOR2_X1 inst_2 ( .Z(net_7), .A(n128), .B(n119) );
XOR2_X1 inst_8 ( .Z(net_16), .A(n143), .B(n128) );
NOR2_X1 inst_118 ( .ZN(net_111), .A1(net_101), .A2(net_99) );
NOR3_X1 inst_86 ( .ZN(net_56), .A3(net_52), .A1(net_51), .A2(net_11) );
NAND2_X1 inst_153 ( .ZN(net_3), .A2(n898), .A1(n224) );
XOR2_X1 inst_20 ( .A(net_146), .Z(n15), .B(n113) );
XOR2_X1 inst_27 ( .Z(net_176), .A(net_171), .B(net_56) );
XNOR2_X1 inst_38 ( .ZN(net_59), .A(net_26), .B(n101) );
NOR2_X1 inst_100 ( .ZN(net_31), .A2(net_30), .A1(n900) );
XNOR2_X1 inst_52 ( .ZN(net_71), .A(net_69), .B(net_65) );
NOR3_X1 inst_90 ( .ZN(net_155), .A1(net_134), .A2(net_133), .A3(net_132) );
NAND4_X1 inst_140 ( .ZN(net_175), .A4(net_174), .A2(net_172), .A3(net_137), .A1(n952) );
AND4_X1 inst_209 ( .ZN(net_196), .A1(net_191), .A2(net_131), .A3(net_125), .A4(net_122) );
AND3_X4 inst_211 ( .ZN(net_129), .A2(net_110), .A1(net_106), .A3(net_105) );
AND2_X4 inst_221 ( .ZN(net_159), .A1(net_143), .A2(net_141) );
XNOR2_X1 inst_40 ( .ZN(net_47), .A(net_46), .B(net_36) );
NAND2_X1 inst_162 ( .ZN(net_29), .A2(net_27), .A1(n221) );
NAND2_X1 inst_167 ( .ZN(net_130), .A1(net_86), .A2(net_85) );
NOR3_X1 inst_93 ( .ZN(net_156), .A1(net_134), .A3(net_132), .A2(net_130) );
NOR4_X1 inst_81 ( .ZN(net_136), .A1(net_116), .A4(net_102), .A2(net_87), .A3(net_86) );
NOR3_X1 inst_95 ( .ZN(net_169), .A1(net_166), .A2(net_165), .A3(net_164) );
XOR2_X1 inst_1 ( .Z(net_6), .A(n119), .B(n116) );
XNOR2_X1 inst_72 ( .ZN(net_195), .B(net_190), .A(net_59) );
NAND4_X1 inst_139 ( .ZN(net_164), .A1(net_160), .A3(net_151), .A4(net_150), .A2(net_138) );
NAND2_X1 inst_155 ( .A2(net_172), .ZN(net_9), .A1(n227) );
XNOR2_X1 inst_59 ( .B(net_150), .ZN(n36), .A(n134) );
NOR2_X1 inst_135 ( .A2(net_196), .A1(net_154), .ZN(n75) );
INV_X1 inst_196 ( .ZN(net_133), .A(net_90) );
XNOR2_X1 inst_44 ( .ZN(net_61), .B(net_47), .A(net_39) );
XNOR2_X1 inst_55 ( .ZN(net_86), .A(net_73), .B(net_62) );
NAND2_X1 inst_174 ( .ZN(net_128), .A1(net_110), .A2(net_109) );
NOR2_X1 inst_115 ( .A1(net_134), .ZN(net_95), .A2(net_89) );
XNOR2_X1 inst_37 ( .ZN(net_38), .A(net_13), .B(n131) );
AND3_X4 inst_210 ( .A2(net_172), .ZN(net_121), .A3(net_24), .A1(n952) );
NAND3_X1 inst_148 ( .A3(net_180), .ZN(net_178), .A1(n902), .A2(n478) );
NAND2_X1 inst_164 ( .ZN(net_89), .A1(net_86), .A2(net_80) );
INV_X1 inst_191 ( .ZN(net_116), .A(net_29) );
XOR2_X1 inst_5 ( .Z(net_12), .A(n122), .B(n113) );
NAND2_X1 inst_157 ( .A2(net_172), .ZN(net_18), .A1(n224) );
NOR3_X1 inst_84 ( .ZN(net_19), .A2(net_1), .A3(n953), .A1(n237) );
XNOR2_X1 inst_51 ( .ZN(net_74), .A(net_54), .B(net_37) );
NAND3_X1 inst_142 ( .ZN(net_30), .A1(net_24), .A3(n953), .A2(n902) );
OR2_X4 inst_80 ( .A1(net_134), .ZN(net_123), .A2(net_93) );
NAND2_X1 inst_173 ( .ZN(net_132), .A2(net_109), .A1(net_108) );
NOR2_X1 inst_105 ( .ZN(net_66), .A2(net_65), .A1(net_8) );
AND2_X4 inst_213 ( .A2(net_53), .ZN(net_51), .A1(net_50) );
XNOR2_X1 inst_68 ( .ZN(net_189), .A(net_179), .B(net_77) );
AND2_X4 inst_216 ( .A1(net_69), .ZN(net_68), .A2(net_67) );
OR2_X4 inst_78 ( .ZN(net_127), .A1(net_86), .A2(net_80) );
XNOR2_X1 inst_42 ( .ZN(net_53), .A(net_44), .B(net_38) );
NAND2_X1 inst_175 ( .ZN(net_147), .A1(net_129), .A2(net_118) );
XNOR2_X1 inst_53 ( .ZN(net_77), .A(net_55), .B(net_35) );
INV_X1 inst_205 ( .ZN(net_170), .A(net_169) );
NAND2_X1 inst_177 ( .ZN(net_151), .A1(net_129), .A2(net_104) );
NAND2_X1 inst_183 ( .ZN(net_173), .A1(net_172), .A2(net_168) );
NOR2_X1 inst_133 ( .A1(net_194), .A2(net_193), .ZN(n51) );
XOR2_X1 inst_26 ( .A(net_159), .Z(n6), .B(n104) );
NAND3_X1 inst_151 ( .ZN(net_182), .A3(net_180), .A1(n902), .A2(n469) );
NOR2_X1 inst_112 ( .ZN(net_84), .A1(net_83), .A2(net_82) );
XNOR2_X1 inst_64 ( .B(net_176), .A(net_22), .ZN(n72) );
NOR2_X1 inst_107 ( .ZN(net_75), .A2(net_74), .A1(n902) );
XNOR2_X1 inst_67 ( .ZN(net_188), .A(net_178), .B(net_63) );
NAND2_X1 inst_181 ( .ZN(net_166), .A1(net_148), .A2(net_147) );
NOR2_X1 inst_127 ( .ZN(net_185), .A2(net_184), .A1(net_73) );
XNOR2_X1 inst_70 ( .ZN(net_192), .A(net_185), .B(net_61) );
INV_X1 inst_186 ( .ZN(net_172), .A(n953) );
NOR2_X1 inst_129 ( .A1(net_194), .A2(net_189), .ZN(n60) );
NOR3_X1 inst_92 ( .ZN(net_139), .A1(net_135), .A2(net_133), .A3(net_128) );
XNOR2_X1 inst_29 ( .ZN(net_42), .A(net_6), .B(n113) );
INV_X1 inst_189 ( .ZN(net_1), .A(n214) );
XOR2_X1 inst_17 ( .Z(net_100), .A(net_79), .B(net_76) );
XOR2_X1 inst_11 ( .Z(net_39), .B(net_25), .A(n137) );
NAND3_X1 inst_146 ( .A3(net_143), .ZN(net_122), .A2(net_121), .A1(net_119) );
INV_X1 inst_188 ( .ZN(net_14), .A(n902) );
XOR2_X1 inst_14 ( .Z(net_80), .B(net_72), .A(n472) );
INV_X1 inst_202 ( .ZN(net_104), .A(net_103) );
AND4_X1 inst_206 ( .A1(net_121), .A4(net_113), .ZN(net_112), .A2(net_106), .A3(net_105) );
INV_X1 inst_187 ( .ZN(net_0), .A(n210) );
NOR2_X1 inst_122 ( .ZN(net_141), .A2(net_132), .A1(net_127) );
XNOR2_X1 inst_31 ( .ZN(net_34), .A(net_5), .B(n107) );
XOR2_X1 inst_25 ( .A(net_158), .Z(n9), .B(n107) );
NOR2_X1 inst_126 ( .ZN(net_171), .A2(net_167), .A1(n953) );
NAND2_X1 inst_158 ( .ZN(net_20), .A2(net_3), .A1(n953) );
NAND3_X1 inst_141 ( .A3(net_172), .ZN(net_23), .A1(n234), .A2(n217) );
XNOR2_X1 inst_62 ( .B(net_160), .ZN(n30), .A(n128) );
INV_X1 inst_200 ( .ZN(net_98), .A(net_97) );
NOR2_X1 inst_110 ( .ZN(net_142), .A2(net_83), .A1(net_81) );
OR3_X2 inst_74 ( .ZN(net_131), .A3(net_130), .A2(net_124), .A1(net_123) );
XNOR2_X1 inst_57 ( .B(net_147), .ZN(n42), .A(n140) );
XNOR2_X1 inst_35 ( .ZN(net_37), .A(net_15), .B(net_9) );
NOR2_X1 inst_99 ( .ZN(net_194), .A1(net_172), .A2(n952) );
XNOR2_X1 inst_48 ( .ZN(net_63), .A(net_48), .B(net_23) );
XNOR2_X1 inst_69 ( .ZN(net_190), .B(net_181), .A(net_58) );
XNOR2_X1 inst_46 ( .ZN(net_58), .B(net_53), .A(net_42) );
NOR4_X1 inst_82 ( .ZN(net_161), .A2(net_159), .A4(net_158), .A3(net_156), .A1(net_155) );
NAND4_X1 inst_136 ( .ZN(net_102), .A1(net_101), .A4(net_100), .A3(net_85), .A2(net_84) );
XNOR2_X1 inst_30 ( .ZN(net_33), .A(net_16), .B(n134) );
NOR2_X1 inst_102 ( .A2(net_53), .ZN(net_52), .A1(net_50) );
NOR2_X1 inst_108 ( .ZN(net_78), .A2(net_77), .A1(n902) );
NAND2_X1 inst_165 ( .ZN(net_135), .A1(net_87), .A2(net_83) );
XNOR2_X1 inst_32 ( .ZN(net_35), .A(net_12), .B(n104) );
XOR2_X1 inst_22 ( .A(net_155), .Z(n3), .B(n101) );
NAND3_X1 inst_144 ( .ZN(net_138), .A3(net_118), .A1(net_110), .A2(net_107) );
XNOR2_X1 inst_34 ( .ZN(net_41), .A(net_4), .B(n101) );
XOR2_X1 inst_12 ( .Z(net_43), .A(net_42), .B(net_41) );
INV_X1 inst_195 ( .A(net_114), .ZN(net_93) );
XNOR2_X1 inst_56 ( .B(net_138), .ZN(n27), .A(n125) );
XNOR2_X1 inst_71 ( .ZN(net_193), .A(net_186), .B(net_71) );
XOR2_X1 inst_21 ( .A(net_139), .Z(n45), .B(n143) );
NOR2_X1 inst_104 ( .ZN(net_64), .A2(net_63), .A1(n902) );
XNOR2_X1 inst_60 ( .B(net_151), .ZN(n33), .A(n131) );
AND2_X4 inst_215 ( .ZN(net_62), .A2(net_61), .A1(net_14) );
NAND2_X1 inst_169 ( .A1(net_142), .ZN(net_97), .A2(net_90) );
NAND2_X1 inst_168 ( .A1(net_101), .A2(net_100), .ZN(net_91) );
NOR2_X1 inst_97 ( .A1(net_172), .ZN(net_8), .A2(n898) );
NAND2_X1 inst_161 ( .ZN(net_79), .A2(net_21), .A1(n210) );
NOR2_X1 inst_124 ( .ZN(net_163), .A1(net_146), .A2(net_145) );
XOR2_X1 inst_18 ( .A(net_152), .Z(n21), .B(n119) );
XOR2_X1 inst_16 ( .Z(net_83), .A(net_78), .B(n475) );
AND4_X1 inst_208 ( .ZN(net_191), .A2(net_183), .A4(net_149), .A1(net_120), .A3(net_117) );
NOR3_X1 inst_88 ( .ZN(net_76), .A1(net_70), .A3(net_68), .A2(n902) );
AND2_X4 inst_220 ( .ZN(net_158), .A1(net_142), .A2(net_141) );
XOR2_X1 inst_3 ( .Z(net_10), .A(n122), .B(n110) );
NAND2_X1 inst_156 ( .ZN(net_27), .A2(net_14), .A1(n234) );
XOR2_X1 inst_9 ( .Z(net_17), .A(n146), .B(n143) );
NOR2_X1 inst_113 ( .A2(net_100), .ZN(net_94), .A1(net_28) );
NAND2_X1 inst_170 ( .A1(net_143), .ZN(net_103), .A2(net_90) );
INV_X1 inst_198 ( .ZN(net_105), .A(net_91) );
XNOR2_X1 inst_50 ( .ZN(net_55), .B(net_49), .A(net_46) );
NAND4_X1 inst_137 ( .A1(net_121), .ZN(net_117), .A3(net_116), .A4(net_113), .A2(net_92) );
INV_X1 inst_199 ( .ZN(net_96), .A(net_95) );
XNOR2_X1 inst_41 ( .ZN(net_48), .B(net_34), .A(net_33) );
NOR2_X1 inst_130 ( .A1(net_194), .A2(net_188), .ZN(n63) );
NOR3_X1 inst_91 ( .ZN(net_153), .A1(net_135), .A2(net_127), .A3(net_126) );
NOR2_X1 inst_132 ( .A1(net_194), .A2(net_192), .ZN(n66) );
NAND3_X1 inst_143 ( .A3(net_172), .ZN(net_25), .A1(n234), .A2(n221) );
NAND2_X1 inst_176 ( .ZN(net_148), .A1(net_129), .A2(net_95) );
NAND2_X1 inst_152 ( .ZN(net_2), .A2(n900), .A1(n227) );
XNOR2_X1 inst_58 ( .B(net_148), .ZN(n39), .A(n137) );
XNOR2_X1 inst_36 ( .ZN(net_44), .A(net_17), .B(n128) );
NAND3_X1 inst_147 ( .ZN(net_168), .A2(net_163), .A1(net_162), .A3(net_161) );
NOR3_X1 inst_87 ( .ZN(net_72), .A3(net_60), .A1(net_57), .A2(n902) );
XNOR2_X1 inst_61 ( .B(net_157), .ZN(n48), .A(n146) );
INV_X1 inst_203 ( .ZN(net_137), .A(net_136) );
XNOR2_X1 inst_45 ( .ZN(net_54), .B(net_53), .A(net_41) );
NOR3_X1 inst_96 ( .ZN(net_167), .A2(net_166), .A1(net_165), .A3(net_164) );
AND3_X4 inst_212 ( .ZN(net_174), .A1(net_163), .A2(net_162), .A3(net_161) );
NOR2_X1 inst_101 ( .ZN(net_32), .A2(net_30), .A1(n898) );
XOR2_X1 inst_0 ( .Z(net_5), .A(n122), .B(n116) );
NAND2_X1 inst_184 ( .ZN(net_180), .A2(net_174), .A1(net_169) );
XOR2_X1 inst_10 ( .B(net_50), .Z(net_46), .A(n146) );
XOR2_X1 inst_4 ( .Z(net_50), .A(n140), .B(n125) );
XNOR2_X1 inst_65 ( .B(net_177), .A(net_20), .ZN(n69) );
NAND2_X1 inst_178 ( .ZN(net_150), .A1(net_129), .A2(net_98) );
NOR3_X1 inst_89 ( .A3(net_127), .ZN(net_119), .A2(net_93), .A1(net_91) );
XNOR2_X1 inst_28 ( .ZN(net_4), .A(n107), .B(n104) );
NOR2_X1 inst_111 ( .ZN(net_90), .A1(net_86), .A2(net_85) );
XNOR2_X1 inst_66 ( .ZN(net_187), .A(net_182), .B(net_74) );
NOR2_X1 inst_117 ( .ZN(net_92), .A2(net_91), .A1(net_82) );
NOR2_X1 inst_98 ( .A1(net_172), .ZN(net_11), .A2(n900) );
INV_X1 inst_190 ( .A(net_101), .ZN(net_28) );
XNOR2_X1 inst_63 ( .ZN(net_177), .B(net_173), .A(net_66) );
XOR2_X1 inst_7 ( .Z(net_15), .A(n140), .B(n110) );
INV_X1 inst_204 ( .ZN(net_140), .A(net_139) );
NAND2_X1 inst_185 ( .ZN(net_184), .A2(net_180), .A1(n902) );
NAND2_X1 inst_182 ( .ZN(net_165), .A1(net_157), .A2(net_140) );
XNOR2_X1 inst_49 ( .ZN(net_69), .A(net_45), .B(net_18) );
NOR2_X1 inst_120 ( .ZN(net_145), .A1(net_126), .A2(net_97) );
NAND2_X1 inst_154 ( .ZN(net_24), .A2(n237), .A1(n234) );
XOR2_X1 inst_13 ( .Z(net_45), .B(net_44), .A(n125) );
NOR2_X1 inst_119 ( .ZN(net_152), .A1(net_126), .A2(net_96) );
OR2_X4 inst_75 ( .ZN(net_21), .A2(n902), .A1(n237) );
INV_X1 inst_192 ( .ZN(net_67), .A(net_65) );
NAND2_X1 inst_166 ( .ZN(net_88), .A2(net_83), .A1(net_81) );
NOR2_X1 inst_116 ( .A1(net_134), .A2(net_127), .ZN(net_113) );
NAND2_X1 inst_163 ( .ZN(net_73), .A2(net_27), .A1(n217) );
NOR3_X1 inst_85 ( .ZN(net_26), .A2(net_0), .A3(n953), .A1(n237) );
XNOR2_X1 inst_54 ( .ZN(net_81), .A(net_64), .B(n478) );
OR2_X4 inst_79 ( .ZN(net_134), .A1(net_87), .A2(net_83) );
NOR2_X1 inst_109 ( .A1(net_116), .ZN(net_114), .A2(net_82) );
NOR2_X1 inst_106 ( .ZN(net_70), .A1(net_69), .A2(net_67) );
AND2_X4 inst_219 ( .ZN(net_109), .A1(net_106), .A2(net_94) );
INV_X1 inst_201 ( .A(net_113), .ZN(net_99) );
INV_X1 inst_193 ( .ZN(net_87), .A(net_81) );
NAND3_X1 inst_149 ( .A3(net_180), .ZN(net_179), .A1(n902), .A2(n475) );
XNOR2_X1 inst_43 ( .ZN(net_49), .A(net_40), .B(n131) );
XNOR2_X1 inst_39 ( .ZN(net_40), .A(net_19), .B(n143) );
NOR2_X1 inst_128 ( .ZN(net_186), .A2(net_184), .A1(net_79) );
OR3_X2 inst_73 ( .A2(net_133), .ZN(net_125), .A1(net_124), .A3(net_123) );
AND2_X4 inst_217 ( .ZN(net_106), .A2(net_82), .A1(net_29) );
XOR2_X1 inst_23 ( .A(net_153), .Z(n24), .B(n122) );
NAND2_X1 inst_171 ( .ZN(net_124), .A1(net_121), .A2(net_105) );
OR2_X4 inst_77 ( .A1(net_121), .ZN(net_108), .A2(net_32) );
NOR3_X1 inst_94 ( .ZN(net_154), .A3(net_136), .A2(n953), .A1(n952) );
endmodule
|
module simple (
inp1,
inp2,
tau2015_clk,
out
);
// Start PIs
input inp1;
input inp2;
input tau2015_clk;
// Start POs
output out;
// Start wires
wire n1;
wire n2;
wire n3;
wire n4;
wire inp1;
wire inp2;
wire tau2015_clk;
wire out;
// Start cells
NAND2_X1 u1 ( .a(inp1), .b(inp2), .o(n1) );
DFF_X80 f1 ( .d(n2), .ck(tau2015_clk), .q(n3) );
INV_X1 u2 ( .a(n3), .o(n4) );
INV_X2 u3 ( .a(n4), .o(out) );
NOR2_X1 u4 ( .a(n1), .b(n3), .o(n2) );
endmodule
|
module s510 (
cnt509,
pcnt12,
cnt283,
cnt44,
cnt13,
pcnt241,
blif_clk_net,
pcnt6,
cnt261,
john,
pcnt17,
cnt511,
cnt272,
cnt21,
cnt567,
cnt10,
cnt45,
pcnt27,
cnt284,
cnt591,
blif_reset_net,
cclr,
vsync,
cblank,
csync,
pc,
csm,
pclr);
// Start PIs
input cnt509;
input pcnt12;
input cnt283;
input cnt44;
input cnt13;
input pcnt241;
input blif_clk_net;
input pcnt6;
input cnt261;
input john;
input pcnt17;
input cnt511;
input cnt272;
input cnt21;
input cnt567;
input cnt10;
input cnt45;
input pcnt27;
input cnt284;
input cnt591;
input blif_reset_net;
// Start POs
output cclr;
output vsync;
output cblank;
output csync;
output pc;
output csm;
output pclr;
// Start wires
wire net_47;
wire net_176;
wire net_215;
wire net_137;
wire net_132;
wire net_54;
wire net_237;
wire net_105;
wire vsync;
wire net_129;
wire net_119;
wire net_98;
wire net_12;
wire net_151;
wire net_53;
wire net_93;
wire net_210;
wire net_168;
wire net_259;
wire net_269;
wire net_127;
wire pclr;
wire net_76;
wire net_101;
wire net_187;
wire net_111;
wire net_264;
wire net_90;
wire net_225;
wire net_283;
wire net_100;
wire net_85;
wire net_263;
wire net_252;
wire net_124;
wire net_240;
wire net_160;
wire net_221;
wire net_115;
wire net_4;
wire net_17;
wire net_164;
wire cnt13;
wire pcnt241;
wire net_87;
wire net_0;
wire net_35;
wire net_16;
wire net_239;
wire net_193;
wire net_157;
wire net_257;
wire net_233;
wire net_42;
wire net_120;
wire net_201;
wire net_109;
wire net_80;
wire net_65;
wire blif_reset_net;
wire net_50;
wire net_234;
wire net_96;
wire net_66;
wire net_38;
wire net_167;
wire net_207;
wire net_136;
wire net_280;
wire net_19;
wire net_126;
wire net_278;
wire net_34;
wire net_108;
wire net_270;
wire net_183;
wire net_150;
wire net_63;
wire net_274;
wire pcnt12;
wire net_30;
wire net_189;
wire net_24;
wire net_99;
wire net_186;
wire net_46;
wire net_118;
wire net_216;
wire net_146;
wire pcnt27;
wire net_122;
wire net_7;
wire net_224;
wire net_172;
wire net_52;
wire net_165;
wire pc;
wire net_13;
wire net_246;
wire net_94;
wire net_219;
wire net_18;
wire net_131;
wire net_114;
wire net_196;
wire net_29;
wire net_149;
wire net_142;
wire net_248;
wire net_31;
wire net_36;
wire net_158;
wire net_41;
wire net_198;
wire net_253;
wire net_276;
wire net_209;
wire net_3;
wire net_154;
wire john;
wire net_213;
wire net_238;
wire net_260;
wire net_28;
wire net_97;
wire net_182;
wire net_192;
wire net_60;
wire net_267;
wire net_273;
wire net_256;
wire net_58;
wire net_82;
wire net_64;
wire cnt567;
wire net_121;
wire cnt45;
wire net_73;
wire net_200;
wire net_177;
wire net_75;
wire net_86;
wire net_206;
wire net_195;
wire net_125;
wire net_107;
wire net_166;
wire net_223;
wire net_179;
wire net_235;
wire net_159;
wire net_61;
wire net_62;
wire net_6;
wire net_217;
wire net_271;
wire net_23;
wire cnt10;
wire net_117;
wire net_74;
wire net_250;
wire net_205;
wire net_135;
wire net_265;
wire net_242;
wire net_130;
wire cclr;
wire net_147;
wire net_14;
wire net_220;
wire net_26;
wire net_113;
wire blif_clk_net;
wire net_32;
wire csm;
wire net_40;
wire net_282;
wire net_69;
wire cblank;
wire cnt284;
wire net_161;
wire net_141;
wire net_83;
wire net_95;
wire net_173;
wire net_78;
wire net_27;
wire cnt44;
wire net_56;
wire net_155;
wire net_261;
wire net_191;
wire net_22;
wire net_181;
wire net_39;
wire net_245;
wire net_2;
wire net_102;
wire net_144;
wire net_227;
wire net_9;
wire net_59;
wire net_162;
wire net_230;
wire net_44;
wire net_277;
wire net_134;
wire net_199;
wire net_45;
wire net_89;
wire cnt272;
wire net_185;
wire net_272;
wire net_178;
wire net_236;
wire net_208;
wire net_212;
wire net_243;
wire cnt283;
wire net_222;
wire net_152;
wire net_116;
wire net_175;
wire net_91;
wire net_55;
wire net_106;
wire net_258;
wire net_255;
wire net_140;
wire net_266;
wire net_247;
wire pcnt17;
wire net_279;
wire net_104;
wire net_148;
wire net_72;
wire net_25;
wire net_229;
wire net_70;
wire net_251;
wire net_194;
wire net_241;
wire net_5;
wire net_244;
wire net_128;
wire net_138;
wire pcnt6;
wire net_184;
wire net_11;
wire net_123;
wire csync;
wire net_262;
wire net_170;
wire net_68;
wire net_77;
wire net_214;
wire net_249;
wire net_20;
wire net_49;
wire net_15;
wire net_275;
wire net_57;
wire net_71;
wire net_153;
wire net_156;
wire net_84;
wire net_218;
wire cnt261;
wire net_174;
wire net_231;
wire net_92;
wire net_1;
wire net_112;
wire net_103;
wire net_139;
wire net_226;
wire net_43;
wire net_228;
wire net_10;
wire net_180;
wire net_21;
wire net_169;
wire net_51;
wire net_79;
wire net_171;
wire net_143;
wire cnt509;
wire net_190;
wire net_88;
wire net_145;
wire net_281;
wire net_197;
wire net_204;
wire net_81;
wire net_232;
wire net_163;
wire net_254;
wire net_67;
wire net_37;
wire net_202;
wire net_268;
wire cnt511;
wire cnt21;
wire net_188;
wire net_110;
wire net_48;
wire net_33;
wire net_8;
wire net_211;
wire cnt591;
wire net_133;
wire net_203;
// Start cells
DFFR_X2 inst_257 ( .QN(net_238), .RN(net_235), .D(net_232), .CK(net_275) );
CLKBUF_X2 inst_290 ( .A(net_282), .Z(net_283) );
NAND2_X2 inst_145 ( .ZN(net_188), .A1(net_110), .A2(net_34) );
CLKBUF_X2 inst_272 ( .A(net_264), .Z(net_265) );
NAND2_X2 inst_103 ( .ZN(net_254), .A1(net_23), .A2(net_0) );
INV_X2 inst_248 ( .ZN(net_246), .A(net_142) );
INV_X2 inst_228 ( .A(net_79), .ZN(net_12) );
NAND2_X2 inst_125 ( .ZN(net_108), .A1(net_96), .A2(net_71) );
INV_X4 inst_207 ( .ZN(net_192), .A(net_149) );
NAND2_X2 inst_138 ( .ZN(net_160), .A1(net_159), .A2(net_157) );
NAND2_X2 inst_159 ( .ZN(net_228), .A1(net_211), .A2(net_209) );
NAND2_X2 inst_134 ( .A2(net_225), .ZN(net_146), .A1(net_127) );
INV_X2 inst_244 ( .ZN(net_125), .A(net_111) );
NAND2_X2 inst_131 ( .ZN(net_128), .A1(net_127), .A2(net_89) );
INV_X4 inst_214 ( .ZN(net_159), .A(net_115) );
INV_X4 inst_180 ( .A(net_238), .ZN(net_104) );
NAND2_X1 inst_160 ( .ZN(net_9), .A1(pcnt17), .A2(cnt284) );
NOR2_X2 inst_33 ( .ZN(net_88), .A2(net_43), .A1(net_23) );
NOR2_X2 inst_47 ( .ZN(net_135), .A2(net_81), .A1(net_18) );
NOR3_X2 inst_19 ( .ZN(net_239), .A1(net_231), .A3(net_230), .A2(net_228) );
OR2_X2 inst_8 ( .ZN(net_171), .A2(net_170), .A1(net_67) );
INV_X2 inst_232 ( .A(net_199), .ZN(net_34) );
INV_X2 inst_247 ( .ZN(net_212), .A(net_113) );
NOR2_X4 inst_27 ( .A2(net_253), .ZN(net_148), .A1(net_142) );
NAND2_X2 inst_100 ( .ZN(net_15), .A2(net_6), .A1(cnt44) );
CLKBUF_X2 inst_279 ( .A(net_271), .Z(net_272) );
INV_X1 inst_253 ( .ZN(net_235), .A(blif_reset_net) );
INV_X4 inst_211 ( .ZN(net_115), .A(net_86) );
INV_X8 inst_162 ( .ZN(net_60), .A(net_11) );
NAND2_X4 inst_93 ( .A2(net_245), .ZN(net_78), .A1(net_57) );
NAND3_X2 inst_81 ( .ZN(net_208), .A2(net_207), .A3(net_122), .A1(net_55) );
NAND2_X2 inst_139 ( .ZN(net_165), .A1(net_106), .A2(net_83) );
NAND2_X2 inst_155 ( .ZN(net_206), .A2(net_155), .A1(net_149) );
NOR2_X2 inst_59 ( .ZN(net_223), .A2(net_217), .A1(net_150) );
NAND2_X2 inst_135 ( .A1(net_207), .ZN(net_151), .A2(net_93) );
INV_X4 inst_196 ( .A(net_173), .ZN(net_49) );
NOR2_X2 inst_55 ( .ZN(net_191), .A2(net_147), .A1(net_97) );
NOR2_X2 inst_37 ( .A2(net_199), .A1(net_100), .ZN(net_61) );
INV_X2 inst_237 ( .ZN(net_63), .A(net_62) );
NAND2_X2 inst_148 ( .ZN(net_194), .A1(net_141), .A2(net_103) );
AND2_X4 inst_264 ( .A2(net_261), .ZN(net_40), .A1(net_10) );
INV_X4 inst_191 ( .ZN(net_102), .A(net_74) );
NAND3_X2 inst_84 ( .ZN(net_218), .A3(net_197), .A1(net_161), .A2(net_158) );
NOR2_X2 inst_51 ( .ZN(net_147), .A2(net_118), .A1(cnt284) );
NAND2_X2 inst_142 ( .ZN(net_177), .A2(net_154), .A1(net_140) );
NAND3_X2 inst_80 ( .A3(net_252), .A1(net_251), .ZN(net_204), .A2(net_73) );
INV_X4 inst_173 ( .ZN(net_23), .A(net_13) );
INV_X2 inst_224 ( .ZN(net_4), .A(cnt511) );
INV_X4 inst_216 ( .ZN(net_141), .A(net_140) );
NAND3_X2 inst_78 ( .ZN(net_193), .A2(net_192), .A1(net_168), .A3(net_153) );
CLKBUF_X2 inst_287 ( .A(net_273), .Z(net_280) );
NOR2_X2 inst_42 ( .ZN(net_120), .A1(net_62), .A2(net_24) );
INV_X2 inst_241 ( .A(net_105), .ZN(net_77) );
INV_X4 inst_177 ( .ZN(net_14), .A(net_13) );
INV_X2 inst_231 ( .A(net_40), .ZN(net_32) );
CLKBUF_X2 inst_270 ( .A(blif_clk_net), .Z(net_263) );
INV_X4 inst_183 ( .ZN(net_52), .A(net_24) );
NOR2_X4 inst_26 ( .ZN(net_249), .A1(net_65), .A2(net_60) );
NAND2_X2 inst_151 ( .ZN(net_197), .A2(net_128), .A1(net_33) );
NOR2_X1 inst_64 ( .ZN(net_182), .A1(net_181), .A2(net_167) );
NAND2_X2 inst_107 ( .A1(net_98), .ZN(net_64), .A2(net_40) );
NAND4_X2 inst_70 ( .ZN(net_233), .A2(net_225), .A4(net_224), .A1(net_223), .A3(net_179) );
NAND2_X2 inst_129 ( .ZN(net_124), .A2(net_123), .A1(net_96) );
NAND2_X4 inst_92 ( .A2(net_244), .ZN(net_65), .A1(net_38) );
INV_X4 inst_189 ( .A(net_57), .ZN(net_47) );
INV_X2 inst_223 ( .ZN(net_3), .A(cnt591) );
NOR4_X2 inst_11 ( .ZN(net_215), .A4(net_183), .A1(net_176), .A2(net_145), .A3(net_119) );
INV_X4 inst_188 ( .ZN(net_75), .A(net_23) );
NOR3_X2 inst_14 ( .A2(net_173), .ZN(net_132), .A1(net_131), .A3(net_98) );
NOR2_X2 inst_31 ( .A2(net_262), .ZN(net_41), .A1(net_23) );
INV_X2 inst_252 ( .ZN(net_176), .A(net_175) );
NAND2_X2 inst_158 ( .A1(net_257), .ZN(net_227), .A2(net_199) );
NAND2_X2 inst_141 ( .ZN(net_174), .A2(net_172), .A1(net_149) );
NOR2_X1 inst_62 ( .A1(net_238), .ZN(net_53), .A2(net_27) );
INV_X4 inst_200 ( .A(net_49), .ZN(net_48) );
INV_X2 inst_251 ( .ZN(net_175), .A(net_159) );
CLKBUF_X2 inst_286 ( .A(net_278), .Z(net_279) );
NOR2_X2 inst_57 ( .ZN(net_210), .A2(net_195), .A1(net_152) );
NAND2_X2 inst_102 ( .A2(net_261), .A1(net_260), .ZN(net_44) );
NOR2_X2 inst_32 ( .ZN(net_30), .A2(net_29), .A1(john) );
NAND2_X2 inst_144 ( .ZN(net_184), .A2(net_183), .A1(net_159) );
INV_X4 inst_195 ( .A(net_44), .ZN(net_35) );
NOR2_X4 inst_21 ( .A1(net_261), .A2(net_260), .ZN(net_38) );
CLKBUF_X2 inst_281 ( .A(net_272), .Z(net_274) );
NAND2_X4 inst_97 ( .ZN(net_255), .A1(net_120), .A2(net_96) );
NAND2_X2 inst_124 ( .ZN(net_256), .A1(net_104), .A2(net_63) );
NOR3_X2 inst_18 ( .ZN(net_243), .A1(net_164), .A3(net_162), .A2(net_61) );
INV_X4 inst_208 ( .ZN(net_87), .A(net_78) );
NAND3_X2 inst_88 ( .A3(net_240), .A1(net_239), .ZN(net_236), .A2(net_210) );
INV_X2 inst_220 ( .ZN(net_0), .A(cnt21) );
OR2_X2 inst_9 ( .ZN(net_179), .A1(net_178), .A2(net_170) );
NAND2_X2 inst_113 ( .A2(net_173), .A1(net_102), .ZN(net_72) );
INV_X4 inst_198 ( .ZN(net_207), .A(net_49) );
NOR2_X2 inst_50 ( .A1(net_149), .ZN(net_145), .A2(net_144) );
NAND2_X2 inst_137 ( .ZN(net_158), .A2(net_157), .A1(net_96) );
INV_X2 inst_245 ( .A(net_225), .ZN(net_103) );
NAND2_X2 inst_130 ( .A2(net_186), .ZN(net_126), .A1(net_125) );
INV_X2 inst_227 ( .ZN(net_6), .A(pcnt12) );
INV_X2 inst_226 ( .ZN(net_5), .A(pcnt17) );
DFFR_X2 inst_260 ( .QN(net_259), .D(net_236), .RN(net_235), .CK(net_273) );
INV_X4 inst_176 ( .A(net_13), .ZN(net_10) );
NOR2_X2 inst_58 ( .ZN(net_217), .A1(net_192), .A2(net_191) );
NAND2_X2 inst_147 ( .ZN(net_190), .A2(net_146), .A1(net_144) );
NAND3_X2 inst_87 ( .ZN(net_232), .A3(net_221), .A1(net_203), .A2(net_134) );
NOR2_X2 inst_61 ( .A1(net_241), .ZN(net_230), .A2(net_96) );
INV_X4 inst_203 ( .ZN(net_137), .A(net_75) );
INV_X4 inst_212 ( .ZN(net_131), .A(net_87) );
INV_X2 inst_234 ( .ZN(net_51), .A(net_50) );
OR3_X2 inst_0 ( .ZN(net_219), .A1(net_207), .A2(net_175), .A3(net_125) );
INV_X4 inst_184 ( .ZN(net_37), .A(net_26) );
INV_X2 inst_236 ( .A(net_68), .ZN(net_56) );
NOR4_X2 inst_10 ( .A3(net_199), .ZN(net_195), .A2(net_163), .A4(net_45), .A1(net_30) );
OR2_X2 inst_4 ( .ZN(net_91), .A2(net_90), .A1(net_52) );
NOR2_X1 inst_65 ( .A2(net_219), .A1(net_186), .ZN(csm) );
NOR2_X2 inst_28 ( .ZN(net_17), .A1(net_4), .A2(pcnt241) );
INV_X2 inst_242 ( .ZN(net_81), .A(net_80) );
CLKBUF_X2 inst_275 ( .A(net_267), .Z(net_268) );
NAND2_X2 inst_117 ( .ZN(net_89), .A2(net_88), .A1(net_16) );
NAND2_X4 inst_98 ( .ZN(net_251), .A1(net_249), .A2(cnt10) );
AND3_X2 inst_263 ( .ZN(net_117), .A1(net_116), .A2(net_96), .A3(net_88) );
INV_X4 inst_190 ( .ZN(net_100), .A(net_31) );
INV_X4 inst_204 ( .ZN(net_149), .A(net_75) );
INV_X4 inst_185 ( .ZN(net_25), .A(net_24) );
NOR2_X2 inst_49 ( .ZN(net_200), .A1(net_84), .A2(net_75) );
NAND2_X2 inst_154 ( .ZN(net_203), .A2(net_180), .A1(net_49) );
NOR3_X2 inst_13 ( .ZN(net_157), .A3(net_78), .A1(net_29), .A2(net_19) );
NAND3_X2 inst_75 ( .ZN(net_106), .A1(net_105), .A3(net_104), .A2(cnt509) );
INV_X4 inst_166 ( .ZN(net_253), .A(cnt45) );
NAND2_X2 inst_116 ( .ZN(net_129), .A2(net_53), .A1(net_52) );
INV_X8 inst_163 ( .A(net_261), .ZN(net_26) );
NOR2_X2 inst_54 ( .A2(net_172), .ZN(net_166), .A1(net_133) );
NAND3_X2 inst_79 ( .A1(net_246), .ZN(net_198), .A2(pcnt6), .A3(cnt284) );
NAND2_X2 inst_109 ( .ZN(net_127), .A1(net_52), .A2(net_41) );
NAND2_X2 inst_106 ( .A1(net_238), .ZN(net_39), .A2(net_38) );
INV_X2 inst_219 ( .A(net_249), .ZN(net_248) );
INV_X4 inst_201 ( .ZN(net_168), .A(net_49) );
NOR2_X2 inst_43 ( .A2(net_258), .ZN(net_95), .A1(net_64) );
DFFR_X2 inst_255 ( .QN(net_262), .RN(net_235), .D(net_222), .CK(net_283) );
NAND2_X2 inst_128 ( .ZN(net_114), .A2(net_80), .A1(cnt567) );
NAND3_X2 inst_73 ( .ZN(net_73), .A3(net_40), .A1(net_25), .A2(cnt21) );
DFFR_X2 inst_256 ( .QN(net_237), .RN(net_235), .D(net_229), .CK(net_279) );
NOR2_X4 inst_23 ( .ZN(net_70), .A1(net_44), .A2(net_43) );
NAND2_X4 inst_94 ( .ZN(net_225), .A1(net_178), .A2(net_47) );
AND3_X4 inst_262 ( .ZN(net_226), .A2(net_225), .A3(net_206), .A1(net_201) );
INV_X2 inst_243 ( .ZN(net_93), .A(net_92) );
CLKBUF_X2 inst_285 ( .A(net_277), .Z(net_278) );
NOR3_X2 inst_15 ( .ZN(net_150), .A2(net_149), .A3(net_116), .A1(net_48) );
INV_X4 inst_218 ( .ZN(net_231), .A(net_227) );
INV_X4 inst_197 ( .A(net_49), .ZN(net_42) );
INV_X2 inst_250 ( .A(net_172), .ZN(net_122) );
INV_X4 inst_179 ( .A(net_238), .ZN(net_29) );
NOR2_X4 inst_24 ( .ZN(net_46), .A1(net_37), .A2(net_11) );
OR2_X2 inst_6 ( .ZN(net_155), .A1(net_154), .A2(net_153) );
NAND2_X2 inst_114 ( .ZN(net_92), .A1(net_75), .A2(net_74) );
INV_X4 inst_194 ( .A(net_98), .ZN(net_54) );
NAND3_X2 inst_76 ( .A2(net_192), .ZN(net_134), .A1(net_133), .A3(net_111) );
NAND2_X2 inst_150 ( .A2(net_256), .A1(net_255), .ZN(net_247) );
INV_X4 inst_172 ( .A(net_79), .ZN(net_8) );
CLKBUF_X2 inst_277 ( .A(net_269), .Z(net_270) );
NAND3_X2 inst_83 ( .ZN(net_214), .A3(net_213), .A1(net_174), .A2(net_102) );
NAND2_X2 inst_121 ( .ZN(net_101), .A2(net_100), .A1(net_86) );
NAND2_X2 inst_123 ( .ZN(net_163), .A2(net_107), .A1(net_52) );
OR3_X1 inst_2 ( .A1(net_216), .A3(net_212), .A2(net_143), .ZN(cclr) );
NAND3_X2 inst_86 ( .A2(net_219), .A1(net_194), .A3(net_171), .ZN(cblank) );
NAND2_X2 inst_118 ( .ZN(net_113), .A2(net_70), .A1(net_7) );
NOR2_X4 inst_20 ( .A1(net_260), .ZN(net_98), .A2(net_21) );
NAND2_X2 inst_153 ( .ZN(net_202), .A2(net_200), .A1(net_42) );
NOR2_X2 inst_38 ( .ZN(net_154), .A1(net_74), .A2(net_36) );
NOR2_X2 inst_52 ( .A2(net_248), .ZN(net_162), .A1(net_17) );
NAND2_X4 inst_90 ( .A1(net_250), .A2(net_238), .ZN(net_43) );
AND2_X4 inst_267 ( .ZN(net_59), .A1(net_57), .A2(net_3) );
NAND2_X2 inst_140 ( .ZN(net_213), .A1(net_173), .A2(net_172) );
INV_X4 inst_209 ( .ZN(net_111), .A(net_76) );
DFFR_X2 inst_259 ( .QN(net_260), .RN(net_235), .D(net_234), .CK(net_270) );
INV_X2 inst_221 ( .ZN(net_1), .A(cnt567) );
NOR2_X2 inst_40 ( .ZN(net_123), .A2(net_39), .A1(net_23) );
INV_X4 inst_167 ( .A(net_262), .ZN(net_79) );
INV_X2 inst_246 ( .A(net_131), .ZN(net_110) );
CLKBUF_X2 inst_289 ( .A(net_281), .Z(net_282) );
NAND2_X4 inst_95 ( .A2(net_186), .ZN(net_142), .A1(net_46) );
OR3_X1 inst_1 ( .A3(net_212), .A2(net_182), .A1(net_166), .ZN(pc) );
CLKBUF_X2 inst_282 ( .A(net_274), .Z(net_275) );
NAND4_X2 inst_72 ( .A4(net_243), .A1(net_242), .ZN(net_234), .A2(net_205), .A3(net_112) );
NOR2_X2 inst_44 ( .ZN(net_97), .A2(net_96), .A1(net_76) );
CLKBUF_X2 inst_274 ( .A(net_266), .Z(net_267) );
INV_X4 inst_174 ( .ZN(net_244), .A(net_13) );
NAND2_X2 inst_115 ( .A1(net_96), .ZN(net_82), .A2(net_56) );
INV_X2 inst_235 ( .ZN(net_55), .A(net_54) );
INV_X4 inst_210 ( .A(net_86), .ZN(net_84) );
INV_X8 inst_164 ( .ZN(net_57), .A(net_26) );
OR2_X2 inst_5 ( .A2(net_127), .ZN(net_94), .A1(net_68) );
CLKBUF_X2 inst_278 ( .A(net_264), .Z(net_271) );
NAND2_X2 inst_157 ( .A2(net_208), .A1(net_94), .ZN(pclr) );
INV_X2 inst_239 ( .A(net_127), .ZN(net_69) );
NAND2_X2 inst_105 ( .ZN(net_62), .A2(net_37), .A1(net_31) );
NAND4_X2 inst_68 ( .ZN(net_222), .A4(net_193), .A2(net_169), .A1(net_160), .A3(net_156) );
INV_X4 inst_213 ( .ZN(net_172), .A(net_99) );
NOR2_X2 inst_53 ( .ZN(net_164), .A2(net_163), .A1(cnt13) );
INV_X4 inst_175 ( .ZN(net_96), .A(net_79) );
INV_X4 inst_205 ( .ZN(net_80), .A(net_64) );
INV_X1 inst_254 ( .ZN(net_107), .A(net_65) );
INV_X2 inst_225 ( .ZN(net_258), .A(cnt283) );
NAND2_X2 inst_133 ( .A2(net_249), .ZN(net_136), .A1(cnt511) );
NAND2_X2 inst_112 ( .ZN(net_116), .A1(net_68), .A2(net_44) );
NAND4_X2 inst_67 ( .ZN(net_221), .A3(net_213), .A4(net_189), .A2(net_115), .A1(net_72) );
INV_X4 inst_181 ( .ZN(net_245), .A(net_23) );
NAND2_X2 inst_127 ( .ZN(net_112), .A1(net_111), .A2(net_69) );
NOR2_X2 inst_29 ( .ZN(net_18), .A1(net_1), .A2(pcnt27) );
INV_X4 inst_186 ( .ZN(net_173), .A(net_29) );
NOR3_X2 inst_17 ( .ZN(net_205), .A2(net_138), .A3(net_135), .A1(net_132) );
NAND2_X2 inst_146 ( .ZN(net_189), .A2(net_139), .A1(net_100) );
INV_X2 inst_249 ( .ZN(net_119), .A(net_118) );
INV_X4 inst_202 ( .ZN(net_144), .A(net_102) );
INV_X4 inst_187 ( .ZN(net_27), .A(net_26) );
INV_X4 inst_206 ( .ZN(net_86), .A(net_52) );
NAND2_X2 inst_122 ( .ZN(net_170), .A1(net_102), .A2(net_87) );
NAND2_X2 inst_126 ( .ZN(net_109), .A2(net_107), .A1(net_28) );
NOR2_X4 inst_25 ( .ZN(net_105), .A2(net_60), .A1(net_50) );
INV_X2 inst_240 ( .ZN(net_71), .A(net_70) );
NAND2_X2 inst_110 ( .A1(net_260), .ZN(net_90), .A2(net_41) );
NAND3_X2 inst_74 ( .ZN(net_83), .A1(net_66), .A3(net_35), .A2(cnt45) );
CLKBUF_X2 inst_288 ( .A(net_280), .Z(net_281) );
INV_X2 inst_229 ( .A(net_260), .ZN(net_19) );
NAND2_X4 inst_99 ( .A1(net_247), .ZN(net_211), .A2(cnt44) );
NOR2_X2 inst_35 ( .ZN(net_178), .A2(net_79), .A1(net_52) );
NAND4_X2 inst_69 ( .ZN(net_229), .A4(net_214), .A2(net_202), .A3(net_190), .A1(net_184) );
NOR2_X2 inst_48 ( .A2(net_225), .ZN(net_138), .A1(net_137) );
NAND3_X2 inst_82 ( .ZN(net_257), .A1(net_198), .A2(net_136), .A3(net_114) );
NOR2_X2 inst_46 ( .ZN(net_153), .A2(net_116), .A1(net_79) );
NOR2_X2 inst_30 ( .ZN(net_20), .A2(net_12), .A1(net_2) );
NAND2_X2 inst_136 ( .ZN(net_156), .A1(net_149), .A2(net_108) );
NAND2_X2 inst_108 ( .A1(net_238), .ZN(net_66), .A2(net_22) );
INV_X2 inst_233 ( .A(net_43), .ZN(net_36) );
INV_X4 inst_165 ( .A(net_259), .ZN(net_13) );
CLKBUF_X2 inst_271 ( .A(net_263), .Z(net_264) );
CLKBUF_X2 inst_283 ( .A(net_272), .Z(net_276) );
NOR2_X4 inst_22 ( .A1(net_260), .ZN(net_31), .A2(net_13) );
NOR2_X2 inst_34 ( .ZN(net_45), .A2(net_20), .A1(cnt10) );
NOR3_X4 inst_12 ( .ZN(net_241), .A1(net_204), .A3(net_148), .A2(net_95) );
NAND4_X2 inst_71 ( .A2(net_226), .A4(net_188), .A1(net_124), .A3(net_90), .ZN(csync) );
NOR2_X2 inst_56 ( .ZN(net_240), .A2(net_187), .A1(net_117) );
NAND2_X2 inst_104 ( .A2(net_238), .ZN(net_28), .A1(cnt13) );
NOR2_X2 inst_60 ( .ZN(net_242), .A2(net_220), .A1(net_121) );
INV_X4 inst_168 ( .A(net_237), .ZN(net_11) );
INV_X4 inst_169 ( .ZN(net_250), .A(net_11) );
INV_X4 inst_215 ( .A(net_149), .ZN(net_140) );
NAND2_X1 inst_161 ( .ZN(net_139), .A2(net_99), .A1(net_74) );
NOR3_X2 inst_16 ( .ZN(net_152), .A3(net_129), .A1(net_92), .A2(cnt261) );
CLKBUF_X2 inst_276 ( .A(net_268), .Z(net_269) );
OR2_X4 inst_3 ( .A2(net_262), .ZN(net_22), .A1(net_21) );
NAND2_X2 inst_156 ( .ZN(net_209), .A2(net_165), .A1(net_137) );
INV_X4 inst_170 ( .A(net_79), .ZN(net_7) );
DFFR_X2 inst_258 ( .QN(net_261), .RN(net_235), .D(net_233), .CK(net_265) );
NOR2_X2 inst_41 ( .ZN(net_85), .A2(net_59), .A1(net_58) );
INV_X4 inst_199 ( .ZN(net_76), .A(net_47) );
NAND2_X4 inst_91 ( .A2(net_260), .ZN(net_50), .A1(net_26) );
NAND2_X2 inst_132 ( .ZN(net_130), .A1(net_129), .A2(net_113) );
NAND2_X2 inst_143 ( .ZN(net_180), .A2(net_101), .A1(net_32) );
NOR2_X2 inst_36 ( .ZN(net_58), .A1(net_57), .A2(cnt272) );
NAND2_X2 inst_152 ( .ZN(net_201), .A1(net_200), .A2(net_199) );
AND2_X4 inst_265 ( .A2(net_260), .ZN(net_186), .A1(net_14) );
NAND2_X4 inst_96 ( .A2(net_254), .ZN(net_252), .A1(net_105) );
NOR2_X2 inst_45 ( .A2(net_199), .ZN(net_183), .A1(net_111) );
NAND2_X2 inst_101 ( .ZN(net_16), .A2(net_5), .A1(cnt284) );
AND2_X2 inst_269 ( .ZN(net_161), .A2(net_109), .A1(net_77) );
INV_X2 inst_238 ( .ZN(net_67), .A(net_66) );
AND4_X2 inst_261 ( .ZN(net_187), .A3(net_186), .A2(net_178), .A1(net_173), .A4(net_85) );
INV_X4 inst_178 ( .A(net_60), .ZN(net_24) );
NAND3_X1 inst_89 ( .A1(net_215), .A3(net_126), .A2(net_82), .ZN(vsync) );
NAND2_X2 inst_111 ( .A1(net_173), .ZN(net_133), .A2(net_54) );
NAND4_X2 inst_66 ( .ZN(net_216), .A3(net_181), .A2(net_177), .A1(net_151), .A4(net_131) );
AND2_X2 inst_268 ( .ZN(net_121), .A2(net_120), .A1(net_15) );
OR2_X2 inst_7 ( .ZN(net_169), .A1(net_168), .A2(net_167) );
NOR2_X1 inst_63 ( .A1(net_207), .ZN(net_143), .A2(net_142) );
INV_X4 inst_182 ( .ZN(net_74), .A(net_19) );
CLKBUF_X2 inst_273 ( .A(net_265), .Z(net_266) );
NAND2_X2 inst_120 ( .ZN(net_167), .A1(net_111), .A2(net_98) );
NAND2_X2 inst_119 ( .A1(net_238), .ZN(net_118), .A2(net_51) );
CLKBUF_X2 inst_284 ( .A(net_276), .Z(net_277) );
INV_X2 inst_222 ( .ZN(net_2), .A(john) );
INV_X4 inst_192 ( .A(net_74), .ZN(net_33) );
CLKBUF_X2 inst_280 ( .A(net_272), .Z(net_273) );
NAND3_X2 inst_85 ( .ZN(net_220), .A3(net_196), .A2(net_185), .A1(net_91) );
AND2_X4 inst_266 ( .A2(net_238), .ZN(net_199), .A1(net_8) );
NAND2_X2 inst_149 ( .ZN(net_196), .A2(net_130), .A1(net_23) );
INV_X4 inst_193 ( .ZN(net_181), .A(net_41) );
NOR2_X2 inst_39 ( .ZN(net_99), .A1(net_79), .A2(net_78) );
INV_X2 inst_230 ( .ZN(net_68), .A(net_38) );
INV_X4 inst_217 ( .ZN(net_224), .A(net_218) );
NAND3_X2 inst_77 ( .ZN(net_185), .A3(net_123), .A2(net_52), .A1(net_9) );
INV_X4 inst_171 ( .ZN(net_21), .A(net_11) );
endmodule
|
module c17 (
nx1,
nx7,
nx3,
nx2,
nx6,
nx23,
nx22);
// Start PIs
input nx1;
input nx7;
input nx3;
input nx2;
input nx6;
// Start POs
output nx23;
output nx22;
// Start wires
wire net_1;
wire nx23;
wire nx1;
wire nx7;
wire nx3;
wire net_2;
wire nx22;
wire nx6;
wire net_0;
wire net_3;
wire nx2;
// Start cells
NAND2_X1 inst_5 ( .A2(net_3), .A1(net_0), .ZN(nx22) );
NAND2_X1 inst_2 ( .ZN(net_2), .A2(net_1), .A1(nx7) );
NAND2_X1 inst_1 ( .ZN(net_0), .A2(nx3), .A1(nx1) );
NAND2_X1 inst_4 ( .A1(net_3), .A2(net_2), .ZN(nx23) );
NAND2_X1 inst_3 ( .ZN(net_3), .A2(net_1), .A1(nx2) );
NAND2_X1 inst_0 ( .ZN(net_1), .A2(nx6), .A1(nx3) );
endmodule
|
module c880 (
n201gat,
n189gat,
n17gat,
n72gat,
n152gat,
n255gat,
n159gat,
n85gat,
n267gat,
n87gat,
n116gat,
n74gat,
n55gat,
n90gat,
n210gat,
n96gat,
n228gat,
n260gat,
n143gat,
n80gat,
n207gat,
n153gat,
n268gat,
n171gat,
n1gat,
n135gat,
n111gat,
n237gat,
n183gat,
n130gat,
n29gat,
n261gat,
n101gat,
n59gat,
n138gat,
n149gat,
n195gat,
n86gat,
n177gat,
n219gat,
n42gat,
n121gat,
n146gat,
n91gat,
n26gat,
n156gat,
n68gat,
n13gat,
n246gat,
n8gat,
n75gat,
n73gat,
n36gat,
n88gat,
n126gat,
n106gat,
n165gat,
n259gat,
n89gat,
n51gat,
n420gat,
n389gat,
n879gat,
n865gat,
n850gat,
n446gat,
n767gat,
n390gat,
n874gat,
n864gat,
n768gat,
n421gat,
n863gat,
n419gat,
n388gat,
n449gat,
n450gat,
n880gat,
n423gat,
n866gat,
n447gat,
n391gat,
n448gat,
n878gat,
n418gat,
n422gat);
// Start PIs
input n201gat;
input n189gat;
input n17gat;
input n72gat;
input n152gat;
input n255gat;
input n159gat;
input n85gat;
input n267gat;
input n87gat;
input n116gat;
input n74gat;
input n55gat;
input n90gat;
input n210gat;
input n96gat;
input n228gat;
input n260gat;
input n143gat;
input n80gat;
input n207gat;
input n153gat;
input n268gat;
input n171gat;
input n1gat;
input n135gat;
input n111gat;
input n237gat;
input n183gat;
input n130gat;
input n29gat;
input n261gat;
input n101gat;
input n59gat;
input n138gat;
input n149gat;
input n195gat;
input n86gat;
input n177gat;
input n219gat;
input n42gat;
input n121gat;
input n146gat;
input n91gat;
input n26gat;
input n156gat;
input n68gat;
input n13gat;
input n246gat;
input n8gat;
input n75gat;
input n73gat;
input n36gat;
input n88gat;
input n126gat;
input n106gat;
input n165gat;
input n259gat;
input n89gat;
input n51gat;
// Start POs
output n420gat;
output n389gat;
output n879gat;
output n865gat;
output n850gat;
output n446gat;
output n767gat;
output n390gat;
output n874gat;
output n864gat;
output n768gat;
output n421gat;
output n863gat;
output n419gat;
output n388gat;
output n449gat;
output n450gat;
output n880gat;
output n423gat;
output n866gat;
output n447gat;
output n391gat;
output n448gat;
output n878gat;
output n418gat;
output n422gat;
// Start wires
wire net_47;
wire net_176;
wire net_137;
wire n159gat;
wire net_132;
wire net_54;
wire n768gat;
wire net_105;
wire n419gat;
wire net_129;
wire net_119;
wire net_98;
wire net_12;
wire net_151;
wire net_53;
wire net_93;
wire net_168;
wire net_127;
wire net_76;
wire net_101;
wire net_187;
wire net_111;
wire net_90;
wire n26gat;
wire net_100;
wire net_85;
wire net_124;
wire net_160;
wire net_115;
wire n878gat;
wire net_4;
wire net_17;
wire n51gat;
wire n865gat;
wire n17gat;
wire net_164;
wire net_87;
wire net_0;
wire net_35;
wire n87gat;
wire net_16;
wire n74gat;
wire net_193;
wire net_157;
wire n260gat;
wire net_42;
wire net_120;
wire net_109;
wire net_80;
wire net_65;
wire net_50;
wire n183gat;
wire n130gat;
wire net_96;
wire net_66;
wire net_38;
wire n446gat;
wire net_167;
wire net_136;
wire net_19;
wire n177gat;
wire net_126;
wire n91gat;
wire net_34;
wire net_108;
wire net_183;
wire n88gat;
wire net_150;
wire net_63;
wire n879gat;
wire n255gat;
wire net_30;
wire net_189;
wire net_99;
wire net_24;
wire net_186;
wire net_46;
wire net_118;
wire n55gat;
wire net_146;
wire n96gat;
wire net_122;
wire n143gat;
wire net_7;
wire n111gat;
wire net_172;
wire net_52;
wire net_165;
wire net_13;
wire net_94;
wire net_18;
wire net_131;
wire net_114;
wire n126gat;
wire n866gat;
wire net_29;
wire net_149;
wire net_142;
wire net_31;
wire net_36;
wire net_158;
wire n189gat;
wire net_41;
wire net_3;
wire net_154;
wire n388gat;
wire net_28;
wire n153gat;
wire n391gat;
wire n448gat;
wire net_97;
wire net_182;
wire net_192;
wire net_60;
wire n101gat;
wire n59gat;
wire n149gat;
wire net_58;
wire n863gat;
wire net_82;
wire net_64;
wire net_121;
wire net_73;
wire net_177;
wire net_86;
wire net_75;
wire n447gat;
wire n106gat;
wire net_125;
wire net_107;
wire net_166;
wire net_179;
wire n152gat;
wire net_159;
wire n767gat;
wire net_61;
wire net_62;
wire n116gat;
wire net_6;
wire net_23;
wire n90gat;
wire net_117;
wire net_74;
wire n80gat;
wire net_135;
wire net_130;
wire n420gat;
wire net_147;
wire n261gat;
wire net_14;
wire net_26;
wire net_113;
wire n195gat;
wire net_32;
wire n219gat;
wire net_40;
wire n246gat;
wire n13gat;
wire n8gat;
wire net_69;
wire net_161;
wire net_141;
wire net_83;
wire net_95;
wire net_173;
wire n389gat;
wire n850gat;
wire net_78;
wire net_27;
wire n72gat;
wire net_56;
wire n874gat;
wire net_155;
wire net_191;
wire net_22;
wire net_181;
wire net_39;
wire n228gat;
wire net_2;
wire net_102;
wire net_144;
wire net_9;
wire net_59;
wire n207gat;
wire n268gat;
wire net_162;
wire net_44;
wire net_134;
wire n421gat;
wire net_45;
wire net_89;
wire n146gat;
wire n156gat;
wire net_185;
wire n75gat;
wire n450gat;
wire net_178;
wire n165gat;
wire n418gat;
wire n89gat;
wire net_152;
wire net_116;
wire n390gat;
wire net_175;
wire net_91;
wire net_55;
wire net_106;
wire net_140;
wire n449gat;
wire n210gat;
wire net_104;
wire net_148;
wire n880gat;
wire net_72;
wire net_25;
wire net_70;
wire n171gat;
wire net_194;
wire net_5;
wire net_128;
wire net_138;
wire net_184;
wire net_11;
wire n68gat;
wire n73gat;
wire n36gat;
wire net_123;
wire net_170;
wire net_68;
wire net_77;
wire net_20;
wire net_49;
wire n201gat;
wire net_15;
wire net_57;
wire n85gat;
wire net_71;
wire n267gat;
wire net_153;
wire net_156;
wire net_84;
wire net_174;
wire net_1;
wire net_92;
wire net_112;
wire net_103;
wire net_139;
wire n423gat;
wire net_43;
wire net_10;
wire net_180;
wire net_21;
wire net_169;
wire net_51;
wire net_171;
wire net_79;
wire n135gat;
wire n1gat;
wire n422gat;
wire n237gat;
wire net_143;
wire net_190;
wire n29gat;
wire net_88;
wire net_145;
wire n138gat;
wire n864gat;
wire net_81;
wire net_163;
wire n86gat;
wire net_67;
wire n121gat;
wire n42gat;
wire net_37;
wire net_188;
wire net_110;
wire net_33;
wire net_48;
wire net_8;
wire net_133;
wire n259gat;
// Start cells
NAND2_X1 inst_145 ( .ZN(net_126), .A2(net_97), .A1(n165gat) );
NAND2_X1 inst_103 ( .ZN(net_36), .A2(net_31), .A1(n42gat) );
NAND2_X1 inst_125 ( .ZN(net_73), .A2(net_72), .A1(n153gat) );
AND2_X4 inst_207 ( .ZN(net_28), .A2(n75gat), .A1(n29gat) );
NAND2_X1 inst_138 ( .ZN(net_122), .A2(net_89), .A1(n195gat) );
NAND2_X1 inst_159 ( .ZN(net_147), .A2(net_123), .A1(net_116) );
AND2_X2 inst_218 ( .A2(net_30), .ZN(n450gat), .A1(n89gat) );
XNOR2_X1 inst_15 ( .ZN(net_48), .A(net_39), .B(n207gat) );
AND4_X1 inst_197 ( .ZN(net_178), .A4(net_172), .A1(net_144), .A2(net_118), .A3(net_7) );
NAND2_X1 inst_134 ( .ZN(net_83), .A2(net_81), .A1(n177gat) );
NAND2_X1 inst_179 ( .ZN(net_191), .A2(net_188), .A1(n219gat) );
XNOR2_X1 inst_24 ( .ZN(net_182), .A(net_180), .B(net_156) );
NAND2_X1 inst_114 ( .ZN(net_85), .A2(net_55), .A1(n55gat) );
XNOR2_X1 inst_6 ( .ZN(net_25), .B(n126gat), .A(n121gat) );
AND4_X1 inst_194 ( .ZN(net_167), .A4(net_162), .A1(net_148), .A2(net_142), .A3(net_1) );
NAND2_X1 inst_131 ( .A2(net_81), .ZN(net_79), .A1(n171gat) );
NAND3_X1 inst_76 ( .A1(net_177), .A3(net_101), .A2(net_78), .ZN(n863gat) );
AND2_X4 inst_214 ( .ZN(net_151), .A2(net_123), .A1(n261gat) );
NAND2_X1 inst_180 ( .ZN(net_192), .A2(net_189), .A1(n219gat) );
NAND2_X1 inst_160 ( .A1(net_141), .ZN(net_133), .A2(net_132) );
NAND2_X1 inst_150 ( .ZN(net_103), .A2(net_102), .A1(n246gat) );
OR2_X4 inst_33 ( .A2(net_122), .A1(net_117), .ZN(net_107) );
NAND2_X1 inst_172 ( .ZN(net_176), .A2(net_175), .A1(net_138) );
NAND2_X1 inst_83 ( .ZN(net_2), .A2(n260gat), .A1(n255gat) );
OR2_X4 inst_47 ( .ZN(net_159), .A2(net_151), .A1(net_141) );
XNOR2_X1 inst_19 ( .ZN(net_158), .A(net_147), .B(n261gat) );
NAND2_X1 inst_123 ( .A2(net_72), .ZN(net_70), .A1(n149gat) );
NAND2_X1 inst_121 ( .ZN(net_68), .A2(net_67), .A1(n106gat) );
XNOR2_X1 inst_2 ( .ZN(net_20), .B(n106gat), .A(n101gat) );
XNOR2_X1 inst_8 ( .ZN(net_34), .A(net_33), .B(n42gat) );
NAND2_X1 inst_118 ( .A2(net_67), .ZN(net_64), .A1(n126gat) );
NAND2_X1 inst_86 ( .ZN(net_4), .A1(n210gat), .A2(n106gat) );
NAND2_X1 inst_153 ( .ZN(net_149), .A1(net_122), .A2(net_121) );
XNOR2_X1 inst_20 ( .ZN(net_161), .A(net_159), .B(net_149) );
OR3_X4 inst_27 ( .ZN(net_84), .A3(net_54), .A2(net_33), .A1(n268gat) );
OR2_X4 inst_38 ( .A2(net_128), .ZN(net_118), .A1(net_117) );
NAND2_X1 inst_100 ( .A2(net_27), .ZN(n421gat), .A1(n80gat) );
NOR2_X1 inst_52 ( .ZN(net_42), .A2(net_32), .A1(net_17) );
NAND2_X1 inst_90 ( .ZN(net_7), .A1(n210gat), .A2(n111gat) );
NAND2_X1 inst_140 ( .A2(net_96), .ZN(net_91), .A1(n246gat) );
AND2_X4 inst_209 ( .A2(net_18), .ZN(n447gat), .A1(n51gat) );
AND2_X4 inst_211 ( .ZN(net_52), .A2(net_45), .A1(n59gat) );
OR2_X4 inst_40 ( .ZN(net_131), .A2(net_130), .A1(net_117) );
NAND2_X1 inst_162 ( .ZN(net_142), .A2(net_141), .A1(n237gat) );
NAND2_X1 inst_167 ( .ZN(net_164), .A2(net_161), .A1(n219gat) );
NAND2_X1 inst_93 ( .ZN(net_10), .A2(n259gat), .A1(n255gat) );
NAND2_X1 inst_81 ( .ZN(net_0), .A2(n96gat), .A1(n210gat) );
NAND2_X1 inst_95 ( .ZN(net_12), .A1(n17gat), .A2(n138gat) );
XOR2_X1 inst_1 ( .Z(net_23), .B(n201gat), .A(n195gat) );
NAND3_X1 inst_72 ( .ZN(net_89), .A2(net_85), .A1(net_70), .A3(net_61) );
NAND2_X1 inst_139 ( .ZN(net_128), .A2(net_90), .A1(n189gat) );
NAND2_X1 inst_155 ( .ZN(net_153), .A1(net_126), .A2(net_105) );
NOR2_X1 inst_59 ( .ZN(net_132), .A1(net_119), .A2(net_98) );
NAND2_X1 inst_135 ( .ZN(net_111), .A2(net_86), .A1(n159gat) );
AND4_X1 inst_196 ( .ZN(net_177), .A4(net_171), .A2(net_146), .A1(net_131), .A3(net_4) );
OR2_X4 inst_44 ( .A1(net_154), .ZN(net_146), .A2(net_145) );
NOR2_X1 inst_55 ( .ZN(net_119), .A2(net_90), .A1(n189gat) );
NAND2_X1 inst_174 ( .ZN(net_181), .A2(net_180), .A1(net_124) );
NAND2_X1 inst_115 ( .A2(net_67), .ZN(net_61), .A1(n121gat) );
OR2_X4 inst_37 ( .A1(net_125), .ZN(net_115), .A2(net_114) );
AND2_X4 inst_210 ( .ZN(net_50), .A1(net_15), .A2(n447gat) );
NAND2_X1 inst_148 ( .ZN(net_101), .A2(net_100), .A1(n246gat) );
NAND2_X1 inst_164 ( .ZN(net_160), .A2(net_159), .A1(net_121) );
INV_X1 inst_191 ( .ZN(net_139), .A(net_106) );
XNOR2_X1 inst_5 ( .ZN(net_24), .B(n189gat), .A(n183gat) );
NAND2_X1 inst_157 ( .ZN(net_143), .A1(net_128), .A2(net_99) );
NAND2_X1 inst_84 ( .ZN(net_16), .A2(n8gat), .A1(n1gat) );
NOR2_X1 inst_51 ( .A2(net_32), .A1(net_16), .ZN(n418gat) );
NAND2_X1 inst_142 ( .A2(net_97), .ZN(net_93), .A1(n246gat) );
NAND3_X1 inst_80 ( .A1(net_194), .A3(net_93), .A2(net_80), .ZN(n879gat) );
NAND2_X1 inst_173 ( .ZN(net_179), .A2(net_174), .A1(n219gat) );
NAND2_X1 inst_105 ( .A2(net_42), .A1(net_36), .ZN(n419gat) );
AND2_X4 inst_213 ( .ZN(net_53), .A2(net_52), .A1(n72gat) );
NAND4_X1 inst_68 ( .A2(net_170), .A4(net_87), .A1(net_75), .A3(net_2), .ZN(n865gat) );
AND2_X2 inst_216 ( .ZN(n391gat), .A2(n86gat), .A1(n85gat) );
NAND3_X1 inst_78 ( .A1(net_190), .A3(net_91), .A2(net_79), .ZN(n880gat) );
OR2_X4 inst_42 ( .A1(net_154), .ZN(net_137), .A2(net_136) );
NAND2_X1 inst_175 ( .ZN(net_183), .A2(net_181), .A1(net_125) );
NOR2_X1 inst_53 ( .ZN(net_55), .A2(net_54), .A1(n268gat) );
AND2_X4 inst_205 ( .ZN(net_27), .A1(n59gat), .A2(n36gat) );
NAND2_X1 inst_177 ( .ZN(net_187), .A2(net_186), .A1(net_110) );
INV_X1 inst_183 ( .ZN(net_117), .A(n237gat) );
NAND2_X1 inst_133 ( .ZN(net_82), .A2(net_81), .A1(n159gat) );
XNOR2_X1 inst_26 ( .ZN(net_189), .A(net_183), .B(net_153) );
NAND2_X1 inst_151 ( .ZN(net_134), .A1(net_111), .A2(net_110) );
NAND2_X1 inst_112 ( .ZN(net_59), .A2(net_58), .A1(n153gat) );
NAND4_X1 inst_64 ( .ZN(net_95), .A2(net_84), .A4(net_68), .A1(net_59), .A3(net_6) );
NAND2_X1 inst_107 ( .ZN(net_51), .A2(net_50), .A1(n17gat) );
NAND4_X1 inst_67 ( .A2(net_167), .A4(net_103), .A1(net_77), .A3(net_9), .ZN(n850gat) );
INV_X1 inst_181 ( .ZN(net_154), .A(n228gat) );
NAND2_X1 inst_127 ( .A2(net_81), .ZN(net_75), .A1(n195gat) );
NAND4_X1 inst_70 ( .A2(net_178), .A4(net_88), .A1(net_76), .A3(net_10), .ZN(n864gat) );
INV_X1 inst_186 ( .A(net_36), .ZN(n390gat) );
NAND2_X1 inst_129 ( .A2(net_81), .ZN(net_77), .A1(n201gat) );
NAND2_X1 inst_92 ( .ZN(net_9), .A2(n267gat), .A1(n255gat) );
OR2_X4 inst_29 ( .ZN(net_110), .A2(net_86), .A1(n159gat) );
INV_X1 inst_189 ( .ZN(net_124), .A(net_104) );
XNOR2_X1 inst_17 ( .B(net_48), .A(net_47), .ZN(n768gat) );
XNOR2_X1 inst_11 ( .ZN(net_40), .B(net_26), .A(net_25) );
NAND2_X1 inst_146 ( .ZN(net_106), .A2(net_95), .A1(n177gat) );
INV_X1 inst_188 ( .A(net_119), .ZN(net_99) );
XNOR2_X1 inst_14 ( .ZN(net_47), .A(net_41), .B(n130gat) );
AND3_X4 inst_202 ( .ZN(net_45), .A3(net_37), .A1(n55gat), .A2(n13gat) );
AND2_X4 inst_206 ( .ZN(net_29), .A2(n75gat), .A1(n59gat) );
INV_X1 inst_187 ( .ZN(net_121), .A(net_98) );
NAND2_X1 inst_122 ( .ZN(net_69), .A2(net_67), .A1(n91gat) );
OR2_X4 inst_31 ( .ZN(net_129), .A2(net_100), .A1(n183gat) );
XNOR2_X1 inst_25 ( .ZN(net_188), .A(net_186), .B(net_134) );
NAND2_X1 inst_126 ( .ZN(net_74), .A2(net_72), .A1(n143gat) );
NAND2_X1 inst_158 ( .ZN(net_145), .A1(net_130), .A2(net_129) );
NAND2_X1 inst_141 ( .ZN(net_92), .A2(net_86), .A1(n246gat) );
NAND4_X1 inst_62 ( .ZN(net_96), .A2(net_84), .A4(net_65), .A1(net_56), .A3(net_12) );
AND4_X1 inst_200 ( .ZN(net_193), .A4(net_191), .A2(net_135), .A1(net_112), .A3(net_3) );
NAND2_X1 inst_110 ( .A2(net_58), .ZN(net_56), .A1(n149gat) );
NAND3_X1 inst_74 ( .ZN(net_102), .A3(net_85), .A2(net_73), .A1(net_64) );
NOR2_X1 inst_57 ( .ZN(net_114), .A2(net_97), .A1(n165gat) );
OR2_X4 inst_35 ( .A2(net_126), .A1(net_117), .ZN(net_109) );
NAND2_X1 inst_99 ( .ZN(net_15), .A1(n59gat), .A2(n156gat) );
OR2_X4 inst_48 ( .ZN(net_155), .A1(net_154), .A2(net_153) );
NAND4_X1 inst_69 ( .ZN(net_186), .A4(net_176), .A1(net_140), .A2(net_126), .A3(net_115) );
OR2_X4 inst_46 ( .A1(net_154), .ZN(net_150), .A2(net_149) );
NAND2_X1 inst_82 ( .ZN(net_1), .A1(n210gat), .A2(n121gat) );
NAND2_X1 inst_136 ( .A2(net_89), .ZN(net_87), .A1(n246gat) );
OR2_X4 inst_30 ( .ZN(net_113), .A2(net_95), .A1(n177gat) );
NAND2_X1 inst_102 ( .A2(net_27), .ZN(n422gat), .A1(n42gat) );
NAND2_X1 inst_108 ( .ZN(net_67), .A2(net_44), .A1(net_43) );
NAND2_X1 inst_165 ( .ZN(net_162), .A2(net_158), .A1(n219gat) );
OR2_X4 inst_32 ( .ZN(net_123), .A2(net_102), .A1(n201gat) );
XNOR2_X1 inst_22 ( .ZN(net_169), .A(net_163), .B(net_143) );
NAND2_X1 inst_144 ( .ZN(net_125), .A2(net_96), .A1(n171gat) );
OR2_X4 inst_34 ( .A2(net_125), .A1(net_117), .ZN(net_108) );
XNOR2_X1 inst_12 ( .ZN(net_41), .B(net_22), .A(net_21) );
AND4_X1 inst_195 ( .ZN(net_170), .A4(net_164), .A1(net_150), .A2(net_107), .A3(net_14) );
NOR2_X1 inst_56 ( .ZN(net_104), .A2(net_96), .A1(n171gat) );
NAND3_X1 inst_71 ( .ZN(net_54), .A2(net_28), .A3(n447gat), .A1(n80gat) );
XNOR2_X1 inst_21 ( .ZN(net_168), .A(net_165), .B(net_145) );
NAND2_X1 inst_104 ( .ZN(net_35), .A2(net_29), .A1(n42gat) );
NAND4_X1 inst_60 ( .ZN(net_43), .A3(net_37), .A4(net_35), .A1(n51gat), .A2(n17gat) );
AND2_X4 inst_215 ( .ZN(net_175), .A2(net_173), .A1(net_113) );
NAND2_X1 inst_169 ( .ZN(net_173), .A2(net_166), .A1(net_130) );
NAND2_X1 inst_168 ( .ZN(net_166), .A2(net_165), .A1(net_129) );
NAND2_X1 inst_97 ( .ZN(net_32), .A2(n17gat), .A1(n13gat) );
NAND2_X1 inst_161 ( .ZN(net_140), .A1(net_139), .A2(net_138) );
NAND2_X1 inst_124 ( .A2(net_72), .ZN(net_71), .A1(n146gat) );
XNOR2_X1 inst_18 ( .A(net_49), .B(net_46), .ZN(n767gat) );
XNOR2_X1 inst_16 ( .ZN(net_49), .A(net_40), .B(n135gat) );
AND2_X4 inst_208 ( .ZN(net_31), .A2(n36gat), .A1(n29gat) );
NAND2_X1 inst_88 ( .ZN(net_5), .A2(n91gat), .A1(n210gat) );
AND2_X2 inst_220 ( .A2(net_30), .ZN(n423gat), .A1(n90gat) );
XNOR2_X1 inst_3 ( .ZN(net_21), .B(n165gat), .A(n159gat) );
NAND2_X1 inst_156 ( .A2(net_139), .ZN(net_127), .A1(n237gat) );
XNOR2_X1 inst_9 ( .ZN(net_38), .B(net_20), .A(net_19) );
NAND2_X1 inst_113 ( .ZN(net_60), .A2(net_58), .A1(n143gat) );
NAND2_X1 inst_170 ( .ZN(net_171), .A2(net_168), .A1(n219gat) );
AND4_X1 inst_198 ( .ZN(net_184), .A4(net_179), .A2(net_137), .A1(net_127), .A3(net_13) );
OR2_X4 inst_50 ( .ZN(net_180), .A2(net_175), .A1(net_139) );
NAND2_X1 inst_137 ( .A2(net_90), .ZN(net_88), .A1(n246gat) );
AND4_X1 inst_199 ( .ZN(net_190), .A4(net_185), .A2(net_157), .A1(net_108), .A3(net_0) );
OR2_X4 inst_41 ( .A1(net_154), .ZN(net_135), .A2(net_134) );
NAND2_X1 inst_130 ( .A2(net_81), .ZN(net_78), .A1(n183gat) );
NAND2_X1 inst_91 ( .ZN(net_8), .A1(n8gat), .A2(n138gat) );
NAND2_X1 inst_132 ( .A2(net_81), .ZN(net_80), .A1(n165gat) );
NAND2_X1 inst_143 ( .A2(net_95), .ZN(net_94), .A1(n246gat) );
NAND2_X1 inst_176 ( .ZN(net_185), .A2(net_182), .A1(n219gat) );
NAND2_X1 inst_152 ( .ZN(net_136), .A2(net_113), .A1(net_106) );
NOR2_X1 inst_58 ( .ZN(net_138), .A1(net_114), .A2(net_104) );
OR2_X4 inst_36 ( .A1(net_117), .ZN(net_112), .A2(net_111) );
NAND2_X1 inst_147 ( .ZN(net_130), .A2(net_100), .A1(n183gat) );
NAND2_X1 inst_87 ( .ZN(net_17), .A2(n26gat), .A1(n1gat) );
NAND4_X1 inst_61 ( .ZN(net_44), .A4(net_34), .A2(n447gat), .A3(n59gat), .A1(n156gat) );
AND3_X2 inst_203 ( .A3(net_45), .ZN(n448gat), .A2(n68gat), .A1(n29gat) );
OR2_X4 inst_45 ( .A1(net_154), .ZN(net_148), .A2(net_147) );
NAND2_X1 inst_96 ( .ZN(net_13), .A1(n210gat), .A2(n101gat) );
AND2_X4 inst_212 ( .ZN(net_58), .A2(net_50), .A1(n55gat) );
NAND2_X1 inst_101 ( .A2(net_29), .ZN(n420gat), .A1(n80gat) );
XOR2_X1 inst_0 ( .Z(net_19), .B(n96gat), .A(n91gat) );
INV_X1 inst_184 ( .ZN(net_37), .A(net_16) );
XNOR2_X1 inst_10 ( .ZN(net_39), .B(net_24), .A(net_23) );
XNOR2_X1 inst_4 ( .ZN(net_22), .B(n177gat), .A(n171gat) );
NAND4_X1 inst_65 ( .ZN(net_86), .A2(net_84), .A4(net_69), .A1(net_60), .A3(net_8) );
NAND2_X1 inst_178 ( .A2(net_187), .A1(net_111), .ZN(n866gat) );
NAND2_X1 inst_89 ( .ZN(net_6), .A1(n152gat), .A2(n138gat) );
OR2_X4 inst_28 ( .ZN(net_30), .A2(n88gat), .A1(n87gat) );
NAND2_X1 inst_111 ( .A2(net_58), .ZN(net_57), .A1(n146gat) );
NAND4_X1 inst_66 ( .ZN(net_165), .A4(net_152), .A1(net_133), .A2(net_128), .A3(net_120) );
NAND2_X1 inst_117 ( .A2(net_67), .ZN(net_63), .A1(n111gat) );
NAND2_X1 inst_98 ( .ZN(net_14), .A1(n210gat), .A2(n116gat) );
INV_X1 inst_190 ( .A(net_114), .ZN(net_105) );
NAND4_X1 inst_63 ( .ZN(net_97), .A2(net_84), .A4(net_66), .A1(net_57), .A3(net_11) );
XNOR2_X1 inst_7 ( .ZN(net_26), .B(n116gat), .A(n111gat) );
AND3_X2 inst_204 ( .A3(net_52), .ZN(n449gat), .A1(n74gat), .A2(n68gat) );
INV_X1 inst_185 ( .ZN(net_18), .A(net_17) );
INV_X1 inst_182 ( .ZN(net_33), .A(n17gat) );
OR2_X4 inst_49 ( .ZN(net_157), .A2(net_156), .A1(net_154) );
NAND2_X1 inst_120 ( .A2(net_67), .ZN(net_66), .A1(n96gat) );
NAND2_X1 inst_154 ( .ZN(net_156), .A1(net_125), .A2(net_124) );
XNOR2_X1 inst_13 ( .ZN(net_46), .A(net_38), .B(n130gat) );
NAND2_X1 inst_119 ( .A2(net_67), .ZN(net_65), .A1(n101gat) );
NAND3_X1 inst_75 ( .ZN(net_100), .A3(net_85), .A2(net_74), .A1(net_63) );
INV_X1 inst_192 ( .ZN(net_141), .A(net_116) );
NAND2_X1 inst_166 ( .ZN(net_163), .A2(net_160), .A1(net_122) );
NAND2_X1 inst_116 ( .A2(net_67), .ZN(net_62), .A1(n116gat) );
NAND2_X1 inst_163 ( .ZN(net_152), .A1(net_151), .A2(net_132) );
NAND2_X1 inst_85 ( .ZN(net_3), .A2(n268gat), .A1(n210gat) );
NOR2_X1 inst_54 ( .ZN(net_98), .A2(net_89), .A1(n195gat) );
NAND3_X1 inst_79 ( .A1(net_193), .A3(net_92), .A2(net_82), .ZN(n878gat) );
NAND2_X1 inst_109 ( .ZN(net_72), .A2(net_51), .A1(n1gat) );
NAND2_X1 inst_106 ( .A2(net_42), .ZN(n446gat), .A1(n390gat) );
AND2_X2 inst_219 ( .A2(net_31), .ZN(n389gat), .A1(n80gat) );
AND4_X1 inst_201 ( .ZN(net_194), .A4(net_192), .A2(net_155), .A1(net_109), .A3(net_5) );
AND4_X1 inst_193 ( .ZN(net_81), .A4(net_53), .A1(n73gat), .A3(n68gat), .A2(n42gat) );
NAND2_X1 inst_149 ( .ZN(net_116), .A2(net_102), .A1(n201gat) );
OR2_X4 inst_43 ( .A1(net_154), .ZN(net_144), .A2(net_143) );
OR2_X4 inst_39 ( .A1(net_122), .ZN(net_120), .A2(net_119) );
NAND2_X1 inst_128 ( .A2(net_81), .ZN(net_76), .A1(n189gat) );
NAND3_X1 inst_73 ( .ZN(net_90), .A2(net_85), .A1(net_71), .A3(net_62) );
AND2_X2 inst_217 ( .A2(net_28), .ZN(n388gat), .A1(n42gat) );
XNOR2_X1 inst_23 ( .ZN(net_174), .B(net_173), .A(net_136) );
NAND2_X1 inst_171 ( .ZN(net_172), .A2(net_169), .A1(n219gat) );
NAND3_X1 inst_77 ( .A1(net_184), .A3(net_94), .A2(net_83), .ZN(n874gat) );
NAND2_X1 inst_94 ( .ZN(net_11), .A1(n51gat), .A2(n138gat) );
endmodule
|
module i2c_master_byte_ctrl
(
clk, my_addr, rst, nReset, ena, clk_cnt, start, stop, read, write, ack_in,
din, cmd_ack, ack_out, dout, i2c_busy, i2c_al, scl_i, sl_cont, scl_o,
scl_oen, sda_i, sda_o, sda_oen,slave_dat_req, slave_en, slave_dat_avail,
slave_act, slave_cmd_ack
);
//
// inputs & outputs
//
input clk; // master clock
input [6:0] my_addr; // Slave address input
input rst; // synchronous active high reset
input nReset; // asynchronous active low reset
input ena; // core enable signal
input sl_cont;
input [15:0] clk_cnt; // 4x SCL
// control inputs
input start;
input stop;
input read;
input write;
input ack_in;
input [7:0] din;
// status outputs
output cmd_ack;
reg cmd_ack;
output ack_out;
reg ack_out;
output i2c_busy;
output i2c_al;
output [7:0] dout;
// I2C signals
input scl_i;
output scl_o;
output scl_oen;
input sda_i;
output sda_o;
output sda_oen;
input slave_en;
output reg slave_dat_req;
output reg slave_dat_avail;
output reg slave_act;
output reg slave_cmd_ack;
//
// Variable declarations
//
// statemachine
parameter [9:0] ST_IDLE = 10'b00_0000_0000;
parameter [9:0] ST_START = 10'b00_0000_0001;
parameter [9:0] ST_READ = 10'b00_0000_0010;
parameter [9:0] ST_WRITE = 10'b00_0000_0100;
parameter [9:0] ST_ACK = 10'b00_0000_1000;
parameter [9:0] ST_STOP = 10'b00_0001_0000;
parameter [9:0] ST_SL_ACK = 10'b00_0010_0000;
parameter [9:0] ST_SL_RD = 10'b00_0100_0000;
parameter [9:0] ST_SL_WR = 10'b00_1000_0000;
parameter [9:0] ST_SL_WAIT = 10'b01_0000_0000;
parameter [9:0] ST_SL_PRELOAD = 10'b10_0000_0000;
reg sl_wait;
// signals for bit_controller
wire [6:0] my_addr;
reg [3:0] core_cmd;
reg core_txd;
wire core_ack, core_rxd;
wire sl_cont;
// signals for shift register
reg [7:0] sr; //8bit shift register
reg shift, ld;
reg master_mode;
reg [1:0] slave_cmd_out;
// signals for state machine
wire go;
reg [2:0] dcnt;
wire cnt_done;
wire slave_ack;
wire slave_reset;
//Slave signals
wire slave_adr_received;
wire [7:0] slave_adr;
reg [1:0] slave_cmd;
//
// Module body
//
// hookup bit_controller
i2c_master_bit_ctrl bit_controller (
.clk ( clk ),
.rst ( rst ),
.nReset ( nReset ),
.ena ( ena ),
.clk_cnt ( clk_cnt ),
.cmd ( core_cmd ),
.cmd_ack ( core_ack ),
.busy ( i2c_busy ),
.al ( i2c_al ),
.din ( core_txd ),
.dout ( core_rxd ),
.scl_i ( scl_i ),
.scl_o ( scl_o ),
.scl_oen ( scl_oen ),
.sda_i ( sda_i ),
.sda_o ( sda_o ),
.sda_oen ( sda_oen ),
.slave_adr_received ( slave_adr_received ),
.slave_adr ( slave_adr ),
.master_mode (master_mode),
.cmd_slave_ack (slave_ack),
.slave_cmd (slave_cmd_out),
.sl_wait (sl_wait),
.slave_reset (slave_reset)
);
reg slave_adr_received_d;
// generate go-signal
assign go = (read | write | stop) & ~cmd_ack;
// assign dout output to shift-register
assign dout = sr;
always @(posedge clk or negedge nReset)
if (!nReset)
slave_adr_received_d <= 1'b0;
else
slave_adr_received_d <= slave_adr_received;
// generate shift register
always @(posedge clk or negedge nReset)
if (!nReset)
sr <= 8'h0;
else if (rst)
sr <= 8'h0;
else if (ld)
sr <= din;
else if (shift)
sr <= {sr[6:0], core_rxd};
else if (slave_adr_received_d & slave_act)
sr <= {slave_adr[7:1], 1'b0};
// generate counter
always @(posedge clk or negedge nReset)
if (!nReset)
dcnt <= 3'h0;
else if (rst)
dcnt <= 3'h0;
else if (ld)
dcnt <= 3'h7;
else if (shift)
dcnt <= dcnt - 3'h1;
assign cnt_done = ~(|dcnt);
//
// state machine
//
reg [9:0] c_state; // synopsys enum_state
always @(posedge clk or negedge nReset)
if (!nReset)
begin
sl_wait <= 1'b0;
core_cmd <= `I2C_CMD_NOP;
core_txd <= 1'b0;
shift <= 1'b0;
ld <= 1'b0;
cmd_ack <= 1'b0;
c_state <= ST_IDLE;
ack_out <= 1'b0;
master_mode <= 1'b0;
slave_cmd <= 2'b0;
slave_dat_req <= 1'b0;
slave_dat_avail <= 1'b0;
slave_act <= 1'b0;
slave_cmd_out <= 2'b0;
slave_cmd_ack <= 1'b0;
end
else if (rst | i2c_al | slave_reset)
begin
core_cmd <= `I2C_CMD_NOP;
core_txd <= 1'b0;
shift <= 1'b0;
sl_wait <= 1'b0;
ld <= 1'b0;
cmd_ack <= 1'b0;
c_state <= ST_IDLE;
ack_out <= 1'b0;
master_mode <= 1'b0;
slave_cmd <= 2'b0;
slave_cmd_out <= 2'b0;
slave_dat_req <= 1'b0;
slave_dat_avail <= 1'b0;
slave_act <= 1'b0;
slave_cmd_ack <= 1'b0;
end
else
begin
slave_cmd_out <= slave_cmd;
// initially reset all signals
core_txd <= sr[7];
shift <= 1'b0;
ld <= 1'b0;
cmd_ack <= 1'b0;
slave_cmd_ack <= 1'b0;
case (c_state) // synopsys full_case parallel_case
ST_IDLE:
begin
slave_act <= 1'b0;
if (slave_en & slave_adr_received &
(slave_adr[7:1] == my_addr )) begin
c_state <= ST_SL_ACK;
master_mode <= 1'b0;
slave_act <= 1'b1;
slave_cmd <= `I2C_SLAVE_CMD_WRITE;
core_txd <= 1'b0;
end
else if (go && !slave_act )
begin
if (start)
begin
c_state <= ST_START;
core_cmd <= `I2C_CMD_START;
master_mode <= 1'b1;
end
else if (read)
begin
c_state <= ST_READ;
core_cmd <= `I2C_CMD_READ;
end
else if (write)
begin
c_state <= ST_WRITE;
core_cmd <= `I2C_CMD_WRITE;
end
else // stop
begin
c_state <= ST_STOP;
core_cmd <= `I2C_CMD_STOP;
end
ld <= 1'b1;
end
end
ST_SL_RD: //If master read, slave sending data
begin
slave_cmd <= `I2C_SLAVE_CMD_NOP;
if (slave_ack) begin
if (cnt_done) begin
c_state <= ST_SL_ACK;
slave_cmd <= `I2C_SLAVE_CMD_READ;
end
else
begin
c_state <= ST_SL_RD;
slave_cmd <= `I2C_SLAVE_CMD_WRITE;
shift <= 1'b1;
end
end
end
ST_SL_WR: //If master write, slave reading data
begin
slave_cmd <= `I2C_SLAVE_CMD_NOP;
if (slave_ack)
begin
if (cnt_done)
begin
c_state <= ST_SL_ACK;
slave_cmd <= `I2C_SLAVE_CMD_WRITE;
core_txd <= 1'b0;
end
else
begin
c_state <= ST_SL_WR;
slave_cmd <= `I2C_SLAVE_CMD_READ;
end
shift <= 1'b1;
end
end
ST_SL_WAIT: //Wait for interupt-clear and hold SCL in waitstate
begin
sl_wait <= 1'b1;
if (sl_cont) begin
sl_wait <= 1'b0;
ld <= 1'b1;
slave_dat_req <= 1'b0;
slave_dat_avail <= 1'b0;
c_state <= ST_SL_PRELOAD;
end
end
ST_SL_PRELOAD:
if (slave_adr[0]) begin
c_state <= ST_SL_RD;
slave_cmd <= `I2C_SLAVE_CMD_WRITE;
end
else begin
c_state <= ST_SL_WR;
slave_cmd <= `I2C_SLAVE_CMD_READ;
end
ST_SL_ACK:
begin
slave_cmd <= `I2C_SLAVE_CMD_NOP;
if (slave_ack) begin
ack_out <= core_rxd;
slave_cmd_ack <= 1'b1;
if (!core_rxd) begin // Valid ack recived
// generate slave command acknowledge signal if
// succesful transfer
c_state <= ST_SL_WAIT;
if (slave_adr[0]) begin // I2C read request
slave_dat_req <= 1'b1;
end
else begin // I2C write request
slave_dat_avail <= 1'b1;
end
end
else begin
c_state <= ST_IDLE;
end
end
else begin
core_txd <= 1'b0;
end
end
ST_START:
if (core_ack)
begin
if (read)
begin
c_state <= ST_READ;
core_cmd <= `I2C_CMD_READ;
end
else
begin
c_state <= ST_WRITE;
core_cmd <= `I2C_CMD_WRITE;
end
ld <= 1'b1;
end
ST_WRITE:
if (core_ack)
if (cnt_done)
begin
c_state <= ST_ACK;
core_cmd <= `I2C_CMD_READ;
end
else
begin
c_state <= ST_WRITE; // stay in same state
core_cmd <= `I2C_CMD_WRITE; // write next bit
shift <= 1'b1;
end
ST_READ:
if (core_ack)
begin
if (cnt_done)
begin
c_state <= ST_ACK;
core_cmd <= `I2C_CMD_WRITE;
end
else
begin
c_state <= ST_READ; // stay in same state
core_cmd <= `I2C_CMD_READ; // read next bit
end
shift <= 1'b1;
core_txd <= ack_in;
end
ST_ACK:
if (core_ack)
begin
if (stop)
begin
c_state <= ST_STOP;
core_cmd <= `I2C_CMD_STOP;
end
else
begin
c_state <= ST_IDLE;
core_cmd <= `I2C_CMD_NOP;
// generate command acknowledge signal
cmd_ack <= 1'b1;
end
// assign ack_out output to bit_controller_rxd (contains last received bit)
ack_out <= core_rxd;
core_txd <= 1'b1;
end
else
core_txd <= ack_in;
ST_STOP:
if (core_ack)
begin
c_state <= ST_IDLE;
core_cmd <= `I2C_CMD_NOP;
// generate command acknowledge signal
cmd_ack <= 1'b1;
end
endcase
end
endmodule
|
module i2c_master_bit_ctrl (
input clk, // system clock
input rst, // synchronous active high reset
input nReset, // asynchronous active low reset
input ena, // core enable signal
input [15:0] clk_cnt, // clock prescale value
input [ 3:0] cmd, // command (from byte controller)
output reg cmd_ack, // command complete acknowledge
output reg busy, // i2c bus busy
output reg al, // i2c bus arbitration lost
input din,
output reg dout,
input scl_i, // i2c clock line input
output scl_o, // i2c clock line output
output scl_oen, // i2c clock line output enable (active low)
input sda_i, // i2c data line input
output sda_o, // i2c data line output
output sda_oen, // i2c data line output enable (active low)
output reg slave_adr_received,
output reg [7:0] slave_adr,
input master_mode,
output reg cmd_slave_ack,
input [1:0] slave_cmd ,
input sl_wait,
output slave_reset
);
//
// variable declarations
//
reg [ 1:0] cSCL, cSDA; // capture SCL and SDA
reg [ 2:0] fSCL, fSDA; // SCL and SDA filter inputs
reg sSCL, sSDA; // filtered and synchronized SCL and SDA inputs
reg dSCL, dSDA; // delayed versions of sSCL and sSDA
reg dscl_oen; // delayed scl_oen
reg sda_chk; // check SDA output (Multi-master arbitration)
reg clk_en; // clock generation signals
reg slave_wait; // slave inserts wait states
reg [15:0] cnt; // clock divider counter (synthesis)
reg [13:0] filter_cnt; // clock divider for filter
// state machine variable
reg [17:0] c_state; // synopsys enum_state
reg [4:0] slave_state;
//
// module body
//
// whenever the slave is not ready it can delay the cycle by pulling SCL low
// delay scl_oen
always @(posedge clk)
dscl_oen <= scl_oen;
// slave_wait is asserted when master wants to drive SCL high, but the slave pulls it low
// slave_wait remains asserted until the slave releases SCL
always @(posedge clk or negedge nReset)
if (!nReset) slave_wait <= 1'b0;
else slave_wait <= (scl_oen & ~dscl_oen & ~sSCL) | (slave_wait & ~sSCL);
// master drives SCL high, but another master pulls it low
// master start counting down its low cycle now (clock synchronization)
wire scl_sync = dSCL & ~sSCL & scl_oen;
// generate clk enable signal
always @(posedge clk or negedge nReset)
if (~nReset)
begin
cnt <= 16'h0;
clk_en <= 1'b1;
end
else if (rst || ~|cnt || !ena || scl_sync)
begin
cnt <= clk_cnt;
clk_en <= 1'b1;
end
else if (slave_wait)
begin
cnt <= cnt;
clk_en <= 1'b0;
end
else
begin
cnt <= cnt - 16'h1;
clk_en <= 1'b0;
end
// generate bus status controller
// capture SDA and SCL
// reduce metastability risk
always @(posedge clk or negedge nReset)
if (!nReset)
begin
cSCL <= 2'b00;
cSDA <= 2'b00;
end
else if (rst)
begin
cSCL <= 2'b00;
cSDA <= 2'b00;
end
else
begin
cSCL <= {cSCL[0],scl_i};
cSDA <= {cSDA[0],sda_i};
end
// filter SCL and SDA signals; (attempt to) remove glitches
always @(posedge clk or negedge nReset)
if (!nReset ) filter_cnt <= 14'h0;
else if (rst || !ena ) filter_cnt <= 14'h0;
else if (~|filter_cnt) filter_cnt <= clk_cnt[15:2]; //16x I2C bus frequency
else filter_cnt <= filter_cnt -14'd1;
always @(posedge clk or negedge nReset)
if (!nReset)
begin
fSCL <= 3'b111;
fSDA <= 3'b111;
end
else if (rst)
begin
fSCL <= 3'b111;
fSDA <= 3'b111;
end
else if (~|filter_cnt)
begin
fSCL <= {fSCL[1:0],cSCL[1]};
fSDA <= {fSDA[1:0],cSDA[1]};
end
// generate filtered SCL and SDA signals
always @(posedge clk or negedge nReset)
if (~nReset)
begin
sSCL <= 1'b1;
sSDA <= 1'b1;
dSCL <= 1'b1;
dSDA <= 1'b1;
end
else if (rst)
begin
sSCL <= 1'b1;
sSDA <= 1'b1;
dSCL <= 1'b1;
dSDA <= 1'b1;
end
else
begin
sSCL <= &fSCL[2:1] | &fSCL[1:0] | (fSCL[2] & fSCL[0]);
sSDA <= &fSDA[2:1] | &fSDA[1:0] | (fSDA[2] & fSDA[0]);
dSCL <= sSCL;
dSDA <= sSDA;
end
// detect start condition => detect falling edge on SDA while SCL is high
// detect stop condition => detect rising edge on SDA while SCL is high
reg sta_condition;
reg sto_condition;
always @(posedge clk or negedge nReset)
if (~nReset)
begin
sta_condition <= 1'b0;
sto_condition <= 1'b0;
end
else if (rst)
begin
sta_condition <= 1'b0;
sto_condition <= 1'b0;
end
else
begin
sta_condition <= ~sSDA & dSDA & sSCL;
sto_condition <= sSDA & ~dSDA & sSCL;
end
// generate i2c bus busy signal
always @(posedge clk or negedge nReset)
if (!nReset) busy <= 1'b0;
else if (rst ) busy <= 1'b0;
else busy <= (sta_condition | busy) & ~sto_condition;
// generate arbitration lost signal
// aribitration lost when:
// 1) master drives SDA high, but the i2c bus is low
// 2) stop detected while not requested
reg cmd_stop;
always @(posedge clk or negedge nReset)
if (~nReset)
cmd_stop <= 1'b0;
else if (rst)
cmd_stop <= 1'b0;
else if (clk_en)
cmd_stop <= cmd == `I2C_CMD_STOP;
always @(posedge clk or negedge nReset)
if (~nReset)
al <= 1'b0;
else if (rst)
al <= 1'b0;
else
al <= (sda_chk & ~sSDA & sda_oen) | (|c_state & sto_condition & ~cmd_stop);
// generate dout signal (store SDA on rising edge of SCL)
always @(posedge clk)
if (sSCL & ~dSCL) dout <= sSDA;
// generate statemachine
// nxt_state decoder
parameter [17:0] idle = 18'b0_0000_0000_0000_0000;
parameter [17:0] start_a = 18'b0_0000_0000_0000_0001;
parameter [17:0] start_b = 18'b0_0000_0000_0000_0010;
parameter [17:0] start_c = 18'b0_0000_0000_0000_0100;
parameter [17:0] start_d = 18'b0_0000_0000_0000_1000;
parameter [17:0] start_e = 18'b0_0000_0000_0001_0000;
parameter [17:0] stop_a = 18'b0_0000_0000_0010_0000;
parameter [17:0] stop_b = 18'b0_0000_0000_0100_0000;
parameter [17:0] stop_c = 18'b0_0000_0000_1000_0000;
parameter [17:0] stop_d = 18'b0_0000_0001_0000_0000;
parameter [17:0] rd_a = 18'b0_0000_0010_0000_0000;
parameter [17:0] rd_b = 18'b0_0000_0100_0000_0000;
parameter [17:0] rd_c = 18'b0_0000_1000_0000_0000;
parameter [17:0] rd_d = 18'b0_0001_0000_0000_0000;
parameter [17:0] wr_a = 18'b0_0010_0000_0000_0000;
parameter [17:0] wr_b = 18'b0_0100_0000_0000_0000;
parameter [17:0] wr_c = 18'b0_1000_0000_0000_0000;
parameter [17:0] wr_d = 18'b1_0000_0000_0000_0000;
reg scl_oen_master ;
reg sda_oen_master ;
reg sda_oen_slave;
reg scl_oen_slave;
always @(posedge clk or negedge nReset)
if (!nReset)
begin
c_state <= idle;
cmd_ack <= 1'b0;
scl_oen_master <= 1'b1;
sda_oen_master <= 1'b1;
sda_chk <= 1'b0;
end
else if (rst | al)
begin
c_state <= idle;
cmd_ack <= 1'b0;
scl_oen_master <= 1'b1;
sda_oen_master <= 1'b1;
sda_chk <= 1'b0;
end
else
begin
cmd_ack <= 1'b0; // default no command acknowledge + assert cmd_ack only 1clk cycle
if (clk_en)
case (c_state) // synopsys full_case parallel_case
// idle state
idle:
begin
case (cmd) // synopsys full_case parallel_case
`I2C_CMD_START: c_state <= start_a;
`I2C_CMD_STOP: c_state <= stop_a;
`I2C_CMD_WRITE: c_state <= wr_a;
`I2C_CMD_READ: c_state <= rd_a;
default: c_state <= idle;
endcase
scl_oen_master <= scl_oen_master; // keep SCL in same state
sda_oen_master <= sda_oen_master; // keep SDA in same state
sda_chk <= 1'b0; // don't check SDA output
end
// start
start_a:
begin
c_state <= start_b;
scl_oen_master <= scl_oen_master; // keep SCL in same state
sda_oen_master <= 1'b1; // set SDA high
sda_chk <= 1'b0; // don't check SDA output
end
start_b:
begin
c_state <= start_c;
scl_oen_master <= 1'b1; // set SCL high
sda_oen_master <= 1'b1; // keep SDA high
sda_chk <= 1'b0; // don't check SDA output
end
start_c:
begin
c_state <= start_d;
scl_oen_master <= 1'b1; // keep SCL high
sda_oen_master <= 1'b0; // set SDA low
sda_chk <= 1'b0; // don't check SDA output
end
start_d:
begin
c_state <= start_e;
scl_oen_master <= 1'b1; // keep SCL high
sda_oen_master <= 1'b0; // keep SDA low
sda_chk <= 1'b0; // don't check SDA output
end
start_e:
begin
c_state <= idle;
cmd_ack <= 1'b1;
scl_oen_master <= 1'b0; // set SCL low
sda_oen_master <= 1'b0; // keep SDA low
sda_chk <= 1'b0; // don't check SDA output
end
// stop
stop_a:
begin
c_state <= stop_b;
scl_oen_master <= 1'b0; // keep SCL low
sda_oen_master <= 1'b0; // set SDA low
sda_chk <= 1'b0; // don't check SDA output
end
stop_b:
begin
c_state <= stop_c;
scl_oen_master <= 1'b1; // set SCL high
sda_oen_master <= 1'b0; // keep SDA low
sda_chk <= 1'b0; // don't check SDA output
end
stop_c:
begin
c_state <= stop_d;
scl_oen_master <= 1'b1; // keep SCL high
sda_oen_master <= 1'b0; // keep SDA low
sda_chk <= 1'b0; // don't check SDA output
end
stop_d:
begin
c_state <= idle;
cmd_ack <= 1'b1;
scl_oen_master <= 1'b1; // keep SCL high
sda_oen_master <= 1'b1; // set SDA high
sda_chk <= 1'b0; // don't check SDA output
end
// read
rd_a:
begin
c_state <= rd_b;
scl_oen_master <= 1'b0; // keep SCL low
sda_oen_master <= 1'b1; // tri-state SDA
sda_chk <= 1'b0; // don't check SDA output
end
rd_b:
begin
c_state <= rd_c;
scl_oen_master <= 1'b1; // set SCL high
sda_oen_master <= 1'b1; // keep SDA tri-stated
sda_chk <= 1'b0; // don't check SDA output
end
rd_c:
begin
c_state <= rd_d;
scl_oen_master <= 1'b1; // keep SCL high
sda_oen_master <= 1'b1; // keep SDA tri-stated
sda_chk <= 1'b0; // don't check SDA output
end
rd_d:
begin
c_state <= idle;
cmd_ack <= 1'b1;
scl_oen_master <= 1'b0; // set SCL low
sda_oen_master <= 1'b1; // keep SDA tri-stated
sda_chk <= 1'b0; // don't check SDA output
end
// write
wr_a:
begin
c_state <= wr_b;
scl_oen_master <= 1'b0; // keep SCL low
sda_oen_master <= din; // set SDA
sda_chk <= 1'b0; // don't check SDA output (SCL low)
end
wr_b:
begin
c_state <= wr_c;
scl_oen_master <= 1'b1; // set SCL high
sda_oen_master <= din; // keep SDA
sda_chk <= 1'b0; // don't check SDA output yet
// allow some time for SDA and SCL to settle
end
wr_c:
begin
c_state <= wr_d;
scl_oen_master <= 1'b1; // keep SCL high
sda_oen_master <= din;
sda_chk <= 1'b1; // check SDA output
end
wr_d:
begin
c_state <= idle;
cmd_ack <= 1'b1;
scl_oen_master <= 1'b0; // set SCL low
sda_oen_master <= din;
sda_chk <= 1'b0; // don't check SDA output (SCL low)
end
endcase
end
//----------Addition for slave mode...
reg [3:0] slave_cnt;
//The SCL can only be driven when Master mode
assign sda_oen = master_mode ? sda_oen_master : sda_oen_slave ;
assign scl_oen = master_mode ? scl_oen_master : scl_oen_slave ;
reg slave_act;
reg slave_adr_received_d;
//A 1 cycle pulse slave_adr_recived is generated when a slave adress is recvied after a startcommand.
always @(posedge clk or negedge nReset)
if (!nReset) begin
slave_adr <= 8'h0;
slave_cnt <= 4'h8;
slave_adr_received <= 1'b0;
slave_act <= 1'b0;
end
else begin
slave_adr_received <= 1'b0;
if ((sSCL & ~dSCL) && slave_cnt != 4'h0 && slave_act) begin
slave_adr <= {slave_adr[6:0], sSDA};
slave_cnt <= slave_cnt -4'd1;
end
else if (slave_cnt == 4'h0 && !sta_condition && slave_act) begin
slave_adr_received <= 1'b1;
slave_act <= 1'b0;
end
if (sta_condition) begin
slave_cnt <= 4'h8;
slave_adr <= 8'h0;
slave_adr_received <= 1'b0;
slave_act <= 1'b1;
end
if(sto_condition) begin
slave_adr_received <= 1'b0;
slave_act <= 1'b0;
end
end
parameter [4:0] slave_idle = 5'b0_0000;
parameter [4:0] slave_wr = 5'b0_0001;
parameter [4:0] slave_wr_a = 5'b0_0010;
parameter [4:0] slave_rd = 5'b0_0100;
parameter [4:0] slave_rd_a = 5'b0_1000;
parameter [4:0] slave_wait_next_cmd_1 = 5'b1_0000;
parameter [4:0] slave_wait_next_cmd_2 = 5'b1_0001;
always @(posedge clk or negedge nReset)
if (!nReset)
begin
slave_state <= slave_idle;
cmd_slave_ack <= 1'b0;
sda_oen_slave <= 1'b1;
scl_oen_slave <= 1'b1;
end
else if (rst | sta_condition || !ena)
begin
slave_state <= slave_idle;
cmd_slave_ack <= 1'b0;
sda_oen_slave <= 1'b1;
scl_oen_slave <= 1'b1;
end
else
begin
cmd_slave_ack <= 1'b0; // default no command acknowledge + assert cmd_ack only 1clk cycle
if (sl_wait)
scl_oen_slave <= 1'b0;
else
scl_oen_slave <= 1'b1;
case (slave_state)
slave_idle:
begin
case (slave_cmd) // synopsys full_case parallel_case
`I2C_SLAVE_CMD_WRITE: slave_state <= slave_wr;
`I2C_SLAVE_CMD_READ:
begin
slave_state <= slave_rd;
// Restore SDA high here in case we're got it low
sda_oen_slave <= 1'b1;
end
default:
begin
slave_state <= slave_idle;
sda_oen_slave <= 1'b1; // Moved this here, JB
end
endcase
end
slave_wr:
begin
if (~sSCL & ~dSCL) begin //SCL == LOW
slave_state <= slave_wr_a;
sda_oen_slave <= din;
end
end
slave_wr_a:
begin
if (~sSCL & dSCL) begin //SCL FALLING EDGE
cmd_slave_ack <= 1'b1;
slave_state <= slave_wait_next_cmd_1;
end
end
slave_wait_next_cmd_1:
slave_state <= slave_wait_next_cmd_2;
slave_wait_next_cmd_2:
slave_state <= slave_idle;
slave_rd:
begin
if (sSCL & ~dSCL) begin // SCL Rising edge
slave_state <= slave_rd_a;
end
end
slave_rd_a:
begin
if (~sSCL & dSCL) begin // SCL falling edge
cmd_slave_ack <= 1'b1;
slave_state <= slave_wait_next_cmd_1;
end
end
endcase // case (slave_state)
end
assign slave_reset = sta_condition | sto_condition;
// assign scl and sda output (always gnd)
assign scl_o = 1'b0;
assign sda_o = 1'b0;
endmodule
|
module wb_master_model(clk, rst, adr, din, dout, cyc, stb, we, sel, ack, err, rty);
parameter dwidth = 32;
parameter awidth = 32;
input clk, rst;
output [awidth -1:0] adr;
input [dwidth -1:0] din;
output [dwidth -1:0] dout;
output cyc, stb;
output we;
output [dwidth/8 -1:0] sel;
input ack, err, rty;
////////////////////////////////////////////////////////////////////
//
// Local Wires
//
reg [awidth -1:0] adr;
reg [dwidth -1:0] dout;
reg cyc, stb;
reg we;
reg [dwidth/8 -1:0] sel;
reg [dwidth -1:0] q;
////////////////////////////////////////////////////////////////////
//
// Memory Logic
//
initial
begin
//adr = 32'hxxxx_xxxx;
//adr = 0;
adr = {awidth{1'bx}};
dout = {dwidth{1'bx}};
cyc = 1'b0;
stb = 1'bx;
we = 1'hx;
sel = {dwidth/8{1'bx}};
#1;
$display("\nINFO: WISHBONE MASTER MODEL INSTANTIATED (%m)\n");
end
////////////////////////////////////////////////////////////////////
//
// Wishbone write cycle
//
task wb_write;
input delay;
integer delay;
input [awidth -1:0] a;
input [dwidth -1:0] d;
begin
// wait initial delay
repeat(delay) @(posedge clk);
// assert wishbone signal
#1;
adr = a;
dout = d;
cyc = 1'b1;
stb = 1'b1;
we = 1'b1;
sel = {dwidth/8{1'b1}};
@(posedge clk);
// wait for acknowledge from slave
while(~ack) @(posedge clk);
// negate wishbone signals
#1;
cyc = 1'b0;
stb = 1'bx;
adr = {awidth{1'bx}};
dout = {dwidth{1'bx}};
we = 1'hx;
sel = {dwidth/8{1'bx}};
end
endtask
////////////////////////////////////////////////////////////////////
//
// Wishbone read cycle
//
task wb_read;
input delay;
integer delay;
input [awidth -1:0] a;
output [dwidth -1:0] d;
begin
// wait initial delay
repeat(delay) @(posedge clk);
// assert wishbone signals
#1;
adr = a;
dout = {dwidth{1'bx}};
cyc = 1'b1;
stb = 1'b1;
we = 1'b0;
sel = {dwidth/8{1'b1}};
@(posedge clk);
// wait for acknowledge from slave
while(~ack) @(posedge clk);
// negate wishbone signals
#1;
cyc = 1'b0;
stb = 1'bx;
adr = {awidth{1'bx}};
dout = {dwidth{1'bx}};
we = 1'hx;
sel = {dwidth/8{1'bx}};
d = din;
end
endtask
////////////////////////////////////////////////////////////////////
//
// Wishbone compare cycle (read data from location and compare with expected data)
//
task wb_cmp;
input delay;
integer delay;
input [awidth -1:0] a;
input [dwidth -1:0] d_exp;
begin
wb_read (delay, a, q);
if (d_exp !== q)
$display("Data compare error. Received %h, expected %h at time %t", q, d_exp, $time);
end
endtask
endmodule
|
module i2c_slave_model (scl, sda);
//
// parameters
//
parameter I2C_ADR = 7'b001_0000;
//
// input && outpus
//
input scl;
inout sda;
//
// Variable declaration
//
wire debug = 1'b1;
reg [7:0] mem [3:0]; // initiate memory
reg [7:0] mem_adr; // memory address
reg [7:0] mem_do; // memory data output
reg sta, d_sta;
reg sto, d_sto;
reg [7:0] sr; // 8bit shift register
reg rw; // read/write direction
wire my_adr; // my address called ??
wire i2c_reset; // i2c-statemachine reset
reg [2:0] bit_cnt; // 3bit downcounter
wire acc_done; // 8bits transfered
reg ld; // load downcounter
reg sda_o; // sda-drive level
wire sda_dly; // delayed version of sda
// statemachine declaration
parameter idle = 3'b000;
parameter slave_ack = 3'b001;
parameter get_mem_adr = 3'b010;
parameter gma_ack = 3'b011;
parameter data = 3'b100;
parameter data_ack = 3'b101;
reg [2:0] state; // synopsys enum_state
//
// module body
//
initial
begin
sda_o = 1'b1;
state = idle;
end
// generate shift register
always @(posedge scl)
sr <= #1 {sr[6:0],sda};
//detect my_address
assign my_adr = (sr[7:1] == I2C_ADR);
// FIXME: This should not be a generic assign, but rather
// qualified on address transfer phase and probably reset by stop
//generate bit-counter
always @(posedge scl)
if(ld)
bit_cnt <= #1 3'b111;
else
bit_cnt <= #1 bit_cnt - 3'h1;
//generate access done signal
assign acc_done = !(|bit_cnt);
// generate delayed version of sda
// this model assumes a hold time for sda after the falling edge of scl.
// According to the Phillips i2c spec, there s/b a 0 ns hold time for sda
// with regards to scl. If the data changes coincident with the clock, the
// acknowledge is missed
// Fix by Michael Sosnoski
assign #1 sda_dly = sda;
//detect start condition
always @(negedge sda)
if(scl)
begin
sta <= #1 1'b1;
d_sta <= #1 1'b0;
sto <= #1 1'b0;
if(debug)
$display("DEBUG i2c_slave; start condition detected at %t", $time);
end
else
sta <= #1 1'b0;
always @(posedge scl)
d_sta <= #1 sta;
// detect stop condition
always @(posedge sda)
if(scl)
begin
sta <= #1 1'b0;
sto <= #1 1'b1;
if(debug)
$display("DEBUG i2c_slave; stop condition detected at %t", $time);
end
else
sto <= #1 1'b0;
//generate i2c_reset signal
assign i2c_reset = sta || sto;
// generate statemachine
always @(negedge scl or posedge sto)
if (sto || (sta && !d_sta) )
begin
state <= #1 idle; // reset statemachine
sda_o <= #1 1'b1;
ld <= #1 1'b1;
end
else
begin
// initial settings
sda_o <= #1 1'b1;
ld <= #1 1'b0;
case(state) // synopsys full_case parallel_case
idle: // idle state
if (acc_done && my_adr)
begin
state <= #1 slave_ack;
rw <= #1 sr[0];
sda_o <= #1 1'b0; // generate i2c_ack
#2;
if(debug && rw)
$display("DEBUG i2c_slave; command byte received (read) at %t", $time);
if(debug && !rw)
$display("DEBUG i2c_slave; command byte received (write) at %t", $time);
if(rw)
begin
mem_do <= #1 mem[mem_adr];
if(debug)
begin
#2 $display("DEBUG i2c_slave; data block read %x from address %x (1)", mem_do, mem_adr);
#2 $display("DEBUG i2c_slave; memcheck [0]=%x, [1]=%x, [2]=%x", mem[4'h0], mem[4'h1], mem[4'h2]);
end
end
end
slave_ack:
begin
if(rw)
begin
state <= #1 data;
sda_o <= #1 mem_do[7];
end
else
state <= #1 get_mem_adr;
ld <= #1 1'b1;
end
get_mem_adr: // wait for memory address
if(acc_done)
begin
state <= #1 gma_ack;
mem_adr <= #1 sr; // store memory address
sda_o <= #1 !(sr <= 15); // generate i2c_ack, for valid address
if(debug)
#1 $display("DEBUG i2c_slave; address received. adr=%x, ack=%b", sr, sda_o);
end
gma_ack:
begin
state <= #1 data;
ld <= #1 1'b1;
end
data: // receive or drive data
begin
if(rw)
sda_o <= #1 mem_do[7];
if(acc_done)
begin
state <= #1 data_ack;
mem_adr <= #2 mem_adr + 8'h1;
sda_o <= #1 (rw && (mem_adr <= 15) ); // send ack on write, receive ack on read
if(rw)
begin
#3 mem_do <= mem[mem_adr];
if(debug)
#5 $display("DEBUG i2c_slave; data block read %x from address %x (2)", mem_do, mem_adr);
end
if(!rw)
begin
mem[ mem_adr[3:0] ] <= #1 sr; // store data in memory
if(debug)
#2 $display("DEBUG i2c_slave; data block write %x to address %x", sr, mem_adr);
end
end
end
data_ack:
begin
ld <= #1 1'b1;
if(rw)
if(sr[0]) // read operation && master send NACK
begin
state <= #1 idle;
sda_o <= #1 1'b1;
end
else
begin
state <= #1 data;
sda_o <= #1 mem_do[7];
end
else
begin
state <= #1 data;
sda_o <= #1 1'b1;
end
end
endcase
end
// read data from memory
always @(posedge scl)
if(!acc_done && rw)
mem_do <= #1 {mem_do[6:0], 1'b1}; // insert 1'b1 for host ack generation
// generate tri-states
assign sda = sda_o ? 1'bz : 1'b0;
//
// Timing checks
//
wire tst_sto = sto;
wire tst_sta = sta;
specify
specparam normal_scl_low = 4700,
normal_scl_high = 4000,
normal_tsu_sta = 4700,
normal_thd_sta = 4000,
normal_tsu_sto = 4000,
normal_tbuf = 4700,
fast_scl_low = 1300,
fast_scl_high = 600,
fast_tsu_sta = 1300,
fast_thd_sta = 600,
fast_tsu_sto = 600,
fast_tbuf = 1300;
$width(negedge scl, normal_scl_low); // scl low time
$width(posedge scl, normal_scl_high); // scl high time
$setup(posedge scl, negedge sda &&& scl, normal_tsu_sta); // setup start
$setup(negedge sda &&& scl, negedge scl, normal_thd_sta); // hold start
$setup(posedge scl, posedge sda &&& scl, normal_tsu_sto); // setup stop
$setup(posedge tst_sta, posedge tst_sto, normal_tbuf); // stop to start time
endspecify
endmodule
|
module dcm12_100
(
// Inputs
input clkref_i
// Outputs
,output clkout0_o
);
wire clkref_buffered_w;
wire clkfb;
wire clk0;
wire clkfx;
// Clocking primitive
DCM_SP
#(
.CLKDV_DIVIDE(2.000),
.CLKFX_DIVIDE(3),
.CLKFX_MULTIPLY(25),
.CLKIN_PERIOD(83.3333333333),
.CLKOUT_PHASE_SHIFT("NONE"),
.CLK_FEEDBACK("1X"),
.DESKEW_ADJUST("SYSTEM_SYNCHRONOUS"),
.PHASE_SHIFT(0)
)
dcm_sp_inst
(
.CLKIN(clkref_i),
.CLKFB(clkfb),
// Output clocks
.CLK0(clk0), // 100MHz
.CLK90(),
.CLK180(),
.CLK270(),
.CLK2X(),
.CLK2X180(),
.CLKFX(clkfx),
.CLKFX180(),
.CLKDV(),
// Ports for dynamic phase shift
.PSCLK(1'b0),
.PSEN(1'b0),
.PSINCDEC(1'b0),
.PSDONE(),
// Other control and status signals,
.LOCKED(),
.STATUS(),
.RST(1'b0),
// Unused pin, tie low
.DSSEN(1'b0)
);
BUFG clkfb_buf
(
.I(clk0),
.O(clkfb)
);
//-----------------------------------------------------------------
// CLK_OUT0
//-----------------------------------------------------------------
BUFG clkout0_buf
(
.I(clkfx),
.O(clkout0_o)
);
endmodule
|
module fpga_top
(
// Inputs
input ftdi_clk_i
,input ftdi_rst_i
,input sample_clk_i
,input sample_rst_i
,input mem_clk_i
,input mem_rst_i
,input clk_i
,input rst_i
,input ftdi_rxf_i
,input ftdi_txe_i
,input [ 7:0] ftdi_data_in_i
,input [ 31:0] input_i
,input mem_awready_i
,input mem_wready_i
,input mem_bvalid_i
,input [ 1:0] mem_bresp_i
,input [ 3:0] mem_bid_i
,input mem_arready_i
,input mem_rvalid_i
,input [ 31:0] mem_rdata_i
,input [ 1:0] mem_rresp_i
,input [ 3:0] mem_rid_i
,input mem_rlast_i
// Outputs
,output ftdi_siwua_o
,output ftdi_wrn_o
,output ftdi_rdn_o
,output ftdi_oen_o
,output [ 7:0] ftdi_data_out_o
,output [ 7:0] gpio_outputs_o
,output status_enabled_o
,output status_triggered_o
,output status_overflow_o
,output cfg_clk_src_ext_o
,output mem_awvalid_o
,output [ 31:0] mem_awaddr_o
,output [ 3:0] mem_awid_o
,output [ 7:0] mem_awlen_o
,output [ 1:0] mem_awburst_o
,output mem_wvalid_o
,output [ 31:0] mem_wdata_o
,output [ 3:0] mem_wstrb_o
,output mem_wlast_o
,output mem_bready_o
,output mem_arvalid_o
,output [ 31:0] mem_araddr_o
,output [ 3:0] mem_arid_o
,output [ 7:0] mem_arlen_o
,output [ 1:0] mem_arburst_o
,output mem_rready_o
);
wire [ 1:0] axi_capture_rresp_w;
wire axi_retime_arvalid_w;
wire axi_capture_awvalid_w;
wire axi_capture_arready_w;
wire [ 1:0] axi_capture_bresp_w;
wire [ 31:0] axi_cfg_wdata_w;
wire axi_ftdi_rready_w;
wire axi_ftdi_bvalid_w;
wire [ 1:0] axi_rresp_w;
wire [ 3:0] axi_retime_wstrb_w;
wire [ 1:0] axi_cdc_rresp_w;
wire axi_capture_bvalid_w;
wire [ 1:0] axi_cdc_arburst_w;
wire [ 3:0] axi_retime_arid_w;
wire axi_ftdi_rlast_w;
wire axi_capture_rready_w;
wire [ 7:0] axi_ftdi_arlen_w;
wire [ 1:0] axi_capture_retimed_arburst_w;
wire [ 1:0] axi_ftdi_rresp_w;
wire axi_capture_retimed_rlast_w;
wire axi_awvalid_w;
wire [ 3:0] axi_capture_bid_w;
wire [ 1:0] axi_arburst_w;
wire [ 3:0] axi_cdc_bid_w;
wire [ 31:0] axi_retime_wdata_w;
wire [ 31:0] axi_capture_araddr_w;
wire axi_awready_w;
wire [ 31:0] axi_capture_wdata_w;
wire [ 1:0] axi_cdc_awburst_w;
wire [ 7:0] axi_capture_retimed_awlen_w;
wire axi_cfg_wvalid_w;
wire [ 31:0] axi_cfg_rdata_w;
wire axi_rready_w;
wire [ 3:0] axi_cfg_wstrb_w;
wire [ 1:0] axi_capture_retimed_rresp_w;
wire [ 3:0] axi_capture_retimed_arid_w;
wire axi_retime_wlast_w;
wire [ 31:0] axi_capture_retimed_araddr_w;
wire [ 3:0] axi_capture_retimed_wstrb_w;
wire axi_ftdi_bready_w;
wire axi_ftdi_wlast_w;
wire [ 3:0] axi_capture_arid_w;
wire [ 31:0] axi_ftdi_awaddr_w;
wire [ 3:0] axi_cdc_rid_w;
wire axi_cdc_rlast_w;
wire [ 1:0] axi_retime_arburst_w;
wire [ 31:0] axi_retime_rdata_w;
wire axi_ftdi_rvalid_w;
wire axi_rlast_w;
wire axi_cfg_bready_w;
wire axi_cfg_awready_w;
wire [ 3:0] axi_bid_w;
wire [ 7:0] axi_cdc_arlen_w;
wire [ 31:0] axi_ftdi_araddr_w;
wire [ 3:0] axi_arid_w;
wire axi_retime_bvalid_w;
wire axi_ftdi_awready_w;
wire axi_cfg_awvalid_w;
wire [ 3:0] axi_capture_awid_w;
wire [ 31:0] axi_ftdi_rdata_w;
wire axi_capture_retimed_arvalid_w;
wire [ 1:0] axi_awburst_w;
wire [ 1:0] cfg_width_w;
wire axi_retime_rlast_w;
wire axi_cfg_wready_w;
wire [ 3:0] axi_cdc_wstrb_w;
wire [ 31:0] axi_cfg_araddr_w;
wire [ 31:0] axi_rdata_w;
wire [ 1:0] axi_ftdi_awburst_w;
wire axi_arready_w;
wire axi_ftdi_awvalid_w;
wire [ 31:0] axi_araddr_w;
wire axi_cdc_bready_w;
wire [ 7:0] axi_ftdi_awlen_w;
wire [ 1:0] axi_ftdi_arburst_w;
wire [ 7:0] axi_arlen_w;
wire axi_capture_arvalid_w;
wire axi_capture_retimed_rvalid_w;
wire axi_retime_arready_w;
wire [ 7:0] axi_retime_awlen_w;
wire [ 1:0] axi_retime_rresp_w;
wire [ 3:0] axi_retime_bid_w;
wire axi_cdc_bvalid_w;
wire [ 3:0] axi_retime_rid_w;
wire axi_ftdi_arvalid_w;
wire axi_cdc_arready_w;
wire [ 31:0] input_data_w;
wire [ 31:0] axi_wdata_w;
wire [ 31:0] axi_cfg_awaddr_w;
wire axi_cdc_awvalid_w;
wire axi_capture_wvalid_w;
wire cfg_test_mode_w;
wire axi_wlast_w;
wire axi_retime_wready_w;
wire [ 31:0] axi_capture_retimed_wdata_w;
wire [ 31:0] axi_cdc_araddr_w;
wire [ 31:0] axi_capture_rdata_w;
wire axi_cfg_arvalid_w;
wire [ 3:0] axi_cdc_awid_w;
wire axi_retime_bready_w;
wire [ 31:0] axi_cdc_wdata_w;
wire [ 1:0] axi_retime_awburst_w;
wire axi_capture_retimed_bvalid_w;
wire [ 7:0] axi_cdc_awlen_w;
wire [ 31:0] axi_cdc_awaddr_w;
wire axi_capture_retimed_rready_w;
wire [ 1:0] axi_bresp_w;
wire input_valid_w;
wire axi_wvalid_w;
wire axi_capture_retimed_awready_w;
wire axi_cdc_arvalid_w;
wire [ 3:0] axi_ftdi_bid_w;
wire axi_retime_wvalid_w;
wire axi_capture_retimed_arready_w;
wire axi_retime_rready_w;
wire [ 3:0] axi_wstrb_w;
wire [ 1:0] axi_ftdi_bresp_w;
wire axi_ftdi_arready_w;
wire [ 1:0] axi_cdc_bresp_w;
wire axi_retime_awvalid_w;
wire axi_retime_rvalid_w;
wire axi_capture_rlast_w;
wire [ 1:0] axi_capture_awburst_w;
wire [ 1:0] axi_capture_arburst_w;
wire [ 1:0] axi_capture_retimed_bresp_w;
wire [ 1:0] axi_capture_retimed_awburst_w;
wire axi_ftdi_wvalid_w;
wire [ 31:0] axi_awaddr_w;
wire [ 31:0] axi_ftdi_wdata_w;
wire [ 3:0] axi_capture_rid_w;
wire [ 3:0] axi_ftdi_rid_w;
wire [ 31:0] axi_retime_araddr_w;
wire axi_capture_wlast_w;
wire [ 31:0] axi_cdc_rdata_w;
wire [ 3:0] cfg_clk_div_w;
wire [ 7:0] axi_capture_arlen_w;
wire [ 1:0] axi_cfg_rresp_w;
wire axi_capture_retimed_awvalid_w;
wire axi_capture_bready_w;
wire axi_cdc_wvalid_w;
wire [ 3:0] axi_capture_wstrb_w;
wire axi_cfg_rvalid_w;
wire axi_cdc_wlast_w;
wire axi_cfg_arready_w;
wire axi_cdc_rready_w;
wire axi_ftdi_wready_w;
wire [ 31:0] axi_retime_awaddr_w;
wire [ 31:0] axi_capture_retimed_awaddr_w;
wire [ 7:0] axi_awlen_w;
wire [ 1:0] axi_retime_bresp_w;
wire axi_cfg_bvalid_w;
wire [ 7:0] axi_retime_arlen_w;
wire [ 31:0] axi_capture_awaddr_w;
wire axi_capture_retimed_wready_w;
wire axi_cdc_awready_w;
wire axi_capture_awready_w;
wire [ 7:0] axi_capture_awlen_w;
wire axi_cfg_rready_w;
wire [ 3:0] axi_ftdi_arid_w;
wire [ 3:0] axi_capture_retimed_awid_w;
wire [ 3:0] axi_retime_awid_w;
wire axi_cdc_wready_w;
wire axi_wready_w;
wire axi_capture_wready_w;
wire axi_cdc_rvalid_w;
wire [ 3:0] axi_capture_retimed_rid_w;
wire axi_capture_retimed_bready_w;
wire [ 7:0] axi_capture_retimed_arlen_w;
wire [ 3:0] axi_cdc_arid_w;
wire axi_rvalid_w;
wire [ 3:0] axi_awid_w;
wire [ 3:0] axi_capture_retimed_bid_w;
wire [ 31:0] axi_capture_retimed_rdata_w;
wire [ 3:0] axi_rid_w;
wire axi_arvalid_w;
wire axi_bvalid_w;
wire axi_bready_w;
wire axi_retime_awready_w;
wire axi_capture_retimed_wvalid_w;
wire [ 3:0] axi_ftdi_awid_w;
wire [ 1:0] axi_cfg_bresp_w;
wire axi_capture_rvalid_w;
wire [ 3:0] axi_ftdi_wstrb_w;
wire axi_capture_retimed_wlast_w;
axi4_cdc
u_cdc
(
// Inputs
.wr_clk_i(ftdi_clk_i)
,.wr_rst_i(ftdi_rst_i)
,.inport_awvalid_i(axi_cdc_awvalid_w)
,.inport_awaddr_i(axi_cdc_awaddr_w)
,.inport_awid_i(axi_cdc_awid_w)
,.inport_awlen_i(axi_cdc_awlen_w)
,.inport_awburst_i(axi_cdc_awburst_w)
,.inport_wvalid_i(axi_cdc_wvalid_w)
,.inport_wdata_i(axi_cdc_wdata_w)
,.inport_wstrb_i(axi_cdc_wstrb_w)
,.inport_wlast_i(axi_cdc_wlast_w)
,.inport_bready_i(axi_cdc_bready_w)
,.inport_arvalid_i(axi_cdc_arvalid_w)
,.inport_araddr_i(axi_cdc_araddr_w)
,.inport_arid_i(axi_cdc_arid_w)
,.inport_arlen_i(axi_cdc_arlen_w)
,.inport_arburst_i(axi_cdc_arburst_w)
,.inport_rready_i(axi_cdc_rready_w)
,.rd_clk_i(clk_i)
,.rd_rst_i(rst_i)
,.outport_awready_i(axi_awready_w)
,.outport_wready_i(axi_wready_w)
,.outport_bvalid_i(axi_bvalid_w)
,.outport_bresp_i(axi_bresp_w)
,.outport_bid_i(axi_bid_w)
,.outport_arready_i(axi_arready_w)
,.outport_rvalid_i(axi_rvalid_w)
,.outport_rdata_i(axi_rdata_w)
,.outport_rresp_i(axi_rresp_w)
,.outport_rid_i(axi_rid_w)
,.outport_rlast_i(axi_rlast_w)
// Outputs
,.inport_awready_o(axi_cdc_awready_w)
,.inport_wready_o(axi_cdc_wready_w)
,.inport_bvalid_o(axi_cdc_bvalid_w)
,.inport_bresp_o(axi_cdc_bresp_w)
,.inport_bid_o(axi_cdc_bid_w)
,.inport_arready_o(axi_cdc_arready_w)
,.inport_rvalid_o(axi_cdc_rvalid_w)
,.inport_rdata_o(axi_cdc_rdata_w)
,.inport_rresp_o(axi_cdc_rresp_w)
,.inport_rid_o(axi_cdc_rid_w)
,.inport_rlast_o(axi_cdc_rlast_w)
,.outport_awvalid_o(axi_awvalid_w)
,.outport_awaddr_o(axi_awaddr_w)
,.outport_awid_o(axi_awid_w)
,.outport_awlen_o(axi_awlen_w)
,.outport_awburst_o(axi_awburst_w)
,.outport_wvalid_o(axi_wvalid_w)
,.outport_wdata_o(axi_wdata_w)
,.outport_wstrb_o(axi_wstrb_w)
,.outport_wlast_o(axi_wlast_w)
,.outport_bready_o(axi_bready_w)
,.outport_arvalid_o(axi_arvalid_w)
,.outport_araddr_o(axi_araddr_w)
,.outport_arid_o(axi_arid_w)
,.outport_arlen_o(axi_arlen_w)
,.outport_arburst_o(axi_arburst_w)
,.outport_rready_o(axi_rready_w)
);
capture_rle
u_input
(
// Inputs
.clk_i(clk_i)
,.rst_i(rst_i)
,.input_clk_i(sample_clk_i)
,.input_rst_i(sample_rst_i)
,.input_i(input_i)
,.cfg_clk_div_i(cfg_clk_div_w)
,.cfg_width_i(cfg_width_w)
,.cfg_test_mode_i(cfg_test_mode_w)
// Outputs
,.valid_o(input_valid_w)
,.data_o(input_data_w)
);
axi4_lite_tap
u_dist
(
// Inputs
.clk_i(clk_i)
,.rst_i(rst_i)
,.inport_awvalid_i(axi_awvalid_w)
,.inport_awaddr_i(axi_awaddr_w)
,.inport_awid_i(axi_awid_w)
,.inport_awlen_i(axi_awlen_w)
,.inport_awburst_i(axi_awburst_w)
,.inport_wvalid_i(axi_wvalid_w)
,.inport_wdata_i(axi_wdata_w)
,.inport_wstrb_i(axi_wstrb_w)
,.inport_wlast_i(axi_wlast_w)
,.inport_bready_i(axi_bready_w)
,.inport_arvalid_i(axi_arvalid_w)
,.inport_araddr_i(axi_araddr_w)
,.inport_arid_i(axi_arid_w)
,.inport_arlen_i(axi_arlen_w)
,.inport_arburst_i(axi_arburst_w)
,.inport_rready_i(axi_rready_w)
,.outport_awready_i(axi_ftdi_awready_w)
,.outport_wready_i(axi_ftdi_wready_w)
,.outport_bvalid_i(axi_ftdi_bvalid_w)
,.outport_bresp_i(axi_ftdi_bresp_w)
,.outport_bid_i(axi_ftdi_bid_w)
,.outport_arready_i(axi_ftdi_arready_w)
,.outport_rvalid_i(axi_ftdi_rvalid_w)
,.outport_rdata_i(axi_ftdi_rdata_w)
,.outport_rresp_i(axi_ftdi_rresp_w)
,.outport_rid_i(axi_ftdi_rid_w)
,.outport_rlast_i(axi_ftdi_rlast_w)
,.outport_peripheral0_awready_i(axi_cfg_awready_w)
,.outport_peripheral0_wready_i(axi_cfg_wready_w)
,.outport_peripheral0_bvalid_i(axi_cfg_bvalid_w)
,.outport_peripheral0_bresp_i(axi_cfg_bresp_w)
,.outport_peripheral0_arready_i(axi_cfg_arready_w)
,.outport_peripheral0_rvalid_i(axi_cfg_rvalid_w)
,.outport_peripheral0_rdata_i(axi_cfg_rdata_w)
,.outport_peripheral0_rresp_i(axi_cfg_rresp_w)
// Outputs
,.inport_awready_o(axi_awready_w)
,.inport_wready_o(axi_wready_w)
,.inport_bvalid_o(axi_bvalid_w)
,.inport_bresp_o(axi_bresp_w)
,.inport_bid_o(axi_bid_w)
,.inport_arready_o(axi_arready_w)
,.inport_rvalid_o(axi_rvalid_w)
,.inport_rdata_o(axi_rdata_w)
,.inport_rresp_o(axi_rresp_w)
,.inport_rid_o(axi_rid_w)
,.inport_rlast_o(axi_rlast_w)
,.outport_awvalid_o(axi_ftdi_awvalid_w)
,.outport_awaddr_o(axi_ftdi_awaddr_w)
,.outport_awid_o(axi_ftdi_awid_w)
,.outport_awlen_o(axi_ftdi_awlen_w)
,.outport_awburst_o(axi_ftdi_awburst_w)
,.outport_wvalid_o(axi_ftdi_wvalid_w)
,.outport_wdata_o(axi_ftdi_wdata_w)
,.outport_wstrb_o(axi_ftdi_wstrb_w)
,.outport_wlast_o(axi_ftdi_wlast_w)
,.outport_bready_o(axi_ftdi_bready_w)
,.outport_arvalid_o(axi_ftdi_arvalid_w)
,.outport_araddr_o(axi_ftdi_araddr_w)
,.outport_arid_o(axi_ftdi_arid_w)
,.outport_arlen_o(axi_ftdi_arlen_w)
,.outport_arburst_o(axi_ftdi_arburst_w)
,.outport_rready_o(axi_ftdi_rready_w)
,.outport_peripheral0_awvalid_o(axi_cfg_awvalid_w)
,.outport_peripheral0_awaddr_o(axi_cfg_awaddr_w)
,.outport_peripheral0_wvalid_o(axi_cfg_wvalid_w)
,.outport_peripheral0_wdata_o(axi_cfg_wdata_w)
,.outport_peripheral0_wstrb_o(axi_cfg_wstrb_w)
,.outport_peripheral0_bready_o(axi_cfg_bready_w)
,.outport_peripheral0_arvalid_o(axi_cfg_arvalid_w)
,.outport_peripheral0_araddr_o(axi_cfg_araddr_w)
,.outport_peripheral0_rready_o(axi_cfg_rready_w)
);
ft245_axi
#(
.AXI_ID(8)
,.RETIME_AXI(1)
)
u_dbg
(
// Inputs
.clk_i(ftdi_clk_i)
,.rst_i(ftdi_rst_i)
,.ftdi_rxf_i(ftdi_rxf_i)
,.ftdi_txe_i(ftdi_txe_i)
,.ftdi_data_in_i(ftdi_data_in_i)
,.outport_awready_i(axi_cdc_awready_w)
,.outport_wready_i(axi_cdc_wready_w)
,.outport_bvalid_i(axi_cdc_bvalid_w)
,.outport_bresp_i(axi_cdc_bresp_w)
,.outport_bid_i(axi_cdc_bid_w)
,.outport_arready_i(axi_cdc_arready_w)
,.outport_rvalid_i(axi_cdc_rvalid_w)
,.outport_rdata_i(axi_cdc_rdata_w)
,.outport_rresp_i(axi_cdc_rresp_w)
,.outport_rid_i(axi_cdc_rid_w)
,.outport_rlast_i(axi_cdc_rlast_w)
// Outputs
,.ftdi_siwua_o(ftdi_siwua_o)
,.ftdi_wrn_o(ftdi_wrn_o)
,.ftdi_rdn_o(ftdi_rdn_o)
,.ftdi_oen_o(ftdi_oen_o)
,.ftdi_data_out_o(ftdi_data_out_o)
,.outport_awvalid_o(axi_cdc_awvalid_w)
,.outport_awaddr_o(axi_cdc_awaddr_w)
,.outport_awid_o(axi_cdc_awid_w)
,.outport_awlen_o(axi_cdc_awlen_w)
,.outport_awburst_o(axi_cdc_awburst_w)
,.outport_wvalid_o(axi_cdc_wvalid_w)
,.outport_wdata_o(axi_cdc_wdata_w)
,.outport_wstrb_o(axi_cdc_wstrb_w)
,.outport_wlast_o(axi_cdc_wlast_w)
,.outport_bready_o(axi_cdc_bready_w)
,.outport_arvalid_o(axi_cdc_arvalid_w)
,.outport_araddr_o(axi_cdc_araddr_w)
,.outport_arid_o(axi_cdc_arid_w)
,.outport_arlen_o(axi_cdc_arlen_w)
,.outport_arburst_o(axi_cdc_arburst_w)
,.outport_rready_o(axi_cdc_rready_w)
,.gpio_outputs_o(gpio_outputs_o)
);
axi4_cdc
u_cdc_mem
(
// Inputs
.wr_clk_i(clk_i)
,.wr_rst_i(rst_i)
,.inport_awvalid_i(axi_retime_awvalid_w)
,.inport_awaddr_i(axi_retime_awaddr_w)
,.inport_awid_i(axi_retime_awid_w)
,.inport_awlen_i(axi_retime_awlen_w)
,.inport_awburst_i(axi_retime_awburst_w)
,.inport_wvalid_i(axi_retime_wvalid_w)
,.inport_wdata_i(axi_retime_wdata_w)
,.inport_wstrb_i(axi_retime_wstrb_w)
,.inport_wlast_i(axi_retime_wlast_w)
,.inport_bready_i(axi_retime_bready_w)
,.inport_arvalid_i(axi_retime_arvalid_w)
,.inport_araddr_i(axi_retime_araddr_w)
,.inport_arid_i(axi_retime_arid_w)
,.inport_arlen_i(axi_retime_arlen_w)
,.inport_arburst_i(axi_retime_arburst_w)
,.inport_rready_i(axi_retime_rready_w)
,.rd_clk_i(mem_clk_i)
,.rd_rst_i(mem_rst_i)
,.outport_awready_i(mem_awready_i)
,.outport_wready_i(mem_wready_i)
,.outport_bvalid_i(mem_bvalid_i)
,.outport_bresp_i(mem_bresp_i)
,.outport_bid_i(mem_bid_i)
,.outport_arready_i(mem_arready_i)
,.outport_rvalid_i(mem_rvalid_i)
,.outport_rdata_i(mem_rdata_i)
,.outport_rresp_i(mem_rresp_i)
,.outport_rid_i(mem_rid_i)
,.outport_rlast_i(mem_rlast_i)
// Outputs
,.inport_awready_o(axi_retime_awready_w)
,.inport_wready_o(axi_retime_wready_w)
,.inport_bvalid_o(axi_retime_bvalid_w)
,.inport_bresp_o(axi_retime_bresp_w)
,.inport_bid_o(axi_retime_bid_w)
,.inport_arready_o(axi_retime_arready_w)
,.inport_rvalid_o(axi_retime_rvalid_w)
,.inport_rdata_o(axi_retime_rdata_w)
,.inport_rresp_o(axi_retime_rresp_w)
,.inport_rid_o(axi_retime_rid_w)
,.inport_rlast_o(axi_retime_rlast_w)
,.outport_awvalid_o(mem_awvalid_o)
,.outport_awaddr_o(mem_awaddr_o)
,.outport_awid_o(mem_awid_o)
,.outport_awlen_o(mem_awlen_o)
,.outport_awburst_o(mem_awburst_o)
,.outport_wvalid_o(mem_wvalid_o)
,.outport_wdata_o(mem_wdata_o)
,.outport_wstrb_o(mem_wstrb_o)
,.outport_wlast_o(mem_wlast_o)
,.outport_bready_o(mem_bready_o)
,.outport_arvalid_o(mem_arvalid_o)
,.outport_araddr_o(mem_araddr_o)
,.outport_arid_o(mem_arid_o)
,.outport_arlen_o(mem_arlen_o)
,.outport_arburst_o(mem_arburst_o)
,.outport_rready_o(mem_rready_o)
);
axi4_arb
u_arb
(
// Inputs
.clk_i(clk_i)
,.rst_i(rst_i)
,.inport0_awvalid_i(axi_capture_retimed_awvalid_w)
,.inport0_awaddr_i(axi_capture_retimed_awaddr_w)
,.inport0_awid_i(axi_capture_retimed_awid_w)
,.inport0_awlen_i(axi_capture_retimed_awlen_w)
,.inport0_awburst_i(axi_capture_retimed_awburst_w)
,.inport0_wvalid_i(axi_capture_retimed_wvalid_w)
,.inport0_wdata_i(axi_capture_retimed_wdata_w)
,.inport0_wstrb_i(axi_capture_retimed_wstrb_w)
,.inport0_wlast_i(axi_capture_retimed_wlast_w)
,.inport0_bready_i(axi_capture_retimed_bready_w)
,.inport0_arvalid_i(axi_capture_retimed_arvalid_w)
,.inport0_araddr_i(axi_capture_retimed_araddr_w)
,.inport0_arid_i(axi_capture_retimed_arid_w)
,.inport0_arlen_i(axi_capture_retimed_arlen_w)
,.inport0_arburst_i(axi_capture_retimed_arburst_w)
,.inport0_rready_i(axi_capture_retimed_rready_w)
,.inport1_awvalid_i(axi_ftdi_awvalid_w)
,.inport1_awaddr_i(axi_ftdi_awaddr_w)
,.inport1_awid_i(axi_ftdi_awid_w)
,.inport1_awlen_i(axi_ftdi_awlen_w)
,.inport1_awburst_i(axi_ftdi_awburst_w)
,.inport1_wvalid_i(axi_ftdi_wvalid_w)
,.inport1_wdata_i(axi_ftdi_wdata_w)
,.inport1_wstrb_i(axi_ftdi_wstrb_w)
,.inport1_wlast_i(axi_ftdi_wlast_w)
,.inport1_bready_i(axi_ftdi_bready_w)
,.inport1_arvalid_i(axi_ftdi_arvalid_w)
,.inport1_araddr_i(axi_ftdi_araddr_w)
,.inport1_arid_i(axi_ftdi_arid_w)
,.inport1_arlen_i(axi_ftdi_arlen_w)
,.inport1_arburst_i(axi_ftdi_arburst_w)
,.inport1_rready_i(axi_ftdi_rready_w)
,.outport_awready_i(axi_retime_awready_w)
,.outport_wready_i(axi_retime_wready_w)
,.outport_bvalid_i(axi_retime_bvalid_w)
,.outport_bresp_i(axi_retime_bresp_w)
,.outport_bid_i(axi_retime_bid_w)
,.outport_arready_i(axi_retime_arready_w)
,.outport_rvalid_i(axi_retime_rvalid_w)
,.outport_rdata_i(axi_retime_rdata_w)
,.outport_rresp_i(axi_retime_rresp_w)
,.outport_rid_i(axi_retime_rid_w)
,.outport_rlast_i(axi_retime_rlast_w)
// Outputs
,.inport0_awready_o(axi_capture_retimed_awready_w)
,.inport0_wready_o(axi_capture_retimed_wready_w)
,.inport0_bvalid_o(axi_capture_retimed_bvalid_w)
,.inport0_bresp_o(axi_capture_retimed_bresp_w)
,.inport0_bid_o(axi_capture_retimed_bid_w)
,.inport0_arready_o(axi_capture_retimed_arready_w)
,.inport0_rvalid_o(axi_capture_retimed_rvalid_w)
,.inport0_rdata_o(axi_capture_retimed_rdata_w)
,.inport0_rresp_o(axi_capture_retimed_rresp_w)
,.inport0_rid_o(axi_capture_retimed_rid_w)
,.inport0_rlast_o(axi_capture_retimed_rlast_w)
,.inport1_awready_o(axi_ftdi_awready_w)
,.inport1_wready_o(axi_ftdi_wready_w)
,.inport1_bvalid_o(axi_ftdi_bvalid_w)
,.inport1_bresp_o(axi_ftdi_bresp_w)
,.inport1_bid_o(axi_ftdi_bid_w)
,.inport1_arready_o(axi_ftdi_arready_w)
,.inport1_rvalid_o(axi_ftdi_rvalid_w)
,.inport1_rdata_o(axi_ftdi_rdata_w)
,.inport1_rresp_o(axi_ftdi_rresp_w)
,.inport1_rid_o(axi_ftdi_rid_w)
,.inport1_rlast_o(axi_ftdi_rlast_w)
,.outport_awvalid_o(axi_retime_awvalid_w)
,.outport_awaddr_o(axi_retime_awaddr_w)
,.outport_awid_o(axi_retime_awid_w)
,.outport_awlen_o(axi_retime_awlen_w)
,.outport_awburst_o(axi_retime_awburst_w)
,.outport_wvalid_o(axi_retime_wvalid_w)
,.outport_wdata_o(axi_retime_wdata_w)
,.outport_wstrb_o(axi_retime_wstrb_w)
,.outport_wlast_o(axi_retime_wlast_w)
,.outport_bready_o(axi_retime_bready_w)
,.outport_arvalid_o(axi_retime_arvalid_w)
,.outport_araddr_o(axi_retime_araddr_w)
,.outport_arid_o(axi_retime_arid_w)
,.outport_arlen_o(axi_retime_arlen_w)
,.outport_arburst_o(axi_retime_arburst_w)
,.outport_rready_o(axi_retime_rready_w)
);
logic_capture_mem
u_capture
(
// Inputs
.clk_i(clk_i)
,.rst_i(rst_i)
,.cfg_awvalid_i(axi_cfg_awvalid_w)
,.cfg_awaddr_i(axi_cfg_awaddr_w)
,.cfg_wvalid_i(axi_cfg_wvalid_w)
,.cfg_wdata_i(axi_cfg_wdata_w)
,.cfg_wstrb_i(axi_cfg_wstrb_w)
,.cfg_bready_i(axi_cfg_bready_w)
,.cfg_arvalid_i(axi_cfg_arvalid_w)
,.cfg_araddr_i(axi_cfg_araddr_w)
,.cfg_rready_i(axi_cfg_rready_w)
,.input_valid_i(input_valid_w)
,.input_data_i(input_data_w)
,.outport_awready_i(axi_capture_awready_w)
,.outport_wready_i(axi_capture_wready_w)
,.outport_bvalid_i(axi_capture_bvalid_w)
,.outport_bresp_i(axi_capture_bresp_w)
,.outport_bid_i(axi_capture_bid_w)
,.outport_arready_i(axi_capture_arready_w)
,.outport_rvalid_i(axi_capture_rvalid_w)
,.outport_rdata_i(axi_capture_rdata_w)
,.outport_rresp_i(axi_capture_rresp_w)
,.outport_rid_i(axi_capture_rid_w)
,.outport_rlast_i(axi_capture_rlast_w)
// Outputs
,.cfg_awready_o(axi_cfg_awready_w)
,.cfg_wready_o(axi_cfg_wready_w)
,.cfg_bvalid_o(axi_cfg_bvalid_w)
,.cfg_bresp_o(axi_cfg_bresp_w)
,.cfg_arready_o(axi_cfg_arready_w)
,.cfg_rvalid_o(axi_cfg_rvalid_w)
,.cfg_rdata_o(axi_cfg_rdata_w)
,.cfg_rresp_o(axi_cfg_rresp_w)
,.outport_awvalid_o(axi_capture_awvalid_w)
,.outport_awaddr_o(axi_capture_awaddr_w)
,.outport_awid_o(axi_capture_awid_w)
,.outport_awlen_o(axi_capture_awlen_w)
,.outport_awburst_o(axi_capture_awburst_w)
,.outport_wvalid_o(axi_capture_wvalid_w)
,.outport_wdata_o(axi_capture_wdata_w)
,.outport_wstrb_o(axi_capture_wstrb_w)
,.outport_wlast_o(axi_capture_wlast_w)
,.outport_bready_o(axi_capture_bready_w)
,.outport_arvalid_o(axi_capture_arvalid_w)
,.outport_araddr_o(axi_capture_araddr_w)
,.outport_arid_o(axi_capture_arid_w)
,.outport_arlen_o(axi_capture_arlen_w)
,.outport_arburst_o(axi_capture_arburst_w)
,.outport_rready_o(axi_capture_rready_w)
,.cfg_clk_src_ext_o(cfg_clk_src_ext_o)
,.cfg_clk_div_o(cfg_clk_div_w)
,.cfg_width_o(cfg_width_w)
,.cfg_test_mode_o(cfg_test_mode_w)
,.status_enabled_o(status_enabled_o)
,.status_triggered_o(status_triggered_o)
,.status_overflow_o(status_overflow_o)
);
axi4_retime
#(
.AXI4_RETIME_RD_RESP(1)
,.AXI4_RETIME_WR_RESP(1)
,.AXI4_RETIME_RD_REQ(1)
,.AXI4_RETIME_WR_REQ(1)
)
u_retime_cap
(
// Inputs
.clk_i(clk_i)
,.rst_i(rst_i)
,.inport_awvalid_i(axi_capture_awvalid_w)
,.inport_awaddr_i(axi_capture_awaddr_w)
,.inport_awid_i(axi_capture_awid_w)
,.inport_awlen_i(axi_capture_awlen_w)
,.inport_awburst_i(axi_capture_awburst_w)
,.inport_wvalid_i(axi_capture_wvalid_w)
,.inport_wdata_i(axi_capture_wdata_w)
,.inport_wstrb_i(axi_capture_wstrb_w)
,.inport_wlast_i(axi_capture_wlast_w)
,.inport_bready_i(axi_capture_bready_w)
,.inport_arvalid_i(axi_capture_arvalid_w)
,.inport_araddr_i(axi_capture_araddr_w)
,.inport_arid_i(axi_capture_arid_w)
,.inport_arlen_i(axi_capture_arlen_w)
,.inport_arburst_i(axi_capture_arburst_w)
,.inport_rready_i(axi_capture_rready_w)
,.outport_awready_i(axi_capture_retimed_awready_w)
,.outport_wready_i(axi_capture_retimed_wready_w)
,.outport_bvalid_i(axi_capture_retimed_bvalid_w)
,.outport_bresp_i(axi_capture_retimed_bresp_w)
,.outport_bid_i(axi_capture_retimed_bid_w)
,.outport_arready_i(axi_capture_retimed_arready_w)
,.outport_rvalid_i(axi_capture_retimed_rvalid_w)
,.outport_rdata_i(axi_capture_retimed_rdata_w)
,.outport_rresp_i(axi_capture_retimed_rresp_w)
,.outport_rid_i(axi_capture_retimed_rid_w)
,.outport_rlast_i(axi_capture_retimed_rlast_w)
// Outputs
,.inport_awready_o(axi_capture_awready_w)
,.inport_wready_o(axi_capture_wready_w)
,.inport_bvalid_o(axi_capture_bvalid_w)
,.inport_bresp_o(axi_capture_bresp_w)
,.inport_bid_o(axi_capture_bid_w)
,.inport_arready_o(axi_capture_arready_w)
,.inport_rvalid_o(axi_capture_rvalid_w)
,.inport_rdata_o(axi_capture_rdata_w)
,.inport_rresp_o(axi_capture_rresp_w)
,.inport_rid_o(axi_capture_rid_w)
,.inport_rlast_o(axi_capture_rlast_w)
,.outport_awvalid_o(axi_capture_retimed_awvalid_w)
,.outport_awaddr_o(axi_capture_retimed_awaddr_w)
,.outport_awid_o(axi_capture_retimed_awid_w)
,.outport_awlen_o(axi_capture_retimed_awlen_w)
,.outport_awburst_o(axi_capture_retimed_awburst_w)
,.outport_wvalid_o(axi_capture_retimed_wvalid_w)
,.outport_wdata_o(axi_capture_retimed_wdata_w)
,.outport_wstrb_o(axi_capture_retimed_wstrb_w)
,.outport_wlast_o(axi_capture_retimed_wlast_w)
,.outport_bready_o(axi_capture_retimed_bready_w)
,.outport_arvalid_o(axi_capture_retimed_arvalid_w)
,.outport_araddr_o(axi_capture_retimed_araddr_w)
,.outport_arid_o(axi_capture_retimed_arid_w)
,.outport_arlen_o(axi_capture_retimed_arlen_w)
,.outport_arburst_o(axi_capture_retimed_arburst_w)
,.outport_rready_o(axi_capture_retimed_rready_w)
);
endmodule
|
module reset_gen
(
input clk_i,
output rst_o
);
reg rst_q = 1'b1;
always @(posedge clk_i)
rst_q <= 1'b0;
assign rst_o = rst_q;
endmodule
|
module spartan6_pll
(
// Inputs
input clkref_i
// Outputs
,output clkout0_o
);
wire clkref_buffered_w;
wire clkfbout_w;
wire pll_clkout0_w;
wire pll_clkout0_buffered_w;
// Input buffering
assign clkref_buffered_w = clkref_i;
// Clocking primitive
PLL_BASE
#(
.BANDWIDTH ("OPTIMIZED"),
.CLK_FEEDBACK ("CLKFBOUT"),
.COMPENSATION ("INTERNAL"),
.DIVCLK_DIVIDE (1),
.CLKFBOUT_MULT (13), // VCO=624MHz
.CLKFBOUT_PHASE (0.000),
.CLKOUT0_DIVIDE (2), // CLK0=312MHz
.CLKOUT0_PHASE (0.0),
.CLKOUT0_DUTY_CYCLE (0.500),
.CLKIN_PERIOD (20.8333333333),
.REF_JITTER (0.010)
)
pll_base_inst
(
.CLKFBOUT(clkfbout_w),
.CLKOUT0(pll_clkout0_w),
.CLKOUT1(),
.CLKOUT2(),
.CLKOUT3(),
.CLKOUT4(),
.CLKOUT5(),
.RST(1'b0),
.CLKFBIN(clkfbout_w),
.CLKIN(clkref_buffered_w)
);
//-----------------------------------------------------------------
// CLK_OUT0
//-----------------------------------------------------------------
BUFG clkout0_buf
(
.I(pll_clkout0_w),
.O(pll_clkout0_buffered_w)
);
assign clkout0_o = pll_clkout0_buffered_w;
endmodule
|
module top
(
// Clocks
input CLK12
,output LD2_B
,output LD2_R
,output LD2_G
,output LD1_R
,output LD1_G
,output LD1_B
,input FTDI_CLK
,inout [7:0] FTDI_D
,input FTDI_RXF
,input FTDI_TXE
,inout FTDI_WR
,inout FTDI_RD
,inout FTDI_SIWUA
,inout FTDI_OE
// Main input port
,input [23:0] DIN_FPGA
,output DIN_VREF_L
,output DIN_VREF_H
// DDR
,inout [15:0] mcb3_dram_dq
,output [13:0] mcb3_dram_a
,output [2:0] mcb3_dram_ba
,output mcb3_dram_ras_n
,output mcb3_dram_cas_n
,output mcb3_dram_we_n
,output mcb3_dram_odt
,output mcb3_dram_reset_n
,output mcb3_dram_cke
,output mcb3_dram_dm
,inout mcb3_dram_udqs
,inout mcb3_dram_udqs_n
,inout mcb3_rzq
,inout mcb3_zio
,output mcb3_dram_udm
,inout mcb3_dram_dqs
,inout mcb3_dram_dqs_n
,output mcb3_dram_ck
,output mcb3_dram_ck_n
);
//-----------------------------------------------------------------
// Reset
//-----------------------------------------------------------------
wire ftdi_clk_w = FTDI_CLK;
wire ftdi_rst_w;
reset_gen
u_rst_gen
(
.clk_i(ftdi_clk_w)
,.rst_o(ftdi_rst_w)
);
//-----------------------------------------------------------------
// Memory Clock
//-----------------------------------------------------------------
wire clk48_w;
wire clk312_w;
wire clk100_w;
wire mem_clk_w; // 104MHz
wire mem_rst_w;
// Input buffering
IBUFG u_clk_buf
(
.I (CLK12),
.O (clk12_buffered_w)
);
dcm12_48
u_dcm_mem
(
.clkref_i(clk12_buffered_w)
,.clkout0_o(clk48_w)
);
dcm12_100
u_dcm_core
(
.clkref_i(clk12_buffered_w)
,.clkout0_o(clk100_w)
);
spartan6_pll
u_pll_mem
(
.clkref_i(clk48_w)
,.clkout0_o(clk312_w)
);
wire clk312_rst_w;
reset_gen
u_rst_mem
(
.clk_i(clk312_w)
,.rst_o(clk312_rst_w)
);
wire clk100_rst_w;
reset_gen
u_rst_core
(
.clk_i(clk100_w)
,.rst_o(clk100_rst_w)
);
//-----------------------------------------------------------------
// Sample clock
//-----------------------------------------------------------------
wire sample_clk_w = clk100_w;
wire sample_rst_w = clk100_rst_w;
//-----------------------------------------------------------------
// FTDI
//-----------------------------------------------------------------
wire [7:0] ftdi_data_in_w;
wire [7:0] ftdi_data_out_w;
wire status_enabled_w;
wire status_trigger_w;
wire status_overflow_w;
wire mem_awvalid_w;
wire [ 31:0] mem_awaddr_w;
wire [ 3:0] mem_awid_w;
wire [ 7:0] mem_awlen_w;
wire [ 1:0] mem_awburst_w;
wire mem_wvalid_w;
wire [ 31:0] mem_wdata_w;
wire [ 3:0] mem_wstrb_w;
wire mem_wlast_w;
wire mem_bready_w;
wire mem_arvalid_w;
wire [ 31:0] mem_araddr_w;
wire [ 3:0] mem_arid_w;
wire [ 7:0] mem_arlen_w;
wire [ 1:0] mem_arburst_w;
wire mem_rready_w;
wire mem_awready_w;
wire mem_wready_w;
wire mem_bvalid_w;
wire [ 1:0] mem_bresp_w;
wire [ 3:0] mem_bid_w;
wire mem_arready_w;
wire mem_rvalid_w;
wire [ 31:0] mem_rdata_w;
wire [ 1:0] mem_rresp_w;
wire [ 3:0] mem_rid_w;
wire mem_rlast_w;
fpga_top
u_core
(
.ftdi_clk_i(ftdi_clk_w)
,.ftdi_rst_i(ftdi_rst_w)
,.ftdi_rxf_i(FTDI_RXF)
,.ftdi_txe_i(FTDI_TXE)
,.ftdi_data_in_i(ftdi_data_in_w)
,.ftdi_siwua_o(FTDI_SIWUA)
,.ftdi_wrn_o(FTDI_WR)
,.ftdi_rdn_o(FTDI_RD)
,.ftdi_oen_o(FTDI_OE)
,.ftdi_data_out_o(ftdi_data_out_w)
,.clk_i(clk100_w)
,.rst_i(clk100_rst_w)
,.sample_clk_i(sample_clk_w)
,.sample_rst_i(sample_rst_w)
,.gpio_outputs_o()
,.input_i({8'b0, DIN_FPGA})
,.status_enabled_o(status_enabled_w)
,.status_triggered_o(status_trigger_w)
,.status_overflow_o(status_overflow_w)
,.cfg_clk_src_ext_o()
,.mem_clk_i(mem_clk_w)
,.mem_rst_i(mem_rst_w)
,.mem_awvalid_o(mem_awvalid_w)
,.mem_awaddr_o(mem_awaddr_w)
,.mem_awid_o(mem_awid_w)
,.mem_awlen_o(mem_awlen_w)
,.mem_awburst_o(mem_awburst_w)
,.mem_wvalid_o(mem_wvalid_w)
,.mem_wdata_o(mem_wdata_w)
,.mem_wstrb_o(mem_wstrb_w)
,.mem_wlast_o(mem_wlast_w)
,.mem_bready_o(mem_bready_w)
,.mem_arvalid_o(mem_arvalid_w)
,.mem_araddr_o(mem_araddr_w)
,.mem_arid_o(mem_arid_w)
,.mem_arlen_o(mem_arlen_w)
,.mem_arburst_o(mem_arburst_w)
,.mem_rready_o(mem_rready_w)
,.mem_awready_i(mem_awready_w)
,.mem_wready_i(mem_wready_w)
,.mem_bvalid_i(mem_bvalid_w)
,.mem_bresp_i(mem_bresp_w)
,.mem_bid_i(mem_bid_w)
,.mem_arready_i(mem_arready_w)
,.mem_rvalid_i(mem_rvalid_w)
,.mem_rdata_i(mem_rdata_w)
,.mem_rresp_i(mem_rresp_w)
,.mem_rid_i(mem_rid_w)
,.mem_rlast_i(mem_rlast_w)
);
assign ftdi_data_in_w = FTDI_D;
assign FTDI_D = FTDI_OE ? ftdi_data_out_w : 8'hZZ;
//-----------------------------------------------------------------
// MIG
//-----------------------------------------------------------------
mig
u_mig
(
.mcb3_dram_dq(mcb3_dram_dq)
,.mcb3_dram_a(mcb3_dram_a)
,.mcb3_dram_ba(mcb3_dram_ba)
,.mcb3_dram_ras_n(mcb3_dram_ras_n)
,.mcb3_dram_cas_n(mcb3_dram_cas_n)
,.mcb3_dram_we_n(mcb3_dram_we_n)
,.mcb3_dram_odt(mcb3_dram_odt)
,.mcb3_dram_reset_n(mcb3_dram_reset_n)
,.mcb3_dram_cke(mcb3_dram_cke)
,.mcb3_dram_dm(mcb3_dram_dm)
,.mcb3_dram_udqs(mcb3_dram_udqs)
,.mcb3_dram_udqs_n(mcb3_dram_udqs_n)
,.mcb3_rzq(mcb3_rzq)
,.mcb3_zio(mcb3_zio)
,.mcb3_dram_udm(mcb3_dram_udm)
,.mcb3_dram_dqs(mcb3_dram_dqs)
,.mcb3_dram_dqs_n(mcb3_dram_dqs_n)
,.mcb3_dram_ck(mcb3_dram_ck)
,.mcb3_dram_ck_n(mcb3_dram_ck_n)
,.c3_sys_clk(clk312_w)
,.c3_sys_rst_i(clk312_rst_w)
,.c3_calib_done()
,.c3_clk0(mem_clk_w) // 104MHz
,.c3_rst0(mem_rst_w)
,.c3_s0_axi_aclk(mem_clk_w)
,.c3_s0_axi_aresetn(~mem_rst_w)
,.c3_s0_axi_awid(mem_awid_w)
,.c3_s0_axi_awaddr(mem_awaddr_w)
,.c3_s0_axi_awlen(mem_awlen_w)
,.c3_s0_axi_awsize(3'b010)
,.c3_s0_axi_awburst(mem_awburst_w)
,.c3_s0_axi_awlock(1'b0)
,.c3_s0_axi_awcache(4'b0)
,.c3_s0_axi_awprot(3'b0)
,.c3_s0_axi_awqos(4'b0)
,.c3_s0_axi_awvalid(mem_awvalid_w)
,.c3_s0_axi_awready(mem_awready_w)
,.c3_s0_axi_wdata(mem_wdata_w)
,.c3_s0_axi_wstrb(mem_wstrb_w)
,.c3_s0_axi_wlast(mem_wlast_w)
,.c3_s0_axi_wvalid(mem_wvalid_w)
,.c3_s0_axi_wready(mem_wready_w)
,.c3_s0_axi_bid(mem_bid_w)
,.c3_s0_axi_wid()
,.c3_s0_axi_bresp(mem_bresp_w)
,.c3_s0_axi_bvalid(mem_bvalid_w)
,.c3_s0_axi_bready(mem_bready_w)
,.c3_s0_axi_arid(mem_arid_w)
,.c3_s0_axi_araddr(mem_araddr_w)
,.c3_s0_axi_arlen(mem_arlen_w)
,.c3_s0_axi_arsize(3'b010)
,.c3_s0_axi_arburst(mem_arburst_w)
,.c3_s0_axi_arlock(1'b0)
,.c3_s0_axi_arcache(4'b0)
,.c3_s0_axi_arprot(3'b0)
,.c3_s0_axi_arqos(4'b0)
,.c3_s0_axi_arvalid(mem_arvalid_w)
,.c3_s0_axi_arready(mem_arready_w)
,.c3_s0_axi_rid(mem_rid_w)
,.c3_s0_axi_rdata(mem_rdata_w)
,.c3_s0_axi_rresp(mem_rresp_w)
,.c3_s0_axi_rlast(mem_rlast_w)
,.c3_s0_axi_rvalid(mem_rvalid_w)
,.c3_s0_axi_rready(mem_rready_w)
);
//-----------------------------------------------------------------
// LED
//-----------------------------------------------------------------
reg [2:0] rgb_q;
always @ (posedge clk100_w)
begin
if (status_overflow_w)
rgb_q <= 3'b100;
else if (status_trigger_w)
rgb_q <= 3'b010;
else if (status_enabled_w)
rgb_q <= 3'b001;
end
assign {LD1_R, LD1_G, LD1_B} = rgb_q;
assign LD2_R = 1'b0;
assign LD2_B = 1'b0;
assign LD2_G = 1'b0;
//-----------------------------------------------------------------
// Misc
//-----------------------------------------------------------------
// VREFIO: 0V, when DIN_VREF_H = DIN_VREF_L = low
assign DIN_VREF_L = 1'b0;
assign DIN_VREF_H = 1'b0;
endmodule
|
module infrastructure #
(
parameter C_INCLK_PERIOD = 2500,
parameter C_RST_ACT_LOW = 1,
parameter C_INPUT_CLK_TYPE = "DIFFERENTIAL",
parameter C_CLKOUT0_DIVIDE = 1,
parameter C_CLKOUT1_DIVIDE = 1,
parameter C_CLKOUT2_DIVIDE = 16,
parameter C_CLKOUT3_DIVIDE = 8,
parameter C_CLKFBOUT_MULT = 2,
parameter C_DIVCLK_DIVIDE = 1
)
(
input sys_clk_p,
input sys_clk_n,
input sys_clk,
input sys_rst_i,
output clk0,
output rst0,
output async_rst,
output sysclk_2x,
output sysclk_2x_180,
output mcb_drp_clk,
output pll_ce_0,
output pll_ce_90,
output pll_lock
);
// # of clock cycles to delay deassertion of reset. Needs to be a fairly
// high number not so much for metastability protection, but to give time
// for reset (i.e. stable clock cycles) to propagate through all state
// machines and to all control signals (i.e. not all control signals have
// resets, instead they rely on base state logic being reset, and the effect
// of that reset propagating through the logic). Need this because we may not
// be getting stable clock cycles while reset asserted (i.e. since reset
// depends on PLL/DCM lock status)
localparam RST_SYNC_NUM = 25;
localparam CLK_PERIOD_NS = C_INCLK_PERIOD / 1000.0;
localparam CLK_PERIOD_INT = C_INCLK_PERIOD/1000;
wire clk_2x_0;
wire clk_2x_180;
wire clk0_bufg;
wire clk0_bufg_in;
wire mcb_drp_clk_bufg_in;
wire clkfbout_clkfbin;
wire locked;
reg [RST_SYNC_NUM-1:0] rst0_sync_r /* synthesis syn_maxfan = 10 */;
wire rst_tmp;
reg powerup_pll_locked;
reg syn_clk0_powerup_pll_locked;
wire sys_rst;
wire bufpll_mcb_locked;
(* KEEP = "TRUE" *) wire sys_clk_ibufg;
assign sys_rst = C_RST_ACT_LOW ? ~sys_rst_i: sys_rst_i;
assign clk0 = clk0_bufg;
assign pll_lock = bufpll_mcb_locked;
generate
if (C_INPUT_CLK_TYPE == "DIFFERENTIAL") begin: diff_input_clk
//***********************************************************************
// Differential input clock input buffers
//***********************************************************************
IBUFGDS #
(
.DIFF_TERM ("TRUE")
)
u_ibufg_sys_clk
(
.I (sys_clk_p),
.IB (sys_clk_n),
.O (sys_clk_ibufg)
);
end else if (C_INPUT_CLK_TYPE == "SINGLE_ENDED") begin: se_input_clk
//***********************************************************************
// SINGLE_ENDED input clock input buffers
//***********************************************************************
//IBUFG u_ibufg_sys_clk
// (
// .I (sys_clk),
// .O (sys_clk_ibufg)
// );
assign sys_clk_ibufg = sys_clk;
end
endgenerate
//***************************************************************************
// Global clock generation and distribution
//***************************************************************************
PLL_ADV #
(
.BANDWIDTH ("OPTIMIZED"),
.CLKIN1_PERIOD (CLK_PERIOD_NS),
.CLKIN2_PERIOD (CLK_PERIOD_NS),
.CLKOUT0_DIVIDE (C_CLKOUT0_DIVIDE),
.CLKOUT1_DIVIDE (C_CLKOUT1_DIVIDE),
.CLKOUT2_DIVIDE (C_CLKOUT2_DIVIDE),
.CLKOUT3_DIVIDE (C_CLKOUT3_DIVIDE),
.CLKOUT4_DIVIDE (1),
.CLKOUT5_DIVIDE (1),
.CLKOUT0_PHASE (0.000),
.CLKOUT1_PHASE (180.000),
.CLKOUT2_PHASE (0.000),
.CLKOUT3_PHASE (0.000),
.CLKOUT4_PHASE (0.000),
.CLKOUT5_PHASE (0.000),
.CLKOUT0_DUTY_CYCLE (0.500),
.CLKOUT1_DUTY_CYCLE (0.500),
.CLKOUT2_DUTY_CYCLE (0.500),
.CLKOUT3_DUTY_CYCLE (0.500),
.CLKOUT4_DUTY_CYCLE (0.500),
.CLKOUT5_DUTY_CYCLE (0.500),
.SIM_DEVICE ("SPARTAN6"),
.COMPENSATION ("INTERNAL"),
.DIVCLK_DIVIDE (C_DIVCLK_DIVIDE),
.CLKFBOUT_MULT (C_CLKFBOUT_MULT),
.CLKFBOUT_PHASE (0.0),
.REF_JITTER (0.005000)
)
u_pll_adv
(
.CLKFBIN (clkfbout_clkfbin),
.CLKINSEL (1'b1),
.CLKIN1 (sys_clk_ibufg),
.CLKIN2 (1'b0),
.DADDR (5'b0),
.DCLK (1'b0),
.DEN (1'b0),
.DI (16'b0),
.DWE (1'b0),
.REL (1'b0),
.RST (sys_rst),
.CLKFBDCM (),
.CLKFBOUT (clkfbout_clkfbin),
.CLKOUTDCM0 (),
.CLKOUTDCM1 (),
.CLKOUTDCM2 (),
.CLKOUTDCM3 (),
.CLKOUTDCM4 (),
.CLKOUTDCM5 (),
.CLKOUT0 (clk_2x_0),
.CLKOUT1 (clk_2x_180),
.CLKOUT2 (clk0_bufg_in),
.CLKOUT3 (mcb_drp_clk_bufg_in),
.CLKOUT4 (),
.CLKOUT5 (),
.DO (),
.DRDY (),
.LOCKED (locked)
);
BUFG U_BUFG_CLK0
(
.O (clk0_bufg),
.I (clk0_bufg_in)
);
BUFGCE U_BUFG_CLK1
(
.O (mcb_drp_clk),
.I (mcb_drp_clk_bufg_in),
.CE (locked)
);
always @(posedge mcb_drp_clk , posedge sys_rst)
if(sys_rst)
powerup_pll_locked <= 1'b0;
else if (bufpll_mcb_locked)
powerup_pll_locked <= 1'b1;
always @(posedge clk0_bufg , posedge sys_rst)
if(sys_rst)
syn_clk0_powerup_pll_locked <= 1'b0;
else if (bufpll_mcb_locked)
syn_clk0_powerup_pll_locked <= 1'b1;
//***************************************************************************
// Reset synchronization
// NOTES:
// 1. shut down the whole operation if the PLL hasn't yet locked (and
// by inference, this means that external SYS_RST_IN has been asserted -
// PLL deasserts LOCKED as soon as SYS_RST_IN asserted)
// 2. asynchronously assert reset. This was we can assert reset even if
// there is no clock (needed for things like 3-stating output buffers).
// reset deassertion is synchronous.
// 3. asynchronous reset only look at pll_lock from PLL during power up. After
// power up and pll_lock is asserted, the powerup_pll_locked will be asserted
// forever until sys_rst is asserted again. PLL will lose lock when FPGA
// enters suspend mode. We don't want reset to MCB get
// asserted in the application that needs suspend feature.
//***************************************************************************
assign async_rst = sys_rst | ~powerup_pll_locked;
// synthesis attribute max_fanout of rst0_sync_r is 10
assign rst_tmp = sys_rst | ~syn_clk0_powerup_pll_locked;
always @(posedge clk0_bufg or posedge rst_tmp)
if (rst_tmp)
rst0_sync_r <= {RST_SYNC_NUM{1'b1}};
else
// logical left shift by one (pads with 0)
rst0_sync_r <= rst0_sync_r << 1;
assign rst0 = rst0_sync_r[RST_SYNC_NUM-1];
BUFPLL_MCB BUFPLL_MCB1
( .IOCLK0 (sysclk_2x),
.IOCLK1 (sysclk_2x_180),
.LOCKED (locked),
.GCLK (mcb_drp_clk),
.SERDESSTROBE0 (pll_ce_0),
.SERDESSTROBE1 (pll_ce_90),
.PLLIN0 (clk_2x_0),
.PLLIN1 (clk_2x_180),
.LOCK (bufpll_mcb_locked)
);
endmodule
|
module cmd_prbs_gen_axi #
(
parameter TCQ = 100,
parameter FAMILY = "SPARTAN6",
parameter ADDR_WIDTH = 29,
parameter DWIDTH = 32,
parameter PRBS_CMD = "ADDRESS", // "INSTR", "BLEN","ADDRESS"
parameter PRBS_WIDTH = 64, // 64,15,20
parameter SEED_WIDTH = 32, // 32,15,4
parameter PRBS_EADDR_MASK_POS = 32'hFFFFD000,
parameter PRBS_SADDR_MASK_POS = 32'h00002000,
parameter PRBS_EADDR = 32'h00002000,
parameter PRBS_SADDR = 32'h00002000
)
(
input clk_i,
input prbs_seed_init, // when high the prbs_x_seed will be loaded
input clk_en,
input [SEED_WIDTH-1:0] prbs_seed_i,
output[SEED_WIDTH-1:0] prbs_o // generated address
);
wire[ADDR_WIDTH - 1:0] ZEROS;
reg [SEED_WIDTH - 1:0] prbs;
reg [PRBS_WIDTH :1] lfsr_q;
assign ZEROS = 'b0;
//
//**************************************************************
//####################################################################################################################
// #
// #
// 64 taps: [64,63,61,60]: {{8'b01011000}, {56'b0}} #
// upper 32 bits are loadable #
// #
//
//
// ........................................................................................
// ^ ^ ^ ^ |
// | ____ | ___ ___ | ___ | ___ ___ ___ |
// | | | |---|<- | | | | |---|<- | | |---|<- | |...| | | | | The first 32 bits are parallel loadable.
// ----|64 |<--|xor|<-- |63 |-->|62 |-|xor|<--|61 |<-|xor|<--|60 |...|33 |<--|1|<<--
// |___| --- |___| |___| --- |___| --- |___|...|___| |___|
//
//
// <<-- shifting --
//#####################################################################################################################
// use SRLC32E for lower 32 stages and 32 registers for upper 32 stages.
// we need to provide 30 bits addres. SRLC32 has only one bit output.
// address seed will be loaded to upper 32 bits.
//
// parallel load and serial shift out to LFSR during INIT time
generate
if(PRBS_CMD == "ADDRESS" && PRBS_WIDTH == 64) begin :gen64_taps
always @ (posedge clk_i) begin
if(prbs_seed_init) begin//reset it to a known good state to prevent it locks up
lfsr_q <= #TCQ {31'b0,prbs_seed_i};
end else if(clk_en) begin
lfsr_q[64] <= #TCQ lfsr_q[64] ^ lfsr_q[63];
lfsr_q[63] <= #TCQ lfsr_q[62];
lfsr_q[62] <= #TCQ lfsr_q[64] ^ lfsr_q[61];
lfsr_q[61] <= #TCQ lfsr_q[64] ^ lfsr_q[60];
lfsr_q[60:2] <= #TCQ lfsr_q[59:1];
lfsr_q[1] <= #TCQ lfsr_q[64];
end
end
always @(lfsr_q[32:1]) begin
prbs = lfsr_q[32:1];
end
end
endgenerate
function integer logb2;
input [31:0] in;
integer i;
begin
i = in;
for(logb2=1; i>0; logb2=logb2+1)
i = i >> 1;
end
endfunction
generate
if(PRBS_CMD == "ADDRESS" && PRBS_WIDTH == 32) begin :gen32_taps
always @ (posedge clk_i) begin
if(prbs_seed_init) begin //reset it to a known good state to prevent it locks up
lfsr_q <= #TCQ {prbs_seed_i};
end else if(clk_en) begin
lfsr_q[32:9] <= #TCQ lfsr_q[31:8];
lfsr_q[8] <= #TCQ lfsr_q[32] ^ lfsr_q[7];
lfsr_q[7] <= #TCQ lfsr_q[32] ^ lfsr_q[6];
lfsr_q[6:4] <= #TCQ lfsr_q[5:3];
lfsr_q[3] <= #TCQ lfsr_q[32] ^ lfsr_q[2];
lfsr_q[2] <= #TCQ lfsr_q[1] ;
lfsr_q[1] <= #TCQ lfsr_q[32];
end
end
integer i;
always @(lfsr_q[32:1]) begin
if (FAMILY == "SPARTAN6" ) begin // for 32 bits
for(i = logb2(DWIDTH) + 1; i <= SEED_WIDTH - 1; i = i + 1)
if(PRBS_SADDR_MASK_POS[i] == 1)
prbs[i] = PRBS_SADDR[i] | lfsr_q[i+1];
else if(PRBS_EADDR_MASK_POS[i] == 1)
prbs[i] = PRBS_EADDR[i] & lfsr_q[i+1];
else
prbs[i] = lfsr_q[i+1];
prbs[logb2(DWIDTH ) :0] = {logb2(DWIDTH ) + 1{1'b0}};
end
else begin
for(i = logb2(DWIDTH)-4; i <= SEED_WIDTH - 1; i = i + 1)
if(PRBS_SADDR_MASK_POS[i] == 1)
prbs[i] = PRBS_SADDR[i] | lfsr_q[i+1];
else if(PRBS_EADDR_MASK_POS[i] == 1)
prbs[i] = PRBS_EADDR[i] & lfsr_q[i+1];
else
prbs[i] = lfsr_q[i+1];
prbs[logb2(DWIDTH)-5:0] = {logb2(DWIDTH) - 4{1'b0}};
end
end
end endgenerate
//////////////////////////////////////////////////////////////////////////
//####################################################################################################################
// #
// #
// 15 taps: [15,14]: #
// #
// #
//
//
// .............................................................
// ^ ^ . ^
// | ____ | ___ ___ ___ ___ ___ |
// | | | |---|<- | | | | | |...| | | | |
// ----|15 |<--|xor|<-- |14 |<--|13 |<--|12 |...|2 |<--|1 |<<--
// |___| --- |___| |___| |___|...|___| |___|
//
//
// <<-- shifting --
//#####################################################################################################################
generate
if(PRBS_CMD == "INSTR" | PRBS_CMD == "BLEN") begin :gen20_taps
always @(posedge clk_i) begin
if(prbs_seed_init) begin//reset it to a known good state to prevent it locks up
lfsr_q <= #TCQ {5'b0,prbs_seed_i[14:0]};
end else if(clk_en) begin
lfsr_q[20] <= #TCQ lfsr_q[19];
lfsr_q[19] <= #TCQ lfsr_q[18];
lfsr_q[18] <= #TCQ lfsr_q[20] ^lfsr_q[17];
lfsr_q[17:2] <= #TCQ lfsr_q[16:1];
lfsr_q[1] <= #TCQ lfsr_q[20];
end
end
always @ (lfsr_q) begin
prbs = lfsr_q[32:1];
end
end
endgenerate
assign prbs_o = prbs;
endmodule
|
module axi4_tg #(
parameter C_AXI_ID_WIDTH = 4, // The AXI id width used for read and write
// This is an integer between 1-16
parameter C_AXI_ADDR_WIDTH = 32, // This is AXI address width for all
// SI and MI slots
parameter C_AXI_DATA_WIDTH = 32, // Width of the AXI write and read data
parameter C_AXI_NBURST_SUPPORT = 0, // Support for narrow burst transfers
// 1-supported, 0-not supported
parameter C_EN_WRAP_TRANS = 0, // Set 1 to enable wrap transactions
parameter C_BEGIN_ADDRESS = 0, // Start address of the address map
parameter C_END_ADDRESS = 32'hFFFF_FFFF, // End address of the address map
parameter DBG_WR_STS_WIDTH = 32,
parameter DBG_RD_STS_WIDTH = 32,
parameter ENFORCE_RD_WR = 0,
parameter ENFORCE_RD_WR_CMD = 8'h11,
parameter EN_UPSIZER = 0,
parameter ENFORCE_RD_WR_PATTERN = 3'b000
)
(
input aclk, // AXI input clock
input aresetn, // Active low AXI reset signal
// Input control signals
input init_cmptd, // Initialization completed
input init_test, // Initialize the test
input wdog_mask, // Mask the watchdog timeouts
input wrap_en, // Enable wrap transactions
// AXI write address channel signals
input axi_wready, // Indicates slave is ready to accept a
output [C_AXI_ID_WIDTH-1:0] axi_wid, // Write ID
output [C_AXI_ADDR_WIDTH-1:0] axi_waddr, // Write address
output [7:0] axi_wlen, // Write Burst Length
output [2:0] axi_wsize, // Write Burst size
output [1:0] axi_wburst, // Write Burst type
output [1:0] axi_wlock, // Write lock type
output [3:0] axi_wcache, // Write Cache type
output [2:0] axi_wprot, // Write Protection type
output axi_wvalid, // Write address valid
// AXI write data channel signals
input axi_wd_wready, // Write data ready
output [C_AXI_ID_WIDTH-1:0] axi_wd_wid, // Write ID tag
output [C_AXI_DATA_WIDTH-1:0] axi_wd_data, // Write data
output [C_AXI_DATA_WIDTH/8-1:0] axi_wd_strb, // Write strobes
output axi_wd_last, // Last write transaction
output axi_wd_valid, // Write valid
// AXI write response channel signals
input [C_AXI_ID_WIDTH-1:0] axi_wd_bid, // Response ID
input [1:0] axi_wd_bresp, // Write response
input axi_wd_bvalid, // Write reponse valid
output axi_wd_bready, // Response ready
// AXI read address channel signals
input axi_rready, // Read address ready
output [C_AXI_ID_WIDTH-1:0] axi_rid, // Read ID
output [C_AXI_ADDR_WIDTH-1:0] axi_raddr, // Read address
output [7:0] axi_rlen, // Read Burst Length
output [2:0] axi_rsize, // Read Burst size
output [1:0] axi_rburst, // Read Burst type
output [1:0] axi_rlock, // Read lock type
output [3:0] axi_rcache, // Read Cache type
output [2:0] axi_rprot, // Read Protection type
output axi_rvalid, // Read address valid
// AXI read data channel signals
input [C_AXI_ID_WIDTH-1:0] axi_rd_bid, // Response ID
input [1:0] axi_rd_rresp, // Read response
input axi_rd_rvalid, // Read reponse valid
input [C_AXI_DATA_WIDTH-1:0] axi_rd_data, // Read data
input axi_rd_last, // Read last
output axi_rd_rready, // Read Response ready
// Error status signals
output cmd_err, // Error during command phase
output data_msmatch_err, // Data mismatch
output write_err, // Write error occured
output read_err, // Read error occured
output test_cmptd, // Data pattern test completed
output write_cmptd, // Write test completed
output read_cmptd, // Read test completed
output cmptd_cycle, // Indicates eight transactions completed
output reg cmptd_one_wr_rd, // Completed atleast one write
// and read
// Debug status signals
output dbg_wr_sts_vld, // Write debug status valid,
output [DBG_WR_STS_WIDTH-1:0] dbg_wr_sts, // Write status
output dbg_rd_sts_vld, // Read debug status valid
output [DBG_RD_STS_WIDTH-1:0] dbg_rd_sts // Read status
);
//*****************************************************************************
// Parameter declarations
//*****************************************************************************
localparam CTL_SIG_WIDTH = 3; // Control signal width
localparam RD_STS_WIDTH = 16; // Read port status signal width
localparam WDG_TIMER_WIDTH = 9;
localparam WR_STS_WIDTH = 16; // Write port status signal width
//*****************************************************************************
// Internal register and wire declarations
//*****************************************************************************
wire cmd_en;
wire [2:0] cmd;
wire [7:0] blen;
wire [31:0] addr;
wire [CTL_SIG_WIDTH-1:0] ctl;
wire cmd_ack;
// User interface write ports
wire wrdata_vld;
wire [C_AXI_DATA_WIDTH-1:0] wrdata;
wire [C_AXI_DATA_WIDTH/8-1:0] wrdata_bvld;
wire wrdata_cmptd;
wire wrdata_rdy;
wire wrdata_sts_vld;
wire [WR_STS_WIDTH-1:0] wrdata_sts;
// User interface read ports
wire rddata_rdy;
wire rddata_vld;
wire [C_AXI_DATA_WIDTH-1:0] rddata;
wire [C_AXI_DATA_WIDTH/8-1:0] rddata_bvld;
wire rddata_cmptd;
wire [RD_STS_WIDTH-1:0] rddata_sts;
reg cmptd_one_wr;
reg cmptd_one_rd;
//*****************************************************************************
// AXI4 wrapper instance
//*****************************************************************************
axi4_wrapper #(
.C_AXI_ID_WIDTH (C_AXI_ID_WIDTH),
.C_AXI_ADDR_WIDTH (C_AXI_ADDR_WIDTH),
.C_AXI_DATA_WIDTH (C_AXI_DATA_WIDTH),
.C_AXI_NBURST_SUPPORT (C_AXI_NBURST_SUPPORT),
.C_BEGIN_ADDRESS (C_BEGIN_ADDRESS),
.C_END_ADDRESS (C_END_ADDRESS),
.CTL_SIG_WIDTH (CTL_SIG_WIDTH),
.WR_STS_WIDTH (WR_STS_WIDTH),
.RD_STS_WIDTH (RD_STS_WIDTH),
.EN_UPSIZER (EN_UPSIZER),
.WDG_TIMER_WIDTH (WDG_TIMER_WIDTH)
) axi4_wrapper_inst
(
.aclk (aclk),
.aresetn (aresetn),
// User interface command port
.cmd_en (cmd_en),
.cmd (cmd),
.blen (blen),
.addr (addr),
.ctl (ctl),
.wdog_mask (wdog_mask),
.cmd_ack (cmd_ack),
// User interface write ports
.wrdata_vld (wrdata_vld),
.wrdata (wrdata),
.wrdata_bvld (wrdata_bvld),
.wrdata_cmptd (wrdata_cmptd),
.wrdata_rdy (wrdata_rdy),
.wrdata_sts_vld (wrdata_sts_vld),
.wrdata_sts (wrdata_sts),
// User interface read ports
.rddata_rdy (rddata_rdy),
.rddata_vld (rddata_vld),
.rddata (rddata),
.rddata_bvld (rddata_bvld),
.rddata_cmptd (rddata_cmptd),
.rddata_sts (rddata_sts),
// AXI write address channel signals
.axi_wready (axi_wready),
.axi_wid (axi_wid),
.axi_waddr (axi_waddr),
.axi_wlen (axi_wlen),
.axi_wsize (axi_wsize),
.axi_wburst (axi_wburst),
.axi_wlock (axi_wlock),
.axi_wcache (axi_wcache),
.axi_wprot (axi_wprot),
.axi_wvalid (axi_wvalid),
// AXI write data channel signals
.axi_wd_wready (axi_wd_wready),
.axi_wd_wid (axi_wd_wid),
.axi_wd_data (axi_wd_data),
.axi_wd_strb (axi_wd_strb),
.axi_wd_last (axi_wd_last),
.axi_wd_valid (axi_wd_valid),
// AXI write response channel signals
.axi_wd_bid (axi_wd_bid),
.axi_wd_bresp (axi_wd_bresp),
.axi_wd_bvalid (axi_wd_bvalid),
.axi_wd_bready (axi_wd_bready),
// AXI read address channel signals
.axi_rready (axi_rready),
.axi_rid (axi_rid),
.axi_raddr (axi_raddr),
.axi_rlen (axi_rlen),
.axi_rsize (axi_rsize),
.axi_rburst (axi_rburst),
.axi_rlock (axi_rlock),
.axi_rcache (axi_rcache),
.axi_rprot (axi_rprot),
.axi_rvalid (axi_rvalid),
// AXI read data channel signals
.axi_rd_bid (axi_rd_bid),
.axi_rd_rresp (axi_rd_rresp),
.axi_rd_rvalid (axi_rd_rvalid),
.axi_rd_data (axi_rd_data),
.axi_rd_last (axi_rd_last),
.axi_rd_rready (axi_rd_rready)
);
//*****************************************************************************
// Traffic Generator instance
//*****************************************************************************
tg #(
.C_AXI_ADDR_WIDTH (C_AXI_ADDR_WIDTH),
.C_AXI_DATA_WIDTH (C_AXI_DATA_WIDTH),
.C_AXI_NBURST_SUPPORT (C_AXI_NBURST_SUPPORT),
.C_BEGIN_ADDRESS (C_BEGIN_ADDRESS),
.C_END_ADDRESS (C_END_ADDRESS),
.C_EN_WRAP_TRANS (C_EN_WRAP_TRANS),
.CTL_SIG_WIDTH (CTL_SIG_WIDTH),
.WR_STS_WIDTH (WR_STS_WIDTH),
.RD_STS_WIDTH (RD_STS_WIDTH),
.DBG_WR_STS_WIDTH (DBG_WR_STS_WIDTH),
.DBG_RD_STS_WIDTH (DBG_RD_STS_WIDTH),
.ENFORCE_RD_WR (ENFORCE_RD_WR),
.ENFORCE_RD_WR_CMD (ENFORCE_RD_WR_CMD),
.ENFORCE_RD_WR_PATTERN (ENFORCE_RD_WR_PATTERN)
) traffic_gen_inst
(
.clk (aclk),
.resetn (aresetn),
// Input start signals
.init_cmptd (init_cmptd),
.init_test (init_test),
.wrap_en (wrap_en),
// Control ports
.cmd_ack (cmd_ack),
.cmd_en (cmd_en),
.cmd (cmd),
.blen (blen),
.addr (addr),
.ctl (ctl),
// Write port
.wdata_rdy (wrdata_rdy),
.wdata_vld (wrdata_vld),
.wdata_cmptd (wrdata_cmptd),
.wdata (wrdata),
.wdata_bvld (wrdata_bvld),
.wdata_sts_vld (wrdata_sts_vld),
.wdata_sts (wrdata_sts),
// Read Port
.rdata_vld (rddata_vld),
.rdata (rddata),
.rdata_bvld (rddata_bvld),
.rdata_cmptd (rddata_cmptd),
.rdata_sts (rddata_sts),
.rdata_rdy (rddata_rdy),
// Error status signals
.cmd_err (cmd_err),
.data_msmatch_err (data_msmatch_err),
.write_err (write_err),
.read_err (read_err),
.test_cmptd (test_cmptd),
.write_cmptd (write_cmptd),
.read_cmptd (read_cmptd),
.cmptd_cycle (cmptd_cycle),
// Debug status signals
.dbg_wr_sts_vld (dbg_wr_sts_vld),
.dbg_wr_sts (dbg_wr_sts),
.dbg_rd_sts_vld (dbg_rd_sts_vld),
.dbg_rd_sts (dbg_rd_sts)
);
always @(posedge aclk)
if (!aresetn)
cmptd_one_wr <= 1'b0;
else if (write_cmptd)
cmptd_one_wr <= 1'b1;
always @(posedge aclk)
if (!aresetn)
cmptd_one_rd <= 1'b0;
else if (read_cmptd)
cmptd_one_rd <= 1'b1;
always @(posedge aclk)
if (!aresetn)
cmptd_one_wr_rd <= 1'b0;
else if (cmptd_one_wr & cmptd_one_rd)
cmptd_one_wr_rd <= 1'b1;
endmodule
|
module mcb_soft_calibration_top # (
parameter C_MEM_TZQINIT_MAXCNT = 10'h512, // DDR3 Minimum delay between resets
parameter C_MC_CALIBRATION_MODE = "CALIBRATION", // if set to CALIBRATION will reset DQS IDELAY to DQS_NUMERATOR/DQS_DENOMINATOR local_param values, and does dynamic recal,
// if set to NOCALIBRATION then defaults to hard cal blocks setting of C_MC_CALBRATION_DELAY *and* no dynamic recal will be done
parameter SKIP_IN_TERM_CAL = 1'b0, // provides option to skip the input termination calibration
parameter SKIP_DYNAMIC_CAL = 1'b0, // provides option to skip the dynamic delay calibration
parameter SKIP_DYN_IN_TERM = 1'b0, // provides option to skip the input termination calibration
parameter C_SIMULATION = "FALSE", // Tells us whether the design is being simulated or implemented
parameter C_MEM_TYPE = "DDR" // provides the memory device used for the design
)
(
input wire UI_CLK, // Input - global clock to be used for input_term_tuner and IODRP clock
input wire RST, // Input - reset for input_term_tuner - synchronous for input_term_tuner state machine, asynch for IODRP (sub)controller
input wire IOCLK, // Input - IOCLK input to the IODRP's
output wire DONE_SOFTANDHARD_CAL, // active high flag signals soft calibration of input delays is complete and MCB_UODONECAL is high (MCB hard calib complete)
input wire PLL_LOCK, // Lock signal from PLL
input wire SELFREFRESH_REQ,
input wire SELFREFRESH_MCB_MODE,
output wire SELFREFRESH_MCB_REQ ,
output wire SELFREFRESH_MODE,
output wire MCB_UIADD, // to MCB's UIADD port
output wire MCB_UISDI, // to MCB's UISDI port
input wire MCB_UOSDO,
input wire MCB_UODONECAL,
input wire MCB_UOREFRSHFLAG,
output wire MCB_UICS,
output wire MCB_UIDRPUPDATE,
output wire MCB_UIBROADCAST,
output wire [4:0] MCB_UIADDR,
output wire MCB_UICMDEN,
output wire MCB_UIDONECAL,
output wire MCB_UIDQLOWERDEC,
output wire MCB_UIDQLOWERINC,
output wire MCB_UIDQUPPERDEC,
output wire MCB_UIDQUPPERINC,
output wire MCB_UILDQSDEC,
output wire MCB_UILDQSINC,
output wire MCB_UIREAD,
output wire MCB_UIUDQSDEC,
output wire MCB_UIUDQSINC,
output wire MCB_RECAL,
output wire MCB_SYSRST,
output wire MCB_UICMD,
output wire MCB_UICMDIN,
output wire [3:0] MCB_UIDQCOUNT,
input wire [7:0] MCB_UODATA,
input wire MCB_UODATAVALID,
input wire MCB_UOCMDREADY,
input wire MCB_UO_CAL_START,
inout wire RZQ_Pin,
inout wire ZIO_Pin,
output wire CKE_Train
);
wire IODRP_ADD;
wire IODRP_SDI;
wire RZQ_IODRP_SDO;
wire RZQ_IODRP_CS;
wire ZIO_IODRP_SDO;
wire ZIO_IODRP_CS;
wire IODRP_SDO;
wire IODRP_CS;
wire IODRP_BKST;
wire RZQ_ZIO_ODATAIN;
wire RZQ_ZIO_TRISTATE;
wire RZQ_TOUT;
wire ZIO_TOUT;
wire [7:0] Max_Value;
wire ZIO_IN;
wire RZQ_IN;
reg ZIO_IN_R1, ZIO_IN_R2;
reg RZQ_IN_R1, RZQ_IN_R2;
assign RZQ_ZIO_ODATAIN = ~RST;
assign RZQ_ZIO_TRISTATE = ~RST;
assign IODRP_BKST = 1'b0; //future hook for possible BKST to ZIO and RZQ
mcb_soft_calibration #(
.C_MEM_TZQINIT_MAXCNT (C_MEM_TZQINIT_MAXCNT),
.C_MC_CALIBRATION_MODE(C_MC_CALIBRATION_MODE),
.SKIP_IN_TERM_CAL (SKIP_IN_TERM_CAL),
.SKIP_DYNAMIC_CAL (SKIP_DYNAMIC_CAL),
.SKIP_DYN_IN_TERM (SKIP_DYN_IN_TERM),
.C_SIMULATION (C_SIMULATION),
.C_MEM_TYPE (C_MEM_TYPE)
)
mcb_soft_calibration_inst (
.UI_CLK (UI_CLK), // main clock input for logic and IODRP CLK pins. At top level, this should also connect to IODRP2_MCB CLK pins
.RST (RST), // main system reset for both this Soft Calibration block - also will act as a passthrough to MCB's SYSRST
.PLL_LOCK (PLL_LOCK), //lock signal from PLL
.SELFREFRESH_REQ (SELFREFRESH_REQ),
.SELFREFRESH_MCB_MODE (SELFREFRESH_MCB_MODE),
.SELFREFRESH_MCB_REQ (SELFREFRESH_MCB_REQ ),
.SELFREFRESH_MODE (SELFREFRESH_MODE),
.DONE_SOFTANDHARD_CAL (DONE_SOFTANDHARD_CAL),// active high flag signals soft calibration of input delays is complete and MCB_UODONECAL is high (MCB hard calib complete) .IODRP_ADD(IODRP_ADD), // RZQ and ZIO IODRP ADD port, and MCB's UIADD port
.IODRP_ADD (IODRP_ADD), // RZQ and ZIO IODRP ADD port
.IODRP_SDI (IODRP_SDI), // RZQ and ZIO IODRP SDI port, and MCB's UISDI port
.RZQ_IN (RZQ_IN_R2), // RZQ pin from board - expected to have a 2*R resistor to ground
.RZQ_IODRP_SDO (RZQ_IODRP_SDO), // RZQ IODRP's SDO port
.RZQ_IODRP_CS (RZQ_IODRP_CS), // RZQ IODRP's CS port
.ZIO_IN (ZIO_IN_R2), // Z-stated IO pin - garanteed not to be driven externally
.ZIO_IODRP_SDO (ZIO_IODRP_SDO), // ZIO IODRP's SDO port
.ZIO_IODRP_CS (ZIO_IODRP_CS), // ZIO IODRP's CS port
.MCB_UIADD (MCB_UIADD), // to MCB's UIADD port
.MCB_UISDI (MCB_UISDI), // to MCB's UISDI port
.MCB_UOSDO (MCB_UOSDO), // from MCB's UOSDO port (User output SDO)
.MCB_UODONECAL (MCB_UODONECAL), // indicates when MCB hard calibration process is complete
.MCB_UOREFRSHFLAG (MCB_UOREFRSHFLAG), //high during refresh cycle and time when MCB is innactive
.MCB_UICS (MCB_UICS), // to MCB's UICS port (User Input CS)
.MCB_UIDRPUPDATE (MCB_UIDRPUPDATE), // MCB's UIDRPUPDATE port (gets passed to IODRP2_MCB's MEMUPDATE port: this controls shadow latch used during IODRP2_MCB writes). Currently just trasnparent
.MCB_UIBROADCAST (MCB_UIBROADCAST), // to MCB's UIBROADCAST port (User Input BROADCAST - gets passed to IODRP2_MCB's BKST port)
.MCB_UIADDR (MCB_UIADDR), //to MCB's UIADDR port (gets passed to IODRP2_MCB's AUXADDR port
.MCB_UICMDEN (MCB_UICMDEN), //set to take control of UI interface - removes control from internal calib block
.MCB_UIDONECAL (MCB_UIDONECAL),
.MCB_UIDQLOWERDEC (MCB_UIDQLOWERDEC),
.MCB_UIDQLOWERINC (MCB_UIDQLOWERINC),
.MCB_UIDQUPPERDEC (MCB_UIDQUPPERDEC),
.MCB_UIDQUPPERINC (MCB_UIDQUPPERINC),
.MCB_UILDQSDEC (MCB_UILDQSDEC),
.MCB_UILDQSINC (MCB_UILDQSINC),
.MCB_UIREAD (MCB_UIREAD), //enables read w/o writing by turning on a SDO->SDI loopback inside the IODRP2_MCBs (doesn't exist in regular IODRP2). IODRPCTRLR_R_WB becomes don't-care.
.MCB_UIUDQSDEC (MCB_UIUDQSDEC),
.MCB_UIUDQSINC (MCB_UIUDQSINC),
.MCB_RECAL (MCB_RECAL), //when high initiates a hard re-calibration sequence
.MCB_UICMD (MCB_UICMD ),
.MCB_UICMDIN (MCB_UICMDIN ),
.MCB_UIDQCOUNT (MCB_UIDQCOUNT ),
.MCB_UODATA (MCB_UODATA ),
.MCB_UODATAVALID (MCB_UODATAVALID ),
.MCB_UOCMDREADY (MCB_UOCMDREADY ),
.MCB_UO_CAL_START (MCB_UO_CAL_START),
.MCB_SYSRST (MCB_SYSRST ), //drives the MCB's SYSRST pin - the main reset for MCB
.Max_Value (Max_Value ), // Maximum Tap Value from calibrated IOI
.CKE_Train (CKE_Train)
);
always@(posedge UI_CLK,posedge RST)
if (RST)
begin
ZIO_IN_R1 <= 1'b0;
ZIO_IN_R2 <= 1'b0;
RZQ_IN_R1 <= 1'b0;
RZQ_IN_R2 <= 1'b0;
end
else
begin
ZIO_IN_R1 <= ZIO_IN;
ZIO_IN_R2 <= ZIO_IN_R1;
RZQ_IN_R1 <= RZQ_IN;
RZQ_IN_R2 <= RZQ_IN_R1;
end
IOBUF IOBUF_RZQ (
.O (RZQ_IN),
.IO (RZQ_Pin),
.I (RZQ_OUT),
.T (RZQ_TOUT)
);
IODRP2 IODRP2_RZQ (
.DATAOUT(),
.DATAOUT2(),
.DOUT(RZQ_OUT),
.SDO(RZQ_IODRP_SDO),
.TOUT(RZQ_TOUT),
.ADD(IODRP_ADD),
.BKST(IODRP_BKST),
.CLK(UI_CLK),
.CS(RZQ_IODRP_CS),
.IDATAIN(RZQ_IN),
.IOCLK0(IOCLK),
.IOCLK1(1'b1),
.ODATAIN(RZQ_ZIO_ODATAIN),
.SDI(IODRP_SDI),
.T(RZQ_ZIO_TRISTATE)
);
generate
if ((C_MEM_TYPE == "DDR" || C_MEM_TYPE == "DDR2" || C_MEM_TYPE == "DDR3") &&
(SKIP_IN_TERM_CAL == 1'b0)
) begin : gen_zio
IOBUF IOBUF_ZIO (
.O (ZIO_IN),
.IO (ZIO_Pin),
.I (ZIO_OUT),
.T (ZIO_TOUT)
);
IODRP2 IODRP2_ZIO (
.DATAOUT(),
.DATAOUT2(),
.DOUT(ZIO_OUT),
.SDO(ZIO_IODRP_SDO),
.TOUT(ZIO_TOUT),
.ADD(IODRP_ADD),
.BKST(IODRP_BKST),
.CLK(UI_CLK),
.CS(ZIO_IODRP_CS),
.IDATAIN(ZIO_IN),
.IOCLK0(IOCLK),
.IOCLK1(1'b1),
.ODATAIN(RZQ_ZIO_ODATAIN),
.SDI(IODRP_SDI),
.T(RZQ_ZIO_TRISTATE)
);
end
endgenerate
endmodule
|
module iodrp_controller(
input wire [7:0] memcell_address,
input wire [7:0] write_data,
output reg [7:0] read_data,
input wire rd_not_write,
input wire cmd_valid,
output wire rdy_busy_n,
input wire use_broadcast,
input wire sync_rst,
input wire DRP_CLK,
output reg DRP_CS,
output wire DRP_SDI, //output to IODRP SDI pin
output reg DRP_ADD,
output reg DRP_BKST,
input wire DRP_SDO //input from IODRP SDO pin
);
reg [7:0] memcell_addr_reg; // Register where memcell_address is captured during the READY state
reg [7:0] data_reg; // Register which stores the write data until it is ready to be shifted out
reg [7:0] shift_through_reg; // The shift register which shifts out SDO and shifts in SDI.
// This register is loaded before the address or data phase, but continues
// to shift for a writeback of read data
reg load_shift_n; // The signal which causes shift_through_reg to load the new value from data_out_mux, or continue to shift data in from DRP_SDO
reg addr_data_sel_n; // The signal which indicates where the shift_through_reg should load from. 0 -> data_reg 1 -> memcell_addr_reg
reg [2:0] bit_cnt; // The counter for which bit is being shifted during address or data phase
reg rd_not_write_reg;
reg AddressPhase; // This is set after the first address phase has executed
reg capture_read_data;
(* FSM_ENCODING="one-hot" *) reg [2:0] state, nextstate;
wire [7:0] data_out_mux; // The mux which selects between data_reg and memcell_addr_reg for sending to shift_through_reg
wire DRP_SDI_pre; // added so that DRP_SDI output is only active when DRP_CS is active
localparam READY = 3'h0;
localparam DECIDE = 3'h1;
localparam ADDR_PHASE = 3'h2;
localparam ADDR_TO_DATA_GAP = 3'h3;
localparam ADDR_TO_DATA_GAP2 = 3'h4;
localparam ADDR_TO_DATA_GAP3 = 3'h5;
localparam DATA_PHASE = 3'h6;
localparam ALMOST_READY = 3'h7;
localparam IOI_DQ0 = 5'h01;
localparam IOI_DQ1 = 5'h00;
localparam IOI_DQ2 = 5'h03;
localparam IOI_DQ3 = 5'h02;
localparam IOI_DQ4 = 5'h05;
localparam IOI_DQ5 = 5'h04;
localparam IOI_DQ6 = 5'h07;
localparam IOI_DQ7 = 5'h06;
localparam IOI_DQ8 = 5'h09;
localparam IOI_DQ9 = 5'h08;
localparam IOI_DQ10 = 5'h0B;
localparam IOI_DQ11 = 5'h0A;
localparam IOI_DQ12 = 5'h0D;
localparam IOI_DQ13 = 5'h0C;
localparam IOI_DQ14 = 5'h0F;
localparam IOI_DQ15 = 5'h0E;
localparam IOI_UDQS_CLK = 5'h1D;
localparam IOI_UDQS_PIN = 5'h1C;
localparam IOI_LDQS_CLK = 5'h1F;
localparam IOI_LDQS_PIN = 5'h1E;
//synthesis translate_off
reg [32*8-1:0] state_ascii;
always @ (state) begin
case (state)
READY :state_ascii <= "READY";
DECIDE :state_ascii <= "DECIDE";
ADDR_PHASE :state_ascii <= "ADDR_PHASE";
ADDR_TO_DATA_GAP :state_ascii <= "ADDR_TO_DATA_GAP";
ADDR_TO_DATA_GAP2 :state_ascii <= "ADDR_TO_DATA_GAP2";
ADDR_TO_DATA_GAP3 :state_ascii <= "ADDR_TO_DATA_GAP3";
DATA_PHASE :state_ascii <= "DATA_PHASE";
ALMOST_READY :state_ascii <= "ALMOST_READY";
endcase // case(state)
end
//synthesis translate_on
/*********************************************
* Input Registers
*********************************************/
always @ (posedge DRP_CLK) begin
if(state == READY) begin
memcell_addr_reg <= memcell_address;
data_reg <= write_data;
rd_not_write_reg <= rd_not_write;
end
end
assign rdy_busy_n = (state == READY);
/*********************************************
* Shift Registers / Bit Counter
*********************************************/
assign data_out_mux = addr_data_sel_n ? memcell_addr_reg : data_reg;
always @ (posedge DRP_CLK) begin
if(sync_rst)
shift_through_reg <= 8'b0;
else begin
if (load_shift_n) //Assume the shifter is either loading or shifting, bit 0 is shifted out first
shift_through_reg <= data_out_mux;
else
shift_through_reg <= {DRP_SDO, shift_through_reg[7:1]};
end
end
always @ (posedge DRP_CLK) begin
if (((state == ADDR_PHASE) | (state == DATA_PHASE)) & !sync_rst)
bit_cnt <= bit_cnt + 1;
else
bit_cnt <= 3'b000;
end
always @ (posedge DRP_CLK) begin
if(sync_rst) begin
read_data <= 8'h00;
// capture_read_data <= 1'b0;
end
else begin
// capture_read_data <= (state == DATA_PHASE);
// if(capture_read_data)
if(state == ALMOST_READY)
read_data <= shift_through_reg;
// else
// read_data <= read_data;
end
end
always @ (posedge DRP_CLK) begin
if(sync_rst) begin
AddressPhase <= 1'b0;
end
else begin
if (AddressPhase) begin
// Keep it set until we finish the cycle
AddressPhase <= AddressPhase && ~(state == ALMOST_READY);
end
else begin
// set the address phase when ever we finish the address phase
AddressPhase <= (state == ADDR_PHASE) && (bit_cnt == 3'b111);
end
end
end
/*********************************************
* DRP Signals
*********************************************/
always @ (posedge DRP_CLK) begin
DRP_ADD <= (nextstate == ADDR_PHASE);
DRP_CS <= (nextstate == ADDR_PHASE) | (nextstate == DATA_PHASE);
if (state == READY)
DRP_BKST <= use_broadcast;
end
// assign DRP_SDI_pre = (DRP_CS)? shift_through_reg[0] : 1'b0; //if DRP_CS is inactive, just drive 0 out - this is a possible place to pipeline for increased performance
// assign DRP_SDI = (rd_not_write_reg & DRP_CS & !DRP_ADD)? DRP_SDO : DRP_SDI_pre; //If reading, then feed SDI back out SDO - this is a possible place to pipeline for increased performance
assign DRP_SDI = shift_through_reg[0]; // The new read method only requires that we shift out the address and the write data
/*********************************************
* State Machine
*********************************************/
always @ (*) begin
addr_data_sel_n = 1'b0;
load_shift_n = 1'b0;
case (state)
READY: begin
if(cmd_valid)
nextstate = DECIDE;
else
nextstate = READY;
end
DECIDE: begin
load_shift_n = 1;
addr_data_sel_n = 1;
nextstate = ADDR_PHASE;
end
ADDR_PHASE: begin
if(&bit_cnt)
if (rd_not_write_reg)
if (AddressPhase)
// After the second pass go to end of statemachine
nextstate = ALMOST_READY;
else
// execute a second address phase for the read access.
nextstate = DECIDE;
else
nextstate = ADDR_TO_DATA_GAP;
else
nextstate = ADDR_PHASE;
end
ADDR_TO_DATA_GAP: begin
load_shift_n = 1;
nextstate = ADDR_TO_DATA_GAP2;
end
ADDR_TO_DATA_GAP2: begin
load_shift_n = 1;
nextstate = ADDR_TO_DATA_GAP3;
end
ADDR_TO_DATA_GAP3: begin
load_shift_n = 1;
nextstate = DATA_PHASE;
end
DATA_PHASE: begin
if(&bit_cnt)
nextstate = ALMOST_READY;
else
nextstate = DATA_PHASE;
end
ALMOST_READY: begin
nextstate = READY;
end
default: begin
nextstate = READY;
end
endcase
end
always @ (posedge DRP_CLK) begin
if(sync_rst)
state <= READY;
else
state <= nextstate;
end
endmodule
|
module iodrp_mcb_controller(
input wire [7:0] memcell_address,
input wire [7:0] write_data,
output reg [7:0] read_data = 0,
input wire rd_not_write,
input wire cmd_valid,
output wire rdy_busy_n,
input wire use_broadcast,
input wire [4:0] drp_ioi_addr,
input wire sync_rst,
input wire DRP_CLK,
output reg DRP_CS,
output wire DRP_SDI, //output to IODRP SDI pin
output reg DRP_ADD,
output reg DRP_BKST,
input wire DRP_SDO, //input from IODRP SDO pin
output reg MCB_UIREAD = 1'b0
);
reg [7:0] memcell_addr_reg; // Register where memcell_address is captured during the READY state
reg [7:0] data_reg; // Register which stores the write data until it is ready to be shifted out
reg [8:0] shift_through_reg; // The shift register which shifts out SDO and shifts in SDI.
// This register is loaded before the address or data phase, but continues to shift for a writeback of read data
reg load_shift_n; // The signal which causes shift_through_reg to load the new value from data_out_mux, or continue to shift data in from DRP_SDO
reg addr_data_sel_n; // The signal which indicates where the shift_through_reg should load from. 0 -> data_reg 1 -> memcell_addr_reg
reg [2:0] bit_cnt= 3'b0; // The counter for which bit is being shifted during address or data phase
reg rd_not_write_reg;
reg AddressPhase; // This is set after the first address phase has executed
reg DRP_CS_pre;
reg extra_cs;
(* FSM_ENCODING="GRAY" *) reg [3:0] state, nextstate;
wire [8:0] data_out;
reg [8:0] data_out_mux; // The mux which selects between data_reg and memcell_addr_reg for sending to shift_through_reg
wire DRP_SDI_pre; //added so that DRP_SDI output is only active when DRP_CS is active
localparam READY = 4'h0;
localparam DECIDE = 4'h1;
localparam ADDR_PHASE = 4'h2;
localparam ADDR_TO_DATA_GAP = 4'h3;
localparam ADDR_TO_DATA_GAP2 = 4'h4;
localparam ADDR_TO_DATA_GAP3 = 4'h5;
localparam DATA_PHASE = 4'h6;
localparam ALMOST_READY = 4'h7;
localparam ALMOST_READY2 = 4'h8;
localparam ALMOST_READY3 = 4'h9;
localparam IOI_DQ0 = 5'h01;
localparam IOI_DQ1 = 5'h00;
localparam IOI_DQ2 = 5'h03;
localparam IOI_DQ3 = 5'h02;
localparam IOI_DQ4 = 5'h05;
localparam IOI_DQ5 = 5'h04;
localparam IOI_DQ6 = 5'h07;
localparam IOI_DQ7 = 5'h06;
localparam IOI_DQ8 = 5'h09;
localparam IOI_DQ9 = 5'h08;
localparam IOI_DQ10 = 5'h0B;
localparam IOI_DQ11 = 5'h0A;
localparam IOI_DQ12 = 5'h0D;
localparam IOI_DQ13 = 5'h0C;
localparam IOI_DQ14 = 5'h0F;
localparam IOI_DQ15 = 5'h0E;
localparam IOI_UDQS_CLK = 5'h1D;
localparam IOI_UDQS_PIN = 5'h1C;
localparam IOI_LDQS_CLK = 5'h1F;
localparam IOI_LDQS_PIN = 5'h1E;
//synthesis translate_off
reg [32*8-1:0] state_ascii;
always @ (state) begin
case (state)
READY :state_ascii<="READY";
DECIDE :state_ascii<="DECIDE";
ADDR_PHASE :state_ascii<="ADDR_PHASE";
ADDR_TO_DATA_GAP :state_ascii<="ADDR_TO_DATA_GAP";
ADDR_TO_DATA_GAP2 :state_ascii<="ADDR_TO_DATA_GAP2";
ADDR_TO_DATA_GAP3 :state_ascii<="ADDR_TO_DATA_GAP3";
DATA_PHASE :state_ascii<="DATA_PHASE";
ALMOST_READY :state_ascii<="ALMOST_READY";
ALMOST_READY2 :state_ascii<="ALMOST_READY2";
ALMOST_READY3 :state_ascii<="ALMOST_READY3";
endcase // case(state)
end
//synthesis translate_on
/*********************************************
* Input Registers
*********************************************/
always @ (posedge DRP_CLK) begin
if(state == READY) begin
memcell_addr_reg <= memcell_address;
data_reg <= write_data;
rd_not_write_reg <= rd_not_write;
end
end
assign rdy_busy_n = (state == READY);
// The changes below are to compensate for an issue with 1.0 silicon.
// It may still be necessary to add a clock cycle to the ADD and CS signals
//`define DRP_v1_0_FIX // Uncomment out this line for synthesis
task shift_n_expand (
input [7:0] data_in,
output [8:0] data_out
);
begin
if (data_in[0])
data_out[1:0] = 2'b11;
else
data_out[1:0] = 2'b00;
if (data_in[1:0] == 2'b10)
data_out[2:1] = 2'b11;
else
data_out[2:1] = {data_in[1], data_out[1]};
if (data_in[2:1] == 2'b10)
data_out[3:2] = 2'b11;
else
data_out[3:2] = {data_in[2], data_out[2]};
if (data_in[3:2] == 2'b10)
data_out[4:3] = 2'b11;
else
data_out[4:3] = {data_in[3], data_out[3]};
if (data_in[4:3] == 2'b10)
data_out[5:4] = 2'b11;
else
data_out[5:4] = {data_in[4], data_out[4]};
if (data_in[5:4] == 2'b10)
data_out[6:5] = 2'b11;
else
data_out[6:5] = {data_in[5], data_out[5]};
if (data_in[6:5] == 2'b10)
data_out[7:6] = 2'b11;
else
data_out[7:6] = {data_in[6], data_out[6]};
if (data_in[7:6] == 2'b10)
data_out[8:7] = 2'b11;
else
data_out[8:7] = {data_in[7], data_out[7]};
end
endtask
always @(*) begin
case(drp_ioi_addr)
`ifdef DRP_v1_0_FIX
IOI_DQ0 : data_out_mux = data_out<<1;
IOI_DQ1 : data_out_mux = data_out;
IOI_DQ2 : data_out_mux = data_out<<1;
// IOI_DQ2 : data_out_mux = data_out;
IOI_DQ3 : data_out_mux = data_out;
IOI_DQ4 : data_out_mux = data_out;
IOI_DQ5 : data_out_mux = data_out;
IOI_DQ6 : shift_n_expand (data_out, data_out_mux);
// IOI_DQ6 : data_out_mux = data_out;
IOI_DQ7 : data_out_mux = data_out;
IOI_DQ8 : data_out_mux = data_out<<1;
IOI_DQ9 : data_out_mux = data_out;
IOI_DQ10 : data_out_mux = data_out<<1;
IOI_DQ11 : data_out_mux = data_out;
IOI_DQ12 : data_out_mux = data_out<<1;
IOI_DQ13 : data_out_mux = data_out;
IOI_DQ14 : data_out_mux = data_out<<1;
IOI_DQ15 : data_out_mux = data_out;
IOI_UDQS_CLK : data_out_mux = data_out<<1;
IOI_UDQS_PIN : data_out_mux = data_out<<1;
IOI_LDQS_CLK : data_out_mux = data_out;
IOI_LDQS_PIN : data_out_mux = data_out;
`else
`endif
IOI_DQ0 : data_out_mux = data_out;
IOI_DQ1 : data_out_mux = data_out;
IOI_DQ2 : data_out_mux = data_out;
IOI_DQ3 : data_out_mux = data_out;
IOI_DQ4 : data_out_mux = data_out;
IOI_DQ5 : data_out_mux = data_out;
IOI_DQ6 : data_out_mux = data_out;
IOI_DQ7 : data_out_mux = data_out;
IOI_DQ8 : data_out_mux = data_out;
IOI_DQ9 : data_out_mux = data_out;
IOI_DQ10 : data_out_mux = data_out;
IOI_DQ11 : data_out_mux = data_out;
IOI_DQ12 : data_out_mux = data_out;
IOI_DQ13 : data_out_mux = data_out;
IOI_DQ14 : data_out_mux = data_out;
IOI_DQ15 : data_out_mux = data_out;
IOI_UDQS_CLK : data_out_mux = data_out;
IOI_UDQS_PIN : data_out_mux = data_out;
IOI_LDQS_CLK : data_out_mux = data_out;
IOI_LDQS_PIN : data_out_mux = data_out;
default : data_out_mux = data_out;
endcase
end
/*********************************************
* Shift Registers / Bit Counter
*********************************************/
assign data_out = (addr_data_sel_n)? {1'b0, memcell_addr_reg} : {1'b0, data_reg};
always @ (posedge DRP_CLK) begin
if(sync_rst)
shift_through_reg <= 9'b0;
else begin
if (load_shift_n) //Assume the shifter is either loading or shifting, bit 0 is shifted out first
shift_through_reg <= data_out_mux;
else
shift_through_reg <= {1'b0, DRP_SDO, shift_through_reg[7:1]};
end
end
always @ (posedge DRP_CLK) begin
if (((state == ADDR_PHASE) | (state == DATA_PHASE)) & !sync_rst)
bit_cnt <= bit_cnt + 1;
else
bit_cnt <= 3'b0;
end
always @ (posedge DRP_CLK) begin
if(sync_rst) begin
read_data <= 8'h00;
end
else begin
if(state == ALMOST_READY3)
read_data <= shift_through_reg;
end
end
always @ (posedge DRP_CLK) begin
if(sync_rst) begin
AddressPhase <= 1'b0;
end
else begin
if (AddressPhase) begin
// Keep it set until we finish the cycle
AddressPhase <= AddressPhase && ~(state == ALMOST_READY2);
end
else begin
// set the address phase when ever we finish the address phase
AddressPhase <= (state == ADDR_PHASE) && (bit_cnt == 3'b111);
end
end
end
/*********************************************
* DRP Signals
*********************************************/
always @ (posedge DRP_CLK) begin
DRP_ADD <= (nextstate == ADDR_PHASE);
DRP_CS <= (nextstate == ADDR_PHASE) | (nextstate == DATA_PHASE);
// DRP_CS <= (drp_ioi_addr != IOI_DQ0) ? (nextstate == ADDR_PHASE) | (nextstate == DATA_PHASE) : (bit_cnt != 3'b111) && (nextstate == ADDR_PHASE) | (nextstate == DATA_PHASE);
MCB_UIREAD <= (nextstate == DATA_PHASE) && rd_not_write_reg;
if (state == READY)
DRP_BKST <= use_broadcast;
end
assign DRP_SDI_pre = (DRP_CS)? shift_through_reg[0] : 1'b0; //if DRP_CS is inactive, just drive 0 out - this is a possible place to pipeline for increased performance
assign DRP_SDI = (rd_not_write_reg & DRP_CS & !DRP_ADD)? DRP_SDO : DRP_SDI_pre; //If reading, then feed SDI back out SDO - this is a possible place to pipeline for increased performance
/*********************************************
* State Machine
*********************************************/
always @ (*) begin
addr_data_sel_n = 1'b0;
load_shift_n = 1'b0;
case (state)
READY: begin
load_shift_n = 0;
if(cmd_valid)
nextstate = DECIDE;
else
nextstate = READY;
end
DECIDE: begin
load_shift_n = 1;
addr_data_sel_n = 1;
nextstate = ADDR_PHASE;
end
ADDR_PHASE: begin
load_shift_n = 0;
if(&bit_cnt[2:0])
if (`ALTERNATE_READ && rd_not_write_reg)
if (AddressPhase)
// After the second pass go to end of statemachine
nextstate = ALMOST_READY;
else
// execute a second address phase for the alternative access method.
nextstate = DECIDE;
else
nextstate = ADDR_TO_DATA_GAP;
else
nextstate = ADDR_PHASE;
end
ADDR_TO_DATA_GAP: begin
load_shift_n = 1;
nextstate = ADDR_TO_DATA_GAP2;
end
ADDR_TO_DATA_GAP2: begin
load_shift_n = 1;
nextstate = ADDR_TO_DATA_GAP3;
end
ADDR_TO_DATA_GAP3: begin
load_shift_n = 1;
nextstate = DATA_PHASE;
end
DATA_PHASE: begin
load_shift_n = 0;
if(&bit_cnt)
nextstate = ALMOST_READY;
else
nextstate = DATA_PHASE;
end
ALMOST_READY: begin
load_shift_n = 0;
nextstate = ALMOST_READY2;
end
ALMOST_READY2: begin
load_shift_n = 0;
nextstate = ALMOST_READY3;
end
ALMOST_READY3: begin
load_shift_n = 0;
nextstate = READY;
end
default: begin
load_shift_n = 0;
nextstate = READY;
end
endcase
end
always @ (posedge DRP_CLK) begin
if(sync_rst)
state <= READY;
else
state <= nextstate;
end
endmodule
|
module axi_mcb_cmd_translator #
(
///////////////////////////////////////////////////////////////////////////////
// Parameter Definitions
///////////////////////////////////////////////////////////////////////////////
// Width of AxADDR
// Range: 32.
parameter integer C_AXI_ADDR_WIDTH = 32,
// Width of cmd_byte_addr
// Range: 30
parameter integer C_MCB_ADDR_WIDTH = 30,
// Width of AXI xDATA and MCB xx_data
// Range: 32, 64, 128.
parameter integer C_DATA_WIDTH = 32,
// Width of beat counter, limits max transaction size.
// Range: 4
parameter integer C_CNT_WIDTH = 4,
// Static value of axsize
// Rannge: 2-4
parameter integer C_AXSIZE = 2,
// Register CMD_BL_SECOND for better timing. Does not add
// any latency.
parameter integer C_PL_CMD_BL_SECOND = 1
)
(
///////////////////////////////////////////////////////////////////////////////
// Port Declarations
///////////////////////////////////////////////////////////////////////////////
input wire clk ,
input wire reset ,
input wire [C_AXI_ADDR_WIDTH-1:0] axaddr ,
input wire [7:0] axlen ,
input wire [2:0] axsize ,
input wire [1:0] axburst ,
input wire axhandshake ,
output wire wrap_cmd_sel ,
output wire [C_MCB_ADDR_WIDTH-1:0] wrap_cmd_byte_addr ,
output wire [5:0] wrap_cmd_bl ,
output wire [C_MCB_ADDR_WIDTH-1:0] incr_cmd_byte_addr ,
output wire [5:0] incr_cmd_bl ,
// Connections to/from fsm module
// signal to increment to the next mcb transaction
input wire next_cmd ,
// signal to the fsm there is another transaction required
output wire next_pending
);
////////////////////////////////////////////////////////////////////////////////
// Local parameters
////////////////////////////////////////////////////////////////////////////////
// AXBURST decodes
localparam P_AXBURST_FIXED = 2'b00;
localparam P_AXBURST_INCR = 2'b01;
localparam P_AXBURST_WRAP = 2'b10;
////////////////////////////////////////////////////////////////////////////////
// Wires/Reg declarations
////////////////////////////////////////////////////////////////////////////////
wire [C_MCB_ADDR_WIDTH-1:0] incr_cmd_byte_addr_i;
wire [5:0] incr_cmd_bl_i;
wire incr_next_pending;
wire [C_MCB_ADDR_WIDTH-1:0] wrap_cmd_byte_addr_i;
wire [5:0] wrap_cmd_bl_i;
wire wrap_next_pending;
reg [1:0] axburst_d1;
reg [5:0] wrap_cmd_bl_d1;
reg [5:0] incr_cmd_bl_d1;
////////////////////////////////////////////////////////////////////////////////
// BEGIN RTL
////////////////////////////////////////////////////////////////////////////////
// INCR and WRAP translations are calcuated in independently, select the one
// for our transactions
always @(posedge clk) begin
axburst_d1 <= axburst;
wrap_cmd_bl_d1 <= wrap_cmd_bl;
incr_cmd_bl_d1 <= incr_cmd_bl;
end
// No support for FIXED. Anything other than a wrap is treated as INCR.
assign wrap_cmd_sel = axburst_d1[1];
assign wrap_cmd_byte_addr = {wrap_cmd_byte_addr_i[C_MCB_ADDR_WIDTH-1:C_AXSIZE], {C_AXSIZE{1'b0}}};
assign wrap_cmd_bl = wrap_cmd_bl_i;
assign incr_cmd_byte_addr = {incr_cmd_byte_addr_i[C_MCB_ADDR_WIDTH-1:C_AXSIZE], {C_AXSIZE{1'b0}}};
assign incr_cmd_bl = incr_cmd_bl_i;
assign next_pending = wrap_cmd_sel ? wrap_next_pending : incr_next_pending;
axi_mcb_incr_cmd #
(
.C_AXI_ADDR_WIDTH (C_AXI_ADDR_WIDTH),
.C_MCB_ADDR_WIDTH (C_MCB_ADDR_WIDTH),
.C_DATA_WIDTH (C_DATA_WIDTH),
.C_CNT_WIDTH (C_CNT_WIDTH),
.C_AXSIZE (C_AXSIZE)
)
axi_mcb_incr_cmd_0
(
.clk ( clk ) ,
.reset ( reset ) ,
.axaddr ( axaddr ) ,
.axlen ( axlen ) ,
.axsize ( axsize ) ,
.axhandshake ( axhandshake ) ,
.cmd_bl ( incr_cmd_bl_i ) ,
.cmd_byte_addr ( incr_cmd_byte_addr_i ) ,
.next_cmd ( next_cmd ) ,
.next_pending ( incr_next_pending )
);
axi_mcb_wrap_cmd #
(
.C_AXI_ADDR_WIDTH ( C_AXI_ADDR_WIDTH ) ,
.C_MCB_ADDR_WIDTH ( C_MCB_ADDR_WIDTH ) ,
.C_DATA_WIDTH ( C_DATA_WIDTH ) ,
.C_PL_CMD_BL_SECOND ( C_PL_CMD_BL_SECOND )
)
axi_mcb_wrap_cmd_0
(
.clk ( clk ) ,
.reset ( reset ) ,
.axaddr ( axaddr ) ,
.axlen ( axlen ) ,
.axsize ( axsize ) ,
.axhandshake ( axhandshake ) ,
.cmd_bl ( wrap_cmd_bl_i ) ,
.cmd_byte_addr ( wrap_cmd_byte_addr_i ) ,
.next_cmd ( next_cmd ) ,
.next_pending ( wrap_next_pending )
);
endmodule
|
module r_upsizer #
(
parameter C_FAMILY = "rtl",
// FPGA Family. Current version: virtex6 or spartan6.
parameter integer C_AXI_ID_WIDTH = 4,
// Width of all ID signals on SI and MI side of converter.
// Range: >= 1.
parameter C_S_AXI_DATA_WIDTH = 32'h00000020,
// Width of S_AXI_WDATA and S_AXI_RDATA.
// Format: Bit32;
// Range: 'h00000020, 'h00000040, 'h00000080, 'h00000100.
parameter C_M_AXI_DATA_WIDTH = 32'h00000040,
// Width of M_AXI_WDATA and M_AXI_RDATA.
// Assume greater than or equal to C_S_AXI_DATA_WIDTH.
// Format: Bit32;
// Range: 'h00000020, 'h00000040, 'h00000080, 'h00000100.
parameter integer C_S_AXI_REGISTER = 0,
// Clock output data.
// Range: 0, 1
parameter integer C_AXI_SUPPORTS_USER_SIGNALS = 0,
// 1 = Propagate all USER signals, 0 = Dont propagate.
parameter integer C_AXI_RUSER_WIDTH = 1,
// Width of RUSER signals.
// Range: >= 1.
parameter integer C_PACKING_LEVEL = 1,
// 0 = Never pack (expander only); packing logic is omitted.
// 1 = Pack only when CACHE[1] (Modifiable) is high.
// 2 = Always pack, regardless of sub-size transaction or Modifiable bit.
// (Required when used as helper-core by mem-con.)
parameter integer C_SUPPORT_BURSTS = 1,
// Disabled when all connected masters and slaves are AxiLite,
// allowing logic to be simplified.
parameter integer C_S_AXI_BYTES_LOG = 3,
// Log2 of number of 32bit word on SI-side.
parameter integer C_M_AXI_BYTES_LOG = 3,
// Log2 of number of 32bit word on MI-side.
parameter integer C_RATIO = 2,
// Up-Sizing ratio for data.
parameter integer C_RATIO_LOG = 1
// Log2 of Up-Sizing ratio for data.
)
(
// Global Signals
input wire ARESET,
input wire ACLK,
// Command Interface
input wire cmd_valid,
input wire cmd_fix,
input wire cmd_modified,
input wire cmd_complete_wrap,
input wire cmd_packed_wrap,
input wire [C_M_AXI_BYTES_LOG-1:0] cmd_first_word,
input wire [C_M_AXI_BYTES_LOG-1:0] cmd_next_word,
input wire [C_M_AXI_BYTES_LOG-1:0] cmd_last_word,
input wire [C_M_AXI_BYTES_LOG-1:0] cmd_offset,
input wire [C_M_AXI_BYTES_LOG-1:0] cmd_mask,
input wire [C_S_AXI_BYTES_LOG:0] cmd_step,
input wire [8-1:0] cmd_length,
output wire cmd_ready,
// Slave Interface Read Data Ports
output wire [C_AXI_ID_WIDTH-1:0] S_AXI_RID,
output wire [C_S_AXI_DATA_WIDTH-1:0] S_AXI_RDATA,
output wire [2-1:0] S_AXI_RRESP,
output wire S_AXI_RLAST,
output wire [C_AXI_RUSER_WIDTH-1:0] S_AXI_RUSER,
output wire S_AXI_RVALID,
input wire S_AXI_RREADY,
// Master Interface Read Data Ports
input wire [C_AXI_ID_WIDTH-1:0] M_AXI_RID,
input wire [C_M_AXI_DATA_WIDTH-1:0] M_AXI_RDATA,
input wire [2-1:0] M_AXI_RRESP,
input wire M_AXI_RLAST,
input wire [C_AXI_RUSER_WIDTH-1:0] M_AXI_RUSER,
input wire M_AXI_RVALID,
output wire M_AXI_RREADY
);
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
/////////////////////////////////////////////////////////////////////////////
genvar bit_cnt;
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
// Constants for packing levels.
localparam integer C_NEVER_PACK = 0;
localparam integer C_DEFAULT_PACK = 1;
localparam integer C_ALWAYS_PACK = 2;
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
// Sub-word handling.
wire sel_first_word;
reg first_word;
reg [C_M_AXI_BYTES_LOG-1:0] current_word_1;
reg [C_M_AXI_BYTES_LOG-1:0] current_word_cmb;
wire [C_M_AXI_BYTES_LOG-1:0] current_word;
wire [C_M_AXI_BYTES_LOG-1:0] current_word_adjusted;
wire last_beat;
wire last_word;
wire [C_M_AXI_BYTES_LOG-1:0] cmd_step_i;
// Sub-word handling for the next cycle.
wire [C_M_AXI_BYTES_LOG-1:0] pre_next_word_i;
wire [C_M_AXI_BYTES_LOG-1:0] pre_next_word;
reg [C_M_AXI_BYTES_LOG-1:0] pre_next_word_1;
wire [C_M_AXI_BYTES_LOG-1:0] next_word_i;
wire [C_M_AXI_BYTES_LOG-1:0] next_word;
// Burst length handling.
wire first_mi_word;
wire [8-1:0] length_counter_1;
reg [8-1:0] length_counter;
wire [8-1:0] next_length_counter;
// Handle wrap buffering.
wire store_in_wrap_buffer;
reg use_wrap_buffer;
reg wrap_buffer_available;
reg [C_AXI_ID_WIDTH-1:0] rid_wrap_buffer;
reg [2-1:0] rresp_wrap_buffer;
reg [C_AXI_RUSER_WIDTH-1:0] ruser_wrap_buffer;
// Throttling help signals.
wire next_word_wrap;
wire word_complete_next_wrap;
wire word_complete_next_wrap_ready;
wire word_complete_next_wrap_pop;
wire word_complete_last_word;
wire word_complete_rest;
wire word_complete_rest_ready;
wire word_complete_rest_pop;
wire word_completed;
wire cmd_ready_i;
wire pop_si_data;
wire pop_mi_data;
wire si_stalling;
// Internal signals for MI-side.
reg [C_M_AXI_DATA_WIDTH-1:0] M_AXI_RDATA_I;
wire M_AXI_RLAST_I;
wire M_AXI_RVALID_I;
wire M_AXI_RREADY_I;
// Internal signals for SI-side.
wire [C_AXI_ID_WIDTH-1:0] S_AXI_RID_I;
wire [C_S_AXI_DATA_WIDTH-1:0] S_AXI_RDATA_I;
wire [2-1:0] S_AXI_RRESP_I;
wire S_AXI_RLAST_I;
wire [C_AXI_RUSER_WIDTH-1:0] S_AXI_RUSER_I;
wire S_AXI_RVALID_I;
wire S_AXI_RREADY_I;
/////////////////////////////////////////////////////////////////////////////
// Handle interface handshaking:
//
// Determine if a MI side word has been completely used. For FIX transactions
// the MI-side word is used to extract a single data word. This is also true
// for for an upsizer in Expander mode (Never Pack). Unmodified burst also
// only use the MI word to extract a single SI-side word (although with
// different offsets).
// Otherwise is the MI-side word considered to be used when last SI-side beat
// has been extracted or when the last (most significant) SI-side word has
// been extracted from ti MI word.
//
// Data on the SI-side is available when data is being taken from MI-side or
// from wrap buffer.
//
// The command is popped from the command queue once the last beat on the
// SI-side has been ackowledged.
//
/////////////////////////////////////////////////////////////////////////////
generate
if ( C_RATIO_LOG > 1 ) begin : USE_LARGE_UPSIZING
assign cmd_step_i = {{C_RATIO_LOG-1{1'b0}}, cmd_step};
end else begin : NO_LARGE_UPSIZING
assign cmd_step_i = cmd_step;
end
endgenerate
generate
if ( C_FAMILY == "rtl" || ( C_SUPPORT_BURSTS == 0 ) ||
( C_PACKING_LEVEL == C_NEVER_PACK ) ) begin : USE_RTL_WORD_COMPLETED
// Detect when MI-side word is completely used.
assign word_completed = cmd_valid &
( ( cmd_fix ) |
( ~cmd_fix & ~cmd_complete_wrap & next_word == {C_M_AXI_BYTES_LOG{1'b0}} ) |
( ~cmd_fix & last_word & ~use_wrap_buffer ) |
( ~cmd_modified & ( C_PACKING_LEVEL == C_DEFAULT_PACK ) ) |
( C_PACKING_LEVEL == C_NEVER_PACK ) |
( C_SUPPORT_BURSTS == 0 ) );
// RTL equivalent of optimized partial extressions (address wrap for next word).
assign word_complete_next_wrap = ( ~cmd_fix & ~cmd_complete_wrap & next_word == {C_M_AXI_BYTES_LOG{1'b0}} ) |
( C_PACKING_LEVEL == C_NEVER_PACK ) |
( C_SUPPORT_BURSTS == 0 );
assign word_complete_next_wrap_ready = word_complete_next_wrap & M_AXI_RVALID_I & ~si_stalling;
assign word_complete_next_wrap_pop = word_complete_next_wrap_ready & M_AXI_RVALID_I;
// RTL equivalent of optimized partial extressions (last word and the remaining).
assign word_complete_last_word = last_word & (~cmd_fix & ~use_wrap_buffer);
assign word_complete_rest = word_complete_last_word | cmd_fix |
( ~cmd_modified & ( C_PACKING_LEVEL == C_DEFAULT_PACK ) );
assign word_complete_rest_ready = word_complete_rest & M_AXI_RVALID_I & ~si_stalling;
assign word_complete_rest_pop = word_complete_rest_ready & M_AXI_RVALID_I;
end else begin : USE_FPGA_WORD_COMPLETED
wire sel_word_complete_next_wrap;
wire sel_word_completed;
wire sel_m_axi_rready;
wire sel_word_complete_last_word;
wire sel_word_complete_rest;
// Optimize next word address wrap branch of expression.
//
comparator_sel_static #
(
.C_FAMILY(C_FAMILY),
.C_VALUE({C_M_AXI_BYTES_LOG{1'b0}}),
.C_DATA_WIDTH(C_M_AXI_BYTES_LOG)
) next_word_wrap_inst
(
.CIN(1'b1),
.S(sel_first_word),
.A(pre_next_word_1),
.B(cmd_next_word),
.COUT(next_word_wrap)
);
assign sel_word_complete_next_wrap = ~cmd_fix & ~cmd_complete_wrap;
carry_and #
(
.C_FAMILY(C_FAMILY)
) word_complete_next_wrap_inst
(
.CIN(next_word_wrap),
.S(sel_word_complete_next_wrap),
.COUT(word_complete_next_wrap)
);
assign sel_m_axi_rready = cmd_valid & S_AXI_RREADY_I;
carry_and #
(
.C_FAMILY(C_FAMILY)
) word_complete_next_wrap_ready_inst
(
.CIN(word_complete_next_wrap),
.S(sel_m_axi_rready),
.COUT(word_complete_next_wrap_ready)
);
carry_and #
(
.C_FAMILY(C_FAMILY)
) word_complete_next_wrap_pop_inst
(
.CIN(word_complete_next_wrap_ready),
.S(M_AXI_RVALID_I),
.COUT(word_complete_next_wrap_pop)
);
// Optimize last word and "rest" branch of expression.
//
assign sel_word_complete_last_word = ~cmd_fix & ~use_wrap_buffer;
carry_and #
(
.C_FAMILY(C_FAMILY)
) word_complete_last_word_inst
(
.CIN(last_word),
.S(sel_word_complete_last_word),
.COUT(word_complete_last_word)
);
assign sel_word_complete_rest = cmd_fix | ( ~cmd_modified & ( C_PACKING_LEVEL == C_DEFAULT_PACK ) );
carry_or #
(
.C_FAMILY(C_FAMILY)
) word_complete_rest_inst
(
.CIN(word_complete_last_word),
.S(sel_word_complete_rest),
.COUT(word_complete_rest)
);
carry_and #
(
.C_FAMILY(C_FAMILY)
) word_complete_rest_ready_inst
(
.CIN(word_complete_rest),
.S(sel_m_axi_rready),
.COUT(word_complete_rest_ready)
);
carry_and #
(
.C_FAMILY(C_FAMILY)
) word_complete_rest_pop_inst
(
.CIN(word_complete_rest_ready),
.S(M_AXI_RVALID_I),
.COUT(word_complete_rest_pop)
);
// Combine the two branches to generate the full signal.
assign word_completed = word_complete_next_wrap | word_complete_rest;
end
endgenerate
// Only propagate Valid when there is command information available.
assign M_AXI_RVALID_I = M_AXI_RVALID & cmd_valid;
generate
if ( C_FAMILY == "rtl" ) begin : USE_RTL_CTRL
// Pop word from MI-side.
assign M_AXI_RREADY_I = word_completed & S_AXI_RREADY_I;
// Get MI-side data.
assign pop_mi_data = M_AXI_RVALID_I & M_AXI_RREADY_I;
// Signal that the command is done (so that it can be poped from command queue).
assign cmd_ready_i = cmd_valid & S_AXI_RLAST_I & pop_si_data;
end else begin : USE_FPGA_CTRL
wire sel_cmd_ready;
assign M_AXI_RREADY_I = word_complete_next_wrap_ready | word_complete_rest_ready;
assign pop_mi_data = word_complete_next_wrap_pop | word_complete_rest_pop;
assign sel_cmd_ready = cmd_valid & pop_si_data;
carry_latch_and #
(
.C_FAMILY(C_FAMILY)
) cmd_ready_inst
(
.CIN(S_AXI_RLAST_I),
.I(sel_cmd_ready),
.O(cmd_ready_i)
);
end
endgenerate
// Indicate when there is data available @ SI-side.
assign S_AXI_RVALID_I = ( M_AXI_RVALID_I | use_wrap_buffer );
// Get SI-side data.
assign pop_si_data = S_AXI_RVALID_I & S_AXI_RREADY_I;
// Assign external signals.
assign M_AXI_RREADY = M_AXI_RREADY_I;
assign cmd_ready = cmd_ready_i;
// Detect when SI-side is stalling.
assign si_stalling = S_AXI_RVALID_I & ~S_AXI_RREADY_I;
/////////////////////////////////////////////////////////////////////////////
// Keep track of data extraction:
//
// Current address is taken form the command buffer for the first data beat
// to handle unaligned Read transactions. After this is the extraction
// address usually calculated from this point.
// FIX transactions uses the same word address for all data beats.
//
// Next word address is generated as current word plus the current step
// size, with masking to facilitate sub-sized wraping. The Mask is all ones
// for normal wraping, and less when sub-sized wraping is used.
//
// The calculated word addresses (current and next) is offseted by the
// current Offset. For sub-sized transaction the Offset points to the least
// significant address of the included data beats. (The least significant
// word is not necessarily the first data to be extracted, consider WRAP).
// Offset is only used for sub-sized WRAP transcation that are Complete.
//
// First word is active during the first SI-side data beat.
//
// First MI is set while the entire first MI-side word is processed.
//
// The transaction length is taken from the command buffer combinatorialy
// during the First MI cycle. For each used MI word it is decreased until
// Last beat is reached.
//
// Last word is determined depending on the current command, i.e. modified
// burst has to scale since multiple words could be packed into one MI-side
// word.
// Last word is 1:1 for:
// FIX, when burst support is disabled or unmodified for Normal Pack.
// Last word is scaled for all other transactions.
//
/////////////////////////////////////////////////////////////////////////////
// Select if the offset comes from command queue directly or
// from a counter while when extracting multiple SI words per MI word
assign sel_first_word = first_word | cmd_fix;
assign current_word = sel_first_word ? cmd_first_word :
current_word_1;
generate
if ( C_FAMILY == "rtl" ) begin : USE_RTL_NEXT_WORD
// Calculate next word.
assign pre_next_word_i = ( next_word_i + cmd_step_i );
// Calculate next word.
assign next_word_i = sel_first_word ? cmd_next_word :
pre_next_word_1;
end else begin : USE_FPGA_NEXT_WORD
wire [C_M_AXI_BYTES_LOG-1:0] next_sel;
wire [C_M_AXI_BYTES_LOG:0] next_carry_local;
// Assign input to local vectors.
assign next_carry_local[0] = 1'b0;
// Instantiate one carry and per level.
for (bit_cnt = 0; bit_cnt < C_M_AXI_BYTES_LOG ; bit_cnt = bit_cnt + 1) begin : LUT_LEVEL
LUT6_2 # (
.INIT(64'h5A5A_5A66_F0F0_F0CC)
) LUT6_2_inst (
.O6(next_sel[bit_cnt]), // 6/5-LUT output (1-bit)
.O5(next_word_i[bit_cnt]), // 5-LUT output (1-bit)
.I0(cmd_step_i[bit_cnt]), // LUT input (1-bit)
.I1(pre_next_word_1[bit_cnt]), // LUT input (1-bit)
.I2(cmd_next_word[bit_cnt]), // LUT input (1-bit)
.I3(first_word), // LUT input (1-bit)
.I4(cmd_fix), // LUT input (1-bit)
.I5(1'b1) // LUT input (1-bit)
);
MUXCY next_carry_inst
(
.O (next_carry_local[bit_cnt+1]),
.CI (next_carry_local[bit_cnt]),
.DI (cmd_step_i[bit_cnt]),
.S (next_sel[bit_cnt])
);
XORCY next_xorcy_inst
(
.O(pre_next_word_i[bit_cnt]),
.CI(next_carry_local[bit_cnt]),
.LI(next_sel[bit_cnt])
);
end // end for bit_cnt
end
endgenerate
// Calculate next word.
assign next_word = next_word_i & cmd_mask;
assign pre_next_word = pre_next_word_i & cmd_mask;
// Calculate the word address with offset.
assign current_word_adjusted = current_word | cmd_offset;
// Prepare next word address.
always @ (posedge ACLK) begin
if (ARESET) begin
first_word <= 1'b1;
current_word_1 <= 'b0;
pre_next_word_1 <= {C_M_AXI_BYTES_LOG{1'b0}};
end else begin
if ( pop_si_data ) begin
if ( last_word ) begin
// Prepare for next access.
first_word <= 1'b1;
end else begin
first_word <= 1'b0;
end
current_word_1 <= next_word;
pre_next_word_1 <= pre_next_word;
end
end
end
// Select command length or counted length.
always @ *
begin
if ( first_mi_word )
length_counter = cmd_length;
else
length_counter = length_counter_1;
end
// Calculate next length counter value.
assign next_length_counter = length_counter - 1'b1;
generate
if ( C_FAMILY == "rtl" ) begin : USE_RTL_LENGTH
reg [8-1:0] length_counter_q;
reg first_mi_word_q;
always @ (posedge ACLK) begin
if (ARESET) begin
first_mi_word_q <= 1'b1;
length_counter_q <= 8'b0;
end else begin
if ( pop_mi_data ) begin
if ( M_AXI_RLAST ) begin
first_mi_word_q <= 1'b1;
end else begin
first_mi_word_q <= 1'b0;
end
length_counter_q <= next_length_counter;
end
end
end
assign first_mi_word = first_mi_word_q;
assign length_counter_1 = length_counter_q;
end else begin : USE_FPGA_LENGTH
wire [8-1:0] length_counter_i;
wire [8-1:0] length_sel;
wire [8-1:0] length_di;
wire [8:0] length_local_carry;
// Assign input to local vectors.
assign length_local_carry[0] = 1'b0;
for (bit_cnt = 0; bit_cnt < 8 ; bit_cnt = bit_cnt + 1) begin : BIT_LANE
LUT6_2 # (
.INIT(64'h333C_555A_FFF0_FFF0)
) LUT6_2_inst (
.O6(length_sel[bit_cnt]), // 6/5-LUT output (1-bit)
.O5(length_di[bit_cnt]), // 5-LUT output (1-bit)
.I0(length_counter_1[bit_cnt]), // LUT input (1-bit)
.I1(cmd_length[bit_cnt]), // LUT input (1-bit)
.I2(word_complete_next_wrap_pop), // LUT input (1-bit)
.I3(word_complete_rest_pop), // LUT input (1-bit)
.I4(first_mi_word), // LUT input (1-bit)
.I5(1'b1) // LUT input (1-bit)
);
MUXCY and_inst
(
.O (length_local_carry[bit_cnt+1]),
.CI (length_local_carry[bit_cnt]),
.DI (length_di[bit_cnt]),
.S (length_sel[bit_cnt])
);
XORCY xorcy_inst
(
.O(length_counter_i[bit_cnt]),
.CI(length_local_carry[bit_cnt]),
.LI(length_sel[bit_cnt])
);
FDRE #(
.INIT(1'b0) // Initial value of register (1'b0 or 1'b1)
) FDRE_inst (
.Q(length_counter_1[bit_cnt]), // Data output
.C(ACLK), // Clock input
.CE(1'b1), // Clock enable input
.R(ARESET), // Synchronous reset input
.D(length_counter_i[bit_cnt]) // Data input
);
end // end for bit_cnt
wire first_mi_word_i;
LUT6 # (
.INIT(64'hAAAC_AAAC_AAAC_AAAC)
) LUT6_cnt_inst (
.O(first_mi_word_i), // 6-LUT output (1-bit)
.I0(M_AXI_RLAST), // LUT input (1-bit)
.I1(first_mi_word), // LUT input (1-bit)
.I2(word_complete_next_wrap_pop), // LUT input (1-bit)
.I3(word_complete_rest_pop), // LUT input (1-bit)
.I4(1'b1), // LUT input (1-bit)
.I5(1'b1) // LUT input (1-bit)
);
FDSE #(
.INIT(1'b1) // Initial value of register (1'b0 or 1'b1)
) FDRE_inst (
.Q(first_mi_word), // Data output
.C(ACLK), // Clock input
.CE(1'b1), // Clock enable input
.S(ARESET), // Synchronous reset input
.D(first_mi_word_i) // Data input
);
end
endgenerate
generate
if ( C_FAMILY == "rtl" || C_SUPPORT_BURSTS == 0 ) begin : USE_RTL_LAST_WORD
// Detect last beat in a burst.
assign last_beat = ( length_counter == 8'b0 );
// Determine if this last word that shall be extracted from this MI-side word.
assign last_word = ( last_beat & ( current_word == cmd_last_word ) & ~wrap_buffer_available & ( current_word == cmd_last_word ) ) |
( use_wrap_buffer & ( current_word == cmd_last_word ) ) |
( last_beat & ( current_word == cmd_last_word ) & ( C_PACKING_LEVEL == C_NEVER_PACK ) ) |
( C_SUPPORT_BURSTS == 0 );
end else begin : USE_FPGA_LAST_WORD
wire sel_last_word;
wire last_beat_ii;
comparator_sel_static #
(
.C_FAMILY(C_FAMILY),
.C_VALUE(8'b0),
.C_DATA_WIDTH(8)
) last_beat_inst
(
.CIN(1'b1),
.S(first_mi_word),
.A(length_counter_1),
.B(cmd_length),
.COUT(last_beat)
);
if ( C_PACKING_LEVEL != C_NEVER_PACK ) begin : USE_FPGA_PACK
//
//
wire sel_last_beat;
wire last_beat_i;
assign sel_last_beat = ~wrap_buffer_available;
carry_and #
(
.C_FAMILY(C_FAMILY)
) last_beat_inst_1
(
.CIN(last_beat),
.S(sel_last_beat),
.COUT(last_beat_i)
);
carry_or #
(
.C_FAMILY(C_FAMILY)
) last_beat_wrap_inst
(
.CIN(last_beat_i),
.S(use_wrap_buffer),
.COUT(last_beat_ii)
);
end else begin : NO_PACK
assign last_beat_ii = last_beat;
end
comparator_sel #
(
.C_FAMILY(C_FAMILY),
.C_DATA_WIDTH(C_M_AXI_BYTES_LOG)
) last_beat_curr_word_inst
(
.CIN(last_beat_ii),
.S(sel_first_word),
.A(current_word_1),
.B(cmd_first_word),
.V(cmd_last_word),
.COUT(last_word)
);
end
endgenerate
/////////////////////////////////////////////////////////////////////////////
// Handle wrap buffer:
//
// The wrap buffer is used to move data around in an unaligned WRAP
// transaction. The requested read address has been rounded down, meaning
// that parts of the first MI-side data beat has to be delayed for later use.
// The extraction starts at the origian unaligned address, the remaining data
// is stored in the wrap buffer to be extracted after the last MI-side data
// beat has been fully processed.
// For example: an 32bit to 64bit read upsizing @ 0x4 will request a MI-side
// read WRAP transaction 0x0. The 0x4 data word is used at once and the 0x0
// word is delayed to be used after all data in the last MI-side beat has
// arrived.
//
/////////////////////////////////////////////////////////////////////////////
// Save data to be able to perform buffer wraping.
assign store_in_wrap_buffer = M_AXI_RVALID_I & cmd_packed_wrap & first_mi_word & ~use_wrap_buffer;
// Mark that there are data available for wrap buffering.
always @ (posedge ACLK) begin
if (ARESET) begin
wrap_buffer_available <= 1'b0;
end else begin
if ( store_in_wrap_buffer & word_completed & pop_si_data ) begin
wrap_buffer_available <= 1'b1;
end else if ( last_beat & word_completed & pop_si_data ) begin
wrap_buffer_available <= 1'b0;
end
end
end
// Start using the wrap buffer.
always @ (posedge ACLK) begin
if (ARESET) begin
use_wrap_buffer <= 1'b0;
end else begin
if ( wrap_buffer_available & last_beat & word_completed & pop_si_data ) begin
use_wrap_buffer <= 1'b1;
end else if ( cmd_ready_i ) begin
use_wrap_buffer <= 1'b0;
end
end
end
// Store data in wrap buffer.
always @ (posedge ACLK) begin
if (ARESET) begin
M_AXI_RDATA_I <= {C_M_AXI_DATA_WIDTH{1'b0}};
rid_wrap_buffer <= {C_AXI_ID_WIDTH{1'b0}};
rresp_wrap_buffer <= 2'b0;
ruser_wrap_buffer <= {C_AXI_ID_WIDTH{1'b0}};
end else begin
if ( store_in_wrap_buffer ) begin
M_AXI_RDATA_I <= M_AXI_RDATA;
rid_wrap_buffer <= M_AXI_RID;
rresp_wrap_buffer <= M_AXI_RRESP;
ruser_wrap_buffer <= M_AXI_RUSER;
end
end
end
/////////////////////////////////////////////////////////////////////////////
// Select the SI-side word to read.
//
// Everything must be multiplexed since the next transfer can be arriving
// with a different set of signals while the wrap buffer is still being
// processed for the current transaction.
//
// Non modifiable word has a 1:1 ratio, i.e. only one SI-side word is
// generated per MI-side word.
// Data is taken either directly from the incomming MI-side data or the
// wrap buffer (for packed WRAP).
//
// Last need special handling since it is the last SI-side word generated
// from the MI-side word.
//
/////////////////////////////////////////////////////////////////////////////
// ID, RESP and USER has to be multiplexed.
assign S_AXI_RID_I = ( use_wrap_buffer & ( C_SUPPORT_BURSTS == 1 ) ) ?
rid_wrap_buffer :
M_AXI_RID;
assign S_AXI_RRESP_I = ( use_wrap_buffer & ( C_SUPPORT_BURSTS == 1 ) ) ?
rresp_wrap_buffer :
M_AXI_RRESP;
assign S_AXI_RUSER_I = ( C_AXI_SUPPORTS_USER_SIGNALS ) ?
( use_wrap_buffer & ( C_SUPPORT_BURSTS == 1 ) ) ?
ruser_wrap_buffer :
M_AXI_RUSER :
{C_AXI_RUSER_WIDTH{1'b0}};
// Data has to be multiplexed.
generate
if ( C_RATIO == 1 ) begin : SINGLE_WORD
assign S_AXI_RDATA_I = ( use_wrap_buffer & ( C_SUPPORT_BURSTS == 1 ) ) ?
M_AXI_RDATA_I :
M_AXI_RDATA;
end else begin : MULTIPLE_WORD
// Get the ratio bits (MI-side words vs SI-side words).
wire [C_RATIO_LOG-1:0] current_index;
assign current_index = current_word_adjusted[C_M_AXI_BYTES_LOG-C_RATIO_LOG +: C_RATIO_LOG];
assign S_AXI_RDATA_I = ( use_wrap_buffer & ( C_SUPPORT_BURSTS == 1 ) ) ?
M_AXI_RDATA_I[current_index * C_S_AXI_DATA_WIDTH +: C_S_AXI_DATA_WIDTH] :
M_AXI_RDATA[current_index * C_S_AXI_DATA_WIDTH +: C_S_AXI_DATA_WIDTH];
end
endgenerate
// Generate the true last flag including "keep" while using wrap buffer.
assign M_AXI_RLAST_I = ( M_AXI_RLAST | use_wrap_buffer );
// Handle last flag, i.e. set for SI-side last word.
assign S_AXI_RLAST_I = last_word;
/////////////////////////////////////////////////////////////////////////////
// SI-side output handling
/////////////////////////////////////////////////////////////////////////////
generate
if ( C_S_AXI_REGISTER ) begin : USE_REGISTER
reg [C_AXI_ID_WIDTH-1:0] S_AXI_RID_q;
reg [C_S_AXI_DATA_WIDTH-1:0] S_AXI_RDATA_q;
reg [2-1:0] S_AXI_RRESP_q;
reg S_AXI_RLAST_q;
reg [C_AXI_RUSER_WIDTH-1:0] S_AXI_RUSER_q;
reg S_AXI_RVALID_q;
reg S_AXI_RREADY_q;
// Register SI-side Data.
always @ (posedge ACLK) begin
if (ARESET) begin
S_AXI_RID_q <= {C_AXI_ID_WIDTH{1'b0}};
S_AXI_RDATA_q <= {C_S_AXI_DATA_WIDTH{1'b0}};
S_AXI_RRESP_q <= 2'b0;
S_AXI_RLAST_q <= 1'b0;
S_AXI_RUSER_q <= {C_AXI_RUSER_WIDTH{1'b0}};
S_AXI_RVALID_q <= 1'b0;
end else begin
if ( S_AXI_RREADY_I ) begin
S_AXI_RID_q <= S_AXI_RID_I;
S_AXI_RDATA_q <= S_AXI_RDATA_I;
S_AXI_RRESP_q <= S_AXI_RRESP_I;
S_AXI_RLAST_q <= S_AXI_RLAST_I;
S_AXI_RUSER_q <= S_AXI_RUSER_I;
S_AXI_RVALID_q <= S_AXI_RVALID_I;
end
end
end
assign S_AXI_RID = S_AXI_RID_q;
assign S_AXI_RDATA = S_AXI_RDATA_q;
assign S_AXI_RRESP = S_AXI_RRESP_q;
assign S_AXI_RLAST = S_AXI_RLAST_q;
assign S_AXI_RUSER = S_AXI_RUSER_q;
assign S_AXI_RVALID = S_AXI_RVALID_q;
assign S_AXI_RREADY_I = ( S_AXI_RVALID_q & S_AXI_RREADY) | ~S_AXI_RVALID_q;
end else begin : NO_REGISTER
// Combinatorial SI-side Data.
assign S_AXI_RREADY_I = S_AXI_RREADY;
assign S_AXI_RVALID = S_AXI_RVALID_I;
assign S_AXI_RID = S_AXI_RID_I;
assign S_AXI_RDATA = S_AXI_RDATA_I;
assign S_AXI_RRESP = S_AXI_RRESP_I;
assign S_AXI_RLAST = S_AXI_RLAST_I;
assign S_AXI_RUSER = S_AXI_RUSER_I;
end
endgenerate
endmodule
|
module axi_upsizer #
(
parameter C_FAMILY = "rtl",
// FPGA Family. Current version: virtex6 or spartan6.
parameter integer C_AXI_ID_WIDTH = 4,
// Width of all ID signals on SI and MI side of converter.
// Range: >= 1.
parameter integer C_AXI_ADDR_WIDTH = 32,
// Width of all ADDR signals on SI and MI side of converter.
// Range: 32.
parameter C_S_AXI_DATA_WIDTH = 32'h00000020,
// Width of S_AXI_WDATA and S_AXI_RDATA.
// Format: Bit32;
// Range: 'h00000020, 'h00000040, 'h00000080, 'h00000100.
parameter C_M_AXI_DATA_WIDTH = 32'h00000040,
// Width of M_AXI_WDATA and M_AXI_RDATA.
// Assume greater than or equal to C_S_AXI_DATA_WIDTH.
// Format: Bit32;
// Range: 'h00000020, 'h00000040, 'h00000080, 'h00000100.
parameter integer C_M_AXI_AW_REGISTER = 0,
// Simple register AW output.
// Range: 0, 1
parameter integer C_M_AXI_W_REGISTER = 1, // Parameter not used; W reg always implemented.
parameter integer C_M_AXI_AR_REGISTER = 0,
// Simple register AR output.
// Range: 0, 1
parameter integer C_S_AXI_R_REGISTER = 0,
// Simple register R output (SI).
// Range: 0, 1
parameter integer C_M_AXI_R_REGISTER = 1,
// Register slice on R input (MI) side.
// 0 = Bypass (not recommended due to combinatorial M_RVALID -> M_RREADY path)
// 1 = Fully-registered (needed only when upsizer propagates bursts at 1:1 width ratio)
// 7 = Light-weight (safe when upsizer always packs at 1:n width ratio, as in interconnect)
parameter integer C_AXI_SUPPORTS_USER_SIGNALS = 0,
// 1 = Propagate all USER signals, 0 = Dont propagate.
parameter integer C_AXI_AWUSER_WIDTH = 1,
// Width of AWUSER signals.
// Range: >= 1.
parameter integer C_AXI_ARUSER_WIDTH = 1,
// Width of ARUSER signals.
// Range: >= 1.
parameter integer C_AXI_WUSER_WIDTH = 1,
// Width of WUSER signals.
// Range: >= 1.
parameter integer C_AXI_RUSER_WIDTH = 1,
// Width of RUSER signals.
// Range: >= 1.
parameter integer C_AXI_BUSER_WIDTH = 1,
// Width of BUSER signals.
// Range: >= 1.
parameter integer C_AXI_SUPPORTS_WRITE = 1,
parameter integer C_AXI_SUPPORTS_READ = 1,
parameter integer C_PACKING_LEVEL = 1,
// 0 = Never pack (expander only); packing logic is omitted.
// 1 = Pack only when CACHE[1] (Modifiable) is high.
// 2 = Always pack, regardless of sub-size transaction or Modifiable bit.
// (Required when used as helper-core by mem-con. Same size AXI interfaces
// should only be used when always packing)
parameter integer C_SUPPORT_BURSTS = 1,
// Disabled when all connected masters and slaves are AxiLite,
// allowing logic to be simplified.
parameter integer C_SINGLE_THREAD = 1
// 0 = Ignore ID when propagating transactions (assume all responses are in order).
// 1 = Allow multiple outstanding transactions only if the IDs are the same
// to prevent response reordering.
// (If ID mismatches, stall until outstanding transaction counter = 0.)
)
(
// Global Signals
input wire ARESETN,
input wire ACLK,
// Slave Interface Write Address Ports
input wire [C_AXI_ID_WIDTH-1:0] S_AXI_AWID,
input wire [C_AXI_ADDR_WIDTH-1:0] S_AXI_AWADDR,
input wire [8-1:0] S_AXI_AWLEN,
input wire [3-1:0] S_AXI_AWSIZE,
input wire [2-1:0] S_AXI_AWBURST,
input wire [2-1:0] S_AXI_AWLOCK,
input wire [4-1:0] S_AXI_AWCACHE,
input wire [3-1:0] S_AXI_AWPROT,
input wire [4-1:0] S_AXI_AWREGION,
input wire [4-1:0] S_AXI_AWQOS,
input wire [C_AXI_AWUSER_WIDTH-1:0] S_AXI_AWUSER,
input wire S_AXI_AWVALID,
output wire S_AXI_AWREADY,
// Slave Interface Write Data Ports
input wire [C_S_AXI_DATA_WIDTH-1:0] S_AXI_WDATA,
input wire [C_S_AXI_DATA_WIDTH/8-1:0] S_AXI_WSTRB,
input wire S_AXI_WLAST,
input wire [C_AXI_WUSER_WIDTH-1:0] S_AXI_WUSER,
input wire S_AXI_WVALID,
output wire S_AXI_WREADY,
// Slave Interface Write Response Ports
output wire [C_AXI_ID_WIDTH-1:0] S_AXI_BID,
output wire [2-1:0] S_AXI_BRESP,
output wire [C_AXI_BUSER_WIDTH-1:0] S_AXI_BUSER,
output wire S_AXI_BVALID,
input wire S_AXI_BREADY,
// Slave Interface Read Address Ports
input wire [C_AXI_ID_WIDTH-1:0] S_AXI_ARID,
input wire [C_AXI_ADDR_WIDTH-1:0] S_AXI_ARADDR,
input wire [8-1:0] S_AXI_ARLEN,
input wire [3-1:0] S_AXI_ARSIZE,
input wire [2-1:0] S_AXI_ARBURST,
input wire [2-1:0] S_AXI_ARLOCK,
input wire [4-1:0] S_AXI_ARCACHE,
input wire [3-1:0] S_AXI_ARPROT,
input wire [4-1:0] S_AXI_ARREGION,
input wire [4-1:0] S_AXI_ARQOS,
input wire [C_AXI_ARUSER_WIDTH-1:0] S_AXI_ARUSER,
input wire S_AXI_ARVALID,
output wire S_AXI_ARREADY,
// Slave Interface Read Data Ports
output wire [C_AXI_ID_WIDTH-1:0] S_AXI_RID,
output wire [C_S_AXI_DATA_WIDTH-1:0] S_AXI_RDATA,
output wire [2-1:0] S_AXI_RRESP,
output wire S_AXI_RLAST,
output wire [C_AXI_RUSER_WIDTH-1:0] S_AXI_RUSER,
output wire S_AXI_RVALID,
input wire S_AXI_RREADY,
// Master Interface Write Address Port
output wire [C_AXI_ID_WIDTH-1:0] M_AXI_AWID,
output wire [C_AXI_ADDR_WIDTH-1:0] M_AXI_AWADDR,
output wire [8-1:0] M_AXI_AWLEN,
output wire [3-1:0] M_AXI_AWSIZE,
output wire [2-1:0] M_AXI_AWBURST,
output wire [2-1:0] M_AXI_AWLOCK,
output wire [4-1:0] M_AXI_AWCACHE,
output wire [3-1:0] M_AXI_AWPROT,
output wire [4-1:0] M_AXI_AWREGION,
output wire [4-1:0] M_AXI_AWQOS,
output wire [C_AXI_AWUSER_WIDTH-1:0] M_AXI_AWUSER,
output wire M_AXI_AWVALID,
input wire M_AXI_AWREADY,
// Master Interface Write Data Ports
output wire [C_M_AXI_DATA_WIDTH-1:0] M_AXI_WDATA,
output wire [C_M_AXI_DATA_WIDTH/8-1:0] M_AXI_WSTRB,
output wire M_AXI_WLAST,
output wire [C_AXI_WUSER_WIDTH-1:0] M_AXI_WUSER,
output wire M_AXI_WVALID,
input wire M_AXI_WREADY,
// Master Interface Write Response Ports
input wire [C_AXI_ID_WIDTH-1:0] M_AXI_BID,
input wire [2-1:0] M_AXI_BRESP,
input wire [C_AXI_BUSER_WIDTH-1:0] M_AXI_BUSER,
input wire M_AXI_BVALID,
output wire M_AXI_BREADY,
// Master Interface Read Address Port
output wire [C_AXI_ID_WIDTH-1:0] M_AXI_ARID,
output wire [C_AXI_ADDR_WIDTH-1:0] M_AXI_ARADDR,
output wire [8-1:0] M_AXI_ARLEN,
output wire [3-1:0] M_AXI_ARSIZE,
output wire [2-1:0] M_AXI_ARBURST,
output wire [2-1:0] M_AXI_ARLOCK,
output wire [4-1:0] M_AXI_ARCACHE,
output wire [3-1:0] M_AXI_ARPROT,
output wire [4-1:0] M_AXI_ARREGION,
output wire [4-1:0] M_AXI_ARQOS,
output wire [C_AXI_ARUSER_WIDTH-1:0] M_AXI_ARUSER,
output wire M_AXI_ARVALID,
input wire M_AXI_ARREADY,
// Master Interface Read Data Ports
input wire [C_AXI_ID_WIDTH-1:0] M_AXI_RID,
input wire [C_M_AXI_DATA_WIDTH-1:0] M_AXI_RDATA,
input wire [2-1:0] M_AXI_RRESP,
input wire M_AXI_RLAST,
input wire [C_AXI_RUSER_WIDTH-1:0] M_AXI_RUSER,
input wire M_AXI_RVALID,
output wire M_AXI_RREADY
);
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
// Log2.
function integer log2;
input integer value;
begin
for (log2=0; value>1; log2=log2+1) begin
value = value >> 1;
end
end
endfunction
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
// Log2 of number of 32bit word on SI-side.
localparam integer C_S_AXI_BYTES_LOG = log2(C_S_AXI_DATA_WIDTH/8);
// Log2 of number of 32bit word on MI-side.
localparam integer C_M_AXI_BYTES_LOG = log2(C_M_AXI_DATA_WIDTH/8);
// Log2 of Up-Sizing ratio for data.
localparam integer C_RATIO = C_M_AXI_DATA_WIDTH / C_S_AXI_DATA_WIDTH;
localparam integer C_RATIO_LOG = log2(C_RATIO);
localparam P_BYPASS = 32'h0;
localparam P_LIGHTWT = 32'h7;
localparam P_FWD_REV = 32'h1;
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
wire [C_AXI_ID_WIDTH-1:0] sr_AWID ;
wire [C_AXI_ADDR_WIDTH-1:0] sr_AWADDR ;
wire [8-1:0] sr_AWLEN ;
wire [3-1:0] sr_AWSIZE ;
wire [2-1:0] sr_AWBURST ;
wire [2-1:0] sr_AWLOCK ;
wire [4-1:0] sr_AWCACHE ;
wire [3-1:0] sr_AWPROT ;
wire [4-1:0] sr_AWREGION ;
wire [4-1:0] sr_AWQOS ;
wire [C_AXI_AWUSER_WIDTH-1:0] sr_AWUSER ;
wire sr_AWVALID ;
wire sr_AWREADY ;
wire [C_AXI_ID_WIDTH-1:0] sr_ARID ;
wire [C_AXI_ADDR_WIDTH-1:0] sr_ARADDR ;
wire [8-1:0] sr_ARLEN ;
wire [3-1:0] sr_ARSIZE ;
wire [2-1:0] sr_ARBURST ;
wire [2-1:0] sr_ARLOCK ;
wire [4-1:0] sr_ARCACHE ;
wire [3-1:0] sr_ARPROT ;
wire [4-1:0] sr_ARREGION ;
wire [4-1:0] sr_ARQOS ;
wire [C_AXI_ARUSER_WIDTH-1:0] sr_ARUSER ;
wire sr_ARVALID ;
wire sr_ARREADY ;
wire [C_S_AXI_DATA_WIDTH-1:0] sr_WDATA ;
wire [(C_S_AXI_DATA_WIDTH/8)-1:0] sr_WSTRB ;
wire sr_WLAST ;
wire sr_WVALID ;
wire sr_WREADY ;
wire [C_AXI_ID_WIDTH-1:0] mr_RID ;
wire [C_M_AXI_DATA_WIDTH-1:0] mr_RDATA ;
wire [2-1:0] mr_RRESP ;
wire mr_RLAST ;
wire [C_AXI_RUSER_WIDTH-1:0] mr_RUSER ;
wire mr_RVALID ;
wire mr_RREADY ;
(* equivalent_register_removal = "no" *) reg ARESET ;
assign M_AXI_WUSER = {C_AXI_WUSER_WIDTH{1'b0}};
assign S_AXI_RUSER = {C_AXI_RUSER_WIDTH{1'b0}};
axi_register_slice #
(
.C_FAMILY (C_FAMILY),
.C_AXI_ID_WIDTH (C_AXI_ID_WIDTH),
.C_AXI_ADDR_WIDTH (C_AXI_ADDR_WIDTH),
.C_AXI_DATA_WIDTH (C_S_AXI_DATA_WIDTH),
.C_AXI_SUPPORTS_USER_SIGNALS (C_AXI_SUPPORTS_USER_SIGNALS),
.C_AXI_AWUSER_WIDTH (C_AXI_AWUSER_WIDTH),
.C_AXI_ARUSER_WIDTH (C_AXI_ARUSER_WIDTH),
.C_REG_CONFIG_AW (C_AXI_SUPPORTS_WRITE ? P_LIGHTWT : P_BYPASS),
.C_REG_CONFIG_AR (C_AXI_SUPPORTS_READ ? P_LIGHTWT : P_BYPASS)
)
si_register_slice_inst
(
.ARESETN (ARESETN),
.ACLK (ACLK),
.S_AXI_AWID (S_AXI_AWID ),
.S_AXI_AWADDR (S_AXI_AWADDR ),
.S_AXI_AWLEN (S_AXI_AWLEN ),
.S_AXI_AWSIZE (S_AXI_AWSIZE ),
.S_AXI_AWBURST (S_AXI_AWBURST ),
.S_AXI_AWLOCK (S_AXI_AWLOCK ),
.S_AXI_AWCACHE (S_AXI_AWCACHE ),
.S_AXI_AWPROT (S_AXI_AWPROT ),
.S_AXI_AWREGION (S_AXI_AWREGION ),
.S_AXI_AWQOS (S_AXI_AWQOS ),
.S_AXI_AWUSER (S_AXI_AWUSER ),
.S_AXI_AWVALID (S_AXI_AWVALID ),
.S_AXI_AWREADY (S_AXI_AWREADY ),
.S_AXI_WID ( {C_AXI_ID_WIDTH{1'b0}}),
.S_AXI_WDATA ( {C_S_AXI_DATA_WIDTH{1'b0}} ),
.S_AXI_WSTRB ( {C_S_AXI_DATA_WIDTH/8{1'b0}} ),
.S_AXI_WLAST ( 1'b0 ),
.S_AXI_WUSER ( 1'b0 ),
.S_AXI_WVALID ( 1'b0 ),
.S_AXI_WREADY ( ),
.S_AXI_BID ( ),
.S_AXI_BRESP ( ),
.S_AXI_BUSER ( ),
.S_AXI_BVALID ( ),
.S_AXI_BREADY ( 1'b0 ),
.S_AXI_ARID (S_AXI_ARID ),
.S_AXI_ARADDR (S_AXI_ARADDR ),
.S_AXI_ARLEN (S_AXI_ARLEN ),
.S_AXI_ARSIZE (S_AXI_ARSIZE ),
.S_AXI_ARBURST (S_AXI_ARBURST ),
.S_AXI_ARLOCK (S_AXI_ARLOCK ),
.S_AXI_ARCACHE (S_AXI_ARCACHE ),
.S_AXI_ARPROT (S_AXI_ARPROT ),
.S_AXI_ARREGION (S_AXI_ARREGION ),
.S_AXI_ARQOS (S_AXI_ARQOS ),
.S_AXI_ARUSER (S_AXI_ARUSER ),
.S_AXI_ARVALID (S_AXI_ARVALID ),
.S_AXI_ARREADY (S_AXI_ARREADY ),
.S_AXI_RID ( ) ,
.S_AXI_RDATA ( ) ,
.S_AXI_RRESP ( ) ,
.S_AXI_RLAST ( ) ,
.S_AXI_RUSER ( ) ,
.S_AXI_RVALID ( ) ,
.S_AXI_RREADY ( 1'b0 ) ,
.M_AXI_AWID (sr_AWID ),
.M_AXI_AWADDR (sr_AWADDR ),
.M_AXI_AWLEN (sr_AWLEN ),
.M_AXI_AWSIZE (sr_AWSIZE ),
.M_AXI_AWBURST (sr_AWBURST ),
.M_AXI_AWLOCK (sr_AWLOCK ),
.M_AXI_AWCACHE (sr_AWCACHE ),
.M_AXI_AWPROT (sr_AWPROT ),
.M_AXI_AWREGION (sr_AWREGION ),
.M_AXI_AWQOS (sr_AWQOS ),
.M_AXI_AWUSER (sr_AWUSER ),
.M_AXI_AWVALID (sr_AWVALID ),
.M_AXI_AWREADY (sr_AWREADY ),
.M_AXI_WID () ,
.M_AXI_WDATA (),
.M_AXI_WSTRB (),
.M_AXI_WLAST (),
.M_AXI_WUSER (),
.M_AXI_WVALID (),
.M_AXI_WREADY (1'b0),
.M_AXI_BID ( {C_AXI_ID_WIDTH{1'b0}} ) ,
.M_AXI_BRESP ( 2'b0 ) ,
.M_AXI_BUSER ( 1'b0 ) ,
.M_AXI_BVALID ( 1'b0 ) ,
.M_AXI_BREADY ( ) ,
.M_AXI_ARID (sr_ARID ),
.M_AXI_ARADDR (sr_ARADDR ),
.M_AXI_ARLEN (sr_ARLEN ),
.M_AXI_ARSIZE (sr_ARSIZE ),
.M_AXI_ARBURST (sr_ARBURST ),
.M_AXI_ARLOCK (sr_ARLOCK ),
.M_AXI_ARCACHE (sr_ARCACHE ),
.M_AXI_ARPROT (sr_ARPROT ),
.M_AXI_ARREGION (sr_ARREGION ),
.M_AXI_ARQOS (sr_ARQOS ),
.M_AXI_ARUSER (sr_ARUSER ),
.M_AXI_ARVALID (sr_ARVALID ),
.M_AXI_ARREADY (sr_ARREADY ),
.M_AXI_RID ( {C_AXI_ID_WIDTH{1'b0}}),
.M_AXI_RDATA ( {C_S_AXI_DATA_WIDTH{1'b0}} ),
.M_AXI_RRESP ( 2'b00 ),
.M_AXI_RLAST ( 1'b0 ),
.M_AXI_RUSER ( 1'b0 ),
.M_AXI_RVALID ( 1'b0 ),
.M_AXI_RREADY ( )
);
axi_register_slice #
(
.C_FAMILY (C_FAMILY),
.C_AXI_ID_WIDTH (C_AXI_ID_WIDTH),
.C_AXI_ADDR_WIDTH (C_AXI_ADDR_WIDTH),
.C_AXI_DATA_WIDTH (C_M_AXI_DATA_WIDTH),
.C_AXI_SUPPORTS_USER_SIGNALS (C_AXI_SUPPORTS_USER_SIGNALS),
.C_AXI_RUSER_WIDTH (C_AXI_RUSER_WIDTH),
.C_REG_CONFIG_R (C_AXI_SUPPORTS_READ ? C_M_AXI_R_REGISTER : P_BYPASS)
)
mi_register_slice_inst
(
.ARESETN (ARESETN),
.ACLK (ACLK),
.S_AXI_AWID ({C_AXI_ID_WIDTH{1'b0}} ),
.S_AXI_AWADDR ( {C_AXI_ADDR_WIDTH{1'b0}} ),
.S_AXI_AWLEN ( 8'b0 ),
.S_AXI_AWSIZE ( 3'b0 ),
.S_AXI_AWBURST ( 2'b0 ),
.S_AXI_AWLOCK ( 2'b0 ),
.S_AXI_AWCACHE ( 4'b0 ),
.S_AXI_AWPROT ( 3'b0 ),
.S_AXI_AWREGION ( 4'b0 ),
.S_AXI_AWQOS ( 4'b0 ),
.S_AXI_AWUSER ( 1'b0 ),
.S_AXI_AWVALID ( 1'b0 ),
.S_AXI_AWREADY ( ),
.S_AXI_WID ( {C_AXI_ID_WIDTH{1'b0}}),
.S_AXI_WDATA ( {C_M_AXI_DATA_WIDTH{1'b0}} ),
.S_AXI_WSTRB ( {C_M_AXI_DATA_WIDTH/8{1'b0}} ),
.S_AXI_WLAST ( 1'b0 ),
.S_AXI_WUSER ( 1'b0 ),
.S_AXI_WVALID ( 1'b0 ),
.S_AXI_WREADY ( ),
.S_AXI_BID ( ),
.S_AXI_BRESP ( ),
.S_AXI_BUSER ( ),
.S_AXI_BVALID ( ),
.S_AXI_BREADY ( 1'b0 ),
.S_AXI_ARID ({C_AXI_ID_WIDTH{1'b0}} ),
.S_AXI_ARADDR ( {C_AXI_ADDR_WIDTH{1'b0}} ),
.S_AXI_ARLEN ( 8'b0 ),
.S_AXI_ARSIZE ( 3'b0 ),
.S_AXI_ARBURST ( 2'b0 ),
.S_AXI_ARLOCK ( 2'b0 ),
.S_AXI_ARCACHE ( 4'b0 ),
.S_AXI_ARPROT ( 3'b0 ),
.S_AXI_ARREGION ( 4'b0 ),
.S_AXI_ARQOS ( 4'b0 ),
.S_AXI_ARUSER ( 1'b0 ),
.S_AXI_ARVALID ( 1'b0 ),
.S_AXI_ARREADY ( ),
.S_AXI_RID (mr_RID ),
.S_AXI_RDATA (mr_RDATA ),
.S_AXI_RRESP (mr_RRESP ),
.S_AXI_RLAST (mr_RLAST ),
.S_AXI_RUSER (mr_RUSER ),
.S_AXI_RVALID (mr_RVALID ),
.S_AXI_RREADY (mr_RREADY ),
.M_AXI_AWID (),
.M_AXI_AWADDR (),
.M_AXI_AWLEN (),
.M_AXI_AWSIZE (),
.M_AXI_AWBURST (),
.M_AXI_AWLOCK (),
.M_AXI_AWCACHE (),
.M_AXI_AWPROT (),
.M_AXI_AWREGION (),
.M_AXI_AWQOS (),
.M_AXI_AWUSER (),
.M_AXI_AWVALID (),
.M_AXI_AWREADY (1'b0),
.M_AXI_WID () ,
.M_AXI_WDATA (),
.M_AXI_WSTRB (),
.M_AXI_WLAST (),
.M_AXI_WUSER (),
.M_AXI_WVALID (),
.M_AXI_WREADY (1'b0),
.M_AXI_BID ( {C_AXI_ID_WIDTH{1'b0}} ) ,
.M_AXI_BRESP ( 2'b0 ) ,
.M_AXI_BUSER ( 1'b0 ) ,
.M_AXI_BVALID ( 1'b0 ) ,
.M_AXI_BREADY ( ) ,
.M_AXI_ARID (),
.M_AXI_ARADDR (),
.M_AXI_ARLEN (),
.M_AXI_ARSIZE (),
.M_AXI_ARBURST (),
.M_AXI_ARLOCK (),
.M_AXI_ARCACHE (),
.M_AXI_ARPROT (),
.M_AXI_ARREGION (),
.M_AXI_ARQOS (),
.M_AXI_ARUSER (),
.M_AXI_ARVALID (),
.M_AXI_ARREADY (1'b0),
.M_AXI_RID (M_AXI_RID ),
.M_AXI_RDATA (M_AXI_RDATA ),
.M_AXI_RRESP (M_AXI_RRESP ),
.M_AXI_RLAST (M_AXI_RLAST ),
.M_AXI_RUSER (M_AXI_RUSER ),
.M_AXI_RVALID (M_AXI_RVALID ),
.M_AXI_RREADY (M_AXI_RREADY )
);
/////////////////////////////////////////////////////////////////////////////
// Handle Internal Reset
/////////////////////////////////////////////////////////////////////////////
always @ (posedge ACLK) begin
ARESET <= !ARESETN;
end
/////////////////////////////////////////////////////////////////////////////
// Handle Write Channels (AW/W/B)
/////////////////////////////////////////////////////////////////////////////
generate
if (C_AXI_SUPPORTS_WRITE == 1) begin : USE_WRITE
// Write Channel Signals for Commands Queue Interface.
wire wr_cmd_valid;
wire wr_cmd_fix;
wire wr_cmd_modified;
wire wr_cmd_complete_wrap;
wire wr_cmd_packed_wrap;
wire [C_M_AXI_BYTES_LOG-1:0] wr_cmd_first_word;
wire [C_M_AXI_BYTES_LOG-1:0] wr_cmd_next_word;
wire [C_M_AXI_BYTES_LOG-1:0] wr_cmd_last_word;
wire [C_M_AXI_BYTES_LOG-1:0] wr_cmd_offset;
wire [C_M_AXI_BYTES_LOG-1:0] wr_cmd_mask;
wire [C_S_AXI_BYTES_LOG:0] wr_cmd_step;
wire [8-1:0] wr_cmd_length;
wire wr_cmd_ready;
// Write Address Channel.
a_upsizer #
(
.C_FAMILY (C_FAMILY),
.C_AXI_ID_WIDTH (C_AXI_ID_WIDTH),
.C_AXI_ADDR_WIDTH (C_AXI_ADDR_WIDTH),
.C_S_AXI_DATA_WIDTH (C_S_AXI_DATA_WIDTH),
.C_M_AXI_DATA_WIDTH (C_M_AXI_DATA_WIDTH),
.C_M_AXI_REGISTER (C_M_AXI_AW_REGISTER),
.C_AXI_SUPPORTS_USER_SIGNALS (C_AXI_SUPPORTS_USER_SIGNALS),
.C_AXI_AUSER_WIDTH (C_AXI_AWUSER_WIDTH),
.C_AXI_CHANNEL (0),
.C_PACKING_LEVEL (C_PACKING_LEVEL),
.C_SUPPORT_BURSTS (C_SUPPORT_BURSTS),
.C_SINGLE_THREAD (C_SINGLE_THREAD),
.C_S_AXI_BYTES_LOG (C_S_AXI_BYTES_LOG),
.C_M_AXI_BYTES_LOG (C_M_AXI_BYTES_LOG)
) write_addr_inst
(
// Global Signals
.ARESET (ARESET),
.ACLK (ACLK),
// Command Interface
.cmd_valid (wr_cmd_valid),
.cmd_fix (wr_cmd_fix),
.cmd_modified (wr_cmd_modified),
.cmd_complete_wrap (wr_cmd_complete_wrap),
.cmd_packed_wrap (wr_cmd_packed_wrap),
.cmd_first_word (wr_cmd_first_word),
.cmd_next_word (wr_cmd_next_word),
.cmd_last_word (wr_cmd_last_word),
.cmd_offset (wr_cmd_offset),
.cmd_mask (wr_cmd_mask),
.cmd_step (wr_cmd_step),
.cmd_length (wr_cmd_length),
.cmd_ready (wr_cmd_ready),
// Slave Interface Write Address Ports
.S_AXI_AID (sr_AWID),
.S_AXI_AADDR (sr_AWADDR),
.S_AXI_ALEN (sr_AWLEN),
.S_AXI_ASIZE (sr_AWSIZE),
.S_AXI_ABURST (sr_AWBURST),
.S_AXI_ALOCK (sr_AWLOCK),
.S_AXI_ACACHE (sr_AWCACHE),
.S_AXI_APROT (sr_AWPROT),
.S_AXI_AREGION (sr_AWREGION),
.S_AXI_AQOS (sr_AWQOS),
.S_AXI_AUSER (sr_AWUSER),
.S_AXI_AVALID (sr_AWVALID),
.S_AXI_AREADY (sr_AWREADY),
// Master Interface Write Address Port
.M_AXI_AID (M_AXI_AWID),
.M_AXI_AADDR (M_AXI_AWADDR),
.M_AXI_ALEN (M_AXI_AWLEN),
.M_AXI_ASIZE (M_AXI_AWSIZE),
.M_AXI_ABURST (M_AXI_AWBURST),
.M_AXI_ALOCK (M_AXI_AWLOCK),
.M_AXI_ACACHE (M_AXI_AWCACHE),
.M_AXI_APROT (M_AXI_AWPROT),
.M_AXI_AREGION (M_AXI_AWREGION),
.M_AXI_AQOS (M_AXI_AWQOS),
.M_AXI_AUSER (M_AXI_AWUSER),
.M_AXI_AVALID (M_AXI_AWVALID),
.M_AXI_AREADY (M_AXI_AWREADY)
);
// Write Data channel.
w_upsizer #
(
.C_FAMILY (C_FAMILY),
.C_S_AXI_DATA_WIDTH (C_S_AXI_DATA_WIDTH),
.C_M_AXI_DATA_WIDTH (C_M_AXI_DATA_WIDTH),
.C_M_AXI_REGISTER (1),
.C_AXI_SUPPORTS_USER_SIGNALS (C_AXI_SUPPORTS_USER_SIGNALS),
.C_AXI_WUSER_WIDTH (C_AXI_WUSER_WIDTH),
.C_PACKING_LEVEL (C_PACKING_LEVEL),
.C_SUPPORT_BURSTS (C_SUPPORT_BURSTS),
.C_S_AXI_BYTES_LOG (C_S_AXI_BYTES_LOG),
.C_M_AXI_BYTES_LOG (C_M_AXI_BYTES_LOG),
.C_RATIO (C_RATIO),
.C_RATIO_LOG (C_RATIO_LOG)
) write_data_inst
(
// Global Signals
.ARESET (ARESET),
.ACLK (ACLK),
// Command Interface
.cmd_valid (wr_cmd_valid),
.cmd_fix (wr_cmd_fix),
.cmd_modified (wr_cmd_modified),
.cmd_complete_wrap (wr_cmd_complete_wrap),
.cmd_packed_wrap (wr_cmd_packed_wrap),
.cmd_first_word (wr_cmd_first_word),
.cmd_next_word (wr_cmd_next_word),
.cmd_last_word (wr_cmd_last_word),
.cmd_offset (wr_cmd_offset),
.cmd_mask (wr_cmd_mask),
.cmd_step (wr_cmd_step),
.cmd_length (wr_cmd_length),
.cmd_ready (wr_cmd_ready),
// Slave Interface Write Data Ports
.S_AXI_WDATA (S_AXI_WDATA),
.S_AXI_WSTRB (S_AXI_WSTRB),
.S_AXI_WLAST (S_AXI_WLAST),
.S_AXI_WUSER (S_AXI_WUSER),
.S_AXI_WVALID (S_AXI_WVALID),
.S_AXI_WREADY (S_AXI_WREADY),
// Master Interface Write Data Ports
.M_AXI_WDATA (M_AXI_WDATA),
.M_AXI_WSTRB (M_AXI_WSTRB),
.M_AXI_WLAST (M_AXI_WLAST),
.M_AXI_WUSER (),
.M_AXI_WVALID (M_AXI_WVALID),
.M_AXI_WREADY (M_AXI_WREADY)
);
// Write Response channel.
assign S_AXI_BID = M_AXI_BID;
assign S_AXI_BRESP = M_AXI_BRESP;
assign S_AXI_BUSER = M_AXI_BUSER;
assign S_AXI_BVALID = M_AXI_BVALID;
assign M_AXI_BREADY = S_AXI_BREADY;
end else begin : NO_WRITE
assign sr_AWREADY = 1'b0;
assign S_AXI_WREADY = 1'b0;
assign S_AXI_BID = {C_AXI_ID_WIDTH{1'b0}};
assign S_AXI_BRESP = 2'b0;
assign S_AXI_BUSER = {C_AXI_BUSER_WIDTH{1'b0}};
assign S_AXI_BVALID = 1'b0;
assign M_AXI_AWID = {C_AXI_ID_WIDTH{1'b0}};
assign M_AXI_AWADDR = {C_AXI_ADDR_WIDTH{1'b0}};
assign M_AXI_AWLEN = 8'b0;
assign M_AXI_AWSIZE = 3'b0;
assign M_AXI_AWBURST = 2'b0;
assign M_AXI_AWLOCK = 2'b0;
assign M_AXI_AWCACHE = 4'b0;
assign M_AXI_AWPROT = 3'b0;
assign M_AXI_AWQOS = 4'b0;
assign M_AXI_AWUSER = {C_AXI_AWUSER_WIDTH{1'b0}};
assign M_AXI_AWVALID = 1'b0;
assign M_AXI_WDATA = {C_M_AXI_DATA_WIDTH{1'b0}};
assign M_AXI_WSTRB = {C_M_AXI_DATA_WIDTH/8{1'b0}};
assign M_AXI_WLAST = 1'b0;
assign M_AXI_WVALID = 1'b0;
assign M_AXI_BREADY = 1'b0;
end
endgenerate
/////////////////////////////////////////////////////////////////////////////
// Handle Read Channels (AR/R)
/////////////////////////////////////////////////////////////////////////////
generate
if (C_AXI_SUPPORTS_READ == 1) begin : USE_READ
// Read Channel Signals for Commands Queue Interface.
wire rd_cmd_valid;
wire rd_cmd_fix;
wire rd_cmd_modified;
wire rd_cmd_complete_wrap;
wire rd_cmd_packed_wrap;
wire [C_M_AXI_BYTES_LOG-1:0] rd_cmd_first_word;
wire [C_M_AXI_BYTES_LOG-1:0] rd_cmd_next_word;
wire [C_M_AXI_BYTES_LOG-1:0] rd_cmd_last_word;
wire [C_M_AXI_BYTES_LOG-1:0] rd_cmd_offset;
wire [C_M_AXI_BYTES_LOG-1:0] rd_cmd_mask;
wire [C_S_AXI_BYTES_LOG:0] rd_cmd_step;
wire [8-1:0] rd_cmd_length;
wire rd_cmd_ready;
// Write Address Channel.
a_upsizer #
(
.C_FAMILY (C_FAMILY),
.C_AXI_ID_WIDTH (C_AXI_ID_WIDTH),
.C_AXI_ADDR_WIDTH (C_AXI_ADDR_WIDTH),
.C_S_AXI_DATA_WIDTH (C_S_AXI_DATA_WIDTH),
.C_M_AXI_DATA_WIDTH (C_M_AXI_DATA_WIDTH),
.C_M_AXI_REGISTER (C_M_AXI_AR_REGISTER),
.C_AXI_SUPPORTS_USER_SIGNALS (C_AXI_SUPPORTS_USER_SIGNALS),
.C_AXI_AUSER_WIDTH (C_AXI_ARUSER_WIDTH),
.C_AXI_CHANNEL (1),
.C_PACKING_LEVEL (C_PACKING_LEVEL),
.C_SUPPORT_BURSTS (C_SUPPORT_BURSTS),
.C_SINGLE_THREAD (C_SINGLE_THREAD),
.C_S_AXI_BYTES_LOG (C_S_AXI_BYTES_LOG),
.C_M_AXI_BYTES_LOG (C_M_AXI_BYTES_LOG)
) read_addr_inst
(
// Global Signals
.ARESET (ARESET),
.ACLK (ACLK),
// Command Interface
.cmd_valid (rd_cmd_valid),
.cmd_fix (rd_cmd_fix),
.cmd_modified (rd_cmd_modified),
.cmd_complete_wrap (rd_cmd_complete_wrap),
.cmd_packed_wrap (rd_cmd_packed_wrap),
.cmd_first_word (rd_cmd_first_word),
.cmd_next_word (rd_cmd_next_word),
.cmd_last_word (rd_cmd_last_word),
.cmd_offset (rd_cmd_offset),
.cmd_mask (rd_cmd_mask),
.cmd_step (rd_cmd_step),
.cmd_length (rd_cmd_length),
.cmd_ready (rd_cmd_ready),
// Slave Interface Write Address Ports
.S_AXI_AID (sr_ARID),
.S_AXI_AADDR (sr_ARADDR),
.S_AXI_ALEN (sr_ARLEN),
.S_AXI_ASIZE (sr_ARSIZE),
.S_AXI_ABURST (sr_ARBURST),
.S_AXI_ALOCK (sr_ARLOCK),
.S_AXI_ACACHE (sr_ARCACHE),
.S_AXI_APROT (sr_ARPROT),
.S_AXI_AREGION (sr_ARREGION),
.S_AXI_AQOS (sr_ARQOS),
.S_AXI_AUSER (sr_ARUSER),
.S_AXI_AVALID (sr_ARVALID),
.S_AXI_AREADY (sr_ARREADY),
// Master Interface Write Address Port
.M_AXI_AID (M_AXI_ARID),
.M_AXI_AADDR (M_AXI_ARADDR),
.M_AXI_ALEN (M_AXI_ARLEN),
.M_AXI_ASIZE (M_AXI_ARSIZE),
.M_AXI_ABURST (M_AXI_ARBURST),
.M_AXI_ALOCK (M_AXI_ARLOCK),
.M_AXI_ACACHE (M_AXI_ARCACHE),
.M_AXI_APROT (M_AXI_ARPROT),
.M_AXI_AREGION (M_AXI_ARREGION),
.M_AXI_AQOS (M_AXI_ARQOS),
.M_AXI_AUSER (M_AXI_ARUSER),
.M_AXI_AVALID (M_AXI_ARVALID),
.M_AXI_AREADY (M_AXI_ARREADY)
);
// Read Data channel.
r_upsizer #
(
.C_FAMILY (C_FAMILY),
.C_AXI_ID_WIDTH (C_AXI_ID_WIDTH),
.C_S_AXI_DATA_WIDTH (C_S_AXI_DATA_WIDTH),
.C_M_AXI_DATA_WIDTH (C_M_AXI_DATA_WIDTH),
.C_S_AXI_REGISTER (C_S_AXI_R_REGISTER),
.C_AXI_SUPPORTS_USER_SIGNALS (C_AXI_SUPPORTS_USER_SIGNALS),
.C_AXI_RUSER_WIDTH (C_AXI_RUSER_WIDTH),
.C_PACKING_LEVEL (C_PACKING_LEVEL),
.C_SUPPORT_BURSTS (C_SUPPORT_BURSTS),
.C_S_AXI_BYTES_LOG (C_S_AXI_BYTES_LOG),
.C_M_AXI_BYTES_LOG (C_M_AXI_BYTES_LOG),
.C_RATIO (C_RATIO),
.C_RATIO_LOG (C_RATIO_LOG)
) read_data_inst
(
// Global Signals
.ARESET (ARESET),
.ACLK (ACLK),
// Command Interface
.cmd_valid (rd_cmd_valid),
.cmd_fix (rd_cmd_fix),
.cmd_modified (rd_cmd_modified),
.cmd_complete_wrap (rd_cmd_complete_wrap),
.cmd_packed_wrap (rd_cmd_packed_wrap),
.cmd_first_word (rd_cmd_first_word),
.cmd_next_word (rd_cmd_next_word),
.cmd_last_word (rd_cmd_last_word),
.cmd_offset (rd_cmd_offset),
.cmd_mask (rd_cmd_mask),
.cmd_step (rd_cmd_step),
.cmd_length (rd_cmd_length),
.cmd_ready (rd_cmd_ready),
// Slave Interface Read Data Ports
.S_AXI_RID (S_AXI_RID),
.S_AXI_RDATA (S_AXI_RDATA),
.S_AXI_RRESP (S_AXI_RRESP),
.S_AXI_RLAST (S_AXI_RLAST),
.S_AXI_RUSER (),
.S_AXI_RVALID (S_AXI_RVALID),
.S_AXI_RREADY (S_AXI_RREADY),
// Master Interface Read Data Ports
.M_AXI_RID (mr_RID),
.M_AXI_RDATA (mr_RDATA),
.M_AXI_RRESP (mr_RRESP),
.M_AXI_RLAST (mr_RLAST),
.M_AXI_RUSER (mr_RUSER),
.M_AXI_RVALID (mr_RVALID),
.M_AXI_RREADY (mr_RREADY)
);
end else begin : NO_READ
assign sr_ARREADY = 1'b0;
assign S_AXI_RID = {C_AXI_ID_WIDTH{1'b0}};
assign S_AXI_RDATA = {C_S_AXI_DATA_WIDTH{1'b0}};
assign S_AXI_RRESP = 2'b0;
assign S_AXI_RLAST = 1'b0;
assign S_AXI_RVALID = 1'b0;
assign M_AXI_ARID = {C_AXI_ID_WIDTH{1'b0}};
assign M_AXI_ARADDR = {C_AXI_ADDR_WIDTH{1'b0}};
assign M_AXI_ARLEN = 8'b0;
assign M_AXI_ARSIZE = 3'b0;
assign M_AXI_ARBURST = 2'b0;
assign M_AXI_ARLOCK = 2'b0;
assign M_AXI_ARCACHE = 4'b0;
assign M_AXI_ARPROT = 3'b0;
assign M_AXI_ARQOS = 4'b0;
assign M_AXI_ARUSER = {C_AXI_ARUSER_WIDTH{1'b0}};
assign M_AXI_ARVALID = 1'b0;
assign mr_RREADY = 1'b0;
end
endgenerate
endmodule
|
module axi_mcb_cmd_fsm
(
///////////////////////////////////////////////////////////////////////////////
// Port Declarations
///////////////////////////////////////////////////////////////////////////////
input wire clk ,
input wire reset ,
output wire axready ,
input wire axvalid ,
output wire cmd_en ,
input wire cmd_full ,
input wire calib_done ,
// signal to increment to the next mcb transaction
output wire next_cmd ,
// signal to the fsm there is another transaction required
input wire next_pending ,
// Write Data portion has completed or Read FIFO has a slot available (not
// full)
input wire data_ready ,
output wire b_push ,
input wire b_full ,
output wire r_push
);
////////////////////////////////////////////////////////////////////////////////
// Local parameters
////////////////////////////////////////////////////////////////////////////////
// AXBURST decodes
localparam SM_WAIT_FOR_CALIB_DONE = 3'b000;
localparam SM_IDLE = 3'b001;
localparam SM_CMD_EN = 3'b010;
localparam SM_CMD_ACCEPTED = 3'b011;
localparam SM_DONE_WAIT = 3'b100;
localparam SM_DONE = 3'b101;
localparam SM_FAIL = 3'b111;
////////////////////////////////////////////////////////////////////////////////
// Wires/Reg declarations
////////////////////////////////////////////////////////////////////////////////
reg [2:0] state;
reg [2:0] next_state;
////////////////////////////////////////////////////////////////////////////////
// BEGIN RTL
////////////////////////////////////////////////////////////////////////////////
// State is registered
always @(posedge clk) begin
if (reset) begin
state <= SM_WAIT_FOR_CALIB_DONE;
end else begin
state <= next_state;
end
end
// Next state transitions.
always @(*)
begin
next_state = state;
case (state)
SM_WAIT_FOR_CALIB_DONE:
if (calib_done)
next_state = SM_IDLE;
else
next_state = state;
SM_IDLE:
if (axvalid & data_ready)
next_state = SM_CMD_EN;
else
next_state = state;
SM_CMD_EN:
if (~cmd_full & next_pending)
next_state = SM_CMD_ACCEPTED;
else if (~cmd_full & ~next_pending & b_full)
next_state = SM_DONE_WAIT;
else if (~cmd_full & ~next_pending & ~b_full)
next_state = SM_DONE;
else
next_state = state;
SM_CMD_ACCEPTED:
if (data_ready)
next_state = SM_CMD_EN;
else
next_state = SM_IDLE;
SM_DONE_WAIT:
if (!b_full)
next_state = SM_DONE;
else
next_state = state;
SM_DONE:
next_state = SM_IDLE;
SM_FAIL:
next_state = SM_FAIL;
default:
next_state = SM_FAIL;
endcase
end
// Assign outputs based on current state.
assign cmd_en = (state == SM_CMD_EN);
assign next_cmd = (state == SM_CMD_ACCEPTED) || (state == SM_DONE);
assign axready = (state == SM_DONE);
assign b_push = (state == SM_DONE);
assign r_push = (state == SM_CMD_ACCEPTED) || (state == SM_DONE);
endmodule
|
module axi_mcb_incr_cmd #
(
///////////////////////////////////////////////////////////////////////////////
// Parameter Definitions
///////////////////////////////////////////////////////////////////////////////
// Width of AxADDR
// Range: 32.
parameter integer C_AXI_ADDR_WIDTH = 32,
// Width of cmd_byte_addr
// Range: 30
parameter integer C_MCB_ADDR_WIDTH = 30,
// Width of AXI xDATA and MCB xx_data
// Range: 32, 64, 128.
parameter integer C_DATA_WIDTH = 32,
// Width of the read counters per mcb transaction
// Range: 4
parameter integer C_CNT_WIDTH = 4,
// Static value of axsize
// Rannge: 2-4
parameter integer C_AXSIZE = 2
)
(
///////////////////////////////////////////////////////////////////////////////
// Port Declarations
///////////////////////////////////////////////////////////////////////////////
input wire clk ,
input wire reset ,
input wire [C_AXI_ADDR_WIDTH-1:0] axaddr ,
input wire [7:0] axlen ,
input wire [2:0] axsize ,
// axhandshake = axvalid & axready
input wire axhandshake ,
output wire [5:0] cmd_bl ,
output wire [C_MCB_ADDR_WIDTH-1:0] cmd_byte_addr ,
// Connections to/from fsm module
// signal to increment to the next mcb transaction
input wire next_cmd ,
// signal to the fsm there is another transaction required
output wire next_pending
);
////////////////////////////////////////////////////////////////////////////////
// Local parameters
////////////////////////////////////////////////////////////////////////////////
localparam P_AXLEN_WIDTH = 8;
localparam P_CMD_BL_WIDTH = 6;
// AXI commands cannot cross 4096 byte boundaries, set counter max at 12 bits
localparam P_AXI_CNT_WIDTH_MAX = 12;
// Address will always increment by at least C_CNT_WIDTH+
localparam P_AXADDR_CNT_WIDTH = P_AXI_CNT_WIDTH_MAX-(8-C_CNT_WIDTH)-C_AXSIZE;
localparam P_AXADDR_CNT_START = C_AXSIZE + C_CNT_WIDTH;
////////////////////////////////////////////////////////////////////////////////
// Wire and register declarations
////////////////////////////////////////////////////////////////////////////////
reg sel_first;
wire [C_MCB_ADDR_WIDTH-1:0] axaddr_i;
wire [C_MCB_ADDR_WIDTH-1:0] axaddr_incr;
wire [P_AXADDR_CNT_WIDTH-1:0] axaddr_cnt_in;
reg [P_AXADDR_CNT_WIDTH-1:0] axaddr_cnt;
wire [C_CNT_WIDTH-1:0] axlen_i;
wire [C_CNT_WIDTH-1:0] cmd_bl_i;
reg [C_CNT_WIDTH-1:0] axlen_cnt;
wire [C_CNT_WIDTH-1:0] axlen_msb_cnt;
reg axlen_cnt_not_zero;
////////////////////////////////////////////////////////////////////////////////
// BEGIN RTL
////////////////////////////////////////////////////////////////////////////////
// calculate cmd_byte_addr
assign cmd_byte_addr = (sel_first) ? axaddr_i : axaddr_incr;
assign axaddr_i = axaddr[0 +: C_MCB_ADDR_WIDTH];
// Incremented version of axaddr
assign axaddr_incr = {
axaddr_i[P_AXI_CNT_WIDTH_MAX +: C_MCB_ADDR_WIDTH-P_AXI_CNT_WIDTH_MAX],
axaddr_cnt,
axaddr_i[0 +: C_AXSIZE+C_CNT_WIDTH]
};
// Pull off bits to increment
assign axaddr_cnt_in = axaddr_i[P_AXADDR_CNT_START +: P_AXADDR_CNT_WIDTH];
// Address Increment Counter
always @(posedge clk) begin
if (next_cmd) begin
axaddr_cnt <= axaddr_cnt + 1'b1;
end else if (sel_first) begin
axaddr_cnt <= axaddr_cnt_in;
end
end
// Calculat cmd_bl
assign cmd_bl = {{(P_CMD_BL_WIDTH-C_CNT_WIDTH){1'b0}}, cmd_bl_i};
assign cmd_bl_i = (next_pending) ? {C_CNT_WIDTH{1'b1}} : axlen_i;
assign axlen_i = axlen[C_CNT_WIDTH-1:0];
// assign next_pending = axlen_msb_cnt > {P_AXADDR_CNT_WIDTH{1'b0}};
assign next_pending = (sel_first) ? (| axlen[C_CNT_WIDTH +: 8-C_CNT_WIDTH]) : axlen_cnt_not_zero;
assign axlen_msb_cnt = (sel_first) ? axlen[C_CNT_WIDTH +: 8-C_CNT_WIDTH] : axlen_cnt;
// Counter to hold number of transactions left to issue
always @(posedge clk) begin
if (next_cmd) begin
axlen_cnt <= axlen_msb_cnt - 1'b1;
axlen_cnt_not_zero <= (axlen_msb_cnt != {{C_CNT_WIDTH-1{1'b0}}, 1'b1});
end
end
// Indicates if we are on the first transaction of a mcb translation with more
// than 1 transaction.
always @(posedge clk) begin
if (reset | axhandshake) begin
sel_first <= 1'b1;
end else if (next_cmd) begin
sel_first <= 1'b0;
end
end
endmodule
|
module axi_mcb_cmd_arbiter #
(
///////////////////////////////////////////////////////////////////////////////
// Parameter Definitions
///////////////////////////////////////////////////////////////////////////////
// Width of cmd_byte_addr
// Range: 30
parameter integer C_MCB_ADDR_WIDTH = 30
)
(
///////////////////////////////////////////////////////////////////////////////
// Port Declarations
///////////////////////////////////////////////////////////////////////////////
// AXI Slave Interface
// Slave Interface System Signals
input wire clk ,
input wire reset ,
input wire wr_cmd_en ,
input wire [2:0] wr_cmd_instr ,
input wire wr_wrap_cmd_sel ,
input wire [5:0] wr_wrap_cmd_bl ,
input wire [C_MCB_ADDR_WIDTH-1:0] wr_wrap_cmd_byte_addr ,
input wire [5:0] wr_incr_cmd_bl ,
input wire [C_MCB_ADDR_WIDTH-1:0] wr_incr_cmd_byte_addr ,
output wire wr_cmd_empty ,
output wire wr_cmd_full ,
input wire wr_cmd_has_next_pending ,
input wire rd_cmd_en ,
input wire [2:0] rd_cmd_instr ,
input wire rd_wrap_cmd_sel ,
input wire [5:0] rd_wrap_cmd_bl ,
input wire [C_MCB_ADDR_WIDTH-1:0] rd_wrap_cmd_byte_addr ,
input wire [5:0] rd_incr_cmd_bl ,
input wire [C_MCB_ADDR_WIDTH-1:0] rd_incr_cmd_byte_addr ,
output wire rd_cmd_empty ,
output wire rd_cmd_full ,
input wire rd_cmd_has_next_pending ,
output wire cmd_en ,
output wire [2:0] cmd_instr ,
output wire [5:0] cmd_bl ,
output wire [C_MCB_ADDR_WIDTH-1:0] cmd_byte_addr ,
input wire cmd_empty ,
input wire cmd_full
);
////////////////////////////////////////////////////////////////////////////////
// Local parameters
////////////////////////////////////////////////////////////////////////////////
localparam P_ARB_ALGO = "READ_PRIORITY_REG";
//localparam P_ARB_ALGO = "ROUND_ROBIN";
////////////////////////////////////////////////////////////////////////////////
// Wires/Reg declarations
////////////////////////////////////////////////////////////////////////////////
wire rnw;
reg [C_MCB_ADDR_WIDTH-1:0] cmd_byte_addr_i;
reg [5:0] cmd_bl_i;
reg wr_cmd_en_last;
reg rd_cmd_en_last;
////////////////////////////////////////////////////////////////////////////////
// BEGIN RTL
////////////////////////////////////////////////////////////////////////////////
assign cmd_en = rnw ? rd_cmd_en : wr_cmd_en;
assign cmd_instr = rnw ? rd_cmd_instr : wr_cmd_instr;
assign cmd_bl = cmd_bl_i;
assign cmd_byte_addr = cmd_byte_addr_i;
assign wr_cmd_empty = cmd_empty;
assign wr_cmd_full = rnw ? 1'b1 : cmd_full;
assign rd_cmd_empty = cmd_empty;
assign rd_cmd_full = ~rnw ? 1'b1 : cmd_full;
always @(*) begin
casex ({wr_wrap_cmd_sel, rd_wrap_cmd_sel, rnw}) // synopsys parallel_case
3'bx01: cmd_byte_addr_i = rd_incr_cmd_byte_addr;
3'bx11: cmd_byte_addr_i = rd_wrap_cmd_byte_addr;
3'b1x0: cmd_byte_addr_i = wr_wrap_cmd_byte_addr;
default: cmd_byte_addr_i = wr_incr_cmd_byte_addr; // 3'b0x0
endcase
end
always @(*) begin
casex ({wr_wrap_cmd_sel, rd_wrap_cmd_sel, rnw}) // synopsys parallel_case
3'bx01: cmd_bl_i = rd_incr_cmd_bl;
3'bx11: cmd_bl_i = rd_wrap_cmd_bl;
3'b1x0: cmd_bl_i = wr_wrap_cmd_bl;
default: cmd_bl_i = wr_incr_cmd_bl; // 3'b0x0
endcase
end
generate
// TDM Arbitration scheme
if (P_ARB_ALGO == "TDM") begin : TDM
reg rnw_i;
// Register rnw status
always @(posedge clk) begin
if (reset) begin
rnw_i <= 1'b0;
end else begin
rnw_i <= ~rnw_i;
end
end
assign rnw = rnw_i;
end
else if (P_ARB_ALGO == "ROUND_ROBIN") begin : ROUND_ROBIN
reg rnw_i;
// Register rnw status
always @(posedge clk) begin
if (reset) begin
rnw_i <= 1'b0;
end else begin
rnw_i <= ~rnw_i;
end
end
assign rnw = (rnw_i & rd_cmd_en) | (~rnw_i & rd_cmd_en & ~wr_cmd_en);
end
else if (P_ARB_ALGO == "ROUND_ROBIN") begin : ROUND_ROBIN
reg rnw_i;
// Register rnw status
always @(posedge clk) begin
if (reset) begin
rnw_i <= 1'b0;
end else begin
rnw_i <= ~rnw_i;
end
end
assign rnw = (rnw_i & rd_cmd_en) | (~rnw_i & rd_cmd_en & ~wr_cmd_en);
end
else if (P_ARB_ALGO == "READ_PRIORITY_REG") begin : READ_PRIORITY_REG
reg rnw_i;
reg rd_cmd_en_last;
reg wr_cmd_en_last;
wire rd_req;
wire wr_req;
always @(posedge clk) begin
rd_cmd_en_last <= rnw & rd_cmd_en & rd_cmd_has_next_pending;
wr_cmd_en_last <= ~rnw & wr_cmd_en & wr_cmd_has_next_pending;
end
// Register rnw status
always @(posedge clk) begin
if (reset) begin
rnw_i <= 1'b1;
end else begin
// Only set RNW to 0 if there is a write pending and read is idle
rnw_i <= rd_req & ~wr_cmd_en_last ? 1'b1 : ~wr_req;
end
end
assign rd_req = rd_cmd_en | rd_cmd_en_last;
assign wr_req = wr_cmd_en | wr_cmd_en_last;
assign rnw = rnw_i;
end
else if (P_ARB_ALGO == "READ_PRIORITY") begin : READ_PRIORITY
assign rnw = ~(wr_cmd_en & ~rd_cmd_en);
end
else if (P_ARB_ALGO == "WRITE_PRIORITY_REG") begin : WRITE_PRIORITY_REG
reg rnw_i;
// Register rnw status
always @(posedge clk) begin
if (reset) begin
rnw_i <= 1'b0;
end else begin
// Only set RNW to 1 if there is a read pending and write is idle
rnw_i <= (~wr_cmd_en & rd_cmd_en);
end
end
assign rnw = rnw_i;
end
else begin : WRITE_PRIORITY
assign rnw = (~wr_cmd_en & rd_cmd_en);
end
endgenerate
endmodule
|
module carry_or #
(
parameter C_FAMILY = "virtex6"
// FPGA Family. Current version: virtex6 or spartan6.
)
(
input wire CIN,
input wire S,
output wire COUT
);
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Instantiate or use RTL code
/////////////////////////////////////////////////////////////////////////////
generate
if ( C_FAMILY == "rtl" ) begin : USE_RTL
assign COUT = CIN | S;
end else begin : USE_FPGA
wire S_n;
assign S_n = ~S;
MUXCY and_inst
(
.O (COUT),
.CI (CIN),
.DI (1'b1),
.S (S_n)
);
end
endgenerate
endmodule
|
module carry_latch_or #
(
parameter C_FAMILY = "virtex6"
// FPGA Family. Current version: virtex6 or spartan6.
)
(
input wire CIN,
input wire I,
output wire O
);
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Instantiate or use RTL code
/////////////////////////////////////////////////////////////////////////////
generate
if ( C_FAMILY == "rtl" ) begin : USE_RTL
assign O = CIN | I;
end else begin : USE_FPGA
OR2L or2l_inst1
(
.O(O),
.DI(CIN),
.SRI(I)
);
end
endgenerate
endmodule
|
module axi_mcb_b_channel #
(
///////////////////////////////////////////////////////////////////////////////
// Parameter Definitions
///////////////////////////////////////////////////////////////////////////////
// Width of ID signals.
// Range: >= 1.
parameter integer C_ID_WIDTH = 4 ,
// Enforces strict checking across all MCB ports for
// write data coherency. This will ensure no race
// conditions will exist between the BRESP and any
// other read/write command on a different MCB port.
// Not necessary for single port MCB operation.
// Range: 0, 1
parameter integer C_STRICT_COHERENCY = 0
)
(
///////////////////////////////////////////////////////////////////////////////
// Port Declarations
///////////////////////////////////////////////////////////////////////////////
input wire clk,
input wire reset,
// AXI signals
output wire [C_ID_WIDTH-1:0] bid,
output wire [1:0] bresp,
output wire bvalid,
input wire bready,
// Signals to/from the axi_mcb_aw_channel modules
input wire b_push,
input wire [C_ID_WIDTH-1:0] b_awid,
output wire b_full,
// MCB signals
// Signal from MCB indicating FIFO underrun or FIFO error, not used.
input wire mcb_error,
// Signal from MCB indicating either cmd fifo is empty
input wire mcb_cmd_empty,
// Signal from MCB indicating either cmd fifo is full
input wire mcb_cmd_full,
// Signal from MCB indicating either wr fifo is empty
input wire mcb_wr_empty
);
////////////////////////////////////////////////////////////////////////////////
// Local parameters
////////////////////////////////////////////////////////////////////////////////
// FIFO settings
localparam P_WIDTH = C_ID_WIDTH;
localparam P_DEPTH = 4;
localparam P_AWIDTH = 2;
// AXI protocol responses:
localparam P_OKAY = 2'b00;
localparam P_EXOKAY = 2'b01;
localparam P_SLVERR = 2'b10;
localparam P_DECERR = 2'b11;
////////////////////////////////////////////////////////////////////////////////
// Wire and register declarations
////////////////////////////////////////////////////////////////////////////////
reg bvalid_i;
wire [C_ID_WIDTH-1:0] bid_i;
wire bhandshake;
wire empty;
wire mcb_cmd_is_done;
////////////////////////////////////////////////////////////////////////////////
// BEGIN RTL
////////////////////////////////////////////////////////////////////////////////
// assign AXI outputs
assign bid = bid_i;
assign bresp = P_OKAY;
assign bvalid = bvalid_i;
assign bhandshake = bvalid & bready;
assign mcb_cmd_is_done = mcb_cmd_empty | mcb_wr_empty | (~mcb_cmd_full & b_full);
// Register output of bvalid
always @(posedge clk) begin
if (reset | bhandshake) begin
bvalid_i <= 1'b0;
end else if (~empty & ((C_STRICT_COHERENCY == 0) | mcb_cmd_is_done)) begin
bvalid_i <= 1'b1;
end
end
axi_mcb_simple_fifo #(
.C_WIDTH (P_WIDTH),
.C_AWIDTH (P_AWIDTH),
.C_DEPTH (P_DEPTH)
)
bid_fifo_0
(
.clk ( clk ) ,
.rst ( reset ) ,
.wr_en ( b_push ) ,
.rd_en ( bhandshake ) ,
.din ( b_awid ) ,
.dout ( bid_i ) ,
.a_full ( ) ,
.full ( b_full ) ,
.a_empty ( ) ,
.empty ( empty )
);
endmodule
|
module mux_enc #
(
parameter C_FAMILY = "rtl",
// FPGA Family. Current version: virtex6 or spartan6.
parameter integer C_RATIO = 4,
// Mux select ratio. Can be any binary value (>= 1)
parameter integer C_SEL_WIDTH = 2,
// Log2-ceiling of C_RATIO (>= 1)
parameter integer C_DATA_WIDTH = 1
// Data width for comparator (>= 1)
)
(
input wire [C_SEL_WIDTH-1:0] S,
input wire [C_RATIO*C_DATA_WIDTH-1:0] A,
output wire [C_DATA_WIDTH-1:0] O,
input wire OE
);
wire [C_DATA_WIDTH-1:0] o_i;
genvar bit_cnt;
function [C_DATA_WIDTH-1:0] f_mux
(
input [C_SEL_WIDTH-1:0] s,
input [C_RATIO*C_DATA_WIDTH-1:0] a
);
integer i;
reg [C_RATIO*C_DATA_WIDTH-1:0] carry;
begin
carry[C_DATA_WIDTH-1:0] = {C_DATA_WIDTH{(s==0)?1'b1:1'b0}} & a[C_DATA_WIDTH-1:0];
for (i=1;i<C_RATIO;i=i+1) begin : gen_carrychain_enc
carry[i*C_DATA_WIDTH +: C_DATA_WIDTH] =
carry[(i-1)*C_DATA_WIDTH +: C_DATA_WIDTH] |
({C_DATA_WIDTH{(s==i)?1'b1:1'b0}} & a[i*C_DATA_WIDTH +: C_DATA_WIDTH]);
end
f_mux = carry[C_DATA_WIDTH*C_RATIO-1:C_DATA_WIDTH*(C_RATIO-1)];
end
endfunction
function [C_DATA_WIDTH-1:0] f_mux4
(
input [1:0] s,
input [4*C_DATA_WIDTH-1:0] a
);
integer i;
reg [4*C_DATA_WIDTH-1:0] carry;
begin
carry[C_DATA_WIDTH-1:0] = {C_DATA_WIDTH{(s==0)?1'b1:1'b0}} & a[C_DATA_WIDTH-1:0];
for (i=1;i<4;i=i+1) begin : gen_carrychain_enc
carry[i*C_DATA_WIDTH +: C_DATA_WIDTH] =
carry[(i-1)*C_DATA_WIDTH +: C_DATA_WIDTH] |
({C_DATA_WIDTH{(s==i)?1'b1:1'b0}} & a[i*C_DATA_WIDTH +: C_DATA_WIDTH]);
end
f_mux4 = carry[C_DATA_WIDTH*4-1:C_DATA_WIDTH*3];
end
endfunction
assign O = o_i & {C_DATA_WIDTH{OE}}; // OE is gated AFTER any MUXF7/8 (can only optimize forward into downstream logic)
generate
if ( C_RATIO < 2 ) begin : gen_bypass
assign o_i = A;
end else if ( C_FAMILY == "rtl" || C_RATIO < 5 ) begin : gen_rtl
assign o_i = f_mux(S, A);
end else begin : gen_fpga
wire [C_DATA_WIDTH-1:0] l;
wire [C_DATA_WIDTH-1:0] h;
wire [C_DATA_WIDTH-1:0] ll;
wire [C_DATA_WIDTH-1:0] lh;
wire [C_DATA_WIDTH-1:0] hl;
wire [C_DATA_WIDTH-1:0] hh;
case (C_RATIO)
1, 5, 9, 13:
assign hh = A[(C_RATIO-1)*C_DATA_WIDTH +: C_DATA_WIDTH];
2, 6, 10, 14:
assign hh = S[0] ?
A[(C_RATIO-1)*C_DATA_WIDTH +: C_DATA_WIDTH] :
A[(C_RATIO-2)*C_DATA_WIDTH +: C_DATA_WIDTH] ;
3, 7, 11, 15:
assign hh = S[1] ?
A[(C_RATIO-1)*C_DATA_WIDTH +: C_DATA_WIDTH] :
(S[0] ?
A[(C_RATIO-2)*C_DATA_WIDTH +: C_DATA_WIDTH] :
A[(C_RATIO-3)*C_DATA_WIDTH +: C_DATA_WIDTH] );
4, 8, 12, 16:
assign hh = S[1] ?
(S[0] ?
A[(C_RATIO-1)*C_DATA_WIDTH +: C_DATA_WIDTH] :
A[(C_RATIO-2)*C_DATA_WIDTH +: C_DATA_WIDTH] ) :
(S[0] ?
A[(C_RATIO-3)*C_DATA_WIDTH +: C_DATA_WIDTH] :
A[(C_RATIO-4)*C_DATA_WIDTH +: C_DATA_WIDTH] );
17:
assign hh = S[1] ?
(S[0] ?
A[15*C_DATA_WIDTH +: C_DATA_WIDTH] :
A[14*C_DATA_WIDTH +: C_DATA_WIDTH] ) :
(S[0] ?
A[13*C_DATA_WIDTH +: C_DATA_WIDTH] :
A[12*C_DATA_WIDTH +: C_DATA_WIDTH] );
default:
assign hh = 0;
endcase
case (C_RATIO)
5, 6, 7, 8: begin
assign l = f_mux4(S[1:0], A[0 +: 4*C_DATA_WIDTH]);
for (bit_cnt = 0; bit_cnt < C_DATA_WIDTH ; bit_cnt = bit_cnt + 1) begin : gen_mux_5_8
MUXF7 mux_s2_inst
(
.I0 (l[bit_cnt]),
.I1 (hh[bit_cnt]),
.S (S[2]),
.O (o_i[bit_cnt])
);
end
end
9, 10, 11, 12: begin
assign ll = f_mux4(S[1:0], A[0 +: 4*C_DATA_WIDTH]);
assign lh = f_mux4(S[1:0], A[4*C_DATA_WIDTH +: 4*C_DATA_WIDTH]);
for (bit_cnt = 0; bit_cnt < C_DATA_WIDTH ; bit_cnt = bit_cnt + 1) begin : gen_mux_9_12
MUXF7 muxf_s2_low_inst
(
.I0 (ll[bit_cnt]),
.I1 (lh[bit_cnt]),
.S (S[2]),
.O (l[bit_cnt])
);
MUXF8 muxf_s3_inst
(
.I0 (l[bit_cnt]),
.I1 (hh[bit_cnt]),
.S (S[3]),
.O (o_i[bit_cnt])
);
end
end
13,14,15,16: begin
assign ll = f_mux4(S[1:0], A[0 +: 4*C_DATA_WIDTH]);
assign lh = f_mux4(S[1:0], A[4*C_DATA_WIDTH +: 4*C_DATA_WIDTH]);
assign hl = f_mux4(S[1:0], A[8*C_DATA_WIDTH +: 4*C_DATA_WIDTH]);
for (bit_cnt = 0; bit_cnt < C_DATA_WIDTH ; bit_cnt = bit_cnt + 1) begin : gen_mux_13_16
MUXF7 muxf_s2_low_inst
(
.I0 (ll[bit_cnt]),
.I1 (lh[bit_cnt]),
.S (S[2]),
.O (l[bit_cnt])
);
MUXF7 muxf_s2_hi_inst
(
.I0 (hl[bit_cnt]),
.I1 (hh[bit_cnt]),
.S (S[2]),
.O (h[bit_cnt])
);
MUXF8 muxf_s3_inst
(
.I0 (l[bit_cnt]),
.I1 (h[bit_cnt]),
.S (S[3]),
.O (o_i[bit_cnt])
);
end
end
17: begin
assign ll = S[4] ? A[16*C_DATA_WIDTH +: C_DATA_WIDTH] : f_mux4(S[1:0], A[0 +: 4*C_DATA_WIDTH]); // 5-input mux
assign lh = f_mux4(S[1:0], A[4*C_DATA_WIDTH +: 4*C_DATA_WIDTH]);
assign hl = f_mux4(S[1:0], A[8*C_DATA_WIDTH +: 4*C_DATA_WIDTH]);
for (bit_cnt = 0; bit_cnt < C_DATA_WIDTH ; bit_cnt = bit_cnt + 1) begin : gen_mux_17
MUXF7 muxf_s2_low_inst
(
.I0 (ll[bit_cnt]),
.I1 (lh[bit_cnt]),
.S (S[2]),
.O (l[bit_cnt])
);
MUXF7 muxf_s2_hi_inst
(
.I0 (hl[bit_cnt]),
.I1 (hh[bit_cnt]),
.S (S[2]),
.O (h[bit_cnt])
);
MUXF8 muxf_s3_inst
(
.I0 (l[bit_cnt]),
.I1 (h[bit_cnt]),
.S (S[3]),
.O (o_i[bit_cnt])
);
end
end
default: // If RATIO > 17, use RTL
assign o_i = f_mux(S, A);
endcase
end // gen_fpga
endgenerate
endmodule
|
module comparator_sel_static #
(
parameter C_FAMILY = "virtex6",
// FPGA Family. Current version: virtex6 or spartan6.
parameter C_VALUE = 4'b0,
// Static value to compare against.
parameter integer C_DATA_WIDTH = 4
// Data width for comparator.
)
(
input wire CIN,
input wire S,
input wire [C_DATA_WIDTH-1:0] A,
input wire [C_DATA_WIDTH-1:0] B,
output wire COUT
);
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
/////////////////////////////////////////////////////////////////////////////
// Generate variable for bit vector.
genvar bit_cnt;
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
// Bits per LUT for this architecture.
localparam integer C_BITS_PER_LUT = 2;
// Constants for packing levels.
localparam integer C_NUM_LUT = ( C_DATA_WIDTH + C_BITS_PER_LUT - 1 ) / C_BITS_PER_LUT;
//
localparam integer C_FIX_DATA_WIDTH = ( C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH ) ? C_NUM_LUT * C_BITS_PER_LUT :
C_DATA_WIDTH;
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
wire [C_FIX_DATA_WIDTH-1:0] a_local;
wire [C_FIX_DATA_WIDTH-1:0] b_local;
wire [C_FIX_DATA_WIDTH-1:0] v_local;
wire [C_NUM_LUT-1:0] sel;
wire [C_NUM_LUT:0] carry_local;
/////////////////////////////////////////////////////////////////////////////
//
/////////////////////////////////////////////////////////////////////////////
generate
// Assign input to local vectors.
assign carry_local[0] = CIN;
// Extend input data to fit.
if ( C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH ) begin : USE_EXTENDED_DATA
assign a_local = {A, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};
assign b_local = {B, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};
assign v_local = {C_VALUE, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};
end else begin : NO_EXTENDED_DATA
assign a_local = A;
assign b_local = B;
assign v_local = C_VALUE;
end
// Instantiate one carry and per level.
for (bit_cnt = 0; bit_cnt < C_NUM_LUT ; bit_cnt = bit_cnt + 1) begin : LUT_LEVEL
// Create the local select signal
assign sel[bit_cnt] = ( ( a_local[bit_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ==
v_local[bit_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ) & ( S == 1'b0 ) ) |
( ( b_local[bit_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ==
v_local[bit_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ) & ( S == 1'b1 ) );
// Instantiate each LUT level.
carry_and #
(
.C_FAMILY(C_FAMILY)
) compare_inst
(
.COUT (carry_local[bit_cnt+1]),
.CIN (carry_local[bit_cnt]),
.S (sel[bit_cnt])
);
end // end for bit_cnt
// Assign output from local vector.
assign COUT = carry_local[C_NUM_LUT];
endgenerate
endmodule
|
module axi_mcb_r_channel #
(
///////////////////////////////////////////////////////////////////////////////
// Parameter Definitions
///////////////////////////////////////////////////////////////////////////////
// Width of ID signals.
// Range: >= 1.
parameter integer C_ID_WIDTH = 4,
// Width of AXI xDATA and MCB xx_data
// Range: 32, 64, 128.
parameter integer C_DATA_WIDTH = 32,
// Width of beat counter, limits max transaction size.
// Range: 1-6 (-> 2-64 beat transactions)
parameter integer C_CNT_WIDTH = 4,
// Pipelines the output of rd_empty to rvalid,
// Adds at least one cycle of latency.
parameter integer C_PL_RD_EMPTY = 1
)
(
///////////////////////////////////////////////////////////////////////////////
// Port Declarations
///////////////////////////////////////////////////////////////////////////////
input wire clk ,
input wire reset ,
output wire [C_ID_WIDTH-1:0] rid ,
output wire [C_DATA_WIDTH-1:0] rdata ,
output wire [1:0] rresp ,
output wire rlast ,
output wire rvalid ,
input wire rready ,
output wire rd_en ,
input wire [C_DATA_WIDTH-1:0] rd_data ,
input wire rd_full ,
input wire rd_empty ,
input wire [6:0] rd_count ,
input wire rd_overflow ,
input wire rd_error ,
// Connections to/from axi_mcb_ar_channel module
input wire r_push ,
input wire [C_CNT_WIDTH-1:0] r_length ,
input wire [C_ID_WIDTH-1:0] r_arid ,
input wire r_rlast ,
output wire r_full
);
////////////////////////////////////////////////////////////////////////////////
// Local parameters
////////////////////////////////////////////////////////////////////////////////
localparam P_WIDTH = C_CNT_WIDTH+C_ID_WIDTH+2;
localparam P_DEPTH = (C_CNT_WIDTH == 4) ? 4 :
(C_CNT_WIDTH == 5) ? 2 :
1;
localparam P_AWIDTH = (P_DEPTH == 4) ? 2 : 1;
// AXI protocol responses:
localparam P_OKAY = 2'b00;
localparam P_EXOKAY = 2'b01;
localparam P_SLVERR = 2'b10;
localparam P_DECERR = 2'b11;
////////////////////////////////////////////////////////////////////////////////
// Wire and register declarations
////////////////////////////////////////////////////////////////////////////////
wire [C_ID_WIDTH-1:0] rid_i;
reg cnt_is_zero;
wire assert_rlast;
wire length_is_zero_i;
wire length_is_zero;
wire [P_WIDTH-1:0] trans_in;
wire [P_WIDTH-1:0] trans_out;
wire fifo_a_full;
wire fifo_full;
wire fifo_empty;
wire [C_CNT_WIDTH-1:0] length;
wire rhandshake;
reg [C_CNT_WIDTH-1:0] cnt;
wire [C_CNT_WIDTH-1:0] rcnt;
wire rvalid_i;
reg sel_first;
(* KEEP = "TRUE" *) wire done /* synthesis syn_keep = 1 */;
////////////////////////////////////////////////////////////////////////////////
// BEGIN RTL
////////////////////////////////////////////////////////////////////////////////
// assign AXI outputs
assign rid = rid_i;
assign rdata = rd_data;
assign rresp = P_OKAY;
assign rlast = ((length_is_zero | cnt_is_zero) & assert_rlast);
assign rvalid = rvalid_i;
generate
if (C_PL_RD_EMPTY) begin : PL_RD_EMPTY
reg rd_empty_d1;
reg [6:0] rd_count_d1;
reg rhandshake_d1;
reg rd_count_gt_2;
reg fifo_empty_d1;
assign rvalid_i = ((~rd_empty_d1 & ~rhandshake_d1) | rd_count_gt_2);
always @(posedge clk) begin
rd_empty_d1 <= rd_empty;
rd_count_d1 <= rd_count;
rhandshake_d1 <= rhandshake;
rd_count_gt_2 <= rd_count > 2;
fifo_empty_d1 <= fifo_empty;
end
end
else begin : NO_PL_RD_EMPTY
assign rvalid_i = ~rd_empty & ~fifo_empty;
end
endgenerate
// assign MCB outputs
assign rd_en = rhandshake;
// assign axi_mcb_ar_channel outputs
assign r_full = fifo_full | (r_push & fifo_a_full);
// Push input from axi_mcb_ar_channel into FIFO
assign length_is_zero_i = (r_length[0 +: C_CNT_WIDTH] == 0);
assign trans_in = {r_length, r_arid, r_rlast, length_is_zero_i};
axi_mcb_simple_fifo #(
.C_WIDTH (P_WIDTH),
.C_AWIDTH (P_AWIDTH),
.C_DEPTH (P_DEPTH)
)
transaction_fifo_0
(
.clk ( clk ) ,
.rst ( reset ) ,
.wr_en ( r_push ) ,
.rd_en ( done ) ,
.din ( trans_in ) ,
.dout ( trans_out ) ,
.a_full ( fifo_a_full ) ,
.full ( fifo_full ) ,
.a_empty ( ) ,
.empty ( fifo_empty )
);
assign length = trans_out[2+C_ID_WIDTH +: C_CNT_WIDTH];
assign rid_i = trans_out[2 +: C_ID_WIDTH];
assign assert_rlast = trans_out[1];
assign length_is_zero = trans_out[0];
// Alias for succesful handshake
assign rhandshake = rvalid & rready;
// Read Transaction counter
always @(posedge clk) begin
if (rhandshake) begin
cnt <= rcnt - 1'b1;
end
end
// Register compare output of counter for timing
always @(posedge clk) begin
if (reset) begin
cnt_is_zero <= 1'b0;
end
else if (rhandshake) begin
cnt_is_zero <= (rcnt == {{C_CNT_WIDTH-1{1'b0}}, 1'b1}); // rcnt == 1
end
end
// For the first beat, use the output of the fifo, otherwise use the output of
// the counter
assign rcnt = sel_first ? length : cnt;
// Indicates if we are on the first beat of a transaction
always @(posedge clk) begin
if (reset | done) begin
sel_first <= 1'b1;
end else if (rhandshake) begin
sel_first <= 1'b0;
end
end
// Transaction is complete when rhandshake and rcnt_is_zero
// assign done = rvalid & rready & rcnt_is_zero;
// Timing optimiziation of above statement
assign done = rvalid & rready & (length_is_zero | cnt_is_zero);
endmodule
|
module comparator_mask #
(
parameter C_FAMILY = "virtex6",
// FPGA Family. Current version: virtex6 or spartan6.
parameter integer C_DATA_WIDTH = 4
// Data width for comparator.
)
(
input wire CIN,
input wire [C_DATA_WIDTH-1:0] A,
input wire [C_DATA_WIDTH-1:0] B,
input wire [C_DATA_WIDTH-1:0] M,
output wire COUT
);
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
/////////////////////////////////////////////////////////////////////////////
// Generate variable for bit vector.
genvar lut_cnt;
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
// Bits per LUT for this architecture.
localparam integer C_BITS_PER_LUT = 2;
// Constants for packing levels.
localparam integer C_NUM_LUT = ( C_DATA_WIDTH + C_BITS_PER_LUT - 1 ) / C_BITS_PER_LUT;
//
localparam integer C_FIX_DATA_WIDTH = ( C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH ) ? C_NUM_LUT * C_BITS_PER_LUT :
C_DATA_WIDTH;
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
wire [C_FIX_DATA_WIDTH-1:0] a_local;
wire [C_FIX_DATA_WIDTH-1:0] b_local;
wire [C_FIX_DATA_WIDTH-1:0] m_local;
wire [C_NUM_LUT-1:0] sel;
wire [C_NUM_LUT:0] carry_local;
/////////////////////////////////////////////////////////////////////////////
//
/////////////////////////////////////////////////////////////////////////////
generate
// Assign input to local vectors.
assign carry_local[0] = CIN;
// Extend input data to fit.
if ( C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH ) begin : USE_EXTENDED_DATA
assign a_local = {A, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};
assign b_local = {B, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};
assign m_local = {M, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};
end else begin : NO_EXTENDED_DATA
assign a_local = A;
assign b_local = B;
assign m_local = M;
end
// Instantiate one carry and per level.
for (lut_cnt = 0; lut_cnt < C_NUM_LUT ; lut_cnt = lut_cnt + 1) begin : LUT_LEVEL
// Create the local select signal
assign sel[lut_cnt] = ( ( a_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] &
m_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ) ==
( b_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] &
m_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ) );
// Instantiate each LUT level.
carry_and #
(
.C_FAMILY(C_FAMILY)
) compare_inst
(
.COUT (carry_local[lut_cnt+1]),
.CIN (carry_local[lut_cnt]),
.S (sel[lut_cnt])
);
end // end for lut_cnt
// Assign output from local vector.
assign COUT = carry_local[C_NUM_LUT];
endgenerate
endmodule
|
module comparator_sel #
(
parameter C_FAMILY = "virtex6",
// FPGA Family. Current version: virtex6 or spartan6.
parameter integer C_DATA_WIDTH = 4
// Data width for comparator.
)
(
input wire CIN,
input wire S,
input wire [C_DATA_WIDTH-1:0] A,
input wire [C_DATA_WIDTH-1:0] B,
input wire [C_DATA_WIDTH-1:0] V,
output wire COUT
);
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
/////////////////////////////////////////////////////////////////////////////
// Generate variable for bit vector.
genvar bit_cnt;
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
// Bits per LUT for this architecture.
localparam integer C_BITS_PER_LUT = 1;
// Constants for packing levels.
localparam integer C_NUM_LUT = ( C_DATA_WIDTH + C_BITS_PER_LUT - 1 ) / C_BITS_PER_LUT;
//
localparam integer C_FIX_DATA_WIDTH = ( C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH ) ? C_NUM_LUT * C_BITS_PER_LUT :
C_DATA_WIDTH;
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
wire [C_FIX_DATA_WIDTH-1:0] a_local;
wire [C_FIX_DATA_WIDTH-1:0] b_local;
wire [C_FIX_DATA_WIDTH-1:0] v_local;
wire [C_NUM_LUT-1:0] sel;
wire [C_NUM_LUT:0] carry_local;
/////////////////////////////////////////////////////////////////////////////
//
/////////////////////////////////////////////////////////////////////////////
generate
// Assign input to local vectors.
assign carry_local[0] = CIN;
// Extend input data to fit.
if ( C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH ) begin : USE_EXTENDED_DATA
assign a_local = {A, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};
assign b_local = {B, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};
assign v_local = {V, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};
end else begin : NO_EXTENDED_DATA
assign a_local = A;
assign b_local = B;
assign v_local = V;
end
// Instantiate one carry and per level.
for (bit_cnt = 0; bit_cnt < C_NUM_LUT ; bit_cnt = bit_cnt + 1) begin : LUT_LEVEL
// Create the local select signal
assign sel[bit_cnt] = ( ( a_local[bit_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ==
v_local[bit_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ) & ( S == 1'b0 ) ) |
( ( b_local[bit_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ==
v_local[bit_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ) & ( S == 1'b1 ) );
// Instantiate each LUT level.
carry_and #
(
.C_FAMILY(C_FAMILY)
) compare_inst
(
.COUT (carry_local[bit_cnt+1]),
.CIN (carry_local[bit_cnt]),
.S (sel[bit_cnt])
);
end // end for bit_cnt
// Assign output from local vector.
assign COUT = carry_local[C_NUM_LUT];
endgenerate
endmodule
|
module mcb_ui_top_synch #
(
///////////////////////////////////////////////////////////////////////////////
// Parameter Definitions
///////////////////////////////////////////////////////////////////////////////
parameter integer C_SYNCH_WIDTH = 0
)
(
///////////////////////////////////////////////////////////////////////////////
// Port Declarations
///////////////////////////////////////////////////////////////////////////////
input wire clk,
input wire [C_SYNCH_WIDTH-1:0] synch_in ,
output wire [C_SYNCH_WIDTH-1:0] synch_out
);
////////////////////////////////////////////////////////////////////////////////
// Local Parameters
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
// Wires/Reg declarations
////////////////////////////////////////////////////////////////////////////////
(* shreg_extract = "no" *)
reg [C_SYNCH_WIDTH-1:0] synch_d1;
(* shreg_extract = "no" *)
reg [C_SYNCH_WIDTH-1:0] synch_d2;
always @(posedge clk) begin
synch_d1 <= synch_in;
end
always @(posedge clk) begin
synch_d2 <= synch_d1;
end
assign synch_out = synch_d2;
endmodule
|
module axi_mcb_w_channel #
(
///////////////////////////////////////////////////////////////////////////////
// Parameter Definitions
///////////////////////////////////////////////////////////////////////////////
// Width of AXI xDATA and MCB xx_data
// Range: 32, 64, 128.
parameter integer C_DATA_WIDTH = 32,
// Width of beat counter, limits max transaction size.
// Range: 1-6 (-> 2-64 beat transactions)
parameter integer C_CNT_WIDTH = 4,
// Pipelines the wr_full signal from mcb by using
// wr_count. Does not add write latency.
parameter integer C_PL_WR_FULL = 1,
// Pipelines the wvalid and wready handshake used for
// counting. May add one cycle of latency.
parameter integer C_PL_WHANDSHAKE = 1,
// Pipelines the intermodule signal w_complete. May add
// 1 cycle of latency.
parameter integer C_PL_W_COMPLETE = 1
)
(
///////////////////////////////////////////////////////////////////////////////
// Port Declarations
///////////////////////////////////////////////////////////////////////////////
input wire clk ,
input wire reset ,
input wire [C_DATA_WIDTH-1:0] wdata,
input wire [C_DATA_WIDTH/8-1:0] wstrb,
input wire wlast,
input wire wvalid,
output wire wready,
output wire wr_en,
output wire [C_DATA_WIDTH/8-1:0] wr_mask,
output wire [C_DATA_WIDTH-1:0] wr_data,
input wire wr_full,
input wire wr_empty,
input wire [6:0] wr_count,
input wire wr_underrun,
input wire wr_error,
input wire calib_done,
output wire w_complete,
input wire w_trans_cnt_full
);
////////////////////////////////////////////////////////////////////////////////
// Local parameters
////////////////////////////////////////////////////////////////////////////////
localparam integer P_MCB_FULL_CNT = 64;
////////////////////////////////////////////////////////////////////////////////
// Wire and register declarations
////////////////////////////////////////////////////////////////////////////////
wire whandshake;
reg [C_CNT_WIDTH-1:0] cnt;
reg subburst_last;
wire w_complete_ns;
wire w_complete_i;
wire wready_i;
wire wlast_i;
wire whandshake_i;
////////////////////////////////////////////////////////////////////////////////
// BEGIN RTL
////////////////////////////////////////////////////////////////////////////////
assign wready = wready_i;
assign wr_en = whandshake;
assign wr_mask = ~wstrb;
assign wr_data = wdata;
assign whandshake = wvalid & wready;
generate
if (C_PL_WR_FULL) begin : PL_WR_FULL
reg [6:0] wr_count_d1;
wire wr_afull_ns;
reg wready_r;
// Calculate almost full from wr_count instead of using wr_full for timing
// closure
always @(posedge clk) begin
wr_count_d1 <= wr_count;
end
assign wr_afull_ns = (wr_count_d1 > (P_MCB_FULL_CNT-3));
always @(posedge clk) begin
if (reset) begin
wready_r <= 1'b0;
end else begin
wready_r <= ~wr_afull_ns & calib_done & ~w_trans_cnt_full;
end
end
assign wready_i = wready_r;
end
else
begin : NO_PL_WR_FULL
assign wready_i = ~wr_full & calib_done & ~w_trans_cnt_full;
end
endgenerate
generate
if (C_PL_WHANDSHAKE) begin : PL_WHANDSHAKE
reg wlast_d1;
reg whandshake_d1;
// Count the number of beats we have
// Use delayed values of the incoming signals for better timing
always @(posedge clk) begin
wlast_d1 <= wlast;
whandshake_d1 <= whandshake;
end
assign wlast_i = wlast_d1;
assign whandshake_i = whandshake_d1;
end
else begin : NO_PL_WHANDSHAKE
assign wlast_i = wlast;
assign whandshake_i = whandshake;
end
endgenerate
always @(posedge clk) begin
if (w_complete_ns | reset) begin
cnt <= {C_CNT_WIDTH{1'b1}};
end else if (whandshake_i) begin
cnt <= cnt - 1'b1;
end
end
// Determines have reached a subburst boundary
always @(posedge clk) begin
if (reset | w_complete_ns) begin
subburst_last <= 1'b0;
end else if ((cnt == {{C_CNT_WIDTH-1{1'b0}},1'b1}) & whandshake_i) begin
subburst_last <= 1'b1;
end
end
assign w_complete_ns = whandshake_i & (wlast_i | subburst_last);
generate
if (C_PL_W_COMPLETE) begin : PL_W_COMPLETE
reg w_complete_r;
// latch the output of w_complete
always @(posedge clk) begin
w_complete_r <= w_complete_ns;
end
assign w_complete_i = w_complete_r;
end
else begin : NO_PL_W_COMPLETE
assign w_complete_i = w_complete_ns;
end
endgenerate
assign w_complete = w_complete_i;
endmodule
|
module axi_mcb_aw_channel #
(
///////////////////////////////////////////////////////////////////////////////
// Parameter Definitions
///////////////////////////////////////////////////////////////////////////////
// Width of ID signals.
// Range: >= 1.
parameter integer C_ID_WIDTH = 4,
// Width of AxADDR
// Range: 32.
parameter integer C_AXI_ADDR_WIDTH = 32,
// Width of cmd_byte_addr
// Range: 30
parameter integer C_MCB_ADDR_WIDTH = 30,
// Width of AXI xDATA and MCB xx_data
// Range: 32, 64, 128.
parameter integer C_DATA_WIDTH = 32,
// Width of beat counter, limits max transaction size.
// Range: 4
parameter integer C_CNT_WIDTH = 4,
// Static value of axsize
// Range: 2-4
parameter integer C_AXSIZE = 2,
// Enforces strict checking across all MCB ports for
// write data coherency. This will ensure no race
// conditions will exist between the BRESP and any
// other read/write command on a different MCB port.
// Not necessary for single port MCB operation.
// Range: 0, 1 (not implemented 12/1/2009)
parameter integer C_STRICT_COHERENCY = 0,
// Instructs the memory controller to issue an
// auto-precharge after each command.
// Range: 0,1
parameter integer C_ENABLE_AP = 0,
// Register CMD_BL_SECOND for better timing. Does not add
// any latency.
parameter integer C_PL_CMD_BL_SECOND = 1
)
(
///////////////////////////////////////////////////////////////////////////////
// Port Declarations
///////////////////////////////////////////////////////////////////////////////
// AXI Slave Interface
// Slave Interface System Signals
input wire clk ,
input wire reset ,
// Slave Interface Write Address Ports
input wire [C_ID_WIDTH-1:0] awid ,
input wire [C_AXI_ADDR_WIDTH-1:0] awaddr ,
input wire [7:0] awlen ,
input wire [2:0] awsize ,
input wire [1:0] awburst ,
input wire [1:0] awlock ,
input wire [3:0] awcache ,
input wire [2:0] awprot ,
input wire [3:0] awqos ,
input wire awvalid ,
output wire awready ,
// MCB Master Interface
//CMD PORT
output wire cmd_en ,
output wire [2:0] cmd_instr ,
output wire wrap_cmd_sel ,
output wire [5:0] wrap_cmd_bl ,
output wire [C_MCB_ADDR_WIDTH-1:0] wrap_cmd_byte_addr ,
output wire [5:0] incr_cmd_bl ,
output wire [C_MCB_ADDR_WIDTH-1:0] incr_cmd_byte_addr ,
input wire cmd_empty ,
input wire cmd_full ,
input wire calib_done ,
output wire next_pending ,
// Connections to/from axi_mcb_w_channel module
input wire w_complete ,
output wire w_trans_cnt_full ,
// Connections to/from axi_mcb_b_channel module
output wire b_push ,
output wire [C_ID_WIDTH-1:0] b_awid ,
input wire b_full
);
////////////////////////////////////////////////////////////////////////////////
// Local parameters
////////////////////////////////////////////////////////////////////////////////
// MCB Commands
localparam P_CMD_WRITE = 3'b000;
localparam P_CMD_READ = 3'b001;
localparam P_CMD_WRITE_AUTO_PRECHARGE = 3'b010;
localparam P_CMD_READ_AUTO_PRECHARGE = 3'b011;
localparam P_CMD_REFRESH = 3'b100;
// AXI Burst Types
localparam P_AXBURST_FIXED = 2'b00;
localparam P_AXBURST_INCR = 2'b01;
localparam P_AXBURST_WRAP = 2'b10;
// Transaction counter depth
localparam P_TRANS_CNT_WIDTH = 3;
localparam P_TRANS_CNT_FULL = (1<<P_TRANS_CNT_WIDTH)-5;
////////////////////////////////////////////////////////////////////////////////
// Wires/Reg declarations
////////////////////////////////////////////////////////////////////////////////
wire [C_ID_WIDTH-1:0] awid_i ;
wire [C_AXI_ADDR_WIDTH-1:0] awaddr_i ;
wire [7:0] awlen_i ;
wire [2:0] awsize_i ;
wire [1:0] awburst_i ;
wire [1:0] awlock_i ;
wire [3:0] awcache_i ;
wire [2:0] awprot_i ;
wire [3:0] awqos_i ;
wire awvalid_i ;
wire awready_i ;
wire next_cmd ;
wire next_cnt ;
reg [P_TRANS_CNT_WIDTH-1:0] w_trans_cnt ;
wire w_trans_cnt_full_ns ;
reg w_trans_cnt_full_r ;
wire wdata_complete ;
////////////////////////////////////////////////////////////////////////////////
// BEGIN RTL
////////////////////////////////////////////////////////////////////////////////
assign awid_i = awid ;
assign awaddr_i = awaddr ;
assign awlen_i = awlen ;
assign awsize_i = awsize ;
assign awburst_i = awburst ;
assign awlock_i = awlock ;
assign awcache_i = awcache ;
assign awprot_i = awprot ;
assign awqos_i = awqos ;
assign awvalid_i = awvalid ;
assign awready = awready_i ;
// Translate the AXI transaction to the MCB transaction(s)
axi_mcb_cmd_translator #
(
.C_AXI_ADDR_WIDTH ( C_AXI_ADDR_WIDTH ) ,
.C_MCB_ADDR_WIDTH ( C_MCB_ADDR_WIDTH ) ,
.C_DATA_WIDTH ( C_DATA_WIDTH ) ,
.C_CNT_WIDTH ( C_CNT_WIDTH ) ,
.C_AXSIZE ( C_AXSIZE ) ,
.C_PL_CMD_BL_SECOND ( C_PL_CMD_BL_SECOND )
)
axi_mcb_cmd_translator_0
(
.clk ( clk ) ,
.reset ( reset ) ,
.axaddr ( awaddr_i ) ,
.axlen ( awlen_i ) ,
.axsize ( awsize_i ) ,
.axburst ( awburst_i ) ,
.axhandshake ( awvalid_i & awready_i ) ,
.wrap_cmd_sel ( wrap_cmd_sel ) ,
.wrap_cmd_bl ( wrap_cmd_bl ) ,
.wrap_cmd_byte_addr ( wrap_cmd_byte_addr ) ,
.incr_cmd_bl ( incr_cmd_bl ) ,
.incr_cmd_byte_addr ( incr_cmd_byte_addr ) ,
.next_cmd ( next_cmd ) ,
.next_pending ( next_pending )
);
axi_mcb_cmd_fsm aw_axi_mcb_cmd_fsm_0
(
.clk ( clk ) ,
.reset ( reset ) ,
.axready ( awready_i ) ,
.axvalid ( awvalid_i ) ,
.cmd_en ( cmd_en ) ,
.cmd_full ( cmd_full ) ,
.calib_done ( calib_done ) ,
.next_cmd ( next_cmd ) ,
.next_pending ( next_pending ) ,
.data_ready ( wdata_complete ) ,
.b_push ( b_push ) ,
.b_full ( b_full ) ,
.r_push ( )
);
assign cmd_instr = C_ENABLE_AP ? P_CMD_WRITE_AUTO_PRECHARGE : P_CMD_WRITE;
assign b_awid = awid_i;
// Count of the number of write data transactions sent to MCB. This would
// either be when 16 beats of write data are pushed into MCB or when a wlast
// is asserted.
always @(posedge clk) begin
if (reset) begin
w_trans_cnt <= {P_TRANS_CNT_WIDTH{1'b0}};
end else if (w_complete & ~next_cnt) begin
w_trans_cnt <= w_trans_cnt + 1'b1;
end else if (~w_complete & next_cnt) begin
w_trans_cnt <= w_trans_cnt - 1'b1;
end
end
always @(posedge clk) begin
if (reset) begin
w_trans_cnt_full_r <= 1'b0;
end else if (w_complete & ~next_cnt & (w_trans_cnt >= P_TRANS_CNT_FULL)) begin
w_trans_cnt_full_r <= 1'b1;
end else if (~w_complete & next_cnt & (w_trans_cnt < P_TRANS_CNT_FULL)) begin
w_trans_cnt_full_r <= 1'b0;
end
end
assign w_trans_cnt_full = w_trans_cnt_full_r;
/*assign w_trans_cnt_full_ns = w_trans_cnt > ((1<<P_TRANS_CNT_WIDTH)-4);*/
/*always @(posedge clk) begin*/
/* w_trans_cnt_full_r <= w_trans_cnt_full_ns;*/
/*end*/
assign wdata_complete = (w_trans_cnt > 0) | w_complete;
assign next_cnt = (cmd_en & ~cmd_full) & ~(wrap_cmd_sel & next_pending);
endmodule
|
module axi_mcb_simple_fifo #
(
parameter C_WIDTH = 8,
parameter C_AWIDTH = 4,
parameter C_DEPTH = 16
)
(
input wire clk, // Main System Clock (Sync FIFO)
input wire rst, // FIFO Counter Reset (Clk
input wire wr_en, // FIFO Write Enable (Clk)
input wire rd_en, // FIFO Read Enable (Clk)
input wire [C_WIDTH-1:0] din, // FIFO Data Input (Clk)
output wire [C_WIDTH-1:0] dout, // FIFO Data Output (Clk)
output wire a_full,
output wire full, // FIFO FULL Status (Clk)
output wire a_empty,
output wire empty // FIFO EMPTY Status (Clk)
);
///////////////////////////////////////
// FIFO Local Parameters
///////////////////////////////////////
localparam [C_AWIDTH-1:0] C_EMPTY = ~(0);
localparam [C_AWIDTH-1:0] C_EMPTY_PRE = (0);
localparam [C_AWIDTH-1:0] C_FULL = C_EMPTY - 1'b1;
localparam [C_AWIDTH-1:0] C_FULL_PRE = C_FULL - 1'b1;
///////////////////////////////////////
// FIFO Internal Signals
///////////////////////////////////////
reg [C_WIDTH-1:0] memory [C_DEPTH-1:0];
reg [C_AWIDTH-1:0] cnt_read;
reg full_r;
reg empty_r;
///////////////////////////////////////
// Main simple FIFO Array
///////////////////////////////////////
always @(posedge clk) begin : BLKSRL
integer i;
if (wr_en) begin
for (i = 0; i < C_DEPTH-1; i = i + 1) begin
memory[i+1] <= memory[i];
end
memory[0] <= din;
end
end
///////////////////////////////////////
// Read Index Counter
// Up/Down Counter
// *** Notice that there is no ***
// *** OVERRUN protection. ***
///////////////////////////////////////
always @(posedge clk) begin
if (rst) cnt_read <= C_EMPTY;
else if ( wr_en & !rd_en) cnt_read <= cnt_read + 1'b1;
else if (!wr_en & rd_en) cnt_read <= cnt_read - 1'b1;
end
///////////////////////////////////////
// Status Flags / Outputs
///////////////////////////////////////
always @(posedge clk) begin
if (rst) begin
full_r <= 1'b0;
end
else if ( wr_en & ~rd_en) begin
full_r <= a_full;
end
else if ( ~wr_en & rd_en ) begin
full_r <= 1'b0;
end
end
always @(posedge clk) begin
if (rst) begin
empty_r <= 1'b1;
end
else if (~wr_en & rd_en) begin
empty_r <= a_empty;
end
else if (wr_en & ~rd_en) begin
empty_r <= 1'b0;
end
end
assign full = full_r;
assign empty = empty_r;
assign a_full = (cnt_read == C_FULL);
assign a_empty = (cnt_read == C_EMPTY_PRE);
assign dout = (C_DEPTH == 1) ? memory[0] : memory[cnt_read];
endmodule // axi_mcb_simple_fifo
|
module axi_mcb_ar_channel #
(
///////////////////////////////////////////////////////////////////////////////
// Parameter Definitions
///////////////////////////////////////////////////////////////////////////////
// Width of ID signals.
// Range: >= 1.
parameter integer C_ID_WIDTH = 4,
// Width of AxADDR
// Range: 32.
parameter integer C_AXI_ADDR_WIDTH = 32,
// Width of cmd_byte_addr
// Range: 30
parameter integer C_MCB_ADDR_WIDTH = 30,
// Width of AXI xDATA and MCB xx_data
// Range: 32, 64, 128.
parameter integer C_DATA_WIDTH = 32,
// Width of beat counter, limits max transaction size.
// Range: 4
parameter integer C_CNT_WIDTH = 4,
// Static value of axsize
// Rannge: 2-4
parameter integer C_AXSIZE = 2,
// Instructs the memory controller to issue an
// auto-precharge after each command.
// Range: 0,1
parameter integer C_ENABLE_AP = 0,
// Register CMD_BL_SECOND for better timing. Does not add
// any latency.
parameter integer C_PL_CMD_BL_SECOND = 1
)
(
///////////////////////////////////////////////////////////////////////////////
// Port Declarations
///////////////////////////////////////////////////////////////////////////////
// AXI Slave Interface
// Slave Interface System Signals
input wire clk ,
input wire reset ,
// Slave Interface Read Address Ports
input wire [C_ID_WIDTH-1:0] arid ,
input wire [C_AXI_ADDR_WIDTH-1:0] araddr ,
input wire [7:0] arlen ,
input wire [2:0] arsize ,
input wire [1:0] arburst ,
input wire [1:0] arlock ,
input wire [3:0] arcache ,
input wire [2:0] arprot ,
input wire [3:0] arqos ,
input wire arvalid ,
output wire arready ,
// MCB Master Interface
//CMD PORT
output wire cmd_en ,
output wire [2:0] cmd_instr ,
output wire wrap_cmd_sel ,
output wire [5:0] wrap_cmd_bl ,
output wire [C_MCB_ADDR_WIDTH-1:0] wrap_cmd_byte_addr ,
output wire [5:0] incr_cmd_bl ,
output wire [C_MCB_ADDR_WIDTH-1:0] incr_cmd_byte_addr ,
input wire cmd_empty ,
input wire cmd_full ,
input wire calib_done ,
output wire next_pending ,
// Connections to/from axi_mcb_r_channel module
output wire r_push ,
output wire [C_CNT_WIDTH-1:0] r_length ,
output wire [C_ID_WIDTH-1:0] r_arid ,
output wire r_rlast ,
input wire r_full
);
////////////////////////////////////////////////////////////////////////////////
// Local parameters
////////////////////////////////////////////////////////////////////////////////
localparam integer C_REG_SLICE_DEPTH = 0;
localparam P_CMD_WRITE = 3'b000;
localparam P_CMD_READ = 3'b001;
localparam P_CMD_WRITE_AUTO_PRECHARGE = 3'b010;
localparam P_CMD_READ_AUTO_PRECHARGE = 3'b011;
localparam P_CMD_REFRESH = 3'b100;
////////////////////////////////////////////////////////////////////////////////
// Wires/Reg declarations
////////////////////////////////////////////////////////////////////////////////
wire [C_ID_WIDTH-1:0] arid_i ;
wire [C_AXI_ADDR_WIDTH-1:0] araddr_i ;
wire [7:0] arlen_i ;
wire [2:0] arsize_i ;
wire [1:0] arburst_i ;
wire [1:0] arlock_i ;
wire [3:0] arcache_i ;
wire [2:0] arprot_i ;
wire [3:0] arqos_i ;
wire arvalid_i ;
wire arready_i ;
wire next_cmd ;
////////////////////////////////////////////////////////////////////////////////
// BEGIN RTL
////////////////////////////////////////////////////////////////////////////////
assign arid_i = arid ;
assign araddr_i = araddr ;
assign arlen_i = arlen ;
assign arsize_i = arsize ;
assign arburst_i = arburst ;
assign arlock_i = arlock ;
assign arcache_i = arcache ;
assign arprot_i = arprot ;
assign arqos_i = arqos ;
assign arvalid_i = arvalid ;
assign arready = arready_i ;
// Translate the AXI transaction to the MCB transaction(s)
axi_mcb_cmd_translator #
(
.C_AXI_ADDR_WIDTH ( C_AXI_ADDR_WIDTH ) ,
.C_MCB_ADDR_WIDTH ( C_MCB_ADDR_WIDTH ) ,
.C_DATA_WIDTH ( C_DATA_WIDTH ) ,
.C_CNT_WIDTH ( C_CNT_WIDTH ) ,
.C_AXSIZE ( C_AXSIZE ) ,
.C_PL_CMD_BL_SECOND ( C_PL_CMD_BL_SECOND )
)
axi_mcb_cmd_translator_0
(
.clk ( clk ) ,
.reset ( reset ) ,
.axaddr ( araddr_i ) ,
.axlen ( arlen_i ) ,
.axsize ( arsize_i ) ,
.axburst ( arburst_i ) ,
.axhandshake ( arvalid_i & arready_i ) ,
.wrap_cmd_sel ( wrap_cmd_sel ) ,
.wrap_cmd_bl ( wrap_cmd_bl ) ,
.wrap_cmd_byte_addr ( wrap_cmd_byte_addr ) ,
.incr_cmd_bl ( incr_cmd_bl ) ,
.incr_cmd_byte_addr ( incr_cmd_byte_addr ) ,
.next_cmd ( next_cmd ) ,
.next_pending ( next_pending )
);
axi_mcb_cmd_fsm ar_axi_mcb_cmd_fsm_0
(
.clk ( clk ) ,
.reset ( reset ) ,
.axready ( arready_i ) ,
.axvalid ( arvalid_i ) ,
.cmd_en ( cmd_en ) ,
.cmd_full ( cmd_full ) ,
.calib_done ( calib_done ) ,
.next_cmd ( next_cmd ) ,
.next_pending ( next_pending ) ,
.data_ready ( ~r_full ) ,
.b_push ( ) ,
.b_full ( 1'b0 ) ,
.r_push ( r_push )
);
assign cmd_instr = C_ENABLE_AP ? P_CMD_READ_AUTO_PRECHARGE : P_CMD_READ;
assign r_length = wrap_cmd_sel ? wrap_cmd_bl[0 +: C_CNT_WIDTH] : incr_cmd_bl[0 +: C_CNT_WIDTH];
assign r_arid = arid_i;
assign r_rlast = ~next_pending;
endmodule
|
module command_fifo #
(
parameter C_FAMILY = "virtex6",
parameter integer C_ENABLE_S_VALID_CARRY = 0,
parameter integer C_ENABLE_REGISTERED_OUTPUT = 0,
parameter integer C_FIFO_DEPTH_LOG = 5, // FIFO depth = 2**C_FIFO_DEPTH_LOG
// Range = [4:5].
parameter integer C_FIFO_WIDTH = 64 // Width of payload [1:512]
)
(
// Global inputs
input wire ACLK, // Clock
input wire ARESET, // Reset
// Information
output wire EMPTY, // FIFO empty (all stages)
// Slave Port
input wire [C_FIFO_WIDTH-1:0] S_MESG, // Payload (may be any set of channel signals)
input wire S_VALID, // FIFO push
output wire S_READY, // FIFO not full
// Master Port
output wire [C_FIFO_WIDTH-1:0] M_MESG, // Payload
output wire M_VALID, // FIFO not empty
input wire M_READY // FIFO pop
);
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
/////////////////////////////////////////////////////////////////////////////
// Generate variable for data vector.
genvar addr_cnt;
genvar bit_cnt;
integer index;
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
wire [C_FIFO_DEPTH_LOG-1:0] addr;
wire buffer_Full;
wire buffer_Empty;
wire next_Data_Exists;
reg data_Exists_I;
wire valid_Write;
wire new_write;
wire [C_FIFO_DEPTH_LOG-1:0] hsum_A;
wire [C_FIFO_DEPTH_LOG-1:0] sum_A;
wire [C_FIFO_DEPTH_LOG-1:0] addr_cy;
wire buffer_full_early;
wire [C_FIFO_WIDTH-1:0] M_MESG_I; // Payload
wire M_VALID_I; // FIFO not empty
wire M_READY_I; // FIFO pop
/////////////////////////////////////////////////////////////////////////////
// Create Flags
/////////////////////////////////////////////////////////////////////////////
assign buffer_full_early = ( (addr == {{C_FIFO_DEPTH_LOG-1{1'b1}}, 1'b0}) & valid_Write & ~M_READY_I ) |
( buffer_Full & ~M_READY_I );
assign S_READY = ~buffer_Full;
assign buffer_Empty = (addr == {C_FIFO_DEPTH_LOG{1'b0}});
assign next_Data_Exists = (data_Exists_I & ~buffer_Empty) |
(buffer_Empty & S_VALID) |
(data_Exists_I & ~(M_READY_I & data_Exists_I));
always @ (posedge ACLK) begin
if (ARESET) begin
data_Exists_I <= 1'b0;
end else begin
data_Exists_I <= next_Data_Exists;
end
end
assign M_VALID_I = data_Exists_I;
// Select RTL or FPGA optimized instatiations for critical parts.
generate
if ( C_FAMILY == "rtl" || C_ENABLE_S_VALID_CARRY == 0 ) begin : USE_RTL_VALID_WRITE
reg buffer_Full_q;
assign valid_Write = S_VALID & ~buffer_Full;
assign new_write = (S_VALID | ~buffer_Empty);
assign addr_cy[0] = valid_Write;
always @ (posedge ACLK) begin
if (ARESET) begin
buffer_Full_q <= 1'b0;
end else if ( data_Exists_I ) begin
buffer_Full_q <= buffer_full_early;
end
end
assign buffer_Full = buffer_Full_q;
end else begin : USE_FPGA_VALID_WRITE
wire s_valid_dummy1;
wire s_valid_dummy2;
wire sel_s_valid;
wire sel_new_write;
wire valid_Write_dummy1;
wire valid_Write_dummy2;
assign sel_s_valid = ~buffer_Full;
carry_and #
(
.C_FAMILY(C_FAMILY)
) s_valid_dummy_inst1
(
.CIN(S_VALID),
.S(1'b1),
.COUT(s_valid_dummy1)
);
carry_and #
(
.C_FAMILY(C_FAMILY)
) s_valid_dummy_inst2
(
.CIN(s_valid_dummy1),
.S(1'b1),
.COUT(s_valid_dummy2)
);
carry_and #
(
.C_FAMILY(C_FAMILY)
) valid_write_inst
(
.CIN(s_valid_dummy2),
.S(sel_s_valid),
.COUT(valid_Write)
);
assign sel_new_write = ~buffer_Empty;
carry_latch_or #
(
.C_FAMILY(C_FAMILY)
) new_write_inst
(
.CIN(valid_Write),
.I(sel_new_write),
.O(new_write)
);
carry_and #
(
.C_FAMILY(C_FAMILY)
) valid_write_dummy_inst1
(
.CIN(valid_Write),
.S(1'b1),
.COUT(valid_Write_dummy1)
);
carry_and #
(
.C_FAMILY(C_FAMILY)
) valid_write_dummy_inst2
(
.CIN(valid_Write_dummy1),
.S(1'b1),
.COUT(valid_Write_dummy2)
);
carry_and #
(
.C_FAMILY(C_FAMILY)
) valid_write_dummy_inst3
(
.CIN(valid_Write_dummy2),
.S(1'b1),
.COUT(addr_cy[0])
);
FDRE #(
.INIT(1'b0) // Initial value of register (1'b0 or 1'b1)
) FDRE_I1 (
.Q(buffer_Full), // Data output
.C(ACLK), // Clock input
.CE(data_Exists_I), // Clock enable input
.R(ARESET), // Synchronous reset input
.D(buffer_full_early) // Data input
);
end
endgenerate
/////////////////////////////////////////////////////////////////////////////
// Create address pointer
/////////////////////////////////////////////////////////////////////////////
generate
if ( C_FAMILY == "rtl" ) begin : USE_RTL_ADDR
reg [C_FIFO_DEPTH_LOG-1:0] addr_q;
always @ (posedge ACLK) begin
if (ARESET) begin
addr_q <= {C_FIFO_DEPTH_LOG{1'b0}};
end else if ( data_Exists_I ) begin
if ( valid_Write & ~(M_READY_I & data_Exists_I) ) begin
addr_q <= addr_q + 1'b1;
end else if ( ~valid_Write & (M_READY_I & data_Exists_I) & ~buffer_Empty ) begin
addr_q <= addr_q - 1'b1;
end
else begin
addr_q <= addr_q;
end
end
else begin
addr_q <= addr_q;
end
end
assign addr = addr_q;
end else begin : USE_FPGA_ADDR
for (addr_cnt = 0; addr_cnt < C_FIFO_DEPTH_LOG ; addr_cnt = addr_cnt + 1) begin : ADDR_GEN
assign hsum_A[addr_cnt] = ((M_READY_I & data_Exists_I) ^ addr[addr_cnt]) & new_write;
// Don't need the last muxcy, addr_cy(last) is not used anywhere
if ( addr_cnt < C_FIFO_DEPTH_LOG - 1 ) begin : USE_MUXCY
MUXCY MUXCY_inst (
.DI(addr[addr_cnt]),
.CI(addr_cy[addr_cnt]),
.S(hsum_A[addr_cnt]),
.O(addr_cy[addr_cnt+1])
);
end
else begin : NO_MUXCY
end
XORCY XORCY_inst (
.LI(hsum_A[addr_cnt]),
.CI(addr_cy[addr_cnt]),
.O(sum_A[addr_cnt])
);
FDRE #(
.INIT(1'b0) // Initial value of register (1'b0 or 1'b1)
) FDRE_inst (
.Q(addr[addr_cnt]), // Data output
.C(ACLK), // Clock input
.CE(data_Exists_I), // Clock enable input
.R(ARESET), // Synchronous reset input
.D(sum_A[addr_cnt]) // Data input
);
end // end for bit_cnt
end // C_FAMILY
endgenerate
/////////////////////////////////////////////////////////////////////////////
// Data storage
/////////////////////////////////////////////////////////////////////////////
generate
if ( C_FAMILY == "rtl" ) begin : USE_RTL_FIFO
reg [C_FIFO_WIDTH-1:0] data_srl[2 ** C_FIFO_DEPTH_LOG-1:0];
always @ (posedge ACLK) begin
if ( valid_Write ) begin
for (index = 0; index < 2 ** C_FIFO_DEPTH_LOG-1 ; index = index + 1) begin
data_srl[index+1] <= data_srl[index];
end
data_srl[0] <= S_MESG;
end
end
assign M_MESG_I = data_srl[addr];
end else begin : USE_FPGA_FIFO
for (bit_cnt = 0; bit_cnt < C_FIFO_WIDTH ; bit_cnt = bit_cnt + 1) begin : DATA_GEN
if ( C_FIFO_DEPTH_LOG == 5 ) begin : USE_32
SRLC32E # (
.INIT(32'h00000000) // Initial Value of Shift Register
) SRLC32E_inst (
.Q(M_MESG_I[bit_cnt]), // SRL data output
.Q31(), // SRL cascade output pin
.A(addr), // 5-bit shift depth select input
.CE(valid_Write), // Clock enable input
.CLK(ACLK), // Clock input
.D(S_MESG[bit_cnt]) // SRL data input
);
end else begin : USE_16
SRLC16E # (
.INIT(32'h00000000) // Initial Value of Shift Register
) SRLC16E_inst (
.Q(M_MESG_I[bit_cnt]), // SRL data output
.Q15(), // SRL cascade output pin
.A0(addr[0]), // 4-bit shift depth select input 0
.A1(addr[1]), // 4-bit shift depth select input 1
.A2(addr[2]), // 4-bit shift depth select input 2
.A3(addr[3]), // 4-bit shift depth select input 3
.CE(valid_Write), // Clock enable input
.CLK(ACLK), // Clock input
.D(S_MESG[bit_cnt]) // SRL data input
);
end // C_FIFO_DEPTH_LOG
end // end for bit_cnt
end // C_FAMILY
endgenerate
/////////////////////////////////////////////////////////////////////////////
// Pipeline stage
/////////////////////////////////////////////////////////////////////////////
generate
if ( C_ENABLE_REGISTERED_OUTPUT != 0 ) begin : USE_FF_OUT
wire [C_FIFO_WIDTH-1:0] M_MESG_FF; // Payload
wire M_VALID_FF; // FIFO not empty
// Select RTL or FPGA optimized instatiations for critical parts.
if ( C_FAMILY == "rtl" ) begin : USE_RTL_OUTPUT_PIPELINE
reg [C_FIFO_WIDTH-1:0] M_MESG_Q; // Payload
reg M_VALID_Q; // FIFO not empty
always @ (posedge ACLK) begin
if (ARESET) begin
M_MESG_Q <= {C_FIFO_WIDTH{1'b0}};
M_VALID_Q <= 1'b0;
end else begin
if ( M_READY_I ) begin
M_MESG_Q <= M_MESG_I;
M_VALID_Q <= M_VALID_I;
end
end
end
assign M_MESG_FF = M_MESG_Q;
assign M_VALID_FF = M_VALID_Q;
end else begin : USE_FPGA_OUTPUT_PIPELINE
reg [C_FIFO_WIDTH-1:0] M_MESG_CMB; // Payload
reg M_VALID_CMB; // FIFO not empty
always @ *
begin
if ( M_READY_I ) begin
M_MESG_CMB <= M_MESG_I;
M_VALID_CMB <= M_VALID_I;
end else begin
M_MESG_CMB <= M_MESG_FF;
M_VALID_CMB <= M_VALID_FF;
end
end
for (bit_cnt = 0; bit_cnt < C_FIFO_WIDTH ; bit_cnt = bit_cnt + 1) begin : DATA_GEN
FDRE #(
.INIT(1'b0) // Initial value of register (1'b0 or 1'b1)
) FDRE_inst (
.Q(M_MESG_FF[bit_cnt]), // Data output
.C(ACLK), // Clock input
.CE(1'b1), // Clock enable input
.R(ARESET), // Synchronous reset input
.D(M_MESG_CMB[bit_cnt]) // Data input
);
end // end for bit_cnt
FDRE #(
.INIT(1'b0) // Initial value of register (1'b0 or 1'b1)
) FDRE_inst (
.Q(M_VALID_FF), // Data output
.C(ACLK), // Clock input
.CE(1'b1), // Clock enable input
.R(ARESET), // Synchronous reset input
.D(M_VALID_CMB) // Data input
);
end
assign EMPTY = ~M_VALID_I & ~M_VALID_FF;
assign M_MESG = M_MESG_FF;
assign M_VALID = M_VALID_FF;
assign M_READY_I = ( M_READY & M_VALID_FF ) | ~M_VALID_FF;
end else begin : NO_FF_OUT
assign EMPTY = ~M_VALID_I;
assign M_MESG = M_MESG_I;
assign M_VALID = M_VALID_I;
assign M_READY_I = M_READY;
end
endgenerate
endmodule
|
module axi_mcb_wrap_cmd #
(
///////////////////////////////////////////////////////////////////////////////
// Parameter Definitions
///////////////////////////////////////////////////////////////////////////////
// Width of AxADDR
// Range: 32.
parameter integer C_AXI_ADDR_WIDTH = 32,
// Width of cmd_byte_addr
// Range: 30
parameter integer C_MCB_ADDR_WIDTH = 30,
// Width of AXI xDATA and MCB xx_data
// Range: 32, 64, 128.
parameter integer C_DATA_WIDTH = 32,
// Register CMD_BL_SECOND for better timing. Does not add
// any latency.
parameter integer C_PL_CMD_BL_SECOND = 1
)
(
///////////////////////////////////////////////////////////////////////////////
// Port Declarations
///////////////////////////////////////////////////////////////////////////////
input wire clk ,
input wire reset ,
input wire [C_AXI_ADDR_WIDTH-1:0] axaddr ,
input wire [7:0] axlen ,
input wire [2:0] axsize ,
// axhandshake = axvalid & axready
input wire axhandshake ,
output wire [5:0] cmd_bl ,
output wire [C_MCB_ADDR_WIDTH-1:0] cmd_byte_addr ,
// Connections to/from fsm module
// signal to increment to the next mcb transaction
input wire next_cmd ,
// signal to the fsm there is another transaction required
output wire next_pending
);
////////////////////////////////////////////////////////////////////////////////
// Wire and register declarations
////////////////////////////////////////////////////////////////////////////////
reg sel_first;
wire [C_MCB_ADDR_WIDTH-1:0] axaddr_i;
wire [3:0] axlen_i;
wire [C_MCB_ADDR_WIDTH-1:0] wrap_boundary_axaddr;
wire [3:0] axaddr_offset;
wire [3:0] cmd_bl_i;
wire [3:0] cmd_bl_first;
wire [3:0] cmd_bl_second;
wire [3:0] cmd_bl_second_i;
wire [3:0] cmd_bl_second_ns;
wire next_pending_ns;
reg next_pending_r;
////////////////////////////////////////////////////////////////////////////////
// BEGIN RTL
////////////////////////////////////////////////////////////////////////////////
assign cmd_byte_addr = (sel_first) ? axaddr_i : wrap_boundary_axaddr;
assign axaddr_i = axaddr[0 +: C_MCB_ADDR_WIDTH];
assign axlen_i = axlen[3:0];
// Mask bits based on transaction length to get wrap boundary low address
assign wrap_boundary_axaddr = axaddr_i & ~(axlen_i << axsize);
// Offset used to calculate the length of each transaction
assign axaddr_offset = axaddr_i[axsize +: 4] & axlen_i;
// burst length will never exceed 16 beats, add zeros to msb
assign cmd_bl = {2'b0, cmd_bl_i};
assign cmd_bl_i = (sel_first) ? cmd_bl_first : cmd_bl_second;
// Equations for calculating the number of beats.
assign cmd_bl_first = axlen_i & ~axaddr_offset;
assign cmd_bl_second = cmd_bl_second_i;
assign cmd_bl_second_ns = axaddr_offset - 1'b1;
generate
if (C_PL_CMD_BL_SECOND) begin : PL_CMD_BL_SECOND
reg [3:0] cmd_bl_second_r;
always @(posedge clk) begin
cmd_bl_second_r <= cmd_bl_second_ns;
end
assign cmd_bl_second_i = cmd_bl_second_r;
end else begin : NO_PL_CMD_BL_SECOND
assign cmd_bl_second_i = cmd_bl_second_ns;
end
endgenerate
assign next_pending_ns = ((axaddr_offset > 4'b0000) & sel_first) & ~next_cmd;
always @(posedge clk) begin
next_pending_r <= next_pending_ns;
end
// Assign output
assign next_pending = next_pending_r;
// Indicates if we are on the first transaction of a mcb translation with more
// than 1 transaction.
always @(posedge clk) begin
if (reset | axhandshake) begin
sel_first <= 1'b1;
end else if (next_cmd) begin
sel_first <= 1'b0;
end
end
endmodule
|
module axi_register_slice #
(
parameter C_FAMILY = "virtex6",
parameter integer C_AXI_ID_WIDTH = 4,
parameter integer C_AXI_ADDR_WIDTH = 32,
parameter integer C_AXI_DATA_WIDTH = 32,
parameter integer C_AXI_SUPPORTS_USER_SIGNALS = 0,
parameter integer C_AXI_AWUSER_WIDTH = 1,
parameter integer C_AXI_ARUSER_WIDTH = 1,
parameter integer C_AXI_WUSER_WIDTH = 1,
parameter integer C_AXI_RUSER_WIDTH = 1,
parameter integer C_AXI_BUSER_WIDTH = 1,
// C_REG_CONFIG_*:
// 0 => BYPASS = The channel is just wired through the module.
// 1 => FWD_REV = Both FWD and REV (fully-registered)
// 2 => FWD = The master VALID and payload signals are registrated.
// 3 => REV = The slave ready signal is registrated
// 4 => SLAVE_FWD = All slave side signals and master VALID and payload are registrated.
// 5 => SLAVE_RDY = All slave side signals and master READY are registrated.
// 6 => INPUTS = Slave and Master side inputs are registrated.
// 7 => LIGHT_WT = 1-stage pipeline register with bubble cycle, both FWD and REV pipelining
parameter C_REG_CONFIG_AW = 32'h00000000,
parameter C_REG_CONFIG_W = 32'h00000000,
parameter C_REG_CONFIG_B = 32'h00000000,
parameter C_REG_CONFIG_AR = 32'h00000000,
parameter C_REG_CONFIG_R = 32'h00000000
)
(
// System Signals
input wire ACLK,
input wire ARESETN,
// Slave Interface Write Address Ports
input wire [C_AXI_ID_WIDTH-1:0] S_AXI_AWID,
input wire [C_AXI_ADDR_WIDTH-1:0] S_AXI_AWADDR,
input wire [8-1:0] S_AXI_AWLEN,
input wire [3-1:0] S_AXI_AWSIZE,
input wire [2-1:0] S_AXI_AWBURST,
input wire [2-1:0] S_AXI_AWLOCK,
input wire [4-1:0] S_AXI_AWCACHE,
input wire [3-1:0] S_AXI_AWPROT,
input wire [4-1:0] S_AXI_AWREGION,
input wire [4-1:0] S_AXI_AWQOS,
input wire [C_AXI_AWUSER_WIDTH-1:0] S_AXI_AWUSER,
input wire S_AXI_AWVALID,
output wire S_AXI_AWREADY,
// Slave Interface Write Data Ports
input wire [C_AXI_ID_WIDTH-1:0] S_AXI_WID,
input wire [C_AXI_DATA_WIDTH-1:0] S_AXI_WDATA,
input wire [C_AXI_DATA_WIDTH/8-1:0] S_AXI_WSTRB,
input wire S_AXI_WLAST,
input wire [C_AXI_WUSER_WIDTH-1:0] S_AXI_WUSER,
input wire S_AXI_WVALID,
output wire S_AXI_WREADY,
// Slave Interface Write Response Ports
output wire [C_AXI_ID_WIDTH-1:0] S_AXI_BID,
output wire [2-1:0] S_AXI_BRESP,
output wire [C_AXI_BUSER_WIDTH-1:0] S_AXI_BUSER,
output wire S_AXI_BVALID,
input wire S_AXI_BREADY,
// Slave Interface Read Address Ports
input wire [C_AXI_ID_WIDTH-1:0] S_AXI_ARID,
input wire [C_AXI_ADDR_WIDTH-1:0] S_AXI_ARADDR,
input wire [8-1:0] S_AXI_ARLEN,
input wire [3-1:0] S_AXI_ARSIZE,
input wire [2-1:0] S_AXI_ARBURST,
input wire [2-1:0] S_AXI_ARLOCK,
input wire [4-1:0] S_AXI_ARCACHE,
input wire [3-1:0] S_AXI_ARPROT,
input wire [4-1:0] S_AXI_ARREGION,
input wire [4-1:0] S_AXI_ARQOS,
input wire [C_AXI_ARUSER_WIDTH-1:0] S_AXI_ARUSER,
input wire S_AXI_ARVALID,
output wire S_AXI_ARREADY,
// Slave Interface Read Data Ports
output wire [C_AXI_ID_WIDTH-1:0] S_AXI_RID,
output wire [C_AXI_DATA_WIDTH-1:0] S_AXI_RDATA,
output wire [2-1:0] S_AXI_RRESP,
output wire S_AXI_RLAST,
output wire [C_AXI_RUSER_WIDTH-1:0] S_AXI_RUSER,
output wire S_AXI_RVALID,
input wire S_AXI_RREADY,
// Master Interface Write Address Port
output wire [C_AXI_ID_WIDTH-1:0] M_AXI_AWID,
output wire [C_AXI_ADDR_WIDTH-1:0] M_AXI_AWADDR,
output wire [8-1:0] M_AXI_AWLEN,
output wire [3-1:0] M_AXI_AWSIZE,
output wire [2-1:0] M_AXI_AWBURST,
output wire [2-1:0] M_AXI_AWLOCK,
output wire [4-1:0] M_AXI_AWCACHE,
output wire [3-1:0] M_AXI_AWPROT,
output wire [4-1:0] M_AXI_AWREGION,
output wire [4-1:0] M_AXI_AWQOS,
output wire [C_AXI_AWUSER_WIDTH-1:0] M_AXI_AWUSER,
output wire M_AXI_AWVALID,
input wire M_AXI_AWREADY,
// Master Interface Write Data Ports
output wire [C_AXI_ID_WIDTH-1:0] M_AXI_WID,
output wire [C_AXI_DATA_WIDTH-1:0] M_AXI_WDATA,
output wire [C_AXI_DATA_WIDTH/8-1:0] M_AXI_WSTRB,
output wire M_AXI_WLAST,
output wire [C_AXI_WUSER_WIDTH-1:0] M_AXI_WUSER,
output wire M_AXI_WVALID,
input wire M_AXI_WREADY,
// Master Interface Write Response Ports
input wire [C_AXI_ID_WIDTH-1:0] M_AXI_BID,
input wire [2-1:0] M_AXI_BRESP,
input wire [C_AXI_BUSER_WIDTH-1:0] M_AXI_BUSER,
input wire M_AXI_BVALID,
output wire M_AXI_BREADY,
// Master Interface Read Address Port
output wire [C_AXI_ID_WIDTH-1:0] M_AXI_ARID,
output wire [C_AXI_ADDR_WIDTH-1:0] M_AXI_ARADDR,
output wire [8-1:0] M_AXI_ARLEN,
output wire [3-1:0] M_AXI_ARSIZE,
output wire [2-1:0] M_AXI_ARBURST,
output wire [2-1:0] M_AXI_ARLOCK,
output wire [4-1:0] M_AXI_ARCACHE,
output wire [3-1:0] M_AXI_ARPROT,
output wire [4-1:0] M_AXI_ARREGION,
output wire [4-1:0] M_AXI_ARQOS,
output wire [C_AXI_ARUSER_WIDTH-1:0] M_AXI_ARUSER,
output wire M_AXI_ARVALID,
input wire M_AXI_ARREADY,
// Master Interface Read Data Ports
input wire [C_AXI_ID_WIDTH-1:0] M_AXI_RID,
input wire [C_AXI_DATA_WIDTH-1:0] M_AXI_RDATA,
input wire [2-1:0] M_AXI_RRESP,
input wire M_AXI_RLAST,
input wire [C_AXI_RUSER_WIDTH-1:0] M_AXI_RUSER,
input wire M_AXI_RVALID,
output wire M_AXI_RREADY
);
(* shift_extract="no", iob="false", equivalent_register_removal = "no" *) reg reset;
always @(posedge ACLK) begin
reset <= ~ARESETN;
end
// Write Address Port bit positions
localparam C_AWUSER_RIGHT = 0;
localparam C_AWUSER_LEN = C_AXI_SUPPORTS_USER_SIGNALS*C_AXI_AWUSER_WIDTH;
localparam C_AWQOS_RIGHT = C_AWUSER_RIGHT + C_AWUSER_LEN;
localparam C_AWQOS_LEN = 4;
localparam C_AWREGION_RIGHT = C_AWQOS_RIGHT + C_AWQOS_LEN;
localparam C_AWREGION_LEN = 4;
localparam C_AWPROT_RIGHT = C_AWREGION_RIGHT + C_AWREGION_LEN;
localparam C_AWPROT_LEN = 3;
localparam C_AWCACHE_RIGHT = C_AWPROT_RIGHT + C_AWPROT_LEN;
localparam C_AWCACHE_LEN = 4;
localparam C_AWLOCK_RIGHT = C_AWCACHE_RIGHT + C_AWCACHE_LEN;
localparam C_AWLOCK_LEN = 2;
localparam C_AWBURST_RIGHT = C_AWLOCK_RIGHT + C_AWLOCK_LEN;
localparam C_AWBURST_LEN = 2;
localparam C_AWSIZE_RIGHT = C_AWBURST_RIGHT + C_AWBURST_LEN;
localparam C_AWSIZE_LEN = 3;
localparam C_AWLEN_RIGHT = C_AWSIZE_RIGHT + C_AWSIZE_LEN;
localparam C_AWLEN_LEN = 8;
localparam C_AWADDR_RIGHT = C_AWLEN_RIGHT + C_AWLEN_LEN;
localparam C_AWADDR_LEN = C_AXI_ADDR_WIDTH;
localparam C_AWID_RIGHT = C_AWADDR_RIGHT + C_AWADDR_LEN;
localparam C_AWID_LEN = C_AXI_ID_WIDTH;
localparam C_AW_SIZE = C_AWID_RIGHT+C_AWID_LEN;
// Write Address Port FIFO data read and write
wire [C_AW_SIZE-1:0] s_aw_data ;
wire [C_AW_SIZE-1:0] m_aw_data ;
// Write Data Port bit positions
localparam C_WUSER_RIGHT = 0;
localparam C_WUSER_LEN = C_AXI_SUPPORTS_USER_SIGNALS*C_AXI_WUSER_WIDTH;
localparam C_WLAST_RIGHT = C_WUSER_RIGHT + C_WUSER_LEN;
localparam C_WLAST_LEN = 1;
localparam C_WSTRB_RIGHT = C_WLAST_RIGHT + C_WLAST_LEN;
localparam C_WSTRB_LEN = C_AXI_DATA_WIDTH/8;
localparam C_WDATA_RIGHT = C_WSTRB_RIGHT + C_WSTRB_LEN;
localparam C_WDATA_LEN = C_AXI_DATA_WIDTH;
localparam C_WID_RIGHT = C_WDATA_RIGHT + C_WDATA_LEN;
localparam C_WID_LEN = C_AXI_ID_WIDTH;
localparam C_W_SIZE = C_WID_RIGHT+C_WID_LEN;
// Write Data Port FIFO data read and write
wire [C_W_SIZE-1:0] s_w_data;
wire [C_W_SIZE-1:0] m_w_data;
// Write Response Port bit positions
localparam C_BUSER_RIGHT = 0;
localparam C_BUSER_LEN = C_AXI_SUPPORTS_USER_SIGNALS*C_AXI_BUSER_WIDTH;
localparam C_BRESP_RIGHT = C_BUSER_RIGHT + C_BUSER_LEN;
localparam C_BRESP_LEN = 2;
localparam C_BID_RIGHT = C_BRESP_RIGHT + C_BRESP_LEN;
localparam C_BID_LEN = C_AXI_ID_WIDTH;
localparam C_B_SIZE = C_BID_RIGHT+C_BID_LEN;
// Write Response Port FIFO data read and write
wire [C_B_SIZE-1:0] s_b_data;
wire [C_B_SIZE-1:0] m_b_data;
// Read Address Port bit positions
localparam C_ARUSER_RIGHT = 0;
localparam C_ARUSER_LEN = C_AXI_SUPPORTS_USER_SIGNALS*C_AXI_ARUSER_WIDTH;
localparam C_ARQOS_RIGHT = C_ARUSER_RIGHT + C_ARUSER_LEN;
localparam C_ARQOS_LEN = 4;
localparam C_ARREGION_RIGHT = C_ARQOS_RIGHT + C_ARQOS_LEN;
localparam C_ARREGION_LEN = 4;
localparam C_ARPROT_RIGHT = C_ARREGION_RIGHT + C_ARREGION_LEN;
localparam C_ARPROT_LEN = 3;
localparam C_ARCACHE_RIGHT = C_ARPROT_RIGHT + C_ARPROT_LEN;
localparam C_ARCACHE_LEN = 4;
localparam C_ARLOCK_RIGHT = C_ARCACHE_RIGHT + C_ARCACHE_LEN;
localparam C_ARLOCK_LEN = 2;
localparam C_ARBURST_RIGHT = C_ARLOCK_RIGHT + C_ARLOCK_LEN;
localparam C_ARBURST_LEN = 2;
localparam C_ARSIZE_RIGHT = C_ARBURST_RIGHT + C_ARBURST_LEN;
localparam C_ARSIZE_LEN = 3;
localparam C_ARLEN_RIGHT = C_ARSIZE_RIGHT + C_ARSIZE_LEN;
localparam C_ARLEN_LEN = 8;
localparam C_ARADDR_RIGHT = C_ARLEN_RIGHT + C_ARLEN_LEN;
localparam C_ARADDR_LEN = C_AXI_ADDR_WIDTH;
localparam C_ARID_RIGHT = C_ARADDR_RIGHT + C_ARADDR_LEN;
localparam C_ARID_LEN = C_AXI_ID_WIDTH;
localparam C_AR_SIZE = C_ARID_RIGHT+C_ARID_LEN;
// Read Address Port FIFO data read and write
wire [C_AR_SIZE-1:0] s_ar_data;
wire [C_AR_SIZE-1:0] m_ar_data;
// Read Data Ports bit positions
localparam C_RUSER_RIGHT = 0;
localparam C_RUSER_LEN = C_AXI_SUPPORTS_USER_SIGNALS*C_AXI_RUSER_WIDTH;
localparam C_RLAST_RIGHT = C_RUSER_RIGHT + C_RUSER_LEN;
localparam C_RLAST_LEN = 1;
localparam C_RRESP_RIGHT = C_RLAST_RIGHT + C_RLAST_LEN;
localparam C_RRESP_LEN = 2;
localparam C_RDATA_RIGHT = C_RRESP_RIGHT + C_RRESP_LEN;
localparam C_RDATA_LEN = C_AXI_DATA_WIDTH;
localparam C_RID_RIGHT = C_RDATA_RIGHT + C_RDATA_LEN;
localparam C_RID_LEN = C_AXI_ID_WIDTH;
localparam C_R_SIZE = C_RID_RIGHT+C_RID_LEN;
// Read Data Ports FIFO data read and write
wire [C_R_SIZE-1:0] s_r_data;
wire [C_R_SIZE-1:0] m_r_data;
generate
///////////////////////////////////////////////////////
//
// AW PIPE
//
///////////////////////////////////////////////////////
if (C_AXI_SUPPORTS_USER_SIGNALS == 1) begin : gen_async_aw_user
assign s_aw_data = {S_AXI_AWID, S_AXI_AWADDR, S_AXI_AWLEN, S_AXI_AWSIZE,
S_AXI_AWBURST, S_AXI_AWLOCK, S_AXI_AWCACHE, S_AXI_AWPROT,
S_AXI_AWREGION, S_AXI_AWQOS, S_AXI_AWUSER};
assign M_AXI_AWUSER = m_aw_data[C_AWUSER_RIGHT+:C_AWUSER_LEN];
end
else begin : gen_asynch_aw_no_user
assign s_aw_data = {S_AXI_AWID, S_AXI_AWADDR, S_AXI_AWLEN, S_AXI_AWSIZE,
S_AXI_AWBURST, S_AXI_AWLOCK, S_AXI_AWCACHE, S_AXI_AWPROT,
S_AXI_AWREGION, S_AXI_AWQOS};
assign M_AXI_AWUSER = {C_AXI_AWUSER_WIDTH{1'b0}};
end
assign M_AXI_AWID = m_aw_data[C_AWID_RIGHT+:C_AWID_LEN];
assign M_AXI_AWADDR = m_aw_data[C_AWADDR_RIGHT+:C_AWADDR_LEN];
assign M_AXI_AWLEN = m_aw_data[C_AWLEN_RIGHT+:C_AWLEN_LEN];
assign M_AXI_AWSIZE = m_aw_data[C_AWSIZE_RIGHT+:C_AWSIZE_LEN];
assign M_AXI_AWBURST = m_aw_data[C_AWBURST_RIGHT+:C_AWBURST_LEN];
assign M_AXI_AWLOCK = m_aw_data[C_AWLOCK_RIGHT+:C_AWLOCK_LEN];
assign M_AXI_AWCACHE = m_aw_data[C_AWCACHE_RIGHT+:C_AWCACHE_LEN];
assign M_AXI_AWPROT = m_aw_data[C_AWPROT_RIGHT+:C_AWPROT_LEN];
assign M_AXI_AWREGION = m_aw_data[C_AWREGION_RIGHT+:C_AWREGION_LEN];
assign M_AXI_AWQOS = m_aw_data[C_AWQOS_RIGHT+:C_AWQOS_LEN];
axic_register_slice #
(
.C_FAMILY(C_FAMILY),
.C_DATA_WIDTH(C_AW_SIZE),
.C_REG_CONFIG(C_REG_CONFIG_AW)
)
aw_pipe
(
// System Signals
.ACLK(ACLK),
.ARESET(reset),
// Slave side
.S_PAYLOAD_DATA(s_aw_data),
.S_VALID(S_AXI_AWVALID),
.S_READY(S_AXI_AWREADY),
// Master side
.M_PAYLOAD_DATA(m_aw_data),
.M_VALID(M_AXI_AWVALID),
.M_READY(M_AXI_AWREADY)
);
///////////////////////////////////////////////////////
//
// Data Write PIPE
//
///////////////////////////////////////////////////////
if (C_AXI_SUPPORTS_USER_SIGNALS == 1) begin : gen_async_w_user
assign s_w_data = {S_AXI_WID, S_AXI_WDATA, S_AXI_WSTRB, S_AXI_WLAST, S_AXI_WUSER};
assign M_AXI_WUSER = m_w_data[C_WUSER_RIGHT+:C_WUSER_LEN];
end
else begin : gen_asynch_w_no_user
assign s_w_data = {S_AXI_WID, S_AXI_WDATA, S_AXI_WSTRB, S_AXI_WLAST};
assign M_AXI_WUSER = {C_AXI_WUSER_WIDTH{1'b0}};
end
assign M_AXI_WID = m_w_data[C_WID_RIGHT+:C_WID_LEN];
assign M_AXI_WDATA = m_w_data[C_WDATA_RIGHT+:C_WDATA_LEN];
assign M_AXI_WSTRB = m_w_data[C_WSTRB_RIGHT+:C_WSTRB_LEN];
assign M_AXI_WLAST = m_w_data[C_WLAST_RIGHT+:C_WLAST_LEN];
axic_register_slice #
(
.C_FAMILY(C_FAMILY),
.C_DATA_WIDTH(C_W_SIZE),
.C_REG_CONFIG(C_REG_CONFIG_W)
)
w_pipe
(
// System Signals
.ACLK(ACLK),
.ARESET(reset),
// Slave side
.S_PAYLOAD_DATA(s_w_data),
.S_VALID(S_AXI_WVALID),
.S_READY(S_AXI_WREADY),
// Master side
.M_PAYLOAD_DATA(m_w_data),
.M_VALID(M_AXI_WVALID),
.M_READY(M_AXI_WREADY)
);
///////////////////////////////////////////////////////
//
// Write Response PIPE
//
///////////////////////////////////////////////////////
if (C_AXI_SUPPORTS_USER_SIGNALS == 1) begin : gen_async_b_user
assign m_b_data = {M_AXI_BID, M_AXI_BRESP, M_AXI_BUSER};
assign S_AXI_BUSER = s_b_data[C_BUSER_RIGHT+:C_BUSER_LEN];
end
else begin : gen_asynch_b_no_user
assign m_b_data = {M_AXI_BID, M_AXI_BRESP};
assign S_AXI_BUSER = {C_AXI_BUSER_WIDTH{1'b0}};
end
assign S_AXI_BID = s_b_data[C_BID_RIGHT+:C_BID_LEN];
assign S_AXI_BRESP = s_b_data[C_BRESP_RIGHT+:C_BRESP_LEN];
axic_register_slice #
(
.C_FAMILY(C_FAMILY),
.C_DATA_WIDTH(C_B_SIZE),
.C_REG_CONFIG(C_REG_CONFIG_B)
)
b_pipe
(
// System Signals
.ACLK(ACLK),
.ARESET(reset),
// Slave side
.S_PAYLOAD_DATA(m_b_data),
.S_VALID(M_AXI_BVALID),
.S_READY(M_AXI_BREADY),
// Master side
.M_PAYLOAD_DATA(s_b_data),
.M_VALID(S_AXI_BVALID),
.M_READY(S_AXI_BREADY)
);
///////////////////////////////////////////////////////
//
// Address Read PIPE
//
///////////////////////////////////////////////////////
if (C_AXI_SUPPORTS_USER_SIGNALS == 1) begin : gen_async_ar_user
assign s_ar_data = {S_AXI_ARID, S_AXI_ARADDR, S_AXI_ARLEN, S_AXI_ARSIZE,
S_AXI_ARBURST, S_AXI_ARLOCK, S_AXI_ARCACHE, S_AXI_ARPROT,
S_AXI_ARREGION, S_AXI_ARQOS, S_AXI_ARUSER};
assign M_AXI_ARUSER = m_ar_data[C_ARUSER_RIGHT+:C_ARUSER_LEN];
end
else begin : gen_asynch_ar_no_user
assign s_ar_data = {S_AXI_ARID, S_AXI_ARADDR, S_AXI_ARLEN, S_AXI_ARSIZE,
S_AXI_ARBURST, S_AXI_ARLOCK, S_AXI_ARCACHE, S_AXI_ARPROT,
S_AXI_ARREGION, S_AXI_ARQOS};
assign M_AXI_ARUSER = {C_AXI_ARUSER_WIDTH{1'b0}};
end
assign M_AXI_ARID = m_ar_data[C_ARID_RIGHT+:C_ARID_LEN];
assign M_AXI_ARADDR = m_ar_data[C_ARADDR_RIGHT+:C_ARADDR_LEN];
assign M_AXI_ARLEN = m_ar_data[C_ARLEN_RIGHT+:C_ARLEN_LEN];
assign M_AXI_ARSIZE = m_ar_data[C_ARSIZE_RIGHT+:C_ARSIZE_LEN];
assign M_AXI_ARBURST = m_ar_data[C_ARBURST_RIGHT+:C_ARBURST_LEN];
assign M_AXI_ARLOCK = m_ar_data[C_ARLOCK_RIGHT+:C_ARLOCK_LEN];
assign M_AXI_ARCACHE = m_ar_data[C_ARCACHE_RIGHT+:C_ARCACHE_LEN];
assign M_AXI_ARPROT = m_ar_data[C_ARPROT_RIGHT+:C_ARPROT_LEN];
assign M_AXI_ARREGION = m_ar_data[C_ARREGION_RIGHT+:C_ARREGION_LEN];
assign M_AXI_ARQOS = m_ar_data[C_ARQOS_RIGHT+:C_ARQOS_LEN];
axic_register_slice #
(
.C_FAMILY(C_FAMILY),
.C_DATA_WIDTH(C_AR_SIZE),
.C_REG_CONFIG(C_REG_CONFIG_AR)
)
ar_pipe
(
// System Signals
.ACLK(ACLK),
.ARESET(reset),
// Slave side
.S_PAYLOAD_DATA(s_ar_data),
.S_VALID(S_AXI_ARVALID),
.S_READY(S_AXI_ARREADY),
// Master side
.M_PAYLOAD_DATA(m_ar_data),
.M_VALID(M_AXI_ARVALID),
.M_READY(M_AXI_ARREADY)
);
///////////////////////////////////////////////////////
//
// Data Read PIPE
//
///////////////////////////////////////////////////////
if (C_AXI_SUPPORTS_USER_SIGNALS == 1) begin : gen_async_r_user
assign m_r_data = {M_AXI_RID, M_AXI_RDATA, M_AXI_RRESP, M_AXI_RLAST, M_AXI_RUSER};
assign S_AXI_RUSER = s_r_data[C_RUSER_RIGHT+:C_RUSER_LEN];
end
else begin : gen_asynch_r_no_user
assign m_r_data = {M_AXI_RID, M_AXI_RDATA, M_AXI_RRESP, M_AXI_RLAST};
assign S_AXI_RUSER = {C_AXI_RUSER_WIDTH{1'b0}};
end
assign S_AXI_RID = s_r_data[C_RID_RIGHT+:C_RID_LEN];
assign S_AXI_RDATA = s_r_data[C_RDATA_RIGHT+:C_RDATA_LEN];
assign S_AXI_RRESP = s_r_data[C_RRESP_RIGHT+:C_RRESP_LEN];
assign S_AXI_RLAST = s_r_data[C_RLAST_RIGHT+:C_RLAST_LEN];
axic_register_slice #
(
.C_FAMILY(C_FAMILY),
.C_DATA_WIDTH(C_R_SIZE),
.C_REG_CONFIG(C_REG_CONFIG_R)
)
r_pipe
(
// System Signals
.ACLK(ACLK),
.ARESET(reset),
// Slave side
.S_PAYLOAD_DATA(m_r_data),
.S_VALID(M_AXI_RVALID),
.S_READY(M_AXI_RREADY),
// Master side
.M_PAYLOAD_DATA(s_r_data),
.M_VALID(S_AXI_RVALID),
.M_READY(S_AXI_RREADY)
);
endgenerate
endmodule // axi_register_slice
|
module ft245_fifo
(
// Inputs
input clk_i
,input rst_i
,input ftdi_rxf_i
,input ftdi_txe_i
,input [ 7:0] ftdi_data_in_i
,input inport_valid_i
,input [ 7:0] inport_data_i
,input outport_accept_i
// Outputs
,output ftdi_siwua_o
,output ftdi_wrn_o
,output ftdi_rdn_o
,output ftdi_oen_o
,output [ 7:0] ftdi_data_out_o
,output inport_accept_o
,output outport_valid_o
,output [ 7:0] outport_data_o
);
//-----------------------------------------------------------------
// Rx RAM: FTDI -> Target
//-----------------------------------------------------------------
reg [10:0] rx_wr_ptr_q;
wire [10:0] rx_wr_ptr_next_w = rx_wr_ptr_q + 11'd1;
reg [10:0] rx_rd_ptr_q;
wire [10:0] rx_rd_ptr_next_w = rx_rd_ptr_q + 11'd1;
// Retime input data
reg [7:0] rd_data_q;
reg rd_valid_q;
wire rx_valid_w;
always @ (posedge clk_i )
if (rst_i)
rd_valid_q <= 1'b0;
else
rd_valid_q <= rx_valid_w;
always @ (posedge clk_i )
if (rst_i)
rd_data_q <= 8'b0;
else
rd_data_q <= ftdi_data_in_i;
// Write pointer
always @ (posedge clk_i )
if (rst_i)
rx_wr_ptr_q <= 11'b0;
else if (rd_valid_q)
rx_wr_ptr_q <= rx_wr_ptr_next_w;
wire [7:0] rx_data_w;
ft245_ram_dp
u_rx_ram
(
.clk0_i(clk_i)
,.rst0_i(rst_i)
,.clk1_i(clk_i)
,.rst1_i(rst_i)
// Write Port
,.wr0_i(rd_valid_q)
,.addr0_i(rx_wr_ptr_q)
,.data0_i(rd_data_q)
,.data0_o()
// Read Port
,.wr1_i(1'b0)
,.addr1_i(rx_rd_ptr_q)
,.data1_i(8'b0)
,.data1_o(rx_data_w)
);
wire [11:0] rx_level_w = (rx_rd_ptr_q <= rx_wr_ptr_q) ? (rx_wr_ptr_q - rx_rd_ptr_q) : (12'd2048 - rx_rd_ptr_q) + rx_wr_ptr_q;
wire rx_space_w = (12'd2048 - rx_level_w) > 12'd1024;
// Delayed write pointer
reg [10:0] rx_wr_ptr2_q;
always @ (posedge clk_i )
if (rst_i)
rx_wr_ptr2_q <= 11'b0;
else
rx_wr_ptr2_q <= rx_wr_ptr_q;
// Read Side
wire read_ok_w = (rx_wr_ptr2_q != rx_rd_ptr_q);
reg rd_q;
always @ (posedge clk_i )
if (rst_i)
rd_q <= 1'b0;
else
rd_q <= read_ok_w;
always @ (posedge clk_i )
if (rst_i)
rx_rd_ptr_q <= 11'b0;
// Read address increment
else if (read_ok_w && ((!outport_valid_o) || (outport_valid_o && outport_accept_i)))
rx_rd_ptr_q <= rx_rd_ptr_next_w;
// Read Skid Buffer
reg rd_skid_q;
reg [7:0] rd_skid_data_q;
always @ (posedge clk_i )
if (rst_i)
begin
rd_skid_q <= 1'b0;
rd_skid_data_q <= 8'b0;
end
else if (outport_valid_o && !outport_accept_i)
begin
rd_skid_q <= 1'b1;
rd_skid_data_q <= outport_data_o;
end
else
begin
rd_skid_q <= 1'b0;
rd_skid_data_q <= 8'b0;
end
assign outport_valid_o = rd_skid_q | rd_q;
assign outport_data_o = rd_skid_q ? rd_skid_data_q : rx_data_w;
//-----------------------------------------------------------------
// Tx RAM: Target -> FTDI
//-----------------------------------------------------------------
reg [10:0] tx_wr_ptr_q;
wire [10:0] tx_wr_ptr_next_w = tx_wr_ptr_q + 11'd1;
reg [10:0] tx_rd_ptr_q;
wire [10:0] tx_rd_ptr_next_w = tx_rd_ptr_q + 11'd1;
wire [10:0] tx_rd_ptr_prev_w = tx_rd_ptr_q - 11'd2;
wire [7:0] tx_data_w;
ft245_ram_dp
u_tx_ram
(
.clk0_i(clk_i)
,.rst0_i(rst_i)
,.clk1_i(clk_i)
,.rst1_i(rst_i)
// Write Port
,.wr0_i(inport_valid_i & inport_accept_o)
,.addr0_i(tx_wr_ptr_q)
,.data0_i(inport_data_i)
,.data0_o()
// Read Port
,.wr1_i(1'b0)
,.addr1_i(tx_rd_ptr_q)
,.data1_i(8'b0)
,.data1_o(tx_data_w)
);
// Write pointer
always @ (posedge clk_i )
if (rst_i)
tx_wr_ptr_q <= 11'b0;
else if (inport_valid_i & inport_accept_o)
tx_wr_ptr_q <= tx_wr_ptr_next_w;
// Delayed write pointer (pesamistic)
reg [10:0] tx_wr_ptr2_q;
always @ (posedge clk_i )
if (rst_i)
tx_wr_ptr2_q <= 11'b0;
else
tx_wr_ptr2_q <= tx_wr_ptr_q;
// Write push timeout
localparam TX_BACKOFF_THRESH = 16'h00FF;
reg [15:0] tx_idle_cycles_q;
always @ (posedge clk_i )
if (rst_i)
tx_idle_cycles_q <= 16'b0;
else if (inport_valid_i)
tx_idle_cycles_q <= 16'b0;
else if (tx_idle_cycles_q != TX_BACKOFF_THRESH)
tx_idle_cycles_q <= tx_idle_cycles_q + 16'd1;
wire tx_timeout_w = (tx_idle_cycles_q == TX_BACKOFF_THRESH);
wire [11:0] tx_level_w = (tx_rd_ptr_q <= tx_wr_ptr2_q) ? (tx_wr_ptr2_q - tx_rd_ptr_q) : (12'd2048 - tx_rd_ptr_q) + tx_wr_ptr2_q;
wire tx_ready_w = (tx_level_w >= (1024 / 4)) || (tx_timeout_w && tx_level_w != 12'd0);
assign inport_accept_o = (tx_level_w < 12'd2000);
reg [11:0] tx_level_q;
always @ (posedge clk_i )
if (rst_i)
tx_level_q <= 12'b0;
else
tx_level_q <= tx_level_w;
//-----------------------------------------------------------------
// Defines / Local params
//-----------------------------------------------------------------
localparam STATE_W = 3;
localparam STATE_IDLE = 3'd0;
localparam STATE_TX_START = 3'd1;
localparam STATE_TX = 3'd2;
localparam STATE_TURNAROUND = 3'd3;
localparam STATE_RX_START = 3'd4;
localparam STATE_RX = 3'd5;
reg [STATE_W-1:0] state_q;
wire rx_ready_w = !ftdi_rxf_i;
wire tx_space_w = !ftdi_txe_i;
assign rx_valid_w = rx_ready_w & (state_q == STATE_RX);
//-----------------------------------------------------------------
// Next State Logic
//-----------------------------------------------------------------
reg [STATE_W-1:0] next_state_r;
reg [2:0] state_count_q;
always @ *
begin
next_state_r = state_q;
case (state_q)
//-----------------------------------------
// STATE_IDLE
//-----------------------------------------
STATE_IDLE :
begin
if (rx_ready_w && rx_space_w)
next_state_r = STATE_RX_START;
else if (tx_space_w && tx_ready_w)
next_state_r = STATE_TX_START;
end
//-----------------------------------------
// STATE_TX_START
//-----------------------------------------
STATE_TX_START :
begin
next_state_r = STATE_TX;
end
//-----------------------------------------
// STATE_TX
//-----------------------------------------
STATE_TX :
begin
if (!tx_space_w || tx_level_q == 12'd0)
next_state_r = STATE_TURNAROUND;
end
//-----------------------------------------
// STATE_TURNAROUND
//-----------------------------------------
STATE_TURNAROUND :
begin
if (state_count_q == 3'b0)
next_state_r = STATE_IDLE;
end
//-----------------------------------------
// STATE_RX_START
//-----------------------------------------
STATE_RX_START :
begin
next_state_r = STATE_RX;
end
//-----------------------------------------
// STATE_RX
//-----------------------------------------
STATE_RX :
begin
if (!rx_ready_w /*|| rx_full_next_w*/)
next_state_r = STATE_TURNAROUND;
end
default:
;
endcase
end
// Update state
always @ (posedge clk_i )
if (rst_i)
state_q <= STATE_IDLE;
else
state_q <= next_state_r;
always @ (posedge clk_i )
if (rst_i)
state_count_q <= 3'b0;
else if (state_q == STATE_TX && next_state_r == STATE_TURNAROUND)
state_count_q <= 3'd7;
else if (state_q == STATE_RX && next_state_r == STATE_TURNAROUND)
state_count_q <= 3'd7;
else if (state_count_q != 3'b0)
state_count_q <= state_count_q - 3'd1;
// Read pointer
always @ (posedge clk_i )
if (rst_i)
tx_rd_ptr_q <= 11'b0;
else if (((state_q == STATE_IDLE && next_state_r == STATE_TX_START) || (state_q == STATE_TX_START) || (state_q == STATE_TX && tx_space_w)) && (tx_rd_ptr_q != tx_wr_ptr2_q) && (tx_level_q != 12'b0))
tx_rd_ptr_q <= tx_rd_ptr_next_w;
else if ((state_q == STATE_TX) && !tx_space_w && tx_level_q == 12'b0)
tx_rd_ptr_q <= tx_rd_ptr_q - 11'd1;
else if ((state_q == STATE_TX) && !tx_space_w)
tx_rd_ptr_q <= tx_rd_ptr_prev_w;
//-----------------------------------------------------------------
// RD/WR/OE
//-----------------------------------------------------------------
// Xilinx placement pragmas:
//synthesis attribute IOB of rdn_q is "TRUE"
//synthesis attribute IOB of wrn_q is "TRUE"
//synthesis attribute IOB of oen_q is "TRUE"
//synthesis attribute IOB of data_q is "TRUE"
reg rdn_q;
reg wrn_q;
reg oen_q;
reg [7:0] data_q;
always @ (posedge clk_i )
if (rst_i)
oen_q <= 1'b1;
else if (state_q == STATE_IDLE && next_state_r == STATE_RX_START)
oen_q <= 1'b0;
else if (state_q == STATE_RX && next_state_r == STATE_TURNAROUND)
oen_q <= 1'b1;
always @ (posedge clk_i )
if (rst_i)
rdn_q <= 1'b1;
else if (state_q == STATE_RX_START && next_state_r == STATE_RX)
rdn_q <= 1'b0;
else if (state_q == STATE_RX && next_state_r == STATE_TURNAROUND)
rdn_q <= 1'b1;
always @ (posedge clk_i )
if (rst_i)
wrn_q <= 1'b1;
else if (state_q == STATE_TX_START && next_state_r == STATE_TX)
wrn_q <= 1'b0;
else if (state_q == STATE_TX && next_state_r == STATE_TURNAROUND)
wrn_q <= 1'b1;
always @ (posedge clk_i )
if (rst_i)
data_q <= 8'b0;
else
data_q <= tx_data_w;
assign ftdi_wrn_o = wrn_q;
assign ftdi_rdn_o = rdn_q;
assign ftdi_oen_o = oen_q;
assign ftdi_data_out_o = data_q;
assign ftdi_siwua_o = 1'b1;
endmodule
|
module ft245_ram_dp
(
// Inputs
input clk0_i
,input rst0_i
,input [ 10:0] addr0_i
,input [ 7:0] data0_i
,input wr0_i
,input clk1_i
,input rst1_i
,input [ 10:0] addr1_i
,input [ 7:0] data1_i
,input wr1_i
// Outputs
,output [ 7:0] data0_o
,output [ 7:0] data1_o
);
//-----------------------------------------------------------------
// Dual Port RAM 2KB
// Mode: Read First
//-----------------------------------------------------------------
/* verilator lint_off MULTIDRIVEN */
reg [7:0] ram [2047:0] /*verilator public*/;
/* verilator lint_on MULTIDRIVEN */
reg [7:0] ram_read0_q;
reg [7:0] ram_read1_q;
// Synchronous write
always @ (posedge clk0_i)
begin
if (wr0_i)
ram[addr0_i][7:0] <= data0_i[7:0];
ram_read0_q <= ram[addr0_i];
end
always @ (posedge clk1_i)
begin
if (wr1_i)
ram[addr1_i][7:0] <= data1_i[7:0];
ram_read1_q <= ram[addr1_i];
end
assign data0_o = ram_read0_q;
assign data1_o = ram_read1_q;
endmodule
|
module ft245_axi_retime
//-----------------------------------------------------------------
// Params
//-----------------------------------------------------------------
#(
parameter AXI4_RETIME_WR_REQ = 1
,parameter AXI4_RETIME_WR_RESP = 1
,parameter AXI4_RETIME_RD_REQ = 1
,parameter AXI4_RETIME_RD_RESP = 1
)
//-----------------------------------------------------------------
// Ports
//-----------------------------------------------------------------
(
// Inputs
input clk_i
,input rst_i
,input inport_awvalid_i
,input [ 31:0] inport_awaddr_i
,input [ 3:0] inport_awid_i
,input [ 7:0] inport_awlen_i
,input [ 1:0] inport_awburst_i
,input inport_wvalid_i
,input [ 31:0] inport_wdata_i
,input [ 3:0] inport_wstrb_i
,input inport_wlast_i
,input inport_bready_i
,input inport_arvalid_i
,input [ 31:0] inport_araddr_i
,input [ 3:0] inport_arid_i
,input [ 7:0] inport_arlen_i
,input [ 1:0] inport_arburst_i
,input inport_rready_i
,input outport_awready_i
,input outport_wready_i
,input outport_bvalid_i
,input [ 1:0] outport_bresp_i
,input [ 3:0] outport_bid_i
,input outport_arready_i
,input outport_rvalid_i
,input [ 31:0] outport_rdata_i
,input [ 1:0] outport_rresp_i
,input [ 3:0] outport_rid_i
,input outport_rlast_i
// Outputs
,output inport_awready_o
,output inport_wready_o
,output inport_bvalid_o
,output [ 1:0] inport_bresp_o
,output [ 3:0] inport_bid_o
,output inport_arready_o
,output inport_rvalid_o
,output [ 31:0] inport_rdata_o
,output [ 1:0] inport_rresp_o
,output [ 3:0] inport_rid_o
,output inport_rlast_o
,output outport_awvalid_o
,output [ 31:0] outport_awaddr_o
,output [ 3:0] outport_awid_o
,output [ 7:0] outport_awlen_o
,output [ 1:0] outport_awburst_o
,output outport_wvalid_o
,output [ 31:0] outport_wdata_o
,output [ 3:0] outport_wstrb_o
,output outport_wlast_o
,output outport_bready_o
,output outport_arvalid_o
,output [ 31:0] outport_araddr_o
,output [ 3:0] outport_arid_o
,output [ 7:0] outport_arlen_o
,output [ 1:0] outport_arburst_o
,output outport_rready_o
);
//-----------------------------------------------------------------
// Write Command Request
//-----------------------------------------------------------------
localparam WRITE_CMD_REQ_W = 32 + 4 + 8 + 2;
generate
if (AXI4_RETIME_WR_REQ)
begin
wire [WRITE_CMD_REQ_W-1:0] write_cmd_req_out_w;
ft245_axi_retime_fifo
#( .WIDTH(WRITE_CMD_REQ_W) )
u_write_cmd_req
(
.clk_i(clk_i),
.rst_i(rst_i),
.push_i(inport_awvalid_i),
.data_in_i({inport_awaddr_i, inport_awid_i, inport_awlen_i, inport_awburst_i}),
.accept_o(inport_awready_o),
.valid_o(outport_awvalid_o),
.data_out_o(write_cmd_req_out_w),
.pop_i(outport_awready_i)
);
assign {outport_awaddr_o, outport_awid_o, outport_awlen_o, outport_awburst_o} = write_cmd_req_out_w;
end
else
begin
assign outport_awvalid_o = inport_awvalid_i;
assign {outport_awaddr_o, outport_awid_o, outport_awlen_o, outport_awburst_o} = {inport_awaddr_i, inport_awid_i, inport_awlen_i, inport_awburst_i};
assign inport_awready_o = outport_awready_i;
end
endgenerate
//-----------------------------------------------------------------
// Write Data Request
//-----------------------------------------------------------------
localparam WRITE_DATA_REQ_W = 32 + 4 + 1;
generate
if (AXI4_RETIME_WR_REQ)
begin
wire [WRITE_DATA_REQ_W-1:0] write_data_req_out_w;
ft245_axi_retime_fifo
#( .WIDTH(WRITE_DATA_REQ_W) )
u_write_data_req
(
.clk_i(clk_i),
.rst_i(rst_i),
.push_i(inport_wvalid_i),
.data_in_i({inport_wlast_i, inport_wstrb_i, inport_wdata_i}),
.accept_o(inport_wready_o),
.valid_o(outport_wvalid_o),
.data_out_o(write_data_req_out_w),
.pop_i(outport_wready_i)
);
assign {outport_wlast_o, outport_wstrb_o, outport_wdata_o} = write_data_req_out_w;
end
else
begin
assign outport_wvalid_o = inport_wvalid_i;
assign {outport_wlast_o, outport_wstrb_o, outport_wdata_o} = {inport_wlast_i, inport_wstrb_i, inport_wdata_i};
assign inport_wready_o = outport_wready_i;
end
endgenerate
//-----------------------------------------------------------------
// Write Response
//-----------------------------------------------------------------
localparam WRITE_RESP_W = 2 + 4;
generate
if (AXI4_RETIME_WR_RESP)
begin
wire [WRITE_RESP_W-1:0] write_resp_out_w;
ft245_axi_retime_fifo
#( .WIDTH(WRITE_RESP_W) )
u_write_resp
(
.clk_i(clk_i),
.rst_i(rst_i),
.push_i(outport_bvalid_i),
.data_in_i({outport_bresp_i, outport_bid_i}),
.accept_o(outport_bready_o),
.valid_o(inport_bvalid_o),
.data_out_o(write_resp_out_w),
.pop_i(inport_bready_i)
);
assign {inport_bresp_o, inport_bid_o} = write_resp_out_w;
end
else
begin
assign inport_bvalid_o = outport_bvalid_i;
assign {inport_bresp_o, inport_bid_o} = {outport_bresp_i, outport_bid_i};
assign outport_bready_o = inport_bready_i;
end
endgenerate
//-----------------------------------------------------------------
// Read Request
//-----------------------------------------------------------------
localparam READ_REQ_W = 32 + 4 + 8 + 2;
generate
if (AXI4_RETIME_RD_REQ)
begin
wire [READ_REQ_W-1:0] read_req_out_w;
ft245_axi_retime_fifo
#( .WIDTH(READ_REQ_W) )
u_read_req
(
.clk_i(clk_i),
.rst_i(rst_i),
.push_i(inport_arvalid_i),
.data_in_i({inport_araddr_i, inport_arid_i, inport_arlen_i, inport_arburst_i}),
.accept_o(inport_arready_o),
.valid_o(outport_arvalid_o),
.data_out_o(read_req_out_w),
.pop_i(outport_arready_i)
);
assign {outport_araddr_o, outport_arid_o, outport_arlen_o, outport_arburst_o} = read_req_out_w;
end
else
begin
assign outport_arvalid_o = inport_arvalid_i;
assign {outport_araddr_o, outport_arid_o, outport_arlen_o, outport_arburst_o} = {inport_araddr_i, inport_arid_i, inport_arlen_i, inport_arburst_i};
assign inport_arready_o = outport_arready_i;
end
endgenerate
//-----------------------------------------------------------------
// Read Response
//-----------------------------------------------------------------
localparam READ_RESP_W = 32 + 2 + 4 + 1;
generate
if (AXI4_RETIME_RD_RESP)
begin
wire [READ_RESP_W-1:0] read_resp_out_w;
ft245_axi_retime_fifo
#( .WIDTH(READ_RESP_W) )
u_read_resp
(
.clk_i(clk_i),
.rst_i(rst_i),
.push_i(outport_rvalid_i),
.data_in_i({outport_rdata_i, outport_rresp_i, outport_rid_i, outport_rlast_i}),
.accept_o(outport_rready_o),
.valid_o(inport_rvalid_o),
.data_out_o(read_resp_out_w),
.pop_i(inport_rready_i)
);
assign {inport_rdata_o, inport_rresp_o, inport_rid_o, inport_rlast_o} = read_resp_out_w;
end
else
begin
assign inport_rvalid_o = outport_rvalid_i;
assign {inport_rdata_o, inport_rresp_o, inport_rid_o, inport_rlast_o} = {outport_rdata_i, outport_rresp_i, outport_rid_i, outport_rlast_i};
assign outport_rready_o = inport_rready_i;
end
endgenerate
endmodule
|
module ft245_axi
//-----------------------------------------------------------------
// Params
//-----------------------------------------------------------------
#(
parameter RETIME_AXI = 1
,parameter AXI_ID = 8
)
//-----------------------------------------------------------------
// Ports
//-----------------------------------------------------------------
(
// Inputs
input clk_i
,input rst_i
,input ftdi_rxf_i
,input ftdi_txe_i
,input [ 7:0] ftdi_data_in_i
,input outport_awready_i
,input outport_wready_i
,input outport_bvalid_i
,input [ 1:0] outport_bresp_i
,input [ 3:0] outport_bid_i
,input outport_arready_i
,input outport_rvalid_i
,input [ 31:0] outport_rdata_i
,input [ 1:0] outport_rresp_i
,input [ 3:0] outport_rid_i
,input outport_rlast_i
// Outputs
,output ftdi_siwua_o
,output ftdi_wrn_o
,output ftdi_rdn_o
,output ftdi_oen_o
,output [ 7:0] ftdi_data_out_o
,output outport_awvalid_o
,output [ 31:0] outport_awaddr_o
,output [ 3:0] outport_awid_o
,output [ 7:0] outport_awlen_o
,output [ 1:0] outport_awburst_o
,output outport_wvalid_o
,output [ 31:0] outport_wdata_o
,output [ 3:0] outport_wstrb_o
,output outport_wlast_o
,output outport_bready_o
,output outport_arvalid_o
,output [ 31:0] outport_araddr_o
,output [ 3:0] outport_arid_o
,output [ 7:0] outport_arlen_o
,output [ 1:0] outport_arburst_o
,output outport_rready_o
,output [ 7:0] gpio_outputs_o
);
//-----------------------------------------------------------------
// AXI interface retiming
//-----------------------------------------------------------------
wire outport_awvalid_w;
wire [ 31:0] outport_awaddr_w;
wire [ 3:0] outport_awid_w;
wire [ 7:0] outport_awlen_w;
wire [ 1:0] outport_awburst_w;
wire outport_wvalid_w;
wire [ 31:0] outport_wdata_w;
wire [ 3:0] outport_wstrb_w;
wire outport_wlast_w;
wire outport_bready_w;
wire outport_arvalid_w;
wire [ 31:0] outport_araddr_w;
wire [ 3:0] outport_arid_w;
wire [ 7:0] outport_arlen_w;
wire [ 1:0] outport_arburst_w;
wire outport_rready_w;
wire outport_awready_w;
wire outport_wready_w;
wire outport_bvalid_w;
wire [ 1:0] outport_bresp_w;
wire [ 3:0] outport_bid_w;
wire outport_arready_w;
wire outport_rvalid_w;
wire [ 31:0] outport_rdata_w;
wire [ 1:0] outport_rresp_w;
wire [ 3:0] outport_rid_w;
wire outport_rlast_w;
generate
if (RETIME_AXI)
begin
ft245_axi_retime
u_retime
(
.clk_i(clk_i)
,.rst_i(rst_i)
,.inport_awvalid_i(outport_awvalid_w)
,.inport_awaddr_i(outport_awaddr_w)
,.inport_awid_i(outport_awid_w)
,.inport_awlen_i(outport_awlen_w)
,.inport_awburst_i(outport_awburst_w)
,.inport_wvalid_i(outport_wvalid_w)
,.inport_wdata_i(outport_wdata_w)
,.inport_wstrb_i(outport_wstrb_w)
,.inport_wlast_i(outport_wlast_w)
,.inport_bready_i(outport_bready_w)
,.inport_arvalid_i(outport_arvalid_w)
,.inport_araddr_i(outport_araddr_w)
,.inport_arid_i(outport_arid_w)
,.inport_arlen_i(outport_arlen_w)
,.inport_arburst_i(outport_arburst_w)
,.inport_rready_i(outport_rready_w)
,.inport_awready_o(outport_awready_w)
,.inport_wready_o(outport_wready_w)
,.inport_bvalid_o(outport_bvalid_w)
,.inport_bresp_o(outport_bresp_w)
,.inport_bid_o(outport_bid_w)
,.inport_arready_o(outport_arready_w)
,.inport_rvalid_o(outport_rvalid_w)
,.inport_rdata_o(outport_rdata_w)
,.inport_rresp_o(outport_rresp_w)
,.inport_rid_o(outport_rid_w)
,.inport_rlast_o(outport_rlast_w)
,.outport_awvalid_o(outport_awvalid_o)
,.outport_awaddr_o(outport_awaddr_o)
,.outport_awid_o(outport_awid_o)
,.outport_awlen_o(outport_awlen_o)
,.outport_awburst_o(outport_awburst_o)
,.outport_wvalid_o(outport_wvalid_o)
,.outport_wdata_o(outport_wdata_o)
,.outport_wstrb_o(outport_wstrb_o)
,.outport_wlast_o(outport_wlast_o)
,.outport_bready_o(outport_bready_o)
,.outport_arvalid_o(outport_arvalid_o)
,.outport_araddr_o(outport_araddr_o)
,.outport_arid_o(outport_arid_o)
,.outport_arlen_o(outport_arlen_o)
,.outport_arburst_o(outport_arburst_o)
,.outport_rready_o(outport_rready_o)
,.outport_awready_i(outport_awready_i)
,.outport_wready_i(outport_wready_i)
,.outport_bvalid_i(outport_bvalid_i)
,.outport_bresp_i(outport_bresp_i)
,.outport_bid_i(outport_bid_i)
,.outport_arready_i(outport_arready_i)
,.outport_rvalid_i(outport_rvalid_i)
,.outport_rdata_i(outport_rdata_i)
,.outport_rresp_i(outport_rresp_i)
,.outport_rid_i(outport_rid_i)
,.outport_rlast_i(outport_rlast_i)
);
end
else
begin
assign outport_arvalid_o = outport_arvalid_w;
assign outport_araddr_o = outport_araddr_w;
assign outport_arid_o = outport_arid_w;
assign outport_arlen_o = outport_arlen_w;
assign outport_arburst_o = outport_arburst_w;
assign outport_awvalid_o = outport_awvalid_w;
assign outport_awaddr_o = outport_awaddr_w;
assign outport_awid_o = outport_awid_w;
assign outport_awlen_o = outport_awlen_w;
assign outport_awburst_o = outport_awburst_w;
assign outport_wvalid_o = outport_wvalid_w;
assign outport_wdata_o = outport_wdata_w;
assign outport_wstrb_o = outport_wstrb_w;
assign outport_wlast_o = outport_wlast_w;
assign outport_rready_o = outport_rready_w;
assign outport_bready_o = outport_bready_w;
assign outport_awready_w = outport_awready_i;
assign outport_wready_w = outport_wready_i;
assign outport_bvalid_w = outport_bvalid_i;
assign outport_bresp_w = outport_bresp_i;
assign outport_bid_w = outport_bid_i;
assign outport_arready_w = outport_arready_i;
assign outport_rvalid_w = outport_rvalid_i;
assign outport_rdata_w = outport_rdata_i;
assign outport_rresp_w = outport_rresp_i;
assign outport_rid_w = outport_rid_i;
assign outport_rlast_w = outport_rlast_i;
end
endgenerate
//-----------------------------------------------------------------
// FTDI <-> Stream
//-----------------------------------------------------------------
wire rx8_valid_w;
wire [ 7:0] rx8_data_w;
wire rx8_accept_w;
wire tx8_valid_w;
wire [ 7:0] tx8_data_w;
wire tx8_accept_w;
ft245_fifo
u_ram
(
.clk_i(clk_i)
,.rst_i(rst_i)
,.ftdi_rxf_i(ftdi_rxf_i)
,.ftdi_txe_i(ftdi_txe_i)
,.ftdi_data_in_i(ftdi_data_in_i)
,.ftdi_wrn_o(ftdi_wrn_o)
,.ftdi_rdn_o(ftdi_rdn_o)
,.ftdi_oen_o(ftdi_oen_o)
,.ftdi_data_out_o(ftdi_data_out_o)
,.ftdi_siwua_o(ftdi_siwua_o)
,.inport_valid_i(tx8_valid_w)
,.inport_data_i(tx8_data_w)
,.inport_accept_o(tx8_accept_w)
,.outport_valid_o(rx8_valid_w)
,.outport_data_o(rx8_data_w)
,.outport_accept_i(rx8_accept_w)
);
wire rx_valid_w;
wire [ 31:0] rx_data_w;
wire rx_accept_w;
ft245_axi_fifo_8_32
u_upconv
(
.clk_i(clk_i)
,.rst_i(rst_i)
,.inport_valid_i(rx8_valid_w)
,.inport_data_i(rx8_data_w)
,.inport_accept_o(rx8_accept_w)
,.outport_valid_o(rx_valid_w)
,.outport_data_o(rx_data_w)
,.outport_accept_i(rx_accept_w)
);
wire tx_valid_w;
wire [ 31:0] tx_data_w;
wire tx_accept_w;
ft245_axi_fifo_32_8
u_downconv
(
.clk_i(clk_i)
,.rst_i(rst_i)
,.inport_valid_i(tx_valid_w)
,.inport_data_i(tx_data_w)
,.inport_accept_o(tx_accept_w)
,.outport_valid_o(tx8_valid_w)
,.outport_data_o(tx8_data_w)
,.outport_accept_i(tx8_accept_w)
);
//-----------------------------------------------------------------
// Defines / Local params
//-----------------------------------------------------------------
localparam STATE_W = 4;
localparam STATE_IDLE = 4'd0;
localparam STATE_CMD_REQ = 4'd1;
localparam STATE_CMD_ADDR = 4'd2;
localparam STATE_ECHO = 4'd3;
localparam STATE_STATUS = 4'd4;
localparam STATE_READ_CMD = 4'd5;
localparam STATE_READ_DATA = 4'd6;
localparam STATE_WRITE_CMD = 4'd7;
localparam STATE_WRITE_DATA = 4'd8;
localparam STATE_WRITE_RESP = 4'd9;
localparam STATE_DRAIN = 4'd10;
localparam STATE_GPIO_WR = 4'd11;
localparam STATE_GPIO_RD = 4'd12;
localparam CMD_ID_ECHO = 8'h01;
localparam CMD_ID_DRAIN = 8'h02;
localparam CMD_ID_READ = 8'h10;
localparam CMD_ID_WRITE8_NP = 8'h20; // 8-bit write (with response)
localparam CMD_ID_WRITE16_NP = 8'h21; // 16-bit write (with response)
localparam CMD_ID_WRITE_NP = 8'h22; // 32-bit write (with response)
localparam CMD_ID_WRITE8 = 8'h30; // 8-bit write
localparam CMD_ID_WRITE16 = 8'h31; // 16-bit write
localparam CMD_ID_WRITE = 8'h32; // 32-bit write
localparam CMD_ID_GPIO_WR = 8'h40;
localparam CMD_ID_GPIO_RD = 8'h41;
reg [STATE_W-1:0] state_q;
reg [7:0] cmd_len_q;
reg [31:0] cmd_addr_q;
reg [15:0] cmd_seq_q;
reg [7:0] cmd_id_q;
reg [7:0] stat_len_q;
reg [1:0] stat_resp_q;
//-----------------------------------------------------------------
// Next State Logic
//-----------------------------------------------------------------
reg [STATE_W-1:0] next_state_r;
always @ *
begin
next_state_r = state_q;
case (state_q)
//-----------------------------------------
// STATE_IDLE
//-----------------------------------------
STATE_IDLE :
begin
if (rx_valid_w)
next_state_r = STATE_CMD_REQ;
end
//-----------------------------------------
// STATE_CMD_REQ
//-----------------------------------------
STATE_CMD_REQ :
begin
if (rx_valid_w) next_state_r = STATE_CMD_ADDR;
end
//-----------------------------------------
// STATE_CMD_ADDR
//-----------------------------------------
STATE_CMD_ADDR :
begin
if (cmd_id_q == CMD_ID_ECHO && cmd_len_q != 8'b0)
next_state_r = STATE_ECHO;
else if (cmd_id_q == CMD_ID_ECHO && cmd_len_q == 8'b0)
next_state_r = STATE_STATUS;
else if (cmd_id_q == CMD_ID_READ)
next_state_r = STATE_READ_CMD;
else if (cmd_id_q == CMD_ID_WRITE8_NP ||
cmd_id_q == CMD_ID_WRITE16_NP ||
cmd_id_q == CMD_ID_WRITE_NP ||
cmd_id_q == CMD_ID_WRITE8 ||
cmd_id_q == CMD_ID_WRITE16 ||
cmd_id_q == CMD_ID_WRITE)
next_state_r = STATE_WRITE_CMD;
else if (cmd_id_q == CMD_ID_DRAIN)
next_state_r = STATE_DRAIN;
else if (cmd_id_q == CMD_ID_GPIO_WR)
next_state_r = STATE_GPIO_WR;
else if (cmd_id_q == CMD_ID_GPIO_RD)
next_state_r = STATE_GPIO_RD;
end
//-----------------------------------------
// STATE_ECHO
//-----------------------------------------
STATE_ECHO :
begin
if ((stat_len_q + 8'd1) == cmd_len_q && tx_accept_w)
next_state_r = STATE_STATUS;
end
//-----------------------------------------
// STATE_READ_CMD
//-----------------------------------------
STATE_READ_CMD :
begin
if (outport_arready_w)
next_state_r = STATE_READ_DATA;
end
//-----------------------------------------
// STATE_READ_DATA
//-----------------------------------------
STATE_READ_DATA :
begin
if (outport_rvalid_w && outport_rready_w && outport_rlast_w)
next_state_r = STATE_STATUS;
end
//-----------------------------------------
// STATE_WRITE_CMD
//-----------------------------------------
STATE_WRITE_CMD :
begin
if (outport_awready_w)
next_state_r = STATE_WRITE_DATA;
end
//-----------------------------------------
// STATE_WRITE_DATA
//-----------------------------------------
STATE_WRITE_DATA :
begin
if (outport_wvalid_w && outport_wlast_w && outport_wready_w)
next_state_r = STATE_WRITE_RESP;
end
//-----------------------------------------
// STATE_WRITE_RESP
//-----------------------------------------
STATE_WRITE_RESP :
begin
if (outport_bvalid_w && outport_bready_w)
begin
if (cmd_id_q == CMD_ID_WRITE8 ||
cmd_id_q == CMD_ID_WRITE16 ||
cmd_id_q == CMD_ID_WRITE)
next_state_r = STATE_IDLE;
else
next_state_r = STATE_STATUS;
end
end
//-----------------------------------------
// STATE_STATUS
//-----------------------------------------
STATE_STATUS :
begin
if (tx_accept_w) next_state_r = STATE_IDLE;
end
//-----------------------------------------
// STATE_DRAIN
//-----------------------------------------
STATE_DRAIN :
begin
if (!rx_valid_w) next_state_r = STATE_IDLE;
end
//-----------------------------------------
// STATE_GPIO_WR
//-----------------------------------------
STATE_GPIO_WR :
begin
if (rx_valid_w) next_state_r = STATE_STATUS;
end
//-----------------------------------------
// STATE_GPIO_RD
//-----------------------------------------
STATE_GPIO_RD :
begin
if (tx_accept_w) next_state_r = STATE_STATUS;
end
default:
;
endcase
end
// Update state
always @ (posedge clk_i )
if (rst_i)
state_q <= STATE_IDLE;
else
state_q <= next_state_r;
//-----------------------------------------------------------------
// Command capture
//-----------------------------------------------------------------
always @ (posedge clk_i )
if (rst_i)
cmd_id_q <= 8'b0;
else if (state_q != STATE_CMD_REQ && next_state_r == STATE_CMD_REQ)
cmd_id_q <= rx_data_w[7:0];
always @ (posedge clk_i )
if (rst_i)
cmd_len_q <= 8'b0;
else if (state_q != STATE_CMD_REQ && next_state_r == STATE_CMD_REQ)
cmd_len_q <= rx_data_w[15:8];
always @ (posedge clk_i )
if (rst_i)
cmd_seq_q <= 16'b0;
else if (state_q != STATE_CMD_REQ && next_state_r == STATE_CMD_REQ)
cmd_seq_q <= rx_data_w[31:16];
always @ (posedge clk_i )
if (rst_i)
cmd_addr_q <= 32'b0;
else if (state_q != STATE_CMD_ADDR && next_state_r == STATE_CMD_ADDR)
cmd_addr_q <= rx_data_w;
//-----------------------------------------------------------------
// Length
//-----------------------------------------------------------------
always @ (posedge clk_i )
if (rst_i)
stat_len_q <= 8'b0;
else if (state_q != STATE_CMD_REQ && next_state_r == STATE_CMD_REQ)
stat_len_q <= 8'b0;
else if (state_q == STATE_ECHO && tx_accept_w)
stat_len_q <= stat_len_q + 8'd1;
else if (state_q == STATE_WRITE_DATA && outport_wvalid_w && outport_wready_w)
stat_len_q <= stat_len_q + 8'd1;
//-----------------------------------------------------------------
// Write Mask
//-----------------------------------------------------------------
reg [3:0] write_strb_q;
always @ (posedge clk_i )
if (rst_i)
write_strb_q <= 4'b0;
else if (state_q != STATE_CMD_ADDR && next_state_r == STATE_CMD_ADDR)
begin
if (cmd_id_q == CMD_ID_WRITE8 || cmd_id_q == CMD_ID_WRITE8_NP)
begin
case (rx_data_w[1:0])
2'b00: write_strb_q <= 4'b0001;
2'b01: write_strb_q <= 4'b0010;
2'b10: write_strb_q <= 4'b0100;
2'b11: write_strb_q <= 4'b1000;
endcase
end
else if (cmd_id_q == CMD_ID_WRITE16 || cmd_id_q == CMD_ID_WRITE16_NP)
begin
case ({rx_data_w[1],1'b0})
2'b00: write_strb_q <= 4'b0011;
2'b10: write_strb_q <= 4'b1100;
default: ;
endcase
end
else
write_strb_q <= 4'b1111;
end
//-----------------------------------------------------------------
// Handshaking
//-----------------------------------------------------------------
reg rx_accept_r;
always @ *
begin
rx_accept_r = 1'b0;
case (state_q)
STATE_IDLE,
STATE_CMD_REQ,
STATE_GPIO_WR,
STATE_DRAIN : rx_accept_r = 1'b1;
STATE_CMD_ADDR : rx_accept_r = 1'b0;
STATE_ECHO: rx_accept_r = tx_accept_w;
STATE_WRITE_DATA: rx_accept_r = outport_wready_w;
default:
;
endcase
end
assign rx_accept_w = rx_accept_r;
reg tx_valid_r;
reg [31:0] tx_data_r;
always @ *
begin
tx_valid_r = 1'b0;
tx_data_r = 32'b0;
case (state_q)
STATE_ECHO:
begin
tx_valid_r = rx_valid_w;
tx_data_r = rx_data_w;
end
STATE_STATUS:
begin
tx_valid_r = 1'b1;
tx_data_r = {14'b0, stat_resp_q, cmd_seq_q};
end
STATE_READ_DATA:
begin
tx_valid_r = outport_rvalid_w;
tx_data_r = outport_rdata_w;
end
STATE_GPIO_RD:
begin
tx_valid_r = 1'b1;
tx_data_r = 32'b0;
end
default:
;
endcase
end
assign tx_valid_w = tx_valid_r;
assign tx_data_w = tx_data_r;
//-----------------------------------------------------------------
// AXI Read
//-----------------------------------------------------------------
assign outport_arvalid_w = (state_q == STATE_READ_CMD);
assign outport_araddr_w = cmd_addr_q;
assign outport_arid_w = AXI_ID;
assign outport_arlen_w = cmd_len_q - 8'd1;
assign outport_arburst_w = 2'b01;
assign outport_rready_w = (state_q == STATE_READ_DATA) && tx_accept_w;
//-----------------------------------------------------------------
// AXI Write
//-----------------------------------------------------------------
assign outport_awvalid_w = (state_q == STATE_WRITE_CMD);
assign outport_awaddr_w = cmd_addr_q;
assign outport_awid_w = AXI_ID;
assign outport_awlen_w = cmd_len_q - 8'd1;
assign outport_awburst_w = 2'b01;
assign outport_wvalid_w = (state_q == STATE_WRITE_DATA) && rx_valid_w;
assign outport_wdata_w = rx_data_w;
assign outport_wstrb_w = write_strb_q;
assign outport_wlast_w = (stat_len_q + 8'd1) == cmd_len_q;
assign outport_bready_w = 1'b1;
//-----------------------------------------------------------------
// AXI Response
//-----------------------------------------------------------------
always @ (posedge clk_i )
if (rst_i)
stat_resp_q <= 2'b0;
else if (state_q == STATE_IDLE)
stat_resp_q <= 2'b0;
else if (outport_bvalid_w && outport_bready_w)
stat_resp_q <= outport_bresp_w;
else if (outport_rvalid_w && outport_rlast_w && outport_rready_w)
stat_resp_q <= outport_rresp_w;
//-----------------------------------------------------------------
// GPIO Outputs
//-----------------------------------------------------------------
reg [7:0] gpio_out_q;
always @ (posedge clk_i )
if (rst_i)
gpio_out_q <= 8'b0;
else if (state_q == STATE_GPIO_WR && rx_valid_w)
gpio_out_q <= rx_data_w[7:0];
assign gpio_outputs_o = gpio_out_q;
endmodule
|
module ft245_axi_fifo_8_32
(
// Inputs
input clk_i
,input rst_i
,input inport_valid_i
,input [ 7:0] inport_data_i
,input outport_accept_i
// Outputs
,output inport_accept_o
,output outport_valid_o
,output [ 31:0] outport_data_o
);
wire flush_w = !inport_valid_i;
wire space_w = !outport_valid_o || outport_accept_i;
//-----------------------------------------------------------------
// Data write index
//-----------------------------------------------------------------
reg [1:0] idx_q;
always @ (posedge clk_i )
if (rst_i)
idx_q <= 2'b0;
else if (flush_w)
idx_q <= 2'b0;
else if (inport_valid_i && inport_accept_o)
idx_q <= idx_q + 2'd1;
//-----------------------------------------------------------------
// Data
//-----------------------------------------------------------------
reg [31:0] data_q;
reg [31:0] data_r;
always @ *
begin
data_r = 32'b0;
case (idx_q)
2'd0: data_r = {24'b0, inport_data_i};
2'd1: data_r = {16'b0, inport_data_i, data_q[7:0]};
2'd2: data_r = {8'b0, inport_data_i, data_q[15:0]};
2'd3: data_r = {inport_data_i, data_q[23:0]};
endcase
end
always @ (posedge clk_i )
if (rst_i)
data_q <= 32'b0;
else if (inport_valid_i && inport_accept_o)
data_q <= data_r;
//-----------------------------------------------------------------
// Valid
//-----------------------------------------------------------------
reg valid_q;
always @ (posedge clk_i )
if (rst_i)
valid_q <= 1'b0;
else if (flush_w && idx_q != 2'd0)
valid_q <= 1'b1;
else if (inport_valid_i && inport_accept_o && idx_q == 2'd3)
valid_q <= 1'b1;
else if (outport_accept_i)
valid_q <= 1'b0;
//-----------------------------------------------------------------
// Outputs
//-----------------------------------------------------------------
assign outport_valid_o = valid_q;
assign outport_data_o = data_q;
assign inport_accept_o = space_w;
endmodule
|
module ft245_axi_fifo_32_8
(
// Inputs
input clk_i
,input rst_i
,input inport_valid_i
,input [ 31:0] inport_data_i
,input outport_accept_i
// Outputs
,output inport_accept_o
,output [ 7:0] outport_data_o
,output outport_valid_o
);
reg valid_q;
reg [7:0] data_q;
reg [1:0] idx_q;
wire accept_w;
//-----------------------------------------------------------------
// Last valid data detection
//-----------------------------------------------------------------
wire last_data_w = (idx_q == 2'd3);
//-----------------------------------------------------------------
// Data
//-----------------------------------------------------------------
reg [7:0] data_r;
always @ *
begin
data_r = 8'b0;
case (idx_q)
2'd0: data_r = inport_data_i[7:0];
2'd1: data_r = inport_data_i[15:8];
2'd2: data_r = inport_data_i[23:16];
2'd3: data_r = inport_data_i[31:24];
endcase
end
always @ (posedge clk_i )
if (rst_i)
data_q <= 8'b0;
else if (accept_w)
data_q <= data_r;
assign outport_data_o = data_q;
//-----------------------------------------------------------------
// Valid
//-----------------------------------------------------------------
always @ (posedge clk_i )
if (rst_i)
valid_q <= 1'b0;
else if (accept_w)
valid_q <= inport_valid_i;
assign outport_valid_o = valid_q;
//-----------------------------------------------------------------
// Data read index
//-----------------------------------------------------------------
always @ (posedge clk_i )
if (rst_i)
idx_q <= 2'b0;
else if (last_data_w && accept_w)
idx_q <= 2'b0;
else if (accept_w && inport_valid_i)
idx_q <= idx_q + 2'd1;
//-----------------------------------------------------------------
// Accept
//-----------------------------------------------------------------
assign accept_w = !outport_valid_o || (outport_valid_o && outport_accept_i);
// Entire word consumed, pop...
assign inport_accept_o = accept_w && last_data_w;
endmodule
|
module axi4_lite_tap
(
// Inputs
input clk_i
,input rst_i
,input inport_awvalid_i
,input [ 31:0] inport_awaddr_i
,input [ 3:0] inport_awid_i
,input [ 7:0] inport_awlen_i
,input [ 1:0] inport_awburst_i
,input inport_wvalid_i
,input [ 31:0] inport_wdata_i
,input [ 3:0] inport_wstrb_i
,input inport_wlast_i
,input inport_bready_i
,input inport_arvalid_i
,input [ 31:0] inport_araddr_i
,input [ 3:0] inport_arid_i
,input [ 7:0] inport_arlen_i
,input [ 1:0] inport_arburst_i
,input inport_rready_i
,input outport_awready_i
,input outport_wready_i
,input outport_bvalid_i
,input [ 1:0] outport_bresp_i
,input [ 3:0] outport_bid_i
,input outport_arready_i
,input outport_rvalid_i
,input [ 31:0] outport_rdata_i
,input [ 1:0] outport_rresp_i
,input [ 3:0] outport_rid_i
,input outport_rlast_i
,input outport_peripheral0_awready_i
,input outport_peripheral0_wready_i
,input outport_peripheral0_bvalid_i
,input [ 1:0] outport_peripheral0_bresp_i
,input outport_peripheral0_arready_i
,input outport_peripheral0_rvalid_i
,input [ 31:0] outport_peripheral0_rdata_i
,input [ 1:0] outport_peripheral0_rresp_i
// Outputs
,output inport_awready_o
,output inport_wready_o
,output inport_bvalid_o
,output [ 1:0] inport_bresp_o
,output [ 3:0] inport_bid_o
,output inport_arready_o
,output inport_rvalid_o
,output [ 31:0] inport_rdata_o
,output [ 1:0] inport_rresp_o
,output [ 3:0] inport_rid_o
,output inport_rlast_o
,output outport_awvalid_o
,output [ 31:0] outport_awaddr_o
,output [ 3:0] outport_awid_o
,output [ 7:0] outport_awlen_o
,output [ 1:0] outport_awburst_o
,output outport_wvalid_o
,output [ 31:0] outport_wdata_o
,output [ 3:0] outport_wstrb_o
,output outport_wlast_o
,output outport_bready_o
,output outport_arvalid_o
,output [ 31:0] outport_araddr_o
,output [ 3:0] outport_arid_o
,output [ 7:0] outport_arlen_o
,output [ 1:0] outport_arburst_o
,output outport_rready_o
,output outport_peripheral0_awvalid_o
,output [ 31:0] outport_peripheral0_awaddr_o
,output outport_peripheral0_wvalid_o
,output [ 31:0] outport_peripheral0_wdata_o
,output [ 3:0] outport_peripheral0_wstrb_o
,output outport_peripheral0_bready_o
,output outport_peripheral0_arvalid_o
,output [ 31:0] outport_peripheral0_araddr_o
,output outport_peripheral0_rready_o
);
`define ADDR_SEL_W 1
`define PERIPH0_ADDR 32'h80000000
`define PERIPH0_MASK 32'h80000000
//-----------------------------------------------------------------
// AXI: Read
//-----------------------------------------------------------------
reg [3:0] read_pending_q;
reg [3:0] read_pending_r;
reg [3:0] arid_q;
reg [`ADDR_SEL_W-1:0] read_port_q;
reg [`ADDR_SEL_W-1:0] read_port_r;
always @ *
begin
read_port_r = `ADDR_SEL_W'b0;
if ((inport_araddr_i & `PERIPH0_MASK) == `PERIPH0_ADDR) read_port_r = `ADDR_SEL_W'd1;
end
wire read_incr_w = (inport_arvalid_i && inport_arready_o);
wire read_decr_w = (inport_rvalid_o && inport_rlast_o && inport_rready_i);
always @ *
begin
read_pending_r = read_pending_q;
if (read_incr_w && !read_decr_w)
read_pending_r = read_pending_r + 4'd1;
else if (!read_incr_w && read_decr_w)
read_pending_r = read_pending_r - 4'd1;
end
always @ (posedge clk_i )
if (rst_i)
begin
read_pending_q <= 4'b0;
arid_q <= 4'b0;
read_port_q <= `ADDR_SEL_W'b0;
end
else
begin
read_pending_q <= read_pending_r;
// Read command accepted
if (inport_arvalid_i && inport_arready_o)
begin
arid_q <= inport_arid_i;
read_port_q <= read_port_r;
end
end
wire read_accept_w = (read_port_q == read_port_r && read_pending_q != 4'hF) || (read_pending_q == 4'h0);
assign outport_arvalid_o = inport_arvalid_i & read_accept_w & (read_port_r == `ADDR_SEL_W'd0);
assign outport_araddr_o = inport_araddr_i;
assign outport_arid_o = inport_arid_i;
assign outport_arlen_o = inport_arlen_i;
assign outport_arburst_o = inport_arburst_i;
assign outport_rready_o = inport_rready_i;
assign outport_peripheral0_arvalid_o = inport_arvalid_i & read_accept_w & (read_port_r == `ADDR_SEL_W'd1);
assign outport_peripheral0_araddr_o = inport_araddr_i;
assign outport_peripheral0_rready_o = inport_rready_i;
reg outport_rvalid_r;
reg [31:0] outport_rdata_r;
reg [1:0] outport_rresp_r;
reg [3:0] outport_rid_r;
reg outport_rlast_r;
always @ *
begin
case (read_port_q)
`ADDR_SEL_W'd1:
begin
outport_rvalid_r = outport_peripheral0_rvalid_i;
outport_rdata_r = outport_peripheral0_rdata_i;
outport_rresp_r = outport_peripheral0_rresp_i;
outport_rid_r = arid_q;
outport_rlast_r = 1'b1;
end
default:
begin
outport_rvalid_r = outport_rvalid_i;
outport_rdata_r = outport_rdata_i;
outport_rresp_r = outport_rresp_i;
outport_rid_r = outport_rid_i;
outport_rlast_r = outport_rlast_i;
end
endcase
end
assign inport_rvalid_o = outport_rvalid_r;
assign inport_rdata_o = outport_rdata_r;
assign inport_rresp_o = outport_rresp_r;
assign inport_rid_o = outport_rid_r;
assign inport_rlast_o = outport_rlast_r;
reg inport_arready_r;
always @ *
begin
case (read_port_r)
`ADDR_SEL_W'd1:
inport_arready_r = outport_peripheral0_arready_i;
default:
inport_arready_r = outport_arready_i;
endcase
end
assign inport_arready_o = read_accept_w & inport_arready_r;
//-------------------------------------------------------------
// Write Request
//-------------------------------------------------------------
reg awvalid_q;
reg wvalid_q;
reg wlast_q;
wire wr_cmd_accepted_w = (inport_awvalid_i && inport_awready_o) || awvalid_q;
wire wr_data_accepted_w = (inport_wvalid_i && inport_wready_o) || wvalid_q;
wire wr_data_last_w = (wvalid_q & wlast_q) || (inport_wvalid_i && inport_wready_o && inport_wlast_i);
always @ (posedge clk_i )
if (rst_i)
awvalid_q <= 1'b0;
else if (inport_awvalid_i && inport_awready_o && (!wr_data_accepted_w || !wr_data_last_w))
awvalid_q <= 1'b1;
else if (wr_data_accepted_w && wr_data_last_w)
awvalid_q <= 1'b0;
always @ (posedge clk_i )
if (rst_i)
wvalid_q <= 1'b0;
else if (inport_wvalid_i && inport_wready_o && !wr_cmd_accepted_w)
wvalid_q <= 1'b1;
else if (wr_cmd_accepted_w)
wvalid_q <= 1'b0;
always @ (posedge clk_i )
if (rst_i)
wlast_q <= 1'b0;
else if (inport_wvalid_i && inport_wready_o)
wlast_q <= inport_wlast_i;
//-----------------------------------------------------------------
// AXI: Write
//-----------------------------------------------------------------
reg [3:0] write_pending_q;
reg [3:0] write_pending_r;
reg [3:0] awid_q;
reg [`ADDR_SEL_W-1:0] write_port_q;
reg [`ADDR_SEL_W-1:0] write_port_r;
always @ *
begin
if (inport_awvalid_i & ~awvalid_q)
begin
write_port_r = `ADDR_SEL_W'b0;
if ((inport_awaddr_i & `PERIPH0_MASK) == `PERIPH0_ADDR) write_port_r = `ADDR_SEL_W'd1;
end
else
write_port_r = write_port_q;
end
wire write_incr_w = (inport_awvalid_i && inport_awready_o);
wire write_decr_w = (inport_bvalid_o && inport_bready_i);
always @ *
begin
write_pending_r = write_pending_q;
if (write_incr_w && !write_decr_w)
write_pending_r = write_pending_r + 4'd1;
else if (!write_incr_w && write_decr_w)
write_pending_r = write_pending_r - 4'd1;
end
always @ (posedge clk_i )
if (rst_i)
begin
write_pending_q <= 4'b0;
awid_q <= 4'b0;
write_port_q <= `ADDR_SEL_W'b0;
end
else
begin
write_pending_q <= write_pending_r;
// Write command accepted
if (inport_awvalid_i && inport_awready_o)
begin
awid_q <= inport_awid_i;
write_port_q <= write_port_r;
end
end
wire write_accept_w = (write_port_q == write_port_r && write_pending_q != 4'hF) || (write_pending_q == 4'h0);
assign outport_awvalid_o = inport_awvalid_i & ~awvalid_q & write_accept_w & (write_port_r == `ADDR_SEL_W'd0);
assign outport_awaddr_o = inport_awaddr_i;
assign outport_awid_o = inport_awid_i;
assign outport_awlen_o = inport_awlen_i;
assign outport_awburst_o = inport_awburst_i;
assign outport_wvalid_o = inport_wvalid_i & ~wvalid_q & (inport_awvalid_i || awvalid_q) & (write_port_r == `ADDR_SEL_W'd0);
assign outport_wdata_o = inport_wdata_i;
assign outport_wstrb_o = inport_wstrb_i;
assign outport_wlast_o = inport_wlast_i;
assign outport_bready_o = inport_bready_i;
assign outport_peripheral0_awvalid_o = inport_awvalid_i & ~awvalid_q & write_accept_w & (write_port_r == `ADDR_SEL_W'd1);
assign outport_peripheral0_awaddr_o = inport_awaddr_i;
assign outport_peripheral0_wvalid_o = inport_wvalid_i & ~wvalid_q & ((inport_awvalid_i && write_accept_w) || awvalid_q) & (write_port_r == `ADDR_SEL_W'd1);
assign outport_peripheral0_wdata_o = inport_wdata_i;
assign outport_peripheral0_wstrb_o = inport_wstrb_i;
assign outport_peripheral0_bready_o = inport_bready_i;
reg outport_bvalid_r;
reg [1:0] outport_bresp_r;
reg [3:0] outport_bid_r;
always @ *
begin
case (write_port_q)
`ADDR_SEL_W'd1:
begin
outport_bvalid_r = outport_peripheral0_bvalid_i;
outport_bresp_r = outport_peripheral0_bresp_i;
outport_bid_r = awid_q;
end
default:
begin
outport_bvalid_r = outport_bvalid_i;
outport_bresp_r = outport_bresp_i;
outport_bid_r = outport_bid_i;
end
endcase
end
assign inport_bvalid_o = outport_bvalid_r;
assign inport_bresp_o = outport_bresp_r;
assign inport_bid_o = outport_bid_r;
reg inport_awready_r;
reg inport_wready_r;
always @ *
begin
case (write_port_r)
`ADDR_SEL_W'd1:
begin
inport_awready_r = outport_peripheral0_awready_i;
inport_wready_r = outport_peripheral0_wready_i;
end
default:
begin
inport_awready_r = outport_awready_i;
inport_wready_r = outport_wready_i;
end
endcase
end
assign inport_awready_o = write_accept_w & ~awvalid_q & inport_awready_r;
assign inport_wready_o = write_accept_w & ~wvalid_q & inport_wready_r;
endmodule
|
module axi4_arb
(
// Inputs
input clk_i
,input rst_i
,input inport0_awvalid_i
,input [ 31:0] inport0_awaddr_i
,input [ 3:0] inport0_awid_i
,input [ 7:0] inport0_awlen_i
,input [ 1:0] inport0_awburst_i
,input inport0_wvalid_i
,input [ 31:0] inport0_wdata_i
,input [ 3:0] inport0_wstrb_i
,input inport0_wlast_i
,input inport0_bready_i
,input inport0_arvalid_i
,input [ 31:0] inport0_araddr_i
,input [ 3:0] inport0_arid_i
,input [ 7:0] inport0_arlen_i
,input [ 1:0] inport0_arburst_i
,input inport0_rready_i
,input inport1_awvalid_i
,input [ 31:0] inport1_awaddr_i
,input [ 3:0] inport1_awid_i
,input [ 7:0] inport1_awlen_i
,input [ 1:0] inport1_awburst_i
,input inport1_wvalid_i
,input [ 31:0] inport1_wdata_i
,input [ 3:0] inport1_wstrb_i
,input inport1_wlast_i
,input inport1_bready_i
,input inport1_arvalid_i
,input [ 31:0] inport1_araddr_i
,input [ 3:0] inport1_arid_i
,input [ 7:0] inport1_arlen_i
,input [ 1:0] inport1_arburst_i
,input inport1_rready_i
,input outport_awready_i
,input outport_wready_i
,input outport_bvalid_i
,input [ 1:0] outport_bresp_i
,input [ 3:0] outport_bid_i
,input outport_arready_i
,input outport_rvalid_i
,input [ 31:0] outport_rdata_i
,input [ 1:0] outport_rresp_i
,input [ 3:0] outport_rid_i
,input outport_rlast_i
// Outputs
,output inport0_awready_o
,output inport0_wready_o
,output inport0_bvalid_o
,output [ 1:0] inport0_bresp_o
,output [ 3:0] inport0_bid_o
,output inport0_arready_o
,output inport0_rvalid_o
,output [ 31:0] inport0_rdata_o
,output [ 1:0] inport0_rresp_o
,output [ 3:0] inport0_rid_o
,output inport0_rlast_o
,output inport1_awready_o
,output inport1_wready_o
,output inport1_bvalid_o
,output [ 1:0] inport1_bresp_o
,output [ 3:0] inport1_bid_o
,output inport1_arready_o
,output inport1_rvalid_o
,output [ 31:0] inport1_rdata_o
,output [ 1:0] inport1_rresp_o
,output [ 3:0] inport1_rid_o
,output inport1_rlast_o
,output outport_awvalid_o
,output [ 31:0] outport_awaddr_o
,output [ 3:0] outport_awid_o
,output [ 7:0] outport_awlen_o
,output [ 1:0] outport_awburst_o
,output outport_wvalid_o
,output [ 31:0] outport_wdata_o
,output [ 3:0] outport_wstrb_o
,output outport_wlast_o
,output outport_bready_o
,output outport_arvalid_o
,output [ 31:0] outport_araddr_o
,output [ 3:0] outport_arid_o
,output [ 7:0] outport_arlen_o
,output [ 1:0] outport_arburst_o
,output outport_rready_o
);
//-----------------------------------------------------------------
// Read Requestor Select
//-----------------------------------------------------------------
wire [1:0] read_req_w;
reg read_hold_q;
wire [1:0] read_grant_w;
assign read_req_w[0] = inport0_arvalid_i;
assign read_req_w[1] = inport1_arvalid_i;
axi4_arb_onehot2
u_rd_arb
(
.clk_i(clk_i),
.rst_i(rst_i),
.hold_i(read_hold_q),
.request_i(read_req_w),
.grant_o(read_grant_w)
);
//-----------------------------------------------------------------
// Read Hold
//-----------------------------------------------------------------
always @ (posedge clk_i )
if (rst_i)
read_hold_q <= 1'b0;
else if (outport_arvalid_o && !outport_arready_i)
read_hold_q <= 1'b1;
else if (outport_arready_i)
read_hold_q <= 1'b0;
//-----------------------------------------------------------------
// Read Request Mux
//-----------------------------------------------------------------
reg outport_arvalid_r;
reg [ 31:0] outport_araddr_r;
reg [ 3:0] outport_arid_r;
reg [ 7:0] outport_arlen_r;
reg [ 1:0] outport_arburst_r;
always @ *
begin
outport_arvalid_r = 1'b0;
outport_araddr_r = 32'b0;
outport_arid_r = 4'b0;
outport_arlen_r = 8'b0;
outport_arburst_r = 2'b0;
case (1'b1)
default: // Input 0
begin
outport_arvalid_r = inport0_arvalid_i;
outport_araddr_r = inport0_araddr_i;
outport_arid_r = inport0_arid_i;
outport_arlen_r = inport0_arlen_i;
outport_arburst_r = inport0_arburst_i;
end
read_grant_w[1]:
begin
outport_arvalid_r = inport1_arvalid_i;
outport_araddr_r = inport1_araddr_i;
outport_arid_r = inport1_arid_i;
outport_arlen_r = inport1_arlen_i;
outport_arburst_r = inport1_arburst_i;
end
endcase
end
assign outport_arvalid_o = outport_arvalid_r;
assign outport_araddr_o = outport_araddr_r;
assign outport_arid_o = outport_arid_r;
assign outport_arlen_o = outport_arlen_r;
assign outport_arburst_o = outport_arburst_r;
//-----------------------------------------------------------------
// Read Handshaking Demux
//-----------------------------------------------------------------
assign inport0_arready_o = read_grant_w[0] ? outport_arready_i : 1'b0;
assign inport1_arready_o = read_grant_w[1] ? outport_arready_i : 1'b0;
//-----------------------------------------------------------------
// Read Response Routing
//-----------------------------------------------------------------
reg [1:0] rd_resp_target_r;
always @ *
begin
rd_resp_target_r = 2'b0;
case (outport_rid_i[3:3])
1'd0:
rd_resp_target_r[0] = 1'b1;
1'd1:
rd_resp_target_r[1] = 1'b1;
default:
rd_resp_target_r[0] = 1'b1;
endcase
end
wire [1:0] inport_rready_w;
assign inport_rready_w[0] = inport0_rready_i;
assign inport_rready_w[1] = inport1_rready_i;
assign outport_rready_o = (inport_rready_w & rd_resp_target_r) != 2'b0;
assign inport0_rvalid_o = outport_rvalid_i & rd_resp_target_r[0];
assign inport0_rdata_o = outport_rdata_i;
assign inport0_rid_o = outport_rid_i;
assign inport0_rresp_o = outport_rresp_i;
assign inport0_rlast_o = outport_rlast_i;
assign inport1_rvalid_o = outport_rvalid_i & rd_resp_target_r[1];
assign inport1_rdata_o = outport_rdata_i;
assign inport1_rid_o = outport_rid_i;
assign inport1_rresp_o = outport_rresp_i;
assign inport1_rlast_o = outport_rlast_i;
//-----------------------------------------------------------------
// Write Requestor Select
//-----------------------------------------------------------------
wire [1:0] write_req_w;
reg write_hold_q;
wire [1:0] write_grant_w;
assign write_req_w[0] = inport0_awvalid_i;
assign write_req_w[1] = inport1_awvalid_i;
axi4_arb_onehot2
u_wr_arb
(
.clk_i(clk_i),
.rst_i(rst_i),
.hold_i(write_hold_q),
.request_i(write_req_w),
.grant_o(write_grant_w)
);
//-----------------------------------------------------------------
// Write state tracking
//-----------------------------------------------------------------
reg awvalid_q;
reg wvalid_q;
reg wlast_q;
wire wr_cmd_accepted_w = (outport_awvalid_o && outport_awready_i) || awvalid_q;
wire wr_data_accepted_w = (outport_wvalid_o && outport_wready_i) || wvalid_q;
wire wr_data_last_w = (wvalid_q & wlast_q) || (outport_wvalid_o && outport_wready_i && outport_wlast_o);
always @ (posedge clk_i )
if (rst_i)
awvalid_q <= 1'b0;
else if (outport_awvalid_o && outport_awready_i && (!wr_data_accepted_w || !wr_data_last_w))
awvalid_q <= 1'b1;
else if (wr_data_accepted_w && wr_data_last_w)
awvalid_q <= 1'b0;
always @ (posedge clk_i )
if (rst_i)
wvalid_q <= 1'b0;
else if (outport_wvalid_o && outport_wready_i && !wr_cmd_accepted_w)
wvalid_q <= 1'b1;
else if (wr_cmd_accepted_w)
wvalid_q <= 1'b0;
always @ (posedge clk_i )
if (rst_i)
wlast_q <= 1'b0;
else if (outport_wvalid_o && outport_wready_i)
wlast_q <= outport_wlast_o;
//-----------------------------------------------------------------
// Write Hold
//-----------------------------------------------------------------
reg write_hold_r;
always @ *
begin
write_hold_r = write_hold_q;
// Write hold - check for both command and data (last) accepted
if (write_hold_r)
begin
if (wr_cmd_accepted_w && wr_data_accepted_w && wr_data_last_w)
write_hold_r = 1'b0;
end
// Single transaction accepted in one go - no hold
else if (wr_cmd_accepted_w && wr_data_accepted_w && wr_data_last_w)
write_hold_r = 1'b0;
// Either command or data presented - hold until transaction complete
else if (outport_awvalid_o || outport_wvalid_o)
write_hold_r = 1'b1;
end
always @ (posedge clk_i )
if (rst_i)
write_hold_q <= 1'b0;
else
write_hold_q <= write_hold_r;
//-----------------------------------------------------------------
// Write Request Mux
//-----------------------------------------------------------------
reg outport_awvalid_r;
reg [ 31:0] outport_awaddr_r;
reg [ 3:0] outport_awid_r;
reg [ 7:0] outport_awlen_r;
reg [ 1:0] outport_awburst_r;
reg outport_wvalid_r;
reg [ 31:0] outport_wdata_r;
reg [ 3:0] outport_wstrb_r;
reg outport_wlast_r;
always @ *
begin
outport_awvalid_r = 1'b0;
outport_awaddr_r = 32'b0;
outport_awid_r = 4'b0;
outport_awlen_r = 8'b0;
outport_awburst_r = 2'b0;
outport_wvalid_r = 1'b0;
outport_wdata_r = 32'b0;
outport_wstrb_r = 4'b0;
outport_wlast_r = 1'b0;
case (1'b1)
default: // Input 0
begin
outport_awvalid_r = inport0_awvalid_i;
outport_awaddr_r = inport0_awaddr_i;
outport_awid_r = inport0_awid_i;
outport_awlen_r = inport0_awlen_i;
outport_awburst_r = inport0_awburst_i;
outport_wvalid_r = inport0_wvalid_i;
outport_wdata_r = inport0_wdata_i;
outport_wstrb_r = inport0_wstrb_i;
outport_wlast_r = inport0_wlast_i;
end
write_grant_w[1]:
begin
outport_awvalid_r = inport1_awvalid_i;
outport_awaddr_r = inport1_awaddr_i;
outport_awid_r = inport1_awid_i;
outport_awlen_r = inport1_awlen_i;
outport_awburst_r = inport1_awburst_i;
outport_wvalid_r = inport1_wvalid_i;
outport_wdata_r = inport1_wdata_i;
outport_wstrb_r = inport1_wstrb_i;
outport_wlast_r = inport1_wlast_i;
end
endcase
end
assign outport_awvalid_o = outport_awvalid_r & ~awvalid_q;
assign outport_awaddr_o = outport_awaddr_r;
assign outport_awid_o = outport_awid_r;
assign outport_awlen_o = outport_awlen_r;
assign outport_awburst_o = outport_awburst_r;
assign outport_wvalid_o = outport_wvalid_r & ~wvalid_q;
assign outport_wdata_o = outport_wdata_r;
assign outport_wstrb_o = outport_wstrb_r;
assign outport_wlast_o = outport_wlast_r;
//-----------------------------------------------------------------
// Write Handshaking Demux
//-----------------------------------------------------------------
assign inport0_awready_o = write_grant_w[0] ? (outport_awready_i & ~awvalid_q) : 1'b0;
assign inport0_wready_o = write_grant_w[0] ? (outport_wready_i & ~wvalid_q) : 1'b0;
assign inport1_awready_o = write_grant_w[1] ? (outport_awready_i & ~awvalid_q) : 1'b0;
assign inport1_wready_o = write_grant_w[1] ? (outport_wready_i & ~wvalid_q) : 1'b0;
//-----------------------------------------------------------------
// Write Response Routing
//-----------------------------------------------------------------
reg [1:0] wr_resp_target_r;
always @ *
begin
wr_resp_target_r = 2'b0;
case (outport_bid_i[3:3])
1'd0:
wr_resp_target_r[0] = 1'b1;
1'd1:
wr_resp_target_r[1] = 1'b1;
default:
wr_resp_target_r[0] = 1'b1;
endcase
end
wire [1:0] inport_bready_w;
assign inport_bready_w[0] = inport0_bready_i;
assign inport_bready_w[1] = inport1_bready_i;
assign outport_bready_o = (inport_bready_w & wr_resp_target_r) != 2'b0;
assign inport0_bvalid_o = outport_bvalid_i & wr_resp_target_r[0];
assign inport0_bid_o = outport_bid_i;
assign inport0_bresp_o = outport_bresp_i;
assign inport1_bvalid_o = outport_bvalid_i & wr_resp_target_r[1];
assign inport1_bid_o = outport_bid_i;
assign inport1_bresp_o = outport_bresp_i;
endmodule
|
module axi4_arb_onehot2
(
// Inputs
input clk_i
,input rst_i
,input hold_i
,input [1:0] request_i
// Outputs
,output [1:0] grant_o
);
//-----------------------------------------------------------------
// Registers / Wires
//-----------------------------------------------------------------
wire [1:0] req_ffs_masked_w;
wire [1:0] req_ffs_unmasked_w;
wire [1:0] req_ffs_w;
reg [1:0] mask_next_q;
reg [1:0] grant_last_q;
wire [1:0] grant_new_w;
//-----------------------------------------------------------------
// ffs: Find first set
//-----------------------------------------------------------------
function [1:0] ffs;
input [1:0] request;
begin
ffs[0] = request[0];
ffs[1] = ffs[0] | request[1];
end
endfunction
assign req_ffs_masked_w = ffs(request_i & mask_next_q);
assign req_ffs_unmasked_w = ffs(request_i);
assign req_ffs_w = (|req_ffs_masked_w) ? req_ffs_masked_w : req_ffs_unmasked_w;
always @ (posedge clk_i )
if (rst_i == 1'b1)
begin
mask_next_q <= {2{1'b1}};
grant_last_q <= 2'b0;
end
else
begin
if (~hold_i)
mask_next_q <= {req_ffs_w[0:0], 1'b0};
grant_last_q <= grant_o;
end
assign grant_new_w = req_ffs_w ^ {req_ffs_w[0:0], 1'b0};
assign grant_o = hold_i ? grant_last_q : grant_new_w;
endmodule
|
module axi4_retime_fifo
//-----------------------------------------------------------------
// Params
//-----------------------------------------------------------------
#(
parameter WIDTH = 8,
parameter DEPTH = 2,
parameter ADDR_W = 1
)
//-----------------------------------------------------------------
// Ports
//-----------------------------------------------------------------
(
// Inputs
input clk_i
,input rst_i
,input [WIDTH-1:0] data_in_i
,input push_i
,input pop_i
// Outputs
,output [WIDTH-1:0] data_out_o
,output accept_o
,output valid_o
);
//-----------------------------------------------------------------
// Local Params
//-----------------------------------------------------------------
localparam COUNT_W = ADDR_W + 1;
//-----------------------------------------------------------------
// Registers
//-----------------------------------------------------------------
reg [WIDTH-1:0] ram_q[DEPTH-1:0];
reg [ADDR_W-1:0] rd_ptr_q;
reg [ADDR_W-1:0] wr_ptr_q;
reg [COUNT_W-1:0] count_q;
//-----------------------------------------------------------------
// Sequential
//-----------------------------------------------------------------
always @ (posedge clk_i )
if (rst_i)
begin
count_q <= {(COUNT_W) {1'b0}};
rd_ptr_q <= {(ADDR_W) {1'b0}};
wr_ptr_q <= {(ADDR_W) {1'b0}};
end
else
begin
// Push
if (push_i & accept_o)
begin
ram_q[wr_ptr_q] <= data_in_i;
wr_ptr_q <= wr_ptr_q + 1;
end
// Pop
if (pop_i & valid_o)
rd_ptr_q <= rd_ptr_q + 1;
// Count up
if ((push_i & accept_o) & ~(pop_i & valid_o))
count_q <= count_q + 1;
// Count down
else if (~(push_i & accept_o) & (pop_i & valid_o))
count_q <= count_q - 1;
end
//-------------------------------------------------------------------
// Combinatorial
//-------------------------------------------------------------------
/* verilator lint_off WIDTH */
assign valid_o = (count_q != 0);
assign accept_o = (count_q != DEPTH);
/* verilator lint_on WIDTH */
assign data_out_o = ram_q[rd_ptr_q];
endmodule
|
module axi4_cdc_fifo6
(
// Inputs
input rd_clk_i
,input rd_rst_i
,input rd_pop_i
,input wr_clk_i
,input wr_rst_i
,input [ 5:0] wr_data_i
,input wr_push_i
// Outputs
,output [ 5:0] rd_data_o
,output rd_empty_o
,output wr_full_o
);
//-----------------------------------------------------------------
// Registers
//-----------------------------------------------------------------
reg [4:0] rd_ptr_q;
reg [4:0] wr_ptr_q;
//-----------------------------------------------------------------
// Write
//-----------------------------------------------------------------
wire [4:0] wr_ptr_next_w = wr_ptr_q + 5'd1;
always @ (posedge wr_clk_i or posedge wr_rst_i)
if (wr_rst_i)
wr_ptr_q <= 5'b0;
else if (wr_push_i & ~wr_full_o)
wr_ptr_q <= wr_ptr_next_w;
wire [4:0] wr_rd_ptr_w;
axi4_cdc_fifo6_resync_bus
#( .WIDTH(5))
u_resync_rd_ptr_q
(
.wr_clk_i(rd_clk_i),
.wr_rst_i(rd_rst_i),
.wr_i(1'b1),
.wr_data_i(rd_ptr_q),
.wr_busy_o(),
.rd_clk_i(wr_clk_i),
.rd_rst_i(wr_rst_i),
.rd_data_o(wr_rd_ptr_w) // Delayed version of rd_ptr_q
);
assign wr_full_o = (wr_ptr_next_w == wr_rd_ptr_w);
//-------------------------------------------------------------------
// Dual port RAM
//-------------------------------------------------------------------
wire [5:0] rd_data_w;
axi4_cdc_fifo6_ram_dp_32_5
u_ram
(
// Inputs
.clk0_i(wr_clk_i),
.rst0_i(wr_rst_i),
.clk1_i(rd_clk_i),
.rst1_i(rd_rst_i),
// Write side
.addr0_i(wr_ptr_q),
.wr0_i(wr_push_i & ~wr_full_o),
.data0_i(wr_data_i),
.data0_o(),
// Read side
.addr1_i(rd_ptr_q),
.data1_i(6'b0),
.wr1_i(1'b0),
.data1_o(rd_data_w)
);
//-----------------------------------------------------------------
// Read
//-----------------------------------------------------------------
wire [4:0] rd_wr_ptr_w;
axi4_cdc_fifo6_resync_bus
#( .WIDTH(5))
u_resync_wr_ptr_q
(
.wr_clk_i(wr_clk_i),
.wr_rst_i(wr_rst_i),
.wr_i(1'b1),
.wr_data_i(wr_ptr_q),
.wr_busy_o(),
.rd_clk_i(rd_clk_i),
.rd_rst_i(rd_rst_i),
.rd_data_o(rd_wr_ptr_w) // Delayed version of wr_ptr_q
);
//-------------------------------------------------------------------
// Read Skid Buffer
//-------------------------------------------------------------------
reg rd_skid_q;
reg [5:0] rd_skid_data_q;
reg rd_q;
wire read_ok_w = (rd_wr_ptr_w != rd_ptr_q);
wire valid_w = (rd_skid_q | rd_q);
always @ (posedge rd_clk_i or posedge rd_rst_i)
if (rd_rst_i)
begin
rd_skid_q <= 1'b0;
rd_skid_data_q <= 6'b0;
end
else if (valid_w && !rd_pop_i)
begin
rd_skid_q <= 1'b1;
rd_skid_data_q <= rd_data_o;
end
else
begin
rd_skid_q <= 1'b0;
rd_skid_data_q <= 6'b0;
end
assign rd_data_o = rd_skid_q ? rd_skid_data_q : rd_data_w;
//-----------------------------------------------------------------
// Read Pointer
//-----------------------------------------------------------------
always @ (posedge rd_clk_i or posedge rd_rst_i)
if (rd_rst_i)
rd_q <= 1'b0;
else
rd_q <= read_ok_w;
wire [4:0] rd_ptr_next_w = rd_ptr_q + 5'd1;
always @ (posedge rd_clk_i or posedge rd_rst_i)
if (rd_rst_i)
rd_ptr_q <= 5'b0;
// Read address increment
else if (read_ok_w && ((!valid_w) || (valid_w && rd_pop_i)))
rd_ptr_q <= rd_ptr_next_w;
assign rd_empty_o = !valid_w;
endmodule
|
module axi4_cdc_fifo6_ram_dp_32_5
(
// Inputs
input clk0_i
,input rst0_i
,input [ 4:0] addr0_i
,input [ 5:0] data0_i
,input wr0_i
,input clk1_i
,input rst1_i
,input [ 4:0] addr1_i
,input [ 5:0] data1_i
,input wr1_i
// Outputs
,output [ 5:0] data0_o
,output [ 5:0] data1_o
);
/* verilator lint_off MULTIDRIVEN */
reg [5:0] ram [31:0] /*verilator public*/;
/* verilator lint_on MULTIDRIVEN */
reg [5:0] ram_read0_q;
reg [5:0] ram_read1_q;
// Synchronous write
always @ (posedge clk0_i)
begin
if (wr0_i)
ram[addr0_i] <= data0_i;
ram_read0_q <= ram[addr0_i];
end
always @ (posedge clk1_i)
begin
if (wr1_i)
ram[addr1_i] <= data1_i;
ram_read1_q <= ram[addr1_i];
end
assign data0_o = ram_read0_q;
assign data1_o = ram_read1_q;
endmodule
|
module axi4_cdc_fifo6_resync_bus
//-----------------------------------------------------------------
// Params
//-----------------------------------------------------------------
#(
parameter WIDTH = 4
)
//-----------------------------------------------------------------
// Ports
//-----------------------------------------------------------------
(
input wr_clk_i,
input wr_rst_i,
input wr_i,
input [WIDTH-1:0] wr_data_i,
output wr_busy_o,
input rd_clk_i,
input rd_rst_i,
output [WIDTH-1:0] rd_data_o
);
wire rd_toggle_w;
wire wr_toggle_w;
//-----------------------------------------------------------------
// Write
//-----------------------------------------------------------------
wire write_req_w = wr_i && !wr_busy_o;
// Write storage for domain crossing
(* ASYNC_REG = "TRUE" *) reg [WIDTH-1:0] wr_buffer_q;
always @ (posedge wr_clk_i or posedge wr_rst_i)
if (wr_rst_i)
wr_buffer_q <= {(WIDTH){1'b0}};
else if (write_req_w)
wr_buffer_q <= wr_data_i;
reg wr_toggle_q;
always @ (posedge wr_clk_i or posedge wr_rst_i)
if (wr_rst_i)
wr_toggle_q <= 1'b0;
else if (write_req_w)
wr_toggle_q <= ~wr_toggle_q;
reg wr_busy_q;
always @ (posedge wr_clk_i or posedge wr_rst_i)
if (wr_rst_i)
wr_busy_q <= 1'b0;
else if (write_req_w)
wr_busy_q <= 1'b1;
else if (wr_toggle_q == wr_toggle_w)
wr_busy_q <= 1'b0;
assign wr_busy_o = wr_busy_q;
//-----------------------------------------------------------------
// Write -> Read request
//-----------------------------------------------------------------
axi4_cdc_fifo6_resync
u_sync_wr_toggle
(
.clk_i(rd_clk_i),
.rst_i(rd_rst_i),
.async_i(wr_toggle_q),
.sync_o(rd_toggle_w)
);
//-----------------------------------------------------------------
// Read
//-----------------------------------------------------------------
reg rd_toggle_q;
always @ (posedge rd_clk_i or posedge rd_rst_i)
if (rd_rst_i)
rd_toggle_q <= 1'b0;
else
rd_toggle_q <= rd_toggle_w;
// Read storage for domain crossing
(* ASYNC_REG = "TRUE" *) reg [WIDTH-1:0] rd_buffer_q;
always @ (posedge rd_clk_i or posedge rd_rst_i)
if (rd_rst_i)
rd_buffer_q <= {(WIDTH){1'b0}};
else if (rd_toggle_q != rd_toggle_w)
rd_buffer_q <= wr_buffer_q; // Capture from other domain
assign rd_data_o = rd_buffer_q;
//-----------------------------------------------------------------
// Read->Write response
//-----------------------------------------------------------------
axi4_cdc_fifo6_resync
u_sync_rd_toggle
(
.clk_i(wr_clk_i),
.rst_i(wr_rst_i),
.async_i(rd_toggle_q),
.sync_o(wr_toggle_w)
);
endmodule
|
module axi4_cdc_fifo6_resync
//-----------------------------------------------------------------
// Params
//-----------------------------------------------------------------
#(
parameter RESET_VAL = 1'b0
)
//-----------------------------------------------------------------
// Ports
//-----------------------------------------------------------------
(
input clk_i,
input rst_i,
input async_i,
output sync_o
);
(* ASYNC_REG = "TRUE" *) reg sync_ms;
(* ASYNC_REG = "TRUE" *) reg sync_q;
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
begin
sync_ms <= RESET_VAL;
sync_q <= RESET_VAL;
end
else
begin
sync_ms <= async_i;
sync_q <= sync_ms;
end
assign sync_o = sync_q;
endmodule
|
module axi4_cdc_fifo37_ram_dp_32_5
(
// Inputs
input clk0_i
,input rst0_i
,input [ 4:0] addr0_i
,input [ 36:0] data0_i
,input wr0_i
,input clk1_i
,input rst1_i
,input [ 4:0] addr1_i
,input [ 36:0] data1_i
,input wr1_i
// Outputs
,output [ 36:0] data0_o
,output [ 36:0] data1_o
);
/* verilator lint_off MULTIDRIVEN */
reg [36:0] ram [31:0] /*verilator public*/;
/* verilator lint_on MULTIDRIVEN */
reg [36:0] ram_read0_q;
reg [36:0] ram_read1_q;
// Synchronous write
always @ (posedge clk0_i)
begin
if (wr0_i)
ram[addr0_i] <= data0_i;
ram_read0_q <= ram[addr0_i];
end
always @ (posedge clk1_i)
begin
if (wr1_i)
ram[addr1_i] <= data1_i;
ram_read1_q <= ram[addr1_i];
end
assign data0_o = ram_read0_q;
assign data1_o = ram_read1_q;
endmodule
|
module axi4_cdc
(
// Inputs
input wr_clk_i
,input wr_rst_i
,input inport_awvalid_i
,input [ 31:0] inport_awaddr_i
,input [ 3:0] inport_awid_i
,input [ 7:0] inport_awlen_i
,input [ 1:0] inport_awburst_i
,input inport_wvalid_i
,input [ 31:0] inport_wdata_i
,input [ 3:0] inport_wstrb_i
,input inport_wlast_i
,input inport_bready_i
,input inport_arvalid_i
,input [ 31:0] inport_araddr_i
,input [ 3:0] inport_arid_i
,input [ 7:0] inport_arlen_i
,input [ 1:0] inport_arburst_i
,input inport_rready_i
,input rd_clk_i
,input rd_rst_i
,input outport_awready_i
,input outport_wready_i
,input outport_bvalid_i
,input [ 1:0] outport_bresp_i
,input [ 3:0] outport_bid_i
,input outport_arready_i
,input outport_rvalid_i
,input [ 31:0] outport_rdata_i
,input [ 1:0] outport_rresp_i
,input [ 3:0] outport_rid_i
,input outport_rlast_i
// Outputs
,output inport_awready_o
,output inport_wready_o
,output inport_bvalid_o
,output [ 1:0] inport_bresp_o
,output [ 3:0] inport_bid_o
,output inport_arready_o
,output inport_rvalid_o
,output [ 31:0] inport_rdata_o
,output [ 1:0] inport_rresp_o
,output [ 3:0] inport_rid_o
,output inport_rlast_o
,output outport_awvalid_o
,output [ 31:0] outport_awaddr_o
,output [ 3:0] outport_awid_o
,output [ 7:0] outport_awlen_o
,output [ 1:0] outport_awburst_o
,output outport_wvalid_o
,output [ 31:0] outport_wdata_o
,output [ 3:0] outport_wstrb_o
,output outport_wlast_o
,output outport_bready_o
,output outport_arvalid_o
,output [ 31:0] outport_araddr_o
,output [ 3:0] outport_arid_o
,output [ 7:0] outport_arlen_o
,output [ 1:0] outport_arburst_o
,output outport_rready_o
);
//-----------------------------------------------------------------
// Write Command Request
//-----------------------------------------------------------------
wire [45:0] write_cmd_req_out_w;
wire write_cmd_full_w;
wire read_cmd_empty_w;
axi4_cdc_fifo46
u_write_cmd_req
(
.wr_clk_i(wr_clk_i),
.wr_rst_i(wr_rst_i),
.wr_push_i(inport_awvalid_i),
.wr_data_i({inport_awaddr_i, inport_awid_i, inport_awlen_i, inport_awburst_i}),
.wr_full_o(write_cmd_full_w),
.rd_clk_i(rd_clk_i),
.rd_rst_i(rd_rst_i),
.rd_empty_o(read_cmd_empty_w),
.rd_data_o(write_cmd_req_out_w),
.rd_pop_i(outport_awready_i)
);
assign inport_awready_o = ~write_cmd_full_w;
assign outport_awvalid_o = ~read_cmd_empty_w;
assign {outport_awaddr_o, outport_awid_o, outport_awlen_o, outport_awburst_o} = write_cmd_req_out_w;
//-----------------------------------------------------------------
// Write Data Request
//-----------------------------------------------------------------
wire [36:0] write_data_req_out_w;
wire write_data_full_w;
wire write_data_empty_w;
axi4_cdc_fifo37
u_write_data_req
(
.wr_clk_i(wr_clk_i),
.wr_rst_i(wr_rst_i),
.wr_push_i(inport_wvalid_i),
.wr_data_i({inport_wlast_i, inport_wstrb_i, inport_wdata_i}),
.wr_full_o(write_data_full_w),
.rd_clk_i(rd_clk_i),
.rd_rst_i(rd_rst_i),
.rd_empty_o(write_data_empty_w),
.rd_data_o(write_data_req_out_w),
.rd_pop_i(outport_wready_i)
);
assign inport_wready_o = ~write_data_full_w;
assign outport_wvalid_o = ~write_data_empty_w;
assign {outport_wlast_o, outport_wstrb_o, outport_wdata_o} = write_data_req_out_w;
//-----------------------------------------------------------------
// Write Response
//-----------------------------------------------------------------
wire [5:0] write_resp_out_w;
wire write_resp_full_w;
wire write_resp_empty_w;
axi4_cdc_fifo6
u_write_resp
(
.wr_clk_i(rd_clk_i),
.wr_rst_i(rd_rst_i),
.wr_push_i(outport_bvalid_i),
.wr_data_i({outport_bresp_i, outport_bid_i}),
.wr_full_o(write_resp_full_w),
.rd_clk_i(wr_clk_i),
.rd_rst_i(wr_rst_i),
.rd_empty_o(write_resp_empty_w),
.rd_data_o(write_resp_out_w),
.rd_pop_i(inport_bready_i)
);
assign outport_bready_o = ~write_resp_full_w;
assign inport_bvalid_o = ~write_resp_empty_w;
assign {inport_bresp_o, inport_bid_o} = write_resp_out_w;
//-----------------------------------------------------------------
// Read Request
//-----------------------------------------------------------------
wire [45:0] read_req_out_w;
wire read_req_full_w;
wire read_req_empty_w;
axi4_cdc_fifo46
u_read_req
(
.wr_clk_i(wr_clk_i),
.wr_rst_i(wr_rst_i),
.wr_push_i(inport_arvalid_i),
.wr_data_i({inport_araddr_i, inport_arid_i, inport_arlen_i, inport_arburst_i}),
.wr_full_o(read_req_full_w),
.rd_clk_i(rd_clk_i),
.rd_rst_i(rd_rst_i),
.rd_empty_o(read_req_empty_w),
.rd_data_o(read_req_out_w),
.rd_pop_i(outport_arready_i)
);
assign inport_arready_o = ~read_req_full_w;
assign outport_arvalid_o = ~read_req_empty_w;
assign {outport_araddr_o, outport_arid_o, outport_arlen_o, outport_arburst_o} = read_req_out_w;
//-----------------------------------------------------------------
// Read Response
//-----------------------------------------------------------------
wire [38:0] read_resp_out_w;
wire read_resp_full_w;
wire read_resp_empty_w;
axi4_cdc_fifo39
u_read_resp
(
.wr_clk_i(rd_clk_i),
.wr_rst_i(rd_rst_i),
.wr_push_i(outport_rvalid_i),
.wr_data_i({outport_rdata_i, outport_rresp_i, outport_rid_i, outport_rlast_i}),
.wr_full_o(read_resp_full_w),
.rd_clk_i(wr_clk_i),
.rd_rst_i(wr_rst_i),
.rd_empty_o(read_resp_empty_w),
.rd_data_o(read_resp_out_w),
.rd_pop_i(inport_rready_i)
);
assign outport_rready_o = ~read_resp_full_w;
assign inport_rvalid_o = ~read_resp_empty_w;
assign {inport_rdata_o, inport_rresp_o, inport_rid_o, inport_rlast_o} = read_resp_out_w;
endmodule
|
module capture_rle
(
// Inputs
input clk_i
,input rst_i
,input input_clk_i
,input input_rst_i
,input [ 31:0] input_i
,input [ 3:0] cfg_clk_div_i
,input [ 1:0] cfg_width_i
,input cfg_test_mode_i
// Outputs
,output valid_o
,output [ 31:0] data_o
);
//-----------------------------------------------------------------
// Config
//-----------------------------------------------------------------
// These may come from another clock domain - they will be stable prior
// to enabling, but resync to keep the timing tools happy.
(* ASYNC_REG = "TRUE" *) reg [6:0] cfg_ms_q;
always @ (posedge input_clk_i )
if (input_rst_i)
cfg_ms_q <= 7'b0;
else
cfg_ms_q <= {cfg_test_mode_i, cfg_width_i, cfg_clk_div_i};
reg [6:0] cfg_q;
always @ (posedge input_clk_i )
if (input_rst_i)
cfg_q <= 7'b0;
else
cfg_q <= cfg_ms_q;
wire cfg_32bit_w;
wire cfg_24bit_w;
wire [3:0] cfg_clk_div_w;
wire cfg_test_mode_w;
assign {cfg_test_mode_w, cfg_32bit_w, cfg_24bit_w, cfg_clk_div_w} = cfg_q;
//-----------------------------------------------------------------
// Clock divider
//-----------------------------------------------------------------
reg [3:0] clk_div_q;
always @ (posedge clk_i )
if (rst_i)
clk_div_q <= 4'd0;
else if (clk_div_q == 4'd0)
clk_div_q <= cfg_clk_div_w;
else
clk_div_q <= clk_div_q - 4'd1;
wire clk_en_w = (clk_div_q == 4'd0);
//-----------------------------------------------------------------
// Resync
//-----------------------------------------------------------------
(* ASYNC_REG = "TRUE" *) reg [31:0] resync_ms_q;
always @ (posedge input_clk_i )
if (input_rst_i)
resync_ms_q <= 32'b0;
else
resync_ms_q <= input_i;
//-----------------------------------------------------------------
// Sample capture
//-----------------------------------------------------------------
reg [31:0] capture_q;
always @ (posedge input_clk_i )
if (input_rst_i)
capture_q <= 32'b0;
else
capture_q <= resync_ms_q;
//-----------------------------------------------------------------
// Test mode
//-----------------------------------------------------------------
reg [31:0] test_count_q;
always @ (posedge input_clk_i )
if (input_rst_i)
test_count_q <= 32'b0;
else if (clk_en_w)
test_count_q <= test_count_q + 32'd1;
wire [31:0] capture_w = cfg_test_mode_w ? test_count_q : capture_q;
//-----------------------------------------------------------------
// Previous capture
//-----------------------------------------------------------------
reg [31:0] prev_q;
always @ (posedge input_clk_i )
if (input_rst_i)
prev_q <= 32'b0;
else if (clk_en_w)
prev_q <= capture_w;
wire same_w = (prev_q == capture_w);
reg prev_valid_q;
always @ (posedge input_clk_i )
if (input_rst_i)
prev_valid_q <= 1'b0;
else if (clk_en_w)
prev_valid_q <= 1'b1;
//-----------------------------------------------------------------
// RLE count
//-----------------------------------------------------------------
reg [15:0] rle_count_q;
wire overflow_w = cfg_32bit_w ? 1'b1 :
cfg_24bit_w ? (rle_count_q >= 16'hFF) :
(rle_count_q == 16'hFFFF);
always @ (posedge input_clk_i )
if (input_rst_i)
rle_count_q <= 16'd1;
else if (!clk_en_w)
;
else if (overflow_w || !same_w)
rle_count_q <= 16'd1;
else
rle_count_q <= rle_count_q + 16'd1;
//-----------------------------------------------------------------
// Output retime
//-----------------------------------------------------------------
reg valid_q;
reg [31:0] data_q;
always @ (posedge input_clk_i )
if (input_rst_i)
valid_q <= 1'b0;
else
valid_q <= (!same_w || overflow_w) && prev_valid_q && clk_en_w;
always @ (posedge input_clk_i )
if (input_rst_i)
data_q <= 32'b0;
else if (!clk_en_w)
;
else if (cfg_32bit_w)
data_q <= prev_q;
else if (cfg_24bit_w)
data_q <= {rle_count_q[7:0], prev_q[23:0]};
else
data_q <= {rle_count_q[15:0], prev_q[15:0]};
//-----------------------------------------------------------------
// Output
//-----------------------------------------------------------------
wire output_empty_w;
capture_rle_cdc
u_cdc
(
.wr_clk_i(input_clk_i)
,.wr_rst_i(input_rst_i)
,.wr_push_i(valid_q)
,.wr_data_i(data_q)
,.wr_full_o()
,.rd_clk_i(clk_i)
,.rd_rst_i(rst_i)
,.rd_data_o(data_o)
,.rd_empty_o(output_empty_w)
,.rd_pop_i(1'b1)
);
assign valid_o = ~output_empty_w;
endmodule
|
module logic_capture_mem_axi_axi
(
// Inputs
input clk_i
,input rst_i
,input inport_valid_i
,input inport_write_i
,input [ 31:0] inport_addr_i
,input [ 3:0] inport_id_i
,input [ 7:0] inport_len_i
,input [ 1:0] inport_burst_i
,input [ 31:0] inport_wdata_i
,input [ 3:0] inport_wstrb_i
,input inport_bready_i
,input inport_rready_i
,input outport_awready_i
,input outport_wready_i
,input outport_bvalid_i
,input [ 1:0] outport_bresp_i
,input [ 3:0] outport_bid_i
,input outport_arready_i
,input outport_rvalid_i
,input [ 31:0] outport_rdata_i
,input [ 1:0] outport_rresp_i
,input [ 3:0] outport_rid_i
,input outport_rlast_i
// Outputs
,output inport_accept_o
,output inport_bvalid_o
,output [ 1:0] inport_bresp_o
,output [ 3:0] inport_bid_o
,output inport_rvalid_o
,output [ 31:0] inport_rdata_o
,output [ 1:0] inport_rresp_o
,output [ 3:0] inport_rid_o
,output inport_rlast_o
,output outport_awvalid_o
,output [ 31:0] outport_awaddr_o
,output [ 3:0] outport_awid_o
,output [ 7:0] outport_awlen_o
,output [ 1:0] outport_awburst_o
,output outport_wvalid_o
,output [ 31:0] outport_wdata_o
,output [ 3:0] outport_wstrb_o
,output outport_wlast_o
,output outport_bready_o
,output outport_arvalid_o
,output [ 31:0] outport_araddr_o
,output [ 3:0] outport_arid_o
,output [ 7:0] outport_arlen_o
,output [ 1:0] outport_arburst_o
,output outport_rready_o
);
//-------------------------------------------------------------
// Write burst tracking
//-------------------------------------------------------------
reg [7:0] req_cnt_q;
always @ (posedge clk_i )
if (rst_i)
req_cnt_q <= 8'b0;
else if (inport_valid_i && inport_write_i && inport_accept_o)
begin
if (req_cnt_q != 8'b0)
req_cnt_q <= req_cnt_q - 8'd1;
else
req_cnt_q <= inport_len_i;
end
//-------------------------------------------------------------
// Request skid buffer
//-------------------------------------------------------------
reg valid_q;
reg [83:0] buf_q;
always @ (posedge clk_i )
if (rst_i)
valid_q <= 1'b0;
else if (inport_valid_i && inport_accept_o && ((outport_awvalid_o && !outport_awready_i) || (outport_wvalid_o && !outport_wready_i) || (outport_arvalid_o && !outport_arready_i)))
valid_q <= 1'b1;
else if ((!outport_awvalid_o || outport_awready_i) && (!outport_wvalid_o || outport_wready_i) && (!outport_arvalid_o || outport_arready_i))
valid_q <= 1'b0;
wire inport_valid_w = valid_q || inport_valid_i;
wire inport_write_w = valid_q ? buf_q[0:0] : inport_write_i;
wire [ 31:0] inport_addr_w = valid_q ? buf_q[32:1] : inport_addr_i;
wire [ 3:0] inport_id_w = valid_q ? buf_q[36:33] : inport_id_i;
wire [ 7:0] inport_len_w = valid_q ? buf_q[44:37] : inport_len_i;
wire [ 1:0] inport_burst_w = valid_q ? buf_q[46:45] : inport_burst_i;
wire [ 31:0] inport_wdata_w = valid_q ? buf_q[78:47] : inport_wdata_i;
wire [ 3:0] inport_wstrb_w = valid_q ? buf_q[82:79] : inport_wstrb_i;
wire inport_wlast_w = valid_q ? buf_q[83:83] : (inport_len_i == 8'd0 && req_cnt_q == 8'd0) || (req_cnt_q == 8'd1);
always @ (posedge clk_i )
if (rst_i)
buf_q <= 84'b0;
else
buf_q <= {inport_wlast_w, inport_wstrb_w, inport_wdata_w, inport_burst_w, inport_len_w, inport_id_w, inport_addr_w, inport_write_w};
wire skid_busy_w = valid_q;
//-------------------------------------------------------------
// Write Request
//-------------------------------------------------------------
reg awvalid_q;
reg wvalid_q;
reg wlast_q;
wire wr_cmd_accepted_w = (outport_awvalid_o && outport_awready_i) || awvalid_q;
wire wr_data_accepted_w = (outport_wvalid_o && outport_wready_i) || wvalid_q;
wire wr_data_last_w = (wvalid_q & wlast_q) || (outport_wvalid_o && outport_wready_i && outport_wlast_o);
always @ (posedge clk_i )
if (rst_i)
awvalid_q <= 1'b0;
else if (outport_awvalid_o && outport_awready_i && (!wr_data_accepted_w || !wr_data_last_w))
awvalid_q <= 1'b1;
else if (wr_data_accepted_w && wr_data_last_w)
awvalid_q <= 1'b0;
always @ (posedge clk_i )
if (rst_i)
wvalid_q <= 1'b0;
else if (outport_wvalid_o && outport_wready_i && !wr_cmd_accepted_w)
wvalid_q <= 1'b1;
else if (wr_cmd_accepted_w)
wvalid_q <= 1'b0;
always @ (posedge clk_i )
if (rst_i)
wlast_q <= 1'b0;
else if (outport_wvalid_o && outport_wready_i)
wlast_q <= outport_wlast_o;
assign outport_awvalid_o = (inport_valid_w & inport_write_w & ~awvalid_q);
assign outport_awaddr_o = inport_addr_w;
assign outport_awid_o = inport_id_w;
assign outport_awlen_o = inport_len_w;
assign outport_awburst_o = inport_burst_w;
assign outport_wvalid_o = (inport_valid_w & inport_write_w & ~wvalid_q);
assign outport_wdata_o = inport_wdata_w;
assign outport_wstrb_o = inport_wstrb_w;
assign outport_wlast_o = inport_wlast_w;
assign inport_bvalid_o = outport_bvalid_i;
assign inport_bresp_o = outport_bresp_i;
assign inport_bid_o = outport_bid_i;
assign outport_bready_o = inport_bready_i;
//-------------------------------------------------------------
// Read Request
//-------------------------------------------------------------
assign outport_arvalid_o = inport_valid_w & ~inport_write_w;
assign outport_araddr_o = inport_addr_w;
assign outport_arid_o = inport_id_w;
assign outport_arlen_o = inport_len_w;
assign outport_arburst_o = inport_burst_w;
assign outport_rready_o = inport_rready_i;
assign inport_rvalid_o = outport_rvalid_i;
assign inport_rdata_o = outport_rdata_i;
assign inport_rresp_o = outport_rresp_i;
assign inport_rid_o = outport_rid_i;
assign inport_rlast_o = outport_rlast_i;
//-------------------------------------------------------------
// Accept logic
//-------------------------------------------------------------
assign inport_accept_o = !skid_busy_w &&
((outport_awvalid_o && outport_awready_i) ||
(outport_wvalid_o && outport_wready_i) ||
(outport_arvalid_o && outport_arready_i));
endmodule
|
module logic_capture_mem
(
// Inputs
input clk_i
,input rst_i
,input cfg_awvalid_i
,input [ 31:0] cfg_awaddr_i
,input cfg_wvalid_i
,input [ 31:0] cfg_wdata_i
,input [ 3:0] cfg_wstrb_i
,input cfg_bready_i
,input cfg_arvalid_i
,input [ 31:0] cfg_araddr_i
,input cfg_rready_i
,input input_valid_i
,input [ 31:0] input_data_i
,input outport_awready_i
,input outport_wready_i
,input outport_bvalid_i
,input [ 1:0] outport_bresp_i
,input [ 3:0] outport_bid_i
,input outport_arready_i
,input outport_rvalid_i
,input [ 31:0] outport_rdata_i
,input [ 1:0] outport_rresp_i
,input [ 3:0] outport_rid_i
,input outport_rlast_i
// Outputs
,output cfg_awready_o
,output cfg_wready_o
,output cfg_bvalid_o
,output [ 1:0] cfg_bresp_o
,output cfg_arready_o
,output cfg_rvalid_o
,output [ 31:0] cfg_rdata_o
,output [ 1:0] cfg_rresp_o
,output outport_awvalid_o
,output [ 31:0] outport_awaddr_o
,output [ 3:0] outport_awid_o
,output [ 7:0] outport_awlen_o
,output [ 1:0] outport_awburst_o
,output outport_wvalid_o
,output [ 31:0] outport_wdata_o
,output [ 3:0] outport_wstrb_o
,output outport_wlast_o
,output outport_bready_o
,output outport_arvalid_o
,output [ 31:0] outport_araddr_o
,output [ 3:0] outport_arid_o
,output [ 7:0] outport_arlen_o
,output [ 1:0] outport_arburst_o
,output outport_rready_o
,output cfg_clk_src_ext_o
,output [ 3:0] cfg_clk_div_o
,output [ 1:0] cfg_width_o
,output cfg_test_mode_o
,output status_enabled_o
,output status_triggered_o
,output status_overflow_o
);
//-----------------------------------------------------------------
// Core
//-----------------------------------------------------------------
wire fifo_tvalid_w;
wire [31:0] fifo_tdata_w;
wire fifo_tready_w;
wire [31:0] buffer_base_w;
wire [31:0] buffer_end_w;
wire buffer_reset_w;
wire [31:0] buffer_current_w;
wire buffer_cont_w;
wire buffer_wrapped_w;
wire buffer_full_w;
logic_capture
u_core
(
.clk_i(clk_i)
,.rst_i(rst_i)
// Config
,.cfg_awvalid_i(cfg_awvalid_i)
,.cfg_awaddr_i(cfg_awaddr_i)
,.cfg_wvalid_i(cfg_wvalid_i)
,.cfg_wdata_i(cfg_wdata_i)
,.cfg_wstrb_i(cfg_wstrb_i)
,.cfg_bready_i(cfg_bready_i)
,.cfg_arvalid_i(cfg_arvalid_i)
,.cfg_araddr_i(cfg_araddr_i)
,.cfg_rready_i(cfg_rready_i)
,.cfg_awready_o(cfg_awready_o)
,.cfg_wready_o(cfg_wready_o)
,.cfg_bvalid_o(cfg_bvalid_o)
,.cfg_bresp_o(cfg_bresp_o)
,.cfg_arready_o(cfg_arready_o)
,.cfg_rvalid_o(cfg_rvalid_o)
,.cfg_rdata_o(cfg_rdata_o)
,.cfg_rresp_o(cfg_rresp_o)
// Input capture
,.input_valid_i(input_valid_i)
,.input_data_i(input_data_i)
// Stream
,.outport_tvalid_o(fifo_tvalid_w)
,.outport_tdata_o(fifo_tdata_w)
,.outport_tstrb_o()
,.outport_tdest_o()
,.outport_tlast_o()
,.outport_tready_i(fifo_tready_w)
// Buffer Config
,.buffer_base_o(buffer_base_w)
,.buffer_end_o(buffer_end_w)
,.buffer_reset_o(buffer_reset_w)
,.buffer_cont_o(buffer_cont_w)
,.buffer_current_i(buffer_current_w)
,.buffer_wrapped_i(buffer_wrapped_w)
// Misc
,.cfg_clk_src_ext_o(cfg_clk_src_ext_o)
,.cfg_clk_div_o(cfg_clk_div_o)
,.cfg_width_o(cfg_width_o)
,.cfg_test_mode_o(cfg_test_mode_o)
// Status
,.status_enabled_o(status_enabled_o)
,.status_triggered_o(status_triggered_o)
,.status_overflow_o(status_overflow_o)
);
//-----------------------------------------------------------------
// Large block RAM based buffer
//-----------------------------------------------------------------
wire stream_tvalid_int_w;
wire stream_tvalid_w;
wire [31:0] stream_tdata_w;
wire stream_tready_w;
wire stream_tready_int_w;
wire fifo_space_w;
reg [31:0] stream_count_q;
logic_capture_mem_fifo_ram
u_buffer
(
.clk_i(clk_i)
,.rst_i(rst_i)
,.push_i(fifo_tvalid_w)
,.data_in_i(fifo_tdata_w)
,.accept_o(fifo_tready_w)
,.valid_o(stream_tvalid_int_w)
,.data_out_o(stream_tdata_w)
,.pop_i(stream_tready_int_w)
);
// Delay output to allow a bursts worth of data to accumulate
reg [3:0] stream_delay_q;
always @ (posedge clk_i )
if (rst_i)
stream_delay_q <= 4'b0;
else if (stream_delay_q != 4'd0)
stream_delay_q <= stream_delay_q - 4'd1;
else if (!stream_tvalid_int_w) // Empty
stream_delay_q <= 4'd15;
assign stream_tvalid_w = stream_tvalid_int_w && (stream_delay_q == 4'd0) && fifo_space_w;
assign stream_tready_int_w = stream_tready_w && (stream_delay_q == 4'd0) && fifo_space_w;
always @ (posedge clk_i )
if (rst_i)
stream_count_q <= 32'b0;
else if ((fifo_tvalid_w && fifo_tready_w) && !(stream_tvalid_int_w && stream_tready_int_w))
stream_count_q <= stream_count_q + 32'd1;
else if (!(fifo_tvalid_w && fifo_tready_w) && (stream_tvalid_int_w && stream_tready_int_w))
stream_count_q <= stream_count_q - 32'd1;
//-----------------------------------------------------------------
// AXI: Write logic
//-----------------------------------------------------------------
reg [31:0] write_addr_q;
wire mem_ack_w;
wire mem_was_burst_w;
reg [7:0] in_burst_q;
wire [7:0] inport_len_w;
wire [31:0] wrap_remain_w = buffer_end_w - write_addr_q;
wire can_burst_w = (write_addr_q[4:0] == 5'd0) && (stream_count_q >= 32'd8) && (wrap_remain_w > 32'd32);
always @ (posedge clk_i )
if (rst_i)
in_burst_q <= 8'b0;
else if (stream_tvalid_w && !buffer_full_w && stream_tready_w && in_burst_q != 8'd0)
in_burst_q <= in_burst_q - 8'd1;
else if (stream_tvalid_w && !buffer_full_w && stream_tready_w)
in_burst_q <= (inport_len_w != 8'd0) ? inport_len_w : 8'd0;
assign inport_len_w = (|in_burst_q) ? 8'd0 :
(can_burst_w) ? 8'd7 : 8'd0;
logic_capture_mem_track_fifo
#(
.WIDTH(1)
,.DEPTH(32)
,.ADDR_W(5)
)
u_fifo_burst_track
(
.clk_i(clk_i)
,.rst_i(rst_i)
,.push_i(stream_tvalid_w && !buffer_full_w && stream_tready_w && in_burst_q == 8'd0)
,.data_in_i(|inport_len_w)
,.accept_o(fifo_space_w)
,.valid_o()
,.data_out_o(mem_was_burst_w)
,.pop_i(mem_ack_w)
);
logic_capture_mem_axi
u_axi
(
.clk_i(clk_i)
,.rst_i(rst_i)
,.outport_awready_i(outport_awready_i)
,.outport_wready_i(outport_wready_i)
,.outport_bvalid_i(outport_bvalid_i)
,.outport_bresp_i(outport_bresp_i)
,.outport_arready_i(outport_arready_i)
,.outport_rvalid_i(outport_rvalid_i)
,.outport_rdata_i(outport_rdata_i)
,.outport_rresp_i(outport_rresp_i)
,.outport_awvalid_o(outport_awvalid_o)
,.outport_awaddr_o(outport_awaddr_o)
,.outport_wvalid_o(outport_wvalid_o)
,.outport_wdata_o(outport_wdata_o)
,.outport_wstrb_o(outport_wstrb_o)
,.outport_bready_o(outport_bready_o)
,.outport_arvalid_o(outport_arvalid_o)
,.outport_araddr_o(outport_araddr_o)
,.outport_rready_o(outport_rready_o)
,.outport_awid_o(outport_awid_o)
,.outport_awlen_o(outport_awlen_o)
,.outport_awburst_o(outport_awburst_o)
,.outport_wlast_o(outport_wlast_o)
,.outport_arid_o(outport_arid_o)
,.outport_arlen_o(outport_arlen_o)
,.outport_arburst_o(outport_arburst_o)
,.outport_bid_i(outport_bid_i)
,.outport_rid_i(outport_rid_i)
,.outport_rlast_i(outport_rlast_i)
,.inport_wr_i({4{stream_tvalid_w & ~buffer_full_w}})
,.inport_rd_i(1'b0)
,.inport_len_i(inport_len_w)
,.inport_addr_i(write_addr_q)
,.inport_write_data_i(stream_tdata_w)
,.inport_accept_o(stream_tready_w)
,.inport_ack_o(mem_ack_w)
,.inport_error_o()
,.inport_read_data_o()
);
//-----------------------------------------------------------------
// Buffer Full
//-----------------------------------------------------------------
reg buffer_full_q;
always @ (posedge clk_i )
if (rst_i)
buffer_full_q <= 1'b0;
else if (buffer_reset_w)
buffer_full_q <= 1'b0;
else if (stream_tvalid_w && stream_tready_w && !buffer_cont_w && (write_addr_q == buffer_end_w))
buffer_full_q <= 1'b1;
assign buffer_full_w = buffer_full_q;
//-----------------------------------------------------------------
// Buffer Wrapped
//-----------------------------------------------------------------
reg buffer_wrap_q;
always @ (posedge clk_i )
if (rst_i)
buffer_wrap_q <= 1'b0;
else if (buffer_reset_w)
buffer_wrap_q <= 1'b0;
else if (stream_tvalid_w && stream_tready_w && buffer_cont_w && (write_addr_q == buffer_end_w))
buffer_wrap_q <= 1'b1;
assign buffer_wrapped_w = buffer_wrap_q;
//-----------------------------------------------------------------
// Write Address
//-----------------------------------------------------------------
always @ (posedge clk_i )
if (rst_i)
write_addr_q <= 32'b0;
else if (buffer_reset_w)
write_addr_q <= buffer_base_w;
else if (stream_tvalid_w && stream_tready_w && !buffer_full_w)
begin
if (write_addr_q == buffer_end_w)
write_addr_q <= buffer_base_w;
else
write_addr_q <= write_addr_q + 32'd4;
end
//-----------------------------------------------------------------
// Read pointer (based on completed writes)
//-----------------------------------------------------------------
reg [31:0] buffer_current_q;
always @ (posedge clk_i )
if (rst_i)
buffer_current_q <= 32'b0;
else if (buffer_reset_w)
buffer_current_q <= buffer_base_w;
// Control word writes actually occur in IDLE...
else if (mem_ack_w && (buffer_cont_w || buffer_current_q != buffer_end_w))
begin
if (buffer_current_q == buffer_end_w)
buffer_current_q <= buffer_base_w;
else
buffer_current_q <= buffer_current_q + (mem_was_burst_w ? 32'd32 : 32'd4);
end
assign buffer_current_w = buffer_current_q;
endmodule
|
module logic_capture_mem_axi
//-----------------------------------------------------------------
// Params
//-----------------------------------------------------------------
#(
parameter AXI_ID = 0
)
//-----------------------------------------------------------------
// Ports
//-----------------------------------------------------------------
(
// Inputs
input clk_i
,input rst_i
,input outport_awready_i
,input outport_wready_i
,input outport_bvalid_i
,input [ 1:0] outport_bresp_i
,input [ 3:0] outport_bid_i
,input outport_arready_i
,input outport_rvalid_i
,input [ 31:0] outport_rdata_i
,input [ 1:0] outport_rresp_i
,input [ 3:0] outport_rid_i
,input outport_rlast_i
,input [ 3:0] inport_wr_i
,input inport_rd_i
,input [ 7:0] inport_len_i
,input [ 31:0] inport_addr_i
,input [ 31:0] inport_write_data_i
// Outputs
,output outport_awvalid_o
,output [ 31:0] outport_awaddr_o
,output [ 3:0] outport_awid_o
,output [ 7:0] outport_awlen_o
,output [ 1:0] outport_awburst_o
,output outport_wvalid_o
,output [ 31:0] outport_wdata_o
,output [ 3:0] outport_wstrb_o
,output outport_wlast_o
,output outport_bready_o
,output outport_arvalid_o
,output [ 31:0] outport_araddr_o
,output [ 3:0] outport_arid_o
,output [ 7:0] outport_arlen_o
,output [ 1:0] outport_arburst_o
,output outport_rready_o
,output inport_accept_o
,output inport_ack_o
,output inport_error_o
,output [ 31:0] inport_read_data_o
);
//-------------------------------------------------------------
// Request FIFO
//-------------------------------------------------------------
wire bvalid_w;
wire rvalid_w;
wire [1:0] bresp_w;
wire [1:0] rresp_w;
wire accept_w;
// Accepts from both FIFOs
wire res_accept_w;
wire req_accept_w;
wire res_valid_w;
wire req_valid_w;
wire [77-1:0] req_w;
// Push on transaction and other FIFO not full
wire req_push_w = (inport_rd_i || inport_wr_i != 4'b0);
wire [77-1:0] req_data_in_w = {inport_len_i, inport_rd_i, inport_wr_i, inport_write_data_i, inport_addr_i};
logic_capture_mem_axi_fifo
#(
.ADDR_W(3),
.DEPTH(8),
.WIDTH(32+32+8+4+1)
)
u_req
(
.clk_i(clk_i),
.rst_i(rst_i),
// Input side
.data_in_i(req_data_in_w),
.push_i(req_push_w),
.accept_o(req_accept_w),
// Outputs
.valid_o(req_valid_w),
.data_out_o(req_w),
.pop_i(accept_w)
);
wire req_can_issue_w = req_valid_w & res_accept_w;
wire req_is_read_w = (req_can_issue_w ? req_w[68] : 1'b0);
wire req_is_write_w = (req_can_issue_w ? ~req_w[68] : 1'b0);
wire [7:0] req_len_w = req_w[76:69];
assign inport_accept_o = req_accept_w;
assign inport_ack_o = bvalid_w || rvalid_w;
assign inport_error_o = bvalid_w ? (bresp_w != 2'b0) : (rresp_w != 2'b0);
//-------------------------------------------------------------
// Write burst tracking
//-------------------------------------------------------------
reg [7:0] req_cnt_q;
always @ (posedge clk_i )
if (rst_i)
req_cnt_q <= 8'b0;
// First cycle of write burst
else if (req_is_write_w && req_cnt_q == 8'd0 && req_len_w != 8'd0 && accept_w)
req_cnt_q <= req_len_w - 8'd1;
else if (req_cnt_q != 8'd0 && req_is_write_w && accept_w)
req_cnt_q <= req_cnt_q - 8'd1;
wire req_last_w = (req_is_write_w && req_len_w == 8'd0 && req_cnt_q == 8'd0);
//-------------------------------------------------------------
// Response tracking
//-------------------------------------------------------------
// Push on transaction and other FIFO not full
wire res_push_w = (req_is_write_w && req_last_w && accept_w) || (req_is_read_w && accept_w);
// Pop on last tick of burst
wire resp_pop_w = outport_bvalid_i || (outport_rvalid_i ? outport_rlast_i : 1'b0);
reg [4:0] resp_outstanding_q;
always @ (posedge clk_i )
if (rst_i)
resp_outstanding_q <= 5'b0;
// Count up
else if ((res_push_w & res_accept_w) & ~(resp_pop_w & res_valid_w))
resp_outstanding_q <= resp_outstanding_q + 5'd1;
// Count down
else if (~(res_push_w & res_accept_w) & (resp_pop_w & res_valid_w))
resp_outstanding_q <= resp_outstanding_q - 5'd1;
assign res_valid_w = (resp_outstanding_q != 5'd0);
assign res_accept_w = (resp_outstanding_q != 5'd16);
//-------------------------------------------------------------
// AXI widget
//-------------------------------------------------------------
logic_capture_mem_axi_axi
u_axi
(
.clk_i(clk_i),
.rst_i(rst_i),
.inport_valid_i(req_can_issue_w),
.inport_write_i(req_is_write_w),
.inport_wdata_i(req_w[63:32]),
.inport_wstrb_i(req_w[67:64]),
.inport_addr_i({req_w[31:2], 2'b0}),
.inport_id_i(AXI_ID),
.inport_len_i(req_len_w),
.inport_burst_i(2'b01),
.inport_accept_o(accept_w),
.inport_bready_i(1'b1),
.inport_rready_i(1'b1),
.inport_bvalid_o(bvalid_w),
.inport_bresp_o(bresp_w),
.inport_bid_o(),
.inport_rvalid_o(rvalid_w),
.inport_rdata_o(inport_read_data_o),
.inport_rresp_o(rresp_w),
.inport_rid_o(),
.inport_rlast_o(),
.outport_awvalid_o(outport_awvalid_o),
.outport_awaddr_o(outport_awaddr_o),
.outport_awid_o(outport_awid_o),
.outport_awlen_o(outport_awlen_o),
.outport_awburst_o(outport_awburst_o),
.outport_wvalid_o(outport_wvalid_o),
.outport_wdata_o(outport_wdata_o),
.outport_wstrb_o(outport_wstrb_o),
.outport_wlast_o(outport_wlast_o),
.outport_bready_o(outport_bready_o),
.outport_arvalid_o(outport_arvalid_o),
.outport_araddr_o(outport_araddr_o),
.outport_arid_o(outport_arid_o),
.outport_arlen_o(outport_arlen_o),
.outport_arburst_o(outport_arburst_o),
.outport_rready_o(outport_rready_o),
.outport_awready_i(outport_awready_i),
.outport_wready_i(outport_wready_i),
.outport_bvalid_i(outport_bvalid_i),
.outport_bresp_i(outport_bresp_i),
.outport_bid_i(outport_bid_i),
.outport_arready_i(outport_arready_i),
.outport_rvalid_i(outport_rvalid_i),
.outport_rdata_i(outport_rdata_i),
.outport_rresp_i(outport_rresp_i),
.outport_rid_i(outport_rid_i),
.outport_rlast_i(outport_rlast_i)
);
endmodule
|
module logic_capture_mem_axi_fifo
//-----------------------------------------------------------------
// Params
//-----------------------------------------------------------------
#(
parameter WIDTH = 8,
parameter DEPTH = 4,
parameter ADDR_W = 2
)
//-----------------------------------------------------------------
// Ports
//-----------------------------------------------------------------
(
// Inputs
input clk_i
,input rst_i
,input [WIDTH-1:0] data_in_i
,input push_i
,input pop_i
// Outputs
,output [WIDTH-1:0] data_out_o
,output accept_o
,output valid_o
);
//-----------------------------------------------------------------
// Local Params
//-----------------------------------------------------------------
localparam COUNT_W = ADDR_W + 1;
//-----------------------------------------------------------------
// Registers
//-----------------------------------------------------------------
reg [WIDTH-1:0] ram_q[DEPTH-1:0];
reg [ADDR_W-1:0] rd_ptr_q;
reg [ADDR_W-1:0] wr_ptr_q;
reg [COUNT_W-1:0] count_q;
//-----------------------------------------------------------------
// Sequential
//-----------------------------------------------------------------
always @ (posedge clk_i )
if (rst_i)
begin
count_q <= {(COUNT_W) {1'b0}};
rd_ptr_q <= {(ADDR_W) {1'b0}};
wr_ptr_q <= {(ADDR_W) {1'b0}};
end
else
begin
// Push
if (push_i & accept_o)
begin
ram_q[wr_ptr_q] <= data_in_i;
wr_ptr_q <= wr_ptr_q + 1;
end
// Pop
if (pop_i & valid_o)
rd_ptr_q <= rd_ptr_q + 1;
// Count up
if ((push_i & accept_o) & ~(pop_i & valid_o))
count_q <= count_q + 1;
// Count down
else if (~(push_i & accept_o) & (pop_i & valid_o))
count_q <= count_q - 1;
end
//-------------------------------------------------------------------
// Combinatorial
//-------------------------------------------------------------------
/* verilator lint_off WIDTH */
assign valid_o = (count_q != 0);
assign accept_o = (count_q != DEPTH);
/* verilator lint_on WIDTH */
assign data_out_o = ram_q[rd_ptr_q];
endmodule
|
module logic_capture_fifo
(
// Inputs
input clk_i
,input rst_i
,input [ 31:0] data_in_i
,input push_i
,input pop_i
// Outputs
,output [ 31:0] data_out_o
,output accept_o
,output valid_o
);
//-----------------------------------------------------------------
// Registers
//-----------------------------------------------------------------
reg [8:0] rd_ptr_q;
reg [8:0] wr_ptr_q;
//-----------------------------------------------------------------
// Write Side
//-----------------------------------------------------------------
wire [8:0] write_next_w = wr_ptr_q + 9'd1;
wire full_w = (write_next_w == rd_ptr_q);
always @ (posedge clk_i )
if (rst_i)
wr_ptr_q <= 9'b0;
// Push
else if (push_i & !full_w)
wr_ptr_q <= write_next_w;
//-----------------------------------------------------------------
// Read Side
//-----------------------------------------------------------------
wire read_ok_w = (wr_ptr_q != rd_ptr_q);
reg rd_q;
always @ (posedge clk_i )
if (rst_i)
rd_q <= 1'b0;
else
rd_q <= read_ok_w;
always @ (posedge clk_i )
if (rst_i)
rd_ptr_q <= 9'b0;
// Read address increment
else if (read_ok_w && ((!valid_o) || (valid_o && pop_i)))
rd_ptr_q <= rd_ptr_q + 9'd1;
//-------------------------------------------------------------------
// Read Skid Buffer
//-------------------------------------------------------------------
reg rd_skid_q;
reg [31:0] rd_skid_data_q;
always @ (posedge clk_i )
if (rst_i)
begin
rd_skid_q <= 1'b0;
rd_skid_data_q <= 32'b0;
end
else if (valid_o && !pop_i)
begin
rd_skid_q <= 1'b1;
rd_skid_data_q <= data_out_o;
end
else
begin
rd_skid_q <= 1'b0;
rd_skid_data_q <= 32'b0;
end
//-------------------------------------------------------------------
// Combinatorial
//-------------------------------------------------------------------
assign valid_o = rd_skid_q | rd_q;
assign accept_o = !full_w;
//-------------------------------------------------------------------
// Dual port RAM
//-------------------------------------------------------------------
wire [31:0] data_out_w;
logic_capture_fifo_dp_512_9
u_ram
(
// Inputs
.clk0_i(clk_i),
.rst0_i(rst_i),
.clk1_i(clk_i),
.rst1_i(rst_i),
// Write side
.addr0_i(wr_ptr_q),
.wr0_i(push_i & accept_o),
.data0_i(data_in_i),
.data0_o(),
// Read side
.addr1_i(rd_ptr_q),
.data1_i(32'b0),
.wr1_i(1'b0),
.data1_o(data_out_w)
);
assign data_out_o = rd_skid_q ? rd_skid_data_q : data_out_w;
endmodule
|
module logic_capture_fifo_dp_512_9
(
// Inputs
input clk0_i
,input rst0_i
,input [ 8:0] addr0_i
,input [ 31:0] data0_i
,input wr0_i
,input clk1_i
,input rst1_i
,input [ 8:0] addr1_i
,input [ 31:0] data1_i
,input wr1_i
// Outputs
,output [ 31:0] data0_o
,output [ 31:0] data1_o
);
/* verilator lint_off MULTIDRIVEN */
reg [31:0] ram [511:0] /*verilator public*/;
/* verilator lint_on MULTIDRIVEN */
reg [31:0] ram_read0_q;
reg [31:0] ram_read1_q;
// Synchronous write
always @ (posedge clk0_i)
begin
if (wr0_i)
ram[addr0_i] <= data0_i;
ram_read0_q <= ram[addr0_i];
end
always @ (posedge clk1_i)
begin
if (wr1_i)
ram[addr1_i] <= data1_i;
ram_read1_q <= ram[addr1_i];
end
assign data0_o = ram_read0_q;
assign data1_o = ram_read1_q;
endmodule
|
module logic_capture_mem_fifo_ram
(
// Inputs
input clk_i
,input rst_i
,input [ 31:0] data_in_i
,input push_i
,input pop_i
// Outputs
,output [ 31:0] data_out_o
,output accept_o
,output valid_o
);
//-----------------------------------------------------------------
// Registers
//-----------------------------------------------------------------
reg [10:0] rd_ptr_q;
reg [10:0] wr_ptr_q;
//-----------------------------------------------------------------
// Write Side
//-----------------------------------------------------------------
wire [10:0] write_next_w = wr_ptr_q + 11'd1;
wire full_w = (write_next_w == rd_ptr_q);
always @ (posedge clk_i )
if (rst_i)
wr_ptr_q <= 11'b0;
// Push
else if (push_i & !full_w)
wr_ptr_q <= write_next_w;
//-----------------------------------------------------------------
// Read Side
//-----------------------------------------------------------------
wire read_ok_w = (wr_ptr_q != rd_ptr_q);
reg rd_q;
always @ (posedge clk_i )
if (rst_i)
rd_q <= 1'b0;
else
rd_q <= read_ok_w;
always @ (posedge clk_i )
if (rst_i)
rd_ptr_q <= 11'b0;
// Read address increment
else if (read_ok_w && ((!valid_o) || (valid_o && pop_i)))
rd_ptr_q <= rd_ptr_q + 11'd1;
//-------------------------------------------------------------------
// Read Skid Buffer
//-------------------------------------------------------------------
reg rd_skid_q;
reg [31:0] rd_skid_data_q;
always @ (posedge clk_i )
if (rst_i)
begin
rd_skid_q <= 1'b0;
rd_skid_data_q <= 32'b0;
end
else if (valid_o && !pop_i)
begin
rd_skid_q <= 1'b1;
rd_skid_data_q <= data_out_o;
end
else
begin
rd_skid_q <= 1'b0;
rd_skid_data_q <= 32'b0;
end
//-------------------------------------------------------------------
// Combinatorial
//-------------------------------------------------------------------
assign valid_o = rd_skid_q | rd_q;
assign accept_o = !full_w;
//-------------------------------------------------------------------
// Dual port RAM
//-------------------------------------------------------------------
wire [31:0] data_out_w;
logic_capture_mem_fifo_ram_ram_dp_16384_11
u_ram
(
// Inputs
.clk0_i(clk_i),
.rst0_i(rst_i),
.clk1_i(clk_i),
.rst1_i(rst_i),
// Write side
.addr0_i(wr_ptr_q),
.wr0_i(push_i & accept_o),
.data0_i(data_in_i),
.data0_o(),
// Read side
.addr1_i(rd_ptr_q),
.data1_i(32'b0),
.wr1_i(1'b0),
.data1_o(data_out_w)
);
assign data_out_o = rd_skid_q ? rd_skid_data_q : data_out_w;
//-------------------------------------------------------------------
// Level
//-------------------------------------------------------------------
endmodule
|
module logic_capture
(
// Inputs
input clk_i
,input rst_i
,input cfg_awvalid_i
,input [31:0] cfg_awaddr_i
,input cfg_wvalid_i
,input [31:0] cfg_wdata_i
,input [3:0] cfg_wstrb_i
,input cfg_bready_i
,input cfg_arvalid_i
,input [31:0] cfg_araddr_i
,input cfg_rready_i
,input input_valid_i
,input [31:0] input_data_i
,input outport_tready_i
,input [31:0] buffer_current_i
,input buffer_wrapped_i
// Outputs
,output cfg_awready_o
,output cfg_wready_o
,output cfg_bvalid_o
,output [1:0] cfg_bresp_o
,output cfg_arready_o
,output cfg_rvalid_o
,output [31:0] cfg_rdata_o
,output [1:0] cfg_rresp_o
,output outport_tvalid_o
,output [31:0] outport_tdata_o
,output [3:0] outport_tstrb_o
,output [3:0] outport_tdest_o
,output outport_tlast_o
,output [31:0] buffer_base_o
,output [31:0] buffer_end_o
,output buffer_reset_o
,output buffer_cont_o
,output cfg_clk_src_ext_o
,output [3:0] cfg_clk_div_o
,output [1:0] cfg_width_o
,output cfg_test_mode_o
,output status_enabled_o
,output status_triggered_o
,output status_overflow_o
);
//-----------------------------------------------------------------
// Write address / data split
//-----------------------------------------------------------------
// Address but no data ready
reg awvalid_q;
// Data but no data ready
reg wvalid_q;
wire wr_cmd_accepted_w = (cfg_awvalid_i && cfg_awready_o) || awvalid_q;
wire wr_data_accepted_w = (cfg_wvalid_i && cfg_wready_o) || wvalid_q;
always @ (posedge clk_i )
if (rst_i)
awvalid_q <= 1'b0;
else if (cfg_awvalid_i && cfg_awready_o && !wr_data_accepted_w)
awvalid_q <= 1'b1;
else if (wr_data_accepted_w)
awvalid_q <= 1'b0;
always @ (posedge clk_i )
if (rst_i)
wvalid_q <= 1'b0;
else if (cfg_wvalid_i && cfg_wready_o && !wr_cmd_accepted_w)
wvalid_q <= 1'b1;
else if (wr_cmd_accepted_w)
wvalid_q <= 1'b0;
//-----------------------------------------------------------------
// Capture address (for delayed data)
//-----------------------------------------------------------------
reg [7:0] wr_addr_q;
always @ (posedge clk_i )
if (rst_i)
wr_addr_q <= 8'b0;
else if (cfg_awvalid_i && cfg_awready_o)
wr_addr_q <= cfg_awaddr_i[7:0];
wire [7:0] wr_addr_w = awvalid_q ? wr_addr_q : cfg_awaddr_i[7:0];
//-----------------------------------------------------------------
// Retime write data
//-----------------------------------------------------------------
reg [31:0] wr_data_q;
always @ (posedge clk_i )
if (rst_i)
wr_data_q <= 32'b0;
else if (cfg_wvalid_i && cfg_wready_o)
wr_data_q <= cfg_wdata_i;
//-----------------------------------------------------------------
// Request Logic
//-----------------------------------------------------------------
wire read_en_w = cfg_arvalid_i & cfg_arready_o;
wire write_en_w = wr_cmd_accepted_w && wr_data_accepted_w;
//-----------------------------------------------------------------
// Accept Logic
//-----------------------------------------------------------------
assign cfg_arready_o = ~cfg_rvalid_o;
assign cfg_awready_o = ~cfg_bvalid_o && ~cfg_arvalid_i && ~awvalid_q;
assign cfg_wready_o = ~cfg_bvalid_o && ~cfg_arvalid_i && ~wvalid_q;
//-----------------------------------------------------------------
// Register la_buffer_cfg
//-----------------------------------------------------------------
reg la_buffer_cfg_wr_q;
always @ (posedge clk_i )
if (rst_i)
la_buffer_cfg_wr_q <= 1'b0;
else if (write_en_w && (wr_addr_w[7:0] == `LA_BUFFER_CFG))
la_buffer_cfg_wr_q <= 1'b1;
else
la_buffer_cfg_wr_q <= 1'b0;
// la_buffer_cfg_cont [internal]
reg la_buffer_cfg_cont_q;
always @ (posedge clk_i )
if (rst_i)
la_buffer_cfg_cont_q <= 1'd`LA_BUFFER_CFG_CONT_DEFAULT;
else if (write_en_w && (wr_addr_w[7:0] == `LA_BUFFER_CFG))
la_buffer_cfg_cont_q <= cfg_wdata_i[`LA_BUFFER_CFG_CONT_R];
wire la_buffer_cfg_cont_out_w = la_buffer_cfg_cont_q;
// la_buffer_cfg_test_mode [internal]
reg la_buffer_cfg_test_mode_q;
always @ (posedge clk_i )
if (rst_i)
la_buffer_cfg_test_mode_q <= 1'd`LA_BUFFER_CFG_TEST_MODE_DEFAULT;
else if (write_en_w && (wr_addr_w[7:0] == `LA_BUFFER_CFG))
la_buffer_cfg_test_mode_q <= cfg_wdata_i[`LA_BUFFER_CFG_TEST_MODE_R];
wire la_buffer_cfg_test_mode_out_w = la_buffer_cfg_test_mode_q;
// la_buffer_cfg_width [internal]
reg [1:0] la_buffer_cfg_width_q;
always @ (posedge clk_i )
if (rst_i)
la_buffer_cfg_width_q <= 2'd`LA_BUFFER_CFG_WIDTH_DEFAULT;
else if (write_en_w && (wr_addr_w[7:0] == `LA_BUFFER_CFG))
la_buffer_cfg_width_q <= cfg_wdata_i[`LA_BUFFER_CFG_WIDTH_R];
wire [1:0] la_buffer_cfg_width_out_w = la_buffer_cfg_width_q;
// la_buffer_cfg_clk_div [internal]
reg [3:0] la_buffer_cfg_clk_div_q;
always @ (posedge clk_i )
if (rst_i)
la_buffer_cfg_clk_div_q <= 4'd`LA_BUFFER_CFG_CLK_DIV_DEFAULT;
else if (write_en_w && (wr_addr_w[7:0] == `LA_BUFFER_CFG))
la_buffer_cfg_clk_div_q <= cfg_wdata_i[`LA_BUFFER_CFG_CLK_DIV_R];
wire [3:0] la_buffer_cfg_clk_div_out_w = la_buffer_cfg_clk_div_q;
// la_buffer_cfg_clk_src [internal]
reg la_buffer_cfg_clk_src_q;
always @ (posedge clk_i )
if (rst_i)
la_buffer_cfg_clk_src_q <= 1'd`LA_BUFFER_CFG_CLK_SRC_DEFAULT;
else if (write_en_w && (wr_addr_w[7:0] == `LA_BUFFER_CFG))
la_buffer_cfg_clk_src_q <= cfg_wdata_i[`LA_BUFFER_CFG_CLK_SRC_R];
wire la_buffer_cfg_clk_src_out_w = la_buffer_cfg_clk_src_q;
// la_buffer_cfg_enabled [internal]
reg la_buffer_cfg_enabled_q;
always @ (posedge clk_i )
if (rst_i)
la_buffer_cfg_enabled_q <= 1'd`LA_BUFFER_CFG_ENABLED_DEFAULT;
else if (write_en_w && (wr_addr_w[7:0] == `LA_BUFFER_CFG))
la_buffer_cfg_enabled_q <= cfg_wdata_i[`LA_BUFFER_CFG_ENABLED_R];
wire la_buffer_cfg_enabled_out_w = la_buffer_cfg_enabled_q;
//-----------------------------------------------------------------
// Register la_buffer_sts
//-----------------------------------------------------------------
reg la_buffer_sts_wr_q;
always @ (posedge clk_i )
if (rst_i)
la_buffer_sts_wr_q <= 1'b0;
else if (write_en_w && (wr_addr_w[7:0] == `LA_BUFFER_STS))
la_buffer_sts_wr_q <= 1'b1;
else
la_buffer_sts_wr_q <= 1'b0;
//-----------------------------------------------------------------
// Register la_buffer_base
//-----------------------------------------------------------------
reg la_buffer_base_wr_q;
always @ (posedge clk_i )
if (rst_i)
la_buffer_base_wr_q <= 1'b0;
else if (write_en_w && (wr_addr_w[7:0] == `LA_BUFFER_BASE))
la_buffer_base_wr_q <= 1'b1;
else
la_buffer_base_wr_q <= 1'b0;
// la_buffer_base_addr [internal]
reg [31:0] la_buffer_base_addr_q;
always @ (posedge clk_i )
if (rst_i)
la_buffer_base_addr_q <= 32'd`LA_BUFFER_BASE_ADDR_DEFAULT;
else if (write_en_w && (wr_addr_w[7:0] == `LA_BUFFER_BASE))
la_buffer_base_addr_q <= cfg_wdata_i[`LA_BUFFER_BASE_ADDR_R];
wire [31:0] la_buffer_base_addr_out_w = la_buffer_base_addr_q;
//-----------------------------------------------------------------
// Register la_buffer_end
//-----------------------------------------------------------------
reg la_buffer_end_wr_q;
always @ (posedge clk_i )
if (rst_i)
la_buffer_end_wr_q <= 1'b0;
else if (write_en_w && (wr_addr_w[7:0] == `LA_BUFFER_END))
la_buffer_end_wr_q <= 1'b1;
else
la_buffer_end_wr_q <= 1'b0;
// la_buffer_end_addr [internal]
reg [31:0] la_buffer_end_addr_q;
always @ (posedge clk_i )
if (rst_i)
la_buffer_end_addr_q <= 32'd`LA_BUFFER_END_ADDR_DEFAULT;
else if (write_en_w && (wr_addr_w[7:0] == `LA_BUFFER_END))
la_buffer_end_addr_q <= cfg_wdata_i[`LA_BUFFER_END_ADDR_R];
wire [31:0] la_buffer_end_addr_out_w = la_buffer_end_addr_q;
//-----------------------------------------------------------------
// Register la_buffer_current
//-----------------------------------------------------------------
reg la_buffer_current_wr_q;
always @ (posedge clk_i )
if (rst_i)
la_buffer_current_wr_q <= 1'b0;
else if (write_en_w && (wr_addr_w[7:0] == `LA_BUFFER_CURRENT))
la_buffer_current_wr_q <= 1'b1;
else
la_buffer_current_wr_q <= 1'b0;
//-----------------------------------------------------------------
// Register la_buffer_samples
//-----------------------------------------------------------------
reg la_buffer_samples_wr_q;
always @ (posedge clk_i )
if (rst_i)
la_buffer_samples_wr_q <= 1'b0;
else if (write_en_w && (wr_addr_w[7:0] == `LA_BUFFER_SAMPLES))
la_buffer_samples_wr_q <= 1'b1;
else
la_buffer_samples_wr_q <= 1'b0;
//-----------------------------------------------------------------
// Register la_buffer_trig_enable
//-----------------------------------------------------------------
reg la_buffer_trig_enable_wr_q;
always @ (posedge clk_i )
if (rst_i)
la_buffer_trig_enable_wr_q <= 1'b0;
else if (write_en_w && (wr_addr_w[7:0] == `LA_BUFFER_TRIG_ENABLE))
la_buffer_trig_enable_wr_q <= 1'b1;
else
la_buffer_trig_enable_wr_q <= 1'b0;
// la_buffer_trig_enable_value [internal]
reg [31:0] la_buffer_trig_enable_value_q;
always @ (posedge clk_i )
if (rst_i)
la_buffer_trig_enable_value_q <= 32'd`LA_BUFFER_TRIG_ENABLE_VALUE_DEFAULT;
else if (write_en_w && (wr_addr_w[7:0] == `LA_BUFFER_TRIG_ENABLE))
la_buffer_trig_enable_value_q <= cfg_wdata_i[`LA_BUFFER_TRIG_ENABLE_VALUE_R];
wire [31:0] la_buffer_trig_enable_value_out_w = la_buffer_trig_enable_value_q;
//-----------------------------------------------------------------
// Register la_buffer_trig_sense
//-----------------------------------------------------------------
reg la_buffer_trig_sense_wr_q;
always @ (posedge clk_i )
if (rst_i)
la_buffer_trig_sense_wr_q <= 1'b0;
else if (write_en_w && (wr_addr_w[7:0] == `LA_BUFFER_TRIG_SENSE))
la_buffer_trig_sense_wr_q <= 1'b1;
else
la_buffer_trig_sense_wr_q <= 1'b0;
// la_buffer_trig_sense_value [internal]
reg [31:0] la_buffer_trig_sense_value_q;
always @ (posedge clk_i )
if (rst_i)
la_buffer_trig_sense_value_q <= 32'd`LA_BUFFER_TRIG_SENSE_VALUE_DEFAULT;
else if (write_en_w && (wr_addr_w[7:0] == `LA_BUFFER_TRIG_SENSE))
la_buffer_trig_sense_value_q <= cfg_wdata_i[`LA_BUFFER_TRIG_SENSE_VALUE_R];
wire [31:0] la_buffer_trig_sense_value_out_w = la_buffer_trig_sense_value_q;
//-----------------------------------------------------------------
// Register la_buffer_trig_level
//-----------------------------------------------------------------
reg la_buffer_trig_level_wr_q;
always @ (posedge clk_i )
if (rst_i)
la_buffer_trig_level_wr_q <= 1'b0;
else if (write_en_w && (wr_addr_w[7:0] == `LA_BUFFER_TRIG_LEVEL))
la_buffer_trig_level_wr_q <= 1'b1;
else
la_buffer_trig_level_wr_q <= 1'b0;
// la_buffer_trig_level_value [internal]
reg [31:0] la_buffer_trig_level_value_q;
always @ (posedge clk_i )
if (rst_i)
la_buffer_trig_level_value_q <= 32'd`LA_BUFFER_TRIG_LEVEL_VALUE_DEFAULT;
else if (write_en_w && (wr_addr_w[7:0] == `LA_BUFFER_TRIG_LEVEL))
la_buffer_trig_level_value_q <= cfg_wdata_i[`LA_BUFFER_TRIG_LEVEL_VALUE_R];
wire [31:0] la_buffer_trig_level_value_out_w = la_buffer_trig_level_value_q;
wire [5:0] la_buffer_sts_num_channels_in_w;
wire la_buffer_sts_data_loss_in_w;
wire la_buffer_sts_wrapped_in_w;
wire la_buffer_sts_trig_in_w;
wire [31:0] la_buffer_current_addr_in_w;
wire [31:0] la_buffer_samples_count_in_w;
//-----------------------------------------------------------------
// Read mux
//-----------------------------------------------------------------
reg [31:0] data_r;
always @ *
begin
data_r = 32'b0;
case (cfg_araddr_i[7:0])
`LA_BUFFER_CFG:
begin
data_r[`LA_BUFFER_CFG_CONT_R] = la_buffer_cfg_cont_q;
data_r[`LA_BUFFER_CFG_TEST_MODE_R] = la_buffer_cfg_test_mode_q;
data_r[`LA_BUFFER_CFG_WIDTH_R] = la_buffer_cfg_width_q;
data_r[`LA_BUFFER_CFG_CLK_DIV_R] = la_buffer_cfg_clk_div_q;
data_r[`LA_BUFFER_CFG_CLK_SRC_R] = la_buffer_cfg_clk_src_q;
data_r[`LA_BUFFER_CFG_ENABLED_R] = la_buffer_cfg_enabled_q;
end
`LA_BUFFER_STS:
begin
data_r[`LA_BUFFER_STS_NUM_CHANNELS_R] = la_buffer_sts_num_channels_in_w;
data_r[`LA_BUFFER_STS_DATA_LOSS_R] = la_buffer_sts_data_loss_in_w;
data_r[`LA_BUFFER_STS_WRAPPED_R] = la_buffer_sts_wrapped_in_w;
data_r[`LA_BUFFER_STS_TRIG_R] = la_buffer_sts_trig_in_w;
end
`LA_BUFFER_BASE:
begin
data_r[`LA_BUFFER_BASE_ADDR_R] = la_buffer_base_addr_q;
end
`LA_BUFFER_END:
begin
data_r[`LA_BUFFER_END_ADDR_R] = la_buffer_end_addr_q;
end
`LA_BUFFER_CURRENT:
begin
data_r[`LA_BUFFER_CURRENT_ADDR_R] = la_buffer_current_addr_in_w;
end
`LA_BUFFER_SAMPLES:
begin
data_r[`LA_BUFFER_SAMPLES_COUNT_R] = la_buffer_samples_count_in_w;
end
`LA_BUFFER_TRIG_ENABLE:
begin
data_r[`LA_BUFFER_TRIG_ENABLE_VALUE_R] = la_buffer_trig_enable_value_q;
end
`LA_BUFFER_TRIG_SENSE:
begin
data_r[`LA_BUFFER_TRIG_SENSE_VALUE_R] = la_buffer_trig_sense_value_q;
end
`LA_BUFFER_TRIG_LEVEL:
begin
data_r[`LA_BUFFER_TRIG_LEVEL_VALUE_R] = la_buffer_trig_level_value_q;
end
default :
data_r = 32'b0;
endcase
end
//-----------------------------------------------------------------
// RVALID
//-----------------------------------------------------------------
reg rvalid_q;
always @ (posedge clk_i )
if (rst_i)
rvalid_q <= 1'b0;
else if (read_en_w)
rvalid_q <= 1'b1;
else if (cfg_rready_i)
rvalid_q <= 1'b0;
assign cfg_rvalid_o = rvalid_q;
//-----------------------------------------------------------------
// Retime read response
//-----------------------------------------------------------------
reg [31:0] rd_data_q;
always @ (posedge clk_i )
if (rst_i)
rd_data_q <= 32'b0;
else if (!cfg_rvalid_o || cfg_rready_i)
rd_data_q <= data_r;
assign cfg_rdata_o = rd_data_q;
assign cfg_rresp_o = 2'b0;
//-----------------------------------------------------------------
// BVALID
//-----------------------------------------------------------------
reg bvalid_q;
always @ (posedge clk_i )
if (rst_i)
bvalid_q <= 1'b0;
else if (write_en_w)
bvalid_q <= 1'b1;
else if (cfg_bready_i)
bvalid_q <= 1'b0;
assign cfg_bvalid_o = bvalid_q;
assign cfg_bresp_o = 2'b0;
parameter NUM_CHANNELS = 16;
localparam WIDTH_16BIT = 2'd0;
localparam WIDTH_24BIT = 2'd1;
localparam WIDTH_32BIT = 2'd2;
//-----------------------------------------------------------------
// Enable detect
//-----------------------------------------------------------------
wire cfg_enabled_w = la_buffer_cfg_enabled_out_w;
reg cfg_enabled_q;
always @ (posedge clk_i )
if (rst_i)
cfg_enabled_q <= 1'b0;
else
cfg_enabled_q <= cfg_enabled_w;
wire cfg_enable_reset_w = !cfg_enabled_q & cfg_enabled_w;
//-----------------------------------------------------------------
// Triggering
//-----------------------------------------------------------------
reg [31:0] prev_q;
always @ (posedge clk_i )
if (rst_i)
prev_q <= 32'b0;
else if (!cfg_enabled_w)
prev_q <= la_buffer_trig_sense_value_out_w;
else if (input_valid_i)
prev_q <= input_data_i;
integer i;
reg [31:0] trig_r;
always @ *
begin
trig_r = 32'b0;
if (input_valid_i)
begin
for (i=0;i<32;i=i+1)
begin
// Level sensitive
if (la_buffer_trig_level_value_out_w[i])
begin
if (input_data_i[i] == la_buffer_trig_sense_value_out_w[i])
trig_r[i] = 1'b1;
end
// Edge sensitive (rising)
else if (la_buffer_trig_sense_value_out_w[i])
begin
if (input_data_i[i] && !prev_q[i])
trig_r[i] = 1'b1;
end
// Edge sensitive (falling)
else
begin
if (!input_data_i[i] && prev_q[i])
trig_r[i] = 1'b1;
end
end
end
// Combine with channel enable
trig_r = trig_r & la_buffer_trig_enable_value_out_w;
end
wire trigger_hit_w = (trig_r == la_buffer_trig_enable_value_out_w);
wire trigger_edge_any_w = |(la_buffer_trig_enable_value_out_w & ~la_buffer_trig_level_value_out_w);
reg triggered_q;
always @ (posedge clk_i )
if (rst_i)
triggered_q <= 1'b0;
else if (cfg_enable_reset_w)
triggered_q <= (la_buffer_trig_enable_value_out_w == 32'b0); // No triggers
else if (cfg_enabled_w && trigger_hit_w)
triggered_q <= 1'b1;
//-----------------------------------------------------------------
// Data delay
//-----------------------------------------------------------------
reg [31:0] buffer_q;
reg buffer_wr_q;
always @ (posedge clk_i )
if (rst_i)
buffer_q <= 32'b0;
else
buffer_q <= input_data_i;
always @ (posedge clk_i )
if (rst_i)
buffer_wr_q <= 1'b0;
else
buffer_wr_q <= input_valid_i;
//-----------------------------------------------------------------
// Sample FIFO - decouple sample capture from memory stalls
//-----------------------------------------------------------------
wire data_accept_w;
// Push on valid data, and push previous value on hitting an edge trigger
wire data_push_w = (buffer_wr_q & triggered_q) ||
(trigger_hit_w && trigger_edge_any_w && !triggered_q);
wire [31:0] data_in_w = (buffer_wr_q & triggered_q) ? buffer_q : prev_q;
logic_capture_fifo
u_fifo_data
(
.clk_i(clk_i)
,.rst_i(rst_i)
,.push_i(data_push_w)
,.data_in_i(data_in_w)
,.accept_o(data_accept_w)
,.valid_o(outport_tvalid_o)
,.data_out_o(outport_tdata_o)
,.pop_i(outport_tready_i)
);
assign outport_tstrb_o = 4'hF;
assign outport_tdest_o = 4'b0;
assign outport_tlast_o = 1'b0;
//-----------------------------------------------------------------
// Sample capture count
//-----------------------------------------------------------------
reg [31:0] samples_count_q;
always @ (posedge clk_i )
if (rst_i)
samples_count_q <= 32'b0;
else if (cfg_enable_reset_w)
samples_count_q <= 32'b0;
else if (outport_tvalid_o && outport_tready_i)
begin
case (la_buffer_cfg_width_out_w)
WIDTH_16BIT: samples_count_q <= samples_count_q + {16'b0, outport_tdata_o[31:16]};
WIDTH_24BIT: samples_count_q <= samples_count_q + {24'b0, outport_tdata_o[31:24]};
default: samples_count_q <= samples_count_q + 32'd1;
endcase
end
assign la_buffer_samples_count_in_w = samples_count_q;
//-----------------------------------------------------------------
// Write detection
//-----------------------------------------------------------------
reg write_detect_q;
always @ (posedge clk_i )
if (rst_i)
write_detect_q <= 1'b0;
else if (cfg_enable_reset_w)
write_detect_q <= 1'b0;
else if (data_push_w)
write_detect_q <= 1'b1;
assign la_buffer_sts_trig_in_w = write_detect_q;
assign la_buffer_sts_num_channels_in_w = NUM_CHANNELS[5:0];
//-----------------------------------------------------------------
// FIFO overflow detect
//-----------------------------------------------------------------
reg data_lost_q;
always @ (posedge clk_i )
if (rst_i)
data_lost_q <= 1'b0;
else if (cfg_enable_reset_w)
data_lost_q <= 1'b0;
else if (data_push_w && !data_accept_w)
data_lost_q <= 1'b1;
assign la_buffer_sts_data_loss_in_w = data_lost_q;
assign la_buffer_current_addr_in_w = buffer_current_i;
assign buffer_base_o = {la_buffer_base_addr_out_w[31:2], 2'b0};
assign buffer_end_o = {la_buffer_end_addr_out_w[31:2], 2'b0};
assign buffer_reset_o = !cfg_enabled_w;
assign la_buffer_sts_wrapped_in_w = buffer_wrapped_i;
assign buffer_cont_o = la_buffer_cfg_cont_out_w;
assign status_enabled_o = cfg_enabled_w;
assign status_triggered_o = la_buffer_sts_trig_in_w;
assign status_overflow_o = la_buffer_sts_data_loss_in_w;
assign cfg_clk_src_ext_o = la_buffer_cfg_clk_src_out_w;
assign cfg_clk_div_o = la_buffer_cfg_clk_div_out_w;
assign cfg_width_o = la_buffer_cfg_width_out_w;
assign cfg_test_mode_o = la_buffer_cfg_test_mode_out_w;
endmodule
|
module sata_stack (
input rst, //reset
input clk, //clock used to run the stack
input data_in_clk,
input data_in_clk_valid,
input data_out_clk,
input data_out_clk_valid,
input platform_ready, //the underlying physical platform is
output platform_error, //Underlying platform errored out, the
//clock is misaligned, stack should
//probably be reset
output linkup, //link is finished
input send_sync_escape,
input [15:0] user_features,
//User Interface
output sata_ready,
output sata_busy,
output hard_drive_error,
// input write_data_stb,
// input read_data_stb,
input execute_command_stb,
input command_layer_reset,
input [7:0] hard_drive_command,
output pio_data_ready,
input [15:0] sector_count,
input [47:0] sector_address,
output dma_activate_stb,
output d2h_reg_stb,
output pio_setup_stb,
output d2h_data_stb,
output dma_setup_stb,
output set_device_bits_stb,
output [7:0] d2h_fis,
output d2h_interrupt,
output d2h_notification,
output [3:0] d2h_port_mult,
output [7:0] d2h_device,
output [47:0] d2h_lba,
output [15:0] d2h_sector_count,
output [7:0] d2h_status,
output [7:0] d2h_error,
input [31:0] user_din,
input user_din_stb,
output [1:0] user_din_ready,
input [1:0] user_din_activate,
output [23:0] user_din_size,
output user_din_empty,
output [31:0] user_dout,
output user_dout_ready,
input user_dout_activate,
input user_dout_stb,
output [23:0] user_dout_size,
output transport_layer_ready,
output link_layer_ready,
output phy_ready,
//Buffer
//Platform Interface
output [31:0] tx_dout,
output tx_is_k, //Connect All 4 'tx_is_k'to this signal
output tx_comm_reset,
output tx_comm_wake,
output tx_elec_idle,
input [31:0] rx_din,
input [3:0] rx_is_k,
input rx_elec_idle,
input rx_byte_is_aligned,
input comm_init_detect,
input comm_wake_detect,
input tx_oob_complete,
input phy_error,
//DMA Specific Control
//Data Control
output [3:0] dbg_cc_lax_state,
output [3:0] dbg_cw_lax_state,
output [3:0] dbg_t_lax_state,
output [3:0] dbg_li_lax_state,
output [3:0] dbg_lr_lax_state,
output [3:0] dbg_lw_lax_state,
output [3:0] dbg_lw_lax_fstate,
//Link Layer
input prim_scrambler_en,
input data_scrambler_en,
output dbg_ll_write_ready,
output dbg_ll_paw,
output dbg_ll_write_strobe,
output dbg_ll_send_crc,
//Phy Layer
output [3:0] oob_state,
//Primative Detection
output dbg_detect_sync,
output dbg_detect_r_rdy,
output dbg_detect_r_ip,
output dbg_detect_r_ok,
output dbg_detect_r_err,
output dbg_detect_x_rdy,
output dbg_detect_sof,
output dbg_detect_eof,
output dbg_detect_wtrm,
output dbg_detect_cont,
output dbg_detect_hold,
output dbg_detect_holda,
output dbg_detect_align,
output dbg_detect_preq_s,
output dbg_detect_preq_p,
output dbg_detect_xrdy_xrdy,
output dbg_send_holda,
output [23:0] slw_in_data_addra,
output [12:0] slw_d_count,
output [12:0] slw_write_count,
output [3:0] slw_buffer_pos
);
//Parameters
//Registers/Wires
//Command Layer
wire send_command_stb;
wire send_control_stb;
wire send_data_stb;
wire if_strobe;
wire [31:0] if_data;
wire if_ready;
wire if_activate;
wire [23:0] if_size;
wire of_strobe;
wire [31:0] of_data;
wire [1:0] of_ready;
wire [1:0] of_activate;
wire [23:0] of_size;
//Link Layer
wire ll_sync_escape;
wire ll_write_start;
wire ll_write_strobe;
wire ll_write_finished;
wire [31:0] ll_write_data;
wire [23:0] ll_write_size;
wire ll_write_hold;
wire ll_write_abort;
wire ll_read_ready;
wire ll_read_start;
wire ll_read_strobe;
wire [31:0] ll_read_data;
wire ll_read_finished;
wire ll_read_crc_ok;
wire ll_remote_abort;
wire ll_xmit_error;
wire [31:0] ll_tx_dout;
wire ll_tx_is_k;
//Phy Layer
wire [31:0] phy_tx_dout;
wire phy_tx_is_k;
//User Interface state machine
//Transport Layer
wire sync_escape;
wire [7:0] h2d_command;
wire [15:0] h2d_features;
wire [7:0] h2d_control;
wire [3:0] h2d_port_mult;
wire [7:0] h2d_device;
wire [47:0] h2d_lba;
wire [15:0] h2d_sector_count;
wire remote_abort;
wire xmit_error;
wire read_crc_error;
//PIO
wire pio_response;
wire pio_direction;
wire [15:0] pio_transfer_count;
wire [7:0] pio_e_status;
//Data Control
wire cl_if_ready;
wire cl_if_activate;
wire [23:0] cl_if_size;
wire cl_if_strobe;
wire [31:0] cl_if_data;
wire [1:0] cl_of_ready;
wire [1:0] cl_of_activate;
wire cl_of_strobe;
wire [31:0] cl_of_data;
wire [23:0] cl_of_size;
//Link Layer Interface
wire t_sync_escape;
wire t_write_start;
wire t_write_strobe;
wire t_write_finished;
wire [31:0] t_write_data;
wire [23:0] t_write_size;
wire t_write_hold;
wire t_write_abort;
wire t_xmit_error;
wire t_read_start;
wire t_read_ready;
wire [31:0] t_read_data;
wire t_read_strobe;
wire t_read_finished;
wire t_read_crc_ok;
wire t_remote_abort;
//Comand Layer registers
//Submodules
sata_command_layer scl (
.rst (rst ),
.linkup (linkup ),
.clk (clk ),
.data_in_clk (data_in_clk ),
.data_in_clk_valid (data_in_clk_valid ),
.data_out_clk (data_out_clk ),
.data_out_clk_valid (data_out_clk_valid ),
//Application Interface
.command_layer_ready (sata_ready ),
.sata_busy (sata_busy ),
.hard_drive_error (hard_drive_error ),
.send_sync_escape (send_sync_escape ),
.user_features (user_features ),
// .write_data_stb (write_data_stb ),
// .read_data_stb (read_data_stb ),
.execute_command_stb (execute_command_stb ),
.command_layer_reset (command_layer_reset ),
.hard_drive_command (hard_drive_command ),
.pio_data_ready (pio_data_ready ),
.sector_count (sector_count ),
.sector_address (sector_address ),
.user_din (user_din ),
.user_din_stb (user_din_stb ),
.user_din_ready (user_din_ready ),
.user_din_activate (user_din_activate ),
.user_din_size (user_din_size ),
.user_din_empty (user_din_empty ),
.user_dout (user_dout ),
.user_dout_ready (user_dout_ready ),
.user_dout_activate (user_dout_activate ),
.user_dout_stb (user_dout_stb ),
.user_dout_size (user_dout_size ),
//Transfer Layer Interface
.transport_layer_ready(transport_layer_ready ),
.sync_escape (sync_escape ),
.t_send_command_stb (send_command_stb ),
.t_send_control_stb (send_control_stb ),
.t_send_data_stb (send_data_stb ),
.t_dma_activate_stb (dma_activate_stb ),
.t_d2h_reg_stb (d2h_reg_stb ),
.t_pio_setup_stb (pio_setup_stb ),
.t_d2h_data_stb (d2h_data_stb ),
.t_dma_setup_stb (dma_setup_stb ),
.t_set_device_bits_stb(set_device_bits_stb ),
.t_remote_abort (remote_abort ),
.t_xmit_error (xmit_error ),
.t_read_crc_error (read_crc_error ),
//PIO
.t_pio_response (pio_response ),
.t_pio_direction (pio_direction ),
.t_pio_transfer_count (pio_transfer_count ),
.t_pio_e_status (pio_e_status ),
//Host to Device Register Values
.h2d_command (h2d_command ),
.h2d_features (h2d_features ),
.h2d_control (h2d_control ),
.h2d_port_mult (h2d_port_mult ),
.h2d_device (h2d_device ),
.h2d_lba (h2d_lba ),
.h2d_sector_count (h2d_sector_count ),
//Device to Host Register Values
.d2h_interrupt (d2h_interrupt ),
.d2h_notification (d2h_notification ),
.d2h_port_mult (d2h_port_mult ),
.d2h_device (d2h_device ),
.d2h_lba (d2h_lba ),
.d2h_sector_count (d2h_sector_count ),
.d2h_status (d2h_status ),
.d2h_error (d2h_error ),
//command layer data interface
.t_if_strobe (if_strobe ),
.t_if_data (if_data ),
.t_if_ready (if_ready ),
.t_if_activate (if_activate ),
.t_if_size (if_size ),
.t_of_strobe (of_strobe ),
.t_of_data (of_data ),
.t_of_ready (of_ready ),
.t_of_activate (of_activate ),
.t_of_size (of_size ),
.cl_c_state (dbg_cc_lax_state ),
.cl_w_state (dbg_cw_lax_state )
);
//Transport Layer
sata_transport_layer stl (
.rst (rst | !linkup ),
.clk (clk ),
.phy_ready (phy_ready ),
//Status
.transport_layer_ready (transport_layer_ready ),
.sync_escape (sync_escape ),
.send_command_stb (send_command_stb ),
.send_control_stb (send_control_stb ),
.send_data_stb (send_data_stb ),
.dma_activate_stb (dma_activate_stb ),
.d2h_reg_stb (d2h_reg_stb ),
.pio_setup_stb (pio_setup_stb ),
.d2h_data_stb (d2h_data_stb ),
.dma_setup_stb (dma_setup_stb ),
.set_device_bits_stb (set_device_bits_stb ),
.remote_abort (remote_abort ),
.xmit_error (xmit_error ),
.read_crc_error (read_crc_error ),
//PIO
.pio_response (pio_response ),
.pio_direction (pio_direction ),
.pio_transfer_count (pio_transfer_count ),
.pio_e_status (pio_e_status ),
//Host to Device Register Values
.h2d_command (h2d_command ),
.h2d_features (h2d_features ),
.h2d_control (h2d_control ),
.h2d_port_mult (h2d_port_mult ),
.h2d_device (h2d_device ),
.h2d_lba (h2d_lba ),
.h2d_sector_count (h2d_sector_count ),
//Device to Host Register Values
.d2h_fis (d2h_fis ),
.d2h_interrupt (d2h_interrupt ),
.d2h_notification (d2h_notification ),
.d2h_port_mult (d2h_port_mult ),
.d2h_device (d2h_device ),
.d2h_lba (d2h_lba ),
.d2h_sector_count (d2h_sector_count ),
.d2h_status (d2h_status ),
.d2h_error (d2h_error ),
//command layer data interface
.cl_if_ready (cl_if_ready ),
.cl_if_activate (cl_if_activate ),
.cl_if_size (cl_if_size ),
.cl_if_strobe (cl_if_strobe ),
.cl_if_data (cl_if_data ),
.cl_of_ready (cl_of_ready ),
.cl_of_activate (cl_of_activate ),
.cl_of_strobe (cl_of_strobe ),
.cl_of_data (cl_of_data ),
.cl_of_size (cl_of_size ),
//Link Layer Interface
.link_layer_ready (link_layer_ready ),
.ll_sync_escape (t_sync_escape ),
.ll_write_start (t_write_start ),
.ll_write_strobe (t_write_strobe ),
.ll_write_finished (t_write_finished ),
.ll_write_data (t_write_data ),
.ll_write_size (t_write_size ),
.ll_write_hold (t_write_hold ),
.ll_write_abort (t_write_abort ),
.ll_xmit_error (t_xmit_error ),
.ll_read_start (t_read_start ),
.ll_read_ready (t_read_ready ),
.ll_read_data (t_read_data ),
.ll_read_strobe (t_read_strobe ),
.ll_read_finished (t_read_finished ),
.ll_read_crc_ok (t_read_crc_ok ),
.ll_remote_abort (t_remote_abort ),
.lax_state (dbg_t_lax_state )
);
sata_link_layer sll(
.rst (rst | !linkup ),
.clk (clk ),
//Status
.link_layer_ready (link_layer_ready ),
.sync_escape (ll_sync_escape ),
.write_ready (dbg_ll_write_ready ),
.post_align_write (dbg_ll_paw ),
.hold (1'b0 ),
//Transport Layer Interface
.write_start (ll_write_start ),
.write_strobe (ll_write_strobe ),
.write_finished (ll_write_finished ),
.write_data (ll_write_data ),
.write_size (ll_write_size ),
.write_hold (ll_write_hold ),
.write_abort (ll_write_abort ),
.read_data (ll_read_data ),
.read_strobe (ll_read_strobe ),
.read_ready (ll_read_ready ),
.read_start (ll_read_start ),
.read_finished (ll_read_finished ),
.remote_abort (ll_remote_abort ),
.xmit_error (ll_xmit_error ),
.read_crc_ok (ll_read_crc_ok ),
.prim_scrambler_en (prim_scrambler_en ),
.data_scrambler_en (data_scrambler_en ),
//Phy Layer
.phy_ready (phy_ready ),
.platform_ready (platform_ready ),
.tx_dout (ll_tx_dout ),
.tx_is_k (ll_tx_is_k ),
.rx_din (rx_din ),
.rx_is_k (rx_is_k ),
.is_device (1'b0 ),
//Primative Detection
.detect_sync (dbg_detect_sync ),
.detect_r_rdy (dbg_detect_r_rdy ),
.detect_r_ip (dbg_detect_r_ip ),
.detect_r_ok (dbg_detect_r_ok ),
.detect_r_err (dbg_detect_r_err ),
.detect_x_rdy (dbg_detect_x_rdy ),
.detect_sof (dbg_detect_sof ),
.detect_eof (dbg_detect_eof ),
.detect_wtrm (dbg_detect_wtrm ),
.detect_cont (dbg_detect_cont ),
.detect_hold (dbg_detect_hold ),
.detect_holda (dbg_detect_holda ),
.detect_align (dbg_detect_align ),
.detect_preq_s (dbg_detect_preq_s ),
.detect_preq_p (dbg_detect_preq_p ),
.detect_xrdy_xrdy (dbg_detect_xrdy_xrdy ),
.dbg_send_holda (dbg_send_holda ),
.send_crc (dbg_ll_send_crc ),
.lax_i_state (dbg_li_lax_state ),
.lax_r_state (dbg_lr_lax_state ),
.lax_w_state (dbg_lw_lax_state ),
.lax_w_fstate (dbg_lw_lax_fstate ),
.in_data_addra (slw_in_data_addra ),
.d_count (slw_d_count ),
.write_count (slw_write_count ),
.buffer_pos (slw_buffer_pos )
);
sata_phy_layer phy (
.rst (rst ),
.clk (clk ),
//Control/Status
.platform_ready (platform_ready ),
.platform_error (platform_error ),
.linkup (linkup ),
//Platform Interface
.tx_dout (phy_tx_dout ),
.tx_is_k (phy_tx_is_k ),
.tx_comm_reset (tx_comm_reset ),
.tx_comm_wake (tx_comm_wake ),
.tx_elec_idle (tx_elec_idle ),
.tx_oob_complete (tx_oob_complete ),
.rx_din (rx_din ),
.rx_is_k (rx_is_k ),
.comm_init_detect (comm_init_detect ),
.comm_wake_detect (comm_wake_detect ),
.rx_elec_idle (rx_elec_idle ),
.rx_byte_is_aligned (rx_byte_is_aligned ),
.phy_error (phy_error ),
.lax_state (oob_state ),
.phy_ready (phy_ready )
);
//Asynchronous Logic
//control of data to the platform controller
//In order to send align primitives the phy must sometimes take over the bus
assign tx_dout = (phy_ready) ? ll_tx_dout : phy_tx_dout;
assign tx_is_k = (phy_ready) ? ll_tx_is_k : phy_tx_is_k;
//no activity on the stack
//Debug
assign ll_write_start = t_write_start;
assign ll_write_data = t_write_data;
assign ll_write_hold = t_write_hold;
assign ll_write_size = t_write_size;
assign ll_write_abort = t_write_abort;
assign ll_read_ready = t_read_ready;
assign ll_sync_escape = t_sync_escape;
assign t_write_strobe = ll_write_strobe;
assign t_write_finished = ll_write_finished;
assign t_read_strobe = ll_read_strobe;
assign t_read_start = ll_read_start;
assign t_read_finished = ll_read_finished;
assign t_read_data = ll_read_data;
assign t_remote_abort = ll_remote_abort;
assign t_xmit_error = ll_xmit_error;
assign t_read_crc_ok = ll_read_crc_ok;
assign cl_if_ready = if_ready;
assign if_activate = cl_if_activate;
assign cl_if_size = if_size;
assign if_strobe = cl_if_strobe;
assign cl_if_data = if_data;
assign cl_of_ready = of_ready;
assign of_activate = cl_of_activate;
assign of_strobe = cl_of_strobe;
assign of_data = cl_of_data;
assign cl_of_size = of_size;
//Synchronous Logic
endmodule
|
module data_test2 (
input rst, //reset
input clk,
output reg din_stb,
input [1:0] din_ready,
output reg [1:0] din_activate,
output reg [31:0] din,
input [23:0] din_size,
input dout_ready,
output reg dout_activate,
input [31:0] dout,
output reg dout_stb,
input [23:0] dout_size,
output reg count_error,
output reg incorrect_data,
output reg [23:0] count_detected,
output reg [31:0] detected_value
);
//Parameters
//Registers/Wires
reg [31:0] write_count;
reg [31:0] read_count;
//Submodules
//Asynchronous Logic
//Synchronous Logic
always @ (posedge clk) begin
if (rst) begin
din_stb <= 0;
din_activate <= 0;
din <= 0;
write_count <= 0;
dout_activate <= 0;
dout_stb <= 0;
read_count <= 0;
count_error <= 0;
incorrect_data <= 0;
detected_value <= 0;
count_detected <= 0;
end
else begin
din_stb <= 0;
dout_stb <= 0;
count_error <= 0;
incorrect_data <= 0;
if ((din_ready > 0) && (din_activate == 0)) begin
write_count <= 0;
din <= 0;
if (din_ready[0]) begin
din_activate[0] <= 1;
end
else begin
din_activate[1] <= 1;
end
end
else if (din_activate != 0) begin
if (write_count < din_size) begin
din_stb <= 1;
din <= write_count;
write_count <= write_count + 1;
end
else begin
din_activate <= 0;
end
end
if (dout_ready && !dout_activate) begin
read_count <= 0;
dout_activate <= 1;
if (dout_size != 24'h0800) begin
count_error <= 1;
count_detected <= dout_size;
end
end
else if (dout_activate) begin
if (read_count < dout_size) begin
dout_stb <= 1;
read_count <= read_count + 1;
end
else begin
dout_activate <= 0;
end
//Error Detection
if (read_count > 0) begin
if (dout != read_count - 1) begin
incorrect_data <= 1;
count_detected <= read_count[23:0];
detected_value <= dout;
end
end
else begin
if (dout != 0) begin
incorrect_data <= 1;
count_detected <= read_count[23:0];
detected_value <= dout;
end
end
end
end
end
endmodule
|
module hd_data_writer(
input clk,
input rst,
input enable,
output reg [31:0] data,
input strobe
);
//Registers and Wires
reg [31:0] test_data;
//Submodules
//Asynchronous Logic
//Synchronous Logic
always @ (posedge clk) begin
if (rst) begin
test_data <= 0;
data <= 0;
end
else begin
if (enable) begin
data <= test_data;
if (strobe) begin
test_data <= test_data + 1;
end
end
else begin
test_data <= 0;
end
end
end
endmodule
|
module test_in (
input clk,
input rst,
input enable,
output reg finished,
input [23:0] write_count,
input [1:0] ready,
output reg [1:0] activate,
output reg [31:0] fifo_data,
input [23:0] fifo_size,
output reg strobe
);
//Parameters
//Registers/Wires
reg [23:0] count;
reg [23:0] total_count;
//Sub modules
//Asynchronous Logic
//Synchronous Logic
always @ (posedge clk or posedge rst) begin
if (rst) begin
activate <= 0;
fifo_data <= 0;
strobe <= 0;
count <= 0;
total_count <= 0;
finished <= 0;
end
else begin
strobe <= 0;
if (!enable) begin
total_count <= 0;
activate <= 0;
finished <= 0;
end
else if (total_count < write_count) begin
if ((ready > 0) && (activate == 0)) begin
//A FIFO is available
count <= 0;
if (ready[0]) begin
activate[0] <= 1;
end
else begin
activate[1] <= 1;
end
end
else if ((activate > 0) && (count < fifo_size))begin
fifo_data <= total_count;
total_count <= total_count + 1;
count <= count + 1;
strobe <= 1;
end
else begin
activate <= 0;
end
end
else begin
finished <= 1;
activate <= 0;
end
end
end
endmodule
|
module tb_cocotb (
//Parameters
//Registers/Wires
input rst, //reset
input clk,
output linkup, //link is finished
output sata_ready,
output sata_busy,
//input write_data_stb,
//input read_data_stb,
input [7:0] hard_drive_command,
input execute_command_stb,
input command_layer_reset,
input [15:0] sector_count,
input [47:0] sector_address,
output d2h_interrupt,
output d2h_notification,
output [3:0] d2h_port_mult,
output [7:0] d2h_device,
output [47:0] d2h_lba,
output [15:0] d2h_sector_count,
output [7:0] d2h_status,
output [7:0] d2h_error,
input u2h_write_enable,
output u2h_write_finished,
input [23:0] u2h_write_count,
input h2u_read_enable,
output [23:0] h2u_read_total_count,
output h2u_read_error,
output h2u_read_busy,
output u2h_read_error,
output transport_layer_ready,
output link_layer_ready,
output phy_ready,
input prim_scrambler_en,
input data_scrambler_en,
//Data Interface
output tx_set_elec_idle,
output rx_is_elec_idle,
output hd_ready,
input platform_ready,
//Debug
input hold,
input single_rdwr
);
reg [31:0] test_id = 0;
wire [31:0] tx_dout;
wire tx_is_k;
wire tx_comm_reset;
wire tx_comm_wake;
wire tx_elec_idle;
wire [31:0] rx_din;
wire [3:0] rx_is_k;
wire rx_elec_idle;
wire comm_init_detect;
wire comm_wake_detect;
reg r_rst;
reg r_write_data_stb;
reg r_read_data_stb;
reg r_command_layer_reset;
reg [15:0] r_sector_count;
reg [47:0] r_sector_address;
reg r_prim_scrambler_en;
reg r_data_scrambler_en;
reg r_platform_ready;
reg r_dout_count;
reg r_hold;
reg r_u2h_write_enable;
reg [23:0] r_u2h_write_count;
reg r_h2u_read_enable;
reg [7:0] r_hard_drive_command;
reg r_execute_command_stb;
wire hd_read_from_host;
wire [31:0] hd_data_from_host;
wire hd_write_to_host;
wire [31:0] hd_data_to_host;
wire [31:0] user_dout;
wire user_dout_ready;
wire user_dout_activate;
wire user_dout_stb;
wire [23:0] user_dout_size;
wire [31:0] user_din;
wire user_din_stb;
wire [1:0] user_din_ready;
wire [1:0] user_din_activate;
wire [23:0] user_din_size;
wire dma_activate_stb;
wire d2h_reg_stb;
wire pio_setup_stb;
wire d2h_data_stb;
wire dma_setup_stb;
wire set_device_bits_stb;
wire [7:0] d2h_fis;
wire i_rx_byte_is_aligned;
//There is a bug in COCOTB when stiumlating a signal, sometimes it can be corrupted if not registered
always @ (*) r_rst = rst;
//always @ (*) r_write_data_stb = write_data_stb;
//always @ (*) r_read_data_stb = read_data_stb;
always @ (*) r_command_layer_reset= command_layer_reset;
always @ (*) r_sector_count = sector_count;
always @ (*) r_sector_address = sector_address;
always @ (*) r_prim_scrambler_en = prim_scrambler_en;
always @ (*) r_data_scrambler_en = data_scrambler_en;
always @ (*) r_platform_ready = platform_ready;
always @ (*) r_hold = hold;
always @ (*) r_u2h_write_enable = u2h_write_enable;
always @ (*) r_u2h_write_count = u2h_write_count;
always @ (*) r_h2u_read_enable = h2u_read_enable;
always @ (*) r_hard_drive_command = hard_drive_command;
always @ (*) r_execute_command_stb= execute_command_stb;
//Submodules
//User Generated Test Data
test_in user_2_hd_generator(
.clk (clk ),
.rst (rst ),
.enable (r_u2h_write_enable ),
.finished (u2h_write_finished ),
.write_count (r_u2h_write_count ),
.ready (user_din_ready ),
.activate (user_din_activate ),
.fifo_data (user_din ),
.fifo_size (user_din_size ),
.strobe (user_din_stb )
);
//Module to process data from Hard Drive to User
test_out hd_2_user_reader(
.clk (clk ),
.rst (rst ),
.busy (h2u_read_busy ),
.enable (r_h2u_read_enable ),
.error (h2u_read_error ),
.total_count (h2u_read_total_count ),
.ready (user_dout_ready ),
.activate (user_dout_activate ),
.size (user_dout_size ),
.data (user_dout ),
.strobe (user_dout_stb )
);
//hd data reader core
hd_data_reader user_2_hd_reader(
.clk (clk ),
.rst (rst ),
.enable (r_u2h_write_enable ),
.error (u2h_read_error ),
.hd_read_from_host (hd_read_from_host ),
.hd_data_from_host (hd_data_from_host )
);
//hd data writer core
hd_data_writer hd_2_user_generator(
.clk (clk ),
.rst (rst ),
.enable (r_h2u_read_enable ),
.data (hd_data_to_host ),
.strobe (hd_write_to_host )
);
sata_stack ss (
.rst (r_rst ), //reset
.clk (clk ), //clock used to run the stack
.command_layer_reset (r_command_layer_reset),
.platform_ready (platform_ready ), //the underlying physical platform is
.platform_error ( ),
.linkup (linkup ), //link is finished
.sata_ready (sata_ready ),
.sata_busy (sata_busy ),
.send_sync_escape (1'b0 ),
.hard_drive_error ( ),
.pio_data_ready ( ),
//Host to Device Control
// .write_data_stb (r_write_data_stb ),
// .read_data_stb (r_read_data_stb ),
.hard_drive_command (r_hard_drive_command ),
.execute_command_stb (r_execute_command_stb),
.user_features (16'h0000 ),
.sector_count (r_sector_count ),
.sector_address (r_sector_address ),
.dma_activate_stb (dma_activate_stb ),
.d2h_reg_stb (d2h_reg_stb ),
.pio_setup_stb (pio_setup_stb ),
.d2h_data_stb (d2h_data_stb ),
.dma_setup_stb (dma_setup_stb ),
.set_device_bits_stb (set_device_bits_stb ),
.d2h_fis (d2h_fis ),
.d2h_interrupt (d2h_interrupt ),
.d2h_notification (d2h_notification ),
.d2h_port_mult (d2h_port_mult ),
.d2h_device (d2h_device ),
.d2h_lba (d2h_lba ),
.d2h_sector_count (d2h_sector_count ),
.d2h_status (d2h_status ),
.d2h_error (d2h_error ),
//Data from host to the hard drive path
.data_in_clk (clk ),
.data_in_clk_valid (1'b1 ),
.user_din (user_din ), //User Data Here
.user_din_stb (user_din_stb ), //Strobe Each Data word in here
.user_din_ready (user_din_ready ), //Using PPFIFO Ready Signal
.user_din_activate (user_din_activate ), //Activate PPFIFO Channel
.user_din_size (user_din_size ), //Find the size of the data to write to the device
//Data from hard drive to host path
.data_out_clk (clk ),
.data_out_clk_valid (1'b1 ),
.user_dout (user_dout ),
.user_dout_ready (user_dout_ready ),
.user_dout_activate (user_dout_activate ),
.user_dout_stb (user_dout_stb ),
.user_dout_size (user_dout_size ),
.transport_layer_ready (transport_layer_ready),
.link_layer_ready (link_layer_ready ),
.phy_ready (phy_ready ),
.phy_error (1'b0 ),
.tx_dout (tx_dout ),
.tx_is_k (tx_is_k ),
.tx_comm_reset (tx_comm_reset ),
.tx_comm_wake (tx_comm_wake ),
.tx_elec_idle (tx_elec_idle ),
.tx_oob_complete (1'b1 ),
.rx_din (rx_din ),
.rx_is_k (rx_is_k ),
.rx_elec_idle (rx_elec_idle ),
.rx_byte_is_aligned (i_rx_byte_is_aligned ),
.comm_init_detect (comm_init_detect ),
.comm_wake_detect (comm_wake_detect ),
//.prim_scrambler_en (r_prim_scrambler_en ),
.prim_scrambler_en (1'b1 ),
//.data_scrambler_en (r_data_scrambler_en )
.data_scrambler_en (1'b1 )
);
faux_sata_hd fshd (
.rst (r_rst ),
.clk (clk ),
.tx_dout (rx_din ),
.tx_is_k (rx_is_k ),
.rx_din (tx_dout ),
.rx_is_k ({3'b000, tx_is_k} ),
.rx_is_elec_idle (tx_elec_idle ),
.rx_byte_is_aligned (i_rx_byte_is_aligned ),
.comm_reset_detect (tx_comm_reset ),
.comm_wake_detect (tx_comm_wake ),
.tx_comm_reset (comm_init_detect ),
.tx_comm_wake (comm_wake_detect ),
.hd_ready (hd_ready ),
// .phy_ready (phy_ready ),
//.dbg_data_scrambler_en (r_data_scrambler_en ),
.dbg_data_scrambler_en (1'b1 ),
.dbg_hold (r_hold ),
.dbg_ll_write_start (1'b0 ),
.dbg_ll_write_data (32'h0 ),
.dbg_ll_write_size (0 ),
.dbg_ll_write_hold (1'b0 ),
.dbg_ll_write_abort (1'b0 ),
.dbg_ll_read_ready (1'b0 ),
.dbg_t_en (1'b0 ),
.dbg_send_reg_stb (1'b0 ),
.dbg_send_dma_act_stb (1'b0 ),
.dbg_send_data_stb (1'b0 ),
.dbg_send_pio_stb (1'b0 ),
.dbg_send_dev_bits_stb (1'b0 ),
.dbg_pio_transfer_count(16'h0000 ),
.dbg_pio_direction (1'b0 ),
.dbg_pio_e_status (8'h00 ),
.dbg_d2h_interrupt (1'b0 ),
.dbg_d2h_notification (1'b0 ),
.dbg_d2h_status (8'b0 ),
.dbg_d2h_error (8'b0 ),
.dbg_d2h_port_mult (4'b0000 ),
.dbg_d2h_device (8'h00 ),
.dbg_d2h_lba (48'h000000000000 ),
.dbg_d2h_sector_count (16'h0000 ),
.dbg_cl_if_data (32'b0 ),
.dbg_cl_if_ready (1'b0 ),
.dbg_cl_if_size (24'h0 ),
.dbg_cl_of_ready (2'b0 ),
.dbg_cl_of_size (24'h0 ),
.hd_read_from_host (hd_read_from_host ),
.hd_data_from_host (hd_data_from_host ),
.hd_write_to_host (hd_write_to_host ),
.hd_data_to_host (hd_data_to_host )
);
//Asynchronous Logic
//Synchronous Logic
//Simulation Control
initial begin
$dumpfile ("design.vcd");
$dumpvars(0, tb_cocotb);
end
endmodule
|
module faux_sata_hd (
//Inputs/Outputs
input rst, //reset
input clk,
//Data Interface
output [31:0] tx_dout,
output [3:0] tx_is_k,
output tx_set_elec_idle,
output rx_byte_is_aligned,
input [31:0] rx_din,
input [3:0] rx_is_k,
input rx_is_elec_idle,
input comm_reset_detect,
input comm_wake_detect,
output tx_comm_reset,
output tx_comm_wake,
output hd_ready,
output phy_ready,
//Debug
output [3:0] oob_state,
output [3:0] cl_state,
//Link Layer
input dbg_ll_write_start,
output dbg_ll_write_strobe,
output dbg_ll_write_finished,
input [31:0] dbg_ll_write_data,
input [31:0] dbg_ll_write_size,
input dbg_ll_write_hold,
input dbg_ll_write_abort,
output dbg_ll_xmit_error,
output dbg_ll_read_start,
output dbg_ll_read_strobe,
output [31:0] dbg_ll_read_data,
input dbg_ll_read_ready,
output dbg_ll_read_finished,
output dbg_ll_remote_abort,
input dbg_data_scrambler_en,
input dbg_hold,
//Transport Layer Debug
input dbg_t_en,
//Trasport Layer Control/Status
output dbg_tl_ready,
input dbg_send_reg_stb,
input dbg_send_dma_act_stb,
input dbg_send_data_stb,
input dbg_send_pio_stb,
input dbg_send_dev_bits_stb,
output dbg_remote_abort,
output dbg_xmit_error,
output dbg_read_crc_fail,
output dbg_h2d_reg_stb,
output dbg_h2d_data_stb,
output dbg_pio_request,
input [15:0] dbg_pio_transfer_count,
input dbg_pio_direction,
input [7:0] dbg_pio_e_status,
//FIS Structure
output [7:0] dbg_h2d_command,
output [15:0] dbg_h2d_features,
output dbg_h2d_cmd_bit,
output [3:0] dbg_h2d_port_mult,
output [7:0] dbg_h2d_control,
output [7:0] dbg_h2d_device,
output [47:0] dbg_h2d_lba,
output [15:0] dbg_h2d_sector_count,
input dbg_d2h_interrupt,
input dbg_d2h_notification,
input [7:0] dbg_d2h_status,
input [7:0] dbg_d2h_error,
input [3:0] dbg_d2h_port_mult,
input [7:0] dbg_d2h_device,
input [47:0] dbg_d2h_lba,
input [15:0] dbg_d2h_sector_count,
//command layer data interface
output dbg_cl_if_strobe,
input [31:0] dbg_cl_if_data,
input dbg_cl_if_ready,
output dbg_cl_if_activate,
input [23:0] dbg_cl_if_size,
output dbg_cl_of_strobe,
output [31:0] dbg_cl_of_data,
input [1:0] dbg_cl_of_ready,
output [1:0] dbg_cl_of_activate,
input [23:0] dbg_cl_of_size,
output command_layer_ready,
output hd_read_from_host,
output [31:0] hd_data_from_host,
output hd_write_to_host,
input [31:0] hd_data_to_host
);
//Parameters
//Registers/Wires
wire [31:0] phy_tx_dout;
wire phy_tx_is_k;
wire [31:0] sll_tx_dout;
wire sll_tx_is_k;
wire ll_ready;
wire ll_write_start;
wire ll_write_finished;
wire ll_write_strobe;
wire [31:0] ll_write_data;
wire [31:0] ll_write_size;
wire ll_write_hold;
wire ll_write_abort;
wire ll_read_start;
wire ll_read_strobe;
wire [31:0] ll_read_data;
wire ll_remote_abort;
wire ll_read_ready;
wire ll_read_finished;
wire ll_read_crc_ok;
wire data_scrambler_en;
//Command Layer
wire cl_send_reg_stb;
wire cl_send_dma_act_stb;
wire cl_send_data_stb;
wire cl_send_pio_stb;
wire cl_send_dev_bits_stb;
wire [15:0] cl_pio_transfer_count;
wire cl_pio_direction;
wire [7:0] cl_pio_e_status;
wire cl_d2h_interrupt;
wire cl_d2h_notification;
wire [7:0] cl_d2h_status;
wire [7:0] cl_d2h_error;
wire [3:0] cl_d2h_port_mult;
wire [7:0] cl_d2h_device;
wire [47:0] cl_d2h_lba;
wire [15:0] cl_d2h_sector_count;
//Trasport Layer Control/Status
wire transport_layer_ready;
wire send_reg_stb;
wire send_dma_act_stb;
wire send_data_stb;
wire send_pio_stb;
wire send_dev_bits_stb;
wire remote_abort;
wire xmit_error;
wire read_crc_fail;
wire h2d_reg_stb;
wire h2d_data_stb;
wire pio_request;
wire [15:0] pio_transfer_count;
wire pio_direction;
wire [7:0] pio_e_status;
wire [31:0] if_data;
wire if_ready;
wire [23:0] if_size;
wire [1:0] of_ready;
wire [23:0] of_size;
//Host to Device Registers
wire [7:0] h2d_command;
wire [15:0] h2d_features;
wire h2d_cmd_bit;
wire [7:0] h2d_control;
wire [3:0] h2d_port_mult;
wire [7:0] h2d_device;
wire [47:0] h2d_lba;
wire [15:0] h2d_sector_count;
//Device to Host Registers
wire d2h_interrupt;
wire d2h_notification;
wire [3:0] d2h_port_mult;
wire [7:0] d2h_device;
wire [47:0] d2h_lba;
wire [15:0] d2h_sector_count;
wire [7:0] d2h_status;
wire [7:0] d2h_error;
//DMA Specific Control
//Data Control
wire cl_if_ready;
wire cl_if_activate;
wire [23:0] cl_if_size;
wire cl_if_strobe;
wire [31:0] cl_if_data;
wire [1:0] cl_of_ready;
wire [1:0] cl_of_activate;
wire cl_of_strobe;
wire [31:0] cl_of_data;
wire [23:0] cl_of_size;
//Link Layer Interface
wire t_write_start;
wire t_write_strobe;
wire t_write_finished;
wire [31:0] t_write_data;
wire [31:0] t_write_size;
wire t_write_hold;
wire t_write_abort;
wire t_xmit_error;
wire t_read_start;
wire t_read_ready;
wire [31:0] t_read_data;
wire t_read_strobe;
wire t_read_finished;
wire t_read_crc_ok;
wire t_remote_abort;
//Sub Modules
faux_sata_hd_phy hd_phy(
.rst (rst ),
.clk (clk ),
//incomming/output data
.tx_dout (phy_tx_dout ),
.tx_is_k (phy_tx_is_k ),
.tx_set_elec_idle (tx_set_elec_idle ),
.rx_din (rx_din ),
.rx_is_k (rx_is_k ),
.rx_is_elec_idle (rx_is_elec_idle ),
.rx_byte_is_aligned (rx_byte_is_aligned ),
.comm_reset_detect (comm_reset_detect ),
.comm_wake_detect (comm_wake_detect ),
.tx_comm_reset (tx_comm_reset ),
.tx_comm_wake (tx_comm_wake ),
//Status
.lax_state (oob_state ),
.phy_ready (phy_ready ),
.hd_ready (hd_ready )
);
sata_link_layer fsll (
.rst (rst || !hd_ready ),
.clk (clk ),
.prim_scrambler_en (1'b1 ),
.data_scrambler_en (data_scrambler_en ),
.link_layer_ready (ll_ready ),
.sync_escape (1'b0 ),
.hold (dbg_hold ),
//Transport Layer Interface
.write_start (ll_write_start ),
.write_strobe (ll_write_strobe ),
.write_data (ll_write_data ),
.write_size (ll_write_size ),
.write_hold (ll_write_hold ),
.write_finished (ll_write_finished ),
.write_abort (ll_write_abort ),
.xmit_error (t_xmit_error ),
.read_strobe (ll_read_strobe ),
.read_data (ll_read_data ),
.read_ready (ll_read_ready ),
.read_start (ll_read_start ),
.read_finished (ll_read_finished ),
.read_crc_ok (ll_read_crc_ok ),
.remote_abort (ll_remote_abort ),
//Phy Layer
.phy_ready (phy_ready ),
.platform_ready (hd_ready ),
.tx_dout (sll_tx_dout ),
.tx_is_k (sll_tx_is_k ),
.rx_din (rx_din ),
.rx_is_k (rx_is_k ),
.is_device (1'b1 )
);
faux_sata_hd_transport ftl (
.rst (rst || !hd_ready ),
.clk (clk ),
//Trasport Layer Control/Status
.transport_layer_ready(transport_layer_ready ),
.send_reg_stb (send_reg_stb ),
.send_dma_act_stb (send_dma_act_stb ),
.send_data_stb (send_data_stb ),
.send_pio_stb (send_pio_stb ),
.send_dev_bits_stb (send_dev_bits_stb ),
.remote_abort (remote_abort ),
.xmit_error (xmit_error ),
.read_crc_fail (read_crc_fail ),
.h2d_reg_stb (h2d_reg_stb ),
.h2d_data_stb (h2d_data_stb ),
.pio_request (pio_request ),
.pio_transfer_count (pio_transfer_count ),
.pio_direction (pio_direction ),
.pio_e_status (pio_e_status ),
//FIS Structure
.h2d_command (h2d_command ),
.h2d_features (h2d_features ),
.h2d_cmd_bit (h2d_cmd_bit ),
.h2d_port_mult (h2d_port_mult ),
.h2d_control (h2d_control ),
.h2d_device (h2d_device ),
.h2d_lba (h2d_lba ),
.h2d_sector_count (h2d_sector_count ),
.d2h_interrupt (d2h_interrupt ),
.d2h_notification (d2h_notification ),
.d2h_status (d2h_status ),
.d2h_error (d2h_error ),
.d2h_port_mult (d2h_port_mult ),
.d2h_device (d2h_device ),
.d2h_lba (d2h_lba ),
.d2h_sector_count (d2h_sector_count ),
//command layer data interface
.cl_if_strobe (cl_if_strobe ),
.cl_if_data (cl_if_data ),
.cl_if_ready (cl_if_ready ),
.cl_if_activate (cl_if_activate ),
.cl_if_size (cl_if_size ),
.cl_of_strobe (cl_of_strobe ),
.cl_of_data (cl_of_data ),
.cl_of_ready (cl_of_ready ),
.cl_of_activate (cl_of_activate ),
.cl_of_size (cl_of_size ),
//Link Layer Interface
.link_layer_ready (ll_ready ),
.ll_write_start (t_write_start ),
.ll_write_strobe (t_write_strobe ),
.ll_write_finished (t_write_finished ),
.ll_write_data (t_write_data ),
.ll_write_size (t_write_size ),
.ll_write_hold (t_write_hold ),
.ll_write_abort (t_write_abort ),
.ll_xmit_error (t_xmit_error ),
.ll_read_start (t_read_start ),
.ll_read_ready (t_read_ready ),
.ll_read_data (t_read_data ),
.ll_read_strobe (t_read_strobe ),
.ll_read_finished (t_read_finished ),
.ll_read_crc_ok (t_read_crc_ok ),
.ll_remote_abort (t_remote_abort )
);
faux_hd_command_layer fcl(
.rst (rst || !hd_ready ),
.clk (clk ),
.command_layer_ready (command_layer_ready ),
.hd_read_from_host (hd_read_from_host ),
.hd_data_from_host (hd_data_from_host ),
.hd_write_to_host (hd_write_to_host ),
.hd_data_to_host (hd_data_to_host ),
.transport_layer_ready(transport_layer_ready ),
.send_reg_stb (cl_send_reg_stb ),
.send_dma_act_stb (cl_send_dma_act_stb ),
.send_data_stb (cl_send_data_stb ),
.send_pio_stb (cl_send_pio_stb ),
.send_dev_bits_stb (cl_send_dev_bits_stb ),
.remote_abort (remote_abort ),
.xmit_error (xmit_error ),
.read_crc_fail (read_crc_fail ),
.h2d_reg_stb (h2d_reg_stb ),
.h2d_data_stb (h2d_data_stb ),
.pio_request (pio_request ),
.pio_transfer_count (cl_pio_transfer_count ),
.pio_direction (cl_pio_direction ),
.pio_e_status (cl_pio_e_status ),
//FIS Structure
.h2d_command (h2d_command ),
.h2d_features (h2d_features ),
.h2d_cmd_bit (h2d_cmd_bit ),
.h2d_port_mult (h2d_port_mult ),
.h2d_control (h2d_control ),
.h2d_device (h2d_device ),
.h2d_lba (h2d_lba ),
.h2d_sector_count (h2d_sector_count ),
.d2h_interrupt (cl_d2h_interrupt ),
.d2h_notification (cl_d2h_notification ),
.d2h_status (cl_d2h_status ),
.d2h_error (cl_d2h_error ),
.d2h_port_mult (cl_d2h_port_mult ),
.d2h_device (cl_d2h_device ),
.d2h_lba (cl_d2h_lba ),
.d2h_sector_count (cl_d2h_sector_count ),
//command layer data interface
.cl_if_strobe (cl_if_strobe ),
.cl_if_data (if_data ),
.cl_if_ready (if_ready ),
.cl_if_activate (cl_if_activate ),
.cl_if_size (if_size ),
.cl_of_strobe (cl_of_strobe ),
.cl_of_data (cl_of_data ),
.cl_of_ready (of_ready ),
.cl_of_activate (cl_of_activate ),
.cl_of_size (of_size ),
.cl_state (cl_state )
);
assign tx_dout = !phy_ready ? phy_tx_dout : sll_tx_dout;
assign tx_is_k[3:1] = 3'b000;
assign tx_is_k[0] = !phy_ready ? phy_tx_is_k : sll_tx_is_k;
//Debug
//assign ll_write_start = (dbg_ll_en) ? dbg_ll_write_start : t_write_start;
//assign ll_write_data = (dbg_ll_en) ? dbg_ll_write_data : t_write_data;
//assign ll_write_hold = (dbg_ll_en) ? dbg_ll_write_hold : t_write_hold;
//assign ll_write_size = (dbg_ll_en) ? dbg_ll_write_size : t_write_size;
//assign ll_write_abort = (dbg_ll_en) ? dbg_ll_write_abort : t_write_abort;
//assign data_scrambler_en = (dbg_ll_en) ? dbg_data_scrambler_en : 1;
//
//assign ll_read_ready = (dbg_ll_en) ? dbg_ll_read_ready : t_read_ready;
//
assign ll_write_start = t_write_start;
assign ll_write_data = t_write_data;
assign ll_write_hold = t_write_hold;
assign ll_write_size = t_write_size;
assign ll_write_abort = t_write_abort;
assign data_scrambler_en = 1;
assign ll_read_ready = t_read_ready;
assign dbg_ll_write_strobe = ll_write_strobe;
assign dbg_ll_write_finished = ll_write_finished;
assign dbg_ll_xmit_error = xmit_error;
assign dbg_ll_read_strobe = ll_read_strobe;
assign dbg_ll_read_start = ll_read_start;
assign dbg_ll_read_finished = ll_read_finished;
assign dbg_ll_read_data = ll_read_data;
assign dbg_ll_remote_abort = ll_remote_abort;
//Transport Layer Debug Signals
assign dbg_tl_ready = transport_layer_ready;
assign t_read_strobe = ll_read_strobe;
assign t_read_start = ll_read_start;
assign t_read_finished = ll_read_finished;
assign t_read_data = ll_read_data;
assign t_remote_abort = ll_remote_abort;
assign t_read_crc_ok = ll_read_crc_ok;
assign t_write_strobe = ll_write_strobe;
assign t_write_finished = ll_write_finished;
assign send_reg_stb = (dbg_t_en) ? dbg_send_reg_stb : cl_send_reg_stb;
assign send_dma_act_stb = (dbg_t_en) ? dbg_send_dma_act_stb : cl_send_dma_act_stb;
assign send_data_stb = (dbg_t_en) ? dbg_send_data_stb : cl_send_data_stb;
assign send_pio_stb = (dbg_t_en) ? dbg_send_pio_stb : cl_send_pio_stb;
assign send_dev_bits_stb = (dbg_t_en) ? dbg_send_dev_bits_stb : cl_send_dev_bits_stb;
assign dbg_pio_request = pio_request;
assign pio_transfer_count = (dbg_t_en) ? dbg_pio_transfer_count : cl_pio_transfer_count;
assign pio_direction = (dbg_t_en) ? dbg_pio_direction : cl_pio_direction;
assign pio_e_status = (dbg_t_en) ? dbg_pio_e_status : cl_pio_e_status;
assign d2h_interrupt = (dbg_t_en) ? dbg_d2h_interrupt : cl_d2h_interrupt;
assign d2h_notification = (dbg_t_en) ? dbg_d2h_notification : cl_d2h_notification;
assign d2h_status = (dbg_t_en) ? dbg_d2h_status : cl_d2h_status;
assign d2h_error = (dbg_t_en) ? dbg_d2h_error : cl_d2h_error;
assign d2h_port_mult = (dbg_t_en) ? dbg_d2h_port_mult : cl_d2h_port_mult;
assign d2h_device = (dbg_t_en) ? dbg_d2h_device : cl_d2h_device;
assign d2h_lba = (dbg_t_en) ? dbg_d2h_lba : cl_d2h_lba;
assign d2h_sector_count = (dbg_t_en) ? dbg_d2h_sector_count : cl_d2h_sector_count;
assign cl_if_data = (dbg_t_en) ? dbg_cl_if_data : if_data;
assign cl_if_ready = (dbg_t_en) ? dbg_cl_if_ready : if_ready;
assign cl_if_size = (dbg_t_en) ? dbg_cl_if_size : if_size;
assign cl_of_ready = (dbg_t_en) ? dbg_cl_of_ready : of_ready;
assign cl_of_size = (dbg_t_en) ? dbg_cl_of_size : of_size;
assign dbg_remote_abort = remote_abort;
assign dbg_xmit_error = xmit_error;
assign dbg_read_crc_fail = read_crc_fail;
assign dbg_h2d_reg_stb = h2d_reg_stb;
assign dbg_h2d_data_stb = h2d_data_stb;
assign dbg_h2d_command = h2d_command;
assign dbg_h2d_features = h2d_features;
assign dbg_h2d_cmd_bit = h2d_cmd_bit;
assign dbg_h2d_port_mult = h2d_port_mult;
assign dbg_h2d_control = h2d_control;
assign dbg_h2d_device = h2d_device;
assign dbg_h2d_lba = h2d_lba;
assign dbg_h2d_sector_count = h2d_sector_count;
endmodule
|
module faux_sata_hd_transport (
input rst, //reset
input clk,
//Trasport Layer Control/Status
output transport_layer_ready,
input send_reg_stb,
input send_dma_act_stb,
input send_data_stb,
input send_pio_stb,
input send_dev_bits_stb,
output reg remote_abort,
output reg xmit_error,
output reg read_crc_fail,
output reg h2d_reg_stb,
output reg h2d_data_stb,
output pio_request,
input [15:0] pio_transfer_count,
input pio_direction,
input [7:0] pio_e_status,
//Host to Device Registers
output reg [7:0] h2d_command,
output reg [15:0] h2d_features,
output reg h2d_cmd_bit,
output reg [7:0] h2d_control,
output reg [3:0] h2d_port_mult,
output reg [7:0] h2d_device,
output reg [47:0] h2d_lba,
output reg [15:0] h2d_sector_count,
//Device to Host Registers
input d2h_interrupt,
input d2h_notification,
input [3:0] d2h_port_mult,
input [7:0] d2h_device,
input [47:0] d2h_lba,
input [15:0] d2h_sector_count,
input [7:0] d2h_status,
input [7:0] d2h_error,
//DMA Specific Control
//Data Control
input cl_if_ready,
output reg cl_if_activate,
input [23:0] cl_if_size,
output cl_if_strobe,
input [31:0] cl_if_data,
input [1:0] cl_of_ready,
output reg [1:0] cl_of_activate,
output cl_of_strobe,
output [31:0] cl_of_data,
input [23:0] cl_of_size,
//Link Layer Interface
input link_layer_ready,
output reg ll_write_start,
input ll_write_strobe,
input ll_write_finished,
output [31:0] ll_write_data,
output [31:0] ll_write_size,
output ll_write_hold,
output ll_write_abort,
input ll_xmit_error,
input ll_read_start,
output ll_read_ready,
input [31:0] ll_read_data,
input ll_read_strobe,
input ll_read_finished,
input ll_read_crc_ok,
input ll_remote_abort
);
//Parameters
parameter IDLE = 4'h0;
parameter READ_FIS = 4'h1;
parameter WAIT_FOR_END = 4'h2;
parameter CHECK_FIS_TYPE = 4'h1;
parameter READ_H2D_REG = 4'h2;
parameter READ_DATA = 4'h3;
parameter WRITE_D2H_REG = 4'h4;
parameter WRITE_DEV_BITS = 4'h5;
parameter WRITE_PIO_SETUP = 4'h6;
parameter WRITE_DMA_ACTIVATE = 4'h7;
parameter WRITE_DMA_SETUP = 4'h8;
parameter SEND_DATA = 4'h9;
parameter RETRY = 4'hA;
//Registers/Wires
reg [3:0] state;
reg [3:0] next_state;
reg [3:0] fis_id_state;
reg [3:0] reg_read_count;
//Detect Wires
wire detect_h2d_reg;
wire detect_h2d_data;
reg send_data_fis_id;
reg detect_fis;
reg [7:0] current_fis;
//Control buffer
reg [7:0] d2h_write_ptr;
wire [31:0] d2h_reg_buffer [5:0];
wire [31:0] d2h_pio_setup [5:0];
wire [31:0] d2h_dev_bits [2:0];
wire [31:0] d2h_dma_act;
wire [31:0] d2h_data_fis_id;
//Submodules
//Asychronous Logic
assign transport_layer_ready = (state == IDLE) && link_layer_ready;
assign detect_h2d_reg = detect_fis ? (ll_read_data[7:0] == `FIS_H2D_REG) : (current_fis == `FIS_H2D_REG );
assign detect_h2d_data = detect_fis ? (ll_read_data[7:0] == `FIS_DATA) : (current_fis == `FIS_DATA );
//Device to host structural packets
assign d2h_reg_buffer[0] = {d2h_error, d2h_status, 1'b0, d2h_interrupt, 2'b00, d2h_port_mult, `FIS_D2H_REG};
assign d2h_reg_buffer[1] = {d2h_device, d2h_lba[23:0]};
assign d2h_reg_buffer[2] = {8'h00, d2h_lba[47:24]};
assign d2h_reg_buffer[3] = {16'h0000, d2h_sector_count};
assign d2h_reg_buffer[4] = 32'h0;
assign d2h_pio_setup[0] = {d2h_error, d2h_status, 1'b0, d2h_interrupt, pio_direction, 1'b0, d2h_port_mult, `FIS_PIO_SETUP};
assign d2h_pio_setup[1] = {d2h_device, d2h_lba[23:0]};
assign d2h_pio_setup[2] = {8'h00, d2h_lba[47:24]};
assign d2h_pio_setup[3] = {pio_e_status, 8'h00, d2h_sector_count};
assign d2h_pio_setup[4] = {16'h0000, pio_transfer_count};
assign d2h_dev_bits[0] = { d2h_error,
1'b0, d2h_status[6:4], 1'b0, d2h_status[2:0],
d2h_notification, d2h_interrupt, 2'b00, d2h_port_mult,
`FIS_SET_DEV_BITS};
assign d2h_dev_bits[1] = 32'h00000000;
assign d2h_dma_act = {8'h00, 8'h00, 4'h0, d2h_port_mult, `FIS_DMA_ACT};
assign d2h_data_fis_id = {8'h00, 8'h00, 4'h0, d2h_port_mult, `FIS_DATA};
//Link Layer Signals
//Write
assign ll_write_data = (send_data_fis_id) ? d2h_data_fis_id :
(state == SEND_DATA) ? cl_if_data :
((state == WRITE_D2H_REG) || send_reg_stb ) ? d2h_reg_buffer[d2h_write_ptr] :
((state == WRITE_DEV_BITS) || send_dev_bits_stb ) ? d2h_dev_bits[d2h_write_ptr] :
((state == WRITE_DMA_ACTIVATE)|| send_dma_act_stb ) ? d2h_dma_act :
((state == WRITE_PIO_SETUP) || send_pio_stb ) ? d2h_pio_setup[d2h_write_ptr] :
32'h00000000;
assign ll_write_size = (send_data_stb) ? cl_if_size + 1 :
(state == SEND_DATA) ? cl_if_size + 1 :
((state == WRITE_D2H_REG) || send_reg_stb ) ? `FIS_D2H_REG_SIZE :
((state == WRITE_DEV_BITS) || send_dev_bits_stb ) ? `FIS_SET_DEV_BITS_SIZE :
((state == WRITE_DMA_ACTIVATE) || send_dma_act_stb ) ? `FIS_DMA_ACT_SIZE :
((state == WRITE_PIO_SETUP) || send_pio_stb ) ? `FIS_PIO_SETUP_SIZE :
24'h000000;
assign ll_write_hold = (state == SEND_DATA) ? !cl_of_activate :
1'b0;
assign ll_write_abort = 1'b0;
assign cl_if_strobe = (state == SEND_DATA) ? ll_write_strobe : 0;
//Read
assign ll_read_ready = (state == READ_DATA) ? cl_of_activate :
1'b1;
assign cl_of_data = (state == READ_DATA) ? ll_read_data :
32'h00000000;
assign cl_of_strobe = (state == READ_DATA) ? ll_read_strobe :
1'b0;
//Synchronous Logic
//FIS ID State machine
always @ (posedge clk) begin
if (rst) begin
fis_id_state <= IDLE;
detect_fis <= 0;
current_fis <= 0;
end
else begin
//in order to set all the detect_* high when the actual fis is detected send this strobe
case (fis_id_state)
IDLE: begin
current_fis <= 0;
detect_fis <= 0;
if (ll_read_start) begin
detect_fis <= 1;
fis_id_state <= READ_FIS;
end
end
READ_FIS: begin
if (ll_read_strobe) begin
detect_fis <= 0;
current_fis <= ll_read_data[7:0];
fis_id_state <= WAIT_FOR_END;
end
end
WAIT_FOR_END: begin
if (ll_read_finished) begin
current_fis <= 0;
fis_id_state <= IDLE;
end
end
default: begin
fis_id_state <= IDLE;
end
endcase
end
end
//Main State machine
always @ (posedge clk) begin
if (rst) begin
state <= IDLE;
next_state <= IDLE;
d2h_write_ptr <= 0;
reg_read_count <= 0;
h2d_reg_stb <= 0;
h2d_data_stb <= 0;
h2d_command <= 0;
cl_of_activate <= 0;
//Link Layer Interface
ll_write_start <= 0;
send_data_fis_id <= 0;
h2d_command <= 0;
h2d_features <= 0;
h2d_cmd_bit <= 0;
h2d_control <= 0;
h2d_port_mult <= 0;
h2d_device <= 0;
h2d_lba <= 0;
h2d_sector_count <= 0;
cl_if_activate <= 0;
end
else begin
//Strobes
h2d_reg_stb <= 0;
h2d_data_stb <= 0;
ll_write_start <= 0;
xmit_error <= 0;
read_crc_fail <= 0;
//if there is any outptu buffers available
if ((cl_of_ready > 0) && (cl_of_activate == 0)) begin
if (cl_of_ready[0]) begin
cl_of_activate[0] <= 1;
end
else begin
cl_of_activate[1] <= 1;
end
end
//if there is any cl incomming buffers available grab it
if (cl_if_ready && !cl_if_activate) begin
cl_if_activate <= 1;
end
//Remote Abortion
if (ll_remote_abort) begin
state <= IDLE;
remote_abort <= 0;
end
if (ll_xmit_error) begin
xmit_error <= 1;
end
if (!ll_read_crc_ok) begin
read_crc_fail <= 1;
end
case (state)
IDLE: begin
d2h_write_ptr <= 0;
reg_read_count <= 0;
send_data_fis_id <= 0;
next_state <= IDLE;
//detect an incomming FIS
if (ll_read_start) begin
state <= CHECK_FIS_TYPE;
end
//Command Layer Initiated a transaction
if (link_layer_ready) begin
if (send_reg_stb) begin
ll_write_start <= 1;
state <= WRITE_D2H_REG;
end
else if (send_dev_bits_stb) begin
ll_write_start <= 1;
state <= WRITE_DEV_BITS;
end
else if (send_dma_act_stb) begin
ll_write_start <= 1;
state <= WRITE_DMA_ACTIVATE;
end
else if (send_pio_stb) begin
ll_write_start <= 1;
state <= WRITE_PIO_SETUP;
end
else if (send_data_stb) begin
ll_write_start <= 1;
send_data_fis_id <= 1;
state <= SEND_DATA;
end
end
end
CHECK_FIS_TYPE: begin
if (detect_h2d_reg) begin
h2d_features[7:0] <= ll_read_data[31:24];
h2d_command <= ll_read_data[23:16];
h2d_cmd_bit <= ll_read_data[15];
h2d_port_mult <= ll_read_data[11:8];
state <= READ_H2D_REG;
reg_read_count <= reg_read_count + 1;
end
else if (detect_h2d_data) begin
state <= READ_DATA;
end
if (ll_read_finished) begin
//unrecognized FIS
state <= IDLE;
end
end
READ_H2D_REG: begin
case (reg_read_count)
1: begin
h2d_device <= ll_read_data[31:24];
h2d_lba[23:0] <= ll_read_data[23:0];
end
2: begin
h2d_features[15:8] <= ll_read_data[31:24];
h2d_lba[47:24] <= ll_read_data[23:0];
end
3: begin
h2d_control <= ll_read_data[31:24];
h2d_sector_count <= ll_read_data[15:0];
end
4: begin
end
default: begin
end
endcase
if (ll_read_strobe) begin
reg_read_count <= reg_read_count + 1;
end
if (ll_read_finished) begin
h2d_reg_stb <= 1;
state <= IDLE;
end
end
READ_DATA: begin
//NOTE: the data_read_ready will automatically 'flow control' the data from the link layer
//so we don't have to check it here
//NOTE: We don't have to keep track of the count because the lower level will give a max of 2048 DWORDS
if (ll_read_finished) begin
h2d_data_stb <= 1;
cl_of_activate <= 0;
state <= IDLE;
end
end
WRITE_D2H_REG: begin
if (ll_write_strobe) begin
d2h_write_ptr <= d2h_write_ptr + 1;
end
if (ll_write_finished) begin
if (ll_xmit_error) begin
next_state <= state;
state <= RETRY;
end
else begin
state <= IDLE;
end
end
end
WRITE_DEV_BITS: begin
if (ll_write_strobe) begin
d2h_write_ptr <= d2h_write_ptr + 1;
end
if (ll_write_finished) begin
if (ll_xmit_error) begin
next_state <= state;
state <= RETRY;
end
else begin
state <= IDLE;
end
end
end
WRITE_PIO_SETUP: begin
if (ll_write_strobe) begin
d2h_write_ptr <= d2h_write_ptr + 1;
end
if (ll_write_finished) begin
if (ll_xmit_error) begin
next_state <= state;
state <= RETRY;
end
else begin
state <= IDLE;
end
end
end
WRITE_DMA_ACTIVATE: begin
if (ll_write_strobe) begin
d2h_write_ptr <= d2h_write_ptr + 1;
end
if (ll_write_finished) begin
if (ll_xmit_error) begin
next_state <= state;
state <= RETRY;
end
else begin
state <= IDLE;
end
end
end
WRITE_DMA_SETUP: begin
//XXX: not implemented yet
state <= IDLE;
end
SEND_DATA: begin
if (ll_write_strobe && send_data_fis_id) begin
send_data_fis_id <= 0;
end
if (ll_write_finished) begin
cl_if_activate <= 0;
state <= IDLE;
end
end
RETRY: begin
d2h_write_ptr <= 0;
reg_read_count <= 0;
if (link_layer_ready) begin
ll_write_start <= 1;
state <= next_state;
next_state <= IDLE;
end
end
default: begin
state <= IDLE;
end
endcase
end
end
endmodule
|
module faux_sata_hd_phy (
//Inputs/Outputs
input rst, //reset
input clk,
//Data Interface
output reg [31:0] tx_dout,
output reg tx_is_k,
output reg tx_set_elec_idle,
output reg rx_byte_is_aligned,
input [31:0] rx_din,
input [3:0] rx_is_k,
input rx_is_elec_idle,
input comm_reset_detect,
input comm_wake_detect,
output reg tx_comm_reset,
output reg tx_comm_wake,
output [3:0] lax_state,
output reg hd_ready,
output phy_ready
);
//Parameters
parameter IDLE = 4'h0;
parameter WAIT_FOR_NO_RESET = 4'h1;
parameter SEND_INIT = 4'h2;
parameter WAIT_FOR_WAKE = 4'h3;
parameter WAIT_FOR_NO_WAKE = 4'h4;
parameter SEND_WAKE = 4'h5;
parameter STOP_SEND_WAKE = 4'h6;
parameter SEND_CONFIGURE_END = 4'h7;
parameter WAIT_FOR_DIALTONE = 4'h8;
parameter SEND_ALIGN = 4'h9;
parameter WAIT_FOR_ALIGN = 4'hA;
parameter READY = 4'hB;
parameter SEND_FIRST_ALIGNMENT = 4'hC;
parameter SEND_SECOND_ALIGNMENT = 4'hD;
parameter INITIALIZE_TIMEOUT = 100;
//Registers/Wires
reg [3:0] state = IDLE;
reg [31:0] timer;
reg [7:0] align_count;
wire align_detected;
wire dialtone_detected;
wire timeout;
//Sub Modules
//Asynchronous Logic
assign lax_state = state;
assign align_detected = ((rx_is_k > 0) && (rx_din == `PRIM_ALIGN));
assign dialtone_detected = ((rx_is_k == 0) && (rx_din == `DIALTONE));
assign timeout = (timer == 0);
assign phy_ready = (state == READY);
//Synchronous Logic
always @ (posedge clk) begin
if (rst) begin
state <= IDLE;
tx_dout <= 0;
tx_is_k <= 0;
tx_set_elec_idle <= 1;
timer <= 0;
hd_ready <= 0;
rx_byte_is_aligned <= 0;
align_count <= 0;
end
else begin
tx_comm_reset <= 0;
tx_comm_wake <= 0;
rx_byte_is_aligned <= 0;
if (state == READY) begin
align_count <= align_count + 1;
end
if (timer > 0) begin
timer <= timer - 1;
end
if ((comm_reset_detect) && (state > WAIT_FOR_NO_RESET)) begin
$display("faux_sata_hd: Asynchronous RESET detected");
align_count <= 0;
hd_ready <= 0;
state <= WAIT_FOR_NO_RESET;
end
case (state)
IDLE: begin
align_count <= 0;
hd_ready <= 0;
tx_set_elec_idle <= 1;
if (comm_reset_detect) begin
//detected a reset from the host
$display("faux_sata_hd: RESET detected");
state <= WAIT_FOR_NO_RESET;
end
end
WAIT_FOR_NO_RESET: begin
if (!comm_reset_detect) begin
//host stopped sending reset
$display("faux_sata_hd: RESET deasserted");
hd_ready <= 0;
state <= SEND_INIT;
end
end
SEND_INIT: begin
//XXX: I may need to send more than one of these
$display("faux_sata_hd: send INIT");
tx_comm_reset <= 1;
state <= WAIT_FOR_WAKE;
end
WAIT_FOR_WAKE: begin
if (comm_wake_detect) begin
$display ("faux_sata_hd: WAKE detected");
state <= WAIT_FOR_NO_WAKE;
end
end
WAIT_FOR_NO_WAKE: begin
if (!comm_wake_detect) begin
$display ("faux_sata_hd: WAKE deasserted");
state <= SEND_WAKE;
end
end
SEND_WAKE: begin
$display ("faux_sata_hd: send WAKE");
tx_comm_wake <= 1;
state <= STOP_SEND_WAKE;
end
STOP_SEND_WAKE: begin
$display ("faux_sata_hd: stop sending WAKE");
state <= WAIT_FOR_DIALTONE;
end
WAIT_FOR_DIALTONE: begin
if (dialtone_detected) begin
$display ("faux_sata_hd: detected dialtone");
state <= SEND_ALIGN;
end
end
SEND_ALIGN: begin
$display ("faux_sata_hd: send aligns");
tx_set_elec_idle <= 0;
tx_dout <= `PRIM_ALIGN;
tx_is_k <= 1;
state <= WAIT_FOR_ALIGN;
timer <= 32'h`INITIALIZE_TIMEOUT;
rx_byte_is_aligned <= 1;
end
WAIT_FOR_ALIGN: begin
tx_is_k <= 1;
tx_dout <= `PRIM_ALIGN;
rx_byte_is_aligned <= 1;
//$display ("faux_sata_hd: waiting for aligns...");
//$display ("rx din: %h, k: %h", rx_din, rx_is_k);
if (align_detected) begin
$display ("faux_sata_hd: detected ALIGN primitive from host");
$display ("faux_sata_hd: Ready");
tx_dout <= `PRIM_ALIGN;
tx_is_k <= 1;
timer <= 0;
state <= READY;
end
else if (timeout) begin
$display ("faux_sata_hd: Timeout while waiting for an alignment from the host");
state <= IDLE;
end
end
READY: begin
hd_ready <= 1;
rx_byte_is_aligned <= 1;
tx_is_k <= 1;
tx_dout <= `PRIM_SYNC;
if (align_count == 255) begin
tx_dout <= `PRIM_ALIGN;
state <= SEND_FIRST_ALIGNMENT;
end
end
SEND_FIRST_ALIGNMENT: begin
rx_byte_is_aligned <= 1;
tx_is_k <= 1;
tx_dout <= `PRIM_ALIGN;
state <= SEND_SECOND_ALIGNMENT;
end
SEND_SECOND_ALIGNMENT: begin
rx_byte_is_aligned <= 1;
tx_is_k <= 1;
tx_dout <= `PRIM_ALIGN;
state <= READY;
end
default: begin
$display ("faux_sata_hd: In undefined state!");
state <= IDLE;
end
endcase
end
end
endmodule
|
module simple_tb ();
//Parameters
//Registers/Wires
reg rst = 0; //reset
reg clk = 0;
reg sata_clk = 0;
reg data_clk = 0;
wire command_layer_reset;
wire linkup; //link is finished
wire sata_ready;
wire sata_busy;
wire send_sync_escape;
wire hard_drive_error;
wire pio_data_ready;
reg soft_reset_en = 0;
reg [15:0] sector_count = 8;
reg [47:0] sector_address = 0;
reg [31:0] user_din;
reg user_din_stb;
wire [1:0] user_din_ready;
reg [1:0] user_din_activate;
wire [23:0] user_din_size;
wire [31:0] user_dout;
wire user_dout_ready;
reg user_dout_activate;
reg user_dout_stb;
wire [23:0] user_dout_size;
wire transport_layer_ready;
wire link_layer_ready;
wire phy_ready;
wire [31:0] tx_dout;
wire tx_is_k;
wire tx_comm_reset;
wire tx_comm_wake;
wire tx_elec_idle;
wire [31:0] rx_din;
wire [3:0] rx_is_k;
wire rx_elec_idle;
wire comm_init_detect;
wire comm_wake_detect;
wire rx_byte_is_aligned;
wire prim_scrambler_en;
wire data_scrambler_en;
//Data Interface
wire tx_set_elec_idle;
wire rx_is_elec_idle;
wire hd_ready;
wire platform_ready;
wire platform_error;
//Debug
wire [31:0] hd_data_to_host;
reg [23:0] din_count;
reg [23:0] dout_count;
reg hold = 0;
reg single_rdwr = 0;
reg [7:0] sata_command = 0;
reg [15:0] user_features = 0;
wire dma_activate_stb;
wire d2h_reg_stb;
wire pio_setup_stb;
wire d2h_data_stb;
wire dma_setup_stb;
wire set_device_bits_stb;
wire [7:0] d2h_fis;
wire d2h_interrupt;
wire d2h_notification;
wire [3:0] d2h_port_mult;
wire [7:0] d2h_device;
wire [47:0] d2h_lba;
wire [15:0] d2h_sector_count;
wire [7:0] d2h_status;
wire [7:0] d2h_error;
reg r_u2h_write_enable = 0;
reg r_h2u_read_enable = 0;
reg sata_execute_command_stb = 0;
wire [31:0] hd_data_from_host;
wire hd_read_from_host;
wire hd_write_to_host;
//hd data reader core
hd_data_reader user_2_hd_reader(
.clk (clk ),
.rst (rst ),
.enable (r_u2h_write_enable ),
.error (u2h_read_error ),
.hd_read_from_host (hd_read_from_host ),
.hd_data_from_host (hd_data_from_host )
);
//hd data writer core
hd_data_writer hd_2_user_generator(
.clk (clk ),
.rst (rst ),
.enable (r_h2u_read_enable ),
.data (hd_data_to_host ),
.strobe (hd_write_to_host )
);
//Submodules
sata_stack ss (
.clk (sata_clk ), //clock used to run the stack
.rst (rst ), //reset
.command_layer_reset (command_layer_reset ), //Reset the command layer and send a software reset to the hard drive
.platform_ready (platform_ready ), //the underlying physical platform is ready
.platform_error (platform_error ), //some bad thing happend at the transceiver level
.linkup (linkup ), //link is finished
.sata_ready (sata_ready ), //Hard drive is ready for commands
.sata_busy (sata_busy ), //Hard drive is busy executing commands
.send_sync_escape (send_sync_escape ), //This is a way to escape from a running transaction
.hard_drive_error (hard_drive_error ),
.pio_data_ready (pio_data_ready ), //Peripheral IO has some data ready
//Host to Device Control
.hard_drive_command (sata_command ), //Hard Drive commands EX: DMA Read 0x25, DMA Write 0x35
.execute_command_stb (sata_execute_command_stb),
.user_features (user_features ),
.sector_count (sector_count ),
.sector_address (sector_address ),
.dma_activate_stb (dma_activate_stb ),
.d2h_reg_stb (d2h_reg_stb ),
.pio_setup_stb (pio_setup_stb ),
.d2h_data_stb (d2h_data_stb ),
.dma_setup_stb (dma_setup_stb ),
.set_device_bits_stb (set_device_bits_stb ),
.d2h_fis (d2h_fis ),
.d2h_interrupt (d2h_interrupt ),
.d2h_notification (d2h_notification ),
.d2h_port_mult (d2h_port_mult ),
.d2h_device (d2h_device ),
.d2h_lba (d2h_lba ),
.d2h_sector_count (d2h_sector_count ),
.d2h_status (d2h_status ),
.d2h_error (d2h_error ),
//Data from host to the hard drive path
.data_in_clk (data_clk ), //Any clock to send data to the hard drive
.data_in_clk_valid (1'b1 ), //the data in clock is valid
.user_din (user_din ), //32-bit data to clock into FIFO
.user_din_stb (user_din_stb ), //Strobe to clock data into FIFO
.user_din_ready (user_din_ready ), //If one of the 2 in FIFOs are ready
.user_din_activate (user_din_activate ), //Activate one of the 2 FIFOs
.user_din_size (user_din_size ), //Number of available spots within the FIFO
.user_din_empty (user_din_empty ),
//Data from hard drive to host path
.data_out_clk (data_clk ),
.data_out_clk_valid (1'b1 ), //the data out clock is valid
.user_dout (user_dout ), //Actual data the comes from FIFO
.user_dout_ready (user_dout_ready ), //The output FIFO is ready (see below for how to use)
.user_dout_activate (user_dout_activate ), //Activate a FIFO (See below for an example on how to use)
.user_dout_stb (user_dout_stb ), //Strobe the data out of the FIFO (first word is available before strobe)
.user_dout_size (user_dout_size ), //Number of 32-bit words available
.transport_layer_ready (transport_layer_ready ),
.link_layer_ready (link_layer_ready ),
.phy_ready (phy_ready ), //sata phy layer has linked up and communication simple comm started
.phy_error (1'b0 ), //an error on the transcievers has occured
//Interface to the gigabit transcievers
.tx_dout (tx_dout ),
.tx_is_k (tx_is_k ),
.tx_comm_reset (tx_comm_reset ),
.tx_comm_wake (tx_comm_wake ),
.tx_elec_idle (tx_elec_idle ),
.tx_oob_complete (1'b1 ),
.rx_din (rx_din ),
.rx_is_k (rx_is_k ),
.rx_elec_idle (1'b0 ),
.rx_byte_is_aligned (rx_byte_is_aligned ),
.comm_init_detect (comm_init_detect ),
.comm_wake_detect (comm_wake_detect ),
//These should be set to 1 for normal operations, while debugging you can set to 0 to help debug things
.prim_scrambler_en (prim_scrambler_en ),
.data_scrambler_en (data_scrambler_en ),
.dbg_cc_lax_state ( ),
.dbg_cw_lax_state (command_write_state ),
.dbg_t_lax_state (transport_state ),
.dbg_li_lax_state ( ),
.dbg_lr_lax_state ( ),
.dbg_lw_lax_state (ll_write_state ),
.dbg_lw_lax_fstate ( ),
.dbg_ll_write_ready ( ),
.dbg_ll_paw ( ),
.dbg_ll_send_crc ( ),
.oob_state (oob_state ),
.dbg_detect_sync ( ),
.dbg_detect_r_rdy ( ),
.dbg_detect_r_ip ( ),
.dbg_detect_r_ok (dbg_detect_r_ok ),
.dbg_detect_r_err (dbg_detect_r_err ),
.dbg_detect_x_rdy ( ),
.dbg_detect_sof ( ),
.dbg_detect_eof ( ),
.dbg_detect_wtrm ( ),
.dbg_detect_cont ( ),
.dbg_detect_hold ( ),
.dbg_detect_holda ( ),
.dbg_detect_align ( ),
.dbg_detect_preq_s ( ),
.dbg_detect_preq_p ( ),
.dbg_detect_xrdy_xrdy ( ),
.dbg_send_holda ( ),
// .slw_in_data_addra (slw_in_data_addra ),
// .slw_d_count (slw_d_count ),
// .slw_write_count (slw_write_count ),
// .slw_buffer_pos (slw_buffer_pos )
.slw_in_data_addra ( ),
.slw_d_count ( ),
.slw_write_count ( ),
.slw_buffer_pos ( )
);
faux_sata_hd fshd (
.rst (rst ),
.clk (sata_clk ),
.tx_dout (rx_din ),
.tx_is_k (rx_is_k ),
.rx_din (tx_dout ),
.rx_is_k ({3'b000, tx_is_k} ),
.rx_is_elec_idle (tx_elec_idle ),
.rx_byte_is_aligned (rx_byte_is_aligned ),
.comm_reset_detect (tx_comm_reset ),
.comm_wake_detect (tx_comm_wake ),
.tx_comm_reset (comm_init_detect ),
.tx_comm_wake (comm_wake_detect ),
.hd_ready (hd_ready ),
// .phy_ready (phy_ready ),
.dbg_data_scrambler_en (data_scrambler_en ),
.dbg_hold (hold ),
.dbg_ll_write_start (0 ),
.dbg_ll_write_data (0 ),
.dbg_ll_write_size (0 ),
.dbg_ll_write_hold (0 ),
.dbg_ll_write_abort (0 ),
.dbg_ll_read_ready (0 ),
.dbg_t_en (0 ),
.dbg_send_reg_stb (0 ),
.dbg_send_dma_act_stb (0 ),
.dbg_send_data_stb (0 ),
.dbg_send_pio_stb (0 ),
.dbg_send_dev_bits_stb (0 ),
.dbg_pio_transfer_count(0 ),
.dbg_pio_direction (0 ),
.dbg_pio_e_status (0 ),
.dbg_d2h_interrupt (0 ),
.dbg_d2h_notification (0 ),
.dbg_d2h_status (0 ),
.dbg_d2h_error (0 ),
.dbg_d2h_port_mult (0 ),
.dbg_d2h_device (0 ),
.dbg_d2h_lba (0 ),
.dbg_d2h_sector_count (0 ),
.dbg_cl_if_data (0 ),
.dbg_cl_if_ready (0 ),
.dbg_cl_if_size (0 ),
.dbg_cl_of_ready (0 ),
.dbg_cl_of_size (0 ),
.hd_read_from_host (hd_read_from_host ),
.hd_data_from_host (hd_data_from_host ),
.hd_write_to_host (hd_write_to_host ),
.hd_data_to_host (hd_data_to_host )
);
//Asynchronous Logic
assign prim_scrambler_en = 1;
assign data_scrambler_en = 1;
assign platform_ready = 1;
//assign hd_data_to_host = 32'h01234567;
assign send_sync_escape = 1'b0;
assign command_layer_reset = 1'b0;
//Synchronous Logic
always #`SCLK_HALF_PERIOD sata_clk = ~sata_clk;
always #`DCLK_HALF_PERIOD data_clk = ~data_clk;
always #1 clk = ~clk;
//Simulation Control
initial begin
rst <= 1;
//$dumpfile ("design.vcd");
//$dumpvars(0, simple_tb);
#(20 * `SCLK_PERIOD);
rst <= 0;
//#(20 * `SCLK_PERIOD);
//$finish();
end
//Simulation Conditions
initial begin
sector_address <= 0;
sector_count <= 8;
single_rdwr <= 0;
sata_command <= 0;
user_features <= 0;
r_u2h_write_enable <= 0;
r_h2u_read_enable <= 0;
sata_execute_command_stb <= 0;
#(20 * `SCLK_PERIOD);
while (!linkup) begin
#(1 * `SCLK_PERIOD);
end
while (!sata_ready) begin
#(1 * `SCLK_PERIOD);
end
//Send a command
// #(700 * `SCLK_PERIOD);
//#(563 * `SCLK_PERIOD);
#(100 * `SCLK_PERIOD);
sata_command <= 8'h35; //Write
sector_count <= 1;
#(1 * `SCLK_PERIOD);
sata_execute_command_stb <= 1;
#(1 * `SCLK_PERIOD);
sata_execute_command_stb <= 0;
r_u2h_write_enable <= 1; //Read Data on the Hard Drive Side
#(1000 * `SCLK_PERIOD);
while (sata_busy) begin
#(1 * `SCLK_PERIOD);
end
#(100 * `SCLK_PERIOD);
r_u2h_write_enable <= 0;
//Put some data in the virtual hard drive
r_h2u_read_enable <= 1;
#(1000 * `SCLK_PERIOD);
sector_count <= 2;
sata_command <= 8'h25; //Read
#(1 * `SCLK_PERIOD);
sata_execute_command_stb <= 1;
#(1 * `SCLK_PERIOD);
sata_execute_command_stb <= 0;
#(1000 * `SCLK_PERIOD);
#(20 * `SCLK_PERIOD);
while (sata_busy) begin
#1;
end
r_h2u_read_enable <= 0;
//$finish();
end
/*
initial begin
hold <= 0;
#(20 * `SCLK_PERIOD);
while (!sata_busy) begin
#1;
end
#(800* `SCLK_PERIOD);
hold <= 1;
#(100 * `SCLK_PERIOD);
hold <= 0;
end
*/
/*
//inject a hold
initial begin
hold <= 0;
#(20 * `SCLK_PERIOD);
while (!write_data_en) begin
#1;
end
#(682 * `SCLK_PERIOD);
hold <= 1;
#(1 * `SCLK_PERIOD);
hold <= 0;
end
*/
/*
initial begin
sector_address <= 0;
sector_count <= 0;
#(20 * `SCLK_PERIOD);
while (!linkup) begin
#1;
end
while (busy) begin
#1;
end
//Send a command
#(824 * `SCLK_PERIOD);
write_data_en <= 1;
#(20 * `SCLK_PERIOD);
while (!busy) begin
#1;
end
write_data_en <= 0;
end
*/
//Buffer Fill/Drain
always @ (posedge data_clk) begin
if (rst) begin
user_din <= 0;
user_din_stb <= 0;
user_din_activate <= 0;
din_count <= 0;
user_dout_activate <= 0;
user_dout_stb <= 0;
dout_count <= 0;
end
else begin
user_din_stb <= 0;
user_dout_stb <= 0;
if ((user_din_ready > 0) && (user_din_activate == 0)) begin
din_count <= 0;
if (user_din_ready[0]) begin
user_din_activate[0] <= 1;
end
else begin
user_din_activate[1] <= 1;
end
end
if (din_count >= user_din_size) begin
user_din_activate <= 0;
end
else if (user_din_activate > 0) begin
user_din_stb <= 1;
user_din <= din_count;
din_count <= din_count + 1;
end
if (user_dout_ready && !user_dout_activate) begin
dout_count <= 0;
user_dout_activate <= 1;
end
if (dout_count >= user_dout_size) begin
user_dout_activate <= 0;
end
else if (user_dout_activate) begin
user_dout_stb <= 1;
end
end
end
endmodule
|
module hd_data_reader (
input clk,
input rst,
input enable,
output reg error,
input hd_read_from_host,
input [31:0] hd_data_from_host
);
//Registers/Wires
reg prev_enable;
wire posedge_enable;
reg [31:0] test_data;
//Submodules
//Asynchronous Logic
assign posedge_enable = (!prev_enable && enable);
//Synchronous Logic
always @ (posedge clk) begin
if (rst) begin
prev_enable <= 0;
error <= 0;
test_data <= 0;
end
else begin
prev_enable <= enable;
if (posedge_enable) begin
error <= 0;
test_data <= 0;
end
else begin
if (hd_read_from_host) begin
if (hd_data_from_host != test_data) begin
error <= 1;
end
test_data <= test_data + 1;
end
end
end
end
endmodule
|
module test_out (
input clk,
input rst,
input enable,
output reg busy,
output reg error,
input ready,
output reg activate,
input [23:0] size,
input [31:0] data,
output reg strobe,
output reg [23:0] total_count
);
reg [31:0] test_value;
reg [23:0] count;
always @ (posedge clk) begin
if (rst) begin
activate <= 0;
count <= 0;
test_value <= 32'h0;
error <= 0;
busy <= 0;
total_count <= 0;
strobe <= 0;
end
else begin
busy <= 0;
strobe <= 0;
//The user is not asking to check anything
if (!enable) begin
//activate <= 0;
//count <= 0;
test_value <= 32'h0;
error <= 0;
total_count <= 0;
end
//Looking for total count
//busy <= 1;
if (ready && !activate) begin
count <= 0;
activate <= 1;
end
else if (activate) begin
busy <= 1;
if (count < size) begin
strobe <= 1;
total_count <= total_count + 1;
count <= count + 1;
if ((data != test_value) && enable) begin
error <= 1;
end
end
else begin
activate <= 0;
end
end
if (strobe) begin
test_value <= test_value + 1;
end
end
end
endmodule
|
module sata_transport_layer (
input rst, //reset
input clk,
input phy_ready,
//Transport Layer Control/Status
output transport_layer_ready,
input sync_escape,
output reg d2h_reg_stb,
output reg dma_activate_stb,
output reg d2h_data_stb,
output reg dma_setup_stb,
output reg pio_setup_stb,
output reg set_device_bits_stb,
output reg remote_abort,
output xmit_error,
output read_crc_error,
input send_command_stb,
input send_control_stb,
input send_data_stb,
//PIO
output reg pio_response,
output reg pio_direction,
output reg [15:0] pio_transfer_count,
output reg [7:0] pio_e_status,
//Host to Device Registers
input [7:0] h2d_command,
input [15:0] h2d_features,
input [7:0] h2d_control,
input [3:0] h2d_port_mult,
input [7:0] h2d_device,
input [47:0] h2d_lba,
input [15:0] h2d_sector_count,
//Device to Host Registers
output reg [7:0] d2h_fis,
output reg d2h_interrupt,
output reg d2h_notification,
output reg [3:0] d2h_port_mult,
output reg [7:0] d2h_device,
output reg [47:0] d2h_lba,
output reg [15:0] d2h_sector_count,
output reg [7:0] d2h_status,
output reg [7:0] d2h_error,
//DMA Specific Control
//Data Control
input cl_if_ready,
output reg cl_if_activate,
input [23:0] cl_if_size,
output cl_if_strobe,
input [31:0] cl_if_data,
input [1:0] cl_of_ready,
output reg [1:0] cl_of_activate,
output cl_of_strobe,
output [31:0] cl_of_data,
input [23:0] cl_of_size,
//Link Layer Interface
input link_layer_ready,
output ll_sync_escape,
output ll_write_start,
input ll_write_strobe,
input ll_write_finished,
output [31:0] ll_write_data,
output [23:0] ll_write_size,
output ll_write_hold,
output ll_write_abort,
input ll_xmit_error,
input ll_read_start,
output ll_read_ready,
input [31:0] ll_read_data,
input ll_read_strobe,
input ll_read_finished,
input ll_read_crc_ok,
input ll_remote_abort,
output [3:0] lax_state
);
//Parameters
parameter IDLE = 4'h0;
parameter READ_FIS = 4'h1;
parameter WAIT_FOR_END = 4'h2;
parameter CHECK_FIS_TYPE = 4'h1;
parameter WRITE_H2D_REG = 4'h2;
parameter RETRY = 4'h3;
parameter READ_D2H_REG = 4'h4;
parameter READ_PIO_SETUP = 4'h5;
parameter READ_SET_DEVICE_BITS = 4'h6;
parameter DMA_ACTIVATE = 4'h7;
parameter SEND_DATA = 4'h8;
parameter READ_DATA = 4'h9;
//Registers/Wires
reg [3:0] fis_id_state;
reg [7:0] current_fis;
reg [3:0] state;
reg detect_fis;
wire processing_fis;
//data direction
wire data_direction;
//Detect FIS from the device
wire detect_d2h_reg;
wire detect_dma_activate;
wire detect_dma_setup;
wire detect_d2h_data;
wire detect_pio_setup;
wire detect_set_device_bits;
//control data signals
wire [31:0] register_fis [5:0];
reg [7:0] register_fis_ptr;
reg cmd_bit;
reg reg_write_start;
wire [31:0] reg_write_data;
wire [23:0] reg_write_size;
reg reg_write_ready;
wire reg_write_hold;
wire reg_write_abort;
wire reg_write_strobe;
//read register
wire reg_read;
wire reg_write;
reg [7:0] reg_read_count;
wire reg_read_stb;
//data state machine signals
reg data_write_start;
wire data_write_strobe;
wire data_read_strobe;
wire [23:0] data_write_size;
wire [31:0] data_write_data;
wire data_write_hold;
wire data_write_abort;
reg data_read_ready;
reg send_data_fis_id;
reg ll_write_finished_en;
//Asnchronous Logic
assign lax_state = state;
assign transport_layer_ready = (state == IDLE) && link_layer_ready;
assign ll_sync_escape = sync_escape;
assign xmit_error = ll_xmit_error;
//Attach Control/Data Signals to link layer depending on the conditions
//Write Control
assign ll_write_start = (reg_write) ? reg_write_start : data_write_start;
assign ll_write_data = (reg_write) ? register_fis[register_fis_ptr] : data_write_data;
assign ll_write_size = (reg_write) ? reg_write_size : data_write_size;
assign ll_write_hold = (reg_write) ? 1'b0 : data_write_hold;
assign ll_write_abort = (reg_write) ? 1'b0 : data_write_abort;
assign cl_if_strobe = (reg_write) ? 1'b0 : (!send_data_fis_id && data_write_strobe);
//Read Control
assign ll_read_ready = (reg_read) ? 1'b1 : data_read_ready;
assign cl_of_strobe = (reg_read) ? 1'b0 : ((state == READ_DATA) && data_read_strobe);
assign cl_of_data = ll_read_data;
//Data Register Write Control Signals
assign data_write_data = (send_data_fis_id) ? {24'h000, `FIS_DATA} : cl_if_data;
//the first DWORD is the FIS ID
assign data_write_size = cl_if_size + 24'h1;
//Add 1 to the size so that there is room for the FIS ID
assign data_write_strobe = ll_write_strobe;
assign data_read_strobe = ll_read_strobe;
assign data_write_hold = 1'b0;
//There should never be a hold on the data becuase the CL will set it up
assign data_write_abort = 1'b0;
assign read_crc_error = !ll_read_crc_ok;
//H2D Register Write control signals
assign reg_write_strobe = ll_write_strobe;
assign reg_write_size = `FIS_H2D_REG_SIZE;
assign reg_write_hold = 1'b0;
assign reg_write_abort = 1'b0;
assign reg_write = (state == WRITE_H2D_REG) || (send_command_stb || send_control_stb);
//D2H Register Read control signals
assign reg_read = (state == READ_D2H_REG) || detect_d2h_reg ||
(state == READ_PIO_SETUP) || detect_pio_setup ||
(state == READ_SET_DEVICE_BITS) || detect_set_device_bits;
assign reg_read_stb = ll_read_strobe;
//Data Read control signals
//Detect Signals
assign processing_fis = (state == READ_FIS);
assign detect_d2h_reg = detect_fis ? (ll_read_data[7:0] == `FIS_D2H_REG) : (current_fis == `FIS_D2H_REG );
assign detect_dma_activate = detect_fis ? (ll_read_data[7:0] == `FIS_DMA_ACT) : (current_fis == `FIS_DMA_ACT );
assign detect_d2h_data = detect_fis ? (ll_read_data[7:0] == `FIS_DATA) : (current_fis == `FIS_DATA );
assign detect_dma_setup = detect_fis ? (ll_read_data[7:0] == `FIS_DMA_SETUP) : (current_fis == `FIS_DMA_SETUP );
assign detect_pio_setup = detect_fis ? (ll_read_data[7:0] == `FIS_PIO_SETUP) : (current_fis == `FIS_PIO_SETUP );
assign detect_set_device_bits = detect_fis ? (ll_read_data[7:0] == `FIS_SET_DEV_BITS) : (current_fis == `FIS_SET_DEV_BITS );
assign register_fis[0] = {h2d_features[7:0], h2d_command, cmd_bit, 3'b000, h2d_port_mult, `FIS_H2D_REG};
assign register_fis[1] = {h2d_device, h2d_lba[23:0]};
assign register_fis[2] = {h2d_features[15:8], h2d_lba[47:24]};
assign register_fis[3] = {h2d_control, 8'h00, h2d_sector_count};
assign register_fis[4] = {32'h00000000};
//Synchronous Logic
//FIS ID State machine
always @ (posedge clk) begin
if (rst) begin
fis_id_state <= IDLE;
detect_fis <= 0;
current_fis <= 0;
d2h_fis <= 0;
end
else begin
//in order to set all the detect_* high when the actual fis is detected send this strobe
if(ll_read_finished) begin
current_fis <= 0;
fis_id_state <= IDLE;
end
else begin
case (fis_id_state)
IDLE: begin
current_fis <= 0;
detect_fis <= 0;
if (ll_read_start) begin
detect_fis <= 1;
fis_id_state <= READ_FIS;
end
end
READ_FIS: begin
if (ll_read_strobe) begin
detect_fis <= 0;
current_fis <= ll_read_data[7:0];
d2h_fis <= ll_read_data[7:0];
fis_id_state <= WAIT_FOR_END;
end
end
WAIT_FOR_END: begin
if (ll_read_finished) begin
current_fis <= 0;
fis_id_state <= IDLE;
end
end
default: begin
fis_id_state <= IDLE;
end
endcase
end
end
end
//main DATA state machine
always @ (posedge clk) begin
if (rst) begin
state <= IDLE;
cl_of_activate <= 0;
cl_if_activate <= 0;
data_read_ready <= 0;
//Data Send
send_data_fis_id <= 0;
//H2D Register
register_fis_ptr <= 0;
reg_write_start <= 0;
//D2H Register
reg_read_count <= 0;
//Device Status
d2h_interrupt <= 0;
d2h_notification <= 0;
d2h_port_mult <= 0;
d2h_lba <= 0;
d2h_sector_count <= 0;
d2h_status <= 0;
d2h_error <= 0;
d2h_reg_stb <= 0;
d2h_data_stb <= 0;
pio_setup_stb <= 0;
set_device_bits_stb <= 0;
dma_activate_stb <= 0;
dma_setup_stb <= 0;
remote_abort <= 0;
cmd_bit <= 0;
//PIO
pio_transfer_count <= 0;
pio_e_status <= 0;
pio_direction <= 0;
pio_response <= 0;
data_write_start <= 0;
ll_write_finished_en <= 0;
end
else begin
//Strobed signals
if (phy_ready) begin
//only deassert a link layer strobe when Phy is ready and not sending aligns
data_write_start <= 0;
reg_write_start <= 0;
end
d2h_reg_stb <= 0;
d2h_data_stb <= 0;
pio_setup_stb <= 0;
set_device_bits_stb <= 0;
dma_activate_stb <= 0;
dma_setup_stb <= 0;
remote_abort <= 0;
d2h_device <= 0;
//Always attempt to get a free buffer
if ((cl_of_activate == 0) && (cl_of_ready > 0)) begin
if (cl_of_ready[0]) begin
cl_of_activate[0] <= 1;
end
else begin
cl_of_activate[1] <= 1;
end
data_read_ready <= 1;
end
else if (cl_of_activate == 0) begin
//XXX: NO BUFFER AVAILABLE!!!! Can't accept new data from the Hard Drive
data_read_ready <= 0;
end
//Always attempt to get the incomming buffer
if (cl_if_ready && !cl_if_activate) begin
cl_if_activate <= 1;
end
if (ll_write_finished) begin
ll_write_finished_en <= 1;
end
case (state)
IDLE: begin
register_fis_ptr <= 0;
reg_read_count <= 0;
cmd_bit <= 0;
ll_write_finished_en <= 0;
//Detect a FIS
if(ll_read_start) begin
//detect the start of a frame
state <= CHECK_FIS_TYPE;
//Clear Errors when a new transaction starts
end
//Send Register
if (send_command_stb || send_control_stb) begin
//Clear Errors when a new transaction starts
if (send_command_stb) begin
cmd_bit <= 1;
end
else if (send_control_stb) begin
cmd_bit <= 0;
end
reg_write_start <= 1;
state <= WRITE_H2D_REG;
end
//Send Data
else if (send_data_stb) begin
//Clear Errors when a new transaction starts
data_write_start <= 1;
send_data_fis_id <= 1;
state <= SEND_DATA;
end
end
CHECK_FIS_TYPE: begin
if (detect_dma_setup) begin
//XXX: Future work!
reg_read_count <= reg_read_count + 8'h1;
state <= IDLE;
end
else if (detect_dma_activate) begin
//hard drive is ready to receive data
state <= DMA_ACTIVATE;
reg_read_count <= reg_read_count + 8'h1;
//state <= IDLE;
end
else if (detect_d2h_data) begin
//incomming data, because the out FIFO is directly connected to the output during a read
state <= READ_DATA;
end
else if (detect_d2h_reg) begin
//store the error, status interrupt from this read
d2h_status <= ll_read_data[23:16];
d2h_error <= ll_read_data[31:24];
d2h_interrupt <= ll_read_data[14];
d2h_port_mult <= ll_read_data[11:8];
state <= READ_D2H_REG;
reg_read_count <= reg_read_count + 8'h1;
end
else if (detect_pio_setup) begin
//store the error, status, direction interrupt from this read
pio_response <= 1;
d2h_status <= ll_read_data[23:16];
d2h_error <= ll_read_data[31:24];
d2h_interrupt <= ll_read_data[14];
pio_direction <= ll_read_data[13];
d2h_port_mult <= ll_read_data[11:8];
state <= READ_PIO_SETUP;
reg_read_count <= reg_read_count + 8'h1;
end
else if (detect_set_device_bits) begin
//store the error, a subset of the status bit and the interrupt
state <= IDLE;
d2h_status[6:4] <= ll_read_data[22:20];
d2h_status[2:0] <= ll_read_data[18:16];
d2h_error <= ll_read_data[31:24];
d2h_notification <= ll_read_data[15];
d2h_interrupt <= ll_read_data[14];
d2h_port_mult <= ll_read_data[11:8];
state <= READ_SET_DEVICE_BITS;
end
else if (ll_read_finished) begin
//unrecognized FIS
state <= IDLE;
end
end
WRITE_H2D_REG: begin
if (register_fis_ptr < `FIS_H2D_REG_SIZE) begin
if (reg_write_strobe) begin
register_fis_ptr <= register_fis_ptr + 8'h1;
end
end
if (ll_write_finished_en) begin
if (ll_xmit_error) begin
state <= RETRY;
end
else begin
state <= IDLE;
end
end
end
RETRY: begin
if (link_layer_ready) begin
ll_write_finished_en <= 0;
reg_write_start <= 1;
register_fis_ptr <= 0;
state <= WRITE_H2D_REG;
end
end
READ_D2H_REG: begin
case (reg_read_count)
1: begin
d2h_device <= ll_read_data[31:24];
d2h_lba[23:0] <= ll_read_data[23:0];
end
2: begin
d2h_lba[47:24] <= ll_read_data[23:0];
end
3: begin
d2h_sector_count <= ll_read_data[15:0];
end
4: begin
end
default: begin
end
endcase
if (reg_read_stb) begin
reg_read_count <= reg_read_count + 8'h1;
end
if (ll_read_finished) begin
d2h_reg_stb <= 1;
state <= IDLE;
end
end
READ_PIO_SETUP: begin
case (reg_read_count)
1: begin
d2h_device <= ll_read_data[31:24];
d2h_lba[23:0] <= ll_read_data[23:0];
end
2: begin
d2h_lba[47:24] <= ll_read_data[23:0];
end
3: begin
d2h_sector_count <= ll_read_data[15:0];
pio_e_status <= ll_read_data[31:24];
end
4: begin
pio_transfer_count <= ll_read_data[15:0];
end
default: begin
end
endcase
if (reg_read_stb) begin
reg_read_count <= reg_read_count + 8'h1;
end
if (ll_read_finished) begin
pio_setup_stb <= 1;
state <= IDLE;
end
end
READ_SET_DEVICE_BITS: begin
state <= IDLE;
set_device_bits_stb <= 1;
end
DMA_ACTIVATE: begin
state <= IDLE;
dma_activate_stb <= 1;
end
SEND_DATA: begin
if (ll_write_strobe && send_data_fis_id) begin
send_data_fis_id <= 0;
end
if (ll_write_finished_en) begin
cl_if_activate <= 0;
state <= IDLE;
if (pio_response) begin
//write the end status to the status pin
d2h_status <= pio_e_status;
end
end
end
READ_DATA: begin
//NOTE: the data_read_ready will automatically 'flow control' the data from the link layer
//so we don't have to check it here
//NOTE: We don't have to keep track of the count because the lower level will give a max of 2048 DWORDS
if (ll_read_finished) begin
//deactivate FIFO
d2h_data_stb <= 1;
cl_of_activate <= 0;
state <= IDLE;
if (pio_response) begin
//write the end status to the status pin
d2h_status <= pio_e_status;
end
end
end
default: begin
state <= IDLE;
end
endcase
if (sync_escape) begin
state <= IDLE;
end
end
end
endmodule
|
module sata_platform (
input rst,
input tx_comm_reset,
input tx_comm_wake,
output comm_init_detect,
output comm_wake_detect,
output rx_elec_idle,
input tx_elec_idle,
output rx_byte_is_aligned,
input [31:0] phy_tx_dout,
input phy_tx_isk,
output [31:0] phy_rx_din,
output [3:0] phy_rx_isk,
//Clock Interface
input mgtclk_in,
output reg cnt_rst,
output pll_locked,
output clk_75mhz,
output platform_ready,
output TXP0_OUT,
output TXN0_OUT,
input RXP0_IN,
input RXN0_IN,
output GTX115_TXP0_OUT,
output GTX115_TXN0_OUT,
input GTX115_RXP0_IN,
input GTX115_RXN0_IN
);
//Parameters
//Registers/Wires
//Submodules
//Asynchronous Logic
//Synchronous Logic
endmodule
|
module sata_phy_layer (
input rst, //reset
input clk,
input platform_ready, //the underlying physical platform is
output platform_error,
output linkup, //link is finished
output [31:0] tx_dout,
output tx_is_k,
output tx_comm_reset,
output tx_comm_wake,
output tx_elec_idle,
input tx_oob_complete,
input [31:0] rx_din,
input [3:0] rx_is_k,
input rx_elec_idle,
input rx_byte_is_aligned,
input comm_init_detect,
input comm_wake_detect,
output phy_ready,
input phy_error,
output [3:0] lax_state
);
//Parameters
parameter NOT_READY = 4'h0;
parameter SEND_FIRST_ALIGN = 4'h1;
parameter SEND_SECOND_ALIGN = 4'h2;
parameter READY = 4'h3;
//Registers/Wires
reg [3:0] state;
reg [7:0] align_count;
//OOB Control
wire [31:0] oob_tx_dout;
wire oob_tx_is_k;
//Phy Control
wire [31:0] phy_tx_dout;
wire phy_tx_is_k;
//wire align_detected;
wire oob_platform_error;
reg phy_platform_error;
//Submodules
oob_controller oob (
.rst (rst ),
.clk (clk ),
//OOB controller
.phy_error (phy_error ),
.platform_ready (platform_ready ),
.platform_error (oob_platform_error ),
.linkup (linkup ),
//Platform Control
.tx_dout (oob_tx_dout ),
.tx_is_k (oob_tx_is_k ),
.tx_comm_reset (tx_comm_reset ),
.tx_comm_wake (tx_comm_wake ),
.tx_set_elec_idle (tx_elec_idle ),
.tx_oob_complete (tx_oob_complete ),
.rx_din (rx_din ),
.rx_is_k (rx_is_k ),
.comm_init_detect (comm_init_detect ),
.comm_wake_detect (comm_wake_detect ),
.rx_is_elec_idle (rx_elec_idle ),
.rx_byte_is_aligned (rx_byte_is_aligned ),
.lax_state (lax_state )
);
//Asynchronous Logic
assign tx_dout = !linkup ? oob_tx_dout : phy_tx_dout;
assign tx_is_k = !linkup ? oob_tx_is_k : phy_tx_is_k;
assign phy_tx_dout = `PRIM_ALIGN;
assign phy_tx_is_k = 1;
//assign align_detected = ((rx_is_k > 0) && (rx_din == `PRIM_ALIGN) && !phy_error);
//assign phy_ready = ((state == READY) && (!align_detected));
assign phy_ready = (state == READY);
assign platform_error = oob_platform_error || phy_platform_error;
//Synchronous Logic
always @ (posedge clk) begin
if (rst) begin
state <= NOT_READY;
align_count <= 0;
phy_platform_error<= 0;
end
else begin
if (state == READY) begin
align_count <= align_count + 8'h01;
end
case (state)
NOT_READY: begin
align_count <= 0;
phy_platform_error <= 0;
if (linkup) begin
`ifdef VERBOSE
$display ("sata_phy_layer: linkup! send aligns");
`endif
state <= SEND_FIRST_ALIGN;
end
end
SEND_FIRST_ALIGN: begin
state <= SEND_SECOND_ALIGN;
end
SEND_SECOND_ALIGN: begin
state <= READY;
end
READY: begin
if (align_count == 255) begin
state <= SEND_FIRST_ALIGN;
`ifdef VERBOSE
$display ("sata_phy_layer: linkup! send alignment dwords");
`endif
end
if (phy_error) begin
phy_platform_error <= 1;
end
end
default: begin
end
endcase
end
end
endmodule
|
module oob_controller (
input rst, //reset
input clk,
input platform_ready, //the underlying physical platform is
output reg platform_error, //Underlyaing physal platform received an error, this should probably be a reset
output reg linkup, //link is finished
output reg tx_comm_reset, //send a init OOB signal
output reg tx_comm_wake, //send a wake OOB signal
input tx_oob_complete, //Phy has said we are finished with this OOB transaction
input comm_init_detect, //detected an init
input comm_wake_detect, //detected a wake on the rx lines
input [31:0] rx_din,
input [3:0] rx_is_k,
input rx_is_elec_idle,
input rx_byte_is_aligned,
input phy_error,
output reg [31:0] tx_dout,
output reg tx_is_k,
output reg tx_set_elec_idle,
output [3:0] lax_state
);
//platform signals
//Parameters
//States
parameter IDLE = 4'h0;
parameter SEND_RESET = 4'h1;
parameter WAIT_FOR_INIT = 4'h2;
parameter WAIT_FOR_NO_INIT = 4'h3;
parameter WAIT_FOR_CONFIGURE_END = 4'h4;
parameter SEND_WAKE = 4'h5;
parameter WAIT_FOR_WAKE = 4'h6;
parameter WAIT_FOR_NO_WAKE = 4'h7;
parameter WAIT_FOR_IDLE = 4'h8;
parameter WAIT_FOR_ALIGN = 4'h9;
parameter SEND_ALIGN = 4'hA;
parameter DETECT_SYNC = 4'hB;
parameter READY = 4'hC;
//Registers/Wires
reg [3:0] state;
reg [31:0] timer;
reg [1:0] no_align_count;
reg [3:0] retries;
//timer used to send 'INITs', WAKEs' and read them
wire timeout;
wire align_detected;
wire sync_detected;
//Submodules
//Asynchronous Logic
assign timeout = (timer == 0);
//assign align_detected = ((rx_is_k > 0) && (rx_din == `PRIM_ALIGN) && !phy_error);
//assign align_detected = ((rx_is_k > 0) && (rx_din == `PRIM_ALIGN));
assign align_detected = ((rx_is_k > 0) && (rx_din == `PRIM_ALIGN) && rx_byte_is_aligned);
assign sync_detected = ((rx_is_k > 0) && (rx_din == `PRIM_SYNC));
assign lax_state = state;
//Synchronous Logic
initial begin
tx_set_elec_idle <= 1;
end
always @ (posedge clk) begin
if (rst) begin
state <= IDLE;
linkup <= 0;
timer <= 0;
tx_comm_reset <= 0;
tx_comm_wake <= 0;
tx_dout <= 0;
tx_is_k <= 0;
tx_set_elec_idle <= 1;
no_align_count <= 0;
platform_error <= 0;
retries <= 0;
end
else begin
//to support strobes, continuously reset the following signals
tx_comm_reset <= 0;
tx_comm_wake <= 0;
tx_is_k <= 0;
//timer (when reache 0 timeout has occured)
if (timer > 0) begin
timer <= timer - 1;
end
//main state machine, if this reaches ready an initialization sequence has completed
case (state)
IDLE: begin
platform_error <= 0;
linkup <= 0;
tx_set_elec_idle <= 1;
if (platform_ready) begin
$display ("oob_controller: send RESET");
//the platform is ready
// PLL has locked onto a clock
// DCM has generated the correct clocks
timer <= 32'h000000A2;
state <= SEND_RESET;
tx_comm_reset <= 1;
end
end
SEND_RESET: begin
//XXX: In the groundhog COMM RESET was continuously issued for a long period of time
//send the INIT sequence, this will initiate a communication with the
//SATA hard drive, or reset it so that it can be initiated to state
//strobe the comm init so that the platform will send an INIT OOB signal
if (timeout || tx_oob_complete) begin
timer <= `INITIALIZE_TIMEOUT;
state <= WAIT_FOR_INIT;
$display ("oob_controller: wait for INIT");
end
end
WAIT_FOR_INIT: begin
//wait for a response from the SATA harddrive, if the timeout occurs
//go back to the SEND_RESET state
if (comm_init_detect) begin
//HD said 'sup' go to a wake
//timer <= 0;
timer <= 32'h00001000;
state <= WAIT_FOR_NO_INIT;
$display ("oob_controller: wait for INIT to go low");
end
if (timeout) begin
$display ("oob_controller: timed out while waiting for INIT");
state <= IDLE;
end
end
WAIT_FOR_NO_INIT: begin
//wait for the init signal to go low from the device
if (!comm_init_detect && (timeout || tx_oob_complete)) begin
$display ("oob_controller: INIT deasserted");
$display ("oob_controller: start configuration");
state <= WAIT_FOR_CONFIGURE_END;
end
end
WAIT_FOR_CONFIGURE_END: begin
$display ("oob_controller: System is configured");
state <= SEND_WAKE;
timer <= 32'h0000009B;
tx_comm_wake <= 1;
//end
end
SEND_WAKE: begin
//XXX: In the groundhog COMM WAKE was continuously send for a long period of time
//Send the WAKE sequence to the hard drive to initiate a wakeup sequence
//XXX: Is this timeout correct?
//880uS
if (timeout || tx_oob_complete) begin
//timer <= 32'd`INITIALIZE_TIMEOUT;
timer <= 32'h000203AD;
state <= WAIT_FOR_WAKE;
end
end
WAIT_FOR_WAKE: begin
//Wait for the device to send a COMM Wake
if (comm_wake_detect) begin
//Found a comm wake, now wait for the device to stop sending WAKE
timer <= 0;
state <= WAIT_FOR_NO_WAKE;
$display ("oob_controller: WAKE detected");
end
if (timeout) begin
//Timeout occured before reading WAKE
state <= IDLE;
$display ("oob_controller: timed out while waiting for WAKE to be asserted");
end
end
WAIT_FOR_NO_WAKE: begin
if (!comm_wake_detect) begin
//The device stopped sending comm wake
//XXX: Is this timeout correct?
//880uS
$display ("oob_controller: detected WAKE deasserted");
$display ("oob_controller: Send Dialtone, wait for ALIGN");
//Going to add more timeout
//timer <= 32'h0203AD;
timer <= 32'h0203AD;
state <= WAIT_FOR_ALIGN;
//state <= WAIT_FOR_IDLE;
retries <= 4;
end
end
/*
WAIT_FOR_IDLE: begin
if (!rx_is_elec_idle) begin
state <= WAIT_FOR_ALIGN;
timer <= 32'h0101D0;
end
else if (timeout) begin
if (retries > 0) begin
timer <= 32'h0203AD;
retries <= retries - 1;
end
if (retries == 0) begin
state <= IDLE;
end
end
end
*/
WAIT_FOR_ALIGN: begin
//transmit the 'dialtone' continuously
//since we need to start sending actual data (not OOB signals, get out
// of tx idle)
tx_set_elec_idle <= 0;
//a sequence of 0's and 1's
tx_dout <= `DIALTONE;
tx_is_k <= 0;
//$display ("rx din: %h, k: %h", rx_din, rx_is_k);
if (align_detected) begin
//we got something from the device!
timer <= 0;
//now send an align from my side
state <= SEND_ALIGN;
no_align_count <= 0;
$display ("oob_controller: ALIGN detected");
$display ("oob_controller: Send out my ALIGNs");
end
if (timeout) begin
//didn't read an align in time :( reset
$display ("oob_controller: timed out while waiting for AIGN");
state <= IDLE;
end
end
SEND_ALIGN: begin
tx_dout <= `PRIM_ALIGN;
tx_is_k <= 1;
if (!align_detected) begin
$display ("oob_controller: detected ALIGN deasserted");
//XXX: Groundhog detects the SYNC primitve before declaring linkup
if (no_align_count == 3) begin
$display ("oob_controller: ready");
state <= READY;
end
else begin
no_align_count <= no_align_count + 2'b01;
end
end
end
DETECT_SYNC: begin
if (sync_detected) begin
state <= READY;
end
end
READY: begin
linkup <= 1;
/*
if (phy_error) begin
platform_error <= 1;
end
*/
if (comm_init_detect) begin
state <= IDLE;
end
end
default: begin
state <= IDLE;
end
endcase
end
end
endmodule
|
module sata_link_layer (
input rst, //reset
input clk,
//Command Interface
output link_layer_ready,
input sync_escape,
output post_align_write,
input hold,
//Phy Layer
input phy_ready,
output write_ready,
input platform_ready,
//XXX: I probably need some feedback to indicate that there is room to write
output [31:0] tx_dout,
output tx_is_k,
input [31:0] rx_din,
input [3:0] rx_is_k,
input write_start,
output write_strobe,
input [31:0] write_data,
input [23:0] write_size,
input write_hold,
output write_finished,
input write_abort,
output read_start,
output read_strobe,
output [31:0] read_data,
input read_ready,
output read_finished,
output read_crc_ok,
output remote_abort,
output xmit_error,
output wsize_z_error,
input prim_scrambler_en,
input data_scrambler_en,
input is_device,
output [3:0] lax_i_state,
output [3:0] lax_r_state,
output [3:0] lax_w_state,
output [3:0] lax_w_fstate,
//Detection
output detect_sync,
output detect_r_rdy,
output detect_r_ip,
output detect_r_ok,
output detect_r_err,
output detect_x_rdy,
output detect_sof,
output detect_eof,
output detect_wtrm,
output detect_cont,
output detect_hold,
output detect_holda,
output detect_align,
output detect_preq_s,
output detect_preq_p,
output detect_xrdy_xrdy,
output send_crc,
output dbg_send_holda,
output [23:0] in_data_addra,
output [12:0] d_count,
output [12:0] write_count,
output [3:0] buffer_pos
);
//Parameters
parameter NOT_READY = 4'h0;
parameter IDLE = 4'h1;
parameter PM_DENY = 4'h2;
//Registers/Wires
reg [3:0] state;
//Primatives
reg send_sync;
reg send_pmack;
reg send_pmnack;
wire sli_idle;
wire [31:0] sli_tx_dout;
wire sli_tx_is_k;
reg write_en;
wire write_idle;
wire [31:0] slw_tx_dout;
wire slw_tx_is_k;
reg read_en;
wire read_idle;
wire [31:0] slr_tx_dout;
wire slr_tx_is_k;
wire [31:0] ll_tx_dout;
wire ll_tx_is_k;
wire last_prim;
//Submodules
//XXX: I can probably use only one CRC checker for the entire stack but to make it easier I'm gonna use two for
//the read and write path
//XXX: maybe add a scrambler for PRIM scrambling
cont_controller ccon (
.rst (rst ),
.clk (clk ),
.phy_ready (phy_ready ),
.xmit_cont_en (prim_scrambler_en ),
.last_prim (last_prim ),
.rx_din (rx_din ),
.rx_is_k (rx_is_k ),
.ll_tx_din (ll_tx_dout ),
.ll_tx_is_k (ll_tx_is_k ),
.cont_tx_dout (tx_dout ),
.cont_tx_is_k (tx_is_k ),
.detect_sync (detect_sync ),
.detect_r_rdy (detect_r_rdy ),
.detect_r_ip (detect_r_ip ),
.detect_r_err (detect_r_err ),
.detect_r_ok (detect_r_ok ),
.detect_x_rdy (detect_x_rdy ),
.detect_sof (detect_sof ),
.detect_eof (detect_eof ),
.detect_wtrm (detect_wtrm ),
.detect_cont (detect_cont ),
.detect_hold (detect_hold ),
.detect_holda (detect_holda ),
.detect_preq_s (detect_preq_s ),
.detect_preq_p (detect_preq_p ),
.detect_align (detect_align ),
.detect_xrdy_xrdy (detect_xrdy_xrdy )
);
sata_link_layer_write slw (
.rst (rst ),
.clk (clk ),
.en (write_en ),
.idle (write_idle ),
.phy_ready (phy_ready ),
.write_ready (write_ready ),
.send_sync_escape (sync_escape ),
.detect_x_rdy (detect_x_rdy ),
.detect_r_rdy (detect_r_rdy ),
.detect_r_ip (detect_r_ip ),
.detect_r_err (detect_r_err ),
.detect_r_ok (detect_r_ok ),
.detect_cont (detect_cont ),
.detect_hold (detect_hold ),
.detect_holda (detect_holda ),
.detect_sync (detect_sync ),
.detect_align (detect_align ),
.send_holda (dbg_send_holda ),
.write_start (write_start ),
.write_strobe (write_strobe ),
.write_data (write_data ),
.write_size (write_size ),
.write_hold (write_hold ),
.write_finished (write_finished ),
.write_abort (write_abort ),
.last_prim (last_prim ),
.send_crc (send_crc ),
.post_align_write (post_align_write ),
.tx_dout (slw_tx_dout ),
.tx_is_k (slw_tx_is_k ),
.rx_din (rx_din ),
.rx_is_k (rx_is_k ),
.xmit_error (xmit_error ),
.wsize_z_error (wsize_z_error ),
.data_scrambler_en (data_scrambler_en ),
.is_device (is_device ),
.state (lax_w_state ),
.fstate (lax_w_fstate ),
.in_data_addra (in_data_addra ),
.write_count (write_count ),
.d_count (d_count ),
.buffer_pos (buffer_pos )
);
sata_link_layer_read slr (
.rst (rst ),
.clk (clk ),
.en (read_en ),
.idle (read_idle ),
.sync_escape (sync_escape ),
.phy_ready (phy_ready ),
.dbg_hold (hold ),
.detect_align (detect_align ),
.detect_sync (detect_sync ),
.detect_x_rdy (detect_x_rdy ),
.detect_sof (detect_sof ),
.detect_eof (detect_eof ),
.detect_wtrm (detect_wtrm ),
.detect_cont (detect_cont ),
.detect_holda (detect_holda ),
.detect_hold (detect_hold ),
.detect_xrdy_xrdy (detect_xrdy_xrdy ),
.tx_dout (slr_tx_dout ),
.tx_is_k (slr_tx_is_k ),
.rx_din (rx_din ),
.rx_is_k (rx_is_k ),
.read_ready (read_ready ),
.read_strobe (read_strobe ),
.read_data (read_data ),
.read_start (read_start ),
.read_finished (read_finished ),
.remote_abort (remote_abort ),
.crc_ok (read_crc_ok ),
.data_scrambler_en (data_scrambler_en ),
.is_device (is_device ),
.lax_r_state (lax_r_state )
);
//Asynchronous logic
assign ll_tx_dout = (!read_idle) ? slr_tx_dout : (!write_idle) ? slw_tx_dout : sli_tx_dout;
assign ll_tx_is_k = (!read_idle) ? slr_tx_is_k : (!write_idle) ? slw_tx_is_k : sli_tx_is_k;
assign sli_tx_dout = (send_pmnack) ? `PRIM_PMNACK :
(send_pmack) ? `PRIM_PMACK :
`PRIM_SYNC;
assign sli_tx_is_k = 1;
assign link_layer_ready = (state == IDLE) && read_idle && write_idle;
assign lax_i_state = state;
//Main State Machine
always @ (posedge clk) begin
if (rst) begin
state <= NOT_READY;
send_pmnack <= 0;
send_pmack <= 0;
write_en <= 0;
read_en <= 0;
end
else begin
//Strobes
send_pmnack <= 0;
send_pmack <= 0;
write_en <= 0;
read_en <= 0;
if (!platform_ready) begin
state <= NOT_READY;
end
if (phy_ready) begin
case (state)
NOT_READY: begin
if (platform_ready) begin
state <= IDLE;
end
end
IDLE: begin
write_en <= 1;
read_en <= 1;
if (detect_preq_s || detect_preq_p) begin
send_pmnack <= 1;
state <= PM_DENY;
end
end
PM_DENY: begin
if (detect_preq_s || detect_preq_p) begin
send_pmnack <= 1;
end
else begin
state <= IDLE;
end
end
default: begin
state <= NOT_READY;
end
endcase
end
end
end
endmodule
|
module sata_link_layer_read (
input rst, //reset
input clk,
input phy_ready,
input en,
output idle,
input sync_escape,
input dbg_hold,
input detect_align,
input detect_sync,
input detect_x_rdy,
input detect_sof,
input detect_eof,
input detect_wtrm,
input detect_holda,
input detect_hold,
input detect_cont,
input detect_xrdy_xrdy,
output [31:0] tx_dout,
output tx_is_k,
input [31:0] rx_din,
input [3:0] rx_is_k,
output reg read_strobe,
output reg [31:0] read_data,
input read_ready,
output read_start,
output read_finished,
output reg remote_abort,
output reg crc_ok,
// output wire crc_ok,
input data_scrambler_en,
input is_device,
output [3:0] lax_r_state
);
//Primatives
parameter IDLE = 4'h0;
parameter READ_START = 4'h1;
parameter READ = 4'h2;
parameter READ_END = 4'h3;
parameter SEND_STATUS = 4'h4;
//Registers/Wires
reg [3:0] state;
reg send_r_rdy;
reg send_r_ip;
reg send_r_err;
reg send_r_ok;
reg send_hold;
reg send_holda;
reg send_sync;
//CRC
//XXX: Tie the CRC_EN to an incomming data dword
wire [31:0] crc_din;
reg [31:0] prev_crc;
reg [31:0] prev_data;
wire data_valid;
reg first_dword;
//Descrambler
wire descr_en;
wire [31:0] descr_din;
wire [31:0] descr_dout;
//SubModules
scrambler descr (
.rst (rst || idle),
.clk (clk ),
.prim_scrambler (1'b0 ),
.en (descr_en ),
.din (rx_din ),
.dout (descr_dout )
);
//Asynchronous Logic
assign idle = (state == IDLE);
assign tx_dout = (send_r_rdy) ? `PRIM_R_RDY :
(send_r_ip) ? `PRIM_R_IP :
(send_r_err) ? `PRIM_R_ERR :
(send_r_ok) ? `PRIM_R_OK :
(send_hold) ? `PRIM_HOLD :
(send_sync) ? `PRIM_SYNC :
(send_holda) ? `PRIM_HOLDA :
`PRIM_SYNC;
assign tx_is_k = ( send_r_rdy ||
send_r_ip ||
send_r_err ||
send_r_ok ||
send_hold ||
send_holda ||
send_sync);
assign crc_din = (data_scrambler_en) ? descr_dout : rx_din;
//assign read_data = (read_strobe) ? rx_din : 32'h0;
assign read_finished = detect_eof;
assign read_start = detect_sof;
assign data_valid = (state == READ) &&
(rx_is_k == 0) &&
(!detect_hold) &&
(!detect_holda) &&
(!detect_align);
assign descr_en = (data_scrambler_en && (detect_sof || data_valid));
assign descr_din = (data_valid) ? rx_din : 32'h00000000;
//assign crc_ok = (prev_data == prev_crc);
assign lax_r_state = state;
//Synchronous Logic
always @ (posedge clk) begin
if (rst) begin
state <= IDLE;
send_r_rdy <= 0;
send_r_ip <= 0;
send_r_err <= 0;
send_r_ok <= 0;
send_hold <= 0;
send_holda <= 0;
send_sync <= 0;
crc_ok <= 0;
prev_crc <= 0;
prev_data <= 0;
read_data <= 0;
read_strobe <= 0;
first_dword <= 0;
remote_abort <= 0;
end
else begin
read_strobe <= 0;
remote_abort <= 0;
if (phy_ready) begin
send_r_rdy <= 0;
send_r_ip <= 0;
send_r_err <= 0;
send_r_ok <= 0;
send_hold <= 0;
send_sync <= 0;
send_holda <= 0;
end
case (state)
IDLE: begin
read_data <= 0;
send_sync <= 1;
if (!detect_align) begin
crc_ok <= 0;
prev_crc <= 0;
prev_data <= 0;
if (detect_x_rdy) begin
if (detect_xrdy_xrdy) begin
if (!is_device) begin
if (read_ready || sync_escape) begin
//Transport is ready
if (phy_ready) begin
send_r_rdy <= 1;
state <= READ_START;
end
end
end
end
else begin
if (read_ready || sync_escape) begin
//Transport is ready
//XXX: I think this is okay because remote will continue to send X_RDY Primative
if (phy_ready) begin
send_r_rdy <= 1;
state <= READ_START;
end
end
end
// else begin
// //Transport Read is not ready
// send_sync <= 1;
// end
end
end
end
READ_START: begin
//wait for a start of frame
send_r_rdy <= 1;
if (detect_sync) begin
remote_abort <= 1;
state <= IDLE;
end
else if (detect_sof) begin
state <= READ;
send_r_ip <= 1;
first_dword <= 1;
end
end
READ: begin
if (sync_escape) begin
send_sync <= 1;
if (detect_sync) begin
state <= IDLE;
end
end
else begin
if (detect_eof) begin
//check the CRC
state <= READ_END;
send_r_ip <= 1;
//if (prev_data == prev_crc) begin
if (prev_data == prev_crc) begin
crc_ok <= 1;
end
end
else begin
if (detect_sync) begin
remote_abort <= 1;
state <= IDLE;
end
else if (!read_ready || dbg_hold) begin
//we should still have 20 DWORD of data to write
send_hold <= 1;
end
else if (detect_hold) begin
send_holda <= 1;
end
else begin
send_r_ip <= 1;
end
end
if (data_valid) begin
if (first_dword) begin
first_dword <= 0;
end
else begin
read_strobe <= 1;
end
read_data <= prev_data;
if (data_scrambler_en) begin
prev_data <= descr_dout;
end
else begin
prev_data <= rx_din;
end
prev_crc <= crc_din;
end
end
//put data into the incomming buffer
//check to see if we have enough room for 20 more dwords
//if not send a hold
end
READ_END: begin
//send r ok or r err
//XXX: Watch out for PHY_READY
//if CRC checks out OK then send an R_OK
//if CRC does not check out then send an R_ERR
//if (phy_ready) begin
if (crc_ok) begin
send_r_ok <= 1;
state <= SEND_STATUS;
end
else begin
send_r_err <= 1;
state <= SEND_STATUS;
end
//end
end
SEND_STATUS: begin
if (send_r_ok) begin
send_r_ok <= 1;
end
else begin
send_r_err <= 1;
end
if (detect_sync) begin
state <= IDLE;
end
end
default: begin
state <= IDLE;
end
endcase
end
end
endmodule
|
module cont_controller (
input rst, //reset
input clk,
input phy_ready,
input xmit_cont_en, //enable the transmit cont primative (slows simulations WAY!!! down)
input last_prim,
input [31:0] ll_tx_din,
input ll_tx_is_k,
output [31:0] cont_tx_dout,
output cont_tx_is_k,
input [31:0] rx_din,
input [3:0] rx_is_k,
output detect_sync,
output detect_r_rdy,
output detect_r_ip,
output detect_r_err,
output detect_r_ok,
output detect_x_rdy,
output detect_sof,
output detect_eof,
output detect_wtrm,
output detect_cont,
output detect_hold,
output detect_holda,
output detect_preq_s,
output detect_preq_p,
output detect_align,
output detect_xrdy_xrdy
);
//Parameters
//Registers/Wires
//CONT detect State Machine
wire hold_cont;
wire holda_cont;
wire pmreq_p_cont;
wire pmreq_s_cont;
wire r_err_cont;
wire r_ip_cont;
wire r_ok_cont;
wire r_rdy_cont;
wire sync_cont;
wire wtrm_cont;
wire x_rdy_cont;
reg cont_detect;
reg [31:0] prev_prim;
reg hold_cont_ready;
reg holda_cont_ready;
reg pmreq_p_cont_ready;
reg pmreq_s_cont_ready;
reg r_err_cont_ready;
reg r_ip_cont_ready;
reg r_ok_cont_ready;
reg r_rdy_cont_ready;
reg sync_cont_ready;
reg wtrm_cont_ready;
reg x_rdy_cont_ready;
//CONT generate state machine
reg [31:0] tx_prev_prim;
reg tx_cont_enable;
reg tx_cont_sent;
reg send_cont;
//Scrambler control
wire scram_en;
wire [31:0] scram_dout;
//Submodules
scrambler scram (
.rst (rst ),
.clk (clk ),
.prim_scrambler (1'b1 ),
.en (scram_en ),
.din (ll_tx_din ),
.dout (scram_dout )
);
//Asynchronous Logic
assign detect_sync = ((rx_is_k[0]) && (rx_din == `PRIM_SYNC )) || sync_cont; //sync (normal) == sync(cont)
assign detect_r_rdy = ((rx_is_k[0]) && (rx_din == `PRIM_R_RDY )) || r_rdy_cont;
assign detect_r_ip = ((rx_is_k[0]) && (rx_din == `PRIM_R_IP )) || r_ip_cont;
assign detect_r_err = ((rx_is_k[0]) && (rx_din == `PRIM_R_ERR )) || r_err_cont;
assign detect_r_ok = ((rx_is_k[0]) && (rx_din == `PRIM_R_OK )) || r_ok_cont;
assign detect_x_rdy = ((rx_is_k[0]) && (rx_din == `PRIM_X_RDY )) || x_rdy_cont;
assign detect_sof = (rx_is_k[0]) && (rx_din == `PRIM_SOF );
assign detect_eof = (rx_is_k[0]) && (rx_din == `PRIM_EOF );
assign detect_wtrm = ((rx_is_k[0]) && (rx_din == `PRIM_WTRM )) || wtrm_cont;
assign detect_cont = (rx_is_k[0]) && (rx_din == `PRIM_CONT );
assign detect_hold = ((rx_is_k[0]) && (rx_din == `PRIM_HOLD )) || hold_cont; //hold (normal) == hold (cont)
assign detect_holda = ((rx_is_k[0]) && (rx_din == `PRIM_HOLDA )) || holda_cont; //holda (normal) == holda (cont)
assign detect_preq_s = ((rx_is_k[0]) && (rx_din == `PRIM_PREQ_S )) || pmreq_s_cont;
assign detect_preq_p = ((rx_is_k[0]) && (rx_din == `PRIM_PREQ_P )) || pmreq_p_cont;
assign detect_align = (rx_is_k[0]) && (rx_din == `PRIM_ALIGN );
assign detect_xrdy_xrdy = ((((rx_is_k[0])&& (rx_din == `PRIM_X_RDY )) || x_rdy_cont) && ll_tx_is_k && (ll_tx_din == `PRIM_X_RDY));
assign sync_cont = sync_cont_ready && ((rx_din == `PRIM_CONT) || (!rx_is_k[0] || detect_align));
assign hold_cont = hold_cont_ready && ((rx_din == `PRIM_CONT) || (!rx_is_k[0] || detect_align));
assign holda_cont = holda_cont_ready && ((rx_din == `PRIM_CONT) || (!rx_is_k[0] || detect_align));
assign pmreq_p_cont = pmreq_p_cont_ready && ((rx_din == `PRIM_CONT) || (!rx_is_k[0] || detect_align));
assign pmreq_s_cont = pmreq_s_cont_ready && ((rx_din == `PRIM_CONT) || (!rx_is_k[0] || detect_align));
assign r_err_cont = r_err_cont_ready && ((rx_din == `PRIM_CONT) || (!rx_is_k[0] || detect_align));
assign r_ip_cont = r_ip_cont_ready && ((rx_din == `PRIM_CONT) || (!rx_is_k[0] || detect_align));
assign r_ok_cont = r_ok_cont_ready && ((rx_din == `PRIM_CONT) || (!rx_is_k[0] || detect_align));
assign r_rdy_cont = r_rdy_cont_ready && ((rx_din == `PRIM_CONT) || (!rx_is_k[0] || detect_align));
assign wtrm_cont = wtrm_cont_ready && ((rx_din == `PRIM_CONT) || (!rx_is_k[0] || detect_align));
assign x_rdy_cont = x_rdy_cont_ready && ((rx_din == `PRIM_CONT) || (!rx_is_k[0] || detect_align));
assign cont_tx_dout = (!xmit_cont_en) ? ll_tx_din : //when transmit cont gen is disable
((tx_prev_prim != ll_tx_din) && ll_tx_is_k) ? ll_tx_din : //if the prev != curr (exit)
(last_prim) ? ll_tx_din:
(tx_cont_enable) ? //if the cont is enabled
send_cont ? `PRIM_CONT : //need to first send the cont
scram_dout : //send the junk
ll_tx_din; //tx cont is not enabled
assign cont_tx_is_k = (!xmit_cont_en) ? ll_tx_is_k :
((tx_prev_prim != ll_tx_din) && ll_tx_is_k) ? ll_tx_is_k ://if the prev != curr (exit)
(last_prim) ?ll_tx_is_k:
(tx_cont_enable) ? //if the cont is enabled
send_cont ? 1'b1 : //need to first send the cont
1'b0 : //send the junk
ll_tx_is_k; //tx cont is not enabled
assign scram_en = tx_cont_enable;
//Synchronous logic
//Cont detect
always @ (posedge clk) begin
if (rst) begin
cont_detect <= 0;
hold_cont_ready <= 0;
holda_cont_ready <= 0;
pmreq_p_cont_ready <= 0;
pmreq_s_cont_ready <= 0;
r_err_cont_ready <= 0;
r_ip_cont_ready <= 0;
r_ok_cont_ready <= 0;
r_rdy_cont_ready <= 0;
sync_cont_ready <= 0;
wtrm_cont_ready <= 0;
x_rdy_cont_ready <= 0;
end
else begin
if (!detect_align) begin
if (rx_is_k) begin
if (rx_din == `PRIM_CONT) begin
cont_detect <= 1;
end
else if (prev_prim == rx_din) begin
case (prev_prim)
`PRIM_SYNC : begin
sync_cont_ready <= 1;
end
`PRIM_R_RDY : begin
r_rdy_cont_ready <= 1;
end
`PRIM_R_IP : begin
r_ip_cont_ready <= 1;
end
`PRIM_R_ERR : begin
r_err_cont_ready <= 1;
end
`PRIM_R_OK : begin
r_ok_cont_ready <= 1;
end
`PRIM_X_RDY : begin
x_rdy_cont_ready <= 1;
end
`PRIM_WTRM : begin
wtrm_cont_ready <= 1;
end
`PRIM_HOLD : begin
if (cont_detect) begin
hold_cont_ready <= 0;
cont_detect <= 0;
end
else begin
hold_cont_ready <= 1;
end
end
`PRIM_HOLDA : begin
if (cont_detect) begin
holda_cont_ready <= 0;
cont_detect <= 0;
end
else begin
holda_cont_ready <= 1;
end
end
`PRIM_PREQ_S : begin
pmreq_s_cont_ready <= 1;
end
`PRIM_PREQ_P : begin
pmreq_p_cont_ready <= 1;
end
`PRIM_ALIGN : begin
end
default: begin
hold_cont_ready <= 0;
holda_cont_ready <= 0;
pmreq_p_cont_ready <= 0;
pmreq_s_cont_ready <= 0;
r_err_cont_ready <= 0;
r_ip_cont_ready <= 0;
r_ok_cont_ready <= 0;
r_rdy_cont_ready <= 0;
sync_cont_ready <= 0;
wtrm_cont_ready <= 0;
x_rdy_cont_ready <= 0;
end
endcase
end
//save the previous primative
else begin
prev_prim <= rx_din;
//previous primative doesn't equal current primitive
cont_detect <= 0;
hold_cont_ready <= 0;
holda_cont_ready <= 0;
pmreq_p_cont_ready <= 0;
pmreq_s_cont_ready <= 0;
r_err_cont_ready <= 0;
r_ip_cont_ready <= 0;
r_ok_cont_ready <= 0;
r_rdy_cont_ready <= 0;
sync_cont_ready <= 0;
wtrm_cont_ready <= 0;
x_rdy_cont_ready <= 0;
end
end
if (!rx_is_k[0] && !cont_detect) begin
cont_detect <= 0;
hold_cont_ready <= 0;
holda_cont_ready <= 0;
pmreq_p_cont_ready <= 0;
pmreq_s_cont_ready <= 0;
r_err_cont_ready <= 0;
r_ip_cont_ready <= 0;
r_ok_cont_ready <= 0;
r_rdy_cont_ready <= 0;
sync_cont_ready <= 0;
wtrm_cont_ready <= 0;
x_rdy_cont_ready <= 0;
end
end
end
end
//Cont Generator
always @ (posedge clk) begin
if (rst || !xmit_cont_en) begin
tx_prev_prim <= 0;
tx_cont_enable <= 0;
tx_cont_sent <= 0;
send_cont <= 0;
end
else begin
if (phy_ready) begin
send_cont <= 0;
if (ll_tx_is_k) begin
//reset everything because the previous primative is not equal to the current one
if (tx_prev_prim != ll_tx_din) begin
send_cont <= 0;
tx_cont_sent <= 0;
tx_cont_enable <= 0;
end
else begin
//see if we need to send the cont primative
if (tx_cont_enable && send_cont) begin
tx_cont_sent <= 1;
end
//previous primative == current primative
case (tx_prev_prim)
`PRIM_SYNC : begin
tx_cont_enable <= 1;
if (!tx_cont_sent && !send_cont) begin
send_cont <= 1;
end
end
`PRIM_R_RDY : begin
tx_cont_enable <= 1;
if (!tx_cont_sent && !send_cont) begin
send_cont <= 1;
end
end
`PRIM_R_IP : begin
tx_cont_enable <= 1;
if (!tx_cont_sent && !send_cont) begin
send_cont <= 1;
end
end
`PRIM_R_ERR : begin
tx_cont_enable <= 1;
if (!tx_cont_sent && !send_cont) begin
send_cont <= 1;
end
end
`PRIM_R_OK : begin
tx_cont_enable <= 1;
if (!tx_cont_sent && !send_cont) begin
send_cont <= 1;
end
end
`PRIM_X_RDY : begin
tx_cont_enable <= 1;
if (!tx_cont_sent && !send_cont) begin
send_cont <= 1;
end
end
`PRIM_WTRM : begin
tx_cont_enable <= 1;
if (!tx_cont_sent && !send_cont) begin
send_cont <= 1;
end
end
`PRIM_HOLD : begin
tx_cont_enable <= 1;
if (!tx_cont_sent && !send_cont) begin
send_cont <= 1;
end
end
`PRIM_HOLDA : begin
tx_cont_enable <= 1;
if (!tx_cont_sent && !send_cont) begin
send_cont <= 1;
end
end
`PRIM_PREQ_S : begin
tx_cont_enable <= 1;
if (!tx_cont_sent && !send_cont) begin
send_cont <= 1;
end
end
`PRIM_PREQ_P : begin
tx_cont_enable <= 1;
if (!tx_cont_sent && !send_cont) begin
send_cont <= 1;
end
end
default: begin
send_cont <= 0;
tx_cont_enable <= 0;
tx_cont_sent <= 0;
end
endcase
end
end
else begin
//it is not a k value so don't read it
tx_prev_prim <= 0;
end
//k value record the PRIM
tx_prev_prim <= ll_tx_din;
if (last_prim) begin
tx_cont_enable <= 0;
end
end
end
end
endmodule
|
module crc (
clk,
rst,
en,
din,
dout
);
input clk;
input rst;
input en;
input [31:0] din;
output reg [31:0] dout;
parameter CRC_INIT = 32'h52325032;
//Registers/Wires
wire [31:0] crc_next;
wire [31:0] crc_new;
always @ (posedge clk) begin
if (rst) begin
dout <= CRC_INIT;
end
else if (en) begin
dout <= crc_next;
end
end
assign crc_new = dout ^ din;
assign crc_next[31] =crc_new[31] ^
crc_new[30] ^
crc_new[29] ^
crc_new[28] ^
crc_new[27] ^
crc_new[25] ^
crc_new[24] ^
crc_new[23] ^
crc_new[15] ^
crc_new[11] ^
crc_new[9] ^
crc_new[8] ^
crc_new[5];
assign crc_next[30] =crc_new[30] ^
crc_new[29] ^
crc_new[28] ^
crc_new[27] ^
crc_new[26] ^
crc_new[24] ^
crc_new[23] ^
crc_new[22] ^
crc_new[14] ^
crc_new[10] ^
crc_new[8] ^
crc_new[7] ^
crc_new[4];
assign crc_next[29] =crc_new[31] ^
crc_new[29] ^
crc_new[28] ^
crc_new[27] ^
crc_new[26] ^
crc_new[25] ^
crc_new[23] ^
crc_new[22] ^
crc_new[21] ^
crc_new[13] ^
crc_new[9] ^
crc_new[7] ^
crc_new[6] ^
crc_new[3];
assign crc_next[28] =crc_new[30] ^
crc_new[28] ^
crc_new[27] ^
crc_new[26] ^
crc_new[25] ^
crc_new[24] ^
crc_new[22] ^
crc_new[21] ^
crc_new[20] ^
crc_new[12] ^
crc_new[8] ^
crc_new[6] ^
crc_new[5] ^
crc_new[2];
assign crc_next[27] =crc_new[29] ^
crc_new[27] ^
crc_new[26] ^
crc_new[25] ^
crc_new[24] ^
crc_new[23] ^
crc_new[21] ^
crc_new[20] ^
crc_new[19] ^
crc_new[11] ^
crc_new[7] ^
crc_new[5] ^
crc_new[4] ^
crc_new[1];
assign crc_next[26] =crc_new[31] ^
crc_new[28] ^
crc_new[26] ^
crc_new[25] ^
crc_new[24] ^
crc_new[23] ^
crc_new[22] ^
crc_new[20] ^
crc_new[19] ^
crc_new[18] ^
crc_new[10] ^
crc_new[6] ^
crc_new[4] ^
crc_new[3] ^
crc_new[0];
assign crc_next[25] =crc_new[31] ^
crc_new[29] ^
crc_new[28] ^
crc_new[22] ^
crc_new[21] ^
crc_new[19] ^
crc_new[18] ^
crc_new[17] ^
crc_new[15] ^
crc_new[11] ^
crc_new[8] ^
crc_new[3] ^
crc_new[2];
assign crc_next[24] =crc_new[30] ^
crc_new[28] ^
crc_new[27] ^
crc_new[21] ^
crc_new[20] ^
crc_new[18] ^
crc_new[17] ^
crc_new[16] ^
crc_new[14] ^
crc_new[10] ^
crc_new[7] ^
crc_new[2] ^
crc_new[1];
assign crc_next[23] =crc_new[31] ^
crc_new[29] ^
crc_new[27] ^
crc_new[26] ^
crc_new[20] ^
crc_new[19] ^
crc_new[17] ^
crc_new[16] ^
crc_new[15] ^
crc_new[13] ^
crc_new[9] ^
crc_new[6] ^
crc_new[1] ^
crc_new[0];
assign crc_next[22] =crc_new[31] ^
crc_new[29] ^
crc_new[27] ^
crc_new[26] ^
crc_new[24] ^
crc_new[23] ^
crc_new[19] ^
crc_new[18] ^
crc_new[16] ^
crc_new[14] ^
crc_new[12] ^
crc_new[11] ^
crc_new[9] ^
crc_new[0];
assign crc_next[21] =crc_new[31] ^
crc_new[29] ^
crc_new[27] ^
crc_new[26] ^
crc_new[24] ^
crc_new[22] ^
crc_new[18] ^
crc_new[17] ^
crc_new[13] ^
crc_new[10] ^
crc_new[9] ^
crc_new[5];
assign crc_next[20] =crc_new[30] ^
crc_new[28] ^
crc_new[26] ^
crc_new[25] ^
crc_new[23] ^
crc_new[21] ^
crc_new[17] ^
crc_new[16] ^
crc_new[12] ^
crc_new[9] ^
crc_new[8] ^
crc_new[4];
assign crc_next[19] =crc_new[29] ^
crc_new[27] ^
crc_new[25] ^
crc_new[24] ^
crc_new[22] ^
crc_new[20] ^
crc_new[16] ^
crc_new[15] ^
crc_new[11] ^
crc_new[8] ^
crc_new[7] ^
crc_new[3];
assign crc_next[18] =crc_new[31] ^
crc_new[28] ^
crc_new[26] ^
crc_new[24] ^
crc_new[23] ^
crc_new[21] ^
crc_new[19] ^
crc_new[15] ^
crc_new[14] ^
crc_new[10] ^
crc_new[7] ^
crc_new[6] ^
crc_new[2];
assign crc_next[17] =crc_new[31] ^
crc_new[30] ^
crc_new[27] ^
crc_new[25] ^
crc_new[23] ^
crc_new[22] ^
crc_new[20] ^
crc_new[18] ^
crc_new[14] ^
crc_new[13] ^
crc_new[9] ^
crc_new[6] ^
crc_new[5] ^
crc_new[1];
assign crc_next[16] =crc_new[30] ^
crc_new[29] ^
crc_new[26] ^
crc_new[24] ^
crc_new[22] ^
crc_new[21] ^
crc_new[19] ^
crc_new[17] ^
crc_new[13] ^
crc_new[12] ^
crc_new[8] ^
crc_new[5] ^
crc_new[4] ^
crc_new[0];
assign crc_next[15] =crc_new[30] ^
crc_new[27] ^
crc_new[24] ^
crc_new[21] ^
crc_new[20] ^
crc_new[18] ^
crc_new[16] ^
crc_new[15] ^
crc_new[12] ^
crc_new[9] ^
crc_new[8] ^
crc_new[7] ^
crc_new[5] ^
crc_new[4] ^
crc_new[3];
assign crc_next[14] =crc_new[29] ^
crc_new[26] ^
crc_new[23] ^
crc_new[20] ^
crc_new[19] ^
crc_new[17] ^
crc_new[15] ^
crc_new[14] ^
crc_new[11] ^
crc_new[8] ^
crc_new[7] ^
crc_new[6] ^
crc_new[4] ^
crc_new[3] ^
crc_new[2];
assign crc_next[13] =crc_new[31] ^
crc_new[28] ^
crc_new[25] ^
crc_new[22] ^
crc_new[19] ^
crc_new[18] ^
crc_new[16] ^
crc_new[14] ^
crc_new[13] ^
crc_new[10] ^
crc_new[7] ^
crc_new[6] ^
crc_new[5] ^
crc_new[3] ^
crc_new[2] ^
crc_new[1];
assign crc_next[12] =crc_new[31] ^
crc_new[30] ^
crc_new[27] ^
crc_new[24] ^
crc_new[21] ^
crc_new[18] ^
crc_new[17] ^
crc_new[15] ^
crc_new[13] ^
crc_new[12] ^
crc_new[9] ^
crc_new[6] ^
crc_new[5] ^
crc_new[4] ^
crc_new[2] ^
crc_new[1] ^
crc_new[0];
assign crc_next[11] =crc_new[31] ^
crc_new[28] ^
crc_new[27] ^
crc_new[26] ^
crc_new[25] ^
crc_new[24] ^
crc_new[20] ^
crc_new[17] ^
crc_new[16] ^
crc_new[15] ^
crc_new[14] ^
crc_new[12] ^
crc_new[9] ^
crc_new[4] ^
crc_new[3] ^
crc_new[1] ^
crc_new[0];
assign crc_next[10] =crc_new[31] ^
crc_new[29] ^
crc_new[28] ^
crc_new[26] ^
crc_new[19] ^
crc_new[16] ^
crc_new[14] ^
crc_new[13] ^
crc_new[9] ^
crc_new[5] ^
crc_new[3] ^
crc_new[2] ^
crc_new[0];
assign crc_next[9] = crc_new[29] ^
crc_new[24] ^
crc_new[23] ^
crc_new[18] ^
crc_new[13] ^
crc_new[12] ^
crc_new[11] ^
crc_new[9] ^
crc_new[5] ^
crc_new[4] ^
crc_new[2] ^
crc_new[1];
assign crc_next[8] = crc_new[31] ^
crc_new[28] ^
crc_new[23] ^
crc_new[22] ^
crc_new[17] ^
crc_new[12] ^
crc_new[11] ^
crc_new[10] ^
crc_new[8] ^
crc_new[4] ^
crc_new[3] ^
crc_new[1] ^
crc_new[0];
assign crc_next[7] = crc_new[29] ^
crc_new[28] ^
crc_new[25] ^
crc_new[24] ^
crc_new[23] ^
crc_new[22] ^
crc_new[21] ^
crc_new[16] ^
crc_new[15] ^
crc_new[10] ^
crc_new[8] ^
crc_new[7] ^
crc_new[5] ^
crc_new[3] ^
crc_new[2] ^
crc_new[0];
assign crc_next[6] = crc_new[30] ^
crc_new[29] ^
crc_new[25] ^
crc_new[22] ^
crc_new[21] ^
crc_new[20] ^
crc_new[14] ^
crc_new[11] ^
crc_new[8] ^
crc_new[7] ^
crc_new[6] ^
crc_new[5] ^
crc_new[4] ^
crc_new[2] ^
crc_new[1];
assign crc_next[5] = crc_new[29] ^
crc_new[28] ^
crc_new[24] ^
crc_new[21] ^
crc_new[20] ^
crc_new[19] ^
crc_new[13] ^
crc_new[10] ^
crc_new[7] ^
crc_new[6] ^
crc_new[5] ^
crc_new[4] ^
crc_new[3] ^
crc_new[1] ^
crc_new[0];
assign crc_next[4] = crc_new[31] ^
crc_new[30] ^
crc_new[29] ^
crc_new[25] ^
crc_new[24] ^
crc_new[20] ^
crc_new[19] ^
crc_new[18] ^
crc_new[15] ^
crc_new[12] ^
crc_new[11] ^
crc_new[8] ^
crc_new[6] ^
crc_new[4] ^
crc_new[3] ^
crc_new[2] ^
crc_new[0];
assign crc_next[3] = crc_new[31] ^
crc_new[27] ^
crc_new[25] ^
crc_new[19] ^
crc_new[18] ^
crc_new[17] ^
crc_new[15] ^
crc_new[14] ^
crc_new[10] ^
crc_new[9] ^
crc_new[8] ^
crc_new[7] ^
crc_new[3] ^
crc_new[2] ^
crc_new[1];
assign crc_next[2] = crc_new[31] ^
crc_new[30] ^
crc_new[26] ^
crc_new[24] ^
crc_new[18] ^
crc_new[17] ^
crc_new[16] ^
crc_new[14] ^
crc_new[13] ^
crc_new[9] ^
crc_new[8] ^
crc_new[7] ^
crc_new[6] ^
crc_new[2] ^
crc_new[1] ^
crc_new[0];
assign crc_next[1] = crc_new[28] ^
crc_new[27] ^
crc_new[24] ^
crc_new[17] ^
crc_new[16] ^
crc_new[13] ^
crc_new[12] ^
crc_new[11] ^
crc_new[9] ^
crc_new[7] ^
crc_new[6] ^
crc_new[1] ^
crc_new[0];
assign crc_next[0] = crc_new[31] ^
crc_new[30] ^
crc_new[29] ^
crc_new[28] ^
crc_new[26] ^
crc_new[25] ^
crc_new[24] ^
crc_new[16] ^
crc_new[12] ^
crc_new[10] ^
crc_new[9] ^
crc_new[6] ^
crc_new[0];
endmodule
|
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