module
stringlengths 21
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module sirv_queue(
input clock,
input reset,
output io_enq_ready,
input io_enq_valid,
input io_enq_bits_read,
input [9:0] io_enq_bits_index,
input [31:0] io_enq_bits_data,
input [3:0] io_enq_bits_mask,
input [9:0] io_enq_bits_extra,
input io_deq_ready,
output io_deq_valid,
output io_deq_bits_read,
output [9:0] io_deq_bits_index,
output [31:0] io_deq_bits_data,
output [3:0] io_deq_bits_mask,
output [9:0] io_deq_bits_extra,
output io_count
);
reg ram_read [0:0];
reg [31:0] GEN_0;
wire ram_read_T_83_data;
wire ram_read_T_83_addr;
wire ram_read_T_69_data;
wire ram_read_T_69_addr;
wire ram_read_T_69_mask;
wire ram_read_T_69_en;
reg [9:0] ram_index [0:0];
reg [31:0] GEN_1;
wire [9:0] ram_index_T_83_data;
wire ram_index_T_83_addr;
wire [9:0] ram_index_T_69_data;
wire ram_index_T_69_addr;
wire ram_index_T_69_mask;
wire ram_index_T_69_en;
reg [31:0] ram_data [0:0];
reg [31:0] GEN_2;
wire [31:0] ram_data_T_83_data;
wire ram_data_T_83_addr;
wire [31:0] ram_data_T_69_data;
wire ram_data_T_69_addr;
wire ram_data_T_69_mask;
wire ram_data_T_69_en;
reg [3:0] ram_mask [0:0];
reg [31:0] GEN_3;
wire [3:0] ram_mask_T_83_data;
wire ram_mask_T_83_addr;
wire [3:0] ram_mask_T_69_data;
wire ram_mask_T_69_addr;
wire ram_mask_T_69_mask;
wire ram_mask_T_69_en;
reg [9:0] ram_extra [0:0];
reg [31:0] GEN_4;
wire [9:0] ram_extra_T_83_data;
wire ram_extra_T_83_addr;
wire [9:0] ram_extra_T_69_data;
wire ram_extra_T_69_addr;
wire ram_extra_T_69_mask;
wire ram_extra_T_69_en;
reg maybe_full;
reg [31:0] GEN_5;
wire T_65;
wire T_66;
wire do_enq;
wire T_67;
wire do_deq;
wire T_77;
wire GEN_8;
wire T_79;
wire GEN_9;
wire [1:0] T_90;
wire ptr_diff;
wire [1:0] T_92;
assign io_enq_ready = GEN_9;
assign io_deq_valid = T_79;
assign io_deq_bits_read = ram_read_T_83_data;
assign io_deq_bits_index = ram_index_T_83_data;
assign io_deq_bits_data = ram_data_T_83_data;
assign io_deq_bits_mask = ram_mask_T_83_data;
assign io_deq_bits_extra = ram_extra_T_83_data;
assign io_count = T_92[0];
assign ram_read_T_83_addr = 1'h0;
assign ram_read_T_83_data = ram_read[ram_read_T_83_addr];
assign ram_read_T_69_data = io_enq_bits_read;
assign ram_read_T_69_addr = 1'h0;
assign ram_read_T_69_mask = do_enq;
assign ram_read_T_69_en = do_enq;
assign ram_index_T_83_addr = 1'h0;
assign ram_index_T_83_data = ram_index[ram_index_T_83_addr];
assign ram_index_T_69_data = io_enq_bits_index;
assign ram_index_T_69_addr = 1'h0;
assign ram_index_T_69_mask = do_enq;
assign ram_index_T_69_en = do_enq;
assign ram_data_T_83_addr = 1'h0;
assign ram_data_T_83_data = ram_data[ram_data_T_83_addr];
assign ram_data_T_69_data = io_enq_bits_data;
assign ram_data_T_69_addr = 1'h0;
assign ram_data_T_69_mask = do_enq;
assign ram_data_T_69_en = do_enq;
assign ram_mask_T_83_addr = 1'h0;
assign ram_mask_T_83_data = ram_mask[ram_mask_T_83_addr];
assign ram_mask_T_69_data = io_enq_bits_mask;
assign ram_mask_T_69_addr = 1'h0;
assign ram_mask_T_69_mask = do_enq;
assign ram_mask_T_69_en = do_enq;
assign ram_extra_T_83_addr = 1'h0;
assign ram_extra_T_83_data = ram_extra[ram_extra_T_83_addr];
assign ram_extra_T_69_data = io_enq_bits_extra;
assign ram_extra_T_69_addr = 1'h0;
assign ram_extra_T_69_mask = do_enq;
assign ram_extra_T_69_en = do_enq;
assign T_65 = maybe_full == 1'h0;
assign T_66 = io_enq_ready & io_enq_valid;
assign do_enq = T_66;
assign T_67 = io_deq_ready & io_deq_valid;
assign do_deq = T_67;
assign T_77 = do_enq != do_deq;
assign GEN_8 = T_77 ? do_enq : maybe_full;
assign T_79 = T_65 == 1'h0;
assign GEN_9 = io_deq_ready ? 1'h1 : T_65;
assign T_90 = 1'h0 - 1'h0;
assign ptr_diff = T_90[0:0];
assign T_92 = {maybe_full,ptr_diff};
always @(posedge clock) begin// The ram block does not need reset
if(ram_read_T_69_en & ram_read_T_69_mask) begin
ram_read[ram_read_T_69_addr] <= ram_read_T_69_data;
end
if(ram_index_T_69_en & ram_index_T_69_mask) begin
ram_index[ram_index_T_69_addr] <= ram_index_T_69_data;
end
if(ram_data_T_69_en & ram_data_T_69_mask) begin
ram_data[ram_data_T_69_addr] <= ram_data_T_69_data;
end
if(ram_mask_T_69_en & ram_mask_T_69_mask) begin
ram_mask[ram_mask_T_69_addr] <= ram_mask_T_69_data;
end
if(ram_extra_T_69_en & ram_extra_T_69_mask) begin
ram_extra[ram_extra_T_69_addr] <= ram_extra_T_69_data;
end
end
always @(posedge clock or posedge reset) begin
if (reset) begin
maybe_full <= 1'h0;
end else begin
if (T_77) begin
maybe_full <= do_enq;
end
end
end
endmodule
|
module sirv_debug_rom(
input [7-1:2] rom_addr,
output [32-1:0] rom_dout
);
// These ROM contents support only RV32
// See $RISCV/riscv-tools/riscv-isa-sim/debug_rom/debug_rom.h/S
// The code assumes only 28 bytes of Debug RAM.
// def xlen32OnlyRomContents : Array[Byte] = Array(
// 0x6f, 0x00, 0xc0, 0x03, 0x6f, 0x00, 0xc0, 0x00, 0x13, 0x04, 0xf0, 0xff,
// 0x6f, 0x00, 0x80, 0x00, 0x13, 0x04, 0x00, 0x00, 0x0f, 0x00, 0xf0, 0x0f,
// 0x83, 0x24, 0x80, 0x41, 0x23, 0x2c, 0x80, 0x40, 0x73, 0x24, 0x40, 0xf1,
// 0x23, 0x20, 0x80, 0x10, 0x73, 0x24, 0x00, 0x7b, 0x13, 0x74, 0x84, 0x00,
// 0x63, 0x1a, 0x04, 0x02, 0x73, 0x24, 0x20, 0x7b, 0x73, 0x00, 0x20, 0x7b,
// 0x73, 0x10, 0x24, 0x7b, 0x73, 0x24, 0x00, 0x7b, 0x13, 0x74, 0x04, 0x1c,
// 0x13, 0x04, 0x04, 0xf4, 0x63, 0x16, 0x04, 0x00, 0x23, 0x2c, 0x90, 0x40,
// 0x67, 0x00, 0x00, 0x40, 0x73, 0x24, 0x40, 0xf1, 0x23, 0x26, 0x80, 0x10,
// 0x73, 0x60, 0x04, 0x7b, 0x73, 0x24, 0x00, 0x7b, 0x13, 0x74, 0x04, 0x02,
// 0xe3, 0x0c, 0x04, 0xfe, 0x6f, 0xf0, 0x1f, 0xfe).map(_.toByte)
wire [31:0] debug_rom [0:28]; // 29 words in total
assign rom_dout = debug_rom[rom_addr];
// 0x6f, 0x00, 0xc0, 0x03, 0x6f, 0x00, 0xc0, 0x00, 0x13, 0x04, 0xf0, 0xff,
assign debug_rom[ 0][7 : 0] = 8'h6f;
assign debug_rom[ 0][15: 8] = 8'h00;
assign debug_rom[ 0][23:16] = 8'hc0;
assign debug_rom[ 0][31:24] = 8'h03;
assign debug_rom[ 1][7 : 0] = 8'h6f;
assign debug_rom[ 1][15: 8] = 8'h00;
assign debug_rom[ 1][23:16] = 8'hc0;
assign debug_rom[ 1][31:24] = 8'h00;
assign debug_rom[ 2][7 : 0] = 8'h13;
assign debug_rom[ 2][15: 8] = 8'h04;
assign debug_rom[ 2][23:16] = 8'hf0;
assign debug_rom[ 2][31:24] = 8'hff;
// 0x6f, 0x00, 0x80, 0x00, 0x13, 0x04, 0x00, 0x00, 0x0f, 0x00, 0xf0, 0x0f,
assign debug_rom[ 3][7 : 0] = 8'h6f;
assign debug_rom[ 3][15: 8] = 8'h00;
assign debug_rom[ 3][23:16] = 8'h80;
assign debug_rom[ 3][31:24] = 8'h00;
assign debug_rom[ 4][7 : 0] = 8'h13;
assign debug_rom[ 4][15: 8] = 8'h04;
assign debug_rom[ 4][23:16] = 8'h00;
assign debug_rom[ 4][31:24] = 8'h00;
assign debug_rom[ 5][7 : 0] = 8'h0f;
assign debug_rom[ 5][15: 8] = 8'h00;
assign debug_rom[ 5][23:16] = 8'hf0;
assign debug_rom[ 5][31:24] = 8'h0f;
// 0x83, 0x24, 0x80, 0x41, 0x23, 0x2c, 0x80, 0x40, 0x73, 0x24, 0x40, 0xf1,
assign debug_rom[ 6][7 : 0] = 8'h83;
assign debug_rom[ 6][15: 8] = 8'h24;
assign debug_rom[ 6][23:16] = 8'h80;
assign debug_rom[ 6][31:24] = 8'h41;
assign debug_rom[ 7][7 : 0] = 8'h23;
assign debug_rom[ 7][15: 8] = 8'h2c;
assign debug_rom[ 7][23:16] = 8'h80;
assign debug_rom[ 7][31:24] = 8'h40;
assign debug_rom[ 8][7 : 0] = 8'h73;
assign debug_rom[ 8][15: 8] = 8'h24;
assign debug_rom[ 8][23:16] = 8'h40;
assign debug_rom[ 8][31:24] = 8'hf1;
// 0x23, 0x20, 0x80, 0x10, 0x73, 0x24, 0x00, 0x7b, 0x13, 0x74, 0x84, 0x00,
assign debug_rom[ 9][7 : 0] = 8'h23;
assign debug_rom[ 9][15: 8] = 8'h20;
assign debug_rom[ 9][23:16] = 8'h80;
assign debug_rom[ 9][31:24] = 8'h10;
assign debug_rom[10][7 : 0] = 8'h73;
assign debug_rom[10][15: 8] = 8'h24;
assign debug_rom[10][23:16] = 8'h00;
assign debug_rom[10][31:24] = 8'h7b;
assign debug_rom[11][7 : 0] = 8'h13;
assign debug_rom[11][15: 8] = 8'h74;
assign debug_rom[11][23:16] = 8'h84;
assign debug_rom[11][31:24] = 8'h00;
// 0x63, 0x1a, 0x04, 0x02, 0x73, 0x24, 0x20, 0x7b, 0x73, 0x00, 0x20, 0x7b,
assign debug_rom[12][7 : 0] = 8'h63;
assign debug_rom[12][15: 8] = 8'h1a;
assign debug_rom[12][23:16] = 8'h04;
assign debug_rom[12][31:24] = 8'h02;
assign debug_rom[13][7 : 0] = 8'h73;
assign debug_rom[13][15: 8] = 8'h24;
assign debug_rom[13][23:16] = 8'h20;
assign debug_rom[13][31:24] = 8'h7b;
assign debug_rom[14][7 : 0] = 8'h73;
assign debug_rom[14][15: 8] = 8'h00;
assign debug_rom[14][23:16] = 8'h20;
assign debug_rom[14][31:24] = 8'h7b;
// 0x73, 0x10, 0x24, 0x7b, 0x73, 0x24, 0x00, 0x7b, 0x13, 0x74, 0x04, 0x1c,
assign debug_rom[15][7 : 0] = 8'h73;
assign debug_rom[15][15: 8] = 8'h10;
assign debug_rom[15][23:16] = 8'h24;
assign debug_rom[15][31:24] = 8'h7b;
assign debug_rom[16][7 : 0] = 8'h73;
assign debug_rom[16][15: 8] = 8'h24;
assign debug_rom[16][23:16] = 8'h00;
assign debug_rom[16][31:24] = 8'h7b;
assign debug_rom[17][7 : 0] = 8'h13;
assign debug_rom[17][15: 8] = 8'h74;
assign debug_rom[17][23:16] = 8'h04;
assign debug_rom[17][31:24] = 8'h1c;
// 0x13, 0x04, 0x04, 0xf4, 0x63, 0x16, 0x04, 0x00, 0x23, 0x2c, 0x90, 0x40,
assign debug_rom[18][7 : 0] = 8'h13;
assign debug_rom[18][15: 8] = 8'h04;
assign debug_rom[18][23:16] = 8'h04;
assign debug_rom[18][31:24] = 8'hf4;
assign debug_rom[19][7 : 0] = 8'h63;
assign debug_rom[19][15: 8] = 8'h16;
assign debug_rom[19][23:16] = 8'h04;
assign debug_rom[19][31:24] = 8'h00;
assign debug_rom[20][7 : 0] = 8'h23;
assign debug_rom[20][15: 8] = 8'h2c;
assign debug_rom[20][23:16] = 8'h90;
assign debug_rom[20][31:24] = 8'h40;
// 0x67, 0x00, 0x00, 0x40, 0x73, 0x24, 0x40, 0xf1, 0x23, 0x26, 0x80, 0x10,
assign debug_rom[21][7 : 0] = 8'h67;
assign debug_rom[21][15: 8] = 8'h00;
assign debug_rom[21][23:16] = 8'h00;
assign debug_rom[21][31:24] = 8'h40;
assign debug_rom[22][7 : 0] = 8'h73;
assign debug_rom[22][15: 8] = 8'h24;
assign debug_rom[22][23:16] = 8'h40;
assign debug_rom[22][31:24] = 8'hf1;
assign debug_rom[23][7 : 0] = 8'h23;
assign debug_rom[23][15: 8] = 8'h26;
assign debug_rom[23][23:16] = 8'h80;
assign debug_rom[23][31:24] = 8'h10;
// 0x73, 0x60, 0x04, 0x7b, 0x73, 0x24, 0x00, 0x7b, 0x13, 0x74, 0x04, 0x02,
assign debug_rom[24][7 : 0] = 8'h73;
assign debug_rom[24][15: 8] = 8'h60;
assign debug_rom[24][23:16] = 8'h04;
assign debug_rom[24][31:24] = 8'h7b;
assign debug_rom[25][7 : 0] = 8'h73;
assign debug_rom[25][15: 8] = 8'h24;
assign debug_rom[25][23:16] = 8'h00;
assign debug_rom[25][31:24] = 8'h7b;
assign debug_rom[26][7 : 0] = 8'h13;
assign debug_rom[26][15: 8] = 8'h74;
assign debug_rom[26][23:16] = 8'h04;
assign debug_rom[26][31:24] = 8'h02;
// 0xe3, 0x0c, 0x04, 0xfe, 0x6f, 0xf0, 0x1f, 0xfe).map(_.toByte)
assign debug_rom[27][7 : 0] = 8'he3;
assign debug_rom[27][15: 8] = 8'h0c;
assign debug_rom[27][23:16] = 8'h04;
assign debug_rom[27][31:24] = 8'hfe;
assign debug_rom[28][7 : 0] = 8'h6f;
assign debug_rom[28][15: 8] = 8'hf0;
assign debug_rom[28][23:16] = 8'h1f;
assign debug_rom[28][31:24] = 8'hfe;
endmodule
|
module sirv_qspi_media(
input clock,
input reset,
output io_port_sck,
input io_port_dq_0_i,
output io_port_dq_0_o,
output io_port_dq_0_oe,
input io_port_dq_1_i,
output io_port_dq_1_o,
output io_port_dq_1_oe,
input io_port_dq_2_i,
output io_port_dq_2_o,
output io_port_dq_2_oe,
input io_port_dq_3_i,
output io_port_dq_3_o,
output io_port_dq_3_oe,
output io_port_cs_0,
input [11:0] io_ctrl_sck_div,
input io_ctrl_sck_pol,
input io_ctrl_sck_pha,
input [7:0] io_ctrl_dla_cssck,
input [7:0] io_ctrl_dla_sckcs,
input [7:0] io_ctrl_dla_intercs,
input [7:0] io_ctrl_dla_interxfr,
input io_ctrl_cs_id,
input io_ctrl_cs_dflt_0,
output io_link_tx_ready,
input io_link_tx_valid,
input [7:0] io_link_tx_bits,
output io_link_rx_valid,
output [7:0] io_link_rx_bits,
input [7:0] io_link_cnt,
input [1:0] io_link_fmt_proto,
input io_link_fmt_endian,
input io_link_fmt_iodir,
input io_link_cs_set,
input io_link_cs_clear,
input io_link_cs_hold,
output io_link_active
);
wire phy_clock;
wire phy_reset;
wire phy_io_port_sck;
wire phy_io_port_dq_0_i;
wire phy_io_port_dq_0_o;
wire phy_io_port_dq_0_oe;
wire phy_io_port_dq_1_i;
wire phy_io_port_dq_1_o;
wire phy_io_port_dq_1_oe;
wire phy_io_port_dq_2_i;
wire phy_io_port_dq_2_o;
wire phy_io_port_dq_2_oe;
wire phy_io_port_dq_3_i;
wire phy_io_port_dq_3_o;
wire phy_io_port_dq_3_oe;
wire phy_io_port_cs_0;
wire [11:0] phy_io_ctrl_sck_div;
wire phy_io_ctrl_sck_pol;
wire phy_io_ctrl_sck_pha;
wire [1:0] phy_io_ctrl_fmt_proto;
wire phy_io_ctrl_fmt_endian;
wire phy_io_ctrl_fmt_iodir;
wire phy_io_op_ready;
wire phy_io_op_valid;
wire phy_io_op_bits_fn;
wire phy_io_op_bits_stb;
wire [7:0] phy_io_op_bits_cnt;
wire [7:0] phy_io_op_bits_data;
wire phy_io_rx_valid;
wire [7:0] phy_io_rx_bits;
reg cs_id;
reg [31:0] GEN_5;
reg cs_dflt_0;
reg [31:0] GEN_52;
reg cs_set;
reg [31:0] GEN_53;
wire [1:0] GEN_48;
wire [1:0] T_162;
wire [1:0] GEN_49;
wire [1:0] T_163;
wire T_164;
wire cs_active_0;
wire cs_update;
reg clear;
reg [31:0] GEN_54;
reg cs_assert;
reg [31:0] GEN_55;
wire T_175;
wire T_176;
wire cs_deassert;
wire T_177;
wire T_178;
wire continuous;
reg [1:0] state;
reg [31:0] GEN_56;
wire T_182;
wire [1:0] GEN_0;
wire [7:0] GEN_1;
wire [1:0] GEN_2;
wire T_184;
wire T_186;
wire [1:0] GEN_3;
wire GEN_4;
wire GEN_6;
wire GEN_7;
wire [1:0] GEN_8;
wire [7:0] GEN_9;
wire [1:0] GEN_10;
wire GEN_11;
wire GEN_12;
wire GEN_13;
wire GEN_14;
wire T_188;
wire T_189;
wire GEN_15;
wire GEN_16;
wire GEN_17;
wire [7:0] GEN_18;
wire GEN_19;
wire GEN_20;
wire GEN_21;
wire T_194;
wire T_195;
wire [7:0] GEN_22;
wire GEN_23;
wire GEN_24;
wire GEN_25;
wire [7:0] GEN_26;
wire [1:0] GEN_27;
wire GEN_28;
wire GEN_29;
wire GEN_30;
wire GEN_31;
wire GEN_32;
wire GEN_33;
wire GEN_34;
wire GEN_35;
wire T_198;
wire T_200;
wire T_201;
wire [1:0] GEN_36;
wire GEN_37;
wire [7:0] GEN_38;
wire [1:0] GEN_39;
wire T_202;
wire [1:0] GEN_50;
wire [1:0] T_206;
wire [1:0] GEN_51;
wire [1:0] T_207;
wire T_208;
wire T_213_0;
wire GEN_40;
wire [1:0] GEN_41;
wire [7:0] GEN_42;
wire GEN_43;
wire GEN_44;
wire GEN_45;
wire GEN_46;
wire [1:0] GEN_47;
sirv_qspi_physical phy (
.clock(phy_clock),
.reset(phy_reset),
.io_port_sck(phy_io_port_sck),
.io_port_dq_0_i(phy_io_port_dq_0_i),
.io_port_dq_0_o(phy_io_port_dq_0_o),
.io_port_dq_0_oe(phy_io_port_dq_0_oe),
.io_port_dq_1_i(phy_io_port_dq_1_i),
.io_port_dq_1_o(phy_io_port_dq_1_o),
.io_port_dq_1_oe(phy_io_port_dq_1_oe),
.io_port_dq_2_i(phy_io_port_dq_2_i),
.io_port_dq_2_o(phy_io_port_dq_2_o),
.io_port_dq_2_oe(phy_io_port_dq_2_oe),
.io_port_dq_3_i(phy_io_port_dq_3_i),
.io_port_dq_3_o(phy_io_port_dq_3_o),
.io_port_dq_3_oe(phy_io_port_dq_3_oe),
.io_port_cs_0(phy_io_port_cs_0),
.io_ctrl_sck_div(phy_io_ctrl_sck_div),
.io_ctrl_sck_pol(phy_io_ctrl_sck_pol),
.io_ctrl_sck_pha(phy_io_ctrl_sck_pha),
.io_ctrl_fmt_proto(phy_io_ctrl_fmt_proto),
.io_ctrl_fmt_endian(phy_io_ctrl_fmt_endian),
.io_ctrl_fmt_iodir(phy_io_ctrl_fmt_iodir),
.io_op_ready(phy_io_op_ready),
.io_op_valid(phy_io_op_valid),
.io_op_bits_fn(phy_io_op_bits_fn),
.io_op_bits_stb(phy_io_op_bits_stb),
.io_op_bits_cnt(phy_io_op_bits_cnt),
.io_op_bits_data(phy_io_op_bits_data),
.io_rx_valid(phy_io_rx_valid),
.io_rx_bits(phy_io_rx_bits)
);
assign io_port_sck = phy_io_port_sck;
assign io_port_dq_0_o = phy_io_port_dq_0_o;
assign io_port_dq_0_oe = phy_io_port_dq_0_oe;
assign io_port_dq_1_o = phy_io_port_dq_1_o;
assign io_port_dq_1_oe = phy_io_port_dq_1_oe;
assign io_port_dq_2_o = phy_io_port_dq_2_o;
assign io_port_dq_2_oe = phy_io_port_dq_2_oe;
assign io_port_dq_3_o = phy_io_port_dq_3_o;
assign io_port_dq_3_oe = phy_io_port_dq_3_oe;
assign io_port_cs_0 = cs_dflt_0;
assign io_link_tx_ready = GEN_31;
assign io_link_rx_valid = phy_io_rx_valid;
assign io_link_rx_bits = phy_io_rx_bits;
assign io_link_active = cs_assert;
assign phy_clock = clock;
assign phy_reset = reset;
assign phy_io_port_dq_0_i = io_port_dq_0_i;
assign phy_io_port_dq_1_i = io_port_dq_1_i;
assign phy_io_port_dq_2_i = io_port_dq_2_i;
assign phy_io_port_dq_3_i = io_port_dq_3_i;
assign phy_io_ctrl_sck_div = io_ctrl_sck_div;
assign phy_io_ctrl_sck_pol = io_ctrl_sck_pol;
assign phy_io_ctrl_sck_pha = io_ctrl_sck_pha;
assign phy_io_ctrl_fmt_proto = io_link_fmt_proto;
assign phy_io_ctrl_fmt_endian = io_link_fmt_endian;
assign phy_io_ctrl_fmt_iodir = io_link_fmt_iodir;
assign phy_io_op_valid = GEN_37;
assign phy_io_op_bits_fn = GEN_28;
assign phy_io_op_bits_stb = GEN_43;
assign phy_io_op_bits_cnt = GEN_42;
assign phy_io_op_bits_data = io_link_tx_bits;
assign GEN_48 = {{1'd0}, io_link_cs_set};
assign T_162 = GEN_48 << io_ctrl_cs_id;
assign GEN_49 = {{1'd0}, io_ctrl_cs_dflt_0};
assign T_163 = GEN_49 ^ T_162;
assign T_164 = T_163[0];
assign cs_active_0 = T_164;
assign cs_update = cs_active_0 != cs_dflt_0;
assign T_175 = io_link_cs_hold == 1'h0;
assign T_176 = cs_update & T_175;
assign cs_deassert = clear | T_176;
assign T_177 = io_link_cs_clear & cs_assert;
assign T_178 = clear | T_177;
assign continuous = io_ctrl_dla_interxfr == 8'h0;
assign T_182 = 2'h0 == state;
assign GEN_0 = phy_io_op_ready ? 2'h2 : state;
assign GEN_1 = cs_deassert ? io_ctrl_dla_sckcs : io_link_cnt;
assign GEN_2 = cs_deassert ? GEN_0 : state;
assign T_184 = cs_deassert == 1'h0;
assign T_186 = phy_io_op_ready & phy_io_op_valid;
assign GEN_3 = T_186 ? 2'h1 : GEN_2;
assign GEN_4 = T_184 ? 1'h0 : 1'h1;
assign GEN_6 = T_184 ? io_link_tx_valid : 1'h1;
assign GEN_7 = T_184 ? phy_io_op_ready : 1'h0;
assign GEN_8 = T_184 ? GEN_3 : GEN_2;
assign GEN_9 = cs_assert ? GEN_1 : io_link_cnt;
assign GEN_10 = cs_assert ? GEN_8 : state;
assign GEN_11 = cs_assert ? GEN_4 : 1'h1;
assign GEN_12 = cs_assert ? T_184 : 1'h0;
assign GEN_13 = cs_assert ? GEN_6 : 1'h1;
assign GEN_14 = cs_assert ? GEN_7 : 1'h0;
assign T_188 = cs_assert == 1'h0;
assign T_189 = T_188 & io_link_tx_valid;
assign GEN_15 = phy_io_op_ready ? 1'h1 : cs_assert;
assign GEN_16 = phy_io_op_ready ? io_link_cs_set : cs_set;
assign GEN_17 = phy_io_op_ready ? cs_active_0 : cs_dflt_0;
assign GEN_18 = T_189 ? io_ctrl_dla_cssck : GEN_9;
assign GEN_19 = T_189 ? GEN_15 : cs_assert;
assign GEN_20 = T_189 ? GEN_16 : cs_set;
assign GEN_21 = T_189 ? GEN_17 : cs_dflt_0;
assign T_194 = io_link_tx_valid == 1'h0;
assign T_195 = T_188 & T_194;
assign GEN_22 = T_195 ? 8'h0 : GEN_18;
assign GEN_23 = T_195 ? 1'h1 : GEN_12;
assign GEN_24 = T_195 ? io_ctrl_cs_id : cs_id;
assign GEN_25 = T_195 ? io_ctrl_cs_dflt_0 : GEN_21;
assign GEN_26 = T_182 ? GEN_22 : io_link_cnt;
assign GEN_27 = T_182 ? GEN_10 : state;
assign GEN_28 = T_182 ? GEN_11 : 1'h1;
assign GEN_29 = T_182 ? GEN_23 : 1'h0;
assign GEN_30 = T_182 ? GEN_13 : 1'h1;
assign GEN_31 = T_182 ? GEN_14 : 1'h0;
assign GEN_32 = T_182 ? GEN_19 : cs_assert;
assign GEN_33 = T_182 ? GEN_20 : cs_set;
assign GEN_34 = T_182 ? GEN_25 : cs_dflt_0;
assign GEN_35 = T_182 ? GEN_24 : cs_id;
assign T_198 = 2'h1 == state;
assign T_200 = continuous == 1'h0;
assign T_201 = phy_io_op_ready | continuous;
assign GEN_36 = T_201 ? 2'h0 : GEN_27;
assign GEN_37 = T_198 ? T_200 : GEN_30;
assign GEN_38 = T_198 ? io_ctrl_dla_interxfr : GEN_26;
assign GEN_39 = T_198 ? GEN_36 : GEN_27;
assign T_202 = 2'h2 == state;
assign GEN_50 = {{1'd0}, cs_set};
assign T_206 = GEN_50 << cs_id;
assign GEN_51 = {{1'd0}, cs_dflt_0};
assign T_207 = GEN_51 ^ T_206;
assign T_208 = T_207[0];
assign T_213_0 = T_208;
assign GEN_40 = phy_io_op_ready ? T_213_0 : GEN_34;
assign GEN_41 = phy_io_op_ready ? 2'h0 : GEN_39;
assign GEN_42 = T_202 ? io_ctrl_dla_intercs : GEN_38;
assign GEN_43 = T_202 ? 1'h1 : GEN_29;
assign GEN_44 = T_202 ? 1'h0 : GEN_32;
assign GEN_45 = T_202 ? 1'h0 : T_178;
assign GEN_46 = T_202 ? GEN_40 : GEN_34;
assign GEN_47 = T_202 ? GEN_41 : GEN_39;
always @(posedge clock or posedge reset)
if(reset) begin
cs_id <= 2'b0;
cs_dflt_0 <= 1'b1;
cs_set <= 1'b0;
end
else begin//{
if (T_182) begin
if (T_195) begin
cs_id <= io_ctrl_cs_id;
end
end
if (T_202) begin
if (phy_io_op_ready) begin
cs_dflt_0 <= T_213_0;
end else begin
if (T_182) begin
if (T_195) begin
cs_dflt_0 <= io_ctrl_cs_dflt_0;
end else begin
if (T_189) begin
if (phy_io_op_ready) begin
cs_dflt_0 <= cs_active_0;
end
end
end
end
end
end else begin
if (T_182) begin
if (T_195) begin
cs_dflt_0 <= io_ctrl_cs_dflt_0;
end else begin
if (T_189) begin
if (phy_io_op_ready) begin
cs_dflt_0 <= cs_active_0;
end
end
end
end
end
if (T_182) begin
if (T_189) begin
if (phy_io_op_ready) begin
cs_set <= io_link_cs_set;
end
end
end
end//}
always @(posedge clock or posedge reset)
if (reset) begin
clear <= 1'h0;
end else begin
if (T_202) begin
clear <= 1'h0;
end else begin
clear <= T_178;
end
end
always @(posedge clock or posedge reset)
if (reset) begin
cs_assert <= 1'h0;
end else begin
if (T_202) begin
cs_assert <= 1'h0;
end else begin
if (T_182) begin
if (T_189) begin
if (phy_io_op_ready) begin
cs_assert <= 1'h1;
end
end
end
end
end
always @(posedge clock or posedge reset)
if (reset) begin
state <= 2'h0;
end else begin
if (T_202) begin
if (phy_io_op_ready) begin
state <= 2'h0;
end else begin
if (T_198) begin
if (T_201) begin
state <= 2'h0;
end else begin
if (T_182) begin
if (cs_assert) begin
if (T_184) begin
if (T_186) begin
state <= 2'h1;
end else begin
if (cs_deassert) begin
if (phy_io_op_ready) begin
state <= 2'h2;
end
end
end
end else begin
if (cs_deassert) begin
if (phy_io_op_ready) begin
state <= 2'h2;
end
end
end
end
end
end
end else begin
if (T_182) begin
if (cs_assert) begin
if (T_184) begin
if (T_186) begin
state <= 2'h1;
end else begin
if (cs_deassert) begin
if (phy_io_op_ready) begin
state <= 2'h2;
end
end
end
end else begin
if (cs_deassert) begin
if (phy_io_op_ready) begin
state <= 2'h2;
end
end
end
end
end
end
end
end else begin
if (T_198) begin
if (T_201) begin
state <= 2'h0;
end else begin
if (T_182) begin
if (cs_assert) begin
if (T_184) begin
if (T_186) begin
state <= 2'h1;
end else begin
state <= GEN_2;
end
end else begin
state <= GEN_2;
end
end
end
end
end else begin
if (T_182) begin
if (cs_assert) begin
if (T_184) begin
if (T_186) begin
state <= 2'h1;
end else begin
state <= GEN_2;
end
end else begin
state <= GEN_2;
end
end
end
end
end
end
endmodule
|
module sirv_jtaggpioport(
input clock,
input reset,
output io_jtag_TCK,
output io_jtag_TMS,
output io_jtag_TDI,
input io_jtag_TDO,
output io_jtag_TRST,
input io_jtag_DRV_TDO,
input io_pins_TCK_i_ival,
output io_pins_TCK_o_oval,
output io_pins_TCK_o_oe,
output io_pins_TCK_o_ie,
output io_pins_TCK_o_pue,
output io_pins_TCK_o_ds,
input io_pins_TMS_i_ival,
output io_pins_TMS_o_oval,
output io_pins_TMS_o_oe,
output io_pins_TMS_o_ie,
output io_pins_TMS_o_pue,
output io_pins_TMS_o_ds,
input io_pins_TDI_i_ival,
output io_pins_TDI_o_oval,
output io_pins_TDI_o_oe,
output io_pins_TDI_o_ie,
output io_pins_TDI_o_pue,
output io_pins_TDI_o_ds,
input io_pins_TDO_i_ival,
output io_pins_TDO_o_oval,
output io_pins_TDO_o_oe,
output io_pins_TDO_o_ie,
output io_pins_TDO_o_pue,
output io_pins_TDO_o_ds,
input io_pins_TRST_n_i_ival,
output io_pins_TRST_n_o_oval,
output io_pins_TRST_n_o_oe,
output io_pins_TRST_n_o_ie,
output io_pins_TRST_n_o_pue,
output io_pins_TRST_n_o_ds
);
wire T_101;
wire T_117;
assign io_jtag_TCK = T_101;
assign io_jtag_TMS = io_pins_TMS_i_ival;
assign io_jtag_TDI = io_pins_TDI_i_ival;
assign io_jtag_TRST = T_117;
assign io_pins_TCK_o_oval = 1'h0;
assign io_pins_TCK_o_oe = 1'h0;
assign io_pins_TCK_o_ie = 1'h1;
assign io_pins_TCK_o_pue = 1'h1;
assign io_pins_TCK_o_ds = 1'h0;
assign io_pins_TMS_o_oval = 1'h0;
assign io_pins_TMS_o_oe = 1'h0;
assign io_pins_TMS_o_ie = 1'h1;
assign io_pins_TMS_o_pue = 1'h1;
assign io_pins_TMS_o_ds = 1'h0;
assign io_pins_TDI_o_oval = 1'h0;
assign io_pins_TDI_o_oe = 1'h0;
assign io_pins_TDI_o_ie = 1'h1;
assign io_pins_TDI_o_pue = 1'h1;
assign io_pins_TDI_o_ds = 1'h0;
assign io_pins_TDO_o_oval = io_jtag_TDO;
assign io_pins_TDO_o_oe = io_jtag_DRV_TDO;
assign io_pins_TDO_o_ie = 1'h0;
assign io_pins_TDO_o_pue = 1'h0;
assign io_pins_TDO_o_ds = 1'h0;
assign io_pins_TRST_n_o_oval = 1'h0;
assign io_pins_TRST_n_o_oe = 1'h0;
assign io_pins_TRST_n_o_ie = 1'h1;
assign io_pins_TRST_n_o_pue = 1'h1;
assign io_pins_TRST_n_o_ds = 1'h0;
assign T_101 = $unsigned(io_pins_TCK_i_ival);
assign T_117 = ~ io_pins_TRST_n_i_ival;
endmodule
|
module sirv_debug_module
# (
parameter SUPPORT_JTAG_DTM = 1,
parameter ASYNC_FF_LEVELS = 2,
parameter PC_SIZE = 32,
parameter HART_NUM = 1,
parameter HART_ID_W = 1
) (
output inspect_jtag_clk,
// The interface with commit stage
input [PC_SIZE-1:0] cmt_dpc,
input cmt_dpc_ena,
input [3-1:0] cmt_dcause,
input cmt_dcause_ena,
input dbg_irq_r,
// The interface with CSR control
input wr_dcsr_ena ,
input wr_dpc_ena ,
input wr_dscratch_ena,
input [32-1:0] wr_csr_nxt ,
output[32-1:0] dcsr_r ,
output[PC_SIZE-1:0] dpc_r ,
output[32-1:0] dscratch_r,
output dbg_mode,
output dbg_halt_r,
output dbg_step_r,
output dbg_ebreakm_r,
output dbg_stopcycle,
// The system memory bus interface
input i_icb_cmd_valid,
output i_icb_cmd_ready,
input [12-1:0] i_icb_cmd_addr,
input i_icb_cmd_read,
input [32-1:0] i_icb_cmd_wdata,
output i_icb_rsp_valid,
input i_icb_rsp_ready,
output [32-1:0] i_icb_rsp_rdata,
input io_pads_jtag_TCK_i_ival,
output io_pads_jtag_TCK_o_oval,
output io_pads_jtag_TCK_o_oe,
output io_pads_jtag_TCK_o_ie,
output io_pads_jtag_TCK_o_pue,
output io_pads_jtag_TCK_o_ds,
input io_pads_jtag_TMS_i_ival,
output io_pads_jtag_TMS_o_oval,
output io_pads_jtag_TMS_o_oe,
output io_pads_jtag_TMS_o_ie,
output io_pads_jtag_TMS_o_pue,
output io_pads_jtag_TMS_o_ds,
input io_pads_jtag_TDI_i_ival,
output io_pads_jtag_TDI_o_oval,
output io_pads_jtag_TDI_o_oe,
output io_pads_jtag_TDI_o_ie,
output io_pads_jtag_TDI_o_pue,
output io_pads_jtag_TDI_o_ds,
input io_pads_jtag_TDO_i_ival,
output io_pads_jtag_TDO_o_oval,
output io_pads_jtag_TDO_o_oe,
output io_pads_jtag_TDO_o_ie,
output io_pads_jtag_TDO_o_pue,
output io_pads_jtag_TDO_o_ds,
input io_pads_jtag_TRST_n_i_ival,
output io_pads_jtag_TRST_n_o_oval,
output io_pads_jtag_TRST_n_o_oe,
output io_pads_jtag_TRST_n_o_ie,
output io_pads_jtag_TRST_n_o_pue,
output io_pads_jtag_TRST_n_o_ds,
// To the target hart
output [HART_NUM-1:0] o_dbg_irq,
output [HART_NUM-1:0] o_ndreset,
output [HART_NUM-1:0] o_fullreset,
input core_csr_clk,
input hfclk,
input corerst,
input test_mode
);
wire dm_rst;
wire dm_rst_n;
//This is to reset Debug module's logic, the debug module have same clock domain
// as the main domain, so just use the same reset.
sirv_ResetCatchAndSync_2 u_dm_ResetCatchAndSync_2_1 (
.test_mode(test_mode),
.clock(hfclk),// Use same clock as main domain
.reset(corerst),
.io_sync_reset(dm_rst)
);
assign dm_rst_n = ~dm_rst;
//This is to reset the JTAG_CLK relevant logics, since the chip does not
// have the JTAG_RST used really, so we need to use the global chip reset to reset
// JTAG relevant logics
wire jtag_TCK;
wire jtag_reset;
sirv_ResetCatchAndSync u_jtag_ResetCatchAndSync_3_1 (
.test_mode(test_mode),
.clock(jtag_TCK),
.reset(corerst),
.io_sync_reset(jtag_reset)
);
wire dm_clk = hfclk;// Currently Debug Module have same clock domain as core
wire jtag_TDI;
wire jtag_TDO;
wire jtag_TMS;
wire jtag_TRST;
wire jtag_DRV_TDO;
sirv_jtaggpioport u_jtag_pins (
.clock(1'b0),
.reset(1'b1),
.io_jtag_TCK(jtag_TCK),
.io_jtag_TMS(jtag_TMS),
.io_jtag_TDI(jtag_TDI),
.io_jtag_TDO(jtag_TDO),
.io_jtag_TRST(jtag_TRST),
.io_jtag_DRV_TDO(jtag_DRV_TDO),
.io_pins_TCK_i_ival(io_pads_jtag_TCK_i_ival),
.io_pins_TCK_o_oval(io_pads_jtag_TCK_o_oval),
.io_pins_TCK_o_oe(io_pads_jtag_TCK_o_oe),
.io_pins_TCK_o_ie(io_pads_jtag_TCK_o_ie),
.io_pins_TCK_o_pue(io_pads_jtag_TCK_o_pue),
.io_pins_TCK_o_ds(io_pads_jtag_TCK_o_ds),
.io_pins_TMS_i_ival(io_pads_jtag_TMS_i_ival),
.io_pins_TMS_o_oval(io_pads_jtag_TMS_o_oval),
.io_pins_TMS_o_oe(io_pads_jtag_TMS_o_oe),
.io_pins_TMS_o_ie(io_pads_jtag_TMS_o_ie),
.io_pins_TMS_o_pue(io_pads_jtag_TMS_o_pue),
.io_pins_TMS_o_ds(io_pads_jtag_TMS_o_ds),
.io_pins_TDI_i_ival(io_pads_jtag_TDI_i_ival),
.io_pins_TDI_o_oval(io_pads_jtag_TDI_o_oval),
.io_pins_TDI_o_oe(io_pads_jtag_TDI_o_oe),
.io_pins_TDI_o_ie(io_pads_jtag_TDI_o_ie),
.io_pins_TDI_o_pue(io_pads_jtag_TDI_o_pue),
.io_pins_TDI_o_ds(io_pads_jtag_TDI_o_ds),
.io_pins_TDO_i_ival(io_pads_jtag_TDO_i_ival),
.io_pins_TDO_o_oval(io_pads_jtag_TDO_o_oval),
.io_pins_TDO_o_oe(io_pads_jtag_TDO_o_oe),
.io_pins_TDO_o_ie(io_pads_jtag_TDO_o_ie),
.io_pins_TDO_o_pue(io_pads_jtag_TDO_o_pue),
.io_pins_TDO_o_ds(io_pads_jtag_TDO_o_ds),
.io_pins_TRST_n_i_ival(io_pads_jtag_TRST_n_i_ival),
.io_pins_TRST_n_o_oval(io_pads_jtag_TRST_n_o_oval),
.io_pins_TRST_n_o_oe(io_pads_jtag_TRST_n_o_oe),
.io_pins_TRST_n_o_ie(io_pads_jtag_TRST_n_o_ie),
.io_pins_TRST_n_o_pue(io_pads_jtag_TRST_n_o_pue),
.io_pins_TRST_n_o_ds(io_pads_jtag_TRST_n_o_ds)
);
sirv_debug_csr # (
.PC_SIZE(PC_SIZE)
) u_sirv_debug_csr (
.dbg_stopcycle (dbg_stopcycle ),
.dbg_irq_r (dbg_irq_r ),
.cmt_dpc (cmt_dpc ),
.cmt_dpc_ena (cmt_dpc_ena ),
.cmt_dcause (cmt_dcause ),
.cmt_dcause_ena (cmt_dcause_ena ),
.wr_dcsr_ena (wr_dcsr_ena ),
.wr_dpc_ena (wr_dpc_ena ),
.wr_dscratch_ena (wr_dscratch_ena),
.wr_csr_nxt (wr_csr_nxt ),
.dcsr_r (dcsr_r ),
.dpc_r (dpc_r ),
.dscratch_r (dscratch_r ),
.dbg_mode (dbg_mode),
.dbg_halt_r (dbg_halt_r),
.dbg_step_r (dbg_step_r),
.dbg_ebreakm_r (dbg_ebreakm_r),
.clk (core_csr_clk),
.rst_n (dm_rst_n )
);
// The debug bus interface
wire dtm_req_valid;
wire dtm_req_ready;
wire [41-1 :0] dtm_req_bits;
wire dtm_resp_valid;
wire dtm_resp_ready;
wire [36-1 : 0] dtm_resp_bits;
generate
if(SUPPORT_JTAG_DTM == 1) begin: jtag_dtm_gen
sirv_jtag_dtm # (
.ASYNC_FF_LEVELS(ASYNC_FF_LEVELS)
) u_sirv_jtag_dtm (
.jtag_TDI (jtag_TDI ),
.jtag_TDO (jtag_TDO ),
.jtag_TCK (jtag_TCK ),
.jtag_TMS (jtag_TMS ),
.jtag_TRST (jtag_reset ),
.jtag_DRV_TDO (jtag_DRV_TDO ),
.dtm_req_valid (dtm_req_valid ),
.dtm_req_ready (dtm_req_ready ),
.dtm_req_bits (dtm_req_bits ),
.dtm_resp_valid (dtm_resp_valid),
.dtm_resp_ready (dtm_resp_ready),
.dtm_resp_bits (dtm_resp_bits )
);
end
else begin: no_jtag_dtm_gen
assign jtag_TDI = 1'b0;
assign jtag_TDO = 1'b0;
assign jtag_TCK = 1'b0;
assign jtag_TMS = 1'b0;
assign jtag_DRV_TDO = 1'b0;
assign dtm_req_valid = 1'b0;
assign dtm_req_bits = 41'b0;
assign dtm_resp_ready = 1'b0;
end
endgenerate
wire i_dtm_req_valid;
wire i_dtm_req_ready;
wire [41-1 :0] i_dtm_req_bits;
wire i_dtm_resp_valid;
wire i_dtm_resp_ready;
wire [36-1 : 0] i_dtm_resp_bits;
sirv_gnrl_cdc_tx
# (
.DW (36),
.SYNC_DP (ASYNC_FF_LEVELS)
) u_dm2dtm_cdc_tx (
.o_vld (dtm_resp_valid),
.o_rdy_a(dtm_resp_ready),
.o_dat (dtm_resp_bits ),
.i_vld (i_dtm_resp_valid),
.i_rdy (i_dtm_resp_ready),
.i_dat (i_dtm_resp_bits ),
.clk (dm_clk),
.rst_n (dm_rst_n)
);
sirv_gnrl_cdc_rx
# (
.DW (41),
.SYNC_DP (ASYNC_FF_LEVELS)
) u_dm2dtm_cdc_rx (
.i_vld_a(dtm_req_valid),
.i_rdy (dtm_req_ready),
.i_dat (dtm_req_bits ),
.o_vld (i_dtm_req_valid),
.o_rdy (i_dtm_req_ready),
.o_dat (i_dtm_req_bits ),
.clk (dm_clk),
.rst_n (dm_rst_n)
);
wire i_dtm_req_hsked = i_dtm_req_valid & i_dtm_req_ready;
wire [ 4:0] dtm_req_bits_addr;
wire [33:0] dtm_req_bits_data;
wire [ 1:0] dtm_req_bits_op;
wire [33:0] dtm_resp_bits_data;
wire [ 1:0] dtm_resp_bits_resp;
assign dtm_req_bits_addr = i_dtm_req_bits[40:36];
assign dtm_req_bits_data = i_dtm_req_bits[35:2];
assign dtm_req_bits_op = i_dtm_req_bits[1:0];
assign i_dtm_resp_bits = {dtm_resp_bits_data, dtm_resp_bits_resp};
// The OP field
// 0: Ignore data. (nop)
// 1: Read from address. (read)
// 2: Read from address. Then write data to address. (write)
// 3: Reserved.
wire dtm_req_rd = (dtm_req_bits_op == 2'd1);
wire dtm_req_wr = (dtm_req_bits_op == 2'd2);
wire dtm_req_sel_dbgram = (dtm_req_bits_addr[4:3] == 2'b0) & (~(dtm_req_bits_addr[2:0] == 3'b111));//0x00-0x06
wire dtm_req_sel_dmcontrl = (dtm_req_bits_addr == 5'h10);
wire dtm_req_sel_dminfo = (dtm_req_bits_addr == 5'h11);
wire dtm_req_sel_haltstat = (dtm_req_bits_addr == 5'h1C);
wire [33:0] dminfo_r;
wire [33:0] dmcontrol_r;
wire [HART_NUM-1:0] dm_haltnot_r;
wire [HART_NUM-1:0] dm_debint_r;
//In the future if it is multi-core, then we need to add the core ID, to support this
// text from the debug_spec_v0.11
// At the cost of more hardware, this can be resolved in two ways. If
// the bus knows an ID for the originator, then the Debug Module can refuse write
// accesses to originators that don't match the hart ID set in hartid of dmcontrol.
//
// The Resp field
// 0: The previous operation completed successfully.
// 1: Reserved.
// 2: The previous operation failed. The data scanned into dbus in this access
// will be ignored. This status is sticky and can be cleared by writing dbusreset in dtmcontrol.
// 3: The previous operation is still in progress. The data scanned into dbus
// in this access will be ignored.
wire [31:0] ram_dout;
assign dtm_resp_bits_data =
({34{dtm_req_sel_dbgram }} & {dmcontrol_r[33:32],ram_dout})
| ({34{dtm_req_sel_dmcontrl}} & dmcontrol_r)
| ({34{dtm_req_sel_dminfo }} & dminfo_r)
| ({34{dtm_req_sel_haltstat}} & {{34-HART_ID_W{1'b0}},dm_haltnot_r});
assign dtm_resp_bits_resp = 2'd0;
wire icb_access_dbgram_ena;
wire i_dtm_req_condi = dtm_req_sel_dbgram ? (~icb_access_dbgram_ena) : 1'b1;
assign i_dtm_req_ready = i_dtm_req_condi & i_dtm_resp_ready;
assign i_dtm_resp_valid = i_dtm_req_condi & i_dtm_req_valid;
// DMINFORdData_reserved0 = 2'h0;
// DMINFORdData_abussize = 7'h0;
// DMINFORdData_serialcount = 4'h0;
// DMINFORdData_access128 = 1'h0;
// DMINFORdData_access64 = 1'h0;
// DMINFORdData_access32 = 1'h0;
// DMINFORdData_access16 = 1'h0;
// DMINFORdData_accesss8 = 1'h0;
// DMINFORdData_dramsize = 6'h6;
// DMINFORdData_haltsum = 1'h0;
// DMINFORdData_reserved1 = 3'h0;
// DMINFORdData_authenticated = 1'h1;
// DMINFORdData_authbusy = 1'h0;
// DMINFORdData_authtype = 2'h0;
// DMINFORdData_version = 2'h1;
assign dminfo_r[33:16] = 18'b0;
assign dminfo_r[15:10] = 6'h6;
assign dminfo_r[9:6] = 4'b0;
assign dminfo_r[5] = 1'h1;
assign dminfo_r[4:2] = 3'b0;
assign dminfo_r[1:0] = 2'h1;
wire [HART_ID_W-1:0] dm_hartid_r;
wire [1:0] dm_debint_arr = {1'b0,dm_debint_r };
wire [1:0] dm_haltnot_arr = {1'b0,dm_haltnot_r};
assign dmcontrol_r[33] = dm_debint_arr [dm_hartid_r];
assign dmcontrol_r[32] = dm_haltnot_arr[dm_hartid_r];
assign dmcontrol_r[31:12] = 20'b0;
assign dmcontrol_r[11:2] = {{10-HART_ID_W{1'b0}},dm_hartid_r};
assign dmcontrol_r[1:0] = 2'b0;
wire dtm_wr_dmcontrol = dtm_req_sel_dmcontrl & dtm_req_wr;
wire dtm_wr_dbgram = dtm_req_sel_dbgram & dtm_req_wr;
wire dtm_wr_interrupt_ena = i_dtm_req_hsked & (dtm_wr_dmcontrol | dtm_wr_dbgram) & dtm_req_bits_data[33];//W1
wire dtm_wr_haltnot_ena = i_dtm_req_hsked & (dtm_wr_dmcontrol | dtm_wr_dbgram) & (~dtm_req_bits_data[32]);//W0
wire dtm_wr_hartid_ena = i_dtm_req_hsked & dtm_wr_dmcontrol;
wire dtm_wr_dbgram_ena = i_dtm_req_hsked & dtm_wr_dbgram;
wire dtm_access_dbgram_ena = i_dtm_req_hsked & dtm_req_sel_dbgram;
wire dm_hartid_ena = dtm_wr_hartid_ena;
wire [HART_ID_W-1:0] dm_hartid_nxt = dtm_req_bits_data[HART_ID_W+2-1:2];
sirv_gnrl_dfflr #(HART_ID_W) dm_hartid_dfflr (dm_hartid_ena, dm_hartid_nxt, dm_hartid_r, dm_clk, dm_rst_n);
//////////////////////////////////////////////////////////////
// Impelement the DM ICB system bus agent
// 0x100 - 0x2ff Debug Module registers described in Section 7.12.
// * Only two registers needed, others are not supported
// cleardebint, at 0x100
// sethaltnot, at 0x10c
// 0x400 - 0x4ff Up to 256 bytes of Debug RAM. Each unique address species 8 bits.
// * Since this is remapped to each core's ITCM, we dont handle it at this module
// 0x800 - 0x9ff Up to 512 bytes of Debug ROM.
//
//
wire i_icb_cmd_hsked = i_icb_cmd_valid & i_icb_cmd_ready;
wire icb_wr_ena = i_icb_cmd_hsked & (~i_icb_cmd_read);
wire icb_sel_cleardebint = (i_icb_cmd_addr == 12'h100);
wire icb_sel_sethaltnot = (i_icb_cmd_addr == 12'h10c);
wire icb_sel_dbgrom = (i_icb_cmd_addr[12-1:8] == 4'h8);
wire icb_sel_dbgram = (i_icb_cmd_addr[12-1:8] == 4'h4);
wire icb_wr_cleardebint_ena = icb_wr_ena & icb_sel_cleardebint;
wire icb_wr_sethaltnot_ena = icb_wr_ena & icb_sel_sethaltnot ;
assign icb_access_dbgram_ena = i_icb_cmd_hsked & icb_sel_dbgram;
wire cleardebint_ena = icb_wr_cleardebint_ena;
wire [HART_ID_W-1:0] cleardebint_r;
wire [HART_ID_W-1:0] cleardebint_nxt = i_icb_cmd_wdata[HART_ID_W-1:0];
sirv_gnrl_dfflr #(HART_ID_W) cleardebint_dfflr (cleardebint_ena, cleardebint_nxt, cleardebint_r, dm_clk, dm_rst_n);
wire sethaltnot_ena = icb_wr_sethaltnot_ena;
wire [HART_ID_W-1:0] sethaltnot_r;
wire [HART_ID_W-1:0] sethaltnot_nxt = i_icb_cmd_wdata[HART_ID_W-1:0];
sirv_gnrl_dfflr #(HART_ID_W) sethaltnot_dfflr (sethaltnot_ena, sethaltnot_nxt, sethaltnot_r, dm_clk, dm_rst_n);
assign i_icb_rsp_valid = i_icb_cmd_valid;// Just directly pass back the valid in 0 cycle
assign i_icb_cmd_ready = i_icb_rsp_ready;
wire [31:0] rom_dout;
assign i_icb_rsp_rdata =
({32{icb_sel_cleardebint}} & {{32-HART_ID_W{1'b0}}, cleardebint_r})
| ({32{icb_sel_sethaltnot }} & {{32-HART_ID_W{1'b0}}, sethaltnot_r})
| ({32{icb_sel_dbgrom }} & rom_dout)
| ({32{icb_sel_dbgram }} & ram_dout);
sirv_debug_rom u_sirv_debug_rom (
.rom_addr (i_icb_cmd_addr[7-1:2]),
.rom_dout (rom_dout)
);
//sirv_debug_rom_64 u_sirv_debug_rom_64(
// .rom_addr (i_icb_cmd_addr[8-1:2]),
// .rom_dout (rom_dout)
//);
wire ram_cs = dtm_access_dbgram_ena | icb_access_dbgram_ena;
wire [3-1:0] ram_addr = dtm_access_dbgram_ena ? dtm_req_bits_addr[2:0] : i_icb_cmd_addr[4:2];
wire ram_rd = dtm_access_dbgram_ena ? dtm_req_rd : i_icb_cmd_read;
wire [32-1:0]ram_wdat = dtm_access_dbgram_ena ? dtm_req_bits_data[31:0]: i_icb_cmd_wdata;
sirv_debug_ram u_sirv_debug_ram(
.clk (dm_clk),
.rst_n (dm_rst_n),
.ram_cs (ram_cs),
.ram_rd (ram_rd),
.ram_addr (ram_addr),
.ram_wdat (ram_wdat),
.ram_dout (ram_dout)
);
wire [HART_NUM-1:0] dm_haltnot_set;
wire [HART_NUM-1:0] dm_haltnot_clr;
wire [HART_NUM-1:0] dm_haltnot_ena;
wire [HART_NUM-1:0] dm_haltnot_nxt;
wire [HART_NUM-1:0] dm_debint_set;
wire [HART_NUM-1:0] dm_debint_clr;
wire [HART_NUM-1:0] dm_debint_ena;
wire [HART_NUM-1:0] dm_debint_nxt;
genvar i;
generate
for(i = 0; i < HART_NUM; i = i+1)//{
begin:dm_halt_int_gen
// The haltnot will be set by system bus set its ID to sethaltnot_r
assign dm_haltnot_set[i] = icb_wr_sethaltnot_ena & (i_icb_cmd_wdata[HART_ID_W-1:0] == i[HART_ID_W-1:0]);
// The haltnot will be cleared by DTM write 0 to haltnot
assign dm_haltnot_clr[i] = dtm_wr_haltnot_ena & (dm_hartid_r == i[HART_ID_W-1:0]);
assign dm_haltnot_ena[i] = dm_haltnot_set[i] | dm_haltnot_clr[i];
assign dm_haltnot_nxt[i] = dm_haltnot_set[i] | (~dm_haltnot_clr[i]);
sirv_gnrl_dfflr #(1) dm_haltnot_dfflr (dm_haltnot_ena[i], dm_haltnot_nxt[i], dm_haltnot_r[i], dm_clk, dm_rst_n);
// The debug intr will be set by DTM write 1 to interrupt
assign dm_debint_set[i] = dtm_wr_interrupt_ena & (dm_hartid_r == i[HART_ID_W-1:0]);
// The debug intr will be clear by system bus set its ID to cleardebint_r
assign dm_debint_clr[i] = icb_wr_cleardebint_ena & (i_icb_cmd_wdata[HART_ID_W-1:0] == i[HART_ID_W-1:0]);
assign dm_debint_ena[i] = dm_debint_set[i] | dm_debint_clr[i];
assign dm_debint_nxt[i] = dm_debint_set[i] | (~dm_debint_clr[i]);
sirv_gnrl_dfflr #(1) dm_debint_dfflr ( dm_debint_ena[i], dm_debint_nxt[i], dm_debint_r[i], dm_clk, dm_rst_n);
end//}
endgenerate
assign o_dbg_irq = dm_debint_r;
assign o_ndreset = {HART_NUM{1'b0}};
assign o_fullreset = {HART_NUM{1'b0}};
assign inspect_jtag_clk = jtag_TCK;
endmodule
|
module sirv_AsyncResetReg (
input d,
output reg q,
input en,
input clk,
input rst);
always @(posedge clk or posedge rst) begin
if (rst) begin
q <= 1'b0;
end else if (en) begin
q <= d;
end
end
endmodule // AsyncResetReg
|
module sirv_pmu_core(
input clock,
input reset,
input io_wakeup_awakeup,
input io_wakeup_dwakeup,
input io_wakeup_rtc,
input io_wakeup_reset,
output io_control_valid,
output io_control_bits_hfclkrst,
output io_control_bits_corerst,
output io_control_bits_reserved1,
output io_control_bits_vddpaden,
output io_control_bits_reserved0,
input [1:0] io_resetCause,
input io_regs_ie_write_valid,
input [3:0] io_regs_ie_write_bits,
output [3:0] io_regs_ie_read,
input io_regs_cause_write_valid,
input [31:0] io_regs_cause_write_bits,
output [31:0] io_regs_cause_read,
input io_regs_sleep_write_valid,
input [31:0] io_regs_sleep_write_bits,
output [31:0] io_regs_sleep_read,
input io_regs_key_write_valid,
input [31:0] io_regs_key_write_bits,
output [31:0] io_regs_key_read,
input io_regs_wakeupProgram_0_write_valid,
input [31:0] io_regs_wakeupProgram_0_write_bits,
output [31:0] io_regs_wakeupProgram_0_read,
input io_regs_wakeupProgram_1_write_valid,
input [31:0] io_regs_wakeupProgram_1_write_bits,
output [31:0] io_regs_wakeupProgram_1_read,
input io_regs_wakeupProgram_2_write_valid,
input [31:0] io_regs_wakeupProgram_2_write_bits,
output [31:0] io_regs_wakeupProgram_2_read,
input io_regs_wakeupProgram_3_write_valid,
input [31:0] io_regs_wakeupProgram_3_write_bits,
output [31:0] io_regs_wakeupProgram_3_read,
input io_regs_wakeupProgram_4_write_valid,
input [31:0] io_regs_wakeupProgram_4_write_bits,
output [31:0] io_regs_wakeupProgram_4_read,
input io_regs_wakeupProgram_5_write_valid,
input [31:0] io_regs_wakeupProgram_5_write_bits,
output [31:0] io_regs_wakeupProgram_5_read,
input io_regs_wakeupProgram_6_write_valid,
input [31:0] io_regs_wakeupProgram_6_write_bits,
output [31:0] io_regs_wakeupProgram_6_read,
input io_regs_wakeupProgram_7_write_valid,
input [31:0] io_regs_wakeupProgram_7_write_bits,
output [31:0] io_regs_wakeupProgram_7_read,
input io_regs_sleepProgram_0_write_valid,
input [31:0] io_regs_sleepProgram_0_write_bits,
output [31:0] io_regs_sleepProgram_0_read,
input io_regs_sleepProgram_1_write_valid,
input [31:0] io_regs_sleepProgram_1_write_bits,
output [31:0] io_regs_sleepProgram_1_read,
input io_regs_sleepProgram_2_write_valid,
input [31:0] io_regs_sleepProgram_2_write_bits,
output [31:0] io_regs_sleepProgram_2_read,
input io_regs_sleepProgram_3_write_valid,
input [31:0] io_regs_sleepProgram_3_write_bits,
output [31:0] io_regs_sleepProgram_3_read,
input io_regs_sleepProgram_4_write_valid,
input [31:0] io_regs_sleepProgram_4_write_bits,
output [31:0] io_regs_sleepProgram_4_read,
input io_regs_sleepProgram_5_write_valid,
input [31:0] io_regs_sleepProgram_5_write_bits,
output [31:0] io_regs_sleepProgram_5_read,
input io_regs_sleepProgram_6_write_valid,
input [31:0] io_regs_sleepProgram_6_write_bits,
output [31:0] io_regs_sleepProgram_6_read,
input io_regs_sleepProgram_7_write_valid,
input [31:0] io_regs_sleepProgram_7_write_bits,
output [31:0] io_regs_sleepProgram_7_read
);
reg wantSleep;
reg run;
reg [31:0] GEN_37;
reg awake;
reg [31:0] GEN_38;
wire T_364;
wire T_365;
wire T_366;
wire T_367;
wire T_368;
wire T_369;
wire T_370;
wire T_371;
wire T_372;
wire T_373;
wire T_374;
wire T_375;
wire T_376;
wire T_377;
wire T_378;
wire T_379;
wire T_380;
wire T_381;
wire T_383;
wire T_385;
wire T_386;
wire T_388;
reg unlocked;
reg [31:0] GEN_39;
wire GEN_0;
wire T_391;
reg [31:0] GEN_40;
wire GEN_1;
reg [2:0] pc;
reg [31:0] GEN_41;
reg [1:0] wakeupCause;
reg [31:0] GEN_42;
wire T_394;
reg [3:0] T_396;
reg [31:0] GEN_43;
wire [3:0] GEN_2;
wire [3:0] ie;
reg [8:0] wakeupProgram_0;
reg [31:0] GEN_44;
reg [8:0] wakeupProgram_1;
reg [31:0] GEN_45;
reg [8:0] wakeupProgram_2;
reg [31:0] GEN_46;
reg [8:0] wakeupProgram_3;
reg [31:0] GEN_47;
reg [8:0] wakeupProgram_4;
reg [31:0] GEN_48;
reg [8:0] wakeupProgram_5;
reg [31:0] GEN_49;
reg [8:0] wakeupProgram_6;
reg [31:0] GEN_50;
reg [8:0] wakeupProgram_7;
reg [31:0] GEN_51;
reg [8:0] sleepProgram_0;
reg [31:0] GEN_52;
reg [8:0] sleepProgram_1;
reg [31:0] GEN_53;
reg [8:0] sleepProgram_2;
reg [31:0] GEN_54;
reg [8:0] sleepProgram_3;
reg [31:0] GEN_55;
reg [8:0] sleepProgram_4;
reg [31:0] GEN_56;
reg [8:0] sleepProgram_5;
reg [31:0] GEN_57;
reg [8:0] sleepProgram_6;
reg [31:0] GEN_58;
reg [8:0] sleepProgram_7;
reg [31:0] GEN_59;
wire [2:0] T_423;
wire T_425;
wire [2:0] T_427;
wire T_429;
wire T_433;
wire [8:0] T_434;
wire [8:0] T_439;
wire [8:0] T_440;
wire [8:0] T_449;
wire [8:0] T_454;
wire [8:0] T_455;
wire [8:0] T_456;
wire [8:0] T_469;
wire [8:0] T_474;
wire [8:0] T_475;
wire [8:0] T_484;
wire [8:0] T_489;
wire [8:0] T_490;
wire [8:0] T_491;
wire [8:0] insnBits;
wire insn_sigs_hfclkrst;
wire insn_sigs_corerst;
wire insn_sigs_reserved1;
wire insn_sigs_vddpaden;
wire insn_sigs_reserved0;
wire [3:0] insn_dt;
wire [3:0] T_515;
wire T_516;
wire T_517;
wire T_518;
wire T_519;
wire T_520;
reg [15:0] count;
reg [31:0] GEN_60;
wire [16:0] T_523;
wire [15:0] T_524;
wire [15:0] T_525;
wire [15:0] T_526;
wire tick;
wire [3:0] npc;
wire last;
wire T_530;
wire T_531;
wire T_532;
wire [15:0] GEN_3;
wire GEN_4;
wire [3:0] GEN_5;
wire [15:0] GEN_6;
wire GEN_7;
wire [3:0] GEN_8;
wire T_540;
wire [1:0] T_541;
wire [1:0] T_542;
wire [3:0] T_543;
wire [3:0] T_544;
wire T_546;
wire T_548;
wire T_549;
wire T_552;
wire T_553;
wire T_554;
wire [1:0] T_560;
wire [1:0] T_561;
wire [1:0] T_562;
wire GEN_9;
wire GEN_10;
wire [1:0] GEN_11;
wire T_563;
wire GEN_12;
wire GEN_13;
wire GEN_14;
wire GEN_15;
wire GEN_16;
wire [1:0] GEN_17;
wire GEN_18;
wire [9:0] GEN_35;
wire [9:0] T_567;
wire [9:0] GEN_36;
wire [9:0] T_568;
wire T_570;
wire [31:0] GEN_19;
wire T_571;
wire [31:0] GEN_20;
wire T_572;
wire [31:0] GEN_21;
wire T_573;
wire [31:0] GEN_22;
wire T_574;
wire [31:0] GEN_23;
wire T_575;
wire [31:0] GEN_24;
wire T_576;
wire [31:0] GEN_25;
wire T_577;
wire [31:0] GEN_26;
wire T_578;
wire [31:0] GEN_27;
wire T_579;
wire [31:0] GEN_28;
wire T_580;
wire [31:0] GEN_29;
wire T_581;
wire [31:0] GEN_30;
wire T_582;
wire [31:0] GEN_31;
wire T_583;
wire [31:0] GEN_32;
wire T_584;
wire [31:0] GEN_33;
wire T_585;
wire [31:0] GEN_34;
assign io_control_valid = T_532;
assign io_control_bits_hfclkrst = insn_sigs_hfclkrst;
assign io_control_bits_corerst = insn_sigs_corerst;
assign io_control_bits_reserved1 = insn_sigs_reserved1;
assign io_control_bits_vddpaden = insn_sigs_vddpaden;
assign io_control_bits_reserved0 = insn_sigs_reserved0;
assign io_regs_ie_read = ie;
assign io_regs_cause_read = {{22'd0}, T_568};
assign io_regs_sleep_read = {31'h0,wantSleep};
assign io_regs_key_read = {{31'd0}, unlocked};
assign io_regs_wakeupProgram_0_read = {{23'd0}, wakeupProgram_0};
assign io_regs_wakeupProgram_1_read = {{23'd0}, wakeupProgram_1};
assign io_regs_wakeupProgram_2_read = {{23'd0}, wakeupProgram_2};
assign io_regs_wakeupProgram_3_read = {{23'd0}, wakeupProgram_3};
assign io_regs_wakeupProgram_4_read = {{23'd0}, wakeupProgram_4};
assign io_regs_wakeupProgram_5_read = {{23'd0}, wakeupProgram_5};
assign io_regs_wakeupProgram_6_read = {{23'd0}, wakeupProgram_6};
assign io_regs_wakeupProgram_7_read = {{23'd0}, wakeupProgram_7};
assign io_regs_sleepProgram_0_read = {{23'd0}, sleepProgram_0};
assign io_regs_sleepProgram_1_read = {{23'd0}, sleepProgram_1};
assign io_regs_sleepProgram_2_read = {{23'd0}, sleepProgram_2};
assign io_regs_sleepProgram_3_read = {{23'd0}, sleepProgram_3};
assign io_regs_sleepProgram_4_read = {{23'd0}, sleepProgram_4};
assign io_regs_sleepProgram_5_read = {{23'd0}, sleepProgram_5};
assign io_regs_sleepProgram_6_read = {{23'd0}, sleepProgram_6};
assign io_regs_sleepProgram_7_read = {{23'd0}, sleepProgram_7};
assign T_364 = io_regs_sleepProgram_0_write_valid | io_regs_sleepProgram_1_write_valid;
assign T_365 = T_364 | io_regs_sleepProgram_2_write_valid;
assign T_366 = T_365 | io_regs_sleepProgram_3_write_valid;
assign T_367 = T_366 | io_regs_sleepProgram_4_write_valid;
assign T_368 = T_367 | io_regs_sleepProgram_5_write_valid;
assign T_369 = T_368 | io_regs_sleepProgram_6_write_valid;
assign T_370 = T_369 | io_regs_sleepProgram_7_write_valid;
assign T_371 = io_regs_wakeupProgram_0_write_valid | io_regs_wakeupProgram_1_write_valid;
assign T_372 = T_371 | io_regs_wakeupProgram_2_write_valid;
assign T_373 = T_372 | io_regs_wakeupProgram_3_write_valid;
assign T_374 = T_373 | io_regs_wakeupProgram_4_write_valid;
assign T_375 = T_374 | io_regs_wakeupProgram_5_write_valid;
assign T_376 = T_375 | io_regs_wakeupProgram_6_write_valid;
assign T_377 = T_376 | io_regs_wakeupProgram_7_write_valid;
assign T_378 = T_370 | T_377;
assign T_379 = T_378 | io_regs_sleep_write_valid;
assign T_380 = T_379 | io_regs_cause_write_valid;
assign T_381 = T_380 | io_regs_ie_write_valid;
assign T_383 = io_regs_key_write_bits == 32'h51f15e;
assign T_385 = T_381 == 1'h0;
assign T_386 = T_383 & T_385;
assign T_388 = io_regs_key_write_valid | T_381;
assign GEN_0 = T_388 ? T_386 : unlocked;
assign T_391 = io_regs_sleep_write_valid & unlocked;
assign GEN_1 = T_391 ? 1'h1 : wantSleep;
assign T_394 = io_regs_ie_write_valid & unlocked;
assign GEN_2 = T_394 ? io_regs_ie_write_bits : T_396;
assign ie = T_396 | 4'h1;
assign T_423 = pc & 3'h3;
assign T_425 = pc >= 3'h4;
assign T_427 = T_423 & 3'h1;
assign T_429 = T_423 >= 3'h2;
assign T_433 = T_427 >= 3'h1;
assign T_434 = T_433 ? wakeupProgram_7 : wakeupProgram_6;
assign T_439 = T_433 ? wakeupProgram_5 : wakeupProgram_4;
assign T_440 = T_429 ? T_434 : T_439;
assign T_449 = T_433 ? wakeupProgram_3 : wakeupProgram_2;
assign T_454 = T_433 ? wakeupProgram_1 : wakeupProgram_0;
assign T_455 = T_429 ? T_449 : T_454;
assign T_456 = T_425 ? T_440 : T_455;
assign T_469 = T_433 ? sleepProgram_7 : sleepProgram_6;
assign T_474 = T_433 ? sleepProgram_5 : sleepProgram_4;
assign T_475 = T_429 ? T_469 : T_474;
assign T_484 = T_433 ? sleepProgram_3 : sleepProgram_2;
assign T_489 = T_433 ? sleepProgram_1 : sleepProgram_0;
assign T_490 = T_429 ? T_484 : T_489;
assign T_491 = T_425 ? T_475 : T_490;
assign insnBits = awake ? T_456 : T_491;
assign insn_sigs_hfclkrst = T_520;
assign insn_sigs_corerst = T_519;
assign insn_sigs_reserved1 = T_518;
assign insn_sigs_vddpaden = T_517;
assign insn_sigs_reserved0 = T_516;
assign insn_dt = T_515;
assign T_515 = insnBits[3:0];
assign T_516 = insnBits[4];
assign T_517 = insnBits[5];
assign T_518 = insnBits[6];
assign T_519 = insnBits[7];
assign T_520 = insnBits[8];
assign T_523 = count + 16'h1;
assign T_524 = T_523[15:0];
assign T_525 = count ^ T_524;
assign T_526 = T_525 >> insn_dt;
assign tick = T_526[0];
assign npc = pc + 3'h1;
assign last = npc >= 4'h8;
assign T_530 = last == 1'h0;
assign T_531 = run & T_530;
assign T_532 = T_531 & tick;
assign GEN_3 = tick ? 16'h0 : T_524;
assign GEN_4 = tick ? T_530 : run;
assign GEN_5 = tick ? npc : {{1'd0}, pc};
assign GEN_6 = run ? GEN_3 : count;
assign GEN_7 = run ? GEN_4 : run;
assign GEN_8 = run ? GEN_5 : {{1'd0}, pc};
assign T_540 = run == 1'h0;
assign T_541 = {io_wakeup_rtc,io_wakeup_reset};
assign T_542 = {io_wakeup_awakeup,io_wakeup_dwakeup};
assign T_543 = {T_542,T_541};
assign T_544 = ie & T_543;
assign T_546 = awake == 1'h0;
assign T_548 = T_544 != 4'h0;
assign T_549 = T_546 & T_548;
assign T_552 = T_544[0];
assign T_553 = T_544[1];
assign T_554 = T_544[2];
assign T_560 = T_554 ? 2'h2 : 2'h3;
assign T_561 = T_553 ? 2'h1 : T_560;
assign T_562 = T_552 ? 2'h0 : T_561;
assign GEN_9 = T_549 ? 1'h1 : GEN_7;
assign GEN_10 = T_549 ? 1'h1 : awake;
assign GEN_11 = T_549 ? T_562 : wakeupCause;
//Bob: here we introduce a core_wfi signal to make sure when the PMU is
// going to power down MOFF, the core is really idle (executed wfi)
//assign T_563 = awake & wantSleep & core_wfi;
assign T_563 = awake & wantSleep;// Current we dont add it
assign GEN_12 = T_563 ? 1'h1 : GEN_9;
assign GEN_13 = T_563 ? 1'h0 : GEN_10;
assign GEN_14 = T_563 ? 1'h0 : GEN_1;
assign GEN_15 = T_540 ? GEN_12 : GEN_7;
assign GEN_16 = T_540 ? GEN_13 : awake;
assign GEN_17 = T_540 ? GEN_11 : wakeupCause;
assign GEN_18 = T_540 ? GEN_14 : GEN_1;
assign GEN_35 = {{8'd0}, io_resetCause};
assign T_567 = GEN_35 << 8;
assign GEN_36 = {{8'd0}, wakeupCause};
assign T_568 = GEN_36 | T_567;
assign T_570 = io_regs_wakeupProgram_0_write_valid & unlocked;
assign GEN_19 = T_570 ? io_regs_wakeupProgram_0_write_bits : {{23'd0}, wakeupProgram_0};
assign T_571 = io_regs_wakeupProgram_1_write_valid & unlocked;
assign GEN_20 = T_571 ? io_regs_wakeupProgram_1_write_bits : {{23'd0}, wakeupProgram_1};
assign T_572 = io_regs_wakeupProgram_2_write_valid & unlocked;
assign GEN_21 = T_572 ? io_regs_wakeupProgram_2_write_bits : {{23'd0}, wakeupProgram_2};
assign T_573 = io_regs_wakeupProgram_3_write_valid & unlocked;
assign GEN_22 = T_573 ? io_regs_wakeupProgram_3_write_bits : {{23'd0}, wakeupProgram_3};
assign T_574 = io_regs_wakeupProgram_4_write_valid & unlocked;
assign GEN_23 = T_574 ? io_regs_wakeupProgram_4_write_bits : {{23'd0}, wakeupProgram_4};
assign T_575 = io_regs_wakeupProgram_5_write_valid & unlocked;
assign GEN_24 = T_575 ? io_regs_wakeupProgram_5_write_bits : {{23'd0}, wakeupProgram_5};
assign T_576 = io_regs_wakeupProgram_6_write_valid & unlocked;
assign GEN_25 = T_576 ? io_regs_wakeupProgram_6_write_bits : {{23'd0}, wakeupProgram_6};
assign T_577 = io_regs_wakeupProgram_7_write_valid & unlocked;
assign GEN_26 = T_577 ? io_regs_wakeupProgram_7_write_bits : {{23'd0}, wakeupProgram_7};
assign T_578 = io_regs_sleepProgram_0_write_valid & unlocked;
assign GEN_27 = T_578 ? io_regs_sleepProgram_0_write_bits : {{23'd0}, sleepProgram_0};
assign T_579 = io_regs_sleepProgram_1_write_valid & unlocked;
assign GEN_28 = T_579 ? io_regs_sleepProgram_1_write_bits : {{23'd0}, sleepProgram_1};
assign T_580 = io_regs_sleepProgram_2_write_valid & unlocked;
assign GEN_29 = T_580 ? io_regs_sleepProgram_2_write_bits : {{23'd0}, sleepProgram_2};
assign T_581 = io_regs_sleepProgram_3_write_valid & unlocked;
assign GEN_30 = T_581 ? io_regs_sleepProgram_3_write_bits : {{23'd0}, sleepProgram_3};
assign T_582 = io_regs_sleepProgram_4_write_valid & unlocked;
assign GEN_31 = T_582 ? io_regs_sleepProgram_4_write_bits : {{23'd0}, sleepProgram_4};
assign T_583 = io_regs_sleepProgram_5_write_valid & unlocked;
assign GEN_32 = T_583 ? io_regs_sleepProgram_5_write_bits : {{23'd0}, sleepProgram_5};
assign T_584 = io_regs_sleepProgram_6_write_valid & unlocked;
assign GEN_33 = T_584 ? io_regs_sleepProgram_6_write_bits : {{23'd0}, sleepProgram_6};
assign T_585 = io_regs_sleepProgram_7_write_valid & unlocked;
assign GEN_34 = T_585 ? io_regs_sleepProgram_7_write_bits : {{23'd0}, sleepProgram_7};
always @(posedge clock or posedge reset)
if (reset) begin
run <= 1'h1;
end else begin
if (T_540) begin
if (T_563) begin
run <= 1'h1;
end else begin
if (T_549) begin
run <= 1'h1;
end else begin
if (run) begin
if (tick) begin
run <= T_530;
end
end
end
end
end else begin
if (run) begin
if (tick) begin
run <= T_530;
end
end
end
end
always @(posedge clock or posedge reset)
if (reset) begin
awake <= 1'h1;
end else begin
if (T_540) begin
if (T_563) begin
awake <= 1'h0;
end else begin
if (T_549) begin
awake <= 1'h1;
end
end
end
end
always @(posedge clock or posedge reset)
if (reset) begin
unlocked <= 1'h0;
end else begin
if (T_388) begin
unlocked <= T_386;
end
end
always @(posedge clock or posedge reset)
if (reset) begin
wantSleep <= 1'h0;
end else begin
if (T_540) begin
if (T_563) begin
wantSleep <= 1'h0;
end else begin
if (T_391) begin
wantSleep <= io_regs_sleep_write_bits[0];
end
end
end else begin
if (T_391) begin
wantSleep <= io_regs_sleep_write_bits[0];
end
end
end
always @(posedge clock or posedge reset)
if (reset) begin
pc <= 3'h0;
end else begin
pc <= GEN_8[2:0];
end
always @(posedge clock or posedge reset)
if (reset) begin
wakeupCause <= 2'h0;
end else begin
if (T_540) begin
if (T_549) begin
if (T_552) begin
wakeupCause <= 2'h0;
end else begin
if (T_553) begin
wakeupCause <= 2'h1;
end else begin
if (T_554) begin
wakeupCause <= 2'h2;
end else begin
wakeupCause <= 2'h3;
end
end
end
end
end
end
always @(posedge clock or posedge reset)
if (reset) begin
T_396 <= 4'b0;
end
else if (T_394) begin
T_396 <= io_regs_ie_write_bits;
end
always @(posedge clock or posedge reset)
if (reset) begin
wakeupProgram_0 <= 9'h1f0;
end else begin
wakeupProgram_0 <= GEN_19[8:0];
end
always @(posedge clock or posedge reset)
if (reset) begin
wakeupProgram_1 <= 9'hf8;
end else begin
wakeupProgram_1 <= GEN_20[8:0];
end
always @(posedge clock or posedge reset)
if (reset) begin
wakeupProgram_2 <= 9'h30;
end else begin
wakeupProgram_2 <= GEN_21[8:0];
end
always @(posedge clock or posedge reset)
if (reset) begin
wakeupProgram_3 <= 9'h30;
end else begin
wakeupProgram_3 <= GEN_22[8:0];
end
always @(posedge clock or posedge reset)
if (reset) begin
wakeupProgram_4 <= 9'h30;
end else begin
wakeupProgram_4 <= GEN_23[8:0];
end
always @(posedge clock or posedge reset)
if (reset) begin
wakeupProgram_5 <= 9'h30;
end else begin
wakeupProgram_5 <= GEN_24[8:0];
end
always @(posedge clock or posedge reset)
if (reset) begin
wakeupProgram_6 <= 9'h30;
end else begin
wakeupProgram_6 <= GEN_25[8:0];
end
always @(posedge clock or posedge reset)
if (reset) begin
wakeupProgram_7 <= 9'h30;
end else begin
wakeupProgram_7 <= GEN_26[8:0];
end
always @(posedge clock or posedge reset)
if (reset) begin
sleepProgram_0 <= 9'hf0;
end else begin
sleepProgram_0 <= GEN_27[8:0];
end
always @(posedge clock or posedge reset)
if (reset) begin
sleepProgram_1 <= 9'h1f0;
end else begin
sleepProgram_1 <= GEN_28[8:0];
end
always @(posedge clock or posedge reset)
if (reset) begin
sleepProgram_2 <= 9'h1d0;
end else begin
sleepProgram_2 <= GEN_29[8:0];
end
always @(posedge clock or posedge reset)
if (reset) begin
sleepProgram_3 <= 9'h1c0;
end else begin
sleepProgram_3 <= GEN_30[8:0];
end
always @(posedge clock or posedge reset)
if (reset) begin
sleepProgram_4 <= 9'h1c0;
end else begin
sleepProgram_4 <= GEN_31[8:0];
end
always @(posedge clock or posedge reset)
if (reset) begin
sleepProgram_5 <= 9'h1c0;
end else begin
sleepProgram_5 <= GEN_32[8:0];
end
always @(posedge clock or posedge reset)
if (reset) begin
sleepProgram_6 <= 9'h1c0;
end else begin
sleepProgram_6 <= GEN_33[8:0];
end
always @(posedge clock or posedge reset)
if (reset) begin
sleepProgram_7 <= 9'h1c0;
end else begin
sleepProgram_7 <= GEN_34[8:0];
end
always @(posedge clock or posedge reset)
if (reset) begin
count <= 16'h0;
end else begin
if (run) begin
if (tick) begin
count <= 16'h0;
end else begin
count <= T_524;
end
end
end
endmodule
|
module e203_itcm_ram(
input sd,
input ds,
input ls,
input cs,
input we,
input [`E203_ITCM_RAM_AW-1:0] addr,
input [`E203_ITCM_RAM_MW-1:0] wem,
input [`E203_ITCM_RAM_DW-1:0] din,
output [`E203_ITCM_RAM_DW-1:0] dout,
input rst_n,
input clk
);
wire wren = we & cs;
wire [7:0]wea;
assign wea = (wren) ? wem : 8'b0;
wire rden;
assign rden = (~we) & cs;
// bram u_e203_itcm_gnrl_ram(
//
// .doa (dout),
// .dia (din ),
// .addra (addr),
// .wea (wea ),
// .cea (cs ),
// .clka (clk ),
// .rsta (1'b0),
//
// .dob (),
// .dib (`E203_ITCM_RAM_DW'b0),
// .addrb (13'b0),
// .web (8'b0),
// .ceb (1'b0),
// .clkb (1'b0),
// .rstb (1'b0)
// );
riscv_ram64 u_e203_itcm_gnrl_ram
(
.address(addr),
.byteena(wea),
.clock (clk),
.data (din),
.rden (rden),
.wren (wren),
.q (dout)
);
// sirv_gnrl_ram #(
// `ifndef E203_HAS_ECC//{
// .FORCE_X2ZERO(0),
// `endif//}
// .DP(`E203_ITCM_RAM_DP),
// .DW(`E203_ITCM_RAM_DW),
// .MW(`E203_ITCM_RAM_MW),
// .AW(`E203_ITCM_RAM_AW)
// ) u_e203_itcm_gnrl_ram(
// .sd (sd ),
// .ds (ds ),
// .ls (ls ),
//
// .rst_n (rst_n ),
// .clk (clk ),
// .cs (cs ),
// .we (we ),
// .addr(addr),
// .din (din ),
// .wem (wem ),
// .dout(dout)
// );
endmodule
|
module sirv_spigpioport_1(
input clock,
input reset,
input io_spi_sck,
output io_spi_dq_0_i,
input io_spi_dq_0_o,
input io_spi_dq_0_oe,
output io_spi_dq_1_i,
input io_spi_dq_1_o,
input io_spi_dq_1_oe,
output io_spi_dq_2_i,
input io_spi_dq_2_o,
input io_spi_dq_2_oe,
output io_spi_dq_3_i,
input io_spi_dq_3_o,
input io_spi_dq_3_oe,
input io_spi_cs_0,
input io_pins_sck_i_ival,
output io_pins_sck_o_oval,
output io_pins_sck_o_oe,
output io_pins_sck_o_ie,
output io_pins_sck_o_pue,
output io_pins_sck_o_ds,
input io_pins_dq_0_i_ival,
output io_pins_dq_0_o_oval,
output io_pins_dq_0_o_oe,
output io_pins_dq_0_o_ie,
output io_pins_dq_0_o_pue,
output io_pins_dq_0_o_ds,
input io_pins_dq_1_i_ival,
output io_pins_dq_1_o_oval,
output io_pins_dq_1_o_oe,
output io_pins_dq_1_o_ie,
output io_pins_dq_1_o_pue,
output io_pins_dq_1_o_ds,
input io_pins_dq_2_i_ival,
output io_pins_dq_2_o_oval,
output io_pins_dq_2_o_oe,
output io_pins_dq_2_o_ie,
output io_pins_dq_2_o_pue,
output io_pins_dq_2_o_ds,
input io_pins_dq_3_i_ival,
output io_pins_dq_3_o_oval,
output io_pins_dq_3_o_oe,
output io_pins_dq_3_o_ie,
output io_pins_dq_3_o_pue,
output io_pins_dq_3_o_ds,
input io_pins_cs_0_i_ival,
output io_pins_cs_0_o_oval,
output io_pins_cs_0_o_oe,
output io_pins_cs_0_o_ie,
output io_pins_cs_0_o_pue,
output io_pins_cs_0_o_ds
);
wire T_267;
wire T_270;
wire T_273;
wire T_276;
assign io_spi_dq_0_i = io_pins_dq_0_i_ival;
assign io_spi_dq_1_i = io_pins_dq_1_i_ival;
assign io_spi_dq_2_i = io_pins_dq_2_i_ival;
assign io_spi_dq_3_i = io_pins_dq_3_i_ival;
assign io_pins_sck_o_oval = io_spi_sck;
assign io_pins_sck_o_oe = 1'h1;
assign io_pins_sck_o_ie = 1'h0;
assign io_pins_sck_o_pue = 1'h0;
assign io_pins_sck_o_ds = 1'h0;
assign io_pins_dq_0_o_oval = io_spi_dq_0_o;
assign io_pins_dq_0_o_oe = io_spi_dq_0_oe;
assign io_pins_dq_0_o_ie = T_267;
assign io_pins_dq_0_o_pue = 1'h1;
assign io_pins_dq_0_o_ds = 1'h0;
assign io_pins_dq_1_o_oval = io_spi_dq_1_o;
assign io_pins_dq_1_o_oe = io_spi_dq_1_oe;
assign io_pins_dq_1_o_ie = T_270;
assign io_pins_dq_1_o_pue = 1'h1;
assign io_pins_dq_1_o_ds = 1'h0;
assign io_pins_dq_2_o_oval = io_spi_dq_2_o;
assign io_pins_dq_2_o_oe = io_spi_dq_2_oe;
assign io_pins_dq_2_o_ie = T_273;
assign io_pins_dq_2_o_pue = 1'h1;
assign io_pins_dq_2_o_ds = 1'h0;
assign io_pins_dq_3_o_oval = io_spi_dq_3_o;
assign io_pins_dq_3_o_oe = io_spi_dq_3_oe;
assign io_pins_dq_3_o_ie = T_276;
assign io_pins_dq_3_o_pue = 1'h1;
assign io_pins_dq_3_o_ds = 1'h0;
assign io_pins_cs_0_o_oval = io_spi_cs_0;
assign io_pins_cs_0_o_oe = 1'h1;
assign io_pins_cs_0_o_ie = 1'h0;
assign io_pins_cs_0_o_pue = 1'h0;
assign io_pins_cs_0_o_ds = 1'h0;
assign T_267 = ~ io_spi_dq_0_oe;
assign T_270 = ~ io_spi_dq_1_oe;
assign T_273 = ~ io_spi_dq_2_oe;
assign T_276 = ~ io_spi_dq_3_oe;
endmodule
|
module sirv_AsyncResetRegVec_67(
input clock,
input reset,
input [31:0] io_d,
output [31:0] io_q,
input io_en
);
wire reg_0_rst;
wire reg_0_clk;
wire reg_0_en;
wire reg_0_q;
wire reg_0_d;
wire reg_1_rst;
wire reg_1_clk;
wire reg_1_en;
wire reg_1_q;
wire reg_1_d;
wire reg_2_rst;
wire reg_2_clk;
wire reg_2_en;
wire reg_2_q;
wire reg_2_d;
wire reg_3_rst;
wire reg_3_clk;
wire reg_3_en;
wire reg_3_q;
wire reg_3_d;
wire reg_4_rst;
wire reg_4_clk;
wire reg_4_en;
wire reg_4_q;
wire reg_4_d;
wire reg_5_rst;
wire reg_5_clk;
wire reg_5_en;
wire reg_5_q;
wire reg_5_d;
wire reg_6_rst;
wire reg_6_clk;
wire reg_6_en;
wire reg_6_q;
wire reg_6_d;
wire reg_7_rst;
wire reg_7_clk;
wire reg_7_en;
wire reg_7_q;
wire reg_7_d;
wire reg_8_rst;
wire reg_8_clk;
wire reg_8_en;
wire reg_8_q;
wire reg_8_d;
wire reg_9_rst;
wire reg_9_clk;
wire reg_9_en;
wire reg_9_q;
wire reg_9_d;
wire reg_10_rst;
wire reg_10_clk;
wire reg_10_en;
wire reg_10_q;
wire reg_10_d;
wire reg_11_rst;
wire reg_11_clk;
wire reg_11_en;
wire reg_11_q;
wire reg_11_d;
wire reg_12_rst;
wire reg_12_clk;
wire reg_12_en;
wire reg_12_q;
wire reg_12_d;
wire reg_13_rst;
wire reg_13_clk;
wire reg_13_en;
wire reg_13_q;
wire reg_13_d;
wire reg_14_rst;
wire reg_14_clk;
wire reg_14_en;
wire reg_14_q;
wire reg_14_d;
wire reg_15_rst;
wire reg_15_clk;
wire reg_15_en;
wire reg_15_q;
wire reg_15_d;
wire reg_16_rst;
wire reg_16_clk;
wire reg_16_en;
wire reg_16_q;
wire reg_16_d;
wire reg_17_rst;
wire reg_17_clk;
wire reg_17_en;
wire reg_17_q;
wire reg_17_d;
wire reg_18_rst;
wire reg_18_clk;
wire reg_18_en;
wire reg_18_q;
wire reg_18_d;
wire reg_19_rst;
wire reg_19_clk;
wire reg_19_en;
wire reg_19_q;
wire reg_19_d;
wire reg_20_rst;
wire reg_20_clk;
wire reg_20_en;
wire reg_20_q;
wire reg_20_d;
wire reg_21_rst;
wire reg_21_clk;
wire reg_21_en;
wire reg_21_q;
wire reg_21_d;
wire reg_22_rst;
wire reg_22_clk;
wire reg_22_en;
wire reg_22_q;
wire reg_22_d;
wire reg_23_rst;
wire reg_23_clk;
wire reg_23_en;
wire reg_23_q;
wire reg_23_d;
wire reg_24_rst;
wire reg_24_clk;
wire reg_24_en;
wire reg_24_q;
wire reg_24_d;
wire reg_25_rst;
wire reg_25_clk;
wire reg_25_en;
wire reg_25_q;
wire reg_25_d;
wire reg_26_rst;
wire reg_26_clk;
wire reg_26_en;
wire reg_26_q;
wire reg_26_d;
wire reg_27_rst;
wire reg_27_clk;
wire reg_27_en;
wire reg_27_q;
wire reg_27_d;
wire reg_28_rst;
wire reg_28_clk;
wire reg_28_en;
wire reg_28_q;
wire reg_28_d;
wire reg_29_rst;
wire reg_29_clk;
wire reg_29_en;
wire reg_29_q;
wire reg_29_d;
wire reg_30_rst;
wire reg_30_clk;
wire reg_30_en;
wire reg_30_q;
wire reg_30_d;
wire reg_31_rst;
wire reg_31_clk;
wire reg_31_en;
wire reg_31_q;
wire reg_31_d;
wire T_8;
wire T_9;
wire T_10;
wire T_11;
wire T_12;
wire T_13;
wire T_14;
wire T_15;
wire T_16;
wire T_17;
wire T_18;
wire T_19;
wire T_20;
wire T_21;
wire T_22;
wire T_23;
wire T_24;
wire T_25;
wire T_26;
wire T_27;
wire T_28;
wire T_29;
wire T_30;
wire T_31;
wire T_32;
wire T_33;
wire T_34;
wire T_35;
wire T_36;
wire T_37;
wire T_38;
wire T_39;
wire [1:0] T_40;
wire [1:0] T_41;
wire [3:0] T_42;
wire [1:0] T_43;
wire [1:0] T_44;
wire [3:0] T_45;
wire [7:0] T_46;
wire [1:0] T_47;
wire [1:0] T_48;
wire [3:0] T_49;
wire [1:0] T_50;
wire [1:0] T_51;
wire [3:0] T_52;
wire [7:0] T_53;
wire [15:0] T_54;
wire [1:0] T_55;
wire [1:0] T_56;
wire [3:0] T_57;
wire [1:0] T_58;
wire [1:0] T_59;
wire [3:0] T_60;
wire [7:0] T_61;
wire [1:0] T_62;
wire [1:0] T_63;
wire [3:0] T_64;
wire [1:0] T_65;
wire [1:0] T_66;
wire [3:0] T_67;
wire [7:0] T_68;
wire [15:0] T_69;
wire [31:0] T_70;
sirv_AsyncResetReg u_reg_0 (
.rst(reg_0_rst),
.clk(reg_0_clk),
.en(reg_0_en),
.q(reg_0_q),
.d(reg_0_d)
);
sirv_AsyncResetReg u_reg_1 (
.rst(reg_1_rst),
.clk(reg_1_clk),
.en(reg_1_en),
.q(reg_1_q),
.d(reg_1_d)
);
sirv_AsyncResetReg u_reg_2 (
.rst(reg_2_rst),
.clk(reg_2_clk),
.en(reg_2_en),
.q(reg_2_q),
.d(reg_2_d)
);
sirv_AsyncResetReg u_reg_3 (
.rst(reg_3_rst),
.clk(reg_3_clk),
.en(reg_3_en),
.q(reg_3_q),
.d(reg_3_d)
);
sirv_AsyncResetReg u_reg_4 (
.rst(reg_4_rst),
.clk(reg_4_clk),
.en(reg_4_en),
.q(reg_4_q),
.d(reg_4_d)
);
sirv_AsyncResetReg u_reg_5 (
.rst(reg_5_rst),
.clk(reg_5_clk),
.en(reg_5_en),
.q(reg_5_q),
.d(reg_5_d)
);
sirv_AsyncResetReg u_reg_6 (
.rst(reg_6_rst),
.clk(reg_6_clk),
.en(reg_6_en),
.q(reg_6_q),
.d(reg_6_d)
);
sirv_AsyncResetReg u_reg_7 (
.rst(reg_7_rst),
.clk(reg_7_clk),
.en(reg_7_en),
.q(reg_7_q),
.d(reg_7_d)
);
sirv_AsyncResetReg u_reg_8 (
.rst(reg_8_rst),
.clk(reg_8_clk),
.en(reg_8_en),
.q(reg_8_q),
.d(reg_8_d)
);
sirv_AsyncResetReg u_reg_9 (
.rst(reg_9_rst),
.clk(reg_9_clk),
.en(reg_9_en),
.q(reg_9_q),
.d(reg_9_d)
);
sirv_AsyncResetReg u_reg_10 (
.rst(reg_10_rst),
.clk(reg_10_clk),
.en(reg_10_en),
.q(reg_10_q),
.d(reg_10_d)
);
sirv_AsyncResetReg u_reg_11 (
.rst(reg_11_rst),
.clk(reg_11_clk),
.en(reg_11_en),
.q(reg_11_q),
.d(reg_11_d)
);
sirv_AsyncResetReg u_reg_12 (
.rst(reg_12_rst),
.clk(reg_12_clk),
.en(reg_12_en),
.q(reg_12_q),
.d(reg_12_d)
);
sirv_AsyncResetReg u_reg_13 (
.rst(reg_13_rst),
.clk(reg_13_clk),
.en(reg_13_en),
.q(reg_13_q),
.d(reg_13_d)
);
sirv_AsyncResetReg u_reg_14 (
.rst(reg_14_rst),
.clk(reg_14_clk),
.en(reg_14_en),
.q(reg_14_q),
.d(reg_14_d)
);
sirv_AsyncResetReg u_reg_15 (
.rst(reg_15_rst),
.clk(reg_15_clk),
.en(reg_15_en),
.q(reg_15_q),
.d(reg_15_d)
);
sirv_AsyncResetReg u_reg_16 (
.rst(reg_16_rst),
.clk(reg_16_clk),
.en(reg_16_en),
.q(reg_16_q),
.d(reg_16_d)
);
sirv_AsyncResetReg u_reg_17 (
.rst(reg_17_rst),
.clk(reg_17_clk),
.en(reg_17_en),
.q(reg_17_q),
.d(reg_17_d)
);
sirv_AsyncResetReg u_reg_18 (
.rst(reg_18_rst),
.clk(reg_18_clk),
.en(reg_18_en),
.q(reg_18_q),
.d(reg_18_d)
);
sirv_AsyncResetReg u_reg_19 (
.rst(reg_19_rst),
.clk(reg_19_clk),
.en(reg_19_en),
.q(reg_19_q),
.d(reg_19_d)
);
sirv_AsyncResetReg u_reg_20 (
.rst(reg_20_rst),
.clk(reg_20_clk),
.en(reg_20_en),
.q(reg_20_q),
.d(reg_20_d)
);
sirv_AsyncResetReg u_reg_21 (
.rst(reg_21_rst),
.clk(reg_21_clk),
.en(reg_21_en),
.q(reg_21_q),
.d(reg_21_d)
);
sirv_AsyncResetReg u_reg_22 (
.rst(reg_22_rst),
.clk(reg_22_clk),
.en(reg_22_en),
.q(reg_22_q),
.d(reg_22_d)
);
sirv_AsyncResetReg u_reg_23 (
.rst(reg_23_rst),
.clk(reg_23_clk),
.en(reg_23_en),
.q(reg_23_q),
.d(reg_23_d)
);
sirv_AsyncResetReg u_reg_24 (
.rst(reg_24_rst),
.clk(reg_24_clk),
.en(reg_24_en),
.q(reg_24_q),
.d(reg_24_d)
);
sirv_AsyncResetReg u_reg_25 (
.rst(reg_25_rst),
.clk(reg_25_clk),
.en(reg_25_en),
.q(reg_25_q),
.d(reg_25_d)
);
sirv_AsyncResetReg u_reg_26 (
.rst(reg_26_rst),
.clk(reg_26_clk),
.en(reg_26_en),
.q(reg_26_q),
.d(reg_26_d)
);
sirv_AsyncResetReg u_reg_27 (
.rst(reg_27_rst),
.clk(reg_27_clk),
.en(reg_27_en),
.q(reg_27_q),
.d(reg_27_d)
);
sirv_AsyncResetReg u_reg_28 (
.rst(reg_28_rst),
.clk(reg_28_clk),
.en(reg_28_en),
.q(reg_28_q),
.d(reg_28_d)
);
sirv_AsyncResetReg u_reg_29 (
.rst(reg_29_rst),
.clk(reg_29_clk),
.en(reg_29_en),
.q(reg_29_q),
.d(reg_29_d)
);
sirv_AsyncResetReg u_reg_30 (
.rst(reg_30_rst),
.clk(reg_30_clk),
.en(reg_30_en),
.q(reg_30_q),
.d(reg_30_d)
);
sirv_AsyncResetReg u_reg_31 (
.rst(reg_31_rst),
.clk(reg_31_clk),
.en(reg_31_en),
.q(reg_31_q),
.d(reg_31_d)
);
assign io_q = T_70;
assign reg_0_rst = reset;
assign reg_0_clk = clock;
assign reg_0_en = io_en;
assign reg_0_d = T_8;
assign reg_1_rst = reset;
assign reg_1_clk = clock;
assign reg_1_en = io_en;
assign reg_1_d = T_9;
assign reg_2_rst = reset;
assign reg_2_clk = clock;
assign reg_2_en = io_en;
assign reg_2_d = T_10;
assign reg_3_rst = reset;
assign reg_3_clk = clock;
assign reg_3_en = io_en;
assign reg_3_d = T_11;
assign reg_4_rst = reset;
assign reg_4_clk = clock;
assign reg_4_en = io_en;
assign reg_4_d = T_12;
assign reg_5_rst = reset;
assign reg_5_clk = clock;
assign reg_5_en = io_en;
assign reg_5_d = T_13;
assign reg_6_rst = reset;
assign reg_6_clk = clock;
assign reg_6_en = io_en;
assign reg_6_d = T_14;
assign reg_7_rst = reset;
assign reg_7_clk = clock;
assign reg_7_en = io_en;
assign reg_7_d = T_15;
assign reg_8_rst = reset;
assign reg_8_clk = clock;
assign reg_8_en = io_en;
assign reg_8_d = T_16;
assign reg_9_rst = reset;
assign reg_9_clk = clock;
assign reg_9_en = io_en;
assign reg_9_d = T_17;
assign reg_10_rst = reset;
assign reg_10_clk = clock;
assign reg_10_en = io_en;
assign reg_10_d = T_18;
assign reg_11_rst = reset;
assign reg_11_clk = clock;
assign reg_11_en = io_en;
assign reg_11_d = T_19;
assign reg_12_rst = reset;
assign reg_12_clk = clock;
assign reg_12_en = io_en;
assign reg_12_d = T_20;
assign reg_13_rst = reset;
assign reg_13_clk = clock;
assign reg_13_en = io_en;
assign reg_13_d = T_21;
assign reg_14_rst = reset;
assign reg_14_clk = clock;
assign reg_14_en = io_en;
assign reg_14_d = T_22;
assign reg_15_rst = reset;
assign reg_15_clk = clock;
assign reg_15_en = io_en;
assign reg_15_d = T_23;
assign reg_16_rst = reset;
assign reg_16_clk = clock;
assign reg_16_en = io_en;
assign reg_16_d = T_24;
assign reg_17_rst = reset;
assign reg_17_clk = clock;
assign reg_17_en = io_en;
assign reg_17_d = T_25;
assign reg_18_rst = reset;
assign reg_18_clk = clock;
assign reg_18_en = io_en;
assign reg_18_d = T_26;
assign reg_19_rst = reset;
assign reg_19_clk = clock;
assign reg_19_en = io_en;
assign reg_19_d = T_27;
assign reg_20_rst = reset;
assign reg_20_clk = clock;
assign reg_20_en = io_en;
assign reg_20_d = T_28;
assign reg_21_rst = reset;
assign reg_21_clk = clock;
assign reg_21_en = io_en;
assign reg_21_d = T_29;
assign reg_22_rst = reset;
assign reg_22_clk = clock;
assign reg_22_en = io_en;
assign reg_22_d = T_30;
assign reg_23_rst = reset;
assign reg_23_clk = clock;
assign reg_23_en = io_en;
assign reg_23_d = T_31;
assign reg_24_rst = reset;
assign reg_24_clk = clock;
assign reg_24_en = io_en;
assign reg_24_d = T_32;
assign reg_25_rst = reset;
assign reg_25_clk = clock;
assign reg_25_en = io_en;
assign reg_25_d = T_33;
assign reg_26_rst = reset;
assign reg_26_clk = clock;
assign reg_26_en = io_en;
assign reg_26_d = T_34;
assign reg_27_rst = reset;
assign reg_27_clk = clock;
assign reg_27_en = io_en;
assign reg_27_d = T_35;
assign reg_28_rst = reset;
assign reg_28_clk = clock;
assign reg_28_en = io_en;
assign reg_28_d = T_36;
assign reg_29_rst = reset;
assign reg_29_clk = clock;
assign reg_29_en = io_en;
assign reg_29_d = T_37;
assign reg_30_rst = reset;
assign reg_30_clk = clock;
assign reg_30_en = io_en;
assign reg_30_d = T_38;
assign reg_31_rst = reset;
assign reg_31_clk = clock;
assign reg_31_en = io_en;
assign reg_31_d = T_39;
assign T_8 = io_d[0];
assign T_9 = io_d[1];
assign T_10 = io_d[2];
assign T_11 = io_d[3];
assign T_12 = io_d[4];
assign T_13 = io_d[5];
assign T_14 = io_d[6];
assign T_15 = io_d[7];
assign T_16 = io_d[8];
assign T_17 = io_d[9];
assign T_18 = io_d[10];
assign T_19 = io_d[11];
assign T_20 = io_d[12];
assign T_21 = io_d[13];
assign T_22 = io_d[14];
assign T_23 = io_d[15];
assign T_24 = io_d[16];
assign T_25 = io_d[17];
assign T_26 = io_d[18];
assign T_27 = io_d[19];
assign T_28 = io_d[20];
assign T_29 = io_d[21];
assign T_30 = io_d[22];
assign T_31 = io_d[23];
assign T_32 = io_d[24];
assign T_33 = io_d[25];
assign T_34 = io_d[26];
assign T_35 = io_d[27];
assign T_36 = io_d[28];
assign T_37 = io_d[29];
assign T_38 = io_d[30];
assign T_39 = io_d[31];
assign T_40 = {reg_1_q,reg_0_q};
assign T_41 = {reg_3_q,reg_2_q};
assign T_42 = {T_41,T_40};
assign T_43 = {reg_5_q,reg_4_q};
assign T_44 = {reg_7_q,reg_6_q};
assign T_45 = {T_44,T_43};
assign T_46 = {T_45,T_42};
assign T_47 = {reg_9_q,reg_8_q};
assign T_48 = {reg_11_q,reg_10_q};
assign T_49 = {T_48,T_47};
assign T_50 = {reg_13_q,reg_12_q};
assign T_51 = {reg_15_q,reg_14_q};
assign T_52 = {T_51,T_50};
assign T_53 = {T_52,T_49};
assign T_54 = {T_53,T_46};
assign T_55 = {reg_17_q,reg_16_q};
assign T_56 = {reg_19_q,reg_18_q};
assign T_57 = {T_56,T_55};
assign T_58 = {reg_21_q,reg_20_q};
assign T_59 = {reg_23_q,reg_22_q};
assign T_60 = {T_59,T_58};
assign T_61 = {T_60,T_57};
assign T_62 = {reg_25_q,reg_24_q};
assign T_63 = {reg_27_q,reg_26_q};
assign T_64 = {T_63,T_62};
assign T_65 = {reg_29_q,reg_28_q};
assign T_66 = {reg_31_q,reg_30_q};
assign T_67 = {T_66,T_65};
assign T_68 = {T_67,T_64};
assign T_69 = {T_68,T_61};
assign T_70 = {T_69,T_54};
endmodule
|
module sirv_expl_apb_slv #(
parameter AW = 32,
parameter DW = 32
)(
input [AW-1:0] apb_paddr,
input apb_pwrite,
input apb_pselx,
input apb_penable,
input [DW-1:0] apb_pwdata,
output [DW-1:0] apb_prdata,
input clk,
input rst_n
);
assign apb_prdata = {DW{1'b0}};
endmodule
|
module e203_ifu(
output[`E203_PC_SIZE-1:0] inspect_pc,
output ifu_active,
input itcm_nohold,
input [`E203_PC_SIZE-1:0] pc_rtvec,
`ifdef E203_HAS_ITCM //{
input ifu2itcm_holdup,
//input ifu2itcm_replay,
// The ITCM address region indication signal
input [`E203_ADDR_SIZE-1:0] itcm_region_indic,
//////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////
// Bus Interface to ITCM, internal protocol called ICB (Internal Chip Bus)
// * Bus cmd channel
output ifu2itcm_icb_cmd_valid, // Handshake valid
input ifu2itcm_icb_cmd_ready, // Handshake ready
// Note: The data on rdata or wdata channel must be naturally
// aligned, this is in line with the AXI definition
output [`E203_ITCM_ADDR_WIDTH-1:0] ifu2itcm_icb_cmd_addr, // Bus transaction start addr
// * Bus RSP channel
input ifu2itcm_icb_rsp_valid, // Response valid
output ifu2itcm_icb_rsp_ready, // Response ready
input ifu2itcm_icb_rsp_err, // Response error
// Note: the RSP rdata is inline with AXI definition
input [`E203_ITCM_DATA_WIDTH-1:0] ifu2itcm_icb_rsp_rdata,
`endif//}
`ifdef E203_HAS_MEM_ITF //{
//////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////
// Bus Interface to System Memory, internal protocol called ICB (Internal Chip Bus)
// * Bus cmd channel
output ifu2biu_icb_cmd_valid, // Handshake valid
input ifu2biu_icb_cmd_ready, // Handshake ready
// Note: The data on rdata or wdata channel must be naturally
// aligned, this is in line with the AXI definition
output [`E203_ADDR_SIZE-1:0] ifu2biu_icb_cmd_addr, // Bus transaction start addr
// * Bus RSP channel
input ifu2biu_icb_rsp_valid, // Response valid
output ifu2biu_icb_rsp_ready, // Response ready
input ifu2biu_icb_rsp_err, // Response error
// Note: the RSP rdata is inline with AXI definition
input [`E203_SYSMEM_DATA_WIDTH-1:0] ifu2biu_icb_rsp_rdata,
//input ifu2biu_replay,
`endif//}
//////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////
// The IR stage to EXU interface
output [`E203_INSTR_SIZE-1:0] ifu_o_ir,// The instruction register
output [`E203_PC_SIZE-1:0] ifu_o_pc, // The PC register along with
output ifu_o_pc_vld,
output ifu_o_misalgn, // The fetch misalign
output ifu_o_buserr, // The fetch bus error
output [`E203_RFIDX_WIDTH-1:0] ifu_o_rs1idx,
output [`E203_RFIDX_WIDTH-1:0] ifu_o_rs2idx,
output ifu_o_prdt_taken, // The Bxx is predicted as taken
output ifu_o_muldiv_b2b,
output ifu_o_valid, // Handshake signals with EXU stage
input ifu_o_ready,
output pipe_flush_ack,
input pipe_flush_req,
input [`E203_PC_SIZE-1:0] pipe_flush_add_op1,
input [`E203_PC_SIZE-1:0] pipe_flush_add_op2,
`ifdef E203_TIMING_BOOST//}
input [`E203_PC_SIZE-1:0] pipe_flush_pc,
`endif//}
// The halt request come from other commit stage
// If the ifu_halt_req is asserting, then IFU will stop fetching new
// instructions and after the oustanding transactions are completed,
// asserting the ifu_halt_ack as the response.
// The IFU will resume fetching only after the ifu_halt_req is deasserted
input ifu_halt_req,
output ifu_halt_ack,
input oitf_empty,
input [`E203_XLEN-1:0] rf2ifu_x1,
input [`E203_XLEN-1:0] rf2ifu_rs1,
input dec2ifu_rden,
input dec2ifu_rs1en,
input [`E203_RFIDX_WIDTH-1:0] dec2ifu_rdidx,
input dec2ifu_mulhsu,
input dec2ifu_div ,
input dec2ifu_rem ,
input dec2ifu_divu ,
input dec2ifu_remu ,
input clk,
input rst_n
);
wire ifu_req_valid;
wire ifu_req_ready;
wire [`E203_PC_SIZE-1:0] ifu_req_pc;
wire ifu_req_seq;
wire ifu_req_seq_rv32;
wire [`E203_PC_SIZE-1:0] ifu_req_last_pc;
wire ifu_rsp_valid;
wire ifu_rsp_ready;
wire ifu_rsp_err;
//wire ifu_rsp_replay;
wire [`E203_INSTR_SIZE-1:0] ifu_rsp_instr;
e203_ifu_ifetch u_e203_ifu_ifetch(
.inspect_pc (inspect_pc),
.pc_rtvec (pc_rtvec),
.ifu_req_valid (ifu_req_valid),
.ifu_req_ready (ifu_req_ready),
.ifu_req_pc (ifu_req_pc ),
.ifu_req_seq (ifu_req_seq ),
.ifu_req_seq_rv32(ifu_req_seq_rv32),
.ifu_req_last_pc (ifu_req_last_pc ),
.ifu_rsp_valid (ifu_rsp_valid),
.ifu_rsp_ready (ifu_rsp_ready),
.ifu_rsp_err (ifu_rsp_err ),
//.ifu_rsp_replay(ifu_rsp_replay),
.ifu_rsp_instr (ifu_rsp_instr),
.ifu_o_ir (ifu_o_ir ),
.ifu_o_pc (ifu_o_pc ),
.ifu_o_pc_vld (ifu_o_pc_vld ),
.ifu_o_misalgn (ifu_o_misalgn),
.ifu_o_buserr (ifu_o_buserr ),
.ifu_o_rs1idx (ifu_o_rs1idx),
.ifu_o_rs2idx (ifu_o_rs2idx),
.ifu_o_prdt_taken(ifu_o_prdt_taken),
.ifu_o_muldiv_b2b(ifu_o_muldiv_b2b),
.ifu_o_valid (ifu_o_valid ),
.ifu_o_ready (ifu_o_ready ),
.pipe_flush_ack (pipe_flush_ack ),
.pipe_flush_req (pipe_flush_req ),
.pipe_flush_add_op1 (pipe_flush_add_op1),
`ifdef E203_TIMING_BOOST//}
.pipe_flush_pc (pipe_flush_pc),
`endif//}
.pipe_flush_add_op2 (pipe_flush_add_op2),
.ifu_halt_req (ifu_halt_req ),
.ifu_halt_ack (ifu_halt_ack ),
.oitf_empty (oitf_empty ),
.rf2ifu_x1 (rf2ifu_x1 ),
.rf2ifu_rs1 (rf2ifu_rs1 ),
.dec2ifu_rden (dec2ifu_rden ),
.dec2ifu_rs1en (dec2ifu_rs1en),
.dec2ifu_rdidx (dec2ifu_rdidx),
.dec2ifu_mulhsu(dec2ifu_mulhsu),
.dec2ifu_div (dec2ifu_div ),
.dec2ifu_rem (dec2ifu_rem ),
.dec2ifu_divu (dec2ifu_divu ),
.dec2ifu_remu (dec2ifu_remu ),
.clk (clk ),
.rst_n (rst_n )
);
e203_ifu_ift2icb u_e203_ifu_ift2icb (
.ifu_req_valid (ifu_req_valid),
.ifu_req_ready (ifu_req_ready),
.ifu_req_pc (ifu_req_pc ),
.ifu_req_seq (ifu_req_seq ),
.ifu_req_seq_rv32(ifu_req_seq_rv32),
.ifu_req_last_pc (ifu_req_last_pc ),
.ifu_rsp_valid (ifu_rsp_valid),
.ifu_rsp_ready (ifu_rsp_ready),
.ifu_rsp_err (ifu_rsp_err ),
//.ifu_rsp_replay(ifu_rsp_replay),
.ifu_rsp_instr (ifu_rsp_instr),
.itcm_nohold (itcm_nohold),
`ifdef E203_HAS_ITCM //{
.itcm_region_indic (itcm_region_indic),
.ifu2itcm_icb_cmd_valid(ifu2itcm_icb_cmd_valid),
.ifu2itcm_icb_cmd_ready(ifu2itcm_icb_cmd_ready),
.ifu2itcm_icb_cmd_addr (ifu2itcm_icb_cmd_addr ),
.ifu2itcm_icb_rsp_valid(ifu2itcm_icb_rsp_valid),
.ifu2itcm_icb_rsp_ready(ifu2itcm_icb_rsp_ready),
.ifu2itcm_icb_rsp_err (ifu2itcm_icb_rsp_err ),
.ifu2itcm_icb_rsp_rdata(ifu2itcm_icb_rsp_rdata),
`endif//}
`ifdef E203_HAS_MEM_ITF //{
.ifu2biu_icb_cmd_valid(ifu2biu_icb_cmd_valid),
.ifu2biu_icb_cmd_ready(ifu2biu_icb_cmd_ready),
.ifu2biu_icb_cmd_addr (ifu2biu_icb_cmd_addr ),
.ifu2biu_icb_rsp_valid(ifu2biu_icb_rsp_valid),
.ifu2biu_icb_rsp_ready(ifu2biu_icb_rsp_ready),
.ifu2biu_icb_rsp_err (ifu2biu_icb_rsp_err ),
.ifu2biu_icb_rsp_rdata(ifu2biu_icb_rsp_rdata),
//.ifu2biu_replay (ifu2biu_replay),
`endif//}
`ifdef E203_HAS_ITCM //{
.ifu2itcm_holdup (ifu2itcm_holdup),
//.ifu2itcm_replay (ifu2itcm_replay),
`endif//}
.clk (clk ),
.rst_n (rst_n )
);
assign ifu_active = 1'b1;// Seems the IFU never rest at block level
endmodule
|
module e203_exu_wbck(
//////////////////////////////////////////////////////////////
// The ALU Write-Back Interface
input alu_wbck_i_valid, // Handshake valid
output alu_wbck_i_ready, // Handshake ready
input [`E203_XLEN-1:0] alu_wbck_i_wdat,
input [`E203_RFIDX_WIDTH-1:0] alu_wbck_i_rdidx,
// If ALU have error, it will not generate the wback_valid to wback module
// so we dont need the alu_wbck_i_err here
//////////////////////////////////////////////////////////////
// The Longp Write-Back Interface
input longp_wbck_i_valid, // Handshake valid
output longp_wbck_i_ready, // Handshake ready
input [`E203_FLEN-1:0] longp_wbck_i_wdat,
input [5-1:0] longp_wbck_i_flags,
input [`E203_RFIDX_WIDTH-1:0] longp_wbck_i_rdidx,
input longp_wbck_i_rdfpu,
//////////////////////////////////////////////////////////////
// The Final arbitrated Write-Back Interface to Regfile
output rf_wbck_o_ena,
output [`E203_XLEN-1:0] rf_wbck_o_wdat,
output [`E203_RFIDX_WIDTH-1:0] rf_wbck_o_rdidx,
input clk,
input rst_n
);
// The ALU instruction can write-back only when there is no any
// long pipeline instruction writing-back
// * Since ALU is the 1 cycle instructions, it have lowest
// priority in arbitration
wire wbck_ready4alu = (~longp_wbck_i_valid);
wire wbck_sel_alu = alu_wbck_i_valid & wbck_ready4alu;
// The Long-pipe instruction can always write-back since it have high priority
wire wbck_ready4longp = 1'b1;
wire wbck_sel_longp = longp_wbck_i_valid & wbck_ready4longp;
//////////////////////////////////////////////////////////////
// The Final arbitrated Write-Back Interface
wire rf_wbck_o_ready = 1'b1; // Regfile is always ready to be write because it just has 1 w-port
wire wbck_i_ready;
wire wbck_i_valid;
wire [`E203_FLEN-1:0] wbck_i_wdat;
wire [5-1:0] wbck_i_flags;
wire [`E203_RFIDX_WIDTH-1:0] wbck_i_rdidx;
wire wbck_i_rdfpu;
assign alu_wbck_i_ready = wbck_ready4alu & wbck_i_ready;
assign longp_wbck_i_ready = wbck_ready4longp & wbck_i_ready;
assign wbck_i_valid = wbck_sel_alu ? alu_wbck_i_valid : longp_wbck_i_valid;
`ifdef E203_FLEN_IS_32//{
assign wbck_i_wdat = wbck_sel_alu ? alu_wbck_i_wdat : longp_wbck_i_wdat;
`else//}{
assign wbck_i_wdat = wbck_sel_alu ? {{`E203_FLEN-`E203_XLEN{1'b0}},alu_wbck_i_wdat} : longp_wbck_i_wdat;
`endif//}
assign wbck_i_flags = wbck_sel_alu ? 5'b0 : longp_wbck_i_flags;
assign wbck_i_rdidx = wbck_sel_alu ? alu_wbck_i_rdidx : longp_wbck_i_rdidx;
assign wbck_i_rdfpu = wbck_sel_alu ? 1'b0 : longp_wbck_i_rdfpu;
// If it have error or non-rdwen it will not be send to this module
// instead have been killed at EU level, so it is always need to
// write back into regfile at here
assign wbck_i_ready = rf_wbck_o_ready;
wire rf_wbck_o_valid = wbck_i_valid;
wire wbck_o_ena = rf_wbck_o_valid & rf_wbck_o_ready;
assign rf_wbck_o_ena = wbck_o_ena & (~wbck_i_rdfpu);
assign rf_wbck_o_wdat = wbck_i_wdat[`E203_XLEN-1:0];
assign rf_wbck_o_rdidx = wbck_i_rdidx;
endmodule
|
module e203_exu_disp(
input wfi_halt_exu_req,
output wfi_halt_exu_ack,
input oitf_empty,
input amo_wait,
//////////////////////////////////////////////////////////////
// The operands and decode info from dispatch
input disp_i_valid, // Handshake valid
output disp_i_ready, // Handshake ready
// The operand 1/2 read-enable signals and indexes
input disp_i_rs1x0,
input disp_i_rs2x0,
input disp_i_rs1en,
input disp_i_rs2en,
input [`E203_RFIDX_WIDTH-1:0] disp_i_rs1idx,
input [`E203_RFIDX_WIDTH-1:0] disp_i_rs2idx,
input [`E203_XLEN-1:0] disp_i_rs1,
input [`E203_XLEN-1:0] disp_i_rs2,
input disp_i_rdwen,
input [`E203_RFIDX_WIDTH-1:0] disp_i_rdidx,
input [`E203_DECINFO_WIDTH-1:0] disp_i_info,
input [`E203_XLEN-1:0] disp_i_imm,
input [`E203_PC_SIZE-1:0] disp_i_pc,
input disp_i_misalgn,
input disp_i_buserr ,
input disp_i_ilegl ,
//////////////////////////////////////////////////////////////
// Dispatch to ALU
output disp_o_alu_valid,
input disp_o_alu_ready,
input disp_o_alu_longpipe,
output [`E203_XLEN-1:0] disp_o_alu_rs1,
output [`E203_XLEN-1:0] disp_o_alu_rs2,
output disp_o_alu_rdwen,
output [`E203_RFIDX_WIDTH-1:0] disp_o_alu_rdidx,
output [`E203_DECINFO_WIDTH-1:0] disp_o_alu_info,
output [`E203_XLEN-1:0] disp_o_alu_imm,
output [`E203_PC_SIZE-1:0] disp_o_alu_pc,
output [`E203_ITAG_WIDTH-1:0] disp_o_alu_itag,
output disp_o_alu_misalgn,
output disp_o_alu_buserr ,
output disp_o_alu_ilegl ,
//////////////////////////////////////////////////////////////
// Dispatch to OITF
input oitfrd_match_disprs1,
input oitfrd_match_disprs2,
input oitfrd_match_disprs3,
input oitfrd_match_disprd,
input [`E203_ITAG_WIDTH-1:0] disp_oitf_ptr ,
output disp_oitf_ena,
input disp_oitf_ready,
output disp_oitf_rs1fpu,
output disp_oitf_rs2fpu,
output disp_oitf_rs3fpu,
output disp_oitf_rdfpu ,
output disp_oitf_rs1en ,
output disp_oitf_rs2en ,
output disp_oitf_rs3en ,
output disp_oitf_rdwen ,
output [`E203_RFIDX_WIDTH-1:0] disp_oitf_rs1idx,
output [`E203_RFIDX_WIDTH-1:0] disp_oitf_rs2idx,
output [`E203_RFIDX_WIDTH-1:0] disp_oitf_rs3idx,
output [`E203_RFIDX_WIDTH-1:0] disp_oitf_rdidx ,
output [`E203_PC_SIZE-1:0] disp_oitf_pc ,
input clk,
input rst_n
);
wire [`E203_DECINFO_GRP_WIDTH-1:0] disp_i_info_grp = disp_i_info [`E203_DECINFO_GRP];
// Based on current 2 pipe stage implementation, the 2nd stage need to have all instruction
// to be commited via ALU interface, so every instruction need to be dispatched to ALU,
// regardless it is long pipe or not, and inside ALU it will issue instructions to different
// other longpipes
//wire disp_alu = (disp_i_info_grp == `E203_DECINFO_GRP_ALU)
// | (disp_i_info_grp == `E203_DECINFO_GRP_BJP)
// | (disp_i_info_grp == `E203_DECINFO_GRP_CSR)
// `ifdef E203_SUPPORT_SHARE_MULDIV //{
// | (disp_i_info_grp == `E203_DECINFO_GRP_MULDIV)
// `endif//E203_SUPPORT_SHARE_MULDIV}
// | (disp_i_info_grp == `E203_DECINFO_GRP_AGU);
wire disp_csr = (disp_i_info_grp == `E203_DECINFO_GRP_CSR);
wire disp_alu_longp_prdt = (disp_i_info_grp == `E203_DECINFO_GRP_AGU)
;
wire disp_alu_longp_real = disp_o_alu_longpipe;
// Both fence and fencei need to make sure all outstanding instruction have been completed
wire disp_fence_fencei = (disp_i_info_grp == `E203_DECINFO_GRP_BJP) &
( disp_i_info [`E203_DECINFO_BJP_FENCE] | disp_i_info [`E203_DECINFO_BJP_FENCEI]);
// Since any instruction will need to be dispatched to ALU, we dont need the gate here
// wire disp_i_ready_pos = disp_alu & disp_o_alu_ready;
// assign disp_o_alu_valid = disp_alu & disp_i_valid_pos;
wire disp_i_valid_pos;
wire disp_i_ready_pos = disp_o_alu_ready;
assign disp_o_alu_valid = disp_i_valid_pos;
//////////////////////////////////////////////////////////////
// The Dispatch Scheme Introduction for two-pipeline stage
// #1: The instruction after dispatched must have already have operand fetched, so
// there is no any WAR dependency happened.
// #2: The ALU-instruction are dispatched and executed in-order inside ALU, so
// there is no any WAW dependency happened among ALU instructions.
// Note: LSU since its AGU is handled inside ALU, so it is treated as a ALU instruction
// #3: The non-ALU-instruction are all tracked by OITF, and must be write-back in-order, so
// it is like ALU in-ordered. So there is no any WAW dependency happened among
// non-ALU instructions.
// Then what dependency will we have?
// * RAW: This is the real dependency
// * WAW: The WAW between ALU an non-ALU instructions
//
// So #1, The dispatching ALU instruction can not proceed and must be stalled when
// ** RAW: The ALU reading operands have data dependency with OITF entries
// *** Note: since it is 2 pipeline stage, any last ALU instruction have already
// write-back into the regfile. So there is no chance for ALU instr to depend
// on last ALU instructions as RAW.
// Note: if it is 3 pipeline stages, then we also need to consider the ALU-to-ALU
// RAW dependency.
// ** WAW: The ALU writing result have no any data dependency with OITF entries
// Note: Since the ALU instruction handled by ALU may surpass non-ALU OITF instructions
// so we must check this.
// And #2, The dispatching non-ALU instruction can not proceed and must be stalled when
// ** RAW: The non-ALU reading operands have data dependency with OITF entries
// *** Note: since it is 2 pipeline stage, any last ALU instruction have already
// write-back into the regfile. So there is no chance for non-ALU instr to depend
// on last ALU instructions as RAW.
// Note: if it is 3 pipeline stages, then we also need to consider the non-ALU-to-ALU
// RAW dependency.
wire raw_dep = ((oitfrd_match_disprs1) |
(oitfrd_match_disprs2) |
(oitfrd_match_disprs3));
// Only check the longp instructions (non-ALU) for WAW, here if we
// use the precise version (disp_alu_longp_real), it will hurt timing very much, but
// if we use imprecise version of disp_alu_longp_prdt, it is kind of tricky and in
// some corner case. For example, the AGU (treated as longp) will actually not dispatch
// to longp but just directly commited, then it become a normal ALU instruction, and should
// check the WAW dependency, but this only happened when it is AMO or unaligned-uop, so
// ideally we dont need to worry about it, because
// * We dont support AMO in 2 stage CPU here
// * We dont support Unalign load-store in 2 stage CPU here, which
// will be triggered as exception, so will not really write-back
// into regfile
// * But it depends on some assumption, so it is still risky if in the future something changed.
// Nevertheless: using this condition only waiver the longpipe WAW case, that is, two
// longp instruction write-back same reg back2back. Is it possible or is it common?
// after we checking the benmark result we found if we remove this complexity here
// it just does not change any benchmark number, so just remove that condition out. Means
// all of the instructions will check waw_dep
//wire alu_waw_dep = (~disp_alu_longp_prdt) & (oitfrd_match_disprd & disp_i_rdwen);
wire waw_dep = (oitfrd_match_disprd);
wire dep = raw_dep | waw_dep;
// The WFI halt exu ack will be asserted when the OITF is empty
// and also there is no AMO oustanding uops
assign wfi_halt_exu_ack = oitf_empty & (~amo_wait);
wire disp_condition =
// To be more conservtive, any accessing CSR instruction need to wait the oitf to be empty.
// Theoretically speaking, it should also flush pipeline after the CSR have been updated
// to make sure the subsequent instruction get correct CSR values, but in our 2-pipeline stage
// implementation, CSR is updated after EXU stage, and subsequent are all executed at EXU stage,
// no chance to got wrong CSR values, so we dont need to worry about this.
(disp_csr ? oitf_empty : 1'b1)
// To handle the Fence: just stall dispatch until the OITF is empty
& (disp_fence_fencei ? oitf_empty : 1'b1)
// If it was a WFI instruction commited halt req, then it will stall the disaptch
& (~wfi_halt_exu_req)
// No dependency
& (~dep)
//// // If dispatch to ALU as long pipeline, then must check
//// // the OITF is ready
//// & ((disp_alu & disp_o_alu_longpipe) ? disp_oitf_ready : 1'b1);
// To cut the critical timing path from longpipe signal
// we always assume the LSU will need oitf ready
& (disp_alu_longp_prdt ? disp_oitf_ready : 1'b1);
assign disp_i_valid_pos = disp_condition & disp_i_valid;
assign disp_i_ready = disp_condition & disp_i_ready_pos;
wire [`E203_XLEN-1:0] disp_i_rs1_msked = disp_i_rs1 & {`E203_XLEN{~disp_i_rs1x0}};
wire [`E203_XLEN-1:0] disp_i_rs2_msked = disp_i_rs2 & {`E203_XLEN{~disp_i_rs2x0}};
// Since we always dispatch any instructions into ALU, so we dont need to gate ops here
//assign disp_o_alu_rs1 = {`E203_XLEN{disp_alu}} & disp_i_rs1_msked;
//assign disp_o_alu_rs2 = {`E203_XLEN{disp_alu}} & disp_i_rs2_msked;
//assign disp_o_alu_rdwen = disp_alu & disp_i_rdwen;
//assign disp_o_alu_rdidx = {`E203_RFIDX_WIDTH{disp_alu}} & disp_i_rdidx;
//assign disp_o_alu_info = {`E203_DECINFO_WIDTH{disp_alu}} & disp_i_info;
assign disp_o_alu_rs1 = disp_i_rs1_msked;
assign disp_o_alu_rs2 = disp_i_rs2_msked;
assign disp_o_alu_rdwen = disp_i_rdwen;
assign disp_o_alu_rdidx = disp_i_rdidx;
assign disp_o_alu_info = disp_i_info;
// Why we use precise version of disp_longp here, because
// only when it is really dispatched as long pipe then allocate the OITF
assign disp_oitf_ena = disp_o_alu_valid & disp_o_alu_ready & disp_alu_longp_real;
assign disp_o_alu_imm = disp_i_imm;
assign disp_o_alu_pc = disp_i_pc;
assign disp_o_alu_itag = disp_oitf_ptr;
assign disp_o_alu_misalgn= disp_i_misalgn;
assign disp_o_alu_buserr = disp_i_buserr ;
assign disp_o_alu_ilegl = disp_i_ilegl ;
`ifndef E203_HAS_FPU//{
wire disp_i_fpu = 1'b0;
wire disp_i_fpu_rs1en = 1'b0;
wire disp_i_fpu_rs2en = 1'b0;
wire disp_i_fpu_rs3en = 1'b0;
wire disp_i_fpu_rdwen = 1'b0;
wire [`E203_RFIDX_WIDTH-1:0] disp_i_fpu_rs1idx = `E203_RFIDX_WIDTH'b0;
wire [`E203_RFIDX_WIDTH-1:0] disp_i_fpu_rs2idx = `E203_RFIDX_WIDTH'b0;
wire [`E203_RFIDX_WIDTH-1:0] disp_i_fpu_rs3idx = `E203_RFIDX_WIDTH'b0;
wire [`E203_RFIDX_WIDTH-1:0] disp_i_fpu_rdidx = `E203_RFIDX_WIDTH'b0;
wire disp_i_fpu_rs1fpu = 1'b0;
wire disp_i_fpu_rs2fpu = 1'b0;
wire disp_i_fpu_rs3fpu = 1'b0;
wire disp_i_fpu_rdfpu = 1'b0;
`endif//}
assign disp_oitf_rs1fpu = disp_i_fpu ? (disp_i_fpu_rs1en & disp_i_fpu_rs1fpu) : 1'b0;
assign disp_oitf_rs2fpu = disp_i_fpu ? (disp_i_fpu_rs2en & disp_i_fpu_rs2fpu) : 1'b0;
assign disp_oitf_rs3fpu = disp_i_fpu ? (disp_i_fpu_rs3en & disp_i_fpu_rs3fpu) : 1'b0;
assign disp_oitf_rdfpu = disp_i_fpu ? (disp_i_fpu_rdwen & disp_i_fpu_rdfpu ) : 1'b0;
assign disp_oitf_rs1en = disp_i_fpu ? disp_i_fpu_rs1en : disp_i_rs1en;
assign disp_oitf_rs2en = disp_i_fpu ? disp_i_fpu_rs2en : disp_i_rs2en;
assign disp_oitf_rs3en = disp_i_fpu ? disp_i_fpu_rs3en : 1'b0;
assign disp_oitf_rdwen = disp_i_fpu ? disp_i_fpu_rdwen : disp_i_rdwen;
assign disp_oitf_rs1idx = disp_i_fpu ? disp_i_fpu_rs1idx : disp_i_rs1idx;
assign disp_oitf_rs2idx = disp_i_fpu ? disp_i_fpu_rs2idx : disp_i_rs2idx;
assign disp_oitf_rs3idx = disp_i_fpu ? disp_i_fpu_rs3idx : `E203_RFIDX_WIDTH'b0;
assign disp_oitf_rdidx = disp_i_fpu ? disp_i_fpu_rdidx : disp_i_rdidx;
assign disp_oitf_pc = disp_i_pc;
endmodule
|
module sirv_LevelGateway(
input clock,
input reset,
input io_interrupt,
output io_plic_valid,
input io_plic_ready,
input io_plic_complete
);
reg inFlight;
reg [31:0] GEN_2;
wire T_12;
wire GEN_0;
wire GEN_1;
wire T_16;
wire T_17;
assign io_plic_valid = T_17;
assign T_12 = io_interrupt & io_plic_ready;
assign GEN_0 = T_12 ? 1'h1 : inFlight;
assign GEN_1 = io_plic_complete ? 1'h0 : GEN_0;
assign T_16 = inFlight == 1'h0;
assign T_17 = io_interrupt & T_16;
always @(posedge clock or posedge reset) begin
if (reset) begin
inFlight <= 1'h0;
end else begin
if (io_plic_complete) begin
inFlight <= 1'h0;
end else begin
if (T_12) begin
inFlight <= 1'h1;
end
end
end
end
endmodule
|
module sirv_pwm16_top(
input clk,
input rst_n,
input i_icb_cmd_valid,
output i_icb_cmd_ready,
input [32-1:0] i_icb_cmd_addr,
input i_icb_cmd_read,
input [32-1:0] i_icb_cmd_wdata,
output i_icb_rsp_valid,
input i_icb_rsp_ready,
output [32-1:0] i_icb_rsp_rdata,
output io_interrupts_0_0,
output io_interrupts_0_1,
output io_interrupts_0_2,
output io_interrupts_0_3,
output io_gpio_0,
output io_gpio_1,
output io_gpio_2,
output io_gpio_3
);
wire io_in_0_a_ready;
assign i_icb_cmd_ready = io_in_0_a_ready;
wire io_in_0_a_valid = i_icb_cmd_valid;
wire [2:0] io_in_0_a_bits_opcode = i_icb_cmd_read ? 3'h4 : 3'h0;
wire [2:0] io_in_0_a_bits_param = 3'b0;
wire [2:0] io_in_0_a_bits_size = 3'd2;
wire [4:0] io_in_0_a_bits_source = 5'b0;
wire [28:0] io_in_0_a_bits_address = i_icb_cmd_addr[28:0];
wire [3:0] io_in_0_a_bits_mask = 4'b1111;
wire [31:0] io_in_0_a_bits_data = i_icb_cmd_wdata;
wire io_in_0_d_ready = i_icb_rsp_ready;
wire [2:0] io_in_0_d_bits_opcode;
wire [1:0] io_in_0_d_bits_param;
wire [2:0] io_in_0_d_bits_size;
wire [4:0] io_in_0_d_bits_source;
wire io_in_0_d_bits_sink;
wire [1:0] io_in_0_d_bits_addr_lo;
wire [31:0] io_in_0_d_bits_data;
wire io_in_0_d_bits_error;
wire io_in_0_d_valid;
assign i_icb_rsp_valid = io_in_0_d_valid;
assign i_icb_rsp_rdata = io_in_0_d_bits_data;
// Not used
wire io_in_0_b_ready = 1'b0;
wire io_in_0_b_valid;
wire [2:0] io_in_0_b_bits_opcode;
wire [1:0] io_in_0_b_bits_param;
wire [2:0] io_in_0_b_bits_size;
wire [4:0] io_in_0_b_bits_source;
wire [28:0] io_in_0_b_bits_address;
wire [3:0] io_in_0_b_bits_mask;
wire [31:0] io_in_0_b_bits_data;
// Not used
wire io_in_0_c_ready;
wire io_in_0_c_valid = 1'b0;
wire [2:0] io_in_0_c_bits_opcode = 3'b0;
wire [2:0] io_in_0_c_bits_param = 3'b0;
wire [2:0] io_in_0_c_bits_size = 3'd2;
wire [4:0] io_in_0_c_bits_source = 5'b0;
wire [28:0] io_in_0_c_bits_address = 29'b0;
wire [31:0] io_in_0_c_bits_data = 32'b0;
wire io_in_0_c_bits_error = 1'b0;
// Not used
wire io_in_0_e_ready;
wire io_in_0_e_valid = 1'b0;
wire io_in_0_e_bits_sink = 1'b0;
sirv_pwm16 u_sirv_pwm16(
.clock (clk ),
.reset (~rst_n ),
.io_interrupts_0_0 (io_interrupts_0_0 ),
.io_interrupts_0_1 (io_interrupts_0_1 ),
.io_interrupts_0_2 (io_interrupts_0_2 ),
.io_interrupts_0_3 (io_interrupts_0_3 ),
.io_gpio_0 (io_gpio_0 ),
.io_gpio_1 (io_gpio_1 ),
.io_gpio_2 (io_gpio_2 ),
.io_gpio_3 (io_gpio_3 ),
.io_in_0_a_ready (io_in_0_a_ready ),
.io_in_0_a_valid (io_in_0_a_valid ),
.io_in_0_a_bits_opcode (io_in_0_a_bits_opcode ),
.io_in_0_a_bits_param (io_in_0_a_bits_param ),
.io_in_0_a_bits_size (io_in_0_a_bits_size ),
.io_in_0_a_bits_source (io_in_0_a_bits_source ),
.io_in_0_a_bits_address (io_in_0_a_bits_address ),
.io_in_0_a_bits_mask (io_in_0_a_bits_mask ),
.io_in_0_a_bits_data (io_in_0_a_bits_data ),
.io_in_0_b_ready (io_in_0_b_ready ),
.io_in_0_b_valid (io_in_0_b_valid ),
.io_in_0_b_bits_opcode (io_in_0_b_bits_opcode ),
.io_in_0_b_bits_param (io_in_0_b_bits_param ),
.io_in_0_b_bits_size (io_in_0_b_bits_size ),
.io_in_0_b_bits_source (io_in_0_b_bits_source ),
.io_in_0_b_bits_address (io_in_0_b_bits_address ),
.io_in_0_b_bits_mask (io_in_0_b_bits_mask ),
.io_in_0_b_bits_data (io_in_0_b_bits_data ),
.io_in_0_c_ready (io_in_0_c_ready ),
.io_in_0_c_valid (io_in_0_c_valid ),
.io_in_0_c_bits_opcode (io_in_0_c_bits_opcode ),
.io_in_0_c_bits_param (io_in_0_c_bits_param ),
.io_in_0_c_bits_size (io_in_0_c_bits_size ),
.io_in_0_c_bits_source (io_in_0_c_bits_source ),
.io_in_0_c_bits_address (io_in_0_c_bits_address ),
.io_in_0_c_bits_data (io_in_0_c_bits_data ),
.io_in_0_c_bits_error (io_in_0_c_bits_error ),
.io_in_0_d_ready (io_in_0_d_ready ),
.io_in_0_d_valid (io_in_0_d_valid ),
.io_in_0_d_bits_opcode (io_in_0_d_bits_opcode ),
.io_in_0_d_bits_param (io_in_0_d_bits_param ),
.io_in_0_d_bits_size (io_in_0_d_bits_size ),
.io_in_0_d_bits_source (io_in_0_d_bits_source ),
.io_in_0_d_bits_sink (io_in_0_d_bits_sink ),
.io_in_0_d_bits_addr_lo (io_in_0_d_bits_addr_lo ),
.io_in_0_d_bits_data (io_in_0_d_bits_data ),
.io_in_0_d_bits_error (io_in_0_d_bits_error ),
.io_in_0_e_ready (io_in_0_e_ready ),
.io_in_0_e_valid (io_in_0_e_valid ),
.io_in_0_e_bits_sink (io_in_0_e_bits_sink )
);
endmodule
|
module sirv_qspi_4cs_top(
input clk,
input rst_n,
input i_icb_cmd_valid,
output i_icb_cmd_ready,
input [32-1:0] i_icb_cmd_addr,
input i_icb_cmd_read,
input [32-1:0] i_icb_cmd_wdata,
output i_icb_rsp_valid,
input i_icb_rsp_ready,
output [32-1:0] i_icb_rsp_rdata,
output io_port_sck,
input io_port_dq_0_i,
output io_port_dq_0_o,
output io_port_dq_0_oe,
input io_port_dq_1_i,
output io_port_dq_1_o,
output io_port_dq_1_oe,
input io_port_dq_2_i,
output io_port_dq_2_o,
output io_port_dq_2_oe,
input io_port_dq_3_i,
output io_port_dq_3_o,
output io_port_dq_3_oe,
output io_port_cs_0,
output io_port_cs_1,
output io_port_cs_2,
output io_port_cs_3,
output io_tl_i_0_0
);
wire io_tl_r_0_a_ready;
assign i_icb_cmd_ready = io_tl_r_0_a_ready;
wire io_tl_r_0_a_valid = i_icb_cmd_valid;
wire [2:0] io_tl_r_0_a_bits_opcode = i_icb_cmd_read ? 3'h4 : 3'h0;
wire [2:0] io_tl_r_0_a_bits_param = 3'b0;
wire [2:0] io_tl_r_0_a_bits_size = 3'd2;
wire [4:0] io_tl_r_0_a_bits_source = 5'b0;
wire [28:0] io_tl_r_0_a_bits_address = i_icb_cmd_addr[28:0];
wire [3:0] io_tl_r_0_a_bits_mask = 4'b1111;
wire [31:0] io_tl_r_0_a_bits_data = i_icb_cmd_wdata;
wire io_tl_r_0_d_ready = i_icb_rsp_ready;
wire [2:0] io_tl_r_0_d_bits_opcode;
wire [1:0] io_tl_r_0_d_bits_param;
wire [2:0] io_tl_r_0_d_bits_size;
wire [4:0] io_tl_r_0_d_bits_source;
wire io_tl_r_0_d_bits_sink;
wire [1:0] io_tl_r_0_d_bits_addr_lo;
wire [31:0] io_tl_r_0_d_bits_data;
wire io_tl_r_0_d_bits_error;
wire io_tl_r_0_d_valid;
assign i_icb_rsp_valid = io_tl_r_0_d_valid;
assign i_icb_rsp_rdata = io_tl_r_0_d_bits_data;
// Not used
wire io_tl_r_0_b_ready = 1'b0;
wire io_tl_r_0_b_valid;
wire [2:0] io_tl_r_0_b_bits_opcode;
wire [1:0] io_tl_r_0_b_bits_param;
wire [2:0] io_tl_r_0_b_bits_size;
wire [4:0] io_tl_r_0_b_bits_source;
wire [28:0] io_tl_r_0_b_bits_address;
wire [3:0] io_tl_r_0_b_bits_mask;
wire [31:0] io_tl_r_0_b_bits_data;
// Not used
wire io_tl_r_0_c_ready;
wire io_tl_r_0_c_valid = 1'b0;
wire [2:0] io_tl_r_0_c_bits_opcode = 3'b0;
wire [2:0] io_tl_r_0_c_bits_param = 3'b0;
wire [2:0] io_tl_r_0_c_bits_size = 3'd2;
wire [4:0] io_tl_r_0_c_bits_source = 5'b0;
wire [28:0] io_tl_r_0_c_bits_address = 29'b0;
wire [31:0] io_tl_r_0_c_bits_data = 32'b0;
wire io_tl_r_0_c_bits_error = 1'b0;
// Not used
wire io_tl_r_0_e_ready;
wire io_tl_r_0_e_valid = 1'b0;
wire io_tl_r_0_e_bits_sink = 1'b0;
sirv_qspi_4cs u_sirv_qspi_4cs(
.clock (clk ),
.reset (~rst_n ),
.io_tl_r_0_a_ready (io_tl_r_0_a_ready ),
.io_tl_r_0_a_valid (io_tl_r_0_a_valid ),
.io_tl_r_0_a_bits_opcode (io_tl_r_0_a_bits_opcode ),
.io_tl_r_0_a_bits_param (io_tl_r_0_a_bits_param ),
.io_tl_r_0_a_bits_size (io_tl_r_0_a_bits_size ),
.io_tl_r_0_a_bits_source (io_tl_r_0_a_bits_source ),
.io_tl_r_0_a_bits_address (io_tl_r_0_a_bits_address ),
.io_tl_r_0_a_bits_mask (io_tl_r_0_a_bits_mask ),
.io_tl_r_0_a_bits_data (io_tl_r_0_a_bits_data ),
.io_tl_r_0_b_ready (io_tl_r_0_b_ready ),
.io_tl_r_0_b_valid (io_tl_r_0_b_valid ),
.io_tl_r_0_b_bits_opcode (io_tl_r_0_b_bits_opcode ),
.io_tl_r_0_b_bits_param (io_tl_r_0_b_bits_param ),
.io_tl_r_0_b_bits_size (io_tl_r_0_b_bits_size ),
.io_tl_r_0_b_bits_source (io_tl_r_0_b_bits_source ),
.io_tl_r_0_b_bits_address (io_tl_r_0_b_bits_address ),
.io_tl_r_0_b_bits_mask (io_tl_r_0_b_bits_mask ),
.io_tl_r_0_b_bits_data (io_tl_r_0_b_bits_data ),
.io_tl_r_0_c_ready (io_tl_r_0_c_ready ),
.io_tl_r_0_c_valid (io_tl_r_0_c_valid ),
.io_tl_r_0_c_bits_opcode (io_tl_r_0_c_bits_opcode ),
.io_tl_r_0_c_bits_param (io_tl_r_0_c_bits_param ),
.io_tl_r_0_c_bits_size (io_tl_r_0_c_bits_size ),
.io_tl_r_0_c_bits_source (io_tl_r_0_c_bits_source ),
.io_tl_r_0_c_bits_address (io_tl_r_0_c_bits_address ),
.io_tl_r_0_c_bits_data (io_tl_r_0_c_bits_data ),
.io_tl_r_0_c_bits_error (io_tl_r_0_c_bits_error ),
.io_tl_r_0_d_ready (io_tl_r_0_d_ready ),
.io_tl_r_0_d_valid (io_tl_r_0_d_valid ),
.io_tl_r_0_d_bits_opcode (io_tl_r_0_d_bits_opcode ),
.io_tl_r_0_d_bits_param (io_tl_r_0_d_bits_param ),
.io_tl_r_0_d_bits_size (io_tl_r_0_d_bits_size ),
.io_tl_r_0_d_bits_source (io_tl_r_0_d_bits_source ),
.io_tl_r_0_d_bits_sink (io_tl_r_0_d_bits_sink ),
.io_tl_r_0_d_bits_addr_lo (io_tl_r_0_d_bits_addr_lo ),
.io_tl_r_0_d_bits_data (io_tl_r_0_d_bits_data ),
.io_tl_r_0_d_bits_error (io_tl_r_0_d_bits_error ),
.io_tl_r_0_e_ready (io_tl_r_0_e_ready ),
.io_tl_r_0_e_valid (io_tl_r_0_e_valid ),
.io_tl_r_0_e_bits_sink (io_tl_r_0_e_bits_sink ),
.io_port_sck (io_port_sck ),
.io_port_dq_0_i (io_port_dq_0_i ),
.io_port_dq_0_o (io_port_dq_0_o ),
.io_port_dq_0_oe (io_port_dq_0_oe),
.io_port_dq_1_i (io_port_dq_1_i ),
.io_port_dq_1_o (io_port_dq_1_o ),
.io_port_dq_1_oe (io_port_dq_1_oe),
.io_port_dq_2_i (io_port_dq_2_i ),
.io_port_dq_2_o (io_port_dq_2_o ),
.io_port_dq_2_oe (io_port_dq_2_oe),
.io_port_dq_3_i (io_port_dq_3_i ),
.io_port_dq_3_o (io_port_dq_3_o ),
.io_port_dq_3_oe (io_port_dq_3_oe),
.io_port_cs_0 (io_port_cs_0 ),
.io_port_cs_1 (io_port_cs_1 ),
.io_port_cs_2 (io_port_cs_2 ),
.io_port_cs_3 (io_port_cs_3 ),
.io_tl_i_0_0 (io_tl_i_0_0 )
);
endmodule
|
module sirv_aon_lclkgen_regs(
input clk,
input rst_n,
output lfxoscen,
input i_icb_cmd_valid,
output i_icb_cmd_ready,
input [8 -1:0] i_icb_cmd_addr,
input i_icb_cmd_read,
input [32-1:0] i_icb_cmd_wdata,
output i_icb_rsp_valid,
input i_icb_rsp_ready,
output [32-1:0] i_icb_rsp_rdata
);
// Directly connect the command channel with response channel
assign i_icb_rsp_valid = i_icb_cmd_valid;
assign i_icb_cmd_ready = i_icb_rsp_ready;
wire icb_wr_en = i_icb_cmd_valid & i_icb_cmd_ready & (~i_icb_cmd_read);
wire [32-1:0] icb_wdata = i_icb_cmd_wdata;
wire [32-1:0] lfxosccfg_r;
// Addr selection
wire sel_lfxosccfg = (i_icb_cmd_addr == 8'h00);
wire icb_wr_en_lfxosccfg = icb_wr_en & sel_lfxosccfg ;
assign i_icb_rsp_rdata = ({32{sel_lfxosccfg}} & lfxosccfg_r);
/////////////////////////////////////////////////////////////////////////////////////////
// LFXOSCCFG
wire lfxoscen_ena = icb_wr_en_lfxosccfg;
// The reset value is 1
sirv_gnrl_dfflrs #(1) lfxoscen_dfflrs (lfxoscen_ena, icb_wdata[30], lfxoscen, clk, rst_n);
assign lfxosccfg_r = {1'b0, lfxoscen, 30'b0};
endmodule
|
module sirv_pmu(
input clock,
input reset,
input io_wakeup_awakeup,
input io_wakeup_dwakeup,
input io_wakeup_rtc,
input io_wakeup_reset,
output io_control_hfclkrst,
output io_control_corerst,
output io_control_reserved1,
output io_control_vddpaden,
output io_control_reserved0,
input io_regs_ie_write_valid,
input [3:0] io_regs_ie_write_bits,
output [3:0] io_regs_ie_read,
input io_regs_cause_write_valid,
input [31:0] io_regs_cause_write_bits,
output [31:0] io_regs_cause_read,
input io_regs_sleep_write_valid,
input [31:0] io_regs_sleep_write_bits,
output [31:0] io_regs_sleep_read,
input io_regs_key_write_valid,
input [31:0] io_regs_key_write_bits,
output [31:0] io_regs_key_read,
input io_regs_wakeupProgram_0_write_valid,
input [31:0] io_regs_wakeupProgram_0_write_bits,
output [31:0] io_regs_wakeupProgram_0_read,
input io_regs_wakeupProgram_1_write_valid,
input [31:0] io_regs_wakeupProgram_1_write_bits,
output [31:0] io_regs_wakeupProgram_1_read,
input io_regs_wakeupProgram_2_write_valid,
input [31:0] io_regs_wakeupProgram_2_write_bits,
output [31:0] io_regs_wakeupProgram_2_read,
input io_regs_wakeupProgram_3_write_valid,
input [31:0] io_regs_wakeupProgram_3_write_bits,
output [31:0] io_regs_wakeupProgram_3_read,
input io_regs_wakeupProgram_4_write_valid,
input [31:0] io_regs_wakeupProgram_4_write_bits,
output [31:0] io_regs_wakeupProgram_4_read,
input io_regs_wakeupProgram_5_write_valid,
input [31:0] io_regs_wakeupProgram_5_write_bits,
output [31:0] io_regs_wakeupProgram_5_read,
input io_regs_wakeupProgram_6_write_valid,
input [31:0] io_regs_wakeupProgram_6_write_bits,
output [31:0] io_regs_wakeupProgram_6_read,
input io_regs_wakeupProgram_7_write_valid,
input [31:0] io_regs_wakeupProgram_7_write_bits,
output [31:0] io_regs_wakeupProgram_7_read,
input io_regs_sleepProgram_0_write_valid,
input [31:0] io_regs_sleepProgram_0_write_bits,
output [31:0] io_regs_sleepProgram_0_read,
input io_regs_sleepProgram_1_write_valid,
input [31:0] io_regs_sleepProgram_1_write_bits,
output [31:0] io_regs_sleepProgram_1_read,
input io_regs_sleepProgram_2_write_valid,
input [31:0] io_regs_sleepProgram_2_write_bits,
output [31:0] io_regs_sleepProgram_2_read,
input io_regs_sleepProgram_3_write_valid,
input [31:0] io_regs_sleepProgram_3_write_bits,
output [31:0] io_regs_sleepProgram_3_read,
input io_regs_sleepProgram_4_write_valid,
input [31:0] io_regs_sleepProgram_4_write_bits,
output [31:0] io_regs_sleepProgram_4_read,
input io_regs_sleepProgram_5_write_valid,
input [31:0] io_regs_sleepProgram_5_write_bits,
output [31:0] io_regs_sleepProgram_5_read,
input io_regs_sleepProgram_6_write_valid,
input [31:0] io_regs_sleepProgram_6_write_bits,
output [31:0] io_regs_sleepProgram_6_read,
input io_regs_sleepProgram_7_write_valid,
input [31:0] io_regs_sleepProgram_7_write_bits,
output [31:0] io_regs_sleepProgram_7_read,
input io_resetCauses_wdogrst,
input io_resetCauses_erst,
input io_resetCauses_porrst
);
reg T_355;
reg [31:0] GEN_1;
reg T_356;
reg [31:0] GEN_2;
wire core_clock;
wire core_reset;
wire core_io_wakeup_awakeup;
wire core_io_wakeup_dwakeup;
wire core_io_wakeup_rtc;
wire core_io_wakeup_reset;
wire core_io_control_valid;
wire core_io_control_bits_hfclkrst;
wire core_io_control_bits_corerst;
wire core_io_control_bits_reserved1;
wire core_io_control_bits_vddpaden;
wire core_io_control_bits_reserved0;
wire [1:0] core_io_resetCause;
wire core_io_regs_ie_write_valid;
wire [3:0] core_io_regs_ie_write_bits;
wire [3:0] core_io_regs_ie_read;
wire core_io_regs_cause_write_valid;
wire [31:0] core_io_regs_cause_write_bits;
wire [31:0] core_io_regs_cause_read;
wire core_io_regs_sleep_write_valid;
wire [31:0] core_io_regs_sleep_write_bits;
wire [31:0] core_io_regs_sleep_read;
wire core_io_regs_key_write_valid;
wire [31:0] core_io_regs_key_write_bits;
wire [31:0] core_io_regs_key_read;
wire core_io_regs_wakeupProgram_0_write_valid;
wire [31:0] core_io_regs_wakeupProgram_0_write_bits;
wire [31:0] core_io_regs_wakeupProgram_0_read;
wire core_io_regs_wakeupProgram_1_write_valid;
wire [31:0] core_io_regs_wakeupProgram_1_write_bits;
wire [31:0] core_io_regs_wakeupProgram_1_read;
wire core_io_regs_wakeupProgram_2_write_valid;
wire [31:0] core_io_regs_wakeupProgram_2_write_bits;
wire [31:0] core_io_regs_wakeupProgram_2_read;
wire core_io_regs_wakeupProgram_3_write_valid;
wire [31:0] core_io_regs_wakeupProgram_3_write_bits;
wire [31:0] core_io_regs_wakeupProgram_3_read;
wire core_io_regs_wakeupProgram_4_write_valid;
wire [31:0] core_io_regs_wakeupProgram_4_write_bits;
wire [31:0] core_io_regs_wakeupProgram_4_read;
wire core_io_regs_wakeupProgram_5_write_valid;
wire [31:0] core_io_regs_wakeupProgram_5_write_bits;
wire [31:0] core_io_regs_wakeupProgram_5_read;
wire core_io_regs_wakeupProgram_6_write_valid;
wire [31:0] core_io_regs_wakeupProgram_6_write_bits;
wire [31:0] core_io_regs_wakeupProgram_6_read;
wire core_io_regs_wakeupProgram_7_write_valid;
wire [31:0] core_io_regs_wakeupProgram_7_write_bits;
wire [31:0] core_io_regs_wakeupProgram_7_read;
wire core_io_regs_sleepProgram_0_write_valid;
wire [31:0] core_io_regs_sleepProgram_0_write_bits;
wire [31:0] core_io_regs_sleepProgram_0_read;
wire core_io_regs_sleepProgram_1_write_valid;
wire [31:0] core_io_regs_sleepProgram_1_write_bits;
wire [31:0] core_io_regs_sleepProgram_1_read;
wire core_io_regs_sleepProgram_2_write_valid;
wire [31:0] core_io_regs_sleepProgram_2_write_bits;
wire [31:0] core_io_regs_sleepProgram_2_read;
wire core_io_regs_sleepProgram_3_write_valid;
wire [31:0] core_io_regs_sleepProgram_3_write_bits;
wire [31:0] core_io_regs_sleepProgram_3_read;
wire core_io_regs_sleepProgram_4_write_valid;
wire [31:0] core_io_regs_sleepProgram_4_write_bits;
wire [31:0] core_io_regs_sleepProgram_4_read;
wire core_io_regs_sleepProgram_5_write_valid;
wire [31:0] core_io_regs_sleepProgram_5_write_bits;
wire [31:0] core_io_regs_sleepProgram_5_read;
wire core_io_regs_sleepProgram_6_write_valid;
wire [31:0] core_io_regs_sleepProgram_6_write_bits;
wire [31:0] core_io_regs_sleepProgram_6_read;
wire core_io_regs_sleepProgram_7_write_valid;
wire [31:0] core_io_regs_sleepProgram_7_write_bits;
wire [31:0] core_io_regs_sleepProgram_7_read;
wire [1:0] T_358;
wire [1:0] T_359;
wire [2:0] T_360;
wire [4:0] T_361;
wire [4:0] T_362;
wire AsyncResetRegVec_1_1_clock;
wire AsyncResetRegVec_1_1_reset;
wire [4:0] AsyncResetRegVec_1_1_io_d;
wire [4:0] AsyncResetRegVec_1_1_io_q;
wire AsyncResetRegVec_1_1_io_en;
//wire [4:0] latch;
//Bob: the naming as latch is not good, which will introduce some confusing, so we give it renames here
wire [4:0] core_io_control_bits;
wire T_369_hfclkrst;
wire T_369_corerst;
wire T_369_reserved1;
wire T_369_vddpaden;
wire T_369_reserved0;
wire T_375;
wire T_376;
wire T_377;
wire T_378;
wire T_379;
wire [1:0] T_380;
wire [2:0] T_381;
//Bob: Name as Latch is not good, give it new name here
//wire SRLatch_3_q;
//wire SRLatch_3_reset;
//wire SRLatch_3_set;
wire T_382;
wire T_383;
wire T_384;
wire T_385;
//wire SRLatch_1_1_q;
//wire SRLatch_1_1_reset;
//wire SRLatch_1_1_set;
wire T_389;
//wire SRLatch_2_1_q;
//wire SRLatch_2_1_reset;
//wire SRLatch_2_1_set;
wire T_393;
wire [1:0] T_394;
wire [2:0] T_395;
wire T_396;
wire [1:0] T_397;
wire [1:0] GEN_0;
wire [1:0] T_400;
wire T_401;
wire [1:0] T_402;
sirv_pmu_core u_pmu_core (
.clock(core_clock),
.reset(core_reset),
.io_wakeup_awakeup(core_io_wakeup_awakeup),
.io_wakeup_dwakeup(core_io_wakeup_dwakeup),
.io_wakeup_rtc(core_io_wakeup_rtc),
.io_wakeup_reset(core_io_wakeup_reset),
.io_control_valid(core_io_control_valid),
.io_control_bits_hfclkrst(core_io_control_bits_hfclkrst),
.io_control_bits_corerst(core_io_control_bits_corerst),
.io_control_bits_reserved1(core_io_control_bits_reserved1),
.io_control_bits_vddpaden(core_io_control_bits_vddpaden),
.io_control_bits_reserved0(core_io_control_bits_reserved0),
.io_resetCause(core_io_resetCause),
.io_regs_ie_write_valid(core_io_regs_ie_write_valid),
.io_regs_ie_write_bits(core_io_regs_ie_write_bits),
.io_regs_ie_read(core_io_regs_ie_read),
.io_regs_cause_write_valid(core_io_regs_cause_write_valid),
.io_regs_cause_write_bits(core_io_regs_cause_write_bits),
.io_regs_cause_read(core_io_regs_cause_read),
.io_regs_sleep_write_valid(core_io_regs_sleep_write_valid),
.io_regs_sleep_write_bits(core_io_regs_sleep_write_bits),
.io_regs_sleep_read(core_io_regs_sleep_read),
.io_regs_key_write_valid(core_io_regs_key_write_valid),
.io_regs_key_write_bits(core_io_regs_key_write_bits),
.io_regs_key_read(core_io_regs_key_read),
.io_regs_wakeupProgram_0_write_valid(core_io_regs_wakeupProgram_0_write_valid),
.io_regs_wakeupProgram_0_write_bits(core_io_regs_wakeupProgram_0_write_bits),
.io_regs_wakeupProgram_0_read(core_io_regs_wakeupProgram_0_read),
.io_regs_wakeupProgram_1_write_valid(core_io_regs_wakeupProgram_1_write_valid),
.io_regs_wakeupProgram_1_write_bits(core_io_regs_wakeupProgram_1_write_bits),
.io_regs_wakeupProgram_1_read(core_io_regs_wakeupProgram_1_read),
.io_regs_wakeupProgram_2_write_valid(core_io_regs_wakeupProgram_2_write_valid),
.io_regs_wakeupProgram_2_write_bits(core_io_regs_wakeupProgram_2_write_bits),
.io_regs_wakeupProgram_2_read(core_io_regs_wakeupProgram_2_read),
.io_regs_wakeupProgram_3_write_valid(core_io_regs_wakeupProgram_3_write_valid),
.io_regs_wakeupProgram_3_write_bits(core_io_regs_wakeupProgram_3_write_bits),
.io_regs_wakeupProgram_3_read(core_io_regs_wakeupProgram_3_read),
.io_regs_wakeupProgram_4_write_valid(core_io_regs_wakeupProgram_4_write_valid),
.io_regs_wakeupProgram_4_write_bits(core_io_regs_wakeupProgram_4_write_bits),
.io_regs_wakeupProgram_4_read(core_io_regs_wakeupProgram_4_read),
.io_regs_wakeupProgram_5_write_valid(core_io_regs_wakeupProgram_5_write_valid),
.io_regs_wakeupProgram_5_write_bits(core_io_regs_wakeupProgram_5_write_bits),
.io_regs_wakeupProgram_5_read(core_io_regs_wakeupProgram_5_read),
.io_regs_wakeupProgram_6_write_valid(core_io_regs_wakeupProgram_6_write_valid),
.io_regs_wakeupProgram_6_write_bits(core_io_regs_wakeupProgram_6_write_bits),
.io_regs_wakeupProgram_6_read(core_io_regs_wakeupProgram_6_read),
.io_regs_wakeupProgram_7_write_valid(core_io_regs_wakeupProgram_7_write_valid),
.io_regs_wakeupProgram_7_write_bits(core_io_regs_wakeupProgram_7_write_bits),
.io_regs_wakeupProgram_7_read(core_io_regs_wakeupProgram_7_read),
.io_regs_sleepProgram_0_write_valid(core_io_regs_sleepProgram_0_write_valid),
.io_regs_sleepProgram_0_write_bits(core_io_regs_sleepProgram_0_write_bits),
.io_regs_sleepProgram_0_read(core_io_regs_sleepProgram_0_read),
.io_regs_sleepProgram_1_write_valid(core_io_regs_sleepProgram_1_write_valid),
.io_regs_sleepProgram_1_write_bits(core_io_regs_sleepProgram_1_write_bits),
.io_regs_sleepProgram_1_read(core_io_regs_sleepProgram_1_read),
.io_regs_sleepProgram_2_write_valid(core_io_regs_sleepProgram_2_write_valid),
.io_regs_sleepProgram_2_write_bits(core_io_regs_sleepProgram_2_write_bits),
.io_regs_sleepProgram_2_read(core_io_regs_sleepProgram_2_read),
.io_regs_sleepProgram_3_write_valid(core_io_regs_sleepProgram_3_write_valid),
.io_regs_sleepProgram_3_write_bits(core_io_regs_sleepProgram_3_write_bits),
.io_regs_sleepProgram_3_read(core_io_regs_sleepProgram_3_read),
.io_regs_sleepProgram_4_write_valid(core_io_regs_sleepProgram_4_write_valid),
.io_regs_sleepProgram_4_write_bits(core_io_regs_sleepProgram_4_write_bits),
.io_regs_sleepProgram_4_read(core_io_regs_sleepProgram_4_read),
.io_regs_sleepProgram_5_write_valid(core_io_regs_sleepProgram_5_write_valid),
.io_regs_sleepProgram_5_write_bits(core_io_regs_sleepProgram_5_write_bits),
.io_regs_sleepProgram_5_read(core_io_regs_sleepProgram_5_read),
.io_regs_sleepProgram_6_write_valid(core_io_regs_sleepProgram_6_write_valid),
.io_regs_sleepProgram_6_write_bits(core_io_regs_sleepProgram_6_write_bits),
.io_regs_sleepProgram_6_read(core_io_regs_sleepProgram_6_read),
.io_regs_sleepProgram_7_write_valid(core_io_regs_sleepProgram_7_write_valid),
.io_regs_sleepProgram_7_write_bits(core_io_regs_sleepProgram_7_write_bits),
.io_regs_sleepProgram_7_read(core_io_regs_sleepProgram_7_read)
);
sirv_AsyncResetRegVec_1 AsyncResetRegVec_1_1 (
.clock(AsyncResetRegVec_1_1_clock),
.reset(AsyncResetRegVec_1_1_reset),
.io_d(AsyncResetRegVec_1_1_io_d),
.io_q(AsyncResetRegVec_1_1_io_q),
.io_en(AsyncResetRegVec_1_1_io_en)
);
//Bob: Since the SR Latch is not friend to the ASIC flow, so I just replace it to the DFF
// And the name as Latch is not good, so give it a new name here
wire por_reset = T_382;// POR
wire erst_reset = T_383;// ERST
wire wdog_reset = T_384;// WDOG
// In case we lost the reset, we need to just use two-dff syncer to catch up the reset, and until the clock
// is there to clear it
reg por_reset_r;
reg por_reset_r_r;
always @(posedge clock or posedge por_reset) begin
if(por_reset) begin
por_reset_r <= 1'b1;
por_reset_r_r <= 1'b1;
end
else begin
por_reset_r <= 1'b0;
por_reset_r_r <= por_reset_r;
end
end
reg erst_reset_r;
reg erst_reset_r_r;
always @(posedge clock or posedge erst_reset) begin
if(erst_reset) begin
erst_reset_r <= 1'b1;
erst_reset_r_r <= 1'b1;
end
else begin
erst_reset_r <= 1'b0;
erst_reset_r_r <= erst_reset_r;
end
end
reg wdog_reset_r;
reg wdog_reset_r_r;
always @(posedge clock or posedge wdog_reset) begin
if(wdog_reset) begin
wdog_reset_r <= 1'b1;
wdog_reset_r_r <= 1'b1;
end
else begin
wdog_reset_r <= 1'b0;
wdog_reset_r_r <= wdog_reset_r;
end
end
// Reset cause priority if they are coming at same time:
// POR
// Erst
// Wdog
wire rstcause_por_set = por_reset_r_r;
wire rstcause_erst_set = erst_reset_r_r & (~por_reset_r_r);
wire rstcause_wdog_set = wdog_reset_r_r & (~erst_reset_r_r) & (~por_reset_r_r);
// The POR only clear if:
// there is no POR reset,
// And there are other two resets
wire rstcause_por_clr = (~por_reset_r_r) & (erst_reset_r_r | wdog_reset_r_r);
// The Erst only clear if:
// there is POR reset,
// or, there is no erst reset and there is wdog reset
wire rstcause_erst_clr = por_reset_r_r | ((~erst_reset_r_r) & wdog_reset_r_r);
// The Wdog only clear if:
// there is POR or Erst reset,
wire rstcause_wdog_clr = por_reset_r_r | erst_reset_r_r;
wire rstcause_por_ena = rstcause_por_set | rstcause_por_clr ;
wire rstcause_erst_ena = rstcause_erst_set | rstcause_erst_clr;
wire rstcause_wdog_ena = rstcause_wdog_set | rstcause_wdog_clr;
wire rstcause_por_nxt = rstcause_por_set | (~rstcause_por_clr );
wire rstcause_erst_nxt = rstcause_erst_set | (~rstcause_erst_clr);
wire rstcause_wdog_nxt = rstcause_wdog_set | (~rstcause_wdog_clr);
reg rstcause_por_r;
reg rstcause_wdog_r;
reg rstcause_erst_r;
// The reset cause itself cannot have reset signal
always @(posedge clock) begin
if(rstcause_por_ena) begin
rstcause_por_r <= rstcause_por_nxt;
end
end
always @(posedge clock) begin
if(rstcause_erst_ena) begin
rstcause_erst_r <= rstcause_erst_nxt;
end
end
always @(posedge clock) begin
if(rstcause_wdog_ena) begin
rstcause_wdog_r <= rstcause_wdog_nxt;
end
end
//sirv_SRLatch SRLatch_3 ( // POR
// .q(SRLatch_3_q),
// .reset(SRLatch_3_reset),
// .set(SRLatch_3_set)
//);
//sirv_SRLatch SRLatch_1_1 (// ERST
// .q(SRLatch_1_1_q),
// .reset(SRLatch_1_1_reset),
// .set(SRLatch_1_1_set)
//);
//sirv_SRLatch SRLatch_2_1 (//WDOG
// .q(SRLatch_2_1_q),
// .reset(SRLatch_2_1_reset),
// .set(SRLatch_2_1_set)
//);
assign io_control_hfclkrst = T_369_hfclkrst;
assign io_control_corerst = T_369_corerst;
assign io_control_reserved1 = T_369_reserved1;
assign io_control_vddpaden = T_369_vddpaden;
assign io_control_reserved0 = T_369_reserved0;
assign io_regs_ie_read = core_io_regs_ie_read;
assign io_regs_cause_read = core_io_regs_cause_read;
assign io_regs_sleep_read = core_io_regs_sleep_read;
assign io_regs_key_read = core_io_regs_key_read;
assign io_regs_wakeupProgram_0_read = core_io_regs_wakeupProgram_0_read;
assign io_regs_wakeupProgram_1_read = core_io_regs_wakeupProgram_1_read;
assign io_regs_wakeupProgram_2_read = core_io_regs_wakeupProgram_2_read;
assign io_regs_wakeupProgram_3_read = core_io_regs_wakeupProgram_3_read;
assign io_regs_wakeupProgram_4_read = core_io_regs_wakeupProgram_4_read;
assign io_regs_wakeupProgram_5_read = core_io_regs_wakeupProgram_5_read;
assign io_regs_wakeupProgram_6_read = core_io_regs_wakeupProgram_6_read;
assign io_regs_wakeupProgram_7_read = core_io_regs_wakeupProgram_7_read;
assign io_regs_sleepProgram_0_read = core_io_regs_sleepProgram_0_read;
assign io_regs_sleepProgram_1_read = core_io_regs_sleepProgram_1_read;
assign io_regs_sleepProgram_2_read = core_io_regs_sleepProgram_2_read;
assign io_regs_sleepProgram_3_read = core_io_regs_sleepProgram_3_read;
assign io_regs_sleepProgram_4_read = core_io_regs_sleepProgram_4_read;
assign io_regs_sleepProgram_5_read = core_io_regs_sleepProgram_5_read;
assign io_regs_sleepProgram_6_read = core_io_regs_sleepProgram_6_read;
assign io_regs_sleepProgram_7_read = core_io_regs_sleepProgram_7_read;
assign core_clock = clock;
assign core_reset = T_356;
assign core_io_wakeup_awakeup = io_wakeup_awakeup;
assign core_io_wakeup_dwakeup = io_wakeup_dwakeup;
assign core_io_wakeup_rtc = io_wakeup_rtc;
assign core_io_wakeup_reset = 1'h0;
assign core_io_resetCause = T_402;
assign core_io_regs_ie_write_valid = io_regs_ie_write_valid;
assign core_io_regs_ie_write_bits = io_regs_ie_write_bits;
assign core_io_regs_cause_write_valid = io_regs_cause_write_valid;
assign core_io_regs_cause_write_bits = io_regs_cause_write_bits;
assign core_io_regs_sleep_write_valid = io_regs_sleep_write_valid;
assign core_io_regs_sleep_write_bits = io_regs_sleep_write_bits;
assign core_io_regs_key_write_valid = io_regs_key_write_valid;
assign core_io_regs_key_write_bits = io_regs_key_write_bits;
assign core_io_regs_wakeupProgram_0_write_valid = io_regs_wakeupProgram_0_write_valid;
assign core_io_regs_wakeupProgram_0_write_bits = io_regs_wakeupProgram_0_write_bits;
assign core_io_regs_wakeupProgram_1_write_valid = io_regs_wakeupProgram_1_write_valid;
assign core_io_regs_wakeupProgram_1_write_bits = io_regs_wakeupProgram_1_write_bits;
assign core_io_regs_wakeupProgram_2_write_valid = io_regs_wakeupProgram_2_write_valid;
assign core_io_regs_wakeupProgram_2_write_bits = io_regs_wakeupProgram_2_write_bits;
assign core_io_regs_wakeupProgram_3_write_valid = io_regs_wakeupProgram_3_write_valid;
assign core_io_regs_wakeupProgram_3_write_bits = io_regs_wakeupProgram_3_write_bits;
assign core_io_regs_wakeupProgram_4_write_valid = io_regs_wakeupProgram_4_write_valid;
assign core_io_regs_wakeupProgram_4_write_bits = io_regs_wakeupProgram_4_write_bits;
assign core_io_regs_wakeupProgram_5_write_valid = io_regs_wakeupProgram_5_write_valid;
assign core_io_regs_wakeupProgram_5_write_bits = io_regs_wakeupProgram_5_write_bits;
assign core_io_regs_wakeupProgram_6_write_valid = io_regs_wakeupProgram_6_write_valid;
assign core_io_regs_wakeupProgram_6_write_bits = io_regs_wakeupProgram_6_write_bits;
assign core_io_regs_wakeupProgram_7_write_valid = io_regs_wakeupProgram_7_write_valid;
assign core_io_regs_wakeupProgram_7_write_bits = io_regs_wakeupProgram_7_write_bits;
assign core_io_regs_sleepProgram_0_write_valid = io_regs_sleepProgram_0_write_valid;
assign core_io_regs_sleepProgram_0_write_bits = io_regs_sleepProgram_0_write_bits;
assign core_io_regs_sleepProgram_1_write_valid = io_regs_sleepProgram_1_write_valid;
assign core_io_regs_sleepProgram_1_write_bits = io_regs_sleepProgram_1_write_bits;
assign core_io_regs_sleepProgram_2_write_valid = io_regs_sleepProgram_2_write_valid;
assign core_io_regs_sleepProgram_2_write_bits = io_regs_sleepProgram_2_write_bits;
assign core_io_regs_sleepProgram_3_write_valid = io_regs_sleepProgram_3_write_valid;
assign core_io_regs_sleepProgram_3_write_bits = io_regs_sleepProgram_3_write_bits;
assign core_io_regs_sleepProgram_4_write_valid = io_regs_sleepProgram_4_write_valid;
assign core_io_regs_sleepProgram_4_write_bits = io_regs_sleepProgram_4_write_bits;
assign core_io_regs_sleepProgram_5_write_valid = io_regs_sleepProgram_5_write_valid;
assign core_io_regs_sleepProgram_5_write_bits = io_regs_sleepProgram_5_write_bits;
assign core_io_regs_sleepProgram_6_write_valid = io_regs_sleepProgram_6_write_valid;
assign core_io_regs_sleepProgram_6_write_bits = io_regs_sleepProgram_6_write_bits;
assign core_io_regs_sleepProgram_7_write_valid = io_regs_sleepProgram_7_write_valid;
assign core_io_regs_sleepProgram_7_write_bits = io_regs_sleepProgram_7_write_bits;
assign T_358 = {core_io_control_bits_vddpaden,core_io_control_bits_reserved0};
assign T_359 = {core_io_control_bits_hfclkrst,core_io_control_bits_corerst};
assign T_360 = {T_359,core_io_control_bits_reserved1};
assign T_361 = {T_360,T_358};
assign T_362 = ~ T_361;
assign AsyncResetRegVec_1_1_clock = clock;
assign AsyncResetRegVec_1_1_reset = reset;
assign AsyncResetRegVec_1_1_io_d = T_362;
assign AsyncResetRegVec_1_1_io_en = core_io_control_valid;
assign core_io_control_bits = ~ AsyncResetRegVec_1_1_io_q;
assign T_369_hfclkrst = T_379;
assign T_369_corerst = T_378;
assign T_369_reserved1 = T_377;
assign T_369_vddpaden = T_376;
assign T_369_reserved0 = T_375;
assign T_375 = core_io_control_bits[0];
assign T_376 = core_io_control_bits[1];
assign T_377 = core_io_control_bits[2];
assign T_378 = core_io_control_bits[3];
assign T_379 = core_io_control_bits[4];
assign T_380 = {io_resetCauses_wdogrst,io_resetCauses_erst};
assign T_381 = {T_380,io_resetCauses_porrst};
//assign SRLatch_3_reset = T_385;
//assign SRLatch_3_set = T_382;// POR
assign T_382 = T_381[0];// The POR
assign T_383 = T_381[1];// The ERST
assign T_384 = T_381[2];// The WDOG
assign T_385 = T_383 | T_384;
//assign SRLatch_1_1_reset = T_389;
//assign SRLatch_1_1_set = T_383;// ERST
assign T_389 = T_382 | T_384;
//assign SRLatch_2_1_reset = T_393;
//assign SRLatch_2_1_set = T_384;// WDOG
assign T_393 = T_382 | T_383;
//assign T_394 = {SRLatch_2_1_q,SRLatch_1_1_q};
//Bob assign T_395 = {T_394,SRLatch_3_q};
assign T_394 = {rstcause_wdog_r,rstcause_erst_r};
assign T_395 = {T_394,rstcause_por_r};
assign T_396 = T_395[2];
assign T_397 = T_395[1:0];
assign GEN_0 = {{1'd0}, T_396};
assign T_400 = GEN_0 | T_397;
assign T_401 = T_400[1];
assign T_402 = {T_396,T_401};
//Bob: The original code is here
//always @(posedge clock) begin
// T_355 <= reset;
// T_356 <= T_355;
//end
//Bob: Why here need to flop the reset twice? this is not allowed in coding style so just comment it out
always @(posedge clock or posedge reset) begin
if(reset) begin
T_355 <= 1'b1;
T_356 <= T_355;
end
else begin
T_355 <= 1'b0;
T_356 <= T_355;
end
end
endmodule
|
module sirv_hclkgen_regs(
input clk,
input rst_n,
output pllbypass ,
output pll_RESET ,
output pll_ASLEEP ,
output [1:0] pll_OD,
output [7:0] pll_M,
output [4:0] pll_N,
output plloutdivby1,
output [5:0] plloutdiv,
output hfxoscen,
input i_icb_cmd_valid,
output i_icb_cmd_ready,
input [12-1:0] i_icb_cmd_addr,
input i_icb_cmd_read,
input [32-1:0] i_icb_cmd_wdata,
output i_icb_rsp_valid,
input i_icb_rsp_ready,
output [32-1:0] i_icb_rsp_rdata
);
// Directly connect the command channel with response channel
assign i_icb_rsp_valid = i_icb_cmd_valid;
assign i_icb_cmd_ready = i_icb_rsp_ready;
wire icb_wr_en = i_icb_cmd_valid & i_icb_cmd_ready & (~i_icb_cmd_read);
wire [32-1:0] icb_wdata = i_icb_cmd_wdata;
wire [32-1:0] hfxosccfg_r;
wire [32-1:0] pllcfg_r;
wire [32-1:0] plloutdiv_r;
// Addr selection
wire sel_hfxosccfg = (i_icb_cmd_addr == 12'h004);
wire sel_pllcfg = (i_icb_cmd_addr == 12'h008);
wire sel_plloutdiv = (i_icb_cmd_addr == 12'h00C);
wire icb_wr_en_hfxosccfg = icb_wr_en & sel_hfxosccfg ;
wire icb_wr_en_pllcfg = icb_wr_en & sel_pllcfg ;
wire icb_wr_en_plloutdiv = icb_wr_en & sel_plloutdiv ;
assign i_icb_rsp_rdata =
({32{sel_hfxosccfg}} & hfxosccfg_r)
| ({32{sel_pllcfg }} & pllcfg_r )
| ({32{sel_plloutdiv}} & plloutdiv_r);
/////////////////////////////////////////////////////////////////////////////////////////
// HFXOSCCFG
wire hfxoscen_ena = icb_wr_en_hfxosccfg;
// The reset value is 1
sirv_gnrl_dfflrs #(1) hfxoscen_dfflrs (hfxoscen_ena, icb_wdata[30], hfxoscen, clk, rst_n);
assign hfxosccfg_r = {1'b0, hfxoscen, 30'b0};
/////////////////////////////////////////////////////////////////////////////////////////
// PLLCFG
//
// N: The reset value is 2 = 5'h2 = 5'b0_0010
sirv_gnrl_dfflr #(3) pll_N_42_dfflr (icb_wr_en_pllcfg, icb_wdata[4:2], pll_N[4:2], clk, rst_n);
sirv_gnrl_dfflrs#(1) pll_N_1_dfflr (icb_wr_en_pllcfg, icb_wdata[1], pll_N[1], clk, rst_n);
sirv_gnrl_dfflr #(1) pll_N_0_dfflr (icb_wr_en_pllcfg, icb_wdata[0], pll_N[0], clk, rst_n);
//
// M: The reset value is 50 = 8'h32 = 8'b0011_0010
sirv_gnrl_dfflr #(1) pll_M_7_dfflr (icb_wr_en_pllcfg, icb_wdata[12], pll_M[7], clk, rst_n);
sirv_gnrl_dfflr #(1) pll_M_6_dfflr (icb_wr_en_pllcfg, icb_wdata[11], pll_M[6], clk, rst_n);
sirv_gnrl_dfflrs#(1) pll_M_5_dfflr (icb_wr_en_pllcfg, icb_wdata[10], pll_M[5], clk, rst_n);
sirv_gnrl_dfflrs#(1) pll_M_4_dfflr (icb_wr_en_pllcfg, icb_wdata[09], pll_M[4], clk, rst_n);
sirv_gnrl_dfflr #(1) pll_M_3_dfflr (icb_wr_en_pllcfg, icb_wdata[08], pll_M[3], clk, rst_n);
sirv_gnrl_dfflr #(1) pll_M_2_dfflr (icb_wr_en_pllcfg, icb_wdata[07], pll_M[2], clk, rst_n);
sirv_gnrl_dfflrs#(1) pll_M_1_dfflr (icb_wr_en_pllcfg, icb_wdata[06], pll_M[1], clk, rst_n);
sirv_gnrl_dfflr #(1) pll_M_0_dfflr (icb_wr_en_pllcfg, icb_wdata[05], pll_M[0], clk, rst_n);
// OD: The reset value is 2 = 2'b10
sirv_gnrl_dfflrs #(1) pll_OD_1_dfflrs(icb_wr_en_pllcfg, icb_wdata[14], pll_OD[1], clk, rst_n);
sirv_gnrl_dfflr #(1) pll_OD_0_dfflr (icb_wr_en_pllcfg, icb_wdata[13], pll_OD[0], clk, rst_n);
// Bypass: The reset value is 1
sirv_gnrl_dfflrs #(1) pllbypass_dfflrs (icb_wr_en_pllcfg, icb_wdata[18], pllbypass, clk, rst_n);
// RESET: The reset value is 0
sirv_gnrl_dfflr #(1) pll_RESET_dfflrs (icb_wr_en_pllcfg, icb_wdata[30], pll_RESET, clk, rst_n);
// ASLEEP: The asleep value is 0
sirv_gnrl_dfflr #(1) pll_ASLEEP_dfflrs (icb_wr_en_pllcfg, icb_wdata[29], pll_ASLEEP, clk, rst_n);
assign pllcfg_r[31] = 1'b0;
assign pllcfg_r[30] = pll_RESET;
assign pllcfg_r[29] = pll_ASLEEP;
assign pllcfg_r[28:19] = 10'b0;
assign pllcfg_r[18] = pllbypass;
assign pllcfg_r[17:15] = 3'b0;
assign pllcfg_r[14:13] = pll_OD;
assign pllcfg_r[12:5] = pll_M;
assign pllcfg_r[4:0] = pll_N;
/////////////////////////////////////////////////////////////////////////////////////////
// PLLOUTDIV
//
wire plloutdiv_ena = icb_wr_en_plloutdiv;
sirv_gnrl_dfflr #(6) plloutdiv_dfflr (plloutdiv_ena, icb_wdata[5:0], plloutdiv, clk, rst_n);
wire plloutdivby1_ena = icb_wr_en_plloutdiv;
// The reset value is 1
sirv_gnrl_dfflrs #(1) plloutdivby1_dfflrs (plloutdivby1_ena, icb_wdata[8], plloutdivby1, clk, rst_n);
assign plloutdiv_r[31:9] = 23'b0;
assign plloutdiv_r[8] = plloutdivby1;
assign plloutdiv_r[7:6] = 2'b0;
assign plloutdiv_r[5:0] = plloutdiv;
endmodule
|
module sirv_rtc(
input clock,
input reset,
input io_regs_cfg_write_valid,
input [31:0] io_regs_cfg_write_bits,
output [31:0] io_regs_cfg_read,
input io_regs_countLo_write_valid,
input [31:0] io_regs_countLo_write_bits,
output [31:0] io_regs_countLo_read,
input io_regs_countHi_write_valid,
input [31:0] io_regs_countHi_write_bits,
output [31:0] io_regs_countHi_read,
input io_regs_s_write_valid,
input [31:0] io_regs_s_write_bits,
output [31:0] io_regs_s_read,
input io_regs_cmp_0_write_valid,
input [31:0] io_regs_cmp_0_write_bits,
output [31:0] io_regs_cmp_0_read,
input io_regs_feed_write_valid,
input [31:0] io_regs_feed_write_bits,
output [31:0] io_regs_feed_read,
input io_regs_key_write_valid,
input [31:0] io_regs_key_write_bits,
output [31:0] io_regs_key_read,
output io_ip_0
);
wire [3:0] T_134;
reg [3:0] scale;
reg [31:0] GEN_7;
wire [3:0] GEN_0;
reg [31:0] cmp_0;
reg [31:0] GEN_8;
wire [31:0] GEN_1;
wire T_141;
wire AsyncResetRegVec_1_clock;
wire AsyncResetRegVec_1_reset;
wire AsyncResetRegVec_1_io_d;
wire AsyncResetRegVec_1_io_q;
wire AsyncResetRegVec_1_io_en;
wire countAlways;
reg [5:0] T_145;
reg [31:0] GEN_10;
wire [5:0] GEN_9;
wire [6:0] T_146;
reg [41:0] T_148;
reg [63:0] GEN_11;
wire T_149;
wire [42:0] T_151;
wire [42:0] GEN_2;
wire [47:0] T_152;
wire [15:0] T_155;
wire [47:0] T_156;
wire [41:0] T_157;
wire [47:0] GEN_3;
wire [42:0] GEN_4;
wire [31:0] T_160;
wire [63:0] T_161;
wire [57:0] T_162;
wire [63:0] GEN_5;
wire [57:0] GEN_6;
wire [47:0] T_163;
wire [31:0] s;
wire elapsed_0;
reg ip;
reg [31:0] GEN_12;
wire [8:0] T_191;
wire [11:0] T_194;
wire [3:0] T_196;
wire [4:0] T_198;
wire [12:0] T_199;
wire [16:0] T_200;
wire [28:0] T_201;
wire T_207_0;
sirv_AsyncResetRegVec AsyncResetRegVec_1 (
.clock(AsyncResetRegVec_1_clock),
.reset(AsyncResetRegVec_1_reset),
.io_d(AsyncResetRegVec_1_io_d),
.io_q(AsyncResetRegVec_1_io_q),
.io_en(AsyncResetRegVec_1_io_en)
);
assign io_regs_cfg_read = {{3'd0}, T_201};
assign io_regs_countLo_read = T_152[31:0];
assign io_regs_countHi_read = {{16'd0}, T_155};
assign io_regs_s_read = s;
assign io_regs_cmp_0_read = cmp_0;
assign io_regs_feed_read = 32'h0;
assign io_regs_key_read = 32'h1;
assign io_ip_0 = T_207_0;
assign T_134 = io_regs_cfg_write_bits[3:0];
assign GEN_0 = io_regs_cfg_write_valid ? T_134 : scale;
assign GEN_1 = io_regs_cmp_0_write_valid ? io_regs_cmp_0_write_bits : cmp_0;
assign T_141 = io_regs_cfg_write_bits[12];
assign AsyncResetRegVec_1_clock = clock;
assign AsyncResetRegVec_1_reset = reset;
assign AsyncResetRegVec_1_io_d = T_141;
assign AsyncResetRegVec_1_io_en = io_regs_cfg_write_valid;
assign countAlways = AsyncResetRegVec_1_io_q;
assign GEN_9 = {{5'd0}, countAlways};
assign T_146 = T_145 + GEN_9;
assign T_149 = T_146[6];
assign T_151 = T_148 + 42'h1;
assign GEN_2 = T_149 ? T_151 : {{1'd0}, T_148};
assign T_152 = {T_148,T_145};
assign T_155 = T_152[47:32];
assign T_156 = {T_155,io_regs_countLo_write_bits};
assign T_157 = T_156[47:6];
assign GEN_3 = io_regs_countLo_write_valid ? T_156 : {{41'd0}, T_146};
assign GEN_4 = io_regs_countLo_write_valid ? {{1'd0}, T_157} : GEN_2;
assign T_160 = T_152[31:0];
assign T_161 = {io_regs_countHi_write_bits,T_160};
assign T_162 = T_161[63:6];
assign GEN_5 = io_regs_countHi_write_valid ? T_161 : {{16'd0}, GEN_3};
assign GEN_6 = io_regs_countHi_write_valid ? T_162 : {{15'd0}, GEN_4};
assign T_163 = T_152 >> scale;
assign s = T_163[31:0];
assign elapsed_0 = s >= cmp_0;
assign T_191 = {5'h0,scale};
assign T_194 = {3'h0,T_191};
assign T_196 = {3'h0,countAlways};
assign T_198 = {ip,4'h0};
assign T_199 = {T_198,8'h0};
assign T_200 = {T_199,T_196};
assign T_201 = {T_200,T_194};
assign T_207_0 = ip;
always @(posedge clock or posedge reset) begin
if(reset) begin
scale <= 4'b0;
cmp_0 <= 32'hFFFF_FFFF;
T_145 <= 6'b0;
T_148 <= 42'b0;
ip <= 1'b0;
end
else begin
if (io_regs_cfg_write_valid) begin
scale <= T_134;
end
if (io_regs_cmp_0_write_valid) begin
cmp_0 <= io_regs_cmp_0_write_bits;
end
T_145 <= GEN_5[5:0];
T_148 <= GEN_6[41:0];
ip <= elapsed_0;
end
end
endmodule
|
module sirv_qspi_physical_1(
input clock,
input reset,
output io_port_sck,
input io_port_dq_0_i,
output io_port_dq_0_o,
output io_port_dq_0_oe,
input io_port_dq_1_i,
output io_port_dq_1_o,
output io_port_dq_1_oe,
input io_port_dq_2_i,
output io_port_dq_2_o,
output io_port_dq_2_oe,
input io_port_dq_3_i,
output io_port_dq_3_o,
output io_port_dq_3_oe,
output io_port_cs_0,
output io_port_cs_1,
output io_port_cs_2,
output io_port_cs_3,
input [11:0] io_ctrl_sck_div,
input io_ctrl_sck_pol,
input io_ctrl_sck_pha,
input [1:0] io_ctrl_fmt_proto,
input io_ctrl_fmt_endian,
input io_ctrl_fmt_iodir,
output io_op_ready,
input io_op_valid,
input io_op_bits_fn,
input io_op_bits_stb,
input [7:0] io_op_bits_cnt,
input [7:0] io_op_bits_data,
output io_rx_valid,
output [7:0] io_rx_bits
);
reg [11:0] ctrl_sck_div;
reg [31:0] GEN_2;
reg ctrl_sck_pol;
reg [31:0] GEN_31;
reg ctrl_sck_pha;
reg [31:0] GEN_52;
reg [1:0] ctrl_fmt_proto;
reg [31:0] GEN_67;
reg ctrl_fmt_endian;
reg [31:0] GEN_68;
reg ctrl_fmt_iodir;
reg [31:0] GEN_69;
wire proto_0;
wire proto_1;
wire proto_2;
wire accept;
wire sample;
wire setup;
wire last;
reg setup_d;
reg [31:0] GEN_70;
reg T_119;
reg [31:0] GEN_71;
reg T_120;
reg [31:0] GEN_72;
reg sample_d;
reg [31:0] GEN_73;
reg T_122;
reg [31:0] GEN_74;
reg T_123;
reg [31:0] GEN_75;
reg last_d;
reg [31:0] GEN_76;
reg [7:0] scnt;
reg [31:0] GEN_77;
reg [11:0] tcnt;
reg [31:0] GEN_78;
wire stop;
wire beat;
wire [11:0] T_127;
wire [12:0] T_129;
wire [11:0] decr;
wire sched;
wire [11:0] T_130;
reg sck;
reg [31:0] GEN_79;
reg cref;
reg [31:0] GEN_80;
wire cinv;
wire [1:0] T_133;
wire [1:0] T_134;
wire [3:0] rxd;
wire samples_0;
wire [1:0] samples_1;
reg [7:0] buffer;
reg [31:0] GEN_81;
wire T_135;
wire T_136;
wire T_137;
wire T_138;
wire T_139;
wire T_140;
wire T_141;
wire T_142;
wire T_143;
wire [1:0] T_144;
wire [1:0] T_145;
wire [3:0] T_146;
wire [1:0] T_147;
wire [1:0] T_148;
wire [3:0] T_149;
wire [7:0] T_150;
wire [7:0] buffer_in;
wire T_151;
wire shift;
wire [6:0] T_152;
wire [6:0] T_153;
wire [6:0] T_154;
wire T_155;
wire T_157;
wire [7:0] T_158;
wire [5:0] T_159;
wire [5:0] T_160;
wire [5:0] T_161;
wire [1:0] T_162;
wire [1:0] T_163;
wire [7:0] T_164;
wire [3:0] T_165;
wire [3:0] T_166;
wire [3:0] T_167;
wire [3:0] T_169;
wire [7:0] T_170;
wire [7:0] T_172;
wire [7:0] T_174;
wire [7:0] T_176;
wire [7:0] T_178;
wire [7:0] T_179;
wire [7:0] T_180;
reg [3:0] txd;
reg [31:0] GEN_82;
wire [3:0] T_182;
wire [3:0] txd_in;
wire [1:0] T_184;
wire txd_sel_0;
wire txd_sel_1;
wire txd_sel_2;
wire txd_shf_0;
wire [1:0] txd_shf_1;
wire T_186;
wire [1:0] T_188;
wire [3:0] T_190;
wire [1:0] GEN_65;
wire [1:0] T_192;
wire [3:0] GEN_66;
wire [3:0] T_193;
wire [3:0] T_194;
wire [3:0] GEN_0;
wire T_195;
wire T_196;
wire txen_1;
wire txen_0;
wire T_208_0;
wire T_208_1;
wire T_208_2;
wire T_208_3;
wire T_215;
wire T_216;
wire T_217;
wire T_218;
reg done;
reg [31:0] GEN_83;
wire T_221;
wire T_222;
wire T_224;
wire T_225;
wire T_226;
wire T_227;
wire T_228;
wire T_229;
wire T_230;
wire [1:0] T_231;
wire [1:0] T_232;
wire [3:0] T_233;
wire [1:0] T_234;
wire [1:0] T_235;
wire [3:0] T_236;
wire [7:0] T_237;
wire [7:0] T_238;
reg xfr;
reg [31:0] GEN_84;
wire GEN_1;
wire T_243;
wire T_245;
wire T_246;
wire GEN_3;
wire GEN_4;
wire GEN_5;
wire [11:0] GEN_6;
wire GEN_7;
wire GEN_8;
wire GEN_9;
wire GEN_10;
wire [11:0] GEN_11;
wire GEN_12;
wire GEN_13;
wire GEN_14;
wire GEN_15;
wire [11:0] GEN_16;
wire T_252;
wire T_253;
wire T_254;
wire T_257;
wire GEN_17;
wire GEN_18;
wire GEN_19;
wire GEN_20;
wire GEN_21;
wire GEN_22;
wire GEN_23;
wire T_260;
wire [1:0] GEN_24;
wire GEN_25;
wire GEN_26;
wire T_263;
wire T_266;
wire [7:0] GEN_27;
wire GEN_28;
wire GEN_29;
wire GEN_30;
wire GEN_32;
wire [11:0] GEN_33;
wire GEN_34;
wire GEN_35;
wire GEN_36;
wire [11:0] GEN_37;
wire GEN_38;
wire GEN_39;
wire [11:0] GEN_40;
wire [1:0] GEN_41;
wire GEN_42;
wire GEN_43;
wire GEN_44;
wire [7:0] GEN_45;
wire GEN_46;
wire GEN_47;
wire GEN_48;
wire [11:0] GEN_49;
wire GEN_50;
wire GEN_51;
wire [11:0] GEN_53;
wire [1:0] GEN_54;
wire GEN_55;
wire GEN_56;
wire GEN_57;
wire [7:0] GEN_58;
wire GEN_59;
wire GEN_60;
wire GEN_61;
wire [11:0] GEN_62;
wire GEN_63;
wire GEN_64;
assign io_port_sck = sck;
assign io_port_dq_0_o = T_215;
assign io_port_dq_0_oe = txen_0;
assign io_port_dq_1_o = T_216;
assign io_port_dq_1_oe = txen_1;
assign io_port_dq_2_o = T_217;
assign io_port_dq_2_oe = T_196;
assign io_port_dq_3_o = T_218;
assign io_port_dq_3_oe = 1'h0;
assign io_port_cs_0 = T_208_0;
assign io_port_cs_1 = T_208_1;
assign io_port_cs_2 = T_208_2;
assign io_port_cs_3 = T_208_3;
assign io_op_ready = T_260;
assign io_rx_valid = done;
assign io_rx_bits = T_238;
assign proto_0 = 2'h0 == ctrl_fmt_proto;
assign proto_1 = 2'h1 == ctrl_fmt_proto;
assign proto_2 = 2'h2 == ctrl_fmt_proto;
assign accept = GEN_21;
assign sample = GEN_14;
assign setup = GEN_60;
assign last = GEN_20;
assign stop = scnt == 8'h0;
assign beat = tcnt == 12'h0;
assign T_127 = beat ? {{4'd0}, scnt} : tcnt;
assign T_129 = T_127 - 12'h1;
assign decr = T_129[11:0];
assign sched = GEN_1;
assign T_130 = sched ? ctrl_sck_div : decr;
assign cinv = ctrl_sck_pha ^ ctrl_sck_pol;
assign T_133 = {io_port_dq_1_i,io_port_dq_0_i};
assign T_134 = {io_port_dq_3_i,io_port_dq_2_i};
assign rxd = {T_134,T_133};
assign samples_0 = rxd[1];
assign samples_1 = rxd[1:0];
assign T_135 = io_ctrl_fmt_endian == 1'h0;
assign T_136 = io_op_bits_data[0];
assign T_137 = io_op_bits_data[1];
assign T_138 = io_op_bits_data[2];
assign T_139 = io_op_bits_data[3];
assign T_140 = io_op_bits_data[4];
assign T_141 = io_op_bits_data[5];
assign T_142 = io_op_bits_data[6];
assign T_143 = io_op_bits_data[7];
assign T_144 = {T_142,T_143};
assign T_145 = {T_140,T_141};
assign T_146 = {T_145,T_144};
assign T_147 = {T_138,T_139};
assign T_148 = {T_136,T_137};
assign T_149 = {T_148,T_147};
assign T_150 = {T_149,T_146};
assign buffer_in = T_135 ? io_op_bits_data : T_150;
assign T_151 = sample_d & stop;
assign shift = setup_d | T_151;
assign T_152 = buffer[6:0];
assign T_153 = buffer[7:1];
assign T_154 = shift ? T_152 : T_153;
assign T_155 = buffer[0];
assign T_157 = sample_d ? samples_0 : T_155;
assign T_158 = {T_154,T_157};
assign T_159 = buffer[5:0];
assign T_160 = buffer[7:2];
assign T_161 = shift ? T_159 : T_160;
assign T_162 = buffer[1:0];
assign T_163 = sample_d ? samples_1 : T_162;
assign T_164 = {T_161,T_163};
assign T_165 = buffer[3:0];
assign T_166 = buffer[7:4];
assign T_167 = shift ? T_165 : T_166;
assign T_169 = sample_d ? rxd : T_165;
assign T_170 = {T_167,T_169};
assign T_172 = proto_0 ? T_158 : 8'h0;
assign T_174 = proto_1 ? T_164 : 8'h0;
assign T_176 = proto_2 ? T_170 : 8'h0;
assign T_178 = T_172 | T_174;
assign T_179 = T_178 | T_176;
assign T_180 = T_179;
assign T_182 = buffer_in[7:4];
assign txd_in = accept ? T_182 : T_166;
assign T_184 = accept ? io_ctrl_fmt_proto : ctrl_fmt_proto;
assign txd_sel_0 = 2'h0 == T_184;
assign txd_sel_1 = 2'h1 == T_184;
assign txd_sel_2 = 2'h2 == T_184;
assign txd_shf_0 = txd_in[3];
assign txd_shf_1 = txd_in[3:2];
assign T_186 = txd_sel_0 ? txd_shf_0 : 1'h0;
assign T_188 = txd_sel_1 ? txd_shf_1 : 2'h0;
assign T_190 = txd_sel_2 ? txd_in : 4'h0;
assign GEN_65 = {{1'd0}, T_186};
assign T_192 = GEN_65 | T_188;
assign GEN_66 = {{2'd0}, T_192};
assign T_193 = GEN_66 | T_190;
assign T_194 = T_193;
assign GEN_0 = setup ? T_194 : txd;
assign T_195 = proto_1 & ctrl_fmt_iodir;
assign T_196 = proto_2 & ctrl_fmt_iodir;
assign txen_1 = T_195 | T_196;
assign txen_0 = proto_0 | txen_1;
assign T_208_0 = 1'h1;
assign T_208_1 = 1'h1;
assign T_208_2 = 1'h1;
assign T_208_3 = 1'h1;
assign T_215 = txd[0];
assign T_216 = txd[1];
assign T_217 = txd[2];
assign T_218 = txd[3];
assign T_221 = done | last_d;
assign T_222 = ctrl_fmt_endian == 1'h0;
assign T_224 = buffer[1];
assign T_225 = buffer[2];
assign T_226 = buffer[3];
assign T_227 = buffer[4];
assign T_228 = buffer[5];
assign T_229 = buffer[6];
assign T_230 = buffer[7];
assign T_231 = {T_229,T_230};
assign T_232 = {T_227,T_228};
assign T_233 = {T_232,T_231};
assign T_234 = {T_225,T_226};
assign T_235 = {T_155,T_224};
assign T_236 = {T_235,T_234};
assign T_237 = {T_236,T_233};
assign T_238 = T_222 ? buffer : T_237;
assign GEN_1 = stop ? 1'h1 : beat;
assign T_243 = stop == 1'h0;
assign T_245 = cref == 1'h0;
assign T_246 = cref ^ cinv;
assign GEN_3 = xfr ? T_246 : sck;
assign GEN_4 = xfr ? cref : 1'h0;
assign GEN_5 = xfr ? T_245 : 1'h0;
assign GEN_6 = T_245 ? decr : {{4'd0}, scnt};
assign GEN_7 = beat ? T_245 : cref;
assign GEN_8 = beat ? GEN_3 : sck;
assign GEN_9 = beat ? GEN_4 : 1'h0;
assign GEN_10 = beat ? GEN_5 : 1'h0;
assign GEN_11 = beat ? GEN_6 : {{4'd0}, scnt};
assign GEN_12 = T_243 ? GEN_7 : cref;
assign GEN_13 = T_243 ? GEN_8 : sck;
assign GEN_14 = T_243 ? GEN_9 : 1'h0;
assign GEN_15 = T_243 ? GEN_10 : 1'h0;
assign GEN_16 = T_243 ? GEN_11 : {{4'd0}, scnt};
assign T_252 = scnt == 8'h1;
assign T_253 = beat & cref;
assign T_254 = T_253 & xfr;
assign T_257 = beat & T_245;
assign GEN_17 = T_257 ? 1'h1 : stop;
assign GEN_18 = T_257 ? 1'h0 : GEN_15;
assign GEN_19 = T_257 ? ctrl_sck_pol : GEN_13;
assign GEN_20 = T_252 ? T_254 : 1'h0;
assign GEN_21 = T_252 ? GEN_17 : stop;
assign GEN_22 = T_252 ? GEN_18 : GEN_15;
assign GEN_23 = T_252 ? GEN_19 : GEN_13;
assign T_260 = accept & done;
assign GEN_24 = io_op_bits_stb ? io_ctrl_fmt_proto : ctrl_fmt_proto;
assign GEN_25 = io_op_bits_stb ? io_ctrl_fmt_endian : ctrl_fmt_endian;
assign GEN_26 = io_op_bits_stb ? io_ctrl_fmt_iodir : ctrl_fmt_iodir;
assign T_263 = 1'h0 == io_op_bits_fn;
assign T_266 = io_op_bits_cnt == 8'h0;
assign GEN_27 = T_263 ? buffer_in : T_180;
assign GEN_28 = T_263 ? cinv : GEN_23;
assign GEN_29 = T_263 ? 1'h1 : GEN_22;
assign GEN_30 = T_263 ? T_266 : T_221;
assign GEN_32 = io_op_bits_stb ? io_ctrl_sck_pol : GEN_28;
assign GEN_33 = io_op_bits_stb ? io_ctrl_sck_div : ctrl_sck_div;
assign GEN_34 = io_op_bits_stb ? io_ctrl_sck_pol : ctrl_sck_pol;
assign GEN_35 = io_op_bits_stb ? io_ctrl_sck_pha : ctrl_sck_pha;
assign GEN_36 = io_op_bits_fn ? GEN_32 : GEN_28;
assign GEN_37 = io_op_bits_fn ? GEN_33 : ctrl_sck_div;
assign GEN_38 = io_op_bits_fn ? GEN_34 : ctrl_sck_pol;
assign GEN_39 = io_op_bits_fn ? GEN_35 : ctrl_sck_pha;
assign GEN_40 = io_op_valid ? {{4'd0}, io_op_bits_cnt} : GEN_16;
assign GEN_41 = io_op_valid ? GEN_24 : ctrl_fmt_proto;
assign GEN_42 = io_op_valid ? GEN_25 : ctrl_fmt_endian;
assign GEN_43 = io_op_valid ? GEN_26 : ctrl_fmt_iodir;
assign GEN_44 = io_op_valid ? T_263 : xfr;
assign GEN_45 = io_op_valid ? GEN_27 : T_180;
assign GEN_46 = io_op_valid ? GEN_36 : GEN_23;
assign GEN_47 = io_op_valid ? GEN_29 : GEN_22;
assign GEN_48 = io_op_valid ? GEN_30 : T_221;
assign GEN_49 = io_op_valid ? GEN_37 : ctrl_sck_div;
assign GEN_50 = io_op_valid ? GEN_38 : ctrl_sck_pol;
assign GEN_51 = io_op_valid ? GEN_39 : ctrl_sck_pha;
assign GEN_53 = T_260 ? GEN_40 : GEN_16;
assign GEN_54 = T_260 ? GEN_41 : ctrl_fmt_proto;
assign GEN_55 = T_260 ? GEN_42 : ctrl_fmt_endian;
assign GEN_56 = T_260 ? GEN_43 : ctrl_fmt_iodir;
assign GEN_57 = T_260 ? GEN_44 : xfr;
assign GEN_58 = T_260 ? GEN_45 : T_180;
assign GEN_59 = T_260 ? GEN_46 : GEN_23;
assign GEN_60 = T_260 ? GEN_47 : GEN_22;
assign GEN_61 = T_260 ? GEN_48 : T_221;
assign GEN_62 = T_260 ? GEN_49 : ctrl_sck_div;
assign GEN_63 = T_260 ? GEN_50 : ctrl_sck_pol;
assign GEN_64 = T_260 ? GEN_51 : ctrl_sck_pha;
always @(posedge clock or posedge reset)
if (reset) begin
ctrl_sck_div <= 12'b0;
ctrl_sck_pol <= 1'b0;
ctrl_sck_pha <= 1'b0;
ctrl_fmt_proto <= 2'b0;
ctrl_fmt_endian <= 1'b0;
ctrl_fmt_iodir <= 1'b0;
setup_d <= 1'b0;
tcnt <= 12'b0;
sck <= 1'b0;
buffer <= 8'b0;
xfr <= 1'b0;
end
else begin
if (T_260) begin
if (io_op_valid) begin
if (io_op_bits_fn) begin
if (io_op_bits_stb) begin
ctrl_sck_div <= io_ctrl_sck_div;
end
end
end
end
if (T_260) begin
if (io_op_valid) begin
if (io_op_bits_fn) begin
if (io_op_bits_stb) begin
ctrl_sck_pol <= io_ctrl_sck_pol;
end
end
end
end
if (T_260) begin
if (io_op_valid) begin
if (io_op_bits_fn) begin
if (io_op_bits_stb) begin
ctrl_sck_pha <= io_ctrl_sck_pha;
end
end
end
end
if (T_260) begin
if (io_op_valid) begin
if (io_op_bits_stb) begin
ctrl_fmt_proto <= io_ctrl_fmt_proto;
end
end
end
if (T_260) begin
if (io_op_valid) begin
if (io_op_bits_stb) begin
ctrl_fmt_endian <= io_ctrl_fmt_endian;
end
end
end
if (T_260) begin
if (io_op_valid) begin
if (io_op_bits_stb) begin
ctrl_fmt_iodir <= io_ctrl_fmt_iodir;
end
end
end
setup_d <= setup;
if (sched) begin
tcnt <= ctrl_sck_div;
end else begin
tcnt <= decr;
end
if (T_260) begin
if (io_op_valid) begin
if (io_op_bits_fn) begin
if (io_op_bits_stb) begin
sck <= io_ctrl_sck_pol;
end else begin
if (T_263) begin
sck <= cinv;
end else begin
if (T_252) begin
if (T_257) begin
sck <= ctrl_sck_pol;
end else begin
if (T_243) begin
if (beat) begin
if (xfr) begin
sck <= T_246;
end
end
end
end
end else begin
if (T_243) begin
if (beat) begin
if (xfr) begin
sck <= T_246;
end
end
end
end
end
end
end else begin
if (T_263) begin
sck <= cinv;
end else begin
if (T_252) begin
if (T_257) begin
sck <= ctrl_sck_pol;
end else begin
if (T_243) begin
if (beat) begin
if (xfr) begin
sck <= T_246;
end
end
end
end
end else begin
if (T_243) begin
if (beat) begin
if (xfr) begin
sck <= T_246;
end
end
end
end
end
end
end else begin
if (T_252) begin
if (T_257) begin
sck <= ctrl_sck_pol;
end else begin
sck <= GEN_13;
end
end else begin
sck <= GEN_13;
end
end
end else begin
if (T_252) begin
if (T_257) begin
sck <= ctrl_sck_pol;
end else begin
sck <= GEN_13;
end
end else begin
sck <= GEN_13;
end
end
if (T_260) begin
if (io_op_valid) begin
if (T_263) begin
if (T_135) begin
buffer <= io_op_bits_data;
end else begin
buffer <= T_150;
end
end else begin
buffer <= T_180;
end
end else begin
buffer <= T_180;
end
end else begin
buffer <= T_180;
end
if (T_260) begin
if (io_op_valid) begin
xfr <= T_263;
end
end
end
always @(posedge clock or posedge reset)
if (reset) begin
cref <= 1'h1;
end else begin
if (T_243) begin
if (beat) begin
cref <= T_245;
end
end
end
always @(posedge clock or posedge reset)
if (reset) begin
txd <= 4'h0;
end else begin
if (setup) begin
txd <= T_194;
end
end
always @(posedge clock or posedge reset)
if (reset) begin
done <= 1'h1;
end else begin
if (T_260) begin
if (io_op_valid) begin
if (T_263) begin
done <= T_266;
end else begin
done <= T_221;
end
end else begin
done <= T_221;
end
end else begin
done <= T_221;
end
end
always @(posedge clock or posedge reset)
if (reset) begin
T_119 <= 1'h0;
end else begin
T_119 <= sample;
end
always @(posedge clock or posedge reset)
if (reset) begin
T_120 <= 1'h0;
end else begin
T_120 <= T_119;
end
always @(posedge clock or posedge reset)
if (reset) begin
sample_d <= 1'h0;
end else begin
sample_d <= T_120;
end
always @(posedge clock or posedge reset)
if (reset) begin
T_122 <= 1'h0;
end else begin
T_122 <= last;
end
always @(posedge clock or posedge reset)
if (reset) begin
T_123 <= 1'h0;
end else begin
T_123 <= T_122;
end
always @(posedge clock or posedge reset)
if (reset) begin
last_d <= 1'h0;
end else begin
last_d <= T_123;
end
always @(posedge clock or posedge reset)
if (reset) begin
scnt <= 8'h0;
end else begin
scnt <= GEN_53[7:0];
end
endmodule
|
module e203_clkgate (
input clk_in,
input test_mode,
input clock_en,
output clk_out
);
`ifdef FPGA_SOURCE//{
// In the FPGA, the clock gating is just pass through
assign clk_out = clk_in;
`endif//}
`ifndef FPGA_SOURCE//{
reg enb;
always@(*)
if (!clk_in)
enb = (clock_en | test_mode);
assign clk_out = enb & clk_in;
`endif//}
endmodule
|
module e203_subsys_pll(
input pll_asleep, // The asleep signal to PLL to power down it
input pllrefclk, // The reference clock into PLL
output plloutclk, // The PLL generated clock
input pll_RESET,
input [1:0] pll_OD,
input [7:0] pll_M,
input [4:0] pll_N
);
wire pllout;
`ifdef FPGA_SOURCE//{
// In FPGA, we have no PLL, so just diretly let it pass through
assign pllout = pllrefclk;
`else //}{
assign pllout = pllrefclk;
`endif//}
assign plloutclk = pllout;
endmodule
|
module sirv_uarttx(
input clock,
input reset,
input io_en,
output io_in_ready,
input io_in_valid,
input [7:0] io_in_bits,
output io_out,
input [15:0] io_div,
input io_nstop
);
reg [15:0] prescaler;
reg [31:0] GEN_6;
wire pulse;
reg [3:0] counter;
reg [31:0] GEN_7;
reg [8:0] shifter;
reg [31:0] GEN_8;
reg out;
reg [31:0] GEN_9;
wire busy;
wire T_32;
wire T_33;
wire T_34;
wire T_36;
wire [8:0] T_38;
wire T_40;
wire [3:0] T_46;
wire [3:0] T_48;
wire [3:0] T_50;
wire [3:0] T_51;
wire [8:0] GEN_0;
wire [3:0] GEN_1;
wire [16:0] T_53;
wire [15:0] T_54;
wire [15:0] T_55;
wire [15:0] GEN_2;
wire T_56;
wire [4:0] T_58;
wire [3:0] T_59;
wire [7:0] T_61;
wire [8:0] T_62;
wire T_63;
wire [3:0] GEN_3;
wire [8:0] GEN_4;
wire GEN_5;
assign io_in_ready = T_33;
assign io_out = out;
assign pulse = prescaler == 16'h0;
assign busy = counter != 4'h0;
assign T_32 = busy == 1'h0;
assign T_33 = io_en & T_32;
assign T_34 = io_in_ready & io_in_valid;
assign T_36 = reset == 1'h0;
assign T_38 = {io_in_bits,1'h0};
assign T_40 = io_nstop == 1'h0;
assign T_46 = T_40 ? 4'ha : 4'h0;
assign T_48 = io_nstop ? 4'hb : 4'h0;
assign T_50 = T_46 | T_48;
assign T_51 = T_50;
assign GEN_0 = T_34 ? T_38 : shifter;
assign GEN_1 = T_34 ? T_51 : counter;
assign T_53 = prescaler - 16'h1;
assign T_54 = T_53[15:0];
assign T_55 = pulse ? io_div : T_54;
assign GEN_2 = busy ? T_55 : prescaler;
assign T_56 = pulse & busy;
assign T_58 = counter - 4'h1;
assign T_59 = T_58[3:0];
assign T_61 = shifter[8:1];
assign T_62 = {1'h1,T_61};
assign T_63 = shifter[0];
assign GEN_3 = T_56 ? T_59 : GEN_1;
assign GEN_4 = T_56 ? T_62 : GEN_0;
assign GEN_5 = T_56 ? T_63 : out;
always @(posedge clock or posedge reset)
if (reset) begin
prescaler <= 16'h0;
end else begin
if (busy) begin
if (pulse) begin
prescaler <= io_div;
end else begin
prescaler <= T_54;
end
end
end
always @(posedge clock or posedge reset)
if (reset) begin
counter <= 4'h0;
end else begin
if (T_56) begin
counter <= T_59;
end else begin
if (T_34) begin
counter <= T_51;
end
end
end
always @(posedge clock or posedge reset)
if (reset) begin
shifter <= 9'b0;
end
else begin
if (T_56) begin
shifter <= T_62;
end else begin
if (T_34) begin
shifter <= T_38;
end
end
end
always @(posedge clock or posedge reset)
if (reset) begin
out <= 1'h1;
end else begin
if (T_56) begin
out <= T_63;
end
end
//`ifndef SYNTHESIS
//`ifdef PRINTF_COND
// if (`PRINTF_COND) begin
//`endif
// if (T_34 & T_36) begin
// $fwrite(32'h80000002,"%c",io_in_bits);
// end
//`ifdef PRINTF_COND
// end
//`endif
//`endif
//synopsys translate_off
always @(posedge clock or posedge reset) begin
if (T_34 & T_36) begin
$fwrite(32'h80000002,"%c",io_in_bits);
end
end
//synopsys translate_on
endmodule
|
module sirv_pwm8_core(
input clock,
input reset,
input io_regs_cfg_write_valid,
input [31:0] io_regs_cfg_write_bits,
output [31:0] io_regs_cfg_read,
input io_regs_countLo_write_valid,
input [31:0] io_regs_countLo_write_bits,
output [31:0] io_regs_countLo_read,
input io_regs_countHi_write_valid,
input [31:0] io_regs_countHi_write_bits,
output [31:0] io_regs_countHi_read,
input io_regs_s_write_valid,
input [7:0] io_regs_s_write_bits,
output [7:0] io_regs_s_read,
input io_regs_cmp_0_write_valid,
input [7:0] io_regs_cmp_0_write_bits,
output [7:0] io_regs_cmp_0_read,
input io_regs_cmp_1_write_valid,
input [7:0] io_regs_cmp_1_write_bits,
output [7:0] io_regs_cmp_1_read,
input io_regs_cmp_2_write_valid,
input [7:0] io_regs_cmp_2_write_bits,
output [7:0] io_regs_cmp_2_read,
input io_regs_cmp_3_write_valid,
input [7:0] io_regs_cmp_3_write_bits,
output [7:0] io_regs_cmp_3_read,
input io_regs_feed_write_valid,
input [31:0] io_regs_feed_write_bits,
output [31:0] io_regs_feed_read,
input io_regs_key_write_valid,
input [31:0] io_regs_key_write_bits,
output [31:0] io_regs_key_read,
output io_ip_0,
output io_ip_1,
output io_ip_2,
output io_ip_3,
output io_gpio_0,
output io_gpio_1,
output io_gpio_2,
output io_gpio_3
);
wire [3:0] T_178;
reg [3:0] scale;
reg [31:0] GEN_21;
wire [3:0] GEN_0;
reg [7:0] cmp_0;
reg [31:0] GEN_22;
wire [7:0] GEN_1;
reg [7:0] cmp_1;
reg [31:0] GEN_23;
wire [7:0] GEN_2;
reg [7:0] cmp_2;
reg [31:0] GEN_24;
wire [7:0] GEN_3;
reg [7:0] cmp_3;
reg [31:0] GEN_25;
wire [7:0] GEN_4;
wire countEn;
reg [4:0] T_196;
reg [31:0] GEN_26;
wire [4:0] GEN_18;
wire [5:0] T_197;
reg [17:0] T_199;
reg [31:0] GEN_27;
wire T_200;
wire [18:0] T_202;
wire [18:0] GEN_5;
wire [22:0] T_203;
wire [32:0] T_207;
wire [27:0] T_208;
wire [32:0] GEN_6;
wire [27:0] GEN_7;
wire [22:0] T_209;
wire [7:0] s;
wire T_210;
wire [3:0] T_211;
reg [3:0] center;
reg [31:0] GEN_28;
wire [3:0] GEN_8;
wire T_215;
wire T_216;
wire [7:0] T_217;
wire [7:0] T_218;
wire elapsed_0;
wire T_220;
wire T_221;
wire [7:0] T_223;
wire elapsed_1;
wire T_225;
wire T_226;
wire [7:0] T_228;
wire elapsed_2;
wire T_230;
wire T_231;
wire [7:0] T_233;
wire elapsed_3;
wire [5:0] GEN_19;
wire [5:0] T_234;
wire [4:0] T_235;
wire [18:0] GEN_20;
wire [18:0] T_239;
wire [18:0] T_241;
wire [17:0] T_242;
wire [22:0] T_243;
wire [4:0] T_245;
wire [3:0] T_246;
wire [22:0] T_247;
wire feed;
wire T_248;
reg zerocmp;
reg [31:0] GEN_29;
wire GEN_9;
wire T_252;
wire countReset;
wire [32:0] GEN_10;
wire [27:0] GEN_11;
wire T_255;
reg T_259;
reg [31:0] GEN_30;
wire GEN_12;
wire T_261;
wire T_262;
wire T_263;
reg T_267;
reg [31:0] GEN_31;
wire GEN_13;
wire T_268;
reg T_269;
reg [31:0] GEN_32;
wire [1:0] T_282;
wire [1:0] T_283;
wire [3:0] T_284;
reg [3:0] ip;
reg [31:0] GEN_33;
wire [1:0] T_286;
wire [1:0] T_287;
wire [3:0] T_288;
wire [3:0] T_289;
wire [3:0] T_290;
wire [3:0] T_297;
wire [3:0] T_298;
wire [3:0] T_299;
wire [3:0] T_300;
wire [3:0] T_301;
wire [3:0] T_304;
wire [3:0] GEN_14;
wire [3:0] T_305;
reg [3:0] gang;
reg [31:0] GEN_34;
wire [3:0] GEN_15;
wire T_316;
wire T_319;
wire T_323;
reg oneShot;
reg [31:0] GEN_35;
wire GEN_16;
wire T_325;
reg countAlways;
reg [31:0] GEN_36;
wire GEN_17;
wire [4:0] T_333;
wire [8:0] T_334;
wire [1:0] T_335;
wire [2:0] T_336;
wire [11:0] T_337;
wire [2:0] T_338;
wire [3:0] T_339;
wire [7:0] T_340;
wire [7:0] T_341;
wire [15:0] T_342;
wire [19:0] T_343;
wire [31:0] T_344;
wire T_350_0;
wire T_350_1;
wire T_350_2;
wire T_350_3;
wire T_352;
wire T_353;
wire T_354;
wire T_355;
wire [2:0] T_357;
wire [3:0] T_358;
wire [3:0] T_359;
wire [3:0] T_360;
wire [3:0] T_361;
wire T_364_0;
wire T_364_1;
wire T_364_2;
wire T_364_3;
wire T_366;
wire T_367;
wire T_368;
wire T_369;
wire T_370;
assign io_regs_cfg_read = T_344;
assign io_regs_countLo_read = {{9'd0}, T_203};
assign io_regs_countHi_read = 32'h0;
assign io_regs_s_read = s;
assign io_regs_cmp_0_read = cmp_0;
assign io_regs_cmp_1_read = cmp_1;
assign io_regs_cmp_2_read = cmp_2;
assign io_regs_cmp_3_read = cmp_3;
assign io_regs_feed_read = 32'h0;
assign io_regs_key_read = 32'h1;
assign io_ip_0 = T_350_0;
assign io_ip_1 = T_350_1;
assign io_ip_2 = T_350_2;
assign io_ip_3 = T_350_3;
assign io_gpio_0 = T_364_0;
assign io_gpio_1 = T_364_1;
assign io_gpio_2 = T_364_2;
assign io_gpio_3 = T_364_3;
assign T_178 = io_regs_cfg_write_bits[3:0];
assign GEN_0 = io_regs_cfg_write_valid ? T_178 : scale;
assign GEN_1 = io_regs_cmp_0_write_valid ? io_regs_cmp_0_write_bits : cmp_0;
assign GEN_2 = io_regs_cmp_1_write_valid ? io_regs_cmp_1_write_bits : cmp_1;
assign GEN_3 = io_regs_cmp_2_write_valid ? io_regs_cmp_2_write_bits : cmp_2;
assign GEN_4 = io_regs_cmp_3_write_valid ? io_regs_cmp_3_write_bits : cmp_3;
assign countEn = T_370;
assign GEN_18 = {{4'd0}, countEn};
assign T_197 = T_196 + GEN_18;
assign T_200 = T_197[5];
assign T_202 = T_199 + 18'h1;
assign GEN_5 = T_200 ? T_202 : {{1'd0}, T_199};
assign T_203 = {T_199,T_196};
assign T_207 = {1'h0,io_regs_countLo_write_bits};
assign T_208 = T_207[32:5];
assign GEN_6 = io_regs_countLo_write_valid ? T_207 : {{27'd0}, T_197};
assign GEN_7 = io_regs_countLo_write_valid ? T_208 : {{9'd0}, GEN_5};
assign T_209 = T_203 >> scale;
assign s = T_209[7:0];
assign T_210 = s[7];
assign T_211 = io_regs_cfg_write_bits[19:16];
assign GEN_8 = io_regs_cfg_write_valid ? T_211 : center;
assign T_215 = center[0];
assign T_216 = T_210 & T_215;
assign T_217 = ~ s;
assign T_218 = T_216 ? T_217 : s;
assign elapsed_0 = T_218 >= cmp_0;
assign T_220 = center[1];
assign T_221 = T_210 & T_220;
assign T_223 = T_221 ? T_217 : s;
assign elapsed_1 = T_223 >= cmp_1;
assign T_225 = center[2];
assign T_226 = T_210 & T_225;
assign T_228 = T_226 ? T_217 : s;
assign elapsed_2 = T_228 >= cmp_2;
assign T_230 = center[3];
assign T_231 = T_210 & T_230;
assign T_233 = T_231 ? T_217 : s;
assign elapsed_3 = T_233 >= cmp_3;
assign GEN_19 = {{1'd0}, T_196};
assign T_234 = GEN_19 ^ T_197;
assign T_235 = T_234[5:1];
assign GEN_20 = {{1'd0}, T_199};
assign T_239 = GEN_20 ^ T_202;
assign T_241 = T_200 ? T_239 : 19'h0;
assign T_242 = T_241[18:1];
assign T_243 = {T_242,T_235};
assign T_245 = scale + 4'h8;
assign T_246 = T_245[3:0];
assign T_247 = T_243 >> T_246;
assign feed = T_247[0];
assign T_248 = io_regs_cfg_write_bits[9];
assign GEN_9 = io_regs_cfg_write_valid ? T_248 : zerocmp;
assign T_252 = zerocmp & elapsed_0;
assign countReset = feed | T_252;
assign GEN_10 = countReset ? 33'h0 : GEN_6;
assign GEN_11 = countReset ? 28'h0 : GEN_7;
assign T_255 = io_regs_cfg_write_bits[10];
assign GEN_12 = io_regs_cfg_write_valid ? T_255 : T_259;
assign T_261 = countReset == 1'h0;
assign T_262 = T_259 & T_261;
assign T_263 = io_regs_cfg_write_bits[8];
assign GEN_13 = io_regs_cfg_write_valid ? T_263 : T_267;
assign T_268 = T_262 | T_267;
assign T_282 = {T_221,T_216};
assign T_283 = {T_231,T_226};
assign T_284 = {T_283,T_282};
assign T_286 = {elapsed_1,elapsed_0};
assign T_287 = {elapsed_3,elapsed_2};
assign T_288 = {T_287,T_286};
assign T_289 = T_284 & T_288;
assign T_290 = ~ T_284;
assign T_297 = T_269 ? 4'hf : 4'h0;
assign T_298 = T_297 & ip;
assign T_299 = T_288 | T_298;
assign T_300 = T_290 & T_299;
assign T_301 = T_289 | T_300;
assign T_304 = io_regs_cfg_write_bits[31:28];
assign GEN_14 = io_regs_cfg_write_valid ? T_304 : T_301;
assign T_305 = io_regs_cfg_write_bits[27:24];
assign GEN_15 = io_regs_cfg_write_valid ? T_305 : gang;
assign T_316 = io_regs_cfg_write_bits[13];
assign T_319 = T_316 & T_261;
assign T_323 = io_regs_cfg_write_valid | countReset;
assign GEN_16 = T_323 ? T_319 : oneShot;
assign T_325 = io_regs_cfg_write_bits[12];
assign GEN_17 = io_regs_cfg_write_valid ? T_325 : countAlways;
assign T_333 = {T_267,4'h0};
assign T_334 = {T_333,scale};
assign T_335 = {1'h0,T_259};
assign T_336 = {T_335,zerocmp};
assign T_337 = {T_336,T_334};
assign T_338 = {2'h0,oneShot};
assign T_339 = {T_338,countAlways};
assign T_340 = {4'h0,center};
assign T_341 = {ip,gang};
assign T_342 = {T_341,T_340};
assign T_343 = {T_342,T_339};
assign T_344 = {T_343,T_337};
assign T_350_0 = T_352;
assign T_350_1 = T_353;
assign T_350_2 = T_354;
assign T_350_3 = T_355;
assign T_352 = ip[0];
assign T_353 = ip[1];
assign T_354 = ip[2];
assign T_355 = ip[3];
assign T_357 = ip[3:1];
assign T_358 = {T_352,T_357};
assign T_359 = gang & T_358;
assign T_360 = ~ T_359;
assign T_361 = ip & T_360;
assign T_364_0 = T_366;
assign T_364_1 = T_367;
assign T_364_2 = T_368;
assign T_364_3 = T_369;
assign T_366 = T_361[0];
assign T_367 = T_361[1];
assign T_368 = T_361[2];
assign T_369 = T_361[3];
assign T_370 = countAlways | oneShot;
always @(posedge clock or posedge reset)
if(reset) begin
scale <= 4'b0;
cmp_0 <= 8'b0;
cmp_1 <= 8'b0;
cmp_2 <= 8'b0;
cmp_3 <= 8'b0;
T_196 <= 5'b0;
T_199 <= 18'b0;
center <= 4'b0;
zerocmp <= 1'b0;
T_259 <= 1'b0;
T_267 <= 1'b0;
T_269 <= 1'b0;
ip <= 4'b0;
gang <= 4'b0;
end
else begin
if (io_regs_cfg_write_valid) begin
scale <= T_178;
end
if (io_regs_cmp_0_write_valid) begin
cmp_0 <= io_regs_cmp_0_write_bits;
end
if (io_regs_cmp_1_write_valid) begin
cmp_1 <= io_regs_cmp_1_write_bits;
end
if (io_regs_cmp_2_write_valid) begin
cmp_2 <= io_regs_cmp_2_write_bits;
end
if (io_regs_cmp_3_write_valid) begin
cmp_3 <= io_regs_cmp_3_write_bits;
end
T_196 <= GEN_10[4:0];
T_199 <= GEN_11[17:0];
if (io_regs_cfg_write_valid) begin
center <= T_211;
end
if (io_regs_cfg_write_valid) begin
zerocmp <= T_248;
end
if (io_regs_cfg_write_valid) begin
T_259 <= T_255;
end
if (io_regs_cfg_write_valid) begin
T_267 <= T_263;
end
T_269 <= T_268;
if (io_regs_cfg_write_valid) begin
ip <= T_304;
end else begin
ip <= T_301;
end
if (io_regs_cfg_write_valid) begin
gang <= T_305;
end
end
always @(posedge clock or posedge reset)
if (reset) begin
oneShot <= 1'h0;
end else begin
if (T_323) begin
oneShot <= T_319;
end
end
always @(posedge clock or posedge reset)
if (reset) begin
countAlways <= 1'h0;
end else begin
if (io_regs_cfg_write_valid) begin
countAlways <= T_325;
end
end
endmodule
|
module i2c_master_bit_ctrl(
clk, rst, nReset,
clk_cnt, ena, cmd, cmd_ack, busy, al, din, dout,
scl_i, scl_o, scl_oen, sda_i, sda_o, sda_oen
);
//
// inputs & outputs
//
input clk;
input rst;
input nReset;
input ena; // core enable signal
input [15:0] clk_cnt; // clock prescale value
input [3:0] cmd;
output cmd_ack; // command complete acknowledge
reg cmd_ack;
output busy; // i2c bus busy
reg busy;
output al; // i2c bus arbitration lost
reg al;
input din;
output dout;
reg dout;
// I2C lines
input scl_i; // i2c clock line input
output scl_o; // i2c clock line output
output scl_oen; // i2c clock line output enable (active low)
reg scl_oen;
input sda_i; // i2c data line input
output sda_o; // i2c data line output
output sda_oen; // i2c data line output enable (active low)
reg sda_oen;
//
// variable declarations
//
reg sSCL, sSDA; // synchronized SCL and SDA inputs
reg dscl_oen; // delayed scl_oen
reg sda_chk; // check SDA output (Multi-master arbitration)
reg clk_en; // clock generation signals
wire slave_wait;
// reg [15:0] cnt = clk_cnt; // clock divider counter (simulation)
reg [15:0] cnt; // clock divider counter (synthesis)
// state machine variable
reg [16:0] c_state;
//
// module body
//
// whenever the slave is not ready it can delay the cycle by pulling SCL low
// delay scl_oen
always @(posedge clk)
dscl_oen <= #1 scl_oen;
assign slave_wait = dscl_oen && !sSCL;
// generate clk enable signal
always @(posedge clk or negedge nReset)
if(~nReset)
begin
cnt <= #1 16'h0;
clk_en <= #1 1'b1;
end
else if (rst)
begin
cnt <= #1 16'h0;
clk_en <= #1 1'b1;
end
else if ( ~|cnt || ~ena)
if (~slave_wait)
begin
cnt <= #1 clk_cnt;
clk_en <= #1 1'b1;
end
else
begin
cnt <= #1 cnt;
clk_en <= #1 1'b0;
end
else
begin
cnt <= #1 cnt - 16'h1;
clk_en <= #1 1'b0;
end
// generate bus status controller
reg dSCL, dSDA;
reg sta_condition;
reg sto_condition;
// synchronize SCL and SDA inputs
// reduce metastability risc
always @(posedge clk or negedge nReset)
if (~nReset)
begin
sSCL <= #1 1'b1;
sSDA <= #1 1'b1;
dSCL <= #1 1'b1;
dSDA <= #1 1'b1;
end
else if (rst)
begin
sSCL <= #1 1'b1;
sSDA <= #1 1'b1;
dSCL <= #1 1'b1;
dSDA <= #1 1'b1;
end
else
begin
sSCL <= #1 scl_i;
sSDA <= #1 sda_i;
dSCL <= #1 sSCL;
dSDA <= #1 sSDA;
end
// detect start condition => detect falling edge on SDA while SCL is high
// detect stop condition => detect rising edge on SDA while SCL is high
always @(posedge clk or negedge nReset)
if (~nReset)
begin
sta_condition <= #1 1'b0;
sto_condition <= #1 1'b0;
end
else if (rst)
begin
sta_condition <= #1 1'b0;
sto_condition <= #1 1'b0;
end
else
begin
sta_condition <= #1 ~sSDA & dSDA & sSCL;
sto_condition <= #1 sSDA & ~dSDA & sSCL;
end
// generate i2c bus busy signal
always @(posedge clk or negedge nReset)
if(!nReset)
busy <= #1 1'b0;
else if (rst)
busy <= #1 1'b0;
else
busy <= #1 (sta_condition | busy) & ~sto_condition;
// generate arbitration lost signal
// aribitration lost when:
// 1) master drives SDA high, but the i2c bus is low
// 2) stop detected while not requested
reg cmd_stop;
always @(posedge clk or negedge nReset)
if (~nReset)
cmd_stop <= #1 1'b0;
else if (rst)
cmd_stop <= #1 1'b0;
else if (clk_en)
cmd_stop <= #1 cmd == `I2C_CMD_STOP;
always @(posedge clk or negedge nReset)
if (~nReset)
al <= #1 1'b0;
else if (rst)
al <= #1 1'b0;
else
al <= #1 (sda_chk & ~sSDA & sda_oen) | (|c_state & sto_condition & ~cmd_stop);
// generate dout signal (store SDA on rising edge of SCL)
always @(posedge clk)
if(sSCL & ~dSCL)
dout <= #1 sSDA;
// generate statemachine
// nxt_state decoder
parameter [16:0] idle = 17'b0_0000_0000_0000_0000;
parameter [16:0] start_a = 17'b0_0000_0000_0000_0001;
parameter [16:0] start_b = 17'b0_0000_0000_0000_0010;
parameter [16:0] start_c = 17'b0_0000_0000_0000_0100;
parameter [16:0] start_d = 17'b0_0000_0000_0000_1000;
parameter [16:0] start_e = 17'b0_0000_0000_0001_0000;
parameter [16:0] stop_a = 17'b0_0000_0000_0010_0000;
parameter [16:0] stop_b = 17'b0_0000_0000_0100_0000;
parameter [16:0] stop_c = 17'b0_0000_0000_1000_0000;
parameter [16:0] stop_d = 17'b0_0000_0001_0000_0000;
parameter [16:0] rd_a = 17'b0_0000_0010_0000_0000;
parameter [16:0] rd_b = 17'b0_0000_0100_0000_0000;
parameter [16:0] rd_c = 17'b0_0000_1000_0000_0000;
parameter [16:0] rd_d = 17'b0_0001_0000_0000_0000;
parameter [16:0] wr_a = 17'b0_0010_0000_0000_0000;
parameter [16:0] wr_b = 17'b0_0100_0000_0000_0000;
parameter [16:0] wr_c = 17'b0_1000_0000_0000_0000;
parameter [16:0] wr_d = 17'b1_0000_0000_0000_0000;
always @(posedge clk or negedge nReset)
if (!nReset)
begin
c_state <= #1 idle;
cmd_ack <= #1 1'b0;
scl_oen <= #1 1'b1;
sda_oen <= #1 1'b1;
sda_chk <= #1 1'b0;
end
else if (rst | al)
begin
c_state <= #1 idle;
cmd_ack <= #1 1'b0;
scl_oen <= #1 1'b1;
sda_oen <= #1 1'b1;
sda_chk <= #1 1'b0;
end
else
begin
cmd_ack <= #1 1'b0; // default no command acknowledge + assert cmd_ack only 1clk cycle
if (clk_en)
case (c_state) // synopsys full_case parallel_case
// idle state
idle:
begin
case (cmd) // synopsys full_case parallel_case
`I2C_CMD_START:
c_state <= #1 start_a;
`I2C_CMD_STOP:
c_state <= #1 stop_a;
`I2C_CMD_WRITE:
c_state <= #1 wr_a;
`I2C_CMD_READ:
c_state <= #1 rd_a;
default:
c_state <= #1 idle;
endcase
scl_oen <= #1 scl_oen; // keep SCL in same state
sda_oen <= #1 sda_oen; // keep SDA in same state
sda_chk <= #1 1'b0; // don't check SDA output
end
// start
start_a:
begin
c_state <= #1 start_b;
scl_oen <= #1 scl_oen; // keep SCL in same state
sda_oen <= #1 1'b1; // set SDA high
sda_chk <= #1 1'b0; // don't check SDA output
end
start_b:
begin
c_state <= #1 start_c;
scl_oen <= #1 1'b1; // set SCL high
sda_oen <= #1 1'b1; // keep SDA high
sda_chk <= #1 1'b0; // don't check SDA output
end
start_c:
begin
c_state <= #1 start_d;
scl_oen <= #1 1'b1; // keep SCL high
sda_oen <= #1 1'b0; // set SDA low
sda_chk <= #1 1'b0; // don't check SDA output
end
start_d:
begin
c_state <= #1 start_e;
scl_oen <= #1 1'b1; // keep SCL high
sda_oen <= #1 1'b0; // keep SDA low
sda_chk <= #1 1'b0; // don't check SDA output
end
start_e:
begin
c_state <= #1 idle;
cmd_ack <= #1 1'b1;
scl_oen <= #1 1'b0; // set SCL low
sda_oen <= #1 1'b0; // keep SDA low
sda_chk <= #1 1'b0; // don't check SDA output
end
// stop
stop_a:
begin
c_state <= #1 stop_b;
scl_oen <= #1 1'b0; // keep SCL low
sda_oen <= #1 1'b0; // set SDA low
sda_chk <= #1 1'b0; // don't check SDA output
end
stop_b:
begin
c_state <= #1 stop_c;
scl_oen <= #1 1'b1; // set SCL high
sda_oen <= #1 1'b0; // keep SDA low
sda_chk <= #1 1'b0; // don't check SDA output
end
stop_c:
begin
c_state <= #1 stop_d;
scl_oen <= #1 1'b1; // keep SCL high
sda_oen <= #1 1'b0; // keep SDA low
sda_chk <= #1 1'b0; // don't check SDA output
end
stop_d:
begin
c_state <= #1 idle;
cmd_ack <= #1 1'b1;
scl_oen <= #1 1'b1; // keep SCL high
sda_oen <= #1 1'b1; // set SDA high
sda_chk <= #1 1'b0; // don't check SDA output
end
// read
rd_a:
begin
c_state <= #1 rd_b;
scl_oen <= #1 1'b0; // keep SCL low
sda_oen <= #1 1'b1; // tri-state SDA
sda_chk <= #1 1'b0; // don't check SDA output
end
rd_b:
begin
c_state <= #1 rd_c;
scl_oen <= #1 1'b1; // set SCL high
sda_oen <= #1 1'b1; // keep SDA tri-stated
sda_chk <= #1 1'b0; // don't check SDA output
end
rd_c:
begin
c_state <= #1 rd_d;
scl_oen <= #1 1'b1; // keep SCL high
sda_oen <= #1 1'b1; // keep SDA tri-stated
sda_chk <= #1 1'b0; // don't check SDA output
end
rd_d:
begin
c_state <= #1 idle;
cmd_ack <= #1 1'b1;
scl_oen <= #1 1'b0; // set SCL low
sda_oen <= #1 1'b1; // keep SDA tri-stated
sda_chk <= #1 1'b0; // don't check SDA output
end
// write
wr_a:
begin
c_state <= #1 wr_b;
scl_oen <= #1 1'b0; // keep SCL low
sda_oen <= #1 din; // set SDA
sda_chk <= #1 1'b0; // don't check SDA output (SCL low)
end
wr_b:
begin
c_state <= #1 wr_c;
scl_oen <= #1 1'b1; // set SCL high
sda_oen <= #1 din; // keep SDA
sda_chk <= #1 1'b1; // check SDA output
end
wr_c:
begin
c_state <= #1 wr_d;
scl_oen <= #1 1'b1; // keep SCL high
sda_oen <= #1 din;
sda_chk <= #1 1'b1; // check SDA output
end
wr_d:
begin
c_state <= #1 idle;
cmd_ack <= #1 1'b1;
scl_oen <= #1 1'b0; // set SCL low
sda_oen <= #1 din;
sda_chk <= #1 1'b0; // don't check SDA output (SCL low)
end
endcase
end
// assign scl and sda output (always gnd)
assign scl_o = 1'b0;
assign sda_o = 1'b0;
endmodule
|
module e203_clk_ctrl (
input clk, // clock
input rst_n, // async reset
input test_mode, // test mode
// The cgstop is coming from CSR (0xBFE mcgstop)'s filed 0
// // This register is our self-defined CSR register to disable the
// automaticall clock gating for CPU logics for debugging purpose
input core_cgstop,
// The Top always on clk and rst
output clk_aon,
input core_ifu_active,
input core_exu_active,
input core_lsu_active,
input core_biu_active,
`ifdef E203_HAS_ITCM
input itcm_active,
output itcm_ls,
`endif
`ifdef E203_HAS_DTCM
input dtcm_active,
output dtcm_ls,
`endif
// The core's clk and rst
output clk_core_ifu,
output clk_core_exu,
output clk_core_lsu,
output clk_core_biu,
// The ITCM/DTCM clk and rst
`ifdef E203_HAS_ITCM
output clk_itcm,
`endif
`ifdef E203_HAS_DTCM
output clk_dtcm,
`endif
input core_wfi
);
// The CSR control bit CGSTOP will override the automatical clock gating here for special debug purpose
// The IFU is always actively fetching unless it is WFI to override it
wire ifu_clk_en = core_cgstop | (core_ifu_active & (~core_wfi));
// The EXU, LSU and BIU module's clock gating does not need to check
// WFI because it may have request from external agent
// and also, it actually will automactically become inactive regardess
// currently is WFI or not, hence we dont need WFI here
wire exu_clk_en = core_cgstop | (core_exu_active);
wire lsu_clk_en = core_cgstop | (core_lsu_active);
wire biu_clk_en = core_cgstop | (core_biu_active);
e203_clkgate u_ifu_clkgate(
.clk_in (clk ),
.test_mode(test_mode ),
.clock_en (ifu_clk_en),
.clk_out (clk_core_ifu)
);
e203_clkgate u_exu_clkgate(
.clk_in (clk ),
.test_mode(test_mode ),
.clock_en (exu_clk_en),
.clk_out (clk_core_exu)
);
e203_clkgate u_lsu_clkgate(
.clk_in (clk ),
.test_mode(test_mode ),
.clock_en (lsu_clk_en),
.clk_out (clk_core_lsu)
);
e203_clkgate u_biu_clkgate(
.clk_in (clk ),
.test_mode(test_mode ),
.clock_en (biu_clk_en),
.clk_out (clk_core_biu)
);
`ifdef E203_HAS_ITCM
// The ITCM and DTCM Ctrl module's clock gating does not need to check
// WFI because it may have request from external agent
// and also, it actually will automactically become inactive regardess
// currently is WFI or not, hence we dont need WFI here
wire itcm_active_r;
sirv_gnrl_dffr #(1)itcm_active_dffr(itcm_active, itcm_active_r, clk, rst_n);
wire itcm_clk_en = core_cgstop | itcm_active | itcm_active_r;
assign itcm_ls = ~itcm_clk_en;
e203_clkgate u_itcm_clkgate(
.clk_in (clk ),
.test_mode(test_mode ),
.clock_en (itcm_clk_en),
.clk_out (clk_itcm)
);
`endif
`ifdef E203_HAS_DTCM
wire dtcm_active_r;
sirv_gnrl_dffr #(1)dtcm_active_dffr(dtcm_active, dtcm_active_r, clk, rst_n);
wire dtcm_clk_en = core_cgstop | dtcm_active | dtcm_active_r;
assign dtcm_ls = ~dtcm_clk_en;
e203_clkgate u_dtcm_clkgate(
.clk_in (clk ),
.test_mode(test_mode ),
.clock_en (dtcm_clk_en),
.clk_out (clk_dtcm)
);
`endif
// The Top always on clk and rst
assign clk_aon = clk;
endmodule
|
module sirv_debug_ram(
input clk,
input rst_n,
input ram_cs,
input ram_rd,
input [ 3-1:0] ram_addr,
input [32-1:0] ram_wdat,
output [32-1:0] ram_dout
);
wire [31:0] debug_ram_r [0:6];
wire [6:0] ram_wen;
assign ram_dout = debug_ram_r[ram_addr];
genvar i;
generate //{
for (i=0; i<7; i=i+1) begin:debug_ram_gen//{
assign ram_wen[i] = ram_cs & (~ram_rd) & (ram_addr == i) ;
sirv_gnrl_dfflr #(32) ram_dfflr (ram_wen[i], ram_wdat, debug_ram_r[i], clk, rst_n);
end//}
endgenerate//}
endmodule
|
module sirv_qspi_fifo(
input clock,
input reset,
input [1:0] io_ctrl_fmt_proto,
input io_ctrl_fmt_endian,
input io_ctrl_fmt_iodir,
input [3:0] io_ctrl_fmt_len,
input [1:0] io_ctrl_cs_mode,
input [3:0] io_ctrl_wm_tx,
input [3:0] io_ctrl_wm_rx,
input io_link_tx_ready,
output io_link_tx_valid,
output [7:0] io_link_tx_bits,
input io_link_rx_valid,
input [7:0] io_link_rx_bits,
output [7:0] io_link_cnt,
output [1:0] io_link_fmt_proto,
output io_link_fmt_endian,
output io_link_fmt_iodir,
output io_link_cs_set,
output io_link_cs_clear,
output io_link_cs_hold,
input io_link_active,
output io_link_lock,
output io_tx_ready,
input io_tx_valid,
input [7:0] io_tx_bits,
input io_rx_ready,
output io_rx_valid,
output [7:0] io_rx_bits,
output io_ip_txwm,
output io_ip_rxwm
);
wire txq_clock;
wire txq_reset;
wire txq_io_enq_ready;
wire txq_io_enq_valid;
wire [7:0] txq_io_enq_bits;
wire txq_io_deq_ready;
wire txq_io_deq_valid;
wire [7:0] txq_io_deq_bits;
wire [3:0] txq_io_count;
wire rxq_clock;
wire rxq_reset;
wire rxq_io_enq_ready;
wire rxq_io_enq_valid;
wire [7:0] rxq_io_enq_bits;
wire rxq_io_deq_ready;
wire rxq_io_deq_valid;
wire [7:0] rxq_io_deq_bits;
wire [3:0] rxq_io_count;
wire fire_tx;
reg rxen;
reg [31:0] GEN_5;
wire T_94;
wire GEN_0;
wire T_96;
wire GEN_1;
wire T_97;
wire T_98;
wire T_99;
wire [2:0] T_101;
wire [1:0] T_102;
wire [3:0] T_104;
wire [2:0] T_106;
wire [1:0] T_108;
wire [3:0] GEN_2;
wire [3:0] T_110;
wire [3:0] GEN_3;
wire [3:0] T_111;
wire [3:0] cnt_quot;
wire T_112;
wire [1:0] T_115;
wire T_117;
wire [2:0] T_118;
wire T_120;
wire T_123;
wire T_126;
wire T_129;
wire T_131;
wire T_132;
wire cnt_rmdr;
wire [3:0] GEN_4;
wire [4:0] T_133;
wire [3:0] T_134;
reg [1:0] cs_mode;
reg [31:0] GEN_6;
wire cs_mode_hold;
wire cs_mode_off;
wire cs_update;
wire T_135;
wire cs_clear;
wire T_138;
wire T_139;
wire T_140;
wire T_142;
wire T_143;
wire T_144;
sirv_queue_1 txq (
.clock(txq_clock),
.reset(txq_reset),
.io_enq_ready(txq_io_enq_ready),
.io_enq_valid(txq_io_enq_valid),
.io_enq_bits(txq_io_enq_bits),
.io_deq_ready(txq_io_deq_ready),
.io_deq_valid(txq_io_deq_valid),
.io_deq_bits(txq_io_deq_bits),
.io_count(txq_io_count)
);
sirv_queue_1 rxq (
.clock(rxq_clock),
.reset(rxq_reset),
.io_enq_ready(rxq_io_enq_ready),
.io_enq_valid(rxq_io_enq_valid),
.io_enq_bits(rxq_io_enq_bits),
.io_deq_ready(rxq_io_deq_ready),
.io_deq_valid(rxq_io_deq_valid),
.io_deq_bits(rxq_io_deq_bits),
.io_count(rxq_io_count)
);
assign io_link_tx_valid = txq_io_deq_valid;
assign io_link_tx_bits = txq_io_deq_bits;
assign io_link_cnt = {{4'd0}, T_134};
assign io_link_fmt_proto = io_ctrl_fmt_proto;
assign io_link_fmt_endian = io_ctrl_fmt_endian;
assign io_link_fmt_iodir = io_ctrl_fmt_iodir;
assign io_link_cs_set = T_138;
assign io_link_cs_clear = T_140;
assign io_link_cs_hold = 1'h0;
assign io_link_lock = T_142;
assign io_tx_ready = txq_io_enq_ready;
assign io_rx_valid = rxq_io_deq_valid;
assign io_rx_bits = rxq_io_deq_bits;
assign io_ip_txwm = T_143;
assign io_ip_rxwm = T_144;
assign txq_clock = clock;
assign txq_reset = reset;
assign txq_io_enq_valid = io_tx_valid;
assign txq_io_enq_bits = io_tx_bits;
assign txq_io_deq_ready = io_link_tx_ready;
assign rxq_clock = clock;
assign rxq_reset = reset;
assign rxq_io_enq_valid = T_94;
assign rxq_io_enq_bits = io_link_rx_bits;
assign rxq_io_deq_ready = io_rx_ready;
assign fire_tx = io_link_tx_ready & io_link_tx_valid;
assign T_94 = io_link_rx_valid & rxen;
assign GEN_0 = io_link_rx_valid ? 1'h0 : rxen;
assign T_96 = io_link_fmt_iodir == 1'h0;
assign GEN_1 = fire_tx ? T_96 : GEN_0;
assign T_97 = 2'h0 == io_link_fmt_proto;
assign T_98 = 2'h1 == io_link_fmt_proto;
assign T_99 = 2'h2 == io_link_fmt_proto;
assign T_101 = io_ctrl_fmt_len[3:1];
assign T_102 = io_ctrl_fmt_len[3:2];
assign T_104 = T_97 ? io_ctrl_fmt_len : 4'h0;
assign T_106 = T_98 ? T_101 : 3'h0;
assign T_108 = T_99 ? T_102 : 2'h0;
assign GEN_2 = {{1'd0}, T_106};
assign T_110 = T_104 | GEN_2;
assign GEN_3 = {{2'd0}, T_108};
assign T_111 = T_110 | GEN_3;
assign cnt_quot = T_111;
assign T_112 = io_ctrl_fmt_len[0];
assign T_115 = io_ctrl_fmt_len[1:0];
assign T_117 = T_115 != 2'h0;
assign T_118 = io_ctrl_fmt_len[2:0];
assign T_120 = T_118 != 3'h0;
assign T_123 = T_97 ? T_112 : 1'h0;
assign T_126 = T_98 ? T_117 : 1'h0;
assign T_129 = T_99 ? T_120 : 1'h0;
assign T_131 = T_123 | T_126;
assign T_132 = T_131 | T_129;
assign cnt_rmdr = T_132;
assign GEN_4 = {{3'd0}, cnt_rmdr};
assign T_133 = cnt_quot + GEN_4;
assign T_134 = T_133[3:0];
assign cs_mode_hold = cs_mode == 2'h2;
assign cs_mode_off = cs_mode == 2'h3;
assign cs_update = cs_mode != io_ctrl_cs_mode;
assign T_135 = cs_mode_hold | cs_mode_off;
assign cs_clear = T_135 == 1'h0;
assign T_138 = cs_mode_off == 1'h0;
assign T_139 = fire_tx & cs_clear;
assign T_140 = cs_update | T_139;
assign T_142 = io_link_tx_valid | rxen;
assign T_143 = txq_io_count < io_ctrl_wm_tx;
assign T_144 = rxq_io_count > io_ctrl_wm_rx;
always @(posedge clock or posedge reset)
if (reset) begin
rxen <= 1'h0;
end else begin
if (fire_tx) begin
rxen <= T_96;
end else begin
if (io_link_rx_valid) begin
rxen <= 1'h0;
end
end
end
always @(posedge clock or posedge reset)
if (reset) begin
cs_mode <= 2'h0;
end else begin
cs_mode <= io_ctrl_cs_mode;
end
endmodule
|
module e203_ifu_ifetch(
output[`E203_PC_SIZE-1:0] inspect_pc,
input [`E203_PC_SIZE-1:0] pc_rtvec,
//////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////
// Fetch Interface to memory system, internal protocol
// * IFetch REQ channel
output ifu_req_valid, // Handshake valid
input ifu_req_ready, // Handshake ready
// Note: the req-addr can be unaligned with the length indicated
// by req_len signal.
// The targetd (ITCM, ICache or Sys-MEM) ctrl modules
// will handle the unalign cases and split-and-merge works
output [`E203_PC_SIZE-1:0] ifu_req_pc, // Fetch PC
output ifu_req_seq, // This request is a sequential instruction fetch
output ifu_req_seq_rv32, // This request is incremented 32bits fetch
output [`E203_PC_SIZE-1:0] ifu_req_last_pc, // The last accessed
// PC address (i.e., pc_r)
// * IFetch RSP channel
input ifu_rsp_valid, // Response valid
output ifu_rsp_ready, // Response ready
input ifu_rsp_err, // Response error
// Note: the RSP channel always return a valid instruction
// fetched from the fetching start PC address.
// The targetd (ITCM, ICache or Sys-MEM) ctrl modules
// will handle the unalign cases and split-and-merge works
//input ifu_rsp_replay,
input [`E203_INSTR_SIZE-1:0] ifu_rsp_instr, // Response instruction
//////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////
// The IR stage to EXU interface
output [`E203_INSTR_SIZE-1:0] ifu_o_ir,// The instruction register
output [`E203_PC_SIZE-1:0] ifu_o_pc, // The PC register along with
output ifu_o_pc_vld,
output [`E203_RFIDX_WIDTH-1:0] ifu_o_rs1idx,
output [`E203_RFIDX_WIDTH-1:0] ifu_o_rs2idx,
output ifu_o_prdt_taken, // The Bxx is predicted as taken
output ifu_o_misalgn, // The fetch misalign
output ifu_o_buserr, // The fetch bus error
output ifu_o_muldiv_b2b, // The mul/div back2back case
output ifu_o_valid, // Handshake signals with EXU stage
input ifu_o_ready,
output pipe_flush_ack,
input pipe_flush_req,
input [`E203_PC_SIZE-1:0] pipe_flush_add_op1,
input [`E203_PC_SIZE-1:0] pipe_flush_add_op2,
`ifdef E203_TIMING_BOOST//}
input [`E203_PC_SIZE-1:0] pipe_flush_pc,
`endif//}
// The halt request come from other commit stage
// If the ifu_halt_req is asserting, then IFU will stop fetching new
// instructions and after the oustanding transactions are completed,
// asserting the ifu_halt_ack as the response.
// The IFU will resume fetching only after the ifu_halt_req is deasserted
input ifu_halt_req,
output ifu_halt_ack,
input oitf_empty,
input [`E203_XLEN-1:0] rf2ifu_x1,
input [`E203_XLEN-1:0] rf2ifu_rs1,
input dec2ifu_rs1en,
input dec2ifu_rden,
input [`E203_RFIDX_WIDTH-1:0] dec2ifu_rdidx,
input dec2ifu_mulhsu,
input dec2ifu_div ,
input dec2ifu_rem ,
input dec2ifu_divu ,
input dec2ifu_remu ,
input clk,
input rst_n
);
wire ifu_req_hsked = (ifu_req_valid & ifu_req_ready) ;
wire ifu_rsp_hsked = (ifu_rsp_valid & ifu_rsp_ready) ;
wire ifu_ir_o_hsked = (ifu_o_valid & ifu_o_ready) ;
wire pipe_flush_hsked = pipe_flush_req & pipe_flush_ack;
// The rst_flag is the synced version of rst_n
// * rst_n is asserted
// The rst_flag will be clear when
// * rst_n is de-asserted
wire reset_flag_r;
sirv_gnrl_dffrs #(1) reset_flag_dffrs (1'b0, reset_flag_r, clk, rst_n);
//
// The reset_req valid is set when
// * Currently reset_flag is asserting
// The reset_req valid is clear when
// * Currently reset_req is asserting
// * Currently the flush can be accepted by IFU
wire reset_req_r;
wire reset_req_set = (~reset_req_r) & reset_flag_r;
wire reset_req_clr = reset_req_r & ifu_req_hsked;
wire reset_req_ena = reset_req_set | reset_req_clr;
wire reset_req_nxt = reset_req_set | (~reset_req_clr);
sirv_gnrl_dfflr #(1) reset_req_dfflr (reset_req_ena, reset_req_nxt, reset_req_r, clk, rst_n);
wire ifu_reset_req = reset_req_r;
//////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////
// The halt ack generation
wire halt_ack_set;
wire halt_ack_clr;
wire halt_ack_ena;
wire halt_ack_r;
wire halt_ack_nxt;
// The halt_ack will be set when
// * Currently halt_req is asserting
// * Currently halt_ack is not asserting
// * Currently the ifetch REQ channel is ready, means
// there is no oustanding transactions
wire ifu_no_outs;
assign halt_ack_set = ifu_halt_req & (~halt_ack_r) & ifu_no_outs;
// The halt_ack_r valid is cleared when
// * Currently halt_ack is asserting
// * Currently halt_req is de-asserting
assign halt_ack_clr = halt_ack_r & (~ifu_halt_req);
assign halt_ack_ena = halt_ack_set | halt_ack_clr;
assign halt_ack_nxt = halt_ack_set | (~halt_ack_clr);
sirv_gnrl_dfflr #(1) halt_ack_dfflr (halt_ack_ena, halt_ack_nxt, halt_ack_r, clk, rst_n);
assign ifu_halt_ack = halt_ack_r;
//////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////
// The flush ack signal generation
//
// Ideally the flush is acked when the ifetch interface is ready
// or there is rsponse valid
// But to cut the comb loop between EXU and IFU, we always accept
// the flush, when it is not really acknowledged, we use a
// delayed flush indication to remember this flush
// Note: Even if there is a delayed flush pending there, we
// still can accept new flush request
assign pipe_flush_ack = 1'b1;
wire dly_flush_set;
wire dly_flush_clr;
wire dly_flush_ena;
wire dly_flush_nxt;
// The dly_flush will be set when
// * There is a flush requst is coming, but the ifu
// is not ready to accept new fetch request
wire dly_flush_r;
assign dly_flush_set = pipe_flush_req & (~ifu_req_hsked);
// The dly_flush_r valid is cleared when
// * The delayed flush is issued
assign dly_flush_clr = dly_flush_r & ifu_req_hsked;
assign dly_flush_ena = dly_flush_set | dly_flush_clr;
assign dly_flush_nxt = dly_flush_set | (~dly_flush_clr);
sirv_gnrl_dfflr #(1) dly_flush_dfflr (dly_flush_ena, dly_flush_nxt, dly_flush_r, clk, rst_n);
wire dly_pipe_flush_req = dly_flush_r;
wire pipe_flush_req_real = pipe_flush_req | dly_pipe_flush_req;
//////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////
// The IR register to be used in EXU for decoding
wire ir_valid_set;
wire ir_valid_clr;
wire ir_valid_ena;
wire ir_valid_r;
wire ir_valid_nxt;
wire ir_pc_vld_set;
wire ir_pc_vld_clr;
wire ir_pc_vld_ena;
wire ir_pc_vld_r;
wire ir_pc_vld_nxt;
// The ir valid is set when there is new instruction fetched *and*
// no flush happening
wire ifu_rsp_need_replay;
wire pc_newpend_r;
wire ifu_ir_i_ready;
assign ir_valid_set = ifu_rsp_hsked & (~pipe_flush_req_real) & (~ifu_rsp_need_replay);
assign ir_pc_vld_set = pc_newpend_r & ifu_ir_i_ready & (~pipe_flush_req_real) & (~ifu_rsp_need_replay);
// The ir valid is cleared when it is accepted by EXU stage *or*
// the flush happening
assign ir_valid_clr = ifu_ir_o_hsked | (pipe_flush_hsked & ir_valid_r);
assign ir_pc_vld_clr = ir_valid_clr;
assign ir_valid_ena = ir_valid_set | ir_valid_clr;
assign ir_valid_nxt = ir_valid_set | (~ir_valid_clr);
assign ir_pc_vld_ena = ir_pc_vld_set | ir_pc_vld_clr;
assign ir_pc_vld_nxt = ir_pc_vld_set | (~ir_pc_vld_clr);
sirv_gnrl_dfflr #(1) ir_valid_dfflr (ir_valid_ena, ir_valid_nxt, ir_valid_r, clk, rst_n);
sirv_gnrl_dfflr #(1) ir_pc_vld_dfflr (ir_pc_vld_ena, ir_pc_vld_nxt, ir_pc_vld_r, clk, rst_n);
// IFU-IR loaded with the returned instruction from the IFetch RSP channel
wire [`E203_INSTR_SIZE-1:0] ifu_ir_nxt = ifu_rsp_instr;
// IFU-PC loaded with the current PC
wire ifu_err_nxt = ifu_rsp_err;
// IFU-IR and IFU-PC as the datapath register, only loaded and toggle when the valid reg is set
wire ifu_err_r;
sirv_gnrl_dfflr #(1) ifu_err_dfflr(ir_valid_set, ifu_err_nxt, ifu_err_r, clk, rst_n);
wire prdt_taken;
wire ifu_prdt_taken_r;
sirv_gnrl_dfflr #(1) ifu_prdt_taken_dfflr (ir_valid_set, prdt_taken, ifu_prdt_taken_r, clk, rst_n);
wire ifu_muldiv_b2b_nxt;
wire ifu_muldiv_b2b_r;
sirv_gnrl_dfflr #(1) ir_muldiv_b2b_dfflr (ir_valid_set, ifu_muldiv_b2b_nxt, ifu_muldiv_b2b_r, clk, rst_n);
//To save power the H-16bits only loaded when it is 32bits length instru
wire [`E203_INSTR_SIZE-1:0] ifu_ir_r;// The instruction register
wire minidec_rv32;
wire ir_hi_ena = ir_valid_set & minidec_rv32;
wire ir_lo_ena = ir_valid_set;
sirv_gnrl_dfflr #(`E203_INSTR_SIZE/2) ifu_hi_ir_dfflr (ir_hi_ena, ifu_ir_nxt[31:16], ifu_ir_r[31:16], clk, rst_n);
sirv_gnrl_dfflr #(`E203_INSTR_SIZE/2) ifu_lo_ir_dfflr (ir_lo_ena, ifu_ir_nxt[15: 0], ifu_ir_r[15: 0], clk, rst_n);
wire minidec_rs1en;
wire minidec_rs2en;
wire [`E203_RFIDX_WIDTH-1:0] minidec_rs1idx;
wire [`E203_RFIDX_WIDTH-1:0] minidec_rs2idx;
`ifndef E203_HAS_FPU//}
wire minidec_fpu = 1'b0;
wire minidec_fpu_rs1en = 1'b0;
wire minidec_fpu_rs2en = 1'b0;
wire minidec_fpu_rs3en = 1'b0;
wire minidec_fpu_rs1fpu = 1'b0;
wire minidec_fpu_rs2fpu = 1'b0;
wire minidec_fpu_rs3fpu = 1'b0;
wire [`E203_RFIDX_WIDTH-1:0] minidec_fpu_rs1idx = `E203_RFIDX_WIDTH'b0;
wire [`E203_RFIDX_WIDTH-1:0] minidec_fpu_rs2idx = `E203_RFIDX_WIDTH'b0;
`endif//}
wire [`E203_RFIDX_WIDTH-1:0] ir_rs1idx_r;
wire [`E203_RFIDX_WIDTH-1:0] ir_rs2idx_r;
wire bpu2rf_rs1_ena;
//FPU: if it is FPU instruction. we still need to put it into the IR register, but we need to mask off the non-integer regfile index to save power
wire ir_rs1idx_ena = (minidec_fpu & ir_valid_set & minidec_fpu_rs1en & (~minidec_fpu_rs1fpu)) | ((~minidec_fpu) & ir_valid_set & minidec_rs1en) | bpu2rf_rs1_ena;
wire ir_rs2idx_ena = (minidec_fpu & ir_valid_set & minidec_fpu_rs2en & (~minidec_fpu_rs2fpu)) | ((~minidec_fpu) & ir_valid_set & minidec_rs2en);
wire [`E203_RFIDX_WIDTH-1:0] ir_rs1idx_nxt = minidec_fpu ? minidec_fpu_rs1idx : minidec_rs1idx;
wire [`E203_RFIDX_WIDTH-1:0] ir_rs2idx_nxt = minidec_fpu ? minidec_fpu_rs2idx : minidec_rs2idx;
sirv_gnrl_dfflr #(`E203_RFIDX_WIDTH) ir_rs1idx_dfflr (ir_rs1idx_ena, ir_rs1idx_nxt, ir_rs1idx_r, clk, rst_n);
sirv_gnrl_dfflr #(`E203_RFIDX_WIDTH) ir_rs2idx_dfflr (ir_rs2idx_ena, ir_rs2idx_nxt, ir_rs2idx_r, clk, rst_n);
wire [`E203_PC_SIZE-1:0] pc_r;
wire [`E203_PC_SIZE-1:0] ifu_pc_nxt = pc_r;
wire [`E203_PC_SIZE-1:0] ifu_pc_r;
sirv_gnrl_dfflr #(`E203_PC_SIZE) ifu_pc_dfflr (ir_pc_vld_set, ifu_pc_nxt, ifu_pc_r, clk, rst_n);
assign ifu_o_ir = ifu_ir_r;
assign ifu_o_pc = ifu_pc_r;
// Instruction fetch misaligned exceptions are not possible on machines that support extensions
// with 16-bit aligned instructions, such as the compressed instruction set extension, C.
assign ifu_o_misalgn = 1'b0;// Never happen in RV32C configuration
assign ifu_o_buserr = ifu_err_r;
assign ifu_o_rs1idx = ir_rs1idx_r;
assign ifu_o_rs2idx = ir_rs2idx_r;
assign ifu_o_prdt_taken = ifu_prdt_taken_r;
assign ifu_o_muldiv_b2b = ifu_muldiv_b2b_r;
assign ifu_o_valid = ir_valid_r;
assign ifu_o_pc_vld = ir_pc_vld_r;
// The IFU-IR stage will be ready when it is empty or under-clearing
assign ifu_ir_i_ready = (~ir_valid_r) | ir_valid_clr;
//////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////
// JALR instruction dependency check
wire ir_empty = ~ir_valid_r;
wire ir_rs1en = dec2ifu_rs1en;
wire ir_rden = dec2ifu_rden;
wire [`E203_RFIDX_WIDTH-1:0] ir_rdidx = dec2ifu_rdidx;
wire [`E203_RFIDX_WIDTH-1:0] minidec_jalr_rs1idx;
wire jalr_rs1idx_cam_irrdidx = ir_rden & (minidec_jalr_rs1idx == ir_rdidx) & ir_valid_r;
//////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////
// MULDIV BACK2BACK Fusing
// To detect the sequence of MULH[[S]U] rdh, rs1, rs2; MUL rdl, rs1, rs2
// To detect the sequence of DIV[U] rdq, rs1, rs2; REM[U] rdr, rs1, rs2
wire minidec_mul ;
wire minidec_div ;
wire minidec_rem ;
wire minidec_divu;
wire minidec_remu;
assign ifu_muldiv_b2b_nxt =
(
// For multiplicaiton, only the MUL instruction following
// MULH/MULHU/MULSU can be treated as back2back
( minidec_mul & dec2ifu_mulhsu)
// For divider and reminder instructions, only the following cases
// can be treated as back2back
// * DIV--REM
// * REM--DIV
// * DIVU--REMU
// * REMU--DIVU
| ( minidec_div & dec2ifu_rem)
| ( minidec_rem & dec2ifu_div)
| ( minidec_divu & dec2ifu_remu)
| ( minidec_remu & dec2ifu_divu)
)
// The last rs1 and rs2 indexes are same as this instruction
& (ir_rs1idx_r == ir_rs1idx_nxt)
& (ir_rs2idx_r == ir_rs2idx_nxt)
// The last rs1 and rs2 indexes are not same as last RD index
& (~(ir_rs1idx_r == ir_rdidx))
& (~(ir_rs2idx_r == ir_rdidx))
;
//////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////
// Next PC generation
wire minidec_bjp;
wire minidec_jal;
wire minidec_jalr;
wire minidec_bxx;
wire [`E203_XLEN-1:0] minidec_bjp_imm;
// The mini-decoder to check instruciton length and branch type
e203_ifu_minidec u_e203_ifu_minidec (
.instr (ifu_ir_nxt ),
.dec_rs1en (minidec_rs1en ),
.dec_rs2en (minidec_rs2en ),
.dec_rs1idx (minidec_rs1idx ),
.dec_rs2idx (minidec_rs2idx ),
.dec_rv32 (minidec_rv32 ),
.dec_bjp (minidec_bjp ),
.dec_jal (minidec_jal ),
.dec_jalr (minidec_jalr ),
.dec_bxx (minidec_bxx ),
.dec_mulhsu (),
.dec_mul (minidec_mul ),
.dec_div (minidec_div ),
.dec_rem (minidec_rem ),
.dec_divu (minidec_divu),
.dec_remu (minidec_remu),
.dec_jalr_rs1idx (minidec_jalr_rs1idx),
.dec_bjp_imm (minidec_bjp_imm )
);
wire bpu_wait;
wire [`E203_PC_SIZE-1:0] prdt_pc_add_op1;
wire [`E203_PC_SIZE-1:0] prdt_pc_add_op2;
e203_ifu_litebpu u_e203_ifu_litebpu(
.pc (pc_r),
.dec_jal (minidec_jal ),
.dec_jalr (minidec_jalr ),
.dec_bxx (minidec_bxx ),
.dec_bjp_imm (minidec_bjp_imm ),
.dec_jalr_rs1idx (minidec_jalr_rs1idx ),
.dec_i_valid (ifu_rsp_valid),
.ir_valid_clr (ir_valid_clr),
.oitf_empty (oitf_empty),
.ir_empty (ir_empty ),
.ir_rs1en (ir_rs1en ),
.jalr_rs1idx_cam_irrdidx (jalr_rs1idx_cam_irrdidx),
.bpu_wait (bpu_wait ),
.prdt_taken (prdt_taken ),
.prdt_pc_add_op1 (prdt_pc_add_op1),
.prdt_pc_add_op2 (prdt_pc_add_op2),
.bpu2rf_rs1_ena (bpu2rf_rs1_ena),
.rf2bpu_x1 (rf2ifu_x1 ),
.rf2bpu_rs1 (rf2ifu_rs1 ),
.clk (clk ) ,
.rst_n (rst_n )
);
// If the instruciton is 32bits length, increament 4, otherwise 2
wire [2:0] pc_incr_ofst = minidec_rv32 ? 3'd4 : 3'd2;
wire [`E203_PC_SIZE-1:0] pc_nxt_pre;
wire [`E203_PC_SIZE-1:0] pc_nxt;
wire bjp_req = minidec_bjp & prdt_taken;
wire ifetch_replay_req;
wire [`E203_PC_SIZE-1:0] pc_add_op1 =
`ifndef E203_TIMING_BOOST//}
pipe_flush_req ? pipe_flush_add_op1 :
dly_pipe_flush_req ? pc_r :
`endif//}
ifetch_replay_req ? pc_r :
bjp_req ? prdt_pc_add_op1 :
ifu_reset_req ? pc_rtvec :
pc_r;
wire [`E203_PC_SIZE-1:0] pc_add_op2 =
`ifndef E203_TIMING_BOOST//}
pipe_flush_req ? pipe_flush_add_op2 :
dly_pipe_flush_req ? `E203_PC_SIZE'b0 :
`endif//}
ifetch_replay_req ? `E203_PC_SIZE'b0 :
bjp_req ? prdt_pc_add_op2 :
ifu_reset_req ? `E203_PC_SIZE'b0 :
pc_incr_ofst ;
assign ifu_req_seq = (~pipe_flush_req_real) & (~ifu_reset_req) & (~ifetch_replay_req) & (~bjp_req);
assign ifu_req_seq_rv32 = minidec_rv32;
assign ifu_req_last_pc = pc_r;
assign pc_nxt_pre = pc_add_op1 + pc_add_op2;
`ifndef E203_TIMING_BOOST//}
assign pc_nxt = {pc_nxt_pre[`E203_PC_SIZE-1:1],1'b0};
`else//}{
assign pc_nxt =
pipe_flush_req ? {pipe_flush_pc[`E203_PC_SIZE-1:1],1'b0} :
dly_pipe_flush_req ? {pc_r[`E203_PC_SIZE-1:1],1'b0} :
{pc_nxt_pre[`E203_PC_SIZE-1:1],1'b0};
`endif//}
// The Ifetch issue new ifetch request when
// * If it is a bjp insturction, and it does not need to wait, and it is not a replay-set cycle
// * and there is no halt_request
wire ifu_new_req = (~bpu_wait) & (~ifu_halt_req) & (~reset_flag_r) & (~ifu_rsp_need_replay);
// The fetch request valid is triggering when
// * New ifetch request
// * or The flush-request is pending
wire ifu_req_valid_pre = ifu_new_req | ifu_reset_req | pipe_flush_req_real | ifetch_replay_req;
// The new request ready condition is:
// * No outstanding reqeusts
// * Or if there is outstanding, but it is reponse valid back
wire out_flag_clr;
wire out_flag_r;
wire new_req_condi = (~out_flag_r) | out_flag_clr;
assign ifu_no_outs = (~out_flag_r) | ifu_rsp_valid;
// Here we use the rsp_valid rather than the out_flag_clr (ifu_rsp_hsked) because
// as long as the rsp_valid is asserting then means last request have returned the
// response back, in WFI case, we cannot expect it to be handshaked (otherwise deadlock)
assign ifu_req_valid = ifu_req_valid_pre & new_req_condi;
//wire ifu_rsp2ir_ready = (ifu_rsp_replay | pipe_flush_req_real) ? 1'b1 : (ifu_ir_i_ready & (~bpu_wait));
wire ifu_rsp2ir_ready = (pipe_flush_req_real) ? 1'b1 : (ifu_ir_i_ready & ifu_req_ready & (~bpu_wait));
// Response channel only ready when:
// * IR is ready to accept new instructions
assign ifu_rsp_ready = ifu_rsp2ir_ready;
// The PC will need to be updated when ifu req channel handshaked or a flush is incoming
wire pc_ena = ifu_req_hsked | pipe_flush_hsked;
sirv_gnrl_dfflr #(`E203_PC_SIZE) pc_dfflr (pc_ena, pc_nxt, pc_r, clk, rst_n);
assign inspect_pc = pc_r;
assign ifu_req_pc = pc_nxt;
// The out_flag will be set if there is a new request handshaked
wire out_flag_set = ifu_req_hsked;
// The out_flag will be cleared if there is a request response handshaked
assign out_flag_clr = ifu_rsp_hsked;
wire out_flag_ena = out_flag_set | out_flag_clr;
// If meanwhile set and clear, then set preempt
wire out_flag_nxt = out_flag_set | (~out_flag_clr);
sirv_gnrl_dfflr #(1) out_flag_dfflr (out_flag_ena, out_flag_nxt, out_flag_r, clk, rst_n);
// The pc_newpend will be set if there is a new PC loaded
wire pc_newpend_set = pc_ena;
// The pc_newpend will be cleared if have already loaded into the IR-PC stage
wire pc_newpend_clr = ir_pc_vld_set;
wire pc_newpend_ena = pc_newpend_set | pc_newpend_clr;
// If meanwhile set and clear, then set preempt
wire pc_newpend_nxt = pc_newpend_set | (~pc_newpend_clr);
sirv_gnrl_dfflr #(1) pc_newpend_dfflr (pc_newpend_ena, pc_newpend_nxt, pc_newpend_r, clk, rst_n);
assign ifu_rsp_need_replay = 1'b0;
assign ifetch_replay_req = 1'b0;
`ifndef FPGA_SOURCE//{
`ifndef DISABLE_SV_ASSERTION//{
//synopsys translate_off
CHECK_IFU_REQ_VALID_NO_X:
assert property (@(posedge clk) disable iff (~rst_n)
(ifu_req_valid !== 1'bx)
)
else $fatal ("\n Error: Oops, detected X value for ifu_req_valid !!! This should never happen. \n");
//synopsys translate_on
`endif//}
`endif//}
endmodule
|
module e203_exu_alu_csrctrl(
//////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////
// The Handshake Interface
//
input csr_i_valid, // Handshake valid
output csr_i_ready, // Handshake ready
input [`E203_XLEN-1:0] csr_i_rs1,
input [`E203_DECINFO_CSR_WIDTH-1:0] csr_i_info,
input csr_i_rdwen,
output csr_ena,
output csr_wr_en,
output csr_rd_en,
output [12-1:0] csr_idx,
input csr_access_ilgl,
input [`E203_XLEN-1:0] read_csr_dat,
output [`E203_XLEN-1:0] wbck_csr_dat,
`ifdef E203_HAS_CSR_EAI//{
output csr_sel_eai,
input eai_xs_off,
output eai_csr_valid,
input eai_csr_ready,
output [31:0] eai_csr_addr,
output eai_csr_wr,
output [31:0] eai_csr_wdata,
input [31:0] eai_csr_rdata,
`endif//}
//////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////
// The CSR Write-back/Commit Interface
output csr_o_valid, // Handshake valid
input csr_o_ready, // Handshake ready
// The Write-Back Interface for Special (unaligned ldst and AMO instructions)
output [`E203_XLEN-1:0] csr_o_wbck_wdat,
output csr_o_wbck_err,
input clk,
input rst_n
);
`ifdef E203_HAS_CSR_EAI//{
// If accessed the EAI CSR range then we need to check if the EAI CSR is ready
assign csr_sel_eai = (csr_idx[11:8] == 4'hE);
wire sel_eai = csr_sel_eai & (~eai_xs_off);
wire addi_condi = sel_eai ? eai_csr_ready : 1'b1;
assign csr_o_valid = csr_i_valid
& addi_condi; // Need to make sure the eai_csr-ready is ready to make sure
// it can be sent to EAI and O interface same cycle
assign eai_csr_valid = sel_eai & csr_i_valid &
csr_o_ready;// Need to make sure the o-ready is ready to make sure
// it can be sent to EAI and O interface same cycle
assign csr_i_ready = sel_eai ? (eai_csr_ready & csr_o_ready) : csr_o_ready;
assign csr_o_wbck_err = csr_access_ilgl;
assign csr_o_wbck_wdat = sel_eai ? eai_csr_rdata : read_csr_dat;
assign eai_csr_addr = csr_idx;
assign eai_csr_wr = csr_wr_en;
assign eai_csr_wdata = wbck_csr_dat;
`else//}{
assign sel_eai = 1'b0;
assign csr_o_valid = csr_i_valid;
assign csr_i_ready = csr_o_ready;
assign csr_o_wbck_err = csr_access_ilgl;
assign csr_o_wbck_wdat = read_csr_dat;
`endif//}
wire csrrw = csr_i_info[`E203_DECINFO_CSR_CSRRW ];
wire csrrs = csr_i_info[`E203_DECINFO_CSR_CSRRS ];
wire csrrc = csr_i_info[`E203_DECINFO_CSR_CSRRC ];
wire rs1imm = csr_i_info[`E203_DECINFO_CSR_RS1IMM];
wire rs1is0 = csr_i_info[`E203_DECINFO_CSR_RS1IS0];
wire [4:0] zimm = csr_i_info[`E203_DECINFO_CSR_ZIMMM ];
wire [11:0] csridx = csr_i_info[`E203_DECINFO_CSR_CSRIDX];
wire [`E203_XLEN-1:0] csr_op1 = rs1imm ? {27'b0,zimm} : csr_i_rs1;
assign csr_rd_en = csr_i_valid &
(
(csrrw ? csr_i_rdwen : 1'b0) // the CSRRW only read when the destination reg need to be writen
| csrrs | csrrc // The set and clear operation always need to read CSR
);
assign csr_wr_en = csr_i_valid & (
csrrw // CSRRW always write the original RS1 value into the CSR
| ((csrrs | csrrc) & (~rs1is0)) // for CSRRS/RC, if the RS is x0, then should not really write
);
assign csr_idx = csridx;
assign csr_ena = csr_o_valid & csr_o_ready & (~sel_eai);
assign wbck_csr_dat =
({`E203_XLEN{csrrw}} & csr_op1)
| ({`E203_XLEN{csrrs}} & ( csr_op1 | read_csr_dat))
| ({`E203_XLEN{csrrc}} & ((~csr_op1) & read_csr_dat));
endmodule
|
module sirv_ResetCatchAndSync(
input clock,
input reset,
input test_mode,
output io_sync_reset
);
wire reset_n_catch_reg_clock;
wire reset_n_catch_reg_reset;
wire [2:0] reset_n_catch_reg_io_d;
wire [2:0] reset_n_catch_reg_io_q;
wire reset_n_catch_reg_io_en;
wire [1:0] T_6;
wire [2:0] T_7;
wire T_8;
wire T_9;
sirv_AsyncResetRegVec_36 reset_n_catch_reg (
.clock(reset_n_catch_reg_clock),
.reset(reset_n_catch_reg_reset),
.io_d(reset_n_catch_reg_io_d),
.io_q(reset_n_catch_reg_io_q),
.io_en(reset_n_catch_reg_io_en)
);
assign io_sync_reset = test_mode ? reset : T_9;
assign reset_n_catch_reg_clock = clock;
assign reset_n_catch_reg_reset = reset;
assign reset_n_catch_reg_io_d = T_7;
assign reset_n_catch_reg_io_en = 1'h1;
assign T_6 = reset_n_catch_reg_io_q[2:1];
assign T_7 = {1'h1,T_6};
assign T_8 = reset_n_catch_reg_io_q[0];
assign T_9 = ~ T_8;
endmodule
|
module sirv_AsyncResetRegVec_36(
input clock,
input reset,
input [2:0] io_d,
output [2:0] io_q,
input io_en
);
wire reg_0_rst;
wire reg_0_clk;
wire reg_0_en;
wire reg_0_q;
wire reg_0_d;
wire reg_1_rst;
wire reg_1_clk;
wire reg_1_en;
wire reg_1_q;
wire reg_1_d;
wire reg_2_rst;
wire reg_2_clk;
wire reg_2_en;
wire reg_2_q;
wire reg_2_d;
wire T_8;
wire T_9;
wire T_10;
wire [1:0] T_11;
wire [2:0] T_12;
sirv_AsyncResetReg reg_0 (
.rst(reg_0_rst),
.clk(reg_0_clk),
.en(reg_0_en),
.q(reg_0_q),
.d(reg_0_d)
);
sirv_AsyncResetReg reg_1 (
.rst(reg_1_rst),
.clk(reg_1_clk),
.en(reg_1_en),
.q(reg_1_q),
.d(reg_1_d)
);
sirv_AsyncResetReg reg_2 (
.rst(reg_2_rst),
.clk(reg_2_clk),
.en(reg_2_en),
.q(reg_2_q),
.d(reg_2_d)
);
assign io_q = T_12;
assign reg_0_rst = reset;
assign reg_0_clk = clock;
assign reg_0_en = io_en;
assign reg_0_d = T_8;
assign reg_1_rst = reset;
assign reg_1_clk = clock;
assign reg_1_en = io_en;
assign reg_1_d = T_9;
assign reg_2_rst = reset;
assign reg_2_clk = clock;
assign reg_2_en = io_en;
assign reg_2_d = T_10;
assign T_8 = io_d[0];
assign T_9 = io_d[1];
assign T_10 = io_d[2];
assign T_11 = {reg_2_q,reg_1_q};
assign T_12 = {T_11,reg_0_q};
endmodule
|
module sirv_qspi_physical_2(
input clock,
input reset,
output io_port_sck,
input io_port_dq_0_i,
output io_port_dq_0_o,
output io_port_dq_0_oe,
input io_port_dq_1_i,
output io_port_dq_1_o,
output io_port_dq_1_oe,
input io_port_dq_2_i,
output io_port_dq_2_o,
output io_port_dq_2_oe,
input io_port_dq_3_i,
output io_port_dq_3_o,
output io_port_dq_3_oe,
output io_port_cs_0,
input [11:0] io_ctrl_sck_div,
input io_ctrl_sck_pol,
input io_ctrl_sck_pha,
input [1:0] io_ctrl_fmt_proto,
input io_ctrl_fmt_endian,
input io_ctrl_fmt_iodir,
output io_op_ready,
input io_op_valid,
input io_op_bits_fn,
input io_op_bits_stb,
input [7:0] io_op_bits_cnt,
input [7:0] io_op_bits_data,
output io_rx_valid,
output [7:0] io_rx_bits
);
reg [11:0] ctrl_sck_div;
reg [31:0] GEN_2;
reg ctrl_sck_pol;
reg [31:0] GEN_31;
reg ctrl_sck_pha;
reg [31:0] GEN_52;
reg [1:0] ctrl_fmt_proto;
reg [31:0] GEN_67;
reg ctrl_fmt_endian;
reg [31:0] GEN_68;
reg ctrl_fmt_iodir;
reg [31:0] GEN_69;
wire proto_0;
wire proto_1;
wire proto_2;
wire accept;
wire sample;
wire setup;
wire last;
reg setup_d;
reg [31:0] GEN_70;
reg T_119;
reg [31:0] GEN_71;
reg T_120;
reg [31:0] GEN_72;
reg sample_d;
reg [31:0] GEN_73;
reg T_122;
reg [31:0] GEN_74;
reg T_123;
reg [31:0] GEN_75;
reg last_d;
reg [31:0] GEN_76;
reg [7:0] scnt;
reg [31:0] GEN_77;
reg [11:0] tcnt;
reg [31:0] GEN_78;
wire stop;
wire beat;
wire [11:0] T_127;
wire [12:0] T_129;
wire [11:0] decr;
wire sched;
wire [11:0] T_130;
reg sck;
reg [31:0] GEN_79;
reg cref;
reg [31:0] GEN_80;
wire cinv;
wire [1:0] T_133;
wire [1:0] T_134;
wire [3:0] rxd;
wire samples_0;
wire [1:0] samples_1;
reg [7:0] buffer;
reg [31:0] GEN_81;
wire T_135;
wire T_136;
wire T_137;
wire T_138;
wire T_139;
wire T_140;
wire T_141;
wire T_142;
wire T_143;
wire [1:0] T_144;
wire [1:0] T_145;
wire [3:0] T_146;
wire [1:0] T_147;
wire [1:0] T_148;
wire [3:0] T_149;
wire [7:0] T_150;
wire [7:0] buffer_in;
wire T_151;
wire shift;
wire [6:0] T_152;
wire [6:0] T_153;
wire [6:0] T_154;
wire T_155;
wire T_157;
wire [7:0] T_158;
wire [5:0] T_159;
wire [5:0] T_160;
wire [5:0] T_161;
wire [1:0] T_162;
wire [1:0] T_163;
wire [7:0] T_164;
wire [3:0] T_165;
wire [3:0] T_166;
wire [3:0] T_167;
wire [3:0] T_169;
wire [7:0] T_170;
wire [7:0] T_172;
wire [7:0] T_174;
wire [7:0] T_176;
wire [7:0] T_178;
wire [7:0] T_179;
wire [7:0] T_180;
reg [3:0] txd;
reg [31:0] GEN_82;
wire [3:0] T_182;
wire [3:0] txd_in;
wire [1:0] T_184;
wire txd_sel_0;
wire txd_sel_1;
wire txd_sel_2;
wire txd_shf_0;
wire [1:0] txd_shf_1;
wire T_186;
wire [1:0] T_188;
wire [3:0] T_190;
wire [1:0] GEN_65;
wire [1:0] T_192;
wire [3:0] GEN_66;
wire [3:0] T_193;
wire [3:0] T_194;
wire [3:0] GEN_0;
wire T_195;
wire T_196;
wire txen_1;
wire txen_0;
wire T_202_0;
wire T_206;
wire T_207;
wire T_208;
wire T_209;
reg done;
reg [31:0] GEN_83;
wire T_212;
wire T_213;
wire T_215;
wire T_216;
wire T_217;
wire T_218;
wire T_219;
wire T_220;
wire T_221;
wire [1:0] T_222;
wire [1:0] T_223;
wire [3:0] T_224;
wire [1:0] T_225;
wire [1:0] T_226;
wire [3:0] T_227;
wire [7:0] T_228;
wire [7:0] T_229;
reg xfr;
reg [31:0] GEN_84;
wire GEN_1;
wire T_234;
wire T_236;
wire T_237;
wire GEN_3;
wire GEN_4;
wire GEN_5;
wire [11:0] GEN_6;
wire GEN_7;
wire GEN_8;
wire GEN_9;
wire GEN_10;
wire [11:0] GEN_11;
wire GEN_12;
wire GEN_13;
wire GEN_14;
wire GEN_15;
wire [11:0] GEN_16;
wire T_243;
wire T_244;
wire T_245;
wire T_248;
wire GEN_17;
wire GEN_18;
wire GEN_19;
wire GEN_20;
wire GEN_21;
wire GEN_22;
wire GEN_23;
wire T_251;
wire [1:0] GEN_24;
wire GEN_25;
wire GEN_26;
wire T_254;
wire T_257;
wire [7:0] GEN_27;
wire GEN_28;
wire GEN_29;
wire GEN_30;
wire GEN_32;
wire [11:0] GEN_33;
wire GEN_34;
wire GEN_35;
wire GEN_36;
wire [11:0] GEN_37;
wire GEN_38;
wire GEN_39;
wire [11:0] GEN_40;
wire [1:0] GEN_41;
wire GEN_42;
wire GEN_43;
wire GEN_44;
wire [7:0] GEN_45;
wire GEN_46;
wire GEN_47;
wire GEN_48;
wire [11:0] GEN_49;
wire GEN_50;
wire GEN_51;
wire [11:0] GEN_53;
wire [1:0] GEN_54;
wire GEN_55;
wire GEN_56;
wire GEN_57;
wire [7:0] GEN_58;
wire GEN_59;
wire GEN_60;
wire GEN_61;
wire [11:0] GEN_62;
wire GEN_63;
wire GEN_64;
assign io_port_sck = sck;
assign io_port_dq_0_o = T_206;
assign io_port_dq_0_oe = txen_0;
assign io_port_dq_1_o = T_207;
assign io_port_dq_1_oe = txen_1;
assign io_port_dq_2_o = T_208;
assign io_port_dq_2_oe = T_196;
assign io_port_dq_3_o = T_209;
assign io_port_dq_3_oe = 1'h0;
assign io_port_cs_0 = T_202_0;
assign io_op_ready = T_251;
assign io_rx_valid = done;
assign io_rx_bits = T_229;
assign proto_0 = 2'h0 == ctrl_fmt_proto;
assign proto_1 = 2'h1 == ctrl_fmt_proto;
assign proto_2 = 2'h2 == ctrl_fmt_proto;
assign accept = GEN_21;
assign sample = GEN_14;
assign setup = GEN_60;
assign last = GEN_20;
assign stop = scnt == 8'h0;
assign beat = tcnt == 12'h0;
assign T_127 = beat ? {{4'd0}, scnt} : tcnt;
assign T_129 = T_127 - 12'h1;
assign decr = T_129[11:0];
assign sched = GEN_1;
assign T_130 = sched ? ctrl_sck_div : decr;
assign cinv = ctrl_sck_pha ^ ctrl_sck_pol;
assign T_133 = {io_port_dq_1_i,io_port_dq_0_i};
assign T_134 = {io_port_dq_3_i,io_port_dq_2_i};
assign rxd = {T_134,T_133};
assign samples_0 = rxd[1];
assign samples_1 = rxd[1:0];
assign T_135 = io_ctrl_fmt_endian == 1'h0;
assign T_136 = io_op_bits_data[0];
assign T_137 = io_op_bits_data[1];
assign T_138 = io_op_bits_data[2];
assign T_139 = io_op_bits_data[3];
assign T_140 = io_op_bits_data[4];
assign T_141 = io_op_bits_data[5];
assign T_142 = io_op_bits_data[6];
assign T_143 = io_op_bits_data[7];
assign T_144 = {T_142,T_143};
assign T_145 = {T_140,T_141};
assign T_146 = {T_145,T_144};
assign T_147 = {T_138,T_139};
assign T_148 = {T_136,T_137};
assign T_149 = {T_148,T_147};
assign T_150 = {T_149,T_146};
assign buffer_in = T_135 ? io_op_bits_data : T_150;
assign T_151 = sample_d & stop;
assign shift = setup_d | T_151;
assign T_152 = buffer[6:0];
assign T_153 = buffer[7:1];
assign T_154 = shift ? T_152 : T_153;
assign T_155 = buffer[0];
assign T_157 = sample_d ? samples_0 : T_155;
assign T_158 = {T_154,T_157};
assign T_159 = buffer[5:0];
assign T_160 = buffer[7:2];
assign T_161 = shift ? T_159 : T_160;
assign T_162 = buffer[1:0];
assign T_163 = sample_d ? samples_1 : T_162;
assign T_164 = {T_161,T_163};
assign T_165 = buffer[3:0];
assign T_166 = buffer[7:4];
assign T_167 = shift ? T_165 : T_166;
assign T_169 = sample_d ? rxd : T_165;
assign T_170 = {T_167,T_169};
assign T_172 = proto_0 ? T_158 : 8'h0;
assign T_174 = proto_1 ? T_164 : 8'h0;
assign T_176 = proto_2 ? T_170 : 8'h0;
assign T_178 = T_172 | T_174;
assign T_179 = T_178 | T_176;
assign T_180 = T_179;
assign T_182 = buffer_in[7:4];
assign txd_in = accept ? T_182 : T_166;
assign T_184 = accept ? io_ctrl_fmt_proto : ctrl_fmt_proto;
assign txd_sel_0 = 2'h0 == T_184;
assign txd_sel_1 = 2'h1 == T_184;
assign txd_sel_2 = 2'h2 == T_184;
assign txd_shf_0 = txd_in[3];
assign txd_shf_1 = txd_in[3:2];
assign T_186 = txd_sel_0 ? txd_shf_0 : 1'h0;
assign T_188 = txd_sel_1 ? txd_shf_1 : 2'h0;
assign T_190 = txd_sel_2 ? txd_in : 4'h0;
assign GEN_65 = {{1'd0}, T_186};
assign T_192 = GEN_65 | T_188;
assign GEN_66 = {{2'd0}, T_192};
assign T_193 = GEN_66 | T_190;
assign T_194 = T_193;
assign GEN_0 = setup ? T_194 : txd;
assign T_195 = proto_1 & ctrl_fmt_iodir;
assign T_196 = proto_2 & ctrl_fmt_iodir;
assign txen_1 = T_195 | T_196;
assign txen_0 = proto_0 | txen_1;
assign T_202_0 = 1'h1;
assign T_206 = txd[0];
assign T_207 = txd[1];
assign T_208 = txd[2];
assign T_209 = txd[3];
assign T_212 = done | last_d;
assign T_213 = ctrl_fmt_endian == 1'h0;
assign T_215 = buffer[1];
assign T_216 = buffer[2];
assign T_217 = buffer[3];
assign T_218 = buffer[4];
assign T_219 = buffer[5];
assign T_220 = buffer[6];
assign T_221 = buffer[7];
assign T_222 = {T_220,T_221};
assign T_223 = {T_218,T_219};
assign T_224 = {T_223,T_222};
assign T_225 = {T_216,T_217};
assign T_226 = {T_155,T_215};
assign T_227 = {T_226,T_225};
assign T_228 = {T_227,T_224};
assign T_229 = T_213 ? buffer : T_228;
assign GEN_1 = stop ? 1'h1 : beat;
assign T_234 = stop == 1'h0;
assign T_236 = cref == 1'h0;
assign T_237 = cref ^ cinv;
assign GEN_3 = xfr ? T_237 : sck;
assign GEN_4 = xfr ? cref : 1'h0;
assign GEN_5 = xfr ? T_236 : 1'h0;
assign GEN_6 = T_236 ? decr : {{4'd0}, scnt};
assign GEN_7 = beat ? T_236 : cref;
assign GEN_8 = beat ? GEN_3 : sck;
assign GEN_9 = beat ? GEN_4 : 1'h0;
assign GEN_10 = beat ? GEN_5 : 1'h0;
assign GEN_11 = beat ? GEN_6 : {{4'd0}, scnt};
assign GEN_12 = T_234 ? GEN_7 : cref;
assign GEN_13 = T_234 ? GEN_8 : sck;
assign GEN_14 = T_234 ? GEN_9 : 1'h0;
assign GEN_15 = T_234 ? GEN_10 : 1'h0;
assign GEN_16 = T_234 ? GEN_11 : {{4'd0}, scnt};
assign T_243 = scnt == 8'h1;
assign T_244 = beat & cref;
assign T_245 = T_244 & xfr;
assign T_248 = beat & T_236;
assign GEN_17 = T_248 ? 1'h1 : stop;
assign GEN_18 = T_248 ? 1'h0 : GEN_15;
assign GEN_19 = T_248 ? ctrl_sck_pol : GEN_13;
assign GEN_20 = T_243 ? T_245 : 1'h0;
assign GEN_21 = T_243 ? GEN_17 : stop;
assign GEN_22 = T_243 ? GEN_18 : GEN_15;
assign GEN_23 = T_243 ? GEN_19 : GEN_13;
assign T_251 = accept & done;
assign GEN_24 = io_op_bits_stb ? io_ctrl_fmt_proto : ctrl_fmt_proto;
assign GEN_25 = io_op_bits_stb ? io_ctrl_fmt_endian : ctrl_fmt_endian;
assign GEN_26 = io_op_bits_stb ? io_ctrl_fmt_iodir : ctrl_fmt_iodir;
assign T_254 = 1'h0 == io_op_bits_fn;
assign T_257 = io_op_bits_cnt == 8'h0;
assign GEN_27 = T_254 ? buffer_in : T_180;
assign GEN_28 = T_254 ? cinv : GEN_23;
assign GEN_29 = T_254 ? 1'h1 : GEN_22;
assign GEN_30 = T_254 ? T_257 : T_212;
assign GEN_32 = io_op_bits_stb ? io_ctrl_sck_pol : GEN_28;
assign GEN_33 = io_op_bits_stb ? io_ctrl_sck_div : ctrl_sck_div;
assign GEN_34 = io_op_bits_stb ? io_ctrl_sck_pol : ctrl_sck_pol;
assign GEN_35 = io_op_bits_stb ? io_ctrl_sck_pha : ctrl_sck_pha;
assign GEN_36 = io_op_bits_fn ? GEN_32 : GEN_28;
assign GEN_37 = io_op_bits_fn ? GEN_33 : ctrl_sck_div;
assign GEN_38 = io_op_bits_fn ? GEN_34 : ctrl_sck_pol;
assign GEN_39 = io_op_bits_fn ? GEN_35 : ctrl_sck_pha;
assign GEN_40 = io_op_valid ? {{4'd0}, io_op_bits_cnt} : GEN_16;
assign GEN_41 = io_op_valid ? GEN_24 : ctrl_fmt_proto;
assign GEN_42 = io_op_valid ? GEN_25 : ctrl_fmt_endian;
assign GEN_43 = io_op_valid ? GEN_26 : ctrl_fmt_iodir;
assign GEN_44 = io_op_valid ? T_254 : xfr;
assign GEN_45 = io_op_valid ? GEN_27 : T_180;
assign GEN_46 = io_op_valid ? GEN_36 : GEN_23;
assign GEN_47 = io_op_valid ? GEN_29 : GEN_22;
assign GEN_48 = io_op_valid ? GEN_30 : T_212;
assign GEN_49 = io_op_valid ? GEN_37 : ctrl_sck_div;
assign GEN_50 = io_op_valid ? GEN_38 : ctrl_sck_pol;
assign GEN_51 = io_op_valid ? GEN_39 : ctrl_sck_pha;
assign GEN_53 = T_251 ? GEN_40 : GEN_16;
assign GEN_54 = T_251 ? GEN_41 : ctrl_fmt_proto;
assign GEN_55 = T_251 ? GEN_42 : ctrl_fmt_endian;
assign GEN_56 = T_251 ? GEN_43 : ctrl_fmt_iodir;
assign GEN_57 = T_251 ? GEN_44 : xfr;
assign GEN_58 = T_251 ? GEN_45 : T_180;
assign GEN_59 = T_251 ? GEN_46 : GEN_23;
assign GEN_60 = T_251 ? GEN_47 : GEN_22;
assign GEN_61 = T_251 ? GEN_48 : T_212;
assign GEN_62 = T_251 ? GEN_49 : ctrl_sck_div;
assign GEN_63 = T_251 ? GEN_50 : ctrl_sck_pol;
assign GEN_64 = T_251 ? GEN_51 : ctrl_sck_pha;
always @(posedge clock or posedge reset)
if (reset) begin
ctrl_sck_div <= 12'b0;
ctrl_sck_pol <= 1'b0;
ctrl_sck_pha <= 1'b0;
ctrl_fmt_proto <= 2'b0;
ctrl_fmt_endian <= 1'b0;
ctrl_fmt_iodir <= 1'b0;
setup_d <= 1'b0;
tcnt <= 12'b0;
sck <= 1'b0;
buffer <= 8'b0;
xfr <= 1'b0;
end
else begin
if (T_251) begin
if (io_op_valid) begin
if (io_op_bits_fn) begin
if (io_op_bits_stb) begin
ctrl_sck_div <= io_ctrl_sck_div;
end
end
end
end
if (T_251) begin
if (io_op_valid) begin
if (io_op_bits_fn) begin
if (io_op_bits_stb) begin
ctrl_sck_pol <= io_ctrl_sck_pol;
end
end
end
end
if (T_251) begin
if (io_op_valid) begin
if (io_op_bits_fn) begin
if (io_op_bits_stb) begin
ctrl_sck_pha <= io_ctrl_sck_pha;
end
end
end
end
if (T_251) begin
if (io_op_valid) begin
if (io_op_bits_stb) begin
ctrl_fmt_proto <= io_ctrl_fmt_proto;
end
end
end
if (T_251) begin
if (io_op_valid) begin
if (io_op_bits_stb) begin
ctrl_fmt_endian <= io_ctrl_fmt_endian;
end
end
end
if (T_251) begin
if (io_op_valid) begin
if (io_op_bits_stb) begin
ctrl_fmt_iodir <= io_ctrl_fmt_iodir;
end
end
end
setup_d <= setup;
if (sched) begin
tcnt <= ctrl_sck_div;
end else begin
tcnt <= decr;
end
if (T_251) begin
if (io_op_valid) begin
if (io_op_bits_fn) begin
if (io_op_bits_stb) begin
sck <= io_ctrl_sck_pol;
end else begin
if (T_254) begin
sck <= cinv;
end else begin
if (T_243) begin
if (T_248) begin
sck <= ctrl_sck_pol;
end else begin
if (T_234) begin
if (beat) begin
if (xfr) begin
sck <= T_237;
end
end
end
end
end else begin
if (T_234) begin
if (beat) begin
if (xfr) begin
sck <= T_237;
end
end
end
end
end
end
end else begin
if (T_254) begin
sck <= cinv;
end else begin
if (T_243) begin
if (T_248) begin
sck <= ctrl_sck_pol;
end else begin
if (T_234) begin
if (beat) begin
if (xfr) begin
sck <= T_237;
end
end
end
end
end else begin
if (T_234) begin
if (beat) begin
if (xfr) begin
sck <= T_237;
end
end
end
end
end
end
end else begin
if (T_243) begin
if (T_248) begin
sck <= ctrl_sck_pol;
end else begin
sck <= GEN_13;
end
end else begin
sck <= GEN_13;
end
end
end else begin
if (T_243) begin
if (T_248) begin
sck <= ctrl_sck_pol;
end else begin
sck <= GEN_13;
end
end else begin
sck <= GEN_13;
end
end
if (T_251) begin
if (io_op_valid) begin
if (T_254) begin
if (T_135) begin
buffer <= io_op_bits_data;
end else begin
buffer <= T_150;
end
end else begin
buffer <= T_180;
end
end else begin
buffer <= T_180;
end
end else begin
buffer <= T_180;
end
if (T_251) begin
if (io_op_valid) begin
xfr <= T_254;
end
end
end
always @(posedge clock or posedge reset)
if (reset) begin
cref <= 1'h1;
end else begin
if (T_234) begin
if (beat) begin
cref <= T_236;
end
end
end
always @(posedge clock or posedge reset)
if (reset) begin
txd <= 4'h0;
end else begin
if (setup) begin
txd <= T_194;
end
end
always @(posedge clock or posedge reset)
if (reset) begin
done <= 1'h1;
end else begin
if (T_251) begin
if (io_op_valid) begin
if (T_254) begin
done <= T_257;
end else begin
done <= T_212;
end
end else begin
done <= T_212;
end
end else begin
done <= T_212;
end
end
always @(posedge clock or posedge reset)
if (reset) begin
T_119 <= 1'h0;
end else begin
T_119 <= sample;
end
always @(posedge clock or posedge reset)
if (reset) begin
T_120 <= 1'h0;
end else begin
T_120 <= T_119;
end
always @(posedge clock or posedge reset)
if (reset) begin
sample_d <= 1'h0;
end else begin
sample_d <= T_120;
end
always @(posedge clock or posedge reset)
if (reset) begin
T_122 <= 1'h0;
end else begin
T_122 <= last;
end
always @(posedge clock or posedge reset)
if (reset) begin
T_123 <= 1'h0;
end else begin
T_123 <= T_122;
end
always @(posedge clock or posedge reset)
if (reset) begin
last_d <= 1'h0;
end else begin
last_d <= T_123;
end
always @(posedge clock or posedge reset)
if (reset) begin
scnt <= 8'h0;
end else begin
scnt <= GEN_53[7:0];
end
endmodule
|
module sirv_otp_top(
input clk,
input rst_n,
input i_icb_cmd_valid,
output i_icb_cmd_ready,
input [32-1:0] i_icb_cmd_addr,
input i_icb_cmd_read,
input [32-1:0] i_icb_cmd_wdata,
output i_icb_rsp_valid,
input i_icb_rsp_ready,
output [32-1:0] i_icb_rsp_rdata,
input f_icb_cmd_valid,
output f_icb_cmd_ready,
input [32-1:0] f_icb_cmd_addr,
input f_icb_cmd_read,
input [32-1:0] f_icb_cmd_wdata,
output f_icb_rsp_valid,
input f_icb_rsp_ready,
output [32-1:0] f_icb_rsp_rdata
);
assign i_icb_cmd_ready = 1'b0;
assign i_icb_rsp_valid = 1'b0;
assign i_icb_rsp_rdata = 32'b0;
assign f_icb_cmd_ready = 1'b0;
assign f_icb_rsp_valid = 1'b0;
assign f_icb_rsp_rdata = 32'b0;
// In FPGA platform this module is just an empty wrapper
endmodule
|
module e203_exu_alu_bjp(
//////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////
// The Handshake Interface
//
input bjp_i_valid, // Handshake valid
output bjp_i_ready, // Handshake ready
input [`E203_XLEN-1:0] bjp_i_rs1,
input [`E203_XLEN-1:0] bjp_i_rs2,
input [`E203_XLEN-1:0] bjp_i_imm,
input [`E203_PC_SIZE-1:0] bjp_i_pc,
input [`E203_DECINFO_BJP_WIDTH-1:0] bjp_i_info,
//////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////
// The BJP Commit Interface
output bjp_o_valid, // Handshake valid
input bjp_o_ready, // Handshake ready
// The Write-Back Result for JAL and JALR
output [`E203_XLEN-1:0] bjp_o_wbck_wdat,
output bjp_o_wbck_err,
// The Commit Result for BJP
output bjp_o_cmt_bjp,
output bjp_o_cmt_mret,
output bjp_o_cmt_dret,
output bjp_o_cmt_fencei,
output bjp_o_cmt_prdt,// The predicted ture/false
output bjp_o_cmt_rslv,// The resolved ture/false
//////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////
// To share the ALU datapath
//
// The operands and info to ALU
output [`E203_XLEN-1:0] bjp_req_alu_op1,
output [`E203_XLEN-1:0] bjp_req_alu_op2,
output bjp_req_alu_cmp_eq ,
output bjp_req_alu_cmp_ne ,
output bjp_req_alu_cmp_lt ,
output bjp_req_alu_cmp_gt ,
output bjp_req_alu_cmp_ltu,
output bjp_req_alu_cmp_gtu,
output bjp_req_alu_add,
input bjp_req_alu_cmp_res,
input [`E203_XLEN-1:0] bjp_req_alu_add_res,
input clk,
input rst_n
);
wire mret = bjp_i_info [`E203_DECINFO_BJP_MRET ];
wire dret = bjp_i_info [`E203_DECINFO_BJP_DRET ];
wire fencei = bjp_i_info [`E203_DECINFO_BJP_FENCEI ];
wire bxx = bjp_i_info [`E203_DECINFO_BJP_BXX ];
wire jump = bjp_i_info [`E203_DECINFO_BJP_JUMP ];
wire rv32 = bjp_i_info [`E203_DECINFO_RV32];
wire wbck_link = jump;
wire bjp_i_bprdt = bjp_i_info [`E203_DECINFO_BJP_BPRDT ];
assign bjp_req_alu_op1 = wbck_link ?
bjp_i_pc
: bjp_i_rs1;
assign bjp_req_alu_op2 = wbck_link ?
(rv32 ? `E203_XLEN'd4 : `E203_XLEN'd2)
: bjp_i_rs2;
assign bjp_o_cmt_bjp = bxx | jump;
assign bjp_o_cmt_mret = mret;
assign bjp_o_cmt_dret = dret;
assign bjp_o_cmt_fencei = fencei;
assign bjp_req_alu_cmp_eq = bjp_i_info [`E203_DECINFO_BJP_BEQ ];
assign bjp_req_alu_cmp_ne = bjp_i_info [`E203_DECINFO_BJP_BNE ];
assign bjp_req_alu_cmp_lt = bjp_i_info [`E203_DECINFO_BJP_BLT ];
assign bjp_req_alu_cmp_gt = bjp_i_info [`E203_DECINFO_BJP_BGT ];
assign bjp_req_alu_cmp_ltu = bjp_i_info [`E203_DECINFO_BJP_BLTU ];
assign bjp_req_alu_cmp_gtu = bjp_i_info [`E203_DECINFO_BJP_BGTU ];
assign bjp_req_alu_add = wbck_link;
assign bjp_o_valid = bjp_i_valid;
assign bjp_i_ready = bjp_o_ready;
assign bjp_o_cmt_prdt = bjp_i_bprdt;
assign bjp_o_cmt_rslv = jump ? 1'b1 : bjp_req_alu_cmp_res;
assign bjp_o_wbck_wdat = bjp_req_alu_add_res;
assign bjp_o_wbck_err = 1'b0;
endmodule
|
module sirv_mrom_top #(
parameter AW = 12,
parameter DW = 32,
parameter DP = 1024
)(
// * Bus cmd channel
input rom_icb_cmd_valid, // Handshake valid
output rom_icb_cmd_ready, // Handshake ready
input [AW-1:0] rom_icb_cmd_addr, // Bus transaction start addr
input rom_icb_cmd_read, // Read or write
// * Bus RSP channel
output rom_icb_rsp_valid, // Response valid
input rom_icb_rsp_ready, // Response ready
output rom_icb_rsp_err, // Response error
output [DW-1:0] rom_icb_rsp_rdata,
input clk,
input rst_n
);
wire [DW-1:0] rom_dout;
assign rom_icb_rsp_valid = rom_icb_cmd_valid;
assign rom_icb_cmd_ready = rom_icb_rsp_ready;
assign rom_icb_rsp_err = ~rom_icb_cmd_read;
assign rom_icb_rsp_rdata = rom_dout;
sirv_mrom # (
.AW(AW),
.DW(DW),
.DP(DP)
)u_sirv_mrom (
.rom_addr (rom_icb_cmd_addr[AW-1:2]),
.rom_dout (rom_dout)
);
endmodule
|
module e203_subsys_hclkgen(
input test_mode,
input hfclkrst,// To reset the PLL Clock
input hfextclk,// The original clock from crystal
input pllbypass ,
input pll_RESET ,
input pll_ASLEEP ,
input [1:0] pll_OD,
input [7:0] pll_M,
input [4:0] pll_N,
input plloutdivby1,
input [5:0] plloutdiv,
output inspect_16m_clk,
output inspect_pll_clk,
output hfclk// The generated clock by this module
);
wire hfclkrst_n = ~hfclkrst;
// The PLL module
wire plloutclk;
wire pll_powerd = pll_ASLEEP | hfclkrst; // Power down by PMU or the register programmed
e203_subsys_pll u_e203_subsys_pll(
.pll_asleep (pll_powerd ),
.pll_RESET (pll_RESET),
.pll_OD (pll_OD),
.pll_M (pll_M ),
.pll_N (pll_N ),
.pllrefclk (hfextclk ),
.plloutclk (plloutclk )
);
// The Reset syncer for the PLLout clk
wire plloutclk_rst_n;
e203_subsys_hclkgen_rstsync plloutclk_rstsync(
.clk (plloutclk),
.rst_n_a (hfclkrst_n),
.test_mode(test_mode),
.rst_n (plloutclk_rst_n)
);
// The Reset syncer for the HFextclk
wire hfextclk_rst_n;
e203_subsys_hclkgen_rstsync hfextclk_rstsync(
.clk (hfextclk),
.rst_n_a (hfclkrst_n),
.test_mode(test_mode),
.rst_n (hfextclk_rst_n)
);
// The PLL divider
wire plloutdivclk;
e203_subsys_pllclkdiv u_e203_subsys_pllclkdiv(
.test_mode(test_mode),
.rst_n (plloutclk_rst_n),
.divby1(plloutdivby1),
.div (plloutdiv ),
.clk (plloutclk),// The PLL clock
.clkout(plloutdivclk) // The divided Clock
);
// The glitch free clock mux
wire gfcm_clk;
e203_subsys_gfcm u_e203_subsys_gfcm(
.test_mode(test_mode),
.clk0_rst_n (plloutclk_rst_n),
.clk1_rst_n (hfextclk_rst_n),
.sel1 (pllbypass),
.clk0 (plloutdivclk),// The divided PLL clock
.clk1 (hfextclk),// The original Crystal clock
.clkout (gfcm_clk)
);
assign hfclk = test_mode ? hfextclk : gfcm_clk;
assign inspect_16m_clk = hfextclk ;
assign inspect_pll_clk = plloutclk;
endmodule
|
module e203_exu(
output commit_mret,
output commit_trap,
output exu_active,
output excp_active,
output core_wfi,
output tm_stop,
output itcm_nohold,
output core_cgstop,
output tcm_cgstop,
input [`E203_HART_ID_W-1:0] core_mhartid,
input dbg_irq_r,
input [`E203_LIRQ_NUM-1:0] lcl_irq_r,
input [`E203_EVT_NUM-1:0] evt_r,
input ext_irq_r,
input sft_irq_r,
input tmr_irq_r,
//////////////////////////////////////////////////////////////
// From/To debug ctrl module
output [`E203_PC_SIZE-1:0] cmt_dpc,
output cmt_dpc_ena,
output [3-1:0] cmt_dcause,
output cmt_dcause_ena,
output wr_dcsr_ena ,
output wr_dpc_ena ,
output wr_dscratch_ena,
output [`E203_XLEN-1:0] wr_csr_nxt ,
input [`E203_XLEN-1:0] dcsr_r ,
input [`E203_PC_SIZE-1:0] dpc_r ,
input [`E203_XLEN-1:0] dscratch_r,
input dbg_mode,
input dbg_halt_r,
input dbg_step_r,
input dbg_ebreakm_r,
input dbg_stopcycle,
//////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////
// The IFU IR stage to EXU interface
input i_valid, // Handshake signals with EXU stage
output i_ready,
input [`E203_INSTR_SIZE-1:0] i_ir,// The instruction register
input [`E203_PC_SIZE-1:0] i_pc, // The PC register along with
input i_pc_vld,
input i_misalgn, // The fetch misalign
input i_buserr, // The fetch bus error
input i_prdt_taken,
input i_muldiv_b2b,
input [`E203_RFIDX_WIDTH-1:0] i_rs1idx, // The RS1 index
input [`E203_RFIDX_WIDTH-1:0] i_rs2idx, // The RS2 index
//////////////////////////////////////////////////////////////
// The Flush interface to IFU
//
// To save the gatecount, when we need to flush pipeline with new PC,
// we want to reuse the adder in IFU, so we will not pass flush-PC
// to IFU, instead, we pass the flush-pc-adder-op1/op2 to IFU
// and IFU will just use its adder to caculate the flush-pc-adder-result
//
input pipe_flush_ack,
output pipe_flush_req,
output [`E203_PC_SIZE-1:0] pipe_flush_add_op1,
output [`E203_PC_SIZE-1:0] pipe_flush_add_op2,
`ifdef E203_TIMING_BOOST//}
output [`E203_PC_SIZE-1:0] pipe_flush_pc,
`endif//}
//////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////
// The LSU Write-Back Interface
input lsu_o_valid, // Handshake valid
output lsu_o_ready, // Handshake ready
input [`E203_XLEN-1:0] lsu_o_wbck_wdat,
input [`E203_ITAG_WIDTH -1:0] lsu_o_wbck_itag,
input lsu_o_wbck_err ,
input lsu_o_cmt_ld,
input lsu_o_cmt_st,
input [`E203_ADDR_SIZE -1:0] lsu_o_cmt_badaddr,
input lsu_o_cmt_buserr , // The bus-error exception generated
output wfi_halt_ifu_req,
input wfi_halt_ifu_ack,
output oitf_empty,
output [`E203_XLEN-1:0] rf2ifu_x1,
output [`E203_XLEN-1:0] rf2ifu_rs1,
output dec2ifu_rden,
output dec2ifu_rs1en,
output [`E203_RFIDX_WIDTH-1:0] dec2ifu_rdidx,
output dec2ifu_mulhsu,
output dec2ifu_div ,
output dec2ifu_rem ,
output dec2ifu_divu ,
output dec2ifu_remu ,
//////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////
// The AGU ICB Interface to LSU-ctrl
// * Bus cmd channel
output agu_icb_cmd_valid, // Handshake valid
input agu_icb_cmd_ready, // Handshake ready
output [`E203_ADDR_SIZE-1:0] agu_icb_cmd_addr, // Bus transaction start addr
output agu_icb_cmd_read, // Read or write
output [`E203_XLEN-1:0] agu_icb_cmd_wdata,
output [`E203_XLEN/8-1:0] agu_icb_cmd_wmask,
output agu_icb_cmd_lock,
output agu_icb_cmd_excl,
output [1:0] agu_icb_cmd_size,
// Several additional side channel signals
// Indicate LSU-ctrl module to
// return the ICB response channel back to AGU
// this is only used by AMO or unaligned load/store 1st uop
// to return the response
output agu_icb_cmd_back2agu,
// Sign extension or not
output agu_icb_cmd_usign,
output [`E203_ITAG_WIDTH -1:0] agu_icb_cmd_itag,
// * Bus RSP channel
input agu_icb_rsp_valid, // Response valid
output agu_icb_rsp_ready, // Response ready
input agu_icb_rsp_err , // Response error
input agu_icb_rsp_excl_ok,
input [`E203_XLEN-1:0] agu_icb_rsp_rdata,
`ifdef E203_HAS_CSR_EAI//{
output eai_csr_valid,
input eai_csr_ready,
output [31:0] eai_csr_addr,
output eai_csr_wr,
output [31:0] eai_csr_wdata,
input [31:0] eai_csr_rdata,
`endif//}
input test_mode,
input clk_aon,
input clk,
input rst_n
);
//////////////////////////////////////////////////////////////
// Instantiate the Regfile
wire [`E203_XLEN-1:0] rf_rs1;
wire [`E203_XLEN-1:0] rf_rs2;
wire rf_wbck_ena;
wire [`E203_XLEN-1:0] rf_wbck_wdat;
wire [`E203_RFIDX_WIDTH-1:0] rf_wbck_rdidx;
e203_exu_regfile u_e203_exu_regfile(
.read_src1_idx (i_rs1idx ),
.read_src2_idx (i_rs2idx ),
.read_src1_dat (rf_rs1),
.read_src2_dat (rf_rs2),
.x1_r (rf2ifu_x1),
.wbck_dest_wen (rf_wbck_ena),
.wbck_dest_idx (rf_wbck_rdidx),
.wbck_dest_dat (rf_wbck_wdat),
.test_mode (test_mode),
.clk (clk ),
.rst_n (rst_n )
);
wire dec_rs1en;
wire dec_rs2en;
//////////////////////////////////////////////////////////////
// Instantiate the Decode
wire [`E203_DECINFO_WIDTH-1:0] dec_info;
wire [`E203_XLEN-1:0] dec_imm;
wire [`E203_PC_SIZE-1:0] dec_pc;
wire dec_rs1x0;
wire dec_rs2x0;
wire dec_rdwen;
wire [`E203_RFIDX_WIDTH-1:0] dec_rdidx;
wire dec_misalgn;
wire dec_buserr;
wire dec_ilegl;
//////////////////////////////////////////////////////////////
// The Decoded Info-Bus
e203_exu_decode u_e203_exu_decode (
.dbg_mode (dbg_mode),
.i_instr (i_ir ),
.i_pc (i_pc ),
.i_misalgn (i_misalgn),
.i_buserr (i_buserr ),
.i_prdt_taken (i_prdt_taken),
.i_muldiv_b2b (i_muldiv_b2b),
.dec_rv32 (),
.dec_bjp (),
.dec_jal (),
.dec_jalr (),
.dec_bxx (),
.dec_jalr_rs1idx(),
.dec_bjp_imm(),
.dec_mulhsu (dec2ifu_mulhsu),
.dec_mul (),
.dec_div (dec2ifu_div ),
.dec_rem (dec2ifu_rem ),
.dec_divu (dec2ifu_divu ),
.dec_remu (dec2ifu_remu ),
.dec_info (dec_info ),
.dec_rs1x0 (dec_rs1x0),
.dec_rs2x0 (dec_rs2x0),
.dec_rs1en (dec_rs1en),
.dec_rs2en (dec_rs2en),
.dec_rdwen (dec_rdwen),
.dec_rs1idx(),
.dec_rs2idx(),
.dec_misalgn(dec_misalgn),
.dec_buserr (dec_buserr ),
.dec_ilegl (dec_ilegl),
.dec_rdidx (dec_rdidx),
.dec_pc (dec_pc),
.dec_imm (dec_imm)
);
//////////////////////////////////////////////////////////////
// Instantiate the Dispatch
wire disp_alu_valid;
wire disp_alu_ready;
wire disp_alu_longpipe;
wire [`E203_ITAG_WIDTH-1:0] disp_alu_itag;
wire [`E203_XLEN-1:0] disp_alu_rs1;
wire [`E203_XLEN-1:0] disp_alu_rs2;
wire [`E203_XLEN-1:0] disp_alu_imm;
wire [`E203_DECINFO_WIDTH-1:0] disp_alu_info;
wire [`E203_PC_SIZE-1:0] disp_alu_pc;
wire [`E203_RFIDX_WIDTH-1:0] disp_alu_rdidx;
wire disp_alu_rdwen;
wire disp_alu_ilegl;
wire disp_alu_misalgn;
wire disp_alu_buserr;
wire [`E203_ITAG_WIDTH-1:0] disp_oitf_ptr;
wire disp_oitf_ready;
wire disp_oitf_rs1fpu;
wire disp_oitf_rs2fpu;
wire disp_oitf_rs3fpu;
wire disp_oitf_rdfpu;
wire [`E203_RFIDX_WIDTH-1:0] disp_oitf_rs1idx;
wire [`E203_RFIDX_WIDTH-1:0] disp_oitf_rs2idx;
wire [`E203_RFIDX_WIDTH-1:0] disp_oitf_rs3idx;
wire [`E203_RFIDX_WIDTH-1:0] disp_oitf_rdidx;
wire disp_oitf_rs1en;
wire disp_oitf_rs2en;
wire disp_oitf_rs3en;
wire disp_oitf_rdwen;
wire [`E203_PC_SIZE-1:0] disp_oitf_pc;
wire oitfrd_match_disprs1;
wire oitfrd_match_disprs2;
wire oitfrd_match_disprs3;
wire oitfrd_match_disprd;
wire disp_oitf_ena;
wire wfi_halt_exu_req;
wire wfi_halt_exu_ack;
wire amo_wait;
e203_exu_disp u_e203_exu_disp(
.wfi_halt_exu_req (wfi_halt_exu_req),
.wfi_halt_exu_ack (wfi_halt_exu_ack),
.oitf_empty (oitf_empty),
.amo_wait (amo_wait),
.disp_i_valid (i_valid ),
.disp_i_ready (i_ready ),
.disp_i_rs1x0 (dec_rs1x0 ),
.disp_i_rs2x0 (dec_rs2x0 ),
.disp_i_rs1en (dec_rs1en ),
.disp_i_rs2en (dec_rs2en ),
.disp_i_rs1idx (i_rs1idx ),
.disp_i_rs2idx (i_rs2idx ),
.disp_i_rdwen (dec_rdwen ),
.disp_i_rdidx (dec_rdidx ),
.disp_i_info (dec_info ),
.disp_i_rs1 (rf_rs1 ),
.disp_i_rs2 (rf_rs2 ),
.disp_i_imm (dec_imm ),
.disp_i_pc (dec_pc ),
.disp_i_misalgn (dec_misalgn ),
.disp_i_buserr (dec_buserr ),
.disp_i_ilegl (dec_ilegl ),
.disp_o_alu_valid (disp_alu_valid ),
.disp_o_alu_ready (disp_alu_ready ),
.disp_o_alu_longpipe (disp_alu_longpipe),
.disp_o_alu_itag (disp_alu_itag ),
.disp_o_alu_rs1 (disp_alu_rs1 ),
.disp_o_alu_rs2 (disp_alu_rs2 ),
.disp_o_alu_rdwen (disp_alu_rdwen ),
.disp_o_alu_rdidx (disp_alu_rdidx ),
.disp_o_alu_info (disp_alu_info ),
.disp_o_alu_pc (disp_alu_pc ),
.disp_o_alu_imm (disp_alu_imm ),
.disp_o_alu_misalgn (disp_alu_misalgn ),
.disp_o_alu_buserr (disp_alu_buserr ),
.disp_o_alu_ilegl (disp_alu_ilegl ),
.disp_oitf_ena (disp_oitf_ena ),
.disp_oitf_ptr (disp_oitf_ptr ),
.disp_oitf_ready (disp_oitf_ready ),
.disp_oitf_rs1en (disp_oitf_rs1en),
.disp_oitf_rs2en (disp_oitf_rs2en),
.disp_oitf_rs3en (disp_oitf_rs3en),
.disp_oitf_rdwen (disp_oitf_rdwen ),
.disp_oitf_rs1idx (disp_oitf_rs1idx),
.disp_oitf_rs2idx (disp_oitf_rs2idx),
.disp_oitf_rs3idx (disp_oitf_rs3idx),
.disp_oitf_rdidx (disp_oitf_rdidx ),
.disp_oitf_rs1fpu (disp_oitf_rs1fpu),
.disp_oitf_rs2fpu (disp_oitf_rs2fpu),
.disp_oitf_rs3fpu (disp_oitf_rs3fpu),
.disp_oitf_rdfpu (disp_oitf_rdfpu),
.disp_oitf_pc (disp_oitf_pc),
.oitfrd_match_disprs1(oitfrd_match_disprs1),
.oitfrd_match_disprs2(oitfrd_match_disprs2),
.oitfrd_match_disprs3(oitfrd_match_disprs3),
.oitfrd_match_disprd (oitfrd_match_disprd ),
.clk (clk ),
.rst_n (rst_n)
);
//////////////////////////////////////////////////////////////
// Instantiate the OITF
wire oitf_ret_ena;
wire [`E203_ITAG_WIDTH-1:0] oitf_ret_ptr;
wire [`E203_RFIDX_WIDTH-1:0] oitf_ret_rdidx;
wire [`E203_PC_SIZE-1:0] oitf_ret_pc;
wire oitf_ret_rdwen;
wire oitf_ret_rdfpu;
e203_exu_oitf u_e203_exu_oitf(
.dis_ready (disp_oitf_ready),
.dis_ena (disp_oitf_ena ),
.ret_ena (oitf_ret_ena ),
.dis_ptr (disp_oitf_ptr ),
.ret_ptr (oitf_ret_ptr ),
.ret_rdidx (oitf_ret_rdidx),
.ret_rdwen (oitf_ret_rdwen),
.ret_rdfpu (oitf_ret_rdfpu),
.ret_pc (oitf_ret_pc),
.disp_i_rs1en (disp_oitf_rs1en),
.disp_i_rs2en (disp_oitf_rs2en),
.disp_i_rs3en (disp_oitf_rs3en),
.disp_i_rdwen (disp_oitf_rdwen ),
.disp_i_rs1idx (disp_oitf_rs1idx),
.disp_i_rs2idx (disp_oitf_rs2idx),
.disp_i_rs3idx (disp_oitf_rs3idx),
.disp_i_rdidx (disp_oitf_rdidx ),
.disp_i_rs1fpu (disp_oitf_rs1fpu),
.disp_i_rs2fpu (disp_oitf_rs2fpu),
.disp_i_rs3fpu (disp_oitf_rs3fpu),
.disp_i_rdfpu (disp_oitf_rdfpu ),
.disp_i_pc (disp_oitf_pc ),
.oitfrd_match_disprs1 (oitfrd_match_disprs1),
.oitfrd_match_disprs2 (oitfrd_match_disprs2),
.oitfrd_match_disprs3 (oitfrd_match_disprs3),
.oitfrd_match_disprd (oitfrd_match_disprd ),
.oitf_empty (oitf_empty ),
.clk (clk ),
.rst_n (rst_n )
);
//////////////////////////////////////////////////////////////
// Instantiate the ALU
wire alu_wbck_o_valid;
wire alu_wbck_o_ready;
wire [`E203_XLEN-1:0] alu_wbck_o_wdat;
wire [`E203_RFIDX_WIDTH-1:0] alu_wbck_o_rdidx;
wire alu_cmt_valid;
wire alu_cmt_ready;
wire alu_cmt_pc_vld;
wire [`E203_PC_SIZE-1:0] alu_cmt_pc;
wire [`E203_INSTR_SIZE-1:0] alu_cmt_instr;
wire [`E203_XLEN-1:0] alu_cmt_imm;
wire alu_cmt_rv32;
wire alu_cmt_bjp;
wire alu_cmt_mret;
wire alu_cmt_dret;
wire alu_cmt_ecall;
wire alu_cmt_ebreak;
wire alu_cmt_wfi;
wire alu_cmt_fencei;
wire alu_cmt_ifu_misalgn;
wire alu_cmt_ifu_buserr;
wire alu_cmt_ifu_ilegl;
wire alu_cmt_bjp_prdt;
wire alu_cmt_bjp_rslv;
wire alu_cmt_misalgn;
wire alu_cmt_ld;
wire alu_cmt_stamo;
wire alu_cmt_buserr;
wire [`E203_ADDR_SIZE-1:0] alu_cmt_badaddr;
wire csr_ena;
wire csr_wr_en;
wire csr_rd_en;
wire [12-1:0] csr_idx;
wire [`E203_XLEN-1:0] read_csr_dat;
wire [`E203_XLEN-1:0] wbck_csr_dat;
wire flush_pulse;
wire flush_req;
wire nonflush_cmt_ena;
wire eai_xs_off;
wire csr_access_ilgl;
wire mdv_nob2b;
e203_exu_alu u_e203_exu_alu(
`ifdef E203_HAS_CSR_EAI//{
.eai_csr_valid (eai_csr_valid),
.eai_csr_ready (eai_csr_ready),
.eai_csr_addr (eai_csr_addr ),
.eai_csr_wr (eai_csr_wr ),
.eai_csr_wdata (eai_csr_wdata),
.eai_csr_rdata (eai_csr_rdata),
`endif//}
.csr_access_ilgl (csr_access_ilgl),
.nonflush_cmt_ena (nonflush_cmt_ena),
.i_valid (disp_alu_valid ),
.i_ready (disp_alu_ready ),
.i_longpipe (disp_alu_longpipe),
.i_itag (disp_alu_itag ),
.i_rs1 (disp_alu_rs1 ),
.i_rs2 (disp_alu_rs2 ),
.eai_xs_off (eai_xs_off),
.i_rdwen (disp_alu_rdwen ),
.i_rdidx (disp_alu_rdidx ),
.i_info (disp_alu_info ),
.i_pc (i_pc ),
.i_pc_vld (i_pc_vld),
.i_instr (i_ir ),
.i_imm (disp_alu_imm ),
.i_misalgn (disp_alu_misalgn ),
.i_buserr (disp_alu_buserr ),
.i_ilegl (disp_alu_ilegl ),
.flush_pulse (flush_pulse ),
.flush_req (flush_req ),
.oitf_empty (oitf_empty),
.amo_wait (amo_wait),
.cmt_o_valid (alu_cmt_valid ),
.cmt_o_ready (alu_cmt_ready ),
.cmt_o_pc_vld (alu_cmt_pc_vld ),
.cmt_o_pc (alu_cmt_pc ),
.cmt_o_instr (alu_cmt_instr ),
.cmt_o_imm (alu_cmt_imm ),
.cmt_o_rv32 (alu_cmt_rv32 ),
.cmt_o_bjp (alu_cmt_bjp ),
.cmt_o_dret (alu_cmt_dret ),
.cmt_o_mret (alu_cmt_mret ),
.cmt_o_ecall (alu_cmt_ecall ),
.cmt_o_ebreak (alu_cmt_ebreak ),
.cmt_o_fencei (alu_cmt_fencei ),
.cmt_o_wfi (alu_cmt_wfi ),
.cmt_o_ifu_misalgn (alu_cmt_ifu_misalgn),
.cmt_o_ifu_buserr (alu_cmt_ifu_buserr ),
.cmt_o_ifu_ilegl (alu_cmt_ifu_ilegl ),
.cmt_o_bjp_prdt (alu_cmt_bjp_prdt ),
.cmt_o_bjp_rslv (alu_cmt_bjp_rslv ),
.cmt_o_misalgn (alu_cmt_misalgn),
.cmt_o_ld (alu_cmt_ld),
.cmt_o_stamo (alu_cmt_stamo),
.cmt_o_buserr (alu_cmt_buserr),
.cmt_o_badaddr (alu_cmt_badaddr),
.wbck_o_valid (alu_wbck_o_valid ),
.wbck_o_ready (alu_wbck_o_ready ),
.wbck_o_wdat (alu_wbck_o_wdat ),
.wbck_o_rdidx (alu_wbck_o_rdidx ),
.csr_ena (csr_ena),
.csr_idx (csr_idx),
.csr_rd_en (csr_rd_en),
.csr_wr_en (csr_wr_en),
.read_csr_dat (read_csr_dat),
.wbck_csr_dat (wbck_csr_dat),
.agu_icb_cmd_valid (agu_icb_cmd_valid ),
.agu_icb_cmd_ready (agu_icb_cmd_ready ),
.agu_icb_cmd_addr (agu_icb_cmd_addr ),
.agu_icb_cmd_read (agu_icb_cmd_read ),
.agu_icb_cmd_wdata (agu_icb_cmd_wdata ),
.agu_icb_cmd_wmask (agu_icb_cmd_wmask ),
.agu_icb_cmd_lock (agu_icb_cmd_lock),
.agu_icb_cmd_excl (agu_icb_cmd_excl),
.agu_icb_cmd_size (agu_icb_cmd_size),
.agu_icb_cmd_back2agu(agu_icb_cmd_back2agu ),
.agu_icb_cmd_usign (agu_icb_cmd_usign),
.agu_icb_cmd_itag (agu_icb_cmd_itag),
.agu_icb_rsp_valid (agu_icb_rsp_valid ),
.agu_icb_rsp_ready (agu_icb_rsp_ready ),
.agu_icb_rsp_err (agu_icb_rsp_err ),
.agu_icb_rsp_excl_ok (agu_icb_rsp_excl_ok),
.agu_icb_rsp_rdata (agu_icb_rsp_rdata),
.mdv_nob2b (mdv_nob2b),
.clk (clk ),
.rst_n (rst_n )
);
//////////////////////////////////////////////////////////////
// Instantiate the Long-pipe Write-Back
wire longp_wbck_o_valid;
wire longp_wbck_o_ready;
wire [`E203_FLEN-1:0] longp_wbck_o_wdat;
wire [`E203_RFIDX_WIDTH-1:0] longp_wbck_o_rdidx;
wire longp_wbck_o_rdfpu;
wire [4:0] longp_wbck_o_flags;
wire longp_excp_o_ready;
wire longp_excp_o_valid;
wire longp_excp_o_ld;
wire longp_excp_o_st;
wire longp_excp_o_buserr ;
wire[`E203_ADDR_SIZE-1:0]longp_excp_o_badaddr;
wire longp_excp_o_insterr;
wire[`E203_PC_SIZE-1:0]longp_excp_o_pc;
e203_exu_longpwbck u_e203_exu_longpwbck(
.lsu_wbck_i_valid (lsu_o_valid ),
.lsu_wbck_i_ready (lsu_o_ready ),
.lsu_wbck_i_wdat (lsu_o_wbck_wdat ),
.lsu_wbck_i_itag (lsu_o_wbck_itag ),
.lsu_wbck_i_err (lsu_o_wbck_err ),
.lsu_cmt_i_ld (lsu_o_cmt_ld ),
.lsu_cmt_i_st (lsu_o_cmt_st ),
.lsu_cmt_i_badaddr (lsu_o_cmt_badaddr),
.lsu_cmt_i_buserr (lsu_o_cmt_buserr ),
.longp_wbck_o_valid (longp_wbck_o_valid ),
.longp_wbck_o_ready (longp_wbck_o_ready ),
.longp_wbck_o_wdat (longp_wbck_o_wdat ),
.longp_wbck_o_rdidx (longp_wbck_o_rdidx ),
.longp_wbck_o_rdfpu (longp_wbck_o_rdfpu ),
.longp_wbck_o_flags (longp_wbck_o_flags ),
.longp_excp_o_ready (longp_excp_o_ready ),
.longp_excp_o_valid (longp_excp_o_valid ),
.longp_excp_o_ld (longp_excp_o_ld ),
.longp_excp_o_st (longp_excp_o_st ),
.longp_excp_o_buserr (longp_excp_o_buserr ),
.longp_excp_o_badaddr (longp_excp_o_badaddr),
.longp_excp_o_insterr (longp_excp_o_insterr),
.longp_excp_o_pc (longp_excp_o_pc),
.oitf_ret_rdidx (oitf_ret_rdidx),
.oitf_ret_rdwen (oitf_ret_rdwen),
.oitf_ret_rdfpu (oitf_ret_rdfpu),
.oitf_ret_pc (oitf_ret_pc),
.oitf_empty (oitf_empty ),
.oitf_ret_ptr (oitf_ret_ptr ),
.oitf_ret_ena (oitf_ret_ena ),
.clk (clk ),
.rst_n (rst_n )
);
//////////////////////////////////////////////////////////////
// Instantiate the Final Write-Back
e203_exu_wbck u_e203_exu_wbck(
.alu_wbck_i_valid (alu_wbck_o_valid ),
.alu_wbck_i_ready (alu_wbck_o_ready ),
.alu_wbck_i_wdat (alu_wbck_o_wdat ),
.alu_wbck_i_rdidx (alu_wbck_o_rdidx ),
.longp_wbck_i_valid (longp_wbck_o_valid ),
.longp_wbck_i_ready (longp_wbck_o_ready ),
.longp_wbck_i_wdat (longp_wbck_o_wdat ),
.longp_wbck_i_rdidx (longp_wbck_o_rdidx ),
.longp_wbck_i_rdfpu (longp_wbck_o_rdfpu ),
.longp_wbck_i_flags (longp_wbck_o_flags ),
.rf_wbck_o_ena (rf_wbck_ena ),
.rf_wbck_o_wdat (rf_wbck_wdat ),
.rf_wbck_o_rdidx (rf_wbck_rdidx ),
.clk (clk ),
.rst_n (rst_n )
);
//////////////////////////////////////////////////////////////
// Instantiate the Commit
wire [`E203_ADDR_SIZE-1:0] cmt_badaddr;
wire cmt_badaddr_ena;
wire [`E203_PC_SIZE-1:0] cmt_epc;
wire cmt_epc_ena;
wire [`E203_XLEN-1:0] cmt_cause;
wire cmt_cause_ena;
wire cmt_instret_ena;
wire cmt_status_ena;
wire cmt_mret_ena;
wire [`E203_PC_SIZE-1:0] csr_epc_r;
wire [`E203_PC_SIZE-1:0] csr_dpc_r;
wire [`E203_XLEN-1:0] csr_mtvec_r;
wire u_mode;
wire s_mode;
wire h_mode;
wire m_mode;
wire status_mie_r;
wire mtie_r;
wire msie_r;
wire meie_r;
e203_exu_commit u_e203_exu_commit(
.commit_mret (commit_mret),
.commit_trap (commit_trap),
.core_wfi (core_wfi ),
.nonflush_cmt_ena (nonflush_cmt_ena),
.excp_active (excp_active),
.amo_wait (amo_wait ),
.wfi_halt_exu_req (wfi_halt_exu_req),
.wfi_halt_exu_ack (wfi_halt_exu_ack),
.wfi_halt_ifu_req (wfi_halt_ifu_req),
.wfi_halt_ifu_ack (wfi_halt_ifu_ack),
.dbg_irq_r (dbg_irq_r),
.lcl_irq_r (lcl_irq_r),
.ext_irq_r (ext_irq_r),
.sft_irq_r (sft_irq_r),
.tmr_irq_r (tmr_irq_r),
.evt_r (evt_r ),
.status_mie_r (status_mie_r),
.mtie_r (mtie_r ),
.msie_r (msie_r ),
.meie_r (meie_r ),
.alu_cmt_i_valid (alu_cmt_valid ),
.alu_cmt_i_ready (alu_cmt_ready ),
.alu_cmt_i_pc (alu_cmt_pc ),
.alu_cmt_i_instr (alu_cmt_instr ),
.alu_cmt_i_pc_vld (alu_cmt_pc_vld ),
.alu_cmt_i_imm (alu_cmt_imm ),
.alu_cmt_i_rv32 (alu_cmt_rv32 ),
.alu_cmt_i_bjp (alu_cmt_bjp ),
.alu_cmt_i_mret (alu_cmt_mret ),
.alu_cmt_i_dret (alu_cmt_dret ),
.alu_cmt_i_ecall (alu_cmt_ecall ),
.alu_cmt_i_ebreak (alu_cmt_ebreak ),
.alu_cmt_i_fencei (alu_cmt_fencei ),
.alu_cmt_i_wfi (alu_cmt_wfi ),
.alu_cmt_i_ifu_misalgn (alu_cmt_ifu_misalgn),
.alu_cmt_i_ifu_buserr (alu_cmt_ifu_buserr ),
.alu_cmt_i_ifu_ilegl (alu_cmt_ifu_ilegl ),
.alu_cmt_i_bjp_prdt (alu_cmt_bjp_prdt ),
.alu_cmt_i_bjp_rslv (alu_cmt_bjp_rslv ),
.alu_cmt_i_misalgn (alu_cmt_misalgn),
.alu_cmt_i_ld (alu_cmt_ld),
.alu_cmt_i_stamo (alu_cmt_stamo),
.alu_cmt_i_buserr (alu_cmt_buserr),
.alu_cmt_i_badaddr (alu_cmt_badaddr),
.longp_excp_i_ready (longp_excp_o_ready ),
.longp_excp_i_valid (longp_excp_o_valid ),
.longp_excp_i_ld (longp_excp_o_ld ),
.longp_excp_i_st (longp_excp_o_st ),
.longp_excp_i_buserr (longp_excp_o_buserr ),
.longp_excp_i_badaddr (longp_excp_o_badaddr),
.longp_excp_i_insterr (longp_excp_o_insterr),
.longp_excp_i_pc (longp_excp_o_pc ),
.dbg_mode (dbg_mode),
.dbg_halt_r (dbg_halt_r),
.dbg_step_r (dbg_step_r),
.dbg_ebreakm_r (dbg_ebreakm_r),
.oitf_empty (oitf_empty),
.u_mode (u_mode),
.s_mode (s_mode),
.h_mode (h_mode),
.m_mode (m_mode),
.cmt_badaddr (cmt_badaddr ),
.cmt_badaddr_ena (cmt_badaddr_ena),
.cmt_epc (cmt_epc ),
.cmt_epc_ena (cmt_epc_ena ),
.cmt_cause (cmt_cause ),
.cmt_cause_ena (cmt_cause_ena ),
.cmt_instret_ena (cmt_instret_ena ),
.cmt_status_ena (cmt_status_ena ),
.cmt_dpc (cmt_dpc ),
.cmt_dpc_ena (cmt_dpc_ena ),
.cmt_dcause (cmt_dcause ),
.cmt_dcause_ena (cmt_dcause_ena ),
.cmt_mret_ena (cmt_mret_ena ),
.csr_epc_r (csr_epc_r ),
.csr_dpc_r (csr_dpc_r ),
.csr_mtvec_r (csr_mtvec_r ),
.flush_pulse (flush_pulse ),
.flush_req (flush_req ),
.pipe_flush_ack (pipe_flush_ack ),
.pipe_flush_req (pipe_flush_req ),
.pipe_flush_add_op1 (pipe_flush_add_op1),
.pipe_flush_add_op2 (pipe_flush_add_op2),
`ifdef E203_TIMING_BOOST//}
.pipe_flush_pc (pipe_flush_pc),
`endif//}
.clk (clk ),
.rst_n (rst_n )
);
// The Decode to IFU read-en used for the branch dependency check
// only need to check the integer regfile, so here we need to exclude
// the FPU condition out
assign dec2ifu_rden = disp_oitf_rdwen & (~disp_oitf_rdfpu);
assign dec2ifu_rs1en = disp_oitf_rs1en & (~disp_oitf_rs1fpu);
assign dec2ifu_rdidx = dec_rdidx;
assign rf2ifu_rs1 = rf_rs1;
e203_exu_csr u_e203_exu_csr(
.csr_access_ilgl (csr_access_ilgl),
.eai_xs_off (eai_xs_off),
.nonflush_cmt_ena (nonflush_cmt_ena),
.tm_stop (tm_stop),
.itcm_nohold (itcm_nohold),
.mdv_nob2b (mdv_nob2b),
.core_cgstop (core_cgstop),
.tcm_cgstop (tcm_cgstop ),
.csr_ena (csr_ena),
.csr_idx (csr_idx),
.csr_rd_en (csr_rd_en),
.csr_wr_en (csr_wr_en),
.read_csr_dat (read_csr_dat),
.wbck_csr_dat (wbck_csr_dat),
.cmt_badaddr (cmt_badaddr ),
.cmt_badaddr_ena (cmt_badaddr_ena),
.cmt_epc (cmt_epc ),
.cmt_epc_ena (cmt_epc_ena ),
.cmt_cause (cmt_cause ),
.cmt_cause_ena (cmt_cause_ena ),
.cmt_instret_ena (cmt_instret_ena ),
.cmt_status_ena (cmt_status_ena ),
.cmt_mret_ena (cmt_mret_ena ),
.csr_epc_r (csr_epc_r ),
.csr_dpc_r (csr_dpc_r ),
.csr_mtvec_r (csr_mtvec_r ),
.wr_dcsr_ena (wr_dcsr_ena ),
.wr_dpc_ena (wr_dpc_ena ),
.wr_dscratch_ena (wr_dscratch_ena),
.wr_csr_nxt (wr_csr_nxt ),
.dcsr_r (dcsr_r ),
.dpc_r (dpc_r ),
.dscratch_r (dscratch_r ),
.dbg_mode (dbg_mode ),
.dbg_stopcycle (dbg_stopcycle),
.u_mode (u_mode),
.s_mode (s_mode),
.h_mode (h_mode),
.m_mode (m_mode),
.core_mhartid (core_mhartid),
.status_mie_r (status_mie_r),
.mtie_r (mtie_r ),
.msie_r (msie_r ),
.meie_r (meie_r ),
.ext_irq_r (ext_irq_r),
.sft_irq_r (sft_irq_r),
.tmr_irq_r (tmr_irq_r),
.clk_aon (clk_aon ),
.clk (clk ),
.rst_n (rst_n )
);
assign exu_active = (~oitf_empty) | i_valid | excp_active;
endmodule
|
module sirv_qspi_physical(
input clock,
input reset,
output io_port_sck,
input io_port_dq_0_i,
output io_port_dq_0_o,
output io_port_dq_0_oe,
input io_port_dq_1_i,
output io_port_dq_1_o,
output io_port_dq_1_oe,
input io_port_dq_2_i,
output io_port_dq_2_o,
output io_port_dq_2_oe,
input io_port_dq_3_i,
output io_port_dq_3_o,
output io_port_dq_3_oe,
output io_port_cs_0,
input [11:0] io_ctrl_sck_div,
input io_ctrl_sck_pol,
input io_ctrl_sck_pha,
input [1:0] io_ctrl_fmt_proto,
input io_ctrl_fmt_endian,
input io_ctrl_fmt_iodir,
output io_op_ready,
input io_op_valid,
input io_op_bits_fn,
input io_op_bits_stb,
input [7:0] io_op_bits_cnt,
input [7:0] io_op_bits_data,
output io_rx_valid,
output [7:0] io_rx_bits
);
reg [11:0] ctrl_sck_div;
reg [31:0] GEN_2;
reg ctrl_sck_pol;
reg [31:0] GEN_31;
reg ctrl_sck_pha;
reg [31:0] GEN_52;
reg [1:0] ctrl_fmt_proto;
reg [31:0] GEN_67;
reg ctrl_fmt_endian;
reg [31:0] GEN_68;
reg ctrl_fmt_iodir;
reg [31:0] GEN_69;
wire proto_0;
wire proto_1;
wire proto_2;
wire accept;
wire sample;
wire setup;
wire last;
reg setup_d;
reg [31:0] GEN_70;
reg T_119;
reg [31:0] GEN_71;
reg T_120;
reg [31:0] GEN_72;
reg sample_d;
reg [31:0] GEN_73;
reg T_122;
reg [31:0] GEN_74;
reg T_123;
reg [31:0] GEN_75;
reg last_d;
reg [31:0] GEN_76;
reg [7:0] scnt;
reg [31:0] GEN_77;
reg [11:0] tcnt;
reg [31:0] GEN_78;
wire stop;
wire beat;
wire [11:0] T_127;
wire [12:0] T_129;
wire [11:0] decr;
wire sched;
wire [11:0] T_130;
reg sck;
reg [31:0] GEN_79;
reg cref;
reg [31:0] GEN_80;
wire cinv;
wire [1:0] T_133;
wire [1:0] T_134;
wire [3:0] rxd;
wire samples_0;
wire [1:0] samples_1;
reg [7:0] buffer;
reg [31:0] GEN_81;
wire T_135;
wire T_136;
wire T_137;
wire T_138;
wire T_139;
wire T_140;
wire T_141;
wire T_142;
wire T_143;
wire [1:0] T_144;
wire [1:0] T_145;
wire [3:0] T_146;
wire [1:0] T_147;
wire [1:0] T_148;
wire [3:0] T_149;
wire [7:0] T_150;
wire [7:0] buffer_in;
wire T_151;
wire shift;
wire [6:0] T_152;
wire [6:0] T_153;
wire [6:0] T_154;
wire T_155;
wire T_157;
wire [7:0] T_158;
wire [5:0] T_159;
wire [5:0] T_160;
wire [5:0] T_161;
wire [1:0] T_162;
wire [1:0] T_163;
wire [7:0] T_164;
wire [3:0] T_165;
wire [3:0] T_166;
wire [3:0] T_167;
wire [3:0] T_169;
wire [7:0] T_170;
wire [7:0] T_172;
wire [7:0] T_174;
wire [7:0] T_176;
wire [7:0] T_178;
wire [7:0] T_179;
wire [7:0] T_180;
reg [3:0] txd;
reg [31:0] GEN_82;
wire [3:0] T_182;
wire [3:0] txd_in;
wire [1:0] T_184;
wire txd_sel_0;
wire txd_sel_1;
wire txd_sel_2;
wire txd_shf_0;
wire [1:0] txd_shf_1;
wire T_186;
wire [1:0] T_188;
wire [3:0] T_190;
wire [1:0] GEN_65;
wire [1:0] T_192;
wire [3:0] GEN_66;
wire [3:0] T_193;
wire [3:0] T_194;
wire [3:0] GEN_0;
wire T_195;
wire T_196;
wire txen_1;
wire txen_0;
wire T_202_0;
wire T_206;
wire T_207;
wire T_208;
wire T_209;
reg done;
reg [31:0] GEN_83;
wire T_212;
wire T_213;
wire T_215;
wire T_216;
wire T_217;
wire T_218;
wire T_219;
wire T_220;
wire T_221;
wire [1:0] T_222;
wire [1:0] T_223;
wire [3:0] T_224;
wire [1:0] T_225;
wire [1:0] T_226;
wire [3:0] T_227;
wire [7:0] T_228;
wire [7:0] T_229;
reg xfr;
reg [31:0] GEN_84;
wire GEN_1;
wire T_234;
wire T_236;
wire T_237;
wire GEN_3;
wire GEN_4;
wire GEN_5;
wire [11:0] GEN_6;
wire GEN_7;
wire GEN_8;
wire GEN_9;
wire GEN_10;
wire [11:0] GEN_11;
wire GEN_12;
wire GEN_13;
wire GEN_14;
wire GEN_15;
wire [11:0] GEN_16;
wire T_243;
wire T_244;
wire T_245;
wire T_248;
wire GEN_17;
wire GEN_18;
wire GEN_19;
wire GEN_20;
wire GEN_21;
wire GEN_22;
wire GEN_23;
wire T_251;
wire [1:0] GEN_24;
wire GEN_25;
wire GEN_26;
wire T_256;
wire T_259;
wire [7:0] GEN_27;
wire GEN_28;
wire GEN_29;
wire GEN_30;
wire GEN_32;
wire [11:0] GEN_33;
wire GEN_34;
wire GEN_35;
wire GEN_36;
wire [11:0] GEN_37;
wire GEN_38;
wire GEN_39;
wire [11:0] GEN_40;
wire [1:0] GEN_41;
wire GEN_42;
wire GEN_43;
wire GEN_44;
wire [7:0] GEN_45;
wire GEN_46;
wire GEN_47;
wire GEN_48;
wire [11:0] GEN_49;
wire GEN_50;
wire GEN_51;
wire [11:0] GEN_53;
wire [1:0] GEN_54;
wire GEN_55;
wire GEN_56;
wire GEN_57;
wire [7:0] GEN_58;
wire GEN_59;
wire GEN_60;
wire GEN_61;
wire [11:0] GEN_62;
wire GEN_63;
wire GEN_64;
assign io_port_sck = sck;
assign io_port_dq_0_o = T_206;
assign io_port_dq_0_oe = txen_0;
assign io_port_dq_1_o = T_207;
assign io_port_dq_1_oe = txen_1;
assign io_port_dq_2_o = T_208;
assign io_port_dq_2_oe = T_196;
assign io_port_dq_3_o = T_209;
assign io_port_dq_3_oe = 1'h0;
assign io_port_cs_0 = T_202_0;
assign io_op_ready = T_251;
assign io_rx_valid = done;
assign io_rx_bits = T_229;
assign proto_0 = 2'h0 == ctrl_fmt_proto;
assign proto_1 = 2'h1 == ctrl_fmt_proto;
assign proto_2 = 2'h2 == ctrl_fmt_proto;
assign accept = GEN_21;
assign sample = GEN_14;
assign setup = GEN_60;
assign last = GEN_20;
assign stop = scnt == 8'h0;
assign beat = tcnt == 12'h0;
assign T_127 = beat ? {{4'd0}, scnt} : tcnt;
assign T_129 = T_127 - 12'h1;
assign decr = T_129[11:0];
assign sched = GEN_1;
assign T_130 = sched ? ctrl_sck_div : decr;
assign cinv = ctrl_sck_pha ^ ctrl_sck_pol;
assign T_133 = {io_port_dq_1_i,io_port_dq_0_i};
assign T_134 = {io_port_dq_3_i,io_port_dq_2_i};
assign rxd = {T_134,T_133};
assign samples_0 = rxd[1];
assign samples_1 = rxd[1:0];
assign T_135 = io_ctrl_fmt_endian == 1'h0;
assign T_136 = io_op_bits_data[0];
assign T_137 = io_op_bits_data[1];
assign T_138 = io_op_bits_data[2];
assign T_139 = io_op_bits_data[3];
assign T_140 = io_op_bits_data[4];
assign T_141 = io_op_bits_data[5];
assign T_142 = io_op_bits_data[6];
assign T_143 = io_op_bits_data[7];
assign T_144 = {T_142,T_143};
assign T_145 = {T_140,T_141};
assign T_146 = {T_145,T_144};
assign T_147 = {T_138,T_139};
assign T_148 = {T_136,T_137};
assign T_149 = {T_148,T_147};
assign T_150 = {T_149,T_146};
assign buffer_in = T_135 ? io_op_bits_data : T_150;
assign T_151 = sample_d & stop;
assign shift = setup_d | T_151;
assign T_152 = buffer[6:0];
assign T_153 = buffer[7:1];
assign T_154 = shift ? T_152 : T_153;
assign T_155 = buffer[0];
assign T_157 = sample_d ? samples_0 : T_155;
assign T_158 = {T_154,T_157};
assign T_159 = buffer[5:0];
assign T_160 = buffer[7:2];
assign T_161 = shift ? T_159 : T_160;
assign T_162 = buffer[1:0];
assign T_163 = sample_d ? samples_1 : T_162;
assign T_164 = {T_161,T_163};
assign T_165 = buffer[3:0];
assign T_166 = buffer[7:4];
assign T_167 = shift ? T_165 : T_166;
assign T_169 = sample_d ? rxd : T_165;
assign T_170 = {T_167,T_169};
assign T_172 = proto_0 ? T_158 : 8'h0;
assign T_174 = proto_1 ? T_164 : 8'h0;
assign T_176 = proto_2 ? T_170 : 8'h0;
assign T_178 = T_172 | T_174;
assign T_179 = T_178 | T_176;
assign T_180 = T_179;
assign T_182 = buffer_in[7:4];
assign txd_in = accept ? T_182 : T_166;
assign T_184 = accept ? io_ctrl_fmt_proto : ctrl_fmt_proto;
assign txd_sel_0 = 2'h0 == T_184;
assign txd_sel_1 = 2'h1 == T_184;
assign txd_sel_2 = 2'h2 == T_184;
assign txd_shf_0 = txd_in[3];
assign txd_shf_1 = txd_in[3:2];
assign T_186 = txd_sel_0 ? txd_shf_0 : 1'h0;
assign T_188 = txd_sel_1 ? txd_shf_1 : 2'h0;
assign T_190 = txd_sel_2 ? txd_in : 4'h0;
assign GEN_65 = {{1'd0}, T_186};
assign T_192 = GEN_65 | T_188;
assign GEN_66 = {{2'd0}, T_192};
assign T_193 = GEN_66 | T_190;
assign T_194 = T_193;
assign GEN_0 = setup ? T_194 : txd;
assign T_195 = proto_1 & ctrl_fmt_iodir;
assign T_196 = proto_2 & ctrl_fmt_iodir;
assign txen_1 = T_195 | T_196;
assign txen_0 = proto_0 | txen_1;
assign T_202_0 = 1'h1;
assign T_206 = txd[0];
assign T_207 = txd[1];
assign T_208 = txd[2];
assign T_209 = txd[3];
assign T_212 = done | last_d;
assign T_213 = ctrl_fmt_endian == 1'h0;
assign T_215 = buffer[1];
assign T_216 = buffer[2];
assign T_217 = buffer[3];
assign T_218 = buffer[4];
assign T_219 = buffer[5];
assign T_220 = buffer[6];
assign T_221 = buffer[7];
assign T_222 = {T_220,T_221};
assign T_223 = {T_218,T_219};
assign T_224 = {T_223,T_222};
assign T_225 = {T_216,T_217};
assign T_226 = {T_155,T_215};
assign T_227 = {T_226,T_225};
assign T_228 = {T_227,T_224};
assign T_229 = T_213 ? buffer : T_228;
assign GEN_1 = stop ? 1'h1 : beat;
assign T_234 = stop == 1'h0;
assign T_236 = cref == 1'h0;
assign T_237 = cref ^ cinv;
assign GEN_3 = xfr ? T_237 : sck;
assign GEN_4 = xfr ? cref : 1'h0;
assign GEN_5 = xfr ? T_236 : 1'h0;
assign GEN_6 = T_236 ? decr : {{4'd0}, scnt};
assign GEN_7 = beat ? T_236 : cref;
assign GEN_8 = beat ? GEN_3 : sck;
assign GEN_9 = beat ? GEN_4 : 1'h0;
assign GEN_10 = beat ? GEN_5 : 1'h0;
assign GEN_11 = beat ? GEN_6 : {{4'd0}, scnt};
assign GEN_12 = T_234 ? GEN_7 : cref;
assign GEN_13 = T_234 ? GEN_8 : sck;
assign GEN_14 = T_234 ? GEN_9 : 1'h0;
assign GEN_15 = T_234 ? GEN_10 : 1'h0;
assign GEN_16 = T_234 ? GEN_11 : {{4'd0}, scnt};
assign T_243 = scnt == 8'h1;
assign T_244 = beat & cref;
assign T_245 = T_244 & xfr;
assign T_248 = beat & T_236;
assign GEN_17 = T_248 ? 1'h1 : stop;
assign GEN_18 = T_248 ? 1'h0 : GEN_15;
assign GEN_19 = T_248 ? ctrl_sck_pol : GEN_13;
assign GEN_20 = T_243 ? T_245 : 1'h0;
assign GEN_21 = T_243 ? GEN_17 : stop;
assign GEN_22 = T_243 ? GEN_18 : GEN_15;
assign GEN_23 = T_243 ? GEN_19 : GEN_13;
assign T_251 = accept & done;
assign GEN_24 = io_op_bits_stb ? io_ctrl_fmt_proto : ctrl_fmt_proto;
assign GEN_25 = io_op_bits_stb ? io_ctrl_fmt_endian : ctrl_fmt_endian;
assign GEN_26 = io_op_bits_stb ? io_ctrl_fmt_iodir : ctrl_fmt_iodir;
assign T_256 = 1'h0 == io_op_bits_fn;
assign T_259 = io_op_bits_cnt == 8'h0;
assign GEN_27 = T_256 ? buffer_in : T_180;
assign GEN_28 = T_256 ? cinv : GEN_23;
assign GEN_29 = T_256 ? 1'h1 : GEN_22;
assign GEN_30 = T_256 ? T_259 : T_212;
assign GEN_32 = io_op_bits_stb ? io_ctrl_sck_pol : GEN_28;
assign GEN_33 = io_op_bits_stb ? io_ctrl_sck_div : ctrl_sck_div;
assign GEN_34 = io_op_bits_stb ? io_ctrl_sck_pol : ctrl_sck_pol;
assign GEN_35 = io_op_bits_stb ? io_ctrl_sck_pha : ctrl_sck_pha;
assign GEN_36 = io_op_bits_fn ? GEN_32 : GEN_28;
assign GEN_37 = io_op_bits_fn ? GEN_33 : ctrl_sck_div;
assign GEN_38 = io_op_bits_fn ? GEN_34 : ctrl_sck_pol;
assign GEN_39 = io_op_bits_fn ? GEN_35 : ctrl_sck_pha;
assign GEN_40 = io_op_valid ? {{4'd0}, io_op_bits_cnt} : GEN_16;
assign GEN_41 = io_op_valid ? GEN_24 : ctrl_fmt_proto;
assign GEN_42 = io_op_valid ? GEN_25 : ctrl_fmt_endian;
assign GEN_43 = io_op_valid ? GEN_26 : ctrl_fmt_iodir;
assign GEN_44 = io_op_valid ? T_256 : xfr;
assign GEN_45 = io_op_valid ? GEN_27 : T_180;
assign GEN_46 = io_op_valid ? GEN_36 : GEN_23;
assign GEN_47 = io_op_valid ? GEN_29 : GEN_22;
assign GEN_48 = io_op_valid ? GEN_30 : T_212;
assign GEN_49 = io_op_valid ? GEN_37 : ctrl_sck_div;
assign GEN_50 = io_op_valid ? GEN_38 : ctrl_sck_pol;
assign GEN_51 = io_op_valid ? GEN_39 : ctrl_sck_pha;
assign GEN_53 = T_251 ? GEN_40 : GEN_16;
assign GEN_54 = T_251 ? GEN_41 : ctrl_fmt_proto;
assign GEN_55 = T_251 ? GEN_42 : ctrl_fmt_endian;
assign GEN_56 = T_251 ? GEN_43 : ctrl_fmt_iodir;
assign GEN_57 = T_251 ? GEN_44 : xfr;
assign GEN_58 = T_251 ? GEN_45 : T_180;
assign GEN_59 = T_251 ? GEN_46 : GEN_23;
assign GEN_60 = T_251 ? GEN_47 : GEN_22;
assign GEN_61 = T_251 ? GEN_48 : T_212;
assign GEN_62 = T_251 ? GEN_49 : ctrl_sck_div;
assign GEN_63 = T_251 ? GEN_50 : ctrl_sck_pol;
assign GEN_64 = T_251 ? GEN_51 : ctrl_sck_pha;
always @(posedge clock or posedge reset)
if (reset) begin
ctrl_sck_div <= 12'b0;
ctrl_sck_pol <= 1'b0;
ctrl_sck_pha <= 1'b0;
ctrl_fmt_proto <= 2'b0;
ctrl_fmt_endian <= 1'b0;
ctrl_fmt_iodir <= 1'b0;
setup_d <= 1'b0;
tcnt <= 12'b0;
sck <= 1'b0;
buffer <= 8'b0;
xfr <= 1'b0;
end
else begin
if (T_251) begin
if (io_op_valid) begin
if (io_op_bits_fn) begin
if (io_op_bits_stb) begin
ctrl_sck_div <= io_ctrl_sck_div;
end
end
end
end
if (T_251) begin
if (io_op_valid) begin
if (io_op_bits_fn) begin
if (io_op_bits_stb) begin
ctrl_sck_pol <= io_ctrl_sck_pol;
end
end
end
end
if (T_251) begin
if (io_op_valid) begin
if (io_op_bits_fn) begin
if (io_op_bits_stb) begin
ctrl_sck_pha <= io_ctrl_sck_pha;
end
end
end
end
if (T_251) begin
if (io_op_valid) begin
if (io_op_bits_stb) begin
ctrl_fmt_proto <= io_ctrl_fmt_proto;
end
end
end
if (T_251) begin
if (io_op_valid) begin
if (io_op_bits_stb) begin
ctrl_fmt_endian <= io_ctrl_fmt_endian;
end
end
end
if (T_251) begin
if (io_op_valid) begin
if (io_op_bits_stb) begin
ctrl_fmt_iodir <= io_ctrl_fmt_iodir;
end
end
end
setup_d <= setup;
if (sched) begin
tcnt <= ctrl_sck_div;
end else begin
tcnt <= decr;
end
if (T_251) begin
if (io_op_valid) begin
if (io_op_bits_fn) begin
if (io_op_bits_stb) begin
sck <= io_ctrl_sck_pol;
end else begin
if (T_256) begin
sck <= cinv;
end else begin
if (T_243) begin
if (T_248) begin
sck <= ctrl_sck_pol;
end else begin
if (T_234) begin
if (beat) begin
if (xfr) begin
sck <= T_237;
end
end
end
end
end else begin
if (T_234) begin
if (beat) begin
if (xfr) begin
sck <= T_237;
end
end
end
end
end
end
end else begin
if (T_256) begin
sck <= cinv;
end else begin
if (T_243) begin
if (T_248) begin
sck <= ctrl_sck_pol;
end else begin
if (T_234) begin
if (beat) begin
if (xfr) begin
sck <= T_237;
end
end
end
end
end else begin
if (T_234) begin
if (beat) begin
if (xfr) begin
sck <= T_237;
end
end
end
end
end
end
end else begin
if (T_243) begin
if (T_248) begin
sck <= ctrl_sck_pol;
end else begin
sck <= GEN_13;
end
end else begin
sck <= GEN_13;
end
end
end else begin
if (T_243) begin
if (T_248) begin
sck <= ctrl_sck_pol;
end else begin
sck <= GEN_13;
end
end else begin
sck <= GEN_13;
end
end
if (T_251) begin
if (io_op_valid) begin
if (T_256) begin
if (T_135) begin
buffer <= io_op_bits_data;
end else begin
buffer <= T_150;
end
end else begin
buffer <= T_180;
end
end else begin
buffer <= T_180;
end
end else begin
buffer <= T_180;
end
if (T_251) begin
if (io_op_valid) begin
xfr <= T_256;
end
end
end
always @(posedge clock or posedge reset)
if (reset) begin
cref <= 1'h1;
end else begin
if (T_234) begin
if (beat) begin
cref <= T_236;
end
end
end
always @(posedge clock or posedge reset)
if (reset) begin
txd <= 4'h0;
end else begin
if (setup) begin
txd <= T_194;
end
end
always @(posedge clock or posedge reset)
if (reset) begin
done <= 1'h1;
end else begin
if (T_251) begin
if (io_op_valid) begin
if (T_256) begin
done <= T_259;
end else begin
done <= T_212;
end
end else begin
done <= T_212;
end
end else begin
done <= T_212;
end
end
always @(posedge clock or posedge reset)
if (reset) begin
T_119 <= 1'h0;
end else begin
T_119 <= sample;
end
always @(posedge clock or posedge reset)
if (reset) begin
T_120 <= 1'h0;
end else begin
T_120 <= T_119;
end
always @(posedge clock or posedge reset)
if (reset) begin
sample_d <= 1'h0;
end else begin
sample_d <= T_120;
end
always @(posedge clock or posedge reset)
if (reset) begin
T_122 <= 1'h0;
end else begin
T_122 <= last;
end
always @(posedge clock or posedge reset)
if (reset) begin
T_123 <= 1'h0;
end else begin
T_123 <= T_122;
end
always @(posedge clock or posedge reset)
if (reset) begin
last_d <= 1'h0;
end else begin
last_d <= T_123;
end
always @(posedge clock or posedge reset)
if (reset) begin
scnt <= 8'h0;
end else begin
scnt <= GEN_53[7:0];
end
endmodule
|
module sirv_spigpioport_2(
input clock,
input reset,
input io_spi_sck,
output io_spi_dq_0_i,
input io_spi_dq_0_o,
input io_spi_dq_0_oe,
output io_spi_dq_1_i,
input io_spi_dq_1_o,
input io_spi_dq_1_oe,
output io_spi_dq_2_i,
input io_spi_dq_2_o,
input io_spi_dq_2_oe,
output io_spi_dq_3_i,
input io_spi_dq_3_o,
input io_spi_dq_3_oe,
input io_spi_cs_0,
input io_pins_sck_i_ival,
output io_pins_sck_o_oval,
output io_pins_sck_o_oe,
output io_pins_sck_o_ie,
output io_pins_sck_o_pue,
output io_pins_sck_o_ds,
input io_pins_dq_0_i_ival,
output io_pins_dq_0_o_oval,
output io_pins_dq_0_o_oe,
output io_pins_dq_0_o_ie,
output io_pins_dq_0_o_pue,
output io_pins_dq_0_o_ds,
input io_pins_dq_1_i_ival,
output io_pins_dq_1_o_oval,
output io_pins_dq_1_o_oe,
output io_pins_dq_1_o_ie,
output io_pins_dq_1_o_pue,
output io_pins_dq_1_o_ds,
input io_pins_dq_2_i_ival,
output io_pins_dq_2_o_oval,
output io_pins_dq_2_o_oe,
output io_pins_dq_2_o_ie,
output io_pins_dq_2_o_pue,
output io_pins_dq_2_o_ds,
input io_pins_dq_3_i_ival,
output io_pins_dq_3_o_oval,
output io_pins_dq_3_o_oe,
output io_pins_dq_3_o_ie,
output io_pins_dq_3_o_pue,
output io_pins_dq_3_o_ds,
input io_pins_cs_0_i_ival,
output io_pins_cs_0_o_oval,
output io_pins_cs_0_o_oe,
output io_pins_cs_0_o_ie,
output io_pins_cs_0_o_pue,
output io_pins_cs_0_o_ds
);
wire T_267;
reg T_271;
reg [31:0] GEN_0;
reg T_272;
reg [31:0] GEN_1;
reg T_273;
reg [31:0] GEN_2;
wire T_274;
reg T_278;
reg [31:0] GEN_3;
reg T_279;
reg [31:0] GEN_4;
reg T_280;
reg [31:0] GEN_5;
wire T_281;
reg T_285;
reg [31:0] GEN_6;
reg T_286;
reg [31:0] GEN_7;
reg T_287;
reg [31:0] GEN_8;
wire T_288;
reg T_292;
reg [31:0] GEN_9;
reg T_293;
reg [31:0] GEN_10;
reg T_294;
reg [31:0] GEN_11;
assign io_spi_dq_0_i = T_273;
assign io_spi_dq_1_i = T_280;
assign io_spi_dq_2_i = T_287;
assign io_spi_dq_3_i = T_294;
assign io_pins_sck_o_oval = io_spi_sck;
assign io_pins_sck_o_oe = 1'h1;
assign io_pins_sck_o_ie = 1'h0;
assign io_pins_sck_o_pue = 1'h0;
assign io_pins_sck_o_ds = 1'h1;
assign io_pins_dq_0_o_oval = io_spi_dq_0_o;
assign io_pins_dq_0_o_oe = io_spi_dq_0_oe;
assign io_pins_dq_0_o_ie = T_267;
assign io_pins_dq_0_o_pue = 1'h1;
assign io_pins_dq_0_o_ds = 1'h1;
assign io_pins_dq_1_o_oval = io_spi_dq_1_o;
assign io_pins_dq_1_o_oe = io_spi_dq_1_oe;
assign io_pins_dq_1_o_ie = T_274;
assign io_pins_dq_1_o_pue = 1'h1;
assign io_pins_dq_1_o_ds = 1'h1;
assign io_pins_dq_2_o_oval = io_spi_dq_2_o;
assign io_pins_dq_2_o_oe = io_spi_dq_2_oe;
assign io_pins_dq_2_o_ie = T_281;
assign io_pins_dq_2_o_pue = 1'h1;
assign io_pins_dq_2_o_ds = 1'h1;
assign io_pins_dq_3_o_oval = io_spi_dq_3_o;
assign io_pins_dq_3_o_oe = io_spi_dq_3_oe;
assign io_pins_dq_3_o_ie = T_288;
assign io_pins_dq_3_o_pue = 1'h1;
assign io_pins_dq_3_o_ds = 1'h1;
assign io_pins_cs_0_o_oval = io_spi_cs_0;
assign io_pins_cs_0_o_oe = 1'h1;
assign io_pins_cs_0_o_ie = 1'h0;
assign io_pins_cs_0_o_pue = 1'h0;
assign io_pins_cs_0_o_ds = 1'h1;
assign T_267 = ~ io_spi_dq_0_oe;
assign T_274 = ~ io_spi_dq_1_oe;
assign T_281 = ~ io_spi_dq_2_oe;
assign T_288 = ~ io_spi_dq_3_oe;
always @(posedge clock or posedge reset) begin
if(reset) begin
T_271 <= 1'b0;
T_272 <= 1'b0;
T_273 <= 1'b0;
T_278 <= 1'b0;
T_279 <= 1'b0;
T_280 <= 1'b0;
T_285 <= 1'b0;
T_286 <= 1'b0;
T_287 <= 1'b0;
T_292 <= 1'b0;
T_293 <= 1'b0;
T_294 <= 1'b0;
end
else begin
T_271 <= io_pins_dq_0_i_ival;
T_272 <= T_271;
T_273 <= T_272;
T_278 <= io_pins_dq_1_i_ival;
T_279 <= T_278;
T_280 <= T_279;
T_285 <= io_pins_dq_2_i_ival;
T_286 <= T_285;
T_287 <= T_286;
T_292 <= io_pins_dq_3_i_ival;
T_293 <= T_292;
T_294 <= T_293;
end
end
endmodule
|
module e203_ifu_minidec(
//////////////////////////////////////////////////////////////
// The IR stage to Decoder
input [`E203_INSTR_SIZE-1:0] instr,
//////////////////////////////////////////////////////////////
// The Decoded Info-Bus
output dec_rs1en,
output dec_rs2en,
output [`E203_RFIDX_WIDTH-1:0] dec_rs1idx,
output [`E203_RFIDX_WIDTH-1:0] dec_rs2idx,
output dec_mulhsu,
output dec_mul ,
output dec_div ,
output dec_rem ,
output dec_divu ,
output dec_remu ,
output dec_rv32,
output dec_bjp,
output dec_jal,
output dec_jalr,
output dec_bxx,
output [`E203_RFIDX_WIDTH-1:0] dec_jalr_rs1idx,
output [`E203_XLEN-1:0] dec_bjp_imm
);
e203_exu_decode u_e203_exu_decode(
.i_instr(instr),
.i_pc(`E203_PC_SIZE'b0),
.i_prdt_taken(1'b0),
.i_muldiv_b2b(1'b0),
.i_misalgn (1'b0),
.i_buserr (1'b0),
.dbg_mode (1'b0),
.dec_misalgn(),
.dec_buserr(),
.dec_ilegl(),
.dec_rs1x0(),
.dec_rs2x0(),
.dec_rs1en(dec_rs1en),
.dec_rs2en(dec_rs2en),
.dec_rdwen(),
.dec_rs1idx(dec_rs1idx),
.dec_rs2idx(dec_rs2idx),
.dec_rdidx(),
.dec_info(),
.dec_imm(),
.dec_pc(),
.dec_mulhsu(dec_mulhsu),
.dec_mul (dec_mul ),
.dec_div (dec_div ),
.dec_rem (dec_rem ),
.dec_divu (dec_divu ),
.dec_remu (dec_remu ),
.dec_rv32(dec_rv32),
.dec_bjp (dec_bjp ),
.dec_jal (dec_jal ),
.dec_jalr(dec_jalr),
.dec_bxx (dec_bxx ),
.dec_jalr_rs1idx(dec_jalr_rs1idx),
.dec_bjp_imm (dec_bjp_imm )
);
endmodule
|
module sirv_AsyncResetRegVec(
input clock,
input reset,
input io_d,
output io_q,
input io_en
);
wire reg_0_rst;
wire reg_0_clk;
wire reg_0_en;
wire reg_0_q;
wire reg_0_d;
sirv_AsyncResetReg reg_0 (
.rst(reg_0_rst),
.clk(reg_0_clk),
.en(reg_0_en),
.q(reg_0_q),
.d(reg_0_d)
);
assign io_q = reg_0_q;
assign reg_0_rst = reset;
assign reg_0_clk = clock;
assign reg_0_en = io_en;
assign reg_0_d = io_d;
endmodule
|
module e203_biu(
output biu_active,
//////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////
// The ICB Interface from LSU
input lsu2biu_icb_cmd_valid,
output lsu2biu_icb_cmd_ready,
input [`E203_ADDR_SIZE-1:0] lsu2biu_icb_cmd_addr,
input lsu2biu_icb_cmd_read,
input [`E203_XLEN-1:0] lsu2biu_icb_cmd_wdata,
input [`E203_XLEN/8-1:0] lsu2biu_icb_cmd_wmask,
input [1:0] lsu2biu_icb_cmd_burst,
input [1:0] lsu2biu_icb_cmd_beat,
input lsu2biu_icb_cmd_lock,
input lsu2biu_icb_cmd_excl,
input [1:0] lsu2biu_icb_cmd_size,
output lsu2biu_icb_rsp_valid,
input lsu2biu_icb_rsp_ready,
output lsu2biu_icb_rsp_err ,
output lsu2biu_icb_rsp_excl_ok,
output [`E203_XLEN-1:0] lsu2biu_icb_rsp_rdata,
`ifdef E203_HAS_MEM_ITF //{
//////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////
// the icb interface from ifetch
//
// * bus cmd channel
input ifu2biu_icb_cmd_valid,
output ifu2biu_icb_cmd_ready,
input [`E203_ADDR_SIZE-1:0] ifu2biu_icb_cmd_addr,
input ifu2biu_icb_cmd_read,
input [`E203_XLEN-1:0] ifu2biu_icb_cmd_wdata,
input [`E203_XLEN/8-1:0] ifu2biu_icb_cmd_wmask,
input [1:0] ifu2biu_icb_cmd_burst,
input [1:0] ifu2biu_icb_cmd_beat,
input ifu2biu_icb_cmd_lock,
input ifu2biu_icb_cmd_excl,
input [1:0] ifu2biu_icb_cmd_size,
//
// * bus rsp channel
output ifu2biu_icb_rsp_valid,
input ifu2biu_icb_rsp_ready,
output ifu2biu_icb_rsp_err ,
output ifu2biu_icb_rsp_excl_ok,
output [`E203_XLEN-1:0] ifu2biu_icb_rsp_rdata,
//output ifu2biu_replay,
`endif//}
//////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////
// The ICB Interface to Private Peripheral Interface
//
input [`E203_ADDR_SIZE-1:0] ppi_region_indic,
input ppi_icb_enable,
// * Bus cmd channel
output ppi_icb_cmd_valid,
input ppi_icb_cmd_ready,
output [`E203_ADDR_SIZE-1:0] ppi_icb_cmd_addr,
output ppi_icb_cmd_read,
output [`E203_XLEN-1:0] ppi_icb_cmd_wdata,
output [`E203_XLEN/8-1:0] ppi_icb_cmd_wmask,
output [1:0] ppi_icb_cmd_burst,
output [1:0] ppi_icb_cmd_beat,
output ppi_icb_cmd_lock,
output ppi_icb_cmd_excl,
output [1:0] ppi_icb_cmd_size,
//
// * Bus RSP channel
input ppi_icb_rsp_valid,
output ppi_icb_rsp_ready,
input ppi_icb_rsp_err ,
input ppi_icb_rsp_excl_ok,
input [`E203_XLEN-1:0] ppi_icb_rsp_rdata,
//
input [`E203_ADDR_SIZE-1:0] clint_region_indic,
input clint_icb_enable,
// * Bus cmd channel
output clint_icb_cmd_valid,
input clint_icb_cmd_ready,
output [`E203_ADDR_SIZE-1:0] clint_icb_cmd_addr,
output clint_icb_cmd_read,
output [`E203_XLEN-1:0] clint_icb_cmd_wdata,
output [`E203_XLEN/8-1:0] clint_icb_cmd_wmask,
output [1:0] clint_icb_cmd_burst,
output [1:0] clint_icb_cmd_beat,
output clint_icb_cmd_lock,
output clint_icb_cmd_excl,
output [1:0] clint_icb_cmd_size,
//
// * Bus RSP channel
input clint_icb_rsp_valid,
output clint_icb_rsp_ready,
input clint_icb_rsp_err ,
input clint_icb_rsp_excl_ok,
input [`E203_XLEN-1:0] clint_icb_rsp_rdata,
//
input [`E203_ADDR_SIZE-1:0] plic_region_indic,
input plic_icb_enable,
// * Bus cmd channel
output plic_icb_cmd_valid,
input plic_icb_cmd_ready,
output [`E203_ADDR_SIZE-1:0] plic_icb_cmd_addr,
output plic_icb_cmd_read,
output [`E203_XLEN-1:0] plic_icb_cmd_wdata,
output [`E203_XLEN/8-1:0] plic_icb_cmd_wmask,
output [1:0] plic_icb_cmd_burst,
output [1:0] plic_icb_cmd_beat,
output plic_icb_cmd_lock,
output plic_icb_cmd_excl,
output [1:0] plic_icb_cmd_size,
//
// * Bus RSP channel
input plic_icb_rsp_valid,
output plic_icb_rsp_ready,
input plic_icb_rsp_err ,
input plic_icb_rsp_excl_ok,
input [`E203_XLEN-1:0] plic_icb_rsp_rdata,
`ifdef E203_HAS_FIO //{
//////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////
// The ICB Interface to Fast I/O
input [`E203_ADDR_SIZE-1:0] fio_region_indic,
input fio_icb_enable,
//
// * Bus cmd channel
output fio_icb_cmd_valid,
input fio_icb_cmd_ready,
output [`E203_ADDR_SIZE-1:0] fio_icb_cmd_addr,
output fio_icb_cmd_read,
output [`E203_XLEN-1:0] fio_icb_cmd_wdata,
output [`E203_XLEN/8-1:0] fio_icb_cmd_wmask,
output [1:0] fio_icb_cmd_burst,
output [1:0] fio_icb_cmd_beat,
output fio_icb_cmd_lock,
output fio_icb_cmd_excl,
output [1:0] fio_icb_cmd_size,
//
// * Bus RSP channel
input fio_icb_rsp_valid,
output fio_icb_rsp_ready,
input fio_icb_rsp_err ,
input fio_icb_rsp_excl_ok,
input [`E203_XLEN-1:0] fio_icb_rsp_rdata,
`endif//}
`ifdef E203_HAS_MEM_ITF //{
//////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////
// The ICB Interface from Ifetch
//
input mem_icb_enable,
// * Bus cmd channel
output mem_icb_cmd_valid,
input mem_icb_cmd_ready,
output [`E203_ADDR_SIZE-1:0] mem_icb_cmd_addr,
output mem_icb_cmd_read,
output [`E203_XLEN-1:0] mem_icb_cmd_wdata,
output [`E203_XLEN/8-1:0] mem_icb_cmd_wmask,
output [1:0] mem_icb_cmd_burst,
output [1:0] mem_icb_cmd_beat,
output mem_icb_cmd_lock,
output mem_icb_cmd_excl,
output [1:0] mem_icb_cmd_size,
//
// * Bus RSP channel
input mem_icb_rsp_valid,
output mem_icb_rsp_ready,
input mem_icb_rsp_err ,
input mem_icb_rsp_excl_ok,
input [`E203_XLEN-1:0] mem_icb_rsp_rdata,
`endif//}
input clk,
input rst_n
);
`ifdef E203_HAS_MEM_ITF //{
localparam BIU_ARBT_I_NUM = 2;
localparam BIU_ARBT_I_PTR_W = 1;
`else//}{
localparam BIU_ARBT_I_NUM = 1;
localparam BIU_ARBT_I_PTR_W = 1;
`endif//}
// The SPLT_NUM is the sum of following components
// * ppi, clint, plic, SystemITF, Fast-IO, IFU-err
localparam BIU_SPLT_I_NUM_0 = 4;
`ifdef E203_HAS_MEM_ITF //{
localparam BIU_SPLT_I_NUM_1 = (BIU_SPLT_I_NUM_0 + 1);
`else//}{
localparam BIU_SPLT_I_NUM_1 = BIU_SPLT_I_NUM_0;
`endif//}
`ifdef E203_HAS_FIO //{
localparam BIU_SPLT_I_NUM_2 = (BIU_SPLT_I_NUM_1 + 1);
`else//}{
localparam BIU_SPLT_I_NUM_2 = BIU_SPLT_I_NUM_1;
`endif//}
localparam BIU_SPLT_I_NUM = BIU_SPLT_I_NUM_2;
wire ifuerr_icb_cmd_valid;
wire ifuerr_icb_cmd_ready;
wire [`E203_ADDR_SIZE-1:0] ifuerr_icb_cmd_addr;
wire ifuerr_icb_cmd_read;
wire [2-1:0] ifuerr_icb_cmd_burst;
wire [2-1:0] ifuerr_icb_cmd_beat;
wire [`E203_XLEN-1:0] ifuerr_icb_cmd_wdata;
wire [`E203_XLEN/8-1:0] ifuerr_icb_cmd_wmask;
wire ifuerr_icb_cmd_lock;
wire ifuerr_icb_cmd_excl;
wire [1:0] ifuerr_icb_cmd_size;
wire ifuerr_icb_rsp_valid;
wire ifuerr_icb_rsp_ready;
wire ifuerr_icb_rsp_err ;
wire ifuerr_icb_rsp_excl_ok;
wire [`E203_XLEN-1:0] ifuerr_icb_rsp_rdata;
wire arbt_icb_cmd_valid;
wire arbt_icb_cmd_ready;
wire [`E203_ADDR_SIZE-1:0] arbt_icb_cmd_addr;
wire arbt_icb_cmd_read;
wire [`E203_XLEN-1:0] arbt_icb_cmd_wdata;
wire [`E203_XLEN/8-1:0] arbt_icb_cmd_wmask;
wire [1:0] arbt_icb_cmd_burst;
wire [1:0] arbt_icb_cmd_beat;
wire arbt_icb_cmd_lock;
wire arbt_icb_cmd_excl;
wire [1:0] arbt_icb_cmd_size;
wire arbt_icb_cmd_usr;
wire arbt_icb_rsp_valid;
wire arbt_icb_rsp_ready;
wire arbt_icb_rsp_err;
wire arbt_icb_rsp_excl_ok;
wire [`E203_XLEN-1:0] arbt_icb_rsp_rdata;
wire [BIU_ARBT_I_NUM*1-1:0] arbt_bus_icb_cmd_valid;
wire [BIU_ARBT_I_NUM*1-1:0] arbt_bus_icb_cmd_ready;
wire [BIU_ARBT_I_NUM*`E203_ADDR_SIZE-1:0] arbt_bus_icb_cmd_addr;
wire [BIU_ARBT_I_NUM*1-1:0] arbt_bus_icb_cmd_read;
wire [BIU_ARBT_I_NUM*`E203_XLEN-1:0] arbt_bus_icb_cmd_wdata;
wire [BIU_ARBT_I_NUM*`E203_XLEN/8-1:0] arbt_bus_icb_cmd_wmask;
wire [BIU_ARBT_I_NUM*2-1:0] arbt_bus_icb_cmd_burst;
wire [BIU_ARBT_I_NUM*2-1:0] arbt_bus_icb_cmd_beat;
wire [BIU_ARBT_I_NUM*1-1:0] arbt_bus_icb_cmd_lock;
wire [BIU_ARBT_I_NUM*1-1:0] arbt_bus_icb_cmd_excl;
wire [BIU_ARBT_I_NUM*2-1:0] arbt_bus_icb_cmd_size;
wire [BIU_ARBT_I_NUM*1-1:0] arbt_bus_icb_cmd_usr;
wire [BIU_ARBT_I_NUM*1-1:0] arbt_bus_icb_rsp_valid;
wire [BIU_ARBT_I_NUM*1-1:0] arbt_bus_icb_rsp_ready;
wire [BIU_ARBT_I_NUM*1-1:0] arbt_bus_icb_rsp_err;
wire [BIU_ARBT_I_NUM*1-1:0] arbt_bus_icb_rsp_excl_ok;
wire [BIU_ARBT_I_NUM*`E203_XLEN-1:0] arbt_bus_icb_rsp_rdata;
//CMD Channel
assign arbt_bus_icb_cmd_valid =
// The LSU take higher priority
{
`ifdef E203_HAS_MEM_ITF //{
ifu2biu_icb_cmd_valid,
`endif//}
lsu2biu_icb_cmd_valid
} ;
assign arbt_bus_icb_cmd_addr =
{
`ifdef E203_HAS_MEM_ITF //{
ifu2biu_icb_cmd_addr,
`endif//}
lsu2biu_icb_cmd_addr
} ;
assign arbt_bus_icb_cmd_read =
{
`ifdef E203_HAS_MEM_ITF //{
ifu2biu_icb_cmd_read,
`endif//}
lsu2biu_icb_cmd_read
} ;
assign arbt_bus_icb_cmd_wdata =
{
`ifdef E203_HAS_MEM_ITF //{
ifu2biu_icb_cmd_wdata,
`endif//}
lsu2biu_icb_cmd_wdata
} ;
assign arbt_bus_icb_cmd_wmask =
{
`ifdef E203_HAS_MEM_ITF //{
ifu2biu_icb_cmd_wmask,
`endif//}
lsu2biu_icb_cmd_wmask
} ;
assign arbt_bus_icb_cmd_burst =
{
`ifdef E203_HAS_MEM_ITF //{
ifu2biu_icb_cmd_burst,
`endif//}
lsu2biu_icb_cmd_burst
} ;
assign arbt_bus_icb_cmd_beat =
{
`ifdef E203_HAS_MEM_ITF //{
ifu2biu_icb_cmd_beat,
`endif//}
lsu2biu_icb_cmd_beat
} ;
assign arbt_bus_icb_cmd_lock =
{
`ifdef E203_HAS_MEM_ITF //{
ifu2biu_icb_cmd_lock,
`endif//}
lsu2biu_icb_cmd_lock
} ;
assign arbt_bus_icb_cmd_excl =
{
`ifdef E203_HAS_MEM_ITF //{
ifu2biu_icb_cmd_excl,
`endif//}
lsu2biu_icb_cmd_excl
} ;
assign arbt_bus_icb_cmd_size =
{
`ifdef E203_HAS_MEM_ITF //{
ifu2biu_icb_cmd_size,
`endif//}
lsu2biu_icb_cmd_size
} ;
wire ifu2biu_icb_cmd_ifu = 1'b1;
wire lsu2biu_icb_cmd_ifu = 1'b0;
assign arbt_bus_icb_cmd_usr =
{
`ifdef E203_HAS_MEM_ITF //{
ifu2biu_icb_cmd_ifu,
`endif//}
lsu2biu_icb_cmd_ifu
} ;
assign {
`ifdef E203_HAS_MEM_ITF //{
ifu2biu_icb_cmd_ready,
`endif//}
lsu2biu_icb_cmd_ready
} = arbt_bus_icb_cmd_ready;
//RSP Channel
assign {
`ifdef E203_HAS_MEM_ITF //{
ifu2biu_icb_rsp_valid,
`endif//}
lsu2biu_icb_rsp_valid
} = arbt_bus_icb_rsp_valid;
assign {
`ifdef E203_HAS_MEM_ITF //{
ifu2biu_icb_rsp_err,
`endif//}
lsu2biu_icb_rsp_err
} = arbt_bus_icb_rsp_err;
assign {
`ifdef E203_HAS_MEM_ITF //{
ifu2biu_icb_rsp_excl_ok,
`endif//}
lsu2biu_icb_rsp_excl_ok
} = arbt_bus_icb_rsp_excl_ok;
assign {
`ifdef E203_HAS_MEM_ITF //{
ifu2biu_icb_rsp_rdata,
`endif//}
lsu2biu_icb_rsp_rdata
} = arbt_bus_icb_rsp_rdata;
assign arbt_bus_icb_rsp_ready = {
`ifdef E203_HAS_MEM_ITF //{
ifu2biu_icb_rsp_ready,
`endif//}
lsu2biu_icb_rsp_ready
};
sirv_gnrl_icb_arbt # (
.ARBT_SCHEME (0),// Priority based
.ALLOW_0CYCL_RSP (0),// Dont allow the 0 cycle response because in BIU we always have CMD_DP larger than 0
// when the response come back from the external bus, it is at least 1 cycle later
.FIFO_OUTS_NUM (`E203_BIU_OUTS_NUM),
.FIFO_CUT_READY (`E203_BIU_CMD_CUT_READY),
.ARBT_NUM (BIU_ARBT_I_NUM),
.ARBT_PTR_W (BIU_ARBT_I_PTR_W),
.USR_W (1),
.AW (`E203_ADDR_SIZE),
.DW (`E203_XLEN)
) u_biu_icb_arbt(
.o_icb_cmd_valid (arbt_icb_cmd_valid ) ,
.o_icb_cmd_ready (arbt_icb_cmd_ready ) ,
.o_icb_cmd_read (arbt_icb_cmd_read ) ,
.o_icb_cmd_addr (arbt_icb_cmd_addr ) ,
.o_icb_cmd_wdata (arbt_icb_cmd_wdata ) ,
.o_icb_cmd_wmask (arbt_icb_cmd_wmask) ,
.o_icb_cmd_burst (arbt_icb_cmd_burst) ,
.o_icb_cmd_beat (arbt_icb_cmd_beat ) ,
.o_icb_cmd_excl (arbt_icb_cmd_excl ) ,
.o_icb_cmd_lock (arbt_icb_cmd_lock ) ,
.o_icb_cmd_size (arbt_icb_cmd_size ) ,
.o_icb_cmd_usr (arbt_icb_cmd_usr ) ,
.o_icb_rsp_valid (arbt_icb_rsp_valid ) ,
.o_icb_rsp_ready (arbt_icb_rsp_ready ) ,
.o_icb_rsp_err (arbt_icb_rsp_err) ,
.o_icb_rsp_excl_ok (arbt_icb_rsp_excl_ok) ,
.o_icb_rsp_rdata (arbt_icb_rsp_rdata ) ,
.o_icb_rsp_usr (1'b0 ) ,
.i_bus_icb_cmd_ready (arbt_bus_icb_cmd_ready ) ,
.i_bus_icb_cmd_valid (arbt_bus_icb_cmd_valid ) ,
.i_bus_icb_cmd_read (arbt_bus_icb_cmd_read ) ,
.i_bus_icb_cmd_addr (arbt_bus_icb_cmd_addr ) ,
.i_bus_icb_cmd_wdata (arbt_bus_icb_cmd_wdata ) ,
.i_bus_icb_cmd_wmask (arbt_bus_icb_cmd_wmask) ,
.i_bus_icb_cmd_burst (arbt_bus_icb_cmd_burst),
.i_bus_icb_cmd_beat (arbt_bus_icb_cmd_beat ),
.i_bus_icb_cmd_excl (arbt_bus_icb_cmd_excl ),
.i_bus_icb_cmd_lock (arbt_bus_icb_cmd_lock ),
.i_bus_icb_cmd_size (arbt_bus_icb_cmd_size ),
.i_bus_icb_cmd_usr (arbt_bus_icb_cmd_usr ),
.i_bus_icb_rsp_valid (arbt_bus_icb_rsp_valid ) ,
.i_bus_icb_rsp_ready (arbt_bus_icb_rsp_ready ) ,
.i_bus_icb_rsp_err (arbt_bus_icb_rsp_err) ,
.i_bus_icb_rsp_excl_ok (arbt_bus_icb_rsp_excl_ok),
.i_bus_icb_rsp_rdata (arbt_bus_icb_rsp_rdata ) ,
.i_bus_icb_rsp_usr () ,
.clk (clk ) ,
.rst_n (rst_n)
);
//// To breakup the dead-lock cases, when incoming load/store request to the BIU but not granted
//// This kind of potential deadlock case only happened at the low end core, where the ifetch response
//// provided to IFU, but IFU cannot accept it because it is waiting the IR stage to be cleared, and IR
//// stage is waiting the LSU to be cleared, and LSU is waiting this BIU to be cleared.
//// At any mid of high end core (or with multiple oustandings), we definitely will update IFU
//// to make sure it always can accept any oustanding transactions traded with area cost.
//// So back to this very low end core, to save areas, we prefetch without knowing if IR can accept
//// the response or not, and also in very low end core it is just 1 oustanding (multiple oustanding
//// belong to mid or high end core), so to cut off this deadlocks, we just let the BIU to trigger
//// and replay indication if LSU cannot get granted, if IFU just overkilly forced to be replayed, it
//// just lost performance, but we dont care, because in low end core, ifetch to system mem is not
//// guranteed by performance. If IFU really suppose to be replayed, then good luck to break this deadlock.
//wire ifu_replay_r;
//// The IFU replay will be set when:
//// * Accessed by non-IFU access
//// * Or non-IFU access is to access ITCM, but not granted
//wire ifu_replay_set = (arbt_icb_cmd_valid & arbt_icb_cmd_ready & lsu2biu_icb_cmd_valid)
// | (lsu2biu_icb_cmd_valid & (~lsu2biu_icb_cmd_ready));
//// The IFU replay will be cleared after accessed by a IFU access
//wire ifu_replay_clr = (arbt_icb_cmd_valid & arbt_icb_cmd_ready & ifu2biu_icb_cmd_valid);
//wire ifu_replay_ena = ifu_replay_set | ifu_replay_clr;
//wire ifu_replay_nxt = ifu_replay_set | (~ifu_replay_clr);
//sirv_gnrl_dfflr #(1)ifu_replay_dffl(ifu_replay_ena, ifu_replay_nxt, ifu_replay_r, clk, rst_n);
//assign ifu2biu_replay = ifu_replay_r;
wire buf_icb_cmd_valid;
wire buf_icb_cmd_ready;
wire [`E203_ADDR_SIZE-1:0] buf_icb_cmd_addr;
wire buf_icb_cmd_read;
wire [`E203_XLEN-1:0] buf_icb_cmd_wdata;
wire [`E203_XLEN/8-1:0] buf_icb_cmd_wmask;
wire [1:0] buf_icb_cmd_burst;
wire [1:0] buf_icb_cmd_beat;
wire buf_icb_cmd_lock;
wire buf_icb_cmd_excl;
wire [1:0] buf_icb_cmd_size;
wire buf_icb_cmd_usr;
wire buf_icb_cmd_ifu = buf_icb_cmd_usr;
wire buf_icb_rsp_valid;
wire buf_icb_rsp_ready;
wire buf_icb_rsp_err;
wire buf_icb_rsp_excl_ok;
wire [`E203_XLEN-1:0] buf_icb_rsp_rdata;
wire icb_buffer_active;
sirv_gnrl_icb_buffer # (
.OUTS_CNT_W (`E203_BIU_OUTS_CNT_W),
.AW (`E203_ADDR_SIZE),
.DW (`E203_XLEN),
.CMD_DP(`E203_BIU_CMD_DP),
.RSP_DP(`E203_BIU_RSP_DP),
.CMD_CUT_READY (`E203_BIU_CMD_CUT_READY),
.RSP_CUT_READY (`E203_BIU_RSP_CUT_READY),
.USR_W (1)
)u_sirv_gnrl_icb_buffer(
.icb_buffer_active (icb_buffer_active),
.i_icb_cmd_valid (arbt_icb_cmd_valid),
.i_icb_cmd_ready (arbt_icb_cmd_ready),
.i_icb_cmd_read (arbt_icb_cmd_read ),
.i_icb_cmd_addr (arbt_icb_cmd_addr ),
.i_icb_cmd_wdata (arbt_icb_cmd_wdata),
.i_icb_cmd_wmask (arbt_icb_cmd_wmask),
.i_icb_cmd_lock (arbt_icb_cmd_lock ),
.i_icb_cmd_excl (arbt_icb_cmd_excl ),
.i_icb_cmd_size (arbt_icb_cmd_size ),
.i_icb_cmd_burst (arbt_icb_cmd_burst),
.i_icb_cmd_beat (arbt_icb_cmd_beat ),
.i_icb_cmd_usr (arbt_icb_cmd_usr ),
.i_icb_rsp_valid (arbt_icb_rsp_valid),
.i_icb_rsp_ready (arbt_icb_rsp_ready),
.i_icb_rsp_err (arbt_icb_rsp_err ),
.i_icb_rsp_excl_ok (arbt_icb_rsp_excl_ok),
.i_icb_rsp_rdata (arbt_icb_rsp_rdata),
.i_icb_rsp_usr (),
.o_icb_cmd_valid (buf_icb_cmd_valid),
.o_icb_cmd_ready (buf_icb_cmd_ready),
.o_icb_cmd_read (buf_icb_cmd_read ),
.o_icb_cmd_addr (buf_icb_cmd_addr ),
.o_icb_cmd_wdata (buf_icb_cmd_wdata),
.o_icb_cmd_wmask (buf_icb_cmd_wmask),
.o_icb_cmd_lock (buf_icb_cmd_lock ),
.o_icb_cmd_excl (buf_icb_cmd_excl ),
.o_icb_cmd_size (buf_icb_cmd_size ),
.o_icb_cmd_burst (buf_icb_cmd_burst),
.o_icb_cmd_beat (buf_icb_cmd_beat ),
.o_icb_cmd_usr (buf_icb_cmd_usr),
.o_icb_rsp_valid (buf_icb_rsp_valid),
.o_icb_rsp_ready (buf_icb_rsp_ready),
.o_icb_rsp_err (buf_icb_rsp_err ),
.o_icb_rsp_excl_ok (buf_icb_rsp_excl_ok),
.o_icb_rsp_rdata (buf_icb_rsp_rdata),
.o_icb_rsp_usr (1'b0 ),
.clk (clk ),
.rst_n (rst_n)
);
wire [BIU_SPLT_I_NUM*1-1:0] splt_bus_icb_cmd_valid;
wire [BIU_SPLT_I_NUM*1-1:0] splt_bus_icb_cmd_ready;
wire [BIU_SPLT_I_NUM*`E203_ADDR_SIZE-1:0] splt_bus_icb_cmd_addr;
wire [BIU_SPLT_I_NUM*1-1:0] splt_bus_icb_cmd_read;
wire [BIU_SPLT_I_NUM*`E203_XLEN-1:0] splt_bus_icb_cmd_wdata;
wire [BIU_SPLT_I_NUM*`E203_XLEN/8-1:0] splt_bus_icb_cmd_wmask;
wire [BIU_SPLT_I_NUM*2-1:0] splt_bus_icb_cmd_burst;
wire [BIU_SPLT_I_NUM*2-1:0] splt_bus_icb_cmd_beat;
wire [BIU_SPLT_I_NUM*1-1:0] splt_bus_icb_cmd_lock;
wire [BIU_SPLT_I_NUM*1-1:0] splt_bus_icb_cmd_excl;
wire [BIU_SPLT_I_NUM*2-1:0] splt_bus_icb_cmd_size;
wire [BIU_SPLT_I_NUM*1-1:0] splt_bus_icb_rsp_valid;
wire [BIU_SPLT_I_NUM*1-1:0] splt_bus_icb_rsp_ready;
wire [BIU_SPLT_I_NUM*1-1:0] splt_bus_icb_rsp_err;
wire [BIU_SPLT_I_NUM*1-1:0] splt_bus_icb_rsp_excl_ok;
wire [BIU_SPLT_I_NUM*`E203_XLEN-1:0] splt_bus_icb_rsp_rdata;
//CMD Channel
assign {
ifuerr_icb_cmd_valid
, ppi_icb_cmd_valid
, clint_icb_cmd_valid
, plic_icb_cmd_valid
`ifdef E203_HAS_FIO //{
, fio_icb_cmd_valid
`endif//}
`ifdef E203_HAS_MEM_ITF //{
, mem_icb_cmd_valid
`endif//}
} = splt_bus_icb_cmd_valid;
assign {
ifuerr_icb_cmd_addr
, ppi_icb_cmd_addr
, clint_icb_cmd_addr
, plic_icb_cmd_addr
`ifdef E203_HAS_FIO //{
, fio_icb_cmd_addr
`endif//}
`ifdef E203_HAS_MEM_ITF //{
, mem_icb_cmd_addr
`endif//}
} = splt_bus_icb_cmd_addr;
assign {
ifuerr_icb_cmd_read
, ppi_icb_cmd_read
, clint_icb_cmd_read
, plic_icb_cmd_read
`ifdef E203_HAS_FIO //{
, fio_icb_cmd_read
`endif//}
`ifdef E203_HAS_MEM_ITF //{
, mem_icb_cmd_read
`endif//}
} = splt_bus_icb_cmd_read;
assign {
ifuerr_icb_cmd_wdata
, ppi_icb_cmd_wdata
, clint_icb_cmd_wdata
, plic_icb_cmd_wdata
`ifdef E203_HAS_FIO //{
, fio_icb_cmd_wdata
`endif//}
`ifdef E203_HAS_MEM_ITF //{
, mem_icb_cmd_wdata
`endif//}
} = splt_bus_icb_cmd_wdata;
assign {
ifuerr_icb_cmd_wmask
, ppi_icb_cmd_wmask
, clint_icb_cmd_wmask
, plic_icb_cmd_wmask
`ifdef E203_HAS_FIO //{
, fio_icb_cmd_wmask
`endif//}
`ifdef E203_HAS_MEM_ITF //{
, mem_icb_cmd_wmask
`endif//}
} = splt_bus_icb_cmd_wmask;
assign {
ifuerr_icb_cmd_burst
, ppi_icb_cmd_burst
, clint_icb_cmd_burst
, plic_icb_cmd_burst
`ifdef E203_HAS_FIO //{
, fio_icb_cmd_burst
`endif//}
`ifdef E203_HAS_MEM_ITF //{
, mem_icb_cmd_burst
`endif//}
} = splt_bus_icb_cmd_burst;
assign {
ifuerr_icb_cmd_beat
, ppi_icb_cmd_beat
, clint_icb_cmd_beat
, plic_icb_cmd_beat
`ifdef E203_HAS_FIO //{
, fio_icb_cmd_beat
`endif//}
`ifdef E203_HAS_MEM_ITF //{
, mem_icb_cmd_beat
`endif//}
} = splt_bus_icb_cmd_beat;
assign {
ifuerr_icb_cmd_lock
, ppi_icb_cmd_lock
, clint_icb_cmd_lock
, plic_icb_cmd_lock
`ifdef E203_HAS_FIO //{
, fio_icb_cmd_lock
`endif//}
`ifdef E203_HAS_MEM_ITF //{
, mem_icb_cmd_lock
`endif//}
} = splt_bus_icb_cmd_lock;
assign {
ifuerr_icb_cmd_excl
, ppi_icb_cmd_excl
, clint_icb_cmd_excl
, plic_icb_cmd_excl
`ifdef E203_HAS_FIO //{
, fio_icb_cmd_excl
`endif//}
`ifdef E203_HAS_MEM_ITF //{
, mem_icb_cmd_excl
`endif//}
} = splt_bus_icb_cmd_excl;
assign {
ifuerr_icb_cmd_size
, ppi_icb_cmd_size
, clint_icb_cmd_size
, plic_icb_cmd_size
`ifdef E203_HAS_FIO //{
, fio_icb_cmd_size
`endif//}
`ifdef E203_HAS_MEM_ITF //{
, mem_icb_cmd_size
`endif//}
} = splt_bus_icb_cmd_size;
assign splt_bus_icb_cmd_ready = {
ifuerr_icb_cmd_ready
, ppi_icb_cmd_ready
, clint_icb_cmd_ready
, plic_icb_cmd_ready
`ifdef E203_HAS_FIO //{
, fio_icb_cmd_ready
`endif//}
`ifdef E203_HAS_MEM_ITF //{
, mem_icb_cmd_ready
`endif//}
};
//RSP Channel
assign splt_bus_icb_rsp_valid = {
ifuerr_icb_rsp_valid
, ppi_icb_rsp_valid
, clint_icb_rsp_valid
, plic_icb_rsp_valid
`ifdef E203_HAS_FIO //{
, fio_icb_rsp_valid
`endif//}
`ifdef E203_HAS_MEM_ITF //{
, mem_icb_rsp_valid
`endif//}
};
assign splt_bus_icb_rsp_err = {
ifuerr_icb_rsp_err
, ppi_icb_rsp_err
, clint_icb_rsp_err
, plic_icb_rsp_err
`ifdef E203_HAS_FIO //{
, fio_icb_rsp_err
`endif//}
`ifdef E203_HAS_MEM_ITF //{
, mem_icb_rsp_err
`endif//}
};
assign splt_bus_icb_rsp_excl_ok = {
ifuerr_icb_rsp_excl_ok
, ppi_icb_rsp_excl_ok
, clint_icb_rsp_excl_ok
, plic_icb_rsp_excl_ok
`ifdef E203_HAS_FIO //{
, fio_icb_rsp_excl_ok
`endif//}
`ifdef E203_HAS_MEM_ITF //{
, mem_icb_rsp_excl_ok
`endif//}
};
assign splt_bus_icb_rsp_rdata = {
ifuerr_icb_rsp_rdata
, ppi_icb_rsp_rdata
, clint_icb_rsp_rdata
, plic_icb_rsp_rdata
`ifdef E203_HAS_FIO //{
, fio_icb_rsp_rdata
`endif//}
`ifdef E203_HAS_MEM_ITF //{
, mem_icb_rsp_rdata
`endif//}
};
assign {
ifuerr_icb_rsp_ready
, ppi_icb_rsp_ready
, clint_icb_rsp_ready
, plic_icb_rsp_ready
`ifdef E203_HAS_FIO //{
, fio_icb_rsp_ready
`endif//}
`ifdef E203_HAS_MEM_ITF //{
, mem_icb_rsp_ready
`endif//}
} = splt_bus_icb_rsp_ready;
wire buf_icb_cmd_ppi = ppi_icb_enable & (buf_icb_cmd_addr[`E203_PPI_BASE_REGION] == ppi_region_indic[`E203_PPI_BASE_REGION]);
wire buf_icb_sel_ppi = buf_icb_cmd_ppi & (~buf_icb_cmd_ifu);
wire buf_icb_cmd_clint = clint_icb_enable & (buf_icb_cmd_addr[`E203_CLINT_BASE_REGION] == clint_region_indic[`E203_CLINT_BASE_REGION]);
wire buf_icb_sel_clint = buf_icb_cmd_clint & (~buf_icb_cmd_ifu);
wire buf_icb_cmd_plic = plic_icb_enable & (buf_icb_cmd_addr[`E203_PLIC_BASE_REGION] == plic_region_indic[`E203_PLIC_BASE_REGION]);
wire buf_icb_sel_plic = buf_icb_cmd_plic & (~buf_icb_cmd_ifu);
`ifdef E203_HAS_FIO //{
wire buf_icb_cmd_fio = fio_icb_enable & (buf_icb_cmd_addr[`E203_FIO_BASE_REGION] == fio_region_indic[`E203_FIO_BASE_REGION]);
wire buf_icb_sel_fio = buf_icb_cmd_fio & (~buf_icb_cmd_ifu);
`endif//}
wire buf_icb_sel_ifuerr =(
buf_icb_cmd_ppi
| buf_icb_cmd_clint
| buf_icb_cmd_plic
`ifdef E203_HAS_FIO //{
| buf_icb_cmd_fio
`endif//}
) & buf_icb_cmd_ifu;
`ifdef E203_HAS_MEM_ITF //{
wire buf_icb_sel_mem = mem_icb_enable
& (~buf_icb_sel_ifuerr)
& (~buf_icb_sel_ppi)
& (~buf_icb_sel_clint)
& (~buf_icb_sel_plic)
`ifdef E203_HAS_FIO //{
& (~buf_icb_sel_fio)
`endif//}
;
`endif//}
wire [BIU_SPLT_I_NUM-1:0] buf_icb_splt_indic =
{
buf_icb_sel_ifuerr
, buf_icb_sel_ppi
, buf_icb_sel_clint
, buf_icb_sel_plic
`ifdef E203_HAS_FIO //{
, buf_icb_sel_fio
`endif//}
`ifdef E203_HAS_MEM_ITF //{
, buf_icb_sel_mem
`endif//}
};
sirv_gnrl_icb_splt # (
.ALLOW_DIFF (0),// Dont allow different branches oustanding
.ALLOW_0CYCL_RSP (1),// Allow the 0 cycle response because in BIU the splt
// is after the buffer, and will directly talk to the external
// bus, where maybe the ROM is 0 cycle responsed.
.FIFO_OUTS_NUM (`E203_BIU_OUTS_NUM),
.FIFO_CUT_READY (`E203_BIU_CMD_CUT_READY),
.SPLT_NUM (BIU_SPLT_I_NUM),
.SPLT_PTR_W (BIU_SPLT_I_NUM),
.SPLT_PTR_1HOT (1),
.USR_W (1),
.AW (`E203_ADDR_SIZE),
.DW (`E203_XLEN)
) u_biu_icb_splt(
.i_icb_splt_indic (buf_icb_splt_indic),
.i_icb_cmd_valid (buf_icb_cmd_valid ) ,
.i_icb_cmd_ready (buf_icb_cmd_ready ) ,
.i_icb_cmd_read (buf_icb_cmd_read ) ,
.i_icb_cmd_addr (buf_icb_cmd_addr ) ,
.i_icb_cmd_wdata (buf_icb_cmd_wdata ) ,
.i_icb_cmd_wmask (buf_icb_cmd_wmask) ,
.i_icb_cmd_burst (buf_icb_cmd_burst) ,
.i_icb_cmd_beat (buf_icb_cmd_beat ) ,
.i_icb_cmd_excl (buf_icb_cmd_excl ) ,
.i_icb_cmd_lock (buf_icb_cmd_lock ) ,
.i_icb_cmd_size (buf_icb_cmd_size ) ,
.i_icb_cmd_usr (1'b0 ) ,
.i_icb_rsp_valid (buf_icb_rsp_valid ) ,
.i_icb_rsp_ready (buf_icb_rsp_ready ) ,
.i_icb_rsp_err (buf_icb_rsp_err) ,
.i_icb_rsp_excl_ok (buf_icb_rsp_excl_ok) ,
.i_icb_rsp_rdata (buf_icb_rsp_rdata ) ,
.i_icb_rsp_usr ( ) ,
.o_bus_icb_cmd_ready (splt_bus_icb_cmd_ready ) ,
.o_bus_icb_cmd_valid (splt_bus_icb_cmd_valid ) ,
.o_bus_icb_cmd_read (splt_bus_icb_cmd_read ) ,
.o_bus_icb_cmd_addr (splt_bus_icb_cmd_addr ) ,
.o_bus_icb_cmd_wdata (splt_bus_icb_cmd_wdata ) ,
.o_bus_icb_cmd_wmask (splt_bus_icb_cmd_wmask) ,
.o_bus_icb_cmd_burst (splt_bus_icb_cmd_burst),
.o_bus_icb_cmd_beat (splt_bus_icb_cmd_beat ),
.o_bus_icb_cmd_excl (splt_bus_icb_cmd_excl ),
.o_bus_icb_cmd_lock (splt_bus_icb_cmd_lock ),
.o_bus_icb_cmd_size (splt_bus_icb_cmd_size ),
.o_bus_icb_cmd_usr () ,
.o_bus_icb_rsp_valid (splt_bus_icb_rsp_valid ) ,
.o_bus_icb_rsp_ready (splt_bus_icb_rsp_ready ) ,
.o_bus_icb_rsp_err (splt_bus_icb_rsp_err) ,
.o_bus_icb_rsp_excl_ok (splt_bus_icb_rsp_excl_ok),
.o_bus_icb_rsp_rdata (splt_bus_icb_rsp_rdata ) ,
.o_bus_icb_rsp_usr ({BIU_SPLT_I_NUM{1'b0}}) ,
.clk (clk ) ,
.rst_n (rst_n)
);
assign biu_active = ifu2biu_icb_cmd_valid | lsu2biu_icb_cmd_valid | icb_buffer_active;
///////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////
// Implement the IFU-accessed-Peripheral region error
assign ifuerr_icb_cmd_ready = ifuerr_icb_rsp_ready;
// 0 Cycle response
assign ifuerr_icb_rsp_valid = ifuerr_icb_cmd_valid;
assign ifuerr_icb_rsp_err = 1'b1;
assign ifuerr_icb_rsp_excl_ok = 1'b0;
assign ifuerr_icb_rsp_rdata = {`E203_XLEN{1'b0}};
endmodule
|
module sirv_pwm16_core(
input clock,
input reset,
input io_regs_cfg_write_valid,
input [31:0] io_regs_cfg_write_bits,
output [31:0] io_regs_cfg_read,
input io_regs_countLo_write_valid,
input [31:0] io_regs_countLo_write_bits,
output [31:0] io_regs_countLo_read,
input io_regs_countHi_write_valid,
input [31:0] io_regs_countHi_write_bits,
output [31:0] io_regs_countHi_read,
input io_regs_s_write_valid,
input [15:0] io_regs_s_write_bits,
output [15:0] io_regs_s_read,
input io_regs_cmp_0_write_valid,
input [15:0] io_regs_cmp_0_write_bits,
output [15:0] io_regs_cmp_0_read,
input io_regs_cmp_1_write_valid,
input [15:0] io_regs_cmp_1_write_bits,
output [15:0] io_regs_cmp_1_read,
input io_regs_cmp_2_write_valid,
input [15:0] io_regs_cmp_2_write_bits,
output [15:0] io_regs_cmp_2_read,
input io_regs_cmp_3_write_valid,
input [15:0] io_regs_cmp_3_write_bits,
output [15:0] io_regs_cmp_3_read,
input io_regs_feed_write_valid,
input [31:0] io_regs_feed_write_bits,
output [31:0] io_regs_feed_read,
input io_regs_key_write_valid,
input [31:0] io_regs_key_write_bits,
output [31:0] io_regs_key_read,
output io_ip_0,
output io_ip_1,
output io_ip_2,
output io_ip_3,
output io_gpio_0,
output io_gpio_1,
output io_gpio_2,
output io_gpio_3
);
wire [3:0] T_178;
reg [3:0] scale;
reg [31:0] GEN_22;
wire [3:0] GEN_0;
reg [15:0] cmp_0;
reg [31:0] GEN_23;
wire [15:0] GEN_1;
reg [15:0] cmp_1;
reg [31:0] GEN_24;
wire [15:0] GEN_2;
reg [15:0] cmp_2;
reg [31:0] GEN_25;
wire [15:0] GEN_3;
reg [15:0] cmp_3;
reg [31:0] GEN_26;
wire [15:0] GEN_4;
wire countEn;
reg [4:0] T_196;
reg [31:0] GEN_27;
wire [4:0] GEN_18;
wire [5:0] T_197;
reg [25:0] T_199;
reg [31:0] GEN_28;
wire T_200;
wire [26:0] T_202;
wire [26:0] GEN_5;
wire [30:0] T_203;
wire [32:0] T_207;
wire [27:0] T_208;
wire [32:0] GEN_6;
wire [27:0] GEN_7;
wire [30:0] T_209;
wire [15:0] s;
wire T_210;
wire [3:0] T_211;
reg [3:0] center;
reg [31:0] GEN_29;
wire [3:0] GEN_8;
wire T_215;
wire T_216;
wire [15:0] T_217;
wire [15:0] T_218;
wire elapsed_0;
wire T_220;
wire T_221;
wire [15:0] T_223;
wire elapsed_1;
wire T_225;
wire T_226;
wire [15:0] T_228;
wire elapsed_2;
wire T_230;
wire T_231;
wire [15:0] T_233;
wire elapsed_3;
wire [5:0] GEN_19;
wire [5:0] T_234;
wire [4:0] T_235;
wire [26:0] GEN_20;
wire [26:0] T_239;
wire [26:0] T_241;
wire [25:0] T_242;
wire [30:0] T_243;
wire [4:0] GEN_21;
wire [5:0] T_245;
wire [4:0] T_246;
wire [30:0] T_247;
wire feed;
wire T_248;
reg zerocmp;
reg [31:0] GEN_30;
wire GEN_9;
wire T_252;
wire countReset;
wire [32:0] GEN_10;
wire [27:0] GEN_11;
wire T_255;
reg T_259;
reg [31:0] GEN_31;
wire GEN_12;
wire T_261;
wire T_262;
wire T_263;
reg T_267;
reg [31:0] GEN_32;
wire GEN_13;
wire T_268;
reg T_269;
reg [31:0] GEN_33;
wire [1:0] T_282;
wire [1:0] T_283;
wire [3:0] T_284;
reg [3:0] ip;
reg [31:0] GEN_34;
wire [1:0] T_286;
wire [1:0] T_287;
wire [3:0] T_288;
wire [3:0] T_289;
wire [3:0] T_290;
wire [3:0] T_297;
wire [3:0] T_298;
wire [3:0] T_299;
wire [3:0] T_300;
wire [3:0] T_301;
wire [3:0] T_304;
wire [3:0] GEN_14;
wire [3:0] T_305;
reg [3:0] gang;
reg [31:0] GEN_35;
wire [3:0] GEN_15;
wire T_316;
wire T_319;
wire T_323;
reg oneShot;
reg [31:0] GEN_36;
wire GEN_16;
wire T_325;
reg countAlways;
reg [31:0] GEN_37;
wire GEN_17;
wire [4:0] T_333;
wire [8:0] T_334;
wire [1:0] T_335;
wire [2:0] T_336;
wire [11:0] T_337;
wire [2:0] T_338;
wire [3:0] T_339;
wire [7:0] T_340;
wire [7:0] T_341;
wire [15:0] T_342;
wire [19:0] T_343;
wire [31:0] T_344;
wire T_350_0;
wire T_350_1;
wire T_350_2;
wire T_350_3;
wire T_352;
wire T_353;
wire T_354;
wire T_355;
wire [2:0] T_357;
wire [3:0] T_358;
wire [3:0] T_359;
wire [3:0] T_360;
wire [3:0] T_361;
wire T_364_0;
wire T_364_1;
wire T_364_2;
wire T_364_3;
wire T_366;
wire T_367;
wire T_368;
wire T_369;
wire T_370;
assign io_regs_cfg_read = T_344;
assign io_regs_countLo_read = {{1'd0}, T_203};
assign io_regs_countHi_read = 32'h0;
assign io_regs_s_read = s;
assign io_regs_cmp_0_read = cmp_0;
assign io_regs_cmp_1_read = cmp_1;
assign io_regs_cmp_2_read = cmp_2;
assign io_regs_cmp_3_read = cmp_3;
assign io_regs_feed_read = 32'h0;
assign io_regs_key_read = 32'h1;
assign io_ip_0 = T_350_0;
assign io_ip_1 = T_350_1;
assign io_ip_2 = T_350_2;
assign io_ip_3 = T_350_3;
assign io_gpio_0 = T_364_0;
assign io_gpio_1 = T_364_1;
assign io_gpio_2 = T_364_2;
assign io_gpio_3 = T_364_3;
assign T_178 = io_regs_cfg_write_bits[3:0];
assign GEN_0 = io_regs_cfg_write_valid ? T_178 : scale;
assign GEN_1 = io_regs_cmp_0_write_valid ? io_regs_cmp_0_write_bits : cmp_0;
assign GEN_2 = io_regs_cmp_1_write_valid ? io_regs_cmp_1_write_bits : cmp_1;
assign GEN_3 = io_regs_cmp_2_write_valid ? io_regs_cmp_2_write_bits : cmp_2;
assign GEN_4 = io_regs_cmp_3_write_valid ? io_regs_cmp_3_write_bits : cmp_3;
assign countEn = T_370;
assign GEN_18 = {{4'd0}, countEn};
assign T_197 = T_196 + GEN_18;
assign T_200 = T_197[5];
assign T_202 = T_199 + 26'h1;
assign GEN_5 = T_200 ? T_202 : {{1'd0}, T_199};
assign T_203 = {T_199,T_196};
assign T_207 = {1'h0,io_regs_countLo_write_bits};
assign T_208 = T_207[32:5];
assign GEN_6 = io_regs_countLo_write_valid ? T_207 : {{27'd0}, T_197};
assign GEN_7 = io_regs_countLo_write_valid ? T_208 : {{1'd0}, GEN_5};
assign T_209 = T_203 >> scale;
assign s = T_209[15:0];
assign T_210 = s[15];
assign T_211 = io_regs_cfg_write_bits[19:16];
assign GEN_8 = io_regs_cfg_write_valid ? T_211 : center;
assign T_215 = center[0];
assign T_216 = T_210 & T_215;
assign T_217 = ~ s;
assign T_218 = T_216 ? T_217 : s;
assign elapsed_0 = T_218 >= cmp_0;
assign T_220 = center[1];
assign T_221 = T_210 & T_220;
assign T_223 = T_221 ? T_217 : s;
assign elapsed_1 = T_223 >= cmp_1;
assign T_225 = center[2];
assign T_226 = T_210 & T_225;
assign T_228 = T_226 ? T_217 : s;
assign elapsed_2 = T_228 >= cmp_2;
assign T_230 = center[3];
assign T_231 = T_210 & T_230;
assign T_233 = T_231 ? T_217 : s;
assign elapsed_3 = T_233 >= cmp_3;
assign GEN_19 = {{1'd0}, T_196};
assign T_234 = GEN_19 ^ T_197;
assign T_235 = T_234[5:1];
assign GEN_20 = {{1'd0}, T_199};
assign T_239 = GEN_20 ^ T_202;
assign T_241 = T_200 ? T_239 : 27'h0;
assign T_242 = T_241[26:1];
assign T_243 = {T_242,T_235};
assign GEN_21 = {{1'd0}, scale};
assign T_245 = GEN_21 + 5'h10;
assign T_246 = T_245[4:0];
assign T_247 = T_243 >> T_246;
assign feed = T_247[0];
assign T_248 = io_regs_cfg_write_bits[9];
assign GEN_9 = io_regs_cfg_write_valid ? T_248 : zerocmp;
assign T_252 = zerocmp & elapsed_0;
assign countReset = feed | T_252;
assign GEN_10 = countReset ? 33'h0 : GEN_6;
assign GEN_11 = countReset ? 28'h0 : GEN_7;
assign T_255 = io_regs_cfg_write_bits[10];
assign GEN_12 = io_regs_cfg_write_valid ? T_255 : T_259;
assign T_261 = countReset == 1'h0;
assign T_262 = T_259 & T_261;
assign T_263 = io_regs_cfg_write_bits[8];
assign GEN_13 = io_regs_cfg_write_valid ? T_263 : T_267;
assign T_268 = T_262 | T_267;
assign T_282 = {T_221,T_216};
assign T_283 = {T_231,T_226};
assign T_284 = {T_283,T_282};
assign T_286 = {elapsed_1,elapsed_0};
assign T_287 = {elapsed_3,elapsed_2};
assign T_288 = {T_287,T_286};
assign T_289 = T_284 & T_288;
assign T_290 = ~ T_284;
assign T_297 = T_269 ? 4'hf : 4'h0;
assign T_298 = T_297 & ip;
assign T_299 = T_288 | T_298;
assign T_300 = T_290 & T_299;
assign T_301 = T_289 | T_300;
assign T_304 = io_regs_cfg_write_bits[31:28];
assign GEN_14 = io_regs_cfg_write_valid ? T_304 : T_301;
assign T_305 = io_regs_cfg_write_bits[27:24];
assign GEN_15 = io_regs_cfg_write_valid ? T_305 : gang;
assign T_316 = io_regs_cfg_write_bits[13];
assign T_319 = T_316 & T_261;
assign T_323 = io_regs_cfg_write_valid | countReset;
assign GEN_16 = T_323 ? T_319 : oneShot;
assign T_325 = io_regs_cfg_write_bits[12];
assign GEN_17 = io_regs_cfg_write_valid ? T_325 : countAlways;
assign T_333 = {T_267,4'h0};
assign T_334 = {T_333,scale};
assign T_335 = {1'h0,T_259};
assign T_336 = {T_335,zerocmp};
assign T_337 = {T_336,T_334};
assign T_338 = {2'h0,oneShot};
assign T_339 = {T_338,countAlways};
assign T_340 = {4'h0,center};
assign T_341 = {ip,gang};
assign T_342 = {T_341,T_340};
assign T_343 = {T_342,T_339};
assign T_344 = {T_343,T_337};
assign T_350_0 = T_352;
assign T_350_1 = T_353;
assign T_350_2 = T_354;
assign T_350_3 = T_355;
assign T_352 = ip[0];
assign T_353 = ip[1];
assign T_354 = ip[2];
assign T_355 = ip[3];
assign T_357 = ip[3:1];
assign T_358 = {T_352,T_357};
assign T_359 = gang & T_358;
assign T_360 = ~ T_359;
assign T_361 = ip & T_360;
assign T_364_0 = T_366;
assign T_364_1 = T_367;
assign T_364_2 = T_368;
assign T_364_3 = T_369;
assign T_366 = T_361[0];
assign T_367 = T_361[1];
assign T_368 = T_361[2];
assign T_369 = T_361[3];
assign T_370 = countAlways | oneShot;
always @(posedge clock or posedge reset)
if(reset) begin
scale <= 4'b0;
cmp_0 <= 16'b0;
cmp_1 <= 16'b0;
cmp_2 <= 16'b0;
cmp_3 <= 16'b0;
T_196 <= 5'b0;
T_199 <= 26'b0;
center <= 4'b0;
zerocmp <= 1'b0;
T_259 <= 1'b0;
T_267 <= 1'b0;
T_269 <= 1'b0;
ip <= 4'b0;
gang <= 4'b0;
end
else begin
if (io_regs_cfg_write_valid) begin
scale <= T_178;
end
if (io_regs_cmp_0_write_valid) begin
cmp_0 <= io_regs_cmp_0_write_bits;
end
if (io_regs_cmp_1_write_valid) begin
cmp_1 <= io_regs_cmp_1_write_bits;
end
if (io_regs_cmp_2_write_valid) begin
cmp_2 <= io_regs_cmp_2_write_bits;
end
if (io_regs_cmp_3_write_valid) begin
cmp_3 <= io_regs_cmp_3_write_bits;
end
T_196 <= GEN_10[4:0];
T_199 <= GEN_11[25:0];
if (io_regs_cfg_write_valid) begin
center <= T_211;
end
if (io_regs_cfg_write_valid) begin
zerocmp <= T_248;
end
if (io_regs_cfg_write_valid) begin
T_259 <= T_255;
end
if (io_regs_cfg_write_valid) begin
T_267 <= T_263;
end
T_269 <= T_268;
if (io_regs_cfg_write_valid) begin
ip <= T_304;
end else begin
ip <= T_301;
end
if (io_regs_cfg_write_valid) begin
gang <= T_305;
end
end
always @(posedge clock or posedge reset)
if (reset) begin
oneShot <= 1'h0;
end else begin
if (T_323) begin
oneShot <= T_319;
end
end
always @(posedge clock or posedge reset)
if (reset) begin
countAlways <= 1'h0;
end else begin
if (io_regs_cfg_write_valid) begin
countAlways <= T_325;
end
end
endmodule
|
module sirv_sim_ram
#(parameter DP = 512,
parameter FORCE_X2ZERO = 0,
parameter DW = 32,
parameter MW = 4,
parameter AW = 32
)
(
input clk,
input [DW-1 :0] din,
input [AW-1 :0] addr,
input cs,
input we,
input [MW-1:0] wem,
output [DW-1:0] dout
);
reg [DW-1:0] mem_r [0:DP-1];
reg [AW-1:0] addr_r;
wire [MW-1:0] wen;
wire ren;
assign ren = cs & (~we);
assign wen = ({MW{cs & we}} & wem);
genvar i;
always @(posedge clk)
begin
if (ren) begin
addr_r <= addr;
end
end
generate
for (i = 0; i < MW; i = i+1) begin :mem
if((8*i+8) > DW ) begin: last
always @(posedge clk) begin
if (wen[i]) begin
mem_r[addr][DW-1:8*i] <= din[DW-1:8*i];
end
end
end
else begin: non_last
always @(posedge clk) begin
if (wen[i]) begin
mem_r[addr][8*i+7:8*i] <= din[8*i+7:8*i];
end
end
end
end
endgenerate
wire [DW-1:0] dout_pre;
assign dout_pre = mem_r[addr_r];
generate
if(FORCE_X2ZERO == 1) begin: force_x_to_zero
for (i = 0; i < DW; i = i+1) begin:force_x_gen
`ifndef SYNTHESIS//{
assign dout[i] = (dout_pre[i] === 1'bx) ? 1'b0 : dout_pre[i];
`else//}{
assign dout[i] = dout_pre[i];
`endif//}
end
end
else begin:no_force_x_to_zero
assign dout = dout_pre;
end
endgenerate
endmodule
|
module sirv_debug_csr
#(
parameter PC_SIZE = 32
)(
// The interface with commit stage
input [PC_SIZE-1:0] cmt_dpc,
input cmt_dpc_ena,
input [3-1:0] cmt_dcause,
input cmt_dcause_ena,
input dbg_irq_r,
// The interface with CSR control
input wr_dcsr_ena ,
input wr_dpc_ena ,
input wr_dscratch_ena,
input [32-1:0] wr_csr_nxt ,
output[32-1:0] dcsr_r ,
output[PC_SIZE-1:0] dpc_r ,
output[32-1:0] dscratch_r,
output dbg_mode,
output dbg_halt_r,
output dbg_step_r,
output dbg_ebreakm_r,
output dbg_stopcycle,
input clk,
input rst_n
);
// Implement DPC reg
wire dpc_ena = wr_dpc_ena | cmt_dpc_ena;
wire [PC_SIZE-1:0] dpc_nxt;
assign dpc_nxt[PC_SIZE-1:1] =
cmt_dpc_ena ? cmt_dpc[PC_SIZE-1:1]
: wr_csr_nxt[PC_SIZE-1:1];
assign dpc_nxt[0] = 1'b0;
sirv_gnrl_dfflr #(PC_SIZE) dpc_dfflr (dpc_ena, dpc_nxt, dpc_r, clk, rst_n);
// Implement Dbg Scratch reg
wire dscratch_ena = wr_dscratch_ena;
wire [32-1:0] dscratch_nxt;
assign dscratch_nxt = wr_csr_nxt;
sirv_gnrl_dfflr #(32) dscratch_dfflr (dscratch_ena, dscratch_nxt, dscratch_r, clk, rst_n);
// We dont support the HW Trigger Module yet now
// Implement dcsr reg
//
// The ndreset field
wire ndreset_ena = wr_dcsr_ena & wr_csr_nxt[29];
wire ndreset_nxt;
wire ndreset_r;
assign ndreset_nxt = wr_csr_nxt[29];
sirv_gnrl_dfflr #(1) ndreset_dfflr (ndreset_ena, ndreset_nxt, ndreset_r, clk, rst_n);
// This bit is not used as rocket impelmentation
//
// The fullreset field
wire fullreset_ena = wr_dcsr_ena & wr_csr_nxt[28];
wire fullreset_nxt;
wire fullreset_r;
assign fullreset_nxt = wr_csr_nxt[28];
sirv_gnrl_dfflr #(1) fullreset_dfflr (fullreset_ena, fullreset_nxt, fullreset_r, clk, rst_n);
// This bit is not used as rocket impelmentation
//
// The cause field
wire dcause_ena = cmt_dcause_ena;
wire [3-1:0] dcause_r;
wire [3-1:0] dcause_nxt = cmt_dcause;
sirv_gnrl_dfflr #(3) dcause_dfflr (dcause_ena, dcause_nxt, dcause_r, clk, rst_n);
//
// The halt field
wire halt_ena = wr_dcsr_ena;
wire halt_nxt;
wire halt_r;
assign halt_nxt = wr_csr_nxt[3];
sirv_gnrl_dfflr #(1) halt_dfflr (halt_ena, halt_nxt, halt_r, clk, rst_n);
//
// The step field
wire step_ena = wr_dcsr_ena;
wire step_nxt;
wire step_r;
assign step_nxt = wr_csr_nxt[2];
sirv_gnrl_dfflr #(1) step_dfflr (step_ena, step_nxt, step_r, clk, rst_n);
//
// The ebreakm field
wire ebreakm_ena = wr_dcsr_ena;
wire ebreakm_nxt;
wire ebreakm_r;
assign ebreakm_nxt = wr_csr_nxt[15];
sirv_gnrl_dfflr #(1) ebreakm_dfflr (ebreakm_ena, ebreakm_nxt, ebreakm_r, clk, rst_n);
//
// // The stopcycle field
//wire stopcycle_ena = wr_dcsr_ena;
//wire stopcycle_nxt;
//wire stopcycle_r;
//assign stopcycle_nxt = wr_csr_nxt[10];
//sirv_gnrl_dfflr #(1) stopcycle_dfflr (stopcycle_ena, stopcycle_nxt, stopcycle_r, clk, rst_n);
// //
// // The stoptime field
//wire stoptime_ena = wr_dcsr_ena;
//wire stoptime_nxt;
//wire stoptime_r;
//assign stoptime_nxt = wr_csr_nxt[9];
//sirv_gnrl_dfflr #(1) stoptime_dfflr (stoptime_ena, stoptime_nxt, stoptime_r, clk, rst_n);
assign dbg_stopcycle = 1'b1;
assign dcsr_r [31:30] = 2'd1;
assign dcsr_r [29:16] = 14'b0;
assign dcsr_r [15:12] = {4{ebreakm_r}};// we replicated the ebreakm for all ebreakh/s/u
assign dcsr_r [11] = 1'b0;
assign dcsr_r [10] = dbg_stopcycle;// Not writeable this bit is constant
assign dcsr_r [9] = 1'b0;//stoptime_r; Not use this bit same as rocket implmementation
assign dcsr_r [8:6] = dcause_r;
assign dcsr_r [5] = dbg_irq_r;
assign dcsr_r [4] = 1'b0;
assign dcsr_r [3] = halt_r;
assign dcsr_r [2] = step_r;
assign dcsr_r [1:0] = 2'b11;
assign dbg_mode = ~(dcause_r == 3'b0);
assign dbg_halt_r = halt_r;
assign dbg_step_r = step_r;
assign dbg_ebreakm_r = ebreakm_r;
endmodule
|
module i2c_master_top(
wb_clk_i, wb_rst_i, arst_i, wb_adr_i, wb_dat_i, wb_dat_o,
wb_we_i, wb_stb_i, wb_cyc_i, wb_ack_o, wb_inta_o,
scl_pad_i, scl_pad_o, scl_padoen_o, sda_pad_i, sda_pad_o, sda_padoen_o );
// parameters
parameter ARST_LVL = 1'b0; // asynchronous reset level
//
// inputs & outputs
//
// wishbone signals
input wb_clk_i; // master clock input
input wb_rst_i; // synchronous active high reset
input arst_i; // asynchronous reset
input [2:0] wb_adr_i; // lower address bits
input [7:0] wb_dat_i; // databus input
output [7:0] wb_dat_o; // databus output
input wb_we_i; // write enable input
input wb_stb_i; // stobe/core select signal
input wb_cyc_i; // valid bus cycle input
output wb_ack_o; // bus cycle acknowledge output
output wb_inta_o; // interrupt request signal output
reg [7:0] wb_dat_o;
reg wb_ack_o;
reg wb_inta_o;
// I2C signals
// i2c clock line
input scl_pad_i; // SCL-line input
output scl_pad_o; // SCL-line output (always 1'b0)
output scl_padoen_o; // SCL-line output enable (active low)
// i2c data line
input sda_pad_i; // SDA-line input
output sda_pad_o; // SDA-line output (always 1'b0)
output sda_padoen_o; // SDA-line output enable (active low)
//
// variable declarations
//
// registers
reg [15:0] prer; // clock prescale register
reg [ 7:0] ctr; // control register
reg [ 7:0] txr; // transmit register
wire [ 7:0] rxr; // receive register
reg [ 7:0] cr; // command register
wire [ 7:0] sr; // status register
// done signal: command completed, clear command register
wire done;
// core enable signal
wire core_en;
wire ien;
// status register signals
wire irxack;
reg rxack; // received aknowledge from slave
reg tip; // transfer in progress
reg irq_flag; // interrupt pending flag
wire i2c_busy; // bus busy (start signal detected)
wire i2c_al; // i2c bus arbitration lost
reg al; // status register arbitration lost bit
//
// module body
//
// generate internal reset
wire rst_i = arst_i ^ ARST_LVL;
// generate wishbone signals
wire wb_wacc = wb_cyc_i & wb_stb_i & wb_we_i;
// generate acknowledge output signal
always @(posedge wb_clk_i or negedge rst_i)
//always @(posedge wb_clk_i)//Bob: Here the ack is X by default, so add the rst here
if (!rst_i)
wb_ack_o <= #1 1'b0;
else
wb_ack_o <= #1 wb_cyc_i & wb_stb_i & ~wb_ack_o; // because timing is always honored
// assign DAT_O
always @(posedge wb_clk_i)
begin
case (wb_adr_i) // synopsis parallel_case
3'b000: wb_dat_o <= #1 prer[ 7:0];
3'b001: wb_dat_o <= #1 prer[15:8];
3'b010: wb_dat_o <= #1 ctr;
3'b011: wb_dat_o <= #1 rxr; // write is transmit register (txr)
3'b100: wb_dat_o <= #1 sr; // write is command register (cr)
3'b101: wb_dat_o <= #1 txr;
3'b110: wb_dat_o <= #1 cr;
3'b111: wb_dat_o <= #1 0; // reserved
endcase
end
// generate registers
always @(posedge wb_clk_i or negedge rst_i)
if (!rst_i)
begin
prer <= #1 16'hffff;
ctr <= #1 8'h0;
txr <= #1 8'h0;
end
else if (wb_rst_i)
begin
prer <= #1 16'hffff;
ctr <= #1 8'h0;
txr <= #1 8'h0;
end
else
if (wb_wacc)
case (wb_adr_i) // synopsis parallel_case
3'b000 : prer [ 7:0] <= #1 wb_dat_i;
3'b001 : prer [15:8] <= #1 wb_dat_i;
3'b010 : ctr <= #1 wb_dat_i;
3'b011 : txr <= #1 wb_dat_i;
//default: ; //Bob: here have a lint warning, so commented it out
endcase
// generate command register (special case)
always @(posedge wb_clk_i or negedge rst_i)
if (~rst_i)
cr <= #1 8'h0;
else if (wb_rst_i)
cr <= #1 8'h0;
else if (wb_wacc)
begin
if (core_en & (wb_adr_i == 3'b100) )
cr <= #1 wb_dat_i;
end
else
begin
if (done | i2c_al)
cr[7:4] <= #1 4'h0; // clear command bits when done
// or when aribitration lost
cr[2:1] <= #1 2'b0; // reserved bits
cr[0] <= #1 2'b0; // clear IRQ_ACK bit
end
// decode command register
wire sta = cr[7];
wire sto = cr[6];
wire rd = cr[5];
wire wr = cr[4];
wire ack = cr[3];
wire iack = cr[0];
// decode control register
assign core_en = ctr[7];
assign ien = ctr[6];
// hookup byte controller block
i2c_master_byte_ctrl byte_controller (
.clk ( wb_clk_i ),
.rst ( wb_rst_i ),
.nReset ( rst_i ),
.ena ( core_en ),
.clk_cnt ( prer ),
.start ( sta ),
.stop ( sto ),
.read ( rd ),
.write ( wr ),
.ack_in ( ack ),
.din ( txr ),
.cmd_ack ( done ),
.ack_out ( irxack ),
.dout ( rxr ),
.i2c_busy ( i2c_busy ),
.i2c_al ( i2c_al ),
.scl_i ( scl_pad_i ),
.scl_o ( scl_pad_o ),
.scl_oen ( scl_padoen_o ),
.sda_i ( sda_pad_i ),
.sda_o ( sda_pad_o ),
.sda_oen ( sda_padoen_o )
);
// status register block + interrupt request signal
always @(posedge wb_clk_i or negedge rst_i)
if (!rst_i)
begin
al <= #1 1'b0;
rxack <= #1 1'b0;
tip <= #1 1'b0;
irq_flag <= #1 1'b0;
end
else if (wb_rst_i)
begin
al <= #1 1'b0;
rxack <= #1 1'b0;
tip <= #1 1'b0;
irq_flag <= #1 1'b0;
end
else
begin
al <= #1 i2c_al | (al & ~sta);
rxack <= #1 irxack;
tip <= #1 (rd | wr);
irq_flag <= #1 (done | i2c_al | irq_flag) & ~iack; // interrupt request flag is always generated
end
// generate interrupt request signals
always @(posedge wb_clk_i or negedge rst_i)
if (!rst_i)
wb_inta_o <= #1 1'b0;
else if (wb_rst_i)
wb_inta_o <= #1 1'b0;
else
wb_inta_o <= #1 irq_flag && ien; // interrupt signal is only generated when IEN (interrupt enable bit is set)
// assign status register bits
assign sr[7] = rxack;
assign sr[6] = i2c_busy;
assign sr[5] = al;
assign sr[4:2] = 3'h0; // reserved
assign sr[1] = tip;
assign sr[0] = irq_flag;
endmodule
|
module sirv_jtag_dtm (
//JTAG Interface
jtag_TDI,
jtag_TDO,
jtag_TCK,
jtag_TMS,
jtag_TRST,
jtag_DRV_TDO,
dtm_req_valid,
dtm_req_ready,
dtm_req_bits,
dtm_resp_valid,
dtm_resp_ready,
dtm_resp_bits
);
//--------------------------------------------------------
// Parameter Declarations
parameter ASYNC_FF_LEVELS = 2;
parameter DEBUG_DATA_BITS = 34;
parameter DEBUG_ADDR_BITS = 5; // Spec allows values are 5-7
parameter DEBUG_OP_BITS = 2; // OP and RESP are the same size.
parameter JTAG_VERSION = 4'h1;
parameter JTAG_PART_NUM = 16'h0E31; // E31
parameter JTAG_MANUF_ID = 11'h489; // As Assigned by JEDEC
// Number of cycles which must remain in IDLE
// The software should handle even if the
// answer is actually higher than this, or
// the software may choose to ignore it entirely
// and just check for busy.
parameter DBUS_IDLE_CYCLES = 3'h5;
localparam IR_BITS = 5;
localparam DEBUG_VERSION = 0;
// JTAG State Machine
localparam TEST_LOGIC_RESET = 4'h0;
localparam RUN_TEST_IDLE = 4'h1;
localparam SELECT_DR = 4'h2;
localparam CAPTURE_DR = 4'h3;
localparam SHIFT_DR = 4'h4;
localparam EXIT1_DR = 4'h5;
localparam PAUSE_DR = 4'h6;
localparam EXIT2_DR = 4'h7;
localparam UPDATE_DR = 4'h8;
localparam SELECT_IR = 4'h9;
localparam CAPTURE_IR = 4'hA;
localparam SHIFT_IR = 4'hB;
localparam EXIT1_IR = 4'hC;
localparam PAUSE_IR = 4'hD;
localparam EXIT2_IR = 4'hE;
localparam UPDATE_IR = 4'hF;
//RISCV DTM Registers (see RISC-V Debug Specification)
// All others are treated as 'BYPASS'.
localparam REG_BYPASS = 5'b11111;
localparam REG_IDCODE = 5'b00001;
localparam REG_DEBUG_ACCESS = 5'b10001;
localparam REG_DTM_INFO = 5'b10000;
localparam DBUS_REG_BITS = DEBUG_OP_BITS + DEBUG_ADDR_BITS + DEBUG_DATA_BITS;
localparam DBUS_REQ_BITS = DEBUG_OP_BITS + DEBUG_ADDR_BITS + DEBUG_DATA_BITS;
localparam DBUS_RESP_BITS = DEBUG_OP_BITS + DEBUG_DATA_BITS;
localparam SHIFT_REG_BITS = DBUS_REG_BITS;
//--------------------------------------------------------
// I/O Declarations
//JTAG SIDE
input jtag_TDI;
output reg jtag_TDO;
input jtag_TCK;
input jtag_TMS;
input jtag_TRST;
// To allow tri-state outside of this block.
output reg jtag_DRV_TDO;
// RISC-V Core Side
output dtm_req_valid;
input dtm_req_ready;
output [DBUS_REQ_BITS - 1 :0] dtm_req_bits;
input dtm_resp_valid;
output dtm_resp_ready;
input [DBUS_RESP_BITS - 1 : 0] dtm_resp_bits;
wire i_dtm_req_valid;
wire i_dtm_req_ready;
wire [DBUS_REQ_BITS - 1 :0] i_dtm_req_bits;
wire i_dtm_resp_valid;
wire i_dtm_resp_ready;
wire[DBUS_RESP_BITS - 1 : 0] i_dtm_resp_bits;
//--------------------------------------------------------
// Reg and Wire Declarations
reg [IR_BITS -1 : 0 ] irReg;
wire [31:0] idcode;
wire [31:0] dtminfo;
reg [DBUS_REG_BITS - 1 : 0] dbusReg;
reg dbusValidReg;
reg [3:0] jtagStateReg;
reg [SHIFT_REG_BITS -1 : 0] shiftReg;
reg doDbusWriteReg;
reg doDbusReadReg;
reg busyReg;
reg stickyBusyReg;
reg stickyNonzeroRespReg;
reg skipOpReg; // Skip op because we're busy.
reg downgradeOpReg; // Downgrade op because prev. op failed.
wire busy;
wire nonzeroResp;
wire [SHIFT_REG_BITS -1 : 0] busyResponse;
wire [SHIFT_REG_BITS -1 : 0] nonbusyResponse;
//--------------------------------------------------------
// Combo Logic
assign idcode = {JTAG_VERSION, JTAG_PART_NUM, JTAG_MANUF_ID, 1'h1};
wire [3:0] debugAddrBits = DEBUG_ADDR_BITS[3:0];
wire [3:0] debugVersion = DEBUG_VERSION[3:0];
wire [1:0] dbusStatus;
wire [2:0] dbusIdleCycles;
wire dbusReset;
assign dbusIdleCycles = DBUS_IDLE_CYCLES;
assign dbusStatus = {stickyNonzeroRespReg, stickyNonzeroRespReg | stickyBusyReg};
assign dbusReset = shiftReg[16];
assign dtminfo = {15'b0,
1'b0, // dbusreset goes here but is write-only
3'b0,
dbusIdleCycles,
dbusStatus,
debugAddrBits,
debugVersion};
//busy, dtm_resp* is only valid during CAPTURE_DR,
// so these signals should only be used at that time.
// This assumes there is only one transaction in flight at a time.
assign busy = (busyReg & ~i_dtm_resp_valid) | stickyBusyReg;
// This is needed especially for the first request.
assign nonzeroResp = (i_dtm_resp_valid ? | {i_dtm_resp_bits[DEBUG_OP_BITS-1:0]} : 1'b0) | stickyNonzeroRespReg;
// Interface to DM.
// Note that this means i_dtm_resp_bits must only be used during CAPTURE_DR.
assign i_dtm_resp_ready = (jtagStateReg == CAPTURE_DR) &&
(irReg == REG_DEBUG_ACCESS) &&
i_dtm_resp_valid;
assign i_dtm_req_valid = dbusValidReg;
assign i_dtm_req_bits = dbusReg;
assign busyResponse = {{(DEBUG_ADDR_BITS + DEBUG_DATA_BITS){1'b0}},
{(DEBUG_OP_BITS){1'b1}}}; // Generalizing 'busy' to 'all-1'
assign nonbusyResponse = {dbusReg[(DEBUG_DATA_BITS + DEBUG_OP_BITS) +: DEBUG_ADDR_BITS] , // retain address bits from Req.
i_dtm_resp_bits[DEBUG_OP_BITS +: DEBUG_DATA_BITS] , // data
i_dtm_resp_bits[0 +: DEBUG_OP_BITS] // response
};
//--------------------------------------------------------
// Sequential Logic
// JTAG STATE MACHINE
always @(posedge jtag_TCK or posedge jtag_TRST) begin
if (jtag_TRST) begin
jtagStateReg <= TEST_LOGIC_RESET;
end else begin
case (jtagStateReg)
TEST_LOGIC_RESET : jtagStateReg <= jtag_TMS ? TEST_LOGIC_RESET : RUN_TEST_IDLE;
RUN_TEST_IDLE : jtagStateReg <= jtag_TMS ? SELECT_DR : RUN_TEST_IDLE;
SELECT_DR : jtagStateReg <= jtag_TMS ? SELECT_IR : CAPTURE_DR;
CAPTURE_DR : jtagStateReg <= jtag_TMS ? EXIT1_DR : SHIFT_DR;
SHIFT_DR : jtagStateReg <= jtag_TMS ? EXIT1_DR : SHIFT_DR;
EXIT1_DR : jtagStateReg <= jtag_TMS ? UPDATE_DR : PAUSE_DR;
PAUSE_DR : jtagStateReg <= jtag_TMS ? EXIT2_DR : PAUSE_DR;
EXIT2_DR : jtagStateReg <= jtag_TMS ? UPDATE_DR : SHIFT_DR;
UPDATE_DR : jtagStateReg <= jtag_TMS ? SELECT_DR : RUN_TEST_IDLE;
SELECT_IR : jtagStateReg <= jtag_TMS ? TEST_LOGIC_RESET : CAPTURE_IR;
CAPTURE_IR : jtagStateReg <= jtag_TMS ? EXIT1_IR : SHIFT_IR;
SHIFT_IR : jtagStateReg <= jtag_TMS ? EXIT1_IR : SHIFT_IR;
EXIT1_IR : jtagStateReg <= jtag_TMS ? UPDATE_IR : PAUSE_IR;
PAUSE_IR : jtagStateReg <= jtag_TMS ? EXIT2_IR : PAUSE_IR;
EXIT2_IR : jtagStateReg <= jtag_TMS ? UPDATE_IR : SHIFT_IR;
UPDATE_IR : jtagStateReg <= jtag_TMS ? SELECT_DR : RUN_TEST_IDLE;
endcase // case (jtagStateReg)
end // else: !if(jtag_TRST)
end // always @ (posedge jtag_TCK or posedge jtag_TRST)
// SHIFT REG
always @(posedge jtag_TCK) begin
case (jtagStateReg)
CAPTURE_IR : shiftReg <= {{(SHIFT_REG_BITS-1){1'b0}}, 1'b1}; //JTAG spec only says must end with 'b01.
SHIFT_IR : shiftReg <= {{(SHIFT_REG_BITS-IR_BITS){1'b0}}, jtag_TDI, shiftReg[IR_BITS-1 : 1]};
CAPTURE_DR : case (irReg)
REG_BYPASS : shiftReg <= {(SHIFT_REG_BITS){1'b0}};
REG_IDCODE : shiftReg <= {{(SHIFT_REG_BITS-32){1'b0}}, idcode};
REG_DTM_INFO : shiftReg <= {{(SHIFT_REG_BITS-32){1'b0}}, dtminfo};
REG_DEBUG_ACCESS : shiftReg <= busy ? busyResponse : nonbusyResponse;
default : //BYPASS
shiftReg <= {(SHIFT_REG_BITS){1'b0}};
endcase
SHIFT_DR : case (irReg)
REG_BYPASS : shiftReg <= {{(SHIFT_REG_BITS- 1){1'b0}}, jtag_TDI};
REG_IDCODE : shiftReg <= {{(SHIFT_REG_BITS-32){1'b0}}, jtag_TDI, shiftReg[31:1]};
REG_DTM_INFO : shiftReg <= {{(SHIFT_REG_BITS-32){1'b0}}, jtag_TDI, shiftReg[31:1]};
REG_DEBUG_ACCESS : shiftReg <= {jtag_TDI, shiftReg[SHIFT_REG_BITS -1 : 1 ]};
default: // BYPASS
shiftReg <= {{(SHIFT_REG_BITS- 1){1'b0}} , jtag_TDI};
endcase // case (irReg)
endcase // case (jtagStateReg)
end
// IR
always @(negedge jtag_TCK or posedge jtag_TRST) begin
if (jtag_TRST) begin
irReg <= REG_IDCODE;
end else if (jtagStateReg == TEST_LOGIC_RESET) begin
irReg <= REG_IDCODE;
end else if (jtagStateReg == UPDATE_IR) begin
irReg <= shiftReg[IR_BITS-1:0];
end
end
// Busy. We become busy when we first try to send a request.
// We stop being busy when we accept a response.
// This means that busyReg will still be set when we check it,
// so the logic for checking busy looks ahead.
always @(posedge jtag_TCK or posedge jtag_TRST) begin
if (jtag_TRST) begin
busyReg <= 1'b0;
end else if (i_dtm_req_valid) begin //UPDATE_DR onwards
busyReg <= 1'b1;
end else if (i_dtm_resp_valid & i_dtm_resp_ready) begin //only in CAPTURE_DR
busyReg <= 1'b0;
end
end // always @ (posedge jtag_TCK or posedge jtag_TRST)
// Downgrade/Skip. We make the decision to downgrade or skip
// during every CAPTURE_DR, and use the result in UPDATE_DR.
always @(posedge jtag_TCK or posedge jtag_TRST) begin
if (jtag_TRST) begin
skipOpReg <= 1'b0;
downgradeOpReg <= 1'b0;
stickyBusyReg <= 1'b0;
stickyNonzeroRespReg <= 1'b0;
end else if (irReg == REG_DEBUG_ACCESS) begin
case(jtagStateReg)
CAPTURE_DR: begin
skipOpReg <= busy;
downgradeOpReg <= (~busy & nonzeroResp);
stickyBusyReg <= busy;
stickyNonzeroRespReg <= nonzeroResp;
end
UPDATE_DR: begin
skipOpReg <= 1'b0;
downgradeOpReg <= 1'b0;
end
endcase // case (jtagStateReg)
end else if (irReg == REG_DTM_INFO) begin
case(jtagStateReg)
UPDATE_DR: begin
if (dbusReset) begin
stickyNonzeroRespReg <= 1'b0;
stickyBusyReg <= 1'b0;
end
end
endcase // case (jtagStateReg)
end
end // always @ (posedge jtag_TCK or posedge jtag_TRST)
//dbusReg, dbusValidReg.
always @(posedge jtag_TCK or posedge jtag_TRST) begin
if (jtag_TRST) begin
dbusReg <= {(DBUS_REG_BITS) {1'b0}};
dbusValidReg <= 1'b0;
end else if (jtagStateReg == UPDATE_DR) begin
if (irReg == REG_DEBUG_ACCESS) begin
if (skipOpReg) begin
// do nothing.
end else if (downgradeOpReg) begin
dbusReg <= {(DBUS_REG_BITS){1'b0}}; // NOP has encoding 2'b00.
dbusValidReg <= 1'b1;
end else begin
dbusReg <= shiftReg[DBUS_REG_BITS-1:0];
dbusValidReg <= 1'b1;
end
end
end else if (i_dtm_req_ready) begin
dbusValidReg <= 1'b0;
end
end // always @ (negedge jtag_TCK or posedge jtag_TRST)
//TDO
always @(negedge jtag_TCK or posedge jtag_TRST) begin
if (jtag_TRST) begin
jtag_TDO <= 1'b0;
jtag_DRV_TDO <= 1'b0;
end else if (jtagStateReg == SHIFT_IR) begin
jtag_TDO <= shiftReg[0];
jtag_DRV_TDO <= 1'b1;
end else if (jtagStateReg == SHIFT_DR) begin
jtag_TDO <= shiftReg[0];
jtag_DRV_TDO <= 1'b1;
end else begin
jtag_TDO <= 1'b0;
jtag_DRV_TDO <= 1'b0;
end
end // always @ (negedge jtag_TCK or posedge jtag_TRST)
sirv_gnrl_cdc_tx
# (
.DW (41),
.SYNC_DP (ASYNC_FF_LEVELS)
) u_jtag2debug_cdc_tx (
.o_vld (dtm_req_valid),
.o_rdy_a(dtm_req_ready),
.o_dat (dtm_req_bits ),
.i_vld (i_dtm_req_valid),
.i_rdy (i_dtm_req_ready),
.i_dat (i_dtm_req_bits ),
.clk (jtag_TCK),
.rst_n (~jtag_TRST)
);
sirv_gnrl_cdc_rx
# (
.DW (36),
.SYNC_DP (ASYNC_FF_LEVELS)
) u_jtag2debug_cdc_rx (
.i_vld_a(dtm_resp_valid),
.i_rdy (dtm_resp_ready),
.i_dat (dtm_resp_bits ),
.o_vld (i_dtm_resp_valid),
.o_rdy (i_dtm_resp_ready),
.o_dat (i_dtm_resp_bits ),
.clk (jtag_TCK),
.rst_n (~jtag_TRST)
);
endmodule
|
module sirv_spigpioport(
input clock,
input reset,
input io_spi_sck,
output io_spi_dq_0_i,
input io_spi_dq_0_o,
input io_spi_dq_0_oe,
output io_spi_dq_1_i,
input io_spi_dq_1_o,
input io_spi_dq_1_oe,
output io_spi_dq_2_i,
input io_spi_dq_2_o,
input io_spi_dq_2_oe,
output io_spi_dq_3_i,
input io_spi_dq_3_o,
input io_spi_dq_3_oe,
input io_spi_cs_0,
input io_spi_cs_1,
input io_spi_cs_2,
input io_spi_cs_3,
input io_pins_sck_i_ival,
output io_pins_sck_o_oval,
output io_pins_sck_o_oe,
output io_pins_sck_o_ie,
output io_pins_sck_o_pue,
output io_pins_sck_o_ds,
input io_pins_dq_0_i_ival,
output io_pins_dq_0_o_oval,
output io_pins_dq_0_o_oe,
output io_pins_dq_0_o_ie,
output io_pins_dq_0_o_pue,
output io_pins_dq_0_o_ds,
input io_pins_dq_1_i_ival,
output io_pins_dq_1_o_oval,
output io_pins_dq_1_o_oe,
output io_pins_dq_1_o_ie,
output io_pins_dq_1_o_pue,
output io_pins_dq_1_o_ds,
input io_pins_dq_2_i_ival,
output io_pins_dq_2_o_oval,
output io_pins_dq_2_o_oe,
output io_pins_dq_2_o_ie,
output io_pins_dq_2_o_pue,
output io_pins_dq_2_o_ds,
input io_pins_dq_3_i_ival,
output io_pins_dq_3_o_oval,
output io_pins_dq_3_o_oe,
output io_pins_dq_3_o_ie,
output io_pins_dq_3_o_pue,
output io_pins_dq_3_o_ds,
input io_pins_cs_0_i_ival,
output io_pins_cs_0_o_oval,
output io_pins_cs_0_o_oe,
output io_pins_cs_0_o_ie,
output io_pins_cs_0_o_pue,
output io_pins_cs_0_o_ds,
input io_pins_cs_1_i_ival,
output io_pins_cs_1_o_oval,
output io_pins_cs_1_o_oe,
output io_pins_cs_1_o_ie,
output io_pins_cs_1_o_pue,
output io_pins_cs_1_o_ds,
input io_pins_cs_2_i_ival,
output io_pins_cs_2_o_oval,
output io_pins_cs_2_o_oe,
output io_pins_cs_2_o_ie,
output io_pins_cs_2_o_pue,
output io_pins_cs_2_o_ds,
input io_pins_cs_3_i_ival,
output io_pins_cs_3_o_oval,
output io_pins_cs_3_o_oe,
output io_pins_cs_3_o_ie,
output io_pins_cs_3_o_pue,
output io_pins_cs_3_o_ds
);
wire T_312;
wire T_315;
wire T_318;
wire T_321;
wire [1:0] T_324;
wire [1:0] T_325;
wire [3:0] T_326;
wire T_330;
wire T_331;
wire T_332;
wire T_333;
assign io_spi_dq_0_i = io_pins_dq_0_i_ival;
assign io_spi_dq_1_i = io_pins_dq_1_i_ival;
assign io_spi_dq_2_i = io_pins_dq_2_i_ival;
assign io_spi_dq_3_i = io_pins_dq_3_i_ival;
assign io_pins_sck_o_oval = io_spi_sck;
assign io_pins_sck_o_oe = 1'h1;
assign io_pins_sck_o_ie = 1'h0;
assign io_pins_sck_o_pue = 1'h0;
assign io_pins_sck_o_ds = 1'h0;
assign io_pins_dq_0_o_oval = io_spi_dq_0_o;
assign io_pins_dq_0_o_oe = io_spi_dq_0_oe;
assign io_pins_dq_0_o_ie = T_312;
assign io_pins_dq_0_o_pue = 1'h1;
assign io_pins_dq_0_o_ds = 1'h0;
assign io_pins_dq_1_o_oval = io_spi_dq_1_o;
assign io_pins_dq_1_o_oe = io_spi_dq_1_oe;
assign io_pins_dq_1_o_ie = T_315;
assign io_pins_dq_1_o_pue = 1'h1;
assign io_pins_dq_1_o_ds = 1'h0;
assign io_pins_dq_2_o_oval = io_spi_dq_2_o;
assign io_pins_dq_2_o_oe = io_spi_dq_2_oe;
assign io_pins_dq_2_o_ie = T_318;
assign io_pins_dq_2_o_pue = 1'h1;
assign io_pins_dq_2_o_ds = 1'h0;
assign io_pins_dq_3_o_oval = io_spi_dq_3_o;
assign io_pins_dq_3_o_oe = io_spi_dq_3_oe;
assign io_pins_dq_3_o_ie = T_321;
assign io_pins_dq_3_o_pue = 1'h1;
assign io_pins_dq_3_o_ds = 1'h0;
assign io_pins_cs_0_o_oval = T_330;
assign io_pins_cs_0_o_oe = 1'h1;
assign io_pins_cs_0_o_ie = 1'h0;
assign io_pins_cs_0_o_pue = 1'h0;
assign io_pins_cs_0_o_ds = 1'h0;
assign io_pins_cs_1_o_oval = T_331;
assign io_pins_cs_1_o_oe = 1'h1;
assign io_pins_cs_1_o_ie = 1'h0;
assign io_pins_cs_1_o_pue = 1'h0;
assign io_pins_cs_1_o_ds = 1'h0;
assign io_pins_cs_2_o_oval = T_332;
assign io_pins_cs_2_o_oe = 1'h1;
assign io_pins_cs_2_o_ie = 1'h0;
assign io_pins_cs_2_o_pue = 1'h0;
assign io_pins_cs_2_o_ds = 1'h0;
assign io_pins_cs_3_o_oval = T_333;
assign io_pins_cs_3_o_oe = 1'h1;
assign io_pins_cs_3_o_ie = 1'h0;
assign io_pins_cs_3_o_pue = 1'h0;
assign io_pins_cs_3_o_ds = 1'h0;
assign T_312 = ~ io_spi_dq_0_oe;
assign T_315 = ~ io_spi_dq_1_oe;
assign T_318 = ~ io_spi_dq_2_oe;
assign T_321 = ~ io_spi_dq_3_oe;
assign T_324 = {io_spi_cs_1,io_spi_cs_0};
assign T_325 = {io_spi_cs_3,io_spi_cs_2};
assign T_326 = {T_325,T_324};
assign T_330 = T_326[0];
assign T_331 = T_326[1];
assign T_332 = T_326[2];
assign T_333 = T_326[3];
endmodule
|
module e203_exu_csr(
input nonflush_cmt_ena,
output eai_xs_off,
input csr_ena,
input csr_wr_en,
input csr_rd_en,
input [12-1:0] csr_idx,
output csr_access_ilgl,
output tm_stop,
output core_cgstop,
output tcm_cgstop,
output itcm_nohold,
output mdv_nob2b,
output [`E203_XLEN-1:0] read_csr_dat,
input [`E203_XLEN-1:0] wbck_csr_dat,
input [`E203_HART_ID_W-1:0] core_mhartid,
input ext_irq_r,
input sft_irq_r,
input tmr_irq_r,
output status_mie_r,
output mtie_r,
output msie_r,
output meie_r,
output wr_dcsr_ena ,
output wr_dpc_ena ,
output wr_dscratch_ena,
input [`E203_XLEN-1:0] dcsr_r ,
input [`E203_PC_SIZE-1:0] dpc_r ,
input [`E203_XLEN-1:0] dscratch_r,
output [`E203_XLEN-1:0] wr_csr_nxt ,
input dbg_mode,
input dbg_stopcycle,
output u_mode,
output s_mode,
output h_mode,
output m_mode,
input [`E203_ADDR_SIZE-1:0] cmt_badaddr,
input cmt_badaddr_ena,
input [`E203_PC_SIZE-1:0] cmt_epc,
input cmt_epc_ena,
input [`E203_XLEN-1:0] cmt_cause,
input cmt_cause_ena,
input cmt_status_ena,
input cmt_instret_ena,
input cmt_mret_ena,
output[`E203_PC_SIZE-1:0] csr_epc_r,
output[`E203_PC_SIZE-1:0] csr_dpc_r,
output[`E203_XLEN-1:0] csr_mtvec_r,
input clk_aon,
input clk,
input rst_n
);
assign csr_access_ilgl = 1'b0
;
// Only toggle when need to read or write to save power
wire wbck_csr_wen = csr_wr_en & csr_ena & (~csr_access_ilgl);
wire read_csr_ena = csr_rd_en & csr_ena & (~csr_access_ilgl);
wire [1:0] priv_mode = u_mode ? 2'b00 :
s_mode ? 2'b01 :
h_mode ? 2'b10 :
m_mode ? 2'b11 :
2'b11;
//0x000 URW ustatus User status register.
// * Since we support the user-level interrupt, hence we need to support UIE
//0x300 MRW mstatus Machine status register.
wire sel_ustatus = (csr_idx == 12'h000);
wire sel_mstatus = (csr_idx == 12'h300);
wire rd_ustatus = sel_ustatus & csr_rd_en;
wire rd_mstatus = sel_mstatus & csr_rd_en;
wire wr_ustatus = sel_ustatus & csr_wr_en;
wire wr_mstatus = sel_mstatus & csr_wr_en;
/////////////////////////////////////////////////////////////////////
// Note: the below implementation only apply to Machine-mode config,
// if other mode is also supported, these logics need to be updated
//////////////////////////
// Implement MPIE field
//
wire status_mpie_r;
// The MPIE Feilds will be updates when:
wire status_mpie_ena =
// The CSR is written by CSR instructions
(wr_mstatus & wbck_csr_wen) |
// The MRET instruction commited
cmt_mret_ena |
// The Trap is taken
cmt_status_ena;
wire status_mpie_nxt =
// See Priv SPEC:
// When a trap is taken from privilege mode y into privilege
// mode x, xPIE is set to the value of xIE;
// So, When the Trap is taken, the MPIE is updated with the current MIE value
cmt_status_ena ? status_mie_r :
// See Priv SPEC:
// When executing an xRET instruction, supposing xPP holds the value y, xIE
// is set to xPIE; the privilege mode is changed to y;
// xPIE is set to 1;
// So, When the MRET instruction commited, the MPIE is updated with 1
cmt_mret_ena ? 1'b1 :
// When the CSR is written by CSR instructions
(wr_mstatus & wbck_csr_wen) ? wbck_csr_dat[7] : // MPIE is in field 7 of mstatus
status_mpie_r; // Unchanged
sirv_gnrl_dfflr #(1) status_mpie_dfflr (status_mpie_ena, status_mpie_nxt, status_mpie_r, clk, rst_n);
//////////////////////////
// Implement MIE field
//
// The MIE Feilds will be updates same as MPIE
wire status_mie_ena = status_mpie_ena;
wire status_mie_nxt =
// See Priv SPEC:
// When a trap is taken from privilege mode y into privilege
// mode x, xPIE is set to the value of xIE,
// xIE is set to 0;
// So, When the Trap is taken, the MIE is updated with 0
cmt_status_ena ? 1'b0 :
// See Priv SPEC:
// When executing an xRET instruction, supposing xPP holds the value y, xIE
// is set to xPIE; the privilege mode is changed to y, xPIE is set to 1;
// So, When the MRET instruction commited, the MIE is updated with MPIE
cmt_mret_ena ? status_mpie_r :
// When the CSR is written by CSR instructions
(wr_mstatus & wbck_csr_wen) ? wbck_csr_dat[3] : // MIE is in field 3 of mstatus
status_mie_r; // Unchanged
sirv_gnrl_dfflr #(1) status_mie_dfflr (status_mie_ena, status_mie_nxt, status_mie_r, clk, rst_n);
//////////////////////////
// Implement SD field
//
// See Priv SPEC:
// The SD bit is read-only
// And is set when either the FS or XS bits encode a Dirty
// state (i.e., SD=((FS==11) OR (XS==11))).
wire [1:0] status_fs_r;
wire [1:0] status_xs_r;
wire status_sd_r = (status_fs_r == 2'b11) | (status_xs_r == 2'b11);
//////////////////////////
// Implement XS field
//
// See Priv SPEC:
// XS field is read-only
// The XS field represents a summary of all extensions' status
// But in E200 we implement XS exactly same as FS to make it usable by software to
// disable extended accelerators
`ifndef E203_HAS_EAI
// If no EAI coprocessor interface configured, the XS is just hardwired to 0
assign status_xs_r = 2'b0;
assign eai_xs_off = 1'b0;// We just make this signal to 0
`endif
//////////////////////////
// Implement FS field
//
`ifndef E203_HAS_FPU
// If no FPU configured, the FS is just hardwired to 0
assign status_fs_r = 2'b0;
`endif
//////////////////////////
// Pack to the full mstatus register
//
wire [`E203_XLEN-1:0] status_r;
assign status_r[31] = status_sd_r; //SD
assign status_r[30:23] = 8'b0; // Reserved
assign status_r[22:17] = 6'b0; // TSR--MPRV
assign status_r[16:15] = status_xs_r; // XS
assign status_r[14:13] = status_fs_r; // FS
assign status_r[12:11] = 2'b11; // MPP
assign status_r[10:9] = 2'b0; // Reserved
assign status_r[8] = 1'b0; // SPP
assign status_r[7] = status_mpie_r; // MPIE
assign status_r[6] = 1'b0; // Reserved
assign status_r[5] = 1'b0; // SPIE
assign status_r[4] = 1'b0; // UPIE
assign status_r[3] = status_mie_r; // MIE
assign status_r[2] = 1'b0; // Reserved
assign status_r[1] = 1'b0; // SIE
assign status_r[0] = 1'b0; // UIE
wire [`E203_XLEN-1:0] csr_mstatus = status_r;
//0x004 URW uie User interrupt-enable register.
// * Since we dont delegate interrupt to user mode, hence it is as all 0s
//0x304 MRW mie Machine interrupt-enable register.
wire sel_mie = (csr_idx == 12'h304);
wire rd_mie = sel_mie & csr_rd_en;
wire wr_mie = sel_mie & csr_wr_en;
wire mie_ena = wr_mie & wbck_csr_wen;
wire [`E203_XLEN-1:0] mie_r;
wire [`E203_XLEN-1:0] mie_nxt;
assign mie_nxt[31:12] = 20'b0;
assign mie_nxt[11] = wbck_csr_dat[11];//MEIE
assign mie_nxt[10:8] = 3'b0;
assign mie_nxt[ 7] = wbck_csr_dat[ 7];//MTIE
assign mie_nxt[6:4] = 3'b0;
assign mie_nxt[ 3] = wbck_csr_dat[ 3];//MSIE
assign mie_nxt[2:0] = 3'b0;
sirv_gnrl_dfflr #(`E203_XLEN) mie_dfflr (mie_ena, mie_nxt, mie_r, clk, rst_n);
wire [`E203_XLEN-1:0] csr_mie = mie_r;
assign meie_r = csr_mie[11];
assign mtie_r = csr_mie[ 7];
assign msie_r = csr_mie[ 3];
//0x044 URW uip User interrupt pending.
// We dont support delegation scheme, so no need to support the uip
//0x344 MRW mip Machine interrupt pending
wire sel_mip = (csr_idx == 12'h344);
wire rd_mip = sel_mip & csr_rd_en;
//wire wr_mip = sel_mip & csr_wr_en;
// The MxIP is read-only
wire meip_r;
wire msip_r;
wire mtip_r;
sirv_gnrl_dffr #(1) meip_dffr (ext_irq_r, meip_r, clk, rst_n);
sirv_gnrl_dffr #(1) msip_dffr (sft_irq_r, msip_r, clk, rst_n);
sirv_gnrl_dffr #(1) mtip_dffr (tmr_irq_r, mtip_r, clk, rst_n);
wire [`E203_XLEN-1:0] ip_r;
assign ip_r[31:12] = 20'b0;
assign ip_r[11] = meip_r;
assign ip_r[10:8] = 3'b0;
assign ip_r[ 7] = mtip_r;
assign ip_r[6:4] = 3'b0;
assign ip_r[ 3] = msip_r;
assign ip_r[2:0] = 3'b0;
wire [`E203_XLEN-1:0] csr_mip = ip_r;
//
//0x005 URW utvec User trap handler base address.
// We dont support user trap, so no utvec needed
//0x305 MRW mtvec Machine trap-handler base address.
wire sel_mtvec = (csr_idx == 12'h305);
wire rd_mtvec = csr_rd_en & sel_mtvec;
`ifdef E203_SUPPORT_MTVEC //{
wire wr_mtvec = sel_mtvec & csr_wr_en;
wire mtvec_ena = (wr_mtvec & wbck_csr_wen);
wire [`E203_XLEN-1:0] mtvec_r;
wire [`E203_XLEN-1:0] mtvec_nxt = wbck_csr_dat;
sirv_gnrl_dfflr #(`E203_XLEN) mtvec_dfflr (mtvec_ena, mtvec_nxt, mtvec_r, clk, rst_n);
wire [`E203_XLEN-1:0] csr_mtvec = mtvec_r;
`else//}{
// THe vector table base is a configurable parameter, so we dont support writeable to it
wire [`E203_XLEN-1:0] csr_mtvec = `E203_MTVEC_TRAP_BASE;
`endif//}
assign csr_mtvec_r = csr_mtvec;
//0x340 MRW mscratch
wire sel_mscratch = (csr_idx == 12'h340);
wire rd_mscratch = sel_mscratch & csr_rd_en;
`ifdef E203_SUPPORT_MSCRATCH //{
wire wr_mscratch = sel_mscratch & csr_wr_en;
wire mscratch_ena = (wr_mscratch & wbck_csr_wen);
wire [`E203_XLEN-1:0] mscratch_r;
wire [`E203_XLEN-1:0] mscratch_nxt = wbck_csr_dat;
sirv_gnrl_dfflr #(`E203_XLEN) mscratch_dfflr (mscratch_ena, mscratch_nxt, mscratch_r, clk, rst_n);
wire [`E203_XLEN-1:0] csr_mscratch = mscratch_r;
`else//}{
wire [`E203_XLEN-1:0] csr_mscratch = `E203_XLEN'b0;
`endif//}
// 0xB00 MRW mcycle
// 0xB02 MRW minstret
// 0xB80 MRW mcycleh
// 0xB82 MRW minstreth
wire sel_mcycle = (csr_idx == 12'hB00);
wire sel_mcycleh = (csr_idx == 12'hB80);
wire sel_minstret = (csr_idx == 12'hB02);
wire sel_minstreth = (csr_idx == 12'hB82);
// 0xBFF MRW counterstop
// This register is our self-defined register to stop
// the cycle/time/instret counters to save dynamic powers
wire sel_counterstop = (csr_idx == 12'hBFF);// This address is not used by ISA
// 0xBFE MRW mcgstop
// This register is our self-defined register to disable the
// automaticall clock gating for CPU logics for debugging purpose
wire sel_mcgstop = (csr_idx == 12'hBFE);// This address is not used by ISA
// 0xBFD MRW itcmnohold
// This register is our self-defined register to disble the
// ITCM SRAM output holdup feature, if set, then we assume
// ITCM SRAM output cannot holdup last read value
wire sel_itcmnohold = (csr_idx == 12'hBFD);// This address is not used by ISA
// 0xBF0 MRW mdvnob2b
// This register is our self-defined register to disble the
// Mul/div back2back feature
wire sel_mdvnob2b = (csr_idx == 12'hBF0);// This address is not used by ISA
wire rd_mcycle = csr_rd_en & sel_mcycle ;
wire rd_mcycleh = csr_rd_en & sel_mcycleh ;
wire rd_minstret = csr_rd_en & sel_minstret ;
wire rd_minstreth = csr_rd_en & sel_minstreth;
wire rd_itcmnohold = csr_rd_en & sel_itcmnohold;
wire rd_mdvnob2b = csr_rd_en & sel_mdvnob2b;
wire rd_counterstop = csr_rd_en & sel_counterstop;
wire rd_mcgstop = csr_rd_en & sel_mcgstop;
`ifdef E203_SUPPORT_MCYCLE_MINSTRET //{
wire wr_mcycle = csr_wr_en & sel_mcycle ;
wire wr_mcycleh = csr_wr_en & sel_mcycleh ;
wire wr_minstret = csr_wr_en & sel_minstret ;
wire wr_minstreth = csr_wr_en & sel_minstreth;
wire wr_itcmnohold = csr_wr_en & sel_itcmnohold ;
wire wr_mdvnob2b = csr_wr_en & sel_mdvnob2b ;
wire wr_counterstop = csr_wr_en & sel_counterstop;
wire wr_mcgstop = csr_wr_en & sel_mcgstop ;
wire mcycle_wr_ena = (wr_mcycle & wbck_csr_wen);
wire mcycleh_wr_ena = (wr_mcycleh & wbck_csr_wen);
wire minstret_wr_ena = (wr_minstret & wbck_csr_wen);
wire minstreth_wr_ena = (wr_minstreth & wbck_csr_wen);
wire itcmnohold_wr_ena = (wr_itcmnohold & wbck_csr_wen);
wire mdvnob2b_wr_ena = (wr_mdvnob2b & wbck_csr_wen);
wire counterstop_wr_ena = (wr_counterstop & wbck_csr_wen);
wire mcgstop_wr_ena = (wr_mcgstop & wbck_csr_wen);
wire [`E203_XLEN-1:0] mcycle_r ;
wire [`E203_XLEN-1:0] mcycleh_r ;
wire [`E203_XLEN-1:0] minstret_r ;
wire [`E203_XLEN-1:0] minstreth_r;
wire cy_stop;
wire ir_stop;
wire stop_cycle_in_dbg = dbg_stopcycle & dbg_mode;
wire mcycle_ena = mcycle_wr_ena |
((~cy_stop) & (~stop_cycle_in_dbg) & (1'b1));
wire mcycleh_ena = mcycleh_wr_ena |
((~cy_stop) & (~stop_cycle_in_dbg) & ((mcycle_r == (~(`E203_XLEN'b0)))));
wire minstret_ena = minstret_wr_ena |
((~ir_stop) & (~stop_cycle_in_dbg) & (cmt_instret_ena));
wire minstreth_ena = minstreth_wr_ena |
((~ir_stop) & (~stop_cycle_in_dbg) & ((cmt_instret_ena & (minstret_r == (~(`E203_XLEN'b0))))));
wire [`E203_XLEN-1:0] mcycle_nxt = mcycle_wr_ena ? wbck_csr_dat : (mcycle_r + 1'b1);
wire [`E203_XLEN-1:0] mcycleh_nxt = mcycleh_wr_ena ? wbck_csr_dat : (mcycleh_r + 1'b1);
wire [`E203_XLEN-1:0] minstret_nxt = minstret_wr_ena ? wbck_csr_dat : (minstret_r + 1'b1);
wire [`E203_XLEN-1:0] minstreth_nxt = minstreth_wr_ena ? wbck_csr_dat : (minstreth_r + 1'b1);
//We need to use the always-on clock for this counter
sirv_gnrl_dfflr #(`E203_XLEN) mcycle_dfflr (mcycle_ena, mcycle_nxt, mcycle_r , clk_aon, rst_n);
sirv_gnrl_dfflr #(`E203_XLEN) mcycleh_dfflr (mcycleh_ena, mcycleh_nxt, mcycleh_r , clk_aon, rst_n);
sirv_gnrl_dfflr #(`E203_XLEN) minstret_dfflr (minstret_ena, minstret_nxt, minstret_r , clk, rst_n);
sirv_gnrl_dfflr #(`E203_XLEN) minstreth_dfflr (minstreth_ena, minstreth_nxt, minstreth_r, clk, rst_n);
wire [`E203_XLEN-1:0] counterstop_r;
wire counterstop_ena = counterstop_wr_ena;
wire [`E203_XLEN-1:0] counterstop_nxt = {29'b0,wbck_csr_dat[2:0]};// Only LSB 3bits are useful
sirv_gnrl_dfflr #(`E203_XLEN) counterstop_dfflr (counterstop_ena, counterstop_nxt, counterstop_r, clk, rst_n);
wire [`E203_XLEN-1:0] csr_mcycle = mcycle_r;
wire [`E203_XLEN-1:0] csr_mcycleh = mcycleh_r;
wire [`E203_XLEN-1:0] csr_minstret = minstret_r;
wire [`E203_XLEN-1:0] csr_minstreth = minstreth_r;
wire [`E203_XLEN-1:0] csr_counterstop = counterstop_r;
`else//}{
wire [`E203_XLEN-1:0] csr_mcycle = `E203_XLEN'b0;
wire [`E203_XLEN-1:0] csr_mcycleh = `E203_XLEN'b0;
wire [`E203_XLEN-1:0] csr_minstret = `E203_XLEN'b0;
wire [`E203_XLEN-1:0] csr_minstreth = `E203_XLEN'b0;
wire [`E203_XLEN-1:0] csr_counterstop = `E203_XLEN'b0;
`endif//}
wire [`E203_XLEN-1:0] itcmnohold_r;
wire itcmnohold_ena = itcmnohold_wr_ena;
wire [`E203_XLEN-1:0] itcmnohold_nxt = {31'b0,wbck_csr_dat[0]};// Only LSB 1bits are useful
sirv_gnrl_dfflr #(`E203_XLEN) itcmnohold_dfflr (itcmnohold_ena, itcmnohold_nxt, itcmnohold_r, clk, rst_n);
wire [`E203_XLEN-1:0] csr_itcmnohold = itcmnohold_r;
wire [`E203_XLEN-1:0] mdvnob2b_r;
wire mdvnob2b_ena = mdvnob2b_wr_ena;
wire [`E203_XLEN-1:0] mdvnob2b_nxt = {31'b0,wbck_csr_dat[0]};// Only LSB 1bits are useful
sirv_gnrl_dfflr #(`E203_XLEN) mdvnob2b_dfflr (mdvnob2b_ena, mdvnob2b_nxt, mdvnob2b_r, clk, rst_n);
wire [`E203_XLEN-1:0] csr_mdvnob2b = mdvnob2b_r;
assign cy_stop = counterstop_r[0];// Stop CYCLE counter
assign tm_stop = counterstop_r[1];// Stop TIME counter
assign ir_stop = counterstop_r[2];// Stop INSTRET counter
assign itcm_nohold = itcmnohold_r[0];// ITCM no-hold up feature
assign mdv_nob2b = mdvnob2b_r[0];// Mul/Div no back2back feature
wire [`E203_XLEN-1:0] mcgstop_r;
wire mcgstop_ena = mcgstop_wr_ena;
wire [`E203_XLEN-1:0] mcgstop_nxt = {30'b0,wbck_csr_dat[1:0]};// Only LSB 2bits are useful
sirv_gnrl_dfflr #(`E203_XLEN) mcgstop_dfflr (mcgstop_ena, mcgstop_nxt, mcgstop_r, clk, rst_n);
wire [`E203_XLEN-1:0] csr_mcgstop = mcgstop_r;
assign core_cgstop = mcgstop_r[0];// Stop Core clock gating
assign tcm_cgstop = mcgstop_r[1];// Stop TCM clock gating
//`ifdef E203_SUPPORT_CYCLE //{
////0xC00 URO cycle
////0xC80 URO cycleh
//wire sel_cycle = (csr_idx == 12'hc00);
//wire sel_cycleh = (csr_idx == 12'hc80);
//wire rd_cycle = sel_cycle & csr_rd_en;
//wire wr_cycle = sel_cycle & csr_wr_en;
//wire cycle_ena = (wr_cycle & wbck_csr_wen);
//wire rd_cycleh = sel_cycleh & csr_rd_en;
//wire wr_cycleh = sel_cycleh & csr_wr_en;
//wire cycleh_ena = (wr_cycleh & wbck_csr_wen);
//wire [`E203_XLEN-1:0] cycle_r;
//wire [`E203_XLEN-1:0] cycleh_r;
//wire [`E203_XLEN-1:0] cycle_nxt = wbck_csr_dat;
//wire [`E203_XLEN-1:0] cycleh_nxt = wbck_csr_dat;
//sirv_gnrl_dfflr #(`E203_XLEN) cycle_dfflr (cycle_ena, cycle_nxt, cycle_r, clk, rst_n);
//sirv_gnrl_dfflr #(`E203_XLEN) cycleh_dfflr(cycleh_ena,cycleh_nxt,cycleh_r,clk, rst_n);
//wire [`E203_XLEN-1:0] csr_cycle = cycle_r;
//wire [`E203_XLEN-1:0] csr_cycleh = cycleh_r;
//`else//}{
//wire [`E203_XLEN-1:0] csr_cycle = `E203_XLEN'b0;
//wire [`E203_XLEN-1:0] csr_cycleh = `E203_XLEN'b0;
//`endif//}
//
//0x041 URW uepc User exception program counter.
// We dont support user trap, so no uepc needed
//0x341 MRW mepc Machine exception program counter.
wire sel_mepc = (csr_idx == 12'h341);
wire rd_mepc = sel_mepc & csr_rd_en;
wire wr_mepc = sel_mepc & csr_wr_en;
wire epc_ena = (wr_mepc & wbck_csr_wen) | cmt_epc_ena;
wire [`E203_PC_SIZE-1:0] epc_r;
wire [`E203_PC_SIZE-1:0] epc_nxt;
assign epc_nxt[`E203_PC_SIZE-1:1] = cmt_epc_ena ? cmt_epc[`E203_PC_SIZE-1:1] : wbck_csr_dat[`E203_PC_SIZE-1:1];
assign epc_nxt[0] = 1'b0;// Must not hold PC which will generate the misalign exception according to ISA
sirv_gnrl_dfflr #(`E203_PC_SIZE) epc_dfflr (epc_ena, epc_nxt, epc_r, clk, rst_n);
wire [`E203_XLEN-1:0] csr_mepc;
wire dummy_0;
assign {dummy_0,csr_mepc} = {{`E203_XLEN+1-`E203_PC_SIZE{1'b0}},epc_r};
assign csr_epc_r = csr_mepc;
//0x042 URW ucause User trap cause.
// We dont support user trap, so no ucause needed
//0x342 MRW mcause Machine trap cause.
wire sel_mcause = (csr_idx == 12'h342);
wire rd_mcause = sel_mcause & csr_rd_en;
wire wr_mcause = sel_mcause & csr_wr_en;
wire cause_ena = (wr_mcause & wbck_csr_wen) | cmt_cause_ena;
wire [`E203_XLEN-1:0] cause_r;
wire [`E203_XLEN-1:0] cause_nxt;
assign cause_nxt[31] = cmt_cause_ena ? cmt_cause[31] : wbck_csr_dat[31];
assign cause_nxt[30:4] = 27'b0;
assign cause_nxt[3:0] = cmt_cause_ena ? cmt_cause[3:0] : wbck_csr_dat[3:0];
sirv_gnrl_dfflr #(`E203_XLEN) cause_dfflr (cause_ena, cause_nxt, cause_r, clk, rst_n);
wire [`E203_XLEN-1:0] csr_mcause = cause_r;
//0x043 URW ubadaddr User bad address.
// We dont support user trap, so no ubadaddr needed
//0x343 MRW mbadaddr Machine bad address.
wire sel_mbadaddr = (csr_idx == 12'h343);
wire rd_mbadaddr = sel_mbadaddr & csr_rd_en;
wire wr_mbadaddr = sel_mbadaddr & csr_wr_en;
wire cmt_trap_badaddr_ena = cmt_badaddr_ena;
wire badaddr_ena = (wr_mbadaddr & wbck_csr_wen) | cmt_trap_badaddr_ena;
wire [`E203_ADDR_SIZE-1:0] badaddr_r;
wire [`E203_ADDR_SIZE-1:0] badaddr_nxt;
assign badaddr_nxt = cmt_trap_badaddr_ena ? cmt_badaddr : wbck_csr_dat[`E203_ADDR_SIZE-1:0];
sirv_gnrl_dfflr #(`E203_ADDR_SIZE) badaddr_dfflr (badaddr_ena, badaddr_nxt, badaddr_r, clk, rst_n);
wire [`E203_XLEN-1:0] csr_mbadaddr;
wire dummy_1;
assign {dummy_1,csr_mbadaddr} = {{`E203_XLEN+1-`E203_ADDR_SIZE{1'b0}},badaddr_r};
// We dont support the delegation scheme, so no need to implement
// delegete registers
//0x301 MRW misa ISA and extensions
wire sel_misa = (csr_idx == 12'h301);
wire rd_misa = sel_misa & csr_rd_en;
// Only implemented the M mode, IMC or EMC
wire [`E203_XLEN-1:0] csr_misa = {
2'b1
,4'b0 //WIRI
,1'b0 // 25 Z Reserved
,1'b0 // 24 Y Reserved
,1'b0 // 23 X Non-standard extensions present
,1'b0 // 22 W Reserved
,1'b0 // 21 V Tentatively reserved for Vector extension 20 U User mode implemented
,1'b0 // 20 U User mode implemented
,1'b0 // 19 T Tentatively reserved for Transactional Memory extension
,1'b0 // 18 S Supervisor mode implemented
,1'b0 // 17 R Reserved
,1'b0 // 16 Q Quad-precision floating-point extension
,1'b0 // 15 P Tentatively reserved for Packed-SIMD extension
,1'b0 // 14 O Reserved
,1'b0 // 13 N User-level interrupts supported
,1'b1 // 12 M Integer Multiply/Divide extension
,1'b0 // 11 L Tentatively reserved for Decimal Floating-Point extension
,1'b0 // 10 K Reserved
,1'b0 // 9 J Reserved
`ifdef E203_RFREG_NUM_IS_32
,1'b1 // 8 I RV32I/64I/128I base ISA
`else
,1'b0
`endif
,1'b0 // 7 H Hypervisor mode implemented
,1'b0 // 6 G Additional standard extensions present
`ifndef E203_HAS_FPU//{
,1'b0 // 5 F Single-precision floating-point extension
`endif//
`ifdef E203_RFREG_NUM_IS_32
,1'b0 // 4 E RV32E base ISA
`else
,1'b1 //
`endif
`ifndef E203_HAS_FPU//{
,1'b0 // 3 D Double-precision floating-point extension
`endif//
,1'b1 // 2 C Compressed extension
,1'b0 // 1 B Tentatively reserved for Bit operations extension
`ifdef E203_SUPPORT_AMO//{
,1'b1 // 0 A Atomic extension
`endif//E203_SUPPORT_AMO}
`ifndef E203_SUPPORT_AMO//{
,1'b0 // 0 A Atomic extension
`endif//}
};
//Machine Information Registers
//0xF11 MRO mvendorid Vendor ID.
//0xF12 MRO marchid Architecture ID.
//0xF13 MRO mimpid Implementation ID.
//0xF14 MRO mhartid Hardware thread ID.
wire [`E203_XLEN-1:0] csr_mvendorid = `E203_XLEN'h`E203_MVENDORID;
wire [`E203_XLEN-1:0] csr_marchid = `E203_XLEN'h`E203_MARCHID ;
wire [`E203_XLEN-1:0] csr_mimpid = `E203_XLEN'h`E203_MIMPID ;
wire [`E203_XLEN-1:0] csr_mhartid = {{`E203_XLEN-`E203_HART_ID_W{1'b0}},core_mhartid};
wire rd_mvendorid = csr_rd_en & (csr_idx == 12'hF11);
wire rd_marchid = csr_rd_en & (csr_idx == 12'hF12);
wire rd_mimpid = csr_rd_en & (csr_idx == 12'hF13);
wire rd_mhartid = csr_rd_en & (csr_idx == 12'hF14);
//0x7b0 Debug Control and Status
//0x7b1 Debug PC
//0x7b2 Debug Scratch Register
//0x7a0 Trigger selection register
wire sel_dcsr = (csr_idx == 12'h7b0);
wire sel_dpc = (csr_idx == 12'h7b1);
wire sel_dscratch = (csr_idx == 12'h7b2);
wire rd_dcsr = dbg_mode & csr_rd_en & sel_dcsr ;
wire rd_dpc = dbg_mode & csr_rd_en & sel_dpc ;
wire rd_dscratch = dbg_mode & csr_rd_en & sel_dscratch;
assign wr_dcsr_ena = dbg_mode & csr_wr_en & sel_dcsr ;
assign wr_dpc_ena = dbg_mode & csr_wr_en & sel_dpc ;
assign wr_dscratch_ena = dbg_mode & csr_wr_en & sel_dscratch;
assign wr_csr_nxt = wbck_csr_dat;
wire [`E203_XLEN-1:0] csr_dcsr = dcsr_r ;
`ifdef E203_PC_SIZE_IS_16
wire [`E203_XLEN-1:0] csr_dpc = {{`E203_XLEN-`E203_PC_SIZE{1'b0}},dpc_r};
`endif
`ifdef E203_PC_SIZE_IS_24
wire [`E203_XLEN-1:0] csr_dpc = {{`E203_XLEN-`E203_PC_SIZE{1'b0}},dpc_r};
`endif
`ifdef E203_PC_SIZE_IS_32
wire [`E203_XLEN-1:0] csr_dpc = dpc_r ;
`endif
wire [`E203_XLEN-1:0] csr_dscratch = dscratch_r;
assign csr_dpc_r = dpc_r;
/////////////////////////////////////////////////////////////////////
// Generate the Read path
//Currently we only support the M mode to simplify the implementation and
// reduce the gatecount because we are a privite core
assign u_mode = 1'b0;
assign s_mode = 1'b0;
assign h_mode = 1'b0;
assign m_mode = 1'b1;
assign read_csr_dat = `E203_XLEN'b0
//| ({`E203_XLEN{rd_ustatus }} & csr_ustatus )
| ({`E203_XLEN{rd_mstatus }} & csr_mstatus )
| ({`E203_XLEN{rd_mie }} & csr_mie )
| ({`E203_XLEN{rd_mtvec }} & csr_mtvec )
| ({`E203_XLEN{rd_mepc }} & csr_mepc )
| ({`E203_XLEN{rd_mscratch }} & csr_mscratch )
| ({`E203_XLEN{rd_mcause }} & csr_mcause )
| ({`E203_XLEN{rd_mbadaddr }} & csr_mbadaddr )
| ({`E203_XLEN{rd_mip }} & csr_mip )
| ({`E203_XLEN{rd_misa }} & csr_misa )
| ({`E203_XLEN{rd_mvendorid}} & csr_mvendorid)
| ({`E203_XLEN{rd_marchid }} & csr_marchid )
| ({`E203_XLEN{rd_mimpid }} & csr_mimpid )
| ({`E203_XLEN{rd_mhartid }} & csr_mhartid )
| ({`E203_XLEN{rd_mcycle }} & csr_mcycle )
| ({`E203_XLEN{rd_mcycleh }} & csr_mcycleh )
| ({`E203_XLEN{rd_minstret }} & csr_minstret )
| ({`E203_XLEN{rd_minstreth}} & csr_minstreth)
| ({`E203_XLEN{rd_counterstop}} & csr_counterstop)// Self-defined
| ({`E203_XLEN{rd_mcgstop}} & csr_mcgstop)// Self-defined
| ({`E203_XLEN{rd_itcmnohold}} & csr_itcmnohold)// Self-defined
| ({`E203_XLEN{rd_mdvnob2b}} & csr_mdvnob2b)// Self-defined
| ({`E203_XLEN{rd_dcsr }} & csr_dcsr )
| ({`E203_XLEN{rd_dpc }} & csr_dpc )
| ({`E203_XLEN{rd_dscratch }} & csr_dscratch)
;
endmodule
|
module sirv_aon_top #(
parameter ASYNC_FF_LEVELS = 2
)(
input i_icb_cmd_valid,
output i_icb_cmd_ready,
input [32-1:0] i_icb_cmd_addr,
input i_icb_cmd_read,
input [32-1:0] i_icb_cmd_wdata,
output i_icb_rsp_valid,
input i_icb_rsp_ready,
output [32-1:0] i_icb_rsp_rdata,
input io_pads_aon_erst_n_i_ival,
output io_pads_aon_erst_n_o_oval,
output io_pads_aon_erst_n_o_oe,
output io_pads_aon_erst_n_o_ie,
output io_pads_aon_erst_n_o_pue,
output io_pads_aon_erst_n_o_ds,
input io_pads_aon_pmu_dwakeup_n_i_ival,
output io_pads_aon_pmu_dwakeup_n_o_oval,
output io_pads_aon_pmu_dwakeup_n_o_oe,
output io_pads_aon_pmu_dwakeup_n_o_ie,
output io_pads_aon_pmu_dwakeup_n_o_pue,
output io_pads_aon_pmu_dwakeup_n_o_ds,
input io_pads_aon_pmu_vddpaden_i_ival,
output io_pads_aon_pmu_vddpaden_o_oval,
output io_pads_aon_pmu_vddpaden_o_oe,
output io_pads_aon_pmu_vddpaden_o_ie,
output io_pads_aon_pmu_vddpaden_o_pue,
output io_pads_aon_pmu_vddpaden_o_ds,
input io_pads_aon_pmu_padrst_i_ival,
output io_pads_aon_pmu_padrst_o_oval,
output io_pads_aon_pmu_padrst_o_oe,
output io_pads_aon_pmu_padrst_o_ie,
output io_pads_aon_pmu_padrst_o_pue,
output io_pads_aon_pmu_padrst_o_ds,
input io_pads_dbgmode0_n_i_ival,
input io_pads_dbgmode1_n_i_ival,
input io_pads_dbgmode2_n_i_ival,
input io_pads_bootrom_n_i_ival,
output io_pads_bootrom_n_o_oval,
output io_pads_bootrom_n_o_oe,
output io_pads_bootrom_n_o_ie,
output io_pads_bootrom_n_o_pue,
output io_pads_bootrom_n_o_ds,
input io_pads_jtagpwd_n_i_ival,
output io_pads_jtagpwd_n_o_oval,
output io_pads_jtagpwd_n_o_oe,
output io_pads_jtagpwd_n_o_ie,
output io_pads_jtagpwd_n_o_pue,
output io_pads_jtagpwd_n_o_ds,
output hfclkrst,
output corerst,
output jtagpwd_iso,
output inspect_mode,
output inspect_por_rst,
output inspect_32k_clk,
input inspect_pc_29b,
input inspect_dbg_irq,
output [32-1:0] pc_rtvec,
output aon_wdg_irq,
output aon_rtc_irq,
output aon_rtcToggle,
input lfextclk,
output lfxoscen,
input test_mode,
input test_iso_override
);
// Since the Aon module need to handle the path from the MOFF domain, which
// maybe powered down, so we need to have the isolation cells here
// it can be handled by UPF flow, but we can also add them mannually here
// The inputs from MOFF to aon domain need to be isolated
// The outputs does not need to be isolated
wire isl_icb_cmd_valid;
wire isl_icb_cmd_ready;
wire [32-1:0] isl_icb_cmd_addr;
wire isl_icb_cmd_read;
wire [32-1:0] isl_icb_cmd_wdata;
wire isl_icb_rsp_valid;
wire isl_icb_rsp_ready;
wire [32-1:0] isl_icb_rsp_rdata;
wire aon_iso;
assign isl_icb_cmd_valid = aon_iso ? 1'b0 : i_icb_cmd_valid;
assign isl_icb_cmd_addr = aon_iso ? 32'b0 : i_icb_cmd_addr ;
assign isl_icb_cmd_read = aon_iso ? 1'b0 : i_icb_cmd_read ;
assign isl_icb_cmd_wdata = aon_iso ? 32'b0 : i_icb_cmd_wdata;
assign isl_icb_rsp_ready = aon_iso ? 1'b0 : i_icb_rsp_ready;
assign i_icb_rsp_valid = isl_icb_rsp_valid;
assign i_icb_cmd_ready = isl_icb_cmd_ready;
assign i_icb_rsp_rdata = isl_icb_rsp_rdata;
wire synced_icb_cmd_valid;
wire synced_icb_cmd_ready;
wire [32-1:0] synced_icb_cmd_addr;
wire synced_icb_cmd_read;
wire [32-1:0] synced_icb_cmd_wdata;
wire synced_icb_rsp_valid;
wire synced_icb_rsp_ready;
wire [32-1:0] synced_icb_rsp_rdata;
wire lclkgen_icb_cmd_valid;
wire lclkgen_icb_cmd_ready;
wire [15-1:0] lclkgen_icb_cmd_addr;
wire lclkgen_icb_cmd_read;
wire [32-1:0] lclkgen_icb_cmd_wdata;
wire lclkgen_icb_rsp_valid;
wire lclkgen_icb_rsp_ready;
wire [32-1:0] lclkgen_icb_rsp_rdata;
wire aon_icb_cmd_valid;
wire aon_icb_cmd_ready;
wire [15-1:0] aon_icb_cmd_addr;
wire aon_icb_cmd_read;
wire [32-1:0] aon_icb_cmd_wdata;
wire aon_icb_rsp_valid;
wire aon_icb_rsp_ready;
wire [32-1:0] aon_icb_rsp_rdata;
localparam CMD_PACK_W = 65;
wire [CMD_PACK_W-1:0] synced_icb_cmd_pack;
wire [CMD_PACK_W-1:0] isl_icb_cmd_pack;
assign isl_icb_cmd_pack = {
isl_icb_cmd_addr,
isl_icb_cmd_read,
isl_icb_cmd_wdata};
assign {synced_icb_cmd_addr,
synced_icb_cmd_read,
synced_icb_cmd_wdata} = synced_icb_cmd_pack;
wire crossing_clock;
wire crossing_reset;
wire crossing_reset_n = ~crossing_reset;
sirv_gnrl_cdc_tx
# (
.DW (32),
.SYNC_DP (ASYNC_FF_LEVELS)
) u_aon_icb_cdc_tx (
.o_vld (isl_icb_rsp_valid ),
.o_rdy_a(isl_icb_rsp_ready ),
.o_dat (isl_icb_rsp_rdata ),
.i_vld (synced_icb_rsp_valid ),
.i_rdy (synced_icb_rsp_ready ),
.i_dat (synced_icb_rsp_rdata ),
.clk (crossing_clock),
.rst_n (crossing_reset_n)
);
sirv_gnrl_cdc_rx
# (
.DW (CMD_PACK_W),
.SYNC_DP (ASYNC_FF_LEVELS)
) u_aon_icb_cdc_rx (
.i_vld_a(isl_icb_cmd_valid),
.i_rdy (isl_icb_cmd_ready),
.i_dat (isl_icb_cmd_pack),
.o_vld (synced_icb_cmd_valid),
.o_rdy (synced_icb_cmd_ready),
.o_dat (synced_icb_cmd_pack),
.clk (crossing_clock),
.rst_n (crossing_reset_n)
);
sirv_icb1to2_bus # (
.ICB_FIFO_DP (0),//Pass through
.ICB_FIFO_CUT_READY (1),//
.AW (15),
.DW (32),
.SPLT_FIFO_OUTS_NUM (1),// Allow 1 oustanding
.SPLT_FIFO_CUT_READY (1),// Always cut ready
// * LCLKGEN : 0x200 -- 0x2FF
.O0_BASE_ADDR (15'h200),
.O0_BASE_REGION_LSB (8)
)u_aon_1to2_icb(
.i_icb_cmd_valid (synced_icb_cmd_valid),
.i_icb_cmd_ready (synced_icb_cmd_ready),
.i_icb_cmd_addr (synced_icb_cmd_addr[14:0] ),
.i_icb_cmd_read (synced_icb_cmd_read ),
.i_icb_cmd_wdata (synced_icb_cmd_wdata),
.i_icb_cmd_wmask (4'hF),
.i_icb_cmd_lock (1'b0),
.i_icb_cmd_excl (1'b0 ),
.i_icb_cmd_size (2'b0 ),
.i_icb_cmd_burst (2'b0 ),
.i_icb_cmd_beat (2'b0 ),
.i_icb_rsp_valid (synced_icb_rsp_valid),
.i_icb_rsp_ready (synced_icb_rsp_ready),
.i_icb_rsp_err (),
.i_icb_rsp_excl_ok(),
.i_icb_rsp_rdata (synced_icb_rsp_rdata),
// * LCLKGEN
//
.o0_icb_cmd_valid (lclkgen_icb_cmd_valid),
.o0_icb_cmd_ready (lclkgen_icb_cmd_ready),
.o0_icb_cmd_addr (lclkgen_icb_cmd_addr ),
.o0_icb_cmd_read (lclkgen_icb_cmd_read ),
.o0_icb_cmd_wdata (lclkgen_icb_cmd_wdata),
.o0_icb_cmd_wmask (),
.o0_icb_cmd_lock (),
.o0_icb_cmd_excl (),
.o0_icb_cmd_size (),
.o0_icb_cmd_burst (),
.o0_icb_cmd_beat (),
.o0_icb_rsp_valid (lclkgen_icb_rsp_valid),
.o0_icb_rsp_ready (lclkgen_icb_rsp_ready),
.o0_icb_rsp_err (1'b0),
.o0_icb_rsp_excl_ok(1'b0 ),
.o0_icb_rsp_rdata (lclkgen_icb_rsp_rdata),
// * AON
.o1_icb_cmd_valid (aon_icb_cmd_valid),
.o1_icb_cmd_ready (aon_icb_cmd_ready),
.o1_icb_cmd_addr (aon_icb_cmd_addr ),
.o1_icb_cmd_read (aon_icb_cmd_read ),
.o1_icb_cmd_wdata (aon_icb_cmd_wdata),
.o1_icb_cmd_wmask (),
.o1_icb_cmd_lock (),
.o1_icb_cmd_excl (),
.o1_icb_cmd_size (),
.o1_icb_cmd_burst (),
.o1_icb_cmd_beat (),
.o1_icb_rsp_valid (aon_icb_rsp_valid),
.o1_icb_rsp_ready (aon_icb_rsp_ready),
.o1_icb_rsp_err (1'b0 ),
.o1_icb_rsp_excl_ok(1'b0 ),
.o1_icb_rsp_rdata (aon_icb_rsp_rdata),
.clk (crossing_clock),
.rst_n (crossing_reset_n)
);
wire aon_reset;
wire aon_reset_n = ~aon_reset;
sirv_aon_lclkgen_regs u_aon_lclkgen_regs(
.clk (crossing_clock),// Crossing clock is actually the aon_clk
.rst_n (aon_reset_n),// Here we need to use the aon_rst rather than the crossing reset
.lfxoscen (lfxoscen ),
.i_icb_cmd_valid(lclkgen_icb_cmd_valid),
.i_icb_cmd_ready(lclkgen_icb_cmd_ready),
.i_icb_cmd_addr (lclkgen_icb_cmd_addr[7:0]),
.i_icb_cmd_read (lclkgen_icb_cmd_read ),
.i_icb_cmd_wdata(lclkgen_icb_cmd_wdata),
.i_icb_rsp_valid(lclkgen_icb_rsp_valid),
.i_icb_rsp_ready(lclkgen_icb_rsp_ready),
.i_icb_rsp_rdata(lclkgen_icb_rsp_rdata)
);
wire io_tl_in_0_a_ready;
assign aon_icb_cmd_ready = io_tl_in_0_a_ready;
wire io_tl_in_0_a_valid = aon_icb_cmd_valid;
wire [2:0] io_tl_in_0_a_bits_opcode = aon_icb_cmd_read ? 3'h4 : 3'h0;
wire [2:0] io_tl_in_0_a_bits_param = 3'b0;
wire [2:0] io_tl_in_0_a_bits_size = 3'd2;
wire [4:0] io_tl_in_0_a_bits_source = 5'b0;
wire [28:0] io_tl_in_0_a_bits_address = {14'b0,aon_icb_cmd_addr[14:0]};
wire [3:0] io_tl_in_0_a_bits_mask = 4'b1111;
wire [31:0] io_tl_in_0_a_bits_data = aon_icb_cmd_wdata;
wire io_tl_in_0_d_ready = aon_icb_rsp_ready;
wire [2:0] io_tl_in_0_d_bits_opcode;
wire [1:0] io_tl_in_0_d_bits_param;
wire [2:0] io_tl_in_0_d_bits_size;
wire [4:0] io_tl_in_0_d_bits_source;
wire io_tl_in_0_d_bits_sink;
wire [1:0] io_tl_in_0_d_bits_addr_lo;
wire [31:0] io_tl_in_0_d_bits_data;
wire io_tl_in_0_d_bits_error;
wire io_tl_in_0_d_valid;
assign aon_icb_rsp_valid = io_tl_in_0_d_valid;
assign aon_icb_rsp_rdata = io_tl_in_0_d_bits_data;
// Not used
wire io_tl_in_0_b_ready = 1'b0;
wire io_tl_in_0_b_valid;
wire [2:0] io_tl_in_0_b_bits_opcode;
wire [1:0] io_tl_in_0_b_bits_param;
wire [2:0] io_tl_in_0_b_bits_size;
wire [4:0] io_tl_in_0_b_bits_source;
wire [28:0] io_tl_in_0_b_bits_address;
wire [3:0] io_tl_in_0_b_bits_mask;
wire [31:0] io_tl_in_0_b_bits_data;
// Not used
wire io_tl_in_0_c_ready;
wire io_tl_in_0_c_valid = 1'b0;
wire [2:0] io_tl_in_0_c_bits_opcode = 3'b0;
wire [2:0] io_tl_in_0_c_bits_param = 3'b0;
wire [2:0] io_tl_in_0_c_bits_size = 3'd2;
wire [4:0] io_tl_in_0_c_bits_source = 5'b0;
wire [28:0] io_tl_in_0_c_bits_address = 29'b0;
wire [31:0] io_tl_in_0_c_bits_data = 32'b0;
wire io_tl_in_0_c_bits_error = 1'b0;
// Not used
wire io_tl_in_0_e_ready;
wire io_tl_in_0_e_valid = 1'b0;
wire io_tl_in_0_e_bits_sink = 1'b0;
sirv_aon_wrapper u_sirv_aon_wrapper(
.aon_reset (aon_reset),
.aon_iso (aon_iso),
.jtagpwd_iso (jtagpwd_iso),
.crossing_clock (crossing_clock),
.crossing_reset (crossing_reset),
.io_in_0_a_ready (io_tl_in_0_a_ready ),
.io_in_0_a_valid (io_tl_in_0_a_valid ),
.io_in_0_a_bits_opcode (io_tl_in_0_a_bits_opcode ),
.io_in_0_a_bits_param (io_tl_in_0_a_bits_param ),
.io_in_0_a_bits_size (io_tl_in_0_a_bits_size ),
.io_in_0_a_bits_source (io_tl_in_0_a_bits_source ),
.io_in_0_a_bits_address (io_tl_in_0_a_bits_address ),
.io_in_0_a_bits_mask (io_tl_in_0_a_bits_mask ),
.io_in_0_a_bits_data (io_tl_in_0_a_bits_data ),
.io_in_0_b_ready (io_tl_in_0_b_ready ),
.io_in_0_b_valid (io_tl_in_0_b_valid ),
.io_in_0_b_bits_opcode (io_tl_in_0_b_bits_opcode ),
.io_in_0_b_bits_param (io_tl_in_0_b_bits_param ),
.io_in_0_b_bits_size (io_tl_in_0_b_bits_size ),
.io_in_0_b_bits_source (io_tl_in_0_b_bits_source ),
.io_in_0_b_bits_address (io_tl_in_0_b_bits_address ),
.io_in_0_b_bits_mask (io_tl_in_0_b_bits_mask ),
.io_in_0_b_bits_data (io_tl_in_0_b_bits_data ),
.io_in_0_c_ready (io_tl_in_0_c_ready ),
.io_in_0_c_valid (io_tl_in_0_c_valid ),
.io_in_0_c_bits_opcode (io_tl_in_0_c_bits_opcode ),
.io_in_0_c_bits_param (io_tl_in_0_c_bits_param ),
.io_in_0_c_bits_size (io_tl_in_0_c_bits_size ),
.io_in_0_c_bits_source (io_tl_in_0_c_bits_source ),
.io_in_0_c_bits_address (io_tl_in_0_c_bits_address ),
.io_in_0_c_bits_data (io_tl_in_0_c_bits_data ),
.io_in_0_c_bits_error (io_tl_in_0_c_bits_error ),
.io_in_0_d_ready (io_tl_in_0_d_ready ),
.io_in_0_d_valid (io_tl_in_0_d_valid ),
.io_in_0_d_bits_opcode (io_tl_in_0_d_bits_opcode ),
.io_in_0_d_bits_param (io_tl_in_0_d_bits_param ),
.io_in_0_d_bits_size (io_tl_in_0_d_bits_size ),
.io_in_0_d_bits_source (io_tl_in_0_d_bits_source ),
.io_in_0_d_bits_sink (io_tl_in_0_d_bits_sink ),
.io_in_0_d_bits_addr_lo (io_tl_in_0_d_bits_addr_lo ),
.io_in_0_d_bits_data (io_tl_in_0_d_bits_data ),
.io_in_0_d_bits_error (io_tl_in_0_d_bits_error ),
.io_in_0_e_ready (io_tl_in_0_e_ready ),
.io_in_0_e_valid (io_tl_in_0_e_valid ),
.io_in_0_e_bits_sink (io_tl_in_0_e_bits_sink ),
.io_ip_0_0 (aon_wdg_irq),
.io_ip_0_1 (aon_rtc_irq),
.io_pads_erst_n_i_ival (io_pads_aon_erst_n_i_ival ),
.io_pads_erst_n_o_oval (io_pads_aon_erst_n_o_oval ),
.io_pads_erst_n_o_oe (io_pads_aon_erst_n_o_oe ),
.io_pads_erst_n_o_ie (io_pads_aon_erst_n_o_ie ),
.io_pads_erst_n_o_pue (io_pads_aon_erst_n_o_pue ),
.io_pads_erst_n_o_ds (io_pads_aon_erst_n_o_ds ),
.io_pads_lfextclk_i_ival (lfextclk ),
.io_pads_lfextclk_o_oval (),
.io_pads_lfextclk_o_oe (),
.io_pads_lfextclk_o_ie (),
.io_pads_lfextclk_o_pue (),
.io_pads_lfextclk_o_ds (),
.io_pads_pmu_dwakeup_n_i_ival(io_pads_aon_pmu_dwakeup_n_i_ival),
.io_pads_pmu_dwakeup_n_o_oval(io_pads_aon_pmu_dwakeup_n_o_oval),
.io_pads_pmu_dwakeup_n_o_oe (io_pads_aon_pmu_dwakeup_n_o_oe ),
.io_pads_pmu_dwakeup_n_o_ie (io_pads_aon_pmu_dwakeup_n_o_ie ),
.io_pads_pmu_dwakeup_n_o_pue (io_pads_aon_pmu_dwakeup_n_o_pue ),
.io_pads_pmu_dwakeup_n_o_ds (io_pads_aon_pmu_dwakeup_n_o_ds ),
.io_pads_pmu_vddpaden_i_ival (io_pads_aon_pmu_vddpaden_i_ival ),
.io_pads_pmu_vddpaden_o_oval (io_pads_aon_pmu_vddpaden_o_oval ),
.io_pads_pmu_vddpaden_o_oe (io_pads_aon_pmu_vddpaden_o_oe ),
.io_pads_pmu_vddpaden_o_ie (io_pads_aon_pmu_vddpaden_o_ie ),
.io_pads_pmu_vddpaden_o_pue (io_pads_aon_pmu_vddpaden_o_pue ),
.io_pads_pmu_vddpaden_o_ds (io_pads_aon_pmu_vddpaden_o_ds ),
.io_pads_pmu_padrst_i_ival (io_pads_aon_pmu_padrst_i_ival ),
.io_pads_pmu_padrst_o_oval (io_pads_aon_pmu_padrst_o_oval ),
.io_pads_pmu_padrst_o_oe (io_pads_aon_pmu_padrst_o_oe ),
.io_pads_pmu_padrst_o_ie (io_pads_aon_pmu_padrst_o_ie ),
.io_pads_pmu_padrst_o_pue (io_pads_aon_pmu_padrst_o_pue ),
.io_pads_pmu_padrst_o_ds (io_pads_aon_pmu_padrst_o_ds ),
.io_pads_jtagpwd_n_i_ival (io_pads_jtagpwd_n_i_ival),
.io_pads_jtagpwd_n_o_oval (io_pads_jtagpwd_n_o_oval),
.io_pads_jtagpwd_n_o_oe (io_pads_jtagpwd_n_o_oe ),
.io_pads_jtagpwd_n_o_ie (io_pads_jtagpwd_n_o_ie ),
.io_pads_jtagpwd_n_o_pue (io_pads_jtagpwd_n_o_pue ),
.io_pads_jtagpwd_n_o_ds (io_pads_jtagpwd_n_o_ds ),
.io_pads_bootrom_n_i_ival (io_pads_bootrom_n_i_ival),
.io_pads_bootrom_n_o_oval (io_pads_bootrom_n_o_oval),
.io_pads_bootrom_n_o_oe (io_pads_bootrom_n_o_oe ),
.io_pads_bootrom_n_o_ie (io_pads_bootrom_n_o_ie ),
.io_pads_bootrom_n_o_pue (io_pads_bootrom_n_o_pue ),
.io_pads_bootrom_n_o_ds (io_pads_bootrom_n_o_ds ),
.io_pads_dbgmode0_n_i_ival (io_pads_dbgmode0_n_i_ival),
.io_pads_dbgmode1_n_i_ival (io_pads_dbgmode1_n_i_ival),
.io_pads_dbgmode2_n_i_ival (io_pads_dbgmode2_n_i_ival),
.inspect_mode (inspect_mode ),
.inspect_pc_29b (inspect_pc_29b ),
.inspect_por_rst (inspect_por_rst ),
.inspect_32k_clk (inspect_32k_clk ),
.inspect_dbg_irq (inspect_dbg_irq ),
.pc_rtvec (pc_rtvec),
.io_rsts_hfclkrst(hfclkrst),
.io_rsts_corerst (corerst ),
.io_rtc (aon_rtcToggle),
.test_mode (test_mode ),
.test_iso_override(test_iso_override)
);
endmodule
|
module e203_cpu #(
parameter MASTER = 1
)(
output [`E203_PC_SIZE-1:0] inspect_pc,
output inspect_dbg_irq ,
output inspect_mem_cmd_valid,
output inspect_mem_cmd_ready,
output inspect_mem_rsp_valid,
output inspect_mem_rsp_ready,
output inspect_core_clk ,
output core_csr_clk ,
`ifdef E203_HAS_ITCM
output rst_itcm,
`endif
`ifdef E203_HAS_DTCM
output rst_dtcm,
`endif
output core_wfi,
output tm_stop,
input [`E203_PC_SIZE-1:0] pc_rtvec,
///////////////////////////////////////
// With the interface to debug module
//
// The interface with commit stage
output [`E203_PC_SIZE-1:0] cmt_dpc,
output cmt_dpc_ena,
output [3-1:0] cmt_dcause,
output cmt_dcause_ena,
output dbg_irq_r,
// The interface with CSR control
output wr_dcsr_ena ,
output wr_dpc_ena ,
output wr_dscratch_ena,
output [32-1:0] wr_csr_nxt ,
input [32-1:0] dcsr_r ,
input [`E203_PC_SIZE-1:0] dpc_r ,
input [32-1:0] dscratch_r,
input dbg_mode,
input dbg_halt_r,
input dbg_step_r,
input dbg_ebreakm_r,
input dbg_stopcycle,
/////////////////////////////////////////////////////
input [`E203_HART_ID_W-1:0] core_mhartid,
input dbg_irq_a,
input ext_irq_a,
input sft_irq_a,
input tmr_irq_a,
`ifdef E203_HAS_ITCM //{
//input [`E203_ADDR_SIZE-1:0] itcm_region_indic,
`endif//}
`ifdef E203_HAS_DTCM //{
//input [`E203_ADDR_SIZE-1:0] dtcm_region_indic,
`endif//}
`ifdef E203_HAS_ITCM_EXTITF //{
//////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////
// External-agent ICB to ITCM
// * Bus cmd channel
input ext2itcm_icb_cmd_valid,
output ext2itcm_icb_cmd_ready,
input [`E203_ITCM_ADDR_WIDTH-1:0] ext2itcm_icb_cmd_addr,
input ext2itcm_icb_cmd_read,
input [`E203_XLEN-1:0] ext2itcm_icb_cmd_wdata,
input [`E203_XLEN/8-1:0] ext2itcm_icb_cmd_wmask,
//
// * Bus RSP channel
output ext2itcm_icb_rsp_valid,
input ext2itcm_icb_rsp_ready,
output ext2itcm_icb_rsp_err ,
output [`E203_XLEN-1:0] ext2itcm_icb_rsp_rdata,
`endif//}
`ifdef E203_HAS_DTCM_EXTITF //{
//////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////
// External-agent ICB to DTCM
// * Bus cmd channel
input ext2dtcm_icb_cmd_valid,
output ext2dtcm_icb_cmd_ready,
input [`E203_DTCM_ADDR_WIDTH-1:0] ext2dtcm_icb_cmd_addr,
input ext2dtcm_icb_cmd_read,
input [`E203_XLEN-1:0] ext2dtcm_icb_cmd_wdata,
input [`E203_XLEN/8-1:0] ext2dtcm_icb_cmd_wmask,
//
// * Bus RSP channel
output ext2dtcm_icb_rsp_valid,
input ext2dtcm_icb_rsp_ready,
output ext2dtcm_icb_rsp_err ,
output [`E203_XLEN-1:0] ext2dtcm_icb_rsp_rdata,
`endif//}
//////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////
// The ICB Interface to Private Peripheral Interface
input [`E203_ADDR_SIZE-1:0] ppi_region_indic,
//
input ppi_icb_enable,
// * Bus cmd channel
output ppi_icb_cmd_valid,
input ppi_icb_cmd_ready,
output [`E203_ADDR_SIZE-1:0] ppi_icb_cmd_addr,
output ppi_icb_cmd_read,
output [`E203_XLEN-1:0] ppi_icb_cmd_wdata,
output [`E203_XLEN/8-1:0] ppi_icb_cmd_wmask,
output ppi_icb_cmd_lock,
output ppi_icb_cmd_excl,
output [1:0] ppi_icb_cmd_size,
//
// * Bus RSP channel
input ppi_icb_rsp_valid,
output ppi_icb_rsp_ready,
input ppi_icb_rsp_err ,
input ppi_icb_rsp_excl_ok ,
input [`E203_XLEN-1:0] ppi_icb_rsp_rdata,
input [`E203_ADDR_SIZE-1:0] clint_region_indic,
input clint_icb_enable,
output clint_icb_cmd_valid,
input clint_icb_cmd_ready,
output [`E203_ADDR_SIZE-1:0] clint_icb_cmd_addr,
output clint_icb_cmd_read,
output [`E203_XLEN-1:0] clint_icb_cmd_wdata,
output [`E203_XLEN/8-1:0] clint_icb_cmd_wmask,
output clint_icb_cmd_lock,
output clint_icb_cmd_excl,
output [1:0] clint_icb_cmd_size,
//
// * Bus RSP channel
input clint_icb_rsp_valid,
output clint_icb_rsp_ready,
input clint_icb_rsp_err ,
input clint_icb_rsp_excl_ok ,
input [`E203_XLEN-1:0] clint_icb_rsp_rdata,
input [`E203_ADDR_SIZE-1:0] plic_region_indic,
input plic_icb_enable,
output plic_icb_cmd_valid,
input plic_icb_cmd_ready,
output [`E203_ADDR_SIZE-1:0] plic_icb_cmd_addr,
output plic_icb_cmd_read,
output [`E203_XLEN-1:0] plic_icb_cmd_wdata,
output [`E203_XLEN/8-1:0] plic_icb_cmd_wmask,
output plic_icb_cmd_lock,
output plic_icb_cmd_excl,
output [1:0] plic_icb_cmd_size,
//
// * Bus RSP channel
input plic_icb_rsp_valid,
output plic_icb_rsp_ready,
input plic_icb_rsp_err ,
input plic_icb_rsp_excl_ok ,
input [`E203_XLEN-1:0] plic_icb_rsp_rdata,
`ifdef E203_HAS_FIO //{
//////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////
// The ICB Interface to Fast I/O
input [`E203_ADDR_SIZE-1:0] fio_region_indic,
//
input fio_icb_enable,
// * Bus cmd channel
output fio_icb_cmd_valid,
input fio_icb_cmd_ready,
output [`E203_ADDR_SIZE-1:0] fio_icb_cmd_addr,
output fio_icb_cmd_read,
output [`E203_XLEN-1:0] fio_icb_cmd_wdata,
output [`E203_XLEN/8-1:0] fio_icb_cmd_wmask,
output fio_icb_cmd_lock,
output fio_icb_cmd_excl,
output [1:0] fio_icb_cmd_size,
//
// * Bus RSP channel
input fio_icb_rsp_valid,
output fio_icb_rsp_ready,
input fio_icb_rsp_err ,
input fio_icb_rsp_excl_ok ,
input [`E203_XLEN-1:0] fio_icb_rsp_rdata,
`endif//}
`ifdef E203_HAS_MEM_ITF //{
//////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////
// The ICB Interface from Ifetch
//
input mem_icb_enable,
// * Bus cmd channel
output mem_icb_cmd_valid,
input mem_icb_cmd_ready,
output [`E203_ADDR_SIZE-1:0] mem_icb_cmd_addr,
output mem_icb_cmd_read,
output [`E203_XLEN-1:0] mem_icb_cmd_wdata,
output [`E203_XLEN/8-1:0] mem_icb_cmd_wmask,
output mem_icb_cmd_lock,
output mem_icb_cmd_excl,
output [1:0] mem_icb_cmd_size,
output [1:0] mem_icb_cmd_burst,
output [1:0] mem_icb_cmd_beat,
//
// * Bus RSP channel
input mem_icb_rsp_valid,
output mem_icb_rsp_ready,
input mem_icb_rsp_err ,
input mem_icb_rsp_excl_ok,
input [`E203_XLEN-1:0] mem_icb_rsp_rdata,
`endif//}
`ifdef E203_HAS_ITCM//{
output itcm_ls,
output itcm_ram_cs,
output itcm_ram_we,
output [`E203_ITCM_RAM_AW-1:0] itcm_ram_addr,
output [`E203_ITCM_RAM_MW-1:0] itcm_ram_wem,
output [`E203_ITCM_RAM_DW-1:0] itcm_ram_din,
input [`E203_ITCM_RAM_DW-1:0] itcm_ram_dout,
output clk_itcm_ram,
`endif//}
`ifdef E203_HAS_DTCM//{
output dtcm_ls,
output dtcm_ram_cs,
output dtcm_ram_we,
output [`E203_DTCM_RAM_AW-1:0] dtcm_ram_addr,
output [`E203_DTCM_RAM_MW-1:0] dtcm_ram_wem,
output [`E203_DTCM_RAM_DW-1:0] dtcm_ram_din,
input [`E203_DTCM_RAM_DW-1:0] dtcm_ram_dout,
output clk_dtcm_ram,
`endif//}
input test_mode,
input clk,
input rst_n
);
wire core_cgstop;
wire tcm_cgstop;
wire core_ifu_active;
wire core_exu_active;
wire core_lsu_active;
wire core_biu_active;
// The core's clk and rst
wire rst_core;
wire clk_core_ifu;
wire clk_core_exu;
wire clk_core_lsu;
wire clk_core_biu;
// The ITCM/DTCM clk and rst
`ifdef E203_HAS_ITCM
wire clk_itcm;
wire itcm_active;
`endif
`ifdef E203_HAS_DTCM
wire clk_dtcm;
wire dtcm_active;
`endif
// The Top always on clk and rst
wire rst_aon;
wire clk_aon;
// The reset ctrl and clock ctrl should be in the power always-on domain
e203_reset_ctrl #(.MASTER(MASTER)) u_e203_reset_ctrl (
.clk (clk_aon ),
.rst_n (rst_n ),
.test_mode (test_mode),
.rst_core (rst_core),
`ifdef E203_HAS_ITCM
.rst_itcm (rst_itcm),
`endif
`ifdef E203_HAS_DTCM
.rst_dtcm (rst_dtcm),
`endif
.rst_aon (rst_aon)
);
e203_clk_ctrl u_e203_clk_ctrl(
.clk (clk ),
.rst_n (rst_aon ),
.test_mode (test_mode ),
.clk_aon (clk_aon ),
.core_cgstop (core_cgstop),
.clk_core_ifu (clk_core_ifu ),
.clk_core_exu (clk_core_exu ),
.clk_core_lsu (clk_core_lsu ),
.clk_core_biu (clk_core_biu ),
`ifdef E203_HAS_ITCM
.clk_itcm (clk_itcm ),
.itcm_active (itcm_active),
.itcm_ls (itcm_ls ),
`endif
`ifdef E203_HAS_DTCM
.clk_dtcm (clk_dtcm ),
.dtcm_active (dtcm_active),
.dtcm_ls (dtcm_ls ),
`endif
.core_ifu_active(core_ifu_active),
.core_exu_active(core_exu_active),
.core_lsu_active(core_lsu_active),
.core_biu_active(core_biu_active),
.core_wfi (core_wfi )
);
wire ext_irq_r;
wire sft_irq_r;
wire tmr_irq_r;
e203_irq_sync #(.MASTER(MASTER)) u_e203_irq_sync(
.clk (clk_aon ),
.rst_n (rst_aon ),
.dbg_irq_a (dbg_irq_a),
.dbg_irq_r (dbg_irq_r),
.ext_irq_a (ext_irq_a),
.sft_irq_a (sft_irq_a),
.tmr_irq_a (tmr_irq_a),
.ext_irq_r (ext_irq_r),
.sft_irq_r (sft_irq_r),
.tmr_irq_r (tmr_irq_r)
);
`ifdef E203_HAS_ITCM //{
wire ifu2itcm_holdup;
//wire ifu2itcm_replay;
wire ifu2itcm_icb_cmd_valid;
wire ifu2itcm_icb_cmd_ready;
wire [`E203_ITCM_ADDR_WIDTH-1:0] ifu2itcm_icb_cmd_addr;
wire ifu2itcm_icb_rsp_valid;
wire ifu2itcm_icb_rsp_ready;
wire ifu2itcm_icb_rsp_err;
wire [`E203_ITCM_DATA_WIDTH-1:0] ifu2itcm_icb_rsp_rdata;
wire lsu2itcm_icb_cmd_valid;
wire lsu2itcm_icb_cmd_ready;
wire [`E203_ITCM_ADDR_WIDTH-1:0] lsu2itcm_icb_cmd_addr;
wire lsu2itcm_icb_cmd_read;
wire [`E203_XLEN-1:0] lsu2itcm_icb_cmd_wdata;
wire [`E203_XLEN/8-1:0] lsu2itcm_icb_cmd_wmask;
wire lsu2itcm_icb_cmd_lock;
wire lsu2itcm_icb_cmd_excl;
wire [1:0] lsu2itcm_icb_cmd_size;
wire lsu2itcm_icb_rsp_valid;
wire lsu2itcm_icb_rsp_ready;
wire lsu2itcm_icb_rsp_err ;
wire [`E203_XLEN-1:0] lsu2itcm_icb_rsp_rdata;
`endif//}
`ifdef E203_HAS_DTCM //{
wire lsu2dtcm_icb_cmd_valid;
wire lsu2dtcm_icb_cmd_ready;
wire [`E203_DTCM_ADDR_WIDTH-1:0] lsu2dtcm_icb_cmd_addr;
wire lsu2dtcm_icb_cmd_read;
wire [`E203_XLEN-1:0] lsu2dtcm_icb_cmd_wdata;
wire [`E203_XLEN/8-1:0] lsu2dtcm_icb_cmd_wmask;
wire lsu2dtcm_icb_cmd_lock;
wire lsu2dtcm_icb_cmd_excl;
wire [1:0] lsu2dtcm_icb_cmd_size;
wire lsu2dtcm_icb_rsp_valid;
wire lsu2dtcm_icb_rsp_ready;
wire lsu2dtcm_icb_rsp_err ;
wire [`E203_XLEN-1:0] lsu2dtcm_icb_rsp_rdata;
`endif//}
`ifdef E203_HAS_CSR_EAI//{
wire eai_csr_valid;
wire eai_csr_ready;
wire [31:0] eai_csr_addr;
wire eai_csr_wr;
wire [31:0] eai_csr_wdata;
wire [31:0] eai_csr_rdata;
// This is an empty module to just connect the EAI CSR interface,
// user can hack it to become a real one
e203_extend_csr u_e203_extend_csr(
.eai_csr_valid (eai_csr_valid),
.eai_csr_ready (eai_csr_ready),
.eai_csr_addr (eai_csr_addr ),
.eai_csr_wr (eai_csr_wr ),
.eai_csr_wdata (eai_csr_wdata),
.eai_csr_rdata (eai_csr_rdata),
.clk (clk_core_exu ),
.rst_n (rst_core )
);
`endif//}
e203_core u_e203_core(
.inspect_pc (inspect_pc),
`ifdef E203_HAS_CSR_EAI//{
.eai_csr_valid (eai_csr_valid),
.eai_csr_ready (eai_csr_ready),
.eai_csr_addr (eai_csr_addr ),
.eai_csr_wr (eai_csr_wr ),
.eai_csr_wdata (eai_csr_wdata),
.eai_csr_rdata (eai_csr_rdata),
`endif//}
.tcm_cgstop (tcm_cgstop),
.core_cgstop (core_cgstop),
.tm_stop (tm_stop),
.pc_rtvec (pc_rtvec),
.ifu_active (core_ifu_active),
.exu_active (core_exu_active),
.lsu_active (core_lsu_active),
.biu_active (core_biu_active),
.core_wfi (core_wfi),
.core_mhartid (core_mhartid),
.dbg_irq_r (dbg_irq_r),
.lcl_irq_r (`E203_LIRQ_NUM'b0),// Not implemented now
.ext_irq_r (ext_irq_r),
.sft_irq_r (sft_irq_r),
.tmr_irq_r (tmr_irq_r),
.evt_r (`E203_EVT_NUM'b0),// Not implemented now
.cmt_dpc (cmt_dpc ),
.cmt_dpc_ena (cmt_dpc_ena ),
.cmt_dcause (cmt_dcause ),
.cmt_dcause_ena (cmt_dcause_ena ),
.wr_dcsr_ena (wr_dcsr_ena ),
.wr_dpc_ena (wr_dpc_ena ),
.wr_dscratch_ena (wr_dscratch_ena),
.wr_csr_nxt (wr_csr_nxt ),
.dcsr_r (dcsr_r ),
.dpc_r (dpc_r ),
.dscratch_r (dscratch_r ),
.dbg_mode (dbg_mode ),
.dbg_halt_r (dbg_halt_r ),
.dbg_step_r (dbg_step_r ),
.dbg_ebreakm_r (dbg_ebreakm_r),
.dbg_stopcycle (dbg_stopcycle),
`ifdef E203_HAS_ITCM //{
//.itcm_region_indic (itcm_region_indic),
.itcm_region_indic (`E203_ITCM_ADDR_BASE),
`endif//}
`ifdef E203_HAS_DTCM //{
//.dtcm_region_indic (dtcm_region_indic),
.dtcm_region_indic (`E203_DTCM_ADDR_BASE),
`endif//}
`ifdef E203_HAS_ITCM //{
.ifu2itcm_holdup (ifu2itcm_holdup ),
//.ifu2itcm_replay (ifu2itcm_replay ),
.ifu2itcm_icb_cmd_valid (ifu2itcm_icb_cmd_valid),
.ifu2itcm_icb_cmd_ready (ifu2itcm_icb_cmd_ready),
.ifu2itcm_icb_cmd_addr (ifu2itcm_icb_cmd_addr ),
.ifu2itcm_icb_rsp_valid (ifu2itcm_icb_rsp_valid),
.ifu2itcm_icb_rsp_ready (ifu2itcm_icb_rsp_ready),
.ifu2itcm_icb_rsp_err (ifu2itcm_icb_rsp_err ),
.ifu2itcm_icb_rsp_rdata (ifu2itcm_icb_rsp_rdata),
.lsu2itcm_icb_cmd_valid (lsu2itcm_icb_cmd_valid),
.lsu2itcm_icb_cmd_ready (lsu2itcm_icb_cmd_ready),
.lsu2itcm_icb_cmd_addr (lsu2itcm_icb_cmd_addr ),
.lsu2itcm_icb_cmd_read (lsu2itcm_icb_cmd_read ),
.lsu2itcm_icb_cmd_wdata (lsu2itcm_icb_cmd_wdata),
.lsu2itcm_icb_cmd_wmask (lsu2itcm_icb_cmd_wmask),
.lsu2itcm_icb_cmd_lock (lsu2itcm_icb_cmd_lock ),
.lsu2itcm_icb_cmd_excl (lsu2itcm_icb_cmd_excl ),
.lsu2itcm_icb_cmd_size (lsu2itcm_icb_cmd_size ),
.lsu2itcm_icb_rsp_valid (lsu2itcm_icb_rsp_valid),
.lsu2itcm_icb_rsp_ready (lsu2itcm_icb_rsp_ready),
.lsu2itcm_icb_rsp_err (lsu2itcm_icb_rsp_err ),
.lsu2itcm_icb_rsp_excl_ok(1'b0),
.lsu2itcm_icb_rsp_rdata (lsu2itcm_icb_rsp_rdata),
`endif//}
`ifdef E203_HAS_DTCM //{
.lsu2dtcm_icb_cmd_valid (lsu2dtcm_icb_cmd_valid),
.lsu2dtcm_icb_cmd_ready (lsu2dtcm_icb_cmd_ready),
.lsu2dtcm_icb_cmd_addr (lsu2dtcm_icb_cmd_addr ),
.lsu2dtcm_icb_cmd_read (lsu2dtcm_icb_cmd_read ),
.lsu2dtcm_icb_cmd_wdata (lsu2dtcm_icb_cmd_wdata),
.lsu2dtcm_icb_cmd_wmask (lsu2dtcm_icb_cmd_wmask),
.lsu2dtcm_icb_cmd_lock (lsu2dtcm_icb_cmd_lock ),
.lsu2dtcm_icb_cmd_excl (lsu2dtcm_icb_cmd_excl ),
.lsu2dtcm_icb_cmd_size (lsu2dtcm_icb_cmd_size ),
.lsu2dtcm_icb_rsp_valid (lsu2dtcm_icb_rsp_valid),
.lsu2dtcm_icb_rsp_ready (lsu2dtcm_icb_rsp_ready),
.lsu2dtcm_icb_rsp_err (lsu2dtcm_icb_rsp_err ),
.lsu2dtcm_icb_rsp_excl_ok(1'b0),
.lsu2dtcm_icb_rsp_rdata (lsu2dtcm_icb_rsp_rdata),
`endif//}
.ppi_icb_enable (ppi_icb_enable),
.ppi_region_indic (ppi_region_indic ),
.ppi_icb_cmd_valid (ppi_icb_cmd_valid),
.ppi_icb_cmd_ready (ppi_icb_cmd_ready),
.ppi_icb_cmd_addr (ppi_icb_cmd_addr ),
.ppi_icb_cmd_read (ppi_icb_cmd_read ),
.ppi_icb_cmd_wdata (ppi_icb_cmd_wdata),
.ppi_icb_cmd_wmask (ppi_icb_cmd_wmask),
.ppi_icb_cmd_lock (ppi_icb_cmd_lock ),
.ppi_icb_cmd_excl (ppi_icb_cmd_excl ),
.ppi_icb_cmd_size (ppi_icb_cmd_size ),
.ppi_icb_rsp_valid (ppi_icb_rsp_valid),
.ppi_icb_rsp_ready (ppi_icb_rsp_ready),
.ppi_icb_rsp_err (ppi_icb_rsp_err ),
.ppi_icb_rsp_excl_ok (ppi_icb_rsp_excl_ok),
.ppi_icb_rsp_rdata (ppi_icb_rsp_rdata),
.plic_icb_enable (plic_icb_enable),
.plic_region_indic (plic_region_indic ),
.plic_icb_cmd_valid (plic_icb_cmd_valid),
.plic_icb_cmd_ready (plic_icb_cmd_ready),
.plic_icb_cmd_addr (plic_icb_cmd_addr ),
.plic_icb_cmd_read (plic_icb_cmd_read ),
.plic_icb_cmd_wdata (plic_icb_cmd_wdata),
.plic_icb_cmd_wmask (plic_icb_cmd_wmask),
.plic_icb_cmd_lock (plic_icb_cmd_lock ),
.plic_icb_cmd_excl (plic_icb_cmd_excl ),
.plic_icb_cmd_size (plic_icb_cmd_size ),
.plic_icb_rsp_valid (plic_icb_rsp_valid),
.plic_icb_rsp_ready (plic_icb_rsp_ready),
.plic_icb_rsp_err (plic_icb_rsp_err ),
.plic_icb_rsp_excl_ok (plic_icb_rsp_excl_ok),
.plic_icb_rsp_rdata (plic_icb_rsp_rdata),
.clint_icb_enable (clint_icb_enable),
.clint_region_indic (clint_region_indic ),
.clint_icb_cmd_valid (clint_icb_cmd_valid),
.clint_icb_cmd_ready (clint_icb_cmd_ready),
.clint_icb_cmd_addr (clint_icb_cmd_addr ),
.clint_icb_cmd_read (clint_icb_cmd_read ),
.clint_icb_cmd_wdata (clint_icb_cmd_wdata),
.clint_icb_cmd_wmask (clint_icb_cmd_wmask),
.clint_icb_cmd_lock (clint_icb_cmd_lock ),
.clint_icb_cmd_excl (clint_icb_cmd_excl ),
.clint_icb_cmd_size (clint_icb_cmd_size ),
.clint_icb_rsp_valid (clint_icb_rsp_valid),
.clint_icb_rsp_ready (clint_icb_rsp_ready),
.clint_icb_rsp_err (clint_icb_rsp_err ),
.clint_icb_rsp_excl_ok (clint_icb_rsp_excl_ok),
.clint_icb_rsp_rdata (clint_icb_rsp_rdata),
`ifdef E203_HAS_FIO //{
.fio_icb_enable (fio_icb_enable),
.fio_region_indic (fio_region_indic ),
.fio_icb_cmd_valid (fio_icb_cmd_valid),
.fio_icb_cmd_ready (fio_icb_cmd_ready),
.fio_icb_cmd_addr (fio_icb_cmd_addr ),
.fio_icb_cmd_read (fio_icb_cmd_read ),
.fio_icb_cmd_wdata (fio_icb_cmd_wdata),
.fio_icb_cmd_wmask (fio_icb_cmd_wmask),
.fio_icb_cmd_lock (fio_icb_cmd_lock ),
.fio_icb_cmd_excl (fio_icb_cmd_excl ),
.fio_icb_cmd_size (fio_icb_cmd_size ),
.fio_icb_rsp_valid (fio_icb_rsp_valid),
.fio_icb_rsp_ready (fio_icb_rsp_ready),
.fio_icb_rsp_err (fio_icb_rsp_err ),
.fio_icb_rsp_excl_ok (fio_icb_rsp_excl_ok),
.fio_icb_rsp_rdata (fio_icb_rsp_rdata),
`endif//}
`ifdef E203_HAS_MEM_ITF //{
.mem_icb_enable (mem_icb_enable),
.mem_icb_cmd_valid (mem_icb_cmd_valid),
.mem_icb_cmd_ready (mem_icb_cmd_ready),
.mem_icb_cmd_addr (mem_icb_cmd_addr ),
.mem_icb_cmd_read (mem_icb_cmd_read ),
.mem_icb_cmd_wdata (mem_icb_cmd_wdata),
.mem_icb_cmd_wmask (mem_icb_cmd_wmask),
.mem_icb_cmd_lock (mem_icb_cmd_lock ),
.mem_icb_cmd_excl (mem_icb_cmd_excl ),
.mem_icb_cmd_size (mem_icb_cmd_size ),
.mem_icb_cmd_burst (mem_icb_cmd_burst ),
.mem_icb_cmd_beat (mem_icb_cmd_beat ),
.mem_icb_rsp_valid (mem_icb_rsp_valid),
.mem_icb_rsp_ready (mem_icb_rsp_ready),
.mem_icb_rsp_err (mem_icb_rsp_err ),
.mem_icb_rsp_excl_ok(mem_icb_rsp_excl_ok ),
.mem_icb_rsp_rdata (mem_icb_rsp_rdata),
`endif//}
.clk_aon (clk_aon ),
.clk_core_ifu (clk_core_ifu ),
.clk_core_exu (clk_core_exu ),
.clk_core_lsu (clk_core_lsu ),
.clk_core_biu (clk_core_biu ),
.test_mode (test_mode),
.rst_n (rst_core )
);
`ifdef E203_HAS_ITCM //{
e203_itcm_ctrl u_e203_itcm_ctrl(
.tcm_cgstop (tcm_cgstop),
.itcm_active (itcm_active),
.ifu2itcm_icb_cmd_valid (ifu2itcm_icb_cmd_valid),
.ifu2itcm_icb_cmd_ready (ifu2itcm_icb_cmd_ready),
.ifu2itcm_icb_cmd_addr (ifu2itcm_icb_cmd_addr ),
.ifu2itcm_icb_cmd_read (1'b1 ),
.ifu2itcm_icb_cmd_wdata ({`E203_ITCM_DATA_WIDTH{1'b0}}),
.ifu2itcm_icb_cmd_wmask ({`E203_ITCM_DATA_WIDTH/8{1'b0}}),
.ifu2itcm_icb_rsp_valid (ifu2itcm_icb_rsp_valid),
.ifu2itcm_icb_rsp_ready (ifu2itcm_icb_rsp_ready),
.ifu2itcm_icb_rsp_err (ifu2itcm_icb_rsp_err ),
.ifu2itcm_icb_rsp_rdata (ifu2itcm_icb_rsp_rdata),
.ifu2itcm_holdup (ifu2itcm_holdup ),
//.ifu2itcm_replay (ifu2itcm_replay ),
.lsu2itcm_icb_cmd_valid (lsu2itcm_icb_cmd_valid),
.lsu2itcm_icb_cmd_ready (lsu2itcm_icb_cmd_ready),
.lsu2itcm_icb_cmd_addr (lsu2itcm_icb_cmd_addr ),
.lsu2itcm_icb_cmd_read (lsu2itcm_icb_cmd_read ),
.lsu2itcm_icb_cmd_wdata (lsu2itcm_icb_cmd_wdata),
.lsu2itcm_icb_cmd_wmask (lsu2itcm_icb_cmd_wmask),
.lsu2itcm_icb_rsp_valid (lsu2itcm_icb_rsp_valid),
.lsu2itcm_icb_rsp_ready (lsu2itcm_icb_rsp_ready),
.lsu2itcm_icb_rsp_err (lsu2itcm_icb_rsp_err ),
.lsu2itcm_icb_rsp_rdata (lsu2itcm_icb_rsp_rdata),
.itcm_ram_cs (itcm_ram_cs ),
.itcm_ram_we (itcm_ram_we ),
.itcm_ram_addr (itcm_ram_addr),
.itcm_ram_wem (itcm_ram_wem ),
.itcm_ram_din (itcm_ram_din ),
.itcm_ram_dout (itcm_ram_dout),
.clk_itcm_ram (clk_itcm_ram ),
`ifdef E203_HAS_ITCM_EXTITF //{
.ext2itcm_icb_cmd_valid (ext2itcm_icb_cmd_valid),
.ext2itcm_icb_cmd_ready (ext2itcm_icb_cmd_ready),
.ext2itcm_icb_cmd_addr (ext2itcm_icb_cmd_addr ),
.ext2itcm_icb_cmd_read (ext2itcm_icb_cmd_read ),
.ext2itcm_icb_cmd_wdata (ext2itcm_icb_cmd_wdata),
.ext2itcm_icb_cmd_wmask (ext2itcm_icb_cmd_wmask),
.ext2itcm_icb_rsp_valid (ext2itcm_icb_rsp_valid),
.ext2itcm_icb_rsp_ready (ext2itcm_icb_rsp_ready),
.ext2itcm_icb_rsp_err (ext2itcm_icb_rsp_err ),
.ext2itcm_icb_rsp_rdata (ext2itcm_icb_rsp_rdata),
`endif//}
.test_mode (test_mode),
.clk (clk_itcm),
.rst_n (rst_itcm)
);
`endif//}
`ifdef E203_HAS_DTCM //{
e203_dtcm_ctrl u_e203_dtcm_ctrl(
.tcm_cgstop (tcm_cgstop),
.dtcm_active (dtcm_active),
.lsu2dtcm_icb_cmd_valid (lsu2dtcm_icb_cmd_valid),
.lsu2dtcm_icb_cmd_ready (lsu2dtcm_icb_cmd_ready),
.lsu2dtcm_icb_cmd_addr (lsu2dtcm_icb_cmd_addr ),
.lsu2dtcm_icb_cmd_read (lsu2dtcm_icb_cmd_read ),
.lsu2dtcm_icb_cmd_wdata (lsu2dtcm_icb_cmd_wdata),
.lsu2dtcm_icb_cmd_wmask (lsu2dtcm_icb_cmd_wmask),
.lsu2dtcm_icb_rsp_valid (lsu2dtcm_icb_rsp_valid),
.lsu2dtcm_icb_rsp_ready (lsu2dtcm_icb_rsp_ready),
.lsu2dtcm_icb_rsp_err (lsu2dtcm_icb_rsp_err ),
.lsu2dtcm_icb_rsp_rdata (lsu2dtcm_icb_rsp_rdata),
.dtcm_ram_cs (dtcm_ram_cs ),
.dtcm_ram_we (dtcm_ram_we ),
.dtcm_ram_addr (dtcm_ram_addr),
.dtcm_ram_wem (dtcm_ram_wem ),
.dtcm_ram_din (dtcm_ram_din ),
.dtcm_ram_dout (dtcm_ram_dout),
.clk_dtcm_ram (clk_dtcm_ram ),
`ifdef E203_HAS_DTCM_EXTITF //{
.ext2dtcm_icb_cmd_valid (ext2dtcm_icb_cmd_valid),
.ext2dtcm_icb_cmd_ready (ext2dtcm_icb_cmd_ready),
.ext2dtcm_icb_cmd_addr (ext2dtcm_icb_cmd_addr ),
.ext2dtcm_icb_cmd_read (ext2dtcm_icb_cmd_read ),
.ext2dtcm_icb_cmd_wdata (ext2dtcm_icb_cmd_wdata),
.ext2dtcm_icb_cmd_wmask (ext2dtcm_icb_cmd_wmask),
.ext2dtcm_icb_rsp_valid (ext2dtcm_icb_rsp_valid),
.ext2dtcm_icb_rsp_ready (ext2dtcm_icb_rsp_ready),
.ext2dtcm_icb_rsp_err (ext2dtcm_icb_rsp_err ),
.ext2dtcm_icb_rsp_rdata (ext2dtcm_icb_rsp_rdata),
`endif//}
.test_mode (test_mode),
.clk (clk_dtcm),
.rst_n (rst_dtcm)
);
`endif//}
assign inspect_dbg_irq = dbg_irq_a;
assign inspect_mem_cmd_valid = mem_icb_cmd_valid;
assign inspect_mem_cmd_ready = mem_icb_cmd_ready;
assign inspect_mem_rsp_valid = mem_icb_rsp_valid;
assign inspect_mem_rsp_ready = mem_icb_rsp_ready;
assign inspect_core_clk = clk;
assign core_csr_clk = clk_core_exu;
endmodule
|
module sirv_mrom # (
parameter AW = 12,
parameter DW = 32,
parameter DP = 1024
)(
input [AW-1:2] rom_addr,
output [DW-1:0] rom_dout
);
wire [31:0] mask_rom [0:DP-1];// 4KB = 1KW
assign rom_dout = mask_rom[rom_addr];
/*
assign mask_rom[ 0] = 32'h0280006f;
assign mask_rom[ 1] = 32'h00000013;
assign mask_rom[ 2] = 32'h00000013;
assign mask_rom[ 3] = 32'h00000013;
assign mask_rom[ 4] = 32'h00000013;
assign mask_rom[ 5] = 32'h00000013;
assign mask_rom[ 6] = 32'h00000013;
assign mask_rom[ 7] = 32'h00000013;
assign mask_rom[ 8] = 32'h00000013;
assign mask_rom[ 9] = 32'h00000013;
assign mask_rom[10] = 32'h00700093;
assign mask_rom[11] = 32'h10012137;
assign mask_rom[12] = 32'h00810113;
assign mask_rom[13] = 32'h00112023;
assign mask_rom[14] = 32'h00000193;
assign mask_rom[15] = 32'h00100293;
assign mask_rom[16] = 32'h00500093;
assign mask_rom[17] = 32'h10012137;
assign mask_rom[18] = 32'h00c10113;
assign mask_rom[19] = 32'h00112023;
assign mask_rom[20] = 32'h00150237;
assign mask_rom[21] = 32'h40520233;
assign mask_rom[22] = 32'hfe321ee3;
assign mask_rom[23] = 32'h00000093;
assign mask_rom[24] = 32'h10012137;
assign mask_rom[25] = 32'h00c10113;
assign mask_rom[26] = 32'h00112023;
assign mask_rom[27] = 32'h00150237;
assign mask_rom[28] = 32'h40520233;
assign mask_rom[29] = 32'hfe321ee3;
assign mask_rom[30] = 32'hfc1ff06f;
assign mask_rom[31] = 32'h00000013;
assign mask_rom[32] = 32'h00000013;
*/
genvar i;
generate
if(1) begin: jump_to_ram_gen
// Just jump to the ITCM base address
for (i=0;i<1024;i=i+1) begin: rom_gen
if(i==0) begin: rom0_gen
assign mask_rom[i] = 32'h7ffff297; //auipc t0, 0x7ffff
end
else if(i==1) begin: rom1_gen
assign mask_rom[i] = 32'h00028067; //jr t0
end
else begin: rom_non01_gen
assign mask_rom[i] = 32'h00000013;
end
end
end
else begin: jump_to_non_ram_gen
// This is the freedom bootrom version, put here have a try
// The actual executed trace is as below:
// CYC: 8615 PC:00001000 IR:0100006f DASM: j pc + 0x10
// CYC: 8618 PC:00001010 IR:204002b7 DASM: lui t0, 0x20400 xpr[5] = 0x20400000
// CYC: 8621 PC:00001014 IR:00028067 DASM: jr t0
// The 20400000 is the flash address
//MEMORY
//{
// flash (rxai!w) : ORIGIN = 0x20400000, LENGTH = 512M
// ram (wxa!ri) : ORIGIN = 0x80000000, LENGTH = 16K
//}
for (i=0;i<1024;i=i+1) begin: rom_gen
if(i==0) begin: rom0_gen
assign mask_rom[i] = 32'h100006f;
end
else if(i==1) begin: rom1_gen
assign mask_rom[i] = 32'h13;
end
else if(i==2) begin: rom1_gen
assign mask_rom[i] = 32'h13;
end
else if(i==3) begin: rom1_gen
assign mask_rom[i] = 32'h6661;// our config code
end
else if(i==4) begin: rom1_gen
//assign mask_rom[i] = 32'h204002b7;
assign mask_rom[i] = 32'h20400000 | 32'h000002b7;
end
else if(i==5) begin: rom1_gen
assign mask_rom[i] = 32'h28067;
end
else begin: rom_non01_gen
assign mask_rom[i] = 32'h00000000;
end
end
// In the https://github.com/sifive/freedom/blob/master/bootrom/xip/xip.S
// ASM code is as below:
// // // See LICENSE for license details.
//// Execute in place
//// Jump directly to XIP_TARGET_ADDR
//
// .text
// .option norvc
// .globl _start
//_start:
// j 1f
// nop
// nop
//#ifdef CONFIG_STRING
// .word cfg_string
//#else
// .word 0 // Filled in by GenerateBootROM in Chisel
//#endif
//
//1:
// li t0, XIP_TARGET_ADDR
// jr t0
//
// .section .rodata
//#ifdef CONFIG_STRING
//cfg_string:
// .incbin CONFIG_STRING
//#endif
end
endgenerate
endmodule
|
module e203_exu_alu_lsuagu(
//////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////
// The Issue Handshake Interface to AGU
//
input agu_i_valid, // Handshake valid
output agu_i_ready, // Handshake ready
input [`E203_XLEN-1:0] agu_i_rs1,
input [`E203_XLEN-1:0] agu_i_rs2,
input [`E203_XLEN-1:0] agu_i_imm,
input [`E203_DECINFO_AGU_WIDTH-1:0] agu_i_info,
input [`E203_ITAG_WIDTH-1:0] agu_i_itag,
output agu_i_longpipe,
input flush_req,
input flush_pulse,
output amo_wait,
input oitf_empty,
//////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////
// The AGU Write-Back/Commit Interface
output agu_o_valid, // Handshake valid
input agu_o_ready, // Handshake ready
output [`E203_XLEN-1:0] agu_o_wbck_wdat,
output agu_o_wbck_err,
// The Commit Interface for all ldst and amo instructions
output agu_o_cmt_misalgn, // The misalign exception generated
output agu_o_cmt_ld,
output agu_o_cmt_stamo,
output agu_o_cmt_buserr, // The bus-error exception generated
output [`E203_ADDR_SIZE-1:0] agu_o_cmt_badaddr,
//////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////
// The ICB Interface to LSU-ctrl
// * Bus cmd channel
output agu_icb_cmd_valid, // Handshake valid
input agu_icb_cmd_ready, // Handshake ready
// Note: The data on rdata or wdata channel must be naturally
// aligned, this is in line with the AXI definition
output [`E203_ADDR_SIZE-1:0] agu_icb_cmd_addr, // Bus transaction start addr
output agu_icb_cmd_read, // Read or write
output [`E203_XLEN-1:0] agu_icb_cmd_wdata,
output [`E203_XLEN/8-1:0] agu_icb_cmd_wmask,
output agu_icb_cmd_back2agu,
output agu_icb_cmd_lock,
output agu_icb_cmd_excl,
output [1:0] agu_icb_cmd_size,
output [`E203_ITAG_WIDTH-1:0]agu_icb_cmd_itag,
output agu_icb_cmd_usign,
// * Bus RSP channel
input agu_icb_rsp_valid, // Response valid
output agu_icb_rsp_ready, // Response ready
input agu_icb_rsp_err , // Response error
input agu_icb_rsp_excl_ok,
// Note: the RSP rdata is inline with AXI definition
input [`E203_XLEN-1:0] agu_icb_rsp_rdata,
//////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////
// To share the ALU datapath, generate interface to ALU
// for single-issue machine, seems the AGU must be shared with ALU, otherwise
// it wasted the area for no points
//
// The operands and info to ALU
output [`E203_XLEN-1:0] agu_req_alu_op1,
output [`E203_XLEN-1:0] agu_req_alu_op2,
output agu_req_alu_swap,
output agu_req_alu_add ,
output agu_req_alu_and ,
output agu_req_alu_or ,
output agu_req_alu_xor ,
output agu_req_alu_max ,
output agu_req_alu_min ,
output agu_req_alu_maxu,
output agu_req_alu_minu,
input [`E203_XLEN-1:0] agu_req_alu_res,
// The Shared-Buffer interface to ALU-Shared-Buffer
output agu_sbf_0_ena,
output [`E203_XLEN-1:0] agu_sbf_0_nxt,
input [`E203_XLEN-1:0] agu_sbf_0_r,
output agu_sbf_1_ena,
output [`E203_XLEN-1:0] agu_sbf_1_nxt,
input [`E203_XLEN-1:0] agu_sbf_1_r,
input clk,
input rst_n
);
//
// When there is a nonalu_flush which is going to flush the ALU, then we need to mask off it
wire icb_sta_is_idle;
wire flush_block = flush_req & icb_sta_is_idle;
wire agu_i_load = agu_i_info [`E203_DECINFO_AGU_LOAD ] & (~flush_block);
wire agu_i_store = agu_i_info [`E203_DECINFO_AGU_STORE ] & (~flush_block);
wire agu_i_amo = agu_i_info [`E203_DECINFO_AGU_AMO ] & (~flush_block);
wire [1:0] agu_i_size = agu_i_info [`E203_DECINFO_AGU_SIZE ];
wire agu_i_usign = agu_i_info [`E203_DECINFO_AGU_USIGN ];
wire agu_i_excl = agu_i_info [`E203_DECINFO_AGU_EXCL ];
wire agu_i_amoswap = agu_i_info [`E203_DECINFO_AGU_AMOSWAP];
wire agu_i_amoadd = agu_i_info [`E203_DECINFO_AGU_AMOADD ];
wire agu_i_amoand = agu_i_info [`E203_DECINFO_AGU_AMOAND ];
wire agu_i_amoor = agu_i_info [`E203_DECINFO_AGU_AMOOR ];
wire agu_i_amoxor = agu_i_info [`E203_DECINFO_AGU_AMOXOR ];
wire agu_i_amomax = agu_i_info [`E203_DECINFO_AGU_AMOMAX ];
wire agu_i_amomin = agu_i_info [`E203_DECINFO_AGU_AMOMIN ];
wire agu_i_amomaxu = agu_i_info [`E203_DECINFO_AGU_AMOMAXU];
wire agu_i_amominu = agu_i_info [`E203_DECINFO_AGU_AMOMINU];
wire agu_icb_cmd_hsked = agu_icb_cmd_valid & agu_icb_cmd_ready;
`ifdef E203_SUPPORT_AMO//{
wire agu_icb_rsp_hsked = agu_icb_rsp_valid & agu_icb_rsp_ready;
`endif//E203_SUPPORT_AMO}
// These strange ifdef/ifndef rather than the ifdef-else, because of
// our internal text processing scripts need this style
`ifndef E203_SUPPORT_AMO//{
`ifndef E203_SUPPORT_UNALGNLDST//{
wire agu_icb_rsp_hsked = 1'b0;
`endif//}
`endif//}
wire agu_i_size_b = (agu_i_size == 2'b00);
wire agu_i_size_hw = (agu_i_size == 2'b01);
wire agu_i_size_w = (agu_i_size == 2'b10);
wire agu_i_addr_unalgn =
(agu_i_size_hw & agu_icb_cmd_addr[0])
| (agu_i_size_w & (|agu_icb_cmd_addr[1:0]));
wire state_last_exit_ena;
`ifdef E203_SUPPORT_AMO//{
wire state_idle_exit_ena;
wire unalgn_flg_r;
// Set when the ICB state is starting and it is unalign
wire unalgn_flg_set = agu_i_addr_unalgn & state_idle_exit_ena;
// Clear when the ICB state is entering
wire unalgn_flg_clr = unalgn_flg_r & state_last_exit_ena;
wire unalgn_flg_ena = unalgn_flg_set | unalgn_flg_clr;
wire unalgn_flg_nxt = unalgn_flg_set | (~unalgn_flg_clr);
sirv_gnrl_dfflr #(1) unalgn_flg_dffl (unalgn_flg_ena, unalgn_flg_nxt, unalgn_flg_r, clk, rst_n);
`endif//E203_SUPPORT_AMO}
wire agu_addr_unalgn =
`ifndef E203_SUPPORT_UNALGNLDST//{
`ifdef E203_SUPPORT_AMO//{
icb_sta_is_idle ? agu_i_addr_unalgn : unalgn_flg_r;
`endif//E203_SUPPORT_AMO}
`ifndef E203_SUPPORT_AMO//{
agu_i_addr_unalgn;
`endif//}
`endif//}
wire agu_i_unalgnld = (agu_addr_unalgn & agu_i_load)
;
wire agu_i_unalgnst = (agu_addr_unalgn & agu_i_store)
;
wire agu_i_unalgnldst = (agu_i_unalgnld | agu_i_unalgnst)
;
wire agu_i_algnld = (~agu_addr_unalgn) & agu_i_load
;
wire agu_i_algnst = (~agu_addr_unalgn) & agu_i_store
;
wire agu_i_algnldst = (agu_i_algnld | agu_i_algnst)
;
`ifdef E203_SUPPORT_AMO//{
wire agu_i_unalgnamo = (agu_addr_unalgn & agu_i_amo)
;
wire agu_i_algnamo = ((~agu_addr_unalgn) & agu_i_amo)
;
`endif//E203_SUPPORT_AMO}
wire agu_i_ofst0 = agu_i_amo | ((agu_i_load | agu_i_store) & agu_i_excl);
localparam ICB_STATE_WIDTH = 4;
wire icb_state_ena;
wire [ICB_STATE_WIDTH-1:0] icb_state_nxt;
wire [ICB_STATE_WIDTH-1:0] icb_state_r;
// State 0: The idle state, means there is no any oustanding ifetch request
localparam ICB_STATE_IDLE = 4'd0;
`ifdef E203_SUPPORT_AMO//{
// State : Issued first request and wait response
localparam ICB_STATE_1ST = 4'd1;
// State : Wait to issue second request
localparam ICB_STATE_WAIT2ND = 4'd2;
// State : Issued second request and wait response
localparam ICB_STATE_2ND = 4'd3;
// State : For AMO instructions, in this state, read-data was in leftover
// buffer for ALU calculation
localparam ICB_STATE_AMOALU = 4'd4;
// State : For AMO instructions, in this state, ALU have caculated the new
// result and put into leftover buffer again
localparam ICB_STATE_AMORDY = 4'd5;
// State : For AMO instructions, in this state, the response data have been returned
// and the write back result to commit/wback interface
localparam ICB_STATE_WBCK = 4'd6;
`endif//E203_SUPPORT_AMO}
`ifdef E203_SUPPORT_AMO//{
wire [ICB_STATE_WIDTH-1:0] state_idle_nxt ;
wire [ICB_STATE_WIDTH-1:0] state_1st_nxt ;
wire [ICB_STATE_WIDTH-1:0] state_wait2nd_nxt;
wire [ICB_STATE_WIDTH-1:0] state_2nd_nxt ;
wire [ICB_STATE_WIDTH-1:0] state_amoalu_nxt ;
wire [ICB_STATE_WIDTH-1:0] state_amordy_nxt ;
wire [ICB_STATE_WIDTH-1:0] state_wbck_nxt ;
`endif//E203_SUPPORT_AMO}
`ifdef E203_SUPPORT_AMO//{
wire state_1st_exit_ena ;
wire state_wait2nd_exit_ena ;
wire state_2nd_exit_ena ;
wire state_amoalu_exit_ena ;
wire state_amordy_exit_ena ;
wire state_wbck_exit_ena ;
`endif//E203_SUPPORT_AMO}
// Define some common signals and reused later to save gatecounts
assign icb_sta_is_idle = (icb_state_r == ICB_STATE_IDLE );
`ifdef E203_SUPPORT_AMO//{
wire icb_sta_is_1st = (icb_state_r == ICB_STATE_1ST );
wire icb_sta_is_amoalu = (icb_state_r == ICB_STATE_AMOALU );
wire icb_sta_is_amordy = (icb_state_r == ICB_STATE_AMORDY );
wire icb_sta_is_wait2nd = (icb_state_r == ICB_STATE_WAIT2ND);
wire icb_sta_is_2nd = (icb_state_r == ICB_STATE_2ND );
wire icb_sta_is_wbck = (icb_state_r == ICB_STATE_WBCK );
`endif//E203_SUPPORT_AMO}
`ifdef E203_SUPPORT_AMO//{
// **** If the current state is idle,
// If a new load-store come and the ICB cmd channel is handshaked, next
// state is ICB_STATE_1ST
wire state_idle_to_exit = (( agu_i_algnamo
// Why do we add an oitf empty signal here? because
// it is better to start AMO state-machine when the
// long-pipes are completed, to avoid the long-pipes
// have error-return which need to flush the pipeline
// and which also need to wait the AMO state-machine
// to complete first, in corner cases it may end
// up with deadlock.
// Force to wait oitf empty before doing amo state-machine
// may hurt performance, but we dont care it. In e200 implementation
// the AMO was not target for performance.
& oitf_empty)
);
assign state_idle_exit_ena = icb_sta_is_idle & state_idle_to_exit
& agu_icb_cmd_hsked & (~flush_pulse);
assign state_idle_nxt = ICB_STATE_1ST;
// **** If the current state is 1st,
// If a response come, exit this state
assign state_1st_exit_ena = icb_sta_is_1st & (agu_icb_rsp_hsked | flush_pulse);
assign state_1st_nxt = flush_pulse ? ICB_STATE_IDLE :
(
// (agu_i_algnamo) ? // No need this condition, because it will be either
// amo or unalgn load-store in this state
ICB_STATE_AMOALU
);
// **** If the current state is AMOALU
// Since the ALU is must be holdoff now, it can always be
// served and then enter into next state
assign state_amoalu_exit_ena = icb_sta_is_amoalu & ( 1'b1 | flush_pulse);
assign state_amoalu_nxt = flush_pulse ? ICB_STATE_IDLE : ICB_STATE_AMORDY;
// **** If the current state is AMORDY
// It always enter into next state
assign state_amordy_exit_ena = icb_sta_is_amordy & ( 1'b1 | flush_pulse);
assign state_amordy_nxt = flush_pulse ? ICB_STATE_IDLE :
(
// AMO after caculated read-modify-result, need to issue 2nd uop as store
// back to memory, hence two ICB needed and we dont care the performance,
// so always let it jump to wait2nd state
ICB_STATE_WAIT2ND
);
// **** If the current state is wait-2nd,
assign state_wait2nd_exit_ena = icb_sta_is_wait2nd & (agu_icb_cmd_ready | flush_pulse);
// If the ICB CMD is ready, then next state is ICB_STATE_2ND
assign state_wait2nd_nxt = flush_pulse ? ICB_STATE_IDLE : ICB_STATE_2ND;
// **** If the current state is 2nd,
// If a response come, exit this state
assign state_2nd_exit_ena = icb_sta_is_2nd & (agu_icb_rsp_hsked | flush_pulse);
assign state_2nd_nxt = flush_pulse ? ICB_STATE_IDLE :
(
ICB_STATE_WBCK
);
// **** If the current state is wbck,
// If it can be write back, exit this state
assign state_wbck_exit_ena = icb_sta_is_wbck & (agu_o_ready | flush_pulse);
assign state_wbck_nxt = flush_pulse ? ICB_STATE_IDLE :
(
ICB_STATE_IDLE
);
`endif//E203_SUPPORT_AMO}
// The state will only toggle when each state is meeting the condition to exit:
assign icb_state_ena = 1'b0
`ifdef E203_SUPPORT_AMO//{
| state_idle_exit_ena | state_1st_exit_ena
| state_amoalu_exit_ena | state_amordy_exit_ena
| state_wait2nd_exit_ena | state_2nd_exit_ena
| state_wbck_exit_ena
`endif//E203_SUPPORT_AMO}
;
// The next-state is onehot mux to select different entries
assign icb_state_nxt =
({ICB_STATE_WIDTH{1'b0}})
`ifdef E203_SUPPORT_AMO//{
| ({ICB_STATE_WIDTH{state_idle_exit_ena }} & state_idle_nxt )
| ({ICB_STATE_WIDTH{state_1st_exit_ena }} & state_1st_nxt )
| ({ICB_STATE_WIDTH{state_amoalu_exit_ena }} & state_amoalu_nxt )
| ({ICB_STATE_WIDTH{state_amordy_exit_ena }} & state_amordy_nxt )
| ({ICB_STATE_WIDTH{state_wait2nd_exit_ena}} & state_wait2nd_nxt)
| ({ICB_STATE_WIDTH{state_2nd_exit_ena }} & state_2nd_nxt )
| ({ICB_STATE_WIDTH{state_wbck_exit_ena }} & state_wbck_nxt )
`endif//E203_SUPPORT_AMO}
;
sirv_gnrl_dfflr #(ICB_STATE_WIDTH) icb_state_dfflr (icb_state_ena, icb_state_nxt, icb_state_r, clk, rst_n);
`ifdef E203_SUPPORT_AMO//{
wire icb_sta_is_last = icb_sta_is_wbck;
`endif//E203_SUPPORT_AMO}
`ifndef E203_SUPPORT_AMO//{
wire icb_sta_is_last = 1'b0;
`endif//}
`ifdef E203_SUPPORT_AMO//{
assign state_last_exit_ena = state_wbck_exit_ena;
`endif//E203_SUPPORT_AMO}
`ifndef E203_SUPPORT_AMO//{
assign state_last_exit_ena = 1'b0;
`endif//}
`ifndef E203_SUPPORT_UNALGNLDST//{
`else//}{
`ifndef E203_SUPPORT_AMO
!!!! ERROR: This config is not supported, must be something wrong
`endif//}
`endif//
// Indicate there is no oustanding memory transactions
`ifdef E203_SUPPORT_AMO//{
// As long as the statemachine started, we must wait it to be empty
// We cannot really kill this instruction when IRQ comes, becuase
// the AMO uop alreay write data into the memory, and we must commit
// this instructions
assign amo_wait = ~icb_sta_is_idle;
`endif//E203_SUPPORT_AMO}
`ifndef E203_SUPPORT_AMO//{
assign amo_wait = 1'b0;// If no AMO or UNaligned supported, then always 0
`endif//}
//
/////////////////////////////////////////////////////////////////////////////////
// Implement the leftover 0 buffer
wire leftover_ena;
wire [`E203_XLEN-1:0] leftover_nxt;
wire [`E203_XLEN-1:0] leftover_r;
wire leftover_err_nxt;
wire leftover_err_r;
wire [`E203_XLEN-1:0] leftover_1_r;
wire leftover_1_ena;
wire [`E203_XLEN-1:0] leftover_1_nxt;
//
`ifdef E203_SUPPORT_AMO//{
wire amo_1stuop = icb_sta_is_1st & agu_i_algnamo;
wire amo_2nduop = icb_sta_is_2nd & agu_i_algnamo;
`endif//E203_SUPPORT_AMO}
assign leftover_ena = agu_icb_rsp_hsked & (
1'b0
`ifdef E203_SUPPORT_AMO//{
| amo_1stuop
| amo_2nduop
`endif//E203_SUPPORT_AMO}
);
assign leftover_nxt =
{`E203_XLEN{1'b0}}
`ifdef E203_SUPPORT_AMO//{
| ({`E203_XLEN{amo_1stuop }} & agu_icb_rsp_rdata)// Load the data from bus
| ({`E203_XLEN{amo_2nduop }} & leftover_r)// Unchange the value of leftover_r
`endif//E203_SUPPORT_AMO}
;
assign leftover_err_nxt = 1'b0
`ifdef E203_SUPPORT_AMO//{
| ({{amo_1stuop }} & agu_icb_rsp_err)// 1st error from the bus
| ({{amo_2nduop }} & (agu_icb_rsp_err | leftover_err_r))// second error merged
`endif//E203_SUPPORT_AMO}
;
//
// The instantiation of leftover buffer is actually shared with the ALU SBF-0 Buffer
assign agu_sbf_0_ena = leftover_ena;
assign agu_sbf_0_nxt = leftover_nxt;
assign leftover_r = agu_sbf_0_r;
// The error bit is implemented here
sirv_gnrl_dfflr #(1) icb_leftover_err_dfflr (leftover_ena, leftover_err_nxt, leftover_err_r, clk, rst_n);
assign leftover_1_ena = 1'b0
`ifdef E203_SUPPORT_AMO//{
| icb_sta_is_amoalu
`endif//E203_SUPPORT_AMO}
;
assign leftover_1_nxt = agu_req_alu_res;
//
// The instantiation of last_icb_addr buffer is actually shared with the ALU SBF-1 Buffer
assign agu_sbf_1_ena = leftover_1_ena;
assign agu_sbf_1_nxt = leftover_1_nxt;
assign leftover_1_r = agu_sbf_1_r;
assign agu_req_alu_add = 1'b0
`ifdef E203_SUPPORT_AMO//{
| (icb_sta_is_amoalu & agu_i_amoadd)
// In order to let AMO 2nd uop have correct address
| (agu_i_amo & (icb_sta_is_wait2nd | icb_sta_is_2nd | icb_sta_is_wbck))
`endif//E203_SUPPORT_AMO}
// To cut down the timing loop from agu_i_valid // | (icb_sta_is_idle & agu_i_valid)
// we dont need this signal at all
| icb_sta_is_idle
;
assign agu_req_alu_op1 = icb_sta_is_idle ? agu_i_rs1
`ifdef E203_SUPPORT_AMO//{
: icb_sta_is_amoalu ? leftover_r
// In order to let AMO 2nd uop have correct address
: (agu_i_amo & (icb_sta_is_wait2nd | icb_sta_is_2nd | icb_sta_is_wbck)) ? agu_i_rs1
`endif//E203_SUPPORT_AMO}
`ifndef E203_SUPPORT_UNALGNLDST//{
: `E203_XLEN'd0
`endif//}
;
wire [`E203_XLEN-1:0] agu_addr_gen_op2 = agu_i_ofst0 ? `E203_XLEN'b0 : agu_i_imm;
assign agu_req_alu_op2 = icb_sta_is_idle ? agu_addr_gen_op2
`ifdef E203_SUPPORT_AMO//{
: icb_sta_is_amoalu ? agu_i_rs2
// In order to let AMO 2nd uop have correct address
: (agu_i_amo & (icb_sta_is_wait2nd | icb_sta_is_2nd | icb_sta_is_wbck)) ? agu_addr_gen_op2
`endif//E203_SUPPORT_AMO}
`ifndef E203_SUPPORT_UNALGNLDST//{
: `E203_XLEN'd0
`endif//}
;
`ifdef E203_SUPPORT_AMO//{
assign agu_req_alu_swap = (icb_sta_is_amoalu & agu_i_amoswap );
assign agu_req_alu_and = (icb_sta_is_amoalu & agu_i_amoand );
assign agu_req_alu_or = (icb_sta_is_amoalu & agu_i_amoor );
assign agu_req_alu_xor = (icb_sta_is_amoalu & agu_i_amoxor );
assign agu_req_alu_max = (icb_sta_is_amoalu & agu_i_amomax );
assign agu_req_alu_min = (icb_sta_is_amoalu & agu_i_amomin );
assign agu_req_alu_maxu = (icb_sta_is_amoalu & agu_i_amomaxu );
assign agu_req_alu_minu = (icb_sta_is_amoalu & agu_i_amominu );
`endif//E203_SUPPORT_AMO}
`ifndef E203_SUPPORT_AMO//{
assign agu_req_alu_swap = 1'b0;
assign agu_req_alu_and = 1'b0;
assign agu_req_alu_or = 1'b0;
assign agu_req_alu_xor = 1'b0;
assign agu_req_alu_max = 1'b0;
assign agu_req_alu_min = 1'b0;
assign agu_req_alu_maxu = 1'b0;
assign agu_req_alu_minu = 1'b0;
`endif//}
/////////////////////////////////////////////////////////////////////////////////
// Implement the AGU op handshake ready signal
//
// The AGU op handshakeke interface will be ready when
// * If it is unaligned instructions, then it will just
// directly pass out the write-back interface, hence it will only be
// ready when the write-back interface is ready
// * If it is not unaligned load/store instructions, then it will just
// directly pass out the instruction to LSU-ctrl interface, hence it need to check
// the AGU ICB interface is ready, but it also need to ask write-back interface
// for commit, so, also need to check if write-back interfac is ready
//
`ifndef E203_SUPPORT_UNALGNLDST//{
`else//}{
!!!! ERROR: This UNALIGNED load/store is not supported, must be something wrong
`endif//}
assign agu_i_ready =
( 1'b0
`ifdef E203_SUPPORT_AMO//{
| agu_i_algnamo
`endif//E203_SUPPORT_AMO}
) ? state_last_exit_ena :
(agu_icb_cmd_ready & agu_o_ready) ;
// The aligned load/store instruction will be dispatched to LSU as long pipeline
// instructions
assign agu_i_longpipe = agu_i_algnldst;
//
/////////////////////////////////////////////////////////////////////////////////
// Implement the Write-back interfaces (unaligned and AMO instructions)
// The AGU write-back will be valid when:
// * For the aligned load/store
// Directly passed to ICB interface, but also need to pass
// to write-back interface asking for commit
assign agu_o_valid =
`ifdef E203_SUPPORT_AMO//{
// For the unaligned load/store and aligned AMO, it will enter
// into the state machine and let the last state to send back
// to the commit stage
icb_sta_is_last
`endif//E203_SUPPORT_AMO}
// For the aligned load/store and unaligned AMO, it will be send
// to the commit stage right the same cycle of agu_i_valid
|(
agu_i_valid & ( agu_i_algnldst
`ifndef E203_SUPPORT_UNALGNLDST//{
// If not support the unaligned load/store by hardware, then
// the unaligned load/store will be treated as exception
// and it will also be send to the commit stage right the
// same cycle of agu_i_valid
| agu_i_unalgnldst
`endif//}
`ifdef E203_SUPPORT_AMO//{
| agu_i_unalgnamo
`endif//E203_SUPPORT_AMO}
)
//// // Since it is issuing to commit stage and
//// // LSU at same cycle, so we must qualify the icb_cmd_ready signal from LSU
//// // to make sure it is out to commit/LSU at same cycle
// To cut the critical timing path from longpipe signal
// we always assume the AGU will need icb_cmd_ready
& agu_icb_cmd_ready
);
assign agu_o_wbck_wdat = {`E203_XLEN{1'b0 }}
`ifdef E203_SUPPORT_AMO//{
| ({`E203_XLEN{agu_i_algnamo }} & leftover_r)
| ({`E203_XLEN{agu_i_unalgnamo}} & `E203_XLEN'b0)
`endif//E203_SUPPORT_AMO}
;
assign agu_o_cmt_buserr = (1'b0
`ifdef E203_SUPPORT_AMO//{
| (agu_i_algnamo & leftover_err_r)
| (agu_i_unalgnamo & 1'b0)
`endif//E203_SUPPORT_AMO}
)
;
assign agu_o_cmt_badaddr = agu_icb_cmd_addr;
assign agu_o_cmt_misalgn = (1'b0
`ifdef E203_SUPPORT_AMO//{
| agu_i_unalgnamo
`endif//E203_SUPPORT_AMO}
| (agu_i_unalgnldst) //& agu_i_excl) We dont support unaligned load/store regardless it is AMO or not
)
;
assign agu_o_cmt_ld = agu_i_load & (~agu_i_excl);
assign agu_o_cmt_stamo = agu_i_store | agu_i_amo | agu_i_excl;
// The exception or error result cannot write-back
assign agu_o_wbck_err = agu_o_cmt_buserr | agu_o_cmt_misalgn
;
assign agu_icb_rsp_ready = 1'b1;
assign agu_icb_cmd_valid =
((agu_i_algnldst & agu_i_valid)
// We must qualify the agu_o_ready signal from commit stage
// to make sure it is out to commit/LSU at same cycle
& (agu_o_ready)
)
`ifdef E203_SUPPORT_AMO//{
| (agu_i_algnamo & (
(icb_sta_is_idle & agu_i_valid
// We must qualify the agu_o_ready signal from commit stage
// to make sure it is out to commit/LSU at same cycle
& agu_o_ready)
| (icb_sta_is_wait2nd)))
| (agu_i_unalgnamo & 1'b0)
`endif//E203_SUPPORT_AMO}
;
assign agu_icb_cmd_addr = agu_req_alu_res[`E203_ADDR_SIZE-1:0];
assign agu_icb_cmd_read =
(agu_i_algnldst & agu_i_load)
`ifdef E203_SUPPORT_AMO//{
| (agu_i_algnamo & icb_sta_is_idle & 1'b1)
| (agu_i_algnamo & icb_sta_is_wait2nd & 1'b0)
`endif//E203_SUPPORT_AMO}
;
// The AGU ICB CMD Wdata sources:
// * For the aligned store instructions
// Directly passed to AGU ICB, wdata is op2 repetitive form,
// wmask is generated according to the LSB and size
wire [`E203_XLEN-1:0] algnst_wdata =
({`E203_XLEN{agu_i_size_b }} & {4{agu_i_rs2[ 7:0]}})
| ({`E203_XLEN{agu_i_size_hw}} & {2{agu_i_rs2[15:0]}})
| ({`E203_XLEN{agu_i_size_w }} & {1{agu_i_rs2[31:0]}});
wire [`E203_XLEN/8-1:0] algnst_wmask =
({`E203_XLEN/8{agu_i_size_b }} & (4'b0001 << agu_icb_cmd_addr[1:0]))
| ({`E203_XLEN/8{agu_i_size_hw}} & (4'b0011 << {agu_icb_cmd_addr[1],1'b0}))
| ({`E203_XLEN/8{agu_i_size_w }} & (4'b1111));
assign agu_icb_cmd_wdata =
`ifdef E203_SUPPORT_AMO//{
agu_i_amo ? leftover_1_r :
`endif//E203_SUPPORT_AMO}
algnst_wdata;
assign agu_icb_cmd_wmask =
`ifdef E203_SUPPORT_AMO//{
// If the 1st uop have bus-error, then not write the data for 2nd uop
agu_i_amo ? (leftover_err_r ? 4'h0 : 4'hF) :
`endif//E203_SUPPORT_AMO}
algnst_wmask;
assign agu_icb_cmd_back2agu = 1'b0
`ifdef E203_SUPPORT_AMO//{
| agu_i_algnamo
`endif//E203_SUPPORT_AMO}
;
//We dont support lock and exclusive in such 2 stage simple implementation
assign agu_icb_cmd_lock = 1'b0
`ifdef E203_SUPPORT_AMO//{
| (agu_i_algnamo & icb_sta_is_idle)
`endif//E203_SUPPORT_AMO}
;
assign agu_icb_cmd_excl = 1'b0
`ifdef E203_SUPPORT_AMO//{
| agu_i_excl
`endif//E203_SUPPORT_AMO}
;
assign agu_icb_cmd_itag = agu_i_itag;
assign agu_icb_cmd_usign = agu_i_usign;
assign agu_icb_cmd_size =
agu_i_size;
endmodule
|
module sirv_pwmgpioport(
input clock,
input reset,
input io_pwm_port_0,
input io_pwm_port_1,
input io_pwm_port_2,
input io_pwm_port_3,
input io_pins_pwm_0_i_ival,
output io_pins_pwm_0_o_oval,
output io_pins_pwm_0_o_oe,
output io_pins_pwm_0_o_ie,
output io_pins_pwm_0_o_pue,
output io_pins_pwm_0_o_ds,
input io_pins_pwm_1_i_ival,
output io_pins_pwm_1_o_oval,
output io_pins_pwm_1_o_oe,
output io_pins_pwm_1_o_ie,
output io_pins_pwm_1_o_pue,
output io_pins_pwm_1_o_ds,
input io_pins_pwm_2_i_ival,
output io_pins_pwm_2_o_oval,
output io_pins_pwm_2_o_oe,
output io_pins_pwm_2_o_ie,
output io_pins_pwm_2_o_pue,
output io_pins_pwm_2_o_ds,
input io_pins_pwm_3_i_ival,
output io_pins_pwm_3_o_oval,
output io_pins_pwm_3_o_oe,
output io_pins_pwm_3_o_ie,
output io_pins_pwm_3_o_pue,
output io_pins_pwm_3_o_ds
);
wire [1:0] T_108;
wire [1:0] T_109;
wire [3:0] T_110;
wire T_114;
wire T_115;
wire T_116;
wire T_117;
assign io_pins_pwm_0_o_oval = T_114;
assign io_pins_pwm_0_o_oe = 1'h1;
assign io_pins_pwm_0_o_ie = 1'h0;
assign io_pins_pwm_0_o_pue = 1'h0;
assign io_pins_pwm_0_o_ds = 1'h0;
assign io_pins_pwm_1_o_oval = T_115;
assign io_pins_pwm_1_o_oe = 1'h1;
assign io_pins_pwm_1_o_ie = 1'h0;
assign io_pins_pwm_1_o_pue = 1'h0;
assign io_pins_pwm_1_o_ds = 1'h0;
assign io_pins_pwm_2_o_oval = T_116;
assign io_pins_pwm_2_o_oe = 1'h1;
assign io_pins_pwm_2_o_ie = 1'h0;
assign io_pins_pwm_2_o_pue = 1'h0;
assign io_pins_pwm_2_o_ds = 1'h0;
assign io_pins_pwm_3_o_oval = T_117;
assign io_pins_pwm_3_o_oe = 1'h1;
assign io_pins_pwm_3_o_ie = 1'h0;
assign io_pins_pwm_3_o_pue = 1'h0;
assign io_pins_pwm_3_o_ds = 1'h0;
assign T_108 = {io_pwm_port_1,io_pwm_port_0};
assign T_109 = {io_pwm_port_3,io_pwm_port_2};
assign T_110 = {T_109,T_108};
assign T_114 = T_110[0];
assign T_115 = T_110[1];
assign T_116 = T_110[2];
assign T_117 = T_110[3];
endmodule
|
module sirv_gnrl_pipe_stage # (
// When the depth is 1, the ready signal may relevant to next stage's ready, hence become logic
// chains. Use CUT_READY to control it
parameter CUT_READY = 0,
parameter DP = 1,
parameter DW = 32
) (
input i_vld,
output i_rdy,
input [DW-1:0] i_dat,
output o_vld,
input o_rdy,
output [DW-1:0] o_dat,
input clk,
input rst_n
);
genvar i;
generate //{
if(DP == 0) begin: dp_eq_0//{ pass through
assign o_vld = i_vld;
assign i_rdy = o_rdy;
assign o_dat = i_dat;
end//}
else begin: dp_gt_0//{
wire vld_set;
wire vld_clr;
wire vld_ena;
wire vld_r;
wire vld_nxt;
// The valid will be set when input handshaked
assign vld_set = i_vld & i_rdy;
// The valid will be clr when output handshaked
assign vld_clr = o_vld & o_rdy;
assign vld_ena = vld_set | vld_clr;
assign vld_nxt = vld_set | (~vld_clr);
sirv_gnrl_dfflr #(1) vld_dfflr (vld_ena, vld_nxt, vld_r, clk, rst_n);
assign o_vld = vld_r;
sirv_gnrl_dffl #(DW) dat_dfflr (vld_set, i_dat, o_dat, clk);
if(CUT_READY == 1) begin:cut_ready//{
// If cut ready, then only accept when stage is not full
assign i_rdy = (~vld_r);
end//}
else begin:no_cut_ready//{
// If not cut ready, then can accept when stage is not full or it is popping
assign i_rdy = (~vld_r) | vld_clr;
end//}
end//}
endgenerate//}
endmodule
|
module sirv_gnrl_sync # (
parameter DP = 2,
parameter DW = 32
) (
input [DW-1:0] din_a,
output [DW-1:0] dout,
input rst_n,
input clk
);
wire [DW-1:0] sync_dat [DP-1:0];
genvar i;
generate
for(i=0;i<DP;i=i+1) begin:sync_gen
if(i==0) begin:i_is_0
sirv_gnrl_dffr #(DW) sync_dffr(din_a, sync_dat[0], clk, rst_n);
end
else begin:i_is_not_0
sirv_gnrl_dffr #(DW) sync_dffr(sync_dat[i-1], sync_dat[i], clk, rst_n);
end
end
endgenerate
assign dout = sync_dat[DP-1];
endmodule
|
module sirv_gnrl_cdc_rx
# (
parameter DW = 32,
parameter SYNC_DP = 2
) (
// The 4-phases handshake interface at in-side
// There are 4 steps required for a full transaction.
// (1) The i_vld is asserted high
// (2) The i_rdy is asserted high
// (3) The i_vld is asserted low
// (4) The i_rdy is asserted low
input i_vld_a,
output i_rdy,
input [DW-1:0] i_dat,
// The regular handshake interface at out-side
// Just the regular handshake o_vld & o_rdy like AXI
output o_vld,
input o_rdy,
output [DW-1:0] o_dat,
input clk,
input rst_n
);
wire i_vld_sync;
// Sync the async signal first
sirv_gnrl_sync #(.DP(SYNC_DP), .DW(1)) u_i_vld_sync (
.clk (clk),
.rst_n (rst_n),
.din_a (i_vld_a),
.dout (i_vld_sync)
);
wire i_vld_sync_r;
sirv_gnrl_dffr #(1) i_vld_sync_dffr(i_vld_sync, i_vld_sync_r, clk, rst_n);
wire i_vld_sync_nedge = (~i_vld_sync) & i_vld_sync_r;
wire buf_rdy;
wire i_rdy_r;
// Because it is a 4-phases handshake, so
// The i_rdy is set (assert to high) when the buf is ready (can save data) and incoming valid detected
// The i_rdy is clear when i_vld neg-edge is detected
wire i_rdy_set = buf_rdy & i_vld_sync & (~i_rdy_r);
wire i_rdy_clr = i_vld_sync_nedge;
wire i_rdy_ena = i_rdy_set | i_rdy_clr;
wire i_rdy_nxt = i_rdy_set | (~i_rdy_clr);
sirv_gnrl_dfflr #(1) i_rdy_dfflr(i_rdy_ena, i_rdy_nxt, i_rdy_r, clk, rst_n);
assign i_rdy = i_rdy_r;
wire buf_vld_r;
wire [DW-1:0] buf_dat_r;
// The buf is loaded with data when i_rdy is set high (i.e.,
// when the buf is ready (can save data) and incoming valid detected
wire buf_dat_ena = i_rdy_set;
sirv_gnrl_dfflr #(DW) buf_dat_dfflr(buf_dat_ena, i_dat, buf_dat_r, clk, rst_n);
// The buf_vld is set when the buf is loaded with data
wire buf_vld_set = buf_dat_ena;
// The buf_vld is clr when the buf is handshaked at the out-end
wire buf_vld_clr = o_vld & o_rdy;
wire buf_vld_ena = buf_vld_set | buf_vld_clr;
wire buf_vld_nxt = buf_vld_set | (~buf_vld_clr);
sirv_gnrl_dfflr #(1) buf_vld_dfflr(buf_vld_ena, buf_vld_nxt, buf_vld_r, clk, rst_n);
// The buf is ready when the buf is empty
assign buf_rdy = (~buf_vld_r);
assign o_vld = buf_vld_r;
assign o_dat = buf_dat_r;
endmodule
|
module sirv_gnrl_cdc_tx
# (
parameter DW = 32,
parameter SYNC_DP = 2
) (
// The regular handshake interface at in-side
// Just the regular handshake o_vld & o_rdy like AXI
input i_vld,
output i_rdy,
input [DW-1:0] i_dat,
// The 4-phases handshake interface at out-side
// There are 4 steps required for a full transaction.
// (1) The i_vld is asserted high
// (2) The i_rdy is asserted high
// (3) The i_vld is asserted low
// (4) The i_rdy is asserted low
output o_vld,
input o_rdy_a,
output [DW-1:0] o_dat,
input clk,
input rst_n
);
wire o_rdy_sync;
// Sync the async signal first
sirv_gnrl_sync #(
.DP(SYNC_DP),
.DW(1)
) u_o_rdy_sync (
.clk (clk),
.rst_n (rst_n),
.din_a (o_rdy_a),
.dout (o_rdy_sync)
);
wire vld_r;
wire [DW-1:0] dat_r;
// Valid set when it is handshaked
wire vld_set = i_vld & i_rdy;
// Valid clr when the TX o_rdy is high
wire vld_clr = o_vld & o_rdy_sync;
wire vld_ena = vld_set | vld_clr;
wire vld_nxt = vld_set | (~vld_clr);
sirv_gnrl_dfflr #(1) vld_dfflr(vld_ena, vld_nxt, vld_r, clk, rst_n);
// The data buf is only loaded when the vld is set
sirv_gnrl_dfflr #(DW) dat_dfflr(vld_set, i_dat, dat_r, clk, rst_n);
// Detect the neg-edge
wire o_rdy_sync_r;
sirv_gnrl_dffr #(1) o_rdy_sync_dffr(o_rdy_sync, o_rdy_sync_r, clk, rst_n);
wire o_rdy_nedge = (~o_rdy_sync) & o_rdy_sync_r;
// Not-ready indication
wire nrdy_r;
// Not-ready is set when the vld_r is set
wire nrdy_set = vld_set;
// Not-ready is clr when the o_rdy neg-edge is detected
wire nrdy_clr = o_rdy_nedge;
wire nrdy_ena = nrdy_set | nrdy_clr;
wire nrdy_nxt = nrdy_set | (~nrdy_clr);
sirv_gnrl_dfflr #(1) buf_nrdy_dfflr(nrdy_ena, nrdy_nxt, nrdy_r, clk, rst_n);
// The output valid
assign o_vld = vld_r;
// The output data
assign o_dat = dat_r;
// The input is ready when the Not-ready indication is low or under clearing
assign i_rdy = (~nrdy_r) | nrdy_clr;
endmodule
|
module sirv_gnrl_bypbuf # (
parameter DP = 8,
parameter DW = 32
) (
input i_vld,
output i_rdy,
input [DW-1:0] i_dat,
output o_vld,
input o_rdy,
output [DW-1:0] o_dat,
input clk,
input rst_n
);
wire fifo_i_vld;
wire fifo_i_rdy;
wire [DW-1:0] fifo_i_dat;
wire fifo_o_vld;
wire fifo_o_rdy;
wire [DW-1:0] fifo_o_dat;
sirv_gnrl_fifo # (
.DP(DP),
.DW(DW),
.CUT_READY(1)
) u_bypbuf_fifo(
.i_vld (fifo_i_vld),
.i_rdy (fifo_i_rdy),
.i_dat (fifo_i_dat),
.o_vld (fifo_o_vld),
.o_rdy (fifo_o_rdy),
.o_dat (fifo_o_dat),
.clk (clk ),
.rst_n (rst_n)
);
// This module is a super-weapon for timing fix,
// but it is tricky, think it harder when you are reading, or contact Bob Hu
assign i_rdy = fifo_i_rdy;
// The FIFO is bypassed when:
// * fifo is empty, and o_rdy is high
wire byp = i_vld & o_rdy & (~fifo_o_vld);
// FIFO o-ready just use the o_rdy
assign fifo_o_rdy = o_rdy;
// The output is valid if FIFO or input have valid
assign o_vld = fifo_o_vld | i_vld;
// The output data select the FIFO as high priority
assign o_dat = fifo_o_vld ? fifo_o_dat : i_dat;
assign fifo_i_dat = i_dat;
// Only pass to FIFO i-valid if FIFO is not bypassed
assign fifo_i_vld = i_vld & (~byp);
endmodule
|
module sirv_gnrl_fifo # (
// When the depth is 1, the ready signal may relevant to next stage's ready, hence become logic
// chains. Use CUT_READY to control it
// When fifo depth is 1, the fifo is a signle stage
// if CUT_READY is set, then the back-pressure ready signal will be cut
// off, and it can only pass 1 data every 2 cycles
// When fifo depth is > 1, then it is actually a really fifo
// The CUT_READY parameter have no impact to any logics
parameter CUT_READY = 0,
parameter MSKO = 0,// Mask out the data with valid or not
parameter DP = 8,// FIFO depth
parameter DW = 32// FIFO width
) (
input i_vld,
output i_rdy,
input [DW-1:0] i_dat,
output o_vld,
input o_rdy,
output [DW-1:0] o_dat,
input clk,
input rst_n
);
genvar i;
generate //{
if(DP == 0) begin: dp_eq1//{ pass through when it is 0 entries
assign o_vld = i_vld;
assign i_rdy = o_rdy;
assign o_dat = i_dat;
end//}
else begin: dp_gt0//{
// FIFO registers
wire [DW-1:0] fifo_rf_r [DP-1:0];
wire [DP-1:0] fifo_rf_en;
// read/write enable
wire wen = i_vld & i_rdy;
wire ren = o_vld & o_rdy;
////////////////
///////// Read-Pointer and Write-Pointer
wire [DP-1:0] rptr_vec_nxt;
wire [DP-1:0] rptr_vec_r;
wire [DP-1:0] wptr_vec_nxt;
wire [DP-1:0] wptr_vec_r;
if(DP == 1) begin:rptr_dp_1
assign rptr_vec_nxt = 1'b1;
end
else begin:rptr_dp_not_1
assign rptr_vec_nxt =
rptr_vec_r[DP-1] ? {{DP-1{1'b0}}, 1'b1} :
(rptr_vec_r << 1);
end
if(DP == 1) begin:wptr_dp_1
assign wptr_vec_nxt = 1'b1;
end
else begin:wptr_dp_not_1
assign wptr_vec_nxt =
wptr_vec_r[DP-1] ? {{DP-1{1'b0}}, 1'b1} :
(wptr_vec_r << 1);
end
sirv_gnrl_dfflrs #(1) rptr_vec_0_dfflrs (ren, rptr_vec_nxt[0] , rptr_vec_r[0] , clk, rst_n);
sirv_gnrl_dfflrs #(1) wptr_vec_0_dfflrs (wen, wptr_vec_nxt[0] , wptr_vec_r[0] , clk, rst_n);
if(DP > 1) begin:dp_gt1
sirv_gnrl_dfflr #(DP-1) rptr_vec_31_dfflr (ren, rptr_vec_nxt[DP-1:1], rptr_vec_r[DP-1:1], clk, rst_n);
sirv_gnrl_dfflr #(DP-1) wptr_vec_31_dfflr (wen, wptr_vec_nxt[DP-1:1], wptr_vec_r[DP-1:1], clk, rst_n);
end
////////////////
///////// Vec register to easy full and empty and the o_vld generation with flop-clean
wire [DP:0] i_vec;
wire [DP:0] o_vec;
wire [DP:0] vec_nxt;
wire [DP:0] vec_r;
wire vec_en = (ren ^ wen );
assign vec_nxt = wen ? {vec_r[DP-1:0], 1'b1} : (vec_r >> 1);
sirv_gnrl_dfflrs #(1) vec_0_dfflrs (vec_en, vec_nxt[0] , vec_r[0] , clk, rst_n);
sirv_gnrl_dfflr #(DP) vec_31_dfflr (vec_en, vec_nxt[DP:1], vec_r[DP:1], clk, rst_n);
assign i_vec = {1'b0,vec_r[DP:1]};
assign o_vec = {1'b0,vec_r[DP:1]};
if(DP == 1) begin:cut_dp_eq1//{
if(CUT_READY == 1) begin:cut_ready//{
// If cut ready, then only accept when fifo is not full
assign i_rdy = (~i_vec[DP-1]);
end//}
else begin:no_cut_ready//{
// If not cut ready, then can accept when fifo is not full or it is popping
assign i_rdy = (~i_vec[DP-1]) | ren;
end//}
end//}
else begin : no_cut_dp_gt1//}{
assign i_rdy = (~i_vec[DP-1]);
end//}
///////// write fifo
for (i=0; i<DP; i=i+1) begin:fifo_rf//{
assign fifo_rf_en[i] = wen & wptr_vec_r[i];
// Write the FIFO registers
sirv_gnrl_dffl #(DW) fifo_rf_dffl (fifo_rf_en[i], i_dat, fifo_rf_r[i], clk);
end//}
/////////One-Hot Mux as the read path
integer j;
reg [DW-1:0] mux_rdat;
always @*
begin : rd_port_PROC//{
mux_rdat = {DW{1'b0}};
for(j=0; j<DP; j=j+1) begin
mux_rdat = mux_rdat | ({DW{rptr_vec_r[j]}} & fifo_rf_r[j]);
end
end//}
if(MSKO == 1) begin:mask_output//{
// Mask the data with valid since the FIFO register is not reset and as X
assign o_dat = {DW{o_vld}} & mux_rdat;
end//}
else begin:no_mask_output//{
// Not Mask the data with valid since no care with X for datapth
assign o_dat = mux_rdat;
end//}
// o_vld as flop-clean
assign o_vld = (o_vec[0]);
end//}
endgenerate//}
endmodule
|
module e203_exu_regfile(
input [`E203_RFIDX_WIDTH-1:0] read_src1_idx,
input [`E203_RFIDX_WIDTH-1:0] read_src2_idx,
output [`E203_XLEN-1:0] read_src1_dat,
output [`E203_XLEN-1:0] read_src2_dat,
input wbck_dest_wen,
input [`E203_RFIDX_WIDTH-1:0] wbck_dest_idx,
input [`E203_XLEN-1:0] wbck_dest_dat,
output [`E203_XLEN-1:0] x1_r,
input test_mode,
input clk,
input rst_n
);
wire [`E203_XLEN-1:0] rf_r [`E203_RFREG_NUM-1:0];
wire [`E203_RFREG_NUM-1:0] rf_wen;
`ifdef E203_REGFILE_LATCH_BASED //{
// Use DFF to buffer the write-port
wire [`E203_XLEN-1:0] wbck_dest_dat_r;
sirv_gnrl_dffl #(`E203_XLEN) wbck_dat_dffl (wbck_dest_wen, wbck_dest_dat, wbck_dest_dat_r, clk);
wire [`E203_RFREG_NUM-1:0] clk_rf_ltch;
`endif//}
genvar i;
generate //{
for (i=0; i<`E203_RFREG_NUM; i=i+1) begin:regfile//{
if(i==0) begin: rf0
// x0 cannot be wrote since it is constant-zeros
assign rf_wen[i] = 1'b0;
assign rf_r[i] = `E203_XLEN'b0;
`ifdef E203_REGFILE_LATCH_BASED //{
assign clk_rf_ltch[i] = 1'b0;
`endif//}
end
else begin: rfno0
assign rf_wen[i] = wbck_dest_wen & (wbck_dest_idx == i) ;
`ifdef E203_REGFILE_LATCH_BASED //{
e203_clkgate u_e203_clkgate(
.clk_in (clk ),
.test_mode(test_mode),
.clock_en(rf_wen[i]),
.clk_out (clk_rf_ltch[i])
);
//from write-enable to clk_rf_ltch to rf_ltch
sirv_gnrl_ltch #(`E203_XLEN) rf_ltch (clk_rf_ltch[i], wbck_dest_dat_r, rf_r[i]);
`else//}{
sirv_gnrl_dffl #(`E203_XLEN) rf_dffl (rf_wen[i], wbck_dest_dat, rf_r[i], clk);
`endif//}
end
end//}
endgenerate//}
assign read_src1_dat = rf_r[read_src1_idx];
assign read_src2_dat = rf_r[read_src2_idx];
// wire [`E203_XLEN-1:0] x0 = rf_r[0];
// wire [`E203_XLEN-1:0] x1 = rf_r[1];
// wire [`E203_XLEN-1:0] x2 = rf_r[2];
// wire [`E203_XLEN-1:0] x3 = rf_r[3];
// wire [`E203_XLEN-1:0] x4 = rf_r[4];
// wire [`E203_XLEN-1:0] x5 = rf_r[5];
// wire [`E203_XLEN-1:0] x6 = rf_r[6];
// wire [`E203_XLEN-1:0] x7 = rf_r[7];
// wire [`E203_XLEN-1:0] x8 = rf_r[8];
// wire [`E203_XLEN-1:0] x9 = rf_r[9];
// wire [`E203_XLEN-1:0] x10 = rf_r[10];
// wire [`E203_XLEN-1:0] x11 = rf_r[11];
// wire [`E203_XLEN-1:0] x12 = rf_r[12];
// wire [`E203_XLEN-1:0] x13 = rf_r[13];
// wire [`E203_XLEN-1:0] x14 = rf_r[14];
// wire [`E203_XLEN-1:0] x15 = rf_r[15];
// `ifdef E203_RFREG_NUM_IS_32 //{
// wire [`E203_XLEN-1:0] x16 = rf_r[16];
// wire [`E203_XLEN-1:0] x17 = rf_r[17];
// wire [`E203_XLEN-1:0] x18 = rf_r[18];
// wire [`E203_XLEN-1:0] x19 = rf_r[19];
// wire [`E203_XLEN-1:0] x20 = rf_r[20];
// wire [`E203_XLEN-1:0] x21 = rf_r[21];
// wire [`E203_XLEN-1:0] x22 = rf_r[22];
// wire [`E203_XLEN-1:0] x23 = rf_r[23];
// wire [`E203_XLEN-1:0] x24 = rf_r[24];
// wire [`E203_XLEN-1:0] x25 = rf_r[25];
// wire [`E203_XLEN-1:0] x26 = rf_r[26];
// wire [`E203_XLEN-1:0] x27 = rf_r[27];
// wire [`E203_XLEN-1:0] x28 = rf_r[28];
// wire [`E203_XLEN-1:0] x29 = rf_r[29];
// wire [`E203_XLEN-1:0] x30 = rf_r[30];
// wire [`E203_XLEN-1:0] x31 = rf_r[31];
// `endif//}
assign x1_r = rf_r[1];
endmodule
|
module e203_core(
output[`E203_PC_SIZE-1:0] inspect_pc,
`ifdef E203_HAS_CSR_EAI//{
output eai_csr_valid,
input eai_csr_ready,
output [31:0] eai_csr_addr,
output eai_csr_wr,
output [31:0] eai_csr_wdata,
input [31:0] eai_csr_rdata,
`endif//}
output core_wfi,
output tm_stop,
output core_cgstop,
output tcm_cgstop,
input [`E203_PC_SIZE-1:0] pc_rtvec,
input [`E203_HART_ID_W-1:0] core_mhartid,
input dbg_irq_r,
input [`E203_LIRQ_NUM-1:0] lcl_irq_r,
input [`E203_EVT_NUM-1:0] evt_r,
input ext_irq_r,
input sft_irq_r,
input tmr_irq_r,
//////////////////////////////////////////////////////////////
// From/To debug ctrl module
output wr_dcsr_ena ,
output wr_dpc_ena ,
output wr_dscratch_ena,
output [32-1:0] wr_csr_nxt ,
input [32-1:0] dcsr_r ,
input [`E203_PC_SIZE-1:0] dpc_r ,
input [32-1:0] dscratch_r,
output [`E203_PC_SIZE-1:0] cmt_dpc,
output cmt_dpc_ena,
output [3-1:0] cmt_dcause,
output cmt_dcause_ena,
input dbg_mode,
input dbg_halt_r,
input dbg_step_r,
input dbg_ebreakm_r,
input dbg_stopcycle,
`ifdef E203_HAS_ITCM //{
// The ITCM address region indication signal
input [`E203_ADDR_SIZE-1:0] itcm_region_indic,
input ifu2itcm_holdup,
//input ifu2itcm_replay,
//////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////
// Bus Interface to ITCM, internal protocol called ICB (Internal Chip Bus)
// * Bus cmd channel
output ifu2itcm_icb_cmd_valid, // Handshake valid
input ifu2itcm_icb_cmd_ready, // Handshake ready
// Note: The data on rdata or wdata channel must be naturally
// aligned, this is in line with the AXI definition
output [`E203_ITCM_ADDR_WIDTH-1:0] ifu2itcm_icb_cmd_addr, // Bus transaction start addr
// * Bus RSP channel
input ifu2itcm_icb_rsp_valid, // Response valid
output ifu2itcm_icb_rsp_ready, // Response ready
input ifu2itcm_icb_rsp_err, // Response error
// Note: the RSP rdata is inline with AXI definition
input [`E203_ITCM_DATA_WIDTH-1:0] ifu2itcm_icb_rsp_rdata,
`endif//}
//////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////
// The ICB Interface to Private Peripheral Interface
input [`E203_ADDR_SIZE-1:0] ppi_region_indic,
//
input ppi_icb_enable,
// * Bus cmd channel
output ppi_icb_cmd_valid,
input ppi_icb_cmd_ready,
output [`E203_ADDR_SIZE-1:0] ppi_icb_cmd_addr,
output ppi_icb_cmd_read,
output [`E203_XLEN-1:0] ppi_icb_cmd_wdata,
output [`E203_XLEN/8-1:0] ppi_icb_cmd_wmask,
output ppi_icb_cmd_lock,
output ppi_icb_cmd_excl,
output [1:0] ppi_icb_cmd_size,
//
// * Bus RSP channel
input ppi_icb_rsp_valid,
output ppi_icb_rsp_ready,
input ppi_icb_rsp_err ,
input ppi_icb_rsp_excl_ok ,
input [`E203_XLEN-1:0] ppi_icb_rsp_rdata,
input [`E203_ADDR_SIZE-1:0] clint_region_indic,
input clint_icb_enable,
output clint_icb_cmd_valid,
input clint_icb_cmd_ready,
output [`E203_ADDR_SIZE-1:0] clint_icb_cmd_addr,
output clint_icb_cmd_read,
output [`E203_XLEN-1:0] clint_icb_cmd_wdata,
output [`E203_XLEN/8-1:0] clint_icb_cmd_wmask,
output clint_icb_cmd_lock,
output clint_icb_cmd_excl,
output [1:0] clint_icb_cmd_size,
//
// * Bus RSP channel
input clint_icb_rsp_valid,
output clint_icb_rsp_ready,
input clint_icb_rsp_err ,
input clint_icb_rsp_excl_ok ,
input [`E203_XLEN-1:0] clint_icb_rsp_rdata,
input [`E203_ADDR_SIZE-1:0] plic_region_indic,
input plic_icb_enable,
output plic_icb_cmd_valid,
input plic_icb_cmd_ready,
output [`E203_ADDR_SIZE-1:0] plic_icb_cmd_addr,
output plic_icb_cmd_read,
output [`E203_XLEN-1:0] plic_icb_cmd_wdata,
output [`E203_XLEN/8-1:0] plic_icb_cmd_wmask,
output plic_icb_cmd_lock,
output plic_icb_cmd_excl,
output [1:0] plic_icb_cmd_size,
//
// * Bus RSP channel
input plic_icb_rsp_valid,
output plic_icb_rsp_ready,
input plic_icb_rsp_err ,
input plic_icb_rsp_excl_ok ,
input [`E203_XLEN-1:0] plic_icb_rsp_rdata,
`ifdef E203_HAS_FIO //{
//////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////
// The ICB Interface to Fast I/O
input [`E203_ADDR_SIZE-1:0] fio_region_indic,
//
input fio_icb_enable,
// * Bus cmd channel
output fio_icb_cmd_valid,
input fio_icb_cmd_ready,
output [`E203_ADDR_SIZE-1:0] fio_icb_cmd_addr,
output fio_icb_cmd_read,
output [`E203_XLEN-1:0] fio_icb_cmd_wdata,
output [`E203_XLEN/8-1:0] fio_icb_cmd_wmask,
output fio_icb_cmd_lock,
output fio_icb_cmd_excl,
output [1:0] fio_icb_cmd_size,
//
// * Bus RSP channel
input fio_icb_rsp_valid,
output fio_icb_rsp_ready,
input fio_icb_rsp_err ,
input fio_icb_rsp_excl_ok ,
input [`E203_XLEN-1:0] fio_icb_rsp_rdata,
`endif//}
`ifdef E203_HAS_MEM_ITF //{
//////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////
// The ICB Interface from Ifetch
//
input mem_icb_enable,
// * Bus cmd channel
output mem_icb_cmd_valid,
input mem_icb_cmd_ready,
output [`E203_ADDR_SIZE-1:0] mem_icb_cmd_addr,
output mem_icb_cmd_read,
output [`E203_XLEN-1:0] mem_icb_cmd_wdata,
output [`E203_XLEN/8-1:0] mem_icb_cmd_wmask,
output mem_icb_cmd_lock,
output mem_icb_cmd_excl,
output [1:0] mem_icb_cmd_size,
output [1:0] mem_icb_cmd_burst,
output [1:0] mem_icb_cmd_beat,
//
// * Bus RSP channel
input mem_icb_rsp_valid,
output mem_icb_rsp_ready,
input mem_icb_rsp_err ,
input mem_icb_rsp_excl_ok ,
input [`E203_XLEN-1:0] mem_icb_rsp_rdata,
`endif//}
`ifdef E203_HAS_ITCM //{
//////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////
// The ICB Interface to ITCM
//
// * Bus cmd channel
output lsu2itcm_icb_cmd_valid,
input lsu2itcm_icb_cmd_ready,
output [`E203_ITCM_ADDR_WIDTH-1:0] lsu2itcm_icb_cmd_addr,
output lsu2itcm_icb_cmd_read,
output [`E203_XLEN-1:0] lsu2itcm_icb_cmd_wdata,
output [`E203_XLEN/8-1:0] lsu2itcm_icb_cmd_wmask,
output lsu2itcm_icb_cmd_lock,
output lsu2itcm_icb_cmd_excl,
output [1:0] lsu2itcm_icb_cmd_size,
//
// * Bus RSP channel
input lsu2itcm_icb_rsp_valid,
output lsu2itcm_icb_rsp_ready,
input lsu2itcm_icb_rsp_err ,
input lsu2itcm_icb_rsp_excl_ok ,
input [`E203_XLEN-1:0] lsu2itcm_icb_rsp_rdata,
`endif//}
`ifdef E203_HAS_DTCM //{
input [`E203_ADDR_SIZE-1:0] dtcm_region_indic,
//////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////
// The ICB Interface to DTCM
//
// * Bus cmd channel
output lsu2dtcm_icb_cmd_valid,
input lsu2dtcm_icb_cmd_ready,
output [`E203_DTCM_ADDR_WIDTH-1:0] lsu2dtcm_icb_cmd_addr,
output lsu2dtcm_icb_cmd_read,
output [`E203_XLEN-1:0] lsu2dtcm_icb_cmd_wdata,
output [`E203_XLEN/8-1:0] lsu2dtcm_icb_cmd_wmask,
output lsu2dtcm_icb_cmd_lock,
output lsu2dtcm_icb_cmd_excl,
output [1:0] lsu2dtcm_icb_cmd_size,
//
// * Bus RSP channel
input lsu2dtcm_icb_rsp_valid,
output lsu2dtcm_icb_rsp_ready,
input lsu2dtcm_icb_rsp_err ,
input lsu2dtcm_icb_rsp_excl_ok,
input [`E203_XLEN-1:0] lsu2dtcm_icb_rsp_rdata,
`endif//}
output exu_active,
output ifu_active,
output lsu_active,
output biu_active,
input clk_core_ifu,
input clk_core_exu,
input clk_core_lsu,
input clk_core_biu,
input clk_aon,
input test_mode,
input rst_n
);
`ifdef E203_HAS_MEM_ITF //{
wire ifu2biu_icb_cmd_valid;
wire ifu2biu_icb_cmd_ready;
wire [`E203_ADDR_SIZE-1:0] ifu2biu_icb_cmd_addr;
wire ifu2biu_icb_rsp_valid;
wire ifu2biu_icb_rsp_ready;
wire ifu2biu_icb_rsp_err ;
wire ifu2biu_icb_rsp_excl_ok;
wire [`E203_XLEN-1:0] ifu2biu_icb_rsp_rdata;
`endif//}
wire ifu_o_valid;
wire ifu_o_ready;
wire [`E203_INSTR_SIZE-1:0] ifu_o_ir;
wire [`E203_PC_SIZE-1:0] ifu_o_pc;
wire ifu_o_pc_vld;
wire ifu_o_misalgn;
wire ifu_o_buserr;
wire [`E203_RFIDX_WIDTH-1:0] ifu_o_rs1idx;
wire [`E203_RFIDX_WIDTH-1:0] ifu_o_rs2idx;
wire ifu_o_prdt_taken;
wire ifu_o_muldiv_b2b;
wire wfi_halt_ifu_req;
wire wfi_halt_ifu_ack;
wire pipe_flush_ack;
wire pipe_flush_req;
wire [`E203_PC_SIZE-1:0] pipe_flush_add_op1;
wire [`E203_PC_SIZE-1:0] pipe_flush_add_op2;
`ifdef E203_TIMING_BOOST//}
wire [`E203_PC_SIZE-1:0] pipe_flush_pc;
`endif//}
wire oitf_empty;
wire [`E203_XLEN-1:0] rf2ifu_x1;
wire [`E203_XLEN-1:0] rf2ifu_rs1;
wire dec2ifu_rden;
wire dec2ifu_rs1en;
wire [`E203_RFIDX_WIDTH-1:0] dec2ifu_rdidx;
wire dec2ifu_mulhsu;
wire dec2ifu_div ;
wire dec2ifu_rem ;
wire dec2ifu_divu ;
wire dec2ifu_remu ;
wire itcm_nohold;
e203_ifu u_e203_ifu(
.inspect_pc (inspect_pc),
.ifu_active (ifu_active),
.pc_rtvec (pc_rtvec),
.itcm_nohold (itcm_nohold),
`ifdef E203_HAS_ITCM //{
.ifu2itcm_holdup (ifu2itcm_holdup),
//.ifu2itcm_replay (ifu2itcm_replay),
// The ITCM address region indication signal
.itcm_region_indic (itcm_region_indic),
.ifu2itcm_icb_cmd_valid(ifu2itcm_icb_cmd_valid),
.ifu2itcm_icb_cmd_ready(ifu2itcm_icb_cmd_ready),
.ifu2itcm_icb_cmd_addr (ifu2itcm_icb_cmd_addr ),
.ifu2itcm_icb_rsp_valid(ifu2itcm_icb_rsp_valid),
.ifu2itcm_icb_rsp_ready(ifu2itcm_icb_rsp_ready),
.ifu2itcm_icb_rsp_err (ifu2itcm_icb_rsp_err ),
.ifu2itcm_icb_rsp_rdata(ifu2itcm_icb_rsp_rdata),
`endif//}
`ifdef E203_HAS_MEM_ITF //{
.ifu2biu_icb_cmd_valid (ifu2biu_icb_cmd_valid),
.ifu2biu_icb_cmd_ready (ifu2biu_icb_cmd_ready),
.ifu2biu_icb_cmd_addr (ifu2biu_icb_cmd_addr ),
.ifu2biu_icb_rsp_valid (ifu2biu_icb_rsp_valid),
.ifu2biu_icb_rsp_ready (ifu2biu_icb_rsp_ready),
.ifu2biu_icb_rsp_err (ifu2biu_icb_rsp_err ),
.ifu2biu_icb_rsp_rdata (ifu2biu_icb_rsp_rdata),
`endif//}
.ifu_o_valid (ifu_o_valid ),
.ifu_o_ready (ifu_o_ready ),
.ifu_o_ir (ifu_o_ir ),
.ifu_o_pc (ifu_o_pc ),
.ifu_o_pc_vld (ifu_o_pc_vld ),
.ifu_o_misalgn (ifu_o_misalgn ),
.ifu_o_buserr (ifu_o_buserr ),
.ifu_o_rs1idx (ifu_o_rs1idx ),
.ifu_o_rs2idx (ifu_o_rs2idx ),
.ifu_o_prdt_taken (ifu_o_prdt_taken ),
.ifu_o_muldiv_b2b (ifu_o_muldiv_b2b ),
.ifu_halt_req (wfi_halt_ifu_req),
.ifu_halt_ack (wfi_halt_ifu_ack),
.pipe_flush_ack (pipe_flush_ack ),
.pipe_flush_req (pipe_flush_req ),
.pipe_flush_add_op1 (pipe_flush_add_op1 ),
.pipe_flush_add_op2 (pipe_flush_add_op2 ),
`ifdef E203_TIMING_BOOST//}
.pipe_flush_pc (pipe_flush_pc),
`endif//}
.oitf_empty (oitf_empty ),
.rf2ifu_x1 (rf2ifu_x1 ),
.rf2ifu_rs1 (rf2ifu_rs1 ),
.dec2ifu_rden (dec2ifu_rden ),
.dec2ifu_rs1en (dec2ifu_rs1en),
.dec2ifu_rdidx (dec2ifu_rdidx),
.dec2ifu_mulhsu (dec2ifu_mulhsu),
.dec2ifu_div (dec2ifu_div ),
.dec2ifu_rem (dec2ifu_rem ),
.dec2ifu_divu (dec2ifu_divu ),
.dec2ifu_remu (dec2ifu_remu ),
.clk (clk_core_ifu ),
.rst_n (rst_n )
);
wire lsu_o_valid;
wire lsu_o_ready;
wire [`E203_XLEN-1:0] lsu_o_wbck_wdat;
wire [`E203_ITAG_WIDTH -1:0] lsu_o_wbck_itag;
wire lsu_o_wbck_err ;
wire lsu_o_cmt_buserr ;
wire lsu_o_cmt_ld;
wire lsu_o_cmt_st;
wire [`E203_ADDR_SIZE -1:0] lsu_o_cmt_badaddr;
wire agu_icb_cmd_valid;
wire agu_icb_cmd_ready;
wire [`E203_ADDR_SIZE-1:0] agu_icb_cmd_addr;
wire agu_icb_cmd_read;
wire [`E203_XLEN-1:0] agu_icb_cmd_wdata;
wire [`E203_XLEN/8-1:0] agu_icb_cmd_wmask;
wire agu_icb_cmd_lock;
wire agu_icb_cmd_excl;
wire [1:0] agu_icb_cmd_size;
wire agu_icb_cmd_back2agu;
wire agu_icb_cmd_usign;
wire [`E203_ITAG_WIDTH -1:0] agu_icb_cmd_itag;
wire agu_icb_rsp_valid;
wire agu_icb_rsp_ready;
wire agu_icb_rsp_err ;
wire agu_icb_rsp_excl_ok ;
wire [`E203_XLEN-1:0] agu_icb_rsp_rdata;
wire commit_mret;
wire commit_trap;
wire excp_active;
e203_exu u_e203_exu(
`ifdef E203_HAS_CSR_EAI//{
.eai_csr_valid (eai_csr_valid),
.eai_csr_ready (eai_csr_ready),
.eai_csr_addr (eai_csr_addr ),
.eai_csr_wr (eai_csr_wr ),
.eai_csr_wdata (eai_csr_wdata),
.eai_csr_rdata (eai_csr_rdata),
`endif//}
.excp_active (excp_active),
.commit_mret (commit_mret),
.commit_trap (commit_trap),
.test_mode (test_mode),
.core_wfi (core_wfi),
.tm_stop (tm_stop),
.itcm_nohold (itcm_nohold),
.core_cgstop (core_cgstop),
.tcm_cgstop (tcm_cgstop),
.exu_active (exu_active),
.core_mhartid (core_mhartid),
.dbg_irq_r (dbg_irq_r),
.lcl_irq_r (lcl_irq_r ),
.ext_irq_r (ext_irq_r ),
.sft_irq_r (sft_irq_r ),
.tmr_irq_r (tmr_irq_r ),
.evt_r (evt_r ),
.cmt_dpc (cmt_dpc ),
.cmt_dpc_ena (cmt_dpc_ena ),
.cmt_dcause (cmt_dcause ),
.cmt_dcause_ena (cmt_dcause_ena ),
.wr_dcsr_ena (wr_dcsr_ena ),
.wr_dpc_ena (wr_dpc_ena ),
.wr_dscratch_ena (wr_dscratch_ena),
.wr_csr_nxt (wr_csr_nxt ),
.dcsr_r (dcsr_r ),
.dpc_r (dpc_r ),
.dscratch_r (dscratch_r ),
.dbg_mode (dbg_mode ),
.dbg_halt_r (dbg_halt_r),
.dbg_step_r (dbg_step_r),
.dbg_ebreakm_r (dbg_ebreakm_r),
.dbg_stopcycle (dbg_stopcycle),
.i_valid (ifu_o_valid ),
.i_ready (ifu_o_ready ),
.i_ir (ifu_o_ir ),
.i_pc (ifu_o_pc ),
.i_pc_vld (ifu_o_pc_vld ),
.i_misalgn (ifu_o_misalgn ),
.i_buserr (ifu_o_buserr ),
.i_rs1idx (ifu_o_rs1idx ),
.i_rs2idx (ifu_o_rs2idx ),
.i_prdt_taken (ifu_o_prdt_taken ),
.i_muldiv_b2b (ifu_o_muldiv_b2b ),
.wfi_halt_ifu_req (wfi_halt_ifu_req),
.wfi_halt_ifu_ack (wfi_halt_ifu_ack),
.pipe_flush_ack (pipe_flush_ack ),
.pipe_flush_req (pipe_flush_req ),
.pipe_flush_add_op1 (pipe_flush_add_op1 ),
.pipe_flush_add_op2 (pipe_flush_add_op2 ),
`ifdef E203_TIMING_BOOST//}
.pipe_flush_pc (pipe_flush_pc),
`endif//}
.lsu_o_valid (lsu_o_valid ),
.lsu_o_ready (lsu_o_ready ),
.lsu_o_wbck_wdat (lsu_o_wbck_wdat ),
.lsu_o_wbck_itag (lsu_o_wbck_itag ),
.lsu_o_wbck_err (lsu_o_wbck_err ),
.lsu_o_cmt_buserr (lsu_o_cmt_buserr ),
.lsu_o_cmt_ld (lsu_o_cmt_ld),
.lsu_o_cmt_st (lsu_o_cmt_st),
.lsu_o_cmt_badaddr (lsu_o_cmt_badaddr ),
.agu_icb_cmd_valid (agu_icb_cmd_valid ),
.agu_icb_cmd_ready (agu_icb_cmd_ready ),
.agu_icb_cmd_addr (agu_icb_cmd_addr ),
.agu_icb_cmd_read (agu_icb_cmd_read ),
.agu_icb_cmd_wdata (agu_icb_cmd_wdata ),
.agu_icb_cmd_wmask (agu_icb_cmd_wmask ),
.agu_icb_cmd_lock (agu_icb_cmd_lock ),
.agu_icb_cmd_excl (agu_icb_cmd_excl ),
.agu_icb_cmd_size (agu_icb_cmd_size ),
.agu_icb_cmd_back2agu (agu_icb_cmd_back2agu),
.agu_icb_cmd_usign (agu_icb_cmd_usign ),
.agu_icb_cmd_itag (agu_icb_cmd_itag ),
.agu_icb_rsp_valid (agu_icb_rsp_valid ),
.agu_icb_rsp_ready (agu_icb_rsp_ready ),
.agu_icb_rsp_err (agu_icb_rsp_err ),
.agu_icb_rsp_excl_ok (agu_icb_rsp_excl_ok ),
.agu_icb_rsp_rdata (agu_icb_rsp_rdata ),
.oitf_empty (oitf_empty ),
.rf2ifu_x1 (rf2ifu_x1 ),
.rf2ifu_rs1 (rf2ifu_rs1 ),
.dec2ifu_rden (dec2ifu_rden ),
.dec2ifu_rs1en (dec2ifu_rs1en),
.dec2ifu_rdidx (dec2ifu_rdidx),
.dec2ifu_mulhsu (dec2ifu_mulhsu),
.dec2ifu_div (dec2ifu_div ),
.dec2ifu_rem (dec2ifu_rem ),
.dec2ifu_divu (dec2ifu_divu ),
.dec2ifu_remu (dec2ifu_remu ),
.clk_aon (clk_aon),
.clk (clk_core_exu),
.rst_n (rst_n )
);
wire lsu2biu_icb_cmd_valid;
wire lsu2biu_icb_cmd_ready;
wire [`E203_ADDR_SIZE-1:0] lsu2biu_icb_cmd_addr;
wire lsu2biu_icb_cmd_read;
wire [`E203_XLEN-1:0] lsu2biu_icb_cmd_wdata;
wire [`E203_XLEN/8-1:0] lsu2biu_icb_cmd_wmask;
wire lsu2biu_icb_cmd_lock;
wire lsu2biu_icb_cmd_excl;
wire [1:0] lsu2biu_icb_cmd_size;
wire lsu2biu_icb_rsp_valid;
wire lsu2biu_icb_rsp_ready;
wire lsu2biu_icb_rsp_err ;
wire lsu2biu_icb_rsp_excl_ok;
wire [`E203_XLEN-1:0] lsu2biu_icb_rsp_rdata;
e203_lsu u_e203_lsu(
.excp_active (excp_active),
.commit_mret (commit_mret),
.commit_trap (commit_trap),
.lsu_active (lsu_active),
.lsu_o_valid (lsu_o_valid ),
.lsu_o_ready (lsu_o_ready ),
.lsu_o_wbck_wdat (lsu_o_wbck_wdat ),
.lsu_o_wbck_itag (lsu_o_wbck_itag ),
.lsu_o_wbck_err (lsu_o_wbck_err ),
.lsu_o_cmt_buserr (lsu_o_cmt_buserr ),
.lsu_o_cmt_ld (lsu_o_cmt_ld),
.lsu_o_cmt_st (lsu_o_cmt_st),
.lsu_o_cmt_badaddr (lsu_o_cmt_badaddr ),
.agu_icb_cmd_valid (agu_icb_cmd_valid ),
.agu_icb_cmd_ready (agu_icb_cmd_ready ),
.agu_icb_cmd_addr (agu_icb_cmd_addr ),
.agu_icb_cmd_read (agu_icb_cmd_read ),
.agu_icb_cmd_wdata (agu_icb_cmd_wdata ),
.agu_icb_cmd_wmask (agu_icb_cmd_wmask ),
.agu_icb_cmd_lock (agu_icb_cmd_lock ),
.agu_icb_cmd_excl (agu_icb_cmd_excl ),
.agu_icb_cmd_size (agu_icb_cmd_size ),
.agu_icb_cmd_back2agu(agu_icb_cmd_back2agu ),
.agu_icb_cmd_usign (agu_icb_cmd_usign),
.agu_icb_cmd_itag (agu_icb_cmd_itag),
.agu_icb_rsp_valid (agu_icb_rsp_valid ),
.agu_icb_rsp_ready (agu_icb_rsp_ready ),
.agu_icb_rsp_err (agu_icb_rsp_err ),
.agu_icb_rsp_excl_ok (agu_icb_rsp_excl_ok),
.agu_icb_rsp_rdata (agu_icb_rsp_rdata),
`ifdef E203_HAS_ITCM //{
.itcm_region_indic (itcm_region_indic),
.itcm_icb_cmd_valid (lsu2itcm_icb_cmd_valid),
.itcm_icb_cmd_ready (lsu2itcm_icb_cmd_ready),
.itcm_icb_cmd_addr (lsu2itcm_icb_cmd_addr ),
.itcm_icb_cmd_read (lsu2itcm_icb_cmd_read ),
.itcm_icb_cmd_wdata (lsu2itcm_icb_cmd_wdata),
.itcm_icb_cmd_wmask (lsu2itcm_icb_cmd_wmask),
.itcm_icb_cmd_lock (lsu2itcm_icb_cmd_lock ),
.itcm_icb_cmd_excl (lsu2itcm_icb_cmd_excl ),
.itcm_icb_cmd_size (lsu2itcm_icb_cmd_size ),
.itcm_icb_rsp_valid (lsu2itcm_icb_rsp_valid),
.itcm_icb_rsp_ready (lsu2itcm_icb_rsp_ready),
.itcm_icb_rsp_err (lsu2itcm_icb_rsp_err ),
.itcm_icb_rsp_excl_ok(lsu2itcm_icb_rsp_excl_ok ),
.itcm_icb_rsp_rdata (lsu2itcm_icb_rsp_rdata),
`endif//}
`ifdef E203_HAS_DTCM //{
.dtcm_region_indic (dtcm_region_indic),
.dtcm_icb_cmd_valid (lsu2dtcm_icb_cmd_valid),
.dtcm_icb_cmd_ready (lsu2dtcm_icb_cmd_ready),
.dtcm_icb_cmd_addr (lsu2dtcm_icb_cmd_addr ),
.dtcm_icb_cmd_read (lsu2dtcm_icb_cmd_read ),
.dtcm_icb_cmd_wdata (lsu2dtcm_icb_cmd_wdata),
.dtcm_icb_cmd_wmask (lsu2dtcm_icb_cmd_wmask),
.dtcm_icb_cmd_lock (lsu2dtcm_icb_cmd_lock ),
.dtcm_icb_cmd_excl (lsu2dtcm_icb_cmd_excl ),
.dtcm_icb_cmd_size (lsu2dtcm_icb_cmd_size ),
.dtcm_icb_rsp_valid (lsu2dtcm_icb_rsp_valid),
.dtcm_icb_rsp_ready (lsu2dtcm_icb_rsp_ready),
.dtcm_icb_rsp_err (lsu2dtcm_icb_rsp_err ),
.dtcm_icb_rsp_excl_ok(lsu2dtcm_icb_rsp_excl_ok ),
.dtcm_icb_rsp_rdata (lsu2dtcm_icb_rsp_rdata),
`endif//}
.biu_icb_cmd_valid (lsu2biu_icb_cmd_valid),
.biu_icb_cmd_ready (lsu2biu_icb_cmd_ready),
.biu_icb_cmd_addr (lsu2biu_icb_cmd_addr ),
.biu_icb_cmd_read (lsu2biu_icb_cmd_read ),
.biu_icb_cmd_wdata (lsu2biu_icb_cmd_wdata),
.biu_icb_cmd_wmask (lsu2biu_icb_cmd_wmask),
.biu_icb_cmd_lock (lsu2biu_icb_cmd_lock ),
.biu_icb_cmd_excl (lsu2biu_icb_cmd_excl ),
.biu_icb_cmd_size (lsu2biu_icb_cmd_size ),
.biu_icb_rsp_valid (lsu2biu_icb_rsp_valid),
.biu_icb_rsp_ready (lsu2biu_icb_rsp_ready),
.biu_icb_rsp_err (lsu2biu_icb_rsp_err ),
.biu_icb_rsp_excl_ok(lsu2biu_icb_rsp_excl_ok),
.biu_icb_rsp_rdata (lsu2biu_icb_rsp_rdata),
.clk (clk_core_lsu ),
.rst_n (rst_n )
);
e203_biu u_e203_biu(
.biu_active (biu_active),
.lsu2biu_icb_cmd_valid (lsu2biu_icb_cmd_valid),
.lsu2biu_icb_cmd_ready (lsu2biu_icb_cmd_ready),
.lsu2biu_icb_cmd_addr (lsu2biu_icb_cmd_addr ),
.lsu2biu_icb_cmd_read (lsu2biu_icb_cmd_read ),
.lsu2biu_icb_cmd_wdata (lsu2biu_icb_cmd_wdata),
.lsu2biu_icb_cmd_wmask (lsu2biu_icb_cmd_wmask),
.lsu2biu_icb_cmd_lock (lsu2biu_icb_cmd_lock ),
.lsu2biu_icb_cmd_excl (lsu2biu_icb_cmd_excl ),
.lsu2biu_icb_cmd_size (lsu2biu_icb_cmd_size ),
.lsu2biu_icb_cmd_burst (2'b0),
.lsu2biu_icb_cmd_beat (2'b0 ),
.lsu2biu_icb_rsp_valid (lsu2biu_icb_rsp_valid),
.lsu2biu_icb_rsp_ready (lsu2biu_icb_rsp_ready),
.lsu2biu_icb_rsp_err (lsu2biu_icb_rsp_err ),
.lsu2biu_icb_rsp_excl_ok(lsu2biu_icb_rsp_excl_ok),
.lsu2biu_icb_rsp_rdata (lsu2biu_icb_rsp_rdata),
`ifdef E203_HAS_MEM_ITF //{
.ifu2biu_icb_cmd_valid (ifu2biu_icb_cmd_valid),
.ifu2biu_icb_cmd_ready (ifu2biu_icb_cmd_ready),
.ifu2biu_icb_cmd_addr (ifu2biu_icb_cmd_addr ),
.ifu2biu_icb_cmd_read (1'b1 ),
.ifu2biu_icb_cmd_wdata (`E203_XLEN'b0),
.ifu2biu_icb_cmd_wmask ({`E203_XLEN/8{1'b0}}),
.ifu2biu_icb_cmd_lock (1'b0 ),
.ifu2biu_icb_cmd_excl (1'b0 ),
.ifu2biu_icb_cmd_size (2'b10),
.ifu2biu_icb_cmd_burst (2'b0),
.ifu2biu_icb_cmd_beat (2'b0),
.ifu2biu_icb_rsp_valid (ifu2biu_icb_rsp_valid),
.ifu2biu_icb_rsp_ready (ifu2biu_icb_rsp_ready),
.ifu2biu_icb_rsp_err (ifu2biu_icb_rsp_err ),
.ifu2biu_icb_rsp_excl_ok(ifu2biu_icb_rsp_excl_ok),
.ifu2biu_icb_rsp_rdata (ifu2biu_icb_rsp_rdata),
`endif//}
.ppi_region_indic (ppi_region_indic ),
.ppi_icb_enable (ppi_icb_enable),
.ppi_icb_cmd_valid (ppi_icb_cmd_valid),
.ppi_icb_cmd_ready (ppi_icb_cmd_ready),
.ppi_icb_cmd_addr (ppi_icb_cmd_addr ),
.ppi_icb_cmd_read (ppi_icb_cmd_read ),
.ppi_icb_cmd_wdata (ppi_icb_cmd_wdata),
.ppi_icb_cmd_wmask (ppi_icb_cmd_wmask),
.ppi_icb_cmd_lock (ppi_icb_cmd_lock ),
.ppi_icb_cmd_excl (ppi_icb_cmd_excl ),
.ppi_icb_cmd_size (ppi_icb_cmd_size ),
.ppi_icb_cmd_burst (),
.ppi_icb_cmd_beat (),
.ppi_icb_rsp_valid (ppi_icb_rsp_valid),
.ppi_icb_rsp_ready (ppi_icb_rsp_ready),
.ppi_icb_rsp_err (ppi_icb_rsp_err ),
.ppi_icb_rsp_excl_ok (ppi_icb_rsp_excl_ok),
.ppi_icb_rsp_rdata (ppi_icb_rsp_rdata),
.plic_icb_enable (plic_icb_enable),
.plic_region_indic (plic_region_indic ),
.plic_icb_cmd_valid (plic_icb_cmd_valid),
.plic_icb_cmd_ready (plic_icb_cmd_ready),
.plic_icb_cmd_addr (plic_icb_cmd_addr ),
.plic_icb_cmd_read (plic_icb_cmd_read ),
.plic_icb_cmd_wdata (plic_icb_cmd_wdata),
.plic_icb_cmd_wmask (plic_icb_cmd_wmask),
.plic_icb_cmd_lock (plic_icb_cmd_lock ),
.plic_icb_cmd_excl (plic_icb_cmd_excl ),
.plic_icb_cmd_size (plic_icb_cmd_size ),
.plic_icb_cmd_burst (),
.plic_icb_cmd_beat (),
.plic_icb_rsp_valid (plic_icb_rsp_valid),
.plic_icb_rsp_ready (plic_icb_rsp_ready),
.plic_icb_rsp_err (plic_icb_rsp_err ),
.plic_icb_rsp_excl_ok (plic_icb_rsp_excl_ok),
.plic_icb_rsp_rdata (plic_icb_rsp_rdata),
.clint_icb_enable (clint_icb_enable),
.clint_region_indic (clint_region_indic ),
.clint_icb_cmd_valid (clint_icb_cmd_valid),
.clint_icb_cmd_ready (clint_icb_cmd_ready),
.clint_icb_cmd_addr (clint_icb_cmd_addr ),
.clint_icb_cmd_read (clint_icb_cmd_read ),
.clint_icb_cmd_wdata (clint_icb_cmd_wdata),
.clint_icb_cmd_wmask (clint_icb_cmd_wmask),
.clint_icb_cmd_lock (clint_icb_cmd_lock ),
.clint_icb_cmd_excl (clint_icb_cmd_excl ),
.clint_icb_cmd_size (clint_icb_cmd_size ),
.clint_icb_cmd_burst (),
.clint_icb_cmd_beat (),
.clint_icb_rsp_valid (clint_icb_rsp_valid),
.clint_icb_rsp_ready (clint_icb_rsp_ready),
.clint_icb_rsp_err (clint_icb_rsp_err ),
.clint_icb_rsp_excl_ok (clint_icb_rsp_excl_ok),
.clint_icb_rsp_rdata (clint_icb_rsp_rdata),
`ifdef E203_HAS_FIO //{
.fio_region_indic (fio_region_indic ),
.fio_icb_enable (fio_icb_enable),
.fio_icb_cmd_valid (fio_icb_cmd_valid),
.fio_icb_cmd_ready (fio_icb_cmd_ready),
.fio_icb_cmd_addr (fio_icb_cmd_addr ),
.fio_icb_cmd_read (fio_icb_cmd_read ),
.fio_icb_cmd_wdata (fio_icb_cmd_wdata),
.fio_icb_cmd_wmask (fio_icb_cmd_wmask),
.fio_icb_cmd_lock (fio_icb_cmd_lock ),
.fio_icb_cmd_excl (fio_icb_cmd_excl ),
.fio_icb_cmd_size (fio_icb_cmd_size ),
.fio_icb_cmd_burst (),
.fio_icb_cmd_beat (),
.fio_icb_rsp_valid (fio_icb_rsp_valid),
.fio_icb_rsp_ready (fio_icb_rsp_ready),
.fio_icb_rsp_err (fio_icb_rsp_err ),
.fio_icb_rsp_excl_ok (fio_icb_rsp_excl_ok ),
.fio_icb_rsp_rdata (fio_icb_rsp_rdata),
`endif//}
`ifdef E203_HAS_MEM_ITF //{
.mem_icb_enable (mem_icb_enable),
.mem_icb_cmd_valid (mem_icb_cmd_valid),
.mem_icb_cmd_ready (mem_icb_cmd_ready),
.mem_icb_cmd_addr (mem_icb_cmd_addr ),
.mem_icb_cmd_read (mem_icb_cmd_read ),
.mem_icb_cmd_wdata (mem_icb_cmd_wdata),
.mem_icb_cmd_wmask (mem_icb_cmd_wmask),
.mem_icb_cmd_lock (mem_icb_cmd_lock ),
.mem_icb_cmd_excl (mem_icb_cmd_excl ),
.mem_icb_cmd_size (mem_icb_cmd_size ),
.mem_icb_cmd_burst (mem_icb_cmd_burst),
.mem_icb_cmd_beat (mem_icb_cmd_beat ),
.mem_icb_rsp_valid (mem_icb_rsp_valid),
.mem_icb_rsp_ready (mem_icb_rsp_ready),
.mem_icb_rsp_err (mem_icb_rsp_err ),
.mem_icb_rsp_excl_ok (mem_icb_rsp_excl_ok ),
.mem_icb_rsp_rdata (mem_icb_rsp_rdata),
`endif//}
.clk (clk_core_biu ),
.rst_n (rst_n )
);
endmodule
|
module sirv_plic_man # (
parameter PLIC_PRIO_WIDTH = 3,
parameter PLIC_IRQ_NUM = 8,// Must larger than 1, if just 1 interrupt, please go without PLIC
parameter PLIC_IRQ_NUM_LOG2 = 3,// If the irq is 1<N<=2, then log2 value is 1;
// If the irq is 2<N<=4, then log2 value is 2;
// If the irq is 4<N<=8, then log2 value is 3;
// ....etc
// We at most support 10 levels, then 1024 interrupt sources
// But the source 0 is just always tied to zero
parameter PLIC_ICB_RSP_FLOP = 0, // Do we flop the ICB response channel to easy timing
parameter PLIC_IRQ_I_FLOP = 0, // Do we flop the input interrupts from sources
parameter PLIC_IRQ_O_FLOP = 0 // Do we flop the output interrupt to the Core target
)(
input clk,
input rst_n,
input icb_cmd_valid,
output icb_cmd_ready,
input [24-1:0] icb_cmd_addr,
input icb_cmd_read,
input [32-1:0] icb_cmd_wdata,
output icb_rsp_valid,
input icb_rsp_ready,
output [32-1:0] icb_rsp_rdata,
input [PLIC_IRQ_NUM-1:0] plic_irq_i,
output plic_irq_o
);
// If there are 32 irq, then we need 1 pend-array ([31:0])
// If there are 40 irq, then we need 2 pend-array ([39:32],[31:0])
// If there are 64 irq, then we need 2 pend-array ([63:32],[31:0])
localparam PLIC_PEND_ARRAY = (((PLIC_IRQ_NUM-1)/32) + 1);
wire icb_cmd_hsked = icb_cmd_valid & icb_cmd_ready;
wire icb_cmd_wr_hsked = icb_cmd_hsked & (~icb_cmd_read);
wire icb_cmd_rd_hsked = icb_cmd_hsked & icb_cmd_read;
wire [PLIC_IRQ_NUM-1:0] plic_irq_i_r;
wire [PLIC_IRQ_NUM-1:0] irq_i_gated_valid;
wire [PLIC_IRQ_NUM-1:0] irq_i_gated_ready;
wire [PLIC_IRQ_NUM-1:0] irq_i_gated_hsked;
reg [PLIC_IRQ_NUM-1:0] icb_claim_irq;
reg [PLIC_IRQ_NUM-1:0] icb_complete_irq;
wire irq_o;
wire [PLIC_IRQ_NUM_LOG2-1:0] irq_id ;
wire [PLIC_IRQ_NUM_LOG2-1:0] plic_irq_id ;
wire [PLIC_PRIO_WIDTH-1:0] plic_irq_prio ;
wire [PLIC_IRQ_NUM-1:0] irq_pend_set;
wire [PLIC_IRQ_NUM-1:0] irq_pend_clr;
wire [PLIC_IRQ_NUM-1:0] irq_pend_ena;
wire [PLIC_IRQ_NUM-1:0] irq_pend_nxt;
wire [PLIC_PEND_ARRAY*32-1:0] irq_pend_r; // The IP bit per interrupt source
wire [PLIC_PEND_ARRAY-1:0] icb_cmd_sel_pend;
wire icb_cmd_sel_clam;
wire icb_cmd_sel_thod;
wire irq_thod_ena;
wire [PLIC_PRIO_WIDTH-1:0] irq_thod_nxt;
wire [PLIC_PRIO_WIDTH-1:0] irq_thod_r ; // The priority per interrupt source
wire [PLIC_IRQ_NUM-1:0] icb_cmd_sel_prio;
wire [PLIC_IRQ_NUM-1:0] irq_prio_ena;
wire [PLIC_PRIO_WIDTH-1:0] irq_prio_nxt [PLIC_IRQ_NUM-1:0];
wire [PLIC_PRIO_WIDTH-1:0] irq_prio_r [PLIC_IRQ_NUM-1:0]; // The priority per interrupt source
wire [PLIC_PRIO_WIDTH-1:0] irq_prio_masked [PLIC_IRQ_NUM-1:0]; // The masked priority per interrupt source
wire irq_prio_lvl_10_lt [1024-1:0]; // The level-10 max priority array
wire irq_prio_lvl_9_lt [512-1:0] ; // The level-9 max priority array
wire irq_prio_lvl_8_lt [256-1:0] ; // The level-8 max priority array
wire irq_prio_lvl_7_lt [128-1:0] ; // The level-7 max priority array
wire irq_prio_lvl_6_lt [64-1:0] ; // The level-6 max priority array
wire irq_prio_lvl_5_lt [32-1:0] ; // The level-5 max priority array
wire irq_prio_lvl_4_lt [16-1:0] ; // The level-4 max priority array
wire irq_prio_lvl_3_lt [8-1:0] ; // The level-3 max priority array
wire irq_prio_lvl_2_lt [4-1:0] ; // The level-2 max priority array
wire irq_prio_lvl_1_lt [2-1:0] ; // The level-1 max priority array
wire irq_prio_top_lt ; // The level-0 max priority
wire [PLIC_PRIO_WIDTH-1:0] irq_prio_lvl_10 [1024-1:0] ; // The level-10 max priority array
wire [PLIC_PRIO_WIDTH-1:0] irq_prio_lvl_9 [512-1:0] ; // The level-9 max priority array
wire [PLIC_PRIO_WIDTH-1:0] irq_prio_lvl_8 [256-1:0] ; // The level-8 max priority array
wire [PLIC_PRIO_WIDTH-1:0] irq_prio_lvl_7 [128-1:0] ; // The level-7 max priority array
wire [PLIC_PRIO_WIDTH-1:0] irq_prio_lvl_6 [64-1:0] ; // The level-6 max priority array
wire [PLIC_PRIO_WIDTH-1:0] irq_prio_lvl_5 [32-1:0] ; // The level-5 max priority array
wire [PLIC_PRIO_WIDTH-1:0] irq_prio_lvl_4 [16-1:0] ; // The level-4 max priority array
wire [PLIC_PRIO_WIDTH-1:0] irq_prio_lvl_3 [8-1:0] ; // The level-3 max priority array
wire [PLIC_PRIO_WIDTH-1:0] irq_prio_lvl_2 [4-1:0] ; // The level-2 max priority array
wire [PLIC_PRIO_WIDTH-1:0] irq_prio_lvl_1 [2-1:0] ; // The level-1 max priority array
wire [PLIC_PRIO_WIDTH-1:0] irq_prio_top ; // The level-0 max priority
wire [PLIC_IRQ_NUM_LOG2-1:0] irq_id_lvl_10 [1024-1:0] ; // The level-10 max id array
wire [PLIC_IRQ_NUM_LOG2-1:0] irq_id_lvl_9 [512-1:0] ; // The level-9 max id array
wire [PLIC_IRQ_NUM_LOG2-1:0] irq_id_lvl_8 [256-1:0] ; // The level-8 max id array
wire [PLIC_IRQ_NUM_LOG2-1:0] irq_id_lvl_7 [128-1:0] ; // The level-7 max id array
wire [PLIC_IRQ_NUM_LOG2-1:0] irq_id_lvl_6 [64-1:0] ; // The level-6 max id array
wire [PLIC_IRQ_NUM_LOG2-1:0] irq_id_lvl_5 [32-1:0] ; // The level-5 max id array
wire [PLIC_IRQ_NUM_LOG2-1:0] irq_id_lvl_4 [16-1:0] ; // The level-4 max id array
wire [PLIC_IRQ_NUM_LOG2-1:0] irq_id_lvl_3 [8-1:0] ; // The level-3 max id array
wire [PLIC_IRQ_NUM_LOG2-1:0] irq_id_lvl_2 [4-1:0] ; // The level-2 max id array
wire [PLIC_IRQ_NUM_LOG2-1:0] irq_id_lvl_1 [2-1:0] ; // The level-1 max id array
wire [PLIC_IRQ_NUM_LOG2-1:0] irq_id_top ; // The level-0 max id
wire irq_ip_lvl_10 [1024-1:0] ; // The level-10 IP array
wire irq_ip_lvl_9 [512-1:0] ; // The level-9 IP array
wire irq_ip_lvl_8 [256-1:0] ; // The level-8 IP array
wire irq_ip_lvl_7 [128-1:0] ; // The level-7 IP array
wire irq_ip_lvl_6 [64-1:0] ; // The level-6 IP array
wire irq_ip_lvl_5 [32-1:0] ; // The level-5 IP array
wire irq_ip_lvl_4 [16-1:0] ; // The level-4 IP array
wire irq_ip_lvl_3 [8-1:0] ; // The level-3 IP array
wire irq_ip_lvl_2 [4-1:0] ; // The level-2 IP array
wire irq_ip_lvl_1 [2-1:0] ; // The level-1 IP array
wire irq_ip_top ; // The level-0 IP
wire icb_cmd_sel_enab [PLIC_PEND_ARRAY-1:0];
wire irq_enab_ena [PLIC_PEND_ARRAY-1:0];
wire [32-1:0] irq_enab_nxt [PLIC_PEND_ARRAY-1:0];
wire [32-1:0] irq_enab_r [PLIC_PEND_ARRAY-1:0];
wire plic_irq_o_pre;
genvar i;
integer ii;
generate
if(PLIC_IRQ_I_FLOP == 1) begin: flop_i_irq
sirv_gnrl_dffr #(PLIC_IRQ_NUM) plic_irq_i_dffr(plic_irq_i , plic_irq_i_r, clk, rst_n);
end
else begin: no_flop_i_irq
assign plic_irq_i_r = plic_irq_i;
end
if(PLIC_IRQ_O_FLOP == 1) begin: flop_o_irq
sirv_gnrl_dffr #(1) plic_irq_o_dffr(irq_o , plic_irq_o_pre, clk, rst_n);
sirv_gnrl_dffr #(PLIC_IRQ_NUM_LOG2) plic_irq_id_dffr(irq_id , plic_irq_id, clk, rst_n);
sirv_gnrl_dffr #(PLIC_PRIO_WIDTH) plic_irq_prio_dffr(irq_prio_top , plic_irq_prio, clk, rst_n);
end
else begin: no_flop_o_irq
assign plic_irq_o_pre = irq_o ;
assign plic_irq_id = irq_id;
assign plic_irq_prio = irq_prio_top;
end
assign plic_irq_o = plic_irq_o_pre;// & (plic_irq_prio > irq_thod_r);
assign irq_i_gated_hsked[0] = 1'b0;
assign irq_i_gated_valid[0] = 1'b0;
assign irq_i_gated_ready[0] = 1'b0;
assign irq_pend_set[0] = 1'b0;
assign irq_pend_clr[0] = 1'b0;
assign irq_pend_ena[0] = 1'b0;
assign irq_pend_nxt[0] = 1'b0;
assign irq_pend_r [0] = 1'b0;
assign irq_prio_ena[0] = 1'b0;
assign irq_prio_nxt[0] = {PLIC_PRIO_WIDTH{1'b0}};
assign irq_prio_r[0] = {PLIC_PRIO_WIDTH{1'b0}};
assign irq_prio_masked[0] = {PLIC_PRIO_WIDTH{1'b0}};
for(i=1; i<PLIC_IRQ_NUM;i=i+1) begin: source_gen//{
///////////////////////////////////////////////////////////////////
// Implment the gateway for each interrupt source
//
sirv_LevelGateway u_LevelGateway_1_1 (
.clock (clk ),
.reset (~rst_n),
.io_interrupt (plic_irq_i_r[i]),
.io_plic_valid (irq_i_gated_valid[i]),
.io_plic_ready (irq_i_gated_ready[i]),
.io_plic_complete(icb_complete_irq[i])
);
assign irq_i_gated_hsked[i] = irq_i_gated_valid[i] & irq_i_gated_ready[i];
///////////////////////////////////////////////////////////////////
// Implment the IP bit for each interrupt source
//
// If the pending irq is cleared, then it is ready to accept new interrupt from gateway
assign irq_i_gated_ready[i] = (~irq_pend_r[i]);
// The IRQ pend is set when the gateway output handshaked
assign irq_pend_set[i] = irq_i_gated_hsked[i];
// The IRQ pend is cleared when the interrupt is claimed, according to the spec:
// After the highest-priority pending interrupt is claimed by a target and the
// corresponding IP bit is cleared.
assign irq_pend_clr[i] = icb_claim_irq[i];
assign irq_pend_ena[i] = (irq_pend_set[i] | irq_pend_clr[i]);
assign irq_pend_nxt[i] = (irq_pend_set[i] | (~irq_pend_clr[i]));
sirv_gnrl_dfflr #(1) irq_pend_dfflr(irq_pend_ena[i] , irq_pend_nxt[i], irq_pend_r[i], clk, rst_n);
///////////////////////////////////////////////////////////////////
// Implment the Priority for each interrupt source
//
// The priority will be set by bus writting
assign irq_prio_ena[i] = icb_cmd_wr_hsked & icb_cmd_sel_prio[i];
assign irq_prio_nxt[i] = icb_cmd_wdata[PLIC_PRIO_WIDTH-1:0];
sirv_gnrl_dfflr #(PLIC_PRIO_WIDTH) irq_prio_dfflr(irq_prio_ena[i] , irq_prio_nxt[i], irq_prio_r[i], clk, rst_n);
///////////////////////////////////////////////////////////////////
// The priority will be masked to zero, if the IP is not set
//
assign irq_prio_masked[i] = irq_prio_r[i] & {PLIC_PRIO_WIDTH{irq_pend_r[i]}};
end//}
for(i=PLIC_IRQ_NUM; i<(PLIC_PEND_ARRAY*32);i=i+1) begin: pend_gen//{
assign irq_pend_r[i] = 1'b0;
end//}
///////////////////////////////////////////////////////////////////
// Implment the IE for each interrupt source and target
//
for(i=0; i<(PLIC_PEND_ARRAY);i=i+1) begin: enab_r_i//{
// The IE will be set by bus writting
assign irq_enab_ena[i] = icb_cmd_sel_enab[i] & icb_cmd_wr_hsked;
sirv_gnrl_dfflr #(32) irq_enab_dfflr(irq_enab_ena[i], irq_enab_nxt[i], irq_enab_r[i], clk, rst_n);
if(i == 0)begin: i0_ena
assign irq_enab_nxt[i] = {icb_cmd_wdata[31:1],1'b0};// The 0-interrupt is always 0
end
else if((PLIC_PEND_ARRAY-1) == i) begin:last_one
if((PLIC_IRQ_NUM%32) == 0) begin:irq_num_div_32
assign irq_enab_nxt[i] = icb_cmd_wdata[31:0];
end
else begin:irq_num_not_div_32
assign irq_enab_nxt[i] = icb_cmd_wdata[(PLIC_IRQ_NUM%32)-1:0];
end
end
else begin:no_last_one
assign irq_enab_nxt[i] = icb_cmd_wdata[31:0];
end
end//}
///////////////////////////////////////////////////////////////////
// Implment the Threshold for each interrupt target
//
//
// The Threshold will be set by bus writting
assign irq_thod_ena = icb_cmd_wr_hsked & icb_cmd_sel_thod;
assign irq_thod_nxt = icb_cmd_wdata[PLIC_PRIO_WIDTH-1:0];
sirv_gnrl_dfflr #(PLIC_PRIO_WIDTH) irq_thod_dfflr(irq_thod_ena , irq_thod_nxt, irq_thod_r, clk, rst_n);
///////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////
// Use the binary-tree structure to compare and select the pending interrupt
// source with the max priority and its ID
//
// Generate the level-10 signals
// We need to tie the unused signals to zeros
// and the synthesis tools will automatically
// optimize unused logics to zeros
//
// Tie the irq0 relevant logics to 0
assign irq_prio_lvl_10[0] = {PLIC_PRIO_WIDTH{1'b0}};
assign irq_id_lvl_10 [0] = {PLIC_IRQ_NUM_LOG2{1'b0}};
assign irq_ip_lvl_10 [0] = 1'b0;
for(i=1; i<PLIC_IRQ_NUM;i=i+1) begin: tie_input//{
// The priority will be masked to zero, if the IE is not set
assign irq_prio_lvl_10[i] = irq_prio_masked[i] & {PLIC_PRIO_WIDTH{irq_enab_r[i/32][i%32]}};
assign irq_id_lvl_10 [i] = i[PLIC_IRQ_NUM_LOG2-1:0];
assign irq_ip_lvl_10 [i] = irq_pend_r[i] & irq_enab_r[i/32][i%32];
end//}
for(i=PLIC_IRQ_NUM; i<1024;i=i+1) begin: tie_unused_tozero//{
assign irq_prio_lvl_10[i] = {PLIC_PRIO_WIDTH{1'b0}};
assign irq_id_lvl_10 [i] = i[PLIC_IRQ_NUM_LOG2-1:0];
assign irq_ip_lvl_10 [i] = 1'b0;
end//}
// Generate the level-9 comp
for(i=0; i<512;i=i+1) begin: lvl_9_comp_gen//{
assign irq_prio_lvl_9_lt[i] = (irq_prio_lvl_10[2*i] < irq_prio_lvl_10[(2*i)+1]);
assign irq_prio_lvl_9[i] = irq_prio_lvl_9_lt[i] ? irq_prio_lvl_10[(2*i)+1] : irq_prio_lvl_10[2*i];
assign irq_id_lvl_9 [i] = irq_prio_lvl_9_lt[i] ? irq_id_lvl_10 [(2*i)+1] : irq_id_lvl_10 [2*i];
assign irq_ip_lvl_9 [i] = irq_prio_lvl_9_lt[i] ? irq_ip_lvl_10 [(2*i)+1] : irq_ip_lvl_10 [2*i];
end//}
// Generate the level-8 comp
for(i=0; i<256;i=i+1) begin: lvl_8_comp_gen//{
assign irq_prio_lvl_8_lt[i] = (irq_prio_lvl_9[2*i] < irq_prio_lvl_9[(2*i)+1]);
assign irq_prio_lvl_8[i] = irq_prio_lvl_8_lt[i] ? irq_prio_lvl_9[(2*i)+1] : irq_prio_lvl_9[2*i];
assign irq_id_lvl_8 [i] = irq_prio_lvl_8_lt[i] ? irq_id_lvl_9 [(2*i)+1] : irq_id_lvl_9 [2*i];
assign irq_ip_lvl_8 [i] = irq_prio_lvl_8_lt[i] ? irq_ip_lvl_9 [(2*i)+1] : irq_ip_lvl_9 [2*i];
end//}
// Generate the level-7 comp
for(i=0; i<128;i=i+1) begin: lvl_7_comp_gen//{
assign irq_prio_lvl_7_lt[i] = (irq_prio_lvl_8[2*i] < irq_prio_lvl_8[(2*i)+1]);
assign irq_prio_lvl_7[i] = irq_prio_lvl_7_lt[i] ? irq_prio_lvl_8[(2*i)+1] : irq_prio_lvl_8[2*i];
assign irq_id_lvl_7 [i] = irq_prio_lvl_7_lt[i] ? irq_id_lvl_8 [(2*i)+1] : irq_id_lvl_8 [2*i];
assign irq_ip_lvl_7 [i] = irq_prio_lvl_7_lt[i] ? irq_ip_lvl_8 [(2*i)+1] : irq_ip_lvl_8 [2*i];
end//}
// Generate the level-6 comp
for(i=0; i<64;i=i+1) begin: lvl_6_comp_gen//{
assign irq_prio_lvl_6_lt[i] = (irq_prio_lvl_7[2*i] < irq_prio_lvl_7[(2*i)+1]);
assign irq_prio_lvl_6[i] = irq_prio_lvl_6_lt[i] ? irq_prio_lvl_7[(2*i)+1] : irq_prio_lvl_7[2*i];
assign irq_id_lvl_6 [i] = irq_prio_lvl_6_lt[i] ? irq_id_lvl_7 [(2*i)+1] : irq_id_lvl_7 [2*i];
assign irq_ip_lvl_6 [i] = irq_prio_lvl_6_lt[i] ? irq_ip_lvl_7 [(2*i)+1] : irq_ip_lvl_7 [2*i];
end//}
// Generate the level-5 comp
for(i=0; i<32;i=i+1) begin: lvl_5_comp_gen//{
assign irq_prio_lvl_5_lt[i] = (irq_prio_lvl_6[2*i] < irq_prio_lvl_6[(2*i)+1]);
assign irq_prio_lvl_5[i] = irq_prio_lvl_5_lt[i] ? irq_prio_lvl_6[(2*i)+1] : irq_prio_lvl_6[2*i];
assign irq_id_lvl_5 [i] = irq_prio_lvl_5_lt[i] ? irq_id_lvl_6 [(2*i)+1] : irq_id_lvl_6 [2*i];
assign irq_ip_lvl_5 [i] = irq_prio_lvl_5_lt[i] ? irq_ip_lvl_6 [(2*i)+1] : irq_ip_lvl_6 [2*i];
end//}
// Generate the level-4 comp
for(i=0; i<16;i=i+1) begin: lvl_4_comp_gen//{
assign irq_prio_lvl_4_lt[i] = (irq_prio_lvl_5[2*i] < irq_prio_lvl_5[(2*i)+1]);
assign irq_prio_lvl_4[i] = irq_prio_lvl_4_lt[i] ? irq_prio_lvl_5[(2*i)+1] : irq_prio_lvl_5[2*i];
assign irq_id_lvl_4 [i] = irq_prio_lvl_4_lt[i] ? irq_id_lvl_5 [(2*i)+1] : irq_id_lvl_5 [2*i];
assign irq_ip_lvl_4 [i] = irq_prio_lvl_4_lt[i] ? irq_ip_lvl_5 [(2*i)+1] : irq_ip_lvl_5 [2*i];
end//}
// Generate the level-3 comp
for(i=0; i<8;i=i+1) begin: lvl_3_comp_gen//{
assign irq_prio_lvl_3_lt[i] = (irq_prio_lvl_4[2*i] < irq_prio_lvl_4[(2*i)+1]);
assign irq_prio_lvl_3[i] = irq_prio_lvl_3_lt[i] ? irq_prio_lvl_4[(2*i)+1] : irq_prio_lvl_4[2*i];
assign irq_id_lvl_3 [i] = irq_prio_lvl_3_lt[i] ? irq_id_lvl_4 [(2*i)+1] : irq_id_lvl_4 [2*i];
assign irq_ip_lvl_3 [i] = irq_prio_lvl_3_lt[i] ? irq_ip_lvl_4 [(2*i)+1] : irq_ip_lvl_4 [2*i];
end//}
// Generate the level-2 comp
for(i=0; i<4;i=i+1) begin: lvl_2_comp_gen//{
assign irq_prio_lvl_2_lt[i] = (irq_prio_lvl_3[2*i] < irq_prio_lvl_3[(2*i)+1]);
assign irq_prio_lvl_2[i] = irq_prio_lvl_2_lt[i] ? irq_prio_lvl_3[(2*i)+1] : irq_prio_lvl_3[2*i];
assign irq_id_lvl_2 [i] = irq_prio_lvl_2_lt[i] ? irq_id_lvl_3 [(2*i)+1] : irq_id_lvl_3 [2*i];
assign irq_ip_lvl_2 [i] = irq_prio_lvl_2_lt[i] ? irq_ip_lvl_3 [(2*i)+1] : irq_ip_lvl_3 [2*i];
end//}
// Generate the level-1 comp
for(i=0; i<2;i=i+1) begin: lvl_1_comp_gen//{
assign irq_prio_lvl_1_lt[i] = (irq_prio_lvl_2[2*i] < irq_prio_lvl_2[(2*i)+1]);
assign irq_prio_lvl_1[i] = irq_prio_lvl_1_lt[i] ? irq_prio_lvl_2[(2*i)+1] : irq_prio_lvl_2[2*i];
assign irq_id_lvl_1 [i] = irq_prio_lvl_1_lt[i] ? irq_id_lvl_2 [(2*i)+1] : irq_id_lvl_2 [2*i];
assign irq_ip_lvl_1 [i] = irq_prio_lvl_1_lt[i] ? irq_ip_lvl_2 [(2*i)+1] : irq_ip_lvl_2 [2*i];
end//}
assign irq_prio_top_lt = (irq_prio_lvl_1[0] < irq_prio_lvl_1[1]);
assign irq_prio_top = irq_prio_top_lt ? irq_prio_lvl_1[1] : irq_prio_lvl_1[0];
assign irq_id_top = irq_prio_top_lt ? irq_id_lvl_1 [1] : irq_id_lvl_1 [0];
assign irq_ip_top = irq_prio_top_lt ? irq_ip_lvl_1 [1] : irq_ip_lvl_1 [0];
assign irq_o = irq_ip_top & (irq_prio_top > irq_thod_r);
assign irq_id = irq_id_top;
endgenerate
///////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////
// Implement the ICB bus
//
// The address map
generate
//
// 0x0C00_0004 source 1 priority
// 0x0C00_0008 source 2 priority
// ...
// 0x0C00_0FFC source 1023 priority
for(i=0; i<PLIC_IRQ_NUM;i=i+1) begin: sel_prio//{
assign icb_cmd_sel_prio[i] = (icb_cmd_addr == ($unsigned(i) * 4));
end//}
//
//0x0C00 1000 Start of pending array
//... (read-only)
//0x0C00 107C End of pending array
for(i=0; i<(PLIC_PEND_ARRAY);i=i+1) begin: sel_pend//{
assign icb_cmd_sel_pend[i] = (icb_cmd_addr == (($unsigned(i) * 4) + 24'h1000));
end//}
//
//0x0C00 1000 Start of target 0 enable array
//0x0C00 107C End of target 0 enable array
//.... target 1
//.... target 2
for(i=0; i<(PLIC_PEND_ARRAY);i=i+1) begin: sel_enab_i//{
assign icb_cmd_sel_enab[i] = (icb_cmd_addr == (($unsigned(i) * 4) + 24'h2000));
end//}
//
// 0x0C20 0000 target 0 priority threshold
// 0x0C20 0004 target 0 claim/complete
// 0x0C20 1000 target 1 priority threshold
// 0x0C20 1004 target 1 claim/complete
assign icb_cmd_sel_thod = (icb_cmd_addr == (24'h20_0000));
assign icb_cmd_sel_clam = (icb_cmd_addr == (24'h20_0004));
endgenerate
///////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////
// Implement the rdata mux
//
reg [32-1:0] rsp_rdata_prio;
reg [32-1:0] rsp_rdata_pend;
reg [32-1:0] rsp_rdata_targ;
always @* begin:rdat_prio_mux//{
rsp_rdata_prio = 32'b0;
for(ii=0; ii<PLIC_IRQ_NUM;ii=ii+1) begin: sel_prio//{
rsp_rdata_prio = rsp_rdata_prio | ({32{icb_cmd_sel_prio[ii]}} & irq_prio_r[ii] );
end//}
end//}
always @* begin:rdat_pend_mux//{
rsp_rdata_pend = 32'b0;
for(ii=0; ii<(PLIC_PEND_ARRAY);ii=ii+1) begin: sel_pend//{
rsp_rdata_pend = rsp_rdata_pend | ({32{icb_cmd_sel_pend[ii]}} &
{
irq_pend_r[ii*32+31], irq_pend_r[ii*32+30], irq_pend_r[ii*32+29], irq_pend_r[ii*32+28],
irq_pend_r[ii*32+27], irq_pend_r[ii*32+26], irq_pend_r[ii*32+25], irq_pend_r[ii*32+24],
irq_pend_r[ii*32+23], irq_pend_r[ii*32+22], irq_pend_r[ii*32+21], irq_pend_r[ii*32+20],
irq_pend_r[ii*32+19], irq_pend_r[ii*32+18], irq_pend_r[ii*32+17], irq_pend_r[ii*32+16],
irq_pend_r[ii*32+15], irq_pend_r[ii*32+14], irq_pend_r[ii*32+13], irq_pend_r[ii*32+12],
irq_pend_r[ii*32+11], irq_pend_r[ii*32+10], irq_pend_r[ii*32+09], irq_pend_r[ii*32+08],
irq_pend_r[ii*32+07], irq_pend_r[ii*32+06], irq_pend_r[ii*32+05], irq_pend_r[ii*32+04],
irq_pend_r[ii*32+03], irq_pend_r[ii*32+02], irq_pend_r[ii*32+01], irq_pend_r[ii*32+00]
});
end//}
end//}
always @* begin:rdat_targ_mux//{
rsp_rdata_targ = 32'b0;
rsp_rdata_targ = rsp_rdata_targ | ({32{icb_cmd_sel_thod}} & irq_thod_r );
rsp_rdata_targ = rsp_rdata_targ | ({32{icb_cmd_sel_clam}} & plic_irq_id);
for(ii=0; ii<(PLIC_PEND_ARRAY);ii=ii+1) begin: sel_enab_i//{
rsp_rdata_targ = rsp_rdata_targ | ({32{icb_cmd_sel_enab[ii]}} & irq_enab_r[ii]);
end//}
//
end//}
wire [32-1:0] rsp_rdata = rsp_rdata_prio | rsp_rdata_pend | rsp_rdata_targ;
generate
if(PLIC_ICB_RSP_FLOP == 1) begin: flop_icb_rsp
sirv_gnrl_pipe_stage # (
.CUT_READY(1),
.DP(1),
.DW(32)
) u_buf_icb_rsp_buf(
.i_vld(icb_cmd_valid),
.i_rdy(icb_cmd_ready),
.i_dat(rsp_rdata),
.o_vld(icb_rsp_valid),
.o_rdy(icb_rsp_ready),
.o_dat(icb_rsp_rdata),
.clk (clk ),
.rst_n(rst_n)
);
end
else begin: no_flop_icb_rsp
// Directly connect the response channel with the command channel for handshake
assign icb_rsp_valid = icb_cmd_valid;
assign icb_cmd_ready = icb_rsp_ready;
assign icb_rsp_rdata = rsp_rdata;
end
endgenerate
generate
//
for(i=0; i<PLIC_IRQ_NUM;i=i+1) begin: claim_complete_gen//{
always @* begin:claim_complete//{
icb_claim_irq [i] = 1'b0;
icb_complete_irq[i] = 1'b0;
// The read data (claimed ID) is equal to the interrupt source ID
icb_claim_irq [i] = icb_claim_irq[i] | ((icb_rsp_rdata == i) & icb_cmd_sel_clam & icb_cmd_rd_hsked);
// The write data (complete ID) is equal to the interrupt source ID
icb_complete_irq[i] = icb_complete_irq[i] | ((icb_cmd_wdata[PLIC_IRQ_NUM_LOG2-1:0] == i) & icb_cmd_sel_clam & icb_cmd_wr_hsked);
end//}
end//}
endgenerate
endmodule
|
module e203_extend_csr(
// The Handshake Interface
input eai_csr_valid,
output eai_csr_ready,
input [31:0] eai_csr_addr,
input eai_csr_wr,
input [31:0] eai_csr_wdata,
output [31:0] eai_csr_rdata,
input clk,
input rst_n
);
assign eai_csr_ready = 1'b1;
assign eai_csr_rdata = 32'b0;
endmodule
|
module sirv_ResetCatchAndSync_2(
input clock,
input reset,
input test_mode,
output io_sync_reset
);
wire reset_n_catch_reg_clock;
wire reset_n_catch_reg_reset;
wire [19:0] reset_n_catch_reg_io_d;
wire [19:0] reset_n_catch_reg_io_q;
wire reset_n_catch_reg_io_en;
wire [18:0] T_6;
wire [19:0] T_7;
wire T_8;
wire T_9;
sirv_AsyncResetRegVec_129 reset_n_catch_reg (
.clock(reset_n_catch_reg_clock),
.reset(reset_n_catch_reg_reset),
.io_d(reset_n_catch_reg_io_d),
.io_q(reset_n_catch_reg_io_q),
.io_en(reset_n_catch_reg_io_en)
);
assign io_sync_reset = test_mode ? reset : T_9;
assign reset_n_catch_reg_clock = clock;
assign reset_n_catch_reg_reset = reset;
assign reset_n_catch_reg_io_d = T_7;
assign reset_n_catch_reg_io_en = 1'h1;
assign T_6 = reset_n_catch_reg_io_q[19:1];
assign T_7 = {1'h1,T_6};
assign T_8 = reset_n_catch_reg_io_q[0];
assign T_9 = ~ T_8;
endmodule
|
module sirv_uartrx(
input clock,
input reset,
input io_en,
input io_in,
output io_out_valid,
output [7:0] io_out_bits,
input [15:0] io_div
);
reg [1:0] debounce;
reg [31:0] GEN_7;
wire debounce_max;
wire debounce_min;
reg [11:0] prescaler;
reg [31:0] GEN_20;
wire start;
wire busy;
wire T_21;
wire pulse;
wire [12:0] T_23;
wire [11:0] T_24;
wire [11:0] GEN_0;
wire T_25;
wire [11:0] T_26;
wire [11:0] GEN_1;
reg [2:0] sample;
reg [31:0] GEN_23;
wire T_28;
wire T_29;
wire T_30;
wire T_31;
wire T_32;
wire T_33;
wire T_34;
wire T_35;
wire [3:0] T_36;
wire [3:0] GEN_2;
reg [4:0] timer;
reg [31:0] GEN_28;
reg [3:0] counter;
reg [31:0] GEN_43;
reg [7:0] shifter;
reg [31:0] GEN_44;
wire T_41;
wire expire;
wire sched;
wire [5:0] T_44;
wire [4:0] T_45;
wire [4:0] GEN_3;
wire [4:0] GEN_4;
reg valid;
reg [31:0] GEN_45;
reg [1:0] state;
reg [31:0] GEN_46;
wire T_50;
wire T_52;
wire T_54;
wire T_56;
wire T_57;
wire [2:0] T_59;
wire [1:0] T_60;
wire [1:0] GEN_5;
wire [2:0] T_64;
wire [1:0] T_65;
wire [1:0] GEN_6;
wire [4:0] GEN_8;
wire [1:0] GEN_9;
wire [1:0] GEN_10;
wire GEN_11;
wire [4:0] GEN_12;
wire [1:0] GEN_13;
wire [1:0] GEN_14;
wire GEN_15;
wire [4:0] GEN_16;
wire T_68;
wire [1:0] GEN_17;
wire T_72;
wire [1:0] GEN_18;
wire [3:0] GEN_19;
wire [1:0] GEN_21;
wire [3:0] GEN_22;
wire GEN_24;
wire [1:0] GEN_25;
wire [3:0] GEN_26;
wire T_74;
wire [4:0] T_77;
wire [3:0] T_78;
wire T_80;
wire [1:0] GEN_27;
wire T_83;
wire [6:0] T_84;
wire [7:0] T_85;
wire [7:0] GEN_29;
wire GEN_30;
wire [3:0] GEN_31;
wire [1:0] GEN_32;
wire GEN_33;
wire [7:0] GEN_34;
wire GEN_35;
wire GEN_36;
wire [3:0] GEN_37;
wire [1:0] GEN_38;
wire GEN_39;
wire [7:0] GEN_40;
wire GEN_41;
wire T_88;
wire [1:0] GEN_42;
assign io_out_valid = valid;
assign io_out_bits = shifter;
assign debounce_max = debounce == 2'h3;
assign debounce_min = debounce == 2'h0;
assign start = GEN_15;
assign busy = GEN_36;
assign T_21 = prescaler == 12'h0;
assign pulse = T_21 & busy;
assign T_23 = prescaler - 12'h1;
assign T_24 = T_23[11:0];
assign GEN_0 = busy ? T_24 : prescaler;
assign T_25 = start | pulse;
assign T_26 = io_div[15:4];
assign GEN_1 = T_25 ? T_26 : GEN_0;
assign T_28 = sample[0];
assign T_29 = sample[1];
assign T_30 = sample[2];
assign T_31 = T_28 & T_29;
assign T_32 = T_28 & T_30;
assign T_33 = T_31 | T_32;
assign T_34 = T_29 & T_30;
assign T_35 = T_33 | T_34;
assign T_36 = {sample,io_in};
assign GEN_2 = pulse ? T_36 : {{1'd0}, sample};
assign T_41 = timer == 5'h0;
assign expire = T_41 & pulse;
assign sched = GEN_41;
assign T_44 = timer - 5'h1;
assign T_45 = T_44[4:0];
assign GEN_3 = pulse ? T_45 : timer;
assign GEN_4 = sched ? 5'hf : GEN_3;
assign T_50 = 2'h0 == state;
assign T_52 = io_in == 1'h0;
assign T_54 = T_52 == 1'h0;
assign T_56 = debounce_min == 1'h0;
assign T_57 = T_54 & T_56;
assign T_59 = debounce - 2'h1;
assign T_60 = T_59[1:0];
assign GEN_5 = T_57 ? T_60 : debounce;
assign T_64 = debounce + 2'h1;
assign T_65 = T_64[1:0];
assign GEN_6 = debounce_max ? 2'h1 : state;
assign GEN_8 = debounce_max ? 5'h8 : GEN_4;
assign GEN_9 = T_52 ? T_65 : GEN_5;
assign GEN_10 = T_52 ? GEN_6 : state;
assign GEN_11 = T_52 ? debounce_max : 1'h0;
assign GEN_12 = T_52 ? GEN_8 : GEN_4;
assign GEN_13 = T_50 ? GEN_9 : debounce;
assign GEN_14 = T_50 ? GEN_10 : state;
assign GEN_15 = T_50 ? GEN_11 : 1'h0;
assign GEN_16 = T_50 ? GEN_12 : GEN_4;
assign T_68 = 2'h1 == state;
assign GEN_17 = T_35 ? 2'h0 : GEN_14;
assign T_72 = T_35 == 1'h0;
assign GEN_18 = T_72 ? 2'h2 : GEN_17;
assign GEN_19 = T_72 ? 4'h8 : counter;
assign GEN_21 = expire ? GEN_18 : GEN_14;
assign GEN_22 = expire ? GEN_19 : counter;
assign GEN_24 = T_68 ? expire : 1'h0;
assign GEN_25 = T_68 ? GEN_21 : GEN_14;
assign GEN_26 = T_68 ? GEN_22 : counter;
assign T_74 = 2'h2 == state;
assign T_77 = counter - 4'h1;
assign T_78 = T_77[3:0];
assign T_80 = counter == 4'h0;
assign GEN_27 = T_80 ? 2'h0 : GEN_25;
assign T_83 = T_80 == 1'h0;
assign T_84 = shifter[7:1];
assign T_85 = {T_35,T_84};
assign GEN_29 = T_83 ? T_85 : shifter;
assign GEN_30 = T_83 ? 1'h1 : GEN_24;
assign GEN_31 = expire ? T_78 : GEN_26;
assign GEN_32 = expire ? GEN_27 : GEN_25;
assign GEN_33 = expire ? T_80 : 1'h0;
assign GEN_34 = expire ? GEN_29 : shifter;
assign GEN_35 = expire ? GEN_30 : GEN_24;
assign GEN_36 = T_74 ? 1'h1 : T_68;
assign GEN_37 = T_74 ? GEN_31 : GEN_26;
assign GEN_38 = T_74 ? GEN_32 : GEN_25;
assign GEN_39 = T_74 ? GEN_33 : 1'h0;
assign GEN_40 = T_74 ? GEN_34 : shifter;
assign GEN_41 = T_74 ? GEN_35 : GEN_24;
assign T_88 = io_en == 1'h0;
assign GEN_42 = T_88 ? 2'h0 : GEN_13;
always @(posedge clock or posedge reset)
if (reset) begin
debounce <= 2'h0;
end else begin
if (T_88) begin
debounce <= 2'h0;
end else begin
if (T_50) begin
if (T_52) begin
debounce <= T_65;
end else begin
if (T_57) begin
debounce <= T_60;
end
end
end
end
end
always @(posedge clock or posedge reset)
if (reset) begin
prescaler <= 12'h0;
end else begin
if (T_25) begin
prescaler <= T_26;
end else begin
if (busy) begin
prescaler <= T_24;
end
end
end
always @(posedge clock or posedge reset)
if (reset) begin
sample <= 3'b0;
timer <= 5'h0;
counter <= 4'b0;
shifter <= 8'b0;
end
else begin
sample <= GEN_2[2:0];
if (T_50) begin
if (T_52) begin
if (debounce_max) begin
timer <= 5'h8;
end else begin
if (sched) begin
timer <= 5'hf;
end else begin
if (pulse) begin
timer <= T_45;
end
end
end
end else begin
if (sched) begin
timer <= 5'hf;
end else begin
if (pulse) begin
timer <= T_45;
end
end
end
end else begin
if (sched) begin
timer <= 5'hf;
end else begin
if (pulse) begin
timer <= T_45;
end
end
end
if (T_74) begin
if (expire) begin
counter <= T_78;
end else begin
if (T_68) begin
if (expire) begin
if (T_72) begin
counter <= 4'h8;
end
end
end
end
end else begin
if (T_68) begin
if (expire) begin
if (T_72) begin
counter <= 4'h8;
end
end
end
end
if (T_74) begin
if (expire) begin
if (T_83) begin
shifter <= T_85;
end
end
end
end
always @(posedge clock or posedge reset)
if (reset) begin
valid <= 1'h0;
end else begin
if (T_74) begin
if (expire) begin
valid <= T_80;
end else begin
valid <= 1'h0;
end
end else begin
valid <= 1'h0;
end
end
always @(posedge clock or posedge reset)
if (reset) begin
state <= 2'h0;
end else begin
if (T_74) begin
if (expire) begin
if (T_80) begin
state <= 2'h0;
end else begin
if (T_68) begin
if (expire) begin
if (T_72) begin
state <= 2'h2;
end else begin
if (T_35) begin
state <= 2'h0;
end else begin
if (T_50) begin
if (T_52) begin
if (debounce_max) begin
state <= 2'h1;
end
end
end
end
end
end else begin
if (T_50) begin
if (T_52) begin
if (debounce_max) begin
state <= 2'h1;
end
end
end
end
end else begin
if (T_50) begin
if (T_52) begin
if (debounce_max) begin
state <= 2'h1;
end
end
end
end
end
end else begin
if (T_68) begin
if (expire) begin
if (T_72) begin
state <= 2'h2;
end else begin
if (T_35) begin
state <= 2'h0;
end else begin
if (T_50) begin
if (T_52) begin
if (debounce_max) begin
state <= 2'h1;
end
end
end
end
end
end else begin
state <= GEN_14;
end
end else begin
state <= GEN_14;
end
end
end else begin
if (T_68) begin
if (expire) begin
if (T_72) begin
state <= 2'h2;
end else begin
if (T_35) begin
state <= 2'h0;
end else begin
state <= GEN_14;
end
end
end else begin
state <= GEN_14;
end
end else begin
state <= GEN_14;
end
end
end
endmodule
|
module sirv_qspi_1cs_top(
input clk,
input rst_n,
input i_icb_cmd_valid,
output i_icb_cmd_ready,
input [32-1:0] i_icb_cmd_addr,
input i_icb_cmd_read,
input [32-1:0] i_icb_cmd_wdata,
output i_icb_rsp_valid,
input i_icb_rsp_ready,
output [32-1:0] i_icb_rsp_rdata,
output io_port_sck,
input io_port_dq_0_i,
output io_port_dq_0_o,
output io_port_dq_0_oe,
input io_port_dq_1_i,
output io_port_dq_1_o,
output io_port_dq_1_oe,
input io_port_dq_2_i,
output io_port_dq_2_o,
output io_port_dq_2_oe,
input io_port_dq_3_i,
output io_port_dq_3_o,
output io_port_dq_3_oe,
output io_port_cs_0,
output io_tl_i_0_0
);
wire io_tl_r_0_a_ready;
assign i_icb_cmd_ready = io_tl_r_0_a_ready;
wire io_tl_r_0_a_valid = i_icb_cmd_valid;
wire [2:0] io_tl_r_0_a_bits_opcode = i_icb_cmd_read ? 3'h4 : 3'h0;
wire [2:0] io_tl_r_0_a_bits_param = 3'b0;
wire [2:0] io_tl_r_0_a_bits_size = 3'd2;
wire [4:0] io_tl_r_0_a_bits_source = 5'b0;
wire [28:0] io_tl_r_0_a_bits_address = i_icb_cmd_addr[28:0];
wire [3:0] io_tl_r_0_a_bits_mask = 4'b1111;
wire [31:0] io_tl_r_0_a_bits_data = i_icb_cmd_wdata;
wire io_tl_r_0_d_ready = i_icb_rsp_ready;
wire [2:0] io_tl_r_0_d_bits_opcode;
wire [1:0] io_tl_r_0_d_bits_param;
wire [2:0] io_tl_r_0_d_bits_size;
wire [4:0] io_tl_r_0_d_bits_source;
wire io_tl_r_0_d_bits_sink;
wire [1:0] io_tl_r_0_d_bits_addr_lo;
wire [31:0] io_tl_r_0_d_bits_data;
wire io_tl_r_0_d_bits_error;
wire io_tl_r_0_d_valid;
assign i_icb_rsp_valid = io_tl_r_0_d_valid;
assign i_icb_rsp_rdata = io_tl_r_0_d_bits_data;
// Not used
wire io_tl_r_0_b_ready = 1'b0;
wire io_tl_r_0_b_valid;
wire [2:0] io_tl_r_0_b_bits_opcode;
wire [1:0] io_tl_r_0_b_bits_param;
wire [2:0] io_tl_r_0_b_bits_size;
wire [4:0] io_tl_r_0_b_bits_source;
wire [28:0] io_tl_r_0_b_bits_address;
wire [3:0] io_tl_r_0_b_bits_mask;
wire [31:0] io_tl_r_0_b_bits_data;
// Not used
wire io_tl_r_0_c_ready;
wire io_tl_r_0_c_valid = 1'b0;
wire [2:0] io_tl_r_0_c_bits_opcode = 3'b0;
wire [2:0] io_tl_r_0_c_bits_param = 3'b0;
wire [2:0] io_tl_r_0_c_bits_size = 3'd2;
wire [4:0] io_tl_r_0_c_bits_source = 5'b0;
wire [28:0] io_tl_r_0_c_bits_address = 29'b0;
wire [31:0] io_tl_r_0_c_bits_data = 32'b0;
wire io_tl_r_0_c_bits_error = 1'b0;
// Not used
wire io_tl_r_0_e_ready;
wire io_tl_r_0_e_valid = 1'b0;
wire io_tl_r_0_e_bits_sink = 1'b0;
sirv_qspi_1cs u_sirv_qspi_1cs(
.clock (clk ),
.reset (~rst_n ),
.io_tl_r_0_a_ready (io_tl_r_0_a_ready ),
.io_tl_r_0_a_valid (io_tl_r_0_a_valid ),
.io_tl_r_0_a_bits_opcode (io_tl_r_0_a_bits_opcode ),
.io_tl_r_0_a_bits_param (io_tl_r_0_a_bits_param ),
.io_tl_r_0_a_bits_size (io_tl_r_0_a_bits_size ),
.io_tl_r_0_a_bits_source (io_tl_r_0_a_bits_source ),
.io_tl_r_0_a_bits_address (io_tl_r_0_a_bits_address ),
.io_tl_r_0_a_bits_mask (io_tl_r_0_a_bits_mask ),
.io_tl_r_0_a_bits_data (io_tl_r_0_a_bits_data ),
.io_tl_r_0_b_ready (io_tl_r_0_b_ready ),
.io_tl_r_0_b_valid (io_tl_r_0_b_valid ),
.io_tl_r_0_b_bits_opcode (io_tl_r_0_b_bits_opcode ),
.io_tl_r_0_b_bits_param (io_tl_r_0_b_bits_param ),
.io_tl_r_0_b_bits_size (io_tl_r_0_b_bits_size ),
.io_tl_r_0_b_bits_source (io_tl_r_0_b_bits_source ),
.io_tl_r_0_b_bits_address (io_tl_r_0_b_bits_address ),
.io_tl_r_0_b_bits_mask (io_tl_r_0_b_bits_mask ),
.io_tl_r_0_b_bits_data (io_tl_r_0_b_bits_data ),
.io_tl_r_0_c_ready (io_tl_r_0_c_ready ),
.io_tl_r_0_c_valid (io_tl_r_0_c_valid ),
.io_tl_r_0_c_bits_opcode (io_tl_r_0_c_bits_opcode ),
.io_tl_r_0_c_bits_param (io_tl_r_0_c_bits_param ),
.io_tl_r_0_c_bits_size (io_tl_r_0_c_bits_size ),
.io_tl_r_0_c_bits_source (io_tl_r_0_c_bits_source ),
.io_tl_r_0_c_bits_address (io_tl_r_0_c_bits_address ),
.io_tl_r_0_c_bits_data (io_tl_r_0_c_bits_data ),
.io_tl_r_0_c_bits_error (io_tl_r_0_c_bits_error ),
.io_tl_r_0_d_ready (io_tl_r_0_d_ready ),
.io_tl_r_0_d_valid (io_tl_r_0_d_valid ),
.io_tl_r_0_d_bits_opcode (io_tl_r_0_d_bits_opcode ),
.io_tl_r_0_d_bits_param (io_tl_r_0_d_bits_param ),
.io_tl_r_0_d_bits_size (io_tl_r_0_d_bits_size ),
.io_tl_r_0_d_bits_source (io_tl_r_0_d_bits_source ),
.io_tl_r_0_d_bits_sink (io_tl_r_0_d_bits_sink ),
.io_tl_r_0_d_bits_addr_lo (io_tl_r_0_d_bits_addr_lo ),
.io_tl_r_0_d_bits_data (io_tl_r_0_d_bits_data ),
.io_tl_r_0_d_bits_error (io_tl_r_0_d_bits_error ),
.io_tl_r_0_e_ready (io_tl_r_0_e_ready ),
.io_tl_r_0_e_valid (io_tl_r_0_e_valid ),
.io_tl_r_0_e_bits_sink (io_tl_r_0_e_bits_sink ),
.io_port_sck (io_port_sck ),
.io_port_dq_0_i (io_port_dq_0_i ),
.io_port_dq_0_o (io_port_dq_0_o ),
.io_port_dq_0_oe (io_port_dq_0_oe),
.io_port_dq_1_i (io_port_dq_1_i ),
.io_port_dq_1_o (io_port_dq_1_o ),
.io_port_dq_1_oe (io_port_dq_1_oe),
.io_port_dq_2_i (io_port_dq_2_i ),
.io_port_dq_2_o (io_port_dq_2_o ),
.io_port_dq_2_oe (io_port_dq_2_oe),
.io_port_dq_3_i (io_port_dq_3_i ),
.io_port_dq_3_o (io_port_dq_3_o ),
.io_port_dq_3_oe (io_port_dq_3_oe),
.io_port_cs_0 (io_port_cs_0 ),
.io_tl_i_0_0 (io_tl_i_0_0 )
);
endmodule
|
module e203_exu_oitf (
output dis_ready,
input dis_ena,
input ret_ena,
output [`E203_ITAG_WIDTH-1:0] dis_ptr,
output [`E203_ITAG_WIDTH-1:0] ret_ptr,
output [`E203_RFIDX_WIDTH-1:0] ret_rdidx,
output ret_rdwen,
output ret_rdfpu,
output [`E203_PC_SIZE-1:0] ret_pc,
input disp_i_rs1en,
input disp_i_rs2en,
input disp_i_rs3en,
input disp_i_rdwen,
input disp_i_rs1fpu,
input disp_i_rs2fpu,
input disp_i_rs3fpu,
input disp_i_rdfpu,
input [`E203_RFIDX_WIDTH-1:0] disp_i_rs1idx,
input [`E203_RFIDX_WIDTH-1:0] disp_i_rs2idx,
input [`E203_RFIDX_WIDTH-1:0] disp_i_rs3idx,
input [`E203_RFIDX_WIDTH-1:0] disp_i_rdidx,
input [`E203_PC_SIZE -1:0] disp_i_pc,
output oitfrd_match_disprs1,
output oitfrd_match_disprs2,
output oitfrd_match_disprs3,
output oitfrd_match_disprd,
output oitf_empty,
input clk,
input rst_n
);
wire [`E203_OITF_DEPTH-1:0] vld_set;
wire [`E203_OITF_DEPTH-1:0] vld_clr;
wire [`E203_OITF_DEPTH-1:0] vld_ena;
wire [`E203_OITF_DEPTH-1:0] vld_nxt;
wire [`E203_OITF_DEPTH-1:0] vld_r;
wire [`E203_OITF_DEPTH-1:0] rdwen_r;
wire [`E203_OITF_DEPTH-1:0] rdfpu_r;
wire [`E203_RFIDX_WIDTH-1:0] rdidx_r[`E203_OITF_DEPTH-1:0];
// The PC here is to be used at wback stage to track out the
// PC of exception of long-pipe instruction
wire [`E203_PC_SIZE-1:0] pc_r[`E203_OITF_DEPTH-1:0];
wire alc_ptr_ena = dis_ena;
wire ret_ptr_ena = ret_ena;
wire oitf_full ;
wire [`E203_ITAG_WIDTH-1:0] alc_ptr_r;
wire [`E203_ITAG_WIDTH-1:0] ret_ptr_r;
generate
if(`E203_OITF_DEPTH > 1) begin: depth_gt1//{
wire alc_ptr_flg_r;
wire alc_ptr_flg_nxt = ~alc_ptr_flg_r;
wire alc_ptr_flg_ena = (alc_ptr_r == ($unsigned(`E203_OITF_DEPTH-1))) & alc_ptr_ena;
sirv_gnrl_dfflr #(1) alc_ptr_flg_dfflrs(alc_ptr_flg_ena, alc_ptr_flg_nxt, alc_ptr_flg_r, clk, rst_n);
wire [`E203_ITAG_WIDTH-1:0] alc_ptr_nxt;
assign alc_ptr_nxt = alc_ptr_flg_ena ? `E203_ITAG_WIDTH'b0 : (alc_ptr_r + 1'b1);
sirv_gnrl_dfflr #(`E203_ITAG_WIDTH) alc_ptr_dfflrs(alc_ptr_ena, alc_ptr_nxt, alc_ptr_r, clk, rst_n);
wire ret_ptr_flg_r;
wire ret_ptr_flg_nxt = ~ret_ptr_flg_r;
wire ret_ptr_flg_ena = (ret_ptr_r == ($unsigned(`E203_OITF_DEPTH-1))) & ret_ptr_ena;
sirv_gnrl_dfflr #(1) ret_ptr_flg_dfflrs(ret_ptr_flg_ena, ret_ptr_flg_nxt, ret_ptr_flg_r, clk, rst_n);
wire [`E203_ITAG_WIDTH-1:0] ret_ptr_nxt;
assign ret_ptr_nxt = ret_ptr_flg_ena ? `E203_ITAG_WIDTH'b0 : (ret_ptr_r + 1'b1);
sirv_gnrl_dfflr #(`E203_ITAG_WIDTH) ret_ptr_dfflrs(ret_ptr_ena, ret_ptr_nxt, ret_ptr_r, clk, rst_n);
assign oitf_empty = (ret_ptr_r == alc_ptr_r) & (ret_ptr_flg_r == alc_ptr_flg_r);
assign oitf_full = (ret_ptr_r == alc_ptr_r) & (~(ret_ptr_flg_r == alc_ptr_flg_r));
end//}
else begin: depth_eq1//}{
assign alc_ptr_r =1'b0;
assign ret_ptr_r =1'b0;
assign oitf_empty = ~vld_r[0];
assign oitf_full = vld_r[0];
end//}
endgenerate//}
assign ret_ptr = ret_ptr_r;
assign dis_ptr = alc_ptr_r;
////
//// // If the OITF is not full, or it is under retiring, then it is ready to accept new dispatch
//// assign dis_ready = (~oitf_full) | ret_ena;
// To cut down the loop between ALU write-back valid --> oitf_ret_ena --> oitf_ready ---> dispatch_ready --- > alu_i_valid
// we exclude the ret_ena from the ready signal
assign dis_ready = (~oitf_full);
wire [`E203_OITF_DEPTH-1:0] rd_match_rs1idx;
wire [`E203_OITF_DEPTH-1:0] rd_match_rs2idx;
wire [`E203_OITF_DEPTH-1:0] rd_match_rs3idx;
wire [`E203_OITF_DEPTH-1:0] rd_match_rdidx;
genvar i;
generate //{
for (i=0; i<`E203_OITF_DEPTH; i=i+1) begin:oitf_entries//{
assign vld_set[i] = alc_ptr_ena & (alc_ptr_r == i);
assign vld_clr[i] = ret_ptr_ena & (ret_ptr_r == i);
assign vld_ena[i] = vld_set[i] | vld_clr[i];
assign vld_nxt[i] = vld_set[i] | (~vld_clr[i]);
sirv_gnrl_dfflr #(1) vld_dfflrs(vld_ena[i], vld_nxt[i], vld_r[i], clk, rst_n);
//Payload only set, no need to clear
sirv_gnrl_dffl #(`E203_RFIDX_WIDTH) rdidx_dfflrs(vld_set[i], disp_i_rdidx, rdidx_r[i], clk);
sirv_gnrl_dffl #(`E203_PC_SIZE ) pc_dfflrs (vld_set[i], disp_i_pc , pc_r[i] , clk);
sirv_gnrl_dffl #(1) rdwen_dfflrs(vld_set[i], disp_i_rdwen, rdwen_r[i], clk);
sirv_gnrl_dffl #(1) rdfpu_dfflrs(vld_set[i], disp_i_rdfpu, rdfpu_r[i], clk);
assign rd_match_rs1idx[i] = vld_r[i] & rdwen_r[i] & disp_i_rs1en & (rdfpu_r[i] == disp_i_rs1fpu) & (rdidx_r[i] == disp_i_rs1idx);
assign rd_match_rs2idx[i] = vld_r[i] & rdwen_r[i] & disp_i_rs2en & (rdfpu_r[i] == disp_i_rs2fpu) & (rdidx_r[i] == disp_i_rs2idx);
assign rd_match_rs3idx[i] = vld_r[i] & rdwen_r[i] & disp_i_rs3en & (rdfpu_r[i] == disp_i_rs3fpu) & (rdidx_r[i] == disp_i_rs3idx);
assign rd_match_rdidx [i] = vld_r[i] & rdwen_r[i] & disp_i_rdwen & (rdfpu_r[i] == disp_i_rdfpu ) & (rdidx_r[i] == disp_i_rdidx );
end//}
endgenerate//}
assign oitfrd_match_disprs1 = |rd_match_rs1idx;
assign oitfrd_match_disprs2 = |rd_match_rs2idx;
assign oitfrd_match_disprs3 = |rd_match_rs3idx;
assign oitfrd_match_disprd = |rd_match_rdidx ;
assign ret_rdidx = rdidx_r[ret_ptr];
assign ret_pc = pc_r [ret_ptr];
assign ret_rdwen = rdwen_r[ret_ptr];
assign ret_rdfpu = rdfpu_r[ret_ptr];
endmodule
|
module sirv_clint_top(
input clk,
input rst_n,
input i_icb_cmd_valid,
output i_icb_cmd_ready,
input [32-1:0] i_icb_cmd_addr,
input i_icb_cmd_read,
input [32-1:0] i_icb_cmd_wdata,
output i_icb_rsp_valid,
input i_icb_rsp_ready,
output [32-1:0] i_icb_rsp_rdata,
output io_tiles_0_mtip,
output io_tiles_0_msip,
input io_rtcToggle
);
wire io_rtcToggle_r;
sirv_gnrl_dffr #(1) io_rtcToggle_dffr (io_rtcToggle, io_rtcToggle_r, clk, rst_n);
wire io_rtcToggle_edge = io_rtcToggle ^ io_rtcToggle_r;
wire io_rtcTick = io_rtcToggle_edge;
wire io_in_0_a_ready;
assign i_icb_cmd_ready = io_in_0_a_ready;
wire io_in_0_a_valid = i_icb_cmd_valid;
wire [2:0] io_in_0_a_bits_opcode = i_icb_cmd_read ? 3'h4 : 3'h0;
wire [2:0] io_in_0_a_bits_param = 3'b0;
wire [2:0] io_in_0_a_bits_size = 3'd2;
wire [4:0] io_in_0_a_bits_source = 5'b0;
wire [25:0] io_in_0_a_bits_address = i_icb_cmd_addr[25:0];
wire [3:0] io_in_0_a_bits_mask = 4'b1111;
wire [31:0] io_in_0_a_bits_data = i_icb_cmd_wdata;
wire io_in_0_d_ready = i_icb_rsp_ready;
wire [2:0] io_in_0_d_bits_opcode;
wire [1:0] io_in_0_d_bits_param;
wire [2:0] io_in_0_d_bits_size;
wire [4:0] io_in_0_d_bits_source;
wire io_in_0_d_bits_sink;
wire [1:0] io_in_0_d_bits_addr_lo;
wire [31:0] io_in_0_d_bits_data;
wire io_in_0_d_bits_error;
wire io_in_0_d_valid;
assign i_icb_rsp_valid = io_in_0_d_valid;
assign i_icb_rsp_rdata = io_in_0_d_bits_data;
// Not used
wire io_in_0_b_ready = 1'b0;
wire io_in_0_b_valid;
wire [2:0] io_in_0_b_bits_opcode;
wire [1:0] io_in_0_b_bits_param;
wire [2:0] io_in_0_b_bits_size;
wire [4:0] io_in_0_b_bits_source;
wire [25:0] io_in_0_b_bits_address;
wire [3:0] io_in_0_b_bits_mask;
wire [31:0] io_in_0_b_bits_data;
// Not used
wire io_in_0_c_ready;
wire io_in_0_c_valid = 1'b0;
wire [2:0] io_in_0_c_bits_opcode = 3'b0;
wire [2:0] io_in_0_c_bits_param = 3'b0;
wire [2:0] io_in_0_c_bits_size = 3'd2;
wire [4:0] io_in_0_c_bits_source = 5'b0;
wire [25:0] io_in_0_c_bits_address = 26'b0;
wire [31:0] io_in_0_c_bits_data = 32'b0;
wire io_in_0_c_bits_error = 1'b0;
// Not used
wire io_in_0_e_ready;
wire io_in_0_e_valid = 1'b0;
wire io_in_0_e_bits_sink = 1'b0;
sirv_clint u_sirv_clint(
.clock (clk ),
.reset (~rst_n ),
.io_in_0_a_ready (io_in_0_a_ready ),
.io_in_0_a_valid (io_in_0_a_valid ),
.io_in_0_a_bits_opcode (io_in_0_a_bits_opcode ),
.io_in_0_a_bits_param (io_in_0_a_bits_param ),
.io_in_0_a_bits_size (io_in_0_a_bits_size ),
.io_in_0_a_bits_source (io_in_0_a_bits_source ),
.io_in_0_a_bits_address (io_in_0_a_bits_address ),
.io_in_0_a_bits_mask (io_in_0_a_bits_mask ),
.io_in_0_a_bits_data (io_in_0_a_bits_data ),
.io_in_0_b_ready (io_in_0_b_ready ),
.io_in_0_b_valid (io_in_0_b_valid ),
.io_in_0_b_bits_opcode (io_in_0_b_bits_opcode ),
.io_in_0_b_bits_param (io_in_0_b_bits_param ),
.io_in_0_b_bits_size (io_in_0_b_bits_size ),
.io_in_0_b_bits_source (io_in_0_b_bits_source ),
.io_in_0_b_bits_address (io_in_0_b_bits_address ),
.io_in_0_b_bits_mask (io_in_0_b_bits_mask ),
.io_in_0_b_bits_data (io_in_0_b_bits_data ),
.io_in_0_c_ready (io_in_0_c_ready ),
.io_in_0_c_valid (io_in_0_c_valid ),
.io_in_0_c_bits_opcode (io_in_0_c_bits_opcode ),
.io_in_0_c_bits_param (io_in_0_c_bits_param ),
.io_in_0_c_bits_size (io_in_0_c_bits_size ),
.io_in_0_c_bits_source (io_in_0_c_bits_source ),
.io_in_0_c_bits_address (io_in_0_c_bits_address ),
.io_in_0_c_bits_data (io_in_0_c_bits_data ),
.io_in_0_c_bits_error (io_in_0_c_bits_error ),
.io_in_0_d_ready (io_in_0_d_ready ),
.io_in_0_d_valid (io_in_0_d_valid ),
.io_in_0_d_bits_opcode (io_in_0_d_bits_opcode ),
.io_in_0_d_bits_param (io_in_0_d_bits_param ),
.io_in_0_d_bits_size (io_in_0_d_bits_size ),
.io_in_0_d_bits_source (io_in_0_d_bits_source ),
.io_in_0_d_bits_sink (io_in_0_d_bits_sink ),
.io_in_0_d_bits_addr_lo (io_in_0_d_bits_addr_lo ),
.io_in_0_d_bits_data (io_in_0_d_bits_data ),
.io_in_0_d_bits_error (io_in_0_d_bits_error ),
.io_in_0_e_ready (io_in_0_e_ready ),
.io_in_0_e_valid (io_in_0_e_valid ),
.io_in_0_e_bits_sink (io_in_0_e_bits_sink ),
.io_tiles_0_mtip (io_tiles_0_mtip),
.io_tiles_0_msip (io_tiles_0_msip),
.io_rtcTick (io_rtcTick )
);
endmodule
|
module sirv_qspi_arbiter(
input clock,
input reset,
output io_inner_0_tx_ready,
input io_inner_0_tx_valid,
input [7:0] io_inner_0_tx_bits,
output io_inner_0_rx_valid,
output [7:0] io_inner_0_rx_bits,
input [7:0] io_inner_0_cnt,
input [1:0] io_inner_0_fmt_proto,
input io_inner_0_fmt_endian,
input io_inner_0_fmt_iodir,
input io_inner_0_cs_set,
input io_inner_0_cs_clear,
input io_inner_0_cs_hold,
output io_inner_0_active,
input io_inner_0_lock,
output io_inner_1_tx_ready,
input io_inner_1_tx_valid,
input [7:0] io_inner_1_tx_bits,
output io_inner_1_rx_valid,
output [7:0] io_inner_1_rx_bits,
input [7:0] io_inner_1_cnt,
input [1:0] io_inner_1_fmt_proto,
input io_inner_1_fmt_endian,
input io_inner_1_fmt_iodir,
input io_inner_1_cs_set,
input io_inner_1_cs_clear,
input io_inner_1_cs_hold,
output io_inner_1_active,
input io_inner_1_lock,
input io_outer_tx_ready,
output io_outer_tx_valid,
output [7:0] io_outer_tx_bits,
input io_outer_rx_valid,
input [7:0] io_outer_rx_bits,
output [7:0] io_outer_cnt,
output [1:0] io_outer_fmt_proto,
output io_outer_fmt_endian,
output io_outer_fmt_iodir,
output io_outer_cs_set,
output io_outer_cs_clear,
output io_outer_cs_hold,
input io_outer_active,
input io_sel
);
wire T_335_0;
wire T_335_1;
reg sel_0;
reg [31:0] GEN_4;
reg sel_1;
reg [31:0] GEN_5;
wire T_346;
wire T_349;
wire T_351;
wire T_352;
wire [7:0] T_354;
wire [7:0] T_356;
wire [7:0] T_358;
wire [7:0] T_359;
wire [7:0] T_361;
wire [7:0] T_363;
wire [7:0] T_365;
wire [7:0] T_366;
wire [2:0] T_367;
wire [3:0] T_368;
wire [3:0] T_370;
wire [2:0] T_371;
wire [3:0] T_372;
wire [3:0] T_374;
wire [3:0] T_379;
wire [1:0] T_384_proto;
wire T_384_endian;
wire T_384_iodir;
wire T_388;
wire T_389;
wire [1:0] T_390;
wire [1:0] T_391;
wire [2:0] T_392;
wire [2:0] T_394;
wire [1:0] T_395;
wire [2:0] T_396;
wire [2:0] T_398;
wire [2:0] T_406;
wire T_414_set;
wire T_414_clear;
wire T_414_hold;
wire T_421;
wire T_422;
wire T_423;
wire T_424;
wire T_425;
wire T_426;
wire T_427;
wire T_428;
wire T_429;
wire T_431;
wire nsel_0;
wire nsel_1;
wire T_445;
wire T_448;
wire T_450;
wire lock;
wire T_452;
wire [1:0] T_453;
wire [1:0] T_454;
wire T_455;
wire GEN_0;
wire GEN_1;
wire GEN_2;
wire GEN_3;
assign io_inner_0_tx_ready = T_424;
assign io_inner_0_rx_valid = T_425;
assign io_inner_0_rx_bits = io_outer_rx_bits;
assign io_inner_0_active = T_426;
assign io_inner_1_tx_ready = T_427;
assign io_inner_1_rx_valid = T_428;
assign io_inner_1_rx_bits = io_outer_rx_bits;
assign io_inner_1_active = T_429;
assign io_outer_tx_valid = T_352;
assign io_outer_tx_bits = T_359;
assign io_outer_cnt = T_366;
assign io_outer_fmt_proto = T_384_proto;
assign io_outer_fmt_endian = T_384_endian;
assign io_outer_fmt_iodir = T_384_iodir;
assign io_outer_cs_set = T_414_set;
assign io_outer_cs_clear = GEN_3;
assign io_outer_cs_hold = T_414_hold;
assign T_335_0 = 1'h1;
assign T_335_1 = 1'h0;
assign T_346 = sel_0 ? io_inner_0_tx_valid : 1'h0;
assign T_349 = sel_1 ? io_inner_1_tx_valid : 1'h0;
assign T_351 = T_346 | T_349;
assign T_352 = T_351;
assign T_354 = sel_0 ? io_inner_0_tx_bits : 8'h0;
assign T_356 = sel_1 ? io_inner_1_tx_bits : 8'h0;
assign T_358 = T_354 | T_356;
assign T_359 = T_358;
assign T_361 = sel_0 ? io_inner_0_cnt : 8'h0;
assign T_363 = sel_1 ? io_inner_1_cnt : 8'h0;
assign T_365 = T_361 | T_363;
assign T_366 = T_365;
assign T_367 = {io_inner_0_fmt_proto,io_inner_0_fmt_endian};
assign T_368 = {T_367,io_inner_0_fmt_iodir};
assign T_370 = sel_0 ? T_368 : 4'h0;
assign T_371 = {io_inner_1_fmt_proto,io_inner_1_fmt_endian};
assign T_372 = {T_371,io_inner_1_fmt_iodir};
assign T_374 = sel_1 ? T_372 : 4'h0;
assign T_379 = T_370 | T_374;
assign T_384_proto = T_390;
assign T_384_endian = T_389;
assign T_384_iodir = T_388;
assign T_388 = T_379[0];
assign T_389 = T_379[1];
assign T_390 = T_379[3:2];
assign T_391 = {io_inner_0_cs_set,io_inner_0_cs_clear};
assign T_392 = {T_391,io_inner_0_cs_hold};
assign T_394 = sel_0 ? T_392 : 3'h0;
assign T_395 = {io_inner_1_cs_set,io_inner_1_cs_clear};
assign T_396 = {T_395,io_inner_1_cs_hold};
assign T_398 = sel_1 ? T_396 : 3'h0;
assign T_406 = T_394 | T_398;
assign T_414_set = T_423;
assign T_414_clear = T_422;
assign T_414_hold = T_421;
assign T_421 = T_406[0];
assign T_422 = T_406[1];
assign T_423 = T_406[2];
assign T_424 = io_outer_tx_ready & sel_0;
assign T_425 = io_outer_rx_valid & sel_0;
assign T_426 = io_outer_active & sel_0;
assign T_427 = io_outer_tx_ready & sel_1;
assign T_428 = io_outer_rx_valid & sel_1;
assign T_429 = io_outer_active & sel_1;
assign T_431 = io_sel == 1'h0;
assign nsel_0 = T_431;
assign nsel_1 = io_sel;
assign T_445 = sel_0 ? io_inner_0_lock : 1'h0;
assign T_448 = sel_1 ? io_inner_1_lock : 1'h0;
assign T_450 = T_445 | T_448;
assign lock = T_450;
assign T_452 = lock == 1'h0;
assign T_453 = {sel_1,sel_0};
assign T_454 = {nsel_1,nsel_0};
assign T_455 = T_453 != T_454;
assign GEN_0 = T_455 ? 1'h1 : T_414_clear;
assign GEN_1 = T_452 ? nsel_0 : sel_0;
assign GEN_2 = T_452 ? nsel_1 : sel_1;
assign GEN_3 = T_452 ? GEN_0 : T_414_clear;
always @(posedge clock or posedge reset)
if (reset) begin
sel_0 <= T_335_0;
end else begin
if (T_452) begin
sel_0 <= nsel_0;
end
end
always @(posedge clock or posedge reset)
if (reset) begin
sel_1 <= T_335_1;
end else begin
if (T_452) begin
sel_1 <= nsel_1;
end
end
endmodule
|
module e203_exu_alu_muldiv(
input mdv_nob2b,
//////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////
// The Issue Handshake Interface to MULDIV
//
input muldiv_i_valid, // Handshake valid
output muldiv_i_ready, // Handshake ready
input [`E203_XLEN-1:0] muldiv_i_rs1,
input [`E203_XLEN-1:0] muldiv_i_rs2,
input [`E203_XLEN-1:0] muldiv_i_imm,
input [`E203_DECINFO_MULDIV_WIDTH-1:0] muldiv_i_info,
input [`E203_ITAG_WIDTH-1:0] muldiv_i_itag,
output muldiv_i_longpipe,
input flush_pulse,
//////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////
// The MULDIV Write-Back/Commit Interface
output muldiv_o_valid, // Handshake valid
input muldiv_o_ready, // Handshake ready
output [`E203_XLEN-1:0] muldiv_o_wbck_wdat,
output muldiv_o_wbck_err,
// There is no exception cases for MULDIV, so no addtional cmt signals
//////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////
// To share the ALU datapath, generate interface to ALU
//
// The operands and info to ALU
output [`E203_MULDIV_ADDER_WIDTH-1:0] muldiv_req_alu_op1,
output [`E203_MULDIV_ADDER_WIDTH-1:0] muldiv_req_alu_op2,
output muldiv_req_alu_add ,
output muldiv_req_alu_sub ,
input [`E203_MULDIV_ADDER_WIDTH-1:0] muldiv_req_alu_res,
// The Shared-Buffer interface to ALU-Shared-Buffer
output muldiv_sbf_0_ena,
output [33-1:0] muldiv_sbf_0_nxt,
input [33-1:0] muldiv_sbf_0_r,
output muldiv_sbf_1_ena,
output [33-1:0] muldiv_sbf_1_nxt,
input [33-1:0] muldiv_sbf_1_r,
input clk,
input rst_n
);
wire muldiv_i_hsked = muldiv_i_valid & muldiv_i_ready;
wire muldiv_o_hsked = muldiv_o_valid & muldiv_o_ready;
wire flushed_r;
wire flushed_set = flush_pulse;
wire flushed_clr = muldiv_o_hsked & (~flush_pulse);
wire flushed_ena = flushed_set | flushed_clr;
wire flushed_nxt = flushed_set | (~flushed_clr);
sirv_gnrl_dfflr #(1) flushed_dfflr (flushed_ena, flushed_nxt, flushed_r, clk, rst_n);
wire i_mul = muldiv_i_info[`E203_DECINFO_MULDIV_MUL ];// We treat this as signed X signed
wire i_mulh = muldiv_i_info[`E203_DECINFO_MULDIV_MULH ];
wire i_mulhsu = muldiv_i_info[`E203_DECINFO_MULDIV_MULHSU];
wire i_mulhu = muldiv_i_info[`E203_DECINFO_MULDIV_MULHU ];
wire i_div = muldiv_i_info[`E203_DECINFO_MULDIV_DIV ];
wire i_divu = muldiv_i_info[`E203_DECINFO_MULDIV_DIVU ];
wire i_rem = muldiv_i_info[`E203_DECINFO_MULDIV_REM ];
wire i_remu = muldiv_i_info[`E203_DECINFO_MULDIV_REMU ];
// If it is flushed then it is not back2back real case
wire i_b2b = muldiv_i_info[`E203_DECINFO_MULDIV_B2B ] & (~flushed_r) & (~mdv_nob2b);
wire back2back_seq = i_b2b;
wire mul_rs1_sign = (i_mulhu) ? 1'b0 : muldiv_i_rs1[`E203_XLEN-1];
wire mul_rs2_sign = (i_mulhsu | i_mulhu) ? 1'b0 : muldiv_i_rs2[`E203_XLEN-1];
wire [32:0] mul_op1 = {mul_rs1_sign, muldiv_i_rs1};
wire [32:0] mul_op2 = {mul_rs2_sign, muldiv_i_rs2};
wire i_op_mul = i_mul | i_mulh | i_mulhsu | i_mulhu;
wire i_op_div = i_div | i_divu | i_rem | i_remu;
/////////////////////////////////////////////////////////////////////////////////
// Implement the state machine for
// (1) The MUL instructions
// (2) The DIV instructions
localparam MULDIV_STATE_WIDTH = 3;
wire [MULDIV_STATE_WIDTH-1:0] muldiv_state_nxt;
wire [MULDIV_STATE_WIDTH-1:0] muldiv_state_r;
wire muldiv_state_ena;
// State 0: The 0th state, means this is the 1 cycle see the operand inputs
localparam MULDIV_STATE_0TH = 3'd0;
// State 1: Executing the instructions
localparam MULDIV_STATE_EXEC = 3'd1;
// State 2: Div check if need correction
localparam MULDIV_STATE_REMD_CHCK = 3'd2;
// State 3: Quotient correction
localparam MULDIV_STATE_QUOT_CORR = 3'd3;
// State 4: Reminder correction
localparam MULDIV_STATE_REMD_CORR = 3'd4;
wire [MULDIV_STATE_WIDTH-1:0] state_0th_nxt;
wire [MULDIV_STATE_WIDTH-1:0] state_exec_nxt;
wire [MULDIV_STATE_WIDTH-1:0] state_remd_chck_nxt;
wire [MULDIV_STATE_WIDTH-1:0] state_quot_corr_nxt;
wire [MULDIV_STATE_WIDTH-1:0] state_remd_corr_nxt;
wire state_0th_exit_ena;
wire state_exec_exit_ena;
wire state_remd_chck_exit_ena;
wire state_quot_corr_exit_ena;
wire state_remd_corr_exit_ena;
wire special_cases;
wire muldiv_i_valid_nb2b = muldiv_i_valid & (~back2back_seq) & (~special_cases);
// Define some common signals and reused later to save gatecounts
wire muldiv_sta_is_0th = (muldiv_state_r == MULDIV_STATE_0TH );
wire muldiv_sta_is_exec = (muldiv_state_r == MULDIV_STATE_EXEC );
wire muldiv_sta_is_remd_chck = (muldiv_state_r == MULDIV_STATE_REMD_CHCK );
wire muldiv_sta_is_quot_corr = (muldiv_state_r == MULDIV_STATE_QUOT_CORR );
wire muldiv_sta_is_remd_corr = (muldiv_state_r == MULDIV_STATE_REMD_CORR );
// **** If the current state is 0th,
// If a new instruction come (non back2back), next state is MULDIV_STATE_EXEC
assign state_0th_exit_ena = muldiv_sta_is_0th & muldiv_i_valid_nb2b & (~flush_pulse);
assign state_0th_nxt = MULDIV_STATE_EXEC;
// **** If the current state is exec,
wire div_need_corrct;
wire mul_exec_last_cycle;
wire div_exec_last_cycle;
wire exec_last_cycle;
assign state_exec_exit_ena = muldiv_sta_is_exec & ((
// If it is the last cycle (16th or 32rd cycles),
exec_last_cycle
// If it is div op, then jump to DIV_CHECK state
& (i_op_div ? 1'b1
// If it is not div-need-correction, then jump to 0th
: muldiv_o_hsked))
| flush_pulse);
assign state_exec_nxt =
(
flush_pulse ? MULDIV_STATE_0TH :
// If it is div op, then jump to DIV_CHECK state
i_op_div ? MULDIV_STATE_REMD_CHCK
// If it is not div-need-correction, then jump to 0th
: MULDIV_STATE_0TH
);
// **** If the current state is REMD_CHCK,
// If it is div-need-correction, then jump to QUOT_CORR state
// otherwise jump to the 0th
assign state_remd_chck_exit_ena = (muldiv_sta_is_remd_chck & (
// If it is div op, then jump to DIV_CHECK state
(div_need_corrct ? 1'b1
// If it is not div-need-correction, then jump to 0th
: muldiv_o_hsked)
| flush_pulse )) ;
assign state_remd_chck_nxt = flush_pulse ? MULDIV_STATE_0TH :
// If it is div-need-correction, then jump to QUOT_CORR state
div_need_corrct ? MULDIV_STATE_QUOT_CORR
// If it is not div-need-correction, then jump to 0th
: MULDIV_STATE_0TH;
// **** If the current state is QUOT_CORR,
// Always jump to REMD_CORR state
assign state_quot_corr_exit_ena = (muldiv_sta_is_quot_corr & (flush_pulse | 1'b1));
assign state_quot_corr_nxt = flush_pulse ? MULDIV_STATE_0TH : MULDIV_STATE_REMD_CORR;
// **** If the current state is REMD_CORR,
// Then jump to 0th
assign state_remd_corr_exit_ena = (muldiv_sta_is_remd_corr & (flush_pulse | muldiv_o_hsked));
assign state_remd_corr_nxt = flush_pulse ? MULDIV_STATE_0TH : MULDIV_STATE_0TH;
// The state will only toggle when each state is meeting the condition to exit
assign muldiv_state_ena = state_0th_exit_ena
| state_exec_exit_ena
| state_remd_chck_exit_ena
| state_quot_corr_exit_ena
| state_remd_corr_exit_ena;
// The next-state is onehot mux to select different entries
assign muldiv_state_nxt =
({MULDIV_STATE_WIDTH{state_0th_exit_ena }} & state_0th_nxt )
| ({MULDIV_STATE_WIDTH{state_exec_exit_ena }} & state_exec_nxt )
| ({MULDIV_STATE_WIDTH{state_remd_chck_exit_ena}} & state_remd_chck_nxt)
| ({MULDIV_STATE_WIDTH{state_quot_corr_exit_ena}} & state_quot_corr_nxt)
| ({MULDIV_STATE_WIDTH{state_remd_corr_exit_ena}} & state_remd_corr_nxt)
;
sirv_gnrl_dfflr #(MULDIV_STATE_WIDTH) muldiv_state_dfflr (muldiv_state_ena, muldiv_state_nxt, muldiv_state_r, clk, rst_n);
wire state_exec_enter_ena = muldiv_state_ena & (muldiv_state_nxt == MULDIV_STATE_EXEC);
localparam EXEC_CNT_W = 6;
localparam EXEC_CNT_1 = 6'd1 ;
localparam EXEC_CNT_16 = 6'd16;
localparam EXEC_CNT_32 = 6'd32;
wire[EXEC_CNT_W-1:0] exec_cnt_r;
wire exec_cnt_set = state_exec_enter_ena;
wire exec_cnt_inc = muldiv_sta_is_exec & (~exec_last_cycle);
wire exec_cnt_ena = exec_cnt_inc | exec_cnt_set;
// When set, the counter is set to 1, because the 0th state also counted as 0th cycle
wire[EXEC_CNT_W-1:0] exec_cnt_nxt = exec_cnt_set ? EXEC_CNT_1 : (exec_cnt_r + 1'b1);
sirv_gnrl_dfflr #(EXEC_CNT_W) exec_cnt_dfflr (exec_cnt_ena, exec_cnt_nxt, exec_cnt_r, clk, rst_n);
// The exec state is the last cycle when the exec_cnt_r is reaching the last cycle (16 or 32cycles)
wire cycle_0th = muldiv_sta_is_0th;
wire cycle_16th = (exec_cnt_r == EXEC_CNT_16);
wire cycle_32nd = (exec_cnt_r == EXEC_CNT_32);
assign mul_exec_last_cycle = cycle_16th;
assign div_exec_last_cycle = cycle_32nd;
assign exec_last_cycle = i_op_mul ? mul_exec_last_cycle : div_exec_last_cycle;
///////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////
// Use booth-4 algorithm to conduct the multiplication
wire [32:0] part_prdt_hi_r;
wire [32:0] part_prdt_lo_r;
wire [32:0] part_prdt_hi_nxt;
wire [32:0] part_prdt_lo_nxt;
wire part_prdt_sft1_r;
wire [2:0] booth_code = cycle_0th ? {muldiv_i_rs1[1:0],1'b0}
: cycle_16th ? {mul_rs1_sign,part_prdt_lo_r[0],part_prdt_sft1_r}
: {part_prdt_lo_r[1:0],part_prdt_sft1_r};
//booth_code == 3'b000 = 0
//booth_code == 3'b001 = 1
//booth_code == 3'b010 = 1
//booth_code == 3'b011 = 2
//booth_code == 3'b100 = -2
//booth_code == 3'b101 = -1
//booth_code == 3'b110 = -1
//booth_code == 3'b111 = -0
wire booth_sel_zero = (booth_code == 3'b000) | (booth_code == 3'b111);
wire booth_sel_two = (booth_code == 3'b011) | (booth_code == 3'b100);
wire booth_sel_one = (~booth_sel_zero) & (~booth_sel_two);
wire booth_sel_sub = booth_code[2];
// 35 bits adder needed
wire [`E203_MULDIV_ADDER_WIDTH-1:0] mul_exe_alu_res = muldiv_req_alu_res;
wire [`E203_MULDIV_ADDER_WIDTH-1:0] mul_exe_alu_op2 =
({`E203_MULDIV_ADDER_WIDTH{booth_sel_zero}} & `E203_MULDIV_ADDER_WIDTH'b0)
| ({`E203_MULDIV_ADDER_WIDTH{booth_sel_one }} & {mul_rs2_sign,mul_rs2_sign,mul_rs2_sign,muldiv_i_rs2})
| ({`E203_MULDIV_ADDER_WIDTH{booth_sel_two }} & {mul_rs2_sign,mul_rs2_sign,muldiv_i_rs2,1'b0})
;
wire [`E203_MULDIV_ADDER_WIDTH-1:0] mul_exe_alu_op1 =
cycle_0th ? `E203_MULDIV_ADDER_WIDTH'b0 : {part_prdt_hi_r[32],part_prdt_hi_r[32],part_prdt_hi_r};
wire mul_exe_alu_add = (~booth_sel_sub);
wire mul_exe_alu_sub = booth_sel_sub;
assign part_prdt_hi_nxt = mul_exe_alu_res[34:2];
assign part_prdt_lo_nxt = {mul_exe_alu_res[1:0],
(cycle_0th ? {mul_rs1_sign,muldiv_i_rs1[31:2]} : part_prdt_lo_r[32:2])
};
wire part_prdt_sft1_nxt = cycle_0th ? muldiv_i_rs1[1] : part_prdt_lo_r[1];
wire mul_exe_cnt_set = exec_cnt_set & i_op_mul;
wire mul_exe_cnt_inc = exec_cnt_inc & i_op_mul;
wire part_prdt_hi_ena = mul_exe_cnt_set | mul_exe_cnt_inc | state_exec_exit_ena;
wire part_prdt_lo_ena = part_prdt_hi_ena;
sirv_gnrl_dfflr #(1) part_prdt_sft1_dfflr (part_prdt_lo_ena, part_prdt_sft1_nxt, part_prdt_sft1_r, clk, rst_n);
// This mul_res is not back2back case, so directly from the adder result
wire[`E203_XLEN-1:0] mul_res = i_mul ? part_prdt_lo_r[32:1] : mul_exe_alu_res[31:0];
///////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////
// The Divider Implementation, using the non-restoring signed division
wire [32:0] part_remd_r;
wire [32:0] part_quot_r;
wire div_rs1_sign = (i_divu | i_remu) ? 1'b0 : muldiv_i_rs1[`E203_XLEN-1];
wire div_rs2_sign = (i_divu | i_remu) ? 1'b0 : muldiv_i_rs2[`E203_XLEN-1];
wire [65:0] dividend = {{33{div_rs1_sign}}, div_rs1_sign, muldiv_i_rs1};
wire [33:0] divisor = {div_rs2_sign, div_rs2_sign, muldiv_i_rs2};
wire quot_0cycl = (dividend[65] ^ divisor[33]) ? 1'b0 : 1'b1;// If the sign(s0)!=sign(d), then set q_1st = -1
wire [66:0] dividend_lsft1 = {dividend[65:0],quot_0cycl};
wire prev_quot = cycle_0th ? quot_0cycl : part_quot_r[0];
wire part_remd_sft1_r;
// 34 bits adder needed
wire [33:0] div_exe_alu_res = muldiv_req_alu_res[33:0];
wire [33:0] div_exe_alu_op1 = cycle_0th ? dividend_lsft1[66:33] : {part_remd_sft1_r, part_remd_r[32:0]};
wire [33:0] div_exe_alu_op2 = divisor;
wire div_exe_alu_add = (~prev_quot);
wire div_exe_alu_sub = prev_quot ;
wire current_quot = (div_exe_alu_res[33] ^ divisor[33]) ? 1'b0 : 1'b1;
wire [66:0] div_exe_part_remd;
assign div_exe_part_remd[66:33] = div_exe_alu_res;
assign div_exe_part_remd[32: 0] = cycle_0th ? dividend_lsft1[32:0] : part_quot_r[32:0];
wire [67:0] div_exe_part_remd_lsft1 = {div_exe_part_remd[66:0],current_quot};
wire part_remd_ena;
// Since the part_remd_r is only save 33bits (after left shifted), so the adder result MSB bit we need to save
// it here, which will be used at next round
sirv_gnrl_dfflr #(1) part_remd_sft1_dfflr (part_remd_ena, div_exe_alu_res[32], part_remd_sft1_r, clk, rst_n);
wire div_exe_cnt_set = exec_cnt_set & i_op_div;
wire div_exe_cnt_inc = exec_cnt_inc & i_op_div;
wire corrct_phase = muldiv_sta_is_remd_corr | muldiv_sta_is_quot_corr;
wire check_phase = muldiv_sta_is_remd_chck;
wire [33:0] div_quot_corr_alu_res;
wire [33:0] div_remd_corr_alu_res;
// Note: in last cycle, the reminder value is the non-shifted value
// but the quotient value is the shifted value, and last bit of quotient value is shifted always by 1
// If need corrective, the correct quot first, and then reminder, so reminder output as comb logic directly to
// save a cycle
wire [32:0] div_remd = check_phase ? part_remd_r [32:0]:
corrct_phase ? div_remd_corr_alu_res[32:0] :
div_exe_part_remd[65:33];
wire [32:0] div_quot = check_phase ? part_quot_r [32:0]:
corrct_phase ? part_quot_r [32:0]:
{div_exe_part_remd[31:0],1'b1};
// The partial reminder and quotient
wire [32:0] part_remd_nxt = corrct_phase ? div_remd_corr_alu_res[32:0] :
(muldiv_sta_is_exec & div_exec_last_cycle) ? div_remd :
div_exe_part_remd_lsft1[65:33];
wire [32:0] part_quot_nxt = corrct_phase ? div_quot_corr_alu_res[32:0] :
(muldiv_sta_is_exec & div_exec_last_cycle) ? div_quot :
div_exe_part_remd_lsft1[32: 0];
wire [33:0] div_remd_chck_alu_res = muldiv_req_alu_res[33:0];
wire [33:0] div_remd_chck_alu_op1 = {part_remd_r[32], part_remd_r};
wire [33:0] div_remd_chck_alu_op2 = divisor;
wire div_remd_chck_alu_add = 1'b1;
wire div_remd_chck_alu_sub = 1'b0;
wire remd_is_0 = ~(|part_remd_r);
wire remd_is_neg_divs = ~(|div_remd_chck_alu_res);
wire remd_is_divs = (part_remd_r == divisor[32:0]);
assign div_need_corrct = i_op_div & (
((part_remd_r[32] ^ dividend[65]) & (~remd_is_0))
| remd_is_neg_divs
| remd_is_divs
);
wire remd_inc_quot_dec = (part_remd_r[32] ^ divisor[33]);
assign div_quot_corr_alu_res = muldiv_req_alu_res[33:0];
wire [33:0] div_quot_corr_alu_op1 = {part_quot_r[32], part_quot_r};
wire [33:0] div_quot_corr_alu_op2 = 34'b1;
wire div_quot_corr_alu_add = (~remd_inc_quot_dec);
wire div_quot_corr_alu_sub = remd_inc_quot_dec;
assign div_remd_corr_alu_res = muldiv_req_alu_res[33:0];
wire [33:0] div_remd_corr_alu_op1 = {part_remd_r[32], part_remd_r};
wire [33:0] div_remd_corr_alu_op2 = divisor;
wire div_remd_corr_alu_add = remd_inc_quot_dec;
wire div_remd_corr_alu_sub = ~remd_inc_quot_dec;
// The partial reminder register will be loaded in the exe state, and in reminder correction cycle
assign part_remd_ena = div_exe_cnt_set | div_exe_cnt_inc | state_exec_exit_ena | state_remd_corr_exit_ena;
// The partial quotient register will be loaded in the exe state, and in quotient correction cycle
wire part_quot_ena = div_exe_cnt_set | div_exe_cnt_inc | state_exec_exit_ena | state_quot_corr_exit_ena;
wire[`E203_XLEN-1:0] div_res = (i_div | i_divu) ? div_quot[`E203_XLEN-1:0] : div_remd[`E203_XLEN-1:0];
wire div_by_0 = ~(|muldiv_i_rs2);// Divisor is all zeros
wire div_ovf = (i_div | i_rem) & (&muldiv_i_rs2) // Divisor is all ones, means -1
//Dividend is 10000...000, means -(2^xlen -1)
& muldiv_i_rs1[`E203_XLEN-1] & (~(|muldiv_i_rs1[`E203_XLEN-2:0]));
wire[`E203_XLEN-1:0] div_by_0_res_quot = ~`E203_XLEN'b0;
wire[`E203_XLEN-1:0] div_by_0_res_remd = dividend[`E203_XLEN-1:0];
wire[`E203_XLEN-1:0] div_by_0_res = (i_div | i_divu) ? div_by_0_res_quot : div_by_0_res_remd;
wire[`E203_XLEN-1:0] div_ovf_res_quot = {1'b1,{`E203_XLEN-1{1'b0}}};
wire[`E203_XLEN-1:0] div_ovf_res_remd = `E203_XLEN'b0;
wire[`E203_XLEN-1:0] div_ovf_res = (i_div | i_divu) ? div_ovf_res_quot : div_ovf_res_remd;
wire div_special_cases = i_op_div & (div_by_0 | div_ovf);
wire[`E203_XLEN-1:0] div_special_res = div_by_0 ? div_by_0_res : div_ovf_res;
///////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////
// Output generateion
assign special_cases = div_special_cases;// Only divider have special cases
wire[`E203_XLEN-1:0] special_res = div_special_res;// Only divider have special cases
// To detect the sequence of MULH[[S]U] rdh, rs1, rs2; MUL rdl, rs1, rs2
// To detect the sequence of DIV[U] rdq, rs1, rs2; REM[U] rdr, rs1, rs2
wire [`E203_XLEN-1:0] back2back_mul_res = {part_prdt_lo_r[`E203_XLEN-2:0],part_prdt_sft1_r};// Only the MUL will be treated as back2back
wire [`E203_XLEN-1:0] back2back_mul_rem = part_remd_r[`E203_XLEN-1:0];
wire [`E203_XLEN-1:0] back2back_mul_div = part_quot_r[`E203_XLEN-1:0];
wire [`E203_XLEN-1:0] back2back_res = (
({`E203_XLEN{i_mul }} & back2back_mul_res)
| ({`E203_XLEN{i_rem | i_remu}} & back2back_mul_rem)
| ({`E203_XLEN{i_div | i_divu}} & back2back_mul_div)
);
// The output will be valid:
// * If it is back2back and sepcial cases, just directly pass out from input
// * If it is not back2back sequence when it is the last cycle of exec state
// (not div need correction) or last correct state;
wire wbck_condi = (back2back_seq | special_cases) ? 1'b1 :
(
(muldiv_sta_is_exec & exec_last_cycle & (~i_op_div))
| (muldiv_sta_is_remd_chck & (~div_need_corrct))
| muldiv_sta_is_remd_corr
);
assign muldiv_o_valid = wbck_condi & muldiv_i_valid;
assign muldiv_i_ready = wbck_condi & muldiv_o_ready;
wire res_sel_spl = special_cases;
wire res_sel_b2b = back2back_seq & (~special_cases);
wire res_sel_div = (~back2back_seq) & (~special_cases) & i_op_div;
wire res_sel_mul = (~back2back_seq) & (~special_cases) & i_op_mul;
assign muldiv_o_wbck_wdat =
({`E203_XLEN{res_sel_b2b}} & back2back_res)
| ({`E203_XLEN{res_sel_spl}} & special_res)
| ({`E203_XLEN{res_sel_div}} & div_res)
| ({`E203_XLEN{res_sel_mul}} & mul_res);
// There is no exception cases for MULDIV, so no addtional cmt signals
assign muldiv_o_wbck_err = 1'b0;
// The operands and info to ALU
wire req_alu_sel1 = i_op_mul;
wire req_alu_sel2 = i_op_div & (muldiv_sta_is_0th | muldiv_sta_is_exec);
wire req_alu_sel3 = i_op_div & muldiv_sta_is_quot_corr;
wire req_alu_sel4 = i_op_div & muldiv_sta_is_remd_corr;
wire req_alu_sel5 = i_op_div & muldiv_sta_is_remd_chck;
assign muldiv_req_alu_op1 =
({`E203_MULDIV_ADDER_WIDTH{req_alu_sel1}} & mul_exe_alu_op1 )
| ({`E203_MULDIV_ADDER_WIDTH{req_alu_sel2}} & {{`E203_MULDIV_ADDER_WIDTH-34{1'b0}},div_exe_alu_op1 })
| ({`E203_MULDIV_ADDER_WIDTH{req_alu_sel3}} & {{`E203_MULDIV_ADDER_WIDTH-34{1'b0}},div_quot_corr_alu_op1})
| ({`E203_MULDIV_ADDER_WIDTH{req_alu_sel4}} & {{`E203_MULDIV_ADDER_WIDTH-34{1'b0}},div_remd_corr_alu_op1})
| ({`E203_MULDIV_ADDER_WIDTH{req_alu_sel5}} & {{`E203_MULDIV_ADDER_WIDTH-34{1'b0}},div_remd_chck_alu_op1});
assign muldiv_req_alu_op2 =
({`E203_MULDIV_ADDER_WIDTH{req_alu_sel1}} & mul_exe_alu_op2 )
| ({`E203_MULDIV_ADDER_WIDTH{req_alu_sel2}} & {{`E203_MULDIV_ADDER_WIDTH-34{1'b0}},div_exe_alu_op2 })
| ({`E203_MULDIV_ADDER_WIDTH{req_alu_sel3}} & {{`E203_MULDIV_ADDER_WIDTH-34{1'b0}},div_quot_corr_alu_op2})
| ({`E203_MULDIV_ADDER_WIDTH{req_alu_sel4}} & {{`E203_MULDIV_ADDER_WIDTH-34{1'b0}},div_remd_corr_alu_op2})
| ({`E203_MULDIV_ADDER_WIDTH{req_alu_sel5}} & {{`E203_MULDIV_ADDER_WIDTH-34{1'b0}},div_remd_chck_alu_op2});
assign muldiv_req_alu_add =
(req_alu_sel1 & mul_exe_alu_add )
| (req_alu_sel2 & div_exe_alu_add )
| (req_alu_sel3 & div_quot_corr_alu_add)
| (req_alu_sel4 & div_remd_corr_alu_add)
| (req_alu_sel5 & div_remd_chck_alu_add);
assign muldiv_req_alu_sub =
(req_alu_sel1 & mul_exe_alu_sub )
| (req_alu_sel2 & div_exe_alu_sub )
| (req_alu_sel3 & div_quot_corr_alu_sub)
| (req_alu_sel4 & div_remd_corr_alu_sub)
| (req_alu_sel5 & div_remd_chck_alu_sub);
assign muldiv_sbf_0_ena = part_remd_ena | part_prdt_hi_ena;
assign muldiv_sbf_0_nxt = i_op_mul ? part_prdt_hi_nxt : part_remd_nxt;
assign muldiv_sbf_1_ena = part_quot_ena | part_prdt_lo_ena;
assign muldiv_sbf_1_nxt = i_op_mul ? part_prdt_lo_nxt : part_quot_nxt;
assign part_remd_r = muldiv_sbf_0_r;
assign part_quot_r = muldiv_sbf_1_r;
assign part_prdt_hi_r = muldiv_sbf_0_r;
assign part_prdt_lo_r = muldiv_sbf_1_r;
assign muldiv_i_longpipe = 1'b0;
`ifndef FPGA_SOURCE//{
`ifndef DISABLE_SV_ASSERTION//{
//synopsys translate_off
///////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////
// These below code are used for reference check with assertion
wire [31:0] golden0_mul_op1 = mul_op1[32] ? (~mul_op1[31:0]+1) : mul_op1[31:0];
wire [31:0] golden0_mul_op2 = mul_op2[32] ? (~mul_op2[31:0]+1) : mul_op2[31:0];
wire [63:0] golden0_mul_res_pre = golden0_mul_op1 * golden0_mul_op2;
wire [63:0] golden0_mul_res = (mul_op1[32]^mul_op2[32]) ? (~golden0_mul_res_pre + 1) : golden0_mul_res_pre;
wire [63:0] golden1_mul_res = $signed(mul_op1) * $signed(mul_op2);
// To check the signed * operation is really get what we wanted
CHECK_SIGNED_OP_CORRECT:
assert property (@(posedge clk) disable iff ((~rst_n) | (~muldiv_o_valid)) ((golden0_mul_res == golden1_mul_res)))
else $fatal ("\n Error: Oops, This should never happen. \n");
wire [31:0] golden1_res_mul = golden1_mul_res[31:0];
wire [31:0] golden1_res_mulh = golden1_mul_res[63:32];
wire [31:0] golden1_res_mulhsu = golden1_mul_res[63:32];
wire [31:0] golden1_res_mulhu = golden1_mul_res[63:32];
wire [63:0] golden2_res_mul_SxS = $signed(muldiv_i_rs1) * $signed(muldiv_i_rs2);
wire [63:0] golden2_res_mul_SxU = $signed(muldiv_i_rs1) * $unsigned(muldiv_i_rs2);
wire [63:0] golden2_res_mul_UxS = $unsigned(muldiv_i_rs1) * $signed(muldiv_i_rs2);
wire [63:0] golden2_res_mul_UxU = $unsigned(muldiv_i_rs1) * $unsigned(muldiv_i_rs2);
wire [31:0] golden2_res_mul = golden2_res_mul_SxS[31:0];
wire [31:0] golden2_res_mulh = golden2_res_mul_SxS[63:32];
wire [31:0] golden2_res_mulhsu = golden2_res_mul_SxU[63:32];
wire [31:0] golden2_res_mulhu = golden2_res_mul_UxU[63:32];
// To check four different combination will all generate same lower 32bits result
CHECK_FOUR_COMB_SAME_RES:
assert property (@(posedge clk) disable iff ((~rst_n) | (~muldiv_o_valid))
(golden2_res_mul_SxS[31:0] == golden2_res_mul_SxU[31:0])
& (golden2_res_mul_UxS[31:0] == golden2_res_mul_UxU[31:0])
& (golden2_res_mul_SxU[31:0] == golden2_res_mul_UxS[31:0])
)
else $fatal ("\n Error: Oops, This should never happen. \n");
// Seems the golden2 result is not correct in case of mulhsu, so have to comment it out
// // To check golden1 and golden2 result are same
// CHECK_GOLD1_AND_GOLD2_SAME:
// assert property (@(posedge clk) disable iff ((~rst_n) | (~muldiv_o_valid))
// (i_mul ? (golden1_res_mul == golden2_res_mul ) : 1'b1)
// &(i_mulh ? (golden1_res_mulh == golden2_res_mulh ) : 1'b1)
// &(i_mulhsu ? (golden1_res_mulhsu == golden2_res_mulhsu) : 1'b1)
// &(i_mulhu ? (golden1_res_mulhu == golden2_res_mulhu ) : 1'b1)
// )
// else $fatal ("\n Error: Oops, This should never happen. \n");
// The special case will need to be handled specially
wire [32:0] golden_res_div = div_special_cases ? div_special_res :
( $signed({div_rs1_sign,muldiv_i_rs1}) / ((div_by_0 | div_ovf) ? 1 : $signed({div_rs2_sign,muldiv_i_rs2})));
wire [32:0] golden_res_divu = div_special_cases ? div_special_res :
($unsigned({div_rs1_sign,muldiv_i_rs1}) / ((div_by_0 | div_ovf) ? 1 : $unsigned({div_rs2_sign,muldiv_i_rs2})));
wire [32:0] golden_res_rem = div_special_cases ? div_special_res :
( $signed({div_rs1_sign,muldiv_i_rs1}) % ((div_by_0 | div_ovf) ? 1 : $signed({div_rs2_sign,muldiv_i_rs2})));
wire [32:0] golden_res_remu = div_special_cases ? div_special_res :
($unsigned({div_rs1_sign,muldiv_i_rs1}) % ((div_by_0 | div_ovf) ? 1 : $unsigned({div_rs2_sign,muldiv_i_rs2})));
// To check golden and actual result are same
wire [`E203_XLEN-1:0] golden_res =
i_mul ? golden1_res_mul :
i_mulh ? golden1_res_mulh :
i_mulhsu ? golden1_res_mulhsu :
i_mulhu ? golden1_res_mulhu :
i_div ? golden_res_div [31:0] :
i_divu ? golden_res_divu[31:0] :
i_rem ? golden_res_rem [31:0] :
i_remu ? golden_res_remu[31:0] :
`E203_XLEN'b0;
CHECK_GOLD_AND_ACTUAL_SAME:
// Since the printed value is not aligned with posedge clock, so change it to negetive
assert property (@(negedge clk) disable iff ((~rst_n) | flush_pulse)
(muldiv_o_valid ? (golden_res == muldiv_o_wbck_wdat ) : 1'b1)
)
else begin
$display("??????????????????????????????????????????");
$display("??????????????????????????????????????????");
$display("{i_mul,i_mulh,i_mulhsu,i_mulhu,i_div,i_divu,i_rem,i_remu}=%d%d%d%d%d%d%d%d",i_mul,i_mulh,i_mulhsu,i_mulhu,i_div,i_divu,i_rem,i_remu);
$display("muldiv_i_rs1=%h\nmuldiv_i_rs2=%h\n",muldiv_i_rs1,muldiv_i_rs2);
$display("golden_res=%h\nmuldiv_o_wbck_wdat=%h",golden_res,muldiv_o_wbck_wdat);
$display("??????????????????????????????????????????");
$fatal ("\n Error: Oops, This should never happen. \n");
end
//synopsys translate_on
`endif//}
`endif//}
endmodule
|
module e203_subsys_plic(
input plic_icb_cmd_valid,
output plic_icb_cmd_ready,
input [`E203_ADDR_SIZE-1:0] plic_icb_cmd_addr,
input plic_icb_cmd_read,
input [`E203_XLEN-1:0] plic_icb_cmd_wdata,
input [`E203_XLEN/8-1:0] plic_icb_cmd_wmask,
//
output plic_icb_rsp_valid,
input plic_icb_rsp_ready,
output plic_icb_rsp_err,
output [`E203_XLEN-1:0] plic_icb_rsp_rdata,
output plic_ext_irq,
input wdg_irq_a,
input rtc_irq_a,
input qspi0_irq,
input qspi1_irq,
input qspi2_irq,
input uart0_irq,
input uart1_irq,
input pwm0_irq_0,
input pwm0_irq_1,
input pwm0_irq_2,
input pwm0_irq_3,
input pwm1_irq_0,
input pwm1_irq_1,
input pwm1_irq_2,
input pwm1_irq_3,
input pwm2_irq_0,
input pwm2_irq_1,
input pwm2_irq_2,
input pwm2_irq_3,
input i2c_mst_irq,
input gpio_irq_0,
input gpio_irq_1,
input gpio_irq_2,
input gpio_irq_3,
input gpio_irq_4,
input gpio_irq_5,
input gpio_irq_6,
input gpio_irq_7,
input gpio_irq_8,
input gpio_irq_9,
input gpio_irq_10,
input gpio_irq_11,
input gpio_irq_12,
input gpio_irq_13,
input gpio_irq_14,
input gpio_irq_15,
input gpio_irq_16,
input gpio_irq_17,
input gpio_irq_18,
input gpio_irq_19,
input gpio_irq_20,
input gpio_irq_21,
input gpio_irq_22,
input gpio_irq_23,
input gpio_irq_24,
input gpio_irq_25,
input gpio_irq_26,
input gpio_irq_27,
input gpio_irq_28,
input gpio_irq_29,
input gpio_irq_30,
input gpio_irq_31,
input clk,
input rst_n
);
assign plic_icb_rsp_err = 1'b0;
wire wdg_irq_r;
wire rtc_irq_r;
sirv_gnrl_sync # (
.DP(`E203_ASYNC_FF_LEVELS),
.DW(1)
) u_rtc_irq_sync(
.din_a (rtc_irq_a),
.dout (rtc_irq_r),
.clk (clk ),
.rst_n (rst_n)
);
sirv_gnrl_sync # (
.DP(`E203_ASYNC_FF_LEVELS),
.DW(1)
) u_wdg_irq_sync(
.din_a (wdg_irq_a),
.dout (wdg_irq_r),
.clk (clk ),
.rst_n (rst_n)
);
wire plic_irq_i_0 = wdg_irq_r;
wire plic_irq_i_1 = rtc_irq_r;
wire plic_irq_i_2 = uart0_irq;
wire plic_irq_i_3 = uart1_irq;
wire plic_irq_i_4 = qspi0_irq;
wire plic_irq_i_5 = qspi1_irq;
wire plic_irq_i_6 = qspi2_irq;
wire plic_irq_i_7 = gpio_irq_0 ;
wire plic_irq_i_8 = gpio_irq_1 ;
wire plic_irq_i_9 = gpio_irq_2 ;
wire plic_irq_i_10 = gpio_irq_3 ;
wire plic_irq_i_11 = gpio_irq_4 ;
wire plic_irq_i_12 = gpio_irq_5 ;
wire plic_irq_i_13 = gpio_irq_6 ;
wire plic_irq_i_14 = gpio_irq_7 ;
wire plic_irq_i_15 = gpio_irq_8 ;
wire plic_irq_i_16 = gpio_irq_9 ;
wire plic_irq_i_17 = gpio_irq_10;
wire plic_irq_i_18 = gpio_irq_11;
wire plic_irq_i_19 = gpio_irq_12;
wire plic_irq_i_20 = gpio_irq_13;
wire plic_irq_i_21 = gpio_irq_14;
wire plic_irq_i_22 = gpio_irq_15;
wire plic_irq_i_23 = gpio_irq_16;
wire plic_irq_i_24 = gpio_irq_17;
wire plic_irq_i_25 = gpio_irq_18;
wire plic_irq_i_26 = gpio_irq_19;
wire plic_irq_i_27 = gpio_irq_20;
wire plic_irq_i_28 = gpio_irq_21;
wire plic_irq_i_29 = gpio_irq_22;
wire plic_irq_i_30 = gpio_irq_23;
wire plic_irq_i_31 = gpio_irq_24;
wire plic_irq_i_32 = gpio_irq_25;
wire plic_irq_i_33 = gpio_irq_26;
wire plic_irq_i_34 = gpio_irq_27;
wire plic_irq_i_35 = gpio_irq_28;
wire plic_irq_i_36 = gpio_irq_29;
wire plic_irq_i_37 = gpio_irq_30;
wire plic_irq_i_38 = gpio_irq_31;
wire plic_irq_i_39 = pwm0_irq_0;
wire plic_irq_i_40 = pwm0_irq_1;
wire plic_irq_i_41 = pwm0_irq_2;
wire plic_irq_i_42 = pwm0_irq_3;
wire plic_irq_i_43 = pwm1_irq_0;
wire plic_irq_i_44 = pwm1_irq_1;
wire plic_irq_i_45 = pwm1_irq_2;
wire plic_irq_i_46 = pwm1_irq_3;
wire plic_irq_i_47 = pwm2_irq_0;
wire plic_irq_i_48 = pwm2_irq_1;
wire plic_irq_i_49 = pwm2_irq_2;
wire plic_irq_i_50 = pwm2_irq_3;
wire plic_irq_i_51 = i2c_mst_irq;
sirv_plic_top u_sirv_plic_top(
.clk (clk ),
.rst_n (rst_n ),
.i_icb_cmd_valid (plic_icb_cmd_valid),
.i_icb_cmd_ready (plic_icb_cmd_ready),
.i_icb_cmd_addr (plic_icb_cmd_addr ),
.i_icb_cmd_read (plic_icb_cmd_read ),
.i_icb_cmd_wdata (plic_icb_cmd_wdata),
.i_icb_rsp_valid (plic_icb_rsp_valid),
.i_icb_rsp_ready (plic_icb_rsp_ready),
.i_icb_rsp_rdata (plic_icb_rsp_rdata),
.io_devices_0_0 (plic_irq_i_0 ),
.io_devices_0_1 (plic_irq_i_1 ),
.io_devices_0_2 (plic_irq_i_2 ),
.io_devices_0_3 (plic_irq_i_3 ),
.io_devices_0_4 (plic_irq_i_4 ),
.io_devices_0_5 (plic_irq_i_5 ),
.io_devices_0_6 (plic_irq_i_6 ),
.io_devices_0_7 (plic_irq_i_7 ),
.io_devices_0_8 (plic_irq_i_8 ),
.io_devices_0_9 (plic_irq_i_9 ),
.io_devices_0_10 (plic_irq_i_10),
.io_devices_0_11 (plic_irq_i_11),
.io_devices_0_12 (plic_irq_i_12),
.io_devices_0_13 (plic_irq_i_13),
.io_devices_0_14 (plic_irq_i_14),
.io_devices_0_15 (plic_irq_i_15),
.io_devices_0_16 (plic_irq_i_16),
.io_devices_0_17 (plic_irq_i_17),
.io_devices_0_18 (plic_irq_i_18),
.io_devices_0_19 (plic_irq_i_19),
.io_devices_0_20 (plic_irq_i_20),
.io_devices_0_21 (plic_irq_i_21),
.io_devices_0_22 (plic_irq_i_22),
.io_devices_0_23 (plic_irq_i_23),
.io_devices_0_24 (plic_irq_i_24),
.io_devices_0_25 (plic_irq_i_25),
.io_devices_0_26 (plic_irq_i_26),
.io_devices_0_27 (plic_irq_i_27),
.io_devices_0_28 (plic_irq_i_28),
.io_devices_0_29 (plic_irq_i_29),
.io_devices_0_30 (plic_irq_i_30),
.io_devices_0_31 (plic_irq_i_31),
.io_devices_0_32 (plic_irq_i_32),
.io_devices_0_33 (plic_irq_i_33),
.io_devices_0_34 (plic_irq_i_34),
.io_devices_0_35 (plic_irq_i_35),
.io_devices_0_36 (plic_irq_i_36),
.io_devices_0_37 (plic_irq_i_37),
.io_devices_0_38 (plic_irq_i_38),
.io_devices_0_39 (plic_irq_i_39),
.io_devices_0_40 (plic_irq_i_40),
.io_devices_0_41 (plic_irq_i_41),
.io_devices_0_42 (plic_irq_i_42),
.io_devices_0_43 (plic_irq_i_43),
.io_devices_0_44 (plic_irq_i_44),
.io_devices_0_45 (plic_irq_i_45),
.io_devices_0_46 (plic_irq_i_46),
.io_devices_0_47 (plic_irq_i_47),
.io_devices_0_48 (plic_irq_i_48),
.io_devices_0_49 (plic_irq_i_49),
.io_devices_0_50 (plic_irq_i_50),
.io_devices_0_51 (plic_irq_i_51),
.io_harts_0_0 (plic_ext_irq )
);
endmodule
|
module e203_dtcm_ctrl(
output dtcm_active,
// The cgstop is coming from CSR (0xBFE mcgstop)'s filed 1
// // This register is our self-defined CSR register to disable the
// DTCM SRAM clock gating for debugging purpose
input tcm_cgstop,
// Note: the DTCM ICB interface only support the single-transaction
//////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////
// LSU ICB to DTCM
// * Bus cmd channel
input lsu2dtcm_icb_cmd_valid, // Handshake valid
output lsu2dtcm_icb_cmd_ready, // Handshake ready
// Note: The data on rdata or wdata channel must be naturally
// aligned, this is in line with the AXI definition
input [`E203_DTCM_ADDR_WIDTH-1:0] lsu2dtcm_icb_cmd_addr, // Bus transaction start addr
input lsu2dtcm_icb_cmd_read, // Read or write
input [32-1:0] lsu2dtcm_icb_cmd_wdata,
input [4-1:0] lsu2dtcm_icb_cmd_wmask,
// * Bus RSP channel
output lsu2dtcm_icb_rsp_valid, // Response valid
input lsu2dtcm_icb_rsp_ready, // Response ready
output lsu2dtcm_icb_rsp_err, // Response error
// Note: the RSP rdata is inline with AXI definition
output [32-1:0] lsu2dtcm_icb_rsp_rdata,
`ifdef E203_HAS_DTCM_EXTITF //{
//////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////
// External-agent ICB to DTCM
// * Bus cmd channel
input ext2dtcm_icb_cmd_valid, // Handshake valid
output ext2dtcm_icb_cmd_ready, // Handshake ready
// Note: The data on rdata or wdata channel must be naturally
// aligned, this is in line with the AXI definition
input [`E203_DTCM_ADDR_WIDTH-1:0] ext2dtcm_icb_cmd_addr, // Bus transaction start addr
input ext2dtcm_icb_cmd_read, // Read or write
input [32-1:0] ext2dtcm_icb_cmd_wdata,
input [ 4-1:0] ext2dtcm_icb_cmd_wmask,
// * Bus RSP channel
output ext2dtcm_icb_rsp_valid, // Response valid
input ext2dtcm_icb_rsp_ready, // Response ready
output ext2dtcm_icb_rsp_err, // Response error
// Note: the RSP rdata is inline with AXI definition
output [32-1:0] ext2dtcm_icb_rsp_rdata,
`endif//}
output dtcm_ram_cs,
output dtcm_ram_we,
output [`E203_DTCM_RAM_AW-1:0] dtcm_ram_addr,
output [`E203_DTCM_RAM_MW-1:0] dtcm_ram_wem,
output [`E203_DTCM_RAM_DW-1:0] dtcm_ram_din,
input [`E203_DTCM_RAM_DW-1:0] dtcm_ram_dout,
output clk_dtcm_ram,
input test_mode,
input clk,
input rst_n
);
wire arbt_icb_cmd_valid;
wire arbt_icb_cmd_ready;
wire [`E203_DTCM_ADDR_WIDTH-1:0] arbt_icb_cmd_addr;
wire arbt_icb_cmd_read;
wire [`E203_DTCM_DATA_WIDTH-1:0] arbt_icb_cmd_wdata;
wire [`E203_DTCM_WMSK_WIDTH-1:0] arbt_icb_cmd_wmask;
wire arbt_icb_rsp_valid;
wire arbt_icb_rsp_ready;
wire arbt_icb_rsp_err;
wire [`E203_DTCM_DATA_WIDTH-1:0] arbt_icb_rsp_rdata;
`ifdef E203_HAS_DTCM_EXTITF //{
localparam DTCM_ARBT_I_NUM = 2;
localparam DTCM_ARBT_I_PTR_W = 1;
`else//}{
localparam DTCM_ARBT_I_NUM = 1;
localparam DTCM_ARBT_I_PTR_W = 1;
`endif//}
wire [DTCM_ARBT_I_NUM*1-1:0] arbt_bus_icb_cmd_valid;
wire [DTCM_ARBT_I_NUM*1-1:0] arbt_bus_icb_cmd_ready;
wire [DTCM_ARBT_I_NUM*`E203_DTCM_ADDR_WIDTH-1:0] arbt_bus_icb_cmd_addr;
wire [DTCM_ARBT_I_NUM*1-1:0] arbt_bus_icb_cmd_read;
wire [DTCM_ARBT_I_NUM*`E203_DTCM_DATA_WIDTH-1:0] arbt_bus_icb_cmd_wdata;
wire [DTCM_ARBT_I_NUM*`E203_DTCM_WMSK_WIDTH-1:0] arbt_bus_icb_cmd_wmask;
wire [DTCM_ARBT_I_NUM*1-1:0] arbt_bus_icb_rsp_valid;
wire [DTCM_ARBT_I_NUM*1-1:0] arbt_bus_icb_rsp_ready;
wire [DTCM_ARBT_I_NUM*1-1:0] arbt_bus_icb_rsp_err;
wire [DTCM_ARBT_I_NUM*`E203_DTCM_DATA_WIDTH-1:0] arbt_bus_icb_rsp_rdata;
assign arbt_bus_icb_cmd_valid =
//LSU take higher priority
{
`ifdef E203_HAS_DTCM_EXTITF //{
ext2dtcm_icb_cmd_valid,
`endif//}
lsu2dtcm_icb_cmd_valid
} ;
assign arbt_bus_icb_cmd_addr =
{
`ifdef E203_HAS_DTCM_EXTITF //{
ext2dtcm_icb_cmd_addr,
`endif//}
lsu2dtcm_icb_cmd_addr
} ;
assign arbt_bus_icb_cmd_read =
{
`ifdef E203_HAS_DTCM_EXTITF //{
ext2dtcm_icb_cmd_read,
`endif//}
lsu2dtcm_icb_cmd_read
} ;
assign arbt_bus_icb_cmd_wdata =
{
`ifdef E203_HAS_DTCM_EXTITF //{
ext2dtcm_icb_cmd_wdata,
`endif//}
lsu2dtcm_icb_cmd_wdata
} ;
assign arbt_bus_icb_cmd_wmask =
{
`ifdef E203_HAS_DTCM_EXTITF //{
ext2dtcm_icb_cmd_wmask,
`endif//}
lsu2dtcm_icb_cmd_wmask
} ;
assign {
`ifdef E203_HAS_DTCM_EXTITF //{
ext2dtcm_icb_cmd_ready,
`endif//}
lsu2dtcm_icb_cmd_ready
} = arbt_bus_icb_cmd_ready;
assign {
`ifdef E203_HAS_DTCM_EXTITF //{
ext2dtcm_icb_rsp_valid,
`endif//}
lsu2dtcm_icb_rsp_valid
} = arbt_bus_icb_rsp_valid;
assign {
`ifdef E203_HAS_DTCM_EXTITF //{
ext2dtcm_icb_rsp_err,
`endif//}
lsu2dtcm_icb_rsp_err
} = arbt_bus_icb_rsp_err;
assign {
`ifdef E203_HAS_DTCM_EXTITF //{
ext2dtcm_icb_rsp_rdata,
`endif//}
lsu2dtcm_icb_rsp_rdata
} = arbt_bus_icb_rsp_rdata;
assign arbt_bus_icb_rsp_ready = {
`ifdef E203_HAS_DTCM_EXTITF //{
ext2dtcm_icb_rsp_ready,
`endif//}
lsu2dtcm_icb_rsp_ready
};
sirv_gnrl_icb_arbt # (
.ARBT_SCHEME (0),// Priority based
.ALLOW_0CYCL_RSP (0),// Dont allow the 0 cycle response because for ITCM and DTCM,
// Dcache, .etc, definitely they cannot reponse as 0 cycle
.FIFO_OUTS_NUM (`E203_DTCM_OUTS_NUM),
.FIFO_CUT_READY(0),
.USR_W (1),
.ARBT_NUM (DTCM_ARBT_I_NUM ),
.ARBT_PTR_W (DTCM_ARBT_I_PTR_W),
.AW (`E203_DTCM_ADDR_WIDTH),
.DW (`E203_DTCM_DATA_WIDTH)
) u_dtcm_icb_arbt(
.o_icb_cmd_valid (arbt_icb_cmd_valid ) ,
.o_icb_cmd_ready (arbt_icb_cmd_ready ) ,
.o_icb_cmd_read (arbt_icb_cmd_read ) ,
.o_icb_cmd_addr (arbt_icb_cmd_addr ) ,
.o_icb_cmd_wdata (arbt_icb_cmd_wdata ) ,
.o_icb_cmd_wmask (arbt_icb_cmd_wmask) ,
.o_icb_cmd_burst () ,
.o_icb_cmd_beat () ,
.o_icb_cmd_lock () ,
.o_icb_cmd_excl () ,
.o_icb_cmd_size () ,
.o_icb_cmd_usr () ,
.o_icb_rsp_valid (arbt_icb_rsp_valid ) ,
.o_icb_rsp_ready (arbt_icb_rsp_ready ) ,
.o_icb_rsp_err (arbt_icb_rsp_err) ,
.o_icb_rsp_rdata (arbt_icb_rsp_rdata ) ,
.o_icb_rsp_usr (1'b0),
.o_icb_rsp_excl_ok (1'b0),
.i_bus_icb_cmd_ready (arbt_bus_icb_cmd_ready ) ,
.i_bus_icb_cmd_valid (arbt_bus_icb_cmd_valid ) ,
.i_bus_icb_cmd_read (arbt_bus_icb_cmd_read ) ,
.i_bus_icb_cmd_addr (arbt_bus_icb_cmd_addr ) ,
.i_bus_icb_cmd_wdata (arbt_bus_icb_cmd_wdata ) ,
.i_bus_icb_cmd_wmask (arbt_bus_icb_cmd_wmask) ,
.i_bus_icb_cmd_burst ({2*DTCM_ARBT_I_NUM{1'b0}}) ,
.i_bus_icb_cmd_beat ({2*DTCM_ARBT_I_NUM{1'b0}}) ,
.i_bus_icb_cmd_lock ({1*DTCM_ARBT_I_NUM{1'b0}}),
.i_bus_icb_cmd_excl ({1*DTCM_ARBT_I_NUM{1'b0}}),
.i_bus_icb_cmd_size ({2*DTCM_ARBT_I_NUM{1'b0}}),
.i_bus_icb_cmd_usr ({1*DTCM_ARBT_I_NUM{1'b0}}),
.i_bus_icb_rsp_valid (arbt_bus_icb_rsp_valid ) ,
.i_bus_icb_rsp_ready (arbt_bus_icb_rsp_ready ) ,
.i_bus_icb_rsp_err (arbt_bus_icb_rsp_err) ,
.i_bus_icb_rsp_rdata (arbt_bus_icb_rsp_rdata ) ,
.i_bus_icb_rsp_usr (),
.i_bus_icb_rsp_excl_ok (),
.clk (clk ) ,
.rst_n (rst_n)
);
wire sram_icb_cmd_ready;
wire sram_icb_cmd_valid;
wire [`E203_DTCM_ADDR_WIDTH-1:0] sram_icb_cmd_addr;
wire sram_icb_cmd_read;
wire [`E203_DTCM_DATA_WIDTH-1:0] sram_icb_cmd_wdata;
wire [`E203_DTCM_WMSK_WIDTH-1:0] sram_icb_cmd_wmask;
assign arbt_icb_cmd_ready = sram_icb_cmd_ready;
assign sram_icb_cmd_valid = arbt_icb_cmd_valid;
assign sram_icb_cmd_addr = arbt_icb_cmd_addr;
assign sram_icb_cmd_read = arbt_icb_cmd_read;
assign sram_icb_cmd_wdata = arbt_icb_cmd_wdata;
assign sram_icb_cmd_wmask = arbt_icb_cmd_wmask;
wire sram_icb_rsp_valid;
wire sram_icb_rsp_ready;
wire [`E203_DTCM_DATA_WIDTH-1:0] sram_icb_rsp_rdata;
wire sram_icb_rsp_err;
wire dtcm_sram_ctrl_active;
wire sram_icb_rsp_read;
`ifndef E203_HAS_ECC //{
sirv_sram_icb_ctrl #(
.DW (`E203_DTCM_DATA_WIDTH),
.AW (`E203_DTCM_ADDR_WIDTH),
.MW (`E203_DTCM_WMSK_WIDTH),
.AW_LSB (2),// DTCM is 32bits wide, so the LSB is 2
.USR_W (1)
) u_sram_icb_ctrl (
.sram_ctrl_active (dtcm_sram_ctrl_active),
.tcm_cgstop (tcm_cgstop),
.i_icb_cmd_valid (sram_icb_cmd_valid),
.i_icb_cmd_ready (sram_icb_cmd_ready),
.i_icb_cmd_read (sram_icb_cmd_read ),
.i_icb_cmd_addr (sram_icb_cmd_addr ),
.i_icb_cmd_wdata (sram_icb_cmd_wdata),
.i_icb_cmd_wmask (sram_icb_cmd_wmask),
.i_icb_cmd_usr (sram_icb_cmd_read ),
.i_icb_rsp_valid (sram_icb_rsp_valid),
.i_icb_rsp_ready (sram_icb_rsp_ready),
.i_icb_rsp_rdata (sram_icb_rsp_rdata),
.i_icb_rsp_usr (sram_icb_rsp_read),
.ram_cs (dtcm_ram_cs ),
.ram_we (dtcm_ram_we ),
.ram_addr (dtcm_ram_addr),
.ram_wem (dtcm_ram_wem ),
.ram_din (dtcm_ram_din ),
.ram_dout (dtcm_ram_dout),
.clk_ram (clk_dtcm_ram ),
.test_mode(test_mode ),
.clk (clk ),
.rst_n(rst_n)
);
assign sram_icb_rsp_err = 1'b0;
`endif//}
assign sram_icb_rsp_ready = arbt_icb_rsp_ready;
assign arbt_icb_rsp_valid = sram_icb_rsp_valid;
assign arbt_icb_rsp_err = sram_icb_rsp_err;
assign arbt_icb_rsp_rdata = sram_icb_rsp_rdata;
assign dtcm_active = lsu2dtcm_icb_cmd_valid | dtcm_sram_ctrl_active
`ifdef E203_HAS_DTCM_EXTITF //{
| ext2dtcm_icb_cmd_valid
`endif//}
;
endmodule
|
module reset_sys (
input slowest_sync_clk,
input ext_reset_in,
input aux_reset_in,//Not used
input mb_debug_sys_rst,//Not used
input dcm_locked,
output mb_reset,// Not used
output bus_struct_reset,// Not used
output peripheral_reset,
output interconnect_aresetn,// Not used
output peripheral_aresetn// Not used
);
wire clk = slowest_sync_clk;
wire rst_n = ext_reset_in;
reg record_rst_r;
// When the peripheral_reset is really asserted, then we can clear the record rst
wire record_rst_clr = peripheral_reset;
always @(posedge clk or negedge rst_n) begin
if(!rst_n) begin
record_rst_r <= 1'b1;
end
else if (record_rst_clr) begin
record_rst_r <= 1'b0;
end
end
reg gen_rst_r;
// When the locked and the record_rst is there, then we assert the gen_rst
wire gen_rst_set = dcm_locked & record_rst_r;
// When the gen_rst asserted with max cycles, then we de-assert it
wire gen_rst_cnt_is_max;
wire gen_rst_clr = gen_rst_r & gen_rst_cnt_is_max;
always @(posedge clk or negedge rst_n) begin
if(!rst_n) begin
gen_rst_r <= 1'b0;
end
else if (gen_rst_set) begin
gen_rst_r <= 1'b1;
end
else if (gen_rst_clr) begin
gen_rst_r <= 1'b0;
end
end
assign peripheral_reset = gen_rst_r;
reg[9:0] gen_rst_cnt_r;
// When the gen_rst is asserted, it need to be clear
wire gen_rst_cnt_clr = gen_rst_set;
// When the gen_rst is asserted, and the counter is not reach the max value
wire gen_rst_cnt_inc = gen_rst_r & (~gen_rst_cnt_is_max);
always @(posedge clk or negedge rst_n) begin
if(!rst_n) begin
gen_rst_cnt_r <= 10'b0;
end
else if (gen_rst_cnt_clr) begin
gen_rst_cnt_r <= 10'b0;
end
else if (gen_rst_cnt_inc) begin
gen_rst_cnt_r <= gen_rst_cnt_r + 1'b1;
end
end
assign gen_rst_cnt_is_max = (gen_rst_cnt_r == 10'd256);
endmodule
|
module riscv_pll (
input wire refclk, // refclk.clk
input wire rst, // reset.reset
output wire outclk_0, // outclk0.clk
output wire outclk_1, // outclk1.clk
output wire locked // locked.export
);
riscv_pll_0002 riscv_pll_inst (
.refclk (refclk), // refclk.clk
.rst (rst), // reset.reset
.outclk_0 (outclk_0), // outclk0.clk
.outclk_1 (outclk_1), // outclk1.clk
.locked (locked) // locked.export
);
endmodule
|
module riscv_ram32 (
address,
byteena,
clock,
data,
rden,
wren,
q);
input [7:0] address;
input [3:0] byteena;
input clock;
input [31:0] data;
input rden;
input wren;
output [31:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 [3:0] byteena;
tri1 clock;
tri1 rden;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [31:0] sub_wire0;
wire [31:0] q = sub_wire0[31:0];
altsyncram altsyncram_component (
.address_a (address),
.byteena_a (byteena),
.clock0 (clock),
.data_a (data),
.rden_a (rden),
.wren_a (wren),
.q_a (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.address_b (1'b1),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_b (1'b1),
.eccstatus (),
.q_b (),
.rden_b (1'b1),
.wren_b (1'b0));
defparam
altsyncram_component.byte_size = 8,
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.intended_device_family = "Cyclone V",
altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 256,
altsyncram_component.operation_mode = "SINGLE_PORT",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_reg_a = "UNREGISTERED",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.read_during_write_mode_port_a = "NEW_DATA_NO_NBE_READ",
altsyncram_component.widthad_a = 8,
altsyncram_component.width_a = 32,
altsyncram_component.width_byteena_a = 4;
endmodule
|
module riscv_ram64 (
address,
byteena,
clock,
data,
rden,
wren,
q);
input [12:0] address;
input [7:0] byteena;
input clock;
input [63:0] data;
input rden;
input wren;
output [63:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 [7:0] byteena;
tri1 clock;
tri1 rden;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
endmodule
|
module riscv_ram32 (
address,
byteena,
clock,
data,
rden,
wren,
q);
input [7:0] address;
input [3:0] byteena;
input clock;
input [31:0] data;
input rden;
input wren;
output [31:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 [3:0] byteena;
tri1 clock;
tri1 rden;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
endmodule
|
module riscv_ram64 (
address,
byteena,
clock,
data,
rden,
wren,
q);
input [12:0] address;
input [7:0] byteena;
input clock;
input [63:0] data;
input rden;
input wren;
output [63:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 [7:0] byteena;
tri1 clock;
tri1 rden;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [63:0] sub_wire0;
wire [63:0] q = sub_wire0[63:0];
altsyncram altsyncram_component (
.address_a (address),
.byteena_a (byteena),
.clock0 (clock),
.data_a (data),
.rden_a (rden),
.wren_a (wren),
.q_a (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.address_b (1'b1),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_b (1'b1),
.eccstatus (),
.q_b (),
.rden_b (1'b1),
.wren_b (1'b0));
defparam
altsyncram_component.byte_size = 8,
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
`ifdef NO_PLI
altsyncram_component.init_file = "./software/led_blink_itcm.rif"
`else
altsyncram_component.init_file = "./software/led_blink_itcm.hex"
`endif
,
altsyncram_component.intended_device_family = "Cyclone V",
altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 8192,
altsyncram_component.operation_mode = "SINGLE_PORT",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_reg_a = "UNREGISTERED",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.read_during_write_mode_port_a = "NEW_DATA_NO_NBE_READ",
altsyncram_component.widthad_a = 13,
altsyncram_component.width_a = 64,
altsyncram_component.width_byteena_a = 8;
endmodule
|
module riscv_pll_0002(
// interface 'refclk'
input wire refclk,
// interface 'reset'
input wire rst,
// interface 'outclk0'
output wire outclk_0,
// interface 'outclk1'
output wire outclk_1,
// interface 'locked'
output wire locked
);
altera_pll #(
.fractional_vco_multiplier("false"),
.reference_clock_frequency("50.0 MHz"),
.operation_mode("direct"),
.number_of_clocks(2),
.output_clock_frequency0("16.000000 MHz"),
.phase_shift0("0 ps"),
.duty_cycle0(50),
.output_clock_frequency1("8.387096 MHz"),
.phase_shift1("0 ps"),
.duty_cycle1(50),
.output_clock_frequency2("0 MHz"),
.phase_shift2("0 ps"),
.duty_cycle2(50),
.output_clock_frequency3("0 MHz"),
.phase_shift3("0 ps"),
.duty_cycle3(50),
.output_clock_frequency4("0 MHz"),
.phase_shift4("0 ps"),
.duty_cycle4(50),
.output_clock_frequency5("0 MHz"),
.phase_shift5("0 ps"),
.duty_cycle5(50),
.output_clock_frequency6("0 MHz"),
.phase_shift6("0 ps"),
.duty_cycle6(50),
.output_clock_frequency7("0 MHz"),
.phase_shift7("0 ps"),
.duty_cycle7(50),
.output_clock_frequency8("0 MHz"),
.phase_shift8("0 ps"),
.duty_cycle8(50),
.output_clock_frequency9("0 MHz"),
.phase_shift9("0 ps"),
.duty_cycle9(50),
.output_clock_frequency10("0 MHz"),
.phase_shift10("0 ps"),
.duty_cycle10(50),
.output_clock_frequency11("0 MHz"),
.phase_shift11("0 ps"),
.duty_cycle11(50),
.output_clock_frequency12("0 MHz"),
.phase_shift12("0 ps"),
.duty_cycle12(50),
.output_clock_frequency13("0 MHz"),
.phase_shift13("0 ps"),
.duty_cycle13(50),
.output_clock_frequency14("0 MHz"),
.phase_shift14("0 ps"),
.duty_cycle14(50),
.output_clock_frequency15("0 MHz"),
.phase_shift15("0 ps"),
.duty_cycle15(50),
.output_clock_frequency16("0 MHz"),
.phase_shift16("0 ps"),
.duty_cycle16(50),
.output_clock_frequency17("0 MHz"),
.phase_shift17("0 ps"),
.duty_cycle17(50),
.pll_type("General"),
.pll_subtype("General")
) altera_pll_i (
.rst (rst),
.outclk ({outclk_1, outclk_0}),
.locked (locked),
.fboutclk ( ),
.fbclk (1'b0),
.refclk (refclk)
);
endmodule
|
module priority_encoder(
input [7:0]in,
output reg [2:0]out);
always @(*)
begin
if(in[7]==1) out=3'b111;
else if(in[6]==1) out=3'b110;
else if(in[5]==1) out=3'b101;
else if(in[4]==1) out=3'b100;
else if(in[3]==1) out=3'b011;
else if(in[2]==1) out=3'b010;
else if(in[1]==1) out=3'b001;
else out=3'b000;
end
endmodule
|
module test_bench;
reg [7:0]in;
wire [2:0]out;
priority_encoder dut(in, out);
always
begin
in= $random;
#10;
end
initial
begin $monitor("in: %b out: %b",in, out);
#100 $finish;
end
endmodule
|
module lfsr (
input clk, reset,
output [7:0] lfsr_out
);
reg [7:0] data;
always @(posedge clk) begin
if (reset)
data <= 8'hff;
else
data <= {data[6:0], data[7] ^ data[5] ^ data[3] ^ data[1]};
end
assign lfsr_out = data;
endmodule
|
module test_bench;
reg clk, reset;
wire [7:0] lfsr_out;
lfsr dut(clk, reset, lfsr_out);
initial begin
clk = 0;
reset = 1;
#10 reset = 0;
end
always #5 clk = ~clk;
initial begin
$monitor("\t\t clk: %b lfsr_out: %b", clk, lfsr_out);
#115 $finish;
end
endmodule
|
module test_bench;
reg [3:0] bcd_in;
wire [3:0] excess3_out;
BCD2excess3 dut(bcd_in, excess3_out);
always begin
bcd_in= 4'd0;
#10;
bcd_in= 4'd1;
#10;
bcd_in= 4'd2;
#10;
bcd_in= 4'd3;
#10;
bcd_in= 4'd4;
#10;
bcd_in= 4'd5;
#10;
bcd_in= 4'd6;
#10;
bcd_in= 4'd7;
#10;
bcd_in= 4'd8;
#10;
bcd_in= 4'd9;
#10;
bcd_in= 4'd10;
#10;
bcd_in= 4'd11;
#10;
bcd_in= 4'd12;
#10;
bcd_in= 4'd13;
#10;
bcd_in= 4'd14;
#10;
bcd_in= 4'd15;
#10;
end
initial begin
$monitor("Input: %b Excess-3 Code: %b", bcd_in, excess3_out);
#160 $finish;
end
endmodule
|
module BCD2excess3(
input [3:0] bcd_in,
output reg [3:0] excess3_out
);
always@(bcd_in)
begin
case(bcd_in)
4'b0000 : excess3_out = 4'b0011;
4'b0001 : excess3_out = 4'b0100;
4'b0010 : excess3_out = 4'b0101;
4'b0011 : excess3_out = 4'b0110;
4'b0100 : excess3_out = 4'b0111;
4'b0101 : excess3_out = 4'b1000;
4'b0110 : excess3_out = 4'b1001;
4'b0111 : excess3_out = 4'b1010;
4'b1000 : excess3_out = 4'b1011;
4'b1001 : excess3_out = 4'b1100;
default : excess3_out = 4'bxxxx;
endcase
end
endmodule
|
module test_bench;
reg [3:0] a;
reg [3:0] b;
reg en;
wire [3:0] sdout;
wire cbout;
add_sub dut(a, b, en, sdout, cbout);
initial begin
a = 4'b1010;
b = 4'b0101;
en = 1'b0;
#10;
$display("a= %b b= %b sum = %b, carry = %b", a, b,sdout, cbout);
en = 1'b1;
#10;
$display("a= %b b= %b difference = %b, borrow = %b", a, b, sdout, cbout);
a = 4'b0100;
b = 4'b0111;
en = 1'b0;
#10;
$display("a= %b b= %b sum = %b, carry = %b", a, b,sdout, cbout);
en = 1'b1;
#10;
$display("a= %b b= %b difference = %b, borrow = %b", a, b, sdout, cbout);
a = 4'b1001;
b = 4'b1111;
en = 1'b0;
#10;
$display("a= %b b= %b sum = %b, carry = %b", a, b,sdout, cbout);
en = 1'b1;;
#10;
$display("a= %b b= %b difference = %b, borrow = %b", a, b, sdout, cbout);
a = 4'b0101;
b = 4'b1101;
en = 1'b0;
#10;
$display("a= %b b= %b sum = %b, carry = %b", a, b,sdout, cbout);
en = 1'b1;
#10;
$display("a= %b b= %b difference = %b, borrow = %b", a, b, sdout, cbout);
$finish;
end
endmodule
|
module full_adder(
input a, b, cin,
output sout, cout
);
assign sout = a^b^cin;
assign cout = (a&b) | (b&cin) | (a&cin);
endmodule
|
module add_sub(
input [3:0] A, B,
input en,
output [3:0] sdout,
output cbout
);
wire [2:0]c;
full_adder fa1(A[0], (B[0]^en), en, sdout[0], c[0]);
full_adder fa2(A[1], (B[1]^en), c[0], sdout[1], c[1]);
full_adder fa3(A[2], (B[2]^en), c[1], sdout[2], c[2]);
full_adder fa4(A[3], (B[3]^en), c[2], sdout[3], cbout);
endmodule
|
module encoder_8_3(
input[7:0]in,
output reg[2:0]out
);
always@(in)
begin
if(in[7]==1)
out=3'b111;
else if(in[6]==1)
out=3'b110;
else if(in[5]==1)
out=3'b101;
else if(in[4]==1)
out=3'b100;
else if(in[3]==1)
out=3'b011;
else if(in[2]==1)
out=3'b010;
else if(in[1]==1)
out=3'b001;
else
out=3'b000;
end
endmodule
|
module test_bench;
reg [7:0] in;
wire [2:0] out;
encoder_8_3 dut(in, out);
initial
begin
#0 in=8'b10000000;
#10 in=8'b01000000;
#10 in=8'b00100000;
#10 in=8'b00010000;
#10 in=8'b00001000;
#10 in=8'b00000100;
#10 in=8'b00000010;
#10 in=8'b00000001;
#10 in=8'b00000000;
end
initial
begin $monitor("in: %b out: %b ",in, out);
#90 $finish;
end
endmodule
|
module synchronous_asynchronous_reset(
input clk,rst,in,
output reg out_async,out_sync
);
////////// SYNCHRONOUS RESET //////////
always@(posedge clk)
begin
if(rst) out_sync<= 1'b0;
else out_sync <= in;
end
////////// ASYNCHRONOUS RESET /////////
always@(posedge clk, posedge rst)
begin
if(rst) out_async<= 1'b0;
else out_async <= in;
end
endmodule
|
module test_bench;
reg clk, rst, in;
wire out_async,out_sync;
synchronous_asynchronous_reset dut(clk, rst, in, out_async, out_sync);
initial begin
clk= 0; rst= 0; in= 1;
end
initial forever #130 clk<= ~clk;
initial forever #450 rst<= ~rst;
initial forever #400 in<= ~in;
initial #6000 $stop;
endmodule
|
module BCD_to_7segment(
input [3:0]BCD,
output [6:0]segment7
);
wire a,b,c,d,e,f,g;
assign a = BCD[3] | BCD[1] | (BCD[2]~^BCD[0]);
assign b = (~BCD[2])| (BCD[1]~^BCD[0]);
assign c = BCD[2] | (~BCD[1]) | (BCD[0]);
assign d = BCD[3] | ((~BCD[2])&(~BCD[0])) | ((~BCD[2])&BCD[1]) | (BCD[1]&(~BCD[0])) | (BCD[2]&(~BCD[1])&BCD[0]);
assign e = ~BCD[0]&(~BCD[2]|BCD[1]);
assign f = BCD[3] | (BCD[2]&(~BCD[1]|~BCD[0])) | ((~BCD[1])&(~BCD[0]));
assign g = BCD[3] | (BCD[2]&(~BCD[1])) | (BCD[1]&(~BCD[2]|~BCD[0]));
assign segment7= {a,b,c,d,e,f,g};
endmodule
|
module test_bench;
reg [3:0]BCD;
wire [6:0]segment7;
BCD_to_7segment dut(BCD, segment7);
always begin
BCD= 4'd0;
#10;
BCD= 4'd1;
#10;
BCD= 4'd2;
#10;
BCD= 4'd3;
#10;
BCD= 4'd4;
#10;
BCD= 4'd5;
#10;
BCD= 4'd6;
#10;
BCD= 4'd7;
#10;
BCD= 4'd8;
#10;
BCD= 4'd9;
#10;
end
initial begin
$monitor("\t BCD: %d : 7 segment display: %h", BCD, segment7);
#100 $finish;
end
endmodule
|
module even_or_odd(
input [3:0] number,
output reg even_odd);
parameter EVEN= 1'b1, ODD= 1'b0;
always@(number)
begin
even_odd= check_even_odd(number);
if(even_odd== 1'b1) $display("\t\t %d is an even number", number);
else $display("\t\t %d is an odd number", number);
end
function check_even_odd;
input [3:0]num;
begin
if(num%2== 0) check_even_odd= EVEN;
else check_even_odd= ODD;
end
endfunction
endmodule
|
module test_bench;
reg [3:0]number;
wire even_odd;
even_or_odd dut(number, even_odd);
always
begin
number=4'd6;
#10;
number=4'd3;
#10;
number=4'd14;
#10;
number=4'd10;
#10;
number=4'd11;
#10;
number=4'd7;
#10;
end
initial #60 $finish;
endmodule
|
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