module
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|
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module clk_edge_detector(
input clk, temp_clk,
output posedge_detect, negedge_detect, dualedge_detect
);
assign posedge_detect= clk & (~temp_clk);
assign negedge_detect= (~clk) & temp_clk;
assign dualedge_detect= clk ^ temp_clk;
endmodule
|
module test_bench;
reg clk, temp_clk;
wire posedge_detect, negedge_detect, dualedge_detect;
clk_edge_detector dut(clk, temp_clk, posedge_detect, negedge_detect, dualedge_detect);
initial begin
clk= 1'b0;
temp_clk= 1'b0;
end
initial forever #5 clk<= ~clk;
initial forever #5.5 temp_clk<= ~temp_clk;
initial begin
$monitor("clock: %b posedge: %b negedge: %b dualedge: %b", clk, posedge_detect, negedge_detect, dualedge_detect);
#30 $finish;
end
endmodule
|
module single_port_ram
#(parameter addr_width = 6,
parameter data_width = 8,
parameter depth = 128)
(input [data_width-1:0] data,
input [addr_width-1:0] address,
input we,clk,
output [data_width-1:0] q);
reg [data_width-1:0] ram [depth-1:0];
reg [addr_width-1:0] addr_reg;
always @(posedge clk)
begin
if(we)
ram[address] <=data;
else
addr_reg <=address;
end
assign q= ram[addr_reg];
endmodule
|
module test_bench;
parameter addr_width = 6;
parameter data_width = 8;
parameter depth = 128;
reg [data_width-1:0] data;
reg [addr_width-1:0] address;
reg we, clk;
wire [data_width-1:0] q;
single_port_ram dut(data, address, we, clk, q);
initial begin
clk=1'b1;
forever #5 clk=~clk;
end
initial begin
data= 8'hf0;
address= 6'd0;
we= 1'b1; //write data
#10;
data= 8'he1;
address= 6'd1;
#10;
data= 8'hd2;
address= 6'd2;
#10;
data= 8'hz;
//read operation
address= 5'd0;
we= 1'b0;
#10;
address= 5'd2;
#10;
address= 5'd1;
#10;
end
initial begin
$monitor("write enable: %b address: %b data: %b output: %b", we, address, data, q);
#60 $finish;
end
endmodule
|
module full_adder(
input a, b, cin,
output sout, cout
);
assign sout = a ^ b ^ cin;
assign cout = (a&b) | cin&(a^b);
endmodule
|
module parallel_adder(
input [3:0] A, B,
input carry_in,
output [3:0] sum,
output carry
);
wire [2:0] c;
full_adder fa1(A[0], B[0], carry_in, sum[0], c[0]);
full_adder fa2(A[1], B[1], c[0], sum[1], c[1]);
full_adder fa3(A[2], B[2], c[1], sum[2], c[2]);
full_adder fa4(A[3], B[3], c[2], sum[3], carry);
endmodule
|
module carry_skip_adder(
output [3:0]sum,
output cout,
input [3:0]a, b,
input cin
);
wire c, sel;
wire [3:0]p;
parallel_adder pa(a, b, cin, sum, c);
xor (p[0], a[0], b[0]),
(p[1], a[1], b[1]),
(p[2], a[2], b[2]),
(p[3], a[3], b[3]);
and (sel, p[0],p[1], p[2], p[3]);
assign cout = sel ? cin : c;
endmodule
|
module test_bench;
reg [3:0] a, b;
reg cin;
wire [3:0] sum;
wire carry;
carry_skip_adder dut(sum, carry, a, b, cin);
initial
begin
a = 4'b1000; b = 4'b0011; cin = 1'b0;
#10 a = 4'b0001; b = 4'b1010; cin = 1'b1;
#10 a = 4'b0110; b = 4'b0110; cin = 1'b0;
#10 a = 4'b0111; b = 4'b1110; cin = 1'b0;
#10 a = 4'b1001; b = 4'b0110; cin = 1'b1;
#10 a = 4'b1001; b = 4'b0100; cin = 1'b0;
#10 a = 4'b1111; b = 4'b1110; cin = 1'b1;
end
initial
begin $monitor("a=%b b=%b cin=%b Sum=%b Carry=%b",a,b,cin,sum,carry);
#70 $finish;
end
endmodule
|
module decoder_2_4(
input [1:0] i,
output reg[3:0] y);
always@(i)
begin
y=0;
case(i)
2'b00 : y[0] = 1'b1;
2'b01 : y[1] = 1'b1;
2'b10 : y[2] = 1'b1;
2'b11 : y[3] = 1'b1;
endcase
end
endmodule
|
module decoder_xor_xnor(
input a,b,
output xor_g, xnor_g
);
wire [3:0] w;
decoder_2_4 gate({a,b}, w);
assign xor_g= w[1] | w[2];
assign xnor_g= w[0] | w[3];
endmodule
|
module test_bench;
reg a, b;
wire xor_g, xnor_g;
decoder_xor_xnor dut(a, b, xor_g, xnor_g);
initial begin
a= 1'b0; b= 1'b0;
#10 a= 1'b0; b= 1'b1;
#10 a= 1'b1; b= 1'b0;
#10 a= 1'b1; b= 1'b1;
end
initial
begin $monitor("a: %b b: %b xor: %b xnor: %b",a, b, xor_g, xnor_g);
#40 $finish;
end
endmodule
|
module fsm_101_0110(
input din,clk,reset,
output reg y);
reg[2:0] cst, nst;
parameter S0=3'b000,
S1=3'b001,
S2=3'b010,
S3=3'b011,
S4=3'b100,
S5=3'b101;
always@ (posedge clk)
begin
if(reset)
cst<=S0;
else
cst<=nst;
end
always @(cst or din)
begin
case(cst)
S0: if(din==1'b1)
begin
nst<=S1;
y<=1'b0;
end
else
begin
nst<=S2;
y<=1'b0;
end
S1: if(din==1'b1)
begin
nst<=S1;
y<=1'b0;
end
else
begin
nst<=S3;
y<=1'b0;
end
S2: if(din==1'b1)
begin
nst<=S4;
y<=1'b0;
end
else
begin
nst<=S2;
y<=1'b0;
end
S3: if(din==1'b1)
begin
nst<=S4;
y<=1'b1;
end
else
begin
nst<=S2;
y<=1'b0;
end
S4: if(din==1'b1)
begin
nst<=S5;
y<=1'b0;
end
else
begin
nst<=S3;
y<=1'b0;
end
S5: if(din==1'b1)
begin
nst<=S1;
y<=1'b0;
end
else
begin
nst<=S3;
y<=1'b1;
end
default: nst<=S0;
endcase
end
endmodule
|
module test_bench;
reg din,clk,reset;
wire y;
fsm_101_0110 dut(din,clk,reset,y);
initial begin
clk= 1'b0;
forever #5 clk= ~clk;
end
initial begin
reset= 1'b1;
#10 reset= 1'b0;
#5 din= 1'b0;
#10 din= 1'b1;
#10 din= 1'b1;
#10 din= 1'b0;
#10 din= 1'b1;
#10 din= 1'b1;
#10 din= 1'b0;
#10 din= 1'b0;
#10 din= 1'b1;
#10 din= 1'b0;
#10 din= 1'b1;
#10 din= 1'b0;
#10 din= 1'b1;
#10 din= 1'b1;
#10 din= 1'b0;
end
initial begin
$monitor("\t\t clock: %d input: %d detect: %d",clk, din, y);
#180 $finish;
end
endmodule
|
module full_adder(
input A, B, Cin,
output reg Sout, Cout
);
always@(*) begin
Sout = A ^ B ^ Cin;
Cout = (A&B) | (B&Cin) | (Cin&A);
end
endmodule
|
module mux(
input a,b,sel,
output reg y
);
always@(*) y = (~sel&a) | (sel&b);
endmodule
|
module carry_select (
input [3:0]a,b,
input carry,
output [3:0]sum,
output cout
);
wire [16:1]w;
full_adder fa1 (a[0], b[0], 1'b0, w[1], w[2]);
full_adder fa2 (a[1], b[1], w[2], w[3], w[4]);
full_adder fa3 (a[2], b[2], w[4], w[5], w[6]);
full_adder fa4 (a[3], b[3], w[6], w[7], w[8]);
full_adder fa5 (a[0], b[0], 1'b1, w[9], w[10]);
full_adder fa6 (a[1], b[1], w[10], w[11], w[12]);
full_adder fa7 (a[2], b[2], w[12], w[13], w[14]);
full_adder fa8 (a[3], b[3], w[14], w[15], w[16]);
mux m1(w[1], w[9], carry, sum[0]);
mux m2(w[3], w[11], carry, sum[1]);
mux m3(w[5], w[13], carry, sum[2]);
mux m4(w[7], w[15], carry, sum[3]);
mux m5(w[8], w[16], carry, cout);
endmodule
|
module test_bench;
reg [3:0]a,b;
reg carry;
wire[3:0]sum;
wire cout ;
carry_select dut(a,b,carry,sum,cout);
initial begin
carry=1'b0;a=4'b1011;b=4'b1010;
#10 carry=1'b1;a=4'b1001;b=4'b1110;
#10 carry=1'b0;a=4'b0001;b=4'b1010;
#10 carry=1'b1;a=4'b1100;b=4'b0011;
end
initial begin
$monitor("a=%b b=%b carry=%b sum=%b cout=%b",a,b,carry,sum,cout);
#40 $finish;
end
endmodule
|
module piso (
input clk, reset, load,
input [2:0]parallel_in,
output serial_out
);
reg [2:0]q= 3'd0;
always @ (posedge clk)
begin
if(reset) q<= 0;
else begin
if (load)
q <= parallel_in;
else
begin
q[0]=q[1];
q[1]=q[2];
q[2]= 1'bx;
end
end
end
assign serial_out= q[0];
endmodule
|
module test_bench;
reg clk, reset, load;
reg [2:0] parallel_in;
wire serial_out;
piso dut(clk, reset, load, parallel_in, serial_out);
initial begin
clk=1'b0;
forever #5 clk=~clk;
end
initial begin
reset= 1;
#10 reset= 0;
load= 1'b1;
parallel_in= 3'b001;
#10 load= 1'b0;
#30 load= 1'b1;
parallel_in= 3'b100;
#10 load= 1'b0;
#30 load= 1'b1;
parallel_in= 3'b101;
#10 load= 1'b0;
end
initial begin
$monitor("\t\t clk: %d load: %d paralel_in: %b serial_out: %d", clk, load, parallel_in, serial_out);
#120 $finish;
end
endmodule
|
module D_flipflop(
input d, clk, reset,
output reg Q
);
always@(posedge clk)
begin
if(reset)
Q<= 1'b0;
else
Q <= d;
end
endmodule
|
module sipo(
input clk, reset, serial_in,
output [2:0] parallel_out
);
D_flipflop D2(serial_in, clk, reset, parallel_out[2]);
D_flipflop D1(parallel_out[2], clk, reset, parallel_out[1]);
D_flipflop D0(parallel_out[1], clk, reset, parallel_out[0]);
endmodule
|
module test_bench;
reg clk, reset, serial_in;
wire [2:0] parallel_out;
sipo dut(clk, reset, serial_in, parallel_out);
initial begin
clk=1'b0;
forever #5 clk=~clk;
end
initial begin
reset= 1'b1;
serial_in= 1'b0;
#10 reset= 1'b0;
#0 serial_in= 1'b1;
#10 serial_in= 1'b0;
#10 serial_in= 1'b1;
#10 serial_in= 1'b1;
#10 serial_in= 1'b0;
#10 serial_in= 1'b0;
#10 serial_in= 1'b1;
#10 serial_in= 1'b0;
#10 serial_in= 1'bx;
end
initial begin
$monitor("\t\t clk: %d reset: %d serial_in: %d parallel_out: %b", clk, reset, serial_in, parallel_out);
#120 $finish;
end
endmodule
|
module logic_gates(
input a, b,
output and_g,
output or_g,
output not_g,
output nand_g,
output nor_g,
output xor_g,
output xnor_g
);
assign and_g = a&b;
assign or_g = a|b;
assign not_g = ~a;
assign nand_g = ~(a&b);
assign nor_g = ~(a|b);
assign xor_g = a^b;
assign xnor_g = ~(a^b);
endmodule
|
module test_bench;
reg a, b;
wire and_g,
or_g,
not_g,
nand_g,
nor_g,
xor_g,
xnor_g;
logic_gates dut(a, b, and_g,or_g,not_g,nand_g,nor_g,xor_g,xnor_g);
initial begin
#10 a= 1'b0; b= 1'b0;
#10 a= 1'b0; b= 1'b1;
#10 a= 1'b1; b= 1'b0;
#10 a= 1'b1; b= 1'b1;
end
endmodule
|
module multiplier(
input [3:0]a,b,
output reg [7:0] out
);
reg [7:0] t1,t2,t3,t4;
always@(a,b)
begin
t1=0; t2=0; t3=0; t4=0;
if(b[0])
t1 = a<<0;
if(b[1])
t2 = a<<1;
if(b[2])
t3 = a<<2;
if(b[3])
t4 = a<<3;
out = t1+t2+t3+t4;
end
endmodule
|
module test_bench;
reg [3:0]a,b;
wire [7:0]mul_out;
multiplier dut(a, b, mul_out);
always begin
a=$random;
b=$random;
#10;
end
initial
begin $monitor("%0d * %0d = %0d ",a, b, mul_out);
#100 $finish;
end
endmodule
|
module lifo(
input [3:0] dataIn,
input rd_en, wr_en, rst, clk,
output reg empty, full,
output reg [3:0] dataOut
);
reg [3:0] stack_mem[0:3];
reg [2:0] stack_ptr;
integer i;
always @ (posedge clk)
begin
if (wr_en==0);
else begin
if (rst==1) begin
stack_ptr = 3'd4;
empty = stack_ptr[2];
dataOut = 4'h0;
for (i=0;i<4;i=i+1) begin
stack_mem[i]= 0;
end
end
else if (rst==0) begin
full = stack_ptr? 0:1;
empty = stack_ptr[2];
dataOut = 4'hx;
if (full == 1'b0 && rd_en == 1'b0) begin
stack_ptr = stack_ptr-1'b1;
full = stack_ptr? 0:1;
empty = stack_ptr[2];
stack_mem[stack_ptr] = dataIn;
end
else if (empty == 1'b0 && rd_en == 1'b1) begin
dataOut = stack_mem[stack_ptr];
stack_mem[stack_ptr] = 0;
stack_ptr = stack_ptr+1;
full = stack_ptr? 0:1;
empty = stack_ptr[2];
end
end
end
end
endmodule
|
module test_bench;
reg [3:0] dataIn;
reg rd_en, wr_en, rst, clk;
wire [3:0] dataOut;
wire empty, full;
lifo uut (dataIn, rd_en, wr_en, rst, clk, empty, full, dataOut);
initial begin
dataIn = 4'h0;
rd_en = 1'b0;
wr_en = 1'b0;
rst = 1'b1;
clk = 1'b0;
#10;
wr_en = 1'b1;
rst = 1'b1;
#40;
rst = 1'b0;
rd_en = 1'b0;
dataIn = 4'h0;
#20;
dataIn = 4'h3;
#20;
dataIn = 4'h7;
#20;
dataIn = 4'ha;
#20;
rd_en = 1'b1;
#100 $finish;
end
always #10 clk = ~clk;
always @(posedge clk) begin
$display("Data in: %d Data out: %d Empty: %d Full: %d", dataIn, dataOut, empty, full);
end
endmodule
|
module gray_counter(
input clk,rst,
output reg [3:0] gray_count
);
reg [3:0] bin_count;
always@(posedge clk)
begin
if(rst)
begin
gray_count=4'b0000;
bin_count=4'b0000;
end
else
begin
bin_count = bin_count + 1;
gray_count = {bin_count[3],bin_count[3]^bin_count[2],bin_count[2]^bin_count[1],bin_count[1]^bin_count[0]};
end
end
endmodule
|
module test_bench;
reg clk,reset;
wire [3:0] gray_count;
gray_counter dut(clk, reset, gray_count);
initial begin
clk= 1'b0;
forever #5 clk= ~clk;
end
initial begin
reset= 1'b1;
#10;
reset= 1'b0;
end
initial begin
$monitor("\t\t counter: %d", gray_count);
#175 $finish;
end
endmodule
|
module logic_gates(
input a, b,
output and_g,
output or_g,
output not_g,
output nand_g,
output nor_g,
output xor_g,
output xnor_g
);
and andgate(and_g, a, b);
or orgate(or_g, a, b);
not notgate(not_g, a);
nand nandgate(nand_g, a, b);
nor norgate(nor_g, a, b);
xor xorgate(xor_g, a, b);
xnor xnorgate(xnor_g, a, b);
endmodule
|
module gray2binary(
input [3:0] gray_in,
output [3:0] binary_out
);
buf buf1(binary_out[3],gray_in[3]);
xor xor1(binary_out[2],gray_in[2],binary_out[3]),
xor2(binary_out[1],gray_in[1],binary_out[2]),
xor3(binary_out[0],gray_in[0],binary_out[1]);
endmodule
|
module test_bench;
reg [3:0] gray_in;
wire [3:0]binary_out;
gray2binary dut(gray_in, binary_out);
initial begin
gray_in= 4'd0;
#10;
gray_in= 4'd1;
#10;
gray_in= 4'd2;
#10;
gray_in= 4'd3;
#10;
gray_in= 4'd4;
#10;
gray_in= 4'd5;
#10;
gray_in= 4'd6;
#10;
gray_in= 4'd7;
#10;
gray_in= 4'd8;
#10;
gray_in= 4'd9;
#10;
gray_in= 4'd10;
#10;
gray_in= 4'd11;
#10;
gray_in= 4'd12;
#10;
gray_in= 4'd13;
#10;
gray_in= 4'd14;
#10;
gray_in= 4'd15;
end
initial
begin $monitor("gray: %b -> binary: %b", gray_in, binary_out);
#160 $finish;
end
endmodule
|
module test_bench;
reg signed [3:0] Q,M;
wire signed [7:0] result;
booth_algorithm dut(Q,M,result);
initial begin
Q= 3; M= 7; #10;
Q= 3; M= -7; #10;
Q= -3; M= -7; #10;
Q= 5; M= 6; #10;
Q= 5; M= -6; #10;
Q= -5; M= -6; #10;
end
initial begin
$monitor("%d * %d = %d", Q,M,result);
#60 $finish;
end
endmodule
|
module booth_algorithm(
input signed [3:0] Q, M,
output reg signed [7:0] result
);
reg [1:0] operation;
integer i;
reg q0;
reg [3:0] M_comp;
always @(Q,M)
begin
result = 8'd0;
q0 = 1'b0;
M_comp = -M;
for (i=0; i<4; i=i+1)
begin
operation = { Q[i], q0 };
case(operation)
2'b10 : result[7:4] = result[7:4] + M_comp;
2'b01 : result[7:4] = result[7:4] + M;
endcase
result = result >> 1;
result[7] = result[6];
q0= Q[i];
end
end
endmodule
|
module half_adder(
input a,b,
output sum,carry
);
assign sum=a^b;
assign carry=a&b;
endmodule
|
module vedic_mul_2_2(
input [1:0] a,b,
output [3:0] out
);
wire [3:0] w;
and m1(out[0],a[0],b[0]);
and m2(w[0],a[0],b[1]);
and m3(w[1],a[1],b[0]);
and m4(w[2],a[1],b[1]);
half_adder ha1(w[0],w[1],out[1],w[3]);
half_adder ha2(w[3],w[2],out[2],out[3]);
endmodule
|
module test_bench;
reg [1:0]a,b;
wire [3:0]out;
vedic_mul_2_2 dut(a,b,out);
always begin
a=2'd2;
b=2'd1;
#10;
a=2'd3;
b=2'd2;
#10;
a=2'd0;
b=2'd1;
#10;
a=2'd3;
b=2'd1;
#10;
a=2'd2;
b=2'd2;
#10;
a=2'd3;
b=2'd3;
#10;
end
initial begin
$monitor("%d * %d = %d", a,b,out);
#60 $finish;
end
endmodule
|
module test_bench;
reg a, b, cin;
wire sum, carry;
full_adder dut(a, b, cin, sum, carry);
initial begin
a = 0; b = 0; cin = 0;
#10;
a = 0; b = 0; cin = 1;
#10;
a = 0; b = 1; cin = 0;
#10;
a = 0; b = 1; cin = 1;
#10;
a = 1; b = 0; cin = 0;
#10;
a = 1; b = 0; cin = 1;
#10;
a = 1; b = 1; cin = 0;
#10;
a = 1; b = 1; cin = 1;
#10;
end
initial begin
$monitor("a = %b, b = %b, cin = %b, sum = %b, carry = %b", a, b, cin, sum, carry);
#80 $finish;
end
endmodule
|
module mux2_1(
input m,n,
input sel,
output y_out
);
assign y_out= sel ? n : m;
endmodule
|
module full_adder(
input a,b,cin,
output sum, carry
);
wire [4:0]w;
mux2_1 m0(1'b1, 1'b0, a, w[0]);
mux2_1 m1(a, w[0], b, w[1]);
mux2_1 m2(1'b1, 1'b0, w[1], w[2]);
mux2_1 m3(w[1], w[2], cin, sum);
mux2_1 m4(1'b0, w[1], cin, w[3]);
mux2_1 m5(1'b0, a, b, w[4]);
mux2_1 m6(w[3], w[4], w[4], carry);
endmodule
|
module traffic_light_control(highway, small_road, sensor, clk, clr);
input sensor, clk, clr;
output reg [1:0] highway, small_road;
parameter RED=2'd0, YELLOW=2'd1, GREEN=2'd2;
parameter S0=3'd0,
S1=3'd1,
S2=3'd2,
S3=3'd3,
S4=3'd4;
reg[2:0] state, next_state;
always@(posedge clk)
if(clr)
state<=S0;
else
state<=next_state;
always@(state) begin
highway= GREEN;
small_road= RED;
case(state)
S0:;
S1: highway= YELLOW;
S2: highway= RED;
S3: begin
highway= RED;
small_road= GREEN;
end
S4: begin
highway= RED;
small_road= YELLOW;
end
endcase
end
always@(state or sensor) begin
case(state)
S0: if(sensor)
next_state= S1;
else
next_state= S0;
S1: begin
repeat (`G2YDELAY) next_state= S1;
next_state= S2;
end
S2: begin
repeat (`Y2RDELAY) next_state= S2;
next_state= S3;
end
S3: begin
if(sensor)
next_state= S3;
else
next_state= S4;
end
S4: begin
repeat (`G2YDELAY) next_state= S4;
next_state= S0;
end
default: next_state= S0;
endcase
end
endmodule
|
module test_bench;
reg sensor, clk, clr;
wire [1:0] highway, small_road;
traffic_light_control dut(highway, small_road, sensor, clk, clr);
initial begin
clk= 1'b0;
forever #10 clk= ~clk;
end
initial begin
clr= 1'b1;
sensor= 1'b0;
#20 clr= 1'b0;
#10 sensor= 1'b1;
#50 sensor= 1'b0;
#70 sensor= 1'b1;
#60 $stop;
end
endmodule
|
module JK_flipflop(
input j,k,clk,reset,
output reg Q
);
always@(posedge clk)
begin
if({reset})
Q <= 1'b0;
else
begin
case({j,k})
2'b00:Q<=Q;
2'b01:Q<=1'b0;
2'b10:Q<=1'b1;
2'b11:Q<=~Q;
endcase
end
end
endmodule
|
module test_bench;
reg clk,rst,j,k;
wire Q;
JK_flipflop dut(j,k,clk,rst,Q);
initial begin
clk=0;
forever #5 clk=~clk;
end
initial
begin
rst=1;
#10;
j = 1'b0;
k = 1'b0;
#10;
rst=0;
#10;
j = 1'b0;
k = 1'b1;
#10;
j = 1'b1;
k = 1'b0;
#10;
j = 1'b1;
k = 1'b1;
#10;
end
initial begin
$monitor("\t clk: %d J: %d K: %d Q: %d", clk, j, k, Q);
#80 $finish;
end
endmodule
|
module fsm_11001(
input din,clk,reset,
output reg y);
reg[2:0] cst, nst;
parameter S0=3'b000,
S1=3'b001,
S2=3'b010,
S3=3'b011,
S4=3'b100;
always@ (posedge clk)
begin
if(reset)
cst<=S0;
else
cst<=nst;
end
always @(cst or din)
begin
case(cst)
S0: if(din==1'b1)
begin
nst<=S1;
y<=1'b0;
end
else
begin
nst<=S0;
y<=1'b0;
end
S1: if(din==1'b1)
begin
nst<=S2;
y<=1'b0;
end
else
begin
nst<=S0;
y<=1'b0;
end
S2: if(din==1'b1)
begin
nst<=S0;
y<=1'b0;
end
else
begin
nst<=S3;
y<=1'b0;
end
S3: if(din==1'b1)
begin
nst<=S0;
y<=1'b0;
end
else
begin
nst<=S4;
y<=1'b0;
end
S4: if(din==1'b1)
begin
nst<=S0;
y<=1'b1;
end
else
begin
nst<=S0;
y<=1'b0;
end
default: nst<=S0;
endcase
end
endmodule
|
module test_bench;
reg din,clk,reset;
wire y;
fsm_11001 dut(din,clk,reset,y);
initial begin
clk= 1'b0;
forever #5 clk= ~clk;
end
initial begin
reset= 1'b1;
#10 reset= 1'b0;
#5 din= 1'b0;
#10 din= 1'b1;
#10 din= 1'b1;
#10 din= 1'b0;
#10 din= 1'b0;
#10 din= 1'b1;
#10 din= 1'b1;
#10 din= 1'b0;
#10 din= 1'b0;
#10 din= 1'b1;
#10 din= 1'b0;
#10 din= 1'b1;
#10 din= 1'b1;
#10 din= 1'b0;
#10 din= 1'b0;
#10 din= 1'b1;
end
initial begin
$monitor("\t\t clock: %d input: %d detect: %d",clk, din, y);
#180 $finish;
end
endmodule
|
module test_bench;
reg [7:0] data;
reg [2:0] amt;
wire [7:0] out;
barrel_shifter dut(data, amt, out);
initial begin
data= 8'hf0;
amt=0;
forever #10 amt= amt+1;
end
initial begin
$monitor("\t\t data: %b shifting amount: %d output: %b", data, amt, out);
#80 $finish;
end
endmodule
|
module mux_2_1(
input [1:0] i,
input sel,
output y_out
);
assign y_out= sel ? i[1] : i[0];
endmodule
|
module mux_4_1(
input [3:0] i,
input [1:0]select,
output y_out
);
wire [1:0]w;
mux_2_1 m1(i[1:0], select[0], w[0]);
mux_2_1 m2(i[3:2], select[0], w[1]);
mux_2_1 m3(w, select[1], y_out);
endmodule
|
module mux_8_1(
input [7:0] i,
input [2:0]select,
output y_out
);
wire [1:0]w;
mux_4_1 m1(i[3:0], select[1:0], w[0]);
mux_4_1 m2(i[7:4], select[1:0], w[1]);
mux_2_1 m3(w, select[2], y_out);
endmodule
|
module barrel_shifter(
input [7:0] data,
input [2:0] amt,
output [7:0] out
);
mux_8_1 m0(data, amt, out[0]);
mux_8_1 m1({data[0], data[7:1]}, amt, out[1]);
mux_8_1 m2({data[1:0], data[7:2]}, amt, out[2]);
mux_8_1 m3({data[2:0], data[7:3]}, amt, out[3]);
mux_8_1 m4({data[3:0], data[7:4]}, amt, out[4]);
mux_8_1 m5({data[4:0], data[7:5]}, amt, out[5]);
mux_8_1 m6({data[5:0], data[7:6]}, amt, out[6]);
mux_8_1 m7({data[6:0], data[7]}, amt, out[7]);
endmodule
|
module demux_1_2(
input sel,
input i,
output y0, y1
);
assign {y0,y1} = sel?{1'b0,i}: {i,1'b0};
endmodule
|
module demux_xor_xnor(
input a,b,
output xor_g, xnor_g
);
wire [3:0] w;
demux_1_2 demux1(b, ~a, w[0], w[1]);
demux_1_2 demux2(b, a, w[2], w[3]);
assign xor_g= w[1] | w[2];
assign xnor_g= w[0] | w[3];
endmodule
|
module test_bench;
reg a, b;
wire xor_g, xnor_g;
demux_xor_xnor dut(a, b, xor_g, xnor_g);
initial begin
a= 1'b0; b= 1'b0;
#10 a= 1'b0; b= 1'b1;
#10 a= 1'b1; b= 1'b0;
#10 a= 1'b1; b= 1'b1;
end
initial
begin $monitor("a: %b b: %b xor: %b xnor: %b",a, b, xor_g, xnor_g);
#40 $finish;
end
endmodule
|
module fsm_1011(
input clk,rst,din,
output reg y);
parameter S0=3'b000,
S1=3'b001,
S2=3'b010,
S3=3'b011,
S4=3'b100;
reg[2:0] cs, nst;
always @(posedge clk)
begin
if(rst)
cs<=S0;
else
cs<=nst;
end
always @(cs,din)
begin
case(cs)
S0: begin
if(din==1)
nst<=S1;
else
nst<=S0;
end
S1: begin
if(din==1)
nst<=S1;
else
nst<=S2;
end
S2: begin
if(din==1)
nst<=S3;
else
nst<=S0;
end
S3: begin
if(din==1)
nst<=S4;
else
nst<=S0;
end
S4: begin
if(din==1)
nst<=S1;
else
nst<=S0;
end
default: nst<=S0;
endcase
end
always @(cs)
begin
case(cs)
S0: y<=0;
S1: y<=0;
S2: y<=0;
S3: y<=0;
S4: y<=1;
default: y<=0;
endcase
end
endmodule
|
module test_bench;
reg din,clk,reset;
wire y;
fsm_1011 dut(clk,reset,din,y);
initial begin
clk= 1'b0;
forever #5 clk= ~clk;
end
initial begin
reset= 1'b1;
#10 reset= 1'b0;
#5 din= 1'b0;
#10 din= 1'b1;
#10 din= 1'b0;
#10 din= 1'b1;
#10 din= 1'b1;
#10 din= 1'b0;
#10 din= 1'b1;
#10 din= 1'b1;
#10 din= 1'b0;
#10 din= 1'b1;
#10 din= 1'b1;
#10 din= 1'b0;
#10 din= 1'b1;
end
initial begin
$monitor("\t\t clock: %d input: %d detect: %d",clk, din, y);
#150 $finish;
end
endmodule
|
module car_parking_management(
input clk, rst, sense_entry, sense_exit,
input [1:0] password_1, password_2,
output reg green_light, red_light,
output reg [6:0] hex_1, hex_2,
output reg [3:0] space_available, space_utilized, count_cars
);
reg [3:0] overall_space=4'b1000;
reg [2:0] current_state, next_state;
reg [1:0] wait_time;
//declaring parameters list
parameter idle = 3'b000,
wait_time_state=3'b001,
password_correct=3'b010,
password_incorrect=3'b011,
stop=3'b100;
//declarimg current state
always@(posedge clk) begin
if(rst==1) current_state<= idle;
else current_state<= next_state;
end
//parking space management
always@(posedge clk) begin
if(rst==1) begin //reseting whole design
space_available<= overall_space;
space_utilized<= 0;
count_cars<=4'b0;
end
else begin
if ((sense_entry==1) && (space_available>0))begin //entry of 1 vehicle
space_available<= space_available - 3'b001;
space_utilized<= space_utilized + 3'b001;
count_cars<=count_cars + 4'b0001;
end
else if ((sense_exit==1) && (space_utilized>0)) begin //exit of 1 vehicle
space_available<= space_available + 3'b001;
space_utilized<= space_utilized - 3'b001;
count_cars<= count_cars - 4'b0001;
end
else begin //no vehicle entered and exited
space_available<= overall_space;
space_utilized<= 0;
count_cars<=4'b0;
end
end
end
//declarationn of wait_timeing period in the wait_time_state
always@(posedge clk) begin
if(rst==1) wait_time<= 2'b0;
else begin
if(current_state==wait_time_state) wait_time<= wait_time + 2'b01;
else wait_time<= 2'b0;
end
end
//declaration of next state
always@(*) begin
case(current_state)
idle: begin
if((sense_entry==1) && (space_available>0)) next_state<= wait_time_state;
else next_state<= idle;
end
wait_time_state: begin
if(wait_time<= 3'b011) next_state<= wait_time_state;
else begin
if ((password_1==2'b01) && (password_2==2'b01)) next_state<= password_correct;
else next_state<= password_incorrect;
end
end
password_correct: begin
if((sense_entry==1) && (sense_exit==1)) next_state<= stop;
else if((sense_exit==1)) next_state<= idle;
else next_state<= password_correct;
end
password_incorrect: begin
if((password_1==2'b01) && (password_2==2'b01)) next_state<= password_correct;
else next_state<= password_incorrect;
end
stop: begin
if((password_1==2'b01) && (password_2==2'b01)) next_state<= password_correct;
else next_state<= stop;
end
default: next_state<= idle;
endcase
end
always@(posedge clk) begin
case(current_state)
idle: begin //starting state with no entry and exit of vehicles
green_light<= 1'b0;
red_light<= 1'b0;
hex_1<= 7'b0000000; //0
hex_2<= 7'b0000000; //0
end
wait_time_state: begin //vechile wait_timeing in the lobby
green_light<= ~green_light;
red_light<= 1'b0;
hex_1<= 7'b1111001; //alphabet-E
hex_2<= 7'b0110111; //N -> ENTER
end
password_correct: begin //vehicle entering and providing password_correct
green_light<= 1'b1;
red_light<= 1'b0;
hex_1<= 7'b1111001; //6
hex_2<= 7'b0000000; //0 -> GO
end
password_incorrect: begin //vehicle entering and providing password_incorrect
green_light<= 1'b0;
red_light<= 1'b1;
hex_1<= 7'b1111001; //E
hex_2<= 7'b1111001; //E -> ERROR
end
stop: begin //stay of the vehicle for some period
green_light<= 1'b0;
red_light<= ~red_light;
hex_1<= 7'b1101101; //5
hex_2<= 7'b1110011; //P -> STOP
end
endcase
end
endmodule
|
module test_bench;
reg clk, rst, sense_entry, sense_exit;
reg [1:0] password_1, password_2;
wire green_light, red_light;
wire [6:0] hex_1, hex_2;
wire [3:0] space_available, space_utilized, count_cars;
car_parking_management dut(clk, rst, sense_entry, sense_exit, password_1, password_2, green_light, red_light, hex_1, hex_2, space_available, space_utilized, count_cars);
initial begin
clk = 1;
forever #5 clk = ~clk;
end
initial begin
rst = 1;
sense_entry = 0;
sense_exit = 0;
password_1 = 0;
password_2 = 0;
#10;
rst = 1'b0;
sense_entry = 1'b1;
sense_exit = 1'b0;
password_1 = 2'b01;
password_2 = 2'b01;
#80; sense_exit = 1'b1; sense_entry = 1'b0;
end
initial begin
$monitor("time=%g, clk=%b, rst=%b, sense_entry=%b, sense_exit=%b, password_1=%b, password_2=%b,\ngreen_light=%b, red_light=%b, hex_1=%b, hex_2=%b, space_available=%d, space_utilized=%d, count_cars=%d", $time, clk, rst, sense_entry, sense_exit, password_1, password_2, green_light, red_light, hex_1, hex_2, space_available, space_utilized, count_cars);
#150 $finish;
end
endmodule
|
module vend(coin, clock, reset, newspaper);
//Input output port declarations
input [1:0] coin;
input clock;
input reset;
output newspaper;
//internal FSM state declarations
wire [1:0] NEXT_STATE;
reg [1:0] PRES_STATE;
//state encodings
parameter s0 = 2'b00,
s5 = 2'b01,
s10 = 2'b10,
s15 = 2'b11;
//Combinational logic
function [2:0] fsm;
input [1:0] fsm_coin;
input [1:0] fsm_PRES_STATE;
reg fsm_newspaper;
reg [1:0] fsm_NEXT_STATE;
begin
case (fsm_PRES_STATE)
s0: //state = s0
begin
if (fsm_coin == 2'b10)
begin
fsm_newspaper = 1'b0;
fsm_NEXT_STATE = s10;
end
else if (fsm_coin == 2'b01)
begin
fsm_newspaper = 1'b0;
fsm_NEXT_STATE = s5;
end
else
begin
fsm_newspaper = 1'b0;
fsm_NEXT_STATE = s0;
end
end
s5: //state = s5
begin
if (fsm_coin == 2'b10)
begin
fsm_newspaper = 1'b0 ;
fsm_NEXT_STATE = s15 ;
end
else if (fsm_coin == 2'b01)
begin
fsm_newspaper = 1'b0;
fsm_NEXT_STATE = s10;
end
else
begin
fsm_newspaper = 1'b0 ;
fsm_NEXT_STATE = s5;
end
end
s10: //state = s10
begin
if (fsm_coin == 2'b10)
begin
fsm_newspaper = 1'b0 ;
fsm_NEXT_STATE =s15 ;
end
else if (fsm_coin == 2'b01 )
begin
fsm_newspaper = 1'b0;
fsm_NEXT_STATE = s15 ;
end
else
begin
fsm_newspaper = 1'b0 ;
fsm_NEXT_STATE = s10;
end
end
s15: //state = s 15
begin
fsm_newspaper = 1'b1 ;
fsm_NEXT_STATE = s0 ;
end
endcase
fsm= {fsm_newspaper, fsm_NEXT_STATE};
end
endfunction
//Reevaluate combinational logic each time a coin is put or the present state changes
assign {newspaper, NEXT_STATE}= fsm(coin, PRES_STATE);
//clock the state flip-flops.
//use synchronous reset
always @(posedge clock)
begin
if (reset == 1'b1)
PRES_STATE = s0 ;
else
PRES_STATE = NEXT_STATE;
end
endmodule
|
module test_bench;
reg clock;
reg [1:0] coin;
reg reset;
wire newspaper;
//instantiate the vending state machine
vend dut(coin, clock, reset, newspaper);
//Display the output
initial begin
$display("\t\tTime Reset Newspaper");
$monitor("\t\t %0d \t %0d \t %0d", $time, reset, newspaper);
end
//Apply stimulus to the vending machine
initial begin
clock = 0;
coin = 0 ;
reset = 1 ;
#50 reset = 0 ;
@(negedge clock); //wait until negative edge of clock
//Put 3 nickels to get newspaper
#80 coin = 1; #40 coin = 0;
#80 coin = 1; #40 coin = 0;
#80 coin = 1; #40 coin = 0 ;
//Put one nickel and then one dime to get newspaper
#180 coin = 1; #40 coin = 0;
#80 coin = 2; #40 coin = 0;
//Put two dimes; machine does not return a nickel to get newspaper
#180 coin = 2 ; #40 coin = 0 ;
#80 coin = 2; #40 coin = 0;
//Put one dime and then one nickel to get newspaper
#180 coin = 2; #40 coin = 0;
#80 coin = 1; #40 coin = 0;
end
initial #1500 $finish;
//setup clock; cycle time = 40 units
always #20 clock = ~clock;
endmodule
|
module sequence_counter(
input clk,
input reset,
output reg [3:0] counter
);
reg [3:0] count;
always @(posedge clk, posedge reset) begin
if (reset) begin
count <= 4'b0000;
counter <= 4'b0000;
end
else begin
case (count)
4'b0000: begin // 0
counter <= 4'b0000;
count <= 3'b010;
end
4'b0010: begin // 2
counter <= 4'b0010;
count <= 4'b0101;
end
4'b0101: begin // 5
counter <= 4'b0101;
count <= 4'b1000;
end
4'b1000: begin // 8
counter <= 4'b1000;
count <= 4'b1011;
end
4'b1011: begin // 11
counter <= 4'b1011;
count <= 4'b1110;
end
4'b1110: begin // 14
counter <= 4'b1110;
count <= 4'b0000;
end
default: count <= 4'b0000;
endcase
end
end
endmodule
|
module test_bench;
reg clk, reset;
wire [3:0] counter;
sequence_counter dut(clk, reset,counter);
initial
begin
clk = 0;
reset = 1;
# 10 reset = 0 ;
end
always #5 clk = ~clk;
initial begin
$monitor("\t\t clk: %b counter:%b", clk, counter);
#140 $finish;
end
endmodule
|
module test_bench;
reg a, b;
wire nand_out, nor_out;
gates_mux dut(a, b, nand_out, nor_out);
initial begin
#0 a= 1'b0; b= 1'b0;
#10 a= 1'b0; b= 1'b1;
#10 a= 1'b1; b= 1'b0;
#10 a= 1'b1; b= 1'b1;
end
initial
begin $monitor("a: %b b: %b nand: %b nor: %b ",a, b, nand_out, nor_out );
#40 $finish;
end
endmodule
|
module mux_2_1(
input [1:0] i,
input select,
output y_out
);
assign y_out= select ? i[1] : i[0];
endmodule
|
module gates_mux(
input a, b,
output nand_out, nor_out
);
wire bbar;
mux_2_1 mbbar({1'b0, 1'b1}, b, bbar);
mux_2_1 mnand({bbar, 1'b1}, a, nand_out);
mux_2_1 mnor({1'b0, bbar}, a, nor_out);
endmodule
|
module fsm_1011(
input clk,rst,din,
output reg y);
parameter S0=3'b000,
S1=3'b001,
S2=3'b010,
S3=3'b011,
S4=3'b100;
reg[2:0] cs, nst;
always @(posedge clk, posedge rst)
begin
if(rst)
cs<=S0;
else
cs<=nst;
end
always @(cs,din)
begin
case(cs)
S0: begin
if(din==1)
nst<=S1;
else
nst<=S0;
end
S1: begin
if(din==1)
nst<=S1;
else
nst<=S2;
end
S2: begin
if(din==1)
nst<=S3;
else
nst<=S0;
end
S3: begin
if(din==1)
nst<=S4;
else
nst<=S2;
end
S4: begin
if(din==1)
nst<=S1;
else
nst<=S2;
end
default: nst<=S0;
endcase
end
always @(cs)
begin
case(cs)
S0: y<=0;
S1: y<=0;
S2: y<=0;
S3: y<=0;
S4: y<=1;
default: y<=0;
endcase
end
endmodule
|
module test_bench;
reg din,clk,reset;
wire y;
fsm_1011 dut(clk,reset,din,y);
initial begin
clk= 1'b0;
forever #5 clk= ~clk;
end
initial begin
reset= 1'b1;
#10 reset= 1'b0;
#5 din= 1'b0;
#10 din= 1'b1;
#10 din= 1'b0;
#10 din= 1'b1;
#10 din= 1'b1;
#10 din= 1'b0;
#10 din= 1'b1;
#10 din= 1'b1;
#10 din= 1'b0;
#10 din= 1'b1;
#10 din= 1'b0;
#10 din= 1'b1;
#10 din= 1'b1;
#10 din= 1'b0;
end
initial begin
$monitor("\t\t clock: %d input: %d detect: %d",clk, din, y);
#160 $finish;
end
endmodule
|
module majority_input(
input [6:0] in,
output out
);
wire [2:0] test;
assign test[0] = (in[0] & in[1]) | (in[0] & in[2]) | (in[1] & in[2]);
assign test[1] = (in[3] & in[4]) | (in[3] & in[5]) | (in[4] & in[5]);
assign test[2] = in[6];
assign out = (test[0]) & (test[1]) | (test[0] & test[2]) | (test[1] & test[2]);
endmodule
|
module test_bench;
reg [6:0]in;
wire out;
majority_input dut(in, out);
initial begin
in=7'd99;
#10;
in=7'd28;
#10;
in=7'd119;
#10;
in=7'd101;
#10;
in=7'd32;
#10;
in=7'd48;
#10;
in=7'd75;
#10;
end
initial
begin $monitor("%b is a majority input of number %b ",out, in);
#70 $finish;
end
endmodule
|
module gates_mux(
input a,b,
output and_out,
output or_out,
output not_out
);
mux_2_1 mand({b, 1'b0}, a, and_out);
mux_2_1 mor({1'b1, b}, a, or_out);
mux_2_1 mnot({1'b0, 1'b1}, a, not_out);
endmodule
|
module ALU(
input [7:0] a,b,
input [3:0] sel,
output reg [15:0] result,
output reg e_bit
);
always@(*)
begin
case(sel)
4'b0000: begin {e_bit,result}<= a+b; $display("1-Addition operation"); end
4'b0001: begin {e_bit,result}<= a-b; $display("2-Subtraction operation"); end
4'b0010: begin result<= a*b; $display("3-Multiplication operation"); end
4'b0011: begin result<= a/b; $display("4-Division operation"); end
4'b0100: begin result<=a<<1; $display("5-Left Shift operation"); end
4'b0101: begin result<=a>>1; $display("6-Right Shift operation"); end
4'b0110: begin result<=a<<1; e_bit <=a[7];
result[0]<=e_bit; $display("7-Left Rotation operation"); end
4'b0111: begin result<=a>>1; e_bit <=a[0];
result[7]<=e_bit; $display("8-Right Rotation operation"); end
4'b1000 : begin result <= a&b; $display("9-AND operation"); end
4'b1001 : begin result <= a|b; $display("10-OR operation"); end
4'b1010 : begin result <= ~(a&b); $display("11-NAND operation"); end
4'b1011 : begin result <= ~(a|b); $display("12-NOR operation"); end
4'b1100 : begin result <= a ^ b; $display("13-XOR operation"); end
4'b1101 : begin result <= a ~^ b; $display("14-XNOR operation"); end
4'b1110 : begin result <= (a>b)? 1'b1:1'b0; $display("15-Equality operation"); end
4'b1111 : begin result <= ~a + 8'b00000001; $display("16-2's Compliment operation"); end
endcase
end
endmodule
|
module test_bench;
reg [7:0] a;
reg [7:0] b;
reg [3:0] sel;
wire [7:0] result;
wire e_bit;
ALU dut(a, b, sel, result, e_bit);
initial begin
a = 8'd15;
b = 8'd3;
sel = 0;
$display(" Inputs are: %b and %b \n", a,b);
end
always #20 sel=sel+1;
initial begin
$monitor("\t Result= %b \n", result);
#320 $finish;
end
endmodule
|
module fsm_11001(
input din,clk,reset,
output reg y
);
reg[2:0] cst, nst;
parameter S0=3'b000,
S1=3'b001,
S2=3'b010,
S3=3'b011,
S4=3'b100;
always@ (posedge clk)
begin
if(reset)
cst<=S0;
else
cst<=nst;
end
always @(cst or din)
begin
case(cst)
S0: if(din==1'b1)
begin
nst<=S1;
y<=1'b0;
end
else
begin
nst<=S0;
y<=1'b0;
end
S1: if(din==1'b1)
begin
nst<=S2;
y<=1'b0;
end
else
begin
nst<=S0;
y<=1'b0;
end
S2: if(din==1'b1)
begin
nst<=S2;
y<=1'b0;
end
else
begin
nst<=S3;
y<=1'b0;
end
S3: if(din==1'b1)
begin
nst<=S1;
y<=1'b0;
end
else
begin
nst=S4;
y=1'b0;
end
S4: if(din==1'b1)
begin
nst<=S1;
y<=1'b1;
end
else
begin
nst<=S0;
y<=1'b0;
end
default: nst<=S0;
endcase
end
endmodule
|
module binary2gray(
input [3:0] binary_in,
output [3:0] gray_out
);
buf buf1(gray_out[3], binary_in[3]);
xor xor1(gray_out[2], binary_in[3], binary_in[2]),
xor2(gray_out[1], binary_in[2], binary_in[1]),
xor3(gray_out[0], binary_in[1], binary_in[0]);
endmodule
|
module test_bench;
reg [3:0]binary_in;
wire [3:0] gray_out;
binary2gray dut(binary_in, gray_out);
initial begin
binary_in= 4'd0;
#10;
binary_in= 4'd1;
#10;
binary_in= 4'd2;
#10;
binary_in= 4'd3;
#10;
binary_in= 4'd4;
#10;
binary_in= 4'd5;
#10;
binary_in= 4'd6;
#10;
binary_in= 4'd7;
#10;
binary_in= 4'd8;
#10;
binary_in= 4'd9;
#10;
binary_in= 4'd10;
#10;
binary_in= 4'd11;
#10;
binary_in= 4'd12;
#10;
binary_in= 4'd13;
#10;
binary_in= 4'd14;
#10;
binary_in= 4'd15;
end
initial
begin $monitor("binary: %b -> gray: %b", binary_in, gray_out);
#160 $finish;
end
endmodule
|
module test_bench;
reg [7:0]data;
wire [3:0] bit0, bit1, bit2;
wire [11:0] BCD;
binary2bcd dut(data, bit0, bit1, bit2, BCD);
always
begin
data=$random;
#10;
end
initial
begin $monitor("data: %d BCD: %b",data,BCD);
#80 $finish;
end
endmodule
|
module binary2bcd(
input [7:0]data,
output reg [3:0] bit0,bit1,bit2,
output reg[11:0] BCD
);
integer n;
always@(data)
begin
bit0=0; bit1=0; bit2=0;
for(n=0; n<8; n=n+1)
begin
if(bit0>4) bit0 = bit0+3;
if(bit1>4) bit1 = bit1+3;
if(bit2>4) bit2 = bit2+3;
{bit2,bit1,bit0} = {bit2,bit1,bit0,data[7-n]};
end
BCD= {bit2, bit1, bit0};
end
endmodule
|
module test_bench;
reg [1:0] i;
reg select;
wire y_out;
mux_2_1 dut(i, select, y_out);
always begin
i=$random;
select=$random;
#10;
end
initial
begin $monitor("Input Data : %0d Select Line : %0d Output : %0d ",i, select, y_out);
#100 $finish;
end
endmodule
|
module rom(
input clk, r_en,
input [3:0] addr,
output reg [15:0] data);
reg [15:0] mem [15:0];
always@(posedge clk) begin
if(r_en)
data <= mem[addr];
else
data <= 'bz;
end
endmodule
|
module test_bench;
reg a, b;
wire xor_out, xnor_out;
gates_mux dut(a, b, xor_out, xnor_out);
initial begin
a= 1'b0; b= 1'b0;
#10 a= 1'b0; b= 1'b1;
#10 a= 1'b1; b= 1'b0;
#10 a= 1'b1; b= 1'b1;
end
initial
begin $monitor("a: %b b: %b xor: %b xnor: %b ",a, b, xor_out, xnor_out );
#40 $finish;
end
endmodule
|
module gates_mux(
input a,b,
output xor_out, xnor_out
);
wire bbar;
mux_2_1 mbbar({1'b0, 1'b1}, b, bbar);
mux_2_1 mxor({bbar, b}, a, xor_out);
mux_2_1 mxnor({b, bbar}, a, xnor_out);
endmodule
|
module test_bench;
parameter N = 6;
parameter LENGTH = 3;
reg clk,reset;
wire [LENGTH-1:0] counter;
mod_N_counter dut(clk, reset, counter);
initial
begin
clk = 0;
forever #5 clk = ~clk;
end
initial
begin
reset = 1;
#10;
reset = 0;
end
initial begin
$monitor("\t\t\t counter: %d",counter);
#125 $finish;
end
endmodule
|
module mod_N_counter
#(parameter N = 6,
parameter LENGTH = 3)
(input clk,reset, output reg [LENGTH-1:0] counter);
always@(posedge clk)
begin
if(reset)
counter <= 0;
else
if(counter == N-1)
counter <= 0;
else
counter <= counter + 1;
end
endmodule
|
module up_down_counter
# (parameter N = 4)
( input clk, reset, upordown, output reg[N-1:0] count);
always @ (posedge clk )
begin
if (reset==1)
count <= 0;
else if(upordown==1) //Up Mode is selected
if (count == 2*N -1)
count <= 0;
else
count<=count+1; //increment counter
else //Down Mode is selected
if(count==0)
count<= 2*N -1;
else
count<=count-1; //Decrement the counter
end
endmodule
|
module test_bench;
reg clk;
reg reset;
reg upordown;
wire [3:0] count;
up_down_counter uut (clk, reset, upordown, count);
initial begin
clk = 0;
reset = 1;
#50 reset =0;
upordown = 0;
#220;
upordown = 1;
#200;
upordown = 0;
#100;
reset = 0;
end
always #10 clk=~clk;
initial
begin
$monitor("\t\t UporDown=%b Count=%b",upordown,count);
#550 $finish;
end
endmodule
|
module dual_edge_trig_ff(
input clk, reset, d,
output q
);
reg q1, q2;
assign q = clk ? q1 : q2;
always@ (posedge clk)
begin
if(reset) q1<= 1'b0;
q1 <= d;
end
always@ (negedge clk)
begin
if(reset) q2<= 1'b0;
q2 <= d;
end
endmodule
|
module test_bench;
reg clk,rst,d;
wire Q;
dual_edge_trig_ff dut(clk,rst,d,Q);
initial begin
clk=0;
d=0;
forever #9 clk=~clk;
end
initial
begin
rst=1;
#10;
rst=0;
forever #6 d= ~d;
end
initial begin
$monitor("\t\t\t clk: %d D: %d Q: %d", clk, d, Q);
#80 $finish;
end
endmodule
|
module mux_4_1(
input [3:0] i,
input [1:0]select,
output y_out
);
wire [1:0]w;
mux_2_1 m1(i[1:0], select[0], w[0]);
mux_2_1 m2(i[3:2], select[0], w[1]);
mux_2_1 m3(w, select[1], y_out);
endmodule
|
module test_bench;
reg [3:0] i;
reg [1:0] select;
wire y_out;
mux_4_1 dut(i, select, y_out);
always begin
i=$random;
select=$random;
#10;
end
initial
begin $monitor("Input Data : %b Select Line : %b Output : %b ",i, select, y_out);
#100 $finish;
end
endmodule
|
module test_bench;
reg [31:0] number;
wire [31:0] sq_root, cube_root;
root dut(number, sq_root, cube_root);
initial begin
#10 number = 27;
#10 number = 121;
#10 number = 961;
#10 number = 512;
#10 number = 1764;
#10 number = 1000;
#10 number = 4761;
#10 number = 5832;
#10 $finish;
end
endmodule
|
module root(
input [31:0] number,
output reg [31:0] sq_root, cube_root
);
real red;
always@(number) begin
find_sq_root(number, sq_root);
find_cube_root(number, cube_root);
$display("\n \t\t Square Root of %0d is %0d", number, sq_root);
$display(" \t\t Cube Root of %0d is %0d ", number, cube_root);
end
task find_sq_root;
input [31:0] num;
output [31:0] res;
begin
res = num**(0.5);
end
endtask
task find_cube_root;
input [31:0] num;
output [31:0] res;
begin
res= num**(0.33);
end
endtask
endmodule
|
module test_bench;
reg clk, reset;
wire [3:0] state;
wire [1:0] out;
one_hot_fsm dut(clk, reset, state, out);
initial begin
clk = 0;
forever #10 clk = ~clk;
end
initial begin
reset = 1;
#20 reset = 0;
end
initial begin
$monitor("\t\t State: %b Output: %b", state, out);
#170 $finish;
end
endmodule
|
module one_hot_fsm (
input clk, reset,
output reg [3:0] state,
output reg [1:0]out);
parameter [3:0] IDLE = 4'b0001,
STATE1 = 4'b0010,
STATE2 = 4'b0100,
STATE3 = 4'b1000;
always @(posedge clk, posedge reset) begin
if (reset)
begin
state <= IDLE;
out<= 2'b00;
end
else
begin
case(state)
IDLE: begin
out<= 2'b00;
state <= STATE1;
end
STATE1: begin
out<= 2'b01;
state <= STATE2;
end
STATE2: begin
out<= 2'b10;
state <= STATE3;
end
STATE3: begin
out<= 2'b11;
state <= IDLE;
end
default: state <= IDLE;
endcase
end
end
endmodule
|
module test_bench;
reg clk, reset;
wire clk_by4;
freq_div_by4 dut(clk, reset, clk_by4);
initial begin
clk= 1'b0;
forever #10 clk= ~clk;
end
initial begin
reset= 1'b1;
#20
reset= 1'b0;
#220 $finish;
end
endmodule
|
module D_flipflop(
input clk, reset, d,
output reg Q
);
always@(posedge clk)
begin
if({reset})
Q<= 1'b0;
else
Q <= d;
end
endmodule
|
module freq_div_by4(
input clk, reset,
output clk_by4
);
wire clk_by2;
D_flipflop D1(clk, reset, ~clk_by4, clk_by2);
D_flipflop D2(clk, reset, clk_by2, clk_by4);
endmodule
|
module T_flipflop(
input t,clk,reset,
output reg Q
);
always@(posedge clk)
begin
if(reset)
Q <= 1'b0;
else
begin
if(t)
Q<= ~Q;
else
Q<= Q;
end
end
endmodule
|
module test_bench;
reg clk,rst,t;
wire q;
T_flipflop dut(t,clk,rst,q);
initial
begin
clk=0;
t=0;
forever #4 clk=~clk;
end
initial
begin
rst=1;
#10;
rst=0;
forever
begin
#10 t = 1'b1;
#20 t = 1'b0;
end
end
initial begin
$monitor("\t clock: %b T: %b Q: %b",clk,t,q);
#100$finish;
end
endmodule
|
module test_bench;
reg [3:0]dividend,divisor;
wire [3:0]quotient,remainder;
divide dut(dividend,divisor,quotient,remainder);
always begin
dividend =$random;
divisor =$random;
#10;
end
initial
begin $monitor("%0d / %0d = %0d with remainder %0d ",dividend,divisor,quotient,remainder);
#100 $finish;
end
endmodule
|
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