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module fifo_video (
data,
rdclk,
rdreq,
wrclk,
wrreq,
q,
rdempty,
rdfull,
rdusedw,
wrfull);
input [21:0] data;
input rdclk;
input rdreq;
input wrclk;
input wrreq;
output [21:0] q;
output rdempty;
output rdfull;
output [8:0] rdusedw;
output wrfull;
endmodule |
module spram (
address,
clock,
data,
wren,
q);
input [7:0] address;
input clock;
input [7:0] data;
input wren;
output [7:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
endmodule |
module PLL_Core (
input wire refclk, // refclk.clk
input wire rst, // reset.reset
output wire outclk_0, // outclk0.clk
output wire locked // locked.export
);
PLL_Core_0002 pll_core_inst (
.refclk (refclk), // refclk.clk
.rst (rst), // reset.reset
.outclk_0 (outclk_0), // outclk0.clk
.locked (locked) // locked.export
);
endmodule |
module BRAM_DUAL_PORT_CLOCK (
address_a,
address_b,
clock_a,
clock_b,
data_a,
data_b,
wren_a,
wren_b,
q_a,
q_b);
input [11:0] address_a;
input [11:0] address_b;
input clock_a;
input clock_b;
input [17:0] data_a;
input [17:0] data_b;
input wren_a;
input wren_b;
output [17:0] q_a;
output [17:0] q_b;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock_a;
tri0 wren_a;
tri0 wren_b;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [17:0] sub_wire0;
wire [17:0] sub_wire1;
wire [17:0] q_a = sub_wire0[17:0];
wire [17:0] q_b = sub_wire1[17:0];
altsyncram altsyncram_component (
.address_a (address_a),
.address_b (address_b),
.clock0 (clock_a),
.clock1 (clock_b),
.data_a (data_a),
.data_b (data_b),
.wren_a (wren_a),
.wren_b (wren_b),
.q_a (sub_wire0),
.q_b (sub_wire1),
.aclr0 (1'b0),
.aclr1 (1'b0),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.eccstatus (),
.rden_a (1'b1),
.rden_b (1'b1));
defparam
altsyncram_component.address_reg_b = "CLOCK1",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_input_b = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.clock_enable_output_b = "BYPASS",
altsyncram_component.indata_reg_b = "CLOCK1",
altsyncram_component.intended_device_family = "Cyclone V",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 4096,
altsyncram_component.numwords_b = 4096,
altsyncram_component.operation_mode = "BIDIR_DUAL_PORT",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_aclr_b = "NONE",
altsyncram_component.outdata_reg_a = "UNREGISTERED",
altsyncram_component.outdata_reg_b = "UNREGISTERED",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.read_during_write_mode_port_a = "NEW_DATA_NO_NBE_READ",
altsyncram_component.read_during_write_mode_port_b = "NEW_DATA_NO_NBE_READ",
altsyncram_component.widthad_a = 12,
altsyncram_component.widthad_b = 12,
altsyncram_component.width_a = 18,
altsyncram_component.width_b = 18,
altsyncram_component.width_byteena_a = 1,
altsyncram_component.width_byteena_b = 1,
altsyncram_component.wrcontrol_wraddress_reg_b = "CLOCK1";
endmodule |
module taperam (
data,
rdaddress,
rdclock,
wraddress,
wrclock,
wren,
q);
input [31:0] data;
input [11:0] rdaddress;
input rdclock;
input [11:0] wraddress;
input wrclock;
input wren;
output [31:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 wrclock;
tri0 wren;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [31:0] sub_wire0;
wire [31:0] q = sub_wire0[31:0];
altsyncram altsyncram_component (
.address_a (wraddress),
.address_b (rdaddress),
.clock0 (wrclock),
.clock1 (rdclock),
.data_a (data),
.wren_a (wren),
.q_b (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_b ({32{1'b1}}),
.eccstatus (),
.q_a (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_b (1'b0));
defparam
altsyncram_component.address_aclr_b = "NONE",
altsyncram_component.address_reg_b = "CLOCK1",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_input_b = "BYPASS",
altsyncram_component.clock_enable_output_b = "BYPASS",
altsyncram_component.intended_device_family = "Cyclone V",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 4096,
altsyncram_component.numwords_b = 4096,
altsyncram_component.operation_mode = "DUAL_PORT",
altsyncram_component.outdata_aclr_b = "NONE",
altsyncram_component.outdata_reg_b = "UNREGISTERED",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.widthad_a = 12,
altsyncram_component.widthad_b = 12,
altsyncram_component.width_a = 32,
altsyncram_component.width_b = 32,
altsyncram_component.width_byteena_a = 1;
endmodule |
module rendram (
address_a,
address_b,
clock,
data_a,
data_b,
wren_a,
wren_b,
q_a,
q_b);
input [9:0] address_a;
input [9:0] address_b;
input clock;
input [31:0] data_a;
input [31:0] data_b;
input wren_a;
input wren_b;
output [31:0] q_a;
output [31:0] q_b;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
tri0 wren_a;
tri0 wren_b;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [31:0] sub_wire0;
wire [31:0] sub_wire1;
wire [31:0] q_a = sub_wire0[31:0];
wire [31:0] q_b = sub_wire1[31:0];
altsyncram altsyncram_component (
.address_a (address_a),
.address_b (address_b),
.clock0 (clock),
.data_a (data_a),
.data_b (data_b),
.wren_a (wren_a),
.wren_b (wren_b),
.q_a (sub_wire0),
.q_b (sub_wire1),
.aclr0 (1'b0),
.aclr1 (1'b0),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.eccstatus (),
.rden_a (1'b1),
.rden_b (1'b1));
defparam
altsyncram_component.address_reg_b = "CLOCK0",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_input_b = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.clock_enable_output_b = "BYPASS",
altsyncram_component.indata_reg_b = "CLOCK0",
altsyncram_component.intended_device_family = "Cyclone V",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 1024,
altsyncram_component.numwords_b = 1024,
altsyncram_component.operation_mode = "BIDIR_DUAL_PORT",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_aclr_b = "NONE",
altsyncram_component.outdata_reg_a = "UNREGISTERED",
altsyncram_component.outdata_reg_b = "UNREGISTERED",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE",
altsyncram_component.read_during_write_mode_port_a = "NEW_DATA_NO_NBE_READ",
altsyncram_component.read_during_write_mode_port_b = "NEW_DATA_NO_NBE_READ",
altsyncram_component.widthad_a = 10,
altsyncram_component.widthad_b = 10,
altsyncram_component.width_a = 32,
altsyncram_component.width_b = 32,
altsyncram_component.width_byteena_a = 1,
altsyncram_component.width_byteena_b = 1,
altsyncram_component.wrcontrol_wraddress_reg_b = "CLOCK0";
endmodule |
module data_fifo (
aclr,
data,
rdclk,
rdreq,
wrclk,
wrreq,
q,
rdempty,
wrfull);
input aclr;
input [31:0] data;
input rdclk;
input rdreq;
input wrclk;
input wrreq;
output [7:0] q;
output rdempty;
output wrfull;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [7:0] sub_wire0;
wire sub_wire1;
wire sub_wire2;
wire [7:0] q = sub_wire0[7:0];
wire rdempty = sub_wire1;
wire wrfull = sub_wire2;
dcfifo_mixed_widths dcfifo_mixed_widths_component (
.aclr (aclr),
.data (data),
.rdclk (rdclk),
.rdreq (rdreq),
.wrclk (wrclk),
.wrreq (wrreq),
.q (sub_wire0),
.rdempty (sub_wire1),
.wrfull (sub_wire2),
.eccstatus (),
.rdfull (),
.rdusedw (),
.wrempty (),
.wrusedw ());
defparam
dcfifo_mixed_widths_component.intended_device_family = "Cyclone V",
dcfifo_mixed_widths_component.lpm_numwords = 8192,
dcfifo_mixed_widths_component.lpm_showahead = "ON",
dcfifo_mixed_widths_component.lpm_type = "dcfifo_mixed_widths",
dcfifo_mixed_widths_component.lpm_width = 32,
dcfifo_mixed_widths_component.lpm_widthu = 13,
dcfifo_mixed_widths_component.lpm_widthu_r = 15,
dcfifo_mixed_widths_component.lpm_width_r = 8,
dcfifo_mixed_widths_component.overflow_checking = "ON",
dcfifo_mixed_widths_component.rdsync_delaypipe = 5,
dcfifo_mixed_widths_component.read_aclr_synch = "OFF",
dcfifo_mixed_widths_component.underflow_checking = "ON",
dcfifo_mixed_widths_component.use_eab = "ON",
dcfifo_mixed_widths_component.write_aclr_synch = "OFF",
dcfifo_mixed_widths_component.wrsync_delaypipe = 5;
endmodule |
module PLL_Core_0002(
// interface 'refclk'
input wire refclk,
// interface 'reset'
input wire rst,
// interface 'outclk0'
output wire outclk_0,
// interface 'locked'
output wire locked
);
altera_pll #(
.fractional_vco_multiplier("true"),
.reference_clock_frequency("74.0 MHz"),
.operation_mode("direct"),
.number_of_clocks(1),
.output_clock_frequency0("50.000000 MHz"),
.phase_shift0("0 ps"),
.duty_cycle0(50),
.output_clock_frequency1("0 MHz"),
.phase_shift1("0 ps"),
.duty_cycle1(50),
.output_clock_frequency2("0 MHz"),
.phase_shift2("0 ps"),
.duty_cycle2(50),
.output_clock_frequency3("0 MHz"),
.phase_shift3("0 ps"),
.duty_cycle3(50),
.output_clock_frequency4("0 MHz"),
.phase_shift4("0 ps"),
.duty_cycle4(50),
.output_clock_frequency5("0 MHz"),
.phase_shift5("0 ps"),
.duty_cycle5(50),
.output_clock_frequency6("0 MHz"),
.phase_shift6("0 ps"),
.duty_cycle6(50),
.output_clock_frequency7("0 MHz"),
.phase_shift7("0 ps"),
.duty_cycle7(50),
.output_clock_frequency8("0 MHz"),
.phase_shift8("0 ps"),
.duty_cycle8(50),
.output_clock_frequency9("0 MHz"),
.phase_shift9("0 ps"),
.duty_cycle9(50),
.output_clock_frequency10("0 MHz"),
.phase_shift10("0 ps"),
.duty_cycle10(50),
.output_clock_frequency11("0 MHz"),
.phase_shift11("0 ps"),
.duty_cycle11(50),
.output_clock_frequency12("0 MHz"),
.phase_shift12("0 ps"),
.duty_cycle12(50),
.output_clock_frequency13("0 MHz"),
.phase_shift13("0 ps"),
.duty_cycle13(50),
.output_clock_frequency14("0 MHz"),
.phase_shift14("0 ps"),
.duty_cycle14(50),
.output_clock_frequency15("0 MHz"),
.phase_shift15("0 ps"),
.duty_cycle15(50),
.output_clock_frequency16("0 MHz"),
.phase_shift16("0 ps"),
.duty_cycle16(50),
.output_clock_frequency17("0 MHz"),
.phase_shift17("0 ps"),
.duty_cycle17(50),
.pll_type("General"),
.pll_subtype("General")
) altera_pll_i (
.rst (rst),
.outclk ({outclk_0}),
.locked (locked),
.fboutclk ( ),
.fbclk (1'b0),
.refclk (refclk)
);
endmodule |
module Multipler_0002 (
clock0,
dataa_0,
datab_0,
result);
input clock0;
input [9:0] dataa_0;
input [9:0] datab_0;
output [20:0] result;
wire [20:0] sub_wire0;
wire [20:0] result = sub_wire0[20:0];
wire [9:0] wire_dataa;
assign wire_dataa[9:0] = dataa_0;
wire [9:0] wire_datab;
assign wire_datab[9:0] = datab_0;
altera_mult_add altera_mult_add_component (
.clock0 (clock0),
.dataa (wire_dataa),
.datab (wire_datab),
.result (sub_wire0),
.accum_sload (1'b0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.aclr2 (1'b0),
.aclr3 (1'b0),
.addnsub1 (1'b1),
.addnsub1_round (1'b0),
.addnsub3 (1'b1),
.addnsub3_round (1'b0),
.chainin (1'b0),
.chainout_round (1'b0),
.chainout_sat_overflow (),
.chainout_saturate (1'b0),
.clock1 (1'b1),
.clock2 (1'b1),
.clock3 (1'b1),
.coefsel0 ({3{1'b0}}),
.coefsel1 ({3{1'b0}}),
.coefsel2 ({3{1'b0}}),
.coefsel3 ({3{1'b0}}),
.datac ({16{1'b0}}),
.ena0 (1'b1),
.ena1 (1'b1),
.ena2 (1'b1),
.ena3 (1'b1),
.mult01_round (1'b0),
.mult01_saturation (1'b0),
.mult0_is_saturated (),
.mult1_is_saturated (),
.mult23_round (1'b0),
.mult23_saturation (1'b0),
.mult2_is_saturated (),
.mult3_is_saturated (),
.negate (1'b0),
.output_round (1'b0),
.output_saturate (1'b0),
.overflow (),
.rotate (1'b0),
.scanina ({10{1'b0}}),
.scaninb ({10{1'b0}}),
.scanouta (),
.scanoutb (),
.sclr0 (1'b0),
.sclr1 (1'b0),
.sclr2 (1'b0),
.sclr3 (1'b0),
.shift_right (1'b0),
.signa (1'b0),
.signb (1'b0),
.sload_accum (1'b0),
.sourcea ({1{1'b0}}),
.sourceb ({1{1'b0}}),
.zero_chainout (1'b0),
.zero_loopback (1'b0));
defparam
altera_mult_add_component.number_of_multipliers = 1,
altera_mult_add_component.width_a = 10,
altera_mult_add_component.width_b = 10,
altera_mult_add_component.width_result = 21,
altera_mult_add_component.output_register = "UNREGISTERED",
altera_mult_add_component.output_aclr = "NONE",
altera_mult_add_component.output_sclr = "NONE",
altera_mult_add_component.multiplier1_direction = "ADD",
altera_mult_add_component.port_addnsub1 = "PORT_UNUSED",
altera_mult_add_component.addnsub_multiplier_register1 = "UNREGISTERED",
altera_mult_add_component.addnsub_multiplier_aclr1 = "NONE",
altera_mult_add_component.addnsub_multiplier_sclr1 = "NONE",
altera_mult_add_component.multiplier3_direction = "ADD",
altera_mult_add_component.port_addnsub3 = "PORT_UNUSED",
altera_mult_add_component.addnsub_multiplier_register3 = "UNREGISTERED",
altera_mult_add_component.addnsub_multiplier_aclr3 = "NONE",
altera_mult_add_component.addnsub_multiplier_sclr3 = "NONE",
altera_mult_add_component.use_subnadd = "NO",
altera_mult_add_component.representation_a = "UNSIGNED",
altera_mult_add_component.port_signa = "PORT_UNUSED",
altera_mult_add_component.signed_register_a = "UNREGISTERED",
altera_mult_add_component.signed_aclr_a = "NONE",
altera_mult_add_component.signed_sclr_a = "NONE",
altera_mult_add_component.port_signb = "PORT_UNUSED",
altera_mult_add_component.representation_b = "UNSIGNED",
altera_mult_add_component.signed_register_b = "UNREGISTERED",
altera_mult_add_component.signed_aclr_b = "NONE",
altera_mult_add_component.signed_sclr_b = "NONE",
altera_mult_add_component.input_register_a0 = "UNREGISTERED",
altera_mult_add_component.input_register_a1 = "UNREGISTERED",
altera_mult_add_component.input_register_a2 = "UNREGISTERED",
altera_mult_add_component.input_register_a3 = "UNREGISTERED",
altera_mult_add_component.input_aclr_a0 = "NONE",
altera_mult_add_component.input_aclr_a1 = "NONE",
altera_mult_add_component.input_aclr_a2 = "NONE",
altera_mult_add_component.input_aclr_a3 = "NONE",
altera_mult_add_component.input_sclr_a0 = "NONE",
altera_mult_add_component.input_sclr_a1 = "NONE",
altera_mult_add_component.input_sclr_a2 = "NONE",
altera_mult_add_component.input_sclr_a3 = "NONE",
altera_mult_add_component.input_register_b0 = "UNREGISTERED",
altera_mult_add_component.input_register_b1 = "UNREGISTERED",
altera_mult_add_component.input_register_b2 = "UNREGISTERED",
altera_mult_add_component.input_register_b3 = "UNREGISTERED",
altera_mult_add_component.input_aclr_b0 = "NONE",
altera_mult_add_component.input_aclr_b1 = "NONE",
altera_mult_add_component.input_aclr_b2 = "NONE",
altera_mult_add_component.input_aclr_b3 = "NONE",
altera_mult_add_component.input_sclr_b0 = "NONE",
altera_mult_add_component.input_sclr_b1 = "NONE",
altera_mult_add_component.input_sclr_b2 = "NONE",
altera_mult_add_component.input_sclr_b3 = "NONE",
altera_mult_add_component.scanouta_register = "UNREGISTERED",
altera_mult_add_component.scanouta_aclr = "NONE",
altera_mult_add_component.scanouta_sclr = "NONE",
altera_mult_add_component.input_source_a0 = "DATAA",
altera_mult_add_component.input_source_a1 = "DATAA",
altera_mult_add_component.input_source_a2 = "DATAA",
altera_mult_add_component.input_source_a3 = "DATAA",
altera_mult_add_component.input_source_b0 = "DATAB",
altera_mult_add_component.input_source_b1 = "DATAB",
altera_mult_add_component.input_source_b2 = "DATAB",
altera_mult_add_component.input_source_b3 = "DATAB",
altera_mult_add_component.multiplier_register0 = "UNREGISTERED",
altera_mult_add_component.multiplier_register1 = "UNREGISTERED",
altera_mult_add_component.multiplier_register2 = "UNREGISTERED",
altera_mult_add_component.multiplier_register3 = "UNREGISTERED",
altera_mult_add_component.multiplier_aclr0 = "NONE",
altera_mult_add_component.multiplier_aclr1 = "NONE",
altera_mult_add_component.multiplier_aclr2 = "NONE",
altera_mult_add_component.multiplier_aclr3 = "NONE",
altera_mult_add_component.multiplier_sclr0 = "NONE",
altera_mult_add_component.multiplier_sclr1 = "NONE",
altera_mult_add_component.multiplier_sclr2 = "NONE",
altera_mult_add_component.multiplier_sclr3 = "NONE",
altera_mult_add_component.preadder_mode = "SIMPLE",
altera_mult_add_component.preadder_direction_0 = "ADD",
altera_mult_add_component.preadder_direction_1 = "ADD",
altera_mult_add_component.preadder_direction_2 = "ADD",
altera_mult_add_component.preadder_direction_3 = "ADD",
altera_mult_add_component.width_c = 16,
altera_mult_add_component.input_register_c0 = "UNREGISTERED",
altera_mult_add_component.input_register_c1 = "UNREGISTERED",
altera_mult_add_component.input_register_c2 = "UNREGISTERED",
altera_mult_add_component.input_register_c3 = "UNREGISTERED",
altera_mult_add_component.input_aclr_c0 = "NONE",
altera_mult_add_component.input_aclr_c1 = "NONE",
altera_mult_add_component.input_aclr_c2 = "NONE",
altera_mult_add_component.input_aclr_c3 = "NONE",
altera_mult_add_component.input_sclr_c0 = "NONE",
altera_mult_add_component.input_sclr_c1 = "NONE",
altera_mult_add_component.input_sclr_c2 = "NONE",
altera_mult_add_component.input_sclr_c3 = "NONE",
altera_mult_add_component.width_coef = 18,
altera_mult_add_component.coefsel0_register = "UNREGISTERED",
altera_mult_add_component.coefsel1_register = "UNREGISTERED",
altera_mult_add_component.coefsel2_register = "UNREGISTERED",
altera_mult_add_component.coefsel3_register = "UNREGISTERED",
altera_mult_add_component.coefsel0_aclr = "NONE",
altera_mult_add_component.coefsel1_aclr = "NONE",
altera_mult_add_component.coefsel2_aclr = "NONE",
altera_mult_add_component.coefsel3_aclr = "NONE",
altera_mult_add_component.coefsel0_sclr = "NONE",
altera_mult_add_component.coefsel1_sclr = "NONE",
altera_mult_add_component.coefsel2_sclr = "NONE",
altera_mult_add_component.coefsel3_sclr = "NONE",
altera_mult_add_component.coef0_0 = 0,
altera_mult_add_component.coef0_1 = 0,
altera_mult_add_component.coef0_2 = 0,
altera_mult_add_component.coef0_3 = 0,
altera_mult_add_component.coef0_4 = 0,
altera_mult_add_component.coef0_5 = 0,
altera_mult_add_component.coef0_6 = 0,
altera_mult_add_component.coef0_7 = 0,
altera_mult_add_component.coef1_0 = 0,
altera_mult_add_component.coef1_1 = 0,
altera_mult_add_component.coef1_2 = 0,
altera_mult_add_component.coef1_3 = 0,
altera_mult_add_component.coef1_4 = 0,
altera_mult_add_component.coef1_5 = 0,
altera_mult_add_component.coef1_6 = 0,
altera_mult_add_component.coef1_7 = 0,
altera_mult_add_component.coef2_0 = 0,
altera_mult_add_component.coef2_1 = 0,
altera_mult_add_component.coef2_2 = 0,
altera_mult_add_component.coef2_3 = 0,
altera_mult_add_component.coef2_4 = 0,
altera_mult_add_component.coef2_5 = 0,
altera_mult_add_component.coef2_6 = 0,
altera_mult_add_component.coef2_7 = 0,
altera_mult_add_component.coef3_0 = 0,
altera_mult_add_component.coef3_1 = 0,
altera_mult_add_component.coef3_2 = 0,
altera_mult_add_component.coef3_3 = 0,
altera_mult_add_component.coef3_4 = 0,
altera_mult_add_component.coef3_5 = 0,
altera_mult_add_component.coef3_6 = 0,
altera_mult_add_component.coef3_7 = 0,
altera_mult_add_component.accumulator = "NO",
altera_mult_add_component.accum_direction = "ADD",
altera_mult_add_component.use_sload_accum_port = "NO",
altera_mult_add_component.loadconst_value = 64,
altera_mult_add_component.accum_sload_register = "UNREGISTERED",
altera_mult_add_component.accum_sload_aclr = "NONE",
altera_mult_add_component.accum_sload_sclr = "NONE",
altera_mult_add_component.double_accum = "NO",
altera_mult_add_component.width_chainin = 1,
altera_mult_add_component.chainout_adder = "NO",
altera_mult_add_component.chainout_adder_direction = "ADD",
altera_mult_add_component.port_negate = "PORT_UNUSED",
altera_mult_add_component.negate_register = "UNREGISTERED",
altera_mult_add_component.negate_aclr = "NONE",
altera_mult_add_component.negate_sclr = "NONE",
altera_mult_add_component.systolic_delay1 = "UNREGISTERED",
altera_mult_add_component.systolic_aclr1 = "NONE",
altera_mult_add_component.systolic_sclr1 = "NONE",
altera_mult_add_component.systolic_delay3 = "UNREGISTERED",
altera_mult_add_component.systolic_aclr3 = "NONE",
altera_mult_add_component.systolic_sclr3 = "NONE",
altera_mult_add_component.latency = 3,
altera_mult_add_component.input_a0_latency_clock = "CLOCK0",
altera_mult_add_component.input_a1_latency_clock = "UNREGISTERED",
altera_mult_add_component.input_a2_latency_clock = "UNREGISTERED",
altera_mult_add_component.input_a3_latency_clock = "UNREGISTERED",
altera_mult_add_component.input_a0_latency_aclr = "NONE",
altera_mult_add_component.input_a1_latency_aclr = "NONE",
altera_mult_add_component.input_a2_latency_aclr = "NONE",
altera_mult_add_component.input_a3_latency_aclr = "NONE",
altera_mult_add_component.input_a0_latency_sclr = "NONE",
altera_mult_add_component.input_a1_latency_sclr = "NONE",
altera_mult_add_component.input_a2_latency_sclr = "NONE",
altera_mult_add_component.input_a3_latency_sclr = "NONE",
altera_mult_add_component.input_b0_latency_clock = "CLOCK0",
altera_mult_add_component.input_b1_latency_clock = "UNREGISTERED",
altera_mult_add_component.input_b2_latency_clock = "UNREGISTERED",
altera_mult_add_component.input_b3_latency_clock = "UNREGISTERED",
altera_mult_add_component.input_b0_latency_aclr = "NONE",
altera_mult_add_component.input_b1_latency_aclr = "NONE",
altera_mult_add_component.input_b2_latency_aclr = "NONE",
altera_mult_add_component.input_b3_latency_aclr = "NONE",
altera_mult_add_component.input_b0_latency_sclr = "NONE",
altera_mult_add_component.input_b1_latency_sclr = "NONE",
altera_mult_add_component.input_b2_latency_sclr = "NONE",
altera_mult_add_component.input_b3_latency_sclr = "NONE",
altera_mult_add_component.input_c0_latency_clock = "UNREGISTERED",
altera_mult_add_component.input_c1_latency_clock = "UNREGISTERED",
altera_mult_add_component.input_c2_latency_clock = "UNREGISTERED",
altera_mult_add_component.input_c3_latency_clock = "UNREGISTERED",
altera_mult_add_component.input_c0_latency_aclr = "NONE",
altera_mult_add_component.input_c1_latency_aclr = "NONE",
altera_mult_add_component.input_c2_latency_aclr = "NONE",
altera_mult_add_component.input_c3_latency_aclr = "NONE",
altera_mult_add_component.input_c0_latency_sclr = "NONE",
altera_mult_add_component.input_c1_latency_sclr = "NONE",
altera_mult_add_component.input_c2_latency_sclr = "NONE",
altera_mult_add_component.input_c3_latency_sclr = "NONE",
altera_mult_add_component.coefsel0_latency_clock = "UNREGISTERED",
altera_mult_add_component.coefsel1_latency_clock = "UNREGISTERED",
altera_mult_add_component.coefsel2_latency_clock = "UNREGISTERED",
altera_mult_add_component.coefsel3_latency_clock = "UNREGISTERED",
altera_mult_add_component.coefsel0_latency_aclr = "NONE",
altera_mult_add_component.coefsel1_latency_aclr = "NONE",
altera_mult_add_component.coefsel2_latency_aclr = "NONE",
altera_mult_add_component.coefsel3_latency_aclr = "NONE",
altera_mult_add_component.coefsel0_latency_sclr = "NONE",
altera_mult_add_component.coefsel1_latency_sclr = "NONE",
altera_mult_add_component.coefsel2_latency_sclr = "NONE",
altera_mult_add_component.coefsel3_latency_sclr = "NONE",
altera_mult_add_component.signed_latency_clock_a = "UNREGISTERED",
altera_mult_add_component.signed_latency_aclr_a = "NONE",
altera_mult_add_component.signed_latency_sclr_a = "NONE",
altera_mult_add_component.signed_latency_clock_b = "UNREGISTERED",
altera_mult_add_component.signed_latency_aclr_b = "NONE",
altera_mult_add_component.signed_latency_sclr_b = "NONE",
altera_mult_add_component.addnsub_multiplier_latency_clock1 = "UNREGISTERED",
altera_mult_add_component.addnsub_multiplier_latency_aclr1 = "NONE",
altera_mult_add_component.addnsub_multiplier_latency_sclr1 = "NONE",
altera_mult_add_component.addnsub_multiplier_latency_clock3 = "UNREGISTERED",
altera_mult_add_component.addnsub_multiplier_latency_aclr3 = "NONE",
altera_mult_add_component.addnsub_multiplier_latency_sclr3 = "NONE",
altera_mult_add_component.accum_sload_latency_clock = "UNREGISTERED",
altera_mult_add_component.accum_sload_latency_aclr = "NONE",
altera_mult_add_component.accum_sload_latency_sclr = "NONE",
altera_mult_add_component.negate_latency_clock = "UNREGISTERED",
altera_mult_add_component.negate_latency_aclr = "NONE",
altera_mult_add_component.negate_latency_sclr = "NONE",
altera_mult_add_component.selected_device_family = "Cyclone V";
endmodule |
module apf_top (
///////////////////////////////////////////////////
// clock inputs 74.25mhz. not phase aligned, so treat these domains as asynchronous
input wire clk_74a, // mainclk1
input wire clk_74b, // mainclk1
///////////////////////////////////////////////////
// cartridge interface
// switches between 3.3v and 5v mechanically
// output enable for multibit translators controlled by PIC32
// GBA AD[15:8]
inout wire [7:0] cart_tran_bank2,
output wire cart_tran_bank2_dir,
// GBA AD[7:0]
inout wire [7:0] cart_tran_bank3,
output wire cart_tran_bank3_dir,
// GBA A[23:16]
inout wire [7:0] cart_tran_bank1,
output wire cart_tran_bank1_dir,
// GBA [7] PHI#
// GBA [6] WR#
// GBA [5] RD#
// GBA [4] CS1#/CS#
// [3:0] unwired
inout wire [7:4] cart_tran_bank0,
output wire cart_tran_bank0_dir,
// GBA CS2#/RES#
inout wire cart_tran_pin30,
output wire cart_tran_pin30_dir,
// when GBC cart is inserted, RES# must stay low and glitch-free to prevent possible loss of SRAM data.
// a special circuit pulls this pin low when the cart switch indicates a GB/GBC type is inserted.
// the goal is that when unconfigured, the FPGA weak pullups won't interfere.
// thus, if a GBC cart is inserted, FPGA must drive this high in order to let the level translators
// and general IO drive this pin.
// when GBA cart is inserted, this circuit is bypassed.
output wire cart_pin30_pwroff_reset,
// GBA IRQ/DRQ
inout wire cart_tran_pin31,
output wire cart_tran_pin31_dir,
// infrared
// avoid driving the TX LED with DC or leaving it stuck on. pulsed usage is fine
input wire port_ir_rx,
output wire port_ir_tx,
output wire port_ir_rx_disable,
// GBA link port
inout wire port_tran_si,
output wire port_tran_si_dir,
inout wire port_tran_so,
output wire port_tran_so_dir,
inout wire port_tran_sck,
output wire port_tran_sck_dir,
inout wire port_tran_sd,
output wire port_tran_sd_dir,
///////////////////////////////////////////////////
// video output to the scaler
inout wire [11:0] scal_vid,
inout wire scal_clk,
inout wire scal_de,
inout wire scal_skip,
inout wire scal_vs,
inout wire scal_hs,
output wire scal_audmclk,
input wire scal_audadc,
output wire scal_auddac,
output wire scal_audlrck,
///////////////////////////////////////////////////
// communication between main and scaler (aristotle) fpga.
// spi bus with aristotle as master.
inout wire bridge_spimosi,
inout wire bridge_spimiso,
inout wire bridge_spiclk,
input wire bridge_spiss,
inout wire bridge_1wire,
///////////////////////////////////////////////////
// cellular psram 0 and 1, two chips (64mbit x2 dual die per chip)
output wire [21:16] cram0_a,
inout wire [15:0] cram0_dq,
input wire cram0_wait,
output wire cram0_clk,
output wire cram0_adv_n,
output wire cram0_cre,
output wire cram0_ce0_n,
output wire cram0_ce1_n,
output wire cram0_oe_n,
output wire cram0_we_n,
output wire cram0_ub_n,
output wire cram0_lb_n,
output wire [21:16] cram1_a,
inout wire [15:0] cram1_dq,
input wire cram1_wait,
output wire cram1_clk,
output wire cram1_adv_n,
output wire cram1_cre,
output wire cram1_ce0_n,
output wire cram1_ce1_n,
output wire cram1_oe_n,
output wire cram1_we_n,
output wire cram1_ub_n,
output wire cram1_lb_n,
///////////////////////////////////////////////////
// sdram, 512mbit x16
output wire [12:0] dram_a,
output wire [1:0] dram_ba,
inout wire [15:0] dram_dq,
output wire [1:0] dram_dqm,
output wire dram_clk,
output wire dram_cke,
output wire dram_ras_n,
output wire dram_cas_n,
output wire dram_we_n,
///////////////////////////////////////////////////
// sram, 1mbit x16
output wire [16:0] sram_a,
inout wire [15:0] sram_dq,
output wire sram_oe_n,
output wire sram_we_n,
output wire sram_ub_n,
output wire sram_lb_n,
///////////////////////////////////////////////////
// vblank output to scaler
input wire vblank,
///////////////////////////////////////////////////
// i/o to 6515D breakout usb uart
output wire dbg_tx,
input wire dbg_rx,
///////////////////////////////////////////////////
// i/o pads near jtag connector user can solder to
output wire user1,
input wire user2,
///////////////////////////////////////////////////
// powerup self test, do not use
inout wire bist,
output wire vpll_feed,
///////////////////////////////////////////////////
// RFU internal i2c bus (DNU)
inout wire aux_sda,
output wire aux_scl
);
assign bist = 1'bZ;
// reset generation
reg [24:0] count;
reg reset_n;
initial begin
count <= 0;
reset_n <= 0;
end
always @(posedge clk_74a) begin
count <= count + 1'b1;
if(count[15]) begin
// exit reset
reset_n <= 1;
end
end
i2s_audio i2s_audio (
.clk_74a (clk_74a),
.left_audio (16'b0),
.right_audio (16'b0),
.audio_mclk (scal_audmclk),
.audio_dac (scal_auddac),
.audio_lrck (scal_audlrck)
);
// convert 24-bit rgb data to 12-bit DDR for ARISTOTLE
wire [23:0] video_rgb;
wire video_rgb_clock;
wire video_rgb_clock_90;
wire video_de;
wire video_skip;
wire video_vs;
wire video_hs;
mf_ddio_bidir_12 isco (
.oe ( 1'b1 ),
.datain_h ( video_rgb[23:12] ),
.datain_l ( video_rgb[11: 0] ),
.outclock ( video_rgb_clock ),
.padio ( scal_ddio_12 )
);
wire [11:0] scal_ddio_12;
assign scal_vid = scal_ddio_12;
mf_ddio_bidir_12 iscc (
.oe ( 1'b1 ),
.datain_h ( {video_vs, video_hs, video_de, video_skip} ),
.datain_l ( {video_vs, video_hs, video_de, video_skip} ),
.outclock ( video_rgb_clock ),
.padio ( scal_ddio_ctrl )
);
wire [3:0] scal_ddio_ctrl;
assign scal_vs = scal_ddio_ctrl[3];
assign scal_hs = scal_ddio_ctrl[2];
assign scal_de = scal_ddio_ctrl[1];
assign scal_skip = scal_ddio_ctrl[0];
mf_ddio_bidir_12 isclk(
.oe ( 1'b1 ),
.datain_h ( 1'b1 ),
.datain_l ( 1'b0 ),
.outclock ( video_rgb_clock_90 ),
.padio ( scal_clk )
);
// controller data (pad) master
wire [15:0] cont1_key;
wire [15:0] cont2_key;
wire [15:0] cont3_key;
wire [15:0] cont4_key;
wire [31:0] cont1_joy;
wire [31:0] cont2_joy;
wire [31:0] cont3_joy;
wire [31:0] cont4_joy;
wire [15:0] cont1_trig;
wire [15:0] cont2_trig;
wire [15:0] cont3_trig;
wire [15:0] cont4_trig;
wire [15:0] buttons_legacy;
wire scaler_slot_strobe;
wire [2:0] scaler_slot;
io_pad_controller ipm (
.clk ( clk_74a ),
.reset_n ( reset_n ),
.pad_1wire ( bridge_1wire ),
.cont1_key ( cont1_key ),
.cont2_key ( cont2_key ),
.cont3_key ( cont3_key ),
.cont4_key ( cont4_key ),
.cont1_joy ( cont1_joy ),
.cont2_joy ( cont2_joy ),
.cont3_joy ( cont3_joy ),
.cont4_joy ( cont4_joy ),
.cont1_trig ( cont1_trig ),
.cont2_trig ( cont2_trig ),
.cont3_trig ( cont3_trig ),
.cont4_trig ( cont4_trig )
);
// virtual pmp bridge
wire bridge_endian_little;
wire [31:0] bridge_addr;
wire bridge_rd;
wire [31:0] bridge_rd_data;
wire bridge_wr;
wire [31:0] bridge_wr_data;
io_bridge_peripheral ibs (
.clk ( clk_74a ),
.reset_n ( reset_n ),
.endian_little ( bridge_endian_little ),
.pmp_addr ( bridge_addr ),
.pmp_rd ( bridge_rd ),
.pmp_rd_data ( bridge_rd_data ),
.pmp_wr ( bridge_wr ),
.pmp_wr_data ( bridge_wr_data ),
.phy_spimosi ( bridge_spimosi ),
.phy_spimiso ( bridge_spimiso ),
.phy_spiclk ( bridge_spiclk ),
.phy_spiss ( bridge_spiss )
);
///////////////////////////////////////////////////
// instantiate the user core top-level
core_top ic (
// physical connections
//
.clk_74a ( clk_74a ),
.clk_74b ( clk_74b ),
.reset_internal_n ( reset_n ),
.cart_tran_bank2 ( cart_tran_bank2 ),
.cart_tran_bank2_dir ( cart_tran_bank2_dir ),
.cart_tran_bank3 ( cart_tran_bank3 ),
.cart_tran_bank3_dir ( cart_tran_bank3_dir ),
.cart_tran_bank1 ( cart_tran_bank1 ),
.cart_tran_bank1_dir ( cart_tran_bank1_dir ),
.cart_tran_bank0 ( cart_tran_bank0 ),
.cart_tran_bank0_dir ( cart_tran_bank0_dir ),
.cart_tran_pin30 ( cart_tran_pin30 ),
.cart_tran_pin30_dir ( cart_tran_pin30_dir ),
.cart_pin30_pwroff_reset ( cart_pin30_pwroff_reset ),
.cart_tran_pin31 ( cart_tran_pin31 ),
.cart_tran_pin31_dir ( cart_tran_pin31_dir ),
.port_ir_rx ( port_ir_rx ),
.port_ir_tx ( port_ir_tx ),
.port_ir_rx_disable ( port_ir_rx_disable ),
.port_tran_si ( port_tran_si ),
.port_tran_si_dir ( port_tran_si_dir ),
.port_tran_so ( port_tran_so ),
.port_tran_so_dir ( port_tran_so_dir ),
.port_tran_sck ( port_tran_sck ),
.port_tran_sck_dir ( port_tran_sck_dir ),
.port_tran_sd ( port_tran_sd ),
.port_tran_sd_dir ( port_tran_sd_dir ),
.cram0_a ( cram0_a ),
.cram0_dq ( cram0_dq ),
.cram0_wait ( cram0_wait ),
.cram0_clk ( cram0_clk ),
.cram0_adv_n ( cram0_adv_n ),
.cram0_cre ( cram0_cre ),
.cram0_ce0_n ( cram0_ce0_n ),
.cram0_ce1_n ( cram0_ce1_n ),
.cram0_oe_n ( cram0_oe_n ),
.cram0_we_n ( cram0_we_n ),
.cram0_ub_n ( cram0_ub_n ),
.cram0_lb_n ( cram0_lb_n ),
.cram1_a ( cram1_a ),
.cram1_dq ( cram1_dq ),
.cram1_wait ( cram1_wait ),
.cram1_clk ( cram1_clk ),
.cram1_adv_n ( cram1_adv_n ),
.cram1_cre ( cram1_cre ),
.cram1_ce0_n ( cram1_ce0_n ),
.cram1_ce1_n ( cram1_ce1_n ),
.cram1_oe_n ( cram1_oe_n ),
.cram1_we_n ( cram1_we_n ),
.cram1_ub_n ( cram1_ub_n ),
.cram1_lb_n ( cram1_lb_n ),
.dram_a ( dram_a ),
.dram_ba ( dram_ba ),
.dram_dq ( dram_dq ),
.dram_dqm ( dram_dqm ),
.dram_clk ( dram_clk ),
.dram_cke ( dram_cke ),
.dram_ras_n ( dram_ras_n ),
.dram_cas_n ( dram_cas_n ),
.dram_we_n ( dram_we_n ),
.sram_a ( sram_a ),
.sram_dq ( sram_dq ),
.sram_oe_n ( sram_oe_n ),
.sram_we_n ( sram_we_n ),
.sram_ub_n ( sram_ub_n ),
.sram_lb_n ( sram_lb_n ),
.vblank ( vblank ),
.vpll_feed ( vpll_feed ),
.dbg_tx ( dbg_tx ),
.dbg_rx ( dbg_rx ),
.user1 ( user1 ),
.user2 ( user2 ),
.aux_sda ( aux_sda ),
.aux_scl ( aux_scl ),
// logical connections with user core
//
.video_rgb ( video_rgb ),
.video_rgb_clock ( video_rgb_clock ),
.video_rgb_clock_90 ( video_rgb_clock_90 ),
.video_de ( video_de ),
.video_skip ( video_skip ),
.video_vs ( video_vs ),
.video_hs ( video_hs ),
.bridge_endian_little ( bridge_endian_little ),
.bridge_addr ( bridge_addr ),
.bridge_rd ( bridge_rd ),
.bridge_rd_data ( bridge_rd_data ),
.bridge_wr ( bridge_wr ),
.bridge_wr_data ( bridge_wr_data ),
.cont1_key ( cont1_key ),
.cont2_key ( cont2_key ),
.cont3_key ( cont3_key ),
.cont4_key ( cont4_key ),
.cont1_joy ( cont1_joy ),
.cont2_joy ( cont2_joy ),
.cont3_joy ( cont3_joy ),
.cont4_joy ( cont4_joy ),
.cont1_trig ( cont1_trig ),
.cont2_trig ( cont2_trig ),
.cont3_trig ( cont3_trig ),
.cont4_trig ( cont4_trig ),
.cont1_legacy ( buttons_legacy )
);
endmodule |
module synch_2 #(parameter WIDTH = 1) (
input wire [WIDTH-1:0] i, // input signal
output reg [WIDTH-1:0] o, // synchronized output
input wire clk, // clock to synchronize on
output wire rise, // one-cycle rising edge pulse
output wire fall // one-cycle falling edge pulse
);
reg [WIDTH-1:0] stage_1;
reg [WIDTH-1:0] stage_2;
reg [WIDTH-1:0] stage_3;
assign rise = (WIDTH == 1) ? (o & ~stage_2) : 1'b0;
assign fall = (WIDTH == 1) ? (~o & stage_2) : 1'b0;
always @(posedge clk)
{stage_2, o, stage_1} <= {o, stage_1, i};
endmodule |
module synch_3 #(parameter WIDTH = 1) (
input wire [WIDTH-1:0] i, // input signal
output reg [WIDTH-1:0] o, // synchronized output
input wire clk, // clock to synchronize on
output wire rise, // one-cycle rising edge pulse
output wire fall // one-cycle falling edge pulse
);
reg [WIDTH-1:0] stage_1;
reg [WIDTH-1:0] stage_2;
reg [WIDTH-1:0] stage_3;
assign rise = (WIDTH == 1) ? (o & ~stage_3) : 1'b0;
assign fall = (WIDTH == 1) ? (~o & stage_3) : 1'b0;
always @(posedge clk)
{stage_3, o, stage_2, stage_1} <= {o, stage_2, stage_1, i};
endmodule |
module bram_block_dp #(
parameter DATA = 32,
parameter ADDR = 7
) (
input wire a_clk,
input wire a_wr,
input wire [ADDR-1:0] a_addr,
input wire [DATA-1:0] a_din,
output reg [DATA-1:0] a_dout,
input wire b_clk,
input wire b_wr,
input wire [ADDR-1:0] b_addr,
input wire [DATA-1:0] b_din,
output reg [DATA-1:0] b_dout
);
reg [DATA-1:0] mem [(2**ADDR)-1:0];
always @(posedge a_clk) begin
if(a_wr) begin
a_dout <= a_din;
mem[a_addr] <= a_din;
end else
a_dout <= mem[a_addr];
end
always @(posedge b_clk) begin
if(b_wr) begin
b_dout <= b_din;
mem[b_addr] <= b_din;
end else
b_dout <= mem[b_addr];
end
endmodule |
module bram_block_dp_nonstd #(
parameter DATA = 32,
parameter ADDR = 7,
parameter DEPTH = 128
) (
input wire a_clk,
input wire a_wr,
input wire [ADDR-1:0] a_addr,
input wire [DATA-1:0] a_din,
output reg [DATA-1:0] a_dout,
input wire b_clk,
input wire b_wr,
input wire [ADDR-1:0] b_addr,
input wire [DATA-1:0] b_din,
output reg [DATA-1:0] b_dout
);
reg [DATA-1:0] mem [DEPTH-1:0];
always @(posedge a_clk) begin
if(a_wr) begin
a_dout <= a_din;
mem[a_addr] <= a_din;
end else
a_dout <= mem[a_addr];
end
always @(posedge b_clk) begin
if(b_wr) begin
b_dout <= b_din;
mem[b_addr] <= b_din;
end else
b_dout <= mem[b_addr];
end
endmodule |
module mf_ddio_bidir_12 (
datain_h,
datain_l,
inclock,
oe,
outclock,
dataout_h,
dataout_l,
padio);
input [11:0] datain_h;
input [11:0] datain_l;
input inclock;
input oe;
input outclock;
output [11:0] dataout_h;
output [11:0] dataout_l;
inout [11:0] padio;
wire [11:0] sub_wire0;
wire [11:0] sub_wire1;
wire [11:0] dataout_h = sub_wire0[11:0];
wire [11:0] dataout_l = sub_wire1[11:0];
altddio_bidir ALTDDIO_BIDIR_component (
.datain_h (datain_h),
.datain_l (datain_l),
.inclock (inclock),
.oe (oe),
.outclock (outclock),
.padio (padio),
.dataout_h (sub_wire0),
.dataout_l (sub_wire1),
.aclr (1'b0),
.aset (1'b0),
.combout (),
.dqsundelayedout (),
.inclocken (1'b1),
.oe_out (),
.outclocken (1'b1),
.sclr (1'b0),
.sset (1'b0));
defparam
ALTDDIO_BIDIR_component.extend_oe_disable = "OFF",
ALTDDIO_BIDIR_component.implement_input_in_lcell = "OFF",
ALTDDIO_BIDIR_component.intended_device_family = "Cyclone V",
ALTDDIO_BIDIR_component.invert_output = "OFF",
ALTDDIO_BIDIR_component.lpm_hint = "UNUSED",
ALTDDIO_BIDIR_component.lpm_type = "altddio_bidir",
ALTDDIO_BIDIR_component.oe_reg = "UNREGISTERED",
ALTDDIO_BIDIR_component.power_up_high = "OFF",
ALTDDIO_BIDIR_component.width = 12;
endmodule |
module pll_0002(
// interface 'refclk'
input wire refclk,
// interface 'reset'
input wire rst,
// interface 'outclk0'
output wire outclk_0,
// interface 'outclk1'
output wire outclk_1,
// interface 'outclk2'
output wire outclk_2,
// interface 'locked'
output wire locked
);
altera_pll #(
.fractional_vco_multiplier("true"),
.reference_clock_frequency("74.25 MHz"),
.operation_mode("direct"),
.number_of_clocks(3),
.output_clock_frequency0("42.400000 MHz"),
.phase_shift0("0 ps"),
.duty_cycle0(50),
.output_clock_frequency1("42.400000 MHz"),
.phase_shift1("5896 ps"),
.duty_cycle1(50),
.output_clock_frequency2("84.800000 MHz"),
.phase_shift2("0 ps"),
.duty_cycle2(50),
.output_clock_frequency3("0 MHz"),
.phase_shift3("0 ps"),
.duty_cycle3(50),
.output_clock_frequency4("0 MHz"),
.phase_shift4("0 ps"),
.duty_cycle4(50),
.output_clock_frequency5("0 MHz"),
.phase_shift5("0 ps"),
.duty_cycle5(50),
.output_clock_frequency6("0 MHz"),
.phase_shift6("0 ps"),
.duty_cycle6(50),
.output_clock_frequency7("0 MHz"),
.phase_shift7("0 ps"),
.duty_cycle7(50),
.output_clock_frequency8("0 MHz"),
.phase_shift8("0 ps"),
.duty_cycle8(50),
.output_clock_frequency9("0 MHz"),
.phase_shift9("0 ps"),
.duty_cycle9(50),
.output_clock_frequency10("0 MHz"),
.phase_shift10("0 ps"),
.duty_cycle10(50),
.output_clock_frequency11("0 MHz"),
.phase_shift11("0 ps"),
.duty_cycle11(50),
.output_clock_frequency12("0 MHz"),
.phase_shift12("0 ps"),
.duty_cycle12(50),
.output_clock_frequency13("0 MHz"),
.phase_shift13("0 ps"),
.duty_cycle13(50),
.output_clock_frequency14("0 MHz"),
.phase_shift14("0 ps"),
.duty_cycle14(50),
.output_clock_frequency15("0 MHz"),
.phase_shift15("0 ps"),
.duty_cycle15(50),
.output_clock_frequency16("0 MHz"),
.phase_shift16("0 ps"),
.duty_cycle16(50),
.output_clock_frequency17("0 MHz"),
.phase_shift17("0 ps"),
.duty_cycle17(50),
.pll_type("General"),
.pll_subtype("General")
) altera_pll_i (
.rst (rst),
.outclk ({outclk_2, outclk_1, outclk_0}),
.locked (locked),
.fboutclk ( ),
.fbclk (1'b0),
.refclk (refclk)
);
endmodule |
module Multipler (
clock0,
dataa_0,
datab_0,
result);
input clock0;
input [9:0] dataa_0;
input [9:0] datab_0;
output [20:0] result;
wire [20:0] sub_wire0;
wire [20:0] result = sub_wire0[20:0];
wire [9:0] wire_dataa;
assign wire_dataa[9:0] = dataa_0;
wire [9:0] wire_datab;
assign wire_datab[9:0] = datab_0;
altera_mult_add altera_mult_add_component (
.clock0 (clock0),
.dataa (wire_dataa),
.datab (wire_datab),
.result (sub_wire0),
.accum_sload (1'b0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.aclr2 (1'b0),
.aclr3 (1'b0),
.addnsub1 (1'b1),
.addnsub1_round (1'b0),
.addnsub3 (1'b1),
.addnsub3_round (1'b0),
.chainin (1'b0),
.chainout_round (1'b0),
.chainout_sat_overflow (),
.chainout_saturate (1'b0),
.clock1 (1'b1),
.clock2 (1'b1),
.clock3 (1'b1),
.coefsel0 ({3{1'b0}}),
.coefsel1 ({3{1'b0}}),
.coefsel2 ({3{1'b0}}),
.coefsel3 ({3{1'b0}}),
.datac ({16{1'b0}}),
.ena0 (1'b1),
.ena1 (1'b1),
.ena2 (1'b1),
.ena3 (1'b1),
.mult01_round (1'b0),
.mult01_saturation (1'b0),
.mult0_is_saturated (),
.mult1_is_saturated (),
.mult23_round (1'b0),
.mult23_saturation (1'b0),
.mult2_is_saturated (),
.mult3_is_saturated (),
.negate (1'b0),
.output_round (1'b0),
.output_saturate (1'b0),
.overflow (),
.rotate (1'b0),
.scanina ({10{1'b0}}),
.scaninb ({10{1'b0}}),
.scanouta (),
.scanoutb (),
.sclr0 (1'b0),
.sclr1 (1'b0),
.sclr2 (1'b0),
.sclr3 (1'b0),
.shift_right (1'b0),
.signa (1'b0),
.signb (1'b0),
.sload_accum (1'b0),
.sourcea ({1{1'b0}}),
.sourceb ({1{1'b0}}),
.zero_chainout (1'b0),
.zero_loopback (1'b0));
defparam
altera_mult_add_component.number_of_multipliers = 1,
altera_mult_add_component.width_a = 10,
altera_mult_add_component.width_b = 10,
altera_mult_add_component.width_result = 21,
altera_mult_add_component.output_register = "UNREGISTERED",
altera_mult_add_component.output_aclr = "NONE",
altera_mult_add_component.output_sclr = "NONE",
altera_mult_add_component.multiplier1_direction = "ADD",
altera_mult_add_component.port_addnsub1 = "PORT_UNUSED",
altera_mult_add_component.addnsub_multiplier_register1 = "UNREGISTERED",
altera_mult_add_component.addnsub_multiplier_aclr1 = "NONE",
altera_mult_add_component.addnsub_multiplier_sclr1 = "NONE",
altera_mult_add_component.multiplier3_direction = "ADD",
altera_mult_add_component.port_addnsub3 = "PORT_UNUSED",
altera_mult_add_component.addnsub_multiplier_register3 = "UNREGISTERED",
altera_mult_add_component.addnsub_multiplier_aclr3 = "NONE",
altera_mult_add_component.addnsub_multiplier_sclr3 = "NONE",
altera_mult_add_component.use_subnadd = "NO",
altera_mult_add_component.representation_a = "UNSIGNED",
altera_mult_add_component.port_signa = "PORT_UNUSED",
altera_mult_add_component.signed_register_a = "UNREGISTERED",
altera_mult_add_component.signed_aclr_a = "NONE",
altera_mult_add_component.signed_sclr_a = "NONE",
altera_mult_add_component.port_signb = "PORT_UNUSED",
altera_mult_add_component.representation_b = "UNSIGNED",
altera_mult_add_component.signed_register_b = "UNREGISTERED",
altera_mult_add_component.signed_aclr_b = "NONE",
altera_mult_add_component.signed_sclr_b = "NONE",
altera_mult_add_component.input_register_a0 = "UNREGISTERED",
altera_mult_add_component.input_register_a1 = "UNREGISTERED",
altera_mult_add_component.input_register_a2 = "UNREGISTERED",
altera_mult_add_component.input_register_a3 = "UNREGISTERED",
altera_mult_add_component.input_aclr_a0 = "NONE",
altera_mult_add_component.input_aclr_a1 = "NONE",
altera_mult_add_component.input_aclr_a2 = "NONE",
altera_mult_add_component.input_aclr_a3 = "NONE",
altera_mult_add_component.input_sclr_a0 = "NONE",
altera_mult_add_component.input_sclr_a1 = "NONE",
altera_mult_add_component.input_sclr_a2 = "NONE",
altera_mult_add_component.input_sclr_a3 = "NONE",
altera_mult_add_component.input_register_b0 = "UNREGISTERED",
altera_mult_add_component.input_register_b1 = "UNREGISTERED",
altera_mult_add_component.input_register_b2 = "UNREGISTERED",
altera_mult_add_component.input_register_b3 = "UNREGISTERED",
altera_mult_add_component.input_aclr_b0 = "NONE",
altera_mult_add_component.input_aclr_b1 = "NONE",
altera_mult_add_component.input_aclr_b2 = "NONE",
altera_mult_add_component.input_aclr_b3 = "NONE",
altera_mult_add_component.input_sclr_b0 = "NONE",
altera_mult_add_component.input_sclr_b1 = "NONE",
altera_mult_add_component.input_sclr_b2 = "NONE",
altera_mult_add_component.input_sclr_b3 = "NONE",
altera_mult_add_component.scanouta_register = "UNREGISTERED",
altera_mult_add_component.scanouta_aclr = "NONE",
altera_mult_add_component.scanouta_sclr = "NONE",
altera_mult_add_component.input_source_a0 = "DATAA",
altera_mult_add_component.input_source_a1 = "DATAA",
altera_mult_add_component.input_source_a2 = "DATAA",
altera_mult_add_component.input_source_a3 = "DATAA",
altera_mult_add_component.input_source_b0 = "DATAB",
altera_mult_add_component.input_source_b1 = "DATAB",
altera_mult_add_component.input_source_b2 = "DATAB",
altera_mult_add_component.input_source_b3 = "DATAB",
altera_mult_add_component.multiplier_register0 = "UNREGISTERED",
altera_mult_add_component.multiplier_register1 = "UNREGISTERED",
altera_mult_add_component.multiplier_register2 = "UNREGISTERED",
altera_mult_add_component.multiplier_register3 = "UNREGISTERED",
altera_mult_add_component.multiplier_aclr0 = "NONE",
altera_mult_add_component.multiplier_aclr1 = "NONE",
altera_mult_add_component.multiplier_aclr2 = "NONE",
altera_mult_add_component.multiplier_aclr3 = "NONE",
altera_mult_add_component.multiplier_sclr0 = "NONE",
altera_mult_add_component.multiplier_sclr1 = "NONE",
altera_mult_add_component.multiplier_sclr2 = "NONE",
altera_mult_add_component.multiplier_sclr3 = "NONE",
altera_mult_add_component.preadder_mode = "SIMPLE",
altera_mult_add_component.preadder_direction_0 = "ADD",
altera_mult_add_component.preadder_direction_1 = "ADD",
altera_mult_add_component.preadder_direction_2 = "ADD",
altera_mult_add_component.preadder_direction_3 = "ADD",
altera_mult_add_component.width_c = 16,
altera_mult_add_component.input_register_c0 = "UNREGISTERED",
altera_mult_add_component.input_register_c1 = "UNREGISTERED",
altera_mult_add_component.input_register_c2 = "UNREGISTERED",
altera_mult_add_component.input_register_c3 = "UNREGISTERED",
altera_mult_add_component.input_aclr_c0 = "NONE",
altera_mult_add_component.input_aclr_c1 = "NONE",
altera_mult_add_component.input_aclr_c2 = "NONE",
altera_mult_add_component.input_aclr_c3 = "NONE",
altera_mult_add_component.input_sclr_c0 = "NONE",
altera_mult_add_component.input_sclr_c1 = "NONE",
altera_mult_add_component.input_sclr_c2 = "NONE",
altera_mult_add_component.input_sclr_c3 = "NONE",
altera_mult_add_component.width_coef = 18,
altera_mult_add_component.coefsel0_register = "UNREGISTERED",
altera_mult_add_component.coefsel1_register = "UNREGISTERED",
altera_mult_add_component.coefsel2_register = "UNREGISTERED",
altera_mult_add_component.coefsel3_register = "UNREGISTERED",
altera_mult_add_component.coefsel0_aclr = "NONE",
altera_mult_add_component.coefsel1_aclr = "NONE",
altera_mult_add_component.coefsel2_aclr = "NONE",
altera_mult_add_component.coefsel3_aclr = "NONE",
altera_mult_add_component.coefsel0_sclr = "NONE",
altera_mult_add_component.coefsel1_sclr = "NONE",
altera_mult_add_component.coefsel2_sclr = "NONE",
altera_mult_add_component.coefsel3_sclr = "NONE",
altera_mult_add_component.coef0_0 = 0,
altera_mult_add_component.coef0_1 = 0,
altera_mult_add_component.coef0_2 = 0,
altera_mult_add_component.coef0_3 = 0,
altera_mult_add_component.coef0_4 = 0,
altera_mult_add_component.coef0_5 = 0,
altera_mult_add_component.coef0_6 = 0,
altera_mult_add_component.coef0_7 = 0,
altera_mult_add_component.coef1_0 = 0,
altera_mult_add_component.coef1_1 = 0,
altera_mult_add_component.coef1_2 = 0,
altera_mult_add_component.coef1_3 = 0,
altera_mult_add_component.coef1_4 = 0,
altera_mult_add_component.coef1_5 = 0,
altera_mult_add_component.coef1_6 = 0,
altera_mult_add_component.coef1_7 = 0,
altera_mult_add_component.coef2_0 = 0,
altera_mult_add_component.coef2_1 = 0,
altera_mult_add_component.coef2_2 = 0,
altera_mult_add_component.coef2_3 = 0,
altera_mult_add_component.coef2_4 = 0,
altera_mult_add_component.coef2_5 = 0,
altera_mult_add_component.coef2_6 = 0,
altera_mult_add_component.coef2_7 = 0,
altera_mult_add_component.coef3_0 = 0,
altera_mult_add_component.coef3_1 = 0,
altera_mult_add_component.coef3_2 = 0,
altera_mult_add_component.coef3_3 = 0,
altera_mult_add_component.coef3_4 = 0,
altera_mult_add_component.coef3_5 = 0,
altera_mult_add_component.coef3_6 = 0,
altera_mult_add_component.coef3_7 = 0,
altera_mult_add_component.accumulator = "NO",
altera_mult_add_component.accum_direction = "ADD",
altera_mult_add_component.use_sload_accum_port = "NO",
altera_mult_add_component.loadconst_value = 64,
altera_mult_add_component.accum_sload_register = "UNREGISTERED",
altera_mult_add_component.accum_sload_aclr = "NONE",
altera_mult_add_component.accum_sload_sclr = "NONE",
altera_mult_add_component.double_accum = "NO",
altera_mult_add_component.width_chainin = 1,
altera_mult_add_component.chainout_adder = "NO",
altera_mult_add_component.chainout_adder_direction = "ADD",
altera_mult_add_component.port_negate = "PORT_UNUSED",
altera_mult_add_component.negate_register = "UNREGISTERED",
altera_mult_add_component.negate_aclr = "NONE",
altera_mult_add_component.negate_sclr = "NONE",
altera_mult_add_component.systolic_delay1 = "UNREGISTERED",
altera_mult_add_component.systolic_aclr1 = "NONE",
altera_mult_add_component.systolic_sclr1 = "NONE",
altera_mult_add_component.systolic_delay3 = "UNREGISTERED",
altera_mult_add_component.systolic_aclr3 = "NONE",
altera_mult_add_component.systolic_sclr3 = "NONE",
altera_mult_add_component.latency = 3,
altera_mult_add_component.input_a0_latency_clock = "CLOCK0",
altera_mult_add_component.input_a1_latency_clock = "UNREGISTERED",
altera_mult_add_component.input_a2_latency_clock = "UNREGISTERED",
altera_mult_add_component.input_a3_latency_clock = "UNREGISTERED",
altera_mult_add_component.input_a0_latency_aclr = "NONE",
altera_mult_add_component.input_a1_latency_aclr = "NONE",
altera_mult_add_component.input_a2_latency_aclr = "NONE",
altera_mult_add_component.input_a3_latency_aclr = "NONE",
altera_mult_add_component.input_a0_latency_sclr = "NONE",
altera_mult_add_component.input_a1_latency_sclr = "NONE",
altera_mult_add_component.input_a2_latency_sclr = "NONE",
altera_mult_add_component.input_a3_latency_sclr = "NONE",
altera_mult_add_component.input_b0_latency_clock = "CLOCK0",
altera_mult_add_component.input_b1_latency_clock = "UNREGISTERED",
altera_mult_add_component.input_b2_latency_clock = "UNREGISTERED",
altera_mult_add_component.input_b3_latency_clock = "UNREGISTERED",
altera_mult_add_component.input_b0_latency_aclr = "NONE",
altera_mult_add_component.input_b1_latency_aclr = "NONE",
altera_mult_add_component.input_b2_latency_aclr = "NONE",
altera_mult_add_component.input_b3_latency_aclr = "NONE",
altera_mult_add_component.input_b0_latency_sclr = "NONE",
altera_mult_add_component.input_b1_latency_sclr = "NONE",
altera_mult_add_component.input_b2_latency_sclr = "NONE",
altera_mult_add_component.input_b3_latency_sclr = "NONE",
altera_mult_add_component.input_c0_latency_clock = "UNREGISTERED",
altera_mult_add_component.input_c1_latency_clock = "UNREGISTERED",
altera_mult_add_component.input_c2_latency_clock = "UNREGISTERED",
altera_mult_add_component.input_c3_latency_clock = "UNREGISTERED",
altera_mult_add_component.input_c0_latency_aclr = "NONE",
altera_mult_add_component.input_c1_latency_aclr = "NONE",
altera_mult_add_component.input_c2_latency_aclr = "NONE",
altera_mult_add_component.input_c3_latency_aclr = "NONE",
altera_mult_add_component.input_c0_latency_sclr = "NONE",
altera_mult_add_component.input_c1_latency_sclr = "NONE",
altera_mult_add_component.input_c2_latency_sclr = "NONE",
altera_mult_add_component.input_c3_latency_sclr = "NONE",
altera_mult_add_component.coefsel0_latency_clock = "UNREGISTERED",
altera_mult_add_component.coefsel1_latency_clock = "UNREGISTERED",
altera_mult_add_component.coefsel2_latency_clock = "UNREGISTERED",
altera_mult_add_component.coefsel3_latency_clock = "UNREGISTERED",
altera_mult_add_component.coefsel0_latency_aclr = "NONE",
altera_mult_add_component.coefsel1_latency_aclr = "NONE",
altera_mult_add_component.coefsel2_latency_aclr = "NONE",
altera_mult_add_component.coefsel3_latency_aclr = "NONE",
altera_mult_add_component.coefsel0_latency_sclr = "NONE",
altera_mult_add_component.coefsel1_latency_sclr = "NONE",
altera_mult_add_component.coefsel2_latency_sclr = "NONE",
altera_mult_add_component.coefsel3_latency_sclr = "NONE",
altera_mult_add_component.signed_latency_clock_a = "UNREGISTERED",
altera_mult_add_component.signed_latency_aclr_a = "NONE",
altera_mult_add_component.signed_latency_sclr_a = "NONE",
altera_mult_add_component.signed_latency_clock_b = "UNREGISTERED",
altera_mult_add_component.signed_latency_aclr_b = "NONE",
altera_mult_add_component.signed_latency_sclr_b = "NONE",
altera_mult_add_component.addnsub_multiplier_latency_clock1 = "UNREGISTERED",
altera_mult_add_component.addnsub_multiplier_latency_aclr1 = "NONE",
altera_mult_add_component.addnsub_multiplier_latency_sclr1 = "NONE",
altera_mult_add_component.addnsub_multiplier_latency_clock3 = "UNREGISTERED",
altera_mult_add_component.addnsub_multiplier_latency_aclr3 = "NONE",
altera_mult_add_component.addnsub_multiplier_latency_sclr3 = "NONE",
altera_mult_add_component.accum_sload_latency_clock = "UNREGISTERED",
altera_mult_add_component.accum_sload_latency_aclr = "NONE",
altera_mult_add_component.accum_sload_latency_sclr = "NONE",
altera_mult_add_component.negate_latency_clock = "UNREGISTERED",
altera_mult_add_component.negate_latency_aclr = "NONE",
altera_mult_add_component.negate_latency_sclr = "NONE",
altera_mult_add_component.selected_device_family = "Cyclone V";
endmodule |
module Scaler_pdp (
input main_clk, /* Main Clock input, 1280 x 1024 @ 60 Hz is 108 MHz pixel clock */
input clk, /* VGA Scaller Clock input, 1280 x 1024 @ 60 Hz is 108 MHz pixel clock */
input [7:0] red_out_internal, /* Outputs RGB values for corresponding pixels */
input [7:0] green_out_internal,
input [7:0] blue_out_internal,
input [10:0] horizontal_counter, /* Current video drawing position */
input [10:0] vertical_counter,
output reg [10:0] horizontal_counter_internal, /* Current video drawing position */
output reg [10:0] vertical_counter_internal,
output reg [7:0] red_out, /* Outputs RGB values for corresponding pixels */
output reg [7:0] green_out,
output reg [7:0] blue_out
);
// this is for the Internal video
parameter DATA_WIDTH = 8;
parameter COEFF_WIDTH = 9;
parameter CHANNELS = 3;
parameter FRACTION_BITS = 8;
localparam internal_BPORCH = 'd1;
localparam internal_ACTIVE = 'd1024;
localparam internal_TOTAL = 'd1030;
// This is for the external Video
localparam VID_H_BPORCH = 'd145;
localparam VID_H_ACTIVE = 'd720;
localparam VID_H_TOTAL = 'd1024;
localparam VID_V_ACTIVE = 'd720;
localparam VID_V_TOTAL = 'd780;
localparam VID_V_BPORCH = 'd8;
wire [8:0] internal_scaler_fraction = 9'b1_01101100;
reg [18:0] Internal_y_scale_adder; // this is the final adder with the scaler
reg [18:0] Internal_x_scale_adder; // this is the final adder with the scaler
wire [23:0] read_color_0, read_color_1, read_color_2, read_color_3;
wire [DATA_WIDTH*CHANNELS-1:0] readData00;
wire [DATA_WIDTH*CHANNELS-1:0] readData01;
wire [DATA_WIDTH*CHANNELS-1:0] readData10;
wire [DATA_WIDTH*CHANNELS-1:0] readData11;
reg [DATA_WIDTH*CHANNELS-1:0] readData00Reg;
reg [DATA_WIDTH*CHANNELS-1:0] readData01Reg;
reg [DATA_WIDTH*CHANNELS-1:0] readData10Reg;
reg [DATA_WIDTH*CHANNELS-1:0] readData11Reg;
reg [1:0] internal_y_read_0;
reg [1:0] internal_y_read_1;
reg swap_y;
reg write_BRAM_reg;
wire write_BRAM_wire = (horizontal_counter_internal >= 1 && horizontal_counter_internal < 1024);
always @(posedge main_clk) begin
write_BRAM_reg <= write_BRAM_wire;
end
reg [1:0] internal_y_write_counter_final;
always @* begin
case (Internal_y_scale_adder[9:8])
2'h3 : internal_y_write_counter_final <= 'd2;
2'h2 : internal_y_write_counter_final <= 'd1;
3'h1 : internal_y_write_counter_final <= 'd0;
default : internal_y_write_counter_final <= 'd3;
endcase
end
always @(posedge main_clk) begin
// This is the starter for the read the video from the high reg video
if ((vertical_counter >= (VID_V_BPORCH - 2)) && (vertical_counter <= (VID_V_BPORCH + VID_V_ACTIVE))) begin
// This checks if the line buffers are full
if (vertical_counter_internal[1:0] != internal_y_write_counter_final) begin
horizontal_counter_internal <= horizontal_counter_internal + 1;
if(horizontal_counter_internal == internal_TOTAL) begin
horizontal_counter_internal <= 0;
vertical_counter_internal <= vertical_counter_internal + 1'b1;
if(vertical_counter_internal == internal_TOTAL) begin
vertical_counter_internal <= 0;
end
end
end
end
else begin
vertical_counter_internal <= 'b0;
horizontal_counter_internal <= 'b0;
end
end
wire [9:0] internal_x_write = horizontal_counter_internal - 1;
wire [1:0] internal_y_write = vertical_counter_internal - 1;
scaler_main_ram scaler_main_ram_0(
.address_a ({internal_y_write[1], internal_x_write[9:0]}),
.address_b ({internal_y_read_0, Internal_x_scale_adder[17:8]}),
.clock_a (main_clk),
.clock_b (clk),
.data_a ({red_out_internal, green_out_internal, blue_out_internal}),
.wren_a (&{~internal_y_write[0], write_BRAM_reg}),
.wren_b (1'b0),
.q_b (readData00));
scaler_main_ram scaler_main_ram_1(
.address_a ({internal_y_write[1], internal_x_write[9:0]}),
.address_b ({internal_y_read_1, Internal_x_scale_adder[17:8]}),
.clock_a (main_clk),
.clock_b (clk),
.data_a ({red_out_internal, green_out_internal, blue_out_internal}),
.wren_a (&{internal_y_write[0], write_BRAM_reg}),
.wren_b (1'b0),
.q_b (readData10));
scaler_main_ram scaler_main_ram_2(
.address_a ({internal_y_write[1], internal_x_write[9:0]}),
.address_b ({internal_y_read_0, Internal_x_scale_adder[17:8] + 1}),
.clock_a (main_clk),
.clock_b (clk),
.data_a ({red_out_internal, green_out_internal, blue_out_internal}),
.wren_a (&{~internal_y_write[0], write_BRAM_reg}),
.wren_b (1'b0),
.q_b (readData01));
scaler_main_ram scaler_main_ram_3(
.address_a ({internal_y_write[1], internal_x_write[9:0]}),
.address_b ({internal_y_read_1, Internal_x_scale_adder[17:8] + 1}),
.clock_a (main_clk),
.clock_b (clk),
.data_a ({red_out_internal, green_out_internal, blue_out_internal}),
.wren_a (&{internal_y_write[0], write_BRAM_reg}),
.wren_b (1'b0),
.q_b (readData11));
// X scaler address Multipler for the read side
wire [10:0] internal_x_read;
reg [10:0] x_read_counter;
reg [18:0] Internal_x_scale_0_adder_reg, Internal_x_scale_1_adder_reg, Internal_x_scale_2_adder_reg, Internal_x_scale_3_adder_reg;
always @(posedge clk) begin
x_read_counter <= (horizontal_counter >= (VID_H_BPORCH) && horizontal_counter <= (VID_H_BPORCH + VID_V_ACTIVE)) ? horizontal_counter - VID_H_BPORCH : 'b0;
Internal_x_scale_adder <= internal_scaler_fraction * x_read_counter;
end
// Y scaler address Multipler for the read side We only need to care about 4 lines of Virtical lines
reg [10:0] y_read_counter;
reg [18:0] Internal_y_scale_0_adder_reg, Internal_y_scale_1_adder_reg, Internal_y_scale_2_adder_reg, Internal_y_scale_3_adder_reg;
always @(posedge clk) begin
y_read_counter <= (vertical_counter >= VID_V_BPORCH ) ? vertical_counter - VID_V_BPORCH : 'b0;
Internal_y_scale_adder <= internal_scaler_fraction * y_read_counter;
end
// This is used for the line selector for the read
always @* begin
case (Internal_y_scale_adder[9:8])
2'd3 : begin
internal_y_read_0 <= 1'b0;
internal_y_read_1 <= 1'b1;
swap_y <= 1'b1;
end
2'd2 : begin
internal_y_read_0 <= 1'b1;
internal_y_read_1 <= 1'b1;
swap_y <= 1'b0;
end
2'd1 : begin
internal_y_read_0 <= 1'b1;
internal_y_read_1 <= 1'b0;
swap_y <= 1'b1;
end
default : begin
internal_y_read_0 <= 1'b0;
internal_y_read_1 <= 1'b0;
swap_y <= 1'b0;
end
endcase
end
// Color Multiplyer
// Red Color (I love making real code for this)
wire [COEFF_WIDTH-1:0] preCoeff00 = (((coeffOne - Internal_x_scale_adder[7:0]) * (coeffOne - Internal_y_scale_adder[7:0]) + (coeffHalf - 1)) >> FRACTION_BITS) & {{COEFF_WIDTH{1'b0}}, {COEFF_WIDTH{1'b1}}};
wire [COEFF_WIDTH-1:0] preCoeff01 = ((Internal_x_scale_adder[7:0] * (coeffOne - Internal_y_scale_adder[7:0]) + (coeffHalf - 1)) >> FRACTION_BITS) & {{COEFF_WIDTH{1'b0}}, {COEFF_WIDTH{1'b1}}};
wire [COEFF_WIDTH-1:0] preCoeff10 = (((coeffOne - Internal_x_scale_adder[7:0]) * Internal_y_scale_adder[7:0] + (coeffHalf - 1)) >> FRACTION_BITS) & {{COEFF_WIDTH{1'b0}}, {COEFF_WIDTH{1'b1}}};
// We will run 4 stages to the scaller
reg [23:0] dOut;
reg [COEFF_WIDTH-1:0] coeff00; //Top left
reg [COEFF_WIDTH-1:0] coeff01; //Top right
reg [COEFF_WIDTH-1:0] coeff10; //Bottom left
reg [COEFF_WIDTH-1:0] coeff11; //Bottom right
//Coefficient value of one, format Q1.COEFF_WIDTH-1
wire [COEFF_WIDTH-1:0] coeffOne = {1'b1, {(COEFF_WIDTH-1){1'b0}}}; //One in MSb, zeros elsewhere
wire [COEFF_WIDTH-1:0] coeffHalf = {2'b01, {(COEFF_WIDTH-2){1'b0}}};
always @(posedge clk) begin
// coeff00 <= Internal_x_scale_adder < coeffHalf && Internal_y_scale_adder < coeffHalf ? coeffOne : {COEFF_WIDTH{1'b0}};
// coeff01 <= Internal_x_scale_adder >= coeffHalf && Internal_y_scale_adder < coeffHalf ? coeffOne : {COEFF_WIDTH{1'b0}};
// coeff10 <= Internal_x_scale_adder < coeffHalf && Internal_y_scale_adder >= coeffHalf ? coeffOne : {COEFF_WIDTH{1'b0}};
// coeff11 <= Internal_x_scale_adder >= coeffHalf && Internal_y_scale_adder >= coeffHalf ? coeffOne : {COEFF_WIDTH{1'b0}};
coeff00 <= preCoeff00;
coeff01 <= preCoeff01;
coeff10 <= preCoeff10;
coeff11 <= ((Internal_x_scale_adder[7:0] * Internal_y_scale_adder[7:0] + (coeffHalf - 1)) >> FRACTION_BITS) & {{COEFF_WIDTH{1'b0}}, {COEFF_WIDTH{1'b1}}};
red_out <= dOut[23:16];
green_out <= dOut[15:8];
blue_out <= dOut[7:0];
end
wire rst = 0;
reg [(DATA_WIDTH+COEFF_WIDTH)*CHANNELS-1:0] product00, product01, product10, product11;
generate
genvar channel;
for(channel = 0; channel < CHANNELS; channel = channel + 1)
begin : blend_mult_generate
always @(posedge clk or posedge rst)
begin
if(rst)
begin
//productxx[channel] <= 0;
product00[ (DATA_WIDTH+COEFF_WIDTH)*(channel+1)-1 : (DATA_WIDTH+COEFF_WIDTH)*channel] <= 0;
product01[ (DATA_WIDTH+COEFF_WIDTH)*(channel+1)-1 : (DATA_WIDTH+COEFF_WIDTH)*channel] <= 0;
product10[ (DATA_WIDTH+COEFF_WIDTH)*(channel+1)-1 : (DATA_WIDTH+COEFF_WIDTH)*channel] <= 0;
product11[ (DATA_WIDTH+COEFF_WIDTH)*(channel+1)-1 : (DATA_WIDTH+COEFF_WIDTH)*channel] <= 0;
//readDataxxReg[channel] <= 0;
readData00Reg[ DATA_WIDTH*(channel+1)-1 : DATA_WIDTH*channel ] <= 0;
readData01Reg[ DATA_WIDTH*(channel+1)-1 : DATA_WIDTH*channel ] <= 0;
readData10Reg[ DATA_WIDTH*(channel+1)-1 : DATA_WIDTH*channel ] <= 0;
readData11Reg[ DATA_WIDTH*(channel+1)-1 : DATA_WIDTH*channel ] <= 0;
//dOut[channel] <= 0;
dOut[ DATA_WIDTH*(channel+1)-1 : DATA_WIDTH*channel ] <= 0;
end
else
begin
//readDataxxReg[channel] <= readDataxx[channel];
readData00Reg[ DATA_WIDTH*(channel+1)-1 : DATA_WIDTH*channel ] <= swap_y ? readData10[ DATA_WIDTH*(channel+1)-1 : DATA_WIDTH*channel ] : readData00[ DATA_WIDTH*(channel+1)-1 : DATA_WIDTH*channel ];
readData01Reg[ DATA_WIDTH*(channel+1)-1 : DATA_WIDTH*channel ] <= swap_y ? readData11[ DATA_WIDTH*(channel+1)-1 : DATA_WIDTH*channel ] : readData01[ DATA_WIDTH*(channel+1)-1 : DATA_WIDTH*channel ];
readData10Reg[ DATA_WIDTH*(channel+1)-1 : DATA_WIDTH*channel ] <= swap_y ? readData00[ DATA_WIDTH*(channel+1)-1 : DATA_WIDTH*channel ] : readData10[ DATA_WIDTH*(channel+1)-1 : DATA_WIDTH*channel ];
readData11Reg[ DATA_WIDTH*(channel+1)-1 : DATA_WIDTH*channel ] <= swap_y ? readData01[ DATA_WIDTH*(channel+1)-1 : DATA_WIDTH*channel ] : readData11[ DATA_WIDTH*(channel+1)-1 : DATA_WIDTH*channel ];
//productxx[channel] <= readDataxxReg[channel] * coeffxx
product00[ (DATA_WIDTH+COEFF_WIDTH)*(channel+1)-1 : (DATA_WIDTH+COEFF_WIDTH)*channel] <= readData00Reg[ DATA_WIDTH*(channel+1)-1 : DATA_WIDTH*channel ] * coeff00;
product01[ (DATA_WIDTH+COEFF_WIDTH)*(channel+1)-1 : (DATA_WIDTH+COEFF_WIDTH)*channel] <= readData01Reg[ DATA_WIDTH*(channel+1)-1 : DATA_WIDTH*channel ] * coeff01;
product10[ (DATA_WIDTH+COEFF_WIDTH)*(channel+1)-1 : (DATA_WIDTH+COEFF_WIDTH)*channel] <= readData10Reg[ DATA_WIDTH*(channel+1)-1 : DATA_WIDTH*channel ] * coeff10;
product11[ (DATA_WIDTH+COEFF_WIDTH)*(channel+1)-1 : (DATA_WIDTH+COEFF_WIDTH)*channel] <= readData11Reg[ DATA_WIDTH*(channel+1)-1 : DATA_WIDTH*channel ] * coeff11;
if (horizontal_counter >= VID_H_BPORCH && horizontal_counter < VID_H_BPORCH + VID_H_ACTIVE) begin
dOut[ DATA_WIDTH*(channel+1)-1 : DATA_WIDTH*channel ] <=
(((product00[ (DATA_WIDTH+COEFF_WIDTH)*(channel+1)-1 : (DATA_WIDTH+COEFF_WIDTH)*channel]) +
(product01[ (DATA_WIDTH+COEFF_WIDTH)*(channel+1)-1 : (DATA_WIDTH+COEFF_WIDTH)*channel]) +
(product10[ (DATA_WIDTH+COEFF_WIDTH)*(channel+1)-1 : (DATA_WIDTH+COEFF_WIDTH)*channel]) +
(product11[ (DATA_WIDTH+COEFF_WIDTH)*(channel+1)-1 : (DATA_WIDTH+COEFF_WIDTH)*channel])) >> FRACTION_BITS) & ({ {COEFF_WIDTH{1'b0}}, {DATA_WIDTH{1'b1}} });
end
else begin
dOut[ DATA_WIDTH*(channel+1)-1 : DATA_WIDTH*channel ] <= 24'h0;
end
end
end
end
endgenerate
endmodule |
module mf_pllbase (
input wire refclk, // refclk.clk
input wire rst, // reset.reset
output wire outclk_0, // outclk0.clk
output wire outclk_1, // outclk1.clk
output wire locked // locked.export
);
mf_pllbase_0002 mf_pllbase_inst (
.refclk (refclk), // refclk.clk
.rst (rst), // reset.reset
.outclk_0 (outclk_0), // outclk0.clk
.outclk_1 (outclk_1), // outclk1.clk
.locked (locked) // locked.export
);
endmodule |
module serial_controller (
input clk, // 50mhz
input serial_clock, // 2.5mhz for the transport
input reset_l,
input slave_core,
input [9:0] pixel_x_addr_cpu,
input [9:0] pixel_y_addr_cpu,
input pixel_shift_cpu,
input [2:0] pixel_brightness_cpu,
output reg [9:0] pixel_x_addr_wire,
output reg [9:0] pixel_y_addr_wire,
output reg pixel_shift_wire,
output reg [2:0] pixel_brightness_wire,
input [15:0] cont1_key,
input [15:0] cont2_key,
output reg [15:0] cont2_key_internal,
// GBA link port
inout port_tran_si,
output reg port_tran_si_dir,
inout port_tran_so,
output reg port_tran_so_dir,
inout port_tran_sck,
output reg port_tran_sck_dir
);
// 50mhz Core
always @(posedge clk or negedge reset_l) begin
if (~reset_l) begin
pixel_x_addr_wire <= 'b0;
pixel_y_addr_wire <= 'b0;
pixel_shift_wire <= 'b0;
pixel_brightness_wire <= 'b0;
cont2_key_internal <= 'b0;
end
else begin
if (slave_core) begin
pixel_x_addr_wire <= 'b0;
pixel_y_addr_wire <= 'b0;
pixel_shift_wire <= 'b0;
pixel_brightness_wire <= 'b0;
cont2_key_internal <= 'b0;
end
else if (master_state == 0) begin
pixel_x_addr_wire <= pixel_x_addr_cpu;
pixel_y_addr_wire <= pixel_y_addr_cpu;
pixel_shift_wire <= pixel_shift_cpu;
pixel_brightness_wire <= pixel_brightness_cpu;
cont2_key_internal <= cont2_key;
end
end
end
// link port is input only
assign port_tran_so = 1'bz;
assign port_tran_si = 1'bz;
assign port_tran_sck = 1'bz;
// 2.5mhzmhz core
always @(posedge serial_clock or negedge reset_l) begin
if (~reset_l) begin
port_tran_so_dir <= 1'b0;
port_tran_si_dir <= 1'b0;
port_tran_sck_dir <= 1'b0;
end
else begin
if (slave_core) begin
port_tran_so_dir <= 1'b0;
port_tran_si_dir <= 1'b0;
port_tran_sck_dir <= 1'b0;
end
else begin
port_tran_so_dir <= 1'b0;
port_tran_si_dir <= 1'b0;
port_tran_sck_dir <= 1'b0;
end
end
end
parameter idle = 'd0;
parameter test_high = 'd1;
parameter test_low = 'd2;
parameter test_check = 'd3;
parameter master_idle = 'd4;
parameter master_start_h = 'd5;
parameter master_start_l = 'd6;
parameter master_high_h = 'd7;
parameter master_high_l = 'd8;
parameter master_low_h = 'd9;
parameter master_low_l = 'd10;
parameter slave_idle = 'd11;
parameter slave_start_h = 'd12;
parameter slave_start_l = 'd13;
parameter slave_high_h = 'd14;
parameter slave_high_l = 'd15;
parameter slave_low_h = 'd16;
parameter slave_low_l = 'd17;
reg [9:0] master_counter;
reg [3:0] master_state;
reg [3:0] slave_state;
reg data_out;
always @(posedge serial_clock or negedge reset_l) begin
if (~reset_l) begin
master_state <= idle;
slave_state <= idle;
master_counter <= 'b0;
// slave_core <= 1'b0;
end
else begin
master_counter <= master_counter + 1;
case (master_state)
idle : begin
// slave_core <= 1'b0;
data_out <= 1'b1;
if (port_tran_si == 1'b1 && master_counter[9]) master_state <= test_high;
else if (port_tran_si == 1'b1 && ~master_counter[9]) master_state <= test_low;
else if (port_tran_si == 1'b0) master_state <= idle;
end
test_high : begin
data_out <= 1'b1;
if (port_tran_si == 1'b1 && ~master_counter[9]) master_state <= test_low;
else if (port_tran_si == 1'b1 && master_counter[9]) master_state <= test_high;
else if (port_tran_si == 1'b0 && ~master_counter[9]) master_state <= test_low;
else if (port_tran_si == 1'b0 && master_counter[9]) master_state <= master_idle;
end
test_low : begin
data_out <= 1'b0;
if (port_tran_si == 1'b1 && ~master_counter[9]) master_state <= test_low;
else if (port_tran_si == 1'b1 && master_counter[9]) master_state <= test_high;
else if (port_tran_si == 1'b0 && ~master_counter[9]) master_state <= test_low;
else if (port_tran_si == 1'b0 && master_counter[9]) master_state <= master_idle;
end
test_check : begin
end
master_idle : begin
end
master_start_h : begin
end
master_start_l : begin
end
master_high_h : begin
end
master_high_l : begin
end
master_low_h : begin
end
master_low_l : begin
end
slave_idle : begin
end
slave_start_h : begin
end
slave_start_l : begin
end
slave_high_h : begin
end
slave_high_l : begin
end
slave_low_h : begin
end
slave_low_l : begin
end
default : begin
end
endcase
end
end
endmodule |
module i2s_audio (
input clk_74a,
input [15:0] left_audio,
input [15:0] right_audio,
output audio_mclk,
output audio_dac,
output audio_lrck
);
assign audio_mclk = audgen_mclk;
assign audio_dac = audgen_dac;
assign audio_lrck = audgen_lrck;
reg audgen_nextsamp;
// generate MCLK = 12.288mhz with fractional accumulator
reg [21:0] audgen_accum;
reg audgen_mclk;
parameter [20:0] CYCLE_48KHZ = 21'd122880 * 2;//21'd122880 * 2;
always @(posedge clk_74a) begin
audgen_accum <= audgen_accum + CYCLE_48KHZ;
if(audgen_accum >= 21'd742500) begin
audgen_mclk <= ~audgen_mclk;
audgen_accum <= audgen_accum - 21'd742500 + CYCLE_48KHZ;
end
end
// generate SCLK = 3.072mhz by dividing MCLK by 4
reg [1:0] aud_mclk_divider;
wire audgen_sclk = aud_mclk_divider[1] /* synthesis keep*/;
reg audgen_lrck_1;
always @(posedge audgen_mclk) begin
aud_mclk_divider <= aud_mclk_divider + 1'b1;
// rising edge
if(audgen_lrck & ~audgen_lrck_1) begin
//aud_mclk_divider <= 1;
end
end
// shift out audio data as I2S
// 32 total bits per channel, but only 16 active bits at the start and then 16 dummy bits
//
// synchronize audio samples coming from the ram readout
wire [31:0] audgen_sampdata_s;
synch_3 #(.WIDTH(32)) s5({left_audio, right_audio}, audgen_sampdata_s, audgen_sclk);
//reg [31:0] audgen_sampdata = 32'hF0008000;
reg [31:0] audgen_sampshift;
reg [4:0] audgen_lrck_cnt;
reg audgen_lrck;
reg audgen_dac;
always @(negedge audgen_sclk) begin
audgen_nextsamp <= 0;
// output the next bit
audgen_dac <= audgen_sampshift[31];
// 48khz * 64
audgen_lrck_cnt <= audgen_lrck_cnt + 1'b1;
if(audgen_lrck_cnt == 31) begin
// switch channels
audgen_lrck <= ~audgen_lrck;
if(audgen_lrck) begin
// load new sample
audgen_nextsamp <= 1;
// RIFF wave data is stored as 16bit little endian signed, so byteswap 16-bit
audgen_sampshift <= {audgen_sampdata_s[23:16], audgen_sampdata_s[31:24], audgen_sampdata_s[7:0], audgen_sampdata_s[15:8]};
end
end else begin
// only shift for 16 clocks per channel
if(audgen_lrck_cnt < 16) begin
audgen_sampshift <= {audgen_sampshift[30:0], 1'b0};
end
end
end
endmodule |
module core_bridge_cmd (
input wire clk,
output reg reset_n,
input wire bridge_endian_little,
input wire [31:0] bridge_addr,
input wire bridge_rd,
output reg [31:0] bridge_rd_data,
input wire bridge_wr,
input wire [31:0] bridge_wr_data,
// all these signals should be synchronous to clk
// add synchronizers if these need to be used in other clock domains
input wire status_boot_done, // assert when PLLs lock and logic is ready
input wire status_setup_done, // assert when core is happy with what's been loaded into it
input wire status_running, // assert when pocket's taken core out of reset and is running
output reg dataslot_requestread,
output reg [15:0] dataslot_requestread_id,
input wire dataslot_requestread_ack,
input wire dataslot_requestread_ok,
output reg dataslot_requestwrite,
output reg [15:0] dataslot_requestwrite_id,
input wire dataslot_requestwrite_ack,
input wire dataslot_requestwrite_ok,
output reg dataslot_allcomplete,
input wire savestate_supported,
input wire [31:0] savestate_addr,
input wire [31:0] savestate_size,
input wire [31:0] savestate_maxloadsize,
output reg savestate_start, // core should detect rising edge on this,
input wire savestate_start_ack, // and then assert ack for at least 1 cycle
input wire savestate_start_busy, // assert constantly while in progress after ack
input wire savestate_start_ok, // assert continuously when done, and clear when new process is started
input wire savestate_start_err, // assert continuously on error, and clear when new process is started
output reg savestate_load,
input wire savestate_load_ack,
input wire savestate_load_busy,
input wire savestate_load_ok,
input wire savestate_load_err,
input wire [9:0] datatable_addr,
input wire datatable_wren,
input wire [31:0] datatable_data,
output wire [31:0] datatable_q
);
// handle endianness
reg [31:0] bridge_wr_data_in;
reg [31:0] bridge_rd_data_out;
wire endian_little_s;
synch_3 s01(bridge_endian_little, endian_little_s, clk);
always @(*) begin
bridge_rd_data <= endian_little_s ? {
bridge_rd_data_out[7:0],
bridge_rd_data_out[15:8],
bridge_rd_data_out[23:16],
bridge_rd_data_out[31:24]
} : bridge_rd_data_out;
bridge_wr_data_in <= endian_little_s ? {
bridge_wr_data[7:0],
bridge_wr_data[15:8],
bridge_wr_data[23:16],
bridge_wr_data[31:24]
} : bridge_wr_data;
end
// minimalistic approach here -
// keep the commonly used registers in logic, but data table in BRAM.
// implementation could be changed quite a bit for a more advanced use case
// host
reg [31:0] host_0;
reg [31:0] host_4 = 'h20; // host cmd parameter data at 0x20
reg [31:0] host_8 = 'h40; // host cmd response data at 0x40
reg [31:0] host_20; // parameter data
reg [31:0] host_24;
reg [31:0] host_28;
reg [31:0] host_2C;
reg [31:0] host_40; // response data
reg [31:0] host_44;
reg [31:0] host_48;
reg [31:0] host_4C;
reg host_cmd_start;
reg [15:0] host_cmd_startval;
reg [15:0] host_cmd;
reg [15:0] host_resultcode;
localparam [3:0] ST_IDLE = 'd0;
localparam [3:0] ST_PARSE = 'd1;
localparam [3:0] ST_WORK = 'd2;
localparam [3:0] ST_DONE_OK = 'd13;
localparam [3:0] ST_DONE_CODE = 'd14;
localparam [3:0] ST_DONE_ERR = 'd15;
reg [3:0] hstate;
// target
reg [31:0] target_0;
reg [31:0] target_4 = 'h20;
reg [31:0] target_8 = 'h40;
reg [31:0] target_20; // parameter data
reg [31:0] target_24;
reg [31:0] target_28;
reg [31:0] target_2C;
reg [31:0] target_40; // response data
reg [31:0] target_44;
reg [31:0] target_48;
reg [31:0] target_4C;
localparam [3:0] TARG_ST_IDLE = 'd0;
localparam [3:0] TARG_ST_READYTORUN = 'd1;
localparam [3:0] TARG_ST_DISPMSG = 'd2;
localparam [3:0] TARG_ST_SLOTREAD = 'd3;
localparam [3:0] TARG_ST_SLOTRELOAD = 'd4;
localparam [3:0] TARG_ST_SLOTWRITE = 'd5;
localparam [3:0] TARG_ST_SLOTFLUSH = 'd6;
localparam [3:0] TARG_ST_WAITRESULT = 'd15;
reg [3:0] tstate;
reg status_setup_done_1;
reg status_setup_done_queue;
initial begin
reset_n <= 0;
dataslot_requestread <= 0;
dataslot_requestwrite <= 0;
dataslot_allcomplete <= 0;
savestate_start <= 0;
savestate_load <= 0;
status_setup_done_queue <= 0;
end
always @(posedge clk) begin
// detect a rising edge on the input signal
// and flag a queue that will be cleared later
status_setup_done_1 <= status_setup_done;
if(status_setup_done & ~status_setup_done_1) begin
status_setup_done_queue <= 1;
end
b_datatable_wren <= 0;
b_datatable_addr <= bridge_addr >> 2;
if(bridge_wr) begin
casex(bridge_addr)
32'hF8xx00xx: begin
case(bridge_addr[7:0])
8'h0: begin
host_0 <= bridge_wr_data_in; // command/status
// check for command
if(bridge_wr_data_in[31:16] == 16'h434D) begin
// host wants us to do a command
host_cmd_startval <= bridge_wr_data_in[15:0];
host_cmd_start <= 1;
end
end
8'h20: host_20 <= bridge_wr_data_in; // parameter data regs
8'h24: host_24 <= bridge_wr_data_in;
8'h28: host_28 <= bridge_wr_data_in;
8'h2C: host_2C <= bridge_wr_data_in;
endcase
end
32'hF8xx10xx: begin
case(bridge_addr[7:0])
8'h0: target_0 <= bridge_wr_data_in; // command/status
8'h4: target_4 <= bridge_wr_data_in; // parameter data pointer
8'h8: target_8 <= bridge_wr_data_in; // response data pointer
8'h40: target_40 <= bridge_wr_data_in; // response data regs
8'h44: target_44 <= bridge_wr_data_in;
8'h48: target_48 <= bridge_wr_data_in;
8'h4C: target_4C <= bridge_wr_data_in;
endcase
end
32'hF8xx2xxx: begin
b_datatable_wren <= 1;
end
endcase
end
if(bridge_rd) begin
casex(bridge_addr)
32'hF8xx00xx: begin
case(bridge_addr[7:0])
8'h0: bridge_rd_data_out <= host_0; // command/status
8'h4: bridge_rd_data_out <= host_4; // parameter data pointer
8'h8: bridge_rd_data_out <= host_8; // response data pointer
8'h40: bridge_rd_data_out <= host_40; // response data regs
8'h44: bridge_rd_data_out <= host_44;
8'h48: bridge_rd_data_out <= host_48;
8'h4C: bridge_rd_data_out <= host_4C;
endcase
end
32'hF8xx10xx: begin
case(bridge_addr[7:0])
8'h0: bridge_rd_data_out <= target_0;
8'h4: bridge_rd_data_out <= target_4;
8'h8: bridge_rd_data_out <= target_8;
8'h20: bridge_rd_data_out <= target_20; // parameter data regs
8'h24: bridge_rd_data_out <= target_24;
8'h28: bridge_rd_data_out <= target_28;
8'h2C: bridge_rd_data_out <= target_2C;
endcase
end
32'hF8xx2xxx: begin
bridge_rd_data_out <= b_datatable_q;
end
endcase
end
// host > target command executer
case(hstate)
ST_IDLE: begin
dataslot_requestread <= 0;
dataslot_requestwrite <= 0;
savestate_start <= 0;
savestate_load <= 0;
// there is no queueing. pocket will always make sure any outstanding host
// commands are finished before starting another
if(host_cmd_start) begin
host_cmd_start <= 0;
// save the command in case it gets clobbered later
host_cmd <= host_cmd_startval;
hstate <= ST_PARSE;
end
end
ST_PARSE: begin
// overwrite command semaphore with busy flag
host_0 <= {16'h4255, host_cmd};
case(host_cmd)
16'h0000: begin
// Request Status
host_resultcode <= 1; // default: booting
if(status_boot_done) begin
host_resultcode <= 2; // setup
if(status_setup_done) begin
host_resultcode <= 3; // idle
end else if(status_running) begin
host_resultcode <= 4; // running
end
end
hstate <= ST_DONE_CODE;
end
16'h0010: begin
// Reset Enter
reset_n <= 0;
hstate <= ST_DONE_OK;
end
16'h0011: begin
// Reset Exit
reset_n <= 1;
hstate <= ST_DONE_OK;
end
16'h0080: begin
// Data slot request read
dataslot_requestread <= 1;
dataslot_requestread_id <= host_20[15:0];
if(dataslot_requestread_ack) begin
host_resultcode <= 0;
if(!dataslot_requestread_ok) host_resultcode <= 2;
hstate <= ST_DONE_CODE;
end
end
16'h0082: begin
// Data slot request write
dataslot_requestwrite <= 1;
dataslot_requestwrite_id <= host_20[15:0];
if(dataslot_requestwrite_ack) begin
host_resultcode <= 0;
if(!dataslot_requestwrite_ok) host_resultcode <= 2;
hstate <= ST_DONE_CODE;
end
end
16'h008F: begin
// Data slot access all complete
dataslot_allcomplete <= 1;
hstate <= ST_DONE_OK;
end
16'h00A0: begin
// Savestate: Start/Query
host_40 <= savestate_supported;
host_44 <= savestate_addr;
host_48 <= savestate_size;
host_resultcode <= 0;
if(savestate_start_busy) host_resultcode <= 1;
if(savestate_start_ok) host_resultcode <= 2;
if(savestate_start_err) host_resultcode <= 3;
if(host_20[0]) begin
// Request Start!
savestate_start <= 1;
// stay in this state until ack'd
if(savestate_start_ack) begin
hstate <= ST_DONE_CODE;
end
end else begin
hstate <= ST_DONE_CODE;
end
end
16'h00A4: begin
// Savestate: Load/Query
host_40 <= savestate_supported;
host_44 <= savestate_addr;
host_48 <= savestate_maxloadsize;
host_resultcode <= 0;
if(savestate_load_busy) host_resultcode <= 1;
if(savestate_load_ok) host_resultcode <= 2;
if(savestate_load_err) host_resultcode <= 3;
if(host_20[0]) begin
// Request Load!
savestate_load <= 1;
// stay in this state until ack'd
if(savestate_load_ack) begin
hstate <= ST_DONE_CODE;
end
end else begin
hstate <= ST_DONE_CODE;
end
end
default: begin
hstate <= ST_DONE_ERR;
end
endcase
end
ST_WORK: begin
hstate <= ST_IDLE;
end
ST_DONE_OK: begin
host_0 <= 32'h4F4B0000; // result code 0
hstate <= ST_IDLE;
end
ST_DONE_CODE: begin
host_0 <= {16'h4F4B, host_resultcode};
hstate <= ST_IDLE;
end
ST_DONE_ERR: begin
host_0 <= 32'h4F4BFFFF; // result code FFFF = unknown command
hstate <= ST_IDLE;
end
endcase
// target > host command executer
case(tstate)
TARG_ST_IDLE: begin
if(status_setup_done_queue) begin
status_setup_done_queue <= 0;
tstate <= TARG_ST_READYTORUN;
end
end
TARG_ST_READYTORUN: begin
target_0 <= 32'h636D_0140;
tstate <= TARG_ST_WAITRESULT;
end
TARG_ST_WAITRESULT: begin
if(target_0[31:16] == 16'h6F6B) begin
// done
tstate <= TARG_ST_IDLE;
end
end
endcase
end
wire [31:0] b_datatable_q;
reg [9:0] b_datatable_addr;
reg b_datatable_wren;
//mf_datatable idt (
// .address_a ( datatable_addr ),
// .address_b ( b_datatable_addr ),
// .clock_a ( clk ),
// .clock_b ( clk ),
// .data_a ( datatable_data ),
// .data_b ( bridge_wr_data_in ),
// .wren_a ( datatable_wren ),
// .wren_b ( b_datatable_wren ),
// .q_a ( datatable_q ),
// .q_b ( b_datatable_q )
//);
endmodule |
module cpu (
input clk, /* CPU clock input, 50 MHz */
input rst, /* Reset signal, if high reset CPU */
/* Main memory connections */
output reg [11:0] MEM_ADDR, /* Address bus - memory address register */
input [17:0] DI, /* Data input */
output reg [17:0] MEM_BUFF, /* Data output - memory data buffer register */
output reg WRITE_ENABLE, /* Write enable register */
/* Outputs to console */
output reg [17:0] AC, /* Accumulator */
output reg [17:0] IO, /* Input Output register */
output reg [11:0] PC, /* Program counter */
output reg [17:0] IR,
output reg [7:0] IOSTA,
output wire [31:0] BUS_out, /* Multiplex various flags for console blinkenlights output */
/* Load_state */
input [17:0] AC_IN, /* Accumulator */
input [17:0] IO_IN, /* Input Output register */
input [11:0] PC_IN, /* Program counter */
input [17:0] IR_IN,
input [17:0] MEM_BUFF_IN, /* Data output - memory data buffer register */
input [11:0] MEM_ADDR_IN,
input [7:0] IOSTA_IN,
input load_state, /* Load regs from state */
/* Input controllers */
input [17:0] gamepad_in, /* Input for spacewar, goes to IO register (4 LSB and 4 MSB bits act as buttons) */
/* Output to Type 30 CRT */
output wire [9:0] pixel_x_out, /* Current column of pixel to write */
output wire [9:0] pixel_y_out, /* In what row the pixel should be written */
output reg [2:0] pixel_brightness, /* Brightness, levels: 4= -3, 5= -2, 6= -1, 7= -0, 0= 0, 1= +1, 2= +2, 3= +3 */
output reg pixel_shift_out, /* Signal to CRT that a pixel is to be written */
output reg halt, /* Signal that the CPU is halted */
/* Typewriter controls */
output [6:0] typewriter_char_out, /* Character to be output to teletype emulation */
output reg typewriter_strobe_out, /* Indicate that the character is ready to be written */
input [5:0] typewriter_char_in, /* Character sent from the keyboard module (teletype) to the CPU */
input typewriter_strobe_in, /* Indicator that there is a key pressed / new character to be read */
output reg typewriter_strobe_ack, /* Signal the keyboard module (i.e. teletype input) that the character is read by the CPU */
/* Paper tape connections */
output reg send_next_tape_char, /* Signal the paper tape reader that it's OK to send another character */
input is_char_available, /* Indicates when there is something to be read from the paper tape input word */
input [17:0] tape_rcv_word, /* Word (18-bit) received from paper tape in binary mode (rpb instruction) */
input [11:0] start_address, /* Address to start running the program from, that's where the JMP instruction from RIM points to */
/* CPU configuration */
input cpu_running, /* If false, well ... cpu is not running! */
input hw_mul_enabled, /* If true, hardware mul/div instructions are used, else mus/dis. Originally a switch in the PDP1 cabinet. */
input crt_wait, /* If true, when doing iot to crt device, respect wait specificed by bits 5 and 6 (12 and 11). */
/* Console switches input */
input [10:0] console_switches, /* Commands (start/stop/continue/examine etc) */
input [17:0] test_word, /* Test word switches (1-18) */
input [17:0] test_address, /* Test address switches (1-12) + extension if implemented */
input [5:0] sense_switches /* Sense switches (1-6) */
);
/* Since 50 MHz is much faster than original CPU, we can be quite generous with the clock cycles.
There is a 250 cycle gap between read_instr_register and read_data_bus which we can simply skip
if the instruction lasts 5 us instead of 10. */
`define start_button console_switches[0]
`define stop_button console_switches[1]
`define continue_button console_switches[2]
`define examine_button console_switches[3]
`define deposit_button console_switches[4]
`define readin_button console_switches[5]
`define reader_button console_switches[6]
`define tapefeed_button console_switches[7]
`define single_inst_switch console_switches[8]
`define single_step_switch console_switches[9]
`define power_switch console_switches[10]
parameter
poweron_state = 8'd0,
initial_state = 8'd4,
read_program_counter = 8'd8,
read_instruction_register = 8'd12,
read_data_bus = 8'd16,
get_effective_address = 8'd25,
execute = 8'd35,
check_instruction_duration = 8'd38,
flush_to_ram = 8'd39,
cleanup = 8'd40;
/* Instructions, opcodes */
parameter
i_and = 5'o1, i_ior = 5'o2, i_xor = 5'o3, i_xct = 5'o4,
i_cal = 5'o7, i_jda = 5'o7, i_lac = 5'o10, i_lio = 5'o11,
i_dac = 5'o12, i_dap = 5'o13, i_dip = 5'o14, i_dio = 5'o15,
i_dzm = 5'o16, i_add = 5'o20, i_sub = 5'o21, i_idx = 5'o22,
i_isp = 5'o23, i_sad = 5'o24, i_sas = 5'o25, i_mu_ = 5'o26,
i_di_ = 5'o27, i_jmp = 5'o30, i_jsp = 5'o31, i_skp = 5'o32,
i_shift = 5'o33, i_law = 5'o34, i_iot = 5'o35, i_opr = 5'o37;
/* Input-output device address list */
parameter
display_crt = 6'd7,
read_gamepad = 6'd9,
read_punched_tape_alpha = 6'd1,
read_punched_tape_binary = 6'd2,
read_reader_buffer = 6'd24,
type_out = 6'd3,
type_in = 6'd4,
cks_iosta_check = 6'd27;
////////////////// REGISTERS ////////////////////
reg [17:0] PREV_IR; /* Instruction Register, previous instruction register */
reg [6:0] PF = 7'b0; /* Program Flags, 1-6 are used, flag 0 exists simply to avoid handling it as a special case */
reg [7:0] cpu_state; /* Implement CPU as a State Machine, specify state the CPU is currently in. Implemented as a sequencer */
reg [11:0] waste_cycles; /* When non-zero, this will be decremented instead of executing anything by the CPU. Used for exact timing of instructions */
//reg [6:0] IOSTA = 7'b0000100; /* Stats of various IO devices, read by cks instruction (72 0033). Bit 2 is initially 1, otherwise it would never write anything out. */
reg [4:0] i = 5'b0; /* Helper register */
reg [3:0] num_shift = 4'b0; /* Number of shifts in sft instruction */
reg [5:0] typewriter_buffer; /* Stores incoming character from teletype emulation */
reg [0:0] old_typewriter_strobe_in, prev_continue_button; /* Registers used in positive edge detection */
reg [0:0] OV, CARRY, SKIP_FLAG, SKIP_REST_OF_INSTR, DIFFERENT_SIGNS; /* Various flags, SKIP_REST_OF_INSTR will skip all phases until cpu_state rolls over */
reg [33:0] division_quotient; /* Store results from the lpm_divide component */
reg [16:0] division_remainder;
////////////////// FUNCTIONS ////////////////////
function automatic [17:0] fix_zero; /* 1's complement is used, and two representations of zero exist. This converts -0 to +0 (all ones to all zeros). */
input [17:0] number;
fix_zero = (number == 18'h3ffff) ? 18'b0 : number;
endfunction
function automatic [17:0] abs; /* MSB bit set means the number is negative. If so, invert all the bits to make it positive (absolute value function). */
input [17:0] number;
abs = (number[17]) ? ~number : number;
endfunction
function automatic [16:0] abs_nosign; /* Like the abs function, but removes the sign bit. */
input [17:0] number;
abs_nosign = (number[17]) ? ~number[16:0]: number[16:0];
endfunction
//////////////////// WIRES //////////////////////
wire [33:0] multiply_result;
wire [33:0] division_quotient_w;
wire [16:0] division_remainder_w;
wire [33:0] multiply_input;
wire [16:0] denominator;
/////////////////// MODULES /////////////////////
pdp1_cpu_alu_div divider(
.in_clock(clk),
.numer(multiply_input),
.denom(denominator),
.quotient(division_quotient_w),
.remain(division_remainder_w)
);
//////////////////// TASKS //////////////////////
task reset_cpu;
begin
PC <= start_address;
AC <= 18'b0;
IO <= 18'b0;
MEM_BUFF <= 18'b0;
MEM_ADDR <= 12'b0;
IR <= 18'b0;
IOSTA <= 7'b0000100;
{PF, OV, cpu_state, halt, WRITE_ENABLE} <= 19'b0;
end
endtask
task execute_instruction;
input [4:0] opcode;
input [0:0] indirect_addr;
input [17:0] instruction;
input [17:0] operand;
reg [5:0] sense_switches_select;
begin
PREV_IR <= IR;
/* The memory reference format is:
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
| op |in| address | memory reference
+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
<0:4> <5> mnemonic action */
case (opcode) /* Instruction Code # Op.Time (us) Explanation */
i_and: AC <= AC & DI; /* and Y 02 10 Add C(Y) to C(AC) */
i_ior: AC <= AC | DI; /* ior Y 04 10 Inclusive OR C(Y) with C(AC) */
i_xor: AC <= AC ^ DI; /* xor Y 06 10 Exclusive OR C(Y) with C(AC) */
i_lac: AC <= DI; /* lac Y 20 10 Load the AC with C(Y) */
i_lio: IO <= DI; /* lio Y 22 10 Load IO with C(Y) */
i_sad: PC <= PC + (AC != DI); /* sad Y 50 10 Skip next instruction if C(AC) != C(Y) */
i_sas: PC <= PC + (AC == DI); /* sas Y 52 10 Skip next instruction if C(AC) == C(Y) */
i_xct: { IR, MEM_BUFF } <= { 2{DI} }; /* xct Y 10 5 + extra Perform instruction in Y */
i_cal, /* cal Y 16 10 Equals JDA 100 */
i_jda: /* jda Y 17 10 Equals dac Y and jsp Y + 1 */
begin
MEM_BUFF <= AC;
{ MEM_ADDR, PC } <= { 2{ instruction[12] ? operand[11:0] : 12'o100 } };
AC <= (OV << 17) + PC + 1'b1;
end
i_law: /* law N 70 5 Load the AC with the number N */
AC <= IR[12] ? ~{6'b0, IR[11:0]} : IR[11:0];
/* Memory write instructions */
/* --------------------------------------------------------------------------------------------------------------------------------------------------- */
i_dac: MEM_BUFF <= AC; /* dac Y, 24, 10, Put C(AC) in Y */
i_dap: MEM_BUFF <= { DI[17:12], AC[11:0] }; /* dap Y, 26, 10, Put contents of address part of AC in Y */
i_dip: MEM_BUFF[17:12] <= AC[17:12]; /* dip Y, 30, 10, Put contents of instruction part of AC in Y */
i_dio: MEM_BUFF <= IO; /* dio Y, 32, 10, Put C(IO) in Y */
i_dzm: MEM_BUFF <= 0; /* dzm Y, 34, 10, Make C(Y) zero */
i_add: /* add Y, 40, 10, Add C(Y) to C(AC */
begin
DIFFERENT_SIGNS = AC[17] ^ DI[17];
{CARRY, AC} = AC + DI;
AC = fix_zero(AC + CARRY);
/* If signs were equal before the addition and now they are not, signal overflow */
if (DIFFERENT_SIGNS == 0 && (DI[17] != AC[17]))
OV = 1;
end
i_sub: /* sub Y 42 10 Subtract C(Y) from C(AC) */
begin
DIFFERENT_SIGNS = AC[17] ^ DI[17];
{CARRY, AC} = AC + (~DI);
AC = fix_zero(AC + !CARRY);
/* If signs were opposite before the subtraction and now they are not, signal overflow */
if (DIFFERENT_SIGNS && (DI[17] == AC[17]))
OV = 1;
end
i_idx, /* idx Y 44 10 Index (add one) C(Y) leave in Y & AC */
i_isp: /* isp Y 46 10 Index and skip if result is positive */
begin
{ MEM_BUFF, AC } <= {2{fix_zero(DI + 1)}};
if (opcode == i_isp && (fix_zero(DI + 1'b1) & 18'o400000) == 12'b0)
PC <= (PREV_IR[17:13] == i_xct) ? PREV_IR[11:0] + 1'b1 : PC + 1'b1; /* Edge-case, if previous opcode was XCT, PC is the corresponding y + 1 */
end
/* Hardware multiply */
i_mu_:
if (hw_mul_enabled) /* mul Y 54 max 25 Multiply, hardware multiply enabled */
begin
DIFFERENT_SIGNS = AC[17] ^ DI[17];
/* Negative times negative is positive, also fix zero for a 34-bit wide result */
if (DIFFERENT_SIGNS && (&multiply_result))
{AC, IO} <= 36'h0;
else
{AC, IO} <= {DIFFERENT_SIGNS, DIFFERENT_SIGNS ? ~multiply_result : multiply_result, DIFFERENT_SIGNS};
end
else /* mus Y 54 10 Multiply step, hardware multiply disabled */
begin
if (IO[0]) begin
{CARRY, AC} = AC + DI;
AC = fix_zero(AC + CARRY);
end
IO = { AC[0], IO[17:1] };
AC = AC >> 1;
end
i_di_:
/* div instruction, hardware divide enabled */
if (hw_mul_enabled) /* div Y 56 max 40 Divide, hardware division enabled */
begin
DIFFERENT_SIGNS = AC[17] ^ DI[17];
if (abs_nosign(AC) < abs_nosign(DI)) /* Only if not overflow */
begin
IO <= fix_zero( AC[17] ? { 1'b1, ~division_remainder_w[16:0]} : {1'b0, division_remainder_w[16:0]});
case ({AC[17], DI[17], division_quotient_w[17]})
3'b000, 3'b110: AC <= fix_zero({ 1'b0, division_quotient_w[16:0] });
3'b001, 3'b111: AC <= fix_zero({ 1'b0, ~division_quotient_w[16:0] });
3'b010, 3'b100: AC <= fix_zero({ 1'b1, ~division_quotient_w[16:0] });
3'b101, 3'b011: AC <= fix_zero({ 1'b1, division_quotient_w[16:0] });
endcase
PC <= PC + 1'b1;
end
else
OV <= 1'b1;
end
else
/* dis instruction, hardware divide disabled */
begin /* dis Y 56 10 Divide, hardware division disabled */
{AC, IO} = { AC[16:0], IO, AC[17] ^ 1'b1};
{CARRY, AC} = (IO[0] ? AC + (~DI) : AC + DI + 1'b1);
AC = fix_zero(AC + (CARRY ^ IO[0]));
end
/* ---------------------------------------------------------------------------------------------------------------------------------------------------
The I/O transfer format is:
17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
| 1 1 1 0 1| W| C| subopcode | device | I/O transfer
+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
*/
i_iot:
begin
case (operand[5:0]) /* device */
display_crt:
begin
pixel_shift_out <= 1'b1;
pixel_brightness <= DI[8:6];
end
read_gamepad:
IO <= gamepad_in;
read_reader_buffer,
read_punched_tape_binary:
begin
if (is_char_available)
begin
send_next_tape_char <= 1'b1;
IO <= tape_rcv_word;
end
else
cpu_state <= cpu_state - 4'd10;
end
type_out:
begin
IOSTA[2] <= 1'b1; /* Set to 0 at the start of each tyo instruction, back to 1 when typewriter free to receive tyo again */
/* Until artificial slow-down is implemented, typewriter is always available so IOSTA[2] can be pulled high */
typewriter_strobe_out <= 1'b1;
end
type_in:
begin
IO <= {11'b0, ~IOSTA[3], typewriter_buffer};
IOSTA[3] <= 1'b0; /* Set to 0 by completion of tyi instruction */
/* Set to 1 when typewriter key struck */
typewriter_strobe_ack <= 1'b1;
end
cks_iosta_check:
IO[17:12] <= { IOSTA[0], IOSTA[1], IOSTA[2], IOSTA[3], IOSTA[4], IOSTA[5] };
endcase
end
/* ---------------------------------------------------------------------------------------------------------------------------------------------------
skp Y, opcode 64, duration 5 us, Skip instruction
17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
+-----------------+--+--+--+--+--+--+--+--+--+--+--+--+
| 1 1 0 1 0| | | | | | | | | | | | | |
+-----------------+--+--+--+--+--+--+--+--+--+--+--+--+
| | | | | | \______/ \______/
| | | | | | | |
| | | | | | | +---- Program Flags (szs)
| | | | | | +------------- Sense Switches (szf)
| | | | | +------------------- AC = 0 (sza)
| | | | +---------------------- AC >= 0 (spa)
| | | +------------------------- AC < 0 (sma)
| | +---------------------------- OV = 0 (szo)
| +------------------------------- IO >= 0 (spi)
+------------------------------------- invert skip
*/
i_skp:
begin
sense_switches_select = sense_switches >> instruction[5:3] - 1;
SKIP_FLAG = (
(instruction[6] && AC == 0) /* Skip on ZERO Accumulator (sza) */
|| (instruction[7] && AC[17] == 0) /* Skip on Plus Accumulator (spa) */
|| (instruction[8] && AC[17] == 1) /* Skip on Minus Accumulator (sma) */
|| (instruction[9] && OV == 0) /* Skip on ZERO Overflow (szo) */
|| (instruction[10] && IO[17] == 0) /* Skip on Plus In-Out Register (spi) */
|| (|instruction[2:0] && ~&instruction[2:0] && PF[instruction[2:0]] == 0) /* Skip on ZERO Program Flag (szf) */
|| (instruction[2:0] == 3'b111 && PF == 0) /* Skip on ZERO Program Flag all (szf) */
|| ( |instruction[5:3] &&
~&instruction[5:3] &&
sense_switches_select[0] == 0)
//((sense_switches[instruction[5:3]]) == 0)) /* Skip on ZERO Switch addr 1-6 (szs) */
|| (instruction[5:3] == 3'b111 && sense_switches == 0) /* Skip on ZERO Switch addr 7 (szs) */
);
if (instruction[12] ^ SKIP_FLAG) /* If 6-th bit (DEC notation) is 1 and skip flag 0, or vice-versa */
PC <= (PREV_IR[17:13] == i_xct) ? PREV_IR[11:0] + 1'b1 : PC + 1'b1; /* Edge-case, if previous opcode was XCT, PC is the corresponding y + 1 */
if (operand[9])
OV <= 0;
end
/* ---------------------------------------------------------------------------------------------------------------------------------------------------
sft Y 66 5 Shift instructions
The shift format is:
17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
| 1 1 0 1 1| subopcode | encoded count | shift
+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+ */
i_shift:
begin
/* num_shift is the number of high bits in instruction word bits 9-17 (DEC notation) - encoded count */
num_shift = DI[8] + DI[7] + DI[6] + DI[5] + DI[4] + DI[3] + DI[2] + DI[1] + DI[0];
for (i=0; i<num_shift; i=i+1'b1)
begin
case (operand[17:9] & 9'o777)
9'o661: /* Rotate Accumulator Left (ral) */
AC = {AC[16:0], AC[17]};
9'o662: /* Rotate IO Left (ril) */
IO = {IO[16:0], IO[17]};
9'o663: /* Rotate AC and IO Left (rcl) */
{AC, IO} = { AC[16:0], IO, AC[17] };
9'o665: /* Shift Accumulator Left (sal) */
AC = { AC[17], AC[15:0], AC[17] };
9'o666: /* Shift In-Out Register Left (sil) */
IO = { IO[17], IO[15:0], IO[17] };
9'o667: /* Shift AC and IO Left (scl) */
{AC, IO} = {AC[17], AC[15:0], IO, AC[17]};
9'o671: /* Rotate Accumulator Right (rar) */
AC = {AC[0], AC[17:1]};
9'o672: /* Rotate IO Right (rir) */
IO = {IO[0], IO[17:1]};
9'o673: /* Rotate AC and IO Right (rcr) */
{AC, IO} = { IO[0], AC, IO[17:1] };
9'o675: /* Shift Accumulator Right (sar) */
AC = { AC[17], AC[17:1] };
9'o676: /* Shift In-Out Register Right (sir) */
IO = { IO[17], IO[17:1] };
9'o677: /* Shift AC and IO Right (scr) */
{AC, IO} = {AC[17], AC[17:0], IO[17:1]};
endcase
end
end
/* The operate format:
17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
| 1 1 1 1 1| | | | | | | | | | | | | | operate
+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
| | | | | | | | | | \______/
| | | | | | | | | | |
| | | | | | | | | | +---- PF select
| | | | | | | | | +---------- clear/set PF
| | | | | | | | +------------- LIA (PDP-1D)
| | | | | | | +---------------- LAI (PDP-1D)
| | | | | | +------------------- or PC
| | | | | +---------------------- CLA
| | | | +------------------------- halt
| | | +---------------------------- CMA
| | +------------------------------- or TW
| +---------------------------------- CLI
+------------------------------------- CMI (PDP-1D) */
i_opr:
begin
if (DI[10] && DI[7]) AC <= test_word; /* Loads test word switches in Accumulator */
else if (DI[10] && !DI[7]) AC <= AC | test_word; /* OR test word switches with existing Accumulator value */
else if (DI[9] && DI[7]) AC <= 18'h3ffff; /* If both flags are set, we need to perform cla and cma operations (which make accumulator equal to 0x3ffff) */
else if (DI[7]) AC <= 0; /* Clear Accumulator (cla, Address 200, 5 uSec) */
else if (DI[9]) AC <= ~AC; /* Complement Accumulator (cma, Address 1000, 5 usec) */
if (DI[4]) IO <= AC; /* Load IO from Accumulator (lia, Address 20, 5 usec) */
if (DI[5]) AC <= IO; /* Load Accumulator from IO (lai, Address 40, 5 usec) */
/* Swap Accumulator and IO (swp, Address 40, 5 usec) - implemented simply by executing both of these ifs */
if (DI[11]) IO <= 0; /* Clear In-Out Register (cli, Address 4000, 5 usec) */
if (DI[8]) halt <= 1; /* Stops the computer, (hlt, Address 400) - temporarily disabled */
/* PF select, 1-7. 1-6 sets/clears individual flags, 7 does them all.
PF[0] exists simply to avoid handling it as a special case, it is not used */
if (operand[2:0] == 3'd7) /* Set and clear program flag (clf / stf) 5 usec */
PF = operand[3] ? 6'b111111 : 6'b000000 ; /* Address 07 clears / sets all program flags */
else
PF[operand[2:0]] = operand[3];
end
i_jmp: PC <= operand[11:0];
i_jsp:
begin
AC <= {OV, 5'b0, PC + 1'b1};
PC <= operand[11:0];
end
default:
SKIP_REST_OF_INSTR <= 1'b1;
endcase
end
endtask
///////////////// ASSIGNMENTS ///////////////////
assign denominator = (DI[17] ? (~(DI[16:0])) : DI[16:0]);
assign multiply_input = AC[17] ? { ~AC[16:0], ~IO[17:1] } : { AC[16:0], IO[17:1] };
assign multiply_result = abs_nosign(AC) * abs_nosign(DI);
assign pixel_x_out = IO[17:8] + 10'd512;
assign pixel_y_out = AC[17:8] + 10'd512;
assign typewriter_char_out = IO[5:0];
assign BUS_out[19:0] = { cpu_running, OV, IR[17:13], PF[6:1], sense_switches[5:0] };
///////////////// MAIN BLOCK ////////////////////
/* 50 MHz input clock = 20 ns period. Instructions last 5 or 10 uS (250 or 500 clocks), so we have time to spare. */
always @(posedge clk) begin
old_typewriter_strobe_in <= typewriter_strobe_in; /* Store old values for positive edge detection */
prev_continue_button <= `continue_button;
pixel_shift_out <= 1'b0;
/* If we are in single instruction mode, remain in initial_state until continue is pressed, then get stuck again in next initial_state */
if (cpu_state == initial_state && `single_inst_switch)
cpu_state <= (~prev_continue_button && `continue_button) ? cpu_state + 1'b1 : initial_state ;
else if (cpu_state == initial_state && waste_cycles) /* If non-zero, it will keep decrementing until zero rather than execute anything. Used to fine-tune instruction duration */
waste_cycles <= waste_cycles - 1'b1;
else if (cpu_state == cleanup + 1'b1) /* If skip rest of instruction flag active, this makes sure it overflows to initial state, not poweron state */
cpu_state <= initial_state;
else begin
if (cpu_running || (!cpu_running && cpu_state != initial_state)) cpu_state <= cpu_state + 1'b1;
end
/* Typewriter positive edge transition sets these registers, i.e. on every char received */
if (~old_typewriter_strobe_in && typewriter_strobe_in) begin
PF[1] = 1'b1;
IOSTA[3] <= 1'b1;
typewriter_buffer <= typewriter_char_in;
end
/* ************************************** */
if (rst) reset_cpu();
else if (load_state) begin
PC <= PC_IN;
AC <= AC_IN;
IO <= IO_IN;
MEM_ADDR <= MEM_ADDR_IN;
MEM_BUFF <= MEM_BUFF_IN; /* Data output - memory data buffer register */
IR <= IR_IN;
IOSTA <= IOSTA_IN;
end
else if (`start_button) /* Pressing start button puts address set by test address switches in program counter */
PC <= test_address[11:0];
// else if (~cpu_running) begin /* If CPU is stopped, enable reading and writing memory through console switches */
// WRITE_ENABLE <= `deposit_button;
// if (`deposit_button) begin
// MEM_ADDR <= test_address[11:0];
// MEM_BUFF <= test_word;
// end
//
// if (`examine_button)
// MEM_ADDR <= test_address[11:0];
// end
else if ( |{!SKIP_REST_OF_INSTR, cpu_running && cpu_state == initial_state}) /* Don't do any of this if SKIP_REST_OF_INSTR is set, except when we reach the next initial state */
begin
SKIP_REST_OF_INSTR <= 1'b0; /* Set this to false by default, set to true when needed */
case (cpu_state)
poweron_state: PC <= start_address;
read_program_counter: MEM_ADDR <= PC;
read_instruction_register: IR <= DI; /* Make sure the opcode remains in IR even after several cycles of indirect addressing */
read_data_bus: MEM_BUFF <= DI;
get_effective_address:
/* Check if we are processing instruction with memory addressing and get effective address in that case */
case (IR[17:13])
i_and, i_ior, i_xor, i_xct, i_lac, i_lio, i_dac,
i_dap, i_dip, i_dio, i_dzm, i_add, i_sub, i_idx,
i_isp, i_sad, i_sas, i_mu_, i_di_, i_jmp, i_jsp:
begin
MEM_ADDR <= MEM_BUFF[11:0];
/* If indirect addressing, go to 2 clocks before read_data_bus state after we set the
MEM_ADDR (address bus) so the memory value has enough time to be clocked onto the data bus.
If not, increment current microcode cycle counter and wait for it to reach execute. */
cpu_state <= (MEM_BUFF[12] == 1'b1) ? read_data_bus - 2'd2: cpu_state + 1'b1;
end
endcase
execute:
begin
execute_instruction(IR[17:13], IR[12], IR, MEM_BUFF); /* MEM_BUFF now contains memory[y] */
case (IR[17:13])
i_jmp, i_jsp: SKIP_REST_OF_INSTR <= 1'b1;
i_xct: cpu_state <= read_data_bus - 3'd8;
endcase
end
check_instruction_duration:
case (IR[17:13])
i_shift, i_jmp, i_law, i_xct, i_jsp, i_skp, i_opr:
waste_cycles <= 12'd0; /* Waste no cycles, these instructions last only 5 us */
i_mu_:
waste_cycles <= hw_mul_enabled ? 12'd1000 : 12'd0; /* Waste additional 1000 cycles * 20 ns = +20 us if hw mul enabled, otherwise +5 us */
i_di_:
waste_cycles <= hw_mul_enabled ? 12'd1750 : 12'd0; /* Waste additional 1750 cycles * 20 ns = +35 us if hw div enabled, otherwise +5 us */
i_iot:
waste_cycles <= ((MEM_BUFF[5:0] == display_crt)) ? /* Waste additional 2250 cycles * 20 ns = +45 us if writing to CRT, wait is specified and enabled in menu, otherwise +5 us */
12'd0 : 12'd0;
default:
waste_cycles <= 12'd0; /* Waste additional 250 cycles * 20 ns = +5 us */
endcase
flush_to_ram:
/* These opcodes need to write to memory, set WE high so the value gets written. */
case (IR[17:13])
i_dac, i_dap, i_dip, i_dio, i_dzm, i_idx, i_cal, i_jda, i_isp:
WRITE_ENABLE <= 1'b1;
endcase
cleanup:
begin
typewriter_strobe_ack <= 1'b0;
typewriter_strobe_out <= 1'b0;
send_next_tape_char <= 1'b0;
WRITE_ENABLE <= 1'b0;
PC <= PC + 1'b1;
cpu_state <= initial_state;
end
endcase
end
end
endmodule |
module pdp1_cpu_alu_div (
in_clock,
denom,
numer,
quotient,
remain);
input in_clock;
input [16:0] denom;
input [33:0] numer;
output [33:0] quotient;
output [16:0] remain;
wire [33:0] sub_wire0;
wire [16:0] sub_wire1;
wire [33:0] quotient = sub_wire0[33:0];
wire [16:0] remain = sub_wire1[16:0];
lpm_divide LPM_DIVIDE_component (
.denom (denom),
.numer (numer),
.quotient (sub_wire0),
.remain (sub_wire1),
.aclr (1'b0),
.clken (1'b1),
.clock (in_clock));
defparam
LPM_DIVIDE_component.lpm_drepresentation = "UNSIGNED",
LPM_DIVIDE_component.lpm_hint = "MAXIMIZE_SPEED=6,LPM_REMAINDERPOSITIVE=TRUE,LPM_PIPELINE=34",
LPM_DIVIDE_component.lpm_nrepresentation = "UNSIGNED",
LPM_DIVIDE_component.lpm_type = "LPM_DIVIDE",
LPM_DIVIDE_component.lpm_widthd = 17,
LPM_DIVIDE_component.lpm_widthn = 34;
endmodule |
module color_lut (
input read_clk,
input [7:0] input_index,
output reg [23:0] output_color,
input write_clk,
input [7:0] write_address,
input [23:0] write_data,
input write_enable
);
reg [23:0] mem [255:0];
always @(posedge read_clk) output_color <= mem[input_index];
always @(posedge write_clk) if (write_enable) mem[write_address] <= write_data;
endmodule |
module mf_pllbase_0002(
// interface 'refclk'
input wire refclk,
// interface 'reset'
input wire rst,
// interface 'outclk0'
output wire outclk_0,
// interface 'outclk1'
output wire outclk_1,
// interface 'locked'
output wire locked
);
altera_pll #(
.fractional_vco_multiplier("true"),
.reference_clock_frequency("74.25 MHz"),
.operation_mode("normal"),
.number_of_clocks(2),
.output_clock_frequency0("12.288000 MHz"),
.phase_shift0("0 ps"),
.duty_cycle0(50),
.output_clock_frequency1("12.288000 MHz"),
.phase_shift1("20345 ps"),
.duty_cycle1(50),
.output_clock_frequency2("0 MHz"),
.phase_shift2("0 ps"),
.duty_cycle2(50),
.output_clock_frequency3("0 MHz"),
.phase_shift3("0 ps"),
.duty_cycle3(50),
.output_clock_frequency4("0 MHz"),
.phase_shift4("0 ps"),
.duty_cycle4(50),
.output_clock_frequency5("0 MHz"),
.phase_shift5("0 ps"),
.duty_cycle5(50),
.output_clock_frequency6("0 MHz"),
.phase_shift6("0 ps"),
.duty_cycle6(50),
.output_clock_frequency7("0 MHz"),
.phase_shift7("0 ps"),
.duty_cycle7(50),
.output_clock_frequency8("0 MHz"),
.phase_shift8("0 ps"),
.duty_cycle8(50),
.output_clock_frequency9("0 MHz"),
.phase_shift9("0 ps"),
.duty_cycle9(50),
.output_clock_frequency10("0 MHz"),
.phase_shift10("0 ps"),
.duty_cycle10(50),
.output_clock_frequency11("0 MHz"),
.phase_shift11("0 ps"),
.duty_cycle11(50),
.output_clock_frequency12("0 MHz"),
.phase_shift12("0 ps"),
.duty_cycle12(50),
.output_clock_frequency13("0 MHz"),
.phase_shift13("0 ps"),
.duty_cycle13(50),
.output_clock_frequency14("0 MHz"),
.phase_shift14("0 ps"),
.duty_cycle14(50),
.output_clock_frequency15("0 MHz"),
.phase_shift15("0 ps"),
.duty_cycle15(50),
.output_clock_frequency16("0 MHz"),
.phase_shift16("0 ps"),
.duty_cycle16(50),
.output_clock_frequency17("0 MHz"),
.phase_shift17("0 ps"),
.duty_cycle17(50),
.pll_type("General"),
.pll_subtype("General")
) altera_pll_i (
.rst (rst),
.outclk ({outclk_1, outclk_0}),
.locked (locked),
.fboutclk ( ),
.fbclk (1'b0),
.refclk (refclk)
);
endmodule |
module mprj_stimulus_tb;
// Signals declaration
reg clock;
reg RSTB;
reg power1, power2;
reg CSB;
wire gpio;
wire [37:0] mprj_io;
wire [15:0] checkbits;
wire [3:0] status;
// Signals Assignment
assign checkbits = mprj_io[31:16];
assign status = mprj_io[35:32];
assign mprj_io[3] = (CSB == 1'b1) ? 1'b1 : 1'bz;
always #12.5 clock <= (clock === 1'b0);
initial begin
clock = 0;
end
`ifdef ENABLE_SDF
initial begin
$sdf_annotate("../../../sdf/user_proj_example.sdf", uut.mprj.mprj) ;
$sdf_annotate("../../../mgmt_core_wrapper/sdf/DFFRAM.sdf", uut.soc.DFFRAM_0) ;
$sdf_annotate("../../../mgmt_core_wrapper/sdf/mgmt_core.sdf", uut.soc.core) ;
$sdf_annotate("../../../caravel/sdf/housekeeping.sdf", uut.housekeeping) ;
$sdf_annotate("../../../caravel/sdf/chip_io.sdf", uut.padframe) ;
$sdf_annotate("../../../caravel/sdf/mprj_logic_high.sdf", uut.mgmt_buffers.mprj_logic_high_inst) ;
$sdf_annotate("../../../caravel/sdf/mprj2_logic_high.sdf", uut.mgmt_buffers.mprj2_logic_high_inst) ;
$sdf_annotate("../../../caravel/sdf/mgmt_protect_hv.sdf", uut.mgmt_buffers.powergood_check) ;
$sdf_annotate("../../../caravel/sdf/mgmt_protect.sdf", uut.mgmt_buffers) ;
$sdf_annotate("../../../caravel/sdf/caravel_clocking.sdf", uut.clocking) ;
$sdf_annotate("../../../caravel/sdf/digital_pll.sdf", uut.pll) ;
$sdf_annotate("../../../caravel/sdf/xres_buf.sdf", uut.rstb_level) ;
$sdf_annotate("../../../caravel/sdf/user_id_programming.sdf", uut.user_id_value) ;
$sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_bidir_1[0] ) ;
$sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_bidir_1[1] ) ;
$sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_bidir_2[0] ) ;
$sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_bidir_2[1] ) ;
$sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_bidir_2[2] ) ;
$sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_1[0] ) ;
$sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_1[1] ) ;
$sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_1[2] ) ;
$sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_1[3] ) ;
$sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_1[4] ) ;
$sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_1[5] ) ;
$sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_1[6] ) ;
$sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_1[7] ) ;
$sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_1[8] ) ;
$sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_1[9] ) ;
$sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_1[10] ) ;
$sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_1a[0] ) ;
$sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_1a[1] ) ;
$sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_1a[2] ) ;
$sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_1a[3] ) ;
$sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_1a[4] ) ;
$sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_1a[5] ) ;
$sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_2[0] ) ;
$sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_2[1] ) ;
$sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_2[2] ) ;
$sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_2[3] ) ;
$sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_2[4] ) ;
$sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_2[5] ) ;
$sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_2[6] ) ;
$sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_2[7] ) ;
$sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_2[8] ) ;
$sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_2[9] ) ;
$sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_2[10] ) ;
$sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_2[11] ) ;
$sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_2[12] ) ;
$sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_2[13] ) ;
$sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_2[14] ) ;
$sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_2[15] ) ;
$sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.\gpio_defaults_block_0[0] ) ;
$sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.\gpio_defaults_block_0[1] ) ;
$sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.\gpio_defaults_block_2[0] ) ;
$sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.\gpio_defaults_block_2[1] ) ;
$sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.\gpio_defaults_block_2[2] ) ;
$sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_5) ;
$sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_6) ;
$sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_7) ;
$sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_8) ;
$sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_9) ;
$sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_10) ;
$sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_11) ;
$sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_12) ;
$sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_13) ;
$sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_14) ;
$sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_15) ;
$sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_16) ;
$sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_17) ;
$sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_18) ;
$sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_19) ;
$sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_20) ;
$sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_21) ;
$sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_22) ;
$sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_23) ;
$sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_24) ;
$sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_25) ;
$sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_26) ;
$sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_27) ;
$sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_28) ;
$sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_29) ;
$sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_30) ;
$sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_31) ;
$sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_32) ;
$sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_33) ;
$sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_34) ;
$sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_35) ;
$sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_36) ;
$sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_37) ;
end
`endif
initial begin
$dumpfile("mprj_stimulus.vcd");
$dumpvars(0, mprj_stimulus_tb);
// Repeat cycles of 1000 clock edges as needed to complete testbench
repeat (100) begin
repeat (1000) @(posedge clock);
end
$display("%c[1;31m",27);
`ifdef GL
$display ("Monitor: Timeout, Test Project IO Stimulus (GL) Failed");
`else
$display ("Monitor: Timeout, Test Project IO Stimulus (RTL) Failed");
`endif
$display("%c[0m",27);
$finish;
end
initial begin
wait(checkbits == 16'hAB40);
$display("Monitor: mprj_stimulus test started");
wait(status == 4'ha);
wait(status == 4'h5);
// Values reflect copying user-controlled outputs to memory and back
// to management-controlled outputs.
wait(checkbits == 16'h1968 || checkbits == 16'h1969 || checkbits == 16'h198B); // They're off because the difference between GL and RTL
wait(checkbits == 16'h1DCD || checkbits == 16'h1DCE || checkbits == 16'h1DE8); // They're off because the difference between GL and RTL
wait(checkbits == 16'hAB51);
$display("Monitor: mprj_stimulus test Passed");
#10000;
$finish;
end
// Reset Operation
initial begin
CSB <= 1'b1;
RSTB <= 1'b0;
#2000;
RSTB <= 1'b1; // Release reset
#1_300_000;
CSB <= 1'b0; // Stop driving CSB
end
initial begin // Power-up sequence
power1 <= 1'b0;
power2 <= 1'b0;
#200;
power1 <= 1'b1;
#200;
power2 <= 1'b1;
end
wire flash_csb;
wire flash_clk;
wire flash_io0;
wire flash_io1;
wire VDD3V3 = power1;
wire VDD1V8 = power2;
wire VSS = 1'b0;
caravel uut (
.vddio (VDD3V3),
.vddio_2 (VDD3V3),
.vssio (VSS),
.vssio_2 (VSS),
.vdda (VDD3V3),
.vssa (VSS),
.vccd (VDD1V8),
.vssd (VSS),
.vdda1 (VDD3V3),
.vdda1_2 (VDD3V3),
.vdda2 (VDD3V3),
.vssa1 (VSS),
.vssa1_2 (VSS),
.vssa2 (VSS),
.vccd1 (VDD1V8),
.vccd2 (VDD1V8),
.vssd1 (VSS),
.vssd2 (VSS),
.clock (clock),
.gpio (gpio),
.mprj_io (mprj_io),
.flash_csb(flash_csb),
.flash_clk(flash_clk),
.flash_io0(flash_io0),
.flash_io1(flash_io1),
.resetb (RSTB)
);
spiflash #(
.FILENAME("mprj_stimulus.hex")
) spiflash (
.csb(flash_csb),
.clk(flash_clk),
.io0(flash_io0),
.io1(flash_io1),
.io2(), // not used
.io3() // not used
);
endmodule |
module wb_port_tb;
reg clock;
reg RSTB;
reg CSB;
reg power1, power2;
reg power3, power4;
wire gpio;
wire [37:0] mprj_io;
wire [7:0] mprj_io_0;
wire [15:0] checkbits;
assign checkbits = mprj_io[31:16];
assign mprj_io[3] = 1'b1;
// External clock is used by default. Make this artificially fast for the
// simulation. Normally this would be a slow clock and the digital PLL
// would be the fast clock.
always #12.5 clock <= (clock === 1'b0);
initial begin
clock = 0;
end
`ifdef ENABLE_SDF
initial begin
$sdf_annotate("../../../sdf/user_proj_example.sdf", uut.mprj) ;
$sdf_annotate("../../../sdf/user_project_wrapper.sdf", uut.mprj.mprj) ;
$sdf_annotate("../../../mgmt_core_wrapper/sdf/DFFRAM.sdf", uut.soc.DFFRAM_0) ;
$sdf_annotate("../../../mgmt_core_wrapper/sdf/mgmt_core.sdf", uut.soc.core) ;
$sdf_annotate("../../../caravel/sdf/housekeeping.sdf", uut.housekeeping) ;
$sdf_annotate("../../../caravel/sdf/chip_io.sdf", uut.padframe) ;
$sdf_annotate("../../../caravel/sdf/mprj_logic_high.sdf", uut.mgmt_buffers.mprj_logic_high_inst) ;
$sdf_annotate("../../../caravel/sdf/mprj2_logic_high.sdf", uut.mgmt_buffers.mprj2_logic_high_inst) ;
$sdf_annotate("../../../caravel/sdf/mgmt_protect_hv.sdf", uut.mgmt_buffers.powergood_check) ;
$sdf_annotate("../../../caravel/sdf/mgmt_protect.sdf", uut.mgmt_buffers) ;
$sdf_annotate("../../../caravel/sdf/caravel_clocking.sdf", uut.clocking) ;
$sdf_annotate("../../../caravel/sdf/digital_pll.sdf", uut.pll) ;
$sdf_annotate("../../../caravel/sdf/xres_buf.sdf", uut.rstb_level) ;
$sdf_annotate("../../../caravel/sdf/user_id_programming.sdf", uut.user_id_value) ;
$sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_bidir_1[0] ) ;
$sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_bidir_1[1] ) ;
$sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_bidir_2[0] ) ;
$sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_bidir_2[1] ) ;
$sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_bidir_2[2] ) ;
$sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_1[0] ) ;
$sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_1[1] ) ;
$sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_1[2] ) ;
$sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_1[3] ) ;
$sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_1[4] ) ;
$sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_1[5] ) ;
$sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_1[6] ) ;
$sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_1[7] ) ;
$sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_1[8] ) ;
$sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_1[9] ) ;
$sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_1[10] ) ;
$sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_1a[0] ) ;
$sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_1a[1] ) ;
$sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_1a[2] ) ;
$sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_1a[3] ) ;
$sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_1a[4] ) ;
$sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_1a[5] ) ;
$sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_2[0] ) ;
$sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_2[1] ) ;
$sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_2[2] ) ;
$sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_2[3] ) ;
$sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_2[4] ) ;
$sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_2[5] ) ;
$sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_2[6] ) ;
$sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_2[7] ) ;
$sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_2[8] ) ;
$sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_2[9] ) ;
$sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_2[10] ) ;
$sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_2[11] ) ;
$sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_2[12] ) ;
$sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_2[13] ) ;
$sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_2[14] ) ;
$sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_2[15] ) ;
$sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.\gpio_defaults_block_0[0] ) ;
$sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.\gpio_defaults_block_0[1] ) ;
$sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.\gpio_defaults_block_2[0] ) ;
$sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.\gpio_defaults_block_2[1] ) ;
$sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.\gpio_defaults_block_2[2] ) ;
$sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_5) ;
$sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_6) ;
$sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_7) ;
$sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_8) ;
$sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_9) ;
$sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_10) ;
$sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_11) ;
$sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_12) ;
$sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_13) ;
$sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_14) ;
$sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_15) ;
$sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_16) ;
$sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_17) ;
$sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_18) ;
$sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_19) ;
$sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_20) ;
$sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_21) ;
$sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_22) ;
$sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_23) ;
$sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_24) ;
$sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_25) ;
$sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_26) ;
$sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_27) ;
$sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_28) ;
$sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_29) ;
$sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_30) ;
$sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_31) ;
$sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_32) ;
$sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_33) ;
$sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_34) ;
$sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_35) ;
$sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_36) ;
$sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_37) ;
end
`endif
initial begin
$dumpfile("wb_port.vcd");
$dumpvars(0, wb_port_tb);
// Repeat cycles of 1000 clock edges as needed to complete testbench
repeat (70) begin
repeat (1000) @(posedge clock);
// $display("+1000 cycles");
end
$display("%c[1;31m",27);
`ifdef GL
$display ("Monitor: Timeout, Test Mega-Project WB Port (GL) Failed");
`else
$display ("Monitor: Timeout, Test Mega-Project WB Port (RTL) Failed");
`endif
$display("%c[0m",27);
$finish;
end
initial begin
wait(checkbits == 16'hAB60);
$display("Monitor: MPRJ-Logic WB Started");
wait(checkbits == 16'hAB61);
`ifdef GL
$display("Monitor: Mega-Project WB (GL) Passed");
`else
$display("Monitor: Mega-Project WB (RTL) Passed");
`endif
$finish;
end
initial begin
RSTB <= 1'b0;
CSB <= 1'b1; // Force CSB high
#2000;
RSTB <= 1'b1; // Release reset
#100000;
CSB = 1'b0; // CSB can be released
end
initial begin // Power-up sequence
power1 <= 1'b0;
power2 <= 1'b0;
#200;
power1 <= 1'b1;
#200;
power2 <= 1'b1;
end
wire flash_csb;
wire flash_clk;
wire flash_io0;
wire flash_io1;
wire VDD3V3 = power1;
wire VDD1V8 = power2;
wire USER_VDD3V3 = power3;
wire USER_VDD1V8 = power4;
wire VSS = 1'b0;
caravel uut (
.vddio (VDD3V3),
.vddio_2 (VDD3V3),
.vssio (VSS),
.vssio_2 (VSS),
.vdda (VDD3V3),
.vssa (VSS),
.vccd (VDD1V8),
.vssd (VSS),
.vdda1 (VDD3V3),
.vdda1_2 (VDD3V3),
.vdda2 (VDD3V3),
.vssa1 (VSS),
.vssa1_2 (VSS),
.vssa2 (VSS),
.vccd1 (VDD1V8),
.vccd2 (VDD1V8),
.vssd1 (VSS),
.vssd2 (VSS),
.clock (clock),
.gpio (gpio),
.mprj_io (mprj_io),
.flash_csb(flash_csb),
.flash_clk(flash_clk),
.flash_io0(flash_io0),
.flash_io1(flash_io1),
.resetb (RSTB)
);
spiflash #(
.FILENAME("wb_port.hex")
) spiflash (
.csb(flash_csb),
.clk(flash_clk),
.io0(flash_io0),
.io1(flash_io1),
.io2(), // not used
.io3() // not used
);
endmodule |
module la_test1_tb;
reg clock;
reg RSTB;
reg CSB;
reg power1, power2;
wire gpio;
wire uart_tx;
wire [37:0] mprj_io;
wire [15:0] checkbits;
assign checkbits = mprj_io[31:16];
assign uart_tx = mprj_io[6];
always #12.5 clock <= (clock === 1'b0);
initial begin
clock = 0;
end
`ifdef ENABLE_SDF
initial begin
$sdf_annotate("../../../sdf/user_proj_example.sdf", uut.mprj) ;
$sdf_annotate("../../../sdf/user_project_wrapper.sdf", uut.mprj.mprj) ;
$sdf_annotate("../../../mgmt_core_wrapper/sdf/DFFRAM.sdf", uut.soc.DFFRAM_0) ;
$sdf_annotate("../../../mgmt_core_wrapper/sdf/mgmt_core.sdf", uut.soc.core) ;
$sdf_annotate("../../../caravel/sdf/housekeeping.sdf", uut.housekeeping) ;
$sdf_annotate("../../../caravel/sdf/chip_io.sdf", uut.padframe) ;
$sdf_annotate("../../../caravel/sdf/mprj_logic_high.sdf", uut.mgmt_buffers.mprj_logic_high_inst) ;
$sdf_annotate("../../../caravel/sdf/mprj2_logic_high.sdf", uut.mgmt_buffers.mprj2_logic_high_inst) ;
$sdf_annotate("../../../caravel/sdf/mgmt_protect_hv.sdf", uut.mgmt_buffers.powergood_check) ;
$sdf_annotate("../../../caravel/sdf/mgmt_protect.sdf", uut.mgmt_buffers) ;
$sdf_annotate("../../../caravel/sdf/caravel_clocking.sdf", uut.clocking) ;
$sdf_annotate("../../../caravel/sdf/digital_pll.sdf", uut.pll) ;
$sdf_annotate("../../../caravel/sdf/xres_buf.sdf", uut.rstb_level) ;
$sdf_annotate("../../../caravel/sdf/user_id_programming.sdf", uut.user_id_value) ;
$sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_bidir_1[0] ) ;
$sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_bidir_1[1] ) ;
$sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_bidir_2[0] ) ;
$sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_bidir_2[1] ) ;
$sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_bidir_2[2] ) ;
$sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_1[0] ) ;
$sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_1[1] ) ;
$sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_1[2] ) ;
$sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_1[3] ) ;
$sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_1[4] ) ;
$sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_1[5] ) ;
$sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_1[6] ) ;
$sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_1[7] ) ;
$sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_1[8] ) ;
$sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_1[9] ) ;
$sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_1[10] ) ;
$sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_1a[0] ) ;
$sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_1a[1] ) ;
$sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_1a[2] ) ;
$sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_1a[3] ) ;
$sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_1a[4] ) ;
$sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_1a[5] ) ;
$sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_2[0] ) ;
$sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_2[1] ) ;
$sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_2[2] ) ;
$sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_2[3] ) ;
$sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_2[4] ) ;
$sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_2[5] ) ;
$sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_2[6] ) ;
$sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_2[7] ) ;
$sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_2[8] ) ;
$sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_2[9] ) ;
$sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_2[10] ) ;
$sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_2[11] ) ;
$sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_2[12] ) ;
$sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_2[13] ) ;
$sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_2[14] ) ;
$sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_2[15] ) ;
$sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.\gpio_defaults_block_0[0] ) ;
$sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.\gpio_defaults_block_0[1] ) ;
$sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.\gpio_defaults_block_2[0] ) ;
$sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.\gpio_defaults_block_2[1] ) ;
$sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.\gpio_defaults_block_2[2] ) ;
$sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_5) ;
$sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_6) ;
$sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_7) ;
$sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_8) ;
$sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_9) ;
$sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_10) ;
$sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_11) ;
$sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_12) ;
$sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_13) ;
$sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_14) ;
$sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_15) ;
$sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_16) ;
$sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_17) ;
$sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_18) ;
$sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_19) ;
$sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_20) ;
$sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_21) ;
$sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_22) ;
$sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_23) ;
$sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_24) ;
$sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_25) ;
$sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_26) ;
$sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_27) ;
$sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_28) ;
$sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_29) ;
$sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_30) ;
$sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_31) ;
$sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_32) ;
$sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_33) ;
$sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_34) ;
$sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_35) ;
$sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_36) ;
$sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_37) ;
end
`endif
// assign mprj_io[3] = 1'b1;
initial begin
$dumpfile("la_test1.vcd");
$dumpvars(0, la_test1_tb);
// Repeat cycles of 1000 clock edges as needed to complete testbench
repeat (250) begin
repeat (1000) @(posedge clock);
// $display("+1000 cycles");
end
$display("%c[1;31m",27);
`ifdef GL
$display ("Monitor: Timeout, Test LA (GL) Failed");
`else
$display ("Monitor: Timeout, Test LA (RTL) Failed");
`endif
$display("%c[0m",27);
$finish;
end
initial begin
wait(checkbits == 16'hAB40);
$display("LA Test 1 started");
wait(checkbits == 16'hAB41);
wait(checkbits == 16'hAB51);
$display("LA Test 2 passed");
#10000;
$finish;
end
initial begin
RSTB <= 1'b0;
CSB <= 1'b1; // Force CSB high
#2000;
RSTB <= 1'b1; // Release reset
#170000;
CSB = 1'b0; // CSB can be released
end
initial begin // Power-up sequence
power1 <= 1'b0;
power2 <= 1'b0;
#200;
power1 <= 1'b1;
#200;
power2 <= 1'b1;
end
wire flash_csb;
wire flash_clk;
wire flash_io0;
wire flash_io1;
wire VDD1V8;
wire VDD3V3;
wire VSS;
assign VDD3V3 = power1;
assign VDD1V8 = power2;
assign VSS = 1'b0;
assign mprj_io[3] = 1; // Force CSB high.
assign mprj_io[0] = 0; // Disable debug mode
caravel uut (
.vddio (VDD3V3),
.vddio_2 (VDD3V3),
.vssio (VSS),
.vssio_2 (VSS),
.vdda (VDD3V3),
.vssa (VSS),
.vccd (VDD1V8),
.vssd (VSS),
.vdda1 (VDD3V3),
.vdda1_2 (VDD3V3),
.vdda2 (VDD3V3),
.vssa1 (VSS),
.vssa1_2 (VSS),
.vssa2 (VSS),
.vccd1 (VDD1V8),
.vccd2 (VDD1V8),
.vssd1 (VSS),
.vssd2 (VSS),
.clock (clock),
.gpio (gpio),
.mprj_io (mprj_io),
.flash_csb(flash_csb),
.flash_clk(flash_clk),
.flash_io0(flash_io0),
.flash_io1(flash_io1),
.resetb (RSTB)
);
spiflash #(
.FILENAME("la_test1.hex")
) spiflash (
.csb(flash_csb),
.clk(flash_clk),
.io0(flash_io0),
.io1(flash_io1),
.io2(), // not used
.io3() // not used
);
// Testbench UART
tbuart tbuart (
.ser_rx(uart_tx)
);
endmodule |
module io_ports_tb;
reg clock;
reg RSTB;
reg CSB;
reg power1, power2;
reg power3, power4;
wire gpio;
wire [37:0] mprj_io;
wire [7:0] mprj_io_0;
assign mprj_io_0 = mprj_io[7:0];
// assign mprj_io_0 = {mprj_io[8:4],mprj_io[2:0]};
assign mprj_io[3] = (CSB == 1'b1) ? 1'b1 : 1'bz;
// assign mprj_io[3] = 1'b1;
// External clock is used by default. Make this artificially fast for the
// simulation. Normally this would be a slow clock and the digital PLL
// would be the fast clock.
always #12.5 clock <= (clock === 1'b0);
initial begin
clock = 0;
end
`ifdef ENABLE_SDF
initial begin
$sdf_annotate("../../../sdf/user_proj_example.sdf", uut.mprj) ;
$sdf_annotate("../../../sdf/user_project_wrapper.sdf", uut.mprj.mprj) ;
$sdf_annotate("../../../mgmt_core_wrapper/sdf/DFFRAM.sdf", uut.soc.DFFRAM_0) ;
$sdf_annotate("../../../mgmt_core_wrapper/sdf/mgmt_core.sdf", uut.soc.core) ;
$sdf_annotate("../../../caravel/sdf/housekeeping.sdf", uut.housekeeping) ;
$sdf_annotate("../../../caravel/sdf/chip_io.sdf", uut.padframe) ;
$sdf_annotate("../../../caravel/sdf/mprj_logic_high.sdf", uut.mgmt_buffers.mprj_logic_high_inst) ;
$sdf_annotate("../../../caravel/sdf/mprj2_logic_high.sdf", uut.mgmt_buffers.mprj2_logic_high_inst) ;
$sdf_annotate("../../../caravel/sdf/mgmt_protect_hv.sdf", uut.mgmt_buffers.powergood_check) ;
$sdf_annotate("../../../caravel/sdf/mgmt_protect.sdf", uut.mgmt_buffers) ;
$sdf_annotate("../../../caravel/sdf/caravel_clocking.sdf", uut.clocking) ;
$sdf_annotate("../../../caravel/sdf/digital_pll.sdf", uut.pll) ;
$sdf_annotate("../../../caravel/sdf/xres_buf.sdf", uut.rstb_level) ;
$sdf_annotate("../../../caravel/sdf/user_id_programming.sdf", uut.user_id_value) ;
$sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_bidir_1[0] ) ;
$sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_bidir_1[1] ) ;
$sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_bidir_2[0] ) ;
$sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_bidir_2[1] ) ;
$sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_bidir_2[2] ) ;
$sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_1[0] ) ;
$sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_1[1] ) ;
$sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_1[2] ) ;
$sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_1[3] ) ;
$sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_1[4] ) ;
$sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_1[5] ) ;
$sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_1[6] ) ;
$sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_1[7] ) ;
$sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_1[8] ) ;
$sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_1[9] ) ;
$sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_1[10] ) ;
$sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_1a[0] ) ;
$sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_1a[1] ) ;
$sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_1a[2] ) ;
$sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_1a[3] ) ;
$sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_1a[4] ) ;
$sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_1a[5] ) ;
$sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_2[0] ) ;
$sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_2[1] ) ;
$sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_2[2] ) ;
$sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_2[3] ) ;
$sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_2[4] ) ;
$sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_2[5] ) ;
$sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_2[6] ) ;
$sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_2[7] ) ;
$sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_2[8] ) ;
$sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_2[9] ) ;
$sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_2[10] ) ;
$sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_2[11] ) ;
$sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_2[12] ) ;
$sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_2[13] ) ;
$sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_2[14] ) ;
$sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_2[15] ) ;
$sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.\gpio_defaults_block_0[0] ) ;
$sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.\gpio_defaults_block_0[1] ) ;
$sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.\gpio_defaults_block_2[0] ) ;
$sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.\gpio_defaults_block_2[1] ) ;
$sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.\gpio_defaults_block_2[2] ) ;
$sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_5) ;
$sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_6) ;
$sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_7) ;
$sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_8) ;
$sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_9) ;
$sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_10) ;
$sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_11) ;
$sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_12) ;
$sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_13) ;
$sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_14) ;
$sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_15) ;
$sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_16) ;
$sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_17) ;
$sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_18) ;
$sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_19) ;
$sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_20) ;
$sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_21) ;
$sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_22) ;
$sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_23) ;
$sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_24) ;
$sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_25) ;
$sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_26) ;
$sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_27) ;
$sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_28) ;
$sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_29) ;
$sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_30) ;
$sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_31) ;
$sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_32) ;
$sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_33) ;
$sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_34) ;
$sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_35) ;
$sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_36) ;
$sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_37) ;
end
`endif
initial begin
$dumpfile("io_ports.vcd");
$dumpvars(0, io_ports_tb);
// Repeat cycles of 1000 clock edges as needed to complete testbench
repeat (25) begin
repeat (1000) @(posedge clock);
// $display("+1000 cycles");
end
$display("%c[1;31m",27);
`ifdef GL
$display ("Monitor: Timeout, Test Mega-Project IO Ports (GL) Failed");
`else
$display ("Monitor: Timeout, Test Mega-Project IO Ports (RTL) Failed");
`endif
$display("%c[0m",27);
$finish;
end
initial begin
// Observe Output pins [7:0]
wait(mprj_io_0 == 8'h01);
wait(mprj_io_0 == 8'h02);
wait(mprj_io_0 == 8'h03);
wait(mprj_io_0 == 8'h04);
wait(mprj_io_0 == 8'h05);
wait(mprj_io_0 == 8'h06);
wait(mprj_io_0 == 8'h07);
wait(mprj_io_0 == 8'h08);
wait(mprj_io_0 == 8'h09);
wait(mprj_io_0 == 8'h0A);
wait(mprj_io_0 == 8'hFF);
wait(mprj_io_0 == 8'h00);
`ifdef GL
$display("Monitor: Test 1 Mega-Project IO (GL) Passed");
`else
$display("Monitor: Test 1 Mega-Project IO (RTL) Passed");
`endif
$finish;
end
initial begin
RSTB <= 1'b0;
CSB <= 1'b1; // Force CSB high
#2000;
RSTB <= 1'b1; // Release reset
#3_00_000;
CSB = 1'b0; // CSB can be released
end
initial begin // Power-up sequence
power1 <= 1'b0;
power2 <= 1'b0;
power3 <= 1'b0;
power4 <= 1'b0;
#100;
power1 <= 1'b1;
#100;
power2 <= 1'b1;
#100;
power3 <= 1'b1;
#100;
power4 <= 1'b1;
end
always @(mprj_io) begin
#1 $display("MPRJ-IO state = %b ", mprj_io[7:0]);
end
wire flash_csb;
wire flash_clk;
wire flash_io0;
wire flash_io1;
wire VDD3V3;
wire VDD1V8;
wire VSS;
assign VDD3V3 = power1;
assign VDD1V8 = power2;
assign VSS = 1'b0;
caravel uut (
.vddio (VDD3V3),
.vddio_2 (VDD3V3),
.vssio (VSS),
.vssio_2 (VSS),
.vdda (VDD3V3),
.vssa (VSS),
.vccd (VDD1V8),
.vssd (VSS),
.vdda1 (VDD3V3),
.vdda1_2 (VDD3V3),
.vdda2 (VDD3V3),
.vssa1 (VSS),
.vssa1_2 (VSS),
.vssa2 (VSS),
.vccd1 (VDD1V8),
.vccd2 (VDD1V8),
.vssd1 (VSS),
.vssd2 (VSS),
.clock (clock),
.gpio (gpio),
.mprj_io (mprj_io),
.flash_csb(flash_csb),
.flash_clk(flash_clk),
.flash_io0(flash_io0),
.flash_io1(flash_io1),
.resetb (RSTB)
);
spiflash #(
.FILENAME("io_ports.hex")
) spiflash (
.csb(flash_csb),
.clk(flash_clk),
.io0(flash_io0),
.io1(flash_io1),
.io2(), // not used
.io3() // not used
);
endmodule |
module la_test2_tb;
reg clock;
reg RSTB;
reg CSB;
reg power1, power2;
reg power3, power4;
wire gpio;
wire [37:0] mprj_io;
wire [15:0] checkbits;
assign checkbits = mprj_io[31:16];
assign mprj_io[3] = (CSB == 1'b1) ? 1'b1 : 1'bz;
always #15 clock <= (clock === 1'b0);
initial begin
clock = 0;
end
`ifdef ENABLE_SDF
initial begin
$sdf_annotate("../../../sdf/user_proj_example.sdf", uut.mprj) ;
$sdf_annotate("../../../sdf/user_project_wrapper.sdf", uut.mprj.mprj) ;
$sdf_annotate("../../../mgmt_core_wrapper/sdf/DFFRAM.sdf", uut.soc.DFFRAM_0) ;
// these breaks the simulation
$sdf_annotate("../../../mgmt_core_wrapper/sdf/mgmt_core.sdf", uut.soc.core) ;
$sdf_annotate("../../../caravel/sdf/housekeeping.sdf", uut.housekeeping) ;
$sdf_annotate("../../../caravel/sdf/chip_io.sdf", uut.padframe) ;
$sdf_annotate("../../../caravel/sdf/mprj_logic_high.sdf", uut.mgmt_buffers.mprj_logic_high_inst) ;
$sdf_annotate("../../../caravel/sdf/mprj2_logic_high.sdf", uut.mgmt_buffers.mprj2_logic_high_inst) ;
$sdf_annotate("../../../caravel/sdf/mgmt_protect_hv.sdf", uut.mgmt_buffers.powergood_check) ;
$sdf_annotate("../../../caravel/sdf/mgmt_protect.sdf", uut.mgmt_buffers) ;
$sdf_annotate("../../../caravel/sdf/caravel_clocking.sdf", uut.clocking) ;
$sdf_annotate("../../../caravel/sdf/digital_pll.sdf", uut.pll) ;
$sdf_annotate("../../../caravel/sdf/xres_buf.sdf", uut.rstb_level) ;
$sdf_annotate("../../../caravel/sdf/user_id_programming.sdf", uut.user_id_value) ;
$sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_bidir_1[0] ) ;
$sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_bidir_1[1] ) ;
$sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_bidir_2[0] ) ;
$sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_bidir_2[1] ) ;
$sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_bidir_2[2] ) ;
$sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_1[0] ) ;
$sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_1[1] ) ;
$sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_1[2] ) ;
$sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_1[3] ) ;
$sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_1[4] ) ;
$sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_1[5] ) ;
$sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_1[6] ) ;
$sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_1[7] ) ;
$sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_1[8] ) ;
$sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_1[9] ) ;
$sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_1[10] ) ;
$sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_1a[0] ) ;
$sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_1a[1] ) ;
$sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_1a[2] ) ;
$sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_1a[3] ) ;
$sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_1a[4] ) ;
$sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_1a[5] ) ;
$sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_2[0] ) ;
$sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_2[1] ) ;
$sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_2[2] ) ;
$sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_2[3] ) ;
$sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_2[4] ) ;
$sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_2[5] ) ;
$sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_2[6] ) ;
$sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_2[7] ) ;
$sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_2[8] ) ;
$sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_2[9] ) ;
$sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_2[10] ) ;
$sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_2[11] ) ;
$sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_2[12] ) ;
$sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_2[13] ) ;
$sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_2[14] ) ;
$sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_2[15] ) ;
$sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.\gpio_defaults_block_0[0] ) ;
$sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.\gpio_defaults_block_0[1] ) ;
$sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.\gpio_defaults_block_2[0] ) ;
$sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.\gpio_defaults_block_2[1] ) ;
$sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.\gpio_defaults_block_2[2] ) ;
$sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_5) ;
$sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_6) ;
$sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_7) ;
$sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_8) ;
$sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_9) ;
$sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_10) ;
$sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_11) ;
$sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_12) ;
$sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_13) ;
$sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_14) ;
$sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_15) ;
$sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_16) ;
$sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_17) ;
$sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_18) ;
$sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_19) ;
$sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_20) ;
$sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_21) ;
$sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_22) ;
$sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_23) ;
$sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_24) ;
$sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_25) ;
$sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_26) ;
$sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_27) ;
$sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_28) ;
$sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_29) ;
$sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_30) ;
$sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_31) ;
$sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_32) ;
$sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_33) ;
$sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_34) ;
$sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_35) ;
$sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_36) ;
$sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_37) ;
end
`endif
initial begin
$dumpfile("la_test2.vcd");
$dumpvars(0, la_test2_tb);
// Repeat cycles of 1000 clock edges as needed to complete testbench
repeat (75) begin
repeat (1000) @(posedge clock);
// $display("+1000 cycles");
end
$display("%c[1;31m",27);
`ifdef GL
$display ("Monitor: Timeout, Test Mega-Project IO (GL) Failed");
`else
$display ("Monitor: Timeout, Test Mega-Project IO (RTL) Failed");
`endif
$display("%c[0m",27);
$finish;
end
initial begin
wait(checkbits == 16'hAB60);
$display("Monitor: Test 2 MPRJ-Logic Analyzer Started");
wait(checkbits == 16'hAB61);
$display("Monitor: Test 2 MPRJ-Logic Analyzer Passed");
$finish;
end
initial begin
RSTB <= 1'b0;
CSB <= 1'b1; // Force CSB high
#2000;
RSTB <= 1'b1; // Release reset
#3_000_000;
CSB = 1'b0; // CSB can be released
end
initial begin // Power-up sequence
power1 <= 1'b0;
power2 <= 1'b0;
power3 <= 1'b0;
power4 <= 1'b0;
#100;
power1 <= 1'b1;
#100;
power2 <= 1'b1;
#100;
power3 <= 1'b1;
#100;
power4 <= 1'b1;
end
wire flash_csb;
wire flash_clk;
wire flash_io0;
wire flash_io1;
wire VDD3V3;
wire VDD1V8;
wire VSS;
assign VDD3V3 = power1;
assign VDD1V8 = power2;
assign VSS = 1'b0;
caravel uut (
.vddio (VDD3V3),
.vddio_2 (VDD3V3),
.vssio (VSS),
.vssio_2 (VSS),
.vdda (VDD3V3),
.vssa (VSS),
.vccd (VDD1V8),
.vssd (VSS),
.vdda1 (VDD3V3),
.vdda1_2 (VDD3V3),
.vdda2 (VDD3V3),
.vssa1 (VSS),
.vssa1_2 (VSS),
.vssa2 (VSS),
.vccd1 (VDD1V8),
.vccd2 (VDD1V8),
.vssd1 (VSS),
.vssd2 (VSS),
.clock (clock),
.gpio (gpio),
.mprj_io (mprj_io),
.flash_csb(flash_csb),
.flash_clk(flash_clk),
.flash_io0(flash_io0),
.flash_io1(flash_io1),
.resetb (RSTB)
);
spiflash #(
.FILENAME("la_test2.hex")
) spiflash (
.csb(flash_csb),
.clk(flash_clk),
.io0(flash_io0),
.io1(flash_io1),
.io2(),
.io3()
);
endmodule |
module aes_sbox(
input wire [31 : 0] sboxw,
output wire [31 : 0] new_sboxw
);
//----------------------------------------------------------------
// The sbox array.
//----------------------------------------------------------------
wire [7 : 0] sbox [0 : 255];
//----------------------------------------------------------------
// Four parallel muxes.
//----------------------------------------------------------------
assign new_sboxw[31 : 24] = sbox[sboxw[31 : 24]];
assign new_sboxw[23 : 16] = sbox[sboxw[23 : 16]];
assign new_sboxw[15 : 08] = sbox[sboxw[15 : 08]];
assign new_sboxw[07 : 00] = sbox[sboxw[07 : 00]];
//----------------------------------------------------------------
// Creating the sbox array contents.
//----------------------------------------------------------------
assign sbox[8'h00] = 8'h63;
assign sbox[8'h01] = 8'h7c;
assign sbox[8'h02] = 8'h77;
assign sbox[8'h03] = 8'h7b;
assign sbox[8'h04] = 8'hf2;
assign sbox[8'h05] = 8'h6b;
assign sbox[8'h06] = 8'h6f;
assign sbox[8'h07] = 8'hc5;
assign sbox[8'h08] = 8'h30;
assign sbox[8'h09] = 8'h01;
assign sbox[8'h0a] = 8'h67;
assign sbox[8'h0b] = 8'h2b;
assign sbox[8'h0c] = 8'hfe;
assign sbox[8'h0d] = 8'hd7;
assign sbox[8'h0e] = 8'hab;
assign sbox[8'h0f] = 8'h76;
assign sbox[8'h10] = 8'hca;
assign sbox[8'h11] = 8'h82;
assign sbox[8'h12] = 8'hc9;
assign sbox[8'h13] = 8'h7d;
assign sbox[8'h14] = 8'hfa;
assign sbox[8'h15] = 8'h59;
assign sbox[8'h16] = 8'h47;
assign sbox[8'h17] = 8'hf0;
assign sbox[8'h18] = 8'had;
assign sbox[8'h19] = 8'hd4;
assign sbox[8'h1a] = 8'ha2;
assign sbox[8'h1b] = 8'haf;
assign sbox[8'h1c] = 8'h9c;
assign sbox[8'h1d] = 8'ha4;
assign sbox[8'h1e] = 8'h72;
assign sbox[8'h1f] = 8'hc0;
assign sbox[8'h20] = 8'hb7;
assign sbox[8'h21] = 8'hfd;
assign sbox[8'h22] = 8'h93;
assign sbox[8'h23] = 8'h26;
assign sbox[8'h24] = 8'h36;
assign sbox[8'h25] = 8'h3f;
assign sbox[8'h26] = 8'hf7;
assign sbox[8'h27] = 8'hcc;
assign sbox[8'h28] = 8'h34;
assign sbox[8'h29] = 8'ha5;
assign sbox[8'h2a] = 8'he5;
assign sbox[8'h2b] = 8'hf1;
assign sbox[8'h2c] = 8'h71;
assign sbox[8'h2d] = 8'hd8;
assign sbox[8'h2e] = 8'h31;
assign sbox[8'h2f] = 8'h15;
assign sbox[8'h30] = 8'h04;
assign sbox[8'h31] = 8'hc7;
assign sbox[8'h32] = 8'h23;
assign sbox[8'h33] = 8'hc3;
assign sbox[8'h34] = 8'h18;
assign sbox[8'h35] = 8'h96;
assign sbox[8'h36] = 8'h05;
assign sbox[8'h37] = 8'h9a;
assign sbox[8'h38] = 8'h07;
assign sbox[8'h39] = 8'h12;
assign sbox[8'h3a] = 8'h80;
assign sbox[8'h3b] = 8'he2;
assign sbox[8'h3c] = 8'heb;
assign sbox[8'h3d] = 8'h27;
assign sbox[8'h3e] = 8'hb2;
assign sbox[8'h3f] = 8'h75;
assign sbox[8'h40] = 8'h09;
assign sbox[8'h41] = 8'h83;
assign sbox[8'h42] = 8'h2c;
assign sbox[8'h43] = 8'h1a;
assign sbox[8'h44] = 8'h1b;
assign sbox[8'h45] = 8'h6e;
assign sbox[8'h46] = 8'h5a;
assign sbox[8'h47] = 8'ha0;
assign sbox[8'h48] = 8'h52;
assign sbox[8'h49] = 8'h3b;
assign sbox[8'h4a] = 8'hd6;
assign sbox[8'h4b] = 8'hb3;
assign sbox[8'h4c] = 8'h29;
assign sbox[8'h4d] = 8'he3;
assign sbox[8'h4e] = 8'h2f;
assign sbox[8'h4f] = 8'h84;
assign sbox[8'h50] = 8'h53;
assign sbox[8'h51] = 8'hd1;
assign sbox[8'h52] = 8'h00;
assign sbox[8'h53] = 8'hed;
assign sbox[8'h54] = 8'h20;
assign sbox[8'h55] = 8'hfc;
assign sbox[8'h56] = 8'hb1;
assign sbox[8'h57] = 8'h5b;
assign sbox[8'h58] = 8'h6a;
assign sbox[8'h59] = 8'hcb;
assign sbox[8'h5a] = 8'hbe;
assign sbox[8'h5b] = 8'h39;
assign sbox[8'h5c] = 8'h4a;
assign sbox[8'h5d] = 8'h4c;
assign sbox[8'h5e] = 8'h58;
assign sbox[8'h5f] = 8'hcf;
assign sbox[8'h60] = 8'hd0;
assign sbox[8'h61] = 8'hef;
assign sbox[8'h62] = 8'haa;
assign sbox[8'h63] = 8'hfb;
assign sbox[8'h64] = 8'h43;
assign sbox[8'h65] = 8'h4d;
assign sbox[8'h66] = 8'h33;
assign sbox[8'h67] = 8'h85;
assign sbox[8'h68] = 8'h45;
assign sbox[8'h69] = 8'hf9;
assign sbox[8'h6a] = 8'h02;
assign sbox[8'h6b] = 8'h7f;
assign sbox[8'h6c] = 8'h50;
assign sbox[8'h6d] = 8'h3c;
assign sbox[8'h6e] = 8'h9f;
assign sbox[8'h6f] = 8'ha8;
assign sbox[8'h70] = 8'h51;
assign sbox[8'h71] = 8'ha3;
assign sbox[8'h72] = 8'h40;
assign sbox[8'h73] = 8'h8f;
assign sbox[8'h74] = 8'h92;
assign sbox[8'h75] = 8'h9d;
assign sbox[8'h76] = 8'h38;
assign sbox[8'h77] = 8'hf5;
assign sbox[8'h78] = 8'hbc;
assign sbox[8'h79] = 8'hb6;
assign sbox[8'h7a] = 8'hda;
assign sbox[8'h7b] = 8'h21;
assign sbox[8'h7c] = 8'h10;
assign sbox[8'h7d] = 8'hff;
assign sbox[8'h7e] = 8'hf3;
assign sbox[8'h7f] = 8'hd2;
assign sbox[8'h80] = 8'hcd;
assign sbox[8'h81] = 8'h0c;
assign sbox[8'h82] = 8'h13;
assign sbox[8'h83] = 8'hec;
assign sbox[8'h84] = 8'h5f;
assign sbox[8'h85] = 8'h97;
assign sbox[8'h86] = 8'h44;
assign sbox[8'h87] = 8'h17;
assign sbox[8'h88] = 8'hc4;
assign sbox[8'h89] = 8'ha7;
assign sbox[8'h8a] = 8'h7e;
assign sbox[8'h8b] = 8'h3d;
assign sbox[8'h8c] = 8'h64;
assign sbox[8'h8d] = 8'h5d;
assign sbox[8'h8e] = 8'h19;
assign sbox[8'h8f] = 8'h73;
assign sbox[8'h90] = 8'h60;
assign sbox[8'h91] = 8'h81;
assign sbox[8'h92] = 8'h4f;
assign sbox[8'h93] = 8'hdc;
assign sbox[8'h94] = 8'h22;
assign sbox[8'h95] = 8'h2a;
assign sbox[8'h96] = 8'h90;
assign sbox[8'h97] = 8'h88;
assign sbox[8'h98] = 8'h46;
assign sbox[8'h99] = 8'hee;
assign sbox[8'h9a] = 8'hb8;
assign sbox[8'h9b] = 8'h14;
assign sbox[8'h9c] = 8'hde;
assign sbox[8'h9d] = 8'h5e;
assign sbox[8'h9e] = 8'h0b;
assign sbox[8'h9f] = 8'hdb;
assign sbox[8'ha0] = 8'he0;
assign sbox[8'ha1] = 8'h32;
assign sbox[8'ha2] = 8'h3a;
assign sbox[8'ha3] = 8'h0a;
assign sbox[8'ha4] = 8'h49;
assign sbox[8'ha5] = 8'h06;
assign sbox[8'ha6] = 8'h24;
assign sbox[8'ha7] = 8'h5c;
assign sbox[8'ha8] = 8'hc2;
assign sbox[8'ha9] = 8'hd3;
assign sbox[8'haa] = 8'hac;
assign sbox[8'hab] = 8'h62;
assign sbox[8'hac] = 8'h91;
assign sbox[8'had] = 8'h95;
assign sbox[8'hae] = 8'he4;
assign sbox[8'haf] = 8'h79;
assign sbox[8'hb0] = 8'he7;
assign sbox[8'hb1] = 8'hc8;
assign sbox[8'hb2] = 8'h37;
assign sbox[8'hb3] = 8'h6d;
assign sbox[8'hb4] = 8'h8d;
assign sbox[8'hb5] = 8'hd5;
assign sbox[8'hb6] = 8'h4e;
assign sbox[8'hb7] = 8'ha9;
assign sbox[8'hb8] = 8'h6c;
assign sbox[8'hb9] = 8'h56;
assign sbox[8'hba] = 8'hf4;
assign sbox[8'hbb] = 8'hea;
assign sbox[8'hbc] = 8'h65;
assign sbox[8'hbd] = 8'h7a;
assign sbox[8'hbe] = 8'hae;
assign sbox[8'hbf] = 8'h08;
assign sbox[8'hc0] = 8'hba;
assign sbox[8'hc1] = 8'h78;
assign sbox[8'hc2] = 8'h25;
assign sbox[8'hc3] = 8'h2e;
assign sbox[8'hc4] = 8'h1c;
assign sbox[8'hc5] = 8'ha6;
assign sbox[8'hc6] = 8'hb4;
assign sbox[8'hc7] = 8'hc6;
assign sbox[8'hc8] = 8'he8;
assign sbox[8'hc9] = 8'hdd;
assign sbox[8'hca] = 8'h74;
assign sbox[8'hcb] = 8'h1f;
assign sbox[8'hcc] = 8'h4b;
assign sbox[8'hcd] = 8'hbd;
assign sbox[8'hce] = 8'h8b;
assign sbox[8'hcf] = 8'h8a;
assign sbox[8'hd0] = 8'h70;
assign sbox[8'hd1] = 8'h3e;
assign sbox[8'hd2] = 8'hb5;
assign sbox[8'hd3] = 8'h66;
assign sbox[8'hd4] = 8'h48;
assign sbox[8'hd5] = 8'h03;
assign sbox[8'hd6] = 8'hf6;
assign sbox[8'hd7] = 8'h0e;
assign sbox[8'hd8] = 8'h61;
assign sbox[8'hd9] = 8'h35;
assign sbox[8'hda] = 8'h57;
assign sbox[8'hdb] = 8'hb9;
assign sbox[8'hdc] = 8'h86;
assign sbox[8'hdd] = 8'hc1;
assign sbox[8'hde] = 8'h1d;
assign sbox[8'hdf] = 8'h9e;
assign sbox[8'he0] = 8'he1;
assign sbox[8'he1] = 8'hf8;
assign sbox[8'he2] = 8'h98;
assign sbox[8'he3] = 8'h11;
assign sbox[8'he4] = 8'h69;
assign sbox[8'he5] = 8'hd9;
assign sbox[8'he6] = 8'h8e;
assign sbox[8'he7] = 8'h94;
assign sbox[8'he8] = 8'h9b;
assign sbox[8'he9] = 8'h1e;
assign sbox[8'hea] = 8'h87;
assign sbox[8'heb] = 8'he9;
assign sbox[8'hec] = 8'hce;
assign sbox[8'hed] = 8'h55;
assign sbox[8'hee] = 8'h28;
assign sbox[8'hef] = 8'hdf;
assign sbox[8'hf0] = 8'h8c;
assign sbox[8'hf1] = 8'ha1;
assign sbox[8'hf2] = 8'h89;
assign sbox[8'hf3] = 8'h0d;
assign sbox[8'hf4] = 8'hbf;
assign sbox[8'hf5] = 8'he6;
assign sbox[8'hf6] = 8'h42;
assign sbox[8'hf7] = 8'h68;
assign sbox[8'hf8] = 8'h41;
assign sbox[8'hf9] = 8'h99;
assign sbox[8'hfa] = 8'h2d;
assign sbox[8'hfb] = 8'h0f;
assign sbox[8'hfc] = 8'hb0;
assign sbox[8'hfd] = 8'h54;
assign sbox[8'hfe] = 8'hbb;
assign sbox[8'hff] = 8'h16;
endmodule // aes_sbox |
module aes_core(
input wire clk,
input wire reset_n,
input wire encdec,
input wire init,
input wire next,
output wire ready,
input wire [255 : 0] key,
input wire keylen,
input wire [127 : 0] block,
output wire [127 : 0] result,
output wire result_valid
);
//----------------------------------------------------------------
// Internal constant and parameter definitions.
//----------------------------------------------------------------
localparam CTRL_IDLE = 2'h0;
localparam CTRL_INIT = 2'h1;
localparam CTRL_NEXT = 2'h2;
//----------------------------------------------------------------
// Registers including update variables and write enable.
//----------------------------------------------------------------
reg [1 : 0] aes_core_ctrl_reg;
reg [1 : 0] aes_core_ctrl_new;
reg aes_core_ctrl_we;
reg result_valid_reg;
reg result_valid_new;
reg result_valid_we;
reg ready_reg;
reg ready_new;
reg ready_we;
//----------------------------------------------------------------
// Wires.
//----------------------------------------------------------------
reg init_state;
wire [127 : 0] round_key;
wire key_ready;
reg enc_next;
wire [3 : 0] enc_round_nr;
wire [127 : 0] enc_new_block;
wire enc_ready;
wire [31 : 0] enc_sboxw;
reg dec_next;
wire [3 : 0] dec_round_nr;
wire [127 : 0] dec_new_block;
wire dec_ready;
reg [127 : 0] muxed_new_block;
reg [3 : 0] muxed_round_nr;
reg muxed_ready;
wire [31 : 0] keymem_sboxw;
/* verilator lint_off UNOPTFLAT */
reg [31 : 0] muxed_sboxw;
wire [31 : 0] new_sboxw;
/* verilator lint_on UNOPTFLAT */
//----------------------------------------------------------------
// Instantiations.
//----------------------------------------------------------------
aes_encipher_block enc_block(
.clk(clk),
.reset_n(reset_n),
.next(enc_next),
.keylen(keylen),
.round(enc_round_nr),
.round_key(round_key),
.sboxw(enc_sboxw),
.new_sboxw(new_sboxw),
.block(block),
.new_block(enc_new_block),
.ready(enc_ready)
);
aes_decipher_block dec_block(
.clk(clk),
.reset_n(reset_n),
.next(dec_next),
.keylen(keylen),
.round(dec_round_nr),
.round_key(round_key),
.block(block),
.new_block(dec_new_block),
.ready(dec_ready)
);
aes_key_mem keymem(
.clk(clk),
.reset_n(reset_n),
.key(key),
.keylen(keylen),
.init(init),
.round(muxed_round_nr),
.round_key(round_key),
.ready(key_ready),
.sboxw(keymem_sboxw),
.new_sboxw(new_sboxw)
);
aes_sbox sbox_inst(.sboxw(muxed_sboxw), .new_sboxw(new_sboxw));
//----------------------------------------------------------------
// Concurrent connectivity for ports etc.
//----------------------------------------------------------------
assign ready = ready_reg;
assign result = muxed_new_block;
assign result_valid = result_valid_reg;
//----------------------------------------------------------------
// reg_update
//
// Update functionality for all registers in the core.
// All registers are positive edge triggered with asynchronous
// active low reset. All registers have write enable.
//----------------------------------------------------------------
always @ (posedge clk or negedge reset_n)
begin: reg_update
if (!reset_n)
begin
result_valid_reg <= 1'b0;
ready_reg <= 1'b1;
aes_core_ctrl_reg <= CTRL_IDLE;
end
else
begin
if (result_valid_we)
result_valid_reg <= result_valid_new;
if (ready_we)
ready_reg <= ready_new;
if (aes_core_ctrl_we)
aes_core_ctrl_reg <= aes_core_ctrl_new;
end
end // reg_update
//----------------------------------------------------------------
// sbox_mux
//
// Controls which of the encipher datapath or the key memory
// that gets access to the sbox.
//----------------------------------------------------------------
always @*
begin : sbox_mux
if (init_state)
begin
muxed_sboxw = keymem_sboxw;
end
else
begin
muxed_sboxw = enc_sboxw;
end
end // sbox_mux
//----------------------------------------------------------------
// encdex_mux
//
// Controls which of the datapaths that get the next signal, have
// access to the memory as well as the block processing result.
//----------------------------------------------------------------
always @*
begin : encdec_mux
enc_next = 1'b0;
dec_next = 1'b0;
if (encdec)
begin
// Encipher operations
enc_next = next;
muxed_round_nr = enc_round_nr;
muxed_new_block = enc_new_block;
muxed_ready = enc_ready;
end
else
begin
// Decipher operations
dec_next = next;
muxed_round_nr = dec_round_nr;
muxed_new_block = dec_new_block;
muxed_ready = dec_ready;
end
end // encdec_mux
//----------------------------------------------------------------
// aes_core_ctrl
//
// Control FSM for aes core. Basically tracks if we are in
// key init, encipher or decipher modes and connects the
// different submodules to shared resources and interface ports.
//----------------------------------------------------------------
always @*
begin : aes_core_ctrl
init_state = 1'b0;
ready_new = 1'b0;
ready_we = 1'b0;
result_valid_new = 1'b0;
result_valid_we = 1'b0;
aes_core_ctrl_new = CTRL_IDLE;
aes_core_ctrl_we = 1'b0;
case (aes_core_ctrl_reg)
CTRL_IDLE:
begin
if (init)
begin
init_state = 1'b1;
ready_new = 1'b0;
ready_we = 1'b1;
result_valid_new = 1'b0;
result_valid_we = 1'b1;
aes_core_ctrl_new = CTRL_INIT;
aes_core_ctrl_we = 1'b1;
end
else if (next)
begin
init_state = 1'b0;
ready_new = 1'b0;
ready_we = 1'b1;
result_valid_new = 1'b0;
result_valid_we = 1'b1;
aes_core_ctrl_new = CTRL_NEXT;
aes_core_ctrl_we = 1'b1;
end
end
CTRL_INIT:
begin
init_state = 1'b1;
if (key_ready)
begin
ready_new = 1'b1;
ready_we = 1'b1;
aes_core_ctrl_new = CTRL_IDLE;
aes_core_ctrl_we = 1'b1;
end
end
CTRL_NEXT:
begin
init_state = 1'b0;
if (muxed_ready)
begin
ready_new = 1'b1;
ready_we = 1'b1;
result_valid_new = 1'b1;
result_valid_we = 1'b1;
aes_core_ctrl_new = CTRL_IDLE;
aes_core_ctrl_we = 1'b1;
end
end
default:
begin
end
endcase // case (aes_core_ctrl_reg)
end // aes_core_ctrl
endmodule // aes_core |
module aes(
// Clock and reset.
input wire clk,
input wire reset_n,
// Control.
input wire cs,
input wire we,
// Data ports.
input wire [7 : 0] address,
input wire [31 : 0] write_data,
output wire [31 : 0] read_data
);
//----------------------------------------------------------------
// Internal constant and parameter definitions.
//----------------------------------------------------------------
localparam ADDR_NAME0 = 8'h00;
localparam ADDR_NAME1 = 8'h01;
localparam ADDR_VERSION = 8'h02;
localparam ADDR_CTRL = 8'h08;
localparam CTRL_INIT_BIT = 0;
localparam CTRL_NEXT_BIT = 1;
localparam ADDR_STATUS = 8'h09;
localparam STATUS_READY_BIT = 0;
localparam STATUS_VALID_BIT = 1;
localparam ADDR_CONFIG = 8'h0a;
localparam CTRL_ENCDEC_BIT = 0;
localparam CTRL_KEYLEN_BIT = 1;
localparam ADDR_KEY0 = 8'h10;
localparam ADDR_KEY7 = 8'h17;
localparam ADDR_BLOCK0 = 8'h20;
localparam ADDR_BLOCK3 = 8'h23;
localparam ADDR_RESULT0 = 8'h30;
localparam ADDR_RESULT3 = 8'h33;
localparam CORE_NAME0 = 32'h61657320; // "aes "
localparam CORE_NAME1 = 32'h20202020; // " "
localparam CORE_VERSION = 32'h302e3630; // "0.60"
//----------------------------------------------------------------
// Registers including update variables and write enable.
//----------------------------------------------------------------
reg init_reg;
reg init_new;
reg next_reg;
reg next_new;
reg encdec_reg;
reg keylen_reg;
reg config_we;
reg [31 : 0] block_reg [0 : 3];
reg block_we;
reg [31 : 0] key_reg [0 : 7];
reg key_we;
reg [127 : 0] result_reg;
reg valid_reg;
reg ready_reg;
//----------------------------------------------------------------
// Wires.
//----------------------------------------------------------------
reg [31 : 0] tmp_read_data;
wire core_encdec;
wire core_init;
wire core_next;
wire core_ready;
wire [255 : 0] core_key;
wire core_keylen;
wire [127 : 0] core_block;
wire [127 : 0] core_result;
wire core_valid;
//----------------------------------------------------------------
// Concurrent connectivity for ports etc.
//----------------------------------------------------------------
assign read_data = tmp_read_data;
assign core_key = {key_reg[0], key_reg[1], key_reg[2], key_reg[3],
key_reg[4], key_reg[5], key_reg[6], key_reg[7]};
assign core_block = {block_reg[0], block_reg[1],
block_reg[2], block_reg[3]};
assign core_init = init_reg;
assign core_next = next_reg;
assign core_encdec = encdec_reg;
assign core_keylen = keylen_reg;
//----------------------------------------------------------------
// core instantiation.
//----------------------------------------------------------------
aes_core core(
.clk(clk),
.reset_n(reset_n),
.encdec(core_encdec),
.init(core_init),
.next(core_next),
.ready(core_ready),
.key(core_key),
.keylen(core_keylen),
.block(core_block),
.result(core_result),
.result_valid(core_valid)
);
//----------------------------------------------------------------
// reg_update
// Update functionality for all registers in the core.
// All registers are positive edge triggered with asynchronous
// active low reset.
//----------------------------------------------------------------
always @ (posedge clk or negedge reset_n)
begin : reg_update
integer i;
if (!reset_n)
begin
for (i = 0 ; i < 4 ; i = i + 1)
block_reg[i] <= 32'h0;
for (i = 0 ; i < 8 ; i = i + 1)
key_reg[i] <= 32'h0;
init_reg <= 1'b0;
next_reg <= 1'b0;
encdec_reg <= 1'b0;
keylen_reg <= 1'b0;
result_reg <= 128'h0;
valid_reg <= 1'b0;
ready_reg <= 1'b0;
end
else
begin
ready_reg <= core_ready;
valid_reg <= core_valid;
result_reg <= core_result;
init_reg <= init_new;
next_reg <= next_new;
if (config_we)
begin
encdec_reg <= write_data[CTRL_ENCDEC_BIT];
keylen_reg <= write_data[CTRL_KEYLEN_BIT];
end
if (key_we)
key_reg[address[2 : 0]] <= write_data;
if (block_we)
block_reg[address[1 : 0]] <= write_data;
end
end // reg_update
//----------------------------------------------------------------
// api
//
// The interface command decoding logic.
//----------------------------------------------------------------
always @*
begin : api
init_new = 1'b0;
next_new = 1'b0;
config_we = 1'b0;
key_we = 1'b0;
block_we = 1'b0;
tmp_read_data = 32'h0;
if (cs)
begin
if (we)
begin
if (address == ADDR_CTRL)
begin
init_new = write_data[CTRL_INIT_BIT];
next_new = write_data[CTRL_NEXT_BIT];
end
if (address == ADDR_CONFIG)
config_we = 1'b1;
if ((address >= ADDR_KEY0) && (address <= ADDR_KEY7))
key_we = 1'b1;
if ((address >= ADDR_BLOCK0) && (address <= ADDR_BLOCK3))
block_we = 1'b1;
end // if (we)
else
begin
case (address)
ADDR_NAME0: tmp_read_data = CORE_NAME0;
ADDR_NAME1: tmp_read_data = CORE_NAME1;
ADDR_VERSION: tmp_read_data = CORE_VERSION;
ADDR_CTRL: tmp_read_data = {28'h0, keylen_reg, encdec_reg, next_reg, init_reg};
ADDR_STATUS: tmp_read_data = {30'h0, valid_reg, ready_reg};
default:
begin
end
endcase // case (address)
if ((address >= ADDR_RESULT0) && (address <= ADDR_RESULT3))
tmp_read_data = result_reg[(3 - (address - ADDR_RESULT0)) * 32 +: 32];
end
end
end // addr_decoder
endmodule // aes |
module aes_decipher_block(
input wire clk,
input wire reset_n,
input wire next,
input wire keylen,
output wire [3 : 0] round,
input wire [127 : 0] round_key,
input wire [127 : 0] block,
output wire [127 : 0] new_block,
output wire ready
);
//----------------------------------------------------------------
// Internal constant and parameter definitions.
//----------------------------------------------------------------
localparam AES_128_BIT_KEY = 1'h0;
localparam AES_256_BIT_KEY = 1'h1;
localparam AES128_ROUNDS = 4'ha;
localparam AES256_ROUNDS = 4'he;
localparam NO_UPDATE = 3'h0;
localparam INIT_UPDATE = 3'h1;
localparam SBOX_UPDATE = 3'h2;
localparam MAIN_UPDATE = 3'h3;
localparam FINAL_UPDATE = 3'h4;
localparam CTRL_IDLE = 2'h0;
localparam CTRL_INIT = 2'h1;
localparam CTRL_SBOX = 2'h2;
localparam CTRL_MAIN = 2'h3;
//----------------------------------------------------------------
// Gaolis multiplication functions for Inverse MixColumn.
//----------------------------------------------------------------
function [7 : 0] gm2(input [7 : 0] op);
begin
gm2 = {op[6 : 0], 1'b0} ^ (8'h1b & {8{op[7]}});
end
endfunction // gm2
function [7 : 0] gm3(input [7 : 0] op);
begin
gm3 = gm2(op) ^ op;
end
endfunction // gm3
function [7 : 0] gm4(input [7 : 0] op);
begin
gm4 = gm2(gm2(op));
end
endfunction // gm4
function [7 : 0] gm8(input [7 : 0] op);
begin
gm8 = gm2(gm4(op));
end
endfunction // gm8
function [7 : 0] gm09(input [7 : 0] op);
begin
gm09 = gm8(op) ^ op;
end
endfunction // gm09
function [7 : 0] gm11(input [7 : 0] op);
begin
gm11 = gm8(op) ^ gm2(op) ^ op;
end
endfunction // gm11
function [7 : 0] gm13(input [7 : 0] op);
begin
gm13 = gm8(op) ^ gm4(op) ^ op;
end
endfunction // gm13
function [7 : 0] gm14(input [7 : 0] op);
begin
gm14 = gm8(op) ^ gm4(op) ^ gm2(op);
end
endfunction // gm14
function [31 : 0] inv_mixw(input [31 : 0] w);
reg [7 : 0] b0, b1, b2, b3;
reg [7 : 0] mb0, mb1, mb2, mb3;
begin
b0 = w[31 : 24];
b1 = w[23 : 16];
b2 = w[15 : 08];
b3 = w[07 : 00];
mb0 = gm14(b0) ^ gm11(b1) ^ gm13(b2) ^ gm09(b3);
mb1 = gm09(b0) ^ gm14(b1) ^ gm11(b2) ^ gm13(b3);
mb2 = gm13(b0) ^ gm09(b1) ^ gm14(b2) ^ gm11(b3);
mb3 = gm11(b0) ^ gm13(b1) ^ gm09(b2) ^ gm14(b3);
inv_mixw = {mb0, mb1, mb2, mb3};
end
endfunction // mixw
function [127 : 0] inv_mixcolumns(input [127 : 0] data);
reg [31 : 0] w0, w1, w2, w3;
reg [31 : 0] ws0, ws1, ws2, ws3;
begin
w0 = data[127 : 096];
w1 = data[095 : 064];
w2 = data[063 : 032];
w3 = data[031 : 000];
ws0 = inv_mixw(w0);
ws1 = inv_mixw(w1);
ws2 = inv_mixw(w2);
ws3 = inv_mixw(w3);
inv_mixcolumns = {ws0, ws1, ws2, ws3};
end
endfunction // inv_mixcolumns
function [127 : 0] inv_shiftrows(input [127 : 0] data);
reg [31 : 0] w0, w1, w2, w3;
reg [31 : 0] ws0, ws1, ws2, ws3;
begin
w0 = data[127 : 096];
w1 = data[095 : 064];
w2 = data[063 : 032];
w3 = data[031 : 000];
ws0 = {w0[31 : 24], w3[23 : 16], w2[15 : 08], w1[07 : 00]};
ws1 = {w1[31 : 24], w0[23 : 16], w3[15 : 08], w2[07 : 00]};
ws2 = {w2[31 : 24], w1[23 : 16], w0[15 : 08], w3[07 : 00]};
ws3 = {w3[31 : 24], w2[23 : 16], w1[15 : 08], w0[07 : 00]};
inv_shiftrows = {ws0, ws1, ws2, ws3};
end
endfunction // inv_shiftrows
function [127 : 0] addroundkey(input [127 : 0] data, input [127 : 0] rkey);
begin
addroundkey = data ^ rkey;
end
endfunction // addroundkey
//----------------------------------------------------------------
// Registers including update variables and write enable.
//----------------------------------------------------------------
reg [1 : 0] sword_ctr_reg;
reg [1 : 0] sword_ctr_new;
reg sword_ctr_we;
reg sword_ctr_inc;
reg sword_ctr_rst;
reg [3 : 0] round_ctr_reg;
reg [3 : 0] round_ctr_new;
reg round_ctr_we;
reg round_ctr_set;
reg round_ctr_dec;
reg [127 : 0] block_new;
reg [31 : 0] block_w0_reg;
reg [31 : 0] block_w1_reg;
reg [31 : 0] block_w2_reg;
reg [31 : 0] block_w3_reg;
reg block_w0_we;
reg block_w1_we;
reg block_w2_we;
reg block_w3_we;
reg ready_reg;
reg ready_new;
reg ready_we;
reg [1 : 0] dec_ctrl_reg;
reg [1 : 0] dec_ctrl_new;
reg dec_ctrl_we;
//----------------------------------------------------------------
// Wires.
//----------------------------------------------------------------
reg [31 : 0] tmp_sboxw;
wire [31 : 0] new_sboxw;
reg [2 : 0] update_type;
//----------------------------------------------------------------
// Instantiations.
//----------------------------------------------------------------
aes_inv_sbox inv_sbox_inst(.sboxw(tmp_sboxw), .new_sboxw(new_sboxw));
//----------------------------------------------------------------
// Concurrent connectivity for ports etc.
//----------------------------------------------------------------
assign round = round_ctr_reg;
assign new_block = {block_w0_reg, block_w1_reg, block_w2_reg, block_w3_reg};
assign ready = ready_reg;
//----------------------------------------------------------------
// reg_update
//
// Update functionality for all registers in the core.
// All registers are positive edge triggered with synchronous
// active low reset. All registers have write enable.
//----------------------------------------------------------------
always @ (posedge clk or negedge reset_n)
begin: reg_update
if (!reset_n)
begin
block_w0_reg <= 32'h0;
block_w1_reg <= 32'h0;
block_w2_reg <= 32'h0;
block_w3_reg <= 32'h0;
sword_ctr_reg <= 2'h0;
round_ctr_reg <= 4'h0;
ready_reg <= 1'b1;
dec_ctrl_reg <= CTRL_IDLE;
end
else
begin
if (block_w0_we)
block_w0_reg <= block_new[127 : 096];
if (block_w1_we)
block_w1_reg <= block_new[095 : 064];
if (block_w2_we)
block_w2_reg <= block_new[063 : 032];
if (block_w3_we)
block_w3_reg <= block_new[031 : 000];
if (sword_ctr_we)
sword_ctr_reg <= sword_ctr_new;
if (round_ctr_we)
round_ctr_reg <= round_ctr_new;
if (ready_we)
ready_reg <= ready_new;
if (dec_ctrl_we)
dec_ctrl_reg <= dec_ctrl_new;
end
end // reg_update
//----------------------------------------------------------------
// round_logic
//
// The logic needed to implement init, main and final rounds.
//----------------------------------------------------------------
always @*
begin : round_logic
reg [127 : 0] old_block, inv_shiftrows_block, inv_mixcolumns_block;
reg [127 : 0] addkey_block;
inv_shiftrows_block = 128'h0;
inv_mixcolumns_block = 128'h0;
addkey_block = 128'h0;
block_new = 128'h0;
tmp_sboxw = 32'h0;
block_w0_we = 1'b0;
block_w1_we = 1'b0;
block_w2_we = 1'b0;
block_w3_we = 1'b0;
old_block = {block_w0_reg, block_w1_reg, block_w2_reg, block_w3_reg};
// Update based on update type.
case (update_type)
// InitRound
INIT_UPDATE:
begin
old_block = block;
addkey_block = addroundkey(old_block, round_key);
inv_shiftrows_block = inv_shiftrows(addkey_block);
block_new = inv_shiftrows_block;
block_w0_we = 1'b1;
block_w1_we = 1'b1;
block_w2_we = 1'b1;
block_w3_we = 1'b1;
end
SBOX_UPDATE:
begin
block_new = {new_sboxw, new_sboxw, new_sboxw, new_sboxw};
case (sword_ctr_reg)
2'h0:
begin
tmp_sboxw = block_w0_reg;
block_w0_we = 1'b1;
end
2'h1:
begin
tmp_sboxw = block_w1_reg;
block_w1_we = 1'b1;
end
2'h2:
begin
tmp_sboxw = block_w2_reg;
block_w2_we = 1'b1;
end
2'h3:
begin
tmp_sboxw = block_w3_reg;
block_w3_we = 1'b1;
end
endcase // case (sbox_mux_ctrl_reg)
end
MAIN_UPDATE:
begin
addkey_block = addroundkey(old_block, round_key);
inv_mixcolumns_block = inv_mixcolumns(addkey_block);
inv_shiftrows_block = inv_shiftrows(inv_mixcolumns_block);
block_new = inv_shiftrows_block;
block_w0_we = 1'b1;
block_w1_we = 1'b1;
block_w2_we = 1'b1;
block_w3_we = 1'b1;
end
FINAL_UPDATE:
begin
block_new = addroundkey(old_block, round_key);
block_w0_we = 1'b1;
block_w1_we = 1'b1;
block_w2_we = 1'b1;
block_w3_we = 1'b1;
end
default:
begin
end
endcase // case (update_type)
end // round_logic
//----------------------------------------------------------------
// sword_ctr
//
// The subbytes word counter with reset and increase logic.
//----------------------------------------------------------------
always @*
begin : sword_ctr
sword_ctr_new = 2'h0;
sword_ctr_we = 1'b0;
if (sword_ctr_rst)
begin
sword_ctr_new = 2'h0;
sword_ctr_we = 1'b1;
end
else if (sword_ctr_inc)
begin
sword_ctr_new = sword_ctr_reg + 1'b1;
sword_ctr_we = 1'b1;
end
end // sword_ctr
//----------------------------------------------------------------
// round_ctr
//
// The round counter with reset and increase logic.
//----------------------------------------------------------------
always @*
begin : round_ctr
round_ctr_new = 4'h0;
round_ctr_we = 1'b0;
if (round_ctr_set)
begin
if (keylen == AES_256_BIT_KEY)
begin
round_ctr_new = AES256_ROUNDS;
end
else
begin
round_ctr_new = AES128_ROUNDS;
end
round_ctr_we = 1'b1;
end
else if (round_ctr_dec)
begin
round_ctr_new = round_ctr_reg - 1'b1;
round_ctr_we = 1'b1;
end
end // round_ctr
//----------------------------------------------------------------
// decipher_ctrl
//
// The FSM that controls the decipher operations.
//----------------------------------------------------------------
always @*
begin: decipher_ctrl
sword_ctr_inc = 1'b0;
sword_ctr_rst = 1'b0;
round_ctr_dec = 1'b0;
round_ctr_set = 1'b0;
ready_new = 1'b0;
ready_we = 1'b0;
update_type = NO_UPDATE;
dec_ctrl_new = CTRL_IDLE;
dec_ctrl_we = 1'b0;
case(dec_ctrl_reg)
CTRL_IDLE:
begin
if (next)
begin
round_ctr_set = 1'b1;
ready_new = 1'b0;
ready_we = 1'b1;
dec_ctrl_new = CTRL_INIT;
dec_ctrl_we = 1'b1;
end
end
CTRL_INIT:
begin
sword_ctr_rst = 1'b1;
update_type = INIT_UPDATE;
dec_ctrl_new = CTRL_SBOX;
dec_ctrl_we = 1'b1;
end
CTRL_SBOX:
begin
sword_ctr_inc = 1'b1;
update_type = SBOX_UPDATE;
if (sword_ctr_reg == 2'h3)
begin
round_ctr_dec = 1'b1;
dec_ctrl_new = CTRL_MAIN;
dec_ctrl_we = 1'b1;
end
end
CTRL_MAIN:
begin
sword_ctr_rst = 1'b1;
if (round_ctr_reg > 0)
begin
update_type = MAIN_UPDATE;
dec_ctrl_new = CTRL_SBOX;
dec_ctrl_we = 1'b1;
end
else
begin
update_type = FINAL_UPDATE;
ready_new = 1'b1;
ready_we = 1'b1;
dec_ctrl_new = CTRL_IDLE;
dec_ctrl_we = 1'b1;
end
end
default:
begin
// Empty. Just here to make the synthesis tool happy.
end
endcase // case (dec_ctrl_reg)
end // decipher_ctrl
endmodule // aes_decipher_block |
module aes_encipher_block(
input wire clk,
input wire reset_n,
input wire next,
input wire keylen,
output wire [3 : 0] round,
input wire [127 : 0] round_key,
output wire [31 : 0] sboxw,
input wire [31 : 0] new_sboxw,
input wire [127 : 0] block,
output wire [127 : 0] new_block,
output wire ready
);
//----------------------------------------------------------------
// Internal constant and parameter definitions.
//----------------------------------------------------------------
localparam AES_128_BIT_KEY = 1'h0;
localparam AES_256_BIT_KEY = 1'h1;
localparam AES128_ROUNDS = 4'ha;
localparam AES256_ROUNDS = 4'he;
localparam NO_UPDATE = 3'h0;
localparam INIT_UPDATE = 3'h1;
localparam SBOX_UPDATE = 3'h2;
localparam MAIN_UPDATE = 3'h3;
localparam FINAL_UPDATE = 3'h4;
localparam CTRL_IDLE = 2'h0;
localparam CTRL_INIT = 2'h1;
localparam CTRL_SBOX = 2'h2;
localparam CTRL_MAIN = 2'h3;
//----------------------------------------------------------------
// Round functions with sub functions.
//----------------------------------------------------------------
function [7 : 0] gm2(input [7 : 0] op);
begin
gm2 = {op[6 : 0], 1'b0} ^ (8'h1b & {8{op[7]}});
end
endfunction // gm2
function [7 : 0] gm3(input [7 : 0] op);
begin
gm3 = gm2(op) ^ op;
end
endfunction // gm3
function [31 : 0] mixw(input [31 : 0] w);
reg [7 : 0] b0, b1, b2, b3;
reg [7 : 0] mb0, mb1, mb2, mb3;
begin
b0 = w[31 : 24];
b1 = w[23 : 16];
b2 = w[15 : 08];
b3 = w[07 : 00];
mb0 = gm2(b0) ^ gm3(b1) ^ b2 ^ b3;
mb1 = b0 ^ gm2(b1) ^ gm3(b2) ^ b3;
mb2 = b0 ^ b1 ^ gm2(b2) ^ gm3(b3);
mb3 = gm3(b0) ^ b1 ^ b2 ^ gm2(b3);
mixw = {mb0, mb1, mb2, mb3};
end
endfunction // mixw
function [127 : 0] mixcolumns(input [127 : 0] data);
reg [31 : 0] w0, w1, w2, w3;
reg [31 : 0] ws0, ws1, ws2, ws3;
begin
w0 = data[127 : 096];
w1 = data[095 : 064];
w2 = data[063 : 032];
w3 = data[031 : 000];
ws0 = mixw(w0);
ws1 = mixw(w1);
ws2 = mixw(w2);
ws3 = mixw(w3);
mixcolumns = {ws0, ws1, ws2, ws3};
end
endfunction // mixcolumns
function [127 : 0] shiftrows(input [127 : 0] data);
reg [31 : 0] w0, w1, w2, w3;
reg [31 : 0] ws0, ws1, ws2, ws3;
begin
w0 = data[127 : 096];
w1 = data[095 : 064];
w2 = data[063 : 032];
w3 = data[031 : 000];
ws0 = {w0[31 : 24], w1[23 : 16], w2[15 : 08], w3[07 : 00]};
ws1 = {w1[31 : 24], w2[23 : 16], w3[15 : 08], w0[07 : 00]};
ws2 = {w2[31 : 24], w3[23 : 16], w0[15 : 08], w1[07 : 00]};
ws3 = {w3[31 : 24], w0[23 : 16], w1[15 : 08], w2[07 : 00]};
shiftrows = {ws0, ws1, ws2, ws3};
end
endfunction // shiftrows
function [127 : 0] addroundkey(input [127 : 0] data, input [127 : 0] rkey);
begin
addroundkey = data ^ rkey;
end
endfunction // addroundkey
//----------------------------------------------------------------
// Registers including update variables and write enable.
//----------------------------------------------------------------
reg [1 : 0] sword_ctr_reg;
reg [1 : 0] sword_ctr_new;
reg sword_ctr_we;
reg sword_ctr_inc;
reg sword_ctr_rst;
reg [3 : 0] round_ctr_reg;
reg [3 : 0] round_ctr_new;
reg round_ctr_we;
reg round_ctr_rst;
reg round_ctr_inc;
reg [127 : 0] block_new;
reg [31 : 0] block_w0_reg;
reg [31 : 0] block_w1_reg;
reg [31 : 0] block_w2_reg;
reg [31 : 0] block_w3_reg;
reg block_w0_we;
reg block_w1_we;
reg block_w2_we;
reg block_w3_we;
reg ready_reg;
reg ready_new;
reg ready_we;
reg [1 : 0] enc_ctrl_reg;
reg [1 : 0] enc_ctrl_new;
reg enc_ctrl_we;
//----------------------------------------------------------------
// Wires.
//----------------------------------------------------------------
reg [2 : 0] update_type;
reg [31 : 0] muxed_sboxw;
//----------------------------------------------------------------
// Concurrent connectivity for ports etc.
//----------------------------------------------------------------
assign round = round_ctr_reg;
assign sboxw = muxed_sboxw;
assign new_block = {block_w0_reg, block_w1_reg, block_w2_reg, block_w3_reg};
assign ready = ready_reg;
//----------------------------------------------------------------
// reg_update
//
// Update functionality for all registers in the core.
// All registers are positive edge triggered with asynchronous
// active low reset. All registers have write enable.
//----------------------------------------------------------------
always @ (posedge clk or negedge reset_n)
begin: reg_update
if (!reset_n)
begin
block_w0_reg <= 32'h0;
block_w1_reg <= 32'h0;
block_w2_reg <= 32'h0;
block_w3_reg <= 32'h0;
sword_ctr_reg <= 2'h0;
round_ctr_reg <= 4'h0;
ready_reg <= 1'b1;
enc_ctrl_reg <= CTRL_IDLE;
end
else
begin
if (block_w0_we)
block_w0_reg <= block_new[127 : 096];
if (block_w1_we)
block_w1_reg <= block_new[095 : 064];
if (block_w2_we)
block_w2_reg <= block_new[063 : 032];
if (block_w3_we)
block_w3_reg <= block_new[031 : 000];
if (sword_ctr_we)
sword_ctr_reg <= sword_ctr_new;
if (round_ctr_we)
round_ctr_reg <= round_ctr_new;
if (ready_we)
ready_reg <= ready_new;
if (enc_ctrl_we)
enc_ctrl_reg <= enc_ctrl_new;
end
end // reg_update
//----------------------------------------------------------------
// round_logic
//
// The logic needed to implement init, main and final rounds.
//----------------------------------------------------------------
always @*
begin : round_logic
reg [127 : 0] old_block, shiftrows_block, mixcolumns_block;
reg [127 : 0] addkey_init_block, addkey_main_block, addkey_final_block;
block_new = 128'h0;
muxed_sboxw = 32'h0;
block_w0_we = 1'b0;
block_w1_we = 1'b0;
block_w2_we = 1'b0;
block_w3_we = 1'b0;
old_block = {block_w0_reg, block_w1_reg, block_w2_reg, block_w3_reg};
shiftrows_block = shiftrows(old_block);
mixcolumns_block = mixcolumns(shiftrows_block);
addkey_init_block = addroundkey(block, round_key);
addkey_main_block = addroundkey(mixcolumns_block, round_key);
addkey_final_block = addroundkey(shiftrows_block, round_key);
case (update_type)
INIT_UPDATE:
begin
block_new = addkey_init_block;
block_w0_we = 1'b1;
block_w1_we = 1'b1;
block_w2_we = 1'b1;
block_w3_we = 1'b1;
end
SBOX_UPDATE:
begin
block_new = {new_sboxw, new_sboxw, new_sboxw, new_sboxw};
case (sword_ctr_reg)
2'h0:
begin
muxed_sboxw = block_w0_reg;
block_w0_we = 1'b1;
end
2'h1:
begin
muxed_sboxw = block_w1_reg;
block_w1_we = 1'b1;
end
2'h2:
begin
muxed_sboxw = block_w2_reg;
block_w2_we = 1'b1;
end
2'h3:
begin
muxed_sboxw = block_w3_reg;
block_w3_we = 1'b1;
end
endcase // case (sbox_mux_ctrl_reg)
end
MAIN_UPDATE:
begin
block_new = addkey_main_block;
block_w0_we = 1'b1;
block_w1_we = 1'b1;
block_w2_we = 1'b1;
block_w3_we = 1'b1;
end
FINAL_UPDATE:
begin
block_new = addkey_final_block;
block_w0_we = 1'b1;
block_w1_we = 1'b1;
block_w2_we = 1'b1;
block_w3_we = 1'b1;
end
default:
begin
end
endcase // case (update_type)
end // round_logic
//----------------------------------------------------------------
// sword_ctr
//
// The subbytes word counter with reset and increase logic.
//----------------------------------------------------------------
always @*
begin : sword_ctr
sword_ctr_new = 2'h0;
sword_ctr_we = 1'b0;
if (sword_ctr_rst)
begin
sword_ctr_new = 2'h0;
sword_ctr_we = 1'b1;
end
else if (sword_ctr_inc)
begin
sword_ctr_new = sword_ctr_reg + 1'b1;
sword_ctr_we = 1'b1;
end
end // sword_ctr
//----------------------------------------------------------------
// round_ctr
//
// The round counter with reset and increase logic.
//----------------------------------------------------------------
always @*
begin : round_ctr
round_ctr_new = 4'h0;
round_ctr_we = 1'b0;
if (round_ctr_rst)
begin
round_ctr_new = 4'h0;
round_ctr_we = 1'b1;
end
else if (round_ctr_inc)
begin
round_ctr_new = round_ctr_reg + 1'b1;
round_ctr_we = 1'b1;
end
end // round_ctr
//----------------------------------------------------------------
// encipher_ctrl
//
// The FSM that controls the encipher operations.
//----------------------------------------------------------------
always @*
begin: encipher_ctrl
reg [3 : 0] num_rounds;
// Default assignments.
sword_ctr_inc = 1'b0;
sword_ctr_rst = 1'b0;
round_ctr_inc = 1'b0;
round_ctr_rst = 1'b0;
ready_new = 1'b0;
ready_we = 1'b0;
update_type = NO_UPDATE;
enc_ctrl_new = CTRL_IDLE;
enc_ctrl_we = 1'b0;
if (keylen == AES_256_BIT_KEY)
begin
num_rounds = AES256_ROUNDS;
end
else
begin
num_rounds = AES128_ROUNDS;
end
case(enc_ctrl_reg)
CTRL_IDLE:
begin
if (next)
begin
round_ctr_rst = 1'b1;
ready_new = 1'b0;
ready_we = 1'b1;
enc_ctrl_new = CTRL_INIT;
enc_ctrl_we = 1'b1;
end
end
CTRL_INIT:
begin
round_ctr_inc = 1'b1;
sword_ctr_rst = 1'b1;
update_type = INIT_UPDATE;
enc_ctrl_new = CTRL_SBOX;
enc_ctrl_we = 1'b1;
end
CTRL_SBOX:
begin
sword_ctr_inc = 1'b1;
update_type = SBOX_UPDATE;
if (sword_ctr_reg == 2'h3)
begin
enc_ctrl_new = CTRL_MAIN;
enc_ctrl_we = 1'b1;
end
end
CTRL_MAIN:
begin
sword_ctr_rst = 1'b1;
round_ctr_inc = 1'b1;
if (round_ctr_reg < num_rounds)
begin
update_type = MAIN_UPDATE;
enc_ctrl_new = CTRL_SBOX;
enc_ctrl_we = 1'b1;
end
else
begin
update_type = FINAL_UPDATE;
ready_new = 1'b1;
ready_we = 1'b1;
enc_ctrl_new = CTRL_IDLE;
enc_ctrl_we = 1'b1;
end
end
default:
begin
// Empty. Just here to make the synthesis tool happy.
end
endcase // case (enc_ctrl_reg)
end // encipher_ctrl
endmodule // aes_encipher_block |
module aes_key_mem(
input wire clk,
input wire reset_n,
input wire [255 : 0] key,
input wire keylen,
input wire init,
input wire [3 : 0] round,
output wire [127 : 0] round_key,
output wire ready,
output wire [31 : 0] sboxw,
input wire [31 : 0] new_sboxw
);
//----------------------------------------------------------------
// Parameters.
//----------------------------------------------------------------
localparam AES_128_BIT_KEY = 1'h0;
localparam AES_256_BIT_KEY = 1'h1;
localparam AES_128_NUM_ROUNDS = 10;
localparam AES_256_NUM_ROUNDS = 14;
localparam CTRL_IDLE = 3'h0;
localparam CTRL_INIT = 3'h1;
localparam CTRL_GENERATE = 3'h2;
localparam CTRL_DONE = 3'h3;
//----------------------------------------------------------------
// Registers.
//----------------------------------------------------------------
reg [127 : 0] key_mem [0 : 14];
reg [127 : 0] key_mem_new;
reg key_mem_we;
reg [127 : 0] prev_key0_reg;
reg [127 : 0] prev_key0_new;
reg prev_key0_we;
reg [127 : 0] prev_key1_reg;
reg [127 : 0] prev_key1_new;
reg prev_key1_we;
reg [3 : 0] round_ctr_reg;
reg [3 : 0] round_ctr_new;
reg round_ctr_rst;
reg round_ctr_inc;
reg round_ctr_we;
reg [2 : 0] key_mem_ctrl_reg;
reg [2 : 0] key_mem_ctrl_new;
reg key_mem_ctrl_we;
reg ready_reg;
reg ready_new;
reg ready_we;
reg [7 : 0] rcon_reg;
reg [7 : 0] rcon_new;
reg rcon_we;
reg rcon_set;
reg rcon_next;
//----------------------------------------------------------------
// Wires.
//----------------------------------------------------------------
reg [31 : 0] tmp_sboxw;
reg round_key_update;
reg [127 : 0] tmp_round_key;
//----------------------------------------------------------------
// Concurrent assignments for ports.
//----------------------------------------------------------------
assign round_key = tmp_round_key;
assign ready = ready_reg;
assign sboxw = tmp_sboxw;
//----------------------------------------------------------------
// reg_update
//
// Update functionality for all registers in the core.
// All registers are positive edge triggered with asynchronous
// active low reset. All registers have write enable.
//----------------------------------------------------------------
always @ (posedge clk or negedge reset_n)
begin: reg_update
integer i;
if (!reset_n)
begin
for (i = 0 ; i <= AES_256_NUM_ROUNDS ; i = i + 1)
key_mem [i] <= 128'h0;
ready_reg <= 1'b0;
rcon_reg <= 8'h0;
round_ctr_reg <= 4'h0;
prev_key0_reg <= 128'h0;
prev_key1_reg <= 128'h0;
key_mem_ctrl_reg <= CTRL_IDLE;
end
else
begin
if (ready_we)
ready_reg <= ready_new;
if (rcon_we)
rcon_reg <= rcon_new;
if (round_ctr_we)
round_ctr_reg <= round_ctr_new;
if (key_mem_we)
key_mem[round_ctr_reg] <= key_mem_new;
if (prev_key0_we)
prev_key0_reg <= prev_key0_new;
if (prev_key1_we)
prev_key1_reg <= prev_key1_new;
if (key_mem_ctrl_we)
key_mem_ctrl_reg <= key_mem_ctrl_new;
end
end // reg_update
//----------------------------------------------------------------
// key_mem_read
//
// Combinational read port for the key memory.
//----------------------------------------------------------------
always @*
begin : key_mem_read
tmp_round_key = key_mem[round];
end // key_mem_read
//----------------------------------------------------------------
// round_key_gen
//
// The round key generator logic for AES-128 and AES-256.
//----------------------------------------------------------------
always @*
begin: round_key_gen
reg [31 : 0] w0, w1, w2, w3, w4, w5, w6, w7;
reg [31 : 0] k0, k1, k2, k3;
reg [31 : 0] rconw, rotstw, tw, trw;
// Default assignments.
key_mem_new = 128'h0;
key_mem_we = 1'b0;
prev_key0_new = 128'h0;
prev_key0_we = 1'b0;
prev_key1_new = 128'h0;
prev_key1_we = 1'b0;
k0 = 32'h0;
k1 = 32'h0;
k2 = 32'h0;
k3 = 32'h0;
rcon_set = 1'b1;
rcon_next = 1'b0;
// Extract words and calculate intermediate values.
// Perform rotation of sbox word etc.
w0 = prev_key0_reg[127 : 096];
w1 = prev_key0_reg[095 : 064];
w2 = prev_key0_reg[063 : 032];
w3 = prev_key0_reg[031 : 000];
w4 = prev_key1_reg[127 : 096];
w5 = prev_key1_reg[095 : 064];
w6 = prev_key1_reg[063 : 032];
w7 = prev_key1_reg[031 : 000];
rconw = {rcon_reg, 24'h0};
tmp_sboxw = w7;
rotstw = {new_sboxw[23 : 00], new_sboxw[31 : 24]};
trw = rotstw ^ rconw;
tw = new_sboxw;
// Generate the specific round keys.
if (round_key_update)
begin
rcon_set = 1'b0;
key_mem_we = 1'b1;
case (keylen)
AES_128_BIT_KEY:
begin
if (round_ctr_reg == 0)
begin
key_mem_new = key[255 : 128];
prev_key1_new = key[255 : 128];
prev_key1_we = 1'b1;
rcon_next = 1'b1;
end
else
begin
k0 = w4 ^ trw;
k1 = w5 ^ w4 ^ trw;
k2 = w6 ^ w5 ^ w4 ^ trw;
k3 = w7 ^ w6 ^ w5 ^ w4 ^ trw;
key_mem_new = {k0, k1, k2, k3};
prev_key1_new = {k0, k1, k2, k3};
prev_key1_we = 1'b1;
rcon_next = 1'b1;
end
end
AES_256_BIT_KEY:
begin
if (round_ctr_reg == 0)
begin
key_mem_new = key[255 : 128];
prev_key0_new = key[255 : 128];
prev_key0_we = 1'b1;
end
else if (round_ctr_reg == 1)
begin
key_mem_new = key[127 : 0];
prev_key1_new = key[127 : 0];
prev_key1_we = 1'b1;
rcon_next = 1'b1;
end
else
begin
if (round_ctr_reg[0] == 0)
begin
k0 = w0 ^ trw;
k1 = w1 ^ w0 ^ trw;
k2 = w2 ^ w1 ^ w0 ^ trw;
k3 = w3 ^ w2 ^ w1 ^ w0 ^ trw;
end
else
begin
k0 = w0 ^ tw;
k1 = w1 ^ w0 ^ tw;
k2 = w2 ^ w1 ^ w0 ^ tw;
k3 = w3 ^ w2 ^ w1 ^ w0 ^ tw;
rcon_next = 1'b1;
end
// Store the generated round keys.
key_mem_new = {k0, k1, k2, k3};
prev_key1_new = {k0, k1, k2, k3};
prev_key1_we = 1'b1;
prev_key0_new = prev_key1_reg;
prev_key0_we = 1'b1;
end
end
default:
begin
end
endcase // case (keylen)
end
end // round_key_gen
//----------------------------------------------------------------
// rcon_logic
//
// Caclulates the rcon value for the different key expansion
// iterations.
//----------------------------------------------------------------
always @*
begin : rcon_logic
reg [7 : 0] tmp_rcon;
rcon_new = 8'h00;
rcon_we = 1'b0;
tmp_rcon = {rcon_reg[6 : 0], 1'b0} ^ (8'h1b & {8{rcon_reg[7]}});
if (rcon_set)
begin
rcon_new = 8'h8d;
rcon_we = 1'b1;
end
if (rcon_next)
begin
rcon_new = tmp_rcon[7 : 0];
rcon_we = 1'b1;
end
end
//----------------------------------------------------------------
// round_ctr
//
// The round counter logic with increase and reset.
//----------------------------------------------------------------
always @*
begin : round_ctr
round_ctr_new = 4'h0;
round_ctr_we = 1'b0;
if (round_ctr_rst)
begin
round_ctr_new = 4'h0;
round_ctr_we = 1'b1;
end
else if (round_ctr_inc)
begin
round_ctr_new = round_ctr_reg + 1'b1;
round_ctr_we = 1'b1;
end
end
//----------------------------------------------------------------
// key_mem_ctrl
//
//
// The FSM that controls the round key generation.
//----------------------------------------------------------------
always @*
begin: key_mem_ctrl
reg [3 : 0] num_rounds;
// Default assignments.
ready_new = 1'b0;
ready_we = 1'b0;
round_key_update = 1'b0;
round_ctr_rst = 1'b0;
round_ctr_inc = 1'b0;
key_mem_ctrl_new = CTRL_IDLE;
key_mem_ctrl_we = 1'b0;
if (keylen == AES_128_BIT_KEY)
num_rounds = AES_128_NUM_ROUNDS;
else
num_rounds = AES_256_NUM_ROUNDS;
case(key_mem_ctrl_reg)
CTRL_IDLE:
begin
if (init)
begin
ready_new = 1'b0;
ready_we = 1'b1;
key_mem_ctrl_new = CTRL_INIT;
key_mem_ctrl_we = 1'b1;
end
end
CTRL_INIT:
begin
round_ctr_rst = 1'b1;
key_mem_ctrl_new = CTRL_GENERATE;
key_mem_ctrl_we = 1'b1;
end
CTRL_GENERATE:
begin
round_ctr_inc = 1'b1;
round_key_update = 1'b1;
if (round_ctr_reg == num_rounds)
begin
key_mem_ctrl_new = CTRL_DONE;
key_mem_ctrl_we = 1'b1;
end
end
CTRL_DONE:
begin
ready_new = 1'b1;
ready_we = 1'b1;
key_mem_ctrl_new = CTRL_IDLE;
key_mem_ctrl_we = 1'b1;
end
default:
begin
end
endcase // case (key_mem_ctrl_reg)
end // key_mem_ctrl
endmodule // aes_key_mem |
module aes_inv_sbox(
input wire [31 : 0] sboxw,
output wire [31 : 0] new_sboxw
);
//----------------------------------------------------------------
// The inverse sbox array.
//----------------------------------------------------------------
wire [7 : 0] inv_sbox [0 : 255];
//----------------------------------------------------------------
// Four parallel muxes.
//----------------------------------------------------------------
assign new_sboxw[31 : 24] = inv_sbox[sboxw[31 : 24]];
assign new_sboxw[23 : 16] = inv_sbox[sboxw[23 : 16]];
assign new_sboxw[15 : 08] = inv_sbox[sboxw[15 : 08]];
assign new_sboxw[07 : 00] = inv_sbox[sboxw[07 : 00]];
//----------------------------------------------------------------
// Creating the contents of the array.
//----------------------------------------------------------------
assign inv_sbox[8'h00] = 8'h52;
assign inv_sbox[8'h01] = 8'h09;
assign inv_sbox[8'h02] = 8'h6a;
assign inv_sbox[8'h03] = 8'hd5;
assign inv_sbox[8'h04] = 8'h30;
assign inv_sbox[8'h05] = 8'h36;
assign inv_sbox[8'h06] = 8'ha5;
assign inv_sbox[8'h07] = 8'h38;
assign inv_sbox[8'h08] = 8'hbf;
assign inv_sbox[8'h09] = 8'h40;
assign inv_sbox[8'h0a] = 8'ha3;
assign inv_sbox[8'h0b] = 8'h9e;
assign inv_sbox[8'h0c] = 8'h81;
assign inv_sbox[8'h0d] = 8'hf3;
assign inv_sbox[8'h0e] = 8'hd7;
assign inv_sbox[8'h0f] = 8'hfb;
assign inv_sbox[8'h10] = 8'h7c;
assign inv_sbox[8'h11] = 8'he3;
assign inv_sbox[8'h12] = 8'h39;
assign inv_sbox[8'h13] = 8'h82;
assign inv_sbox[8'h14] = 8'h9b;
assign inv_sbox[8'h15] = 8'h2f;
assign inv_sbox[8'h16] = 8'hff;
assign inv_sbox[8'h17] = 8'h87;
assign inv_sbox[8'h18] = 8'h34;
assign inv_sbox[8'h19] = 8'h8e;
assign inv_sbox[8'h1a] = 8'h43;
assign inv_sbox[8'h1b] = 8'h44;
assign inv_sbox[8'h1c] = 8'hc4;
assign inv_sbox[8'h1d] = 8'hde;
assign inv_sbox[8'h1e] = 8'he9;
assign inv_sbox[8'h1f] = 8'hcb;
assign inv_sbox[8'h20] = 8'h54;
assign inv_sbox[8'h21] = 8'h7b;
assign inv_sbox[8'h22] = 8'h94;
assign inv_sbox[8'h23] = 8'h32;
assign inv_sbox[8'h24] = 8'ha6;
assign inv_sbox[8'h25] = 8'hc2;
assign inv_sbox[8'h26] = 8'h23;
assign inv_sbox[8'h27] = 8'h3d;
assign inv_sbox[8'h28] = 8'hee;
assign inv_sbox[8'h29] = 8'h4c;
assign inv_sbox[8'h2a] = 8'h95;
assign inv_sbox[8'h2b] = 8'h0b;
assign inv_sbox[8'h2c] = 8'h42;
assign inv_sbox[8'h2d] = 8'hfa;
assign inv_sbox[8'h2e] = 8'hc3;
assign inv_sbox[8'h2f] = 8'h4e;
assign inv_sbox[8'h30] = 8'h08;
assign inv_sbox[8'h31] = 8'h2e;
assign inv_sbox[8'h32] = 8'ha1;
assign inv_sbox[8'h33] = 8'h66;
assign inv_sbox[8'h34] = 8'h28;
assign inv_sbox[8'h35] = 8'hd9;
assign inv_sbox[8'h36] = 8'h24;
assign inv_sbox[8'h37] = 8'hb2;
assign inv_sbox[8'h38] = 8'h76;
assign inv_sbox[8'h39] = 8'h5b;
assign inv_sbox[8'h3a] = 8'ha2;
assign inv_sbox[8'h3b] = 8'h49;
assign inv_sbox[8'h3c] = 8'h6d;
assign inv_sbox[8'h3d] = 8'h8b;
assign inv_sbox[8'h3e] = 8'hd1;
assign inv_sbox[8'h3f] = 8'h25;
assign inv_sbox[8'h40] = 8'h72;
assign inv_sbox[8'h41] = 8'hf8;
assign inv_sbox[8'h42] = 8'hf6;
assign inv_sbox[8'h43] = 8'h64;
assign inv_sbox[8'h44] = 8'h86;
assign inv_sbox[8'h45] = 8'h68;
assign inv_sbox[8'h46] = 8'h98;
assign inv_sbox[8'h47] = 8'h16;
assign inv_sbox[8'h48] = 8'hd4;
assign inv_sbox[8'h49] = 8'ha4;
assign inv_sbox[8'h4a] = 8'h5c;
assign inv_sbox[8'h4b] = 8'hcc;
assign inv_sbox[8'h4c] = 8'h5d;
assign inv_sbox[8'h4d] = 8'h65;
assign inv_sbox[8'h4e] = 8'hb6;
assign inv_sbox[8'h4f] = 8'h92;
assign inv_sbox[8'h50] = 8'h6c;
assign inv_sbox[8'h51] = 8'h70;
assign inv_sbox[8'h52] = 8'h48;
assign inv_sbox[8'h53] = 8'h50;
assign inv_sbox[8'h54] = 8'hfd;
assign inv_sbox[8'h55] = 8'hed;
assign inv_sbox[8'h56] = 8'hb9;
assign inv_sbox[8'h57] = 8'hda;
assign inv_sbox[8'h58] = 8'h5e;
assign inv_sbox[8'h59] = 8'h15;
assign inv_sbox[8'h5a] = 8'h46;
assign inv_sbox[8'h5b] = 8'h57;
assign inv_sbox[8'h5c] = 8'ha7;
assign inv_sbox[8'h5d] = 8'h8d;
assign inv_sbox[8'h5e] = 8'h9d;
assign inv_sbox[8'h5f] = 8'h84;
assign inv_sbox[8'h60] = 8'h90;
assign inv_sbox[8'h61] = 8'hd8;
assign inv_sbox[8'h62] = 8'hab;
assign inv_sbox[8'h63] = 8'h00;
assign inv_sbox[8'h64] = 8'h8c;
assign inv_sbox[8'h65] = 8'hbc;
assign inv_sbox[8'h66] = 8'hd3;
assign inv_sbox[8'h67] = 8'h0a;
assign inv_sbox[8'h68] = 8'hf7;
assign inv_sbox[8'h69] = 8'he4;
assign inv_sbox[8'h6a] = 8'h58;
assign inv_sbox[8'h6b] = 8'h05;
assign inv_sbox[8'h6c] = 8'hb8;
assign inv_sbox[8'h6d] = 8'hb3;
assign inv_sbox[8'h6e] = 8'h45;
assign inv_sbox[8'h6f] = 8'h06;
assign inv_sbox[8'h70] = 8'hd0;
assign inv_sbox[8'h71] = 8'h2c;
assign inv_sbox[8'h72] = 8'h1e;
assign inv_sbox[8'h73] = 8'h8f;
assign inv_sbox[8'h74] = 8'hca;
assign inv_sbox[8'h75] = 8'h3f;
assign inv_sbox[8'h76] = 8'h0f;
assign inv_sbox[8'h77] = 8'h02;
assign inv_sbox[8'h78] = 8'hc1;
assign inv_sbox[8'h79] = 8'haf;
assign inv_sbox[8'h7a] = 8'hbd;
assign inv_sbox[8'h7b] = 8'h03;
assign inv_sbox[8'h7c] = 8'h01;
assign inv_sbox[8'h7d] = 8'h13;
assign inv_sbox[8'h7e] = 8'h8a;
assign inv_sbox[8'h7f] = 8'h6b;
assign inv_sbox[8'h80] = 8'h3a;
assign inv_sbox[8'h81] = 8'h91;
assign inv_sbox[8'h82] = 8'h11;
assign inv_sbox[8'h83] = 8'h41;
assign inv_sbox[8'h84] = 8'h4f;
assign inv_sbox[8'h85] = 8'h67;
assign inv_sbox[8'h86] = 8'hdc;
assign inv_sbox[8'h87] = 8'hea;
assign inv_sbox[8'h88] = 8'h97;
assign inv_sbox[8'h89] = 8'hf2;
assign inv_sbox[8'h8a] = 8'hcf;
assign inv_sbox[8'h8b] = 8'hce;
assign inv_sbox[8'h8c] = 8'hf0;
assign inv_sbox[8'h8d] = 8'hb4;
assign inv_sbox[8'h8e] = 8'he6;
assign inv_sbox[8'h8f] = 8'h73;
assign inv_sbox[8'h90] = 8'h96;
assign inv_sbox[8'h91] = 8'hac;
assign inv_sbox[8'h92] = 8'h74;
assign inv_sbox[8'h93] = 8'h22;
assign inv_sbox[8'h94] = 8'he7;
assign inv_sbox[8'h95] = 8'had;
assign inv_sbox[8'h96] = 8'h35;
assign inv_sbox[8'h97] = 8'h85;
assign inv_sbox[8'h98] = 8'he2;
assign inv_sbox[8'h99] = 8'hf9;
assign inv_sbox[8'h9a] = 8'h37;
assign inv_sbox[8'h9b] = 8'he8;
assign inv_sbox[8'h9c] = 8'h1c;
assign inv_sbox[8'h9d] = 8'h75;
assign inv_sbox[8'h9e] = 8'hdf;
assign inv_sbox[8'h9f] = 8'h6e;
assign inv_sbox[8'ha0] = 8'h47;
assign inv_sbox[8'ha1] = 8'hf1;
assign inv_sbox[8'ha2] = 8'h1a;
assign inv_sbox[8'ha3] = 8'h71;
assign inv_sbox[8'ha4] = 8'h1d;
assign inv_sbox[8'ha5] = 8'h29;
assign inv_sbox[8'ha6] = 8'hc5;
assign inv_sbox[8'ha7] = 8'h89;
assign inv_sbox[8'ha8] = 8'h6f;
assign inv_sbox[8'ha9] = 8'hb7;
assign inv_sbox[8'haa] = 8'h62;
assign inv_sbox[8'hab] = 8'h0e;
assign inv_sbox[8'hac] = 8'haa;
assign inv_sbox[8'had] = 8'h18;
assign inv_sbox[8'hae] = 8'hbe;
assign inv_sbox[8'haf] = 8'h1b;
assign inv_sbox[8'hb0] = 8'hfc;
assign inv_sbox[8'hb1] = 8'h56;
assign inv_sbox[8'hb2] = 8'h3e;
assign inv_sbox[8'hb3] = 8'h4b;
assign inv_sbox[8'hb4] = 8'hc6;
assign inv_sbox[8'hb5] = 8'hd2;
assign inv_sbox[8'hb6] = 8'h79;
assign inv_sbox[8'hb7] = 8'h20;
assign inv_sbox[8'hb8] = 8'h9a;
assign inv_sbox[8'hb9] = 8'hdb;
assign inv_sbox[8'hba] = 8'hc0;
assign inv_sbox[8'hbb] = 8'hfe;
assign inv_sbox[8'hbc] = 8'h78;
assign inv_sbox[8'hbd] = 8'hcd;
assign inv_sbox[8'hbe] = 8'h5a;
assign inv_sbox[8'hbf] = 8'hf4;
assign inv_sbox[8'hc0] = 8'h1f;
assign inv_sbox[8'hc1] = 8'hdd;
assign inv_sbox[8'hc2] = 8'ha8;
assign inv_sbox[8'hc3] = 8'h33;
assign inv_sbox[8'hc4] = 8'h88;
assign inv_sbox[8'hc5] = 8'h07;
assign inv_sbox[8'hc6] = 8'hc7;
assign inv_sbox[8'hc7] = 8'h31;
assign inv_sbox[8'hc8] = 8'hb1;
assign inv_sbox[8'hc9] = 8'h12;
assign inv_sbox[8'hca] = 8'h10;
assign inv_sbox[8'hcb] = 8'h59;
assign inv_sbox[8'hcc] = 8'h27;
assign inv_sbox[8'hcd] = 8'h80;
assign inv_sbox[8'hce] = 8'hec;
assign inv_sbox[8'hcf] = 8'h5f;
assign inv_sbox[8'hd0] = 8'h60;
assign inv_sbox[8'hd1] = 8'h51;
assign inv_sbox[8'hd2] = 8'h7f;
assign inv_sbox[8'hd3] = 8'ha9;
assign inv_sbox[8'hd4] = 8'h19;
assign inv_sbox[8'hd5] = 8'hb5;
assign inv_sbox[8'hd6] = 8'h4a;
assign inv_sbox[8'hd7] = 8'h0d;
assign inv_sbox[8'hd8] = 8'h2d;
assign inv_sbox[8'hd9] = 8'he5;
assign inv_sbox[8'hda] = 8'h7a;
assign inv_sbox[8'hdb] = 8'h9f;
assign inv_sbox[8'hdc] = 8'h93;
assign inv_sbox[8'hdd] = 8'hc9;
assign inv_sbox[8'hde] = 8'h9c;
assign inv_sbox[8'hdf] = 8'hef;
assign inv_sbox[8'he0] = 8'ha0;
assign inv_sbox[8'he1] = 8'he0;
assign inv_sbox[8'he2] = 8'h3b;
assign inv_sbox[8'he3] = 8'h4d;
assign inv_sbox[8'he4] = 8'hae;
assign inv_sbox[8'he5] = 8'h2a;
assign inv_sbox[8'he6] = 8'hf5;
assign inv_sbox[8'he7] = 8'hb0;
assign inv_sbox[8'he8] = 8'hc8;
assign inv_sbox[8'he9] = 8'heb;
assign inv_sbox[8'hea] = 8'hbb;
assign inv_sbox[8'heb] = 8'h3c;
assign inv_sbox[8'hec] = 8'h83;
assign inv_sbox[8'hed] = 8'h53;
assign inv_sbox[8'hee] = 8'h99;
assign inv_sbox[8'hef] = 8'h61;
assign inv_sbox[8'hf0] = 8'h17;
assign inv_sbox[8'hf1] = 8'h2b;
assign inv_sbox[8'hf2] = 8'h04;
assign inv_sbox[8'hf3] = 8'h7e;
assign inv_sbox[8'hf4] = 8'hba;
assign inv_sbox[8'hf5] = 8'h77;
assign inv_sbox[8'hf6] = 8'hd6;
assign inv_sbox[8'hf7] = 8'h26;
assign inv_sbox[8'hf8] = 8'he1;
assign inv_sbox[8'hf9] = 8'h69;
assign inv_sbox[8'hfa] = 8'h14;
assign inv_sbox[8'hfb] = 8'h63;
assign inv_sbox[8'hfc] = 8'h55;
assign inv_sbox[8'hfd] = 8'h21;
assign inv_sbox[8'hfe] = 8'h0c;
assign inv_sbox[8'hff] = 8'h7d;
endmodule // aes_inv_sbox |
module binary_tower_32b_sqr (
ap_clk,
ap_ce,
a,
ap_return,
ap_rst
);
input ap_clk;
input ap_ce;
input [31:0] a;
output [31:0] ap_return;
input ap_rst;
wire [0:0] a0_42_fu_114_p1;
wire [0:0] a1_36_fu_118_p3;
wire [0:0] xor_ln59_fu_126_p2;
wire [0:0] a0_43_fu_140_p3;
wire [0:0] a1_fu_148_p3;
wire [0:0] a0_fu_156_p2;
wire [1:0] a1_sqr_29_fu_162_p3;
wire [1:0] a0_sqr_1_fu_132_p3;
reg [1:0] tmp_fu_176_p4;
wire [1:0] xor_ln59_2_fu_170_p2;
wire [0:0] a0_44_fu_194_p3;
wire [0:0] a1_37_fu_202_p3;
wire [0:0] xor_ln59_3_fu_210_p2;
wire [0:0] a0_45_fu_224_p3;
wire [0:0] a1_38_fu_232_p3;
wire [0:0] a0_5_fu_240_p2;
wire [1:0] a1_sqr_30_fu_246_p3;
wire [1:0] a0_sqr_5_fu_216_p3;
reg [1:0] tmp_16_fu_260_p4;
wire [1:0] a0_6_fu_254_p2;
wire [1:0] tmp_6_fu_278_p3;
wire [3:0] a1_sqr_31_fu_270_p3;
wire [3:0] a0_sqr_3_fu_186_p3;
wire [1:0] xor_ln28_fu_286_p2;
wire [3:0] xor_ln59_6_fu_292_p2;
wire [0:0] a0_46_fu_308_p3;
wire [0:0] a1_39_fu_316_p3;
wire [0:0] xor_ln59_7_fu_324_p2;
wire [0:0] a0_47_fu_338_p3;
wire [0:0] a1_7_fu_346_p3;
wire [0:0] a0_10_fu_354_p2;
wire [1:0] a1_sqr_32_fu_360_p3;
wire [1:0] a0_sqr_9_fu_330_p3;
reg [1:0] tmp_21_fu_374_p4;
wire [1:0] xor_ln59_9_fu_368_p2;
wire [0:0] a0_48_fu_392_p3;
wire [0:0] a1_40_fu_400_p3;
wire [0:0] xor_ln59_10_fu_408_p2;
wire [0:0] a0_49_fu_422_p3;
wire [0:0] a1_41_fu_430_p3;
wire [0:0] a0_13_fu_438_p2;
wire [1:0] a1_sqr_33_fu_444_p3;
wire [1:0] a0_sqr_13_fu_414_p3;
reg [1:0] a1_42_fu_458_p4;
wire [1:0] a0_14_fu_452_p2;
wire [1:0] tmp_2_fu_476_p3;
wire [3:0] a1_sqr_34_fu_468_p3;
wire [3:0] a0_sqr_11_fu_384_p3;
wire [1:0] a1_43_fu_484_p2;
wire [3:0] a0_16_fu_490_p2;
wire [0:0] a0_18_fu_506_p1;
wire [0:0] a1_14_fu_510_p3;
wire [0:0] xor_ln28_2_fu_518_p2;
wire [1:0] tmp_5_fu_524_p3;
wire [1:0] xor_ln28_3_fu_532_p2;
wire [3:0] tmp_8_fu_538_p3;
wire [7:0] a1_sqr_35_fu_496_p4;
wire [7:0] a0_sqr_7_fu_298_p4;
wire [3:0] xor_ln28_4_fu_546_p2;
wire [7:0] xor_ln59_14_fu_552_p2;
wire [0:0] a0_50_fu_570_p3;
wire [0:0] a1_44_fu_578_p3;
wire [0:0] xor_ln59_15_fu_586_p2;
wire [0:0] a0_51_fu_600_p3;
wire [0:0] a1_17_fu_608_p3;
wire [0:0] a0_21_fu_616_p2;
wire [1:0] a1_sqr_36_fu_622_p3;
wire [1:0] a0_sqr_17_fu_592_p3;
reg [1:0] tmp_32_fu_636_p4;
wire [1:0] xor_ln59_17_fu_630_p2;
wire [0:0] a0_52_fu_654_p3;
wire [0:0] a1_45_fu_662_p3;
wire [0:0] xor_ln59_18_fu_670_p2;
wire [0:0] a0_53_fu_684_p3;
wire [0:0] a1_46_fu_692_p3;
wire [0:0] a0_24_fu_700_p2;
wire [1:0] a1_sqr_37_fu_706_p3;
wire [1:0] a0_sqr_21_fu_676_p3;
reg [1:0] tmp_37_fu_720_p4;
wire [1:0] a0_25_fu_714_p2;
wire [1:0] tmp_s_fu_738_p3;
wire [3:0] a1_sqr_38_fu_730_p3;
wire [3:0] a0_sqr_19_fu_646_p3;
wire [1:0] xor_ln28_5_fu_746_p2;
wire [3:0] xor_ln59_21_fu_752_p2;
wire [0:0] a0_54_fu_768_p3;
wire [0:0] a1_47_fu_776_p3;
wire [0:0] xor_ln59_22_fu_784_p2;
wire [0:0] a0_55_fu_798_p3;
wire [0:0] a1_24_fu_806_p3;
wire [0:0] a0_29_fu_814_p2;
wire [1:0] a1_sqr_fu_820_p3;
wire [1:0] a0_sqr_25_fu_790_p3;
reg [1:0] tmp_42_fu_834_p4;
wire [1:0] xor_ln59_24_fu_828_p2;
wire [0:0] a0_56_fu_852_p3;
wire [0:0] a1_48_fu_860_p3;
wire [0:0] xor_ln59_25_fu_868_p2;
wire [0:0] a0_57_fu_882_p3;
wire [0:0] a1_49_fu_890_p3;
wire [0:0] a0_32_fu_898_p2;
wire [1:0] a1_sqr_39_fu_904_p3;
wire [1:0] a0_sqr_29_fu_874_p3;
reg [1:0] a1_50_fu_918_p4;
wire [1:0] a0_33_fu_912_p2;
wire [1:0] tmp_1_fu_936_p3;
wire [3:0] a1_sqr_40_fu_928_p3;
wire [3:0] a0_sqr_27_fu_844_p3;
wire [1:0] a1_52_fu_944_p2;
wire [3:0] a0_35_fu_950_p2;
wire [0:0] a0_37_fu_974_p1;
wire [0:0] a1_32_fu_978_p3;
wire [0:0] xor_ln28_7_fu_986_p2;
wire [1:0] tmp_3_fu_992_p3;
wire [1:0] xor_ln28_8_fu_1000_p2;
wire [3:0] tmp_4_fu_1006_p3;
wire [7:0] a1_sqr_41_fu_956_p4;
wire [7:0] a0_sqr_23_fu_758_p4;
wire [3:0] a1_53_fu_1014_p2;
wire [7:0] a0_38_fu_1020_p2;
wire [0:0] a0_41_fu_1052_p3;
wire [0:0] a1_35_fu_1060_p3;
wire [0:0] xor_ln28_10_fu_1068_p2;
wire [1:0] a0_40_fu_1038_p1;
wire [1:0] tmp_7_fu_1074_p3;
wire [1:0] xor_ln28_11_fu_1082_p2;
wire [1:0] a1_54_fu_1042_p4;
wire [3:0] a1_51_fu_966_p3;
wire [3:0] tmp_9_fu_1088_p3;
wire [3:0] xor_ln28_12_fu_1096_p2;
wire [7:0] tmp_10_fu_1102_p3;
wire [15:0] a1_sqr_42_fu_1026_p5;
wire [15:0] a0_sqr_15_fu_558_p5;
wire [7:0] xor_ln28_13_fu_1110_p2;
wire [15:0] xor_ln59_30_fu_1116_p2;
assign a0_10_fu_354_p2 = (a1_7_fu_346_p3 ^ a0_47_fu_338_p3);
assign a0_13_fu_438_p2 = (a1_41_fu_430_p3 ^ a0_49_fu_422_p3);
assign a0_14_fu_452_p2 = (a1_sqr_33_fu_444_p3 ^ a0_sqr_13_fu_414_p3);
assign a0_16_fu_490_p2 = (a1_sqr_34_fu_468_p3 ^ a0_sqr_11_fu_384_p3);
assign a0_18_fu_506_p1 = a1_43_fu_484_p2[0:0];
assign a0_21_fu_616_p2 = (a1_17_fu_608_p3 ^ a0_51_fu_600_p3);
assign a0_24_fu_700_p2 = (a1_46_fu_692_p3 ^ a0_53_fu_684_p3);
assign a0_25_fu_714_p2 = (a1_sqr_37_fu_706_p3 ^ a0_sqr_21_fu_676_p3);
assign a0_29_fu_814_p2 = (a1_24_fu_806_p3 ^ a0_55_fu_798_p3);
assign a0_32_fu_898_p2 = (a1_49_fu_890_p3 ^ a0_57_fu_882_p3);
assign a0_33_fu_912_p2 = (a1_sqr_39_fu_904_p3 ^ a0_sqr_29_fu_874_p3);
assign a0_35_fu_950_p2 = (a1_sqr_40_fu_928_p3 ^ a0_sqr_27_fu_844_p3);
assign a0_37_fu_974_p1 = a1_52_fu_944_p2[0:0];
assign a0_38_fu_1020_p2 = (a1_sqr_41_fu_956_p4 ^ a0_sqr_23_fu_758_p4);
assign a0_40_fu_1038_p1 = a1_53_fu_1014_p2[1:0];
assign a0_41_fu_1052_p3 = a1_53_fu_1014_p2[32'd2];
assign a0_42_fu_114_p1 = a[0:0];
assign a0_43_fu_140_p3 = a[32'd2];
assign a0_44_fu_194_p3 = a[32'd4];
assign a0_45_fu_224_p3 = a[32'd6];
assign a0_46_fu_308_p3 = a[32'd8];
assign a0_47_fu_338_p3 = a[32'd10];
assign a0_48_fu_392_p3 = a[32'd12];
assign a0_49_fu_422_p3 = a[32'd14];
assign a0_50_fu_570_p3 = a[32'd16];
assign a0_51_fu_600_p3 = a[32'd18];
assign a0_52_fu_654_p3 = a[32'd20];
assign a0_53_fu_684_p3 = a[32'd22];
assign a0_54_fu_768_p3 = a[32'd24];
assign a0_55_fu_798_p3 = a[32'd26];
assign a0_56_fu_852_p3 = a[32'd28];
assign a0_57_fu_882_p3 = a[32'd30];
assign a0_5_fu_240_p2 = (a1_38_fu_232_p3 ^ a0_45_fu_224_p3);
assign a0_6_fu_254_p2 = (a1_sqr_30_fu_246_p3 ^ a0_sqr_5_fu_216_p3);
assign a0_fu_156_p2 = (a1_fu_148_p3 ^ a0_43_fu_140_p3);
assign a0_sqr_11_fu_384_p3 = {{tmp_21_fu_374_p4}, {xor_ln59_9_fu_368_p2}};
assign a0_sqr_13_fu_414_p3 = {{a1_40_fu_400_p3}, {xor_ln59_10_fu_408_p2}};
assign a0_sqr_15_fu_558_p5 = {{{{xor_ln28_4_fu_546_p2}, {a1_43_fu_484_p2}}, {a1_42_fu_458_p4}}, {xor_ln59_14_fu_552_p2}};
assign a0_sqr_17_fu_592_p3 = {{a1_44_fu_578_p3}, {xor_ln59_15_fu_586_p2}};
assign a0_sqr_19_fu_646_p3 = {{tmp_32_fu_636_p4}, {xor_ln59_17_fu_630_p2}};
assign a0_sqr_1_fu_132_p3 = {{a1_36_fu_118_p3}, {xor_ln59_fu_126_p2}};
assign a0_sqr_21_fu_676_p3 = {{a1_45_fu_662_p3}, {xor_ln59_18_fu_670_p2}};
assign a0_sqr_23_fu_758_p4 = {{{xor_ln28_5_fu_746_p2}, {tmp_37_fu_720_p4}}, {xor_ln59_21_fu_752_p2}};
assign a0_sqr_25_fu_790_p3 = {{a1_47_fu_776_p3}, {xor_ln59_22_fu_784_p2}};
assign a0_sqr_27_fu_844_p3 = {{tmp_42_fu_834_p4}, {xor_ln59_24_fu_828_p2}};
assign a0_sqr_29_fu_874_p3 = {{a1_48_fu_860_p3}, {xor_ln59_25_fu_868_p2}};
assign a0_sqr_3_fu_186_p3 = {{tmp_fu_176_p4}, {xor_ln59_2_fu_170_p2}};
assign a0_sqr_5_fu_216_p3 = {{a1_37_fu_202_p3}, {xor_ln59_3_fu_210_p2}};
assign a0_sqr_7_fu_298_p4 = {{{xor_ln28_fu_286_p2}, {tmp_16_fu_260_p4}}, {xor_ln59_6_fu_292_p2}};
assign a0_sqr_9_fu_330_p3 = {{a1_39_fu_316_p3}, {xor_ln59_7_fu_324_p2}};
assign a1_14_fu_510_p3 = a1_43_fu_484_p2[32'd1];
assign a1_17_fu_608_p3 = a[32'd19];
assign a1_24_fu_806_p3 = a[32'd27];
assign a1_32_fu_978_p3 = a1_52_fu_944_p2[32'd1];
assign a1_35_fu_1060_p3 = a1_53_fu_1014_p2[32'd3];
assign a1_36_fu_118_p3 = a[32'd1];
assign a1_37_fu_202_p3 = a[32'd5];
assign a1_38_fu_232_p3 = a[32'd7];
assign a1_39_fu_316_p3 = a[32'd9];
assign a1_40_fu_400_p3 = a[32'd13];
assign a1_41_fu_430_p3 = a[32'd15];
integer ap_tvar_int_0;
always @ (a) begin
for (ap_tvar_int_0 = 2 - 1; ap_tvar_int_0 >= 0; ap_tvar_int_0 = ap_tvar_int_0 - 1) begin
if (ap_tvar_int_0 > 15 - 14) begin
a1_42_fu_458_p4[ap_tvar_int_0] = 1'b0;
end else begin
a1_42_fu_458_p4[ap_tvar_int_0] = a[15 - ap_tvar_int_0];
end
end
end
assign a1_43_fu_484_p2 = (tmp_2_fu_476_p3 ^ a0_14_fu_452_p2);
assign a1_44_fu_578_p3 = a[32'd17];
assign a1_45_fu_662_p3 = a[32'd21];
assign a1_46_fu_692_p3 = a[32'd23];
assign a1_47_fu_776_p3 = a[32'd25];
assign a1_48_fu_860_p3 = a[32'd29];
assign a1_49_fu_890_p3 = a[32'd31];
integer ap_tvar_int_1;
always @ (a) begin
for (ap_tvar_int_1 = 2 - 1; ap_tvar_int_1 >= 0; ap_tvar_int_1 = ap_tvar_int_1 - 1) begin
if (ap_tvar_int_1 > 31 - 30) begin
a1_50_fu_918_p4[ap_tvar_int_1] = 1'b0;
end else begin
a1_50_fu_918_p4[ap_tvar_int_1] = a[31 - ap_tvar_int_1];
end
end
end
assign a1_51_fu_966_p3 = {{a1_52_fu_944_p2}, {a1_50_fu_918_p4}};
assign a1_52_fu_944_p2 = (tmp_1_fu_936_p3 ^ a0_33_fu_912_p2);
assign a1_53_fu_1014_p2 = (tmp_4_fu_1006_p3 ^ a0_35_fu_950_p2);
assign a1_54_fu_1042_p4 = {{a1_53_fu_1014_p2[3:2]}};
assign a1_7_fu_346_p3 = a[32'd11];
assign a1_fu_148_p3 = a[32'd3];
assign a1_sqr_29_fu_162_p3 = {{a1_fu_148_p3}, {a0_fu_156_p2}};
assign a1_sqr_30_fu_246_p3 = {{a1_38_fu_232_p3}, {a0_5_fu_240_p2}};
assign a1_sqr_31_fu_270_p3 = {{tmp_16_fu_260_p4}, {a0_6_fu_254_p2}};
assign a1_sqr_32_fu_360_p3 = {{a1_7_fu_346_p3}, {a0_10_fu_354_p2}};
assign a1_sqr_33_fu_444_p3 = {{a1_41_fu_430_p3}, {a0_13_fu_438_p2}};
assign a1_sqr_34_fu_468_p3 = {{a1_42_fu_458_p4}, {a0_14_fu_452_p2}};
assign a1_sqr_35_fu_496_p4 = {{{a1_43_fu_484_p2}, {a1_42_fu_458_p4}}, {a0_16_fu_490_p2}};
assign a1_sqr_36_fu_622_p3 = {{a1_17_fu_608_p3}, {a0_21_fu_616_p2}};
assign a1_sqr_37_fu_706_p3 = {{a1_46_fu_692_p3}, {a0_24_fu_700_p2}};
assign a1_sqr_38_fu_730_p3 = {{tmp_37_fu_720_p4}, {a0_25_fu_714_p2}};
assign a1_sqr_39_fu_904_p3 = {{a1_49_fu_890_p3}, {a0_32_fu_898_p2}};
assign a1_sqr_40_fu_928_p3 = {{a1_50_fu_918_p4}, {a0_33_fu_912_p2}};
assign a1_sqr_41_fu_956_p4 = {{{a1_52_fu_944_p2}, {a1_50_fu_918_p4}}, {a0_35_fu_950_p2}};
assign a1_sqr_42_fu_1026_p5 = {{{{a1_53_fu_1014_p2}, {a1_52_fu_944_p2}}, {a1_50_fu_918_p4}}, {a0_38_fu_1020_p2}};
assign a1_sqr_fu_820_p3 = {{a1_24_fu_806_p3}, {a0_29_fu_814_p2}};
assign tmp_10_fu_1102_p3 = {{xor_ln28_12_fu_1096_p2}, {a1_53_fu_1014_p2}};
integer ap_tvar_int_2;
always @ (a) begin
for (ap_tvar_int_2 = 2 - 1; ap_tvar_int_2 >= 0; ap_tvar_int_2 = ap_tvar_int_2 - 1) begin
if (ap_tvar_int_2 > 7 - 6) begin
tmp_16_fu_260_p4[ap_tvar_int_2] = 1'b0;
end else begin
tmp_16_fu_260_p4[ap_tvar_int_2] = a[7 - ap_tvar_int_2];
end
end
end
assign tmp_1_fu_936_p3 = {{a0_32_fu_898_p2}, {a0_57_fu_882_p3}};
integer ap_tvar_int_3;
always @ (a) begin
for (ap_tvar_int_3 = 2 - 1; ap_tvar_int_3 >= 0; ap_tvar_int_3 = ap_tvar_int_3 - 1) begin
if (ap_tvar_int_3 > 11 - 10) begin
tmp_21_fu_374_p4[ap_tvar_int_3] = 1'b0;
end else begin
tmp_21_fu_374_p4[ap_tvar_int_3] = a[11 - ap_tvar_int_3];
end
end
end
assign tmp_2_fu_476_p3 = {{a0_13_fu_438_p2}, {a0_49_fu_422_p3}};
integer ap_tvar_int_4;
always @ (a) begin
for (ap_tvar_int_4 = 2 - 1; ap_tvar_int_4 >= 0; ap_tvar_int_4 = ap_tvar_int_4 - 1) begin
if (ap_tvar_int_4 > 19 - 18) begin
tmp_32_fu_636_p4[ap_tvar_int_4] = 1'b0;
end else begin
tmp_32_fu_636_p4[ap_tvar_int_4] = a[19 - ap_tvar_int_4];
end
end
end
integer ap_tvar_int_5;
always @ (a) begin
for (ap_tvar_int_5 = 2 - 1; ap_tvar_int_5 >= 0; ap_tvar_int_5 = ap_tvar_int_5 - 1) begin
if (ap_tvar_int_5 > 23 - 22) begin
tmp_37_fu_720_p4[ap_tvar_int_5] = 1'b0;
end else begin
tmp_37_fu_720_p4[ap_tvar_int_5] = a[23 - ap_tvar_int_5];
end
end
end
assign tmp_3_fu_992_p3 = {{xor_ln28_7_fu_986_p2}, {a1_32_fu_978_p3}};
integer ap_tvar_int_6;
always @ (a) begin
for (ap_tvar_int_6 = 2 - 1; ap_tvar_int_6 >= 0; ap_tvar_int_6 = ap_tvar_int_6 - 1) begin
if (ap_tvar_int_6 > 27 - 26) begin
tmp_42_fu_834_p4[ap_tvar_int_6] = 1'b0;
end else begin
tmp_42_fu_834_p4[ap_tvar_int_6] = a[27 - ap_tvar_int_6];
end
end
end
assign tmp_4_fu_1006_p3 = {{xor_ln28_8_fu_1000_p2}, {a1_52_fu_944_p2}};
assign tmp_5_fu_524_p3 = {{xor_ln28_2_fu_518_p2}, {a1_14_fu_510_p3}};
assign tmp_6_fu_278_p3 = {{a0_5_fu_240_p2}, {a0_45_fu_224_p3}};
assign tmp_7_fu_1074_p3 = {{xor_ln28_10_fu_1068_p2}, {a1_35_fu_1060_p3}};
assign tmp_8_fu_538_p3 = {{xor_ln28_3_fu_532_p2}, {a1_43_fu_484_p2}};
assign tmp_9_fu_1088_p3 = {{xor_ln28_11_fu_1082_p2}, {a1_54_fu_1042_p4}};
integer ap_tvar_int_7;
always @ (a) begin
for (ap_tvar_int_7 = 2 - 1; ap_tvar_int_7 >= 0; ap_tvar_int_7 = ap_tvar_int_7 - 1) begin
if (ap_tvar_int_7 > 3 - 2) begin
tmp_fu_176_p4[ap_tvar_int_7] = 1'b0;
end else begin
tmp_fu_176_p4[ap_tvar_int_7] = a[3 - ap_tvar_int_7];
end
end
end
assign tmp_s_fu_738_p3 = {{a0_24_fu_700_p2}, {a0_53_fu_684_p3}};
assign xor_ln28_10_fu_1068_p2 = (a1_35_fu_1060_p3 ^ a0_41_fu_1052_p3);
assign xor_ln28_11_fu_1082_p2 = (tmp_7_fu_1074_p3 ^ a0_40_fu_1038_p1);
assign xor_ln28_12_fu_1096_p2 = (tmp_9_fu_1088_p3 ^ a1_51_fu_966_p3);
assign xor_ln28_13_fu_1110_p2 = (tmp_10_fu_1102_p3 ^ a0_38_fu_1020_p2);
assign xor_ln28_2_fu_518_p2 = (a1_14_fu_510_p3 ^ a0_18_fu_506_p1);
assign xor_ln28_3_fu_532_p2 = (tmp_5_fu_524_p3 ^ a1_42_fu_458_p4);
assign xor_ln28_4_fu_546_p2 = (tmp_8_fu_538_p3 ^ a0_16_fu_490_p2);
assign xor_ln28_5_fu_746_p2 = (tmp_s_fu_738_p3 ^ a0_25_fu_714_p2);
assign xor_ln28_7_fu_986_p2 = (a1_32_fu_978_p3 ^ a0_37_fu_974_p1);
assign xor_ln28_8_fu_1000_p2 = (tmp_3_fu_992_p3 ^ a1_50_fu_918_p4);
assign xor_ln28_fu_286_p2 = (tmp_6_fu_278_p3 ^ a0_6_fu_254_p2);
assign xor_ln59_10_fu_408_p2 = (a1_40_fu_400_p3 ^ a0_48_fu_392_p3);
assign xor_ln59_14_fu_552_p2 = (a1_sqr_35_fu_496_p4 ^ a0_sqr_7_fu_298_p4);
assign xor_ln59_15_fu_586_p2 = (a1_44_fu_578_p3 ^ a0_50_fu_570_p3);
assign xor_ln59_17_fu_630_p2 = (a1_sqr_36_fu_622_p3 ^ a0_sqr_17_fu_592_p3);
assign xor_ln59_18_fu_670_p2 = (a1_45_fu_662_p3 ^ a0_52_fu_654_p3);
assign xor_ln59_21_fu_752_p2 = (a1_sqr_38_fu_730_p3 ^ a0_sqr_19_fu_646_p3);
assign xor_ln59_22_fu_784_p2 = (a1_47_fu_776_p3 ^ a0_54_fu_768_p3);
assign xor_ln59_24_fu_828_p2 = (a1_sqr_fu_820_p3 ^ a0_sqr_25_fu_790_p3);
assign xor_ln59_25_fu_868_p2 = (a1_48_fu_860_p3 ^ a0_56_fu_852_p3);
assign xor_ln59_2_fu_170_p2 = (a1_sqr_29_fu_162_p3 ^ a0_sqr_1_fu_132_p3);
assign xor_ln59_30_fu_1116_p2 = (a1_sqr_42_fu_1026_p5 ^ a0_sqr_15_fu_558_p5);
assign xor_ln59_3_fu_210_p2 = (a1_37_fu_202_p3 ^ a0_44_fu_194_p3);
assign xor_ln59_6_fu_292_p2 = (a1_sqr_31_fu_270_p3 ^ a0_sqr_3_fu_186_p3);
assign xor_ln59_7_fu_324_p2 = (a1_39_fu_316_p3 ^ a0_46_fu_308_p3);
assign xor_ln59_9_fu_368_p2 = (a1_sqr_32_fu_360_p3 ^ a0_sqr_9_fu_330_p3);
assign xor_ln59_fu_126_p2 = (a1_36_fu_118_p3 ^ a0_42_fu_114_p1);
assign ap_return = {{{{{xor_ln28_13_fu_1110_p2}, {a1_53_fu_1014_p2}}, {a1_52_fu_944_p2}}, {a1_50_fu_918_p4}}, {xor_ln59_30_fu_1116_p2}};
endmodule //binary_tower_32b_sqr |
module binary_tower_32b_mul_alpha (
ap_clk,
ap_ce,
a,
ap_return,
ap_rst
);
input ap_clk;
input ap_ce;
input [31:0] a;
output [31:0] ap_return;
input ap_rst;
wire [0:0] a0_4_fu_142_p3;
wire [0:0] a1_fu_150_p3;
wire [0:0] xor_ln26_fu_158_p2;
wire [1:0] tmp_fu_164_p3;
wire [1:0] a0_3_fu_122_p4;
wire [1:0] xor_ln26_1_fu_172_p2;
wire [1:0] a1_4_fu_132_p4;
wire [3:0] tmp_1_fu_178_p3;
wire [3:0] a0_2_fu_102_p4;
wire [3:0] xor_ln26_2_fu_186_p2;
wire [3:0] a1_3_fu_112_p4;
wire [7:0] tmp_2_fu_192_p3;
wire [7:0] a0_1_fu_82_p4;
wire [7:0] xor_ln26_3_fu_200_p2;
wire [7:0] a1_2_fu_92_p4;
wire [15:0] tmp_3_fu_206_p3;
wire [15:0] a0_fu_68_p1;
wire [15:0] xor_ln26_4_fu_214_p2;
wire [15:0] a1_1_fu_72_p4;
assign a0_1_fu_82_p4 = {{a[23:16]}};
assign a0_2_fu_102_p4 = {{a[27:24]}};
assign a0_3_fu_122_p4 = {{a[29:28]}};
assign a0_4_fu_142_p3 = a[32'd30];
assign a0_fu_68_p1 = a[15:0];
assign a1_1_fu_72_p4 = {{a[31:16]}};
assign a1_2_fu_92_p4 = {{a[31:24]}};
assign a1_3_fu_112_p4 = {{a[31:28]}};
assign a1_4_fu_132_p4 = {{a[31:30]}};
assign a1_fu_150_p3 = a[32'd31];
assign tmp_1_fu_178_p3 = {{xor_ln26_1_fu_172_p2}, {a1_4_fu_132_p4}};
assign tmp_2_fu_192_p3 = {{xor_ln26_2_fu_186_p2}, {a1_3_fu_112_p4}};
assign tmp_3_fu_206_p3 = {{xor_ln26_3_fu_200_p2}, {a1_2_fu_92_p4}};
assign tmp_fu_164_p3 = {{xor_ln26_fu_158_p2}, {a1_fu_150_p3}};
assign xor_ln26_1_fu_172_p2 = (tmp_fu_164_p3 ^ a0_3_fu_122_p4);
assign xor_ln26_2_fu_186_p2 = (tmp_1_fu_178_p3 ^ a0_2_fu_102_p4);
assign xor_ln26_3_fu_200_p2 = (tmp_2_fu_192_p3 ^ a0_1_fu_82_p4);
assign xor_ln26_4_fu_214_p2 = (tmp_3_fu_206_p3 ^ a0_fu_68_p1);
assign xor_ln26_fu_158_p2 = (a1_fu_150_p3 ^ a0_4_fu_142_p3);
assign ap_return = {{xor_ln26_4_fu_214_p2}, {a1_1_fu_72_p4}};
endmodule //binary_tower_32b_mul_alpha |
module heart_beat (
input CLK ,
input [31:0] CLK_FREQ ,
output reg CK_1HZ
) ;
//---50MHZ CLOCK1 TEST---
reg [31:0] CLK_DELAY ;
//--
always @(posedge CLK )
begin
if (CLK_DELAY> CLK_FREQ/2)
begin
CLK_DELAY<=0;
CK_1HZ <=~CK_1HZ ;
end
else
CLK_DELAY <=CLK_DELAY+1;
end
endmodule |
module DE10_NANO_E300(
///////// ADC /////////
output ADC_CONVST ,
output ADC_SCK ,
output ADC_SDI ,
input ADC_SDO ,
///////// ARDUINO /////////
inout [15:0] ARDUINO_IO ,
inout ARDUINO_RESET_N ,
///////// FPGA /////////
input FPGA_CLK1_50 ,
input FPGA_CLK2_50 ,
input FPGA_CLK3_50 ,
///////// GPIO /////////
//inout [35:0] GPIO_0 ,
inout [35:0] GPIO_1 ,
///////// HDMI /////////
inout HDMI_I2C_SCL ,
inout HDMI_I2C_SDA ,
inout HDMI_I2S ,
inout HDMI_LRCLK ,
inout HDMI_MCLK ,
inout HDMI_SCLK ,
output HDMI_TX_CLK ,
output [23:0] HDMI_TX_D ,
output HDMI_TX_DE ,
output HDMI_TX_HS ,
input HDMI_TX_INT ,
output HDMI_TX_VS ,
`ifdef ENABLE_HPS
///////// HPS /////////
inout HPS_CONV_USB_N ,
output [14:0] HPS_DDR3_ADDR ,
output [2:0] HPS_DDR3_BA ,
output HPS_DDR3_CAS_N ,
output HPS_DDR3_CKE ,
output HPS_DDR3_CK_N ,
output HPS_DDR3_CK_P ,
output HPS_DDR3_CS_N ,
output [3:0] HPS_DDR3_DM ,
inout [31:0] HPS_DDR3_DQ ,
inout [3:0] HPS_DDR3_DQS_N ,
inout [3:0] HPS_DDR3_DQS_P ,
output HPS_DDR3_ODT ,
output HPS_DDR3_RAS_N ,
output HPS_DDR3_RESET_N ,
input HPS_DDR3_RZQ ,
output HPS_DDR3_WE_N ,
output HPS_ENET_GTX_CLK ,
inout HPS_ENET_INT_N ,
output HPS_ENET_MDC ,
inout HPS_ENET_MDIO ,
input HPS_ENET_RX_CLK ,
input [3:0] HPS_ENET_RX_DATA ,
input HPS_ENET_RX_DV ,
output [3:0] HPS_ENET_TX_DATA ,
output HPS_ENET_TX_EN ,
inout HPS_GSENSOR_INT ,
inout HPS_I2C0_SCLK ,
inout HPS_I2C0_SDAT ,
inout HPS_I2C1_SCLK ,
inout HPS_I2C1_SDAT ,
inout HPS_KEY ,
inout HPS_LED ,
inout HPS_LTC_GPIO ,
output HPS_SD_CLK ,
inout HPS_SD_CMD ,
inout [3:0] HPS_SD_DATA ,
output HPS_SPIM_CLK ,
input HPS_SPIM_MISO ,
output HPS_SPIM_MOSI ,
inout HPS_SPIM_SS ,
input HPS_UART_RX ,
output HPS_UART_TX ,
input HPS_USB_CLKOUT ,
inout [7:0] HPS_USB_DATA ,
input HPS_USB_DIR ,
input HPS_USB_NXT ,
output HPS_USB_STP ,
`endif /*ENABLE_HPS*/
///////// KEY /////////
input [1:0] KEY ,
///////// LED /////////
output [7:0] LED ,
///////// SW /////////
input [3:0] SW ,
///////// QSPI /////////
output QSPI_FLASH_SCLK ,
inout [3:0] QSPI_FLASH_DATA ,
output QSPI_FLASH_CE_n ,
///////// RISCV /////////
input RISCV_JTAG_TCK , //GPIO_1[2]
input RISCV_JTAG_TMS , //GPIO_1[3]
output RISCV_JTAG_TDO , //GPIO_1[4]
input RISCV_JTAG_TDI //GPIO_1[5]
);
//for jtag
wire jtag_tck ;
wire jtag_tms ;
wire jtag_tdi ;
wire jtag_tdo ;
wire SRST_n ;
//for pll_sys
wire clk_8388 ;
wire clk_32M ;
wire ip_mmcm_8388m_locked ;
wire ip_mmcm_32m_locked ;
wire ip_mmcm_locked ;
//for clkdivider
wire slowclk;
//for reset
reg reset_periph_t ;
wire ip_reset_sys_peripheral_reset ;
wire fpga_power_on_power_on_reset ;
wire ip_reset_sys_mb_debug_sys_rst ;
pll_sys ip_mmcm(
/*input wire */ .inclk0 ( FPGA_CLK1_50 ),
/*input wire */ .areset ( 1'b0 ), // ~CPU_RESET_n ) ,
/*output wire */ .c0 ( clk_8388 ),
/*output wire */ .locked ( ip_mmcm_8388m_locked )
);
pll_sys_32m ip_mmcm_32m(
/*input wire */ .inclk0 ( FPGA_CLK1_50 ),
/*input wire */ .areset ( 1'b0 ), // ~CPU_RESET_n ) ,
/*output wire */ .c0 ( clk_32M ),
/*output wire */ .locked ( ip_mmcm_32m_locked )
);
assign ip_mmcm_locked = ip_mmcm_8388m_locked && ip_mmcm_32m_locked;
clkdivider slowclkgen(
/*input wire */ .clk ( clk_8388 ), // use this clock divide to 32.768KHz
/*input wire */ .reset ( ~ip_mmcm_locked ),
/*output wire */ .clk_out ( slowclk )
);
always @(posedge clk_8388)
begin
if( KEY[0] == 1'b0 || ip_mmcm_locked == 1'b0 || /*SRST_n == 1'b0 || */ip_reset_sys_mb_debug_sys_rst == 1'b1)
begin
reset_periph_t <= 1'b1;
end
else
begin
reset_periph_t <= 1'b0;
end
end
assign ip_reset_sys_peripheral_reset = reset_periph_t;
PowerOnResetFPGAOnly fpga_power_on (
/*input wire */ .clock ( clk_32M ),
/*output wire */ .power_on_reset ( fpga_power_on_power_on_reset )
);
Freedom_E300_Wrapper E300_SoC_Wrapped(
/*input wire */ .clock ( clk_32M ),
/*input wire */ .aon_lfextclk ( slowclk ),
/*input wire */ .aon_erst_n ( ~ip_reset_sys_peripheral_reset ),
/*input wire */ .jtag_reset ( fpga_power_on_power_on_reset ),
/*output wire */ .io_ndreset ( ip_reset_sys_mb_debug_sys_rst ),
/*input wire */ .jtag_tck ( RISCV_JTAG_TCK ),
/*input wire */ .jtag_tms ( RISCV_JTAG_TMS ),
/*input wire */ .jtag_tdi ( RISCV_JTAG_TDI ),
/*output wire */ .jtag_tdo ( RISCV_JTAG_TDO ),
/*output wire */ .qspi_sck ( QSPI_FLASH_SCLK ),
/*output wire */ .qspi_cs_0 ( QSPI_FLASH_CE_n ),
/*inout wire [3:0] */ .qspi_dq ( QSPI_FLASH_DATA ),
/*input wire [31:0] */ .e300_gpio_i_ival ( e300_gpio_i_ival ),
/*output wire [31:0] */ .e300_gpio_o_ie ( e300_gpio_o_ie ),
/*output wire [31:0] */ .e300_gpio_o_oval ( e300_gpio_o_oval ),
/*output wire [31:0] */ .e300_gpio_o_oe ( e300_gpio_o_oe )
);
////////////////////////////////
// GPIO 0-31 map
/////////////////////
//
// GPIO, IOF0 , IOF1
// 0 , ,pwn0_0
// 1 , ,pwn0_1
// 2 ,spi0_cs0,pwn0_2
// 3 ,spi0_dq0,pwn0_3
// 4 ,spi0_dq1,
// 5 ,spi0_sck,
// 6 ,spi0_dq2,
// 7 ,spi0_dq3,
// 8 ,spi0_cs1,
// 9 ,spi0_cs2,
// 10 ,spi0_cs3,pwn2_0
// 11 , ,pwn2_1
// 12 ,i2c0_sda,pwn2_2
// 13 ,i2c0_scl,pwn2_3
// 14 , ,
// 15 , ,
// 16 ,uart0_rx,
// 17 ,uart0_tx,
// 18 , ,
// 19 , ,pwn1_0
// 20 , ,pwn1_1
// 21 , ,pwn1_2
// 22 , ,pwn1_3
// 23 , ,
// 24 ,uart1_rx,
// 25 ,uart1_tx,
// 26 ,spi1_cs0,
// 27 ,spi1_dq0,
// 28 ,spi1_dq1,
// 29 ,spi1_sck,
// 30 ,spi1_dq2,
// 31 ,spi1_dq3,
///// to Use GPIO, iof_en = 0
//// to Use IOF0, iof_en = 1, iof_sel = 0www
//// to Use IOF1, iof_en = 1, iof_sel = 1
wire [31:0] e300_gpio_i_ival ;
wire [31:0] e300_gpio_o_ie ;
wire [31:0] e300_gpio_o_oval ;
wire [31:0] e300_gpio_o_oe ;
//uart, GPIO_1[0]: UART_TX (fpga to PC), GPIO_1[1]: UART_RX (pc to FPGA),
assign GPIO_1[0] = e300_gpio_o_oe[17] ? e300_gpio_o_oval[17] :1'bz;
assign e300_gpio_i_ival[16] = e300_gpio_o_ie[16] & GPIO_1[1] ;
//LEDs
assign LED[0] = e300_gpio_o_oe[0] ? e300_gpio_o_oval[0] : 1'bz;
assign LED[1] = e300_gpio_o_oe[1] ? e300_gpio_o_oval[1] : 1'bz;
assign LED[2] = e300_gpio_o_oe[2] ? e300_gpio_o_oval[2] : 1'bz;
assign LED[3] = e300_gpio_o_oe[3] ? e300_gpio_o_oval[3] : 1'bz;
assign LED[7] = 1'b1;
//SWs
assign e300_gpio_i_ival[4] = e300_gpio_o_ie[4] & SW[0];
assign e300_gpio_i_ival[5] = e300_gpio_o_ie[5] & SW[1];
assign e300_gpio_i_ival[6] = e300_gpio_o_ie[6] & SW[2];
assign e300_gpio_i_ival[7] = e300_gpio_o_ie[7] & SW[3];
//KEYs
assign e300_gpio_i_ival[8] = e300_gpio_o_ie[8] & KEY[0];
assign e300_gpio_i_ival[9] = e300_gpio_o_ie[9] & KEY[1];
endmodule |
module DE10_NANO_RISCV(
///////// ADC /////////
output ADC_CONVST ,
output ADC_SCK ,
output ADC_SDI ,
input ADC_SDO ,
///////// ARDUINO /////////
inout [15:0] ARDUINO_IO ,
inout ARDUINO_RESET_N ,
///////// FPGA /////////
input FPGA_CLK1_50 ,
input FPGA_CLK2_50 ,
input FPGA_CLK3_50 ,
///////// GPIO /////////
inout [35:0] GPIO_0 ,
//inout [35:12] GPIO_1 ,
///////// HDMI /////////
inout HDMI_I2C_SCL ,
inout HDMI_I2C_SDA ,
inout HDMI_I2S ,
inout HDMI_LRCLK ,
inout HDMI_MCLK ,
inout HDMI_SCLK ,
output HDMI_TX_CLK ,
output [23:0] HDMI_TX_D ,
output HDMI_TX_DE ,
output HDMI_TX_HS ,
input HDMI_TX_INT ,
output HDMI_TX_VS ,
`ifdef ENABLE_HPS
///////// HPS /////////
inout HPS_CONV_USB_N ,
output [14:0] HPS_DDR3_ADDR ,
output [2:0] HPS_DDR3_BA ,
output HPS_DDR3_CAS_N ,
output HPS_DDR3_CKE ,
output HPS_DDR3_CK_N ,
output HPS_DDR3_CK_P ,
output HPS_DDR3_CS_N ,
output [3:0] HPS_DDR3_DM ,
inout [31:0] HPS_DDR3_DQ ,
inout [3:0] HPS_DDR3_DQS_N ,
inout [3:0] HPS_DDR3_DQS_P ,
output HPS_DDR3_ODT ,
output HPS_DDR3_RAS_N ,
output HPS_DDR3_RESET_N ,
input HPS_DDR3_RZQ ,
output HPS_DDR3_WE_N ,
output HPS_ENET_GTX_CLK ,
inout HPS_ENET_INT_N ,
output HPS_ENET_MDC ,
inout HPS_ENET_MDIO ,
input HPS_ENET_RX_CLK ,
input [3:0] HPS_ENET_RX_DATA ,
input HPS_ENET_RX_DV ,
output [3:0] HPS_ENET_TX_DATA ,
output HPS_ENET_TX_EN ,
inout HPS_GSENSOR_INT ,
inout HPS_I2C0_SCLK ,
inout HPS_I2C0_SDAT ,
inout HPS_I2C1_SCLK ,
inout HPS_I2C1_SDAT ,
inout HPS_KEY ,
inout HPS_LED ,
inout HPS_LTC_GPIO ,
output HPS_SD_CLK ,
inout HPS_SD_CMD ,
inout [3:0] HPS_SD_DATA ,
output HPS_SPIM_CLK ,
input HPS_SPIM_MISO ,
output HPS_SPIM_MOSI ,
inout HPS_SPIM_SS ,
input HPS_UART_RX ,
output HPS_UART_TX ,
input HPS_USB_CLKOUT ,
inout [7:0] HPS_USB_DATA ,
input HPS_USB_DIR ,
input HPS_USB_NXT ,
output HPS_USB_STP ,
`endif /*ENABLE_HPS*/
input RISCV_UART_RX , // GPIO_1[0]
output RISCV_UART_TX , // GPIO_1[1]
input RISCV_JTAG_TCK , // GPIO_1[2]
input RISCV_JTAG_TMS , // GPIO_1[3]
output RISCV_JTAG_TDO , // GPIO_1[4]
input RISCV_JTAG_TDI , // GPIO_1[5]
output RISCV_QSPI_CS ,
output RISCV_QSPI_SCK ,
inout [3:0] RISCV_QSPI_DQ ,
///////// KEY /////////
input [1:0] KEY ,
///////// LED /////////
output [7:0] LED ,
///////// SW /////////
input [3:0] SW
);
//=======================================================
// REG/WIRE declarations
//=======================================================
wire mmcm_locked ;
wire reset_periph ;
// All wires connected to the chip top
wire dut_clock ;
wire dut_reset ;
wire e203_jtag_TCK_i_ival ;
wire e203_jtag_TMS_i_ival ;
wire e203_jtag_TMS_o_oval ;
wire e203_jtag_TMS_o_oe ;
wire e203_jtag_TMS_o_ie ;
wire e203_jtag_TMS_o_pue ;
wire e203_jtag_TMS_o_ds ;
wire e203_jtag_TDI_i_ival ;
wire e203_jtag_TDO_o_oval ;
wire e203_jtag_TDO_o_oe ;
wire [31:0] e203_i_ival_gpio ;
wire [31:0] e203_o_oval_gpio ;
wire [31:0] e203_o_oe_gpio ;
wire [31:0] e203_o_ie_gpio ;
wire [31:0] e203_o_pue_gpio ;
wire [31:0] e203_o_ds_gpio ;
wire e203_qspi_sck_o_oval ;
wire e203_qspi_cs_0_o_oval ;
wire [ 3:0] e203_qspi_i_ival_dq ;
wire [ 3:0] e203_qspi_o_oval_dq ;
wire [ 3:0] e203_qspi_o_oe_dq ;
wire [ 3:0] e203_qspi_o_ie_dq ;
wire [ 3:0] e203_qspi_o_pue_dq ;
wire [ 3:0] e203_qspi_o_ds_dq ;
wire e203_aon_erst_n_i_ival ;
wire e203_aon_pmu_dwakeup_n_i_ival ;
wire e203_aon_pmu_vddpaden_o_oval ;
wire e203_aon_pmu_padrst_o_oval ;
wire e203_bootrom_n_i_ival ;
wire e203_dbgmode0_n_i_ival ;
wire e203_dbgmode1_n_i_ival ;
wire e203_dbgmode2_n_i_ival ;
//=================================================
// Clock & Reset
wire clk_8388 ;
wire clk_16M ;
wire slowclk ;
riscv_pll riscv_pll_inst (
.refclk ( FPGA_CLK1_50 ) , // refclk.clk
.rst ( 1'b0 ) , // reset.reset
.outclk_0 ( clk_16M ) , //16MHz
.outclk_1 ( clk_8388 ) , // 8.388 MHz = 32.768 kHz * 256
.locked ( mmcm_locked ) // locked.export
);
clkdivider slowclkgen (
.clk ( clk_8388 ) ,// We use this clock divide to 32.768KHz
.reset ( ~mmcm_locked ) ,
.clk_out ( slowclk )
);
reset_sys ip_reset_sys (
.slowest_sync_clk ( slowclk ) ,
//.ext_reset_in ( KEY[0] & SRST_n ) , // Active-low
.ext_reset_in ( KEY[0] ) , // Active-low
.aux_reset_in ( 1'b1 ) ,
.mb_debug_sys_rst ( 1'b0 ) ,
.dcm_locked ( mmcm_locked ) ,
.mb_reset ( ) ,
.bus_struct_reset ( ) ,
.peripheral_reset ( reset_periph ) ,
.interconnect_aresetn ( ) ,
.peripheral_aresetn ( )
);
//=================================================
// SPI Interface
wire [3:0] qspi_ui_dq_o ;
wire [3:0] qspi_ui_dq_oe;
wire [3:0] qspi_ui_dq_i ;
assign RISCV_QSPI_DQ[0] = qspi_ui_dq_oe ? qspi_ui_dq_o[0] : 1'bz;
assign RISCV_QSPI_DQ[1] = qspi_ui_dq_oe ? qspi_ui_dq_o[1] : 1'bz;
assign RISCV_QSPI_DQ[2] = qspi_ui_dq_oe ? qspi_ui_dq_o[2] : 1'bz;
assign RISCV_QSPI_DQ[3] = qspi_ui_dq_oe ? qspi_ui_dq_o[3] : 1'bz;
assign qspi_ui_dq_i[0] = RISCV_QSPI_DQ[0];
assign qspi_ui_dq_i[1] = RISCV_QSPI_DQ[1];
assign qspi_ui_dq_i[2] = RISCV_QSPI_DQ[2];
assign qspi_ui_dq_i[3] = RISCV_QSPI_DQ[3];
assign qspi_ui_dq_o = e203_qspi_o_oval_dq;
assign qspi_ui_dq_oe = e203_qspi_o_oe_dq;
assign e203_qspi_i_ival_dq = qspi_ui_dq_i;
assign RISCV_QSPI_SCK = e203_qspi_sck_o_oval;
assign RISCV_QSPI_CS = e203_qspi_cs_0_o_oval;
//=================================================
// IOBUF instantiation for GPIOs
assign GPIO_0[00] = e203_o_oe_gpio[00] ? e203_o_oval_gpio[00] : 1'bz;
assign GPIO_0[01] = e203_o_oe_gpio[01] ? e203_o_oval_gpio[01] : 1'bz;
assign GPIO_0[02] = e203_o_oe_gpio[02] ? e203_o_oval_gpio[02] : 1'bz;
assign GPIO_0[03] = e203_o_oe_gpio[03] ? e203_o_oval_gpio[03] : 1'bz;
assign GPIO_0[04] = e203_o_oe_gpio[04] ? e203_o_oval_gpio[04] : 1'bz;
assign GPIO_0[05] = e203_o_oe_gpio[05] ? e203_o_oval_gpio[05] : 1'bz;
assign GPIO_0[06] = e203_o_oe_gpio[06] ? e203_o_oval_gpio[06] : 1'bz;
assign GPIO_0[07] = e203_o_oe_gpio[07] ? e203_o_oval_gpio[07] : 1'bz;
assign GPIO_0[08] = e203_o_oe_gpio[08] ? e203_o_oval_gpio[08] : 1'bz;
assign GPIO_0[09] = e203_o_oe_gpio[09] ? e203_o_oval_gpio[09] : 1'bz;
assign GPIO_0[10] = e203_o_oe_gpio[10] ? e203_o_oval_gpio[10] : 1'bz;
assign GPIO_0[11] = e203_o_oe_gpio[11] ? e203_o_oval_gpio[11] : 1'bz;
assign GPIO_0[12] = e203_o_oe_gpio[12] ? e203_o_oval_gpio[12] : 1'bz;
assign GPIO_0[13] = e203_o_oe_gpio[13] ? e203_o_oval_gpio[13] : 1'bz;
assign GPIO_0[14] = e203_o_oe_gpio[14] ? e203_o_oval_gpio[14] : 1'bz;
assign GPIO_0[15] = e203_o_oe_gpio[15] ? e203_o_oval_gpio[15] : 1'bz;
assign GPIO_0[16] = e203_o_oe_gpio[16] ? e203_o_oval_gpio[16] : 1'bz;
assign GPIO_0[17] = e203_o_oe_gpio[17] ? e203_o_oval_gpio[17] : 1'bz;
assign GPIO_0[18] = e203_o_oe_gpio[18] ? e203_o_oval_gpio[18] : 1'bz;
assign GPIO_0[19] = e203_o_oe_gpio[19] ? e203_o_oval_gpio[19] : 1'bz;
assign GPIO_0[20] = e203_o_oe_gpio[20] ? e203_o_oval_gpio[20] : 1'bz;
assign GPIO_0[21] = e203_o_oe_gpio[21] ? e203_o_oval_gpio[21] : 1'bz;
assign GPIO_0[22] = e203_o_oe_gpio[22] ? e203_o_oval_gpio[22] : 1'bz;
assign GPIO_0[23] = e203_o_oe_gpio[23] ? e203_o_oval_gpio[23] : 1'bz;
assign GPIO_0[24] = e203_o_oe_gpio[24] ? e203_o_oval_gpio[24] : 1'bz;
assign GPIO_0[25] = e203_o_oe_gpio[25] ? e203_o_oval_gpio[25] : 1'bz;
assign GPIO_0[26] = e203_o_oe_gpio[26] ? e203_o_oval_gpio[26] : 1'bz;
assign GPIO_0[27] = e203_o_oe_gpio[27] ? e203_o_oval_gpio[27] : 1'bz;
assign GPIO_0[28] = e203_o_oe_gpio[28] ? e203_o_oval_gpio[28] : 1'bz;
assign GPIO_0[29] = e203_o_oe_gpio[29] ? e203_o_oval_gpio[29] : 1'bz;
assign GPIO_0[30] = e203_o_oe_gpio[30] ? e203_o_oval_gpio[30] : 1'bz;
assign GPIO_0[31] = e203_o_oe_gpio[31] ? e203_o_oval_gpio[31] : 1'bz;
assign e203_i_ival_gpio[00] = GPIO_0[00] & e203_o_ie_gpio[00];
assign e203_i_ival_gpio[01] = GPIO_0[01] & e203_o_ie_gpio[01];
assign e203_i_ival_gpio[02] = GPIO_0[02] & e203_o_ie_gpio[02];
assign e203_i_ival_gpio[03] = GPIO_0[03] & e203_o_ie_gpio[03];
assign e203_i_ival_gpio[04] = GPIO_0[04] & e203_o_ie_gpio[04];
assign e203_i_ival_gpio[05] = GPIO_0[05] & e203_o_ie_gpio[05];
assign e203_i_ival_gpio[06] = GPIO_0[06] & e203_o_ie_gpio[06];
assign e203_i_ival_gpio[07] = GPIO_0[07] & e203_o_ie_gpio[07];
assign e203_i_ival_gpio[08] = GPIO_0[08] & e203_o_ie_gpio[08];
assign e203_i_ival_gpio[09] = GPIO_0[09] & e203_o_ie_gpio[09];
assign e203_i_ival_gpio[10] = GPIO_0[10] & e203_o_ie_gpio[10];
assign e203_i_ival_gpio[11] = GPIO_0[11] & e203_o_ie_gpio[11];
assign e203_i_ival_gpio[12] = GPIO_0[12] & e203_o_ie_gpio[12];
assign e203_i_ival_gpio[13] = GPIO_0[13] & e203_o_ie_gpio[13];
assign e203_i_ival_gpio[14] = GPIO_0[14] & e203_o_ie_gpio[14];
assign e203_i_ival_gpio[15] = GPIO_0[15] & e203_o_ie_gpio[15];
//assign e203_i_ival_gpio[16] = GPIO_0[16] & e203_o_ie_gpio[16];
assign e203_i_ival_gpio[17] = GPIO_0[17] & e203_o_ie_gpio[17];
assign e203_i_ival_gpio[18] = GPIO_0[18] & e203_o_ie_gpio[18];
assign e203_i_ival_gpio[19] = GPIO_0[19] & e203_o_ie_gpio[19];
assign e203_i_ival_gpio[20] = GPIO_0[20] & e203_o_ie_gpio[20];
assign e203_i_ival_gpio[21] = GPIO_0[21] & e203_o_ie_gpio[21];
assign e203_i_ival_gpio[22] = GPIO_0[22] & e203_o_ie_gpio[22];
assign e203_i_ival_gpio[23] = GPIO_0[23] & e203_o_ie_gpio[23];
assign e203_i_ival_gpio[24] = GPIO_0[24] & e203_o_ie_gpio[24];
assign e203_i_ival_gpio[25] = GPIO_0[25] & e203_o_ie_gpio[25];
assign e203_i_ival_gpio[26] = GPIO_0[26] & e203_o_ie_gpio[26];
assign e203_i_ival_gpio[27] = GPIO_0[27] & e203_o_ie_gpio[27];
assign e203_i_ival_gpio[28] = GPIO_0[28] & e203_o_ie_gpio[28];
assign e203_i_ival_gpio[29] = GPIO_0[29] & e203_o_ie_gpio[29];
assign e203_i_ival_gpio[30] = GPIO_0[30] & e203_o_ie_gpio[30];
assign e203_i_ival_gpio[31] = GPIO_0[31] & e203_o_ie_gpio[31];
// This GPIO input is shared between FTDI TX pin and Arduino shield pin using SW[3]
// see below for details
//assign e203_i_ival_gpio[16] = sw_3 ? (iobuf_gpio[16] & e203_o_ie_gpio[16]) : (uart_txd_in & e203_o_ie_gpio[16]);
//Bob: I hacked this, just let it always come from FDTI, and free the sw_3
assign e203_i_ival_gpio[16] = (RISCV_UART_RX & e203_o_ie_gpio[16]);
assign RISCV_UART_TX = (e203_o_oval_gpio[17] & e203_o_oe_gpio[17]);
//=================================================
// JTAG IOBUFs
assign e203_jtag_TCK_i_ival = RISCV_JTAG_TCK;
assign e203_jtag_TMS_i_ival = RISCV_JTAG_TMS;
assign e203_jtag_TDI_i_ival = RISCV_JTAG_TDI;
assign RISCV_JTAG_TDO = e203_jtag_TDO_o_oe ? e203_jtag_TDO_o_oval : 1'bz;
//=================================================
assign LED[0] = e203_o_oval_gpio[0] & e203_o_oe_gpio[0];
assign LED[1] = e203_o_oval_gpio[1] & e203_o_oe_gpio[1];
assign LED[2] = e203_o_oval_gpio[2] & e203_o_oe_gpio[2];
assign LED[3] = e203_o_oval_gpio[3] & e203_o_oe_gpio[3];
assign LED[7] = 1'b1;
// model select
//all set to 1
assign e203_bootrom_n_i_ival = 1'b0;
assign e203_dbgmode0_n_i_ival = 1'b1;
assign e203_dbgmode1_n_i_ival = 1'b1;
assign e203_dbgmode2_n_i_ival = 1'b1;
// Assign reasonable values to otherwise unconnected inputs to chip top
assign e203_aon_pmu_dwakeup_n_i_ival = ~KEY[1] ; //?? 1'b0?
assign e203_aon_erst_n_i_ival = ~reset_periph ;
assign e203_aon_pmu_vddpaden_i_ival = 1'b1 ;
e203_soc_top dut
(
.hfextclk ( clk_16M ) ,
.hfxoscen ( ) ,
.lfextclk ( slowclk ) ,
.lfxoscen ( ) ,
// Note: this is the real SoC top AON domain slow clock
.io_pads_jtag_TCK_i_ival ( e203_jtag_TCK_i_ival ) ,
.io_pads_jtag_TMS_i_ival ( e203_jtag_TMS_i_ival ) ,
.io_pads_jtag_TDI_i_ival ( e203_jtag_TDI_i_ival ) ,
.io_pads_jtag_TDO_o_oval ( e203_jtag_TDO_o_oval ) ,
.io_pads_jtag_TDO_o_oe ( e203_jtag_TDO_o_oe ) ,
.io_pads_gpio_0_i_ival ( e203_i_ival_gpio [ 0] ) ,
.io_pads_gpio_0_o_oval ( e203_o_oval_gpio [ 0] ) ,
.io_pads_gpio_0_o_oe ( e203_o_oe_gpio [ 0] ) ,
.io_pads_gpio_0_o_ie ( e203_o_ie_gpio [ 0] ) ,
.io_pads_gpio_0_o_pue ( e203_o_pue_gpio [ 0] ) ,
.io_pads_gpio_0_o_ds ( e203_o_ds_gpio [ 0] ) ,
.io_pads_gpio_1_i_ival ( e203_i_ival_gpio [ 1] ) ,
.io_pads_gpio_1_o_oval ( e203_o_oval_gpio [ 1] ) ,
.io_pads_gpio_1_o_oe ( e203_o_oe_gpio [ 1] ) ,
.io_pads_gpio_1_o_ie ( e203_o_ie_gpio [ 1] ) ,
.io_pads_gpio_1_o_pue ( e203_o_pue_gpio [ 1] ) ,
.io_pads_gpio_1_o_ds ( e203_o_ds_gpio [ 1] ) ,
.io_pads_gpio_2_i_ival ( e203_i_ival_gpio [ 2] ) ,
.io_pads_gpio_2_o_oval ( e203_o_oval_gpio [ 2] ) ,
.io_pads_gpio_2_o_oe ( e203_o_oe_gpio [ 2] ) ,
.io_pads_gpio_2_o_ie ( e203_o_ie_gpio [ 2] ) ,
.io_pads_gpio_2_o_pue ( e203_o_pue_gpio [ 2] ) ,
.io_pads_gpio_2_o_ds ( e203_o_ds_gpio [ 2] ) ,
.io_pads_gpio_3_i_ival ( e203_i_ival_gpio [ 3] ) ,
.io_pads_gpio_3_o_oval ( e203_o_oval_gpio [ 3] ) ,
.io_pads_gpio_3_o_oe ( e203_o_oe_gpio [ 3] ) ,
.io_pads_gpio_3_o_ie ( e203_o_ie_gpio [ 3] ) ,
.io_pads_gpio_3_o_pue ( e203_o_pue_gpio [ 3] ) ,
.io_pads_gpio_3_o_ds ( e203_o_ds_gpio [ 3] ) ,
.io_pads_gpio_4_i_ival ( e203_i_ival_gpio [ 4] ) ,
.io_pads_gpio_4_o_oval ( e203_o_oval_gpio [ 4] ) ,
.io_pads_gpio_4_o_oe ( e203_o_oe_gpio [ 4] ) ,
.io_pads_gpio_4_o_ie ( e203_o_ie_gpio [ 4] ) ,
.io_pads_gpio_4_o_pue ( e203_o_pue_gpio [ 4] ) ,
.io_pads_gpio_4_o_ds ( e203_o_ds_gpio [ 4] ) ,
.io_pads_gpio_5_i_ival ( e203_i_ival_gpio [ 5] ) ,
.io_pads_gpio_5_o_oval ( e203_o_oval_gpio [ 5] ) ,
.io_pads_gpio_5_o_oe ( e203_o_oe_gpio [ 5] ) ,
.io_pads_gpio_5_o_ie ( e203_o_ie_gpio [ 5] ) ,
.io_pads_gpio_5_o_pue ( e203_o_pue_gpio [ 5] ) ,
.io_pads_gpio_5_o_ds ( e203_o_ds_gpio [ 5] ) ,
.io_pads_gpio_6_i_ival ( e203_i_ival_gpio [ 6] ) ,
.io_pads_gpio_6_o_oval ( e203_o_oval_gpio [ 6] ) ,
.io_pads_gpio_6_o_oe ( e203_o_oe_gpio [ 6] ) ,
.io_pads_gpio_6_o_ie ( e203_o_ie_gpio [ 6] ) ,
.io_pads_gpio_6_o_pue ( e203_o_pue_gpio [ 6] ) ,
.io_pads_gpio_6_o_ds ( e203_o_ds_gpio [ 6] ) ,
.io_pads_gpio_7_i_ival ( e203_i_ival_gpio [ 7] ) ,
.io_pads_gpio_7_o_oval ( e203_o_oval_gpio [ 7] ) ,
.io_pads_gpio_7_o_oe ( e203_o_oe_gpio [ 7] ) ,
.io_pads_gpio_7_o_ie ( e203_o_ie_gpio [ 7] ) ,
.io_pads_gpio_7_o_pue ( e203_o_pue_gpio [ 7] ) ,
.io_pads_gpio_7_o_ds ( e203_o_ds_gpio [ 7] ) ,
.io_pads_gpio_8_i_ival ( e203_i_ival_gpio [ 8] ) ,
.io_pads_gpio_8_o_oval ( e203_o_oval_gpio [ 8] ) ,
.io_pads_gpio_8_o_oe ( e203_o_oe_gpio [ 8] ) ,
.io_pads_gpio_8_o_ie ( e203_o_ie_gpio [ 8] ) ,
.io_pads_gpio_8_o_pue ( e203_o_pue_gpio [ 8] ) ,
.io_pads_gpio_8_o_ds ( e203_o_ds_gpio [ 8] ) ,
.io_pads_gpio_9_i_ival ( e203_i_ival_gpio [ 9] ) ,
.io_pads_gpio_9_o_oval ( e203_o_oval_gpio [ 9] ) ,
.io_pads_gpio_9_o_oe ( e203_o_oe_gpio [ 9] ) ,
.io_pads_gpio_9_o_ie ( e203_o_ie_gpio [ 9] ) ,
.io_pads_gpio_9_o_pue ( e203_o_pue_gpio [ 9] ) ,
.io_pads_gpio_9_o_ds ( e203_o_ds_gpio [ 9] ) ,
.io_pads_gpio_10_i_ival ( e203_i_ival_gpio [10] ) ,
.io_pads_gpio_10_o_oval ( e203_o_oval_gpio [10] ) ,
.io_pads_gpio_10_o_oe ( e203_o_oe_gpio [10] ) ,
.io_pads_gpio_10_o_ie ( e203_o_ie_gpio [10] ) ,
.io_pads_gpio_10_o_pue ( e203_o_pue_gpio [10] ) ,
.io_pads_gpio_10_o_ds ( e203_o_ds_gpio [10] ) ,
.io_pads_gpio_11_i_ival ( e203_i_ival_gpio [11] ) ,
.io_pads_gpio_11_o_oval ( e203_o_oval_gpio [11] ) ,
.io_pads_gpio_11_o_oe ( e203_o_oe_gpio [11] ) ,
.io_pads_gpio_11_o_ie ( e203_o_ie_gpio [11] ) ,
.io_pads_gpio_11_o_pue ( e203_o_pue_gpio [11] ) ,
.io_pads_gpio_11_o_ds ( e203_o_ds_gpio [11] ) ,
.io_pads_gpio_12_i_ival ( e203_i_ival_gpio [12] ) ,
.io_pads_gpio_12_o_oval ( e203_o_oval_gpio [12] ) ,
.io_pads_gpio_12_o_oe ( e203_o_oe_gpio [12] ) ,
.io_pads_gpio_12_o_ie ( e203_o_ie_gpio [12] ) ,
.io_pads_gpio_12_o_pue ( e203_o_pue_gpio [12] ) ,
.io_pads_gpio_12_o_ds ( e203_o_ds_gpio [12] ) ,
.io_pads_gpio_13_i_ival ( e203_i_ival_gpio [13] ) ,
.io_pads_gpio_13_o_oval ( e203_o_oval_gpio [13] ) ,
.io_pads_gpio_13_o_oe ( e203_o_oe_gpio [13] ) ,
.io_pads_gpio_13_o_ie ( e203_o_ie_gpio [13] ) ,
.io_pads_gpio_13_o_pue ( e203_o_pue_gpio [13] ) ,
.io_pads_gpio_13_o_ds ( e203_o_ds_gpio [13] ) ,
.io_pads_gpio_14_i_ival ( e203_i_ival_gpio [14] ) ,
.io_pads_gpio_14_o_oval ( e203_o_oval_gpio [14] ) ,
.io_pads_gpio_14_o_oe ( e203_o_oe_gpio [14] ) ,
.io_pads_gpio_14_o_ie ( e203_o_ie_gpio [14] ) ,
.io_pads_gpio_14_o_pue ( e203_o_pue_gpio [14] ) ,
.io_pads_gpio_14_o_ds ( e203_o_ds_gpio [14] ) ,
.io_pads_gpio_15_i_ival ( e203_i_ival_gpio [15] ) ,
.io_pads_gpio_15_o_oval ( e203_o_oval_gpio [15] ) ,
.io_pads_gpio_15_o_oe ( e203_o_oe_gpio [15] ) ,
.io_pads_gpio_15_o_ie ( e203_o_ie_gpio [15] ) ,
.io_pads_gpio_15_o_pue ( e203_o_pue_gpio [15] ) ,
.io_pads_gpio_15_o_ds ( e203_o_ds_gpio [15] ) ,
.io_pads_gpio_16_i_ival ( e203_i_ival_gpio [16] ) ,
.io_pads_gpio_16_o_oval ( e203_o_oval_gpio [16] ) ,
.io_pads_gpio_16_o_oe ( e203_o_oe_gpio [16] ) ,
.io_pads_gpio_16_o_ie ( e203_o_ie_gpio [16] ) ,
.io_pads_gpio_16_o_pue ( e203_o_pue_gpio [16] ) ,
.io_pads_gpio_16_o_ds ( e203_o_ds_gpio [16] ) ,
.io_pads_gpio_17_i_ival ( e203_i_ival_gpio [17] ) ,
.io_pads_gpio_17_o_oval ( e203_o_oval_gpio [17] ) ,
.io_pads_gpio_17_o_oe ( e203_o_oe_gpio [17] ) ,
.io_pads_gpio_17_o_ie ( e203_o_ie_gpio [17] ) ,
.io_pads_gpio_17_o_pue ( e203_o_pue_gpio [17] ) ,
.io_pads_gpio_17_o_ds ( e203_o_ds_gpio [17] ) ,
.io_pads_gpio_18_i_ival ( e203_i_ival_gpio [18] ) ,
.io_pads_gpio_18_o_oval ( e203_o_oval_gpio [18] ) ,
.io_pads_gpio_18_o_oe ( e203_o_oe_gpio [18] ) ,
.io_pads_gpio_18_o_ie ( e203_o_ie_gpio [18] ) ,
.io_pads_gpio_18_o_pue ( e203_o_pue_gpio [18] ) ,
.io_pads_gpio_18_o_ds ( e203_o_ds_gpio [18] ) ,
.io_pads_gpio_19_i_ival ( e203_i_ival_gpio [19] ) ,
.io_pads_gpio_19_o_oval ( e203_o_oval_gpio [19] ) ,
.io_pads_gpio_19_o_oe ( e203_o_oe_gpio [19] ) ,
.io_pads_gpio_19_o_ie ( e203_o_ie_gpio [19] ) ,
.io_pads_gpio_19_o_pue ( e203_o_pue_gpio [19] ) ,
.io_pads_gpio_19_o_ds ( e203_o_ds_gpio [19] ) ,
.io_pads_gpio_20_i_ival ( e203_i_ival_gpio [20] ) ,
.io_pads_gpio_20_o_oval ( e203_o_oval_gpio [20] ) ,
.io_pads_gpio_20_o_oe ( e203_o_oe_gpio [20] ) ,
.io_pads_gpio_20_o_ie ( e203_o_ie_gpio [20] ) ,
.io_pads_gpio_20_o_pue ( e203_o_pue_gpio [20] ) ,
.io_pads_gpio_20_o_ds ( e203_o_ds_gpio [20] ) ,
.io_pads_gpio_21_i_ival ( e203_i_ival_gpio [21] ) ,
.io_pads_gpio_21_o_oval ( e203_o_oval_gpio [21] ) ,
.io_pads_gpio_21_o_oe ( e203_o_oe_gpio [21] ) ,
.io_pads_gpio_21_o_ie ( e203_o_ie_gpio [21] ) ,
.io_pads_gpio_21_o_pue ( e203_o_pue_gpio [21] ) ,
.io_pads_gpio_21_o_ds ( e203_o_ds_gpio [21] ) ,
.io_pads_gpio_22_i_ival ( e203_i_ival_gpio [22] ) ,
.io_pads_gpio_22_o_oval ( e203_o_oval_gpio [22] ) ,
.io_pads_gpio_22_o_oe ( e203_o_oe_gpio [22] ) ,
.io_pads_gpio_22_o_ie ( e203_o_ie_gpio [22] ) ,
.io_pads_gpio_22_o_pue ( e203_o_pue_gpio [22] ) ,
.io_pads_gpio_22_o_ds ( e203_o_ds_gpio [22] ) ,
.io_pads_gpio_23_i_ival ( e203_i_ival_gpio [23] ) ,
.io_pads_gpio_23_o_oval ( e203_o_oval_gpio [23] ) ,
.io_pads_gpio_23_o_oe ( e203_o_oe_gpio [23] ) ,
.io_pads_gpio_23_o_ie ( e203_o_ie_gpio [23] ) ,
.io_pads_gpio_23_o_pue ( e203_o_pue_gpio [23] ) ,
.io_pads_gpio_23_o_ds ( e203_o_ds_gpio [23] ) ,
.io_pads_gpio_24_i_ival ( e203_i_ival_gpio [24] ) ,
.io_pads_gpio_24_o_oval ( e203_o_oval_gpio [24] ) ,
.io_pads_gpio_24_o_oe ( e203_o_oe_gpio [24] ) ,
.io_pads_gpio_24_o_ie ( e203_o_ie_gpio [24] ) ,
.io_pads_gpio_24_o_pue ( e203_o_pue_gpio [24] ) ,
.io_pads_gpio_24_o_ds ( e203_o_ds_gpio [24] ) ,
.io_pads_gpio_25_i_ival ( e203_i_ival_gpio [25] ) ,
.io_pads_gpio_25_o_oval ( e203_o_oval_gpio [25] ) ,
.io_pads_gpio_25_o_oe ( e203_o_oe_gpio [25] ) ,
.io_pads_gpio_25_o_ie ( e203_o_ie_gpio [25] ) ,
.io_pads_gpio_25_o_pue ( e203_o_pue_gpio [25] ) ,
.io_pads_gpio_25_o_ds ( e203_o_ds_gpio [25] ) ,
.io_pads_gpio_26_i_ival ( e203_i_ival_gpio [26] ) ,
.io_pads_gpio_26_o_oval ( e203_o_oval_gpio [26] ) ,
.io_pads_gpio_26_o_oe ( e203_o_oe_gpio [26] ) ,
.io_pads_gpio_26_o_ie ( e203_o_ie_gpio [26] ) ,
.io_pads_gpio_26_o_pue ( e203_o_pue_gpio [26] ) ,
.io_pads_gpio_26_o_ds ( e203_o_ds_gpio [26] ) ,
.io_pads_gpio_27_i_ival ( e203_i_ival_gpio [27] ) ,
.io_pads_gpio_27_o_oval ( e203_o_oval_gpio [27] ) ,
.io_pads_gpio_27_o_oe ( e203_o_oe_gpio [27] ) ,
.io_pads_gpio_27_o_ie ( e203_o_ie_gpio [27] ) ,
.io_pads_gpio_27_o_pue ( e203_o_pue_gpio [27] ) ,
.io_pads_gpio_27_o_ds ( e203_o_ds_gpio [27] ) ,
.io_pads_gpio_28_i_ival ( e203_i_ival_gpio [28] ) ,
.io_pads_gpio_28_o_oval ( e203_o_oval_gpio [28] ) ,
.io_pads_gpio_28_o_oe ( e203_o_oe_gpio [28] ) ,
.io_pads_gpio_28_o_ie ( e203_o_ie_gpio [28] ) ,
.io_pads_gpio_28_o_pue ( e203_o_pue_gpio [28] ) ,
.io_pads_gpio_28_o_ds ( e203_o_ds_gpio [28] ) ,
.io_pads_gpio_29_i_ival ( e203_i_ival_gpio [29] ) ,
.io_pads_gpio_29_o_oval ( e203_o_oval_gpio [29] ) ,
.io_pads_gpio_29_o_oe ( e203_o_oe_gpio [29] ) ,
.io_pads_gpio_29_o_ie ( e203_o_ie_gpio [29] ) ,
.io_pads_gpio_29_o_pue ( e203_o_pue_gpio [29] ) ,
.io_pads_gpio_29_o_ds ( e203_o_ds_gpio [29] ) ,
.io_pads_gpio_30_i_ival ( e203_i_ival_gpio [30] ) ,
.io_pads_gpio_30_o_oval ( e203_o_oval_gpio [30] ) ,
.io_pads_gpio_30_o_oe ( e203_o_oe_gpio [30] ) ,
.io_pads_gpio_30_o_ie ( e203_o_ie_gpio [30] ) ,
.io_pads_gpio_30_o_pue ( e203_o_pue_gpio [30] ) ,
.io_pads_gpio_30_o_ds ( e203_o_ds_gpio [30] ) ,
.io_pads_gpio_31_i_ival ( e203_i_ival_gpio [31] ) ,
.io_pads_gpio_31_o_oval ( e203_o_oval_gpio [31] ) ,
.io_pads_gpio_31_o_oe ( e203_o_oe_gpio [31] ) ,
.io_pads_gpio_31_o_ie ( e203_o_ie_gpio [31] ) ,
.io_pads_gpio_31_o_pue ( e203_o_pue_gpio [31] ) ,
.io_pads_gpio_31_o_ds ( e203_o_ds_gpio [31] ) ,
.io_pads_qspi_sck_o_oval ( e203_qspi_sck_o_oval ) ,
.io_pads_qspi_dq_0_i_ival ( e203_qspi_i_ival_dq [ 0] ) ,
.io_pads_qspi_dq_0_o_oval ( e203_qspi_o_oval_dq [ 0] ) ,
.io_pads_qspi_dq_0_o_oe ( e203_qspi_o_oe_dq [ 0] ) ,
.io_pads_qspi_dq_0_o_ie ( e203_qspi_o_ie_dq [ 0] ) ,
.io_pads_qspi_dq_0_o_pue ( e203_qspi_o_pue_dq [ 0] ) ,
.io_pads_qspi_dq_0_o_ds ( e203_qspi_o_ds_dq [ 0] ) ,
.io_pads_qspi_dq_1_i_ival ( e203_qspi_i_ival_dq [ 1] ) ,
.io_pads_qspi_dq_1_o_oval ( e203_qspi_o_oval_dq [ 1] ) ,
.io_pads_qspi_dq_1_o_oe ( e203_qspi_o_oe_dq [ 1] ) ,
.io_pads_qspi_dq_1_o_ie ( e203_qspi_o_ie_dq [ 1] ) ,
.io_pads_qspi_dq_1_o_pue ( e203_qspi_o_pue_dq [ 1] ) ,
.io_pads_qspi_dq_1_o_ds ( e203_qspi_o_ds_dq [ 1] ) ,
.io_pads_qspi_dq_2_i_ival ( e203_qspi_i_ival_dq [ 2] ) ,
.io_pads_qspi_dq_2_o_oval ( e203_qspi_o_oval_dq [ 2] ) ,
.io_pads_qspi_dq_2_o_oe ( e203_qspi_o_oe_dq [ 2] ) ,
.io_pads_qspi_dq_2_o_ie ( e203_qspi_o_ie_dq [ 2] ) ,
.io_pads_qspi_dq_2_o_pue ( e203_qspi_o_pue_dq [ 2] ) ,
.io_pads_qspi_dq_2_o_ds ( e203_qspi_o_ds_dq [ 2] ) ,
.io_pads_qspi_dq_3_i_ival ( e203_qspi_i_ival_dq [ 3] ) ,
.io_pads_qspi_dq_3_o_oval ( e203_qspi_o_oval_dq [ 3] ) ,
.io_pads_qspi_dq_3_o_oe ( e203_qspi_o_oe_dq [ 3] ) ,
.io_pads_qspi_dq_3_o_ie ( e203_qspi_o_ie_dq [ 3] ) ,
.io_pads_qspi_dq_3_o_pue ( e203_qspi_o_pue_dq [ 3] ) ,
.io_pads_qspi_dq_3_o_ds ( e203_qspi_o_ds_dq [ 3] ) ,
.io_pads_qspi_cs_0_o_oval ( e203_qspi_cs_0_o_oval ) ,
// Note: this is the real SoC top level reset signal
.io_pads_aon_erst_n_i_ival ( e203_aon_erst_n_i_ival ) ,
.io_pads_aon_pmu_dwakeup_n_i_ival ( e203_aon_pmu_dwakeup_n_i_ival ) ,
.io_pads_aon_pmu_vddpaden_o_oval ( e203_aon_pmu_vddpaden_o_oval ) ,
.io_pads_aon_pmu_padrst_o_oval ( e203_aon_pmu_padrst_o_oval ) ,
.io_pads_bootrom_n_i_ival ( e203_bootrom_n_i_ival ) ,
.io_pads_dbgmode0_n_i_ival ( e203_dbgmode0_n_i_ival ) ,
.io_pads_dbgmode1_n_i_ival ( e203_dbgmode1_n_i_ival ) ,
.io_pads_dbgmode2_n_i_ival ( e203_dbgmode2_n_i_ival )
);
endmodule |
module plusarg_reader #(parameter FORMAT="borked=%d", DEFAULT=0) (
output [31:0] out
);
`ifdef SYNTHESIS
assign out = DEFAULT;
`else
reg [31:0] myplus;
assign out = myplus;
// mask by daisy
//initial begin
// if (!$value$plusargs(FORMAT, myplus)) myplus = DEFAULT;
//end
`endif
endmodule |
module AsyncResetReg (d, q, en, clk, rst);
parameter RESET_VALUE = 0;
input wire d;
output reg q;
input wire en;
input wire clk;
input wire rst;
// There is a lot of initialization
// here you don't normally find in Verilog
// async registers because of scenarios in which reset
// is not actually asserted cleanly at time 0,
// and we want to make sure to properly model
// that, yet Chisel codebase is absolutely intolerant
// of Xs.
`ifndef SYNTHESIS
initial begin
`ifdef RANDOMIZE
integer initvar;
reg [31:0] _RAND;
_RAND = {1{$random}};
q = _RAND[0];
`endif // RANDOMIZE
if (rst) begin
q = RESET_VALUE;
end
end
`endif
always @(posedge clk or posedge rst) begin
if (rst) begin
q <= RESET_VALUE;
end else if (en) begin
q <= d;
end
end
endmodule // AsyncResetReg |
module SRLatch (
input set,
input reset,
output q
);
reg latch;
// synopsys async_set_reset "set"
// synopsys one_hot "set, reset"
always @(set or reset)
begin
if (set)
latch <= 1'b1;
else if (reset)
latch <= 1'b0;
end
assign q = latch;
endmodule |
module clkdivider
(
input wire clk,
input wire reset,
output reg clk_out
);
reg [7:0] counter;
always @(posedge clk)
begin
if (reset)
begin
counter <= 8'd0;
clk_out <= 1'b0;
end
// Bob: this original source code is wrong, because it is actually divided clock by 512, so correct it
//else if (counter == 8'hff)
else if (counter == 8'h7f)
begin
counter <= 8'd0;
clk_out <= ~clk_out;
end
else
begin
counter <= counter+1;
end
end
endmodule |
module Freedom_E300_Wrapper (
input wire clock,
input wire aon_lfextclk,
input wire aon_erst_n,
input wire jtag_reset,
output wire io_ndreset,
input wire jtag_tck,
input wire jtag_tms,
input wire jtag_tdi,
output wire jtag_tdo,
output wire qspi_sck,
output wire qspi_cs_0,
inout wire [3:0] qspi_dq,
input wire [31:0] e300_gpio_i_ival,
output wire [31:0] e300_gpio_o_ie,
output wire [31:0] e300_gpio_o_oval,
output wire [31:0] e300_gpio_o_oe
);
wire io_pins_jtag_TDO_o_oval;
wire io_pins_jtag_TDO_o_oe;
assign jtag_tdo = io_pins_jtag_TDO_o_oe ? io_pins_jtag_TDO_o_oval :1'bz;
assign qspi_dq[0] = io_pins_qspi_dq_0_o_oe ? io_pins_qspi_dq_0_o_oval :1'bz;
assign qspi_dq[1] = io_pins_qspi_dq_1_o_oe ? io_pins_qspi_dq_1_o_oval :1'bz;
assign qspi_dq[2] = io_pins_qspi_dq_2_o_oe ? io_pins_qspi_dq_2_o_oval :1'bz;
assign qspi_dq[3] = io_pins_qspi_dq_3_o_oe ? io_pins_qspi_dq_3_o_oval :1'bz;
assign io_pins_qspi_dq_0_i_ival = qspi_dq[0] & io_pins_qspi_dq_0_o_ie;
assign io_pins_qspi_dq_1_i_ival = qspi_dq[1] & io_pins_qspi_dq_1_o_ie;
assign io_pins_qspi_dq_2_i_ival = qspi_dq[2] & io_pins_qspi_dq_2_o_ie;
assign io_pins_qspi_dq_3_i_ival = qspi_dq[3] & io_pins_qspi_dq_3_o_ie;
E300ArtyDevKitPlatform E300ArtyDevKitPlatform_inst(
/*input */ .clock(clock),
/*input */ .io_pins_aon_erst_n_i_ival(aon_erst_n),
/*input */ .io_pins_aon_lfextclk_i_ival(aon_lfextclk),
/*output */ .io_ndreset(io_ndreset),
/*input */ .io_jtag_reset(jtag_reset),
/*input */ .io_pins_jtag_TCK_i_ival(jtag_tck),
/*input */ .io_pins_jtag_TMS_i_ival(jtag_tms),
/*input */ .io_pins_jtag_TDI_i_ival(jtag_tdi),
/*output */ .io_pins_jtag_TDO_o_oval(io_pins_jtag_TDO_o_oval),
/*output */ .io_pins_jtag_TDO_o_oe(io_pins_jtag_TDO_o_oe),
/*input */ .io_pins_gpio_pins_0_i_ival(e300_gpio_i_ival[0]),
/*output */ .io_pins_gpio_pins_0_o_oval(e300_gpio_o_oval[0]),
/*output */ .io_pins_gpio_pins_0_o_oe(e300_gpio_o_oe[0]),
/*output */ .io_pins_gpio_pins_0_o_ie(e300_gpio_o_ie[0]),
/*input */ .io_pins_gpio_pins_1_i_ival(e300_gpio_i_ival[1]),
/*output */ .io_pins_gpio_pins_1_o_oval(e300_gpio_o_oval[1]),
/*output */ .io_pins_gpio_pins_1_o_oe(e300_gpio_o_oe[1]),
/*output */ .io_pins_gpio_pins_1_o_ie(e300_gpio_o_ie[1]),
/*input */ .io_pins_gpio_pins_2_i_ival(e300_gpio_i_ival[2]),
/*output */ .io_pins_gpio_pins_2_o_oval(e300_gpio_o_oval[2]),
/*output */ .io_pins_gpio_pins_2_o_oe(e300_gpio_o_oe[2]),
/*output */ .io_pins_gpio_pins_2_o_ie(e300_gpio_o_ie[2]),
/*input */ .io_pins_gpio_pins_3_i_ival(e300_gpio_i_ival[3]),
/*output */ .io_pins_gpio_pins_3_o_oval(e300_gpio_o_oval[3]),
/*output */ .io_pins_gpio_pins_3_o_oe(e300_gpio_o_oe[3]),
/*output */ .io_pins_gpio_pins_3_o_ie(e300_gpio_o_ie[3]),
/*input */ .io_pins_gpio_pins_4_i_ival(e300_gpio_i_ival[4]),
/*output */ .io_pins_gpio_pins_4_o_oval(e300_gpio_o_oval[4]),
/*output */ .io_pins_gpio_pins_4_o_oe(e300_gpio_o_oe[4]),
/*output */ .io_pins_gpio_pins_4_o_ie(e300_gpio_o_ie[4]),
/*input */ .io_pins_gpio_pins_5_i_ival(e300_gpio_i_ival[5]),
/*output */ .io_pins_gpio_pins_5_o_oval(e300_gpio_o_oval[5]),
/*output */ .io_pins_gpio_pins_5_o_oe(e300_gpio_o_oe[5]),
/*output */ .io_pins_gpio_pins_5_o_ie(e300_gpio_o_ie[5]),
/*input */ .io_pins_gpio_pins_6_i_ival(e300_gpio_i_ival[6]),
/*output */ .io_pins_gpio_pins_6_o_oval(e300_gpio_o_oval[6]),
/*output */ .io_pins_gpio_pins_6_o_oe(e300_gpio_o_oe[6]),
/*output */ .io_pins_gpio_pins_6_o_ie(e300_gpio_o_ie[6]),
/*input */ .io_pins_gpio_pins_7_i_ival(e300_gpio_i_ival[7]),
/*output */ .io_pins_gpio_pins_7_o_oval(e300_gpio_o_oval[7]),
/*output */ .io_pins_gpio_pins_7_o_oe(e300_gpio_o_oe[7]),
/*output */ .io_pins_gpio_pins_7_o_ie(e300_gpio_o_ie[7]),
/*input */ .io_pins_gpio_pins_8_i_ival(e300_gpio_i_ival[8]),
/*output */ .io_pins_gpio_pins_8_o_oval(e300_gpio_o_oval[8]),
/*output */ .io_pins_gpio_pins_8_o_oe(e300_gpio_o_oe[8]),
/*output */ .io_pins_gpio_pins_8_o_ie(e300_gpio_o_ie[8]),
/*input */ .io_pins_gpio_pins_9_i_ival(e300_gpio_i_ival[9]),
/*output */ .io_pins_gpio_pins_9_o_oval(e300_gpio_o_oval[9]),
/*output */ .io_pins_gpio_pins_9_o_oe(e300_gpio_o_oe[9]),
/*output */ .io_pins_gpio_pins_9_o_ie(e300_gpio_o_ie[9]),
/*input */ .io_pins_gpio_pins_10_i_ival(e300_gpio_i_ival[10]),
/*output */ .io_pins_gpio_pins_10_o_oval(e300_gpio_o_oval[10]),
/*output */ .io_pins_gpio_pins_10_o_oe(e300_gpio_o_oe[10]),
/*output */ .io_pins_gpio_pins_10_o_ie(e300_gpio_o_ie[10]),
/*input */ .io_pins_gpio_pins_11_i_ival(e300_gpio_i_ival[11]),
/*output */ .io_pins_gpio_pins_11_o_oval(e300_gpio_o_oval[11]),
/*output */ .io_pins_gpio_pins_11_o_oe(e300_gpio_o_oe[11]),
/*output */ .io_pins_gpio_pins_11_o_ie(e300_gpio_o_ie[11]),
/*input */ .io_pins_gpio_pins_12_i_ival(e300_gpio_i_ival[12]),
/*output */ .io_pins_gpio_pins_12_o_oval(e300_gpio_o_oval[12]),
/*output */ .io_pins_gpio_pins_12_o_oe(e300_gpio_o_oe[12]),
/*output */ .io_pins_gpio_pins_12_o_ie(e300_gpio_o_ie[12]),
/*input */ .io_pins_gpio_pins_13_i_ival(e300_gpio_i_ival[13]),
/*output */ .io_pins_gpio_pins_13_o_oval(e300_gpio_o_oval[13]),
/*output */ .io_pins_gpio_pins_13_o_oe(e300_gpio_o_oe[13]),
/*output */ .io_pins_gpio_pins_13_o_ie(e300_gpio_o_ie[13]),
/*input */ .io_pins_gpio_pins_14_i_ival(e300_gpio_i_ival[14]),
/*output */ .io_pins_gpio_pins_14_o_oval(e300_gpio_o_oval[14]),
/*output */ .io_pins_gpio_pins_14_o_oe(e300_gpio_o_oe[14]),
/*output */ .io_pins_gpio_pins_14_o_ie(e300_gpio_o_ie[14]),
/*input */ .io_pins_gpio_pins_15_i_ival(e300_gpio_i_ival[15]),
/*output */ .io_pins_gpio_pins_15_o_oval(e300_gpio_o_oval[15]),
/*output */ .io_pins_gpio_pins_15_o_oe(e300_gpio_o_oe[15]),
/*output */ .io_pins_gpio_pins_15_o_ie(e300_gpio_o_ie[15]),
/*input */ .io_pins_gpio_pins_16_i_ival(e300_gpio_i_ival[16]),
/*output */ .io_pins_gpio_pins_16_o_oval(e300_gpio_o_oval[16]),
/*output */ .io_pins_gpio_pins_16_o_oe(e300_gpio_o_oe[16]),
/*output */ .io_pins_gpio_pins_16_o_ie(e300_gpio_o_ie[16]),
/*input */ .io_pins_gpio_pins_17_i_ival(e300_gpio_i_ival[17]),
/*output */ .io_pins_gpio_pins_17_o_oval(e300_gpio_o_oval[17]),
/*output */ .io_pins_gpio_pins_17_o_oe(e300_gpio_o_oe[17]),
/*output */ .io_pins_gpio_pins_17_o_ie(e300_gpio_o_ie[17]),
/*input */ .io_pins_gpio_pins_18_i_ival(e300_gpio_i_ival[18]),
/*output */ .io_pins_gpio_pins_18_o_oval(e300_gpio_o_oval[18]),
/*output */ .io_pins_gpio_pins_18_o_oe(e300_gpio_o_oe[18]),
/*output */ .io_pins_gpio_pins_18_o_ie(e300_gpio_o_ie[18]),
/*input */ .io_pins_gpio_pins_19_i_ival(e300_gpio_i_ival[19]),
/*output */ .io_pins_gpio_pins_19_o_oval(e300_gpio_o_oval[19]),
/*output */ .io_pins_gpio_pins_19_o_oe(e300_gpio_o_oe[19]),
/*output */ .io_pins_gpio_pins_19_o_ie(e300_gpio_o_ie[19]),
/*input */ .io_pins_gpio_pins_20_i_ival(e300_gpio_i_ival[20]),
/*output */ .io_pins_gpio_pins_20_o_oval(e300_gpio_o_oval[20]),
/*output */ .io_pins_gpio_pins_20_o_oe(e300_gpio_o_oe[20]),
/*output */ .io_pins_gpio_pins_20_o_ie(e300_gpio_o_ie[20]),
/*input */ .io_pins_gpio_pins_21_i_ival(e300_gpio_i_ival[21]),
/*output */ .io_pins_gpio_pins_21_o_oval(e300_gpio_o_oval[21]),
/*output */ .io_pins_gpio_pins_21_o_oe(e300_gpio_o_oe[21]),
/*output */ .io_pins_gpio_pins_21_o_ie(e300_gpio_o_ie[21]),
/*input */ .io_pins_gpio_pins_22_i_ival(e300_gpio_i_ival[22]),
/*output */ .io_pins_gpio_pins_22_o_oval(e300_gpio_o_oval[22]),
/*output */ .io_pins_gpio_pins_22_o_oe(e300_gpio_o_oe[22]),
/*output */ .io_pins_gpio_pins_22_o_ie(e300_gpio_o_ie[22]),
/*input */ .io_pins_gpio_pins_23_i_ival(e300_gpio_i_ival[23]),
/*output */ .io_pins_gpio_pins_23_o_oval(e300_gpio_o_oval[23]),
/*output */ .io_pins_gpio_pins_23_o_oe(e300_gpio_o_oe[23]),
/*output */ .io_pins_gpio_pins_23_o_ie(e300_gpio_o_ie[23]),
/*input */ .io_pins_gpio_pins_24_i_ival(e300_gpio_i_ival[24]),
/*output */ .io_pins_gpio_pins_24_o_oval(e300_gpio_o_oval[24]),
/*output */ .io_pins_gpio_pins_24_o_oe(e300_gpio_o_oe[24]),
/*output */ .io_pins_gpio_pins_24_o_ie(e300_gpio_o_ie[24]),
/*input */ .io_pins_gpio_pins_25_i_ival(e300_gpio_i_ival[25]),
/*output */ .io_pins_gpio_pins_25_o_oval(e300_gpio_o_oval[25]),
/*output */ .io_pins_gpio_pins_25_o_oe(e300_gpio_o_oe[25]),
/*output */ .io_pins_gpio_pins_25_o_ie(e300_gpio_o_ie[25]),
/*input */ .io_pins_gpio_pins_26_i_ival(e300_gpio_i_ival[26]),
/*output */ .io_pins_gpio_pins_26_o_oval(e300_gpio_o_oval[26]),
/*output */ .io_pins_gpio_pins_26_o_oe(e300_gpio_o_oe[26]),
/*output */ .io_pins_gpio_pins_26_o_ie(e300_gpio_o_ie[26]),
/*input */ .io_pins_gpio_pins_27_i_ival(e300_gpio_i_ival[27]),
/*output */ .io_pins_gpio_pins_27_o_oval(e300_gpio_o_oval[27]),
/*output */ .io_pins_gpio_pins_27_o_oe(e300_gpio_o_oe[27]),
/*output */ .io_pins_gpio_pins_27_o_ie(e300_gpio_o_ie[27]),
/*input */ .io_pins_gpio_pins_28_i_ival(e300_gpio_i_ival[28]),
/*output */ .io_pins_gpio_pins_28_o_oval(e300_gpio_o_oval[28]),
/*output */ .io_pins_gpio_pins_28_o_oe(e300_gpio_o_oe[28]),
/*output */ .io_pins_gpio_pins_28_o_ie(e300_gpio_o_ie[28]),
/*input */ .io_pins_gpio_pins_29_i_ival(e300_gpio_i_ival[29]),
/*output */ .io_pins_gpio_pins_29_o_oval(e300_gpio_o_oval[29]),
/*output */ .io_pins_gpio_pins_29_o_oe(e300_gpio_o_oe[29]),
/*output */ .io_pins_gpio_pins_29_o_ie(e300_gpio_o_ie[29]),
/*input */ .io_pins_gpio_pins_30_i_ival(e300_gpio_i_ival[30]),
/*output */ .io_pins_gpio_pins_30_o_oval(e300_gpio_o_oval[30]),
/*output */ .io_pins_gpio_pins_30_o_oe(e300_gpio_o_oe[30]),
/*output */ .io_pins_gpio_pins_30_o_ie(e300_gpio_o_ie[30]),
/*input */ .io_pins_gpio_pins_31_i_ival(e300_gpio_i_ival[31]),
/*output */ .io_pins_gpio_pins_31_o_oval(e300_gpio_o_oval[31]),
/*output */ .io_pins_gpio_pins_31_o_oe(e300_gpio_o_oe[31]),
/*output */ .io_pins_gpio_pins_31_o_ie(e300_gpio_o_ie[31]),
/*output */ .io_pins_qspi_sck_o_oval(qspi_sck),
/*output */ .io_pins_qspi_cs_0_o_oval(qspi_cs_0),
/*input */ .io_pins_qspi_dq_0_i_ival(io_pins_qspi_dq_0_i_ival),
/*output */ .io_pins_qspi_dq_0_o_oval(io_pins_qspi_dq_0_o_oval),
/*output */ .io_pins_qspi_dq_0_o_oe(io_pins_qspi_dq_0_o_oe),
/*output */ .io_pins_qspi_dq_0_o_ie(io_pins_qspi_dq_0_o_ie),
/*input */ .io_pins_qspi_dq_1_i_ival(io_pins_qspi_dq_1_i_ival),
/*output */ .io_pins_qspi_dq_1_o_oval(io_pins_qspi_dq_1_o_oval),
/*output */ .io_pins_qspi_dq_1_o_oe(io_pins_qspi_dq_1_o_oe),
/*output */ .io_pins_qspi_dq_1_o_ie(io_pins_qspi_dq_1_o_ie),
/*input */ .io_pins_qspi_dq_2_i_ival(io_pins_qspi_dq_2_i_ival),
/*output */ .io_pins_qspi_dq_2_o_oval(io_pins_qspi_dq_2_o_oval),
/*output */ .io_pins_qspi_dq_2_o_oe(io_pins_qspi_dq_2_o_oe),
/*output */ .io_pins_qspi_dq_2_o_ie(io_pins_qspi_dq_2_o_ie),
/*input */ .io_pins_qspi_dq_3_i_ival(io_pins_qspi_dq_3_i_ival),
/*output */ .io_pins_qspi_dq_3_o_oval(io_pins_qspi_dq_3_o_oval),
/*output */ .io_pins_qspi_dq_3_o_oe(io_pins_qspi_dq_3_o_oe),
/*output */ .io_pins_qspi_dq_3_o_ie(io_pins_qspi_dq_3_o_ie)
);
endmodule |
module SEG7_LUT ( oSEG,iDIG );
input [3:0] iDIG;
output [7:0] oSEG;
reg [7:0] oSEG;
always @(iDIG)
begin
case(iDIG)
4'h1: oSEG = 8'b01111001; // ---0----
4'h2: oSEG = 8'b00100100; // | |
4'h3: oSEG = 8'b00110000; // 5 1
4'h4: oSEG = 8'b00011001; // | |
4'h5: oSEG = 8'b00010010; // ---6----
4'h6: oSEG = 8'b00000010; // | |
4'h7: oSEG = 8'b01111000; // 4 2
4'h8: oSEG = 8'b00000000; // | |
4'h9: oSEG = 8'b00011000; // ---3---- .7
4'ha: oSEG = 8'b00001000;
4'hb: oSEG = 8'b00000011;
4'hc: oSEG = 8'b01000110;
4'hd: oSEG = 8'b00100001;
4'he: oSEG = 8'b00000110;
4'hf: oSEG = 8'b00001110; //C5P board's HEX is common anode
4'h0: oSEG = 8'b01000000; //this code use for default code ,so the point always light ,you can change it if you need.
endcase
end
endmodule |
module pll_sys (
areset,
inclk0,
c0,
locked);
input areset;
input inclk0;
output c0;
output locked;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 areset;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [0:0] sub_wire2 = 1'h0;
wire [4:0] sub_wire3;
wire sub_wire5;
wire sub_wire0 = inclk0;
wire [1:0] sub_wire1 = {sub_wire2, sub_wire0};
wire [0:0] sub_wire4 = sub_wire3[0:0];
wire c0 = sub_wire4;
wire locked = sub_wire5;
altpll altpll_component (
.areset (areset),
.inclk (sub_wire1),
.clk (sub_wire3),
.locked (sub_wire5),
.activeclock (),
.clkbad (),
.clkena ({6{1'b1}}),
.clkloss (),
.clkswitch (1'b0),
.configupdate (1'b0),
.enable0 (),
.enable1 (),
.extclk (),
.extclkena ({4{1'b1}}),
.fbin (1'b1),
.fbmimicbidir (),
.fbout (),
.fref (),
.icdrclk (),
.pfdena (1'b1),
.phasecounterselect ({4{1'b1}}),
.phasedone (),
.phasestep (1'b1),
.phaseupdown (1'b1),
.pllena (1'b1),
.scanaclr (1'b0),
.scanclk (1'b0),
.scanclkena (1'b1),
.scandata (1'b0),
.scandataout (),
.scandone (),
.scanread (1'b0),
.scanwrite (1'b0),
.sclkout0 (),
.sclkout1 (),
.vcooverrange (),
.vcounderrange ());
defparam
altpll_component.bandwidth_type = "AUTO",
altpll_component.clk0_divide_by = 12500,
altpll_component.clk0_duty_cycle = 50,
altpll_component.clk0_multiply_by = 2097,
altpll_component.clk0_phase_shift = "0",
altpll_component.compensate_clock = "CLK0",
altpll_component.inclk0_input_frequency = 20000,
altpll_component.intended_device_family = "MAX 10",
altpll_component.lpm_hint = "CBX_MODULE_PREFIX=pll_sys",
altpll_component.lpm_type = "altpll",
altpll_component.operation_mode = "NORMAL",
altpll_component.pll_type = "AUTO",
altpll_component.port_activeclock = "PORT_UNUSED",
altpll_component.port_areset = "PORT_USED",
altpll_component.port_clkbad0 = "PORT_UNUSED",
altpll_component.port_clkbad1 = "PORT_UNUSED",
altpll_component.port_clkloss = "PORT_UNUSED",
altpll_component.port_clkswitch = "PORT_UNUSED",
altpll_component.port_configupdate = "PORT_UNUSED",
altpll_component.port_fbin = "PORT_UNUSED",
altpll_component.port_inclk0 = "PORT_USED",
altpll_component.port_inclk1 = "PORT_UNUSED",
altpll_component.port_locked = "PORT_USED",
altpll_component.port_pfdena = "PORT_UNUSED",
altpll_component.port_phasecounterselect = "PORT_UNUSED",
altpll_component.port_phasedone = "PORT_UNUSED",
altpll_component.port_phasestep = "PORT_UNUSED",
altpll_component.port_phaseupdown = "PORT_UNUSED",
altpll_component.port_pllena = "PORT_UNUSED",
altpll_component.port_scanaclr = "PORT_UNUSED",
altpll_component.port_scanclk = "PORT_UNUSED",
altpll_component.port_scanclkena = "PORT_UNUSED",
altpll_component.port_scandata = "PORT_UNUSED",
altpll_component.port_scandataout = "PORT_UNUSED",
altpll_component.port_scandone = "PORT_UNUSED",
altpll_component.port_scanread = "PORT_UNUSED",
altpll_component.port_scanwrite = "PORT_UNUSED",
altpll_component.port_clk0 = "PORT_USED",
altpll_component.port_clk1 = "PORT_UNUSED",
altpll_component.port_clk2 = "PORT_UNUSED",
altpll_component.port_clk3 = "PORT_UNUSED",
altpll_component.port_clk4 = "PORT_UNUSED",
altpll_component.port_clk5 = "PORT_UNUSED",
altpll_component.port_clkena0 = "PORT_UNUSED",
altpll_component.port_clkena1 = "PORT_UNUSED",
altpll_component.port_clkena2 = "PORT_UNUSED",
altpll_component.port_clkena3 = "PORT_UNUSED",
altpll_component.port_clkena4 = "PORT_UNUSED",
altpll_component.port_clkena5 = "PORT_UNUSED",
altpll_component.port_extclk0 = "PORT_UNUSED",
altpll_component.port_extclk1 = "PORT_UNUSED",
altpll_component.port_extclk2 = "PORT_UNUSED",
altpll_component.port_extclk3 = "PORT_UNUSED",
altpll_component.self_reset_on_loss_lock = "OFF",
altpll_component.width_clock = 5;
endmodule |
module pll_sys_32m (
areset,
inclk0,
c0,
locked);
input areset;
input inclk0;
output c0;
output locked;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 areset;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [0:0] sub_wire2 = 1'h0;
wire [4:0] sub_wire3;
wire sub_wire5;
wire sub_wire0 = inclk0;
wire [1:0] sub_wire1 = {sub_wire2, sub_wire0};
wire [0:0] sub_wire4 = sub_wire3[0:0];
wire c0 = sub_wire4;
wire locked = sub_wire5;
altpll altpll_component (
.areset (areset),
.inclk (sub_wire1),
.clk (sub_wire3),
.locked (sub_wire5),
.activeclock (),
.clkbad (),
.clkena ({6{1'b1}}),
.clkloss (),
.clkswitch (1'b0),
.configupdate (1'b0),
.enable0 (),
.enable1 (),
.extclk (),
.extclkena ({4{1'b1}}),
.fbin (1'b1),
.fbmimicbidir (),
.fbout (),
.fref (),
.icdrclk (),
.pfdena (1'b1),
.phasecounterselect ({4{1'b1}}),
.phasedone (),
.phasestep (1'b1),
.phaseupdown (1'b1),
.pllena (1'b1),
.scanaclr (1'b0),
.scanclk (1'b0),
.scanclkena (1'b1),
.scandata (1'b0),
.scandataout (),
.scandone (),
.scanread (1'b0),
.scanwrite (1'b0),
.sclkout0 (),
.sclkout1 (),
.vcooverrange (),
.vcounderrange ());
defparam
altpll_component.bandwidth_type = "AUTO",
altpll_component.clk0_divide_by = 20,
altpll_component.clk0_duty_cycle = 50,
altpll_component.clk0_multiply_by = 13,
altpll_component.clk0_phase_shift = "0",
altpll_component.compensate_clock = "CLK0",
altpll_component.inclk0_input_frequency = 20000,
altpll_component.intended_device_family = "MAX 10",
altpll_component.lpm_hint = "CBX_MODULE_PREFIX=pll_sys_32m",
altpll_component.lpm_type = "altpll",
altpll_component.operation_mode = "NORMAL",
altpll_component.pll_type = "AUTO",
altpll_component.port_activeclock = "PORT_UNUSED",
altpll_component.port_areset = "PORT_USED",
altpll_component.port_clkbad0 = "PORT_UNUSED",
altpll_component.port_clkbad1 = "PORT_UNUSED",
altpll_component.port_clkloss = "PORT_UNUSED",
altpll_component.port_clkswitch = "PORT_UNUSED",
altpll_component.port_configupdate = "PORT_UNUSED",
altpll_component.port_fbin = "PORT_UNUSED",
altpll_component.port_inclk0 = "PORT_USED",
altpll_component.port_inclk1 = "PORT_UNUSED",
altpll_component.port_locked = "PORT_USED",
altpll_component.port_pfdena = "PORT_UNUSED",
altpll_component.port_phasecounterselect = "PORT_UNUSED",
altpll_component.port_phasedone = "PORT_UNUSED",
altpll_component.port_phasestep = "PORT_UNUSED",
altpll_component.port_phaseupdown = "PORT_UNUSED",
altpll_component.port_pllena = "PORT_UNUSED",
altpll_component.port_scanaclr = "PORT_UNUSED",
altpll_component.port_scanclk = "PORT_UNUSED",
altpll_component.port_scanclkena = "PORT_UNUSED",
altpll_component.port_scandata = "PORT_UNUSED",
altpll_component.port_scandataout = "PORT_UNUSED",
altpll_component.port_scandone = "PORT_UNUSED",
altpll_component.port_scanread = "PORT_UNUSED",
altpll_component.port_scanwrite = "PORT_UNUSED",
altpll_component.port_clk0 = "PORT_USED",
altpll_component.port_clk1 = "PORT_UNUSED",
altpll_component.port_clk2 = "PORT_UNUSED",
altpll_component.port_clk3 = "PORT_UNUSED",
altpll_component.port_clk4 = "PORT_UNUSED",
altpll_component.port_clk5 = "PORT_UNUSED",
altpll_component.port_clkena0 = "PORT_UNUSED",
altpll_component.port_clkena1 = "PORT_UNUSED",
altpll_component.port_clkena2 = "PORT_UNUSED",
altpll_component.port_clkena3 = "PORT_UNUSED",
altpll_component.port_clkena4 = "PORT_UNUSED",
altpll_component.port_clkena5 = "PORT_UNUSED",
altpll_component.port_extclk0 = "PORT_UNUSED",
altpll_component.port_extclk1 = "PORT_UNUSED",
altpll_component.port_extclk2 = "PORT_UNUSED",
altpll_component.port_extclk3 = "PORT_UNUSED",
altpll_component.self_reset_on_loss_lock = "OFF",
altpll_component.width_clock = 5;
endmodule |
module i2c_master_byte_ctrl (
clk, rst, nReset, ena, clk_cnt, start, stop, read, write, ack_in, din,
cmd_ack, ack_out, dout, i2c_busy, i2c_al, scl_i, scl_o, scl_oen, sda_i, sda_o, sda_oen );
//
// inputs & outputs
//
input clk; // master clock
input rst; // synchronous active high reset
input nReset; // asynchronous active low reset
input ena; // core enable signal
input [15:0] clk_cnt; // 4x SCL
// control inputs
input start;
input stop;
input read;
input write;
input ack_in;
input [7:0] din;
// status outputs
output cmd_ack;
reg cmd_ack;
output ack_out;
reg ack_out;
output i2c_busy;
output i2c_al;
output [7:0] dout;
// I2C signals
input scl_i;
output scl_o;
output scl_oen;
input sda_i;
output sda_o;
output sda_oen;
//
// Variable declarations
//
// statemachine
parameter [4:0] ST_IDLE = 5'b0_0000;
parameter [4:0] ST_START = 5'b0_0001;
parameter [4:0] ST_READ = 5'b0_0010;
parameter [4:0] ST_WRITE = 5'b0_0100;
parameter [4:0] ST_ACK = 5'b0_1000;
parameter [4:0] ST_STOP = 5'b1_0000;
// signals for bit_controller
reg [3:0] core_cmd;
reg core_txd;
wire core_ack, core_rxd;
// signals for shift register
reg [7:0] sr; //8bit shift register
reg shift, ld;
// signals for state machine
wire go;
reg [2:0] dcnt;
wire cnt_done;
//
// Module body
//
// hookup bit_controller
i2c_master_bit_ctrl bit_controller (
.clk ( clk ),
.rst ( rst ),
.nReset ( nReset ),
.ena ( ena ),
.clk_cnt ( clk_cnt ),
.cmd ( core_cmd ),
.cmd_ack ( core_ack ),
.busy ( i2c_busy ),
.al ( i2c_al ),
.din ( core_txd ),
.dout ( core_rxd ),
.scl_i ( scl_i ),
.scl_o ( scl_o ),
.scl_oen ( scl_oen ),
.sda_i ( sda_i ),
.sda_o ( sda_o ),
.sda_oen ( sda_oen )
);
// generate go-signal
assign go = (read | write | stop) & ~cmd_ack;
// assign dout output to shift-register
assign dout = sr;
// generate shift register
always @(posedge clk or negedge nReset)
if (!nReset)
sr <= #1 8'h0;
else if (rst)
sr <= #1 8'h0;
else if (ld)
sr <= #1 din;
else if (shift)
sr <= #1 {sr[6:0], core_rxd};
// generate counter
always @(posedge clk or negedge nReset)
if (!nReset)
dcnt <= #1 3'h0;
else if (rst)
dcnt <= #1 3'h0;
else if (ld)
dcnt <= #1 3'h7;
else if (shift)
dcnt <= #1 dcnt - 3'h1;
assign cnt_done = ~(|dcnt);
//
// state machine
//
reg [4:0] c_state; // synopsis enum_state
always @(posedge clk or negedge nReset)
if (!nReset)
begin
core_cmd <= #1 `I2C_CMD_NOP;
core_txd <= #1 1'b0;
shift <= #1 1'b0;
ld <= #1 1'b0;
cmd_ack <= #1 1'b0;
c_state <= #1 ST_IDLE;
ack_out <= #1 1'b0;
end
else if (rst | i2c_al)
begin
core_cmd <= #1 `I2C_CMD_NOP;
core_txd <= #1 1'b0;
shift <= #1 1'b0;
ld <= #1 1'b0;
cmd_ack <= #1 1'b0;
c_state <= #1 ST_IDLE;
ack_out <= #1 1'b0;
end
else
begin
// initially reset all signals
core_txd <= #1 sr[7];
shift <= #1 1'b0;
ld <= #1 1'b0;
cmd_ack <= #1 1'b0;
case (c_state) // synopsys full_case parallel_case
ST_IDLE:
if (go)
begin
if (start)
begin
c_state <= #1 ST_START;
core_cmd <= #1 `I2C_CMD_START;
end
else if (read)
begin
c_state <= #1 ST_READ;
core_cmd <= #1 `I2C_CMD_READ;
end
else if (write)
begin
c_state <= #1 ST_WRITE;
core_cmd <= #1 `I2C_CMD_WRITE;
end
else // stop
begin
c_state <= #1 ST_STOP;
core_cmd <= #1 `I2C_CMD_STOP;
end
ld <= #1 1'b1;
end
ST_START:
if (core_ack)
begin
if (read)
begin
c_state <= #1 ST_READ;
core_cmd <= #1 `I2C_CMD_READ;
end
else
begin
c_state <= #1 ST_WRITE;
core_cmd <= #1 `I2C_CMD_WRITE;
end
ld <= #1 1'b1;
end
ST_WRITE:
if (core_ack)
if (cnt_done)
begin
c_state <= #1 ST_ACK;
core_cmd <= #1 `I2C_CMD_READ;
end
else
begin
c_state <= #1 ST_WRITE; // stay in same state
core_cmd <= #1 `I2C_CMD_WRITE; // write next bit
shift <= #1 1'b1;
end
ST_READ:
if (core_ack)
begin
if (cnt_done)
begin
c_state <= #1 ST_ACK;
core_cmd <= #1 `I2C_CMD_WRITE;
end
else
begin
c_state <= #1 ST_READ; // stay in same state
core_cmd <= #1 `I2C_CMD_READ; // read next bit
end
shift <= #1 1'b1;
core_txd <= #1 ack_in;
end
ST_ACK:
if (core_ack)
begin
if (stop)
begin
c_state <= #1 ST_STOP;
core_cmd <= #1 `I2C_CMD_STOP;
end
else
begin
c_state <= #1 ST_IDLE;
core_cmd <= #1 `I2C_CMD_NOP;
// generate command acknowledge signal
cmd_ack <= #1 1'b1;
end
// assign ack_out output to bit_controller_rxd (contains last received bit)
ack_out <= #1 core_rxd;
core_txd <= #1 1'b1;
end
else
core_txd <= #1 ack_in;
ST_STOP:
if (core_ack)
begin
c_state <= #1 ST_IDLE;
core_cmd <= #1 `I2C_CMD_NOP;
// generate command acknowledge signal
cmd_ack <= #1 1'b1;
end
endcase
end
endmodule |
module e203_reset_ctrl #(
parameter MASTER = 1
)(
input clk, // clock
input rst_n, // async reset
input test_mode, // test mode
// The core's clk and rst
output rst_core,
// The ITCM/DTCM clk and rst
`ifdef E203_HAS_ITCM
output rst_itcm,
`endif
`ifdef E203_HAS_DTCM
output rst_dtcm,
`endif
// The Top always on clk and rst
output rst_aon
);
wire rst_sync_n;
`ifndef E203_HAS_LOCKSTEP//{
localparam RST_SYNC_LEVEL = `E203_ASYNC_FF_LEVELS;
`endif//}
reg [RST_SYNC_LEVEL-1:0] rst_sync_r;
generate
if(MASTER == 1) begin:master_gen
always @(posedge clk or negedge rst_n)
begin:rst_sync_PROC
if(rst_n == 1'b0)
begin
rst_sync_r[RST_SYNC_LEVEL-1:0] <= {RST_SYNC_LEVEL{1'b0}};
end
else
begin
rst_sync_r[RST_SYNC_LEVEL-1:0] <= {rst_sync_r[RST_SYNC_LEVEL-2:0],1'b1};
end
end
assign rst_sync_n = test_mode ? rst_n : rst_sync_r[`E203_ASYNC_FF_LEVELS-1];
end
else begin:slave_gen
// Just pass through for slave in lockstep mode
always @ *
begin:rst_sync_PROC
rst_sync_r = {RST_SYNC_LEVEL{1'b0}};
end
assign rst_sync_n = rst_n;
end
endgenerate
// The core's clk and rst
assign rst_core = rst_sync_n;
// The ITCM/DTCM clk and rst
`ifdef E203_HAS_ITCM
assign rst_itcm = rst_sync_n;
`endif
`ifdef E203_HAS_DTCM
assign rst_dtcm = rst_sync_n;
`endif
// The Top always on clk and rst
assign rst_aon = rst_sync_n;
endmodule |
module sirv_clint(
input clock,
input reset,
output io_in_0_a_ready,
input io_in_0_a_valid,
input [2:0] io_in_0_a_bits_opcode,
input [2:0] io_in_0_a_bits_param,
input [2:0] io_in_0_a_bits_size,
input [4:0] io_in_0_a_bits_source,
input [25:0] io_in_0_a_bits_address,
input [3:0] io_in_0_a_bits_mask,
input [31:0] io_in_0_a_bits_data,
input io_in_0_b_ready,
output io_in_0_b_valid,
output [2:0] io_in_0_b_bits_opcode,
output [1:0] io_in_0_b_bits_param,
output [2:0] io_in_0_b_bits_size,
output [4:0] io_in_0_b_bits_source,
output [25:0] io_in_0_b_bits_address,
output [3:0] io_in_0_b_bits_mask,
output [31:0] io_in_0_b_bits_data,
output io_in_0_c_ready,
input io_in_0_c_valid,
input [2:0] io_in_0_c_bits_opcode,
input [2:0] io_in_0_c_bits_param,
input [2:0] io_in_0_c_bits_size,
input [4:0] io_in_0_c_bits_source,
input [25:0] io_in_0_c_bits_address,
input [31:0] io_in_0_c_bits_data,
input io_in_0_c_bits_error,
input io_in_0_d_ready,
output io_in_0_d_valid,
output [2:0] io_in_0_d_bits_opcode,
output [1:0] io_in_0_d_bits_param,
output [2:0] io_in_0_d_bits_size,
output [4:0] io_in_0_d_bits_source,
output io_in_0_d_bits_sink,
output [1:0] io_in_0_d_bits_addr_lo,
output [31:0] io_in_0_d_bits_data,
output io_in_0_d_bits_error,
output io_in_0_e_ready,
input io_in_0_e_valid,
input io_in_0_e_bits_sink,
output io_tiles_0_mtip,
output io_tiles_0_msip,
input io_rtcTick
);
reg [31:0] time_0;
reg [31:0] GEN_62;
reg [31:0] time_1;
reg [31:0] GEN_63;
wire [63:0] T_904;
wire [64:0] T_906;
wire [63:0] T_907;
wire [31:0] T_909;
wire [63:0] GEN_6;
wire [31:0] GEN_7;
reg [31:0] timecmp_0_0;
reg [31:0] GEN_64;
reg [31:0] timecmp_0_1;
reg [31:0] GEN_65;
reg ipi_0;
reg [31:0] GEN_66;
wire [63:0] T_915;
wire T_916;
wire T_940_ready;
wire T_940_valid;
wire T_940_bits_read;
wire [13:0] T_940_bits_index;
wire [31:0] T_940_bits_data;
wire [3:0] T_940_bits_mask;
wire [9:0] T_940_bits_extra;
wire T_957;
wire [23:0] T_958;
wire [1:0] T_959;
wire [6:0] T_960;
wire [9:0] T_961;
wire T_979_ready;
wire T_979_valid;
wire T_979_bits_read;
wire [31:0] T_979_bits_data;
wire [9:0] T_979_bits_extra;
wire T_1015_ready;
wire T_1015_valid;
wire T_1015_bits_read;
wire [13:0] T_1015_bits_index;
wire [31:0] T_1015_bits_data;
wire [3:0] T_1015_bits_mask;
wire [9:0] T_1015_bits_extra;
wire T_1058_0;
wire T_1058_1;
wire T_1058_2;
wire T_1058_3;
wire T_1058_4;
wire T_1063_0;
wire T_1063_1;
wire T_1063_2;
wire T_1063_3;
wire T_1063_4;
wire T_1068_0;
wire T_1068_1;
wire T_1068_2;
wire T_1068_3;
wire T_1068_4;
wire T_1073_0;
wire T_1073_1;
wire T_1073_2;
wire T_1073_3;
wire T_1073_4;
wire T_1078_0;
wire T_1078_1;
wire T_1078_2;
wire T_1078_3;
wire T_1078_4;
wire T_1083_0;
wire T_1083_1;
wire T_1083_2;
wire T_1083_3;
wire T_1083_4;
wire T_1088_0;
wire T_1088_1;
wire T_1088_2;
wire T_1088_3;
wire T_1088_4;
wire T_1093_0;
wire T_1093_1;
wire T_1093_2;
wire T_1093_3;
wire T_1093_4;
wire T_1135;
wire T_1136;
wire T_1137;
wire T_1138;
wire [7:0] T_1142;
wire [7:0] T_1146;
wire [7:0] T_1150;
wire [7:0] T_1154;
wire [15:0] T_1155;
wire [15:0] T_1156;
wire [31:0] T_1157;
wire [31:0] T_1185;
wire T_1187;
wire T_1200;
wire [31:0] GEN_8;
wire [31:0] T_1219;
wire T_1240;
wire [31:0] GEN_9;
wire T_1280;
wire [63:0] GEN_10;
wire T_1320;
wire [31:0] GEN_11;
wire T_1360;
wire [31:0] GEN_12;
wire T_1421_0;
wire T_1421_1;
wire T_1421_2;
wire T_1421_3;
wire T_1421_4;
wire T_1421_5;
wire T_1421_6;
wire T_1421_7;
wire T_1472_0;
wire T_1472_1;
wire T_1472_2;
wire T_1472_3;
wire T_1472_4;
wire T_1472_5;
wire T_1472_6;
wire T_1472_7;
wire T_1523_0;
wire T_1523_1;
wire T_1523_2;
wire T_1523_3;
wire T_1523_4;
wire T_1523_5;
wire T_1523_6;
wire T_1523_7;
wire T_1574_0;
wire T_1574_1;
wire T_1574_2;
wire T_1574_3;
wire T_1574_4;
wire T_1574_5;
wire T_1574_6;
wire T_1574_7;
wire T_1585;
wire T_1586;
wire T_1597;
wire [1:0] T_1599;
wire [2:0] T_1600;
wire GEN_0;
wire GEN_13;
wire GEN_14;
wire GEN_15;
wire GEN_16;
wire GEN_17;
wire GEN_18;
wire GEN_19;
wire GEN_1;
wire GEN_20;
wire GEN_21;
wire GEN_22;
wire GEN_23;
wire GEN_24;
wire GEN_25;
wire GEN_26;
wire T_1619;
wire GEN_2;
wire GEN_27;
wire GEN_28;
wire GEN_29;
wire GEN_30;
wire GEN_31;
wire GEN_32;
wire GEN_33;
wire GEN_3;
wire GEN_34;
wire GEN_35;
wire GEN_36;
wire GEN_37;
wire GEN_38;
wire GEN_39;
wire GEN_40;
wire T_1622;
wire T_1623;
wire T_1624;
wire T_1625;
wire T_1626;
wire [7:0] T_1628;
wire T_1647;
wire T_1648;
wire T_1649;
wire T_1650;
wire T_1653;
wire T_1654;
wire T_1656;
wire T_1657;
wire T_1658;
wire T_1660;
wire T_1664;
wire T_1666;
wire T_1689;
wire T_1690;
wire T_1696;
wire T_1700;
wire T_1706;
wire T_1709;
wire T_1710;
wire T_1716;
wire T_1720;
wire T_1726;
wire T_1729;
wire T_1730;
wire T_1736;
wire T_1740;
wire T_1746;
wire T_1749;
wire T_1750;
wire T_1756;
wire T_1760;
wire T_1766;
wire T_1838_0;
wire T_1838_1;
wire T_1838_2;
wire T_1838_3;
wire T_1838_4;
wire T_1838_5;
wire T_1838_6;
wire T_1838_7;
wire [31:0] T_1861_0;
wire [31:0] T_1861_1;
wire [31:0] T_1861_2;
wire [31:0] T_1861_3;
wire [31:0] T_1861_4;
wire [31:0] T_1861_5;
wire [31:0] T_1861_6;
wire [31:0] T_1861_7;
wire GEN_4;
wire GEN_41;
wire GEN_42;
wire GEN_43;
wire GEN_44;
wire GEN_45;
wire GEN_46;
wire GEN_47;
wire [31:0] GEN_5;
wire [31:0] GEN_48;
wire [31:0] GEN_49;
wire [31:0] GEN_50;
wire [31:0] GEN_51;
wire [31:0] GEN_52;
wire [31:0] GEN_53;
wire [31:0] GEN_54;
wire [31:0] T_1874;
wire [1:0] T_1875;
wire [4:0] T_1877;
wire [2:0] T_1878;
wire [2:0] T_1889_opcode;
wire [1:0] T_1889_param;
wire [2:0] T_1889_size;
wire [4:0] T_1889_source;
wire T_1889_sink;
wire [1:0] T_1889_addr_lo;
wire [31:0] T_1889_data;
wire T_1889_error;
wire [2:0] GEN_55 = 3'b0;
reg [31:0] GEN_67;
wire [1:0] GEN_56 = 2'b0;
reg [31:0] GEN_68;
wire [2:0] GEN_57 = 3'b0;
reg [31:0] GEN_69;
wire [4:0] GEN_58 = 5'b0;
reg [31:0] GEN_70;
wire [25:0] GEN_59 = 26'b0;
reg [31:0] GEN_71;
wire [3:0] GEN_60 = 4'b0;
reg [31:0] GEN_72;
wire [31:0] GEN_61 = 32'b0;
reg [31:0] GEN_73;
assign io_in_0_a_ready = T_940_ready;
assign io_in_0_b_valid = 1'h0;
assign io_in_0_b_bits_opcode = GEN_55;
assign io_in_0_b_bits_param = GEN_56;
assign io_in_0_b_bits_size = GEN_57;
assign io_in_0_b_bits_source = GEN_58;
assign io_in_0_b_bits_address = GEN_59;
assign io_in_0_b_bits_mask = GEN_60;
assign io_in_0_b_bits_data = GEN_61;
assign io_in_0_c_ready = 1'h1;
assign io_in_0_d_valid = T_979_valid;
assign io_in_0_d_bits_opcode = {{2'd0}, T_979_bits_read};
assign io_in_0_d_bits_param = T_1889_param;
assign io_in_0_d_bits_size = T_1889_size;
assign io_in_0_d_bits_source = T_1889_source;
assign io_in_0_d_bits_sink = T_1889_sink;
assign io_in_0_d_bits_addr_lo = T_1889_addr_lo;
assign io_in_0_d_bits_data = T_979_bits_data;
assign io_in_0_d_bits_error = T_1889_error;
assign io_in_0_e_ready = 1'h1;
assign io_tiles_0_mtip = T_916;
assign io_tiles_0_msip = ipi_0;
assign T_904 = {time_1,time_0};
assign T_906 = T_904 + 64'h1;
assign T_907 = T_906[63:0];
assign T_909 = T_907[63:32];
assign GEN_6 = io_rtcTick ? T_907 : {{32'd0}, time_0};
assign GEN_7 = io_rtcTick ? T_909 : time_1;
assign T_915 = {timecmp_0_1,timecmp_0_0};
assign T_916 = T_904 >= T_915;
assign T_940_ready = T_1623;
assign T_940_valid = io_in_0_a_valid;
assign T_940_bits_read = T_957;
assign T_940_bits_index = T_958[13:0];
assign T_940_bits_data = io_in_0_a_bits_data;
assign T_940_bits_mask = io_in_0_a_bits_mask;
assign T_940_bits_extra = T_961;
assign T_957 = io_in_0_a_bits_opcode == 3'h4;
assign T_958 = io_in_0_a_bits_address[25:2];
assign T_959 = io_in_0_a_bits_address[1:0];
assign T_960 = {T_959,io_in_0_a_bits_source};
assign T_961 = {T_960,io_in_0_a_bits_size};
assign T_979_ready = io_in_0_d_ready;
assign T_979_valid = T_1626;
assign T_979_bits_read = T_1015_bits_read;
assign T_979_bits_data = T_1874;
assign T_979_bits_extra = T_1015_bits_extra;
assign T_1015_ready = T_1625;
assign T_1015_valid = T_1624;
assign T_1015_bits_read = T_940_bits_read;
assign T_1015_bits_index = T_940_bits_index;
assign T_1015_bits_data = T_940_bits_data;
assign T_1015_bits_mask = T_940_bits_mask;
assign T_1015_bits_extra = T_940_bits_extra;
assign T_1058_0 = T_1650;
assign T_1058_1 = T_1750;
assign T_1058_2 = T_1690;
assign T_1058_3 = T_1710;
assign T_1058_4 = T_1730;
assign T_1063_0 = T_1656;
assign T_1063_1 = T_1756;
assign T_1063_2 = T_1696;
assign T_1063_3 = T_1716;
assign T_1063_4 = T_1736;
assign T_1068_0 = 1'h1;
assign T_1068_1 = 1'h1;
assign T_1068_2 = 1'h1;
assign T_1068_3 = 1'h1;
assign T_1068_4 = 1'h1;
assign T_1073_0 = 1'h1;
assign T_1073_1 = 1'h1;
assign T_1073_2 = 1'h1;
assign T_1073_3 = 1'h1;
assign T_1073_4 = 1'h1;
assign T_1078_0 = 1'h1;
assign T_1078_1 = 1'h1;
assign T_1078_2 = 1'h1;
assign T_1078_3 = 1'h1;
assign T_1078_4 = 1'h1;
assign T_1083_0 = 1'h1;
assign T_1083_1 = 1'h1;
assign T_1083_2 = 1'h1;
assign T_1083_3 = 1'h1;
assign T_1083_4 = 1'h1;
assign T_1088_0 = T_1660;
assign T_1088_1 = T_1760;
assign T_1088_2 = T_1700;
assign T_1088_3 = T_1720;
assign T_1088_4 = T_1740;
assign T_1093_0 = T_1666;
assign T_1093_1 = T_1766;
assign T_1093_2 = T_1706;
assign T_1093_3 = T_1726;
assign T_1093_4 = T_1746;
assign T_1135 = T_1015_bits_mask[0];
assign T_1136 = T_1015_bits_mask[1];
assign T_1137 = T_1015_bits_mask[2];
assign T_1138 = T_1015_bits_mask[3];
assign T_1142 = T_1135 ? 8'hff : 8'h0;
assign T_1146 = T_1136 ? 8'hff : 8'h0;
assign T_1150 = T_1137 ? 8'hff : 8'h0;
assign T_1154 = T_1138 ? 8'hff : 8'h0;
assign T_1155 = {T_1146,T_1142};
assign T_1156 = {T_1154,T_1150};
assign T_1157 = {T_1156,T_1155};
assign T_1185 = ~ T_1157;
assign T_1187 = T_1185 == 32'h0;
assign T_1200 = T_1093_0 & T_1187;
assign GEN_8 = T_1200 ? T_1015_bits_data : {{31'd0}, ipi_0};
assign T_1219 = {{31'd0}, ipi_0};
assign T_1240 = T_1093_1 & T_1187;
assign GEN_9 = T_1240 ? T_1015_bits_data : timecmp_0_1;
assign T_1280 = T_1093_2 & T_1187;
assign GEN_10 = T_1280 ? {{32'd0}, T_1015_bits_data} : GEN_6;
assign T_1320 = T_1093_3 & T_1187;
assign GEN_11 = T_1320 ? T_1015_bits_data : GEN_7;
assign T_1360 = T_1093_4 & T_1187;
assign GEN_12 = T_1360 ? T_1015_bits_data : timecmp_0_0;
assign T_1421_0 = T_1068_0;
assign T_1421_1 = 1'h1;
assign T_1421_2 = T_1068_2;
assign T_1421_3 = T_1068_3;
assign T_1421_4 = T_1068_4;
assign T_1421_5 = T_1068_1;
assign T_1421_6 = 1'h1;
assign T_1421_7 = 1'h1;
assign T_1472_0 = T_1073_0;
assign T_1472_1 = 1'h1;
assign T_1472_2 = T_1073_2;
assign T_1472_3 = T_1073_3;
assign T_1472_4 = T_1073_4;
assign T_1472_5 = T_1073_1;
assign T_1472_6 = 1'h1;
assign T_1472_7 = 1'h1;
assign T_1523_0 = T_1078_0;
assign T_1523_1 = 1'h1;
assign T_1523_2 = T_1078_2;
assign T_1523_3 = T_1078_3;
assign T_1523_4 = T_1078_4;
assign T_1523_5 = T_1078_1;
assign T_1523_6 = 1'h1;
assign T_1523_7 = 1'h1;
assign T_1574_0 = T_1083_0;
assign T_1574_1 = 1'h1;
assign T_1574_2 = T_1083_2;
assign T_1574_3 = T_1083_3;
assign T_1574_4 = T_1083_4;
assign T_1574_5 = T_1083_1;
assign T_1574_6 = 1'h1;
assign T_1574_7 = 1'h1;
assign T_1585 = T_1015_bits_index[0];
assign T_1586 = T_1015_bits_index[1];
assign T_1597 = T_1015_bits_index[12];
assign T_1599 = {T_1597,T_1586};
assign T_1600 = {T_1599,T_1585};
assign GEN_0 = GEN_19;
assign GEN_13 = 3'h1 == T_1600 ? T_1421_1 : T_1421_0;
assign GEN_14 = 3'h2 == T_1600 ? T_1421_2 : GEN_13;
assign GEN_15 = 3'h3 == T_1600 ? T_1421_3 : GEN_14;
assign GEN_16 = 3'h4 == T_1600 ? T_1421_4 : GEN_15;
assign GEN_17 = 3'h5 == T_1600 ? T_1421_5 : GEN_16;
assign GEN_18 = 3'h6 == T_1600 ? T_1421_6 : GEN_17;
assign GEN_19 = 3'h7 == T_1600 ? T_1421_7 : GEN_18;
assign GEN_1 = GEN_26;
assign GEN_20 = 3'h1 == T_1600 ? T_1472_1 : T_1472_0;
assign GEN_21 = 3'h2 == T_1600 ? T_1472_2 : GEN_20;
assign GEN_22 = 3'h3 == T_1600 ? T_1472_3 : GEN_21;
assign GEN_23 = 3'h4 == T_1600 ? T_1472_4 : GEN_22;
assign GEN_24 = 3'h5 == T_1600 ? T_1472_5 : GEN_23;
assign GEN_25 = 3'h6 == T_1600 ? T_1472_6 : GEN_24;
assign GEN_26 = 3'h7 == T_1600 ? T_1472_7 : GEN_25;
assign T_1619 = T_1015_bits_read ? GEN_0 : GEN_1;
assign GEN_2 = GEN_33;
assign GEN_27 = 3'h1 == T_1600 ? T_1523_1 : T_1523_0;
assign GEN_28 = 3'h2 == T_1600 ? T_1523_2 : GEN_27;
assign GEN_29 = 3'h3 == T_1600 ? T_1523_3 : GEN_28;
assign GEN_30 = 3'h4 == T_1600 ? T_1523_4 : GEN_29;
assign GEN_31 = 3'h5 == T_1600 ? T_1523_5 : GEN_30;
assign GEN_32 = 3'h6 == T_1600 ? T_1523_6 : GEN_31;
assign GEN_33 = 3'h7 == T_1600 ? T_1523_7 : GEN_32;
assign GEN_3 = GEN_40;
assign GEN_34 = 3'h1 == T_1600 ? T_1574_1 : T_1574_0;
assign GEN_35 = 3'h2 == T_1600 ? T_1574_2 : GEN_34;
assign GEN_36 = 3'h3 == T_1600 ? T_1574_3 : GEN_35;
assign GEN_37 = 3'h4 == T_1600 ? T_1574_4 : GEN_36;
assign GEN_38 = 3'h5 == T_1600 ? T_1574_5 : GEN_37;
assign GEN_39 = 3'h6 == T_1600 ? T_1574_6 : GEN_38;
assign GEN_40 = 3'h7 == T_1600 ? T_1574_7 : GEN_39;
assign T_1622 = T_1015_bits_read ? GEN_2 : GEN_3;
assign T_1623 = T_1015_ready & T_1619;
assign T_1624 = T_940_valid & T_1619;
assign T_1625 = T_979_ready & T_1622;
assign T_1626 = T_1015_valid & T_1622;
assign T_1628 = 8'h1 << T_1600;
assign T_1647 = T_940_valid & T_1015_ready;
assign T_1648 = T_1647 & T_1015_bits_read;
assign T_1649 = T_1628[0];
assign T_1650 = T_1648 & T_1649;
assign T_1653 = T_1015_bits_read == 1'h0;
assign T_1654 = T_1647 & T_1653;
assign T_1656 = T_1654 & T_1649;
assign T_1657 = T_1015_valid & T_979_ready;
assign T_1658 = T_1657 & T_1015_bits_read;
assign T_1660 = T_1658 & T_1649;
assign T_1664 = T_1657 & T_1653;
assign T_1666 = T_1664 & T_1649;
assign T_1689 = T_1628[2];
assign T_1690 = T_1648 & T_1689;
assign T_1696 = T_1654 & T_1689;
assign T_1700 = T_1658 & T_1689;
assign T_1706 = T_1664 & T_1689;
assign T_1709 = T_1628[3];
assign T_1710 = T_1648 & T_1709;
assign T_1716 = T_1654 & T_1709;
assign T_1720 = T_1658 & T_1709;
assign T_1726 = T_1664 & T_1709;
assign T_1729 = T_1628[4];
assign T_1730 = T_1648 & T_1729;
assign T_1736 = T_1654 & T_1729;
assign T_1740 = T_1658 & T_1729;
assign T_1746 = T_1664 & T_1729;
assign T_1749 = T_1628[5];
assign T_1750 = T_1648 & T_1749;
assign T_1756 = T_1654 & T_1749;
assign T_1760 = T_1658 & T_1749;
assign T_1766 = T_1664 & T_1749;
assign T_1838_0 = 1'h1;
assign T_1838_1 = 1'h1;
assign T_1838_2 = 1'h1;
assign T_1838_3 = 1'h1;
assign T_1838_4 = 1'h1;
assign T_1838_5 = 1'h1;
assign T_1838_6 = 1'h1;
assign T_1838_7 = 1'h1;
assign T_1861_0 = T_1219;
assign T_1861_1 = 32'h0;
assign T_1861_2 = time_0;
assign T_1861_3 = time_1;
assign T_1861_4 = timecmp_0_0;
assign T_1861_5 = timecmp_0_1;
assign T_1861_6 = 32'h0;
assign T_1861_7 = 32'h0;
assign GEN_4 = GEN_47;
assign GEN_41 = 3'h1 == T_1600 ? T_1838_1 : T_1838_0;
assign GEN_42 = 3'h2 == T_1600 ? T_1838_2 : GEN_41;
assign GEN_43 = 3'h3 == T_1600 ? T_1838_3 : GEN_42;
assign GEN_44 = 3'h4 == T_1600 ? T_1838_4 : GEN_43;
assign GEN_45 = 3'h5 == T_1600 ? T_1838_5 : GEN_44;
assign GEN_46 = 3'h6 == T_1600 ? T_1838_6 : GEN_45;
assign GEN_47 = 3'h7 == T_1600 ? T_1838_7 : GEN_46;
assign GEN_5 = GEN_54;
assign GEN_48 = 3'h1 == T_1600 ? T_1861_1 : T_1861_0;
assign GEN_49 = 3'h2 == T_1600 ? T_1861_2 : GEN_48;
assign GEN_50 = 3'h3 == T_1600 ? T_1861_3 : GEN_49;
assign GEN_51 = 3'h4 == T_1600 ? T_1861_4 : GEN_50;
assign GEN_52 = 3'h5 == T_1600 ? T_1861_5 : GEN_51;
assign GEN_53 = 3'h6 == T_1600 ? T_1861_6 : GEN_52;
assign GEN_54 = 3'h7 == T_1600 ? T_1861_7 : GEN_53;
assign T_1874 = GEN_4 ? GEN_5 : 32'h0;
assign T_1875 = T_979_bits_extra[9:8];
assign T_1877 = T_979_bits_extra[7:3];
assign T_1878 = T_979_bits_extra[2:0];
assign T_1889_opcode = 3'h0;
assign T_1889_param = 2'h0;
assign T_1889_size = T_1878;
assign T_1889_source = T_1877;
assign T_1889_sink = 1'h0;
assign T_1889_addr_lo = T_1875;
assign T_1889_data = 32'h0;
assign T_1889_error = 1'h0;
always @(posedge clock or posedge reset) begin
if (reset) begin
time_0 <= 32'h0;
end else begin
time_0 <= GEN_10[31:0];
end
end
always @(posedge clock or posedge reset) begin
if (reset) begin
time_1 <= 32'h0;
end else begin
if (T_1320) begin
time_1 <= T_1015_bits_data;
end else begin
if (io_rtcTick) begin
time_1 <= T_909;
end
end
end
end
always @(posedge clock or posedge reset) begin
if (reset) begin
timecmp_0_0 <= 32'hFFFF_FFFF;
end
else if (T_1360) begin
timecmp_0_0 <= T_1015_bits_data;
end
end
always @(posedge clock or posedge reset) begin
if (reset) begin
timecmp_0_1 <= 32'hFFFF_FFFF;
end
else if (T_1240) begin
timecmp_0_1 <= T_1015_bits_data;
end
end
always @(posedge clock or posedge reset) begin
if (reset) begin
ipi_0 <= 1'h0;
end else begin
ipi_0 <= GEN_8[0];
end
end
endmodule |
module sirv_wdog(
input clock,
input reset,
input io_regs_cfg_write_valid,
input [31:0] io_regs_cfg_write_bits,
output [31:0] io_regs_cfg_read,
input io_regs_countLo_write_valid,
input [31:0] io_regs_countLo_write_bits,
output [31:0] io_regs_countLo_read,
input io_regs_countHi_write_valid,
input [31:0] io_regs_countHi_write_bits,
output [31:0] io_regs_countHi_read,
input io_regs_s_write_valid,
input [15:0] io_regs_s_write_bits,
output [15:0] io_regs_s_read,
input io_regs_cmp_0_write_valid,
input [15:0] io_regs_cmp_0_write_bits,
output [15:0] io_regs_cmp_0_read,
input io_regs_feed_write_valid,
input [31:0] io_regs_feed_write_bits,
output [31:0] io_regs_feed_read,
input io_regs_key_write_valid,
input [31:0] io_regs_key_write_bits,
output [31:0] io_regs_key_read,
output io_ip_0,
input io_corerst,
output io_rst
);
wire [3:0] T_138;
wire T_139;
wire T_140;
wire T_141;
wire T_142;
wire T_143;
wire T_145;
wire T_147;
wire T_148;
wire T_149;
wire AsyncResetRegVec_2_1_clock;
wire AsyncResetRegVec_2_1_reset;
wire AsyncResetRegVec_2_1_io_d;
wire AsyncResetRegVec_2_1_io_q;
wire AsyncResetRegVec_2_1_io_en;
wire unlocked;
wire T_150;
reg [3:0] scale;
reg [31:0] GEN_10;
wire [3:0] GEN_0;
wire T_152;
reg [15:0] cmp_0;
reg [31:0] GEN_11;
wire [15:0] GEN_1;
reg T_154;
reg [31:0] GEN_12;
reg T_155;
reg [31:0] GEN_13;
wire T_156;
wire AsyncResetRegVec_3_1_clock;
wire AsyncResetRegVec_3_1_reset;
wire AsyncResetRegVec_3_1_io_d;
wire AsyncResetRegVec_3_1_io_q;
wire AsyncResetRegVec_3_1_io_en;
wire countAlways;
wire T_158;
wire AsyncResetRegVec_4_1_clock;
wire AsyncResetRegVec_4_1_reset;
wire AsyncResetRegVec_4_1_io_d;
wire AsyncResetRegVec_4_1_io_q;
wire AsyncResetRegVec_4_1_io_en;
wire countAwake;
wire T_161;
wire T_162;
wire countEn;
reg [4:0] T_164;
reg [31:0] GEN_14;
wire [4:0] GEN_9;
wire [5:0] T_165;
reg [25:0] T_167;
reg [31:0] GEN_15;
wire T_168;
wire [26:0] T_170;
wire [26:0] GEN_2;
wire [30:0] T_171;
wire T_172;
wire [32:0] T_174;
wire [27:0] T_175;
wire [32:0] GEN_3;
wire [27:0] GEN_4;
wire [30:0] T_176;
wire [15:0] s;
wire elapsed_0;
wire T_183;
wire T_185;
wire feed;
wire T_186;
reg zerocmp;
reg [31:0] GEN_16;
wire GEN_5;
wire T_189;
wire countReset;
wire [32:0] GEN_6;
wire [27:0] GEN_7;
wire T_192;
wire T_193;
wire T_195;
reg ip;
reg [31:0] GEN_17;
wire GEN_8;
wire T_209;
wire AsyncResetRegVec_5_1_clock;
wire AsyncResetRegVec_5_1_reset;
wire AsyncResetRegVec_5_1_io_d;
wire AsyncResetRegVec_5_1_io_q;
wire AsyncResetRegVec_5_1_io_en;
wire rsten;
wire [4:0] T_214;
wire [8:0] T_215;
wire [2:0] T_217;
wire [11:0] T_218;
wire [2:0] T_219;
wire [3:0] T_220;
wire [4:0] T_222;
wire [12:0] T_223;
wire [16:0] T_224;
wire [28:0] T_225;
wire T_230_0;
wire T_234;
wire AsyncResetRegVec_6_1_clock;
wire AsyncResetRegVec_6_1_reset;
wire AsyncResetRegVec_6_1_io_d;
wire AsyncResetRegVec_6_1_io_q;
wire AsyncResetRegVec_6_1_io_en;
sirv_AsyncResetRegVec AsyncResetRegVec_2_1 (
.clock(AsyncResetRegVec_2_1_clock),
.reset(AsyncResetRegVec_2_1_reset),
.io_d(AsyncResetRegVec_2_1_io_d),
.io_q(AsyncResetRegVec_2_1_io_q),
.io_en(AsyncResetRegVec_2_1_io_en)
);
sirv_AsyncResetRegVec AsyncResetRegVec_3_1 (
.clock(AsyncResetRegVec_3_1_clock),
.reset(AsyncResetRegVec_3_1_reset),
.io_d(AsyncResetRegVec_3_1_io_d),
.io_q(AsyncResetRegVec_3_1_io_q),
.io_en(AsyncResetRegVec_3_1_io_en)
);
sirv_AsyncResetRegVec AsyncResetRegVec_4_1 (
.clock(AsyncResetRegVec_4_1_clock),
.reset(AsyncResetRegVec_4_1_reset),
.io_d(AsyncResetRegVec_4_1_io_d),
.io_q(AsyncResetRegVec_4_1_io_q),
.io_en(AsyncResetRegVec_4_1_io_en)
);
sirv_AsyncResetRegVec AsyncResetRegVec_5_1 (
.clock(AsyncResetRegVec_5_1_clock),
.reset(AsyncResetRegVec_5_1_reset),
.io_d(AsyncResetRegVec_5_1_io_d),
.io_q(AsyncResetRegVec_5_1_io_q),
.io_en(AsyncResetRegVec_5_1_io_en)
);
sirv_AsyncResetRegVec AsyncResetRegVec_6_1 (
.clock(AsyncResetRegVec_6_1_clock),
.reset(AsyncResetRegVec_6_1_reset),
.io_d(AsyncResetRegVec_6_1_io_d),
.io_q(AsyncResetRegVec_6_1_io_q),
.io_en(AsyncResetRegVec_6_1_io_en)
);
assign io_regs_cfg_read = {{3'd0}, T_225};
assign io_regs_countLo_read = {{1'd0}, T_171};
assign io_regs_countHi_read = 32'h0;
assign io_regs_s_read = s;
assign io_regs_cmp_0_read = cmp_0;
assign io_regs_feed_read = 32'h0;
assign io_regs_key_read = {{31'd0}, unlocked};
assign io_ip_0 = T_230_0;
assign io_rst = AsyncResetRegVec_6_1_io_q;
assign T_138 = io_regs_cfg_write_bits[3:0];
assign T_139 = io_regs_feed_write_valid | io_regs_cmp_0_write_valid;
assign T_140 = T_139 | io_regs_s_write_valid;
assign T_141 = T_140 | io_regs_countHi_write_valid;
assign T_142 = T_141 | io_regs_countLo_write_valid;
assign T_143 = T_142 | io_regs_cfg_write_valid;
assign T_145 = io_regs_key_write_bits == 32'h51f15e;
assign T_147 = T_143 == 1'h0;
assign T_148 = T_145 & T_147;
assign T_149 = io_regs_key_write_valid | T_143;
assign AsyncResetRegVec_2_1_clock = clock;
assign AsyncResetRegVec_2_1_reset = reset;
assign AsyncResetRegVec_2_1_io_d = T_148;
assign AsyncResetRegVec_2_1_io_en = T_149;
assign unlocked = AsyncResetRegVec_2_1_io_q;
assign T_150 = io_regs_cfg_write_valid & unlocked;
assign GEN_0 = T_150 ? T_138 : scale;
assign T_152 = io_regs_cmp_0_write_valid & unlocked;
assign GEN_1 = T_152 ? io_regs_cmp_0_write_bits : cmp_0;
assign T_156 = io_regs_cfg_write_bits[12];
assign AsyncResetRegVec_3_1_clock = clock;
assign AsyncResetRegVec_3_1_reset = reset;
assign AsyncResetRegVec_3_1_io_d = T_156;
assign AsyncResetRegVec_3_1_io_en = T_150;
assign countAlways = AsyncResetRegVec_3_1_io_q;
assign T_158 = io_regs_cfg_write_bits[13];
assign AsyncResetRegVec_4_1_clock = clock;
assign AsyncResetRegVec_4_1_reset = reset;
assign AsyncResetRegVec_4_1_io_d = T_158;
assign AsyncResetRegVec_4_1_io_en = T_150;
assign countAwake = AsyncResetRegVec_4_1_io_q;
assign T_161 = T_155 == 1'h0;
assign T_162 = countAwake & T_161;
assign countEn = countAlways | T_162;
assign GEN_9 = {{4'd0}, countEn};
assign T_165 = T_164 + GEN_9;
assign T_168 = T_165[5];
assign T_170 = T_167 + 26'h1;
assign GEN_2 = T_168 ? T_170 : {{1'd0}, T_167};
assign T_171 = {T_167,T_164};
assign T_172 = io_regs_countLo_write_valid & unlocked;
assign T_174 = {1'h0,io_regs_countLo_write_bits};
assign T_175 = T_174[32:5];
assign GEN_3 = T_172 ? T_174 : {{27'd0}, T_165};
assign GEN_4 = T_172 ? T_175 : {{1'd0}, GEN_2};
assign T_176 = T_171 >> scale;
assign s = T_176[15:0];
assign elapsed_0 = s >= cmp_0;
assign T_183 = unlocked & io_regs_feed_write_valid;
assign T_185 = io_regs_feed_write_bits == 32'hd09f00d;
assign feed = T_183 & T_185;
assign T_186 = io_regs_cfg_write_bits[9];
assign GEN_5 = T_150 ? T_186 : zerocmp;
assign T_189 = zerocmp & elapsed_0;
assign countReset = feed | T_189;
assign GEN_6 = countReset ? 33'h0 : GEN_3;
assign GEN_7 = countReset ? 28'h0 : GEN_4;
assign T_192 = io_regs_cfg_write_bits[28];
assign T_193 = T_192 | elapsed_0;
assign T_195 = T_150 | elapsed_0;
assign GEN_8 = T_195 ? T_193 : ip;
assign T_209 = io_regs_cfg_write_bits[8];
assign AsyncResetRegVec_5_1_clock = clock;
assign AsyncResetRegVec_5_1_reset = reset;
assign AsyncResetRegVec_5_1_io_d = T_209;
assign AsyncResetRegVec_5_1_io_en = T_150;
assign rsten = AsyncResetRegVec_5_1_io_q;
assign T_214 = {rsten,4'h0};
assign T_215 = {T_214,scale};
assign T_217 = {2'h0,zerocmp};
assign T_218 = {T_217,T_215};
assign T_219 = {2'h0,countAwake};
assign T_220 = {T_219,countAlways};
assign T_222 = {ip,4'h0};
assign T_223 = {T_222,8'h0};
assign T_224 = {T_223,T_220};
assign T_225 = {T_224,T_218};
assign T_230_0 = ip;
assign T_234 = rsten & elapsed_0;
assign AsyncResetRegVec_6_1_clock = clock;
assign AsyncResetRegVec_6_1_reset = reset;
assign AsyncResetRegVec_6_1_io_d = 1'h1;
assign AsyncResetRegVec_6_1_io_en = T_234;
`ifdef RANDOMIZE
integer initvar;
initial begin
`ifndef verilator
#0.002 begin end
`endif
`ifdef RANDOMIZE_REG_INIT
GEN_10 = {1{$random}};
scale = GEN_10[3:0];
`endif
`ifdef RANDOMIZE_REG_INIT
GEN_11 = {1{$random}};
cmp_0 = GEN_11[15:0];
`endif
`ifdef RANDOMIZE_REG_INIT
GEN_12 = {1{$random}};
T_154 = GEN_12[0:0];
`endif
`ifdef RANDOMIZE_REG_INIT
GEN_13 = {1{$random}};
T_155 = GEN_13[0:0];
`endif
`ifdef RANDOMIZE_REG_INIT
GEN_14 = {1{$random}};
T_164 = GEN_14[4:0];
`endif
`ifdef RANDOMIZE_REG_INIT
GEN_15 = {1{$random}};
T_167 = GEN_15[25:0];
`endif
`ifdef RANDOMIZE_REG_INIT
GEN_16 = {1{$random}};
zerocmp = GEN_16[0:0];
`endif
`ifdef RANDOMIZE_REG_INIT
GEN_17 = {1{$random}};
ip = GEN_17[0:0];
`endif
end
`endif
always @(posedge clock or posedge reset) begin
if(reset) begin
scale <= 4'b0;
cmp_0 <= 16'hFFFF;
T_154 <= 1'b0;
T_155 <= 1'b0;
T_164 <= 5'b0;
T_167 <= 26'b0;
zerocmp <= 1'b0;
ip <= 1'b0;
end
else begin
if (T_150) begin
scale <= T_138;
end
if (T_152) begin
cmp_0 <= io_regs_cmp_0_write_bits;
end
T_154 <= io_corerst;
T_155 <= T_154;
T_164 <= GEN_6[4:0];
T_167 <= GEN_7[25:0];
if (T_150) begin
zerocmp <= T_186;
end
if (T_195) begin
ip <= T_193;
end
end
end
endmodule |
module e203_soc_top(
// This clock should comes from the crystal pad generated high speed clock (16MHz)
input hfextclk,
output hfxoscen,// The signal to enable the crystal pad generated clock
// This clock should comes from the crystal pad generated low speed clock (32.768KHz)
input lfextclk,
output lfxoscen,// The signal to enable the crystal pad generated clock
// The JTAG TCK is input, need to be pull-up
input io_pads_jtag_TCK_i_ival,
// The JTAG TMS is input, need to be pull-up
input io_pads_jtag_TMS_i_ival,
// The JTAG TDI is input, need to be pull-up
input io_pads_jtag_TDI_i_ival,
// The JTAG TDO is output have enable
output io_pads_jtag_TDO_o_oval,
output io_pads_jtag_TDO_o_oe,
// The GPIO are all bidir pad have enables
input io_pads_gpio_0_i_ival,
output io_pads_gpio_0_o_oval,
output io_pads_gpio_0_o_oe,
output io_pads_gpio_0_o_ie,
output io_pads_gpio_0_o_pue,
output io_pads_gpio_0_o_ds,
input io_pads_gpio_1_i_ival,
output io_pads_gpio_1_o_oval,
output io_pads_gpio_1_o_oe,
output io_pads_gpio_1_o_ie,
output io_pads_gpio_1_o_pue,
output io_pads_gpio_1_o_ds,
input io_pads_gpio_2_i_ival,
output io_pads_gpio_2_o_oval,
output io_pads_gpio_2_o_oe,
output io_pads_gpio_2_o_ie,
output io_pads_gpio_2_o_pue,
output io_pads_gpio_2_o_ds,
input io_pads_gpio_3_i_ival,
output io_pads_gpio_3_o_oval,
output io_pads_gpio_3_o_oe,
output io_pads_gpio_3_o_ie,
output io_pads_gpio_3_o_pue,
output io_pads_gpio_3_o_ds,
input io_pads_gpio_4_i_ival,
output io_pads_gpio_4_o_oval,
output io_pads_gpio_4_o_oe,
output io_pads_gpio_4_o_ie,
output io_pads_gpio_4_o_pue,
output io_pads_gpio_4_o_ds,
input io_pads_gpio_5_i_ival,
output io_pads_gpio_5_o_oval,
output io_pads_gpio_5_o_oe,
output io_pads_gpio_5_o_ie,
output io_pads_gpio_5_o_pue,
output io_pads_gpio_5_o_ds,
input io_pads_gpio_6_i_ival,
output io_pads_gpio_6_o_oval,
output io_pads_gpio_6_o_oe,
output io_pads_gpio_6_o_ie,
output io_pads_gpio_6_o_pue,
output io_pads_gpio_6_o_ds,
input io_pads_gpio_7_i_ival,
output io_pads_gpio_7_o_oval,
output io_pads_gpio_7_o_oe,
output io_pads_gpio_7_o_ie,
output io_pads_gpio_7_o_pue,
output io_pads_gpio_7_o_ds,
input io_pads_gpio_8_i_ival,
output io_pads_gpio_8_o_oval,
output io_pads_gpio_8_o_oe,
output io_pads_gpio_8_o_ie,
output io_pads_gpio_8_o_pue,
output io_pads_gpio_8_o_ds,
input io_pads_gpio_9_i_ival,
output io_pads_gpio_9_o_oval,
output io_pads_gpio_9_o_oe,
output io_pads_gpio_9_o_ie,
output io_pads_gpio_9_o_pue,
output io_pads_gpio_9_o_ds,
input io_pads_gpio_10_i_ival,
output io_pads_gpio_10_o_oval,
output io_pads_gpio_10_o_oe,
output io_pads_gpio_10_o_ie,
output io_pads_gpio_10_o_pue,
output io_pads_gpio_10_o_ds,
input io_pads_gpio_11_i_ival,
output io_pads_gpio_11_o_oval,
output io_pads_gpio_11_o_oe,
output io_pads_gpio_11_o_ie,
output io_pads_gpio_11_o_pue,
output io_pads_gpio_11_o_ds,
input io_pads_gpio_12_i_ival,
output io_pads_gpio_12_o_oval,
output io_pads_gpio_12_o_oe,
output io_pads_gpio_12_o_ie,
output io_pads_gpio_12_o_pue,
output io_pads_gpio_12_o_ds,
input io_pads_gpio_13_i_ival,
output io_pads_gpio_13_o_oval,
output io_pads_gpio_13_o_oe,
output io_pads_gpio_13_o_ie,
output io_pads_gpio_13_o_pue,
output io_pads_gpio_13_o_ds,
input io_pads_gpio_14_i_ival,
output io_pads_gpio_14_o_oval,
output io_pads_gpio_14_o_oe,
output io_pads_gpio_14_o_ie,
output io_pads_gpio_14_o_pue,
output io_pads_gpio_14_o_ds,
input io_pads_gpio_15_i_ival,
output io_pads_gpio_15_o_oval,
output io_pads_gpio_15_o_oe,
output io_pads_gpio_15_o_ie,
output io_pads_gpio_15_o_pue,
output io_pads_gpio_15_o_ds,
input io_pads_gpio_16_i_ival,
output io_pads_gpio_16_o_oval,
output io_pads_gpio_16_o_oe,
output io_pads_gpio_16_o_ie,
output io_pads_gpio_16_o_pue,
output io_pads_gpio_16_o_ds,
input io_pads_gpio_17_i_ival,
output io_pads_gpio_17_o_oval,
output io_pads_gpio_17_o_oe,
output io_pads_gpio_17_o_ie,
output io_pads_gpio_17_o_pue,
output io_pads_gpio_17_o_ds,
input io_pads_gpio_18_i_ival,
output io_pads_gpio_18_o_oval,
output io_pads_gpio_18_o_oe,
output io_pads_gpio_18_o_ie,
output io_pads_gpio_18_o_pue,
output io_pads_gpio_18_o_ds,
input io_pads_gpio_19_i_ival,
output io_pads_gpio_19_o_oval,
output io_pads_gpio_19_o_oe,
output io_pads_gpio_19_o_ie,
output io_pads_gpio_19_o_pue,
output io_pads_gpio_19_o_ds,
input io_pads_gpio_20_i_ival,
output io_pads_gpio_20_o_oval,
output io_pads_gpio_20_o_oe,
output io_pads_gpio_20_o_ie,
output io_pads_gpio_20_o_pue,
output io_pads_gpio_20_o_ds,
input io_pads_gpio_21_i_ival,
output io_pads_gpio_21_o_oval,
output io_pads_gpio_21_o_oe,
output io_pads_gpio_21_o_ie,
output io_pads_gpio_21_o_pue,
output io_pads_gpio_21_o_ds,
input io_pads_gpio_22_i_ival,
output io_pads_gpio_22_o_oval,
output io_pads_gpio_22_o_oe,
output io_pads_gpio_22_o_ie,
output io_pads_gpio_22_o_pue,
output io_pads_gpio_22_o_ds,
input io_pads_gpio_23_i_ival,
output io_pads_gpio_23_o_oval,
output io_pads_gpio_23_o_oe,
output io_pads_gpio_23_o_ie,
output io_pads_gpio_23_o_pue,
output io_pads_gpio_23_o_ds,
input io_pads_gpio_24_i_ival,
output io_pads_gpio_24_o_oval,
output io_pads_gpio_24_o_oe,
output io_pads_gpio_24_o_ie,
output io_pads_gpio_24_o_pue,
output io_pads_gpio_24_o_ds,
input io_pads_gpio_25_i_ival,
output io_pads_gpio_25_o_oval,
output io_pads_gpio_25_o_oe,
output io_pads_gpio_25_o_ie,
output io_pads_gpio_25_o_pue,
output io_pads_gpio_25_o_ds,
input io_pads_gpio_26_i_ival,
output io_pads_gpio_26_o_oval,
output io_pads_gpio_26_o_oe,
output io_pads_gpio_26_o_ie,
output io_pads_gpio_26_o_pue,
output io_pads_gpio_26_o_ds,
input io_pads_gpio_27_i_ival,
output io_pads_gpio_27_o_oval,
output io_pads_gpio_27_o_oe,
output io_pads_gpio_27_o_ie,
output io_pads_gpio_27_o_pue,
output io_pads_gpio_27_o_ds,
input io_pads_gpio_28_i_ival,
output io_pads_gpio_28_o_oval,
output io_pads_gpio_28_o_oe,
output io_pads_gpio_28_o_ie,
output io_pads_gpio_28_o_pue,
output io_pads_gpio_28_o_ds,
input io_pads_gpio_29_i_ival,
output io_pads_gpio_29_o_oval,
output io_pads_gpio_29_o_oe,
output io_pads_gpio_29_o_ie,
output io_pads_gpio_29_o_pue,
output io_pads_gpio_29_o_ds,
input io_pads_gpio_30_i_ival,
output io_pads_gpio_30_o_oval,
output io_pads_gpio_30_o_oe,
output io_pads_gpio_30_o_ie,
output io_pads_gpio_30_o_pue,
output io_pads_gpio_30_o_ds,
input io_pads_gpio_31_i_ival,
output io_pads_gpio_31_o_oval,
output io_pads_gpio_31_o_oe,
output io_pads_gpio_31_o_ie,
output io_pads_gpio_31_o_pue,
output io_pads_gpio_31_o_ds,
//QSPI SCK and CS is output without enable
output io_pads_qspi_sck_o_oval,
output io_pads_qspi_cs_0_o_oval,
//QSPI DQ is bidir I/O with enable, and need pull-up enable
input io_pads_qspi_dq_0_i_ival,
output io_pads_qspi_dq_0_o_oval,
output io_pads_qspi_dq_0_o_oe,
output io_pads_qspi_dq_0_o_ie,
output io_pads_qspi_dq_0_o_pue,
output io_pads_qspi_dq_0_o_ds,
input io_pads_qspi_dq_1_i_ival,
output io_pads_qspi_dq_1_o_oval,
output io_pads_qspi_dq_1_o_oe,
output io_pads_qspi_dq_1_o_ie,
output io_pads_qspi_dq_1_o_pue,
output io_pads_qspi_dq_1_o_ds,
input io_pads_qspi_dq_2_i_ival,
output io_pads_qspi_dq_2_o_oval,
output io_pads_qspi_dq_2_o_oe,
output io_pads_qspi_dq_2_o_ie,
output io_pads_qspi_dq_2_o_pue,
output io_pads_qspi_dq_2_o_ds,
input io_pads_qspi_dq_3_i_ival,
output io_pads_qspi_dq_3_o_oval,
output io_pads_qspi_dq_3_o_oe,
output io_pads_qspi_dq_3_o_ie,
output io_pads_qspi_dq_3_o_pue,
output io_pads_qspi_dq_3_o_ds,
// Erst is input need to be pull-up by default
input io_pads_aon_erst_n_i_ival,
// dbgmode are inputs need to be pull-up by default
input io_pads_dbgmode0_n_i_ival,
input io_pads_dbgmode1_n_i_ival,
input io_pads_dbgmode2_n_i_ival,
// BootRom is input need to be pull-up by default
input io_pads_bootrom_n_i_ival,
// dwakeup is input need to be pull-up by default
input io_pads_aon_pmu_dwakeup_n_i_ival,
// PMU output is just output without enable
output io_pads_aon_pmu_padrst_o_oval,
output io_pads_aon_pmu_vddpaden_o_oval
);
wire sysper_icb_cmd_valid;
wire sysper_icb_cmd_ready;
wire sysfio_icb_cmd_valid;
wire sysfio_icb_cmd_ready;
wire sysmem_icb_cmd_valid;
wire sysmem_icb_cmd_ready;
e203_subsys_top u_e203_subsys_top(
.core_mhartid (1'b0),
`ifdef E203_HAS_ITCM_EXTITF //{
.ext2itcm_icb_cmd_valid (1'b0),
.ext2itcm_icb_cmd_ready (),
.ext2itcm_icb_cmd_addr (`E203_ITCM_ADDR_WIDTH'b0 ),
.ext2itcm_icb_cmd_read (1'b0 ),
.ext2itcm_icb_cmd_wdata (32'b0),
.ext2itcm_icb_cmd_wmask (4'b0),
.ext2itcm_icb_rsp_valid (),
.ext2itcm_icb_rsp_ready (1'b0),
.ext2itcm_icb_rsp_err (),
.ext2itcm_icb_rsp_rdata (),
`endif//}
`ifdef E203_HAS_DTCM_EXTITF //{
.ext2dtcm_icb_cmd_valid (1'b0),
.ext2dtcm_icb_cmd_ready (),
.ext2dtcm_icb_cmd_addr (`E203_DTCM_ADDR_WIDTH'b0 ),
.ext2dtcm_icb_cmd_read (1'b0 ),
.ext2dtcm_icb_cmd_wdata (32'b0),
.ext2dtcm_icb_cmd_wmask (4'b0),
.ext2dtcm_icb_rsp_valid (),
.ext2dtcm_icb_rsp_ready (1'b0),
.ext2dtcm_icb_rsp_err (),
.ext2dtcm_icb_rsp_rdata (),
`endif//}
.sysper_icb_cmd_valid (sysper_icb_cmd_valid),
.sysper_icb_cmd_ready (sysper_icb_cmd_ready),
.sysper_icb_cmd_read (),
.sysper_icb_cmd_addr (),
.sysper_icb_cmd_wdata (),
.sysper_icb_cmd_wmask (),
.sysper_icb_rsp_valid (sysper_icb_cmd_valid),
.sysper_icb_rsp_ready (sysper_icb_cmd_ready),
.sysper_icb_rsp_err (1'b0 ),
.sysper_icb_rsp_rdata (32'b0),
.sysfio_icb_cmd_valid(sysfio_icb_cmd_valid),
.sysfio_icb_cmd_ready(sysfio_icb_cmd_ready),
.sysfio_icb_cmd_read (),
.sysfio_icb_cmd_addr (),
.sysfio_icb_cmd_wdata(),
.sysfio_icb_cmd_wmask(),
.sysfio_icb_rsp_valid(sysfio_icb_cmd_valid),
.sysfio_icb_rsp_ready(sysfio_icb_cmd_ready),
.sysfio_icb_rsp_err (1'b0 ),
.sysfio_icb_rsp_rdata(32'b0),
.sysmem_icb_cmd_valid(sysmem_icb_cmd_valid),
.sysmem_icb_cmd_ready(sysmem_icb_cmd_ready),
.sysmem_icb_cmd_read (),
.sysmem_icb_cmd_addr (),
.sysmem_icb_cmd_wdata(),
.sysmem_icb_cmd_wmask(),
.sysmem_icb_rsp_valid(sysmem_icb_cmd_valid),
.sysmem_icb_rsp_ready(sysmem_icb_cmd_ready),
.sysmem_icb_rsp_err (1'b0 ),
.sysmem_icb_rsp_rdata(32'b0),
.io_pads_jtag_TCK_i_ival (io_pads_jtag_TCK_i_ival ),
.io_pads_jtag_TCK_o_oval (),
.io_pads_jtag_TCK_o_oe (),
.io_pads_jtag_TCK_o_ie (),
.io_pads_jtag_TCK_o_pue (),
.io_pads_jtag_TCK_o_ds (),
.io_pads_jtag_TMS_i_ival (io_pads_jtag_TMS_i_ival ),
.io_pads_jtag_TMS_o_oval (),
.io_pads_jtag_TMS_o_oe (),
.io_pads_jtag_TMS_o_ie (),
.io_pads_jtag_TMS_o_pue (),
.io_pads_jtag_TMS_o_ds (),
.io_pads_jtag_TDI_i_ival (io_pads_jtag_TDI_i_ival ),
.io_pads_jtag_TDI_o_oval (),
.io_pads_jtag_TDI_o_oe (),
.io_pads_jtag_TDI_o_ie (),
.io_pads_jtag_TDI_o_pue (),
.io_pads_jtag_TDI_o_ds (),
.io_pads_jtag_TDO_i_ival (1'b1 ),
.io_pads_jtag_TDO_o_oval (io_pads_jtag_TDO_o_oval ),
.io_pads_jtag_TDO_o_oe (io_pads_jtag_TDO_o_oe ),
.io_pads_jtag_TDO_o_ie (),
.io_pads_jtag_TDO_o_pue (),
.io_pads_jtag_TDO_o_ds (),
.io_pads_jtag_TRST_n_i_ival (1'b1 ),
.io_pads_jtag_TRST_n_o_oval (),
.io_pads_jtag_TRST_n_o_oe (),
.io_pads_jtag_TRST_n_o_ie (),
.io_pads_jtag_TRST_n_o_pue (),
.io_pads_jtag_TRST_n_o_ds (),
.test_mode(1'b0),
.test_iso_override(1'b0),
.io_pads_gpio_0_i_ival (io_pads_gpio_0_i_ival & io_pads_gpio_0_o_ie),
.io_pads_gpio_0_o_oval (io_pads_gpio_0_o_oval),
.io_pads_gpio_0_o_oe (io_pads_gpio_0_o_oe),
.io_pads_gpio_0_o_ie (io_pads_gpio_0_o_ie),
.io_pads_gpio_0_o_pue (io_pads_gpio_0_o_pue),
.io_pads_gpio_0_o_ds (io_pads_gpio_0_o_ds),
.io_pads_gpio_1_i_ival (io_pads_gpio_1_i_ival & io_pads_gpio_1_o_ie),
.io_pads_gpio_1_o_oval (io_pads_gpio_1_o_oval),
.io_pads_gpio_1_o_oe (io_pads_gpio_1_o_oe),
.io_pads_gpio_1_o_ie (io_pads_gpio_1_o_ie),
.io_pads_gpio_1_o_pue (io_pads_gpio_1_o_pue),
.io_pads_gpio_1_o_ds (io_pads_gpio_1_o_ds),
.io_pads_gpio_2_i_ival (io_pads_gpio_2_i_ival & io_pads_gpio_2_o_ie),
.io_pads_gpio_2_o_oval (io_pads_gpio_2_o_oval),
.io_pads_gpio_2_o_oe (io_pads_gpio_2_o_oe),
.io_pads_gpio_2_o_ie (io_pads_gpio_2_o_ie),
.io_pads_gpio_2_o_pue (io_pads_gpio_2_o_pue),
.io_pads_gpio_2_o_ds (io_pads_gpio_2_o_ds),
.io_pads_gpio_3_i_ival (io_pads_gpio_3_i_ival & io_pads_gpio_3_o_ie),
.io_pads_gpio_3_o_oval (io_pads_gpio_3_o_oval),
.io_pads_gpio_3_o_oe (io_pads_gpio_3_o_oe),
.io_pads_gpio_3_o_ie (io_pads_gpio_3_o_ie),
.io_pads_gpio_3_o_pue (io_pads_gpio_3_o_pue),
.io_pads_gpio_3_o_ds (io_pads_gpio_3_o_ds),
.io_pads_gpio_4_i_ival (io_pads_gpio_4_i_ival & io_pads_gpio_4_o_ie),
.io_pads_gpio_4_o_oval (io_pads_gpio_4_o_oval),
.io_pads_gpio_4_o_oe (io_pads_gpio_4_o_oe),
.io_pads_gpio_4_o_ie (io_pads_gpio_4_o_ie),
.io_pads_gpio_4_o_pue (io_pads_gpio_4_o_pue),
.io_pads_gpio_4_o_ds (io_pads_gpio_4_o_ds),
.io_pads_gpio_5_i_ival (io_pads_gpio_5_i_ival & io_pads_gpio_5_o_ie),
.io_pads_gpio_5_o_oval (io_pads_gpio_5_o_oval),
.io_pads_gpio_5_o_oe (io_pads_gpio_5_o_oe),
.io_pads_gpio_5_o_ie (io_pads_gpio_5_o_ie),
.io_pads_gpio_5_o_pue (io_pads_gpio_5_o_pue),
.io_pads_gpio_5_o_ds (io_pads_gpio_5_o_ds),
.io_pads_gpio_6_i_ival (io_pads_gpio_6_i_ival & io_pads_gpio_6_o_ie),
.io_pads_gpio_6_o_oval (io_pads_gpio_6_o_oval),
.io_pads_gpio_6_o_oe (io_pads_gpio_6_o_oe),
.io_pads_gpio_6_o_ie (io_pads_gpio_6_o_ie),
.io_pads_gpio_6_o_pue (io_pads_gpio_6_o_pue),
.io_pads_gpio_6_o_ds (io_pads_gpio_6_o_ds),
.io_pads_gpio_7_i_ival (io_pads_gpio_7_i_ival & io_pads_gpio_7_o_ie),
.io_pads_gpio_7_o_oval (io_pads_gpio_7_o_oval),
.io_pads_gpio_7_o_oe (io_pads_gpio_7_o_oe),
.io_pads_gpio_7_o_ie (io_pads_gpio_7_o_ie),
.io_pads_gpio_7_o_pue (io_pads_gpio_7_o_pue),
.io_pads_gpio_7_o_ds (io_pads_gpio_7_o_ds),
.io_pads_gpio_8_i_ival (io_pads_gpio_8_i_ival & io_pads_gpio_8_o_ie),
.io_pads_gpio_8_o_oval (io_pads_gpio_8_o_oval),
.io_pads_gpio_8_o_oe (io_pads_gpio_8_o_oe),
.io_pads_gpio_8_o_ie (io_pads_gpio_8_o_ie),
.io_pads_gpio_8_o_pue (io_pads_gpio_8_o_pue),
.io_pads_gpio_8_o_ds (io_pads_gpio_8_o_ds),
.io_pads_gpio_9_i_ival (io_pads_gpio_9_i_ival & io_pads_gpio_9_o_ie),
.io_pads_gpio_9_o_oval (io_pads_gpio_9_o_oval),
.io_pads_gpio_9_o_oe (io_pads_gpio_9_o_oe),
.io_pads_gpio_9_o_ie (io_pads_gpio_9_o_ie),
.io_pads_gpio_9_o_pue (io_pads_gpio_9_o_pue),
.io_pads_gpio_9_o_ds (io_pads_gpio_9_o_ds),
.io_pads_gpio_10_i_ival (io_pads_gpio_10_i_ival & io_pads_gpio_10_o_ie),
.io_pads_gpio_10_o_oval (io_pads_gpio_10_o_oval),
.io_pads_gpio_10_o_oe (io_pads_gpio_10_o_oe),
.io_pads_gpio_10_o_ie (io_pads_gpio_10_o_ie),
.io_pads_gpio_10_o_pue (io_pads_gpio_10_o_pue),
.io_pads_gpio_10_o_ds (io_pads_gpio_10_o_ds),
.io_pads_gpio_11_i_ival (io_pads_gpio_11_i_ival & io_pads_gpio_11_o_ie),
.io_pads_gpio_11_o_oval (io_pads_gpio_11_o_oval),
.io_pads_gpio_11_o_oe (io_pads_gpio_11_o_oe),
.io_pads_gpio_11_o_ie (io_pads_gpio_11_o_ie),
.io_pads_gpio_11_o_pue (io_pads_gpio_11_o_pue),
.io_pads_gpio_11_o_ds (io_pads_gpio_11_o_ds),
.io_pads_gpio_12_i_ival (io_pads_gpio_12_i_ival & io_pads_gpio_12_o_ie),
.io_pads_gpio_12_o_oval (io_pads_gpio_12_o_oval),
.io_pads_gpio_12_o_oe (io_pads_gpio_12_o_oe),
.io_pads_gpio_12_o_ie (io_pads_gpio_12_o_ie),
.io_pads_gpio_12_o_pue (io_pads_gpio_12_o_pue),
.io_pads_gpio_12_o_ds (io_pads_gpio_12_o_ds),
.io_pads_gpio_13_i_ival (io_pads_gpio_13_i_ival & io_pads_gpio_13_o_ie),
.io_pads_gpio_13_o_oval (io_pads_gpio_13_o_oval),
.io_pads_gpio_13_o_oe (io_pads_gpio_13_o_oe),
.io_pads_gpio_13_o_ie (io_pads_gpio_13_o_ie),
.io_pads_gpio_13_o_pue (io_pads_gpio_13_o_pue),
.io_pads_gpio_13_o_ds (io_pads_gpio_13_o_ds),
.io_pads_gpio_14_i_ival (io_pads_gpio_14_i_ival & io_pads_gpio_14_o_ie),
.io_pads_gpio_14_o_oval (io_pads_gpio_14_o_oval),
.io_pads_gpio_14_o_oe (io_pads_gpio_14_o_oe),
.io_pads_gpio_14_o_ie (io_pads_gpio_14_o_ie),
.io_pads_gpio_14_o_pue (io_pads_gpio_14_o_pue),
.io_pads_gpio_14_o_ds (io_pads_gpio_14_o_ds),
.io_pads_gpio_15_i_ival (io_pads_gpio_15_i_ival & io_pads_gpio_15_o_ie),
.io_pads_gpio_15_o_oval (io_pads_gpio_15_o_oval),
.io_pads_gpio_15_o_oe (io_pads_gpio_15_o_oe),
.io_pads_gpio_15_o_ie (io_pads_gpio_15_o_ie),
.io_pads_gpio_15_o_pue (io_pads_gpio_15_o_pue),
.io_pads_gpio_15_o_ds (io_pads_gpio_15_o_ds),
.io_pads_gpio_16_i_ival (io_pads_gpio_16_i_ival & io_pads_gpio_16_o_ie),
.io_pads_gpio_16_o_oval (io_pads_gpio_16_o_oval),
.io_pads_gpio_16_o_oe (io_pads_gpio_16_o_oe),
.io_pads_gpio_16_o_ie (io_pads_gpio_16_o_ie),
.io_pads_gpio_16_o_pue (io_pads_gpio_16_o_pue),
.io_pads_gpio_16_o_ds (io_pads_gpio_16_o_ds),
.io_pads_gpio_17_i_ival (io_pads_gpio_17_i_ival & io_pads_gpio_17_o_ie),
.io_pads_gpio_17_o_oval (io_pads_gpio_17_o_oval),
.io_pads_gpio_17_o_oe (io_pads_gpio_17_o_oe),
.io_pads_gpio_17_o_ie (io_pads_gpio_17_o_ie),
.io_pads_gpio_17_o_pue (io_pads_gpio_17_o_pue),
.io_pads_gpio_17_o_ds (io_pads_gpio_17_o_ds),
.io_pads_gpio_18_i_ival (io_pads_gpio_18_i_ival & io_pads_gpio_18_o_ie),
.io_pads_gpio_18_o_oval (io_pads_gpio_18_o_oval),
.io_pads_gpio_18_o_oe (io_pads_gpio_18_o_oe),
.io_pads_gpio_18_o_ie (io_pads_gpio_18_o_ie),
.io_pads_gpio_18_o_pue (io_pads_gpio_18_o_pue),
.io_pads_gpio_18_o_ds (io_pads_gpio_18_o_ds),
.io_pads_gpio_19_i_ival (io_pads_gpio_19_i_ival & io_pads_gpio_19_o_ie),
.io_pads_gpio_19_o_oval (io_pads_gpio_19_o_oval),
.io_pads_gpio_19_o_oe (io_pads_gpio_19_o_oe),
.io_pads_gpio_19_o_ie (io_pads_gpio_19_o_ie),
.io_pads_gpio_19_o_pue (io_pads_gpio_19_o_pue),
.io_pads_gpio_19_o_ds (io_pads_gpio_19_o_ds),
.io_pads_gpio_20_i_ival (io_pads_gpio_20_i_ival & io_pads_gpio_20_o_ie),
.io_pads_gpio_20_o_oval (io_pads_gpio_20_o_oval),
.io_pads_gpio_20_o_oe (io_pads_gpio_20_o_oe),
.io_pads_gpio_20_o_ie (io_pads_gpio_20_o_ie),
.io_pads_gpio_20_o_pue (io_pads_gpio_20_o_pue),
.io_pads_gpio_20_o_ds (io_pads_gpio_20_o_ds),
.io_pads_gpio_21_i_ival (io_pads_gpio_21_i_ival & io_pads_gpio_21_o_ie),
.io_pads_gpio_21_o_oval (io_pads_gpio_21_o_oval),
.io_pads_gpio_21_o_oe (io_pads_gpio_21_o_oe),
.io_pads_gpio_21_o_ie (io_pads_gpio_21_o_ie),
.io_pads_gpio_21_o_pue (io_pads_gpio_21_o_pue),
.io_pads_gpio_21_o_ds (io_pads_gpio_21_o_ds),
.io_pads_gpio_22_i_ival (io_pads_gpio_22_i_ival & io_pads_gpio_22_o_ie),
.io_pads_gpio_22_o_oval (io_pads_gpio_22_o_oval),
.io_pads_gpio_22_o_oe (io_pads_gpio_22_o_oe),
.io_pads_gpio_22_o_ie (io_pads_gpio_22_o_ie),
.io_pads_gpio_22_o_pue (io_pads_gpio_22_o_pue),
.io_pads_gpio_22_o_ds (io_pads_gpio_22_o_ds),
.io_pads_gpio_23_i_ival (io_pads_gpio_23_i_ival & io_pads_gpio_23_o_ie),
.io_pads_gpio_23_o_oval (io_pads_gpio_23_o_oval),
.io_pads_gpio_23_o_oe (io_pads_gpio_23_o_oe),
.io_pads_gpio_23_o_ie (io_pads_gpio_23_o_ie),
.io_pads_gpio_23_o_pue (io_pads_gpio_23_o_pue),
.io_pads_gpio_23_o_ds (io_pads_gpio_23_o_ds),
.io_pads_gpio_24_i_ival (io_pads_gpio_24_i_ival & io_pads_gpio_24_o_ie),
.io_pads_gpio_24_o_oval (io_pads_gpio_24_o_oval),
.io_pads_gpio_24_o_oe (io_pads_gpio_24_o_oe),
.io_pads_gpio_24_o_ie (io_pads_gpio_24_o_ie),
.io_pads_gpio_24_o_pue (io_pads_gpio_24_o_pue),
.io_pads_gpio_24_o_ds (io_pads_gpio_24_o_ds),
.io_pads_gpio_25_i_ival (io_pads_gpio_25_i_ival & io_pads_gpio_25_o_ie),
.io_pads_gpio_25_o_oval (io_pads_gpio_25_o_oval),
.io_pads_gpio_25_o_oe (io_pads_gpio_25_o_oe),
.io_pads_gpio_25_o_ie (io_pads_gpio_25_o_ie),
.io_pads_gpio_25_o_pue (io_pads_gpio_25_o_pue),
.io_pads_gpio_25_o_ds (io_pads_gpio_25_o_ds),
.io_pads_gpio_26_i_ival (io_pads_gpio_26_i_ival & io_pads_gpio_26_o_ie),
.io_pads_gpio_26_o_oval (io_pads_gpio_26_o_oval),
.io_pads_gpio_26_o_oe (io_pads_gpio_26_o_oe),
.io_pads_gpio_26_o_ie (io_pads_gpio_26_o_ie),
.io_pads_gpio_26_o_pue (io_pads_gpio_26_o_pue),
.io_pads_gpio_26_o_ds (io_pads_gpio_26_o_ds),
.io_pads_gpio_27_i_ival (io_pads_gpio_27_i_ival & io_pads_gpio_27_o_ie),
.io_pads_gpio_27_o_oval (io_pads_gpio_27_o_oval),
.io_pads_gpio_27_o_oe (io_pads_gpio_27_o_oe),
.io_pads_gpio_27_o_ie (io_pads_gpio_27_o_ie),
.io_pads_gpio_27_o_pue (io_pads_gpio_27_o_pue),
.io_pads_gpio_27_o_ds (io_pads_gpio_27_o_ds),
.io_pads_gpio_28_i_ival (io_pads_gpio_28_i_ival & io_pads_gpio_28_o_ie),
.io_pads_gpio_28_o_oval (io_pads_gpio_28_o_oval),
.io_pads_gpio_28_o_oe (io_pads_gpio_28_o_oe),
.io_pads_gpio_28_o_ie (io_pads_gpio_28_o_ie),
.io_pads_gpio_28_o_pue (io_pads_gpio_28_o_pue),
.io_pads_gpio_28_o_ds (io_pads_gpio_28_o_ds),
.io_pads_gpio_29_i_ival (io_pads_gpio_29_i_ival & io_pads_gpio_29_o_ie),
.io_pads_gpio_29_o_oval (io_pads_gpio_29_o_oval),
.io_pads_gpio_29_o_oe (io_pads_gpio_29_o_oe),
.io_pads_gpio_29_o_ie (io_pads_gpio_29_o_ie),
.io_pads_gpio_29_o_pue (io_pads_gpio_29_o_pue),
.io_pads_gpio_29_o_ds (io_pads_gpio_29_o_ds),
.io_pads_gpio_30_i_ival (io_pads_gpio_30_i_ival & io_pads_gpio_30_o_ie),
.io_pads_gpio_30_o_oval (io_pads_gpio_30_o_oval),
.io_pads_gpio_30_o_oe (io_pads_gpio_30_o_oe),
.io_pads_gpio_30_o_ie (io_pads_gpio_30_o_ie),
.io_pads_gpio_30_o_pue (io_pads_gpio_30_o_pue),
.io_pads_gpio_30_o_ds (io_pads_gpio_30_o_ds),
.io_pads_gpio_31_i_ival (io_pads_gpio_31_i_ival & io_pads_gpio_31_o_ie),
.io_pads_gpio_31_o_oval (io_pads_gpio_31_o_oval),
.io_pads_gpio_31_o_oe (io_pads_gpio_31_o_oe),
.io_pads_gpio_31_o_ie (io_pads_gpio_31_o_ie),
.io_pads_gpio_31_o_pue (io_pads_gpio_31_o_pue),
.io_pads_gpio_31_o_ds (io_pads_gpio_31_o_ds),
.io_pads_qspi_sck_i_ival (1'b1 ),
.io_pads_qspi_sck_o_oval (io_pads_qspi_sck_o_oval ),
.io_pads_qspi_sck_o_oe (),
.io_pads_qspi_sck_o_ie (),
.io_pads_qspi_sck_o_pue (),
.io_pads_qspi_sck_o_ds (),
.io_pads_qspi_dq_0_i_ival (io_pads_qspi_dq_0_i_ival & io_pads_qspi_dq_0_o_ie),
.io_pads_qspi_dq_0_o_oval (io_pads_qspi_dq_0_o_oval),
.io_pads_qspi_dq_0_o_oe (io_pads_qspi_dq_0_o_oe ),
.io_pads_qspi_dq_0_o_ie (io_pads_qspi_dq_0_o_ie ),
.io_pads_qspi_dq_0_o_pue (io_pads_qspi_dq_0_o_pue ),
.io_pads_qspi_dq_0_o_ds (io_pads_qspi_dq_0_o_ds ),
.io_pads_qspi_dq_1_i_ival (io_pads_qspi_dq_1_i_ival & io_pads_qspi_dq_1_o_ie),
.io_pads_qspi_dq_1_o_oval (io_pads_qspi_dq_1_o_oval),
.io_pads_qspi_dq_1_o_oe (io_pads_qspi_dq_1_o_oe ),
.io_pads_qspi_dq_1_o_ie (io_pads_qspi_dq_1_o_ie ),
.io_pads_qspi_dq_1_o_pue (io_pads_qspi_dq_1_o_pue ),
.io_pads_qspi_dq_1_o_ds (io_pads_qspi_dq_1_o_ds ),
.io_pads_qspi_dq_2_i_ival (io_pads_qspi_dq_2_i_ival & io_pads_qspi_dq_2_o_ie),
.io_pads_qspi_dq_2_o_oval (io_pads_qspi_dq_2_o_oval),
.io_pads_qspi_dq_2_o_oe (io_pads_qspi_dq_2_o_oe ),
.io_pads_qspi_dq_2_o_ie (io_pads_qspi_dq_2_o_ie ),
.io_pads_qspi_dq_2_o_pue (io_pads_qspi_dq_2_o_pue ),
.io_pads_qspi_dq_2_o_ds (io_pads_qspi_dq_2_o_ds ),
.io_pads_qspi_dq_3_i_ival (io_pads_qspi_dq_3_i_ival & io_pads_qspi_dq_3_o_ie),
.io_pads_qspi_dq_3_o_oval (io_pads_qspi_dq_3_o_oval),
.io_pads_qspi_dq_3_o_oe (io_pads_qspi_dq_3_o_oe ),
.io_pads_qspi_dq_3_o_ie (io_pads_qspi_dq_3_o_ie ),
.io_pads_qspi_dq_3_o_pue (io_pads_qspi_dq_3_o_pue ),
.io_pads_qspi_dq_3_o_ds (io_pads_qspi_dq_3_o_ds ),
.io_pads_qspi_cs_0_i_ival (1'b1),
.io_pads_qspi_cs_0_o_oval (io_pads_qspi_cs_0_o_oval),
.io_pads_qspi_cs_0_o_oe (),
.io_pads_qspi_cs_0_o_ie (),
.io_pads_qspi_cs_0_o_pue (),
.io_pads_qspi_cs_0_o_ds (),
.hfextclk (hfextclk),
.hfxoscen (hfxoscen),
.lfextclk (lfextclk),
.lfxoscen (lfxoscen),
.io_pads_aon_erst_n_i_ival (io_pads_aon_erst_n_i_ival ),
.io_pads_aon_erst_n_o_oval (),
.io_pads_aon_erst_n_o_oe (),
.io_pads_aon_erst_n_o_ie (),
.io_pads_aon_erst_n_o_pue (),
.io_pads_aon_erst_n_o_ds (),
.io_pads_aon_pmu_dwakeup_n_i_ival (io_pads_aon_pmu_dwakeup_n_i_ival),
.io_pads_aon_pmu_dwakeup_n_o_oval (),
.io_pads_aon_pmu_dwakeup_n_o_oe (),
.io_pads_aon_pmu_dwakeup_n_o_ie (),
.io_pads_aon_pmu_dwakeup_n_o_pue (),
.io_pads_aon_pmu_dwakeup_n_o_ds (),
.io_pads_aon_pmu_vddpaden_i_ival (1'b1 ),
.io_pads_aon_pmu_vddpaden_o_oval (io_pads_aon_pmu_vddpaden_o_oval ),
.io_pads_aon_pmu_vddpaden_o_oe (),
.io_pads_aon_pmu_vddpaden_o_ie (),
.io_pads_aon_pmu_vddpaden_o_pue (),
.io_pads_aon_pmu_vddpaden_o_ds (),
.io_pads_aon_pmu_padrst_i_ival (1'b1 ),
.io_pads_aon_pmu_padrst_o_oval (io_pads_aon_pmu_padrst_o_oval ),
.io_pads_aon_pmu_padrst_o_oe (),
.io_pads_aon_pmu_padrst_o_ie (),
.io_pads_aon_pmu_padrst_o_pue (),
.io_pads_aon_pmu_padrst_o_ds (),
.io_pads_bootrom_n_i_ival (io_pads_bootrom_n_i_ival),
.io_pads_bootrom_n_o_oval (),
.io_pads_bootrom_n_o_oe (),
.io_pads_bootrom_n_o_ie (),
.io_pads_bootrom_n_o_pue (),
.io_pads_bootrom_n_o_ds (),
.io_pads_dbgmode0_n_i_ival (io_pads_dbgmode0_n_i_ival),
.io_pads_dbgmode1_n_i_ival (io_pads_dbgmode1_n_i_ival),
.io_pads_dbgmode2_n_i_ival (io_pads_dbgmode2_n_i_ival)
);
endmodule |
module sirv_DeglitchShiftRegister(
input clock,
input reset,
input io_d,
output io_q
);
reg T_8;
reg [31:0] GEN_0;
reg T_9;
reg [31:0] GEN_1;
reg sync;
reg [31:0] GEN_2;
reg last;
reg [31:0] GEN_3;
wire T_12;
assign io_q = T_12;
assign T_12 = sync & last;
always @(posedge clock) begin// sync reg do not need reset, and the external reset is tied to 1, do not use it
T_8 <= io_d;
T_9 <= T_8;
sync <= T_9;
last <= sync;
end
endmodule |
module sirv_qspi_media_1(
input clock,
input reset,
output io_port_sck,
input io_port_dq_0_i,
output io_port_dq_0_o,
output io_port_dq_0_oe,
input io_port_dq_1_i,
output io_port_dq_1_o,
output io_port_dq_1_oe,
input io_port_dq_2_i,
output io_port_dq_2_o,
output io_port_dq_2_oe,
input io_port_dq_3_i,
output io_port_dq_3_o,
output io_port_dq_3_oe,
output io_port_cs_0,
output io_port_cs_1,
output io_port_cs_2,
output io_port_cs_3,
input [11:0] io_ctrl_sck_div,
input io_ctrl_sck_pol,
input io_ctrl_sck_pha,
input [7:0] io_ctrl_dla_cssck,
input [7:0] io_ctrl_dla_sckcs,
input [7:0] io_ctrl_dla_intercs,
input [7:0] io_ctrl_dla_interxfr,
input [1:0] io_ctrl_cs_id,
input io_ctrl_cs_dflt_0,
input io_ctrl_cs_dflt_1,
input io_ctrl_cs_dflt_2,
input io_ctrl_cs_dflt_3,
output io_link_tx_ready,
input io_link_tx_valid,
input [7:0] io_link_tx_bits,
output io_link_rx_valid,
output [7:0] io_link_rx_bits,
input [7:0] io_link_cnt,
input [1:0] io_link_fmt_proto,
input io_link_fmt_endian,
input io_link_fmt_iodir,
input io_link_cs_set,
input io_link_cs_clear,
input io_link_cs_hold,
output io_link_active
);
wire phy_clock;
wire phy_reset;
wire phy_io_port_sck;
wire phy_io_port_dq_0_i;
wire phy_io_port_dq_0_o;
wire phy_io_port_dq_0_oe;
wire phy_io_port_dq_1_i;
wire phy_io_port_dq_1_o;
wire phy_io_port_dq_1_oe;
wire phy_io_port_dq_2_i;
wire phy_io_port_dq_2_o;
wire phy_io_port_dq_2_oe;
wire phy_io_port_dq_3_i;
wire phy_io_port_dq_3_o;
wire phy_io_port_dq_3_oe;
wire phy_io_port_cs_0;
wire phy_io_port_cs_1;
wire phy_io_port_cs_2;
wire phy_io_port_cs_3;
wire [11:0] phy_io_ctrl_sck_div;
wire phy_io_ctrl_sck_pol;
wire phy_io_ctrl_sck_pha;
wire [1:0] phy_io_ctrl_fmt_proto;
wire phy_io_ctrl_fmt_endian;
wire phy_io_ctrl_fmt_iodir;
wire phy_io_op_ready;
wire phy_io_op_valid;
wire phy_io_op_bits_fn;
wire phy_io_op_bits_stb;
wire [7:0] phy_io_op_bits_cnt;
wire [7:0] phy_io_op_bits_data;
wire phy_io_rx_valid;
wire [7:0] phy_io_rx_bits;
reg [1:0] cs_id;
reg [31:0] GEN_5;
reg cs_dflt_0;
reg [31:0] GEN_68;
reg cs_dflt_1;
reg [31:0] GEN_69;
reg cs_dflt_2;
reg [31:0] GEN_70;
reg cs_dflt_3;
reg [31:0] GEN_71;
reg cs_set;
reg [31:0] GEN_72;
wire [3:0] GEN_66;
wire [3:0] T_162;
wire [1:0] T_163;
wire [1:0] T_164;
wire [3:0] T_165;
wire [3:0] T_166;
wire T_167;
wire T_168;
wire T_169;
wire T_170;
wire cs_active_0;
wire cs_active_1;
wire cs_active_2;
wire cs_active_3;
wire [1:0] T_184;
wire [1:0] T_185;
wire [3:0] T_186;
wire [1:0] T_187;
wire [1:0] T_188;
wire [3:0] T_189;
wire cs_update;
reg clear;
reg [31:0] GEN_73;
reg cs_assert;
reg [31:0] GEN_74;
wire T_193;
wire T_194;
wire cs_deassert;
wire T_195;
wire T_196;
wire continuous;
reg [1:0] state;
reg [31:0] GEN_75;
wire T_200;
wire [1:0] GEN_0;
wire [7:0] GEN_1;
wire [1:0] GEN_2;
wire T_202;
wire T_204;
wire [1:0] GEN_3;
wire GEN_4;
wire GEN_6;
wire GEN_7;
wire [1:0] GEN_8;
wire [7:0] GEN_9;
wire [1:0] GEN_10;
wire GEN_11;
wire GEN_12;
wire GEN_13;
wire GEN_14;
wire T_206;
wire T_207;
wire GEN_15;
wire GEN_16;
wire GEN_17;
wire GEN_18;
wire GEN_19;
wire GEN_20;
wire [7:0] GEN_21;
wire GEN_22;
wire GEN_23;
wire GEN_24;
wire GEN_25;
wire GEN_26;
wire GEN_27;
wire T_212;
wire T_213;
wire [7:0] GEN_28;
wire GEN_29;
wire [1:0] GEN_30;
wire GEN_31;
wire GEN_32;
wire GEN_33;
wire GEN_34;
wire [7:0] GEN_35;
wire [1:0] GEN_36;
wire GEN_37;
wire GEN_38;
wire GEN_39;
wire GEN_40;
wire GEN_41;
wire GEN_42;
wire GEN_43;
wire GEN_44;
wire GEN_45;
wire GEN_46;
wire [1:0] GEN_47;
wire T_216;
wire T_218;
wire T_219;
wire [1:0] GEN_48;
wire GEN_49;
wire [7:0] GEN_50;
wire [1:0] GEN_51;
wire T_220;
wire [3:0] GEN_67;
wire [3:0] T_224;
wire [3:0] T_228;
wire T_229;
wire T_230;
wire T_231;
wire T_232;
wire T_240_0;
wire T_240_1;
wire T_240_2;
wire T_240_3;
wire GEN_52;
wire GEN_53;
wire GEN_54;
wire GEN_55;
wire [1:0] GEN_56;
wire [7:0] GEN_57;
wire GEN_58;
wire GEN_59;
wire GEN_60;
wire GEN_61;
wire GEN_62;
wire GEN_63;
wire GEN_64;
wire [1:0] GEN_65;
sirv_qspi_physical_1 phy (
.clock(phy_clock),
.reset(phy_reset),
.io_port_sck(phy_io_port_sck),
.io_port_dq_0_i(phy_io_port_dq_0_i),
.io_port_dq_0_o(phy_io_port_dq_0_o),
.io_port_dq_0_oe(phy_io_port_dq_0_oe),
.io_port_dq_1_i(phy_io_port_dq_1_i),
.io_port_dq_1_o(phy_io_port_dq_1_o),
.io_port_dq_1_oe(phy_io_port_dq_1_oe),
.io_port_dq_2_i(phy_io_port_dq_2_i),
.io_port_dq_2_o(phy_io_port_dq_2_o),
.io_port_dq_2_oe(phy_io_port_dq_2_oe),
.io_port_dq_3_i(phy_io_port_dq_3_i),
.io_port_dq_3_o(phy_io_port_dq_3_o),
.io_port_dq_3_oe(phy_io_port_dq_3_oe),
.io_port_cs_0(phy_io_port_cs_0),
.io_port_cs_1(phy_io_port_cs_1),
.io_port_cs_2(phy_io_port_cs_2),
.io_port_cs_3(phy_io_port_cs_3),
.io_ctrl_sck_div(phy_io_ctrl_sck_div),
.io_ctrl_sck_pol(phy_io_ctrl_sck_pol),
.io_ctrl_sck_pha(phy_io_ctrl_sck_pha),
.io_ctrl_fmt_proto(phy_io_ctrl_fmt_proto),
.io_ctrl_fmt_endian(phy_io_ctrl_fmt_endian),
.io_ctrl_fmt_iodir(phy_io_ctrl_fmt_iodir),
.io_op_ready(phy_io_op_ready),
.io_op_valid(phy_io_op_valid),
.io_op_bits_fn(phy_io_op_bits_fn),
.io_op_bits_stb(phy_io_op_bits_stb),
.io_op_bits_cnt(phy_io_op_bits_cnt),
.io_op_bits_data(phy_io_op_bits_data),
.io_rx_valid(phy_io_rx_valid),
.io_rx_bits(phy_io_rx_bits)
);
assign io_port_sck = phy_io_port_sck;
assign io_port_dq_0_o = phy_io_port_dq_0_o;
assign io_port_dq_0_oe = phy_io_port_dq_0_oe;
assign io_port_dq_1_o = phy_io_port_dq_1_o;
assign io_port_dq_1_oe = phy_io_port_dq_1_oe;
assign io_port_dq_2_o = phy_io_port_dq_2_o;
assign io_port_dq_2_oe = phy_io_port_dq_2_oe;
assign io_port_dq_3_o = phy_io_port_dq_3_o;
assign io_port_dq_3_oe = phy_io_port_dq_3_oe;
assign io_port_cs_0 = cs_dflt_0;
assign io_port_cs_1 = cs_dflt_1;
assign io_port_cs_2 = cs_dflt_2;
assign io_port_cs_3 = cs_dflt_3;
assign io_link_tx_ready = GEN_40;
assign io_link_rx_valid = phy_io_rx_valid;
assign io_link_rx_bits = phy_io_rx_bits;
assign io_link_active = cs_assert;
assign phy_clock = clock;
assign phy_reset = reset;
assign phy_io_port_dq_0_i = io_port_dq_0_i;
assign phy_io_port_dq_1_i = io_port_dq_1_i;
assign phy_io_port_dq_2_i = io_port_dq_2_i;
assign phy_io_port_dq_3_i = io_port_dq_3_i;
assign phy_io_ctrl_sck_div = io_ctrl_sck_div;
assign phy_io_ctrl_sck_pol = io_ctrl_sck_pol;
assign phy_io_ctrl_sck_pha = io_ctrl_sck_pha;
assign phy_io_ctrl_fmt_proto = io_link_fmt_proto;
assign phy_io_ctrl_fmt_endian = io_link_fmt_endian;
assign phy_io_ctrl_fmt_iodir = io_link_fmt_iodir;
assign phy_io_op_valid = GEN_49;
assign phy_io_op_bits_fn = GEN_37;
assign phy_io_op_bits_stb = GEN_58;
assign phy_io_op_bits_cnt = GEN_57;
assign phy_io_op_bits_data = io_link_tx_bits;
assign GEN_66 = {{3'd0}, io_link_cs_set};
assign T_162 = GEN_66 << io_ctrl_cs_id;
assign T_163 = {io_ctrl_cs_dflt_1,io_ctrl_cs_dflt_0};
assign T_164 = {io_ctrl_cs_dflt_3,io_ctrl_cs_dflt_2};
assign T_165 = {T_164,T_163};
assign T_166 = T_165 ^ T_162;
assign T_167 = T_166[0];
assign T_168 = T_166[1];
assign T_169 = T_166[2];
assign T_170 = T_166[3];
assign cs_active_0 = T_167;
assign cs_active_1 = T_168;
assign cs_active_2 = T_169;
assign cs_active_3 = T_170;
assign T_184 = {cs_active_1,cs_active_0};
assign T_185 = {cs_active_3,cs_active_2};
assign T_186 = {T_185,T_184};
assign T_187 = {cs_dflt_1,cs_dflt_0};
assign T_188 = {cs_dflt_3,cs_dflt_2};
assign T_189 = {T_188,T_187};
assign cs_update = T_186 != T_189;
assign T_193 = io_link_cs_hold == 1'h0;
assign T_194 = cs_update & T_193;
assign cs_deassert = clear | T_194;
assign T_195 = io_link_cs_clear & cs_assert;
assign T_196 = clear | T_195;
assign continuous = io_ctrl_dla_interxfr == 8'h0;
assign T_200 = 2'h0 == state;
assign GEN_0 = phy_io_op_ready ? 2'h2 : state;
assign GEN_1 = cs_deassert ? io_ctrl_dla_sckcs : io_link_cnt;
assign GEN_2 = cs_deassert ? GEN_0 : state;
assign T_202 = cs_deassert == 1'h0;
assign T_204 = phy_io_op_ready & phy_io_op_valid;
assign GEN_3 = T_204 ? 2'h1 : GEN_2;
assign GEN_4 = T_202 ? 1'h0 : 1'h1;
assign GEN_6 = T_202 ? io_link_tx_valid : 1'h1;
assign GEN_7 = T_202 ? phy_io_op_ready : 1'h0;
assign GEN_8 = T_202 ? GEN_3 : GEN_2;
assign GEN_9 = cs_assert ? GEN_1 : io_link_cnt;
assign GEN_10 = cs_assert ? GEN_8 : state;
assign GEN_11 = cs_assert ? GEN_4 : 1'h1;
assign GEN_12 = cs_assert ? T_202 : 1'h0;
assign GEN_13 = cs_assert ? GEN_6 : 1'h1;
assign GEN_14 = cs_assert ? GEN_7 : 1'h0;
assign T_206 = cs_assert == 1'h0;
assign T_207 = T_206 & io_link_tx_valid;
assign GEN_15 = phy_io_op_ready ? 1'h1 : cs_assert;
assign GEN_16 = phy_io_op_ready ? io_link_cs_set : cs_set;
assign GEN_17 = phy_io_op_ready ? cs_active_0 : cs_dflt_0;
assign GEN_18 = phy_io_op_ready ? cs_active_1 : cs_dflt_1;
assign GEN_19 = phy_io_op_ready ? cs_active_2 : cs_dflt_2;
assign GEN_20 = phy_io_op_ready ? cs_active_3 : cs_dflt_3;
assign GEN_21 = T_207 ? io_ctrl_dla_cssck : GEN_9;
assign GEN_22 = T_207 ? GEN_15 : cs_assert;
assign GEN_23 = T_207 ? GEN_16 : cs_set;
assign GEN_24 = T_207 ? GEN_17 : cs_dflt_0;
assign GEN_25 = T_207 ? GEN_18 : cs_dflt_1;
assign GEN_26 = T_207 ? GEN_19 : cs_dflt_2;
assign GEN_27 = T_207 ? GEN_20 : cs_dflt_3;
assign T_212 = io_link_tx_valid == 1'h0;
assign T_213 = T_206 & T_212;
assign GEN_28 = T_213 ? 8'h0 : GEN_21;
assign GEN_29 = T_213 ? 1'h1 : GEN_12;
assign GEN_30 = T_213 ? io_ctrl_cs_id : cs_id;
assign GEN_31 = T_213 ? io_ctrl_cs_dflt_0 : GEN_24;
assign GEN_32 = T_213 ? io_ctrl_cs_dflt_1 : GEN_25;
assign GEN_33 = T_213 ? io_ctrl_cs_dflt_2 : GEN_26;
assign GEN_34 = T_213 ? io_ctrl_cs_dflt_3 : GEN_27;
assign GEN_35 = T_200 ? GEN_28 : io_link_cnt;
assign GEN_36 = T_200 ? GEN_10 : state;
assign GEN_37 = T_200 ? GEN_11 : 1'h1;
assign GEN_38 = T_200 ? GEN_29 : 1'h0;
assign GEN_39 = T_200 ? GEN_13 : 1'h1;
assign GEN_40 = T_200 ? GEN_14 : 1'h0;
assign GEN_41 = T_200 ? GEN_22 : cs_assert;
assign GEN_42 = T_200 ? GEN_23 : cs_set;
assign GEN_43 = T_200 ? GEN_31 : cs_dflt_0;
assign GEN_44 = T_200 ? GEN_32 : cs_dflt_1;
assign GEN_45 = T_200 ? GEN_33 : cs_dflt_2;
assign GEN_46 = T_200 ? GEN_34 : cs_dflt_3;
assign GEN_47 = T_200 ? GEN_30 : cs_id;
assign T_216 = 2'h1 == state;
assign T_218 = continuous == 1'h0;
assign T_219 = phy_io_op_ready | continuous;
assign GEN_48 = T_219 ? 2'h0 : GEN_36;
assign GEN_49 = T_216 ? T_218 : GEN_39;
assign GEN_50 = T_216 ? io_ctrl_dla_interxfr : GEN_35;
assign GEN_51 = T_216 ? GEN_48 : GEN_36;
assign T_220 = 2'h2 == state;
assign GEN_67 = {{3'd0}, cs_set};
assign T_224 = GEN_67 << cs_id;
assign T_228 = T_189 ^ T_224;
assign T_229 = T_228[0];
assign T_230 = T_228[1];
assign T_231 = T_228[2];
assign T_232 = T_228[3];
assign T_240_0 = T_229;
assign T_240_1 = T_230;
assign T_240_2 = T_231;
assign T_240_3 = T_232;
assign GEN_52 = phy_io_op_ready ? T_240_0 : GEN_43;
assign GEN_53 = phy_io_op_ready ? T_240_1 : GEN_44;
assign GEN_54 = phy_io_op_ready ? T_240_2 : GEN_45;
assign GEN_55 = phy_io_op_ready ? T_240_3 : GEN_46;
assign GEN_56 = phy_io_op_ready ? 2'h0 : GEN_51;
assign GEN_57 = T_220 ? io_ctrl_dla_intercs : GEN_50;
assign GEN_58 = T_220 ? 1'h1 : GEN_38;
assign GEN_59 = T_220 ? 1'h0 : GEN_41;
assign GEN_60 = T_220 ? 1'h0 : T_196;
assign GEN_61 = T_220 ? GEN_52 : GEN_43;
assign GEN_62 = T_220 ? GEN_53 : GEN_44;
assign GEN_63 = T_220 ? GEN_54 : GEN_45;
assign GEN_64 = T_220 ? GEN_55 : GEN_46;
assign GEN_65 = T_220 ? GEN_56 : GEN_51;
always @(posedge clock or posedge reset)
if(reset) begin
cs_id <= 2'b0;
cs_dflt_0 <= 1'b1;
cs_dflt_1 <= 1'b1;
cs_dflt_2 <= 1'b1;
cs_dflt_3 <= 1'b1;
cs_set <= 1'b0;
end
else begin//{
if (T_200) begin
if (T_213) begin
cs_id <= io_ctrl_cs_id;
end
end
if (T_220) begin
if (phy_io_op_ready) begin
cs_dflt_0 <= T_240_0;
end else begin
if (T_200) begin
if (T_213) begin
cs_dflt_0 <= io_ctrl_cs_dflt_0;
end else begin
if (T_207) begin
if (phy_io_op_ready) begin
cs_dflt_0 <= cs_active_0;
end
end
end
end
end
end else begin
if (T_200) begin
if (T_213) begin
cs_dflt_0 <= io_ctrl_cs_dflt_0;
end else begin
if (T_207) begin
if (phy_io_op_ready) begin
cs_dflt_0 <= cs_active_0;
end
end
end
end
end
if (T_220) begin
if (phy_io_op_ready) begin
cs_dflt_1 <= T_240_1;
end else begin
if (T_200) begin
if (T_213) begin
cs_dflt_1 <= io_ctrl_cs_dflt_1;
end else begin
if (T_207) begin
if (phy_io_op_ready) begin
cs_dflt_1 <= cs_active_1;
end
end
end
end
end
end else begin
if (T_200) begin
if (T_213) begin
cs_dflt_1 <= io_ctrl_cs_dflt_1;
end else begin
if (T_207) begin
if (phy_io_op_ready) begin
cs_dflt_1 <= cs_active_1;
end
end
end
end
end
if (T_220) begin
if (phy_io_op_ready) begin
cs_dflt_2 <= T_240_2;
end else begin
if (T_200) begin
if (T_213) begin
cs_dflt_2 <= io_ctrl_cs_dflt_2;
end else begin
if (T_207) begin
if (phy_io_op_ready) begin
cs_dflt_2 <= cs_active_2;
end
end
end
end
end
end else begin
if (T_200) begin
if (T_213) begin
cs_dflt_2 <= io_ctrl_cs_dflt_2;
end else begin
if (T_207) begin
if (phy_io_op_ready) begin
cs_dflt_2 <= cs_active_2;
end
end
end
end
end
if (T_220) begin
if (phy_io_op_ready) begin
cs_dflt_3 <= T_240_3;
end else begin
if (T_200) begin
if (T_213) begin
cs_dflt_3 <= io_ctrl_cs_dflt_3;
end else begin
if (T_207) begin
if (phy_io_op_ready) begin
cs_dflt_3 <= cs_active_3;
end
end
end
end
end
end else begin
if (T_200) begin
if (T_213) begin
cs_dflt_3 <= io_ctrl_cs_dflt_3;
end else begin
if (T_207) begin
if (phy_io_op_ready) begin
cs_dflt_3 <= cs_active_3;
end
end
end
end
end
if (T_200) begin
if (T_207) begin
if (phy_io_op_ready) begin
cs_set <= io_link_cs_set;
end
end
end
end//}
always @(posedge clock or posedge reset)
if (reset) begin
clear <= 1'h0;
end else begin
if (T_220) begin
clear <= 1'h0;
end else begin
clear <= T_196;
end
end
always @(posedge clock or posedge reset)
if (reset) begin
cs_assert <= 1'h0;
end else begin
if (T_220) begin
cs_assert <= 1'h0;
end else begin
if (T_200) begin
if (T_207) begin
if (phy_io_op_ready) begin
cs_assert <= 1'h1;
end
end
end
end
end
always @(posedge clock or posedge reset)
if (reset) begin
state <= 2'h0;
end else begin
if (T_220) begin
if (phy_io_op_ready) begin
state <= 2'h0;
end else begin
if (T_216) begin
if (T_219) begin
state <= 2'h0;
end else begin
if (T_200) begin
if (cs_assert) begin
if (T_202) begin
if (T_204) begin
state <= 2'h1;
end else begin
if (cs_deassert) begin
if (phy_io_op_ready) begin
state <= 2'h2;
end
end
end
end else begin
if (cs_deassert) begin
if (phy_io_op_ready) begin
state <= 2'h2;
end
end
end
end
end
end
end else begin
if (T_200) begin
if (cs_assert) begin
if (T_202) begin
if (T_204) begin
state <= 2'h1;
end else begin
if (cs_deassert) begin
if (phy_io_op_ready) begin
state <= 2'h2;
end
end
end
end else begin
if (cs_deassert) begin
if (phy_io_op_ready) begin
state <= 2'h2;
end
end
end
end
end
end
end
end else begin
if (T_216) begin
if (T_219) begin
state <= 2'h0;
end else begin
if (T_200) begin
if (cs_assert) begin
if (T_202) begin
if (T_204) begin
state <= 2'h1;
end else begin
state <= GEN_2;
end
end else begin
state <= GEN_2;
end
end
end
end
end else begin
if (T_200) begin
if (cs_assert) begin
if (T_202) begin
if (T_204) begin
state <= 2'h1;
end else begin
state <= GEN_2;
end
end else begin
state <= GEN_2;
end
end
end
end
end
end
endmodule |
module sirv_qspi_flashmap(
input clock,
input reset,
input io_en,
input [1:0] io_ctrl_insn_cmd_proto,
input [7:0] io_ctrl_insn_cmd_code,
input io_ctrl_insn_cmd_en,
input [1:0] io_ctrl_insn_addr_proto,
input [2:0] io_ctrl_insn_addr_len,
input [7:0] io_ctrl_insn_pad_code,
input [3:0] io_ctrl_insn_pad_cnt,
input [1:0] io_ctrl_insn_data_proto,
input io_ctrl_fmt_endian,
output io_addr_ready,
input io_addr_valid,
input [31:0] io_addr_bits_next,
input [31:0] io_addr_bits_hold,
input io_data_ready,
output io_data_valid,
output [7:0] io_data_bits,
input io_link_tx_ready,
output io_link_tx_valid,
output [7:0] io_link_tx_bits,
input io_link_rx_valid,
input [7:0] io_link_rx_bits,
output [7:0] io_link_cnt,
output [1:0] io_link_fmt_proto,
output io_link_fmt_endian,
output io_link_fmt_iodir,
output io_link_cs_set,
output io_link_cs_clear,
output io_link_cs_hold,
input io_link_active,
output io_link_lock
);
wire [32:0] T_110;
wire [31:0] addr;
wire T_111;
wire merge;
wire T_113;
wire T_114;
wire T_115;
wire [3:0] T_120;
wire [2:0] T_122;
wire [1:0] T_124;
wire [3:0] GEN_46;
wire [3:0] T_126;
wire [3:0] GEN_47;
wire [3:0] T_127;
wire [3:0] T_128;
reg [3:0] cnt;
reg [31:0] GEN_5;
wire cnt_en;
wire cnt_cmp_0;
wire cnt_cmp_1;
wire cnt_cmp_2;
wire cnt_cmp_3;
wire cnt_cmp_4;
wire cnt_last;
wire cnt_done;
wire T_143;
wire T_144;
wire [4:0] T_146;
wire [3:0] T_147;
wire [3:0] GEN_0;
wire GEN_1;
wire [3:0] GEN_2;
reg [2:0] state;
reg [31:0] GEN_9;
wire T_149;
wire [2:0] GEN_3;
wire T_153;
wire [2:0] T_154;
wire [2:0] GEN_4;
wire [2:0] GEN_6;
wire GEN_7;
wire T_157;
wire GEN_8;
wire [2:0] GEN_10;
wire GEN_11;
wire GEN_12;
wire T_160;
wire GEN_13;
wire GEN_14;
wire [7:0] GEN_15;
wire GEN_16;
wire GEN_17;
wire GEN_18;
wire [2:0] GEN_19;
wire GEN_20;
wire GEN_21;
wire GEN_22;
wire [7:0] GEN_23;
wire T_163;
wire [2:0] GEN_24;
wire [3:0] GEN_25;
wire [1:0] GEN_26;
wire [2:0] GEN_28;
wire [3:0] GEN_29;
wire T_164;
wire [7:0] T_165;
wire [7:0] T_166;
wire [7:0] T_167;
wire [7:0] T_168;
wire [7:0] T_170;
wire [7:0] T_172;
wire [7:0] T_174;
wire [7:0] T_176;
wire [7:0] T_178;
wire [7:0] T_179;
wire [7:0] T_180;
wire [7:0] T_181;
wire [2:0] GEN_30;
wire [7:0] GEN_31;
wire [2:0] GEN_33;
wire T_183;
wire [2:0] GEN_34;
wire [3:0] GEN_35;
wire [7:0] GEN_36;
wire [2:0] GEN_37;
wire T_184;
wire [2:0] GEN_38;
wire [1:0] GEN_39;
wire GEN_40;
wire [2:0] GEN_41;
wire T_185;
wire T_187;
wire [2:0] GEN_42;
wire GEN_43;
wire GEN_44;
wire [2:0] GEN_45;
assign io_addr_ready = GEN_18;
assign io_data_valid = GEN_44;
assign io_data_bits = GEN_23;
assign io_link_tx_valid = GEN_43;
assign io_link_tx_bits = GEN_36;
assign io_link_cnt = {{4'd0}, GEN_35};
assign io_link_fmt_proto = GEN_39;
assign io_link_fmt_endian = io_ctrl_fmt_endian;
assign io_link_fmt_iodir = GEN_40;
assign io_link_cs_set = 1'h1;
assign io_link_cs_clear = GEN_20;
assign io_link_cs_hold = 1'h1;
assign io_link_lock = GEN_21;
assign T_110 = io_addr_bits_hold + 32'h1;
assign addr = T_110[31:0];
assign T_111 = io_addr_bits_next == addr;
assign merge = io_link_active & T_111;
assign T_113 = 2'h0 == io_link_fmt_proto;
assign T_114 = 2'h1 == io_link_fmt_proto;
assign T_115 = 2'h2 == io_link_fmt_proto;
assign T_120 = T_113 ? 4'h8 : 4'h0;
assign T_122 = T_114 ? 3'h4 : 3'h0;
assign T_124 = T_115 ? 2'h2 : 2'h0;
assign GEN_46 = {{1'd0}, T_122};
assign T_126 = T_120 | GEN_46;
assign GEN_47 = {{2'd0}, T_124};
assign T_127 = T_126 | GEN_47;
assign T_128 = T_127;
assign cnt_en = T_164;
assign cnt_cmp_0 = cnt == 4'h0;
assign cnt_cmp_1 = cnt == 4'h1;
assign cnt_cmp_2 = cnt == 4'h2;
assign cnt_cmp_3 = cnt == 4'h3;
assign cnt_cmp_4 = cnt == 4'h4;
assign cnt_last = cnt_cmp_1 & io_link_tx_ready;
assign cnt_done = cnt_last | cnt_cmp_0;
assign T_143 = cnt_cmp_0 == 1'h0;
assign T_144 = io_link_tx_ready & io_link_tx_valid;
assign T_146 = cnt - 4'h1;
assign T_147 = T_146[3:0];
assign GEN_0 = T_144 ? T_147 : cnt;
assign GEN_1 = cnt_en ? T_143 : 1'h1;
assign GEN_2 = cnt_en ? GEN_0 : cnt;
assign T_149 = 3'h0 == state;
assign GEN_3 = merge ? 3'h4 : state;
assign T_153 = merge == 1'h0;
assign T_154 = io_ctrl_insn_cmd_en ? 3'h1 : 3'h2;
assign GEN_4 = T_153 ? T_154 : GEN_3;
assign GEN_6 = io_addr_valid ? GEN_4 : state;
assign GEN_7 = io_addr_valid ? T_153 : 1'h0;
assign T_157 = io_addr_valid == 1'h0;
assign GEN_8 = T_157 ? 1'h0 : 1'h1;
assign GEN_10 = io_en ? GEN_6 : state;
assign GEN_11 = io_en ? GEN_7 : 1'h0;
assign GEN_12 = io_en ? GEN_8 : 1'h1;
assign T_160 = io_en == 1'h0;
assign GEN_13 = T_160 ? io_addr_valid : 1'h0;
assign GEN_14 = T_160 ? io_data_ready : io_en;
assign GEN_15 = T_160 ? 8'h0 : io_link_rx_bits;
assign GEN_16 = T_160 ? 1'h0 : GEN_12;
assign GEN_17 = T_149 ? 1'h0 : GEN_1;
assign GEN_18 = T_149 ? GEN_14 : 1'h0;
assign GEN_19 = T_149 ? GEN_10 : state;
assign GEN_20 = T_149 ? GEN_11 : 1'h0;
assign GEN_21 = T_149 ? GEN_16 : 1'h1;
assign GEN_22 = T_149 ? GEN_13 : 1'h0;
assign GEN_23 = T_149 ? GEN_15 : io_link_rx_bits;
assign T_163 = 3'h1 == state;
assign GEN_24 = io_link_tx_ready ? 3'h2 : GEN_19;
assign GEN_25 = io_link_tx_ready ? {{1'd0}, io_ctrl_insn_addr_len} : GEN_2;
assign GEN_26 = T_163 ? io_ctrl_insn_cmd_proto : io_ctrl_insn_addr_proto;
assign GEN_28 = T_163 ? GEN_24 : GEN_19;
assign GEN_29 = T_163 ? GEN_25 : GEN_2;
assign T_164 = 3'h2 == state;
assign T_165 = io_addr_bits_hold[7:0];
assign T_166 = io_addr_bits_hold[15:8];
assign T_167 = io_addr_bits_hold[23:16];
assign T_168 = io_addr_bits_hold[31:24];
assign T_170 = cnt_cmp_1 ? T_165 : 8'h0;
assign T_172 = cnt_cmp_2 ? T_166 : 8'h0;
assign T_174 = cnt_cmp_3 ? T_167 : 8'h0;
assign T_176 = cnt_cmp_4 ? T_168 : 8'h0;
assign T_178 = T_170 | T_172;
assign T_179 = T_178 | T_174;
assign T_180 = T_179 | T_176;
assign T_181 = T_180;
assign GEN_30 = cnt_done ? 3'h3 : GEN_28;
assign GEN_31 = T_164 ? T_181 : io_ctrl_insn_cmd_code;
assign GEN_33 = T_164 ? GEN_30 : GEN_28;
assign T_183 = 3'h3 == state;
assign GEN_34 = io_link_tx_ready ? 3'h4 : GEN_33;
assign GEN_35 = T_183 ? io_ctrl_insn_pad_cnt : T_128;
assign GEN_36 = T_183 ? io_ctrl_insn_pad_code : GEN_31;
assign GEN_37 = T_183 ? GEN_34 : GEN_33;
assign T_184 = 3'h4 == state;
assign GEN_38 = io_link_tx_ready ? 3'h5 : GEN_37;
assign GEN_39 = T_184 ? io_ctrl_insn_data_proto : GEN_26;
assign GEN_40 = T_184 ? 1'h0 : 1'h1;
assign GEN_41 = T_184 ? GEN_38 : GEN_37;
assign T_185 = 3'h5 == state;
assign T_187 = io_data_ready & io_data_valid;
assign GEN_42 = T_187 ? 3'h0 : GEN_41;
assign GEN_43 = T_185 ? 1'h0 : GEN_17;
assign GEN_44 = T_185 ? io_link_rx_valid : GEN_22;
assign GEN_45 = T_185 ? GEN_42 : GEN_41;
always @(posedge clock or posedge reset)
if (reset) begin
cnt <= 4'b0;
end
else begin
if (T_163) begin
if (io_link_tx_ready) begin
cnt <= {{1'd0}, io_ctrl_insn_addr_len};
end else begin
if (cnt_en) begin
if (T_144) begin
cnt <= T_147;
end
end
end
end else begin
if (cnt_en) begin
if (T_144) begin
cnt <= T_147;
end
end
end
end
always @(posedge clock or posedge reset)
if (reset) begin
state <= 3'h0;
end else begin
if (T_185) begin
if (T_187) begin
state <= 3'h0;
end else begin
if (T_184) begin
if (io_link_tx_ready) begin
state <= 3'h5;
end else begin
if (T_183) begin
if (io_link_tx_ready) begin
state <= 3'h4;
end else begin
if (T_164) begin
if (cnt_done) begin
state <= 3'h3;
end else begin
if (T_163) begin
if (io_link_tx_ready) begin
state <= 3'h2;
end else begin
if (T_149) begin
if (io_en) begin
if (io_addr_valid) begin
if (T_153) begin
if (io_ctrl_insn_cmd_en) begin
state <= 3'h1;
end else begin
state <= 3'h2;
end
end else begin
if (merge) begin
state <= 3'h4;
end
end
end
end
end
end
end else begin
if (T_149) begin
if (io_en) begin
if (io_addr_valid) begin
if (T_153) begin
if (io_ctrl_insn_cmd_en) begin
state <= 3'h1;
end else begin
state <= 3'h2;
end
end else begin
if (merge) begin
state <= 3'h4;
end
end
end
end
end
end
end
end else begin
if (T_163) begin
if (io_link_tx_ready) begin
state <= 3'h2;
end else begin
if (T_149) begin
if (io_en) begin
if (io_addr_valid) begin
if (T_153) begin
if (io_ctrl_insn_cmd_en) begin
state <= 3'h1;
end else begin
state <= 3'h2;
end
end else begin
if (merge) begin
state <= 3'h4;
end
end
end
end
end
end
end else begin
if (T_149) begin
if (io_en) begin
if (io_addr_valid) begin
if (T_153) begin
if (io_ctrl_insn_cmd_en) begin
state <= 3'h1;
end else begin
state <= 3'h2;
end
end else begin
if (merge) begin
state <= 3'h4;
end
end
end
end
end
end
end
end
end else begin
if (T_164) begin
if (cnt_done) begin
state <= 3'h3;
end else begin
if (T_163) begin
if (io_link_tx_ready) begin
state <= 3'h2;
end else begin
state <= GEN_19;
end
end else begin
state <= GEN_19;
end
end
end else begin
if (T_163) begin
if (io_link_tx_ready) begin
state <= 3'h2;
end else begin
state <= GEN_19;
end
end else begin
state <= GEN_19;
end
end
end
end
end else begin
if (T_183) begin
if (io_link_tx_ready) begin
state <= 3'h4;
end else begin
if (T_164) begin
if (cnt_done) begin
state <= 3'h3;
end else begin
state <= GEN_28;
end
end else begin
state <= GEN_28;
end
end
end else begin
if (T_164) begin
if (cnt_done) begin
state <= 3'h3;
end else begin
state <= GEN_28;
end
end else begin
state <= GEN_28;
end
end
end
end
end else begin
if (T_184) begin
if (io_link_tx_ready) begin
state <= 3'h5;
end else begin
if (T_183) begin
if (io_link_tx_ready) begin
state <= 3'h4;
end else begin
state <= GEN_33;
end
end else begin
state <= GEN_33;
end
end
end else begin
if (T_183) begin
if (io_link_tx_ready) begin
state <= 3'h4;
end else begin
state <= GEN_33;
end
end else begin
state <= GEN_33;
end
end
end
end
endmodule |
module e203_irq_sync #(
parameter MASTER = 1
) (
input clk,
input rst_n,
input ext_irq_a,
input sft_irq_a,
input tmr_irq_a,
input dbg_irq_a,
output ext_irq_r,
output sft_irq_r,
output tmr_irq_r,
output dbg_irq_r
);
generate
if(MASTER == 1) begin:master_gen
`ifndef E203_HAS_LOCKSTEP//{
`ifdef E203_IRQ_NEED_SYNC//{
sirv_gnrl_sync # (
.DP(`E203_ASYNC_FF_LEVELS),
.DW(1)
) u_dbg_irq_sync(
.din_a (dbg_irq_a),
.dout (dbg_irq_r),
.clk (clk ),
.rst_n (rst_n)
);
sirv_gnrl_sync # (
.DP(`E203_ASYNC_FF_LEVELS),
.DW(1)
) u_ext_irq_sync(
.din_a (ext_irq_a),
.dout (ext_irq_r),
.clk (clk ),
.rst_n (rst_n)
);
sirv_gnrl_sync # (
.DP(`E203_ASYNC_FF_LEVELS),
.DW(1)
) u_sft_irq_sync(
.din_a (sft_irq_a),
.dout (sft_irq_r),
.clk (clk ),
.rst_n (rst_n)
);
sirv_gnrl_sync # (
.DP(`E203_ASYNC_FF_LEVELS),
.DW(1)
) u_tmr_irq_sync(
.din_a (tmr_irq_a),
.dout (tmr_irq_r),
.clk (clk ),
.rst_n (rst_n)
);
`else//}{
assign ext_irq_r = ext_irq_a;
assign sft_irq_r = sft_irq_a;
assign tmr_irq_r = tmr_irq_a;
assign dbg_irq_r = dbg_irq_a;
`endif//}
`endif//}
end
else begin:slave_gen
// Just pass through for slave in lockstep mode
assign ext_irq_r = ext_irq_a;
assign sft_irq_r = sft_irq_a;
assign tmr_irq_r = tmr_irq_a;
assign dbg_irq_r = dbg_irq_a;
end
endgenerate
endmodule |
module sirv_icb1to8_bus # (
parameter ICB_FIFO_DP = 0, // This is to optionally add the pipeline stage for ICB bus
// if the depth is 0, then means pass through, not add pipeline
// if the depth is 2, then means added one ping-pong buffer stage
parameter ICB_FIFO_CUT_READY = 1, // This is to cut the back-pressure signal if you set as 1
parameter AW = 32,
parameter DW = 32,
parameter SPLT_FIFO_OUTS_NUM = 1,
parameter SPLT_FIFO_CUT_READY = 1,
parameter O0_BASE_ADDR = 32'h0000_1000,
parameter O0_BASE_REGION_LSB = 12,
parameter O1_BASE_ADDR = 32'h0000_1000,
parameter O1_BASE_REGION_LSB = 12,
parameter O2_BASE_ADDR = 32'h0000_1000,
parameter O2_BASE_REGION_LSB = 12,
parameter O3_BASE_ADDR = 32'h0000_1000,
parameter O3_BASE_REGION_LSB = 12,
parameter O4_BASE_ADDR = 32'h0000_1000,
parameter O4_BASE_REGION_LSB = 12,
parameter O5_BASE_ADDR = 32'h0000_1000,
parameter O5_BASE_REGION_LSB = 12,
parameter O6_BASE_ADDR = 32'h0000_1000,
parameter O6_BASE_REGION_LSB = 12,
parameter O7_BASE_ADDR = 32'h0000_1000,
parameter O7_BASE_REGION_LSB = 12
)(
input o0_icb_enable,
input o1_icb_enable,
input o2_icb_enable,
input o3_icb_enable,
input o4_icb_enable,
input o5_icb_enable,
input o6_icb_enable,
input o7_icb_enable,
input i_icb_cmd_valid,
output i_icb_cmd_ready,
input [ AW-1:0] i_icb_cmd_addr,
input i_icb_cmd_read,
input [2-1:0] i_icb_cmd_burst,
input [2-1:0] i_icb_cmd_beat,
input [ DW-1:0] i_icb_cmd_wdata,
input [ DW/8-1:0] i_icb_cmd_wmask,
input i_icb_cmd_lock,
input i_icb_cmd_excl,
input [1:0] i_icb_cmd_size,
output i_icb_rsp_valid,
input i_icb_rsp_ready,
output i_icb_rsp_err ,
output i_icb_rsp_excl_ok,
output [ DW-1:0] i_icb_rsp_rdata,
output o0_icb_cmd_valid,
input o0_icb_cmd_ready,
output [ AW-1:0] o0_icb_cmd_addr,
output o0_icb_cmd_read,
output [2-1:0] o0_icb_cmd_burst,
output [2-1:0] o0_icb_cmd_beat,
output [ DW-1:0] o0_icb_cmd_wdata,
output [ DW/8-1:0] o0_icb_cmd_wmask,
output o0_icb_cmd_lock,
output o0_icb_cmd_excl,
output [1:0] o0_icb_cmd_size,
input o0_icb_rsp_valid,
output o0_icb_rsp_ready,
input o0_icb_rsp_err ,
input o0_icb_rsp_excl_ok,
input [ DW-1:0] o0_icb_rsp_rdata,
output o1_icb_cmd_valid,
input o1_icb_cmd_ready,
output [ AW-1:0] o1_icb_cmd_addr,
output o1_icb_cmd_read,
output [2-1:0] o1_icb_cmd_burst,
output [2-1:0] o1_icb_cmd_beat,
output [ DW-1:0] o1_icb_cmd_wdata,
output [ DW/8-1:0] o1_icb_cmd_wmask,
output o1_icb_cmd_lock,
output o1_icb_cmd_excl,
output [1:0] o1_icb_cmd_size,
input o1_icb_rsp_valid,
output o1_icb_rsp_ready,
input o1_icb_rsp_err ,
input o1_icb_rsp_excl_ok,
input [ DW-1:0] o1_icb_rsp_rdata,
output o2_icb_cmd_valid,
input o2_icb_cmd_ready,
output [ AW-1:0] o2_icb_cmd_addr,
output o2_icb_cmd_read,
output [2-1:0] o2_icb_cmd_burst,
output [2-1:0] o2_icb_cmd_beat,
output [ DW-1:0] o2_icb_cmd_wdata,
output [ DW/8-1:0] o2_icb_cmd_wmask,
output o2_icb_cmd_lock,
output o2_icb_cmd_excl,
output [1:0] o2_icb_cmd_size,
input o2_icb_rsp_valid,
output o2_icb_rsp_ready,
input o2_icb_rsp_err ,
input o2_icb_rsp_excl_ok,
input [ DW-1:0] o2_icb_rsp_rdata,
output o3_icb_cmd_valid,
input o3_icb_cmd_ready,
output [ AW-1:0] o3_icb_cmd_addr,
output o3_icb_cmd_read,
output [2-1:0] o3_icb_cmd_burst,
output [2-1:0] o3_icb_cmd_beat,
output [ DW-1:0] o3_icb_cmd_wdata,
output [ DW/8-1:0] o3_icb_cmd_wmask,
output o3_icb_cmd_lock,
output o3_icb_cmd_excl,
output [1:0] o3_icb_cmd_size,
input o3_icb_rsp_valid,
output o3_icb_rsp_ready,
input o3_icb_rsp_err ,
input o3_icb_rsp_excl_ok,
input [ DW-1:0] o3_icb_rsp_rdata,
output o4_icb_cmd_valid,
input o4_icb_cmd_ready,
output [ AW-1:0] o4_icb_cmd_addr,
output o4_icb_cmd_read,
output [2-1:0] o4_icb_cmd_burst,
output [2-1:0] o4_icb_cmd_beat,
output [ DW-1:0] o4_icb_cmd_wdata,
output [ DW/8-1:0] o4_icb_cmd_wmask,
output o4_icb_cmd_lock,
output o4_icb_cmd_excl,
output [1:0] o4_icb_cmd_size,
input o4_icb_rsp_valid,
output o4_icb_rsp_ready,
input o4_icb_rsp_err ,
input o4_icb_rsp_excl_ok,
input [ DW-1:0] o4_icb_rsp_rdata,
output o5_icb_cmd_valid,
input o5_icb_cmd_ready,
output [ AW-1:0] o5_icb_cmd_addr,
output o5_icb_cmd_read,
output [2-1:0] o5_icb_cmd_burst,
output [2-1:0] o5_icb_cmd_beat,
output [ DW-1:0] o5_icb_cmd_wdata,
output [ DW/8-1:0] o5_icb_cmd_wmask,
output o5_icb_cmd_lock,
output o5_icb_cmd_excl,
output [1:0] o5_icb_cmd_size,
input o5_icb_rsp_valid,
output o5_icb_rsp_ready,
input o5_icb_rsp_err ,
input o5_icb_rsp_excl_ok,
input [ DW-1:0] o5_icb_rsp_rdata,
output o6_icb_cmd_valid,
input o6_icb_cmd_ready,
output [ AW-1:0] o6_icb_cmd_addr,
output o6_icb_cmd_read,
output [2-1:0] o6_icb_cmd_burst,
output [2-1:0] o6_icb_cmd_beat,
output [ DW-1:0] o6_icb_cmd_wdata,
output [ DW/8-1:0] o6_icb_cmd_wmask,
output o6_icb_cmd_lock,
output o6_icb_cmd_excl,
output [1:0] o6_icb_cmd_size,
input o6_icb_rsp_valid,
output o6_icb_rsp_ready,
input o6_icb_rsp_err ,
input o6_icb_rsp_excl_ok,
input [ DW-1:0] o6_icb_rsp_rdata,
output o7_icb_cmd_valid,
input o7_icb_cmd_ready,
output [ AW-1:0] o7_icb_cmd_addr,
output o7_icb_cmd_read,
output [2-1:0] o7_icb_cmd_burst,
output [2-1:0] o7_icb_cmd_beat,
output [ DW-1:0] o7_icb_cmd_wdata,
output [ DW/8-1:0] o7_icb_cmd_wmask,
output o7_icb_cmd_lock,
output o7_icb_cmd_excl,
output [1:0] o7_icb_cmd_size,
input o7_icb_rsp_valid,
output o7_icb_rsp_ready,
input o7_icb_rsp_err ,
input o7_icb_rsp_excl_ok,
input [ DW-1:0] o7_icb_rsp_rdata,
input clk,
input rst_n
);
wire buf_icb_cmd_valid;
wire buf_icb_cmd_ready;
wire [ AW-1:0] buf_icb_cmd_addr;
wire buf_icb_cmd_read;
wire [2-1:0] buf_icb_cmd_burst;
wire [2-1:0] buf_icb_cmd_beat;
wire [ DW-1:0] buf_icb_cmd_wdata;
wire [ DW/8-1:0] buf_icb_cmd_wmask;
wire buf_icb_cmd_lock;
wire buf_icb_cmd_excl;
wire [1:0] buf_icb_cmd_size;
wire buf_icb_rsp_valid;
wire buf_icb_rsp_ready;
wire buf_icb_rsp_err ;
wire buf_icb_rsp_excl_ok;
wire [ DW-1:0] buf_icb_rsp_rdata;
sirv_gnrl_icb_buffer # (
.OUTS_CNT_W (SPLT_FIFO_OUTS_NUM),
.AW (AW),
.DW (DW),
.CMD_DP(ICB_FIFO_DP),
.RSP_DP(ICB_FIFO_DP),
.CMD_CUT_READY (ICB_FIFO_CUT_READY),
.RSP_CUT_READY (ICB_FIFO_CUT_READY),
.USR_W (1)
)u_sirv_gnrl_icb_buffer(
.icb_buffer_active (),
.i_icb_cmd_valid (i_icb_cmd_valid),
.i_icb_cmd_ready (i_icb_cmd_ready),
.i_icb_cmd_read (i_icb_cmd_read ),
.i_icb_cmd_addr (i_icb_cmd_addr ),
.i_icb_cmd_wdata (i_icb_cmd_wdata),
.i_icb_cmd_wmask (i_icb_cmd_wmask),
.i_icb_cmd_lock (i_icb_cmd_lock ),
.i_icb_cmd_excl (i_icb_cmd_excl ),
.i_icb_cmd_size (i_icb_cmd_size ),
.i_icb_cmd_burst (i_icb_cmd_burst),
.i_icb_cmd_beat (i_icb_cmd_beat ),
.i_icb_cmd_usr (1'b0 ),
.i_icb_rsp_valid (i_icb_rsp_valid),
.i_icb_rsp_ready (i_icb_rsp_ready),
.i_icb_rsp_err (i_icb_rsp_err ),
.i_icb_rsp_excl_ok (i_icb_rsp_excl_ok),
.i_icb_rsp_rdata (i_icb_rsp_rdata),
.i_icb_rsp_usr (),
.o_icb_cmd_valid (buf_icb_cmd_valid),
.o_icb_cmd_ready (buf_icb_cmd_ready),
.o_icb_cmd_read (buf_icb_cmd_read ),
.o_icb_cmd_addr (buf_icb_cmd_addr ),
.o_icb_cmd_wdata (buf_icb_cmd_wdata),
.o_icb_cmd_wmask (buf_icb_cmd_wmask),
.o_icb_cmd_lock (buf_icb_cmd_lock ),
.o_icb_cmd_excl (buf_icb_cmd_excl ),
.o_icb_cmd_size (buf_icb_cmd_size ),
.o_icb_cmd_burst (buf_icb_cmd_burst),
.o_icb_cmd_beat (buf_icb_cmd_beat ),
.o_icb_cmd_usr (),
.o_icb_rsp_valid (buf_icb_rsp_valid),
.o_icb_rsp_ready (buf_icb_rsp_ready),
.o_icb_rsp_err (buf_icb_rsp_err ),
.o_icb_rsp_excl_ok (buf_icb_rsp_excl_ok),
.o_icb_rsp_rdata (buf_icb_rsp_rdata),
.o_icb_rsp_usr (1'b0 ),
.clk (clk ),
.rst_n (rst_n)
);
localparam BASE_REGION_MSB = (AW-1);
localparam SPLT_I_NUM = 9;
wire deft_icb_cmd_valid;
wire deft_icb_cmd_ready;
wire [ AW-1:0] deft_icb_cmd_addr;
wire deft_icb_cmd_read;
wire [2-1:0] deft_icb_cmd_burst;
wire [2-1:0] deft_icb_cmd_beat;
wire [ DW-1:0] deft_icb_cmd_wdata;
wire [ DW/8-1:0] deft_icb_cmd_wmask;
wire deft_icb_cmd_lock;
wire deft_icb_cmd_excl;
wire [1:0] deft_icb_cmd_size;
wire deft_icb_rsp_valid;
wire deft_icb_rsp_ready;
wire deft_icb_rsp_err ;
wire deft_icb_rsp_excl_ok;
wire [ DW-1:0] deft_icb_rsp_rdata;
wire [SPLT_I_NUM*1-1:0] splt_bus_icb_cmd_valid;
wire [SPLT_I_NUM*1-1:0] splt_bus_icb_cmd_ready;
wire [SPLT_I_NUM* AW-1:0] splt_bus_icb_cmd_addr;
wire [SPLT_I_NUM*1-1:0] splt_bus_icb_cmd_read;
wire [SPLT_I_NUM*2-1:0] splt_bus_icb_cmd_burst;
wire [SPLT_I_NUM*2-1:0] splt_bus_icb_cmd_beat;
wire [SPLT_I_NUM* DW-1:0] splt_bus_icb_cmd_wdata;
wire [SPLT_I_NUM* DW/8-1:0] splt_bus_icb_cmd_wmask;
wire [SPLT_I_NUM*1-1:0] splt_bus_icb_cmd_lock;
wire [SPLT_I_NUM*1-1:0] splt_bus_icb_cmd_excl;
wire [SPLT_I_NUM*2-1:0] splt_bus_icb_cmd_size;
wire [SPLT_I_NUM*1-1:0] splt_bus_icb_rsp_valid;
wire [SPLT_I_NUM*1-1:0] splt_bus_icb_rsp_ready;
wire [SPLT_I_NUM*1-1:0] splt_bus_icb_rsp_err;
wire [SPLT_I_NUM*1-1:0] splt_bus_icb_rsp_excl_ok;
wire [SPLT_I_NUM* DW-1:0] splt_bus_icb_rsp_rdata;
//CMD Channel
assign {
o0_icb_cmd_valid
, o1_icb_cmd_valid
, o2_icb_cmd_valid
, o3_icb_cmd_valid
, o4_icb_cmd_valid
, o5_icb_cmd_valid
, o6_icb_cmd_valid
, o7_icb_cmd_valid
, deft_icb_cmd_valid
} = splt_bus_icb_cmd_valid;
assign {
o0_icb_cmd_addr
, o1_icb_cmd_addr
, o2_icb_cmd_addr
, o3_icb_cmd_addr
, o4_icb_cmd_addr
, o5_icb_cmd_addr
, o6_icb_cmd_addr
, o7_icb_cmd_addr
, deft_icb_cmd_addr
} = splt_bus_icb_cmd_addr;
assign {
o0_icb_cmd_read
, o1_icb_cmd_read
, o2_icb_cmd_read
, o3_icb_cmd_read
, o4_icb_cmd_read
, o5_icb_cmd_read
, o6_icb_cmd_read
, o7_icb_cmd_read
, deft_icb_cmd_read
} = splt_bus_icb_cmd_read;
assign {
o0_icb_cmd_burst
, o1_icb_cmd_burst
, o2_icb_cmd_burst
, o3_icb_cmd_burst
, o4_icb_cmd_burst
, o5_icb_cmd_burst
, o6_icb_cmd_burst
, o7_icb_cmd_burst
, deft_icb_cmd_burst
} = splt_bus_icb_cmd_burst;
assign {
o0_icb_cmd_beat
, o1_icb_cmd_beat
, o2_icb_cmd_beat
, o3_icb_cmd_beat
, o4_icb_cmd_beat
, o5_icb_cmd_beat
, o6_icb_cmd_beat
, o7_icb_cmd_beat
, deft_icb_cmd_beat
} = splt_bus_icb_cmd_beat;
assign {
o0_icb_cmd_wdata
, o1_icb_cmd_wdata
, o2_icb_cmd_wdata
, o3_icb_cmd_wdata
, o4_icb_cmd_wdata
, o5_icb_cmd_wdata
, o6_icb_cmd_wdata
, o7_icb_cmd_wdata
, deft_icb_cmd_wdata
} = splt_bus_icb_cmd_wdata;
assign {
o0_icb_cmd_wmask
, o1_icb_cmd_wmask
, o2_icb_cmd_wmask
, o3_icb_cmd_wmask
, o4_icb_cmd_wmask
, o5_icb_cmd_wmask
, o6_icb_cmd_wmask
, o7_icb_cmd_wmask
, deft_icb_cmd_wmask
} = splt_bus_icb_cmd_wmask;
assign {
o0_icb_cmd_lock
, o1_icb_cmd_lock
, o2_icb_cmd_lock
, o3_icb_cmd_lock
, o4_icb_cmd_lock
, o5_icb_cmd_lock
, o6_icb_cmd_lock
, o7_icb_cmd_lock
, deft_icb_cmd_lock
} = splt_bus_icb_cmd_lock;
assign {
o0_icb_cmd_excl
, o1_icb_cmd_excl
, o2_icb_cmd_excl
, o3_icb_cmd_excl
, o4_icb_cmd_excl
, o5_icb_cmd_excl
, o6_icb_cmd_excl
, o7_icb_cmd_excl
, deft_icb_cmd_excl
} = splt_bus_icb_cmd_excl;
assign {
o0_icb_cmd_size
, o1_icb_cmd_size
, o2_icb_cmd_size
, o3_icb_cmd_size
, o4_icb_cmd_size
, o5_icb_cmd_size
, o6_icb_cmd_size
, o7_icb_cmd_size
, deft_icb_cmd_size
} = splt_bus_icb_cmd_size;
assign splt_bus_icb_cmd_ready = {
o0_icb_cmd_ready
, o1_icb_cmd_ready
, o2_icb_cmd_ready
, o3_icb_cmd_ready
, o4_icb_cmd_ready
, o5_icb_cmd_ready
, o6_icb_cmd_ready
, o7_icb_cmd_ready
, deft_icb_cmd_ready
};
//RSP Channel
assign splt_bus_icb_rsp_valid = {
o0_icb_rsp_valid
, o1_icb_rsp_valid
, o2_icb_rsp_valid
, o3_icb_rsp_valid
, o4_icb_rsp_valid
, o5_icb_rsp_valid
, o6_icb_rsp_valid
, o7_icb_rsp_valid
, deft_icb_rsp_valid
};
assign splt_bus_icb_rsp_err = {
o0_icb_rsp_err
, o1_icb_rsp_err
, o2_icb_rsp_err
, o3_icb_rsp_err
, o4_icb_rsp_err
, o5_icb_rsp_err
, o6_icb_rsp_err
, o7_icb_rsp_err
, deft_icb_rsp_err
};
assign splt_bus_icb_rsp_excl_ok = {
o0_icb_rsp_excl_ok
, o1_icb_rsp_excl_ok
, o2_icb_rsp_excl_ok
, o3_icb_rsp_excl_ok
, o4_icb_rsp_excl_ok
, o5_icb_rsp_excl_ok
, o6_icb_rsp_excl_ok
, o7_icb_rsp_excl_ok
, deft_icb_rsp_excl_ok
};
assign splt_bus_icb_rsp_rdata = {
o0_icb_rsp_rdata
, o1_icb_rsp_rdata
, o2_icb_rsp_rdata
, o3_icb_rsp_rdata
, o4_icb_rsp_rdata
, o5_icb_rsp_rdata
, o6_icb_rsp_rdata
, o7_icb_rsp_rdata
, deft_icb_rsp_rdata
};
assign {
o0_icb_rsp_ready
, o1_icb_rsp_ready
, o2_icb_rsp_ready
, o3_icb_rsp_ready
, o4_icb_rsp_ready
, o5_icb_rsp_ready
, o6_icb_rsp_ready
, o7_icb_rsp_ready
, deft_icb_rsp_ready
} = splt_bus_icb_rsp_ready;
wire icb_cmd_o0 = buf_icb_cmd_valid & (buf_icb_cmd_addr [BASE_REGION_MSB:O0_BASE_REGION_LSB]
== O0_BASE_ADDR [BASE_REGION_MSB:O0_BASE_REGION_LSB]
) & o0_icb_enable;
wire icb_cmd_o1 = buf_icb_cmd_valid & (buf_icb_cmd_addr [BASE_REGION_MSB:O1_BASE_REGION_LSB]
== O1_BASE_ADDR [BASE_REGION_MSB:O1_BASE_REGION_LSB]
) & o1_icb_enable;
wire icb_cmd_o2 = buf_icb_cmd_valid & (buf_icb_cmd_addr [BASE_REGION_MSB:O2_BASE_REGION_LSB]
== O2_BASE_ADDR [BASE_REGION_MSB:O2_BASE_REGION_LSB]
) & o2_icb_enable;
wire icb_cmd_o3 = buf_icb_cmd_valid & (buf_icb_cmd_addr [BASE_REGION_MSB:O3_BASE_REGION_LSB]
== O3_BASE_ADDR [BASE_REGION_MSB:O3_BASE_REGION_LSB]
) & o3_icb_enable;
wire icb_cmd_o4 = buf_icb_cmd_valid & (buf_icb_cmd_addr [BASE_REGION_MSB:O4_BASE_REGION_LSB]
== O4_BASE_ADDR [BASE_REGION_MSB:O4_BASE_REGION_LSB]
) & o4_icb_enable;
wire icb_cmd_o5 = buf_icb_cmd_valid & (buf_icb_cmd_addr [BASE_REGION_MSB:O5_BASE_REGION_LSB]
== O5_BASE_ADDR [BASE_REGION_MSB:O5_BASE_REGION_LSB]
) & o5_icb_enable;
wire icb_cmd_o6 = buf_icb_cmd_valid & (buf_icb_cmd_addr [BASE_REGION_MSB:O6_BASE_REGION_LSB]
== O6_BASE_ADDR [BASE_REGION_MSB:O6_BASE_REGION_LSB]
) & o6_icb_enable;
wire icb_cmd_o7 = buf_icb_cmd_valid & (buf_icb_cmd_addr [BASE_REGION_MSB:O7_BASE_REGION_LSB]
== O7_BASE_ADDR [BASE_REGION_MSB:O7_BASE_REGION_LSB]
) & o7_icb_enable;
wire icb_cmd_deft = (~icb_cmd_o0)
& (~icb_cmd_o1)
& (~icb_cmd_o2)
& (~icb_cmd_o3)
& (~icb_cmd_o4)
& (~icb_cmd_o5)
& (~icb_cmd_o6)
& (~icb_cmd_o7)
;
wire [SPLT_I_NUM-1:0] buf_icb_splt_indic =
{
icb_cmd_o0
, icb_cmd_o1
, icb_cmd_o2
, icb_cmd_o3
, icb_cmd_o4
, icb_cmd_o5
, icb_cmd_o6
, icb_cmd_o7
, icb_cmd_deft
};
sirv_gnrl_icb_splt # (
.ALLOW_DIFF (0),// Dont allow different branches oustanding
.ALLOW_0CYCL_RSP (1),// Allow the 0 cycle response because in BIU the splt
// is after the buffer, and will directly talk to the external
// bus, where maybe the ROM is 0 cycle responsed.
.FIFO_OUTS_NUM (SPLT_FIFO_OUTS_NUM ),
.FIFO_CUT_READY (SPLT_FIFO_CUT_READY),
.SPLT_NUM (SPLT_I_NUM),
.SPLT_PTR_W (SPLT_I_NUM),
.SPLT_PTR_1HOT (1),
.VLD_MSK_PAYLOAD(1),
.USR_W (1),
.AW (AW),
.DW (DW)
) u_i_icb_splt(
.i_icb_splt_indic (buf_icb_splt_indic),
.i_icb_cmd_valid (buf_icb_cmd_valid ) ,
.i_icb_cmd_ready (buf_icb_cmd_ready ) ,
.i_icb_cmd_read (buf_icb_cmd_read ) ,
.i_icb_cmd_addr (buf_icb_cmd_addr ) ,
.i_icb_cmd_wdata (buf_icb_cmd_wdata ) ,
.i_icb_cmd_wmask (buf_icb_cmd_wmask) ,
.i_icb_cmd_burst (buf_icb_cmd_burst) ,
.i_icb_cmd_beat (buf_icb_cmd_beat ) ,
.i_icb_cmd_excl (buf_icb_cmd_excl ) ,
.i_icb_cmd_lock (buf_icb_cmd_lock ) ,
.i_icb_cmd_size (buf_icb_cmd_size ) ,
.i_icb_cmd_usr (1'b0) ,
.i_icb_rsp_valid (buf_icb_rsp_valid ) ,
.i_icb_rsp_ready (buf_icb_rsp_ready ) ,
.i_icb_rsp_err (buf_icb_rsp_err) ,
.i_icb_rsp_excl_ok (buf_icb_rsp_excl_ok) ,
.i_icb_rsp_rdata (buf_icb_rsp_rdata ) ,
.i_icb_rsp_usr ( ) ,
.o_bus_icb_cmd_ready (splt_bus_icb_cmd_ready ) ,
.o_bus_icb_cmd_valid (splt_bus_icb_cmd_valid ) ,
.o_bus_icb_cmd_read (splt_bus_icb_cmd_read ) ,
.o_bus_icb_cmd_addr (splt_bus_icb_cmd_addr ) ,
.o_bus_icb_cmd_wdata (splt_bus_icb_cmd_wdata ) ,
.o_bus_icb_cmd_wmask (splt_bus_icb_cmd_wmask) ,
.o_bus_icb_cmd_burst (splt_bus_icb_cmd_burst),
.o_bus_icb_cmd_beat (splt_bus_icb_cmd_beat ),
.o_bus_icb_cmd_excl (splt_bus_icb_cmd_excl ),
.o_bus_icb_cmd_lock (splt_bus_icb_cmd_lock ),
.o_bus_icb_cmd_size (splt_bus_icb_cmd_size ),
.o_bus_icb_cmd_usr () ,
.o_bus_icb_rsp_valid (splt_bus_icb_rsp_valid ) ,
.o_bus_icb_rsp_ready (splt_bus_icb_rsp_ready ) ,
.o_bus_icb_rsp_err (splt_bus_icb_rsp_err) ,
.o_bus_icb_rsp_excl_ok (splt_bus_icb_rsp_excl_ok),
.o_bus_icb_rsp_rdata (splt_bus_icb_rsp_rdata ) ,
.o_bus_icb_rsp_usr ({SPLT_I_NUM{1'b0}}) ,
.clk (clk ) ,
.rst_n (rst_n)
);
///////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////
// Implement the default slave
assign deft_icb_cmd_ready = deft_icb_rsp_ready;
// 0 Cycle response
assign deft_icb_rsp_valid = deft_icb_cmd_valid;
assign deft_icb_rsp_err = 1'b1;
assign deft_icb_rsp_excl_ok = 1'b0;
assign deft_icb_rsp_rdata = {DW{1'b0}};
endmodule |
module e203_exu_commit(
output commit_mret,
output commit_trap,
output core_wfi,
output nonflush_cmt_ena,
output excp_active,
input amo_wait,
output wfi_halt_ifu_req,
output wfi_halt_exu_req,
input wfi_halt_ifu_ack,
input wfi_halt_exu_ack,
input dbg_irq_r,
input [`E203_LIRQ_NUM-1:0] lcl_irq_r,
input ext_irq_r,
input sft_irq_r,
input tmr_irq_r,
input [`E203_EVT_NUM-1:0] evt_r,
input status_mie_r,
input mtie_r,
input msie_r,
input meie_r,
input alu_cmt_i_valid,
output alu_cmt_i_ready,
input [`E203_PC_SIZE-1:0] alu_cmt_i_pc,
input [`E203_INSTR_SIZE-1:0] alu_cmt_i_instr,
input alu_cmt_i_pc_vld,
input [`E203_XLEN-1:0] alu_cmt_i_imm,
input alu_cmt_i_rv32,
// The Branch Commit
input alu_cmt_i_bjp,
input alu_cmt_i_wfi,
input alu_cmt_i_fencei,
input alu_cmt_i_mret,
input alu_cmt_i_dret,
input alu_cmt_i_ecall,
input alu_cmt_i_ebreak,
input alu_cmt_i_ifu_misalgn ,
input alu_cmt_i_ifu_buserr ,
input alu_cmt_i_ifu_ilegl ,
input alu_cmt_i_bjp_prdt,// The predicted ture/false
input alu_cmt_i_bjp_rslv,// The resolved ture/false
// The AGU Exception
input alu_cmt_i_misalgn, // The misalign exception generated
input alu_cmt_i_ld,
input alu_cmt_i_stamo,
input alu_cmt_i_buserr , // The bus-error exception generated
input [`E203_ADDR_SIZE-1:0]alu_cmt_i_badaddr,
output [`E203_ADDR_SIZE-1:0] cmt_badaddr,
output cmt_badaddr_ena,
output [`E203_PC_SIZE-1:0] cmt_epc,
output cmt_epc_ena,
output [`E203_XLEN-1:0] cmt_cause,
output cmt_cause_ena,
output cmt_instret_ena,
output cmt_status_ena,
output [`E203_PC_SIZE-1:0] cmt_dpc,
output cmt_dpc_ena,
output [3-1:0] cmt_dcause,
output cmt_dcause_ena,
output cmt_mret_ena,
input [`E203_PC_SIZE-1:0] csr_epc_r,
input [`E203_PC_SIZE-1:0] csr_dpc_r,
input [`E203_XLEN-1:0] csr_mtvec_r,
input dbg_mode,
input dbg_halt_r,
input dbg_step_r,
input dbg_ebreakm_r,
input oitf_empty,
input u_mode,
input s_mode,
input h_mode,
input m_mode,
output longp_excp_i_ready,
input longp_excp_i_valid,
input longp_excp_i_ld,
input longp_excp_i_st,
input longp_excp_i_buserr , // The load/store bus-error exception generated
input [`E203_ADDR_SIZE-1:0]longp_excp_i_badaddr,
input longp_excp_i_insterr,
input [`E203_PC_SIZE-1:0] longp_excp_i_pc,
//////////////////////////////////////////////////////////////
// The Flush interface to IFU
//
// To save the gatecount, when we need to flush pipeline with new PC,
// we want to reuse the adder in IFU, so we will not pass flush-PC
// to IFU, instead, we pass the flush-pc-adder-op1/op2 to IFU
// and IFU will just use its adder to caculate the flush-pc-adder-result
//
output flush_pulse,
// To cut the combinational loop, we need this flush_req from non-alu source to flush ALU pipeline (e.g., MUL-div statemachine)
output flush_req,
input pipe_flush_ack,
output pipe_flush_req,
output [`E203_PC_SIZE-1:0] pipe_flush_add_op1,
output [`E203_PC_SIZE-1:0] pipe_flush_add_op2,
`ifdef E203_TIMING_BOOST//}
output [`E203_PC_SIZE-1:0] pipe_flush_pc,
`endif//}
input clk,
input rst_n
);
wire alu_brchmis_flush_ack;
wire alu_brchmis_flush_req;
wire [`E203_PC_SIZE-1:0] alu_brchmis_flush_add_op1;
wire [`E203_PC_SIZE-1:0] alu_brchmis_flush_add_op2;
`ifdef E203_TIMING_BOOST//}
wire [`E203_PC_SIZE-1:0] alu_brchmis_flush_pc;
`endif//}
wire alu_brchmis_cmt_i_ready;
wire cmt_dret_ena;
wire nonalu_excpirq_flush_req_raw;
e203_exu_branchslv u_e203_exu_branchslv(
.cmt_i_ready (alu_brchmis_cmt_i_ready ),
.cmt_i_valid (alu_cmt_i_valid ),
.cmt_i_rv32 (alu_cmt_i_rv32 ),
.cmt_i_bjp (alu_cmt_i_bjp ),
.cmt_i_fencei (alu_cmt_i_fencei ),
.cmt_i_mret (alu_cmt_i_mret ),
.cmt_i_dret (alu_cmt_i_dret ),
.cmt_i_bjp_prdt (alu_cmt_i_bjp_prdt),
.cmt_i_bjp_rslv (alu_cmt_i_bjp_rslv),
.cmt_i_pc (alu_cmt_i_pc ),
.cmt_i_imm (alu_cmt_i_imm ),
.cmt_mret_ena (cmt_mret_ena ),
.cmt_dret_ena (cmt_dret_ena ),
.cmt_fencei_ena (),
.csr_epc_r (csr_epc_r ),
.csr_dpc_r (csr_dpc_r ),
.nonalu_excpirq_flush_req_raw(nonalu_excpirq_flush_req_raw ),
.brchmis_flush_ack (alu_brchmis_flush_ack ),
.brchmis_flush_req (alu_brchmis_flush_req ),
.brchmis_flush_add_op1 (alu_brchmis_flush_add_op1),
.brchmis_flush_add_op2 (alu_brchmis_flush_add_op2),
`ifdef E203_TIMING_BOOST//}
.brchmis_flush_pc (alu_brchmis_flush_pc),
`endif//}
.clk (clk ),
.rst_n (rst_n)
);
wire excpirq_flush_ack;
wire excpirq_flush_req;
wire [`E203_PC_SIZE-1:0] excpirq_flush_add_op1;
wire [`E203_PC_SIZE-1:0] excpirq_flush_add_op2;
`ifdef E203_TIMING_BOOST//}
wire [`E203_PC_SIZE-1:0] excpirq_flush_pc;
`endif//}
wire [`E203_XLEN-1:0] excpirq_cause;
wire alu_excp_cmt_i_ready;
wire cmt_ena;
e203_exu_excp u_e203_exu_excp(
.commit_trap (commit_trap ),
.core_wfi (core_wfi ),
.wfi_halt_ifu_req (wfi_halt_ifu_req),
.wfi_halt_exu_req (wfi_halt_exu_req),
.wfi_halt_ifu_ack (wfi_halt_ifu_ack),
.wfi_halt_exu_ack (wfi_halt_exu_ack),
.cmt_badaddr (cmt_badaddr ),
.cmt_badaddr_ena (cmt_badaddr_ena),
.cmt_epc (cmt_epc ),
.cmt_epc_ena (cmt_epc_ena ),
.cmt_cause (cmt_cause ),
.cmt_cause_ena (cmt_cause_ena ),
.cmt_status_ena (cmt_status_ena ),
.cmt_dpc (cmt_dpc ),
.cmt_dpc_ena (cmt_dpc_ena ),
.cmt_dcause (cmt_dcause ),
.cmt_dcause_ena (cmt_dcause_ena ),
.cmt_dret_ena (cmt_dret_ena ),
.cmt_ena (cmt_ena ),
.alu_excp_i_valid (alu_cmt_i_valid ),
.alu_excp_i_ready (alu_excp_cmt_i_ready ),
.alu_excp_i_misalgn (alu_cmt_i_misalgn),
.alu_excp_i_ld (alu_cmt_i_ld ),
.alu_excp_i_stamo (alu_cmt_i_stamo ),
.alu_excp_i_buserr (alu_cmt_i_buserr ),
.alu_excp_i_pc (alu_cmt_i_pc ),
.alu_excp_i_instr (alu_cmt_i_instr ),
.alu_excp_i_pc_vld (alu_cmt_i_pc_vld ),
.alu_excp_i_badaddr (alu_cmt_i_badaddr ),
.alu_excp_i_ecall (alu_cmt_i_ecall ),
.alu_excp_i_ebreak (alu_cmt_i_ebreak ),
.alu_excp_i_wfi (alu_cmt_i_wfi ),
.alu_excp_i_ifu_misalgn(alu_cmt_i_ifu_misalgn),
.alu_excp_i_ifu_buserr (alu_cmt_i_ifu_buserr ),
.alu_excp_i_ifu_ilegl (alu_cmt_i_ifu_ilegl ),
.longp_excp_i_ready (longp_excp_i_ready ),
.longp_excp_i_valid (longp_excp_i_valid ),
.longp_excp_i_ld (longp_excp_i_ld ),
.longp_excp_i_st (longp_excp_i_st ),
.longp_excp_i_buserr (longp_excp_i_buserr ),
.longp_excp_i_badaddr (longp_excp_i_badaddr),
.longp_excp_i_insterr (longp_excp_i_insterr),
.longp_excp_i_pc (longp_excp_i_pc ),
.csr_mtvec_r (csr_mtvec_r ),
.dbg_irq_r (dbg_irq_r),
.lcl_irq_r (lcl_irq_r),
.ext_irq_r (ext_irq_r),
.sft_irq_r (sft_irq_r),
.tmr_irq_r (tmr_irq_r),
.status_mie_r (status_mie_r),
.mtie_r (mtie_r ),
.msie_r (msie_r ),
.meie_r (meie_r ),
.dbg_mode (dbg_mode),
.dbg_halt_r (dbg_halt_r),
.dbg_step_r (dbg_step_r),
.dbg_ebreakm_r (dbg_ebreakm_r),
.oitf_empty (oitf_empty),
.u_mode (u_mode),
.s_mode (s_mode),
.h_mode (h_mode),
.m_mode (m_mode),
.excpirq_flush_ack (excpirq_flush_ack ),
.excpirq_flush_req (excpirq_flush_req ),
.nonalu_excpirq_flush_req_raw (nonalu_excpirq_flush_req_raw ),
.excpirq_flush_add_op1 (excpirq_flush_add_op1),
.excpirq_flush_add_op2 (excpirq_flush_add_op2),
`ifdef E203_TIMING_BOOST//}
.excpirq_flush_pc (excpirq_flush_pc),
`endif//}
.excp_active (excp_active),
.amo_wait (amo_wait),
.clk (clk ),
.rst_n (rst_n)
);
assign excpirq_flush_ack = pipe_flush_ack;
assign alu_brchmis_flush_ack = pipe_flush_ack;
assign pipe_flush_req = excpirq_flush_req | alu_brchmis_flush_req;
assign alu_cmt_i_ready = alu_excp_cmt_i_ready & alu_brchmis_cmt_i_ready;
assign pipe_flush_add_op1 = excpirq_flush_req ? excpirq_flush_add_op1 : alu_brchmis_flush_add_op1;
assign pipe_flush_add_op2 = excpirq_flush_req ? excpirq_flush_add_op2 : alu_brchmis_flush_add_op2;
`ifdef E203_TIMING_BOOST//}
assign pipe_flush_pc = excpirq_flush_req ? excpirq_flush_pc : alu_brchmis_flush_pc;
`endif//}
assign cmt_ena = alu_cmt_i_valid & alu_cmt_i_ready;
assign cmt_instret_ena = cmt_ena & (~alu_brchmis_flush_req);
// Generate the signal as the real-commit enable (non-flush)
assign nonflush_cmt_ena = cmt_ena & (~pipe_flush_req);
assign flush_pulse = pipe_flush_ack & pipe_flush_req;
assign flush_req = nonalu_excpirq_flush_req_raw;
assign commit_mret = cmt_mret_ena;
`ifndef FPGA_SOURCE//{
`ifndef DISABLE_SV_ASSERTION//{
//synopsys translate_off
`ifndef E203_HAS_LOCKSTEP//{
CHECK_1HOT_FLUSH_HALT:
assert property (@(posedge clk) disable iff (~rst_n)
($onehot0({wfi_halt_ifu_req,pipe_flush_req}))
)
else $fatal ("\n Error: Oops, detected non-onehot0 value for halt and flush req!!! This should never happen. \n");
`endif//}
//synopsys translate_on
`endif//}
`endif//}
endmodule |
module sirv_AsyncResetRegVec_129(
input clock,
input reset,
input [19:0] io_d,
output [19:0] io_q,
input io_en
);
wire reg_0_rst;
wire reg_0_clk;
wire reg_0_en;
wire reg_0_q;
wire reg_0_d;
wire reg_1_rst;
wire reg_1_clk;
wire reg_1_en;
wire reg_1_q;
wire reg_1_d;
wire reg_2_rst;
wire reg_2_clk;
wire reg_2_en;
wire reg_2_q;
wire reg_2_d;
wire reg_3_rst;
wire reg_3_clk;
wire reg_3_en;
wire reg_3_q;
wire reg_3_d;
wire reg_4_rst;
wire reg_4_clk;
wire reg_4_en;
wire reg_4_q;
wire reg_4_d;
wire reg_5_rst;
wire reg_5_clk;
wire reg_5_en;
wire reg_5_q;
wire reg_5_d;
wire reg_6_rst;
wire reg_6_clk;
wire reg_6_en;
wire reg_6_q;
wire reg_6_d;
wire reg_7_rst;
wire reg_7_clk;
wire reg_7_en;
wire reg_7_q;
wire reg_7_d;
wire reg_8_rst;
wire reg_8_clk;
wire reg_8_en;
wire reg_8_q;
wire reg_8_d;
wire reg_9_rst;
wire reg_9_clk;
wire reg_9_en;
wire reg_9_q;
wire reg_9_d;
wire reg_10_rst;
wire reg_10_clk;
wire reg_10_en;
wire reg_10_q;
wire reg_10_d;
wire reg_11_rst;
wire reg_11_clk;
wire reg_11_en;
wire reg_11_q;
wire reg_11_d;
wire reg_12_rst;
wire reg_12_clk;
wire reg_12_en;
wire reg_12_q;
wire reg_12_d;
wire reg_13_rst;
wire reg_13_clk;
wire reg_13_en;
wire reg_13_q;
wire reg_13_d;
wire reg_14_rst;
wire reg_14_clk;
wire reg_14_en;
wire reg_14_q;
wire reg_14_d;
wire reg_15_rst;
wire reg_15_clk;
wire reg_15_en;
wire reg_15_q;
wire reg_15_d;
wire reg_16_rst;
wire reg_16_clk;
wire reg_16_en;
wire reg_16_q;
wire reg_16_d;
wire reg_17_rst;
wire reg_17_clk;
wire reg_17_en;
wire reg_17_q;
wire reg_17_d;
wire reg_18_rst;
wire reg_18_clk;
wire reg_18_en;
wire reg_18_q;
wire reg_18_d;
wire reg_19_rst;
wire reg_19_clk;
wire reg_19_en;
wire reg_19_q;
wire reg_19_d;
wire T_8;
wire T_9;
wire T_10;
wire T_11;
wire T_12;
wire T_13;
wire T_14;
wire T_15;
wire T_16;
wire T_17;
wire T_18;
wire T_19;
wire T_20;
wire T_21;
wire T_22;
wire T_23;
wire T_24;
wire T_25;
wire T_26;
wire T_27;
wire [1:0] T_28;
wire [1:0] T_29;
wire [2:0] T_30;
wire [4:0] T_31;
wire [1:0] T_32;
wire [1:0] T_33;
wire [2:0] T_34;
wire [4:0] T_35;
wire [9:0] T_36;
wire [1:0] T_37;
wire [1:0] T_38;
wire [2:0] T_39;
wire [4:0] T_40;
wire [1:0] T_41;
wire [1:0] T_42;
wire [2:0] T_43;
wire [4:0] T_44;
wire [9:0] T_45;
wire [19:0] T_46;
sirv_AsyncResetReg reg_0 (
.rst(reg_0_rst),
.clk(reg_0_clk),
.en(reg_0_en),
.q(reg_0_q),
.d(reg_0_d)
);
sirv_AsyncResetReg reg_1 (
.rst(reg_1_rst),
.clk(reg_1_clk),
.en(reg_1_en),
.q(reg_1_q),
.d(reg_1_d)
);
sirv_AsyncResetReg reg_2 (
.rst(reg_2_rst),
.clk(reg_2_clk),
.en(reg_2_en),
.q(reg_2_q),
.d(reg_2_d)
);
sirv_AsyncResetReg reg_3 (
.rst(reg_3_rst),
.clk(reg_3_clk),
.en(reg_3_en),
.q(reg_3_q),
.d(reg_3_d)
);
sirv_AsyncResetReg reg_4 (
.rst(reg_4_rst),
.clk(reg_4_clk),
.en(reg_4_en),
.q(reg_4_q),
.d(reg_4_d)
);
sirv_AsyncResetReg reg_5 (
.rst(reg_5_rst),
.clk(reg_5_clk),
.en(reg_5_en),
.q(reg_5_q),
.d(reg_5_d)
);
sirv_AsyncResetReg reg_6 (
.rst(reg_6_rst),
.clk(reg_6_clk),
.en(reg_6_en),
.q(reg_6_q),
.d(reg_6_d)
);
sirv_AsyncResetReg reg_7 (
.rst(reg_7_rst),
.clk(reg_7_clk),
.en(reg_7_en),
.q(reg_7_q),
.d(reg_7_d)
);
sirv_AsyncResetReg reg_8 (
.rst(reg_8_rst),
.clk(reg_8_clk),
.en(reg_8_en),
.q(reg_8_q),
.d(reg_8_d)
);
sirv_AsyncResetReg reg_9 (
.rst(reg_9_rst),
.clk(reg_9_clk),
.en(reg_9_en),
.q(reg_9_q),
.d(reg_9_d)
);
sirv_AsyncResetReg reg_10 (
.rst(reg_10_rst),
.clk(reg_10_clk),
.en(reg_10_en),
.q(reg_10_q),
.d(reg_10_d)
);
sirv_AsyncResetReg reg_11 (
.rst(reg_11_rst),
.clk(reg_11_clk),
.en(reg_11_en),
.q(reg_11_q),
.d(reg_11_d)
);
sirv_AsyncResetReg reg_12 (
.rst(reg_12_rst),
.clk(reg_12_clk),
.en(reg_12_en),
.q(reg_12_q),
.d(reg_12_d)
);
sirv_AsyncResetReg reg_13 (
.rst(reg_13_rst),
.clk(reg_13_clk),
.en(reg_13_en),
.q(reg_13_q),
.d(reg_13_d)
);
sirv_AsyncResetReg reg_14 (
.rst(reg_14_rst),
.clk(reg_14_clk),
.en(reg_14_en),
.q(reg_14_q),
.d(reg_14_d)
);
sirv_AsyncResetReg reg_15 (
.rst(reg_15_rst),
.clk(reg_15_clk),
.en(reg_15_en),
.q(reg_15_q),
.d(reg_15_d)
);
sirv_AsyncResetReg reg_16 (
.rst(reg_16_rst),
.clk(reg_16_clk),
.en(reg_16_en),
.q(reg_16_q),
.d(reg_16_d)
);
sirv_AsyncResetReg reg_17 (
.rst(reg_17_rst),
.clk(reg_17_clk),
.en(reg_17_en),
.q(reg_17_q),
.d(reg_17_d)
);
sirv_AsyncResetReg reg_18 (
.rst(reg_18_rst),
.clk(reg_18_clk),
.en(reg_18_en),
.q(reg_18_q),
.d(reg_18_d)
);
sirv_AsyncResetReg reg_19 (
.rst(reg_19_rst),
.clk(reg_19_clk),
.en(reg_19_en),
.q(reg_19_q),
.d(reg_19_d)
);
assign io_q = T_46;
assign reg_0_rst = reset;
assign reg_0_clk = clock;
assign reg_0_en = io_en;
assign reg_0_d = T_8;
assign reg_1_rst = reset;
assign reg_1_clk = clock;
assign reg_1_en = io_en;
assign reg_1_d = T_9;
assign reg_2_rst = reset;
assign reg_2_clk = clock;
assign reg_2_en = io_en;
assign reg_2_d = T_10;
assign reg_3_rst = reset;
assign reg_3_clk = clock;
assign reg_3_en = io_en;
assign reg_3_d = T_11;
assign reg_4_rst = reset;
assign reg_4_clk = clock;
assign reg_4_en = io_en;
assign reg_4_d = T_12;
assign reg_5_rst = reset;
assign reg_5_clk = clock;
assign reg_5_en = io_en;
assign reg_5_d = T_13;
assign reg_6_rst = reset;
assign reg_6_clk = clock;
assign reg_6_en = io_en;
assign reg_6_d = T_14;
assign reg_7_rst = reset;
assign reg_7_clk = clock;
assign reg_7_en = io_en;
assign reg_7_d = T_15;
assign reg_8_rst = reset;
assign reg_8_clk = clock;
assign reg_8_en = io_en;
assign reg_8_d = T_16;
assign reg_9_rst = reset;
assign reg_9_clk = clock;
assign reg_9_en = io_en;
assign reg_9_d = T_17;
assign reg_10_rst = reset;
assign reg_10_clk = clock;
assign reg_10_en = io_en;
assign reg_10_d = T_18;
assign reg_11_rst = reset;
assign reg_11_clk = clock;
assign reg_11_en = io_en;
assign reg_11_d = T_19;
assign reg_12_rst = reset;
assign reg_12_clk = clock;
assign reg_12_en = io_en;
assign reg_12_d = T_20;
assign reg_13_rst = reset;
assign reg_13_clk = clock;
assign reg_13_en = io_en;
assign reg_13_d = T_21;
assign reg_14_rst = reset;
assign reg_14_clk = clock;
assign reg_14_en = io_en;
assign reg_14_d = T_22;
assign reg_15_rst = reset;
assign reg_15_clk = clock;
assign reg_15_en = io_en;
assign reg_15_d = T_23;
assign reg_16_rst = reset;
assign reg_16_clk = clock;
assign reg_16_en = io_en;
assign reg_16_d = T_24;
assign reg_17_rst = reset;
assign reg_17_clk = clock;
assign reg_17_en = io_en;
assign reg_17_d = T_25;
assign reg_18_rst = reset;
assign reg_18_clk = clock;
assign reg_18_en = io_en;
assign reg_18_d = T_26;
assign reg_19_rst = reset;
assign reg_19_clk = clock;
assign reg_19_en = io_en;
assign reg_19_d = T_27;
assign T_8 = io_d[0];
assign T_9 = io_d[1];
assign T_10 = io_d[2];
assign T_11 = io_d[3];
assign T_12 = io_d[4];
assign T_13 = io_d[5];
assign T_14 = io_d[6];
assign T_15 = io_d[7];
assign T_16 = io_d[8];
assign T_17 = io_d[9];
assign T_18 = io_d[10];
assign T_19 = io_d[11];
assign T_20 = io_d[12];
assign T_21 = io_d[13];
assign T_22 = io_d[14];
assign T_23 = io_d[15];
assign T_24 = io_d[16];
assign T_25 = io_d[17];
assign T_26 = io_d[18];
assign T_27 = io_d[19];
assign T_28 = {reg_1_q,reg_0_q};
assign T_29 = {reg_4_q,reg_3_q};
assign T_30 = {T_29,reg_2_q};
assign T_31 = {T_30,T_28};
assign T_32 = {reg_6_q,reg_5_q};
assign T_33 = {reg_9_q,reg_8_q};
assign T_34 = {T_33,reg_7_q};
assign T_35 = {T_34,T_32};
assign T_36 = {T_35,T_31};
assign T_37 = {reg_11_q,reg_10_q};
assign T_38 = {reg_14_q,reg_13_q};
assign T_39 = {T_38,reg_12_q};
assign T_40 = {T_39,T_37};
assign T_41 = {reg_16_q,reg_15_q};
assign T_42 = {reg_19_q,reg_18_q};
assign T_43 = {T_42,reg_17_q};
assign T_44 = {T_43,T_41};
assign T_45 = {T_44,T_40};
assign T_46 = {T_45,T_36};
endmodule |
module e203_lsu(
input commit_mret,
input commit_trap,
input excp_active,
output lsu_active,
`ifdef E203_HAS_ITCM //{
input [`E203_ADDR_SIZE-1:0] itcm_region_indic,
`endif//}
`ifdef E203_HAS_DTCM //{
input [`E203_ADDR_SIZE-1:0] dtcm_region_indic,
`endif//}
//////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////
// The LSU Write-Back Interface
output lsu_o_valid, // Handshake valid
input lsu_o_ready, // Handshake ready
output [`E203_XLEN-1:0] lsu_o_wbck_wdat,
output [`E203_ITAG_WIDTH -1:0] lsu_o_wbck_itag,
output lsu_o_wbck_err ,
output lsu_o_cmt_ld,
output lsu_o_cmt_st,
output [`E203_ADDR_SIZE -1:0] lsu_o_cmt_badaddr,
output lsu_o_cmt_buserr , // The bus-error exception generated
//////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////
// The AGU ICB Interface to LSU-ctrl
// * Bus cmd channel
input agu_icb_cmd_valid, // Handshake valid
output agu_icb_cmd_ready, // Handshake ready
input [`E203_ADDR_SIZE-1:0] agu_icb_cmd_addr, // Bus transaction start addr
input agu_icb_cmd_read, // Read or write
input [`E203_XLEN-1:0] agu_icb_cmd_wdata,
input [`E203_XLEN/8-1:0] agu_icb_cmd_wmask,
input agu_icb_cmd_lock,
input agu_icb_cmd_excl,
input [1:0] agu_icb_cmd_size,
// Several additional side channel signals
// Indicate LSU-ctrl module to
// return the ICB response channel back to AGU
// this is only used by AMO or unaligned load/store 1st uop
// to return the response
input agu_icb_cmd_back2agu,
// Sign extension or not
input agu_icb_cmd_usign,
input [`E203_ITAG_WIDTH -1:0] agu_icb_cmd_itag,
// * Bus RSP channel
output agu_icb_rsp_valid, // Response valid
input agu_icb_rsp_ready, // Response ready
output agu_icb_rsp_err , // Response error
output agu_icb_rsp_excl_ok, // Response error
output [`E203_XLEN-1:0] agu_icb_rsp_rdata,
`ifdef E203_HAS_ITCM //{
//////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////
// The ICB Interface to ITCM
//
// * Bus cmd channel
output itcm_icb_cmd_valid,
input itcm_icb_cmd_ready,
output [`E203_ITCM_ADDR_WIDTH-1:0] itcm_icb_cmd_addr,
output itcm_icb_cmd_read,
output [`E203_XLEN-1:0] itcm_icb_cmd_wdata,
output [`E203_XLEN/8-1:0] itcm_icb_cmd_wmask,
output itcm_icb_cmd_lock,
output itcm_icb_cmd_excl,
output [1:0] itcm_icb_cmd_size,
//
// * Bus RSP channel
input itcm_icb_rsp_valid,
output itcm_icb_rsp_ready,
input itcm_icb_rsp_err ,
input itcm_icb_rsp_excl_ok ,
input [`E203_XLEN-1:0] itcm_icb_rsp_rdata,
`endif//}
`ifdef E203_HAS_DTCM //{
//////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////
// The ICB Interface to DTCM
//
// * Bus cmd channel
output dtcm_icb_cmd_valid,
input dtcm_icb_cmd_ready,
output [`E203_DTCM_ADDR_WIDTH-1:0] dtcm_icb_cmd_addr,
output dtcm_icb_cmd_read,
output [`E203_XLEN-1:0] dtcm_icb_cmd_wdata,
output [`E203_XLEN/8-1:0] dtcm_icb_cmd_wmask,
output dtcm_icb_cmd_lock,
output dtcm_icb_cmd_excl,
output [1:0] dtcm_icb_cmd_size,
//
// * Bus RSP channel
input dtcm_icb_rsp_valid,
output dtcm_icb_rsp_ready,
input dtcm_icb_rsp_err ,
input dtcm_icb_rsp_excl_ok ,
input [`E203_XLEN-1:0] dtcm_icb_rsp_rdata,
`endif//}
//////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////
// The ICB Interface to BIU
//
// * Bus cmd channel
output biu_icb_cmd_valid,
input biu_icb_cmd_ready,
output [`E203_ADDR_SIZE-1:0] biu_icb_cmd_addr,
output biu_icb_cmd_read,
output [`E203_XLEN-1:0] biu_icb_cmd_wdata,
output [`E203_XLEN/8-1:0] biu_icb_cmd_wmask,
output biu_icb_cmd_lock,
output biu_icb_cmd_excl,
output [1:0] biu_icb_cmd_size,
//
// * Bus RSP channel
input biu_icb_rsp_valid,
output biu_icb_rsp_ready,
input biu_icb_rsp_err ,
input biu_icb_rsp_excl_ok ,
input [`E203_XLEN-1:0] biu_icb_rsp_rdata,
input clk,
input rst_n
);
`ifdef E203_HAS_DCACHE //{
//////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////
// The ICB Interface to DCache
//
// * Bus cmd channel
wire dcache_icb_cmd_valid;
wire dcache_icb_cmd_ready;
wire [`E203_ADDR_SIZE-1:0] dcache_icb_cmd_addr;
wire dcache_icb_cmd_read;
wire [`E203_XLEN-1:0] dcache_icb_cmd_wdata;
wire [`E203_XLEN/8-1:0] dcache_icb_cmd_wmask;
wire dcache_icb_cmd_lock;
wire dcache_icb_cmd_excl;
wire [1:0] dcache_icb_cmd_size;
//
// * Bus RSP channel
wire dcache_icb_rsp_valid;
wire dcache_icb_rsp_ready;
wire dcache_icb_rsp_err ;
wire dcache_icb_rsp_excl_ok ;
wire [`E203_XLEN-1:0] dcache_icb_rsp_rdata;
`endif//}
wire lsu_ctrl_active;
e203_lsu_ctrl u_e203_lsu_ctrl(
.commit_mret (commit_mret),
.commit_trap (commit_trap),
.lsu_ctrl_active (lsu_ctrl_active),
`ifdef E203_HAS_ITCM //{
.itcm_region_indic (itcm_region_indic),
`endif//}
`ifdef E203_HAS_DTCM //{
.dtcm_region_indic (dtcm_region_indic),
`endif//}
.lsu_o_valid (lsu_o_valid ),
.lsu_o_ready (lsu_o_ready ),
.lsu_o_wbck_wdat (lsu_o_wbck_wdat),
.lsu_o_wbck_itag (lsu_o_wbck_itag),
.lsu_o_wbck_err (lsu_o_wbck_err ),
.lsu_o_cmt_buserr (lsu_o_cmt_buserr ),
.lsu_o_cmt_badaddr (lsu_o_cmt_badaddr ),
.lsu_o_cmt_ld (lsu_o_cmt_ld ),
.lsu_o_cmt_st (lsu_o_cmt_st ),
.agu_icb_cmd_valid (agu_icb_cmd_valid ),
.agu_icb_cmd_ready (agu_icb_cmd_ready ),
.agu_icb_cmd_addr (agu_icb_cmd_addr ),
.agu_icb_cmd_read (agu_icb_cmd_read ),
.agu_icb_cmd_wdata (agu_icb_cmd_wdata ),
.agu_icb_cmd_wmask (agu_icb_cmd_wmask ),
.agu_icb_cmd_lock (agu_icb_cmd_lock),
.agu_icb_cmd_excl (agu_icb_cmd_excl),
.agu_icb_cmd_size (agu_icb_cmd_size),
.agu_icb_cmd_back2agu (agu_icb_cmd_back2agu ),
.agu_icb_cmd_usign (agu_icb_cmd_usign),
.agu_icb_cmd_itag (agu_icb_cmd_itag),
.agu_icb_rsp_valid (agu_icb_rsp_valid ),
.agu_icb_rsp_ready (agu_icb_rsp_ready ),
.agu_icb_rsp_err (agu_icb_rsp_err ),
.agu_icb_rsp_excl_ok (agu_icb_rsp_excl_ok),
.agu_icb_rsp_rdata (agu_icb_rsp_rdata),
`ifndef E203_HAS_EAI
.eai_mem_holdup (1'b0),
.eai_icb_cmd_valid (1'b0),
.eai_icb_cmd_ready (),
.eai_icb_cmd_addr (`E203_ADDR_SIZE'b0 ),
.eai_icb_cmd_read (1'b0 ),
.eai_icb_cmd_wdata (`E203_XLEN'b0),
.eai_icb_cmd_wmask ({`E203_XLEN/8{1'b0}}),
.eai_icb_cmd_lock (1'b0),
.eai_icb_cmd_excl (1'b0),
.eai_icb_cmd_size (2'b0),
.eai_icb_rsp_valid (),
.eai_icb_rsp_ready (1'b0),
.eai_icb_rsp_err (),
.eai_icb_rsp_excl_ok (),
.eai_icb_rsp_rdata (),
`endif
`ifdef E203_HAS_DCACHE
.dcache_icb_cmd_valid (dcache_icb_cmd_valid),
.dcache_icb_cmd_ready (dcache_icb_cmd_ready),
.dcache_icb_cmd_addr (dcache_icb_cmd_addr ),
.dcache_icb_cmd_read (dcache_icb_cmd_read ),
.dcache_icb_cmd_wdata (dcache_icb_cmd_wdata),
.dcache_icb_cmd_wmask (dcache_icb_cmd_wmask),
.dcache_icb_cmd_lock (dcache_icb_cmd_lock),
.dcache_icb_cmd_excl (dcache_icb_cmd_excl),
.dcache_icb_cmd_size (dcache_icb_cmd_size),
.dcache_icb_rsp_valid (dcache_icb_rsp_valid),
.dcache_icb_rsp_ready (dcache_icb_rsp_ready),
.dcache_icb_rsp_err (dcache_icb_rsp_err ),
.dcache_icb_rsp_excl_ok(dcache_icb_rsp_excl_ok ),
.dcache_icb_rsp_rdata (dcache_icb_rsp_rdata),
`endif
`ifdef E203_HAS_DTCM
.dtcm_icb_cmd_valid (dtcm_icb_cmd_valid),
.dtcm_icb_cmd_ready (dtcm_icb_cmd_ready),
.dtcm_icb_cmd_addr (dtcm_icb_cmd_addr ),
.dtcm_icb_cmd_read (dtcm_icb_cmd_read ),
.dtcm_icb_cmd_wdata (dtcm_icb_cmd_wdata),
.dtcm_icb_cmd_wmask (dtcm_icb_cmd_wmask),
.dtcm_icb_cmd_lock (dtcm_icb_cmd_lock),
.dtcm_icb_cmd_excl (dtcm_icb_cmd_excl),
.dtcm_icb_cmd_size (dtcm_icb_cmd_size),
.dtcm_icb_rsp_valid (dtcm_icb_rsp_valid),
.dtcm_icb_rsp_ready (dtcm_icb_rsp_ready),
.dtcm_icb_rsp_err (dtcm_icb_rsp_err ),
.dtcm_icb_rsp_excl_ok (dtcm_icb_rsp_excl_ok ),
.dtcm_icb_rsp_rdata (dtcm_icb_rsp_rdata),
`endif
`ifdef E203_HAS_ITCM
.itcm_icb_cmd_valid (itcm_icb_cmd_valid),
.itcm_icb_cmd_ready (itcm_icb_cmd_ready),
.itcm_icb_cmd_addr (itcm_icb_cmd_addr ),
.itcm_icb_cmd_read (itcm_icb_cmd_read ),
.itcm_icb_cmd_wdata (itcm_icb_cmd_wdata),
.itcm_icb_cmd_wmask (itcm_icb_cmd_wmask),
.itcm_icb_cmd_lock (itcm_icb_cmd_lock),
.itcm_icb_cmd_excl (itcm_icb_cmd_excl),
.itcm_icb_cmd_size (itcm_icb_cmd_size),
.itcm_icb_rsp_valid (itcm_icb_rsp_valid),
.itcm_icb_rsp_ready (itcm_icb_rsp_ready),
.itcm_icb_rsp_err (itcm_icb_rsp_err ),
.itcm_icb_rsp_excl_ok (itcm_icb_rsp_excl_ok ),
.itcm_icb_rsp_rdata (itcm_icb_rsp_rdata),
`endif
.biu_icb_cmd_valid (biu_icb_cmd_valid),
.biu_icb_cmd_ready (biu_icb_cmd_ready),
.biu_icb_cmd_addr (biu_icb_cmd_addr ),
.biu_icb_cmd_read (biu_icb_cmd_read ),
.biu_icb_cmd_wdata (biu_icb_cmd_wdata),
.biu_icb_cmd_wmask (biu_icb_cmd_wmask),
.biu_icb_cmd_lock (biu_icb_cmd_lock),
.biu_icb_cmd_excl (biu_icb_cmd_excl),
.biu_icb_cmd_size (biu_icb_cmd_size),
.biu_icb_rsp_valid (biu_icb_rsp_valid),
.biu_icb_rsp_ready (biu_icb_rsp_ready),
.biu_icb_rsp_err (biu_icb_rsp_err ),
.biu_icb_rsp_excl_ok (biu_icb_rsp_excl_ok ),
.biu_icb_rsp_rdata (biu_icb_rsp_rdata),
.clk (clk),
.rst_n (rst_n)
);
assign lsu_active = lsu_ctrl_active
// When interrupts comes, need to update the exclusive monitor
// so also need to turn on the clock
| excp_active;
endmodule |
module e203_exu_longpwbck(
//////////////////////////////////////////////////////////////
// The LSU Write-Back Interface
input lsu_wbck_i_valid, // Handshake valid
output lsu_wbck_i_ready, // Handshake ready
input [`E203_XLEN-1:0] lsu_wbck_i_wdat,
input [`E203_ITAG_WIDTH -1:0] lsu_wbck_i_itag,
input lsu_wbck_i_err , // The error exception generated
input lsu_cmt_i_buserr ,
input [`E203_ADDR_SIZE -1:0] lsu_cmt_i_badaddr,
input lsu_cmt_i_ld,
input lsu_cmt_i_st,
//////////////////////////////////////////////////////////////
// The Long pipe instruction Wback interface to final wbck module
output longp_wbck_o_valid, // Handshake valid
input longp_wbck_o_ready, // Handshake ready
output [`E203_FLEN-1:0] longp_wbck_o_wdat,
output [5-1:0] longp_wbck_o_flags,
output [`E203_RFIDX_WIDTH -1:0] longp_wbck_o_rdidx,
output longp_wbck_o_rdfpu,
//
// The Long pipe instruction Exception interface to commit stage
output longp_excp_o_valid,
input longp_excp_o_ready,
output longp_excp_o_insterr,
output longp_excp_o_ld,
output longp_excp_o_st,
output longp_excp_o_buserr , // The load/store bus-error exception generated
output [`E203_ADDR_SIZE-1:0] longp_excp_o_badaddr,
output [`E203_PC_SIZE -1:0] longp_excp_o_pc,
//
//The itag of toppest entry of OITF
input oitf_empty,
input [`E203_ITAG_WIDTH -1:0] oitf_ret_ptr,
input [`E203_RFIDX_WIDTH-1:0] oitf_ret_rdidx,
input [`E203_PC_SIZE-1:0] oitf_ret_pc,
input oitf_ret_rdwen,
input oitf_ret_rdfpu,
output oitf_ret_ena,
input clk,
input rst_n
);
// The Long-pipe instruction can write-back only when it's itag
// is same as the itag of toppest entry of OITF
wire wbck_ready4lsu = (lsu_wbck_i_itag == oitf_ret_ptr) & (~oitf_empty);
wire wbck_sel_lsu = lsu_wbck_i_valid & wbck_ready4lsu;
//assign longp_excp_o_ld = wbck_sel_lsu & lsu_cmt_i_ld;
//assign longp_excp_o_st = wbck_sel_lsu & lsu_cmt_i_st;
//assign longp_excp_o_buserr = wbck_sel_lsu & lsu_cmt_i_buserr;
//assign longp_excp_o_badaddr = wbck_sel_lsu ? lsu_cmt_i_badaddr : `E203_ADDR_SIZE'b0;
assign {
longp_excp_o_insterr
,longp_excp_o_ld
,longp_excp_o_st
,longp_excp_o_buserr
,longp_excp_o_badaddr } =
({`E203_ADDR_SIZE+4{wbck_sel_lsu}} &
{
1'b0,
lsu_cmt_i_ld,
lsu_cmt_i_st,
lsu_cmt_i_buserr,
lsu_cmt_i_badaddr
})
;
//////////////////////////////////////////////////////////////
// The Final arbitrated Write-Back Interface
wire wbck_i_ready;
wire wbck_i_valid;
wire [`E203_FLEN-1:0] wbck_i_wdat;
wire [5-1:0] wbck_i_flags;
wire [`E203_RFIDX_WIDTH-1:0] wbck_i_rdidx;
wire [`E203_PC_SIZE-1:0] wbck_i_pc;
wire wbck_i_rdwen;
wire wbck_i_rdfpu;
wire wbck_i_err ;
assign lsu_wbck_i_ready = wbck_ready4lsu & wbck_i_ready;
assign wbck_i_valid = ({1{wbck_sel_lsu}} & lsu_wbck_i_valid)
;
`ifdef E203_FLEN_IS_32 //{
wire [`E203_FLEN-1:0] lsu_wbck_i_wdat_exd = lsu_wbck_i_wdat;
`else//}{
wire [`E203_FLEN-1:0] lsu_wbck_i_wdat_exd = {{`E203_FLEN-`E203_XLEN{1'b0}},lsu_wbck_i_wdat};
`endif//}
assign wbck_i_wdat = ({`E203_FLEN{wbck_sel_lsu}} & lsu_wbck_i_wdat_exd )
;
assign wbck_i_flags = 5'b0
;
assign wbck_i_err = wbck_sel_lsu & lsu_wbck_i_err
;
assign wbck_i_pc = oitf_ret_pc;
assign wbck_i_rdidx = oitf_ret_rdidx;
assign wbck_i_rdwen = oitf_ret_rdwen;
assign wbck_i_rdfpu = oitf_ret_rdfpu;
// If the instruction have no error and it have the rdwen, then it need to
// write back into regfile, otherwise, it does not need to write regfile
wire need_wbck = wbck_i_rdwen & (~wbck_i_err);
// If the long pipe instruction have error result, then it need to handshake
// with the commit module.
wire need_excp = wbck_i_err;
assign wbck_i_ready =
(need_wbck ? longp_wbck_o_ready : 1'b1)
& (need_excp ? longp_excp_o_ready : 1'b1);
assign longp_wbck_o_valid = need_wbck & wbck_i_valid & (need_excp ? longp_excp_o_ready : 1'b1);
assign longp_excp_o_valid = need_excp & wbck_i_valid & (need_wbck ? longp_wbck_o_ready : 1'b1);
assign longp_wbck_o_wdat = wbck_i_wdat ;
assign longp_wbck_o_flags = wbck_i_flags ;
assign longp_wbck_o_rdfpu = wbck_i_rdfpu ;
assign longp_wbck_o_rdidx = wbck_i_rdidx;
assign longp_excp_o_pc = wbck_i_pc;
assign oitf_ret_ena = wbck_i_valid & wbck_i_ready;
endmodule |
module sirv_flash_qspi_top(
input clk,
input rst_n,
input i_icb_cmd_valid,
output i_icb_cmd_ready,
input [32-1:0] i_icb_cmd_addr,
input i_icb_cmd_read,
input [32-1:0] i_icb_cmd_wdata,
output i_icb_rsp_valid,
input i_icb_rsp_ready,
output [32-1:0] i_icb_rsp_rdata,
input f_icb_cmd_valid,
output f_icb_cmd_ready,
input [32-1:0] f_icb_cmd_addr,
input f_icb_cmd_read,
input [32-1:0] f_icb_cmd_wdata,
output f_icb_rsp_valid,
input f_icb_rsp_ready,
output [32-1:0] f_icb_rsp_rdata,
output io_port_sck,
input io_port_dq_0_i,
output io_port_dq_0_o,
output io_port_dq_0_oe,
input io_port_dq_1_i,
output io_port_dq_1_o,
output io_port_dq_1_oe,
input io_port_dq_2_i,
output io_port_dq_2_o,
output io_port_dq_2_oe,
input io_port_dq_3_i,
output io_port_dq_3_o,
output io_port_dq_3_oe,
output io_port_cs_0,
output io_tl_i_0_0
);
wire io_tl_r_0_a_ready;
assign i_icb_cmd_ready = io_tl_r_0_a_ready;
wire io_tl_r_0_a_valid = i_icb_cmd_valid;
wire [2:0] io_tl_r_0_a_bits_opcode = i_icb_cmd_read ? 3'h4 : 3'h0;
wire [2:0] io_tl_r_0_a_bits_param = 3'b0;
wire [2:0] io_tl_r_0_a_bits_size = 3'd2;
wire [4:0] io_tl_r_0_a_bits_source = 5'b0;
wire [28:0] io_tl_r_0_a_bits_address = i_icb_cmd_addr[28:0];
wire [3:0] io_tl_r_0_a_bits_mask = 4'b1111;
wire [31:0] io_tl_r_0_a_bits_data = i_icb_cmd_wdata;
wire io_tl_r_0_d_ready = i_icb_rsp_ready;
wire [2:0] io_tl_r_0_d_bits_opcode;
wire [1:0] io_tl_r_0_d_bits_param;
wire [2:0] io_tl_r_0_d_bits_size;
wire [4:0] io_tl_r_0_d_bits_source;
wire io_tl_r_0_d_bits_sink;
wire [1:0] io_tl_r_0_d_bits_addr_lo;
wire [31:0] io_tl_r_0_d_bits_data;
wire io_tl_r_0_d_bits_error;
wire io_tl_r_0_d_valid;
assign i_icb_rsp_valid = io_tl_r_0_d_valid;
assign i_icb_rsp_rdata = io_tl_r_0_d_bits_data;
// Not used
wire io_tl_r_0_b_ready = 1'b0;
wire io_tl_r_0_b_valid;
wire [2:0] io_tl_r_0_b_bits_opcode;
wire [1:0] io_tl_r_0_b_bits_param;
wire [2:0] io_tl_r_0_b_bits_size;
wire [4:0] io_tl_r_0_b_bits_source;
wire [28:0] io_tl_r_0_b_bits_address;
wire [3:0] io_tl_r_0_b_bits_mask;
wire [31:0] io_tl_r_0_b_bits_data;
// Not used
wire io_tl_r_0_c_ready;
wire io_tl_r_0_c_valid = 1'b0;
wire [2:0] io_tl_r_0_c_bits_opcode = 3'b0;
wire [2:0] io_tl_r_0_c_bits_param = 3'b0;
wire [2:0] io_tl_r_0_c_bits_size = 3'd2;
wire [4:0] io_tl_r_0_c_bits_source = 5'b0;
wire [28:0] io_tl_r_0_c_bits_address = 29'b0;
wire [31:0] io_tl_r_0_c_bits_data = 32'b0;
wire io_tl_r_0_c_bits_error = 1'b0;
// Not used
wire io_tl_r_0_e_ready;
wire io_tl_r_0_e_valid = 1'b0;
wire io_tl_r_0_e_bits_sink = 1'b0;
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
wire io_tl_f_0_a_ready;
assign f_icb_cmd_ready = io_tl_f_0_a_ready;
wire io_tl_f_0_a_valid = f_icb_cmd_valid;
wire [2:0] io_tl_f_0_a_bits_opcode = f_icb_cmd_read ? 3'h4 : 3'h0;
wire [2:0] io_tl_f_0_a_bits_param = 3'b0;
wire [2:0] io_tl_f_0_a_bits_size = 3'd2;
wire [1:0] io_tl_f_0_a_bits_source = 2'b0;
// We must force the address to be aligned to 32bits
wire [29:0] io_tl_f_0_a_bits_address = {f_icb_cmd_addr[29:2],2'b0};
wire [3:0] io_tl_f_0_a_bits_mask = 4'b1111;
wire [31:0] io_tl_f_0_a_bits_data = f_icb_cmd_wdata;
wire io_tl_f_0_d_ready = f_icb_rsp_ready;
wire [2:0] io_tl_f_0_d_bits_opcode;
wire [1:0] io_tl_f_0_d_bits_param;
wire [2:0] io_tl_f_0_d_bits_size;
wire [1:0] io_tl_f_0_d_bits_source;
wire io_tl_f_0_d_bits_sink;
wire [1:0] io_tl_f_0_d_bits_addr_lo;
wire [31:0] io_tl_f_0_d_bits_data;
wire io_tl_f_0_d_bits_error;
wire io_tl_f_0_d_valid;
assign f_icb_rsp_valid = io_tl_f_0_d_valid;
assign f_icb_rsp_rdata = io_tl_f_0_d_bits_data;
// Not used
wire io_tl_f_0_b_ready = 1'b0;
wire io_tl_f_0_b_valid;
wire [2:0] io_tl_f_0_b_bits_opcode;
wire [1:0] io_tl_f_0_b_bits_param;
wire [2:0] io_tl_f_0_b_bits_size;
wire [1:0] io_tl_f_0_b_bits_source;
wire [29:0] io_tl_f_0_b_bits_address;
wire [3:0] io_tl_f_0_b_bits_mask;
wire [31:0] io_tl_f_0_b_bits_data;
// Not used
wire io_tl_f_0_c_ready;
wire io_tl_f_0_c_valid = 1'b0;
wire [2:0] io_tl_f_0_c_bits_opcode = 3'b0;
wire [2:0] io_tl_f_0_c_bits_param = 3'b0;
wire [2:0] io_tl_f_0_c_bits_size = 3'd2;
wire [1:0] io_tl_f_0_c_bits_source = 2'b0;
wire [29:0] io_tl_f_0_c_bits_address = 30'b0;
wire [31:0] io_tl_f_0_c_bits_data = 32'b0;
wire io_tl_f_0_c_bits_error = 1'b0;
// Not used
wire io_tl_f_0_e_ready;
wire io_tl_f_0_e_valid = 1'b0;
wire io_tl_f_0_e_bits_sink = 1'b0;
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
wire tl_f_0_a_ready;
wire tl_f_0_a_valid;
wire [2:0] tl_f_0_a_bits_opcode;
wire [2:0] tl_f_0_a_bits_param;
wire [2:0] tl_f_0_a_bits_size;
wire [6:0] tl_f_0_a_bits_source;
wire [29:0] tl_f_0_a_bits_address;
wire tl_f_0_a_bits_mask;
wire [7:0] tl_f_0_a_bits_data;
wire io_in_0_a_ready;
wire io_in_0_a_valid;
wire [2:0] io_in_0_a_bits_opcode;
wire [2:0] io_in_0_a_bits_param;
wire [2:0] io_in_0_a_bits_size;
wire [1:0] io_in_0_a_bits_source;
wire [29:0] io_in_0_a_bits_address;
wire io_in_0_a_bits_mask;
wire [7:0] io_in_0_a_bits_data;
wire io_in_0_b_ready;
wire io_in_0_b_valid;
wire [2:0] io_in_0_b_bits_opcode;
wire [1:0] io_in_0_b_bits_param;
wire [2:0] io_in_0_b_bits_size;
wire [1:0] io_in_0_b_bits_source;
wire [29:0] io_in_0_b_bits_address;
wire io_in_0_b_bits_mask;
wire [7:0] io_in_0_b_bits_data;
wire io_in_0_c_ready;
wire io_in_0_c_valid;
wire [2:0] io_in_0_c_bits_opcode;
wire [2:0] io_in_0_c_bits_param;
wire [2:0] io_in_0_c_bits_size;
wire [1:0] io_in_0_c_bits_source;
wire [29:0] io_in_0_c_bits_address;
wire [7:0] io_in_0_c_bits_data;
wire io_in_0_c_bits_error;
wire io_in_0_d_ready;
wire io_in_0_d_valid;
wire [2:0] io_in_0_d_bits_opcode;
wire [1:0] io_in_0_d_bits_param;
wire [2:0] io_in_0_d_bits_size;
wire [1:0] io_in_0_d_bits_source;
wire io_in_0_d_bits_sink;
wire io_in_0_d_bits_addr_lo;
wire [7:0] io_in_0_d_bits_data;
wire io_in_0_d_bits_error;
wire io_in_0_e_ready;
wire io_in_0_e_valid;
wire io_in_0_e_bits_sink;
wire io_out_0_a_ready;
wire io_out_0_a_valid;
wire [2:0] io_out_0_a_bits_opcode;
wire [2:0] io_out_0_a_bits_param;
wire [2:0] io_out_0_a_bits_size;
wire [6:0] io_out_0_a_bits_source;
wire [29:0] io_out_0_a_bits_address;
wire io_out_0_a_bits_mask;
wire [7:0] io_out_0_a_bits_data;
wire io_out_0_b_ready;
wire io_out_0_b_valid;
wire [2:0] io_out_0_b_bits_opcode;
wire [1:0] io_out_0_b_bits_param;
wire [2:0] io_out_0_b_bits_size;
wire [6:0] io_out_0_b_bits_source;
wire [29:0] io_out_0_b_bits_address;
wire io_out_0_b_bits_mask;
wire [7:0] io_out_0_b_bits_data;
wire io_out_0_c_ready;
wire io_out_0_c_valid;
wire [2:0] io_out_0_c_bits_opcode;
wire [2:0] io_out_0_c_bits_param;
wire [2:0] io_out_0_c_bits_size;
wire [6:0] io_out_0_c_bits_source;
wire [29:0] io_out_0_c_bits_address;
wire [7:0] io_out_0_c_bits_data;
wire io_out_0_c_bits_error;
wire io_out_0_d_ready;
wire io_out_0_d_valid;
wire [2:0] io_out_0_d_bits_opcode;
wire [1:0] io_out_0_d_bits_param;
wire [2:0] io_out_0_d_bits_size;
wire [6:0] io_out_0_d_bits_source;
wire io_out_0_d_bits_sink;
wire io_out_0_d_bits_addr_lo;
wire [7:0] io_out_0_d_bits_data;
wire io_out_0_d_bits_error;
wire io_out_0_e_ready;
wire io_out_0_e_valid;
wire io_out_0_e_bits_sink;
sirv_tlwidthwidget_qspi qspi_TLWidthWidget (
.clock(clk),
.reset(~rst_n),
.io_in_0_a_ready(io_tl_f_0_a_ready),
.io_in_0_a_valid(io_tl_f_0_a_valid),
.io_in_0_a_bits_opcode(io_tl_f_0_a_bits_opcode),
.io_in_0_a_bits_param(io_tl_f_0_a_bits_param),
.io_in_0_a_bits_size(io_tl_f_0_a_bits_size),
.io_in_0_a_bits_source(io_tl_f_0_a_bits_source),
.io_in_0_a_bits_address(io_tl_f_0_a_bits_address),
.io_in_0_a_bits_mask(io_tl_f_0_a_bits_mask),
.io_in_0_a_bits_data(io_tl_f_0_a_bits_data),
.io_in_0_b_ready(io_tl_f_0_b_ready),
.io_in_0_b_valid(io_tl_f_0_b_valid),
.io_in_0_b_bits_opcode(io_tl_f_0_b_bits_opcode),
.io_in_0_b_bits_param(io_tl_f_0_b_bits_param),
.io_in_0_b_bits_size(io_tl_f_0_b_bits_size),
.io_in_0_b_bits_source(io_tl_f_0_b_bits_source),
.io_in_0_b_bits_address(io_tl_f_0_b_bits_address),
.io_in_0_b_bits_mask(io_tl_f_0_b_bits_mask),
.io_in_0_b_bits_data(io_tl_f_0_b_bits_data),
.io_in_0_c_ready(io_tl_f_0_c_ready),
.io_in_0_c_valid(io_tl_f_0_c_valid),
.io_in_0_c_bits_opcode(io_tl_f_0_c_bits_opcode),
.io_in_0_c_bits_param(io_tl_f_0_c_bits_param),
.io_in_0_c_bits_size(io_tl_f_0_c_bits_size),
.io_in_0_c_bits_source(io_tl_f_0_c_bits_source),
.io_in_0_c_bits_address(io_tl_f_0_c_bits_address),
.io_in_0_c_bits_data(io_tl_f_0_c_bits_data),
.io_in_0_c_bits_error(io_tl_f_0_c_bits_error),
.io_in_0_d_ready(io_tl_f_0_d_ready),
.io_in_0_d_valid(io_tl_f_0_d_valid),
.io_in_0_d_bits_opcode(io_tl_f_0_d_bits_opcode),
.io_in_0_d_bits_param(io_tl_f_0_d_bits_param),
.io_in_0_d_bits_size(io_tl_f_0_d_bits_size),
.io_in_0_d_bits_source(io_tl_f_0_d_bits_source),
.io_in_0_d_bits_sink(io_tl_f_0_d_bits_sink),
.io_in_0_d_bits_addr_lo(io_tl_f_0_d_bits_addr_lo),
.io_in_0_d_bits_data(io_tl_f_0_d_bits_data),
.io_in_0_d_bits_error(io_tl_f_0_d_bits_error),
.io_in_0_e_ready(io_tl_f_0_e_ready),
.io_in_0_e_valid(io_tl_f_0_e_valid),
.io_in_0_e_bits_sink(io_tl_f_0_e_bits_sink),
.io_out_0_a_ready(io_in_0_a_ready),
.io_out_0_a_valid(io_in_0_a_valid),
.io_out_0_a_bits_opcode(io_in_0_a_bits_opcode),
.io_out_0_a_bits_param(io_in_0_a_bits_param),
.io_out_0_a_bits_size(io_in_0_a_bits_size),
.io_out_0_a_bits_source(io_in_0_a_bits_source),
.io_out_0_a_bits_address(io_in_0_a_bits_address),
.io_out_0_a_bits_mask(io_in_0_a_bits_mask),
.io_out_0_a_bits_data(io_in_0_a_bits_data),
.io_out_0_b_ready(io_in_0_b_ready),
.io_out_0_b_valid(io_in_0_b_valid),
.io_out_0_b_bits_opcode(io_in_0_b_bits_opcode),
.io_out_0_b_bits_param(io_in_0_b_bits_param),
.io_out_0_b_bits_size(io_in_0_b_bits_size),
.io_out_0_b_bits_source(io_in_0_b_bits_source),
.io_out_0_b_bits_address(io_in_0_b_bits_address),
.io_out_0_b_bits_mask(io_in_0_b_bits_mask),
.io_out_0_b_bits_data(io_in_0_b_bits_data),
.io_out_0_c_ready(io_in_0_c_ready),
.io_out_0_c_valid(io_in_0_c_valid),
.io_out_0_c_bits_opcode(io_in_0_c_bits_opcode),
.io_out_0_c_bits_param(io_in_0_c_bits_param),
.io_out_0_c_bits_size(io_in_0_c_bits_size),
.io_out_0_c_bits_source(io_in_0_c_bits_source),
.io_out_0_c_bits_address(io_in_0_c_bits_address),
.io_out_0_c_bits_data(io_in_0_c_bits_data),
.io_out_0_c_bits_error(io_in_0_c_bits_error),
.io_out_0_d_ready(io_in_0_d_ready),
.io_out_0_d_valid(io_in_0_d_valid),
.io_out_0_d_bits_opcode(io_in_0_d_bits_opcode),
.io_out_0_d_bits_param(io_in_0_d_bits_param),
.io_out_0_d_bits_size(io_in_0_d_bits_size),
.io_out_0_d_bits_source(io_in_0_d_bits_source),
.io_out_0_d_bits_sink(io_in_0_d_bits_sink),
.io_out_0_d_bits_addr_lo(io_in_0_d_bits_addr_lo),
.io_out_0_d_bits_data(io_in_0_d_bits_data),
.io_out_0_d_bits_error(io_in_0_d_bits_error),
.io_out_0_e_ready(io_in_0_e_ready),
.io_out_0_e_valid(io_in_0_e_valid),
.io_out_0_e_bits_sink(io_in_0_e_bits_sink)
);
sirv_tlfragmenter_qspi_1 qspi_TLFragmenter_1 (
.clock (clk ),
.reset (~rst_n),
.io_in_0_a_ready(io_in_0_a_ready),
.io_in_0_a_valid(io_in_0_a_valid),
.io_in_0_a_bits_opcode(io_in_0_a_bits_opcode),
.io_in_0_a_bits_param(io_in_0_a_bits_param),
.io_in_0_a_bits_size(io_in_0_a_bits_size),
.io_in_0_a_bits_source(io_in_0_a_bits_source),
.io_in_0_a_bits_address(io_in_0_a_bits_address),
.io_in_0_a_bits_mask(io_in_0_a_bits_mask),
.io_in_0_a_bits_data(io_in_0_a_bits_data),
.io_in_0_b_ready(io_in_0_b_ready),
.io_in_0_b_valid(io_in_0_b_valid),
.io_in_0_b_bits_opcode(io_in_0_b_bits_opcode),
.io_in_0_b_bits_param(io_in_0_b_bits_param),
.io_in_0_b_bits_size(io_in_0_b_bits_size),
.io_in_0_b_bits_source(io_in_0_b_bits_source),
.io_in_0_b_bits_address(io_in_0_b_bits_address),
.io_in_0_b_bits_mask(io_in_0_b_bits_mask),
.io_in_0_b_bits_data(io_in_0_b_bits_data),
.io_in_0_c_ready(io_in_0_c_ready),
.io_in_0_c_valid(io_in_0_c_valid),
.io_in_0_c_bits_opcode(io_in_0_c_bits_opcode),
.io_in_0_c_bits_param(io_in_0_c_bits_param),
.io_in_0_c_bits_size(io_in_0_c_bits_size),
.io_in_0_c_bits_source(io_in_0_c_bits_source),
.io_in_0_c_bits_address(io_in_0_c_bits_address),
.io_in_0_c_bits_data(io_in_0_c_bits_data),
.io_in_0_c_bits_error(io_in_0_c_bits_error),
.io_in_0_d_ready(io_in_0_d_ready),
.io_in_0_d_valid(io_in_0_d_valid),
.io_in_0_d_bits_opcode(io_in_0_d_bits_opcode),
.io_in_0_d_bits_param(io_in_0_d_bits_param),
.io_in_0_d_bits_size(io_in_0_d_bits_size),
.io_in_0_d_bits_source(io_in_0_d_bits_source),
.io_in_0_d_bits_sink(io_in_0_d_bits_sink),
.io_in_0_d_bits_addr_lo(io_in_0_d_bits_addr_lo),
.io_in_0_d_bits_data(io_in_0_d_bits_data),
.io_in_0_d_bits_error(io_in_0_d_bits_error),
.io_in_0_e_ready(io_in_0_e_ready),
.io_in_0_e_valid(io_in_0_e_valid),
.io_in_0_e_bits_sink(io_in_0_e_bits_sink),
.io_out_0_a_ready(io_out_0_a_ready),
.io_out_0_a_valid(io_out_0_a_valid),
.io_out_0_a_bits_opcode(io_out_0_a_bits_opcode),
.io_out_0_a_bits_param(io_out_0_a_bits_param),
.io_out_0_a_bits_size(io_out_0_a_bits_size),
.io_out_0_a_bits_source(io_out_0_a_bits_source),
.io_out_0_a_bits_address(io_out_0_a_bits_address),
.io_out_0_a_bits_mask(io_out_0_a_bits_mask),
.io_out_0_a_bits_data(io_out_0_a_bits_data),
.io_out_0_b_ready(io_out_0_b_ready),
.io_out_0_b_valid(io_out_0_b_valid),
.io_out_0_b_bits_opcode(io_out_0_b_bits_opcode),
.io_out_0_b_bits_param(io_out_0_b_bits_param),
.io_out_0_b_bits_size(io_out_0_b_bits_size),
.io_out_0_b_bits_source(io_out_0_b_bits_source),
.io_out_0_b_bits_address(io_out_0_b_bits_address),
.io_out_0_b_bits_mask(io_out_0_b_bits_mask),
.io_out_0_b_bits_data(io_out_0_b_bits_data),
.io_out_0_c_ready(io_out_0_c_ready),
.io_out_0_c_valid(io_out_0_c_valid),
.io_out_0_c_bits_opcode(io_out_0_c_bits_opcode),
.io_out_0_c_bits_param(io_out_0_c_bits_param),
.io_out_0_c_bits_size(io_out_0_c_bits_size),
.io_out_0_c_bits_source(io_out_0_c_bits_source),
.io_out_0_c_bits_address(io_out_0_c_bits_address),
.io_out_0_c_bits_data(io_out_0_c_bits_data),
.io_out_0_c_bits_error(io_out_0_c_bits_error),
.io_out_0_d_ready(io_out_0_d_ready),
.io_out_0_d_valid(io_out_0_d_valid),
.io_out_0_d_bits_opcode(io_out_0_d_bits_opcode),
.io_out_0_d_bits_param(io_out_0_d_bits_param),
.io_out_0_d_bits_size(io_out_0_d_bits_size),
.io_out_0_d_bits_source(io_out_0_d_bits_source),
.io_out_0_d_bits_sink(io_out_0_d_bits_sink),
.io_out_0_d_bits_addr_lo(io_out_0_d_bits_addr_lo),
.io_out_0_d_bits_data(io_out_0_d_bits_data),
.io_out_0_d_bits_error(io_out_0_d_bits_error),
.io_out_0_e_ready(io_out_0_e_ready),
.io_out_0_e_valid(io_out_0_e_valid),
.io_out_0_e_bits_sink(io_out_0_e_bits_sink)
);
sirv_flash_qspi u_sirv_flash_qspi(
.clock (clk ),
.reset (~rst_n ),
.io_tl_r_0_a_ready (io_tl_r_0_a_ready ),
.io_tl_r_0_a_valid (io_tl_r_0_a_valid ),
.io_tl_r_0_a_bits_opcode (io_tl_r_0_a_bits_opcode ),
.io_tl_r_0_a_bits_param (io_tl_r_0_a_bits_param ),
.io_tl_r_0_a_bits_size (io_tl_r_0_a_bits_size ),
.io_tl_r_0_a_bits_source (io_tl_r_0_a_bits_source ),
.io_tl_r_0_a_bits_address (io_tl_r_0_a_bits_address ),
.io_tl_r_0_a_bits_mask (io_tl_r_0_a_bits_mask ),
.io_tl_r_0_a_bits_data (io_tl_r_0_a_bits_data ),
.io_tl_r_0_b_ready (io_tl_r_0_b_ready ),
.io_tl_r_0_b_valid (io_tl_r_0_b_valid ),
.io_tl_r_0_b_bits_opcode (io_tl_r_0_b_bits_opcode ),
.io_tl_r_0_b_bits_param (io_tl_r_0_b_bits_param ),
.io_tl_r_0_b_bits_size (io_tl_r_0_b_bits_size ),
.io_tl_r_0_b_bits_source (io_tl_r_0_b_bits_source ),
.io_tl_r_0_b_bits_address (io_tl_r_0_b_bits_address ),
.io_tl_r_0_b_bits_mask (io_tl_r_0_b_bits_mask ),
.io_tl_r_0_b_bits_data (io_tl_r_0_b_bits_data ),
.io_tl_r_0_c_ready (io_tl_r_0_c_ready ),
.io_tl_r_0_c_valid (io_tl_r_0_c_valid ),
.io_tl_r_0_c_bits_opcode (io_tl_r_0_c_bits_opcode ),
.io_tl_r_0_c_bits_param (io_tl_r_0_c_bits_param ),
.io_tl_r_0_c_bits_size (io_tl_r_0_c_bits_size ),
.io_tl_r_0_c_bits_source (io_tl_r_0_c_bits_source ),
.io_tl_r_0_c_bits_address (io_tl_r_0_c_bits_address ),
.io_tl_r_0_c_bits_data (io_tl_r_0_c_bits_data ),
.io_tl_r_0_c_bits_error (io_tl_r_0_c_bits_error ),
.io_tl_r_0_d_ready (io_tl_r_0_d_ready ),
.io_tl_r_0_d_valid (io_tl_r_0_d_valid ),
.io_tl_r_0_d_bits_opcode (io_tl_r_0_d_bits_opcode ),
.io_tl_r_0_d_bits_param (io_tl_r_0_d_bits_param ),
.io_tl_r_0_d_bits_size (io_tl_r_0_d_bits_size ),
.io_tl_r_0_d_bits_source (io_tl_r_0_d_bits_source ),
.io_tl_r_0_d_bits_sink (io_tl_r_0_d_bits_sink ),
.io_tl_r_0_d_bits_addr_lo (io_tl_r_0_d_bits_addr_lo ),
.io_tl_r_0_d_bits_data (io_tl_r_0_d_bits_data ),
.io_tl_r_0_d_bits_error (io_tl_r_0_d_bits_error ),
.io_tl_r_0_e_ready (io_tl_r_0_e_ready ),
.io_tl_r_0_e_valid (io_tl_r_0_e_valid ),
.io_tl_r_0_e_bits_sink (io_tl_r_0_e_bits_sink ),
.io_tl_f_0_a_ready (io_out_0_a_ready ),
.io_tl_f_0_a_valid (io_out_0_a_valid ),
.io_tl_f_0_a_bits_opcode (io_out_0_a_bits_opcode ),
.io_tl_f_0_a_bits_param (io_out_0_a_bits_param ),
.io_tl_f_0_a_bits_size (io_out_0_a_bits_size ),
.io_tl_f_0_a_bits_source (io_out_0_a_bits_source ),
.io_tl_f_0_a_bits_address (io_out_0_a_bits_address ),
.io_tl_f_0_a_bits_mask (io_out_0_a_bits_mask ),
.io_tl_f_0_a_bits_data (io_out_0_a_bits_data ),
.io_tl_f_0_b_ready (io_out_0_b_ready ),
.io_tl_f_0_b_valid (io_out_0_b_valid ),
.io_tl_f_0_b_bits_opcode (io_out_0_b_bits_opcode ),
.io_tl_f_0_b_bits_param (io_out_0_b_bits_param ),
.io_tl_f_0_b_bits_size (io_out_0_b_bits_size ),
.io_tl_f_0_b_bits_source (io_out_0_b_bits_source ),
.io_tl_f_0_b_bits_address (io_out_0_b_bits_address ),
.io_tl_f_0_b_bits_mask (io_out_0_b_bits_mask ),
.io_tl_f_0_b_bits_data (io_out_0_b_bits_data ),
.io_tl_f_0_c_ready (io_out_0_c_ready ),
.io_tl_f_0_c_valid (io_out_0_c_valid ),
.io_tl_f_0_c_bits_opcode (io_out_0_c_bits_opcode ),
.io_tl_f_0_c_bits_param (io_out_0_c_bits_param ),
.io_tl_f_0_c_bits_size (io_out_0_c_bits_size ),
.io_tl_f_0_c_bits_source (io_out_0_c_bits_source ),
.io_tl_f_0_c_bits_address (io_out_0_c_bits_address ),
.io_tl_f_0_c_bits_data (io_out_0_c_bits_data ),
.io_tl_f_0_c_bits_error (io_out_0_c_bits_error ),
.io_tl_f_0_d_ready (io_out_0_d_ready ),
.io_tl_f_0_d_valid (io_out_0_d_valid ),
.io_tl_f_0_d_bits_opcode (io_out_0_d_bits_opcode ),
.io_tl_f_0_d_bits_param (io_out_0_d_bits_param ),
.io_tl_f_0_d_bits_size (io_out_0_d_bits_size ),
.io_tl_f_0_d_bits_source (io_out_0_d_bits_source ),
.io_tl_f_0_d_bits_sink (io_out_0_d_bits_sink ),
.io_tl_f_0_d_bits_addr_lo (io_out_0_d_bits_addr_lo ),
.io_tl_f_0_d_bits_data (io_out_0_d_bits_data ),
.io_tl_f_0_d_bits_error (io_out_0_d_bits_error ),
.io_tl_f_0_e_ready (io_out_0_e_ready ),
.io_tl_f_0_e_valid (io_out_0_e_valid ),
.io_tl_f_0_e_bits_sink (io_out_0_e_bits_sink ),
.io_port_sck (io_port_sck ),
.io_port_dq_0_i (io_port_dq_0_i ),
.io_port_dq_0_o (io_port_dq_0_o ),
.io_port_dq_0_oe (io_port_dq_0_oe),
.io_port_dq_1_i (io_port_dq_1_i ),
.io_port_dq_1_o (io_port_dq_1_o ),
.io_port_dq_1_oe (io_port_dq_1_oe),
.io_port_dq_2_i (io_port_dq_2_i ),
.io_port_dq_2_o (io_port_dq_2_o ),
.io_port_dq_2_oe (io_port_dq_2_oe),
.io_port_dq_3_i (io_port_dq_3_i ),
.io_port_dq_3_o (io_port_dq_3_o ),
.io_port_dq_3_oe (io_port_dq_3_oe),
.io_port_cs_0 (io_port_cs_0 ),
.io_tl_i_0_0 (io_tl_i_0_0 )
);
endmodule |
module sirv_qspi_media_2(
input clock,
input reset,
output io_port_sck,
input io_port_dq_0_i,
output io_port_dq_0_o,
output io_port_dq_0_oe,
input io_port_dq_1_i,
output io_port_dq_1_o,
output io_port_dq_1_oe,
input io_port_dq_2_i,
output io_port_dq_2_o,
output io_port_dq_2_oe,
input io_port_dq_3_i,
output io_port_dq_3_o,
output io_port_dq_3_oe,
output io_port_cs_0,
input [11:0] io_ctrl_sck_div,
input io_ctrl_sck_pol,
input io_ctrl_sck_pha,
input [7:0] io_ctrl_dla_cssck,
input [7:0] io_ctrl_dla_sckcs,
input [7:0] io_ctrl_dla_intercs,
input [7:0] io_ctrl_dla_interxfr,
input io_ctrl_cs_id,
input io_ctrl_cs_dflt_0,
output io_link_tx_ready,
input io_link_tx_valid,
input [7:0] io_link_tx_bits,
output io_link_rx_valid,
output [7:0] io_link_rx_bits,
input [7:0] io_link_cnt,
input [1:0] io_link_fmt_proto,
input io_link_fmt_endian,
input io_link_fmt_iodir,
input io_link_cs_set,
input io_link_cs_clear,
input io_link_cs_hold,
output io_link_active
);
wire phy_clock;
wire phy_reset;
wire phy_io_port_sck;
wire phy_io_port_dq_0_i;
wire phy_io_port_dq_0_o;
wire phy_io_port_dq_0_oe;
wire phy_io_port_dq_1_i;
wire phy_io_port_dq_1_o;
wire phy_io_port_dq_1_oe;
wire phy_io_port_dq_2_i;
wire phy_io_port_dq_2_o;
wire phy_io_port_dq_2_oe;
wire phy_io_port_dq_3_i;
wire phy_io_port_dq_3_o;
wire phy_io_port_dq_3_oe;
wire phy_io_port_cs_0;
wire [11:0] phy_io_ctrl_sck_div;
wire phy_io_ctrl_sck_pol;
wire phy_io_ctrl_sck_pha;
wire [1:0] phy_io_ctrl_fmt_proto;
wire phy_io_ctrl_fmt_endian;
wire phy_io_ctrl_fmt_iodir;
wire phy_io_op_ready;
wire phy_io_op_valid;
wire phy_io_op_bits_fn;
wire phy_io_op_bits_stb;
wire [7:0] phy_io_op_bits_cnt;
wire [7:0] phy_io_op_bits_data;
wire phy_io_rx_valid;
wire [7:0] phy_io_rx_bits;
reg cs_id;
reg [31:0] GEN_5;
reg cs_dflt_0;
reg [31:0] GEN_52;
reg cs_set;
reg [31:0] GEN_53;
wire [1:0] GEN_48;
wire [1:0] T_162;
wire [1:0] GEN_49;
wire [1:0] T_163;
wire T_164;
wire cs_active_0;
wire cs_update;
reg clear;
reg [31:0] GEN_54;
reg cs_assert;
reg [31:0] GEN_55;
wire T_175;
wire T_176;
wire cs_deassert;
wire T_177;
wire T_178;
wire continuous;
reg [1:0] state;
reg [31:0] GEN_56;
wire T_182;
wire [1:0] GEN_0;
wire [7:0] GEN_1;
wire [1:0] GEN_2;
wire T_184;
wire T_186;
wire [1:0] GEN_3;
wire GEN_4;
wire GEN_6;
wire GEN_7;
wire [1:0] GEN_8;
wire [7:0] GEN_9;
wire [1:0] GEN_10;
wire GEN_11;
wire GEN_12;
wire GEN_13;
wire GEN_14;
wire T_188;
wire T_189;
wire GEN_15;
wire GEN_16;
wire GEN_17;
wire [7:0] GEN_18;
wire GEN_19;
wire GEN_20;
wire GEN_21;
wire T_194;
wire T_195;
wire [7:0] GEN_22;
wire GEN_23;
wire GEN_24;
wire GEN_25;
wire [7:0] GEN_26;
wire [1:0] GEN_27;
wire GEN_28;
wire GEN_29;
wire GEN_30;
wire GEN_31;
wire GEN_32;
wire GEN_33;
wire GEN_34;
wire GEN_35;
wire T_198;
wire T_200;
wire T_201;
wire [1:0] GEN_36;
wire GEN_37;
wire [7:0] GEN_38;
wire [1:0] GEN_39;
wire T_202;
wire [1:0] GEN_50;
wire [1:0] T_206;
wire [1:0] GEN_51;
wire [1:0] T_207;
wire T_208;
wire T_213_0;
wire GEN_40;
wire [1:0] GEN_41;
wire [7:0] GEN_42;
wire GEN_43;
wire GEN_44;
wire GEN_45;
wire GEN_46;
wire [1:0] GEN_47;
sirv_qspi_physical_2 phy (
.clock(phy_clock),
.reset(phy_reset),
.io_port_sck(phy_io_port_sck),
.io_port_dq_0_i(phy_io_port_dq_0_i),
.io_port_dq_0_o(phy_io_port_dq_0_o),
.io_port_dq_0_oe(phy_io_port_dq_0_oe),
.io_port_dq_1_i(phy_io_port_dq_1_i),
.io_port_dq_1_o(phy_io_port_dq_1_o),
.io_port_dq_1_oe(phy_io_port_dq_1_oe),
.io_port_dq_2_i(phy_io_port_dq_2_i),
.io_port_dq_2_o(phy_io_port_dq_2_o),
.io_port_dq_2_oe(phy_io_port_dq_2_oe),
.io_port_dq_3_i(phy_io_port_dq_3_i),
.io_port_dq_3_o(phy_io_port_dq_3_o),
.io_port_dq_3_oe(phy_io_port_dq_3_oe),
.io_port_cs_0(phy_io_port_cs_0),
.io_ctrl_sck_div(phy_io_ctrl_sck_div),
.io_ctrl_sck_pol(phy_io_ctrl_sck_pol),
.io_ctrl_sck_pha(phy_io_ctrl_sck_pha),
.io_ctrl_fmt_proto(phy_io_ctrl_fmt_proto),
.io_ctrl_fmt_endian(phy_io_ctrl_fmt_endian),
.io_ctrl_fmt_iodir(phy_io_ctrl_fmt_iodir),
.io_op_ready(phy_io_op_ready),
.io_op_valid(phy_io_op_valid),
.io_op_bits_fn(phy_io_op_bits_fn),
.io_op_bits_stb(phy_io_op_bits_stb),
.io_op_bits_cnt(phy_io_op_bits_cnt),
.io_op_bits_data(phy_io_op_bits_data),
.io_rx_valid(phy_io_rx_valid),
.io_rx_bits(phy_io_rx_bits)
);
assign io_port_sck = phy_io_port_sck;
assign io_port_dq_0_o = phy_io_port_dq_0_o;
assign io_port_dq_0_oe = phy_io_port_dq_0_oe;
assign io_port_dq_1_o = phy_io_port_dq_1_o;
assign io_port_dq_1_oe = phy_io_port_dq_1_oe;
assign io_port_dq_2_o = phy_io_port_dq_2_o;
assign io_port_dq_2_oe = phy_io_port_dq_2_oe;
assign io_port_dq_3_o = phy_io_port_dq_3_o;
assign io_port_dq_3_oe = phy_io_port_dq_3_oe;
assign io_port_cs_0 = cs_dflt_0;
assign io_link_tx_ready = GEN_31;
assign io_link_rx_valid = phy_io_rx_valid;
assign io_link_rx_bits = phy_io_rx_bits;
assign io_link_active = cs_assert;
assign phy_clock = clock;
assign phy_reset = reset;
assign phy_io_port_dq_0_i = io_port_dq_0_i;
assign phy_io_port_dq_1_i = io_port_dq_1_i;
assign phy_io_port_dq_2_i = io_port_dq_2_i;
assign phy_io_port_dq_3_i = io_port_dq_3_i;
assign phy_io_ctrl_sck_div = io_ctrl_sck_div;
assign phy_io_ctrl_sck_pol = io_ctrl_sck_pol;
assign phy_io_ctrl_sck_pha = io_ctrl_sck_pha;
assign phy_io_ctrl_fmt_proto = io_link_fmt_proto;
assign phy_io_ctrl_fmt_endian = io_link_fmt_endian;
assign phy_io_ctrl_fmt_iodir = io_link_fmt_iodir;
assign phy_io_op_valid = GEN_37;
assign phy_io_op_bits_fn = GEN_28;
assign phy_io_op_bits_stb = GEN_43;
assign phy_io_op_bits_cnt = GEN_42;
assign phy_io_op_bits_data = io_link_tx_bits;
assign GEN_48 = {{1'd0}, io_link_cs_set};
assign T_162 = GEN_48 << io_ctrl_cs_id;
assign GEN_49 = {{1'd0}, io_ctrl_cs_dflt_0};
assign T_163 = GEN_49 ^ T_162;
assign T_164 = T_163[0];
assign cs_active_0 = T_164;
assign cs_update = cs_active_0 != cs_dflt_0;
assign T_175 = io_link_cs_hold == 1'h0;
assign T_176 = cs_update & T_175;
assign cs_deassert = clear | T_176;
assign T_177 = io_link_cs_clear & cs_assert;
assign T_178 = clear | T_177;
assign continuous = io_ctrl_dla_interxfr == 8'h0;
assign T_182 = 2'h0 == state;
assign GEN_0 = phy_io_op_ready ? 2'h2 : state;
assign GEN_1 = cs_deassert ? io_ctrl_dla_sckcs : io_link_cnt;
assign GEN_2 = cs_deassert ? GEN_0 : state;
assign T_184 = cs_deassert == 1'h0;
assign T_186 = phy_io_op_ready & phy_io_op_valid;
assign GEN_3 = T_186 ? 2'h1 : GEN_2;
assign GEN_4 = T_184 ? 1'h0 : 1'h1;
assign GEN_6 = T_184 ? io_link_tx_valid : 1'h1;
assign GEN_7 = T_184 ? phy_io_op_ready : 1'h0;
assign GEN_8 = T_184 ? GEN_3 : GEN_2;
assign GEN_9 = cs_assert ? GEN_1 : io_link_cnt;
assign GEN_10 = cs_assert ? GEN_8 : state;
assign GEN_11 = cs_assert ? GEN_4 : 1'h1;
assign GEN_12 = cs_assert ? T_184 : 1'h0;
assign GEN_13 = cs_assert ? GEN_6 : 1'h1;
assign GEN_14 = cs_assert ? GEN_7 : 1'h0;
assign T_188 = cs_assert == 1'h0;
assign T_189 = T_188 & io_link_tx_valid;
assign GEN_15 = phy_io_op_ready ? 1'h1 : cs_assert;
assign GEN_16 = phy_io_op_ready ? io_link_cs_set : cs_set;
assign GEN_17 = phy_io_op_ready ? cs_active_0 : cs_dflt_0;
assign GEN_18 = T_189 ? io_ctrl_dla_cssck : GEN_9;
assign GEN_19 = T_189 ? GEN_15 : cs_assert;
assign GEN_20 = T_189 ? GEN_16 : cs_set;
assign GEN_21 = T_189 ? GEN_17 : cs_dflt_0;
assign T_194 = io_link_tx_valid == 1'h0;
assign T_195 = T_188 & T_194;
assign GEN_22 = T_195 ? 8'h0 : GEN_18;
assign GEN_23 = T_195 ? 1'h1 : GEN_12;
assign GEN_24 = T_195 ? io_ctrl_cs_id : cs_id;
assign GEN_25 = T_195 ? io_ctrl_cs_dflt_0 : GEN_21;
assign GEN_26 = T_182 ? GEN_22 : io_link_cnt;
assign GEN_27 = T_182 ? GEN_10 : state;
assign GEN_28 = T_182 ? GEN_11 : 1'h1;
assign GEN_29 = T_182 ? GEN_23 : 1'h0;
assign GEN_30 = T_182 ? GEN_13 : 1'h1;
assign GEN_31 = T_182 ? GEN_14 : 1'h0;
assign GEN_32 = T_182 ? GEN_19 : cs_assert;
assign GEN_33 = T_182 ? GEN_20 : cs_set;
assign GEN_34 = T_182 ? GEN_25 : cs_dflt_0;
assign GEN_35 = T_182 ? GEN_24 : cs_id;
assign T_198 = 2'h1 == state;
assign T_200 = continuous == 1'h0;
assign T_201 = phy_io_op_ready | continuous;
assign GEN_36 = T_201 ? 2'h0 : GEN_27;
assign GEN_37 = T_198 ? T_200 : GEN_30;
assign GEN_38 = T_198 ? io_ctrl_dla_interxfr : GEN_26;
assign GEN_39 = T_198 ? GEN_36 : GEN_27;
assign T_202 = 2'h2 == state;
assign GEN_50 = {{1'd0}, cs_set};
assign T_206 = GEN_50 << cs_id;
assign GEN_51 = {{1'd0}, cs_dflt_0};
assign T_207 = GEN_51 ^ T_206;
assign T_208 = T_207[0];
assign T_213_0 = T_208;
assign GEN_40 = phy_io_op_ready ? T_213_0 : GEN_34;
assign GEN_41 = phy_io_op_ready ? 2'h0 : GEN_39;
assign GEN_42 = T_202 ? io_ctrl_dla_intercs : GEN_38;
assign GEN_43 = T_202 ? 1'h1 : GEN_29;
assign GEN_44 = T_202 ? 1'h0 : GEN_32;
assign GEN_45 = T_202 ? 1'h0 : T_178;
assign GEN_46 = T_202 ? GEN_40 : GEN_34;
assign GEN_47 = T_202 ? GEN_41 : GEN_39;
always @(posedge clock or posedge reset)
if(reset) begin
cs_id <= 2'b0;
cs_dflt_0 <= 1'b1;
cs_set <= 1'b0;
end
else begin//{
if (T_182) begin
if (T_195) begin
cs_id <= io_ctrl_cs_id;
end
end
if (T_202) begin
if (phy_io_op_ready) begin
cs_dflt_0 <= T_213_0;
end else begin
if (T_182) begin
if (T_195) begin
cs_dflt_0 <= io_ctrl_cs_dflt_0;
end else begin
if (T_189) begin
if (phy_io_op_ready) begin
cs_dflt_0 <= cs_active_0;
end
end
end
end
end
end else begin
if (T_182) begin
if (T_195) begin
cs_dflt_0 <= io_ctrl_cs_dflt_0;
end else begin
if (T_189) begin
if (phy_io_op_ready) begin
cs_dflt_0 <= cs_active_0;
end
end
end
end
end
if (T_182) begin
if (T_189) begin
if (phy_io_op_ready) begin
cs_set <= io_link_cs_set;
end
end
end
end//}
always @(posedge clock or posedge reset)
if (reset) begin
clear <= 1'h0;
end else begin
if (T_202) begin
clear <= 1'h0;
end else begin
clear <= T_178;
end
end
always @(posedge clock or posedge reset)
if (reset) begin
cs_assert <= 1'h0;
end else begin
if (T_202) begin
cs_assert <= 1'h0;
end else begin
if (T_182) begin
if (T_189) begin
if (phy_io_op_ready) begin
cs_assert <= 1'h1;
end
end
end
end
end
always @(posedge clock or posedge reset)
if (reset) begin
state <= 2'h0;
end else begin
if (T_202) begin
if (phy_io_op_ready) begin
state <= 2'h0;
end else begin
if (T_198) begin
if (T_201) begin
state <= 2'h0;
end else begin
if (T_182) begin
if (cs_assert) begin
if (T_184) begin
if (T_186) begin
state <= 2'h1;
end else begin
if (cs_deassert) begin
if (phy_io_op_ready) begin
state <= 2'h2;
end
end
end
end else begin
if (cs_deassert) begin
if (phy_io_op_ready) begin
state <= 2'h2;
end
end
end
end
end
end
end else begin
if (T_182) begin
if (cs_assert) begin
if (T_184) begin
if (T_186) begin
state <= 2'h1;
end else begin
if (cs_deassert) begin
if (phy_io_op_ready) begin
state <= 2'h2;
end
end
end
end else begin
if (cs_deassert) begin
if (phy_io_op_ready) begin
state <= 2'h2;
end
end
end
end
end
end
end
end else begin
if (T_198) begin
if (T_201) begin
state <= 2'h0;
end else begin
if (T_182) begin
if (cs_assert) begin
if (T_184) begin
if (T_186) begin
state <= 2'h1;
end else begin
state <= GEN_2;
end
end else begin
state <= GEN_2;
end
end
end
end
end else begin
if (T_182) begin
if (cs_assert) begin
if (T_184) begin
if (T_186) begin
state <= 2'h1;
end else begin
state <= GEN_2;
end
end else begin
state <= GEN_2;
end
end
end
end
end
end
endmodule |
module sirv_tlwidthwidget_qspi(
input clock,
input reset,
output io_in_0_a_ready,
input io_in_0_a_valid,
input [2:0] io_in_0_a_bits_opcode,
input [2:0] io_in_0_a_bits_param,
input [2:0] io_in_0_a_bits_size,
input [1:0] io_in_0_a_bits_source,
input [29:0] io_in_0_a_bits_address,
input [3:0] io_in_0_a_bits_mask,
input [31:0] io_in_0_a_bits_data,
input io_in_0_b_ready,
output io_in_0_b_valid,
output [2:0] io_in_0_b_bits_opcode,
output [1:0] io_in_0_b_bits_param,
output [2:0] io_in_0_b_bits_size,
output [1:0] io_in_0_b_bits_source,
output [29:0] io_in_0_b_bits_address,
output [3:0] io_in_0_b_bits_mask,
output [31:0] io_in_0_b_bits_data,
output io_in_0_c_ready,
input io_in_0_c_valid,
input [2:0] io_in_0_c_bits_opcode,
input [2:0] io_in_0_c_bits_param,
input [2:0] io_in_0_c_bits_size,
input [1:0] io_in_0_c_bits_source,
input [29:0] io_in_0_c_bits_address,
input [31:0] io_in_0_c_bits_data,
input io_in_0_c_bits_error,
input io_in_0_d_ready,
output io_in_0_d_valid,
output [2:0] io_in_0_d_bits_opcode,
output [1:0] io_in_0_d_bits_param,
output [2:0] io_in_0_d_bits_size,
output [1:0] io_in_0_d_bits_source,
output io_in_0_d_bits_sink,
output [1:0] io_in_0_d_bits_addr_lo,
output [31:0] io_in_0_d_bits_data,
output io_in_0_d_bits_error,
output io_in_0_e_ready,
input io_in_0_e_valid,
input io_in_0_e_bits_sink,
input io_out_0_a_ready,
output io_out_0_a_valid,
output [2:0] io_out_0_a_bits_opcode,
output [2:0] io_out_0_a_bits_param,
output [2:0] io_out_0_a_bits_size,
output [1:0] io_out_0_a_bits_source,
output [29:0] io_out_0_a_bits_address,
output io_out_0_a_bits_mask,
output [7:0] io_out_0_a_bits_data,
output io_out_0_b_ready,
input io_out_0_b_valid,
input [2:0] io_out_0_b_bits_opcode,
input [1:0] io_out_0_b_bits_param,
input [2:0] io_out_0_b_bits_size,
input [1:0] io_out_0_b_bits_source,
input [29:0] io_out_0_b_bits_address,
input io_out_0_b_bits_mask,
input [7:0] io_out_0_b_bits_data,
input io_out_0_c_ready,
output io_out_0_c_valid,
output [2:0] io_out_0_c_bits_opcode,
output [2:0] io_out_0_c_bits_param,
output [2:0] io_out_0_c_bits_size,
output [1:0] io_out_0_c_bits_source,
output [29:0] io_out_0_c_bits_address,
output [7:0] io_out_0_c_bits_data,
output io_out_0_c_bits_error,
output io_out_0_d_ready,
input io_out_0_d_valid,
input [2:0] io_out_0_d_bits_opcode,
input [1:0] io_out_0_d_bits_param,
input [2:0] io_out_0_d_bits_size,
input [1:0] io_out_0_d_bits_source,
input io_out_0_d_bits_sink,
input io_out_0_d_bits_addr_lo,
input [7:0] io_out_0_d_bits_data,
input io_out_0_d_bits_error,
input io_out_0_e_ready,
output io_out_0_e_valid,
output io_out_0_e_bits_sink
);
wire T_1403;
wire Repeater_5_1_clock;
wire Repeater_5_1_reset;
wire Repeater_5_1_io_repeat;
wire Repeater_5_1_io_full;
wire Repeater_5_1_io_enq_ready;
wire Repeater_5_1_io_enq_valid;
wire [2:0] Repeater_5_1_io_enq_bits_opcode;
wire [2:0] Repeater_5_1_io_enq_bits_param;
wire [2:0] Repeater_5_1_io_enq_bits_size;
wire [1:0] Repeater_5_1_io_enq_bits_source;
wire [29:0] Repeater_5_1_io_enq_bits_address;
wire [3:0] Repeater_5_1_io_enq_bits_mask;
wire [31:0] Repeater_5_1_io_enq_bits_data;
wire Repeater_5_1_io_deq_ready;
wire Repeater_5_1_io_deq_valid;
wire [2:0] Repeater_5_1_io_deq_bits_opcode;
wire [2:0] Repeater_5_1_io_deq_bits_param;
wire [2:0] Repeater_5_1_io_deq_bits_size;
wire [1:0] Repeater_5_1_io_deq_bits_source;
wire [29:0] Repeater_5_1_io_deq_bits_address;
wire [3:0] Repeater_5_1_io_deq_bits_mask;
wire [31:0] Repeater_5_1_io_deq_bits_data;
wire [7:0] T_1408;
wire [7:0] T_1409;
wire [7:0] T_1410;
wire [7:0] T_1411;
wire [7:0] T_1419_0;
wire [7:0] T_1419_1;
wire [7:0] T_1419_2;
wire [7:0] T_1419_3;
wire T_1426;
wire T_1427;
wire T_1428;
wire T_1429;
wire T_1437_0;
wire T_1437_1;
wire T_1437_2;
wire T_1437_3;
reg [3:0] T_1447;
reg [31:0] GEN_28;
wire [8:0] T_1458;
wire [1:0] T_1459;
wire [1:0] T_1460;
wire T_1463;
wire T_1465;
wire T_1466;
wire T_1468;
wire T_1472;
wire [1:0] T_1473;
wire [1:0] T_1474;
wire [3:0] T_1475;
wire [4:0] GEN_12;
wire [4:0] T_1476;
wire [4:0] T_1477;
wire T_1482;
wire [4:0] GEN_2;
wire [1:0] T_1487;
wire [1:0] T_1488;
wire [3:0] T_1489;
wire [4:0] GEN_13;
wire [4:0] T_1490;
wire T_1492;
wire T_1493;
wire T_1494;
wire T_1495;
wire T_1497;
wire T_1499;
wire T_1501;
wire T_1503;
wire T_1505;
wire T_1506;
wire T_1507;
wire T_1508;
reg [23:0] T_1512;
reg [31:0] GEN_29;
reg [2:0] T_1514;
reg [31:0] GEN_30;
wire [31:0] T_1515;
wire [3:0] T_1523;
reg [1:0] T_1527;
reg [31:0] GEN_31;
wire [8:0] T_1532;
wire [1:0] T_1533;
wire [1:0] T_1534;
wire T_1536;
wire T_1540;
wire [23:0] T_1541;
wire [2:0] T_1542;
wire [2:0] T_1544;
wire [1:0] T_1545;
wire [1:0] GEN_3;
wire [23:0] GEN_4;
wire [2:0] GEN_5;
wire [1:0] GEN_6;
wire [7:0] T_1547;
wire [15:0] T_1548;
wire [31:0] T_1549;
wire T_1550;
wire [3:0] T_1554;
wire [15:0] T_1555;
wire [31:0] T_1556;
wire [1:0] T_1557;
wire [3:0] T_1558;
wire [31:0] T_1570_0;
wire [31:0] T_1570_1;
wire [31:0] T_1570_2;
wire [31:0] T_1570_3;
wire [31:0] T_1570_4;
wire [31:0] T_1570_5;
wire [3:0] T_1588_0;
wire [3:0] T_1588_1;
wire [3:0] T_1588_2;
wire [3:0] T_1588_3;
wire [3:0] T_1588_4;
wire [3:0] T_1588_5;
wire T_1599;
wire T_1600;
wire T_1601;
wire [31:0] GEN_0;
wire [31:0] GEN_7;
wire [31:0] GEN_8;
wire [31:0] GEN_9;
wire [31:0] GEN_10;
wire [31:0] GEN_11;
wire [2:0] GEN_1 = 3'b0;
reg [31:0] GEN_32;
wire [1:0] GEN_14 = 2'b0;
reg [31:0] GEN_33;
wire [2:0] GEN_15 = 3'b0;
reg [31:0] GEN_34;
wire [1:0] GEN_16 = 2'b0;
reg [31:0] GEN_35;
wire [29:0] GEN_17 = 30'b0;
reg [31:0] GEN_36;
wire [3:0] GEN_18 = 4'b0;
reg [31:0] GEN_37;
wire [31:0] GEN_19 = 32'b0;
reg [31:0] GEN_38;
wire [2:0] GEN_20 = 3'b0;
reg [31:0] GEN_39;
wire [2:0] GEN_21 = 3'b0;
reg [31:0] GEN_40;
wire [2:0] GEN_22 = 3'b0;
reg [31:0] GEN_41;
wire [1:0] GEN_23 = 2'b0;
reg [31:0] GEN_42;
wire [29:0] GEN_24 = 30'b0;
reg [31:0] GEN_43;
wire [7:0] GEN_25 = 8'b0;
reg [31:0] GEN_44;
wire GEN_26 = 1'b0;
reg [31:0] GEN_45;
wire GEN_27 = 1'b0;
reg [31:0] GEN_46;
sirv_tl_repeater_5 Repeater_5_1 (
.clock(Repeater_5_1_clock),
.reset(Repeater_5_1_reset),
.io_repeat(Repeater_5_1_io_repeat),
.io_full(Repeater_5_1_io_full),
.io_enq_ready(Repeater_5_1_io_enq_ready),
.io_enq_valid(Repeater_5_1_io_enq_valid),
.io_enq_bits_opcode(Repeater_5_1_io_enq_bits_opcode),
.io_enq_bits_param(Repeater_5_1_io_enq_bits_param),
.io_enq_bits_size(Repeater_5_1_io_enq_bits_size),
.io_enq_bits_source(Repeater_5_1_io_enq_bits_source),
.io_enq_bits_address(Repeater_5_1_io_enq_bits_address),
.io_enq_bits_mask(Repeater_5_1_io_enq_bits_mask),
.io_enq_bits_data(Repeater_5_1_io_enq_bits_data),
.io_deq_ready(Repeater_5_1_io_deq_ready),
.io_deq_valid(Repeater_5_1_io_deq_valid),
.io_deq_bits_opcode(Repeater_5_1_io_deq_bits_opcode),
.io_deq_bits_param(Repeater_5_1_io_deq_bits_param),
.io_deq_bits_size(Repeater_5_1_io_deq_bits_size),
.io_deq_bits_source(Repeater_5_1_io_deq_bits_source),
.io_deq_bits_address(Repeater_5_1_io_deq_bits_address),
.io_deq_bits_mask(Repeater_5_1_io_deq_bits_mask),
.io_deq_bits_data(Repeater_5_1_io_deq_bits_data)
);
assign io_in_0_a_ready = Repeater_5_1_io_enq_ready;
assign io_in_0_b_valid = 1'h0;
assign io_in_0_b_bits_opcode = GEN_1;
assign io_in_0_b_bits_param = GEN_14;
assign io_in_0_b_bits_size = GEN_15;
assign io_in_0_b_bits_source = GEN_16;
assign io_in_0_b_bits_address = GEN_17;
assign io_in_0_b_bits_mask = GEN_18;
assign io_in_0_b_bits_data = GEN_19;
assign io_in_0_c_ready = 1'h1;
assign io_in_0_d_valid = T_1601;
assign io_in_0_d_bits_opcode = io_out_0_d_bits_opcode;
assign io_in_0_d_bits_param = io_out_0_d_bits_param;
assign io_in_0_d_bits_size = io_out_0_d_bits_size;
assign io_in_0_d_bits_source = io_out_0_d_bits_source;
assign io_in_0_d_bits_sink = io_out_0_d_bits_sink;
assign io_in_0_d_bits_addr_lo = {{1'd0}, io_out_0_d_bits_addr_lo};
assign io_in_0_d_bits_data = GEN_0;
assign io_in_0_d_bits_error = io_out_0_d_bits_error;
assign io_in_0_e_ready = 1'h1;
assign io_out_0_a_valid = Repeater_5_1_io_deq_valid;
assign io_out_0_a_bits_opcode = Repeater_5_1_io_deq_bits_opcode;
assign io_out_0_a_bits_param = Repeater_5_1_io_deq_bits_param;
assign io_out_0_a_bits_size = Repeater_5_1_io_deq_bits_size;
assign io_out_0_a_bits_source = Repeater_5_1_io_deq_bits_source;
assign io_out_0_a_bits_address = Repeater_5_1_io_deq_bits_address;
assign io_out_0_a_bits_mask = T_1508;
assign io_out_0_a_bits_data = 8'h0;
assign io_out_0_b_ready = 1'h1;
assign io_out_0_c_valid = 1'h0;
assign io_out_0_c_bits_opcode = GEN_20;
assign io_out_0_c_bits_param = GEN_21;
assign io_out_0_c_bits_size = GEN_22;
assign io_out_0_c_bits_source = GEN_23;
assign io_out_0_c_bits_address = GEN_24;
assign io_out_0_c_bits_data = GEN_25;
assign io_out_0_c_bits_error = GEN_26;
assign io_out_0_d_ready = T_1600;
assign io_out_0_e_valid = 1'h0;
assign io_out_0_e_bits_sink = GEN_27;
assign T_1403 = 1'h0;
assign Repeater_5_1_clock = clock;
assign Repeater_5_1_reset = reset;
assign Repeater_5_1_io_repeat = T_1403;
assign Repeater_5_1_io_enq_valid = io_in_0_a_valid;
assign Repeater_5_1_io_enq_bits_opcode = io_in_0_a_bits_opcode;
assign Repeater_5_1_io_enq_bits_param = io_in_0_a_bits_param;
assign Repeater_5_1_io_enq_bits_size = io_in_0_a_bits_size;
assign Repeater_5_1_io_enq_bits_source = io_in_0_a_bits_source;
assign Repeater_5_1_io_enq_bits_address = io_in_0_a_bits_address;
assign Repeater_5_1_io_enq_bits_mask = io_in_0_a_bits_mask;
assign Repeater_5_1_io_enq_bits_data = io_in_0_a_bits_data;
assign Repeater_5_1_io_deq_ready = io_out_0_a_ready;
assign T_1408 = Repeater_5_1_io_deq_bits_data[7:0];
assign T_1409 = Repeater_5_1_io_deq_bits_data[15:8];
assign T_1410 = Repeater_5_1_io_deq_bits_data[23:16];
assign T_1411 = Repeater_5_1_io_deq_bits_data[31:24];
assign T_1419_0 = T_1408;
assign T_1419_1 = T_1409;
assign T_1419_2 = T_1410;
assign T_1419_3 = T_1411;
assign T_1426 = Repeater_5_1_io_deq_bits_mask[0];
assign T_1427 = Repeater_5_1_io_deq_bits_mask[1];
assign T_1428 = Repeater_5_1_io_deq_bits_mask[2];
assign T_1429 = Repeater_5_1_io_deq_bits_mask[3];
assign T_1437_0 = T_1426;
assign T_1437_1 = T_1427;
assign T_1437_2 = T_1428;
assign T_1437_3 = T_1429;
assign T_1458 = 9'h3 << Repeater_5_1_io_deq_bits_size;
assign T_1459 = T_1458[1:0];
assign T_1460 = ~ T_1459;
assign T_1463 = T_1460[0];
assign T_1465 = T_1463 == 1'h0;
assign T_1466 = T_1460[1];
assign T_1468 = T_1466 == 1'h0;
assign T_1472 = T_1447[3];
assign T_1473 = {T_1465,1'h1};
assign T_1474 = {T_1465,T_1468};
assign T_1475 = {T_1474,T_1473};
assign GEN_12 = {{1'd0}, T_1447};
assign T_1476 = GEN_12 << 1;
assign T_1477 = T_1472 ? {{1'd0}, T_1475} : T_1476;
assign T_1482 = io_out_0_a_ready & io_out_0_a_valid;
assign GEN_2 = T_1482 ? 5'hf : {{1'd0}, T_1447};
assign T_1487 = {T_1437_1,T_1437_0};
assign T_1488 = {T_1437_3,T_1437_2};
assign T_1489 = {T_1488,T_1487};
assign GEN_13 = {{1'd0}, T_1489};
assign T_1490 = GEN_13 & T_1477;
assign T_1492 = T_1490[0];
assign T_1493 = T_1490[1];
assign T_1494 = T_1490[2];
assign T_1495 = T_1490[3];
assign T_1497 = T_1492 ? T_1437_0 : 1'h0;
assign T_1499 = T_1493 ? T_1437_1 : 1'h0;
assign T_1501 = T_1494 ? T_1437_2 : 1'h0;
assign T_1503 = T_1495 ? T_1437_3 : 1'h0;
assign T_1505 = T_1497 | T_1499;
assign T_1506 = T_1505 | T_1501;
assign T_1507 = T_1506 | T_1503;
assign T_1508 = T_1507;
assign T_1515 = {io_out_0_d_bits_data,T_1512};
assign T_1523 = {1'h1,T_1514};
assign T_1532 = 9'h3 << io_out_0_d_bits_size;
assign T_1533 = T_1532[1:0];
assign T_1534 = ~ T_1533;
assign T_1536 = T_1527 == T_1534;
assign T_1540 = io_out_0_d_ready & io_out_0_d_valid;
assign T_1541 = T_1515[31:8];
assign T_1542 = T_1523[3:1];
assign T_1544 = T_1527 + 2'h1;
assign T_1545 = T_1544[1:0];
assign GEN_3 = T_1536 ? 2'h0 : T_1545;
assign GEN_4 = T_1540 ? T_1541 : T_1512;
assign GEN_5 = T_1540 ? T_1542 : T_1514;
assign GEN_6 = T_1540 ? GEN_3 : T_1527;
assign T_1547 = T_1515[31:24];
assign T_1548 = {T_1547,T_1547};
assign T_1549 = {T_1548,T_1548};
assign T_1550 = T_1523[3];
assign T_1554 = T_1550 ? 4'hf : 4'h0;
assign T_1555 = T_1515[31:16];
assign T_1556 = {T_1555,T_1555};
assign T_1557 = T_1523[3:2];
assign T_1558 = {T_1557,T_1557};
assign T_1570_0 = T_1549;
assign T_1570_1 = T_1556;
assign T_1570_2 = T_1515;
assign T_1570_3 = T_1515;
assign T_1570_4 = T_1515;
assign T_1570_5 = T_1515;
assign T_1588_0 = T_1554;
assign T_1588_1 = T_1558;
assign T_1588_2 = T_1523;
assign T_1588_3 = T_1523;
assign T_1588_4 = T_1523;
assign T_1588_5 = T_1523;
assign T_1599 = T_1536 == 1'h0;
assign T_1600 = io_in_0_d_ready | T_1599;
assign T_1601 = io_out_0_d_valid & T_1536;
assign GEN_0 = GEN_11;
assign GEN_7 = 3'h1 == io_out_0_d_bits_size ? T_1570_1 : T_1570_0;
assign GEN_8 = 3'h2 == io_out_0_d_bits_size ? T_1570_2 : GEN_7;
assign GEN_9 = 3'h3 == io_out_0_d_bits_size ? T_1570_3 : GEN_8;
assign GEN_10 = 3'h4 == io_out_0_d_bits_size ? T_1570_4 : GEN_9;
assign GEN_11 = 3'h5 == io_out_0_d_bits_size ? T_1570_5 : GEN_10;
always @(posedge clock or posedge reset)
if (reset) begin
T_1447 <= 4'hf;
end else begin
T_1447 <= GEN_2[3:0];
end
always @(posedge clock or posedge reset)
if (reset) begin
T_1512 <= 24'b0;
T_1514 <= 3'b0;
end
else begin
if (T_1540) begin
T_1512 <= T_1541;
end
if (T_1540) begin
T_1514 <= T_1542;
end
end
always @(posedge clock or posedge reset)
if (reset) begin
T_1527 <= 2'h0;
end else begin
if (T_1540) begin
if (T_1536) begin
T_1527 <= 2'h0;
end else begin
T_1527 <= T_1545;
end
end
end
endmodule |
module sirv_aon_porrst(
output porrst_n
);
`ifdef FPGA_SOURCE//{
// In FPGA, we have no PORRST circult
assign porrst_n = 1'b1;
`else //}{
assign porrst_n = 1'b1;
`endif//}
endmodule |
module e203_exu_alu(
//////////////////////////////////////////////////////////////
// The operands and decode info from dispatch
input i_valid,
output i_ready,
output i_longpipe, // Indicate this instruction is
// issued as a long pipe instruction
`ifdef E203_HAS_CSR_EAI//{
`ifndef E203_HAS_EAI
input eai_xs_off,
`endif//
output eai_csr_valid,
input eai_csr_ready,
output [31:0] eai_csr_addr,
output eai_csr_wr,
output [31:0] eai_csr_wdata,
input [31:0] eai_csr_rdata,
`endif//}
output amo_wait,
input oitf_empty,
input [`E203_ITAG_WIDTH-1:0] i_itag,
input [`E203_XLEN-1:0] i_rs1,
input [`E203_XLEN-1:0] i_rs2,
input [`E203_XLEN-1:0] i_imm,
input [`E203_DECINFO_WIDTH-1:0] i_info,
input [`E203_PC_SIZE-1:0] i_pc,
input [`E203_INSTR_SIZE-1:0] i_instr,
input i_pc_vld,
input [`E203_RFIDX_WIDTH-1:0] i_rdidx,
input i_rdwen,
input i_ilegl,
input i_buserr,
input i_misalgn,
input flush_req,
input flush_pulse,
//////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////
// The Commit Interface
output cmt_o_valid, // Handshake valid
input cmt_o_ready, // Handshake ready
output cmt_o_pc_vld,
output [`E203_PC_SIZE-1:0] cmt_o_pc,
output [`E203_INSTR_SIZE-1:0] cmt_o_instr,
output [`E203_XLEN-1:0] cmt_o_imm,// The resolved ture/false
// The Branch and Jump Commit
output cmt_o_rv32,// The predicted ture/false
output cmt_o_bjp,
output cmt_o_mret,
output cmt_o_dret,
output cmt_o_ecall,
output cmt_o_ebreak,
output cmt_o_fencei,
output cmt_o_wfi,
output cmt_o_ifu_misalgn,
output cmt_o_ifu_buserr,
output cmt_o_ifu_ilegl,
output cmt_o_bjp_prdt,// The predicted ture/false
output cmt_o_bjp_rslv,// The resolved ture/false
// The AGU Exception
output cmt_o_misalgn, // The misalign exception generated
output cmt_o_ld,
output cmt_o_stamo,
output cmt_o_buserr , // The bus-error exception generated
output [`E203_ADDR_SIZE-1:0] cmt_o_badaddr,
//////////////////////////////////////////////////////////////
// The ALU Write-Back Interface
output wbck_o_valid, // Handshake valid
input wbck_o_ready, // Handshake ready
output [`E203_XLEN-1:0] wbck_o_wdat,
output [`E203_RFIDX_WIDTH-1:0] wbck_o_rdidx,
input mdv_nob2b,
//////////////////////////////////////////////////////////////
// The CSR Interface
output csr_ena,
output csr_wr_en,
output csr_rd_en,
output [12-1:0] csr_idx,
input nonflush_cmt_ena,
input csr_access_ilgl,
input [`E203_XLEN-1:0] read_csr_dat,
output [`E203_XLEN-1:0] wbck_csr_dat,
//////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////
// The AGU ICB Interface to LSU-ctrl
// * Bus cmd channel
output agu_icb_cmd_valid, // Handshake valid
input agu_icb_cmd_ready, // Handshake ready
output [`E203_ADDR_SIZE-1:0] agu_icb_cmd_addr, // Bus transaction start addr
output agu_icb_cmd_read, // Read or write
output [`E203_XLEN-1:0] agu_icb_cmd_wdata,
output [`E203_XLEN/8-1:0] agu_icb_cmd_wmask,
output agu_icb_cmd_lock,
output agu_icb_cmd_excl,
output [1:0] agu_icb_cmd_size,
output agu_icb_cmd_back2agu,
output agu_icb_cmd_usign,
output [`E203_ITAG_WIDTH -1:0] agu_icb_cmd_itag,
// * Bus RSP channel
input agu_icb_rsp_valid, // Response valid
output agu_icb_rsp_ready, // Response ready
input agu_icb_rsp_err , // Response error
input agu_icb_rsp_excl_ok,
input [`E203_XLEN-1:0] agu_icb_rsp_rdata,
input clk,
input rst_n
);
//////////////////////////////////////////////////////////////
// Dispatch to different sub-modules according to their types
wire ifu_excp_op = i_ilegl | i_buserr | i_misalgn;
wire alu_op = (~ifu_excp_op) & (i_info[`E203_DECINFO_GRP] == `E203_DECINFO_GRP_ALU);
wire agu_op = (~ifu_excp_op) & (i_info[`E203_DECINFO_GRP] == `E203_DECINFO_GRP_AGU);
wire bjp_op = (~ifu_excp_op) & (i_info[`E203_DECINFO_GRP] == `E203_DECINFO_GRP_BJP);
wire csr_op = (~ifu_excp_op) & (i_info[`E203_DECINFO_GRP] == `E203_DECINFO_GRP_CSR);
`ifdef E203_SUPPORT_SHARE_MULDIV //{
wire mdv_op = (~ifu_excp_op) & (i_info[`E203_DECINFO_GRP] == `E203_DECINFO_GRP_MULDIV);
`endif//E203_SUPPORT_SHARE_MULDIV}
// The ALU incoming instruction may go to several different targets:
// * The ALUDATAPATH if it is a regular ALU instructions
// * The Branch-cmp if it is a BJP instructions
// * The AGU if it is a load/store relevant instructions
// * The MULDIV if it is a MUL/DIV relevant instructions and MULDIV
// is reusing the ALU adder
`ifdef E203_SUPPORT_SHARE_MULDIV //{
wire mdv_i_valid = i_valid & mdv_op;
`endif//E203_SUPPORT_SHARE_MULDIV}
wire agu_i_valid = i_valid & agu_op;
wire alu_i_valid = i_valid & alu_op;
wire bjp_i_valid = i_valid & bjp_op;
wire csr_i_valid = i_valid & csr_op;
wire ifu_excp_i_valid = i_valid & ifu_excp_op;
`ifdef E203_SUPPORT_SHARE_MULDIV //{
wire mdv_i_ready;
`endif//E203_SUPPORT_SHARE_MULDIV}
wire agu_i_ready;
wire alu_i_ready;
wire bjp_i_ready;
wire csr_i_ready;
wire ifu_excp_i_ready;
assign i_ready = (agu_i_ready & agu_op)
`ifdef E203_SUPPORT_SHARE_MULDIV //{
| (mdv_i_ready & mdv_op)
`endif//E203_SUPPORT_SHARE_MULDIV}
| (alu_i_ready & alu_op)
| (ifu_excp_i_ready & ifu_excp_op)
| (bjp_i_ready & bjp_op)
| (csr_i_ready & csr_op)
;
wire agu_i_longpipe;
`ifdef E203_SUPPORT_SHARE_MULDIV //{
wire mdv_i_longpipe;
`endif//E203_SUPPORT_SHARE_MULDIV}
assign i_longpipe = (agu_i_longpipe & agu_op)
`ifdef E203_SUPPORT_SHARE_MULDIV //{
| (mdv_i_longpipe & mdv_op)
`endif//E203_SUPPORT_SHARE_MULDIV}
;
//////////////////////////////////////////////////////////////
// Instantiate the CSR module
//
wire csr_o_valid;
wire csr_o_ready;
wire [`E203_XLEN-1:0] csr_o_wbck_wdat;
wire csr_o_wbck_err;
wire [`E203_XLEN-1:0] csr_i_rs1 = {`E203_XLEN {csr_op}} & i_rs1;
wire [`E203_XLEN-1:0] csr_i_rs2 = {`E203_XLEN {csr_op}} & i_rs2;
wire [`E203_XLEN-1:0] csr_i_imm = {`E203_XLEN {csr_op}} & i_imm;
wire [`E203_DECINFO_WIDTH-1:0] csr_i_info = {`E203_DECINFO_WIDTH{csr_op}} & i_info;
wire csr_i_rdwen = csr_op & i_rdwen;
`ifndef E203_HAS_EAI//{
wire eai_o_cmt_wr_reg;
wire csr_sel_eai;
`endif//}
e203_exu_alu_csrctrl u_e203_exu_alu_csrctrl(
`ifdef E203_HAS_CSR_EAI//{
.csr_sel_eai (csr_sel_eai),
.eai_xs_off (eai_xs_off),
.eai_csr_valid (eai_csr_valid),
.eai_csr_ready (eai_csr_ready),
.eai_csr_addr (eai_csr_addr ),
.eai_csr_wr (eai_csr_wr ),
.eai_csr_wdata (eai_csr_wdata),
.eai_csr_rdata (eai_csr_rdata),
`endif//}
.csr_access_ilgl (csr_access_ilgl),
.csr_i_valid (csr_i_valid),
.csr_i_ready (csr_i_ready),
.csr_i_rs1 (csr_i_rs1 ),
.csr_i_info (csr_i_info[`E203_DECINFO_CSR_WIDTH-1:0]),
.csr_i_rdwen (csr_i_rdwen),
.csr_ena (csr_ena),
.csr_idx (csr_idx),
.csr_rd_en (csr_rd_en),
.csr_wr_en (csr_wr_en),
.read_csr_dat (read_csr_dat),
.wbck_csr_dat (wbck_csr_dat),
.csr_o_valid (csr_o_valid ),
.csr_o_ready (csr_o_ready ),
.csr_o_wbck_wdat (csr_o_wbck_wdat ),
.csr_o_wbck_err (csr_o_wbck_err ),
.clk (clk),
.rst_n (rst_n)
);
//////////////////////////////////////////////////////////////
// Instantiate the BJP module
//
wire bjp_o_valid;
wire bjp_o_ready;
wire [`E203_XLEN-1:0] bjp_o_wbck_wdat;
wire bjp_o_wbck_err;
wire bjp_o_cmt_bjp;
wire bjp_o_cmt_mret;
wire bjp_o_cmt_dret;
wire bjp_o_cmt_fencei;
wire bjp_o_cmt_prdt;
wire bjp_o_cmt_rslv;
wire [`E203_XLEN-1:0] bjp_req_alu_op1;
wire [`E203_XLEN-1:0] bjp_req_alu_op2;
wire bjp_req_alu_cmp_eq ;
wire bjp_req_alu_cmp_ne ;
wire bjp_req_alu_cmp_lt ;
wire bjp_req_alu_cmp_gt ;
wire bjp_req_alu_cmp_ltu;
wire bjp_req_alu_cmp_gtu;
wire bjp_req_alu_add;
wire bjp_req_alu_cmp_res;
wire [`E203_XLEN-1:0] bjp_req_alu_add_res;
wire [`E203_XLEN-1:0] bjp_i_rs1 = {`E203_XLEN {bjp_op}} & i_rs1;
wire [`E203_XLEN-1:0] bjp_i_rs2 = {`E203_XLEN {bjp_op}} & i_rs2;
wire [`E203_XLEN-1:0] bjp_i_imm = {`E203_XLEN {bjp_op}} & i_imm;
wire [`E203_DECINFO_WIDTH-1:0] bjp_i_info = {`E203_DECINFO_WIDTH{bjp_op}} & i_info;
wire [`E203_PC_SIZE-1:0] bjp_i_pc = {`E203_PC_SIZE {bjp_op}} & i_pc;
e203_exu_alu_bjp u_e203_exu_alu_bjp(
.bjp_i_valid (bjp_i_valid ),
.bjp_i_ready (bjp_i_ready ),
.bjp_i_rs1 (bjp_i_rs1 ),
.bjp_i_rs2 (bjp_i_rs2 ),
.bjp_i_info (bjp_i_info[`E203_DECINFO_BJP_WIDTH-1:0]),
.bjp_i_imm (bjp_i_imm ),
.bjp_i_pc (bjp_i_pc ),
.bjp_o_valid (bjp_o_valid ),
.bjp_o_ready (bjp_o_ready ),
.bjp_o_wbck_wdat (bjp_o_wbck_wdat ),
.bjp_o_wbck_err (bjp_o_wbck_err ),
.bjp_o_cmt_bjp (bjp_o_cmt_bjp ),
.bjp_o_cmt_mret (bjp_o_cmt_mret ),
.bjp_o_cmt_dret (bjp_o_cmt_dret ),
.bjp_o_cmt_fencei (bjp_o_cmt_fencei ),
.bjp_o_cmt_prdt (bjp_o_cmt_prdt ),
.bjp_o_cmt_rslv (bjp_o_cmt_rslv ),
.bjp_req_alu_op1 (bjp_req_alu_op1 ),
.bjp_req_alu_op2 (bjp_req_alu_op2 ),
.bjp_req_alu_cmp_eq (bjp_req_alu_cmp_eq ),
.bjp_req_alu_cmp_ne (bjp_req_alu_cmp_ne ),
.bjp_req_alu_cmp_lt (bjp_req_alu_cmp_lt ),
.bjp_req_alu_cmp_gt (bjp_req_alu_cmp_gt ),
.bjp_req_alu_cmp_ltu (bjp_req_alu_cmp_ltu ),
.bjp_req_alu_cmp_gtu (bjp_req_alu_cmp_gtu ),
.bjp_req_alu_add (bjp_req_alu_add ),
.bjp_req_alu_cmp_res (bjp_req_alu_cmp_res ),
.bjp_req_alu_add_res (bjp_req_alu_add_res ),
.clk (clk),
.rst_n (rst_n)
);
//////////////////////////////////////////////////////////////
// Instantiate the AGU module
//
wire agu_o_valid;
wire agu_o_ready;
wire [`E203_XLEN-1:0] agu_o_wbck_wdat;
wire agu_o_wbck_err;
wire agu_o_cmt_misalgn;
wire agu_o_cmt_ld;
wire agu_o_cmt_stamo;
wire agu_o_cmt_buserr ;
wire [`E203_ADDR_SIZE-1:0]agu_o_cmt_badaddr ;
wire [`E203_XLEN-1:0] agu_req_alu_op1;
wire [`E203_XLEN-1:0] agu_req_alu_op2;
wire agu_req_alu_swap;
wire agu_req_alu_add ;
wire agu_req_alu_and ;
wire agu_req_alu_or ;
wire agu_req_alu_xor ;
wire agu_req_alu_max ;
wire agu_req_alu_min ;
wire agu_req_alu_maxu;
wire agu_req_alu_minu;
wire [`E203_XLEN-1:0] agu_req_alu_res;
wire agu_sbf_0_ena;
wire [`E203_XLEN-1:0] agu_sbf_0_nxt;
wire [`E203_XLEN-1:0] agu_sbf_0_r;
wire agu_sbf_1_ena;
wire [`E203_XLEN-1:0] agu_sbf_1_nxt;
wire [`E203_XLEN-1:0] agu_sbf_1_r;
wire [`E203_XLEN-1:0] agu_i_rs1 = {`E203_XLEN {agu_op}} & i_rs1;
wire [`E203_XLEN-1:0] agu_i_rs2 = {`E203_XLEN {agu_op}} & i_rs2;
wire [`E203_XLEN-1:0] agu_i_imm = {`E203_XLEN {agu_op}} & i_imm;
wire [`E203_DECINFO_WIDTH-1:0] agu_i_info = {`E203_DECINFO_WIDTH{agu_op}} & i_info;
wire [`E203_ITAG_WIDTH-1:0] agu_i_itag = {`E203_ITAG_WIDTH {agu_op}} & i_itag;
e203_exu_alu_lsuagu u_e203_exu_alu_lsuagu(
.agu_i_valid (agu_i_valid ),
.agu_i_ready (agu_i_ready ),
.agu_i_rs1 (agu_i_rs1 ),
.agu_i_rs2 (agu_i_rs2 ),
.agu_i_imm (agu_i_imm ),
.agu_i_info (agu_i_info[`E203_DECINFO_AGU_WIDTH-1:0]),
.agu_i_longpipe (agu_i_longpipe ),
.agu_i_itag (agu_i_itag ),
.flush_pulse (flush_pulse ),
.flush_req (flush_req ),
.amo_wait (amo_wait),
.oitf_empty (oitf_empty),
.agu_o_valid (agu_o_valid ),
.agu_o_ready (agu_o_ready ),
.agu_o_wbck_wdat (agu_o_wbck_wdat ),
.agu_o_wbck_err (agu_o_wbck_err ),
.agu_o_cmt_misalgn (agu_o_cmt_misalgn ),
.agu_o_cmt_ld (agu_o_cmt_ld ),
.agu_o_cmt_stamo (agu_o_cmt_stamo ),
.agu_o_cmt_buserr (agu_o_cmt_buserr ),
.agu_o_cmt_badaddr (agu_o_cmt_badaddr ),
.agu_icb_cmd_valid (agu_icb_cmd_valid ),
.agu_icb_cmd_ready (agu_icb_cmd_ready ),
.agu_icb_cmd_addr (agu_icb_cmd_addr ),
.agu_icb_cmd_read (agu_icb_cmd_read ),
.agu_icb_cmd_wdata (agu_icb_cmd_wdata ),
.agu_icb_cmd_wmask (agu_icb_cmd_wmask ),
.agu_icb_cmd_lock (agu_icb_cmd_lock ),
.agu_icb_cmd_excl (agu_icb_cmd_excl ),
.agu_icb_cmd_size (agu_icb_cmd_size ),
.agu_icb_cmd_back2agu(agu_icb_cmd_back2agu),
.agu_icb_cmd_usign (agu_icb_cmd_usign ),
.agu_icb_cmd_itag (agu_icb_cmd_itag ),
.agu_icb_rsp_valid (agu_icb_rsp_valid ),
.agu_icb_rsp_ready (agu_icb_rsp_ready ),
.agu_icb_rsp_err (agu_icb_rsp_err ),
.agu_icb_rsp_excl_ok (agu_icb_rsp_excl_ok ),
.agu_icb_rsp_rdata (agu_icb_rsp_rdata ),
.agu_req_alu_op1 (agu_req_alu_op1 ),
.agu_req_alu_op2 (agu_req_alu_op2 ),
.agu_req_alu_swap (agu_req_alu_swap ),
.agu_req_alu_add (agu_req_alu_add ),
.agu_req_alu_and (agu_req_alu_and ),
.agu_req_alu_or (agu_req_alu_or ),
.agu_req_alu_xor (agu_req_alu_xor ),
.agu_req_alu_max (agu_req_alu_max ),
.agu_req_alu_min (agu_req_alu_min ),
.agu_req_alu_maxu (agu_req_alu_maxu ),
.agu_req_alu_minu (agu_req_alu_minu ),
.agu_req_alu_res (agu_req_alu_res ),
.agu_sbf_0_ena (agu_sbf_0_ena ),
.agu_sbf_0_nxt (agu_sbf_0_nxt ),
.agu_sbf_0_r (agu_sbf_0_r ),
.agu_sbf_1_ena (agu_sbf_1_ena ),
.agu_sbf_1_nxt (agu_sbf_1_nxt ),
.agu_sbf_1_r (agu_sbf_1_r ),
.clk (clk),
.rst_n (rst_n)
);
//////////////////////////////////////////////////////////////
// Instantiate the regular ALU module
//
wire alu_o_valid;
wire alu_o_ready;
wire [`E203_XLEN-1:0] alu_o_wbck_wdat;
wire alu_o_wbck_err;
wire alu_o_cmt_ecall;
wire alu_o_cmt_ebreak;
wire alu_o_cmt_wfi;
wire alu_req_alu_add ;
wire alu_req_alu_sub ;
wire alu_req_alu_xor ;
wire alu_req_alu_sll ;
wire alu_req_alu_srl ;
wire alu_req_alu_sra ;
wire alu_req_alu_or ;
wire alu_req_alu_and ;
wire alu_req_alu_slt ;
wire alu_req_alu_sltu;
wire alu_req_alu_lui ;
wire [`E203_XLEN-1:0] alu_req_alu_op1;
wire [`E203_XLEN-1:0] alu_req_alu_op2;
wire [`E203_XLEN-1:0] alu_req_alu_res;
wire [`E203_XLEN-1:0] alu_i_rs1 = {`E203_XLEN {alu_op}} & i_rs1;
wire [`E203_XLEN-1:0] alu_i_rs2 = {`E203_XLEN {alu_op}} & i_rs2;
wire [`E203_XLEN-1:0] alu_i_imm = {`E203_XLEN {alu_op}} & i_imm;
wire [`E203_DECINFO_WIDTH-1:0] alu_i_info = {`E203_DECINFO_WIDTH{alu_op}} & i_info;
wire [`E203_PC_SIZE-1:0] alu_i_pc = {`E203_PC_SIZE {alu_op}} & i_pc;
e203_exu_alu_rglr u_e203_exu_alu_rglr(
.alu_i_valid (alu_i_valid ),
.alu_i_ready (alu_i_ready ),
.alu_i_rs1 (alu_i_rs1 ),
.alu_i_rs2 (alu_i_rs2 ),
.alu_i_info (alu_i_info[`E203_DECINFO_ALU_WIDTH-1:0]),
.alu_i_imm (alu_i_imm ),
.alu_i_pc (alu_i_pc ),
.alu_o_valid (alu_o_valid ),
.alu_o_ready (alu_o_ready ),
.alu_o_wbck_wdat (alu_o_wbck_wdat ),
.alu_o_wbck_err (alu_o_wbck_err ),
.alu_o_cmt_ecall (alu_o_cmt_ecall ),
.alu_o_cmt_ebreak (alu_o_cmt_ebreak),
.alu_o_cmt_wfi (alu_o_cmt_wfi ),
.alu_req_alu_add (alu_req_alu_add ),
.alu_req_alu_sub (alu_req_alu_sub ),
.alu_req_alu_xor (alu_req_alu_xor ),
.alu_req_alu_sll (alu_req_alu_sll ),
.alu_req_alu_srl (alu_req_alu_srl ),
.alu_req_alu_sra (alu_req_alu_sra ),
.alu_req_alu_or (alu_req_alu_or ),
.alu_req_alu_and (alu_req_alu_and ),
.alu_req_alu_slt (alu_req_alu_slt ),
.alu_req_alu_sltu (alu_req_alu_sltu ),
.alu_req_alu_lui (alu_req_alu_lui ),
.alu_req_alu_op1 (alu_req_alu_op1 ),
.alu_req_alu_op2 (alu_req_alu_op2 ),
.alu_req_alu_res (alu_req_alu_res ),
.clk (clk ),
.rst_n (rst_n )
);
`ifdef E203_SUPPORT_SHARE_MULDIV //{
//////////////////////////////////////////////////////
// Instantiate the MULDIV module
wire [`E203_XLEN-1:0] mdv_i_rs1 = {`E203_XLEN {mdv_op}} & i_rs1;
wire [`E203_XLEN-1:0] mdv_i_rs2 = {`E203_XLEN {mdv_op}} & i_rs2;
wire [`E203_XLEN-1:0] mdv_i_imm = {`E203_XLEN {mdv_op}} & i_imm;
wire [`E203_DECINFO_WIDTH-1:0] mdv_i_info = {`E203_DECINFO_WIDTH{mdv_op}} & i_info;
wire [`E203_ITAG_WIDTH-1:0] mdv_i_itag = {`E203_ITAG_WIDTH {mdv_op}} & i_itag;
wire mdv_o_valid;
wire mdv_o_ready;
wire [`E203_XLEN-1:0] mdv_o_wbck_wdat;
wire mdv_o_wbck_err;
wire [`E203_ALU_ADDER_WIDTH-1:0] muldiv_req_alu_op1;
wire [`E203_ALU_ADDER_WIDTH-1:0] muldiv_req_alu_op2;
wire muldiv_req_alu_add ;
wire muldiv_req_alu_sub ;
wire [`E203_ALU_ADDER_WIDTH-1:0] muldiv_req_alu_res;
wire muldiv_sbf_0_ena;
wire [33-1:0] muldiv_sbf_0_nxt;
wire [33-1:0] muldiv_sbf_0_r;
wire muldiv_sbf_1_ena;
wire [33-1:0] muldiv_sbf_1_nxt;
wire [33-1:0] muldiv_sbf_1_r;
e203_exu_alu_muldiv u_e203_exu_alu_muldiv(
.mdv_nob2b (mdv_nob2b),
.muldiv_i_valid (mdv_i_valid ),
.muldiv_i_ready (mdv_i_ready ),
.muldiv_i_rs1 (mdv_i_rs1 ),
.muldiv_i_rs2 (mdv_i_rs2 ),
.muldiv_i_imm (mdv_i_imm ),
.muldiv_i_info (mdv_i_info[`E203_DECINFO_MULDIV_WIDTH-1:0]),
.muldiv_i_longpipe (mdv_i_longpipe ),
.muldiv_i_itag (mdv_i_itag ),
.flush_pulse (flush_pulse ),
.muldiv_o_valid (mdv_o_valid ),
.muldiv_o_ready (mdv_o_ready ),
.muldiv_o_wbck_wdat (mdv_o_wbck_wdat),
.muldiv_o_wbck_err (mdv_o_wbck_err ),
.muldiv_req_alu_op1 (muldiv_req_alu_op1),
.muldiv_req_alu_op2 (muldiv_req_alu_op2),
.muldiv_req_alu_add (muldiv_req_alu_add),
.muldiv_req_alu_sub (muldiv_req_alu_sub),
.muldiv_req_alu_res (muldiv_req_alu_res),
.muldiv_sbf_0_ena (muldiv_sbf_0_ena ),
.muldiv_sbf_0_nxt (muldiv_sbf_0_nxt ),
.muldiv_sbf_0_r (muldiv_sbf_0_r ),
.muldiv_sbf_1_ena (muldiv_sbf_1_ena ),
.muldiv_sbf_1_nxt (muldiv_sbf_1_nxt ),
.muldiv_sbf_1_r (muldiv_sbf_1_r ),
.clk (clk ),
.rst_n (rst_n )
);
`endif//E203_SUPPORT_SHARE_MULDIV}
//////////////////////////////////////////////////////////////
// Instantiate the Shared Datapath module
//
wire alu_req_alu = alu_op & i_rdwen;// Regular ALU only req datapath when it need to write-back
`ifdef E203_SUPPORT_SHARE_MULDIV //{
wire muldiv_req_alu = mdv_op;// Since MULDIV have no point to let rd=0, so always need ALU datapath
`endif//E203_SUPPORT_SHARE_MULDIV}
wire bjp_req_alu = bjp_op;// Since BJP may not write-back, but still need ALU datapath
wire agu_req_alu = agu_op;// Since AGU may have some other features, so always need ALU datapath
e203_exu_alu_dpath u_e203_exu_alu_dpath(
.alu_req_alu (alu_req_alu ),
.alu_req_alu_add (alu_req_alu_add ),
.alu_req_alu_sub (alu_req_alu_sub ),
.alu_req_alu_xor (alu_req_alu_xor ),
.alu_req_alu_sll (alu_req_alu_sll ),
.alu_req_alu_srl (alu_req_alu_srl ),
.alu_req_alu_sra (alu_req_alu_sra ),
.alu_req_alu_or (alu_req_alu_or ),
.alu_req_alu_and (alu_req_alu_and ),
.alu_req_alu_slt (alu_req_alu_slt ),
.alu_req_alu_sltu (alu_req_alu_sltu ),
.alu_req_alu_lui (alu_req_alu_lui ),
.alu_req_alu_op1 (alu_req_alu_op1 ),
.alu_req_alu_op2 (alu_req_alu_op2 ),
.alu_req_alu_res (alu_req_alu_res ),
.bjp_req_alu (bjp_req_alu ),
.bjp_req_alu_op1 (bjp_req_alu_op1 ),
.bjp_req_alu_op2 (bjp_req_alu_op2 ),
.bjp_req_alu_cmp_eq (bjp_req_alu_cmp_eq ),
.bjp_req_alu_cmp_ne (bjp_req_alu_cmp_ne ),
.bjp_req_alu_cmp_lt (bjp_req_alu_cmp_lt ),
.bjp_req_alu_cmp_gt (bjp_req_alu_cmp_gt ),
.bjp_req_alu_cmp_ltu (bjp_req_alu_cmp_ltu ),
.bjp_req_alu_cmp_gtu (bjp_req_alu_cmp_gtu ),
.bjp_req_alu_add (bjp_req_alu_add ),
.bjp_req_alu_cmp_res (bjp_req_alu_cmp_res ),
.bjp_req_alu_add_res (bjp_req_alu_add_res ),
.agu_req_alu (agu_req_alu ),
.agu_req_alu_op1 (agu_req_alu_op1 ),
.agu_req_alu_op2 (agu_req_alu_op2 ),
.agu_req_alu_swap (agu_req_alu_swap ),
.agu_req_alu_add (agu_req_alu_add ),
.agu_req_alu_and (agu_req_alu_and ),
.agu_req_alu_or (agu_req_alu_or ),
.agu_req_alu_xor (agu_req_alu_xor ),
.agu_req_alu_max (agu_req_alu_max ),
.agu_req_alu_min (agu_req_alu_min ),
.agu_req_alu_maxu (agu_req_alu_maxu ),
.agu_req_alu_minu (agu_req_alu_minu ),
.agu_req_alu_res (agu_req_alu_res ),
.agu_sbf_0_ena (agu_sbf_0_ena ),
.agu_sbf_0_nxt (agu_sbf_0_nxt ),
.agu_sbf_0_r (agu_sbf_0_r ),
.agu_sbf_1_ena (agu_sbf_1_ena ),
.agu_sbf_1_nxt (agu_sbf_1_nxt ),
.agu_sbf_1_r (agu_sbf_1_r ),
`ifdef E203_SUPPORT_SHARE_MULDIV //{
.muldiv_req_alu (muldiv_req_alu ),
.muldiv_req_alu_op1 (muldiv_req_alu_op1),
.muldiv_req_alu_op2 (muldiv_req_alu_op2),
.muldiv_req_alu_add (muldiv_req_alu_add),
.muldiv_req_alu_sub (muldiv_req_alu_sub),
.muldiv_req_alu_res (muldiv_req_alu_res),
.muldiv_sbf_0_ena (muldiv_sbf_0_ena ),
.muldiv_sbf_0_nxt (muldiv_sbf_0_nxt ),
.muldiv_sbf_0_r (muldiv_sbf_0_r ),
.muldiv_sbf_1_ena (muldiv_sbf_1_ena ),
.muldiv_sbf_1_nxt (muldiv_sbf_1_nxt ),
.muldiv_sbf_1_r (muldiv_sbf_1_r ),
`endif//E203_SUPPORT_SHARE_MULDIV}
.clk (clk ),
.rst_n (rst_n )
);
wire ifu_excp_o_valid;
wire ifu_excp_o_ready;
wire [`E203_XLEN-1:0] ifu_excp_o_wbck_wdat;
wire ifu_excp_o_wbck_err;
assign ifu_excp_i_ready = ifu_excp_o_ready;
assign ifu_excp_o_valid = ifu_excp_i_valid;
assign ifu_excp_o_wbck_wdat = `E203_XLEN'b0;
assign ifu_excp_o_wbck_err = 1'b1;// IFU illegal instruction always treat as error
//////////////////////////////////////////////////////////////
// Aribtrate the Result and generate output interfaces
//
wire o_valid;
wire o_ready;
wire o_sel_ifu_excp = ifu_excp_op;
wire o_sel_alu = alu_op;
wire o_sel_bjp = bjp_op;
wire o_sel_csr = csr_op;
wire o_sel_agu = agu_op;
`ifdef E203_SUPPORT_SHARE_MULDIV //{
wire o_sel_mdv = mdv_op;
`endif//E203_SUPPORT_SHARE_MULDIV}
assign o_valid = (o_sel_alu & alu_o_valid )
| (o_sel_bjp & bjp_o_valid )
| (o_sel_csr & csr_o_valid )
| (o_sel_agu & agu_o_valid )
| (o_sel_ifu_excp & ifu_excp_o_valid)
`ifdef E203_SUPPORT_SHARE_MULDIV //{
| (o_sel_mdv & mdv_o_valid )
`endif//E203_SUPPORT_SHARE_MULDIV}
;
assign ifu_excp_o_ready = o_sel_ifu_excp & o_ready;
assign alu_o_ready = o_sel_alu & o_ready;
assign agu_o_ready = o_sel_agu & o_ready;
`ifdef E203_SUPPORT_SHARE_MULDIV //{
assign mdv_o_ready = o_sel_mdv & o_ready;
`endif//E203_SUPPORT_SHARE_MULDIV}
assign bjp_o_ready = o_sel_bjp & o_ready;
assign csr_o_ready = o_sel_csr & o_ready;
assign wbck_o_wdat =
({`E203_XLEN{o_sel_alu}} & alu_o_wbck_wdat)
| ({`E203_XLEN{o_sel_bjp}} & bjp_o_wbck_wdat)
| ({`E203_XLEN{o_sel_csr}} & csr_o_wbck_wdat)
| ({`E203_XLEN{o_sel_agu}} & agu_o_wbck_wdat)
`ifdef E203_SUPPORT_SHARE_MULDIV //{
| ({`E203_XLEN{o_sel_mdv}} & mdv_o_wbck_wdat)
`endif//E203_SUPPORT_SHARE_MULDIV}
| ({`E203_XLEN{o_sel_ifu_excp}} & ifu_excp_o_wbck_wdat)
;
assign wbck_o_rdidx = i_rdidx;
wire wbck_o_rdwen = i_rdwen;
wire wbck_o_err =
({1{o_sel_alu}} & alu_o_wbck_err)
| ({1{o_sel_bjp}} & bjp_o_wbck_err)
| ({1{o_sel_csr}} & csr_o_wbck_err)
| ({1{o_sel_agu}} & agu_o_wbck_err)
`ifdef E203_SUPPORT_SHARE_MULDIV //{
| ({1{o_sel_mdv}} & mdv_o_wbck_err)
`endif//E203_SUPPORT_SHARE_MULDIV}
| ({1{o_sel_ifu_excp}} & ifu_excp_o_wbck_err)
;
// Each Instruction need to commit or write-back
// * The write-back only needed when the unit need to write-back
// the result (need to write RD), and it is not a long-pipe uop
// (need to be write back by its long-pipe write-back, not here)
// * Each instruction need to be commited
wire o_need_wbck = wbck_o_rdwen & (~i_longpipe) & (~wbck_o_err);
wire o_need_cmt = 1'b1;
assign o_ready =
(o_need_cmt ? cmt_o_ready : 1'b1)
& (o_need_wbck ? wbck_o_ready : 1'b1);
assign wbck_o_valid = o_need_wbck & o_valid & (o_need_cmt ? cmt_o_ready : 1'b1);
assign cmt_o_valid = o_need_cmt & o_valid & (o_need_wbck ? wbck_o_ready : 1'b1);
//
// The commint interface have some special signals
assign cmt_o_instr = i_instr;
assign cmt_o_pc = i_pc;
assign cmt_o_imm = i_imm;
assign cmt_o_rv32 = i_info[`E203_DECINFO_RV32];
// The cmt_o_pc_vld is used by the commit stage to check
// if current instruction is outputing a valid current PC
// to guarante the commit to flush pipeline safely, this
// vld only be asserted when:
// * There is a valid instruction here
// --- otherwise, the commit stage may use wrong PC
// value to stored in DPC or EPC
assign cmt_o_pc_vld =
// Otherwise, just use the i_pc_vld
i_pc_vld;
assign cmt_o_misalgn = (o_sel_agu & agu_o_cmt_misalgn)
;
assign cmt_o_ld = (o_sel_agu & agu_o_cmt_ld)
;
assign cmt_o_badaddr = ({`E203_ADDR_SIZE{o_sel_agu}} & agu_o_cmt_badaddr)
;
assign cmt_o_buserr = o_sel_agu & agu_o_cmt_buserr;
assign cmt_o_stamo = o_sel_agu & agu_o_cmt_stamo ;
assign cmt_o_bjp = o_sel_bjp & bjp_o_cmt_bjp;
assign cmt_o_mret = o_sel_bjp & bjp_o_cmt_mret;
assign cmt_o_dret = o_sel_bjp & bjp_o_cmt_dret;
assign cmt_o_bjp_prdt = o_sel_bjp & bjp_o_cmt_prdt;
assign cmt_o_bjp_rslv = o_sel_bjp & bjp_o_cmt_rslv;
assign cmt_o_fencei = o_sel_bjp & bjp_o_cmt_fencei;
assign cmt_o_ecall = o_sel_alu & alu_o_cmt_ecall;
assign cmt_o_ebreak = o_sel_alu & alu_o_cmt_ebreak;
assign cmt_o_wfi = o_sel_alu & alu_o_cmt_wfi;
assign cmt_o_ifu_misalgn = i_misalgn;
assign cmt_o_ifu_buserr = i_buserr;
assign cmt_o_ifu_ilegl = i_ilegl
| (o_sel_csr & csr_access_ilgl)
;
endmodule |
module e203_exu_alu_rglr(
//////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////
// The Handshake Interface
//
input alu_i_valid, // Handshake valid
output alu_i_ready, // Handshake ready
input [`E203_XLEN-1:0] alu_i_rs1,
input [`E203_XLEN-1:0] alu_i_rs2,
input [`E203_XLEN-1:0] alu_i_imm,
input [`E203_PC_SIZE-1:0] alu_i_pc,
input [`E203_DECINFO_ALU_WIDTH-1:0] alu_i_info,
//////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////
// The ALU Write-back/Commit Interface
output alu_o_valid, // Handshake valid
input alu_o_ready, // Handshake ready
// The Write-Back Interface for Special (unaligned ldst and AMO instructions)
output [`E203_XLEN-1:0] alu_o_wbck_wdat,
output alu_o_wbck_err,
output alu_o_cmt_ecall,
output alu_o_cmt_ebreak,
output alu_o_cmt_wfi,
//////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////
// To share the ALU datapath
//
// The operands and info to ALU
output alu_req_alu_add ,
output alu_req_alu_sub ,
output alu_req_alu_xor ,
output alu_req_alu_sll ,
output alu_req_alu_srl ,
output alu_req_alu_sra ,
output alu_req_alu_or ,
output alu_req_alu_and ,
output alu_req_alu_slt ,
output alu_req_alu_sltu,
output alu_req_alu_lui ,
output [`E203_XLEN-1:0] alu_req_alu_op1,
output [`E203_XLEN-1:0] alu_req_alu_op2,
input [`E203_XLEN-1:0] alu_req_alu_res,
input clk,
input rst_n
);
wire op2imm = alu_i_info [`E203_DECINFO_ALU_OP2IMM ];
wire op1pc = alu_i_info [`E203_DECINFO_ALU_OP1PC ];
assign alu_req_alu_op1 = op1pc ? alu_i_pc : alu_i_rs1;
assign alu_req_alu_op2 = op2imm ? alu_i_imm : alu_i_rs2;
wire nop = alu_i_info [`E203_DECINFO_ALU_NOP ] ;
wire ecall = alu_i_info [`E203_DECINFO_ALU_ECAL ];
wire ebreak = alu_i_info [`E203_DECINFO_ALU_EBRK ];
wire wfi = alu_i_info [`E203_DECINFO_ALU_WFI ];
// The NOP is encoded as ADDI, so need to uncheck it
assign alu_req_alu_add = alu_i_info [`E203_DECINFO_ALU_ADD ] & (~nop);
assign alu_req_alu_sub = alu_i_info [`E203_DECINFO_ALU_SUB ];
assign alu_req_alu_xor = alu_i_info [`E203_DECINFO_ALU_XOR ];
assign alu_req_alu_sll = alu_i_info [`E203_DECINFO_ALU_SLL ];
assign alu_req_alu_srl = alu_i_info [`E203_DECINFO_ALU_SRL ];
assign alu_req_alu_sra = alu_i_info [`E203_DECINFO_ALU_SRA ];
assign alu_req_alu_or = alu_i_info [`E203_DECINFO_ALU_OR ];
assign alu_req_alu_and = alu_i_info [`E203_DECINFO_ALU_AND ];
assign alu_req_alu_slt = alu_i_info [`E203_DECINFO_ALU_SLT ];
assign alu_req_alu_sltu = alu_i_info [`E203_DECINFO_ALU_SLTU];
assign alu_req_alu_lui = alu_i_info [`E203_DECINFO_ALU_LUI ];
assign alu_o_valid = alu_i_valid;
assign alu_i_ready = alu_o_ready;
assign alu_o_wbck_wdat = alu_req_alu_res;
assign alu_o_cmt_ecall = ecall;
assign alu_o_cmt_ebreak = ebreak;
assign alu_o_cmt_wfi = wfi;
// The exception or error result cannot write-back
assign alu_o_wbck_err = alu_o_cmt_ecall | alu_o_cmt_ebreak | alu_o_cmt_wfi;
endmodule |
module e203_exu_branchslv(
// The BJP condition final result need to be resolved at ALU
input cmt_i_valid,
output cmt_i_ready,
input cmt_i_rv32,
input cmt_i_dret,// The dret instruction
input cmt_i_mret,// The ret instruction
input cmt_i_fencei,// The fencei instruction
input cmt_i_bjp,
input cmt_i_bjp_prdt,// The predicted ture/false
input cmt_i_bjp_rslv,// The resolved ture/false
input [`E203_PC_SIZE-1:0] cmt_i_pc,
input [`E203_XLEN-1:0] cmt_i_imm,// The resolved ture/false
input [`E203_PC_SIZE-1:0] csr_epc_r,
input [`E203_PC_SIZE-1:0] csr_dpc_r,
input nonalu_excpirq_flush_req_raw,
input brchmis_flush_ack,
output brchmis_flush_req,
output [`E203_PC_SIZE-1:0] brchmis_flush_add_op1,
output [`E203_PC_SIZE-1:0] brchmis_flush_add_op2,
`ifdef E203_TIMING_BOOST//}
output [`E203_PC_SIZE-1:0] brchmis_flush_pc,
`endif//}
output cmt_mret_ena,
output cmt_dret_ena,
output cmt_fencei_ena,
input clk,
input rst_n
);
wire brchmis_flush_ack_pre;
wire brchmis_flush_req_pre;
assign brchmis_flush_req = brchmis_flush_req_pre & (~nonalu_excpirq_flush_req_raw);
assign brchmis_flush_ack_pre = brchmis_flush_ack & (~nonalu_excpirq_flush_req_raw);
// In Two stage impelmentation, several branch instructions are handled as below:
// * It is predicted at IFU, and target is handled in IFU. But
// we need to check if it is predicted correctly or not. If not,
// we need to flush the pipeline
// Note: the JUMP instrution will always jump, hence they will be
// both predicted and resolved as true
wire brchmis_need_flush = (
(cmt_i_bjp & (cmt_i_bjp_prdt ^ cmt_i_bjp_rslv))
// If it is a FenceI instruction, it is always Flush
| cmt_i_fencei
// If it is a RET instruction, it is always jump
| cmt_i_mret
// If it is a DRET instruction, it is always jump
| cmt_i_dret
);
wire cmt_i_is_branch = (
cmt_i_bjp
| cmt_i_fencei
| cmt_i_mret
| cmt_i_dret
);
assign brchmis_flush_req_pre = cmt_i_valid & brchmis_need_flush;
// * If it is a DRET instruction, the new target PC is DPC register
// * If it is a RET instruction, the new target PC is EPC register
// * If predicted as taken, but actually it is not taken, then
// The new target PC should caculated by PC+2/4
// * If predicted as not taken, but actually it is taken, then
// The new target PC should caculated by PC+offset
assign brchmis_flush_add_op1 = cmt_i_dret ? csr_dpc_r : cmt_i_mret ? csr_epc_r : cmt_i_pc;
assign brchmis_flush_add_op2 = cmt_i_dret ? `E203_PC_SIZE'b0 : cmt_i_mret ? `E203_PC_SIZE'b0 :
(cmt_i_fencei | cmt_i_bjp_prdt) ? (cmt_i_rv32 ? `E203_PC_SIZE'd4 : `E203_PC_SIZE'd2)
: cmt_i_imm[`E203_PC_SIZE-1:0];
`ifdef E203_TIMING_BOOST//}
// Replicated two adders here to trade area with timing
assign brchmis_flush_pc =
// The fenceI is also need to trigger the flush to its next instructions
(cmt_i_fencei | (cmt_i_bjp & cmt_i_bjp_prdt)) ? (cmt_i_pc + (cmt_i_rv32 ? `E203_PC_SIZE'd4 : `E203_PC_SIZE'd2)) :
(cmt_i_bjp & (~cmt_i_bjp_prdt)) ? (cmt_i_pc + cmt_i_imm[`E203_PC_SIZE-1:0]) :
cmt_i_dret ? csr_dpc_r :
//cmt_i_mret ? csr_epc_r :
csr_epc_r ;// Last condition cmt_i_mret commented
// to save gatecount and timing
`endif//}
wire brchmis_flush_hsked = brchmis_flush_req & brchmis_flush_ack;
assign cmt_mret_ena = cmt_i_mret & brchmis_flush_hsked;
assign cmt_dret_ena = cmt_i_dret & brchmis_flush_hsked;
assign cmt_fencei_ena = cmt_i_fencei & brchmis_flush_hsked;
assign cmt_i_ready = (~cmt_i_is_branch) |
(
(brchmis_need_flush ? brchmis_flush_ack_pre : 1'b1)
// The Non-ALU flush will override the ALU flush
& (~nonalu_excpirq_flush_req_raw)
);
endmodule |
module sirv_expl_axi_slv #(
parameter AW = 32,
parameter DW = 32
)(
input axi_arvalid,
output axi_arready,
input [AW-1:0] axi_araddr,
input [3:0] axi_arcache,
input [2:0] axi_arprot,
input [1:0] axi_arlock,
input [1:0] axi_arburst,
input [3:0] axi_arlen,
input [2:0] axi_arsize,
input axi_awvalid,
output axi_awready,
input [AW-1:0] axi_awaddr,
input [3:0] axi_awcache,
input [2:0] axi_awprot,
input [1:0] axi_awlock,
input [1:0] axi_awburst,
input [3:0] axi_awlen,
input [2:0] axi_awsize,
output axi_rvalid,
input axi_rready,
output [DW-1:0] axi_rdata,
output [1:0] axi_rresp,
output axi_rlast,
input axi_wvalid,
output axi_wready,
input [DW-1:0] axi_wdata,
input [(DW/8)-1:0] axi_wstrb,
input axi_wlast,
output axi_bvalid,
input axi_bready,
output [1:0] axi_bresp,
input clk,
input rst_n
);
assign axi_rvalid = axi_arvalid;
assign axi_arready = axi_rready;
assign axi_rdata = {DW{1'b0}};
assign axi_rresp = 2'b0;
assign axi_rlast = 1'b1;
assign axi_bvalid = axi_wvalid;
assign axi_wready = axi_bready;
assign axi_bresp = 2'b0;
assign axi_awready = 1'b1;
endmodule |
module sirv_repeater_6(
input clock,
input reset,
input io_repeat,
output io_full,
output io_enq_ready,
input io_enq_valid,
input [2:0] io_enq_bits_opcode,
input [2:0] io_enq_bits_param,
input [2:0] io_enq_bits_size,
input [1:0] io_enq_bits_source,
input [29:0] io_enq_bits_address,
input io_enq_bits_mask,
input [7:0] io_enq_bits_data,
input io_deq_ready,
output io_deq_valid,
output [2:0] io_deq_bits_opcode,
output [2:0] io_deq_bits_param,
output [2:0] io_deq_bits_size,
output [1:0] io_deq_bits_source,
output [29:0] io_deq_bits_address,
output io_deq_bits_mask,
output [7:0] io_deq_bits_data
);
reg full;
reg [31:0] GEN_9;
reg [2:0] saved_opcode;
reg [31:0] GEN_10;
reg [2:0] saved_param;
reg [31:0] GEN_11;
reg [2:0] saved_size;
reg [31:0] GEN_12;
reg [1:0] saved_source;
reg [31:0] GEN_13;
reg [29:0] saved_address;
reg [31:0] GEN_14;
reg saved_mask;
reg [31:0] GEN_15;
reg [7:0] saved_data;
reg [31:0] GEN_16;
wire T_77;
wire T_79;
wire T_80;
wire [2:0] T_81_opcode;
wire [2:0] T_81_param;
wire [2:0] T_81_size;
wire [1:0] T_81_source;
wire [29:0] T_81_address;
wire T_81_mask;
wire [7:0] T_81_data;
wire T_89;
wire T_90;
wire GEN_0;
wire [2:0] GEN_1;
wire [2:0] GEN_2;
wire [2:0] GEN_3;
wire [1:0] GEN_4;
wire [29:0] GEN_5;
wire GEN_6;
wire [7:0] GEN_7;
wire T_92;
wire T_94;
wire T_95;
wire GEN_8;
assign io_full = full;
assign io_enq_ready = T_80;
assign io_deq_valid = T_77;
assign io_deq_bits_opcode = T_81_opcode;
assign io_deq_bits_param = T_81_param;
assign io_deq_bits_size = T_81_size;
assign io_deq_bits_source = T_81_source;
assign io_deq_bits_address = T_81_address;
assign io_deq_bits_mask = T_81_mask;
assign io_deq_bits_data = T_81_data;
assign T_77 = io_enq_valid | full;
assign T_79 = full == 1'h0;
assign T_80 = io_deq_ready & T_79;
assign T_81_opcode = full ? saved_opcode : io_enq_bits_opcode;
assign T_81_param = full ? saved_param : io_enq_bits_param;
assign T_81_size = full ? saved_size : io_enq_bits_size;
assign T_81_source = full ? saved_source : io_enq_bits_source;
assign T_81_address = full ? saved_address : io_enq_bits_address;
assign T_81_mask = full ? saved_mask : io_enq_bits_mask;
assign T_81_data = full ? saved_data : io_enq_bits_data;
assign T_89 = io_enq_ready & io_enq_valid;
assign T_90 = T_89 & io_repeat;
assign GEN_0 = T_90 ? 1'h1 : full;
assign GEN_1 = T_90 ? io_enq_bits_opcode : saved_opcode;
assign GEN_2 = T_90 ? io_enq_bits_param : saved_param;
assign GEN_3 = T_90 ? io_enq_bits_size : saved_size;
assign GEN_4 = T_90 ? io_enq_bits_source : saved_source;
assign GEN_5 = T_90 ? io_enq_bits_address : saved_address;
assign GEN_6 = T_90 ? io_enq_bits_mask : saved_mask;
assign GEN_7 = T_90 ? io_enq_bits_data : saved_data;
assign T_92 = io_deq_ready & io_deq_valid;
assign T_94 = io_repeat == 1'h0;
assign T_95 = T_92 & T_94;
assign GEN_8 = T_95 ? 1'h0 : GEN_0;
always @(posedge clock or posedge reset)
if (reset) begin
full <= 1'h0;
end else begin
if (T_95) begin
full <= 1'h0;
end else begin
if (T_90) begin
full <= 1'h1;
end
end
end
always @(posedge clock or posedge reset)
if (reset) begin
saved_opcode <= 3'b0;
saved_param <= 3'b0;
saved_size <= 3'b0;
saved_source <= 2'b0;
saved_address <= 30'b0;
saved_mask <= 1'b0;
saved_data <= 8'b0;
end
else begin
if (T_90) begin
saved_opcode <= io_enq_bits_opcode;
end
if (T_90) begin
saved_param <= io_enq_bits_param;
end
if (T_90) begin
saved_size <= io_enq_bits_size;
end
if (T_90) begin
saved_source <= io_enq_bits_source;
end
if (T_90) begin
saved_address <= io_enq_bits_address;
end
if (T_90) begin
saved_mask <= io_enq_bits_mask;
end
if (T_90) begin
saved_data <= io_enq_bits_data;
end
end
endmodule |
module e203_subsys_mems(
input mem_icb_cmd_valid,
output mem_icb_cmd_ready,
input [`E203_ADDR_SIZE-1:0] mem_icb_cmd_addr,
input mem_icb_cmd_read,
input [`E203_XLEN-1:0] mem_icb_cmd_wdata,
input [`E203_XLEN/8-1:0] mem_icb_cmd_wmask,
//
output mem_icb_rsp_valid,
input mem_icb_rsp_ready,
output mem_icb_rsp_err,
output [`E203_XLEN-1:0] mem_icb_rsp_rdata,
//////////////////////////////////////////////////////////
output sysmem_icb_cmd_valid,
input sysmem_icb_cmd_ready,
output [`E203_ADDR_SIZE-1:0] sysmem_icb_cmd_addr,
output sysmem_icb_cmd_read,
output [`E203_XLEN-1:0] sysmem_icb_cmd_wdata,
output [`E203_XLEN/8-1:0] sysmem_icb_cmd_wmask,
//
input sysmem_icb_rsp_valid,
output sysmem_icb_rsp_ready,
input sysmem_icb_rsp_err,
input [`E203_XLEN-1:0] sysmem_icb_rsp_rdata,
//////////////////////////////////////////////////////////
output qspi0_ro_icb_cmd_valid,
input qspi0_ro_icb_cmd_ready,
output [`E203_ADDR_SIZE-1:0] qspi0_ro_icb_cmd_addr,
output qspi0_ro_icb_cmd_read,
output [`E203_XLEN-1:0] qspi0_ro_icb_cmd_wdata,
//
input qspi0_ro_icb_rsp_valid,
output qspi0_ro_icb_rsp_ready,
input qspi0_ro_icb_rsp_err,
input [`E203_XLEN-1:0] qspi0_ro_icb_rsp_rdata,
//////////////////////////////////////////////////////////
output otp_ro_icb_cmd_valid,
input otp_ro_icb_cmd_ready,
output [`E203_ADDR_SIZE-1:0] otp_ro_icb_cmd_addr,
output otp_ro_icb_cmd_read,
output [`E203_XLEN-1:0] otp_ro_icb_cmd_wdata,
//
input otp_ro_icb_rsp_valid,
output otp_ro_icb_rsp_ready,
input otp_ro_icb_rsp_err,
input [`E203_XLEN-1:0] otp_ro_icb_rsp_rdata,
//////////////////////////////////////////////////////////
output dm_icb_cmd_valid,
input dm_icb_cmd_ready,
output [`E203_ADDR_SIZE-1:0] dm_icb_cmd_addr,
output dm_icb_cmd_read,
output [`E203_XLEN-1:0] dm_icb_cmd_wdata,
//
input dm_icb_rsp_valid,
output dm_icb_rsp_ready,
input [`E203_XLEN-1:0] dm_icb_rsp_rdata,
input clk,
input bus_rst_n,
input rst_n
);
wire mrom_icb_cmd_valid;
wire mrom_icb_cmd_ready;
wire [`E203_ADDR_SIZE-1:0] mrom_icb_cmd_addr;
wire mrom_icb_cmd_read;
wire mrom_icb_rsp_valid;
wire mrom_icb_rsp_ready;
wire mrom_icb_rsp_err ;
wire [`E203_XLEN-1:0] mrom_icb_rsp_rdata;
wire expl_axi_icb_cmd_valid;
wire expl_axi_icb_cmd_ready;
wire [32-1:0] expl_axi_icb_cmd_addr;
wire expl_axi_icb_cmd_read;
wire [32-1:0] expl_axi_icb_cmd_wdata;
wire [4 -1:0] expl_axi_icb_cmd_wmask;
wire expl_axi_icb_rsp_valid;
wire expl_axi_icb_rsp_ready;
wire [32-1:0] expl_axi_icb_rsp_rdata;
wire expl_axi_icb_rsp_err;
localparam MROM_AW = 12 ;
localparam MROM_DP = 1024;
// There are several slaves for Mem bus, including:
// * DM : 0x0000 0000 -- 0x0000 0FFF
// * MROM : 0x0000 1000 -- 0x0000 1FFF
// * OTP-RO : 0x0002 0000 -- 0x0003 FFFF
// * QSPI0-RO : 0x2000 0000 -- 0x3FFF FFFF
// * SysMem : 0x8000 0000 -- 0xFFFF FFFF
sirv_icb1to8_bus # (
.ICB_FIFO_DP (2),// We add a ping-pong buffer here to cut down the timing path
.ICB_FIFO_CUT_READY (1),// We configure it to cut down the back-pressure ready signal
.AW (32),
.DW (`E203_XLEN),
.SPLT_FIFO_OUTS_NUM (1),// The Mem only allow 1 oustanding
.SPLT_FIFO_CUT_READY (1),// The Mem always cut ready
// * DM : 0x0000 0000 -- 0x0000 0FFF
.O0_BASE_ADDR (32'h0000_0000),
.O0_BASE_REGION_LSB (12),
// * MROM : 0x0000 1000 -- 0x0000 1FFF
.O1_BASE_ADDR (32'h0000_1000),
.O1_BASE_REGION_LSB (12),
// * OTP-RO : 0x0002 0000 -- 0x0003 FFFF
.O2_BASE_ADDR (32'h0002_0000),
.O2_BASE_REGION_LSB (17),
// * QSPI0-RO : 0x2000 0000 -- 0x3FFF FFFF
.O3_BASE_ADDR (32'h2000_0000),
.O3_BASE_REGION_LSB (29),
// * SysMem : 0x8000 0000 -- 0xFFFF FFFF
// Actually since the 0xFxxx xxxx have been occupied by FIO,
// sysmem have no chance to access it
.O4_BASE_ADDR (32'h8000_0000),
.O4_BASE_REGION_LSB (31),
// * Here is an example AXI Peripheral
.O5_BASE_ADDR (32'h4000_0000),
.O5_BASE_REGION_LSB (28),
// Not used
.O6_BASE_ADDR (32'h0000_0000),
.O6_BASE_REGION_LSB (0),
// Not used
.O7_BASE_ADDR (32'h0000_0000),
.O7_BASE_REGION_LSB (0)
)u_sirv_mem_fab(
.i_icb_cmd_valid (mem_icb_cmd_valid),
.i_icb_cmd_ready (mem_icb_cmd_ready),
.i_icb_cmd_addr (mem_icb_cmd_addr ),
.i_icb_cmd_read (mem_icb_cmd_read ),
.i_icb_cmd_wdata (mem_icb_cmd_wdata),
.i_icb_cmd_wmask (mem_icb_cmd_wmask),
.i_icb_cmd_lock (1'b0 ),
.i_icb_cmd_excl (1'b0 ),
.i_icb_cmd_size (2'b0 ),
.i_icb_cmd_burst (2'b0),
.i_icb_cmd_beat (2'b0 ),
.i_icb_rsp_valid (mem_icb_rsp_valid),
.i_icb_rsp_ready (mem_icb_rsp_ready),
.i_icb_rsp_err (mem_icb_rsp_err ),
.i_icb_rsp_excl_ok(),
.i_icb_rsp_rdata (mem_icb_rsp_rdata),
// * DM
.o0_icb_enable (1'b1),
.o0_icb_cmd_valid (dm_icb_cmd_valid),
.o0_icb_cmd_ready (dm_icb_cmd_ready),
.o0_icb_cmd_addr (dm_icb_cmd_addr ),
.o0_icb_cmd_read (dm_icb_cmd_read ),
.o0_icb_cmd_wdata (dm_icb_cmd_wdata),
.o0_icb_cmd_wmask (),
.o0_icb_cmd_lock (),
.o0_icb_cmd_excl (),
.o0_icb_cmd_size (),
.o0_icb_cmd_burst (),
.o0_icb_cmd_beat (),
.o0_icb_rsp_valid (dm_icb_rsp_valid),
.o0_icb_rsp_ready (dm_icb_rsp_ready),
.o0_icb_rsp_err (1'b0),
.o0_icb_rsp_excl_ok(1'b0),
.o0_icb_rsp_rdata (dm_icb_rsp_rdata),
// * MROM
.o1_icb_enable (1'b1),
.o1_icb_cmd_valid (mrom_icb_cmd_valid),
.o1_icb_cmd_ready (mrom_icb_cmd_ready),
.o1_icb_cmd_addr (mrom_icb_cmd_addr ),
.o1_icb_cmd_read (mrom_icb_cmd_read ),
.o1_icb_cmd_wdata (),
.o1_icb_cmd_wmask (),
.o1_icb_cmd_lock (),
.o1_icb_cmd_excl (),
.o1_icb_cmd_size (),
.o1_icb_cmd_burst (),
.o1_icb_cmd_beat (),
.o1_icb_rsp_valid (mrom_icb_rsp_valid),
.o1_icb_rsp_ready (mrom_icb_rsp_ready),
.o1_icb_rsp_err (mrom_icb_rsp_err),
.o1_icb_rsp_excl_ok(1'b0 ),
.o1_icb_rsp_rdata (mrom_icb_rsp_rdata),
// * OTP-RO
.o2_icb_enable (1'b1),
.o2_icb_cmd_valid (otp_ro_icb_cmd_valid),
.o2_icb_cmd_ready (otp_ro_icb_cmd_ready),
.o2_icb_cmd_addr (otp_ro_icb_cmd_addr ),
.o2_icb_cmd_read (otp_ro_icb_cmd_read ),
.o2_icb_cmd_wdata (otp_ro_icb_cmd_wdata),
.o2_icb_cmd_wmask (),
.o2_icb_cmd_lock (),
.o2_icb_cmd_excl (),
.o2_icb_cmd_size (),
.o2_icb_cmd_burst (),
.o2_icb_cmd_beat (),
.o2_icb_rsp_valid (otp_ro_icb_rsp_valid),
.o2_icb_rsp_ready (otp_ro_icb_rsp_ready),
.o2_icb_rsp_err (otp_ro_icb_rsp_err),
.o2_icb_rsp_excl_ok(1'b0 ),
.o2_icb_rsp_rdata (otp_ro_icb_rsp_rdata),
// * QSPI0-RO
.o3_icb_enable (1'b1),
.o3_icb_cmd_valid (qspi0_ro_icb_cmd_valid),
.o3_icb_cmd_ready (qspi0_ro_icb_cmd_ready),
.o3_icb_cmd_addr (qspi0_ro_icb_cmd_addr ),
.o3_icb_cmd_read (qspi0_ro_icb_cmd_read ),
.o3_icb_cmd_wdata (qspi0_ro_icb_cmd_wdata),
.o3_icb_cmd_wmask (),
.o3_icb_cmd_lock (),
.o3_icb_cmd_excl (),
.o3_icb_cmd_size (),
.o3_icb_cmd_burst (),
.o3_icb_cmd_beat (),
.o3_icb_rsp_valid (qspi0_ro_icb_rsp_valid),
.o3_icb_rsp_ready (qspi0_ro_icb_rsp_ready),
.o3_icb_rsp_err (qspi0_ro_icb_rsp_err),
.o3_icb_rsp_excl_ok(1'b0 ),
.o3_icb_rsp_rdata (qspi0_ro_icb_rsp_rdata),
// * SysMem
.o4_icb_enable (1'b1),
.o4_icb_cmd_valid (sysmem_icb_cmd_valid),
.o4_icb_cmd_ready (sysmem_icb_cmd_ready),
.o4_icb_cmd_addr (sysmem_icb_cmd_addr ),
.o4_icb_cmd_read (sysmem_icb_cmd_read ),
.o4_icb_cmd_wdata (sysmem_icb_cmd_wdata),
.o4_icb_cmd_wmask (sysmem_icb_cmd_wmask),
.o4_icb_cmd_lock (),
.o4_icb_cmd_excl (),
.o4_icb_cmd_size (),
.o4_icb_cmd_burst (),
.o4_icb_cmd_beat (),
.o4_icb_rsp_valid (sysmem_icb_rsp_valid),
.o4_icb_rsp_ready (sysmem_icb_rsp_ready),
.o4_icb_rsp_err (sysmem_icb_rsp_err ),
.o4_icb_rsp_excl_ok(1'b0),
.o4_icb_rsp_rdata (sysmem_icb_rsp_rdata),
// * Example AXI
.o5_icb_enable (1'b1),
.o5_icb_cmd_valid (expl_axi_icb_cmd_valid),
.o5_icb_cmd_ready (expl_axi_icb_cmd_ready),
.o5_icb_cmd_addr (expl_axi_icb_cmd_addr ),
.o5_icb_cmd_read (expl_axi_icb_cmd_read ),
.o5_icb_cmd_wdata (expl_axi_icb_cmd_wdata),
.o5_icb_cmd_wmask (expl_axi_icb_cmd_wmask),
.o5_icb_cmd_lock (),
.o5_icb_cmd_excl (),
.o5_icb_cmd_size (),
.o5_icb_cmd_burst (),
.o5_icb_cmd_beat (),
.o5_icb_rsp_valid (expl_axi_icb_rsp_valid),
.o5_icb_rsp_ready (expl_axi_icb_rsp_ready),
.o5_icb_rsp_err (expl_axi_icb_rsp_err),
.o5_icb_rsp_excl_ok(1'b0 ),
.o5_icb_rsp_rdata (expl_axi_icb_rsp_rdata),
// * Not used
.o6_icb_enable (1'b0),
.o6_icb_cmd_valid (),
.o6_icb_cmd_ready (1'b0),
.o6_icb_cmd_addr (),
.o6_icb_cmd_read (),
.o6_icb_cmd_wdata (),
.o6_icb_cmd_wmask (),
.o6_icb_cmd_lock (),
.o6_icb_cmd_excl (),
.o6_icb_cmd_size (),
.o6_icb_cmd_burst (),
.o6_icb_cmd_beat (),
.o6_icb_rsp_valid (1'b0),
.o6_icb_rsp_ready (),
.o6_icb_rsp_err (1'b0 ),
.o6_icb_rsp_excl_ok(1'b0 ),
.o6_icb_rsp_rdata (`E203_XLEN'b0),
// * Not used
.o7_icb_enable (1'b0),
.o7_icb_cmd_valid (),
.o7_icb_cmd_ready (1'b0),
.o7_icb_cmd_addr (),
.o7_icb_cmd_read (),
.o7_icb_cmd_wdata (),
.o7_icb_cmd_wmask (),
.o7_icb_cmd_lock (),
.o7_icb_cmd_excl (),
.o7_icb_cmd_size (),
.o7_icb_cmd_burst (),
.o7_icb_cmd_beat (),
.o7_icb_rsp_valid (1'b0),
.o7_icb_rsp_ready (),
.o7_icb_rsp_err (1'b0 ),
.o7_icb_rsp_excl_ok(1'b0 ),
.o7_icb_rsp_rdata (`E203_XLEN'b0),
.clk (clk ),
.rst_n (bus_rst_n)
);
sirv_mrom_top #(
.AW(MROM_AW),
.DW(32),
.DP(MROM_DP)
)u_sirv_mrom_top(
.rom_icb_cmd_valid (mrom_icb_cmd_valid),
.rom_icb_cmd_ready (mrom_icb_cmd_ready),
.rom_icb_cmd_addr (mrom_icb_cmd_addr [MROM_AW-1:0]),
.rom_icb_cmd_read (mrom_icb_cmd_read ),
.rom_icb_rsp_valid (mrom_icb_rsp_valid),
.rom_icb_rsp_ready (mrom_icb_rsp_ready),
.rom_icb_rsp_err (mrom_icb_rsp_err ),
.rom_icb_rsp_rdata (mrom_icb_rsp_rdata),
.clk (clk ),
.rst_n (rst_n)
);
// * Here is an example AXI Peripheral
wire expl_axi_arvalid;
wire expl_axi_arready;
wire [`E203_ADDR_SIZE-1:0] expl_axi_araddr;
wire [3:0] expl_axi_arcache;
wire [2:0] expl_axi_arprot;
wire [1:0] expl_axi_arlock;
wire [1:0] expl_axi_arburst;
wire [3:0] expl_axi_arlen;
wire [2:0] expl_axi_arsize;
wire expl_axi_awvalid;
wire expl_axi_awready;
wire [`E203_ADDR_SIZE-1:0] expl_axi_awaddr;
wire [3:0] expl_axi_awcache;
wire [2:0] expl_axi_awprot;
wire [1:0] expl_axi_awlock;
wire [1:0] expl_axi_awburst;
wire [3:0] expl_axi_awlen;
wire [2:0] expl_axi_awsize;
wire expl_axi_rvalid;
wire expl_axi_rready;
wire [`E203_XLEN-1:0] expl_axi_rdata;
wire [1:0] expl_axi_rresp;
wire expl_axi_rlast;
wire expl_axi_wvalid;
wire expl_axi_wready;
wire [`E203_XLEN-1:0] expl_axi_wdata;
wire [(`E203_XLEN/8)-1:0] expl_axi_wstrb;
wire expl_axi_wlast;
wire expl_axi_bvalid;
wire expl_axi_bready;
wire [1:0] expl_axi_bresp;
sirv_gnrl_icb2axi # (
.AXI_FIFO_DP (2), // We just add ping-pong buffer here to avoid any potential timing loops
// User can change it to 0 if dont care
.AXI_FIFO_CUT_READY (1), // This is to cut the back-pressure signal if you set as 1
.AW (32),
.FIFO_OUTS_NUM (4),// We only allow 4 oustandings at most for mem, user can configure it to any value
.FIFO_CUT_READY(1),
.DW (`E203_XLEN)
) u_expl_axi_icb2axi(
.i_icb_cmd_valid (expl_axi_icb_cmd_valid),
.i_icb_cmd_ready (expl_axi_icb_cmd_ready),
.i_icb_cmd_addr (expl_axi_icb_cmd_addr ),
.i_icb_cmd_read (expl_axi_icb_cmd_read ),
.i_icb_cmd_wdata (expl_axi_icb_cmd_wdata),
.i_icb_cmd_wmask (expl_axi_icb_cmd_wmask),
.i_icb_cmd_size (),
.i_icb_rsp_valid (expl_axi_icb_rsp_valid),
.i_icb_rsp_ready (expl_axi_icb_rsp_ready),
.i_icb_rsp_rdata (expl_axi_icb_rsp_rdata),
.i_icb_rsp_err (expl_axi_icb_rsp_err),
.o_axi_arvalid (expl_axi_arvalid),
.o_axi_arready (expl_axi_arready),
.o_axi_araddr (expl_axi_araddr ),
.o_axi_arcache (expl_axi_arcache),
.o_axi_arprot (expl_axi_arprot ),
.o_axi_arlock (expl_axi_arlock ),
.o_axi_arburst (expl_axi_arburst),
.o_axi_arlen (expl_axi_arlen ),
.o_axi_arsize (expl_axi_arsize ),
.o_axi_awvalid (expl_axi_awvalid),
.o_axi_awready (expl_axi_awready),
.o_axi_awaddr (expl_axi_awaddr ),
.o_axi_awcache (expl_axi_awcache),
.o_axi_awprot (expl_axi_awprot ),
.o_axi_awlock (expl_axi_awlock ),
.o_axi_awburst (expl_axi_awburst),
.o_axi_awlen (expl_axi_awlen ),
.o_axi_awsize (expl_axi_awsize ),
.o_axi_rvalid (expl_axi_rvalid ),
.o_axi_rready (expl_axi_rready ),
.o_axi_rdata (expl_axi_rdata ),
.o_axi_rresp (expl_axi_rresp ),
.o_axi_rlast (expl_axi_rlast ),
.o_axi_wvalid (expl_axi_wvalid ),
.o_axi_wready (expl_axi_wready ),
.o_axi_wdata (expl_axi_wdata ),
.o_axi_wstrb (expl_axi_wstrb ),
.o_axi_wlast (expl_axi_wlast ),
.o_axi_bvalid (expl_axi_bvalid ),
.o_axi_bready (expl_axi_bready ),
.o_axi_bresp (expl_axi_bresp ),
.clk (clk ),
.rst_n (bus_rst_n)
);
sirv_expl_axi_slv # (
.AW (32),
.DW (`E203_XLEN)
) u_perips_expl_axi_slv (
.axi_arvalid (expl_axi_arvalid),
.axi_arready (expl_axi_arready),
.axi_araddr (expl_axi_araddr ),
.axi_arcache (expl_axi_arcache),
.axi_arprot (expl_axi_arprot ),
.axi_arlock (expl_axi_arlock ),
.axi_arburst (expl_axi_arburst),
.axi_arlen (expl_axi_arlen ),
.axi_arsize (expl_axi_arsize ),
.axi_awvalid (expl_axi_awvalid),
.axi_awready (expl_axi_awready),
.axi_awaddr (expl_axi_awaddr ),
.axi_awcache (expl_axi_awcache),
.axi_awprot (expl_axi_awprot ),
.axi_awlock (expl_axi_awlock ),
.axi_awburst (expl_axi_awburst),
.axi_awlen (expl_axi_awlen ),
.axi_awsize (expl_axi_awsize ),
.axi_rvalid (expl_axi_rvalid ),
.axi_rready (expl_axi_rready ),
.axi_rdata (expl_axi_rdata ),
.axi_rresp (expl_axi_rresp ),
.axi_rlast (expl_axi_rlast ),
.axi_wvalid (expl_axi_wvalid ),
.axi_wready (expl_axi_wready ),
.axi_wdata (expl_axi_wdata ),
.axi_wstrb (expl_axi_wstrb ),
.axi_wlast (expl_axi_wlast ),
.axi_bvalid (expl_axi_bvalid ),
.axi_bready (expl_axi_bready ),
.axi_bresp (expl_axi_bresp ),
.clk (clk ),
.rst_n (rst_n)
);
endmodule |
module sirv_AsyncResetRegVec_1(
input clock,
input reset,
input [4:0] io_d,
output [4:0] io_q,
input io_en
);
wire reg_0_rst;
wire reg_0_clk;
wire reg_0_en;
wire reg_0_q;
wire reg_0_d;
wire reg_1_rst;
wire reg_1_clk;
wire reg_1_en;
wire reg_1_q;
wire reg_1_d;
wire reg_2_rst;
wire reg_2_clk;
wire reg_2_en;
wire reg_2_q;
wire reg_2_d;
wire reg_3_rst;
wire reg_3_clk;
wire reg_3_en;
wire reg_3_q;
wire reg_3_d;
wire reg_4_rst;
wire reg_4_clk;
wire reg_4_en;
wire reg_4_q;
wire reg_4_d;
wire T_8;
wire T_9;
wire T_10;
wire T_11;
wire T_12;
wire [1:0] T_13;
wire [1:0] T_14;
wire [2:0] T_15;
wire [4:0] T_16;
sirv_AsyncResetReg reg_0 (
.rst(reg_0_rst),
.clk(reg_0_clk),
.en(reg_0_en),
.q(reg_0_q),
.d(reg_0_d)
);
sirv_AsyncResetReg reg_1 (
.rst(reg_1_rst),
.clk(reg_1_clk),
.en(reg_1_en),
.q(reg_1_q),
.d(reg_1_d)
);
sirv_AsyncResetReg reg_2 (
.rst(reg_2_rst),
.clk(reg_2_clk),
.en(reg_2_en),
.q(reg_2_q),
.d(reg_2_d)
);
sirv_AsyncResetReg reg_3 (
.rst(reg_3_rst),
.clk(reg_3_clk),
.en(reg_3_en),
.q(reg_3_q),
.d(reg_3_d)
);
sirv_AsyncResetReg reg_4 (
.rst(reg_4_rst),
.clk(reg_4_clk),
.en(reg_4_en),
.q(reg_4_q),
.d(reg_4_d)
);
assign io_q = T_16;
assign reg_0_rst = reset;
assign reg_0_clk = clock;
assign reg_0_en = io_en;
assign reg_0_d = T_8;
assign reg_1_rst = reset;
assign reg_1_clk = clock;
assign reg_1_en = io_en;
assign reg_1_d = T_9;
assign reg_2_rst = reset;
assign reg_2_clk = clock;
assign reg_2_en = io_en;
assign reg_2_d = T_10;
assign reg_3_rst = reset;
assign reg_3_clk = clock;
assign reg_3_en = io_en;
assign reg_3_d = T_11;
assign reg_4_rst = reset;
assign reg_4_clk = clock;
assign reg_4_en = io_en;
assign reg_4_d = T_12;
assign T_8 = io_d[0];
assign T_9 = io_d[1];
assign T_10 = io_d[2];
assign T_11 = io_d[3];
assign T_12 = io_d[4];
assign T_13 = {reg_1_q,reg_0_q};
assign T_14 = {reg_4_q,reg_3_q};
assign T_15 = {T_14,reg_2_q};
assign T_16 = {T_15,T_13};
endmodule |
module sirv_queue_1(
input clock,
input reset,
output io_enq_ready,
input io_enq_valid,
input [7:0] io_enq_bits,
input io_deq_ready,
output io_deq_valid,
output [7:0] io_deq_bits,
output [3:0] io_count
);
reg [7:0] ram [0:7];
reg [31:0] GEN_0;
wire [7:0] ram_T_51_data;
wire [2:0] ram_T_51_addr;
wire [7:0] ram_T_35_data;
wire [2:0] ram_T_35_addr;
wire ram_T_35_mask;
wire ram_T_35_en;
reg [2:0] T_27;
reg [31:0] GEN_1;
reg [2:0] T_29;
reg [31:0] GEN_2;
reg maybe_full;
reg [31:0] GEN_3;
wire ptr_match;
wire T_32;
wire empty;
wire full;
wire T_33;
wire do_enq;
wire T_34;
wire do_deq;
wire [3:0] T_39;
wire [2:0] T_40;
wire [2:0] GEN_4;
wire [3:0] T_44;
wire [2:0] T_45;
wire [2:0] GEN_5;
wire T_46;
wire GEN_6;
wire T_48;
wire T_50;
wire [3:0] T_52;
wire [2:0] ptr_diff;
wire T_53;
wire [3:0] T_54;
assign io_enq_ready = T_50;
assign io_deq_valid = T_48;
assign io_deq_bits = ram_T_51_data;
assign io_count = T_54;
assign ram_T_51_addr = T_29;
assign ram_T_51_data = ram[ram_T_51_addr];
assign ram_T_35_data = io_enq_bits;
assign ram_T_35_addr = T_27;
assign ram_T_35_mask = do_enq;
assign ram_T_35_en = do_enq;
assign ptr_match = T_27 == T_29;
assign T_32 = maybe_full == 1'h0;
assign empty = ptr_match & T_32;
assign full = ptr_match & maybe_full;
assign T_33 = io_enq_ready & io_enq_valid;
assign do_enq = T_33;
assign T_34 = io_deq_ready & io_deq_valid;
assign do_deq = T_34;
assign T_39 = T_27 + 3'h1;
assign T_40 = T_39[2:0];
assign GEN_4 = do_enq ? T_40 : T_27;
assign T_44 = T_29 + 3'h1;
assign T_45 = T_44[2:0];
assign GEN_5 = do_deq ? T_45 : T_29;
assign T_46 = do_enq != do_deq;
assign GEN_6 = T_46 ? do_enq : maybe_full;
assign T_48 = empty == 1'h0;
assign T_50 = full == 1'h0;
assign T_52 = T_27 - T_29;
assign ptr_diff = T_52[2:0];
assign T_53 = maybe_full & ptr_match;
assign T_54 = {T_53,ptr_diff};
always @(posedge clock) begin // The RAM block does not need reset
if(ram_T_35_en & ram_T_35_mask) begin
ram[ram_T_35_addr] <= ram_T_35_data;
end
end
always @(posedge clock or posedge reset)
if (reset) begin
T_27 <= 3'h0;
end else begin
if (do_enq) begin
T_27 <= T_40;
end
end
always @(posedge clock or posedge reset)
if (reset) begin
T_29 <= 3'h0;
end else begin
if (do_deq) begin
T_29 <= T_45;
end
end
always @(posedge clock or posedge reset)
if (reset) begin
maybe_full <= 1'h0;
end else begin
if (T_46) begin
maybe_full <= do_enq;
end
end
endmodule |
module sirv_gnrl_ram
#(parameter DP = 32,
parameter DW = 32,
parameter FORCE_X2ZERO = 1,
parameter MW = 4,
parameter AW = 15
) (
input sd,
input ds,
input ls,
input rst_n,
input clk,
input cs,
input we,
input [AW-1:0] addr,
input [DW-1:0] din,
input [MW-1:0] wem,
output[DW-1:0] dout
);
//To add the ASIC or FPGA or Sim-model control here
// This is the Sim-model
//
`ifdef FPGA_SOURCE
sirv_sim_ram #(
.FORCE_X2ZERO (1'b0),
.DP (DP),
.AW (AW),
.MW (MW),
.DW (DW)
)u_sirv_sim_ram (
.clk (clk),
.din (din),
.addr (addr),
.cs (cs),
.we (we),
.wem (wem),
.dout (dout)
);
`else
sirv_sim_ram #(
.FORCE_X2ZERO (FORCE_X2ZERO),
.DP (DP),
.AW (AW),
.MW (MW),
.DW (DW)
)u_sirv_sim_ram (
.clk (clk),
.din (din),
.addr (addr),
.cs (cs),
.we (we),
.wem (wem),
.dout (dout)
);
`endif
endmodule |
module e203_cpu_top(
output [`E203_PC_SIZE-1:0] inspect_pc,
output inspect_dbg_irq ,
output inspect_mem_cmd_valid,
output inspect_mem_cmd_ready,
output inspect_mem_rsp_valid,
output inspect_mem_rsp_ready,
output inspect_core_clk ,
output core_csr_clk ,
// If this signal is high, then indicate the Core have executed WFI instruction
// and entered into the sleep state
output core_wfi,
// This signal is from our self-defined COUNTERSTOP (0xBFF) CSR's TM field
// software can programe this CSR to turn off the MTIME timer to save power
// If this signal is high, then the MTIME timer from CLINT module will stop counting
output tm_stop,
// This signal can be used to indicate the PC value for the core after reset
input [`E203_PC_SIZE-1:0] pc_rtvec,
///////////////////////////////////////
// The interface to Debug Module: Begin
//
// The synced debug interrupt back to Debug module
output dbg_irq_r,
// The debug mode CSR registers control interface from/to Debug module
output [`E203_PC_SIZE-1:0] cmt_dpc,
output cmt_dpc_ena,
output [3-1:0] cmt_dcause,
output cmt_dcause_ena,
output wr_dcsr_ena ,
output wr_dpc_ena ,
output wr_dscratch_ena,
output [32-1:0] wr_csr_nxt ,
input [32-1:0] dcsr_r ,
input [`E203_PC_SIZE-1:0] dpc_r ,
input [32-1:0] dscratch_r,
// The debug mode control signals from Debug Module
input dbg_mode,
input dbg_halt_r,
input dbg_step_r,
input dbg_ebreakm_r,
input dbg_stopcycle,
input dbg_irq_a,
// The interface to Debug Module: End
// This signal can be used to indicate the HART ID for this core
input [`E203_HART_ID_W-1:0] core_mhartid,
// The External Interrupt signal from PLIC
input ext_irq_a,
// The Software Interrupt signal from CLINT
input sft_irq_a,
// The Timer Interrupt signal from CLINT
input tmr_irq_a,
// The PMU control signal from PMU to control the TCM Shutdown
input tcm_sd,
// The PMU control signal from PMU to control the TCM Deep-Sleep
input tcm_ds,
`ifdef E203_HAS_ITCM_EXTITF //{
//////////////////////////////////////////////////////////////
// External interface (ICB) to access ITCM: Begin
// * Bus cmd channel
input ext2itcm_icb_cmd_valid,
output ext2itcm_icb_cmd_ready,
input [`E203_ITCM_ADDR_WIDTH-1:0] ext2itcm_icb_cmd_addr,
input ext2itcm_icb_cmd_read,
input [`E203_XLEN-1:0] ext2itcm_icb_cmd_wdata,
input [`E203_XLEN/8-1:0] ext2itcm_icb_cmd_wmask,
//
// * Bus RSP channel
output ext2itcm_icb_rsp_valid,
input ext2itcm_icb_rsp_ready,
output ext2itcm_icb_rsp_err ,
output [`E203_XLEN-1:0] ext2itcm_icb_rsp_rdata,
// External interface (ICB) to access ITCM: End
`endif//}
`ifdef E203_HAS_DTCM_EXTITF //{
//////////////////////////////////////////////////////////////
// External interface (ICB) to access DTCM: Start
// * Bus cmd channel
input ext2dtcm_icb_cmd_valid,
output ext2dtcm_icb_cmd_ready,
input [`E203_DTCM_ADDR_WIDTH-1:0] ext2dtcm_icb_cmd_addr,
input ext2dtcm_icb_cmd_read,
input [`E203_XLEN-1:0] ext2dtcm_icb_cmd_wdata,
input [`E203_XLEN/8-1:0] ext2dtcm_icb_cmd_wmask,
//
// * Bus RSP channel
output ext2dtcm_icb_rsp_valid,
input ext2dtcm_icb_rsp_ready,
output ext2dtcm_icb_rsp_err ,
output [`E203_XLEN-1:0] ext2dtcm_icb_rsp_rdata,
// External interface (ICB) to access DTCM: End
`endif//}
//////////////////////////////////////////////////////////////
// The Private Peripheral Interface (ICB): Begin
//
// * Bus cmd channel
output ppi_icb_cmd_valid,
input ppi_icb_cmd_ready,
output [`E203_ADDR_SIZE-1:0] ppi_icb_cmd_addr,
output ppi_icb_cmd_read,
output [`E203_XLEN-1:0] ppi_icb_cmd_wdata,
output [`E203_XLEN/8-1:0] ppi_icb_cmd_wmask,
//
// * Bus RSP channel
input ppi_icb_rsp_valid,
output ppi_icb_rsp_ready,
input ppi_icb_rsp_err ,
input [`E203_XLEN-1:0] ppi_icb_rsp_rdata,
// The Private Peripheral Interface (ICB): End
//////////////////////////////////////////////////////////////
// The CLINT Interface (ICB): Begin
output clint_icb_cmd_valid,
input clint_icb_cmd_ready,
output [`E203_ADDR_SIZE-1:0] clint_icb_cmd_addr,
output clint_icb_cmd_read,
output [`E203_XLEN-1:0] clint_icb_cmd_wdata,
output [`E203_XLEN/8-1:0] clint_icb_cmd_wmask,
//
// * Bus RSP channel
input clint_icb_rsp_valid,
output clint_icb_rsp_ready,
input clint_icb_rsp_err ,
input [`E203_XLEN-1:0] clint_icb_rsp_rdata,
// The CLINT Interface (ICB): End
//////////////////////////////////////////////////////////////
// The PLIC Interface (ICB): Begin
output plic_icb_cmd_valid,
input plic_icb_cmd_ready,
output [`E203_ADDR_SIZE-1:0] plic_icb_cmd_addr,
output plic_icb_cmd_read,
output [`E203_XLEN-1:0] plic_icb_cmd_wdata,
output [`E203_XLEN/8-1:0] plic_icb_cmd_wmask,
//
// * Bus RSP channel
input plic_icb_rsp_valid,
output plic_icb_rsp_ready,
input plic_icb_rsp_err ,
input [`E203_XLEN-1:0] plic_icb_rsp_rdata,
// The PLIC Interface (ICB): End
//////////////////////////////////////////////////////////////
// The Fast IO Interface (ICB): Begin
//
// * Bus cmd channel
output fio_icb_cmd_valid,
input fio_icb_cmd_ready,
output [`E203_ADDR_SIZE-1:0] fio_icb_cmd_addr,
output fio_icb_cmd_read,
output [`E203_XLEN-1:0] fio_icb_cmd_wdata,
output [`E203_XLEN/8-1:0] fio_icb_cmd_wmask,
//
// * Bus RSP channel
input fio_icb_rsp_valid,
output fio_icb_rsp_ready,
input fio_icb_rsp_err ,
input [`E203_XLEN-1:0] fio_icb_rsp_rdata,
// The Fast IO Interface (ICB): End
//////////////////////////////////////////////////////////////
// The System Memory Interface (ICB): Begin
//
// * Bus cmd channel
output mem_icb_cmd_valid,
input mem_icb_cmd_ready,
output [`E203_ADDR_SIZE-1:0] mem_icb_cmd_addr,
output mem_icb_cmd_read,
output [`E203_XLEN-1:0] mem_icb_cmd_wdata,
output [`E203_XLEN/8-1:0] mem_icb_cmd_wmask,
//
// * Bus RSP channel
input mem_icb_rsp_valid,
output mem_icb_rsp_ready,
input mem_icb_rsp_err ,
input [`E203_XLEN-1:0] mem_icb_rsp_rdata,
// The System Memory Interface (ICB): End
// The test mode signal
input test_mode,
// The Clock
input clk,
// The low-level active reset signal, treated as async
input rst_n
);
`ifdef E203_HAS_ITCM //{
wire itcm_ls;
wire rst_itcm;
wire itcm_ram_cs ;
wire itcm_ram_we ;
wire [`E203_ITCM_RAM_AW-1:0] itcm_ram_addr;
wire [`E203_ITCM_RAM_MW-1:0] itcm_ram_wem ;
wire [`E203_ITCM_RAM_DW-1:0] itcm_ram_din ;
`ifndef E203_HAS_LOCKSTEP//{
wire [`E203_ITCM_RAM_DW-1:0] itcm_ram_dout;
`endif//}
wire clk_itcm_ram ;
`endif//}
`ifdef E203_HAS_DTCM //{
wire dtcm_ls;
wire rst_dtcm;
wire dtcm_ram_cs ;
wire dtcm_ram_we ;
wire [`E203_DTCM_RAM_AW-1:0] dtcm_ram_addr;
wire [`E203_DTCM_RAM_MW-1:0] dtcm_ram_wem ;
wire [`E203_DTCM_RAM_DW-1:0] dtcm_ram_din ;
`ifndef E203_HAS_LOCKSTEP//{
wire [`E203_DTCM_RAM_DW-1:0] dtcm_ram_dout;
`endif//}
wire clk_dtcm_ram ;
`endif//}
`ifndef E203_HAS_LOCKSTEP//{
wire ppi_icb_rsp_excl_ok ;
wire fio_icb_rsp_excl_ok ;
wire plic_icb_rsp_excl_ok ;
wire clint_icb_rsp_excl_ok ;
wire mem_icb_rsp_excl_ok ;
`ifdef E203_HAS_PPI
wire ppi_icb_enable;
wire [`E203_ADDR_SIZE-1:0] ppi_region_indic;
`endif
`ifdef E203_HAS_PLIC
wire plic_icb_enable;
wire [`E203_ADDR_SIZE-1:0] plic_region_indic;
`endif
`ifdef E203_HAS_CLINT
wire clint_icb_enable;
wire [`E203_ADDR_SIZE-1:0] clint_region_indic;
`endif
`ifdef E203_HAS_MEM_ITF
wire mem_icb_enable;
`endif
`ifdef E203_HAS_FIO
wire fio_icb_enable;
wire [`E203_ADDR_SIZE-1:0] fio_region_indic;
`endif
`endif//}
assign ppi_icb_rsp_excl_ok = 1'b0;
assign fio_icb_rsp_excl_ok = 1'b0;
assign plic_icb_rsp_excl_ok = 1'b0;
assign clint_icb_rsp_excl_ok = 1'b0;
assign mem_icb_rsp_excl_ok = 1'b0;
`ifdef E203_HAS_PPI
assign ppi_icb_enable = 1'b1;
assign ppi_region_indic = `E203_PPI_ADDR_BASE;
`else
assign ppi_icb_enable = 1'b0;
`endif
`ifdef E203_HAS_PLIC
assign plic_icb_enable = 1'b1;
assign plic_region_indic = `E203_PLIC_ADDR_BASE;
`else
assign plic_icb_enable = 1'b0;
`endif
`ifdef E203_HAS_CLINT
assign clint_icb_enable = 1'b1;
assign clint_region_indic = `E203_CLINT_ADDR_BASE;
`else
assign clint_icb_enable = 1'b0;
`endif
`ifdef E203_HAS_MEM_ITF
assign mem_icb_enable = 1'b1;
`else
assign mem_icb_enable = 1'b0;
`endif
`ifdef E203_HAS_FIO
assign fio_icb_enable = 1'b1;
assign fio_region_indic = `E203_FIO_ADDR_BASE;
`else
assign fio_icb_enable = 1'b0;
`endif
e203_cpu #(.MASTER(1)) u_e203_cpu(
.inspect_pc (inspect_pc),
.inspect_dbg_irq (inspect_dbg_irq ),
.inspect_mem_cmd_valid (inspect_mem_cmd_valid),
.inspect_mem_cmd_ready (inspect_mem_cmd_ready),
.inspect_mem_rsp_valid (inspect_mem_rsp_valid),
.inspect_mem_rsp_ready (inspect_mem_rsp_ready),
.inspect_core_clk (inspect_core_clk ),
.core_csr_clk (core_csr_clk ),
.tm_stop (tm_stop),
.pc_rtvec(pc_rtvec),
`ifdef E203_HAS_ITCM //{
.itcm_ls (itcm_ls),
`endif//}
`ifdef E203_HAS_DTCM //{
.dtcm_ls (dtcm_ls),
`endif//}
.core_wfi (core_wfi),
.dbg_irq_r (dbg_irq_r ),
.cmt_dpc (cmt_dpc ),
.cmt_dpc_ena (cmt_dpc_ena ),
.cmt_dcause (cmt_dcause ),
.cmt_dcause_ena (cmt_dcause_ena ),
.wr_dcsr_ena (wr_dcsr_ena ),
.wr_dpc_ena (wr_dpc_ena ),
.wr_dscratch_ena (wr_dscratch_ena),
.wr_csr_nxt (wr_csr_nxt ),
.dcsr_r (dcsr_r ),
.dpc_r (dpc_r ),
.dscratch_r (dscratch_r ),
.dbg_mode (dbg_mode),
.dbg_halt_r (dbg_halt_r),
.dbg_step_r (dbg_step_r),
.dbg_ebreakm_r (dbg_ebreakm_r),
.dbg_stopcycle (dbg_stopcycle),
.core_mhartid (core_mhartid),
.dbg_irq_a (dbg_irq_a),
.ext_irq_a (ext_irq_a),
.sft_irq_a (sft_irq_a),
.tmr_irq_a (tmr_irq_a),
`ifdef E203_HAS_ITCM_EXTITF //{
.ext2itcm_icb_cmd_valid (ext2itcm_icb_cmd_valid),
.ext2itcm_icb_cmd_ready (ext2itcm_icb_cmd_ready),
.ext2itcm_icb_cmd_addr (ext2itcm_icb_cmd_addr ),
.ext2itcm_icb_cmd_read (ext2itcm_icb_cmd_read ),
.ext2itcm_icb_cmd_wdata (ext2itcm_icb_cmd_wdata),
.ext2itcm_icb_cmd_wmask (ext2itcm_icb_cmd_wmask),
.ext2itcm_icb_rsp_valid (ext2itcm_icb_rsp_valid),
.ext2itcm_icb_rsp_ready (ext2itcm_icb_rsp_ready),
.ext2itcm_icb_rsp_err (ext2itcm_icb_rsp_err ),
.ext2itcm_icb_rsp_rdata (ext2itcm_icb_rsp_rdata),
`endif//}
`ifdef E203_HAS_DTCM_EXTITF //{
.ext2dtcm_icb_cmd_valid (ext2dtcm_icb_cmd_valid),
.ext2dtcm_icb_cmd_ready (ext2dtcm_icb_cmd_ready),
.ext2dtcm_icb_cmd_addr (ext2dtcm_icb_cmd_addr ),
.ext2dtcm_icb_cmd_read (ext2dtcm_icb_cmd_read ),
.ext2dtcm_icb_cmd_wdata (ext2dtcm_icb_cmd_wdata),
.ext2dtcm_icb_cmd_wmask (ext2dtcm_icb_cmd_wmask),
.ext2dtcm_icb_rsp_valid (ext2dtcm_icb_rsp_valid),
.ext2dtcm_icb_rsp_ready (ext2dtcm_icb_rsp_ready),
.ext2dtcm_icb_rsp_err (ext2dtcm_icb_rsp_err ),
.ext2dtcm_icb_rsp_rdata (ext2dtcm_icb_rsp_rdata),
`endif//}
.ppi_region_indic (ppi_region_indic),
.ppi_icb_enable (ppi_icb_enable),
.ppi_icb_cmd_valid (ppi_icb_cmd_valid),
.ppi_icb_cmd_ready (ppi_icb_cmd_ready),
.ppi_icb_cmd_addr (ppi_icb_cmd_addr ),
.ppi_icb_cmd_read (ppi_icb_cmd_read ),
.ppi_icb_cmd_wdata (ppi_icb_cmd_wdata),
.ppi_icb_cmd_wmask (ppi_icb_cmd_wmask),
.ppi_icb_cmd_lock (),
.ppi_icb_cmd_excl (),
.ppi_icb_cmd_size (),
.ppi_icb_rsp_valid (ppi_icb_rsp_valid),
.ppi_icb_rsp_ready (ppi_icb_rsp_ready),
.ppi_icb_rsp_err (ppi_icb_rsp_err ),
.ppi_icb_rsp_excl_ok (ppi_icb_rsp_excl_ok ),
.ppi_icb_rsp_rdata (ppi_icb_rsp_rdata),
.clint_region_indic (clint_region_indic),
.clint_icb_enable (clint_icb_enable),
.clint_icb_cmd_valid (clint_icb_cmd_valid),
.clint_icb_cmd_ready (clint_icb_cmd_ready),
.clint_icb_cmd_addr (clint_icb_cmd_addr ),
.clint_icb_cmd_read (clint_icb_cmd_read ),
.clint_icb_cmd_wdata (clint_icb_cmd_wdata),
.clint_icb_cmd_wmask (clint_icb_cmd_wmask),
.clint_icb_cmd_lock (),
.clint_icb_cmd_excl (),
.clint_icb_cmd_size (),
.clint_icb_rsp_valid (clint_icb_rsp_valid),
.clint_icb_rsp_ready (clint_icb_rsp_ready),
.clint_icb_rsp_err (clint_icb_rsp_err ),
.clint_icb_rsp_excl_ok (clint_icb_rsp_excl_ok ),
.clint_icb_rsp_rdata (clint_icb_rsp_rdata),
.plic_region_indic (plic_region_indic),
.plic_icb_enable (plic_icb_enable),
.plic_icb_cmd_valid (plic_icb_cmd_valid),
.plic_icb_cmd_ready (plic_icb_cmd_ready),
.plic_icb_cmd_addr (plic_icb_cmd_addr ),
.plic_icb_cmd_read (plic_icb_cmd_read ),
.plic_icb_cmd_wdata (plic_icb_cmd_wdata),
.plic_icb_cmd_wmask (plic_icb_cmd_wmask),
.plic_icb_cmd_lock (),
.plic_icb_cmd_excl (),
.plic_icb_cmd_size (),
.plic_icb_rsp_valid (plic_icb_rsp_valid),
.plic_icb_rsp_ready (plic_icb_rsp_ready),
.plic_icb_rsp_err (plic_icb_rsp_err ),
.plic_icb_rsp_excl_ok (plic_icb_rsp_excl_ok ),
.plic_icb_rsp_rdata (plic_icb_rsp_rdata),
`ifdef E203_HAS_FIO //{
.fio_icb_enable (fio_icb_enable),
.fio_region_indic (fio_region_indic),
.fio_icb_cmd_valid (fio_icb_cmd_valid),
.fio_icb_cmd_ready (fio_icb_cmd_ready),
.fio_icb_cmd_addr (fio_icb_cmd_addr ),
.fio_icb_cmd_read (fio_icb_cmd_read ),
.fio_icb_cmd_wdata (fio_icb_cmd_wdata),
.fio_icb_cmd_wmask (fio_icb_cmd_wmask),
.fio_icb_cmd_lock (),
.fio_icb_cmd_excl (),
.fio_icb_cmd_size (),
.fio_icb_rsp_valid (fio_icb_rsp_valid),
.fio_icb_rsp_ready (fio_icb_rsp_ready),
.fio_icb_rsp_err (fio_icb_rsp_err ),
.fio_icb_rsp_excl_ok (fio_icb_rsp_excl_ok ),
.fio_icb_rsp_rdata (fio_icb_rsp_rdata),
`endif//}
`ifdef E203_HAS_MEM_ITF //{
.mem_icb_enable (mem_icb_enable),
.mem_icb_cmd_valid (mem_icb_cmd_valid),
.mem_icb_cmd_ready (mem_icb_cmd_ready),
.mem_icb_cmd_addr (mem_icb_cmd_addr ),
.mem_icb_cmd_read (mem_icb_cmd_read ),
.mem_icb_cmd_wdata (mem_icb_cmd_wdata),
.mem_icb_cmd_wmask (mem_icb_cmd_wmask),
.mem_icb_cmd_lock (),
.mem_icb_cmd_excl (),
.mem_icb_cmd_size (),
.mem_icb_cmd_burst (),
.mem_icb_cmd_beat (),
.mem_icb_rsp_valid (mem_icb_rsp_valid),
.mem_icb_rsp_ready (mem_icb_rsp_ready),
.mem_icb_rsp_err (mem_icb_rsp_err ),
.mem_icb_rsp_excl_ok(mem_icb_rsp_excl_ok ),
.mem_icb_rsp_rdata (mem_icb_rsp_rdata),
`endif//}
`ifdef E203_HAS_ITCM //{
.itcm_ram_cs (itcm_ram_cs ),
.itcm_ram_we (itcm_ram_we ),
.itcm_ram_addr (itcm_ram_addr),
.itcm_ram_wem (itcm_ram_wem ),
.itcm_ram_din (itcm_ram_din ),
.itcm_ram_dout (itcm_ram_dout),
.clk_itcm_ram (clk_itcm_ram ),
.rst_itcm(rst_itcm),
`endif//}
`ifdef E203_HAS_DTCM //{
.dtcm_ram_cs (dtcm_ram_cs ),
.dtcm_ram_we (dtcm_ram_we ),
.dtcm_ram_addr (dtcm_ram_addr),
.dtcm_ram_wem (dtcm_ram_wem ),
.dtcm_ram_din (dtcm_ram_din ),
.dtcm_ram_dout (dtcm_ram_dout),
.clk_dtcm_ram (clk_dtcm_ram ),
.rst_dtcm(rst_dtcm),
`endif//}
.test_mode (test_mode),
`ifndef E203_HAS_LOCKSTEP//{
`endif//}
.rst_n (rst_n),
.clk (clk )
);
e203_srams u_e203_srams(
`ifdef E203_HAS_DTCM //{
.dtcm_ram_sd (tcm_sd),
.dtcm_ram_ds (tcm_ds),
.dtcm_ram_ls (dtcm_ls),
.dtcm_ram_cs (dtcm_ram_cs ),
.dtcm_ram_we (dtcm_ram_we ),
.dtcm_ram_addr (dtcm_ram_addr),
.dtcm_ram_wem (dtcm_ram_wem ),
.dtcm_ram_din (dtcm_ram_din ),
.dtcm_ram_dout (dtcm_ram_dout),
.clk_dtcm_ram (clk_dtcm_ram ),
.rst_dtcm(rst_dtcm),
`endif//}
`ifdef E203_HAS_ITCM //{
.itcm_ram_sd (tcm_sd),
.itcm_ram_ds (tcm_ds),
.itcm_ram_ls (itcm_ls),
.itcm_ram_cs (itcm_ram_cs ),
.itcm_ram_we (itcm_ram_we ),
.itcm_ram_addr (itcm_ram_addr),
.itcm_ram_wem (itcm_ram_wem ),
.itcm_ram_din (itcm_ram_din ),
.itcm_ram_dout (itcm_ram_dout),
.clk_itcm_ram (clk_itcm_ram ),
.rst_itcm(rst_itcm),
`endif//}
.test_mode (test_mode)
);
endmodule |
module sirv_uartgpioport(
input clock,
input reset,
input io_uart_txd,
output io_uart_rxd,
input io_pins_rxd_i_ival,
output io_pins_rxd_o_oval,
output io_pins_rxd_o_oe,
output io_pins_rxd_o_ie,
output io_pins_rxd_o_pue,
output io_pins_rxd_o_ds,
input io_pins_txd_i_ival,
output io_pins_txd_o_oval,
output io_pins_txd_o_oe,
output io_pins_txd_o_ie,
output io_pins_txd_o_pue,
output io_pins_txd_o_ds
);
assign io_uart_rxd = io_pins_rxd_i_ival;
assign io_pins_rxd_o_oval = 1'h0;
assign io_pins_rxd_o_oe = 1'h0;
assign io_pins_rxd_o_ie = 1'h1;
assign io_pins_rxd_o_pue = 1'h0;
assign io_pins_rxd_o_ds = 1'h0;
assign io_pins_txd_o_oval = io_uart_txd;
assign io_pins_txd_o_oe = 1'h1;
assign io_pins_txd_o_ie = 1'h0;
assign io_pins_txd_o_pue = 1'h0;
assign io_pins_txd_o_ds = 1'h0;
endmodule |
module e203_exu_excp(
output commit_trap,
output core_wfi,
output wfi_halt_ifu_req,
output wfi_halt_exu_req,
input wfi_halt_ifu_ack,
input wfi_halt_exu_ack,
input amo_wait,
output alu_excp_i_ready,
input alu_excp_i_valid ,
input alu_excp_i_ld ,
input alu_excp_i_stamo ,
input alu_excp_i_misalgn ,
input alu_excp_i_buserr ,
input alu_excp_i_ecall ,
input alu_excp_i_ebreak ,
input alu_excp_i_wfi ,
input alu_excp_i_ifu_misalgn ,
input alu_excp_i_ifu_buserr ,
input alu_excp_i_ifu_ilegl ,
input [`E203_ADDR_SIZE-1:0] alu_excp_i_badaddr,
input [`E203_PC_SIZE-1:0] alu_excp_i_pc,
input [`E203_INSTR_SIZE-1:0] alu_excp_i_instr,
input alu_excp_i_pc_vld,
output longp_excp_i_ready,
input longp_excp_i_valid,
input longp_excp_i_ld,
input longp_excp_i_st,// 1: load, 0: store
input longp_excp_i_buserr , // The load/store bus-error exception generated
input longp_excp_i_insterr,
input [`E203_ADDR_SIZE-1:0] longp_excp_i_badaddr,
input [`E203_PC_SIZE-1:0] longp_excp_i_pc,
input excpirq_flush_ack,
output excpirq_flush_req,
output nonalu_excpirq_flush_req_raw,
output [`E203_PC_SIZE-1:0] excpirq_flush_add_op1,
output [`E203_PC_SIZE-1:0] excpirq_flush_add_op2,
`ifdef E203_TIMING_BOOST//}
output [`E203_PC_SIZE-1:0] excpirq_flush_pc,
`endif//}
input [`E203_XLEN-1:0] csr_mtvec_r,
input cmt_dret_ena,
input cmt_ena,
output [`E203_ADDR_SIZE-1:0] cmt_badaddr,
output [`E203_PC_SIZE-1:0] cmt_epc,
output [`E203_XLEN-1:0] cmt_cause,
output cmt_badaddr_ena,
output cmt_epc_ena,
output cmt_cause_ena,
output cmt_status_ena,
output [`E203_PC_SIZE-1:0] cmt_dpc,
output cmt_dpc_ena,
output [3-1:0] cmt_dcause,
output cmt_dcause_ena,
input dbg_irq_r,
input [`E203_LIRQ_NUM-1:0] lcl_irq_r,
input ext_irq_r,
input sft_irq_r,
input tmr_irq_r,
input status_mie_r,
input mtie_r,
input msie_r,
input meie_r,
input dbg_mode,
input dbg_halt_r,
input dbg_step_r,
input dbg_ebreakm_r,
input oitf_empty,
input u_mode,
input s_mode,
input h_mode,
input m_mode,
output excp_active,
input clk,
input rst_n
);
////////////////////////////////////////////////////////////////////////////
// Because the core's clock may be gated when it is idle, we need to check
// if the interrupts is coming, and generate an active indication, and use
// this active signal to turn on core's clock
wire irq_req_active;
wire nonalu_dbg_entry_req_raw;
assign excp_active = irq_req_active | nonalu_dbg_entry_req_raw;
////////////////////////////////////////////////////////////////////////////
// WFI flag generation
//
wire wfi_req_hsked = (wfi_halt_ifu_req & wfi_halt_ifu_ack & wfi_halt_exu_req & wfi_halt_exu_ack)
;
// The wfi_flag will be set if there is a new WFI instruction halt req handshaked
wire wfi_flag_set = wfi_req_hsked;
// The wfi_flag will be cleared if there is interrupt pending, or debug entry request
wire wfi_irq_req;
wire dbg_entry_req;
wire wfi_flag_r;
wire wfi_flag_clr = (wfi_irq_req | dbg_entry_req);// & wfi_flag_r;// Here we cannot use this flag_r
wire wfi_flag_ena = wfi_flag_set | wfi_flag_clr;
// If meanwhile set and clear, then clear preempt
wire wfi_flag_nxt = wfi_flag_set & (~wfi_flag_clr);
sirv_gnrl_dfflr #(1) wfi_flag_dfflr (wfi_flag_ena, wfi_flag_nxt, wfi_flag_r, clk, rst_n);
assign core_wfi = wfi_flag_r & (~wfi_flag_clr);
// The wfi_halt_req will be set if there is a new WFI instruction committed
// And note in debug mode WFI is treated as nop
wire wfi_cmt_ena = alu_excp_i_wfi & cmt_ena;
wire wfi_halt_req_set = wfi_cmt_ena & (~dbg_mode);
// The wfi_halt_req will be cleared same as wfi_flag_r
wire wfi_halt_req_clr = wfi_flag_clr;
wire wfi_halt_req_ena = wfi_halt_req_set | wfi_halt_req_clr;
// If meanwhile set and clear, then clear preempt
wire wfi_halt_req_nxt = wfi_halt_req_set & (~wfi_halt_req_clr);
wire wfi_halt_req_r;
sirv_gnrl_dfflr #(1) wfi_halt_req_dfflr (wfi_halt_req_ena, wfi_halt_req_nxt, wfi_halt_req_r, clk, rst_n);
// In order to make sure the flush to IFU and halt to IFU is not asserte at same cycle
// we use the clr signal here to qualify it
assign wfi_halt_ifu_req = (wfi_halt_req_r & (~wfi_halt_req_clr))
;
// To cut the comb loops, we dont use the clr signal here to qualify,
// the outcome is the halt-to-exu will be deasserted 1 cycle later than to-IFU
// but it doesnt matter much.
assign wfi_halt_exu_req = wfi_halt_req_r
;
wire irq_req;
wire longp_need_flush;
wire alu_need_flush;
wire dbg_ebrk_req;
wire dbg_trig_req;
////////////////////////////////////////////////////////////////////////////
// The Exception generate included several cases, priority from top to down
// *** Long-pipe triggered exception
// ---- Must wait the PC vld
// *** DebugMode-entry triggered exception (included ALU ebreakm)
// ---- Must wait the OITF empty and PC vld
// *** IRQ triggered exception
// ---- Must wait the OITF empty and PC vld
// *** ALU triggered exception (excluded the ebreakm into debug-mode)
// ---- Must wait the OITF empty
// Exclude the pc_vld for longp, to just always make sure the longp can always accepted
wire longp_excp_flush_req = longp_need_flush ;
assign longp_excp_i_ready = excpirq_flush_ack;
// ^^^ Below we qualified the pc_vld signal to IRQ and Debug-entry req, why?
// -- The Asyn-precise-excp (include IRQ and Debug-entry exception)
// need to use the next upcoming (not yet commited) instruction's PC
// for the mepc value, so we must wait next valid instruction coming
// and use its PC.
// -- The pc_vld indicate is just used to indicate next instruction's valid
// PC value.
// ^^^ Then the questions are coming, is there a possible that there is no pc_vld
// comes forever? and then this async-precise-exception never
// get served, and then become a deadlock?
// -- It should not be. Becuase:
// The IFU is always actively fetching next instructions, never stop,
// so ideally it will always provide next valid instructions as
// long as the Ifetch-path (bus to external memory or ITCM) is not hang
// (no bus response returned).
// ^^^ Then if there possible the Ifetch-path is hang? For examples:
// -- The Ifetched external memory does not provide response because of the External IRQ is not
// accepted by core.
// ** How could it be? This should not happen, otherwise it is a SoC bug.
//
wire dbg_entry_flush_req = dbg_entry_req & oitf_empty & alu_excp_i_pc_vld & (~longp_need_flush);
wire alu_excp_i_ready4dbg = (excpirq_flush_ack & oitf_empty & alu_excp_i_pc_vld & (~longp_need_flush));
wire irq_flush_req = irq_req & oitf_empty & alu_excp_i_pc_vld
& (~dbg_entry_req)
& (~longp_need_flush);
wire alu_excp_flush_req = alu_excp_i_valid & alu_need_flush & oitf_empty
& (~irq_req)
& (~dbg_entry_req)
& (~longp_need_flush);
wire nonalu_dbg_entry_req;
wire alu_excp_i_ready4nondbg = alu_need_flush ?
(excpirq_flush_ack & oitf_empty & (~irq_req) & (~nonalu_dbg_entry_req) & (~longp_need_flush))
: ( // The other higher priorty flush will override ALU commit
(~irq_req)
& (~nonalu_dbg_entry_req)
& (~longp_need_flush)
);
wire alu_ebreakm_flush_req_novld;
wire alu_dbgtrig_flush_req_novld;
assign alu_excp_i_ready = (alu_ebreakm_flush_req_novld | alu_dbgtrig_flush_req_novld) ? alu_excp_i_ready4dbg : alu_excp_i_ready4nondbg;
assign excpirq_flush_req = longp_excp_flush_req | dbg_entry_flush_req | irq_flush_req | alu_excp_flush_req;
wire all_excp_flush_req = longp_excp_flush_req | alu_excp_flush_req;
assign nonalu_excpirq_flush_req_raw =
longp_need_flush |
nonalu_dbg_entry_req_raw |
irq_req ;
wire excpirq_taken_ena = excpirq_flush_req & excpirq_flush_ack;
assign commit_trap = excpirq_taken_ena;
wire excp_taken_ena = all_excp_flush_req & excpirq_taken_ena;
wire irq_taken_ena = irq_flush_req & excpirq_taken_ena;
wire dbg_entry_taken_ena = dbg_entry_flush_req & excpirq_taken_ena;
assign excpirq_flush_add_op1 = dbg_entry_flush_req ? `E203_PC_SIZE'h800 : (all_excp_flush_req & dbg_mode) ? `E203_PC_SIZE'h808 : csr_mtvec_r;
assign excpirq_flush_add_op2 = dbg_entry_flush_req ? `E203_PC_SIZE'h0 : (all_excp_flush_req & dbg_mode) ? `E203_PC_SIZE'h0 : `E203_PC_SIZE'b0;
`ifdef E203_TIMING_BOOST//}
assign excpirq_flush_pc = dbg_entry_flush_req ? `E203_PC_SIZE'h800 : (all_excp_flush_req & dbg_mode) ? `E203_PC_SIZE'h808 : csr_mtvec_r;
`endif//}
////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////
// The Long-pipe triggered Exception
//
assign longp_need_flush = longp_excp_i_valid;// The longp come to excp
// module always ask for excepiton
////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////
// The DebugMode-entry triggered Exception
//
wire step_req_r;
wire alu_ebreakm_flush_req;
wire alu_dbgtrig_flush_req;
// The priority from top to down
// dbg_trig_req ? 3'd2 :
// dbg_ebrk_req ? 3'd1 :
// dbg_irq_req ? 3'd3 :
// dbg_step_req ? 3'd4 :
// dbg_halt_req ? 3'd5 :
// Since the step_req_r is last cycle generated indicated, means last instruction is single-step
// and it have been commited in non debug-mode, and then this cyclc step_req_r is the of the highest priority
wire dbg_step_req = step_req_r;
assign dbg_trig_req = alu_dbgtrig_flush_req & (~step_req_r);
assign dbg_ebrk_req = alu_ebreakm_flush_req & (~alu_dbgtrig_flush_req) & (~step_req_r);
wire dbg_irq_req = dbg_irq_r & (~alu_ebreakm_flush_req) & (~alu_dbgtrig_flush_req) & (~step_req_r);
wire nonalu_dbg_irq_req = dbg_irq_r & (~step_req_r);
// The step have higher priority, and will preempt the halt
wire dbg_halt_req = dbg_halt_r & (~dbg_irq_r) & (~alu_ebreakm_flush_req) & (~alu_dbgtrig_flush_req) & (~step_req_r) & (~dbg_step_r);
wire nonalu_dbg_halt_req = dbg_halt_r & (~dbg_irq_r) & (~step_req_r) & (~dbg_step_r);
// The debug-step request will be set when currently the step_r is high, and one
// instruction (in non debug_mode) have been executed
// The step request will be clear when
// core enter into the debug-mode
wire step_req_set = (~dbg_mode) & dbg_step_r & cmt_ena & (~dbg_entry_taken_ena);
wire step_req_clr = dbg_entry_taken_ena;
wire step_req_ena = step_req_set | step_req_clr;
wire step_req_nxt = step_req_set | (~step_req_clr);
sirv_gnrl_dfflr #(1) step_req_dfflr (step_req_ena, step_req_nxt, step_req_r, clk, rst_n);
// The debug-mode will mask off the debug-mode-entry
wire dbg_entry_mask = dbg_mode;
assign dbg_entry_req = (~dbg_entry_mask) & (
// Why do we put a AMO_wait here, because the AMO instructions
// is atomic, we must wait it to complete its all atomic operations
// and during wait cycles irq must be masked, otherwise the irq_req
// will block ALU commit (including AMO) and cause a deadlock
//
// Note: Only the async irq and halt and trig need to have this amo_wait to check
// others are sync event, no need to check with this
(dbg_irq_req & (~amo_wait))
| (dbg_halt_req & (~amo_wait))
| dbg_step_req
| (dbg_trig_req & (~amo_wait))
| dbg_ebrk_req
);
assign nonalu_dbg_entry_req = (~dbg_entry_mask) & (
(nonalu_dbg_irq_req & (~amo_wait))
| (nonalu_dbg_halt_req & (~amo_wait))
| dbg_step_req
//| (dbg_trig_req & (~amo_wait))
//| dbg_ebrk_req
);
assign nonalu_dbg_entry_req_raw = (~dbg_entry_mask) & (
dbg_irq_r
| dbg_halt_r
| step_req_r
//| dbg_trig_req
//| dbg_ebrk_req
);
////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////
// The IRQ triggered Exception
//
// The debug mode will mask off the interrupts
// The single-step mode will mask off the interrupts
wire irq_mask = dbg_mode | dbg_step_r | (~status_mie_r)
// Why do we put a AMO_wait here, because the AMO instructions
// is atomic, we must wait it to complete its all atomic operations
// and during wait cycles irq must be masked, otherwise the irq_req
// will block ALU commit (including AMO) and cause a deadlock
// Dont need to worry about the clock gating issue, if amo_wait,
// then defefinitely the ALU is active, and clock on
| amo_wait;
wire wfi_irq_mask = dbg_mode | dbg_step_r;
// Why dont we put amo_wait here, because this is for IRQ to wake
// up the core from sleep mode, the core was in sleep mode, then
// means there is no chance for it to still executing the AMO instructions
// with oustanding uops, so we dont need to worry about it.
wire irq_req_raw = (
//(|lcl_irq_r) // not support this now
(ext_irq_r & meie_r)
| (sft_irq_r & msie_r)
| (tmr_irq_r & mtie_r)
);
assign irq_req = (~irq_mask) & irq_req_raw;
assign wfi_irq_req = (~wfi_irq_mask) & irq_req_raw;
assign irq_req_active = wfi_flag_r ? wfi_irq_req : irq_req;
wire [`E203_XLEN-1:0] irq_cause;
assign irq_cause[31] = 1'b1;
assign irq_cause[30:4] = 27'b0;
assign irq_cause[3:0] = (sft_irq_r & msie_r) ? 4'd3 : // 3 Machine software interrupt
(tmr_irq_r & mtie_r) ? 4'd7 : // 7 Machine timer interrupt
(ext_irq_r & meie_r) ? 4'd11 : // 11 Machine external interrupt
4'b0;
////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////
// The ALU triggered Exception
// The ebreak instruction will generated regular exception when the ebreakm
// bit of DCSR reg is not set
wire alu_excp_i_ebreak4excp = (alu_excp_i_ebreak & ((~dbg_ebreakm_r) | dbg_mode))
;
// The ebreak instruction will enter into the debug-mode when the ebreakm
// bit of DCSR reg is set
wire alu_excp_i_ebreak4dbg = alu_excp_i_ebreak
& (~alu_need_flush)// override by other alu exceptions
& dbg_ebreakm_r
& (~dbg_mode);//Not in debug mode
assign alu_ebreakm_flush_req = alu_excp_i_valid & alu_excp_i_ebreak4dbg;
assign alu_ebreakm_flush_req_novld = alu_excp_i_ebreak4dbg;
`ifndef E203_SUPPORT_TRIGM//{
// We dont support the HW Trigger Module yet
assign alu_dbgtrig_flush_req_novld = 1'b0;
assign alu_dbgtrig_flush_req = 1'b0;
`endif
assign alu_need_flush =
( alu_excp_i_misalgn
| alu_excp_i_buserr
| alu_excp_i_ebreak4excp
| alu_excp_i_ecall
| alu_excp_i_ifu_misalgn
| alu_excp_i_ifu_buserr
| alu_excp_i_ifu_ilegl
);
////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////
// Update the CSRs (Mcause, .etc)
wire longp_excp_flush_req_ld = longp_excp_flush_req & longp_excp_i_ld;
wire longp_excp_flush_req_st = longp_excp_flush_req & longp_excp_i_st;
wire longp_excp_flush_req_insterr = longp_excp_flush_req & longp_excp_i_insterr;
wire alu_excp_flush_req_ld = alu_excp_flush_req & alu_excp_i_ld;
wire alu_excp_flush_req_stamo = alu_excp_flush_req & alu_excp_i_stamo;
wire alu_excp_flush_req_ebreak = (alu_excp_flush_req & alu_excp_i_ebreak4excp);
wire alu_excp_flush_req_ecall = (alu_excp_flush_req & alu_excp_i_ecall);
wire alu_excp_flush_req_ifu_misalgn = (alu_excp_flush_req & alu_excp_i_ifu_misalgn);
wire alu_excp_flush_req_ifu_buserr = (alu_excp_flush_req & alu_excp_i_ifu_buserr);
wire alu_excp_flush_req_ifu_ilegl = (alu_excp_flush_req & alu_excp_i_ifu_ilegl);
wire alu_excp_flush_req_ld_misalgn = (alu_excp_flush_req_ld & alu_excp_i_misalgn);// ALU load misalign
wire alu_excp_flush_req_ld_buserr = (alu_excp_flush_req_ld & alu_excp_i_buserr);// ALU load bus error
wire alu_excp_flush_req_stamo_misalgn = (alu_excp_flush_req_stamo & alu_excp_i_misalgn);// ALU store/AMO misalign
wire alu_excp_flush_req_stamo_buserr = (alu_excp_flush_req_stamo & alu_excp_i_buserr);// ALU store/AMO bus error
wire longp_excp_flush_req_ld_buserr = (longp_excp_flush_req_ld & longp_excp_i_buserr);// Longpipe load bus error
wire longp_excp_flush_req_st_buserr = (longp_excp_flush_req_st & longp_excp_i_buserr);// Longpipe store bus error
wire excp_flush_by_alu_agu =
alu_excp_flush_req_ld_misalgn
| alu_excp_flush_req_ld_buserr
| alu_excp_flush_req_stamo_misalgn
| alu_excp_flush_req_stamo_buserr;
wire excp_flush_by_longp_ldst =
longp_excp_flush_req_ld_buserr
| longp_excp_flush_req_st_buserr;
wire [`E203_XLEN-1:0] excp_cause;
assign excp_cause[31:5] = 27'b0;
assign excp_cause[4:0] =
alu_excp_flush_req_ifu_misalgn? 5'd0 //Instruction address misaligned
: alu_excp_flush_req_ifu_buserr ? 5'd1 //Instruction access fault
: alu_excp_flush_req_ifu_ilegl ? 5'd2 //Illegal instruction
: alu_excp_flush_req_ebreak ? 5'd3 //Breakpoint
: alu_excp_flush_req_ld_misalgn ? 5'd4 //load address misalign
: (longp_excp_flush_req_ld_buserr | alu_excp_flush_req_ld_buserr) ? 5'd5 //load access fault
: alu_excp_flush_req_stamo_misalgn ? 5'd6 //Store/AMO address misalign
: (longp_excp_flush_req_st_buserr | alu_excp_flush_req_stamo_buserr) ? 5'd7 //Store/AMO access fault
: (alu_excp_flush_req_ecall & u_mode) ? 5'd8 //Environment call from U-mode
: (alu_excp_flush_req_ecall & s_mode) ? 5'd9 //Environment call from S-mode
: (alu_excp_flush_req_ecall & h_mode) ? 5'd10 //Environment call from H-mode
: (alu_excp_flush_req_ecall & m_mode) ? 5'd11 //Environment call from M-mode
: longp_excp_flush_req_insterr ? 5'd16// This only happened for the EAI long instructions actually
: 5'h1F;//Otherwise a reserved value
// mbadaddr is an XLEN-bit read-write register formatted as shown in Figure 3.21. When
// * a hardware breakpoint is triggered,
// * an instruction-fetch address-misaligned or access exception
// * load address-misaligned or access exception
// * store address-misaligned or access exception
// occurs, mbadaddr is written with the faulting address.
// In Priv SPEC v1.10, the mbadaddr have been replaced to mtval, and added following points:
// * On an illegal instruction trap, mtval is written with the first XLEN bits of the faulting
// instruction .
// * For other exceptions, mtval is set to zero, but a future standard may redefine mtval's
// setting for other exceptions.
//
wire excp_flush_req_ld_misalgn = alu_excp_flush_req_ld_misalgn;
wire excp_flush_req_ld_buserr = alu_excp_flush_req_ld_buserr | longp_excp_flush_req_ld_buserr;
//wire cmt_badaddr_update = all_excp_flush_req &
// (
// alu_excp_flush_req_ebreak
// | alu_excp_flush_req_ifu_misalgn
// | alu_excp_flush_req_ifu_buserr
// | excp_flush_by_alu_agu
// | excp_flush_by_longp_ldst);
// Per Priv Spec v1.10, all trap need to update this register
// * When a trap is taken into M-mode, mtval is written with exception-specific
// information to assist software in handling the trap.
wire cmt_badaddr_update = excpirq_flush_req;
assign cmt_badaddr = excp_flush_by_longp_ldst ? longp_excp_i_badaddr :
excp_flush_by_alu_agu ? alu_excp_i_badaddr :
(alu_excp_flush_req_ebreak
| alu_excp_flush_req_ifu_misalgn
| alu_excp_flush_req_ifu_buserr) ? alu_excp_i_pc :
alu_excp_flush_req_ifu_ilegl ? alu_excp_i_instr :
`E203_ADDR_SIZE'b0;
// We use the exact PC of long-instruction when exception happened, but
// to note since the later instruction may already commited, so long-pipe
// excpetion is async-imprecise exceptions
assign cmt_epc = longp_excp_i_valid ? longp_excp_i_pc : alu_excp_i_pc;
assign cmt_cause = excp_taken_ena ? excp_cause : irq_cause;
// Any trap include exception and irq (exclude dbg_irq) will update mstatus register
// In the debug mode, epc/cause/status/badaddr will not update badaddr
assign cmt_epc_ena = (~dbg_mode) & (excp_taken_ena | irq_taken_ena);
assign cmt_cause_ena = cmt_epc_ena;
assign cmt_status_ena = cmt_epc_ena;
assign cmt_badaddr_ena = cmt_epc_ena & cmt_badaddr_update;
assign cmt_dpc = alu_excp_i_pc;// The ALU PC is the current next commiting PC (not yet commited)
assign cmt_dpc_ena = dbg_entry_taken_ena;
wire cmt_dcause_set = dbg_entry_taken_ena;
wire cmt_dcause_clr = cmt_dret_ena;
wire [2:0] set_dcause_nxt =
dbg_trig_req ? 3'd2 :
dbg_ebrk_req ? 3'd1 :
dbg_irq_req ? 3'd3 :
dbg_step_req ? 3'd4 :
dbg_halt_req ? 3'd5 :
3'd0;
assign cmt_dcause_ena = cmt_dcause_set | cmt_dcause_clr;
assign cmt_dcause = cmt_dcause_set ? set_dcause_nxt : 3'd0;
endmodule |
module IOBUF(
input I,
input T,
output O,
inout IO
);
assign IO = ~T ? I:1'bz;
assign O = IO;
endmodule |
module e203_subsys_gfcm(
input test_mode,
input clk0_rst_n,
input clk1_rst_n,
input sel1 ,
input clk0 ,
input clk1 ,
output clkout
);
wire clk0_sel = ~sel1;
wire clk1_sel = sel1;
localparam SYNC_LEVEL = 3;
wire clk0_sync_in;
reg [SYNC_LEVEL-1:0] clk0_sync_r;
always @(posedge clk0 or negedge clk0_rst_n)
begin:clk0_sync_PROC
if(clk0_rst_n == 1'b0)
begin
clk0_sync_r[SYNC_LEVEL-1:0] <= {SYNC_LEVEL{1'b0}};
end
else
begin
clk0_sync_r[SYNC_LEVEL-1:0] <= {clk0_sync_r[SYNC_LEVEL-2:0],clk0_sync_in};
end
end
wire clk1_sync_in;
reg [SYNC_LEVEL-1:0] clk1_sync_r;
always @(posedge clk1 or negedge clk1_rst_n)
begin:clk1_sync_PROC
if(clk1_rst_n == 1'b0)
begin
clk1_sync_r[SYNC_LEVEL-1:0] <= {SYNC_LEVEL{1'b0}};
end
else
begin
clk1_sync_r[SYNC_LEVEL-1:0] <= {clk1_sync_r[SYNC_LEVEL-2:0],clk1_sync_in};
end
end
assign clk0_sync_in = (~clk1_sync_r[SYNC_LEVEL-1]) & clk0_sel;
assign clk1_sync_in = (~clk0_sync_r[SYNC_LEVEL-1]) & clk1_sel;
wire clk0_gated;
wire clk1_gated;
wire clk0_gate_en = clk0_sync_r[1];
e203_clkgate u_clk0_clkgate(
.clk_in (clk0 ),
.test_mode(test_mode ),
.clock_en (clk0_gate_en),
.clk_out (clk0_gated)
);
wire clk1_gate_en = clk1_sync_r[1];
e203_clkgate u_clk1_clkgate(
.clk_in (clk1 ),
.test_mode(test_mode ),
.clock_en (clk1_gate_en),
.clk_out (clk1_gated)
);
assign clkout = clk0_gated | clk1_gated;
endmodule |
module e203_dtcm_ram(
input sd,
input ds,
input ls,
input cs,
input we,
input [`E203_DTCM_RAM_AW-1:0] addr,
input [`E203_DTCM_RAM_MW-1:0] wem,
input [`E203_DTCM_RAM_DW-1:0] din,
output [`E203_DTCM_RAM_DW-1:0] dout,
input rst_n,
input clk
);
wire wren = we & cs;
wire [3:0]wea;
assign wea = (wren) ? wem : 4'b0;
wire rden;
assign rden = (~we) & cs;
// bram_32 u_e203_dtcm_gnrl_ram(
//
// .doa (dout),
// .dia (din ),
// .addra (addr),
// .wea (wea ),
// .cea (cs ),
// .clka (clk ),
// .rsta (1'b0)
// );
riscv_ram32 u_e203_dtcm_gnrl_ram
(
.address(addr),
.byteena(wea),
.clock (clk),
.data (din),
.rden (rden),
.wren (wren),
.q (dout)
);
// sirv_gnrl_ram #(
// `ifndef E203_HAS_ECC//{
// .FORCE_X2ZERO(0),
// `endif//}
// .DP(`E203_DTCM_RAM_DP),
// .DW(`E203_DTCM_RAM_DW),
// .MW(`E203_DTCM_RAM_MW),
// .AW(`E203_DTCM_RAM_AW)
// ) u_e203_dtcm_gnrl_ram(
// .sd (sd ),
// .ds (ds ),
// .ls (ls ),
//
// .rst_n (rst_n ),
// .clk (clk ),
// .cs (cs ),
// .we (we ),
// .addr(addr),
// .din (din ),
// .wem (wem ),
// .dout(dout)
// );
endmodule |
module e203_subsys_clint(
input clint_icb_cmd_valid,
output clint_icb_cmd_ready,
input [`E203_ADDR_SIZE-1:0] clint_icb_cmd_addr,
input clint_icb_cmd_read,
input [`E203_XLEN-1:0] clint_icb_cmd_wdata,
input [`E203_XLEN/8-1:0] clint_icb_cmd_wmask,
//
output clint_icb_rsp_valid,
input clint_icb_rsp_ready,
output clint_icb_rsp_err,
output [`E203_XLEN-1:0] clint_icb_rsp_rdata,
output clint_tmr_irq,
output clint_sft_irq,
input aon_rtcToggle_a,
input tm_stop,
input clk,
input rst_n
);
wire aon_rtcToggle_r;
wire aon_rtcToggle;
sirv_gnrl_sync # (
.DP(`E203_ASYNC_FF_LEVELS),
.DW(1)
) u_aon_rtctoggle_sync(
.din_a (aon_rtcToggle_a),
.dout (aon_rtcToggle_r),
.clk (clk ),
.rst_n (rst_n)
);
sirv_clint_top u_sirv_clint_top(
.clk (clk ),
.rst_n (rst_n ),
.i_icb_cmd_valid (clint_icb_cmd_valid),
.i_icb_cmd_ready (clint_icb_cmd_ready),
.i_icb_cmd_addr (clint_icb_cmd_addr ),
.i_icb_cmd_read (clint_icb_cmd_read ),
.i_icb_cmd_wdata (clint_icb_cmd_wdata),
.i_icb_rsp_valid (clint_icb_rsp_valid),
.i_icb_rsp_ready (clint_icb_rsp_ready),
.i_icb_rsp_rdata (clint_icb_rsp_rdata),
.io_tiles_0_mtip (clint_tmr_irq),
.io_tiles_0_msip (clint_sft_irq),
.io_rtcToggle (aon_rtcToggle)
);
// We self-defined a mcounterstop CSR which contained a tm_stop field, this
// field can be use to disable different counters to save dynamic powers
// in the case where they dont really need the counters
assign aon_rtcToggle = aon_rtcToggle_r & (~tm_stop);
assign clint_icb_rsp_err = 1'b0;
endmodule |
module e203_subsys_pllclkdiv(
input rst_n,
input test_mode,
input divby1,
input [5:0] div,
input clk,// The PLL clock
output clkout // The divided Clock
);
wire [5:0] div_cnt_r;
wire div_cnt_sat = (div_cnt_r == div);
wire [5:0] div_cnt_nxt = div_cnt_sat ? 6'b0 : (div_cnt_r + 1'b1);
wire div_cnt_ena = (~divby1);
sirv_gnrl_dfflr #(6) div_cnt_dfflr (div_cnt_ena, div_cnt_nxt, div_cnt_r, clk, rst_n);
wire flag_r;
wire flag_nxt = ~flag_r;
wire flag_ena = div_cnt_ena & div_cnt_sat;
sirv_gnrl_dfflr #(1) flag_dfflr (flag_ena, flag_nxt, flag_r, clk, rst_n);
wire plloutdiv_en = divby1 |
((~flag_r) & div_cnt_sat);
e203_clkgate u_pllclkdiv_clkgate(
.clk_in (clk ),
.test_mode(test_mode ),
.clock_en (plloutdiv_en),
.clk_out (clkout)
);
endmodule |
module sirv_pwm8_top(
input clk,
input rst_n,
input i_icb_cmd_valid,
output i_icb_cmd_ready,
input [32-1:0] i_icb_cmd_addr,
input i_icb_cmd_read,
input [32-1:0] i_icb_cmd_wdata,
output i_icb_rsp_valid,
input i_icb_rsp_ready,
output [32-1:0] i_icb_rsp_rdata,
output io_interrupts_0_0,
output io_interrupts_0_1,
output io_interrupts_0_2,
output io_interrupts_0_3,
output io_gpio_0,
output io_gpio_1,
output io_gpio_2,
output io_gpio_3
);
wire io_in_0_a_ready;
assign i_icb_cmd_ready = io_in_0_a_ready;
wire io_in_0_a_valid = i_icb_cmd_valid;
wire [2:0] io_in_0_a_bits_opcode = i_icb_cmd_read ? 3'h4 : 3'h0;
wire [2:0] io_in_0_a_bits_param = 3'b0;
wire [2:0] io_in_0_a_bits_size = 3'd2;
wire [4:0] io_in_0_a_bits_source = 5'b0;
wire [28:0] io_in_0_a_bits_address = i_icb_cmd_addr[28:0];
wire [3:0] io_in_0_a_bits_mask = 4'b1111;
wire [31:0] io_in_0_a_bits_data = i_icb_cmd_wdata;
wire io_in_0_d_ready = i_icb_rsp_ready;
wire [2:0] io_in_0_d_bits_opcode;
wire [1:0] io_in_0_d_bits_param;
wire [2:0] io_in_0_d_bits_size;
wire [4:0] io_in_0_d_bits_source;
wire io_in_0_d_bits_sink;
wire [1:0] io_in_0_d_bits_addr_lo;
wire [31:0] io_in_0_d_bits_data;
wire io_in_0_d_bits_error;
wire io_in_0_d_valid;
assign i_icb_rsp_valid = io_in_0_d_valid;
assign i_icb_rsp_rdata = io_in_0_d_bits_data;
// Not used
wire io_in_0_b_ready = 1'b0;
wire io_in_0_b_valid;
wire [2:0] io_in_0_b_bits_opcode;
wire [1:0] io_in_0_b_bits_param;
wire [2:0] io_in_0_b_bits_size;
wire [4:0] io_in_0_b_bits_source;
wire [28:0] io_in_0_b_bits_address;
wire [3:0] io_in_0_b_bits_mask;
wire [31:0] io_in_0_b_bits_data;
// Not used
wire io_in_0_c_ready;
wire io_in_0_c_valid = 1'b0;
wire [2:0] io_in_0_c_bits_opcode = 3'b0;
wire [2:0] io_in_0_c_bits_param = 3'b0;
wire [2:0] io_in_0_c_bits_size = 3'd2;
wire [4:0] io_in_0_c_bits_source = 5'b0;
wire [28:0] io_in_0_c_bits_address = 29'b0;
wire [31:0] io_in_0_c_bits_data = 32'b0;
wire io_in_0_c_bits_error = 1'b0;
// Not used
wire io_in_0_e_ready;
wire io_in_0_e_valid = 1'b0;
wire io_in_0_e_bits_sink = 1'b0;
sirv_pwm8 u_sirv_pwm8(
.clock (clk ),
.reset (~rst_n ),
.io_interrupts_0_0 (io_interrupts_0_0 ),
.io_interrupts_0_1 (io_interrupts_0_1 ),
.io_interrupts_0_2 (io_interrupts_0_2 ),
.io_interrupts_0_3 (io_interrupts_0_3 ),
.io_gpio_0 (io_gpio_0 ),
.io_gpio_1 (io_gpio_1 ),
.io_gpio_2 (io_gpio_2 ),
.io_gpio_3 (io_gpio_3 ),
.io_in_0_a_ready (io_in_0_a_ready ),
.io_in_0_a_valid (io_in_0_a_valid ),
.io_in_0_a_bits_opcode (io_in_0_a_bits_opcode ),
.io_in_0_a_bits_param (io_in_0_a_bits_param ),
.io_in_0_a_bits_size (io_in_0_a_bits_size ),
.io_in_0_a_bits_source (io_in_0_a_bits_source ),
.io_in_0_a_bits_address (io_in_0_a_bits_address ),
.io_in_0_a_bits_mask (io_in_0_a_bits_mask ),
.io_in_0_a_bits_data (io_in_0_a_bits_data ),
.io_in_0_b_ready (io_in_0_b_ready ),
.io_in_0_b_valid (io_in_0_b_valid ),
.io_in_0_b_bits_opcode (io_in_0_b_bits_opcode ),
.io_in_0_b_bits_param (io_in_0_b_bits_param ),
.io_in_0_b_bits_size (io_in_0_b_bits_size ),
.io_in_0_b_bits_source (io_in_0_b_bits_source ),
.io_in_0_b_bits_address (io_in_0_b_bits_address ),
.io_in_0_b_bits_mask (io_in_0_b_bits_mask ),
.io_in_0_b_bits_data (io_in_0_b_bits_data ),
.io_in_0_c_ready (io_in_0_c_ready ),
.io_in_0_c_valid (io_in_0_c_valid ),
.io_in_0_c_bits_opcode (io_in_0_c_bits_opcode ),
.io_in_0_c_bits_param (io_in_0_c_bits_param ),
.io_in_0_c_bits_size (io_in_0_c_bits_size ),
.io_in_0_c_bits_source (io_in_0_c_bits_source ),
.io_in_0_c_bits_address (io_in_0_c_bits_address ),
.io_in_0_c_bits_data (io_in_0_c_bits_data ),
.io_in_0_c_bits_error (io_in_0_c_bits_error ),
.io_in_0_d_ready (io_in_0_d_ready ),
.io_in_0_d_valid (io_in_0_d_valid ),
.io_in_0_d_bits_opcode (io_in_0_d_bits_opcode ),
.io_in_0_d_bits_param (io_in_0_d_bits_param ),
.io_in_0_d_bits_size (io_in_0_d_bits_size ),
.io_in_0_d_bits_source (io_in_0_d_bits_source ),
.io_in_0_d_bits_sink (io_in_0_d_bits_sink ),
.io_in_0_d_bits_addr_lo (io_in_0_d_bits_addr_lo ),
.io_in_0_d_bits_data (io_in_0_d_bits_data ),
.io_in_0_d_bits_error (io_in_0_d_bits_error ),
.io_in_0_e_ready (io_in_0_e_ready ),
.io_in_0_e_valid (io_in_0_e_valid ),
.io_in_0_e_bits_sink (io_in_0_e_bits_sink )
);
endmodule |
module sirv_uart_top(
input clk,
input rst_n,
input i_icb_cmd_valid,
output i_icb_cmd_ready,
input [32-1:0] i_icb_cmd_addr,
input i_icb_cmd_read,
input [32-1:0] i_icb_cmd_wdata,
output i_icb_rsp_valid,
input i_icb_rsp_ready,
output [32-1:0] i_icb_rsp_rdata,
output io_interrupts_0_0,
output io_port_txd,
input io_port_rxd
);
wire io_in_0_a_ready;
assign i_icb_cmd_ready = io_in_0_a_ready;
wire io_in_0_a_valid = i_icb_cmd_valid;
wire [2:0] io_in_0_a_bits_opcode = i_icb_cmd_read ? 3'h4 : 3'h0;
wire [2:0] io_in_0_a_bits_param = 3'b0;
wire [2:0] io_in_0_a_bits_size = 3'd2;
wire [4:0] io_in_0_a_bits_source = 5'b0;
wire [28:0] io_in_0_a_bits_address = i_icb_cmd_addr[28:0];
wire [3:0] io_in_0_a_bits_mask = 4'b1111;
wire [31:0] io_in_0_a_bits_data = i_icb_cmd_wdata;
wire io_in_0_d_ready = i_icb_rsp_ready;
wire [2:0] io_in_0_d_bits_opcode;
wire [1:0] io_in_0_d_bits_param;
wire [2:0] io_in_0_d_bits_size;
wire [4:0] io_in_0_d_bits_source;
wire io_in_0_d_bits_sink;
wire [1:0] io_in_0_d_bits_addr_lo;
wire [31:0] io_in_0_d_bits_data;
wire io_in_0_d_bits_error;
wire io_in_0_d_valid;
assign i_icb_rsp_valid = io_in_0_d_valid;
assign i_icb_rsp_rdata = io_in_0_d_bits_data;
// Not used
wire io_in_0_b_ready = 1'b0;
wire io_in_0_b_valid;
wire [2:0] io_in_0_b_bits_opcode;
wire [1:0] io_in_0_b_bits_param;
wire [2:0] io_in_0_b_bits_size;
wire [4:0] io_in_0_b_bits_source;
wire [28:0] io_in_0_b_bits_address;
wire [3:0] io_in_0_b_bits_mask;
wire [31:0] io_in_0_b_bits_data;
// Not used
wire io_in_0_c_ready;
wire io_in_0_c_valid = 1'b0;
wire [2:0] io_in_0_c_bits_opcode = 3'b0;
wire [2:0] io_in_0_c_bits_param = 3'b0;
wire [2:0] io_in_0_c_bits_size = 3'd2;
wire [4:0] io_in_0_c_bits_source = 5'b0;
wire [28:0] io_in_0_c_bits_address = 29'b0;
wire [31:0] io_in_0_c_bits_data = 32'b0;
wire io_in_0_c_bits_error = 1'b0;
// Not used
wire io_in_0_e_ready;
wire io_in_0_e_valid = 1'b0;
wire io_in_0_e_bits_sink = 1'b0;
sirv_uart u_sirv_uart(
.clock (clk ),
.reset (~rst_n ),
.io_interrupts_0_0 (io_interrupts_0_0 ),
.io_in_0_a_ready (io_in_0_a_ready ),
.io_in_0_a_valid (io_in_0_a_valid ),
.io_in_0_a_bits_opcode (io_in_0_a_bits_opcode ),
.io_in_0_a_bits_param (io_in_0_a_bits_param ),
.io_in_0_a_bits_size (io_in_0_a_bits_size ),
.io_in_0_a_bits_source (io_in_0_a_bits_source ),
.io_in_0_a_bits_address (io_in_0_a_bits_address ),
.io_in_0_a_bits_mask (io_in_0_a_bits_mask ),
.io_in_0_a_bits_data (io_in_0_a_bits_data ),
.io_in_0_b_ready (io_in_0_b_ready ),
.io_in_0_b_valid (io_in_0_b_valid ),
.io_in_0_b_bits_opcode (io_in_0_b_bits_opcode ),
.io_in_0_b_bits_param (io_in_0_b_bits_param ),
.io_in_0_b_bits_size (io_in_0_b_bits_size ),
.io_in_0_b_bits_source (io_in_0_b_bits_source ),
.io_in_0_b_bits_address (io_in_0_b_bits_address ),
.io_in_0_b_bits_mask (io_in_0_b_bits_mask ),
.io_in_0_b_bits_data (io_in_0_b_bits_data ),
.io_in_0_c_ready (io_in_0_c_ready ),
.io_in_0_c_valid (io_in_0_c_valid ),
.io_in_0_c_bits_opcode (io_in_0_c_bits_opcode ),
.io_in_0_c_bits_param (io_in_0_c_bits_param ),
.io_in_0_c_bits_size (io_in_0_c_bits_size ),
.io_in_0_c_bits_source (io_in_0_c_bits_source ),
.io_in_0_c_bits_address (io_in_0_c_bits_address ),
.io_in_0_c_bits_data (io_in_0_c_bits_data ),
.io_in_0_c_bits_error (io_in_0_c_bits_error ),
.io_in_0_d_ready (io_in_0_d_ready ),
.io_in_0_d_valid (io_in_0_d_valid ),
.io_in_0_d_bits_opcode (io_in_0_d_bits_opcode ),
.io_in_0_d_bits_param (io_in_0_d_bits_param ),
.io_in_0_d_bits_size (io_in_0_d_bits_size ),
.io_in_0_d_bits_source (io_in_0_d_bits_source ),
.io_in_0_d_bits_sink (io_in_0_d_bits_sink ),
.io_in_0_d_bits_addr_lo (io_in_0_d_bits_addr_lo ),
.io_in_0_d_bits_data (io_in_0_d_bits_data ),
.io_in_0_d_bits_error (io_in_0_d_bits_error ),
.io_in_0_e_ready (io_in_0_e_ready ),
.io_in_0_e_valid (io_in_0_e_valid ),
.io_in_0_e_bits_sink (io_in_0_e_bits_sink ),
.io_port_txd (io_port_txd ),
.io_port_rxd (io_port_rxd )
);
endmodule |
module sirv_tl_repeater_5(
input clock,
input reset,
input io_repeat,
output io_full,
output io_enq_ready,
input io_enq_valid,
input [2:0] io_enq_bits_opcode,
input [2:0] io_enq_bits_param,
input [2:0] io_enq_bits_size,
input [1:0] io_enq_bits_source,
input [29:0] io_enq_bits_address,
input [3:0] io_enq_bits_mask,
input [31:0] io_enq_bits_data,
input io_deq_ready,
output io_deq_valid,
output [2:0] io_deq_bits_opcode,
output [2:0] io_deq_bits_param,
output [2:0] io_deq_bits_size,
output [1:0] io_deq_bits_source,
output [29:0] io_deq_bits_address,
output [3:0] io_deq_bits_mask,
output [31:0] io_deq_bits_data
);
reg full;
reg [31:0] GEN_9;
reg [2:0] saved_opcode;
reg [31:0] GEN_10;
reg [2:0] saved_param;
reg [31:0] GEN_11;
reg [2:0] saved_size;
reg [31:0] GEN_12;
reg [1:0] saved_source;
reg [31:0] GEN_13;
reg [29:0] saved_address;
reg [31:0] GEN_14;
reg [3:0] saved_mask;
reg [31:0] GEN_15;
reg [31:0] saved_data;
reg [31:0] GEN_16;
wire T_77;
wire T_79;
wire T_80;
wire [2:0] T_81_opcode;
wire [2:0] T_81_param;
wire [2:0] T_81_size;
wire [1:0] T_81_source;
wire [29:0] T_81_address;
wire [3:0] T_81_mask;
wire [31:0] T_81_data;
wire T_89;
wire T_90;
wire GEN_0;
wire [2:0] GEN_1;
wire [2:0] GEN_2;
wire [2:0] GEN_3;
wire [1:0] GEN_4;
wire [29:0] GEN_5;
wire [3:0] GEN_6;
wire [31:0] GEN_7;
wire T_92;
wire T_94;
wire T_95;
wire GEN_8;
assign io_full = full;
assign io_enq_ready = T_80;
assign io_deq_valid = T_77;
assign io_deq_bits_opcode = T_81_opcode;
assign io_deq_bits_param = T_81_param;
assign io_deq_bits_size = T_81_size;
assign io_deq_bits_source = T_81_source;
assign io_deq_bits_address = T_81_address;
assign io_deq_bits_mask = T_81_mask;
assign io_deq_bits_data = T_81_data;
assign T_77 = io_enq_valid | full;
assign T_79 = full == 1'h0;
assign T_80 = io_deq_ready & T_79;
assign T_81_opcode = full ? saved_opcode : io_enq_bits_opcode;
assign T_81_param = full ? saved_param : io_enq_bits_param;
assign T_81_size = full ? saved_size : io_enq_bits_size;
assign T_81_source = full ? saved_source : io_enq_bits_source;
assign T_81_address = full ? saved_address : io_enq_bits_address;
assign T_81_mask = full ? saved_mask : io_enq_bits_mask;
assign T_81_data = full ? saved_data : io_enq_bits_data;
assign T_89 = io_enq_ready & io_enq_valid;
assign T_90 = T_89 & io_repeat;
assign GEN_0 = T_90 ? 1'h1 : full;
assign GEN_1 = T_90 ? io_enq_bits_opcode : saved_opcode;
assign GEN_2 = T_90 ? io_enq_bits_param : saved_param;
assign GEN_3 = T_90 ? io_enq_bits_size : saved_size;
assign GEN_4 = T_90 ? io_enq_bits_source : saved_source;
assign GEN_5 = T_90 ? io_enq_bits_address : saved_address;
assign GEN_6 = T_90 ? io_enq_bits_mask : saved_mask;
assign GEN_7 = T_90 ? io_enq_bits_data : saved_data;
assign T_92 = io_deq_ready & io_deq_valid;
assign T_94 = io_repeat == 1'h0;
assign T_95 = T_92 & T_94;
assign GEN_8 = T_95 ? 1'h0 : GEN_0;
always @(posedge clock or posedge reset)
if (reset) begin
full <= 1'h0;
end else begin
if (T_95) begin
full <= 1'h0;
end else begin
if (T_90) begin
full <= 1'h1;
end
end
end
always @(posedge clock or posedge reset)
if (reset) begin
saved_opcode <= 3'b0;
saved_param <= 3'b0;
saved_size <= 3'b0;
saved_source <= 2'b0;
saved_address <= 30'b0;
saved_mask <= 4'b0;
saved_data <= 32'b0;
end
else begin
if (T_90) begin
saved_opcode <= io_enq_bits_opcode;
end
if (T_90) begin
saved_param <= io_enq_bits_param;
end
if (T_90) begin
saved_size <= io_enq_bits_size;
end
if (T_90) begin
saved_source <= io_enq_bits_source;
end
if (T_90) begin
saved_address <= io_enq_bits_address;
end
if (T_90) begin
saved_mask <= io_enq_bits_mask;
end
if (T_90) begin
saved_data <= io_enq_bits_data;
end
end
endmodule |
module sirv_tlfragmenter_qspi_1(
input clock,
input reset,
output io_in_0_a_ready,
input io_in_0_a_valid,
input [2:0] io_in_0_a_bits_opcode,
input [2:0] io_in_0_a_bits_param,
input [2:0] io_in_0_a_bits_size,
input [1:0] io_in_0_a_bits_source,
input [29:0] io_in_0_a_bits_address,
input io_in_0_a_bits_mask,
input [7:0] io_in_0_a_bits_data,
input io_in_0_b_ready,
output io_in_0_b_valid,
output [2:0] io_in_0_b_bits_opcode,
output [1:0] io_in_0_b_bits_param,
output [2:0] io_in_0_b_bits_size,
output [1:0] io_in_0_b_bits_source,
output [29:0] io_in_0_b_bits_address,
output io_in_0_b_bits_mask,
output [7:0] io_in_0_b_bits_data,
output io_in_0_c_ready,
input io_in_0_c_valid,
input [2:0] io_in_0_c_bits_opcode,
input [2:0] io_in_0_c_bits_param,
input [2:0] io_in_0_c_bits_size,
input [1:0] io_in_0_c_bits_source,
input [29:0] io_in_0_c_bits_address,
input [7:0] io_in_0_c_bits_data,
input io_in_0_c_bits_error,
input io_in_0_d_ready,
output io_in_0_d_valid,
output [2:0] io_in_0_d_bits_opcode,
output [1:0] io_in_0_d_bits_param,
output [2:0] io_in_0_d_bits_size,
output [1:0] io_in_0_d_bits_source,
output io_in_0_d_bits_sink,
output io_in_0_d_bits_addr_lo,
output [7:0] io_in_0_d_bits_data,
output io_in_0_d_bits_error,
output io_in_0_e_ready,
input io_in_0_e_valid,
input io_in_0_e_bits_sink,
input io_out_0_a_ready,
output io_out_0_a_valid,
output [2:0] io_out_0_a_bits_opcode,
output [2:0] io_out_0_a_bits_param,
output [2:0] io_out_0_a_bits_size,
output [6:0] io_out_0_a_bits_source,
output [29:0] io_out_0_a_bits_address,
output io_out_0_a_bits_mask,
output [7:0] io_out_0_a_bits_data,
output io_out_0_b_ready,
input io_out_0_b_valid,
input [2:0] io_out_0_b_bits_opcode,
input [1:0] io_out_0_b_bits_param,
input [2:0] io_out_0_b_bits_size,
input [6:0] io_out_0_b_bits_source,
input [29:0] io_out_0_b_bits_address,
input io_out_0_b_bits_mask,
input [7:0] io_out_0_b_bits_data,
input io_out_0_c_ready,
output io_out_0_c_valid,
output [2:0] io_out_0_c_bits_opcode,
output [2:0] io_out_0_c_bits_param,
output [2:0] io_out_0_c_bits_size,
output [6:0] io_out_0_c_bits_source,
output [29:0] io_out_0_c_bits_address,
output [7:0] io_out_0_c_bits_data,
output io_out_0_c_bits_error,
output io_out_0_d_ready,
input io_out_0_d_valid,
input [2:0] io_out_0_d_bits_opcode,
input [1:0] io_out_0_d_bits_param,
input [2:0] io_out_0_d_bits_size,
input [6:0] io_out_0_d_bits_source,
input io_out_0_d_bits_sink,
input io_out_0_d_bits_addr_lo,
input [7:0] io_out_0_d_bits_data,
input io_out_0_d_bits_error,
input io_out_0_e_ready,
output io_out_0_e_valid,
output io_out_0_e_bits_sink
);
reg [4:0] acknum;
reg [31:0] GEN_25;
reg [2:0] dOrig;
reg [31:0] GEN_26;
wire [4:0] dFragnum;
wire dFirst;
wire [7:0] T_1410;
wire T_1411;
wire dsizeOH1;
wire T_1414;
wire [4:0] GEN_5;
wire [4:0] T_1415;
wire T_1417;
wire T_1418;
wire T_1419;
wire T_1421;
wire [4:0] dFirst_acknum;
wire [5:0] GEN_8;
wire [5:0] T_1428;
wire [5:0] T_1430;
wire [5:0] T_1432;
wire [5:0] T_1433;
wire [5:0] T_1434;
wire [1:0] T_1435;
wire [3:0] T_1436;
wire T_1438;
wire [3:0] GEN_9;
wire [3:0] T_1439;
wire [1:0] T_1440;
wire [1:0] T_1441;
wire T_1443;
wire [1:0] T_1444;
wire T_1445;
wire [1:0] T_1446;
wire [2:0] dFirst_size;
wire T_1447;
wire [5:0] T_1448;
wire [4:0] T_1449;
wire [4:0] T_1450;
wire [2:0] GEN_0;
wire [4:0] GEN_1;
wire [2:0] GEN_2;
wire T_1459;
wire T_1460;
wire [1:0] T_1461;
reg r_error;
reg [31:0] GEN_27;
wire d_error;
wire GEN_3;
wire repeater_clock;
wire repeater_reset;
wire repeater_io_repeat;
wire repeater_io_full;
wire repeater_io_enq_ready;
wire repeater_io_enq_valid;
wire [2:0] repeater_io_enq_bits_opcode;
wire [2:0] repeater_io_enq_bits_param;
wire [2:0] repeater_io_enq_bits_size;
wire [1:0] repeater_io_enq_bits_source;
wire [29:0] repeater_io_enq_bits_address;
wire repeater_io_enq_bits_mask;
wire [7:0] repeater_io_enq_bits_data;
wire repeater_io_deq_ready;
wire repeater_io_deq_valid;
wire [2:0] repeater_io_deq_bits_opcode;
wire [2:0] repeater_io_deq_bits_param;
wire [2:0] repeater_io_deq_bits_size;
wire [1:0] repeater_io_deq_bits_source;
wire [29:0] repeater_io_deq_bits_address;
wire repeater_io_deq_bits_mask;
wire [7:0] repeater_io_deq_bits_data;
wire find_0;
wire T_1494;
wire [2:0] aFrag;
wire [11:0] T_1497;
wire [4:0] T_1498;
wire [4:0] aOrigOH1;
wire [7:0] T_1501;
wire T_1502;
wire aFragOH1;
reg [4:0] gennum;
reg [31:0] GEN_28;
wire aFirst;
wire [5:0] T_1511;
wire [4:0] T_1512;
wire [4:0] old_gennum1;
wire [4:0] T_1513;
wire [4:0] GEN_10;
wire [4:0] T_1515;
wire [4:0] new_gennum;
wire T_1520;
wire [4:0] GEN_4;
wire T_1524;
wire [4:0] T_1526;
wire [4:0] T_1528;
wire [29:0] GEN_12;
wire [29:0] T_1529;
wire [6:0] T_1530;
wire T_1532;
wire T_1541;
wire T_1542;
wire T_1543;
wire T_1545;
wire T_1546;
wire [2:0] GEN_6 = 3'b0;
reg [31:0] GEN_29;
wire [1:0] GEN_7 = 2'b0;
reg [31:0] GEN_30;
wire [2:0] GEN_11 = 3'b0;
reg [31:0] GEN_31;
wire [1:0] GEN_13 = 2'b0;
reg [31:0] GEN_32;
wire [29:0] GEN_14 = 30'b0;
reg [31:0] GEN_33;
wire GEN_15 = 1'b0;
reg [31:0] GEN_34;
wire [7:0] GEN_16 = 8'b0;
reg [31:0] GEN_35;
wire [2:0] GEN_17 = 3'b0;
reg [31:0] GEN_36;
wire [2:0] GEN_18 = 3'b0;
reg [31:0] GEN_37;
wire [2:0] GEN_19 = 3'b0;
reg [31:0] GEN_38;
wire [6:0] GEN_20 = 7'b0;
reg [31:0] GEN_39;
wire [29:0] GEN_21 = 30'b0;
reg [31:0] GEN_40;
wire [7:0] GEN_22 = 8'b0;
reg [31:0] GEN_41;
wire GEN_23 = 1'b0;
reg [31:0] GEN_42;
wire GEN_24 = 1'b0;
reg [31:0] GEN_43;
sirv_repeater_6 u_repeater (
.clock(repeater_clock),
.reset(repeater_reset),
.io_repeat(repeater_io_repeat),
.io_full(repeater_io_full),
.io_enq_ready(repeater_io_enq_ready),
.io_enq_valid(repeater_io_enq_valid),
.io_enq_bits_opcode(repeater_io_enq_bits_opcode),
.io_enq_bits_param(repeater_io_enq_bits_param),
.io_enq_bits_size(repeater_io_enq_bits_size),
.io_enq_bits_source(repeater_io_enq_bits_source),
.io_enq_bits_address(repeater_io_enq_bits_address),
.io_enq_bits_mask(repeater_io_enq_bits_mask),
.io_enq_bits_data(repeater_io_enq_bits_data),
.io_deq_ready(repeater_io_deq_ready),
.io_deq_valid(repeater_io_deq_valid),
.io_deq_bits_opcode(repeater_io_deq_bits_opcode),
.io_deq_bits_param(repeater_io_deq_bits_param),
.io_deq_bits_size(repeater_io_deq_bits_size),
.io_deq_bits_source(repeater_io_deq_bits_source),
.io_deq_bits_address(repeater_io_deq_bits_address),
.io_deq_bits_mask(repeater_io_deq_bits_mask),
.io_deq_bits_data(repeater_io_deq_bits_data)
);
assign io_in_0_a_ready = repeater_io_enq_ready;
assign io_in_0_b_valid = 1'h0;
assign io_in_0_b_bits_opcode = GEN_6;
assign io_in_0_b_bits_param = GEN_7;
assign io_in_0_b_bits_size = GEN_11;
assign io_in_0_b_bits_source = GEN_13;
assign io_in_0_b_bits_address = GEN_14;
assign io_in_0_b_bits_mask = GEN_15;
assign io_in_0_b_bits_data = GEN_16;
assign io_in_0_c_ready = 1'h1;
assign io_in_0_d_valid = io_out_0_d_valid;
assign io_in_0_d_bits_opcode = io_out_0_d_bits_opcode;
assign io_in_0_d_bits_param = io_out_0_d_bits_param;
assign io_in_0_d_bits_size = GEN_0;
assign io_in_0_d_bits_source = T_1461;
assign io_in_0_d_bits_sink = io_out_0_d_bits_sink;
assign io_in_0_d_bits_addr_lo = T_1460;
assign io_in_0_d_bits_data = io_out_0_d_bits_data;
assign io_in_0_d_bits_error = d_error;
assign io_in_0_e_ready = 1'h1;
assign io_out_0_a_valid = repeater_io_deq_valid;
assign io_out_0_a_bits_opcode = repeater_io_deq_bits_opcode;
assign io_out_0_a_bits_param = repeater_io_deq_bits_param;
assign io_out_0_a_bits_size = aFrag;
assign io_out_0_a_bits_source = T_1530;
assign io_out_0_a_bits_address = T_1529;
assign io_out_0_a_bits_mask = T_1546;
assign io_out_0_a_bits_data = io_in_0_a_bits_data;
assign io_out_0_b_ready = 1'h1;
assign io_out_0_c_valid = 1'h0;
assign io_out_0_c_bits_opcode = GEN_17;
assign io_out_0_c_bits_param = GEN_18;
assign io_out_0_c_bits_size = GEN_19;
assign io_out_0_c_bits_source = GEN_20;
assign io_out_0_c_bits_address = GEN_21;
assign io_out_0_c_bits_data = GEN_22;
assign io_out_0_c_bits_error = GEN_23;
assign io_out_0_d_ready = io_in_0_d_ready;
assign io_out_0_e_valid = 1'h0;
assign io_out_0_e_bits_sink = GEN_24;
assign dFragnum = io_out_0_d_bits_source[4:0];
assign dFirst = acknum == 5'h0;
assign T_1410 = 8'h1 << io_out_0_d_bits_size;
assign T_1411 = T_1410[0];
assign dsizeOH1 = ~ T_1411;
assign T_1414 = io_out_0_d_valid == 1'h0;
assign GEN_5 = {{4'd0}, dsizeOH1};
assign T_1415 = dFragnum & GEN_5;
assign T_1417 = T_1415 == 5'h0;
assign T_1418 = T_1414 | T_1417;
assign T_1419 = T_1418 | reset;
assign T_1421 = T_1419 == 1'h0;
assign dFirst_acknum = dFragnum | GEN_5;
assign GEN_8 = {{1'd0}, dFirst_acknum};
assign T_1428 = GEN_8 << 1;
assign T_1430 = T_1428 | 6'h1;
assign T_1432 = {1'h0,dFirst_acknum};
assign T_1433 = ~ T_1432;
assign T_1434 = T_1430 & T_1433;
assign T_1435 = T_1434[5:4];
assign T_1436 = T_1434[3:0];
assign T_1438 = T_1435 != 2'h0;
assign GEN_9 = {{2'd0}, T_1435};
assign T_1439 = GEN_9 | T_1436;
assign T_1440 = T_1439[3:2];
assign T_1441 = T_1439[1:0];
assign T_1443 = T_1440 != 2'h0;
assign T_1444 = T_1440 | T_1441;
assign T_1445 = T_1444[1];
assign T_1446 = {T_1443,T_1445};
assign dFirst_size = {T_1438,T_1446};
assign T_1447 = io_out_0_d_ready & io_out_0_d_valid;
assign T_1448 = acknum - 5'h1;
assign T_1449 = T_1448[4:0];
assign T_1450 = dFirst ? dFirst_acknum : T_1449;
assign GEN_0 = dFirst ? dFirst_size : dOrig;
assign GEN_1 = T_1447 ? T_1450 : acknum;
assign GEN_2 = T_1447 ? GEN_0 : dOrig;
assign T_1459 = ~ dsizeOH1;
assign T_1460 = io_out_0_d_bits_addr_lo & T_1459;
assign T_1461 = io_out_0_d_bits_source[6:5];
assign d_error = r_error | io_out_0_d_bits_error;
assign GEN_3 = T_1447 ? 1'h0 : r_error;
assign repeater_clock = clock;
assign repeater_reset = reset;
assign repeater_io_repeat = T_1524;
assign repeater_io_enq_valid = io_in_0_a_valid;
assign repeater_io_enq_bits_opcode = io_in_0_a_bits_opcode;
assign repeater_io_enq_bits_param = io_in_0_a_bits_param;
assign repeater_io_enq_bits_size = io_in_0_a_bits_size;
assign repeater_io_enq_bits_source = io_in_0_a_bits_source;
assign repeater_io_enq_bits_address = io_in_0_a_bits_address;
assign repeater_io_enq_bits_mask = io_in_0_a_bits_mask;
assign repeater_io_enq_bits_data = io_in_0_a_bits_data;
assign repeater_io_deq_ready = io_out_0_a_ready;
assign find_0 = 1'h1;
assign T_1494 = repeater_io_deq_bits_size > 3'h0;
assign aFrag = T_1494 ? 3'h0 : repeater_io_deq_bits_size;
assign T_1497 = 12'h1f << repeater_io_deq_bits_size;
assign T_1498 = T_1497[4:0];
assign aOrigOH1 = ~ T_1498;
assign T_1501 = 8'h1 << aFrag;
assign T_1502 = T_1501[0];
assign aFragOH1 = ~ T_1502;
assign aFirst = gennum == 5'h0;
assign T_1511 = gennum - 5'h1;
assign T_1512 = T_1511[4:0];
assign old_gennum1 = aFirst ? aOrigOH1 : T_1512;
assign T_1513 = ~ old_gennum1;
assign GEN_10 = {{4'd0}, aFragOH1};
assign T_1515 = T_1513 | GEN_10;
assign new_gennum = ~ T_1515;
assign T_1520 = io_out_0_a_ready & io_out_0_a_valid;
assign GEN_4 = T_1520 ? new_gennum : gennum;
assign T_1524 = new_gennum != 5'h0;
assign T_1526 = ~ new_gennum;
assign T_1528 = T_1526 & aOrigOH1;
assign GEN_12 = {{25'd0}, T_1528};
assign T_1529 = repeater_io_deq_bits_address | GEN_12;
assign T_1530 = {repeater_io_deq_bits_source,new_gennum};
assign T_1532 = repeater_io_full == 1'h0;
assign T_1541 = repeater_io_deq_bits_mask;
assign T_1542 = T_1532 | T_1541;
assign T_1543 = T_1542 | reset;
assign T_1545 = T_1543 == 1'h0;
assign T_1546 = repeater_io_full ? 1'h1 : io_in_0_a_bits_mask;
always @(posedge clock or posedge reset)
if (reset) begin
acknum <= 5'h0;
end else begin
if (T_1447) begin
if (dFirst) begin
acknum <= dFirst_acknum;
end else begin
acknum <= T_1449;
end
end
end
always @(posedge clock or posedge reset)
if (reset) begin
dOrig <= 3'b0;
end
else begin
if (T_1447) begin
if (dFirst) begin
dOrig <= dFirst_size;
end
end
end
always @(posedge clock or posedge reset)
if (reset) begin
r_error <= 1'h0;
end else begin
if (T_1447) begin
r_error <= 1'h0;
end
end
always @(posedge clock or posedge reset)
if (reset) begin
gennum <= 5'h0;
end else begin
if (T_1520) begin
gennum <= new_gennum;
end
end
// `ifndef SYNTHESIS
// `ifdef PRINTF_COND
// if (`PRINTF_COND) begin
// `endif
// if (T_1421) begin
// $fwrite(32'h80000002,"Assertion failed\n at Fragmenter.scala:149 assert (!out.d.valid || (acknum_fragment & acknum_size) === UInt(0))\n");
// end
// `ifdef PRINTF_COND
// end
// `endif
// `endif
// `ifndef SYNTHESIS
// `ifdef STOP_COND
// if (`STOP_COND) begin
// `endif
// if (T_1421) begin
// $fatal;
// end
// `ifdef STOP_COND
// end
// `endif
// `endif
// `ifndef SYNTHESIS
// `ifdef PRINTF_COND
// if (`PRINTF_COND) begin
// `endif
// if (1'h0) begin
// $fwrite(32'h80000002,"Assertion failed\n at Fragmenter.scala:237 assert (!repeater.io.full || !aHasData)\n");
// end
// `ifdef PRINTF_COND
// end
// `endif
// `endif
// `ifndef SYNTHESIS
// `ifdef STOP_COND
// if (`STOP_COND) begin
// `endif
// if (1'h0) begin
// $fatal;
// end
// `ifdef STOP_COND
// end
// `endif
// `endif
// `ifndef SYNTHESIS
// `ifdef PRINTF_COND
// if (`PRINTF_COND) begin
// `endif
// if (T_1545) begin
// $fwrite(32'h80000002,"Assertion failed\n at Fragmenter.scala:240 assert (!repeater.io.full || in_a.bits.mask === fullMask)\n");
// end
// `ifdef PRINTF_COND
// end
// `endif
// `endif
// `ifndef SYNTHESIS
// `ifdef STOP_COND
// if (`STOP_COND) begin
// `endif
// if (T_1545) begin
// $fatal;
// end
// `ifdef STOP_COND
// end
// `endif
// `endif
//synopsys translate_off
always @(posedge clock or posedge reset) begin
if (T_1421) begin
$fwrite(32'h80000002,"Assertion failed\n at Fragmenter.scala:149 assert (!out.d.valid || (acknum_fragment & acknum_size) === UInt(0))\n");
end
if (T_1545) begin
$fwrite(32'h80000002,"Assertion failed\n at Fragmenter.scala:240 assert (!repeater.io.full || in_a.bits.mask === fullMask)\n");
end
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed\n at Fragmenter.scala:237 assert (!repeater.io.full || !aHasData)\n");
end
end
//synopsys translate_on
endmodule |
module e203_subsys_hclkgen_rstsync (
input clk, // clock
input rst_n_a, // async reset
input test_mode, // test mode
output rst_n
);
localparam RST_SYNC_LEVEL = `E203_ASYNC_FF_LEVELS;
reg [RST_SYNC_LEVEL-1:0] rst_sync_r;
always @(posedge clk or negedge rst_n_a)
begin:rst_sync_PROC
if(rst_n_a == 1'b0)
begin
rst_sync_r[RST_SYNC_LEVEL-1:0] <= {RST_SYNC_LEVEL{1'b0}};
end
else
begin
rst_sync_r[RST_SYNC_LEVEL-1:0] <= {rst_sync_r[RST_SYNC_LEVEL-2:0],1'b1};
end
end
assign rst_n = test_mode ? rst_n_a : rst_sync_r[`E203_ASYNC_FF_LEVELS-1];
endmodule |
module e203_ifu_litebpu(
// Current PC
input [`E203_PC_SIZE-1:0] pc,
// The mini-decoded info
input dec_jal,
input dec_jalr,
input dec_bxx,
input [`E203_XLEN-1:0] dec_bjp_imm,
input [`E203_RFIDX_WIDTH-1:0] dec_jalr_rs1idx,
// The IR index and OITF status to be used for checking dependency
input oitf_empty,
input ir_empty,
input ir_rs1en,
input jalr_rs1idx_cam_irrdidx,
// The add op to next-pc adder
output bpu_wait,
output prdt_taken,
output [`E203_PC_SIZE-1:0] prdt_pc_add_op1,
output [`E203_PC_SIZE-1:0] prdt_pc_add_op2,
input dec_i_valid,
// The RS1 to read regfile
output bpu2rf_rs1_ena,
input ir_valid_clr,
input [`E203_XLEN-1:0] rf2bpu_x1,
input [`E203_XLEN-1:0] rf2bpu_rs1,
input clk,
input rst_n
);
// BPU of E201 utilize very simple static branch prediction logics
// * JAL: The target address of JAL is calculated based on current PC value
// and offset, and JAL is unconditionally always jump
// * JALR with rs1 == x0: The target address of JALR is calculated based on
// x0+offset, and JALR is unconditionally always jump
// * JALR with rs1 = x1: The x1 register value is directly wired from regfile
// when the x1 have no dependency with ongoing instructions by checking
// two conditions:
// ** (1) The OTIF in EXU must be empty
// ** (2) The instruction in IR have no x1 as destination register
// * If there is dependency, then hold up IFU until the dependency is cleared
// * JALR with rs1 != x0 or x1: The target address of JALR need to be resolved
// at EXU stage, hence have to be forced halted, wait the EXU to be
// empty and then read the regfile to grab the value of xN.
// This will exert 1 cycle performance lost for JALR instruction
// * Bxxx: Conditional branch is always predicted as taken if it is backward
// jump, and not-taken if it is forward jump. The target address of JAL
// is calculated based on current PC value and offset
// The JAL and JALR is always jump, bxxx backward is predicted as taken
assign prdt_taken = (dec_jal | dec_jalr | (dec_bxx & dec_bjp_imm[`E203_XLEN-1]));
// The JALR with rs1 == x1 have dependency or xN have dependency
wire dec_jalr_rs1x0 = (dec_jalr_rs1idx == `E203_RFIDX_WIDTH'd0);
wire dec_jalr_rs1x1 = (dec_jalr_rs1idx == `E203_RFIDX_WIDTH'd1);
wire dec_jalr_rs1xn = (~dec_jalr_rs1x0) & (~dec_jalr_rs1x1);
wire jalr_rs1x1_dep = dec_i_valid & dec_jalr & dec_jalr_rs1x1 & ((~oitf_empty) | (jalr_rs1idx_cam_irrdidx));
wire jalr_rs1xn_dep = dec_i_valid & dec_jalr & dec_jalr_rs1xn & ((~oitf_empty) | (~ir_empty));
// If only depend to IR stage (OITF is empty), then if IR is under clearing, or
// it does not use RS1 index, then we can also treat it as non-dependency
wire jalr_rs1xn_dep_ir_clr = (jalr_rs1xn_dep & oitf_empty & (~ir_empty)) & (ir_valid_clr | (~ir_rs1en));
wire rs1xn_rdrf_r;
wire rs1xn_rdrf_set = (~rs1xn_rdrf_r) & dec_i_valid & dec_jalr & dec_jalr_rs1xn & ((~jalr_rs1xn_dep) | jalr_rs1xn_dep_ir_clr);
wire rs1xn_rdrf_clr = rs1xn_rdrf_r;
wire rs1xn_rdrf_ena = rs1xn_rdrf_set | rs1xn_rdrf_clr;
wire rs1xn_rdrf_nxt = rs1xn_rdrf_set | (~rs1xn_rdrf_clr);
sirv_gnrl_dfflr #(1) rs1xn_rdrf_dfflrs(rs1xn_rdrf_ena, rs1xn_rdrf_nxt, rs1xn_rdrf_r, clk, rst_n);
assign bpu2rf_rs1_ena = rs1xn_rdrf_set;
assign bpu_wait = jalr_rs1x1_dep | jalr_rs1xn_dep | rs1xn_rdrf_set;
assign prdt_pc_add_op1 = (dec_bxx | dec_jal) ? pc[`E203_PC_SIZE-1:0]
: (dec_jalr & dec_jalr_rs1x0) ? `E203_PC_SIZE'b0
: (dec_jalr & dec_jalr_rs1x1) ? rf2bpu_x1[`E203_PC_SIZE-1:0]
: rf2bpu_rs1[`E203_PC_SIZE-1:0];
assign prdt_pc_add_op2 = dec_bjp_imm[`E203_PC_SIZE-1:0];
endmodule |
module sirv_plic_top(
input clk,
input rst_n,
input i_icb_cmd_valid,
output i_icb_cmd_ready,
input [32-1:0] i_icb_cmd_addr,
input i_icb_cmd_read,
input [32-1:0] i_icb_cmd_wdata,
output i_icb_rsp_valid,
input i_icb_rsp_ready,
output [32-1:0] i_icb_rsp_rdata,
input io_devices_0_0,
input io_devices_0_1,
input io_devices_0_2,
input io_devices_0_3,
input io_devices_0_4,
input io_devices_0_5,
input io_devices_0_6,
input io_devices_0_7,
input io_devices_0_8,
input io_devices_0_9,
input io_devices_0_10,
input io_devices_0_11,
input io_devices_0_12,
input io_devices_0_13,
input io_devices_0_14,
input io_devices_0_15,
input io_devices_0_16,
input io_devices_0_17,
input io_devices_0_18,
input io_devices_0_19,
input io_devices_0_20,
input io_devices_0_21,
input io_devices_0_22,
input io_devices_0_23,
input io_devices_0_24,
input io_devices_0_25,
input io_devices_0_26,
input io_devices_0_27,
input io_devices_0_28,
input io_devices_0_29,
input io_devices_0_30,
input io_devices_0_31,
input io_devices_0_32,
input io_devices_0_33,
input io_devices_0_34,
input io_devices_0_35,
input io_devices_0_36,
input io_devices_0_37,
input io_devices_0_38,
input io_devices_0_39,
input io_devices_0_40,
input io_devices_0_41,
input io_devices_0_42,
input io_devices_0_43,
input io_devices_0_44,
input io_devices_0_45,
input io_devices_0_46,
input io_devices_0_47,
input io_devices_0_48,
input io_devices_0_49,
input io_devices_0_50,
input io_devices_0_51,
output io_harts_0_0
);
wire plic_irq;
assign io_harts_0_0 = plic_irq;
localparam PLIC_IRQ_NUM = 53;// The number can be enlarged as long as not larger than 1024
wire [PLIC_IRQ_NUM-1:0] plic_irq_i = {
io_devices_0_51 ,
io_devices_0_50 ,
io_devices_0_49 ,
io_devices_0_48 ,
io_devices_0_47 ,
io_devices_0_46 ,
io_devices_0_45 ,
io_devices_0_44 ,
io_devices_0_43 ,
io_devices_0_42 ,
io_devices_0_41 ,
io_devices_0_40 ,
io_devices_0_39 ,
io_devices_0_38 ,
io_devices_0_37 ,
io_devices_0_36 ,
io_devices_0_35 ,
io_devices_0_34 ,
io_devices_0_33 ,
io_devices_0_32 ,
io_devices_0_31 ,
io_devices_0_30 ,
io_devices_0_29 ,
io_devices_0_28 ,
io_devices_0_27 ,
io_devices_0_26 ,
io_devices_0_25 ,
io_devices_0_24 ,
io_devices_0_23 ,
io_devices_0_22 ,
io_devices_0_21 ,
io_devices_0_20 ,
io_devices_0_19 ,
io_devices_0_18 ,
io_devices_0_17 ,
io_devices_0_16 ,
io_devices_0_15 ,
io_devices_0_14 ,
io_devices_0_13 ,
io_devices_0_12 ,
io_devices_0_11 ,
io_devices_0_10 ,
io_devices_0_9 ,
io_devices_0_8 ,
io_devices_0_7 ,
io_devices_0_6 ,
io_devices_0_5 ,
io_devices_0_4 ,
io_devices_0_3 ,
io_devices_0_2 ,
io_devices_0_1 ,
io_devices_0_0 ,
1'b0 };// The IRQ0 must be tied to zero
sirv_plic_man #(
.PLIC_PRIO_WIDTH (3),
.PLIC_IRQ_NUM (PLIC_IRQ_NUM),
.PLIC_IRQ_NUM_LOG2 (6),
.PLIC_ICB_RSP_FLOP (1),
.PLIC_IRQ_I_FLOP (1),
.PLIC_IRQ_O_FLOP (1)
) u_sirv_plic_man(
.clk (clk ),
.rst_n (rst_n ),
.icb_cmd_valid (i_icb_cmd_valid),
.icb_cmd_addr (i_icb_cmd_addr[24-1:0] ),
.icb_cmd_read (i_icb_cmd_read ),
.icb_cmd_wdata (i_icb_cmd_wdata),
.icb_rsp_ready (i_icb_rsp_ready),
.icb_rsp_valid (i_icb_rsp_valid),
.icb_cmd_ready (i_icb_cmd_ready),
.icb_rsp_rdata (i_icb_rsp_rdata),
.plic_irq_i (plic_irq_i),
.plic_irq_o (plic_irq )
);
endmodule |
module sirv_gnrl_dfflrs # (
parameter DW = 32
) (
input lden,
input [DW-1:0] dnxt,
output [DW-1:0] qout,
input clk,
input rst_n
);
reg [DW-1:0] qout_r;
always @(posedge clk or negedge rst_n)
begin : DFFLRS_PROC
if (rst_n == 1'b0)
qout_r <= {DW{1'b1}};
else if (lden == 1'b1)
qout_r <= #1 dnxt;
end
assign qout = qout_r;
endmodule |
module sirv_gnrl_dfflr # (
parameter DW = 32
) (
input lden,
input [DW-1:0] dnxt,
output [DW-1:0] qout,
input clk,
input rst_n
);
reg [DW-1:0] qout_r;
always @(posedge clk or negedge rst_n)
begin : DFFLR_PROC
if (rst_n == 1'b0)
qout_r <= {DW{1'b0}};
else if (lden == 1'b1)
qout_r <= #1 dnxt;
end
assign qout = qout_r;
endmodule |
module sirv_gnrl_dffl # (
parameter DW = 32
) (
input lden,
input [DW-1:0] dnxt,
output [DW-1:0] qout,
input clk
);
reg [DW-1:0] qout_r;
always @(posedge clk)
begin : DFFL_PROC
if (lden == 1'b1)
qout_r <= #1 dnxt;
end
assign qout = qout_r;
endmodule |
module sirv_gnrl_dffrs # (
parameter DW = 32
) (
input [DW-1:0] dnxt,
output [DW-1:0] qout,
input clk,
input rst_n
);
reg [DW-1:0] qout_r;
always @(posedge clk or negedge rst_n)
begin : DFFRS_PROC
if (rst_n == 1'b0)
qout_r <= {DW{1'b1}};
else
qout_r <= #1 dnxt;
end
assign qout = qout_r;
endmodule |
module sirv_gnrl_dffr # (
parameter DW = 32
) (
input [DW-1:0] dnxt,
output [DW-1:0] qout,
input clk,
input rst_n
);
reg [DW-1:0] qout_r;
always @(posedge clk or negedge rst_n)
begin : DFFR_PROC
if (rst_n == 1'b0)
qout_r <= {DW{1'b0}};
else
qout_r <= #1 dnxt;
end
assign qout = qout_r;
endmodule |
module sirv_gnrl_ltch # (
parameter DW = 32
) (
//input test_mode,
input lden,
input [DW-1:0] dnxt,
output [DW-1:0] qout
);
reg [DW-1:0] qout_r;
always @ *
begin : LTCH_PROC
if (lden == 1'b1)
qout_r <= dnxt;
end
//assign qout = test_mode ? dnxt : qout_r;
assign qout = qout_r;
endmodule |
module sirv_icb1to2_bus # (
parameter ICB_FIFO_DP = 0, // This is to optionally add the pipeline stage for ICB bus
// if the depth is 0, then means pass through, not add pipeline
// if the depth is 2, then means added one ping-pong buffer stage
parameter ICB_FIFO_CUT_READY = 1, // This is to cut the back-pressure signal if you set as 1
parameter AW = 32,
parameter DW = 32,
parameter SPLT_FIFO_OUTS_NUM = 1,
parameter SPLT_FIFO_CUT_READY = 1,
parameter O0_BASE_ADDR = 32'h0000_1000,
parameter O0_BASE_REGION_LSB = 12
)(
input i_icb_cmd_valid,
output i_icb_cmd_ready,
input [ AW-1:0] i_icb_cmd_addr,
input i_icb_cmd_read,
input [2-1:0] i_icb_cmd_burst,
input [2-1:0] i_icb_cmd_beat,
input [ DW-1:0] i_icb_cmd_wdata,
input [ DW/8-1:0] i_icb_cmd_wmask,
input i_icb_cmd_lock,
input i_icb_cmd_excl,
input [1:0] i_icb_cmd_size,
output i_icb_rsp_valid,
input i_icb_rsp_ready,
output i_icb_rsp_err ,
output i_icb_rsp_excl_ok,
output [ DW-1:0] i_icb_rsp_rdata,
output o0_icb_cmd_valid,
input o0_icb_cmd_ready,
output [ AW-1:0] o0_icb_cmd_addr,
output o0_icb_cmd_read,
output [2-1:0] o0_icb_cmd_burst,
output [2-1:0] o0_icb_cmd_beat,
output [ DW-1:0] o0_icb_cmd_wdata,
output [ DW/8-1:0] o0_icb_cmd_wmask,
output o0_icb_cmd_lock,
output o0_icb_cmd_excl,
output [1:0] o0_icb_cmd_size,
input o0_icb_rsp_valid,
output o0_icb_rsp_ready,
input o0_icb_rsp_err ,
input o0_icb_rsp_excl_ok,
input [ DW-1:0] o0_icb_rsp_rdata,
output o1_icb_cmd_valid,
input o1_icb_cmd_ready,
output [ AW-1:0] o1_icb_cmd_addr,
output o1_icb_cmd_read,
output [2-1:0] o1_icb_cmd_burst,
output [2-1:0] o1_icb_cmd_beat,
output [ DW-1:0] o1_icb_cmd_wdata,
output [ DW/8-1:0] o1_icb_cmd_wmask,
output o1_icb_cmd_lock,
output o1_icb_cmd_excl,
output [1:0] o1_icb_cmd_size,
input o1_icb_rsp_valid,
output o1_icb_rsp_ready,
input o1_icb_rsp_err ,
input o1_icb_rsp_excl_ok,
input [ DW-1:0] o1_icb_rsp_rdata,
input clk,
input rst_n
);
wire buf_icb_cmd_valid;
wire buf_icb_cmd_ready;
wire [ AW-1:0] buf_icb_cmd_addr;
wire buf_icb_cmd_read;
wire [2-1:0] buf_icb_cmd_burst;
wire [2-1:0] buf_icb_cmd_beat;
wire [ DW-1:0] buf_icb_cmd_wdata;
wire [ DW/8-1:0] buf_icb_cmd_wmask;
wire buf_icb_cmd_lock;
wire buf_icb_cmd_excl;
wire [1:0] buf_icb_cmd_size;
wire buf_icb_rsp_valid;
wire buf_icb_rsp_ready;
wire buf_icb_rsp_err ;
wire buf_icb_rsp_excl_ok;
wire [ DW-1:0] buf_icb_rsp_rdata;
sirv_gnrl_icb_buffer # (
.OUTS_CNT_W (SPLT_FIFO_OUTS_NUM),
.AW (AW),
.DW (DW),
.CMD_DP(ICB_FIFO_DP),
.RSP_DP(ICB_FIFO_DP),
.CMD_CUT_READY (ICB_FIFO_CUT_READY),
.RSP_CUT_READY (ICB_FIFO_CUT_READY),
.USR_W (1)
)u_sirv_gnrl_icb_buffer(
.icb_buffer_active (),
.i_icb_cmd_valid (i_icb_cmd_valid),
.i_icb_cmd_ready (i_icb_cmd_ready),
.i_icb_cmd_read (i_icb_cmd_read ),
.i_icb_cmd_addr (i_icb_cmd_addr ),
.i_icb_cmd_wdata (i_icb_cmd_wdata),
.i_icb_cmd_wmask (i_icb_cmd_wmask),
.i_icb_cmd_lock (i_icb_cmd_lock ),
.i_icb_cmd_excl (i_icb_cmd_excl ),
.i_icb_cmd_size (i_icb_cmd_size ),
.i_icb_cmd_burst (i_icb_cmd_burst),
.i_icb_cmd_beat (i_icb_cmd_beat ),
.i_icb_cmd_usr (1'b0 ),
.i_icb_rsp_valid (i_icb_rsp_valid),
.i_icb_rsp_ready (i_icb_rsp_ready),
.i_icb_rsp_err (i_icb_rsp_err ),
.i_icb_rsp_excl_ok (i_icb_rsp_excl_ok),
.i_icb_rsp_rdata (i_icb_rsp_rdata),
.i_icb_rsp_usr (),
.o_icb_cmd_valid (buf_icb_cmd_valid),
.o_icb_cmd_ready (buf_icb_cmd_ready),
.o_icb_cmd_read (buf_icb_cmd_read ),
.o_icb_cmd_addr (buf_icb_cmd_addr ),
.o_icb_cmd_wdata (buf_icb_cmd_wdata),
.o_icb_cmd_wmask (buf_icb_cmd_wmask),
.o_icb_cmd_lock (buf_icb_cmd_lock ),
.o_icb_cmd_excl (buf_icb_cmd_excl ),
.o_icb_cmd_size (buf_icb_cmd_size ),
.o_icb_cmd_burst (buf_icb_cmd_burst),
.o_icb_cmd_beat (buf_icb_cmd_beat ),
.o_icb_cmd_usr (),
.o_icb_rsp_valid (buf_icb_rsp_valid),
.o_icb_rsp_ready (buf_icb_rsp_ready),
.o_icb_rsp_err (buf_icb_rsp_err ),
.o_icb_rsp_excl_ok (buf_icb_rsp_excl_ok),
.o_icb_rsp_rdata (buf_icb_rsp_rdata),
.o_icb_rsp_usr (1'b0 ),
.clk (clk ),
.rst_n (rst_n)
);
localparam BASE_REGION_MSB = (AW-1);
localparam SPLT_I_NUM = 2;
wire [SPLT_I_NUM*1-1:0] splt_bus_icb_cmd_valid;
wire [SPLT_I_NUM*1-1:0] splt_bus_icb_cmd_ready;
wire [SPLT_I_NUM* AW-1:0] splt_bus_icb_cmd_addr;
wire [SPLT_I_NUM*1-1:0] splt_bus_icb_cmd_read;
wire [SPLT_I_NUM*2-1:0] splt_bus_icb_cmd_burst;
wire [SPLT_I_NUM*2-1:0] splt_bus_icb_cmd_beat;
wire [SPLT_I_NUM* DW-1:0] splt_bus_icb_cmd_wdata;
wire [SPLT_I_NUM* DW/8-1:0] splt_bus_icb_cmd_wmask;
wire [SPLT_I_NUM*1-1:0] splt_bus_icb_cmd_lock;
wire [SPLT_I_NUM*1-1:0] splt_bus_icb_cmd_excl;
wire [SPLT_I_NUM*2-1:0] splt_bus_icb_cmd_size;
wire [SPLT_I_NUM*1-1:0] splt_bus_icb_rsp_valid;
wire [SPLT_I_NUM*1-1:0] splt_bus_icb_rsp_ready;
wire [SPLT_I_NUM*1-1:0] splt_bus_icb_rsp_err;
wire [SPLT_I_NUM*1-1:0] splt_bus_icb_rsp_excl_ok;
wire [SPLT_I_NUM* DW-1:0] splt_bus_icb_rsp_rdata;
//CMD Channel
assign {
o0_icb_cmd_valid
, o1_icb_cmd_valid
} = splt_bus_icb_cmd_valid;
assign {
o0_icb_cmd_addr
, o1_icb_cmd_addr
} = splt_bus_icb_cmd_addr;
assign {
o0_icb_cmd_read
, o1_icb_cmd_read
} = splt_bus_icb_cmd_read;
assign {
o0_icb_cmd_burst
, o1_icb_cmd_burst
} = splt_bus_icb_cmd_burst;
assign {
o0_icb_cmd_beat
, o1_icb_cmd_beat
} = splt_bus_icb_cmd_beat;
assign {
o0_icb_cmd_wdata
, o1_icb_cmd_wdata
} = splt_bus_icb_cmd_wdata;
assign {
o0_icb_cmd_wmask
, o1_icb_cmd_wmask
} = splt_bus_icb_cmd_wmask;
assign {
o0_icb_cmd_lock
, o1_icb_cmd_lock
} = splt_bus_icb_cmd_lock;
assign {
o0_icb_cmd_excl
, o1_icb_cmd_excl
} = splt_bus_icb_cmd_excl;
assign {
o0_icb_cmd_size
, o1_icb_cmd_size
} = splt_bus_icb_cmd_size;
assign splt_bus_icb_cmd_ready = {
o0_icb_cmd_ready
, o1_icb_cmd_ready
};
//RSP Channel
assign splt_bus_icb_rsp_valid = {
o0_icb_rsp_valid
, o1_icb_rsp_valid
};
assign splt_bus_icb_rsp_err = {
o0_icb_rsp_err
, o1_icb_rsp_err
};
assign splt_bus_icb_rsp_excl_ok = {
o0_icb_rsp_excl_ok
, o1_icb_rsp_excl_ok
};
assign splt_bus_icb_rsp_rdata = {
o0_icb_rsp_rdata
, o1_icb_rsp_rdata
};
assign {
o0_icb_rsp_ready
, o1_icb_rsp_ready
} = splt_bus_icb_rsp_ready;
wire icb_cmd_o0 = buf_icb_cmd_valid & (buf_icb_cmd_addr [BASE_REGION_MSB:O0_BASE_REGION_LSB]
== O0_BASE_ADDR [BASE_REGION_MSB:O0_BASE_REGION_LSB]
);
wire icb_cmd_o1 = ~icb_cmd_o0;
wire [SPLT_I_NUM-1:0] buf_icb_splt_indic =
{
icb_cmd_o0
, icb_cmd_o1
};
sirv_gnrl_icb_splt # (
.ALLOW_DIFF (0),// Dont allow different branches oustanding
.ALLOW_0CYCL_RSP (1),// Allow the 0 cycle response because in BIU the splt
// is after the buffer, and will directly talk to the external
// bus, where maybe the ROM is 0 cycle responsed.
.FIFO_OUTS_NUM (SPLT_FIFO_OUTS_NUM ),
.FIFO_CUT_READY (SPLT_FIFO_CUT_READY),
.SPLT_NUM (SPLT_I_NUM),
.SPLT_PTR_W (SPLT_I_NUM),
.SPLT_PTR_1HOT (1),
.VLD_MSK_PAYLOAD(1),
.USR_W (1),
.AW (AW),
.DW (DW)
) u_i_icb_splt(
.i_icb_splt_indic (buf_icb_splt_indic),
.i_icb_cmd_valid (buf_icb_cmd_valid ) ,
.i_icb_cmd_ready (buf_icb_cmd_ready ) ,
.i_icb_cmd_read (buf_icb_cmd_read ) ,
.i_icb_cmd_addr (buf_icb_cmd_addr ) ,
.i_icb_cmd_wdata (buf_icb_cmd_wdata ) ,
.i_icb_cmd_wmask (buf_icb_cmd_wmask) ,
.i_icb_cmd_burst (buf_icb_cmd_burst) ,
.i_icb_cmd_beat (buf_icb_cmd_beat ) ,
.i_icb_cmd_excl (buf_icb_cmd_excl ) ,
.i_icb_cmd_lock (buf_icb_cmd_lock ) ,
.i_icb_cmd_size (buf_icb_cmd_size ) ,
.i_icb_cmd_usr (1'b0) ,
.i_icb_rsp_valid (buf_icb_rsp_valid ) ,
.i_icb_rsp_ready (buf_icb_rsp_ready ) ,
.i_icb_rsp_err (buf_icb_rsp_err) ,
.i_icb_rsp_excl_ok (buf_icb_rsp_excl_ok) ,
.i_icb_rsp_rdata (buf_icb_rsp_rdata ) ,
.i_icb_rsp_usr ( ) ,
.o_bus_icb_cmd_ready (splt_bus_icb_cmd_ready ) ,
.o_bus_icb_cmd_valid (splt_bus_icb_cmd_valid ) ,
.o_bus_icb_cmd_read (splt_bus_icb_cmd_read ) ,
.o_bus_icb_cmd_addr (splt_bus_icb_cmd_addr ) ,
.o_bus_icb_cmd_wdata (splt_bus_icb_cmd_wdata ) ,
.o_bus_icb_cmd_wmask (splt_bus_icb_cmd_wmask) ,
.o_bus_icb_cmd_burst (splt_bus_icb_cmd_burst),
.o_bus_icb_cmd_beat (splt_bus_icb_cmd_beat ),
.o_bus_icb_cmd_excl (splt_bus_icb_cmd_excl ),
.o_bus_icb_cmd_lock (splt_bus_icb_cmd_lock ),
.o_bus_icb_cmd_size (splt_bus_icb_cmd_size ),
.o_bus_icb_cmd_usr () ,
.o_bus_icb_rsp_valid (splt_bus_icb_rsp_valid ) ,
.o_bus_icb_rsp_ready (splt_bus_icb_rsp_ready ) ,
.o_bus_icb_rsp_err (splt_bus_icb_rsp_err) ,
.o_bus_icb_rsp_excl_ok (splt_bus_icb_rsp_excl_ok),
.o_bus_icb_rsp_rdata (splt_bus_icb_rsp_rdata ) ,
.o_bus_icb_rsp_usr ({SPLT_I_NUM{1'b0}}) ,
.clk (clk ) ,
.rst_n (rst_n)
);
endmodule |
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