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module axi4_retime_fifo
//-----------------------------------------------------------------
// Params
//-----------------------------------------------------------------
#(
parameter WIDTH = 8,
parameter DEPTH = 2,
parameter ADDR_W = 1
)
//-----------------------------------------------------------------
// Ports
//-----------------------------------------------------------------
(
// Inputs
input clk_i
,input rst_i
,input [WIDTH-1:0] data_in_i
,input push_i
,input pop_i
// Outputs
,output [WIDTH-1:0] data_out_o
,output accept_o
,output valid_o
);
//-----------------------------------------------------------------
// Local Params
//-----------------------------------------------------------------
localparam COUNT_W = ADDR_W + 1;
//-----------------------------------------------------------------
// Registers
//-----------------------------------------------------------------
reg [WIDTH-1:0] ram_q[DEPTH-1:0];
reg [ADDR_W-1:0] rd_ptr_q;
reg [ADDR_W-1:0] wr_ptr_q;
reg [COUNT_W-1:0] count_q;
//-----------------------------------------------------------------
// Sequential
//-----------------------------------------------------------------
always @ (posedge clk_i )
if (rst_i)
begin
count_q <= {(COUNT_W) {1'b0}};
rd_ptr_q <= {(ADDR_W) {1'b0}};
wr_ptr_q <= {(ADDR_W) {1'b0}};
end
else
begin
// Push
if (push_i & accept_o)
begin
ram_q[wr_ptr_q] <= data_in_i;
wr_ptr_q <= wr_ptr_q + 1;
end
// Pop
if (pop_i & valid_o)
rd_ptr_q <= rd_ptr_q + 1;
// Count up
if ((push_i & accept_o) & ~(pop_i & valid_o))
count_q <= count_q + 1;
// Count down
else if (~(push_i & accept_o) & (pop_i & valid_o))
count_q <= count_q - 1;
end
//-------------------------------------------------------------------
// Combinatorial
//-------------------------------------------------------------------
/* verilator lint_off WIDTH */
assign valid_o = (count_q != 0);
assign accept_o = (count_q != DEPTH);
/* verilator lint_on WIDTH */
assign data_out_o = ram_q[rd_ptr_q];
endmodule |
module axi4_cdc_fifo6
(
// Inputs
input rd_clk_i
,input rd_rst_i
,input rd_pop_i
,input wr_clk_i
,input wr_rst_i
,input [ 5:0] wr_data_i
,input wr_push_i
// Outputs
,output [ 5:0] rd_data_o
,output rd_empty_o
,output wr_full_o
);
//-----------------------------------------------------------------
// Registers
//-----------------------------------------------------------------
reg [4:0] rd_ptr_q;
reg [4:0] wr_ptr_q;
//-----------------------------------------------------------------
// Write
//-----------------------------------------------------------------
wire [4:0] wr_ptr_next_w = wr_ptr_q + 5'd1;
always @ (posedge wr_clk_i or posedge wr_rst_i)
if (wr_rst_i)
wr_ptr_q <= 5'b0;
else if (wr_push_i & ~wr_full_o)
wr_ptr_q <= wr_ptr_next_w;
wire [4:0] wr_rd_ptr_w;
axi4_cdc_fifo6_resync_bus
#( .WIDTH(5))
u_resync_rd_ptr_q
(
.wr_clk_i(rd_clk_i),
.wr_rst_i(rd_rst_i),
.wr_i(1'b1),
.wr_data_i(rd_ptr_q),
.wr_busy_o(),
.rd_clk_i(wr_clk_i),
.rd_rst_i(wr_rst_i),
.rd_data_o(wr_rd_ptr_w) // Delayed version of rd_ptr_q
);
assign wr_full_o = (wr_ptr_next_w == wr_rd_ptr_w);
//-------------------------------------------------------------------
// Dual port RAM
//-------------------------------------------------------------------
wire [5:0] rd_data_w;
axi4_cdc_fifo6_ram_dp_32_5
u_ram
(
// Inputs
.clk0_i(wr_clk_i),
.rst0_i(wr_rst_i),
.clk1_i(rd_clk_i),
.rst1_i(rd_rst_i),
// Write side
.addr0_i(wr_ptr_q),
.wr0_i(wr_push_i & ~wr_full_o),
.data0_i(wr_data_i),
.data0_o(),
// Read side
.addr1_i(rd_ptr_q),
.data1_i(6'b0),
.wr1_i(1'b0),
.data1_o(rd_data_w)
);
//-----------------------------------------------------------------
// Read
//-----------------------------------------------------------------
wire [4:0] rd_wr_ptr_w;
axi4_cdc_fifo6_resync_bus
#( .WIDTH(5))
u_resync_wr_ptr_q
(
.wr_clk_i(wr_clk_i),
.wr_rst_i(wr_rst_i),
.wr_i(1'b1),
.wr_data_i(wr_ptr_q),
.wr_busy_o(),
.rd_clk_i(rd_clk_i),
.rd_rst_i(rd_rst_i),
.rd_data_o(rd_wr_ptr_w) // Delayed version of wr_ptr_q
);
//-------------------------------------------------------------------
// Read Skid Buffer
//-------------------------------------------------------------------
reg rd_skid_q;
reg [5:0] rd_skid_data_q;
reg rd_q;
wire read_ok_w = (rd_wr_ptr_w != rd_ptr_q);
wire valid_w = (rd_skid_q | rd_q);
always @ (posedge rd_clk_i or posedge rd_rst_i)
if (rd_rst_i)
begin
rd_skid_q <= 1'b0;
rd_skid_data_q <= 6'b0;
end
else if (valid_w && !rd_pop_i)
begin
rd_skid_q <= 1'b1;
rd_skid_data_q <= rd_data_o;
end
else
begin
rd_skid_q <= 1'b0;
rd_skid_data_q <= 6'b0;
end
assign rd_data_o = rd_skid_q ? rd_skid_data_q : rd_data_w;
//-----------------------------------------------------------------
// Read Pointer
//-----------------------------------------------------------------
always @ (posedge rd_clk_i or posedge rd_rst_i)
if (rd_rst_i)
rd_q <= 1'b0;
else
rd_q <= read_ok_w;
wire [4:0] rd_ptr_next_w = rd_ptr_q + 5'd1;
always @ (posedge rd_clk_i or posedge rd_rst_i)
if (rd_rst_i)
rd_ptr_q <= 5'b0;
// Read address increment
else if (read_ok_w && ((!valid_w) || (valid_w && rd_pop_i)))
rd_ptr_q <= rd_ptr_next_w;
assign rd_empty_o = !valid_w;
endmodule |
module axi4_cdc_fifo6_ram_dp_32_5
(
// Inputs
input clk0_i
,input rst0_i
,input [ 4:0] addr0_i
,input [ 5:0] data0_i
,input wr0_i
,input clk1_i
,input rst1_i
,input [ 4:0] addr1_i
,input [ 5:0] data1_i
,input wr1_i
// Outputs
,output [ 5:0] data0_o
,output [ 5:0] data1_o
);
/* verilator lint_off MULTIDRIVEN */
reg [5:0] ram [31:0] /*verilator public*/;
/* verilator lint_on MULTIDRIVEN */
reg [5:0] ram_read0_q;
reg [5:0] ram_read1_q;
// Synchronous write
always @ (posedge clk0_i)
begin
if (wr0_i)
ram[addr0_i] <= data0_i;
ram_read0_q <= ram[addr0_i];
end
always @ (posedge clk1_i)
begin
if (wr1_i)
ram[addr1_i] <= data1_i;
ram_read1_q <= ram[addr1_i];
end
assign data0_o = ram_read0_q;
assign data1_o = ram_read1_q;
endmodule |
module axi4_cdc_fifo6_resync_bus
//-----------------------------------------------------------------
// Params
//-----------------------------------------------------------------
#(
parameter WIDTH = 4
)
//-----------------------------------------------------------------
// Ports
//-----------------------------------------------------------------
(
input wr_clk_i,
input wr_rst_i,
input wr_i,
input [WIDTH-1:0] wr_data_i,
output wr_busy_o,
input rd_clk_i,
input rd_rst_i,
output [WIDTH-1:0] rd_data_o
);
wire rd_toggle_w;
wire wr_toggle_w;
//-----------------------------------------------------------------
// Write
//-----------------------------------------------------------------
wire write_req_w = wr_i && !wr_busy_o;
// Write storage for domain crossing
(* ASYNC_REG = "TRUE" *) reg [WIDTH-1:0] wr_buffer_q;
always @ (posedge wr_clk_i or posedge wr_rst_i)
if (wr_rst_i)
wr_buffer_q <= {(WIDTH){1'b0}};
else if (write_req_w)
wr_buffer_q <= wr_data_i;
reg wr_toggle_q;
always @ (posedge wr_clk_i or posedge wr_rst_i)
if (wr_rst_i)
wr_toggle_q <= 1'b0;
else if (write_req_w)
wr_toggle_q <= ~wr_toggle_q;
reg wr_busy_q;
always @ (posedge wr_clk_i or posedge wr_rst_i)
if (wr_rst_i)
wr_busy_q <= 1'b0;
else if (write_req_w)
wr_busy_q <= 1'b1;
else if (wr_toggle_q == wr_toggle_w)
wr_busy_q <= 1'b0;
assign wr_busy_o = wr_busy_q;
//-----------------------------------------------------------------
// Write -> Read request
//-----------------------------------------------------------------
axi4_cdc_fifo6_resync
u_sync_wr_toggle
(
.clk_i(rd_clk_i),
.rst_i(rd_rst_i),
.async_i(wr_toggle_q),
.sync_o(rd_toggle_w)
);
//-----------------------------------------------------------------
// Read
//-----------------------------------------------------------------
reg rd_toggle_q;
always @ (posedge rd_clk_i or posedge rd_rst_i)
if (rd_rst_i)
rd_toggle_q <= 1'b0;
else
rd_toggle_q <= rd_toggle_w;
// Read storage for domain crossing
(* ASYNC_REG = "TRUE" *) reg [WIDTH-1:0] rd_buffer_q;
always @ (posedge rd_clk_i or posedge rd_rst_i)
if (rd_rst_i)
rd_buffer_q <= {(WIDTH){1'b0}};
else if (rd_toggle_q != rd_toggle_w)
rd_buffer_q <= wr_buffer_q; // Capture from other domain
assign rd_data_o = rd_buffer_q;
//-----------------------------------------------------------------
// Read->Write response
//-----------------------------------------------------------------
axi4_cdc_fifo6_resync
u_sync_rd_toggle
(
.clk_i(wr_clk_i),
.rst_i(wr_rst_i),
.async_i(rd_toggle_q),
.sync_o(wr_toggle_w)
);
endmodule |
module axi4_cdc_fifo6_resync
//-----------------------------------------------------------------
// Params
//-----------------------------------------------------------------
#(
parameter RESET_VAL = 1'b0
)
//-----------------------------------------------------------------
// Ports
//-----------------------------------------------------------------
(
input clk_i,
input rst_i,
input async_i,
output sync_o
);
(* ASYNC_REG = "TRUE" *) reg sync_ms;
(* ASYNC_REG = "TRUE" *) reg sync_q;
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
begin
sync_ms <= RESET_VAL;
sync_q <= RESET_VAL;
end
else
begin
sync_ms <= async_i;
sync_q <= sync_ms;
end
assign sync_o = sync_q;
endmodule |
module axi4_cdc_fifo46
(
// Inputs
input rd_clk_i
,input rd_rst_i
,input rd_pop_i
,input wr_clk_i
,input wr_rst_i
,input [ 45:0] wr_data_i
,input wr_push_i
// Outputs
,output [ 45:0] rd_data_o
,output rd_empty_o
,output wr_full_o
);
//-----------------------------------------------------------------
// Registers
//-----------------------------------------------------------------
reg [4:0] rd_ptr_q;
reg [4:0] wr_ptr_q;
//-----------------------------------------------------------------
// Write
//-----------------------------------------------------------------
wire [4:0] wr_ptr_next_w = wr_ptr_q + 5'd1;
always @ (posedge wr_clk_i or posedge wr_rst_i)
if (wr_rst_i)
wr_ptr_q <= 5'b0;
else if (wr_push_i & ~wr_full_o)
wr_ptr_q <= wr_ptr_next_w;
wire [4:0] wr_rd_ptr_w;
axi4_cdc_fifo46_resync_bus
#( .WIDTH(5))
u_resync_rd_ptr_q
(
.wr_clk_i(rd_clk_i),
.wr_rst_i(rd_rst_i),
.wr_i(1'b1),
.wr_data_i(rd_ptr_q),
.wr_busy_o(),
.rd_clk_i(wr_clk_i),
.rd_rst_i(wr_rst_i),
.rd_data_o(wr_rd_ptr_w) // Delayed version of rd_ptr_q
);
assign wr_full_o = (wr_ptr_next_w == wr_rd_ptr_w);
//-------------------------------------------------------------------
// Dual port RAM
//-------------------------------------------------------------------
wire [45:0] rd_data_w;
axi4_cdc_fifo46_ram_dp_32_5
u_ram
(
// Inputs
.clk0_i(wr_clk_i),
.rst0_i(wr_rst_i),
.clk1_i(rd_clk_i),
.rst1_i(rd_rst_i),
// Write side
.addr0_i(wr_ptr_q),
.wr0_i(wr_push_i & ~wr_full_o),
.data0_i(wr_data_i),
.data0_o(),
// Read side
.addr1_i(rd_ptr_q),
.data1_i(46'b0),
.wr1_i(1'b0),
.data1_o(rd_data_w)
);
//-----------------------------------------------------------------
// Read
//-----------------------------------------------------------------
wire [4:0] rd_wr_ptr_w;
axi4_cdc_fifo46_resync_bus
#( .WIDTH(5))
u_resync_wr_ptr_q
(
.wr_clk_i(wr_clk_i),
.wr_rst_i(wr_rst_i),
.wr_i(1'b1),
.wr_data_i(wr_ptr_q),
.wr_busy_o(),
.rd_clk_i(rd_clk_i),
.rd_rst_i(rd_rst_i),
.rd_data_o(rd_wr_ptr_w) // Delayed version of wr_ptr_q
);
//-------------------------------------------------------------------
// Read Skid Buffer
//-------------------------------------------------------------------
reg rd_skid_q;
reg [45:0] rd_skid_data_q;
reg rd_q;
wire read_ok_w = (rd_wr_ptr_w != rd_ptr_q);
wire valid_w = (rd_skid_q | rd_q);
always @ (posedge rd_clk_i or posedge rd_rst_i)
if (rd_rst_i)
begin
rd_skid_q <= 1'b0;
rd_skid_data_q <= 46'b0;
end
else if (valid_w && !rd_pop_i)
begin
rd_skid_q <= 1'b1;
rd_skid_data_q <= rd_data_o;
end
else
begin
rd_skid_q <= 1'b0;
rd_skid_data_q <= 46'b0;
end
assign rd_data_o = rd_skid_q ? rd_skid_data_q : rd_data_w;
//-----------------------------------------------------------------
// Read Pointer
//-----------------------------------------------------------------
always @ (posedge rd_clk_i or posedge rd_rst_i)
if (rd_rst_i)
rd_q <= 1'b0;
else
rd_q <= read_ok_w;
wire [4:0] rd_ptr_next_w = rd_ptr_q + 5'd1;
always @ (posedge rd_clk_i or posedge rd_rst_i)
if (rd_rst_i)
rd_ptr_q <= 5'b0;
// Read address increment
else if (read_ok_w && ((!valid_w) || (valid_w && rd_pop_i)))
rd_ptr_q <= rd_ptr_next_w;
assign rd_empty_o = !valid_w;
endmodule |
module axi4_cdc_fifo46_ram_dp_32_5
(
// Inputs
input clk0_i
,input rst0_i
,input [ 4:0] addr0_i
,input [ 45:0] data0_i
,input wr0_i
,input clk1_i
,input rst1_i
,input [ 4:0] addr1_i
,input [ 45:0] data1_i
,input wr1_i
// Outputs
,output [ 45:0] data0_o
,output [ 45:0] data1_o
);
/* verilator lint_off MULTIDRIVEN */
reg [45:0] ram [31:0] /*verilator public*/;
/* verilator lint_on MULTIDRIVEN */
reg [45:0] ram_read0_q;
reg [45:0] ram_read1_q;
// Synchronous write
always @ (posedge clk0_i)
begin
if (wr0_i)
ram[addr0_i] <= data0_i;
ram_read0_q <= ram[addr0_i];
end
always @ (posedge clk1_i)
begin
if (wr1_i)
ram[addr1_i] <= data1_i;
ram_read1_q <= ram[addr1_i];
end
assign data0_o = ram_read0_q;
assign data1_o = ram_read1_q;
endmodule |
module axi4_cdc_fifo46_resync_bus
//-----------------------------------------------------------------
// Params
//-----------------------------------------------------------------
#(
parameter WIDTH = 4
)
//-----------------------------------------------------------------
// Ports
//-----------------------------------------------------------------
(
input wr_clk_i,
input wr_rst_i,
input wr_i,
input [WIDTH-1:0] wr_data_i,
output wr_busy_o,
input rd_clk_i,
input rd_rst_i,
output [WIDTH-1:0] rd_data_o
);
wire rd_toggle_w;
wire wr_toggle_w;
//-----------------------------------------------------------------
// Write
//-----------------------------------------------------------------
wire write_req_w = wr_i && !wr_busy_o;
// Write storage for domain crossing
(* ASYNC_REG = "TRUE" *) reg [WIDTH-1:0] wr_buffer_q;
always @ (posedge wr_clk_i or posedge wr_rst_i)
if (wr_rst_i)
wr_buffer_q <= {(WIDTH){1'b0}};
else if (write_req_w)
wr_buffer_q <= wr_data_i;
reg wr_toggle_q;
always @ (posedge wr_clk_i or posedge wr_rst_i)
if (wr_rst_i)
wr_toggle_q <= 1'b0;
else if (write_req_w)
wr_toggle_q <= ~wr_toggle_q;
reg wr_busy_q;
always @ (posedge wr_clk_i or posedge wr_rst_i)
if (wr_rst_i)
wr_busy_q <= 1'b0;
else if (write_req_w)
wr_busy_q <= 1'b1;
else if (wr_toggle_q == wr_toggle_w)
wr_busy_q <= 1'b0;
assign wr_busy_o = wr_busy_q;
//-----------------------------------------------------------------
// Write -> Read request
//-----------------------------------------------------------------
axi4_cdc_fifo46_resync
u_sync_wr_toggle
(
.clk_i(rd_clk_i),
.rst_i(rd_rst_i),
.async_i(wr_toggle_q),
.sync_o(rd_toggle_w)
);
//-----------------------------------------------------------------
// Read
//-----------------------------------------------------------------
reg rd_toggle_q;
always @ (posedge rd_clk_i or posedge rd_rst_i)
if (rd_rst_i)
rd_toggle_q <= 1'b0;
else
rd_toggle_q <= rd_toggle_w;
// Read storage for domain crossing
(* ASYNC_REG = "TRUE" *) reg [WIDTH-1:0] rd_buffer_q;
always @ (posedge rd_clk_i or posedge rd_rst_i)
if (rd_rst_i)
rd_buffer_q <= {(WIDTH){1'b0}};
else if (rd_toggle_q != rd_toggle_w)
rd_buffer_q <= wr_buffer_q; // Capture from other domain
assign rd_data_o = rd_buffer_q;
//-----------------------------------------------------------------
// Read->Write response
//-----------------------------------------------------------------
axi4_cdc_fifo46_resync
u_sync_rd_toggle
(
.clk_i(wr_clk_i),
.rst_i(wr_rst_i),
.async_i(rd_toggle_q),
.sync_o(wr_toggle_w)
);
endmodule |
module axi4_cdc_fifo46_resync
//-----------------------------------------------------------------
// Params
//-----------------------------------------------------------------
#(
parameter RESET_VAL = 1'b0
)
//-----------------------------------------------------------------
// Ports
//-----------------------------------------------------------------
(
input clk_i,
input rst_i,
input async_i,
output sync_o
);
(* ASYNC_REG = "TRUE" *) reg sync_ms;
(* ASYNC_REG = "TRUE" *) reg sync_q;
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
begin
sync_ms <= RESET_VAL;
sync_q <= RESET_VAL;
end
else
begin
sync_ms <= async_i;
sync_q <= sync_ms;
end
assign sync_o = sync_q;
endmodule |
module axi4_cdc_fifo37
(
// Inputs
input rd_clk_i
,input rd_rst_i
,input rd_pop_i
,input wr_clk_i
,input wr_rst_i
,input [ 36:0] wr_data_i
,input wr_push_i
// Outputs
,output [ 36:0] rd_data_o
,output rd_empty_o
,output wr_full_o
);
//-----------------------------------------------------------------
// Registers
//-----------------------------------------------------------------
reg [4:0] rd_ptr_q;
reg [4:0] wr_ptr_q;
//-----------------------------------------------------------------
// Write
//-----------------------------------------------------------------
wire [4:0] wr_ptr_next_w = wr_ptr_q + 5'd1;
always @ (posedge wr_clk_i or posedge wr_rst_i)
if (wr_rst_i)
wr_ptr_q <= 5'b0;
else if (wr_push_i & ~wr_full_o)
wr_ptr_q <= wr_ptr_next_w;
wire [4:0] wr_rd_ptr_w;
axi4_cdc_fifo37_resync_bus
#( .WIDTH(5))
u_resync_rd_ptr_q
(
.wr_clk_i(rd_clk_i),
.wr_rst_i(rd_rst_i),
.wr_i(1'b1),
.wr_data_i(rd_ptr_q),
.wr_busy_o(),
.rd_clk_i(wr_clk_i),
.rd_rst_i(wr_rst_i),
.rd_data_o(wr_rd_ptr_w) // Delayed version of rd_ptr_q
);
assign wr_full_o = (wr_ptr_next_w == wr_rd_ptr_w);
//-------------------------------------------------------------------
// Dual port RAM
//-------------------------------------------------------------------
wire [36:0] rd_data_w;
axi4_cdc_fifo37_ram_dp_32_5
u_ram
(
// Inputs
.clk0_i(wr_clk_i),
.rst0_i(wr_rst_i),
.clk1_i(rd_clk_i),
.rst1_i(rd_rst_i),
// Write side
.addr0_i(wr_ptr_q),
.wr0_i(wr_push_i & ~wr_full_o),
.data0_i(wr_data_i),
.data0_o(),
// Read side
.addr1_i(rd_ptr_q),
.data1_i(37'b0),
.wr1_i(1'b0),
.data1_o(rd_data_w)
);
//-----------------------------------------------------------------
// Read
//-----------------------------------------------------------------
wire [4:0] rd_wr_ptr_w;
axi4_cdc_fifo37_resync_bus
#( .WIDTH(5))
u_resync_wr_ptr_q
(
.wr_clk_i(wr_clk_i),
.wr_rst_i(wr_rst_i),
.wr_i(1'b1),
.wr_data_i(wr_ptr_q),
.wr_busy_o(),
.rd_clk_i(rd_clk_i),
.rd_rst_i(rd_rst_i),
.rd_data_o(rd_wr_ptr_w) // Delayed version of wr_ptr_q
);
//-------------------------------------------------------------------
// Read Skid Buffer
//-------------------------------------------------------------------
reg rd_skid_q;
reg [36:0] rd_skid_data_q;
reg rd_q;
wire read_ok_w = (rd_wr_ptr_w != rd_ptr_q);
wire valid_w = (rd_skid_q | rd_q);
always @ (posedge rd_clk_i or posedge rd_rst_i)
if (rd_rst_i)
begin
rd_skid_q <= 1'b0;
rd_skid_data_q <= 37'b0;
end
else if (valid_w && !rd_pop_i)
begin
rd_skid_q <= 1'b1;
rd_skid_data_q <= rd_data_o;
end
else
begin
rd_skid_q <= 1'b0;
rd_skid_data_q <= 37'b0;
end
assign rd_data_o = rd_skid_q ? rd_skid_data_q : rd_data_w;
//-----------------------------------------------------------------
// Read Pointer
//-----------------------------------------------------------------
always @ (posedge rd_clk_i or posedge rd_rst_i)
if (rd_rst_i)
rd_q <= 1'b0;
else
rd_q <= read_ok_w;
wire [4:0] rd_ptr_next_w = rd_ptr_q + 5'd1;
always @ (posedge rd_clk_i or posedge rd_rst_i)
if (rd_rst_i)
rd_ptr_q <= 5'b0;
// Read address increment
else if (read_ok_w && ((!valid_w) || (valid_w && rd_pop_i)))
rd_ptr_q <= rd_ptr_next_w;
assign rd_empty_o = !valid_w;
endmodule |
module axi4_cdc_fifo37_ram_dp_32_5
(
// Inputs
input clk0_i
,input rst0_i
,input [ 4:0] addr0_i
,input [ 36:0] data0_i
,input wr0_i
,input clk1_i
,input rst1_i
,input [ 4:0] addr1_i
,input [ 36:0] data1_i
,input wr1_i
// Outputs
,output [ 36:0] data0_o
,output [ 36:0] data1_o
);
/* verilator lint_off MULTIDRIVEN */
reg [36:0] ram [31:0] /*verilator public*/;
/* verilator lint_on MULTIDRIVEN */
reg [36:0] ram_read0_q;
reg [36:0] ram_read1_q;
// Synchronous write
always @ (posedge clk0_i)
begin
if (wr0_i)
ram[addr0_i] <= data0_i;
ram_read0_q <= ram[addr0_i];
end
always @ (posedge clk1_i)
begin
if (wr1_i)
ram[addr1_i] <= data1_i;
ram_read1_q <= ram[addr1_i];
end
assign data0_o = ram_read0_q;
assign data1_o = ram_read1_q;
endmodule |
module axi4_cdc_fifo37_resync_bus
//-----------------------------------------------------------------
// Params
//-----------------------------------------------------------------
#(
parameter WIDTH = 4
)
//-----------------------------------------------------------------
// Ports
//-----------------------------------------------------------------
(
input wr_clk_i,
input wr_rst_i,
input wr_i,
input [WIDTH-1:0] wr_data_i,
output wr_busy_o,
input rd_clk_i,
input rd_rst_i,
output [WIDTH-1:0] rd_data_o
);
wire rd_toggle_w;
wire wr_toggle_w;
//-----------------------------------------------------------------
// Write
//-----------------------------------------------------------------
wire write_req_w = wr_i && !wr_busy_o;
// Write storage for domain crossing
(* ASYNC_REG = "TRUE" *) reg [WIDTH-1:0] wr_buffer_q;
always @ (posedge wr_clk_i or posedge wr_rst_i)
if (wr_rst_i)
wr_buffer_q <= {(WIDTH){1'b0}};
else if (write_req_w)
wr_buffer_q <= wr_data_i;
reg wr_toggle_q;
always @ (posedge wr_clk_i or posedge wr_rst_i)
if (wr_rst_i)
wr_toggle_q <= 1'b0;
else if (write_req_w)
wr_toggle_q <= ~wr_toggle_q;
reg wr_busy_q;
always @ (posedge wr_clk_i or posedge wr_rst_i)
if (wr_rst_i)
wr_busy_q <= 1'b0;
else if (write_req_w)
wr_busy_q <= 1'b1;
else if (wr_toggle_q == wr_toggle_w)
wr_busy_q <= 1'b0;
assign wr_busy_o = wr_busy_q;
//-----------------------------------------------------------------
// Write -> Read request
//-----------------------------------------------------------------
axi4_cdc_fifo37_resync
u_sync_wr_toggle
(
.clk_i(rd_clk_i),
.rst_i(rd_rst_i),
.async_i(wr_toggle_q),
.sync_o(rd_toggle_w)
);
//-----------------------------------------------------------------
// Read
//-----------------------------------------------------------------
reg rd_toggle_q;
always @ (posedge rd_clk_i or posedge rd_rst_i)
if (rd_rst_i)
rd_toggle_q <= 1'b0;
else
rd_toggle_q <= rd_toggle_w;
// Read storage for domain crossing
(* ASYNC_REG = "TRUE" *) reg [WIDTH-1:0] rd_buffer_q;
always @ (posedge rd_clk_i or posedge rd_rst_i)
if (rd_rst_i)
rd_buffer_q <= {(WIDTH){1'b0}};
else if (rd_toggle_q != rd_toggle_w)
rd_buffer_q <= wr_buffer_q; // Capture from other domain
assign rd_data_o = rd_buffer_q;
//-----------------------------------------------------------------
// Read->Write response
//-----------------------------------------------------------------
axi4_cdc_fifo37_resync
u_sync_rd_toggle
(
.clk_i(wr_clk_i),
.rst_i(wr_rst_i),
.async_i(rd_toggle_q),
.sync_o(wr_toggle_w)
);
endmodule |
module axi4_cdc_fifo37_resync
//-----------------------------------------------------------------
// Params
//-----------------------------------------------------------------
#(
parameter RESET_VAL = 1'b0
)
//-----------------------------------------------------------------
// Ports
//-----------------------------------------------------------------
(
input clk_i,
input rst_i,
input async_i,
output sync_o
);
(* ASYNC_REG = "TRUE" *) reg sync_ms;
(* ASYNC_REG = "TRUE" *) reg sync_q;
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
begin
sync_ms <= RESET_VAL;
sync_q <= RESET_VAL;
end
else
begin
sync_ms <= async_i;
sync_q <= sync_ms;
end
assign sync_o = sync_q;
endmodule |
module axi4_cdc
(
// Inputs
input wr_clk_i
,input wr_rst_i
,input inport_awvalid_i
,input [ 31:0] inport_awaddr_i
,input [ 3:0] inport_awid_i
,input [ 7:0] inport_awlen_i
,input [ 1:0] inport_awburst_i
,input inport_wvalid_i
,input [ 31:0] inport_wdata_i
,input [ 3:0] inport_wstrb_i
,input inport_wlast_i
,input inport_bready_i
,input inport_arvalid_i
,input [ 31:0] inport_araddr_i
,input [ 3:0] inport_arid_i
,input [ 7:0] inport_arlen_i
,input [ 1:0] inport_arburst_i
,input inport_rready_i
,input rd_clk_i
,input rd_rst_i
,input outport_awready_i
,input outport_wready_i
,input outport_bvalid_i
,input [ 1:0] outport_bresp_i
,input [ 3:0] outport_bid_i
,input outport_arready_i
,input outport_rvalid_i
,input [ 31:0] outport_rdata_i
,input [ 1:0] outport_rresp_i
,input [ 3:0] outport_rid_i
,input outport_rlast_i
// Outputs
,output inport_awready_o
,output inport_wready_o
,output inport_bvalid_o
,output [ 1:0] inport_bresp_o
,output [ 3:0] inport_bid_o
,output inport_arready_o
,output inport_rvalid_o
,output [ 31:0] inport_rdata_o
,output [ 1:0] inport_rresp_o
,output [ 3:0] inport_rid_o
,output inport_rlast_o
,output outport_awvalid_o
,output [ 31:0] outport_awaddr_o
,output [ 3:0] outport_awid_o
,output [ 7:0] outport_awlen_o
,output [ 1:0] outport_awburst_o
,output outport_wvalid_o
,output [ 31:0] outport_wdata_o
,output [ 3:0] outport_wstrb_o
,output outport_wlast_o
,output outport_bready_o
,output outport_arvalid_o
,output [ 31:0] outport_araddr_o
,output [ 3:0] outport_arid_o
,output [ 7:0] outport_arlen_o
,output [ 1:0] outport_arburst_o
,output outport_rready_o
);
//-----------------------------------------------------------------
// Write Command Request
//-----------------------------------------------------------------
wire [45:0] write_cmd_req_out_w;
wire write_cmd_full_w;
wire read_cmd_empty_w;
axi4_cdc_fifo46
u_write_cmd_req
(
.wr_clk_i(wr_clk_i),
.wr_rst_i(wr_rst_i),
.wr_push_i(inport_awvalid_i),
.wr_data_i({inport_awaddr_i, inport_awid_i, inport_awlen_i, inport_awburst_i}),
.wr_full_o(write_cmd_full_w),
.rd_clk_i(rd_clk_i),
.rd_rst_i(rd_rst_i),
.rd_empty_o(read_cmd_empty_w),
.rd_data_o(write_cmd_req_out_w),
.rd_pop_i(outport_awready_i)
);
assign inport_awready_o = ~write_cmd_full_w;
assign outport_awvalid_o = ~read_cmd_empty_w;
assign {outport_awaddr_o, outport_awid_o, outport_awlen_o, outport_awburst_o} = write_cmd_req_out_w;
//-----------------------------------------------------------------
// Write Data Request
//-----------------------------------------------------------------
wire [36:0] write_data_req_out_w;
wire write_data_full_w;
wire write_data_empty_w;
axi4_cdc_fifo37
u_write_data_req
(
.wr_clk_i(wr_clk_i),
.wr_rst_i(wr_rst_i),
.wr_push_i(inport_wvalid_i),
.wr_data_i({inport_wlast_i, inport_wstrb_i, inport_wdata_i}),
.wr_full_o(write_data_full_w),
.rd_clk_i(rd_clk_i),
.rd_rst_i(rd_rst_i),
.rd_empty_o(write_data_empty_w),
.rd_data_o(write_data_req_out_w),
.rd_pop_i(outport_wready_i)
);
assign inport_wready_o = ~write_data_full_w;
assign outport_wvalid_o = ~write_data_empty_w;
assign {outport_wlast_o, outport_wstrb_o, outport_wdata_o} = write_data_req_out_w;
//-----------------------------------------------------------------
// Write Response
//-----------------------------------------------------------------
wire [5:0] write_resp_out_w;
wire write_resp_full_w;
wire write_resp_empty_w;
axi4_cdc_fifo6
u_write_resp
(
.wr_clk_i(rd_clk_i),
.wr_rst_i(rd_rst_i),
.wr_push_i(outport_bvalid_i),
.wr_data_i({outport_bresp_i, outport_bid_i}),
.wr_full_o(write_resp_full_w),
.rd_clk_i(wr_clk_i),
.rd_rst_i(wr_rst_i),
.rd_empty_o(write_resp_empty_w),
.rd_data_o(write_resp_out_w),
.rd_pop_i(inport_bready_i)
);
assign outport_bready_o = ~write_resp_full_w;
assign inport_bvalid_o = ~write_resp_empty_w;
assign {inport_bresp_o, inport_bid_o} = write_resp_out_w;
//-----------------------------------------------------------------
// Read Request
//-----------------------------------------------------------------
wire [45:0] read_req_out_w;
wire read_req_full_w;
wire read_req_empty_w;
axi4_cdc_fifo46
u_read_req
(
.wr_clk_i(wr_clk_i),
.wr_rst_i(wr_rst_i),
.wr_push_i(inport_arvalid_i),
.wr_data_i({inport_araddr_i, inport_arid_i, inport_arlen_i, inport_arburst_i}),
.wr_full_o(read_req_full_w),
.rd_clk_i(rd_clk_i),
.rd_rst_i(rd_rst_i),
.rd_empty_o(read_req_empty_w),
.rd_data_o(read_req_out_w),
.rd_pop_i(outport_arready_i)
);
assign inport_arready_o = ~read_req_full_w;
assign outport_arvalid_o = ~read_req_empty_w;
assign {outport_araddr_o, outport_arid_o, outport_arlen_o, outport_arburst_o} = read_req_out_w;
//-----------------------------------------------------------------
// Read Response
//-----------------------------------------------------------------
wire [38:0] read_resp_out_w;
wire read_resp_full_w;
wire read_resp_empty_w;
axi4_cdc_fifo39
u_read_resp
(
.wr_clk_i(rd_clk_i),
.wr_rst_i(rd_rst_i),
.wr_push_i(outport_rvalid_i),
.wr_data_i({outport_rdata_i, outport_rresp_i, outport_rid_i, outport_rlast_i}),
.wr_full_o(read_resp_full_w),
.rd_clk_i(wr_clk_i),
.rd_rst_i(wr_rst_i),
.rd_empty_o(read_resp_empty_w),
.rd_data_o(read_resp_out_w),
.rd_pop_i(inport_rready_i)
);
assign outport_rready_o = ~read_resp_full_w;
assign inport_rvalid_o = ~read_resp_empty_w;
assign {inport_rdata_o, inport_rresp_o, inport_rid_o, inport_rlast_o} = read_resp_out_w;
endmodule |
module capture_rle
(
// Inputs
input clk_i
,input rst_i
,input input_clk_i
,input input_rst_i
,input [ 31:0] input_i
,input [ 3:0] cfg_clk_div_i
,input [ 1:0] cfg_width_i
,input cfg_test_mode_i
// Outputs
,output valid_o
,output [ 31:0] data_o
);
//-----------------------------------------------------------------
// Config
//-----------------------------------------------------------------
// These may come from another clock domain - they will be stable prior
// to enabling, but resync to keep the timing tools happy.
(* ASYNC_REG = "TRUE" *) reg [6:0] cfg_ms_q;
always @ (posedge input_clk_i )
if (input_rst_i)
cfg_ms_q <= 7'b0;
else
cfg_ms_q <= {cfg_test_mode_i, cfg_width_i, cfg_clk_div_i};
reg [6:0] cfg_q;
always @ (posedge input_clk_i )
if (input_rst_i)
cfg_q <= 7'b0;
else
cfg_q <= cfg_ms_q;
wire cfg_32bit_w;
wire cfg_24bit_w;
wire [3:0] cfg_clk_div_w;
wire cfg_test_mode_w;
assign {cfg_test_mode_w, cfg_32bit_w, cfg_24bit_w, cfg_clk_div_w} = cfg_q;
//-----------------------------------------------------------------
// Clock divider
//-----------------------------------------------------------------
reg [3:0] clk_div_q;
always @ (posedge clk_i )
if (rst_i)
clk_div_q <= 4'd0;
else if (clk_div_q == 4'd0)
clk_div_q <= cfg_clk_div_w;
else
clk_div_q <= clk_div_q - 4'd1;
wire clk_en_w = (clk_div_q == 4'd0);
//-----------------------------------------------------------------
// Resync
//-----------------------------------------------------------------
(* ASYNC_REG = "TRUE" *) reg [31:0] resync_ms_q;
always @ (posedge input_clk_i )
if (input_rst_i)
resync_ms_q <= 32'b0;
else
resync_ms_q <= input_i;
//-----------------------------------------------------------------
// Sample capture
//-----------------------------------------------------------------
reg [31:0] capture_q;
always @ (posedge input_clk_i )
if (input_rst_i)
capture_q <= 32'b0;
else
capture_q <= resync_ms_q;
//-----------------------------------------------------------------
// Test mode
//-----------------------------------------------------------------
reg [31:0] test_count_q;
always @ (posedge input_clk_i )
if (input_rst_i)
test_count_q <= 32'b0;
else if (clk_en_w)
test_count_q <= test_count_q + 32'd1;
wire [31:0] capture_w = cfg_test_mode_w ? test_count_q : capture_q;
//-----------------------------------------------------------------
// Previous capture
//-----------------------------------------------------------------
reg [31:0] prev_q;
always @ (posedge input_clk_i )
if (input_rst_i)
prev_q <= 32'b0;
else if (clk_en_w)
prev_q <= capture_w;
wire same_w = (prev_q == capture_w);
reg prev_valid_q;
always @ (posedge input_clk_i )
if (input_rst_i)
prev_valid_q <= 1'b0;
else if (clk_en_w)
prev_valid_q <= 1'b1;
//-----------------------------------------------------------------
// RLE count
//-----------------------------------------------------------------
reg [15:0] rle_count_q;
wire overflow_w = cfg_32bit_w ? 1'b1 :
cfg_24bit_w ? (rle_count_q >= 16'hFF) :
(rle_count_q == 16'hFFFF);
always @ (posedge input_clk_i )
if (input_rst_i)
rle_count_q <= 16'd1;
else if (!clk_en_w)
;
else if (overflow_w || !same_w)
rle_count_q <= 16'd1;
else
rle_count_q <= rle_count_q + 16'd1;
//-----------------------------------------------------------------
// Output retime
//-----------------------------------------------------------------
reg valid_q;
reg [31:0] data_q;
always @ (posedge input_clk_i )
if (input_rst_i)
valid_q <= 1'b0;
else
valid_q <= (!same_w || overflow_w) && prev_valid_q && clk_en_w;
always @ (posedge input_clk_i )
if (input_rst_i)
data_q <= 32'b0;
else if (!clk_en_w)
;
else if (cfg_32bit_w)
data_q <= prev_q;
else if (cfg_24bit_w)
data_q <= {rle_count_q[7:0], prev_q[23:0]};
else
data_q <= {rle_count_q[15:0], prev_q[15:0]};
//-----------------------------------------------------------------
// Output
//-----------------------------------------------------------------
wire output_empty_w;
capture_rle_cdc
u_cdc
(
.wr_clk_i(input_clk_i)
,.wr_rst_i(input_rst_i)
,.wr_push_i(valid_q)
,.wr_data_i(data_q)
,.wr_full_o()
,.rd_clk_i(clk_i)
,.rd_rst_i(rst_i)
,.rd_data_o(data_o)
,.rd_empty_o(output_empty_w)
,.rd_pop_i(1'b1)
);
assign valid_o = ~output_empty_w;
endmodule |
module logic_capture_mem_axi_axi
(
// Inputs
input clk_i
,input rst_i
,input inport_valid_i
,input inport_write_i
,input [ 31:0] inport_addr_i
,input [ 3:0] inport_id_i
,input [ 7:0] inport_len_i
,input [ 1:0] inport_burst_i
,input [ 31:0] inport_wdata_i
,input [ 3:0] inport_wstrb_i
,input inport_bready_i
,input inport_rready_i
,input outport_awready_i
,input outport_wready_i
,input outport_bvalid_i
,input [ 1:0] outport_bresp_i
,input [ 3:0] outport_bid_i
,input outport_arready_i
,input outport_rvalid_i
,input [ 31:0] outport_rdata_i
,input [ 1:0] outport_rresp_i
,input [ 3:0] outport_rid_i
,input outport_rlast_i
// Outputs
,output inport_accept_o
,output inport_bvalid_o
,output [ 1:0] inport_bresp_o
,output [ 3:0] inport_bid_o
,output inport_rvalid_o
,output [ 31:0] inport_rdata_o
,output [ 1:0] inport_rresp_o
,output [ 3:0] inport_rid_o
,output inport_rlast_o
,output outport_awvalid_o
,output [ 31:0] outport_awaddr_o
,output [ 3:0] outport_awid_o
,output [ 7:0] outport_awlen_o
,output [ 1:0] outport_awburst_o
,output outport_wvalid_o
,output [ 31:0] outport_wdata_o
,output [ 3:0] outport_wstrb_o
,output outport_wlast_o
,output outport_bready_o
,output outport_arvalid_o
,output [ 31:0] outport_araddr_o
,output [ 3:0] outport_arid_o
,output [ 7:0] outport_arlen_o
,output [ 1:0] outport_arburst_o
,output outport_rready_o
);
//-------------------------------------------------------------
// Write burst tracking
//-------------------------------------------------------------
reg [7:0] req_cnt_q;
always @ (posedge clk_i )
if (rst_i)
req_cnt_q <= 8'b0;
else if (inport_valid_i && inport_write_i && inport_accept_o)
begin
if (req_cnt_q != 8'b0)
req_cnt_q <= req_cnt_q - 8'd1;
else
req_cnt_q <= inport_len_i;
end
//-------------------------------------------------------------
// Request skid buffer
//-------------------------------------------------------------
reg valid_q;
reg [83:0] buf_q;
always @ (posedge clk_i )
if (rst_i)
valid_q <= 1'b0;
else if (inport_valid_i && inport_accept_o && ((outport_awvalid_o && !outport_awready_i) || (outport_wvalid_o && !outport_wready_i) || (outport_arvalid_o && !outport_arready_i)))
valid_q <= 1'b1;
else if ((!outport_awvalid_o || outport_awready_i) && (!outport_wvalid_o || outport_wready_i) && (!outport_arvalid_o || outport_arready_i))
valid_q <= 1'b0;
wire inport_valid_w = valid_q || inport_valid_i;
wire inport_write_w = valid_q ? buf_q[0:0] : inport_write_i;
wire [ 31:0] inport_addr_w = valid_q ? buf_q[32:1] : inport_addr_i;
wire [ 3:0] inport_id_w = valid_q ? buf_q[36:33] : inport_id_i;
wire [ 7:0] inport_len_w = valid_q ? buf_q[44:37] : inport_len_i;
wire [ 1:0] inport_burst_w = valid_q ? buf_q[46:45] : inport_burst_i;
wire [ 31:0] inport_wdata_w = valid_q ? buf_q[78:47] : inport_wdata_i;
wire [ 3:0] inport_wstrb_w = valid_q ? buf_q[82:79] : inport_wstrb_i;
wire inport_wlast_w = valid_q ? buf_q[83:83] : (inport_len_i == 8'd0 && req_cnt_q == 8'd0) || (req_cnt_q == 8'd1);
always @ (posedge clk_i )
if (rst_i)
buf_q <= 84'b0;
else
buf_q <= {inport_wlast_w, inport_wstrb_w, inport_wdata_w, inport_burst_w, inport_len_w, inport_id_w, inport_addr_w, inport_write_w};
wire skid_busy_w = valid_q;
//-------------------------------------------------------------
// Write Request
//-------------------------------------------------------------
reg awvalid_q;
reg wvalid_q;
reg wlast_q;
wire wr_cmd_accepted_w = (outport_awvalid_o && outport_awready_i) || awvalid_q;
wire wr_data_accepted_w = (outport_wvalid_o && outport_wready_i) || wvalid_q;
wire wr_data_last_w = (wvalid_q & wlast_q) || (outport_wvalid_o && outport_wready_i && outport_wlast_o);
always @ (posedge clk_i )
if (rst_i)
awvalid_q <= 1'b0;
else if (outport_awvalid_o && outport_awready_i && (!wr_data_accepted_w || !wr_data_last_w))
awvalid_q <= 1'b1;
else if (wr_data_accepted_w && wr_data_last_w)
awvalid_q <= 1'b0;
always @ (posedge clk_i )
if (rst_i)
wvalid_q <= 1'b0;
else if (outport_wvalid_o && outport_wready_i && !wr_cmd_accepted_w)
wvalid_q <= 1'b1;
else if (wr_cmd_accepted_w)
wvalid_q <= 1'b0;
always @ (posedge clk_i )
if (rst_i)
wlast_q <= 1'b0;
else if (outport_wvalid_o && outport_wready_i)
wlast_q <= outport_wlast_o;
assign outport_awvalid_o = (inport_valid_w & inport_write_w & ~awvalid_q);
assign outport_awaddr_o = inport_addr_w;
assign outport_awid_o = inport_id_w;
assign outport_awlen_o = inport_len_w;
assign outport_awburst_o = inport_burst_w;
assign outport_wvalid_o = (inport_valid_w & inport_write_w & ~wvalid_q);
assign outport_wdata_o = inport_wdata_w;
assign outport_wstrb_o = inport_wstrb_w;
assign outport_wlast_o = inport_wlast_w;
assign inport_bvalid_o = outport_bvalid_i;
assign inport_bresp_o = outport_bresp_i;
assign inport_bid_o = outport_bid_i;
assign outport_bready_o = inport_bready_i;
//-------------------------------------------------------------
// Read Request
//-------------------------------------------------------------
assign outport_arvalid_o = inport_valid_w & ~inport_write_w;
assign outport_araddr_o = inport_addr_w;
assign outport_arid_o = inport_id_w;
assign outport_arlen_o = inport_len_w;
assign outport_arburst_o = inport_burst_w;
assign outport_rready_o = inport_rready_i;
assign inport_rvalid_o = outport_rvalid_i;
assign inport_rdata_o = outport_rdata_i;
assign inport_rresp_o = outport_rresp_i;
assign inport_rid_o = outport_rid_i;
assign inport_rlast_o = outport_rlast_i;
//-------------------------------------------------------------
// Accept logic
//-------------------------------------------------------------
assign inport_accept_o = !skid_busy_w &&
((outport_awvalid_o && outport_awready_i) ||
(outport_wvalid_o && outport_wready_i) ||
(outport_arvalid_o && outport_arready_i));
endmodule |
module logic_capture_mem
(
// Inputs
input clk_i
,input rst_i
,input cfg_awvalid_i
,input [ 31:0] cfg_awaddr_i
,input cfg_wvalid_i
,input [ 31:0] cfg_wdata_i
,input [ 3:0] cfg_wstrb_i
,input cfg_bready_i
,input cfg_arvalid_i
,input [ 31:0] cfg_araddr_i
,input cfg_rready_i
,input input_valid_i
,input [ 31:0] input_data_i
,input outport_awready_i
,input outport_wready_i
,input outport_bvalid_i
,input [ 1:0] outport_bresp_i
,input [ 3:0] outport_bid_i
,input outport_arready_i
,input outport_rvalid_i
,input [ 31:0] outport_rdata_i
,input [ 1:0] outport_rresp_i
,input [ 3:0] outport_rid_i
,input outport_rlast_i
// Outputs
,output cfg_awready_o
,output cfg_wready_o
,output cfg_bvalid_o
,output [ 1:0] cfg_bresp_o
,output cfg_arready_o
,output cfg_rvalid_o
,output [ 31:0] cfg_rdata_o
,output [ 1:0] cfg_rresp_o
,output outport_awvalid_o
,output [ 31:0] outport_awaddr_o
,output [ 3:0] outport_awid_o
,output [ 7:0] outport_awlen_o
,output [ 1:0] outport_awburst_o
,output outport_wvalid_o
,output [ 31:0] outport_wdata_o
,output [ 3:0] outport_wstrb_o
,output outport_wlast_o
,output outport_bready_o
,output outport_arvalid_o
,output [ 31:0] outport_araddr_o
,output [ 3:0] outport_arid_o
,output [ 7:0] outport_arlen_o
,output [ 1:0] outport_arburst_o
,output outport_rready_o
,output cfg_clk_src_ext_o
,output [ 3:0] cfg_clk_div_o
,output [ 1:0] cfg_width_o
,output cfg_test_mode_o
,output status_enabled_o
,output status_triggered_o
,output status_overflow_o
);
//-----------------------------------------------------------------
// Core
//-----------------------------------------------------------------
wire fifo_tvalid_w;
wire [31:0] fifo_tdata_w;
wire fifo_tready_w;
wire [31:0] buffer_base_w;
wire [31:0] buffer_end_w;
wire buffer_reset_w;
wire [31:0] buffer_current_w;
wire buffer_cont_w;
wire buffer_wrapped_w;
wire buffer_full_w;
logic_capture
u_core
(
.clk_i(clk_i)
,.rst_i(rst_i)
// Config
,.cfg_awvalid_i(cfg_awvalid_i)
,.cfg_awaddr_i(cfg_awaddr_i)
,.cfg_wvalid_i(cfg_wvalid_i)
,.cfg_wdata_i(cfg_wdata_i)
,.cfg_wstrb_i(cfg_wstrb_i)
,.cfg_bready_i(cfg_bready_i)
,.cfg_arvalid_i(cfg_arvalid_i)
,.cfg_araddr_i(cfg_araddr_i)
,.cfg_rready_i(cfg_rready_i)
,.cfg_awready_o(cfg_awready_o)
,.cfg_wready_o(cfg_wready_o)
,.cfg_bvalid_o(cfg_bvalid_o)
,.cfg_bresp_o(cfg_bresp_o)
,.cfg_arready_o(cfg_arready_o)
,.cfg_rvalid_o(cfg_rvalid_o)
,.cfg_rdata_o(cfg_rdata_o)
,.cfg_rresp_o(cfg_rresp_o)
// Input capture
,.input_valid_i(input_valid_i)
,.input_data_i(input_data_i)
// Stream
,.outport_tvalid_o(fifo_tvalid_w)
,.outport_tdata_o(fifo_tdata_w)
,.outport_tstrb_o()
,.outport_tdest_o()
,.outport_tlast_o()
,.outport_tready_i(fifo_tready_w)
// Buffer Config
,.buffer_base_o(buffer_base_w)
,.buffer_end_o(buffer_end_w)
,.buffer_reset_o(buffer_reset_w)
,.buffer_cont_o(buffer_cont_w)
,.buffer_current_i(buffer_current_w)
,.buffer_wrapped_i(buffer_wrapped_w)
// Misc
,.cfg_clk_src_ext_o(cfg_clk_src_ext_o)
,.cfg_clk_div_o(cfg_clk_div_o)
,.cfg_width_o(cfg_width_o)
,.cfg_test_mode_o(cfg_test_mode_o)
// Status
,.status_enabled_o(status_enabled_o)
,.status_triggered_o(status_triggered_o)
,.status_overflow_o(status_overflow_o)
);
//-----------------------------------------------------------------
// Large block RAM based buffer
//-----------------------------------------------------------------
wire stream_tvalid_int_w;
wire stream_tvalid_w;
wire [31:0] stream_tdata_w;
wire stream_tready_w;
wire stream_tready_int_w;
wire fifo_space_w;
reg [31:0] stream_count_q;
logic_capture_mem_fifo_ram
u_buffer
(
.clk_i(clk_i)
,.rst_i(rst_i)
,.push_i(fifo_tvalid_w)
,.data_in_i(fifo_tdata_w)
,.accept_o(fifo_tready_w)
,.valid_o(stream_tvalid_int_w)
,.data_out_o(stream_tdata_w)
,.pop_i(stream_tready_int_w)
);
// Delay output to allow a bursts worth of data to accumulate
reg [3:0] stream_delay_q;
always @ (posedge clk_i )
if (rst_i)
stream_delay_q <= 4'b0;
else if (stream_delay_q != 4'd0)
stream_delay_q <= stream_delay_q - 4'd1;
else if (!stream_tvalid_int_w) // Empty
stream_delay_q <= 4'd15;
assign stream_tvalid_w = stream_tvalid_int_w && (stream_delay_q == 4'd0) && fifo_space_w;
assign stream_tready_int_w = stream_tready_w && (stream_delay_q == 4'd0) && fifo_space_w;
always @ (posedge clk_i )
if (rst_i)
stream_count_q <= 32'b0;
else if ((fifo_tvalid_w && fifo_tready_w) && !(stream_tvalid_int_w && stream_tready_int_w))
stream_count_q <= stream_count_q + 32'd1;
else if (!(fifo_tvalid_w && fifo_tready_w) && (stream_tvalid_int_w && stream_tready_int_w))
stream_count_q <= stream_count_q - 32'd1;
//-----------------------------------------------------------------
// AXI: Write logic
//-----------------------------------------------------------------
reg [31:0] write_addr_q;
wire mem_ack_w;
wire mem_was_burst_w;
reg [7:0] in_burst_q;
wire [7:0] inport_len_w;
wire [31:0] wrap_remain_w = buffer_end_w - write_addr_q;
wire can_burst_w = (write_addr_q[4:0] == 5'd0) && (stream_count_q >= 32'd8) && (wrap_remain_w > 32'd32);
always @ (posedge clk_i )
if (rst_i)
in_burst_q <= 8'b0;
else if (stream_tvalid_w && !buffer_full_w && stream_tready_w && in_burst_q != 8'd0)
in_burst_q <= in_burst_q - 8'd1;
else if (stream_tvalid_w && !buffer_full_w && stream_tready_w)
in_burst_q <= (inport_len_w != 8'd0) ? inport_len_w : 8'd0;
assign inport_len_w = (|in_burst_q) ? 8'd0 :
(can_burst_w) ? 8'd7 : 8'd0;
logic_capture_mem_track_fifo
#(
.WIDTH(1)
,.DEPTH(32)
,.ADDR_W(5)
)
u_fifo_burst_track
(
.clk_i(clk_i)
,.rst_i(rst_i)
,.push_i(stream_tvalid_w && !buffer_full_w && stream_tready_w && in_burst_q == 8'd0)
,.data_in_i(|inport_len_w)
,.accept_o(fifo_space_w)
,.valid_o()
,.data_out_o(mem_was_burst_w)
,.pop_i(mem_ack_w)
);
logic_capture_mem_axi
u_axi
(
.clk_i(clk_i)
,.rst_i(rst_i)
,.outport_awready_i(outport_awready_i)
,.outport_wready_i(outport_wready_i)
,.outport_bvalid_i(outport_bvalid_i)
,.outport_bresp_i(outport_bresp_i)
,.outport_arready_i(outport_arready_i)
,.outport_rvalid_i(outport_rvalid_i)
,.outport_rdata_i(outport_rdata_i)
,.outport_rresp_i(outport_rresp_i)
,.outport_awvalid_o(outport_awvalid_o)
,.outport_awaddr_o(outport_awaddr_o)
,.outport_wvalid_o(outport_wvalid_o)
,.outport_wdata_o(outport_wdata_o)
,.outport_wstrb_o(outport_wstrb_o)
,.outport_bready_o(outport_bready_o)
,.outport_arvalid_o(outport_arvalid_o)
,.outport_araddr_o(outport_araddr_o)
,.outport_rready_o(outport_rready_o)
,.outport_awid_o(outport_awid_o)
,.outport_awlen_o(outport_awlen_o)
,.outport_awburst_o(outport_awburst_o)
,.outport_wlast_o(outport_wlast_o)
,.outport_arid_o(outport_arid_o)
,.outport_arlen_o(outport_arlen_o)
,.outport_arburst_o(outport_arburst_o)
,.outport_bid_i(outport_bid_i)
,.outport_rid_i(outport_rid_i)
,.outport_rlast_i(outport_rlast_i)
,.inport_wr_i({4{stream_tvalid_w & ~buffer_full_w}})
,.inport_rd_i(1'b0)
,.inport_len_i(inport_len_w)
,.inport_addr_i(write_addr_q)
,.inport_write_data_i(stream_tdata_w)
,.inport_accept_o(stream_tready_w)
,.inport_ack_o(mem_ack_w)
,.inport_error_o()
,.inport_read_data_o()
);
//-----------------------------------------------------------------
// Buffer Full
//-----------------------------------------------------------------
reg buffer_full_q;
always @ (posedge clk_i )
if (rst_i)
buffer_full_q <= 1'b0;
else if (buffer_reset_w)
buffer_full_q <= 1'b0;
else if (stream_tvalid_w && stream_tready_w && !buffer_cont_w && (write_addr_q == buffer_end_w))
buffer_full_q <= 1'b1;
assign buffer_full_w = buffer_full_q;
//-----------------------------------------------------------------
// Buffer Wrapped
//-----------------------------------------------------------------
reg buffer_wrap_q;
always @ (posedge clk_i )
if (rst_i)
buffer_wrap_q <= 1'b0;
else if (buffer_reset_w)
buffer_wrap_q <= 1'b0;
else if (stream_tvalid_w && stream_tready_w && buffer_cont_w && (write_addr_q == buffer_end_w))
buffer_wrap_q <= 1'b1;
assign buffer_wrapped_w = buffer_wrap_q;
//-----------------------------------------------------------------
// Write Address
//-----------------------------------------------------------------
always @ (posedge clk_i )
if (rst_i)
write_addr_q <= 32'b0;
else if (buffer_reset_w)
write_addr_q <= buffer_base_w;
else if (stream_tvalid_w && stream_tready_w && !buffer_full_w)
begin
if (write_addr_q == buffer_end_w)
write_addr_q <= buffer_base_w;
else
write_addr_q <= write_addr_q + 32'd4;
end
//-----------------------------------------------------------------
// Read pointer (based on completed writes)
//-----------------------------------------------------------------
reg [31:0] buffer_current_q;
always @ (posedge clk_i )
if (rst_i)
buffer_current_q <= 32'b0;
else if (buffer_reset_w)
buffer_current_q <= buffer_base_w;
// Control word writes actually occur in IDLE...
else if (mem_ack_w && (buffer_cont_w || buffer_current_q != buffer_end_w))
begin
if (buffer_current_q == buffer_end_w)
buffer_current_q <= buffer_base_w;
else
buffer_current_q <= buffer_current_q + (mem_was_burst_w ? 32'd32 : 32'd4);
end
assign buffer_current_w = buffer_current_q;
endmodule |
module capture_rle_cdc
(
// Inputs
input rd_clk_i
,input rd_rst_i
,input rd_pop_i
,input wr_clk_i
,input wr_rst_i
,input [ 31:0] wr_data_i
,input wr_push_i
// Outputs
,output [ 31:0] rd_data_o
,output rd_empty_o
,output wr_full_o
);
//-----------------------------------------------------------------
// Registers
//-----------------------------------------------------------------
reg [4:0] rd_ptr_q;
reg [4:0] wr_ptr_q;
//-----------------------------------------------------------------
// Write
//-----------------------------------------------------------------
wire [4:0] wr_ptr_next_w = wr_ptr_q + 5'd1;
always @ (posedge wr_clk_i or posedge wr_rst_i)
if (wr_rst_i)
wr_ptr_q <= 5'b0;
else if (wr_push_i & ~wr_full_o)
wr_ptr_q <= wr_ptr_next_w;
wire [4:0] wr_rd_ptr_w;
capture_rle_cdc_resync_bus
#( .WIDTH(5))
u_resync_rd_ptr_q
(
.wr_clk_i(rd_clk_i),
.wr_rst_i(rd_rst_i),
.wr_i(1'b1),
.wr_data_i(rd_ptr_q),
.wr_busy_o(),
.rd_clk_i(wr_clk_i),
.rd_rst_i(wr_rst_i),
.rd_data_o(wr_rd_ptr_w) // Delayed version of rd_ptr_q
);
assign wr_full_o = (wr_ptr_next_w == wr_rd_ptr_w);
//-------------------------------------------------------------------
// Dual port RAM
//-------------------------------------------------------------------
wire [31:0] rd_data_w;
capture_rle_cdc_ram_dp_32_5
u_ram
(
// Inputs
.clk0_i(wr_clk_i),
.rst0_i(wr_rst_i),
.clk1_i(rd_clk_i),
.rst1_i(rd_rst_i),
// Write side
.addr0_i(wr_ptr_q),
.wr0_i(wr_push_i & ~wr_full_o),
.data0_i(wr_data_i),
.data0_o(),
// Read side
.addr1_i(rd_ptr_q),
.data1_i(32'b0),
.wr1_i(1'b0),
.data1_o(rd_data_w)
);
//-----------------------------------------------------------------
// Read
//-----------------------------------------------------------------
wire [4:0] rd_wr_ptr_w;
capture_rle_cdc_resync_bus
#( .WIDTH(5))
u_resync_wr_ptr_q
(
.wr_clk_i(wr_clk_i),
.wr_rst_i(wr_rst_i),
.wr_i(1'b1),
.wr_data_i(wr_ptr_q),
.wr_busy_o(),
.rd_clk_i(rd_clk_i),
.rd_rst_i(rd_rst_i),
.rd_data_o(rd_wr_ptr_w) // Delayed version of wr_ptr_q
);
//-------------------------------------------------------------------
// Read Skid Buffer
//-------------------------------------------------------------------
reg rd_skid_q;
reg [31:0] rd_skid_data_q;
reg rd_q;
wire read_ok_w = (rd_wr_ptr_w != rd_ptr_q);
wire valid_w = (rd_skid_q | rd_q);
always @ (posedge rd_clk_i or posedge rd_rst_i)
if (rd_rst_i)
begin
rd_skid_q <= 1'b0;
rd_skid_data_q <= 32'b0;
end
else if (valid_w && !rd_pop_i)
begin
rd_skid_q <= 1'b1;
rd_skid_data_q <= rd_data_o;
end
else
begin
rd_skid_q <= 1'b0;
rd_skid_data_q <= 32'b0;
end
assign rd_data_o = rd_skid_q ? rd_skid_data_q : rd_data_w;
//-----------------------------------------------------------------
// Read Pointer
//-----------------------------------------------------------------
always @ (posedge rd_clk_i or posedge rd_rst_i)
if (rd_rst_i)
rd_q <= 1'b0;
else
rd_q <= read_ok_w;
wire [4:0] rd_ptr_next_w = rd_ptr_q + 5'd1;
always @ (posedge rd_clk_i or posedge rd_rst_i)
if (rd_rst_i)
rd_ptr_q <= 5'b0;
// Read address increment
else if (read_ok_w && ((!valid_w) || (valid_w && rd_pop_i)))
rd_ptr_q <= rd_ptr_next_w;
assign rd_empty_o = !valid_w;
endmodule |
module capture_rle_cdc_ram_dp_32_5
(
// Inputs
input clk0_i
,input rst0_i
,input [ 4:0] addr0_i
,input [ 31:0] data0_i
,input wr0_i
,input clk1_i
,input rst1_i
,input [ 4:0] addr1_i
,input [ 31:0] data1_i
,input wr1_i
// Outputs
,output [ 31:0] data0_o
,output [ 31:0] data1_o
);
/* verilator lint_off MULTIDRIVEN */
reg [31:0] ram [31:0] /*verilator public*/;
/* verilator lint_on MULTIDRIVEN */
reg [31:0] ram_read0_q;
reg [31:0] ram_read1_q;
// Synchronous write
always @ (posedge clk0_i)
begin
if (wr0_i)
ram[addr0_i] <= data0_i;
ram_read0_q <= ram[addr0_i];
end
always @ (posedge clk1_i)
begin
if (wr1_i)
ram[addr1_i] <= data1_i;
ram_read1_q <= ram[addr1_i];
end
assign data0_o = ram_read0_q;
assign data1_o = ram_read1_q;
endmodule |
module capture_rle_cdc_resync_bus
//-----------------------------------------------------------------
// Params
//-----------------------------------------------------------------
#(
parameter WIDTH = 4
)
//-----------------------------------------------------------------
// Ports
//-----------------------------------------------------------------
(
input wr_clk_i,
input wr_rst_i,
input wr_i,
input [WIDTH-1:0] wr_data_i,
output wr_busy_o,
input rd_clk_i,
input rd_rst_i,
output [WIDTH-1:0] rd_data_o
);
wire rd_toggle_w;
wire wr_toggle_w;
//-----------------------------------------------------------------
// Write
//-----------------------------------------------------------------
wire write_req_w = wr_i && !wr_busy_o;
// Write storage for domain crossing
(* ASYNC_REG = "TRUE" *) reg [WIDTH-1:0] wr_buffer_q;
always @ (posedge wr_clk_i or posedge wr_rst_i)
if (wr_rst_i)
wr_buffer_q <= {(WIDTH){1'b0}};
else if (write_req_w)
wr_buffer_q <= wr_data_i;
reg wr_toggle_q;
always @ (posedge wr_clk_i or posedge wr_rst_i)
if (wr_rst_i)
wr_toggle_q <= 1'b0;
else if (write_req_w)
wr_toggle_q <= ~wr_toggle_q;
reg wr_busy_q;
always @ (posedge wr_clk_i or posedge wr_rst_i)
if (wr_rst_i)
wr_busy_q <= 1'b0;
else if (write_req_w)
wr_busy_q <= 1'b1;
else if (wr_toggle_q == wr_toggle_w)
wr_busy_q <= 1'b0;
assign wr_busy_o = wr_busy_q;
//-----------------------------------------------------------------
// Write -> Read request
//-----------------------------------------------------------------
capture_rle_cdc_resync
u_sync_wr_toggle
(
.clk_i(rd_clk_i),
.rst_i(rd_rst_i),
.async_i(wr_toggle_q),
.sync_o(rd_toggle_w)
);
//-----------------------------------------------------------------
// Read
//-----------------------------------------------------------------
reg rd_toggle_q;
always @ (posedge rd_clk_i or posedge rd_rst_i)
if (rd_rst_i)
rd_toggle_q <= 1'b0;
else
rd_toggle_q <= rd_toggle_w;
// Read storage for domain crossing
(* ASYNC_REG = "TRUE" *) reg [WIDTH-1:0] rd_buffer_q;
always @ (posedge rd_clk_i or posedge rd_rst_i)
if (rd_rst_i)
rd_buffer_q <= {(WIDTH){1'b0}};
else if (rd_toggle_q != rd_toggle_w)
rd_buffer_q <= wr_buffer_q; // Capture from other domain
assign rd_data_o = rd_buffer_q;
//-----------------------------------------------------------------
// Read->Write response
//-----------------------------------------------------------------
capture_rle_cdc_resync
u_sync_rd_toggle
(
.clk_i(wr_clk_i),
.rst_i(wr_rst_i),
.async_i(rd_toggle_q),
.sync_o(wr_toggle_w)
);
endmodule |
module capture_rle_cdc_resync
//-----------------------------------------------------------------
// Params
//-----------------------------------------------------------------
#(
parameter RESET_VAL = 1'b0
)
//-----------------------------------------------------------------
// Ports
//-----------------------------------------------------------------
(
input clk_i,
input rst_i,
input async_i,
output sync_o
);
(* ASYNC_REG = "TRUE" *) reg sync_ms;
(* ASYNC_REG = "TRUE" *) reg sync_q;
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
begin
sync_ms <= RESET_VAL;
sync_q <= RESET_VAL;
end
else
begin
sync_ms <= async_i;
sync_q <= sync_ms;
end
assign sync_o = sync_q;
endmodule |
module logic_capture_mem_axi
//-----------------------------------------------------------------
// Params
//-----------------------------------------------------------------
#(
parameter AXI_ID = 0
)
//-----------------------------------------------------------------
// Ports
//-----------------------------------------------------------------
(
// Inputs
input clk_i
,input rst_i
,input outport_awready_i
,input outport_wready_i
,input outport_bvalid_i
,input [ 1:0] outport_bresp_i
,input [ 3:0] outport_bid_i
,input outport_arready_i
,input outport_rvalid_i
,input [ 31:0] outport_rdata_i
,input [ 1:0] outport_rresp_i
,input [ 3:0] outport_rid_i
,input outport_rlast_i
,input [ 3:0] inport_wr_i
,input inport_rd_i
,input [ 7:0] inport_len_i
,input [ 31:0] inport_addr_i
,input [ 31:0] inport_write_data_i
// Outputs
,output outport_awvalid_o
,output [ 31:0] outport_awaddr_o
,output [ 3:0] outport_awid_o
,output [ 7:0] outport_awlen_o
,output [ 1:0] outport_awburst_o
,output outport_wvalid_o
,output [ 31:0] outport_wdata_o
,output [ 3:0] outport_wstrb_o
,output outport_wlast_o
,output outport_bready_o
,output outport_arvalid_o
,output [ 31:0] outport_araddr_o
,output [ 3:0] outport_arid_o
,output [ 7:0] outport_arlen_o
,output [ 1:0] outport_arburst_o
,output outport_rready_o
,output inport_accept_o
,output inport_ack_o
,output inport_error_o
,output [ 31:0] inport_read_data_o
);
//-------------------------------------------------------------
// Request FIFO
//-------------------------------------------------------------
wire bvalid_w;
wire rvalid_w;
wire [1:0] bresp_w;
wire [1:0] rresp_w;
wire accept_w;
// Accepts from both FIFOs
wire res_accept_w;
wire req_accept_w;
wire res_valid_w;
wire req_valid_w;
wire [77-1:0] req_w;
// Push on transaction and other FIFO not full
wire req_push_w = (inport_rd_i || inport_wr_i != 4'b0);
wire [77-1:0] req_data_in_w = {inport_len_i, inport_rd_i, inport_wr_i, inport_write_data_i, inport_addr_i};
logic_capture_mem_axi_fifo
#(
.ADDR_W(3),
.DEPTH(8),
.WIDTH(32+32+8+4+1)
)
u_req
(
.clk_i(clk_i),
.rst_i(rst_i),
// Input side
.data_in_i(req_data_in_w),
.push_i(req_push_w),
.accept_o(req_accept_w),
// Outputs
.valid_o(req_valid_w),
.data_out_o(req_w),
.pop_i(accept_w)
);
wire req_can_issue_w = req_valid_w & res_accept_w;
wire req_is_read_w = (req_can_issue_w ? req_w[68] : 1'b0);
wire req_is_write_w = (req_can_issue_w ? ~req_w[68] : 1'b0);
wire [7:0] req_len_w = req_w[76:69];
assign inport_accept_o = req_accept_w;
assign inport_ack_o = bvalid_w || rvalid_w;
assign inport_error_o = bvalid_w ? (bresp_w != 2'b0) : (rresp_w != 2'b0);
//-------------------------------------------------------------
// Write burst tracking
//-------------------------------------------------------------
reg [7:0] req_cnt_q;
always @ (posedge clk_i )
if (rst_i)
req_cnt_q <= 8'b0;
// First cycle of write burst
else if (req_is_write_w && req_cnt_q == 8'd0 && req_len_w != 8'd0 && accept_w)
req_cnt_q <= req_len_w - 8'd1;
else if (req_cnt_q != 8'd0 && req_is_write_w && accept_w)
req_cnt_q <= req_cnt_q - 8'd1;
wire req_last_w = (req_is_write_w && req_len_w == 8'd0 && req_cnt_q == 8'd0);
//-------------------------------------------------------------
// Response tracking
//-------------------------------------------------------------
// Push on transaction and other FIFO not full
wire res_push_w = (req_is_write_w && req_last_w && accept_w) || (req_is_read_w && accept_w);
// Pop on last tick of burst
wire resp_pop_w = outport_bvalid_i || (outport_rvalid_i ? outport_rlast_i : 1'b0);
reg [4:0] resp_outstanding_q;
always @ (posedge clk_i )
if (rst_i)
resp_outstanding_q <= 5'b0;
// Count up
else if ((res_push_w & res_accept_w) & ~(resp_pop_w & res_valid_w))
resp_outstanding_q <= resp_outstanding_q + 5'd1;
// Count down
else if (~(res_push_w & res_accept_w) & (resp_pop_w & res_valid_w))
resp_outstanding_q <= resp_outstanding_q - 5'd1;
assign res_valid_w = (resp_outstanding_q != 5'd0);
assign res_accept_w = (resp_outstanding_q != 5'd16);
//-------------------------------------------------------------
// AXI widget
//-------------------------------------------------------------
logic_capture_mem_axi_axi
u_axi
(
.clk_i(clk_i),
.rst_i(rst_i),
.inport_valid_i(req_can_issue_w),
.inport_write_i(req_is_write_w),
.inport_wdata_i(req_w[63:32]),
.inport_wstrb_i(req_w[67:64]),
.inport_addr_i({req_w[31:2], 2'b0}),
.inport_id_i(AXI_ID),
.inport_len_i(req_len_w),
.inport_burst_i(2'b01),
.inport_accept_o(accept_w),
.inport_bready_i(1'b1),
.inport_rready_i(1'b1),
.inport_bvalid_o(bvalid_w),
.inport_bresp_o(bresp_w),
.inport_bid_o(),
.inport_rvalid_o(rvalid_w),
.inport_rdata_o(inport_read_data_o),
.inport_rresp_o(rresp_w),
.inport_rid_o(),
.inport_rlast_o(),
.outport_awvalid_o(outport_awvalid_o),
.outport_awaddr_o(outport_awaddr_o),
.outport_awid_o(outport_awid_o),
.outport_awlen_o(outport_awlen_o),
.outport_awburst_o(outport_awburst_o),
.outport_wvalid_o(outport_wvalid_o),
.outport_wdata_o(outport_wdata_o),
.outport_wstrb_o(outport_wstrb_o),
.outport_wlast_o(outport_wlast_o),
.outport_bready_o(outport_bready_o),
.outport_arvalid_o(outport_arvalid_o),
.outport_araddr_o(outport_araddr_o),
.outport_arid_o(outport_arid_o),
.outport_arlen_o(outport_arlen_o),
.outport_arburst_o(outport_arburst_o),
.outport_rready_o(outport_rready_o),
.outport_awready_i(outport_awready_i),
.outport_wready_i(outport_wready_i),
.outport_bvalid_i(outport_bvalid_i),
.outport_bresp_i(outport_bresp_i),
.outport_bid_i(outport_bid_i),
.outport_arready_i(outport_arready_i),
.outport_rvalid_i(outport_rvalid_i),
.outport_rdata_i(outport_rdata_i),
.outport_rresp_i(outport_rresp_i),
.outport_rid_i(outport_rid_i),
.outport_rlast_i(outport_rlast_i)
);
endmodule |
module logic_capture_mem_axi_fifo
//-----------------------------------------------------------------
// Params
//-----------------------------------------------------------------
#(
parameter WIDTH = 8,
parameter DEPTH = 4,
parameter ADDR_W = 2
)
//-----------------------------------------------------------------
// Ports
//-----------------------------------------------------------------
(
// Inputs
input clk_i
,input rst_i
,input [WIDTH-1:0] data_in_i
,input push_i
,input pop_i
// Outputs
,output [WIDTH-1:0] data_out_o
,output accept_o
,output valid_o
);
//-----------------------------------------------------------------
// Local Params
//-----------------------------------------------------------------
localparam COUNT_W = ADDR_W + 1;
//-----------------------------------------------------------------
// Registers
//-----------------------------------------------------------------
reg [WIDTH-1:0] ram_q[DEPTH-1:0];
reg [ADDR_W-1:0] rd_ptr_q;
reg [ADDR_W-1:0] wr_ptr_q;
reg [COUNT_W-1:0] count_q;
//-----------------------------------------------------------------
// Sequential
//-----------------------------------------------------------------
always @ (posedge clk_i )
if (rst_i)
begin
count_q <= {(COUNT_W) {1'b0}};
rd_ptr_q <= {(ADDR_W) {1'b0}};
wr_ptr_q <= {(ADDR_W) {1'b0}};
end
else
begin
// Push
if (push_i & accept_o)
begin
ram_q[wr_ptr_q] <= data_in_i;
wr_ptr_q <= wr_ptr_q + 1;
end
// Pop
if (pop_i & valid_o)
rd_ptr_q <= rd_ptr_q + 1;
// Count up
if ((push_i & accept_o) & ~(pop_i & valid_o))
count_q <= count_q + 1;
// Count down
else if (~(push_i & accept_o) & (pop_i & valid_o))
count_q <= count_q - 1;
end
//-------------------------------------------------------------------
// Combinatorial
//-------------------------------------------------------------------
/* verilator lint_off WIDTH */
assign valid_o = (count_q != 0);
assign accept_o = (count_q != DEPTH);
/* verilator lint_on WIDTH */
assign data_out_o = ram_q[rd_ptr_q];
endmodule |
module logic_capture_mem_track_fifo
//-----------------------------------------------------------------
// Params
//-----------------------------------------------------------------
#(
parameter WIDTH = 8,
parameter DEPTH = 4,
parameter ADDR_W = 2
)
//-----------------------------------------------------------------
// Ports
//-----------------------------------------------------------------
(
// Inputs
input clk_i
,input rst_i
,input [WIDTH-1:0] data_in_i
,input push_i
,input pop_i
// Outputs
,output [WIDTH-1:0] data_out_o
,output accept_o
,output valid_o
);
//-----------------------------------------------------------------
// Local Params
//-----------------------------------------------------------------
localparam COUNT_W = ADDR_W + 1;
//-----------------------------------------------------------------
// Registers
//-----------------------------------------------------------------
reg [WIDTH-1:0] ram_q[DEPTH-1:0];
reg [ADDR_W-1:0] rd_ptr_q;
reg [ADDR_W-1:0] wr_ptr_q;
reg [COUNT_W-1:0] count_q;
//-----------------------------------------------------------------
// Sequential
//-----------------------------------------------------------------
always @ (posedge clk_i )
if (rst_i)
begin
count_q <= {(COUNT_W) {1'b0}};
rd_ptr_q <= {(ADDR_W) {1'b0}};
wr_ptr_q <= {(ADDR_W) {1'b0}};
end
else
begin
// Push
if (push_i & accept_o)
begin
ram_q[wr_ptr_q] <= data_in_i;
wr_ptr_q <= wr_ptr_q + 1;
end
// Pop
if (pop_i & valid_o)
rd_ptr_q <= rd_ptr_q + 1;
// Count up
if ((push_i & accept_o) & ~(pop_i & valid_o))
count_q <= count_q + 1;
// Count down
else if (~(push_i & accept_o) & (pop_i & valid_o))
count_q <= count_q - 1;
end
//-------------------------------------------------------------------
// Combinatorial
//-------------------------------------------------------------------
/* verilator lint_off WIDTH */
assign valid_o = (count_q != 0);
assign accept_o = (count_q != DEPTH);
/* verilator lint_on WIDTH */
assign data_out_o = ram_q[rd_ptr_q];
endmodule |
module logic_capture_fifo
(
// Inputs
input clk_i
,input rst_i
,input [ 31:0] data_in_i
,input push_i
,input pop_i
// Outputs
,output [ 31:0] data_out_o
,output accept_o
,output valid_o
);
//-----------------------------------------------------------------
// Registers
//-----------------------------------------------------------------
reg [8:0] rd_ptr_q;
reg [8:0] wr_ptr_q;
//-----------------------------------------------------------------
// Write Side
//-----------------------------------------------------------------
wire [8:0] write_next_w = wr_ptr_q + 9'd1;
wire full_w = (write_next_w == rd_ptr_q);
always @ (posedge clk_i )
if (rst_i)
wr_ptr_q <= 9'b0;
// Push
else if (push_i & !full_w)
wr_ptr_q <= write_next_w;
//-----------------------------------------------------------------
// Read Side
//-----------------------------------------------------------------
wire read_ok_w = (wr_ptr_q != rd_ptr_q);
reg rd_q;
always @ (posedge clk_i )
if (rst_i)
rd_q <= 1'b0;
else
rd_q <= read_ok_w;
always @ (posedge clk_i )
if (rst_i)
rd_ptr_q <= 9'b0;
// Read address increment
else if (read_ok_w && ((!valid_o) || (valid_o && pop_i)))
rd_ptr_q <= rd_ptr_q + 9'd1;
//-------------------------------------------------------------------
// Read Skid Buffer
//-------------------------------------------------------------------
reg rd_skid_q;
reg [31:0] rd_skid_data_q;
always @ (posedge clk_i )
if (rst_i)
begin
rd_skid_q <= 1'b0;
rd_skid_data_q <= 32'b0;
end
else if (valid_o && !pop_i)
begin
rd_skid_q <= 1'b1;
rd_skid_data_q <= data_out_o;
end
else
begin
rd_skid_q <= 1'b0;
rd_skid_data_q <= 32'b0;
end
//-------------------------------------------------------------------
// Combinatorial
//-------------------------------------------------------------------
assign valid_o = rd_skid_q | rd_q;
assign accept_o = !full_w;
//-------------------------------------------------------------------
// Dual port RAM
//-------------------------------------------------------------------
wire [31:0] data_out_w;
logic_capture_fifo_dp_512_9
u_ram
(
// Inputs
.clk0_i(clk_i),
.rst0_i(rst_i),
.clk1_i(clk_i),
.rst1_i(rst_i),
// Write side
.addr0_i(wr_ptr_q),
.wr0_i(push_i & accept_o),
.data0_i(data_in_i),
.data0_o(),
// Read side
.addr1_i(rd_ptr_q),
.data1_i(32'b0),
.wr1_i(1'b0),
.data1_o(data_out_w)
);
assign data_out_o = rd_skid_q ? rd_skid_data_q : data_out_w;
endmodule |
module logic_capture_fifo_dp_512_9
(
// Inputs
input clk0_i
,input rst0_i
,input [ 8:0] addr0_i
,input [ 31:0] data0_i
,input wr0_i
,input clk1_i
,input rst1_i
,input [ 8:0] addr1_i
,input [ 31:0] data1_i
,input wr1_i
// Outputs
,output [ 31:0] data0_o
,output [ 31:0] data1_o
);
/* verilator lint_off MULTIDRIVEN */
reg [31:0] ram [511:0] /*verilator public*/;
/* verilator lint_on MULTIDRIVEN */
reg [31:0] ram_read0_q;
reg [31:0] ram_read1_q;
// Synchronous write
always @ (posedge clk0_i)
begin
if (wr0_i)
ram[addr0_i] <= data0_i;
ram_read0_q <= ram[addr0_i];
end
always @ (posedge clk1_i)
begin
if (wr1_i)
ram[addr1_i] <= data1_i;
ram_read1_q <= ram[addr1_i];
end
assign data0_o = ram_read0_q;
assign data1_o = ram_read1_q;
endmodule |
module logic_capture_mem_fifo_ram
(
// Inputs
input clk_i
,input rst_i
,input [ 31:0] data_in_i
,input push_i
,input pop_i
// Outputs
,output [ 31:0] data_out_o
,output accept_o
,output valid_o
);
//-----------------------------------------------------------------
// Registers
//-----------------------------------------------------------------
reg [10:0] rd_ptr_q;
reg [10:0] wr_ptr_q;
//-----------------------------------------------------------------
// Write Side
//-----------------------------------------------------------------
wire [10:0] write_next_w = wr_ptr_q + 11'd1;
wire full_w = (write_next_w == rd_ptr_q);
always @ (posedge clk_i )
if (rst_i)
wr_ptr_q <= 11'b0;
// Push
else if (push_i & !full_w)
wr_ptr_q <= write_next_w;
//-----------------------------------------------------------------
// Read Side
//-----------------------------------------------------------------
wire read_ok_w = (wr_ptr_q != rd_ptr_q);
reg rd_q;
always @ (posedge clk_i )
if (rst_i)
rd_q <= 1'b0;
else
rd_q <= read_ok_w;
always @ (posedge clk_i )
if (rst_i)
rd_ptr_q <= 11'b0;
// Read address increment
else if (read_ok_w && ((!valid_o) || (valid_o && pop_i)))
rd_ptr_q <= rd_ptr_q + 11'd1;
//-------------------------------------------------------------------
// Read Skid Buffer
//-------------------------------------------------------------------
reg rd_skid_q;
reg [31:0] rd_skid_data_q;
always @ (posedge clk_i )
if (rst_i)
begin
rd_skid_q <= 1'b0;
rd_skid_data_q <= 32'b0;
end
else if (valid_o && !pop_i)
begin
rd_skid_q <= 1'b1;
rd_skid_data_q <= data_out_o;
end
else
begin
rd_skid_q <= 1'b0;
rd_skid_data_q <= 32'b0;
end
//-------------------------------------------------------------------
// Combinatorial
//-------------------------------------------------------------------
assign valid_o = rd_skid_q | rd_q;
assign accept_o = !full_w;
//-------------------------------------------------------------------
// Dual port RAM
//-------------------------------------------------------------------
wire [31:0] data_out_w;
logic_capture_mem_fifo_ram_ram_dp_16384_11
u_ram
(
// Inputs
.clk0_i(clk_i),
.rst0_i(rst_i),
.clk1_i(clk_i),
.rst1_i(rst_i),
// Write side
.addr0_i(wr_ptr_q),
.wr0_i(push_i & accept_o),
.data0_i(data_in_i),
.data0_o(),
// Read side
.addr1_i(rd_ptr_q),
.data1_i(32'b0),
.wr1_i(1'b0),
.data1_o(data_out_w)
);
assign data_out_o = rd_skid_q ? rd_skid_data_q : data_out_w;
//-------------------------------------------------------------------
// Level
//-------------------------------------------------------------------
endmodule |
module logic_capture_mem_fifo_ram_ram_dp_16384_11
(
// Inputs
input clk0_i
,input rst0_i
,input [ 10:0] addr0_i
,input [ 31:0] data0_i
,input wr0_i
,input clk1_i
,input rst1_i
,input [ 10:0] addr1_i
,input [ 31:0] data1_i
,input wr1_i
// Outputs
,output [ 31:0] data0_o
,output [ 31:0] data1_o
);
/* verilator lint_off MULTIDRIVEN */
reg [31:0] ram [2047:0] /*verilator public*/;
/* verilator lint_on MULTIDRIVEN */
reg [31:0] ram_read0_q;
reg [31:0] ram_read1_q;
// Synchronous write
always @ (posedge clk0_i)
begin
if (wr0_i)
ram[addr0_i] <= data0_i;
ram_read0_q <= ram[addr0_i];
end
always @ (posedge clk1_i)
begin
if (wr1_i)
ram[addr1_i] <= data1_i;
ram_read1_q <= ram[addr1_i];
end
assign data0_o = ram_read0_q;
assign data1_o = ram_read1_q;
endmodule |
module logic_capture
(
// Inputs
input clk_i
,input rst_i
,input cfg_awvalid_i
,input [31:0] cfg_awaddr_i
,input cfg_wvalid_i
,input [31:0] cfg_wdata_i
,input [3:0] cfg_wstrb_i
,input cfg_bready_i
,input cfg_arvalid_i
,input [31:0] cfg_araddr_i
,input cfg_rready_i
,input input_valid_i
,input [31:0] input_data_i
,input outport_tready_i
,input [31:0] buffer_current_i
,input buffer_wrapped_i
// Outputs
,output cfg_awready_o
,output cfg_wready_o
,output cfg_bvalid_o
,output [1:0] cfg_bresp_o
,output cfg_arready_o
,output cfg_rvalid_o
,output [31:0] cfg_rdata_o
,output [1:0] cfg_rresp_o
,output outport_tvalid_o
,output [31:0] outport_tdata_o
,output [3:0] outport_tstrb_o
,output [3:0] outport_tdest_o
,output outport_tlast_o
,output [31:0] buffer_base_o
,output [31:0] buffer_end_o
,output buffer_reset_o
,output buffer_cont_o
,output cfg_clk_src_ext_o
,output [3:0] cfg_clk_div_o
,output [1:0] cfg_width_o
,output cfg_test_mode_o
,output status_enabled_o
,output status_triggered_o
,output status_overflow_o
);
//-----------------------------------------------------------------
// Write address / data split
//-----------------------------------------------------------------
// Address but no data ready
reg awvalid_q;
// Data but no data ready
reg wvalid_q;
wire wr_cmd_accepted_w = (cfg_awvalid_i && cfg_awready_o) || awvalid_q;
wire wr_data_accepted_w = (cfg_wvalid_i && cfg_wready_o) || wvalid_q;
always @ (posedge clk_i )
if (rst_i)
awvalid_q <= 1'b0;
else if (cfg_awvalid_i && cfg_awready_o && !wr_data_accepted_w)
awvalid_q <= 1'b1;
else if (wr_data_accepted_w)
awvalid_q <= 1'b0;
always @ (posedge clk_i )
if (rst_i)
wvalid_q <= 1'b0;
else if (cfg_wvalid_i && cfg_wready_o && !wr_cmd_accepted_w)
wvalid_q <= 1'b1;
else if (wr_cmd_accepted_w)
wvalid_q <= 1'b0;
//-----------------------------------------------------------------
// Capture address (for delayed data)
//-----------------------------------------------------------------
reg [7:0] wr_addr_q;
always @ (posedge clk_i )
if (rst_i)
wr_addr_q <= 8'b0;
else if (cfg_awvalid_i && cfg_awready_o)
wr_addr_q <= cfg_awaddr_i[7:0];
wire [7:0] wr_addr_w = awvalid_q ? wr_addr_q : cfg_awaddr_i[7:0];
//-----------------------------------------------------------------
// Retime write data
//-----------------------------------------------------------------
reg [31:0] wr_data_q;
always @ (posedge clk_i )
if (rst_i)
wr_data_q <= 32'b0;
else if (cfg_wvalid_i && cfg_wready_o)
wr_data_q <= cfg_wdata_i;
//-----------------------------------------------------------------
// Request Logic
//-----------------------------------------------------------------
wire read_en_w = cfg_arvalid_i & cfg_arready_o;
wire write_en_w = wr_cmd_accepted_w && wr_data_accepted_w;
//-----------------------------------------------------------------
// Accept Logic
//-----------------------------------------------------------------
assign cfg_arready_o = ~cfg_rvalid_o;
assign cfg_awready_o = ~cfg_bvalid_o && ~cfg_arvalid_i && ~awvalid_q;
assign cfg_wready_o = ~cfg_bvalid_o && ~cfg_arvalid_i && ~wvalid_q;
//-----------------------------------------------------------------
// Register la_buffer_cfg
//-----------------------------------------------------------------
reg la_buffer_cfg_wr_q;
always @ (posedge clk_i )
if (rst_i)
la_buffer_cfg_wr_q <= 1'b0;
else if (write_en_w && (wr_addr_w[7:0] == `LA_BUFFER_CFG))
la_buffer_cfg_wr_q <= 1'b1;
else
la_buffer_cfg_wr_q <= 1'b0;
// la_buffer_cfg_cont [internal]
reg la_buffer_cfg_cont_q;
always @ (posedge clk_i )
if (rst_i)
la_buffer_cfg_cont_q <= 1'd`LA_BUFFER_CFG_CONT_DEFAULT;
else if (write_en_w && (wr_addr_w[7:0] == `LA_BUFFER_CFG))
la_buffer_cfg_cont_q <= cfg_wdata_i[`LA_BUFFER_CFG_CONT_R];
wire la_buffer_cfg_cont_out_w = la_buffer_cfg_cont_q;
// la_buffer_cfg_test_mode [internal]
reg la_buffer_cfg_test_mode_q;
always @ (posedge clk_i )
if (rst_i)
la_buffer_cfg_test_mode_q <= 1'd`LA_BUFFER_CFG_TEST_MODE_DEFAULT;
else if (write_en_w && (wr_addr_w[7:0] == `LA_BUFFER_CFG))
la_buffer_cfg_test_mode_q <= cfg_wdata_i[`LA_BUFFER_CFG_TEST_MODE_R];
wire la_buffer_cfg_test_mode_out_w = la_buffer_cfg_test_mode_q;
// la_buffer_cfg_width [internal]
reg [1:0] la_buffer_cfg_width_q;
always @ (posedge clk_i )
if (rst_i)
la_buffer_cfg_width_q <= 2'd`LA_BUFFER_CFG_WIDTH_DEFAULT;
else if (write_en_w && (wr_addr_w[7:0] == `LA_BUFFER_CFG))
la_buffer_cfg_width_q <= cfg_wdata_i[`LA_BUFFER_CFG_WIDTH_R];
wire [1:0] la_buffer_cfg_width_out_w = la_buffer_cfg_width_q;
// la_buffer_cfg_clk_div [internal]
reg [3:0] la_buffer_cfg_clk_div_q;
always @ (posedge clk_i )
if (rst_i)
la_buffer_cfg_clk_div_q <= 4'd`LA_BUFFER_CFG_CLK_DIV_DEFAULT;
else if (write_en_w && (wr_addr_w[7:0] == `LA_BUFFER_CFG))
la_buffer_cfg_clk_div_q <= cfg_wdata_i[`LA_BUFFER_CFG_CLK_DIV_R];
wire [3:0] la_buffer_cfg_clk_div_out_w = la_buffer_cfg_clk_div_q;
// la_buffer_cfg_clk_src [internal]
reg la_buffer_cfg_clk_src_q;
always @ (posedge clk_i )
if (rst_i)
la_buffer_cfg_clk_src_q <= 1'd`LA_BUFFER_CFG_CLK_SRC_DEFAULT;
else if (write_en_w && (wr_addr_w[7:0] == `LA_BUFFER_CFG))
la_buffer_cfg_clk_src_q <= cfg_wdata_i[`LA_BUFFER_CFG_CLK_SRC_R];
wire la_buffer_cfg_clk_src_out_w = la_buffer_cfg_clk_src_q;
// la_buffer_cfg_enabled [internal]
reg la_buffer_cfg_enabled_q;
always @ (posedge clk_i )
if (rst_i)
la_buffer_cfg_enabled_q <= 1'd`LA_BUFFER_CFG_ENABLED_DEFAULT;
else if (write_en_w && (wr_addr_w[7:0] == `LA_BUFFER_CFG))
la_buffer_cfg_enabled_q <= cfg_wdata_i[`LA_BUFFER_CFG_ENABLED_R];
wire la_buffer_cfg_enabled_out_w = la_buffer_cfg_enabled_q;
//-----------------------------------------------------------------
// Register la_buffer_sts
//-----------------------------------------------------------------
reg la_buffer_sts_wr_q;
always @ (posedge clk_i )
if (rst_i)
la_buffer_sts_wr_q <= 1'b0;
else if (write_en_w && (wr_addr_w[7:0] == `LA_BUFFER_STS))
la_buffer_sts_wr_q <= 1'b1;
else
la_buffer_sts_wr_q <= 1'b0;
//-----------------------------------------------------------------
// Register la_buffer_base
//-----------------------------------------------------------------
reg la_buffer_base_wr_q;
always @ (posedge clk_i )
if (rst_i)
la_buffer_base_wr_q <= 1'b0;
else if (write_en_w && (wr_addr_w[7:0] == `LA_BUFFER_BASE))
la_buffer_base_wr_q <= 1'b1;
else
la_buffer_base_wr_q <= 1'b0;
// la_buffer_base_addr [internal]
reg [31:0] la_buffer_base_addr_q;
always @ (posedge clk_i )
if (rst_i)
la_buffer_base_addr_q <= 32'd`LA_BUFFER_BASE_ADDR_DEFAULT;
else if (write_en_w && (wr_addr_w[7:0] == `LA_BUFFER_BASE))
la_buffer_base_addr_q <= cfg_wdata_i[`LA_BUFFER_BASE_ADDR_R];
wire [31:0] la_buffer_base_addr_out_w = la_buffer_base_addr_q;
//-----------------------------------------------------------------
// Register la_buffer_end
//-----------------------------------------------------------------
reg la_buffer_end_wr_q;
always @ (posedge clk_i )
if (rst_i)
la_buffer_end_wr_q <= 1'b0;
else if (write_en_w && (wr_addr_w[7:0] == `LA_BUFFER_END))
la_buffer_end_wr_q <= 1'b1;
else
la_buffer_end_wr_q <= 1'b0;
// la_buffer_end_addr [internal]
reg [31:0] la_buffer_end_addr_q;
always @ (posedge clk_i )
if (rst_i)
la_buffer_end_addr_q <= 32'd`LA_BUFFER_END_ADDR_DEFAULT;
else if (write_en_w && (wr_addr_w[7:0] == `LA_BUFFER_END))
la_buffer_end_addr_q <= cfg_wdata_i[`LA_BUFFER_END_ADDR_R];
wire [31:0] la_buffer_end_addr_out_w = la_buffer_end_addr_q;
//-----------------------------------------------------------------
// Register la_buffer_current
//-----------------------------------------------------------------
reg la_buffer_current_wr_q;
always @ (posedge clk_i )
if (rst_i)
la_buffer_current_wr_q <= 1'b0;
else if (write_en_w && (wr_addr_w[7:0] == `LA_BUFFER_CURRENT))
la_buffer_current_wr_q <= 1'b1;
else
la_buffer_current_wr_q <= 1'b0;
//-----------------------------------------------------------------
// Register la_buffer_samples
//-----------------------------------------------------------------
reg la_buffer_samples_wr_q;
always @ (posedge clk_i )
if (rst_i)
la_buffer_samples_wr_q <= 1'b0;
else if (write_en_w && (wr_addr_w[7:0] == `LA_BUFFER_SAMPLES))
la_buffer_samples_wr_q <= 1'b1;
else
la_buffer_samples_wr_q <= 1'b0;
//-----------------------------------------------------------------
// Register la_buffer_trig_enable
//-----------------------------------------------------------------
reg la_buffer_trig_enable_wr_q;
always @ (posedge clk_i )
if (rst_i)
la_buffer_trig_enable_wr_q <= 1'b0;
else if (write_en_w && (wr_addr_w[7:0] == `LA_BUFFER_TRIG_ENABLE))
la_buffer_trig_enable_wr_q <= 1'b1;
else
la_buffer_trig_enable_wr_q <= 1'b0;
// la_buffer_trig_enable_value [internal]
reg [31:0] la_buffer_trig_enable_value_q;
always @ (posedge clk_i )
if (rst_i)
la_buffer_trig_enable_value_q <= 32'd`LA_BUFFER_TRIG_ENABLE_VALUE_DEFAULT;
else if (write_en_w && (wr_addr_w[7:0] == `LA_BUFFER_TRIG_ENABLE))
la_buffer_trig_enable_value_q <= cfg_wdata_i[`LA_BUFFER_TRIG_ENABLE_VALUE_R];
wire [31:0] la_buffer_trig_enable_value_out_w = la_buffer_trig_enable_value_q;
//-----------------------------------------------------------------
// Register la_buffer_trig_sense
//-----------------------------------------------------------------
reg la_buffer_trig_sense_wr_q;
always @ (posedge clk_i )
if (rst_i)
la_buffer_trig_sense_wr_q <= 1'b0;
else if (write_en_w && (wr_addr_w[7:0] == `LA_BUFFER_TRIG_SENSE))
la_buffer_trig_sense_wr_q <= 1'b1;
else
la_buffer_trig_sense_wr_q <= 1'b0;
// la_buffer_trig_sense_value [internal]
reg [31:0] la_buffer_trig_sense_value_q;
always @ (posedge clk_i )
if (rst_i)
la_buffer_trig_sense_value_q <= 32'd`LA_BUFFER_TRIG_SENSE_VALUE_DEFAULT;
else if (write_en_w && (wr_addr_w[7:0] == `LA_BUFFER_TRIG_SENSE))
la_buffer_trig_sense_value_q <= cfg_wdata_i[`LA_BUFFER_TRIG_SENSE_VALUE_R];
wire [31:0] la_buffer_trig_sense_value_out_w = la_buffer_trig_sense_value_q;
//-----------------------------------------------------------------
// Register la_buffer_trig_level
//-----------------------------------------------------------------
reg la_buffer_trig_level_wr_q;
always @ (posedge clk_i )
if (rst_i)
la_buffer_trig_level_wr_q <= 1'b0;
else if (write_en_w && (wr_addr_w[7:0] == `LA_BUFFER_TRIG_LEVEL))
la_buffer_trig_level_wr_q <= 1'b1;
else
la_buffer_trig_level_wr_q <= 1'b0;
// la_buffer_trig_level_value [internal]
reg [31:0] la_buffer_trig_level_value_q;
always @ (posedge clk_i )
if (rst_i)
la_buffer_trig_level_value_q <= 32'd`LA_BUFFER_TRIG_LEVEL_VALUE_DEFAULT;
else if (write_en_w && (wr_addr_w[7:0] == `LA_BUFFER_TRIG_LEVEL))
la_buffer_trig_level_value_q <= cfg_wdata_i[`LA_BUFFER_TRIG_LEVEL_VALUE_R];
wire [31:0] la_buffer_trig_level_value_out_w = la_buffer_trig_level_value_q;
wire [5:0] la_buffer_sts_num_channels_in_w;
wire la_buffer_sts_data_loss_in_w;
wire la_buffer_sts_wrapped_in_w;
wire la_buffer_sts_trig_in_w;
wire [31:0] la_buffer_current_addr_in_w;
wire [31:0] la_buffer_samples_count_in_w;
//-----------------------------------------------------------------
// Read mux
//-----------------------------------------------------------------
reg [31:0] data_r;
always @ *
begin
data_r = 32'b0;
case (cfg_araddr_i[7:0])
`LA_BUFFER_CFG:
begin
data_r[`LA_BUFFER_CFG_CONT_R] = la_buffer_cfg_cont_q;
data_r[`LA_BUFFER_CFG_TEST_MODE_R] = la_buffer_cfg_test_mode_q;
data_r[`LA_BUFFER_CFG_WIDTH_R] = la_buffer_cfg_width_q;
data_r[`LA_BUFFER_CFG_CLK_DIV_R] = la_buffer_cfg_clk_div_q;
data_r[`LA_BUFFER_CFG_CLK_SRC_R] = la_buffer_cfg_clk_src_q;
data_r[`LA_BUFFER_CFG_ENABLED_R] = la_buffer_cfg_enabled_q;
end
`LA_BUFFER_STS:
begin
data_r[`LA_BUFFER_STS_NUM_CHANNELS_R] = la_buffer_sts_num_channels_in_w;
data_r[`LA_BUFFER_STS_DATA_LOSS_R] = la_buffer_sts_data_loss_in_w;
data_r[`LA_BUFFER_STS_WRAPPED_R] = la_buffer_sts_wrapped_in_w;
data_r[`LA_BUFFER_STS_TRIG_R] = la_buffer_sts_trig_in_w;
end
`LA_BUFFER_BASE:
begin
data_r[`LA_BUFFER_BASE_ADDR_R] = la_buffer_base_addr_q;
end
`LA_BUFFER_END:
begin
data_r[`LA_BUFFER_END_ADDR_R] = la_buffer_end_addr_q;
end
`LA_BUFFER_CURRENT:
begin
data_r[`LA_BUFFER_CURRENT_ADDR_R] = la_buffer_current_addr_in_w;
end
`LA_BUFFER_SAMPLES:
begin
data_r[`LA_BUFFER_SAMPLES_COUNT_R] = la_buffer_samples_count_in_w;
end
`LA_BUFFER_TRIG_ENABLE:
begin
data_r[`LA_BUFFER_TRIG_ENABLE_VALUE_R] = la_buffer_trig_enable_value_q;
end
`LA_BUFFER_TRIG_SENSE:
begin
data_r[`LA_BUFFER_TRIG_SENSE_VALUE_R] = la_buffer_trig_sense_value_q;
end
`LA_BUFFER_TRIG_LEVEL:
begin
data_r[`LA_BUFFER_TRIG_LEVEL_VALUE_R] = la_buffer_trig_level_value_q;
end
default :
data_r = 32'b0;
endcase
end
//-----------------------------------------------------------------
// RVALID
//-----------------------------------------------------------------
reg rvalid_q;
always @ (posedge clk_i )
if (rst_i)
rvalid_q <= 1'b0;
else if (read_en_w)
rvalid_q <= 1'b1;
else if (cfg_rready_i)
rvalid_q <= 1'b0;
assign cfg_rvalid_o = rvalid_q;
//-----------------------------------------------------------------
// Retime read response
//-----------------------------------------------------------------
reg [31:0] rd_data_q;
always @ (posedge clk_i )
if (rst_i)
rd_data_q <= 32'b0;
else if (!cfg_rvalid_o || cfg_rready_i)
rd_data_q <= data_r;
assign cfg_rdata_o = rd_data_q;
assign cfg_rresp_o = 2'b0;
//-----------------------------------------------------------------
// BVALID
//-----------------------------------------------------------------
reg bvalid_q;
always @ (posedge clk_i )
if (rst_i)
bvalid_q <= 1'b0;
else if (write_en_w)
bvalid_q <= 1'b1;
else if (cfg_bready_i)
bvalid_q <= 1'b0;
assign cfg_bvalid_o = bvalid_q;
assign cfg_bresp_o = 2'b0;
parameter NUM_CHANNELS = 16;
localparam WIDTH_16BIT = 2'd0;
localparam WIDTH_24BIT = 2'd1;
localparam WIDTH_32BIT = 2'd2;
//-----------------------------------------------------------------
// Enable detect
//-----------------------------------------------------------------
wire cfg_enabled_w = la_buffer_cfg_enabled_out_w;
reg cfg_enabled_q;
always @ (posedge clk_i )
if (rst_i)
cfg_enabled_q <= 1'b0;
else
cfg_enabled_q <= cfg_enabled_w;
wire cfg_enable_reset_w = !cfg_enabled_q & cfg_enabled_w;
//-----------------------------------------------------------------
// Triggering
//-----------------------------------------------------------------
reg [31:0] prev_q;
always @ (posedge clk_i )
if (rst_i)
prev_q <= 32'b0;
else if (!cfg_enabled_w)
prev_q <= la_buffer_trig_sense_value_out_w;
else if (input_valid_i)
prev_q <= input_data_i;
integer i;
reg [31:0] trig_r;
always @ *
begin
trig_r = 32'b0;
if (input_valid_i)
begin
for (i=0;i<32;i=i+1)
begin
// Level sensitive
if (la_buffer_trig_level_value_out_w[i])
begin
if (input_data_i[i] == la_buffer_trig_sense_value_out_w[i])
trig_r[i] = 1'b1;
end
// Edge sensitive (rising)
else if (la_buffer_trig_sense_value_out_w[i])
begin
if (input_data_i[i] && !prev_q[i])
trig_r[i] = 1'b1;
end
// Edge sensitive (falling)
else
begin
if (!input_data_i[i] && prev_q[i])
trig_r[i] = 1'b1;
end
end
end
// Combine with channel enable
trig_r = trig_r & la_buffer_trig_enable_value_out_w;
end
wire trigger_hit_w = (trig_r == la_buffer_trig_enable_value_out_w);
wire trigger_edge_any_w = |(la_buffer_trig_enable_value_out_w & ~la_buffer_trig_level_value_out_w);
reg triggered_q;
always @ (posedge clk_i )
if (rst_i)
triggered_q <= 1'b0;
else if (cfg_enable_reset_w)
triggered_q <= (la_buffer_trig_enable_value_out_w == 32'b0); // No triggers
else if (cfg_enabled_w && trigger_hit_w)
triggered_q <= 1'b1;
//-----------------------------------------------------------------
// Data delay
//-----------------------------------------------------------------
reg [31:0] buffer_q;
reg buffer_wr_q;
always @ (posedge clk_i )
if (rst_i)
buffer_q <= 32'b0;
else
buffer_q <= input_data_i;
always @ (posedge clk_i )
if (rst_i)
buffer_wr_q <= 1'b0;
else
buffer_wr_q <= input_valid_i;
//-----------------------------------------------------------------
// Sample FIFO - decouple sample capture from memory stalls
//-----------------------------------------------------------------
wire data_accept_w;
// Push on valid data, and push previous value on hitting an edge trigger
wire data_push_w = (buffer_wr_q & triggered_q) ||
(trigger_hit_w && trigger_edge_any_w && !triggered_q);
wire [31:0] data_in_w = (buffer_wr_q & triggered_q) ? buffer_q : prev_q;
logic_capture_fifo
u_fifo_data
(
.clk_i(clk_i)
,.rst_i(rst_i)
,.push_i(data_push_w)
,.data_in_i(data_in_w)
,.accept_o(data_accept_w)
,.valid_o(outport_tvalid_o)
,.data_out_o(outport_tdata_o)
,.pop_i(outport_tready_i)
);
assign outport_tstrb_o = 4'hF;
assign outport_tdest_o = 4'b0;
assign outport_tlast_o = 1'b0;
//-----------------------------------------------------------------
// Sample capture count
//-----------------------------------------------------------------
reg [31:0] samples_count_q;
always @ (posedge clk_i )
if (rst_i)
samples_count_q <= 32'b0;
else if (cfg_enable_reset_w)
samples_count_q <= 32'b0;
else if (outport_tvalid_o && outport_tready_i)
begin
case (la_buffer_cfg_width_out_w)
WIDTH_16BIT: samples_count_q <= samples_count_q + {16'b0, outport_tdata_o[31:16]};
WIDTH_24BIT: samples_count_q <= samples_count_q + {24'b0, outport_tdata_o[31:24]};
default: samples_count_q <= samples_count_q + 32'd1;
endcase
end
assign la_buffer_samples_count_in_w = samples_count_q;
//-----------------------------------------------------------------
// Write detection
//-----------------------------------------------------------------
reg write_detect_q;
always @ (posedge clk_i )
if (rst_i)
write_detect_q <= 1'b0;
else if (cfg_enable_reset_w)
write_detect_q <= 1'b0;
else if (data_push_w)
write_detect_q <= 1'b1;
assign la_buffer_sts_trig_in_w = write_detect_q;
assign la_buffer_sts_num_channels_in_w = NUM_CHANNELS[5:0];
//-----------------------------------------------------------------
// FIFO overflow detect
//-----------------------------------------------------------------
reg data_lost_q;
always @ (posedge clk_i )
if (rst_i)
data_lost_q <= 1'b0;
else if (cfg_enable_reset_w)
data_lost_q <= 1'b0;
else if (data_push_w && !data_accept_w)
data_lost_q <= 1'b1;
assign la_buffer_sts_data_loss_in_w = data_lost_q;
assign la_buffer_current_addr_in_w = buffer_current_i;
assign buffer_base_o = {la_buffer_base_addr_out_w[31:2], 2'b0};
assign buffer_end_o = {la_buffer_end_addr_out_w[31:2], 2'b0};
assign buffer_reset_o = !cfg_enabled_w;
assign la_buffer_sts_wrapped_in_w = buffer_wrapped_i;
assign buffer_cont_o = la_buffer_cfg_cont_out_w;
assign status_enabled_o = cfg_enabled_w;
assign status_triggered_o = la_buffer_sts_trig_in_w;
assign status_overflow_o = la_buffer_sts_data_loss_in_w;
assign cfg_clk_src_ext_o = la_buffer_cfg_clk_src_out_w;
assign cfg_clk_div_o = la_buffer_cfg_clk_div_out_w;
assign cfg_width_o = la_buffer_cfg_width_out_w;
assign cfg_test_mode_o = la_buffer_cfg_test_mode_out_w;
endmodule |
module sata_stack (
input rst, //reset
input clk, //clock used to run the stack
input data_in_clk,
input data_in_clk_valid,
input data_out_clk,
input data_out_clk_valid,
input platform_ready, //the underlying physical platform is
output platform_error, //Underlying platform errored out, the
//clock is misaligned, stack should
//probably be reset
output linkup, //link is finished
input send_sync_escape,
input [15:0] user_features,
//User Interface
output sata_ready,
output sata_busy,
output hard_drive_error,
// input write_data_stb,
// input read_data_stb,
input execute_command_stb,
input command_layer_reset,
input [7:0] hard_drive_command,
output pio_data_ready,
input [15:0] sector_count,
input [47:0] sector_address,
output dma_activate_stb,
output d2h_reg_stb,
output pio_setup_stb,
output d2h_data_stb,
output dma_setup_stb,
output set_device_bits_stb,
output [7:0] d2h_fis,
output d2h_interrupt,
output d2h_notification,
output [3:0] d2h_port_mult,
output [7:0] d2h_device,
output [47:0] d2h_lba,
output [15:0] d2h_sector_count,
output [7:0] d2h_status,
output [7:0] d2h_error,
input [31:0] user_din,
input user_din_stb,
output [1:0] user_din_ready,
input [1:0] user_din_activate,
output [23:0] user_din_size,
output user_din_empty,
output [31:0] user_dout,
output user_dout_ready,
input user_dout_activate,
input user_dout_stb,
output [23:0] user_dout_size,
output transport_layer_ready,
output link_layer_ready,
output phy_ready,
//Buffer
//Platform Interface
output [31:0] tx_dout,
output tx_is_k, //Connect All 4 'tx_is_k'to this signal
output tx_comm_reset,
output tx_comm_wake,
output tx_elec_idle,
input [31:0] rx_din,
input [3:0] rx_is_k,
input rx_elec_idle,
input rx_byte_is_aligned,
input comm_init_detect,
input comm_wake_detect,
input tx_oob_complete,
input phy_error,
//DMA Specific Control
//Data Control
output [3:0] dbg_cc_lax_state,
output [3:0] dbg_cw_lax_state,
output [3:0] dbg_t_lax_state,
output [3:0] dbg_li_lax_state,
output [3:0] dbg_lr_lax_state,
output [3:0] dbg_lw_lax_state,
output [3:0] dbg_lw_lax_fstate,
//Link Layer
input prim_scrambler_en,
input data_scrambler_en,
output dbg_ll_write_ready,
output dbg_ll_paw,
output dbg_ll_write_strobe,
output dbg_ll_send_crc,
//Phy Layer
output [3:0] oob_state,
//Primative Detection
output dbg_detect_sync,
output dbg_detect_r_rdy,
output dbg_detect_r_ip,
output dbg_detect_r_ok,
output dbg_detect_r_err,
output dbg_detect_x_rdy,
output dbg_detect_sof,
output dbg_detect_eof,
output dbg_detect_wtrm,
output dbg_detect_cont,
output dbg_detect_hold,
output dbg_detect_holda,
output dbg_detect_align,
output dbg_detect_preq_s,
output dbg_detect_preq_p,
output dbg_detect_xrdy_xrdy,
output dbg_send_holda,
output [23:0] slw_in_data_addra,
output [12:0] slw_d_count,
output [12:0] slw_write_count,
output [3:0] slw_buffer_pos
);
//Parameters
//Registers/Wires
//Command Layer
wire send_command_stb;
wire send_control_stb;
wire send_data_stb;
wire if_strobe;
wire [31:0] if_data;
wire if_ready;
wire if_activate;
wire [23:0] if_size;
wire of_strobe;
wire [31:0] of_data;
wire [1:0] of_ready;
wire [1:0] of_activate;
wire [23:0] of_size;
//Link Layer
wire ll_sync_escape;
wire ll_write_start;
wire ll_write_strobe;
wire ll_write_finished;
wire [31:0] ll_write_data;
wire [23:0] ll_write_size;
wire ll_write_hold;
wire ll_write_abort;
wire ll_read_ready;
wire ll_read_start;
wire ll_read_strobe;
wire [31:0] ll_read_data;
wire ll_read_finished;
wire ll_read_crc_ok;
wire ll_remote_abort;
wire ll_xmit_error;
wire [31:0] ll_tx_dout;
wire ll_tx_is_k;
//Phy Layer
wire [31:0] phy_tx_dout;
wire phy_tx_is_k;
//User Interface state machine
//Transport Layer
wire sync_escape;
wire [7:0] h2d_command;
wire [15:0] h2d_features;
wire [7:0] h2d_control;
wire [3:0] h2d_port_mult;
wire [7:0] h2d_device;
wire [47:0] h2d_lba;
wire [15:0] h2d_sector_count;
wire remote_abort;
wire xmit_error;
wire read_crc_error;
//PIO
wire pio_response;
wire pio_direction;
wire [15:0] pio_transfer_count;
wire [7:0] pio_e_status;
//Data Control
wire cl_if_ready;
wire cl_if_activate;
wire [23:0] cl_if_size;
wire cl_if_strobe;
wire [31:0] cl_if_data;
wire [1:0] cl_of_ready;
wire [1:0] cl_of_activate;
wire cl_of_strobe;
wire [31:0] cl_of_data;
wire [23:0] cl_of_size;
//Link Layer Interface
wire t_sync_escape;
wire t_write_start;
wire t_write_strobe;
wire t_write_finished;
wire [31:0] t_write_data;
wire [23:0] t_write_size;
wire t_write_hold;
wire t_write_abort;
wire t_xmit_error;
wire t_read_start;
wire t_read_ready;
wire [31:0] t_read_data;
wire t_read_strobe;
wire t_read_finished;
wire t_read_crc_ok;
wire t_remote_abort;
//Comand Layer registers
//Submodules
sata_command_layer scl (
.rst (rst ),
.linkup (linkup ),
.clk (clk ),
.data_in_clk (data_in_clk ),
.data_in_clk_valid (data_in_clk_valid ),
.data_out_clk (data_out_clk ),
.data_out_clk_valid (data_out_clk_valid ),
//Application Interface
.command_layer_ready (sata_ready ),
.sata_busy (sata_busy ),
.hard_drive_error (hard_drive_error ),
.send_sync_escape (send_sync_escape ),
.user_features (user_features ),
// .write_data_stb (write_data_stb ),
// .read_data_stb (read_data_stb ),
.execute_command_stb (execute_command_stb ),
.command_layer_reset (command_layer_reset ),
.hard_drive_command (hard_drive_command ),
.pio_data_ready (pio_data_ready ),
.sector_count (sector_count ),
.sector_address (sector_address ),
.user_din (user_din ),
.user_din_stb (user_din_stb ),
.user_din_ready (user_din_ready ),
.user_din_activate (user_din_activate ),
.user_din_size (user_din_size ),
.user_din_empty (user_din_empty ),
.user_dout (user_dout ),
.user_dout_ready (user_dout_ready ),
.user_dout_activate (user_dout_activate ),
.user_dout_stb (user_dout_stb ),
.user_dout_size (user_dout_size ),
//Transfer Layer Interface
.transport_layer_ready(transport_layer_ready ),
.sync_escape (sync_escape ),
.t_send_command_stb (send_command_stb ),
.t_send_control_stb (send_control_stb ),
.t_send_data_stb (send_data_stb ),
.t_dma_activate_stb (dma_activate_stb ),
.t_d2h_reg_stb (d2h_reg_stb ),
.t_pio_setup_stb (pio_setup_stb ),
.t_d2h_data_stb (d2h_data_stb ),
.t_dma_setup_stb (dma_setup_stb ),
.t_set_device_bits_stb(set_device_bits_stb ),
.t_remote_abort (remote_abort ),
.t_xmit_error (xmit_error ),
.t_read_crc_error (read_crc_error ),
//PIO
.t_pio_response (pio_response ),
.t_pio_direction (pio_direction ),
.t_pio_transfer_count (pio_transfer_count ),
.t_pio_e_status (pio_e_status ),
//Host to Device Register Values
.h2d_command (h2d_command ),
.h2d_features (h2d_features ),
.h2d_control (h2d_control ),
.h2d_port_mult (h2d_port_mult ),
.h2d_device (h2d_device ),
.h2d_lba (h2d_lba ),
.h2d_sector_count (h2d_sector_count ),
//Device to Host Register Values
.d2h_interrupt (d2h_interrupt ),
.d2h_notification (d2h_notification ),
.d2h_port_mult (d2h_port_mult ),
.d2h_device (d2h_device ),
.d2h_lba (d2h_lba ),
.d2h_sector_count (d2h_sector_count ),
.d2h_status (d2h_status ),
.d2h_error (d2h_error ),
//command layer data interface
.t_if_strobe (if_strobe ),
.t_if_data (if_data ),
.t_if_ready (if_ready ),
.t_if_activate (if_activate ),
.t_if_size (if_size ),
.t_of_strobe (of_strobe ),
.t_of_data (of_data ),
.t_of_ready (of_ready ),
.t_of_activate (of_activate ),
.t_of_size (of_size ),
.cl_c_state (dbg_cc_lax_state ),
.cl_w_state (dbg_cw_lax_state )
);
//Transport Layer
sata_transport_layer stl (
.rst (rst | !linkup ),
.clk (clk ),
.phy_ready (phy_ready ),
//Status
.transport_layer_ready (transport_layer_ready ),
.sync_escape (sync_escape ),
.send_command_stb (send_command_stb ),
.send_control_stb (send_control_stb ),
.send_data_stb (send_data_stb ),
.dma_activate_stb (dma_activate_stb ),
.d2h_reg_stb (d2h_reg_stb ),
.pio_setup_stb (pio_setup_stb ),
.d2h_data_stb (d2h_data_stb ),
.dma_setup_stb (dma_setup_stb ),
.set_device_bits_stb (set_device_bits_stb ),
.remote_abort (remote_abort ),
.xmit_error (xmit_error ),
.read_crc_error (read_crc_error ),
//PIO
.pio_response (pio_response ),
.pio_direction (pio_direction ),
.pio_transfer_count (pio_transfer_count ),
.pio_e_status (pio_e_status ),
//Host to Device Register Values
.h2d_command (h2d_command ),
.h2d_features (h2d_features ),
.h2d_control (h2d_control ),
.h2d_port_mult (h2d_port_mult ),
.h2d_device (h2d_device ),
.h2d_lba (h2d_lba ),
.h2d_sector_count (h2d_sector_count ),
//Device to Host Register Values
.d2h_fis (d2h_fis ),
.d2h_interrupt (d2h_interrupt ),
.d2h_notification (d2h_notification ),
.d2h_port_mult (d2h_port_mult ),
.d2h_device (d2h_device ),
.d2h_lba (d2h_lba ),
.d2h_sector_count (d2h_sector_count ),
.d2h_status (d2h_status ),
.d2h_error (d2h_error ),
//command layer data interface
.cl_if_ready (cl_if_ready ),
.cl_if_activate (cl_if_activate ),
.cl_if_size (cl_if_size ),
.cl_if_strobe (cl_if_strobe ),
.cl_if_data (cl_if_data ),
.cl_of_ready (cl_of_ready ),
.cl_of_activate (cl_of_activate ),
.cl_of_strobe (cl_of_strobe ),
.cl_of_data (cl_of_data ),
.cl_of_size (cl_of_size ),
//Link Layer Interface
.link_layer_ready (link_layer_ready ),
.ll_sync_escape (t_sync_escape ),
.ll_write_start (t_write_start ),
.ll_write_strobe (t_write_strobe ),
.ll_write_finished (t_write_finished ),
.ll_write_data (t_write_data ),
.ll_write_size (t_write_size ),
.ll_write_hold (t_write_hold ),
.ll_write_abort (t_write_abort ),
.ll_xmit_error (t_xmit_error ),
.ll_read_start (t_read_start ),
.ll_read_ready (t_read_ready ),
.ll_read_data (t_read_data ),
.ll_read_strobe (t_read_strobe ),
.ll_read_finished (t_read_finished ),
.ll_read_crc_ok (t_read_crc_ok ),
.ll_remote_abort (t_remote_abort ),
.lax_state (dbg_t_lax_state )
);
sata_link_layer sll(
.rst (rst | !linkup ),
.clk (clk ),
//Status
.link_layer_ready (link_layer_ready ),
.sync_escape (ll_sync_escape ),
.write_ready (dbg_ll_write_ready ),
.post_align_write (dbg_ll_paw ),
.hold (1'b0 ),
//Transport Layer Interface
.write_start (ll_write_start ),
.write_strobe (ll_write_strobe ),
.write_finished (ll_write_finished ),
.write_data (ll_write_data ),
.write_size (ll_write_size ),
.write_hold (ll_write_hold ),
.write_abort (ll_write_abort ),
.read_data (ll_read_data ),
.read_strobe (ll_read_strobe ),
.read_ready (ll_read_ready ),
.read_start (ll_read_start ),
.read_finished (ll_read_finished ),
.remote_abort (ll_remote_abort ),
.xmit_error (ll_xmit_error ),
.read_crc_ok (ll_read_crc_ok ),
.prim_scrambler_en (prim_scrambler_en ),
.data_scrambler_en (data_scrambler_en ),
//Phy Layer
.phy_ready (phy_ready ),
.platform_ready (platform_ready ),
.tx_dout (ll_tx_dout ),
.tx_is_k (ll_tx_is_k ),
.rx_din (rx_din ),
.rx_is_k (rx_is_k ),
.is_device (1'b0 ),
//Primative Detection
.detect_sync (dbg_detect_sync ),
.detect_r_rdy (dbg_detect_r_rdy ),
.detect_r_ip (dbg_detect_r_ip ),
.detect_r_ok (dbg_detect_r_ok ),
.detect_r_err (dbg_detect_r_err ),
.detect_x_rdy (dbg_detect_x_rdy ),
.detect_sof (dbg_detect_sof ),
.detect_eof (dbg_detect_eof ),
.detect_wtrm (dbg_detect_wtrm ),
.detect_cont (dbg_detect_cont ),
.detect_hold (dbg_detect_hold ),
.detect_holda (dbg_detect_holda ),
.detect_align (dbg_detect_align ),
.detect_preq_s (dbg_detect_preq_s ),
.detect_preq_p (dbg_detect_preq_p ),
.detect_xrdy_xrdy (dbg_detect_xrdy_xrdy ),
.dbg_send_holda (dbg_send_holda ),
.send_crc (dbg_ll_send_crc ),
.lax_i_state (dbg_li_lax_state ),
.lax_r_state (dbg_lr_lax_state ),
.lax_w_state (dbg_lw_lax_state ),
.lax_w_fstate (dbg_lw_lax_fstate ),
.in_data_addra (slw_in_data_addra ),
.d_count (slw_d_count ),
.write_count (slw_write_count ),
.buffer_pos (slw_buffer_pos )
);
sata_phy_layer phy (
.rst (rst ),
.clk (clk ),
//Control/Status
.platform_ready (platform_ready ),
.platform_error (platform_error ),
.linkup (linkup ),
//Platform Interface
.tx_dout (phy_tx_dout ),
.tx_is_k (phy_tx_is_k ),
.tx_comm_reset (tx_comm_reset ),
.tx_comm_wake (tx_comm_wake ),
.tx_elec_idle (tx_elec_idle ),
.tx_oob_complete (tx_oob_complete ),
.rx_din (rx_din ),
.rx_is_k (rx_is_k ),
.comm_init_detect (comm_init_detect ),
.comm_wake_detect (comm_wake_detect ),
.rx_elec_idle (rx_elec_idle ),
.rx_byte_is_aligned (rx_byte_is_aligned ),
.phy_error (phy_error ),
.lax_state (oob_state ),
.phy_ready (phy_ready )
);
//Asynchronous Logic
//control of data to the platform controller
//In order to send align primitives the phy must sometimes take over the bus
assign tx_dout = (phy_ready) ? ll_tx_dout : phy_tx_dout;
assign tx_is_k = (phy_ready) ? ll_tx_is_k : phy_tx_is_k;
//no activity on the stack
//Debug
assign ll_write_start = t_write_start;
assign ll_write_data = t_write_data;
assign ll_write_hold = t_write_hold;
assign ll_write_size = t_write_size;
assign ll_write_abort = t_write_abort;
assign ll_read_ready = t_read_ready;
assign ll_sync_escape = t_sync_escape;
assign t_write_strobe = ll_write_strobe;
assign t_write_finished = ll_write_finished;
assign t_read_strobe = ll_read_strobe;
assign t_read_start = ll_read_start;
assign t_read_finished = ll_read_finished;
assign t_read_data = ll_read_data;
assign t_remote_abort = ll_remote_abort;
assign t_xmit_error = ll_xmit_error;
assign t_read_crc_ok = ll_read_crc_ok;
assign cl_if_ready = if_ready;
assign if_activate = cl_if_activate;
assign cl_if_size = if_size;
assign if_strobe = cl_if_strobe;
assign cl_if_data = if_data;
assign cl_of_ready = of_ready;
assign of_activate = cl_of_activate;
assign of_strobe = cl_of_strobe;
assign of_data = cl_of_data;
assign cl_of_size = of_size;
//Synchronous Logic
endmodule |
module data_test2 (
input rst, //reset
input clk,
output reg din_stb,
input [1:0] din_ready,
output reg [1:0] din_activate,
output reg [31:0] din,
input [23:0] din_size,
input dout_ready,
output reg dout_activate,
input [31:0] dout,
output reg dout_stb,
input [23:0] dout_size,
output reg count_error,
output reg incorrect_data,
output reg [23:0] count_detected,
output reg [31:0] detected_value
);
//Parameters
//Registers/Wires
reg [31:0] write_count;
reg [31:0] read_count;
//Submodules
//Asynchronous Logic
//Synchronous Logic
always @ (posedge clk) begin
if (rst) begin
din_stb <= 0;
din_activate <= 0;
din <= 0;
write_count <= 0;
dout_activate <= 0;
dout_stb <= 0;
read_count <= 0;
count_error <= 0;
incorrect_data <= 0;
detected_value <= 0;
count_detected <= 0;
end
else begin
din_stb <= 0;
dout_stb <= 0;
count_error <= 0;
incorrect_data <= 0;
if ((din_ready > 0) && (din_activate == 0)) begin
write_count <= 0;
din <= 0;
if (din_ready[0]) begin
din_activate[0] <= 1;
end
else begin
din_activate[1] <= 1;
end
end
else if (din_activate != 0) begin
if (write_count < din_size) begin
din_stb <= 1;
din <= write_count;
write_count <= write_count + 1;
end
else begin
din_activate <= 0;
end
end
if (dout_ready && !dout_activate) begin
read_count <= 0;
dout_activate <= 1;
if (dout_size != 24'h0800) begin
count_error <= 1;
count_detected <= dout_size;
end
end
else if (dout_activate) begin
if (read_count < dout_size) begin
dout_stb <= 1;
read_count <= read_count + 1;
end
else begin
dout_activate <= 0;
end
//Error Detection
if (read_count > 0) begin
if (dout != read_count - 1) begin
incorrect_data <= 1;
count_detected <= read_count[23:0];
detected_value <= dout;
end
end
else begin
if (dout != 0) begin
incorrect_data <= 1;
count_detected <= read_count[23:0];
detected_value <= dout;
end
end
end
end
end
endmodule |
module hd_data_writer(
input clk,
input rst,
input enable,
output reg [31:0] data,
input strobe
);
//Registers and Wires
reg [31:0] test_data;
//Submodules
//Asynchronous Logic
//Synchronous Logic
always @ (posedge clk) begin
if (rst) begin
test_data <= 0;
data <= 0;
end
else begin
if (enable) begin
data <= test_data;
if (strobe) begin
test_data <= test_data + 1;
end
end
else begin
test_data <= 0;
end
end
end
endmodule |
module test_in (
input clk,
input rst,
input enable,
output reg finished,
input [23:0] write_count,
input [1:0] ready,
output reg [1:0] activate,
output reg [31:0] fifo_data,
input [23:0] fifo_size,
output reg strobe
);
//Parameters
//Registers/Wires
reg [23:0] count;
reg [23:0] total_count;
//Sub modules
//Asynchronous Logic
//Synchronous Logic
always @ (posedge clk or posedge rst) begin
if (rst) begin
activate <= 0;
fifo_data <= 0;
strobe <= 0;
count <= 0;
total_count <= 0;
finished <= 0;
end
else begin
strobe <= 0;
if (!enable) begin
total_count <= 0;
activate <= 0;
finished <= 0;
end
else if (total_count < write_count) begin
if ((ready > 0) && (activate == 0)) begin
//A FIFO is available
count <= 0;
if (ready[0]) begin
activate[0] <= 1;
end
else begin
activate[1] <= 1;
end
end
else if ((activate > 0) && (count < fifo_size))begin
fifo_data <= total_count;
total_count <= total_count + 1;
count <= count + 1;
strobe <= 1;
end
else begin
activate <= 0;
end
end
else begin
finished <= 1;
activate <= 0;
end
end
end
endmodule |
module tb_cocotb (
//Parameters
//Registers/Wires
input rst, //reset
input clk,
output linkup, //link is finished
output sata_ready,
output sata_busy,
//input write_data_stb,
//input read_data_stb,
input [7:0] hard_drive_command,
input execute_command_stb,
input command_layer_reset,
input [15:0] sector_count,
input [47:0] sector_address,
output d2h_interrupt,
output d2h_notification,
output [3:0] d2h_port_mult,
output [7:0] d2h_device,
output [47:0] d2h_lba,
output [15:0] d2h_sector_count,
output [7:0] d2h_status,
output [7:0] d2h_error,
input u2h_write_enable,
output u2h_write_finished,
input [23:0] u2h_write_count,
input h2u_read_enable,
output [23:0] h2u_read_total_count,
output h2u_read_error,
output h2u_read_busy,
output u2h_read_error,
output transport_layer_ready,
output link_layer_ready,
output phy_ready,
input prim_scrambler_en,
input data_scrambler_en,
//Data Interface
output tx_set_elec_idle,
output rx_is_elec_idle,
output hd_ready,
input platform_ready,
//Debug
input hold,
input single_rdwr
);
reg [31:0] test_id = 0;
wire [31:0] tx_dout;
wire tx_is_k;
wire tx_comm_reset;
wire tx_comm_wake;
wire tx_elec_idle;
wire [31:0] rx_din;
wire [3:0] rx_is_k;
wire rx_elec_idle;
wire comm_init_detect;
wire comm_wake_detect;
reg r_rst;
reg r_write_data_stb;
reg r_read_data_stb;
reg r_command_layer_reset;
reg [15:0] r_sector_count;
reg [47:0] r_sector_address;
reg r_prim_scrambler_en;
reg r_data_scrambler_en;
reg r_platform_ready;
reg r_dout_count;
reg r_hold;
reg r_u2h_write_enable;
reg [23:0] r_u2h_write_count;
reg r_h2u_read_enable;
reg [7:0] r_hard_drive_command;
reg r_execute_command_stb;
wire hd_read_from_host;
wire [31:0] hd_data_from_host;
wire hd_write_to_host;
wire [31:0] hd_data_to_host;
wire [31:0] user_dout;
wire user_dout_ready;
wire user_dout_activate;
wire user_dout_stb;
wire [23:0] user_dout_size;
wire [31:0] user_din;
wire user_din_stb;
wire [1:0] user_din_ready;
wire [1:0] user_din_activate;
wire [23:0] user_din_size;
wire dma_activate_stb;
wire d2h_reg_stb;
wire pio_setup_stb;
wire d2h_data_stb;
wire dma_setup_stb;
wire set_device_bits_stb;
wire [7:0] d2h_fis;
wire i_rx_byte_is_aligned;
//There is a bug in COCOTB when stiumlating a signal, sometimes it can be corrupted if not registered
always @ (*) r_rst = rst;
//always @ (*) r_write_data_stb = write_data_stb;
//always @ (*) r_read_data_stb = read_data_stb;
always @ (*) r_command_layer_reset= command_layer_reset;
always @ (*) r_sector_count = sector_count;
always @ (*) r_sector_address = sector_address;
always @ (*) r_prim_scrambler_en = prim_scrambler_en;
always @ (*) r_data_scrambler_en = data_scrambler_en;
always @ (*) r_platform_ready = platform_ready;
always @ (*) r_hold = hold;
always @ (*) r_u2h_write_enable = u2h_write_enable;
always @ (*) r_u2h_write_count = u2h_write_count;
always @ (*) r_h2u_read_enable = h2u_read_enable;
always @ (*) r_hard_drive_command = hard_drive_command;
always @ (*) r_execute_command_stb= execute_command_stb;
//Submodules
//User Generated Test Data
test_in user_2_hd_generator(
.clk (clk ),
.rst (rst ),
.enable (r_u2h_write_enable ),
.finished (u2h_write_finished ),
.write_count (r_u2h_write_count ),
.ready (user_din_ready ),
.activate (user_din_activate ),
.fifo_data (user_din ),
.fifo_size (user_din_size ),
.strobe (user_din_stb )
);
//Module to process data from Hard Drive to User
test_out hd_2_user_reader(
.clk (clk ),
.rst (rst ),
.busy (h2u_read_busy ),
.enable (r_h2u_read_enable ),
.error (h2u_read_error ),
.total_count (h2u_read_total_count ),
.ready (user_dout_ready ),
.activate (user_dout_activate ),
.size (user_dout_size ),
.data (user_dout ),
.strobe (user_dout_stb )
);
//hd data reader core
hd_data_reader user_2_hd_reader(
.clk (clk ),
.rst (rst ),
.enable (r_u2h_write_enable ),
.error (u2h_read_error ),
.hd_read_from_host (hd_read_from_host ),
.hd_data_from_host (hd_data_from_host )
);
//hd data writer core
hd_data_writer hd_2_user_generator(
.clk (clk ),
.rst (rst ),
.enable (r_h2u_read_enable ),
.data (hd_data_to_host ),
.strobe (hd_write_to_host )
);
sata_stack ss (
.rst (r_rst ), //reset
.clk (clk ), //clock used to run the stack
.command_layer_reset (r_command_layer_reset),
.platform_ready (platform_ready ), //the underlying physical platform is
.platform_error ( ),
.linkup (linkup ), //link is finished
.sata_ready (sata_ready ),
.sata_busy (sata_busy ),
.send_sync_escape (1'b0 ),
.hard_drive_error ( ),
.pio_data_ready ( ),
//Host to Device Control
// .write_data_stb (r_write_data_stb ),
// .read_data_stb (r_read_data_stb ),
.hard_drive_command (r_hard_drive_command ),
.execute_command_stb (r_execute_command_stb),
.user_features (16'h0000 ),
.sector_count (r_sector_count ),
.sector_address (r_sector_address ),
.dma_activate_stb (dma_activate_stb ),
.d2h_reg_stb (d2h_reg_stb ),
.pio_setup_stb (pio_setup_stb ),
.d2h_data_stb (d2h_data_stb ),
.dma_setup_stb (dma_setup_stb ),
.set_device_bits_stb (set_device_bits_stb ),
.d2h_fis (d2h_fis ),
.d2h_interrupt (d2h_interrupt ),
.d2h_notification (d2h_notification ),
.d2h_port_mult (d2h_port_mult ),
.d2h_device (d2h_device ),
.d2h_lba (d2h_lba ),
.d2h_sector_count (d2h_sector_count ),
.d2h_status (d2h_status ),
.d2h_error (d2h_error ),
//Data from host to the hard drive path
.data_in_clk (clk ),
.data_in_clk_valid (1'b1 ),
.user_din (user_din ), //User Data Here
.user_din_stb (user_din_stb ), //Strobe Each Data word in here
.user_din_ready (user_din_ready ), //Using PPFIFO Ready Signal
.user_din_activate (user_din_activate ), //Activate PPFIFO Channel
.user_din_size (user_din_size ), //Find the size of the data to write to the device
//Data from hard drive to host path
.data_out_clk (clk ),
.data_out_clk_valid (1'b1 ),
.user_dout (user_dout ),
.user_dout_ready (user_dout_ready ),
.user_dout_activate (user_dout_activate ),
.user_dout_stb (user_dout_stb ),
.user_dout_size (user_dout_size ),
.transport_layer_ready (transport_layer_ready),
.link_layer_ready (link_layer_ready ),
.phy_ready (phy_ready ),
.phy_error (1'b0 ),
.tx_dout (tx_dout ),
.tx_is_k (tx_is_k ),
.tx_comm_reset (tx_comm_reset ),
.tx_comm_wake (tx_comm_wake ),
.tx_elec_idle (tx_elec_idle ),
.tx_oob_complete (1'b1 ),
.rx_din (rx_din ),
.rx_is_k (rx_is_k ),
.rx_elec_idle (rx_elec_idle ),
.rx_byte_is_aligned (i_rx_byte_is_aligned ),
.comm_init_detect (comm_init_detect ),
.comm_wake_detect (comm_wake_detect ),
//.prim_scrambler_en (r_prim_scrambler_en ),
.prim_scrambler_en (1'b1 ),
//.data_scrambler_en (r_data_scrambler_en )
.data_scrambler_en (1'b1 )
);
faux_sata_hd fshd (
.rst (r_rst ),
.clk (clk ),
.tx_dout (rx_din ),
.tx_is_k (rx_is_k ),
.rx_din (tx_dout ),
.rx_is_k ({3'b000, tx_is_k} ),
.rx_is_elec_idle (tx_elec_idle ),
.rx_byte_is_aligned (i_rx_byte_is_aligned ),
.comm_reset_detect (tx_comm_reset ),
.comm_wake_detect (tx_comm_wake ),
.tx_comm_reset (comm_init_detect ),
.tx_comm_wake (comm_wake_detect ),
.hd_ready (hd_ready ),
// .phy_ready (phy_ready ),
//.dbg_data_scrambler_en (r_data_scrambler_en ),
.dbg_data_scrambler_en (1'b1 ),
.dbg_hold (r_hold ),
.dbg_ll_write_start (1'b0 ),
.dbg_ll_write_data (32'h0 ),
.dbg_ll_write_size (0 ),
.dbg_ll_write_hold (1'b0 ),
.dbg_ll_write_abort (1'b0 ),
.dbg_ll_read_ready (1'b0 ),
.dbg_t_en (1'b0 ),
.dbg_send_reg_stb (1'b0 ),
.dbg_send_dma_act_stb (1'b0 ),
.dbg_send_data_stb (1'b0 ),
.dbg_send_pio_stb (1'b0 ),
.dbg_send_dev_bits_stb (1'b0 ),
.dbg_pio_transfer_count(16'h0000 ),
.dbg_pio_direction (1'b0 ),
.dbg_pio_e_status (8'h00 ),
.dbg_d2h_interrupt (1'b0 ),
.dbg_d2h_notification (1'b0 ),
.dbg_d2h_status (8'b0 ),
.dbg_d2h_error (8'b0 ),
.dbg_d2h_port_mult (4'b0000 ),
.dbg_d2h_device (8'h00 ),
.dbg_d2h_lba (48'h000000000000 ),
.dbg_d2h_sector_count (16'h0000 ),
.dbg_cl_if_data (32'b0 ),
.dbg_cl_if_ready (1'b0 ),
.dbg_cl_if_size (24'h0 ),
.dbg_cl_of_ready (2'b0 ),
.dbg_cl_of_size (24'h0 ),
.hd_read_from_host (hd_read_from_host ),
.hd_data_from_host (hd_data_from_host ),
.hd_write_to_host (hd_write_to_host ),
.hd_data_to_host (hd_data_to_host )
);
//Asynchronous Logic
//Synchronous Logic
//Simulation Control
initial begin
$dumpfile ("design.vcd");
$dumpvars(0, tb_cocotb);
end
endmodule |
module faux_sata_hd (
//Inputs/Outputs
input rst, //reset
input clk,
//Data Interface
output [31:0] tx_dout,
output [3:0] tx_is_k,
output tx_set_elec_idle,
output rx_byte_is_aligned,
input [31:0] rx_din,
input [3:0] rx_is_k,
input rx_is_elec_idle,
input comm_reset_detect,
input comm_wake_detect,
output tx_comm_reset,
output tx_comm_wake,
output hd_ready,
output phy_ready,
//Debug
output [3:0] oob_state,
output [3:0] cl_state,
//Link Layer
input dbg_ll_write_start,
output dbg_ll_write_strobe,
output dbg_ll_write_finished,
input [31:0] dbg_ll_write_data,
input [31:0] dbg_ll_write_size,
input dbg_ll_write_hold,
input dbg_ll_write_abort,
output dbg_ll_xmit_error,
output dbg_ll_read_start,
output dbg_ll_read_strobe,
output [31:0] dbg_ll_read_data,
input dbg_ll_read_ready,
output dbg_ll_read_finished,
output dbg_ll_remote_abort,
input dbg_data_scrambler_en,
input dbg_hold,
//Transport Layer Debug
input dbg_t_en,
//Trasport Layer Control/Status
output dbg_tl_ready,
input dbg_send_reg_stb,
input dbg_send_dma_act_stb,
input dbg_send_data_stb,
input dbg_send_pio_stb,
input dbg_send_dev_bits_stb,
output dbg_remote_abort,
output dbg_xmit_error,
output dbg_read_crc_fail,
output dbg_h2d_reg_stb,
output dbg_h2d_data_stb,
output dbg_pio_request,
input [15:0] dbg_pio_transfer_count,
input dbg_pio_direction,
input [7:0] dbg_pio_e_status,
//FIS Structure
output [7:0] dbg_h2d_command,
output [15:0] dbg_h2d_features,
output dbg_h2d_cmd_bit,
output [3:0] dbg_h2d_port_mult,
output [7:0] dbg_h2d_control,
output [7:0] dbg_h2d_device,
output [47:0] dbg_h2d_lba,
output [15:0] dbg_h2d_sector_count,
input dbg_d2h_interrupt,
input dbg_d2h_notification,
input [7:0] dbg_d2h_status,
input [7:0] dbg_d2h_error,
input [3:0] dbg_d2h_port_mult,
input [7:0] dbg_d2h_device,
input [47:0] dbg_d2h_lba,
input [15:0] dbg_d2h_sector_count,
//command layer data interface
output dbg_cl_if_strobe,
input [31:0] dbg_cl_if_data,
input dbg_cl_if_ready,
output dbg_cl_if_activate,
input [23:0] dbg_cl_if_size,
output dbg_cl_of_strobe,
output [31:0] dbg_cl_of_data,
input [1:0] dbg_cl_of_ready,
output [1:0] dbg_cl_of_activate,
input [23:0] dbg_cl_of_size,
output command_layer_ready,
output hd_read_from_host,
output [31:0] hd_data_from_host,
output hd_write_to_host,
input [31:0] hd_data_to_host
);
//Parameters
//Registers/Wires
wire [31:0] phy_tx_dout;
wire phy_tx_is_k;
wire [31:0] sll_tx_dout;
wire sll_tx_is_k;
wire ll_ready;
wire ll_write_start;
wire ll_write_finished;
wire ll_write_strobe;
wire [31:0] ll_write_data;
wire [31:0] ll_write_size;
wire ll_write_hold;
wire ll_write_abort;
wire ll_read_start;
wire ll_read_strobe;
wire [31:0] ll_read_data;
wire ll_remote_abort;
wire ll_read_ready;
wire ll_read_finished;
wire ll_read_crc_ok;
wire data_scrambler_en;
//Command Layer
wire cl_send_reg_stb;
wire cl_send_dma_act_stb;
wire cl_send_data_stb;
wire cl_send_pio_stb;
wire cl_send_dev_bits_stb;
wire [15:0] cl_pio_transfer_count;
wire cl_pio_direction;
wire [7:0] cl_pio_e_status;
wire cl_d2h_interrupt;
wire cl_d2h_notification;
wire [7:0] cl_d2h_status;
wire [7:0] cl_d2h_error;
wire [3:0] cl_d2h_port_mult;
wire [7:0] cl_d2h_device;
wire [47:0] cl_d2h_lba;
wire [15:0] cl_d2h_sector_count;
//Trasport Layer Control/Status
wire transport_layer_ready;
wire send_reg_stb;
wire send_dma_act_stb;
wire send_data_stb;
wire send_pio_stb;
wire send_dev_bits_stb;
wire remote_abort;
wire xmit_error;
wire read_crc_fail;
wire h2d_reg_stb;
wire h2d_data_stb;
wire pio_request;
wire [15:0] pio_transfer_count;
wire pio_direction;
wire [7:0] pio_e_status;
wire [31:0] if_data;
wire if_ready;
wire [23:0] if_size;
wire [1:0] of_ready;
wire [23:0] of_size;
//Host to Device Registers
wire [7:0] h2d_command;
wire [15:0] h2d_features;
wire h2d_cmd_bit;
wire [7:0] h2d_control;
wire [3:0] h2d_port_mult;
wire [7:0] h2d_device;
wire [47:0] h2d_lba;
wire [15:0] h2d_sector_count;
//Device to Host Registers
wire d2h_interrupt;
wire d2h_notification;
wire [3:0] d2h_port_mult;
wire [7:0] d2h_device;
wire [47:0] d2h_lba;
wire [15:0] d2h_sector_count;
wire [7:0] d2h_status;
wire [7:0] d2h_error;
//DMA Specific Control
//Data Control
wire cl_if_ready;
wire cl_if_activate;
wire [23:0] cl_if_size;
wire cl_if_strobe;
wire [31:0] cl_if_data;
wire [1:0] cl_of_ready;
wire [1:0] cl_of_activate;
wire cl_of_strobe;
wire [31:0] cl_of_data;
wire [23:0] cl_of_size;
//Link Layer Interface
wire t_write_start;
wire t_write_strobe;
wire t_write_finished;
wire [31:0] t_write_data;
wire [31:0] t_write_size;
wire t_write_hold;
wire t_write_abort;
wire t_xmit_error;
wire t_read_start;
wire t_read_ready;
wire [31:0] t_read_data;
wire t_read_strobe;
wire t_read_finished;
wire t_read_crc_ok;
wire t_remote_abort;
//Sub Modules
faux_sata_hd_phy hd_phy(
.rst (rst ),
.clk (clk ),
//incomming/output data
.tx_dout (phy_tx_dout ),
.tx_is_k (phy_tx_is_k ),
.tx_set_elec_idle (tx_set_elec_idle ),
.rx_din (rx_din ),
.rx_is_k (rx_is_k ),
.rx_is_elec_idle (rx_is_elec_idle ),
.rx_byte_is_aligned (rx_byte_is_aligned ),
.comm_reset_detect (comm_reset_detect ),
.comm_wake_detect (comm_wake_detect ),
.tx_comm_reset (tx_comm_reset ),
.tx_comm_wake (tx_comm_wake ),
//Status
.lax_state (oob_state ),
.phy_ready (phy_ready ),
.hd_ready (hd_ready )
);
sata_link_layer fsll (
.rst (rst || !hd_ready ),
.clk (clk ),
.prim_scrambler_en (1'b1 ),
.data_scrambler_en (data_scrambler_en ),
.link_layer_ready (ll_ready ),
.sync_escape (1'b0 ),
.hold (dbg_hold ),
//Transport Layer Interface
.write_start (ll_write_start ),
.write_strobe (ll_write_strobe ),
.write_data (ll_write_data ),
.write_size (ll_write_size ),
.write_hold (ll_write_hold ),
.write_finished (ll_write_finished ),
.write_abort (ll_write_abort ),
.xmit_error (t_xmit_error ),
.read_strobe (ll_read_strobe ),
.read_data (ll_read_data ),
.read_ready (ll_read_ready ),
.read_start (ll_read_start ),
.read_finished (ll_read_finished ),
.read_crc_ok (ll_read_crc_ok ),
.remote_abort (ll_remote_abort ),
//Phy Layer
.phy_ready (phy_ready ),
.platform_ready (hd_ready ),
.tx_dout (sll_tx_dout ),
.tx_is_k (sll_tx_is_k ),
.rx_din (rx_din ),
.rx_is_k (rx_is_k ),
.is_device (1'b1 )
);
faux_sata_hd_transport ftl (
.rst (rst || !hd_ready ),
.clk (clk ),
//Trasport Layer Control/Status
.transport_layer_ready(transport_layer_ready ),
.send_reg_stb (send_reg_stb ),
.send_dma_act_stb (send_dma_act_stb ),
.send_data_stb (send_data_stb ),
.send_pio_stb (send_pio_stb ),
.send_dev_bits_stb (send_dev_bits_stb ),
.remote_abort (remote_abort ),
.xmit_error (xmit_error ),
.read_crc_fail (read_crc_fail ),
.h2d_reg_stb (h2d_reg_stb ),
.h2d_data_stb (h2d_data_stb ),
.pio_request (pio_request ),
.pio_transfer_count (pio_transfer_count ),
.pio_direction (pio_direction ),
.pio_e_status (pio_e_status ),
//FIS Structure
.h2d_command (h2d_command ),
.h2d_features (h2d_features ),
.h2d_cmd_bit (h2d_cmd_bit ),
.h2d_port_mult (h2d_port_mult ),
.h2d_control (h2d_control ),
.h2d_device (h2d_device ),
.h2d_lba (h2d_lba ),
.h2d_sector_count (h2d_sector_count ),
.d2h_interrupt (d2h_interrupt ),
.d2h_notification (d2h_notification ),
.d2h_status (d2h_status ),
.d2h_error (d2h_error ),
.d2h_port_mult (d2h_port_mult ),
.d2h_device (d2h_device ),
.d2h_lba (d2h_lba ),
.d2h_sector_count (d2h_sector_count ),
//command layer data interface
.cl_if_strobe (cl_if_strobe ),
.cl_if_data (cl_if_data ),
.cl_if_ready (cl_if_ready ),
.cl_if_activate (cl_if_activate ),
.cl_if_size (cl_if_size ),
.cl_of_strobe (cl_of_strobe ),
.cl_of_data (cl_of_data ),
.cl_of_ready (cl_of_ready ),
.cl_of_activate (cl_of_activate ),
.cl_of_size (cl_of_size ),
//Link Layer Interface
.link_layer_ready (ll_ready ),
.ll_write_start (t_write_start ),
.ll_write_strobe (t_write_strobe ),
.ll_write_finished (t_write_finished ),
.ll_write_data (t_write_data ),
.ll_write_size (t_write_size ),
.ll_write_hold (t_write_hold ),
.ll_write_abort (t_write_abort ),
.ll_xmit_error (t_xmit_error ),
.ll_read_start (t_read_start ),
.ll_read_ready (t_read_ready ),
.ll_read_data (t_read_data ),
.ll_read_strobe (t_read_strobe ),
.ll_read_finished (t_read_finished ),
.ll_read_crc_ok (t_read_crc_ok ),
.ll_remote_abort (t_remote_abort )
);
faux_hd_command_layer fcl(
.rst (rst || !hd_ready ),
.clk (clk ),
.command_layer_ready (command_layer_ready ),
.hd_read_from_host (hd_read_from_host ),
.hd_data_from_host (hd_data_from_host ),
.hd_write_to_host (hd_write_to_host ),
.hd_data_to_host (hd_data_to_host ),
.transport_layer_ready(transport_layer_ready ),
.send_reg_stb (cl_send_reg_stb ),
.send_dma_act_stb (cl_send_dma_act_stb ),
.send_data_stb (cl_send_data_stb ),
.send_pio_stb (cl_send_pio_stb ),
.send_dev_bits_stb (cl_send_dev_bits_stb ),
.remote_abort (remote_abort ),
.xmit_error (xmit_error ),
.read_crc_fail (read_crc_fail ),
.h2d_reg_stb (h2d_reg_stb ),
.h2d_data_stb (h2d_data_stb ),
.pio_request (pio_request ),
.pio_transfer_count (cl_pio_transfer_count ),
.pio_direction (cl_pio_direction ),
.pio_e_status (cl_pio_e_status ),
//FIS Structure
.h2d_command (h2d_command ),
.h2d_features (h2d_features ),
.h2d_cmd_bit (h2d_cmd_bit ),
.h2d_port_mult (h2d_port_mult ),
.h2d_control (h2d_control ),
.h2d_device (h2d_device ),
.h2d_lba (h2d_lba ),
.h2d_sector_count (h2d_sector_count ),
.d2h_interrupt (cl_d2h_interrupt ),
.d2h_notification (cl_d2h_notification ),
.d2h_status (cl_d2h_status ),
.d2h_error (cl_d2h_error ),
.d2h_port_mult (cl_d2h_port_mult ),
.d2h_device (cl_d2h_device ),
.d2h_lba (cl_d2h_lba ),
.d2h_sector_count (cl_d2h_sector_count ),
//command layer data interface
.cl_if_strobe (cl_if_strobe ),
.cl_if_data (if_data ),
.cl_if_ready (if_ready ),
.cl_if_activate (cl_if_activate ),
.cl_if_size (if_size ),
.cl_of_strobe (cl_of_strobe ),
.cl_of_data (cl_of_data ),
.cl_of_ready (of_ready ),
.cl_of_activate (cl_of_activate ),
.cl_of_size (of_size ),
.cl_state (cl_state )
);
assign tx_dout = !phy_ready ? phy_tx_dout : sll_tx_dout;
assign tx_is_k[3:1] = 3'b000;
assign tx_is_k[0] = !phy_ready ? phy_tx_is_k : sll_tx_is_k;
//Debug
//assign ll_write_start = (dbg_ll_en) ? dbg_ll_write_start : t_write_start;
//assign ll_write_data = (dbg_ll_en) ? dbg_ll_write_data : t_write_data;
//assign ll_write_hold = (dbg_ll_en) ? dbg_ll_write_hold : t_write_hold;
//assign ll_write_size = (dbg_ll_en) ? dbg_ll_write_size : t_write_size;
//assign ll_write_abort = (dbg_ll_en) ? dbg_ll_write_abort : t_write_abort;
//assign data_scrambler_en = (dbg_ll_en) ? dbg_data_scrambler_en : 1;
//
//assign ll_read_ready = (dbg_ll_en) ? dbg_ll_read_ready : t_read_ready;
//
assign ll_write_start = t_write_start;
assign ll_write_data = t_write_data;
assign ll_write_hold = t_write_hold;
assign ll_write_size = t_write_size;
assign ll_write_abort = t_write_abort;
assign data_scrambler_en = 1;
assign ll_read_ready = t_read_ready;
assign dbg_ll_write_strobe = ll_write_strobe;
assign dbg_ll_write_finished = ll_write_finished;
assign dbg_ll_xmit_error = xmit_error;
assign dbg_ll_read_strobe = ll_read_strobe;
assign dbg_ll_read_start = ll_read_start;
assign dbg_ll_read_finished = ll_read_finished;
assign dbg_ll_read_data = ll_read_data;
assign dbg_ll_remote_abort = ll_remote_abort;
//Transport Layer Debug Signals
assign dbg_tl_ready = transport_layer_ready;
assign t_read_strobe = ll_read_strobe;
assign t_read_start = ll_read_start;
assign t_read_finished = ll_read_finished;
assign t_read_data = ll_read_data;
assign t_remote_abort = ll_remote_abort;
assign t_read_crc_ok = ll_read_crc_ok;
assign t_write_strobe = ll_write_strobe;
assign t_write_finished = ll_write_finished;
assign send_reg_stb = (dbg_t_en) ? dbg_send_reg_stb : cl_send_reg_stb;
assign send_dma_act_stb = (dbg_t_en) ? dbg_send_dma_act_stb : cl_send_dma_act_stb;
assign send_data_stb = (dbg_t_en) ? dbg_send_data_stb : cl_send_data_stb;
assign send_pio_stb = (dbg_t_en) ? dbg_send_pio_stb : cl_send_pio_stb;
assign send_dev_bits_stb = (dbg_t_en) ? dbg_send_dev_bits_stb : cl_send_dev_bits_stb;
assign dbg_pio_request = pio_request;
assign pio_transfer_count = (dbg_t_en) ? dbg_pio_transfer_count : cl_pio_transfer_count;
assign pio_direction = (dbg_t_en) ? dbg_pio_direction : cl_pio_direction;
assign pio_e_status = (dbg_t_en) ? dbg_pio_e_status : cl_pio_e_status;
assign d2h_interrupt = (dbg_t_en) ? dbg_d2h_interrupt : cl_d2h_interrupt;
assign d2h_notification = (dbg_t_en) ? dbg_d2h_notification : cl_d2h_notification;
assign d2h_status = (dbg_t_en) ? dbg_d2h_status : cl_d2h_status;
assign d2h_error = (dbg_t_en) ? dbg_d2h_error : cl_d2h_error;
assign d2h_port_mult = (dbg_t_en) ? dbg_d2h_port_mult : cl_d2h_port_mult;
assign d2h_device = (dbg_t_en) ? dbg_d2h_device : cl_d2h_device;
assign d2h_lba = (dbg_t_en) ? dbg_d2h_lba : cl_d2h_lba;
assign d2h_sector_count = (dbg_t_en) ? dbg_d2h_sector_count : cl_d2h_sector_count;
assign cl_if_data = (dbg_t_en) ? dbg_cl_if_data : if_data;
assign cl_if_ready = (dbg_t_en) ? dbg_cl_if_ready : if_ready;
assign cl_if_size = (dbg_t_en) ? dbg_cl_if_size : if_size;
assign cl_of_ready = (dbg_t_en) ? dbg_cl_of_ready : of_ready;
assign cl_of_size = (dbg_t_en) ? dbg_cl_of_size : of_size;
assign dbg_remote_abort = remote_abort;
assign dbg_xmit_error = xmit_error;
assign dbg_read_crc_fail = read_crc_fail;
assign dbg_h2d_reg_stb = h2d_reg_stb;
assign dbg_h2d_data_stb = h2d_data_stb;
assign dbg_h2d_command = h2d_command;
assign dbg_h2d_features = h2d_features;
assign dbg_h2d_cmd_bit = h2d_cmd_bit;
assign dbg_h2d_port_mult = h2d_port_mult;
assign dbg_h2d_control = h2d_control;
assign dbg_h2d_device = h2d_device;
assign dbg_h2d_lba = h2d_lba;
assign dbg_h2d_sector_count = h2d_sector_count;
endmodule |
module faux_sata_hd_transport (
input rst, //reset
input clk,
//Trasport Layer Control/Status
output transport_layer_ready,
input send_reg_stb,
input send_dma_act_stb,
input send_data_stb,
input send_pio_stb,
input send_dev_bits_stb,
output reg remote_abort,
output reg xmit_error,
output reg read_crc_fail,
output reg h2d_reg_stb,
output reg h2d_data_stb,
output pio_request,
input [15:0] pio_transfer_count,
input pio_direction,
input [7:0] pio_e_status,
//Host to Device Registers
output reg [7:0] h2d_command,
output reg [15:0] h2d_features,
output reg h2d_cmd_bit,
output reg [7:0] h2d_control,
output reg [3:0] h2d_port_mult,
output reg [7:0] h2d_device,
output reg [47:0] h2d_lba,
output reg [15:0] h2d_sector_count,
//Device to Host Registers
input d2h_interrupt,
input d2h_notification,
input [3:0] d2h_port_mult,
input [7:0] d2h_device,
input [47:0] d2h_lba,
input [15:0] d2h_sector_count,
input [7:0] d2h_status,
input [7:0] d2h_error,
//DMA Specific Control
//Data Control
input cl_if_ready,
output reg cl_if_activate,
input [23:0] cl_if_size,
output cl_if_strobe,
input [31:0] cl_if_data,
input [1:0] cl_of_ready,
output reg [1:0] cl_of_activate,
output cl_of_strobe,
output [31:0] cl_of_data,
input [23:0] cl_of_size,
//Link Layer Interface
input link_layer_ready,
output reg ll_write_start,
input ll_write_strobe,
input ll_write_finished,
output [31:0] ll_write_data,
output [31:0] ll_write_size,
output ll_write_hold,
output ll_write_abort,
input ll_xmit_error,
input ll_read_start,
output ll_read_ready,
input [31:0] ll_read_data,
input ll_read_strobe,
input ll_read_finished,
input ll_read_crc_ok,
input ll_remote_abort
);
//Parameters
parameter IDLE = 4'h0;
parameter READ_FIS = 4'h1;
parameter WAIT_FOR_END = 4'h2;
parameter CHECK_FIS_TYPE = 4'h1;
parameter READ_H2D_REG = 4'h2;
parameter READ_DATA = 4'h3;
parameter WRITE_D2H_REG = 4'h4;
parameter WRITE_DEV_BITS = 4'h5;
parameter WRITE_PIO_SETUP = 4'h6;
parameter WRITE_DMA_ACTIVATE = 4'h7;
parameter WRITE_DMA_SETUP = 4'h8;
parameter SEND_DATA = 4'h9;
parameter RETRY = 4'hA;
//Registers/Wires
reg [3:0] state;
reg [3:0] next_state;
reg [3:0] fis_id_state;
reg [3:0] reg_read_count;
//Detect Wires
wire detect_h2d_reg;
wire detect_h2d_data;
reg send_data_fis_id;
reg detect_fis;
reg [7:0] current_fis;
//Control buffer
reg [7:0] d2h_write_ptr;
wire [31:0] d2h_reg_buffer [5:0];
wire [31:0] d2h_pio_setup [5:0];
wire [31:0] d2h_dev_bits [2:0];
wire [31:0] d2h_dma_act;
wire [31:0] d2h_data_fis_id;
//Submodules
//Asychronous Logic
assign transport_layer_ready = (state == IDLE) && link_layer_ready;
assign detect_h2d_reg = detect_fis ? (ll_read_data[7:0] == `FIS_H2D_REG) : (current_fis == `FIS_H2D_REG );
assign detect_h2d_data = detect_fis ? (ll_read_data[7:0] == `FIS_DATA) : (current_fis == `FIS_DATA );
//Device to host structural packets
assign d2h_reg_buffer[0] = {d2h_error, d2h_status, 1'b0, d2h_interrupt, 2'b00, d2h_port_mult, `FIS_D2H_REG};
assign d2h_reg_buffer[1] = {d2h_device, d2h_lba[23:0]};
assign d2h_reg_buffer[2] = {8'h00, d2h_lba[47:24]};
assign d2h_reg_buffer[3] = {16'h0000, d2h_sector_count};
assign d2h_reg_buffer[4] = 32'h0;
assign d2h_pio_setup[0] = {d2h_error, d2h_status, 1'b0, d2h_interrupt, pio_direction, 1'b0, d2h_port_mult, `FIS_PIO_SETUP};
assign d2h_pio_setup[1] = {d2h_device, d2h_lba[23:0]};
assign d2h_pio_setup[2] = {8'h00, d2h_lba[47:24]};
assign d2h_pio_setup[3] = {pio_e_status, 8'h00, d2h_sector_count};
assign d2h_pio_setup[4] = {16'h0000, pio_transfer_count};
assign d2h_dev_bits[0] = { d2h_error,
1'b0, d2h_status[6:4], 1'b0, d2h_status[2:0],
d2h_notification, d2h_interrupt, 2'b00, d2h_port_mult,
`FIS_SET_DEV_BITS};
assign d2h_dev_bits[1] = 32'h00000000;
assign d2h_dma_act = {8'h00, 8'h00, 4'h0, d2h_port_mult, `FIS_DMA_ACT};
assign d2h_data_fis_id = {8'h00, 8'h00, 4'h0, d2h_port_mult, `FIS_DATA};
//Link Layer Signals
//Write
assign ll_write_data = (send_data_fis_id) ? d2h_data_fis_id :
(state == SEND_DATA) ? cl_if_data :
((state == WRITE_D2H_REG) || send_reg_stb ) ? d2h_reg_buffer[d2h_write_ptr] :
((state == WRITE_DEV_BITS) || send_dev_bits_stb ) ? d2h_dev_bits[d2h_write_ptr] :
((state == WRITE_DMA_ACTIVATE)|| send_dma_act_stb ) ? d2h_dma_act :
((state == WRITE_PIO_SETUP) || send_pio_stb ) ? d2h_pio_setup[d2h_write_ptr] :
32'h00000000;
assign ll_write_size = (send_data_stb) ? cl_if_size + 1 :
(state == SEND_DATA) ? cl_if_size + 1 :
((state == WRITE_D2H_REG) || send_reg_stb ) ? `FIS_D2H_REG_SIZE :
((state == WRITE_DEV_BITS) || send_dev_bits_stb ) ? `FIS_SET_DEV_BITS_SIZE :
((state == WRITE_DMA_ACTIVATE) || send_dma_act_stb ) ? `FIS_DMA_ACT_SIZE :
((state == WRITE_PIO_SETUP) || send_pio_stb ) ? `FIS_PIO_SETUP_SIZE :
24'h000000;
assign ll_write_hold = (state == SEND_DATA) ? !cl_of_activate :
1'b0;
assign ll_write_abort = 1'b0;
assign cl_if_strobe = (state == SEND_DATA) ? ll_write_strobe : 0;
//Read
assign ll_read_ready = (state == READ_DATA) ? cl_of_activate :
1'b1;
assign cl_of_data = (state == READ_DATA) ? ll_read_data :
32'h00000000;
assign cl_of_strobe = (state == READ_DATA) ? ll_read_strobe :
1'b0;
//Synchronous Logic
//FIS ID State machine
always @ (posedge clk) begin
if (rst) begin
fis_id_state <= IDLE;
detect_fis <= 0;
current_fis <= 0;
end
else begin
//in order to set all the detect_* high when the actual fis is detected send this strobe
case (fis_id_state)
IDLE: begin
current_fis <= 0;
detect_fis <= 0;
if (ll_read_start) begin
detect_fis <= 1;
fis_id_state <= READ_FIS;
end
end
READ_FIS: begin
if (ll_read_strobe) begin
detect_fis <= 0;
current_fis <= ll_read_data[7:0];
fis_id_state <= WAIT_FOR_END;
end
end
WAIT_FOR_END: begin
if (ll_read_finished) begin
current_fis <= 0;
fis_id_state <= IDLE;
end
end
default: begin
fis_id_state <= IDLE;
end
endcase
end
end
//Main State machine
always @ (posedge clk) begin
if (rst) begin
state <= IDLE;
next_state <= IDLE;
d2h_write_ptr <= 0;
reg_read_count <= 0;
h2d_reg_stb <= 0;
h2d_data_stb <= 0;
h2d_command <= 0;
cl_of_activate <= 0;
//Link Layer Interface
ll_write_start <= 0;
send_data_fis_id <= 0;
h2d_command <= 0;
h2d_features <= 0;
h2d_cmd_bit <= 0;
h2d_control <= 0;
h2d_port_mult <= 0;
h2d_device <= 0;
h2d_lba <= 0;
h2d_sector_count <= 0;
cl_if_activate <= 0;
end
else begin
//Strobes
h2d_reg_stb <= 0;
h2d_data_stb <= 0;
ll_write_start <= 0;
xmit_error <= 0;
read_crc_fail <= 0;
//if there is any outptu buffers available
if ((cl_of_ready > 0) && (cl_of_activate == 0)) begin
if (cl_of_ready[0]) begin
cl_of_activate[0] <= 1;
end
else begin
cl_of_activate[1] <= 1;
end
end
//if there is any cl incomming buffers available grab it
if (cl_if_ready && !cl_if_activate) begin
cl_if_activate <= 1;
end
//Remote Abortion
if (ll_remote_abort) begin
state <= IDLE;
remote_abort <= 0;
end
if (ll_xmit_error) begin
xmit_error <= 1;
end
if (!ll_read_crc_ok) begin
read_crc_fail <= 1;
end
case (state)
IDLE: begin
d2h_write_ptr <= 0;
reg_read_count <= 0;
send_data_fis_id <= 0;
next_state <= IDLE;
//detect an incomming FIS
if (ll_read_start) begin
state <= CHECK_FIS_TYPE;
end
//Command Layer Initiated a transaction
if (link_layer_ready) begin
if (send_reg_stb) begin
ll_write_start <= 1;
state <= WRITE_D2H_REG;
end
else if (send_dev_bits_stb) begin
ll_write_start <= 1;
state <= WRITE_DEV_BITS;
end
else if (send_dma_act_stb) begin
ll_write_start <= 1;
state <= WRITE_DMA_ACTIVATE;
end
else if (send_pio_stb) begin
ll_write_start <= 1;
state <= WRITE_PIO_SETUP;
end
else if (send_data_stb) begin
ll_write_start <= 1;
send_data_fis_id <= 1;
state <= SEND_DATA;
end
end
end
CHECK_FIS_TYPE: begin
if (detect_h2d_reg) begin
h2d_features[7:0] <= ll_read_data[31:24];
h2d_command <= ll_read_data[23:16];
h2d_cmd_bit <= ll_read_data[15];
h2d_port_mult <= ll_read_data[11:8];
state <= READ_H2D_REG;
reg_read_count <= reg_read_count + 1;
end
else if (detect_h2d_data) begin
state <= READ_DATA;
end
if (ll_read_finished) begin
//unrecognized FIS
state <= IDLE;
end
end
READ_H2D_REG: begin
case (reg_read_count)
1: begin
h2d_device <= ll_read_data[31:24];
h2d_lba[23:0] <= ll_read_data[23:0];
end
2: begin
h2d_features[15:8] <= ll_read_data[31:24];
h2d_lba[47:24] <= ll_read_data[23:0];
end
3: begin
h2d_control <= ll_read_data[31:24];
h2d_sector_count <= ll_read_data[15:0];
end
4: begin
end
default: begin
end
endcase
if (ll_read_strobe) begin
reg_read_count <= reg_read_count + 1;
end
if (ll_read_finished) begin
h2d_reg_stb <= 1;
state <= IDLE;
end
end
READ_DATA: begin
//NOTE: the data_read_ready will automatically 'flow control' the data from the link layer
//so we don't have to check it here
//NOTE: We don't have to keep track of the count because the lower level will give a max of 2048 DWORDS
if (ll_read_finished) begin
h2d_data_stb <= 1;
cl_of_activate <= 0;
state <= IDLE;
end
end
WRITE_D2H_REG: begin
if (ll_write_strobe) begin
d2h_write_ptr <= d2h_write_ptr + 1;
end
if (ll_write_finished) begin
if (ll_xmit_error) begin
next_state <= state;
state <= RETRY;
end
else begin
state <= IDLE;
end
end
end
WRITE_DEV_BITS: begin
if (ll_write_strobe) begin
d2h_write_ptr <= d2h_write_ptr + 1;
end
if (ll_write_finished) begin
if (ll_xmit_error) begin
next_state <= state;
state <= RETRY;
end
else begin
state <= IDLE;
end
end
end
WRITE_PIO_SETUP: begin
if (ll_write_strobe) begin
d2h_write_ptr <= d2h_write_ptr + 1;
end
if (ll_write_finished) begin
if (ll_xmit_error) begin
next_state <= state;
state <= RETRY;
end
else begin
state <= IDLE;
end
end
end
WRITE_DMA_ACTIVATE: begin
if (ll_write_strobe) begin
d2h_write_ptr <= d2h_write_ptr + 1;
end
if (ll_write_finished) begin
if (ll_xmit_error) begin
next_state <= state;
state <= RETRY;
end
else begin
state <= IDLE;
end
end
end
WRITE_DMA_SETUP: begin
//XXX: not implemented yet
state <= IDLE;
end
SEND_DATA: begin
if (ll_write_strobe && send_data_fis_id) begin
send_data_fis_id <= 0;
end
if (ll_write_finished) begin
cl_if_activate <= 0;
state <= IDLE;
end
end
RETRY: begin
d2h_write_ptr <= 0;
reg_read_count <= 0;
if (link_layer_ready) begin
ll_write_start <= 1;
state <= next_state;
next_state <= IDLE;
end
end
default: begin
state <= IDLE;
end
endcase
end
end
endmodule |
module faux_sata_hd_phy (
//Inputs/Outputs
input rst, //reset
input clk,
//Data Interface
output reg [31:0] tx_dout,
output reg tx_is_k,
output reg tx_set_elec_idle,
output reg rx_byte_is_aligned,
input [31:0] rx_din,
input [3:0] rx_is_k,
input rx_is_elec_idle,
input comm_reset_detect,
input comm_wake_detect,
output reg tx_comm_reset,
output reg tx_comm_wake,
output [3:0] lax_state,
output reg hd_ready,
output phy_ready
);
//Parameters
parameter IDLE = 4'h0;
parameter WAIT_FOR_NO_RESET = 4'h1;
parameter SEND_INIT = 4'h2;
parameter WAIT_FOR_WAKE = 4'h3;
parameter WAIT_FOR_NO_WAKE = 4'h4;
parameter SEND_WAKE = 4'h5;
parameter STOP_SEND_WAKE = 4'h6;
parameter SEND_CONFIGURE_END = 4'h7;
parameter WAIT_FOR_DIALTONE = 4'h8;
parameter SEND_ALIGN = 4'h9;
parameter WAIT_FOR_ALIGN = 4'hA;
parameter READY = 4'hB;
parameter SEND_FIRST_ALIGNMENT = 4'hC;
parameter SEND_SECOND_ALIGNMENT = 4'hD;
parameter INITIALIZE_TIMEOUT = 100;
//Registers/Wires
reg [3:0] state = IDLE;
reg [31:0] timer;
reg [7:0] align_count;
wire align_detected;
wire dialtone_detected;
wire timeout;
//Sub Modules
//Asynchronous Logic
assign lax_state = state;
assign align_detected = ((rx_is_k > 0) && (rx_din == `PRIM_ALIGN));
assign dialtone_detected = ((rx_is_k == 0) && (rx_din == `DIALTONE));
assign timeout = (timer == 0);
assign phy_ready = (state == READY);
//Synchronous Logic
always @ (posedge clk) begin
if (rst) begin
state <= IDLE;
tx_dout <= 0;
tx_is_k <= 0;
tx_set_elec_idle <= 1;
timer <= 0;
hd_ready <= 0;
rx_byte_is_aligned <= 0;
align_count <= 0;
end
else begin
tx_comm_reset <= 0;
tx_comm_wake <= 0;
rx_byte_is_aligned <= 0;
if (state == READY) begin
align_count <= align_count + 1;
end
if (timer > 0) begin
timer <= timer - 1;
end
if ((comm_reset_detect) && (state > WAIT_FOR_NO_RESET)) begin
$display("faux_sata_hd: Asynchronous RESET detected");
align_count <= 0;
hd_ready <= 0;
state <= WAIT_FOR_NO_RESET;
end
case (state)
IDLE: begin
align_count <= 0;
hd_ready <= 0;
tx_set_elec_idle <= 1;
if (comm_reset_detect) begin
//detected a reset from the host
$display("faux_sata_hd: RESET detected");
state <= WAIT_FOR_NO_RESET;
end
end
WAIT_FOR_NO_RESET: begin
if (!comm_reset_detect) begin
//host stopped sending reset
$display("faux_sata_hd: RESET deasserted");
hd_ready <= 0;
state <= SEND_INIT;
end
end
SEND_INIT: begin
//XXX: I may need to send more than one of these
$display("faux_sata_hd: send INIT");
tx_comm_reset <= 1;
state <= WAIT_FOR_WAKE;
end
WAIT_FOR_WAKE: begin
if (comm_wake_detect) begin
$display ("faux_sata_hd: WAKE detected");
state <= WAIT_FOR_NO_WAKE;
end
end
WAIT_FOR_NO_WAKE: begin
if (!comm_wake_detect) begin
$display ("faux_sata_hd: WAKE deasserted");
state <= SEND_WAKE;
end
end
SEND_WAKE: begin
$display ("faux_sata_hd: send WAKE");
tx_comm_wake <= 1;
state <= STOP_SEND_WAKE;
end
STOP_SEND_WAKE: begin
$display ("faux_sata_hd: stop sending WAKE");
state <= WAIT_FOR_DIALTONE;
end
WAIT_FOR_DIALTONE: begin
if (dialtone_detected) begin
$display ("faux_sata_hd: detected dialtone");
state <= SEND_ALIGN;
end
end
SEND_ALIGN: begin
$display ("faux_sata_hd: send aligns");
tx_set_elec_idle <= 0;
tx_dout <= `PRIM_ALIGN;
tx_is_k <= 1;
state <= WAIT_FOR_ALIGN;
timer <= 32'h`INITIALIZE_TIMEOUT;
rx_byte_is_aligned <= 1;
end
WAIT_FOR_ALIGN: begin
tx_is_k <= 1;
tx_dout <= `PRIM_ALIGN;
rx_byte_is_aligned <= 1;
//$display ("faux_sata_hd: waiting for aligns...");
//$display ("rx din: %h, k: %h", rx_din, rx_is_k);
if (align_detected) begin
$display ("faux_sata_hd: detected ALIGN primitive from host");
$display ("faux_sata_hd: Ready");
tx_dout <= `PRIM_ALIGN;
tx_is_k <= 1;
timer <= 0;
state <= READY;
end
else if (timeout) begin
$display ("faux_sata_hd: Timeout while waiting for an alignment from the host");
state <= IDLE;
end
end
READY: begin
hd_ready <= 1;
rx_byte_is_aligned <= 1;
tx_is_k <= 1;
tx_dout <= `PRIM_SYNC;
if (align_count == 255) begin
tx_dout <= `PRIM_ALIGN;
state <= SEND_FIRST_ALIGNMENT;
end
end
SEND_FIRST_ALIGNMENT: begin
rx_byte_is_aligned <= 1;
tx_is_k <= 1;
tx_dout <= `PRIM_ALIGN;
state <= SEND_SECOND_ALIGNMENT;
end
SEND_SECOND_ALIGNMENT: begin
rx_byte_is_aligned <= 1;
tx_is_k <= 1;
tx_dout <= `PRIM_ALIGN;
state <= READY;
end
default: begin
$display ("faux_sata_hd: In undefined state!");
state <= IDLE;
end
endcase
end
end
endmodule |
module simple_tb ();
//Parameters
//Registers/Wires
reg rst = 0; //reset
reg clk = 0;
reg sata_clk = 0;
reg data_clk = 0;
wire command_layer_reset;
wire linkup; //link is finished
wire sata_ready;
wire sata_busy;
wire send_sync_escape;
wire hard_drive_error;
wire pio_data_ready;
reg soft_reset_en = 0;
reg [15:0] sector_count = 8;
reg [47:0] sector_address = 0;
reg [31:0] user_din;
reg user_din_stb;
wire [1:0] user_din_ready;
reg [1:0] user_din_activate;
wire [23:0] user_din_size;
wire [31:0] user_dout;
wire user_dout_ready;
reg user_dout_activate;
reg user_dout_stb;
wire [23:0] user_dout_size;
wire transport_layer_ready;
wire link_layer_ready;
wire phy_ready;
wire [31:0] tx_dout;
wire tx_is_k;
wire tx_comm_reset;
wire tx_comm_wake;
wire tx_elec_idle;
wire [31:0] rx_din;
wire [3:0] rx_is_k;
wire rx_elec_idle;
wire comm_init_detect;
wire comm_wake_detect;
wire rx_byte_is_aligned;
wire prim_scrambler_en;
wire data_scrambler_en;
//Data Interface
wire tx_set_elec_idle;
wire rx_is_elec_idle;
wire hd_ready;
wire platform_ready;
wire platform_error;
//Debug
wire [31:0] hd_data_to_host;
reg [23:0] din_count;
reg [23:0] dout_count;
reg hold = 0;
reg single_rdwr = 0;
reg [7:0] sata_command = 0;
reg [15:0] user_features = 0;
wire dma_activate_stb;
wire d2h_reg_stb;
wire pio_setup_stb;
wire d2h_data_stb;
wire dma_setup_stb;
wire set_device_bits_stb;
wire [7:0] d2h_fis;
wire d2h_interrupt;
wire d2h_notification;
wire [3:0] d2h_port_mult;
wire [7:0] d2h_device;
wire [47:0] d2h_lba;
wire [15:0] d2h_sector_count;
wire [7:0] d2h_status;
wire [7:0] d2h_error;
reg r_u2h_write_enable = 0;
reg r_h2u_read_enable = 0;
reg sata_execute_command_stb = 0;
wire [31:0] hd_data_from_host;
wire hd_read_from_host;
wire hd_write_to_host;
//hd data reader core
hd_data_reader user_2_hd_reader(
.clk (clk ),
.rst (rst ),
.enable (r_u2h_write_enable ),
.error (u2h_read_error ),
.hd_read_from_host (hd_read_from_host ),
.hd_data_from_host (hd_data_from_host )
);
//hd data writer core
hd_data_writer hd_2_user_generator(
.clk (clk ),
.rst (rst ),
.enable (r_h2u_read_enable ),
.data (hd_data_to_host ),
.strobe (hd_write_to_host )
);
//Submodules
sata_stack ss (
.clk (sata_clk ), //clock used to run the stack
.rst (rst ), //reset
.command_layer_reset (command_layer_reset ), //Reset the command layer and send a software reset to the hard drive
.platform_ready (platform_ready ), //the underlying physical platform is ready
.platform_error (platform_error ), //some bad thing happend at the transceiver level
.linkup (linkup ), //link is finished
.sata_ready (sata_ready ), //Hard drive is ready for commands
.sata_busy (sata_busy ), //Hard drive is busy executing commands
.send_sync_escape (send_sync_escape ), //This is a way to escape from a running transaction
.hard_drive_error (hard_drive_error ),
.pio_data_ready (pio_data_ready ), //Peripheral IO has some data ready
//Host to Device Control
.hard_drive_command (sata_command ), //Hard Drive commands EX: DMA Read 0x25, DMA Write 0x35
.execute_command_stb (sata_execute_command_stb),
.user_features (user_features ),
.sector_count (sector_count ),
.sector_address (sector_address ),
.dma_activate_stb (dma_activate_stb ),
.d2h_reg_stb (d2h_reg_stb ),
.pio_setup_stb (pio_setup_stb ),
.d2h_data_stb (d2h_data_stb ),
.dma_setup_stb (dma_setup_stb ),
.set_device_bits_stb (set_device_bits_stb ),
.d2h_fis (d2h_fis ),
.d2h_interrupt (d2h_interrupt ),
.d2h_notification (d2h_notification ),
.d2h_port_mult (d2h_port_mult ),
.d2h_device (d2h_device ),
.d2h_lba (d2h_lba ),
.d2h_sector_count (d2h_sector_count ),
.d2h_status (d2h_status ),
.d2h_error (d2h_error ),
//Data from host to the hard drive path
.data_in_clk (data_clk ), //Any clock to send data to the hard drive
.data_in_clk_valid (1'b1 ), //the data in clock is valid
.user_din (user_din ), //32-bit data to clock into FIFO
.user_din_stb (user_din_stb ), //Strobe to clock data into FIFO
.user_din_ready (user_din_ready ), //If one of the 2 in FIFOs are ready
.user_din_activate (user_din_activate ), //Activate one of the 2 FIFOs
.user_din_size (user_din_size ), //Number of available spots within the FIFO
.user_din_empty (user_din_empty ),
//Data from hard drive to host path
.data_out_clk (data_clk ),
.data_out_clk_valid (1'b1 ), //the data out clock is valid
.user_dout (user_dout ), //Actual data the comes from FIFO
.user_dout_ready (user_dout_ready ), //The output FIFO is ready (see below for how to use)
.user_dout_activate (user_dout_activate ), //Activate a FIFO (See below for an example on how to use)
.user_dout_stb (user_dout_stb ), //Strobe the data out of the FIFO (first word is available before strobe)
.user_dout_size (user_dout_size ), //Number of 32-bit words available
.transport_layer_ready (transport_layer_ready ),
.link_layer_ready (link_layer_ready ),
.phy_ready (phy_ready ), //sata phy layer has linked up and communication simple comm started
.phy_error (1'b0 ), //an error on the transcievers has occured
//Interface to the gigabit transcievers
.tx_dout (tx_dout ),
.tx_is_k (tx_is_k ),
.tx_comm_reset (tx_comm_reset ),
.tx_comm_wake (tx_comm_wake ),
.tx_elec_idle (tx_elec_idle ),
.tx_oob_complete (1'b1 ),
.rx_din (rx_din ),
.rx_is_k (rx_is_k ),
.rx_elec_idle (1'b0 ),
.rx_byte_is_aligned (rx_byte_is_aligned ),
.comm_init_detect (comm_init_detect ),
.comm_wake_detect (comm_wake_detect ),
//These should be set to 1 for normal operations, while debugging you can set to 0 to help debug things
.prim_scrambler_en (prim_scrambler_en ),
.data_scrambler_en (data_scrambler_en ),
.dbg_cc_lax_state ( ),
.dbg_cw_lax_state (command_write_state ),
.dbg_t_lax_state (transport_state ),
.dbg_li_lax_state ( ),
.dbg_lr_lax_state ( ),
.dbg_lw_lax_state (ll_write_state ),
.dbg_lw_lax_fstate ( ),
.dbg_ll_write_ready ( ),
.dbg_ll_paw ( ),
.dbg_ll_send_crc ( ),
.oob_state (oob_state ),
.dbg_detect_sync ( ),
.dbg_detect_r_rdy ( ),
.dbg_detect_r_ip ( ),
.dbg_detect_r_ok (dbg_detect_r_ok ),
.dbg_detect_r_err (dbg_detect_r_err ),
.dbg_detect_x_rdy ( ),
.dbg_detect_sof ( ),
.dbg_detect_eof ( ),
.dbg_detect_wtrm ( ),
.dbg_detect_cont ( ),
.dbg_detect_hold ( ),
.dbg_detect_holda ( ),
.dbg_detect_align ( ),
.dbg_detect_preq_s ( ),
.dbg_detect_preq_p ( ),
.dbg_detect_xrdy_xrdy ( ),
.dbg_send_holda ( ),
// .slw_in_data_addra (slw_in_data_addra ),
// .slw_d_count (slw_d_count ),
// .slw_write_count (slw_write_count ),
// .slw_buffer_pos (slw_buffer_pos )
.slw_in_data_addra ( ),
.slw_d_count ( ),
.slw_write_count ( ),
.slw_buffer_pos ( )
);
faux_sata_hd fshd (
.rst (rst ),
.clk (sata_clk ),
.tx_dout (rx_din ),
.tx_is_k (rx_is_k ),
.rx_din (tx_dout ),
.rx_is_k ({3'b000, tx_is_k} ),
.rx_is_elec_idle (tx_elec_idle ),
.rx_byte_is_aligned (rx_byte_is_aligned ),
.comm_reset_detect (tx_comm_reset ),
.comm_wake_detect (tx_comm_wake ),
.tx_comm_reset (comm_init_detect ),
.tx_comm_wake (comm_wake_detect ),
.hd_ready (hd_ready ),
// .phy_ready (phy_ready ),
.dbg_data_scrambler_en (data_scrambler_en ),
.dbg_hold (hold ),
.dbg_ll_write_start (0 ),
.dbg_ll_write_data (0 ),
.dbg_ll_write_size (0 ),
.dbg_ll_write_hold (0 ),
.dbg_ll_write_abort (0 ),
.dbg_ll_read_ready (0 ),
.dbg_t_en (0 ),
.dbg_send_reg_stb (0 ),
.dbg_send_dma_act_stb (0 ),
.dbg_send_data_stb (0 ),
.dbg_send_pio_stb (0 ),
.dbg_send_dev_bits_stb (0 ),
.dbg_pio_transfer_count(0 ),
.dbg_pio_direction (0 ),
.dbg_pio_e_status (0 ),
.dbg_d2h_interrupt (0 ),
.dbg_d2h_notification (0 ),
.dbg_d2h_status (0 ),
.dbg_d2h_error (0 ),
.dbg_d2h_port_mult (0 ),
.dbg_d2h_device (0 ),
.dbg_d2h_lba (0 ),
.dbg_d2h_sector_count (0 ),
.dbg_cl_if_data (0 ),
.dbg_cl_if_ready (0 ),
.dbg_cl_if_size (0 ),
.dbg_cl_of_ready (0 ),
.dbg_cl_of_size (0 ),
.hd_read_from_host (hd_read_from_host ),
.hd_data_from_host (hd_data_from_host ),
.hd_write_to_host (hd_write_to_host ),
.hd_data_to_host (hd_data_to_host )
);
//Asynchronous Logic
assign prim_scrambler_en = 1;
assign data_scrambler_en = 1;
assign platform_ready = 1;
//assign hd_data_to_host = 32'h01234567;
assign send_sync_escape = 1'b0;
assign command_layer_reset = 1'b0;
//Synchronous Logic
always #`SCLK_HALF_PERIOD sata_clk = ~sata_clk;
always #`DCLK_HALF_PERIOD data_clk = ~data_clk;
always #1 clk = ~clk;
//Simulation Control
initial begin
rst <= 1;
//$dumpfile ("design.vcd");
//$dumpvars(0, simple_tb);
#(20 * `SCLK_PERIOD);
rst <= 0;
//#(20 * `SCLK_PERIOD);
//$finish();
end
//Simulation Conditions
initial begin
sector_address <= 0;
sector_count <= 8;
single_rdwr <= 0;
sata_command <= 0;
user_features <= 0;
r_u2h_write_enable <= 0;
r_h2u_read_enable <= 0;
sata_execute_command_stb <= 0;
#(20 * `SCLK_PERIOD);
while (!linkup) begin
#(1 * `SCLK_PERIOD);
end
while (!sata_ready) begin
#(1 * `SCLK_PERIOD);
end
//Send a command
// #(700 * `SCLK_PERIOD);
//#(563 * `SCLK_PERIOD);
#(100 * `SCLK_PERIOD);
sata_command <= 8'h35; //Write
sector_count <= 1;
#(1 * `SCLK_PERIOD);
sata_execute_command_stb <= 1;
#(1 * `SCLK_PERIOD);
sata_execute_command_stb <= 0;
r_u2h_write_enable <= 1; //Read Data on the Hard Drive Side
#(1000 * `SCLK_PERIOD);
while (sata_busy) begin
#(1 * `SCLK_PERIOD);
end
#(100 * `SCLK_PERIOD);
r_u2h_write_enable <= 0;
//Put some data in the virtual hard drive
r_h2u_read_enable <= 1;
#(1000 * `SCLK_PERIOD);
sector_count <= 2;
sata_command <= 8'h25; //Read
#(1 * `SCLK_PERIOD);
sata_execute_command_stb <= 1;
#(1 * `SCLK_PERIOD);
sata_execute_command_stb <= 0;
#(1000 * `SCLK_PERIOD);
#(20 * `SCLK_PERIOD);
while (sata_busy) begin
#1;
end
r_h2u_read_enable <= 0;
//$finish();
end
/*
initial begin
hold <= 0;
#(20 * `SCLK_PERIOD);
while (!sata_busy) begin
#1;
end
#(800* `SCLK_PERIOD);
hold <= 1;
#(100 * `SCLK_PERIOD);
hold <= 0;
end
*/
/*
//inject a hold
initial begin
hold <= 0;
#(20 * `SCLK_PERIOD);
while (!write_data_en) begin
#1;
end
#(682 * `SCLK_PERIOD);
hold <= 1;
#(1 * `SCLK_PERIOD);
hold <= 0;
end
*/
/*
initial begin
sector_address <= 0;
sector_count <= 0;
#(20 * `SCLK_PERIOD);
while (!linkup) begin
#1;
end
while (busy) begin
#1;
end
//Send a command
#(824 * `SCLK_PERIOD);
write_data_en <= 1;
#(20 * `SCLK_PERIOD);
while (!busy) begin
#1;
end
write_data_en <= 0;
end
*/
//Buffer Fill/Drain
always @ (posedge data_clk) begin
if (rst) begin
user_din <= 0;
user_din_stb <= 0;
user_din_activate <= 0;
din_count <= 0;
user_dout_activate <= 0;
user_dout_stb <= 0;
dout_count <= 0;
end
else begin
user_din_stb <= 0;
user_dout_stb <= 0;
if ((user_din_ready > 0) && (user_din_activate == 0)) begin
din_count <= 0;
if (user_din_ready[0]) begin
user_din_activate[0] <= 1;
end
else begin
user_din_activate[1] <= 1;
end
end
if (din_count >= user_din_size) begin
user_din_activate <= 0;
end
else if (user_din_activate > 0) begin
user_din_stb <= 1;
user_din <= din_count;
din_count <= din_count + 1;
end
if (user_dout_ready && !user_dout_activate) begin
dout_count <= 0;
user_dout_activate <= 1;
end
if (dout_count >= user_dout_size) begin
user_dout_activate <= 0;
end
else if (user_dout_activate) begin
user_dout_stb <= 1;
end
end
end
endmodule |
module hd_data_reader (
input clk,
input rst,
input enable,
output reg error,
input hd_read_from_host,
input [31:0] hd_data_from_host
);
//Registers/Wires
reg prev_enable;
wire posedge_enable;
reg [31:0] test_data;
//Submodules
//Asynchronous Logic
assign posedge_enable = (!prev_enable && enable);
//Synchronous Logic
always @ (posedge clk) begin
if (rst) begin
prev_enable <= 0;
error <= 0;
test_data <= 0;
end
else begin
prev_enable <= enable;
if (posedge_enable) begin
error <= 0;
test_data <= 0;
end
else begin
if (hd_read_from_host) begin
if (hd_data_from_host != test_data) begin
error <= 1;
end
test_data <= test_data + 1;
end
end
end
end
endmodule |
module test_out (
input clk,
input rst,
input enable,
output reg busy,
output reg error,
input ready,
output reg activate,
input [23:0] size,
input [31:0] data,
output reg strobe,
output reg [23:0] total_count
);
reg [31:0] test_value;
reg [23:0] count;
always @ (posedge clk) begin
if (rst) begin
activate <= 0;
count <= 0;
test_value <= 32'h0;
error <= 0;
busy <= 0;
total_count <= 0;
strobe <= 0;
end
else begin
busy <= 0;
strobe <= 0;
//The user is not asking to check anything
if (!enable) begin
//activate <= 0;
//count <= 0;
test_value <= 32'h0;
error <= 0;
total_count <= 0;
end
//Looking for total count
//busy <= 1;
if (ready && !activate) begin
count <= 0;
activate <= 1;
end
else if (activate) begin
busy <= 1;
if (count < size) begin
strobe <= 1;
total_count <= total_count + 1;
count <= count + 1;
if ((data != test_value) && enable) begin
error <= 1;
end
end
else begin
activate <= 0;
end
end
if (strobe) begin
test_value <= test_value + 1;
end
end
end
endmodule |
module sata_transport_layer (
input rst, //reset
input clk,
input phy_ready,
//Transport Layer Control/Status
output transport_layer_ready,
input sync_escape,
output reg d2h_reg_stb,
output reg dma_activate_stb,
output reg d2h_data_stb,
output reg dma_setup_stb,
output reg pio_setup_stb,
output reg set_device_bits_stb,
output reg remote_abort,
output xmit_error,
output read_crc_error,
input send_command_stb,
input send_control_stb,
input send_data_stb,
//PIO
output reg pio_response,
output reg pio_direction,
output reg [15:0] pio_transfer_count,
output reg [7:0] pio_e_status,
//Host to Device Registers
input [7:0] h2d_command,
input [15:0] h2d_features,
input [7:0] h2d_control,
input [3:0] h2d_port_mult,
input [7:0] h2d_device,
input [47:0] h2d_lba,
input [15:0] h2d_sector_count,
//Device to Host Registers
output reg [7:0] d2h_fis,
output reg d2h_interrupt,
output reg d2h_notification,
output reg [3:0] d2h_port_mult,
output reg [7:0] d2h_device,
output reg [47:0] d2h_lba,
output reg [15:0] d2h_sector_count,
output reg [7:0] d2h_status,
output reg [7:0] d2h_error,
//DMA Specific Control
//Data Control
input cl_if_ready,
output reg cl_if_activate,
input [23:0] cl_if_size,
output cl_if_strobe,
input [31:0] cl_if_data,
input [1:0] cl_of_ready,
output reg [1:0] cl_of_activate,
output cl_of_strobe,
output [31:0] cl_of_data,
input [23:0] cl_of_size,
//Link Layer Interface
input link_layer_ready,
output ll_sync_escape,
output ll_write_start,
input ll_write_strobe,
input ll_write_finished,
output [31:0] ll_write_data,
output [23:0] ll_write_size,
output ll_write_hold,
output ll_write_abort,
input ll_xmit_error,
input ll_read_start,
output ll_read_ready,
input [31:0] ll_read_data,
input ll_read_strobe,
input ll_read_finished,
input ll_read_crc_ok,
input ll_remote_abort,
output [3:0] lax_state
);
//Parameters
parameter IDLE = 4'h0;
parameter READ_FIS = 4'h1;
parameter WAIT_FOR_END = 4'h2;
parameter CHECK_FIS_TYPE = 4'h1;
parameter WRITE_H2D_REG = 4'h2;
parameter RETRY = 4'h3;
parameter READ_D2H_REG = 4'h4;
parameter READ_PIO_SETUP = 4'h5;
parameter READ_SET_DEVICE_BITS = 4'h6;
parameter DMA_ACTIVATE = 4'h7;
parameter SEND_DATA = 4'h8;
parameter READ_DATA = 4'h9;
//Registers/Wires
reg [3:0] fis_id_state;
reg [7:0] current_fis;
reg [3:0] state;
reg detect_fis;
wire processing_fis;
//data direction
wire data_direction;
//Detect FIS from the device
wire detect_d2h_reg;
wire detect_dma_activate;
wire detect_dma_setup;
wire detect_d2h_data;
wire detect_pio_setup;
wire detect_set_device_bits;
//control data signals
wire [31:0] register_fis [5:0];
reg [7:0] register_fis_ptr;
reg cmd_bit;
reg reg_write_start;
wire [31:0] reg_write_data;
wire [23:0] reg_write_size;
reg reg_write_ready;
wire reg_write_hold;
wire reg_write_abort;
wire reg_write_strobe;
//read register
wire reg_read;
wire reg_write;
reg [7:0] reg_read_count;
wire reg_read_stb;
//data state machine signals
reg data_write_start;
wire data_write_strobe;
wire data_read_strobe;
wire [23:0] data_write_size;
wire [31:0] data_write_data;
wire data_write_hold;
wire data_write_abort;
reg data_read_ready;
reg send_data_fis_id;
reg ll_write_finished_en;
//Asnchronous Logic
assign lax_state = state;
assign transport_layer_ready = (state == IDLE) && link_layer_ready;
assign ll_sync_escape = sync_escape;
assign xmit_error = ll_xmit_error;
//Attach Control/Data Signals to link layer depending on the conditions
//Write Control
assign ll_write_start = (reg_write) ? reg_write_start : data_write_start;
assign ll_write_data = (reg_write) ? register_fis[register_fis_ptr] : data_write_data;
assign ll_write_size = (reg_write) ? reg_write_size : data_write_size;
assign ll_write_hold = (reg_write) ? 1'b0 : data_write_hold;
assign ll_write_abort = (reg_write) ? 1'b0 : data_write_abort;
assign cl_if_strobe = (reg_write) ? 1'b0 : (!send_data_fis_id && data_write_strobe);
//Read Control
assign ll_read_ready = (reg_read) ? 1'b1 : data_read_ready;
assign cl_of_strobe = (reg_read) ? 1'b0 : ((state == READ_DATA) && data_read_strobe);
assign cl_of_data = ll_read_data;
//Data Register Write Control Signals
assign data_write_data = (send_data_fis_id) ? {24'h000, `FIS_DATA} : cl_if_data;
//the first DWORD is the FIS ID
assign data_write_size = cl_if_size + 24'h1;
//Add 1 to the size so that there is room for the FIS ID
assign data_write_strobe = ll_write_strobe;
assign data_read_strobe = ll_read_strobe;
assign data_write_hold = 1'b0;
//There should never be a hold on the data becuase the CL will set it up
assign data_write_abort = 1'b0;
assign read_crc_error = !ll_read_crc_ok;
//H2D Register Write control signals
assign reg_write_strobe = ll_write_strobe;
assign reg_write_size = `FIS_H2D_REG_SIZE;
assign reg_write_hold = 1'b0;
assign reg_write_abort = 1'b0;
assign reg_write = (state == WRITE_H2D_REG) || (send_command_stb || send_control_stb);
//D2H Register Read control signals
assign reg_read = (state == READ_D2H_REG) || detect_d2h_reg ||
(state == READ_PIO_SETUP) || detect_pio_setup ||
(state == READ_SET_DEVICE_BITS) || detect_set_device_bits;
assign reg_read_stb = ll_read_strobe;
//Data Read control signals
//Detect Signals
assign processing_fis = (state == READ_FIS);
assign detect_d2h_reg = detect_fis ? (ll_read_data[7:0] == `FIS_D2H_REG) : (current_fis == `FIS_D2H_REG );
assign detect_dma_activate = detect_fis ? (ll_read_data[7:0] == `FIS_DMA_ACT) : (current_fis == `FIS_DMA_ACT );
assign detect_d2h_data = detect_fis ? (ll_read_data[7:0] == `FIS_DATA) : (current_fis == `FIS_DATA );
assign detect_dma_setup = detect_fis ? (ll_read_data[7:0] == `FIS_DMA_SETUP) : (current_fis == `FIS_DMA_SETUP );
assign detect_pio_setup = detect_fis ? (ll_read_data[7:0] == `FIS_PIO_SETUP) : (current_fis == `FIS_PIO_SETUP );
assign detect_set_device_bits = detect_fis ? (ll_read_data[7:0] == `FIS_SET_DEV_BITS) : (current_fis == `FIS_SET_DEV_BITS );
assign register_fis[0] = {h2d_features[7:0], h2d_command, cmd_bit, 3'b000, h2d_port_mult, `FIS_H2D_REG};
assign register_fis[1] = {h2d_device, h2d_lba[23:0]};
assign register_fis[2] = {h2d_features[15:8], h2d_lba[47:24]};
assign register_fis[3] = {h2d_control, 8'h00, h2d_sector_count};
assign register_fis[4] = {32'h00000000};
//Synchronous Logic
//FIS ID State machine
always @ (posedge clk) begin
if (rst) begin
fis_id_state <= IDLE;
detect_fis <= 0;
current_fis <= 0;
d2h_fis <= 0;
end
else begin
//in order to set all the detect_* high when the actual fis is detected send this strobe
if(ll_read_finished) begin
current_fis <= 0;
fis_id_state <= IDLE;
end
else begin
case (fis_id_state)
IDLE: begin
current_fis <= 0;
detect_fis <= 0;
if (ll_read_start) begin
detect_fis <= 1;
fis_id_state <= READ_FIS;
end
end
READ_FIS: begin
if (ll_read_strobe) begin
detect_fis <= 0;
current_fis <= ll_read_data[7:0];
d2h_fis <= ll_read_data[7:0];
fis_id_state <= WAIT_FOR_END;
end
end
WAIT_FOR_END: begin
if (ll_read_finished) begin
current_fis <= 0;
fis_id_state <= IDLE;
end
end
default: begin
fis_id_state <= IDLE;
end
endcase
end
end
end
//main DATA state machine
always @ (posedge clk) begin
if (rst) begin
state <= IDLE;
cl_of_activate <= 0;
cl_if_activate <= 0;
data_read_ready <= 0;
//Data Send
send_data_fis_id <= 0;
//H2D Register
register_fis_ptr <= 0;
reg_write_start <= 0;
//D2H Register
reg_read_count <= 0;
//Device Status
d2h_interrupt <= 0;
d2h_notification <= 0;
d2h_port_mult <= 0;
d2h_lba <= 0;
d2h_sector_count <= 0;
d2h_status <= 0;
d2h_error <= 0;
d2h_reg_stb <= 0;
d2h_data_stb <= 0;
pio_setup_stb <= 0;
set_device_bits_stb <= 0;
dma_activate_stb <= 0;
dma_setup_stb <= 0;
remote_abort <= 0;
cmd_bit <= 0;
//PIO
pio_transfer_count <= 0;
pio_e_status <= 0;
pio_direction <= 0;
pio_response <= 0;
data_write_start <= 0;
ll_write_finished_en <= 0;
end
else begin
//Strobed signals
if (phy_ready) begin
//only deassert a link layer strobe when Phy is ready and not sending aligns
data_write_start <= 0;
reg_write_start <= 0;
end
d2h_reg_stb <= 0;
d2h_data_stb <= 0;
pio_setup_stb <= 0;
set_device_bits_stb <= 0;
dma_activate_stb <= 0;
dma_setup_stb <= 0;
remote_abort <= 0;
d2h_device <= 0;
//Always attempt to get a free buffer
if ((cl_of_activate == 0) && (cl_of_ready > 0)) begin
if (cl_of_ready[0]) begin
cl_of_activate[0] <= 1;
end
else begin
cl_of_activate[1] <= 1;
end
data_read_ready <= 1;
end
else if (cl_of_activate == 0) begin
//XXX: NO BUFFER AVAILABLE!!!! Can't accept new data from the Hard Drive
data_read_ready <= 0;
end
//Always attempt to get the incomming buffer
if (cl_if_ready && !cl_if_activate) begin
cl_if_activate <= 1;
end
if (ll_write_finished) begin
ll_write_finished_en <= 1;
end
case (state)
IDLE: begin
register_fis_ptr <= 0;
reg_read_count <= 0;
cmd_bit <= 0;
ll_write_finished_en <= 0;
//Detect a FIS
if(ll_read_start) begin
//detect the start of a frame
state <= CHECK_FIS_TYPE;
//Clear Errors when a new transaction starts
end
//Send Register
if (send_command_stb || send_control_stb) begin
//Clear Errors when a new transaction starts
if (send_command_stb) begin
cmd_bit <= 1;
end
else if (send_control_stb) begin
cmd_bit <= 0;
end
reg_write_start <= 1;
state <= WRITE_H2D_REG;
end
//Send Data
else if (send_data_stb) begin
//Clear Errors when a new transaction starts
data_write_start <= 1;
send_data_fis_id <= 1;
state <= SEND_DATA;
end
end
CHECK_FIS_TYPE: begin
if (detect_dma_setup) begin
//XXX: Future work!
reg_read_count <= reg_read_count + 8'h1;
state <= IDLE;
end
else if (detect_dma_activate) begin
//hard drive is ready to receive data
state <= DMA_ACTIVATE;
reg_read_count <= reg_read_count + 8'h1;
//state <= IDLE;
end
else if (detect_d2h_data) begin
//incomming data, because the out FIFO is directly connected to the output during a read
state <= READ_DATA;
end
else if (detect_d2h_reg) begin
//store the error, status interrupt from this read
d2h_status <= ll_read_data[23:16];
d2h_error <= ll_read_data[31:24];
d2h_interrupt <= ll_read_data[14];
d2h_port_mult <= ll_read_data[11:8];
state <= READ_D2H_REG;
reg_read_count <= reg_read_count + 8'h1;
end
else if (detect_pio_setup) begin
//store the error, status, direction interrupt from this read
pio_response <= 1;
d2h_status <= ll_read_data[23:16];
d2h_error <= ll_read_data[31:24];
d2h_interrupt <= ll_read_data[14];
pio_direction <= ll_read_data[13];
d2h_port_mult <= ll_read_data[11:8];
state <= READ_PIO_SETUP;
reg_read_count <= reg_read_count + 8'h1;
end
else if (detect_set_device_bits) begin
//store the error, a subset of the status bit and the interrupt
state <= IDLE;
d2h_status[6:4] <= ll_read_data[22:20];
d2h_status[2:0] <= ll_read_data[18:16];
d2h_error <= ll_read_data[31:24];
d2h_notification <= ll_read_data[15];
d2h_interrupt <= ll_read_data[14];
d2h_port_mult <= ll_read_data[11:8];
state <= READ_SET_DEVICE_BITS;
end
else if (ll_read_finished) begin
//unrecognized FIS
state <= IDLE;
end
end
WRITE_H2D_REG: begin
if (register_fis_ptr < `FIS_H2D_REG_SIZE) begin
if (reg_write_strobe) begin
register_fis_ptr <= register_fis_ptr + 8'h1;
end
end
if (ll_write_finished_en) begin
if (ll_xmit_error) begin
state <= RETRY;
end
else begin
state <= IDLE;
end
end
end
RETRY: begin
if (link_layer_ready) begin
ll_write_finished_en <= 0;
reg_write_start <= 1;
register_fis_ptr <= 0;
state <= WRITE_H2D_REG;
end
end
READ_D2H_REG: begin
case (reg_read_count)
1: begin
d2h_device <= ll_read_data[31:24];
d2h_lba[23:0] <= ll_read_data[23:0];
end
2: begin
d2h_lba[47:24] <= ll_read_data[23:0];
end
3: begin
d2h_sector_count <= ll_read_data[15:0];
end
4: begin
end
default: begin
end
endcase
if (reg_read_stb) begin
reg_read_count <= reg_read_count + 8'h1;
end
if (ll_read_finished) begin
d2h_reg_stb <= 1;
state <= IDLE;
end
end
READ_PIO_SETUP: begin
case (reg_read_count)
1: begin
d2h_device <= ll_read_data[31:24];
d2h_lba[23:0] <= ll_read_data[23:0];
end
2: begin
d2h_lba[47:24] <= ll_read_data[23:0];
end
3: begin
d2h_sector_count <= ll_read_data[15:0];
pio_e_status <= ll_read_data[31:24];
end
4: begin
pio_transfer_count <= ll_read_data[15:0];
end
default: begin
end
endcase
if (reg_read_stb) begin
reg_read_count <= reg_read_count + 8'h1;
end
if (ll_read_finished) begin
pio_setup_stb <= 1;
state <= IDLE;
end
end
READ_SET_DEVICE_BITS: begin
state <= IDLE;
set_device_bits_stb <= 1;
end
DMA_ACTIVATE: begin
state <= IDLE;
dma_activate_stb <= 1;
end
SEND_DATA: begin
if (ll_write_strobe && send_data_fis_id) begin
send_data_fis_id <= 0;
end
if (ll_write_finished_en) begin
cl_if_activate <= 0;
state <= IDLE;
if (pio_response) begin
//write the end status to the status pin
d2h_status <= pio_e_status;
end
end
end
READ_DATA: begin
//NOTE: the data_read_ready will automatically 'flow control' the data from the link layer
//so we don't have to check it here
//NOTE: We don't have to keep track of the count because the lower level will give a max of 2048 DWORDS
if (ll_read_finished) begin
//deactivate FIFO
d2h_data_stb <= 1;
cl_of_activate <= 0;
state <= IDLE;
if (pio_response) begin
//write the end status to the status pin
d2h_status <= pio_e_status;
end
end
end
default: begin
state <= IDLE;
end
endcase
if (sync_escape) begin
state <= IDLE;
end
end
end
endmodule |
module sata_platform (
input rst,
input tx_comm_reset,
input tx_comm_wake,
output comm_init_detect,
output comm_wake_detect,
output rx_elec_idle,
input tx_elec_idle,
output rx_byte_is_aligned,
input [31:0] phy_tx_dout,
input phy_tx_isk,
output [31:0] phy_rx_din,
output [3:0] phy_rx_isk,
//Clock Interface
input mgtclk_in,
output reg cnt_rst,
output pll_locked,
output clk_75mhz,
output platform_ready,
output TXP0_OUT,
output TXN0_OUT,
input RXP0_IN,
input RXN0_IN,
output GTX115_TXP0_OUT,
output GTX115_TXN0_OUT,
input GTX115_RXP0_IN,
input GTX115_RXN0_IN
);
//Parameters
//Registers/Wires
//Submodules
//Asynchronous Logic
//Synchronous Logic
endmodule |
module sata_phy_layer (
input rst, //reset
input clk,
input platform_ready, //the underlying physical platform is
output platform_error,
output linkup, //link is finished
output [31:0] tx_dout,
output tx_is_k,
output tx_comm_reset,
output tx_comm_wake,
output tx_elec_idle,
input tx_oob_complete,
input [31:0] rx_din,
input [3:0] rx_is_k,
input rx_elec_idle,
input rx_byte_is_aligned,
input comm_init_detect,
input comm_wake_detect,
output phy_ready,
input phy_error,
output [3:0] lax_state
);
//Parameters
parameter NOT_READY = 4'h0;
parameter SEND_FIRST_ALIGN = 4'h1;
parameter SEND_SECOND_ALIGN = 4'h2;
parameter READY = 4'h3;
//Registers/Wires
reg [3:0] state;
reg [7:0] align_count;
//OOB Control
wire [31:0] oob_tx_dout;
wire oob_tx_is_k;
//Phy Control
wire [31:0] phy_tx_dout;
wire phy_tx_is_k;
//wire align_detected;
wire oob_platform_error;
reg phy_platform_error;
//Submodules
oob_controller oob (
.rst (rst ),
.clk (clk ),
//OOB controller
.phy_error (phy_error ),
.platform_ready (platform_ready ),
.platform_error (oob_platform_error ),
.linkup (linkup ),
//Platform Control
.tx_dout (oob_tx_dout ),
.tx_is_k (oob_tx_is_k ),
.tx_comm_reset (tx_comm_reset ),
.tx_comm_wake (tx_comm_wake ),
.tx_set_elec_idle (tx_elec_idle ),
.tx_oob_complete (tx_oob_complete ),
.rx_din (rx_din ),
.rx_is_k (rx_is_k ),
.comm_init_detect (comm_init_detect ),
.comm_wake_detect (comm_wake_detect ),
.rx_is_elec_idle (rx_elec_idle ),
.rx_byte_is_aligned (rx_byte_is_aligned ),
.lax_state (lax_state )
);
//Asynchronous Logic
assign tx_dout = !linkup ? oob_tx_dout : phy_tx_dout;
assign tx_is_k = !linkup ? oob_tx_is_k : phy_tx_is_k;
assign phy_tx_dout = `PRIM_ALIGN;
assign phy_tx_is_k = 1;
//assign align_detected = ((rx_is_k > 0) && (rx_din == `PRIM_ALIGN) && !phy_error);
//assign phy_ready = ((state == READY) && (!align_detected));
assign phy_ready = (state == READY);
assign platform_error = oob_platform_error || phy_platform_error;
//Synchronous Logic
always @ (posedge clk) begin
if (rst) begin
state <= NOT_READY;
align_count <= 0;
phy_platform_error<= 0;
end
else begin
if (state == READY) begin
align_count <= align_count + 8'h01;
end
case (state)
NOT_READY: begin
align_count <= 0;
phy_platform_error <= 0;
if (linkup) begin
`ifdef VERBOSE
$display ("sata_phy_layer: linkup! send aligns");
`endif
state <= SEND_FIRST_ALIGN;
end
end
SEND_FIRST_ALIGN: begin
state <= SEND_SECOND_ALIGN;
end
SEND_SECOND_ALIGN: begin
state <= READY;
end
READY: begin
if (align_count == 255) begin
state <= SEND_FIRST_ALIGN;
`ifdef VERBOSE
$display ("sata_phy_layer: linkup! send alignment dwords");
`endif
end
if (phy_error) begin
phy_platform_error <= 1;
end
end
default: begin
end
endcase
end
end
endmodule |
module oob_controller (
input rst, //reset
input clk,
input platform_ready, //the underlying physical platform is
output reg platform_error, //Underlyaing physal platform received an error, this should probably be a reset
output reg linkup, //link is finished
output reg tx_comm_reset, //send a init OOB signal
output reg tx_comm_wake, //send a wake OOB signal
input tx_oob_complete, //Phy has said we are finished with this OOB transaction
input comm_init_detect, //detected an init
input comm_wake_detect, //detected a wake on the rx lines
input [31:0] rx_din,
input [3:0] rx_is_k,
input rx_is_elec_idle,
input rx_byte_is_aligned,
input phy_error,
output reg [31:0] tx_dout,
output reg tx_is_k,
output reg tx_set_elec_idle,
output [3:0] lax_state
);
//platform signals
//Parameters
//States
parameter IDLE = 4'h0;
parameter SEND_RESET = 4'h1;
parameter WAIT_FOR_INIT = 4'h2;
parameter WAIT_FOR_NO_INIT = 4'h3;
parameter WAIT_FOR_CONFIGURE_END = 4'h4;
parameter SEND_WAKE = 4'h5;
parameter WAIT_FOR_WAKE = 4'h6;
parameter WAIT_FOR_NO_WAKE = 4'h7;
parameter WAIT_FOR_IDLE = 4'h8;
parameter WAIT_FOR_ALIGN = 4'h9;
parameter SEND_ALIGN = 4'hA;
parameter DETECT_SYNC = 4'hB;
parameter READY = 4'hC;
//Registers/Wires
reg [3:0] state;
reg [31:0] timer;
reg [1:0] no_align_count;
reg [3:0] retries;
//timer used to send 'INITs', WAKEs' and read them
wire timeout;
wire align_detected;
wire sync_detected;
//Submodules
//Asynchronous Logic
assign timeout = (timer == 0);
//assign align_detected = ((rx_is_k > 0) && (rx_din == `PRIM_ALIGN) && !phy_error);
//assign align_detected = ((rx_is_k > 0) && (rx_din == `PRIM_ALIGN));
assign align_detected = ((rx_is_k > 0) && (rx_din == `PRIM_ALIGN) && rx_byte_is_aligned);
assign sync_detected = ((rx_is_k > 0) && (rx_din == `PRIM_SYNC));
assign lax_state = state;
//Synchronous Logic
initial begin
tx_set_elec_idle <= 1;
end
always @ (posedge clk) begin
if (rst) begin
state <= IDLE;
linkup <= 0;
timer <= 0;
tx_comm_reset <= 0;
tx_comm_wake <= 0;
tx_dout <= 0;
tx_is_k <= 0;
tx_set_elec_idle <= 1;
no_align_count <= 0;
platform_error <= 0;
retries <= 0;
end
else begin
//to support strobes, continuously reset the following signals
tx_comm_reset <= 0;
tx_comm_wake <= 0;
tx_is_k <= 0;
//timer (when reache 0 timeout has occured)
if (timer > 0) begin
timer <= timer - 1;
end
//main state machine, if this reaches ready an initialization sequence has completed
case (state)
IDLE: begin
platform_error <= 0;
linkup <= 0;
tx_set_elec_idle <= 1;
if (platform_ready) begin
$display ("oob_controller: send RESET");
//the platform is ready
// PLL has locked onto a clock
// DCM has generated the correct clocks
timer <= 32'h000000A2;
state <= SEND_RESET;
tx_comm_reset <= 1;
end
end
SEND_RESET: begin
//XXX: In the groundhog COMM RESET was continuously issued for a long period of time
//send the INIT sequence, this will initiate a communication with the
//SATA hard drive, or reset it so that it can be initiated to state
//strobe the comm init so that the platform will send an INIT OOB signal
if (timeout || tx_oob_complete) begin
timer <= `INITIALIZE_TIMEOUT;
state <= WAIT_FOR_INIT;
$display ("oob_controller: wait for INIT");
end
end
WAIT_FOR_INIT: begin
//wait for a response from the SATA harddrive, if the timeout occurs
//go back to the SEND_RESET state
if (comm_init_detect) begin
//HD said 'sup' go to a wake
//timer <= 0;
timer <= 32'h00001000;
state <= WAIT_FOR_NO_INIT;
$display ("oob_controller: wait for INIT to go low");
end
if (timeout) begin
$display ("oob_controller: timed out while waiting for INIT");
state <= IDLE;
end
end
WAIT_FOR_NO_INIT: begin
//wait for the init signal to go low from the device
if (!comm_init_detect && (timeout || tx_oob_complete)) begin
$display ("oob_controller: INIT deasserted");
$display ("oob_controller: start configuration");
state <= WAIT_FOR_CONFIGURE_END;
end
end
WAIT_FOR_CONFIGURE_END: begin
$display ("oob_controller: System is configured");
state <= SEND_WAKE;
timer <= 32'h0000009B;
tx_comm_wake <= 1;
//end
end
SEND_WAKE: begin
//XXX: In the groundhog COMM WAKE was continuously send for a long period of time
//Send the WAKE sequence to the hard drive to initiate a wakeup sequence
//XXX: Is this timeout correct?
//880uS
if (timeout || tx_oob_complete) begin
//timer <= 32'd`INITIALIZE_TIMEOUT;
timer <= 32'h000203AD;
state <= WAIT_FOR_WAKE;
end
end
WAIT_FOR_WAKE: begin
//Wait for the device to send a COMM Wake
if (comm_wake_detect) begin
//Found a comm wake, now wait for the device to stop sending WAKE
timer <= 0;
state <= WAIT_FOR_NO_WAKE;
$display ("oob_controller: WAKE detected");
end
if (timeout) begin
//Timeout occured before reading WAKE
state <= IDLE;
$display ("oob_controller: timed out while waiting for WAKE to be asserted");
end
end
WAIT_FOR_NO_WAKE: begin
if (!comm_wake_detect) begin
//The device stopped sending comm wake
//XXX: Is this timeout correct?
//880uS
$display ("oob_controller: detected WAKE deasserted");
$display ("oob_controller: Send Dialtone, wait for ALIGN");
//Going to add more timeout
//timer <= 32'h0203AD;
timer <= 32'h0203AD;
state <= WAIT_FOR_ALIGN;
//state <= WAIT_FOR_IDLE;
retries <= 4;
end
end
/*
WAIT_FOR_IDLE: begin
if (!rx_is_elec_idle) begin
state <= WAIT_FOR_ALIGN;
timer <= 32'h0101D0;
end
else if (timeout) begin
if (retries > 0) begin
timer <= 32'h0203AD;
retries <= retries - 1;
end
if (retries == 0) begin
state <= IDLE;
end
end
end
*/
WAIT_FOR_ALIGN: begin
//transmit the 'dialtone' continuously
//since we need to start sending actual data (not OOB signals, get out
// of tx idle)
tx_set_elec_idle <= 0;
//a sequence of 0's and 1's
tx_dout <= `DIALTONE;
tx_is_k <= 0;
//$display ("rx din: %h, k: %h", rx_din, rx_is_k);
if (align_detected) begin
//we got something from the device!
timer <= 0;
//now send an align from my side
state <= SEND_ALIGN;
no_align_count <= 0;
$display ("oob_controller: ALIGN detected");
$display ("oob_controller: Send out my ALIGNs");
end
if (timeout) begin
//didn't read an align in time :( reset
$display ("oob_controller: timed out while waiting for AIGN");
state <= IDLE;
end
end
SEND_ALIGN: begin
tx_dout <= `PRIM_ALIGN;
tx_is_k <= 1;
if (!align_detected) begin
$display ("oob_controller: detected ALIGN deasserted");
//XXX: Groundhog detects the SYNC primitve before declaring linkup
if (no_align_count == 3) begin
$display ("oob_controller: ready");
state <= READY;
end
else begin
no_align_count <= no_align_count + 2'b01;
end
end
end
DETECT_SYNC: begin
if (sync_detected) begin
state <= READY;
end
end
READY: begin
linkup <= 1;
/*
if (phy_error) begin
platform_error <= 1;
end
*/
if (comm_init_detect) begin
state <= IDLE;
end
end
default: begin
state <= IDLE;
end
endcase
end
end
endmodule |
module sata_link_layer (
input rst, //reset
input clk,
//Command Interface
output link_layer_ready,
input sync_escape,
output post_align_write,
input hold,
//Phy Layer
input phy_ready,
output write_ready,
input platform_ready,
//XXX: I probably need some feedback to indicate that there is room to write
output [31:0] tx_dout,
output tx_is_k,
input [31:0] rx_din,
input [3:0] rx_is_k,
input write_start,
output write_strobe,
input [31:0] write_data,
input [23:0] write_size,
input write_hold,
output write_finished,
input write_abort,
output read_start,
output read_strobe,
output [31:0] read_data,
input read_ready,
output read_finished,
output read_crc_ok,
output remote_abort,
output xmit_error,
output wsize_z_error,
input prim_scrambler_en,
input data_scrambler_en,
input is_device,
output [3:0] lax_i_state,
output [3:0] lax_r_state,
output [3:0] lax_w_state,
output [3:0] lax_w_fstate,
//Detection
output detect_sync,
output detect_r_rdy,
output detect_r_ip,
output detect_r_ok,
output detect_r_err,
output detect_x_rdy,
output detect_sof,
output detect_eof,
output detect_wtrm,
output detect_cont,
output detect_hold,
output detect_holda,
output detect_align,
output detect_preq_s,
output detect_preq_p,
output detect_xrdy_xrdy,
output send_crc,
output dbg_send_holda,
output [23:0] in_data_addra,
output [12:0] d_count,
output [12:0] write_count,
output [3:0] buffer_pos
);
//Parameters
parameter NOT_READY = 4'h0;
parameter IDLE = 4'h1;
parameter PM_DENY = 4'h2;
//Registers/Wires
reg [3:0] state;
//Primatives
reg send_sync;
reg send_pmack;
reg send_pmnack;
wire sli_idle;
wire [31:0] sli_tx_dout;
wire sli_tx_is_k;
reg write_en;
wire write_idle;
wire [31:0] slw_tx_dout;
wire slw_tx_is_k;
reg read_en;
wire read_idle;
wire [31:0] slr_tx_dout;
wire slr_tx_is_k;
wire [31:0] ll_tx_dout;
wire ll_tx_is_k;
wire last_prim;
//Submodules
//XXX: I can probably use only one CRC checker for the entire stack but to make it easier I'm gonna use two for
//the read and write path
//XXX: maybe add a scrambler for PRIM scrambling
cont_controller ccon (
.rst (rst ),
.clk (clk ),
.phy_ready (phy_ready ),
.xmit_cont_en (prim_scrambler_en ),
.last_prim (last_prim ),
.rx_din (rx_din ),
.rx_is_k (rx_is_k ),
.ll_tx_din (ll_tx_dout ),
.ll_tx_is_k (ll_tx_is_k ),
.cont_tx_dout (tx_dout ),
.cont_tx_is_k (tx_is_k ),
.detect_sync (detect_sync ),
.detect_r_rdy (detect_r_rdy ),
.detect_r_ip (detect_r_ip ),
.detect_r_err (detect_r_err ),
.detect_r_ok (detect_r_ok ),
.detect_x_rdy (detect_x_rdy ),
.detect_sof (detect_sof ),
.detect_eof (detect_eof ),
.detect_wtrm (detect_wtrm ),
.detect_cont (detect_cont ),
.detect_hold (detect_hold ),
.detect_holda (detect_holda ),
.detect_preq_s (detect_preq_s ),
.detect_preq_p (detect_preq_p ),
.detect_align (detect_align ),
.detect_xrdy_xrdy (detect_xrdy_xrdy )
);
sata_link_layer_write slw (
.rst (rst ),
.clk (clk ),
.en (write_en ),
.idle (write_idle ),
.phy_ready (phy_ready ),
.write_ready (write_ready ),
.send_sync_escape (sync_escape ),
.detect_x_rdy (detect_x_rdy ),
.detect_r_rdy (detect_r_rdy ),
.detect_r_ip (detect_r_ip ),
.detect_r_err (detect_r_err ),
.detect_r_ok (detect_r_ok ),
.detect_cont (detect_cont ),
.detect_hold (detect_hold ),
.detect_holda (detect_holda ),
.detect_sync (detect_sync ),
.detect_align (detect_align ),
.send_holda (dbg_send_holda ),
.write_start (write_start ),
.write_strobe (write_strobe ),
.write_data (write_data ),
.write_size (write_size ),
.write_hold (write_hold ),
.write_finished (write_finished ),
.write_abort (write_abort ),
.last_prim (last_prim ),
.send_crc (send_crc ),
.post_align_write (post_align_write ),
.tx_dout (slw_tx_dout ),
.tx_is_k (slw_tx_is_k ),
.rx_din (rx_din ),
.rx_is_k (rx_is_k ),
.xmit_error (xmit_error ),
.wsize_z_error (wsize_z_error ),
.data_scrambler_en (data_scrambler_en ),
.is_device (is_device ),
.state (lax_w_state ),
.fstate (lax_w_fstate ),
.in_data_addra (in_data_addra ),
.write_count (write_count ),
.d_count (d_count ),
.buffer_pos (buffer_pos )
);
sata_link_layer_read slr (
.rst (rst ),
.clk (clk ),
.en (read_en ),
.idle (read_idle ),
.sync_escape (sync_escape ),
.phy_ready (phy_ready ),
.dbg_hold (hold ),
.detect_align (detect_align ),
.detect_sync (detect_sync ),
.detect_x_rdy (detect_x_rdy ),
.detect_sof (detect_sof ),
.detect_eof (detect_eof ),
.detect_wtrm (detect_wtrm ),
.detect_cont (detect_cont ),
.detect_holda (detect_holda ),
.detect_hold (detect_hold ),
.detect_xrdy_xrdy (detect_xrdy_xrdy ),
.tx_dout (slr_tx_dout ),
.tx_is_k (slr_tx_is_k ),
.rx_din (rx_din ),
.rx_is_k (rx_is_k ),
.read_ready (read_ready ),
.read_strobe (read_strobe ),
.read_data (read_data ),
.read_start (read_start ),
.read_finished (read_finished ),
.remote_abort (remote_abort ),
.crc_ok (read_crc_ok ),
.data_scrambler_en (data_scrambler_en ),
.is_device (is_device ),
.lax_r_state (lax_r_state )
);
//Asynchronous logic
assign ll_tx_dout = (!read_idle) ? slr_tx_dout : (!write_idle) ? slw_tx_dout : sli_tx_dout;
assign ll_tx_is_k = (!read_idle) ? slr_tx_is_k : (!write_idle) ? slw_tx_is_k : sli_tx_is_k;
assign sli_tx_dout = (send_pmnack) ? `PRIM_PMNACK :
(send_pmack) ? `PRIM_PMACK :
`PRIM_SYNC;
assign sli_tx_is_k = 1;
assign link_layer_ready = (state == IDLE) && read_idle && write_idle;
assign lax_i_state = state;
//Main State Machine
always @ (posedge clk) begin
if (rst) begin
state <= NOT_READY;
send_pmnack <= 0;
send_pmack <= 0;
write_en <= 0;
read_en <= 0;
end
else begin
//Strobes
send_pmnack <= 0;
send_pmack <= 0;
write_en <= 0;
read_en <= 0;
if (!platform_ready) begin
state <= NOT_READY;
end
if (phy_ready) begin
case (state)
NOT_READY: begin
if (platform_ready) begin
state <= IDLE;
end
end
IDLE: begin
write_en <= 1;
read_en <= 1;
if (detect_preq_s || detect_preq_p) begin
send_pmnack <= 1;
state <= PM_DENY;
end
end
PM_DENY: begin
if (detect_preq_s || detect_preq_p) begin
send_pmnack <= 1;
end
else begin
state <= IDLE;
end
end
default: begin
state <= NOT_READY;
end
endcase
end
end
end
endmodule |
module sata_link_layer_read (
input rst, //reset
input clk,
input phy_ready,
input en,
output idle,
input sync_escape,
input dbg_hold,
input detect_align,
input detect_sync,
input detect_x_rdy,
input detect_sof,
input detect_eof,
input detect_wtrm,
input detect_holda,
input detect_hold,
input detect_cont,
input detect_xrdy_xrdy,
output [31:0] tx_dout,
output tx_is_k,
input [31:0] rx_din,
input [3:0] rx_is_k,
output reg read_strobe,
output reg [31:0] read_data,
input read_ready,
output read_start,
output read_finished,
output reg remote_abort,
output reg crc_ok,
// output wire crc_ok,
input data_scrambler_en,
input is_device,
output [3:0] lax_r_state
);
//Primatives
parameter IDLE = 4'h0;
parameter READ_START = 4'h1;
parameter READ = 4'h2;
parameter READ_END = 4'h3;
parameter SEND_STATUS = 4'h4;
//Registers/Wires
reg [3:0] state;
reg send_r_rdy;
reg send_r_ip;
reg send_r_err;
reg send_r_ok;
reg send_hold;
reg send_holda;
reg send_sync;
//CRC
//XXX: Tie the CRC_EN to an incomming data dword
wire [31:0] crc_din;
reg [31:0] prev_crc;
reg [31:0] prev_data;
wire data_valid;
reg first_dword;
//Descrambler
wire descr_en;
wire [31:0] descr_din;
wire [31:0] descr_dout;
//SubModules
scrambler descr (
.rst (rst || idle),
.clk (clk ),
.prim_scrambler (1'b0 ),
.en (descr_en ),
.din (rx_din ),
.dout (descr_dout )
);
//Asynchronous Logic
assign idle = (state == IDLE);
assign tx_dout = (send_r_rdy) ? `PRIM_R_RDY :
(send_r_ip) ? `PRIM_R_IP :
(send_r_err) ? `PRIM_R_ERR :
(send_r_ok) ? `PRIM_R_OK :
(send_hold) ? `PRIM_HOLD :
(send_sync) ? `PRIM_SYNC :
(send_holda) ? `PRIM_HOLDA :
`PRIM_SYNC;
assign tx_is_k = ( send_r_rdy ||
send_r_ip ||
send_r_err ||
send_r_ok ||
send_hold ||
send_holda ||
send_sync);
assign crc_din = (data_scrambler_en) ? descr_dout : rx_din;
//assign read_data = (read_strobe) ? rx_din : 32'h0;
assign read_finished = detect_eof;
assign read_start = detect_sof;
assign data_valid = (state == READ) &&
(rx_is_k == 0) &&
(!detect_hold) &&
(!detect_holda) &&
(!detect_align);
assign descr_en = (data_scrambler_en && (detect_sof || data_valid));
assign descr_din = (data_valid) ? rx_din : 32'h00000000;
//assign crc_ok = (prev_data == prev_crc);
assign lax_r_state = state;
//Synchronous Logic
always @ (posedge clk) begin
if (rst) begin
state <= IDLE;
send_r_rdy <= 0;
send_r_ip <= 0;
send_r_err <= 0;
send_r_ok <= 0;
send_hold <= 0;
send_holda <= 0;
send_sync <= 0;
crc_ok <= 0;
prev_crc <= 0;
prev_data <= 0;
read_data <= 0;
read_strobe <= 0;
first_dword <= 0;
remote_abort <= 0;
end
else begin
read_strobe <= 0;
remote_abort <= 0;
if (phy_ready) begin
send_r_rdy <= 0;
send_r_ip <= 0;
send_r_err <= 0;
send_r_ok <= 0;
send_hold <= 0;
send_sync <= 0;
send_holda <= 0;
end
case (state)
IDLE: begin
read_data <= 0;
send_sync <= 1;
if (!detect_align) begin
crc_ok <= 0;
prev_crc <= 0;
prev_data <= 0;
if (detect_x_rdy) begin
if (detect_xrdy_xrdy) begin
if (!is_device) begin
if (read_ready || sync_escape) begin
//Transport is ready
if (phy_ready) begin
send_r_rdy <= 1;
state <= READ_START;
end
end
end
end
else begin
if (read_ready || sync_escape) begin
//Transport is ready
//XXX: I think this is okay because remote will continue to send X_RDY Primative
if (phy_ready) begin
send_r_rdy <= 1;
state <= READ_START;
end
end
end
// else begin
// //Transport Read is not ready
// send_sync <= 1;
// end
end
end
end
READ_START: begin
//wait for a start of frame
send_r_rdy <= 1;
if (detect_sync) begin
remote_abort <= 1;
state <= IDLE;
end
else if (detect_sof) begin
state <= READ;
send_r_ip <= 1;
first_dword <= 1;
end
end
READ: begin
if (sync_escape) begin
send_sync <= 1;
if (detect_sync) begin
state <= IDLE;
end
end
else begin
if (detect_eof) begin
//check the CRC
state <= READ_END;
send_r_ip <= 1;
//if (prev_data == prev_crc) begin
if (prev_data == prev_crc) begin
crc_ok <= 1;
end
end
else begin
if (detect_sync) begin
remote_abort <= 1;
state <= IDLE;
end
else if (!read_ready || dbg_hold) begin
//we should still have 20 DWORD of data to write
send_hold <= 1;
end
else if (detect_hold) begin
send_holda <= 1;
end
else begin
send_r_ip <= 1;
end
end
if (data_valid) begin
if (first_dword) begin
first_dword <= 0;
end
else begin
read_strobe <= 1;
end
read_data <= prev_data;
if (data_scrambler_en) begin
prev_data <= descr_dout;
end
else begin
prev_data <= rx_din;
end
prev_crc <= crc_din;
end
end
//put data into the incomming buffer
//check to see if we have enough room for 20 more dwords
//if not send a hold
end
READ_END: begin
//send r ok or r err
//XXX: Watch out for PHY_READY
//if CRC checks out OK then send an R_OK
//if CRC does not check out then send an R_ERR
//if (phy_ready) begin
if (crc_ok) begin
send_r_ok <= 1;
state <= SEND_STATUS;
end
else begin
send_r_err <= 1;
state <= SEND_STATUS;
end
//end
end
SEND_STATUS: begin
if (send_r_ok) begin
send_r_ok <= 1;
end
else begin
send_r_err <= 1;
end
if (detect_sync) begin
state <= IDLE;
end
end
default: begin
state <= IDLE;
end
endcase
end
end
endmodule |
module cont_controller (
input rst, //reset
input clk,
input phy_ready,
input xmit_cont_en, //enable the transmit cont primative (slows simulations WAY!!! down)
input last_prim,
input [31:0] ll_tx_din,
input ll_tx_is_k,
output [31:0] cont_tx_dout,
output cont_tx_is_k,
input [31:0] rx_din,
input [3:0] rx_is_k,
output detect_sync,
output detect_r_rdy,
output detect_r_ip,
output detect_r_err,
output detect_r_ok,
output detect_x_rdy,
output detect_sof,
output detect_eof,
output detect_wtrm,
output detect_cont,
output detect_hold,
output detect_holda,
output detect_preq_s,
output detect_preq_p,
output detect_align,
output detect_xrdy_xrdy
);
//Parameters
//Registers/Wires
//CONT detect State Machine
wire hold_cont;
wire holda_cont;
wire pmreq_p_cont;
wire pmreq_s_cont;
wire r_err_cont;
wire r_ip_cont;
wire r_ok_cont;
wire r_rdy_cont;
wire sync_cont;
wire wtrm_cont;
wire x_rdy_cont;
reg cont_detect;
reg [31:0] prev_prim;
reg hold_cont_ready;
reg holda_cont_ready;
reg pmreq_p_cont_ready;
reg pmreq_s_cont_ready;
reg r_err_cont_ready;
reg r_ip_cont_ready;
reg r_ok_cont_ready;
reg r_rdy_cont_ready;
reg sync_cont_ready;
reg wtrm_cont_ready;
reg x_rdy_cont_ready;
//CONT generate state machine
reg [31:0] tx_prev_prim;
reg tx_cont_enable;
reg tx_cont_sent;
reg send_cont;
//Scrambler control
wire scram_en;
wire [31:0] scram_dout;
//Submodules
scrambler scram (
.rst (rst ),
.clk (clk ),
.prim_scrambler (1'b1 ),
.en (scram_en ),
.din (ll_tx_din ),
.dout (scram_dout )
);
//Asynchronous Logic
assign detect_sync = ((rx_is_k[0]) && (rx_din == `PRIM_SYNC )) || sync_cont; //sync (normal) == sync(cont)
assign detect_r_rdy = ((rx_is_k[0]) && (rx_din == `PRIM_R_RDY )) || r_rdy_cont;
assign detect_r_ip = ((rx_is_k[0]) && (rx_din == `PRIM_R_IP )) || r_ip_cont;
assign detect_r_err = ((rx_is_k[0]) && (rx_din == `PRIM_R_ERR )) || r_err_cont;
assign detect_r_ok = ((rx_is_k[0]) && (rx_din == `PRIM_R_OK )) || r_ok_cont;
assign detect_x_rdy = ((rx_is_k[0]) && (rx_din == `PRIM_X_RDY )) || x_rdy_cont;
assign detect_sof = (rx_is_k[0]) && (rx_din == `PRIM_SOF );
assign detect_eof = (rx_is_k[0]) && (rx_din == `PRIM_EOF );
assign detect_wtrm = ((rx_is_k[0]) && (rx_din == `PRIM_WTRM )) || wtrm_cont;
assign detect_cont = (rx_is_k[0]) && (rx_din == `PRIM_CONT );
assign detect_hold = ((rx_is_k[0]) && (rx_din == `PRIM_HOLD )) || hold_cont; //hold (normal) == hold (cont)
assign detect_holda = ((rx_is_k[0]) && (rx_din == `PRIM_HOLDA )) || holda_cont; //holda (normal) == holda (cont)
assign detect_preq_s = ((rx_is_k[0]) && (rx_din == `PRIM_PREQ_S )) || pmreq_s_cont;
assign detect_preq_p = ((rx_is_k[0]) && (rx_din == `PRIM_PREQ_P )) || pmreq_p_cont;
assign detect_align = (rx_is_k[0]) && (rx_din == `PRIM_ALIGN );
assign detect_xrdy_xrdy = ((((rx_is_k[0])&& (rx_din == `PRIM_X_RDY )) || x_rdy_cont) && ll_tx_is_k && (ll_tx_din == `PRIM_X_RDY));
assign sync_cont = sync_cont_ready && ((rx_din == `PRIM_CONT) || (!rx_is_k[0] || detect_align));
assign hold_cont = hold_cont_ready && ((rx_din == `PRIM_CONT) || (!rx_is_k[0] || detect_align));
assign holda_cont = holda_cont_ready && ((rx_din == `PRIM_CONT) || (!rx_is_k[0] || detect_align));
assign pmreq_p_cont = pmreq_p_cont_ready && ((rx_din == `PRIM_CONT) || (!rx_is_k[0] || detect_align));
assign pmreq_s_cont = pmreq_s_cont_ready && ((rx_din == `PRIM_CONT) || (!rx_is_k[0] || detect_align));
assign r_err_cont = r_err_cont_ready && ((rx_din == `PRIM_CONT) || (!rx_is_k[0] || detect_align));
assign r_ip_cont = r_ip_cont_ready && ((rx_din == `PRIM_CONT) || (!rx_is_k[0] || detect_align));
assign r_ok_cont = r_ok_cont_ready && ((rx_din == `PRIM_CONT) || (!rx_is_k[0] || detect_align));
assign r_rdy_cont = r_rdy_cont_ready && ((rx_din == `PRIM_CONT) || (!rx_is_k[0] || detect_align));
assign wtrm_cont = wtrm_cont_ready && ((rx_din == `PRIM_CONT) || (!rx_is_k[0] || detect_align));
assign x_rdy_cont = x_rdy_cont_ready && ((rx_din == `PRIM_CONT) || (!rx_is_k[0] || detect_align));
assign cont_tx_dout = (!xmit_cont_en) ? ll_tx_din : //when transmit cont gen is disable
((tx_prev_prim != ll_tx_din) && ll_tx_is_k) ? ll_tx_din : //if the prev != curr (exit)
(last_prim) ? ll_tx_din:
(tx_cont_enable) ? //if the cont is enabled
send_cont ? `PRIM_CONT : //need to first send the cont
scram_dout : //send the junk
ll_tx_din; //tx cont is not enabled
assign cont_tx_is_k = (!xmit_cont_en) ? ll_tx_is_k :
((tx_prev_prim != ll_tx_din) && ll_tx_is_k) ? ll_tx_is_k ://if the prev != curr (exit)
(last_prim) ?ll_tx_is_k:
(tx_cont_enable) ? //if the cont is enabled
send_cont ? 1'b1 : //need to first send the cont
1'b0 : //send the junk
ll_tx_is_k; //tx cont is not enabled
assign scram_en = tx_cont_enable;
//Synchronous logic
//Cont detect
always @ (posedge clk) begin
if (rst) begin
cont_detect <= 0;
hold_cont_ready <= 0;
holda_cont_ready <= 0;
pmreq_p_cont_ready <= 0;
pmreq_s_cont_ready <= 0;
r_err_cont_ready <= 0;
r_ip_cont_ready <= 0;
r_ok_cont_ready <= 0;
r_rdy_cont_ready <= 0;
sync_cont_ready <= 0;
wtrm_cont_ready <= 0;
x_rdy_cont_ready <= 0;
end
else begin
if (!detect_align) begin
if (rx_is_k) begin
if (rx_din == `PRIM_CONT) begin
cont_detect <= 1;
end
else if (prev_prim == rx_din) begin
case (prev_prim)
`PRIM_SYNC : begin
sync_cont_ready <= 1;
end
`PRIM_R_RDY : begin
r_rdy_cont_ready <= 1;
end
`PRIM_R_IP : begin
r_ip_cont_ready <= 1;
end
`PRIM_R_ERR : begin
r_err_cont_ready <= 1;
end
`PRIM_R_OK : begin
r_ok_cont_ready <= 1;
end
`PRIM_X_RDY : begin
x_rdy_cont_ready <= 1;
end
`PRIM_WTRM : begin
wtrm_cont_ready <= 1;
end
`PRIM_HOLD : begin
if (cont_detect) begin
hold_cont_ready <= 0;
cont_detect <= 0;
end
else begin
hold_cont_ready <= 1;
end
end
`PRIM_HOLDA : begin
if (cont_detect) begin
holda_cont_ready <= 0;
cont_detect <= 0;
end
else begin
holda_cont_ready <= 1;
end
end
`PRIM_PREQ_S : begin
pmreq_s_cont_ready <= 1;
end
`PRIM_PREQ_P : begin
pmreq_p_cont_ready <= 1;
end
`PRIM_ALIGN : begin
end
default: begin
hold_cont_ready <= 0;
holda_cont_ready <= 0;
pmreq_p_cont_ready <= 0;
pmreq_s_cont_ready <= 0;
r_err_cont_ready <= 0;
r_ip_cont_ready <= 0;
r_ok_cont_ready <= 0;
r_rdy_cont_ready <= 0;
sync_cont_ready <= 0;
wtrm_cont_ready <= 0;
x_rdy_cont_ready <= 0;
end
endcase
end
//save the previous primative
else begin
prev_prim <= rx_din;
//previous primative doesn't equal current primitive
cont_detect <= 0;
hold_cont_ready <= 0;
holda_cont_ready <= 0;
pmreq_p_cont_ready <= 0;
pmreq_s_cont_ready <= 0;
r_err_cont_ready <= 0;
r_ip_cont_ready <= 0;
r_ok_cont_ready <= 0;
r_rdy_cont_ready <= 0;
sync_cont_ready <= 0;
wtrm_cont_ready <= 0;
x_rdy_cont_ready <= 0;
end
end
if (!rx_is_k[0] && !cont_detect) begin
cont_detect <= 0;
hold_cont_ready <= 0;
holda_cont_ready <= 0;
pmreq_p_cont_ready <= 0;
pmreq_s_cont_ready <= 0;
r_err_cont_ready <= 0;
r_ip_cont_ready <= 0;
r_ok_cont_ready <= 0;
r_rdy_cont_ready <= 0;
sync_cont_ready <= 0;
wtrm_cont_ready <= 0;
x_rdy_cont_ready <= 0;
end
end
end
end
//Cont Generator
always @ (posedge clk) begin
if (rst || !xmit_cont_en) begin
tx_prev_prim <= 0;
tx_cont_enable <= 0;
tx_cont_sent <= 0;
send_cont <= 0;
end
else begin
if (phy_ready) begin
send_cont <= 0;
if (ll_tx_is_k) begin
//reset everything because the previous primative is not equal to the current one
if (tx_prev_prim != ll_tx_din) begin
send_cont <= 0;
tx_cont_sent <= 0;
tx_cont_enable <= 0;
end
else begin
//see if we need to send the cont primative
if (tx_cont_enable && send_cont) begin
tx_cont_sent <= 1;
end
//previous primative == current primative
case (tx_prev_prim)
`PRIM_SYNC : begin
tx_cont_enable <= 1;
if (!tx_cont_sent && !send_cont) begin
send_cont <= 1;
end
end
`PRIM_R_RDY : begin
tx_cont_enable <= 1;
if (!tx_cont_sent && !send_cont) begin
send_cont <= 1;
end
end
`PRIM_R_IP : begin
tx_cont_enable <= 1;
if (!tx_cont_sent && !send_cont) begin
send_cont <= 1;
end
end
`PRIM_R_ERR : begin
tx_cont_enable <= 1;
if (!tx_cont_sent && !send_cont) begin
send_cont <= 1;
end
end
`PRIM_R_OK : begin
tx_cont_enable <= 1;
if (!tx_cont_sent && !send_cont) begin
send_cont <= 1;
end
end
`PRIM_X_RDY : begin
tx_cont_enable <= 1;
if (!tx_cont_sent && !send_cont) begin
send_cont <= 1;
end
end
`PRIM_WTRM : begin
tx_cont_enable <= 1;
if (!tx_cont_sent && !send_cont) begin
send_cont <= 1;
end
end
`PRIM_HOLD : begin
tx_cont_enable <= 1;
if (!tx_cont_sent && !send_cont) begin
send_cont <= 1;
end
end
`PRIM_HOLDA : begin
tx_cont_enable <= 1;
if (!tx_cont_sent && !send_cont) begin
send_cont <= 1;
end
end
`PRIM_PREQ_S : begin
tx_cont_enable <= 1;
if (!tx_cont_sent && !send_cont) begin
send_cont <= 1;
end
end
`PRIM_PREQ_P : begin
tx_cont_enable <= 1;
if (!tx_cont_sent && !send_cont) begin
send_cont <= 1;
end
end
default: begin
send_cont <= 0;
tx_cont_enable <= 0;
tx_cont_sent <= 0;
end
endcase
end
end
else begin
//it is not a k value so don't read it
tx_prev_prim <= 0;
end
//k value record the PRIM
tx_prev_prim <= ll_tx_din;
if (last_prim) begin
tx_cont_enable <= 0;
end
end
end
end
endmodule |
module crc (
clk,
rst,
en,
din,
dout
);
input clk;
input rst;
input en;
input [31:0] din;
output reg [31:0] dout;
parameter CRC_INIT = 32'h52325032;
//Registers/Wires
wire [31:0] crc_next;
wire [31:0] crc_new;
always @ (posedge clk) begin
if (rst) begin
dout <= CRC_INIT;
end
else if (en) begin
dout <= crc_next;
end
end
assign crc_new = dout ^ din;
assign crc_next[31] =crc_new[31] ^
crc_new[30] ^
crc_new[29] ^
crc_new[28] ^
crc_new[27] ^
crc_new[25] ^
crc_new[24] ^
crc_new[23] ^
crc_new[15] ^
crc_new[11] ^
crc_new[9] ^
crc_new[8] ^
crc_new[5];
assign crc_next[30] =crc_new[30] ^
crc_new[29] ^
crc_new[28] ^
crc_new[27] ^
crc_new[26] ^
crc_new[24] ^
crc_new[23] ^
crc_new[22] ^
crc_new[14] ^
crc_new[10] ^
crc_new[8] ^
crc_new[7] ^
crc_new[4];
assign crc_next[29] =crc_new[31] ^
crc_new[29] ^
crc_new[28] ^
crc_new[27] ^
crc_new[26] ^
crc_new[25] ^
crc_new[23] ^
crc_new[22] ^
crc_new[21] ^
crc_new[13] ^
crc_new[9] ^
crc_new[7] ^
crc_new[6] ^
crc_new[3];
assign crc_next[28] =crc_new[30] ^
crc_new[28] ^
crc_new[27] ^
crc_new[26] ^
crc_new[25] ^
crc_new[24] ^
crc_new[22] ^
crc_new[21] ^
crc_new[20] ^
crc_new[12] ^
crc_new[8] ^
crc_new[6] ^
crc_new[5] ^
crc_new[2];
assign crc_next[27] =crc_new[29] ^
crc_new[27] ^
crc_new[26] ^
crc_new[25] ^
crc_new[24] ^
crc_new[23] ^
crc_new[21] ^
crc_new[20] ^
crc_new[19] ^
crc_new[11] ^
crc_new[7] ^
crc_new[5] ^
crc_new[4] ^
crc_new[1];
assign crc_next[26] =crc_new[31] ^
crc_new[28] ^
crc_new[26] ^
crc_new[25] ^
crc_new[24] ^
crc_new[23] ^
crc_new[22] ^
crc_new[20] ^
crc_new[19] ^
crc_new[18] ^
crc_new[10] ^
crc_new[6] ^
crc_new[4] ^
crc_new[3] ^
crc_new[0];
assign crc_next[25] =crc_new[31] ^
crc_new[29] ^
crc_new[28] ^
crc_new[22] ^
crc_new[21] ^
crc_new[19] ^
crc_new[18] ^
crc_new[17] ^
crc_new[15] ^
crc_new[11] ^
crc_new[8] ^
crc_new[3] ^
crc_new[2];
assign crc_next[24] =crc_new[30] ^
crc_new[28] ^
crc_new[27] ^
crc_new[21] ^
crc_new[20] ^
crc_new[18] ^
crc_new[17] ^
crc_new[16] ^
crc_new[14] ^
crc_new[10] ^
crc_new[7] ^
crc_new[2] ^
crc_new[1];
assign crc_next[23] =crc_new[31] ^
crc_new[29] ^
crc_new[27] ^
crc_new[26] ^
crc_new[20] ^
crc_new[19] ^
crc_new[17] ^
crc_new[16] ^
crc_new[15] ^
crc_new[13] ^
crc_new[9] ^
crc_new[6] ^
crc_new[1] ^
crc_new[0];
assign crc_next[22] =crc_new[31] ^
crc_new[29] ^
crc_new[27] ^
crc_new[26] ^
crc_new[24] ^
crc_new[23] ^
crc_new[19] ^
crc_new[18] ^
crc_new[16] ^
crc_new[14] ^
crc_new[12] ^
crc_new[11] ^
crc_new[9] ^
crc_new[0];
assign crc_next[21] =crc_new[31] ^
crc_new[29] ^
crc_new[27] ^
crc_new[26] ^
crc_new[24] ^
crc_new[22] ^
crc_new[18] ^
crc_new[17] ^
crc_new[13] ^
crc_new[10] ^
crc_new[9] ^
crc_new[5];
assign crc_next[20] =crc_new[30] ^
crc_new[28] ^
crc_new[26] ^
crc_new[25] ^
crc_new[23] ^
crc_new[21] ^
crc_new[17] ^
crc_new[16] ^
crc_new[12] ^
crc_new[9] ^
crc_new[8] ^
crc_new[4];
assign crc_next[19] =crc_new[29] ^
crc_new[27] ^
crc_new[25] ^
crc_new[24] ^
crc_new[22] ^
crc_new[20] ^
crc_new[16] ^
crc_new[15] ^
crc_new[11] ^
crc_new[8] ^
crc_new[7] ^
crc_new[3];
assign crc_next[18] =crc_new[31] ^
crc_new[28] ^
crc_new[26] ^
crc_new[24] ^
crc_new[23] ^
crc_new[21] ^
crc_new[19] ^
crc_new[15] ^
crc_new[14] ^
crc_new[10] ^
crc_new[7] ^
crc_new[6] ^
crc_new[2];
assign crc_next[17] =crc_new[31] ^
crc_new[30] ^
crc_new[27] ^
crc_new[25] ^
crc_new[23] ^
crc_new[22] ^
crc_new[20] ^
crc_new[18] ^
crc_new[14] ^
crc_new[13] ^
crc_new[9] ^
crc_new[6] ^
crc_new[5] ^
crc_new[1];
assign crc_next[16] =crc_new[30] ^
crc_new[29] ^
crc_new[26] ^
crc_new[24] ^
crc_new[22] ^
crc_new[21] ^
crc_new[19] ^
crc_new[17] ^
crc_new[13] ^
crc_new[12] ^
crc_new[8] ^
crc_new[5] ^
crc_new[4] ^
crc_new[0];
assign crc_next[15] =crc_new[30] ^
crc_new[27] ^
crc_new[24] ^
crc_new[21] ^
crc_new[20] ^
crc_new[18] ^
crc_new[16] ^
crc_new[15] ^
crc_new[12] ^
crc_new[9] ^
crc_new[8] ^
crc_new[7] ^
crc_new[5] ^
crc_new[4] ^
crc_new[3];
assign crc_next[14] =crc_new[29] ^
crc_new[26] ^
crc_new[23] ^
crc_new[20] ^
crc_new[19] ^
crc_new[17] ^
crc_new[15] ^
crc_new[14] ^
crc_new[11] ^
crc_new[8] ^
crc_new[7] ^
crc_new[6] ^
crc_new[4] ^
crc_new[3] ^
crc_new[2];
assign crc_next[13] =crc_new[31] ^
crc_new[28] ^
crc_new[25] ^
crc_new[22] ^
crc_new[19] ^
crc_new[18] ^
crc_new[16] ^
crc_new[14] ^
crc_new[13] ^
crc_new[10] ^
crc_new[7] ^
crc_new[6] ^
crc_new[5] ^
crc_new[3] ^
crc_new[2] ^
crc_new[1];
assign crc_next[12] =crc_new[31] ^
crc_new[30] ^
crc_new[27] ^
crc_new[24] ^
crc_new[21] ^
crc_new[18] ^
crc_new[17] ^
crc_new[15] ^
crc_new[13] ^
crc_new[12] ^
crc_new[9] ^
crc_new[6] ^
crc_new[5] ^
crc_new[4] ^
crc_new[2] ^
crc_new[1] ^
crc_new[0];
assign crc_next[11] =crc_new[31] ^
crc_new[28] ^
crc_new[27] ^
crc_new[26] ^
crc_new[25] ^
crc_new[24] ^
crc_new[20] ^
crc_new[17] ^
crc_new[16] ^
crc_new[15] ^
crc_new[14] ^
crc_new[12] ^
crc_new[9] ^
crc_new[4] ^
crc_new[3] ^
crc_new[1] ^
crc_new[0];
assign crc_next[10] =crc_new[31] ^
crc_new[29] ^
crc_new[28] ^
crc_new[26] ^
crc_new[19] ^
crc_new[16] ^
crc_new[14] ^
crc_new[13] ^
crc_new[9] ^
crc_new[5] ^
crc_new[3] ^
crc_new[2] ^
crc_new[0];
assign crc_next[9] = crc_new[29] ^
crc_new[24] ^
crc_new[23] ^
crc_new[18] ^
crc_new[13] ^
crc_new[12] ^
crc_new[11] ^
crc_new[9] ^
crc_new[5] ^
crc_new[4] ^
crc_new[2] ^
crc_new[1];
assign crc_next[8] = crc_new[31] ^
crc_new[28] ^
crc_new[23] ^
crc_new[22] ^
crc_new[17] ^
crc_new[12] ^
crc_new[11] ^
crc_new[10] ^
crc_new[8] ^
crc_new[4] ^
crc_new[3] ^
crc_new[1] ^
crc_new[0];
assign crc_next[7] = crc_new[29] ^
crc_new[28] ^
crc_new[25] ^
crc_new[24] ^
crc_new[23] ^
crc_new[22] ^
crc_new[21] ^
crc_new[16] ^
crc_new[15] ^
crc_new[10] ^
crc_new[8] ^
crc_new[7] ^
crc_new[5] ^
crc_new[3] ^
crc_new[2] ^
crc_new[0];
assign crc_next[6] = crc_new[30] ^
crc_new[29] ^
crc_new[25] ^
crc_new[22] ^
crc_new[21] ^
crc_new[20] ^
crc_new[14] ^
crc_new[11] ^
crc_new[8] ^
crc_new[7] ^
crc_new[6] ^
crc_new[5] ^
crc_new[4] ^
crc_new[2] ^
crc_new[1];
assign crc_next[5] = crc_new[29] ^
crc_new[28] ^
crc_new[24] ^
crc_new[21] ^
crc_new[20] ^
crc_new[19] ^
crc_new[13] ^
crc_new[10] ^
crc_new[7] ^
crc_new[6] ^
crc_new[5] ^
crc_new[4] ^
crc_new[3] ^
crc_new[1] ^
crc_new[0];
assign crc_next[4] = crc_new[31] ^
crc_new[30] ^
crc_new[29] ^
crc_new[25] ^
crc_new[24] ^
crc_new[20] ^
crc_new[19] ^
crc_new[18] ^
crc_new[15] ^
crc_new[12] ^
crc_new[11] ^
crc_new[8] ^
crc_new[6] ^
crc_new[4] ^
crc_new[3] ^
crc_new[2] ^
crc_new[0];
assign crc_next[3] = crc_new[31] ^
crc_new[27] ^
crc_new[25] ^
crc_new[19] ^
crc_new[18] ^
crc_new[17] ^
crc_new[15] ^
crc_new[14] ^
crc_new[10] ^
crc_new[9] ^
crc_new[8] ^
crc_new[7] ^
crc_new[3] ^
crc_new[2] ^
crc_new[1];
assign crc_next[2] = crc_new[31] ^
crc_new[30] ^
crc_new[26] ^
crc_new[24] ^
crc_new[18] ^
crc_new[17] ^
crc_new[16] ^
crc_new[14] ^
crc_new[13] ^
crc_new[9] ^
crc_new[8] ^
crc_new[7] ^
crc_new[6] ^
crc_new[2] ^
crc_new[1] ^
crc_new[0];
assign crc_next[1] = crc_new[28] ^
crc_new[27] ^
crc_new[24] ^
crc_new[17] ^
crc_new[16] ^
crc_new[13] ^
crc_new[12] ^
crc_new[11] ^
crc_new[9] ^
crc_new[7] ^
crc_new[6] ^
crc_new[1] ^
crc_new[0];
assign crc_next[0] = crc_new[31] ^
crc_new[30] ^
crc_new[29] ^
crc_new[28] ^
crc_new[26] ^
crc_new[25] ^
crc_new[24] ^
crc_new[16] ^
crc_new[12] ^
crc_new[10] ^
crc_new[9] ^
crc_new[6] ^
crc_new[0];
endmodule |
module sata_link_layer_write (
input rst, //reset
input clk,
input phy_ready,
output write_ready,
input en,
output idle,
input send_sync_escape,
input detect_align,
input detect_sync,
input detect_x_rdy,
input detect_r_rdy,
input detect_r_ip,
input detect_r_err,
input detect_r_ok,
input detect_cont,
input detect_hold,
input detect_holda,
output reg send_holda,
output [31:0] tx_dout,
output tx_is_k,
input [31:0] rx_din,
input [3:0] rx_is_k,
input write_start,
output reg write_strobe,
input [31:0] write_data,
input [23:0] write_size, //maximum 2048
input write_hold,
output reg write_finished,
output reg xmit_error,
output reg wsize_z_error,
input write_abort,
input data_scrambler_en,
input is_device,
output reg [3:0] state,
output reg [3:0] fstate,
output reg last_prim,
output reg send_crc,
output reg post_align_write,
output reg [23:0] in_data_addra,
output reg [12:0] d_count,
output reg [12:0] write_count,
output reg [3:0] buffer_pos
);
//Primatives
localparam IDLE = 4'h0;
//fstate
localparam FIRST_DATA = 4'h1;
localparam ENQUEUE = 4'h2;
localparam LAST_DATA = 4'h3;
localparam WRITE_CRC = 4'h4;
localparam WAIT = 4'h5;
//state
localparam WRITE_START = 4'h1;
localparam WRITE = 4'h2;
localparam WRITE_END = 4'h3;
localparam WAIT_RESPONSE = 4'h4;
//Registers/Wires
reg [31:0] post_align_data;
reg send_x_rdy;
reg send_sof;
reg send_eof;
reg send_wtrm;
reg send_cont;
reg send_hold;
//reg send_holda;
reg send_sync;
//Transport
reg [31:0] align_data_out;
reg prev_phy_ready;
wire pos_phy_ready;
wire neg_phy_ready;
reg prev_hold;
//wire pos_hold;
wire neg_holda;
reg [3:0] min_holda_count;
wire min_holda_timeout;
reg [3:0] dhold_delay_cnt;
reg dhold_delay;
//CRC
//XXX: Tie the CRC_EN to the read strobe
wire [31:0] crc_dout;
//Scrambler
reg scr_rst;
reg scr_en;
reg [31:0] scr_din;
wire [31:0] scr_dout;
//Internal FIFOs
reg [23:0] data_size;
reg wr_en;
wire [31:0] rd_dout;
wire empty;
wire enable_write_transaction;
reg [31:0] bump_buffer [0:3];
reg [3:0] data_pointer;
//XXX: Fix this aweful HACK!
wire [31:0] d0_buf;
wire [31:0] d1_buf;
wire [31:0] d2_buf;
wire [31:0] d3_buf;
//Sub Modules
blk_mem # (
.DATA_WIDTH (32 ),
.ADDRESS_WIDTH (13 )
)br(
.clka (clk ),
.wea (wr_en ),
.addra (in_data_addra[12:0] ),
.dina (scr_dout ),
.clkb (clk ),
.addrb (write_count[12:0] ),
.doutb (rd_dout )
);
scrambler scr (
.rst (scr_rst ),
.clk (clk ),
.prim_scrambler (1'b0 ),
.en (scr_en ),
.din (scr_din ),
.dout (scr_dout )
);
crc crc_inst (
//reset the CRC any time we're in IDLE
.rst (scr_rst ),
.clk (clk ),
.en (write_strobe ),
.din (write_data ),
.dout (crc_dout )
);
//Asynchronous Logic
assign idle = (state == IDLE);
assign tx_dout = (send_x_rdy) ? `PRIM_X_RDY:
(send_sof) ? `PRIM_SOF:
(send_eof) ? `PRIM_EOF:
(send_wtrm) ? `PRIM_WTRM:
(send_cont) ? `PRIM_CONT:
(send_hold) ? `PRIM_HOLD:
(send_holda) ? `PRIM_HOLDA:
(send_sync) ? `PRIM_SYNC:
bump_buffer[buffer_pos];
assign tx_is_k = ( send_x_rdy ||
send_sof ||
send_eof ||
send_wtrm ||
send_cont ||
send_hold ||
send_holda ||
send_sync);
assign enable_write_transaction = (in_data_addra != 0);
assign empty = (in_data_addra == 0);
assign pos_phy_ready = phy_ready && ~prev_phy_ready;
assign neg_phy_ready = ~phy_ready && prev_phy_ready;
//assign pos_hold = detect_hold && ~prev_hold;
assign min_holda_timeout = (min_holda_count >= `MIN_HOLDA_TIMEOUT);
assign d0_buf = bump_buffer[0];
assign d1_buf = bump_buffer[1];
assign d2_buf = bump_buffer[2];
assign d3_buf = bump_buffer[3];
assign write_ready = phy_ready && !send_holda;
//Synchronous Logic
//Incomming buffer (this is the buffer after the scrambler and CRC)
always @ (posedge clk) begin
if (rst) begin
fstate <= IDLE;
data_size <= 0;
in_data_addra <= 0;
scr_din <= 0;
scr_en <= 0;
scr_rst <= 1;
wr_en <= 0;
write_strobe <= 0;
end
else begin
//Strobes
scr_en <= 0;
wr_en <= 0;
write_strobe <= 0;
scr_rst <= 0;
case (fstate)
IDLE: begin
in_data_addra <= 0;
if (write_start) begin
//add an extra space for the CRC
write_strobe <= 1;
data_size <= write_size;
scr_en <= 1;
scr_din <= 0;
fstate <= FIRST_DATA;
end
end
FIRST_DATA: begin
//$display ("LLW: Data Size: %d", data_size);
write_strobe <= 1;
wr_en <= 1;
scr_en <= 1;
scr_din <= write_data;
fstate <= ENQUEUE;
if (data_size == 1) begin
fstate <= LAST_DATA;
end
else begin
fstate <= ENQUEUE;
end
end
ENQUEUE: begin
in_data_addra <= in_data_addra + 24'h1;
wr_en <= 1;
scr_en <= 1;
scr_din <= write_data;
//write_strobe <= 1;
if (in_data_addra < data_size - 2) begin
write_strobe <= 1;
end
else begin
fstate <= LAST_DATA;
end
end
LAST_DATA: begin
in_data_addra <= in_data_addra + 24'h1;
wr_en <= 1;
scr_en <= 1;
scr_din <= crc_dout;
fstate <= WRITE_CRC;
end
WRITE_CRC: begin
fstate <= WAIT;
end
WAIT: begin
scr_rst <= 1;
if (state == WRITE) begin
//Because a transaction is in progress and our write buffer is full we can reset the in address to 0
in_data_addra <= 0;
end
if (write_finished) begin
fstate <= IDLE;
data_size <= 0;
end
end
default: begin
fstate <= IDLE;
end
endcase
if (send_sync_escape) begin
fstate <= IDLE;
data_size <= 0;
end
end
end
//Detect Hold Delay
always @ (posedge clk) begin
if (rst) begin
dhold_delay <= 0;
dhold_delay_cnt <= 0;
end
else begin
if (dhold_delay_cnt < `DHOLD_DELAY) begin
dhold_delay_cnt <= dhold_delay_cnt + 4'h1;
end
else begin
dhold_delay <= 1;
end
//Always deassert dhold_delay whenever detect hold goes low
if (!detect_hold) begin
dhold_delay_cnt <= 0;
dhold_delay <= 0;
end
end
end
always @ (posedge clk) begin
if (rst) begin
state <= IDLE;
post_align_write <= 0;
post_align_data <= 32'h0;
send_x_rdy <= 0;
send_sof <= 0;
send_eof <= 0;
send_wtrm <= 0;
send_cont <= 0;
send_hold <= 0;
send_holda <= 0;
send_crc <= 0;
send_sync <= 0;
write_count <= 0;
//write_strobe <= 0;
write_finished <= 0;
//error strobe
xmit_error <= 0;
wsize_z_error <= 0;
last_prim <= 0;
align_data_out <= 0;
min_holda_count <= `MIN_HOLDA_TIMEOUT;
prev_phy_ready <= 0;
prev_hold <= 0;
bump_buffer[0] <= 0;
bump_buffer[1] <= 0;
bump_buffer[2] <= 0;
bump_buffer[3] <= 0;
d_count <= 0;
buffer_pos <= 0;
end
else begin
//XXX: Remove Bump Buffer
if ((state == WRITE_START) || ((state != IDLE) && (d_count != write_count))) begin
bump_buffer[3] <= bump_buffer[2];
bump_buffer[2] <= bump_buffer[1];
bump_buffer[1] <= bump_buffer[0];
bump_buffer[0] <= rd_dout;
d_count <= write_count;
end
//XXX: End Remove Bump Buffer
//write_strobe <= 0;
write_finished <= 0;
xmit_error <= 0;
wsize_z_error <= 0;
//previous
prev_phy_ready <= phy_ready;
`ifdef DHOLD_DELAY_EN
prev_hold <= dhold_delay;
`else
prev_hold <= detect_hold;
`endif
if (min_holda_count < `MIN_HOLDA_TIMEOUT) begin
min_holda_count <= min_holda_count + 4'h1;
end
if (phy_ready) begin
send_sync <= 0;
send_x_rdy <= 0;
send_sof <= 0;
send_eof <= 0;
send_wtrm <= 0;
send_cont <= 0;
send_hold <= 0;
send_holda <= 0;
send_crc <= 0;
last_prim <= 0;
end
case (state)
IDLE: begin
buffer_pos <= 0;
send_sync <= 1;
if (enable_write_transaction) begin
//There is some data within the input write buffer
state <= WRITE_START;
write_count <= 0;
d_count <= 0;
end
end
WRITE_START: begin
if (phy_ready) begin
send_sync <= 1;
if (!is_device && detect_x_rdy) begin
//hard drive wins the draw :(
state <= IDLE;
end
else if (detect_r_rdy) begin
state <= WRITE;
send_sof <= 1;
//bump_buffer[buffer_pos] <= rd_dout;
write_count <= write_count + 13'h1;
//Send First Read
//read the first packet of data
end
else begin
send_x_rdy <= 1;
end
end
end
WRITE: begin
if (!write_ready) begin
if (neg_phy_ready && (buffer_pos == 0)) begin
buffer_pos <= buffer_pos + 4'h1;
end
`ifdef DHOLD_DELAY_EN
if (dhold_delay || !min_holda_timeout) begin
`else
if (detect_hold || !min_holda_timeout) begin
`endif
//Haven't sent out a holda yet
send_holda <= 1;
end
else begin
//Detect the remote side finishing up with a hold
//if (!detect_hold && min_holda_timeout) begin
if (send_holda && !last_prim) begin
last_prim <= 1;
send_holda <= 1;
end
end
end
else begin
if (write_count <= data_size + 1) begin //is this data_size + 1 for the CRC?
if (buffer_pos > 0) begin
buffer_pos <= buffer_pos - 1;
if (buffer_pos == 1) begin
write_count <= write_count + 13'h1;
end
end
else begin
write_count <= write_count + 13'h1;
end
end
else begin
send_eof <= 1;
state <= WAIT_RESPONSE;
end
end
//I can use this to see if the phy is ready too
`ifdef DHOLD_DELAY_EN
if (dhold_delay && (buffer_pos == 0)) begin
`else
if (detect_hold && (buffer_pos == 0)) begin
`endif
min_holda_count <= 0;
//XXX: I may need this to capture holds at the end of a trnasfer
buffer_pos <= buffer_pos + 4'h1;
send_holda <= 1;
end
end
WRITE_END: begin
state <= WAIT_RESPONSE;
end
WAIT_RESPONSE: begin
send_wtrm <= 1;
if (detect_r_err) begin
write_finished <= 1;
xmit_error <= 1;
state <= IDLE;
end
else if (detect_r_ok) begin
write_finished <= 1;
state <= IDLE;
end
end
default: begin
state <= IDLE;
end
endcase
if (send_sync_escape) begin
send_sync <= 1;
state <= IDLE;
buffer_pos <= 0;
write_count <= 0;
d_count <= 0;
end
end
end
endmodule |
module blk_mem #(
parameter DATA_WIDTH = 8,
parameter ADDRESS_WIDTH = 4
)(
input clka,
input wea,
input [ADDRESS_WIDTH - 1 :0] addra,
input [DATA_WIDTH - 1:0] dina,
input clkb,
input [ADDRESS_WIDTH - 1:0] addrb,
output [DATA_WIDTH - 1:0] doutb
);
//Parameters
//Registers/Wires
reg [DATA_WIDTH - 1:0] mem [0:2 ** ADDRESS_WIDTH];
reg [DATA_WIDTH - 1:0] dout;
//Submodules
//Asynchronous Logic
assign doutb = dout;
//Synchronous Logic
//write only on the A side
`ifdef SIMULATION
//Only initialize in simulation... somthing gets fucked when you try and do it on an FPGA
integer i;
initial begin
i = 0;
for (i = 0; i < (2 ** ADDRESS_WIDTH); i = i + 1) begin
mem[i] <= 0;
end
end
`endif
always @ (posedge clka)
begin
if ( wea ) begin
mem[addra] <= dina;
end
end
//read only on the b side
always @ (posedge clkb)
begin
dout <= mem[addrb];
end
endmodule |
module cross_clock_enable (
input rst,
input in_en,
input out_clk,
output reg out_en
);
//Parameters
//Registers/Wires
reg [2:0] out_en_sync;
//Submodules
//Asynchronous Logic
//Synchronous Logic
always @ (posedge out_clk) begin
if (rst) begin
out_en_sync <= 0;
out_en <= 0;
end
else begin
if (out_en_sync[2:1] == 2'b11) begin
out_en <= 1;
end
else if (out_en_sync[2:1] == 2'b00) begin
out_en <= 0;
end
out_en_sync <= {out_en_sync[1:0], in_en};
end
end
endmodule |
module debounce #(
parameter INITIAL_STATE = 0,
parameter DEBOUNCE_COUNT = 100
)(
input clk,
input in_signal,
output reg out_signal
);
reg [DEBOUNCE_COUNT - 1: 0] debounce;
initial begin
out_signal <= INITIAL_STATE;
debounce <= INITIAL_STATE;
end
always @ (posedge clk) begin
debounce <= {debounce[(DEBOUNCE_COUNT - 2) : 0], in_signal};
if (debounce[0] == 1 && (& debounce)) begin
out_signal <= 1;
end
else if ((debounce[0] == 0) && (~| debounce)) begin
out_signal <= 0;
end
end
endmodule |
module ppfifo
#(parameter DATA_WIDTH = 8,
ADDRESS_WIDTH = 4
)(
//universal input
input reset,
//write side
input write_clock,
output reg [1:0] write_ready,
input [1:0] write_activate,
output [23:0] write_fifo_size,
input write_strobe,
input [DATA_WIDTH - 1: 0] write_data,
output starved,
//read side
input read_clock,
input read_strobe,
output reg read_ready,
input read_activate,
output reg [23:0] read_count,
output [DATA_WIDTH - 1: 0] read_data,
output inactive
);
localparam FIFO_DEPTH = (1 << ADDRESS_WIDTH);
//Local Registers/Wires
//Write Side
wire ppfifo_ready; // The write side only needs to
// know were ready if we don't
// write anything read won't start
wire [ADDRESS_WIDTH: 0] addr_in; // Actual address to the BRAM
reg [ADDRESS_WIDTH - 1: 0]write_address;
reg r_wselect; // Select the FIFO to work with
reg write_enable; // Enable a write to the BRAM
reg [1:0] wcc_read_ready;// Tell read side a FIFO is ready
wire [1:0] wcc_read_done;
// write status of the read
// available
reg wcc_tie_select; //because it's possible if the read
//side is slower than the write
//side it might be unknown which
//side was selected first, so use
//this signal to break ties
reg [23:0] w_count[1:0]; // save the write count for the read
// side
reg w_empty[1:0];
reg w_reset; //write side reset
reg [4:0] w_reset_timeout;
wire ready;
//Read Side
wire [ADDRESS_WIDTH: 0] addr_out; //Actual address to the BRAM
reg r_reset;
reg [4:0] r_reset_timeout;
reg [ADDRESS_WIDTH - 1: 0]r_address; //Address to access a bank
reg r_rselect; //Select a bank (Select a FIFO)
wire [1:0] rcc_read_ready;
// Write side says X is ready
reg [1:0] rcc_read_done;// Tell write side X is ready
wire rcc_tie_select;
//If there is a tie, then this will
//break it
reg [23:0] r_size[1:0]; // Size of FX read
reg [1:0] r_ready; //FIFO is ready
reg [1:0] r_wait; //Waiting for write side to send data
reg [1:0] r_activate; //Controls which FIFO is activated
reg r_next_fifo; //If both FIFOs are availalbe use this
reg [1:0] r_pre_activate; //Used to delay the clock cycle by
//one when the user activates the
//FIFO
reg r_pre_strobe;
reg r_pre_read_wait;//Wait an extra cycle so the registered data has a chance to set
//the data to be registered
wire [DATA_WIDTH - 1: 0] w_read_data; //data from the read FIFO
reg [DATA_WIDTH - 1: 0] r_read_data; //data from the read FIFO
//assign r_wselect = (write_activate == 2'b00) ? 1'b0 :
// (write_activate == 2'b01) ? 1'b0 :
// (write_activate == 2'b10) ? 1'b1 :
// reset ? 1'b0 :
// r_wselect;
// //I know this can be shortened down but it's more
// //readible thi way
assign write_fifo_size = FIFO_DEPTH;
assign addr_in = {r_wselect, write_address};
//assign write_enable = (write_activate > 0) && write_strobe;
assign ppfifo_ready = !(w_reset || r_reset);
assign ready = ppfifo_ready;
//assign wcc_tie_select = (wcc_read_ready == 2'b00) ? 1'b0 :
// (wcc_read_ready == 2'b01) ? 1'b0 :
// (wcc_read_ready == 2'b10) ? 1'b1 :
// wcc_tie_select;
// If the first FIFO is ready,
// then both FIFOs are ready then
// keep the first FIFO
assign addr_out = {r_rselect, r_address};
//Debug
//wire [23:0] debug_f0_w_count;
//wire [23:0] debug_f1_w_count;
//wire [23:0] debug_f0_r_size;
//wire [23:0] debug_f1_r_size;
//wire [23:0] debug_f0_r_count;
//wire [23:0] debug_f1_r_count;
//assign debug_f0_w_count = w_count[0];
//assign debug_f1_w_count = w_count[1];
//assign debug_f0_r_size = r_size[0];
//assign debug_f1_r_size = r_size[1];
assign inactive = (w_count[0] == 0) &&
(w_count[1] == 0) &&
(write_ready == 2'b11) &&
(!write_strobe);
assign read_data = (r_pre_strobe) ? w_read_data : r_read_data;
//Submodules
blk_mem #(
.DATA_WIDTH(DATA_WIDTH),
.ADDRESS_WIDTH(ADDRESS_WIDTH + 1)
) fifo0 (
//Write
.clka (write_clock ),
.wea (write_enable ), //This may just be replaced with write activate
.dina (write_data ),
.addra (addr_in ),
.clkb (read_clock ),
.doutb (w_read_data ),
.addrb (addr_out )
);
//W - R FIFO 0
cross_clock_enable ccwf0 (
.rst (reset ),
.in_en (wcc_read_ready[0] ),
.out_clk (read_clock ),
.out_en (rcc_read_ready[0] )
);
//W - R FIFO 1
cross_clock_enable ccwf1 (
.rst (reset ),
.in_en (wcc_read_ready[1] ),
.out_clk (read_clock ),
.out_en (rcc_read_ready[1] )
);
//W - R Tie Select
cross_clock_enable ccts (
.rst (reset ),
.in_en (wcc_tie_select ),
.out_clk (read_clock ),
.out_en (rcc_tie_select )
);
//R - W FIFO 0
cross_clock_enable ccrf0 (
.rst (reset ),
.in_en (rcc_read_done[0] ),
.out_clk (read_clock ),
.out_en (wcc_read_done[0] )
);
//R - W FIFO 1
cross_clock_enable ccrf1 (
.rst (reset ),
.in_en (rcc_read_done[1] ),
.out_clk (read_clock ),
.out_en (wcc_read_done[1] )
);
//R - W Reset
cross_clock_enable cc_starved(
.rst (reset ),
.in_en (!read_ready && !read_activate ),
.out_clk (write_clock ),
.out_en (starved )
);
//asynchronous logic
always @ (*) begin
case (wcc_read_ready)
2'b00: begin
wcc_tie_select = 1'b0;
end
2'b01: begin
wcc_tie_select = 1'b0;
end
2'b10: begin
wcc_tie_select = 1'b1;
end
default: begin
wcc_tie_select = 1'b0;
end
endcase
end
always @ (*) begin
case (write_activate)
2'b00: begin
r_wselect = 1'b0;
end
2'b01: begin
r_wselect = 1'b0;
end
2'b10: begin
r_wselect = 1'b1;
end
default: begin
r_wselect = 1'b0;
end
endcase
end
always @ (*) begin
if (write_activate > 0 && write_strobe) begin
write_enable = 1'b1;
end
else begin
write_enable = 1'b0;
end
end
//synchronous logic
//Reset Logic
always @ (posedge write_clock) begin
if (reset) begin
w_reset <= 1;
w_reset_timeout <= 0;
end
else begin
if (w_reset && (w_reset_timeout < 5'h4)) begin
w_reset_timeout <= w_reset_timeout + 5'h1;
end
else begin
w_reset <= 0;
end
end
end
always @ (posedge read_clock) begin
if (reset) begin
r_reset <= 1;
r_reset_timeout <= 0;
end
else begin
if (r_reset && (r_reset_timeout < 5'h4)) begin
r_reset_timeout <= r_reset_timeout + 5'h1;
end
else begin
r_reset <= 0;
end
end
end
//---------------Write Side---------------
initial begin
write_address = 0;
wcc_read_ready = 2'b00;
write_ready = 2'b00;
w_reset = 1;
w_reset_timeout = 0;
write_enable = 0;
r_wselect = 0;
wcc_tie_select = 0;
end
always @ (posedge write_clock) begin
if (reset) begin
write_ready <= 0;
end
else if (ready) begin
//Logic for the Write Enable
if (write_activate[0] && write_strobe) begin
write_ready[0] <= 1'b0;
end
if (write_activate[1] && write_strobe) begin
write_ready[1] <= 1'b0;
end
if (!write_activate[0] && (w_count[0] == 0) && wcc_read_done[0]) begin
//FIFO 0 is not accessed by the read side, and user has not activated
write_ready[0] <= 1;
end
if (!write_activate[1] && (w_count[1] == 0) && wcc_read_done[1]) begin
//FIFO 1 is not accessed by the read side, and user has not activated
write_ready[1] <= 1;
end
//When the user is finished reading the ready signal might go high
//I SHOULD MAKE A CONDITION WHERE THE WRITE COUND MUST BE 0
end
end
always @ (posedge write_clock) begin
if (reset) begin //Asynchronous Reset
wcc_read_ready <= 2'b00;
write_address <= 0;
w_count[0] <= 24'h0;
w_count[1] <= 24'h0;
end
else begin
if (write_activate > 0 && write_strobe) begin
write_address <= write_address + 1;
if (write_activate[0]) begin
w_count[0] <= w_count[0] + 1;
end
if (write_activate[1]) begin
w_count[1] <= w_count[1] + 1;
end
end
if (write_activate == 0) begin
write_address <= 0;
if (w_count[0] > 0) begin
wcc_read_ready[0] <= 1;
end
if (w_count[1] > 0) begin
wcc_read_ready[1] <= 1;
end
end
//I can't reset the w_count until the read side has indicated that it
//is done but that may be mistriggered when the write side finishes
//a write. So how do
//Only reset the write count when the done signal has been de-asserted
//Deassert w_readX_ready when we see the read has de-asserted r_readX_done
if (!wcc_read_done[0]) begin
//Only reset write count when the read side has said it's busy so it
//must be done reading
w_count[0] <= 0;
wcc_read_ready[0] <= 0;
end
if (!wcc_read_done[1]) begin
w_count[1] <= 0;
wcc_read_ready[1] <= 0;
end
end
end
//---------------Read Side---------------
initial begin
r_rselect = 0;
r_address = 0;
rcc_read_done = 2'b00;
r_size[0] = 24'h0;
r_size[1] = 24'h0;
r_wait = 2'b11;
r_ready = 2'b00;
r_activate = 2'b00;
r_pre_activate = 0;
r_next_fifo = 0;
r_reset = 1;
r_reset_timeout = 0;
read_ready = 0;
r_read_data = 32'h0;
r_pre_read_wait = 0;
end
always @ (posedge read_clock) begin
if (reset) begin //Asynchronous Reset
r_rselect <= 0;
r_address <= 0;
rcc_read_done <= 2'b11;
read_count <= 0;
r_activate <= 2'b00;
r_pre_activate <= 2'b00;
r_pre_read_wait <= 0;
r_size[0] <= 24'h0;
r_size[1] <= 24'h0;
//are these signals redundant?? can I just use the done?
r_wait <= 2'b11;
r_ready <= 2'b00;
r_next_fifo <= 0;
r_read_data <= 0;
read_ready <= 0;
end
else begin
r_pre_strobe <= read_strobe;
//Handle user enable and ready
if (!read_activate && !r_pre_activate) begin
//User has not activated the read side
//Prepare the read side
//Reset the address
if (r_activate == 0) begin
read_count <= 0;
r_address <= 0;
r_pre_read_wait <= 0;
if (r_ready > 0) begin
//This goes to one instead of activate
//Output select
//read_ready <= 1;
if (r_ready[0] && r_ready[1]) begin
//$display ("Tie");
//Tie
r_rselect <= r_next_fifo;
r_pre_activate[r_next_fifo] <= 1;
r_pre_activate[~r_next_fifo]<= 0;
r_next_fifo <= ~r_next_fifo;
read_count <= r_size[r_next_fifo];
end
else begin
//Only one side is ready
if (r_ready[0]) begin
//$display ("select 0");
r_rselect <= 0;
r_pre_activate[0] <= 1;
r_pre_activate[1] <= 0;
r_next_fifo <= 1;
read_count <= r_size[0];
end
else begin
//$display ("select 1");
r_rselect <= 1;
r_pre_activate[0] <= 0;
r_pre_activate[1] <= 1;
r_next_fifo <= 0;
read_count <= r_size[1];
end
end
end
end
//User has finished reading something
else if (r_activate[r_rselect] && !r_ready[r_rselect]) begin
r_activate[r_rselect] <= 0;
rcc_read_done[r_rselect] <= 1;
end
end
else begin
if ((r_pre_activate > 0) && r_pre_read_wait) begin
read_ready <= 1;
end
if (r_activate) begin
read_ready <= 0;
//User is requesting an accss
//Handle read strobes
//Only handle strobes when we are enabled
r_ready[r_rselect] <= 0;
end
//XXX: There should be a better way to handle these edge conditions
if (!r_activate && r_pre_read_wait) begin
r_read_data <= w_read_data;
r_address <= r_address + 1;
r_activate <= r_pre_activate;
r_pre_activate <= 0;
end
else if (!r_pre_read_wait) begin
r_pre_read_wait <= 1;
end
if (read_strobe && (r_address < (r_size[r_rselect] + 1))) begin
//Increment the address
r_read_data <= w_read_data;
r_address <= r_address + 1;
end
if (r_pre_strobe && !read_strobe) begin
r_read_data <= w_read_data;
end
end
if (!rcc_read_ready[0] && !r_ready[0] && !r_activate[0]) begin
r_wait[0] <= 1;
end
if (!rcc_read_ready[1] && !r_ready[1] && !r_activate[1]) begin
r_wait[1] <= 1;
end
//Check if the write side has sent over some data
if (rcc_read_ready > 0) begin
if ((r_wait == 2'b11) && (rcc_read_ready == 2'b11) && (w_count[0] > 0) && (w_count[1] > 0)) begin
//An ambiguous sitution that can arrise if the read side is much
//slower than the write side, both sides can arrise seemingly at the
//same time, so there needs to be a tie breaker
//$display ("Combo breaker goes to: %h", rcc_tie_select);
r_next_fifo <= rcc_tie_select;
end
if (r_wait[0] && rcc_read_ready[0]) begin
//$display ("write has send over data t othe 0 side");
//Normally it would not be cool to transfer data over a clock domain
//but the w_count[x] is stable before the write side sends over a write
//strobe
if (w_count[0] > 0) begin
//Only enable when count > 0
if ((r_activate == 0) && (!rcc_read_ready[1])) begin
//$display ("select 0");
r_next_fifo <= 0;
end
r_size[0] <= w_count[0];
r_ready[0] <= 1;
r_wait[0] <= 0;
rcc_read_done[0] <= 0;
end
end
if (r_wait[1] && rcc_read_ready[1]) begin
//$display ("write has send over data t othe 1 side");
//Write side has sent some data over
if (w_count[1] > 0) begin
if ((r_activate == 0) && (!rcc_read_ready[0])) begin
//$display ("select 1");
r_next_fifo <= 1;
end
r_size[1] <= w_count[1];
r_ready[1] <= 1;
r_wait[1] <= 0;
rcc_read_done[1] <= 0;
end
end
end
end
end
endmodule |
module sata_command_layer (
input rst, //reset
input linkup,
input clk,
input data_in_clk,
input data_in_clk_valid,
input data_out_clk,
input data_out_clk_valid,
//User Interface
output command_layer_ready,
output reg sata_busy,
input send_sync_escape,
input [15:0] user_features,
//XXX: New Stb
// input write_data_stb,
// input read_data_stb,
output hard_drive_error,
input execute_command_stb,
input command_layer_reset,
output reg pio_data_ready,
input [7:0] hard_drive_command,
input [15:0] sector_count,
input [47:0] sector_address,
input [31:0] user_din,
input user_din_stb,
output [1:0] user_din_ready,
input [1:0] user_din_activate,
output [23:0] user_din_size,
output user_din_empty,
output [31:0] user_dout,
output user_dout_ready,
input user_dout_activate,
input user_dout_stb,
output [23:0] user_dout_size,
//Transfer Layer Interface
input transport_layer_ready,
output reg sync_escape,
output t_send_command_stb,
output reg t_send_control_stb,
output t_send_data_stb,
input t_dma_activate_stb,
input t_d2h_reg_stb,
input t_pio_setup_stb,
input t_d2h_data_stb,
input t_dma_setup_stb,
input t_set_device_bits_stb,
input t_remote_abort,
input t_xmit_error,
input t_read_crc_error,
//PIO
input t_pio_response,
input t_pio_direction,
input [15:0] t_pio_transfer_count,
input [7:0] t_pio_e_status,
//Host to Device Register Values
output [7:0] h2d_command,
output reg [15:0] h2d_features,
output [7:0] h2d_control,
output [3:0] h2d_port_mult,
output [7:0] h2d_device,
output [47:0] h2d_lba,
output [15:0] h2d_sector_count,
//Device to Host Register Values
input d2h_interrupt,
input d2h_notification,
input [3:0] d2h_port_mult,
input [7:0] d2h_device,
input [47:0] d2h_lba,
input [15:0] d2h_sector_count,
input [7:0] d2h_status,
input [7:0] d2h_error,
output d2h_error_bbk, //Bad Block
output d2h_error_unc, //Uncorrectable Error
output d2h_error_mc, //Removable Media Error
output d2h_error_idnf, //request sector's ID Field could not be found
output d2h_error_mcr, //Removable Media Error
output d2h_error_abrt, //Abort (from invalid command, drive not ready, write fault)
output d2h_error_tk0nf, //Track 0 not found
output d2h_error_amnf, //Data Address Mark is not found after finding correct ID
output d2h_status_bsy, //Set to 1 when drive has access to command block, no other bits are valid when 1
// Set after reset
// Set after soft reset (srst)
// Set immediately after host writes to command register
output d2h_status_drdy, //Drive is ready to accept command
output d2h_status_dwf, //Drive Write Fault
output d2h_status_dsc, //Drive Seek Complete
output d2h_status_drq, //Data Request, Drive is ready to send data to the host
output d2h_status_corr, //Correctable Data bit (an error that was encountered but was corrected)
output d2h_status_idx, //once per disc revolution this bit is set to one then back to zero
output d2h_status_err, //error bit, if this bit is high check the error flags
//command layer data interface
input t_if_strobe,
output [31:0] t_if_data,
output t_if_ready,
input t_if_activate,
output [23:0] t_if_size,
input t_of_strobe,
input [31:0] t_of_data,
output [1:0] t_of_ready,
input [1:0] t_of_activate,
output [23:0] t_of_size,
//Debug
output [3:0] cl_c_state,
output [3:0] cl_w_state
);
//Parameters
parameter IDLE = 4'h0;
parameter PIO_WAIT_FOR_DATA = 4'h1;
parameter PIO_WRITE_DATA = 4'h2;
parameter WAIT_FOR_DMA_ACT = 4'h1;
parameter WAIT_FOR_WRITE_DATA = 4'h2;
parameter SEND_DATA = 4'h3;
//Registers/Wires
reg [3:0] cntrl_state;
reg srst;
reg [7:0] status;
wire idle;
reg cntrl_send_data_stb;
reg send_command_stb;
wire dev_busy;
wire dev_data_req;
//Write State Machine
reg [3:0] write_state;
reg dma_send_data_stb;
reg dma_act_detected_en;
reg enable_tl_data_ready;
//Ping Pong FIFOs
wire [1:0] if_write_ready;
wire [1:0] if_write_activate;
wire [23:0] if_write_size;
wire if_write_strobe;
wire [31:0] if_write_data;
wire if_read_strobe;
wire if_read_ready;
wire if_read_activate;
wire [23:0] if_read_size;
wire [31:0] if_read_data;
wire if_reset;
wire [31:0] of_write_data;
wire [1:0] of_write_ready;
wire [1:0] of_write_activate;
wire [23:0] of_read_size;
wire of_write_strobe;
wire out_fifo_starved;
wire of_read_ready;
wire [31:0] of_read_data;
wire of_read_activate;
wire [23:0] of_write_size;
wire of_read_strobe;
wire of_reset;
//ping pong FIFO
//Input FIFO
ppfifo # (
.DATA_WIDTH (`DATA_SIZE ),
.ADDRESS_WIDTH (`FIFO_ADDRESS_WIDTH )
) fifo_in (
.reset (if_reset ), //XXX: Veify that new PPFIFO doesn't need an external reset
//write side
//XXX: This can be different clocks
.write_clock (data_in_clk ),
.write_data (if_write_data ),
.write_ready (if_write_ready ),
.write_activate (if_write_activate ),
.write_fifo_size (if_write_size ),
.write_strobe (if_write_strobe ),
//.starved (if_starved ),
.starved (user_din_empty ),
//read side
//XXX: This can be different clocks
.read_clock (clk ),
.read_strobe (if_read_strobe ),
.read_ready (if_read_ready ),
.read_activate (if_read_activate ),
.read_count (if_read_size ),
.read_data (if_read_data ),
.inactive ( )
);
//Output FIFO
ppfifo # (
.DATA_WIDTH (`DATA_SIZE ),
.ADDRESS_WIDTH (`FIFO_ADDRESS_WIDTH )
) fifo_out (
.reset (of_reset ),
//.reset (0),
//write side
//XXX: This can be different clocks
.write_clock (clk ),
.write_data (of_write_data ),
.write_ready (of_write_ready ),
.write_activate (of_write_activate ),
.write_fifo_size (of_write_size ),
.write_strobe (of_write_strobe ),
//.starved (out_fifo_starved ),
.starved ( ),
//read side
//XXX: This can be different clocks
.read_clock (data_out_clk ),
.read_strobe (of_read_strobe ),
.read_ready (of_read_ready ),
.read_activate (of_read_activate ),
.read_count (of_read_size ),
.read_data (of_read_data ),
.inactive ( )
);
//Asynchronous Logic
//Attach output of Input FIFO to TL
assign t_if_ready = if_read_ready && enable_tl_data_ready;
assign t_if_size = if_read_size;
assign t_if_data = if_read_data;
assign if_read_activate = t_if_activate;
assign if_read_strobe = t_if_strobe;
//Attach input of output FIFO to TL
assign t_of_ready = of_write_ready;
//assign t_of_size = of_write_size;
assign t_of_size = 24'h00800;
assign of_write_data = t_of_data;
assign of_write_activate = t_of_activate;
assign of_write_strobe = t_of_strobe;
assign of_reset = (rst && data_out_clk_valid);
assign if_reset = (rst && data_in_clk_valid);
assign if_write_data = user_din;
assign if_write_strobe = user_din_stb;
assign user_din_ready = if_write_ready;
assign if_write_activate = user_din_activate;
assign user_din_size = if_write_size;
assign user_dout = of_read_data;
assign user_dout_ready = of_read_ready;
assign of_read_activate = user_dout_activate;
assign user_dout_size = of_read_size;
assign of_read_strobe = user_dout_stb;
assign d2h_status_bsy = d2h_status[7];
assign d2h_status_drdy = d2h_status[6];
assign d2h_status_dwf = d2h_status[5];
assign d2h_status_dsc = d2h_status[4];
assign d2h_status_drq = d2h_status[3];
assign d2h_status_corr = d2h_status[2];
assign d2h_status_idx = d2h_status[1];
assign d2h_status_err = d2h_status[0];
assign d2h_error_bbk = d2h_error[7];
assign d2h_error_unc = d2h_error[6];
assign d2h_error_mc = d2h_error[5];
assign d2h_error_idnf = d2h_error[4];
assign d2h_error_mcr = d2h_error[3];
assign d2h_error_abrt = d2h_error[2];
assign d2h_error_tk0nf = d2h_error[1];
assign d2h_error_amnf = d2h_error[0];
//Strobes
//assign t_send_command_stb = read_data_stb || write_data_stb || execute_command_stb;
assign t_send_command_stb = execute_command_stb;
assign t_send_data_stb = dma_send_data_stb ||cntrl_send_data_stb;
//IDLE
assign idle = (cntrl_state == IDLE) &&
(write_state == IDLE) &&
transport_layer_ready;
assign command_layer_ready = idle;
assign h2d_command = hard_drive_command;
assign h2d_sector_count = sector_count;
assign h2d_lba = sector_address;
//XXX: The individual bits should be controlled directly
assign h2d_control = {5'h00, srst, 2'b00};
//XXX: This should be controlled from a higher level
assign h2d_port_mult = 4'h0;
//XXX: This should be controlled from a higher level
assign h2d_device = `D2H_REG_DEVICE;
assign dev_busy = status[`STATUS_BUSY_BIT];
assign dev_data_req = status[`STATUS_DRQ_BIT];
assign hard_drive_error = status[`STATUS_ERR_BIT];
assign cl_c_state = cntrl_state;
assign cl_w_state = write_state;
//Synchronous Logic
//Control State Machine
always @ (posedge clk) begin
if (rst || (!linkup)) begin
cntrl_state <= IDLE;
h2d_features <= `D2H_REG_FEATURES;
srst <= 0;
//Strobes
t_send_control_stb <= 0;
cntrl_send_data_stb <= 0;
pio_data_ready <= 0;
status <= 0;
sata_busy <= 0;
sync_escape <= 0;
end
else begin
t_send_control_stb <= 0;
cntrl_send_data_stb <= 0;
pio_data_ready <= 0;
//Reset Count
if (t_d2h_reg_stb) begin
//Receiving a register strobe from the device
sata_busy <= 0;
h2d_features <= `D2H_REG_FEATURES;
end
/*
if (t_send_command_stb || t_send_control_stb) begin
sata_busy <= 1;
end
*/
if (execute_command_stb) begin
h2d_features <= user_features;
sata_busy <= 1;
end
case (cntrl_state)
IDLE: begin
//Soft Reset will break out of any flow
if (command_layer_reset && !srst) begin
srst <= 1;
t_send_control_stb <= 1;
end
if (idle) begin
//The only way to transition to another state is if CL is IDLE
//User Initiated commands
if (!command_layer_reset && srst) begin
srst <= 0;
t_send_control_stb <= 1;
end
end
//Device Initiated Transfers
if(t_pio_setup_stb) begin
if (t_pio_direction) begin
//Read from device
cntrl_state <= PIO_WAIT_FOR_DATA;
end
else begin
//Write to device
cntrl_state <= PIO_WRITE_DATA;
end
end
if (t_set_device_bits_stb) begin
status <= d2h_status;
//status register was updated
end
if (t_d2h_reg_stb) begin
status <= d2h_status;
end
end
PIO_WAIT_FOR_DATA: begin
if (t_d2h_data_stb) begin
//the next peice of data is related to the PIO
pio_data_ready <= 1;
cntrl_state <= IDLE;
status <= t_pio_e_status;
end
end
PIO_WRITE_DATA: begin
if (if_read_activate) begin
cntrl_send_data_stb <= 0;
cntrl_state <= IDLE;
status <= t_pio_e_status;
end
end
default: begin
cntrl_state <= IDLE;
end
endcase
if (send_sync_escape) begin
cntrl_state <= IDLE;
sync_escape <= 1;
sata_busy <= 0;
end
end
end
//Write State Machine
always @ (posedge clk) begin
if (rst || !linkup) begin
write_state <= IDLE;
dma_send_data_stb <= 0;
enable_tl_data_ready <= 0;
dma_act_detected_en <= 0;
end
else begin
dma_send_data_stb <= 0;
if (t_dma_activate_stb) begin
//Set an enable signal instead of a strobe so that there is no chance of missing this signal
dma_act_detected_en <= 1;
end
case (write_state)
IDLE: begin
enable_tl_data_ready <= 0;
if (idle) begin
//The only way to transition to another state is if CL is IDLE
//if (write_data_stb) begin
if (dma_act_detected_en) begin
//send a request to write data
write_state <= WAIT_FOR_DMA_ACT;
end
end
end
WAIT_FOR_DMA_ACT: begin
if (dma_act_detected_en) begin
dma_act_detected_en <= 0;
enable_tl_data_ready <= 1;
write_state <= WAIT_FOR_WRITE_DATA;
end
end
WAIT_FOR_WRITE_DATA: begin
if (if_read_activate) begin
enable_tl_data_ready <= 0;
write_state <= SEND_DATA;
end
end
SEND_DATA: begin
if (transport_layer_ready) begin
//Send the Data FIS
dma_send_data_stb <= 1;
dma_act_detected_en <= 0;
write_state <= IDLE;
end
end
default: begin
write_state <= IDLE;
end
endcase
//if (command_layer_reset || !reset_timeout) begin
if (command_layer_reset) begin
//Break out of the normal flow and return to IDLE
write_state <= IDLE;
end
if (t_d2h_reg_stb) begin
//Whenever I read a register transfer from the device I need to go back to IDLE
write_state <= IDLE;
end
if (send_sync_escape) begin
write_state <= IDLE;
end
end
end
endmodule |
module uart (
/********** ????a? & ???a? **********/
input wire clk, // ????a?
input wire reset, // ???????a?
/********** ?V?????????`?? **********/
input wire cs_, // ???a??????
input wire as_, // ??????????`??
input wire rw, // Read / Write
input wire [`UartAddrBus] addr, // ?????
input wire [`WordDataBus] wr_data, // ?????z???`??
output wire [`WordDataBus] rd_data, // ?i???????`??
output wire rdy_, // ????
/********** ????z?? **********/
output wire irq_rx, // ???????????z??
output wire irq_tx, // ???????????z??
/********** UART????????? **********/
input wire rx, // UART???????
output wire tx // UART???????
);
/********** ??????? **********/
// ????????
wire rx_busy; // ?????V??
wire rx_end; // ???????????
wire [`ByteDataBus] rx_data; // ?????`??
// ????????
wire tx_busy; // ?????V??
wire tx_end; // ???????????
wire tx_start; // ?????_????
wire [`ByteDataBus] tx_data; // ?????`??
/********** UART????????`?? **********/
uart_ctrl uart_ctrl (
/********** ????a? & ???a? **********/
.clk (clk), // ????a?
.reset (reset), // ???????a?
/********** Host Interface **********/
.cs_ (cs_), // ???a??????
.as_ (as_), // ??????????`??
.rw (rw), // Read / Write
.addr (addr), // ?????
.wr_data (wr_data), // ?????z???`??
.rd_data (rd_data), // ?i???????`??
.rdy_ (rdy_), // ????
/********** Interrupt **********/
.irq_rx (irq_rx), // ???????????z??
.irq_tx (irq_tx), // ???????????z??
/********** ??????? **********/
// ????????
.rx_busy (rx_busy), // ?????V??
.rx_end (rx_end), // ???????????
.rx_data (rx_data), // ?????`??
// ????????
.tx_busy (tx_busy), // ?????V??
.tx_end (tx_end), // ???????????
.tx_start (tx_start), // ?????_????
.tx_data (tx_data) // ?????`??
);
/********** UART???????`?? **********/
uart_tx uart_tx (
/********** ????a? & ???a? **********/
.clk (clk), // ????a?
.reset (reset), // ???????a?
/********** ??????? **********/
.tx_start (tx_start), // ?????_????
.tx_data (tx_data), // ?????`??
.tx_busy (tx_busy), // ?????V??
.tx_end (tx_end), // ???????????
/********** Transmit Signal **********/
.tx (tx) // UART???????
);
/********** UART???????`?? **********/
uart_rx uart_rx (
/********** ????a? & ???a? **********/
.clk (clk), // ????a?
.reset (reset), // ???????a?
/********** ??????? **********/
.rx_busy (rx_busy), // ?????V??
.rx_end (rx_end), // ???????????
.rx_data (rx_data), // ?????`??
/********** Receive Signal **********/
.rx (rx) // UART???????
);
endmodule |
module bus_master_mux (
/********** ÊäÈëÊä³öÐźŠ**********/
// 0ºÅ×ÜÏßÖ÷¿Ø
input wire [`WordAddrBus] m0_addr, // µØÖ·
input wire m0_as_, // µØַѡͨ
input wire m0_rw, // ¶Á/д
input wire [`WordDataBus] m0_wr_data, // дÈëµÄÊý¾Ý
input wire m0_grnt_, // ¸³Óè×ÜÏß
// 1ºÅ×ÜÏßÖ÷¿Ø
input wire [`WordAddrBus] m1_addr, // µØÖ·
input wire m1_as_, // µØַѡͨ
input wire m1_rw, // ¶Á/д
input wire [`WordDataBus] m1_wr_data, // дÈëµÄÊý¾Ý
input wire m1_grnt_, // ¸³Óè×ÜÏß
// 3ºÅ×ÜÏßÖ÷¿Ø
input wire [`WordAddrBus] m2_addr, // µØÖ·
input wire m2_as_, // µØַѡͨ
input wire m2_rw, // ¶Á/д
input wire [`WordDataBus] m2_wr_data, // дÈëµÄÊý¾Ý
input wire m2_grnt_, // ¸³Óè×ÜÏß
// 3ºÅ×ÜÏßÖ÷¿Ø
input wire [`WordAddrBus] m3_addr, // µØÖ·
input wire m3_as_, // µØַѡͨ
input wire m3_rw, // ¶Á/д
input wire [`WordDataBus] m3_wr_data, // дÈëµÄÊý¾Ý
input wire m3_grnt_, // ¸³Óè×ÜÏß
/********** ¹²ÏíÐźÅ×ÜÏß´ÓÊô **********/
output reg [`WordAddrBus] s_addr, // µØÖ·
output reg s_as_, // µØַѡͨ
output reg s_rw, // ¶Á/д
output reg [`WordDataBus] s_wr_data // дÈëµÄÊý¾Ý
);
/********** ×ÜÏßÖ÷¿Ø¶à·¸´ÓÃÆ÷ **********/
always @(*) begin
/* Ñ¡Ôñ³ÖÓÐ×ÜÏßʹÓÃȨµÄÖ÷¿Ø */
if (m0_grnt_ == `ENABLE_) begin // 0ºÅ×ÜÏß×Ü¿Ø
s_addr = m0_addr;
s_as_ = m0_as_;
s_rw = m0_rw;
s_wr_data = m0_wr_data;
end else if (m1_grnt_ == `ENABLE_) begin // 1ºÅ×ÜÏß×Ü¿Ø
s_addr = m1_addr;
s_as_ = m1_as_;
s_rw = m1_rw;
s_wr_data = m1_wr_data;
end else if (m2_grnt_ == `ENABLE_) begin // 2ºÅ×ÜÏß×Ü¿Ø
s_addr = m2_addr;
s_as_ = m2_as_;
s_rw = m2_rw;
s_wr_data = m2_wr_data;
end else if (m3_grnt_ == `ENABLE_) begin // 3ºÅ×ÜÏß×Ü¿Ø
s_addr = m3_addr;
s_as_ = m3_as_;
s_rw = m3_rw;
s_wr_data = m3_wr_data;
end else begin // ĬÈÏÖµ
s_addr = `WORD_ADDR_W'h0;
s_as_ = `DISABLE_;
s_rw = `READ;
s_wr_data = `WORD_DATA_W'h0;
end
end
endmodule |
module bus_addr_dec (
/********** µØÖ· **********/
input wire [`WordAddrBus] s_addr, // ×ÜÏß×Ü¿ØÌṩµÄµØÖ·ÐźÅ
/********** Êä³öƬѡÐźŠ**********/
output reg s0_cs_, // 0ºÅ×ÜÏß´ÓÊôƬѡÐźÅ
output reg s1_cs_, // 1ºÅ×ÜÏß´ÓÊôƬѡÐźÅ
output reg s2_cs_, // 2ºÅ×ÜÏß´ÓÊôƬѡÐźÅ
output reg s3_cs_, // 3ºÅ×ÜÏß´ÓÊôƬѡÐźÅ
output reg s4_cs_, // 4ºÅ×ÜÏß´ÓÊôƬѡÐźÅ
output reg s5_cs_, // 5ºÅ×ÜÏß´ÓÊôƬѡÐźÅ
output reg s6_cs_, // 6ºÅ×ÜÏß´ÓÊôƬѡÐźÅ
output reg s7_cs_ // 7ºÅ×ÜÏß´ÓÊôƬѡÐźÅ
);
/********** ×ÜÏß´ÓÊôË÷Òý **********/
wire [`BusSlaveIndexBus] s_index = s_addr[`BusSlaveIndexLoc]; // È¡µØÖ·Öиß3λ±íʾµÄ´ÓÊôºÅ
/********** ×ÜÏß´ÓÊô¶à·¸´ÓÃÆ÷**********/
always @(*) begin
/* ³õʼ»¯Æ¬Ñ¡ÐźŠ*/
s0_cs_ = `DISABLE_;
s1_cs_ = `DISABLE_;
s2_cs_ = `DISABLE_;
s3_cs_ = `DISABLE_;
s4_cs_ = `DISABLE_;
s5_cs_ = `DISABLE_;
s6_cs_ = `DISABLE_;
s7_cs_ = `DISABLE_;
/* Ñ¡ÔñµØÖ·¶ÔÓ¦µÄ´ÓÊô */
case (s_index)
`BUS_SLAVE_0 : begin // 0ºÅ×ÜÏß´ÓÊô
s0_cs_ = `ENABLE_;
end
`BUS_SLAVE_1 : begin // 1ºÅ×ÜÏß´ÓÊô
s1_cs_ = `ENABLE_;
end
`BUS_SLAVE_2 : begin // 2ºÅ×ÜÏß´ÓÊô
s2_cs_ = `ENABLE_;
end
`BUS_SLAVE_3 : begin // 0ºÅ×ÜÏß´ÓÊô
s3_cs_ = `ENABLE_;
end
`BUS_SLAVE_4 : begin // 4ºÅ×ÜÏß´ÓÊô
s4_cs_ = `ENABLE_;
end
`BUS_SLAVE_5 : begin // 5ºÅ×ÜÏß´ÓÊô
s5_cs_ = `ENABLE_;
end
`BUS_SLAVE_6 : begin // 6ºÅ×ÜÏß´ÓÊô
s6_cs_ = `ENABLE_;
end
`BUS_SLAVE_7 : begin // 7ºÅ×ÜÏß´ÓÊô
s7_cs_ = `ENABLE_;
end
endcase
end
endmodule |
module bus (
/********** ¥¯¥í¥Ã¥¯ & ¥ê¥»¥Ã¥È **********/
input wire clk, // ¥¯¥í¥Ã¥¯
input wire reset, // ·ÇͬÆڥꥻ¥Ã¥È
/********** ¥Ð¥¹¥Þ¥¹¥¿ÐźŠ**********/
// ¥Ð¥¹¥Þ¥¹¥¿¹²Í¨ÐźÅ
output wire [`WordDataBus] m_rd_data, // Õi¤ß³ö¤·¥Ç©`¥¿
output wire m_rdy_, // ¥ì¥Ç¥£
// ¥Ð¥¹¥Þ¥¹¥¿0·¬
input wire m0_req_, // ¥Ð¥¹¥ê¥¯¥¨¥¹¥È
input wire [`WordAddrBus] m0_addr, // ¥¢¥É¥ì¥¹
input wire m0_as_, // ¥¢¥É¥ì¥¹¥¹¥È¥í©`¥Ö
input wire m0_rw, // Õi¤ß£¯ø¤
input wire [`WordDataBus] m0_wr_data, // ø¤Þz¤ß¥Ç©`¥¿
output wire m0_grnt_, // ¥Ð¥¹¥°¥é¥ó¥È
// ¥Ð¥¹¥Þ¥¹¥¿1·¬
input wire m1_req_, // ¥Ð¥¹¥ê¥¯¥¨¥¹¥È
input wire [`WordAddrBus] m1_addr, // ¥¢¥É¥ì¥¹
input wire m1_as_, // ¥¢¥É¥ì¥¹¥¹¥È¥í©`¥Ö
input wire m1_rw, // Õi¤ß£¯ø¤
input wire [`WordDataBus] m1_wr_data, // ø¤Þz¤ß¥Ç©`¥¿
output wire m1_grnt_, // ¥Ð¥¹¥°¥é¥ó¥È
// ¥Ð¥¹¥Þ¥¹¥¿2·¬
input wire m2_req_, // ¥Ð¥¹¥ê¥¯¥¨¥¹¥È
input wire [`WordAddrBus] m2_addr, // ¥¢¥É¥ì¥¹
input wire m2_as_, // ¥¢¥É¥ì¥¹¥¹¥È¥í©`¥Ö
input wire m2_rw, // Õi¤ß£¯ø¤
input wire [`WordDataBus] m2_wr_data, // ø¤Þz¤ß¥Ç©`¥¿
output wire m2_grnt_, // ¥Ð¥¹¥°¥é¥ó¥È
// ¥Ð¥¹¥Þ¥¹¥¿3·¬
input wire m3_req_, // ¥Ð¥¹¥ê¥¯¥¨¥¹¥È
input wire [`WordAddrBus] m3_addr, // ¥¢¥É¥ì¥¹
input wire m3_as_, // ¥¢¥É¥ì¥¹¥¹¥È¥í©`¥Ö
input wire m3_rw, // Õi¤ß£¯ø¤
input wire [`WordDataBus] m3_wr_data, // ø¤Þz¤ß¥Ç©`¥¿
output wire m3_grnt_, // ¥Ð¥¹¥°¥é¥ó¥È
/********** ¥Ð¥¹¥¹¥ì©`¥ÖÐźŠ**********/
// ¥Ð¥¹¥¹¥ì©`¥Ö¹²Í¨ÐźÅ
output wire [`WordAddrBus] s_addr, // ¥¢¥É¥ì¥¹
output wire s_as_, // ¥¢¥É¥ì¥¹¥¹¥È¥í©`¥Ö
output wire s_rw, // Õi¤ß£¯ø¤
output wire [`WordDataBus] s_wr_data, // ø¤Þz¤ß¥Ç©`¥¿
// ¥Ð¥¹¥¹¥ì©`¥Ö0·¬
input wire [`WordDataBus] s0_rd_data, // Õi¤ß³ö¤·¥Ç©`¥¿
input wire s0_rdy_, // ¥ì¥Ç¥£
output wire s0_cs_, // ¥Á¥Ã¥×¥»¥ì¥¯¥È
// ¥Ð¥¹¥¹¥ì©`¥Ö1·¬
input wire [`WordDataBus] s1_rd_data, // Õi¤ß³ö¤·¥Ç©`¥¿
input wire s1_rdy_, // ¥ì¥Ç¥£
output wire s1_cs_, // ¥Á¥Ã¥×¥»¥ì¥¯¥È
// ¥Ð¥¹¥¹¥ì©`¥Ö2·¬
input wire [`WordDataBus] s2_rd_data, // Õi¤ß³ö¤·¥Ç©`¥¿
input wire s2_rdy_, // ¥ì¥Ç¥£
output wire s2_cs_, // ¥Á¥Ã¥×¥»¥ì¥¯¥È
// ¥Ð¥¹¥¹¥ì©`¥Ö3·¬
input wire [`WordDataBus] s3_rd_data, // Õi¤ß³ö¤·¥Ç©`¥¿
input wire s3_rdy_, // ¥ì¥Ç¥£
output wire s3_cs_, // ¥Á¥Ã¥×¥»¥ì¥¯¥È
// ¥Ð¥¹¥¹¥ì©`¥Ö4·¬
input wire [`WordDataBus] s4_rd_data, // Õi¤ß³ö¤·¥Ç©`¥¿
input wire s4_rdy_, // ¥ì¥Ç¥£
output wire s4_cs_, // ¥Á¥Ã¥×¥»¥ì¥¯¥È
// ¥Ð¥¹¥¹¥ì©`¥Ö5·¬
input wire [`WordDataBus] s5_rd_data, // Õi¤ß³ö¤·¥Ç©`¥¿
input wire s5_rdy_, // ¥ì¥Ç¥£
output wire s5_cs_, // ¥Á¥Ã¥×¥»¥ì¥¯¥È
// ¥Ð¥¹¥¹¥ì©`¥Ö6·¬
input wire [`WordDataBus] s6_rd_data, // Õi¤ß³ö¤·¥Ç©`¥¿
input wire s6_rdy_, // ¥ì¥Ç¥£
output wire s6_cs_, // ¥Á¥Ã¥×¥»¥ì¥¯¥È
// ¥Ð¥¹¥¹¥ì©`¥Ö7·¬
input wire [`WordDataBus] s7_rd_data, // Õi¤ß³ö¤·¥Ç©`¥¿
input wire s7_rdy_, // ¥ì¥Ç¥£
output wire s7_cs_ // ¥Á¥Ã¥×¥»¥ì¥¯¥È
);
/********** ¥Ð¥¹¥¢©`¥Ó¥¿ **********/
bus_arbiter bus_arbiter (
/********** ¥¯¥í¥Ã¥¯ & ¥ê¥»¥Ã¥È **********/
.clk (clk), // ¥¯¥í¥Ã¥¯
.reset (reset), // ·ÇͬÆڥꥻ¥Ã¥È
/********** ¥¢©`¥Ó¥È¥ì©`¥·¥ç¥óÐźŠ**********/
// ¥Ð¥¹¥Þ¥¹¥¿0·¬
.m0_req_ (m0_req_), // ¥Ð¥¹¥ê¥¯¥¨¥¹¥È
.m0_grnt_ (m0_grnt_), // ¥Ð¥¹¥°¥é¥ó¥È
// ¥Ð¥¹¥Þ¥¹¥¿1·¬
.m1_req_ (m1_req_), // ¥Ð¥¹¥ê¥¯¥¨¥¹¥È
.m1_grnt_ (m1_grnt_), // ¥Ð¥¹¥°¥é¥ó¥È
// ¥Ð¥¹¥Þ¥¹¥¿2·¬
.m2_req_ (m2_req_), // ¥Ð¥¹¥ê¥¯¥¨¥¹¥È
.m2_grnt_ (m2_grnt_), // ¥Ð¥¹¥°¥é¥ó¥È
// ¥Ð¥¹¥Þ¥¹¥¿3·¬
.m3_req_ (m3_req_), // ¥Ð¥¹¥ê¥¯¥¨¥¹¥È
.m3_grnt_ (m3_grnt_) // ¥Ð¥¹¥°¥é¥ó¥È
);
/********** ¥Ð¥¹¥Þ¥¹¥¿¥Þ¥ë¥Á¥×¥ì¥¯¥µ **********/
bus_master_mux bus_master_mux (
/********** ¥Ð¥¹¥Þ¥¹¥¿ÐźŠ**********/
// ¥Ð¥¹¥Þ¥¹¥¿0·¬
.m0_addr (m0_addr), // ¥¢¥É¥ì¥¹
.m0_as_ (m0_as_), // ¥¢¥É¥ì¥¹¥¹¥È¥í©`¥Ö
.m0_rw (m0_rw), // Õi¤ß£¯ø¤
.m0_wr_data (m0_wr_data), // ø¤Þz¤ß¥Ç©`¥¿
.m0_grnt_ (m0_grnt_), // ¥Ð¥¹¥°¥é¥ó¥È
// ¥Ð¥¹¥Þ¥¹¥¿1·¬
.m1_addr (m1_addr), // ¥¢¥É¥ì¥¹
.m1_as_ (m1_as_), // ¥¢¥É¥ì¥¹¥¹¥È¥í©`¥Ö
.m1_rw (m1_rw), // Õi¤ß£¯ø¤
.m1_wr_data (m1_wr_data), // ø¤Þz¤ß¥Ç©`¥¿
.m1_grnt_ (m1_grnt_), // ¥Ð¥¹¥°¥é¥ó¥È
// ¥Ð¥¹¥Þ¥¹¥¿2·¬
.m2_addr (m2_addr), // ¥¢¥É¥ì¥¹
.m2_as_ (m2_as_), // ¥¢¥É¥ì¥¹¥¹¥È¥í©`¥Ö
.m2_rw (m2_rw), // Õi¤ß£¯ø¤
.m2_wr_data (m2_wr_data), // ø¤Þz¤ß¥Ç©`¥¿
.m2_grnt_ (m2_grnt_), // ¥Ð¥¹¥°¥é¥ó¥È
// ¥Ð¥¹¥Þ¥¹¥¿3·¬
.m3_addr (m3_addr), // ¥¢¥É¥ì¥¹
.m3_as_ (m3_as_), // ¥¢¥É¥ì¥¹¥¹¥È¥í©`¥Ö
.m3_rw (m3_rw), // Õi¤ß£¯ø¤
.m3_wr_data (m3_wr_data), // ø¤Þz¤ß¥Ç©`¥¿
.m3_grnt_ (m3_grnt_), // ¥Ð¥¹¥°¥é¥ó¥È
/********** ¥Ð¥¹¥¹¥ì©`¥Ö¹²Í¨ÐźŠ**********/
.s_addr (s_addr), // ¥¢¥É¥ì¥¹
.s_as_ (s_as_), // ¥¢¥É¥ì¥¹¥¹¥È¥í©`¥Ö
.s_rw (s_rw), // Õi¤ß£¯ø¤
.s_wr_data (s_wr_data) // ø¤Þz¤ß¥Ç©`¥¿
);
/********** ¥¢¥É¥ì¥¹¥Ç¥³©`¥À **********/
bus_addr_dec bus_addr_dec (
/********** ¥¢¥É¥ì¥¹ **********/
.s_addr (s_addr), // ¥¢¥É¥ì¥¹
/********** ¥Á¥Ã¥×¥»¥ì¥¯¥È **********/
.s0_cs_ (s0_cs_), // ¥Ð¥¹¥¹¥ì©`¥Ö0·¬
.s1_cs_ (s1_cs_), // ¥Ð¥¹¥¹¥ì©`¥Ö1·¬
.s2_cs_ (s2_cs_), // ¥Ð¥¹¥¹¥ì©`¥Ö2·¬
.s3_cs_ (s3_cs_), // ¥Ð¥¹¥¹¥ì©`¥Ö3·¬
.s4_cs_ (s4_cs_), // ¥Ð¥¹¥¹¥ì©`¥Ö4·¬
.s5_cs_ (s5_cs_), // ¥Ð¥¹¥¹¥ì©`¥Ö5·¬
.s6_cs_ (s6_cs_), // ¥Ð¥¹¥¹¥ì©`¥Ö6·¬
.s7_cs_ (s7_cs_) // ¥Ð¥¹¥¹¥ì©`¥Ö7·¬
);
/********** ¥Ð¥¹¥¹¥ì©`¥Ö¥Þ¥ë¥Á¥×¥ì¥¯¥µ **********/
bus_slave_mux bus_slave_mux (
/********** ¥Á¥Ã¥×¥»¥ì¥¯¥È **********/
.s0_cs_ (s0_cs_), // ¥Ð¥¹¥¹¥ì©`¥Ö0·¬
.s1_cs_ (s1_cs_), // ¥Ð¥¹¥¹¥ì©`¥Ö1·¬
.s2_cs_ (s2_cs_), // ¥Ð¥¹¥¹¥ì©`¥Ö2·¬
.s3_cs_ (s3_cs_), // ¥Ð¥¹¥¹¥ì©`¥Ö3·¬
.s4_cs_ (s4_cs_), // ¥Ð¥¹¥¹¥ì©`¥Ö4·¬
.s5_cs_ (s5_cs_), // ¥Ð¥¹¥¹¥ì©`¥Ö5·¬
.s6_cs_ (s6_cs_), // ¥Ð¥¹¥¹¥ì©`¥Ö6·¬
.s7_cs_ (s7_cs_), // ¥Ð¥¹¥¹¥ì©`¥Ö7·¬
/********** ¥Ð¥¹¥¹¥ì©`¥ÖÐźŠ**********/
// ¥Ð¥¹¥¹¥ì©`¥Ö0·¬
.s0_rd_data (s0_rd_data), // Õi¤ß³ö¤·¥Ç©`¥¿
.s0_rdy_ (s0_rdy_), // ¥ì¥Ç¥£
// ¥Ð¥¹¥¹¥ì©`¥Ö1·¬
.s1_rd_data (s1_rd_data), // Õi¤ß³ö¤·¥Ç©`¥¿
.s1_rdy_ (s1_rdy_), // ¥ì¥Ç¥£
// ¥Ð¥¹¥¹¥ì©`¥Ö2·¬
.s2_rd_data (s2_rd_data), // Õi¤ß³ö¤·¥Ç©`¥¿
.s2_rdy_ (s2_rdy_), // ¥ì¥Ç¥£
// ¥Ð¥¹¥¹¥ì©`¥Ö3·¬
.s3_rd_data (s3_rd_data), // Õi¤ß³ö¤·¥Ç©`¥¿
.s3_rdy_ (s3_rdy_), // ¥ì¥Ç¥£
// ¥Ð¥¹¥¹¥ì©`¥Ö4·¬
.s4_rd_data (s4_rd_data), // Õi¤ß³ö¤·¥Ç©`¥¿
.s4_rdy_ (s4_rdy_), // ¥ì¥Ç¥£
// ¥Ð¥¹¥¹¥ì©`¥Ö5·¬
.s5_rd_data (s5_rd_data), // Õi¤ß³ö¤·¥Ç©`¥¿
.s5_rdy_ (s5_rdy_), // ¥ì¥Ç¥£
// ¥Ð¥¹¥¹¥ì©`¥Ö6·¬
.s6_rd_data (s6_rd_data), // Õi¤ß³ö¤·¥Ç©`¥¿
.s6_rdy_ (s6_rdy_), // ¥ì¥Ç¥£
// ¥Ð¥¹¥¹¥ì©`¥Ö7·¬
.s7_rd_data (s7_rd_data), // Õi¤ß³ö¤·¥Ç©`¥¿
.s7_rdy_ (s7_rdy_), // ¥ì¥Ç¥£
/********** ¥Ð¥¹¥Þ¥¹¥¿¹²Í¨ÐźŠ**********/
.m_rd_data (m_rd_data), // Õi¤ß³ö¤·¥Ç©`¥¿
.m_rdy_ (m_rdy_) // ¥ì¥Ç¥£
);
endmodule |
module bus_slave_mux (
/********** ÊäÈëÐźŠ**********/
input wire s0_cs_, // 0ºÅ×ÜÏß´ÓÊôƬѡ
input wire s1_cs_, // 1ºÅ×ÜÏß´ÓÊôƬѡ
input wire s2_cs_, // 2ºÅ×ÜÏß´ÓÊôƬѡ
input wire s3_cs_, // 3ºÅ×ÜÏß´ÓÊôƬѡ
input wire s4_cs_, // 4ºÅ×ÜÏß´ÓÊôƬѡ
input wire s5_cs_, // 5ºÅ×ÜÏß´ÓÊôƬѡ
input wire s6_cs_, // 6ºÅ×ÜÏß´ÓÊôƬѡ
input wire s7_cs_, // 7ºÅ×ÜÏß´ÓÊôƬѡ
/********** ¥Ð¥¹¥¹¥ì©`¥ÖÐźŠ**********/
// 0ºÅ×ÜÏß´ÓÊô
input wire [`WordDataBus] s0_rd_data, // ¶Á³öµÄÊý¾Ý
input wire s0_rdy_, // ¾ÍÐ÷
// 1ºÅ×ÜÏß´ÓÊô
input wire [`WordDataBus] s1_rd_data, // ¶Á³öµÄÊý¾Ý
input wire s1_rdy_, // ¾ÍÐ÷
// 2ºÅ×ÜÏß´ÓÊô
input wire [`WordDataBus] s2_rd_data, // ¶Á³öµÄÊý¾Ý
input wire s2_rdy_, // ¾ÍÐ÷
// 3ºÅ×ÜÏß´ÓÊô
input wire [`WordDataBus] s3_rd_data, // ¶Á³öµÄÊý¾Ý
input wire s3_rdy_, // ¾ÍÐ÷
// 4ºÅ×ÜÏß´ÓÊô
input wire [`WordDataBus] s4_rd_data, // ¶Á³öµÄÊý¾Ý
input wire s4_rdy_, // ¾ÍÐ÷
// 5ºÅ×ÜÏß´ÓÊô
input wire [`WordDataBus] s5_rd_data, // ¶Á³öµÄÊý¾Ý
input wire s5_rdy_, // ¾ÍÐ÷
// 6ºÅ×ÜÏß´ÓÊô
input wire [`WordDataBus] s6_rd_data, // ¶Á³öµÄÊý¾Ý
input wire s6_rdy_, // ¾ÍÐ÷
// 7ºÅ×ÜÏß´ÓÊô
input wire [`WordDataBus] s7_rd_data, // ¶Á³öµÄÊý¾Ý
input wire s7_rdy_, // ¾ÍÐ÷
/********** ×ÜÏßÖ÷¿Ø¹²ÏíÐźŠ**********/
output reg [`WordDataBus] m_rd_data, // ¶Á³öµÄÊý¾Ý
output reg m_rdy_ // ¾ÍÐ÷
);
/********** ×ÜÏß´ÓÊô¶à·¸´ÓÃÆ÷ **********/
always @(*) begin
/* Ñ¡ÔñƬѡÐźŶÔÓ¦µÄ´ÓÊô */
if (s0_cs_ == `ENABLE_) begin // ·ÃÎÊ0ºÅ×ÜÏß´ÓÊô
m_rd_data = s0_rd_data;
m_rdy_ = s0_rdy_;
end else if (s1_cs_ == `ENABLE_) begin // ·ÃÎÊ1ºÅ×ÜÏß´ÓÊô
m_rd_data = s1_rd_data;
m_rdy_ = s1_rdy_;
end else if (s2_cs_ == `ENABLE_) begin // ·ÃÎÊ2ºÅ×ÜÏß´ÓÊô
m_rd_data = s2_rd_data;
m_rdy_ = s2_rdy_;
end else if (s3_cs_ == `ENABLE_) begin // ·ÃÎÊ3ºÅ×ÜÏß´ÓÊô
m_rd_data = s3_rd_data;
m_rdy_ = s3_rdy_;
end else if (s4_cs_ == `ENABLE_) begin // ·ÃÎÊ4ºÅ×ÜÏß´ÓÊô
m_rd_data = s4_rd_data;
m_rdy_ = s4_rdy_;
end else if (s5_cs_ == `ENABLE_) begin // ·ÃÎÊ5ºÅ×ÜÏß´ÓÊô
m_rd_data = s5_rd_data;
m_rdy_ = s5_rdy_;
end else if (s6_cs_ == `ENABLE_) begin // ·ÃÎÊ6ºÅ×ÜÏß´ÓÊô
m_rd_data = s6_rd_data;
m_rdy_ = s6_rdy_;
end else if (s7_cs_ == `ENABLE_) begin // ·ÃÎÊ7ºÅ×ÜÏß´ÓÊô
m_rd_data = s7_rd_data;
m_rdy_ = s7_rdy_;
end else begin // ĬÈÏÖµ
m_rd_data = `WORD_DATA_W'h0;
m_rdy_ = `DISABLE_;
end
end
endmodule |
module clk_gen (
/********** ʱÖÓÓ븴λ **********/
input wire clk_ref, // »ù±¾Ê±ÖÓ
input wire reset_sw, // È«¾Ö¸´Î»
/********** Éú³ÉʱÖÓ **********/
output wire clk, // ʱÖÓ
output wire clk_, // ·´ÏàʱÖÓ
/********** оƬ¸´Î» **********/
output wire chip_reset // оƬ¸´Î»
);
/********** ÄÚ²¿ÐźŠ**********/
wire locked; // Ëø¶¨ÐźÅ
wire dcm_reset; // dcm ¸´Î»
/********** ²úÉú¸´Î» **********/
// DCM¸´Î»
assign dcm_reset = (reset_sw == `RESET_ENABLE) ? `ENABLE : `DISABLE;
// оƬ¸´Î»
assign chip_reset = ((reset_sw == `RESET_ENABLE) || (locked == `DISABLE)) ?
`RESET_ENABLE : `RESET_DISABLE;
/********** Xilinx DCM (Digitl Clock Manager) -> altera pll**********/
/* x_s3e_dcm x_s3e_dcm (
.CLKIN_IN (clk_ref), // »ù±¾Ê±ÖÓ
.RST_IN (dcm_reset), // DCM¸´Î»
.CLK0_OUT (clk), // ʱÖÓ
.CLK180_OUT (clk_), // ·´ÏàʱÖÓ
.LOCKED_OUT (locked) // Ëø¶¨
);
*/
altera_dcm x_s3e_dcm (
.inclk0 (clk_ref), // »ù±¾Ê±ÖÓ
.areset (dcm_reset), // DCM¸´Î»
.c0 (clk), // ʱÖÓ
.c1 (clk_), // ·´ÏàʱÖÓ
.locked (locked) // Ëø¶¨
);
endmodule |
module chip (
/********** ʱÖÓÓ븴λ **********/
input wire clk, // ʱÖÓ
input wire clk_, // ·´ÏàʱÖÓ
input wire reset // ¸´Î»
/********** UART **********/
`ifdef IMPLEMENT_UART // UARTʵÏÖ
, input wire uart_rx // UART½ÓÊÕÐźÅ
, output wire uart_tx // UART·¢ËÍÐźÅ
`endif
/********** ͨÓÃI/ O¶Ë¿Ú **********/
`ifdef IMPLEMENT_GPIO //GPIOʵÏÖ
`ifdef GPIO_IN_CH // ÊäÈë½Ó¿ÚʵÏÖ
, input wire [`GPIO_IN_CH-1:0] gpio_in // ÊäÈë½Ó¿Ú
`endif
`ifdef GPIO_OUT_CH // Êä³ö½Ó¿ÚʵÏÖ
, output wire [`GPIO_OUT_CH-1:0] gpio_out // Êä³ö½Ó¿Ú
`endif
`ifdef GPIO_IO_CH // ÊäÈëÊä³ö½Ó¿ÚʵÏÖ
, inout wire [`GPIO_IO_CH-1:0] gpio_io // ÊäÈëÊä³ö½Ó¿Ú
`endif
`endif
);
/********** ×ÜÏßÐźŠ**********/
// ×ÜÏßÖ÷¿ØÐźÅ
wire [`WordDataBus] m_rd_data; // ¶ÁÈ¡Êý¾Ý
wire m_rdy_; // ¥ì¥Ç¥£
// ×ÜÏßÖ÷¿Ø0
wire m0_req_; // ×ÜÏßÇëÇó
wire [`WordAddrBus] m0_addr; // µØÖ·
wire m0_as_; // µØַѡͨ
wire m0_rw; // ¶Á/д
wire [`WordDataBus] m0_wr_data; // Êý¾Ý
wire m0_grnt_; // ×ÜÏßÊÚȨ
// ×ÜÏßÖ÷¿Ø1
wire m1_req_; // ×ÜÏßÇëÇó
wire [`WordAddrBus] m1_addr; // µØÖ·
wire m1_as_; // µØַѡͨ
wire m1_rw; // ¶Á/д
wire [`WordDataBus] m1_wr_data; // Êý¾Ý
wire m1_grnt_; // ×ÜÏßÊÚȨ
// ×ÜÏßÖ÷¿Ø2
wire m2_req_; // ×ÜÏßÇëÇó
wire [`WordAddrBus] m2_addr; // µØÖ·
wire m2_as_; // µØַѡͨ
wire m2_rw; // ¶Á/д
wire [`WordDataBus] m2_wr_data; // Êý¾Ý
wire m2_grnt_; // ×ÜÏßÊÚȨ
// ×ÜÏßÖ÷¿Ø3
wire m3_req_; // ×ÜÏßÇëÇó
wire [`WordAddrBus] m3_addr; // µØÖ·
wire m3_as_; // µØַѡͨ
wire m3_rw; // ¶Á/д
wire [`WordDataBus] m3_wr_data; // Êý¾Ý
wire m3_grnt_; // ×ÜÏßÊÚȨ
/********** ×ÜÏß´ÓÉ豸ÐźÅ**********/
//ËùÓдÓÉ豸¹²ÓÃÐźÅ
wire [`WordAddrBus] s_addr; // µØÖ·
wire s_as_; // µØַѡͨ
wire s_rw; // ¶Á/д
wire [`WordDataBus] s_wr_data; // дÈëÊý¾Ý
// 0ºÅ×ÜÏß´ÓÉ豸
wire [`WordDataBus] s0_rd_data; // ¶ÁÈ¡Êý¾Ý
wire s0_rdy_; // ¾ÍÐ÷
wire s0_cs_; // Ƭѡ
// 1ºÅ×ÜÏß´ÓÉ豸
wire [`WordDataBus] s1_rd_data; // ¶ÁÈ¡Êý¾Ý
wire s1_rdy_; // ¾ÍÐ÷
wire s1_cs_; // Ƭѡ
// 2ºÅ×ÜÏß´ÓÉ豸
wire [`WordDataBus] s2_rd_data; // ¶ÁÈ¡Êý¾Ý
wire s2_rdy_; // ¾ÍÐ÷
wire s2_cs_; // Ƭѡ
// 3ºÅ×ÜÏß´ÓÉ豸
wire [`WordDataBus] s3_rd_data; // ¶ÁÈ¡Êý¾Ý
wire s3_rdy_; // ¾ÍÐ÷
wire s3_cs_; // Ƭѡ
// 4ºÅ×ÜÏß´ÓÉ豸
wire [`WordDataBus] s4_rd_data; // ¶ÁÈ¡Êý¾Ý
wire s4_rdy_; // ¾ÍÐ÷
wire s4_cs_; // Ƭѡ
// 5ºÅ×ÜÏß´ÓÉ豸
wire [`WordDataBus] s5_rd_data; // ¶ÁÈ¡Êý¾Ý
wire s5_rdy_; // ¾ÍÐ÷
wire s5_cs_; // Ƭѡ
// 6ºÅ×ÜÏß´ÓÉ豸
wire [`WordDataBus] s6_rd_data; // ¶ÁÈ¡Êý¾Ý
wire s6_rdy_; // ¾ÍÐ÷
wire s6_cs_; // Ƭѡ
// 7ºÅ×ÜÏß´ÓÉ豸
wire [`WordDataBus] s7_rd_data; // ¶ÁÈ¡Êý¾Ý
wire s7_rdy_; // ¾ÍÐ÷
wire s7_cs_; // Ƭѡ
/**********ÖжÏÇëÇóÐźŠ**********/
wire irq_timer; // ¶¨Ê±Æ÷ÖжÏ
wire irq_uart_rx; // UART IRQ£¨¶ÁÈ¡£©
wire irq_uart_tx; // UART IRQ£¨·¢ËÍ£©
wire [`CPU_IRQ_CH-1:0] cpu_irq; // CPU IRQ
assign cpu_irq = {{`CPU_IRQ_CH-3{`LOW}},
irq_uart_rx, irq_uart_tx, irq_timer};
/********** CPU **********/
cpu cpu (
/********** ʱÖÓÓ븴λ **********/
.clk (clk), // ʱÖÓ
.clk_ (clk_), // ·´ÏàʱÖÓ
.reset (reset), // ¸´Î»
/********** ×ÜÏß½Ó¿Ú **********/
// IF Stage Ö¸Áî¶ÁÈ¡--×ÜÏßÖ÷¿Ø0
.if_bus_rd_data (m_rd_data), // ¶Á³öµÄÊý¾Ý
.if_bus_rdy_ (m_rdy_), // ¾ÍÐ÷
.if_bus_grnt_ (m0_grnt_), // ×ÜÏßÊÚȨ
.if_bus_req_ (m0_req_), // ÇëÇó×ÜÏß
.if_bus_addr (m0_addr), // µØÖ·
.if_bus_as_ (m0_as_), // µØַѡͨ
.if_bus_rw (m0_rw), // ¶Á/д
.if_bus_wr_data (m0_wr_data), // дÈëµÄÊý¾Ý
// MEM Stage ÄÚ´æ·ÃÎÊ--×ÜÏßÖ÷¿Ø1
.mem_bus_rd_data (m_rd_data), // ¶Á³öµÄÊý¾Ý
.mem_bus_rdy_ (m_rdy_), // ¾ÍÐ÷
.mem_bus_grnt_ (m1_grnt_), // ×ÜÏßÊÚȨ
.mem_bus_req_ (m1_req_), // ÇëÇó×ÜÏß
.mem_bus_addr (m1_addr), // µØÖ·
.mem_bus_as_ (m1_as_), // µØַѡͨ
.mem_bus_rw (m1_rw), // ¶Á/д
.mem_bus_wr_data (m1_wr_data), // дÈëµÄÊý¾Ý
/********** ÖÐ¶Ï **********/
.cpu_irq (cpu_irq) // ÖжÏÇëÇó
);
/********** ×ÜÏßÖ÷¿Ø2 : δg×° **********/
assign m2_addr = `WORD_ADDR_W'h0;
assign m2_as_ = `DISABLE_;
assign m2_rw = `READ;
assign m2_wr_data = `WORD_DATA_W'h0;
assign m2_req_ = `DISABLE_;
/********** ×ÜÏßÖ÷¿Ø 3 : δg×° **********/
assign m3_addr = `WORD_ADDR_W'h0;
assign m3_as_ = `DISABLE_;
assign m3_rw = `READ;
assign m3_wr_data = `WORD_DATA_W'h0;
assign m3_req_ = `DISABLE_;
/********** ×ÜÏß´ÓÉ豸 0 : ROM **********/
rom rom (
/********** Clock & Reset **********/
.clk (clk), // ʱÖÓ
.reset (reset), // Òì²½¸´Î»
/**********×ÜÏß½Ó¿Ú **********/
.cs_ (s0_cs_), // Ƭѡ
.as_ (s_as_), // µØַѡͨ
.addr (s_addr[`RomAddrLoc]), // µØÖ·
.rd_data (s0_rd_data), // ¶Á³öµÄÊý¾Ý
.rdy_ (s0_rdy_) // ¾ÍÐ÷
);
/********** ×ÜÏß´ÓÉ豸 1 : Scratch Pad Memory£¬±¾·½°¸ÖÐRAM²»Í¨¹ý×ÜÏßÖ±½Ó·½·¨ **********/
assign s1_rd_data = `WORD_DATA_W'h0;
assign s1_rdy_ = `DISABLE_;
/********** ×ÜÏß´ÓÉ豸 2 : ¶¨Ê±Æ÷ **********/
`ifdef IMPLEMENT_TIMER // ¶¨Ê±Æ÷ѡװ
timer timer (
/********** ʱÖÓÓ븴λ **********/
.clk (clk), // ʱÖÓ
.reset (reset), // Òì²½¸´Î»
/********** ×ÜÏß½Ó¿Ú **********/
.cs_ (s2_cs_), // Ƭѡ
.as_ (s_as_), // µØַѡͨ
.addr (s_addr[`TimerAddrLoc]), // µØÖ·
.rw (s_rw), // ¶Á/д
.wr_data (s_wr_data), // дÈëµÄÊý¾Ý
.rd_data (s2_rd_data), // ¶Á³öµÄÊý¾Ý
.rdy_ (s2_rdy_), // ¾ÍÐ÷
/********** ÖÐ¶Ï **********/
.irq (irq_timer) // ¶¨Ê±Æ÷ÖжÏÇëÇó
);
`else // ¶¨Ê±Æ÷δѡװ
assign s2_rd_data = `WORD_DATA_W'h0;
assign s2_rdy_ = `DISABLE_;
assign irq_timer = `DISABLE;
`endif
/********** ×ÜÏß´ÓÉ豸 3 : UART **********/
`ifdef IMPLEMENT_UART // UARTѡװ
uart uart (
/********** ʱÖÓÓ븴λ **********/
.clk (clk), // ʱÖÓ
.reset (reset), // Òì²½¸´Î»
/********** ×ÜÏß½Ó¿Ú **********/
.cs_ (s3_cs_), // Ƭѡ
.as_ (s_as_), // µØַѡͨ
.rw (s_rw), // ¶Á/д
.addr (s_addr[`UartAddrLoc]), // µØÖ·
.wr_data (s_wr_data), // дÈëµÄÊý¾Ý
.rd_data (s3_rd_data), // ¶Á³öµÄÊý¾Ý
.rdy_ (s3_rdy_), // ¾ÍÐ÷
/********** ÖÐ¶Ï **********/
.irq_rx (irq_uart_rx), // ½ÓÊÕÍê³ÉÖжÏÇëÇó
.irq_tx (irq_uart_tx), // ·¢ËÍÍê³ÉÖжÏÇëÇó
/********** UARTÊÕ·¢Ðźţ¬Í¨¹ýFPGAÒý½ÅΪTTLµçƽ£¬Èç¹ûͨ¹ý´®¿Ú½ÓÔòΪRS232µçƽ **********/
.rx (uart_rx), // UART½ÓÊÕÐźţ¬Òý½ÅÔ¼ÊøʱעÒâ
.tx (uart_tx) // UART·¢ËÍÐźţ¬Òý½ÅÔ¼ÊøʱעÒâ
);
`else // UARTδѡװ
assign s3_rd_data = `WORD_DATA_W'h0;
assign s3_rdy_ = `DISABLE_;
assign irq_uart_rx = `DISABLE;
assign irq_uart_tx = `DISABLE;
`endif
/********** ×ÜÏß´ÓÉ豸 4 : GPIO **********/
`ifdef IMPLEMENT_GPIO // GPIOѡװ
gpio gpio (
/********** ʱÖÓÓ븴λ **********/
.clk (clk), // ʱÖÓ
.reset (reset), // Òì²½¸´Î»
/********** ×ÜÏß½Ó¿Ú **********/
.cs_ (s4_cs_), // Ƭѡ
.as_ (s_as_), // µØַѡͨ
.rw (s_rw), // ¶Á/д
.addr (s_addr[`GpioAddrLoc]), // µØÖ·
.wr_data (s_wr_data), // дÈëµÄÊý¾Ý
.rd_data (s4_rd_data), // ¶Á³öµÄÊý¾Ý
.rdy_ (s4_rdy_) // ¾ÍÐ÷
/********** GPIO ¶Ë¿Ú **********/
`ifdef GPIO_IN_CH // ѡװÊäÈë¿Ú
, .gpio_in (~gpio_in) // ÊäÈë¿Ú,zhangly×¢£º±©·ç°åÉÏÒý½ÅÔ¼Êøµ½Ëĸö¸ºÂß¼µÄ°´Å¥£¬¹ÊÈ¡·´
`endif
`ifdef GPIO_OUT_CH // ѡװÊä³ö¿Ú
, .gpio_out (gpio_out) // Êä³ö¿Ú
`endif
`ifdef GPIO_IO_CH // ѡװÁËÊäÈëÊä³ö
, .gpio_io (gpio_io) // ÊäÈëÊä³ö¿Ú
`endif
);
`else // GPIOûѡװ
assign s4_rd_data = `WORD_DATA_W'h0;
assign s4_rdy_ = `DISABLE_;
`endif
/********** ×ÜÏß´ÓÉ豸 5 : ûѡװ **********/
assign s5_rd_data = `WORD_DATA_W'h0;
assign s5_rdy_ = `DISABLE_;
/********** ×ÜÏß´ÓÉ豸 6 : ûѡװ **********/
assign s6_rd_data = `WORD_DATA_W'h0;
assign s6_rdy_ = `DISABLE_;
/********** ×ÜÏß´ÓÉ豸 7 : ûѡװ **********/
assign s7_rd_data = `WORD_DATA_W'h0;
assign s7_rdy_ = `DISABLE_;
/********** ×ÜÏß **********/
bus bus (
/********** ʱÖÓÓ븴λ **********/
.clk (clk), // ʱÖÓ
.reset (reset), // Òì²½¸´Î»
/********** ×ÜÏßÖ÷¿ØÐźŠ**********/
// ËùÓÐ×ÜÏßÖ÷¿Ø¹²ÓÃÐźÅ
.m_rd_data (m_rd_data), // ¶Á³öµÄÊý¾Ý
.m_rdy_ (m_rdy_), // ¾ÍÐ÷
// 0ºÅ×ÜÏßÖ÷¿Ø
.m0_req_ (m0_req_), // ÇëÇó×ÜÏß
.m0_addr (m0_addr), // µØÖ·
.m0_as_ (m0_as_), // µØַѡͨ
.m0_rw (m0_rw), // ¶Á/д
.m0_wr_data (m0_wr_data), // дÈëµÄÊý¾Ý
.m0_grnt_ (m0_grnt_), // ×ÜÏßÊÚȨ
// 1ºÅ×ÜÏßÖ÷¿Ø
.m1_req_ (m1_req_), // ¥Ð¥¹¥ê¥¯¥¨¥¹¥È
.m1_addr (m1_addr), // ¥¢¥É¥ì¥¹
.m1_as_ (m1_as_), // ¥¢¥É¥ì¥¹¥¹¥È¥í©`¥Ö
.m1_rw (m1_rw), // Õi¤ß£¯ø¤
.m1_wr_data (m1_wr_data), // ø¤Þz¤ß¥Ç©`¥¿
.m1_grnt_ (m1_grnt_), // ¥Ð¥¹¥°¥é¥ó¥È
// 2ºÅ×ÜÏßÖ÷¿Ø
.m2_req_ (m2_req_), // ¥Ð¥¹¥ê¥¯¥¨¥¹¥È
.m2_addr (m2_addr), // ¥¢¥É¥ì¥¹
.m2_as_ (m2_as_), // ¥¢¥É¥ì¥¹¥¹¥È¥í©`¥Ö
.m2_rw (m2_rw), // Õi¤ß£¯ø¤
.m2_wr_data (m2_wr_data), // ø¤Þz¤ß¥Ç©`¥¿
.m2_grnt_ (m2_grnt_), // ¥Ð¥¹¥°¥é¥ó¥È
// 3ºÅ×ÜÏßÖ÷¿Ø
.m3_req_ (m3_req_), // ¥Ð¥¹¥ê¥¯¥¨¥¹¥È
.m3_addr (m3_addr), // ¥¢¥É¥ì¥¹
.m3_as_ (m3_as_), // ¥¢¥É¥ì¥¹¥¹¥È¥í©`¥Ö
.m3_rw (m3_rw), // Õi¤ß£¯ø¤
.m3_wr_data (m3_wr_data), // ø¤Þz¤ß¥Ç©`¥¿
.m3_grnt_ (m3_grnt_), // ¥Ð¥¹¥°¥é¥ó¥È
/********** ×ÜÏß´ÓÉ豸ÐźŠ**********/
// ËùÓÐ×ÜÏß´ÓÊôÉ豸¹²ÓÃÐźÅ
.s_addr (s_addr), // µØÖ·
.s_as_ (s_as_), // µØַѡͨ
.s_rw (s_rw), // ¶Á/д
.s_wr_data (s_wr_data), // дÈëµÄÊý¾Ý
// 0ºÅ×ÜÏß´ÓÊô
.s0_rd_data (s0_rd_data), // ¶Á³öµÄÊý¾Ý
.s0_rdy_ (s0_rdy_), // ¾ÍÐ÷
.s0_cs_ (s0_cs_), // Ƭѡ
// 1ºÅ×ÜÏß´ÓÊô
.s1_rd_data (s1_rd_data), // Õi¤ß³ö¤·¥Ç©`¥¿
.s1_rdy_ (s1_rdy_), // ¥ì¥Ç¥£
.s1_cs_ (s1_cs_), // ¥Á¥Ã¥×¥»¥ì¥¯¥È
// 2ºÅ×ÜÏß´ÓÊô
.s2_rd_data (s2_rd_data), // Õi¤ß³ö¤·¥Ç©`¥¿
.s2_rdy_ (s2_rdy_), // ¥ì¥Ç¥£
.s2_cs_ (s2_cs_), // ¥Á¥Ã¥×¥»¥ì¥¯¥È
// 3ºÅ×ÜÏß´ÓÊô
.s3_rd_data (s3_rd_data), // Õi¤ß³ö¤·¥Ç©`¥¿
.s3_rdy_ (s3_rdy_), // ¥ì¥Ç¥£
.s3_cs_ (s3_cs_), // ¥Á¥Ã¥×¥»¥ì¥¯¥È
// 4ºÅ×ÜÏß´ÓÊô
.s4_rd_data (s4_rd_data), // Õi¤ß³ö¤·¥Ç©`¥¿
.s4_rdy_ (s4_rdy_), // ¥ì¥Ç¥£
.s4_cs_ (s4_cs_), // ¥Á¥Ã¥×¥»¥ì¥¯¥È
// 5ºÅ×ÜÏß´ÓÊô
.s5_rd_data (s5_rd_data), // Õi¤ß³ö¤·¥Ç©`¥¿
.s5_rdy_ (s5_rdy_), // ¥ì¥Ç¥£
.s5_cs_ (s5_cs_), // ¥Á¥Ã¥×¥»¥ì¥¯¥È
// 6ºÅ×ÜÏß´ÓÊô
.s6_rd_data (s6_rd_data), // Õi¤ß³ö¤·¥Ç©`¥¿
.s6_rdy_ (s6_rdy_), // ¥ì¥Ç¥£
.s6_cs_ (s6_cs_), // ¥Á¥Ã¥×¥»¥ì¥¯¥È
// 7ºÅ×ÜÏß´ÓÊô
.s7_rd_data (s7_rd_data), // Õi¤ß³ö¤·¥Ç©`¥¿
.s7_rdy_ (s7_rdy_), // ¥ì¥Ç¥£
.s7_cs_ (s7_cs_) // ¥Á¥Ã¥×¥»¥ì¥¯¥È
);
endmodule |
module chip_top (
/********** ʱÖÓÓ븴λ **********/
input wire clk_ref, // »ù±¾Ê±ÖÓ
input wire reset_sw // È«¾Ö¸´Î»£¬È±Ê¡¶¨ÒåΪ¸ºÂß¼,¼ûglobal_config.h
/********** UART **********/
`ifdef IMPLEMENT_UART // UARTʵÏÖ
, input wire uart_rx // UART½ÓÊÕÐźÅ
, output wire uart_tx // UART·¢ËÍÐźÅ
`endif
/********** ͨÓÃI/ O¶Ë¿Ú **********/
`ifdef IMPLEMENT_GPIO // GPIOʵÏÖ
`ifdef GPIO_IN_CH //ÊäÈë½Ó¿ÚʵÏÖ
, input wire [`GPIO_IN_CH-1:0] gpio_in // ÊäÈë½Ó¿Ú
`endif
`ifdef GPIO_OUT_CH // Êä³ö½Ó¿ÚʵÏÖ
, output wire [`GPIO_OUT_CH-1:0] gpio_out // Êä³ö½Ó¿Ú
`endif
`ifdef GPIO_IO_CH // ÊäÈëÊä³ö½Ó¿ÚʵÏÖ
, inout wire [`GPIO_IO_CH-1:0] gpio_io // ÊäÈëÊä³ö½Ó¿Ú
`endif
`endif
);
/********** ʱÖÓÓ븴λ **********/
wire clk; // ʱÖÓ
wire clk_; // ·´ÏàʱÖÓ
wire chip_reset; // ¸´Î»
/********** ʱÖÓÄ£¿é **********/
clk_gen clk_gen (
/********** ʱÖÓÓ븴λ **********/
.clk_ref (clk_ref), // »ù±¾Ê±ÖÓ
.reset_sw (reset_sw), // È«¾Ö¸´Î»
/********** Éú³ÉʱÖÓ **********/
.clk (clk), // ʱÖÓ
.clk_ (clk_), // ·´ÏòʱÖÓ
/********** ¸´Î» **********/
.chip_reset (chip_reset) // ¸´Î»
);
/********** оƬ **********/
chip chip (
/********** ʱÖÓÓ븴λ **********/
.clk (clk), // ʱÖÓ
.clk_ (clk_), // ·´ÏòʱÖÓ
.reset (chip_reset) // ¸´Î»
/********** UART **********/
`ifdef IMPLEMENT_UART
, .uart_rx (uart_rx) // UART½ÓÊÕÐźÅ
, .uart_tx (uart_tx) // UART·¢ËÍÐźÅ
`endif
/********** GPIO **********/
`ifdef IMPLEMENT_GPIO
`ifdef GPIO_IN_CH // ÊäÈë½Ó¿ÚʵÏÖ
, .gpio_in (gpio_in) // ÊäÈë½Ó¿Ú
`endif
`ifdef GPIO_OUT_CH // Êä³ö½Ó¿ÚʵÏÖ
, .gpio_out (gpio_out) // Êä³ö½Ó¿Ú
`endif
`ifdef GPIO_IO_CH // ÊäÈëÊä³ö½Ó¿ÚʵÏÖ
, .gpio_io (gpio_io) // ÊäÈëÊä³ö½Ó¿Ú
`endif
`endif
);
endmodule |
module altera_sprom (
address,
clock,
q);
input [10:0] address;
input clock;
output [31:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
endmodule |
module x_s3e_sprom (
input wire clka, // NbN
input wire [`RomAddrBus] addra, // AhX
output reg [`WordDataBus] douta // ÇÝoµf[^
);
/********** **********/
reg [`WordDataBus] mem [0:`ROM_DEPTH-1];
/********** ÇÝoµANZX **********/
always @(posedge clka) begin
douta <= #1 mem[addra];
end
endmodule |
module x_s3e_dpram (
/********** |[g A **********/
input wire clka, // NbN
input wire [`SpmAddrBus] addra, // AhX
input wire [`WordDataBus] dina, // «Ýf[^
input wire wea, // «ÝLø
output reg [`WordDataBus] douta, // ÇÝoµf[^
/********** |[g B **********/
input wire clkb, // NbN
input wire [`SpmAddrBus] addrb, // AhX
input wire [`WordDataBus] dinb, // «Ýf[^
input wire web, // «ÝLø
output reg [`WordDataBus] doutb // ÇÝoµf[^
);
/********** **********/
reg [`WordDataBus] mem [0:`SPM_DEPTH-1];
/********** ANZXi|[g Aj **********/
always @(posedge clka) begin
// ÇÝoµANZX
if ((web == `ENABLE) && (addra == addrb)) begin
douta <= #1 dinb;
end else begin
douta <= #1 mem[addra];
end
// «ÝANZX
if (wea == `ENABLE) begin
mem[addra]<= #1 dina;
end
end
/********** ANZXi|[g Bj **********/
always @(posedge clkb) begin
// ÇÝoµANZX
if ((wea == `ENABLE) && (addrb == addra)) begin
doutb <= #1 dina;
end else begin
doutb <= #1 mem[addrb];
end
// «ÝANZX
if (web == `ENABLE) begin
mem[addrb]<= #1 dinb;
end
end
endmodule |
module altera_dpram (
address_a,
address_b,
clock_a,
clock_b,
data_a,
data_b,
wren_a,
wren_b,
q_a,
q_b);
input [11:0] address_a;
input [11:0] address_b;
input clock_a;
input clock_b;
input [31:0] data_a;
input [31:0] data_b;
input wren_a;
input wren_b;
output [31:0] q_a;
output [31:0] q_b;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock_a;
tri0 wren_a;
tri0 wren_b;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
endmodule |
module altera_dpram (
address_a,
address_b,
clock_a,
clock_b,
data_a,
data_b,
wren_a,
wren_b,
q_a,
q_b);
input [11:0] address_a;
input [11:0] address_b;
input clock_a;
input clock_b;
input [31:0] data_a;
input [31:0] data_b;
input wren_a;
input wren_b;
output [31:0] q_a;
output [31:0] q_b;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock_a;
tri0 wren_a;
tri0 wren_b;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [31:0] sub_wire0;
wire [31:0] sub_wire1;
wire [31:0] q_a = sub_wire0[31:0];
wire [31:0] q_b = sub_wire1[31:0];
altsyncram altsyncram_component (
.clock0 (clock_a),
.wren_a (wren_a),
.address_b (address_b),
.clock1 (clock_b),
.data_b (data_b),
.wren_b (wren_b),
.address_a (address_a),
.data_a (data_a),
.q_a (sub_wire0),
.q_b (sub_wire1),
.aclr0 (1'b0),
.aclr1 (1'b0),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.eccstatus (),
.rden_a (1'b1),
.rden_b (1'b1));
defparam
altsyncram_component.address_reg_b = "CLOCK1",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_input_b = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.clock_enable_output_b = "BYPASS",
altsyncram_component.indata_reg_b = "CLOCK1",
altsyncram_component.intended_device_family = "Cyclone IV E",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 4096,
altsyncram_component.numwords_b = 4096,
altsyncram_component.operation_mode = "BIDIR_DUAL_PORT",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_aclr_b = "NONE",
altsyncram_component.outdata_reg_a = "CLOCK0",
altsyncram_component.outdata_reg_b = "CLOCK1",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.read_during_write_mode_port_a = "NEW_DATA_NO_NBE_READ",
altsyncram_component.read_during_write_mode_port_b = "NEW_DATA_NO_NBE_READ",
altsyncram_component.widthad_a = 12,
altsyncram_component.widthad_b = 12,
altsyncram_component.width_a = 32,
altsyncram_component.width_b = 32,
altsyncram_component.width_byteena_a = 1,
altsyncram_component.width_byteena_b = 1,
altsyncram_component.wrcontrol_wraddress_reg_b = "CLOCK1";
endmodule |
module altera_dcm (
areset,
inclk0,
c0,
c1,
locked);
input areset;
input inclk0;
output c0;
output c1;
output locked;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 areset;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [4:0] sub_wire0;
wire sub_wire2;
wire [0:0] sub_wire6 = 1'h0;
wire [0:0] sub_wire3 = sub_wire0[0:0];
wire [1:1] sub_wire1 = sub_wire0[1:1];
wire c1 = sub_wire1;
wire locked = sub_wire2;
wire c0 = sub_wire3;
wire sub_wire4 = inclk0;
wire [1:0] sub_wire5 = {sub_wire6, sub_wire4};
altpll altpll_component (
.areset (areset),
.inclk (sub_wire5),
.clk (sub_wire0),
.locked (sub_wire2),
.activeclock (),
.clkbad (),
.clkena ({6{1'b1}}),
.clkloss (),
.clkswitch (1'b0),
.configupdate (1'b0),
.enable0 (),
.enable1 (),
.extclk (),
.extclkena ({4{1'b1}}),
.fbin (1'b1),
.fbmimicbidir (),
.fbout (),
.fref (),
.icdrclk (),
.pfdena (1'b1),
.phasecounterselect ({4{1'b1}}),
.phasedone (),
.phasestep (1'b1),
.phaseupdown (1'b1),
.pllena (1'b1),
.scanaclr (1'b0),
.scanclk (1'b0),
.scanclkena (1'b1),
.scandata (1'b0),
.scandataout (),
.scandone (),
.scanread (1'b0),
.scanwrite (1'b0),
.sclkout0 (),
.sclkout1 (),
.vcooverrange (),
.vcounderrange ());
defparam
altpll_component.bandwidth_type = "AUTO",
altpll_component.clk0_divide_by = 5,
altpll_component.clk0_duty_cycle = 50,
altpll_component.clk0_multiply_by = 1,
altpll_component.clk0_phase_shift = "0",
altpll_component.clk1_divide_by = 5,
altpll_component.clk1_duty_cycle = 50,
altpll_component.clk1_multiply_by = 1,
altpll_component.clk1_phase_shift = "50000",
altpll_component.compensate_clock = "CLK0",
altpll_component.inclk0_input_frequency = 20000,
altpll_component.intended_device_family = "Cyclone IV E",
altpll_component.lpm_hint = "CBX_MODULE_PREFIX=altera_dcm",
altpll_component.lpm_type = "altpll",
altpll_component.operation_mode = "NORMAL",
altpll_component.pll_type = "AUTO",
altpll_component.port_activeclock = "PORT_UNUSED",
altpll_component.port_areset = "PORT_USED",
altpll_component.port_clkbad0 = "PORT_UNUSED",
altpll_component.port_clkbad1 = "PORT_UNUSED",
altpll_component.port_clkloss = "PORT_UNUSED",
altpll_component.port_clkswitch = "PORT_UNUSED",
altpll_component.port_configupdate = "PORT_UNUSED",
altpll_component.port_fbin = "PORT_UNUSED",
altpll_component.port_inclk0 = "PORT_USED",
altpll_component.port_inclk1 = "PORT_UNUSED",
altpll_component.port_locked = "PORT_USED",
altpll_component.port_pfdena = "PORT_UNUSED",
altpll_component.port_phasecounterselect = "PORT_UNUSED",
altpll_component.port_phasedone = "PORT_UNUSED",
altpll_component.port_phasestep = "PORT_UNUSED",
altpll_component.port_phaseupdown = "PORT_UNUSED",
altpll_component.port_pllena = "PORT_UNUSED",
altpll_component.port_scanaclr = "PORT_UNUSED",
altpll_component.port_scanclk = "PORT_UNUSED",
altpll_component.port_scanclkena = "PORT_UNUSED",
altpll_component.port_scandata = "PORT_UNUSED",
altpll_component.port_scandataout = "PORT_UNUSED",
altpll_component.port_scandone = "PORT_UNUSED",
altpll_component.port_scanread = "PORT_UNUSED",
altpll_component.port_scanwrite = "PORT_UNUSED",
altpll_component.port_clk0 = "PORT_USED",
altpll_component.port_clk1 = "PORT_USED",
altpll_component.port_clk2 = "PORT_UNUSED",
altpll_component.port_clk3 = "PORT_UNUSED",
altpll_component.port_clk4 = "PORT_UNUSED",
altpll_component.port_clk5 = "PORT_UNUSED",
altpll_component.port_clkena0 = "PORT_UNUSED",
altpll_component.port_clkena1 = "PORT_UNUSED",
altpll_component.port_clkena2 = "PORT_UNUSED",
altpll_component.port_clkena3 = "PORT_UNUSED",
altpll_component.port_clkena4 = "PORT_UNUSED",
altpll_component.port_clkena5 = "PORT_UNUSED",
altpll_component.port_extclk0 = "PORT_UNUSED",
altpll_component.port_extclk1 = "PORT_UNUSED",
altpll_component.port_extclk2 = "PORT_UNUSED",
altpll_component.port_extclk3 = "PORT_UNUSED",
altpll_component.self_reset_on_loss_lock = "OFF",
altpll_component.width_clock = 5;
endmodule |
module x_s3e_dcm (
input wire CLKIN_IN, // ùèNbN
input wire RST_IN, // Zbg
output wire CLK0_OUT, // NbNiÓ0j
output wire CLK180_OUT, // NbNiÓ180j
output wire LOCKED_OUT // bN
);
/********** NbNoÍ **********/
assign CLK0_OUT = CLKIN_IN;
assign CLK180_OUT = ~CLKIN_IN;
assign LOCKED_OUT = ~RST_IN;
endmodule |
module altera_dcm (
areset,
inclk0,
c0,
c1,
locked);
input areset;
input inclk0;
output c0;
output c1;
output locked;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 areset;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
endmodule |
module altera_sprom (
address,
clock,
q);
input [10:0] address;
input clock;
output [31:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [31:0] sub_wire0;
wire [31:0] q = sub_wire0[31:0];
altsyncram altsyncram_component (
.address_a (address),
.clock0 (clock),
.q_a (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.address_b (1'b1),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_a ({32{1'b1}}),
.data_b (1'b1),
.eccstatus (),
.q_b (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_a (1'b0),
.wren_b (1'b0));
defparam
altsyncram_component.address_aclr_a = "NONE",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.init_file = "../azpr_asm/loader16.mif",
altsyncram_component.intended_device_family = "Cyclone IV E",
altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 2048,
altsyncram_component.operation_mode = "ROM",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_reg_a = "CLOCK0",
altsyncram_component.widthad_a = 11,
altsyncram_component.width_a = 32,
altsyncram_component.width_byteena_a = 1;
endmodule |
module spm (
/********** ÊäÈëÊä³ö²ÎÊý **********/
input wire clk, // ʱÖÓ
/********** ¶Ë¿ÚA : IF½×¶Î **********/
input wire [`SpmAddrBus] if_spm_addr, // ?????
input wire if_spm_as_, // ??????????`??
input wire if_spm_rw, // ?i???????
input wire [`WordDataBus] if_spm_wr_data, // ?????z???`??
output wire [`WordDataBus] if_spm_rd_data, // ?i???????`??
/********** ¶Ë¿ÚB : MEM½×¶Î **********/
input wire [`SpmAddrBus] mem_spm_addr, // ?????
input wire mem_spm_as_, // ??????????`??
input wire mem_spm_rw, // ?i???????
input wire [`WordDataBus] mem_spm_wr_data, // ?????z???`??
output wire [`WordDataBus] mem_spm_rd_data // ?i???????`??
);
/********** ?????z???????? **********/
reg wea; // ??`?? A
reg web; // ??`?? B
/********** ?????z????????????? **********/
always @(*) begin
/* ¶Ë¿ÚA */
if ((if_spm_as_ == `ENABLE_) && (if_spm_rw == `WRITE)) begin
wea = `MEM_ENABLE; // ?????z?????
end else begin
wea = `MEM_DISABLE; // ?????z??o??
end
/* ¶Ë¿ÚB */
if ((mem_spm_as_ == `ENABLE_) && (mem_spm_rw == `WRITE)) begin
web = `MEM_ENABLE; // ?????z?????
end else begin
web = `MEM_DISABLE; // ?????z??o??
end
end
/********** Xilinx FPGA Block RAM :->altera_dpram **********/
altera_dpram x_s3e_dpram (
/********** ¶Ë¿ÚA : IF????`?? **********/
.clock_a (clk), // ????a?
.address_a (if_spm_addr), // ?????
.data_a (if_spm_wr_data), // ?????z???`????????A??
.wren_a (wea), // ?????z???????????`???
.q_a (if_spm_rd_data), // ?i???????`??
/********** ¶Ë¿ÚB : MEM????`?? **********/
.clock_b (clk), // ????a?
.address_b (mem_spm_addr), // ?????
.data_b (mem_spm_wr_data), // ?????z???`??
.wren_b (web), // ?????z?????
.q_b (mem_spm_rd_data) // ?i???????`??
);
endmodule |
module cpu (
/********** ¥¯¥í¥Ã¥¯ & ¥ê¥»¥Ã¥È **********/
input wire clk, // ¥¯¥í¥Ã¥¯
input wire clk_, // ·´Ü¥¯¥í¥Ã¥¯
input wire reset, // ·ÇͬÆڥꥻ¥Ã¥È
/********** ¥Ð¥¹¥¤¥ó¥¿¥Õ¥§©`¥¹ **********/
// IF Stage
input wire [`WordDataBus] if_bus_rd_data, // Õi¤ß³ö¤·¥Ç©`¥¿
input wire if_bus_rdy_, // ¥ì¥Ç¥£
input wire if_bus_grnt_, // ¥Ð¥¹¥°¥é¥ó¥È
output wire if_bus_req_, // ¥Ð¥¹¥ê¥¯¥¨¥¹¥È
output wire [`WordAddrBus] if_bus_addr, // ¥¢¥É¥ì¥¹
output wire if_bus_as_, // ¥¢¥É¥ì¥¹¥¹¥È¥í©`¥Ö
output wire if_bus_rw, // Õi¤ß£¯ø¤
output wire [`WordDataBus] if_bus_wr_data, // ø¤Þz¤ß¥Ç©`¥¿
// MEM Stage
input wire [`WordDataBus] mem_bus_rd_data, // Õi¤ß³ö¤·¥Ç©`¥¿
input wire mem_bus_rdy_, // ¥ì¥Ç¥£
input wire mem_bus_grnt_, // ¥Ð¥¹¥°¥é¥ó¥È
output wire mem_bus_req_, // ¥Ð¥¹¥ê¥¯¥¨¥¹¥È
output wire [`WordAddrBus] mem_bus_addr, // ¥¢¥É¥ì¥¹
output wire mem_bus_as_, // ¥¢¥É¥ì¥¹¥¹¥È¥í©`¥Ö
output wire mem_bus_rw, // Õi¤ß£¯ø¤
output wire [`WordDataBus] mem_bus_wr_data, // ø¤Þz¤ß¥Ç©`¥¿
/********** ¸î¤êÞz¤ß **********/
input wire [`CPU_IRQ_CH-1:0] cpu_irq // ¸î¤êÞz¤ßÒªÇó
);
/********** ¥Ñ¥¤¥×¥é¥¤¥ó¥ì¥¸¥¹¥¿ **********/
// IF/ID
wire [`WordAddrBus] if_pc; // ¥×¥í¥°¥é¥à¥«¥¦¥ó¥¿
wire [`WordDataBus] if_insn; // ÃüÁî
wire if_en; // ¥Ñ¥¤¥×¥é¥¤¥ó¥Ç©`¥¿¤ÎÓп
// ID/EX¥Ñ¥¤¥×¥é¥¤¥ó¥ì¥¸¥¹¥¿
wire [`WordAddrBus] id_pc; // ¥×¥í¥°¥é¥à¥«¥¦¥ó¥¿
wire id_en; // ¥Ñ¥¤¥×¥é¥¤¥ó¥Ç©`¥¿¤ÎÓп
wire [`AluOpBus] id_alu_op; // ALU¥ª¥Ú¥ì©`¥·¥ç¥ó
wire [`WordDataBus] id_alu_in_0; // ALUÈëÁ¦ 0
wire [`WordDataBus] id_alu_in_1; // ALUÈëÁ¦ 1
wire id_br_flag; // ·Ö᪥ե饰
wire [`MemOpBus] id_mem_op; // ¥á¥â¥ê¥ª¥Ú¥ì©`¥·¥ç¥ó
wire [`WordDataBus] id_mem_wr_data; // ¥á¥â¥êø¤Þz¤ß¥Ç©`¥¿
wire [`CtrlOpBus] id_ctrl_op; // ÖÆÓù¥ª¥Ú¥ì©`¥·¥ç¥ó
wire [`RegAddrBus] id_dst_addr; // GPRø¤Þz¤ß¥¢¥É¥ì¥¹
wire id_gpr_we_; // GPRø¤Þz¤ßÓп
wire [`IsaExpBus] id_exp_code; // ÀýÍ⥳©`¥É
// EX/MEM¥Ñ¥¤¥×¥é¥¤¥ó¥ì¥¸¥¹¥¿
wire [`WordAddrBus] ex_pc; // ¥×¥í¥°¥é¥à¥«¥¦¥ó¥¿
wire ex_en; // ¥Ñ¥¤¥×¥é¥¤¥ó¥Ç©`¥¿¤ÎÓп
wire ex_br_flag; // ·Ö᪥ե饰
wire [`MemOpBus] ex_mem_op; // ¥á¥â¥ê¥ª¥Ú¥ì©`¥·¥ç¥ó
wire [`WordDataBus] ex_mem_wr_data; // ¥á¥â¥êø¤Þz¤ß¥Ç©`¥¿
wire [`CtrlOpBus] ex_ctrl_op; // ÖÆÓù¥ì¥¸¥¹¥¿¥ª¥Ú¥ì©`¥·¥ç¥ó
wire [`RegAddrBus] ex_dst_addr; // øÓå쥸¥¹¥¿ø¤Þz¤ß¥¢¥É¥ì¥¹
wire ex_gpr_we_; // øÓå쥸¥¹¥¿ø¤Þz¤ßÓп
wire [`IsaExpBus] ex_exp_code; // ÀýÍ⥳©`¥É
wire [`WordDataBus] ex_out; // IÀí½Y¹û
// MEM/WB¥Ñ¥¤¥×¥é¥¤¥ó¥ì¥¸¥¹¥¿
wire [`WordAddrBus] mem_pc; // ¥×¥í¥°¥é¥ó¥«¥¦¥ó¥¿
wire mem_en; // ¥Ñ¥¤¥×¥é¥¤¥ó¥Ç©`¥¿¤ÎÓп
wire mem_br_flag; // ·Ö᪥ե饰
wire [`CtrlOpBus] mem_ctrl_op; // ÖÆÓù¥ì¥¸¥¹¥¿¥ª¥Ú¥ì©`¥·¥ç¥ó
wire [`RegAddrBus] mem_dst_addr; // øÓå쥸¥¹¥¿ø¤Þz¤ß¥¢¥É¥ì¥¹
wire mem_gpr_we_; // øÓå쥸¥¹¥¿ø¤Þz¤ßÓп
wire [`IsaExpBus] mem_exp_code; // ÀýÍ⥳©`¥É
wire [`WordDataBus] mem_out; // IÀí½Y¹û
/********** ¥Ñ¥¤¥×¥é¥¤¥óÖÆÓùÐźŠ**********/
// ¥¹¥È©`¥ëÐźÅ
wire if_stall; // IF¥¹¥Æ©`¥¸
wire id_stall; // ID¥¹¥Æ©`
wire ex_stall; // EX¥¹¥Æ©`¥¸
wire mem_stall; // MEM¥¹¥Æ©`¥¸
// ¥Õ¥é¥Ã¥·¥åÐźÅ
wire if_flush; // IF¥¹¥Æ©`¥¸
wire id_flush; // ID¥¹¥Æ©`¥¸
wire ex_flush; // EX¥¹¥Æ©`¥¸
wire mem_flush; // MEM¥¹¥Æ©`¥¸
// ¥Ó¥¸©`ÐźÅ
wire if_busy; // IF¥¹¥Æ©`¥¸
wire mem_busy; // MEM¥¹¥Æ©`¥¸
// ¤½¤ÎËû¤ÎÖÆÓùÐźÅ
wire [`WordAddrBus] new_pc; // Ф·¤¤PC
wire [`WordAddrBus] br_addr; // ·Ö᪥¢¥É¥ì¥¹
wire br_taken; // ·Ö᪤γÉÁ¢
wire ld_hazard; // ¥í©`¥É¥Ï¥¶©`¥É
/********** øÓå쥸¥¹¥¿ÐźŠ**********/
wire [`WordDataBus] gpr_rd_data_0; // Õi¤ß³ö¤·¥Ç©`¥¿ 0
wire [`WordDataBus] gpr_rd_data_1; // Õi¤ß³ö¤·¥Ç©`¥¿ 1
wire [`RegAddrBus] gpr_rd_addr_0; // Õi¤ß³ö¤·¥¢¥É¥ì¥¹ 0
wire [`RegAddrBus] gpr_rd_addr_1; // Õi¤ß³ö¤·¥¢¥É¥ì¥¹ 1
/********** ÖÆÓù¥ì¥¸¥¹¥¿ÐźŠ**********/
wire [`CpuExeModeBus] exe_mode; // gÐÐ¥â©`¥É
wire [`WordDataBus] creg_rd_data; // Õi¤ß³ö¤·¥Ç©`¥¿
wire [`RegAddrBus] creg_rd_addr; // Õi¤ß³ö¤·¥¢¥É¥ì¥¹
/********** Interrupt Request **********/
wire int_detect; // ¸î¤êÞz¤ßʳö
/********** ¥¹¥¯¥é¥Ã¥Á¥Ñ¥Ã¥É¥á¥â¥êÐźŠ**********/
// IF¥¹¥Æ©`¥¸
wire [`WordDataBus] if_spm_rd_data; // Õi¤ß³ö¤·¥Ç©`¥¿
wire [`WordAddrBus] if_spm_addr; // ¥¢¥É¥ì¥¹
wire if_spm_as_; // ¥¢¥É¥ì¥¹¥¹¥È¥í©`¥Ö
wire if_spm_rw; // Õi¤ß£¯ø¤
wire [`WordDataBus] if_spm_wr_data; // ø¤Þz¤ß¥Ç©`¥¿
// MEM¥¹¥Æ©`¥¸
wire [`WordDataBus] mem_spm_rd_data; // Õi¤ß³ö¤·¥Ç©`¥¿
wire [`WordAddrBus] mem_spm_addr; // ¥¢¥É¥ì¥¹
wire mem_spm_as_; // ¥¢¥É¥ì¥¹¥¹¥È¥í©`¥Ö
wire mem_spm_rw; // Õi¤ß£¯ø¤
wire [`WordDataBus] mem_spm_wr_data; // ø¤Þz¤ß¥Ç©`¥¿
/********** ¥Õ¥©¥ï©`¥Ç¥£¥ó¥°ÐźŠ**********/
wire [`WordDataBus] ex_fwd_data; // EX¥¹¥Æ©`¥¸
wire [`WordDataBus] mem_fwd_data; // MEM¥¹¥Æ©`¥¸
/********** IF¥¹¥Æ©`¥¸ **********/
if_stage if_stage (
/********** ¥¯¥í¥Ã¥¯ & ¥ê¥»¥Ã¥È **********/
.clk (clk), // ¥¯¥í¥Ã¥¯
.reset (reset), // ·ÇͬÆڥꥻ¥Ã¥È
/********** SPM¥¤¥ó¥¿¥Õ¥§©`¥¹ **********/
.spm_rd_data (if_spm_rd_data), // Õi¤ß³ö¤·¥Ç©`¥¿
.spm_addr (if_spm_addr), // ¥¢¥É¥ì¥¹
.spm_as_ (if_spm_as_), // ¥¢¥É¥ì¥¹¥¹¥È¥í©`¥Ö
.spm_rw (if_spm_rw), // Õi¤ß£¯ø¤
.spm_wr_data (if_spm_wr_data), // ø¤Þz¤ß¥Ç©`¥¿
/********** ¥Ð¥¹¥¤¥ó¥¿¥Õ¥§©`¥¹ **********/
.bus_rd_data (if_bus_rd_data), // Õi¤ß³ö¤·¥Ç©`¥¿
.bus_rdy_ (if_bus_rdy_), // ¥ì¥Ç¥£
.bus_grnt_ (if_bus_grnt_), // ¥Ð¥¹¥°¥é¥ó¥È
.bus_req_ (if_bus_req_), // ¥Ð¥¹¥ê¥¯¥¨¥¹¥È
.bus_addr (if_bus_addr), // ¥¢¥É¥ì¥¹
.bus_as_ (if_bus_as_), // ¥¢¥É¥ì¥¹¥¹¥È¥í©`¥Ö
.bus_rw (if_bus_rw), // Õi¤ß£¯ø¤
.bus_wr_data (if_bus_wr_data), // ø¤Þz¤ß¥Ç©`¥¿
/********** ¥Ñ¥¤¥×¥é¥¤¥óÖÆÓùÐźŠ**********/
.stall (if_stall), // ¥¹¥È©`¥ë
.flush (if_flush), // ¥Õ¥é¥Ã¥·¥å
.new_pc (new_pc), // Ф·¤¤PC
.br_taken (br_taken), // ·Ö᪤γÉÁ¢
.br_addr (br_addr), // ·ÖáªÏÈ¥¢¥É¥ì¥¹
.busy (if_busy), // ¥Ó¥¸©`ÐźÅ
/********** IF/ID¥Ñ¥¤¥×¥é¥¤¥ó¥ì¥¸¥¹¥¿ **********/
.if_pc (if_pc), // ¥×¥í¥°¥é¥à¥«¥¦¥ó¥¿
.if_insn (if_insn), // ÃüÁî
.if_en (if_en) // ¥Ñ¥¤¥×¥é¥¤¥ó¥Ç©`¥¿¤ÎÓп
);
/********** ID¥¹¥Æ©`¥¸ **********/
id_stage id_stage (
/********** ¥¯¥í¥Ã¥¯ & ¥ê¥»¥Ã¥È **********/
.clk (clk), // ¥¯¥í¥Ã¥¯
.reset (reset), // ·ÇͬÆڥꥻ¥Ã¥È
/********** GPR¥¤¥ó¥¿¥Õ¥§©`¥¹ **********/
.gpr_rd_data_0 (gpr_rd_data_0), // Õi¤ß³ö¤·¥Ç©`¥¿ 0
.gpr_rd_data_1 (gpr_rd_data_1), // Õi¤ß³ö¤·¥Ç©`¥¿ 1
.gpr_rd_addr_0 (gpr_rd_addr_0), // Õi¤ß³ö¤·¥¢¥É¥ì¥¹ 0
.gpr_rd_addr_1 (gpr_rd_addr_1), // Õi¤ß³ö¤·¥¢¥É¥ì¥¹ 1
/********** ¥Õ¥©¥ï©`¥Ç¥£¥ó¥° **********/
// EX¥¹¥Æ©`¥¸¤«¤é¤Î¥Õ¥©¥ï©`¥Ç¥£¥ó¥°
.ex_en (ex_en), // ¥Ñ¥¤¥×¥é¥¤¥ó¥Ç©`¥¿¤ÎÓп
.ex_fwd_data (ex_fwd_data), // ¥Õ¥©¥ï©`¥Ç¥£¥ó¥°¥Ç©`¥¿
.ex_dst_addr (ex_dst_addr), // ø¤Þz¤ß¥¢¥É¥ì¥¹
.ex_gpr_we_ (ex_gpr_we_), // ø¤Þz¤ßÓп
// MEM¥¹¥Æ©`¥¸¤«¤é¤Î¥Õ¥©¥ï©`¥Ç¥£¥ó¥°
.mem_fwd_data (mem_fwd_data), // ¥Õ¥©¥ï©`¥Ç¥£¥ó¥°¥Ç©`¥¿
/********** ÖÆÓù¥ì¥¸¥¹¥¿¥¤¥ó¥¿¥Õ¥§©`¥¹ **********/
.exe_mode (exe_mode), // gÐÐ¥â©`¥É
.creg_rd_data (creg_rd_data), // Õi¤ß³ö¤·¥Ç©`¥¿
.creg_rd_addr (creg_rd_addr), // Õi¤ß³ö¤·¥¢¥É¥ì¥¹
/********** ¥Ñ¥¤¥×¥é¥¤¥óÖÆÓùÐźŠ**********/
.stall (id_stall), // ¥¹¥È©`¥ë
.flush (id_flush), // ¥Õ¥é¥Ã¥·¥å
.br_addr (br_addr), // ·Ö᪥¢¥É¥ì¥¹
.br_taken (br_taken), // ·Ö᪤γÉÁ¢
.ld_hazard (ld_hazard), // ¥í©`¥É¥Ï¥¶©`¥É
/********** IF/ID¥Ñ¥¤¥×¥é¥¤¥ó¥ì¥¸¥¹¥¿ **********/
.if_pc (if_pc), // ¥×¥í¥°¥é¥à¥«¥¦¥ó¥¿
.if_insn (if_insn), // ÃüÁî
.if_en (if_en), // ¥Ñ¥¤¥×¥é¥¤¥ó¥Ç©`¥¿¤ÎÓп
/********** ID/EX¥Ñ¥¤¥×¥é¥¤¥ó¥ì¥¸¥¹¥¿ **********/
.id_pc (id_pc), // ¥×¥í¥°¥é¥à¥«¥¦¥ó¥¿
.id_en (id_en), // ¥Ñ¥¤¥×¥é¥¤¥ó¥Ç©`¥¿¤ÎÓп
.id_alu_op (id_alu_op), // ALU¥ª¥Ú¥ì©`¥·¥ç¥ó
.id_alu_in_0 (id_alu_in_0), // ALUÈëÁ¦ 0
.id_alu_in_1 (id_alu_in_1), // ALUÈëÁ¦ 1
.id_br_flag (id_br_flag), // ·Ö᪥ե饰
.id_mem_op (id_mem_op), // ¥á¥â¥ê¥ª¥Ú¥ì©`¥·¥ç¥ó
.id_mem_wr_data (id_mem_wr_data), // ¥á¥â¥êø¤Þz¤ß¥Ç©`¥¿
.id_ctrl_op (id_ctrl_op), // ÖÆÓù¥ª¥Ú¥ì©`¥·¥ç¥ó
.id_dst_addr (id_dst_addr), // GPRø¤Þz¤ß¥¢¥É¥ì¥¹
.id_gpr_we_ (id_gpr_we_), // GPRø¤Þz¤ßÓп
.id_exp_code (id_exp_code) // ÀýÍ⥳©`¥É
);
/********** EX¥¹¥Æ©`¥¸ **********/
ex_stage ex_stage (
/********** ¥¯¥í¥Ã¥¯ & ¥ê¥»¥Ã¥È **********/
.clk (clk), // ¥¯¥í¥Ã¥¯
.reset (reset), // ·ÇͬÆڥꥻ¥Ã¥È
/********** ¥Ñ¥¤¥×¥é¥¤¥óÖÆÓùÐźŠ**********/
.stall (ex_stall), // ¥¹¥È©`¥ë
.flush (ex_flush), // ¥Õ¥é¥Ã¥·¥å
.int_detect (int_detect), // ¸î¤êÞz¤ßʳö
/********** ¥Õ¥©¥ï©`¥Ç¥£¥ó¥° **********/
.fwd_data (ex_fwd_data), // ¥Õ¥©¥ï©`¥Ç¥£¥ó¥°¥Ç©`¥¿
/********** ID/EX¥Ñ¥¤¥×¥é¥¤¥ó¥ì¥¸¥¹¥¿ **********/
.id_pc (id_pc), // ¥×¥í¥°¥é¥à¥«¥¦¥ó¥¿
.id_en (id_en), // ¥Ñ¥¤¥×¥é¥¤¥ó¥Ç©`¥¿¤ÎÓп
.id_alu_op (id_alu_op), // ALU¥ª¥Ú¥ì©`¥·¥ç¥ó
.id_alu_in_0 (id_alu_in_0), // ALUÈëÁ¦ 0
.id_alu_in_1 (id_alu_in_1), // ALUÈëÁ¦ 1
.id_br_flag (id_br_flag), // ·Ö᪥ե饰
.id_mem_op (id_mem_op), // ¥á¥â¥ê¥ª¥Ú¥ì©`¥·¥ç¥ó
.id_mem_wr_data (id_mem_wr_data), // ¥á¥â¥êø¤Þz¤ß¥Ç©`¥¿
.id_ctrl_op (id_ctrl_op), // ÖÆÓù¥ì¥¸¥¹¥¿¥ª¥Ú¥ì©`¥·¥ç¥ó
.id_dst_addr (id_dst_addr), // øÓå쥸¥¹¥¿ø¤Þz¤ß¥¢¥É¥ì¥¹
.id_gpr_we_ (id_gpr_we_), // øÓå쥸¥¹¥¿ø¤Þz¤ßÓп
.id_exp_code (id_exp_code), // ÀýÍ⥳©`¥É
/********** EX/MEM¥Ñ¥¤¥×¥é¥¤¥ó¥ì¥¸¥¹¥¿ **********/
.ex_pc (ex_pc), // ¥×¥í¥°¥é¥à¥«¥¦¥ó¥¿
.ex_en (ex_en), // ¥Ñ¥¤¥×¥é¥¤¥ó¥Ç©`¥¿¤ÎÓп
.ex_br_flag (ex_br_flag), // ·Ö᪥ե饰
.ex_mem_op (ex_mem_op), // ¥á¥â¥ê¥ª¥Ú¥ì©`¥·¥ç¥ó
.ex_mem_wr_data (ex_mem_wr_data), // ¥á¥â¥êø¤Þz¤ß¥Ç©`¥¿
.ex_ctrl_op (ex_ctrl_op), // ÖÆÓù¥ì¥¸¥¹¥¿¥ª¥Ú¥ì©`¥·¥ç¥ó
.ex_dst_addr (ex_dst_addr), // øÓå쥸¥¹¥¿ø¤Þz¤ß¥¢¥É¥ì¥¹
.ex_gpr_we_ (ex_gpr_we_), // øÓå쥸¥¹¥¿ø¤Þz¤ßÓп
.ex_exp_code (ex_exp_code), // ÀýÍ⥳©`¥É
.ex_out (ex_out) // IÀí½Y¹û
);
/********** MEM¥¹¥Æ©`¥¸ **********/
mem_stage mem_stage (
/********** ¥¯¥í¥Ã¥¯ & ¥ê¥»¥Ã¥È **********/
.clk (clk), // ¥¯¥í¥Ã¥¯
.reset (reset), // ·ÇͬÆڥꥻ¥Ã¥È
/********** ¥Ñ¥¤¥×¥é¥¤¥óÖÆÓùÐźŠ**********/
.stall (mem_stall), // ¥¹¥È©`¥ë
.flush (mem_flush), // ¥Õ¥é¥Ã¥·¥å
.busy (mem_busy), // ¥Ó¥¸©`ÐźÅ
/********** ¥Õ¥©¥ï©`¥Ç¥£¥ó¥° **********/
.fwd_data (mem_fwd_data), // ¥Õ¥©¥ï©`¥Ç¥£¥ó¥°¥Ç©`¥¿
/********** SPM¥¤¥ó¥¿¥Õ¥§©`¥¹ **********/
.spm_rd_data (mem_spm_rd_data), // Õi¤ß³ö¤·¥Ç©`¥¿
.spm_addr (mem_spm_addr), // ¥¢¥É¥ì¥¹
.spm_as_ (mem_spm_as_), // ¥¢¥É¥ì¥¹¥¹¥È¥í©`¥Ö
.spm_rw (mem_spm_rw), // Õi¤ß£¯ø¤
.spm_wr_data (mem_spm_wr_data), // ø¤Þz¤ß¥Ç©`¥¿
/********** ¥Ð¥¹¥¤¥ó¥¿¥Õ¥§©`¥¹ **********/
.bus_rd_data (mem_bus_rd_data), // Õi¤ß³ö¤·¥Ç©`¥¿
.bus_rdy_ (mem_bus_rdy_), // ¥ì¥Ç¥£
.bus_grnt_ (mem_bus_grnt_), // ¥Ð¥¹¥°¥é¥ó¥È
.bus_req_ (mem_bus_req_), // ¥Ð¥¹¥ê¥¯¥¨¥¹¥È
.bus_addr (mem_bus_addr), // ¥¢¥É¥ì¥¹
.bus_as_ (mem_bus_as_), // ¥¢¥É¥ì¥¹¥¹¥È¥í©`¥Ö
.bus_rw (mem_bus_rw), // Õi¤ß£¯ø¤
.bus_wr_data (mem_bus_wr_data), // ø¤Þz¤ß¥Ç©`¥¿
/********** EX/MEM¥Ñ¥¤¥×¥é¥¤¥ó¥ì¥¸¥¹¥¿ **********/
.ex_pc (ex_pc), // ¥×¥í¥°¥é¥à¥«¥¦¥ó¥¿
.ex_en (ex_en), // ¥Ñ¥¤¥×¥é¥¤¥ó¥Ç©`¥¿¤ÎÓп
.ex_br_flag (ex_br_flag), // ·Ö᪥ե饰
.ex_mem_op (ex_mem_op), // ¥á¥â¥ê¥ª¥Ú¥ì©`¥·¥ç¥ó
.ex_mem_wr_data (ex_mem_wr_data), // ¥á¥â¥êø¤Þz¤ß¥Ç©`¥¿
.ex_ctrl_op (ex_ctrl_op), // ÖÆÓù¥ì¥¸¥¹¥¿¥ª¥Ú¥ì©`¥·¥ç¥ó
.ex_dst_addr (ex_dst_addr), // øÓå쥸¥¹¥¿ø¤Þz¤ß¥¢¥É¥ì¥¹
.ex_gpr_we_ (ex_gpr_we_), // øÓå쥸¥¹¥¿ø¤Þz¤ßÓп
.ex_exp_code (ex_exp_code), // ÀýÍ⥳©`¥É
.ex_out (ex_out), // IÀí½Y¹û
/********** MEM/WB¥Ñ¥¤¥×¥é¥¤¥ó¥ì¥¸¥¹¥¿ **********/
.mem_pc (mem_pc), // ¥×¥í¥°¥é¥ó¥«¥¦¥ó¥¿
.mem_en (mem_en), // ¥Ñ¥¤¥×¥é¥¤¥ó¥Ç©`¥¿¤ÎÓп
.mem_br_flag (mem_br_flag), // ·Ö᪥ե饰
.mem_ctrl_op (mem_ctrl_op), // ÖÆÓù¥ì¥¸¥¹¥¿¥ª¥Ú¥ì©`¥·¥ç¥ó
.mem_dst_addr (mem_dst_addr), // øÓå쥸¥¹¥¿ø¤Þz¤ß¥¢¥É¥ì¥¹
.mem_gpr_we_ (mem_gpr_we_), // øÓå쥸¥¹¥¿ø¤Þz¤ßÓп
.mem_exp_code (mem_exp_code), // ÀýÍ⥳©`¥É
.mem_out (mem_out) // IÀí½Y¹û
);
/********** ÖÆÓù¥æ¥Ë¥Ã¥È **********/
ctrl ctrl (
/********** ¥¯¥í¥Ã¥¯ & ¥ê¥»¥Ã¥È **********/
.clk (clk), // ¥¯¥í¥Ã¥¯
.reset (reset), // ·ÇͬÆڥꥻ¥Ã¥È
/********** ÖÆÓù¥ì¥¸¥¹¥¿¥¤¥ó¥¿¥Õ¥§©`¥¹ **********/
.creg_rd_addr (creg_rd_addr), // Õi¤ß³ö¤·¥¢¥É¥ì¥¹
.creg_rd_data (creg_rd_data), // Õi¤ß³ö¤·¥Ç©`¥¿
.exe_mode (exe_mode), // gÐÐ¥â©`¥É
/********** ¸î¤êÞz¤ß **********/
.irq (cpu_irq), // ¸î¤êÞz¤ßÒªÇó
.int_detect (int_detect), // ¸î¤êÞz¤ßʳö
/********** ID/EX¥Ñ¥¤¥×¥é¥¤¥ó¥ì¥¸¥¹¥¿ **********/
.id_pc (id_pc), // ¥×¥í¥°¥é¥à¥«¥¦¥ó¥¿
/********** MEM/WB¥Ñ¥¤¥×¥é¥¤¥ó¥ì¥¸¥¹¥¿ **********/
.mem_pc (mem_pc), // ¥×¥í¥°¥é¥ó¥«¥¦¥ó¥¿
.mem_en (mem_en), // ¥Ñ¥¤¥×¥é¥¤¥ó¥Ç©`¥¿¤ÎÓп
.mem_br_flag (mem_br_flag), // ·Ö᪥ե饰
.mem_ctrl_op (mem_ctrl_op), // ÖÆÓù¥ì¥¸¥¹¥¿¥ª¥Ú¥ì©`¥·¥ç¥ó
.mem_dst_addr (mem_dst_addr), // øÓå쥸¥¹¥¿ø¤Þz¤ß¥¢¥É¥ì¥¹
.mem_exp_code (mem_exp_code), // ÀýÍ⥳©`¥É
.mem_out (mem_out), // IÀí½Y¹û
/********** ¥Ñ¥¤¥×¥é¥¤¥óÖÆÓùÐźŠ**********/
// ¥Ñ¥¤¥×¥é¥¤¥ó¤Î×´B
.if_busy (if_busy), // IF¥¹¥Æ©`¥¸¥Ó¥¸©`
.ld_hazard (ld_hazard), // Load¥Ï¥¶©`¥É
.mem_busy (mem_busy), // MEM¥¹¥Æ©`¥¸¥Ó¥¸©`
// ¥¹¥È©`¥ëÐźÅ
.if_stall (if_stall), // IF¥¹¥Æ©`¥¸¥¹¥È©`¥ë
.id_stall (id_stall), // ID¥¹¥Æ©`¥¸¥¹¥È©`¥ë
.ex_stall (ex_stall), // EX¥¹¥Æ©`¥¸¥¹¥È©`¥ë
.mem_stall (mem_stall), // MEM¥¹¥Æ©`¥¸¥¹¥È©`¥ë
// ¥Õ¥é¥Ã¥·¥åÐźÅ
.if_flush (if_flush), // IF¥¹¥Æ©`¥¸¥Õ¥é¥Ã¥·¥å
.id_flush (id_flush), // ID¥¹¥Æ©`¥¸¥Õ¥é¥Ã¥·¥å
.ex_flush (ex_flush), // EX¥¹¥Æ©`¥¸¥Õ¥é¥Ã¥·¥å
.mem_flush (mem_flush), // MEM¥¹¥Æ©`¥¸¥Õ¥é¥Ã¥·¥å
// Ф·¤¤¥×¥í¥°¥é¥à¥«¥¦¥ó¥¿
.new_pc (new_pc) // Ф·¤¤¥×¥í¥°¥é¥à¥«¥¦¥ó¥¿
);
/********** øÓå쥸¥¹¥¿ **********/
gpr gpr (
/********** ¥¯¥í¥Ã¥¯ & ¥ê¥»¥Ã¥È **********/
.clk (clk), // ¥¯¥í¥Ã¥¯
.reset (reset), // ·ÇͬÆڥꥻ¥Ã¥È
/********** Õi¤ß³ö¤·¥Ý©`¥È 0 **********/
.rd_addr_0 (gpr_rd_addr_0), // Õi¤ß³ö¤·¥¢¥É¥ì¥¹
.rd_data_0 (gpr_rd_data_0), // Õi¤ß³ö¤·¥Ç©`¥¿
/********** Õi¤ß³ö¤·¥Ý©`¥È 1 **********/
.rd_addr_1 (gpr_rd_addr_1), // Õi¤ß³ö¤·¥¢¥É¥ì¥¹
.rd_data_1 (gpr_rd_data_1), // Õi¤ß³ö¤·¥Ç©`¥¿
/********** ø¤Þz¤ß¥Ý©`¥È **********/
.we_ (mem_gpr_we_), // ø¤Þz¤ßÓп
.wr_addr (mem_dst_addr), // ø¤Þz¤ß¥¢¥É¥ì¥¹
.wr_data (mem_out) // ø¤Þz¤ß¥Ç©`¥¿
);
/********** ¥¹¥¯¥é¥Ã¥Á¥Ñ¥Ã¥É¥á¥â¥ê **********/
spm spm (
/********** ¥¯¥í¥Ã¥¯ **********/
.clk (clk_), // ¥¯¥í¥Ã¥¯
/********** ¥Ý©`¥ÈA : IF¥¹¥Æ©`¥¸ **********/
.if_spm_addr (if_spm_addr[`SpmAddrLoc]), // ¥¢¥É¥ì¥¹
.if_spm_as_ (if_spm_as_), // ¥¢¥É¥ì¥¹¥¹¥È¥í©`¥Ö
.if_spm_rw (if_spm_rw), // Õi¤ß£¯ø¤
.if_spm_wr_data (if_spm_wr_data), // ø¤Þz¤ß¥Ç©`¥¿
.if_spm_rd_data (if_spm_rd_data), // Õi¤ß³ö¤·¥Ç©`¥¿
/********** ¥Ý©`¥ÈB : MEM¥¹¥Æ©`¥¸ **********/
.mem_spm_addr (mem_spm_addr[`SpmAddrLoc]), // ¥¢¥É¥ì¥¹
.mem_spm_as_ (mem_spm_as_), // ¥¢¥É¥ì¥¹¥¹¥È¥í©`¥Ö
.mem_spm_rw (mem_spm_rw), // Õi¤ß£¯ø¤
.mem_spm_wr_data (mem_spm_wr_data), // ø¤Þz¤ß¥Ç©`¥¿
.mem_spm_rd_data (mem_spm_rd_data) // Õi¤ß³ö¤·¥Ç©`¥¿
);
endmodule |
module ex_stage (
/********** ¥¯¥í¥Ã¥¯ & ¥ê¥»¥Ã¥È **********/
input wire clk, // ¥¯¥í¥Ã¥¯
input wire reset, // ·ÇͬÆڥꥻ¥Ã¥È
/********** ¥Ñ¥¤¥×¥é¥¤¥óÖÆÓùÐźŠ**********/
input wire stall, // ¥¹¥È©`¥ë
input wire flush, // ¥Õ¥é¥Ã¥·¥å
input wire int_detect, // ¸î¤êÞz¤ßʳö
/********** ¥Õ¥©¥ï©`¥Ç¥£¥ó¥° **********/
output wire [`WordDataBus] fwd_data, // ¥Õ¥©¥ï©`¥Ç¥£¥ó¥°¥Ç©`¥¿
/********** ID/EX¥Ñ¥¤¥×¥é¥¤¥ó¥ì¥¸¥¹¥¿ **********/
input wire [`WordAddrBus] id_pc, // ¥×¥í¥°¥é¥à¥«¥¦¥ó¥¿
input wire id_en, // ¥Ñ¥¤¥×¥é¥¤¥ó¥Ç©`¥¿¤ÎÓп
input wire [`AluOpBus] id_alu_op, // ALU¥ª¥Ú¥ì©`¥·¥ç¥ó
input wire [`WordDataBus] id_alu_in_0, // ALUÈëÁ¦ 0
input wire [`WordDataBus] id_alu_in_1, // ALUÈëÁ¦ 1
input wire id_br_flag, // ·Ö᪥ե饰
input wire [`MemOpBus] id_mem_op, // ¥á¥â¥ê¥ª¥Ú¥ì©`¥·¥ç¥ó
input wire [`WordDataBus] id_mem_wr_data, // ¥á¥â¥êø¤Þz¤ß¥Ç©`¥¿
input wire [`CtrlOpBus] id_ctrl_op, // ÖÆÓù¥ì¥¸¥¹¥¿¥ª¥Ú¥ì©`¥·¥ç¥ó
input wire [`RegAddrBus] id_dst_addr, // øÓå쥸¥¹¥¿ø¤Þz¤ß¥¢¥É¥ì¥¹
input wire id_gpr_we_, // øÓå쥸¥¹¥¿ø¤Þz¤ßÓп
input wire [`IsaExpBus] id_exp_code, // ÀýÍ⥳©`¥É
/********** EX/MEM¥Ñ¥¤¥×¥é¥¤¥ó¥ì¥¸¥¹¥¿ **********/
output wire [`WordAddrBus] ex_pc, // ¥×¥í¥°¥é¥à¥«¥¦¥ó¥¿
output wire ex_en, // ¥Ñ¥¤¥×¥é¥¤¥ó¥Ç©`¥¿¤ÎÓп
output wire ex_br_flag, // ·Ö᪥ե饰
output wire [`MemOpBus] ex_mem_op, // ¥á¥â¥ê¥ª¥Ú¥ì©`¥·¥ç¥ó
output wire [`WordDataBus] ex_mem_wr_data, // ¥á¥â¥êø¤Þz¤ß¥Ç©`¥¿
output wire [`CtrlOpBus] ex_ctrl_op, // ÖÆÓù¥ì¥¸¥¹¥¿¥ª¥Ú¥ì©`¥·¥ç¥ó
output wire [`RegAddrBus] ex_dst_addr, // øÓå쥸¥¹¥¿ø¤Þz¤ß¥¢¥É¥ì¥¹
output wire ex_gpr_we_, // øÓå쥸¥¹¥¿ø¤Þz¤ßÓп
output wire [`IsaExpBus] ex_exp_code, // ÀýÍ⥳©`¥É
output wire [`WordDataBus] ex_out // IÀí½Y¹û
);
/********** ALU¤Î³öÁ¦ **********/
wire [`WordDataBus] alu_out; // ÑÝËã½Y¹û
wire alu_of; // ¥ª©`¥Ð¥Õ¥í©`
/********** ÑÝËã½Y¹û¤Î¥Õ¥©¥ï©`¥Ç¥£¥ó¥° **********/
assign fwd_data = alu_out;
/********** ALU **********/
alu alu (
.in_0 (id_alu_in_0), // ÈëÁ¦ 0
.in_1 (id_alu_in_1), // ÈëÁ¦ 1
.op (id_alu_op), // ¥ª¥Ú¥ì©`¥·¥ç¥ó
.out (alu_out), // ³öÁ¦
.of (alu_of) // ¥ª©`¥Ð¥Õ¥í©`
);
/********** ¥Ñ¥¤¥×¥é¥¤¥ó¥ì¥¸¥¹¥¿ **********/
ex_reg ex_reg (
/********** ¥¯¥í¥Ã¥¯ & ¥ê¥»¥Ã¥È **********/
.clk (clk), // ¥¯¥í¥Ã¥¯
.reset (reset), // ·ÇͬÆڥꥻ¥Ã¥È
/********** ALU¤Î³öÁ¦ **********/
.alu_out (alu_out), // ÑÝËã½Y¹û
.alu_of (alu_of), // ¥ª©`¥Ð¥Õ¥í©`
/********** ¥Ñ¥¤¥×¥é¥¤¥óÖÆÓùÐźŠ**********/
.stall (stall), // ¥¹¥È©`¥ë
.flush (flush), // ¥Õ¥é¥Ã¥·¥å
.int_detect (int_detect), // ¸î¤êÞz¤ßʳö
/********** ID/EX¥Ñ¥¤¥×¥é¥¤¥ó¥ì¥¸¥¹¥¿ **********/
.id_pc (id_pc), // ¥×¥í¥°¥é¥à¥«¥¦¥ó¥¿
.id_en (id_en), // ¥Ñ¥¤¥×¥é¥¤¥ó¥Ç©`¥¿¤ÎÓп
.id_br_flag (id_br_flag), // ·Ö᪥ե饰
.id_mem_op (id_mem_op), // ¥á¥â¥ê¥ª¥Ú¥ì©`¥·¥ç¥ó
.id_mem_wr_data (id_mem_wr_data), // ¥á¥â¥êø¤Þz¤ß¥Ç©`¥¿
.id_ctrl_op (id_ctrl_op), // ÖÆÓù¥ì¥¸¥¹¥¿¥ª¥Ú¥ì©`¥·¥ç¥ó
.id_dst_addr (id_dst_addr), // øÓå쥸¥¹¥¿ø¤Þz¤ß¥¢¥É¥ì¥¹
.id_gpr_we_ (id_gpr_we_), // øÓå쥸¥¹¥¿ø¤Þz¤ßÓп
.id_exp_code (id_exp_code), // ÀýÍ⥳©`¥É
/********** EX/MEM¥Ñ¥¤¥×¥é¥¤¥ó¥ì¥¸¥¹¥¿ **********/
.ex_pc (ex_pc), // ¥×¥í¥°¥é¥à¥«¥¦¥ó¥¿
.ex_en (ex_en), // ¥Ñ¥¤¥×¥é¥¤¥ó¥Ç©`¥¿¤ÎÓп
.ex_br_flag (ex_br_flag), // ·Ö᪥ե饰
.ex_mem_op (ex_mem_op), // ¥á¥â¥ê¥ª¥Ú¥ì©`¥·¥ç¥ó
.ex_mem_wr_data (ex_mem_wr_data), // ¥á¥â¥êø¤Þz¤ß¥Ç©`¥¿
.ex_ctrl_op (ex_ctrl_op), // ÖÆÓù¥ì¥¸¥¹¥¿¥ª¥Ú¥ì©`¥·¥ç¥ó
.ex_dst_addr (ex_dst_addr), // øÓå쥸¥¹¥¿ø¤Þz¤ß¥¢¥É¥ì¥¹
.ex_gpr_we_ (ex_gpr_we_), // øÓå쥸¥¹¥¿ø¤Þz¤ßÓп
.ex_exp_code (ex_exp_code), // ÀýÍ⥳©`¥É
.ex_out (ex_out) // IÀí½Y¹û
);
endmodule |
module id_stage (
/********** ¥¯¥í¥Ã¥¯ & ¥ê¥»¥Ã¥È **********/
input wire clk, // ¥¯¥í¥Ã¥¯
input wire reset, // ·ÇͬÆڥꥻ¥Ã¥È
/********** GPR¥¤¥ó¥¿¥Õ¥§©`¥¹ **********/
input wire [`WordDataBus] gpr_rd_data_0, // Õi¤ß³ö¤·¥Ç©`¥¿ 0
input wire [`WordDataBus] gpr_rd_data_1, // Õi¤ß³ö¤·¥Ç©`¥¿ 1
output wire [`RegAddrBus] gpr_rd_addr_0, // Õi¤ß³ö¤·¥¢¥É¥ì¥¹ 0
output wire [`RegAddrBus] gpr_rd_addr_1, // Õi¤ß³ö¤·¥¢¥É¥ì¥¹ 1
/********** ¥Õ¥©¥ï©`¥Ç¥£¥ó¥° **********/
// EX¥¹¥Æ©`¥¸¤«¤é¤Î¥Õ¥©¥ï©`¥Ç¥£¥ó¥°
input wire ex_en, // ¥Ñ¥¤¥×¥é¥¤¥ó¥Ç©`¥¿¤ÎÓп
input wire [`WordDataBus] ex_fwd_data, // ¥Õ¥©¥ï©`¥Ç¥£¥ó¥°¥Ç©`¥¿
input wire [`RegAddrBus] ex_dst_addr, // ø¤Þz¤ß¥¢¥É¥ì¥¹
input wire ex_gpr_we_, // ø¤Þz¤ßÓп
// MEM¥¹¥Æ©`¥¸¤«¤é¤Î¥Õ¥©¥ï©`¥Ç¥£¥ó¥°
input wire [`WordDataBus] mem_fwd_data, // ¥Õ¥©¥ï©`¥Ç¥£¥ó¥°¥Ç©`¥¿
/********** ÖÆÓù¥ì¥¸¥¹¥¿¥¤¥ó¥¿¥Õ¥§©`¥¹ **********/
input wire [`CpuExeModeBus] exe_mode, // gÐÐ¥â©`¥É
input wire [`WordDataBus] creg_rd_data, // Õi¤ß³ö¤·¥Ç©`¥¿
output wire [`RegAddrBus] creg_rd_addr, // Õi¤ß³ö¤·¥¢¥É¥ì¥¹
/********** ¥Ñ¥¤¥×¥é¥¤¥óÖÆÓùÐźŠ**********/
input wire stall, // ¥¹¥È©`¥ë
input wire flush, // ¥Õ¥é¥Ã¥·¥å
output wire [`WordAddrBus] br_addr, // ·Ö᪥¢¥É¥ì¥¹
output wire br_taken, // ·Ö᪤γÉÁ¢
output wire ld_hazard, // ¥í©`¥É¥Ï¥¶©`¥É
/********** IF/ID¥Ñ¥¤¥×¥é¥¤¥ó¥ì¥¸¥¹¥¿ **********/
input wire [`WordAddrBus] if_pc, // ¥×¥í¥°¥é¥à¥«¥¦¥ó¥¿
input wire [`WordDataBus] if_insn, // ÃüÁî
input wire if_en, // ¥Ñ¥¤¥×¥é¥¤¥ó¥Ç©`¥¿¤ÎÓп
/********** ID/EX¥Ñ¥¤¥×¥é¥¤¥ó¥ì¥¸¥¹¥¿ **********/
output wire [`WordAddrBus] id_pc, // ¥×¥í¥°¥é¥à¥«¥¦¥ó¥¿
output wire id_en, // ¥Ñ¥¤¥×¥é¥¤¥ó¥Ç©`¥¿¤ÎÓп
output wire [`AluOpBus] id_alu_op, // ALU¥ª¥Ú¥ì©`¥·¥ç¥ó
output wire [`WordDataBus] id_alu_in_0, // ALUÈëÁ¦ 0
output wire [`WordDataBus] id_alu_in_1, // ALUÈëÁ¦ 1
output wire id_br_flag, // ·Ö᪥ե饰
output wire [`MemOpBus] id_mem_op, // ¥á¥â¥ê¥ª¥Ú¥ì©`¥·¥ç¥ó
output wire [`WordDataBus] id_mem_wr_data, // ¥á¥â¥êø¤Þz¤ß¥Ç©`¥¿
output wire [`CtrlOpBus] id_ctrl_op, // ÖÆÓù¥ª¥Ú¥ì©`¥·¥ç¥ó
output wire [`RegAddrBus] id_dst_addr, // GPRø¤Þz¤ß¥¢¥É¥ì¥¹
output wire id_gpr_we_, // GPRø¤Þz¤ßÓп
output wire [`IsaExpBus] id_exp_code // ÀýÍ⥳©`¥É
);
/********** ¥Ç¥³©`¥ÉÐźŠ**********/
wire [`AluOpBus] alu_op; // ALU¥ª¥Ú¥ì©`¥·¥ç¥ó
wire [`WordDataBus] alu_in_0; // ALUÈëÁ¦ 0
wire [`WordDataBus] alu_in_1; // ALUÈëÁ¦ 1
wire br_flag; // ·Ö᪥ե饰
wire [`MemOpBus] mem_op; // ¥á¥â¥ê¥ª¥Ú¥ì©`¥·¥ç¥ó
wire [`WordDataBus] mem_wr_data; // ¥á¥â¥êø¤Þz¤ß¥Ç©`¥¿
wire [`CtrlOpBus] ctrl_op; // ÖÆÓù¥ª¥Ú¥ì©`¥·¥ç¥ó
wire [`RegAddrBus] dst_addr; // GPRø¤Þz¤ß¥¢¥É¥ì¥¹
wire gpr_we_; // GPRø¤Þz¤ßÓп
wire [`IsaExpBus] exp_code; // ÀýÍ⥳©`¥É
/********** ¥Ç¥³©`¥À **********/
decoder decoder (
/********** IF/ID¥Ñ¥¤¥×¥é¥¤¥ó¥ì¥¸¥¹¥¿ **********/
.if_pc (if_pc), // ¥×¥í¥°¥é¥à¥«¥¦¥ó¥¿
.if_insn (if_insn), // ÃüÁî
.if_en (if_en), // ¥Ñ¥¤¥×¥é¥¤¥ó¥Ç©`¥¿¤ÎÓп
/********** GPR¥¤¥ó¥¿¥Õ¥§©`¥¹ **********/
.gpr_rd_data_0 (gpr_rd_data_0), // Õi¤ß³ö¤·¥Ç©`¥¿ 0
.gpr_rd_data_1 (gpr_rd_data_1), // Õi¤ß³ö¤·¥Ç©`¥¿ 1
.gpr_rd_addr_0 (gpr_rd_addr_0), // Õi¤ß³ö¤·¥¢¥É¥ì¥¹ 0
.gpr_rd_addr_1 (gpr_rd_addr_1), // Õi¤ß³ö¤·¥¢¥É¥ì¥¹ 1
/********** ¥Õ¥©¥ï©`¥Ç¥£¥ó¥° **********/
// ID¥¹¥Æ©`¥¸¤«¤é¤Î¥Õ¥©¥ï©`¥Ç¥£¥ó¥°
.id_en (id_en), // ¥Ñ¥¤¥×¥é¥¤¥ó¥Ç©`¥¿¤ÎÓп
.id_dst_addr (id_dst_addr), // ø¤Þz¤ß¥¢¥É¥ì¥¹
.id_gpr_we_ (id_gpr_we_), // ø¤Þz¤ßÓп
.id_mem_op (id_mem_op), // ¥á¥â¥ê¥ª¥Ú¥ì©`¥·¥ç¥ó
// EX¥¹¥Æ©`¥¸¤«¤é¤Î¥Õ¥©¥ï©`¥Ç¥£¥ó¥°
.ex_en (ex_en), // ¥Ñ¥¤¥×¥é¥¤¥ó¥Ç©`¥¿¤ÎÓп
.ex_fwd_data (ex_fwd_data), // ¥Õ¥©¥ï©`¥Ç¥£¥ó¥°¥Ç©`¥¿
.ex_dst_addr (ex_dst_addr), // ø¤Þz¤ß¥¢¥É¥ì¥¹
.ex_gpr_we_ (ex_gpr_we_), // ø¤Þz¤ßÓп
// MEM¥¹¥Æ©`¥¸¤«¤é¤Î¥Õ¥©¥ï©`¥Ç¥£¥ó¥°
.mem_fwd_data (mem_fwd_data), // ¥Õ¥©¥ï©`¥Ç¥£¥ó¥°¥Ç©`¥¿
/********** ÖÆÓù¥ì¥¸¥¹¥¿¥¤¥ó¥¿¥Õ¥§©`¥¹ **********/
.exe_mode (exe_mode), // gÐÐ¥â©`¥É
.creg_rd_data (creg_rd_data), // Õi¤ß³ö¤·¥Ç©`¥¿
.creg_rd_addr (creg_rd_addr), // Õi¤ß³ö¤·¥¢¥É¥ì¥¹
/********** ¥Ç¥³©`¥ÉÐźŠ**********/
.alu_op (alu_op), // ALU¥ª¥Ú¥ì©`¥·¥ç¥ó
.alu_in_0 (alu_in_0), // ALUÈëÁ¦ 0
.alu_in_1 (alu_in_1), // ALUÈëÁ¦ 1
.br_addr (br_addr), // ·Ö᪥¢¥É¥ì¥¹
.br_taken (br_taken), // ·Ö᪤γÉÁ¢
.br_flag (br_flag), // ·Ö᪥ե饰
.mem_op (mem_op), // ¥á¥â¥ê¥ª¥Ú¥ì©`¥·¥ç¥ó
.mem_wr_data (mem_wr_data), // ¥á¥â¥êø¤Þz¤ß¥Ç©`¥¿
.ctrl_op (ctrl_op), // ÖÆÓù¥ª¥Ú¥ì©`¥·¥ç¥ó
.dst_addr (dst_addr), // øÓå쥸¥¹¥¿ø¤Þz¤ß¥¢¥É¥ì¥¹
.gpr_we_ (gpr_we_), // øÓå쥸¥¹¥¿ø¤Þz¤ßÓп
.exp_code (exp_code), // ÀýÍ⥳©`¥É
.ld_hazard (ld_hazard) // ¥í©`¥É¥Ï¥¶©`¥É
);
/********** ¥Ñ¥¤¥×¥é¥¤¥ó¥ì¥¸¥¹¥¿ **********/
id_reg id_reg (
/********** ¥¯¥í¥Ã¥¯ & ¥ê¥»¥Ã¥È **********/
.clk (clk), // ¥¯¥í¥Ã¥¯
.reset (reset), // ·ÇͬÆڥꥻ¥Ã¥È
/********** ¥Ç¥³©`¥É½Y¹û **********/
.alu_op (alu_op), // ALU¥ª¥Ú¥ì©`¥·¥ç¥ó
.alu_in_0 (alu_in_0), // ALUÈëÁ¦ 0
.alu_in_1 (alu_in_1), // ALUÈëÁ¦ 1
.br_flag (br_flag), // ·Ö᪥ե饰
.mem_op (mem_op), // ¥á¥â¥ê¥ª¥Ú¥ì©`¥·¥ç¥ó
.mem_wr_data (mem_wr_data), // ¥á¥â¥êø¤Þz¤ß¥Ç©`¥¿
.ctrl_op (ctrl_op), // ÖÆÓù¥ª¥Ú¥ì©`¥·¥ç¥ó
.dst_addr (dst_addr), // øÓå쥸¥¹¥¿ø¤Þz¤ß¥¢¥É¥ì¥¹
.gpr_we_ (gpr_we_), // øÓå쥸¥¹¥¿ø¤Þz¤ßÓп
.exp_code (exp_code), // ÀýÍ⥳©`¥É
/********** ¥Ñ¥¤¥×¥é¥¤¥óÖÆÓùÐźŠ**********/
.stall (stall), // ¥¹¥È©`¥ë
.flush (flush), // ¥Õ¥é¥Ã¥·¥å
/********** IF/ID¥Ñ¥¤¥×¥é¥¤¥ó¥ì¥¸¥¹¥¿ **********/
.if_pc (if_pc), // ¥×¥í¥°¥é¥à¥«¥¦¥ó¥¿
.if_en (if_en), // ¥Ñ¥¤¥×¥é¥¤¥ó¥Ç©`¥¿¤ÎÓп
/********** ID/EX¥Ñ¥¤¥×¥é¥¤¥ó¥ì¥¸¥¹¥¿ **********/
.id_pc (id_pc), // ¥×¥í¥°¥é¥à¥«¥¦¥ó¥¿
.id_en (id_en), // ¥Ñ¥¤¥×¥é¥¤¥ó¥Ç©`¥¿¤ÎÓп
.id_alu_op (id_alu_op), // ALU¥ª¥Ú¥ì©`¥·¥ç¥ó
.id_alu_in_0 (id_alu_in_0), // ALUÈëÁ¦ 0
.id_alu_in_1 (id_alu_in_1), // ALUÈëÁ¦ 1
.id_br_flag (id_br_flag), // ·Ö᪥ե饰
.id_mem_op (id_mem_op), // ¥á¥â¥ê¥ª¥Ú¥ì©`¥·¥ç¥ó
.id_mem_wr_data (id_mem_wr_data), // ¥á¥â¥êø¤Þz¤ß¥Ç©`¥¿
.id_ctrl_op (id_ctrl_op), // ÖÆÓù¥ª¥Ú¥ì©`¥·¥ç¥ó
.id_dst_addr (id_dst_addr), // øÓå쥸¥¹¥¿ø¤Þz¤ß¥¢¥É¥ì¥¹
.id_gpr_we_ (id_gpr_we_), // øÓå쥸¥¹¥¿ø¤Þz¤ßÓп
.id_exp_code (id_exp_code) // ÀýÍ⥳©`¥É
);
endmodule |
module decoder (
/********** IF/ID¥Ñ¥¤¥×¥é¥¤¥ó¥ì¥¸¥¹¥¿ **********/
input wire [`WordAddrBus] if_pc, // ¥×¥í¥°¥é¥à¥«¥¦¥ó¥¿
input wire [`WordDataBus] if_insn, // ÃüÁî
input wire if_en, // ¥Ñ¥¤¥×¥é¥¤¥ó¥Ç©`¥¿¤ÎÓп
/********** GPR¥¤¥ó¥¿¥Õ¥§©`¥¹ **********/
input wire [`WordDataBus] gpr_rd_data_0, // Õi¤ß³ö¤·¥Ç©`¥¿ 0
input wire [`WordDataBus] gpr_rd_data_1, // Õi¤ß³ö¤·¥Ç©`¥¿ 1
output wire [`RegAddrBus] gpr_rd_addr_0, // Õi¤ß³ö¤·¥¢¥É¥ì¥¹ 0
output wire [`RegAddrBus] gpr_rd_addr_1, // Õi¤ß³ö¤·¥¢¥É¥ì¥¹ 1
/********** ¥Õ¥©¥ï©`¥Ç¥£¥ó¥° **********/
// ID¥¹¥Æ©`¥¸¤«¤é¤Î¥Õ¥©¥ï©`¥Ç¥£¥ó¥°
input wire id_en, // ¥Ñ¥¤¥×¥é¥¤¥ó¥Ç©`¥¿¤ÎÓп
input wire [`RegAddrBus] id_dst_addr, // ø¤Þz¤ß¥¢¥É¥ì¥¹
input wire id_gpr_we_, // ø¤Þz¤ßÓп
input wire [`MemOpBus] id_mem_op, // ¥á¥â¥ê¥ª¥Ú¥ì©`¥·¥ç¥ó
// EX¥¹¥Æ©`¥¸¤«¤é¤Î¥Õ¥©¥ï©`¥Ç¥£¥ó¥°
input wire ex_en, // ¥Ñ¥¤¥×¥é¥¤¥ó¥Ç©`¥¿¤ÎÓп
input wire [`RegAddrBus] ex_dst_addr, // ø¤Þz¤ß¥¢¥É¥ì¥¹
input wire ex_gpr_we_, // ø¤Þz¤ßÓп
input wire [`WordDataBus] ex_fwd_data, // ¥Õ¥©¥ï©`¥Ç¥£¥ó¥°¥Ç©`¥¿
// MEM¥¹¥Æ©`¥¸¤«¤é¤Î¥Õ¥©¥ï©`¥Ç¥£¥ó¥°
input wire [`WordDataBus] mem_fwd_data, // ¥Õ¥©¥ï©`¥Ç¥£¥ó¥°¥Ç©`¥¿
/********** ÖÆÓù¥ì¥¸¥¹¥¿¥¤¥ó¥¿¥Õ¥§©`¥¹ **********/
input wire [`CpuExeModeBus] exe_mode, // gÐÐ¥â©`¥É
input wire [`WordDataBus] creg_rd_data, // Õi¤ß³ö¤·¥Ç©`¥¿
output wire [`RegAddrBus] creg_rd_addr, // Õi¤ß³ö¤·¥¢¥É¥ì¥¹
/********** ¥Ç¥³©`¥É½Y¹û **********/
output reg [`AluOpBus] alu_op, // ALU¥ª¥Ú¥ì©`¥·¥ç¥ó
output reg [`WordDataBus] alu_in_0, // ALUÈëÁ¦ 0
output reg [`WordDataBus] alu_in_1, // ALUÈëÁ¦ 1
output reg [`WordAddrBus] br_addr, // ·Ö᪥¢¥É¥ì¥¹
output reg br_taken, // ·Ö᪤γÉÁ¢
output reg br_flag, // ·Ö᪥ե饰
output reg [`MemOpBus] mem_op, // ¥á¥â¥ê¥ª¥Ú¥ì©`¥·¥ç¥ó
output wire [`WordDataBus] mem_wr_data, // ¥á¥â¥êø¤Þz¤ß¥Ç©`¥¿
output reg [`CtrlOpBus] ctrl_op, // ÖÆÓù¥ª¥Ú¥ì©`¥·¥ç¥ó
output reg [`RegAddrBus] dst_addr, // øÓå쥸¥¹¥¿ø¤Þz¤ß¥¢¥É¥ì¥¹
output reg gpr_we_, // øÓå쥸¥¹¥¿ø¤Þz¤ßÓп
output reg [`IsaExpBus] exp_code, // ÀýÍ⥳©`¥É
output reg ld_hazard // ¥í©`¥É¥Ï¥¶©`¥É
);
/********** ÃüÁî¥Õ¥£©`¥ë¥É **********/
wire [`IsaOpBus] op = if_insn[`IsaOpLoc]; // ¥ª¥Ú¥³©`¥É
wire [`RegAddrBus] ra_addr = if_insn[`IsaRaAddrLoc]; // Ra¥¢¥É¥ì¥¹
wire [`RegAddrBus] rb_addr = if_insn[`IsaRbAddrLoc]; // Rb¥¢¥É¥ì¥¹
wire [`RegAddrBus] rc_addr = if_insn[`IsaRcAddrLoc]; // Rc¥¢¥É¥ì¥¹
wire [`IsaImmBus] imm = if_insn[`IsaImmLoc]; // ¼´
/********** ¼´ **********/
// ·ûºÅ
wire [`WordDataBus] imm_s = {{`ISA_EXT_W{imm[`ISA_IMM_MSB]}}, imm};
// ¥¼¥í
wire [`WordDataBus] imm_u = {{`ISA_EXT_W{1'b0}}, imm};
/********** ¥ì¥¸¥¹¥¿¤ÎÕi¤ß³ö¤·¥¢¥É¥ì¥¹ **********/
assign gpr_rd_addr_0 = ra_addr; // øÓå쥸¥¹¥¿Õi¤ß³ö¤·¥¢¥É¥ì¥¹ 0
assign gpr_rd_addr_1 = rb_addr; // øÓå쥸¥¹¥¿Õi¤ß³ö¤·¥¢¥É¥ì¥¹ 1
assign creg_rd_addr = ra_addr; // ÖÆÓù¥ì¥¸¥¹¥¿Õi¤ß³ö¤·¥¢¥É¥ì¥¹
/********** øÓå쥸¥¹¥¿¤ÎÕi¤ß³ö¤·¥Ç©`¥¿ **********/
reg [`WordDataBus] ra_data; // ·ûºÅ¤Ê¤·Ra
wire signed [`WordDataBus] s_ra_data = $signed(ra_data); // ·ûºÅ¸¶¤Ra
reg [`WordDataBus] rb_data; // ·ûºÅ¤Ê¤·Rb
wire signed [`WordDataBus] s_rb_data = $signed(rb_data); // ·ûºÅ¸¶¤Rb
assign mem_wr_data = rb_data; // ¥á¥â¥êø¤Þz¤ß¥Ç©`¥¿
/********** ¥¢¥É¥ì¥¹ **********/
wire [`WordAddrBus] ret_addr = if_pc + 1'b1; // ø¤ê·¬µØ
wire [`WordAddrBus] br_target = if_pc + imm_s[`WORD_ADDR_MSB:0]; // ·ÖáªÏÈ
wire [`WordAddrBus] jr_target = ra_data[`WordAddrLoc]; // ¥¸¥ã¥ó¥×ÏÈ
/********** ¥Õ¥©¥ï©`¥Ç¥£¥ó¥° **********/
always @(*) begin
/* Ra¥ì¥¸¥¹¥¿ */
if ((id_en == `ENABLE) && (id_gpr_we_ == `ENABLE_) &&
(id_dst_addr == ra_addr)) begin
ra_data = ex_fwd_data; // EX¥¹¥Æ©`¥¸¤«¤é¤Î¥Õ¥©¥ï©`¥Ç¥£¥ó¥°
end else if ((ex_en == `ENABLE) && (ex_gpr_we_ == `ENABLE_) &&
(ex_dst_addr == ra_addr)) begin
ra_data = mem_fwd_data; // MEM¥¹¥Æ©`¥¸¤«¤é¤Î¥Õ¥©¥ï©`¥Ç¥£¥ó¥°
end else begin
ra_data = gpr_rd_data_0; // ¥ì¥¸¥¹¥¿¥Õ¥¡¥¤¥ë¤«¤é¤ÎÕi¤ß³ö¤·
end
/* Rb¥ì¥¸¥¹¥¿ */
if ((id_en == `ENABLE) && (id_gpr_we_ == `ENABLE_) &&
(id_dst_addr == rb_addr)) begin
rb_data = ex_fwd_data; // EX¥¹¥Æ©`¥¸¤«¤é¤Î¥Õ¥©¥ï©`¥Ç¥£¥ó¥°
end else if ((ex_en == `ENABLE) && (ex_gpr_we_ == `ENABLE_) &&
(ex_dst_addr == rb_addr)) begin
rb_data = mem_fwd_data; // MEM¥¹¥Æ©`¥¸¤«¤é¤Î¥Õ¥©¥ï©`¥Ç¥£¥ó¥°
end else begin
rb_data = gpr_rd_data_1; // ¥ì¥¸¥¹¥¿¥Õ¥¡¥¤¥ë¤«¤é¤ÎÕi¤ß³ö¤·
end
end
/********** ¥í©`¥É¥Ï¥¶©`¥É¤Îʳö **********/
always @(*) begin
if ((id_en == `ENABLE) && (id_mem_op == `MEM_OP_LDW) &&
((id_dst_addr == ra_addr) || (id_dst_addr == rb_addr))) begin
ld_hazard = `ENABLE; // ¥í©`¥É¥Ï¥¶©`¥É
end else begin
ld_hazard = `DISABLE; // ¥Ï¥¶©`¥É¤Ê¤·
end
end
/********** ÃüÁî¤Î¥Ç¥³©`¥É **********/
always @(*) begin
/* ¥Ç¥Õ¥©¥ë¥È */
alu_op = `ALU_OP_NOP;
alu_in_0 = ra_data;
alu_in_1 = rb_data;
br_taken = `DISABLE;
br_flag = `DISABLE;
br_addr = {`WORD_ADDR_W{1'b0}};
mem_op = `MEM_OP_NOP;
ctrl_op = `CTRL_OP_NOP;
dst_addr = rb_addr;
gpr_we_ = `DISABLE_;
exp_code = `ISA_EXP_NO_EXP;
/* ¥ª¥Ú¥³©`¥É¤ÎÅж¨ */
if (if_en == `ENABLE) begin
case (op)
/* ÕÀíÑÝËãÃüÁî */
`ISA_OP_ANDR : begin // ¥ì¥¸¥¹¥¿Í¬Ê¿¤ÎÕÀí·e
alu_op = `ALU_OP_AND;
dst_addr = rc_addr;
gpr_we_ = `ENABLE_;
end
`ISA_OP_ANDI : begin // ¥ì¥¸¥¹¥¿¤È¼´¤ÎÕÀí·e
alu_op = `ALU_OP_AND;
alu_in_1 = imm_u;
gpr_we_ = `ENABLE_;
end
`ISA_OP_ORR : begin // ¥ì¥¸¥¹¥¿Í¬Ê¿¤ÎÕÀíºÍ
alu_op = `ALU_OP_OR;
dst_addr = rc_addr;
gpr_we_ = `ENABLE_;
end
`ISA_OP_ORI : begin // ¥ì¥¸¥¹¥¿¤È¼´¤ÎÕÀíºÍ
alu_op = `ALU_OP_OR;
alu_in_1 = imm_u;
gpr_we_ = `ENABLE_;
end
`ISA_OP_XORR : begin // ¥ì¥¸¥¹¥¿Í¬Ê¿¤ÎÅÅËûµÄÕÀíºÍ
alu_op = `ALU_OP_XOR;
dst_addr = rc_addr;
gpr_we_ = `ENABLE_;
end
`ISA_OP_XORI : begin // ¥ì¥¸¥¹¥¿¤È¼´¤ÎÅÅËûµÄÕÀíºÍ
alu_op = `ALU_OP_XOR;
alu_in_1 = imm_u;
gpr_we_ = `ENABLE_;
end
/* ËãÐgÑÝËãÃüÁî */
`ISA_OP_ADDSR : begin // ¥ì¥¸¥¹¥¿Í¬Ê¿¤Î·ûºÅ¸¶¤¼ÓËã
alu_op = `ALU_OP_ADDS;
dst_addr = rc_addr;
gpr_we_ = `ENABLE_;
end
`ISA_OP_ADDSI : begin // ¥ì¥¸¥¹¥¿¤È¼´¤Î·ûºÅ¸¶¤¼ÓËã
alu_op = `ALU_OP_ADDS;
alu_in_1 = imm_s;
gpr_we_ = `ENABLE_;
end
`ISA_OP_ADDUR : begin // ¥ì¥¸¥¹¥¿Í¬Ê¿¤Î·ûºÅ¤Ê¤·¼ÓËã
alu_op = `ALU_OP_ADDU;
dst_addr = rc_addr;
gpr_we_ = `ENABLE_;
end
`ISA_OP_ADDUI : begin // ¥ì¥¸¥¹¥¿¤È¼´¤Î·ûºÅ¤Ê¤·¼ÓËã
alu_op = `ALU_OP_ADDU;
alu_in_1 = imm_s;
gpr_we_ = `ENABLE_;
end
`ISA_OP_SUBSR : begin // ¥ì¥¸¥¹¥¿Í¬Ê¿¤Î·ûºÅ¸¶¤pËã
alu_op = `ALU_OP_SUBS;
dst_addr = rc_addr;
gpr_we_ = `ENABLE_;
end
`ISA_OP_SUBUR : begin // ¥ì¥¸¥¹¥¿Í¬Ê¿¤Î·ûºÅ¤Ê¤·pËã
alu_op = `ALU_OP_SUBU;
dst_addr = rc_addr;
gpr_we_ = `ENABLE_;
end
/* ¥·¥Õ¥ÈÃüÁî */
`ISA_OP_SHRLR : begin // ¥ì¥¸¥¹¥¿Í¬Ê¿¤ÎÕÀíÓÒ¥·¥Õ¥È
alu_op = `ALU_OP_SHRL;
dst_addr = rc_addr;
gpr_we_ = `ENABLE_;
end
`ISA_OP_SHRLI : begin // ¥ì¥¸¥¹¥¿¤È¼´¤ÎÕÀíÓÒ¥·¥Õ¥È
alu_op = `ALU_OP_SHRL;
alu_in_1 = imm_u;
gpr_we_ = `ENABLE_;
end
`ISA_OP_SHLLR : begin // ¥ì¥¸¥¹¥¿Í¬Ê¿¤ÎÕÀí×ó¥·¥Õ¥È
alu_op = `ALU_OP_SHLL;
dst_addr = rc_addr;
gpr_we_ = `ENABLE_;
end
`ISA_OP_SHLLI : begin // ¥ì¥¸¥¹¥¿¤È¼´¤ÎÕÀí×ó¥·¥Õ¥È
alu_op = `ALU_OP_SHLL;
alu_in_1 = imm_u;
gpr_we_ = `ENABLE_;
end
/* ·ÖáªÃüÁî */
`ISA_OP_BE : begin // ¥ì¥¸¥¹¥¿Í¬Ê¿¤Î·ûºÅ¸¶¤±ÈÝ^£¨Ra == Rb£©
br_addr = br_target;
br_taken = (ra_data == rb_data) ? `ENABLE : `DISABLE;
br_flag = `ENABLE;
end
`ISA_OP_BNE : begin // ¥ì¥¸¥¹¥¿Í¬Ê¿¤Î·ûºÅ¸¶¤±ÈÝ^£¨Ra != Rb£©
br_addr = br_target;
br_taken = (ra_data != rb_data) ? `ENABLE : `DISABLE;
br_flag = `ENABLE;
end
`ISA_OP_BSGT : begin // ¥ì¥¸¥¹¥¿Í¬Ê¿¤Î·ûºÅ¸¶¤±ÈÝ^£¨Ra < Rb£©
br_addr = br_target;
br_taken = (s_ra_data < s_rb_data) ? `ENABLE : `DISABLE;
br_flag = `ENABLE;
end
`ISA_OP_BUGT : begin // ¥ì¥¸¥¹¥¿Í¬Ê¿¤Î·ûºÅ¤Ê¤·±ÈÝ^£¨Ra < Rb£©
br_addr = br_target;
br_taken = (ra_data < rb_data) ? `ENABLE : `DISABLE;
br_flag = `ENABLE;
end
`ISA_OP_JMP : begin // oÌõ¼þ·Öáª
br_addr = jr_target;
br_taken = `ENABLE;
br_flag = `ENABLE;
end
`ISA_OP_CALL : begin // ¥³©`¥ë
alu_in_0 = {ret_addr, {`BYTE_OFFSET_W{1'b0}}};
br_addr = jr_target;
br_taken = `ENABLE;
br_flag = `ENABLE;
dst_addr = `REG_ADDR_W'd31;
gpr_we_ = `ENABLE_;
end
/* ¥á¥â¥ê¥¢¥¯¥»¥¹ÃüÁî */
`ISA_OP_LDW : begin // ¥ï©`¥ÉÕi¤ß³ö¤·
alu_op = `ALU_OP_ADDU;
alu_in_1 = imm_s;
mem_op = `MEM_OP_LDW;
gpr_we_ = `ENABLE_;
end
`ISA_OP_STW : begin // ¥ï©`¥Éø¤Þz¤ß
alu_op = `ALU_OP_ADDU;
alu_in_1 = imm_s;
mem_op = `MEM_OP_STW;
end
/* ¥·¥¹¥Æ¥à¥³©`¥ëÃüÁî */
`ISA_OP_TRAP : begin // ¥È¥é¥Ã¥×
exp_code = `ISA_EXP_TRAP;
end
/* ÌØØÃüÁî */
`ISA_OP_RDCR : begin // ÖÆÓù¥ì¥¸¥¹¥¿¤ÎÕi¤ß³ö¤·
if (exe_mode == `CPU_KERNEL_MODE) begin
alu_in_0 = creg_rd_data;
gpr_we_ = `ENABLE_;
end else begin
exp_code = `ISA_EXP_PRV_VIO;
end
end
`ISA_OP_WRCR : begin // ÖÆÓù¥ì¥¸¥¹¥¿¤Ø¤Îø¤Þz¤ß
if (exe_mode == `CPU_KERNEL_MODE) begin
ctrl_op = `CTRL_OP_WRCR;
end else begin
exp_code = `ISA_EXP_PRV_VIO;
end
end
`ISA_OP_EXRT : begin // ÀýÍ⤫¤é¤ÎÍ¢
if (exe_mode == `CPU_KERNEL_MODE) begin
ctrl_op = `CTRL_OP_EXRT;
end else begin
exp_code = `ISA_EXP_PRV_VIO;
end
end
/* ¤½¤ÎËû¤ÎÃüÁî */
default : begin // 䶨ÁxÃüÁî
exp_code = `ISA_EXP_UNDEF_INSN;
end
endcase
end
end
endmodule |
module if_stage (
/********** ¥¯¥í¥Ã¥¯ & ¥ê¥»¥Ã¥È **********/
input wire clk, // ¥¯¥í¥Ã¥¯
input wire reset, // ·ÇͬÆڥꥻ¥Ã¥È
/********** SPM¥¤¥ó¥¿¥Õ¥§©`¥¹ **********/
input wire [`WordDataBus] spm_rd_data, // Õi¤ß³ö¤·¥Ç©`¥¿
output wire [`WordAddrBus] spm_addr, // ¥¢¥É¥ì¥¹
output wire spm_as_, // ¥¢¥É¥ì¥¹¥¹¥È¥í©`¥Ö
output wire spm_rw, // Õi¤ß£¯ø¤
output wire [`WordDataBus] spm_wr_data, // ø¤Þz¤ß¥Ç©`¥¿
/********** ¥Ð¥¹¥¤¥ó¥¿¥Õ¥§©`¥¹ **********/
input wire [`WordDataBus] bus_rd_data, // Õi¤ß³ö¤·¥Ç©`¥¿
input wire bus_rdy_, // ¥ì¥Ç¥£
input wire bus_grnt_, // ¥Ð¥¹¥°¥é¥ó¥È
output wire bus_req_, // ¥Ð¥¹¥ê¥¯¥¨¥¹¥È
output wire [`WordAddrBus] bus_addr, // ¥¢¥É¥ì¥¹
output wire bus_as_, // ¥¢¥É¥ì¥¹¥¹¥È¥í©`¥Ö
output wire bus_rw, // Õi¤ß£¯ø¤
output wire [`WordDataBus] bus_wr_data, // ø¤Þz¤ß¥Ç©`¥¿
/********** ¥Ñ¥¤¥×¥é¥¤¥óÖÆÓùÐźŠ**********/
input wire stall, // ¥¹¥È©`¥ë
input wire flush, // ¥Õ¥é¥Ã¥·¥å
input wire [`WordAddrBus] new_pc, // Ф·¤¤¥×¥í¥°¥é¥à¥«¥¦¥ó¥¿
input wire br_taken, // ·Ö᪤γÉÁ¢
input wire [`WordAddrBus] br_addr, // ·ÖáªÏÈ¥¢¥É¥ì¥¹
output wire busy, // ¥Ó¥¸©`ÐźÅ
/********** IF/ID¥Ñ¥¤¥×¥é¥¤¥ó¥ì¥¸¥¹¥¿ **********/
output wire [`WordAddrBus] if_pc, // ¥×¥í¥°¥é¥à¥«¥¦¥ó¥¿
output wire [`WordDataBus] if_insn, // ÃüÁî
output wire if_en // ¥Ñ¥¤¥×¥é¥¤¥ó¥Ç©`¥¿¤ÎÓп
);
/********** ÄÚ²¿½Ó¾AÐźŠ**********/
wire [`WordDataBus] insn; // ¥Õ¥§¥Ã¥Á¤·¤¿ÃüÁî
/********** ¥Ð¥¹¥¤¥ó¥¿¥Õ¥§©`¥¹ **********/
bus_if bus_if (
/********** ¥¯¥í¥Ã¥¯ & ¥ê¥»¥Ã¥È **********/
.clk (clk), // ¥¯¥í¥Ã¥¯
.reset (reset), // ·ÇͬÆڥꥻ¥Ã¥È
/********** ¥Ñ¥¤¥×¥é¥¤¥óÖÆÓùÐźŠ**********/
.stall (stall), // ¥¹¥È©`¥ë
.flush (flush), // ¥Õ¥é¥Ã¥·¥åÐźÅ
.busy (busy), // ¥Ó¥¸©`ÐźÅ
/********** CPU¥¤¥ó¥¿¥Õ¥§©`¥¹ **********/
.addr (if_pc), // ¥¢¥É¥ì¥¹
.as_ (`ENABLE_), // ¥¢¥É¥ì¥¹Óп
.rw (`READ), // Õi¤ß£¯ø¤
.wr_data (`WORD_DATA_W'h0), // ø¤Þz¤ß¥Ç©`¥¿
.rd_data (insn), // Õi¤ß³ö¤·¥Ç©`¥¿
/********** ¥¹¥¯¥é¥Ã¥Á¥Ñ¥Ã¥É¥á¥â¥ê¥¤¥ó¥¿¥Õ¥§©`¥¹ **********/
.spm_rd_data (spm_rd_data), // Õi¤ß³ö¤·¥Ç©`¥¿
.spm_addr (spm_addr), // ¥¢¥É¥ì¥¹
.spm_as_ (spm_as_), // ¥¢¥É¥ì¥¹¥¹¥È¥í©`¥Ö
.spm_rw (spm_rw), // Õi¤ß£¯ø¤
.spm_wr_data (spm_wr_data), // ø¤Þz¤ß¥Ç©`¥¿
/********** ¥Ð¥¹¥¤¥ó¥¿¥Õ¥§©`¥¹ **********/
.bus_rd_data (bus_rd_data), // Õi¤ß³ö¤·¥Ç©`¥¿
.bus_rdy_ (bus_rdy_), // ¥ì¥Ç¥£
.bus_grnt_ (bus_grnt_), // ¥Ð¥¹¥°¥é¥ó¥È
.bus_req_ (bus_req_), // ¥Ð¥¹¥ê¥¯¥¨¥¹¥È
.bus_addr (bus_addr), // ¥¢¥É¥ì¥¹
.bus_as_ (bus_as_), // ¥¢¥É¥ì¥¹¥¹¥È¥í©`¥Ö
.bus_rw (bus_rw), // Õi¤ß£¯ø¤
.bus_wr_data (bus_wr_data) // ø¤Þz¤ß¥Ç©`¥¿
);
/********** IF¥¹¥Æ©`¥¸¥Ñ¥¤¥×¥é¥¤¥ó¥ì¥¸¥¹¥¿ **********/
if_reg if_reg (
/********** ¥¯¥í¥Ã¥¯ & ¥ê¥»¥Ã¥È **********/
.clk (clk), // ¥¯¥í¥Ã¥¯
.reset (reset), // ·ÇͬÆڥꥻ¥Ã¥È
/********** ¥Õ¥§¥Ã¥Á¥Ç©`¥¿ **********/
.insn (insn), // ¥Õ¥§¥Ã¥Á¤·¤¿ÃüÁî
/********** ¥Ñ¥¤¥×¥é¥¤¥óÖÆÓùÐźŠ**********/
.stall (stall), // ¥¹¥È©`¥ë
.flush (flush), // ¥Õ¥é¥Ã¥·¥å
.new_pc (new_pc), // Ф·¤¤¥×¥í¥°¥é¥à¥«¥¦¥ó¥¿
.br_taken (br_taken), // ·Ö᪤γÉÁ¢
.br_addr (br_addr), // ·ÖáªÏÈ¥¢¥É¥ì¥¹
/********** IF/ID¥Ñ¥¤¥×¥é¥¤¥ó¥ì¥¸¥¹¥¿ **********/
.if_pc (if_pc), // ¥×¥í¥°¥é¥à¥«¥¦¥ó¥¿
.if_insn (if_insn), // ÃüÁî
.if_en (if_en) // ¥Ñ¥¤¥×¥é¥¤¥ó¥Ç©`¥¿¤ÎÓп
);
endmodule |
module mem_ctrl (
/********** EX/MEM¥Ñ¥¤¥×¥é¥¤¥ó¥ì¥¸¥¹¥¿ **********/
input wire ex_en, // ¥Ñ¥¤¥×¥é¥¤¥ó¥Ç©`¥¿¤ÎÓп
input wire [`MemOpBus] ex_mem_op, // ¥á¥â¥ê¥ª¥Ú¥ì©`¥·¥ç¥ó
input wire [`WordDataBus] ex_mem_wr_data, // ¥á¥â¥êø¤Þz¤ß¥Ç©`¥¿
input wire [`WordDataBus] ex_out, // IÀí½Y¹û
/********** ¥á¥â¥ê¥¢¥¯¥»¥¹¥¤¥ó¥¿¥Õ¥§©`¥¹ **********/
input wire [`WordDataBus] rd_data, // Õi¤ß³ö¤·¥Ç©`¥¿
output wire [`WordAddrBus] addr, // ¥¢¥É¥ì¥¹
output reg as_, // ¥¢¥É¥ì¥¹Óп
output reg rw, // Õi¤ß£¯ø¤
output wire [`WordDataBus] wr_data, // ø¤Þz¤ß¥Ç©`¥¿
/********** ¥á¥â¥ê¥¢¥¯¥»¥¹½Y¹û **********/
output reg [`WordDataBus] out , // ¥á¥â¥ê¥¢¥¯¥»¥¹½Y¹û
output reg miss_align // ¥ß¥¹¥¢¥é¥¤¥ó
);
/********** ÄÚ²¿ÐźŠ**********/
wire [`ByteOffsetBus] offset; // ¥ª¥Õ¥»¥Ã¥È
/********** ³öÁ¦¤Î¥¢¥µ¥¤¥ó **********/
assign wr_data = ex_mem_wr_data; // ø¤Þz¤ß¥Ç©`¥¿
assign addr = ex_out[`WordAddrLoc]; // ¥¢¥É¥ì¥¹
assign offset = ex_out[`ByteOffsetLoc]; // ¥ª¥Õ¥»¥Ã¥È
/********** ¥á¥â¥ê¥¢¥¯¥»¥¹¤ÎÖÆÓù **********/
always @(*) begin
/* ¥Ç¥Õ¥©¥ë¥È */
miss_align = `DISABLE;
out = `WORD_DATA_W'h0;
as_ = `DISABLE_;
rw = `READ;
/* ¥á¥â¥ê¥¢¥¯¥»¥¹ */
if (ex_en == `ENABLE) begin
case (ex_mem_op)
`MEM_OP_LDW : begin // ¥ï©`¥ÉÕi¤ß³ö¤·
/* ¥Ð¥¤¥È¥ª¥Õ¥»¥Ã¥È¤Î¥Á¥§¥Ã¥¯ */
if (offset == `BYTE_OFFSET_WORD) begin // ¥¢¥é¥¤¥ó
out = rd_data;
as_ = `ENABLE_;
end else begin // ¥ß¥¹¥¢¥é¥¤¥ó
miss_align = `ENABLE;
end
end
`MEM_OP_STW : begin // ¥ï©`¥Éø¤Þz¤ß
/* ¥Ð¥¤¥È¥ª¥Õ¥»¥Ã¥È¤Î¥Á¥§¥Ã¥¯ */
if (offset == `BYTE_OFFSET_WORD) begin // ¥¢¥é¥¤¥ó
rw = `WRITE;
as_ = `ENABLE_;
end else begin // ¥ß¥¹¥¢¥é¥¤¥ó
miss_align = `ENABLE;
end
end
default : begin // ¥á¥â¥ê¥¢¥¯¥»¥¹¤Ê¤·
out = ex_out;
end
endcase
end
end
endmodule |
module alu (
input wire [`WordDataBus] in_0, // ÈëÁ¦ 0
input wire [`WordDataBus] in_1, // ÈëÁ¦ 1
input wire [`AluOpBus] op, // ¥ª¥Ú¥ì©`¥·¥ç¥ó
output reg [`WordDataBus] out, // ³öÁ¦
output reg of // ¥ª©`¥Ð¥Õ¥í©`
);
/********** ·ûºÅ¸¶¤Èë³öÁ¦ÐźŠ**********/
wire signed [`WordDataBus] s_in_0 = $signed(in_0); // ·ûºÅ¸¶¤ÈëÁ¦ 0
wire signed [`WordDataBus] s_in_1 = $signed(in_1); // ·ûºÅ¸¶¤ÈëÁ¦ 1
wire signed [`WordDataBus] s_out = $signed(out); // ·ûºÅ¸¶¤³öÁ¦
/********** ËãÐgÕÀíÑÝËã **********/
always @(*) begin
case (op)
`ALU_OP_AND : begin // ÕÀí·e£¨AND£©
out = in_0 & in_1;
end
`ALU_OP_OR : begin // ÕÀíºÍ£¨OR£©
out = in_0 | in_1;
end
`ALU_OP_XOR : begin // ÅÅËûµÄÕÀíºÍ£¨XOR£©
out = in_0 ^ in_1;
end
`ALU_OP_ADDS : begin // ·ûºÅ¸¶¤¼ÓËã
out = in_0 + in_1;
end
`ALU_OP_ADDU : begin // ·ûºÅ¤Ê¤·¼ÓËã
out = in_0 + in_1;
end
`ALU_OP_SUBS : begin // ·ûºÅ¸¶¤pËã
out = in_0 - in_1;
end
`ALU_OP_SUBU : begin // ·ûºÅ¤Ê¤·pËã
out = in_0 - in_1;
end
`ALU_OP_SHRL : begin // ÕÀíÓÒ¥·¥Õ¥È
out = in_0 >> in_1[`ShAmountLoc];
end
`ALU_OP_SHLL : begin // ÕÀí×ó¥·¥Õ¥È
out = in_0 << in_1[`ShAmountLoc];
end
default : begin // ¥Ç¥Õ¥©¥ë¥È (No Operation)
out = in_0;
end
endcase
end
/********** ¥ª©`¥Ð¥Õ¥í©`¥Á¥§¥Ã¥¯ **********/
always @(*) begin
case (op)
`ALU_OP_ADDS : begin // ¼ÓË㥪©`¥Ð¥Õ¥í©`¤Î¥Á¥§¥Ã¥¯
if (((s_in_0 > 0) && (s_in_1 > 0) && (s_out < 0)) ||
((s_in_0 < 0) && (s_in_1 < 0) && (s_out > 0))) begin
of = `ENABLE;
end else begin
of = `DISABLE;
end
end
`ALU_OP_SUBS : begin // pË㥪©`¥Ð¥Õ¥í©`¤Î¥Á¥§¥Ã¥¯
if (((s_in_0 < 0) && (s_in_1 > 0) && (s_out > 0)) ||
((s_in_0 > 0) && (s_in_1 < 0) && (s_out < 0))) begin
of = `ENABLE;
end else begin
of = `DISABLE;
end
end
default : begin // ¥Ç¥Õ¥©¥ë¥È
of = `DISABLE;
end
endcase
end
endmodule |
module mem_stage (
/********** ¥¯¥í¥Ã¥¯ & ¥ê¥»¥Ã¥È **********/
input wire clk, // ¥¯¥í¥Ã¥¯
input wire reset, // ·ÇͬÆڥꥻ¥Ã¥È
/********** ¥Ñ¥¤¥×¥é¥¤¥óÖÆÓùÐźŠ**********/
input wire stall, // ¥¹¥È©`¥ë
input wire flush, // ¥Õ¥é¥Ã¥·¥å
output wire busy, // ¥Ó¥¸©`ÐźÅ
/********** ¥Õ¥©¥ï©`¥Ç¥£¥ó¥° **********/
output wire [`WordDataBus] fwd_data, // ¥Õ¥©¥ï©`¥Ç¥£¥ó¥°¥Ç©`¥¿
/********** SPM¥¤¥ó¥¿¥Õ¥§©`¥¹ **********/
input wire [`WordDataBus] spm_rd_data, // Õi¤ß³ö¤·¥Ç©`¥¿
output wire [`WordAddrBus] spm_addr, // ¥¢¥É¥ì¥¹
output wire spm_as_, // ¥¢¥É¥ì¥¹¥¹¥È¥í©`¥Ö
output wire spm_rw, // Õi¤ß£¯ø¤
output wire [`WordDataBus] spm_wr_data, // ø¤Þz¤ß¥Ç©`¥¿
/********** ¥Ð¥¹¥¤¥ó¥¿¥Õ¥§©`¥¹ **********/
input wire [`WordDataBus] bus_rd_data, // Õi¤ß³ö¤·¥Ç©`¥¿
input wire bus_rdy_, // ¥ì¥Ç¥£
input wire bus_grnt_, // ¥Ð¥¹¥°¥é¥ó¥È
output wire bus_req_, // ¥Ð¥¹¥ê¥¯¥¨¥¹¥È
output wire [`WordAddrBus] bus_addr, // ¥¢¥É¥ì¥¹
output wire bus_as_, // ¥¢¥É¥ì¥¹¥¹¥È¥í©`¥Ö
output wire bus_rw, // Õi¤ß£¯ø¤
output wire [`WordDataBus] bus_wr_data, // ø¤Þz¤ß¥Ç©`¥¿
/********** EX/MEM¥Ñ¥¤¥×¥é¥¤¥ó¥ì¥¸¥¹¥¿ **********/
input wire [`WordAddrBus] ex_pc, // ¥×¥í¥°¥é¥à¥«¥¦¥ó¥¿
input wire ex_en, // ¥Ñ¥¤¥×¥é¥¤¥ó¥Ç©`¥¿¤ÎÓп
input wire ex_br_flag, // ·Ö᪥ե饰
input wire [`MemOpBus] ex_mem_op, // ¥á¥â¥ê¥ª¥Ú¥ì©`¥·¥ç¥ó
input wire [`WordDataBus] ex_mem_wr_data, // ¥á¥â¥êø¤Þz¤ß¥Ç©`¥¿
input wire [`CtrlOpBus] ex_ctrl_op, // ÖÆÓù¥ì¥¸¥¹¥¿¥ª¥Ú¥ì©`¥·¥ç¥ó
input wire [`RegAddrBus] ex_dst_addr, // øÓå쥸¥¹¥¿ø¤Þz¤ß¥¢¥É¥ì¥¹
input wire ex_gpr_we_, // øÓå쥸¥¹¥¿ø¤Þz¤ßÓп
input wire [`IsaExpBus] ex_exp_code, // ÀýÍ⥳©`¥É
input wire [`WordDataBus] ex_out, // IÀí½Y¹û
/********** MEM/WB¥Ñ¥¤¥×¥é¥¤¥ó¥ì¥¸¥¹¥¿ **********/
output wire [`WordAddrBus] mem_pc, // ¥×¥í¥°¥é¥ó¥«¥¦¥ó¥¿
output wire mem_en, // ¥Ñ¥¤¥×¥é¥¤¥ó¥Ç©`¥¿¤ÎÓп
output wire mem_br_flag, // ·Ö᪥ե饰
output wire [`CtrlOpBus] mem_ctrl_op, // ÖÆÓù¥ì¥¸¥¹¥¿¥ª¥Ú¥ì©`¥·¥ç¥ó
output wire [`RegAddrBus] mem_dst_addr, // øÓå쥸¥¹¥¿ø¤Þz¤ß¥¢¥É¥ì¥¹
output wire mem_gpr_we_, // øÓå쥸¥¹¥¿ø¤Þz¤ßÓп
output wire [`IsaExpBus] mem_exp_code, // ÀýÍ⥳©`¥É
output wire [`WordDataBus] mem_out // IÀí½Y¹û
);
/********** ÄÚ²¿ÐźŠ**********/
wire [`WordDataBus] rd_data; // Õi¤ß³ö¤·¥Ç©`¥¿
wire [`WordAddrBus] addr; // ¥¢¥É¥ì¥¹
wire as_; // ¥¢¥É¥ì¥¹Óп
wire rw; // Õi¤ß£¯ø¤
wire [`WordDataBus] wr_data; // ø¤Þz¤ß¥Ç©`¥¿
wire [`WordDataBus] out; // ¥á¥â¥ê¥¢¥¯¥»¥¹½Y¹û
wire miss_align; // ¥ß¥¹¥¢¥é¥¤¥ó
/********** ½Y¹û¤Î¥Õ¥©¥ï©`¥Ç¥£¥ó¥° **********/
assign fwd_data = out;
/********** ¥á¥â¥ê¥¢¥¯¥»¥¹ÖÆÓù¥æ¥Ë¥Ã¥È **********/
mem_ctrl mem_ctrl (
/********** EX/MEM¥Ñ¥¤¥×¥é¥¤¥ó¥ì¥¸¥¹¥¿ **********/
.ex_en (ex_en), // ¥Ñ¥¤¥×¥é¥¤¥ó¥Ç©`¥¿¤ÎÓп
.ex_mem_op (ex_mem_op), // ¥á¥â¥ê¥ª¥Ú¥ì©`¥·¥ç¥ó
.ex_mem_wr_data (ex_mem_wr_data), // ¥á¥â¥êø¤Þz¤ß¥Ç©`¥¿
.ex_out (ex_out), // IÀí½Y¹û
/********** ¥á¥â¥ê¥¢¥¯¥»¥¹¥¤¥ó¥¿¥Õ¥§©`¥¹ **********/
.rd_data (rd_data), // Õi¤ß³ö¤·¥Ç©`¥¿
.addr (addr), // ¥¢¥É¥ì¥¹
.as_ (as_), // ¥¢¥É¥ì¥¹Óп
.rw (rw), // Õi¤ß£¯ø¤
.wr_data (wr_data), // ø¤Þz¤ß¥Ç©`¥¿
/********** ¥á¥â¥ê¥¢¥¯¥»¥¹½Y¹û **********/
.out (out), // ¥á¥â¥ê¥¢¥¯¥»¥¹½Y¹û
.miss_align (miss_align) // ¥ß¥¹¥¢¥é¥¤¥ó
);
/********** ¥Ð¥¹¥¤¥ó¥¿¥Õ¥§©`¥¹ **********/
bus_if bus_if (
/********** ¥¯¥í¥Ã¥¯ & ¥ê¥»¥Ã¥È **********/
.clk (clk), // ¥¯¥í¥Ã¥¯
.reset (reset), // ·ÇͬÆڥꥻ¥Ã¥È
/********** ¥Ñ¥¤¥×¥é¥¤¥óÖÆÓùÐźŠ**********/
.stall (stall), // ¥¹¥È©`¥ë
.flush (flush), // ¥Õ¥é¥Ã¥·¥åÐźÅ
.busy (busy), // ¥Ó¥¸©`ÐźÅ
/********** CPU¥¤¥ó¥¿¥Õ¥§©`¥¹ **********/
.addr (addr), // ¥¢¥É¥ì¥¹
.as_ (as_), // ¥¢¥É¥ì¥¹Óп
.rw (rw), // Õi¤ß£¯ø¤
.wr_data (wr_data), // ø¤Þz¤ß¥Ç©`¥¿
.rd_data (rd_data), // Õi¤ß³ö¤·¥Ç©`¥¿
/********** ¥¹¥¯¥é¥Ã¥Á¥Ñ¥Ã¥É¥á¥â¥ê¥¤¥ó¥¿¥Õ¥§©`¥¹ **********/
.spm_rd_data (spm_rd_data), // Õi¤ß³ö¤·¥Ç©`¥¿
.spm_addr (spm_addr), // ¥¢¥É¥ì¥¹
.spm_as_ (spm_as_), // ¥¢¥É¥ì¥¹¥¹¥È¥í©`¥Ö
.spm_rw (spm_rw), // Õi¤ß£¯ø¤
.spm_wr_data (spm_wr_data), // ø¤Þz¤ß¥Ç©`¥¿
/********** ¥Ð¥¹¥¤¥ó¥¿¥Õ¥§©`¥¹ **********/
.bus_rd_data (bus_rd_data), // Õi¤ß³ö¤·¥Ç©`¥¿
.bus_rdy_ (bus_rdy_), // ¥ì¥Ç¥£
.bus_grnt_ (bus_grnt_), // ¥Ð¥¹¥°¥é¥ó¥È
.bus_req_ (bus_req_), // ¥Ð¥¹¥ê¥¯¥¨¥¹¥È
.bus_addr (bus_addr), // ¥¢¥É¥ì¥¹
.bus_as_ (bus_as_), // ¥¢¥É¥ì¥¹¥¹¥È¥í©`¥Ö
.bus_rw (bus_rw), // Õi¤ß£¯ø¤
.bus_wr_data (bus_wr_data) // ø¤Þz¤ß¥Ç©`¥¿
);
/********** MEM¥¹¥Æ©`¥¸¥Ñ¥¤¥×¥é¥¤¥ó¥ì¥¸¥¹¥¿ **********/
mem_reg mem_reg (
/********** ¥¯¥í¥Ã¥¯ & ¥ê¥»¥Ã¥È **********/
.clk (clk), // ¥¯¥í¥Ã¥¯
.reset (reset), // ·ÇͬÆڥꥻ¥Ã¥È
/********** ¥á¥â¥ê¥¢¥¯¥»¥¹½Y¹û **********/
.out (out), // ½Y¹û
.miss_align (miss_align), // ¥ß¥¹¥¢¥é¥¤¥ó
/********** ¥Ñ¥¤¥×¥é¥¤¥óÖÆÓùÐźŠ**********/
.stall (stall), // ¥¹¥È©`¥ë
.flush (flush), // ¥Õ¥é¥Ã¥·¥å
/********** EX/MEM¥Ñ¥¤¥×¥é¥¤¥ó¥ì¥¸¥¹¥¿ **********/
.ex_pc (ex_pc), // ¥×¥í¥°¥é¥ó¥«¥¦¥ó¥¿
.ex_en (ex_en), // ¥Ñ¥¤¥×¥é¥¤¥ó¥Ç©`¥¿¤ÎÓп
.ex_br_flag (ex_br_flag), // ·Ö᪥ե饰
.ex_ctrl_op (ex_ctrl_op), // ÖÆÓù¥ì¥¸¥¹¥¿¥ª¥Ú¥ì©`¥·¥ç¥ó
.ex_dst_addr (ex_dst_addr), // øÓå쥸¥¹¥¿ø¤Þz¤ß¥¢¥É¥ì¥¹
.ex_gpr_we_ (ex_gpr_we_), // øÓå쥸¥¹¥¿ø¤Þz¤ßÓп
.ex_exp_code (ex_exp_code), // ÀýÍ⥳©`¥É
/********** MEM/WB¥Ñ¥¤¥×¥é¥¤¥ó¥ì¥¸¥¹¥¿ **********/
.mem_pc (mem_pc), // ¥×¥í¥°¥é¥ó¥«¥¦¥ó¥¿
.mem_en (mem_en), // ¥Ñ¥¤¥×¥é¥¤¥ó¥Ç©`¥¿¤ÎÓп
.mem_br_flag (mem_br_flag), // ·Ö᪥ե饰
.mem_ctrl_op (mem_ctrl_op), // ÖÆÓù¥ì¥¸¥¹¥¿¥ª¥Ú¥ì©`¥·¥ç¥ó
.mem_dst_addr (mem_dst_addr), // øÓå쥸¥¹¥¿ø¤Þz¤ß¥¢¥É¥ì¥¹
.mem_gpr_we_ (mem_gpr_we_), // øÓå쥸¥¹¥¿ø¤Þz¤ßÓп
.mem_exp_code (mem_exp_code), // ÀýÍ⥳©`¥É
.mem_out (mem_out) // IÀí½Y¹û
);
endmodule |
module pdp1_main_ram_mon (
address,
clock,
data,
wren,
q);
input [11:0] address;
input clock;
input [17:0] data;
input wren;
output [17:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [17:0] sub_wire0;
wire [17:0] q = sub_wire0[17:0];
altsyncram altsyncram_component (
.address_a (address),
.clock0 (clock),
.data_a (data),
.wren_a (wren),
.q_a (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.address_b (1'b1),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_b (1'b1),
.eccstatus (),
.q_b (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_b (1'b0));
defparam
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.intended_device_family = "Cyclone V",
altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 4096,
altsyncram_component.operation_mode = "SINGLE_PORT",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_reg_a = "CLOCK0",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.read_during_write_mode_port_a = "NEW_DATA_NO_NBE_READ",
altsyncram_component.widthad_a = 12,
altsyncram_component.width_a = 18,
altsyncram_component.width_byteena_a = 1;
endmodule |
module BRAM_TEST (
address,
clock,
data,
wren,
q);
input [12:0] address;
input clock;
input [7:0] data;
input wren;
output [7:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
endmodule |
module linebuf (
address_a,
address_b,
clock,
data_a,
data_b,
wren_a,
wren_b,
q_a,
q_b);
input [13:0] address_a;
input [13:0] address_b;
input clock;
input [7:0] data_a;
input [7:0] data_b;
input wren_a;
input wren_b;
output [7:0] q_a;
output [7:0] q_b;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
tri0 wren_a;
tri0 wren_b;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [7:0] sub_wire0;
wire [7:0] sub_wire1;
wire [7:0] q_a = sub_wire0[7:0];
wire [7:0] q_b = sub_wire1[7:0];
altsyncram altsyncram_component (
.address_a (address_a),
.address_b (address_b),
.clock0 (clock),
.data_a (data_a),
.data_b (data_b),
.wren_a (wren_a),
.wren_b (wren_b),
.q_a (sub_wire0),
.q_b (sub_wire1),
.aclr0 (1'b0),
.aclr1 (1'b0),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.eccstatus (),
.rden_a (1'b1),
.rden_b (1'b1));
defparam
altsyncram_component.address_reg_b = "CLOCK0",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_input_b = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.clock_enable_output_b = "BYPASS",
altsyncram_component.indata_reg_b = "CLOCK0",
altsyncram_component.intended_device_family = "Cyclone V",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 16384,
altsyncram_component.numwords_b = 16384,
altsyncram_component.operation_mode = "BIDIR_DUAL_PORT",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_aclr_b = "NONE",
altsyncram_component.outdata_reg_a = "UNREGISTERED",
altsyncram_component.outdata_reg_b = "UNREGISTERED",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE",
altsyncram_component.read_during_write_mode_port_a = "NEW_DATA_NO_NBE_READ",
altsyncram_component.read_during_write_mode_port_b = "NEW_DATA_NO_NBE_READ",
altsyncram_component.widthad_a = 14,
altsyncram_component.widthad_b = 14,
altsyncram_component.width_a = 8,
altsyncram_component.width_b = 8,
altsyncram_component.width_byteena_a = 1,
altsyncram_component.width_byteena_b = 1,
altsyncram_component.wrcontrol_wraddress_reg_b = "CLOCK0";
endmodule |
module pll (
input wire refclk, // refclk.clk
input wire rst, // reset.reset
output wire outclk_0, // outclk0.clk
output wire outclk_1, // outclk1.clk
output wire outclk_2, // outclk2.clk
output wire locked // locked.export
);
pll_0002 pll_inst (
.refclk (refclk), // refclk.clk
.rst (rst), // reset.reset
.outclk_0 (outclk_0), // outclk0.clk
.outclk_1 (outclk_1), // outclk1.clk
.outclk_2 (outclk_2), // outclk2.clk
.locked (locked) // locked.export
);
endmodule |
module RAM_TESTER (
address,
clock,
data,
wren,
q);
input [11:0] address;
input clock;
input [17:0] data;
input wren;
output [17:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [17:0] sub_wire0;
wire [17:0] q = sub_wire0[17:0];
altsyncram altsyncram_component (
.address_a (address),
.clock0 (clock),
.data_a (data),
.wren_a (wren),
.q_a (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.address_b (1'b1),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_b (1'b1),
.eccstatus (),
.q_b (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_b (1'b0));
defparam
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.intended_device_family = "Cyclone V",
altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=YES,INSTANCE_NAME=RAM",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 4096,
altsyncram_component.operation_mode = "SINGLE_PORT",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_reg_a = "UNREGISTERED",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.read_during_write_mode_port_a = "NEW_DATA_NO_NBE_READ",
altsyncram_component.widthad_a = 12,
altsyncram_component.width_a = 18,
altsyncram_component.width_byteena_a = 1;
endmodule |
module serial_fifo (
aclr,
data,
rdclk,
rdreq,
wrclk,
wrreq,
q,
rdempty,
wrfull);
input aclr;
input [7:0] data;
input rdclk;
input rdreq;
input wrclk;
input wrreq;
output [7:0] q;
output rdempty;
output wrfull;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [7:0] sub_wire0;
wire sub_wire1;
wire sub_wire2;
wire [7:0] q = sub_wire0[7:0];
wire rdempty = sub_wire1;
wire wrfull = sub_wire2;
dcfifo dcfifo_component (
.aclr (aclr),
.data (data),
.rdclk (rdclk),
.rdreq (rdreq),
.wrclk (wrclk),
.wrreq (wrreq),
.q (sub_wire0),
.rdempty (sub_wire1),
.wrfull (sub_wire2),
.eccstatus (),
.rdfull (),
.rdusedw (),
.wrempty (),
.wrusedw ());
defparam
dcfifo_component.intended_device_family = "Cyclone V",
dcfifo_component.lpm_numwords = 256,
dcfifo_component.lpm_showahead = "ON",
dcfifo_component.lpm_type = "dcfifo",
dcfifo_component.lpm_width = 8,
dcfifo_component.lpm_widthu = 8,
dcfifo_component.overflow_checking = "ON",
dcfifo_component.rdsync_delaypipe = 5,
dcfifo_component.read_aclr_synch = "OFF",
dcfifo_component.underflow_checking = "ON",
dcfifo_component.use_eab = "ON",
dcfifo_component.write_aclr_synch = "OFF",
dcfifo_component.wrsync_delaypipe = 5;
endmodule |
module pdp1_vga_rowbuffer (
data,
rdaddress,
rdclock,
wraddress,
wrclock,
wren,
q);
input [7:0] data;
input [12:0] rdaddress;
input rdclock;
input [12:0] wraddress;
input wrclock;
input wren;
output [7:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 wrclock;
tri0 wren;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [7:0] sub_wire0;
wire [7:0] q = sub_wire0[7:0];
altsyncram altsyncram_component (
.address_a (wraddress),
.address_b (rdaddress),
.clock0 (wrclock),
.clock1 (rdclock),
.data_a (data),
.wren_a (wren),
.q_b (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_b ({8{1'b1}}),
.eccstatus (),
.q_a (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_b (1'b0));
defparam
altsyncram_component.address_aclr_b = "NONE",
altsyncram_component.address_reg_b = "CLOCK1",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_input_b = "BYPASS",
altsyncram_component.clock_enable_output_b = "BYPASS",
altsyncram_component.intended_device_family = "Cyclone V",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 8192,
altsyncram_component.numwords_b = 8192,
altsyncram_component.operation_mode = "DUAL_PORT",
altsyncram_component.outdata_aclr_b = "NONE",
altsyncram_component.outdata_reg_b = "UNREGISTERED",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.widthad_a = 13,
altsyncram_component.widthad_b = 13,
altsyncram_component.width_a = 8,
altsyncram_component.width_b = 8,
altsyncram_component.width_byteena_a = 1;
endmodule |
module spram (
address,
clock,
data,
wren,
q);
input [7:0] address;
input clock;
input [7:0] data;
input wren;
output [7:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [7:0] sub_wire0;
wire [7:0] q = sub_wire0[7:0];
altsyncram altsyncram_component (
.address_a (address),
.clock0 (clock),
.data_a (data),
.wren_a (wren),
.q_a (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.address_b (1'b1),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_b (1'b1),
.eccstatus (),
.q_b (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_b (1'b0));
defparam
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.intended_device_family = "Cyclone V",
altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 256,
altsyncram_component.operation_mode = "SINGLE_PORT",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_reg_a = "UNREGISTERED",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.read_during_write_mode_port_a = "NEW_DATA_NO_NBE_READ",
altsyncram_component.widthad_a = 8,
altsyncram_component.width_a = 8,
altsyncram_component.width_byteena_a = 1;
endmodule |
module RAM_TESTER (
address,
clock,
data,
wren,
q);
input [11:0] address;
input clock;
input [17:0] data;
input wren;
output [17:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
endmodule |
module BRAM_TEST (
address,
clock,
data,
wren,
q);
input [12:0] address;
input clock;
input [7:0] data;
input wren;
output [7:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [7:0] sub_wire0;
wire [7:0] q = sub_wire0[7:0];
altsyncram altsyncram_component (
.address_a (address),
.clock0 (clock),
.data_a (data),
.wren_a (wren),
.q_a (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.address_b (1'b1),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_b (1'b1),
.eccstatus (),
.q_b (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_b (1'b0));
defparam
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.intended_device_family = "Cyclone V",
altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=YES,INSTANCE_NAME=VIDE",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 8192,
altsyncram_component.operation_mode = "SINGLE_PORT",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_reg_a = "CLOCK0",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.read_during_write_mode_port_a = "DONT_CARE",
altsyncram_component.widthad_a = 13,
altsyncram_component.width_a = 8,
altsyncram_component.width_byteena_a = 1;
endmodule |
module pdp1_main_ram_mon (
address,
clock,
data,
wren,
q);
input [11:0] address;
input clock;
input [17:0] data;
input wren;
output [17:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
endmodule |
module serial_fifo (
aclr,
data,
rdclk,
rdreq,
wrclk,
wrreq,
q,
rdempty,
wrfull);
input aclr;
input [7:0] data;
input rdclk;
input rdreq;
input wrclk;
input wrreq;
output [7:0] q;
output rdempty;
output wrfull;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
endmodule |
module Multipler (
output wire [20:0] result, // result.result
input wire [9:0] dataa_0, // dataa_0.dataa_0
input wire [9:0] datab_0, // datab_0.datab_0
input wire clock0 // clock0.clock0
);
Multipler_0002 multipler_inst (
.result (result), // result.result
.dataa_0 (dataa_0), // dataa_0.dataa_0
.datab_0 (datab_0), // datab_0.datab_0
.clock0 (clock0) // clock0.clock0
);
endmodule |
module linebuf (
address_a,
address_b,
clock,
data_a,
data_b,
wren_a,
wren_b,
q_a,
q_b);
input [13:0] address_a;
input [13:0] address_b;
input clock;
input [7:0] data_a;
input [7:0] data_b;
input wren_a;
input wren_b;
output [7:0] q_a;
output [7:0] q_b;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
tri0 wren_a;
tri0 wren_b;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
endmodule |
module data_fifo (
aclr,
data,
rdclk,
rdreq,
wrclk,
wrreq,
q,
rdempty,
wrfull);
input aclr;
input [31:0] data;
input rdclk;
input rdreq;
input wrclk;
input wrreq;
output [7:0] q;
output rdempty;
output wrfull;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
endmodule |
module taperam (
data,
rdaddress,
rdclock,
wraddress,
wrclock,
wren,
q);
input [31:0] data;
input [11:0] rdaddress;
input rdclock;
input [11:0] wraddress;
input wrclock;
input wren;
output [31:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 wrclock;
tri0 wren;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
endmodule |
module pdp1_vga_rowbuffer (
data,
rdaddress,
rdclock,
wraddress,
wrclock,
wren,
q);
input [7:0] data;
input [12:0] rdaddress;
input rdclock;
input [12:0] wraddress;
input wrclock;
input wren;
output [7:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 wrclock;
tri0 wren;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
endmodule |
module fifo_video (
data,
rdclk,
rdreq,
wrclk,
wrreq,
q,
rdempty,
rdfull,
rdusedw,
wrfull);
input [21:0] data;
input rdclk;
input rdreq;
input wrclk;
input wrreq;
output [21:0] q;
output rdempty;
output rdfull;
output [8:0] rdusedw;
output wrfull;
wire [21:0] sub_wire0;
wire sub_wire1;
wire sub_wire2;
wire [8:0] sub_wire3;
wire sub_wire4;
wire [21:0] q = sub_wire0[21:0];
wire rdempty = sub_wire1;
wire rdfull = sub_wire2;
wire [8:0] rdusedw = sub_wire3[8:0];
wire wrfull = sub_wire4;
dcfifo dcfifo_component (
.data (data),
.rdclk (rdclk),
.rdreq (rdreq),
.wrclk (wrclk),
.wrreq (wrreq),
.q (sub_wire0),
.rdempty (sub_wire1),
.rdfull (sub_wire2),
.rdusedw (sub_wire3),
.wrfull (sub_wire4),
.aclr (),
.eccstatus (),
.wrempty (),
.wrusedw ());
defparam
dcfifo_component.intended_device_family = "Cyclone V",
dcfifo_component.lpm_numwords = 512,
dcfifo_component.lpm_showahead = "ON",
dcfifo_component.lpm_type = "dcfifo",
dcfifo_component.lpm_width = 22,
dcfifo_component.lpm_widthu = 9,
dcfifo_component.overflow_checking = "ON",
dcfifo_component.rdsync_delaypipe = 8,
dcfifo_component.underflow_checking = "ON",
dcfifo_component.use_eab = "ON",
dcfifo_component.wrsync_delaypipe = 8;
endmodule |
module rendram (
address_a,
address_b,
clock,
data_a,
data_b,
wren_a,
wren_b,
q_a,
q_b);
input [9:0] address_a;
input [9:0] address_b;
input clock;
input [31:0] data_a;
input [31:0] data_b;
input wren_a;
input wren_b;
output [31:0] q_a;
output [31:0] q_b;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
tri0 wren_a;
tri0 wren_b;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
endmodule |
module BRAM_DUAL_PORT_CLOCK (
address_a,
address_b,
clock_a,
clock_b,
data_a,
data_b,
wren_a,
wren_b,
q_a,
q_b);
input [11:0] address_a;
input [11:0] address_b;
input clock_a;
input clock_b;
input [17:0] data_a;
input [17:0] data_b;
input wren_a;
input wren_b;
output [17:0] q_a;
output [17:0] q_b;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock_a;
tri0 wren_a;
tri0 wren_b;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
endmodule |
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