uid
int64 2
114k
| input
stringlengths 101
58.4k
| output
stringlengths 422
72.4k
| input_tokens
int64 24
31.2k
| output_tokens
int64 182
31.2k
|
|---|---|---|---|---|
498 |
Convert the following CUDA device assembly code to AMD device assembly:
```cudaasm
code for sm_80
Function : _Z23parallel_max_each_chunkPfS_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ;
I2F.U32.RP R4, c[0x0][0x0] ;
IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x0] ;
ISETP.NE.U32.AND P2, PT, RZ, c[0x0][0x0], PT ;
S2R R14, SR_TID.X ;
ULDC.64 UR6, c[0x0][0x118] ;
IADD3 R0, R0, c[0x0][0x170], RZ ;
IADD3 R0, R0, -0x1, RZ ;
MUFU.RCP R4, R4 ;
IADD3 R2, R4, 0xffffffe, RZ ;
F2I.FTZ.U32.TRUNC.NTZ R3, R2 ;
IMAD.MOV.U32 R2, RZ, RZ, RZ ;
IMAD.MOV R5, RZ, RZ, -R3 ;
IMAD R5, R5, c[0x0][0x0], RZ ;
IMAD.HI.U32 R3, R3, R5, R2 ;
IMAD.HI.U32 R5, R3, R0, RZ ;
IMAD.MOV R3, RZ, RZ, -R5 ;
IMAD R0, R3, c[0x0][0x0], R0 ;
ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x0], PT ;
@P0 IADD3 R0, R0, -c[0x0][0x0], RZ ;
@P0 IADD3 R5, R5, 0x1, RZ ;
ISETP.GE.U32.AND P1, PT, R0, c[0x0][0x0], PT ;
@P1 IADD3 R5, R5, 0x1, RZ ;
@!P2 LOP3.LUT R5, RZ, c[0x0][0x0], RZ, 0x33, !PT ;
ISETP.GE.AND P0, PT, R5, 0x1, PT ;
@!P0 BRA 0xc30 ;
IADD3 R0, R5.reuse, -0x1, RZ ;
IMAD.MOV.U32 R3, RZ, RZ, RZ ;
LOP3.LUT R2, R5.reuse, 0x3, RZ, 0xc0, !PT ;
ISETP.GE.U32.AND P0, PT, R0, 0x3, PT ;
IMAD R0, R5, R14, RZ ;
@!P0 BRA 0xb70 ;
IMAD.IADD R4, R5, 0x1, -R2 ;
IMAD.MOV.U32 R3, RZ, RZ, RZ ;
ISETP.GT.AND P0, PT, R4, RZ, PT ;
@!P0 BRA 0xa00 ;
ISETP.GT.AND P1, PT, R4, 0xc, PT ;
PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ;
@!P1 BRA 0x720 ;
PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ;
IMAD.IADD R9, R0, 0x1, R3 ;
IMAD.MOV.U32 R8, RZ, RZ, 0x4 ;
IADD3 R5, R9.reuse, 0x1, RZ ;
IADD3 R6, R9, 0x2, RZ ;
ISETP.GE.AND P2, PT, R5, c[0x0][0x170], PT ;
ISETP.GE.AND P3, PT, R9.reuse, c[0x0][0x170], PT ;
ISETP.GE.AND P4, PT, R6, c[0x0][0x170], PT ;
IMAD.WIDE R6, R9.reuse, R8, c[0x0][0x168] ;
IADD3 R5, R9, 0x3, RZ ;
ISETP.GE.AND P1, PT, R5, c[0x0][0x170], PT ;
@!P2 LDG.E R16, [R6.64+0x4] ;
@!P3 LDG.E R12, [R6.64] ;
@!P4 LDG.E R18, [R6.64+0x8] ;
@!P1 LDG.E R20, [R6.64+0xc] ;
IADD3 R11, R0, 0x4, R3 ;
IADD3 R10, R9.reuse, 0x5, RZ ;
IMAD.SHL.U32 R5, R9, 0x4, RZ ;
ISETP.GE.AND P6, PT, R11, c[0x0][0x170], PT ;
ISETP.GE.AND P5, PT, R10, c[0x0][0x170], PT ;
IADD3 R13, R9.reuse, 0x6, RZ ;
IADD3 R10, R9, 0x7, RZ ;
IADD3 R7, R0, 0x8, R3 ;
IADD3 R6, R9, 0x9, RZ ;
@!P2 STS [R5+0x4], R16 ;
ISETP.GE.AND P2, PT, R10, c[0x0][0x170], PT ;
@!P3 STS [R5], R12 ;
ISETP.GE.AND P3, PT, R13, c[0x0][0x170], PT ;
@!P4 STS [R5+0x8], R18 ;
ISETP.GE.AND P4, PT, R7, c[0x0][0x170], PT ;
IMAD.WIDE R10, R11, R8.reuse, c[0x0][0x168] ;
@!P1 STS [R5+0xc], R20 ;
ISETP.GE.AND P1, PT, R6, c[0x0][0x170], PT ;
IMAD.WIDE R6, R7, R8, c[0x0][0x168] ;
@!P6 LDG.E R22, [R10.64] ;
@!P5 LDG.E R12, [R10.64+0x4] ;
@!P3 LDG.E R16, [R10.64+0x8] ;
@!P2 LDG.E R24, [R10.64+0xc] ;
@!P4 LDG.E R26, [R6.64] ;
@!P1 LDG.E R18, [R6.64+0x4] ;
IADD3 R13, R9, 0xa, RZ ;
IADD3 R15, R9.reuse, 0xb, RZ ;
IADD3 R11, R0, 0xc, R3 ;
IADD3 R10, R9, 0xe, RZ ;
@!P6 STS [R5+0x10], R22 ;
ISETP.GE.AND P6, PT, R13, c[0x0][0x170], PT ;
IADD3 R13, R9, 0xd, RZ ;
@!P5 STS [R5+0x14], R12 ;
ISETP.GE.AND P5, PT, R15, c[0x0][0x170], PT ;
IADD3 R9, R9, 0xf, RZ ;
@!P3 STS [R5+0x18], R16 ;
ISETP.GE.AND P3, PT, R13, c[0x0][0x170], PT ;
@!P2 STS [R5+0x1c], R24 ;
ISETP.GE.AND P2, PT, R10, c[0x0][0x170], PT ;
@!P4 STS [R5+0x20], R26 ;
ISETP.GE.AND P4, PT, R11, c[0x0][0x170], PT ;
@!P1 STS [R5+0x24], R18 ;
ISETP.GE.AND P1, PT, R9, c[0x0][0x170], PT ;
IMAD.WIDE R8, R11, R8, c[0x0][0x168] ;
@!P6 LDG.E R10, [R6.64+0x8] ;
@!P5 LDG.E R12, [R6.64+0xc] ;
@!P4 LDG.E R16, [R8.64] ;
@!P3 LDG.E R20, [R8.64+0x4] ;
@!P2 LDG.E R22, [R8.64+0x8] ;
@!P1 LDG.E R24, [R8.64+0xc] ;
IADD3 R4, R4, -0x10, RZ ;
IADD3 R3, R3, 0x10, RZ ;
@!P6 STS [R5+0x28], R10 ;
@!P5 STS [R5+0x2c], R12 ;
@!P4 STS [R5+0x30], R16 ;
@!P3 STS [R5+0x34], R20 ;
@!P2 STS [R5+0x38], R22 ;
@!P1 STS [R5+0x3c], R24 ;
ISETP.GT.AND P1, PT, R4, 0xc, PT ;
@P1 BRA 0x280 ;
ISETP.GT.AND P1, PT, R4, 0x4, PT ;
@!P1 BRA 0x9e0 ;
IMAD.IADD R10, R0, 0x1, R3 ;
IMAD.MOV.U32 R11, RZ, RZ, 0x4 ;
ISETP.GE.AND P6, PT, R10.reuse, c[0x0][0x170], PT ;
IMAD.WIDE R6, R10, R11, c[0x0][0x168] ;
@!P6 LDG.E R5, [R6.64] ;
IADD3 R19, R3, 0x4, RZ ;
IMAD.SHL.U32 R18, R10.reuse, 0x4, RZ ;
IADD3 R3, R10.reuse, 0x1, RZ ;
IADD3 R8, R10, 0x2, RZ ;
IMAD.IADD R20, R0, 0x1, R19 ;
ISETP.GE.AND P5, PT, R3, c[0x0][0x170], PT ;
IADD3 R9, R10, 0x3, RZ ;
IADD3 R3, R20, 0x1, RZ ;
ISETP.GE.AND P4, PT, R8, c[0x0][0x170], PT ;
ISETP.GE.AND P1, PT, R3, c[0x0][0x170], PT ;
IADD3 R3, R20.reuse, 0x3, RZ ;
ISETP.GE.AND P3, PT, R9, c[0x0][0x170], PT ;
@!P5 LDG.E R10, [R6.64+0x4] ;
ISETP.GE.AND P2, PT, R20.reuse, c[0x0][0x170], PT ;
IADD3 R8, R20, 0x2, RZ ;
ISETP.GE.AND P0, PT, R8, c[0x0][0x170], PT ;
IMAD.WIDE R8, R20, R11, c[0x0][0x168] ;
@!P4 LDG.E R11, [R6.64+0x8] ;
@!P3 LDG.E R12, [R6.64+0xc] ;
@!P2 LDG.E R13, [R8.64] ;
@!P1 LDG.E R15, [R8.64+0x4] ;
@!P0 LDG.E R16, [R8.64+0x8] ;
@!P6 STS [R18], R5 ;
ISETP.GE.AND P6, PT, R3, c[0x0][0x170], PT ;
@!P6 LDG.E R17, [R8.64+0xc] ;
IMAD.SHL.U32 R20, R20, 0x4, RZ ;
@!P5 STS [R18+0x4], R10 ;
@!P4 STS [R18+0x8], R11 ;
@!P3 STS [R18+0xc], R12 ;
@!P2 STS [R20], R13 ;
@!P1 STS [R20+0x4], R15 ;
IADD3 R4, R4, -0x4, RZ ;
IADD3 R3, R19, 0x4, RZ ;
@!P0 STS [R20+0x8], R16 ;
PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ;
IADD3 R4, R4, -0x4, RZ ;
@!P6 STS [R20+0xc], R17 ;
ISETP.NE.OR P0, PT, R4, RZ, P0 ;
@!P0 BRA 0xb70 ;
IMAD.IADD R11, R0, 0x1, R3 ;
IADD3 R5, R11.reuse, 0x1, RZ ;
IADD3 R6, R11.reuse, 0x2, RZ ;
IADD3 R7, R11, 0x3, RZ ;
ISETP.GE.AND P1, PT, R5, c[0x0][0x170], PT ;
ISETP.GE.AND P2, PT, R6, c[0x0][0x170], PT ;
IMAD.MOV.U32 R6, RZ, RZ, 0x4 ;
ISETP.GE.AND P3, PT, R7, c[0x0][0x170], PT ;
ISETP.GE.AND P0, PT, R11.reuse, c[0x0][0x170], PT ;
IMAD.WIDE R6, R11, R6, c[0x0][0x168] ;
@!P1 LDG.E R8, [R6.64+0x4] ;
@!P2 LDG.E R9, [R6.64+0x8] ;
@!P3 LDG.E R10, [R6.64+0xc] ;
@!P0 LDG.E R5, [R6.64] ;
IMAD.SHL.U32 R11, R11, 0x4, RZ ;
IADD3 R4, R4, -0x4, RZ ;
IADD3 R3, R3, 0x4, RZ ;
@!P1 STS [R11+0x4], R8 ;
@!P2 STS [R11+0x8], R9 ;
@!P3 STS [R11+0xc], R10 ;
@!P0 STS [R11], R5 ;
ISETP.NE.AND P0, PT, R4, RZ, PT ;
@P0 BRA 0xa00 ;
ISETP.NE.AND P0, PT, R2, RZ, PT ;
@!P0 BRA 0xc30 ;
IMAD.IADD R7, R0, 0x1, R3 ;
ISETP.GE.AND P0, PT, R7, c[0x0][0x170], PT ;
@!P0 IMAD.MOV.U32 R4, RZ, RZ, 0x4 ;
@!P0 IMAD.WIDE R4, R7, R4, c[0x0][0x168] ;
@!P0 LDG.E R4, [R4.64] ;
IADD3 R2, R2, -0x1, RZ ;
IADD3 R3, R3, 0x1, RZ ;
@!P0 STS [R7.X4], R4 ;
ISETP.NE.AND P0, PT, R2, RZ, PT ;
@P0 BRA 0xb90 ;
S2R R13, SR_CTAID.X ;
ULDC.64 UR4, c[0x0][0x170] ;
BSSY B2, 0x1b00 ;
UIADD3 UR4, UR4, -UR5, URZ ;
IMAD.SHL.U32 R10, R14, 0x4, RZ ;
IMAD R12, R13, c[0x0][0x0], R14 ;
BAR.SYNC.DEFER_BLOCKING 0x0 ;
ISETP.GT.AND P0, PT, R12, UR4, PT ;
@P0 BRA 0x1ae0 ;
IADD3 R8, -R12, c[0x0][0x170], RZ ;
BSSY B1, 0x1ad0 ;
ISETP.GE.AND P0, PT, R8, c[0x0][0x174], PT ;
@!P0 BRA 0x1ac0 ;
IMAD.MOV R15, RZ, RZ, -R13 ;
IADD3 R11, -R12.reuse, 0x1, RZ ;
IMAD.MOV.U32 R4, RZ, RZ, RZ ;
IADD3 R9, R12.reuse, c[0x0][0x174], RZ ;
IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x174] ;
IADD3 R7, R12.reuse, 0x1, RZ ;
IMAD R2, R15, c[0x0][0x0], -R14 ;
IADD3 R6, R12.reuse, 0x2, RZ ;
IADD3 R5, R12, 0x3, RZ ;
ISETP.NE.AND P0, PT, R3, c[0x0][0x174], PT ;
IMAD.IADD R0, R9, 0x1, R4 ;
BSSY B0, 0x1a20 ;
IMNMX R15, R7, R0, !PT ;
IMAD.IADD R0, R12, 0x1, R3 ;
IMAD.IADD R15, R2, 0x1, R15 ;
@!P0 BRA 0xfc0 ;
LDS R15, [R0.X4+-0x4] ;
I2F.F64 R16, R3 ;
IMAD.MOV.U32 R22, RZ, RZ, 0x1 ;
IADD3 R26, R3, -0x1, RZ ;
BSSY B3, 0xfa0 ;
I2F.F64 R26, R26 ;
MUFU.RCP64H R23, R17 ;
DFMA R20, -R16, R22, 1 ;
DFMA R20, R20, R20, R20 ;
F2F.F64.F32 R24, R15 ;
DFMA R20, R22, R20, R22 ;
DFMA R22, -R16, R20, 1 ;
DFMA R24, R26, R18, R24 ;
DFMA R22, R20, R22, R20 ;
DMUL R18, R24, R22 ;
FSETP.GEU.AND P1, PT, |R25|, 6.5827683646048100446e-37, PT ;
DFMA R20, -R16, R18, R24 ;
DFMA R18, R22, R20, R18 ;
FFMA R20, RZ, R17, R19 ;
FSETP.GT.AND P0, PT, |R20|, 1.469367938527859385e-39, PT ;
@P0 BRA P1, 0xf90 ;
MOV R30, 0xf70 ;
CALL.REL.NOINC 0x1ce0 ;
IMAD.MOV.U32 R18, RZ, RZ, R20 ;
IMAD.MOV.U32 R19, RZ, RZ, R21 ;
BSYNC B3 ;
LDS R17, [R14.X4] ;
BRA 0x1a10 ;
IMAD.MOV.U32 R16, RZ, RZ, c[0x0][0x174] ;
ISETP.GE.AND P0, PT, R16, 0x1, PT ;
CS2R R16, SRZ ;
@!P0 BRA 0x1850 ;
LOP3.LUT P0, R19, R15.reuse, 0x3, RZ, 0xc0, !PT ;
BSSY B3, 0x1170 ;
IADD3 R16, R15, -0x1, RZ ;
IMAD.MOV.U32 R15, RZ, RZ, R12 ;
ISETP.GE.U32.AND P1, PT, R16, 0x3, PT ;
CS2R R16, SRZ ;
@!P0 BRA 0x1160 ;
LDS R18, [R12.X4] ;
ISETP.NE.AND P0, PT, R19, 0x1, PT ;
IMAD.MOV.U32 R15, RZ, RZ, R7 ;
F2F.F64.F32 R16, R18 ;
DADD R16, RZ, R16 ;
@!P0 BRA 0x1160 ;
ISETP.NE.AND P0, PT, R19, 0x2, PT ;
LDS R18, [R12.X4+0x4] ;
IMAD.MOV.U32 R15, RZ, RZ, R6 ;
@P0 LDS R20, [R12.X4+0x8] ;
@P0 IMAD.MOV.U32 R15, RZ, RZ, R5 ;
F2F.F64.F32 R18, R18 ;
@P0 F2F.F64.F32 R20, R20 ;
DADD R16, R16, R18 ;
@P0 DADD R16, R16, R20 ;
BSYNC B3 ;
BSSY B3, 0x1850 ;
@!P1 BRA 0x1840 ;
IMAD.IADD R18, R0, 0x1, -R15 ;
BSSY B4, 0x1560 ;
PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ;
LEA R24, R15, 0x8, 0x2 ;
ISETP.GT.AND P1, PT, R18, 0xc, PT ;
@!P1 BRA 0x1550 ;
PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ;
IADD3 R26, R0, -0xc, RZ ;
LDS R33, [R24+-0x8] ;
IADD3 R15, R15, 0x10, RZ ;
LDS R34, [R24+-0x4] ;
ISETP.GE.AND P1, PT, R15, R26, PT ;
LDS R35, [R24] ;
LDS R36, [R24+0x4] ;
LDS R31, [R24+0x8] ;
LDS R25, [R24+0xc] ;
LDS R27, [R24+0x10] ;
LDS R28, [R24+0x14] ;
LDS R29, [R24+0x18] ;
LDS R30, [R24+0x1c] ;
F2F.F64.F32 R22, R33 ;
LDS R32, [R24+0x20] ;
LDS R37, [R24+0x34] ;
F2F.F64.F32 R20, R34 ;
LDS R33, [R24+0x24] ;
F2F.F64.F32 R18, R35 ;
DADD R22, R22, R16 ;
LDS R34, [R24+0x28] ;
F2F.F64.F32 R16, R36 ;
DADD R20, R22, R20 ;
LDS R35, [R24+0x2c] ;
F2F.F64.F32 R22, R31 ;
DADD R18, R20, R18 ;
LDS R36, [R24+0x30] ;
F2F.F64.F32 R20, R25 ;
DADD R16, R18, R16 ;
IADD3 R24, R24, 0x40, RZ ;
F2F.F64.F32 R18, R27 ;
DADD R16, R16, R22 ;
F2F.F64.F32 R22, R28 ;
DADD R16, R16, R20 ;
F2F.F64.F32 R20, R29 ;
DADD R16, R16, R18 ;
F2F.F64.F32 R30, R30 ;
DADD R16, R16, R22 ;
F2F.F64.F32 R18, R32 ;
DADD R16, R16, R20 ;
F2F.F64.F32 R20, R33 ;
DADD R16, R16, R30 ;
F2F.F64.F32 R22, R34 ;
DADD R16, R16, R18 ;
F2F.F64.F32 R18, R35 ;
DADD R16, R16, R20 ;
F2F.F64.F32 R20, R36 ;
DADD R16, R16, R22 ;
F2F.F64.F32 R22, R37 ;
DADD R16, R16, R18 ;
DADD R16, R16, R20 ;
DADD R16, R16, R22 ;
@!P1 BRA 0x1210 ;
BSYNC B4 ;
IMAD.IADD R18, R0, 0x1, -R15 ;
BSSY B4, 0x1760 ;
ISETP.GT.AND P1, PT, R18, 0x4, PT ;
@!P1 BRA 0x1750 ;
LDS R27, [R24+-0x8] ;
PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ;
IADD3 R15, R15, 0x8, RZ ;
LDS R30, [R24+-0x4] ;
LDS R31, [R24] ;
LDS R32, [R24+0x4] ;
LDS R29, [R24+0x8] ;
LDS R28, [R24+0xc] ;
LDS R25, [R24+0x10] ;
LDS R26, [R24+0x14] ;
IADD3 R24, R24, 0x20, RZ ;
F2F.F64.F32 R20, R27 ;
F2F.F64.F32 R18, R30 ;
F2F.F64.F32 R22, R31 ;
DADD R16, R16, R20 ;
F2F.F64.F32 R20, R32 ;
DADD R18, R16, R18 ;
F2F.F64.F32 R16, R29 ;
DADD R22, R18, R22 ;
F2F.F64.F32 R18, R28 ;
DADD R20, R22, R20 ;
F2F.F64.F32 R22, R25 ;
DADD R16, R20, R16 ;
F2F.F64.F32 R26, R26 ;
DADD R16, R16, R18 ;
DADD R16, R16, R22 ;
DADD R16, R16, R26 ;
BSYNC B4 ;
ISETP.LT.OR P0, PT, R15, R0, P0 ;
@!P0 BRA 0x1840 ;
LDS R15, [R24+-0x8] ;
LDS R25, [R24+-0x4] ;
LDS R20, [R24] ;
LDS R26, [R24+0x4] ;
F2F.F64.F32 R22, R15 ;
F2F.F64.F32 R18, R25 ;
F2F.F64.F32 R20, R20 ;
DADD R22, R16, R22 ;
F2F.F64.F32 R16, R26 ;
DADD R18, R22, R18 ;
DADD R18, R18, R20 ;
DADD R16, R18, R16 ;
BSYNC B3 ;
IADD3 R18, R11, -0x1, R0 ;
IMAD.MOV.U32 R20, RZ, RZ, 0x1 ;
FSETP.GEU.AND P1, PT, |R17|, 6.5827683646048100446e-37, PT ;
BSSY B3, 0x19d0 ;
I2F.F64 R18, R18 ;
MUFU.RCP64H R21, R19 ;
DFMA R22, -R18, R20, 1 ;
DFMA R22, R22, R22, R22 ;
DFMA R22, R20, R22, R20 ;
DFMA R24, -R18, R22, 1 ;
DFMA R24, R22, R24, R22 ;
DMUL R20, R24, R16 ;
DFMA R22, -R18, R20, R16 ;
DFMA R20, R24, R22, R20 ;
FFMA R15, RZ, R19, R21 ;
FSETP.GT.AND P0, PT, |R15|, 1.469367938527859385e-39, PT ;
@P0 BRA P1, 0x19c0 ;
IMAD.MOV.U32 R24, RZ, RZ, R16 ;
MOV R30, 0x19c0 ;
IMAD.MOV.U32 R25, RZ, RZ, R17 ;
IMAD.MOV.U32 R16, RZ, RZ, R18 ;
IMAD.MOV.U32 R17, RZ, RZ, R19 ;
CALL.REL.NOINC 0x1ce0 ;
BSYNC B3 ;
F2F.F32.F64 R17, R20 ;
IMAD.MOV.U32 R18, RZ, RZ, R20 ;
IMAD.MOV.U32 R19, RZ, RZ, R21 ;
STS [R14.X4], R17 ;
BSYNC B0 ;
F2F.F64.F32 R16, R17 ;
IADD3 R4, R4, 0x1, RZ ;
DSETP.GT.AND P0, PT, R18, R16, PT ;
@P0 IADD3 R0, R0, -0x1, RZ ;
@P0 I2F R15, R0 ;
@P0 STS [R14.X4], R15 ;
ISETP.GE.AND P0, PT, R3.reuse, R8, PT ;
IADD3 R3, R3, 0x1, RZ ;
@P0 CALL.REL.NOINC 0x1ac0 ;
BRA 0xd90 ;
BSYNC B1 ;
BRA 0x1af0 ;
STS [R14.X4], RZ ;
BSYNC B2 ;
ULDC UR4, c[0x0][0x0] ;
BAR.SYNC.DEFER_BLOCKING 0x0 ;
USHF.R.U32.HI UR4, URZ, 0x1, UR4 ;
ISETP.NE.AND P0, PT, RZ, UR4, PT ;
@!P0 BRA 0x1c70 ;
IMAD.U32 R3, RZ, RZ, UR4 ;
ISETP.GE.AND P0, PT, R14, R3, PT ;
BSSY B0, 0x1c30 ;
@P0 BRA 0x1c20 ;
IMAD R2, R3, 0x4, R10 ;
LDS R0, [R14.X4] ;
LDS R9, [R2] ;
FSETP.GT.AND P0, PT, R9, R0, PT ;
@P0 STS [R14.X4], R9 ;
@P0 LDS R5, [R2] ;
@P0 STS [R14.X4], R5 ;
@P0 LDS R7, [R2] ;
@P0 STS [R14.X4], R7 ;
BSYNC B0 ;
SHF.R.U32.HI R3, RZ, 0x1, R3 ;
BAR.SYNC.DEFER_BLOCKING 0x0 ;
ISETP.NE.AND P0, PT, R3, RZ, PT ;
@P0 BRA 0x1b60 ;
ISETP.NE.AND P0, PT, R14, RZ, PT ;
@P0 EXIT ;
LDS R5, [RZ] ;
IMAD.MOV.U32 R2, RZ, RZ, 0x4 ;
IMAD.WIDE.U32 R2, R13, R2, c[0x0][0x160] ;
STG.E [R2.64], R5 ;
EXIT ;
FSETP.GEU.AND P0, PT, |R17|.reuse, 1.469367938527859385e-39, PT ;
IMAD.MOV.U32 R19, RZ, RZ, R25 ;
LOP3.LUT R28, R17.reuse, 0x800fffff, RZ, 0xc0, !PT ;
IMAD.MOV.U32 R31, RZ, RZ, 0x1ca00000 ;
LOP3.LUT R32, R17, 0x7ff00000, RZ, 0xc0, !PT ;
IMAD.MOV.U32 R22, RZ, RZ, 0x1 ;
FSETP.GEU.AND P2, PT, |R19|.reuse, 1.469367938527859385e-39, PT ;
IMAD.MOV.U32 R18, RZ, RZ, R24 ;
LOP3.LUT R29, R28, 0x3ff00000, RZ, 0xfc, !PT ;
IMAD.MOV.U32 R28, RZ, RZ, R16 ;
LOP3.LUT R15, R19, 0x7ff00000, RZ, 0xc0, !PT ;
IMAD.MOV.U32 R26, RZ, RZ, R18 ;
BSSY B4, 0x2290 ;
@!P0 DMUL R28, R16, 8.98846567431157953865e+307 ;
ISETP.GE.U32.AND P1, PT, R15, R32, PT ;
IMAD.MOV.U32 R33, RZ, RZ, R15 ;
SEL R27, R31, 0x63400000, !P1 ;
MUFU.RCP64H R23, R29 ;
@!P2 LOP3.LUT R20, R17, 0x7ff00000, RZ, 0xc0, !PT ;
@!P2 IMAD.MOV.U32 R24, RZ, RZ, RZ ;
LOP3.LUT R27, R27, 0x800fffff, R19, 0xf8, !PT ;
@!P2 ISETP.GE.U32.AND P3, PT, R15, R20, PT ;
@!P0 LOP3.LUT R32, R29, 0x7ff00000, RZ, 0xc0, !PT ;
@!P2 SEL R25, R31, 0x63400000, !P3 ;
IADD3 R34, R32, -0x1, RZ ;
@!P2 LOP3.LUT R25, R25, 0x80000000, R19, 0xf8, !PT ;
DFMA R20, R22, -R28, 1 ;
@!P2 LOP3.LUT R25, R25, 0x100000, RZ, 0xfc, !PT ;
DFMA R20, R20, R20, R20 ;
@!P2 DFMA R26, R26, 2, -R24 ;
DFMA R20, R22, R20, R22 ;
@!P2 LOP3.LUT R33, R27, 0x7ff00000, RZ, 0xc0, !PT ;
DFMA R24, R20, -R28, 1 ;
IADD3 R22, R33, -0x1, RZ ;
DFMA R24, R20, R24, R20 ;
ISETP.GT.U32.AND P0, PT, R22, 0x7feffffe, PT ;
ISETP.GT.U32.OR P0, PT, R34, 0x7feffffe, P0 ;
DMUL R20, R24, R26 ;
DFMA R22, R20, -R28, R26 ;
DFMA R22, R24, R22, R20 ;
@P0 BRA 0x2130 ;
LOP3.LUT R20, R17, 0x7ff00000, RZ, 0xc0, !PT ;
ISETP.GE.U32.AND P0, PT, R15.reuse, R20, PT ;
IMAD.IADD R18, R15, 0x1, -R20 ;
SEL R20, R31, 0x63400000, !P0 ;
IMNMX R18, R18, -0x46a00000, !PT ;
IMNMX R15, R18, 0x46a00000, PT ;
IMAD.MOV.U32 R18, RZ, RZ, RZ ;
IMAD.IADD R15, R15, 0x1, -R20 ;
IADD3 R19, R15, 0x7fe00000, RZ ;
DMUL R20, R22, R18 ;
FSETP.GTU.AND P0, PT, |R21|, 1.469367938527859385e-39, PT ;
@P0 BRA 0x2280 ;
DFMA R26, R22, -R28, R26 ;
IMAD.MOV.U32 R18, RZ, RZ, RZ ;
FSETP.NEU.AND P0, PT, R27.reuse, RZ, PT ;
LOP3.LUT R25, R27, 0x80000000, R17, 0x48, !PT ;
LOP3.LUT R19, R25, R19, RZ, 0xfc, !PT ;
@!P0 BRA 0x2280 ;
IMAD.MOV R17, RZ, RZ, -R15 ;
DMUL.RP R18, R22, R18 ;
IMAD.MOV.U32 R16, RZ, RZ, RZ ;
IADD3 R15, -R15, -0x43300000, RZ ;
DFMA R16, R20, -R16, R22 ;
LOP3.LUT R25, R19, R25, RZ, 0x3c, !PT ;
FSETP.NEU.AND P0, PT, |R17|, R15, PT ;
FSEL R20, R18, R20, !P0 ;
FSEL R21, R25, R21, !P0 ;
BRA 0x2280 ;
DSETP.NAN.AND P0, PT, R18, R18, PT ;
@P0 BRA 0x2260 ;
DSETP.NAN.AND P0, PT, R16, R16, PT ;
@P0 BRA 0x2230 ;
ISETP.NE.AND P0, PT, R33, R32, PT ;
IMAD.MOV.U32 R20, RZ, RZ, 0x0 ;
IMAD.MOV.U32 R21, RZ, RZ, -0x80000 ;
@!P0 BRA 0x2280 ;
ISETP.NE.AND P0, PT, R33, 0x7ff00000, PT ;
LOP3.LUT R21, R19, 0x80000000, R17, 0x48, !PT ;
ISETP.EQ.OR P0, PT, R32, RZ, !P0 ;
@P0 LOP3.LUT R15, R21, 0x7ff00000, RZ, 0xfc, !PT ;
@!P0 IMAD.MOV.U32 R20, RZ, RZ, RZ ;
@P0 IMAD.MOV.U32 R20, RZ, RZ, RZ ;
@P0 IMAD.MOV.U32 R21, RZ, RZ, R15 ;
BRA 0x2280 ;
LOP3.LUT R21, R17, 0x80000, RZ, 0xfc, !PT ;
IMAD.MOV.U32 R20, RZ, RZ, R16 ;
BRA 0x2280 ;
LOP3.LUT R21, R19, 0x80000, RZ, 0xfc, !PT ;
IMAD.MOV.U32 R20, RZ, RZ, R18 ;
BSYNC B4 ;
IMAD.MOV.U32 R31, RZ, RZ, 0x0 ;
RET.REL.NODEC R30 0x0 ;
BRA 0x22b0;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
```
|
```amdasm
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z23parallel_max_each_chunkPfS_ii ; -- Begin function _Z23parallel_max_each_chunkPfS_ii
.globl _Z23parallel_max_each_chunkPfS_ii
.p2align 8
.type _Z23parallel_max_each_chunkPfS_ii,@function
_Z23parallel_max_each_chunkPfS_ii: ; @_Z23parallel_max_each_chunkPfS_ii
; %bb.0:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b64 s[6:7], s[0:1], 0x10
s_mov_b32 s4, s15
s_waitcnt lgkmcnt(0)
s_and_b32 s5, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_cvt_f32_u32_e32 v1, s5
s_sub_i32 s3, 0, s5
s_add_i32 s8, s6, s5
s_add_i32 s8, s8, -1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v1, v1
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v1, 0x4f7ffffe, v1
v_cvt_u32_f32_e32 v1, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s2, v1
s_mul_i32 s3, s3, s2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_hi_u32 s3, s2, s3
s_add_i32 s9, s2, s3
s_load_b128 s[0:3], s[0:1], 0x0
s_mul_hi_u32 s9, s8, s9
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s10, s9, s5
s_sub_i32 s8, s8, s10
s_add_i32 s10, s9, 1
s_sub_i32 s11, s8, s5
s_cmp_ge_u32 s8, s5
s_cselect_b32 s9, s10, s9
s_cselect_b32 s8, s11, s8
s_add_i32 s10, s9, 1
s_cmp_ge_u32 s8, s5
s_cselect_b32 s8, s10, s9
s_mov_b32 s9, 0
s_cmp_lt_i32 s8, 1
s_cbranch_scc1 .LBB0_5
; %bb.1: ; %.lr.ph
v_mul_lo_u32 v1, s8, v0
v_mov_b32_e32 v2, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[2:3], 2, v[1:2]
v_lshl_add_u32 v4, v1, 2, 0
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s2, v2
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
.LBB0_2: ; =>This Inner Loop Header: Depth=1
v_add_nc_u32_e32 v5, s9, v1
s_mov_b32 s2, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s6, v5
s_cbranch_execz .LBB0_4
; %bb.3: ; in Loop: Header=BB0_2 Depth=1
global_load_b32 v5, v[2:3], off
s_waitcnt vmcnt(0)
ds_store_b32 v4, v5
.LBB0_4: ; in Loop: Header=BB0_2 Depth=1
s_or_b32 exec_lo, exec_lo, s2
v_add_co_u32 v2, vcc_lo, v2, 4
v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
v_add_nc_u32_e32 v4, 4, v4
s_add_i32 s9, s9, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_lt_i32 s9, s8
s_cbranch_scc1 .LBB0_2
.LBB0_5: ; %._crit_edge
v_mad_u64_u32 v[1:2], null, s4, s5, v[0:1]
s_waitcnt lgkmcnt(0)
s_sub_i32 s2, s6, s7
s_barrier
buffer_gl0_inv
v_cmp_ge_i32_e32 vcc_lo, s2, v1
s_and_saveexec_b32 s2, vcc_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s2, exec_lo, s2
s_cbranch_execz .LBB0_21
; %bb.6: ; %.preheader83
v_sub_nc_u32_e32 v6, s6, v1
s_mov_b32 s3, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_le_i32_e64 s7, v6
s_cbranch_execz .LBB0_20
; %bb.7: ; %.lr.ph93
v_cvt_f64_i32_e32 v[2:3], s7
v_lshl_add_u32 v7, v0, 2, 0
v_cvt_f32_i32_e32 v8, v1
v_lshl_add_u32 v9, v1, 2, 0
s_cmp_gt_i32 s7, 0
s_mov_b32 s8, 0
ds_load_b32 v11, v7
s_cselect_b32 s6, -1, 0
s_mov_b32 s9, s7
; implicit-def: $vgpr4_vgpr5
.LBB0_8: ; =>This Loop Header: Depth=1
; Child Loop BB0_14 Depth 2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v12, s9, v1
s_cmp_lg_u32 s9, s7
v_add_nc_u32_e32 v10, -1, v12
s_cbranch_scc0 .LBB0_10
; %bb.9: ; in Loop: Header=BB0_8 Depth=1
s_delay_alu instid0(VALU_DEP_1)
v_lshl_add_u32 v13, v10, 2, 0
s_add_i32 s10, s9, -1
v_cvt_f64_i32_e32 v[17:18], s9
ds_load_b32 v15, v13
v_cvt_f64_i32_e32 v[13:14], s10
s_mov_b32 s10, 0
s_waitcnt lgkmcnt(0)
v_cvt_f64_f32_e32 v[15:16], v15
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[4:5], v[4:5], v[13:14], v[15:16]
v_div_scale_f64 v[13:14], null, v[17:18], v[17:18], v[4:5]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f64_e32 v[15:16], v[13:14]
s_waitcnt_depctr 0xfff
v_fma_f64 v[19:20], -v[13:14], v[15:16], 1.0
v_fma_f64 v[15:16], v[15:16], v[19:20], v[15:16]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[19:20], -v[13:14], v[15:16], 1.0
v_fma_f64 v[15:16], v[15:16], v[19:20], v[15:16]
v_div_scale_f64 v[19:20], vcc_lo, v[4:5], v[17:18], v[4:5]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f64 v[21:22], v[19:20], v[15:16]
v_fma_f64 v[13:14], -v[13:14], v[21:22], v[19:20]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fmas_f64 v[13:14], v[13:14], v[15:16], v[21:22]
v_div_fixup_f64 v[4:5], v[13:14], v[17:18], v[4:5]
s_branch .LBB0_11
.LBB0_10: ; in Loop: Header=BB0_8 Depth=1
s_mov_b32 s10, -1
; implicit-def: $vgpr4_vgpr5
; implicit-def: $vgpr11
.LBB0_11: ; %Flow122
; in Loop: Header=BB0_8 Depth=1
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 vcc_lo, exec_lo, s10
s_cbranch_vccnz .LBB0_17
; %bb.12: ; %.preheader
; in Loop: Header=BB0_8 Depth=1
v_mov_b32_e32 v4, 0
v_mov_b32_e32 v5, 0
s_and_not1_b32 vcc_lo, exec_lo, s6
s_cbranch_vccnz .LBB0_16
; %bb.13: ; %.lr.ph88.preheader
; in Loop: Header=BB0_8 Depth=1
s_waitcnt lgkmcnt(0)
v_mov_b32_e32 v11, v9
v_mov_b32_e32 v13, v1
s_mov_b32 s10, 0
.LBB0_14: ; %.lr.ph88
; Parent Loop BB0_8 Depth=1
; => This Inner Loop Header: Depth=2
ds_load_b32 v14, v11
v_add_nc_u32_e32 v13, 1, v13
v_add_nc_u32_e32 v11, 4, v11
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_cmp_ge_i32_e32 vcc_lo, v13, v12
s_or_b32 s10, vcc_lo, s10
s_waitcnt lgkmcnt(0)
v_cvt_f64_f32_e32 v[14:15], v14
v_add_f64 v[4:5], v[4:5], v[14:15]
s_and_not1_b32 exec_lo, exec_lo, s10
s_cbranch_execnz .LBB0_14
; %bb.15: ; %Flow120
; in Loop: Header=BB0_8 Depth=1
s_or_b32 exec_lo, exec_lo, s10
.LBB0_16: ; %._crit_edge89
; in Loop: Header=BB0_8 Depth=1
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_scale_f64 v[11:12], null, v[2:3], v[2:3], v[4:5]
v_rcp_f64_e32 v[13:14], v[11:12]
s_waitcnt_depctr 0xfff
v_fma_f64 v[15:16], -v[11:12], v[13:14], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[13:14], v[13:14], v[15:16], v[13:14]
v_fma_f64 v[15:16], -v[11:12], v[13:14], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_fma_f64 v[13:14], v[13:14], v[15:16], v[13:14]
v_div_scale_f64 v[15:16], vcc_lo, v[4:5], v[2:3], v[4:5]
v_mul_f64 v[17:18], v[15:16], v[13:14]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[11:12], -v[11:12], v[17:18], v[15:16]
v_div_fmas_f64 v[11:12], v[11:12], v[13:14], v[17:18]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fixup_f64 v[4:5], v[11:12], v[2:3], v[4:5]
v_cvt_f32_f64_e32 v11, v[4:5]
ds_store_b32 v7, v11
.LBB0_17: ; in Loop: Header=BB0_8 Depth=1
s_waitcnt lgkmcnt(0)
v_cvt_f64_f32_e32 v[12:13], v11
s_mov_b32 s10, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_f64_e32 v[4:5], v[12:13]
s_cbranch_execz .LBB0_19
; %bb.18: ; in Loop: Header=BB0_8 Depth=1
v_cvt_f32_f64_e32 v11, v[4:5]
v_cvt_f32_i32_e32 v10, v10
ds_store_b32 v7, v11
ds_store_b32 v7, v8
ds_store_b32 v7, v10
.LBB0_19: ; in Loop: Header=BB0_8 Depth=1
s_or_b32 exec_lo, exec_lo, s10
v_cmp_ge_i32_e32 vcc_lo, s9, v6
s_add_i32 s9, s9, 1
s_or_b32 s8, vcc_lo, s8
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s8
s_cbranch_execnz .LBB0_8
.LBB0_20: ; %Flow125
s_or_b32 exec_lo, exec_lo, s3
.LBB0_21: ; %Flow126
s_or_saveexec_b32 s2, s2
v_lshl_add_u32 v1, v0, 2, 0
s_xor_b32 exec_lo, exec_lo, s2
s_cbranch_execz .LBB0_23
; %bb.22:
v_mov_b32_e32 v2, 0
ds_store_b32 v1, v2
.LBB0_23: ; %.loopexit
s_or_b32 exec_lo, exec_lo, s2
s_cmp_lt_u32 s5, 2
s_waitcnt vmcnt(0) lgkmcnt(0)
s_waitcnt_vscnt null, 0x0
.LBB0_24: ; %.loopexit
; =>This Inner Loop Header: Depth=1
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB0_29
; %bb.25: ; in Loop: Header=BB0_24 Depth=1
s_mov_b32 s2, s5
s_lshr_b32 s5, s5, 1
s_mov_b32 s3, exec_lo
v_cmpx_gt_u32_e64 s5, v0
s_cbranch_execz .LBB0_28
; %bb.26: ; in Loop: Header=BB0_24 Depth=1
v_lshl_add_u32 v2, s5, 2, v1
ds_load_b32 v2, v2
ds_load_b32 v3, v1
s_waitcnt lgkmcnt(0)
v_cmp_gt_f32_e32 vcc_lo, v2, v3
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_28
; %bb.27: ; in Loop: Header=BB0_24 Depth=1
s_lshl_b32 s6, s5, 2
s_delay_alu instid0(SALU_CYCLE_1)
v_add_nc_u32_e32 v3, s6, v1
ds_load_b32 v4, v3
ds_load_b32 v3, v3
ds_store_b32 v1, v2
s_waitcnt lgkmcnt(2)
ds_store_b32 v1, v4
s_waitcnt lgkmcnt(2)
ds_store_b32 v1, v3
.LBB0_28: ; in Loop: Header=BB0_24 Depth=1
s_or_b32 exec_lo, exec_lo, s3
s_waitcnt lgkmcnt(0)
s_cmp_lt_u32 s2, 4
s_branch .LBB0_24
.LBB0_29: ; %._crit_edge99
s_mov_b32 s5, 0
s_mov_b32 s2, exec_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB0_31
; %bb.30:
v_mov_b32_e32 v0, 0
s_lshl_b64 s[2:3], s[4:5], 2
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
ds_load_b32 v1, v0
s_waitcnt lgkmcnt(0)
global_store_b32 v0, v1, s[0:1]
.LBB0_31:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z23parallel_max_each_chunkPfS_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 23
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z23parallel_max_each_chunkPfS_ii, .Lfunc_end0-_Z23parallel_max_each_chunkPfS_ii
; -- End function
.section .AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1200
; NumSgprs: 18
; NumVgprs: 23
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 2
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 23
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object ; @__hip_cuid_
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0 ; 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
- .offset: 144
.size: 4
.value_kind: hidden_dynamic_lds_size
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z23parallel_max_each_chunkPfS_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z23parallel_max_each_chunkPfS_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 23
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
```
| 10,955 | 7,045 |
499 |
Convert the following CUDA host assembly code to AMD host assembly:
```cudaasm
.file "tmpxft_001ae8d9_00000000-6_HW3_small_n.cudafe1.cpp"
.text
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z47__device_stub__Z23parallel_max_each_chunkPfS_iiPfS_ii
.type _Z47__device_stub__Z23parallel_max_each_chunkPfS_iiPfS_ii, @function
_Z47__device_stub__Z23parallel_max_each_chunkPfS_iiPfS_ii:
.LFB2082:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z23parallel_max_each_chunkPfS_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z47__device_stub__Z23parallel_max_each_chunkPfS_iiPfS_ii, .-_Z47__device_stub__Z23parallel_max_each_chunkPfS_iiPfS_ii
.globl _Z23parallel_max_each_chunkPfS_ii
.type _Z23parallel_max_each_chunkPfS_ii, @function
_Z23parallel_max_each_chunkPfS_ii:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z47__device_stub__Z23parallel_max_each_chunkPfS_iiPfS_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z23parallel_max_each_chunkPfS_ii, .-_Z23parallel_max_each_chunkPfS_ii
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "right\n"
.LC2:
.string "wrong\n"
.LC3:
.string "max of block %d, %f %f\n "
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC4:
.string "\n--------correct or wrong---------\n"
.section .rodata.str1.1
.LC5:
.string "\n--------1d array---------\n"
.LC6:
.string "element %d, %f\n "
.LC7:
.string "CUDA error: %s\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $88, %rsp
.cfi_def_cfa_offset 144
movq %rsi, %rbx
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movq 8(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %r14
movq %rax, 24(%rsp)
movl %eax, %r15d
movq 16(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %r12
movl %eax, 12(%rsp)
movslq %r14d, %rbx
salq $2, %rbx
movq %rbx, %rdi
call malloc@PLT
movq %rax, 16(%rsp)
testl %r14d, %r14d
jle .L12
movq %rax, %rdx
movl %r14d, %eax
.L13:
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movss %xmm0, (%rdx)
addq $4, %rdx
subl $1, %eax
jne .L13
.L12:
movq 24(%rsp), %rax
leal 14(%rax), %ebp
addl $7, %eax
cmovns %eax, %ebp
sarl $3, %ebp
movslq %ebp, %rax
leaq 0(,%rax,4), %r13
movq %r13, %rdi
call malloc@PLT
movq %rax, %r14
leaq 32(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq 40(%rsp), %rdi
movq %r13, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %rbx, %rdx
movq 16(%rsp), %rsi
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
movl %ebp, 48(%rsp)
movl $1, 52(%rsp)
movl $8, 60(%rsp)
movl $1, 64(%rsp)
movl $0, %r9d
leaq 96(%rbx), %r8
movq 60(%rsp), %rdx
movl $1, %ecx
movq 48(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L33
.L14:
call cudaThreadSynchronize@PLT
movl $2, %ecx
movq %r13, %rdx
movq 40(%rsp), %rsi
movq %r14, %rdi
call cudaMemcpy@PLT
movq %r13, %rdi
call malloc@PLT
movq %rax, %r13
cmpl $0, 24(%rsp)
jle .L15
movl %r12d, %esi
shrl $31, %esi
addl %r12d, %esi
sarl %esi
movl %r12d, %edx
movl $0, %eax
pxor %xmm1, %xmm1
subl %r12d, %esi
jmp .L17
.L33:
movl 12(%rsp), %ecx
movl %r15d, %edx
movq 32(%rsp), %rsi
movq 40(%rsp), %rdi
call _Z47__device_stub__Z23parallel_max_each_chunkPfS_iiPfS_ii
jmp .L14
.L16:
movss %xmm0, 0(%r13,%rax,4)
addq $1, %rax
addl $8, %edx
cmpl %eax, %ebp
jle .L34
.L17:
movaps %xmm1, %xmm0
cmpl %edx, %r15d
jl .L16
leal (%rsi,%rdx), %ecx
movslq %ecx, %rcx
movq 16(%rsp), %rdi
movss (%rdi,%rcx,4), %xmm0
jmp .L16
.L34:
movl $0, %ebx
movl $1, %r12d
jmp .L19
.L18:
addq $1, %rbx
cmpl %ebx, %ebp
jle .L35
.L19:
movss 0(%r13,%rbx,4), %xmm2
movss %xmm2, 12(%rsp)
pxor %xmm0, %xmm0
cvtss2sd %xmm2, %xmm0
pxor %xmm1, %xmm1
cvtss2sd (%r14,%rbx,4), %xmm1
movl %ebx, %edx
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $2, %eax
call __printf_chk@PLT
testb %r12b, %r12b
je .L18
movss 12(%rsp), %xmm2
ucomiss (%r14,%rbx,4), %xmm2
setnp %r12b
movl $0, %eax
cmovne %eax, %r12d
jmp .L18
.L35:
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
testb %r12b, %r12b
leaq .LC2(%rip), %rsi
leaq .LC1(%rip), %rax
cmovne %rax, %rsi
.L20:
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 24(%rsp), %eax
subl $1, %eax
cmpl $13, %eax
ja .L21
movl $0, %ebx
leaq .LC6(%rip), %rbp
.L22:
movq 16(%rsp), %rax
pxor %xmm0, %xmm0
cvtss2sd (%rax,%rbx,4), %xmm0
movl %ebx, %edx
movq %rbp, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpl %ebx, %r15d
jg .L22
.L21:
call cudaGetLastError@PLT
testl %eax, %eax
jne .L36
.L23:
movq 40(%rsp), %rdi
call cudaFree@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L37
movl $0, %eax
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L36:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L23
.L15:
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC1(%rip), %rsi
jmp .L20
.L37:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.8
.align 8
.LC8:
.string "_Z23parallel_max_each_chunkPfS_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _Z23parallel_max_each_chunkPfS_ii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
```
|
```amdasm
.text
.file "HW3_small_n.hip"
.globl main # -- Begin function main
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $40, %rsp
.cfi_def_cfa_offset 96
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsi, %rbx
movq 8(%rsi), %rdi
callq atoi
movl %eax, %ebp
movq 16(%rbx), %rdi
callq atoi
movl %eax, 4(%rsp) # 4-byte Spill
movslq %ebp, %r14
leaq (,%r14,4), %rdi
movq %rdi, 32(%rsp) # 8-byte Spill
callq malloc
movq %rax, %rbx
testl %r14d, %r14d
jle .LBB0_3
# %bb.1: # %.lr.ph.preheader
leaq 1(%r14), %rax
movl %ebp, %ecx
movq %rbx, %rdx
.LBB0_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
xorps %xmm0, %xmm0
cvtsi2ss %ecx, %xmm0
movss %xmm0, (%rdx)
decq %rax
addq $4, %rdx
decl %ecx
cmpq $1, %rax
jg .LBB0_2
.LBB0_3: # %._crit_edge
leal 7(%r14), %eax
leal 14(%r14), %r13d
testl %eax, %eax
cmovnsl %eax, %r13d
sarl $3, %r13d
movslq %r13d, %r12
shlq $2, %r12
movq %r12, %rdi
callq malloc
movq %rax, %r15
movq %rbp, 24(%rsp) # 8-byte Spill
leaq 16(%rsp), %rdi
movq 32(%rsp), %rbp # 8-byte Reload
movq %rbp, %rsi
callq hipMalloc
leaq 8(%rsp), %rdi
movq %r12, %rsi
callq hipMalloc
leaq 16(%rsp), %rax
movq (%rax), %rdi
movq 24(%rsp), %rax # 8-byte Reload
movq %rbx, %rsi
movq %rbp, %rdx
movq %rax, %rbp
movl $1, %ecx
callq hipMemcpy
movq %r13, %rdi
btsq $32, %rdi
leaq 96(,%r14,4), %r8
movabsq $4294967296, %rdx # imm = 0x100000000
orq $8, %rdx
movl $1, %esi
movl $1, %ecx
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB0_5
# %bb.4:
movq 8(%rsp), %rdi
movq 16(%rsp), %rsi
movl %ebp, %edx
movl 4(%rsp), %ecx # 4-byte Reload
callq _Z38__device_stub__parallel_max_each_chunkPfS_ii
.LBB0_5:
callq hipDeviceSynchronize
movq 8(%rsp), %rsi
movq %r15, %rdi
movq %r12, %rdx
movl $2, %ecx
callq hipMemcpy
movq %r12, %rdi
callq malloc
movl $.L.str.2, %edi
testl %ebp, %ebp
jle .LBB0_17
# %bb.6: # %.lr.ph76
movq %rax, %r12
movl 4(%rsp), %edx # 4-byte Reload
movl %edx, %eax
shrl $31, %eax
addl %edx, %eax
sarl %eax
movslq %eax, %rcx
movslq %edx, %rdx
cmpl $2, %r13d
movl $1, %eax
cmovgel %r13d, %eax
subq %rdx, %r14
leaq (%rbx,%rcx,4), %rcx
shlq $3, %rax
xorl %edx, %edx
movq %r12, %rsi
.LBB0_7: # =>This Inner Loop Header: Depth=1
xorps %xmm0, %xmm0
cmpq %r14, %rdx
jg .LBB0_9
# %bb.8: # in Loop: Header=BB0_7 Depth=1
movss (%rcx,%rdx,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
.LBB0_9: # in Loop: Header=BB0_7 Depth=1
movss %xmm0, (%rsi)
addq $8, %rdx
addq $4, %rsi
cmpq %rdx, %rax
jne .LBB0_7
# %bb.10: # %.preheader72
testl %ebp, %ebp
jle .LBB0_17
# %bb.11: # %.lr.ph79.preheader
cmpl $2, %r13d
movl $1, %r14d
cmovgel %r13d, %r14d
movb $1, %bpl
xorl %r13d, %r13d
.LBB0_12: # %.lr.ph79
# =>This Inner Loop Header: Depth=1
movss (%r12,%r13,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
movss %xmm0, 4(%rsp) # 4-byte Spill
cvtss2sd %xmm0, %xmm0
xorps %xmm1, %xmm1
cvtss2sd (%r15,%r13,4), %xmm1
movl $.L.str, %edi
movl %r13d, %esi
movb $2, %al
callq printf
testb $1, %bpl
je .LBB0_13
# %bb.14: # in Loop: Header=BB0_12 Depth=1
movss 4(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
cmpeqss (%r15,%r13,4), %xmm0
movd %xmm0, %ebp
andl $1, %ebp
jmp .LBB0_15
.LBB0_13: # in Loop: Header=BB0_12 Depth=1
xorl %ebp, %ebp
.LBB0_15: # in Loop: Header=BB0_12 Depth=1
incq %r13
cmpq %r13, %r14
jne .LBB0_12
# %bb.16: # %._crit_edge80.loopexit
movl $.L.str.2, %eax
movl $.L.str.3, %edi
testb %bpl, %bpl
cmovneq %rax, %rdi
movq 24(%rsp), %rbp # 8-byte Reload
.LBB0_17: # %._crit_edge80
movq %rdi, %r14
movl $.Lstr, %edi
callq puts@PLT
movq %r14, %rdi
xorl %eax, %eax
callq printf
movl $.Lstr.1, %edi
callq puts@PLT
leal -1(%rbp), %eax
cmpl $13, %eax
ja .LBB0_20
# %bb.18: # %.lr.ph82.preheader
movl %ebp, %r15d
xorl %r14d, %r14d
.LBB0_19: # %.lr.ph82
# =>This Inner Loop Header: Depth=1
xorps %xmm0, %xmm0
cvtss2sd (%rbx,%r14,4), %xmm0
movl $.L.str.5, %edi
movl %r14d, %esi
movb $1, %al
callq printf
incq %r14
cmpq %r14, %r15
jne .LBB0_19
.LBB0_20: # %.loopexit
callq hipGetLastError
testl %eax, %eax
je .LBB0_22
# %bb.21:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.6, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
.LBB0_22:
movq 8(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $40, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.globl _Z38__device_stub__parallel_max_each_chunkPfS_ii # -- Begin function _Z38__device_stub__parallel_max_each_chunkPfS_ii
.type _Z38__device_stub__parallel_max_each_chunkPfS_ii,@function
_Z38__device_stub__parallel_max_each_chunkPfS_ii: # @_Z38__device_stub__parallel_max_each_chunkPfS_ii
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $112, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 40(%rsp), %rax
movq %rdi, (%rax)
leaq 32(%rsp), %rdi
movq %rsi, (%rdi)
leaq 12(%rsp), %rsi
movl %edx, (%rsi)
leaq 8(%rsp), %rdx
movl %ecx, (%rdx)
leaq 80(%rsp), %rbx
movq %rax, (%rbx)
movq %rdi, 8(%rbx)
movq %rsi, 16(%rbx)
movq %rdx, 24(%rbx)
leaq 64(%rsp), %r14
leaq 48(%rsp), %r15
leaq 24(%rsp), %r12
leaq 16(%rsp), %r13
movq %r14, %rdi
movq %r15, %rsi
movq %r12, %rdx
movq %r13, %rcx
callq __hipPopCallConfiguration
movq (%r14), %rsi
movl 8(%r14), %edx
movq (%r15), %rcx
movl 8(%r15), %r8d
movl $_Z23parallel_max_each_chunkPfS_ii, %edi
movq %rbx, %r9
pushq (%r13)
.cfi_adjust_cfa_offset 8
pushq (%r12)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $128, %rsp
.cfi_adjust_cfa_offset -128
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z38__device_stub__parallel_max_each_chunkPfS_ii, .Lfunc_end1-_Z38__device_stub__parallel_max_each_chunkPfS_ii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, %rdi
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z23parallel_max_each_chunkPfS_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z23parallel_max_each_chunkPfS_ii,@object # @_Z23parallel_max_each_chunkPfS_ii
.section .rodata,"a",@progbits
.globl _Z23parallel_max_each_chunkPfS_ii
.p2align 3, 0x0
_Z23parallel_max_each_chunkPfS_ii:
.quad _Z38__device_stub__parallel_max_each_chunkPfS_ii
.size _Z23parallel_max_each_chunkPfS_ii, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "max of block %d, %f %f\n "
.size .L.str, 27
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "right\n"
.size .L.str.2, 7
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "wrong\n"
.size .L.str.3, 7
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "element %d, %f\n "
.size .L.str.5, 19
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "CUDA error: %s\n"
.size .L.str.6, 16
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z23parallel_max_each_chunkPfS_ii"
.size .L__unnamed_1, 34
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "\n--------correct or wrong---------"
.size .Lstr, 35
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "\n--------1d array---------"
.size .Lstr.1, 27
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z38__device_stub__parallel_max_each_chunkPfS_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z23parallel_max_each_chunkPfS_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
```
| 4,582 | 5,206 |
500 |
Convert the following CUDA device assembly code to AMD device assembly:
```cudaasm
code for sm_80
```
|
```amdasm
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object ; @__hip_cuid_
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0 ; 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
```
| 24 | 306 |
501 |
Convert the following CUDA host assembly code to AMD host assembly:
```cudaasm
.file "tmpxft_00179e6d_00000000-6_GPUKernels.cudafe1.cpp"
.text
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
```
|
```amdasm
.text
.file "GPUKernels.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
```
| 748 | 185 |
502 |
Convert the following CUDA device assembly code to AMD device assembly:
```cudaasm
code for sm_80
```
|
```amdasm
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object ; @__hip_cuid_
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0 ; 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
```
| 24 | 306 |
503 |
Convert the following CUDA host assembly code to AMD host assembly:
```cudaasm
.file "tmpxft_001a30f0_00000000-6_main_cpu.cudafe1.cpp"
.text
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2063:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2063:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z6VecAddPKfS0_Pfi
.type _Z6VecAddPKfS0_Pfi, @function
_Z6VecAddPKfS0_Pfi:
.LFB2057:
.cfi_startproc
endbr64
testl %ecx, %ecx
jle .L3
movslq %ecx, %rcx
salq $2, %rcx
movl $0, %eax
.L5:
movss (%rdi,%rax), %xmm0
addss (%rsi,%rax), %xmm0
movss %xmm0, (%rdx,%rax)
addq $4, %rax
cmpq %rcx, %rax
jne .L5
.L3:
ret
.cfi_endproc
.LFE2057:
.size _Z6VecAddPKfS0_Pfi, .-_Z6VecAddPKfS0_Pfi
.globl _Z7VecFillPfiff
.type _Z7VecFillPfiff, @function
_Z7VecFillPfiff:
.LFB2058:
.cfi_startproc
endbr64
testl %esi, %esi
jle .L7
movslq %esi, %rsi
movl $0, %eax
.L9:
pxor %xmm2, %xmm2
cvtsi2ssl %eax, %xmm2
mulss %xmm1, %xmm2
addss %xmm0, %xmm2
movss %xmm2, (%rdi,%rax,4)
addq $1, %rax
cmpq %rsi, %rax
jne .L9
.L7:
ret
.cfi_endproc
.LFE2058:
.size _Z7VecFillPfiff, .-_Z7VecFillPfiff
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%s : \n"
.LC1:
.string "[%d] : %f\n"
.text
.globl _Z8VecPrintPKfiPKc
.type _Z8VecPrintPKfiPKc, @function
_Z8VecPrintPKfiPKc:
.LFB2059:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $8, %rsp
.cfi_def_cfa_offset 48
movq %rdi, %r12
movl %esi, %ebp
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
testl %ebp, %ebp
jle .L11
movslq %ebp, %rbp
movl $0, %ebx
leaq .LC1(%rip), %r13
.L13:
pxor %xmm0, %xmm0
cvtss2sd (%r12,%rbx,4), %xmm0
movl %ebx, %edx
movq %r13, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq %rbp, %rbx
jne .L13
.L11:
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2059:
.size _Z8VecPrintPKfiPKc, .-_Z8VecPrintPKfiPKc
.section .rodata.str1.1
.LC4:
.string "A"
.LC7:
.string "B"
.LC8:
.string "A+B"
.text
.globl main
.type main, @function
main:
.LFB2060:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
movl $40, %edi
call malloc@PLT
movq %rax, %rbp
movl $40, %edi
call malloc@PLT
movq %rax, %rbx
movl $40, %edi
call malloc@PLT
movq %rax, %r12
movss .LC2(%rip), %xmm1
pxor %xmm0, %xmm0
movl $10, %esi
movq %rbp, %rdi
call _Z7VecFillPfiff
leaq .LC4(%rip), %rdx
movl $10, %esi
movq %rbp, %rdi
call _Z8VecPrintPKfiPKc
movss .LC5(%rip), %xmm1
movss .LC6(%rip), %xmm0
movl $10, %esi
movq %rbx, %rdi
call _Z7VecFillPfiff
leaq .LC7(%rip), %rdx
movl $10, %esi
movq %rbx, %rdi
call _Z8VecPrintPKfiPKc
movl $10, %ecx
movq %r12, %rdx
movq %rbx, %rsi
movq %rbp, %rdi
call _Z6VecAddPKfS0_Pfi
leaq .LC8(%rip), %rdx
movl $10, %esi
movq %r12, %rdi
call _Z8VecPrintPKfiPKc
movq %rbp, %rdi
call free@PLT
movq %rbx, %rdi
call free@PLT
movq %r12, %rdi
call free@PLT
movl $0, %eax
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC2:
.long 1065353216
.align 4
.LC5:
.long -1090519040
.align 4
.LC6:
.long 1092616192
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
```
|
```amdasm
.text
.file "main_cpu.hip"
.globl _Z6VecAddPKfS0_Pfi # -- Begin function _Z6VecAddPKfS0_Pfi
.type _Z6VecAddPKfS0_Pfi,@function
_Z6VecAddPKfS0_Pfi: # @_Z6VecAddPKfS0_Pfi
.cfi_startproc
# %bb.0:
testl %ecx, %ecx
jle .LBB0_3
# %bb.1: # %.lr.ph.preheader
movl %ecx, %eax
xorl %ecx, %ecx
.LBB0_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movss (%rdi,%rcx,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
addss (%rsi,%rcx,4), %xmm0
movss %xmm0, (%rdx,%rcx,4)
incq %rcx
cmpq %rcx, %rax
jne .LBB0_2
.LBB0_3: # %._crit_edge
retq
.Lfunc_end0:
.size _Z6VecAddPKfS0_Pfi, .Lfunc_end0-_Z6VecAddPKfS0_Pfi
.cfi_endproc
# -- End function
.globl _Z7VecFillPfiff # -- Begin function _Z7VecFillPfiff
.type _Z7VecFillPfiff,@function
_Z7VecFillPfiff: # @_Z7VecFillPfiff
.cfi_startproc
# %bb.0:
testl %esi, %esi
jle .LBB1_3
# %bb.1: # %.lr.ph.preheader
movl %esi, %eax
xorl %ecx, %ecx
.LBB1_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
xorps %xmm2, %xmm2
cvtsi2ss %ecx, %xmm2
mulss %xmm1, %xmm2
addss %xmm0, %xmm2
movss %xmm2, (%rdi,%rcx,4)
incq %rcx
cmpq %rcx, %rax
jne .LBB1_2
.LBB1_3: # %._crit_edge
retq
.Lfunc_end1:
.size _Z7VecFillPfiff, .Lfunc_end1-_Z7VecFillPfiff
.cfi_endproc
# -- End function
.globl _Z8VecPrintPKfiPKc # -- Begin function _Z8VecPrintPKfiPKc
.type _Z8VecPrintPKfiPKc,@function
_Z8VecPrintPKfiPKc: # @_Z8VecPrintPKfiPKc
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
pushq %rax
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %esi, %ebp
movq %rdi, %rbx
movl $.L.str, %edi
movq %rdx, %rsi
xorl %eax, %eax
callq printf
testl %ebp, %ebp
jle .LBB2_3
# %bb.1: # %.lr.ph.preheader
movl %ebp, %r15d
xorl %r14d, %r14d
.LBB2_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
xorps %xmm0, %xmm0
cvtss2sd (%rbx,%r14,4), %xmm0
movl $.L.str.1, %edi
movl %r14d, %esi
movb $1, %al
callq printf
incq %r14
cmpq %r14, %r15
jne .LBB2_2
.LBB2_3: # %._crit_edge
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size _Z8VecPrintPKfiPKc, .Lfunc_end2-_Z8VecPrintPKfiPKc
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI3_0:
.long 0xbf000000 # float -0.5
.LCPI3_1:
.long 0x41200000 # float 10
.text
.globl main
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $40, %edi
callq malloc
movq %rax, %rbx
movl $40, %edi
callq malloc
movq %rax, %r14
movl $40, %edi
callq malloc
movq %rax, %r15
xorl %eax, %eax
.LBB3_1: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movss %xmm0, (%rbx,%rax,4)
incq %rax
cmpq $10, %rax
jne .LBB3_1
# %bb.2: # %_Z7VecFillPfiff.exit
movl $.L.str.2, %edx
movq %rbx, %rdi
movl $10, %esi
callq _Z8VecPrintPKfiPKc
xorl %eax, %eax
movss .LCPI3_0(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero
movss .LCPI3_1(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero
.LBB3_3: # %.lr.ph.i20
# =>This Inner Loop Header: Depth=1
xorps %xmm2, %xmm2
cvtsi2ss %eax, %xmm2
mulss %xmm0, %xmm2
addss %xmm1, %xmm2
movss %xmm2, (%r14,%rax,4)
incq %rax
cmpq $10, %rax
jne .LBB3_3
# %bb.4: # %_Z7VecFillPfiff.exit24
movl $.L.str.3, %edx
movq %r14, %rdi
movl $10, %esi
callq _Z8VecPrintPKfiPKc
xorl %eax, %eax
.LBB3_5: # %.lr.ph.i25
# =>This Inner Loop Header: Depth=1
movss (%rbx,%rax,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
addss (%r14,%rax,4), %xmm0
movss %xmm0, (%r15,%rax,4)
incq %rax
cmpq $10, %rax
jne .LBB3_5
# %bb.6: # %_Z6VecAddPKfS0_Pfi.exit
movl $.L.str.4, %edx
movq %r15, %rdi
movl $10, %esi
callq _Z8VecPrintPKfiPKc
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
xorl %eax, %eax
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%s : \n"
.size .L.str, 7
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "[%d] : %f\n"
.size .L.str.1, 11
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "A"
.size .L.str.2, 2
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "B"
.size .L.str.3, 2
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "A+B"
.size .L.str.4, 4
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
```
| 2,573 | 2,670 |
508 |
Convert the following CUDA device assembly code to AMD device assembly:
```cudaasm
code for sm_80
Function : _Z13gpu_multABtoCPfS_S_iii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
MOV R1, c[0x0][0x28] ;
S2R R0, SR_CTAID.X ;
S2R R5, SR_TID.X ;
S2R R3, SR_CTAID.Y ;
S2R R2, SR_TID.Y ;
IMAD R0, R0, c[0x0][0x0], R5 ;
ISETP.GE.AND P0, PT, R0, c[0x0][0x180], PT ;
IMAD R3, R3, c[0x0][0x4], R2 ;
ISETP.GE.OR P0, PT, R3, c[0x0][0x178], P0 ;
@P0 EXIT ;
MOV R4, c[0x0][0x17c] ;
ULDC.64 UR4, c[0x0][0x118] ;
HFMA2.MMA R24, -RZ, RZ, 0, 0 ;
ISETP.GE.AND P0, PT, R4, 0x1, PT ;
@!P0 BRA 0xc40 ;
IADD3 R2, R4.reuse, -0x1, RZ ;
LOP3.LUT R4, R4, 0x3, RZ, 0xc0, !PT ;
ISETP.GE.U32.AND P0, PT, R2, 0x3, PT ;
MOV R24, RZ ;
MOV R2, RZ ;
@!P0 BRA 0xb30 ;
IADD3 R5, -R4, c[0x0][0x17c], RZ ;
HFMA2.MMA R9, -RZ, RZ, 0, 2.384185791015625e-07 ;
ULDC.64 UR6, c[0x0][0x160] ;
HFMA2.MMA R2, -RZ, RZ, 0, 0 ;
ISETP.GT.AND P0, PT, R5, RZ, PT ;
IMAD R6, R3, c[0x0][0x17c], RZ ;
MOV R24, RZ ;
IMAD.WIDE R8, R0, R9, c[0x0][0x168] ;
@!P0 BRA 0x990 ;
ISETP.GT.AND P1, PT, R5, 0xc, PT ;
PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ;
@!P1 BRA 0x6c0 ;
PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ;
MOV R12, UR6 ;
LDG.E R21, [R8.64] ;
MOV R13, UR7 ;
IMAD.WIDE R12, R6, 0x4, R12 ;
LDG.E R20, [R12.64] ;
MOV R7, c[0x0][0x180] ;
LDG.E R14, [R12.64+0x4] ;
IMAD.WIDE R10, R7.reuse, 0x4, R8 ;
LDG.E R27, [R12.64+0x8] ;
LDG.E R15, [R10.64] ;
IMAD.WIDE R22, R7, 0x4, R10 ;
LDG.E R18, [R12.64+0xc] ;
IMAD.WIDE R28, R7.reuse, 0x4, R22 ;
LDG.E R26, [R22.64] ;
LDG.E R19, [R28.64] ;
IMAD.WIDE R16, R7, 0x4, R28 ;
LDG.E R8, [R12.64+0x10] ;
LDG.E R9, [R16.64] ;
LDG.E R10, [R12.64+0x14] ;
LDG.E R28, [R12.64+0x1c] ;
IMAD.WIDE R16, R7, 0x4, R16 ;
LDG.E R11, [R16.64] ;
IMAD.WIDE R22, R7, 0x4, R16 ;
FFMA R16, R21, R20, R24 ;
LDG.E R20, [R12.64+0x18] ;
IMAD.WIDE R24, R7, 0x4, R22 ;
LDG.E R21, [R22.64] ;
LDG.E R29, [R24.64] ;
FFMA R16, R15, R14, R16 ;
IMAD.WIDE R14, R7.reuse, 0x4, R24 ;
LDG.E R23, [R12.64+0x20] ;
FFMA R26, R26, R27, R16 ;
LDG.E R25, [R12.64+0x24] ;
IMAD.WIDE R16, R7, 0x4, R14 ;
LDG.E R14, [R14.64] ;
FFMA R26, R19, R18, R26 ;
IMAD.WIDE R18, R7, 0x4, R16 ;
LDG.E R22, [R12.64+0x28] ;
FFMA R26, R9, R8, R26 ;
LDG.E R16, [R16.64] ;
IMAD.WIDE R8, R7, 0x4, R18 ;
LDG.E R18, [R18.64] ;
LDG.E R24, [R8.64] ;
LDG.E R15, [R12.64+0x2c] ;
FFMA R26, R11, R10, R26 ;
IMAD.WIDE R10, R7, 0x4, R8 ;
LDG.E R17, [R12.64+0x30] ;
FFMA R26, R21, R20, R26 ;
IMAD.WIDE R20, R7, 0x4, R10 ;
LDG.E R10, [R10.64] ;
FFMA R28, R29, R28, R26 ;
IMAD.WIDE R26, R7.reuse, 0x4, R20 ;
LDG.E R29, [R12.64+0x34] ;
LDG.E R20, [R20.64] ;
IMAD.WIDE R8, R7, 0x4, R26 ;
LDG.E R19, [R26.64] ;
LDG.E R11, [R8.64] ;
LDG.E R21, [R12.64+0x38] ;
LDG.E R26, [R12.64+0x3c] ;
FFMA R14, R14, R23, R28 ;
FFMA R25, R16, R25, R14 ;
IADD3 R5, R5, -0x10, RZ ;
FFMA R18, R18, R22, R25 ;
ISETP.GT.AND P1, PT, R5, 0xc, PT ;
FFMA R15, R24, R15, R18 ;
UIADD3 UR6, UP0, UR6, 0x40, URZ ;
IMAD.WIDE R8, R7, 0x4, R8 ;
UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ;
IADD3 R2, R2, 0x10, RZ ;
FFMA R10, R10, R17, R15 ;
FFMA R10, R20, R29, R10 ;
FFMA R10, R19, R21, R10 ;
FFMA R24, R11, R26, R10 ;
@P1 BRA 0x220 ;
ISETP.GT.AND P1, PT, R5, 0x4, PT ;
@!P1 BRA 0x970 ;
MOV R7, c[0x0][0x180] ;
LDG.E R23, [R8.64] ;
MOV R10, UR6 ;
MOV R11, UR7 ;
IMAD.WIDE R16, R7, 0x4, R8 ;
IMAD.WIDE R10, R6, 0x4, R10 ;
IMAD.WIDE R12, R7.reuse, 0x4, R16 ;
LDG.E R22, [R10.64] ;
LDG.E R16, [R16.64] ;
IMAD.WIDE R14, R7, 0x4, R12 ;
LDG.E R25, [R10.64+0x4] ;
IMAD.WIDE R18, R7.reuse, 0x4, R14 ;
LDG.E R26, [R12.64] ;
LDG.E R27, [R10.64+0x8] ;
IMAD.WIDE R20, R7, 0x4, R18 ;
LDG.E R14, [R14.64] ;
LDG.E R29, [R10.64+0xc] ;
IMAD.WIDE R8, R7, 0x4, R20 ;
LDG.E R18, [R18.64] ;
LDG.E R28, [R10.64+0x10] ;
IMAD.WIDE R12, R7, 0x4, R8 ;
LDG.E R20, [R20.64] ;
LDG.E R15, [R10.64+0x14] ;
LDG.E R17, [R8.64] ;
LDG.E R21, [R10.64+0x1c] ;
LDG.E R19, [R12.64] ;
LDG.E R8, [R10.64+0x18] ;
UIADD3 UR6, UP0, UR6, 0x20, URZ ;
PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ;
IADD3 R2, R2, 0x8, RZ ;
IADD3 R5, R5, -0x8, RZ ;
UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ;
FFMA R22, R23, R22, R24 ;
FFMA R16, R16, R25, R22 ;
FFMA R16, R26, R27, R16 ;
FFMA R29, R14, R29, R16 ;
FFMA R18, R18, R28, R29 ;
FFMA R15, R20, R15, R18 ;
FFMA R24, R17, R8, R15 ;
IMAD.WIDE R8, R7, 0x4, R12 ;
FFMA R24, R19, R21, R24 ;
ISETP.NE.OR P0, PT, R5, RZ, P0 ;
@!P0 BRA 0xb30 ;
MOV R10, UR6 ;
MOV R11, UR7 ;
MOV R7, c[0x0][0x180] ;
IMAD.WIDE R10, R6, 0x4, R10 ;
IMAD.WIDE R16, R7.reuse, 0x4, R8 ;
LDG.E R18, [R10.64] ;
LDG.E R9, [R8.64] ;
IMAD.WIDE R12, R7, 0x4, R16 ;
LDG.E R17, [R16.64] ;
LDG.E R19, [R10.64+0x4] ;
IMAD.WIDE R14, R7, 0x4, R12 ;
LDG.E R21, [R12.64] ;
LDG.E R20, [R10.64+0x8] ;
LDG.E R22, [R10.64+0xc] ;
LDG.E R23, [R14.64] ;
IADD3 R5, R5, -0x4, RZ ;
ISETP.NE.AND P0, PT, R5, RZ, PT ;
UIADD3 UR6, UP0, UR6, 0x10, URZ ;
IADD3 R2, R2, 0x4, RZ ;
UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ;
FFMA R18, R9, R18, R24 ;
FFMA R18, R17, R19, R18 ;
IMAD.WIDE R8, R7, 0x4, R14 ;
FFMA R18, R21, R20, R18 ;
FFMA R24, R23, R22, R18 ;
@P0 BRA 0x990 ;
ISETP.NE.AND P0, PT, R4, RZ, PT ;
@!P0 BRA 0xc40 ;
HFMA2.MMA R9, -RZ, RZ, 0, 2.384185791015625e-07 ;
IMAD R6, R3, c[0x0][0x17c], R2 ;
IMAD R2, R2, c[0x0][0x180], R0 ;
IMAD.WIDE R6, R6, R9, c[0x0][0x160] ;
IMAD.WIDE R8, R2, R9, c[0x0][0x168] ;
LDG.E R5, [R8.64] ;
LDG.E R2, [R6.64] ;
IADD3 R4, R4, -0x1, RZ ;
MOV R11, c[0x0][0x180] ;
ISETP.NE.AND P0, PT, R4, RZ, PT ;
IMAD.WIDE R8, R11, 0x4, R8 ;
IADD3 R6, P1, R6, 0x4, RZ ;
IADD3.X R7, RZ, R7, RZ, P1, !PT ;
FFMA R24, R5, R2, R24 ;
@P0 BRA 0xba0 ;
MOV R2, 0x4 ;
IMAD R3, R3, c[0x0][0x180], R0 ;
IMAD.WIDE R2, R3, R2, c[0x0][0x170] ;
STG.E [R2.64], R24 ;
EXIT ;
BRA 0xc90;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
```
|
```amdasm
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z13gpu_multABtoCPfS_S_iii ; -- Begin function _Z13gpu_multABtoCPfS_S_iii
.globl _Z13gpu_multABtoCPfS_S_iii
.p2align 8
.type _Z13gpu_multABtoCPfS_S_iii,@function
_Z13gpu_multABtoCPfS_S_iii: ; @_Z13gpu_multABtoCPfS_S_iii
; %bb.0:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x34
s_load_b128 s[4:7], s[0:1], 0x18
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_lshr_b32 s3, s2, 16
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[0:1], null, s14, s2, v[2:3]
v_mad_u64_u32 v[1:2], null, s15, s3, v[3:4]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_gt_i32_e32 vcc_lo, s6, v0
v_cmp_gt_i32_e64 s2, s4, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, s2, vcc_lo
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_6
; %bb.1: ; %.preheader
s_clause 0x1
s_load_b128 s[8:11], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
s_cmp_lt_i32 s5, 1
s_cbranch_scc1 .LBB0_4
; %bb.2: ; %.lr.ph
v_mul_lo_u32 v2, v1, s5
v_mov_b32_e32 v6, 0
v_mov_b32_e32 v4, v0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s8, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s9, v3, vcc_lo
.LBB0_3: ; =>This Inner Loop Header: Depth=1
v_ashrrev_i32_e32 v5, 31, v4
s_add_i32 s5, s5, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_cmp_eq_u32 s5, 0
v_lshlrev_b64 v[7:8], 2, v[4:5]
v_add_nc_u32_e32 v4, s6, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v7, vcc_lo, s10, v7
v_add_co_ci_u32_e32 v8, vcc_lo, s11, v8, vcc_lo
global_load_b32 v5, v[2:3], off
global_load_b32 v7, v[7:8], off
v_add_co_u32 v2, vcc_lo, v2, 4
v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v6, v5, v7
s_cbranch_scc0 .LBB0_3
s_branch .LBB0_5
.LBB0_4:
v_mov_b32_e32 v6, 0
.LBB0_5: ; %Flow54
v_mad_u64_u32 v[2:3], null, v1, s6, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[0:1], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v6, off
.LBB0_6:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13gpu_multABtoCPfS_S_iii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z13gpu_multABtoCPfS_S_iii, .Lfunc_end0-_Z13gpu_multABtoCPfS_S_iii
; -- End function
.section .AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 340
; NumSgprs: 18
; NumVgprs: 9
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 9
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object ; @__hip_cuid_
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0 ; 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13gpu_multABtoCPfS_S_iii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z13gpu_multABtoCPfS_S_iii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
```
| 3,765 | 3,397 |
509 |
Convert the following CUDA host assembly code to AMD host assembly:
```cudaasm
.file "tmpxft_00167915_00000000-6_matmul.cudafe1.cpp"
.text
.globl _ZSt21ios_base_library_initv
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3927:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3927:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z40__device_stub__Z13gpu_multABtoCPfS_S_iiiPfS_S_iii
.type _Z40__device_stub__Z13gpu_multABtoCPfS_S_iiiPfS_S_iii, @function
_Z40__device_stub__Z13gpu_multABtoCPfS_S_iiiPfS_S_iii:
.LFB3949:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z13gpu_multABtoCPfS_S_iii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3949:
.size _Z40__device_stub__Z13gpu_multABtoCPfS_S_iiiPfS_S_iii, .-_Z40__device_stub__Z13gpu_multABtoCPfS_S_iiiPfS_S_iii
.globl _Z13gpu_multABtoCPfS_S_iii
.type _Z13gpu_multABtoCPfS_S_iii, @function
_Z13gpu_multABtoCPfS_S_iii:
.LFB3950:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z40__device_stub__Z13gpu_multABtoCPfS_S_iiiPfS_S_iii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3950:
.size _Z13gpu_multABtoCPfS_S_iii, .-_Z13gpu_multABtoCPfS_S_iii
.globl matmul
.type matmul, @function
matmul:
.LFB3924:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $104, %rsp
.cfi_def_cfa_offset 160
movq %rdi, (%rsp)
movq %rsi, 8(%rsp)
movq %rdx, 16(%rsp)
movl %ecx, %ebx
movl %r8d, 28(%rsp)
movl %r9d, %ebp
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
movslq %ecx, %r12
movslq %r8d, %r13
movq %r12, %r14
imulq %r13, %r14
salq $2, %r14
leaq 40(%rsp), %rdi
movq %r14, %rsi
call cudaMalloc@PLT
movslq %ebp, %r15
salq $2, %r15
imulq %r15, %r13
leaq 48(%rsp), %rdi
movq %r13, %rsi
call cudaMalloc@PLT
imulq %r15, %r12
leaq 56(%rsp), %rdi
movq %r12, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %r14, %rdx
movq 8(%rsp), %rsi
movq 40(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %r13, %rdx
movq 16(%rsp), %rsi
movq 48(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %r12, %rdx
movq (%rsp), %rsi
movq 56(%rsp), %rdi
call cudaMemcpy@PLT
leal 30(%rbp), %eax
movl %ebp, %edx
addl $15, %edx
cmovns %edx, %eax
sarl $4, %eax
movl %eax, 64(%rsp)
leal 30(%rbx), %eax
movl %ebx, %edx
addl $15, %edx
cmovns %edx, %eax
sarl $4, %eax
movl %eax, 68(%rsp)
movl $16, 76(%rsp)
movl $16, 80(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 76(%rsp), %rdx
movl $1, %ecx
movq 64(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L15
.L12:
movl $2, %ecx
movq %r12, %rdx
movq 56(%rsp), %rsi
movq (%rsp), %rdi
call cudaMemcpy@PLT
call cudaDeviceSynchronize@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
movq 48(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rdi
call cudaFree@PLT
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
movl %ebp, %r9d
movl 28(%rsp), %r8d
movl %ebx, %ecx
movq 56(%rsp), %rdx
movq 48(%rsp), %rsi
movq 40(%rsp), %rdi
call _Z40__device_stub__Z13gpu_multABtoCPfS_S_iiiPfS_S_iii
jmp .L12
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3924:
.size matmul, .-matmul
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z13gpu_multABtoCPfS_S_iii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3952:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z13gpu_multABtoCPfS_S_iii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3952:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
```
|
```amdasm
.text
.file "matmul.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z28__device_stub__gpu_multABtoCPfS_S_iii # -- Begin function _Z28__device_stub__gpu_multABtoCPfS_S_iii
.type _Z28__device_stub__gpu_multABtoCPfS_S_iii,@function
_Z28__device_stub__gpu_multABtoCPfS_S_iii: # @_Z28__device_stub__gpu_multABtoCPfS_S_iii
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $144, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 56(%rsp), %rax
movq %rdi, (%rax)
leaq 48(%rsp), %rdi
movq %rsi, (%rdi)
leaq 40(%rsp), %rsi
movq %rdx, (%rsi)
leaq 20(%rsp), %rdx
movl %ecx, (%rdx)
leaq 16(%rsp), %rcx
movl %r8d, (%rcx)
leaq 12(%rsp), %r8
movl %r9d, (%r8)
leaq 96(%rsp), %rbx
movq %rax, (%rbx)
movq %rdi, 8(%rbx)
movq %rsi, 16(%rbx)
movq %rdx, 24(%rbx)
movq %rcx, 32(%rbx)
movq %r8, 40(%rbx)
leaq 80(%rsp), %r14
leaq 64(%rsp), %r15
leaq 32(%rsp), %r12
leaq 24(%rsp), %r13
movq %r14, %rdi
movq %r15, %rsi
movq %r12, %rdx
movq %r13, %rcx
callq __hipPopCallConfiguration
movq (%r14), %rsi
movl 8(%r14), %edx
movq (%r15), %rcx
movl 8(%r15), %r8d
movl $_Z13gpu_multABtoCPfS_S_iii, %edi
movq %rbx, %r9
pushq (%r13)
.cfi_adjust_cfa_offset 8
pushq (%r12)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $160, %rsp
.cfi_adjust_cfa_offset -160
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z28__device_stub__gpu_multABtoCPfS_S_iii, .Lfunc_end0-_Z28__device_stub__gpu_multABtoCPfS_S_iii
.cfi_endproc
# -- End function
.globl matmul # -- Begin function matmul
.type matmul,@function
matmul: # @matmul
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $56, %rsp
.cfi_def_cfa_offset 112
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %r9d, %ebp
movq %rdx, 48(%rsp) # 8-byte Spill
movq %rsi, %r12
movq %rdi, 40(%rsp) # 8-byte Spill
movl %ecx, 28(%rsp) # 4-byte Spill
movslq %ecx, %r13
leaq (,%r13,4), %r14
movl %r8d, 32(%rsp) # 4-byte Spill
movslq %r8d, %r15
movq %r14, %rbx
imulq %r15, %rbx
leaq 16(%rsp), %rdi
movq %rbx, %rsi
callq hipMalloc
movl %ebp, 36(%rsp) # 4-byte Spill
movslq %ebp, %rbp
imulq %rbp, %r15
shlq $2, %r15
leaq 8(%rsp), %rdi
movq %r15, %rsi
callq hipMalloc
imulq %rbp, %r14
movq %rsp, %rdi
movq %r14, %rsi
callq hipMalloc
leaq 16(%rsp), %rax
movq (%rax), %rdi
movq %r12, %rsi
movq %rbx, %rdx
movq 40(%rsp), %rbx # 8-byte Reload
movl $1, %ecx
callq hipMemcpy
leaq 8(%rsp), %rax
movq (%rax), %rdi
movq 48(%rsp), %rsi # 8-byte Reload
movq %r15, %rdx
movl $1, %ecx
callq hipMemcpy
movq %rsp, %rax
movq (%rax), %rdi
movq %rbx, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
leal 15(%r13), %eax
addl $30, %r13d
testl %eax, %eax
cmovnsl %eax, %r13d
sarl $4, %r13d
leal 15(%rbp), %eax
addl $30, %ebp
testl %eax, %eax
cmovnsl %eax, %ebp
sarl $4, %ebp
shlq $32, %r13
orq %rbp, %r13
movabsq $68719476752, %rdx # imm = 0x1000000010
movq %r13, %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq 16(%rsp), %rdi
movq 8(%rsp), %rsi
movq (%rsp), %rdx
movl 28(%rsp), %ecx # 4-byte Reload
movl 32(%rsp), %r8d # 4-byte Reload
movl 36(%rsp), %r9d # 4-byte Reload
callq _Z28__device_stub__gpu_multABtoCPfS_S_iii
.LBB1_2:
movq (%rsp), %rsi
movq %rbx, %rdi
movq %r14, %rdx
movl $2, %ecx
callq hipMemcpy
callq hipDeviceSynchronize
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipFree
addq $56, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size matmul, .Lfunc_end1-matmul
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, %rdi
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13gpu_multABtoCPfS_S_iii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z13gpu_multABtoCPfS_S_iii,@object # @_Z13gpu_multABtoCPfS_S_iii
.section .rodata,"a",@progbits
.globl _Z13gpu_multABtoCPfS_S_iii
.p2align 3, 0x0
_Z13gpu_multABtoCPfS_S_iii:
.quad _Z28__device_stub__gpu_multABtoCPfS_S_iii
.size _Z13gpu_multABtoCPfS_S_iii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z13gpu_multABtoCPfS_S_iii"
.size .L__unnamed_1, 27
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z28__device_stub__gpu_multABtoCPfS_S_iii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z13gpu_multABtoCPfS_S_iii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
```
| 3,446 | 3,687 |
510 |
Convert the following CUDA device assembly code to AMD device assembly:
```cudaasm
code for sm_80
Function : _Z21createLaplacianKernelPfS_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ;
S2R R6, SR_CTAID.X ;
IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x174] ;
S2R R3, SR_TID.X ;
SHF.R.S32.HI R4, RZ, 0x1f, R5 ;
IMAD R6, R6, c[0x0][0x0], R3 ;
ISETP.GE.U32.AND P0, PT, R6, c[0x0][0x174], PT ;
ISETP.GE.U32.AND.EX P0, PT, RZ, R4, PT, P0 ;
@P0 EXIT ;
IMAD.MOV.U32 R7, RZ, RZ, c[0x0][0x170] ;
SHF.R.U32.HI R3, RZ, 0x1e, R6 ;
IMAD.SHL.U32 R2, R6, 0x4, RZ ;
ULDC.64 UR4, c[0x0][0x118] ;
ISETP.GE.AND P0, PT, R7, 0x1, PT ;
@P0 IADD3 R8, P1, R2, c[0x0][0x160], RZ ;
@P0 IADD3.X R9, R3, c[0x0][0x164], RZ, P1, !PT ;
@P0 LDG.E R9, [R8.64] ;
IMAD.MOV.U32 R0, RZ, RZ, RZ ;
IADD3 R2, P2, R2, c[0x0][0x168], RZ ;
@P0 IMAD.MOV.U32 R0, RZ, RZ, 0x1 ;
IADD3.X R3, R3, c[0x0][0x16c], RZ, P2, !PT ;
ISETP.GE.AND P1, PT, R0, c[0x0][0x170], PT ;
@P0 STG.E [R2.64], R9 ;
@P1 EXIT ;
IADD3 R8, -R0, c[0x0][0x170], RZ ;
LOP3.LUT R9, RZ, R0, RZ, 0x33, !PT ;
LOP3.LUT P1, R8, R8, 0x3, RZ, 0xc0, !PT ;
IADD3 R9, R9, c[0x0][0x170], RZ ;
ISETP.GE.U32.AND P0, PT, R9, 0x3, PT ;
@!P1 BRA 0x310 ;
LDG.E R11, [R2.64] ;
IMAD R9, R0, c[0x0][0x174], RZ ;
IMAD.MOV.U32 R10, RZ, RZ, R8 ;
IADD3 R13, P1, R6, R9, RZ ;
LEA.HI.X.SX32 R14, R9, RZ, 0x1, P1 ;
LEA R12, P1, R13, c[0x0][0x160], 0x2 ;
LEA.HI.X R13, R13, c[0x0][0x164], R14, 0x2, P1 ;
SHF.L.U64.HI R14, R5, 0x2, R4 ;
IMAD.MOV.U32 R8, RZ, RZ, R12 ;
MOV R9, R13 ;
LDG.E R8, [R8.64] ;
IADD3 R10, R10, -0x1, RZ ;
LEA R12, P2, R5, R12, 0x2 ;
ISETP.NE.AND P1, PT, R10, RZ, PT ;
IADD3 R0, R0, 0x1, RZ ;
IMAD.X R13, R13, 0x1, R14, P2 ;
FADD R11, R8, R11 ;
STG.E [R2.64], R11 ;
@P1 BRA 0x260 ;
@!P0 EXIT ;
IADD3 R8, -R0.reuse, c[0x0][0x170], RZ ;
IMAD R9, R0, c[0x0][0x174], RZ ;
SHF.L.U64.HI R4, R5.reuse, 0x2, R4 ;
IMAD.SHL.U32 R5, R5, 0x4, RZ ;
ISETP.GT.AND P1, PT, R8, 0xc, PT ;
IADD3 R6, P0, R6, R9, RZ ;
LEA.HI.X.SX32 R9, R9, RZ, 0x1, P0 ;
LEA R12, P0, R6, c[0x0][0x160], 0x2 ;
LEA.HI.X R13, R6, c[0x0][0x164], R9, 0x2, P0 ;
LDG.E R9, [R2.64] ;
PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ;
@!P1 BRA 0x950 ;
PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ;
IADD3 R7, R7, -0xc, RZ ;
IMAD.MOV.U32 R10, RZ, RZ, R12 ;
IMAD.MOV.U32 R11, RZ, RZ, R13 ;
LDG.E R6, [R10.64] ;
IADD3 R12, P1, R12, R5, RZ ;
IMAD.X R13, R13, 0x1, R4, P1 ;
FADD R15, R6, R9 ;
STG.E [R2.64], R15 ;
LDG.E R6, [R12.64] ;
IADD3 R8, P1, R12, R5, RZ ;
IMAD.X R9, R13, 0x1, R4, P1 ;
FADD R17, R15, R6 ;
STG.E [R2.64], R17 ;
LDG.E R6, [R8.64] ;
IADD3 R10, P1, R8, R5, RZ ;
IMAD.X R11, R9, 0x1, R4, P1 ;
FADD R19, R17, R6 ;
STG.E [R2.64], R19 ;
LDG.E R6, [R10.64] ;
IADD3 R12, P1, R10, R5, RZ ;
IADD3.X R13, R11, R4, RZ, P1, !PT ;
FADD R15, R19, R6 ;
STG.E [R2.64], R15 ;
LDG.E R6, [R12.64] ;
IADD3 R8, P1, R12, R5, RZ ;
IMAD.X R9, R13, 0x1, R4, P1 ;
FADD R17, R15, R6 ;
STG.E [R2.64], R17 ;
LDG.E R6, [R8.64] ;
IADD3 R10, P1, R8, R5, RZ ;
IMAD.X R11, R9, 0x1, R4, P1 ;
FADD R19, R17, R6 ;
STG.E [R2.64], R19 ;
LDG.E R6, [R10.64] ;
IADD3 R12, P1, R10, R5, RZ ;
IMAD.X R13, R11, 0x1, R4, P1 ;
FADD R15, R19, R6 ;
STG.E [R2.64], R15 ;
LDG.E R6, [R12.64] ;
IADD3 R8, P1, R12, R5, RZ ;
IMAD.X R9, R13, 0x1, R4, P1 ;
FADD R17, R15, R6 ;
STG.E [R2.64], R17 ;
LDG.E R6, [R8.64] ;
IADD3 R10, P1, R8, R5, RZ ;
IMAD.X R11, R9, 0x1, R4, P1 ;
FADD R19, R17, R6 ;
STG.E [R2.64], R19 ;
LDG.E R6, [R10.64] ;
IADD3 R12, P1, R10, R5, RZ ;
IMAD.X R13, R11, 0x1, R4, P1 ;
FADD R15, R19, R6 ;
STG.E [R2.64], R15 ;
LDG.E R6, [R12.64] ;
IADD3 R8, P1, R12, R5, RZ ;
IMAD.X R9, R13, 0x1, R4, P1 ;
FADD R17, R15, R6 ;
STG.E [R2.64], R17 ;
LDG.E R6, [R8.64] ;
IADD3 R10, P1, R8, R5, RZ ;
IADD3.X R11, R9, R4, RZ, P1, !PT ;
FADD R19, R17, R6 ;
STG.E [R2.64], R19 ;
LDG.E R6, [R10.64] ;
IADD3 R12, P1, R10, R5, RZ ;
IMAD.X R13, R11, 0x1, R4, P1 ;
FADD R21, R19, R6 ;
STG.E [R2.64], R21 ;
LDG.E R6, [R12.64] ;
IADD3 R14, P1, R12, R5, RZ ;
IMAD.X R15, R13, 0x1, R4, P1 ;
FADD R17, R21, R6 ;
STG.E [R2.64], R17 ;
LDG.E R6, [R14.64] ;
IADD3 R10, P1, R14, R5, RZ ;
IMAD.X R11, R15, 0x1, R4, P1 ;
FADD R19, R17, R6 ;
STG.E [R2.64], R19 ;
LDG.E R6, [R10.64] ;
IADD3 R0, R0, 0x10, RZ ;
IADD3 R12, P2, R10, R5, RZ ;
ISETP.GE.AND P1, PT, R0, R7, PT ;
IMAD.X R13, R11, 0x1, R4, P2 ;
FADD R9, R19, R6 ;
STG.E [R2.64], R9 ;
@!P1 BRA 0x400 ;
IADD3 R6, -R0, c[0x0][0x170], RZ ;
ISETP.GT.AND P1, PT, R6, 0x4, PT ;
@!P1 BRA 0xc40 ;
IMAD.MOV.U32 R6, RZ, RZ, R12 ;
IMAD.MOV.U32 R7, RZ, RZ, R13 ;
LDG.E R6, [R6.64] ;
IADD3 R10, P0, R12, R5, RZ ;
IADD3.X R11, R13, R4, RZ, P0, !PT ;
FADD R13, R9, R6 ;
STG.E [R2.64], R13 ;
LDG.E R12, [R10.64] ;
IADD3 R8, P0, R10, R5, RZ ;
IMAD.X R9, R11, 0x1, R4, P0 ;
FADD R15, R13, R12 ;
STG.E [R2.64], R15 ;
LDG.E R12, [R8.64] ;
IADD3 R6, P0, R8, R5, RZ ;
IMAD.X R7, R9, 0x1, R4, P0 ;
FADD R17, R15, R12 ;
STG.E [R2.64], R17 ;
LDG.E R12, [R6.64] ;
IADD3 R10, P0, R6, R5, RZ ;
IMAD.X R11, R7, 0x1, R4, P0 ;
FADD R13, R17, R12 ;
STG.E [R2.64], R13 ;
LDG.E R12, [R10.64] ;
IADD3 R8, P0, R10, R5, RZ ;
IMAD.X R9, R11, 0x1, R4, P0 ;
FADD R15, R13, R12 ;
STG.E [R2.64], R15 ;
LDG.E R12, [R8.64] ;
IADD3 R6, P0, R8, R5, RZ ;
IMAD.X R7, R9, 0x1, R4, P0 ;
FADD R17, R15, R12 ;
STG.E [R2.64], R17 ;
LDG.E R12, [R6.64] ;
IADD3 R10, P0, R6, R5, RZ ;
IMAD.X R11, R7, 0x1, R4, P0 ;
FADD R13, R17, R12 ;
STG.E [R2.64], R13 ;
LDG.E R12, [R10.64] ;
PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ;
IADD3 R0, R0, 0x8, RZ ;
FADD R9, R13, R12 ;
IADD3 R12, P1, R10, R5, RZ ;
STG.E [R2.64], R9 ;
IADD3.X R13, R11, R4, RZ, P1, !PT ;
ISETP.LT.OR P0, PT, R0, c[0x0][0x170], P0 ;
@!P0 EXIT ;
IMAD.MOV.U32 R6, RZ, RZ, R12 ;
IMAD.MOV.U32 R7, RZ, RZ, R13 ;
LDG.E R0, [R6.64] ;
IADD3 R10, P0, R12, R5, RZ ;
IMAD.X R11, R13, 0x1, R4, P0 ;
FADD R13, R0, R9 ;
STG.E [R2.64], R13 ;
LDG.E R0, [R10.64] ;
IADD3 R8, P0, R10, R5, RZ ;
IMAD.X R9, R11, 0x1, R4, P0 ;
FADD R15, R13, R0 ;
STG.E [R2.64], R15 ;
LDG.E R0, [R8.64] ;
IADD3 R6, P0, R8, R5, RZ ;
IMAD.X R7, R9, 0x1, R4, P0 ;
FADD R5, R15, R0 ;
STG.E [R2.64], R5 ;
LDG.E R6, [R6.64] ;
FADD R11, R5, R6 ;
STG.E [R2.64], R11 ;
EXIT ;
BRA 0xdb0;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
```
|
```amdasm
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z21createLaplacianKernelPfS_ii ; -- Begin function _Z21createLaplacianKernelPfS_ii
.globl _Z21createLaplacianKernelPfS_ii
.p2align 8
.type _Z21createLaplacianKernelPfS_ii,@function
_Z21createLaplacianKernelPfS_ii: ; @_Z21createLaplacianKernelPfS_ii
; %bb.0:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x24
s_load_b64 s[2:3], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_ashr_i32 s5, s3, 31
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
v_mov_b32_e32 v2, 0
s_mov_b32 s4, s3
s_cmp_gt_i32 s2, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
v_cmp_gt_u64_e32 vcc_lo, s[4:5], v[1:2]
s_cselect_b32 s5, -1, 0
s_mov_b32 s4, 0
s_and_b32 s5, vcc_lo, s5
s_and_saveexec_b32 s6, s5
s_cbranch_execz .LBB0_8
; %bb.1: ; %.lr.ph
s_load_b128 s[8:11], s[0:1], 0x0
v_lshlrev_b64 v[2:3], 2, v[1:2]
s_mov_b32 s0, 0
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s8, v2
v_add_co_ci_u32_e32 v1, vcc_lo, s9, v3, vcc_lo
v_add_co_u32 v2, vcc_lo, s10, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s11, v3, vcc_lo
.LBB0_2: ; =>This Inner Loop Header: Depth=1
s_cmp_lg_u32 s0, 0
s_cbranch_scc0 .LBB0_4
; %bb.3: ; in Loop: Header=BB0_2 Depth=1
s_ashr_i32 s5, s4, 31
s_mov_b32 s1, 0
s_lshl_b64 s[6:7], s[4:5], 2
s_delay_alu instid0(SALU_CYCLE_1)
v_add_co_u32 v4, vcc_lo, v0, s6
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
global_load_b32 v4, v[4:5], off
global_load_b32 v5, v[2:3], off
s_waitcnt vmcnt(0)
v_add_f32_e32 v4, v4, v5
s_branch .LBB0_5
.LBB0_4: ; in Loop: Header=BB0_2 Depth=1
s_mov_b32 s1, -1
; implicit-def: $vgpr4
.LBB0_5: ; %Flow
; in Loop: Header=BB0_2 Depth=1
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 vcc_lo, exec_lo, s1
s_cbranch_vccnz .LBB0_7
; %bb.6: ; in Loop: Header=BB0_2 Depth=1
global_load_b32 v4, v[0:1], off
.LBB0_7: ; in Loop: Header=BB0_2 Depth=1
s_add_i32 s0, s0, 1
s_add_i32 s4, s4, s3
s_cmp_lg_u32 s2, s0
s_waitcnt vmcnt(0)
global_store_b32 v[2:3], v4, off
s_cbranch_scc1 .LBB0_2
.LBB0_8: ; %.loopexit
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z21createLaplacianKernelPfS_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z21createLaplacianKernelPfS_ii, .Lfunc_end0-_Z21createLaplacianKernelPfS_ii
; -- End function
.section .AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 264
; NumSgprs: 18
; NumVgprs: 6
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 6
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object ; @__hip_cuid_
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0 ; 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z21createLaplacianKernelPfS_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z21createLaplacianKernelPfS_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
```
| 4,060 | 3,075 |
511 |
Convert the following CUDA host assembly code to AMD host assembly:
```cudaasm
.file "tmpxft_000dcd8c_00000000-6_createLaplacianKernel.cudafe1.cpp"
.text
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z45__device_stub__Z21createLaplacianKernelPfS_iiPfS_ii
.type _Z45__device_stub__Z21createLaplacianKernelPfS_iiPfS_ii, @function
_Z45__device_stub__Z21createLaplacianKernelPfS_iiPfS_ii:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z21createLaplacianKernelPfS_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z45__device_stub__Z21createLaplacianKernelPfS_iiPfS_ii, .-_Z45__device_stub__Z21createLaplacianKernelPfS_iiPfS_ii
.globl _Z21createLaplacianKernelPfS_ii
.type _Z21createLaplacianKernelPfS_ii, @function
_Z21createLaplacianKernelPfS_ii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z45__device_stub__Z21createLaplacianKernelPfS_iiPfS_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z21createLaplacianKernelPfS_ii, .-_Z21createLaplacianKernelPfS_ii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z21createLaplacianKernelPfS_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z21createLaplacianKernelPfS_ii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
```
|
```amdasm
.text
.file "createLaplacianKernel.hip"
.globl _Z36__device_stub__createLaplacianKernelPfS_ii # -- Begin function _Z36__device_stub__createLaplacianKernelPfS_ii
.type _Z36__device_stub__createLaplacianKernelPfS_ii,@function
_Z36__device_stub__createLaplacianKernelPfS_ii: # @_Z36__device_stub__createLaplacianKernelPfS_ii
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $112, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 40(%rsp), %rax
movq %rdi, (%rax)
leaq 32(%rsp), %rdi
movq %rsi, (%rdi)
leaq 12(%rsp), %rsi
movl %edx, (%rsi)
leaq 8(%rsp), %rdx
movl %ecx, (%rdx)
leaq 80(%rsp), %rbx
movq %rax, (%rbx)
movq %rdi, 8(%rbx)
movq %rsi, 16(%rbx)
movq %rdx, 24(%rbx)
leaq 64(%rsp), %r14
leaq 48(%rsp), %r15
leaq 24(%rsp), %r12
leaq 16(%rsp), %r13
movq %r14, %rdi
movq %r15, %rsi
movq %r12, %rdx
movq %r13, %rcx
callq __hipPopCallConfiguration
movq (%r14), %rsi
movl 8(%r14), %edx
movq (%r15), %rcx
movl 8(%r15), %r8d
movl $_Z21createLaplacianKernelPfS_ii, %edi
movq %rbx, %r9
pushq (%r13)
.cfi_adjust_cfa_offset 8
pushq (%r12)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $128, %rsp
.cfi_adjust_cfa_offset -128
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z36__device_stub__createLaplacianKernelPfS_ii, .Lfunc_end0-_Z36__device_stub__createLaplacianKernelPfS_ii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, %rdi
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z21createLaplacianKernelPfS_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z21createLaplacianKernelPfS_ii,@object # @_Z21createLaplacianKernelPfS_ii
.section .rodata,"a",@progbits
.globl _Z21createLaplacianKernelPfS_ii
.p2align 3, 0x0
_Z21createLaplacianKernelPfS_ii:
.quad _Z36__device_stub__createLaplacianKernelPfS_ii
.size _Z21createLaplacianKernelPfS_ii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z21createLaplacianKernelPfS_ii"
.size .L__unnamed_1, 32
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z36__device_stub__createLaplacianKernelPfS_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z21createLaplacianKernelPfS_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
```
| 1,969 | 2,157 |
512 |
Convert the following CUDA device assembly code to AMD device assembly:
```cudaasm
code for sm_80
Function : _Z8maxValuePiS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ;
S2R R5, SR_TID.X ;
HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ;
ULDC.64 UR4, c[0x0][0x118] ;
S2R R4, SR_CTAID.X ;
IMAD R2, R4, c[0x0][0x0], R5 ;
IMAD.WIDE.U32 R2, R2, R7, c[0x0][0x160] ;
LDG.E R2, [R2.64] ;
ISETP.GT.U32.AND P1, PT, R5.reuse, 0x1, PT ;
BSSY B0, 0x110 ;
ISETP.NE.AND P0, PT, R5, RZ, PT ;
STS [R5.X4], R2 ;
@P1 BRA 0x100 ;
LDS R3, [R5.X4+0x8] ;
ISETP.GE.AND P1, PT, R2, R3, PT ;
@!P1 STS [R5.X4], R3 ;
BSYNC B0 ;
BAR.SYNC.DEFER_BLOCKING 0x0 ;
BSSY B0, 0x190 ;
@P0 BRA 0x180 ;
LDS R0, [R5.X4] ;
LDS R3, [0x4] ;
ISETP.GE.AND P1, PT, R0, R3, PT ;
@!P1 STS [R5.X4], R3 ;
BSYNC B0 ;
BAR.SYNC.DEFER_BLOCKING 0x0 ;
@P0 EXIT ;
LDS R5, [RZ] ;
IMAD.WIDE.U32 R2, R4, R7, c[0x0][0x168] ;
STG.E [R2.64], R5 ;
EXIT ;
BRA 0x1f0;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
```
|
```amdasm
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z8maxValuePiS_ ; -- Begin function _Z8maxValuePiS_
.globl _Z8maxValuePiS_
.p2align 8
.type _Z8maxValuePiS_,@function
_Z8maxValuePiS_: ; @_Z8maxValuePiS_
; %bb.0:
s_clause 0x1
s_load_b32 s5, s[0:1], 0x1c
s_load_b128 s[0:3], s[0:1], 0x0
s_mov_b32 s4, s15
s_waitcnt lgkmcnt(0)
s_and_b32 s5, s5, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s4, s5, v[0:1]
v_mov_b32_e32 v2, 0
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v1, vcc_lo, s0, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
s_mov_b32 s0, 2
global_load_b32 v2, v[1:2], off
v_lshlrev_b32_e32 v1, 2, v0
s_waitcnt vmcnt(0)
ds_store_b32 v1, v2
.LBB0_1: ; =>This Inner Loop Header: Depth=1
s_mov_b32 s1, exec_lo
v_cmpx_gt_u32_e64 s0, v0
s_cbranch_execz .LBB0_4
; %bb.2: ; in Loop: Header=BB0_1 Depth=1
v_lshl_add_u32 v2, s0, 2, v1
ds_load_b32 v3, v1
ds_load_b32 v2, v2
s_waitcnt lgkmcnt(0)
v_cmp_lt_i32_e32 vcc_lo, v3, v2
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_4
; %bb.3: ; in Loop: Header=BB0_1 Depth=1
ds_store_b32 v1, v2
.LBB0_4: ; in Loop: Header=BB0_1 Depth=1
s_or_b32 exec_lo, exec_lo, s1
s_lshr_b32 s1, s0, 1
s_cmp_lt_u32 s0, 2
s_mov_b32 s0, s1
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc0 .LBB0_1
; %bb.5:
s_mov_b32 s5, 0
s_mov_b32 s0, exec_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB0_7
; %bb.6:
v_mov_b32_e32 v0, 0
s_lshl_b64 s[0:1], s[4:5], 2
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s0, s2, s0
s_addc_u32 s1, s3, s1
ds_load_b32 v1, v0
s_waitcnt lgkmcnt(0)
global_store_b32 v0, v1, s[0:1]
.LBB0_7:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z8maxValuePiS_
.amdhsa_group_segment_fixed_size 16
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z8maxValuePiS_, .Lfunc_end0-_Z8maxValuePiS_
; -- End function
.section .AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 272
; NumSgprs: 18
; NumVgprs: 4
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 16 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 4
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object ; @__hip_cuid_
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0 ; 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 16
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z8maxValuePiS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z8maxValuePiS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
```
| 573 | 2,774 |
513 |
Convert the following CUDA host assembly code to AMD host assembly:
```cudaasm
.file "tmpxft_0016c829_00000000-6_kernel.cudafe1.cpp"
.text
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z29__device_stub__Z8maxValuePiS_PiS_
.type _Z29__device_stub__Z8maxValuePiS_PiS_, @function
_Z29__device_stub__Z8maxValuePiS_PiS_:
.LFB2082:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z8maxValuePiS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z29__device_stub__Z8maxValuePiS_PiS_, .-_Z29__device_stub__Z8maxValuePiS_PiS_
.globl _Z8maxValuePiS_
.type _Z8maxValuePiS_, @function
_Z8maxValuePiS_:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z8maxValuePiS_PiS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z8maxValuePiS_, .-_Z8maxValuePiS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Max: %d\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
addq $-128, %rsp
.cfi_def_cfa_offset 160
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
movl $0, %edi
call time@PLT
movl %eax, %edi
call srand@PLT
movl $1, 64(%rsp)
movl $3, 68(%rsp)
movl $21, 72(%rsp)
movl $55, 76(%rsp)
movl $2, 80(%rsp)
movl $5, 84(%rsp)
movl $6, 88(%rsp)
movl $8, 92(%rsp)
movl $87, 96(%rsp)
movl $6, 100(%rsp)
movl $5, 104(%rsp)
movl $0, 108(%rsp)
leaq 8(%rsp), %rdi
movl $48, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $16, %esi
call cudaMalloc@PLT
leaq 64(%rsp), %rsi
movl $1, %ecx
movl $48, %edx
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $4, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $3, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 40(%rsp), %rdx
movl $1, %ecx
movq 28(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L17
.L12:
call cudaDeviceSynchronize@PLT
leaq 52(%rsp), %rbx
movl $2, %ecx
movl $12, %edx
movq 16(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
leaq 64(%rsp), %r12
leaq .LC0(%rip), %rbp
.L13:
movl (%rbx), %edx
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %r12, %rbx
jne .L13
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L18
movl $0, %eax
subq $-128, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L17:
.cfi_restore_state
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z29__device_stub__Z8maxValuePiS_PiS_
jmp .L12
.L18:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC1:
.string "_Z8maxValuePiS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z8maxValuePiS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
```
|
```amdasm
.text
.file "kernel.hip"
.globl _Z23__device_stub__maxValuePiS_ # -- Begin function _Z23__device_stub__maxValuePiS_
.type _Z23__device_stub__maxValuePiS_,@function
_Z23__device_stub__maxValuePiS_: # @_Z23__device_stub__maxValuePiS_
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $80, %rsp
.cfi_def_cfa_offset 128
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 24(%rsp), %rax
movq %rdi, (%rax)
leaq 16(%rsp), %rcx
movq %rsi, (%rcx)
leaq 64(%rsp), %rbx
movq %rax, (%rbx)
movq %rcx, 8(%rbx)
leaq 48(%rsp), %r14
leaq 32(%rsp), %r15
leaq 8(%rsp), %r12
movq %rsp, %r13
movq %r14, %rdi
movq %r15, %rsi
movq %r12, %rdx
movq %r13, %rcx
callq __hipPopCallConfiguration
movq (%r14), %rsi
movl 8(%r14), %edx
movq (%r15), %rcx
movl 8(%r15), %r8d
movl $_Z8maxValuePiS_, %edi
movq %rbx, %r9
pushq (%r13)
.cfi_adjust_cfa_offset 8
pushq (%r12)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $96, %rsp
.cfi_adjust_cfa_offset -96
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z23__device_stub__maxValuePiS_, .Lfunc_end0-_Z23__device_stub__maxValuePiS_
.cfi_endproc
# -- End function
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0 # -- Begin function main
.LCPI1_0:
.long 1 # 0x1
.long 3 # 0x3
.long 21 # 0x15
.long 55 # 0x37
.LCPI1_1:
.long 2 # 0x2
.long 5 # 0x5
.long 6 # 0x6
.long 8 # 0x8
.LCPI1_2:
.long 87 # 0x57
.long 6 # 0x6
.long 5 # 0x5
.long 0 # 0x0
.text
.globl main
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $88, %rsp
.cfi_def_cfa_offset 112
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
xorl %edi, %edi
callq time
movl %eax, %edi
callq srand
movaps .LCPI1_0(%rip), %xmm0 # xmm0 = [1,3,21,55]
leaq 32(%rsp), %rbx
movaps %xmm0, (%rbx)
movaps .LCPI1_1(%rip), %xmm0 # xmm0 = [2,5,6,8]
movaps %xmm0, 16(%rbx)
movaps .LCPI1_2(%rip), %xmm0 # xmm0 = [87,6,5,0]
movaps %xmm0, 32(%rbx)
leaq 8(%rsp), %r14
movl $48, %esi
movq %r14, %rdi
callq hipMalloc
movq %rsp, %rdi
movl $16, %esi
callq hipMalloc
movq (%r14), %rdi
movl $48, %edx
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $4294967299, %rdi # imm = 0x100000003
leaq 1(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq 8(%rsp), %rdi
movq (%rsp), %rsi
callq _Z23__device_stub__maxValuePiS_
.LBB1_2:
callq hipDeviceSynchronize
movq (%rsp), %rsi
leaq 20(%rsp), %rdi
movl $12, %edx
movl $2, %ecx
callq hipMemcpy
xorl %ebx, %ebx
.LBB1_3: # =>This Inner Loop Header: Depth=1
movl 20(%rsp,%rbx,4), %esi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
incq %rbx
cmpq $3, %rbx
jne .LBB1_3
# %bb.4:
movq 8(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $88, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, %rdi
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8maxValuePiS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z8maxValuePiS_,@object # @_Z8maxValuePiS_
.section .rodata,"a",@progbits
.globl _Z8maxValuePiS_
.p2align 3, 0x0
_Z8maxValuePiS_:
.quad _Z23__device_stub__maxValuePiS_
.size _Z8maxValuePiS_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Max: %d\n"
.size .L.str, 9
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z8maxValuePiS_"
.size .L__unnamed_1, 16
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z23__device_stub__maxValuePiS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z8maxValuePiS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
```
| 2,861 | 3,039 |
514 |
Convert the following CUDA device assembly code to AMD device assembly:
```cudaasm
code for sm_80
Function : _Z12pcmul_kernelP6float2S0_Pfii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
MOV R1, c[0x0][0x28] ;
S2R R6, SR_CTAID.X ;
ULDC.64 UR4, c[0x0][0x178] ;
UIMAD UR4, UR5, UR4, URZ ;
S2R R3, SR_TID.X ;
IMAD R6, R6, c[0x0][0x0], R3 ;
ISETP.GE.U32.AND P0, PT, R6, UR4, PT ;
@P0 EXIT ;
HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ;
MOV R7, 0x8 ;
ULDC.64 UR4, c[0x0][0x118] ;
IMAD.WIDE.U32 R2, R6, R7, c[0x0][0x168] ;
IMAD.WIDE.U32 R4, R6.reuse, R5, c[0x0][0x170] ;
LDG.E.64 R2, [R2.64] ;
LDG.E R4, [R4.64] ;
IMAD.WIDE.U32 R6, R6, R7, c[0x0][0x160] ;
FMUL R9, R3, R4.reuse ;
FMUL R8, R2, R4 ;
STG.E.64 [R6.64], R8 ;
EXIT ;
BRA 0x140;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
```
|
```amdasm
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z12pcmul_kernelP15HIP_vector_typeIfLj2EES1_Pfii ; -- Begin function _Z12pcmul_kernelP15HIP_vector_typeIfLj2EES1_Pfii
.globl _Z12pcmul_kernelP15HIP_vector_typeIfLj2EES1_Pfii
.p2align 8
.type _Z12pcmul_kernelP15HIP_vector_typeIfLj2EES1_Pfii,@function
_Z12pcmul_kernelP15HIP_vector_typeIfLj2EES1_Pfii: ; @_Z12pcmul_kernelP15HIP_vector_typeIfLj2EES1_Pfii
; %bb.0:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x2c
s_load_b64 s[2:3], s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_mul_i32 s2, s3, s2
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
s_delay_alu instid0(VALU_DEP_1)
v_cmp_gt_u32_e32 vcc_lo, s2, v1
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_2
; %bb.1:
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
v_mov_b32_e32 v2, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[3:4], 3, v[1:2]
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v5, vcc_lo, s6, v3
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e32 v6, vcc_lo, s7, v4, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_4)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
v_add_co_u32 v2, vcc_lo, s4, v3
global_load_b64 v[5:6], v[5:6], off
global_load_b32 v1, v[0:1], off
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v4, vcc_lo
s_waitcnt vmcnt(0)
v_mul_f32_e32 v0, v5, v1
v_mul_f32_e32 v1, v6, v1
global_store_b64 v[2:3], v[0:1], off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z12pcmul_kernelP15HIP_vector_typeIfLj2EES1_Pfii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z12pcmul_kernelP15HIP_vector_typeIfLj2EES1_Pfii, .Lfunc_end0-_Z12pcmul_kernelP15HIP_vector_typeIfLj2EES1_Pfii
; -- End function
.section .AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 200
; NumSgprs: 18
; NumVgprs: 7
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 7
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object ; @__hip_cuid_
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0 ; 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z12pcmul_kernelP15HIP_vector_typeIfLj2EES1_Pfii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z12pcmul_kernelP15HIP_vector_typeIfLj2EES1_Pfii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
```
| 464 | 2,831 |
515 |
Convert the following CUDA host assembly code to AMD host assembly:
```cudaasm
.file "tmpxft_001b3799_00000000-6_complex2.cudafe1.cpp"
.text
.globl _ZSt21ios_base_library_initv
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3998:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3998:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z5pcmulP6float2Pfii
.type _Z5pcmulP6float2Pfii, @function
_Z5pcmulP6float2Pfii:
.LFB3993:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $8, %rsp
.cfi_def_cfa_offset 48
movq %rdi, %r12
movl %edx, %eax
imull %ecx, %eax
cltq
movq %rax, %rdi
shrq $60, %rdi
jne .L4
movq %rsi, %r13
movl %edx, %ebp
movl %ecx, %ebx
leaq 0(,%rax,8), %rdi
call _Znam@PLT
movq %rax, %r10
testl %ebp, %ebp
jle .L3
movl $0, %r9d
movl $0, %r8d
movslq %ebx, %rdi
jmp .L6
.L4:
call __cxa_throw_bad_array_new_length@PLT
.L8:
movslq %r9d, %rax
leaq 0(,%rax,8), %rdx
leaq (%r12,%rdx), %rcx
leaq 0(%r13,%rax,4), %rsi
addq %r10, %rdx
movl $0, %eax
.L7:
movss (%rsi,%rax,4), %xmm0
movaps %xmm0, %xmm1
mulss 4(%rcx,%rax,8), %xmm1
mulss (%rcx,%rax,8), %xmm0
movss %xmm0, (%rdx,%rax,8)
movss %xmm1, 4(%rdx,%rax,8)
addq $1, %rax
cmpq %rdi, %rax
jne .L7
.L9:
addl $1, %r8d
addl %ebx, %r9d
cmpl %r8d, %ebp
je .L3
.L6:
testl %ebx, %ebx
jg .L8
jmp .L9
.L3:
movq %r10, %rax
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3993:
.size _Z5pcmulP6float2Pfii, .-_Z5pcmulP6float2Pfii
.globl _Z45__device_stub__Z12pcmul_kernelP6float2S0_PfiiP6float2S0_Pfii
.type _Z45__device_stub__Z12pcmul_kernelP6float2S0_PfiiP6float2S0_Pfii, @function
_Z45__device_stub__Z12pcmul_kernelP6float2S0_PfiiP6float2S0_Pfii:
.LFB4020:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L16
.L12:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L17
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L16:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z12pcmul_kernelP6float2S0_Pfii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L12
.L17:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4020:
.size _Z45__device_stub__Z12pcmul_kernelP6float2S0_PfiiP6float2S0_Pfii, .-_Z45__device_stub__Z12pcmul_kernelP6float2S0_PfiiP6float2S0_Pfii
.globl _Z12pcmul_kernelP6float2S0_Pfii
.type _Z12pcmul_kernelP6float2S0_Pfii, @function
_Z12pcmul_kernelP6float2S0_Pfii:
.LFB4021:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z45__device_stub__Z12pcmul_kernelP6float2S0_PfiiP6float2S0_Pfii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4021:
.size _Z12pcmul_kernelP6float2S0_Pfii, .-_Z12pcmul_kernelP6float2S0_Pfii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "copy to device "
.LC1:
.string "kernel compute "
.LC2:
.string "copy to host "
.text
.globl _Z9pcmul_gpuP6float2Pfii
.type _Z9pcmul_gpuP6float2Pfii, @function
_Z9pcmul_gpuP6float2Pfii:
.LFB3994:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $120, %rsp
.cfi_def_cfa_offset 176
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
movl %edx, %ebx
imull %ecx, %ebx
movslq %ebx, %rbx
movq %rbx, %rax
shrq $60, %rax
jne .L21
movq %rdi, %r14
movq %rsi, %r15
movl %edx, %r12d
movl %ecx, %r13d
leaq 0(,%rbx,8), %rbp
movq %rbp, %rdi
call _Znam@PLT
movq %rax, (%rsp)
leaq 24(%rsp), %rdi
movq %rbp, %rsi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movq %rbp, %rsi
call cudaMalloc@PLT
salq $2, %rbx
leaq 32(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq 64(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
movl $1, %ecx
movq %rbp, %rdx
movq %r14, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %rbx, %rdx
movq %r15, %rsi
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
leaq 80(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
imulq $1000000, 64(%rsp), %r15
movq 88(%rsp), %rbx
imulq $1000000, 80(%rsp), %rax
subq 72(%rsp), %rax
movq %rax, 8(%rsp)
movl $15, %edx
leaq .LC0(%rip), %rsi
leaq _ZSt4cout(%rip), %r14
movq %r14, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq 8(%rsp), %rax
leaq (%rbx,%rax), %rsi
subq %r15, %rsi
movq %r14, %rdi
call _ZNSo9_M_insertIyEERSoT_@PLT
movq %rax, %rbx
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %r14
testq %r14, %r14
je .L40
cmpb $0, 56(%r14)
je .L24
movzbl 67(%r14), %esi
.L25:
movsbl %sil, %esi
movq %rbx, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
leaq 64(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
movl %r13d, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl %r12d, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 52(%rsp), %rdx
movl $1, %ecx
movq 40(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L41
.L26:
leaq 80(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
imulq $1000000, 64(%rsp), %r13
movq 88(%rsp), %rbx
imulq $1000000, 80(%rsp), %r14
subq 72(%rsp), %r14
movl $15, %edx
leaq .LC1(%rip), %rsi
leaq _ZSt4cout(%rip), %r12
movq %r12, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
leaq (%rbx,%r14), %rsi
subq %r13, %rsi
movq %r12, %rdi
call _ZNSo9_M_insertIyEERSoT_@PLT
movq %rax, %rbx
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %r12
testq %r12, %r12
je .L42
cmpb $0, 56(%r12)
je .L31
movzbl 67(%r12), %esi
.L32:
movsbl %sil, %esi
movq %rbx, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
leaq 64(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
movl $2, %ecx
movq %rbp, %rdx
movq 24(%rsp), %rsi
movq (%rsp), %rdi
call cudaMemcpy@PLT
leaq 80(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
imulq $1000000, 64(%rsp), %r12
movq 88(%rsp), %rbx
imulq $1000000, 80(%rsp), %r13
subq 72(%rsp), %r13
movl $13, %edx
leaq .LC2(%rip), %rsi
leaq _ZSt4cout(%rip), %rbp
movq %rbp, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
leaq (%rbx,%r13), %rsi
subq %r12, %rsi
movq %rbp, %rdi
call _ZNSo9_M_insertIyEERSoT_@PLT
movq %rax, %rbx
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %rbp
testq %rbp, %rbp
je .L43
cmpb $0, 56(%rbp)
je .L35
movzbl 67(%rbp), %esi
.L36:
movsbl %sil, %esi
movq %rbx, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L44
movq (%rsp), %rax
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L40:
.cfi_restore_state
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L45
call _ZSt16__throw_bad_castv@PLT
.L45:
call __stack_chk_fail@PLT
.L24:
movq %r14, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r14), %rax
movl $10, %esi
movq %r14, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L25
.L21:
movq 104(%rsp), %rax
subq %fs:40, %rax
je .L28
call __stack_chk_fail@PLT
.L28:
call __cxa_throw_bad_array_new_length@PLT
.L41:
movl %r13d, %r8d
movl %r12d, %ecx
movq 32(%rsp), %rdx
movq 16(%rsp), %rsi
movq 24(%rsp), %rdi
call _Z45__device_stub__Z12pcmul_kernelP6float2S0_PfiiP6float2S0_Pfii
jmp .L26
.L42:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L46
call _ZSt16__throw_bad_castv@PLT
.L46:
call __stack_chk_fail@PLT
.L31:
movq %r12, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r12), %rax
movl $10, %esi
movq %r12, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L32
.L43:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L47
call _ZSt16__throw_bad_castv@PLT
.L47:
call __stack_chk_fail@PLT
.L35:
movq %rbp, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq 0(%rbp), %rax
movl $10, %esi
movq %rbp, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L36
.L44:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3994:
.size _Z9pcmul_gpuP6float2Pfii, .-_Z9pcmul_gpuP6float2Pfii
.globl main
.type main, @function
main:
.LFB3995:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $48, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movl $4194304, %edi
call _Znam@PLT
movq %rax, %rbp
movl $2097152, %edi
call _Znam@PLT
movq %rax, %rbx
movq %rbp, %rdx
movq %rax, %rcx
movl $0, %esi
.L49:
movl $0, %eax
pxor %xmm0, %xmm0
cvtsi2ssl %esi, %xmm0
.L50:
movss %xmm0, (%rdx,%rax,8)
pxor %xmm1, %xmm1
cvtsi2ssl %eax, %xmm1
movss %xmm1, 4(%rdx,%rax,8)
movss %xmm0, (%rcx,%rax,4)
addq $1, %rax
cmpq $512, %rax
jne .L50
addl $1, %esi
addq $4096, %rdx
addq $2048, %rcx
cmpl $1024, %esi
jne .L49
movq %rsp, %r12
movl $0, %esi
movq %r12, %rdi
call gettimeofday@PLT
movl $512, %ecx
movl $1024, %edx
movq %rbx, %rsi
movq %rbp, %rdi
call _Z5pcmulP6float2Pfii
leaq 16(%rsp), %r14
movl $0, %esi
movq %r14, %rdi
call gettimeofday@PLT
imulq $1000000, 16(%rsp), %rsi
subq 8(%rsp), %rsi
addq 24(%rsp), %rsi
imulq $1000000, (%rsp), %rax
subq %rax, %rsi
leaq _ZSt4cout(%rip), %r13
movq %r13, %rdi
call _ZNSo9_M_insertIyEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $0, %esi
movq %r12, %rdi
call gettimeofday@PLT
movl $512, %ecx
movl $1024, %edx
movq %rbx, %rsi
movq %rbp, %rdi
call _Z9pcmul_gpuP6float2Pfii
movq %rax, %r12
movl $0, %esi
movq %r14, %rdi
call gettimeofday@PLT
imulq $1000000, 16(%rsp), %rsi
subq 8(%rsp), %rsi
addq 24(%rsp), %rsi
imulq $1000000, (%rsp), %rax
subq %rax, %rsi
movq %r13, %rdi
call _ZNSo9_M_insertIyEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq %rbp, %rdi
call _ZdaPv@PLT
movq %rbx, %rdi
call _ZdaPv@PLT
testq %r12, %r12
je .L52
movq %r12, %rdi
call _ZdaPv@PLT
.L52:
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L56
movl $0, %eax
addq $48, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L56:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3995:
.size main, .-main
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC3:
.string "_Z12pcmul_kernelP6float2S0_Pfii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB4023:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z12pcmul_kernelP6float2S0_Pfii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4023:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
```
|
```amdasm
.text
.file "complex2.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z5pcmulP15HIP_vector_typeIfLj2EEPfii # -- Begin function _Z5pcmulP15HIP_vector_typeIfLj2EEPfii
.type _Z5pcmulP15HIP_vector_typeIfLj2EEPfii,@function
_Z5pcmulP15HIP_vector_typeIfLj2EEPfii: # @_Z5pcmulP15HIP_vector_typeIfLj2EEPfii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
pushq %rax
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %ecx, %ebx
movl %edx, %ebp
movq %rsi, %r14
movq %rdi, %r15
movl %ecx, %eax
imull %edx, %eax
leaq (,%rax,8), %rcx
testl %eax, %eax
movq $-1, %rdi
cmovnsq %rcx, %rdi
callq _Znam
testl %ebp, %ebp
jle .LBB0_6
# %bb.1: # %.preheader.lr.ph
movl %ebp, %ecx
movl %ebx, %edx
xorl %esi, %esi
xorl %edi, %edi
.LBB0_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB0_4 Depth 2
testl %ebx, %ebx
jle .LBB0_5
# %bb.3: # %.lr.ph
# in Loop: Header=BB0_2 Depth=1
movl %esi, %r10d
leaq (%rax,%r10,8), %r8
leaq (%r14,%r10,4), %r9
leaq (%r15,%r10,8), %r10
xorl %r11d, %r11d
.LBB0_4: # Parent Loop BB0_2 Depth=1
# => This Inner Loop Header: Depth=2
movss (%r9,%r11,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
movss (%r10,%r11,8), %xmm1 # xmm1 = mem[0],zero,zero,zero
mulss %xmm0, %xmm1
mulss 4(%r10,%r11,8), %xmm0
movss %xmm1, (%rsp)
movss %xmm0, 4(%rsp)
movsd (%rsp), %xmm0 # xmm0 = mem[0],zero
movsd %xmm0, (%r8,%r11,8)
incq %r11
cmpq %r11, %rdx
jne .LBB0_4
.LBB0_5: # %._crit_edge
# in Loop: Header=BB0_2 Depth=1
incq %rdi
addl %ebx, %esi
cmpq %rcx, %rdi
jne .LBB0_2
.LBB0_6: # %._crit_edge37
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z5pcmulP15HIP_vector_typeIfLj2EEPfii, .Lfunc_end0-_Z5pcmulP15HIP_vector_typeIfLj2EEPfii
.cfi_endproc
# -- End function
.globl _Z27__device_stub__pcmul_kernelP15HIP_vector_typeIfLj2EES1_Pfii # -- Begin function _Z27__device_stub__pcmul_kernelP15HIP_vector_typeIfLj2EES1_Pfii
.type _Z27__device_stub__pcmul_kernelP15HIP_vector_typeIfLj2EES1_Pfii,@function
_Z27__device_stub__pcmul_kernelP15HIP_vector_typeIfLj2EES1_Pfii: # @_Z27__device_stub__pcmul_kernelP15HIP_vector_typeIfLj2EES1_Pfii
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $128, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 40(%rsp), %rax
movq %rdi, (%rax)
leaq 32(%rsp), %rdi
movq %rsi, (%rdi)
leaq 24(%rsp), %rsi
movq %rdx, (%rsi)
leaq 4(%rsp), %rdx
movl %ecx, (%rdx)
movq %rsp, %rcx
movl %r8d, (%rcx)
leaq 80(%rsp), %rbx
movq %rax, (%rbx)
movq %rdi, 8(%rbx)
movq %rsi, 16(%rbx)
movq %rdx, 24(%rbx)
movq %rcx, 32(%rbx)
leaq 64(%rsp), %r14
leaq 48(%rsp), %r15
leaq 16(%rsp), %r12
leaq 8(%rsp), %r13
movq %r14, %rdi
movq %r15, %rsi
movq %r12, %rdx
movq %r13, %rcx
callq __hipPopCallConfiguration
movq (%r14), %rsi
movl 8(%r14), %edx
movq (%r15), %rcx
movl 8(%r15), %r8d
movl $_Z12pcmul_kernelP15HIP_vector_typeIfLj2EES1_Pfii, %edi
movq %rbx, %r9
pushq (%r13)
.cfi_adjust_cfa_offset 8
pushq (%r12)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $144, %rsp
.cfi_adjust_cfa_offset -144
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z27__device_stub__pcmul_kernelP15HIP_vector_typeIfLj2EES1_Pfii, .Lfunc_end1-_Z27__device_stub__pcmul_kernelP15HIP_vector_typeIfLj2EES1_Pfii
.cfi_endproc
# -- End function
.globl _Z9pcmul_gpuP15HIP_vector_typeIfLj2EEPfii # -- Begin function _Z9pcmul_gpuP15HIP_vector_typeIfLj2EEPfii
.type _Z9pcmul_gpuP15HIP_vector_typeIfLj2EEPfii,@function
_Z9pcmul_gpuP15HIP_vector_typeIfLj2EEPfii: # @_Z9pcmul_gpuP15HIP_vector_typeIfLj2EEPfii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $88, %rsp
.cfi_def_cfa_offset 144
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %ecx, 12(%rsp) # 4-byte Spill
movl %edx, %ebp
movq %rsi, 32(%rsp) # 8-byte Spill
movq %rdi, %r12
movl %ecx, %eax
imull %edx, %eax
movslq %eax, %rbx
leaq (,%rbx,8), %r14
testl %ebx, %ebx
movq $-1, %rdi
cmovnsq %r14, %rdi
callq _Znam
movq %rax, 48(%rsp) # 8-byte Spill
movq %rsp, %rdi
movq %r14, %rsi
callq hipMalloc
leaq 24(%rsp), %r15
movq %r15, %rdi
movq %r14, %rsi
callq hipMalloc
shlq $2, %rbx
leaq 16(%rsp), %r13
movq %r13, %rdi
movq %rbx, %rsi
callq hipMalloc
leaq 56(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
movq (%r15), %rdi
movq %r12, %rsi
movq %r14, 40(%rsp) # 8-byte Spill
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
movq (%r13), %rdi
movq 32(%rsp), %rsi # 8-byte Reload
movq %rbx, %rdx
movl $1, %ecx
callq hipMemcpy
leaq 72(%rsp), %rbx
movq %rbx, %rdi
xorl %esi, %esi
callq gettimeofday
movq (%rbx), %r15
movq 8(%rbx), %rbx
leaq 56(%rsp), %r12
subq (%r12), %r15
subq 8(%r12), %rbx
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $15, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
imulq $1000000, %r15, %rsi # imm = 0xF4240
addq %rbx, %rsi
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIyEERSoT_
movq %rax, %rbx
movq (%rax), %rax
movq -24(%rax), %rdi
addq %rbx, %rdi
movl $10, %esi
callq _ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
movsbl %al, %esi
movq %rbx, %rdi
movl 12(%rsp), %ebx # 4-byte Reload
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq %r12, %rdi
xorl %esi, %esi
callq gettimeofday
movl %ebp, %edi
btsq $32, %rdi
movl %ebx, %edx
btsq $32, %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_2
# %bb.1:
movq (%rsp), %rdi
movq 24(%rsp), %rsi
movq 16(%rsp), %rdx
movl %ebp, %ecx
movl %ebx, %r8d
callq _Z27__device_stub__pcmul_kernelP15HIP_vector_typeIfLj2EES1_Pfii
.LBB2_2:
leaq 72(%rsp), %r15
movq %r15, %rdi
xorl %esi, %esi
callq gettimeofday
movq (%r15), %rbx
movq 8(%r15), %r13
leaq 56(%rsp), %r12
subq (%r12), %rbx
subq 8(%r12), %r13
movl $_ZSt4cout, %edi
movl $.L.str.1, %esi
movl $15, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
imulq $1000000, %rbx, %rsi # imm = 0xF4240
addq %r13, %rsi
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIyEERSoT_
movq %rax, %rbx
movq (%rax), %rax
movq -24(%rax), %rdi
addq %rbx, %rdi
movl $10, %esi
callq _ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
movsbl %al, %esi
movq %rbx, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq %r12, %rdi
xorl %esi, %esi
callq gettimeofday
movq (%rsp), %rsi
movq 48(%rsp), %r13 # 8-byte Reload
movq %r13, %rdi
movq 40(%rsp), %rdx # 8-byte Reload
movl $2, %ecx
callq hipMemcpy
movq %r15, %rdi
xorl %esi, %esi
callq gettimeofday
movq (%r15), %rbx
movq 8(%r15), %r14
subq (%r12), %rbx
subq 8(%r12), %r14
movl $_ZSt4cout, %edi
movl $.L.str.2, %esi
movl $13, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
imulq $1000000, %rbx, %rsi # imm = 0xF4240
addq %r14, %rsi
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIyEERSoT_
movq %rax, %rbx
movq (%rax), %rax
movq -24(%rax), %rdi
addq %rbx, %rdi
movl $10, %esi
callq _ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
movsbl %al, %esi
movq %rbx, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq (%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq %r13, %rax
addq $88, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size _Z9pcmul_gpuP15HIP_vector_typeIfLj2EEPfii, .Lfunc_end2-_Z9pcmul_gpuP15HIP_vector_typeIfLj2EEPfii
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $32, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $4194304, %edi # imm = 0x400000
callq _Znam
movq %rax, %rbx
movl $2097152, %edi # imm = 0x200000
callq _Znam
movq %rax, %r14
xorl %eax, %eax
movq %rbx, %rcx
movq %r14, %rdx
.LBB3_1: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB3_2 Depth 2
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
xorl %esi, %esi
.LBB3_2: # Parent Loop BB3_1 Depth=1
# => This Inner Loop Header: Depth=2
xorps %xmm1, %xmm1
cvtsi2ss %esi, %xmm1
movss %xmm0, (%rsp)
movss %xmm1, 4(%rsp)
movsd (%rsp), %xmm1 # xmm1 = mem[0],zero
movsd %xmm1, (%rcx,%rsi,8)
movss %xmm0, (%rdx,%rsi,4)
incq %rsi
cmpq $512, %rsi # imm = 0x200
jne .LBB3_2
# %bb.3: # in Loop: Header=BB3_1 Depth=1
incq %rax
addq $2048, %rdx # imm = 0x800
addq $4096, %rcx # imm = 0x1000
cmpq $1024, %rax # imm = 0x400
jne .LBB3_1
# %bb.4:
movq %rsp, %r15
movq %r15, %rdi
xorl %esi, %esi
callq gettimeofday
movq %rbx, %rdi
movq %r14, %rsi
movl $1024, %edx # imm = 0x400
movl $512, %ecx # imm = 0x200
callq _Z5pcmulP15HIP_vector_typeIfLj2EEPfii
leaq 16(%rsp), %r12
movq %r12, %rdi
xorl %esi, %esi
callq gettimeofday
movq (%r12), %rax
movq 8(%r12), %rsi
subq (%r15), %rax
imulq $1000000, %rax, %rax # imm = 0xF4240
subq 8(%r15), %rsi
addq %rax, %rsi
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIyEERSoT_
movq %rax, %r13
movq (%rax), %rax
movq -24(%rax), %rdi
addq %r13, %rdi
movl $10, %esi
callq _ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
movsbl %al, %esi
movq %r13, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq %r15, %rdi
xorl %esi, %esi
callq gettimeofday
movq %rbx, %rdi
movq %r14, %rsi
movl $1024, %edx # imm = 0x400
movl $512, %ecx # imm = 0x200
callq _Z9pcmul_gpuP15HIP_vector_typeIfLj2EEPfii
movq %rax, %r13
movq %r12, %rdi
xorl %esi, %esi
callq gettimeofday
movq (%r12), %rax
movq 8(%r12), %rsi
subq (%r15), %rax
imulq $1000000, %rax, %rax # imm = 0xF4240
subq 8(%r15), %rsi
addq %rax, %rsi
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIyEERSoT_
movq %rax, %r15
movq (%rax), %rax
movq -24(%rax), %rdi
addq %r15, %rdi
movl $10, %esi
callq _ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
movsbl %al, %esi
movq %r15, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq %rbx, %rdi
callq _ZdaPv
movq %r14, %rdi
callq _ZdaPv
movq %r13, %rdi
callq _ZdaPv
xorl %eax, %eax
addq $32, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, %rdi
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12pcmul_kernelP15HIP_vector_typeIfLj2EES1_Pfii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z12pcmul_kernelP15HIP_vector_typeIfLj2EES1_Pfii,@object # @_Z12pcmul_kernelP15HIP_vector_typeIfLj2EES1_Pfii
.section .rodata,"a",@progbits
.globl _Z12pcmul_kernelP15HIP_vector_typeIfLj2EES1_Pfii
.p2align 3, 0x0
_Z12pcmul_kernelP15HIP_vector_typeIfLj2EES1_Pfii:
.quad _Z27__device_stub__pcmul_kernelP15HIP_vector_typeIfLj2EES1_Pfii
.size _Z12pcmul_kernelP15HIP_vector_typeIfLj2EES1_Pfii, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "copy to device "
.size .L.str, 16
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "kernel compute "
.size .L.str.1, 16
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "copy to host "
.size .L.str.2, 14
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z12pcmul_kernelP15HIP_vector_typeIfLj2EES1_Pfii"
.size .L__unnamed_1, 49
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z27__device_stub__pcmul_kernelP15HIP_vector_typeIfLj2EES1_Pfii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z12pcmul_kernelP15HIP_vector_typeIfLj2EES1_Pfii
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
```
| 7,504 | 7,781 |
518 |
Convert the following CUDA device assembly code to AMD device assembly:
```cudaasm
code for sm_80
Function : _Z7mat_mulPiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
MOV R1, c[0x0][0x28] ;
S2R R0, SR_TID.Y ;
S2R R3, SR_TID.X ;
IMAD R0, R0, c[0x0][0x0], R3 ;
ISETP.GT.AND P0, PT, R0, 0xfffff, PT ;
@P0 EXIT ;
UMOV UR4, 0x20 ;
ULDC.64 UR6, c[0x0][0x168] ;
ULDC.64 UR8, c[0x0][0x160] ;
UIADD3 UR6, UP0, UR4, UR6, URZ ;
UIADD3 UR4, UP1, UR4, UR8, URZ ;
UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ;
UIADD3.X UR5, URZ, UR9, URZ, UP1, !UPT ;
ULDC.64 UR8, c[0x0][0x118] ;
SHF.R.S32.HI R3, RZ, 0x1f, R0 ;
IMAD.MOV.U32 R22, RZ, RZ, RZ ;
MOV R11, c[0x0][0x0] ;
LEA.HI R3, R3, R0, RZ, 0xa ;
MOV R2, UR6 ;
LOP3.LUT R7, R3, 0xfffffc00, RZ, 0xc0, !PT ;
IMAD.U32 R3, RZ, RZ, UR7 ;
MOV R4, UR4 ;
MOV R5, UR5 ;
IMAD.IADD R6, R0, 0x1, -R7.reuse ;
IMAD R0, R11, c[0x0][0x4], R0 ;
SHF.R.S32.HI R11, RZ, 0x1f, R7 ;
IMAD.WIDE R4, R7, 0x4, R4 ;
SHF.L.U32 R9, R6, 0xa, RZ ;
ISETP.GE.AND P0, PT, R0, 0x100000, PT ;
IMAD.WIDE R2, R9, 0x4, R2 ;
HFMA2.MMA R9, -RZ, RZ, 0, 0 ;
LDG.E R13, [R2.64+-0x20] ;
LDG.E R8, [R4.64+-0x20] ;
LDG.E R27, [R2.64+-0x1c] ;
LDG.E R24, [R4.64+-0x1c] ;
LDG.E R19, [R2.64+-0x18] ;
LDG.E R14, [R4.64+-0x18] ;
LDG.E R16, [R2.64+-0x14] ;
LDG.E R21, [R4.64+-0x14] ;
LDG.E R18, [R2.64+-0x10] ;
LDG.E R23, [R4.64+-0x10] ;
LDG.E R20, [R2.64+-0xc] ;
LDG.E R25, [R4.64+-0xc] ;
LDG.E R12, [R2.64+-0x8] ;
LDG.E R17, [R4.64+-0x8] ;
LDG.E R15, [R2.64+-0x4] ;
LDG.E R10, [R4.64+-0x4] ;
IMAD R8, R13, R8, R22 ;
LDG.E R13, [R4.64] ;
LDG.E R22, [R2.64+0x1c] ;
IMAD R24, R27, R24, R8 ;
LDG.E R8, [R2.64] ;
LDG.E R27, [R4.64+0x1c] ;
IMAD R24, R19, R14, R24 ;
LDG.E R19, [R2.64+0x4] ;
LDG.E R14, [R4.64+0x4] ;
IMAD R24, R16, R21, R24 ;
LDG.E R16, [R2.64+0x8] ;
LDG.E R21, [R4.64+0x8] ;
IMAD R24, R18, R23, R24 ;
LDG.E R18, [R2.64+0xc] ;
LDG.E R23, [R4.64+0xc] ;
IMAD R24, R20, R25, R24 ;
LDG.E R20, [R2.64+0x10] ;
LDG.E R25, [R4.64+0x10] ;
IMAD R24, R12, R17, R24 ;
LDG.E R12, [R2.64+0x14] ;
LDG.E R17, [R4.64+0x14] ;
IMAD R24, R15, R10, R24 ;
LDG.E R10, [R2.64+0x18] ;
LDG.E R15, [R4.64+0x18] ;
IADD3 R9, R9, 0x10, RZ ;
ISETP.NE.AND P1, PT, R9, 0x400, PT ;
IADD3 R2, P2, R2, 0x40, RZ ;
IADD3 R4, P3, R4, 0x40, RZ ;
IADD3.X R3, RZ, R3, RZ, P2, !PT ;
IADD3.X R5, RZ, R5, RZ, P3, !PT ;
IMAD R8, R8, R13, R24 ;
IMAD R8, R19, R14, R8 ;
IMAD R8, R16, R21, R8 ;
IMAD R8, R18, R23, R8 ;
IMAD R8, R20, R25, R8 ;
IMAD R8, R12, R17, R8 ;
IMAD R8, R10, R15, R8 ;
IMAD R22, R22, R27, R8 ;
@P1 BRA 0x1f0 ;
IADD3 R7, P1, R7, R6, RZ ;
LEA.HI.X.SX32 R6, R6, R11, 0x1, P1 ;
LEA R2, P1, R7, c[0x0][0x170], 0x2 ;
LEA.HI.X R3, R7, c[0x0][0x174], R6, 0x2, P1 ;
STG.E [R2.64], R22 ;
@!P0 BRA 0xe0 ;
EXIT ;
BRA 0x5d0;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
```
|
```amdasm
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z7mat_mulPiS_S_ ; -- Begin function _Z7mat_mulPiS_S_
.globl _Z7mat_mulPiS_S_
.p2align 8
.type _Z7mat_mulPiS_S_,@function
_Z7mat_mulPiS_S_: ; @_Z7mat_mulPiS_S_
; %bb.0:
s_load_b32 s4, s[0:1], 0x24
v_and_b32_e32 v1, 0x3ff, v0
v_bfe_u32 v0, v0, 10, 10
s_add_u32 s2, s0, 24
s_addc_u32 s3, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s8, s4, 0xffff
s_mov_b32 s4, exec_lo
v_mad_u32_u24 v6, v0, s8, v1
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_u32_e32 0x100000, v6
s_cbranch_execz .LBB0_5
; %bb.1: ; %.lr.ph
s_load_b32 s9, s[2:3], 0xc
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[2:3], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_lshr_b32 s0, s9, 16
s_mov_b32 s9, 0
s_mul_i32 s8, s0, s8
.LBB0_2: ; =>This Loop Header: Depth=1
; Child Loop BB0_3 Depth 2
v_ashrrev_i32_e32 v0, 31, v6
s_mov_b64 s[0:1], 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshrrev_b32_e32 v0, 22, v0
v_add_nc_u32_e32 v1, v6, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v0, 10, v1
v_and_b32_e32 v1, 0xfffffc00, v1
v_mul_i32_i24_e32 v0, 0x400, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v2, 31, v1
v_sub_nc_u32_e32 v0, v6, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[2:3], 2, v[1:2]
v_dual_mov_b32 v1, 0 :: v_dual_lshlrev_b32 v4, 10, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v7, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v8, vcc_lo, s5, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v5, 31, v4
v_lshlrev_b64 v[4:5], 2, v[4:5]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v9, vcc_lo, s6, v4
v_add_co_ci_u32_e32 v10, vcc_lo, s7, v5, vcc_lo
.LBB0_3: ; Parent Loop BB0_2 Depth=1
; => This Inner Loop Header: Depth=2
v_add_co_u32 v4, vcc_lo, v7, s0
v_add_co_ci_u32_e32 v5, vcc_lo, s1, v8, vcc_lo
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v11, vcc_lo, v9, s0
v_add_co_ci_u32_e32 v12, vcc_lo, s1, v10, vcc_lo
s_add_u32 s0, s0, 4
global_load_b32 v13, v[4:5], off
global_load_b32 v11, v[11:12], off
s_addc_u32 s1, s1, 0
s_cmpk_eq_i32 s0, 0x1000
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[4:5], null, v11, v13, v[1:2]
s_delay_alu instid0(VALU_DEP_1)
v_mov_b32_e32 v1, v4
s_cbranch_scc0 .LBB0_3
; %bb.4: ; in Loop: Header=BB0_2 Depth=1
v_ashrrev_i32_e32 v1, 31, v0
v_add_nc_u32_e32 v6, s8, v6
v_add_co_u32 v2, vcc_lo, s2, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_lshlrev_b64 v[0:1], 2, v[0:1]
v_cmp_lt_i32_e32 vcc_lo, 0xfffff, v6
s_or_b32 s9, vcc_lo, s9
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v0, s0, v2, v0
v_add_co_ci_u32_e64 v1, s0, v3, v1, s0
global_store_b32 v[0:1], v4, off
s_and_not1_b32 exec_lo, exec_lo, s9
s_cbranch_execnz .LBB0_2
.LBB0_5: ; %._crit_edge
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z7mat_mulPiS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 14
.amdhsa_next_free_sgpr 10
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z7mat_mulPiS_S_, .Lfunc_end0-_Z7mat_mulPiS_S_
; -- End function
.section .AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 412
; NumSgprs: 12
; NumVgprs: 14
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 1
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 12
; NumVGPRsForWavesPerEU: 14
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object ; @__hip_cuid_
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0 ; 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z7mat_mulPiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 12
.sgpr_spill_count: 0
.symbol: _Z7mat_mulPiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 14
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
```
| 1,807 | 3,608 |
519 |
Convert the following CUDA host assembly code to AMD host assembly:
```cudaasm
.file "tmpxft_000ba5a4_00000000-6_1T_CPU.cudafe1.cpp"
.text
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z30__device_stub__Z7mat_mulPiS_S_PiS_S_
.type _Z30__device_stub__Z7mat_mulPiS_S_PiS_S_, @function
_Z30__device_stub__Z7mat_mulPiS_S_PiS_S_:
.LFB2082:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z7mat_mulPiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z30__device_stub__Z7mat_mulPiS_S_PiS_S_, .-_Z30__device_stub__Z7mat_mulPiS_S_PiS_S_
.globl _Z7mat_mulPiS_S_
.type _Z7mat_mulPiS_S_, @function
_Z7mat_mulPiS_S_:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z7mat_mulPiS_S_PiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z7mat_mulPiS_S_, .-_Z7mat_mulPiS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "PASSED"
.LC1:
.string "FAILED"
.LC3:
.string "CPU time: %13lf msec\n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC4:
.string "CPU transpose time: %13f msec\n"
.section .rodata.str1.1
.LC5:
.string "GPU mat-mul time: %13f msec\n"
.LC6:
.string "GPU total time: %13f msec\n"
.section .rodata.str1.8
.align 8
.LC7:
.string "before kernel call: error = %s\n"
.align 8
.LC8:
.string "MxN[%d][%d] = %d P[%d][%d] = %d\n"
.section .rodata.str1.1
.LC9:
.string "Test %s\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $136, %rsp
.cfi_def_cfa_offset 192
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq M(%rip), %rbx
leaq N(%rip), %rbp
leaq 4194304(%rbx), %r15
movq %rbp, %r14
movq %rbx, %r13
.L12:
movl $0, %r12d
.L13:
call rand@PLT
movl %eax, %edx
cltq
imulq $-2139062143, %rax, %rax
shrq $32, %rax
addl %edx, %eax
sarl $7, %eax
movl %edx, %ecx
sarl $31, %ecx
subl %ecx, %eax
movl %eax, %ecx
sall $8, %ecx
subl %eax, %ecx
subl %ecx, %edx
leal 1(%rdx), %eax
movl %eax, 0(%r13,%r12)
call rand@PLT
movl %eax, %edx
cltq
imulq $-2139062143, %rax, %rax
shrq $32, %rax
addl %edx, %eax
sarl $7, %eax
movl %edx, %ecx
sarl $31, %ecx
subl %ecx, %eax
movl %eax, %ecx
sall $8, %ecx
subl %eax, %ecx
subl %ecx, %edx
leal 1(%rdx), %eax
movl %eax, (%r14,%r12)
addq $4, %r12
cmpq $4096, %r12
jne .L13
addq $4096, %r13
addq $4096, %r14
cmpq %r15, %r13
jne .L12
leaq 80(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
movl $0, %r10d
leaq 4198400(%rbp), %r11
jmp .L15
.L38:
movl %esi, (%r9)
addq $4, %r8
addq $4, %rdi
cmpq %r11, %rdi
je .L17
.L19:
movq %r8, %r9
movl (%r8), %esi
leaq (%r10,%rbx), %rcx
leaq -4194304(%rdi), %rax
.L16:
movl (%rcx), %edx
imull (%rax), %edx
addl %edx, %esi
addq $4, %rcx
addq $4096, %rax
cmpq %rdi, %rax
jne .L16
jmp .L38
.L17:
addq $4096, %r10
cmpq $4194304, %r10
je .L18
.L15:
leaq MxN(%rip), %r12
leaq (%r10,%r12), %r8
leaq 4194304(%rbp), %rdi
jmp .L19
.L18:
leaq 96(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
movq 96(%rsp), %rax
subq 80(%rsp), %rax
pxor %xmm1, %xmm1
cvtsi2sdq %rax, %xmm1
movsd .LC2(%rip), %xmm2
mulsd %xmm2, %xmm1
movq 104(%rsp), %rax
subq 88(%rsp), %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
divsd %xmm2, %xmm0
addsd %xmm1, %xmm0
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
leaq 40(%rsp), %rdi
call cudaEventCreate@PLT
leaq 48(%rsp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq 40(%rsp), %rdi
call cudaEventRecord@PLT
movq %rbp, %rcx
movl $0, %edi
movl $0, %edx
movl $1023, %r8d
addq $4, %rbp
jmp .L22
.L39:
addq $4100, %rcx
addq $1025, %rdi
.L22:
addl $1, %edx
cmpl $1024, %edx
je .L20
movl %r8d, %eax
subl %edx, %eax
addq %rdi, %rax
leaq 0(%rbp,%rax,4), %r9
movq %rcx, %rsi
movq %rcx, %rax
.L21:
movl 4(%rax), %r10d
movl 4096(%rsi), %r11d
movl %r11d, 4(%rax)
movl %r10d, 4096(%rsi)
addq $4, %rax
addq $4096, %rsi
cmpq %r9, %rax
jne .L21
jmp .L39
.L20:
movl $0, %esi
movq 48(%rsp), %rdi
call cudaEventRecord@PLT
movq 48(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 8(%rsp), %rdi
movq 48(%rsp), %rdx
movq 40(%rsp), %rsi
call cudaEventElapsedTime@PLT
pxor %xmm0, %xmm0
cvtss2sd 8(%rsp), %xmm0
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
leaq 16(%rsp), %rdi
movl $4194304, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $4194304, %edx
leaq M(%rip), %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
leaq 24(%rsp), %rdi
movl $4194304, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $4194304, %edx
leaq N(%rip), %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
leaq 32(%rsp), %rdi
movl $4194304, %esi
call cudaMalloc@PLT
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $16, 68(%rsp)
movl $16, 72(%rsp)
movl $1, 76(%rsp)
movl $0, %esi
movq 40(%rsp), %rdi
call cudaEventRecord@PLT
movl 76(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 68(%rsp), %rdx
movq 56(%rsp), %rdi
movl 64(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L40
.L23:
movl $0, %esi
movq 48(%rsp), %rdi
call cudaEventRecord@PLT
movq 48(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 12(%rsp), %rdi
movq 48(%rsp), %rdx
movq 40(%rsp), %rsi
call cudaEventElapsedTime@PLT
pxor %xmm0, %xmm0
cvtss2sd 12(%rsp), %xmm0
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movss 8(%rsp), %xmm0
addss 12(%rsp), %xmm0
cvtss2sd %xmm0, %xmm0
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
call cudaGetLastError@PLT
movl %eax, %edi
testl %eax, %eax
jne .L41
movq 40(%rsp), %rdi
call cudaEventDestroy@PLT
movq 48(%rsp), %rdi
call cudaEventDestroy@PLT
movl $2, %ecx
movl $4194304, %edx
movq 32(%rsp), %rsi
leaq P(%rip), %rbx
movq %rbx, %rdi
call cudaMemcpy@PLT
movl $0, %ebp
movl $1, %edx
leaq .LC8(%rip), %r13
jmp .L25
.L40:
movq 32(%rsp), %rdx
movq 24(%rsp), %rsi
movq 16(%rsp), %rdi
call _Z30__device_stub__Z7mat_mulPiS_S_PiS_S_
jmp .L23
.L41:
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L42:
pushq %rcx
.cfi_def_cfa_offset 200
pushq %rax
.cfi_def_cfa_offset 208
movl %ebp, %r9d
movl %eax, %ecx
movl %ebp, %edx
movq %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
movl $0, %edx
.L27:
addl $1, %ebp
addq $4096, %r12
addq $4096, %rbx
cmpl $1024, %ebp
je .L29
.L25:
movl $0, %eax
.L28:
movl (%r12,%rax,4), %r8d
movl (%rbx,%rax,4), %ecx
cmpl %ecx, %r8d
jne .L42
addq $1, %rax
cmpq $1024, %rax
jne .L28
jmp .L27
.L29:
testl %edx, %edx
leaq .LC1(%rip), %rdx
leaq .LC0(%rip), %rax
cmovne %rax, %rdx
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L43
movl $0, %eax
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L43:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC10:
.string "_Z7mat_mulPiS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC10(%rip), %rdx
movq %rdx, %rcx
leaq _Z7mat_mulPiS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl MxN
.bss
.align 32
.type MxN, @object
.size MxN, 4194304
MxN:
.zero 4194304
.globl P
.align 32
.type P, @object
.size P, 4194304
P:
.zero 4194304
.globl N
.align 32
.type N, @object
.size N, 4194304
N:
.zero 4194304
.globl M
.align 32
.type M, @object
.size M, 4194304
M:
.zero 4194304
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC2:
.long 0
.long 1083129856
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
```
|
```amdasm
.text
.file "1T_CPU.hip"
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI0_0:
.quad 0x408f400000000000 # double 1000
.text
.globl main
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $104, %rsp
.cfi_def_cfa_offset 144
.cfi_offset %rbx, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
xorl %ebx, %ebx
xorl %r14d, %r14d
.LBB0_1: # %.preheader87
# =>This Loop Header: Depth=1
# Child Loop BB0_2 Depth 2
movq $-4096, %r15 # imm = 0xF000
.LBB0_2: # Parent Loop BB0_1 Depth=1
# => This Inner Loop Header: Depth=2
callq rand
cltq
imulq $-2139062143, %rax, %rcx # imm = 0x80808081
shrq $32, %rcx
addl %eax, %ecx
movl %ecx, %edx
shrl $31, %edx
sarl $7, %ecx
addl %edx, %ecx
movl %ecx, %edx
shll $8, %edx
subl %edx, %ecx
addl %ecx, %eax
incl %eax
movl %eax, M+4096(%rbx,%r15)
callq rand
cltq
imulq $-2139062143, %rax, %rcx # imm = 0x80808081
shrq $32, %rcx
addl %eax, %ecx
movl %ecx, %edx
shrl $31, %edx
sarl $7, %ecx
addl %edx, %ecx
movl %ecx, %edx
shll $8, %edx
subl %edx, %ecx
addl %ecx, %eax
incl %eax
movl %eax, N+4096(%rbx,%r15)
addq $4, %r15
jne .LBB0_2
# %bb.3: # in Loop: Header=BB0_1 Depth=1
incq %r14
addq $4096, %rbx # imm = 0x1000
cmpq $1024, %r14 # imm = 0x400
jne .LBB0_1
# %bb.4:
xorl %ebx, %ebx
leaq 72(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
movl $M, %eax
.LBB0_5: # %.preheader86
# =>This Loop Header: Depth=1
# Child Loop BB0_6 Depth 2
# Child Loop BB0_7 Depth 3
movl $N, %ecx
movq %rbx, %rdx
shlq $12, %rdx
xorl %esi, %esi
.LBB0_6: # %.preheader85
# Parent Loop BB0_5 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB0_7 Depth 3
leaq (%rdx,%rsi,4), %rdi
addq $MxN, %rdi
movl (%rdi), %r8d
movq %rcx, %r9
xorl %r10d, %r10d
.LBB0_7: # Parent Loop BB0_5 Depth=1
# Parent Loop BB0_6 Depth=2
# => This Inner Loop Header: Depth=3
movl (%r9), %r11d
imull (%rax,%r10,4), %r11d
addl %r11d, %r8d
incq %r10
addq $4096, %r9 # imm = 0x1000
cmpq $1024, %r10 # imm = 0x400
jne .LBB0_7
# %bb.8: # in Loop: Header=BB0_6 Depth=2
movl %r8d, (%rdi)
incq %rsi
addq $4, %rcx
cmpq $1024, %rsi # imm = 0x400
jne .LBB0_6
# %bb.9: # in Loop: Header=BB0_5 Depth=1
incq %rbx
addq $4096, %rax # imm = 0x1000
cmpq $1024, %rbx # imm = 0x400
jne .LBB0_5
# %bb.10:
xorl %r14d, %r14d
leaq 88(%rsp), %rbx
movq %rbx, %rdi
xorl %esi, %esi
callq gettimeofday
movq (%rbx), %rax
movq 8(%rbx), %rcx
subq 72(%rsp), %rax
cvtsi2sd %rax, %xmm1
movsd .LCPI0_0(%rip), %xmm2 # xmm2 = mem[0],zero
mulsd %xmm2, %xmm1
subq 80(%rsp), %rcx
cvtsi2sd %rcx, %xmm0
divsd %xmm2, %xmm0
addsd %xmm1, %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
leaq 24(%rsp), %rbx
movq %rbx, %rdi
callq hipEventCreate
leaq 16(%rsp), %rdi
callq hipEventCreate
movq (%rbx), %rdi
xorl %esi, %esi
callq hipEventRecord
movl $N+4, %eax
movl $N+4096, %ecx
movl $4100, %edx # imm = 0x1004
.LBB0_11: # =>This Loop Header: Depth=1
# Child Loop BB0_18 Depth 2
cmpq $1022, %r14 # imm = 0x3FE
ja .LBB0_12
# %bb.17: # %.lr.ph.preheader
# in Loop: Header=BB0_11 Depth=1
movl $1, %esi
movq %rcx, %rdi
.LBB0_18: # %.lr.ph
# Parent Loop BB0_11 Depth=1
# => This Inner Loop Header: Depth=2
movl -4(%rax,%rsi,4), %r8d
movl (%rdi), %r9d
movl %r9d, -4(%rax,%rsi,4)
movl %r8d, (%rdi)
addq $4096, %rdi # imm = 0x1000
leaq (%r14,%rsi), %r8
incq %r8
incq %rsi
cmpq $1024, %r8 # imm = 0x400
jne .LBB0_18
.LBB0_12: # %.loopexit84
# in Loop: Header=BB0_11 Depth=1
incq %r14
addq %rdx, %rax
addq %rdx, %rcx
cmpq $1024, %r14 # imm = 0x400
jne .LBB0_11
# %bb.13:
movq 16(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 16(%rsp), %rdi
callq hipEventSynchronize
movq 24(%rsp), %rsi
movq 16(%rsp), %rdx
leaq 44(%rsp), %rbx
movq %rbx, %rdi
callq hipEventElapsedTime
xorps %xmm0, %xmm0
cvtss2sd (%rbx), %xmm0
movl $.L.str.1, %edi
movb $1, %al
callq printf
leaq 56(%rsp), %rbx
movl $4194304, %esi # imm = 0x400000
movq %rbx, %rdi
callq hipMalloc
movq (%rbx), %rdi
movl $M, %esi
movl $4194304, %edx # imm = 0x400000
movl $1, %ecx
callq hipMemcpy
leaq 48(%rsp), %rbx
movl $4194304, %esi # imm = 0x400000
movq %rbx, %rdi
callq hipMalloc
movq (%rbx), %rdi
movl $N, %esi
movl $4194304, %edx # imm = 0x400000
movl $1, %ecx
callq hipMemcpy
leaq 32(%rsp), %rdi
movl $4194304, %esi # imm = 0x400000
callq hipMalloc
movq 24(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movabsq $4294967297, %rdi # imm = 0x100000001
movabsq $68719476752, %rdx # imm = 0x1000000010
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB0_15
# %bb.14:
movq 56(%rsp), %rdi
movq 48(%rsp), %rsi
movq 32(%rsp), %rdx
callq _Z22__device_stub__mat_mulPiS_S_
.LBB0_15:
movq 16(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 16(%rsp), %rdi
callq hipEventSynchronize
movq 24(%rsp), %rsi
movq 16(%rsp), %rdx
leaq 68(%rsp), %rbx
movq %rbx, %rdi
callq hipEventElapsedTime
xorps %xmm0, %xmm0
cvtss2sd (%rbx), %xmm0
movl $.L.str.2, %edi
movb $1, %al
callq printf
movss 44(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
addss (%rbx), %xmm0
cvtss2sd %xmm0, %xmm0
movl $.L.str.3, %edi
movb $1, %al
callq printf
callq hipGetLastError
testl %eax, %eax
jne .LBB0_16
# %bb.19:
movq 24(%rsp), %rdi
callq hipEventDestroy
movq 16(%rsp), %rdi
callq hipEventDestroy
movq 32(%rsp), %rsi
movl $P, %edi
movl $4194304, %edx # imm = 0x400000
movl $2, %ecx
callq hipMemcpy
movl $1, %ebp
xorl %r14d, %r14d
xorl %ebx, %ebx
.LBB0_20: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB0_21 Depth 2
xorl %edx, %edx
.LBB0_21: # Parent Loop BB0_20 Depth=1
# => This Inner Loop Header: Depth=2
movl MxN(%r14,%rdx,4), %ecx
movl P(%r14,%rdx,4), %eax
cmpl %eax, %ecx
jne .LBB0_22
# %bb.23: # in Loop: Header=BB0_21 Depth=2
incq %rdx
cmpq $1024, %rdx # imm = 0x400
jne .LBB0_21
jmp .LBB0_24
.LBB0_22: # in Loop: Header=BB0_20 Depth=1
movl %eax, (%rsp)
xorl %ebp, %ebp
movl $.L.str.5, %edi
movl %ebx, %esi
movl %ebx, %r8d
movl %edx, %r9d
xorl %eax, %eax
callq printf
.LBB0_24: # %.loopexit
# in Loop: Header=BB0_20 Depth=1
incq %rbx
addq $4096, %r14 # imm = 0x1000
cmpq $1024, %rbx # imm = 0x400
jne .LBB0_20
# %bb.25:
testl %ebp, %ebp
movl $.L.str.8, %eax
movl $.L.str.7, %esi
cmoveq %rax, %rsi
movl $.L.str.6, %edi
xorl %eax, %eax
callq printf
movq 56(%rsp), %rdi
callq hipFree
movq 48(%rsp), %rdi
callq hipFree
movq 32(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $104, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB0_16:
.cfi_def_cfa_offset 144
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.4, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
movl $1, %edi
callq exit
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.globl _Z22__device_stub__mat_mulPiS_S_ # -- Begin function _Z22__device_stub__mat_mulPiS_S_
.type _Z22__device_stub__mat_mulPiS_S_,@function
_Z22__device_stub__mat_mulPiS_S_: # @_Z22__device_stub__mat_mulPiS_S_
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $112, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 40(%rsp), %rax
movq %rdi, (%rax)
leaq 32(%rsp), %rcx
movq %rsi, (%rcx)
leaq 24(%rsp), %rsi
movq %rdx, (%rsi)
leaq 80(%rsp), %rbx
movq %rax, (%rbx)
movq %rcx, 8(%rbx)
movq %rsi, 16(%rbx)
leaq 64(%rsp), %r14
leaq 48(%rsp), %r15
leaq 16(%rsp), %r12
leaq 8(%rsp), %r13
movq %r14, %rdi
movq %r15, %rsi
movq %r12, %rdx
movq %r13, %rcx
callq __hipPopCallConfiguration
movq (%r14), %rsi
movl 8(%r14), %edx
movq (%r15), %rcx
movl 8(%r15), %r8d
movl $_Z7mat_mulPiS_S_, %edi
movq %rbx, %r9
pushq (%r13)
.cfi_adjust_cfa_offset 8
pushq (%r12)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $128, %rsp
.cfi_adjust_cfa_offset -128
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z22__device_stub__mat_mulPiS_S_, .Lfunc_end1-_Z22__device_stub__mat_mulPiS_S_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, %rdi
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7mat_mulPiS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type M,@object # @M
.bss
.globl M
.p2align 4, 0x0
M:
.zero 4194304
.size M, 4194304
.type N,@object # @N
.globl N
.p2align 4, 0x0
N:
.zero 4194304
.size N, 4194304
.type P,@object # @P
.globl P
.p2align 4, 0x0
P:
.zero 4194304
.size P, 4194304
.type MxN,@object # @MxN
.globl MxN
.p2align 4, 0x0
MxN:
.zero 4194304
.size MxN, 4194304
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "CPU time: %13lf msec\n"
.size .L.str, 22
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "CPU transpose time: %13f msec\n"
.size .L.str.1, 31
.type _Z7mat_mulPiS_S_,@object # @_Z7mat_mulPiS_S_
.section .rodata,"a",@progbits
.globl _Z7mat_mulPiS_S_
.p2align 3, 0x0
_Z7mat_mulPiS_S_:
.quad _Z22__device_stub__mat_mulPiS_S_
.size _Z7mat_mulPiS_S_, 8
.type .L.str.2,@object # @.str.2
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.2:
.asciz "GPU mat-mul time: %13f msec\n"
.size .L.str.2, 29
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "GPU total time: %13f msec\n"
.size .L.str.3, 27
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "before kernel call: error = %s\n"
.size .L.str.4, 32
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "MxN[%d][%d] = %d P[%d][%d] = %d\n"
.size .L.str.5, 35
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "Test %s\n"
.size .L.str.6, 9
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "PASSED"
.size .L.str.7, 7
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "FAILED"
.size .L.str.8, 7
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z7mat_mulPiS_S_"
.size .L__unnamed_1, 17
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__mat_mulPiS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym M
.addrsig_sym N
.addrsig_sym P
.addrsig_sym _Z7mat_mulPiS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
```
| 5,845 | 6,721 |
520 |
Convert the following CUDA device assembly code to AMD device assembly:
```cudaasm
code for sm_80
Function : _Z12mandelKernelffffPiiii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ;
S2R R0, SR_CTAID.X ;
S2R R3, SR_TID.X ;
S2R R9, SR_CTAID.Y ;
IMAD R0, R0, c[0x0][0x0], R3 ;
ISETP.GE.AND P0, PT, R0, c[0x0][0x178], PT ;
@P0 EXIT ;
I2F R5, c[0x0][0x178] ;
IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x160] ;
S2R R10, SR_TID.Y ;
FADD R4, R4, -c[0x0][0x168] ;
I2F R2, R0 ;
MUFU.RCP R6, R5 ;
FCHK P0, R4, R5 ;
FFMA R3, -R5, R6, 1 ;
FFMA R7, R6, R3, R6 ;
IMAD R3, R9, c[0x0][0x4], R10 ;
FFMA R6, R4, R7, RZ ;
FFMA R8, -R5, R6, R4 ;
FFMA R7, R7, R8, R6 ;
@!P0 BRA 0x1a0 ;
IMAD.MOV.U32 R9, RZ, RZ, R4 ;
MOV R6, 0x190 ;
IMAD.MOV.U32 R8, RZ, RZ, R5 ;
CALL.REL.NOINC 0x480 ;
IMAD.MOV.U32 R7, RZ, RZ, R5 ;
I2F R6, c[0x0][0x17c] ;
IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x164] ;
FFMA R2, R2, R7, c[0x0][0x168] ;
FADD R5, R5, -c[0x0][0x16c] ;
I2F R4, R3 ;
MUFU.RCP R9, R6 ;
FCHK P0, R5, R6 ;
FFMA R8, -R6, R9, 1 ;
FFMA R8, R9, R8, R9 ;
FFMA R9, R5, R8, RZ ;
FFMA R10, -R6, R9, R5 ;
FFMA R9, R8, R10, R9 ;
@!P0 BRA 0x2c0 ;
IMAD.MOV.U32 R8, RZ, RZ, R6 ;
MOV R9, R5 ;
MOV R6, 0x2b0 ;
CALL.REL.NOINC 0x480 ;
IMAD.MOV.U32 R9, RZ, RZ, R5 ;
IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x180] ;
ULDC.64 UR4, c[0x0][0x118] ;
FFMA R8, R4, R9, c[0x0][0x16c] ;
ISETP.GE.AND P0, PT, R5, 0x1, PT ;
IMAD.MOV.U32 R5, RZ, RZ, RZ ;
@!P0 BRA 0x430 ;
BSSY B0, 0x430 ;
IMAD.MOV.U32 R5, RZ, RZ, RZ ;
MOV R4, R8 ;
IMAD.MOV.U32 R6, RZ, RZ, R2 ;
FMUL R7, R4, R4 ;
FMUL R10, R6, R6 ;
FADD R9, R7, R10 ;
FSETP.GT.AND P0, PT, R9, 4, PT ;
@P0 BRA 0x420 ;
IADD3 R5, R5, 0x1, RZ ;
FADD R9, R6, R6 ;
FADD R7, -R7, R10 ;
ISETP.GE.AND P0, PT, R5, c[0x0][0x180], PT ;
FFMA R4, R9, R4, R8 ;
FADD R6, R2, R7 ;
@!P0 BRA 0x360 ;
BSYNC B0 ;
IMAD.MOV.U32 R2, RZ, RZ, 0x4 ;
IMAD R3, R3, c[0x0][0x178], R0 ;
IMAD.WIDE R2, R3, R2, c[0x0][0x170] ;
STG.E [R2.64], R5 ;
EXIT ;
SHF.R.U32.HI R7, RZ, 0x17, R8 ;
SHF.R.U32.HI R5, RZ, 0x17, R9.reuse ;
LOP3.LUT R13, R7, 0xff, RZ, 0xc0, !PT ;
LOP3.LUT R11, R5, 0xff, RZ, 0xc0, !PT ;
IMAD.MOV.U32 R5, RZ, RZ, R9 ;
IADD3 R12, R13, -0x1, RZ ;
IADD3 R10, R11, -0x1, RZ ;
ISETP.GT.U32.AND P0, PT, R12, 0xfd, PT ;
ISETP.GT.U32.OR P0, PT, R10, 0xfd, P0 ;
@!P0 IMAD.MOV.U32 R7, RZ, RZ, RZ ;
@!P0 BRA 0x6a0 ;
FSETP.GTU.FTZ.AND P0, PT, |R9|, +INF , PT ;
FSETP.GTU.FTZ.AND P1, PT, |R8|, +INF , PT ;
PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ;
@P0 BRA 0xa80 ;
LOP3.LUT P0, RZ, R8, 0x7fffffff, R5, 0xc8, !PT ;
@!P0 BRA 0xa60 ;
FSETP.NEU.FTZ.AND P2, PT, |R9|.reuse, +INF , PT ;
FSETP.NEU.FTZ.AND P1, PT, |R8|, +INF , PT ;
FSETP.NEU.FTZ.AND P0, PT, |R9|, +INF , PT ;
@!P1 BRA !P2, 0xa60 ;
LOP3.LUT P2, RZ, R5, 0x7fffffff, RZ, 0xc0, !PT ;
PLOP3.LUT P1, PT, P1, P2, PT, 0x2a, 0x0 ;
@P1 BRA 0xa40 ;
LOP3.LUT P1, RZ, R8, 0x7fffffff, RZ, 0xc0, !PT ;
PLOP3.LUT P0, PT, P0, P1, PT, 0x2a, 0x0 ;
@P0 BRA 0xa10 ;
ISETP.GE.AND P0, PT, R10, RZ, PT ;
ISETP.GE.AND P1, PT, R12, RZ, PT ;
@P0 MOV R7, RZ ;
@!P0 IMAD.MOV.U32 R7, RZ, RZ, -0x40 ;
@!P0 FFMA R5, R9, 1.84467440737095516160e+19, RZ ;
@!P1 FFMA R8, R8, 1.84467440737095516160e+19, RZ ;
@!P1 IADD3 R7, R7, 0x40, RZ ;
LEA R9, R13, 0xc0800000, 0x17 ;
IMAD.IADD R9, R8, 0x1, -R9 ;
IADD3 R8, R11, -0x7f, RZ ;
MUFU.RCP R10, R9 ;
FADD.FTZ R12, -R9, -RZ ;
IMAD R5, R8, -0x800000, R5 ;
FFMA R11, R10, R12, 1 ;
FFMA R14, R10, R11, R10 ;
FFMA R10, R5, R14, RZ ;
FFMA R11, R12, R10, R5 ;
FFMA R11, R14, R11, R10 ;
IADD3 R10, R8, 0x7f, -R13 ;
FFMA R12, R12, R11, R5 ;
IMAD.IADD R10, R10, 0x1, R7 ;
FFMA R5, R14, R12, R11 ;
SHF.R.U32.HI R8, RZ, 0x17, R5 ;
LOP3.LUT R8, R8, 0xff, RZ, 0xc0, !PT ;
IMAD.IADD R13, R8, 0x1, R10 ;
IADD3 R7, R13, -0x1, RZ ;
ISETP.GE.U32.AND P0, PT, R7, 0xfe, PT ;
@!P0 BRA 0x9f0 ;
ISETP.GT.AND P0, PT, R13, 0xfe, PT ;
@P0 BRA 0x9c0 ;
ISETP.GE.AND P0, PT, R13, 0x1, PT ;
@P0 BRA 0xa90 ;
ISETP.GE.AND P0, PT, R13, -0x18, PT ;
LOP3.LUT R5, R5, 0x80000000, RZ, 0xc0, !PT ;
@!P0 BRA 0xa90 ;
FFMA.RZ R7, R14.reuse, R12.reuse, R11.reuse ;
IADD3 R10, R13.reuse, 0x20, RZ ;
FFMA.RM R8, R14.reuse, R12.reuse, R11.reuse ;
ISETP.NE.AND P2, PT, R13, RZ, PT ;
LOP3.LUT R9, R7, 0x7fffff, RZ, 0xc0, !PT ;
FFMA.RP R7, R14, R12, R11 ;
ISETP.NE.AND P1, PT, R13, RZ, PT ;
LOP3.LUT R9, R9, 0x800000, RZ, 0xfc, !PT ;
IADD3 R11, -R13, RZ, RZ ;
SHF.L.U32 R10, R9, R10, RZ ;
FSETP.NEU.FTZ.AND P0, PT, R7, R8, PT ;
SEL R8, R11, RZ, P2 ;
ISETP.NE.AND P1, PT, R10, RZ, P1 ;
SHF.R.U32.HI R8, RZ, R8, R9 ;
PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ;
SHF.R.U32.HI R10, RZ, 0x1, R8 ;
SEL R7, RZ, 0x1, !P0 ;
LOP3.LUT R7, R7, 0x1, R10, 0xf8, !PT ;
LOP3.LUT R7, R7, R8, RZ, 0xc0, !PT ;
IMAD.IADD R10, R10, 0x1, R7 ;
LOP3.LUT R5, R10, R5, RZ, 0xfc, !PT ;
BRA 0xa90 ;
LOP3.LUT R5, R5, 0x80000000, RZ, 0xc0, !PT ;
LOP3.LUT R5, R5, 0x7f800000, RZ, 0xfc, !PT ;
BRA 0xa90 ;
IMAD R5, R10, 0x800000, R5 ;
BRA 0xa90 ;
LOP3.LUT R5, R8, 0x80000000, R5, 0x48, !PT ;
LOP3.LUT R5, R5, 0x7f800000, RZ, 0xfc, !PT ;
BRA 0xa90 ;
LOP3.LUT R5, R8, 0x80000000, R5, 0x48, !PT ;
BRA 0xa90 ;
MUFU.RSQ R5, -QNAN ;
BRA 0xa90 ;
FADD.FTZ R5, R9, R8 ;
IMAD.MOV.U32 R7, RZ, RZ, 0x0 ;
RET.REL.NODEC R6 0x0 ;
BRA 0xab0;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
```
|
```amdasm
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z12mandelKernelffffPiiii ; -- Begin function _Z12mandelKernelffffPiiii
.globl _Z12mandelKernelffffPiiii
.p2align 8
.type _Z12mandelKernelffffPiiii,@function
_Z12mandelKernelffffPiiii: ; @_Z12mandelKernelffffPiiii
; %bb.0:
s_clause 0x1
s_load_b32 s8, s[0:1], 0x34
s_load_b128 s[4:7], s[0:1], 0x18
v_and_b32_e32 v3, 0x3ff, v0
s_add_u32 s2, s0, 40
s_addc_u32 s3, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s7, s8, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s14, s7, v[3:4]
s_mov_b32 s7, exec_lo
v_cmpx_gt_i32_e64 s4, v1
s_cbranch_execz .LBB0_9
; %bb.1: ; %.lr.ph54
s_load_b32 s2, s[2:3], 0xc
v_bfe_u32 v0, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_lshr_b32 s2, s2, 16
s_cmp_lt_i32 s6, 1
s_delay_alu instid0(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, s15, s2, v[0:1]
s_cbranch_scc1 .LBB0_7
; %bb.2: ; %.lr.ph.preheader
s_load_b128 s[8:11], s[0:1], 0x0
v_cvt_f32_i32_e32 v0, s4
v_cvt_f32_i32_e32 v4, s5
s_mov_b32 s3, 0
; implicit-def: $sgpr5
s_waitcnt lgkmcnt(0)
v_sub_f32_e64 v3, s8, s10
v_sub_f32_e64 v5, s9, s11
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_div_scale_f32 v6, null, v0, v0, v3
v_div_scale_f32 v7, null, v4, v4, v5
v_div_scale_f32 v12, vcc_lo, v3, v0, v3
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_rcp_f32_e32 v8, v6
v_rcp_f32_e32 v9, v7
s_waitcnt_depctr 0xfff
v_fma_f32 v10, -v6, v8, 1.0
v_fma_f32 v11, -v7, v9, 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_dual_fmac_f32 v8, v10, v8 :: v_dual_fmac_f32 v9, v11, v9
v_div_scale_f32 v10, s2, v5, v4, v5
v_mul_f32_e32 v11, v12, v8
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_f32_e32 v13, v10, v9
v_fma_f32 v14, -v6, v11, v12
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v15, -v7, v13, v10
v_fmac_f32_e32 v11, v14, v8
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fmac_f32_e32 v13, v15, v9
v_fma_f32 v6, -v6, v11, v12
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v7, -v7, v13, v10
v_div_fmas_f32 v6, v6, v8, v11
s_mov_b32 vcc_lo, s2
v_cvt_f32_i32_e32 v8, v2
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)
v_div_fmas_f32 v7, v7, v9, v13
v_cvt_f32_i32_e32 v9, v1
v_div_fixup_f32 v3, v6, v0, v3
s_mov_b32 s2, 0
v_div_fixup_f32 v4, v7, v4, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v3, v3, v9, s10
v_fma_f32 v0, v4, v8, s11
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mov_b32_e32 v6, v3
v_mov_b32_e32 v4, v0
.LBB0_3: ; %.lr.ph
; =>This Inner Loop Header: Depth=1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mul_f32_e32 v7, v4, v4
s_or_b32 s5, s5, exec_lo
v_fma_f32 v5, v6, v6, v7
s_delay_alu instid0(VALU_DEP_1)
v_cmp_nlt_f32_e32 vcc_lo, 4.0, v5
v_mov_b32_e32 v5, s3
s_and_saveexec_b32 s7, vcc_lo
s_cbranch_execz .LBB0_5
; %bb.4: ; in Loop: Header=BB0_3 Depth=1
v_mul_f32_e32 v5, v6, v6
v_add_f32_e32 v6, v6, v6
s_add_i32 s3, s3, 1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
s_cmp_eq_u32 s6, s3
v_sub_f32_e32 v7, v5, v7
s_cselect_b32 s8, -1, 0
v_mov_b32_e32 v5, s6
v_fma_f32 v4, v6, v4, v0
s_and_not1_b32 s5, s5, exec_lo
v_add_f32_e32 v6, v3, v7
s_and_b32 s8, s8, exec_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 s5, s5, s8
.LBB0_5: ; %Flow
; in Loop: Header=BB0_3 Depth=1
s_or_b32 exec_lo, exec_lo, s7
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s7, exec_lo, s5
s_or_b32 s2, s7, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s2
s_cbranch_execnz .LBB0_3
; %bb.6: ; %Flow79
s_or_b32 exec_lo, exec_lo, s2
s_branch .LBB0_8
.LBB0_7:
v_mov_b32_e32 v5, 0
.LBB0_8: ; %._crit_edge
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[3:4], null, v2, s4, v[1:2]
v_ashrrev_i32_e32 v4, 31, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[3:4]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v5, off
.LBB0_9: ; %Flow81
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z12mandelKernelffffPiiii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 16
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z12mandelKernelffffPiiii, .Lfunc_end0-_Z12mandelKernelffffPiiii
; -- End function
.section .AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 604
; NumSgprs: 18
; NumVgprs: 16
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 16
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object ; @__hip_cuid_
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0 ; 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z12mandelKernelffffPiiii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z12mandelKernelffffPiiii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 16
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
```
| 3,329 | 4,494 |
521 |
Convert the following CUDA host assembly code to AMD host assembly:
```cudaasm
.file "tmpxft_0006fc5d_00000000-6_kernel3.cudafe1.cpp"
.text
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z39__device_stub__Z12mandelKernelffffPiiiiffffPiiii
.type _Z39__device_stub__Z12mandelKernelffffPiiiiffffPiiii, @function
_Z39__device_stub__Z12mandelKernelffffPiiiiffffPiiii:
.LFB2082:
.cfi_startproc
endbr64
subq $200, %rsp
.cfi_def_cfa_offset 208
movss %xmm0, 44(%rsp)
movss %xmm1, 40(%rsp)
movss %xmm2, 36(%rsp)
movss %xmm3, 32(%rsp)
movq %rdi, 24(%rsp)
movl %esi, 20(%rsp)
movl %edx, 16(%rsp)
movl %ecx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
leaq 44(%rsp), %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rax
movq %rax, 120(%rsp)
leaq 36(%rsp), %rax
movq %rax, 128(%rsp)
leaq 32(%rsp), %rax
movq %rax, 136(%rsp)
leaq 24(%rsp), %rax
movq %rax, 144(%rsp)
leaq 20(%rsp), %rax
movq %rax, 152(%rsp)
leaq 16(%rsp), %rax
movq %rax, 160(%rsp)
leaq 12(%rsp), %rax
movq %rax, 168(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 216
pushq 56(%rsp)
.cfi_def_cfa_offset 224
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z12mandelKernelffffPiiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 208
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z39__device_stub__Z12mandelKernelffffPiiiiffffPiiii, .-_Z39__device_stub__Z12mandelKernelffffPiiiiffffPiiii
.globl _Z12mandelKernelffffPiiii
.type _Z12mandelKernelffffPiiii, @function
_Z12mandelKernelffffPiiii:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z39__device_stub__Z12mandelKernelffffPiiiiffffPiiii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z12mandelKernelffffPiiii, .-_Z12mandelKernelffffPiiii
.globl _Z6hostFEffffPiiii
.type _Z6hostFEffffPiiii, @function
_Z6hostFEffffPiiii:
.LFB2057:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $80, %rsp
.cfi_def_cfa_offset 128
movss %xmm0, (%rsp)
movss %xmm1, 4(%rsp)
movss %xmm2, 8(%rsp)
movss %xmm3, 12(%rsp)
movq %rdi, %r13
movl %esi, %ebp
movl %edx, %r12d
movl %ecx, %r14d
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl %esi, %ebx
imull %edx, %ebx
movslq %ebx, %rbx
salq $2, %rbx
leaq 32(%rsp), %rdi
movl $0, %edx
movq %rbx, %rsi
call cudaHostAlloc@PLT
movslq %r12d, %rcx
movslq %ebp, %rdx
salq $2, %rdx
leaq 40(%rsp), %rsi
leaq 24(%rsp), %rdi
call cudaMallocPitch@PLT
movzbl _ZGVZ6hostFEffffPiiiiE8x_blocks(%rip), %eax
testb %al, %al
je .L21
.L12:
movzbl _ZGVZ6hostFEffffPiiiiE8y_blocks(%rip), %eax
testb %al, %al
je .L22
.L15:
movl $32, 48(%rsp)
movl $32, 52(%rsp)
movl _ZZ6hostFEffffPiiiiE8x_blocks(%rip), %eax
movl %eax, 60(%rsp)
movl _ZZ6hostFEffffPiiiiE8y_blocks(%rip), %eax
movl %eax, 64(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 48(%rsp), %rdx
movl $1, %ecx
movq 60(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L23
.L18:
movl $2, %ecx
movq %rbx, %rdx
movq 24(%rsp), %rsi
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
movq 32(%rsp), %rbp
movq %rbx, %rdx
movq %rbp, %rsi
movq %r13, %rdi
call memcpy@PLT
movq %rbp, %rdi
call cudaFreeHost@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L24
addq $80, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L21:
.cfi_restore_state
leaq _ZGVZ6hostFEffffPiiiiE8x_blocks(%rip), %rdi
call __cxa_guard_acquire@PLT
testl %eax, %eax
je .L12
testb $31, %bpl
jne .L13
leal 31(%rbp), %eax
testl %ebp, %ebp
cmovns %ebp, %eax
sarl $5, %eax
.L14:
movl %eax, _ZZ6hostFEffffPiiiiE8x_blocks(%rip)
leaq _ZGVZ6hostFEffffPiiiiE8x_blocks(%rip), %rdi
call __cxa_guard_release@PLT
jmp .L12
.L13:
leal 31(%rbp), %eax
testl %ebp, %ebp
cmovns %ebp, %eax
sarl $5, %eax
addl $1, %eax
jmp .L14
.L22:
leaq _ZGVZ6hostFEffffPiiiiE8y_blocks(%rip), %rdi
call __cxa_guard_acquire@PLT
testl %eax, %eax
je .L15
testb $31, %r12b
jne .L16
leal 31(%r12), %eax
testl %r12d, %r12d
cmovns %r12d, %eax
sarl $5, %eax
.L17:
movl %eax, _ZZ6hostFEffffPiiiiE8y_blocks(%rip)
leaq _ZGVZ6hostFEffffPiiiiE8y_blocks(%rip), %rdi
call __cxa_guard_release@PLT
jmp .L15
.L16:
leal 31(%r12), %eax
testl %r12d, %r12d
cmovns %r12d, %eax
sarl $5, %eax
addl $1, %eax
jmp .L17
.L23:
movl %r14d, %ecx
movl %r12d, %edx
movl %ebp, %esi
movq 24(%rsp), %rdi
movss 12(%rsp), %xmm3
movss 8(%rsp), %xmm2
movss 4(%rsp), %xmm1
movss (%rsp), %xmm0
call _Z39__device_stub__Z12mandelKernelffffPiiiiffffPiiii
jmp .L18
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size _Z6hostFEffffPiiii, .-_Z6hostFEffffPiiii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z12mandelKernelffffPiiii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z12mandelKernelffffPiiii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZGVZ6hostFEffffPiiiiE8y_blocks
.comm _ZGVZ6hostFEffffPiiiiE8y_blocks,8,8
.local _ZZ6hostFEffffPiiiiE8y_blocks
.comm _ZZ6hostFEffffPiiiiE8y_blocks,4,4
.local _ZGVZ6hostFEffffPiiiiE8x_blocks
.comm _ZGVZ6hostFEffffPiiiiE8x_blocks,8,8
.local _ZZ6hostFEffffPiiiiE8x_blocks
.comm _ZZ6hostFEffffPiiiiE8x_blocks,4,4
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
```
|
```amdasm
.text
.file "kernel3.hip"
.globl _Z27__device_stub__mandelKernelffffPiiii # -- Begin function _Z27__device_stub__mandelKernelffffPiiii
.type _Z27__device_stub__mandelKernelffffPiiii,@function
_Z27__device_stub__mandelKernelffffPiiii: # @_Z27__device_stub__mandelKernelffffPiiii
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $160, %rsp
.cfi_def_cfa_offset 208
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 36(%rsp), %rax
movss %xmm0, (%rax)
leaq 32(%rsp), %r8
movss %xmm1, (%r8)
leaq 28(%rsp), %r9
movss %xmm2, (%r9)
leaq 24(%rsp), %r10
movss %xmm3, (%r10)
leaq 56(%rsp), %r11
movq %rdi, (%r11)
leaq 20(%rsp), %rdi
movl %esi, (%rdi)
leaq 16(%rsp), %rsi
movl %edx, (%rsi)
leaq 12(%rsp), %rdx
movl %ecx, (%rdx)
leaq 96(%rsp), %rbx
movq %rax, (%rbx)
movq %r8, 8(%rbx)
movq %r9, 16(%rbx)
movq %r10, 24(%rbx)
movq %r11, 32(%rbx)
movq %rdi, 40(%rbx)
movq %rsi, 48(%rbx)
movq %rdx, 56(%rbx)
leaq 80(%rsp), %r14
leaq 64(%rsp), %r15
leaq 48(%rsp), %r12
leaq 40(%rsp), %r13
movq %r14, %rdi
movq %r15, %rsi
movq %r12, %rdx
movq %r13, %rcx
callq __hipPopCallConfiguration
movq (%r14), %rsi
movl 8(%r14), %edx
movq (%r15), %rcx
movl 8(%r15), %r8d
movl $_Z12mandelKernelffffPiiii, %edi
movq %rbx, %r9
pushq (%r13)
.cfi_adjust_cfa_offset 8
pushq (%r12)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $176, %rsp
.cfi_adjust_cfa_offset -176
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z27__device_stub__mandelKernelffffPiiii, .Lfunc_end0-_Z27__device_stub__mandelKernelffffPiiii
.cfi_endproc
# -- End function
.globl _Z6hostFEffffPiiii # -- Begin function _Z6hostFEffffPiiii
.type _Z6hostFEffffPiiii,@function
_Z6hostFEffffPiiii: # @_Z6hostFEffffPiiii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $48, %rsp
.cfi_def_cfa_offset 96
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %ecx, %ebp
movl %edx, %r15d
movl %esi, %r12d
movq %rdi, %rbx
movss %xmm3, 28(%rsp) # 4-byte Spill
movss %xmm2, 24(%rsp) # 4-byte Spill
movss %xmm1, 20(%rsp) # 4-byte Spill
movss %xmm0, 16(%rsp) # 4-byte Spill
movl %edx, %eax
imull %esi, %eax
movslq %eax, %r14
shlq $2, %r14
leaq 32(%rsp), %rdi
movq %r14, %rsi
xorl %edx, %edx
callq hipHostAlloc
movslq %r12d, %rdx
shlq $2, %rdx
movslq %r15d, %rcx
leaq 8(%rsp), %rdi
leaq 40(%rsp), %rsi
callq hipMallocPitch
movb _ZGVZ6hostFEffffPiiiiE8x_blocks(%rip), %al
testb %al, %al
je .LBB1_1
.LBB1_6:
movb _ZGVZ6hostFEffffPiiiiE8y_blocks(%rip), %al
testb %al, %al
je .LBB1_7
.LBB1_12:
movl _ZZ6hostFEffffPiiiiE8x_blocks(%rip), %eax
movl _ZZ6hostFEffffPiiiiE8y_blocks(%rip), %edi
shlq $32, %rdi
orq %rax, %rdi
movabsq $137438953504, %rdx # imm = 0x2000000020
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_14
# %bb.13:
movq 8(%rsp), %rdi
movss 16(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
movss 20(%rsp), %xmm1 # 4-byte Reload
# xmm1 = mem[0],zero,zero,zero
movss 24(%rsp), %xmm2 # 4-byte Reload
# xmm2 = mem[0],zero,zero,zero
movss 28(%rsp), %xmm3 # 4-byte Reload
# xmm3 = mem[0],zero,zero,zero
movl %r12d, %esi
movl %r15d, %edx
movl %ebp, %ecx
callq _Z27__device_stub__mandelKernelffffPiiii
.LBB1_14:
movq 32(%rsp), %rdi
movq 8(%rsp), %rsi
movq %r14, %rdx
movl $2, %ecx
callq hipMemcpy
movq 32(%rsp), %r15
movq %rbx, %rdi
movq %r15, %rsi
movq %r14, %rdx
callq memcpy@PLT
movq %r15, %rdi
callq hipHostFree
movq 8(%rsp), %rdi
callq hipFree
addq $48, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB1_1:
.cfi_def_cfa_offset 96
movl $_ZGVZ6hostFEffffPiiiiE8x_blocks, %edi
callq __cxa_guard_acquire
testl %eax, %eax
je .LBB1_6
# %bb.2:
testb $31, %r12b
je .LBB1_3
# %bb.4:
leal 31(%r12), %eax
testl %r12d, %r12d
cmovnsl %r12d, %eax
sarl $5, %eax
incl %eax
jmp .LBB1_5
.LBB1_7:
movl $_ZGVZ6hostFEffffPiiiiE8y_blocks, %edi
callq __cxa_guard_acquire
testl %eax, %eax
je .LBB1_12
# %bb.8:
testb $31, %r15b
je .LBB1_9
# %bb.10:
leal 31(%r15), %eax
testl %r15d, %r15d
cmovnsl %r15d, %eax
sarl $5, %eax
incl %eax
jmp .LBB1_11
.LBB1_3:
movl %r12d, %eax
sarl $5, %eax
.LBB1_5:
movl %eax, _ZZ6hostFEffffPiiiiE8x_blocks(%rip)
movl $_ZGVZ6hostFEffffPiiiiE8x_blocks, %edi
callq __cxa_guard_release
jmp .LBB1_6
.LBB1_9:
movl %r15d, %eax
sarl $5, %eax
.LBB1_11:
movl %eax, _ZZ6hostFEffffPiiiiE8y_blocks(%rip)
movl $_ZGVZ6hostFEffffPiiiiE8y_blocks, %edi
callq __cxa_guard_release
jmp .LBB1_12
.Lfunc_end1:
.size _Z6hostFEffffPiiii, .Lfunc_end1-_Z6hostFEffffPiiii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, %rdi
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12mandelKernelffffPiiii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z12mandelKernelffffPiiii,@object # @_Z12mandelKernelffffPiiii
.section .rodata,"a",@progbits
.globl _Z12mandelKernelffffPiiii
.p2align 3, 0x0
_Z12mandelKernelffffPiiii:
.quad _Z27__device_stub__mandelKernelffffPiiii
.size _Z12mandelKernelffffPiiii, 8
.type _ZZ6hostFEffffPiiiiE8x_blocks,@object # @_ZZ6hostFEffffPiiiiE8x_blocks
.local _ZZ6hostFEffffPiiiiE8x_blocks
.comm _ZZ6hostFEffffPiiiiE8x_blocks,4,4
.type _ZGVZ6hostFEffffPiiiiE8x_blocks,@object # @_ZGVZ6hostFEffffPiiiiE8x_blocks
.local _ZGVZ6hostFEffffPiiiiE8x_blocks
.comm _ZGVZ6hostFEffffPiiiiE8x_blocks,8,8
.type _ZZ6hostFEffffPiiiiE8y_blocks,@object # @_ZZ6hostFEffffPiiiiE8y_blocks
.local _ZZ6hostFEffffPiiiiE8y_blocks
.comm _ZZ6hostFEffffPiiiiE8y_blocks,4,4
.type _ZGVZ6hostFEffffPiiiiE8y_blocks,@object # @_ZGVZ6hostFEffffPiiiiE8y_blocks
.local _ZGVZ6hostFEffffPiiiiE8y_blocks
.comm _ZGVZ6hostFEffffPiiiiE8y_blocks,8,8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z12mandelKernelffffPiiii"
.size .L__unnamed_1, 26
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z27__device_stub__mandelKernelffffPiiii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z12mandelKernelffffPiiii
.addrsig_sym _ZGVZ6hostFEffffPiiiiE8x_blocks
.addrsig_sym _ZGVZ6hostFEffffPiiiiE8y_blocks
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
```
| 4,006 | 4,448 |
522 |
Convert the following CUDA device assembly code to AMD device assembly:
```cudaasm
code for sm_80
Function : _Z20matrixMultiplySharedPfS_S_iiiiii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
MOV R1, c[0x0][0x28] ;
S2R R18, SR_TID.Y ;
MOV R2, c[0x0][0x17c] ;
ULDC.64 UR6, c[0x0][0x118] ;
HFMA2.MMA R7, -RZ, RZ, 0, 0 ;
S2R R0, SR_TID.X ;
ISETP.GE.AND P1, PT, R2, -0x1e, PT ;
S2R R23, SR_CTAID.X ;
S2R R20, SR_CTAID.Y ;
SHF.L.U32 R21, R18, 0x7, RZ ;
LEA R19, R0, R21, 0x2 ;
IMAD R23, R23, c[0x0][0x0], R0 ;
STS [R19], RZ ;
IMAD R20, R20, c[0x0][0x4], R18 ;
STS [R19+0x1000], RZ ;
ISETP.GE.AND P0, PT, R23, c[0x0][0x18c], PT ;
ISETP.GE.OR P0, PT, R20, c[0x0][0x188], P0 ;
@!P1 BRA 0x7a0 ;
IADD3 R2, R2, -0x1, RZ ;
UMOV UR4, 0xffffffff ;
MOV R17, R0 ;
SHF.R.S32.HI R3, RZ, 0x1f, R2 ;
MOV R7, RZ ;
LEA.HI R16, R3, R2, RZ, 0x5 ;
IMAD R3, R18, c[0x0][0x184], R23 ;
IMAD R2, R20, c[0x0][0x17c], R17 ;
SHF.R.S32.HI R16, RZ, 0x5, R16 ;
ISETP.GE.U32.AND P2, PT, R17, c[0x0][0x17c], PT ;
HFMA2.MMA R6, -RZ, RZ, 0, 0 ;
ISETP.GE.U32.AND P1, PT, R18, c[0x0][0x180], PT ;
ISETP.GE.OR P2, PT, R20, c[0x0][0x178], P2 ;
ISETP.GE.OR P1, PT, R23, c[0x0][0x184], P1 ;
MOV R28, RZ ;
@!P2 MOV R5, 0x4 ;
@!P1 MOV R24, 0x4 ;
@!P2 IMAD.WIDE.U32 R4, R2, R5, c[0x0][0x160] ;
@!P1 IMAD.WIDE.U32 R24, R3, R24, c[0x0][0x168] ;
@!P2 LDG.E R6, [R4.64] ;
@!P1 LDG.E R28, [R24.64] ;
UIADD3 UR4, UR4, 0x1, URZ ;
IADD3 R18, R18, 0x20, RZ ;
IADD3 R17, R17, 0x20, RZ ;
IADD3 R2, R2, 0x20, RZ ;
ISETP.LE.AND P1, PT, R16, UR4, PT ;
STS [R19], R6 ;
STS [R19+0x1000], R28 ;
BAR.SYNC.DEFER_BLOCKING 0x0 ;
LDS R29, [R0.X4+0x1000] ;
LDS.128 R8, [R21] ;
LDS R4, [R0.X4+0x1080] ;
LDS R5, [R0.X4+0x1100] ;
LDS R26, [R0.X4+0x1180] ;
LDS R27, [R0.X4+0x1200] ;
LDS.128 R12, [R21+0x10] ;
LDS R22, [R0.X4+0x1280] ;
LDS R25, [R0.X4+0x1300] ;
LDS R24, [R0.X4+0x1380] ;
LDS R28, [R0.X4+0x1a80] ;
FFMA R8, R29, R8, R7 ;
LDS R29, [R0.X4+0x1800] ;
FFMA R9, R4, R9, R8 ;
LDS R8, [R0.X4+0x1480] ;
FFMA R10, R5, R10, R9 ;
LDS R9, [R0.X4+0x1400] ;
FFMA R10, R26, R11, R10 ;
LDS.128 R4, [R21+0x20] ;
LDS R11, [R0.X4+0x1500] ;
FFMA R10, R27, R12, R10 ;
LDS R27, [R0.X4+0x1700] ;
FFMA R10, R22, R13, R10 ;
LDS R22, [R0.X4+0x1580] ;
FFMA R10, R25, R14, R10 ;
LDS R25, [R0.X4+0x1600] ;
FFMA R10, R24, R15, R10 ;
LDS.128 R12, [R21+0x30] ;
LDS R24, [R0.X4+0x1680] ;
LDS R26, [R0.X4+0x1880] ;
FFMA R9, R9, R4, R10 ;
LDS R4, [R0.X4+0x1780] ;
FFMA R5, R8, R5, R9 ;
FFMA R5, R11, R6, R5 ;
LDS.128 R8, [R21+0x40] ;
FFMA R5, R22, R7, R5 ;
LDS R22, [R0.X4+0x1900] ;
FFMA R5, R25, R12, R5 ;
LDS R25, [R0.X4+0x1b00] ;
FFMA R5, R24, R13, R5 ;
LDS R24, [R0.X4+0x1980] ;
FFMA R5, R27, R14, R5 ;
LDS R27, [R0.X4+0x1a00] ;
FFMA R15, R4, R15, R5 ;
LDS.128 R4, [R21+0x50] ;
FFMA R15, R29, R8, R15 ;
LDS R8, [R0.X4+0x1b80] ;
FFMA R9, R26, R9, R15 ;
LDS.128 R12, [R21+0x60] ;
FFMA R10, R22, R10, R9 ;
LDS R9, [R0.X4+0x1c00] ;
LDS R22, [R0.X4+0x1d80] ;
FFMA R10, R24, R11, R10 ;
LDS R11, [R0.X4+0x1d00] ;
FFMA R4, R27, R4, R10 ;
LDS R10, [R0.X4+0x1c80] ;
FFMA R4, R28, R5, R4 ;
LDS R27, [R0.X4+0x1e00] ;
FFMA R4, R25, R6, R4 ;
LDS R25, [R0.X4+0x1f00] ;
FFMA R24, R8, R7, R4 ;
LDS.128 R4, [R21+0x70] ;
FFMA R9, R9, R12, R24 ;
LDS R8, [R0.X4+0x1e80] ;
LDS R12, [R0.X4+0x1f80] ;
FFMA R9, R10, R13, R9 ;
FFMA R9, R11, R14, R9 ;
FFMA R9, R22, R15, R9 ;
FFMA R4, R27, R4, R9 ;
FFMA R4, R8, R5, R4 ;
HFMA2.MMA R8, -RZ, RZ, 0, 1.9073486328125e-06 ;
FFMA R4, R25, R6, R4 ;
FFMA R7, R12, R7, R4 ;
IMAD R3, R8, c[0x0][0x184], R3 ;
@!P1 BRA 0x1b0 ;
@P0 EXIT ;
MOV R3, 0x4 ;
IMAD R2, R20, c[0x0][0x18c], R23 ;
IMAD.WIDE R2, R2, R3, c[0x0][0x170] ;
STG.E [R2.64], R7 ;
EXIT ;
BRA 0x800;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
```
|
```amdasm
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z20matrixMultiplySharedPfS_S_iiiiii ; -- Begin function _Z20matrixMultiplySharedPfS_S_iiiiii
.globl _Z20matrixMultiplySharedPfS_S_iiiiii
.p2align 8
.type _Z20matrixMultiplySharedPfS_S_iiiiii,@function
_Z20matrixMultiplySharedPfS_S_iiiiii: ; @_Z20matrixMultiplySharedPfS_S_iiiiii
; %bb.0:
s_clause 0x4
s_load_b32 s16, s[0:1], 0x3c
s_load_b128 s[4:7], s[0:1], 0x18
s_load_b128 s[8:11], s[0:1], 0x0
s_load_b64 s[2:3], s[0:1], 0x10
s_load_b64 s[12:13], s[0:1], 0x28
v_and_b32_e32 v3, 0x3ff, v0
v_bfe_u32 v4, v0, 10, 10
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b32_e32 v5, 2, v3
v_lshl_add_u32 v7, v4, 7, v5
s_waitcnt lgkmcnt(0)
s_lshr_b32 s0, s16, 16
s_and_b32 s1, s16, 0xffff
v_mad_u64_u32 v[0:1], null, s15, s0, v[4:5]
v_mad_u64_u32 v[1:2], null, s14, s1, v[3:4]
v_mov_b32_e32 v2, 0
s_cmpk_lt_i32 s5, 0xffe2
ds_store_2addr_stride64_b32 v7, v2, v2 offset1:16
s_cbranch_scc1 .LBB0_14
; %bb.1: ; %.lr.ph
s_add_i32 s0, s5, -1
v_mul_lo_u32 v9, v0, s5
s_ashr_i32 s1, s0, 31
v_add_nc_u32_e32 v8, 0x1000, v7
s_lshr_b32 s1, s1, 27
v_cmp_gt_i32_e32 vcc_lo, s4, v0
s_add_i32 s1, s0, s1
v_cmp_gt_i32_e64 s0, s7, v1
v_lshlrev_b32_e32 v10, 7, v4
v_lshl_or_b32 v11, v3, 2, 0x1000
v_mov_b32_e32 v6, 0
v_mov_b32_e32 v2, 0
s_ashr_i32 s4, s1, 5
s_mov_b32 s14, 0
.LBB0_2: ; =>This Loop Header: Depth=1
; Child Loop BB0_11 Depth 2
v_mov_b32_e32 v5, 0
s_and_saveexec_b32 s15, vcc_lo
s_cbranch_execz .LBB0_6
; %bb.3: ; in Loop: Header=BB0_2 Depth=1
v_lshl_add_u32 v12, s14, 5, v3
v_mov_b32_e32 v5, 0
s_mov_b32 s16, exec_lo
s_delay_alu instid0(VALU_DEP_2)
v_cmpx_gt_u32_e64 s5, v12
s_cbranch_execz .LBB0_5
; %bb.4: ; in Loop: Header=BB0_2 Depth=1
v_add_nc_u32_e32 v5, v12, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[12:13], 2, v[5:6]
v_add_co_u32 v12, s1, s8, v12
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v13, s1, s9, v13, s1
global_load_b32 v5, v[12:13], off
.LBB0_5: ; %Flow84
; in Loop: Header=BB0_2 Depth=1
s_or_b32 exec_lo, exec_lo, s16
.LBB0_6: ; in Loop: Header=BB0_2 Depth=1
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s15
v_mov_b32_e32 v12, 0
s_waitcnt vmcnt(0)
ds_store_b32 v7, v5
s_and_saveexec_b32 s15, s0
s_cbranch_execz .LBB0_10
; %bb.7: ; in Loop: Header=BB0_2 Depth=1
v_lshl_add_u32 v5, s14, 5, v4
v_mov_b32_e32 v12, 0
s_mov_b32 s16, exec_lo
s_delay_alu instid0(VALU_DEP_2)
v_cmpx_gt_u32_e64 s6, v5
s_cbranch_execz .LBB0_9
; %bb.8: ; in Loop: Header=BB0_2 Depth=1
v_mad_u64_u32 v[12:13], null, v5, s7, v[1:2]
v_mov_b32_e32 v13, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[12:13], 2, v[12:13]
v_add_co_u32 v12, s1, s10, v12
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v13, s1, s11, v13, s1
global_load_b32 v12, v[12:13], off
.LBB0_9: ; %Flow
; in Loop: Header=BB0_2 Depth=1
s_or_b32 exec_lo, exec_lo, s16
.LBB0_10: ; in Loop: Header=BB0_2 Depth=1
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s15
v_mov_b32_e32 v5, v11
s_mov_b32 s1, 0
s_waitcnt vmcnt(0)
ds_store_b32 v8, v12
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
.LBB0_11: ; Parent Loop BB0_2 Depth=1
; => This Inner Loop Header: Depth=2
v_add_nc_u32_e32 v12, s1, v10
s_add_i32 s1, s1, 4
ds_load_b32 v13, v5
ds_load_b32 v12, v12
v_add_nc_u32_e32 v5, 0x80, v5
s_cmpk_eq_i32 s1, 0x80
s_waitcnt lgkmcnt(0)
v_fmac_f32_e32 v2, v12, v13
s_cbranch_scc0 .LBB0_11
; %bb.12: ; in Loop: Header=BB0_2 Depth=1
s_add_i32 s1, s14, 1
s_cmp_eq_u32 s14, s4
s_cbranch_scc1 .LBB0_14
; %bb.13: ; in Loop: Header=BB0_2 Depth=1
s_mov_b32 s14, s1
s_branch .LBB0_2
.LBB0_14: ; %Flow86
v_cmp_gt_i32_e32 vcc_lo, s12, v0
v_cmp_gt_i32_e64 s0, s13, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s0, vcc_lo, s0
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_16
; %bb.15:
v_mad_u64_u32 v[3:4], null, v0, s13, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v4, 31, v3
v_lshlrev_b64 v[0:1], 2, v[3:4]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_store_b32 v[0:1], v2, off
.LBB0_16:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z20matrixMultiplySharedPfS_S_iiiiii
.amdhsa_group_segment_fixed_size 8192
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 304
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 14
.amdhsa_next_free_sgpr 17
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z20matrixMultiplySharedPfS_S_iiiiii, .Lfunc_end0-_Z20matrixMultiplySharedPfS_S_iiiiii
; -- End function
.section .AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 616
; NumSgprs: 19
; NumVgprs: 14
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 8192 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 19
; NumVGPRsForWavesPerEU: 14
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object ; @__hip_cuid_
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0 ; 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 36
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: by_value
- .offset: 44
.size: 4
.value_kind: by_value
- .offset: 48
.size: 4
.value_kind: hidden_block_count_x
- .offset: 52
.size: 4
.value_kind: hidden_block_count_y
- .offset: 56
.size: 4
.value_kind: hidden_block_count_z
- .offset: 60
.size: 2
.value_kind: hidden_group_size_x
- .offset: 62
.size: 2
.value_kind: hidden_group_size_y
- .offset: 64
.size: 2
.value_kind: hidden_group_size_z
- .offset: 66
.size: 2
.value_kind: hidden_remainder_x
- .offset: 68
.size: 2
.value_kind: hidden_remainder_y
- .offset: 70
.size: 2
.value_kind: hidden_remainder_z
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 112
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 8192
.kernarg_segment_align: 8
.kernarg_segment_size: 304
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z20matrixMultiplySharedPfS_S_iiiiii
.private_segment_fixed_size: 0
.sgpr_count: 19
.sgpr_spill_count: 0
.symbol: _Z20matrixMultiplySharedPfS_S_iiiiii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 14
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
```
| 2,473 | 4,523 |
523 |
Convert the following CUDA host assembly code to AMD host assembly:
```cudaasm
.file "tmpxft_001bc1ff_00000000-6_matrixMultiplyShared.cudafe1.cpp"
.text
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z50__device_stub__Z20matrixMultiplySharedPfS_S_iiiiiiPfS_S_iiiiii
.type _Z50__device_stub__Z20matrixMultiplySharedPfS_S_iiiiiiPfS_S_iiiiii, @function
_Z50__device_stub__Z20matrixMultiplySharedPfS_S_iiiiiiPfS_S_iiiiii:
.LFB2051:
.cfi_startproc
endbr64
subq $200, %rsp
.cfi_def_cfa_offset 208
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
leaq 208(%rsp), %rax
movq %rax, 160(%rsp)
leaq 216(%rsp), %rax
movq %rax, 168(%rsp)
leaq 224(%rsp), %rax
movq %rax, 176(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 216
pushq 56(%rsp)
.cfi_def_cfa_offset 224
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z20matrixMultiplySharedPfS_S_iiiiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 208
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z50__device_stub__Z20matrixMultiplySharedPfS_S_iiiiiiPfS_S_iiiiii, .-_Z50__device_stub__Z20matrixMultiplySharedPfS_S_iiiiiiPfS_S_iiiiii
.globl _Z20matrixMultiplySharedPfS_S_iiiiii
.type _Z20matrixMultiplySharedPfS_S_iiiiii, @function
_Z20matrixMultiplySharedPfS_S_iiiiii:
.LFB2052:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 40
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 48
call _Z50__device_stub__Z20matrixMultiplySharedPfS_S_iiiiiiPfS_S_iiiiii
addq $40, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z20matrixMultiplySharedPfS_S_iiiiii, .-_Z20matrixMultiplySharedPfS_S_iiiiii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z20matrixMultiplySharedPfS_S_iiiiii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z20matrixMultiplySharedPfS_S_iiiiii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
```
|
```amdasm
.text
.file "matrixMultiplyShared.hip"
.globl _Z35__device_stub__matrixMultiplySharedPfS_S_iiiiii # -- Begin function _Z35__device_stub__matrixMultiplySharedPfS_S_iiiiii
.type _Z35__device_stub__matrixMultiplySharedPfS_S_iiiiii,@function
_Z35__device_stub__matrixMultiplySharedPfS_S_iiiiii: # @_Z35__device_stub__matrixMultiplySharedPfS_S_iiiiii
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $176, %rsp
.cfi_def_cfa_offset 224
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 56(%rsp), %rax
movq %rdi, (%rax)
leaq 48(%rsp), %rdi
movq %rsi, (%rdi)
leaq 40(%rsp), %rsi
movq %rdx, (%rsi)
leaq 20(%rsp), %rdx
movl %ecx, (%rdx)
leaq 16(%rsp), %rcx
movl %r8d, (%rcx)
leaq 12(%rsp), %r8
movl %r9d, (%r8)
leaq 96(%rsp), %rbx
movq %rax, (%rbx)
movq %rdi, 8(%rbx)
movq %rsi, 16(%rbx)
movq %rdx, 24(%rbx)
movq %rcx, 32(%rbx)
movq %r8, 40(%rbx)
leaq 224(%rsp), %rax
movq %rax, 48(%rbx)
leaq 232(%rsp), %rax
movq %rax, 56(%rbx)
leaq 240(%rsp), %rax
movq %rax, 64(%rbx)
leaq 80(%rsp), %r14
leaq 64(%rsp), %r15
leaq 32(%rsp), %r12
leaq 24(%rsp), %r13
movq %r14, %rdi
movq %r15, %rsi
movq %r12, %rdx
movq %r13, %rcx
callq __hipPopCallConfiguration
movq (%r14), %rsi
movl 8(%r14), %edx
movq (%r15), %rcx
movl 8(%r15), %r8d
movl $_Z20matrixMultiplySharedPfS_S_iiiiii, %edi
movq %rbx, %r9
pushq (%r13)
.cfi_adjust_cfa_offset 8
pushq (%r12)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $192, %rsp
.cfi_adjust_cfa_offset -192
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z35__device_stub__matrixMultiplySharedPfS_S_iiiiii, .Lfunc_end0-_Z35__device_stub__matrixMultiplySharedPfS_S_iiiiii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, %rdi
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z20matrixMultiplySharedPfS_S_iiiiii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z20matrixMultiplySharedPfS_S_iiiiii,@object # @_Z20matrixMultiplySharedPfS_S_iiiiii
.section .rodata,"a",@progbits
.globl _Z20matrixMultiplySharedPfS_S_iiiiii
.p2align 3, 0x0
_Z20matrixMultiplySharedPfS_S_iiiiii:
.quad _Z35__device_stub__matrixMultiplySharedPfS_S_iiiiii
.size _Z20matrixMultiplySharedPfS_S_iiiiii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z20matrixMultiplySharedPfS_S_iiiiii"
.size .L__unnamed_1, 37
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z35__device_stub__matrixMultiplySharedPfS_S_iiiiii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z20matrixMultiplySharedPfS_S_iiiiii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
```
| 2,230 | 2,312 |
528 |
Convert the following CUDA device assembly code to AMD device assembly:
```cudaasm
code for sm_80
Function : _Z12generate_GPUPdi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ;
S2R R0, SR_CTAID.X ;
S2R R3, SR_TID.X ;
IMAD R0, R0, c[0x0][0x0], R3 ;
ISETP.GE.AND P0, PT, R0, c[0x0][0x168], PT ;
@P0 EXIT ;
ULDC.64 UR4, c[0x0][0x118] ;
LEA R2, R0, 0x1, 0x1 ;
IMAD.MOV.U32 R4, RZ, RZ, 0x1 ;
BSSY B0, 0x1a0 ;
I2F.F64 R2, R2 ;
MUFU.RCP64H R5, R3 ;
DFMA R6, -R2, R4, 1 ;
DFMA R6, R6, R6, R6 ;
DFMA R6, R4, R6, R4 ;
DFMA R4, -R2, R6, 1 ;
DFMA R4, R6, R4, R6 ;
DMUL R6, R4, 4 ;
DFMA R8, -R2, R6, 4 ;
DFMA R4, R4, R8, R6 ;
FFMA R6, RZ, R3, R5 ;
FSETP.GT.AND P0, PT, |R6|, 1.469367938527859385e-39, PT ;
@P0 BRA 0x190 ;
MOV R6, 0x190 ;
CALL.REL.NOINC 0x280 ;
BSYNC B0 ;
LOP3.LUT R3, R0, 0x1, RZ, 0xc0, !PT ;
IMAD.MOV.U32 R2, RZ, RZ, 0x3ff00000 ;
IMAD.MOV.U32 R7, RZ, RZ, 0x8 ;
ISETP.NE.U32.AND P0, PT, R3, 0x1, PT ;
FSEL R3, -R2, 1.875, !P0 ;
IMAD.MOV.U32 R2, RZ, RZ, RZ ;
DMUL R4, R4, R2 ;
IMAD.WIDE R2, R0, R7, c[0x0][0x160] ;
IMAD.MOV.U32 R7, RZ, RZ, c[0x0][0xc] ;
STG.E.64 [R2.64], R4 ;
IADD3 R0, R0, c[0x0][0x0], R7 ;
ISETP.GE.AND P0, PT, R0, c[0x0][0x168], PT ;
@!P0 BRA 0x70 ;
EXIT ;
FSETP.GEU.AND P0, PT, |R3|.reuse, 1.469367938527859385e-39, PT ;
IMAD.MOV.U32 R8, RZ, RZ, 0x1 ;
LOP3.LUT R4, R3.reuse, 0x800fffff, RZ, 0xc0, !PT ;
IMAD.MOV.U32 R16, RZ, RZ, 0x40100000 ;
LOP3.LUT R7, R3, 0x7ff00000, RZ, 0xc0, !PT ;
IMAD.MOV.U32 R17, RZ, RZ, 0x1ca00000 ;
LOP3.LUT R5, R4, 0x3ff00000, RZ, 0xfc, !PT ;
IMAD.MOV.U32 R4, RZ, RZ, R2 ;
ISETP.LE.U32.AND P1, PT, R7, 0x40100000, PT ;
BSSY B1, 0x720 ;
IADD3 R14, R16, -0x1, RZ ;
@!P0 DMUL R4, R2, 8.98846567431157953865e+307 ;
MUFU.RCP64H R9, R5 ;
@!P0 LOP3.LUT R7, R5, 0x7ff00000, RZ, 0xc0, !PT ;
ISETP.GT.U32.AND P0, PT, R14, 0x7feffffe, PT ;
IADD3 R18, R7, -0x1, RZ ;
ISETP.GT.U32.OR P0, PT, R18, 0x7feffffe, P0 ;
DFMA R10, R8, -R4, 1 ;
DFMA R10, R10, R10, R10 ;
DFMA R10, R8, R10, R8 ;
SEL R9, R17, 0x63400000, !P1 ;
IMAD.MOV.U32 R8, RZ, RZ, RZ ;
DFMA R12, R10, -R4, 1 ;
DFMA R10, R10, R12, R10 ;
DMUL R12, R10, R8 ;
DFMA R14, R12, -R4, R8 ;
DFMA R10, R10, R14, R12 ;
@P0 BRA 0x600 ;
LOP3.LUT R12, R3, 0x7ff00000, RZ, 0xc0, !PT ;
IMAD.MOV.U32 R14, RZ, RZ, RZ ;
IADD3 R7, -R12.reuse, 0x40100000, RZ ;
ISETP.LE.U32.AND P0, PT, R12, 0x40100000, PT ;
IMNMX R7, R7, -0x46a00000, !PT ;
SEL R12, R17, 0x63400000, !P0 ;
IMNMX R7, R7, 0x46a00000, PT ;
IMAD.IADD R16, R7, 0x1, -R12 ;
IADD3 R15, R16, 0x7fe00000, RZ ;
DMUL R12, R10, R14 ;
FSETP.GTU.AND P0, PT, |R13|, 1.469367938527859385e-39, PT ;
@P0 BRA 0x710 ;
DFMA R4, R10, -R4, R8 ;
IMAD.MOV.U32 R14, RZ, RZ, RZ ;
FSETP.NEU.AND P0, PT, R5.reuse, RZ, PT ;
LOP3.LUT R7, R5, 0x80000000, R3, 0x48, !PT ;
LOP3.LUT R15, R7, R15, RZ, 0xfc, !PT ;
@!P0 BRA 0x710 ;
IMAD.MOV R3, RZ, RZ, -R16 ;
IMAD.MOV.U32 R2, RZ, RZ, RZ ;
DFMA R2, R12, -R2, R10 ;
DMUL.RP R10, R10, R14 ;
IADD3 R2, -R16, -0x43300000, RZ ;
FSETP.NEU.AND P0, PT, |R3|, R2, PT ;
LOP3.LUT R7, R11, R7, RZ, 0x3c, !PT ;
FSEL R12, R10, R12, !P0 ;
FSEL R13, R7, R13, !P0 ;
BRA 0x710 ;
DSETP.NAN.AND P0, PT, R2, R2, PT ;
@P0 BRA 0x6f0 ;
ISETP.NE.AND P0, PT, R16, R7, PT ;
IMAD.MOV.U32 R12, RZ, RZ, 0x0 ;
IMAD.MOV.U32 R13, RZ, RZ, -0x80000 ;
@!P0 BRA 0x710 ;
ISETP.NE.AND P0, PT, R16, 0x7ff00000, PT ;
LOP3.LUT R2, R3, 0x40100000, RZ, 0x3c, !PT ;
ISETP.EQ.OR P0, PT, R7, RZ, !P0 ;
LOP3.LUT R13, R2, 0x80000000, RZ, 0xc0, !PT ;
@P0 LOP3.LUT R2, R13, 0x7ff00000, RZ, 0xfc, !PT ;
@!P0 IMAD.MOV.U32 R12, RZ, RZ, RZ ;
@P0 IMAD.MOV.U32 R12, RZ, RZ, RZ ;
@P0 IMAD.MOV.U32 R13, RZ, RZ, R2 ;
BRA 0x710 ;
LOP3.LUT R13, R3, 0x80000, RZ, 0xfc, !PT ;
IMAD.MOV.U32 R12, RZ, RZ, R2 ;
BSYNC B1 ;
IMAD.MOV.U32 R7, RZ, RZ, 0x0 ;
IMAD.MOV.U32 R4, RZ, RZ, R12 ;
IMAD.MOV.U32 R5, RZ, RZ, R13 ;
RET.REL.NODEC R6 0x0 ;
BRA 0x760;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
Function : _Z20add_components_GPU_2PdS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ;
IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x170] ;
S2R R5, SR_CTAID.X ;
ISETP.GE.AND P0, PT, R0, 0x1, PT ;
@!P0 EXIT ;
IABS R7, c[0x0][0x170] ;
S2R R4, SR_TID.X ;
IMAD.MOV.U32 R12, RZ, RZ, 0x8 ;
ULDC.64 UR4, c[0x0][0x118] ;
I2F.RP R0, R7 ;
BSSY B0, 0x3d0 ;
MUFU.RCP R0, R0 ;
IMAD R5, R5, c[0x0][0x0], R4 ;
IMAD R5, R5, c[0x0][0x170], RZ ;
IADD3 R2, R0, 0xffffffe, RZ ;
IABS R0, R5 ;
F2I.FTZ.U32.TRUNC.NTZ R3, R2 ;
IMAD.MOV.U32 R2, RZ, RZ, RZ ;
IMAD.MOV R6, RZ, RZ, -R3 ;
IMAD.MOV.U32 R4, RZ, RZ, R6 ;
IMAD R9, R4, R7, RZ ;
IMAD.HI.U32 R3, R3, R9, R2 ;
IMAD.HI.U32 R3, R3, R0, RZ ;
IMAD.MOV R2, RZ, RZ, -R3 ;
IMAD R0, R7, R2, R0 ;
LOP3.LUT R2, R5, c[0x0][0x170], RZ, 0x3c, !PT ;
ISETP.GT.U32.AND P0, PT, R7, R0, PT ;
ISETP.GE.AND P2, PT, R2, RZ, PT ;
@!P0 IADD3 R0, R0, -R7.reuse, RZ ;
@!P0 IADD3 R3, R3, 0x1, RZ ;
ISETP.GE.U32.AND P1, PT, R0, R7, PT ;
IADD3 R0, R5.reuse, c[0x0][0x170], RZ ;
IADD3 R7, R5, 0x1, RZ ;
ISETP.NE.AND P0, PT, RZ, c[0x0][0x170], PT ;
IMNMX R2, R0, R7, !PT ;
LOP3.LUT R7, RZ, R5, RZ, 0x33, !PT ;
@P1 IADD3 R3, R3, 0x1, RZ ;
IMAD.IADD R4, R2.reuse, 0x1, -R5 ;
IMAD.IADD R7, R2, 0x1, R7 ;
@!P2 IMAD.MOV R3, RZ, RZ, -R3 ;
LOP3.LUT P2, R4, R4, 0x3, RZ, 0xc0, !PT ;
@!P0 LOP3.LUT R3, RZ, c[0x0][0x170], RZ, 0x33, !PT ;
ISETP.GE.U32.AND P1, PT, R7, 0x3, PT ;
IMAD.WIDE R2, R3, R12, c[0x0][0x168] ;
@!P2 BRA 0x3c0 ;
LDG.E.64 R8, [R2.64] ;
IMAD.WIDE R6, R5, R12, c[0x0][0x160] ;
IMAD.MOV.U32 R11, RZ, RZ, R7 ;
MOV R10, R6 ;
IMAD.MOV.U32 R6, RZ, RZ, R10 ;
IMAD.MOV.U32 R7, RZ, RZ, R11 ;
LDG.E.64 R6, [R6.64] ;
IADD3 R4, R4, -0x1, RZ ;
IADD3 R10, P2, R10, 0x8, RZ ;
ISETP.NE.AND P0, PT, R4, RZ, PT ;
IADD3 R5, R5, 0x1, RZ ;
IMAD.X R11, RZ, RZ, R11, P2 ;
DADD R8, R6, R8 ;
STG.E.64 [R2.64], R8 ;
@P0 BRA 0x310 ;
BSYNC B0 ;
@!P1 EXIT ;
LDG.E.64 R8, [R2.64] ;
IMAD.WIDE R6, R5, R12, c[0x0][0x160] ;
IADD3 R4, P0, R6, 0x10, RZ ;
IADD3.X R7, RZ, R7, RZ, P0, !PT ;
IMAD.MOV.U32 R14, RZ, RZ, R4 ;
IMAD.MOV.U32 R15, RZ, RZ, R7 ;
LDG.E.64 R6, [R14.64+-0x10] ;
DADD R6, R6, R8 ;
STG.E.64 [R2.64], R6 ;
LDG.E.64 R8, [R14.64+-0x8] ;
DADD R10, R6, R8 ;
STG.E.64 [R2.64], R10 ;
LDG.E.64 R8, [R14.64] ;
DADD R12, R10, R8 ;
STG.E.64 [R2.64], R12 ;
LDG.E.64 R8, [R14.64+0x8] ;
IADD3 R5, R5, 0x4, RZ ;
IADD3 R4, P1, R14, 0x20, RZ ;
ISETP.GE.AND P0, PT, R5, R0, PT ;
IMAD.X R7, RZ, RZ, R15, P1 ;
DADD R8, R12, R8 ;
STG.E.64 [R2.64], R8 ;
@!P0 BRA 0x420 ;
EXIT ;
BRA 0x560;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
```
|
```amdasm
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z20add_components_GPU_2PdS_i ; -- Begin function _Z20add_components_GPU_2PdS_i
.globl _Z20add_components_GPU_2PdS_i
.p2align 8
.type _Z20add_components_GPU_2PdS_i,@function
_Z20add_components_GPU_2PdS_i: ; @_Z20add_components_GPU_2PdS_i
; %bb.0:
s_load_b32 s2, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s2, 1
s_cbranch_scc1 .LBB0_3
; %bb.1: ; %.lr.ph
s_load_b32 s3, s[0:1], 0x24
s_ashr_i32 s4, s2, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s5, s2, s4
s_xor_b32 s5, s5, s4
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_f32_u32_e32 v1, s5
v_rcp_iflag_f32_e32 v1, v1
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v3, 0x4f7ffffe, v1
v_mad_u64_u32 v[1:2], null, s15, s3, v[0:1]
s_sub_i32 s3, 0, s5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cvt_u32_f32_e32 v2, v3
v_mul_lo_u32 v0, v1, s2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_lo_u32 v3, s3, v2
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_hi_u32 v3, v2, v3
v_add_nc_u32_e32 v4, v0, v1
v_lshlrev_b64 v[6:7], 3, v[0:1]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_nc_u32_e32 v2, v2, v3
v_xor_b32_e32 v3, v4, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v2, v3, v2
v_mul_lo_u32 v4, v2, s5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v3, v3, v4
v_add_nc_u32_e32 v4, 1, v2
v_subrev_nc_u32_e32 v5, s5, v3
v_cmp_le_u32_e32 vcc_lo, s5, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_dual_cndmask_b32 v3, v3, v5 :: v_dual_cndmask_b32 v2, v2, v4
v_xor_b32_e32 v5, s4, v1
v_add_nc_u32_e32 v1, s2, v0
v_cmp_le_u32_e32 vcc_lo, s5, v3
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v4, 1, v2
s_load_b128 s[4:7], s[0:1], 0x0
s_mov_b32 s1, 0
v_cndmask_b32_e32 v2, v2, v4, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_xor_b32_e32 v2, v2, v5
v_sub_nc_u32_e32 v2, v2, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[2:3], 3, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s6, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v3, vcc_lo
v_add_co_u32 v6, vcc_lo, s4, v6
v_add_co_ci_u32_e32 v7, vcc_lo, s5, v7, vcc_lo
global_load_b64 v[4:5], v[2:3], off
.LBB0_2: ; =>This Inner Loop Header: Depth=1
global_load_b64 v[8:9], v[6:7], off
v_add_nc_u32_e32 v0, 1, v0
v_add_co_u32 v6, s0, v6, 8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e64 v7, s0, 0, v7, s0
v_cmp_ge_i32_e32 vcc_lo, v0, v1
s_or_b32 s1, vcc_lo, s1
s_waitcnt vmcnt(0)
v_add_f64 v[4:5], v[8:9], v[4:5]
global_store_b64 v[2:3], v[4:5], off
s_and_not1_b32 exec_lo, exec_lo, s1
s_cbranch_execnz .LBB0_2
.LBB0_3: ; %._crit_edge
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z20add_components_GPU_2PdS_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 10
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z20add_components_GPU_2PdS_i, .Lfunc_end0-_Z20add_components_GPU_2PdS_i
; -- End function
.section .AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 396
; NumSgprs: 18
; NumVgprs: 10
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 10
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
.text
.protected _Z12generate_GPUPdi ; -- Begin function _Z12generate_GPUPdi
.globl _Z12generate_GPUPdi
.p2align 8
.type _Z12generate_GPUPdi,@function
_Z12generate_GPUPdi: ; @_Z12generate_GPUPdi
; %bb.0:
s_clause 0x1
s_load_b32 s5, s[0:1], 0x1c
s_load_b32 s4, s[0:1], 0x8
s_add_u32 s2, s0, 16
s_addc_u32 s3, s1, 0
s_mov_b32 s6, exec_lo
s_waitcnt lgkmcnt(0)
s_and_b32 s5, s5, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s5, v[0:1]
v_cmpx_gt_i32_e64 s4, v1
s_cbranch_execz .LBB1_3
; %bb.1: ; %.lr.ph
s_load_b32 s6, s[2:3], 0x0
s_load_b64 s[2:3], s[0:1], 0x0
v_lshl_or_b32 v0, v1, 1, 1
s_mov_b32 s7, 0
s_waitcnt lgkmcnt(0)
s_add_i32 s5, s6, s5
s_delay_alu instid0(SALU_CYCLE_1)
s_lshl_b32 s6, s5, 1
.LBB1_2: ; =>This Inner Loop Header: Depth=1
v_cvt_f64_i32_e32 v[2:3], v0
v_add_nc_u32_e32 v0, s6, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_div_scale_f64 v[4:5], null, v[2:3], v[2:3], 4.0
v_div_scale_f64 v[10:11], vcc_lo, 4.0, v[2:3], 4.0
v_rcp_f64_e32 v[6:7], v[4:5]
s_waitcnt_depctr 0xfff
v_fma_f64 v[8:9], -v[4:5], v[6:7], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[6:7], v[6:7], v[8:9], v[6:7]
v_fma_f64 v[8:9], -v[4:5], v[6:7], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[6:7], v[6:7], v[8:9], v[6:7]
v_mul_f64 v[8:9], v[10:11], v[6:7]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[4:5], -v[4:5], v[8:9], v[10:11]
v_div_fmas_f64 v[4:5], v[4:5], v[6:7], v[8:9]
v_and_b32_e32 v7, 1, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cmp_eq_u32_e64 s0, 0, v7
v_div_fixup_f64 v[3:4], v[4:5], v[2:3], 4.0
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[5:6], 3, v[1:2]
v_add_nc_u32_e32 v1, s5, v1
v_cmp_le_i32_e32 vcc_lo, s4, v1
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v5, s1, s2, v5
v_add_co_ci_u32_e64 v6, s1, s3, v6, s1
s_or_b32 s7, vcc_lo, s7
v_xor_b32_e32 v2, 0x80000000, v4
v_cndmask_b32_e64 v3, v3, v3, s0
s_delay_alu instid0(VALU_DEP_2)
v_cndmask_b32_e64 v4, v2, v4, s0
global_store_b64 v[5:6], v[3:4], off
s_and_not1_b32 exec_lo, exec_lo, s7
s_cbranch_execnz .LBB1_2
.LBB1_3: ; %Flow14
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z12generate_GPUPdi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 12
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z12generate_GPUPdi, .Lfunc_end1-_Z12generate_GPUPdi
; -- End function
.section .AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 344
; NumSgprs: 18
; NumVgprs: 12
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 12
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object ; @__hip_cuid_
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0 ; 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z20add_components_GPU_2PdS_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z20add_components_GPU_2PdS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 10
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z12generate_GPUPdi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z12generate_GPUPdi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 12
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
```
| 4,201 | 6,541 |
529 |
Convert the following CUDA host assembly code to AMD host assembly:
```cudaasm
.file "tmpxft_000372fc_00000000-6_pi.cudafe1.cpp"
.text
.globl _ZSt21ios_base_library_initv
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3955:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3955:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z19generate_componentsPdi
.type _Z19generate_componentsPdi, @function
_Z19generate_componentsPdi:
.LFB3950:
.cfi_startproc
endbr64
addl %esi, %esi
cmpl $1, %esi
jle .L3
addl $1, %esi
movl $1, %edx
movl $1, %ecx
movsd .LC0(%rip), %xmm2
.L5:
movl %edx, %eax
shrl $31, %eax
addl %edx, %eax
sarl %eax
cltq
pxor %xmm1, %xmm1
cvtsi2sdl %edx, %xmm1
movapd %xmm2, %xmm0
divsd %xmm1, %xmm0
pxor %xmm1, %xmm1
cvtsi2sdl %ecx, %xmm1
mulsd %xmm1, %xmm0
movsd %xmm0, (%rdi,%rax,8)
negl %ecx
addl $2, %edx
cmpl %esi, %edx
jne .L5
.L3:
ret
.cfi_endproc
.LFE3950:
.size _Z19generate_componentsPdi, .-_Z19generate_componentsPdi
.globl _Z14add_componentsPdi
.type _Z14add_componentsPdi, @function
_Z14add_componentsPdi:
.LFB3951:
.cfi_startproc
endbr64
testl %esi, %esi
jle .L10
movq %rdi, %rax
movslq %esi, %rsi
leaq (%rdi,%rsi,8), %rdx
pxor %xmm0, %xmm0
.L9:
addsd (%rax), %xmm0
addq $8, %rax
cmpq %rdx, %rax
jne .L9
ret
.L10:
pxor %xmm0, %xmm0
ret
.cfi_endproc
.LFE3951:
.size _Z14add_componentsPdi, .-_Z14add_componentsPdi
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "comp "
.LC3:
.string ": "
.LC4:
.string "\n"
.text
.globl _Z16print_componentsPdi
.type _Z16print_componentsPdi, @function
_Z16print_componentsPdi:
.LFB3952:
.cfi_startproc
endbr64
testl %esi, %esi
jle .L17
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $8, %rsp
.cfi_def_cfa_offset 64
movq %rdi, %r14
movslq %esi, %r13
movl $0, %ebx
leaq .LC2(%rip), %r15
leaq _ZSt4cout(%rip), %r12
.L14:
movl $5, %edx
movq %r15, %rsi
movq %r12, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl %ebx, %esi
movq %r12, %rdi
call _ZNSolsEi@PLT
movq %rax, %rbp
movl $2, %edx
leaq .LC3(%rip), %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movsd (%r14,%rbx,8), %xmm0
movq %rbp, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
movl $1, %edx
leaq .LC4(%rip), %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
addq $1, %rbx
cmpq %rbx, %r13
jne .L14
addq $8, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L17:
.cfi_restore 3
.cfi_restore 6
.cfi_restore 12
.cfi_restore 13
.cfi_restore 14
.cfi_restore 15
ret
.cfi_endproc
.LFE3952:
.size _Z16print_componentsPdi, .-_Z16print_componentsPdi
.globl _Z43__device_stub__Z20add_components_GPU_2PdS_iPdS_i
.type _Z43__device_stub__Z20add_components_GPU_2PdS_iPdS_i, @function
_Z43__device_stub__Z20add_components_GPU_2PdS_iPdS_i:
.LFB3977:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L24
.L20:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L25
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L24:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z20add_components_GPU_2PdS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L20
.L25:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3977:
.size _Z43__device_stub__Z20add_components_GPU_2PdS_iPdS_i, .-_Z43__device_stub__Z20add_components_GPU_2PdS_iPdS_i
.globl _Z20add_components_GPU_2PdS_i
.type _Z20add_components_GPU_2PdS_i, @function
_Z20add_components_GPU_2PdS_i:
.LFB3978:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z43__device_stub__Z20add_components_GPU_2PdS_iPdS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3978:
.size _Z20add_components_GPU_2PdS_i, .-_Z20add_components_GPU_2PdS_i
.section .rodata.str1.1
.LC5:
.string "n: "
.LC6:
.string "\n\n"
.LC7:
.string "pi_constant: "
.LC9:
.string "\n\nCPU\n"
.LC10:
.string "pi CPU: "
.LC11:
.string "Czas_CPU: "
.LC13:
.string " ms"
.LC14:
.string "pi_error: "
.LC15:
.string "cudaMalloc failed!\n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC16:
.string "add_components_GPU_2 launch failed: %s\n"
.section .rodata.str1.1
.LC17:
.string "\n\nGPU\n"
.LC18:
.string "pi GPU: "
.LC19:
.string "Czas_GPU: "
.LC20:
.string "Speedup: "
.text
.globl main
.type main, @function
main:
.LFB3949:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $64, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
leaq .LC5(%rip), %rsi
leaq _ZSt4cout(%rip), %rbp
movq %rbp, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl $600000000, %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
leaq .LC6(%rip), %r13
movq %r13, %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movabsq $4800000000, %rdi
call malloc@PLT
movq %rax, %rbx
movl $600000000, %esi
movq %rax, %rdi
call _Z19generate_componentsPdi
call clock@PLT
movq %rax, %r14
movl $600000000, %esi
movq %rbx, %rdi
call _Z14add_componentsPdi
movsd %xmm0, 8(%rsp)
call clock@PLT
movq %rax, %r12
leaq .LC7(%rip), %rsi
movq %rbp, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movq (%rax), %rax
movq -24(%rax), %rax
movq $50, 8(%rdi,%rax)
movsd .LC8(%rip), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
movq %r13, %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
leaq .LC9(%rip), %rsi
movq %rbp, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
leaq .LC10(%rip), %rsi
movq %rbp, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movq (%rax), %rax
movq -24(%rax), %rax
movq $50, 8(%rdi,%rax)
movsd 8(%rsp), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
leaq .LC4(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
leaq .LC11(%rip), %rsi
movq %rbp, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
subq %r14, %r12
imulq $1000, %r12, %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
divsd .LC12(%rip), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
leaq .LC13(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq .LC14(%rip), %rsi
movq %rbp, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movq (%rax), %rax
movq -24(%rax), %rax
movq $50, 8(%rdi,%rax)
movsd .LC8(%rip), %xmm2
subsd 8(%rsp), %xmm2
movapd %xmm2, %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
movq %r13, %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
leaq 16(%rsp), %rdi
movabsq $4800032768, %rsi
call cudaMalloc@PLT
testl %eax, %eax
jne .L35
.L29:
leaq 24(%rsp), %rdi
movl $32768, %esi
call cudaMalloc@PLT
testl %eax, %eax
jne .L36
.L30:
movl $1, %ecx
movabsq $4800000000, %rdx
movq %rbx, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
call clock@PLT
movq %rax, %r14
movl $256, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $16, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L37
.L31:
call cudaGetLastError@PLT
testl %eax, %eax
jne .L38
.L32:
movl $2, %ecx
movl $32768, %edx
movq 24(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
movl $4096, %esi
movq %rbx, %rdi
call _Z14add_componentsPdi
movsd %xmm0, 8(%rsp)
call clock@PLT
movq %rax, %rbp
leaq .LC17(%rip), %rsi
leaq _ZSt4cout(%rip), %r13
movq %r13, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
leaq .LC18(%rip), %rsi
movq %r13, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movq (%rax), %rax
movq -24(%rax), %rax
movq $50, 8(%rdi,%rax)
movsd 8(%rsp), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
leaq .LC4(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
leaq .LC19(%rip), %rsi
movq %r13, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
subq %r14, %rbp
imulq $1000, %rbp, %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
divsd .LC12(%rip), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
leaq .LC13(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq .LC14(%rip), %rsi
movq %r13, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movq (%rax), %rax
movq -24(%rax), %rax
movq $50, 8(%rdi,%rax)
movsd .LC8(%rip), %xmm0
subsd 8(%rsp), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
leaq .LC6(%rip), %r14
movq %r14, %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
leaq .LC20(%rip), %rsi
movq %r13, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
pxor %xmm0, %xmm0
cvtsi2sdq %r12, %xmm0
pxor %xmm1, %xmm1
cvtsi2sdq %rbp, %xmm1
divsd %xmm1, %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
movq %r14, %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq %rbx, %rdi
call free@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L39
movl $0, %eax
addq $64, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L35:
.cfi_restore_state
leaq .LC15(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L29
.L36:
leaq .LC15(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L30
.L37:
movl $146485, %edx
movq 24(%rsp), %rsi
movq 16(%rsp), %rdi
call _Z43__device_stub__Z20add_components_GPU_2PdS_iPdS_i
jmp .L31
.L38:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC16(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L32
.L39:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3949:
.size main, .-main
.globl _Z33__device_stub__Z12generate_GPUPdiPdi
.type _Z33__device_stub__Z12generate_GPUPdiPdi, @function
_Z33__device_stub__Z12generate_GPUPdiPdi:
.LFB3979:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L44
.L40:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L45
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L44:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z12generate_GPUPdi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L40
.L45:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3979:
.size _Z33__device_stub__Z12generate_GPUPdiPdi, .-_Z33__device_stub__Z12generate_GPUPdiPdi
.globl _Z12generate_GPUPdi
.type _Z12generate_GPUPdi, @function
_Z12generate_GPUPdi:
.LFB3980:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z12generate_GPUPdiPdi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3980:
.size _Z12generate_GPUPdi, .-_Z12generate_GPUPdi
.section .rodata.str1.1
.LC21:
.string "_Z12generate_GPUPdi"
.LC22:
.string "_Z20add_components_GPU_2PdS_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3982:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC21(%rip), %rdx
movq %rdx, %rcx
leaq _Z12generate_GPUPdi(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC22(%rip), %rdx
movq %rdx, %rcx
leaq _Z20add_components_GPU_2PdS_i(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3982:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC0:
.long 0
.long 1074790400
.align 8
.LC8:
.long 1413754136
.long 1074340347
.align 8
.LC12:
.long 0
.long 1093567616
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
```
|
```amdasm
.text
.file "pi.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z35__device_stub__add_components_GPU_2PdS_i # -- Begin function _Z35__device_stub__add_components_GPU_2PdS_i
.type _Z35__device_stub__add_components_GPU_2PdS_i,@function
_Z35__device_stub__add_components_GPU_2PdS_i: # @_Z35__device_stub__add_components_GPU_2PdS_i
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $112, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 40(%rsp), %rax
movq %rdi, (%rax)
leaq 32(%rsp), %rcx
movq %rsi, (%rcx)
leaq 12(%rsp), %rsi
movl %edx, (%rsi)
leaq 80(%rsp), %rbx
movq %rax, (%rbx)
movq %rcx, 8(%rbx)
movq %rsi, 16(%rbx)
leaq 64(%rsp), %r14
leaq 48(%rsp), %r15
leaq 24(%rsp), %r12
leaq 16(%rsp), %r13
movq %r14, %rdi
movq %r15, %rsi
movq %r12, %rdx
movq %r13, %rcx
callq __hipPopCallConfiguration
movq (%r14), %rsi
movl 8(%r14), %edx
movq (%r15), %rcx
movl 8(%r15), %r8d
movl $_Z20add_components_GPU_2PdS_i, %edi
movq %rbx, %r9
pushq (%r13)
.cfi_adjust_cfa_offset 8
pushq (%r12)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $128, %rsp
.cfi_adjust_cfa_offset -128
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z35__device_stub__add_components_GPU_2PdS_i, .Lfunc_end0-_Z35__device_stub__add_components_GPU_2PdS_i
.cfi_endproc
# -- End function
.globl _Z27__device_stub__generate_GPUPdi # -- Begin function _Z27__device_stub__generate_GPUPdi
.type _Z27__device_stub__generate_GPUPdi,@function
_Z27__device_stub__generate_GPUPdi: # @_Z27__device_stub__generate_GPUPdi
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $80, %rsp
.cfi_def_cfa_offset 128
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 24(%rsp), %rax
movq %rdi, (%rax)
leaq 4(%rsp), %rcx
movl %esi, (%rcx)
leaq 64(%rsp), %rbx
movq %rax, (%rbx)
movq %rcx, 8(%rbx)
leaq 48(%rsp), %r14
leaq 32(%rsp), %r15
leaq 16(%rsp), %r12
leaq 8(%rsp), %r13
movq %r14, %rdi
movq %r15, %rsi
movq %r12, %rdx
movq %r13, %rcx
callq __hipPopCallConfiguration
movq (%r14), %rsi
movl 8(%r14), %edx
movq (%r15), %rcx
movl 8(%r15), %r8d
movl $_Z12generate_GPUPdi, %edi
movq %rbx, %r9
pushq (%r13)
.cfi_adjust_cfa_offset 8
pushq (%r12)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $96, %rsp
.cfi_adjust_cfa_offset -96
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z27__device_stub__generate_GPUPdi, .Lfunc_end1-_Z27__device_stub__generate_GPUPdi
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI2_0:
.quad 0x4010000000000000 # double 4
.LCPI2_1:
.quad 0x400921fb54442d18 # double 3.1415926535897931
.LCPI2_2:
.quad 0x412e848000000000 # double 1.0E+6
.text
.globl main
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $32, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movabsq $4800000000, %r15 # imm = 0x11E1A3000
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $3, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl $600000000, %esi # imm = 0x23C34600
callq _ZNSolsEi
movl $.L.str.1, %esi
movl $2, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq %r15, %rdi
callq malloc
movq %rax, %rbx
movl $1, %eax
movq $-1, %rcx
movsd .LCPI2_0(%rip), %xmm0 # xmm0 = mem[0],zero
.LBB2_1: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
leaq 2(%rcx), %rdx
xorps %xmm1, %xmm1
cvtsi2sd %edx, %xmm1
movapd %xmm0, %xmm2
divsd %xmm1, %xmm2
xorps %xmm1, %xmm1
cvtsi2sd %eax, %xmm1
mulsd %xmm2, %xmm1
movsd %xmm1, 4(%rbx,%rcx,4)
negl %eax
movq %rdx, %rcx
cmpq $1199999998, %rdx # imm = 0x47868BFE
jb .LBB2_1
# %bb.2: # %_Z19generate_componentsPdi.exit
xorl %r14d, %r14d
callq clock
xorpd %xmm0, %xmm0
movq %rax, %r12
.LBB2_3: # %.lr.ph.i55
# =>This Inner Loop Header: Depth=1
addsd (%rbx,%r14,8), %xmm0
incq %r14
cmpq $600000000, %r14 # imm = 0x23C34600
jne .LBB2_3
# %bb.4: # %_Z14add_componentsPdi.exit
movsd %xmm0, 8(%rsp) # 8-byte Spill
callq clock
movq %rax, %r14
movl $_ZSt4cout, %edi
movl $.L.str.2, %esi
movl $13, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movl $50, %r13d
movq %r13, _ZSt4cout+8(%rax)
movsd .LCPI2_1(%rip), %xmm0 # xmm0 = mem[0],zero
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movl $.L.str.1, %esi
movl $2, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl $.L.str.3, %esi
movl $6, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl $.L.str.4, %esi
movl $8, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq %r13, _ZSt4cout+8(%rax)
movl $_ZSt4cout, %edi
movsd 8(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
callq _ZNSo9_M_insertIdEERSoT_
movl $.L.str.5, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl $.L.str.6, %esi
movl $10, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
subq %r12, %r14
imulq $1000, %r14, %rax # imm = 0x3E8
xorps %xmm0, %xmm0
cvtsi2sd %rax, %xmm0
divsd .LCPI2_2(%rip), %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq %rax, %r12
movl $.L.str.7, %esi
movl $3, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq (%r12), %rax
movq -24(%rax), %rdi
addq %r12, %rdi
movl $10, %esi
callq _ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
movsbl %al, %esi
movq %r12, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str.8, %esi
movl $10, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq %r13, _ZSt4cout+8(%rax)
movsd .LCPI2_1(%rip), %xmm0 # xmm0 = mem[0],zero
subsd 8(%rsp), %xmm0 # 8-byte Folded Reload
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movl $.L.str.1, %esi
movl $2, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
leaq 32768(%r15), %rsi
leaq 24(%rsp), %rdi
callq hipMalloc
testl %eax, %eax
jne .LBB2_5
.LBB2_6:
leaq 16(%rsp), %rdi
movl $32768, %esi # imm = 0x8000
callq hipMalloc
testl %eax, %eax
jne .LBB2_7
.LBB2_8:
movq 24(%rsp), %rdi
movq %rbx, %rsi
movq %r15, %rdx
movl $1, %ecx
callq hipMemcpy
callq clock
movq %rax, %r12
leaq -505032688(%r15), %rdi
addq $-505032448, %r15 # imm = 0xE1E5D100
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_10
# %bb.9:
movq 24(%rsp), %rdi
movq 16(%rsp), %rsi
movl $146485, %edx # imm = 0x23C35
callq _Z35__device_stub__add_components_GPU_2PdS_i
.LBB2_10:
callq hipGetLastError
testl %eax, %eax
jne .LBB2_11
.LBB2_12:
movq 16(%rsp), %rsi
movl $32768, %edx # imm = 0x8000
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
xorpd %xmm0, %xmm0
xorl %eax, %eax
.LBB2_13: # %.lr.ph.i58
# =>This Inner Loop Header: Depth=1
addsd (%rbx,%rax,8), %xmm0
incq %rax
cmpq $4096, %rax # imm = 0x1000
jne .LBB2_13
# %bb.14: # %_Z14add_componentsPdi.exit63
movsd %xmm0, 8(%rsp) # 8-byte Spill
callq clock
movq %rax, %r15
movl $_ZSt4cout, %edi
movl $.L.str.11, %esi
movl $6, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl $.L.str.12, %esi
movl $8, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movl $50, %r13d
movq %r13, _ZSt4cout+8(%rax)
movl $_ZSt4cout, %edi
movsd 8(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
callq _ZNSo9_M_insertIdEERSoT_
movl $.L.str.5, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl $.L.str.13, %esi
movl $10, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
subq %r12, %r15
imulq $1000, %r15, %rax # imm = 0x3E8
xorps %xmm0, %xmm0
cvtsi2sd %rax, %xmm0
divsd .LCPI2_2(%rip), %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq %rax, %r12
movl $.L.str.7, %esi
movl $3, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq (%r12), %rax
movq -24(%rax), %rdi
addq %r12, %rdi
movl $10, %esi
callq _ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
movsbl %al, %esi
movq %r12, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str.8, %esi
movl $10, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq %r13, _ZSt4cout+8(%rax)
movsd .LCPI2_1(%rip), %xmm0 # xmm0 = mem[0],zero
subsd 8(%rsp), %xmm0 # 8-byte Folded Reload
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movl $.L.str.1, %esi
movl $2, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl $.L.str.14, %esi
movl $9, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
xorps %xmm0, %xmm0
cvtsi2sd %r14, %xmm0
cvtsi2sd %r15, %xmm1
divsd %xmm1, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movl $.L.str.1, %esi
movl $2, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq %rbx, %rdi
callq free
xorl %eax, %eax
addq $32, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB2_5:
.cfi_def_cfa_offset 80
movq stderr(%rip), %rcx
movl $.L.str.9, %edi
movl $18, %esi
movl $1, %edx
callq fwrite@PLT
jmp .LBB2_6
.LBB2_7:
movq stderr(%rip), %rcx
movl $.L.str.9, %edi
movl $18, %esi
movl $1, %edx
callq fwrite@PLT
jmp .LBB2_8
.LBB2_11:
movq stderr(%rip), %r15
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.10, %esi
movq %r15, %rdi
movq %rax, %rdx
xorl %eax, %eax
callq fprintf
jmp .LBB2_12
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z19generate_componentsPdi
.LCPI3_0:
.quad 0x4010000000000000 # double 4
.text
.globl _Z19generate_componentsPdi
.type _Z19generate_componentsPdi,@function
_Z19generate_componentsPdi: # @_Z19generate_componentsPdi
.cfi_startproc
# %bb.0:
# kill: def $esi killed $esi def $rsi
testl %esi, %esi
jle .LBB3_3
# %bb.1: # %.lr.ph.preheader
addl %esi, %esi
movl $1, %eax
movl $1, %ecx
movsd .LCPI3_0(%rip), %xmm0 # xmm0 = mem[0],zero
.LBB3_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
xorps %xmm1, %xmm1
cvtsi2sd %ecx, %xmm1
movapd %xmm0, %xmm2
divsd %xmm1, %xmm2
xorps %xmm1, %xmm1
cvtsi2sd %eax, %xmm1
mulsd %xmm2, %xmm1
movsd %xmm1, -4(%rdi,%rcx,4)
negl %eax
addq $2, %rcx
cmpq %rsi, %rcx
jb .LBB3_2
.LBB3_3: # %._crit_edge
retq
.Lfunc_end3:
.size _Z19generate_componentsPdi, .Lfunc_end3-_Z19generate_componentsPdi
.cfi_endproc
# -- End function
.globl _Z14add_componentsPdi # -- Begin function _Z14add_componentsPdi
.type _Z14add_componentsPdi,@function
_Z14add_componentsPdi: # @_Z14add_componentsPdi
.cfi_startproc
# %bb.0:
testl %esi, %esi
jle .LBB4_1
# %bb.3: # %.lr.ph.preheader
movl %esi, %eax
xorpd %xmm0, %xmm0
xorl %ecx, %ecx
.LBB4_4: # %.lr.ph
# =>This Inner Loop Header: Depth=1
addsd (%rdi,%rcx,8), %xmm0
incq %rcx
cmpq %rcx, %rax
jne .LBB4_4
# %bb.2: # %._crit_edge
retq
.LBB4_1:
xorps %xmm0, %xmm0
retq
.Lfunc_end4:
.size _Z14add_componentsPdi, .Lfunc_end4-_Z14add_componentsPdi
.cfi_endproc
# -- End function
.globl _Z16print_componentsPdi # -- Begin function _Z16print_componentsPdi
.type _Z16print_componentsPdi,@function
_Z16print_componentsPdi: # @_Z16print_componentsPdi
.cfi_startproc
# %bb.0:
testl %esi, %esi
jle .LBB5_4
# %bb.1: # %.lr.ph.preheader
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
pushq %rax
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rdi, %rbx
movl %esi, %r12d
xorl %r14d, %r14d
.LBB5_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl $_ZSt4cout, %edi
movl $.L.str.15, %esi
movl $5, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl %r14d, %esi
callq _ZNSolsEi
movq %rax, %r15
movl $.L.str.16, %esi
movl $2, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movsd (%rbx,%r14,8), %xmm0 # xmm0 = mem[0],zero
movq %r15, %rdi
callq _ZNSo9_M_insertIdEERSoT_
movl $.L.str.5, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
incq %r14
cmpq %r14, %r12
jne .LBB5_2
# %bb.3:
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r12
.cfi_restore %r14
.cfi_restore %r15
.LBB5_4: # %._crit_edge
retq
.Lfunc_end5:
.size _Z16print_componentsPdi, .Lfunc_end5-_Z16print_componentsPdi
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
movq __hip_gpubin_handle(%rip), %rbx
testq %rbx, %rbx
jne .LBB6_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, %rbx
movq %rax, __hip_gpubin_handle(%rip)
.LBB6_2:
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z20add_components_GPU_2PdS_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12generate_GPUPdi, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end6:
.size __hip_module_ctor, .Lfunc_end6-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB7_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB7_2:
retq
.Lfunc_end7:
.size __hip_module_dtor, .Lfunc_end7-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z20add_components_GPU_2PdS_i,@object # @_Z20add_components_GPU_2PdS_i
.section .rodata,"a",@progbits
.globl _Z20add_components_GPU_2PdS_i
.p2align 3, 0x0
_Z20add_components_GPU_2PdS_i:
.quad _Z35__device_stub__add_components_GPU_2PdS_i
.size _Z20add_components_GPU_2PdS_i, 8
.type _Z12generate_GPUPdi,@object # @_Z12generate_GPUPdi
.globl _Z12generate_GPUPdi
.p2align 3, 0x0
_Z12generate_GPUPdi:
.quad _Z27__device_stub__generate_GPUPdi
.size _Z12generate_GPUPdi, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "n: "
.size .L.str, 4
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "\n\n"
.size .L.str.1, 3
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "pi_constant: "
.size .L.str.2, 14
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "\n\nCPU\n"
.size .L.str.3, 7
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "pi CPU: "
.size .L.str.4, 9
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "\n"
.size .L.str.5, 2
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "Czas_CPU: "
.size .L.str.6, 11
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz " ms"
.size .L.str.7, 4
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "pi_error: "
.size .L.str.8, 11
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "hipMalloc failed!\n"
.size .L.str.9, 19
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "add_components_GPU_2 launch failed: %s\n"
.size .L.str.10, 40
.type .L.str.11,@object # @.str.11
.L.str.11:
.asciz "\n\nGPU\n"
.size .L.str.11, 7
.type .L.str.12,@object # @.str.12
.L.str.12:
.asciz "pi GPU: "
.size .L.str.12, 9
.type .L.str.13,@object # @.str.13
.L.str.13:
.asciz "Czas_GPU: "
.size .L.str.13, 11
.type .L.str.14,@object # @.str.14
.L.str.14:
.asciz "Speedup: "
.size .L.str.14, 10
.type .L.str.15,@object # @.str.15
.L.str.15:
.asciz "comp "
.size .L.str.15, 6
.type .L.str.16,@object # @.str.16
.L.str.16:
.asciz ": "
.size .L.str.16, 3
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z20add_components_GPU_2PdS_i"
.size .L__unnamed_1, 30
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z12generate_GPUPdi"
.size .L__unnamed_2, 20
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z35__device_stub__add_components_GPU_2PdS_i
.addrsig_sym _Z27__device_stub__generate_GPUPdi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z20add_components_GPU_2PdS_i
.addrsig_sym _Z12generate_GPUPdi
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
```
| 8,217 | 10,107 |
530 |
Convert the following CUDA device assembly code to AMD device assembly:
```cudaasm
code for sm_80
Function : _Z3dotPfS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
MOV R1, c[0x0][0x28] ;
S2R R7, SR_CTAID.X ;
ULDC.64 UR6, c[0x0][0x118] ;
BSSY B0, 0x150 ;
HFMA2.MMA R6, -RZ, RZ, 0, 0 ;
S2R R8, SR_TID.X ;
IMAD R0, R7, c[0x0][0x0], R8 ;
ISETP.GT.AND P0, PT, R0, 0x13, PT ;
@P0 BRA 0x140 ;
IMAD.MOV.U32 R6, RZ, RZ, RZ ;
MOV R5, 0x4 ;
IMAD.WIDE R2, R0, R5, c[0x0][0x160] ;
IMAD.WIDE R4, R0, R5, c[0x0][0x168] ;
LDG.E R2, [R2.64] ;
LDG.E R5, [R4.64] ;
IMAD.MOV.U32 R9, RZ, RZ, c[0x0][0x0] ;
IMAD R0, R9, c[0x0][0xc], R0 ;
ISETP.GE.AND P0, PT, R0, 0x14, PT ;
FFMA R6, R5, R2, R6 ;
@!P0 BRA 0xa0 ;
BSYNC B0 ;
ULDC UR4, c[0x0][0x0] ;
STS [R8.X4], R6 ;
USHF.R.U32.HI UR4, URZ, 0x1, UR4 ;
BAR.SYNC.DEFER_BLOCKING 0x0 ;
ISETP.NE.AND P0, PT, R8, RZ, PT ;
ISETP.NE.AND P1, PT, RZ, UR4, PT ;
@!P1 BRA 0x280 ;
SHF.L.U32 R0, R8, 0x2, RZ ;
IMAD.U32 R3, RZ, RZ, UR4 ;
ISETP.GE.AND P1, PT, R8, R3, PT ;
@!P1 LEA R2, R3, R0, 0x2 ;
@!P1 LDS R4, [R8.X4] ;
SHF.R.U32.HI R3, RZ, 0x1, R3 ;
@!P1 LDS R5, [R2] ;
@!P1 FADD R4, R4, R5 ;
@!P1 STS [R8.X4], R4 ;
BAR.SYNC.DEFER_BLOCKING 0x0 ;
ISETP.NE.AND P1, PT, R3, RZ, PT ;
@P1 BRA 0x1e0 ;
@P0 EXIT ;
LDS R5, [RZ] ;
IMAD.MOV.U32 R2, RZ, RZ, 0x4 ;
IMAD.WIDE.U32 R2, R7, R2, c[0x0][0x170] ;
STG.E [R2.64], R5 ;
EXIT ;
BRA 0x2e0;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
```
|
```amdasm
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3dotPfS_S_ ; -- Begin function _Z3dotPfS_S_
.globl _Z3dotPfS_S_
.p2align 8
.type _Z3dotPfS_S_,@function
_Z3dotPfS_S_: ; @_Z3dotPfS_S_
; %bb.0:
s_clause 0x2
s_load_b32 s3, s[0:1], 0x24
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[8:9], s[0:1], 0x10
s_add_u32 s0, s0, 24
s_mov_b32 s2, s15
s_addc_u32 s1, s1, 0
v_mov_b32_e32 v3, 0
s_mov_b32 s10, exec_lo
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s2, s3, v[0:1]
v_cmpx_gt_i32_e32 20, v1
s_cbranch_execz .LBB0_4
; %bb.1: ; %.lr.ph
s_load_b32 s1, s[0:1], 0x0
v_mov_b32_e32 v3, 0
s_mov_b32 s0, 0
s_waitcnt lgkmcnt(0)
s_mul_i32 s1, s1, s3
.LBB0_2: ; =>This Inner Loop Header: Depth=1
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[4:5], 2, v[1:2]
v_add_nc_u32_e32 v1, s1, v1
v_add_co_u32 v6, vcc_lo, s4, v4
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v7, vcc_lo, s5, v5, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v5, vcc_lo
v_cmp_lt_i32_e32 vcc_lo, 19, v1
global_load_b32 v2, v[6:7], off
global_load_b32 v4, v[4:5], off
s_or_b32 s0, vcc_lo, s0
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v3, v2, v4
s_and_not1_b32 exec_lo, exec_lo, s0
s_cbranch_execnz .LBB0_2
; %bb.3: ; %Flow39
s_or_b32 exec_lo, exec_lo, s0
.LBB0_4: ; %Flow40
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s10
v_lshlrev_b32_e32 v1, 2, v0
s_cmp_lt_u32 s3, 2
ds_store_b32 v1, v3
s_waitcnt lgkmcnt(0)
s_barrier
.LBB0_5: ; %._crit_edge
; =>This Inner Loop Header: Depth=1
buffer_gl0_inv
s_cbranch_scc1 .LBB0_9
; %bb.6: ; %.lr.ph28
; in Loop: Header=BB0_5 Depth=1
s_lshr_b32 s0, s3, 1
s_mov_b32 s1, exec_lo
v_cmpx_gt_u32_e64 s0, v0
s_cbranch_execz .LBB0_8
; %bb.7: ; in Loop: Header=BB0_5 Depth=1
v_lshl_add_u32 v2, s0, 2, v1
ds_load_b32 v2, v2
ds_load_b32 v3, v1
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v2, v2, v3
ds_store_b32 v1, v2
.LBB0_8: ; in Loop: Header=BB0_5 Depth=1
s_or_b32 exec_lo, exec_lo, s1
s_waitcnt lgkmcnt(0)
s_barrier
s_cmp_lt_u32 s3, 4
s_mov_b32 s3, s0
s_branch .LBB0_5
.LBB0_9: ; %._crit_edge29
s_mov_b32 s3, 0
s_mov_b32 s0, exec_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB0_11
; %bb.10:
v_mov_b32_e32 v0, 0
s_lshl_b64 s[0:1], s[2:3], 2
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s0, s8, s0
s_addc_u32 s1, s9, s1
ds_load_b32 v1, v0
s_waitcnt lgkmcnt(0)
global_store_b32 v0, v1, s[0:1]
.LBB0_11:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3dotPfS_S_
.amdhsa_group_segment_fixed_size 1024
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3dotPfS_S_, .Lfunc_end0-_Z3dotPfS_S_
; -- End function
.section .AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 392
; NumSgprs: 18
; NumVgprs: 8
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 1024 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 8
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object ; @__hip_cuid_
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0 ; 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 1024
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3dotPfS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z3dotPfS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
```
| 838 | 3,305 |
531 |
Convert the following CUDA host assembly code to AMD host assembly:
```cudaasm
.file "tmpxft_0013a672_00000000-6_dot.cudafe1.cpp"
.text
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z26__device_stub__Z3dotPfS_S_PfS_S_
.type _Z26__device_stub__Z3dotPfS_S_PfS_S_, @function
_Z26__device_stub__Z3dotPfS_S_PfS_S_:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z3dotPfS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z26__device_stub__Z3dotPfS_S_PfS_S_, .-_Z26__device_stub__Z3dotPfS_S_PfS_S_
.globl _Z3dotPfS_S_
.type _Z3dotPfS_S_, @function
_Z3dotPfS_S_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z3dotPfS_S_PfS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z3dotPfS_S_, .-_Z3dotPfS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z3dotPfS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z3dotPfS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
```
|
```amdasm
.text
.file "dot.hip"
.globl _Z18__device_stub__dotPfS_S_ # -- Begin function _Z18__device_stub__dotPfS_S_
.type _Z18__device_stub__dotPfS_S_,@function
_Z18__device_stub__dotPfS_S_: # @_Z18__device_stub__dotPfS_S_
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $112, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 40(%rsp), %rax
movq %rdi, (%rax)
leaq 32(%rsp), %rcx
movq %rsi, (%rcx)
leaq 24(%rsp), %rsi
movq %rdx, (%rsi)
leaq 80(%rsp), %rbx
movq %rax, (%rbx)
movq %rcx, 8(%rbx)
movq %rsi, 16(%rbx)
leaq 64(%rsp), %r14
leaq 48(%rsp), %r15
leaq 16(%rsp), %r12
leaq 8(%rsp), %r13
movq %r14, %rdi
movq %r15, %rsi
movq %r12, %rdx
movq %r13, %rcx
callq __hipPopCallConfiguration
movq (%r14), %rsi
movl 8(%r14), %edx
movq (%r15), %rcx
movl 8(%r15), %r8d
movl $_Z3dotPfS_S_, %edi
movq %rbx, %r9
pushq (%r13)
.cfi_adjust_cfa_offset 8
pushq (%r12)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $128, %rsp
.cfi_adjust_cfa_offset -128
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z18__device_stub__dotPfS_S_, .Lfunc_end0-_Z18__device_stub__dotPfS_S_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, %rdi
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3dotPfS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3dotPfS_S_,@object # @_Z3dotPfS_S_
.section .rodata,"a",@progbits
.globl _Z3dotPfS_S_
.p2align 3, 0x0
_Z3dotPfS_S_:
.quad _Z18__device_stub__dotPfS_S_
.size _Z3dotPfS_S_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z3dotPfS_S_"
.size .L__unnamed_1, 13
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__dotPfS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3dotPfS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
```
| 1,825 | 2,007 |
534 |
Convert the following CUDA device assembly code to AMD device assembly:
```cudaasm
code for sm_80
Function : _Z10STREAM_AddPfS_S_m
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ;
S2R R0, SR_CTAID.X ;
S2R R3, SR_TID.X ;
IMAD R0, R0, c[0x0][0x0], R3 ;
ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x178], PT ;
ISETP.GE.U32.AND.EX P0, PT, RZ, c[0x0][0x17c], PT, P0 ;
@P0 EXIT ;
IMAD.MOV.U32 R11, RZ, RZ, RZ ;
ULDC.64 UR4, c[0x0][0x118] ;
IMAD.MOV.U32 R8, RZ, RZ, c[0x0][0x0] ;
IMAD.SHL.U32 R6, R0.reuse, 0x4, RZ ;
SHF.L.U64.HI R7, R0, 0x2, R11 ;
IADD3 R4, P1, R6.reuse, c[0x0][0x160], RZ ;
IADD3 R2, P0, R6, c[0x0][0x168], RZ ;
IADD3.X R5, R7.reuse, c[0x0][0x164], RZ, P1, !PT ;
IADD3.X R3, R7, c[0x0][0x16c], RZ, P0, !PT ;
LDG.E R5, [R4.64] ;
LDG.E R2, [R2.64] ;
IADD3 R6, P0, R6, c[0x0][0x170], RZ ;
IMAD R13, R8, c[0x0][0xc], RZ ;
IADD3.X R7, R7, c[0x0][0x174], RZ, P0, !PT ;
IADD3 R0, P0, R13, R0, RZ ;
IMAD.X R11, RZ, RZ, R11, P0 ;
ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x178], PT ;
ISETP.GE.U32.AND.EX P0, PT, R11, c[0x0][0x17c], PT, P0 ;
FADD R9, R2, R5 ;
STG.E [R6.64], R9 ;
@!P0 BRA 0xa0 ;
EXIT ;
BRA 0x1d0;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
```
|
```amdasm
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10STREAM_AddPfS_S_m ; -- Begin function _Z10STREAM_AddPfS_S_m
.globl _Z10STREAM_AddPfS_S_m
.p2align 8
.type _Z10STREAM_AddPfS_S_m,@function
_Z10STREAM_AddPfS_S_m: ; @_Z10STREAM_AddPfS_S_m
; %bb.0:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b256 s[4:11], s[0:1], 0x0
s_add_u32 s0, s0, 32
s_addc_u32 s1, s1, 0
s_mov_b32 s3, exec_lo
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
v_mov_b32_e32 v2, 0
v_cmpx_gt_u64_e64 s[10:11], v[1:2]
s_cbranch_execz .LBB0_3
; %bb.1: ; %.lr.ph
s_load_b32 s0, s[0:1], 0x0
v_lshlrev_b64 v[3:4], 2, v[1:2]
s_mov_b32 s3, 0
s_waitcnt lgkmcnt(0)
s_mul_i32 s2, s0, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_lshl_b64 s[12:13], s[2:3], 2
.LBB0_2: ; =>This Inner Loop Header: Depth=1
s_delay_alu instid0(VALU_DEP_1)
v_add_co_u32 v5, vcc_lo, s4, v3
v_add_co_ci_u32_e32 v6, vcc_lo, s5, v4, vcc_lo
v_add_co_u32 v7, vcc_lo, s6, v3
v_add_co_ci_u32_e32 v8, vcc_lo, s7, v4, vcc_lo
v_add_co_u32 v1, vcc_lo, v1, s2
global_load_b32 v0, v[5:6], off
global_load_b32 v7, v[7:8], off
v_add_co_ci_u32_e32 v2, vcc_lo, 0, v2, vcc_lo
v_add_co_u32 v5, vcc_lo, s8, v3
v_add_co_ci_u32_e32 v6, vcc_lo, s9, v4, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_le_u64_e32 vcc_lo, s[10:11], v[1:2]
v_add_co_u32 v3, s0, v3, s12
v_add_co_ci_u32_e64 v4, s0, s13, v4, s0
s_or_b32 s3, vcc_lo, s3
s_waitcnt vmcnt(0)
v_add_f32_e32 v0, v0, v7
global_store_b32 v[5:6], v0, off
s_and_not1_b32 exec_lo, exec_lo, s3
s_cbranch_execnz .LBB0_2
.LBB0_3: ; %._crit_edge
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10STREAM_AddPfS_S_m
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10STREAM_AddPfS_S_m, .Lfunc_end0-_Z10STREAM_AddPfS_S_m
; -- End function
.section .AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 240
; NumSgprs: 18
; NumVgprs: 9
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 9
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object ; @__hip_cuid_
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0 ; 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 8
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10STREAM_AddPfS_S_m
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z10STREAM_AddPfS_S_m.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
```
| 727 | 2,854 |
535 |
Convert the following CUDA host assembly code to AMD host assembly:
```cudaasm
.file "tmpxft_00096e9e_00000000-6_STREAM_Add.cudafe1.cpp"
.text
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z35__device_stub__Z10STREAM_AddPfS_S_mPfS_S_m
.type _Z35__device_stub__Z10STREAM_AddPfS_S_mPfS_S_m, @function
_Z35__device_stub__Z10STREAM_AddPfS_S_mPfS_S_m:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %rcx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z10STREAM_AddPfS_S_m(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z35__device_stub__Z10STREAM_AddPfS_S_mPfS_S_m, .-_Z35__device_stub__Z10STREAM_AddPfS_S_mPfS_S_m
.globl _Z10STREAM_AddPfS_S_m
.type _Z10STREAM_AddPfS_S_m, @function
_Z10STREAM_AddPfS_S_m:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z10STREAM_AddPfS_S_mPfS_S_m
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z10STREAM_AddPfS_S_m, .-_Z10STREAM_AddPfS_S_m
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z10STREAM_AddPfS_S_m"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z10STREAM_AddPfS_S_m(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
```
|
```amdasm
.text
.file "STREAM_Add.hip"
.globl _Z25__device_stub__STREAM_AddPfS_S_m # -- Begin function _Z25__device_stub__STREAM_AddPfS_S_m
.type _Z25__device_stub__STREAM_AddPfS_S_m,@function
_Z25__device_stub__STREAM_AddPfS_S_m: # @_Z25__device_stub__STREAM_AddPfS_S_m
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $112, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 40(%rsp), %rax
movq %rdi, (%rax)
leaq 32(%rsp), %rdi
movq %rsi, (%rdi)
leaq 24(%rsp), %rsi
movq %rdx, (%rsi)
leaq 16(%rsp), %rdx
movq %rcx, (%rdx)
leaq 80(%rsp), %rbx
movq %rax, (%rbx)
movq %rdi, 8(%rbx)
movq %rsi, 16(%rbx)
movq %rdx, 24(%rbx)
leaq 64(%rsp), %r14
leaq 48(%rsp), %r15
leaq 8(%rsp), %r12
movq %rsp, %r13
movq %r14, %rdi
movq %r15, %rsi
movq %r12, %rdx
movq %r13, %rcx
callq __hipPopCallConfiguration
movq (%r14), %rsi
movl 8(%r14), %edx
movq (%r15), %rcx
movl 8(%r15), %r8d
movl $_Z10STREAM_AddPfS_S_m, %edi
movq %rbx, %r9
pushq (%r13)
.cfi_adjust_cfa_offset 8
pushq (%r12)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $128, %rsp
.cfi_adjust_cfa_offset -128
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z25__device_stub__STREAM_AddPfS_S_m, .Lfunc_end0-_Z25__device_stub__STREAM_AddPfS_S_m
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, %rdi
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10STREAM_AddPfS_S_m, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10STREAM_AddPfS_S_m,@object # @_Z10STREAM_AddPfS_S_m
.section .rodata,"a",@progbits
.globl _Z10STREAM_AddPfS_S_m
.p2align 3, 0x0
_Z10STREAM_AddPfS_S_m:
.quad _Z25__device_stub__STREAM_AddPfS_S_m
.size _Z10STREAM_AddPfS_S_m, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z10STREAM_AddPfS_S_m"
.size .L__unnamed_1, 22
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__STREAM_AddPfS_S_m
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10STREAM_AddPfS_S_m
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
```
| 1,901 | 2,082 |
538 |
Convert the following CUDA device assembly code to AMD device assembly:
```cudaasm
code for sm_80
Function : multiply
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
MOV R1, c[0x0][0x28] ;
S2R R0, SR_CTAID.X ;
S2R R3, SR_TID.X ;
IMAD R0, R0, c[0x0][0x0], R3 ;
ISETP.GE.AND P0, PT, R0, c[0x0][0x160], PT ;
@P0 EXIT ;
MOV R2, c[0x0][0x164] ;
ULDC.64 UR4, c[0x0][0x118] ;
CS2R R26, SRZ ;
ISETP.GE.AND P0, PT, R2, 0x1, PT ;
@!P0 BRA 0xeb0 ;
IADD3 R3, R2.reuse, -0x1, RZ ;
IMAD.MOV.U32 R5, RZ, RZ, RZ ;
LOP3.LUT R2, R2, 0x3, RZ, 0xc0, !PT ;
CS2R R26, SRZ ;
ISETP.GE.U32.AND P0, PT, R3, 0x3, PT ;
@!P0 BRA 0xd10 ;
IADD3 R3, -R2, c[0x0][0x164], RZ ;
HFMA2.MMA R9, -RZ, RZ, 0, 2.384185791015625e-07 ;
IMAD R4, R0, c[0x0][0x164], RZ ;
ULDC.64 UR6, c[0x0][0x178] ;
ISETP.GT.AND P0, PT, R3, RZ, PT ;
CS2R R26, SRZ ;
MOV R5, RZ ;
IMAD.WIDE R8, R4, R9, c[0x0][0x170] ;
@!P0 BRA 0xb10 ;
ISETP.GT.AND P1, PT, R3, 0xc, PT ;
PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ;
@!P1 BRA 0x7a0 ;
PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ;
LDG.E R19, [R8.64] ;
LDG.E R11, [R8.64+0x4] ;
HFMA2.MMA R24, -RZ, RZ, 0, 4.76837158203125e-07 ;
MOV R7, UR7 ;
IMAD.U32 R6, RZ, RZ, UR6 ;
LDG.E R17, [R8.64+0x8] ;
IMAD.WIDE R6, R4, 0x8, R6 ;
LDG.E R29, [R8.64+0xc] ;
LDG.E.64 R12, [R6.64] ;
LDG.E.64 R22, [R6.64+0x8] ;
LDG.E R15, [R8.64+0x10] ;
LDG.E R25, [R8.64+0x18] ;
LDG.E.64 R20, [R6.64+0x20] ;
IMAD.WIDE R18, R19, R24, c[0x0][0x180] ;
LDG.E.64 R18, [R18.64] ;
IMAD.WIDE R10, R11, R24, c[0x0][0x180] ;
LDG.E.64 R10, [R10.64] ;
IMAD.WIDE R16, R17, R24, c[0x0][0x180] ;
LDG.E.64 R16, [R16.64] ;
IMAD.WIDE R28, R29, R24, c[0x0][0x180] ;
IMAD.WIDE R14, R15, R24, c[0x0][0x180] ;
LDG.E.64 R14, [R14.64] ;
DFMA R26, R18, R12, R26 ;
LDG.E.64 R12, [R6.64+0x10] ;
LDG.E.64 R18, [R28.64] ;
DFMA R22, R10, R22, R26 ;
LDG.E R27, [R8.64+0x14] ;
LDG.E.64 R10, [R6.64+0x18] ;
LDG.E R29, [R8.64+0x20] ;
DFMA R12, R16, R12, R22 ;
LDG.E R23, [R8.64+0x1c] ;
IMAD.WIDE R16, R27, R24, c[0x0][0x180] ;
LDG.E.64 R26, [R6.64+0x30] ;
DFMA R18, R18, R10, R12 ;
IMAD.WIDE R10, R25, R24, c[0x0][0x180] ;
LDG.E.64 R16, [R16.64] ;
LDG.E.64 R12, [R6.64+0x28] ;
LDG.E.64 R10, [R10.64] ;
DFMA R20, R14, R20, R18 ;
LDG.E R15, [R8.64+0x24] ;
IMAD.WIDE R28, R29, R24, c[0x0][0x180] ;
LDG.E R25, [R8.64+0x28] ;
IMAD.WIDE R18, R23, R24, c[0x0][0x180] ;
LDG.E.64 R22, [R28.64] ;
LDG.E.64 R18, [R18.64] ;
DFMA R16, R16, R12, R20 ;
LDG.E.64 R12, [R6.64+0x38] ;
DFMA R26, R10, R26, R16 ;
LDG.E R21, [R8.64+0x2c] ;
LDG.E.64 R10, [R6.64+0x40] ;
IMAD.WIDE R14, R15, R24, c[0x0][0x180] ;
LDG.E.64 R16, [R6.64+0x48] ;
LDG.E.64 R14, [R14.64] ;
DFMA R18, R18, R12, R26 ;
IMAD.WIDE R12, R25, R24, c[0x0][0x180] ;
LDG.E R27, [R8.64+0x34] ;
LDG.E R25, [R8.64+0x3c] ;
DFMA R22, R22, R10, R18 ;
LDG.E R11, [R8.64+0x30] ;
IMAD.WIDE R18, R21, R24, c[0x0][0x180] ;
LDG.E.64 R12, [R12.64] ;
LDG.E.64 R20, [R6.64+0x50] ;
DFMA R16, R14, R16, R22 ;
LDG.E.64 R18, [R18.64] ;
LDG.E.64 R14, [R6.64+0x58] ;
LDG.E R23, [R8.64+0x38] ;
IMAD.WIDE R10, R11, R24, c[0x0][0x180] ;
LDG.E.64 R10, [R10.64] ;
DFMA R20, R12, R20, R16 ;
IMAD.WIDE R16, R27, R24, c[0x0][0x180] ;
LDG.E.64 R12, [R6.64+0x60] ;
LDG.E.64 R26, [R6.64+0x78] ;
DFMA R14, R18, R14, R20 ;
LDG.E.64 R16, [R16.64] ;
IMAD.WIDE R20, R23, R24, c[0x0][0x180] ;
LDG.E.64 R18, [R6.64+0x68] ;
IMAD.WIDE R24, R25, R24, c[0x0][0x180] ;
LDG.E.64 R20, [R20.64] ;
LDG.E.64 R22, [R6.64+0x70] ;
LDG.E.64 R24, [R24.64] ;
IADD3 R3, R3, -0x10, RZ ;
ISETP.GT.AND P1, PT, R3, 0xc, PT ;
UIADD3 UR6, UP0, UR6, 0x80, URZ ;
IADD3 R8, P2, R8, 0x40, RZ ;
UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ;
IADD3 R5, R5, 0x10, RZ ;
IMAD.X R9, RZ, RZ, R9, P2 ;
DFMA R10, R10, R12, R14 ;
DFMA R10, R16, R18, R10 ;
DFMA R10, R20, R22, R10 ;
DFMA R26, R24, R26, R10 ;
@P1 BRA 0x1e0 ;
ISETP.GT.AND P1, PT, R3, 0x4, PT ;
@!P1 BRA 0xaf0 ;
LDG.E R17, [R8.64] ;
LDG.E R13, [R8.64+0x4] ;
MOV R10, UR6 ;
IMAD.MOV.U32 R6, RZ, RZ, 0x8 ;
MOV R11, UR7 ;
LDG.E R29, [R8.64+0x8] ;
IMAD.WIDE R10, R4, 0x8, R10 ;
LDG.E R7, [R8.64+0xc] ;
LDG.E.64 R24, [R10.64] ;
LDG.E.64 R22, [R10.64+0x8] ;
LDG.E R21, [R8.64+0x10] ;
IMAD.WIDE R16, R17, R6, c[0x0][0x180] ;
IMAD.WIDE R12, R13, R6.reuse, c[0x0][0x180] ;
LDG.E.64 R14, [R16.64] ;
LDG.E.64 R12, [R12.64] ;
IMAD.WIDE R28, R29, R6, c[0x0][0x180] ;
LDG.E.64 R16, [R10.64+0x10] ;
LDG.E.64 R18, [R28.64] ;
DFMA R24, R14, R24, R26 ;
IMAD.WIDE R14, R7, R6.reuse, c[0x0][0x180] ;
LDG.E R27, [R8.64+0x14] ;
DFMA R22, R12, R22, R24 ;
LDG.E R7, [R8.64+0x18] ;
LDG.E.64 R14, [R14.64] ;
LDG.E.64 R12, [R10.64+0x18] ;
LDG.E R25, [R8.64+0x1c] ;
IMAD.WIDE R20, R21, R6, c[0x0][0x180] ;
DFMA R16, R18, R16, R22 ;
LDG.E.64 R22, [R10.64+0x20] ;
LDG.E.64 R20, [R20.64] ;
IMAD.WIDE R18, R27, R6, c[0x0][0x180] ;
LDG.E.64 R26, [R10.64+0x38] ;
LDG.E.64 R18, [R18.64] ;
DFMA R12, R14, R12, R16 ;
IMAD.WIDE R16, R7, R6.reuse, c[0x0][0x180] ;
LDG.E.64 R14, [R10.64+0x28] ;
IMAD.WIDE R6, R25, R6, c[0x0][0x180] ;
LDG.E.64 R16, [R16.64] ;
LDG.E.64 R24, [R10.64+0x30] ;
LDG.E.64 R6, [R6.64] ;
DFMA R12, R20, R22, R12 ;
IADD3 R8, P1, R8, 0x20, RZ ;
UIADD3 UR6, UP0, UR6, 0x40, URZ ;
PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ;
IADD3.X R9, RZ, R9, RZ, P1, !PT ;
IADD3 R5, R5, 0x8, RZ ;
IADD3 R3, R3, -0x8, RZ ;
UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ;
DFMA R12, R18, R14, R12 ;
DFMA R12, R16, R24, R12 ;
DFMA R26, R6, R26, R12 ;
ISETP.NE.OR P0, PT, R3, RZ, P0 ;
@!P0 BRA 0xd10 ;
LDG.E R22, [R8.64] ;
LDG.E R12, [R8.64+0x4] ;
LDG.E R16, [R8.64+0x8] ;
LDG.E R20, [R8.64+0xc] ;
MOV R21, 0x8 ;
IMAD.U32 R7, RZ, RZ, UR7 ;
MOV R6, UR6 ;
IMAD.WIDE R6, R4, 0x8, R6 ;
LDG.E.64 R10, [R6.64] ;
LDG.E.64 R14, [R6.64+0x8] ;
LDG.E.64 R18, [R6.64+0x10] ;
LDG.E.64 R24, [R6.64+0x18] ;
IMAD.WIDE R22, R22, R21, c[0x0][0x180] ;
IMAD.WIDE R12, R12, R21.reuse, c[0x0][0x180] ;
LDG.E.64 R22, [R22.64] ;
IMAD.WIDE R16, R16, R21.reuse, c[0x0][0x180] ;
LDG.E.64 R12, [R12.64] ;
IMAD.WIDE R20, R20, R21, c[0x0][0x180] ;
LDG.E.64 R16, [R16.64] ;
LDG.E.64 R20, [R20.64] ;
IADD3 R3, R3, -0x4, RZ ;
ISETP.NE.AND P0, PT, R3, RZ, PT ;
UIADD3 UR6, UP0, UR6, 0x20, URZ ;
IADD3 R8, P1, R8, 0x10, RZ ;
UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ;
IADD3.X R9, RZ, R9, RZ, P1, !PT ;
IADD3 R5, R5, 0x4, RZ ;
DFMA R10, R22, R10, R26 ;
DFMA R10, R12, R14, R10 ;
DFMA R10, R16, R18, R10 ;
DFMA R26, R20, R24, R10 ;
@P0 BRA 0xb10 ;
ISETP.NE.AND P0, PT, R2, RZ, PT ;
@!P0 BRA 0xeb0 ;
IMAD.MOV.U32 R13, RZ, RZ, 0x8 ;
MOV R7, 0x4 ;
IMAD R6, R0, c[0x0][0x164], R5 ;
IMAD.WIDE R4, R6, R13, c[0x0][0x178] ;
IMAD.WIDE R6, R6, R7, c[0x0][0x170] ;
MOV R10, R4 ;
MOV R11, R5 ;
IMAD.MOV.U32 R3, RZ, RZ, R6 ;
MOV R9, R7 ;
MOV R8, R3 ;
LDG.E R4, [R8.64] ;
MOV R6, R10 ;
IMAD.MOV.U32 R7, RZ, RZ, R11 ;
LDG.E.64 R6, [R6.64] ;
IADD3 R2, R2, -0x1, RZ ;
IMAD.WIDE R4, R4, R13, c[0x0][0x180] ;
LDG.E.64 R4, [R4.64] ;
ISETP.NE.AND P0, PT, R2, RZ, PT ;
IADD3 R10, P1, R10, 0x8, RZ ;
IADD3 R3, P2, R3, 0x4, RZ ;
IADD3.X R11, RZ, R11, RZ, P1, !PT ;
IADD3.X R9, RZ, R9, RZ, P2, !PT ;
DFMA R26, R4, R6, R26 ;
@P0 BRA 0xdc0 ;
MOV R11, 0x8 ;
IMAD.WIDE R2, R0, R11, c[0x0][0x180] ;
LDG.E.64 R4, [R2.64] ;
IMAD.WIDE R6, R0, R11, c[0x0][0x188] ;
DFMA R4, R4, c[0x0][0x168], R26 ;
STG.E.64 [R6.64], R4 ;
LDG.E.64 R8, [R2.64] ;
IMAD.WIDE R10, R0, R11, c[0x0][0x190] ;
DADD R8, -R4, R8 ;
STG.E.64 [R10.64], R8 ;
EXIT ;
BRA 0xf60;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
Function : surface_area
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ;
S2R R0, SR_CTAID.X ;
S2R R3, SR_TID.X ;
IMAD R0, R0, c[0x0][0x0], R3 ;
ISETP.GE.AND P0, PT, R0, c[0x0][0x160], PT ;
@P0 EXIT ;
IMAD.MOV.U32 R7, RZ, RZ, 0x4 ;
ULDC.64 UR4, c[0x0][0x118] ;
IMAD R6, R0, 0x3, RZ ;
IMAD.WIDE R6, R6, R7, c[0x0][0x168] ;
LDG.E R2, [R6.64] ;
LDG.E R4, [R6.64+0x8] ;
LDG.E R3, [R6.64+0x4] ;
HFMA2.MMA R25, -RZ, RZ, 0, 4.76837158203125e-07 ;
IMAD R2, R2, 0x3, RZ ;
IMAD R4, R4, 0x3, RZ ;
IMAD.WIDE R22, R2, R25, c[0x0][0x170] ;
IMAD R3, R3, 0x3, RZ ;
LDG.E.64 R12, [R22.64] ;
IMAD.WIDE R26, R4, R25, c[0x0][0x170] ;
LDG.E.64 R4, [R22.64+0x10] ;
IMAD.WIDE R24, R3, R25, c[0x0][0x170] ;
LDG.E.64 R2, [R22.64+0x8] ;
LDG.E.64 R14, [R26.64+0x8] ;
LDG.E.64 R6, [R24.64+0x8] ;
LDG.E.64 R8, [R24.64] ;
LDG.E.64 R10, [R26.64+0x10] ;
LDG.E.64 R16, [R24.64+0x10] ;
LDG.E.64 R18, [R26.64] ;
BSSY B0, 0x480 ;
DADD R28, -R14, R2 ;
DADD R20, -R14, R6 ;
DMUL R28, R28, R8 ;
DADD R22, -R10, R4 ;
DFMA R20, R20, R12, -R28 ;
DMUL R22, R6, R22 ;
DADD R28, -R10, R16 ;
DFMA R28, R2, R28, -R22 ;
DADD R22, -R16, R4 ;
DFMA R14, R14, R22, R28 ;
DADD R22, R12, -R18 ;
DADD R2, -R6, R2 ;
DMUL R22, R16, R22 ;
DADD R16, R8, -R18 ;
DADD R8, R12, -R8 ;
DFMA R16, R4, R16, -R22 ;
DFMA R2, R2, R18, R20 ;
DMUL R14, R14, R14 ;
DFMA R8, R10, R8, R16 ;
DFMA R4, R2, R2, R14 ;
DFMA R4, R8, R8, R4 ;
MUFU.RSQ64H R7, R5 ;
IADD3 R6, R5, -0x3500000, RZ ;
IMAD.MOV.U32 R8, RZ, RZ, 0x0 ;
MOV R9, 0x3fd80000 ;
DMUL R2, R6, R6 ;
DFMA R2, R4, -R2, 1 ;
DFMA R8, R2, R8, 0.5 ;
DMUL R2, R6, R2 ;
ISETP.GE.U32.AND P0, PT, R6, 0x7ca00000, PT ;
DFMA R8, R8, R2, R6 ;
DMUL R10, R4, R8 ;
IADD3 R15, R9, -0x100000, RZ ;
IMAD.MOV.U32 R14, RZ, RZ, R8 ;
DFMA R12, R10, -R10, R4 ;
DFMA R2, R12, R14, R10 ;
@!P0 BRA 0x470 ;
MOV R2, 0x450 ;
CALL.REL.NOINC 0x4d0 ;
MOV R2, R6 ;
IMAD.MOV.U32 R3, RZ, RZ, R7 ;
BSYNC B0 ;
HFMA2.MMA R5, -RZ, RZ, 0, 4.76837158203125e-07 ;
DMUL R2, R2, 0.5 ;
IMAD.WIDE R4, R0, R5, c[0x0][0x178] ;
STG.E.64 [R4.64], R2 ;
EXIT ;
ISETP.GE.U32.AND P0, PT, R6, -0x3400000, PT ;
BSSY B1, 0x730 ;
IMAD.MOV.U32 R9, RZ, RZ, R15 ;
@!P0 BRA 0x590 ;
DFMA.RM R8, R12, R8, R10 ;
IADD3 R6, P0, R8, 0x1, RZ ;
IADD3.X R7, RZ, R9, RZ, P0, !PT ;
DFMA.RP R4, -R8, R6, R4 ;
DSETP.GT.AND P0, PT, R4, RZ, PT ;
FSEL R6, R6, R8, P0 ;
FSEL R7, R7, R9, P0 ;
BRA 0x720 ;
DSETP.NE.AND P0, PT, R4, RZ, PT ;
@!P0 BRA 0x710 ;
ISETP.GE.AND P0, PT, R5, RZ, PT ;
@!P0 IMAD.MOV.U32 R6, RZ, RZ, 0x0 ;
@!P0 MOV R7, 0xfff80000 ;
@!P0 BRA 0x720 ;
ISETP.GT.AND P0, PT, R5, 0x7fefffff, PT ;
@P0 BRA 0x710 ;
DMUL R4, R4, 8.11296384146066816958e+31 ;
IMAD.MOV.U32 R6, RZ, RZ, RZ ;
MOV R10, 0x0 ;
IMAD.MOV.U32 R11, RZ, RZ, 0x3fd80000 ;
MUFU.RSQ64H R7, R5 ;
DMUL R8, R6, R6 ;
DFMA R8, R4, -R8, 1 ;
DFMA R10, R8, R10, 0.5 ;
DMUL R8, R6, R8 ;
DFMA R8, R10, R8, R6 ;
DMUL R6, R4, R8 ;
IADD3 R9, R9, -0x100000, RZ ;
DFMA R10, R6, -R6, R4 ;
DFMA R6, R8, R10, R6 ;
IADD3 R7, R7, -0x3500000, RZ ;
BRA 0x720 ;
DADD R6, R4, R4 ;
BSYNC B1 ;
MOV R3, 0x0 ;
RET.REL.NODEC R2 0x0 ;
BRA 0x750;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
```
|
```amdasm
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected surface_area ; -- Begin function surface_area
.globl surface_area
.p2align 8
.type surface_area,@function
surface_area: ; @surface_area
; %bb.0:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
; %bb.1:
s_load_b128 s[4:7], s[0:1], 0x8
v_lshl_add_u32 v2, v1, 1, v1
s_load_b64 s[0:1], s[0:1], 0x18
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
global_load_b96 v[2:4], v[2:3], off
s_waitcnt vmcnt(0)
v_lshl_add_u32 v5, v2, 1, v2
v_lshl_add_u32 v7, v4, 1, v4
v_lshl_add_u32 v2, v3, 1, v3
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_ashrrev_i32_e32 v6, 31, v5
v_ashrrev_i32_e32 v8, 31, v7
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[4:5], 3, v[5:6]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[6:7], 3, v[7:8]
v_lshlrev_b64 v[2:3], 3, v[2:3]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v4, vcc_lo, s6, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v5, vcc_lo
s_delay_alu instid0(VALU_DEP_4)
v_add_co_u32 v6, vcc_lo, s6, v6
v_add_co_ci_u32_e32 v7, vcc_lo, s7, v7, vcc_lo
v_add_co_u32 v10, vcc_lo, s6, v2
s_clause 0x1
global_load_b64 v[14:15], v[4:5], off offset:16
global_load_b64 v[16:17], v[6:7], off offset:16
v_add_co_ci_u32_e32 v11, vcc_lo, s7, v3, vcc_lo
s_clause 0x3
global_load_b128 v[2:5], v[4:5], off
global_load_b128 v[6:9], v[6:7], off
global_load_b64 v[18:19], v[10:11], off offset:16
global_load_b128 v[10:13], v[10:11], off
s_waitcnt vmcnt(4)
v_add_f64 v[20:21], v[14:15], -v[16:17]
s_waitcnt vmcnt(2)
v_add_f64 v[22:23], v[4:5], -v[8:9]
s_waitcnt vmcnt(1)
v_add_f64 v[24:25], v[18:19], -v[16:17]
s_waitcnt vmcnt(0)
v_add_f64 v[26:27], v[12:13], -v[8:9]
v_add_f64 v[28:29], v[14:15], -v[18:19]
v_add_f64 v[30:31], v[2:3], -v[6:7]
v_mul_f64 v[20:21], v[12:13], v[20:21]
v_mul_f64 v[22:23], v[10:11], v[22:23]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_mul_f64 v[18:19], v[18:19], v[30:31]
v_fma_f64 v[20:21], v[4:5], v[24:25], -v[20:21]
v_add_f64 v[4:5], v[4:5], -v[12:13]
v_add_f64 v[12:13], v[10:11], -v[6:7]
v_fma_f64 v[22:23], v[2:3], v[26:27], -v[22:23]
v_add_f64 v[2:3], v[2:3], -v[10:11]
v_fma_f64 v[8:9], v[28:29], v[8:9], v[20:21]
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_fma_f64 v[10:11], v[14:15], v[12:13], -v[18:19]
v_fma_f64 v[4:5], v[4:5], v[6:7], v[22:23]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_mul_f64 v[6:7], v[8:9], v[8:9]
v_fma_f64 v[2:3], v[2:3], v[16:17], v[10:11]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[4:5], v[4:5], v[4:5], v[6:7]
v_fma_f64 v[2:3], v[2:3], v[2:3], v[4:5]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_gt_f64_e32 vcc_lo, 0x10000000, v[2:3]
v_cndmask_b32_e64 v0, 0, 1, vcc_lo
v_lshlrev_b32_e32 v0, 8, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_ldexp_f64 v[2:3], v[2:3], v0
v_cndmask_b32_e64 v0, 0, 0xffffff80, vcc_lo
v_rsq_f64_e32 v[4:5], v[2:3]
v_cmp_class_f64_e64 vcc_lo, v[2:3], 0x260
s_waitcnt_depctr 0xfff
v_mul_f64 v[6:7], v[2:3], v[4:5]
v_mul_f64 v[4:5], v[4:5], 0.5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[8:9], -v[4:5], v[6:7], 0.5
v_fma_f64 v[6:7], v[6:7], v[8:9], v[6:7]
v_fma_f64 v[4:5], v[4:5], v[8:9], v[4:5]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[8:9], -v[6:7], v[6:7], v[2:3]
v_fma_f64 v[6:7], v[8:9], v[4:5], v[6:7]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[8:9], -v[6:7], v[6:7], v[2:3]
v_fma_f64 v[4:5], v[8:9], v[4:5], v[6:7]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ldexp_f64 v[4:5], v[4:5], v0
v_dual_cndmask_b32 v3, v5, v3 :: v_dual_cndmask_b32 v2, v4, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mul_f64 v[3:4], v[2:3], 0.5
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b64 v[0:1], 3, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b64 v[0:1], v[3:4], off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel surface_area
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 32
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size surface_area, .Lfunc_end0-surface_area
; -- End function
.section .AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 736
; NumSgprs: 18
; NumVgprs: 32
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 3
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 32
; Occupancy: 16
; WaveLimiterHint : 1
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
.text
.protected multiply ; -- Begin function multiply
.globl multiply
.p2align 8
.type multiply,@function
multiply: ; @multiply
; %bb.0:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x44
s_load_b64 s[12:13], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s12, v1
s_cbranch_execz .LBB1_6
; %bb.1: ; %.preheader
s_clause 0x1
s_load_b256 s[4:11], s[0:1], 0x8
s_load_b128 s[0:3], s[0:1], 0x28
s_cmp_lt_i32 s13, 1
s_cbranch_scc1 .LBB1_4
; %bb.2: ; %.lr.ph
v_mul_lo_u32 v5, v1, s13
v_mov_b32_e32 v3, 0
v_mov_b32_e32 v4, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v6, 31, v5
v_lshlrev_b64 v[7:8], 2, v[5:6]
v_lshlrev_b64 v[9:10], 3, v[5:6]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v5, vcc_lo, s6, v7
v_add_co_ci_u32_e32 v6, vcc_lo, s7, v8, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v7, vcc_lo, s8, v9
v_add_co_ci_u32_e32 v8, vcc_lo, s9, v10, vcc_lo
.LBB1_3: ; =>This Inner Loop Header: Depth=1
global_load_b32 v9, v[5:6], off
s_add_i32 s13, s13, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
s_cmp_eq_u32 s13, 0
s_waitcnt vmcnt(0)
v_ashrrev_i32_e32 v10, 31, v9
v_lshlrev_b64 v[9:10], 3, v[9:10]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v9, vcc_lo, s10, v9
v_add_co_ci_u32_e32 v10, vcc_lo, s11, v10, vcc_lo
v_add_co_u32 v5, vcc_lo, v5, 4
global_load_b64 v[11:12], v[7:8], off
global_load_b64 v[9:10], v[9:10], off
v_add_co_ci_u32_e32 v6, vcc_lo, 0, v6, vcc_lo
v_add_co_u32 v7, vcc_lo, v7, 8
v_add_co_ci_u32_e32 v8, vcc_lo, 0, v8, vcc_lo
s_waitcnt vmcnt(0)
v_fma_f64 v[3:4], v[11:12], v[9:10], v[3:4]
s_cbranch_scc0 .LBB1_3
s_branch .LBB1_5
.LBB1_4:
v_mov_b32_e32 v3, 0
v_mov_b32_e32 v4, 0
.LBB1_5: ; %Flow66
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 3, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v5, vcc_lo, s10, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v6, vcc_lo, s11, v1, vcc_lo
global_load_b64 v[7:8], v[5:6], off
s_waitcnt vmcnt(0)
v_fma_f64 v[2:3], v[7:8], s[4:5], v[3:4]
v_add_co_u32 v7, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v8, vcc_lo, s1, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_store_b64 v[7:8], v[2:3], off
global_load_b64 v[4:5], v[5:6], off
s_waitcnt vmcnt(0)
v_add_f64 v[2:3], v[4:5], -v[2:3]
global_store_b64 v[0:1], v[2:3], off
.LBB1_6:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel multiply
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 312
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 13
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size multiply, .Lfunc_end1-multiply
; -- End function
.section .AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 412
; NumSgprs: 18
; NumVgprs: 13
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 13
; Occupancy: 16
; WaveLimiterHint : 1
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object ; @__hip_cuid_
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0 ; 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: surface_area
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: surface_area.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 32
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .offset: 8
.size: 8
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 40
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 48
.size: 8
.value_kind: global_buffer
- .offset: 56
.size: 4
.value_kind: hidden_block_count_x
- .offset: 60
.size: 4
.value_kind: hidden_block_count_y
- .offset: 64
.size: 4
.value_kind: hidden_block_count_z
- .offset: 68
.size: 2
.value_kind: hidden_group_size_x
- .offset: 70
.size: 2
.value_kind: hidden_group_size_y
- .offset: 72
.size: 2
.value_kind: hidden_group_size_z
- .offset: 74
.size: 2
.value_kind: hidden_remainder_x
- .offset: 76
.size: 2
.value_kind: hidden_remainder_y
- .offset: 78
.size: 2
.value_kind: hidden_remainder_z
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 112
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 120
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 312
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: multiply
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: multiply.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 13
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
```
| 7,066 | 7,961 |
539 |
Convert the following CUDA host assembly code to AMD host assembly:
```cudaasm
.file "tmpxft_000676f7_00000000-6_JCudaMatrixVectorMultKernel3.cudafe1.cpp"
.text
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z38__device_stub__Z12surface_areaiPiPdS0_iPiPdS0_
.type _Z38__device_stub__Z12surface_areaiPiPdS0_iPiPdS0_, @function
_Z38__device_stub__Z12surface_areaiPiPdS0_iPiPdS0_:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 28(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %rcx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq surface_area(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z38__device_stub__Z12surface_areaiPiPdS0_iPiPdS0_, .-_Z38__device_stub__Z12surface_areaiPiPdS0_iPiPdS0_
.globl surface_area
.type surface_area, @function
surface_area:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z38__device_stub__Z12surface_areaiPiPdS0_iPiPdS0_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size surface_area, .-surface_area
.globl _Z41__device_stub__Z8multiplyiidPiPdS0_S0_S0_iidPiPdS0_S0_S0_
.type _Z41__device_stub__Z8multiplyiidPiPdS0_S0_S0_iidPiPdS0_S0_S0_, @function
_Z41__device_stub__Z8multiplyiidPiPdS0_S0_S0_iidPiPdS0_S0_S0_:
.LFB2053:
.cfi_startproc
endbr64
subq $216, %rsp
.cfi_def_cfa_offset 224
movl %edi, 60(%rsp)
movl %esi, 56(%rsp)
movsd %xmm0, 48(%rsp)
movq %rdx, 40(%rsp)
movq %rcx, 32(%rsp)
movq %r8, 24(%rsp)
movq %r9, 16(%rsp)
movq 224(%rsp), %rax
movq %rax, 8(%rsp)
movq %fs:40, %rax
movq %rax, 200(%rsp)
xorl %eax, %eax
leaq 60(%rsp), %rax
movq %rax, 128(%rsp)
leaq 56(%rsp), %rax
movq %rax, 136(%rsp)
leaq 48(%rsp), %rax
movq %rax, 144(%rsp)
leaq 40(%rsp), %rax
movq %rax, 152(%rsp)
leaq 32(%rsp), %rax
movq %rax, 160(%rsp)
leaq 24(%rsp), %rax
movq %rax, 168(%rsp)
leaq 16(%rsp), %rax
movq %rax, 176(%rsp)
leaq 8(%rsp), %rax
movq %rax, 184(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
leaq 72(%rsp), %rcx
leaq 64(%rsp), %rdx
leaq 92(%rsp), %rsi
leaq 80(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 200(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $216, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 72(%rsp)
.cfi_def_cfa_offset 232
pushq 72(%rsp)
.cfi_def_cfa_offset 240
leaq 144(%rsp), %r9
movq 108(%rsp), %rcx
movl 116(%rsp), %r8d
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
leaq multiply(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 224
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2053:
.size _Z41__device_stub__Z8multiplyiidPiPdS0_S0_S0_iidPiPdS0_S0_S0_, .-_Z41__device_stub__Z8multiplyiidPiPdS0_S0_S0_iidPiPdS0_S0_S0_
.globl multiply
.type multiply, @function
multiply:
.LFB2054:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
pushq 24(%rsp)
.cfi_def_cfa_offset 32
call _Z41__device_stub__Z8multiplyiidPiPdS0_S0_S0_iidPiPdS0_S0_S0_
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size multiply, .-multiply
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "multiply"
.LC1:
.string "surface_area"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2056:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq multiply(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq surface_area(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2056:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
```
|
```amdasm
.text
.file "JCudaMatrixVectorMultKernel3.hip"
.globl __device_stub__surface_area # -- Begin function __device_stub__surface_area
.type __device_stub__surface_area,@function
__device_stub__surface_area: # @__device_stub__surface_area
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $112, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 4(%rsp), %rax
movl %edi, (%rax)
leaq 40(%rsp), %rdi
movq %rsi, (%rdi)
leaq 32(%rsp), %rsi
movq %rdx, (%rsi)
leaq 24(%rsp), %rdx
movq %rcx, (%rdx)
leaq 80(%rsp), %rbx
movq %rax, (%rbx)
movq %rdi, 8(%rbx)
movq %rsi, 16(%rbx)
movq %rdx, 24(%rbx)
leaq 64(%rsp), %r14
leaq 48(%rsp), %r15
leaq 16(%rsp), %r12
leaq 8(%rsp), %r13
movq %r14, %rdi
movq %r15, %rsi
movq %r12, %rdx
movq %r13, %rcx
callq __hipPopCallConfiguration
movq (%r14), %rsi
movl 8(%r14), %edx
movq (%r15), %rcx
movl 8(%r15), %r8d
movl $surface_area, %edi
movq %rbx, %r9
pushq (%r13)
.cfi_adjust_cfa_offset 8
pushq (%r12)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $128, %rsp
.cfi_adjust_cfa_offset -128
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size __device_stub__surface_area, .Lfunc_end0-__device_stub__surface_area
.cfi_endproc
# -- End function
.globl __device_stub__multiply # -- Begin function __device_stub__multiply
.type __device_stub__multiply,@function
__device_stub__multiply: # @__device_stub__multiply
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $160, %rsp
.cfi_def_cfa_offset 208
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 4(%rsp), %rax
movl %edi, (%rax)
movq %rsp, %rdi
movl %esi, (%rdi)
leaq 56(%rsp), %rsi
movsd %xmm0, (%rsi)
leaq 48(%rsp), %r10
movq %rdx, (%r10)
leaq 40(%rsp), %rdx
movq %rcx, (%rdx)
leaq 32(%rsp), %rcx
movq %r8, (%rcx)
leaq 24(%rsp), %r8
movq %r9, (%r8)
leaq 96(%rsp), %rbx
movq %rax, (%rbx)
movq %rdi, 8(%rbx)
movq %rsi, 16(%rbx)
movq %r10, 24(%rbx)
movq %rdx, 32(%rbx)
movq %rcx, 40(%rbx)
movq %r8, 48(%rbx)
leaq 208(%rsp), %rax
movq %rax, 56(%rbx)
leaq 80(%rsp), %r14
leaq 64(%rsp), %r15
leaq 16(%rsp), %r12
leaq 8(%rsp), %r13
movq %r14, %rdi
movq %r15, %rsi
movq %r12, %rdx
movq %r13, %rcx
callq __hipPopCallConfiguration
movq (%r14), %rsi
movl 8(%r14), %edx
movq (%r15), %rcx
movl 8(%r15), %r8d
movl $multiply, %edi
movq %rbx, %r9
pushq (%r13)
.cfi_adjust_cfa_offset 8
pushq (%r12)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $176, %rsp
.cfi_adjust_cfa_offset -176
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size __device_stub__multiply, .Lfunc_end1-__device_stub__multiply
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
movq __hip_gpubin_handle(%rip), %rbx
testq %rbx, %rbx
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, %rbx
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $surface_area, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $multiply, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type surface_area,@object # @surface_area
.section .rodata,"a",@progbits
.globl surface_area
.p2align 3, 0x0
surface_area:
.quad __device_stub__surface_area
.size surface_area, 8
.type multiply,@object # @multiply
.globl multiply
.p2align 3, 0x0
multiply:
.quad __device_stub__multiply
.size multiply, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "surface_area"
.size .L__unnamed_1, 13
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "multiply"
.size .L__unnamed_2, 9
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __device_stub__surface_area
.addrsig_sym __device_stub__multiply
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym surface_area
.addrsig_sym multiply
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
```
| 3,175 | 3,144 |
540 |
Convert the following CUDA device assembly code to AMD device assembly:
```cudaasm
code for sm_80
Function : _Z7computePfii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
MOV R1, c[0x0][0x28] ;
S2R R0, SR_TID.X ;
MOV R4, c[0x0][0x160] ;
ULDC.64 UR4, c[0x0][0x118] ;
MOV R5, c[0x0][0x164] ;
S2R R3, SR_CTAID.X ;
IMAD R0, R3, c[0x0][0x0], R0 ;
I2F.F64 R2, R0 ;
DADD R2, R2, R2 ;
F2F.F32.F64 R3, R2 ;
STG.E [R4.64], R3 ;
EXIT ;
BRA 0xc0;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
```
|
```amdasm
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z7computePfii ; -- Begin function _Z7computePfii
.globl _Z7computePfii
.p2align 8
.type _Z7computePfii,@function
_Z7computePfii: ; @_Z7computePfii
; %bb.0:
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x8
s_load_b32 s4, s[0:1], 0x1c
v_and_b32_e32 v1, 31, v0
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_cmp_gt_i32_e32 vcc_lo, s3, v1
s_and_saveexec_b32 s3, vcc_lo
s_cbranch_execz .LBB0_3
; %bb.1:
s_cmp_lt_i32 s2, 1
;;#ASMSTART
.reg .s32 %r111;
.reg .s32 %r112;
.reg .s32 %r113;
.reg .s32 %r114;
.reg .s32 %r115;
.reg .s32 %r116;
.reg .s32 %r117;
.reg .s32 %r118;
.reg .s32 %r119;
.reg .s32 %r120;
.reg .s32 %r121;
.reg .s32 %r122;
.reg .s32 %r123;
.reg .s32 %r124;
.reg .s32 %r125;
.reg .s32 %r126;
.reg .s32 %r127;
.reg .s32 %r128;
mov.s32 %r112, 44;
mov.s32 %r113, %r112;
mov.s32 %r114, 22;
mov.s32 %r115, 33;
mov.s32 %r116, 123;
mov.s32 %r117, 242;
mov.s32 %r118, 334;
mov.s32 %r119, 562;
mov.s32 %r120, 256;
mov.s32 %r121, 156;
mov.s32 %r122, 256;
mov.s32 %r123, 556;
mov.s32 %r124, 856;
mov.s32 %r125, 356;
mov.s32 %r126, 556;
mov.s32 %r127, 656;
mov.s32 %r128, 56;
;;#ASMEND
s_cbranch_scc1 .LBB0_3
.LBB0_2: ; %.lr.ph
; =>This Inner Loop Header: Depth=1
s_add_i32 s2, s2, -1
;;#ASMSTART
add.s32 %r113, %r111, %r113;
add.s32 %r114, %r111, %r114;
add.s32 %r115, %r111, %r115;
add.s32 %r116, %r111, %r116;
add.s32 %r117, %r111, %r117;
add.s32 %r118, %r111, %r118;
add.s32 %r119, %r111, %r119;
add.s32 %r120, %r111, %r120;
add.s32 %r121, %r111, %r121;
add.s32 %r122, %r111, %r122;
add.s32 %r123, %r111, %r123;
add.s32 %r124, %r111, %r124;
add.s32 %r125, %r111, %r125;
add.s32 %r126, %r111, %r126;
add.s32 %r127, %r111, %r127;
add.s32 %r128, %r111, %r128;
add.s32 %r113, %r111, %r113;
add.s32 %r114, %r111, %r114;
add.s32 %r115, %r111, %r115;
add.s32 %r116, %r111, %r116;
add.s32 %r117, %r111, %r117;
add.s32 %r118, %r111, %r118;
add.s32 %r119, %r111, %r119;
add.s32 %r120, %r111, %r120;
add.s32 %r121, %r111, %r121;
add.s32 %r122, %r111, %r122;
add.s32 %r123, %r111, %r123;
add.s32 %r124, %r111, %r124;
add.s32 %r125, %r111, %r125;
add.s32 %r126, %r111, %r126;
add.s32 %r127, %r111, %r127;
add.s32 %r128, %r111, %r128;
add.s32 %r113, %r111, %r113;
add.s32 %r114, %r111, %r114;
add.s32 %r115, %r111, %r115;
add.s32 %r116, %r111, %r116;
add.s32 %r117, %r111, %r117;
add.s32 %r118, %r111, %r118;
add.s32 %r119, %r111, %r119;
add.s32 %r120, %r111, %r120;
add.s32 %r121, %r111, %r121;
add.s32 %r122, %r111, %r122;
add.s32 %r123, %r111, %r123;
add.s32 %r124, %r111, %r124;
add.s32 %r125, %r111, %r125;
add.s32 %r126, %r111, %r126;
add.s32 %r127, %r111, %r127;
add.s32 %r128, %r111, %r128;
add.s32 %r113, %r111, %r113;
add.s32 %r114, %r111, %r114;
add.s32 %r115, %r111, %r115;
add.s32 %r116, %r111, %r116;
add.s32 %r117, %r111, %r117;
add.s32 %r118, %r111, %r118;
add.s32 %r119, %r111, %r119;
add.s32 %r120, %r111, %r120;
add.s32 %r121, %r111, %r121;
add.s32 %r122, %r111, %r122;
add.s32 %r123, %r111, %r123;
add.s32 %r124, %r111, %r124;
add.s32 %r125, %r111, %r125;
add.s32 %r126, %r111, %r126;
add.s32 %r127, %r111, %r127;
add.s32 %r128, %r111, %r128;
add.s32 %r113, %r111, %r113;
add.s32 %r114, %r111, %r114;
add.s32 %r115, %r111, %r115;
add.s32 %r116, %r111, %r116;
add.s32 %r117, %r111, %r117;
add.s32 %r118, %r111, %r118;
add.s32 %r119, %r111, %r119;
add.s32 %r120, %r111, %r120;
add.s32 %r121, %r111, %r121;
add.s32 %r122, %r111, %r122;
add.s32 %r123, %r111, %r123;
add.s32 %r124, %r111, %r124;
add.s32 %r125, %r111, %r125;
add.s32 %r126, %r111, %r126;
add.s32 %r127, %r111, %r127;
add.s32 %r128, %r111, %r128;
add.s32 %r113, %r111, %r113;
add.s32 %r114, %r111, %r114;
add.s32 %r115, %r111, %r115;
add.s32 %r116, %r111, %r116;
add.s32 %r117, %r111, %r117;
add.s32 %r118, %r111, %r118;
add.s32 %r119, %r111, %r119;
add.s32 %r120, %r111, %r120;
add.s32 %r121, %r111, %r121;
add.s32 %r122, %r111, %r122;
add.s32 %r123, %r111, %r123;
add.s32 %r124, %r111, %r124;
add.s32 %r125, %r111, %r125;
add.s32 %r126, %r111, %r126;
add.s32 %r127, %r111, %r127;
add.s32 %r128, %r111, %r128;
add.s32 %r113, %r111, %r113;
add.s32 %r114, %r111, %r114;
add.s32 %r115, %r111, %r115;
add.s32 %r116, %r111, %r116;
add.s32 %r117, %r111, %r117;
add.s32 %r118, %r111, %r118;
add.s32 %r119, %r111, %r119;
add.s32 %r120, %r111, %r120;
add.s32 %r121, %r111, %r121;
add.s32 %r122, %r111, %r122;
add.s32 %r123, %r111, %r123;
add.s32 %r124, %r111, %r124;
add.s32 %r125, %r111, %r125;
add.s32 %r126, %r111, %r126;
add.s32 %r127, %r111, %r127;
add.s32 %r128, %r111, %r128;
add.s32 %r113, %r111, %r113;
add.s32 %r114, %r111, %r114;
add.s32 %r115, %r111, %r115;
add.s32 %r116, %r111, %r116;
add.s32 %r117, %r111, %r117;
add.s32 %r118, %r111, %r118;
add.s32 %r119, %r111, %r119;
add.s32 %r120, %r111, %r120;
add.s32 %r121, %r111, %r121;
add.s32 %r122, %r111, %r122;
add.s32 %r123, %r111, %r123;
add.s32 %r124, %r111, %r124;
add.s32 %r125, %r111, %r125;
add.s32 %r126, %r111, %r126;
add.s32 %r127, %r111, %r127;
add.s32 %r128, %r111, %r128;
add.s32 %r113, %r111, %r113;
add.s32 %r114, %r111, %r114;
add.s32 %r115, %r111, %r115;
add.s32 %r116, %r111, %r116;
add.s32 %r117, %r111, %r117;
add.s32 %r118, %r111, %r118;
add.s32 %r119, %r111, %r119;
add.s32 %r120, %r111, %r120;
add.s32 %r121, %r111, %r121;
add.s32 %r122, %r111, %r122;
add.s32 %r123, %r111, %r123;
add.s32 %r124, %r111, %r124;
add.s32 %r125, %r111, %r125;
add.s32 %r126, %r111, %r126;
add.s32 %r127, %r111, %r127;
add.s32 %r128, %r111, %r128;
add.s32 %r113, %r111, %r113;
add.s32 %r114, %r111, %r114;
add.s32 %r115, %r111, %r115;
add.s32 %r116, %r111, %r116;
add.s32 %r117, %r111, %r117;
add.s32 %r118, %r111, %r118;
add.s32 %r119, %r111, %r119;
add.s32 %r120, %r111, %r120;
add.s32 %r121, %r111, %r121;
add.s32 %r122, %r111, %r122;
add.s32 %r123, %r111, %r123;
add.s32 %r124, %r111, %r124;
add.s32 %r125, %r111, %r125;
add.s32 %r126, %r111, %r126;
add.s32 %r127, %r111, %r127;
add.s32 %r128, %r111, %r128;
add.s32 %r113, %r111, %r113;
add.s32 %r114, %r111, %r114;
add.s32 %r115, %r111, %r115;
add.s32 %r116, %r111, %r116;
add.s32 %r117, %r111, %r117;
add.s32 %r118, %r111, %r118;
add.s32 %r119, %r111, %r119;
add.s32 %r120, %r111, %r120;
add.s32 %r121, %r111, %r121;
add.s32 %r122, %r111, %r122;
add.s32 %r123, %r111, %r123;
add.s32 %r124, %r111, %r124;
add.s32 %r125, %r111, %r125;
add.s32 %r126, %r111, %r126;
add.s32 %r127, %r111, %r127;
add.s32 %r128, %r111, %r128;
add.s32 %r113, %r111, %r113;
add.s32 %r114, %r111, %r114;
add.s32 %r115, %r111, %r115;
add.s32 %r116, %r111, %r116;
add.s32 %r117, %r111, %r117;
add.s32 %r118, %r111, %r118;
add.s32 %r119, %r111, %r119;
add.s32 %r120, %r111, %r120;
add.s32 %r121, %r111, %r121;
add.s32 %r122, %r111, %r122;
add.s32 %r123, %r111, %r123;
add.s32 %r124, %r111, %r124;
add.s32 %r125, %r111, %r125;
add.s32 %r126, %r111, %r126;
add.s32 %r127, %r111, %r127;
add.s32 %r128, %r111, %r128;
add.s32 %r113, %r111, %r113;
add.s32 %r114, %r111, %r114;
add.s32 %r115, %r111, %r115;
add.s32 %r116, %r111, %r116;
add.s32 %r117, %r111, %r117;
add.s32 %r118, %r111, %r118;
add.s32 %r119, %r111, %r119;
add.s32 %r120, %r111, %r120;
add.s32 %r121, %r111, %r121;
add.s32 %r122, %r111, %r122;
add.s32 %r123, %r111, %r123;
add.s32 %r124, %r111, %r124;
add.s32 %r125, %r111, %r125;
add.s32 %r126, %r111, %r126;
add.s32 %r127, %r111, %r127;
add.s32 %r128, %r111, %r128;
add.s32 %r113, %r111, %r113;
add.s32 %r114, %r111, %r114;
add.s32 %r115, %r111, %r115;
add.s32 %r116, %r111, %r116;
add.s32 %r117, %r111, %r117;
add.s32 %r118, %r111, %r118;
add.s32 %r119, %r111, %r119;
add.s32 %r120, %r111, %r120;
add.s32 %r121, %r111, %r121;
add.s32 %r122, %r111, %r122;
add.s32 %r123, %r111, %r123;
add.s32 %r124, %r111, %r124;
add.s32 %r125, %r111, %r125;
add.s32 %r126, %r111, %r126;
add.s32 %r127, %r111, %r127;
add.s32 %r128, %r111, %r128;
add.s32 %r113, %r111, %r113;
add.s32 %r114, %r111, %r114;
add.s32 %r115, %r111, %r115;
add.s32 %r116, %r111, %r116;
add.s32 %r117, %r111, %r117;
add.s32 %r118, %r111, %r118;
add.s32 %r119, %r111, %r119;
add.s32 %r120, %r111, %r120;
add.s32 %r121, %r111, %r121;
add.s32 %r122, %r111, %r122;
add.s32 %r123, %r111, %r123;
add.s32 %r124, %r111, %r124;
add.s32 %r125, %r111, %r125;
add.s32 %r126, %r111, %r126;
add.s32 %r127, %r111, %r127;
add.s32 %r128, %r111, %r128;
add.s32 %r113, %r111, %r113;
add.s32 %r114, %r111, %r114;
add.s32 %r115, %r111, %r115;
add.s32 %r116, %r111, %r116;
add.s32 %r117, %r111, %r117;
add.s32 %r118, %r111, %r118;
add.s32 %r119, %r111, %r119;
add.s32 %r120, %r111, %r120;
add.s32 %r121, %r111, %r121;
add.s32 %r122, %r111, %r122;
add.s32 %r123, %r111, %r123;
add.s32 %r124, %r111, %r124;
add.s32 %r125, %r111, %r125;
add.s32 %r126, %r111, %r126;
add.s32 %r127, %r111, %r127;
add.s32 %r128, %r111, %r128;
;;#ASMEND
s_cmp_lg_u32 s2, 0
s_cbranch_scc1 .LBB0_2
.LBB0_3: ; %.loopexit
s_or_b32 exec_lo, exec_lo, s3
s_and_b32 s2, 0xffff, s4
s_load_b64 s[0:1], s[0:1], 0x0
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_f64_i32_e32 v[0:1], v1
v_add_f64 v[0:1], v[0:1], v[0:1]
s_delay_alu instid0(VALU_DEP_1)
v_cvt_f32_f64_e32 v0, v[0:1]
v_mov_b32_e32 v1, 0
s_waitcnt lgkmcnt(0)
global_store_b32 v1, v0, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z7computePfii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z7computePfii, .Lfunc_end0-_Z7computePfii
; -- End function
.section .AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 5964
; NumSgprs: 18
; NumVgprs: 3
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 3
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object ; @__hip_cuid_
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0 ; 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z7computePfii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z7computePfii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
```
| 265 | 8,580 |
541 |
Convert the following CUDA host assembly code to AMD host assembly:
```cudaasm
.file "tmpxft_001860ce_00000000-6_iadd_32p_asm.cudafe1.cpp"
.text
.globl _ZSt21ios_base_library_initv
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3673:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3673:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "Usage ./binary <num_blocks> <num_threads_per_block> <iterations>threads active per warp"
.text
.globl _Z5usagev
.type _Z5usagev, @function
_Z5usagev:
.LFB3669:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movl $87, %edx
leaq .LC0(%rip), %rsi
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %rbx
testq %rbx, %rbx
je .L8
cmpb $0, 56(%rbx)
je .L5
movzbl 67(%rbx), %esi
.L6:
movsbl %sil, %esi
leaq _ZSt4cout(%rip), %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
popq %rbx
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L8:
.cfi_restore_state
call _ZSt16__throw_bad_castv@PLT
.L5:
movq %rbx, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%rbx), %rax
movl $10, %esi
movq %rbx, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L6
.cfi_endproc
.LFE3669:
.size _Z5usagev, .-_Z5usagev
.globl _Z28__device_stub__Z7computePfiiPfii
.type _Z28__device_stub__Z7computePfiiPfii, @function
_Z28__device_stub__Z7computePfiiPfii:
.LFB3695:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rax
movq %rax, 96(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L13
.L9:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L14
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L13:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z7computePfii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L9
.L14:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3695:
.size _Z28__device_stub__Z7computePfiiPfii, .-_Z28__device_stub__Z7computePfiiPfii
.globl _Z7computePfii
.type _Z7computePfii, @function
_Z7computePfii:
.LFB3696:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z28__device_stub__Z7computePfiiPfii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3696:
.size _Z7computePfii, .-_Z7computePfii
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "GPU Elapsed Time = "
.text
.globl main
.type main, @function
main:
.LFB3670:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $56, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
cmpl $5, %edi
jne .L22
movq %rsi, %rbx
movq 8(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %rbp
movq 16(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %r12
movq 24(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %r13
movq 32(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %rbx
movl $4, %esi
leaq d_res(%rip), %rdi
call cudaMalloc@PLT
movq %rsp, %rdi
call cudaEventCreate@PLT
leaq 8(%rsp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq (%rsp), %rdi
call cudaEventRecord@PLT
call cudaProfilerStart@PLT
movl %r12d, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl %ebp, 16(%rsp)
movl $1, 20(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L23
.L19:
call cudaProfilerStop@PLT
movl $0, %esi
movq 8(%rsp), %rdi
call cudaEventRecord@PLT
movq 8(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 28(%rsp), %rdi
movq 8(%rsp), %rdx
movq (%rsp), %rsi
call cudaEventElapsedTime@PLT
leaq .LC1(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
pxor %xmm0, %xmm0
cvtss2sd 28(%rsp), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq (%rsp), %rdi
call cudaEventDestroy@PLT
movq 8(%rsp), %rdi
call cudaEventDestroy@PLT
call cudaDeviceSynchronize@PLT
movl $2, %ecx
movl $4, %edx
movq d_res(%rip), %rsi
movq h_res(%rip), %rdi
call cudaMemcpy@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L24
movl $0, %eax
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L22:
.cfi_restore_state
call _Z5usagev
movl $1, %edi
call exit@PLT
.L23:
movl %ebx, %edx
movl %r13d, %esi
movq d_res(%rip), %rdi
call _Z28__device_stub__Z7computePfiiPfii
jmp .L19
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3670:
.size main, .-main
.section .rodata.str1.1
.LC2:
.string "_Z7computePfii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3698:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z7computePfii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3698:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl d_res
.bss
.align 8
.type d_res, @object
.size d_res, 8
d_res:
.zero 8
.globl d_C
.align 8
.type d_C, @object
.size d_C, 8
d_C:
.zero 8
.globl d_B
.align 8
.type d_B, @object
.size d_B, 8
d_B:
.zero 8
.globl d_A
.align 8
.type d_A, @object
.size d_A, 8
d_A:
.zero 8
.globl h_res
.align 8
.type h_res, @object
.size h_res, 8
h_res:
.zero 8
.globl h_C
.align 8
.type h_C, @object
.size h_C, 8
h_C:
.zero 8
.globl h_B
.align 8
.type h_B, @object
.size h_B, 8
h_B:
.zero 8
.globl h_A
.align 8
.type h_A, @object
.size h_A, 8
h_A:
.zero 8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
```
|
```amdasm
.text
.file "iadd_32p_asm.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z22__device_stub__computePfii # -- Begin function _Z22__device_stub__computePfii
.type _Z22__device_stub__computePfii,@function
_Z22__device_stub__computePfii: # @_Z22__device_stub__computePfii
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $96, %rsp
.cfi_def_cfa_offset 144
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 24(%rsp), %rax
movq %rdi, (%rax)
leaq 4(%rsp), %rcx
movl %esi, (%rcx)
movq %rsp, %rsi
movl %edx, (%rsi)
leaq 64(%rsp), %rbx
movq %rax, (%rbx)
movq %rcx, 8(%rbx)
movq %rsi, 16(%rbx)
leaq 48(%rsp), %r14
leaq 32(%rsp), %r15
leaq 16(%rsp), %r12
leaq 8(%rsp), %r13
movq %r14, %rdi
movq %r15, %rsi
movq %r12, %rdx
movq %r13, %rcx
callq __hipPopCallConfiguration
movq (%r14), %rsi
movl 8(%r14), %edx
movq (%r15), %rcx
movl 8(%r15), %r8d
movl $_Z7computePfii, %edi
movq %rbx, %r9
pushq (%r13)
.cfi_adjust_cfa_offset 8
pushq (%r12)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $112, %rsp
.cfi_adjust_cfa_offset -112
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z22__device_stub__computePfii, .Lfunc_end0-_Z22__device_stub__computePfii
.cfi_endproc
# -- End function
.globl _Z5usagev # -- Begin function _Z5usagev
.type _Z5usagev,@function
_Z5usagev: # @_Z5usagev
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
movl $_ZSt4cout, %ebx
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $87, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rdi
addq %rbx, %rdi
movl $10, %esi
callq _ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
popq %rbx
.cfi_def_cfa_offset 8
jmp _ZNSo5flushEv # TAILCALL
.Lfunc_end1:
.size _Z5usagev, .Lfunc_end1-_Z5usagev
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $32, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
cmpl $5, %edi
jne .LBB2_4
# %bb.1:
movq %rsi, %r12
movq 8(%rsi), %rdi
callq atoi
movl %eax, %r14d
movq 16(%r12), %rdi
callq atoi
movl %eax, %r15d
movq 24(%r12), %rdi
callq atoi
movl %eax, %ebx
movq 32(%r12), %rdi
callq atoi
movl %eax, %ebp
movl $d_res, %edi
movl $4, %esi
callq hipMalloc
leaq 16(%rsp), %r12
movq %r12, %rdi
callq hipEventCreate
leaq 8(%rsp), %rdi
callq hipEventCreate
movq (%r12), %rdi
xorl %esi, %esi
callq hipEventRecord
callq hipProfilerStart
movl %r14d, %edi
btsq $32, %rdi
movl %r15d, %edx
btsq $32, %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_3
# %bb.2:
movq d_res(%rip), %rdi
movl %ebx, %esi
movl %ebp, %edx
callq _Z22__device_stub__computePfii
.LBB2_3:
callq hipProfilerStop
movq 8(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 8(%rsp), %rdi
callq hipEventSynchronize
movq 16(%rsp), %rsi
movq 8(%rsp), %rdx
leaq 28(%rsp), %rbx
movq %rbx, %rdi
callq hipEventElapsedTime
movl $_ZSt4cout, %edi
movl $.L.str.1, %esi
movl $19, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
cvtss2sd (%rbx), %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq %rax, %rbx
movq (%rax), %rax
movq -24(%rax), %rdi
addq %rbx, %rdi
movl $10, %esi
callq _ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
movsbl %al, %esi
movq %rbx, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq 16(%rsp), %rdi
callq hipEventDestroy
movq 8(%rsp), %rdi
callq hipEventDestroy
callq hipDeviceSynchronize
movq h_res(%rip), %rdi
movq d_res(%rip), %rsi
movl $4, %edx
movl $2, %ecx
callq hipMemcpy
xorl %eax, %eax
addq $32, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB2_4:
.cfi_def_cfa_offset 80
callq _Z5usagev
movl $1, %edi
callq exit
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, %rdi
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7computePfii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type h_A,@object # @h_A
.bss
.globl h_A
.p2align 3, 0x0
h_A:
.quad 0
.size h_A, 8
.type h_B,@object # @h_B
.globl h_B
.p2align 3, 0x0
h_B:
.quad 0
.size h_B, 8
.type h_C,@object # @h_C
.globl h_C
.p2align 3, 0x0
h_C:
.quad 0
.size h_C, 8
.type h_res,@object # @h_res
.globl h_res
.p2align 3, 0x0
h_res:
.quad 0
.size h_res, 8
.type d_A,@object # @d_A
.globl d_A
.p2align 3, 0x0
d_A:
.quad 0
.size d_A, 8
.type d_B,@object # @d_B
.globl d_B
.p2align 3, 0x0
d_B:
.quad 0
.size d_B, 8
.type d_C,@object # @d_C
.globl d_C
.p2align 3, 0x0
d_C:
.quad 0
.size d_C, 8
.type d_res,@object # @d_res
.globl d_res
.p2align 3, 0x0
d_res:
.quad 0
.size d_res, 8
.type _Z7computePfii,@object # @_Z7computePfii
.section .rodata,"a",@progbits
.globl _Z7computePfii
.p2align 3, 0x0
_Z7computePfii:
.quad _Z22__device_stub__computePfii
.size _Z7computePfii, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Usage ./binary <num_blocks> <num_threads_per_block> <iterations>threads active per warp"
.size .L.str, 88
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "GPU Elapsed Time = "
.size .L.str.1, 20
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z7computePfii"
.size .L__unnamed_1, 15
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__computePfii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym d_res
.addrsig_sym _Z7computePfii
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
```
| 3,994 | 4,142 |
542 |
Convert the following CUDA device assembly code to AMD device assembly:
```cudaasm
code for sm_80
Function : _Z9addVectorPfS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
MOV R1, c[0x0][0x28] ;
S2R R0, SR_TID.X ;
HFMA2.MMA R9, -RZ, RZ, 0, 0 ;
ULDC.64 UR4, c[0x0][0x118] ;
MOV R8, R9.reuse ;
ULDC.64 UR6, c[0x0][0x168] ;
LEA R2, R0, R9, 0xa ;
MOV R3, 0x4 ;
IADD3 R9, R9, 0x1, RZ ;
MOV R10, c[0x0][0x160] ;
IMAD.WIDE R2, R2, R3, c[0x0][0x170] ;
ISETP.GE.U32.AND P2, PT, R9, 0x400, PT ;
MOV R11, c[0x0][0x164] ;
MOV R12, RZ ;
MOV R6, UR6 ;
IMAD.WIDE R4, R8, 0x4, R10 ;
MOV R7, UR7 ;
LDG.E R14, [R4.64] ;
IMAD.WIDE R6, R0, 0x4, R6 ;
LDG.E R13, [R6.64] ;
FADD R13, R13, R14 ;
STG.E [R2.64], R13 ;
LDG.E R14, [R6.64+0x1000] ;
LDG.E R15, [R4.64+0x1000] ;
FADD R15, R14, R15 ;
STG.E [R2.64], R15 ;
LDG.E R14, [R6.64+0x2000] ;
LDG.E R17, [R4.64+0x2000] ;
FADD R17, R14, R17 ;
STG.E [R2.64], R17 ;
LDG.E R14, [R6.64+0x3000] ;
LDG.E R19, [R4.64+0x3000] ;
FADD R19, R14, R19 ;
STG.E [R2.64], R19 ;
LDG.E R13, [R6.64+0x4000] ;
LDG.E R14, [R4.64+0x4000] ;
FADD R13, R13, R14 ;
STG.E [R2.64], R13 ;
LDG.E R14, [R6.64+0x5000] ;
LDG.E R15, [R4.64+0x5000] ;
FADD R15, R14, R15 ;
STG.E [R2.64], R15 ;
LDG.E R14, [R6.64+0x6000] ;
LDG.E R17, [R4.64+0x6000] ;
FADD R17, R14, R17 ;
STG.E [R2.64], R17 ;
LDG.E R14, [R6.64+0x7000] ;
LDG.E R19, [R4.64+0x7000] ;
FADD R19, R14, R19 ;
STG.E [R2.64], R19 ;
LDG.E R13, [R6.64+0x8000] ;
LDG.E R14, [R4.64+0x8000] ;
FADD R13, R13, R14 ;
STG.E [R2.64], R13 ;
LDG.E R14, [R6.64+0x9000] ;
LDG.E R15, [R4.64+0x9000] ;
FADD R15, R14, R15 ;
STG.E [R2.64], R15 ;
LDG.E R14, [R6.64+0xa000] ;
LDG.E R17, [R4.64+0xa000] ;
FADD R17, R14, R17 ;
STG.E [R2.64], R17 ;
LDG.E R14, [R6.64+0xb000] ;
LDG.E R19, [R4.64+0xb000] ;
FADD R19, R14, R19 ;
STG.E [R2.64], R19 ;
LDG.E R13, [R6.64+0xc000] ;
LDG.E R14, [R4.64+0xc000] ;
FADD R13, R13, R14 ;
STG.E [R2.64], R13 ;
LDG.E R14, [R6.64+0xd000] ;
LDG.E R15, [R4.64+0xd000] ;
FADD R15, R14, R15 ;
STG.E [R2.64], R15 ;
LDG.E R14, [R6.64+0xe000] ;
LDG.E R17, [R4.64+0xe000] ;
IADD3 R12, R12, 0x10, RZ ;
FADD R17, R14, R17 ;
STG.E [R2.64], R17 ;
LDG.E R14, [R6.64+0xf000] ;
LDG.E R19, [R4.64+0xf000] ;
ISETP.NE.AND P0, PT, R12, 0x400, PT ;
UIADD3 UR6, UP0, UR6, 0x10000, URZ ;
IADD3 R10, P1, R10, 0x10000, RZ ;
UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ;
IADD3.X R11, RZ, R11, RZ, P1, !PT ;
FADD R19, R14, R19 ;
STG.E [R2.64], R19 ;
@P0 BRA 0xe0 ;
@!P2 BRA 0x40 ;
EXIT ;
BRA 0x5b0;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
```
|
```amdasm
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9addVectorPfS_S_ ; -- Begin function _Z9addVectorPfS_S_
.globl _Z9addVectorPfS_S_
.p2align 8
.type _Z9addVectorPfS_S_,@function
_Z9addVectorPfS_S_: ; @_Z9addVectorPfS_S_
; %bb.0:
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
v_dual_mov_b32 v1, 0 :: v_dual_lshlrev_b32 v2, 2, v0
v_lshlrev_b32_e32 v4, 10, v0
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v5, s2, s6, v2
v_add_co_ci_u32_e64 v6, null, s7, 0, s2
s_mov_b32 s6, 0
.LBB0_1: ; %.preheader
; =>This Loop Header: Depth=1
; Child Loop BB0_2 Depth 2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v0, s6, v4
s_mov_b64 s[2:3], 0
v_lshlrev_b64 v[2:3], 2, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s0, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
.LBB0_2: ; Parent Loop BB0_1 Depth=1
; => This Inner Loop Header: Depth=2
v_add_co_u32 v7, vcc_lo, v5, s2
v_add_co_ci_u32_e32 v8, vcc_lo, s3, v6, vcc_lo
s_add_u32 s8, s4, s2
s_addc_u32 s9, s5, s3
global_load_b32 v0, v1, s[8:9]
global_load_b32 v7, v[7:8], off
s_add_u32 s2, s2, 0x1000
s_addc_u32 s3, s3, 0
s_cmp_eq_u32 s2, 0x400000
s_waitcnt vmcnt(0)
v_add_f32_e32 v0, v0, v7
global_store_b32 v[2:3], v0, off
s_cbranch_scc0 .LBB0_2
; %bb.3: ; in Loop: Header=BB0_1 Depth=1
s_add_i32 s6, s6, 1
s_add_u32 s4, s4, 4
s_addc_u32 s5, s5, 0
s_cmpk_eq_i32 s6, 0x400
s_cbranch_scc0 .LBB0_1
; %bb.4:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9addVectorPfS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 10
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9addVectorPfS_S_, .Lfunc_end0-_Z9addVectorPfS_S_
; -- End function
.section .AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 204
; NumSgprs: 12
; NumVgprs: 9
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 1
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 12
; NumVGPRsForWavesPerEU: 9
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object ; @__hip_cuid_
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0 ; 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9addVectorPfS_S_
.private_segment_fixed_size: 0
.sgpr_count: 12
.sgpr_spill_count: 0
.symbol: _Z9addVectorPfS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
```
| 1,679 | 2,370 |
543 |
Convert the following CUDA host assembly code to AMD host assembly:
```cudaasm
.file "tmpxft_0019adce_00000000-6_test_6.cudafe1.cpp"
.text
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z32__device_stub__Z9addVectorPfS_S_PfS_S_
.type _Z32__device_stub__Z9addVectorPfS_S_PfS_S_, @function
_Z32__device_stub__Z9addVectorPfS_S_PfS_S_:
.LFB2082:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9addVectorPfS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z32__device_stub__Z9addVectorPfS_S_PfS_S_, .-_Z32__device_stub__Z9addVectorPfS_S_PfS_S_
.globl _Z9addVectorPfS_S_
.type _Z9addVectorPfS_S_, @function
_Z9addVectorPfS_S_:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z9addVectorPfS_S_PfS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z9addVectorPfS_S_, .-_Z9addVectorPfS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "Element
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $72, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl $4194304, %edi
call _Znam@PLT
movq %rax, %r12
movl $4194304, %edi
call _Znam@PLT
movq %rax, %rbp
movq %r12, %rax
leaq 4194304(%r12), %rdx
movss .LC0(%rip), %xmm0
.L12:
movss %xmm0, (%rax)
addq $4, %rax
cmpq %rdx, %rax
jne .L12
leaq 8(%rsp), %rdi
movl $4194304, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $4194304, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $4194304, %edx
movq %r12, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $4194304, %edx
movq %rbp, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1024, 44(%rsp)
movl $1, 48(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L19
.L13:
leaq 24(%rsp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq 24(%rsp), %rdi
call cudaEventRecord@PLT
movq 24(%rsp), %rdi
call cudaEventSynchronize@PLT
movl $2, %ecx
movl $4194304, %edx
movq 16(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
movl $0, %ebx
leaq .LC1(%rip), %r13
.L14:
pxor %xmm0, %xmm0
cvtss2sd 0(%rbp,%rbx,4), %xmm0
movl %ebx, %edx
movq %r13, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq $1034, %rbx
jne .L14
movq 24(%rsp), %rdi
call cudaEventDestroy@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq %r12, %rdi
call _ZdaPv@PLT
movq %rbp, %rdi
call _ZdaPv@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L20
movl $0, %eax
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
movq 8(%rsp), %rdi
movq 16(%rsp), %rdx
movq %rdi, %rsi
call _Z32__device_stub__Z9addVectorPfS_S_PfS_S_
jmp .L13
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC2:
.string "_Z9addVectorPfS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z9addVectorPfS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC0:
.long 1101104415
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
```
|
```amdasm
.text
.file "test_6.hip"
.globl _Z24__device_stub__addVectorPfS_S_ # -- Begin function _Z24__device_stub__addVectorPfS_S_
.type _Z24__device_stub__addVectorPfS_S_,@function
_Z24__device_stub__addVectorPfS_S_: # @_Z24__device_stub__addVectorPfS_S_
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $112, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 40(%rsp), %rax
movq %rdi, (%rax)
leaq 32(%rsp), %rcx
movq %rsi, (%rcx)
leaq 24(%rsp), %rsi
movq %rdx, (%rsi)
leaq 80(%rsp), %rbx
movq %rax, (%rbx)
movq %rcx, 8(%rbx)
movq %rsi, 16(%rbx)
leaq 64(%rsp), %r14
leaq 48(%rsp), %r15
leaq 16(%rsp), %r12
leaq 8(%rsp), %r13
movq %r14, %rdi
movq %r15, %rsi
movq %r12, %rdx
movq %r13, %rcx
callq __hipPopCallConfiguration
movq (%r14), %rsi
movl 8(%r14), %edx
movq (%r15), %rcx
movl 8(%r15), %r8d
movl $_Z9addVectorPfS_S_, %edi
movq %rbx, %r9
pushq (%r13)
.cfi_adjust_cfa_offset 8
pushq (%r12)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $128, %rsp
.cfi_adjust_cfa_offset -128
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z24__device_stub__addVectorPfS_S_, .Lfunc_end0-_Z24__device_stub__addVectorPfS_S_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $24, %rsp
.cfi_def_cfa_offset 64
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $4194304, %edi # imm = 0x400000
callq _Znam
movq %rax, %rbx
movl $4194304, %edi # imm = 0x400000
callq _Znam
movq %rax, %r14
xorl %eax, %eax
.LBB1_1: # =>This Inner Loop Header: Depth=1
movl $1101104415, (%rbx,%rax,4) # imm = 0x41A1851F
incq %rax
cmpq $1048576, %rax # imm = 0x100000
jne .LBB1_1
# %bb.2:
leaq 8(%rsp), %r15
movl $4194304, %esi # imm = 0x400000
movq %r15, %rdi
callq hipMalloc
movq %rsp, %r12
movl $4194304, %esi # imm = 0x400000
movq %r12, %rdi
callq hipMalloc
movq (%r15), %rdi
movl $4194304, %edx # imm = 0x400000
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq (%r12), %rdi
movl $4194304, %edx # imm = 0x400000
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 1023(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq 8(%rsp), %rdi
movq (%rsp), %rdx
movq %rdi, %rsi
callq _Z24__device_stub__addVectorPfS_S_
.LBB1_4:
leaq 16(%rsp), %r12
movq %r12, %rdi
callq hipEventCreate
movq (%r12), %rdi
xorl %r15d, %r15d
xorl %esi, %esi
callq hipEventRecord
movq (%r12), %rdi
callq hipEventSynchronize
movq (%rsp), %rsi
movl $4194304, %edx # imm = 0x400000
movq %r14, %rdi
movl $2, %ecx
callq hipMemcpy
.LBB1_5: # =>This Inner Loop Header: Depth=1
xorps %xmm0, %xmm0
cvtss2sd (%r14,%r15,4), %xmm0
movl $.L.str, %edi
movl %r15d, %esi
movb $1, %al
callq printf
incq %r15
cmpq $1034, %r15 # imm = 0x40A
jne .LBB1_5
# %bb.6:
movq 16(%rsp), %rdi
callq hipEventDestroy
movq 8(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipFree
movq %rbx, %rdi
callq _ZdaPv
movq %r14, %rdi
callq _ZdaPv
xorl %eax, %eax
addq $24, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, %rdi
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9addVectorPfS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9addVectorPfS_S_,@object # @_Z9addVectorPfS_S_
.section .rodata,"a",@progbits
.globl _Z9addVectorPfS_S_
.p2align 3, 0x0
_Z9addVectorPfS_S_:
.quad _Z24__device_stub__addVectorPfS_S_
.size _Z9addVectorPfS_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Element #%i: %.1f\n"
.size .L.str, 19
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z9addVectorPfS_S_"
.size .L__unnamed_1, 19
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__addVectorPfS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9addVectorPfS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
```
| 3,201 | 3,416 |
544 |
Convert the following CUDA device assembly code to AMD device assembly:
```cudaasm
code for sm_80
Function : add
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
MOV R1, c[0x0][0x28] ;
S2R R6, SR_CTAID.X ;
S2R R3, SR_TID.X ;
IMAD R6, R6, c[0x0][0x0], R3 ;
ISETP.GE.AND P0, PT, R6, c[0x0][0x160], PT ;
@P0 EXIT ;
HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ;
ULDC.64 UR4, c[0x0][0x118] ;
IMAD.WIDE R4, R6, R7, c[0x0][0x170] ;
IMAD.WIDE R2, R6.reuse, R7.reuse, c[0x0][0x168] ;
LDG.E R4, [R4.64] ;
LDG.E R3, [R2.64] ;
IMAD.WIDE R6, R6, R7, c[0x0][0x178] ;
FADD R9, R4, R3 ;
STG.E [R6.64], R9 ;
EXIT ;
BRA 0x100;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
```
|
```amdasm
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected add ; -- Begin function add
.globl add
.p2align 8
.type add,@function
add: ; @add
; %bb.0:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
; %bb.1:
s_load_b128 s[4:7], s[0:1], 0x8
v_ashrrev_i32_e32 v2, 31, v1
s_load_b64 s[0:1], s[0:1], 0x18
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_f32_e32 v2, v2, v3
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel add
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size add, .Lfunc_end0-add
; -- End function
.section .AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 180
; NumSgprs: 18
; NumVgprs: 6
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 6
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object ; @__hip_cuid_
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0 ; 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: add
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: add.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
```
| 392 | 2,482 |
545 |
Convert the following CUDA host assembly code to AMD host assembly:
```cudaasm
.file "tmpxft_001508bd_00000000-6_JCudaVectorAddKernel.cudafe1.cpp"
.text
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z27__device_stub__Z3addiPfS_S_iPfS_S_
.type _Z27__device_stub__Z3addiPfS_S_iPfS_S_, @function
_Z27__device_stub__Z3addiPfS_S_iPfS_S_:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 28(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %rcx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq add(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z27__device_stub__Z3addiPfS_S_iPfS_S_, .-_Z27__device_stub__Z3addiPfS_S_iPfS_S_
.globl add
.type add, @function
add:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z27__device_stub__Z3addiPfS_S_iPfS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size add, .-add
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "add"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq add(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
```
|
```amdasm
.text
.file "JCudaVectorAddKernel.hip"
.globl __device_stub__add # -- Begin function __device_stub__add
.type __device_stub__add,@function
__device_stub__add: # @__device_stub__add
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $112, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 4(%rsp), %rax
movl %edi, (%rax)
leaq 40(%rsp), %rdi
movq %rsi, (%rdi)
leaq 32(%rsp), %rsi
movq %rdx, (%rsi)
leaq 24(%rsp), %rdx
movq %rcx, (%rdx)
leaq 80(%rsp), %rbx
movq %rax, (%rbx)
movq %rdi, 8(%rbx)
movq %rsi, 16(%rbx)
movq %rdx, 24(%rbx)
leaq 64(%rsp), %r14
leaq 48(%rsp), %r15
leaq 16(%rsp), %r12
leaq 8(%rsp), %r13
movq %r14, %rdi
movq %r15, %rsi
movq %r12, %rdx
movq %r13, %rcx
callq __hipPopCallConfiguration
movq (%r14), %rsi
movl 8(%r14), %edx
movq (%r15), %rcx
movl 8(%r15), %r8d
movl $add, %edi
movq %rbx, %r9
pushq (%r13)
.cfi_adjust_cfa_offset 8
pushq (%r12)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $128, %rsp
.cfi_adjust_cfa_offset -128
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size __device_stub__add, .Lfunc_end0-__device_stub__add
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, %rdi
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $add, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type add,@object # @add
.section .rodata,"a",@progbits
.globl add
.p2align 3, 0x0
add:
.quad __device_stub__add
.size add, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "add"
.size .L__unnamed_1, 4
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __device_stub__add
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym add
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
```
| 1,815 | 1,918 |
550 |
Convert the following CUDA device assembly code to AMD device assembly:
```cudaasm
code for sm_80
Function : _Z13el_stress_adjPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_iifffii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
MOV R1, c[0x0][0x28] ;
S2R R2, SR_CTAID.X ;
MOV R10, c[0x0][0x258] ;
ULDC UR4, c[0x0][0x25c] ;
S2R R3, SR_TID.X ;
IADD3 R0, R10, -0x3, RZ ;
UIADD3 UR4, UR4, -0x3, URZ ;
S2R R4, SR_CTAID.Y ;
S2R R5, SR_TID.Y ;
IMAD R2, R2, c[0x0][0x0], R3 ;
IADD3 R3, R0, -c[0x0][0x270], RZ ;
ISETP.GT.AND P0, PT, R2, R3, PT ;
IMAD R3, R4, c[0x0][0x4], R5 ;
ISETP.LT.OR P0, PT, R2, 0x2, P0 ;
ISETP.LT.OR P0, PT, R3, 0x2, P0 ;
ISETP.GT.OR P0, PT, R3, UR4, P0 ;
@P0 EXIT ;
IMAD R4, R3, c[0x0][0x258], R2 ;
HFMA2.MMA R8, -RZ, RZ, 0, 2.384185791015625e-07 ;
IADD3 R6, RZ, -c[0x0][0x258], RZ ;
ULDC.64 UR4, c[0x0][0x118] ;
IADD3 R5, R4, c[0x0][0x258], RZ ;
IADD3 R11, R5.reuse, c[0x0][0x258], RZ ;
IMAD.WIDE R14, R5, R8, c[0x0][0x190] ;
IMAD.WIDE R16, R6, 0x4, R14 ;
LDG.E R15, [R14.64] ;
IMAD.WIDE R18, R11, R8, c[0x0][0x190] ;
IMAD.WIDE R20, R6, 0x4, R16 ;
LDG.E R16, [R16.64] ;
LDG.E R19, [R18.64] ;
LDG.E R20, [R20.64] ;
IMAD.WIDE R12, R4, R8, c[0x0][0x1c8] ;
MUFU.RCP R22, c[0x0][0x268] ;
MOV R23, c[0x0][0x268] ;
IMAD.WIDE R8, R4, R8, c[0x0][0x1d0] ;
LDG.E R7, [R12.64] ;
BSSY B2, 0x370 ;
LDG.E R8, [R8.64] ;
IMAD R10, R10, -0x3, R11 ;
FFMA R17, R22, -R23, 1 ;
FFMA R22, R22, R17, R22 ;
FADD R15, -R16, R15 ;
FMUL R15, R15, 1.125 ;
FADD R0, -R20, R19 ;
FFMA R25, R0, 0.041666667908430099487, -R15 ;
FCHK P0, R25, c[0x0][0x268] ;
FFMA R0, R25, R22, RZ ;
FFMA R9, R0, -c[0x0][0x268], R25 ;
FFMA R9, R22, R9, R0 ;
@!P0 BRA 0x360 ;
MOV R27, c[0x0][0x268] ;
MOV R0, 0x350 ;
CALL.REL.NOINC 0x18d0 ;
MOV R9, R21 ;
BSYNC B2 ;
HFMA2.MMA R0, -RZ, RZ, 0, 2.384185791015625e-07 ;
IMAD.WIDE R14, R5, R0, c[0x0][0x160] ;
IMAD.WIDE R16, R4, R0.reuse, c[0x0][0x160] ;
LDG.E R15, [R14.64] ;
IMAD.WIDE R12, R11, R0, c[0x0][0x160] ;
IMAD.WIDE R10, R10, R0, c[0x0][0x160] ;
LDG.E R0, [R16.64] ;
LDG.E R13, [R12.64] ;
LDG.E R10, [R10.64] ;
MUFU.RCP R18, c[0x0][0x268] ;
MOV R21, c[0x0][0x268] ;
BSSY B2, 0x530 ;
FFMA R21, R18, -R21, 1 ;
FADD R0, -R0, R15 ;
FMUL R0, R0, 1.125 ;
FADD R19, -R10, R13 ;
FFMA R25, R19, 0.041666667908430099487, -R0 ;
FCHK P0, R25, c[0x0][0x268] ;
FFMA R0, R18, R21, R18 ;
FFMA R18, R0, R25, RZ ;
FFMA R11, R18, -c[0x0][0x268], R25 ;
FFMA R18, R0, R11, R18 ;
@!P0 BRA 0x520 ;
MOV R27, c[0x0][0x268] ;
MOV R0, 0x510 ;
CALL.REL.NOINC 0x18d0 ;
MOV R18, R21 ;
BSYNC B2 ;
HFMA2.MMA R11, -RZ, RZ, 0, 2.384185791015625e-07 ;
IMAD.WIDE R10, R4, R11, c[0x0][0x198] ;
LDG.E R0, [R10.64] ;
LDG.E R13, [R10.64+0x4] ;
LDG.E R12, [R10.64+-0x4] ;
LDG.E R15, [R10.64+0x8] ;
MUFU.RCP R14, c[0x0][0x264] ;
BSSY B2, 0x6d0 ;
FADD R0, -R0, R13 ;
MOV R13, c[0x0][0x264] ;
FMUL R0, R0, 1.125 ;
FFMA R13, R14, -R13, 1 ;
FADD R15, -R12, R15 ;
IADD3 R12, R4, 0x1, RZ ;
FFMA R14, R14, R13, R14 ;
FFMA R25, R15, 0.041666667908430099487, -R0 ;
FCHK P0, R25, c[0x0][0x264] ;
FFMA R0, R25, R14, RZ ;
FFMA R11, R0, -c[0x0][0x264], R25 ;
FFMA R10, R14, R11, R0 ;
@!P0 BRA 0x6c0 ;
MOV R27, c[0x0][0x264] ;
MOV R0, 0x6b0 ;
CALL.REL.NOINC 0x18d0 ;
MOV R10, R21 ;
BSYNC B2 ;
HFMA2.MMA R13, -RZ, RZ, 0, 2.384185791015625e-07 ;
IMAD.WIDE R14, R4, R13, c[0x0][0x168] ;
LDG.E R0, [R14.64] ;
LDG.E R11, [R14.64+0x4] ;
LDG.E R19, [R14.64+-0x4] ;
LDG.E R20, [R14.64+0x8] ;
MUFU.RCP R21, c[0x0][0x264] ;
MOV R22, c[0x0][0x264] ;
BSSY B2, 0x870 ;
IMAD.WIDE R12, R12, R13, c[0x0][0x168] ;
FFMA R22, R21, -R22, 1 ;
FFMA R22, R21, R22, R21 ;
FADD R0, -R0, R11 ;
FMUL R0, R0, 1.125 ;
FADD R19, -R19, R20 ;
FFMA R25, R19, 0.041666667908430099487, -R0 ;
FCHK P0, R25, c[0x0][0x264] ;
FFMA R0, R22, R25, RZ ;
FFMA R11, R0, -c[0x0][0x264], R25 ;
FFMA R11, R22, R11, R0 ;
@!P0 BRA 0x860 ;
MOV R27, c[0x0][0x264] ;
MOV R0, 0x850 ;
CALL.REL.NOINC 0x18d0 ;
MOV R11, R21 ;
BSYNC B2 ;
HFMA2.MMA R22, -RZ, RZ, 0, 2.384185791015625e-07 ;
IMAD.WIDE R20, R3, R22, c[0x0][0x240] ;
LDG.E R27, [R20.64] ;
IMAD.WIDE R22, R3, R22, c[0x0][0x248] ;
LDG.E R20, [R22.64] ;
BSSY B2, 0x9a0 ;
MUFU.RCP R0, R27 ;
FCHK P0, R18, R27 ;
FFMA R19, -R27, R0, 1 ;
FFMA R19, R0, R19, R0 ;
FFMA R0, R19, R18, RZ ;
FFMA R24, -R27, R0, R18 ;
FFMA R0, R19, R24, R0 ;
@!P0 BRA 0x990 ;
MOV R25, R18 ;
MOV R0, 0x980 ;
CALL.REL.NOINC 0x18d0 ;
MOV R0, R21 ;
BSYNC B2 ;
HFMA2.MMA R23, -RZ, RZ, 0, 2.384185791015625e-07 ;
IMAD.WIDE R18, R2, R23, c[0x0][0x228] ;
LDG.E R27, [R18.64] ;
IMAD.WIDE R18, R4, R23, c[0x0][0x1e8] ;
LDG.E R21, [R18.64] ;
IMAD.WIDE R22, R2, R23, c[0x0][0x230] ;
LDG.E R23, [R22.64] ;
BSSY B2, 0xb30 ;
MUFU.RCP R24, R27 ;
FCHK P0, R11, R27 ;
FMUL R0, R21, R0 ;
FFMA R25, -R27, R24, 1 ;
FMUL R0, R0, c[0x0][0x260] ;
FFMA R24, R24, R25, R24 ;
FFMA R0, R20, R9, R0 ;
FFMA R26, R24, R11, RZ ;
FFMA R10, R23, R10, R0 ;
FFMA R9, -R27, R26, R11 ;
FFMA R9, R24, R9, R26 ;
@!P0 BRA 0xb20 ;
MOV R25, R11 ;
MOV R0, 0xb10 ;
CALL.REL.NOINC 0x18d0 ;
MOV R9, R21 ;
BSYNC B2 ;
HFMA2.MMA R0, -RZ, RZ, 0, 2.384185791015625e-07 ;
IMAD.WIDE R30, R4, R0, c[0x0][0x1f0] ;
LDG.E R22, [R30.64] ;
IMAD.WIDE R20, R4, R0, c[0x0][0x180] ;
LDG.E R24, [R20.64] ;
FMUL R9, R22, R9 ;
FFMA R9, R9, c[0x0][0x260], R10 ;
IMAD.WIDE R10, R4, R0, c[0x0][0x1d8] ;
FADD R25, R9, R24 ;
STG.E [R20.64], R25 ;
LDG.E R24, [R10.64] ;
IMAD.WIDE R22, R3, R0, c[0x0][0x220] ;
LDG.E R9, [R22.64] ;
IMAD.WIDE R22, R4, R0, c[0x0][0x1b0] ;
FMUL R26, R25, R24 ;
LDG.E R24, [R22.64] ;
FMUL R26, R26, c[0x0][0x260] ;
FFMA R9, R24, R9, R26 ;
STG.E [R22.64], R9 ;
LDG.E R26, [R10.64] ;
LDG.E R27, [R20.64] ;
IMAD.WIDE R10, R2, R0, c[0x0][0x208] ;
IMAD.WIDE R20, R4.reuse, R0.reuse, c[0x0][0x1b8] ;
LDG.E R25, [R10.64] ;
LDG.E R24, [R20.64] ;
IMAD.WIDE R22, R4, R0, c[0x0][0x1a0] ;
IMAD.WIDE R10, R6, 0x4, R22 ;
FMUL R26, R26, R27 ;
FMUL R26, R26, c[0x0][0x260] ;
FFMA R25, R24, R25, R26 ;
STG.E [R20.64], R25 ;
LDG.E R9, [R22.64] ;
IMAD.WIDE R20, R6, 0x4, R10 ;
LDG.E R10, [R10.64] ;
IMAD.WIDE R22, R5, R0, c[0x0][0x1a0] ;
LDG.E R0, [R20.64] ;
LDG.E R27, [R22.64] ;
MUFU.RCP R24, c[0x0][0x268] ;
MOV R29, c[0x0][0x268] ;
BSSY B2, 0xeb0 ;
FFMA R29, R24, -R29, 1 ;
FFMA R24, R24, R29, R24 ;
FADD R9, -R10, R9 ;
FMUL R9, R9, 1.125 ;
FADD R0, -R0, R27 ;
FFMA R25, R0, 0.041666667908430099487, -R9 ;
FCHK P0, R25, c[0x0][0x268] ;
FFMA R0, R24, R25, RZ ;
FFMA R9, R0, -c[0x0][0x268], R25 ;
FFMA R9, R24, R9, R0 ;
@!P0 BRA 0xea0 ;
MOV R27, c[0x0][0x268] ;
MOV R0, 0xe90 ;
CALL.REL.NOINC 0x18d0 ;
MOV R9, R21 ;
BSYNC B2 ;
HFMA2.MMA R20, -RZ, RZ, 0, 2.384185791015625e-07 ;
IMAD.WIDE R12, R6.reuse, 0x4, R12 ;
LDG.E R15, [R14.64] ;
IMAD.WIDE R10, R6, 0x4, R12 ;
LDG.E R12, [R12.64+-0x4] ;
IMAD.WIDE R20, R5, R20, c[0x0][0x168] ;
LDG.E R10, [R10.64+-0x4] ;
LDG.E R21, [R20.64] ;
MUFU.RCP R6, c[0x0][0x268] ;
MOV R23, c[0x0][0x268] ;
BSSY B2, 0x1060 ;
FFMA R23, R6, -R23, 1 ;
FADD R0, -R12, R15 ;
FMUL R0, R0, 1.125 ;
FADD R5, -R10, R21 ;
FFMA R25, R5, 0.041666667908430099487, -R0 ;
FCHK P0, R25, c[0x0][0x268] ;
FFMA R0, R6, R23, R6 ;
FFMA R6, R0, R25, RZ ;
FFMA R5, R6, -c[0x0][0x268], R25 ;
FFMA R6, R0, R5, R6 ;
@!P0 BRA 0x1050 ;
MOV R27, c[0x0][0x268] ;
MOV R0, 0x1040 ;
CALL.REL.NOINC 0x18d0 ;
MOV R6, R21 ;
BSYNC B2 ;
HFMA2.MMA R11, -RZ, RZ, 0, 2.384185791015625e-07 ;
IMAD.WIDE R10, R4, R11, c[0x0][0x188] ;
LDG.E R0, [R10.64+-0x4] ;
LDG.E R5, [R10.64] ;
LDG.E R12, [R10.64+-0x8] ;
LDG.E R13, [R10.64+0x4] ;
MUFU.RCP R14, c[0x0][0x264] ;
BSSY B2, 0x11f0 ;
FADD R0, -R0, R5 ;
MOV R5, c[0x0][0x264] ;
FMUL R0, R0, 1.125 ;
FFMA R5, R14, -R5, 1 ;
FADD R13, -R12, R13 ;
FFMA R14, R14, R5, R14 ;
FFMA R25, R13, 0.041666667908430099487, -R0 ;
FCHK P0, R25, c[0x0][0x264] ;
FFMA R0, R14, R25, RZ ;
FFMA R5, R0, -c[0x0][0x264], R25 ;
FFMA R5, R14, R5, R0 ;
@!P0 BRA 0x11e0 ;
MOV R27, c[0x0][0x264] ;
MOV R0, 0x11d0 ;
CALL.REL.NOINC 0x18d0 ;
MOV R5, R21 ;
BSYNC B2 ;
LDG.E R0, [R16.64+-0x4] ;
LDG.E R11, [R16.64] ;
LDG.E R10, [R16.64+-0x8] ;
LDG.E R13, [R16.64+0x4] ;
MUFU.RCP R12, c[0x0][0x264] ;
BSSY B2, 0x1360 ;
FADD R0, -R0, R11 ;
MOV R11, c[0x0][0x264] ;
FMUL R0, R0, 1.125 ;
FFMA R11, R12, -R11, 1 ;
FADD R13, -R10, R13 ;
FFMA R12, R12, R11, R12 ;
FFMA R25, R13, 0.041666667908430099487, -R0 ;
FCHK P0, R25, c[0x0][0x264] ;
FFMA R10, R12, R25, RZ ;
FFMA R11, R10, -c[0x0][0x264], R25 ;
FFMA R10, R12, R11, R10 ;
@!P0 BRA 0x1350 ;
MOV R27, c[0x0][0x264] ;
MOV R0, 0x1340 ;
CALL.REL.NOINC 0x18d0 ;
MOV R10, R21 ;
BSYNC B2 ;
HFMA2.MMA R12, -RZ, RZ, 0, 2.384185791015625e-07 ;
LDG.E R31, [R30.64] ;
IMAD.WIDE R14, R3, R12, c[0x0][0x210] ;
LDG.E R27, [R14.64] ;
IMAD.WIDE R12, R3, R12, c[0x0][0x218] ;
LDG.E R11, [R12.64] ;
BSSY B2, 0x1490 ;
FMUL R25, R31, R6 ;
MUFU.RCP R0, R27 ;
FCHK P0, R25, R27 ;
FFMA R17, -R27, R0, 1 ;
FFMA R17, R0, R17, R0 ;
FFMA R0, R25, R17, RZ ;
FFMA R6, -R27, R0, R25 ;
FFMA R21, R17, R6, R0 ;
@!P0 BRA 0x1480 ;
MOV R0, 0x1480 ;
CALL.REL.NOINC 0x18d0 ;
BSYNC B2 ;
MOV R23, 0x4 ;
IMAD.WIDE R12, R4, R23, c[0x0][0x178] ;
LDG.E R15, [R12.64] ;
FMUL R0, R21, c[0x0][0x260] ;
IMAD.WIDE R16, R2, R23, c[0x0][0x1f8] ;
FFMA R0, R11, R9, R0 ;
FADD R9, R0, R15 ;
STG.E [R12.64], R9 ;
LDG.E R27, [R16.64] ;
LDG.E R19, [R18.64] ;
IMAD.WIDE R14, R2, R23, c[0x0][0x200] ;
LDG.E R6, [R14.64] ;
BSSY B2, 0x1620 ;
MUFU.RCP R0, R27 ;
FMUL R25, R19, R10 ;
FCHK P0, R25, R27 ;
FFMA R11, -R27, R0, 1 ;
FFMA R11, R0, R11, R0 ;
FFMA R0, R25, R11, RZ ;
FFMA R9, -R27, R0, R25 ;
FFMA R21, R11, R9, R0 ;
@!P0 BRA 0x1610 ;
MOV R0, 0x1610 ;
CALL.REL.NOINC 0x18d0 ;
BSYNC B2 ;
HFMA2.MMA R9, -RZ, RZ, 0, 2.384185791015625e-07 ;
IMAD.WIDE R10, R4, R9, c[0x0][0x170] ;
LDG.E R0, [R10.64] ;
FMUL R21, R21, c[0x0][0x260] ;
IMAD.WIDE R24, R3, R9, c[0x0][0x250] ;
FFMA R5, R6, R5, R21 ;
IMAD.WIDE R14, R4, R9, c[0x0][0x1c0] ;
FADD R0, R5, R0 ;
STG.E [R10.64], R0 ;
LDG.E R6, [R12.64] ;
LDG.E R24, [R24.64] ;
LDG.E R3, [R14.64] ;
FMUL R5, R7, R0 ;
F2F.F64.F32 R18, R8 ;
FMUL R5, R5, c[0x0][0x260] ;
F2F.F64.F32 R20, R7 ;
F2F.F64.F32 R16, c[0x0][0x260] ;
DFMA R18, R18, 2, R20 ;
F2F.F64.F32 R22, R6 ;
FFMA R26, R3, R24, R5 ;
IMAD.WIDE R2, R2, R9, c[0x0][0x238] ;
F2F.F64.F32 R26, R26 ;
IMAD.WIDE R4, R4, R9, c[0x0][0x1a8] ;
DMUL R22, R18, R22 ;
DFMA R22, R22, R16, R26 ;
F2F.F32.F64 R23, R22 ;
STG.E [R14.64], R23 ;
LDG.E R10, [R10.64] ;
LDG.E R3, [R2.64] ;
LDG.E R0, [R4.64] ;
LDG.E R12, [R12.64] ;
F2F.F64.F32 R8, R10 ;
FMUL R0, R0, R3 ;
FMUL R20, R7, R12 ;
F2F.F64.F32 R6, R0 ;
FMUL R20, R20, c[0x0][0x260] ;
DMUL R8, R18, R8 ;
F2F.F64.F32 R20, R20 ;
DFMA R6, R16, R8, R6 ;
DADD R6, R6, R20 ;
F2F.F32.F64 R7, R6 ;
STG.E [R4.64], R7 ;
EXIT ;
SHF.R.U32.HI R21, RZ, 0x17, R27 ;
BSSY B0, 0x1f10 ;
SHF.R.U32.HI R24, RZ, 0x17, R25 ;
LOP3.LUT R21, R21, 0xff, RZ, 0xc0, !PT ;
LOP3.LUT R24, R24, 0xff, RZ, 0xc0, !PT ;
IADD3 R23, R21, -0x1, RZ ;
IADD3 R26, R24, -0x1, RZ ;
ISETP.GT.U32.AND P0, PT, R23, 0xfd, PT ;
ISETP.GT.U32.OR P0, PT, R26, 0xfd, P0 ;
@!P0 MOV R22, RZ ;
@!P0 BRA 0x1af0 ;
FSETP.GTU.FTZ.AND P0, PT, |R25|, +INF , PT ;
FSETP.GTU.FTZ.AND P1, PT, |R27|, +INF , PT ;
PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ;
@P0 BRA 0x1ef0 ;
LOP3.LUT P0, RZ, R27, 0x7fffffff, R25, 0xc8, !PT ;
@!P0 BRA 0x1ed0 ;
FSETP.NEU.FTZ.AND P2, PT, |R25|, +INF , PT ;
FSETP.NEU.FTZ.AND P1, PT, |R27|, +INF , PT ;
FSETP.NEU.FTZ.AND P0, PT, |R25|, +INF , PT ;
@!P1 BRA !P2, 0x1ed0 ;
LOP3.LUT P2, RZ, R25, 0x7fffffff, RZ, 0xc0, !PT ;
PLOP3.LUT P1, PT, P1, P2, PT, 0x2a, 0x0 ;
@P1 BRA 0x1eb0 ;
LOP3.LUT P1, RZ, R27, 0x7fffffff, RZ, 0xc0, !PT ;
PLOP3.LUT P0, PT, P0, P1, PT, 0x2a, 0x0 ;
@P0 BRA 0x1e80 ;
ISETP.GE.AND P0, PT, R26, RZ, PT ;
ISETP.GE.AND P1, PT, R23, RZ, PT ;
@P0 MOV R22, RZ ;
@!P0 FFMA R25, R25, 1.84467440737095516160e+19, RZ ;
@!P0 MOV R22, 0xffffffc0 ;
@!P1 FFMA R27, R27, 1.84467440737095516160e+19, RZ ;
@!P1 IADD3 R22, R22, 0x40, RZ ;
LEA R23, R21, 0xc0800000, 0x17 ;
BSSY B1, 0x1e70 ;
IADD3 R24, R24, -0x7f, RZ ;
IADD3 R23, -R23, R27, RZ ;
IMAD R25, R24.reuse, -0x800000, R25 ;
MUFU.RCP R26, R23 ;
IADD3 R24, R24, 0x7f, -R21 ;
IADD3 R22, R24, R22, RZ ;
FADD.FTZ R23, -R23, -RZ ;
FFMA R27, R26, R23, 1 ;
FFMA R26, R26, R27, R26 ;
FFMA R27, R25, R26, RZ ;
FFMA R28, R23, R27, R25 ;
FFMA R28, R26, R28, R27 ;
FFMA R23, R23, R28, R25 ;
FFMA R25, R26, R23, R28 ;
SHF.R.U32.HI R21, RZ, 0x17, R25 ;
LOP3.LUT R21, R21, 0xff, RZ, 0xc0, !PT ;
IADD3 R21, R21, R22, RZ ;
IADD3 R24, R21, -0x1, RZ ;
ISETP.GE.U32.AND P0, PT, R24, 0xfe, PT ;
@!P0 BRA 0x1e50 ;
ISETP.GT.AND P0, PT, R21, 0xfe, PT ;
@P0 BRA 0x1e20 ;
ISETP.GE.AND P0, PT, R21, 0x1, PT ;
@P0 BRA 0x1e60 ;
ISETP.GE.AND P0, PT, R21, -0x18, PT ;
LOP3.LUT R25, R25, 0x80000000, RZ, 0xc0, !PT ;
@!P0 BRA 0x1e60 ;
FFMA.RZ R22, R26.reuse, R23.reuse, R28.reuse ;
ISETP.NE.AND P2, PT, R21.reuse, RZ, PT ;
FFMA.RP R24, R26.reuse, R23.reuse, R28.reuse ;
ISETP.NE.AND P1, PT, R21.reuse, RZ, PT ;
FFMA.RM R26, R26, R23, R28 ;
LOP3.LUT R22, R22, 0x7fffff, RZ, 0xc0, !PT ;
IADD3 R23, R21.reuse, 0x20, RZ ;
LOP3.LUT R22, R22, 0x800000, RZ, 0xfc, !PT ;
IADD3 R21, -R21, RZ, RZ ;
SHF.L.U32 R23, R22, R23, RZ ;
FSETP.NEU.FTZ.AND P0, PT, R24, R26, PT ;
SEL R21, R21, RZ, P2 ;
ISETP.NE.AND P1, PT, R23, RZ, P1 ;
SHF.R.U32.HI R23, RZ, R21, R22 ;
PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ;
SHF.R.U32.HI R22, RZ, 0x1, R23 ;
SEL R21, RZ, 0x1, !P0 ;
LOP3.LUT R21, R21, 0x1, R22, 0xf8, !PT ;
LOP3.LUT R21, R21, R23, RZ, 0xc0, !PT ;
IADD3 R21, R22, R21, RZ ;
LOP3.LUT R25, R21, R25, RZ, 0xfc, !PT ;
BRA 0x1e60 ;
LOP3.LUT R25, R25, 0x80000000, RZ, 0xc0, !PT ;
LOP3.LUT R25, R25, 0x7f800000, RZ, 0xfc, !PT ;
BRA 0x1e60 ;
LEA R25, R22, R25, 0x17 ;
BSYNC B1 ;
BRA 0x1f00 ;
LOP3.LUT R25, R27, 0x80000000, R25, 0x48, !PT ;
LOP3.LUT R25, R25, 0x7f800000, RZ, 0xfc, !PT ;
BRA 0x1f00 ;
LOP3.LUT R25, R27, 0x80000000, R25, 0x48, !PT ;
BRA 0x1f00 ;
MUFU.RSQ R25, -QNAN ;
BRA 0x1f00 ;
FADD.FTZ R25, R25, R27 ;
BSYNC B0 ;
HFMA2.MMA R23, -RZ, RZ, 0, 0 ;
MOV R22, R0 ;
MOV R21, R25 ;
RET.REL.NODEC R22 0x0 ;
BRA 0x1f50;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
```
|
```amdasm
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z13el_stress_adjPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_iifffii ; -- Begin function _Z13el_stress_adjPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_iifffii
.globl _Z13el_stress_adjPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_iifffii
.p2align 8
.type _Z13el_stress_adjPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_iifffii,@function
_Z13el_stress_adjPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_iifffii: ; @_Z13el_stress_adjPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_iifffii
; %bb.0:
s_load_b32 s2, s[0:1], 0x124
v_and_b32_e32 v1, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s2, 0xffff
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[8:9], null, s14, s3, v[1:2]
s_mov_b32 s3, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_lt_i32_e32 1, v8
s_cbranch_execz .LBB0_3
; %bb.1:
s_clause 0x1
s_load_b128 s[28:31], s[0:1], 0xf8
s_load_b32 s3, s[0:1], 0x110
v_bfe_u32 v0, v0, 10, 10
s_lshr_b32 s2, s2, 16
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[10:11], null, s15, s2, v[0:1]
s_waitcnt lgkmcnt(0)
s_sub_i32 s2, s28, s3
s_add_i32 s3, s29, -3
s_add_i32 s2, s2, -3
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_ge_i32_e32 vcc_lo, s2, v8
v_cmp_ge_i32_e64 s2, s3, v10
v_cmp_lt_i32_e64 s3, 1, v10
s_delay_alu instid0(VALU_DEP_2)
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
s_and_b32 s2, s2, s3
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 exec_lo, exec_lo, s2
s_cbranch_execz .LBB0_3
; %bb.2:
v_mad_u64_u32 v[6:7], null, v10, s28, v[8:9]
s_clause 0x1
s_load_b512 s[8:23], s[0:1], 0x0
s_load_b512 s[52:67], s[0:1], 0x40
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_add_nc_u32_e32 v2, s28, v6
v_ashrrev_i32_e32 v7, 31, v6
v_add_nc_u32_e32 v4, -1, v6
v_add_nc_u32_e32 v11, s28, v2
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_lshlrev_b64 v[0:1], 2, v[6:7]
v_ashrrev_i32_e32 v3, 31, v2
v_ashrrev_i32_e32 v5, 31, v4
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_ashrrev_i32_e32 v12, 31, v11
v_lshlrev_b64 v[17:18], 2, v[2:3]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s20, v0
s_delay_alu instid0(VALU_DEP_3)
v_mad_u64_u32 v[15:16], null, s28, -3, v[11:12]
v_add_co_ci_u32_e32 v3, vcc_lo, s21, v1, vcc_lo
v_add_co_u32 v13, vcc_lo, s8, v0
v_add_co_ci_u32_e32 v14, vcc_lo, s9, v1, vcc_lo
v_add_co_u32 v19, vcc_lo, s20, v17
v_add_co_ci_u32_e32 v20, vcc_lo, s21, v18, vcc_lo
v_ashrrev_i32_e32 v16, 31, v15
v_lshlrev_b64 v[11:12], 2, v[11:12]
v_add_co_u32 v21, vcc_lo, s8, v17
s_clause 0x1
global_load_b32 v7, v[19:20], off
global_load_b32 v35, v[2:3], off
v_lshlrev_b64 v[19:20], 2, v[15:16]
v_add_co_ci_u32_e32 v22, vcc_lo, s9, v18, vcc_lo
v_add_co_u32 v2, vcc_lo, s20, v11
v_add_co_ci_u32_e32 v3, vcc_lo, s21, v12, vcc_lo
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_4)
v_add_co_u32 v27, vcc_lo, s20, v19
v_lshlrev_b64 v[15:16], 2, v[4:5]
v_add_co_ci_u32_e32 v28, vcc_lo, s21, v20, vcc_lo
v_add_co_u32 v4, vcc_lo, s22, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s23, v1, vcc_lo
v_add_co_u32 v29, vcc_lo, s22, v15
v_add_co_ci_u32_e32 v30, vcc_lo, s23, v16, vcc_lo
v_add_co_u32 v31, vcc_lo, s10, v0
v_add_co_ci_u32_e32 v32, vcc_lo, s11, v1, vcc_lo
v_add_co_u32 v33, vcc_lo, s10, v15
v_add_co_ci_u32_e32 v34, vcc_lo, s11, v16, vcc_lo
s_clause 0x1
global_load_b32 v36, v[21:22], off
global_load_b32 v37, v[13:14], off
global_load_b96 v[21:23], v[4:5], off
global_load_b96 v[24:26], v[31:32], off
global_load_b32 v38, v[29:30], off
global_load_b32 v39, v[33:34], off
v_add_co_u32 v11, vcc_lo, s8, v11
v_add_co_ci_u32_e32 v12, vcc_lo, s9, v12, vcc_lo
v_add_co_u32 v4, vcc_lo, s8, v19
v_add_co_ci_u32_e32 v5, vcc_lo, s9, v20, vcc_lo
s_clause 0x1
global_load_b32 v40, v[2:3], off
global_load_b32 v41, v[27:28], off
s_clause 0x1
global_load_b32 v42, v[11:12], off
global_load_b32 v43, v[4:5], off
s_load_b256 s[20:27], s[0:1], 0xc8
v_mov_b32_e32 v11, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[10:11]
v_dual_mov_b32 v9, v11 :: v_dual_add_nc_u32 v10, -2, v10
v_lshlrev_b64 v[4:5], 2, v[8:9]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v11, vcc_lo, s26, v2
v_add_co_ci_u32_e32 v12, vcc_lo, s27, v3, vcc_lo
global_load_b32 v9, v[11:12], off
v_add_co_u32 v11, vcc_lo, s20, v4
v_add_co_ci_u32_e32 v12, vcc_lo, s21, v5, vcc_lo
global_load_b32 v44, v[11:12], off
s_clause 0x1
s_load_b512 s[36:51], s[0:1], 0x88
s_load_b128 s[4:7], s[0:1], 0xe8
s_waitcnt lgkmcnt(0)
v_add_co_u32 v11, vcc_lo, s36, v0
v_add_co_ci_u32_e32 v12, vcc_lo, s37, v1, vcc_lo
v_add_co_u32 v27, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v28, vcc_lo, s5, v3, vcc_lo
global_load_b32 v45, v[11:12], off
v_add_co_u32 v29, vcc_lo, s22, v4
v_add_co_ci_u32_e32 v30, vcc_lo, s23, v5, vcc_lo
v_add_co_u32 v33, vcc_lo, s38, v0
v_add_co_ci_u32_e32 v34, vcc_lo, s39, v1, vcc_lo
global_load_b32 v46, v[27:28], off
global_load_b32 v47, v[33:34], off
global_load_b32 v29, v[29:30], off
v_add_co_u32 v27, vcc_lo, s16, v0
v_add_co_ci_u32_e32 v28, vcc_lo, s17, v1, vcc_lo
s_load_b32 s5, s[0:1], 0x108
global_load_b32 v30, v[27:28], off
s_waitcnt vmcnt(17)
v_sub_f32_e32 v7, v7, v35
s_waitcnt vmcnt(13)
v_dual_sub_f32 v21, v22, v21 :: v_dual_sub_f32 v22, v25, v24
s_waitcnt vmcnt(12)
v_dual_sub_f32 v24, v36, v37 :: v_dual_sub_f32 v23, v23, v38
s_waitcnt vmcnt(11)
v_sub_f32_e32 v25, v26, v39
v_dual_mul_f32 v7, 0x3f900000, v7 :: v_dual_mul_f32 v22, 0x3f900000, v22
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_dual_mul_f32 v21, 0x3f900000, v21 :: v_dual_mul_f32 v24, 0x3f900000, v24
s_waitcnt vmcnt(7)
v_sub_f32_e32 v26, v42, v43
v_fma_f32 v21, 0x3d2aaaab, v23, -v21
v_sub_f32_e32 v23, v40, v41
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_div_scale_f32 v40, s2, v21, s31, v21
v_fma_f32 v7, 0x3d2aaaab, v23, -v7
v_fma_f32 v23, 0x3d2aaaab, v26, -v24
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_div_scale_f32 v26, null, s5, s5, v7
v_div_scale_f32 v35, null, s5, s5, v23
v_div_scale_f32 v49, vcc_lo, v7, s5, v7
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_rcp_f32_e32 v38, v26
v_rcp_f32_e32 v39, v35
v_div_scale_f32 v50, s3, v23, s5, v23
s_waitcnt_depctr 0xfff
v_fma_f32 v43, -v26, v38, 1.0
v_fma_f32 v48, -v35, v39, 1.0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_fmac_f32_e32 v38, v43, v38
v_fma_f32 v22, 0x3d2aaaab, v25, -v22
v_div_scale_f32 v25, null, s31, s31, v21
v_div_scale_f32 v24, null, s31, s31, v22
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_rcp_f32_e32 v36, v25
v_div_scale_f32 v43, s4, v22, s31, v22
v_rcp_f32_e32 v37, v24
s_waitcnt_depctr 0xfff
v_fma_f32 v41, -v25, v36, 1.0
v_fma_f32 v42, -v24, v37, 1.0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_fmac_f32_e32 v36, v41, v36
v_mul_f32_e32 v41, v49, v38
v_fmac_f32_e32 v37, v42, v37
v_fmac_f32_e32 v39, v48, v39
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_mul_f32_e32 v48, v40, v36
v_fma_f32 v51, -v26, v41, v49
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_mul_f32_e32 v52, v43, v37
v_mul_f32_e32 v42, v50, v39
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_fma_f32 v54, -v25, v48, v40
v_fmac_f32_e32 v41, v51, v38
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_fma_f32 v51, -v24, v52, v43
v_fma_f32 v53, -v35, v42, v50
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_fmac_f32_e32 v48, v54, v36
v_fma_f32 v26, -v26, v41, v49
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_fmac_f32_e32 v42, v53, v39
v_fmac_f32_e32 v52, v51, v37
v_div_fmas_f32 v26, v26, v38, v41
s_mov_b32 vcc_lo, s3
v_fma_f32 v25, -v25, v48, v40
v_fma_f32 v35, -v35, v42, v50
v_fma_f32 v24, -v24, v52, v43
v_div_fixup_f32 v7, v26, s5, v7
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_2)
v_div_fmas_f32 v35, v35, v39, v42
s_mov_b32 vcc_lo, s2
v_div_fmas_f32 v25, v25, v36, v48
s_mov_b32 vcc_lo, s4
v_div_fixup_f32 v23, v35, s5, v23
v_div_fmas_f32 v24, v24, v37, v52
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_div_fixup_f32 v21, v25, s31, v21
s_waitcnt vmcnt(6)
v_div_scale_f32 v35, null, v9, v9, v23
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_div_fixup_f32 v22, v24, s31, v22
v_div_scale_f32 v39, vcc_lo, v23, v9, v23
v_rcp_f32_e32 v36, v35
s_waitcnt vmcnt(5)
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_div_scale_f32 v24, null, v44, v44, v22
v_div_scale_f32 v42, s2, v22, v44, v22
v_rcp_f32_e32 v38, v24
s_waitcnt_depctr 0xfff
v_fma_f32 v37, -v35, v36, 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v36, v37, v36
v_fma_f32 v40, -v24, v38, 1.0
v_dual_mul_f32 v37, v39, v36 :: v_dual_fmac_f32 v38, v40, v38
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v41, -v35, v37, v39
v_fmac_f32_e32 v37, v41, v36
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v35, -v35, v37, v39
v_div_fmas_f32 v35, v35, v36, v37
s_mov_b32 vcc_lo, s2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_div_fixup_f32 v9, v35, v9, v23
s_waitcnt vmcnt(4)
v_dual_mul_f32 v40, v42, v38 :: v_dual_mul_f32 v9, v9, v45
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v39, -v24, v40, v42
v_dual_mul_f32 v9, s30, v9 :: v_dual_fmac_f32 v40, v39, v38
s_waitcnt vmcnt(3)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fmac_f32_e32 v9, v7, v46
v_fma_f32 v23, -v24, v40, v42
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fmac_f32_e32 v9, v21, v29
v_div_fmas_f32 v23, v23, v38, v40
v_add_co_u32 v21, vcc_lo, s62, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fixup_f32 v22, v23, v44, v22
v_mul_f32_e32 v7, v22, v47
v_add_co_ci_u32_e32 v22, vcc_lo, s63, v1, vcc_lo
v_add_co_u32 v23, vcc_lo, s64, v0
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)
v_fmac_f32_e32 v9, s30, v7
v_add_co_ci_u32_e32 v24, vcc_lo, s65, v1, vcc_lo
v_add_co_u32 v25, vcc_lo, s66, v0
s_waitcnt vmcnt(0)
v_add_f32_e32 v29, v30, v9
v_add_co_ci_u32_e32 v26, vcc_lo, s67, v1, vcc_lo
global_load_b32 v7, v[21:22], off
global_load_b32 v9, v[23:24], off
v_add_co_u32 v21, vcc_lo, s50, v2
global_store_b32 v[27:28], v29, off
global_load_b32 v30, v[25:26], off
v_add_co_ci_u32_e32 v22, vcc_lo, s51, v3, vcc_lo
v_add_co_u32 v23, vcc_lo, s56, v0
v_add_co_ci_u32_e32 v24, vcc_lo, s57, v1, vcc_lo
global_load_b32 v21, v[21:22], off
global_load_b32 v22, v[23:24], off
s_waitcnt vmcnt(2)
v_mul_f32_e32 v29, v29, v30
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mul_f32_e32 v29, s30, v29
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v29, v21, v22
v_add_co_u32 v21, vcc_lo, s44, v4
v_add_co_ci_u32_e32 v22, vcc_lo, s45, v5, vcc_lo
global_store_b32 v[23:24], v29, off
global_load_b32 v35, v[27:28], off
global_load_b32 v36, v[25:26], off
v_add_co_u32 v23, vcc_lo, s58, v0
v_add_co_ci_u32_e32 v24, vcc_lo, s59, v1, vcc_lo
global_load_b32 v37, v[21:22], off
global_load_b32 v38, v[23:24], off
v_mad_u64_u32 v[21:22], null, v10, s28, v[8:9]
v_add_co_u32 v25, vcc_lo, s52, v0
v_add_co_ci_u32_e32 v26, vcc_lo, s53, v1, vcc_lo
v_add_co_u32 v27, vcc_lo, s52, v17
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_ashrrev_i32_e32 v22, 31, v21
v_add_co_ci_u32_e32 v28, vcc_lo, s53, v18, vcc_lo
v_add_co_u32 v17, vcc_lo, s10, v17
v_lshlrev_b64 v[21:22], 2, v[21:22]
v_add_co_ci_u32_e32 v18, vcc_lo, s11, v18, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v29, vcc_lo, s52, v21
v_add_co_ci_u32_e32 v30, vcc_lo, s53, v22, vcc_lo
v_add_co_u32 v21, vcc_lo, s10, v21
v_add_co_ci_u32_e32 v22, vcc_lo, s11, v22, vcc_lo
s_waitcnt vmcnt(2)
v_mul_f32_e32 v8, v35, v36
v_add_co_u32 v35, vcc_lo, s52, v19
v_add_co_ci_u32_e32 v36, vcc_lo, s53, v20, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)
v_mul_f32_e32 v8, s30, v8
v_add_co_u32 v19, vcc_lo, s10, v19
v_add_co_ci_u32_e32 v20, vcc_lo, s11, v20, vcc_lo
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v8, v37, v38
global_store_b32 v[23:24], v8, off
s_clause 0x1
global_load_b32 v8, v[25:26], off
global_load_b32 v10, v[35:36], off
s_clause 0x1
global_load_b32 v25, v[31:32], off
global_load_b32 v26, v[19:20], off
s_clause 0x1
global_load_b32 v27, v[27:28], off
global_load_b32 v28, v[29:30], off
s_clause 0x1
global_load_b32 v29, v[17:18], off
global_load_b32 v30, v[21:22], off
v_add_co_u32 v19, vcc_lo, s18, v0
v_add_co_ci_u32_e32 v20, vcc_lo, s19, v1, vcc_lo
v_add_co_u32 v21, vcc_lo, s18, v15
v_add_co_ci_u32_e32 v22, vcc_lo, s19, v16, vcc_lo
s_waitcnt vmcnt(6)
v_sub_f32_e32 v8, v8, v10
s_waitcnt vmcnt(2)
v_dual_sub_f32 v10, v25, v26 :: v_dual_sub_f32 v25, v27, v28
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_mul_f32_e32 v8, 0x3f900000, v8
s_waitcnt vmcnt(0)
v_sub_f32_e32 v26, v29, v30
v_fma_f32 v8, 0x3d2aaaab, v25, -v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_scale_f32 v25, null, s5, s5, v8
v_rcp_f32_e32 v27, v25
s_waitcnt_depctr 0xfff
v_fma_f32 v29, -v25, v27, 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_dual_mul_f32 v10, 0x3f900000, v10 :: v_dual_fmac_f32 v27, v29, v27
v_add_nc_u32_e32 v17, -2, v6
v_ashrrev_i32_e32 v18, 31, v17
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[17:18], 2, v[17:18]
v_add_co_u32 v23, vcc_lo, s18, v17
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v24, vcc_lo, s19, v18, vcc_lo
v_add_co_u32 v15, vcc_lo, s8, v15
v_add_co_ci_u32_e32 v16, vcc_lo, s9, v16, vcc_lo
v_add_co_u32 v17, vcc_lo, s8, v17
v_add_co_ci_u32_e32 v18, vcc_lo, s9, v18, vcc_lo
s_clause 0x2
global_load_b64 v[19:20], v[19:20], off
global_load_b32 v6, v[21:22], off
global_load_b32 v21, v[23:24], off
s_clause 0x2
global_load_b64 v[13:14], v[13:14], off
global_load_b32 v22, v[15:16], off
global_load_b32 v23, v[17:18], off
global_load_b32 v24, v[33:34], off
v_add_co_u32 v15, vcc_lo, s46, v2
v_add_co_ci_u32_e32 v16, vcc_lo, s47, v3, vcc_lo
global_load_b32 v31, v[15:16], off
v_add_co_u32 v15, vcc_lo, s48, v2
v_add_co_ci_u32_e32 v16, vcc_lo, s49, v3, vcc_lo
v_add_co_u32 v17, vcc_lo, s14, v0
v_add_co_ci_u32_e32 v18, vcc_lo, s15, v1, vcc_lo
global_load_b32 v15, v[15:16], off
global_load_b32 v16, v[17:18], off
v_div_scale_f32 v32, vcc_lo, v8, s5, v8
s_waitcnt vmcnt(5)
v_sub_f32_e32 v13, v13, v22
v_dual_sub_f32 v6, v19, v6 :: v_dual_sub_f32 v19, v20, v21
v_fma_f32 v10, 0x3d2aaaab, v26, -v10
s_waitcnt vmcnt(4)
v_sub_f32_e32 v14, v14, v23
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_div_scale_f32 v26, null, s5, s5, v10
v_div_scale_f32 v29, s0, v10, s5, v10
v_rcp_f32_e32 v28, v26
s_waitcnt_depctr 0xfff
v_fma_f32 v30, -v26, v28, 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v28, v30, v28
v_mul_f32_e32 v30, v32, v27
v_fma_f32 v34, -v25, v30, v32
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_mul_f32 v33, v29, v28 :: v_dual_fmac_f32 v30, v34, v27
v_fma_f32 v35, -v26, v33, v29
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v20, -v25, v30, v32
v_fmac_f32_e32 v33, v35, v28
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_div_fmas_f32 v20, v20, v27, v30
v_fma_f32 v21, -v26, v33, v29
s_mov_b32 vcc_lo, s0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_div_fixup_f32 v8, v20, s5, v8
v_div_fmas_f32 v21, v21, v28, v33
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_div_fixup_f32 v10, v21, s5, v10
s_waitcnt vmcnt(3)
v_dual_mul_f32 v10, v10, v24 :: v_dual_mul_f32 v13, 0x3f900000, v13
v_mul_f32_e32 v6, 0x3f900000, v6
s_waitcnt vmcnt(2)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_div_scale_f32 v22, null, v31, v31, v10
v_fma_f32 v6, 0x3d2aaaab, v19, -v6
v_fma_f32 v19, 0x3d2aaaab, v14, -v13
v_div_scale_f32 v29, s1, v10, v31, v10
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_rcp_f32_e32 v24, v22
v_div_scale_f32 v13, null, s31, s31, v6
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_div_scale_f32 v14, null, s31, s31, v19
v_div_scale_f32 v26, vcc_lo, v6, s31, v6
v_rcp_f32_e32 v21, v13
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(TRANS32_DEP_3)
v_rcp_f32_e32 v23, v14
v_fma_f32 v28, -v22, v24, 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
v_fmac_f32_e32 v24, v28, v24
s_waitcnt_depctr 0xfff
v_fma_f32 v25, -v13, v21, 1.0
v_fma_f32 v27, -v14, v23, 1.0
v_fmac_f32_e32 v21, v25, v21
v_div_scale_f32 v25, s0, v19, s31, v19
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v23, v27, v23
v_dual_mul_f32 v27, v26, v21 :: v_dual_mul_f32 v28, v25, v23
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_fma_f32 v30, -v13, v27, v26
v_mul_f32_e32 v32, v29, v24
v_fma_f32 v33, -v14, v28, v25
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_fmac_f32_e32 v27, v30, v21
v_fma_f32 v30, -v22, v32, v29
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_fmac_f32_e32 v28, v33, v23
v_fma_f32 v13, -v13, v27, v26
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_fmac_f32_e32 v32, v30, v24
v_fma_f32 v14, -v14, v28, v25
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_div_fmas_f32 v21, v13, v21, v27
v_fma_f32 v13, -v22, v32, v29
s_mov_b32 vcc_lo, s0
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_div_fmas_f32 v22, v14, v23, v28
s_mov_b32 vcc_lo, s1
v_div_fixup_f32 v6, v21, s31, v6
v_div_fmas_f32 v13, v13, v24, v32
v_div_fixup_f32 v10, v13, v31, v10
v_add_co_u32 v13, vcc_lo, s40, v4
v_add_co_ci_u32_e32 v14, vcc_lo, s41, v5, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mul_f32_e32 v10, s30, v10
s_waitcnt vmcnt(1)
v_fmac_f32_e32 v10, v8, v15
v_div_fixup_f32 v15, v22, s31, v19
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_2)
v_add_f32_e32 v8, v16, v10
v_add_co_u32 v10, vcc_lo, s42, v4
global_store_b32 v[17:18], v8, off
global_load_b32 v8, v[11:12], off
global_load_b32 v14, v[13:14], off
v_add_co_ci_u32_e32 v11, vcc_lo, s43, v5, vcc_lo
v_add_co_u32 v12, vcc_lo, s12, v0
v_add_co_ci_u32_e32 v13, vcc_lo, s13, v1, vcc_lo
global_load_b32 v10, v[10:11], off
global_load_b32 v11, v[12:13], off
s_waitcnt vmcnt(3)
v_mul_f32_e32 v8, v15, v8
s_waitcnt vmcnt(2)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_div_scale_f32 v15, null, v14, v14, v8
v_div_scale_f32 v20, vcc_lo, v8, v14, v8
v_rcp_f32_e32 v16, v15
s_waitcnt_depctr 0xfff
v_fma_f32 v19, -v15, v16, 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v16, v19, v16
v_mul_f32_e32 v19, v20, v16
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v22, -v15, v19, v20
v_fmac_f32_e32 v19, v22, v16
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v15, -v15, v19, v20
v_div_fmas_f32 v15, v15, v16, v19
v_add_co_u32 v2, vcc_lo, s6, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fixup_f32 v8, v15, v14, v8
v_mul_f32_e32 v8, s30, v8
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_fmac_f32_e32 v8, v6, v10
v_add_co_u32 v10, vcc_lo, s60, v0
s_waitcnt vmcnt(0)
v_add_f32_e32 v6, v11, v8
v_add_co_ci_u32_e32 v11, vcc_lo, s61, v1, vcc_lo
v_cvt_f64_f32_e32 v[8:9], v9
v_add_co_u32 v4, vcc_lo, s24, v4
global_store_b32 v[12:13], v6, off
global_load_b32 v14, v[17:18], off
global_load_b32 v15, v[2:3], off
global_load_b32 v16, v[10:11], off
v_cvt_f64_f32_e32 v[2:3], v7
v_mul_f32_e32 v6, v7, v6
v_add_co_ci_u32_e32 v5, vcc_lo, s25, v5, vcc_lo
v_add_co_u32 v0, vcc_lo, s54, v0
s_delay_alu instid0(VALU_DEP_3)
v_mul_f32_e32 v6, s30, v6
v_add_co_ci_u32_e32 v1, vcc_lo, s55, v1, vcc_lo
v_fma_f64 v[2:3], v[8:9], 2.0, v[2:3]
s_waitcnt vmcnt(2)
v_cvt_f64_f32_e32 v[8:9], v14
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v6, v15, v16
v_cvt_f64_f32_e32 v[14:15], s30
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
v_cvt_f64_f32_e32 v[19:20], v6
v_mul_f64 v[8:9], v[2:3], v[8:9]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[8:9], v[8:9], v[14:15], v[19:20]
v_cvt_f32_f64_e32 v6, v[8:9]
global_store_b32 v[10:11], v6, off
global_load_b32 v6, v[12:13], off
global_load_b32 v8, v[4:5], off
global_load_b32 v9, v[0:1], off
global_load_b32 v10, v[17:18], off
s_waitcnt vmcnt(3)
v_cvt_f64_f32_e32 v[4:5], v6
s_waitcnt vmcnt(1)
v_mul_f32_e32 v6, v8, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cvt_f64_f32_e32 v[8:9], v6
v_mul_f64 v[2:3], v[2:3], v[4:5]
s_waitcnt vmcnt(0)
v_mul_f32_e32 v4, v7, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v4, s30, v4
v_cvt_f64_f32_e32 v[4:5], v4
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[2:3], v[2:3], v[14:15], v[8:9]
v_add_f64 v[2:3], v[2:3], v[4:5]
s_delay_alu instid0(VALU_DEP_1)
v_cvt_f32_f64_e32 v2, v[2:3]
global_store_b32 v[0:1], v2, off
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13el_stress_adjPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_iifffii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 536
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 55
.amdhsa_next_free_sgpr 68
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z13el_stress_adjPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_iifffii, .Lfunc_end0-_Z13el_stress_adjPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_iifffii
; -- End function
.section .AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 3300
; NumSgprs: 70
; NumVgprs: 55
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 8
; VGPRBlocks: 6
; NumSGPRsForWavesPerEU: 70
; NumVGPRsForWavesPerEU: 55
; Occupancy: 16
; WaveLimiterHint : 1
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object ; @__hip_cuid_
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0 ; 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 40
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 48
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 56
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 64
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 72
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 80
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 88
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 96
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 104
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 112
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 120
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 128
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 136
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 144
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 152
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 160
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 168
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 176
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 184
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 192
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 200
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 208
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 216
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 224
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 232
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 240
.size: 8
.value_kind: global_buffer
- .offset: 248
.size: 4
.value_kind: by_value
- .offset: 252
.size: 4
.value_kind: by_value
- .offset: 256
.size: 4
.value_kind: by_value
- .offset: 260
.size: 4
.value_kind: by_value
- .offset: 264
.size: 4
.value_kind: by_value
- .offset: 268
.size: 4
.value_kind: by_value
- .offset: 272
.size: 4
.value_kind: by_value
- .offset: 280
.size: 4
.value_kind: hidden_block_count_x
- .offset: 284
.size: 4
.value_kind: hidden_block_count_y
- .offset: 288
.size: 4
.value_kind: hidden_block_count_z
- .offset: 292
.size: 2
.value_kind: hidden_group_size_x
- .offset: 294
.size: 2
.value_kind: hidden_group_size_y
- .offset: 296
.size: 2
.value_kind: hidden_group_size_z
- .offset: 298
.size: 2
.value_kind: hidden_remainder_x
- .offset: 300
.size: 2
.value_kind: hidden_remainder_y
- .offset: 302
.size: 2
.value_kind: hidden_remainder_z
- .offset: 320
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 328
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 336
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 344
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 536
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13el_stress_adjPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_iifffii
.private_segment_fixed_size: 0
.sgpr_count: 70
.sgpr_spill_count: 0
.symbol: _Z13el_stress_adjPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_iifffii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 55
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
```
| 9,460 | 16,039 |
551 |
Convert the following CUDA host assembly code to AMD host assembly:
```cudaasm
.file "tmpxft_0003f1a6_00000000-6_el_stress_adj.cudafe1.cpp"
.text
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z100__device_stub__Z13el_stress_adjPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_iifffiiPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_iifffii
.type _Z100__device_stub__Z13el_stress_adjPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_iifffiiPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_iifffii, @function
_Z100__device_stub__Z13el_stress_adjPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_iifffiiPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_iifffii:
.LFB2051:
.cfi_startproc
endbr64
subq $664, %rsp
.cfi_def_cfa_offset 672
movq %rdi, 264(%rsp)
movq %rsi, 256(%rsp)
movq %rdx, 248(%rsp)
movq %rcx, 240(%rsp)
movq %r8, 232(%rsp)
movq %r9, 224(%rsp)
movss %xmm0, 20(%rsp)
movss %xmm1, 16(%rsp)
movss %xmm2, 12(%rsp)
movq 672(%rsp), %rax
movq %rax, 216(%rsp)
movq 680(%rsp), %rax
movq %rax, 208(%rsp)
movq 688(%rsp), %rax
movq %rax, 200(%rsp)
movq 696(%rsp), %rax
movq %rax, 192(%rsp)
movq 704(%rsp), %rax
movq %rax, 184(%rsp)
movq 712(%rsp), %rax
movq %rax, 176(%rsp)
movq 720(%rsp), %rax
movq %rax, 168(%rsp)
movq 728(%rsp), %rax
movq %rax, 160(%rsp)
movq 736(%rsp), %rax
movq %rax, 152(%rsp)
movq 744(%rsp), %rax
movq %rax, 144(%rsp)
movq 752(%rsp), %rax
movq %rax, 136(%rsp)
movq 760(%rsp), %rax
movq %rax, 128(%rsp)
movq 768(%rsp), %rax
movq %rax, 120(%rsp)
movq 776(%rsp), %rax
movq %rax, 112(%rsp)
movq 784(%rsp), %rax
movq %rax, 104(%rsp)
movq 792(%rsp), %rax
movq %rax, 96(%rsp)
movq 800(%rsp), %rax
movq %rax, 88(%rsp)
movq 808(%rsp), %rax
movq %rax, 80(%rsp)
movq 816(%rsp), %rax
movq %rax, 72(%rsp)
movq 824(%rsp), %rax
movq %rax, 64(%rsp)
movq 832(%rsp), %rax
movq %rax, 56(%rsp)
movq 840(%rsp), %rax
movq %rax, 48(%rsp)
movq 848(%rsp), %rax
movq %rax, 40(%rsp)
movq 856(%rsp), %rax
movq %rax, 32(%rsp)
movq 864(%rsp), %rax
movq %rax, 24(%rsp)
movq %fs:40, %rax
movq %rax, 648(%rsp)
xorl %eax, %eax
leaq 264(%rsp), %rax
movq %rax, 336(%rsp)
leaq 256(%rsp), %rax
movq %rax, 344(%rsp)
leaq 248(%rsp), %rax
movq %rax, 352(%rsp)
leaq 240(%rsp), %rax
movq %rax, 360(%rsp)
leaq 232(%rsp), %rax
movq %rax, 368(%rsp)
leaq 224(%rsp), %rax
movq %rax, 376(%rsp)
leaq 216(%rsp), %rax
movq %rax, 384(%rsp)
leaq 208(%rsp), %rax
movq %rax, 392(%rsp)
leaq 200(%rsp), %rax
movq %rax, 400(%rsp)
leaq 192(%rsp), %rax
movq %rax, 408(%rsp)
leaq 184(%rsp), %rax
movq %rax, 416(%rsp)
leaq 176(%rsp), %rax
movq %rax, 424(%rsp)
leaq 168(%rsp), %rax
movq %rax, 432(%rsp)
leaq 160(%rsp), %rax
movq %rax, 440(%rsp)
leaq 152(%rsp), %rax
movq %rax, 448(%rsp)
leaq 144(%rsp), %rax
movq %rax, 456(%rsp)
leaq 136(%rsp), %rax
movq %rax, 464(%rsp)
leaq 128(%rsp), %rax
movq %rax, 472(%rsp)
leaq 120(%rsp), %rax
movq %rax, 480(%rsp)
leaq 112(%rsp), %rax
movq %rax, 488(%rsp)
leaq 104(%rsp), %rax
movq %rax, 496(%rsp)
leaq 96(%rsp), %rax
movq %rax, 504(%rsp)
leaq 88(%rsp), %rax
movq %rax, 512(%rsp)
leaq 80(%rsp), %rax
movq %rax, 520(%rsp)
leaq 72(%rsp), %rax
movq %rax, 528(%rsp)
leaq 64(%rsp), %rax
movq %rax, 536(%rsp)
leaq 56(%rsp), %rax
movq %rax, 544(%rsp)
leaq 48(%rsp), %rax
movq %rax, 552(%rsp)
leaq 40(%rsp), %rax
movq %rax, 560(%rsp)
leaq 32(%rsp), %rax
movq %rax, 568(%rsp)
leaq 24(%rsp), %rax
movq %rax, 576(%rsp)
leaq 872(%rsp), %rax
movq %rax, 584(%rsp)
leaq 880(%rsp), %rax
movq %rax, 592(%rsp)
leaq 20(%rsp), %rax
movq %rax, 600(%rsp)
leaq 16(%rsp), %rax
movq %rax, 608(%rsp)
leaq 12(%rsp), %rax
movq %rax, 616(%rsp)
leaq 888(%rsp), %rax
movq %rax, 624(%rsp)
leaq 896(%rsp), %rax
movq %rax, 632(%rsp)
movl $1, 288(%rsp)
movl $1, 292(%rsp)
movl $1, 296(%rsp)
movl $1, 300(%rsp)
movl $1, 304(%rsp)
movl $1, 308(%rsp)
leaq 280(%rsp), %rcx
leaq 272(%rsp), %rdx
leaq 300(%rsp), %rsi
leaq 288(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 648(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $664, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 280(%rsp)
.cfi_def_cfa_offset 680
pushq 280(%rsp)
.cfi_def_cfa_offset 688
leaq 352(%rsp), %r9
movq 316(%rsp), %rcx
movl 324(%rsp), %r8d
movq 304(%rsp), %rsi
movl 312(%rsp), %edx
leaq _Z13el_stress_adjPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_iifffii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 672
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z100__device_stub__Z13el_stress_adjPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_iifffiiPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_iifffii, .-_Z100__device_stub__Z13el_stress_adjPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_iifffiiPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_iifffii
.globl _Z13el_stress_adjPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_iifffii
.type _Z13el_stress_adjPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_iifffii, @function
_Z13el_stress_adjPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_iifffii:
.LFB2052:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
movl 248(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
movl 248(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 40
movl 248(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 48
movl 248(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 56
pushq 248(%rsp)
.cfi_def_cfa_offset 64
pushq 248(%rsp)
.cfi_def_cfa_offset 72
pushq 248(%rsp)
.cfi_def_cfa_offset 80
pushq 248(%rsp)
.cfi_def_cfa_offset 88
pushq 248(%rsp)
.cfi_def_cfa_offset 96
pushq 248(%rsp)
.cfi_def_cfa_offset 104
pushq 248(%rsp)
.cfi_def_cfa_offset 112
pushq 248(%rsp)
.cfi_def_cfa_offset 120
pushq 248(%rsp)
.cfi_def_cfa_offset 128
pushq 248(%rsp)
.cfi_def_cfa_offset 136
pushq 248(%rsp)
.cfi_def_cfa_offset 144
pushq 248(%rsp)
.cfi_def_cfa_offset 152
pushq 248(%rsp)
.cfi_def_cfa_offset 160
pushq 248(%rsp)
.cfi_def_cfa_offset 168
pushq 248(%rsp)
.cfi_def_cfa_offset 176
pushq 248(%rsp)
.cfi_def_cfa_offset 184
pushq 248(%rsp)
.cfi_def_cfa_offset 192
pushq 248(%rsp)
.cfi_def_cfa_offset 200
pushq 248(%rsp)
.cfi_def_cfa_offset 208
pushq 248(%rsp)
.cfi_def_cfa_offset 216
pushq 248(%rsp)
.cfi_def_cfa_offset 224
pushq 248(%rsp)
.cfi_def_cfa_offset 232
pushq 248(%rsp)
.cfi_def_cfa_offset 240
pushq 248(%rsp)
.cfi_def_cfa_offset 248
pushq 248(%rsp)
.cfi_def_cfa_offset 256
call _Z100__device_stub__Z13el_stress_adjPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_iifffiiPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_iifffii
addq $248, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z13el_stress_adjPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_iifffii, .-_Z13el_stress_adjPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_iifffii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z13el_stress_adjPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_iifffii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z13el_stress_adjPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_iifffii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
```
|
```amdasm
.text
.file "el_stress_adj.hip"
.globl _Z28__device_stub__el_stress_adjPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_iifffii # -- Begin function _Z28__device_stub__el_stress_adjPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_iifffii
.type _Z28__device_stub__el_stress_adjPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_iifffii,@function
_Z28__device_stub__el_stress_adjPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_iifffii: # @_Z28__device_stub__el_stress_adjPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_iifffii
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $416, %rsp # imm = 0x1A0
.cfi_def_cfa_offset 464
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 72(%rsp), %r10
movq %rdi, (%r10)
leaq 64(%rsp), %rdi
movq %rsi, (%rdi)
leaq 56(%rsp), %rsi
movq %rdx, (%rsi)
leaq 48(%rsp), %r11
movq %rcx, (%r11)
leaq 40(%rsp), %r14
movq %r8, (%r14)
leaq 32(%rsp), %r8
movq %r9, (%r8)
leaq 12(%rsp), %rax
movss %xmm0, (%rax)
leaq 8(%rsp), %rcx
movss %xmm1, (%rcx)
leaq 4(%rsp), %rdx
movss %xmm2, (%rdx)
leaq 112(%rsp), %rbx
movq %r10, (%rbx)
movq %rdi, 8(%rbx)
movq %rsi, 16(%rbx)
movq %r11, 24(%rbx)
movq %r14, 32(%rbx)
movq %r8, 40(%rbx)
leaq 464(%rsp), %rsi
movq %rsi, 48(%rbx)
leaq 472(%rsp), %rsi
movq %rsi, 56(%rbx)
leaq 480(%rsp), %rsi
movq %rsi, 64(%rbx)
leaq 488(%rsp), %rsi
movq %rsi, 72(%rbx)
leaq 496(%rsp), %rsi
movq %rsi, 80(%rbx)
leaq 504(%rsp), %rsi
movq %rsi, 88(%rbx)
leaq 512(%rsp), %rsi
movq %rsi, 96(%rbx)
leaq 520(%rsp), %rsi
movq %rsi, 104(%rbx)
leaq 528(%rsp), %rsi
movq %rsi, 112(%rbx)
leaq 536(%rsp), %rsi
movq %rsi, 120(%rbx)
leaq 544(%rsp), %rsi
movq %rsi, 128(%rbx)
leaq 552(%rsp), %rsi
movq %rsi, 136(%rbx)
leaq 560(%rsp), %rsi
movq %rsi, 144(%rbx)
leaq 568(%rsp), %rsi
movq %rsi, 152(%rbx)
leaq 576(%rsp), %rsi
movq %rsi, 160(%rbx)
leaq 584(%rsp), %rsi
movq %rsi, 168(%rbx)
leaq 592(%rsp), %rsi
movq %rsi, 176(%rbx)
leaq 600(%rsp), %rsi
movq %rsi, 184(%rbx)
leaq 608(%rsp), %rsi
movq %rsi, 192(%rbx)
leaq 616(%rsp), %rsi
movq %rsi, 200(%rbx)
leaq 624(%rsp), %rsi
movq %rsi, 208(%rbx)
leaq 632(%rsp), %rsi
movq %rsi, 216(%rbx)
leaq 640(%rsp), %rsi
movq %rsi, 224(%rbx)
leaq 648(%rsp), %rsi
movq %rsi, 232(%rbx)
leaq 656(%rsp), %rsi
movq %rsi, 240(%rbx)
leaq 664(%rsp), %rsi
movq %rsi, 248(%rbx)
leaq 672(%rsp), %rsi
movq %rsi, 256(%rbx)
movq %rax, 264(%rbx)
movq %rcx, 272(%rbx)
movq %rdx, 280(%rbx)
leaq 680(%rsp), %rax
movq %rax, 288(%rbx)
leaq 688(%rsp), %rax
movq %rax, 296(%rbx)
leaq 96(%rsp), %r14
leaq 80(%rsp), %r15
leaq 24(%rsp), %r12
leaq 16(%rsp), %r13
movq %r14, %rdi
movq %r15, %rsi
movq %r12, %rdx
movq %r13, %rcx
callq __hipPopCallConfiguration
movq (%r14), %rsi
movl 8(%r14), %edx
movq (%r15), %rcx
movl 8(%r15), %r8d
movl $_Z13el_stress_adjPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_iifffii, %edi
movq %rbx, %r9
pushq (%r13)
.cfi_adjust_cfa_offset 8
pushq (%r12)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $432, %rsp # imm = 0x1B0
.cfi_adjust_cfa_offset -432
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z28__device_stub__el_stress_adjPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_iifffii, .Lfunc_end0-_Z28__device_stub__el_stress_adjPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_iifffii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, %rdi
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13el_stress_adjPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_iifffii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z13el_stress_adjPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_iifffii,@object # @_Z13el_stress_adjPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_iifffii
.section .rodata,"a",@progbits
.globl _Z13el_stress_adjPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_iifffii
.p2align 3, 0x0
_Z13el_stress_adjPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_iifffii:
.quad _Z28__device_stub__el_stress_adjPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_iifffii
.size _Z13el_stress_adjPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_iifffii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z13el_stress_adjPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_iifffii"
.size .L__unnamed_1, 87
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z28__device_stub__el_stress_adjPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_iifffii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z13el_stress_adjPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_iifffii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
```
| 4,787 | 3,731 |
560 |
Convert the following CUDA device assembly code to AMD device assembly:
```cudaasm
code for sm_80
Function : _Z2k1PfS_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
MOV R1, c[0x0][0x28] ;
S2R R3, SR_CTAID.X ;
ULDC UR4, c[0x0][0x174] ;
UIADD3 UR4, UR4, -0x1, URZ ;
S2R R14, SR_TID.X ;
S2R R4, SR_CTAID.Y ;
S2R R17, SR_TID.Y ;
IMAD R3, R3, c[0x0][0x0], RZ ;
IADD3 R16, R14, 0x1, RZ ;
IADD3 R0, R3, R16, RZ ;
IMAD R17, R4, c[0x0][0x4], R17 ;
ISETP.GE.U32.AND P0, PT, R0, UR4, PT ;
IADD3 R17, R17, 0x1, RZ ;
ISETP.GE.U32.OR P0, PT, R17, UR4, P0 ;
ISETP.EQ.OR P0, PT, R17, RZ, P0 ;
ISETP.EQ.OR P0, PT, R0, RZ, P0 ;
@P0 EXIT ;
IADD3 R2, -R3.reuse, -0x3, RZ ;
ULDC UR5, c[0x0][0x0] ;
IADD3 R6, R3, 0x1, R4 ;
UIADD3 UR6, UR5, -0x1, URZ ;
IADD3 R5, R2, c[0x0][0x174], RZ ;
IMAD R2, R4.reuse, c[0x0][0x170], R3.reuse ;
ISETP.NE.AND P1, PT, R4, RZ, PT ;
HFMA2.MMA R15, -RZ, RZ, 0, 2.384185791015625e-07 ;
ISETP.NE.AND P0, PT, R14, R5, PT ;
IMAD R3, R2, c[0x0][0x170], R3 ;
ISETP.GE.AND P2, PT, R6, UR4, PT ;
ISETP.EQ.OR P0, PT, R14, UR6, !P0 ;
ULDC.64 UR6, c[0x0][0x118] ;
IADD3 R4, R16, R3, RZ ;
@!P1 IADD3 R22, R3, R14, RZ ;
@!P2 IMAD.WIDE R18, R4.reuse, R15.reuse, c[0x0][0x160] ;
@P0 IADD3 R6, R4, 0x1, RZ ;
@!P1 IMAD.WIDE R22, R22, R15, c[0x0][0x160] ;
@!P2 IMAD.WIDE R20, R15, c[0x0][0x170], R18 ;
@!P2 LDG.E R19, [R18.64] ;
@P0 IMAD.WIDE R6, R6, R15, c[0x0][0x160] ;
@!P1 IMAD.WIDE R2, R15, c[0x0][0x170], R22 ;
@!P1 LDG.E R23, [R22.64] ;
@P0 IMAD.WIDE R4, R4, R15, c[0x0][0x160] ;
@!P2 IMAD.WIDE R8, R15.reuse, c[0x0][0x170], R20 ;
@!P2 LDG.E R21, [R20.64] ;
@P0 IMAD.WIDE R6, R15.reuse, c[0x0][0x170], R6 ;
@!P2 LDG.E R8, [R8.64] ;
@!P1 IMAD.WIDE R10, R15.reuse, c[0x0][0x170], R2 ;
@!P1 LDG.E R2, [R2.64] ;
@P0 IMAD.WIDE R12, R15, c[0x0][0x170], R4 ;
@!P1 LDG.E R10, [R10.64] ;
@P0 IMAD.WIDE R6, R15, c[0x0][0x170], R6 ;
@P0 LDG.E R5, [R4.64+0x4] ;
@P0 LDG.E R12, [R12.64+0x4] ;
@P0 LDG.E R7, [R6.64] ;
IADD3 R25, R14.reuse, c[0x0][0x0], RZ ;
USHF.L.U32 UR5, UR5, 0x2, URZ ;
SHF.L.U32 R18, R14, 0x2, RZ ;
IMAD.MOV.U32 R20, RZ, RZ, c[0x0][0x0] ;
@!P1 SHF.L.U32 R9, R25, 0x2, RZ ;
MOV R27, c[0x0][0x0] ;
@P0 IADD3 R18, R18, 0x8, RZ ;
@!P2 LEA R3, R16, UR5, 0x2 ;
@!P1 IMAD R9, R20, 0x4, R9 ;
@P0 LEA R11, R27, R18, 0x2 ;
MOV R4, c[0x0][0x0] ;
@P0 LEA R4, R4, R11, 0x2 ;
IADD3 R18, R25, c[0x0][0x0], RZ ;
IMAD R0, R17, c[0x0][0x174], R0 ;
@!P2 STS [R14.X4+0x4], R19 ;
@!P2 STS [R14.X4+UR5+0xc], R21 ;
@!P2 STS [R3+UR5+0x10], R8 ;
@!P1 STS [R14.X4], R23 ;
@!P1 STS [R25.X4+0x8], R2 ;
@!P1 STS [R9+0x10], R10 ;
@P0 STS [R14.X4+0x8], R5 ;
@P0 STS [R11+0x8], R12 ;
@P0 STS [R4+0x10], R7 ;
BAR.SYNC.DEFER_BLOCKING 0x0 ;
LDS R13, [R14.X4] ;
LDS R6, [R25.X4+0xc] ;
LDS R3, [R14.X4+0x8] ;
LDS R8, [R14.X4+0x4] ;
LDS R16, [R25.X4+0x10] ;
LDS R2, [R25.X4+0x8] ;
LDS R5, [R18.X4+0x14] ;
LDS R9, [R18.X4+0x10] ;
LDS R7, [R18.X4+0x18] ;
FMUL R13, R13, 0.10000000149011611938 ;
FFMA R6, R6, 0.20000000298023223877, R13 ;
FFMA R3, R3, 0.10000000149011611938, R6 ;
FFMA R3, R8, 0.10000000149011611938, R3 ;
FFMA R3, R16, 0.10000000149011611938, R3 ;
FFMA R2, R2, 0.10000000149011611938, R3 ;
FFMA R2, R5, 0.10000000149011611938, R2 ;
FFMA R2, R9, 0.10000000149011611938, R2 ;
FFMA R7, R7, 0.10000000149011611938, R2 ;
IMAD.WIDE.U32 R2, R0, R15, c[0x0][0x168] ;
FMUL R7, R7, 0.94999998807907104492 ;
STG.E [R2.64], R7 ;
EXIT ;
BRA 0x630;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
```
|
```amdasm
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z2k1PfS_ii ; -- Begin function _Z2k1PfS_ii
.globl _Z2k1PfS_ii
.p2align 8
.type _Z2k1PfS_ii,@function
_Z2k1PfS_ii: ; @_Z2k1PfS_ii
; %bb.0:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b64 s[8:9], s[0:1], 0x10
v_bfe_u32 v1, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_lshr_b32 s3, s2, 16
s_add_i32 s12, s9, -1
s_mul_i32 s3, s15, s3
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add3_u32 v7, v1, s3, 1
s_mov_b32 s3, exec_lo
v_cmpx_gt_u32_e64 s12, v7
s_cbranch_execz .LBB0_11
; %bb.1:
v_and_b32_e32 v10, 0x3ff, v0
s_and_b32 s10, s2, 0xffff
v_cmp_ne_u32_e32 vcc_lo, 0, v7
s_mul_i32 s11, s14, s10
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v1, 1, v10
v_add_nc_u32_e32 v0, s11, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cmp_ne_u32_e64 s2, 0, v0
v_cmp_gt_u32_e64 s3, s12, v0
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
s_and_b32 s2, s2, s3
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 exec_lo, exec_lo, s2
s_cbranch_execz .LBB0_11
; %bb.2:
s_load_b128 s[4:7], s[0:1], 0x0
s_mul_i32 s0, s15, s8
s_add_i32 s3, s10, 2
s_add_i32 s0, s11, s0
v_add_nc_u32_e32 v11, s3, v10
s_add_i32 s1, s0, 1
s_mul_i32 s2, s0, s8
s_mul_i32 s1, s1, s8
s_add_i32 s2, s2, s11
s_add_i32 s1, s1, s11
v_add_nc_u32_e32 v5, s2, v1
s_add_i32 s0, s1, s8
v_add_nc_u32_e32 v3, s1, v1
v_add_nc_u32_e32 v1, s0, v1
v_add_nc_u32_e32 v12, s3, v11
s_add_i32 s8, s11, s15
v_ashrrev_i32_e32 v6, 31, v5
v_ashrrev_i32_e32 v4, 31, v3
v_ashrrev_i32_e32 v2, 31, v1
v_lshl_add_u32 v9, v10, 2, 0
v_lshl_add_u32 v8, v12, 2, 0
s_add_i32 s8, s8, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_ge_i32 s8, s12
s_cbranch_scc1 .LBB0_4
; %bb.3:
v_lshlrev_b64 v[13:14], 2, v[5:6]
v_lshlrev_b64 v[15:16], 2, v[3:4]
v_lshlrev_b64 v[17:18], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v13, vcc_lo, s4, v13
v_add_co_ci_u32_e32 v14, vcc_lo, s5, v14, vcc_lo
s_delay_alu instid0(VALU_DEP_4)
v_add_co_u32 v15, vcc_lo, s4, v15
v_add_co_ci_u32_e32 v16, vcc_lo, s5, v16, vcc_lo
v_add_co_u32 v17, vcc_lo, s4, v17
v_add_co_ci_u32_e32 v18, vcc_lo, s5, v18, vcc_lo
s_clause 0x2
global_load_b32 v13, v[13:14], off
global_load_b32 v14, v[15:16], off
global_load_b32 v15, v[17:18], off
v_add_nc_u32_e32 v16, 4, v9
s_delay_alu instid0(VALU_DEP_1)
v_lshl_add_u32 v16, s10, 2, v16
s_waitcnt vmcnt(2)
ds_store_b32 v9, v13 offset:4
s_waitcnt vmcnt(1)
ds_store_b32 v16, v14 offset:8
s_waitcnt vmcnt(0)
ds_store_b32 v8, v15 offset:4
.LBB0_4:
s_cmp_lg_u32 s15, 0
s_cbranch_scc1 .LBB0_6
; %bb.5:
v_add_nc_u32_e32 v13, s2, v10
v_add_nc_u32_e32 v15, s1, v10
v_add_nc_u32_e32 v17, s0, v10
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_ashrrev_i32_e32 v14, 31, v13
v_ashrrev_i32_e32 v16, 31, v15
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_ashrrev_i32_e32 v18, 31, v17
v_lshlrev_b64 v[13:14], 2, v[13:14]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[15:16], 2, v[15:16]
v_lshlrev_b64 v[17:18], 2, v[17:18]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v13, vcc_lo, s4, v13
v_add_co_ci_u32_e32 v14, vcc_lo, s5, v14, vcc_lo
s_delay_alu instid0(VALU_DEP_4)
v_add_co_u32 v15, vcc_lo, s4, v15
v_add_co_ci_u32_e32 v16, vcc_lo, s5, v16, vcc_lo
v_add_co_u32 v17, vcc_lo, s4, v17
v_add_co_ci_u32_e32 v18, vcc_lo, s5, v18, vcc_lo
s_clause 0x2
global_load_b32 v13, v[13:14], off
global_load_b32 v14, v[15:16], off
global_load_b32 v15, v[17:18], off
v_lshl_add_u32 v16, s10, 2, v9
s_waitcnt vmcnt(2)
ds_store_b32 v9, v13
s_waitcnt vmcnt(1)
ds_store_b32 v16, v14 offset:8
s_waitcnt vmcnt(0)
ds_store_b32 v8, v15
.LBB0_6:
s_sub_i32 s0, s9, s11
s_add_i32 s1, s10, -1
s_add_i32 s0, s0, -3
v_cmp_ne_u32_e32 vcc_lo, s1, v10
v_cmp_ne_u32_e64 s0, s0, v10
v_add_nc_u32_e32 v15, 2, v10
v_add_nc_u32_e32 v14, 2, v11
v_add_nc_u32_e32 v13, 2, v12
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s0, s0, vcc_lo
s_and_saveexec_b32 s1, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s0, exec_lo, s1
; %bb.7: ; %._crit_edge
v_add_nc_u32_e32 v15, 2, v10
v_add_nc_u32_e32 v14, 2, v11
v_add_nc_u32_e32 v13, 2, v12
; implicit-def: $vgpr5
; implicit-def: $vgpr3
; implicit-def: $vgpr1
; %bb.8: ; %Flow
s_and_not1_saveexec_b32 s0, s0
s_cbranch_execz .LBB0_10
; %bb.9:
v_lshlrev_b64 v[5:6], 2, v[5:6]
v_lshlrev_b64 v[3:4], 2, v[3:4]
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_lshl_b32 s1, s10, 2
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_3)
v_add_co_u32 v5, vcc_lo, s4, v5
v_add_co_ci_u32_e32 v6, vcc_lo, s5, v6, vcc_lo
v_add_co_u32 v3, vcc_lo, s4, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
v_add_co_u32 v1, vcc_lo, s4, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s5, v2, vcc_lo
s_clause 0x2
global_load_b32 v3, v[3:4], off offset:4
global_load_b32 v4, v[5:6], off offset:4
global_load_b32 v1, v[1:2], off offset:4
v_add3_u32 v2, v9, 8, s1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v5, 8, v2
v_add_nc_u32_e32 v5, s1, v5
s_waitcnt vmcnt(2)
ds_store_b32 v2, v3 offset:8
s_waitcnt vmcnt(1)
ds_store_b32 v9, v4 offset:8
s_waitcnt vmcnt(0)
ds_store_b32 v5, v1 offset:8
.LBB0_10:
s_or_b32 exec_lo, exec_lo, s0
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
ds_load_2addr_b32 v[1:2], v9 offset1:1
v_lshl_add_u32 v3, s10, 2, v9
v_lshl_add_u32 v5, v15, 2, 0
ds_load_2addr_b32 v[3:4], v3 offset0:2 offset1:3
ds_load_b32 v9, v5
v_lshl_add_u32 v10, v14, 2, 0
ds_load_2addr_b32 v[5:6], v8 offset1:1
v_lshl_add_u32 v8, v13, 2, 0
ds_load_b32 v10, v10
ds_load_b32 v8, v8
s_waitcnt lgkmcnt(5)
v_mul_f32_e32 v1, 0x3dcccccd, v1
s_waitcnt lgkmcnt(4)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_fmamk_f32 v4, v4, 0x3e4ccccd, v1
s_waitcnt lgkmcnt(3)
v_fmac_f32_e32 v4, 0x3dcccccd, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
v_fmac_f32_e32 v4, 0x3dcccccd, v2
v_mad_u64_u32 v[1:2], null, v7, s9, v[0:1]
v_mov_b32_e32 v2, 0
s_waitcnt lgkmcnt(1)
v_fmac_f32_e32 v4, 0x3dcccccd, v10
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[0:1], 2, v[1:2]
v_fmac_f32_e32 v4, 0x3dcccccd, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s6, v0
v_fmac_f32_e32 v4, 0x3dcccccd, v6
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
v_fmac_f32_e32 v4, 0x3dcccccd, v5
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v4, 0x3dcccccd, v8
v_mul_f32_e32 v2, 0x3f733333, v4
global_store_b32 v[0:1], v2, off
.LBB0_11:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z2k1PfS_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 19
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z2k1PfS_ii, .Lfunc_end0-_Z2k1PfS_ii
; -- End function
.section .AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1112
; NumSgprs: 18
; NumVgprs: 19
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 2
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 19
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object ; @__hip_cuid_
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0 ; 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
- .offset: 144
.size: 4
.value_kind: hidden_dynamic_lds_size
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z2k1PfS_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z2k1PfS_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 19
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
```
| 2,298 | 5,911 |
561 |
Convert the following CUDA host assembly code to AMD host assembly:
```cudaasm
.file "tmpxft_0010b144_00000000-6_k1.cudafe1.cpp"
.text
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z25__device_stub__Z2k1PfS_iiPfS_ii
.type _Z25__device_stub__Z2k1PfS_iiPfS_ii, @function
_Z25__device_stub__Z2k1PfS_iiPfS_ii:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z2k1PfS_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z25__device_stub__Z2k1PfS_iiPfS_ii, .-_Z25__device_stub__Z2k1PfS_iiPfS_ii
.globl _Z2k1PfS_ii
.type _Z2k1PfS_ii, @function
_Z2k1PfS_ii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z25__device_stub__Z2k1PfS_iiPfS_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z2k1PfS_ii, .-_Z2k1PfS_ii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z2k1PfS_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z2k1PfS_ii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
```
|
```amdasm
.text
.file "k1.hip"
.globl _Z17__device_stub__k1PfS_ii # -- Begin function _Z17__device_stub__k1PfS_ii
.type _Z17__device_stub__k1PfS_ii,@function
_Z17__device_stub__k1PfS_ii: # @_Z17__device_stub__k1PfS_ii
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $112, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 40(%rsp), %rax
movq %rdi, (%rax)
leaq 32(%rsp), %rdi
movq %rsi, (%rdi)
leaq 12(%rsp), %rsi
movl %edx, (%rsi)
leaq 8(%rsp), %rdx
movl %ecx, (%rdx)
leaq 80(%rsp), %rbx
movq %rax, (%rbx)
movq %rdi, 8(%rbx)
movq %rsi, 16(%rbx)
movq %rdx, 24(%rbx)
leaq 64(%rsp), %r14
leaq 48(%rsp), %r15
leaq 24(%rsp), %r12
leaq 16(%rsp), %r13
movq %r14, %rdi
movq %r15, %rsi
movq %r12, %rdx
movq %r13, %rcx
callq __hipPopCallConfiguration
movq (%r14), %rsi
movl 8(%r14), %edx
movq (%r15), %rcx
movl 8(%r15), %r8d
movl $_Z2k1PfS_ii, %edi
movq %rbx, %r9
pushq (%r13)
.cfi_adjust_cfa_offset 8
pushq (%r12)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $128, %rsp
.cfi_adjust_cfa_offset -128
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z17__device_stub__k1PfS_ii, .Lfunc_end0-_Z17__device_stub__k1PfS_ii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, %rdi
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z2k1PfS_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z2k1PfS_ii,@object # @_Z2k1PfS_ii
.section .rodata,"a",@progbits
.globl _Z2k1PfS_ii
.p2align 3, 0x0
_Z2k1PfS_ii:
.quad _Z17__device_stub__k1PfS_ii
.size _Z2k1PfS_ii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z2k1PfS_ii"
.size .L__unnamed_1, 12
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z17__device_stub__k1PfS_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z2k1PfS_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
```
| 1,891 | 2,074 |
566 |
Convert the following CUDA device assembly code to AMD device assembly:
```cudaasm
code for sm_80
Function : _Z4copyPfPKfi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
MOV R1, c[0x0][0x28] ;
S2R R0, SR_CTAID.X ;
S2R R3, SR_TID.X ;
IMAD R0, R0, c[0x0][0x0], R3 ;
ISETP.GE.AND P0, PT, R0, c[0x0][0x170], PT ;
@P0 EXIT ;
ULDC.64 UR4, c[0x0][0x118] ;
HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ;
IMAD R6, R0, 0x6, RZ ;
IMAD.WIDE R2, R6, R7, c[0x0][0x168] ;
LDG.E R9, [R2.64] ;
SHF.L.U32 R4, R0, 0x3, RZ ;
IMAD.WIDE R4, R4, R7, c[0x0][0x160] ;
STG.E [R4.64], R9 ;
LDG.E R11, [R2.64+0x4] ;
STG.E [R4.64+0x4], R11 ;
LDG.E R13, [R2.64+0x8] ;
IADD3 R6, R6, 0x4, RZ ;
STG.E [R4.64+0x8], R13 ;
LDG.E R15, [R2.64+0xc] ;
IMAD.WIDE R6, R6, R7, c[0x0][0x168] ;
STG.E [R4.64+0x10], R15 ;
LDG.E R17, [R6.64] ;
MOV R11, c[0x0][0x0] ;
STG.E [R4.64+0x14], R17 ;
LDG.E R9, [R6.64+0x4] ;
IMAD R0, R11, c[0x0][0xc], R0 ;
ISETP.GE.AND P0, PT, R0, c[0x0][0x170], PT ;
STG.E [R4.64+0x18], R9 ;
@!P0 BRA 0x70 ;
EXIT ;
BRA 0x1f0;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
```
|
```amdasm
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z4copyPfPKfi ; -- Begin function _Z4copyPfPKfi
.globl _Z4copyPfPKfi
.p2align 8
.type _Z4copyPfPKfi,@function
_Z4copyPfPKfi: ; @_Z4copyPfPKfi
; %bb.0:
s_clause 0x1
s_load_b32 s5, s[0:1], 0x24
s_load_b32 s4, s[0:1], 0x10
s_add_u32 s2, s0, 24
s_addc_u32 s3, s1, 0
s_mov_b32 s6, exec_lo
s_waitcnt lgkmcnt(0)
s_and_b32 s5, s5, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s5, v[0:1]
v_cmpx_gt_i32_e64 s4, v1
s_cbranch_execz .LBB0_3
; %bb.1: ; %.lr.ph
s_load_b32 s6, s[2:3], 0x0
s_load_b128 s[0:3], s[0:1], 0x0
v_mul_lo_u32 v2, v1, 6
v_lshlrev_b32_e32 v4, 3, v1
s_mov_b32 s8, 0
s_waitcnt lgkmcnt(0)
s_mul_i32 s5, s6, s5
s_delay_alu instid0(SALU_CYCLE_1)
s_mul_i32 s6, s5, 6
s_lshl_b32 s7, s5, 3
.LBB0_2: ; =>This Inner Loop Header: Depth=1
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v3, 31, v2
v_add_nc_u32_e32 v1, s5, v1
v_lshlrev_b64 v[5:6], 2, v[2:3]
v_add_nc_u32_e32 v2, s6, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v7, vcc_lo, s2, v5
v_add_co_ci_u32_e32 v8, vcc_lo, s3, v6, vcc_lo
v_ashrrev_i32_e32 v5, 31, v4
global_load_b32 v0, v[7:8], off
v_lshlrev_b64 v[5:6], 2, v[4:5]
v_add_nc_u32_e32 v4, s7, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v5, vcc_lo, s0, v5
v_add_co_ci_u32_e32 v6, vcc_lo, s1, v6, vcc_lo
v_cmp_le_i32_e32 vcc_lo, s4, v1
s_or_b32 s8, vcc_lo, s8
s_waitcnt vmcnt(0)
global_store_b32 v[5:6], v0, off
global_load_b32 v0, v[7:8], off offset:4
s_waitcnt vmcnt(0)
global_store_b32 v[5:6], v0, off offset:4
global_load_b32 v0, v[7:8], off offset:8
s_waitcnt vmcnt(0)
global_store_b32 v[5:6], v0, off offset:8
global_load_b32 v0, v[7:8], off offset:12
s_waitcnt vmcnt(0)
global_store_b32 v[5:6], v0, off offset:16
global_load_b32 v0, v[7:8], off offset:16
s_waitcnt vmcnt(0)
global_store_b32 v[5:6], v0, off offset:20
global_load_b32 v0, v[7:8], off offset:20
s_waitcnt vmcnt(0)
global_store_b32 v[5:6], v0, off offset:24
s_and_not1_b32 exec_lo, exec_lo, s8
s_cbranch_execnz .LBB0_2
.LBB0_3: ; %Flow38
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z4copyPfPKfi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z4copyPfPKfi, .Lfunc_end0-_Z4copyPfPKfi
; -- End function
.section .AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 340
; NumSgprs: 18
; NumVgprs: 9
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 9
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object ; @__hip_cuid_
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0 ; 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z4copyPfPKfi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z4copyPfPKfi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
```
| 666 | 3,050 |
567 |
Convert the following CUDA host assembly code to AMD host assembly:
```cudaasm
.file "tmpxft_0008b2c0_00000000-6_copy.cudafe1.cpp"
.text
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z27__device_stub__Z4copyPfPKfiPfPKfi
.type _Z27__device_stub__Z4copyPfPKfiPfPKfi, @function
_Z27__device_stub__Z4copyPfPKfiPfPKfi:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z4copyPfPKfi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z27__device_stub__Z4copyPfPKfiPfPKfi, .-_Z27__device_stub__Z4copyPfPKfiPfPKfi
.globl _Z4copyPfPKfi
.type _Z4copyPfPKfi, @function
_Z4copyPfPKfi:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z27__device_stub__Z4copyPfPKfiPfPKfi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z4copyPfPKfi, .-_Z4copyPfPKfi
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z4copyPfPKfi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z4copyPfPKfi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
```
|
```amdasm
.text
.file "copy.hip"
.globl _Z19__device_stub__copyPfPKfi # -- Begin function _Z19__device_stub__copyPfPKfi
.type _Z19__device_stub__copyPfPKfi,@function
_Z19__device_stub__copyPfPKfi: # @_Z19__device_stub__copyPfPKfi
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $112, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 40(%rsp), %rax
movq %rdi, (%rax)
leaq 32(%rsp), %rcx
movq %rsi, (%rcx)
leaq 12(%rsp), %rsi
movl %edx, (%rsi)
leaq 80(%rsp), %rbx
movq %rax, (%rbx)
movq %rcx, 8(%rbx)
movq %rsi, 16(%rbx)
leaq 64(%rsp), %r14
leaq 48(%rsp), %r15
leaq 24(%rsp), %r12
leaq 16(%rsp), %r13
movq %r14, %rdi
movq %r15, %rsi
movq %r12, %rdx
movq %r13, %rcx
callq __hipPopCallConfiguration
movq (%r14), %rsi
movl 8(%r14), %edx
movq (%r15), %rcx
movl 8(%r15), %r8d
movl $_Z4copyPfPKfi, %edi
movq %rbx, %r9
pushq (%r13)
.cfi_adjust_cfa_offset 8
pushq (%r12)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $128, %rsp
.cfi_adjust_cfa_offset -128
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z19__device_stub__copyPfPKfi, .Lfunc_end0-_Z19__device_stub__copyPfPKfi
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, %rdi
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z4copyPfPKfi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z4copyPfPKfi,@object # @_Z4copyPfPKfi
.section .rodata,"a",@progbits
.globl _Z4copyPfPKfi
.p2align 3, 0x0
_Z4copyPfPKfi:
.quad _Z19__device_stub__copyPfPKfi
.size _Z4copyPfPKfi, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z4copyPfPKfi"
.size .L__unnamed_1, 14
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z19__device_stub__copyPfPKfi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z4copyPfPKfi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
```
| 1,821 | 2,002 |
568 |
Convert the following CUDA device assembly code to AMD device assembly:
```cudaasm
code for sm_80
Function : _Z35cumulativeOffspringToAncestorKernelPKiPii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ;
S2R R5, SR_CTAID.X ;
S2R R0, SR_TID.X ;
IMAD R5, R5, c[0x0][0x0], R0 ;
ISETP.GE.AND P0, PT, R5, c[0x0][0x170], PT ;
ISETP.LT.OR P0, PT, R5, RZ, P0 ;
@P0 EXIT ;
ISETP.NE.AND P0, PT, R5.reuse, RZ, PT ;
IMAD.MOV.U32 R11, RZ, RZ, 0x4 ;
ULDC.64 UR4, c[0x0][0x118] ;
IMAD.MOV.U32 R0, RZ, RZ, RZ ;
IMAD.WIDE R2, R5, R11, c[0x0][0x160] ;
LDG.E R7, [R2.64] ;
@P0 LDG.E R0, [R2.64+-0x4] ;
ISETP.GT.AND P0, PT, R7, R0, PT ;
@!P0 EXIT ;
LOP3.LUT R2, RZ, R0, RZ, 0x33, !PT ;
IMAD.IADD R3, R7.reuse, 0x1, -R0 ;
BSSY B1, 0x600 ;
IMAD.IADD R2, R7, 0x1, R2 ;
LOP3.LUT R4, R3, 0x3, RZ, 0xc0, !PT ;
IMAD.MOV.U32 R7, RZ, RZ, RZ ;
ISETP.GE.U32.AND P0, PT, R2, 0x3, PT ;
@!P0 BRA 0x5f0 ;
IMAD.IADD R6, R3, 0x1, -R4 ;
BSSY B0, 0x530 ;
IMAD.MOV.U32 R7, RZ, RZ, RZ ;
IMAD.WIDE R2, R0, R11, c[0x0][0x168] ;
ISETP.GT.AND P0, PT, R6, RZ, PT ;
@!P0 BRA 0x520 ;
ISETP.GT.AND P1, PT, R6, 0xc, PT ;
BSSY B2, 0x3c0 ;
PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ;
@!P1 BRA 0x3b0 ;
PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ;
IADD3 R6, R6, -0x10, RZ ;
STG.E [R2.64], R5 ;
IADD3 R8, P2, R2, 0x40, RZ ;
ISETP.GT.AND P1, PT, R6, 0xc, PT ;
STG.E [R2.64+0x4], R5 ;
IADD3 R7, R7, 0x10, RZ ;
IMAD.X R9, RZ, RZ, R3, P2 ;
STG.E [R2.64+0x8], R5 ;
STG.E [R2.64+0xc], R5 ;
STG.E [R2.64+0x10], R5 ;
STG.E [R2.64+0x14], R5 ;
STG.E [R2.64+0x18], R5 ;
STG.E [R2.64+0x1c], R5 ;
STG.E [R2.64+0x20], R5 ;
STG.E [R2.64+0x24], R5 ;
STG.E [R2.64+0x28], R5 ;
STG.E [R2.64+0x2c], R5 ;
STG.E [R2.64+0x30], R5 ;
STG.E [R2.64+0x34], R5 ;
STG.E [R2.64+0x38], R5 ;
STG.E [R2.64+0x3c], R5 ;
IMAD.MOV.U32 R2, RZ, RZ, R8 ;
IMAD.MOV.U32 R3, RZ, RZ, R9 ;
@P1 BRA 0x230 ;
BSYNC B2 ;
ISETP.GT.AND P1, PT, R6, 0x4, PT ;
BSSY B2, 0x4f0 ;
@!P1 BRA 0x4e0 ;
IADD3 R8, P1, R2, 0x20, RZ ;
STG.E [R2.64], R5 ;
PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ;
IADD3 R7, R7, 0x8, RZ ;
IMAD.X R9, RZ, RZ, R3, P1 ;
STG.E [R2.64+0x4], R5 ;
IADD3 R6, R6, -0x8, RZ ;
STG.E [R2.64+0x8], R5 ;
STG.E [R2.64+0xc], R5 ;
STG.E [R2.64+0x10], R5 ;
STG.E [R2.64+0x14], R5 ;
STG.E [R2.64+0x18], R5 ;
STG.E [R2.64+0x1c], R5 ;
IMAD.MOV.U32 R2, RZ, RZ, R8 ;
IMAD.MOV.U32 R3, RZ, RZ, R9 ;
BSYNC B2 ;
ISETP.NE.OR P0, PT, R6, RZ, P0 ;
@!P0 BREAK B0 ;
@!P0 BRA 0x5f0 ;
BSYNC B0 ;
IADD3 R6, R6, -0x4, RZ ;
STG.E [R2.64], R5 ;
IADD3 R8, P1, R2, 0x10, RZ ;
ISETP.NE.AND P0, PT, R6, RZ, PT ;
STG.E [R2.64+0x4], R5 ;
IADD3 R7, R7, 0x4, RZ ;
IMAD.X R9, RZ, RZ, R3, P1 ;
STG.E [R2.64+0x8], R5 ;
STG.E [R2.64+0xc], R5 ;
IMAD.MOV.U32 R2, RZ, RZ, R8 ;
IMAD.MOV.U32 R3, RZ, RZ, R9 ;
@P0 BRA 0x530 ;
BSYNC B1 ;
WARPSYNC 0xffffffff ;
ISETP.NE.AND P0, PT, R4, RZ, PT ;
@!P0 EXIT ;
IMAD.IADD R2, R7, 0x1, R0 ;
IMAD.WIDE R2, R2, R11, c[0x0][0x168] ;
IADD3 R4, R4, -0x1, RZ ;
STG.E [R2.64], R5 ;
ISETP.NE.AND P0, PT, R4, RZ, PT ;
IADD3 R2, P1, R2, 0x4, RZ ;
IMAD.X R3, RZ, RZ, R3, P1 ;
@P0 BRA 0x650 ;
EXIT ;
BRA 0x6c0;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
```
|
```amdasm
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z35cumulativeOffspringToAncestorKernelPKiPii ; -- Begin function _Z35cumulativeOffspringToAncestorKernelPKiPii
.globl _Z35cumulativeOffspringToAncestorKernelPKiPii
.p2align 8
.type _Z35cumulativeOffspringToAncestorKernelPKiPii,@function
_Z35cumulativeOffspringToAncestorKernelPKiPii: ; @_Z35cumulativeOffspringToAncestorKernelPKiPii
; %bb.0:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s3, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
v_cmp_gt_i32_e32 vcc_lo, s3, v1
v_cmp_lt_i32_e64 s2, -1, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, vcc_lo, s2
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_6
; %bb.1:
s_load_b128 s[0:3], s[0:1], 0x0
v_dual_mov_b32 v4, 0 :: v_dual_mov_b32 v3, 0
v_mov_b32_e32 v5, 0
s_mov_b32 s4, exec_lo
v_cmpx_ne_u32_e32 0, v1
s_cbranch_execz .LBB0_3
; %bb.2:
v_mov_b32_e32 v2, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v3, vcc_lo, s0, v3
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo
global_load_b32 v3, v[3:4], off offset:-4
v_dual_mov_b32 v5, v2 :: v_dual_mov_b32 v4, v1
.LBB0_3: ; %._crit_edge
s_or_b32 exec_lo, exec_lo, s4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[4:5], 2, v[4:5]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v4, vcc_lo, s0, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v5, vcc_lo, s1, v5, vcc_lo
global_load_b32 v0, v[4:5], off
s_waitcnt vmcnt(0)
v_sub_nc_u32_e32 v0, v0, v3
v_cmp_lt_i32_e32 vcc_lo, 0, v0
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_6
; %bb.4: ; %.lr.ph.preheader
v_ashrrev_i32_e32 v4, 31, v3
s_mov_b32 s1, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[3:4]
v_add_co_u32 v2, vcc_lo, s2, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
s_mov_b32 s2, 0
.LBB0_5: ; %.lr.ph
; =>This Inner Loop Header: Depth=1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
s_add_i32 s2, s2, 1
global_store_b32 v[2:3], v1, off
v_cmp_ge_i32_e32 vcc_lo, s2, v0
v_add_co_u32 v2, s0, v2, 4
v_add_co_ci_u32_e64 v3, s0, 0, v3, s0
s_or_b32 s1, vcc_lo, s1
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s1
s_cbranch_execnz .LBB0_5
.LBB0_6: ; %.loopexit
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z35cumulativeOffspringToAncestorKernelPKiPii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z35cumulativeOffspringToAncestorKernelPKiPii, .Lfunc_end0-_Z35cumulativeOffspringToAncestorKernelPKiPii
; -- End function
.section .AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 324
; NumSgprs: 18
; NumVgprs: 6
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 6
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object ; @__hip_cuid_
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0 ; 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z35cumulativeOffspringToAncestorKernelPKiPii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z35cumulativeOffspringToAncestorKernelPKiPii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
```
| 1,953 | 3,259 |
569 |
Convert the following CUDA host assembly code to AMD host assembly:
```cudaasm
.file "tmpxft_000cb7b3_00000000-6_cumulativeOffspringToAncestorKernel.cudafe1.cpp"
.text
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z59__device_stub__Z35cumulativeOffspringToAncestorKernelPKiPiiPKiPii
.type _Z59__device_stub__Z35cumulativeOffspringToAncestorKernelPKiPiiPKiPii, @function
_Z59__device_stub__Z35cumulativeOffspringToAncestorKernelPKiPiiPKiPii:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z35cumulativeOffspringToAncestorKernelPKiPii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z59__device_stub__Z35cumulativeOffspringToAncestorKernelPKiPiiPKiPii, .-_Z59__device_stub__Z35cumulativeOffspringToAncestorKernelPKiPiiPKiPii
.globl _Z35cumulativeOffspringToAncestorKernelPKiPii
.type _Z35cumulativeOffspringToAncestorKernelPKiPii, @function
_Z35cumulativeOffspringToAncestorKernelPKiPii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z59__device_stub__Z35cumulativeOffspringToAncestorKernelPKiPiiPKiPii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z35cumulativeOffspringToAncestorKernelPKiPii, .-_Z35cumulativeOffspringToAncestorKernelPKiPii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z35cumulativeOffspringToAncestorKernelPKiPii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z35cumulativeOffspringToAncestorKernelPKiPii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
```
|
```amdasm
.text
.file "cumulativeOffspringToAncestorKernel.hip"
.globl _Z50__device_stub__cumulativeOffspringToAncestorKernelPKiPii # -- Begin function _Z50__device_stub__cumulativeOffspringToAncestorKernelPKiPii
.type _Z50__device_stub__cumulativeOffspringToAncestorKernelPKiPii,@function
_Z50__device_stub__cumulativeOffspringToAncestorKernelPKiPii: # @_Z50__device_stub__cumulativeOffspringToAncestorKernelPKiPii
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $112, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 40(%rsp), %rax
movq %rdi, (%rax)
leaq 32(%rsp), %rcx
movq %rsi, (%rcx)
leaq 12(%rsp), %rsi
movl %edx, (%rsi)
leaq 80(%rsp), %rbx
movq %rax, (%rbx)
movq %rcx, 8(%rbx)
movq %rsi, 16(%rbx)
leaq 64(%rsp), %r14
leaq 48(%rsp), %r15
leaq 24(%rsp), %r12
leaq 16(%rsp), %r13
movq %r14, %rdi
movq %r15, %rsi
movq %r12, %rdx
movq %r13, %rcx
callq __hipPopCallConfiguration
movq (%r14), %rsi
movl 8(%r14), %edx
movq (%r15), %rcx
movl 8(%r15), %r8d
movl $_Z35cumulativeOffspringToAncestorKernelPKiPii, %edi
movq %rbx, %r9
pushq (%r13)
.cfi_adjust_cfa_offset 8
pushq (%r12)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $128, %rsp
.cfi_adjust_cfa_offset -128
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z50__device_stub__cumulativeOffspringToAncestorKernelPKiPii, .Lfunc_end0-_Z50__device_stub__cumulativeOffspringToAncestorKernelPKiPii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, %rdi
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z35cumulativeOffspringToAncestorKernelPKiPii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z35cumulativeOffspringToAncestorKernelPKiPii,@object # @_Z35cumulativeOffspringToAncestorKernelPKiPii
.section .rodata,"a",@progbits
.globl _Z35cumulativeOffspringToAncestorKernelPKiPii
.p2align 3, 0x0
_Z35cumulativeOffspringToAncestorKernelPKiPii:
.quad _Z50__device_stub__cumulativeOffspringToAncestorKernelPKiPii
.size _Z35cumulativeOffspringToAncestorKernelPKiPii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z35cumulativeOffspringToAncestorKernelPKiPii"
.size .L__unnamed_1, 46
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z50__device_stub__cumulativeOffspringToAncestorKernelPKiPii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z35cumulativeOffspringToAncestorKernelPKiPii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
```
| 1,944 | 2,141 |
570 |
Convert the following CUDA device assembly code to AMD device assembly:
```cudaasm
code for sm_80
Function : _Z10segmentMaxPfS_iiiii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ;
S2R R0, SR_CTAID.X ;
IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x174] ;
ULDC.64 UR4, c[0x0][0x118] ;
BSSY B2, 0xaa0 ;
S2R R3, SR_TID.X ;
IMAD.MOV.U32 R5, RZ, RZ, RZ ;
IMAD R0, R0, c[0x0][0x0], R3 ;
IMAD R6, R0.reuse, c[0x0][0x178], RZ ;
IADD3 R2, R0, -c[0x0][0x17c], RZ ;
IADD3 R3, R2, 0x1, RZ ;
IMAD R3, R3, c[0x0][0x180], R4 ;
ISETP.GE.U32.AND P0, PT, R3, c[0x0][0x170], PT ;
IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x180] ;
ISETP.GT.U32.AND P0, PT, R6, c[0x0][0x174], !P0 ;
SEL R3, R3, c[0x0][0x178], P0 ;
ISETP.GE.AND P1, PT, R3, 0x1, PT ;
@P0 IMAD R6, R2, c[0x0][0x180], R4 ;
@!P1 BRA 0xa90 ;
IADD3 R2, R3.reuse, -0x1, RZ ;
BSSY B1, 0x990 ;
LOP3.LUT R4, R3, 0x3, RZ, 0xc0, !PT ;
IMAD.MOV.U32 R7, RZ, RZ, RZ ;
ISETP.GE.U32.AND P0, PT, R2, 0x3, PT ;
IMAD.MOV.U32 R5, RZ, RZ, RZ ;
@!P0 BRA 0x980 ;
LEA R2, P0, R6.reuse, c[0x0][0x160], 0x2 ;
IMAD.IADD R8, R3, 0x1, -R4 ;
BSSY B0, 0x850 ;
IMAD.MOV.U32 R7, RZ, RZ, RZ ;
LEA.HI.X R3, R6, c[0x0][0x164], RZ, 0x2, P0 ;
IMAD.MOV.U32 R5, RZ, RZ, RZ ;
ISETP.GT.AND P0, PT, R8, RZ, PT ;
IADD3 R2, P1, R2, 0x8, RZ ;
IMAD.X R3, RZ, RZ, R3, P1 ;
@!P0 BRA 0x840 ;
ISETP.GT.AND P1, PT, R8, 0xc, PT ;
BSSY B3, 0x600 ;
PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ;
@!P1 BRA 0x5f0 ;
PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ;
LDG.E R20, [R2.64+-0x8] ;
LDG.E R22, [R2.64+-0x4] ;
LDG.E R24, [R2.64] ;
LDG.E R26, [R2.64+0x4] ;
LDG.E R28, [R2.64+0x8] ;
LDG.E R19, [R2.64+0xc] ;
LDG.E R18, [R2.64+0x10] ;
LDG.E R17, [R2.64+0x14] ;
LDG.E R16, [R2.64+0x18] ;
LDG.E R15, [R2.64+0x1c] ;
LDG.E R14, [R2.64+0x20] ;
LDG.E R13, [R2.64+0x24] ;
LDG.E R12, [R2.64+0x28] ;
LDG.E R11, [R2.64+0x2c] ;
LDG.E R10, [R2.64+0x30] ;
LDG.E R9, [R2.64+0x34] ;
IADD3 R8, R8, -0x10, RZ ;
IADD3 R7, R7, 0x10, RZ ;
ISETP.GT.AND P2, PT, R8, 0xc, PT ;
IADD3 R2, P3, R2, 0x40, RZ ;
IMAD.X R3, RZ, RZ, R3, P3 ;
FSETP.GEU.AND P1, PT, R5, |R20|, PT ;
FSEL R5, |R20|, R5, !P1 ;
FSETP.GEU.AND P1, PT, R5, |R22|, PT ;
FSEL R5, |R22|, R5, !P1 ;
FSETP.GEU.AND P1, PT, R5, |R24|, PT ;
FSEL R5, |R24|, R5, !P1 ;
FSETP.GEU.AND P1, PT, R5, |R26|, PT ;
FSEL R5, |R26|, R5, !P1 ;
FSETP.GEU.AND P1, PT, R5, |R28|, PT ;
FSEL R5, |R28|, R5, !P1 ;
FSETP.GEU.AND P1, PT, R5, |R19|, PT ;
FSEL R5, |R19|, R5, !P1 ;
FSETP.GEU.AND P1, PT, R5, |R18|, PT ;
FSEL R18, |R18|, R5, !P1 ;
FSETP.GEU.AND P1, PT, R18, |R17|, PT ;
FSEL R17, |R17|, R18, !P1 ;
FSETP.GEU.AND P1, PT, R17, |R16|, PT ;
FSEL R16, |R16|, R17, !P1 ;
FSETP.GEU.AND P1, PT, R16, |R15|, PT ;
FSEL R15, |R15|, R16, !P1 ;
FSETP.GEU.AND P1, PT, R15, |R14|, PT ;
FSEL R14, |R14|, R15, !P1 ;
FSETP.GEU.AND P1, PT, R14, |R13|, PT ;
FSEL R13, |R13|, R14, !P1 ;
FSETP.GEU.AND P1, PT, R13, |R12|, PT ;
FSEL R12, |R12|, R13, !P1 ;
FSETP.GEU.AND P1, PT, R12, |R11|, PT ;
FSEL R11, |R11|, R12, !P1 ;
FSETP.GEU.AND P1, PT, R11, |R10|, PT ;
FSEL R10, |R10|, R11, !P1 ;
FSETP.GEU.AND P1, PT, R10, |R9|, PT ;
FSEL R5, |R9|, R10, !P1 ;
@P2 BRA 0x290 ;
BSYNC B3 ;
ISETP.GT.AND P1, PT, R8, 0x4, PT ;
BSSY B3, 0x810 ;
@!P1 BRA 0x800 ;
LDG.E R10, [R2.64+-0x8] ;
LDG.E R12, [R2.64+-0x4] ;
LDG.E R14, [R2.64] ;
LDG.E R16, [R2.64+0x4] ;
LDG.E R18, [R2.64+0x8] ;
LDG.E R20, [R2.64+0xc] ;
LDG.E R22, [R2.64+0x10] ;
LDG.E R24, [R2.64+0x14] ;
IADD3 R7, R7, 0x8, RZ ;
IADD3 R8, R8, -0x8, RZ ;
IADD3 R2, P2, R2, 0x20, RZ ;
IMAD.X R3, RZ, RZ, R3, P2 ;
FSETP.GEU.AND P0, PT, R5, |R10|, PT ;
FSEL R5, |R10|, R5, !P0 ;
FSETP.GEU.AND P0, PT, R5, |R12|, PT ;
FSEL R5, |R12|, R5, !P0 ;
FSETP.GEU.AND P0, PT, R5, |R14|, PT ;
FSEL R5, |R14|, R5, !P0 ;
FSETP.GEU.AND P0, PT, R5, |R16|, PT ;
FSEL R5, |R16|, R5, !P0 ;
FSETP.GEU.AND P0, PT, R5, |R18|, PT ;
FSEL R5, |R18|, R5, !P0 ;
FSETP.GEU.AND P0, PT, R5, |R20|, PT ;
FSEL R5, |R20|, R5, !P0 ;
FSETP.GEU.AND P0, PT, R5, |R22|, PT ;
FSEL R5, |R22|, R5, !P0 ;
PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ;
FSETP.GEU.AND P1, PT, R5, |R24|, PT ;
FSEL R5, |R24|, R5, !P1 ;
BSYNC B3 ;
ISETP.NE.OR P0, PT, R8, RZ, P0 ;
@!P0 BREAK B0 ;
@!P0 BRA 0x980 ;
BSYNC B0 ;
LDG.E R10, [R2.64+-0x8] ;
LDG.E R12, [R2.64+-0x4] ;
LDG.E R14, [R2.64] ;
LDG.E R16, [R2.64+0x4] ;
IADD3 R8, R8, -0x4, RZ ;
IADD3 R9, P2, R2, 0x10, RZ ;
ISETP.NE.AND P1, PT, R8, RZ, PT ;
IADD3 R7, R7, 0x4, RZ ;
IMAD.X R3, RZ, RZ, R3, P2 ;
IMAD.MOV.U32 R2, RZ, RZ, R9 ;
FSETP.GEU.AND P0, PT, R5, |R10|, PT ;
FSEL R5, |R10|, R5, !P0 ;
FSETP.GEU.AND P0, PT, R5, |R12|, PT ;
FSEL R5, |R12|, R5, !P0 ;
FSETP.GEU.AND P0, PT, R5, |R14|, PT ;
FSEL R5, |R14|, R5, !P0 ;
FSETP.GEU.AND P0, PT, R5, |R16|, PT ;
FSEL R5, |R16|, R5, !P0 ;
@P1 BRA 0x850 ;
BSYNC B1 ;
ISETP.NE.AND P0, PT, R4, RZ, PT ;
@!P0 BRA 0xa90 ;
IADD3 R2, P0, R6, R7, RZ ;
LEA R6, P1, R2, c[0x0][0x160], 0x2 ;
LEA.HI.X.SX32 R7, R7, RZ, 0x1, P0 ;
LEA.HI.X R7, R2, c[0x0][0x164], R7, 0x2, P1 ;
IMAD.MOV.U32 R2, RZ, RZ, R6 ;
IMAD.MOV.U32 R3, RZ, RZ, R7 ;
LDG.E R2, [R2.64] ;
IADD3 R4, R4, -0x1, RZ ;
IADD3 R6, P2, R6, 0x4, RZ ;
ISETP.NE.AND P1, PT, R4, RZ, PT ;
IMAD.X R7, RZ, RZ, R7, P2 ;
FSETP.GEU.AND P0, PT, R5, |R2|, PT ;
FSEL R5, |R2|, R5, !P0 ;
@P1 BRA 0x9f0 ;
BSYNC B2 ;
WARPSYNC 0xffffffff ;
IMAD.MOV.U32 R3, RZ, RZ, 0x4 ;
IMAD.WIDE.U32 R2, R0, R3, c[0x0][0x168] ;
STG.E [R2.64], R5 ;
EXIT ;
BRA 0xaf0;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
```
|
```amdasm
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10segmentMaxPfS_iiiii ; -- Begin function _Z10segmentMaxPfS_iiiii
.globl _Z10segmentMaxPfS_iiiii
.p2align 8
.type _Z10segmentMaxPfS_iiiii,@function
_Z10segmentMaxPfS_iiiii: ; @_Z10segmentMaxPfS_iiiii
; %bb.0:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x34
s_load_b256 s[4:11], s[0:1], 0x0
s_load_b32 s3, s[0:1], 0x20
s_mov_b32 s1, exec_lo
v_mov_b32_e32 v3, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s0, s2, 0xffff
s_mov_b32 s2, 0
v_mad_u64_u32 v[1:2], null, s15, s0, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v4, s11, v1
v_mul_lo_u32 v2, v1, s10
v_mul_lo_u32 v0, s3, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_lt_u32_e32 vcc_lo, s9, v2
v_add3_u32 v0, s9, s3, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cmp_gt_u32_e64 s0, s8, v0
v_mov_b32_e32 v0, s3
s_and_b32 vcc_lo, vcc_lo, s0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v0, s10, v0, vcc_lo
v_cmpx_lt_i32_e32 0, v0
s_cbranch_execz .LBB0_4
; %bb.1: ; %.lr.ph.i.preheader
s_mov_b32 s0, s9
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[5:6], null, v4, s3, s[0:1]
v_dual_mov_b32 v3, 0 :: v_dual_cndmask_b32 v2, v2, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[4:5], 2, v[2:3]
v_add_co_u32 v4, vcc_lo, s4, v4
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v5, vcc_lo
.LBB0_2: ; %.lr.ph.i
; =>This Inner Loop Header: Depth=1
global_load_b32 v2, v[4:5], off
v_add_nc_u32_e32 v0, -1, v0
v_add_co_u32 v4, vcc_lo, v4, 4
v_add_co_ci_u32_e32 v5, vcc_lo, 0, v5, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_eq_u32_e64 s0, 0, v0
s_or_b32 s2, s0, s2
s_waitcnt vmcnt(0)
v_cmp_lt_f32_e64 s3, v3, |v2|
s_delay_alu instid0(VALU_DEP_1)
v_cndmask_b32_e64 v3, v3, |v2|, s3
s_and_not1_b32 exec_lo, exec_lo, s2
s_cbranch_execnz .LBB0_2
; %bb.3: ; %Flow
s_or_b32 exec_lo, exec_lo, s2
.LBB0_4: ; %Flow45
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
s_or_b32 exec_lo, exec_lo, s1
v_mov_b32_e32 v2, 0
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
global_store_b32 v[0:1], v3, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10segmentMaxPfS_iiiii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10segmentMaxPfS_iiiii, .Lfunc_end0-_Z10segmentMaxPfS_iiiii
; -- End function
.section .AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 320
; NumSgprs: 18
; NumVgprs: 7
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 7
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object ; @__hip_cuid_
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0 ; 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10segmentMaxPfS_iiiii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z10segmentMaxPfS_iiiii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
```
| 3,471 | 3,328 |
571 |
Convert the following CUDA host assembly code to AMD host assembly:
```cudaasm
.file "tmpxft_0001bd55_00000000-6_segmentMax.cudafe1.cpp"
.text
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2030:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z9getAbsMaxPfi
.type _Z9getAbsMaxPfi, @function
_Z9getAbsMaxPfi:
.LFB2027:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2027:
.size _Z9getAbsMaxPfi, .-_Z9getAbsMaxPfi
.globl _Z37__device_stub__Z10segmentMaxPfS_iiiiiPfS_iiiii
.type _Z37__device_stub__Z10segmentMaxPfS_iiiiiPfS_iiiii, @function
_Z37__device_stub__Z10segmentMaxPfS_iiiiiPfS_iiiii:
.LFB2052:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
movl %r9d, (%rsp)
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 4(%rsp), %rax
movq %rax, 128(%rsp)
movq %rsp, %rax
movq %rax, 136(%rsp)
leaq 176(%rsp), %rax
movq %rax, 144(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L9
.L5:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L10
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L9:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 184
pushq 40(%rsp)
.cfi_def_cfa_offset 192
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z10segmentMaxPfS_iiiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L5
.L10:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2052:
.size _Z37__device_stub__Z10segmentMaxPfS_iiiiiPfS_iiiii, .-_Z37__device_stub__Z10segmentMaxPfS_iiiiiPfS_iiiii
.globl _Z10segmentMaxPfS_iiiii
.type _Z10segmentMaxPfS_iiiii, @function
_Z10segmentMaxPfS_iiiii:
.LFB2053:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
call _Z37__device_stub__Z10segmentMaxPfS_iiiiiPfS_iiiii
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2053:
.size _Z10segmentMaxPfS_iiiii, .-_Z10segmentMaxPfS_iiiii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z10segmentMaxPfS_iiiii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2055:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z10segmentMaxPfS_iiiii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2055:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
```
|
```amdasm
.text
.file "segmentMax.hip"
.globl _Z25__device_stub__segmentMaxPfS_iiiii # -- Begin function _Z25__device_stub__segmentMaxPfS_iiiii
.type _Z25__device_stub__segmentMaxPfS_iiiii,@function
_Z25__device_stub__segmentMaxPfS_iiiii: # @_Z25__device_stub__segmentMaxPfS_iiiii
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $144, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 40(%rsp), %rax
movq %rdi, (%rax)
leaq 32(%rsp), %rdi
movq %rsi, (%rdi)
leaq 12(%rsp), %rsi
movl %edx, (%rsi)
leaq 8(%rsp), %rdx
movl %ecx, (%rdx)
leaq 4(%rsp), %rcx
movl %r8d, (%rcx)
movq %rsp, %r8
movl %r9d, (%r8)
leaq 80(%rsp), %rbx
movq %rax, (%rbx)
movq %rdi, 8(%rbx)
movq %rsi, 16(%rbx)
movq %rdx, 24(%rbx)
movq %rcx, 32(%rbx)
movq %r8, 40(%rbx)
leaq 192(%rsp), %rax
movq %rax, 48(%rbx)
leaq 64(%rsp), %r14
leaq 48(%rsp), %r15
leaq 24(%rsp), %r12
leaq 16(%rsp), %r13
movq %r14, %rdi
movq %r15, %rsi
movq %r12, %rdx
movq %r13, %rcx
callq __hipPopCallConfiguration
movq (%r14), %rsi
movl 8(%r14), %edx
movq (%r15), %rcx
movl 8(%r15), %r8d
movl $_Z10segmentMaxPfS_iiiii, %edi
movq %rbx, %r9
pushq (%r13)
.cfi_adjust_cfa_offset 8
pushq (%r12)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $160, %rsp
.cfi_adjust_cfa_offset -160
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z25__device_stub__segmentMaxPfS_iiiii, .Lfunc_end0-_Z25__device_stub__segmentMaxPfS_iiiii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, %rdi
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10segmentMaxPfS_iiiii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10segmentMaxPfS_iiiii,@object # @_Z10segmentMaxPfS_iiiii
.section .rodata,"a",@progbits
.globl _Z10segmentMaxPfS_iiiii
.p2align 3, 0x0
_Z10segmentMaxPfS_iiiii:
.quad _Z25__device_stub__segmentMaxPfS_iiiii
.size _Z10segmentMaxPfS_iiiii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z10segmentMaxPfS_iiiii"
.size .L__unnamed_1, 24
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__segmentMaxPfS_iiiii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10segmentMaxPfS_iiiii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
```
| 2,221 | 2,199 |
572 |
Convert the following CUDA device assembly code to AMD device assembly:
```cudaasm
code for sm_80
Function : _Z12mmult_kernelPKiS0_Pi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
MOV R1, c[0x0][0x28] ;
S2R R11, SR_CTAID.X ;
ULDC.64 UR4, c[0x0][0x118] ;
S2R R0, SR_TID.X ;
S2R R2, SR_CTAID.Y ;
S2R R3, SR_TID.Y ;
STS [RZ], RZ ;
HFMA2.MMA R10, -RZ, RZ, 0, 0 ;
MOV R4, c[0x0][0x160] ;
ULDC.64 UR6, c[0x0][0x168] ;
IMAD R11, R11, c[0x0][0x0], R0 ;
SHF.L.U32 R11, R11, 0xa, RZ ;
IMAD R0, R2, c[0x0][0x4], R3 ;
HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ;
IADD3 R2, R0, R11, RZ ;
IMAD.WIDE R2, R2, R3, c[0x0][0x170] ;
LDG.E R17, [R2.64] ;
MOV R5, c[0x0][0x164] ;
IADD3 R13, R11, 0x1, RZ ;
MOV R6, UR6 ;
IMAD.WIDE R14, R11, 0x4, R4 ;
MOV R7, UR7 ;
LDG.E R8, [R14.64] ;
IMAD.WIDE R6, R0, 0x4, R6 ;
LDG.E R9, [R6.64] ;
IMAD.SHL.U32 R8, R8, 0x2, RZ ;
IMAD R17, R8, R9, R17 ;
IMAD.WIDE R8, R13, 0x4, R4 ;
STG.E [R2.64], R17 ;
LDG.E R12, [R8.64] ;
LDG.E R16, [R6.64+0x1000] ;
SHF.L.U32 R12, R12, 0x1, RZ ;
IMAD R19, R12, R16, R17 ;
STG.E [R2.64], R19 ;
LDG.E R12, [R8.64+0x4] ;
LDG.E R16, [R6.64+0x2000] ;
SHF.L.U32 R12, R12, 0x1, RZ ;
IMAD R21, R12, R16, R19 ;
STG.E [R2.64], R21 ;
LDG.E R12, [R8.64+0x8] ;
LDG.E R16, [R6.64+0x3000] ;
SHF.L.U32 R12, R12, 0x1, RZ ;
IMAD R17, R12, R16, R21 ;
STG.E [R2.64], R17 ;
LDG.E R12, [R8.64+0xc] ;
LDG.E R16, [R6.64+0x4000] ;
SHF.L.U32 R12, R12, 0x1, RZ ;
IMAD R19, R12, R16, R17 ;
STG.E [R2.64], R19 ;
LDG.E R12, [R8.64+0x10] ;
LDG.E R16, [R6.64+0x5000] ;
SHF.L.U32 R12, R12, 0x1, RZ ;
IMAD R21, R12, R16, R19 ;
STG.E [R2.64], R21 ;
LDG.E R12, [R8.64+0x14] ;
LDG.E R16, [R6.64+0x6000] ;
SHF.L.U32 R12, R12, 0x1, RZ ;
IMAD R17, R12, R16, R21 ;
STG.E [R2.64], R17 ;
LDG.E R12, [R8.64+0x18] ;
LDG.E R16, [R6.64+0x7000] ;
SHF.L.U32 R12, R12, 0x1, RZ ;
IMAD R19, R12, R16, R17 ;
STG.E [R2.64], R19 ;
LDG.E R12, [R14.64+0x20] ;
LDG.E R16, [R6.64+0x8000] ;
IMAD.SHL.U32 R12, R12, 0x2, RZ ;
IMAD R21, R12, R16, R19 ;
STG.E [R2.64], R21 ;
LDG.E R12, [R8.64+0x20] ;
LDG.E R16, [R6.64+0x9000] ;
SHF.L.U32 R12, R12, 0x1, RZ ;
IMAD R17, R12, R16, R21 ;
STG.E [R2.64], R17 ;
LDG.E R12, [R8.64+0x24] ;
LDG.E R16, [R6.64+0xa000] ;
SHF.L.U32 R12, R12, 0x1, RZ ;
IMAD R19, R12, R16, R17 ;
STG.E [R2.64], R19 ;
LDG.E R12, [R8.64+0x28] ;
LDG.E R16, [R6.64+0xb000] ;
SHF.L.U32 R12, R12, 0x1, RZ ;
IMAD R21, R12, R16, R19 ;
STG.E [R2.64], R21 ;
LDG.E R12, [R8.64+0x2c] ;
LDG.E R16, [R6.64+0xc000] ;
SHF.L.U32 R12, R12, 0x1, RZ ;
IMAD R17, R12, R16, R21 ;
STG.E [R2.64], R17 ;
LDG.E R12, [R8.64+0x30] ;
LDG.E R16, [R6.64+0xd000] ;
SHF.L.U32 R12, R12, 0x1, RZ ;
IMAD R19, R12, R16, R17 ;
STG.E [R2.64], R19 ;
LDG.E R12, [R8.64+0x34] ;
LDG.E R16, [R6.64+0xe000] ;
SHF.L.U32 R12, R12, 0x1, RZ ;
IMAD R21, R12, R16, R19 ;
STG.E [R2.64], R21 ;
LDG.E R12, [R8.64+0x38] ;
LDG.E R16, [R6.64+0xf000] ;
SHF.L.U32 R12, R12, 0x1, RZ ;
IMAD R17, R12, R16, R21 ;
STG.E [R2.64], R17 ;
LDG.E R12, [R14.64+0x40] ;
LDG.E R16, [R6.64+0x10000] ;
IMAD.SHL.U32 R12, R12, 0x2, RZ ;
IMAD R19, R12, R16, R17 ;
STG.E [R2.64], R19 ;
LDG.E R12, [R8.64+0x40] ;
LDG.E R16, [R6.64+0x11000] ;
SHF.L.U32 R12, R12, 0x1, RZ ;
IMAD R21, R12, R16, R19 ;
STG.E [R2.64], R21 ;
LDG.E R12, [R8.64+0x44] ;
LDG.E R16, [R6.64+0x12000] ;
SHF.L.U32 R12, R12, 0x1, RZ ;
IMAD R17, R12, R16, R21 ;
STG.E [R2.64], R17 ;
LDG.E R12, [R8.64+0x48] ;
LDG.E R16, [R6.64+0x13000] ;
SHF.L.U32 R12, R12, 0x1, RZ ;
IMAD R19, R12, R16, R17 ;
STG.E [R2.64], R19 ;
LDG.E R12, [R8.64+0x4c] ;
LDG.E R16, [R6.64+0x14000] ;
SHF.L.U32 R12, R12, 0x1, RZ ;
IMAD R21, R12, R16, R19 ;
STG.E [R2.64], R21 ;
LDG.E R12, [R8.64+0x50] ;
LDG.E R16, [R6.64+0x15000] ;
SHF.L.U32 R12, R12, 0x1, RZ ;
IMAD R17, R12, R16, R21 ;
STG.E [R2.64], R17 ;
LDG.E R12, [R8.64+0x54] ;
LDG.E R16, [R6.64+0x16000] ;
SHF.L.U32 R12, R12, 0x1, RZ ;
IMAD R19, R12, R16, R17 ;
STG.E [R2.64], R19 ;
LDG.E R12, [R8.64+0x58] ;
LDG.E R16, [R6.64+0x17000] ;
SHF.L.U32 R12, R12, 0x1, RZ ;
IMAD R21, R12, R16, R19 ;
STG.E [R2.64], R21 ;
LDG.E R14, [R14.64+0x60] ;
LDG.E R17, [R6.64+0x18000] ;
SHF.L.U32 R12, R14, 0x1, RZ ;
IMAD R17, R12, R17, R21 ;
STG.E [R2.64], R17 ;
LDG.E R12, [R8.64+0x60] ;
LDG.E R16, [R6.64+0x19000] ;
IMAD.SHL.U32 R12, R12, 0x2, RZ ;
IMAD R19, R12, R16, R17 ;
STG.E [R2.64], R19 ;
LDG.E R12, [R8.64+0x64] ;
LDG.E R14, [R6.64+0x1a000] ;
SHF.L.U32 R12, R12, 0x1, RZ ;
IMAD R15, R12, R14, R19 ;
STG.E [R2.64], R15 ;
LDG.E R12, [R8.64+0x68] ;
LDG.E R14, [R6.64+0x1b000] ;
SHF.L.U32 R12, R12, 0x1, RZ ;
IMAD R17, R12, R14, R15 ;
STG.E [R2.64], R17 ;
LDG.E R12, [R8.64+0x6c] ;
LDG.E R14, [R6.64+0x1c000] ;
SHF.L.U32 R12, R12, 0x1, RZ ;
IMAD R19, R12, R14, R17 ;
STG.E [R2.64], R19 ;
LDG.E R12, [R8.64+0x70] ;
LDG.E R14, [R6.64+0x1d000] ;
SHF.L.U32 R12, R12, 0x1, RZ ;
IMAD R15, R12, R14, R19 ;
STG.E [R2.64], R15 ;
LDG.E R12, [R8.64+0x74] ;
LDG.E R14, [R6.64+0x1e000] ;
SHF.L.U32 R12, R12, 0x1, RZ ;
IMAD R21, R12, R14, R15 ;
STG.E [R2.64], R21 ;
LDG.E R12, [R8.64+0x78] ;
LDG.E R17, [R6.64+0x1f000] ;
IADD3 R10, R10, 0x20, RZ ;
ISETP.NE.AND P0, PT, R10, 0x400, PT ;
UIADD3 UR6, UP0, UR6, 0x20000, URZ ;
IADD3 R4, P1, R4, 0x80, RZ ;
UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ;
IADD3.X R5, RZ, R5, RZ, P1, !PT ;
SHF.L.U32 R12, R12, 0x1, RZ ;
IMAD R17, R12, R17, R21 ;
STG.E [R2.64], R17 ;
@P0 BRA 0x130 ;
MOV R0, 0x400 ;
STS [RZ], R0 ;
EXIT ;
BRA 0xc20;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
```
|
```amdasm
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z12mmult_kernelPKiS0_Pi ; -- Begin function _Z12mmult_kernelPKiS0_Pi
.globl _Z12mmult_kernelPKiS0_Pi
.p2align 8
.type _Z12mmult_kernelPKiS0_Pi,@function
_Z12mmult_kernelPKiS0_Pi: ; @_Z12mmult_kernelPKiS0_Pi
; %bb.0:
s_load_b32 s2, s[0:1], 0x24
v_bfe_u32 v2, v0, 10, 10
v_and_b32_e32 v3, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s3, s2, 16
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[0:1], null, s15, s3, v[2:3]
s_mul_i32 s14, s14, s2
s_load_b64 s[2:3], s[0:1], 0x10
v_add_lshl_u32 v5, s14, v3, 10
v_ashrrev_i32_e32 v6, 31, v5
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v1, v5, v0
v_lshlrev_b64 v[5:6], 2, v[5:6]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b64 v[2:3], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s2, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
s_load_b128 s[0:3], s[0:1], 0x0
global_load_b32 v4, v[2:3], off
s_waitcnt lgkmcnt(0)
v_add_co_u32 v5, vcc_lo, s0, v5
v_add_co_ci_u32_e32 v6, vcc_lo, s1, v6, vcc_lo
s_mov_b64 s[0:1], 0
.LBB0_1: ; =>This Inner Loop Header: Depth=1
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v7, vcc_lo, v5, s0
v_add_co_ci_u32_e32 v8, vcc_lo, s1, v6, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[9:10], 2, v[0:1]
v_add_nc_u32_e32 v0, 0x400, v0
s_add_u32 s0, s0, 4
s_addc_u32 s1, s1, 0
s_cmpk_lg_i32 s0, 0x1000
v_add_co_u32 v9, vcc_lo, s2, v9
v_add_co_ci_u32_e32 v10, vcc_lo, s3, v10, vcc_lo
global_load_b32 v1, v[7:8], off
global_load_b32 v7, v[9:10], off
s_waitcnt vmcnt(0)
v_mul_lo_u32 v1, v1, v7
s_delay_alu instid0(VALU_DEP_1)
v_lshl_add_u32 v4, v1, 1, v4
global_store_b32 v[2:3], v4, off
s_cbranch_scc1 .LBB0_1
; %bb.2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z12mmult_kernelPKiS0_Pi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 11
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z12mmult_kernelPKiS0_Pi, .Lfunc_end0-_Z12mmult_kernelPKiS0_Pi
; -- End function
.section .AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 292
; NumSgprs: 18
; NumVgprs: 11
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 11
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object ; @__hip_cuid_
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0 ; 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z12mmult_kernelPKiS0_Pi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z12mmult_kernelPKiS0_Pi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 11
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
```
| 3,759 | 3,059 |
573 |
Convert the following CUDA host assembly code to AMD host assembly:
```cudaasm
.file "tmpxft_0002dbba_00000000-6_mm.cudafe1.cpp"
.text
.globl _ZSt21ios_base_library_initv
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3674:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3674:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z5mmultv
.type _Z5mmultv, @function
_Z5mmultv:
.LFB3669:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
movl $0, %r10d
leaq outputArrayC(%rip), %rbp
leaq 4198400+inputArrayB(%rip), %rbx
leaq inputArrayA(%rip), %r11
.L4:
leaq (%r10,%rbp), %r8
leaq 4194304+inputArrayB(%rip), %rdi
.L8:
movq %r8, %r9
movl (%r8), %esi
leaq (%r10,%r11), %rcx
leaq -4194304(%rdi), %rax
.L5:
movl (%rcx), %edx
imull (%rax), %edx
leal (%rsi,%rdx,2), %esi
addq $4, %rcx
addq $4096, %rax
cmpq %rdi, %rax
jne .L5
movl %esi, (%r9)
addq $4, %r8
addq $4, %rdi
cmpq %rbx, %rdi
jne .L8
addq $4096, %r10
cmpq $4194304, %r10
jne .L4
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3669:
.size _Z5mmultv, .-_Z5mmultv
.globl _Z38__device_stub__Z12mmult_kernelPKiS0_PiPKiS0_Pi
.type _Z38__device_stub__Z12mmult_kernelPKiS0_PiPKiS0_Pi, @function
_Z38__device_stub__Z12mmult_kernelPKiS0_PiPKiS0_Pi:
.LFB3696:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z12mmult_kernelPKiS0_Pi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3696:
.size _Z38__device_stub__Z12mmult_kernelPKiS0_PiPKiS0_Pi, .-_Z38__device_stub__Z12mmult_kernelPKiS0_PiPKiS0_Pi
.globl _Z12mmult_kernelPKiS0_Pi
.type _Z12mmult_kernelPKiS0_Pi, @function
_Z12mmult_kernelPKiS0_Pi:
.LFB3697:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z38__device_stub__Z12mmult_kernelPKiS0_PiPKiS0_Pi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _Z12mmult_kernelPKiS0_Pi, .-_Z12mmult_kernelPKiS0_Pi
.globl _Z9mmult_gpuPKiS0_Pi
.type _Z9mmult_gpuPKiS0_Pi, @function
_Z9mmult_gpuPKiS0_Pi:
.LFB3670:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $32, %rsp
.cfi_def_cfa_offset 64
movq %rdi, %rbx
movq %rsi, %rbp
movq %rdx, %r12
movl $64, 8(%rsp)
movl $64, 12(%rsp)
movl $16, 20(%rsp)
movl $16, 24(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L22
.L19:
addq $32, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L22:
.cfi_restore_state
movq %r12, %rdx
movq %rbp, %rsi
movq %rbx, %rdi
call _Z38__device_stub__Z12mmult_kernelPKiS0_PiPKiS0_Pi
jmp .L19
.cfi_endproc
.LFE3670:
.size _Z9mmult_gpuPKiS0_Pi, .-_Z9mmult_gpuPKiS0_Pi
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "Run time on CPU: %lf sec\n"
.LC2:
.string "Run time on GPU: %lf sec\n"
.LC3:
.string "totalSum_cpu = "
.LC4:
.string "totalSum_gpu = "
.text
.globl main
.type main, @function
main:
.LFB3671:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $56, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movl $4194304, %edi
call _Znam@PLT
movq %rax, %r15
movl $4194304, %edi
call _Znam@PLT
movq %rax, %r13
movl $4194304, %edi
call _Znam@PLT
movq %rax, %r14
leaq 16(%rsp), %rdi
movl $4194304, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $4194304, %esi
call cudaMalloc@PLT
leaq 32(%rsp), %rdi
movl $4194304, %esi
call cudaMalloc@PLT
movq %r15, %rsi
movl $1024, %ecx
.L24:
leal -1024(%rcx), %eax
movq %rsi, %rdx
.L25:
movl %eax, (%rdx)
addl $1, %eax
addq $4, %rdx
cmpl %ecx, %eax
jne .L25
addq $4096, %rsi
addl $1024, %ecx
cmpl $1049600, %ecx
jne .L24
movq %r13, %rcx
leaq 4194304(%r13), %rsi
.L28:
movq %rcx, %rdx
movl $0, %eax
.L27:
movl %eax, (%rdx)
addl $1025, %eax
addq $4, %rdx
cmpl $1049600, %eax
jne .L27
addq $4096, %rcx
cmpq %rsi, %rcx
jne .L28
leaq inputArrayA(%rip), %rbx
leaq inputArrayB(%rip), %rbp
leaq 4194304(%rbx), %r12
leaq outputArrayC(%rip), %r9
movq %rbp, %r8
movq %rbx, %rsi
movl $0, %edi
.L29:
movl $0, %edx
movl $0, %eax
.L30:
leal (%rdi,%rax), %ecx
movl %ecx, (%rsi,%rax,4)
movl %edx, (%r8,%rax,4)
movl $0, (%r9,%rax,4)
addq $1, %rax
addl $1025, %edx
cmpq $1024, %rax
jne .L30
addl $1024, %edi
addq $4096, %rsi
addq $4096, %r8
addq $4096, %r9
cmpq %r12, %rsi
jne .L29
movl $1, %ecx
movl $4194304, %edx
movq %r15, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $4194304, %edx
movq %r13, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl $0, %esi
.L32:
movl $0, %edx
movl $0, %eax
.L33:
leal (%rsi,%rax), %ecx
movl %ecx, (%rbx,%rax,4)
movl %edx, 0(%rbp,%rax,4)
addq $1, %rax
addl $1025, %edx
cmpq $1024, %rax
jne .L33
addl $1024, %esi
addq $4096, %rbx
addq $4096, %rbp
cmpq %r12, %rbx
jne .L32
call clock@PLT
movq %rax, %rbx
call _Z5mmultv
call clock@PLT
subq %rbx, %rax
pxor %xmm0, %xmm0
cvtsi2ssq %rax, %xmm0
divss .LC0(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
call clock@PLT
movq %rax, %rbx
movq 32(%rsp), %rdx
movq 24(%rsp), %rsi
movq 16(%rsp), %rdi
call _Z9mmult_gpuPKiS0_Pi
call cudaThreadSynchronize@PLT
movl $2, %ecx
movl $4194304, %edx
movq 32(%rsp), %rsi
movq %r14, %rdi
call cudaMemcpy@PLT
call clock@PLT
subq %rbx, %rax
pxor %xmm0, %xmm0
cvtsi2ssq %rax, %xmm0
divss .LC0(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
leaq 4096+outputArrayC(%rip), %rdx
leaq 4194304(%rdx), %rcx
.L35:
leaq -4096(%rdx), %rax
.L36:
pxor %xmm0, %xmm0
cvtsi2sdl (%rax), %xmm0
addsd (%rsp), %xmm0
movsd %xmm0, (%rsp)
addq $4, %rax
cmpq %rdx, %rax
jne .L36
addq $4096, %rdx
cmpq %rdx, %rcx
jne .L35
leaq .LC3(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movsd (%rsp), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq %r14, %rax
leaq 4194304(%r14), %rdx
.L38:
pxor %xmm0, %xmm0
cvtsi2sdl (%rax), %xmm0
addsd 8(%rsp), %xmm0
movsd %xmm0, 8(%rsp)
addq $4, %rax
cmpq %rax, %rdx
jne .L38
leaq .LC4(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movsd 8(%rsp), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq %r14, %rdi
call _ZdaPv@PLT
movq %r13, %rdi
call _ZdaPv@PLT
movq %r15, %rdi
call _ZdaPv@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L48
movl $0, %eax
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L48:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3671:
.size main, .-main
.section .rodata.str1.1
.LC5:
.string "_Z12mmult_kernelPKiS0_Pi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3699:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _Z12mmult_kernelPKiS0_Pi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3699:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl outputArrayC
.bss
.align 32
.type outputArrayC, @object
.size outputArrayC, 4194304
outputArrayC:
.zero 4194304
.globl inputArrayB
.align 32
.type inputArrayB, @object
.size inputArrayB, 4194304
inputArrayB:
.zero 4194304
.globl inputArrayA
.align 32
.type inputArrayA, @object
.size inputArrayA, 4194304
inputArrayA:
.zero 4194304
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC0:
.long 1232348160
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
```
|
```amdasm
.text
.file "mm.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z5mmultv # -- Begin function _Z5mmultv
.type _Z5mmultv,@function
_Z5mmultv: # @_Z5mmultv
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
movl $inputArrayA, %eax
xorl %ecx, %ecx
.LBB0_1: # %.preheader14
# =>This Loop Header: Depth=1
# Child Loop BB0_2 Depth 2
# Child Loop BB0_3 Depth 3
movl $inputArrayB, %edx
movq %rcx, %rsi
shlq $12, %rsi
xorl %edi, %edi
.LBB0_2: # %.preheader
# Parent Loop BB0_1 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB0_3 Depth 3
leaq (%rsi,%rdi,4), %r8
addq $outputArrayC, %r8
movl (%r8), %r9d
movq %rdx, %r10
xorl %r11d, %r11d
.LBB0_3: # Parent Loop BB0_1 Depth=1
# Parent Loop BB0_2 Depth=2
# => This Inner Loop Header: Depth=3
movl (%rax,%r11,4), %ebx
imull (%r10), %ebx
leal (%r9,%rbx,2), %r9d
incq %r11
addq $4096, %r10 # imm = 0x1000
cmpq $1024, %r11 # imm = 0x400
jne .LBB0_3
# %bb.4: # in Loop: Header=BB0_2 Depth=2
movl %r9d, (%r8)
incq %rdi
addq $4, %rdx
cmpq $1024, %rdi # imm = 0x400
jne .LBB0_2
# %bb.5: # in Loop: Header=BB0_1 Depth=1
incq %rcx
addq $4096, %rax # imm = 0x1000
cmpq $1024, %rcx # imm = 0x400
jne .LBB0_1
# %bb.6:
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z5mmultv, .Lfunc_end0-_Z5mmultv
.cfi_endproc
# -- End function
.globl _Z27__device_stub__mmult_kernelPKiS0_Pi # -- Begin function _Z27__device_stub__mmult_kernelPKiS0_Pi
.type _Z27__device_stub__mmult_kernelPKiS0_Pi,@function
_Z27__device_stub__mmult_kernelPKiS0_Pi: # @_Z27__device_stub__mmult_kernelPKiS0_Pi
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $112, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 40(%rsp), %rax
movq %rdi, (%rax)
leaq 32(%rsp), %rcx
movq %rsi, (%rcx)
leaq 24(%rsp), %rsi
movq %rdx, (%rsi)
leaq 80(%rsp), %rbx
movq %rax, (%rbx)
movq %rcx, 8(%rbx)
movq %rsi, 16(%rbx)
leaq 64(%rsp), %r14
leaq 48(%rsp), %r15
leaq 16(%rsp), %r12
leaq 8(%rsp), %r13
movq %r14, %rdi
movq %r15, %rsi
movq %r12, %rdx
movq %r13, %rcx
callq __hipPopCallConfiguration
movq (%r14), %rsi
movl 8(%r14), %edx
movq (%r15), %rcx
movl 8(%r15), %r8d
movl $_Z12mmult_kernelPKiS0_Pi, %edi
movq %rbx, %r9
pushq (%r13)
.cfi_adjust_cfa_offset 8
pushq (%r12)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $128, %rsp
.cfi_adjust_cfa_offset -128
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z27__device_stub__mmult_kernelPKiS0_Pi, .Lfunc_end1-_Z27__device_stub__mmult_kernelPKiS0_Pi
.cfi_endproc
# -- End function
.globl _Z9mmult_gpuPKiS0_Pi # -- Begin function _Z9mmult_gpuPKiS0_Pi
.type _Z9mmult_gpuPKiS0_Pi,@function
_Z9mmult_gpuPKiS0_Pi: # @_Z9mmult_gpuPKiS0_Pi
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rdx, %rbx
movq %rsi, %r14
movq %rdi, %r15
movabsq $274877907008, %rdi # imm = 0x4000000040
movabsq $68719476752, %rdx # imm = 0x1000000010
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
je .LBB2_2
# %bb.1:
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB2_2:
.cfi_def_cfa_offset 32
movq %r15, %rdi
movq %r14, %rsi
movq %rbx, %rdx
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
jmp _Z27__device_stub__mmult_kernelPKiS0_Pi # TAILCALL
.Lfunc_end2:
.size _Z9mmult_gpuPKiS0_Pi, .Lfunc_end2-_Z9mmult_gpuPKiS0_Pi
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI3_0:
.long 0x49742400 # float 1.0E+6
.text
.globl main
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $40, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $4194304, %edi # imm = 0x400000
callq _Znam
movq %rax, %rbx
movl $4194304, %edi # imm = 0x400000
callq _Znam
movq %rax, %r14
movl $4194304, %edi # imm = 0x400000
callq _Znam
movq %rax, %r15
leaq 32(%rsp), %rdi
movl $4194304, %esi # imm = 0x400000
callq hipMalloc
leaq 24(%rsp), %rdi
movl $4194304, %esi # imm = 0x400000
callq hipMalloc
leaq 16(%rsp), %rdi
movl $4194304, %esi # imm = 0x400000
callq hipMalloc
xorl %eax, %eax
movl $1024, %ecx # imm = 0x400
xorl %edx, %edx
.LBB3_1: # %.preheader87
# =>This Loop Header: Depth=1
# Child Loop BB3_2 Depth 2
movl $1024, %esi # imm = 0x400
movq %rax, %rdi
.LBB3_2: # Parent Loop BB3_1 Depth=1
# => This Inner Loop Header: Depth=2
movl %edi, (%rbx,%rdi,4)
incq %rdi
decq %rsi
jne .LBB3_2
# %bb.3: # in Loop: Header=BB3_1 Depth=1
incq %rdx
addq %rcx, %rax
cmpq %rcx, %rdx
jne .LBB3_1
# %bb.4: # %.preheader85.preheader
xorl %eax, %eax
movq %r14, %rcx
.LBB3_5: # %.preheader85
# =>This Loop Header: Depth=1
# Child Loop BB3_6 Depth 2
xorl %edx, %edx
movq %rcx, %rsi
.LBB3_6: # Parent Loop BB3_5 Depth=1
# => This Inner Loop Header: Depth=2
movl %edx, (%rsi)
addq $4, %rsi
addq $1025, %rdx # imm = 0x401
cmpq $1049600, %rdx # imm = 0x100400
jne .LBB3_6
# %bb.7: # in Loop: Header=BB3_5 Depth=1
incq %rax
addq $4096, %rcx # imm = 0x1000
cmpq $1024, %rax # imm = 0x400
jne .LBB3_5
# %bb.8: # %.preheader83.preheader
xorl %r12d, %r12d
movl $outputArrayC, %edi
movl $4194304, %edx # imm = 0x400000
xorl %esi, %esi
callq memset@PLT
movl $1024, %eax # imm = 0x400
xorl %ecx, %ecx
.LBB3_9: # %.preheader83
# =>This Loop Header: Depth=1
# Child Loop BB3_10 Depth 2
movq %r12, %rdx
xorl %esi, %esi
.LBB3_10: # Parent Loop BB3_9 Depth=1
# => This Inner Loop Header: Depth=2
movl %edx, inputArrayA(,%rdx,4)
movl %esi, inputArrayB(,%rdx,4)
addq $1025, %rsi # imm = 0x401
incq %rdx
cmpq $1049600, %rsi # imm = 0x100400
jne .LBB3_10
# %bb.11: # in Loop: Header=BB3_9 Depth=1
incq %rcx
addq %rax, %r12
cmpq %rax, %rcx
jne .LBB3_9
# %bb.12:
movq 32(%rsp), %rdi
movl $4194304, %edx # imm = 0x400000
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq 24(%rsp), %rdi
movl $4194304, %edx # imm = 0x400000
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
xorl %eax, %eax
movl $1024, %ecx # imm = 0x400
xorl %edx, %edx
.LBB3_13: # %.preheader82
# =>This Loop Header: Depth=1
# Child Loop BB3_14 Depth 2
movq %rax, %rsi
xorl %edi, %edi
.LBB3_14: # Parent Loop BB3_13 Depth=1
# => This Inner Loop Header: Depth=2
movl %esi, inputArrayA(,%rsi,4)
movl %edi, inputArrayB(,%rsi,4)
addq $1025, %rdi # imm = 0x401
incq %rsi
cmpq $1049600, %rdi # imm = 0x100400
jne .LBB3_14
# %bb.15: # in Loop: Header=BB3_13 Depth=1
incq %rdx
addq %rcx, %rax
cmpq %rcx, %rdx
jne .LBB3_13
# %bb.16:
callq clock
movq %rax, %r12
callq _Z5mmultv
callq clock
subq %r12, %rax
cvtsi2ss %rax, %xmm0
divss .LCPI3_0(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
callq clock
movq %rax, %r12
movq 32(%rsp), %rdi
movq 24(%rsp), %rsi
movq 16(%rsp), %rdx
callq _Z9mmult_gpuPKiS0_Pi
callq hipDeviceSynchronize
movq 16(%rsp), %rsi
movl $4194304, %edx # imm = 0x400000
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
callq clock
subq %r12, %rax
xorps %xmm0, %xmm0
cvtsi2ss %rax, %xmm0
divss .LCPI3_0(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movl $.L.str.1, %edi
movb $1, %al
callq printf
movl $outputArrayC, %eax
xorl %ecx, %ecx
# implicit-def: $xmm1
.LBB3_17: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB3_18 Depth 2
xorl %edx, %edx
.LBB3_18: # Parent Loop BB3_17 Depth=1
# => This Inner Loop Header: Depth=2
xorps %xmm0, %xmm0
cvtsi2sdl (%rax,%rdx,4), %xmm0
addsd %xmm0, %xmm1
incq %rdx
cmpq $1024, %rdx # imm = 0x400
jne .LBB3_18
# %bb.19: # in Loop: Header=BB3_17 Depth=1
incq %rcx
addq $4096, %rax # imm = 0x1000
cmpq $1024, %rcx # imm = 0x400
jne .LBB3_17
# %bb.20:
movl $_ZSt4cout, %edi
movl $.L.str.2, %esi
movl $15, %edx
movsd %xmm1, 8(%rsp) # 8-byte Spill
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movsd 8(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
callq _ZNSo9_M_insertIdEERSoT_
movq %rax, %r12
movq (%rax), %rax
movq -24(%rax), %rdi
addq %r12, %rdi
movl $10, %esi
callq _ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
movsbl %al, %esi
movq %r12, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
xorl %eax, %eax
# implicit-def: $xmm1
.LBB3_21: # =>This Inner Loop Header: Depth=1
xorps %xmm0, %xmm0
cvtsi2sdl (%r15,%rax,4), %xmm0
addsd %xmm0, %xmm1
incq %rax
cmpq $1048576, %rax # imm = 0x100000
jne .LBB3_21
# %bb.22:
movl $_ZSt4cout, %edi
movl $.L.str.3, %esi
movl $15, %edx
movsd %xmm1, 8(%rsp) # 8-byte Spill
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movsd 8(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
callq _ZNSo9_M_insertIdEERSoT_
movq %rax, %r12
movq (%rax), %rax
movq -24(%rax), %rdi
addq %r12, %rdi
movl $10, %esi
callq _ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
movsbl %al, %esi
movq %r12, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq 16(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
movq 32(%rsp), %rdi
callq hipFree
movq %r15, %rdi
callq _ZdaPv
movq %r14, %rdi
callq _ZdaPv
movq %rbx, %rdi
callq _ZdaPv
xorl %eax, %eax
addq $40, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, %rdi
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12mmult_kernelPKiS0_Pi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type inputArrayA,@object # @inputArrayA
.bss
.globl inputArrayA
.p2align 4, 0x0
inputArrayA:
.zero 4194304
.size inputArrayA, 4194304
.type inputArrayB,@object # @inputArrayB
.globl inputArrayB
.p2align 4, 0x0
inputArrayB:
.zero 4194304
.size inputArrayB, 4194304
.type outputArrayC,@object # @outputArrayC
.globl outputArrayC
.p2align 4, 0x0
outputArrayC:
.zero 4194304
.size outputArrayC, 4194304
.type _Z12mmult_kernelPKiS0_Pi,@object # @_Z12mmult_kernelPKiS0_Pi
.section .rodata,"a",@progbits
.globl _Z12mmult_kernelPKiS0_Pi
.p2align 3, 0x0
_Z12mmult_kernelPKiS0_Pi:
.quad _Z27__device_stub__mmult_kernelPKiS0_Pi
.size _Z12mmult_kernelPKiS0_Pi, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Run time on CPU: %lf sec\n"
.size .L.str, 26
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Run time on GPU: %lf sec\n"
.size .L.str.1, 26
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "totalSum_cpu = "
.size .L.str.2, 16
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "totalSum_gpu = "
.size .L.str.3, 16
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z12mmult_kernelPKiS0_Pi"
.size .L__unnamed_1, 25
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z27__device_stub__mmult_kernelPKiS0_Pi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z12mmult_kernelPKiS0_Pi
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
```
| 5,876 | 7,281 |
578 |
Convert the following CUDA device assembly code to AMD device assembly:
```cudaasm
code for sm_80
Function : _Z21multiply_const_kernelP6float2S0_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
MOV R1, c[0x0][0x28] ;
S2R R4, SR_CTAID.X ;
S2R R3, SR_TID.X ;
IMAD R4, R4, c[0x0][0x0], R3 ;
ISETP.GE.AND P0, PT, R4, c[0x0][0x178], PT ;
@P0 EXIT ;
HFMA2.MMA R5, -RZ, RZ, 0, 4.76837158203125e-07 ;
ULDC.64 UR4, c[0x0][0x118] ;
IMAD.WIDE R2, R4, R5, c[0x0][0x160] ;
LDG.E.64 R2, [R2.64] ;
IMAD.WIDE R4, R4, R5, c[0x0][0x168] ;
FMUL R9, R3.reuse, c[0x0][0x170] ;
FMUL R7, R3, c[0x0][0x174] ;
FFMA R9, R2.reuse, c[0x0][0x174], R9 ;
FFMA R8, R2, c[0x0][0x170], -R7 ;
STG.E.64 [R4.64], R8 ;
EXIT ;
BRA 0x110;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
```
|
```amdasm
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z21multiply_const_kernelP15HIP_vector_typeIfLj2EES1_S0_i ; -- Begin function _Z21multiply_const_kernelP15HIP_vector_typeIfLj2EES1_S0_i
.globl _Z21multiply_const_kernelP15HIP_vector_typeIfLj2EES1_S0_i
.p2align 8
.type _Z21multiply_const_kernelP15HIP_vector_typeIfLj2EES1_S0_i,@function
_Z21multiply_const_kernelP15HIP_vector_typeIfLj2EES1_S0_i: ; @_Z21multiply_const_kernelP15HIP_vector_typeIfLj2EES1_S0_i
; %bb.0:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
; %bb.1:
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 3, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
global_load_b64 v[2:3], v[2:3], off
s_waitcnt vmcnt(0)
v_mul_f32_e32 v4, s0, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_mul_f32 v5, s1, v3 :: v_dual_fmac_f32 v4, s1, v2
v_fma_f32 v3, s0, v2, -v5
global_store_b64 v[0:1], v[3:4], off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z21multiply_const_kernelP15HIP_vector_typeIfLj2EES1_S0_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z21multiply_const_kernelP15HIP_vector_typeIfLj2EES1_S0_i, .Lfunc_end0-_Z21multiply_const_kernelP15HIP_vector_typeIfLj2EES1_S0_i
; -- End function
.section .AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 180
; NumSgprs: 18
; NumVgprs: 6
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 6
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object ; @__hip_cuid_
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0 ; 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 8
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z21multiply_const_kernelP15HIP_vector_typeIfLj2EES1_S0_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z21multiply_const_kernelP15HIP_vector_typeIfLj2EES1_S0_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
```
| 447 | 2,740 |
579 |
Convert the following CUDA host assembly code to AMD host assembly:
```cudaasm
.file "tmpxft_0015bc8d_00000000-6_multiply_const.cudafe1.cpp"
.text
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z33get_block_and_grid_multiply_constPiS_
.type _Z33get_block_and_grid_multiply_constPiS_, @function
_Z33get_block_and_grid_multiply_constPiS_:
.LFB2051:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $232, %rsp
.cfi_def_cfa_offset 288
movq %fs:40, %rax
movq %rax, 216(%rsp)
xorl %eax, %eax
testq %rdi, %rdi
je .L3
movq %rdi, %rbx
movq %rsi, %rbp
testq %rsi, %rsi
je .L3
leaq 40(%rsp), %rdi
call cudaGetDevice@PLT
testl %eax, %eax
je .L14
.L3:
movq 216(%rsp), %rax
subq %fs:40, %rax
jne .L15
addq $232, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
leaq 44(%rsp), %rdi
movl 40(%rsp), %edx
movl $39, %esi
call cudaDeviceGetAttribute@PLT
testl %eax, %eax
jne .L3
leaq 48(%rsp), %rdi
movl 40(%rsp), %edx
movl $10, %esi
call cudaDeviceGetAttribute@PLT
testl %eax, %eax
jne .L3
leaq 52(%rsp), %rdi
movl 40(%rsp), %edx
movl $1, %esi
call cudaDeviceGetAttribute@PLT
testl %eax, %eax
jne .L3
leaq 56(%rsp), %rdi
movl 40(%rsp), %edx
movl $16, %esi
call cudaDeviceGetAttribute@PLT
testl %eax, %eax
jne .L3
leaq 64(%rsp), %rdi
leaq _Z21multiply_const_kernelP6float2S0_S_i(%rip), %rsi
call cudaFuncGetAttributes@PLT
testl %eax, %eax
jne .L3
movl 44(%rsp), %esi
movl 48(%rsp), %ecx
movl 88(%rsp), %r14d
movl 52(%rsp), %eax
cmpl %eax, %r14d
cmovg %eax, %r14d
leal -1(%rcx,%r14), %eax
cltd
idivl %ecx
imull %ecx, %eax
movl %eax, %r12d
testl %eax, %eax
jle .L9
movl $0, 8(%rsp)
movl $0, 12(%rsp)
movl $0, %r15d
movl %ecx, %r13d
movq %rbx, 16(%rsp)
movq %rbp, 24(%rsp)
movl %esi, %ebp
jmp .L7
.L6:
cmpl %r15d, %ebp
je .L12
subl %r13d, %r12d
testl %r12d, %r12d
jle .L16
.L7:
cmpl %r12d, %r14d
movl %r12d, %ebx
cmovle %r14d, %ebx
leaq 60(%rsp), %rdi
movl $0, %r8d
movl $0, %ecx
movl %ebx, %edx
leaq _Z21multiply_const_kernelP6float2S0_S_i(%rip), %rsi
call cudaOccupancyMaxActiveBlocksPerMultiprocessorWithFlags@PLT
testl %eax, %eax
jne .L3
movl 60(%rsp), %eax
movl %ebx, %edx
imull %eax, %edx
cmpl %r15d, %edx
jle .L6
movl %edx, %r15d
movl %eax, 8(%rsp)
movl %ebx, 12(%rsp)
jmp .L6
.L16:
movq 16(%rsp), %rbx
movq 24(%rsp), %rbp
jmp .L5
.L9:
movl $0, 8(%rsp)
movl $0, 12(%rsp)
jmp .L5
.L12:
movq 16(%rsp), %rbx
movq 24(%rsp), %rbp
.L5:
movl 8(%rsp), %eax
imull 56(%rsp), %eax
movl %eax, (%rbx)
movl 12(%rsp), %eax
movl %eax, 0(%rbp)
jmp .L3
.L15:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z33get_block_and_grid_multiply_constPiS_, .-_Z33get_block_and_grid_multiply_constPiS_
.globl _Z53__device_stub__Z21multiply_const_kernelP6float2S0_S_iP6float2S0_RS_i
.type _Z53__device_stub__Z21multiply_const_kernelP6float2S0_S_iP6float2S0_RS_i, @function
_Z53__device_stub__Z21multiply_const_kernelP6float2S0_S_iP6float2S0_RS_i:
.LFB2076:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %ecx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
movq %rdx, 112(%rsp)
leaq 12(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L21
.L17:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L22
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L21:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z21multiply_const_kernelP6float2S0_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L17
.L22:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2076:
.size _Z53__device_stub__Z21multiply_const_kernelP6float2S0_S_iP6float2S0_RS_i, .-_Z53__device_stub__Z21multiply_const_kernelP6float2S0_S_iP6float2S0_RS_i
.globl _Z21multiply_const_kernelP6float2S0_S_i
.type _Z21multiply_const_kernelP6float2S0_S_i, @function
_Z21multiply_const_kernelP6float2S0_S_i:
.LFB2077:
.cfi_startproc
endbr64
subq $24, %rsp
.cfi_def_cfa_offset 32
movq %xmm0, 8(%rsp)
movl %edx, %ecx
leaq 8(%rsp), %rdx
call _Z53__device_stub__Z21multiply_const_kernelP6float2S0_S_iP6float2S0_RS_i
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2077:
.size _Z21multiply_const_kernelP6float2S0_S_i, .-_Z21multiply_const_kernelP6float2S0_S_i
.globl _Z19exec_multiply_constP6float2S0_S_iiiP11CUstream_st
.type _Z19exec_multiply_constP6float2S0_S_iiiP11CUstream_st, @function
_Z19exec_multiply_constP6float2S0_S_iiiP11CUstream_st:
.LFB2050:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $56, %rsp
.cfi_def_cfa_offset 96
movq %rdi, %rbx
movq %rsi, %rbp
movq %xmm0, %r13
movl %edx, %r12d
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movl %r8d, 28(%rsp)
movl $1, 32(%rsp)
movl %ecx, 16(%rsp)
movl $1, 20(%rsp)
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L29
.L25:
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L30
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L29:
.cfi_restore_state
movq %r13, 8(%rsp)
leaq 8(%rsp), %rdx
movl %r12d, %ecx
movq %rbp, %rsi
movq %rbx, %rdi
call _Z53__device_stub__Z21multiply_const_kernelP6float2S0_S_iP6float2S0_RS_i
jmp .L25
.L30:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2050:
.size _Z19exec_multiply_constP6float2S0_S_iiiP11CUstream_st, .-_Z19exec_multiply_constP6float2S0_S_iiiP11CUstream_st
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z21multiply_const_kernelP6float2S0_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2079:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z21multiply_const_kernelP6float2S0_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2079:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
```
|
```amdasm
.text
.file "multiply_const.hip"
.globl _Z36__device_stub__multiply_const_kernelP15HIP_vector_typeIfLj2EES1_S0_i # -- Begin function _Z36__device_stub__multiply_const_kernelP15HIP_vector_typeIfLj2EES1_S0_i
.type _Z36__device_stub__multiply_const_kernelP15HIP_vector_typeIfLj2EES1_S0_i,@function
_Z36__device_stub__multiply_const_kernelP15HIP_vector_typeIfLj2EES1_S0_i: # @_Z36__device_stub__multiply_const_kernelP15HIP_vector_typeIfLj2EES1_S0_i
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $112, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 40(%rsp), %rax
movsd %xmm0, (%rax)
leaq 32(%rsp), %rcx
movq %rdi, (%rcx)
leaq 24(%rsp), %rdi
movq %rsi, (%rdi)
leaq 4(%rsp), %rsi
movl %edx, (%rsi)
leaq 80(%rsp), %rbx
movq %rcx, (%rbx)
movq %rdi, 8(%rbx)
movq %rax, 16(%rbx)
movq %rsi, 24(%rbx)
leaq 64(%rsp), %r14
leaq 48(%rsp), %r15
leaq 16(%rsp), %r12
leaq 8(%rsp), %r13
movq %r14, %rdi
movq %r15, %rsi
movq %r12, %rdx
movq %r13, %rcx
callq __hipPopCallConfiguration
movq (%r14), %rsi
movl 8(%r14), %edx
movq (%r15), %rcx
movl 8(%r15), %r8d
movl $_Z21multiply_const_kernelP15HIP_vector_typeIfLj2EES1_S0_i, %edi
movq %rbx, %r9
pushq (%r13)
.cfi_adjust_cfa_offset 8
pushq (%r12)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $128, %rsp
.cfi_adjust_cfa_offset -128
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z36__device_stub__multiply_const_kernelP15HIP_vector_typeIfLj2EES1_S0_i, .Lfunc_end0-_Z36__device_stub__multiply_const_kernelP15HIP_vector_typeIfLj2EES1_S0_i
.cfi_endproc
# -- End function
.globl _Z19exec_multiply_constP15HIP_vector_typeIfLj2EES1_S0_iiiP12ihipStream_t # -- Begin function _Z19exec_multiply_constP15HIP_vector_typeIfLj2EES1_S0_iiiP12ihipStream_t
.type _Z19exec_multiply_constP15HIP_vector_typeIfLj2EES1_S0_iiiP12ihipStream_t,@function
_Z19exec_multiply_constP15HIP_vector_typeIfLj2EES1_S0_iiiP12ihipStream_t: # @_Z19exec_multiply_constP15HIP_vector_typeIfLj2EES1_S0_iiiP12ihipStream_t
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $16, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl %edx, %ebx
movsd %xmm0, 8(%rsp) # 8-byte Spill
movq %rsi, %r14
movq %rdi, %r15
movl %ecx, %edi
btsq $32, %rdi
movl %r8d, %edx
btsq $32, %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
callq __hipPushCallConfiguration
testl %eax, %eax
je .LBB1_2
# %bb.1:
addq $16, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB1_2:
.cfi_def_cfa_offset 48
movq %r15, %rdi
movq %r14, %rsi
movsd 8(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
movl %ebx, %edx
addq $16, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
jmp _Z36__device_stub__multiply_const_kernelP15HIP_vector_typeIfLj2EES1_S0_i # TAILCALL
.Lfunc_end1:
.size _Z19exec_multiply_constP15HIP_vector_typeIfLj2EES1_S0_iiiP12ihipStream_t, .Lfunc_end1-_Z19exec_multiply_constP15HIP_vector_typeIfLj2EES1_S0_iiiP12ihipStream_t
.cfi_endproc
# -- End function
.globl _Z33get_block_and_grid_multiply_constPiS_ # -- Begin function _Z33get_block_and_grid_multiply_constPiS_
.type _Z33get_block_and_grid_multiply_constPiS_,@function
_Z33get_block_and_grid_multiply_constPiS_: # @_Z33get_block_and_grid_multiply_constPiS_
.cfi_startproc
# %bb.0:
movl $_Z21multiply_const_kernelP15HIP_vector_typeIfLj2EES1_S0_i, %edx
xorl %ecx, %ecx
xorl %r8d, %r8d
jmp hipOccupancyMaxPotentialBlockSize # TAILCALL
.Lfunc_end2:
.size _Z33get_block_and_grid_multiply_constPiS_, .Lfunc_end2-_Z33get_block_and_grid_multiply_constPiS_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, %rdi
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z21multiply_const_kernelP15HIP_vector_typeIfLj2EES1_S0_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z21multiply_const_kernelP15HIP_vector_typeIfLj2EES1_S0_i,@object # @_Z21multiply_const_kernelP15HIP_vector_typeIfLj2EES1_S0_i
.section .rodata,"a",@progbits
.globl _Z21multiply_const_kernelP15HIP_vector_typeIfLj2EES1_S0_i
.p2align 3, 0x0
_Z21multiply_const_kernelP15HIP_vector_typeIfLj2EES1_S0_i:
.quad _Z36__device_stub__multiply_const_kernelP15HIP_vector_typeIfLj2EES1_S0_i
.size _Z21multiply_const_kernelP15HIP_vector_typeIfLj2EES1_S0_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z21multiply_const_kernelP15HIP_vector_typeIfLj2EES1_S0_i"
.size .L__unnamed_1, 58
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z36__device_stub__multiply_const_kernelP15HIP_vector_typeIfLj2EES1_S0_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z21multiply_const_kernelP15HIP_vector_typeIfLj2EES1_S0_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
```
| 4,371 | 3,318 |
582 |
Convert the following CUDA device assembly code to AMD device assembly:
```cudaasm
code for sm_80
Function : _Z21calc_reduce_meanshiftiPfS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
MOV R1, c[0x0][0x28] ;
S2R R8, SR_CTAID.X ;
ULDC.64 UR6, c[0x0][0x118] ;
BSSY B0, 0x160 ;
HFMA2.MMA R6, -RZ, RZ, 0, 0 ;
S2R R9, SR_TID.X ;
IMAD R0, R8, c[0x0][0x0], R9 ;
ISETP.GE.AND P0, PT, R0, c[0x0][0x160], PT ;
@P0 BRA 0x150 ;
IMAD.MOV.U32 R6, RZ, RZ, RZ ;
MOV R5, 0x4 ;
IMAD.WIDE R2, R0, R5, c[0x0][0x168] ;
IMAD.WIDE R4, R0, R5, c[0x0][0x170] ;
LDG.E R3, [R2.64] ;
LDG.E R4, [R4.64] ;
IMAD.MOV.U32 R7, RZ, RZ, c[0x0][0x0] ;
IMAD R0, R7, c[0x0][0xc], R0 ;
ISETP.GE.AND P0, PT, R0, c[0x0][0x160], PT ;
FADD R7, -R4, R3 ;
FFMA R6, R7, R7, R6 ;
@!P0 BRA 0xa0 ;
BSYNC B0 ;
ULDC UR4, c[0x0][0x0] ;
STS [R9.X4], R6 ;
USHF.R.U32.HI UR4, URZ, 0x1, UR4 ;
BAR.SYNC.DEFER_BLOCKING 0x0 ;
ISETP.NE.AND P0, PT, R9, RZ, PT ;
ISETP.NE.AND P1, PT, RZ, UR4, PT ;
@!P1 BRA 0x290 ;
SHF.L.U32 R0, R9, 0x2, RZ ;
IMAD.U32 R3, RZ, RZ, UR4 ;
ISETP.GE.AND P1, PT, R9, R3, PT ;
@!P1 LEA R2, R3, R0, 0x2 ;
@!P1 LDS R4, [R9.X4] ;
SHF.R.U32.HI R3, RZ, 0x1, R3 ;
@!P1 LDS R5, [R2] ;
@!P1 FADD R4, R4, R5 ;
@!P1 STS [R9.X4], R4 ;
BAR.SYNC.DEFER_BLOCKING 0x0 ;
ISETP.NE.AND P1, PT, R3, RZ, PT ;
@P1 BRA 0x1f0 ;
@P0 EXIT ;
LDS R5, [RZ] ;
IMAD.MOV.U32 R3, RZ, RZ, 0x4 ;
IMAD.WIDE.U32 R2, R8, R3, c[0x0][0x178] ;
STG.E [R2.64], R5 ;
EXIT ;
BRA 0x2f0;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
Function : _Z9copy_to_yiPfS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
MOV R1, c[0x0][0x28] ;
S2R R0, SR_CTAID.X ;
HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ;
ULDC.64 UR4, c[0x0][0x118] ;
S2R R3, SR_TID.X ;
IMAD R0, R0, c[0x0][0x0], R3 ;
IMAD.WIDE R2, R0, R5, c[0x0][0x170] ;
LDG.E R3, [R2.64] ;
MOV R7, c[0x0][0x160] ;
IMAD R4, R0, R7, c[0x0][0x178] ;
IMAD.WIDE R4, R4, R5, c[0x0][0x168] ;
STG.E [R4.64], R3 ;
EXIT ;
BRA 0xd0;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
Function : _Z16kernel_Dvec_multiiPfS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
MOV R1, c[0x0][0x28] ;
S2R R0, SR_CTAID.X ;
HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ;
MOV R4, c[0x0][0x164] ;
ULDC.64 UR4, c[0x0][0x118] ;
S2R R3, SR_CTAID.Y ;
S2R R2, SR_TID.Y ;
S2R R5, SR_TID.X ;
IMAD R3, R3, c[0x0][0x4], R2 ;
IMAD R0, R0, c[0x0][0x0], R5 ;
IMAD R4, R3, R4, c[0x0][0x180] ;
IMAD R0, R0, c[0x0][0x160], R3 ;
IMAD.WIDE R4, R4, R7, c[0x0][0x170] ;
IMAD.WIDE R2, R0.reuse, R7.reuse, c[0x0][0x168] ;
LDG.E R5, [R4.64] ;
LDG.E R2, [R2.64] ;
IMAD.WIDE R6, R0, R7, c[0x0][0x178] ;
FMUL R9, R2, R5 ;
STG.E [R6.64], R9 ;
EXIT ;
BRA 0x140;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
Function : _Z14kernel_sum_diviPfS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ;
S2R R6, SR_CTAID.X ;
IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x160] ;
S2R R3, SR_TID.X ;
ISETP.GE.AND P0, PT, R0, 0x1, PT ;
@!P0 EXIT ;
IADD3 R2, R0, -0x1, RZ ;
IMAD.MOV.U32 R5, RZ, RZ, 0x4 ;
ULDC.64 UR4, c[0x0][0x118] ;
IMAD R6, R6, c[0x0][0x0], R3 ;
ISETP.GE.U32.AND P0, PT, R2, 0x3, PT ;
IMAD.MOV.U32 R9, RZ, RZ, RZ ;
LOP3.LUT R0, R0, 0x3, RZ, 0xc0, !PT ;
IMAD.WIDE R2, R6, R5, c[0x0][0x170] ;
@!P0 BRA 0x5b0 ;
IMAD R4, R6, c[0x0][0x160], RZ ;
IADD3 R7, -R0, c[0x0][0x160], RZ ;
IMAD.MOV.U32 R9, RZ, RZ, RZ ;
IMAD.WIDE R4, R4, R5, c[0x0][0x168] ;
LDG.E R8, [R2.64] ;
LDG.E R14, [R4.64] ;
IADD3 R7, R7, -0x4, RZ ;
BSSY B0, 0x250 ;
ISETP.NE.AND P2, PT, R7, RZ, PT ;
MUFU.RCP R11, R8 ;
FCHK P0, R14, R8 ;
FFMA R10, -R8, R11, 1 ;
FFMA R10, R11, R10, R11 ;
FFMA R11, R14, R10, RZ ;
FFMA R12, -R8, R11, R14 ;
FFMA R11, R10, R12, R11 ;
@!P0 BRA 0x240 ;
IMAD.MOV.U32 R13, RZ, RZ, R8 ;
MOV R8, 0x230 ;
CALL.REL.NOINC 0x770 ;
IMAD.MOV.U32 R11, RZ, RZ, R13 ;
BSYNC B0 ;
STG.E [R4.64], R11 ;
LDG.E R8, [R2.64] ;
LDG.E R14, [R4.64+0x4] ;
BSSY B0, 0x350 ;
MUFU.RCP R13, R8 ;
FCHK P0, R14, R8 ;
FFMA R10, -R8, R13, 1 ;
FFMA R10, R13, R10, R13 ;
FFMA R13, R14, R10, RZ ;
FFMA R12, -R8, R13, R14 ;
FFMA R13, R10, R12, R13 ;
@!P0 BRA 0x340 ;
IMAD.MOV.U32 R13, RZ, RZ, R8 ;
MOV R8, 0x340 ;
CALL.REL.NOINC 0x770 ;
BSYNC B0 ;
STG.E [R4.64+0x4], R13 ;
LDG.E R8, [R2.64] ;
LDG.E R14, [R4.64+0x8] ;
BSSY B0, 0x460 ;
MUFU.RCP R11, R8 ;
FCHK P0, R14, R8 ;
FFMA R10, -R8, R11, 1 ;
FFMA R10, R11, R10, R11 ;
FFMA R11, R14, R10, RZ ;
FFMA R12, -R8, R11, R14 ;
FFMA R11, R10, R12, R11 ;
@!P0 BRA 0x450 ;
IMAD.MOV.U32 R13, RZ, RZ, R8 ;
MOV R8, 0x440 ;
CALL.REL.NOINC 0x770 ;
MOV R11, R13 ;
BSYNC B0 ;
STG.E [R4.64+0x8], R11 ;
LDG.E R8, [R2.64] ;
LDG.E R14, [R4.64+0xc] ;
BSSY B0, 0x560 ;
MUFU.RCP R13, R8 ;
FCHK P0, R14, R8 ;
FFMA R10, -R8, R13, 1 ;
FFMA R10, R13, R10, R13 ;
FFMA R13, R14, R10, RZ ;
FFMA R12, -R8, R13, R14 ;
FFMA R13, R10, R12, R13 ;
@!P0 BRA 0x550 ;
IMAD.MOV.U32 R13, RZ, RZ, R8 ;
MOV R8, 0x550 ;
CALL.REL.NOINC 0x770 ;
BSYNC B0 ;
STG.E [R4.64+0xc], R13 ;
IADD3 R9, R9, 0x4, RZ ;
IADD3 R4, P0, R4, 0x10, RZ ;
IMAD.X R5, RZ, RZ, R5, P0 ;
@P2 BRA 0x130 ;
ISETP.NE.AND P0, PT, R0, RZ, PT ;
@!P0 EXIT ;
IMAD.MOV.U32 R5, RZ, RZ, 0x4 ;
IMAD R4, R6, c[0x0][0x160], R9 ;
IMAD.WIDE R4, R4, R5, c[0x0][0x168] ;
LDG.E R6, [R2.64] ;
LDG.E R14, [R4.64] ;
BSSY B0, 0x700 ;
MUFU.RCP R7, R6 ;
FCHK P0, R14, R6 ;
FFMA R8, -R6, R7, 1 ;
FFMA R8, R7, R8, R7 ;
FFMA R7, R14, R8, RZ ;
FFMA R9, -R6, R7, R14 ;
FFMA R7, R8, R9, R7 ;
@!P0 BRA 0x6f0 ;
IMAD.MOV.U32 R13, RZ, RZ, R6 ;
MOV R8, 0x6e0 ;
CALL.REL.NOINC 0x770 ;
IMAD.MOV.U32 R7, RZ, RZ, R13 ;
BSYNC B0 ;
IADD3 R0, R0, -0x1, RZ ;
STG.E [R4.64], R7 ;
ISETP.NE.AND P0, PT, R0, RZ, PT ;
IADD3 R4, P1, R4, 0x4, RZ ;
IMAD.X R5, RZ, RZ, R5, P1 ;
@P0 BRA 0x600 ;
EXIT ;
SHF.R.U32.HI R12, RZ, 0x17, R13 ;
BSSY B1, 0xdc0 ;
SHF.R.U32.HI R10, RZ, 0x17, R14 ;
LOP3.LUT R12, R12, 0xff, RZ, 0xc0, !PT ;
LOP3.LUT R15, R10, 0xff, RZ, 0xc0, !PT ;
IADD3 R17, R12, -0x1, RZ ;
IADD3 R16, R15, -0x1, RZ ;
ISETP.GT.U32.AND P0, PT, R17, 0xfd, PT ;
MOV R10, R14 ;
ISETP.GT.U32.OR P0, PT, R16, 0xfd, P0 ;
@!P0 IMAD.MOV.U32 R11, RZ, RZ, RZ ;
@!P0 BRA 0x9a0 ;
FSETP.GTU.FTZ.AND P0, PT, |R14|, +INF , PT ;
FSETP.GTU.FTZ.AND P1, PT, |R13|, +INF , PT ;
PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ;
@P0 BRA 0xda0 ;
LOP3.LUT P0, RZ, R13, 0x7fffffff, R10, 0xc8, !PT ;
@!P0 BRA 0xd80 ;
FSETP.NEU.FTZ.AND P3, PT, |R14|.reuse, +INF , PT ;
FSETP.NEU.FTZ.AND P1, PT, |R13|, +INF , PT ;
FSETP.NEU.FTZ.AND P0, PT, |R14|, +INF , PT ;
@!P1 BRA !P3, 0xd80 ;
LOP3.LUT P3, RZ, R10, 0x7fffffff, RZ, 0xc0, !PT ;
PLOP3.LUT P1, PT, P1, P3, PT, 0x2a, 0x0 ;
@P1 BRA 0xd60 ;
LOP3.LUT P1, RZ, R13, 0x7fffffff, RZ, 0xc0, !PT ;
PLOP3.LUT P0, PT, P0, P1, PT, 0x2a, 0x0 ;
@P0 BRA 0xd30 ;
ISETP.GE.AND P0, PT, R16, RZ, PT ;
ISETP.GE.AND P1, PT, R17, RZ, PT ;
@P0 IMAD.MOV.U32 R11, RZ, RZ, RZ ;
@!P0 IMAD.MOV.U32 R11, RZ, RZ, -0x40 ;
@!P0 FFMA R10, R14, 1.84467440737095516160e+19, RZ ;
@!P1 FFMA R13, R13, 1.84467440737095516160e+19, RZ ;
@!P1 IADD3 R11, R11, 0x40, RZ ;
LEA R14, R12, 0xc0800000, 0x17 ;
BSSY B2, 0xd20 ;
IADD3 R15, R15, -0x7f, RZ ;
IMAD.IADD R14, R13, 0x1, -R14 ;
IMAD R10, R15.reuse, -0x800000, R10 ;
MUFU.RCP R13, R14 ;
FADD.FTZ R17, -R14, -RZ ;
IADD3 R14, R15, 0x7f, -R12 ;
IMAD.IADD R11, R14, 0x1, R11 ;
FFMA R16, R13, R17, 1 ;
FFMA R13, R13, R16, R13 ;
FFMA R16, R10, R13, RZ ;
FFMA R18, R17, R16, R10 ;
FFMA R18, R13, R18, R16 ;
FFMA R17, R17, R18, R10 ;
FFMA R10, R13, R17, R18 ;
SHF.R.U32.HI R12, RZ, 0x17, R10 ;
LOP3.LUT R12, R12, 0xff, RZ, 0xc0, !PT ;
IMAD.IADD R15, R12, 0x1, R11 ;
IADD3 R12, R15, -0x1, RZ ;
ISETP.GE.U32.AND P0, PT, R12, 0xfe, PT ;
@!P0 BRA 0xd00 ;
ISETP.GT.AND P0, PT, R15, 0xfe, PT ;
@P0 BRA 0xcd0 ;
ISETP.GE.AND P0, PT, R15, 0x1, PT ;
@P0 BRA 0xd10 ;
ISETP.GE.AND P0, PT, R15, -0x18, PT ;
LOP3.LUT R10, R10, 0x80000000, RZ, 0xc0, !PT ;
@!P0 BRA 0xd10 ;
FFMA.RZ R11, R13, R17.reuse, R18.reuse ;
ISETP.NE.AND P3, PT, R15, RZ, PT ;
FFMA.RM R12, R13, R17.reuse, R18.reuse ;
ISETP.NE.AND P1, PT, R15, RZ, PT ;
LOP3.LUT R14, R11, 0x7fffff, RZ, 0xc0, !PT ;
FFMA.RP R11, R13, R17, R18 ;
IADD3 R13, R15.reuse, 0x20, RZ ;
LOP3.LUT R14, R14, 0x800000, RZ, 0xfc, !PT ;
IADD3 R15, -R15, RZ, RZ ;
SHF.L.U32 R13, R14, R13, RZ ;
FSETP.NEU.FTZ.AND P0, PT, R11, R12, PT ;
SEL R11, R15, RZ, P3 ;
ISETP.NE.AND P1, PT, R13, RZ, P1 ;
SHF.R.U32.HI R11, RZ, R11, R14 ;
PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ;
SHF.R.U32.HI R13, RZ, 0x1, R11 ;
SEL R12, RZ, 0x1, !P0 ;
LOP3.LUT R12, R12, 0x1, R13, 0xf8, !PT ;
LOP3.LUT R12, R12, R11, RZ, 0xc0, !PT ;
IMAD.IADD R13, R13, 0x1, R12 ;
LOP3.LUT R10, R13, R10, RZ, 0xfc, !PT ;
BRA 0xd10 ;
LOP3.LUT R10, R10, 0x80000000, RZ, 0xc0, !PT ;
LOP3.LUT R10, R10, 0x7f800000, RZ, 0xfc, !PT ;
BRA 0xd10 ;
IMAD R10, R11, 0x800000, R10 ;
BSYNC B2 ;
BRA 0xdb0 ;
LOP3.LUT R10, R13, 0x80000000, R10, 0x48, !PT ;
LOP3.LUT R10, R10, 0x7f800000, RZ, 0xfc, !PT ;
BRA 0xdb0 ;
LOP3.LUT R10, R13, 0x80000000, R10, 0x48, !PT ;
BRA 0xdb0 ;
MUFU.RSQ R10, -QNAN ;
BRA 0xdb0 ;
FADD.FTZ R10, R14, R13 ;
BSYNC B1 ;
IMAD.MOV.U32 R13, RZ, RZ, R10 ;
IMAD.MOV.U32 R10, RZ, RZ, R8 ;
IMAD.MOV.U32 R11, RZ, RZ, 0x0 ;
RET.REL.NODEC R10 0x0 ;
BRA 0xe00;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
Function : _Z18calc_Kernel_MatrixiiPfS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
MOV R1, c[0x0][0x28] ;
S2R R0, SR_CTAID.X ;
MOV R9, c[0x0][0x164] ;
ULDC.64 UR4, c[0x0][0x118] ;
HFMA2.MMA R14, -RZ, RZ, 0, 0 ;
S2R R3, SR_TID.X ;
ISETP.GE.AND P0, PT, R9, 0x1, PT ;
IMAD.MOV.U32 R6, RZ, RZ, RZ ;
S2R R7, SR_CTAID.Y ;
S2R R2, SR_TID.Y ;
IMAD R0, R0, c[0x0][0x0], R3 ;
IMAD R7, R7, c[0x0][0x4], R2 ;
@!P0 BRA 0xcb0 ;
IADD3 R2, R9.reuse, -0x1, RZ ;
IMAD.MOV.U32 R14, RZ, RZ, RZ ;
LOP3.LUT R9, R9, 0x3, RZ, 0xc0, !PT ;
ISETP.GE.U32.AND P0, PT, R2, 0x3, PT ;
MOV R8, RZ ;
@!P0 BRA 0xb50 ;
IADD3 R10, -R9, c[0x0][0x164], RZ ;
HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ;
IMAD R2, R0, c[0x0][0x164], RZ ;
ULDC.64 UR6, c[0x0][0x168] ;
ISETP.GT.AND P0, PT, R10, RZ, PT ;
IMAD R11, R7, c[0x0][0x164], RZ ;
MOV R8, RZ ;
IMAD.MOV.U32 R14, RZ, RZ, RZ ;
IMAD.WIDE R2, R2, R3, c[0x0][0x170] ;
@!P0 BRA 0x9a0 ;
ISETP.GT.AND P1, PT, R10, 0xc, PT ;
PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ;
@!P1 BRA 0x6c0 ;
PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ;
MOV R4, UR6 ;
IMAD.U32 R5, RZ, RZ, UR7 ;
LDG.E R13, [R2.64] ;
IMAD.WIDE R4, R11, 0x4, R4 ;
LDG.E R24, [R2.64+0x4] ;
LDG.E R12, [R4.64] ;
LDG.E R21, [R4.64+0x4] ;
LDG.E R20, [R2.64+0x8] ;
LDG.E R25, [R4.64+0x8] ;
LDG.E R22, [R2.64+0xc] ;
LDG.E R23, [R4.64+0xc] ;
LDG.E R18, [R2.64+0x10] ;
LDG.E R19, [R4.64+0x10] ;
LDG.E R16, [R2.64+0x14] ;
LDG.E R17, [R4.64+0x14] ;
LDG.E R27, [R4.64+0x3c] ;
FADD R15, -R12, R13 ;
LDG.E R12, [R2.64+0x18] ;
LDG.E R13, [R4.64+0x18] ;
FFMA R26, R15, R15, R14 ;
LDG.E R14, [R2.64+0x1c] ;
LDG.E R15, [R4.64+0x1c] ;
FADD R21, -R21, R24 ;
FADD R25, -R25, R20 ;
LDG.E R24, [R2.64+0x38] ;
FFMA R26, R21, R21, R26 ;
LDG.E R20, [R2.64+0x20] ;
FFMA R26, R25, R25, R26 ;
FADD R25, -R23, R22 ;
LDG.E R21, [R4.64+0x20] ;
FFMA R26, R25, R25, R26 ;
LDG.E R23, [R2.64+0x24] ;
FADD R25, -R19, R18 ;
LDG.E R22, [R4.64+0x24] ;
FFMA R26, R25, R25, R26 ;
FADD R25, -R17, R16 ;
LDG.E R18, [R2.64+0x28] ;
LDG.E R19, [R4.64+0x28] ;
FFMA R26, R25, R25, R26 ;
LDG.E R16, [R2.64+0x2c] ;
LDG.E R17, [R4.64+0x2c] ;
FADD R25, -R13, R12 ;
LDG.E R12, [R2.64+0x30] ;
FFMA R26, R25, R25, R26 ;
LDG.E R13, [R4.64+0x30] ;
FADD R25, -R15, R14 ;
LDG.E R14, [R2.64+0x34] ;
LDG.E R15, [R4.64+0x34] ;
FFMA R28, R25, R25, R26 ;
LDG.E R25, [R4.64+0x38] ;
LDG.E R26, [R2.64+0x3c] ;
FADD R21, -R21, R20 ;
FFMA R28, R21, R21, R28 ;
FADD R23, -R22, R23 ;
FFMA R28, R23, R23, R28 ;
FADD R19, -R19, R18 ;
IADD3 R10, R10, -0x10, RZ ;
FFMA R28, R19, R19, R28 ;
FADD R17, -R17, R16 ;
ISETP.GT.AND P1, PT, R10, 0xc, PT ;
FFMA R28, R17, R17, R28 ;
UIADD3 UR6, UP0, UR6, 0x40, URZ ;
IADD3 R2, P2, R2, 0x40, RZ ;
UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ;
IADD3.X R3, RZ, R3, RZ, P2, !PT ;
IADD3 R8, R8, 0x10, RZ ;
FADD R13, -R13, R12 ;
FFMA R28, R13, R13, R28 ;
FADD R15, -R15, R14 ;
FFMA R28, R15, R15, R28 ;
FADD R25, -R25, R24 ;
FADD R27, -R27, R26 ;
FFMA R28, R25, R25, R28 ;
FFMA R14, R27, R27, R28 ;
@P1 BRA 0x210 ;
ISETP.GT.AND P1, PT, R10, 0x4, PT ;
@!P1 BRA 0x980 ;
MOV R4, UR6 ;
IMAD.U32 R5, RZ, RZ, UR7 ;
LDG.E R28, [R2.64] ;
IMAD.WIDE R4, R11, 0x4, R4 ;
LDG.E R24, [R2.64+0x4] ;
LDG.E R27, [R4.64] ;
LDG.E R21, [R4.64+0x4] ;
LDG.E R19, [R2.64+0x8] ;
LDG.E R22, [R4.64+0x8] ;
LDG.E R17, [R2.64+0xc] ;
LDG.E R20, [R4.64+0xc] ;
LDG.E R15, [R2.64+0x10] ;
LDG.E R18, [R4.64+0x10] ;
LDG.E R13, [R2.64+0x14] ;
LDG.E R16, [R4.64+0x14] ;
LDG.E R12, [R4.64+0x18] ;
LDG.E R23, [R2.64+0x18] ;
LDG.E R26, [R4.64+0x1c] ;
LDG.E R25, [R2.64+0x1c] ;
UIADD3 UR6, UP0, UR6, 0x20, URZ ;
PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ;
IADD3 R8, R8, 0x8, RZ ;
IADD3 R10, R10, -0x8, RZ ;
IADD3 R2, P1, R2, 0x20, RZ ;
UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ;
IADD3.X R3, RZ, R3, RZ, P1, !PT ;
FADD R27, -R27, R28 ;
FFMA R14, R27, R27, R14 ;
FADD R21, -R21, R24 ;
FFMA R14, R21, R21, R14 ;
FADD R19, -R22, R19 ;
FFMA R14, R19, R19, R14 ;
FADD R17, -R20, R17 ;
FFMA R14, R17, R17, R14 ;
FADD R15, -R18, R15 ;
FFMA R14, R15, R15, R14 ;
FADD R13, -R16, R13 ;
FFMA R14, R13, R13, R14 ;
FADD R23, -R12, R23 ;
FFMA R14, R23, R23, R14 ;
FADD R25, -R26, R25 ;
FFMA R14, R25, R25, R14 ;
ISETP.NE.OR P0, PT, R10, RZ, P0 ;
@!P0 BRA 0xb50 ;
MOV R4, UR6 ;
IMAD.U32 R5, RZ, RZ, UR7 ;
LDG.E R13, [R2.64] ;
IMAD.WIDE R4, R11, 0x4, R4 ;
LDG.E R16, [R2.64+0x4] ;
LDG.E R12, [R4.64] ;
LDG.E R15, [R4.64+0x4] ;
LDG.E R18, [R2.64+0x8] ;
LDG.E R17, [R4.64+0x8] ;
LDG.E R19, [R4.64+0xc] ;
LDG.E R20, [R2.64+0xc] ;
IADD3 R10, R10, -0x4, RZ ;
ISETP.NE.AND P0, PT, R10, RZ, PT ;
UIADD3 UR6, UP0, UR6, 0x10, URZ ;
IADD3 R2, P1, R2, 0x10, RZ ;
UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ;
IADD3 R8, R8, 0x4, RZ ;
IADD3.X R3, RZ, R3, RZ, P1, !PT ;
FADD R13, -R12, R13 ;
FFMA R13, R13, R13, R14 ;
FADD R16, -R15, R16 ;
FFMA R13, R16, R16, R13 ;
FADD R18, -R17, R18 ;
FFMA R13, R18, R18, R13 ;
FADD R20, -R19, R20 ;
FFMA R14, R20, R20, R13 ;
@P0 BRA 0x9a0 ;
ISETP.NE.AND P0, PT, R9, RZ, PT ;
@!P0 BRA 0xcb0 ;
HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ;
IMAD R2, R7, c[0x0][0x164], R8.reuse ;
IMAD R4, R0, c[0x0][0x164], R8 ;
IMAD.WIDE R2, R2, R5, c[0x0][0x168] ;
IMAD.WIDE R4, R4, R5, c[0x0][0x170] ;
IMAD.MOV.U32 R8, RZ, RZ, R2 ;
MOV R13, R5 ;
MOV R2, R8 ;
IMAD.MOV.U32 R5, RZ, RZ, R13 ;
LDG.E R2, [R2.64] ;
LDG.E R5, [R4.64] ;
IADD3 R9, R9, -0x1, RZ ;
IADD3 R8, P1, R8, 0x4, RZ ;
ISETP.NE.AND P0, PT, R9, RZ, PT ;
IADD3.X R3, RZ, R3, RZ, P1, !PT ;
IADD3 R4, P2, R4, 0x4, RZ ;
IADD3.X R13, RZ, R13, RZ, P2, !PT ;
FADD R11, -R2, R5 ;
FFMA R14, R11, R11, R14 ;
@P0 BRA 0xbe0 ;
I2F R3, c[0x0][0x180] ;
BSSY B0, 0xe80 ;
FSETP.GT.AND P0, PT, R14, R3, PT ;
@P0 BRA 0xe70 ;
MUFU.RCP R2, R3 ;
FMUL R6, R14, -0.5 ;
BSSY B1, 0xdd0 ;
FCHK P0, R6, R3 ;
FFMA R5, -R3, R2, 1 ;
FFMA R5, R2, R5, R2 ;
FFMA R2, R6, R5, RZ ;
FFMA R4, -R3, R2, R6 ;
FFMA R2, R5, R4, R2 ;
@!P0 BRA 0xdc0 ;
MOV R2, 0xdb0 ;
CALL.REL.NOINC 0xed0 ;
IMAD.MOV.U32 R2, RZ, RZ, R4 ;
BSYNC B1 ;
HFMA2.MMA R3, -RZ, RZ, 0.96630859375, -0.0022525787353515625 ;
MOV R4, 0x437c0000 ;
FFMA.SAT R3, R2, R3, 0.5 ;
FFMA.RM R3, R3, R4, 12582913 ;
FADD R5, R3.reuse, -12583039 ;
IMAD.SHL.U32 R3, R3, 0x800000, RZ ;
FFMA R5, R2, 1.4426950216293334961, -R5 ;
FFMA R5, R2, 1.925963033500011079e-08, R5 ;
MUFU.EX2 R6, R5 ;
FMUL R6, R3, R6 ;
BSYNC B0 ;
HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ;
IMAD R2, R0, c[0x0][0x160], R7 ;
IMAD.WIDE R2, R2, R3, c[0x0][0x178] ;
STG.E [R2.64], R6 ;
EXIT ;
SHF.R.U32.HI R5, RZ, 0x17, R3 ;
BSSY B2, 0x1530 ;
SHF.R.U32.HI R4, RZ, 0x17, R6 ;
LOP3.LUT R5, R5, 0xff, RZ, 0xc0, !PT ;
LOP3.LUT R10, R4, 0xff, RZ, 0xc0, !PT ;
IADD3 R11, R5, -0x1, RZ ;
IADD3 R12, R10, -0x1, RZ ;
ISETP.GT.U32.AND P0, PT, R11, 0xfd, PT ;
MOV R9, R3 ;
ISETP.GT.U32.OR P0, PT, R12, 0xfd, P0 ;
@!P0 IMAD.MOV.U32 R8, RZ, RZ, RZ ;
@!P0 BRA 0x1110 ;
FSETP.GTU.FTZ.AND P0, PT, |R6|, +INF , PT ;
FSETP.GTU.FTZ.AND P1, PT, |R3|, +INF , PT ;
MOV R4, R6 ;
PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ;
@P0 BRA 0x1510 ;
LOP3.LUT P0, RZ, R9, 0x7fffffff, R6, 0xc8, !PT ;
@!P0 BRA 0x14f0 ;
FSETP.NEU.FTZ.AND P2, PT, |R4|.reuse, +INF , PT ;
FSETP.NEU.FTZ.AND P1, PT, |R3|, +INF , PT ;
FSETP.NEU.FTZ.AND P0, PT, |R4|, +INF , PT ;
@!P1 BRA !P2, 0x14f0 ;
LOP3.LUT P2, RZ, R6, 0x7fffffff, RZ, 0xc0, !PT ;
PLOP3.LUT P1, PT, P1, P2, PT, 0x2a, 0x0 ;
@P1 BRA 0x14d0 ;
LOP3.LUT P1, RZ, R9, 0x7fffffff, RZ, 0xc0, !PT ;
PLOP3.LUT P0, PT, P0, P1, PT, 0x2a, 0x0 ;
@P0 BRA 0x14a0 ;
ISETP.GE.AND P0, PT, R12, RZ, PT ;
ISETP.GE.AND P1, PT, R11, RZ, PT ;
@P0 MOV R8, RZ ;
@!P0 IMAD.MOV.U32 R8, RZ, RZ, -0x40 ;
@!P0 FFMA R6, R4, 1.84467440737095516160e+19, RZ ;
@!P1 FFMA R9, R3, 1.84467440737095516160e+19, RZ ;
@!P1 IADD3 R8, R8, 0x40, RZ ;
LEA R4, R5, 0xc0800000, 0x17 ;
BSSY B3, 0x1490 ;
IADD3 R9, -R4, R9, RZ ;
IADD3 R4, R10, -0x7f, RZ ;
MUFU.RCP R3, R9 ;
FADD.FTZ R11, -R9, -RZ ;
IADD3 R5, R4.reuse, 0x7f, -R5 ;
IMAD R6, R4, -0x800000, R6 ;
IADD3 R5, R5, R8, RZ ;
FFMA R10, R3, R11, 1 ;
FFMA R13, R3, R10, R3 ;
FFMA R3, R6, R13, RZ ;
FFMA R10, R11, R3, R6 ;
FFMA R10, R13, R10, R3 ;
FFMA R11, R11, R10, R6 ;
FFMA R3, R13, R11, R10 ;
SHF.R.U32.HI R4, RZ, 0x17, R3 ;
LOP3.LUT R4, R4, 0xff, RZ, 0xc0, !PT ;
IMAD.IADD R8, R4, 0x1, R5 ;
IADD3 R4, R8, -0x1, RZ ;
ISETP.GE.U32.AND P0, PT, R4, 0xfe, PT ;
@!P0 BRA 0x1470 ;
ISETP.GT.AND P0, PT, R8, 0xfe, PT ;
@P0 BRA 0x1440 ;
ISETP.GE.AND P0, PT, R8, 0x1, PT ;
@P0 BRA 0x1480 ;
ISETP.GE.AND P0, PT, R8, -0x18, PT ;
LOP3.LUT R3, R3, 0x80000000, RZ, 0xc0, !PT ;
@!P0 BRA 0x1480 ;
FFMA.RZ R4, R13.reuse, R11.reuse, R10.reuse ;
IADD3 R9, R8.reuse, 0x20, RZ ;
FFMA.RM R5, R13.reuse, R11.reuse, R10.reuse ;
ISETP.NE.AND P2, PT, R8, RZ, PT ;
LOP3.LUT R6, R4, 0x7fffff, RZ, 0xc0, !PT ;
FFMA.RP R4, R13, R11, R10 ;
ISETP.NE.AND P1, PT, R8, RZ, PT ;
LOP3.LUT R6, R6, 0x800000, RZ, 0xfc, !PT ;
IADD3 R8, -R8, RZ, RZ ;
SHF.L.U32 R9, R6, R9, RZ ;
FSETP.NEU.FTZ.AND P0, PT, R4, R5, PT ;
SEL R5, R8, RZ, P2 ;
ISETP.NE.AND P1, PT, R9, RZ, P1 ;
SHF.R.U32.HI R5, RZ, R5, R6 ;
PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ;
SHF.R.U32.HI R9, RZ, 0x1, R5 ;
SEL R4, RZ, 0x1, !P0 ;
LOP3.LUT R4, R4, 0x1, R9, 0xf8, !PT ;
LOP3.LUT R4, R4, R5, RZ, 0xc0, !PT ;
IADD3 R4, R9, R4, RZ ;
LOP3.LUT R3, R4, R3, RZ, 0xfc, !PT ;
BRA 0x1480 ;
LOP3.LUT R3, R3, 0x80000000, RZ, 0xc0, !PT ;
LOP3.LUT R3, R3, 0x7f800000, RZ, 0xfc, !PT ;
BRA 0x1480 ;
IMAD R3, R5, 0x800000, R3 ;
BSYNC B3 ;
BRA 0x1520 ;
LOP3.LUT R3, R9, 0x80000000, R6, 0x48, !PT ;
LOP3.LUT R3, R3, 0x7f800000, RZ, 0xfc, !PT ;
BRA 0x1520 ;
LOP3.LUT R3, R9, 0x80000000, R6, 0x48, !PT ;
BRA 0x1520 ;
MUFU.RSQ R3, -QNAN ;
BRA 0x1520 ;
FADD.FTZ R3, R4, R3 ;
BSYNC B2 ;
MOV R4, R3 ;
HFMA2.MMA R3, -RZ, RZ, 0, 0 ;
RET.REL.NODEC R2 0x0 ;
BRA 0x1560;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
Function : _Z15calc_meanshift2PfS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
MOV R1, c[0x0][0x28] ;
S2R R6, SR_CTAID.X ;
HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ;
ULDC.64 UR4, c[0x0][0x118] ;
S2R R3, SR_TID.X ;
IMAD R6, R6, c[0x0][0x0], R3 ;
IMAD.WIDE R2, R6, R7, c[0x0][0x160] ;
IMAD.WIDE R4, R6.reuse, R7.reuse, c[0x0][0x168] ;
LDG.E R2, [R2.64] ;
LDG.E R5, [R4.64] ;
IMAD.WIDE R6, R6, R7, c[0x0][0x170] ;
FADD R0, R2, -R5 ;
FMUL R9, R0, R0 ;
STG.E [R6.64], R9 ;
EXIT ;
BRA 0xf0;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
```
|
```amdasm
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z15calc_meanshift2PfS_S_ ; -- Begin function _Z15calc_meanshift2PfS_S_
.globl _Z15calc_meanshift2PfS_S_
.p2align 8
.type _Z15calc_meanshift2PfS_S_,@function
_Z15calc_meanshift2PfS_S_: ; @_Z15calc_meanshift2PfS_S_
; %bb.0:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x24
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_sub_f32_e32 v2, v2, v3
s_delay_alu instid0(VALU_DEP_1)
v_mul_f32_e32 v2, v2, v2
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z15calc_meanshift2PfS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z15calc_meanshift2PfS_S_, .Lfunc_end0-_Z15calc_meanshift2PfS_S_
; -- End function
.section .AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 160
; NumSgprs: 18
; NumVgprs: 6
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 6
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
.text
.protected _Z18calc_Kernel_MatrixiiPfS_S_i ; -- Begin function _Z18calc_Kernel_MatrixiiPfS_S_i
.globl _Z18calc_Kernel_MatrixiiPfS_S_i
.p2align 8
.type _Z18calc_Kernel_MatrixiiPfS_S_i,@function
_Z18calc_Kernel_MatrixiiPfS_S_i: ; @_Z18calc_Kernel_MatrixiiPfS_S_i
; %bb.0:
s_clause 0x3
s_load_b32 s10, s[0:1], 0x34
s_load_b64 s[8:9], s[0:1], 0x0
s_load_b64 s[2:3], s[0:1], 0x18
s_load_b128 s[4:7], s[0:1], 0x8
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_lshr_b32 s11, s10, 16
s_and_b32 s10, s10, 0xffff
s_cmp_lt_i32 s9, 1
v_mad_u64_u32 v[0:1], null, s14, s10, v[2:3]
v_mad_u64_u32 v[1:2], null, s15, s11, v[3:4]
s_cbranch_scc1 .LBB1_3
; %bb.1: ; %.lr.ph
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_mul_lo_u32 v2, v1, s9
v_mul_lo_u32 v4, v0, s9
v_mov_b32_e32 v6, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_ashrrev_i32_e32 v3, 31, v2
v_ashrrev_i32_e32 v5, 31, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[2:3], 2, v[2:3]
v_lshlrev_b64 v[4:5], 2, v[4:5]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v2, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v4, vcc_lo, s6, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v5, vcc_lo
.LBB1_2: ; =>This Inner Loop Header: Depth=1
global_load_b32 v7, v[4:5], off
global_load_b32 v8, v[2:3], off
v_add_co_u32 v2, vcc_lo, v2, 4
v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
v_add_co_u32 v4, vcc_lo, v4, 4
v_add_co_ci_u32_e32 v5, vcc_lo, 0, v5, vcc_lo
s_add_i32 s9, s9, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
s_cmp_eq_u32 s9, 0
s_waitcnt vmcnt(0)
v_sub_f32_e32 v7, v7, v8
v_fmac_f32_e32 v6, v7, v7
s_cbranch_scc0 .LBB1_2
s_branch .LBB1_4
.LBB1_3:
v_mov_b32_e32 v6, 0
.LBB1_4: ; %._crit_edge
s_load_b32 s0, s[0:1], 0x20
v_mov_b32_e32 v3, 0
s_waitcnt lgkmcnt(0)
v_cvt_f32_i32_e32 v2, s0
s_mov_b32 s0, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_ngt_f32_e32 v6, v2
s_cbranch_execz .LBB1_6
; %bb.5:
v_mul_f32_e32 v3, -0.5, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_div_scale_f32 v4, null, v2, v2, v3
v_div_scale_f32 v7, vcc_lo, v3, v2, v3
v_rcp_f32_e32 v5, v4
s_waitcnt_depctr 0xfff
v_fma_f32 v6, -v4, v5, 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v5, v6, v5
v_mul_f32_e32 v6, v7, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v8, -v4, v6, v7
v_fmac_f32_e32 v6, v8, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v4, -v4, v6, v7
v_div_fmas_f32 v4, v4, v5, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fixup_f32 v2, v4, v2, v3
v_mul_f32_e32 v3, 0x3fb8aa3b, v2
v_cmp_ngt_f32_e32 vcc_lo, 0xc2ce8ed0, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_fma_f32 v4, 0x3fb8aa3b, v2, -v3
v_rndne_f32_e32 v5, v3
v_dual_fmamk_f32 v4, v2, 0x32a5705f, v4 :: v_dual_sub_f32 v3, v3, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_f32_e32 v3, v3, v4
v_cvt_i32_f32_e32 v4, v5
v_exp_f32_e32 v3, v3
s_waitcnt_depctr 0xfff
v_ldexp_f32 v3, v3, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v3, 0, v3, vcc_lo
v_cmp_nlt_f32_e32 vcc_lo, 0x42b17218, v2
v_cndmask_b32_e32 v3, 0x7f800000, v3, vcc_lo
.LBB1_6: ; %_Z10kernel_funff.exit
s_or_b32 exec_lo, exec_lo, s0
v_mad_u64_u32 v[4:5], null, v0, s8, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v5, 31, v4
v_lshlrev_b64 v[0:1], 2, v[4:5]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_store_b32 v[0:1], v3, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z18calc_Kernel_MatrixiiPfS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z18calc_Kernel_MatrixiiPfS_S_i, .Lfunc_end1-_Z18calc_Kernel_MatrixiiPfS_S_i
; -- End function
.section .AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 556
; NumSgprs: 18
; NumVgprs: 9
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 9
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
.text
.protected _Z14kernel_sum_diviPfS_ ; -- Begin function _Z14kernel_sum_diviPfS_
.globl _Z14kernel_sum_diviPfS_
.p2align 8
.type _Z14kernel_sum_diviPfS_,@function
_Z14kernel_sum_diviPfS_: ; @_Z14kernel_sum_diviPfS_
; %bb.0:
s_load_b32 s2, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s2, 1
s_cbranch_scc1 .LBB2_3
; %bb.1: ; %.lr.ph
s_clause 0x1
s_load_b32 s3, s[0:1], 0x24
s_load_b128 s[4:7], s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s3, v[0:1]
v_mul_lo_u32 v3, v1, s2
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[0:1], 2, v[1:2]
v_ashrrev_i32_e32 v4, 31, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s6, v0
v_lshlrev_b64 v[2:3], 2, v[3:4]
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v2, vcc_lo, s4, v2
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
.LBB2_2: ; =>This Inner Loop Header: Depth=1
global_load_b32 v4, v[2:3], off
global_load_b32 v5, v[0:1], off
s_add_i32 s2, s2, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
s_cmp_eq_u32 s2, 0
s_waitcnt vmcnt(0)
v_div_scale_f32 v6, null, v5, v5, v4
v_div_scale_f32 v9, vcc_lo, v4, v5, v4
v_rcp_f32_e32 v7, v6
s_waitcnt_depctr 0xfff
v_fma_f32 v8, -v6, v7, 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v7, v8, v7
v_mul_f32_e32 v8, v9, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v10, -v6, v8, v9
v_fmac_f32_e32 v8, v10, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v6, -v6, v8, v9
v_div_fmas_f32 v6, v6, v7, v8
s_delay_alu instid0(VALU_DEP_1)
v_div_fixup_f32 v4, v6, v5, v4
global_store_b32 v[2:3], v4, off
v_add_co_u32 v2, vcc_lo, v2, 4
v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
s_cbranch_scc0 .LBB2_2
.LBB2_3: ; %._crit_edge
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z14kernel_sum_diviPfS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 11
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end2:
.size _Z14kernel_sum_diviPfS_, .Lfunc_end2-_Z14kernel_sum_diviPfS_
; -- End function
.section .AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 296
; NumSgprs: 18
; NumVgprs: 11
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 11
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
.text
.protected _Z16kernel_Dvec_multiiPfS_S_i ; -- Begin function _Z16kernel_Dvec_multiiPfS_S_i
.globl _Z16kernel_Dvec_multiiPfS_S_i
.p2align 8
.type _Z16kernel_Dvec_multiiPfS_S_i,@function
_Z16kernel_Dvec_multiiPfS_S_i: ; @_Z16kernel_Dvec_multiiPfS_S_i
; %bb.0:
s_clause 0x2
s_load_b32 s4, s[0:1], 0x34
s_load_b64 s[2:3], s[0:1], 0x0
s_load_b32 s8, s[0:1], 0x20
v_and_b32_e32 v1, 0x3ff, v0
v_bfe_u32 v0, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_lshr_b32 s5, s4, 16
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, s14, s4, v[1:2]
v_mad_u64_u32 v[3:4], null, s15, s5, v[0:1]
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x8
s_load_b64 s[0:1], s[0:1], 0x18
v_mad_u64_u32 v[0:1], null, v2, s2, v[3:4]
v_mad_u64_u32 v[4:5], null, v3, s3, s[8:9]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v1, 31, v0
v_ashrrev_i32_e32 v5, 31, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[0:1], 2, v[0:1]
v_lshlrev_b64 v[2:3], 2, v[4:5]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v4, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v2, vcc_lo, s6, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v3, vcc_lo
global_load_b32 v4, v[4:5], off
global_load_b32 v2, v[2:3], off
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_mul_f32_e32 v2, v4, v2
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z16kernel_Dvec_multiiPfS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end3:
.size _Z16kernel_Dvec_multiiPfS_S_i, .Lfunc_end3-_Z16kernel_Dvec_multiiPfS_S_i
; -- End function
.section .AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 240
; NumSgprs: 18
; NumVgprs: 6
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 6
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
.text
.protected _Z9copy_to_yiPfS_i ; -- Begin function _Z9copy_to_yiPfS_i
.globl _Z9copy_to_yiPfS_i
.p2align 8
.type _Z9copy_to_yiPfS_i,@function
_Z9copy_to_yiPfS_i: ; @_Z9copy_to_yiPfS_i
; %bb.0:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b128 s[4:7], s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_clause 0x1
s_load_b32 s2, s[0:1], 0x18
s_load_b32 s0, s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[1:2]
v_add_co_u32 v2, vcc_lo, s6, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v3, vcc_lo
global_load_b32 v4, v[2:3], off
s_waitcnt lgkmcnt(0)
v_mad_u64_u32 v[2:3], null, v1, s0, s[2:3]
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[2:3]
v_add_co_u32 v0, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
s_waitcnt vmcnt(0)
global_store_b32 v[0:1], v4, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9copy_to_yiPfS_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end4:
.size _Z9copy_to_yiPfS_i, .Lfunc_end4-_Z9copy_to_yiPfS_i
; -- End function
.section .AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 172
; NumSgprs: 18
; NumVgprs: 5
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 5
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
.text
.protected _Z21calc_reduce_meanshiftiPfS_S_ ; -- Begin function _Z21calc_reduce_meanshiftiPfS_S_
.globl _Z21calc_reduce_meanshiftiPfS_S_
.p2align 8
.type _Z21calc_reduce_meanshiftiPfS_S_,@function
_Z21calc_reduce_meanshiftiPfS_S_: ; @_Z21calc_reduce_meanshiftiPfS_S_
; %bb.0:
s_clause 0x3
s_load_b32 s3, s[0:1], 0x2c
s_load_b32 s10, s[0:1], 0x0
s_load_b64 s[8:9], s[0:1], 0x18
s_load_b128 s[4:7], s[0:1], 0x8
s_add_u32 s0, s0, 32
s_mov_b32 s2, s15
s_addc_u32 s1, s1, 0
v_mov_b32_e32 v3, 0
s_mov_b32 s11, exec_lo
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s2, s3, v[0:1]
v_cmpx_gt_i32_e64 s10, v1
s_cbranch_execz .LBB5_4
; %bb.1: ; %.lr.ph
s_load_b32 s1, s[0:1], 0x0
v_mov_b32_e32 v3, 0
s_mov_b32 s0, 0
s_waitcnt lgkmcnt(0)
s_mul_i32 s1, s1, s3
.LBB5_2: ; =>This Inner Loop Header: Depth=1
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[4:5], 2, v[1:2]
v_add_co_u32 v6, vcc_lo, s4, v4
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v7, vcc_lo, s5, v5, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v5, vcc_lo
global_load_b32 v2, v[6:7], off
global_load_b32 v4, v[4:5], off
s_waitcnt vmcnt(0)
v_dual_sub_f32 v2, v2, v4 :: v_dual_add_nc_u32 v1, s1, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_le_i32_e32 vcc_lo, s10, v1
v_fmac_f32_e32 v3, v2, v2
s_or_b32 s0, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s0
s_cbranch_execnz .LBB5_2
; %bb.3: ; %Flow49
s_or_b32 exec_lo, exec_lo, s0
.LBB5_4: ; %Flow50
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s11
v_lshl_add_u32 v1, v0, 2, 0
s_cmp_lt_u32 s3, 2
ds_store_b32 v1, v3
s_waitcnt lgkmcnt(0)
s_barrier
.LBB5_5: ; %Flow50
; =>This Inner Loop Header: Depth=1
buffer_gl0_inv
s_cbranch_scc1 .LBB5_9
; %bb.6: ; %.lr.ph36
; in Loop: Header=BB5_5 Depth=1
s_lshr_b32 s0, s3, 1
s_mov_b32 s1, exec_lo
v_cmpx_gt_u32_e64 s0, v0
s_cbranch_execz .LBB5_8
; %bb.7: ; in Loop: Header=BB5_5 Depth=1
v_lshl_add_u32 v2, s0, 2, v1
ds_load_b32 v2, v2
ds_load_b32 v3, v1
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v2, v2, v3
ds_store_b32 v1, v2
.LBB5_8: ; in Loop: Header=BB5_5 Depth=1
s_or_b32 exec_lo, exec_lo, s1
s_waitcnt lgkmcnt(0)
s_barrier
s_cmp_lt_u32 s3, 4
s_mov_b32 s3, s0
s_branch .LBB5_5
.LBB5_9: ; %._crit_edge37
s_mov_b32 s0, exec_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB5_11
; %bb.10:
v_mov_b32_e32 v0, 0
s_mov_b32 s3, 0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_lshl_b64 s[0:1], s[2:3], 2
s_add_u32 s0, s8, s0
ds_load_b32 v1, v0
s_addc_u32 s1, s9, s1
s_waitcnt lgkmcnt(0)
global_store_b32 v0, v1, s[0:1]
.LBB5_11:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z21calc_reduce_meanshiftiPfS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end5:
.size _Z21calc_reduce_meanshiftiPfS_S_, .Lfunc_end5-_Z21calc_reduce_meanshiftiPfS_S_
; -- End function
.section .AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 420
; NumSgprs: 18
; NumVgprs: 8
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 8
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object ; @__hip_cuid_
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0 ; 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z15calc_meanshift2PfS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z15calc_meanshift2PfS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z18calc_Kernel_MatrixiiPfS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z18calc_Kernel_MatrixiiPfS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z14kernel_sum_diviPfS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z14kernel_sum_diviPfS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 11
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z16kernel_Dvec_multiiPfS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z16kernel_Dvec_multiiPfS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9copy_to_yiPfS_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z9copy_to_yiPfS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
- .offset: 152
.size: 4
.value_kind: hidden_dynamic_lds_size
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z21calc_reduce_meanshiftiPfS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z21calc_reduce_meanshiftiPfS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
```
| 12,638 | 17,343 |
583 |
Convert the following CUDA host assembly code to AMD host assembly:
```cudaasm
.file "tmpxft_000c76d3_00000000-6_cuda_meanshift.cudafe1.cpp"
.text
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z10kernel_funff
.type _Z10kernel_funff, @function
_Z10kernel_funff:
.LFB2057:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2057:
.size _Z10kernel_funff, .-_Z10kernel_funff
.globl _Z39__device_stub__Z15calc_meanshift2PfS_S_PfS_S_
.type _Z39__device_stub__Z15calc_meanshift2PfS_S_PfS_S_, @function
_Z39__device_stub__Z15calc_meanshift2PfS_S_PfS_S_:
.LFB2082:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L9
.L5:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L10
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L9:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z15calc_meanshift2PfS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L5
.L10:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z39__device_stub__Z15calc_meanshift2PfS_S_PfS_S_, .-_Z39__device_stub__Z15calc_meanshift2PfS_S_PfS_S_
.globl _Z15calc_meanshift2PfS_S_
.type _Z15calc_meanshift2PfS_S_, @function
_Z15calc_meanshift2PfS_S_:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z39__device_stub__Z15calc_meanshift2PfS_S_PfS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z15calc_meanshift2PfS_S_, .-_Z15calc_meanshift2PfS_S_
.globl _Z45__device_stub__Z18calc_Kernel_MatrixiiPfS_S_iiiPfS_S_i
.type _Z45__device_stub__Z18calc_Kernel_MatrixiiPfS_S_iiiPfS_S_i, @function
_Z45__device_stub__Z18calc_Kernel_MatrixiiPfS_S_iiiPfS_S_i:
.LFB2084:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movl %edi, 44(%rsp)
movl %esi, 40(%rsp)
movq %rdx, 32(%rsp)
movq %rcx, 24(%rsp)
movq %r8, 16(%rsp)
movl %r9d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 44(%rsp), %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rax
movq %rax, 120(%rsp)
leaq 32(%rsp), %rax
movq %rax, 128(%rsp)
leaq 24(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L17
.L13:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L18
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L17:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z18calc_Kernel_MatrixiiPfS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L13
.L18:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z45__device_stub__Z18calc_Kernel_MatrixiiPfS_S_iiiPfS_S_i, .-_Z45__device_stub__Z18calc_Kernel_MatrixiiPfS_S_iiiPfS_S_i
.globl _Z18calc_Kernel_MatrixiiPfS_S_i
.type _Z18calc_Kernel_MatrixiiPfS_S_i, @function
_Z18calc_Kernel_MatrixiiPfS_S_i:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z45__device_stub__Z18calc_Kernel_MatrixiiPfS_S_iiiPfS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z18calc_Kernel_MatrixiiPfS_S_i, .-_Z18calc_Kernel_MatrixiiPfS_S_i
.globl _Z37__device_stub__Z14kernel_sum_diviPfS_iPfS_
.type _Z37__device_stub__Z14kernel_sum_diviPfS_iPfS_, @function
_Z37__device_stub__Z14kernel_sum_diviPfS_iPfS_:
.LFB2086:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movl %edi, 28(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L25
.L21:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L26
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L25:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z14kernel_sum_diviPfS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L21
.L26:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2086:
.size _Z37__device_stub__Z14kernel_sum_diviPfS_iPfS_, .-_Z37__device_stub__Z14kernel_sum_diviPfS_iPfS_
.globl _Z14kernel_sum_diviPfS_
.type _Z14kernel_sum_diviPfS_, @function
_Z14kernel_sum_diviPfS_:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z37__device_stub__Z14kernel_sum_diviPfS_iPfS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _Z14kernel_sum_diviPfS_, .-_Z14kernel_sum_diviPfS_
.globl _Z43__device_stub__Z16kernel_Dvec_multiiPfS_S_iiiPfS_S_i
.type _Z43__device_stub__Z16kernel_Dvec_multiiPfS_S_iiiPfS_S_i, @function
_Z43__device_stub__Z16kernel_Dvec_multiiPfS_S_iiiPfS_S_i:
.LFB2088:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movl %edi, 44(%rsp)
movl %esi, 40(%rsp)
movq %rdx, 32(%rsp)
movq %rcx, 24(%rsp)
movq %r8, 16(%rsp)
movl %r9d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 44(%rsp), %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rax
movq %rax, 120(%rsp)
leaq 32(%rsp), %rax
movq %rax, 128(%rsp)
leaq 24(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L33
.L29:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L34
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L33:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z16kernel_Dvec_multiiPfS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L29
.L34:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2088:
.size _Z43__device_stub__Z16kernel_Dvec_multiiPfS_S_iiiPfS_S_i, .-_Z43__device_stub__Z16kernel_Dvec_multiiPfS_S_iiiPfS_S_i
.globl _Z16kernel_Dvec_multiiPfS_S_i
.type _Z16kernel_Dvec_multiiPfS_S_i, @function
_Z16kernel_Dvec_multiiPfS_S_i:
.LFB2089:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z43__device_stub__Z16kernel_Dvec_multiiPfS_S_iiiPfS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2089:
.size _Z16kernel_Dvec_multiiPfS_S_i, .-_Z16kernel_Dvec_multiiPfS_S_i
.globl _Z32__device_stub__Z9copy_to_yiPfS_iiPfS_i
.type _Z32__device_stub__Z9copy_to_yiPfS_iiPfS_i, @function
_Z32__device_stub__Z9copy_to_yiPfS_iiPfS_i:
.LFB2090:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 28(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 24(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 24(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L41
.L37:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L42
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L41:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9copy_to_yiPfS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L37
.L42:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2090:
.size _Z32__device_stub__Z9copy_to_yiPfS_iiPfS_i, .-_Z32__device_stub__Z9copy_to_yiPfS_iiPfS_i
.globl _Z9copy_to_yiPfS_i
.type _Z9copy_to_yiPfS_i, @function
_Z9copy_to_yiPfS_i:
.LFB2091:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z9copy_to_yiPfS_iiPfS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2091:
.size _Z9copy_to_yiPfS_i, .-_Z9copy_to_yiPfS_i
.globl _Z46__device_stub__Z21calc_reduce_meanshiftiPfS_S_iPfS_S_
.type _Z46__device_stub__Z21calc_reduce_meanshiftiPfS_S_iPfS_S_, @function
_Z46__device_stub__Z21calc_reduce_meanshiftiPfS_S_iPfS_S_:
.LFB2092:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 28(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %rcx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L49
.L45:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L50
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L49:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z21calc_reduce_meanshiftiPfS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L45
.L50:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2092:
.size _Z46__device_stub__Z21calc_reduce_meanshiftiPfS_S_iPfS_S_, .-_Z46__device_stub__Z21calc_reduce_meanshiftiPfS_S_iPfS_S_
.globl _Z21calc_reduce_meanshiftiPfS_S_
.type _Z21calc_reduce_meanshiftiPfS_S_, @function
_Z21calc_reduce_meanshiftiPfS_S_:
.LFB2093:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z46__device_stub__Z21calc_reduce_meanshiftiPfS_S_iPfS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2093:
.size _Z21calc_reduce_meanshiftiPfS_S_, .-_Z21calc_reduce_meanshiftiPfS_S_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z21calc_reduce_meanshiftiPfS_S_"
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "_Z9copy_to_yiPfS_i"
.LC2:
.string "_Z16kernel_Dvec_multiiPfS_S_i"
.LC3:
.string "_Z14kernel_sum_diviPfS_"
.section .rodata.str1.8
.align 8
.LC4:
.string "_Z18calc_Kernel_MatrixiiPfS_S_i"
.section .rodata.str1.1
.LC5:
.string "_Z15calc_meanshift2PfS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2095:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z21calc_reduce_meanshiftiPfS_S_(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z9copy_to_yiPfS_i(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z16kernel_Dvec_multiiPfS_S_i(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z14kernel_sum_diviPfS_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z18calc_Kernel_MatrixiiPfS_S_i(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _Z15calc_meanshift2PfS_S_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2095:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
```
|
```amdasm
.text
.file "cuda_meanshift.hip"
.globl _Z30__device_stub__calc_meanshift2PfS_S_ # -- Begin function _Z30__device_stub__calc_meanshift2PfS_S_
.type _Z30__device_stub__calc_meanshift2PfS_S_,@function
_Z30__device_stub__calc_meanshift2PfS_S_: # @_Z30__device_stub__calc_meanshift2PfS_S_
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $112, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 40(%rsp), %rax
movq %rdi, (%rax)
leaq 32(%rsp), %rcx
movq %rsi, (%rcx)
leaq 24(%rsp), %rsi
movq %rdx, (%rsi)
leaq 80(%rsp), %rbx
movq %rax, (%rbx)
movq %rcx, 8(%rbx)
movq %rsi, 16(%rbx)
leaq 64(%rsp), %r14
leaq 48(%rsp), %r15
leaq 16(%rsp), %r12
leaq 8(%rsp), %r13
movq %r14, %rdi
movq %r15, %rsi
movq %r12, %rdx
movq %r13, %rcx
callq __hipPopCallConfiguration
movq (%r14), %rsi
movl 8(%r14), %edx
movq (%r15), %rcx
movl 8(%r15), %r8d
movl $_Z15calc_meanshift2PfS_S_, %edi
movq %rbx, %r9
pushq (%r13)
.cfi_adjust_cfa_offset 8
pushq (%r12)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $128, %rsp
.cfi_adjust_cfa_offset -128
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z30__device_stub__calc_meanshift2PfS_S_, .Lfunc_end0-_Z30__device_stub__calc_meanshift2PfS_S_
.cfi_endproc
# -- End function
.globl _Z33__device_stub__calc_Kernel_MatrixiiPfS_S_i # -- Begin function _Z33__device_stub__calc_Kernel_MatrixiiPfS_S_i
.type _Z33__device_stub__calc_Kernel_MatrixiiPfS_S_i,@function
_Z33__device_stub__calc_Kernel_MatrixiiPfS_S_i: # @_Z33__device_stub__calc_Kernel_MatrixiiPfS_S_i
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $144, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 20(%rsp), %rax
movl %edi, (%rax)
leaq 16(%rsp), %rdi
movl %esi, (%rdi)
leaq 56(%rsp), %rsi
movq %rdx, (%rsi)
leaq 48(%rsp), %rdx
movq %rcx, (%rdx)
leaq 40(%rsp), %rcx
movq %r8, (%rcx)
leaq 12(%rsp), %r8
movl %r9d, (%r8)
leaq 96(%rsp), %rbx
movq %rax, (%rbx)
movq %rdi, 8(%rbx)
movq %rsi, 16(%rbx)
movq %rdx, 24(%rbx)
movq %rcx, 32(%rbx)
movq %r8, 40(%rbx)
leaq 80(%rsp), %r14
leaq 64(%rsp), %r15
leaq 32(%rsp), %r12
leaq 24(%rsp), %r13
movq %r14, %rdi
movq %r15, %rsi
movq %r12, %rdx
movq %r13, %rcx
callq __hipPopCallConfiguration
movq (%r14), %rsi
movl 8(%r14), %edx
movq (%r15), %rcx
movl 8(%r15), %r8d
movl $_Z18calc_Kernel_MatrixiiPfS_S_i, %edi
movq %rbx, %r9
pushq (%r13)
.cfi_adjust_cfa_offset 8
pushq (%r12)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $160, %rsp
.cfi_adjust_cfa_offset -160
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z33__device_stub__calc_Kernel_MatrixiiPfS_S_i, .Lfunc_end1-_Z33__device_stub__calc_Kernel_MatrixiiPfS_S_i
.cfi_endproc
# -- End function
.globl _Z29__device_stub__kernel_sum_diviPfS_ # -- Begin function _Z29__device_stub__kernel_sum_diviPfS_
.type _Z29__device_stub__kernel_sum_diviPfS_,@function
_Z29__device_stub__kernel_sum_diviPfS_: # @_Z29__device_stub__kernel_sum_diviPfS_
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $112, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 12(%rsp), %rax
movl %edi, (%rax)
leaq 40(%rsp), %rcx
movq %rsi, (%rcx)
leaq 32(%rsp), %rsi
movq %rdx, (%rsi)
leaq 80(%rsp), %rbx
movq %rax, (%rbx)
movq %rcx, 8(%rbx)
movq %rsi, 16(%rbx)
leaq 64(%rsp), %r14
leaq 48(%rsp), %r15
leaq 24(%rsp), %r12
leaq 16(%rsp), %r13
movq %r14, %rdi
movq %r15, %rsi
movq %r12, %rdx
movq %r13, %rcx
callq __hipPopCallConfiguration
movq (%r14), %rsi
movl 8(%r14), %edx
movq (%r15), %rcx
movl 8(%r15), %r8d
movl $_Z14kernel_sum_diviPfS_, %edi
movq %rbx, %r9
pushq (%r13)
.cfi_adjust_cfa_offset 8
pushq (%r12)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $128, %rsp
.cfi_adjust_cfa_offset -128
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size _Z29__device_stub__kernel_sum_diviPfS_, .Lfunc_end2-_Z29__device_stub__kernel_sum_diviPfS_
.cfi_endproc
# -- End function
.globl _Z31__device_stub__kernel_Dvec_multiiPfS_S_i # -- Begin function _Z31__device_stub__kernel_Dvec_multiiPfS_S_i
.type _Z31__device_stub__kernel_Dvec_multiiPfS_S_i,@function
_Z31__device_stub__kernel_Dvec_multiiPfS_S_i: # @_Z31__device_stub__kernel_Dvec_multiiPfS_S_i
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $144, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 20(%rsp), %rax
movl %edi, (%rax)
leaq 16(%rsp), %rdi
movl %esi, (%rdi)
leaq 56(%rsp), %rsi
movq %rdx, (%rsi)
leaq 48(%rsp), %rdx
movq %rcx, (%rdx)
leaq 40(%rsp), %rcx
movq %r8, (%rcx)
leaq 12(%rsp), %r8
movl %r9d, (%r8)
leaq 96(%rsp), %rbx
movq %rax, (%rbx)
movq %rdi, 8(%rbx)
movq %rsi, 16(%rbx)
movq %rdx, 24(%rbx)
movq %rcx, 32(%rbx)
movq %r8, 40(%rbx)
leaq 80(%rsp), %r14
leaq 64(%rsp), %r15
leaq 32(%rsp), %r12
leaq 24(%rsp), %r13
movq %r14, %rdi
movq %r15, %rsi
movq %r12, %rdx
movq %r13, %rcx
callq __hipPopCallConfiguration
movq (%r14), %rsi
movl 8(%r14), %edx
movq (%r15), %rcx
movl 8(%r15), %r8d
movl $_Z16kernel_Dvec_multiiPfS_S_i, %edi
movq %rbx, %r9
pushq (%r13)
.cfi_adjust_cfa_offset 8
pushq (%r12)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $160, %rsp
.cfi_adjust_cfa_offset -160
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size _Z31__device_stub__kernel_Dvec_multiiPfS_S_i, .Lfunc_end3-_Z31__device_stub__kernel_Dvec_multiiPfS_S_i
.cfi_endproc
# -- End function
.globl _Z24__device_stub__copy_to_yiPfS_i # -- Begin function _Z24__device_stub__copy_to_yiPfS_i
.type _Z24__device_stub__copy_to_yiPfS_i,@function
_Z24__device_stub__copy_to_yiPfS_i: # @_Z24__device_stub__copy_to_yiPfS_i
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $112, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 12(%rsp), %rax
movl %edi, (%rax)
leaq 40(%rsp), %rdi
movq %rsi, (%rdi)
leaq 32(%rsp), %rsi
movq %rdx, (%rsi)
leaq 8(%rsp), %rdx
movl %ecx, (%rdx)
leaq 80(%rsp), %rbx
movq %rax, (%rbx)
movq %rdi, 8(%rbx)
movq %rsi, 16(%rbx)
movq %rdx, 24(%rbx)
leaq 64(%rsp), %r14
leaq 48(%rsp), %r15
leaq 24(%rsp), %r12
leaq 16(%rsp), %r13
movq %r14, %rdi
movq %r15, %rsi
movq %r12, %rdx
movq %r13, %rcx
callq __hipPopCallConfiguration
movq (%r14), %rsi
movl 8(%r14), %edx
movq (%r15), %rcx
movl 8(%r15), %r8d
movl $_Z9copy_to_yiPfS_i, %edi
movq %rbx, %r9
pushq (%r13)
.cfi_adjust_cfa_offset 8
pushq (%r12)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $128, %rsp
.cfi_adjust_cfa_offset -128
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end4:
.size _Z24__device_stub__copy_to_yiPfS_i, .Lfunc_end4-_Z24__device_stub__copy_to_yiPfS_i
.cfi_endproc
# -- End function
.globl _Z36__device_stub__calc_reduce_meanshiftiPfS_S_ # -- Begin function _Z36__device_stub__calc_reduce_meanshiftiPfS_S_
.type _Z36__device_stub__calc_reduce_meanshiftiPfS_S_,@function
_Z36__device_stub__calc_reduce_meanshiftiPfS_S_: # @_Z36__device_stub__calc_reduce_meanshiftiPfS_S_
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $112, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 4(%rsp), %rax
movl %edi, (%rax)
leaq 40(%rsp), %rdi
movq %rsi, (%rdi)
leaq 32(%rsp), %rsi
movq %rdx, (%rsi)
leaq 24(%rsp), %rdx
movq %rcx, (%rdx)
leaq 80(%rsp), %rbx
movq %rax, (%rbx)
movq %rdi, 8(%rbx)
movq %rsi, 16(%rbx)
movq %rdx, 24(%rbx)
leaq 64(%rsp), %r14
leaq 48(%rsp), %r15
leaq 16(%rsp), %r12
leaq 8(%rsp), %r13
movq %r14, %rdi
movq %r15, %rsi
movq %r12, %rdx
movq %r13, %rcx
callq __hipPopCallConfiguration
movq (%r14), %rsi
movl 8(%r14), %edx
movq (%r15), %rcx
movl 8(%r15), %r8d
movl $_Z21calc_reduce_meanshiftiPfS_S_, %edi
movq %rbx, %r9
pushq (%r13)
.cfi_adjust_cfa_offset 8
pushq (%r12)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $128, %rsp
.cfi_adjust_cfa_offset -128
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end5:
.size _Z36__device_stub__calc_reduce_meanshiftiPfS_S_, .Lfunc_end5-_Z36__device_stub__calc_reduce_meanshiftiPfS_S_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
movq __hip_gpubin_handle(%rip), %rbx
testq %rbx, %rbx
jne .LBB6_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, %rbx
movq %rax, __hip_gpubin_handle(%rip)
.LBB6_2:
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15calc_meanshift2PfS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z18calc_Kernel_MatrixiiPfS_S_i, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z14kernel_sum_diviPfS_, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z16kernel_Dvec_multiiPfS_S_i, %esi
movl $.L__unnamed_4, %edx
movl $.L__unnamed_4, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9copy_to_yiPfS_i, %esi
movl $.L__unnamed_5, %edx
movl $.L__unnamed_5, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z21calc_reduce_meanshiftiPfS_S_, %esi
movl $.L__unnamed_6, %edx
movl $.L__unnamed_6, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end6:
.size __hip_module_ctor, .Lfunc_end6-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB7_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB7_2:
retq
.Lfunc_end7:
.size __hip_module_dtor, .Lfunc_end7-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z15calc_meanshift2PfS_S_,@object # @_Z15calc_meanshift2PfS_S_
.section .rodata,"a",@progbits
.globl _Z15calc_meanshift2PfS_S_
.p2align 3, 0x0
_Z15calc_meanshift2PfS_S_:
.quad _Z30__device_stub__calc_meanshift2PfS_S_
.size _Z15calc_meanshift2PfS_S_, 8
.type _Z18calc_Kernel_MatrixiiPfS_S_i,@object # @_Z18calc_Kernel_MatrixiiPfS_S_i
.globl _Z18calc_Kernel_MatrixiiPfS_S_i
.p2align 3, 0x0
_Z18calc_Kernel_MatrixiiPfS_S_i:
.quad _Z33__device_stub__calc_Kernel_MatrixiiPfS_S_i
.size _Z18calc_Kernel_MatrixiiPfS_S_i, 8
.type _Z14kernel_sum_diviPfS_,@object # @_Z14kernel_sum_diviPfS_
.globl _Z14kernel_sum_diviPfS_
.p2align 3, 0x0
_Z14kernel_sum_diviPfS_:
.quad _Z29__device_stub__kernel_sum_diviPfS_
.size _Z14kernel_sum_diviPfS_, 8
.type _Z16kernel_Dvec_multiiPfS_S_i,@object # @_Z16kernel_Dvec_multiiPfS_S_i
.globl _Z16kernel_Dvec_multiiPfS_S_i
.p2align 3, 0x0
_Z16kernel_Dvec_multiiPfS_S_i:
.quad _Z31__device_stub__kernel_Dvec_multiiPfS_S_i
.size _Z16kernel_Dvec_multiiPfS_S_i, 8
.type _Z9copy_to_yiPfS_i,@object # @_Z9copy_to_yiPfS_i
.globl _Z9copy_to_yiPfS_i
.p2align 3, 0x0
_Z9copy_to_yiPfS_i:
.quad _Z24__device_stub__copy_to_yiPfS_i
.size _Z9copy_to_yiPfS_i, 8
.type _Z21calc_reduce_meanshiftiPfS_S_,@object # @_Z21calc_reduce_meanshiftiPfS_S_
.globl _Z21calc_reduce_meanshiftiPfS_S_
.p2align 3, 0x0
_Z21calc_reduce_meanshiftiPfS_S_:
.quad _Z36__device_stub__calc_reduce_meanshiftiPfS_S_
.size _Z21calc_reduce_meanshiftiPfS_S_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z15calc_meanshift2PfS_S_"
.size .L__unnamed_1, 26
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z18calc_Kernel_MatrixiiPfS_S_i"
.size .L__unnamed_2, 32
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z14kernel_sum_diviPfS_"
.size .L__unnamed_3, 24
.type .L__unnamed_4,@object # @3
.L__unnamed_4:
.asciz "_Z16kernel_Dvec_multiiPfS_S_i"
.size .L__unnamed_4, 30
.type .L__unnamed_5,@object # @4
.L__unnamed_5:
.asciz "_Z9copy_to_yiPfS_i"
.size .L__unnamed_5, 19
.type .L__unnamed_6,@object # @5
.L__unnamed_6:
.asciz "_Z21calc_reduce_meanshiftiPfS_S_"
.size .L__unnamed_6, 33
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z30__device_stub__calc_meanshift2PfS_S_
.addrsig_sym _Z33__device_stub__calc_Kernel_MatrixiiPfS_S_i
.addrsig_sym _Z29__device_stub__kernel_sum_diviPfS_
.addrsig_sym _Z31__device_stub__kernel_Dvec_multiiPfS_S_i
.addrsig_sym _Z24__device_stub__copy_to_yiPfS_i
.addrsig_sym _Z36__device_stub__calc_reduce_meanshiftiPfS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z15calc_meanshift2PfS_S_
.addrsig_sym _Z18calc_Kernel_MatrixiiPfS_S_i
.addrsig_sym _Z14kernel_sum_diviPfS_
.addrsig_sym _Z16kernel_Dvec_multiiPfS_S_i
.addrsig_sym _Z9copy_to_yiPfS_i
.addrsig_sym _Z21calc_reduce_meanshiftiPfS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
```
| 8,019 | 8,248 |
584 |
Convert the following CUDA device assembly code to AMD device assembly:
```cudaasm
code for sm_80
Function : _Z18scan_workefficientPfS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ;
S2R R9, SR_TID.X ;
IMAD.MOV.U32 R3, RZ, RZ, 0x4 ;
ULDC.64 UR4, c[0x0][0x118] ;
IMAD.SHL.U32 R0, R9, 0x2, RZ ;
IMAD.WIDE R2, R0, R3, c[0x0][0x168] ;
LDG.E R7, [R2.64+0x4] ;
LDG.E R6, [R2.64] ;
MOV R4, c[0x0][0x170] ;
IMAD.MOV.U32 R5, RZ, RZ, 0x1 ;
ISETP.NE.AND P0, PT, R9, RZ, PT ;
ISETP.GE.AND P1, PT, R4, 0x2, PT ;
IADD3 R4, R0, 0x1, RZ ;
@!P0 IMAD.MOV.U32 R8, RZ, RZ, c[0x0][0x170] ;
@!P0 LEA R8, R8, 0xfffffffc, 0x2 ;
STS.64 [R9.X8], R6 ;
@!P1 BRA 0x210 ;
HFMA2.MMA R5, -RZ, RZ, 0, 5.9604644775390625e-08 ;
IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x170] ;
SHF.R.S32.HI R10, RZ, 0x1, R2 ;
BAR.SYNC.DEFER_BLOCKING 0x0 ;
ISETP.GE.AND P2, PT, R9, R10, PT ;
@!P2 IMAD R3, R4, R5, RZ ;
@!P2 IMAD.SHL.U32 R6, R3, 0x4, RZ ;
@!P2 LDS R3, [R3.X4+-0x4] ;
@!P2 LEA R7, R5.reuse, R6, 0x2 ;
IMAD.SHL.U32 R5, R5, 0x2, RZ ;
@!P2 LDS R6, [R7+-0x4] ;
@!P2 FADD R6, R6, R3 ;
@!P2 STS [R7+-0x4], R6 ;
ISETP.GT.AND P2, PT, R2, 0x3, PT ;
IMAD.MOV.U32 R2, RZ, RZ, R10 ;
@P2 BRA 0x130 ;
@!P0 STS [R8], RZ ;
SHF.R.S32.HI R13, RZ, 0x1f, R0 ;
@!P1 BRA 0x370 ;
MOV R2, 0x1 ;
BAR.SYNC.DEFER_BLOCKING 0x0 ;
ISETP.GE.AND P0, PT, R9, R2, PT ;
IMAD.SHL.U32 R2, R2, 0x2, RZ ;
SHF.R.S32.HI R5, RZ, 0x1, R5 ;
BSSY B0, 0x360 ;
ISETP.GE.AND P1, PT, R2, c[0x0][0x170], PT ;
@P0 BRA 0x350 ;
IMAD R3, R4, R5, RZ ;
IMAD.SHL.U32 R6, R3, 0x4, RZ ;
LEA R11, R5, R6, 0x2 ;
LDS R6, [R3.X4+-0x4] ;
LDS R8, [R11+-0x4] ;
STS [R3.X4+-0x4], R8 ;
LDS R7, [R11+-0x4] ;
FADD R6, R6, R7 ;
STS [R11+-0x4], R6 ;
BSYNC B0 ;
@!P1 BRA 0x250 ;
BAR.SYNC.DEFER_BLOCKING 0x0 ;
LEA R2, P0, R0, c[0x0][0x160], 0x2 ;
LEA.HI.X R3, R0, c[0x0][0x164], R13, 0x2, P0 ;
LDS.64 R4, [R9.X8] ;
STG.E [R2.64], R4 ;
STG.E [R2.64+0x4], R5 ;
EXIT ;
BRA 0x3e0;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
```
|
```amdasm
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z18scan_workefficientPfS_i ; -- Begin function _Z18scan_workefficientPfS_i
.globl _Z18scan_workefficientPfS_i
.p2align 8
.type _Z18scan_workefficientPfS_i,@function
_Z18scan_workefficientPfS_i: ; @_Z18scan_workefficientPfS_i
; %bb.0:
s_load_b128 s[4:7], s[0:1], 0x0
v_lshlrev_b32_e32 v2, 3, v0
s_load_b32 s0, s[0:1], 0x10
v_lshlrev_b32_e32 v1, 1, v0
s_mov_b32 s1, 1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
v_or_b32_e32 v3, 1, v1
s_waitcnt lgkmcnt(0)
global_load_b64 v[4:5], v2, s[6:7]
v_add_nc_u32_e32 v2, 0, v2
s_ashr_i32 s2, s0, 1
s_cmp_lt_i32 s2, 1
s_waitcnt vmcnt(0)
ds_store_2addr_b32 v2, v4, v5 offset1:1
s_cbranch_scc1 .LBB0_5
.LBB0_1: ; =>This Inner Loop Header: Depth=1
s_mov_b32 s3, exec_lo
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_cmpx_gt_i32_e64 s2, v0
s_cbranch_execz .LBB0_3
; %bb.2: ; in Loop: Header=BB0_1 Depth=1
v_mul_lo_u32 v4, s1, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b32_e32 v4, 2, v4
v_add3_u32 v4, v4, 0, -4
s_delay_alu instid0(VALU_DEP_1)
v_lshl_add_u32 v5, s1, 2, v4
ds_load_b32 v4, v4
ds_load_b32 v6, v5
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v4, v4, v6
ds_store_b32 v5, v4
.LBB0_3: ; in Loop: Header=BB0_1 Depth=1
s_or_b32 exec_lo, exec_lo, s3
s_lshl_b32 s1, s1, 1
s_lshr_b32 s3, s2, 1
s_cmp_lt_u32 s2, 2
s_cbranch_scc1 .LBB0_5
; %bb.4: ; in Loop: Header=BB0_1 Depth=1
s_mov_b32 s2, s3
s_branch .LBB0_1
.LBB0_5: ; %Flow60
s_mov_b32 s2, exec_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB0_7
; %bb.6:
s_lshl_b32 s3, s0, 2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s3, s3, 0
s_add_i32 s3, s3, -4
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v4, 0 :: v_dual_mov_b32 v5, s3
ds_store_b32 v5, v4
.LBB0_7:
s_or_b32 exec_lo, exec_lo, s2
s_cmp_lt_i32 s0, 2
s_cbranch_scc1 .LBB0_12
; %bb.8: ; %.lr.ph49
s_mov_b32 s2, 1
.LBB0_9: ; =>This Inner Loop Header: Depth=1
s_lshr_b32 s1, s1, 1
s_mov_b32 s3, exec_lo
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_cmpx_gt_u32_e64 s2, v0
s_cbranch_execz .LBB0_11
; %bb.10: ; in Loop: Header=BB0_9 Depth=1
v_mul_lo_u32 v4, s1, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b32_e32 v4, 2, v4
v_add3_u32 v4, v4, 0, -4
s_delay_alu instid0(VALU_DEP_1)
v_lshl_add_u32 v5, s1, 2, v4
ds_load_b32 v6, v4
ds_load_b32 v7, v5
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v6, v6, v7
ds_store_b32 v4, v7
ds_store_b32 v5, v6
.LBB0_11: ; in Loop: Header=BB0_9 Depth=1
s_or_b32 exec_lo, exec_lo, s3
s_lshl_b32 s2, s2, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_ge_i32 s2, s0
s_cbranch_scc0 .LBB0_9
.LBB0_12: ; %._crit_edge50
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
ds_load_2addr_b32 v[2:3], v2 offset1:1
v_lshlrev_b32_e32 v0, 2, v1
s_waitcnt lgkmcnt(0)
global_store_b64 v0, v[2:3], s[4:5]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z18scan_workefficientPfS_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 20
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 8
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z18scan_workefficientPfS_i, .Lfunc_end0-_Z18scan_workefficientPfS_i
; -- End function
.section .AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 452
; NumSgprs: 8
; NumVgprs: 8
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 0
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 8
; NumVGPRsForWavesPerEU: 8
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object ; @__hip_cuid_
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0 ; 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 20
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z18scan_workefficientPfS_i
.private_segment_fixed_size: 0
.sgpr_count: 8
.sgpr_spill_count: 0
.symbol: _Z18scan_workefficientPfS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
```
| 1,228 | 3,101 |
585 |
Convert the following CUDA host assembly code to AMD host assembly:
```cudaasm
.file "tmpxft_000d0eba_00000000-6_scan_workefficient.cudafe1.cpp"
.text
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z41__device_stub__Z18scan_workefficientPfS_iPfS_i
.type _Z41__device_stub__Z18scan_workefficientPfS_iPfS_i, @function
_Z41__device_stub__Z18scan_workefficientPfS_iPfS_i:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z18scan_workefficientPfS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z41__device_stub__Z18scan_workefficientPfS_iPfS_i, .-_Z41__device_stub__Z18scan_workefficientPfS_iPfS_i
.globl _Z18scan_workefficientPfS_i
.type _Z18scan_workefficientPfS_i, @function
_Z18scan_workefficientPfS_i:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z41__device_stub__Z18scan_workefficientPfS_iPfS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z18scan_workefficientPfS_i, .-_Z18scan_workefficientPfS_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z18scan_workefficientPfS_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z18scan_workefficientPfS_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
```
|
```amdasm
.text
.file "scan_workefficient.hip"
.globl _Z33__device_stub__scan_workefficientPfS_i # -- Begin function _Z33__device_stub__scan_workefficientPfS_i
.type _Z33__device_stub__scan_workefficientPfS_i,@function
_Z33__device_stub__scan_workefficientPfS_i: # @_Z33__device_stub__scan_workefficientPfS_i
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $112, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 40(%rsp), %rax
movq %rdi, (%rax)
leaq 32(%rsp), %rcx
movq %rsi, (%rcx)
leaq 12(%rsp), %rsi
movl %edx, (%rsi)
leaq 80(%rsp), %rbx
movq %rax, (%rbx)
movq %rcx, 8(%rbx)
movq %rsi, 16(%rbx)
leaq 64(%rsp), %r14
leaq 48(%rsp), %r15
leaq 24(%rsp), %r12
leaq 16(%rsp), %r13
movq %r14, %rdi
movq %r15, %rsi
movq %r12, %rdx
movq %r13, %rcx
callq __hipPopCallConfiguration
movq (%r14), %rsi
movl 8(%r14), %edx
movq (%r15), %rcx
movl 8(%r15), %r8d
movl $_Z18scan_workefficientPfS_i, %edi
movq %rbx, %r9
pushq (%r13)
.cfi_adjust_cfa_offset 8
pushq (%r12)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $128, %rsp
.cfi_adjust_cfa_offset -128
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z33__device_stub__scan_workefficientPfS_i, .Lfunc_end0-_Z33__device_stub__scan_workefficientPfS_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, %rdi
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z18scan_workefficientPfS_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z18scan_workefficientPfS_i,@object # @_Z18scan_workefficientPfS_i
.section .rodata,"a",@progbits
.globl _Z18scan_workefficientPfS_i
.p2align 3, 0x0
_Z18scan_workefficientPfS_i:
.quad _Z33__device_stub__scan_workefficientPfS_i
.size _Z18scan_workefficientPfS_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z18scan_workefficientPfS_i"
.size .L__unnamed_1, 28
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z33__device_stub__scan_workefficientPfS_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z18scan_workefficientPfS_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
```
| 1,908 | 2,103 |
586 |
Convert the following CUDA device assembly code to AMD device assembly:
```cudaasm
code for sm_80
Function : _Z7minimumPiS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ;
S2R R0, SR_TID.X ;
ULDC.64 UR6, c[0x0][0x118] ;
BSSY B2, 0x8d0 ;
IMAD.MOV.U32 R4, RZ, RZ, 0x7fffffff ;
IADD3 R2, R0, 0x100, RZ ;
IMNMX R3, R2, c[0x0][0x170], PT ;
ISETP.GE.AND P0, PT, R0, R3, PT ;
@P0 BRA 0x8c0 ;
ULDC UR4, c[0x0][0x170] ;
IADD3 R2, -R0, -0x101, RZ ;
ULOP3.LUT UR4, URZ, UR4, URZ, 0x33, !UPT ;
BSSY B1, 0x7f0 ;
IMAD.MOV.U32 R6, RZ, RZ, R0 ;
IMNMX R3, R2, UR4, !PT ;
LOP3.LUT R2, RZ, R0, RZ, 0x33, !PT ;
IADD3 R4, -R3, -0x2, -R0 ;
IMAD.IADD R2, R2, 0x1, -R3 ;
ISETP.GE.U32.AND P0, PT, R4, 0x3, PT ;
IMAD.MOV.U32 R4, RZ, RZ, 0x7fffffff ;
LOP3.LUT R5, R2, 0x3, RZ, 0xc0, !PT ;
@!P0 BRA 0x7e0 ;
IADD3 R7, R5, R0, R3 ;
IMAD.MOV.U32 R9, RZ, RZ, 0x4 ;
BSSY B0, 0x6e0 ;
IMAD.MOV.U32 R4, RZ, RZ, 0x7fffffff ;
IMAD.MOV R7, RZ, RZ, -R7 ;
IMAD.WIDE R2, R0, R9, c[0x0][0x160] ;
ISETP.GT.AND P0, PT, R7, 0x1, PT ;
IMAD.MOV.U32 R6, RZ, RZ, R0 ;
IADD3 R2, P1, R2, 0x8, RZ ;
IMAD.X R3, RZ, RZ, R3, P1 ;
@!P0 BRA 0x6d0 ;
IADD3 R8, R7, -0x1, RZ ;
BSSY B3, 0x4e0 ;
PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ;
ISETP.GT.AND P1, PT, R8, 0xc, PT ;
@!P1 BRA 0x4d0 ;
PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ;
LDG.E R17, [R2.64+-0x8] ;
LDG.E R18, [R2.64+-0x4] ;
LDG.E R20, [R2.64] ;
LDG.E R22, [R2.64+0x4] ;
LDG.E R24, [R2.64+0x8] ;
LDG.E R26, [R2.64+0xc] ;
LDG.E R28, [R2.64+0x10] ;
LDG.E R16, [R2.64+0x14] ;
LDG.E R15, [R2.64+0x18] ;
LDG.E R14, [R2.64+0x1c] ;
LDG.E R13, [R2.64+0x20] ;
LDG.E R12, [R2.64+0x24] ;
LDG.E R11, [R2.64+0x28] ;
LDG.E R9, [R2.64+0x2c] ;
LDG.E R10, [R2.64+0x30] ;
LDG.E R8, [R2.64+0x34] ;
IADD3 R7, R7, -0x10, RZ ;
IADD3 R6, R6, 0x10, RZ ;
ISETP.GT.AND P1, PT, R7, 0xd, PT ;
IADD3 R2, P2, R2, 0x40, RZ ;
IMAD.X R3, RZ, RZ, R3, P2 ;
IMNMX R17, R17, R4, PT ;
IMNMX R17, R17, R18, PT ;
IMNMX R17, R17, R20, PT ;
IMNMX R17, R17, R22, PT ;
IMNMX R17, R17, R24, PT ;
IMNMX R17, R17, R26, PT ;
IMNMX R17, R17, R28, PT ;
IMNMX R16, R17, R16, PT ;
IMNMX R15, R16, R15, PT ;
IMNMX R14, R15, R14, PT ;
IMNMX R13, R14, R13, PT ;
IMNMX R12, R13, R12, PT ;
IMNMX R12, R12, R11, PT ;
IMNMX R9, R12, R9, PT ;
IMNMX R9, R9, R10, PT ;
IMNMX R4, R9, R8, PT ;
@P1 BRA 0x270 ;
BSYNC B3 ;
IADD3 R8, R7, -0x1, RZ ;
BSSY B3, 0x6a0 ;
ISETP.GT.AND P1, PT, R8, 0x4, PT ;
@!P1 BRA 0x690 ;
LDG.E R9, [R2.64+-0x8] ;
LDG.E R8, [R2.64+-0x4] ;
LDG.E R11, [R2.64] ;
LDG.E R13, [R2.64+0x4] ;
LDG.E R15, [R2.64+0x8] ;
LDG.E R17, [R2.64+0xc] ;
LDG.E R19, [R2.64+0x10] ;
LDG.E R21, [R2.64+0x14] ;
PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ;
IADD3 R6, R6, 0x8, RZ ;
IADD3 R7, R7, -0x8, RZ ;
IMNMX R9, R4, R9, PT ;
IMNMX R8, R9, R8, PT ;
IADD3 R9, P1, R2, 0x20, RZ ;
IMNMX R8, R8, R11, PT ;
IMAD.X R10, RZ, RZ, R3, P1 ;
IMNMX R8, R8, R13, PT ;
IMAD.MOV.U32 R2, RZ, RZ, R9 ;
IMAD.MOV.U32 R3, RZ, RZ, R10 ;
IMNMX R8, R8, R15, PT ;
IMNMX R8, R8, R17, PT ;
IMNMX R8, R8, R19, PT ;
IMNMX R4, R8, R21, PT ;
BSYNC B3 ;
ISETP.NE.OR P0, PT, R7, 0x1, P0 ;
@!P0 BREAK B0 ;
@!P0 BRA 0x7e0 ;
BSYNC B0 ;
LDG.E R9, [R2.64+-0x8] ;
LDG.E R8, [R2.64+-0x4] ;
LDG.E R11, [R2.64] ;
LDG.E R13, [R2.64+0x4] ;
IADD3 R7, R7, -0x4, RZ ;
IADD3 R6, R6, 0x4, RZ ;
ISETP.NE.AND P0, PT, R7, 0x1, PT ;
IMNMX R9, R9, R4, PT ;
IMNMX R8, R9, R8, PT ;
IADD3 R9, P1, R2, 0x10, RZ ;
IMNMX R8, R8, R11, PT ;
IMAD.X R10, RZ, RZ, R3, P1 ;
IMNMX R4, R8, R13, PT ;
IMAD.MOV.U32 R2, RZ, RZ, R9 ;
IMAD.MOV.U32 R3, RZ, RZ, R10 ;
@P0 BRA 0x6e0 ;
BSYNC B1 ;
ISETP.NE.AND P0, PT, R5, RZ, PT ;
@!P0 BRA 0x8c0 ;
IMAD.MOV.U32 R3, RZ, RZ, 0x4 ;
IMAD.WIDE R2, R6, R3, c[0x0][0x160] ;
IMAD.MOV.U32 R7, RZ, RZ, R3 ;
IMAD.MOV.U32 R3, RZ, RZ, R7 ;
LDG.E R3, [R2.64] ;
IADD3 R5, R5, -0x1, RZ ;
ISETP.NE.AND P0, PT, R5, RZ, PT ;
IADD3 R2, P1, R2, 0x4, RZ ;
IMAD.X R7, RZ, RZ, R7, P1 ;
IMNMX R4, R3, R4, PT ;
@P0 BRA 0x840 ;
BSYNC B2 ;
WARPSYNC 0xffffffff ;
IMAD.MOV.U32 R3, RZ, RZ, 0x4 ;
IMAD.WIDE R2, R0, R3, c[0x0][0x168] ;
STG.E [R2.64], R4 ;
EXIT ;
BRA 0x920;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
```
|
```amdasm
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z7minimumPiS_i ; -- Begin function _Z7minimumPiS_i
.globl _Z7minimumPiS_i
.p2align 8
.type _Z7minimumPiS_i,@function
_Z7minimumPiS_i: ; @_Z7minimumPiS_i
; %bb.0:
s_clause 0x1
s_load_b32 s5, s[0:1], 0x10
s_load_b128 s[0:3], s[0:1], 0x0
v_bfrev_b32_e32 v4, -2
v_lshlrev_b32_e32 v3, 2, v0
s_mov_b32 s4, exec_lo
s_waitcnt lgkmcnt(0)
v_cmpx_gt_i32_e64 s5, v0
s_cbranch_execz .LBB0_4
; %bb.1: ; %.lr.ph.preheader
v_add_nc_u32_e32 v4, 0x100, v0
v_add_co_u32 v1, s0, s0, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e64 v2, null, s1, 0, s0
v_min_i32_e32 v5, s5, v4
v_bfrev_b32_e32 v4, -2
s_mov_b32 s1, 0
.LBB0_2: ; %.lr.ph
; =>This Inner Loop Header: Depth=1
global_load_b32 v6, v[1:2], off
v_add_nc_u32_e32 v0, 1, v0
v_add_co_u32 v1, vcc_lo, v1, 4
v_add_co_ci_u32_e32 v2, vcc_lo, 0, v2, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_ge_i32_e64 s0, v0, v5
s_or_b32 s1, s0, s1
s_waitcnt vmcnt(0)
v_min_i32_e32 v4, v4, v6
s_and_not1_b32 exec_lo, exec_lo, s1
s_cbranch_execnz .LBB0_2
; %bb.3: ; %Flow
s_or_b32 exec_lo, exec_lo, s1
.LBB0_4: ; %Flow26
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s4
global_store_b32 v3, v4, s[2:3]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z7minimumPiS_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 20
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 6
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z7minimumPiS_i, .Lfunc_end0-_Z7minimumPiS_i
; -- End function
.section .AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 176
; NumSgprs: 8
; NumVgprs: 7
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 0
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 8
; NumVGPRsForWavesPerEU: 7
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object ; @__hip_cuid_
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0 ; 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 20
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z7minimumPiS_i
.private_segment_fixed_size: 0
.sgpr_count: 8
.sgpr_spill_count: 0
.symbol: _Z7minimumPiS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
```
| 2,634 | 2,177 |
587 |
Convert the following CUDA host assembly code to AMD host assembly:
```cudaasm
.file "tmpxft_00090cfa_00000000-6_cuda_max.cudafe1.cpp"
.text
.globl _ZSt21ios_base_library_initv
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z29__device_stub__Z7minimumPiS_iPiS_i
.type _Z29__device_stub__Z7minimumPiS_iPiS_i, @function
_Z29__device_stub__Z7minimumPiS_iPiS_i:
.LFB3694:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z7minimumPiS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3694:
.size _Z29__device_stub__Z7minimumPiS_iPiS_i, .-_Z29__device_stub__Z7minimumPiS_iPiS_i
.globl _Z7minimumPiS_i
.type _Z7minimumPiS_i, @function
_Z7minimumPiS_i:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z7minimumPiS_iPiS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _Z7minimumPiS_i, .-_Z7minimumPiS_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string " "
.LC1:
.string "Minimum of the array is "
.LC2:
.string "total elapsed time "
.LC3:
.string "ms"
.LC4:
.string "Min by CPU "
.text
.globl main
.type main, @function
main:
.LFB3669:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $72, %rsp
.cfi_def_cfa_offset 128
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl $512, %edi
call malloc@PLT
movq %rax, %r14
movl $0, %edi
call time@PLT
movl %eax, %edi
call srand@PLT
movq %r14, %rbx
leaq 512(%r14), %r12
movq %r14, %rbp
.L12:
call rand@PLT
movl %eax, 0(%rbp)
addq $4, %rbp
cmpq %r12, %rbp
jne .L12
movq %r14, %rbp
leaq _ZSt4cout(%rip), %r15
leaq .LC0(%rip), %r13
.L13:
movl 0(%rbp), %esi
movq %r15, %rdi
call _ZNSolsEi@PLT
movq %rax, %rdi
movl $1, %edx
movq %r13, %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
addq $4, %rbp
cmpq %r12, %rbp
jne .L13
leaq _ZSt4cout(%rip), %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq 16(%rsp), %rdi
call cudaEventCreate@PLT
leaq 24(%rsp), %rdi
call cudaEventCreate@PLT
movq %rsp, %rdi
movl $512, %esi
call cudaMalloc@PLT
leaq 8(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
movl $4, %edi
call malloc@PLT
movq %rax, %rbp
movl $1, %ecx
movl $512, %edx
movq %r14, %rsi
movq (%rsp), %rdi
call cudaMemcpy@PLT
movl $0, %esi
movq 16(%rsp), %rdi
call cudaEventRecord@PLT
movl $128, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L21
.L14:
call cudaDeviceSynchronize@PLT
movl $2, %ecx
movl $4, %edx
movq 8(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
movl $0, %esi
movq 24(%rsp), %rdi
call cudaEventRecord@PLT
leaq 44(%rsp), %rdi
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
call cudaEventElapsedTime@PLT
movq 16(%rsp), %rdi
call cudaEventDestroy@PLT
movq 24(%rsp), %rdi
call cudaEventDestroy@PLT
leaq .LC1(%rip), %rsi
leaq _ZSt4cout(%rip), %r13
movq %r13, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl 0(%rbp), %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq .LC2(%rip), %rsi
movq %r13, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
pxor %xmm0, %xmm0
cvtss2sd 44(%rsp), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
leaq .LC3(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
call clock@PLT
movq %rax, %r13
movl $2147483647, %ebp
.L15:
movl (%rbx), %eax
cmpl %eax, %ebp
cmovg %eax, %ebp
addq $4, %rbx
cmpq %r12, %rbx
jne .L15
call clock@PLT
movq %rax, %r12
leaq .LC4(%rip), %rsi
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl %ebp, %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq %r12, %rcx
subq %r13, %rcx
movabsq $2361183241434822607, %rdx
movq %rcx, %rax
imulq %rdx
sarq $7, %rdx
sarq $63, %rcx
subq %rcx, %rdx
movq %rdx, %rsi
movq %rbx, %rdi
call _ZNSo9_M_insertIlEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L22
movl $0, %eax
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L21:
.cfi_restore_state
movl $128, %edx
movq 8(%rsp), %rsi
movq (%rsp), %rdi
call _Z29__device_stub__Z7minimumPiS_iPiS_i
jmp .L14
.L22:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size main, .-main
.section .rodata.str1.1
.LC5:
.string "_Z7minimumPiS_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3697:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _Z7minimumPiS_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
```
|
```amdasm
.text
.file "cuda_max.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z22__device_stub__minimumPiS_i # -- Begin function _Z22__device_stub__minimumPiS_i
.type _Z22__device_stub__minimumPiS_i,@function
_Z22__device_stub__minimumPiS_i: # @_Z22__device_stub__minimumPiS_i
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $112, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 40(%rsp), %rax
movq %rdi, (%rax)
leaq 32(%rsp), %rcx
movq %rsi, (%rcx)
leaq 12(%rsp), %rsi
movl %edx, (%rsi)
leaq 80(%rsp), %rbx
movq %rax, (%rbx)
movq %rcx, 8(%rbx)
movq %rsi, 16(%rbx)
leaq 64(%rsp), %r14
leaq 48(%rsp), %r15
leaq 24(%rsp), %r12
leaq 16(%rsp), %r13
movq %r14, %rdi
movq %r15, %rsi
movq %r12, %rdx
movq %r13, %rcx
callq __hipPopCallConfiguration
movq (%r14), %rsi
movl 8(%r14), %edx
movq (%r15), %rcx
movl 8(%r15), %r8d
movl $_Z7minimumPiS_i, %edi
movq %rbx, %r9
pushq (%r13)
.cfi_adjust_cfa_offset 8
pushq (%r12)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $128, %rsp
.cfi_adjust_cfa_offset -128
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z22__device_stub__minimumPiS_i, .Lfunc_end0-_Z22__device_stub__minimumPiS_i
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $48, %rsp
.cfi_def_cfa_offset 96
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $512, %edi # imm = 0x200
callq malloc
movq %rax, %rbx
xorl %r14d, %r14d
xorl %edi, %edi
callq time
movl %eax, %edi
callq srand
.LBB1_1: # =>This Inner Loop Header: Depth=1
callq rand
movl %eax, (%rbx,%r14,4)
incq %r14
cmpq $128, %r14
jne .LBB1_1
# %bb.2: # %.preheader.preheader
xorl %r14d, %r14d
.LBB1_3: # %.preheader
# =>This Inner Loop Header: Depth=1
movl (%rbx,%r14,4), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movl $.L.str, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
incq %r14
cmpq $128, %r14
jne .LBB1_3
# %bb.4:
movq _ZSt4cout(%rip), %rax
movl $_ZSt4cout, %ecx
movq -24(%rax), %rdi
addq %rcx, %rdi
movl $10, %esi
callq _ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
leaq 16(%rsp), %r15
movq %r15, %rdi
callq hipEventCreate
leaq 8(%rsp), %rdi
callq hipEventCreate
leaq 32(%rsp), %r12
movl $512, %esi # imm = 0x200
movq %r12, %rdi
callq hipMalloc
leaq 24(%rsp), %rdi
movl $4, %esi
callq hipMalloc
movl $4, %edi
callq malloc
movq %rax, %r14
movq (%r12), %rdi
movl $512, %edx # imm = 0x200
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq (%r15), %rdi
xorl %esi, %esi
callq hipEventRecord
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 127(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_6
# %bb.5:
movq 32(%rsp), %rdi
movq 24(%rsp), %rsi
movl $128, %edx
callq _Z22__device_stub__minimumPiS_i
.LBB1_6:
callq hipDeviceSynchronize
movq 24(%rsp), %rsi
movl $4, %edx
movq %r14, %rdi
movl $2, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
xorl %r12d, %r12d
xorl %esi, %esi
callq hipEventRecord
movq 16(%rsp), %rsi
movq 8(%rsp), %rdx
leaq 44(%rsp), %r15
movq %r15, %rdi
callq hipEventElapsedTime
movq 16(%rsp), %rdi
callq hipEventDestroy
movq 8(%rsp), %rdi
callq hipEventDestroy
movl $_ZSt4cout, %edi
movl $.L.str.1, %esi
movl $24, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl (%r14), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movq %rax, %r14
movq (%rax), %rax
movq -24(%rax), %rdi
addq %r14, %rdi
movl $10, %esi
callq _ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
movsbl %al, %esi
movq %r14, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str.2, %esi
movl $19, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
cvtss2sd (%r15), %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq %rax, %r14
movl $.L.str.3, %esi
movl $2, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq (%r14), %rax
movq -24(%rax), %rdi
addq %r14, %rdi
movl $10, %esi
callq _ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
movsbl %al, %esi
movq %r14, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $2147483647, %ebp # imm = 0x7FFFFFFF
callq clock
movq %rax, %r14
.LBB1_7: # =>This Inner Loop Header: Depth=1
movl (%rbx,%r12,4), %eax
cmpl %ebp, %eax
cmovll %eax, %ebp
incq %r12
cmpq $128, %r12
jne .LBB1_7
# %bb.8:
callq clock
movq %rax, %rbx
movl $_ZSt4cout, %edi
movl $.L.str.4, %esi
movl $11, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl %ebp, %esi
callq _ZNSolsEi
movq %rax, %r15
movq (%rax), %rax
movq -24(%rax), %rdi
addq %r15, %rdi
movl $10, %esi
callq _ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
movsbl %al, %esi
movq %r15, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
subq %r14, %rbx
movabsq $2361183241434822607, %rcx # imm = 0x20C49BA5E353F7CF
movq %rbx, %rax
imulq %rcx
movq %rdx, %rsi
shrq $63, %rsi
sarq $7, %rdx
addq %rdx, %rsi
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIlEERSoT_
movq %rax, %rbx
movq (%rax), %rax
movq -24(%rax), %rdi
addq %rbx, %rdi
movl $10, %esi
callq _ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
movsbl %al, %esi
movq %rbx, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
xorl %eax, %eax
addq $48, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, %rdi
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7minimumPiS_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z7minimumPiS_i,@object # @_Z7minimumPiS_i
.section .rodata,"a",@progbits
.globl _Z7minimumPiS_i
.p2align 3, 0x0
_Z7minimumPiS_i:
.quad _Z22__device_stub__minimumPiS_i
.size _Z7minimumPiS_i, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz " "
.size .L.str, 2
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Minimum of the array is "
.size .L.str.1, 25
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "total elapsed time "
.size .L.str.2, 20
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "ms"
.size .L.str.3, 3
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Min by CPU "
.size .L.str.4, 12
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z7minimumPiS_i"
.size .L__unnamed_1, 16
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__minimumPiS_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z7minimumPiS_i
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
```
| 4,159 | 4,909 |
588 |
Convert the following CUDA device assembly code to AMD device assembly:
```cudaasm
code for sm_80
Function : _Z9vectorAddPdS_m
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ;
S2R R0, SR_CTAID.X ;
S2R R3, SR_TID.X ;
IMAD R0, R0, c[0x0][0x0], R3 ;
ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x170], PT ;
SHF.R.S32.HI R3, RZ, 0x1f, R0 ;
ISETP.GE.U32.AND.EX P0, PT, R3, c[0x0][0x174], PT, P0 ;
@P0 EXIT ;
LEA R2, P0, R0, c[0x0][0x168], 0x3 ;
ULDC.64 UR4, c[0x0][0x118] ;
LEA.HI.X R3, R0, c[0x0][0x16c], R3, 0x3, P0 ;
LDG.E.64 R2, [R2.64] ;
IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x160] ;
IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x164] ;
RED.E.ADD.F64.RN.STRONG.GPU [R4.64], R2 ;
EXIT ;
BRA 0x100;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
```
|
```amdasm
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9vectorAddPdS_m ; -- Begin function _Z9vectorAddPdS_m
.globl _Z9vectorAddPdS_m
.p2align 8
.type _Z9vectorAddPdS_m,@function
_Z9vectorAddPdS_m: ; @_Z9vectorAddPdS_m
; %bb.0:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x24
s_load_b64 s[2:3], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1)
v_cmp_gt_u64_e32 vcc_lo, s[2:3], v[1:2]
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_6
; %bb.1:
s_load_b128 s[0:3], s[0:1], 0x0
v_lshlrev_b64 v[0:1], 3, v[1:2]
v_mov_b32_e32 v4, 0
v_bfrev_b32_e32 v5, 1
s_mov_b32 s4, exec_lo
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_3)
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_load_b64 v[0:1], v[0:1], off
.LBB0_2: ; %ComputeLoop
; =>This Inner Loop Header: Depth=1
s_ctz_i32_b32 s5, s4
s_waitcnt vmcnt(0)
v_readlane_b32 s3, v1, s5
v_readlane_b32 s2, v0, s5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_add_f64 v[4:5], v[4:5], s[2:3]
s_lshl_b32 s2, 1, s5
s_and_not1_b32 s4, s4, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_lg_u32 s4, 0
s_cbranch_scc1 .LBB0_2
; %bb.3: ; %ComputeEnd
v_mbcnt_lo_u32_b32 v0, exec_lo, 0
s_mov_b32 s2, 0
s_mov_b32 s3, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_eq_u32_e32 0, v0
s_xor_b32 s3, exec_lo, s3
s_cbranch_execz .LBB0_6
; %bb.4:
s_load_b64 s[4:5], s[0:1], 0x0
v_mov_b32_e32 v6, 0
s_waitcnt lgkmcnt(0)
v_dual_mov_b32 v2, s4 :: v_dual_mov_b32 v3, s5
.LBB0_5: ; %atomicrmw.start
; =>This Inner Loop Header: Depth=1
s_delay_alu instid0(VALU_DEP_1)
v_add_f64 v[0:1], v[2:3], v[4:5]
global_atomic_cmpswap_b64 v[0:1], v6, v[0:3], s[0:1] glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[0:1], v[2:3]
v_dual_mov_b32 v3, v1 :: v_dual_mov_b32 v2, v0
s_or_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s2
s_cbranch_execnz .LBB0_5
.LBB0_6: ; %Flow15
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9vectorAddPdS_m
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9vectorAddPdS_m, .Lfunc_end0-_Z9vectorAddPdS_m
; -- End function
.section .AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 288
; NumSgprs: 18
; NumVgprs: 7
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 7
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object ; @__hip_cuid_
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0 ; 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 8
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9vectorAddPdS_m
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z9vectorAddPdS_m.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
```
| 458 | 2,990 |
589 |
Convert the following CUDA host assembly code to AMD host assembly:
```cudaasm
.file "tmpxft_000cbc17_00000000-6_test.cudafe1.cpp"
.text
.globl _ZSt21ios_base_library_initv
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB4134:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4134:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z31__device_stub__Z9vectorAddPdS_mPdS_m
.type _Z31__device_stub__Z9vectorAddPdS_mPdS_m, @function
_Z31__device_stub__Z9vectorAddPdS_mPdS_m:
.LFB4156:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9vectorAddPdS_m(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4156:
.size _Z31__device_stub__Z9vectorAddPdS_mPdS_m, .-_Z31__device_stub__Z9vectorAddPdS_mPdS_m
.globl _Z9vectorAddPdS_m
.type _Z9vectorAddPdS_m, @function
_Z9vectorAddPdS_m:
.LFB4157:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z31__device_stub__Z9vectorAddPdS_mPdS_m
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4157:
.size _Z9vectorAddPdS_m, .-_Z9vectorAddPdS_m
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z9vectorAddPdS_m"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB4159:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z9vectorAddPdS_m(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4159:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .text._ZNSt6vectorIdSaIdEED2Ev,"axG",@progbits,_ZNSt6vectorIdSaIdEED5Ev,comdat
.align 2
.weak _ZNSt6vectorIdSaIdEED2Ev
.type _ZNSt6vectorIdSaIdEED2Ev, @function
_ZNSt6vectorIdSaIdEED2Ev:
.LFB4497:
.cfi_startproc
endbr64
movq (%rdi), %rax
testq %rax, %rax
je .L16
subq $8, %rsp
.cfi_def_cfa_offset 16
movq 16(%rdi), %rsi
subq %rax, %rsi
movq %rax, %rdi
call _ZdlPvm@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.L16:
ret
.cfi_endproc
.LFE4497:
.size _ZNSt6vectorIdSaIdEED2Ev, .-_ZNSt6vectorIdSaIdEED2Ev
.weak _ZNSt6vectorIdSaIdEED1Ev
.set _ZNSt6vectorIdSaIdEED1Ev,_ZNSt6vectorIdSaIdEED2Ev
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC3:
.string "/home/ubuntu/Datasets/stackv2/train-structured/edofersan/tdo/master/Debug/test.cu"
.align 8
.LC4:
.string "cudaMalloc( (void**)&d_a, sizeof(double) )"
.align 8
.LC5:
.string "CUDA error for %s in %d of %s : %s.\n"
.align 8
.LC6:
.string "cudaMalloc( (void**)&d_b, sizeof(double) * N )"
.align 8
.LC7:
.string "cudaMemcpy( d_a, &a, sizeof(double), cudaMemcpyHostToDevice )"
.align 8
.LC8:
.string "cudaMemcpy( d_b, &b[0], sizeof(double) * N, cudaMemcpyHostToDevice )"
.align 8
.LC9:
.string "cudaMemcpy( &a, d_a, sizeof(double), cudaMemcpyDeviceToHost )"
.text
.globl main
.type main, @function
main:
.LFB4131:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA4131
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
movq %rsp, %rbp
.cfi_def_cfa_register 6
pushq %rbx
subq $88, %rsp
.cfi_offset 3, -24
movq %fs:40, %rax
movq %rax, -24(%rbp)
xorl %eax, %eax
movq $0x000000000, -96(%rbp)
movl $80, %edi
.LEHB0:
call _Znwm@PLT
.LEHE0:
movq %rax, %rbx
movq %rax, -48(%rbp)
leaq 80(%rax), %rdx
movq %rdx, -32(%rbp)
movsd .LC2(%rip), %xmm0
.L20:
movsd %xmm0, (%rax)
addq $8, %rax
cmpq %rdx, %rax
jne .L20
movq %rdx, -40(%rbp)
leaq -88(%rbp), %rdi
movl $8, %esi
.LEHB1:
call cudaMalloc@PLT
testl %eax, %eax
je .L21
movl %eax, %edi
call cudaGetErrorString@PLT
subq $8, %rsp
pushq %rax
leaq .LC3(%rip), %r9
movl $65, %r8d
leaq .LC4(%rip), %rcx
leaq .LC5(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
.cfi_escape 0x2e,0x10
call __fprintf_chk@PLT
addq $16, %rsp
.L21:
leaq -80(%rbp), %rdi
movl $80, %esi
.cfi_escape 0x2e,0
call cudaMalloc@PLT
testl %eax, %eax
je .L22
movl %eax, %edi
call cudaGetErrorString@PLT
subq $8, %rsp
pushq %rax
leaq .LC3(%rip), %r9
movl $66, %r8d
leaq .LC6(%rip), %rcx
leaq .LC5(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
.cfi_escape 0x2e,0x10
call __fprintf_chk@PLT
addq $16, %rsp
.L22:
leaq -96(%rbp), %rsi
movl $1, %ecx
movl $8, %edx
movq -88(%rbp), %rdi
.cfi_escape 0x2e,0
call cudaMemcpy@PLT
testl %eax, %eax
je .L23
movl %eax, %edi
call cudaGetErrorString@PLT
subq $8, %rsp
pushq %rax
leaq .LC3(%rip), %r9
movl $67, %r8d
leaq .LC7(%rip), %rcx
leaq .LC5(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
.cfi_escape 0x2e,0x10
call __fprintf_chk@PLT
addq $16, %rsp
.L23:
movl $1, %ecx
movl $80, %edx
movq %rbx, %rsi
movq -80(%rbp), %rdi
.cfi_escape 0x2e,0
call cudaMemcpy@PLT
testl %eax, %eax
je .L24
movl %eax, %edi
call cudaGetErrorString@PLT
subq $8, %rsp
pushq %rax
leaq .LC3(%rip), %r9
movl $68, %r8d
leaq .LC8(%rip), %rcx
leaq .LC5(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
.cfi_escape 0x2e,0x10
call __fprintf_chk@PLT
addq $16, %rsp
.L24:
movl $10, -60(%rbp)
movl $1, -56(%rbp)
movl $1, -72(%rbp)
movl $1, -68(%rbp)
movl $0, %r9d
movl $0, %r8d
movq -60(%rbp), %rdx
movl $1, %ecx
movq -72(%rbp), %rdi
movl $1, %esi
.cfi_escape 0x2e,0
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L25
movl $10, %edx
movq -80(%rbp), %rsi
movq -88(%rbp), %rdi
call _Z31__device_stub__Z9vectorAddPdS_mPdS_m
.L25:
leaq -96(%rbp), %rdi
movl $2, %ecx
movl $8, %edx
movq -88(%rbp), %rsi
call cudaMemcpy@PLT
testl %eax, %eax
je .L26
movl %eax, %edi
call cudaGetErrorString@PLT
subq $8, %rsp
pushq %rax
leaq .LC3(%rip), %r9
movl $72, %r8d
leaq .LC9(%rip), %rcx
leaq .LC5(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
.cfi_escape 0x2e,0x10
call __fprintf_chk@PLT
addq $16, %rsp
.L26:
movsd -96(%rbp), %xmm0
leaq _ZSt4cout(%rip), %rdi
.cfi_escape 0x2e,0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq -88(%rbp), %rdi
call cudaFree@PLT
movq -80(%rbp), %rdi
call cudaFree@PLT
call cudaDeviceSynchronize@PLT
.LEHE1:
leaq -48(%rbp), %rdi
call _ZNSt6vectorIdSaIdEED1Ev
movq -24(%rbp), %rax
subq %fs:40, %rax
jne .L34
movl $0, %eax
movq -8(%rbp), %rbx
leave
.cfi_remember_state
.cfi_def_cfa 7, 8
ret
.L30:
.cfi_restore_state
endbr64
movq %rax, %rbx
leaq -48(%rbp), %rdi
call _ZNSt6vectorIdSaIdEED1Ev
movq -24(%rbp), %rax
subq %fs:40, %rax
je .L28
call __stack_chk_fail@PLT
.L28:
movq %rbx, %rdi
.LEHB2:
call _Unwind_Resume@PLT
.LEHE2:
.L34:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4131:
.globl __gxx_personality_v0
.section .gcc_except_table,"a",@progbits
.LLSDA4131:
.byte 0xff
.byte 0xff
.byte 0x1
.uleb128 .LLSDACSE4131-.LLSDACSB4131
.LLSDACSB4131:
.uleb128 .LEHB0-.LFB4131
.uleb128 .LEHE0-.LEHB0
.uleb128 0
.uleb128 0
.uleb128 .LEHB1-.LFB4131
.uleb128 .LEHE1-.LEHB1
.uleb128 .L30-.LFB4131
.uleb128 0
.uleb128 .LEHB2-.LFB4131
.uleb128 .LEHE2-.LEHB2
.uleb128 0
.uleb128 0
.LLSDACSE4131:
.text
.size main, .-main
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC2:
.long 0
.long 1072693248
.hidden DW.ref.__gxx_personality_v0
.weak DW.ref.__gxx_personality_v0
.section .data.rel.local.DW.ref.__gxx_personality_v0,"awG",@progbits,DW.ref.__gxx_personality_v0,comdat
.align 8
.type DW.ref.__gxx_personality_v0, @object
.size DW.ref.__gxx_personality_v0, 8
DW.ref.__gxx_personality_v0:
.quad __gxx_personality_v0
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
```
|
```amdasm
.text
.file "test.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z24__device_stub__vectorAddPdS_m # -- Begin function _Z24__device_stub__vectorAddPdS_m
.type _Z24__device_stub__vectorAddPdS_m,@function
_Z24__device_stub__vectorAddPdS_m: # @_Z24__device_stub__vectorAddPdS_m
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $112, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 40(%rsp), %rax
movq %rdi, (%rax)
leaq 32(%rsp), %rcx
movq %rsi, (%rcx)
leaq 24(%rsp), %rsi
movq %rdx, (%rsi)
leaq 80(%rsp), %rbx
movq %rax, (%rbx)
movq %rcx, 8(%rbx)
movq %rsi, 16(%rbx)
leaq 64(%rsp), %r14
leaq 48(%rsp), %r15
leaq 16(%rsp), %r12
leaq 8(%rsp), %r13
movq %r14, %rdi
movq %r15, %rsi
movq %r12, %rdx
movq %r13, %rcx
callq __hipPopCallConfiguration
movq (%r14), %rsi
movl 8(%r14), %edx
movq (%r15), %rcx
movl 8(%r15), %r8d
movl $_Z9vectorAddPdS_m, %edi
movq %rbx, %r9
pushq (%r13)
.cfi_adjust_cfa_offset 8
pushq (%r12)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $128, %rsp
.cfi_adjust_cfa_offset -128
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z24__device_stub__vectorAddPdS_m, .Lfunc_end0-_Z24__device_stub__vectorAddPdS_m
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.type main,@function
main: # @main
.Lfunc_begin0:
.cfi_startproc
.cfi_personality 3, __gxx_personality_v0
.cfi_lsda 3, .Lexception0
# %bb.0: # %.noexc
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $24, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movq $0, 16(%rsp)
movl $80, %edi
callq _Znwm
movq %rax, %rbx
xorl %eax, %eax
movabsq $4607182418800017408, %rcx # imm = 0x3FF0000000000000
.LBB1_1: # %.lr.ph.i.i.i.i.i.i.i.i.i
# =>This Inner Loop Header: Depth=1
movq %rcx, (%rbx,%rax)
addq $8, %rax
cmpq $80, %rax
jne .LBB1_1
# %bb.2: # %_ZNSt6vectorIdSaIdEEC2EmRKdRKS0_.exit
.Ltmp0:
movq %rsp, %rdi
movl $8, %esi
callq hipMalloc
.Ltmp1:
# %bb.3:
testl %eax, %eax
jne .LBB1_4
.LBB1_6:
.Ltmp5:
leaq 8(%rsp), %rdi
movl $80, %esi
callq hipMalloc
.Ltmp6:
# %bb.7:
testl %eax, %eax
jne .LBB1_8
.LBB1_10:
movq (%rsp), %rdi
.Ltmp10:
leaq 16(%rsp), %rsi
movl $8, %edx
movl $1, %ecx
callq hipMemcpy
.Ltmp11:
# %bb.11:
testl %eax, %eax
jne .LBB1_12
.LBB1_14:
movq 8(%rsp), %rdi
.Ltmp15:
movl $80, %edx
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
.Ltmp16:
# %bb.15:
testl %eax, %eax
jne .LBB1_16
.LBB1_18:
.Ltmp20:
movabsq $4294967297, %rdi # imm = 0x100000001
movabsq $4294967306, %rdx # imm = 0x10000000A
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
.Ltmp21:
# %bb.19:
testl %eax, %eax
jne .LBB1_21
# %bb.20:
movq (%rsp), %rdi
movq 8(%rsp), %rsi
.Ltmp22:
movl $10, %edx
callq _Z24__device_stub__vectorAddPdS_m
.Ltmp23:
.LBB1_21:
movq (%rsp), %rsi
.Ltmp24:
leaq 16(%rsp), %rdi
movl $8, %edx
movl $2, %ecx
callq hipMemcpy
.Ltmp25:
# %bb.22:
testl %eax, %eax
jne .LBB1_23
.LBB1_25:
movsd 16(%rsp), %xmm0 # xmm0 = mem[0],zero
.Ltmp29:
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
.Ltmp30:
# %bb.26: # %_ZNSolsEd.exit
movq %rax, %r14
movq (%rax), %rax
movq -24(%rax), %rdi
addq %r14, %rdi
.Ltmp31:
movl $10, %esi
callq _ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
.Ltmp32:
# %bb.27: # %.noexc37
.Ltmp33:
movsbl %al, %esi
movq %r14, %rdi
callq _ZNSo3putEc
.Ltmp34:
# %bb.28: # %.noexc38
.Ltmp35:
movq %rax, %rdi
callq _ZNSo5flushEv
.Ltmp36:
# %bb.29: # %_ZNSolsEPFRSoS_E.exit
movq (%rsp), %rdi
.Ltmp37:
callq hipFree
.Ltmp38:
# %bb.30:
movq 8(%rsp), %rdi
.Ltmp39:
callq hipFree
.Ltmp40:
# %bb.31:
.Ltmp41:
callq hipDeviceSynchronize
.Ltmp42:
# %bb.32: # %_ZNSt6vectorIdSaIdEED2Ev.exit
movq %rbx, %rdi
callq _ZdlPv
xorl %eax, %eax
addq $24, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.LBB1_4:
.cfi_def_cfa_offset 48
movq stderr(%rip), %r14
.Ltmp2:
movl %eax, %edi
callq hipGetErrorString
.Ltmp3:
# %bb.5:
movl $.L.str, %esi
movl $.L.str.1, %edx
movl $.L.str.2, %r8d
movq %r14, %rdi
movl $65, %ecx
movq %rax, %r9
xorl %eax, %eax
callq fprintf
jmp .LBB1_6
.LBB1_8:
movq stderr(%rip), %r14
.Ltmp7:
movl %eax, %edi
callq hipGetErrorString
.Ltmp8:
# %bb.9:
movl $.L.str, %esi
movl $.L.str.3, %edx
movl $.L.str.2, %r8d
movq %r14, %rdi
movl $66, %ecx
movq %rax, %r9
xorl %eax, %eax
callq fprintf
jmp .LBB1_10
.LBB1_12:
movq stderr(%rip), %r14
.Ltmp12:
movl %eax, %edi
callq hipGetErrorString
.Ltmp13:
# %bb.13:
movl $.L.str, %esi
movl $.L.str.4, %edx
movl $.L.str.2, %r8d
movq %r14, %rdi
movl $67, %ecx
movq %rax, %r9
xorl %eax, %eax
callq fprintf
jmp .LBB1_14
.LBB1_16:
movq stderr(%rip), %r14
.Ltmp17:
movl %eax, %edi
callq hipGetErrorString
.Ltmp18:
# %bb.17:
movl $.L.str, %esi
movl $.L.str.5, %edx
movl $.L.str.2, %r8d
movq %r14, %rdi
movl $68, %ecx
movq %rax, %r9
xorl %eax, %eax
callq fprintf
jmp .LBB1_18
.LBB1_23:
movq stderr(%rip), %r14
.Ltmp26:
movl %eax, %edi
callq hipGetErrorString
.Ltmp27:
# %bb.24:
movl $.L.str, %esi
movl $.L.str.6, %edx
movl $.L.str.2, %r8d
movq %r14, %rdi
movl $72, %ecx
movq %rax, %r9
xorl %eax, %eax
callq fprintf
jmp .LBB1_25
.LBB1_39:
.Ltmp28:
jmp .LBB1_34
.LBB1_37:
.Ltmp19:
jmp .LBB1_34
.LBB1_36:
.Ltmp14:
jmp .LBB1_34
.LBB1_35:
.Ltmp9:
jmp .LBB1_34
.LBB1_33:
.Ltmp4:
jmp .LBB1_34
.LBB1_38:
.Ltmp43:
.LBB1_34: # %_ZNSt6vectorIdSaIdEED2Ev.exit35
movq %rax, %r14
movq %rbx, %rdi
callq _ZdlPv
movq %r14, %rdi
callq _Unwind_Resume@PLT
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
.section .gcc_except_table,"a",@progbits
.p2align 2, 0x0
GCC_except_table1:
.Lexception0:
.byte 255 # @LPStart Encoding = omit
.byte 255 # @TType Encoding = omit
.byte 1 # Call site Encoding = uleb128
.uleb128 .Lcst_end0-.Lcst_begin0
.Lcst_begin0:
.uleb128 .Lfunc_begin0-.Lfunc_begin0 # >> Call Site 1 <<
.uleb128 .Ltmp0-.Lfunc_begin0 # Call between .Lfunc_begin0 and .Ltmp0
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp0-.Lfunc_begin0 # >> Call Site 2 <<
.uleb128 .Ltmp1-.Ltmp0 # Call between .Ltmp0 and .Ltmp1
.uleb128 .Ltmp4-.Lfunc_begin0 # jumps to .Ltmp4
.byte 0 # On action: cleanup
.uleb128 .Ltmp5-.Lfunc_begin0 # >> Call Site 3 <<
.uleb128 .Ltmp6-.Ltmp5 # Call between .Ltmp5 and .Ltmp6
.uleb128 .Ltmp9-.Lfunc_begin0 # jumps to .Ltmp9
.byte 0 # On action: cleanup
.uleb128 .Ltmp10-.Lfunc_begin0 # >> Call Site 4 <<
.uleb128 .Ltmp11-.Ltmp10 # Call between .Ltmp10 and .Ltmp11
.uleb128 .Ltmp14-.Lfunc_begin0 # jumps to .Ltmp14
.byte 0 # On action: cleanup
.uleb128 .Ltmp15-.Lfunc_begin0 # >> Call Site 5 <<
.uleb128 .Ltmp16-.Ltmp15 # Call between .Ltmp15 and .Ltmp16
.uleb128 .Ltmp19-.Lfunc_begin0 # jumps to .Ltmp19
.byte 0 # On action: cleanup
.uleb128 .Ltmp20-.Lfunc_begin0 # >> Call Site 6 <<
.uleb128 .Ltmp23-.Ltmp20 # Call between .Ltmp20 and .Ltmp23
.uleb128 .Ltmp43-.Lfunc_begin0 # jumps to .Ltmp43
.byte 0 # On action: cleanup
.uleb128 .Ltmp24-.Lfunc_begin0 # >> Call Site 7 <<
.uleb128 .Ltmp25-.Ltmp24 # Call between .Ltmp24 and .Ltmp25
.uleb128 .Ltmp28-.Lfunc_begin0 # jumps to .Ltmp28
.byte 0 # On action: cleanup
.uleb128 .Ltmp29-.Lfunc_begin0 # >> Call Site 8 <<
.uleb128 .Ltmp42-.Ltmp29 # Call between .Ltmp29 and .Ltmp42
.uleb128 .Ltmp43-.Lfunc_begin0 # jumps to .Ltmp43
.byte 0 # On action: cleanup
.uleb128 .Ltmp2-.Lfunc_begin0 # >> Call Site 9 <<
.uleb128 .Ltmp3-.Ltmp2 # Call between .Ltmp2 and .Ltmp3
.uleb128 .Ltmp4-.Lfunc_begin0 # jumps to .Ltmp4
.byte 0 # On action: cleanup
.uleb128 .Ltmp7-.Lfunc_begin0 # >> Call Site 10 <<
.uleb128 .Ltmp8-.Ltmp7 # Call between .Ltmp7 and .Ltmp8
.uleb128 .Ltmp9-.Lfunc_begin0 # jumps to .Ltmp9
.byte 0 # On action: cleanup
.uleb128 .Ltmp12-.Lfunc_begin0 # >> Call Site 11 <<
.uleb128 .Ltmp13-.Ltmp12 # Call between .Ltmp12 and .Ltmp13
.uleb128 .Ltmp14-.Lfunc_begin0 # jumps to .Ltmp14
.byte 0 # On action: cleanup
.uleb128 .Ltmp17-.Lfunc_begin0 # >> Call Site 12 <<
.uleb128 .Ltmp18-.Ltmp17 # Call between .Ltmp17 and .Ltmp18
.uleb128 .Ltmp19-.Lfunc_begin0 # jumps to .Ltmp19
.byte 0 # On action: cleanup
.uleb128 .Ltmp26-.Lfunc_begin0 # >> Call Site 13 <<
.uleb128 .Ltmp27-.Ltmp26 # Call between .Ltmp26 and .Ltmp27
.uleb128 .Ltmp28-.Lfunc_begin0 # jumps to .Ltmp28
.byte 0 # On action: cleanup
.uleb128 .Ltmp27-.Lfunc_begin0 # >> Call Site 14 <<
.uleb128 .Lfunc_end1-.Ltmp27 # Call between .Ltmp27 and .Lfunc_end1
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.Lcst_end0:
.p2align 2, 0x0
# -- End function
.text
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, %rdi
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9vectorAddPdS_m, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9vectorAddPdS_m,@object # @_Z9vectorAddPdS_m
.section .rodata,"a",@progbits
.globl _Z9vectorAddPdS_m
.p2align 3, 0x0
_Z9vectorAddPdS_m:
.quad _Z24__device_stub__vectorAddPdS_m
.size _Z9vectorAddPdS_m, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "CUDA error for %s in %d of %s : %s.\n"
.size .L.str, 37
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "hipMalloc( (void**)&d_a, sizeof(double) )"
.size .L.str.1, 42
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/edofersan/tdo/master/Debug/test.hip"
.size .L.str.2, 93
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "hipMalloc( (void**)&d_b, sizeof(double) * N )"
.size .L.str.3, 46
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "hipMemcpy( d_a, &a, sizeof(double), hipMemcpyHostToDevice )"
.size .L.str.4, 60
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "hipMemcpy( d_b, &b[0], sizeof(double) * N, hipMemcpyHostToDevice )"
.size .L.str.5, 67
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "hipMemcpy( &a, d_a, sizeof(double), hipMemcpyDeviceToHost )"
.size .L.str.6, 60
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z9vectorAddPdS_m"
.size .L__unnamed_1, 18
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__vectorAddPdS_m
.addrsig_sym __gxx_personality_v0
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Unwind_Resume
.addrsig_sym _Z9vectorAddPdS_m
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
```
| 4,973 | 6,385 |
590 |
Convert the following CUDA device assembly code to AMD device assembly:
```cudaasm
code for sm_80
```
|
```amdasm
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object ; @__hip_cuid_
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0 ; 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
```
| 24 | 306 |
591 |
Convert the following CUDA host assembly code to AMD host assembly:
```cudaasm
.file "tmpxft_00180623_00000000-6_tryMemoryAllocationError.cudafe1.cpp"
.text
.globl _ZSt21ios_base_library_initv
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3674:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3674:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "/home/ubuntu/Datasets/stackv2/train-structured/NeziheSozen/stitching_with_cuda/master/tryMemoryAllocationError/tryMemoryAllocationError.cu"
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "GPUassert: %s %s %d\n"
.section .rodata.str1.8
.align 8
.LC2:
.string "Successfully allocated %zu bytes.\n"
.text
.globl main
.type main, @function
main:
.LFB3670:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $16, %rsp
.cfi_def_cfa_offset 32
movq %fs:40, %rax
movq %rax, 8(%rsp)
xorl %eax, %eax
movq $0, (%rsp)
movq %rsp, %rdi
movl $4000000000, %esi
call cudaMalloc@PLT
testl %eax, %eax
jne .L7
movl $4000000000, %edx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq (%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rax
subq %fs:40, %rax
jne .L8
movl $0, %eax
addq $16, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
movl %eax, %ebx
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $22, %r9d
leaq .LC0(%rip), %r8
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %ebx, %edi
call exit@PLT
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3670:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3697:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
```
|
```amdasm
.text
.file "tryMemoryAllocationError.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl main # -- Begin function main
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
pushq %rax
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movq %rsp, %rdi
movq $0, (%rdi)
movl $4000000000, %esi # imm = 0xEE6B2800
callq hipMalloc
testl %eax, %eax
jne .LBB0_2
# %bb.1: # %_Z9gpuAssert10hipError_tPKcib.exit
movl $.L.str.1, %edi
movl $4000000000, %esi # imm = 0xEE6B2800
xorl %eax, %eax
callq printf
movq (%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.LBB0_2:
.cfi_def_cfa_offset 32
movl %eax, %ebx
movq stderr(%rip), %r14
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.2, %esi
movl $.L.str, %ecx
movq %r14, %rdi
movq %rax, %rdx
movl $24, %r8d
xorl %eax, %eax
callq fprintf
movl %ebx, %edi
callq exit
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/NeziheSozen/stitching_with_cuda/master/tryMemoryAllocationError/tryMemoryAllocationError.hip"
.size .L.str, 150
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Successfully allocated %zu bytes.\n"
.size .L.str.1, 35
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "GPUassert: %s %s %d\n"
.size .L.str.2, 21
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
```
| 1,412 | 929 |
592 |
Convert the following CUDA device assembly code to AMD device assembly:
```cudaasm
code for sm_80
```
|
```amdasm
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object ; @__hip_cuid_
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0 ; 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
```
| 24 | 306 |
593 |
Convert the following CUDA host assembly code to AMD host assembly:
```cudaasm
.file "tmpxft_00079063_00000000-6_cov_matrix.cudafe1.cpp"
.text
.globl _ZSt21ios_base_library_initv
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3807:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3807:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "/home/ubuntu/Datasets/stackv2/train-structured/linanqiu/pwas/master/cov_matrix.cu"
.align 8
.LC1:
.string "Error %s at line %d in file %s\n"
.text
.globl _Z8free_allv
.type _Z8free_allv, @function
_Z8free_allv:
.LFB3800:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq patients_host(%rip), %rdi
call cudaFreeHost@PLT
testl %eax, %eax
jne .L7
movq icds_host(%rip), %rdi
call cudaFreeHost@PLT
testl %eax, %eax
jne .L8
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC0(%rip), %r9
movl $35, %r8d
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L8:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC0(%rip), %r9
movl $36, %r8d
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.cfi_endproc
.LFE3800:
.size _Z8free_allv, .-_Z8free_allv
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3830:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3830:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .rodata.str1.8
.align 8
.LC2:
.string "csv_data/patients_sorted_short.csv"
.section .rodata.str1.1,"aMS",@progbits,1
.LC3:
.string "%d patients read\n"
.LC4:
.string ","
.text
.globl _Z13read_patientsv
.type _Z13read_patientsv, @function
_Z13read_patientsv:
.LFB3801:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA3801
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $560, %rsp
.cfi_def_cfa_offset 608
movq %fs:40, %rax
movq %rax, 552(%rsp)
xorl %eax, %eax
movl $0, patient_count(%rip)
leaq 16(%rsp), %rax
movq %rax, (%rsp)
movq $0, 8(%rsp)
movb $0, 16(%rsp)
leaq 32(%rsp), %rbx
leaq 288(%rsp), %rdi
call _ZNSt8ios_baseC2Ev@PLT
leaq 16+_ZTVSt9basic_iosIcSt11char_traitsIcEE(%rip), %rax
movq %rax, 288(%rsp)
movq $0, 504(%rsp)
movb $0, 512(%rsp)
movb $0, 513(%rsp)
movq $0, 520(%rsp)
movq $0, 528(%rsp)
movq $0, 536(%rsp)
movq $0, 544(%rsp)
movq 8+_ZTTSt14basic_ifstreamIcSt11char_traitsIcEE(%rip), %r12
movq %r12, 32(%rsp)
movq 16+_ZTTSt14basic_ifstreamIcSt11char_traitsIcEE(%rip), %r13
movq -24(%r12), %rax
movq %r13, 32(%rsp,%rax)
movq $0, 40(%rsp)
movq 32(%rsp), %rax
addq -24(%rax), %rbx
movq %rbx, %rdi
movl $0, %esi
.LEHB0:
call _ZNSt9basic_iosIcSt11char_traitsIcEE4initEPSt15basic_streambufIcS1_E@PLT
.LEHE0:
leaq 24+_ZTVSt14basic_ifstreamIcSt11char_traitsIcEE(%rip), %rax
movq %rax, 32(%rsp)
leaq 40(%rax), %rax
movq %rax, 288(%rsp)
leaq 48(%rsp), %rdi
.LEHB1:
call _ZNSt13basic_filebufIcSt11char_traitsIcEEC1Ev@PLT
.LEHE1:
leaq 48(%rsp), %rsi
leaq 288(%rsp), %rdi
.LEHB2:
call _ZNSt9basic_iosIcSt11char_traitsIcEE4initEPSt15basic_streambufIcS1_E@PLT
leaq 48(%rsp), %rdi
movl $8, %edx
leaq .LC2(%rip), %rsi
call _ZNSt13basic_filebufIcSt11char_traitsIcEE4openEPKcSt13_Ios_Openmode@PLT
testq %rax, %rax
je .L60
movq 32(%rsp), %rax
movq -24(%rax), %rax
leaq 32(%rsp,%rax), %rdi
movl $0, %esi
call _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate@PLT
jmp .L13
.L60:
movq 32(%rsp), %rax
movq -24(%rax), %rax
leaq 32(%rsp,%rax), %rdi
movl 32(%rdi), %esi
orl $4, %esi
call _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate@PLT
.LEHE2:
.L13:
leaq 152(%rsp), %rdi
call _ZNKSt12__basic_fileIcE7is_openEv@PLT
testb %al, %al
jne .L14
.L15:
movl patient_count(%rip), %edx
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
.LEHB3:
call __printf_chk@PLT
jmp .L61
.L53:
endbr64
movq %rax, %rbx
leaq 48(%rsp), %rdi
call _ZNSt13basic_filebufIcSt11char_traitsIcEED1Ev@PLT
.L17:
movq %r12, 32(%rsp)
movq -24(%r12), %rax
movq %r13, 32(%rsp,%rax)
movq $0, 40(%rsp)
.L18:
leaq 16+_ZTVSt9basic_iosIcSt11char_traitsIcEE(%rip), %rax
movq %rax, 288(%rsp)
leaq 288(%rsp), %rdi
call _ZNSt8ios_baseD2Ev@PLT
.L19:
movq %rsp, %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
movq 552(%rsp), %rax
subq %fs:40, %rax
je .L48
call __stack_chk_fail@PLT
.L52:
endbr64
movq %rax, %rbx
jmp .L17
.L51:
endbr64
movq %rax, %rbx
jmp .L18
.L14:
movq 32(%rsp), %rax
movq -24(%rax), %rax
movq 272(%rsp,%rax), %rbx
testq %rbx, %rbx
je .L62
cmpb $0, 56(%rbx)
je .L22
movzbl 67(%rbx), %edx
.L23:
movsbl %dl, %edx
movq %rsp, %rsi
leaq 32(%rsp), %rdi
call _ZSt7getlineIcSt11char_traitsIcESaIcEERSt13basic_istreamIT_T0_ES7_RNSt7__cxx1112basic_stringIS4_S5_T1_EES4_@PLT
jmp .L63
.L62:
movq 552(%rsp), %rax
subq %fs:40, %rax
jne .L64
call _ZSt16__throw_bad_castv@PLT
.L64:
call __stack_chk_fail@PLT
.L22:
movq %rbx, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%rbx), %rax
movl $10, %esi
movq %rbx, %rdi
call *48(%rax)
movl %eax, %edx
jmp .L23
.L63:
movq 32(%rsp), %rax
movq -24(%rax), %rax
movq 272(%rsp,%rax), %rbp
testq %rbp, %rbp
je .L24
movq %rsp, %rbx
jmp .L25
.L24:
movq 552(%rsp), %rax
subq %fs:40, %rax
jne .L65
call _ZSt16__throw_bad_castv@PLT
.L50:
endbr64
movq %rax, %rbx
leaq 32(%rsp), %rdi
call _ZNSt14basic_ifstreamIcSt11char_traitsIcEED1Ev@PLT
jmp .L19
.L65:
call __stack_chk_fail@PLT
.L27:
movq %rbp, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq 0(%rbp), %rax
movl $10, %esi
movq %rbp, %rdi
call *48(%rax)
movl %eax, %edx
jmp .L28
.L66:
movq (%rax), %rdx
movq -24(%rdx), %rdx
testb $5, 32(%rax,%rdx)
jne .L15
addl $1, patient_count(%rip)
movq 32(%rsp), %rax
movq -24(%rax), %rax
movq 272(%rsp,%rax), %rbp
testq %rbp, %rbp
je .L24
.L25:
cmpb $0, 56(%rbp)
je .L27
movzbl 67(%rbp), %edx
.L28:
movsbl %dl, %edx
leaq 32(%rsp), %rdi
movq %rbx, %rsi
call _ZSt7getlineIcSt11char_traitsIcESaIcEERSt13basic_istreamIT_T0_ES7_RNSt7__cxx1112basic_stringIS4_S5_T1_EES4_@PLT
jmp .L66
.L61:
movl patient_count(%rip), %eax
leal 0(,%rax,4), %esi
movslq %esi, %rsi
salq $2, %rsi
movl $0, %edx
leaq patients_host(%rip), %rdi
call cudaHostAlloc@PLT
testl %eax, %eax
jne .L67
movl $0, patient_count(%rip)
leaq 288(%rsp), %rdi
movl $0, %esi
call _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate@PLT
jmp .L68
.L67:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC0(%rip), %r9
movl $54, %r8d
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L68:
leaq 32(%rsp), %rdi
movl $0, %edx
movl $0, %esi
call _ZNSi5seekgElSt12_Ios_Seekdir@PLT
leaq 152(%rsp), %rdi
call _ZNKSt12__basic_fileIcE7is_openEv@PLT
testb %al, %al
je .L31
movq 32(%rsp), %rax
movq -24(%rax), %rax
movq 272(%rsp,%rax), %rbx
testq %rbx, %rbx
je .L69
cmpb $0, 56(%rbx)
je .L34
movzbl 67(%rbx), %edx
.L35:
movsbl %dl, %edx
movq %rsp, %rsi
leaq 32(%rsp), %rdi
call _ZSt7getlineIcSt11char_traitsIcESaIcEERSt13basic_istreamIT_T0_ES7_RNSt7__cxx1112basic_stringIS4_S5_T1_EES4_@PLT
jmp .L70
.L69:
movq 552(%rsp), %rax
subq %fs:40, %rax
jne .L71
call _ZSt16__throw_bad_castv@PLT
.L71:
call __stack_chk_fail@PLT
.L34:
movq %rbx, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%rbx), %rax
movl $10, %esi
movq %rbx, %rdi
call *48(%rax)
movl %eax, %edx
jmp .L35
.L70:
movq 32(%rsp), %rax
movq -24(%rax), %rax
movq 272(%rsp,%rax), %rbx
testq %rbx, %rbx
je .L36
leaq .LC4(%rip), %rbp
jmp .L37
.L36:
movq 552(%rsp), %rax
subq %fs:40, %rax
jne .L72
call _ZSt16__throw_bad_castv@PLT
.L72:
call __stack_chk_fail@PLT
.L40:
movq %rbx, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%rbx), %rax
movl $10, %esi
movq %rbx, %rdi
call *48(%rax)
movl %eax, %edx
jmp .L41
.L73:
movq (%rax), %rdx
movq -24(%rdx), %rdx
movl 32(%rax,%rdx), %ebx
andl $5, %ebx
jne .L31
movq (%rsp), %rdi
call strdup@PLT
movq %rax, %rdi
movq %rbp, %rsi
call strtok@PLT
movq %rax, %rdi
.L38:
movl patient_count(%rip), %eax
leal (%rbx,%rax,4), %eax
cltq
movq patients_host(%rip), %rdx
leaq (%rdx,%rax,4), %r14
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movl %eax, (%r14)
movq %rbp, %rsi
movl $0, %edi
call strtok@PLT
movq %rax, %rdi
addl $1, %ebx
cmpl $4, %ebx
jne .L38
addl $1, patient_count(%rip)
movq 32(%rsp), %rax
movq -24(%rax), %rax
movq 272(%rsp,%rax), %rbx
testq %rbx, %rbx
je .L36
.L37:
cmpb $0, 56(%rbx)
je .L40
movzbl 67(%rbx), %edx
.L41:
movsbl %dl, %edx
movq %rsp, %rsi
leaq 32(%rsp), %rdi
call _ZSt7getlineIcSt11char_traitsIcESaIcEERSt13basic_istreamIT_T0_ES7_RNSt7__cxx1112basic_stringIS4_S5_T1_EES4_@PLT
.LEHE3:
jmp .L73
.L31:
leaq 24+_ZTVSt14basic_ifstreamIcSt11char_traitsIcEE(%rip), %rax
movq %rax, 32(%rsp)
leaq 40(%rax), %rax
movq %rax, 288(%rsp)
leaq 16+_ZTVSt13basic_filebufIcSt11char_traitsIcEE(%rip), %rax
movq %rax, 48(%rsp)
leaq 48(%rsp), %rdi
.LEHB4:
call _ZNSt13basic_filebufIcSt11char_traitsIcEE5closeEv@PLT
.LEHE4:
jmp .L46
.L54:
endbr64
movq %rax, %rdi
call __cxa_begin_catch@PLT
call __cxa_end_catch@PLT
.L46:
leaq 152(%rsp), %rdi
call _ZNSt12__basic_fileIcED1Ev@PLT
leaq 16+_ZTVSt15basic_streambufIcSt11char_traitsIcEE(%rip), %rax
movq %rax, 48(%rsp)
leaq 104(%rsp), %rdi
call _ZNSt6localeD1Ev@PLT
movq %r12, 32(%rsp)
movq -24(%r12), %rax
movq %r13, 32(%rsp,%rax)
movq $0, 40(%rsp)
leaq 16+_ZTVSt9basic_iosIcSt11char_traitsIcEE(%rip), %rax
movq %rax, 288(%rsp)
leaq 288(%rsp), %rdi
call _ZNSt8ios_baseD2Ev@PLT
movq (%rsp), %rdi
leaq 16(%rsp), %rax
cmpq %rax, %rdi
je .L11
movq 16(%rsp), %rax
leaq 1(%rax), %rsi
call _ZdlPvm@PLT
.L11:
movq 552(%rsp), %rax
subq %fs:40, %rax
jne .L74
addq $560, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L48:
.cfi_restore_state
movq %rbx, %rdi
.LEHB5:
call _Unwind_Resume@PLT
.LEHE5:
.L74:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3801:
.globl __gxx_personality_v0
.section .gcc_except_table,"a",@progbits
.align 4
.LLSDA3801:
.byte 0xff
.byte 0x9b
.uleb128 .LLSDATT3801-.LLSDATTD3801
.LLSDATTD3801:
.byte 0x1
.uleb128 .LLSDACSE3801-.LLSDACSB3801
.LLSDACSB3801:
.uleb128 .LEHB0-.LFB3801
.uleb128 .LEHE0-.LEHB0
.uleb128 .L51-.LFB3801
.uleb128 0
.uleb128 .LEHB1-.LFB3801
.uleb128 .LEHE1-.LEHB1
.uleb128 .L52-.LFB3801
.uleb128 0
.uleb128 .LEHB2-.LFB3801
.uleb128 .LEHE2-.LEHB2
.uleb128 .L53-.LFB3801
.uleb128 0
.uleb128 .LEHB3-.LFB3801
.uleb128 .LEHE3-.LEHB3
.uleb128 .L50-.LFB3801
.uleb128 0
.uleb128 .LEHB4-.LFB3801
.uleb128 .LEHE4-.LEHB4
.uleb128 .L54-.LFB3801
.uleb128 0x1
.uleb128 .LEHB5-.LFB3801
.uleb128 .LEHE5-.LEHB5
.uleb128 0
.uleb128 0
.LLSDACSE3801:
.byte 0x1
.byte 0
.align 4
.long 0
.LLSDATT3801:
.text
.size _Z13read_patientsv, .-_Z13read_patientsv
.section .rodata.str1.1
.LC5:
.string "csv_data/icds.csv"
.LC6:
.string "%d ICDs read\n"
.text
.globl _Z9read_icdsv
.type _Z9read_icdsv, @function
_Z9read_icdsv:
.LFB3803:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA3803
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $568, %rsp
.cfi_def_cfa_offset 608
movq %fs:40, %rax
movq %rax, 552(%rsp)
xorl %eax, %eax
movl $0, icd_count(%rip)
leaq 16(%rsp), %rax
movq %rax, (%rsp)
movq $0, 8(%rsp)
movb $0, 16(%rsp)
leaq 32(%rsp), %r12
leaq 288(%rsp), %rdi
call _ZNSt8ios_baseC2Ev@PLT
leaq 16+_ZTVSt9basic_iosIcSt11char_traitsIcEE(%rip), %rax
movq %rax, 288(%rsp)
movq $0, 504(%rsp)
movb $0, 512(%rsp)
movb $0, 513(%rsp)
movq $0, 520(%rsp)
movq $0, 528(%rsp)
movq $0, 536(%rsp)
movq $0, 544(%rsp)
movq 8+_ZTTSt14basic_ifstreamIcSt11char_traitsIcEE(%rip), %rbx
movq %rbx, 32(%rsp)
movq 16+_ZTTSt14basic_ifstreamIcSt11char_traitsIcEE(%rip), %rbp
movq -24(%rbx), %rax
movq %rbp, 32(%rsp,%rax)
movq $0, 40(%rsp)
movq 32(%rsp), %rax
movq %r12, %rdi
addq -24(%rax), %rdi
movl $0, %esi
.LEHB6:
call _ZNSt9basic_iosIcSt11char_traitsIcEE4initEPSt15basic_streambufIcS1_E@PLT
.LEHE6:
leaq 24+_ZTVSt14basic_ifstreamIcSt11char_traitsIcEE(%rip), %rax
movq %rax, 32(%rsp)
leaq 40(%rax), %rax
movq %rax, 288(%rsp)
leaq 48(%rsp), %rdi
.LEHB7:
call _ZNSt13basic_filebufIcSt11char_traitsIcEEC1Ev@PLT
.LEHE7:
leaq 48(%rsp), %rsi
leaq 288(%rsp), %rdi
.LEHB8:
call _ZNSt9basic_iosIcSt11char_traitsIcEE4initEPSt15basic_streambufIcS1_E@PLT
leaq 48(%rsp), %rdi
movl $8, %edx
leaq .LC5(%rip), %rsi
call _ZNSt13basic_filebufIcSt11char_traitsIcEE4openEPKcSt13_Ios_Openmode@PLT
testq %rax, %rax
je .L122
movq 32(%rsp), %rax
movq -24(%rax), %rax
leaq 32(%rsp,%rax), %rdi
movl $0, %esi
call _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate@PLT
jmp .L77
.L122:
movq 32(%rsp), %rax
movq -24(%rax), %rax
leaq 32(%rsp,%rax), %rdi
movl 32(%rdi), %esi
orl $4, %esi
call _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate@PLT
.LEHE8:
.L77:
leaq 152(%rsp), %rdi
call _ZNKSt12__basic_fileIcE7is_openEv@PLT
testb %al, %al
jne .L78
.L79:
movl icd_count(%rip), %edx
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
.LEHB9:
call __printf_chk@PLT
jmp .L123
.L116:
endbr64
movq %rax, %r12
leaq 48(%rsp), %rdi
call _ZNSt13basic_filebufIcSt11char_traitsIcEED1Ev@PLT
movq %r12, %rax
.L81:
movq %rbx, 32(%rsp)
movq -24(%rbx), %rdx
movq %rbp, 32(%rsp,%rdx)
movq $0, 40(%rsp)
movq %rax, %rbx
.L82:
leaq 16+_ZTVSt9basic_iosIcSt11char_traitsIcEE(%rip), %rax
movq %rax, 288(%rsp)
leaq 288(%rsp), %rdi
call _ZNSt8ios_baseD2Ev@PLT
.L83:
movq %rsp, %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
movq 552(%rsp), %rax
subq %fs:40, %rax
je .L111
call __stack_chk_fail@PLT
.L115:
endbr64
jmp .L81
.L114:
endbr64
movq %rax, %rbx
jmp .L82
.L78:
movq 32(%rsp), %rax
movq -24(%rax), %rax
movq 272(%rsp,%rax), %r12
testq %r12, %r12
je .L124
cmpb $0, 56(%r12)
je .L86
movzbl 67(%r12), %edx
.L87:
movsbl %dl, %edx
movq %rsp, %rsi
leaq 32(%rsp), %rdi
call _ZSt7getlineIcSt11char_traitsIcESaIcEERSt13basic_istreamIT_T0_ES7_RNSt7__cxx1112basic_stringIS4_S5_T1_EES4_@PLT
jmp .L125
.L124:
movq 552(%rsp), %rax
subq %fs:40, %rax
jne .L126
call _ZSt16__throw_bad_castv@PLT
.L126:
call __stack_chk_fail@PLT
.L86:
movq %r12, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r12), %rax
movl $10, %esi
movq %r12, %rdi
call *48(%rax)
movl %eax, %edx
jmp .L87
.L125:
movq 32(%rsp), %rax
movq -24(%rax), %rax
movq 272(%rsp,%rax), %r13
testq %r13, %r13
je .L88
movq %rsp, %r12
jmp .L89
.L88:
movq 552(%rsp), %rax
subq %fs:40, %rax
jne .L127
call _ZSt16__throw_bad_castv@PLT
.L113:
endbr64
movq %rax, %rbx
leaq 32(%rsp), %rdi
call _ZNSt14basic_ifstreamIcSt11char_traitsIcEED1Ev@PLT
jmp .L83
.L127:
call __stack_chk_fail@PLT
.L91:
movq %r13, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq 0(%r13), %rax
movl $10, %esi
movq %r13, %rdi
call *48(%rax)
movl %eax, %edx
jmp .L92
.L128:
movq (%rax), %rdx
movq -24(%rdx), %rdx
testb $5, 32(%rax,%rdx)
jne .L79
addl $1, icd_count(%rip)
movq 32(%rsp), %rax
movq -24(%rax), %rax
movq 272(%rsp,%rax), %r13
testq %r13, %r13
je .L88
.L89:
cmpb $0, 56(%r13)
je .L91
movzbl 67(%r13), %edx
.L92:
movsbl %dl, %edx
leaq 32(%rsp), %rdi
movq %r12, %rsi
call _ZSt7getlineIcSt11char_traitsIcESaIcEERSt13basic_istreamIT_T0_ES7_RNSt7__cxx1112basic_stringIS4_S5_T1_EES4_@PLT
jmp .L128
.L123:
movslq icd_count(%rip), %rsi
salq $2, %rsi
movl $0, %edx
leaq icds_host(%rip), %rdi
call cudaHostAlloc@PLT
testl %eax, %eax
jne .L129
movl $0, icd_count(%rip)
leaq 288(%rsp), %rdi
movl $0, %esi
call _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate@PLT
jmp .L130
.L129:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC0(%rip), %r9
movl $92, %r8d
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L130:
leaq 32(%rsp), %rdi
movl $0, %edx
movl $0, %esi
call _ZNSi5seekgElSt12_Ios_Seekdir@PLT
leaq 152(%rsp), %rdi
call _ZNKSt12__basic_fileIcE7is_openEv@PLT
testb %al, %al
je .L95
movq 32(%rsp), %rax
movq -24(%rax), %rax
movq 272(%rsp,%rax), %r12
testq %r12, %r12
je .L131
cmpb $0, 56(%r12)
je .L98
movzbl 67(%r12), %edx
.L99:
movsbl %dl, %edx
movq %rsp, %rsi
leaq 32(%rsp), %rdi
call _ZSt7getlineIcSt11char_traitsIcESaIcEERSt13basic_istreamIT_T0_ES7_RNSt7__cxx1112basic_stringIS4_S5_T1_EES4_@PLT
jmp .L132
.L131:
movq 552(%rsp), %rax
subq %fs:40, %rax
jne .L133
call _ZSt16__throw_bad_castv@PLT
.L133:
call __stack_chk_fail@PLT
.L98:
movq %r12, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r12), %rax
movl $10, %esi
movq %r12, %rdi
call *48(%rax)
movl %eax, %edx
jmp .L99
.L132:
movq 32(%rsp), %rax
movq -24(%rax), %rax
movq 272(%rsp,%rax), %r13
testq %r13, %r13
je .L100
leaq .LC4(%rip), %r12
jmp .L101
.L100:
movq 552(%rsp), %rax
subq %fs:40, %rax
jne .L134
call _ZSt16__throw_bad_castv@PLT
.L134:
call __stack_chk_fail@PLT
.L103:
movq %r13, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq 0(%r13), %rax
movl $10, %esi
movq %r13, %rdi
call *48(%rax)
movl %eax, %edx
jmp .L104
.L135:
movq (%rax), %rdx
movq -24(%rdx), %rdx
testb $5, 32(%rax,%rdx)
jne .L95
movq (%rsp), %rdi
call strdup@PLT
movq %rax, %rdi
movq %r12, %rsi
call strtok@PLT
movq %rax, %rdi
movslq icd_count(%rip), %rdx
movq icds_host(%rip), %rax
leaq (%rax,%rdx,4), %r13
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movl %eax, 0(%r13)
addl $1, icd_count(%rip)
movq 32(%rsp), %rax
movq -24(%rax), %rax
movq 272(%rsp,%rax), %r13
testq %r13, %r13
je .L100
.L101:
cmpb $0, 56(%r13)
je .L103
movzbl 67(%r13), %edx
.L104:
movsbl %dl, %edx
movq %rsp, %rsi
leaq 32(%rsp), %rdi
call _ZSt7getlineIcSt11char_traitsIcESaIcEERSt13basic_istreamIT_T0_ES7_RNSt7__cxx1112basic_stringIS4_S5_T1_EES4_@PLT
.LEHE9:
jmp .L135
.L95:
leaq 24+_ZTVSt14basic_ifstreamIcSt11char_traitsIcEE(%rip), %rax
movq %rax, 32(%rsp)
leaq 40(%rax), %rax
movq %rax, 288(%rsp)
leaq 16+_ZTVSt13basic_filebufIcSt11char_traitsIcEE(%rip), %rax
movq %rax, 48(%rsp)
leaq 48(%rsp), %rdi
.LEHB10:
call _ZNSt13basic_filebufIcSt11char_traitsIcEE5closeEv@PLT
.LEHE10:
jmp .L109
.L117:
endbr64
movq %rax, %rdi
call __cxa_begin_catch@PLT
call __cxa_end_catch@PLT
.L109:
leaq 152(%rsp), %rdi
call _ZNSt12__basic_fileIcED1Ev@PLT
leaq 16+_ZTVSt15basic_streambufIcSt11char_traitsIcEE(%rip), %rax
movq %rax, 48(%rsp)
leaq 104(%rsp), %rdi
call _ZNSt6localeD1Ev@PLT
movq %rbx, 32(%rsp)
movq -24(%rbx), %rax
movq %rbp, 32(%rsp,%rax)
movq $0, 40(%rsp)
leaq 16+_ZTVSt9basic_iosIcSt11char_traitsIcEE(%rip), %rax
movq %rax, 288(%rsp)
leaq 288(%rsp), %rdi
call _ZNSt8ios_baseD2Ev@PLT
movq (%rsp), %rdi
leaq 16(%rsp), %rax
cmpq %rax, %rdi
je .L75
movq 16(%rsp), %rax
leaq 1(%rax), %rsi
call _ZdlPvm@PLT
.L75:
movq 552(%rsp), %rax
subq %fs:40, %rax
jne .L136
addq $568, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L111:
.cfi_restore_state
movq %rbx, %rdi
.LEHB11:
call _Unwind_Resume@PLT
.LEHE11:
.L136:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3803:
.section .gcc_except_table
.align 4
.LLSDA3803:
.byte 0xff
.byte 0x9b
.uleb128 .LLSDATT3803-.LLSDATTD3803
.LLSDATTD3803:
.byte 0x1
.uleb128 .LLSDACSE3803-.LLSDACSB3803
.LLSDACSB3803:
.uleb128 .LEHB6-.LFB3803
.uleb128 .LEHE6-.LEHB6
.uleb128 .L114-.LFB3803
.uleb128 0
.uleb128 .LEHB7-.LFB3803
.uleb128 .LEHE7-.LEHB7
.uleb128 .L115-.LFB3803
.uleb128 0
.uleb128 .LEHB8-.LFB3803
.uleb128 .LEHE8-.LEHB8
.uleb128 .L116-.LFB3803
.uleb128 0
.uleb128 .LEHB9-.LFB3803
.uleb128 .LEHE9-.LEHB9
.uleb128 .L113-.LFB3803
.uleb128 0
.uleb128 .LEHB10-.LFB3803
.uleb128 .LEHE10-.LEHB10
.uleb128 .L117-.LFB3803
.uleb128 0x1
.uleb128 .LEHB11-.LFB3803
.uleb128 .LEHE11-.LEHB11
.uleb128 0
.uleb128 0
.LLSDACSE3803:
.byte 0x1
.byte 0
.align 4
.long 0
.LLSDATT3803:
.text
.size _Z9read_icdsv, .-_Z9read_icdsv
.globl main
.type main, @function
main:
.LFB3804:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z13read_patientsv
call _Z9read_icdsv
call _Z8free_allv
movl $0, %eax
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3804:
.size main, .-main
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl icds_host
.bss
.align 8
.type icds_host, @object
.size icds_host, 8
icds_host:
.zero 8
.globl patients_host
.align 8
.type patients_host, @object
.size patients_host, 8
patients_host:
.zero 8
.globl icd_count
.align 4
.type icd_count, @object
.size icd_count, 4
icd_count:
.zero 4
.globl patient_count
.align 4
.type patient_count, @object
.size patient_count, 4
patient_count:
.zero 4
.hidden DW.ref.__gxx_personality_v0
.weak DW.ref.__gxx_personality_v0
.section .data.rel.local.DW.ref.__gxx_personality_v0,"awG",@progbits,DW.ref.__gxx_personality_v0,comdat
.align 8
.type DW.ref.__gxx_personality_v0, @object
.size DW.ref.__gxx_personality_v0, 8
DW.ref.__gxx_personality_v0:
.quad __gxx_personality_v0
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
```
|
```amdasm
.text
.file "cov_matrix.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z8free_allv # -- Begin function _Z8free_allv
.type _Z8free_allv,@function
_Z8free_allv: # @_Z8free_allv
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
movq patients_host(%rip), %rdi
callq hipHostFree
testl %eax, %eax
jne .LBB0_1
# %bb.3:
movq icds_host(%rip), %rdi
callq hipHostFree
testl %eax, %eax
jne .LBB0_4
# %bb.5:
popq %rbx
.cfi_def_cfa_offset 8
retq
.LBB0_1:
.cfi_def_cfa_offset 16
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %esi
movl $.L.str.1, %r8d
movq %rbx, %rdi
movq %rax, %rdx
movl $37, %ecx
jmp .LBB0_2
.LBB0_4:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %esi
movl $.L.str.1, %r8d
movq %rbx, %rdi
movq %rax, %rdx
movl $38, %ecx
.LBB0_2:
xorl %eax, %eax
callq fprintf
movl $1, %edi
callq exit
.Lfunc_end0:
.size _Z8free_allv, .Lfunc_end0-_Z8free_allv
.cfi_endproc
# -- End function
.globl _Z13read_patientsv # -- Begin function _Z13read_patientsv
.type _Z13read_patientsv,@function
_Z13read_patientsv: # @_Z13read_patientsv
.Lfunc_begin0:
.cfi_startproc
.cfi_personality 3, __gxx_personality_v0
.cfi_lsda 3, .Lexception0
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $560, %rsp # imm = 0x230
.cfi_def_cfa_offset 608
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $0, patient_count(%rip)
leaq 24(%rsp), %r13
movq %r13, -16(%r13)
movq $0, -8(%r13)
movb $0, (%r13)
.Ltmp0:
leaq 40(%rsp), %r14
movl $.L.str.2, %esi
movq %r14, %rdi
movl $8, %edx
callq _ZNSt14basic_ifstreamIcSt11char_traitsIcEEC1EPKcSt13_Ios_Openmode
.Ltmp1:
# %bb.1:
leaq 160(%rsp), %rbx
movq %rbx, %rdi
callq _ZNKSt12__basic_fileIcE7is_openEv
testb %al, %al
je .LBB1_12
# %bb.2:
movq 40(%rsp), %rax
movq -24(%rax), %rdi
addq %r14, %rdi
.Ltmp3:
movl $10, %esi
callq _ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
.Ltmp4:
# %bb.3: # %.noexc
.Ltmp5:
movsbl %al, %edx
leaq 40(%rsp), %r15
leaq 8(%rsp), %rsi
movq %r15, %rdi
callq _ZSt7getlineIcSt11char_traitsIcESaIcEERSt13basic_istreamIT_T0_ES7_RNSt7__cxx1112basic_stringIS4_S5_T1_EES4_
.Ltmp6:
# %bb.4: # %_ZSt7getlineIcSt11char_traitsIcESaIcEERSt13basic_istreamIT_T0_ES7_RNSt7__cxx1112basic_stringIS4_S5_T1_EE.exit.preheader
leaq 8(%rsp), %r12
.LBB1_5: # %_ZSt7getlineIcSt11char_traitsIcESaIcEERSt13basic_istreamIT_T0_ES7_RNSt7__cxx1112basic_stringIS4_S5_T1_EE.exit
# =>This Inner Loop Header: Depth=1
movq 40(%rsp), %rax
movq -24(%rax), %rdi
addq %r15, %rdi
.Ltmp7:
movl $10, %esi
callq _ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
.Ltmp8:
# %bb.6: # %.noexc16
# in Loop: Header=BB1_5 Depth=1
.Ltmp9:
movsbl %al, %edx
movq %r15, %rdi
movq %r12, %rsi
callq _ZSt7getlineIcSt11char_traitsIcESaIcEERSt13basic_istreamIT_T0_ES7_RNSt7__cxx1112basic_stringIS4_S5_T1_EES4_
.Ltmp10:
# %bb.7: # in Loop: Header=BB1_5 Depth=1
movq (%rax), %rcx
movq -24(%rcx), %rcx
testb $5, 32(%rax,%rcx)
jne .LBB1_12
# %bb.8: # in Loop: Header=BB1_5 Depth=1
incl patient_count(%rip)
jmp .LBB1_5
.LBB1_12: # %.loopexit33
movl patient_count(%rip), %esi
movl $.L.str.3, %edi
xorl %eax, %eax
callq printf
movslq patient_count(%rip), %rsi
shlq $4, %rsi
.Ltmp12:
movl $patients_host, %edi
xorl %edx, %edx
callq hipHostAlloc
.Ltmp13:
# %bb.13:
testl %eax, %eax
jne .LBB1_14
# %bb.17:
movl $0, patient_count(%rip)
movq 40(%rsp), %rax
addq -24(%rax), %r14
.Ltmp17:
movq %r14, %rdi
xorl %esi, %esi
callq _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate
.Ltmp18:
# %bb.18:
.Ltmp19:
leaq 40(%rsp), %r14
movq %r14, %rdi
xorl %esi, %esi
xorl %edx, %edx
callq _ZNSi5seekgElSt12_Ios_Seekdir
.Ltmp20:
# %bb.19:
movq %rbx, %rdi
callq _ZNKSt12__basic_fileIcE7is_openEv
testb %al, %al
je .LBB1_29
# %bb.20:
movq 40(%rsp), %rax
addq -24(%rax), %r14
.Ltmp21:
movq %r14, %rdi
movl $10, %esi
callq _ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
.Ltmp22:
# %bb.21: # %.noexc19
.Ltmp23:
movsbl %al, %edx
leaq 40(%rsp), %rbx
leaq 8(%rsp), %rsi
movq %rbx, %rdi
callq _ZSt7getlineIcSt11char_traitsIcESaIcEERSt13basic_istreamIT_T0_ES7_RNSt7__cxx1112basic_stringIS4_S5_T1_EES4_
.Ltmp24:
# %bb.22: # %_ZSt7getlineIcSt11char_traitsIcESaIcEERSt13basic_istreamIT_T0_ES7_RNSt7__cxx1112basic_stringIS4_S5_T1_EE.exit21.preheader
leaq 8(%rsp), %r14
.LBB1_23: # %_ZSt7getlineIcSt11char_traitsIcESaIcEERSt13basic_istreamIT_T0_ES7_RNSt7__cxx1112basic_stringIS4_S5_T1_EE.exit21
# =>This Loop Header: Depth=1
# Child Loop BB1_27 Depth 2
movq 40(%rsp), %rax
movq -24(%rax), %rdi
addq %rbx, %rdi
.Ltmp26:
movl $10, %esi
callq _ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
.Ltmp27:
# %bb.24: # %.noexc22
# in Loop: Header=BB1_23 Depth=1
.Ltmp28:
movsbl %al, %edx
movq %rbx, %rdi
movq %r14, %rsi
callq _ZSt7getlineIcSt11char_traitsIcESaIcEERSt13basic_istreamIT_T0_ES7_RNSt7__cxx1112basic_stringIS4_S5_T1_EES4_
.Ltmp29:
# %bb.25: # in Loop: Header=BB1_23 Depth=1
movq (%rax), %rcx
movq -24(%rcx), %rcx
testb $5, 32(%rax,%rcx)
jne .LBB1_29
# %bb.26: # in Loop: Header=BB1_23 Depth=1
movq 8(%rsp), %rdi
callq strdup
movl $.L.str.4, %esi
movq %rax, %rdi
callq strtok
xorl %r15d, %r15d
.LBB1_27: # Parent Loop BB1_23 Depth=1
# => This Inner Loop Header: Depth=2
movq %rax, %rdi
callq atoi
movq patients_host(%rip), %rcx
movslq patient_count(%rip), %rdx
leaq (%r15,%rdx,4), %rdx
movl %eax, (%rcx,%rdx,4)
movl $.L.str.4, %esi
xorl %edi, %edi
callq strtok
incq %r15
cmpl $4, %r15d
jne .LBB1_27
# %bb.28: # in Loop: Header=BB1_23 Depth=1
incl patient_count(%rip)
jmp .LBB1_23
.LBB1_29: # %.loopexit29
leaq 40(%rsp), %rdi
callq _ZNSt14basic_ifstreamIcSt11char_traitsIcEED1Ev
movq 8(%rsp), %rdi
cmpq %r13, %rdi
je .LBB1_31
# %bb.30: # %_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE11_M_is_localEv.exit.i.i
callq _ZdlPv
.LBB1_31: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev.exit
addq $560, %rsp # imm = 0x230
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB1_14:
.cfi_def_cfa_offset 608
movq stderr(%rip), %rbx
.Ltmp14:
movl %eax, %edi
callq hipGetErrorString
.Ltmp15:
# %bb.15:
movl $.L.str, %esi
movl $.L.str.1, %r8d
movq %rbx, %rdi
movq %rax, %rdx
movl $56, %ecx
xorl %eax, %eax
callq fprintf
movl $1, %edi
callq exit
.LBB1_9:
.Ltmp2:
movq %rax, %rbx
jmp .LBB1_34
.LBB1_16:
.Ltmp16:
jmp .LBB1_33
.LBB1_11: # %.loopexit.split-lp.loopexit.split-lp
.Ltmp25:
jmp .LBB1_33
.LBB1_32: # %.loopexit
.Ltmp30:
jmp .LBB1_33
.LBB1_10: # %.loopexit.split-lp.loopexit
.Ltmp11:
.LBB1_33: # %.loopexit.split-lp
movq %rax, %rbx
leaq 40(%rsp), %rdi
callq _ZNSt14basic_ifstreamIcSt11char_traitsIcEED1Ev
.LBB1_34:
movq 8(%rsp), %rdi
cmpq %r13, %rdi
je .LBB1_36
# %bb.35: # %_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE11_M_is_localEv.exit.i.i26
callq _ZdlPv
.LBB1_36: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev.exit28
movq %rbx, %rdi
callq _Unwind_Resume@PLT
.Lfunc_end1:
.size _Z13read_patientsv, .Lfunc_end1-_Z13read_patientsv
.cfi_endproc
.section .gcc_except_table,"a",@progbits
.p2align 2, 0x0
GCC_except_table1:
.Lexception0:
.byte 255 # @LPStart Encoding = omit
.byte 255 # @TType Encoding = omit
.byte 1 # Call site Encoding = uleb128
.uleb128 .Lcst_end0-.Lcst_begin0
.Lcst_begin0:
.uleb128 .Ltmp0-.Lfunc_begin0 # >> Call Site 1 <<
.uleb128 .Ltmp1-.Ltmp0 # Call between .Ltmp0 and .Ltmp1
.uleb128 .Ltmp2-.Lfunc_begin0 # jumps to .Ltmp2
.byte 0 # On action: cleanup
.uleb128 .Ltmp3-.Lfunc_begin0 # >> Call Site 2 <<
.uleb128 .Ltmp6-.Ltmp3 # Call between .Ltmp3 and .Ltmp6
.uleb128 .Ltmp25-.Lfunc_begin0 # jumps to .Ltmp25
.byte 0 # On action: cleanup
.uleb128 .Ltmp7-.Lfunc_begin0 # >> Call Site 3 <<
.uleb128 .Ltmp10-.Ltmp7 # Call between .Ltmp7 and .Ltmp10
.uleb128 .Ltmp11-.Lfunc_begin0 # jumps to .Ltmp11
.byte 0 # On action: cleanup
.uleb128 .Ltmp12-.Lfunc_begin0 # >> Call Site 4 <<
.uleb128 .Ltmp13-.Ltmp12 # Call between .Ltmp12 and .Ltmp13
.uleb128 .Ltmp16-.Lfunc_begin0 # jumps to .Ltmp16
.byte 0 # On action: cleanup
.uleb128 .Ltmp17-.Lfunc_begin0 # >> Call Site 5 <<
.uleb128 .Ltmp24-.Ltmp17 # Call between .Ltmp17 and .Ltmp24
.uleb128 .Ltmp25-.Lfunc_begin0 # jumps to .Ltmp25
.byte 0 # On action: cleanup
.uleb128 .Ltmp26-.Lfunc_begin0 # >> Call Site 6 <<
.uleb128 .Ltmp29-.Ltmp26 # Call between .Ltmp26 and .Ltmp29
.uleb128 .Ltmp30-.Lfunc_begin0 # jumps to .Ltmp30
.byte 0 # On action: cleanup
.uleb128 .Ltmp14-.Lfunc_begin0 # >> Call Site 7 <<
.uleb128 .Ltmp15-.Ltmp14 # Call between .Ltmp14 and .Ltmp15
.uleb128 .Ltmp16-.Lfunc_begin0 # jumps to .Ltmp16
.byte 0 # On action: cleanup
.uleb128 .Ltmp15-.Lfunc_begin0 # >> Call Site 8 <<
.uleb128 .Lfunc_end1-.Ltmp15 # Call between .Ltmp15 and .Lfunc_end1
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.Lcst_end0:
.p2align 2, 0x0
# -- End function
.text
.globl _Z9read_icdsv # -- Begin function _Z9read_icdsv
.type _Z9read_icdsv,@function
_Z9read_icdsv: # @_Z9read_icdsv
.Lfunc_begin1:
.cfi_startproc
.cfi_personality 3, __gxx_personality_v0
.cfi_lsda 3, .Lexception1
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $560, %rsp # imm = 0x230
.cfi_def_cfa_offset 608
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $0, icd_count(%rip)
leaq 24(%rsp), %r13
movq %r13, -16(%r13)
movq $0, -8(%r13)
movb $0, (%r13)
.Ltmp31:
leaq 40(%rsp), %r14
movl $.L.str.5, %esi
movq %r14, %rdi
movl $8, %edx
callq _ZNSt14basic_ifstreamIcSt11char_traitsIcEEC1EPKcSt13_Ios_Openmode
.Ltmp32:
# %bb.1:
leaq 160(%rsp), %rbx
movq %rbx, %rdi
callq _ZNKSt12__basic_fileIcE7is_openEv
testb %al, %al
je .LBB2_12
# %bb.2:
movq 40(%rsp), %rax
movq -24(%rax), %rdi
addq %r14, %rdi
.Ltmp34:
movl $10, %esi
callq _ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
.Ltmp35:
# %bb.3: # %.noexc
.Ltmp36:
movsbl %al, %edx
leaq 40(%rsp), %r15
leaq 8(%rsp), %rsi
movq %r15, %rdi
callq _ZSt7getlineIcSt11char_traitsIcESaIcEERSt13basic_istreamIT_T0_ES7_RNSt7__cxx1112basic_stringIS4_S5_T1_EES4_
.Ltmp37:
# %bb.4: # %_ZSt7getlineIcSt11char_traitsIcESaIcEERSt13basic_istreamIT_T0_ES7_RNSt7__cxx1112basic_stringIS4_S5_T1_EE.exit.preheader
leaq 8(%rsp), %r12
.LBB2_5: # %_ZSt7getlineIcSt11char_traitsIcESaIcEERSt13basic_istreamIT_T0_ES7_RNSt7__cxx1112basic_stringIS4_S5_T1_EE.exit
# =>This Inner Loop Header: Depth=1
movq 40(%rsp), %rax
movq -24(%rax), %rdi
addq %r15, %rdi
.Ltmp38:
movl $10, %esi
callq _ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
.Ltmp39:
# %bb.6: # %.noexc11
# in Loop: Header=BB2_5 Depth=1
.Ltmp40:
movsbl %al, %edx
movq %r15, %rdi
movq %r12, %rsi
callq _ZSt7getlineIcSt11char_traitsIcESaIcEERSt13basic_istreamIT_T0_ES7_RNSt7__cxx1112basic_stringIS4_S5_T1_EES4_
.Ltmp41:
# %bb.7: # in Loop: Header=BB2_5 Depth=1
movq (%rax), %rcx
movq -24(%rcx), %rcx
testb $5, 32(%rax,%rcx)
jne .LBB2_12
# %bb.8: # in Loop: Header=BB2_5 Depth=1
incl icd_count(%rip)
jmp .LBB2_5
.LBB2_12: # %.loopexit28
movl icd_count(%rip), %esi
movl $.L.str.6, %edi
xorl %eax, %eax
callq printf
movslq icd_count(%rip), %rsi
shlq $2, %rsi
.Ltmp43:
movl $icds_host, %edi
xorl %edx, %edx
callq hipHostAlloc
.Ltmp44:
# %bb.13:
testl %eax, %eax
jne .LBB2_14
# %bb.17:
movl $0, icd_count(%rip)
movq 40(%rsp), %rax
addq -24(%rax), %r14
.Ltmp48:
movq %r14, %rdi
xorl %esi, %esi
callq _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate
.Ltmp49:
# %bb.18:
.Ltmp50:
leaq 40(%rsp), %r14
movq %r14, %rdi
xorl %esi, %esi
xorl %edx, %edx
callq _ZNSi5seekgElSt12_Ios_Seekdir
.Ltmp51:
# %bb.19:
movq %rbx, %rdi
callq _ZNKSt12__basic_fileIcE7is_openEv
testb %al, %al
je .LBB2_27
# %bb.20:
movq 40(%rsp), %rax
addq -24(%rax), %r14
.Ltmp52:
movq %r14, %rdi
movl $10, %esi
callq _ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
.Ltmp53:
# %bb.21: # %.noexc14
.Ltmp54:
movsbl %al, %edx
leaq 40(%rsp), %rbx
leaq 8(%rsp), %rsi
movq %rbx, %rdi
callq _ZSt7getlineIcSt11char_traitsIcESaIcEERSt13basic_istreamIT_T0_ES7_RNSt7__cxx1112basic_stringIS4_S5_T1_EES4_
.Ltmp55:
# %bb.22: # %_ZSt7getlineIcSt11char_traitsIcESaIcEERSt13basic_istreamIT_T0_ES7_RNSt7__cxx1112basic_stringIS4_S5_T1_EE.exit16.preheader
leaq 8(%rsp), %r14
.LBB2_23: # %_ZSt7getlineIcSt11char_traitsIcESaIcEERSt13basic_istreamIT_T0_ES7_RNSt7__cxx1112basic_stringIS4_S5_T1_EE.exit16
# =>This Inner Loop Header: Depth=1
movq 40(%rsp), %rax
movq -24(%rax), %rdi
addq %rbx, %rdi
.Ltmp57:
movl $10, %esi
callq _ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
.Ltmp58:
# %bb.24: # %.noexc17
# in Loop: Header=BB2_23 Depth=1
.Ltmp59:
movsbl %al, %edx
movq %rbx, %rdi
movq %r14, %rsi
callq _ZSt7getlineIcSt11char_traitsIcESaIcEERSt13basic_istreamIT_T0_ES7_RNSt7__cxx1112basic_stringIS4_S5_T1_EES4_
.Ltmp60:
# %bb.25: # in Loop: Header=BB2_23 Depth=1
movq (%rax), %rcx
movq -24(%rcx), %rcx
testb $5, 32(%rax,%rcx)
jne .LBB2_27
# %bb.26: # in Loop: Header=BB2_23 Depth=1
movq 8(%rsp), %rdi
callq strdup
movl $.L.str.4, %esi
movq %rax, %rdi
callq strtok
movq %rax, %rdi
callq atoi
movq icds_host(%rip), %rcx
movslq icd_count(%rip), %rdx
movl %eax, (%rcx,%rdx,4)
incl icd_count(%rip)
jmp .LBB2_23
.LBB2_27: # %.loopexit24
leaq 40(%rsp), %rdi
callq _ZNSt14basic_ifstreamIcSt11char_traitsIcEED1Ev
movq 8(%rsp), %rdi
cmpq %r13, %rdi
je .LBB2_29
# %bb.28: # %_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE11_M_is_localEv.exit.i.i
callq _ZdlPv
.LBB2_29: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev.exit
addq $560, %rsp # imm = 0x230
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB2_14:
.cfi_def_cfa_offset 608
movq stderr(%rip), %rbx
.Ltmp45:
movl %eax, %edi
callq hipGetErrorString
.Ltmp46:
# %bb.15:
movl $.L.str, %esi
movl $.L.str.1, %r8d
movq %rbx, %rdi
movq %rax, %rdx
movl $94, %ecx
xorl %eax, %eax
callq fprintf
movl $1, %edi
callq exit
.LBB2_9:
.Ltmp33:
movq %rax, %rbx
jmp .LBB2_32
.LBB2_16:
.Ltmp47:
jmp .LBB2_31
.LBB2_11: # %.loopexit.split-lp.loopexit.split-lp
.Ltmp56:
jmp .LBB2_31
.LBB2_30: # %.loopexit
.Ltmp61:
jmp .LBB2_31
.LBB2_10: # %.loopexit.split-lp.loopexit
.Ltmp42:
.LBB2_31: # %.loopexit.split-lp
movq %rax, %rbx
leaq 40(%rsp), %rdi
callq _ZNSt14basic_ifstreamIcSt11char_traitsIcEED1Ev
.LBB2_32:
movq 8(%rsp), %rdi
cmpq %r13, %rdi
je .LBB2_34
# %bb.33: # %_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE11_M_is_localEv.exit.i.i21
callq _ZdlPv
.LBB2_34: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev.exit23
movq %rbx, %rdi
callq _Unwind_Resume@PLT
.Lfunc_end2:
.size _Z9read_icdsv, .Lfunc_end2-_Z9read_icdsv
.cfi_endproc
.section .gcc_except_table,"a",@progbits
.p2align 2, 0x0
GCC_except_table2:
.Lexception1:
.byte 255 # @LPStart Encoding = omit
.byte 255 # @TType Encoding = omit
.byte 1 # Call site Encoding = uleb128
.uleb128 .Lcst_end1-.Lcst_begin1
.Lcst_begin1:
.uleb128 .Ltmp31-.Lfunc_begin1 # >> Call Site 1 <<
.uleb128 .Ltmp32-.Ltmp31 # Call between .Ltmp31 and .Ltmp32
.uleb128 .Ltmp33-.Lfunc_begin1 # jumps to .Ltmp33
.byte 0 # On action: cleanup
.uleb128 .Ltmp34-.Lfunc_begin1 # >> Call Site 2 <<
.uleb128 .Ltmp37-.Ltmp34 # Call between .Ltmp34 and .Ltmp37
.uleb128 .Ltmp56-.Lfunc_begin1 # jumps to .Ltmp56
.byte 0 # On action: cleanup
.uleb128 .Ltmp38-.Lfunc_begin1 # >> Call Site 3 <<
.uleb128 .Ltmp41-.Ltmp38 # Call between .Ltmp38 and .Ltmp41
.uleb128 .Ltmp42-.Lfunc_begin1 # jumps to .Ltmp42
.byte 0 # On action: cleanup
.uleb128 .Ltmp43-.Lfunc_begin1 # >> Call Site 4 <<
.uleb128 .Ltmp44-.Ltmp43 # Call between .Ltmp43 and .Ltmp44
.uleb128 .Ltmp47-.Lfunc_begin1 # jumps to .Ltmp47
.byte 0 # On action: cleanup
.uleb128 .Ltmp48-.Lfunc_begin1 # >> Call Site 5 <<
.uleb128 .Ltmp55-.Ltmp48 # Call between .Ltmp48 and .Ltmp55
.uleb128 .Ltmp56-.Lfunc_begin1 # jumps to .Ltmp56
.byte 0 # On action: cleanup
.uleb128 .Ltmp57-.Lfunc_begin1 # >> Call Site 6 <<
.uleb128 .Ltmp60-.Ltmp57 # Call between .Ltmp57 and .Ltmp60
.uleb128 .Ltmp61-.Lfunc_begin1 # jumps to .Ltmp61
.byte 0 # On action: cleanup
.uleb128 .Ltmp45-.Lfunc_begin1 # >> Call Site 7 <<
.uleb128 .Ltmp46-.Ltmp45 # Call between .Ltmp45 and .Ltmp46
.uleb128 .Ltmp47-.Lfunc_begin1 # jumps to .Ltmp47
.byte 0 # On action: cleanup
.uleb128 .Ltmp46-.Lfunc_begin1 # >> Call Site 8 <<
.uleb128 .Lfunc_end2-.Ltmp46 # Call between .Ltmp46 and .Lfunc_end2
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.Lcst_end1:
.p2align 2, 0x0
# -- End function
.text
.globl main # -- Begin function main
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
callq _Z13read_patientsv
callq _Z9read_icdsv
callq _Z8free_allv
xorl %eax, %eax
popq %rcx
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
# -- End function
.type patient_count,@object # @patient_count
.bss
.globl patient_count
.p2align 2, 0x0
patient_count:
.long 0 # 0x0
.size patient_count, 4
.type icd_count,@object # @icd_count
.globl icd_count
.p2align 2, 0x0
icd_count:
.long 0 # 0x0
.size icd_count, 4
.type patients_host,@object # @patients_host
.globl patients_host
.p2align 3, 0x0
patients_host:
.quad 0
.size patients_host, 8
.type icds_host,@object # @icds_host
.globl icds_host
.p2align 3, 0x0
icds_host:
.quad 0
.size icds_host, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Error %s at line %d in file %s\n"
.size .L.str, 32
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/linanqiu/pwas/master/cov_matrix.hip"
.size .L.str.1, 93
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "csv_data/patients_sorted_short.csv"
.size .L.str.2, 35
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "%d patients read\n"
.size .L.str.3, 18
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz ","
.size .L.str.4, 2
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "csv_data/icds.csv"
.size .L.str.5, 18
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "%d ICDs read\n"
.size .L.str.6, 14
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __gxx_personality_v0
.addrsig_sym _Unwind_Resume
.addrsig_sym patients_host
.addrsig_sym icds_host
.addrsig_sym __hip_cuid_
```
| 12,499 | 9,882 |
596 |
Convert the following CUDA device assembly code to AMD device assembly:
```cudaasm
code for sm_80
Function : _Z7_dilatePcS_iiiPi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ;
I2F.U32.RP R4, c[0x0][0x170] ;
S2R R0, SR_CTAID.X ;
ISETP.NE.U32.AND P2, PT, RZ, c[0x0][0x170], PT ;
IMAD.MOV.U32 R6, RZ, RZ, c[0x0][0x178] ;
S2R R5, SR_TID.X ;
MUFU.RCP R4, R4 ;
IMAD R0, R0, c[0x0][0x0], R5 ;
IADD3 R2, R4, 0xffffffe, RZ ;
F2I.FTZ.U32.TRUNC.NTZ R3, R2 ;
IMAD.MOV.U32 R2, RZ, RZ, RZ ;
IMAD.MOV R7, RZ, RZ, -R3 ;
IMAD R7, R7, c[0x0][0x170], RZ ;
IMAD.HI.U32 R3, R3, R7, R2 ;
IMAD.HI.U32 R3, R3, R0, RZ ;
IMAD.MOV R5, RZ, RZ, -R3 ;
IMAD R2, R5, c[0x0][0x170], R0 ;
ISETP.GE.U32.AND P0, PT, R2, c[0x0][0x170], PT ;
@P0 IADD3 R2, R2, -c[0x0][0x170], RZ ;
@P0 IADD3 R3, R3, 0x1, RZ ;
ISETP.GE.U32.AND P1, PT, R2, c[0x0][0x170], PT ;
LEA.HI R2, R6, c[0x0][0x178], RZ, 0x1 ;
SHF.R.S32.HI R4, RZ, 0x1, R2 ;
@P1 IADD3 R3, R3, 0x1, RZ ;
@!P2 LOP3.LUT R3, RZ, c[0x0][0x170], RZ, 0x33, !PT ;
ISETP.GE.AND P0, PT, R3, R4, PT ;
IMAD.MOV R5, RZ, RZ, -R3 ;
IMAD R2, R5, c[0x0][0x170], R0 ;
ISETP.LT.OR P0, PT, R2, R4, !P0 ;
@P0 EXIT ;
IMAD.IADD R3, R3, 0x1, R4.reuse ;
IMAD.IADD R2, R2, 0x1, R4 ;
ISETP.GT.AND P0, PT, R3, c[0x0][0x174], PT ;
ISETP.GT.OR P0, PT, R2, c[0x0][0x170], P0 ;
@P0 EXIT ;
IMAD R5, R6, c[0x0][0x178], RZ ;
ULDC.64 UR8, c[0x0][0x118] ;
PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ;
ISETP.NE.AND P1, PT, R5, RZ, PT ;
@!P1 BRA 0x1430 ;
IADD3 R2, R5.reuse, -0x1, RZ ;
UMOV UR4, URZ ;
IMAD.MOV.U32 R3, RZ, RZ, RZ ;
ISETP.GE.U32.AND P0, PT, R2, 0x3, PT ;
LOP3.LUT R2, R5, 0x3, RZ, 0xc0, !PT ;
@!P0 BRA 0x12d0 ;
IMAD.IADD R4, R5, 0x1, -R2 ;
UMOV UR4, URZ ;
IMAD.MOV.U32 R12, RZ, RZ, c[0x0][0x180] ;
IMAD.MOV.U32 R13, RZ, RZ, c[0x0][0x184] ;
ISETP.GT.AND P0, PT, R4, RZ, PT ;
@!P0 BRA 0x1070 ;
ISETP.GT.AND P1, PT, R4, 0xc, PT ;
PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ;
@!P1 BRA 0xbe0 ;
PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ;
LDG.E R5, [R12.64] ;
LDG.E R7, [R12.64+0x4] ;
LDG.E R10, [R12.64+0x8] ;
LDG.E R11, [R12.64+0xc] ;
LDG.E R18, [R12.64+0x10] ;
LDG.E R19, [R12.64+0x14] ;
LDG.E R20, [R12.64+0x18] ;
LDG.E R16, [R12.64+0x1c] ;
LDG.E R23, [R12.64+0x20] ;
LDG.E R29, [R12.64+0x24] ;
LDG.E R14, [R12.64+0x28] ;
LDG.E R21, [R12.64+0x2c] ;
LDG.E R17, [R12.64+0x30] ;
LDG.E R15, [R12.64+0x34] ;
LDG.E R27, [R12.64+0x38] ;
LDG.E R25, [R12.64+0x3c] ;
IMAD.IADD R5, R0, 0x1, R5 ;
IMAD.IADD R7, R0, 0x1, R7 ;
IADD3 R8, P1, R5, c[0x0][0x160], RZ ;
IMAD.X R9, RZ, RZ, c[0x0][0x164], P1 ;
IADD3 R6, P1, R7, c[0x0][0x160], RZ ;
IMAD.IADD R10, R0, 0x1, R10 ;
LDG.E.U8 R5, [R8.64] ;
IMAD.X R7, RZ, RZ, c[0x0][0x164], P1 ;
IADD3 R10, P1, R10, c[0x0][0x160], RZ ;
IMAD.IADD R22, R0, 0x1, R11 ;
LDG.E.U8 R6, [R6.64] ;
IMAD.X R11, RZ, RZ, c[0x0][0x164], P1 ;
IADD3 R8, P1, R22, c[0x0][0x160], RZ ;
IMAD.IADD R18, R0, 0x1, R18 ;
IMAD.X R9, RZ, RZ, c[0x0][0x164], P1 ;
LDG.E.U8 R7, [R10.64] ;
IADD3 R18, P1, R18, c[0x0][0x160], RZ ;
IMAD.IADD R22, R0, 0x1, R19 ;
LDG.E.U8 R8, [R8.64] ;
IMAD.X R19, RZ, RZ, c[0x0][0x164], P1 ;
IADD3 R10, P1, R22, c[0x0][0x160], RZ ;
IMAD.IADD R20, R0, 0x1, R20 ;
LDG.E.U8 R9, [R18.64] ;
IMAD.X R11, RZ, RZ, c[0x0][0x164], P1 ;
IMAD.IADD R16, R0, 0x1, R16 ;
LDG.E.U8 R10, [R10.64] ;
IADD3 R18, P1, R20, c[0x0][0x160], RZ ;
IMAD.IADD R28, R0, 0x1, R23 ;
IMAD.X R19, RZ, RZ, c[0x0][0x164], P1 ;
IADD3 R22, P1, R16, c[0x0][0x160], RZ ;
LDG.E.U8 R11, [R18.64] ;
IMAD.X R23, RZ, RZ, c[0x0][0x164], P1 ;
IADD3 R28, P1, R28, c[0x0][0x160], RZ ;
IMAD.IADD R16, R0, 0x1, R29 ;
LDG.E.U8 R22, [R22.64] ;
IMAD.X R29, RZ, RZ, c[0x0][0x164], P1 ;
IADD3 R18, P1, R16, c[0x0][0x160], RZ ;
IMAD.IADD R14, R0, 0x1, R14 ;
IMAD.X R19, RZ, RZ, c[0x0][0x164], P1 ;
LDG.E.U8 R23, [R28.64] ;
IADD3 R20, P1, R14, c[0x0][0x160], RZ ;
IMAD.IADD R16, R0, 0x1, R21 ;
LDG.E.U8 R24, [R18.64] ;
IMAD.X R21, RZ, RZ, c[0x0][0x164], P1 ;
IADD3 R16, P1, R16, c[0x0][0x160], RZ ;
IMAD.IADD R14, R0, 0x1, R17 ;
LDG.E.U8 R26, [R20.64] ;
IMAD.X R17, RZ, RZ, c[0x0][0x164], P1 ;
IADD3 R14, P1, R14, c[0x0][0x160], RZ ;
IMAD.IADD R29, R0, 0x1, R15 ;
LDG.E.U8 R28, [R16.64] ;
IMAD.X R15, RZ, RZ, c[0x0][0x164], P1 ;
IADD3 R18, P1, R29, c[0x0][0x160], RZ ;
IMAD.IADD R27, R0, 0x1, R27 ;
LDG.E.U8 R14, [R14.64] ;
IMAD.X R19, RZ, RZ, c[0x0][0x164], P1 ;
IADD3 R20, P1, R27, c[0x0][0x160], RZ ;
IMAD.IADD R25, R0, 0x1, R25 ;
LDG.E.U8 R18, [R18.64] ;
IMAD.X R21, RZ, RZ, c[0x0][0x164], P1 ;
IADD3 R16, P1, R25, c[0x0][0x160], RZ ;
LDG.E.U8 R20, [R20.64] ;
IMAD.X R17, RZ, RZ, c[0x0][0x164], P1 ;
LDG.E.U8 R16, [R16.64] ;
IADD3 R4, R4, -0x10, RZ ;
UIADD3 UR4, UR4, 0x10, URZ ;
ISETP.GT.U32.AND P1, PT, R5, 0x64, PT ;
ISETP.GT.U32.AND P2, PT, R6, 0x64, PT ;
IADD3 R5, R3, 0x1, RZ ;
@!P1 IMAD.MOV R5, RZ, RZ, R3 ;
ISETP.GT.U32.AND P1, PT, R7, 0x64, PT ;
IADD3 R3, R5, 0x1, RZ ;
@!P2 IMAD.MOV R3, RZ, RZ, R5 ;
ISETP.GT.U32.AND P2, PT, R8, 0x64, PT ;
IADD3 R5, R3, 0x1, RZ ;
@!P1 IMAD.MOV R5, RZ, RZ, R3 ;
ISETP.GT.U32.AND P1, PT, R9, 0x64, PT ;
IADD3 R3, R5, 0x1, RZ ;
@!P2 IMAD.MOV R3, RZ, RZ, R5 ;
ISETP.GT.U32.AND P2, PT, R10, 0x64, PT ;
IADD3 R5, R3, 0x1, RZ ;
@!P1 IMAD.MOV R5, RZ, RZ, R3 ;
ISETP.GT.U32.AND P1, PT, R11, 0x64, PT ;
IADD3 R3, R5, 0x1, RZ ;
@!P2 IMAD.MOV R3, RZ, RZ, R5 ;
ISETP.GT.U32.AND P2, PT, R22, 0x64, PT ;
IADD3 R5, R3, 0x1, RZ ;
@!P1 IMAD.MOV R5, RZ, RZ, R3 ;
ISETP.GT.U32.AND P1, PT, R23, 0x64, PT ;
IADD3 R3, R5, 0x1, RZ ;
@!P2 IMAD.MOV R3, RZ, RZ, R5 ;
ISETP.GT.U32.AND P2, PT, R24, 0x64, PT ;
IADD3 R5, R3, 0x1, RZ ;
@!P1 IMAD.MOV R5, RZ, RZ, R3 ;
ISETP.GT.U32.AND P1, PT, R26, 0x64, PT ;
IADD3 R3, R5, 0x1, RZ ;
@!P2 IMAD.MOV R3, RZ, RZ, R5 ;
ISETP.GT.U32.AND P2, PT, R28, 0x64, PT ;
IADD3 R5, R3, 0x1, RZ ;
@!P1 IMAD.MOV R5, RZ, RZ, R3 ;
ISETP.GT.U32.AND P1, PT, R14, 0x64, PT ;
IADD3 R3, R5, 0x1, RZ ;
@!P2 IMAD.MOV R3, RZ, RZ, R5 ;
ISETP.GT.U32.AND P2, PT, R18, 0x64, PT ;
IADD3 R5, R3, 0x1, RZ ;
@!P1 IMAD.MOV R5, RZ, RZ, R3 ;
ISETP.GT.U32.AND P3, PT, R20, 0x64, PT ;
IADD3 R3, R5, 0x1, RZ ;
@!P2 IMAD.MOV R3, RZ, RZ, R5 ;
ISETP.GT.AND P2, PT, R4, 0xc, PT ;
ISETP.GT.U32.AND P1, PT, R16, 0x64, PT ;
IADD3 R5, R3, 0x1, RZ ;
@!P3 IMAD.MOV R5, RZ, RZ, R3 ;
IADD3 R12, P3, R12, 0x40, RZ ;
IADD3 R3, R5, 0x1, RZ ;
IMAD.X R13, RZ, RZ, R13, P3 ;
@!P1 IMAD.MOV R3, RZ, RZ, R5 ;
@P2 BRA 0x380 ;
ISETP.GT.AND P1, PT, R4, 0x4, PT ;
@!P1 BRA 0x1050 ;
LDG.E R11, [R12.64] ;
LDG.E R15, [R12.64+0x4] ;
LDG.E R19, [R12.64+0x8] ;
LDG.E R21, [R12.64+0xc] ;
LDG.E R23, [R12.64+0x10] ;
LDG.E R7, [R12.64+0x14] ;
LDG.E R9, [R12.64+0x18] ;
LDG.E R5, [R12.64+0x1c] ;
IMAD.IADD R11, R0, 0x1, R11 ;
IMAD.IADD R15, R0, 0x1, R15 ;
IADD3 R16, P0, R11, c[0x0][0x160], RZ ;
IMAD.X R17, RZ, RZ, c[0x0][0x164], P0 ;
IADD3 R10, P0, R15, c[0x0][0x160], RZ ;
IMAD.IADD R19, R0, 0x1, R19 ;
LDG.E.U8 R8, [R16.64] ;
IMAD.X R11, RZ, RZ, c[0x0][0x164], P0 ;
IADD3 R14, P0, R19, c[0x0][0x160], RZ ;
IMAD.IADD R21, R0, 0x1, R21 ;
LDG.E.U8 R20, [R10.64] ;
IMAD.X R15, RZ, RZ, c[0x0][0x164], P0 ;
IADD3 R18, P0, R21, c[0x0][0x160], RZ ;
IMAD.IADD R23, R0, 0x1, R23 ;
LDG.E.U8 R21, [R14.64] ;
IMAD.X R19, RZ, RZ, c[0x0][0x164], P0 ;
IADD3 R6, P0, R23, c[0x0][0x160], RZ ;
IMAD.IADD R16, R0, 0x1, R7 ;
LDG.E.U8 R18, [R18.64] ;
IMAD.X R7, RZ, RZ, c[0x0][0x164], P0 ;
IADD3 R10, P0, R16, c[0x0][0x160], RZ ;
IMAD.IADD R9, R0, 0x1, R9 ;
LDG.E.U8 R6, [R6.64] ;
IMAD.X R11, RZ, RZ, c[0x0][0x164], P0 ;
IADD3 R14, P0, R9, c[0x0][0x160], RZ ;
IMAD.IADD R5, R0, 0x1, R5 ;
LDG.E.U8 R10, [R10.64] ;
IMAD.X R15, RZ, RZ, c[0x0][0x164], P0 ;
IADD3 R16, P0, R5, c[0x0][0x160], RZ ;
LDG.E.U8 R14, [R14.64] ;
IMAD.X R17, RZ, RZ, c[0x0][0x164], P0 ;
LDG.E.U8 R16, [R16.64] ;
IADD3 R5, R3, 0x1, RZ ;
UIADD3 UR4, UR4, 0x8, URZ ;
IADD3 R12, P2, R12, 0x20, RZ ;
IADD3 R4, R4, -0x8, RZ ;
IMAD.X R13, RZ, RZ, R13, P2 ;
ISETP.GT.U32.AND P0, PT, R8, 0x64, PT ;
ISETP.GT.U32.AND P1, PT, R20, 0x64, PT ;
@!P0 IMAD.MOV R5, RZ, RZ, R3 ;
ISETP.GT.U32.AND P0, PT, R21, 0x64, PT ;
IADD3 R3, R5, 0x1, RZ ;
@!P1 IMAD.MOV R3, RZ, RZ, R5 ;
ISETP.GT.U32.AND P1, PT, R18, 0x64, PT ;
IADD3 R5, R3, 0x1, RZ ;
@!P0 IMAD.MOV R5, RZ, RZ, R3 ;
ISETP.GT.U32.AND P0, PT, R6, 0x64, PT ;
IADD3 R3, R5, 0x1, RZ ;
@!P1 IMAD.MOV R3, RZ, RZ, R5 ;
ISETP.GT.U32.AND P1, PT, R10, 0x64, PT ;
IADD3 R5, R3, 0x1, RZ ;
@!P0 IMAD.MOV R5, RZ, RZ, R3 ;
ISETP.GT.U32.AND P0, PT, R14, 0x64, PT ;
IADD3 R3, R5, 0x1, RZ ;
@!P1 IMAD.MOV R3, RZ, RZ, R5 ;
ISETP.GT.U32.AND P1, PT, R16, 0x64, PT ;
IADD3 R5, R3, 0x1, RZ ;
@!P0 IMAD.MOV R5, RZ, RZ, R3 ;
PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ;
IADD3 R3, R5, 0x1, RZ ;
@!P1 IMAD.MOV R3, RZ, RZ, R5 ;
ISETP.NE.OR P0, PT, R4, RZ, P0 ;
@!P0 BRA 0x12d0 ;
LDG.E R5, [R12.64] ;
LDG.E R7, [R12.64+0x4] ;
LDG.E R9, [R12.64+0x8] ;
LDG.E R11, [R12.64+0xc] ;
IMAD.IADD R5, R0, 0x1, R5 ;
IMAD.IADD R8, R0, 0x1, R7 ;
IADD3 R6, P0, R5, c[0x0][0x160], RZ ;
IMAD.X R7, RZ, RZ, c[0x0][0x164], P0 ;
IADD3 R8, P0, R8, c[0x0][0x160], RZ ;
IMAD.IADD R10, R0, 0x1, R9 ;
LDG.E.U8 R6, [R6.64] ;
IMAD.X R9, RZ, RZ, c[0x0][0x164], P0 ;
IADD3 R10, P0, R10, c[0x0][0x160], RZ ;
IMAD.IADD R14, R0, 0x1, R11 ;
LDG.E.U8 R8, [R8.64] ;
IMAD.X R11, RZ, RZ, c[0x0][0x164], P0 ;
IADD3 R14, P0, R14, c[0x0][0x160], RZ ;
LDG.E.U8 R10, [R10.64] ;
IMAD.X R15, RZ, RZ, c[0x0][0x164], P0 ;
LDG.E.U8 R14, [R14.64] ;
IADD3 R5, R3, 0x1, RZ ;
UIADD3 UR4, UR4, 0x4, URZ ;
IADD3 R4, R4, -0x4, RZ ;
IADD3 R12, P2, R12, 0x10, RZ ;
IMAD.X R13, RZ, RZ, R13, P2 ;
ISETP.GT.U32.AND P0, PT, R6, 0x64, PT ;
ISETP.GT.U32.AND P1, PT, R8, 0x64, PT ;
@!P0 IMAD.MOV R5, RZ, RZ, R3 ;
ISETP.GT.U32.AND P0, PT, R10, 0x64, PT ;
IADD3 R3, R5, 0x1, RZ ;
@!P1 IMAD.MOV R3, RZ, RZ, R5 ;
ISETP.GT.U32.AND P1, PT, R14, 0x64, PT ;
IADD3 R5, R3, 0x1, RZ ;
@!P0 IMAD.MOV R5, RZ, RZ, R3 ;
ISETP.NE.AND P0, PT, R4, RZ, PT ;
IADD3 R3, R5, 0x1, RZ ;
@!P1 IMAD.MOV R3, RZ, RZ, R5 ;
@P0 BRA 0x1070 ;
ISETP.NE.AND P0, PT, R2, RZ, PT ;
@!P0 BRA 0x1420 ;
UMOV UR5, 0x4 ;
ULDC.64 UR6, c[0x0][0x180] ;
UIMAD.WIDE UR4, UR4, UR5, UR6 ;
IMAD.U32 R5, RZ, RZ, UR5 ;
IMAD.U32 R4, RZ, RZ, UR4 ;
LDG.E R5, [R4.64] ;
IMAD.IADD R6, R0, 0x1, R5 ;
IADD3 R6, P0, R6, c[0x0][0x160], RZ ;
IMAD.X R7, RZ, RZ, c[0x0][0x164], P0 ;
LDG.E.U8 R6, [R6.64] ;
IADD3 R2, R2, -0x1, RZ ;
UIADD3 UR4, UP0, UR4, 0x4, URZ ;
IADD3 R8, R3, 0x1, RZ ;
ISETP.NE.AND P1, PT, R2, RZ, PT ;
UIADD3.X UR5, URZ, UR5, URZ, UP0, !UPT ;
ISETP.GT.U32.AND P0, PT, R6, 0x64, PT ;
@!P0 IMAD.MOV R8, RZ, RZ, R3 ;
IMAD.MOV.U32 R3, RZ, RZ, R8 ;
@P1 BRA 0x1320 ;
ISETP.EQ.AND P0, PT, R3, RZ, PT ;
IADD3 R2, P1, R0, c[0x0][0x168], RZ ;
IMAD.MOV.U32 R0, RZ, RZ, 0xff ;
IMAD.X R3, RZ, RZ, c[0x0][0x16c], P1 ;
@!P0 STG.E.U8 [R2.64], R0 ;
@!P0 EXIT ;
STG.E.U8 [R2.64], RZ ;
EXIT ;
BRA 0x14a0;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
Function : _Z6_erodePcS_iiiPi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ;
I2F.U32.RP R4, c[0x0][0x170] ;
S2R R0, SR_CTAID.X ;
ISETP.NE.U32.AND P2, PT, RZ, c[0x0][0x170], PT ;
IMAD.MOV.U32 R6, RZ, RZ, c[0x0][0x178] ;
S2R R5, SR_TID.X ;
MUFU.RCP R4, R4 ;
IMAD R0, R0, c[0x0][0x0], R5 ;
IADD3 R2, R4, 0xffffffe, RZ ;
F2I.FTZ.U32.TRUNC.NTZ R3, R2 ;
IMAD.MOV.U32 R2, RZ, RZ, RZ ;
IMAD.MOV R7, RZ, RZ, -R3 ;
IMAD R7, R7, c[0x0][0x170], RZ ;
IMAD.HI.U32 R3, R3, R7, R2 ;
IMAD.HI.U32 R3, R3, R0, RZ ;
IMAD.MOV R5, RZ, RZ, -R3 ;
IMAD R2, R5, c[0x0][0x170], R0 ;
ISETP.GE.U32.AND P0, PT, R2, c[0x0][0x170], PT ;
@P0 IADD3 R2, R2, -c[0x0][0x170], RZ ;
@P0 IADD3 R3, R3, 0x1, RZ ;
ISETP.GE.U32.AND P1, PT, R2, c[0x0][0x170], PT ;
LEA.HI R2, R6, c[0x0][0x178], RZ, 0x1 ;
SHF.R.S32.HI R4, RZ, 0x1, R2 ;
@P1 IADD3 R3, R3, 0x1, RZ ;
@!P2 LOP3.LUT R3, RZ, c[0x0][0x170], RZ, 0x33, !PT ;
ISETP.GE.AND P0, PT, R3, R4, PT ;
IMAD.MOV R5, RZ, RZ, -R3 ;
IMAD R2, R5, c[0x0][0x170], R0 ;
ISETP.LT.OR P0, PT, R2, R4, !P0 ;
@P0 EXIT ;
IMAD.IADD R3, R3, 0x1, R4.reuse ;
IMAD.IADD R2, R2, 0x1, R4 ;
ISETP.GT.AND P0, PT, R3, c[0x0][0x174], PT ;
ISETP.GT.OR P0, PT, R2, c[0x0][0x170], P0 ;
@P0 EXIT ;
IMAD R2, R6, c[0x0][0x178], RZ ;
ULDC.64 UR8, c[0x0][0x118] ;
IMAD.MOV.U32 R5, RZ, RZ, RZ ;
ISETP.NE.AND P0, PT, R2, RZ, PT ;
@!P0 BRA 0x1420 ;
IADD3 R3, R2.reuse, -0x1, RZ ;
UMOV UR4, URZ ;
IMAD.MOV.U32 R5, RZ, RZ, RZ ;
ISETP.GE.U32.AND P0, PT, R3, 0x3, PT ;
LOP3.LUT R3, R2, 0x3, RZ, 0xc0, !PT ;
@!P0 BRA 0x12d0 ;
IMAD.IADD R4, R2, 0x1, -R3 ;
UMOV UR4, URZ ;
IMAD.MOV.U32 R12, RZ, RZ, c[0x0][0x180] ;
IMAD.MOV.U32 R13, RZ, RZ, c[0x0][0x184] ;
ISETP.GT.AND P0, PT, R4, RZ, PT ;
@!P0 BRA 0x1070 ;
ISETP.GT.AND P1, PT, R4, 0xc, PT ;
PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ;
@!P1 BRA 0xbe0 ;
PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ;
LDG.E R7, [R12.64] ;
LDG.E R8, [R12.64+0x4] ;
LDG.E R29, [R12.64+0x8] ;
LDG.E R9, [R12.64+0xc] ;
LDG.E R10, [R12.64+0x10] ;
LDG.E R11, [R12.64+0x14] ;
LDG.E R18, [R12.64+0x18] ;
LDG.E R23, [R12.64+0x1c] ;
LDG.E R16, [R12.64+0x20] ;
LDG.E R25, [R12.64+0x24] ;
LDG.E R14, [R12.64+0x28] ;
LDG.E R21, [R12.64+0x2c] ;
LDG.E R19, [R12.64+0x30] ;
LDG.E R15, [R12.64+0x34] ;
LDG.E R17, [R12.64+0x38] ;
LDG.E R27, [R12.64+0x3c] ;
IMAD.IADD R7, R0, 0x1, R7 ;
IMAD.IADD R8, R0, 0x1, R8 ;
IADD3 R6, P1, R7, c[0x0][0x160], RZ ;
IMAD.X R7, RZ, RZ, c[0x0][0x164], P1 ;
IADD3 R28, P1, R8, c[0x0][0x160], RZ ;
IMAD.IADD R8, R0, 0x1, R29 ;
LDG.E.U8 R6, [R6.64] ;
IMAD.X R29, RZ, RZ, c[0x0][0x164], P1 ;
IADD3 R8, P1, R8, c[0x0][0x160], RZ ;
IMAD.IADD R20, R0, 0x1, R9 ;
IMAD.X R9, RZ, RZ, c[0x0][0x164], P1 ;
LDG.E.U8 R7, [R28.64] ;
IMAD.IADD R10, R0, 0x1, R10 ;
LDG.E.U8 R8, [R8.64] ;
IADD3 R28, P1, R20, c[0x0][0x160], RZ ;
IMAD.IADD R20, R0, 0x1, R11 ;
IMAD.X R29, RZ, RZ, c[0x0][0x164], P1 ;
IADD3 R10, P1, R10, c[0x0][0x160], RZ ;
LDG.E.U8 R9, [R28.64] ;
IMAD.X R11, RZ, RZ, c[0x0][0x164], P1 ;
IMAD.IADD R18, R0, 0x1, R18 ;
LDG.E.U8 R10, [R10.64] ;
IADD3 R28, P1, R20, c[0x0][0x160], RZ ;
IMAD.X R29, RZ, RZ, c[0x0][0x164], P1 ;
IADD3 R22, P1, R18, c[0x0][0x160], RZ ;
IMAD.IADD R18, R0, 0x1, R23 ;
LDG.E.U8 R11, [R28.64] ;
IMAD.X R23, RZ, RZ, c[0x0][0x164], P1 ;
IMAD.IADD R16, R0, 0x1, R16 ;
LDG.E.U8 R22, [R22.64] ;
IADD3 R28, P1, R18, c[0x0][0x160], RZ ;
IMAD.X R29, RZ, RZ, c[0x0][0x164], P1 ;
IADD3 R24, P1, R16, c[0x0][0x160], RZ ;
IMAD.IADD R16, R0, 0x1, R25 ;
LDG.E.U8 R23, [R28.64] ;
IMAD.X R25, RZ, RZ, c[0x0][0x164], P1 ;
IMAD.IADD R14, R0, 0x1, R14 ;
LDG.E.U8 R24, [R24.64] ;
IADD3 R28, P1, R16, c[0x0][0x160], RZ ;
IMAD.IADD R18, R0, 0x1, R21 ;
IMAD.X R29, RZ, RZ, c[0x0][0x164], P1 ;
IADD3 R20, P1, R14, c[0x0][0x160], RZ ;
LDG.E.U8 R25, [R28.64] ;
IMAD.X R21, RZ, RZ, c[0x0][0x164], P1 ;
IADD3 R18, P1, R18, c[0x0][0x160], RZ ;
IMAD.IADD R14, R0, 0x1, R19 ;
LDG.E.U8 R26, [R20.64] ;
IMAD.X R19, RZ, RZ, c[0x0][0x164], P1 ;
IADD3 R14, P1, R14, c[0x0][0x160], RZ ;
IMAD.IADD R16, R0, 0x1, R15 ;
LDG.E.U8 R28, [R18.64] ;
IMAD.X R15, RZ, RZ, c[0x0][0x164], P1 ;
IADD3 R16, P1, R16, c[0x0][0x160], RZ ;
IMAD.IADD R29, R0, 0x1, R17 ;
LDG.E.U8 R14, [R14.64] ;
IMAD.X R17, RZ, RZ, c[0x0][0x164], P1 ;
IADD3 R20, P1, R29, c[0x0][0x160], RZ ;
IMAD.IADD R27, R0, 0x1, R27 ;
LDG.E.U8 R16, [R16.64] ;
IMAD.X R21, RZ, RZ, c[0x0][0x164], P1 ;
IADD3 R18, P1, R27, c[0x0][0x160], RZ ;
LDG.E.U8 R20, [R20.64] ;
IMAD.X R19, RZ, RZ, c[0x0][0x164], P1 ;
LDG.E.U8 R18, [R18.64] ;
IADD3 R4, R4, -0x10, RZ ;
UIADD3 UR4, UR4, 0x10, URZ ;
ISETP.GT.U32.AND P1, PT, R6, 0x64, PT ;
IADD3 R6, R5, 0x1, RZ ;
ISETP.GT.U32.AND P2, PT, R7, 0x64, PT ;
@!P1 IMAD.MOV R6, RZ, RZ, R5 ;
ISETP.GT.U32.AND P1, PT, R8, 0x64, PT ;
IADD3 R5, R6, 0x1, RZ ;
@!P2 IMAD.MOV R5, RZ, RZ, R6 ;
ISETP.GT.U32.AND P2, PT, R9, 0x64, PT ;
IADD3 R6, R5, 0x1, RZ ;
@!P1 IMAD.MOV R6, RZ, RZ, R5 ;
ISETP.GT.U32.AND P1, PT, R10, 0x64, PT ;
IADD3 R5, R6, 0x1, RZ ;
@!P2 IMAD.MOV R5, RZ, RZ, R6 ;
ISETP.GT.U32.AND P2, PT, R11, 0x64, PT ;
IADD3 R6, R5, 0x1, RZ ;
@!P1 IMAD.MOV R6, RZ, RZ, R5 ;
ISETP.GT.U32.AND P1, PT, R22, 0x64, PT ;
IADD3 R5, R6, 0x1, RZ ;
@!P2 IMAD.MOV R5, RZ, RZ, R6 ;
ISETP.GT.U32.AND P2, PT, R23, 0x64, PT ;
IADD3 R6, R5, 0x1, RZ ;
@!P1 IMAD.MOV R6, RZ, RZ, R5 ;
ISETP.GT.U32.AND P1, PT, R24, 0x64, PT ;
IADD3 R5, R6, 0x1, RZ ;
@!P2 IMAD.MOV R5, RZ, RZ, R6 ;
ISETP.GT.U32.AND P2, PT, R25, 0x64, PT ;
IADD3 R6, R5, 0x1, RZ ;
@!P1 IMAD.MOV R6, RZ, RZ, R5 ;
ISETP.GT.U32.AND P1, PT, R26, 0x64, PT ;
IADD3 R5, R6, 0x1, RZ ;
@!P2 IMAD.MOV R5, RZ, RZ, R6 ;
ISETP.GT.U32.AND P2, PT, R28, 0x64, PT ;
IADD3 R6, R5, 0x1, RZ ;
@!P1 IMAD.MOV R6, RZ, RZ, R5 ;
ISETP.GT.U32.AND P1, PT, R14, 0x64, PT ;
IADD3 R5, R6, 0x1, RZ ;
@!P2 IMAD.MOV R5, RZ, RZ, R6 ;
ISETP.GT.U32.AND P2, PT, R16, 0x64, PT ;
IADD3 R6, R5, 0x1, RZ ;
@!P1 IMAD.MOV R6, RZ, RZ, R5 ;
ISETP.GT.U32.AND P3, PT, R20, 0x64, PT ;
IADD3 R5, R6, 0x1, RZ ;
@!P2 IMAD.MOV R5, RZ, RZ, R6 ;
ISETP.GT.AND P2, PT, R4, 0xc, PT ;
ISETP.GT.U32.AND P1, PT, R18, 0x64, PT ;
IADD3 R6, R5, 0x1, RZ ;
@!P3 IMAD.MOV R6, RZ, RZ, R5 ;
IADD3 R12, P3, R12, 0x40, RZ ;
IADD3 R5, R6, 0x1, RZ ;
IMAD.X R13, RZ, RZ, R13, P3 ;
@!P1 IMAD.MOV R5, RZ, RZ, R6 ;
@P2 BRA 0x380 ;
ISETP.GT.AND P1, PT, R4, 0x4, PT ;
@!P1 BRA 0x1050 ;
LDG.E R7, [R12.64] ;
LDG.E R19, [R12.64+0x4] ;
LDG.E R21, [R12.64+0x8] ;
LDG.E R23, [R12.64+0xc] ;
LDG.E R9, [R12.64+0x10] ;
LDG.E R11, [R12.64+0x14] ;
LDG.E R15, [R12.64+0x18] ;
LDG.E R17, [R12.64+0x1c] ;
IMAD.IADD R7, R0, 0x1, R7 ;
IMAD.IADD R20, R0, 0x1, R19 ;
IADD3 R18, P0, R7, c[0x0][0x160], RZ ;
IMAD.X R19, RZ, RZ, c[0x0][0x164], P0 ;
IADD3 R20, P0, R20, c[0x0][0x160], RZ ;
IMAD.IADD R6, R0, 0x1, R21 ;
LDG.E.U8 R18, [R18.64] ;
IMAD.X R21, RZ, RZ, c[0x0][0x164], P0 ;
IADD3 R6, P0, R6, c[0x0][0x160], RZ ;
IMAD.IADD R23, R0, 0x1, R23 ;
LDG.E.U8 R20, [R20.64] ;
IMAD.X R7, RZ, RZ, c[0x0][0x164], P0 ;
IADD3 R8, P0, R23, c[0x0][0x160], RZ ;
IMAD.IADD R10, R0, 0x1, R9 ;
LDG.E.U8 R16, [R6.64] ;
IMAD.X R9, RZ, RZ, c[0x0][0x164], P0 ;
IADD3 R10, P0, R10, c[0x0][0x160], RZ ;
IMAD.IADD R14, R0, 0x1, R11 ;
LDG.E.U8 R19, [R8.64] ;
IMAD.X R11, RZ, RZ, c[0x0][0x164], P0 ;
IADD3 R14, P0, R14, c[0x0][0x160], RZ ;
IMAD.IADD R21, R0, 0x1, R15 ;
LDG.E.U8 R11, [R10.64] ;
IMAD.X R15, RZ, RZ, c[0x0][0x164], P0 ;
IADD3 R6, P0, R21, c[0x0][0x160], RZ ;
IMAD.IADD R17, R0, 0x1, R17 ;
LDG.E.U8 R14, [R14.64] ;
IMAD.X R7, RZ, RZ, c[0x0][0x164], P0 ;
IADD3 R8, P0, R17, c[0x0][0x160], RZ ;
LDG.E.U8 R7, [R6.64] ;
IMAD.X R9, RZ, RZ, c[0x0][0x164], P0 ;
LDG.E.U8 R8, [R8.64] ;
IADD3 R10, R5, 0x1, RZ ;
UIADD3 UR4, UR4, 0x8, URZ ;
IADD3 R12, P2, R12, 0x20, RZ ;
IADD3 R4, R4, -0x8, RZ ;
IMAD.X R13, RZ, RZ, R13, P2 ;
ISETP.GT.U32.AND P0, PT, R18, 0x64, PT ;
ISETP.GT.U32.AND P1, PT, R20, 0x64, PT ;
@!P0 IMAD.MOV R10, RZ, RZ, R5 ;
ISETP.GT.U32.AND P0, PT, R16, 0x64, PT ;
IADD3 R5, R10, 0x1, RZ ;
@!P1 IMAD.MOV R5, RZ, RZ, R10 ;
ISETP.GT.U32.AND P1, PT, R19, 0x64, PT ;
IADD3 R6, R5, 0x1, RZ ;
@!P0 IMAD.MOV R6, RZ, RZ, R5 ;
ISETP.GT.U32.AND P0, PT, R11, 0x64, PT ;
IADD3 R5, R6, 0x1, RZ ;
@!P1 IMAD.MOV R5, RZ, RZ, R6 ;
ISETP.GT.U32.AND P1, PT, R14, 0x64, PT ;
IADD3 R6, R5, 0x1, RZ ;
@!P0 IMAD.MOV R6, RZ, RZ, R5 ;
ISETP.GT.U32.AND P0, PT, R7, 0x64, PT ;
IADD3 R5, R6, 0x1, RZ ;
@!P1 IMAD.MOV R5, RZ, RZ, R6 ;
ISETP.GT.U32.AND P1, PT, R8, 0x64, PT ;
IADD3 R6, R5, 0x1, RZ ;
@!P0 IMAD.MOV R6, RZ, RZ, R5 ;
PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ;
IADD3 R5, R6, 0x1, RZ ;
@!P1 IMAD.MOV R5, RZ, RZ, R6 ;
ISETP.NE.OR P0, PT, R4, RZ, P0 ;
@!P0 BRA 0x12d0 ;
LDG.E R7, [R12.64] ;
LDG.E R9, [R12.64+0x4] ;
LDG.E R11, [R12.64+0x8] ;
LDG.E R15, [R12.64+0xc] ;
IMAD.IADD R7, R0, 0x1, R7 ;
IMAD.IADD R9, R0, 0x1, R9 ;
IADD3 R6, P0, R7, c[0x0][0x160], RZ ;
IMAD.X R7, RZ, RZ, c[0x0][0x164], P0 ;
IADD3 R8, P0, R9, c[0x0][0x160], RZ ;
IMAD.IADD R11, R0, 0x1, R11 ;
LDG.E.U8 R6, [R6.64] ;
IMAD.X R9, RZ, RZ, c[0x0][0x164], P0 ;
IADD3 R10, P0, R11, c[0x0][0x160], RZ ;
LDG.E.U8 R8, [R8.64] ;
IMAD.X R11, RZ, RZ, c[0x0][0x164], P0 ;
IMAD.IADD R15, R0, 0x1, R15 ;
LDG.E.U8 R10, [R10.64] ;
IADD3 R14, P0, R15, c[0x0][0x160], RZ ;
IMAD.X R15, RZ, RZ, c[0x0][0x164], P0 ;
LDG.E.U8 R14, [R14.64] ;
IADD3 R4, R4, -0x4, RZ ;
IADD3 R12, P2, R12, 0x10, RZ ;
UIADD3 UR4, UR4, 0x4, URZ ;
IMAD.X R13, RZ, RZ, R13, P2 ;
ISETP.GT.U32.AND P0, PT, R6, 0x64, PT ;
IADD3 R6, R5, 0x1, RZ ;
ISETP.GT.U32.AND P1, PT, R8, 0x64, PT ;
@!P0 IMAD.MOV R6, RZ, RZ, R5 ;
ISETP.GT.U32.AND P0, PT, R10, 0x64, PT ;
IADD3 R5, R6, 0x1, RZ ;
@!P1 IMAD.MOV R5, RZ, RZ, R6 ;
IADD3 R6, R5, 0x1, RZ ;
@!P0 IMAD.MOV R6, RZ, RZ, R5 ;
ISETP.NE.AND P0, PT, R4, RZ, PT ;
ISETP.GT.U32.AND P1, PT, R14, 0x64, PT ;
IADD3 R5, R6, 0x1, RZ ;
@!P1 IMAD.MOV R5, RZ, RZ, R6 ;
@P0 BRA 0x1070 ;
ISETP.NE.AND P0, PT, R3, RZ, PT ;
@!P0 BRA 0x1420 ;
UMOV UR5, 0x4 ;
ULDC.64 UR6, c[0x0][0x180] ;
UIMAD.WIDE UR4, UR4, UR5, UR6 ;
IMAD.U32 R7, RZ, RZ, UR5 ;
IMAD.U32 R6, RZ, RZ, UR4 ;
LDG.E R7, [R6.64] ;
IMAD.IADD R8, R0, 0x1, R7 ;
IADD3 R8, P0, R8, c[0x0][0x160], RZ ;
IMAD.X R9, RZ, RZ, c[0x0][0x164], P0 ;
LDG.E.U8 R8, [R8.64] ;
IADD3 R3, R3, -0x1, RZ ;
UIADD3 UR4, UP0, UR4, 0x4, URZ ;
IADD3 R4, R5, 0x1, RZ ;
ISETP.NE.AND P1, PT, R3, RZ, PT ;
UIADD3.X UR5, URZ, UR5, URZ, UP0, !UPT ;
ISETP.GT.U32.AND P0, PT, R8, 0x64, PT ;
@!P0 IMAD.MOV R4, RZ, RZ, R5 ;
IMAD.MOV.U32 R5, RZ, RZ, R4 ;
@P1 BRA 0x1320 ;
ISETP.NE.AND P0, PT, R5, R2, PT ;
IADD3 R2, P1, R0, c[0x0][0x168], RZ ;
IMAD.X R3, RZ, RZ, c[0x0][0x16c], P1 ;
@P0 STG.E.U8 [R2.64], RZ ;
@P0 EXIT ;
IMAD.MOV.U32 R0, RZ, RZ, 0xff ;
STG.E.U8 [R2.64], R0 ;
EXIT ;
BRA 0x14a0;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
```
|
```amdasm
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6_erodePcS_iiiPi ; -- Begin function _Z6_erodePcS_iiiPi
.globl _Z6_erodePcS_iiiPi
.p2align 8
.type _Z6_erodePcS_iiiPi,@function
_Z6_erodePcS_iiiPi: ; @_Z6_erodePcS_iiiPi
; %bb.0:
s_clause 0x1
s_load_b128 s[8:11], s[0:1], 0x10
s_load_b32 s2, s[0:1], 0x34
s_waitcnt lgkmcnt(0)
v_cvt_f32_u32_e32 v1, s8
s_sub_i32 s3, 0, s8
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v1, v1
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v1, 0x4f7ffffe, v1
v_cvt_u32_f32_e32 v3, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v1, s3, v3
v_mul_hi_u32 v4, v3, v1
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_lshr_b32 s2, s10, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s2, s10, s2
s_ashr_i32 s3, s2, 1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v0, v3, v4
v_mul_hi_u32 v0, v1, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_lo_u32 v2, v0, s8
v_add_nc_u32_e32 v3, 1, v0
v_sub_nc_u32_e32 v2, v1, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_subrev_nc_u32_e32 v4, s8, v2
v_cmp_le_u32_e32 vcc_lo, s8, v2
v_cndmask_b32_e32 v0, v0, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v2, v2, v4, vcc_lo
v_add_nc_u32_e32 v3, 1, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_le_u32_e32 vcc_lo, s8, v2
v_cndmask_b32_e32 v0, v0, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mul_lo_u32 v2, v0, s8
v_add_nc_u32_e32 v4, s3, v0
v_cmp_ge_i32_e64 s2, s9, v4
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v2, v1, v2
v_add_nc_u32_e32 v3, s3, v2
v_min_i32_e32 v0, v2, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_ge_i32_e32 vcc_lo, s8, v3
v_cmp_le_i32_e64 s3, s3, v0
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
s_and_b32 s2, s2, s3
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_5
; %bb.1:
s_load_b128 s[4:7], s[0:1], 0x0
v_mov_b32_e32 v0, 0
s_cmp_eq_u32 s10, 0
s_mul_i32 s2, s10, s10
s_cbranch_scc1 .LBB0_4
; %bb.2: ; %.lr.ph.preheader
s_load_b64 s[0:1], s[0:1], 0x20
v_mov_b32_e32 v0, 0
s_max_u32 s3, s2, 1
.LBB0_3: ; %.lr.ph
; =>This Inner Loop Header: Depth=1
s_waitcnt lgkmcnt(0)
s_load_b32 s8, s[0:1], 0x0
s_add_i32 s3, s3, -1
s_add_u32 s0, s0, 4
s_addc_u32 s1, s1, 0
s_cmp_eq_u32 s3, 0
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v2, s8, v1
global_load_u8 v2, v2, s[4:5]
s_waitcnt vmcnt(0)
v_cmp_lt_u16_e32 vcc_lo, 0x64, v2
v_add_co_ci_u32_e32 v0, vcc_lo, 0, v0, vcc_lo
s_cbranch_scc0 .LBB0_3
.LBB0_4: ; %Flow58
s_delay_alu instid0(VALU_DEP_1)
v_cmp_eq_u32_e32 vcc_lo, s2, v0
v_cndmask_b32_e64 v0, 0, -1, vcc_lo
s_waitcnt lgkmcnt(0)
global_store_b8 v1, v0, s[6:7]
.LBB0_5:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6_erodePcS_iiiPi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6_erodePcS_iiiPi, .Lfunc_end0-_Z6_erodePcS_iiiPi
; -- End function
.section .AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 408
; NumSgprs: 18
; NumVgprs: 5
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 5
; Occupancy: 16
; WaveLimiterHint : 1
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
.text
.protected _Z7_dilatePcS_iiiPi ; -- Begin function _Z7_dilatePcS_iiiPi
.globl _Z7_dilatePcS_iiiPi
.p2align 8
.type _Z7_dilatePcS_iiiPi,@function
_Z7_dilatePcS_iiiPi: ; @_Z7_dilatePcS_iiiPi
; %bb.0:
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x10
s_load_b32 s2, s[0:1], 0x34
s_waitcnt lgkmcnt(0)
v_cvt_f32_u32_e32 v1, s4
s_sub_i32 s3, 0, s4
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v1, v1
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v1, 0x4f7ffffe, v1
v_cvt_u32_f32_e32 v3, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v1, s3, v3
v_mul_hi_u32 v4, v3, v1
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_lshr_b32 s2, s6, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s2, s6, s2
s_ashr_i32 s3, s2, 1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v0, v3, v4
v_mul_hi_u32 v0, v1, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_lo_u32 v2, v0, s4
v_add_nc_u32_e32 v3, 1, v0
v_sub_nc_u32_e32 v2, v1, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_subrev_nc_u32_e32 v4, s4, v2
v_cmp_le_u32_e32 vcc_lo, s4, v2
v_cndmask_b32_e32 v0, v0, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v2, v2, v4, vcc_lo
v_add_nc_u32_e32 v3, 1, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_le_u32_e32 vcc_lo, s4, v2
v_cndmask_b32_e32 v0, v0, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mul_lo_u32 v2, v0, s4
v_add_nc_u32_e32 v4, s3, v0
v_cmp_ge_i32_e64 s2, s5, v4
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v2, v1, v2
v_add_nc_u32_e32 v3, s3, v2
v_min_i32_e32 v0, v2, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_ge_i32_e32 vcc_lo, s4, v3
v_cmp_le_i32_e64 s3, s3, v0
s_and_b32 s4, vcc_lo, s2
s_mov_b32 s2, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s3, s4, s3
s_and_saveexec_b32 s4, s3
s_cbranch_execz .LBB1_6
; %bb.1:
s_load_b128 s[8:11], s[0:1], 0x0
s_cmp_eq_u32 s6, 0
s_cbranch_scc1 .LBB1_5
; %bb.2: ; %.lr.ph.preheader
s_load_b64 s[0:1], s[0:1], 0x20
v_mov_b32_e32 v0, 0
s_mul_i32 s2, s6, s6
s_delay_alu instid0(SALU_CYCLE_1)
s_max_u32 s2, s2, 1
.LBB1_3: ; %.lr.ph
; =>This Inner Loop Header: Depth=1
s_waitcnt lgkmcnt(0)
s_load_b32 s3, s[0:1], 0x0
s_add_i32 s2, s2, -1
s_add_u32 s0, s0, 4
s_addc_u32 s1, s1, 0
s_cmp_eq_u32 s2, 0
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v2, s3, v1
global_load_u8 v2, v2, s[8:9]
s_waitcnt vmcnt(0)
v_cmp_lt_u16_e32 vcc_lo, 0x64, v2
v_add_co_ci_u32_e32 v0, vcc_lo, 0, v0, vcc_lo
s_cbranch_scc0 .LBB1_3
; %bb.4: ; %._crit_edge.loopexit
s_delay_alu instid0(VALU_DEP_1)
v_cmp_ne_u32_e64 s2, 0, v0
.LBB1_5: ; %Flow
s_delay_alu instid0(VALU_DEP_1)
v_cndmask_b32_e64 v0, 0, -1, s2
s_waitcnt lgkmcnt(0)
global_store_b8 v1, v0, s[10:11]
.LBB1_6:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z7_dilatePcS_iiiPi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z7_dilatePcS_iiiPi, .Lfunc_end1-_Z7_dilatePcS_iiiPi
; -- End function
.section .AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 416
; NumSgprs: 18
; NumVgprs: 5
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 5
; Occupancy: 16
; WaveLimiterHint : 1
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object ; @__hip_cuid_
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0 ; 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6_erodePcS_iiiPi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z6_erodePcS_iiiPi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z7_dilatePcS_iiiPi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z7_dilatePcS_iiiPi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
```
| 14,167 | 7,098 |
597 |
Convert the following CUDA host assembly code to AMD host assembly:
```cudaasm
.file "tmpxft_00154da5_00000000-6_CudaImageMorphology.cudafe1.cpp"
.text
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z13_getRangeMaskii
.type _Z13_getRangeMaskii, @function
_Z13_getRangeMaskii:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
movl %edi, %ebx
movl %esi, %ebp
movslq %edi, %rdi
imulq %rdi, %rdi
salq $2, %rdi
call malloc@PLT
movq %rax, %r8
movl %ebx, %edi
imull %ebx, %edi
movl %edi, %eax
shrl $31, %eax
addl %edi, %eax
sarl %eax
cltd
idivl %ebx
testl %edi, %edi
jle .L3
movl %edx, %r9d
movl %eax, %esi
movslq %edi, %rdi
movl $0, %ecx
.L5:
movl %ecx, %eax
cltd
idivl %ebx
subl %r9d, %eax
imull %ebp, %eax
subl %esi, %edx
addl %edx, %eax
movl %eax, (%r8,%rcx,4)
addq $1, %rcx
cmpq %rdi, %rcx
jne .L5
.L3:
movq %r8, %rax
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size _Z13_getRangeMaskii, .-_Z13_getRangeMaskii
.globl _Z32__device_stub__Z6_erodePcS_iiiPiPcS_iiiPi
.type _Z32__device_stub__Z6_erodePcS_iiiPiPcS_iiiPi, @function
_Z32__device_stub__Z6_erodePcS_iiiPiPcS_iiiPi:
.LFB2084:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movl %edx, 28(%rsp)
movl %ecx, 24(%rsp)
movl %r8d, 20(%rsp)
movq %r9, 8(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 28(%rsp), %rax
movq %rax, 128(%rsp)
leaq 24(%rsp), %rax
movq %rax, 136(%rsp)
leaq 20(%rsp), %rax
movq %rax, 144(%rsp)
leaq 8(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L12
.L8:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L13
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L12:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z6_erodePcS_iiiPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L8
.L13:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z32__device_stub__Z6_erodePcS_iiiPiPcS_iiiPi, .-_Z32__device_stub__Z6_erodePcS_iiiPiPcS_iiiPi
.globl _Z6_erodePcS_iiiPi
.type _Z6_erodePcS_iiiPi, @function
_Z6_erodePcS_iiiPi:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z6_erodePcS_iiiPiPcS_iiiPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z6_erodePcS_iiiPi, .-_Z6_erodePcS_iiiPi
.globl _Z9gpu_erodePcS_iii
.type _Z9gpu_erodePcS_iii, @function
_Z9gpu_erodePcS_iii:
.LFB2058:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $1144, %rsp
.cfi_def_cfa_offset 1200
movq %rdi, 8(%rsp)
movq %rsi, 16(%rsp)
movl %edx, %r13d
movl %ecx, %r14d
movl %r8d, %r15d
movq %fs:40, %rax
movq %rax, 1128(%rsp)
xorl %eax, %eax
movl $1, 44(%rsp)
leaq 44(%rsp), %rdi
call cudaGetDeviceCount@PLT
cmpl $0, 44(%rsp)
jle .L17
movl $0, %ebp
leaq 96(%rsp), %r12
.L18:
movl %ebp, %esi
movq %r12, %rdi
call cudaGetDeviceProperties_v2@PLT
movl 416(%rsp), %ebx
addl $1, %ebp
cmpl %ebp, 44(%rsp)
jg .L18
.L17:
movl %r13d, %eax
imull %r14d, %eax
leal -1(%rbx,%rax), %eax
cltd
idivl %ebx
movl %eax, 28(%rsp)
movslq %r13d, %rbp
movslq %r14d, %rax
imulq %rax, %rbp
leaq 48(%rsp), %rdi
movq %rbp, %rsi
call cudaMalloc@PLT
leaq 56(%rsp), %rdi
movq %rbp, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %rbp, %rdx
movq 8(%rsp), %rsi
movq 48(%rsp), %rdi
call cudaMemcpy@PLT
movl %r13d, %esi
movl %r15d, %edi
call _Z13_getRangeMaskii
movq %rax, 8(%rsp)
movslq %r15d, %r12
imulq %r12, %r12
salq $2, %r12
leaq 64(%rsp), %rdi
movq %r12, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %r12, %rdx
movq 8(%rsp), %rsi
movq 64(%rsp), %rdi
call cudaMemcpy@PLT
movl %ebx, 84(%rsp)
movl $1, 88(%rsp)
movl 28(%rsp), %eax
movl %eax, 72(%rsp)
movl $1, 76(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 84(%rsp), %rdx
movl $1, %ecx
movq 72(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L23
.L19:
movl $2, %ecx
movq %rbp, %rdx
movq 56(%rsp), %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movq 48(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rdi
call cudaFree@PLT
movq 64(%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call free@PLT
movq 1128(%rsp), %rax
subq %fs:40, %rax
jne .L24
addq $1144, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
movq 64(%rsp), %r9
movl %r15d, %r8d
movl %r14d, %ecx
movl %r13d, %edx
movq 56(%rsp), %rsi
movq 48(%rsp), %rdi
call _Z32__device_stub__Z6_erodePcS_iiiPiPcS_iiiPi
jmp .L19
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size _Z9gpu_erodePcS_iii, .-_Z9gpu_erodePcS_iii
.globl _Z33__device_stub__Z7_dilatePcS_iiiPiPcS_iiiPi
.type _Z33__device_stub__Z7_dilatePcS_iiiPiPcS_iiiPi, @function
_Z33__device_stub__Z7_dilatePcS_iiiPiPcS_iiiPi:
.LFB2086:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movl %edx, 28(%rsp)
movl %ecx, 24(%rsp)
movl %r8d, 20(%rsp)
movq %r9, 8(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 28(%rsp), %rax
movq %rax, 128(%rsp)
leaq 24(%rsp), %rax
movq %rax, 136(%rsp)
leaq 20(%rsp), %rax
movq %rax, 144(%rsp)
leaq 8(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L29
.L25:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L30
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L29:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z7_dilatePcS_iiiPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L25
.L30:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2086:
.size _Z33__device_stub__Z7_dilatePcS_iiiPiPcS_iiiPi, .-_Z33__device_stub__Z7_dilatePcS_iiiPiPcS_iiiPi
.globl _Z7_dilatePcS_iiiPi
.type _Z7_dilatePcS_iiiPi, @function
_Z7_dilatePcS_iiiPi:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z7_dilatePcS_iiiPiPcS_iiiPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _Z7_dilatePcS_iiiPi, .-_Z7_dilatePcS_iiiPi
.globl _Z10gpu_dilatePcS_iii
.type _Z10gpu_dilatePcS_iii, @function
_Z10gpu_dilatePcS_iii:
.LFB2059:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $1144, %rsp
.cfi_def_cfa_offset 1200
movq %rdi, 8(%rsp)
movq %rsi, 16(%rsp)
movl %edx, %r13d
movl %ecx, %r14d
movl %r8d, %r15d
movq %fs:40, %rax
movq %rax, 1128(%rsp)
xorl %eax, %eax
movl $1, 44(%rsp)
leaq 44(%rsp), %rdi
call cudaGetDeviceCount@PLT
cmpl $0, 44(%rsp)
jle .L34
movl $0, %ebp
leaq 96(%rsp), %r12
.L35:
movl %ebp, %esi
movq %r12, %rdi
call cudaGetDeviceProperties_v2@PLT
movl 416(%rsp), %ebx
addl $1, %ebp
cmpl %ebp, 44(%rsp)
jg .L35
.L34:
movl %r13d, %eax
imull %r14d, %eax
leal -1(%rbx,%rax), %eax
cltd
idivl %ebx
movl %eax, 28(%rsp)
movslq %r13d, %rbp
movslq %r14d, %rax
imulq %rax, %rbp
leaq 48(%rsp), %rdi
movq %rbp, %rsi
call cudaMalloc@PLT
leaq 56(%rsp), %rdi
movq %rbp, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %rbp, %rdx
movq 8(%rsp), %rsi
movq 48(%rsp), %rdi
call cudaMemcpy@PLT
movl %r13d, %esi
movl %r15d, %edi
call _Z13_getRangeMaskii
movq %rax, 8(%rsp)
movslq %r15d, %r12
imulq %r12, %r12
salq $2, %r12
leaq 64(%rsp), %rdi
movq %r12, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %r12, %rdx
movq 8(%rsp), %rsi
movq 64(%rsp), %rdi
call cudaMemcpy@PLT
movl %ebx, 84(%rsp)
movl $1, 88(%rsp)
movl 28(%rsp), %eax
movl %eax, 72(%rsp)
movl $1, 76(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 84(%rsp), %rdx
movl $1, %ecx
movq 72(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L40
.L36:
movl $2, %ecx
movq %rbp, %rdx
movq 56(%rsp), %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movq 48(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rdi
call cudaFree@PLT
movq 64(%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call free@PLT
movq 1128(%rsp), %rax
subq %fs:40, %rax
jne .L41
addq $1144, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L40:
.cfi_restore_state
movq 64(%rsp), %r9
movl %r15d, %r8d
movl %r14d, %ecx
movl %r13d, %edx
movq 56(%rsp), %rsi
movq 48(%rsp), %rdi
call _Z33__device_stub__Z7_dilatePcS_iiiPiPcS_iiiPi
jmp .L36
.L41:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size _Z10gpu_dilatePcS_iii, .-_Z10gpu_dilatePcS_iii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z7_dilatePcS_iiiPi"
.LC1:
.string "_Z6_erodePcS_iiiPi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2089:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z7_dilatePcS_iiiPi(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z6_erodePcS_iiiPi(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2089:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
```
|
```amdasm
.text
.file "CudaImageMorphology.hip"
.globl _Z21__device_stub___erodePcS_iiiPi # -- Begin function _Z21__device_stub___erodePcS_iiiPi
.type _Z21__device_stub___erodePcS_iiiPi,@function
_Z21__device_stub___erodePcS_iiiPi: # @_Z21__device_stub___erodePcS_iiiPi
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $144, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 56(%rsp), %rax
movq %rdi, (%rax)
leaq 48(%rsp), %rdi
movq %rsi, (%rdi)
leaq 20(%rsp), %rsi
movl %edx, (%rsi)
leaq 16(%rsp), %rdx
movl %ecx, (%rdx)
leaq 12(%rsp), %rcx
movl %r8d, (%rcx)
leaq 40(%rsp), %r8
movq %r9, (%r8)
leaq 96(%rsp), %rbx
movq %rax, (%rbx)
movq %rdi, 8(%rbx)
movq %rsi, 16(%rbx)
movq %rdx, 24(%rbx)
movq %rcx, 32(%rbx)
movq %r8, 40(%rbx)
leaq 80(%rsp), %r14
leaq 64(%rsp), %r15
leaq 32(%rsp), %r12
leaq 24(%rsp), %r13
movq %r14, %rdi
movq %r15, %rsi
movq %r12, %rdx
movq %r13, %rcx
callq __hipPopCallConfiguration
movq (%r14), %rsi
movl 8(%r14), %edx
movq (%r15), %rcx
movl 8(%r15), %r8d
movl $_Z6_erodePcS_iiiPi, %edi
movq %rbx, %r9
pushq (%r13)
.cfi_adjust_cfa_offset 8
pushq (%r12)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $160, %rsp
.cfi_adjust_cfa_offset -160
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z21__device_stub___erodePcS_iiiPi, .Lfunc_end0-_Z21__device_stub___erodePcS_iiiPi
.cfi_endproc
# -- End function
.globl _Z22__device_stub___dilatePcS_iiiPi # -- Begin function _Z22__device_stub___dilatePcS_iiiPi
.type _Z22__device_stub___dilatePcS_iiiPi,@function
_Z22__device_stub___dilatePcS_iiiPi: # @_Z22__device_stub___dilatePcS_iiiPi
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $144, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 56(%rsp), %rax
movq %rdi, (%rax)
leaq 48(%rsp), %rdi
movq %rsi, (%rdi)
leaq 20(%rsp), %rsi
movl %edx, (%rsi)
leaq 16(%rsp), %rdx
movl %ecx, (%rdx)
leaq 12(%rsp), %rcx
movl %r8d, (%rcx)
leaq 40(%rsp), %r8
movq %r9, (%r8)
leaq 96(%rsp), %rbx
movq %rax, (%rbx)
movq %rdi, 8(%rbx)
movq %rsi, 16(%rbx)
movq %rdx, 24(%rbx)
movq %rcx, 32(%rbx)
movq %r8, 40(%rbx)
leaq 80(%rsp), %r14
leaq 64(%rsp), %r15
leaq 32(%rsp), %r12
leaq 24(%rsp), %r13
movq %r14, %rdi
movq %r15, %rsi
movq %r12, %rdx
movq %r13, %rcx
callq __hipPopCallConfiguration
movq (%r14), %rsi
movl 8(%r14), %edx
movq (%r15), %rcx
movl 8(%r15), %r8d
movl $_Z7_dilatePcS_iiiPi, %edi
movq %rbx, %r9
pushq (%r13)
.cfi_adjust_cfa_offset 8
pushq (%r12)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $160, %rsp
.cfi_adjust_cfa_offset -160
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z22__device_stub___dilatePcS_iiiPi, .Lfunc_end1-_Z22__device_stub___dilatePcS_iiiPi
.cfi_endproc
# -- End function
.globl _Z13_getRangeMaskii # -- Begin function _Z13_getRangeMaskii
.type _Z13_getRangeMaskii,@function
_Z13_getRangeMaskii: # @_Z13_getRangeMaskii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %rbp, -16
movl %esi, %ebx
movl %edi, %ebp
movslq %edi, %r14
movq %r14, %rdi
imulq %r14, %rdi
shlq $2, %rdi
callq malloc
movq %rax, %rcx
movl %r14d, %r9d
imull %r9d, %r9d
movl %r9d, %eax
shrl %eax
xorl %edx, %edx
idivl %r14d
movl %eax, %esi
movl %edx, %edi
xorl %r8d, %r8d
cmpl $1, %r9d
adcl $0, %r9d
.LBB2_1: # =>This Inner Loop Header: Depth=1
movl %r8d, %eax
cltd
idivl %ebp
subl %edi, %eax
imull %ebx, %eax
subl %esi, %edx
addl %eax, %edx
movl %edx, (%rcx,%r8,4)
incq %r8
cmpq %r8, %r9
jne .LBB2_1
# %bb.2:
movq %rcx, %rax
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size _Z13_getRangeMaskii, .Lfunc_end2-_Z13_getRangeMaskii
.cfi_endproc
# -- End function
.globl _Z9gpu_erodePcS_iii # -- Begin function _Z9gpu_erodePcS_iii
.type _Z9gpu_erodePcS_iii,@function
_Z9gpu_erodePcS_iii: # @_Z9gpu_erodePcS_iii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $1528, %rsp # imm = 0x5F8
.cfi_def_cfa_offset 1584
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %r8d, %r13d
movl %ecx, %r14d
movl %edx, %r12d
movq %rsi, 48(%rsp) # 8-byte Spill
movq %rdi, %r15
leaq 20(%rsp), %rbx
movl $1, (%rbx)
movq %rbx, %rdi
callq hipGetDeviceCount
cmpl $0, (%rbx)
movl %r12d, 4(%rsp) # 4-byte Spill
jle .LBB3_1
# %bb.6: # %.lr.ph.preheader
xorl %ebx, %ebx
leaq 56(%rsp), %r12
.LBB3_7: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movq %r12, %rdi
movl %ebx, %esi
callq hipGetDevicePropertiesR0600
incl %ebx
cmpl 20(%rsp), %ebx
jl .LBB3_7
# %bb.2: # %._crit_edge
movl 376(%rsp), %ecx
movl 4(%rsp), %r12d # 4-byte Reload
jmp .LBB3_3
.LBB3_1:
# implicit-def: $ecx
.LBB3_3:
movq %rcx, 40(%rsp) # 8-byte Spill
movl %r14d, %eax
imull %r12d, %eax
addl %ecx, %eax
decl %eax
cltd
idivl %ecx
movl %eax, %ebx
movslq %r12d, %rbp
movslq %r14d, %r12
imulq %rbp, %r12
movl %r14d, 16(%rsp) # 4-byte Spill
leaq 32(%rsp), %r14
movq %r14, %rdi
movq %r12, %rsi
callq hipMalloc
leaq 8(%rsp), %rdi
movq %r12, %rsi
callq hipMalloc
movq (%r14), %rdi
movq %r15, %rsi
movq %r12, %rdx
movl $1, %ecx
callq hipMemcpy
movl %r13d, %edi
movl %ebp, %esi
callq _Z13_getRangeMaskii
movq %rax, %rbp
movslq %r13d, %r14
imulq %r14, %r14
shlq $2, %r14
leaq 24(%rsp), %r15
movq %r15, %rdi
movq %r14, %rsi
callq hipMalloc
movq (%r15), %rdi
movq %rbp, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
btsq $32, %rbx
movl 40(%rsp), %edx # 4-byte Reload
btsq $32, %rdx
movq %rbx, %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_5
# %bb.4:
movq 32(%rsp), %rdi
movq 8(%rsp), %rsi
movq 24(%rsp), %r9
movl 4(%rsp), %edx # 4-byte Reload
movl 16(%rsp), %ecx # 4-byte Reload
movl %r13d, %r8d
callq _Z21__device_stub___erodePcS_iiiPi
.LBB3_5:
movq 8(%rsp), %rsi
movq 48(%rsp), %rdi # 8-byte Reload
movq %r12, %rdx
movl $2, %ecx
callq hipMemcpy
movq 32(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
movq %rbp, %rdi
callq free
addq $1528, %rsp # imm = 0x5F8
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size _Z9gpu_erodePcS_iii, .Lfunc_end3-_Z9gpu_erodePcS_iii
.cfi_endproc
# -- End function
.globl _Z10gpu_dilatePcS_iii # -- Begin function _Z10gpu_dilatePcS_iii
.type _Z10gpu_dilatePcS_iii,@function
_Z10gpu_dilatePcS_iii: # @_Z10gpu_dilatePcS_iii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $1528, %rsp # imm = 0x5F8
.cfi_def_cfa_offset 1584
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %r8d, %r13d
movl %ecx, %r14d
movl %edx, %r12d
movq %rsi, 48(%rsp) # 8-byte Spill
movq %rdi, %r15
leaq 20(%rsp), %rbx
movl $1, (%rbx)
movq %rbx, %rdi
callq hipGetDeviceCount
cmpl $0, (%rbx)
movl %r12d, 4(%rsp) # 4-byte Spill
jle .LBB4_1
# %bb.6: # %.lr.ph.preheader
xorl %ebx, %ebx
leaq 56(%rsp), %r12
.LBB4_7: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movq %r12, %rdi
movl %ebx, %esi
callq hipGetDevicePropertiesR0600
incl %ebx
cmpl 20(%rsp), %ebx
jl .LBB4_7
# %bb.2: # %._crit_edge
movl 376(%rsp), %ecx
movl 4(%rsp), %r12d # 4-byte Reload
jmp .LBB4_3
.LBB4_1:
# implicit-def: $ecx
.LBB4_3:
movq %rcx, 40(%rsp) # 8-byte Spill
movl %r14d, %eax
imull %r12d, %eax
addl %ecx, %eax
decl %eax
cltd
idivl %ecx
movl %eax, %ebx
movslq %r12d, %rbp
movslq %r14d, %r12
imulq %rbp, %r12
movl %r14d, 16(%rsp) # 4-byte Spill
leaq 32(%rsp), %r14
movq %r14, %rdi
movq %r12, %rsi
callq hipMalloc
leaq 8(%rsp), %rdi
movq %r12, %rsi
callq hipMalloc
movq (%r14), %rdi
movq %r15, %rsi
movq %r12, %rdx
movl $1, %ecx
callq hipMemcpy
movl %r13d, %edi
movl %ebp, %esi
callq _Z13_getRangeMaskii
movq %rax, %rbp
movslq %r13d, %r14
imulq %r14, %r14
shlq $2, %r14
leaq 24(%rsp), %r15
movq %r15, %rdi
movq %r14, %rsi
callq hipMalloc
movq (%r15), %rdi
movq %rbp, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
btsq $32, %rbx
movl 40(%rsp), %edx # 4-byte Reload
btsq $32, %rdx
movq %rbx, %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_5
# %bb.4:
movq 32(%rsp), %rdi
movq 8(%rsp), %rsi
movq 24(%rsp), %r9
movl 4(%rsp), %edx # 4-byte Reload
movl 16(%rsp), %ecx # 4-byte Reload
movl %r13d, %r8d
callq _Z22__device_stub___dilatePcS_iiiPi
.LBB4_5:
movq 8(%rsp), %rsi
movq 48(%rsp), %rdi # 8-byte Reload
movq %r12, %rdx
movl $2, %ecx
callq hipMemcpy
movq 32(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
movq %rbp, %rdi
callq free
addq $1528, %rsp # imm = 0x5F8
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end4:
.size _Z10gpu_dilatePcS_iii, .Lfunc_end4-_Z10gpu_dilatePcS_iii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
movq __hip_gpubin_handle(%rip), %rbx
testq %rbx, %rbx
jne .LBB5_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, %rbx
movq %rax, __hip_gpubin_handle(%rip)
.LBB5_2:
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6_erodePcS_iiiPi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7_dilatePcS_iiiPi, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end5:
.size __hip_module_ctor, .Lfunc_end5-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB6_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB6_2:
retq
.Lfunc_end6:
.size __hip_module_dtor, .Lfunc_end6-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6_erodePcS_iiiPi,@object # @_Z6_erodePcS_iiiPi
.section .rodata,"a",@progbits
.globl _Z6_erodePcS_iiiPi
.p2align 3, 0x0
_Z6_erodePcS_iiiPi:
.quad _Z21__device_stub___erodePcS_iiiPi
.size _Z6_erodePcS_iiiPi, 8
.type _Z7_dilatePcS_iiiPi,@object # @_Z7_dilatePcS_iiiPi
.globl _Z7_dilatePcS_iiiPi
.p2align 3, 0x0
_Z7_dilatePcS_iiiPi:
.quad _Z22__device_stub___dilatePcS_iiiPi
.size _Z7_dilatePcS_iiiPi, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z6_erodePcS_iiiPi"
.size .L__unnamed_1, 19
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z7_dilatePcS_iiiPi"
.size .L__unnamed_2, 20
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub___erodePcS_iiiPi
.addrsig_sym _Z22__device_stub___dilatePcS_iiiPi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6_erodePcS_iiiPi
.addrsig_sym _Z7_dilatePcS_iiiPi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
```
| 6,814 | 7,407 |
598 |
Convert the following CUDA device assembly code to AMD device assembly:
```cudaasm
code for sm_80
Function : _Z31remove_redness_from_coordinatesPKjPhS1_S1_S1_iiiii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ;
S2R R0, SR_CTAID.X ;
S2R R3, SR_TID.X ;
IMAD R0, R0, c[0x0][0x0], R3 ;
ISETP.GE.AND P0, PT, R0, c[0x0][0x188], PT ;
@P0 EXIT ;
LOP3.LUT R3, RZ, R0, RZ, 0x33, !PT ;
IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x190] ;
ULDC.64 UR6, c[0x0][0x118] ;
IMAD.MOV.U32 R2, RZ, RZ, 0x4 ;
IMAD R3, R4, c[0x0][0x18c], R3 ;
IMAD.WIDE R2, R3, R2, c[0x0][0x160] ;
LDG.E R2, [R2.64] ;
I2F.U32.RP R0, c[0x0][0x190] ;
MUFU.RCP R0, R0 ;
IADD3 R6, R0, 0xffffffe, RZ ;
F2I.FTZ.U32.TRUNC.NTZ R7, R6 ;
IMAD.MOV.U32 R6, RZ, RZ, RZ ;
IMAD.MOV R5, RZ, RZ, -R7 ;
IMAD R5, R5, c[0x0][0x190], RZ ;
IMAD.HI.U32 R7, R7, R5, R6 ;
LOP3.LUT R6, RZ, c[0x0][0x190], RZ, 0x33, !PT ;
IMAD.HI.U32 R7, R7, R2, RZ ;
IMAD.MOV R3, RZ, RZ, -R7 ;
IMAD R2, R3, c[0x0][0x190], R2 ;
ISETP.GE.U32.AND P0, PT, R2, c[0x0][0x190], PT ;
@P0 IADD3 R2, R2, -c[0x0][0x190], RZ ;
@P0 IADD3 R7, R7, 0x1, RZ ;
ISETP.GE.U32.AND P1, PT, R2, c[0x0][0x190], PT ;
ISETP.NE.U32.AND P0, PT, RZ, c[0x0][0x190], PT ;
@P1 IADD3 R7, R7, 0x1, RZ ;
SEL R7, R6, R7, !P0 ;
LOP3.LUT R7, R7, 0xffff, RZ, 0xc0, !PT ;
IADD3 R5, R7.reuse, -c[0x0][0x194], RZ ;
IADD3 R0, R7, c[0x0][0x194], RZ ;
ISETP.GT.AND P2, PT, R5, R0, PT ;
@P2 EXIT ;
IADD3 R3, R2, -c[0x0][0x190], RZ ;
ULDC UR4, c[0x0][0x18c] ;
IADD3 R4, R4, -0x1, RZ ;
UIADD3 UR4, UR4, -0x1, URZ ;
@P0 SEL R6, R3, R2, P1 ;
LOP3.LUT R7, R6, 0xffff, RZ, 0xc0, !PT ;
IADD3 R2, R7.reuse, -c[0x0][0x198], RZ ;
IADD3 R3, R7, c[0x0][0x198], RZ ;
IMNMX R9, RZ, R2, !PT ;
IMNMX R8, R2, R3, !PT ;
IMNMX R9, R9, R4, PT ;
IADD3 R8, R8, c[0x0][0x198], RZ ;
IADD3 R24, -R6, 0x1, R8 ;
IMAD.IADD R7, R8, 0x1, -R7 ;
IADD3 R6, R2.reuse, 0x1, RZ ;
IADD3 R8, R2.reuse, 0x3, RZ ;
ISETP.GE.U32.AND P0, PT, R7, 0x3, PT ;
IADD3 R7, R2, 0x2, RZ ;
IMNMX R11, RZ, R6, !PT ;
IMNMX R13, RZ, R7, !PT ;
IMNMX R10, R4.reuse, R11, PT ;
IMNMX R11, R4, R13, PT ;
LOP3.LUT R24, R24, 0x3, RZ, 0xc0, !PT ;
ISETP.GT.AND P1, PT, R2, R3, PT ;
BSSY B0, 0xb90 ;
@P1 BRA 0xb80 ;
ISETP.NE.AND P1, PT, R24, RZ, PT ;
BSSY B1, 0x740 ;
IMNMX R26, RZ, R5, !PT ;
IMAD.MOV.U32 R18, RZ, RZ, R2 ;
IMNMX R26, R26, UR4, PT ;
@!P1 BRA 0x730 ;
IMAD R16, R26, c[0x0][0x190], R9 ;
SHF.R.S32.HI R17, RZ, 0x1f, R16 ;
IADD3 R12, P2, R16.reuse, c[0x0][0x170], RZ ;
IADD3 R14, P1, R16, c[0x0][0x178], RZ ;
IADD3.X R13, R17.reuse, c[0x0][0x174], RZ, P2, !PT ;
IADD3.X R15, R17, c[0x0][0x17c], RZ, P1, !PT ;
LDG.E.U8 R13, [R12.64] ;
LDG.E.U8 R14, [R14.64] ;
IADD3 R16, P1, R16, c[0x0][0x180], RZ ;
IADD3.X R17, R17, c[0x0][0x184], RZ, P1, !PT ;
ISETP.NE.AND P1, PT, R24, 0x1, PT ;
IMAD.IADD R18, R14, 0x1, R13 ;
SHF.R.U32.HI R19, RZ, 0x1, R18 ;
STG.E.U8 [R16.64], R19 ;
IMAD.MOV.U32 R18, RZ, RZ, R6 ;
@!P1 BRA 0x730 ;
IMAD R16, R26, c[0x0][0x190], R10 ;
SHF.R.S32.HI R17, RZ, 0x1f, R16 ;
IADD3 R12, P2, R16.reuse, c[0x0][0x170], RZ ;
IADD3 R14, P1, R16, c[0x0][0x178], RZ ;
IADD3.X R13, R17.reuse, c[0x0][0x174], RZ, P2, !PT ;
IADD3.X R15, R17, c[0x0][0x17c], RZ, P1, !PT ;
LDG.E.U8 R13, [R12.64] ;
LDG.E.U8 R14, [R14.64] ;
IADD3 R16, P1, R16, c[0x0][0x180], RZ ;
IADD3.X R17, R17, c[0x0][0x184], RZ, P1, !PT ;
ISETP.NE.AND P1, PT, R24, 0x2, PT ;
IMAD.IADD R18, R14, 0x1, R13 ;
SHF.R.U32.HI R19, RZ, 0x1, R18 ;
STG.E.U8 [R16.64], R19 ;
IMAD.MOV.U32 R18, RZ, RZ, R7 ;
@!P1 BRA 0x730 ;
IMAD R16, R26, c[0x0][0x190], R11 ;
SHF.R.S32.HI R17, RZ, 0x1f, R16 ;
IADD3 R12, P2, R16.reuse, c[0x0][0x170], RZ ;
IADD3 R14, P1, R16, c[0x0][0x178], RZ ;
IADD3.X R13, R17.reuse, c[0x0][0x174], RZ, P2, !PT ;
IADD3.X R15, R17, c[0x0][0x17c], RZ, P1, !PT ;
LDG.E.U8 R13, [R12.64] ;
LDG.E.U8 R14, [R14.64] ;
IADD3 R16, P1, R16, c[0x0][0x180], RZ ;
IADD3.X R17, R17, c[0x0][0x184], RZ, P1, !PT ;
IMAD.IADD R18, R14, 0x1, R13 ;
SHF.R.U32.HI R19, RZ, 0x1, R18 ;
STG.E.U8 [R16.64], R19 ;
IMAD.MOV.U32 R18, RZ, RZ, R8 ;
BSYNC B1 ;
@!P0 BRA 0xb80 ;
IADD3 R28, R18, 0x3, RZ ;
IADD3 R12, R28, -0x3, RZ ;
IMNMX R13, RZ, R12, !PT ;
IMNMX R13, R4, R13, PT ;
IMAD R22, R26, c[0x0][0x190], R13 ;
SHF.R.S32.HI R19, RZ, 0x1f, R22 ;
IADD3 R12, P2, R22.reuse, c[0x0][0x170], RZ ;
IADD3 R14, P1, R22, c[0x0][0x178], RZ ;
IADD3.X R13, R19.reuse, c[0x0][0x174], RZ, P2, !PT ;
IADD3.X R15, R19, c[0x0][0x17c], RZ, P1, !PT ;
LDG.E.U8 R13, [R12.64] ;
LDG.E.U8 R14, [R14.64] ;
IADD3 R16, R28, -0x2, RZ ;
IMNMX R17, RZ, R16, !PT ;
IMNMX R17, R4, R17, PT ;
IMAD R16, R26, c[0x0][0x190], R17 ;
IADD3 R22, P1, R22, c[0x0][0x180], RZ ;
SHF.R.S32.HI R17, RZ, 0x1f, R16 ;
IADD3 R18, P3, R16.reuse, c[0x0][0x170], RZ ;
IADD3 R20, P2, R16, c[0x0][0x178], RZ ;
IADD3.X R23, R19, c[0x0][0x184], RZ, P1, !PT ;
IADD3.X R19, R17.reuse, c[0x0][0x174], RZ, P3, !PT ;
IADD3.X R21, R17, c[0x0][0x17c], RZ, P2, !PT ;
IMAD.IADD R25, R14, 0x1, R13 ;
SHF.R.U32.HI R29, RZ, 0x1, R25 ;
STG.E.U8 [R22.64], R29 ;
LDG.E.U8 R20, [R20.64] ;
LDG.E.U8 R19, [R18.64] ;
IADD3 R12, R28, -0x1, RZ ;
IMNMX R13, RZ, R12, !PT ;
IMNMX R13, R4, R13, PT ;
IMAD R27, R26, c[0x0][0x190], R13 ;
IADD3 R12, P1, R16, c[0x0][0x180], RZ ;
SHF.R.S32.HI R25, RZ, 0x1f, R27 ;
IADD3 R16, P3, R27.reuse, c[0x0][0x170], RZ ;
IADD3 R14, P2, R27, c[0x0][0x178], RZ ;
IADD3.X R13, R17, c[0x0][0x184], RZ, P1, !PT ;
IADD3.X R17, R25.reuse, c[0x0][0x174], RZ, P3, !PT ;
IADD3.X R15, R25, c[0x0][0x17c], RZ, P2, !PT ;
IMAD.IADD R22, R20, 0x1, R19 ;
SHF.R.U32.HI R19, RZ, 0x1, R22 ;
STG.E.U8 [R12.64], R19 ;
LDG.E.U8 R14, [R14.64] ;
LDG.E.U8 R17, [R16.64] ;
IMNMX R21, RZ, R28, !PT ;
IMNMX R21, R4, R21, PT ;
IADD3 R22, P1, R27, c[0x0][0x180], RZ ;
IMAD R15, R26, c[0x0][0x190], R21 ;
IADD3.X R23, R25, c[0x0][0x184], RZ, P1, !PT ;
SHF.R.S32.HI R29, RZ, 0x1f, R15 ;
IADD3 R20, P3, R15.reuse, c[0x0][0x170], RZ ;
IADD3 R18, P2, R15, c[0x0][0x178], RZ ;
IADD3.X R21, R29.reuse, c[0x0][0x174], RZ, P3, !PT ;
IADD3.X R19, R29, c[0x0][0x17c], RZ, P2, !PT ;
IMAD.IADD R27, R14, 0x1, R17 ;
SHF.R.U32.HI R27, RZ, 0x1, R27 ;
STG.E.U8 [R22.64], R27 ;
LDG.E.U8 R18, [R18.64] ;
LDG.E.U8 R21, [R20.64] ;
IADD3 R12, P1, R15, c[0x0][0x180], RZ ;
IADD3.X R13, R29, c[0x0][0x184], RZ, P1, !PT ;
ISETP.GE.AND P1, PT, R28.reuse, R3, PT ;
IADD3 R28, R28, 0x4, RZ ;
IMAD.IADD R14, R18, 0x1, R21 ;
SHF.R.U32.HI R15, RZ, 0x1, R14 ;
STG.E.U8 [R12.64], R15 ;
@!P1 BRA 0x760 ;
BSYNC B0 ;
ISETP.GE.AND P1, PT, R5.reuse, R0, PT ;
IADD3 R5, R5, 0x1, RZ ;
@!P1 BRA 0x3c0 ;
EXIT ;
BRA 0xbd0;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
```
|
```amdasm
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z31remove_redness_from_coordinatesPKjPhS1_S1_S1_iiiii ; -- Begin function _Z31remove_redness_from_coordinatesPKjPhS1_S1_S1_iiiii
.globl _Z31remove_redness_from_coordinatesPKjPhS1_S1_S1_iiiii
.p2align 8
.type _Z31remove_redness_from_coordinatesPKjPhS1_S1_S1_iiiii,@function
_Z31remove_redness_from_coordinatesPKjPhS1_S1_S1_iiiii: ; @_Z31remove_redness_from_coordinatesPKjPhS1_S1_S1_iiiii
; %bb.0:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x4c
s_load_b128 s[4:7], s[0:1], 0x28
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s4, v1
s_cbranch_execz .LBB0_7
; %bb.1:
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x0
s_load_b32 s12, s[0:1], 0x38
s_mul_i32 s4, s6, s5
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_xad_u32 v0, v1, -1, s4
s_mov_b32 s4, 0
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
s_sub_i32 s2, 0, s6
global_load_b32 v0, v[0:1], off
v_cvt_f32_u32_e32 v1, s6
v_rcp_iflag_f32_e32 v1, v1
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v1, 0x4f7ffffe, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_u32_f32_e32 v1, v1
v_mul_lo_u32 v2, s2, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v2, v1, v2
v_add_nc_u32_e32 v1, v1, v2
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v1, v0, v1
v_mul_lo_u32 v2, v1, s6
v_add_nc_u32_e32 v3, 1, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v2, v0, v2
v_subrev_nc_u32_e32 v4, s6, v2
v_cmp_le_u32_e32 vcc_lo, s6, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_cndmask_b32 v2, v2, v4 :: v_dual_cndmask_b32 v1, v1, v3
v_cmp_le_u32_e32 vcc_lo, s6, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v3, 1, v1
v_cndmask_b32_e32 v1, v1, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v2, v1, s6
v_sub_nc_u32_e32 v0, v0, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_perm_b32 v2, v1, v0, 0x5040100
v_lshrrev_b32_e32 v0, 16, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_subrev_nc_u32_e32 v1, s7, v0
v_add_nc_u32_e32 v0, s7, v0
v_cmp_le_i32_e32 vcc_lo, v1, v0
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_7
; %bb.2: ; %.lr.ph56
s_clause 0x1
s_load_b128 s[8:11], s[0:1], 0x10
s_load_b64 s[2:3], s[0:1], 0x20
v_and_b32_e32 v3, 0xffff, v2
s_lshl_b32 s0, s12, 1
s_add_i32 s7, s6, -1
s_add_i32 s5, s5, -1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_subrev_nc_u32_e32 v2, s12, v3
v_add_nc_u32_e32 v3, s12, v3
s_or_b32 s12, s0, 1
v_cmp_le_i32_e32 vcc_lo, v2, v3
.LBB0_3: ; =>This Loop Header: Depth=1
; Child Loop BB0_5 Depth 2
s_and_saveexec_b32 s13, vcc_lo
s_cbranch_execz .LBB0_6
; %bb.4: ; %.lr.ph
; in Loop: Header=BB0_3 Depth=1
v_maxmin_i32 v3, v1, 0, s5
v_mov_b32_e32 v4, v2
s_mov_b32 s14, s12
s_delay_alu instid0(VALU_DEP_2)
v_mul_lo_u32 v3, v3, s6
.LBB0_5: ; Parent Loop BB0_3 Depth=1
; => This Inner Loop Header: Depth=2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_maxmin_i32 v5, v4, 0, s7
v_add_nc_u32_e32 v4, 1, v4
s_add_i32 s14, s14, -1
s_cmp_eq_u32 s14, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v9, v5, v3
v_ashrrev_i32_e32 v10, 31, v9
s_waitcnt lgkmcnt(0)
v_add_co_u32 v7, s1, s10, v9
v_add_co_u32 v5, s0, s8, v9
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e64 v8, s1, s11, v10, s1
v_add_co_ci_u32_e64 v6, s0, s9, v10, s0
global_load_u8 v7, v[7:8], off
global_load_u8 v5, v[5:6], off
s_waitcnt vmcnt(0)
v_add_nc_u16 v7, v5, v7
v_add_co_u32 v5, s0, s2, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e64 v6, s0, s3, v10, s0
v_lshrrev_b16 v7, 1, v7
global_store_b8 v[5:6], v7, off
s_cbranch_scc0 .LBB0_5
.LBB0_6: ; %Flow119
; in Loop: Header=BB0_3 Depth=1
s_or_b32 exec_lo, exec_lo, s13
v_add_nc_u32_e32 v3, 1, v1
v_cmp_eq_u32_e64 s0, v1, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mov_b32_e32 v1, v3
s_or_b32 s4, s0, s4
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s4
s_cbranch_execnz .LBB0_3
.LBB0_7: ; %.loopexit
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z31remove_redness_from_coordinatesPKjPhS1_S1_S1_iiiii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 320
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 11
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z31remove_redness_from_coordinatesPKjPhS1_S1_S1_iiiii, .Lfunc_end0-_Z31remove_redness_from_coordinatesPKjPhS1_S1_S1_iiiii
; -- End function
.section .AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 624
; NumSgprs: 18
; NumVgprs: 11
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 11
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object ; @__hip_cuid_
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0 ; 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .offset: 40
.size: 4
.value_kind: by_value
- .offset: 44
.size: 4
.value_kind: by_value
- .offset: 48
.size: 4
.value_kind: by_value
- .offset: 52
.size: 4
.value_kind: by_value
- .offset: 56
.size: 4
.value_kind: by_value
- .offset: 64
.size: 4
.value_kind: hidden_block_count_x
- .offset: 68
.size: 4
.value_kind: hidden_block_count_y
- .offset: 72
.size: 4
.value_kind: hidden_block_count_z
- .offset: 76
.size: 2
.value_kind: hidden_group_size_x
- .offset: 78
.size: 2
.value_kind: hidden_group_size_y
- .offset: 80
.size: 2
.value_kind: hidden_group_size_z
- .offset: 82
.size: 2
.value_kind: hidden_remainder_x
- .offset: 84
.size: 2
.value_kind: hidden_remainder_y
- .offset: 86
.size: 2
.value_kind: hidden_remainder_z
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 112
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 120
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 128
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 320
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z31remove_redness_from_coordinatesPKjPhS1_S1_S1_iiiii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z31remove_redness_from_coordinatesPKjPhS1_S1_S1_iiiii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 11
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
```
| 4,314 | 4,737 |
599 |
Convert the following CUDA host assembly code to AMD host assembly:
```cudaasm
.file "tmpxft_0008b061_00000000-6_remove_redness_from_coordinates.cudafe1.cpp"
.text
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z68__device_stub__Z31remove_redness_from_coordinatesPKjPhS1_S1_S1_iiiiiPKjPhS1_S1_S1_iiiii
.type _Z68__device_stub__Z31remove_redness_from_coordinatesPKjPhS1_S1_S1_iiiiiPKjPhS1_S1_S1_iiiii, @function
_Z68__device_stub__Z31remove_redness_from_coordinatesPKjPhS1_S1_S1_iiiiiPKjPhS1_S1_S1_iiiii:
.LFB2051:
.cfi_startproc
endbr64
subq $216, %rsp
.cfi_def_cfa_offset 224
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movq %r8, 8(%rsp)
movl %r9d, 4(%rsp)
movq %fs:40, %rax
movq %rax, 200(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
leaq 4(%rsp), %rax
movq %rax, 152(%rsp)
leaq 224(%rsp), %rax
movq %rax, 160(%rsp)
leaq 232(%rsp), %rax
movq %rax, 168(%rsp)
leaq 240(%rsp), %rax
movq %rax, 176(%rsp)
leaq 248(%rsp), %rax
movq %rax, 184(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 200(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $216, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 232
pushq 56(%rsp)
.cfi_def_cfa_offset 240
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z31remove_redness_from_coordinatesPKjPhS1_S1_S1_iiiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 224
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z68__device_stub__Z31remove_redness_from_coordinatesPKjPhS1_S1_S1_iiiiiPKjPhS1_S1_S1_iiiii, .-_Z68__device_stub__Z31remove_redness_from_coordinatesPKjPhS1_S1_S1_iiiiiPKjPhS1_S1_S1_iiiii
.globl _Z31remove_redness_from_coordinatesPKjPhS1_S1_S1_iiiii
.type _Z31remove_redness_from_coordinatesPKjPhS1_S1_S1_iiiii, @function
_Z31remove_redness_from_coordinatesPKjPhS1_S1_S1_iiiii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 24
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 40
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 48
call _Z68__device_stub__Z31remove_redness_from_coordinatesPKjPhS1_S1_S1_iiiiiPKjPhS1_S1_S1_iiiii
addq $40, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z31remove_redness_from_coordinatesPKjPhS1_S1_S1_iiiii, .-_Z31remove_redness_from_coordinatesPKjPhS1_S1_S1_iiiii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z31remove_redness_from_coordinatesPKjPhS1_S1_S1_iiiii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z31remove_redness_from_coordinatesPKjPhS1_S1_S1_iiiii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
```
|
```amdasm
.text
.file "remove_redness_from_coordinates.hip"
.globl _Z46__device_stub__remove_redness_from_coordinatesPKjPhS1_S1_S1_iiiii # -- Begin function _Z46__device_stub__remove_redness_from_coordinatesPKjPhS1_S1_S1_iiiii
.type _Z46__device_stub__remove_redness_from_coordinatesPKjPhS1_S1_S1_iiiii,@function
_Z46__device_stub__remove_redness_from_coordinatesPKjPhS1_S1_S1_iiiii: # @_Z46__device_stub__remove_redness_from_coordinatesPKjPhS1_S1_S1_iiiii
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $176, %rsp
.cfi_def_cfa_offset 224
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 56(%rsp), %rax
movq %rdi, (%rax)
leaq 48(%rsp), %rdi
movq %rsi, (%rdi)
leaq 40(%rsp), %rsi
movq %rdx, (%rsi)
leaq 32(%rsp), %rdx
movq %rcx, (%rdx)
leaq 24(%rsp), %rcx
movq %r8, (%rcx)
leaq 4(%rsp), %r8
movl %r9d, (%r8)
leaq 96(%rsp), %rbx
movq %rax, (%rbx)
movq %rdi, 8(%rbx)
movq %rsi, 16(%rbx)
movq %rdx, 24(%rbx)
movq %rcx, 32(%rbx)
movq %r8, 40(%rbx)
leaq 224(%rsp), %rax
movq %rax, 48(%rbx)
leaq 232(%rsp), %rax
movq %rax, 56(%rbx)
leaq 240(%rsp), %rax
movq %rax, 64(%rbx)
leaq 248(%rsp), %rax
movq %rax, 72(%rbx)
leaq 80(%rsp), %r14
leaq 64(%rsp), %r15
leaq 16(%rsp), %r12
leaq 8(%rsp), %r13
movq %r14, %rdi
movq %r15, %rsi
movq %r12, %rdx
movq %r13, %rcx
callq __hipPopCallConfiguration
movq (%r14), %rsi
movl 8(%r14), %edx
movq (%r15), %rcx
movl 8(%r15), %r8d
movl $_Z31remove_redness_from_coordinatesPKjPhS1_S1_S1_iiiii, %edi
movq %rbx, %r9
pushq (%r13)
.cfi_adjust_cfa_offset 8
pushq (%r12)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $192, %rsp
.cfi_adjust_cfa_offset -192
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z46__device_stub__remove_redness_from_coordinatesPKjPhS1_S1_S1_iiiii, .Lfunc_end0-_Z46__device_stub__remove_redness_from_coordinatesPKjPhS1_S1_S1_iiiii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, %rdi
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z31remove_redness_from_coordinatesPKjPhS1_S1_S1_iiiii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z31remove_redness_from_coordinatesPKjPhS1_S1_S1_iiiii,@object # @_Z31remove_redness_from_coordinatesPKjPhS1_S1_S1_iiiii
.section .rodata,"a",@progbits
.globl _Z31remove_redness_from_coordinatesPKjPhS1_S1_S1_iiiii
.p2align 3, 0x0
_Z31remove_redness_from_coordinatesPKjPhS1_S1_S1_iiiii:
.quad _Z46__device_stub__remove_redness_from_coordinatesPKjPhS1_S1_S1_iiiii
.size _Z31remove_redness_from_coordinatesPKjPhS1_S1_S1_iiiii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z31remove_redness_from_coordinatesPKjPhS1_S1_S1_iiiii"
.size .L__unnamed_1, 55
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z46__device_stub__remove_redness_from_coordinatesPKjPhS1_S1_S1_iiiii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z31remove_redness_from_coordinatesPKjPhS1_S1_S1_iiiii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
```
| 2,391 | 2,446 |
600 |
Convert the following CUDA device assembly code to AMD device assembly:
```cudaasm
code for sm_80
Function : _Z2bwifPfS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
MOV R1, c[0x0][0x28] ;
S2R R4, SR_CTAID.X ;
ISETP.GE.AND P0, PT, R4, c[0x0][0x160], PT ;
@P0 EXIT ;
HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ;
ULDC.64 UR4, c[0x0][0x118] ;
IMAD.WIDE R2, R4, R5, c[0x0][0x168] ;
IMAD.WIDE R4, R4, R5, c[0x0][0x170] ;
LDG.E R3, [R2.64] ;
LDG.E R0, [R4.64] ;
FFMA R7, R0, c[0x0][0x164], R3 ;
STG.E [R4.64], R7 ;
EXIT ;
BRA 0xd0;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
```
|
```amdasm
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z2bwifPfS_ ; -- Begin function _Z2bwifPfS_
.globl _Z2bwifPfS_
.p2align 8
.type _Z2bwifPfS_,@function
_Z2bwifPfS_: ; @_Z2bwifPfS_
; %bb.0:
s_load_b64 s[2:3], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_cmp_ge_i32 s15, s2
s_cbranch_scc1 .LBB0_2
; %bb.1:
s_load_b128 s[8:11], s[0:1], 0x8
s_mov_b32 s4, s15
s_ashr_i32 s5, s15, 31
v_mov_b32_e32 v1, 0
s_lshl_b64 s[0:1], s[4:5], 2
s_waitcnt lgkmcnt(0)
s_add_u32 s4, s8, s0
s_addc_u32 s5, s9, s1
s_add_u32 s0, s10, s0
s_load_b32 s2, s[4:5], 0x0
s_addc_u32 s1, s11, s1
s_load_b32 s4, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
v_mov_b32_e32 v0, s2
s_delay_alu instid0(VALU_DEP_1)
v_fmac_f32_e64 v0, s4, s3
global_store_b32 v1, v0, s[0:1]
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z2bwifPfS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 16
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z2bwifPfS_, .Lfunc_end0-_Z2bwifPfS_
; -- End function
.section .AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 120
; NumSgprs: 16
; NumVgprs: 2
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 1
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 16
; NumVGPRsForWavesPerEU: 2
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object ; @__hip_cuid_
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0 ; 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z2bwifPfS_
.private_segment_fixed_size: 0
.sgpr_count: 16
.sgpr_spill_count: 0
.symbol: _Z2bwifPfS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
```
| 337 | 1,979 |
601 |
Convert the following CUDA host assembly code to AMD host assembly:
```cudaasm
.file "tmpxft_0002e9ab_00000000-6_gpuKB.cudafe1.cpp"
.text
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z25__device_stub__Z2bwifPfS_ifPfS_
.type _Z25__device_stub__Z2bwifPfS_ifPfS_, @function
_Z25__device_stub__Z2bwifPfS_ifPfS_:
.LFB2082:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 28(%rsp)
movss %xmm0, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 24(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z2bwifPfS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z25__device_stub__Z2bwifPfS_ifPfS_, .-_Z25__device_stub__Z2bwifPfS_ifPfS_
.globl _Z2bwifPfS_
.type _Z2bwifPfS_, @function
_Z2bwifPfS_:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z25__device_stub__Z2bwifPfS_ifPfS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z2bwifPfS_, .-_Z2bwifPfS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC6:
.string "Bandwidth(GB/s): %f \n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $72, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl $4096, %edi
call malloc@PLT
movq %rax, %rbp
movl $4096, %edi
call malloc@PLT
movq %rax, %rbx
movq %rsp, %rdi
movl $4096, %esi
call cudaMalloc@PLT
leaq 8(%rsp), %rdi
movl $4096, %esi
call cudaMalloc@PLT
movl $0, %eax
movss .LC0(%rip), %xmm1
movss .LC1(%rip), %xmm0
.L12:
movss %xmm1, 0(%rbp,%rax)
movss %xmm0, (%rbx,%rax)
addq $4, %rax
cmpq $4096, %rax
jne .L12
movl $1, %ecx
movl $4096, %edx
movq %rbp, %rsi
movq (%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $4096, %edx
movq %rbx, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
leaq 16(%rsp), %rdi
call cudaEventCreate@PLT
leaq 24(%rsp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq 16(%rsp), %rdi
call cudaEventRecord@PLT
movl $448, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $3, 32(%rsp)
movl $1, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L17
.L13:
movl $0, %esi
movq 24(%rsp), %rdi
call cudaEventRecord@PLT
movq 24(%rsp), %rdi
call cudaEventSynchronize@PLT
movl $0x00000000, 44(%rsp)
leaq 44(%rsp), %rdi
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
call cudaEventElapsedTime@PLT
movss .LC4(%rip), %xmm0
divss 44(%rsp), %xmm0
cvtss2sd %xmm0, %xmm0
divsd .LC5(%rip), %xmm0
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq (%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L18
movl $0, %eax
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L17:
.cfi_restore_state
movq 8(%rsp), %rdx
movq (%rsp), %rsi
movss .LC2(%rip), %xmm0
movl $1024, %edi
call _Z25__device_stub__Z2bwifPfS_ifPfS_
jmp .L13
.L18:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC7:
.string "_Z2bwifPfS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _Z2bwifPfS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC0:
.long 1082130432
.align 4
.LC1:
.long 1065353216
.align 4
.LC2:
.long 1073741824
.align 4
.LC4:
.long 1178599424
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC5:
.long 0
.long 1093567616
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
```
|
```amdasm
.text
.file "gpuKB.hip"
.globl _Z17__device_stub__bwifPfS_ # -- Begin function _Z17__device_stub__bwifPfS_
.type _Z17__device_stub__bwifPfS_,@function
_Z17__device_stub__bwifPfS_: # @_Z17__device_stub__bwifPfS_
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $112, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 12(%rsp), %rax
movl %edi, (%rax)
leaq 8(%rsp), %rcx
movss %xmm0, (%rcx)
leaq 40(%rsp), %rdi
movq %rsi, (%rdi)
leaq 32(%rsp), %rsi
movq %rdx, (%rsi)
leaq 80(%rsp), %rbx
movq %rax, (%rbx)
movq %rcx, 8(%rbx)
movq %rdi, 16(%rbx)
movq %rsi, 24(%rbx)
leaq 64(%rsp), %r14
leaq 48(%rsp), %r15
leaq 24(%rsp), %r12
leaq 16(%rsp), %r13
movq %r14, %rdi
movq %r15, %rsi
movq %r12, %rdx
movq %r13, %rcx
callq __hipPopCallConfiguration
movq (%r14), %rsi
movl 8(%r14), %edx
movq (%r15), %rcx
movl 8(%r15), %r8d
movl $_Z2bwifPfS_, %edi
movq %rbx, %r9
pushq (%r13)
.cfi_adjust_cfa_offset 8
pushq (%r12)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $128, %rsp
.cfi_adjust_cfa_offset -128
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z17__device_stub__bwifPfS_, .Lfunc_end0-_Z17__device_stub__bwifPfS_
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI1_0:
.long 0x40000000 # float 2
.LCPI1_1:
.long 0x46400000 # float 12288
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0
.LCPI1_2:
.quad 0x412e848000000000 # double 1.0E+6
.text
.globl main
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $40, %rsp
.cfi_def_cfa_offset 64
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movl $4096, %edi # imm = 0x1000
callq malloc
movq %rax, %r14
movl $4096, %edi # imm = 0x1000
callq malloc
movq %rax, %rbx
leaq 16(%rsp), %rdi
movl $4096, %esi # imm = 0x1000
callq hipMalloc
leaq 8(%rsp), %rdi
movl $4096, %esi # imm = 0x1000
callq hipMalloc
xorl %eax, %eax
.LBB1_1: # =>This Inner Loop Header: Depth=1
movl $1082130432, (%r14,%rax,4) # imm = 0x40800000
movl $1065353216, (%rbx,%rax,4) # imm = 0x3F800000
incq %rax
cmpq $1024, %rax # imm = 0x400
jne .LBB1_1
# %bb.2:
movq 16(%rsp), %rdi
movl $4096, %edx # imm = 0x1000
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
movl $4096, %edx # imm = 0x1000
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
leaq 24(%rsp), %rbx
movq %rbx, %rdi
callq hipEventCreate
movq %rsp, %rdi
callq hipEventCreate
movq (%rbx), %rdi
xorl %esi, %esi
callq hipEventRecord
movabsq $4294967299, %rdi # imm = 0x100000003
leaq 445(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq 16(%rsp), %rsi
movq 8(%rsp), %rdx
movss .LCPI1_0(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero
movl $1024, %edi # imm = 0x400
callq _Z17__device_stub__bwifPfS_
.LBB1_4:
movq (%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq (%rsp), %rdi
callq hipEventSynchronize
leaq 36(%rsp), %rbx
movl $0, (%rbx)
movq 24(%rsp), %rsi
movq (%rsp), %rdx
movq %rbx, %rdi
callq hipEventElapsedTime
movss .LCPI1_1(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero
divss (%rbx), %xmm0
cvtss2sd %xmm0, %xmm0
divsd .LCPI1_2(%rip), %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $40, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, %rdi
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z2bwifPfS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z2bwifPfS_,@object # @_Z2bwifPfS_
.section .rodata,"a",@progbits
.globl _Z2bwifPfS_
.p2align 3, 0x0
_Z2bwifPfS_:
.quad _Z17__device_stub__bwifPfS_
.size _Z2bwifPfS_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Bandwidth(GB/s): %f \n"
.size .L.str, 22
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z2bwifPfS_"
.size .L__unnamed_1, 12
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z17__device_stub__bwifPfS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z2bwifPfS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
```
| 3,205 | 3,439 |
606 |
Convert the following CUDA device assembly code to AMD device assembly:
```cudaasm
code for sm_80
Function : _Z16matrixMultDevicePfS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
MOV R1, c[0x0][0x28] ;
S2R R0, SR_CTAID.X ;
S2R R5, SR_TID.X ;
S2R R3, SR_CTAID.Y ;
S2R R2, SR_TID.Y ;
IMAD R0, R0, c[0x0][0x0], R5 ;
ISETP.GE.AND P0, PT, R0, c[0x0][0x178], PT ;
IMAD R3, R3, c[0x0][0x4], R2 ;
ISETP.GE.OR P0, PT, R3, c[0x0][0x178], P0 ;
@P0 EXIT ;
MOV R2, c[0x0][0x178] ;
ULDC.64 UR4, c[0x0][0x118] ;
HFMA2.MMA R28, -RZ, RZ, 0, 0 ;
IMAD R3, R3, c[0x0][0x178], RZ ;
ISETP.GE.AND P0, PT, R2, 0x1, PT ;
@!P0 BRA 0xc00 ;
IADD3 R4, R2.reuse, -0x1, RZ ;
LOP3.LUT R5, R2, 0x3, RZ, 0xc0, !PT ;
ISETP.GE.U32.AND P0, PT, R4, 0x3, PT ;
MOV R28, RZ ;
MOV R4, RZ ;
@!P0 BRA 0xb00 ;
IADD3 R6, -R5, c[0x0][0x178], RZ ;
HFMA2.MMA R25, -RZ, RZ, 0, 2.384185791015625e-07 ;
ULDC.64 UR6, c[0x0][0x160] ;
HFMA2.MMA R4, -RZ, RZ, 0, 0 ;
ISETP.GT.AND P0, PT, R6, RZ, PT ;
MOV R28, RZ ;
IMAD.WIDE R24, R0, R25, c[0x0][0x168] ;
@!P0 BRA 0x970 ;
ISETP.GT.AND P1, PT, R6, 0xc, PT ;
PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ;
@!P1 BRA 0x6b0 ;
PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ;
MOV R12, UR6 ;
LDG.E R29, [R24.64] ;
MOV R13, UR7 ;
IMAD.WIDE R12, R3, 0x4, R12 ;
LDG.E R27, [R12.64] ;
IMAD.WIDE R10, R2, 0x4, R24 ;
LDG.E R17, [R12.64+0x4] ;
IMAD.WIDE R18, R2.reuse, 0x4, R10 ;
LDG.E R16, [R10.64] ;
LDG.E R7, [R12.64+0xc] ;
IMAD.WIDE R14, R2, 0x4, R18 ;
LDG.E R18, [R18.64] ;
IMAD.WIDE R20, R2.reuse, 0x4, R14 ;
LDG.E R26, [R14.64] ;
LDG.E R9, [R12.64+0x10] ;
LDG.E R19, [R12.64+0x8] ;
IMAD.WIDE R14, R2, 0x4, R20 ;
LDG.E R20, [R20.64] ;
IMAD.WIDE R22, R2.reuse, 0x4, R14 ;
LDG.E R8, [R14.64] ;
LDG.E R11, [R12.64+0x14] ;
IMAD.WIDE R24, R2, 0x4, R22 ;
LDG.E R10, [R22.64] ;
LDG.E R21, [R12.64+0x18] ;
FFMA R29, R29, R27, R28 ;
LDG.E R27, [R12.64+0x1c] ;
LDG.E R28, [R24.64] ;
IMAD.WIDE R14, R2, 0x4, R24 ;
FFMA R29, R16, R17, R29 ;
IMAD.WIDE R16, R2, 0x4, R14 ;
LDG.E R14, [R14.64] ;
FFMA R29, R18, R19, R29 ;
IMAD.WIDE R18, R2, 0x4, R16 ;
LDG.E R16, [R16.64] ;
FFMA R26, R26, R7, R29 ;
IMAD.WIDE R22, R2.reuse, 0x4, R18 ;
LDG.E R7, [R12.64+0x20] ;
LDG.E R29, [R12.64+0x24] ;
IMAD.WIDE R24, R2, 0x4, R22 ;
LDG.E R18, [R18.64] ;
FFMA R9, R20, R9, R26 ;
LDG.E R26, [R12.64+0x28] ;
FFMA R11, R8, R11, R9 ;
IMAD.WIDE R8, R2, 0x4, R24 ;
LDG.E R22, [R22.64] ;
LDG.E R17, [R12.64+0x2c] ;
FFMA R21, R10, R21, R11 ;
LDG.E R15, [R24.64] ;
IMAD.WIDE R10, R2, 0x4, R8 ;
LDG.E R19, [R8.64] ;
LDG.E R23, [R10.64] ;
LDG.E R24, [R12.64+0x30] ;
LDG.E R25, [R12.64+0x38] ;
LDG.E R8, [R12.64+0x3c] ;
FFMA R9, R28, R27, R21 ;
LDG.E R28, [R12.64+0x34] ;
IMAD.WIDE R20, R2, 0x4, R10 ;
LDG.E R27, [R20.64] ;
IADD3 R6, R6, -0x10, RZ ;
ISETP.GT.AND P1, PT, R6, 0xc, PT ;
FFMA R7, R14, R7, R9 ;
FFMA R7, R16, R29, R7 ;
FFMA R7, R18, R26, R7 ;
FFMA R7, R22, R17, R7 ;
UIADD3 UR6, UP0, UR6, 0x40, URZ ;
IADD3 R4, R4, 0x10, RZ ;
UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ;
FFMA R7, R15, R24, R7 ;
FFMA R28, R19, R28, R7 ;
FFMA R28, R23, R25, R28 ;
IMAD.WIDE R24, R2, 0x4, R20 ;
FFMA R28, R27, R8, R28 ;
@P1 BRA 0x220 ;
ISETP.GT.AND P1, PT, R6, 0x4, PT ;
@!P1 BRA 0x950 ;
IMAD.WIDE R16, R2, 0x4, R24 ;
MOV R8, UR6 ;
LDG.E R7, [R24.64] ;
MOV R9, UR7 ;
IMAD.WIDE R12, R2.reuse, 0x4, R16 ;
LDG.E R21, [R16.64] ;
IMAD.WIDE R8, R3, 0x4, R8 ;
LDG.E R23, [R12.64] ;
IMAD.WIDE R14, R2.reuse, 0x4, R12 ;
LDG.E R20, [R8.64] ;
LDG.E R22, [R8.64+0x4] ;
IMAD.WIDE R10, R2, 0x4, R14 ;
LDG.E R26, [R8.64+0x8] ;
IMAD.WIDE R16, R2.reuse, 0x4, R10 ;
LDG.E R14, [R14.64] ;
LDG.E R27, [R8.64+0xc] ;
IMAD.WIDE R18, R2, 0x4, R16 ;
LDG.E R10, [R10.64] ;
LDG.E R25, [R8.64+0x10] ;
IMAD.WIDE R12, R2, 0x4, R18 ;
LDG.E R16, [R16.64] ;
LDG.E R29, [R8.64+0x14] ;
LDG.E R24, [R18.64] ;
LDG.E R11, [R8.64+0x18] ;
LDG.E R15, [R12.64] ;
LDG.E R18, [R8.64+0x1c] ;
UIADD3 UR6, UP0, UR6, 0x20, URZ ;
PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ;
IADD3 R4, R4, 0x8, RZ ;
IADD3 R6, R6, -0x8, RZ ;
UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ;
FFMA R7, R7, R20, R28 ;
FFMA R7, R21, R22, R7 ;
FFMA R7, R23, R26, R7 ;
FFMA R7, R14, R27, R7 ;
FFMA R7, R10, R25, R7 ;
FFMA R7, R16, R29, R7 ;
FFMA R7, R24, R11, R7 ;
IMAD.WIDE R24, R2, 0x4, R12 ;
FFMA R28, R15, R18, R7 ;
ISETP.NE.OR P0, PT, R6, RZ, P0 ;
@!P0 BRA 0xb00 ;
MOV R8, UR6 ;
IMAD.WIDE R14, R2, 0x4, R24 ;
MOV R9, UR7 ;
LDG.E R25, [R24.64] ;
IMAD.WIDE R8, R3, 0x4, R8 ;
IMAD.WIDE R12, R2.reuse, 0x4, R14 ;
LDG.E R7, [R8.64] ;
LDG.E R14, [R14.64] ;
IMAD.WIDE R10, R2, 0x4, R12 ;
LDG.E R16, [R8.64+0x4] ;
LDG.E R18, [R12.64] ;
LDG.E R17, [R8.64+0x8] ;
LDG.E R19, [R8.64+0xc] ;
LDG.E R20, [R10.64] ;
IADD3 R6, R6, -0x4, RZ ;
ISETP.NE.AND P0, PT, R6, RZ, PT ;
UIADD3 UR6, UP0, UR6, 0x10, URZ ;
IADD3 R4, R4, 0x4, RZ ;
UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ;
FFMA R7, R25, R7, R28 ;
FFMA R7, R14, R16, R7 ;
IMAD.WIDE R24, R2, 0x4, R10 ;
FFMA R7, R18, R17, R7 ;
FFMA R28, R20, R19, R7 ;
@P0 BRA 0x970 ;
ISETP.NE.AND P0, PT, R5, RZ, PT ;
@!P0 BRA 0xc00 ;
HFMA2.MMA R9, -RZ, RZ, 0, 2.384185791015625e-07 ;
IADD3 R6, R3, R4, RZ ;
IMAD R4, R4, c[0x0][0x178], R0 ;
IMAD.WIDE R6, R6, R9, c[0x0][0x160] ;
IMAD.WIDE R8, R4, R9, c[0x0][0x168] ;
LDG.E R11, [R8.64] ;
LDG.E R4, [R6.64] ;
IADD3 R5, R5, -0x1, RZ ;
ISETP.NE.AND P0, PT, R5, RZ, PT ;
IMAD.WIDE R8, R2, 0x4, R8 ;
IADD3 R6, P1, R6, 0x4, RZ ;
IADD3.X R7, RZ, R7, RZ, P1, !PT ;
FFMA R28, R11, R4, R28 ;
@P0 BRA 0xb70 ;
IADD3 R3, R0, R3, RZ ;
MOV R2, 0x4 ;
IMAD.WIDE R2, R3, R2, c[0x0][0x170] ;
STG.E [R2.64], R28 ;
EXIT ;
BRA 0xc50;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
```
|
```amdasm
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z16matrixMultDevicePfS_S_i ; -- Begin function _Z16matrixMultDevicePfS_S_i
.globl _Z16matrixMultDevicePfS_S_i
.p2align 8
.type _Z16matrixMultDevicePfS_S_i,@function
_Z16matrixMultDevicePfS_S_i: ; @_Z16matrixMultDevicePfS_S_i
; %bb.0:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x2c
s_load_b32 s2, s[0:1], 0x18
v_bfe_u32 v1, v0, 10, 10
v_and_b32_e32 v4, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s4, s3, 16
s_and_b32 s3, s3, 0xffff
v_mad_u64_u32 v[2:3], null, s15, s4, v[1:2]
v_mad_u64_u32 v[0:1], null, s14, s3, v[4:5]
s_mov_b32 s3, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_max_i32_e32 v1, v2, v0
v_cmpx_gt_i32_e64 s2, v1
s_cbranch_execz .LBB0_6
; %bb.1: ; %.preheader
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
v_mul_lo_u32 v1, v2, s2
s_cmp_lt_i32 s2, 1
s_cbranch_scc1 .LBB0_4
; %bb.2: ; %.lr.ph.preheader
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
v_ashrrev_i32_e32 v2, 31, v1
v_mov_b32_e32 v6, 0
v_mov_b32_e32 v4, v0
s_mov_b32 s3, s2
v_lshlrev_b64 v[2:3], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
.LBB0_3: ; %.lr.ph
; =>This Inner Loop Header: Depth=1
v_ashrrev_i32_e32 v5, 31, v4
s_add_i32 s3, s3, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_cmp_eq_u32 s3, 0
v_lshlrev_b64 v[7:8], 2, v[4:5]
v_add_nc_u32_e32 v4, s2, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v7, vcc_lo, s6, v7
v_add_co_ci_u32_e32 v8, vcc_lo, s7, v8, vcc_lo
global_load_b32 v5, v[2:3], off
global_load_b32 v7, v[7:8], off
v_add_co_u32 v2, vcc_lo, v2, 4
v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v6, v5, v7
s_cbranch_scc0 .LBB0_3
s_branch .LBB0_5
.LBB0_4:
v_mov_b32_e32 v6, 0
.LBB0_5: ; %Flow46
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v0, v1, v0
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v6, off
.LBB0_6:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z16matrixMultDevicePfS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z16matrixMultDevicePfS_S_i, .Lfunc_end0-_Z16matrixMultDevicePfS_S_i
; -- End function
.section .AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 332
; NumSgprs: 18
; NumVgprs: 9
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 9
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object ; @__hip_cuid_
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0 ; 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z16matrixMultDevicePfS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z16matrixMultDevicePfS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
```
| 3,632 | 3,261 |
607 |
Convert the following CUDA host assembly code to AMD host assembly:
```cudaasm
.file "tmpxft_000bacc7_00000000-6_matrixMultDevice.cudafe1.cpp"
.text
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z41__device_stub__Z16matrixMultDevicePfS_S_iPfS_S_i
.type _Z41__device_stub__Z16matrixMultDevicePfS_S_iPfS_S_i, @function
_Z41__device_stub__Z16matrixMultDevicePfS_S_iPfS_S_i:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z16matrixMultDevicePfS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z41__device_stub__Z16matrixMultDevicePfS_S_iPfS_S_i, .-_Z41__device_stub__Z16matrixMultDevicePfS_S_iPfS_S_i
.globl _Z16matrixMultDevicePfS_S_i
.type _Z16matrixMultDevicePfS_S_i, @function
_Z16matrixMultDevicePfS_S_i:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z41__device_stub__Z16matrixMultDevicePfS_S_iPfS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z16matrixMultDevicePfS_S_i, .-_Z16matrixMultDevicePfS_S_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z16matrixMultDevicePfS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z16matrixMultDevicePfS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
```
|
```amdasm
.text
.file "matrixMultDevice.hip"
.globl _Z31__device_stub__matrixMultDevicePfS_S_i # -- Begin function _Z31__device_stub__matrixMultDevicePfS_S_i
.type _Z31__device_stub__matrixMultDevicePfS_S_i,@function
_Z31__device_stub__matrixMultDevicePfS_S_i: # @_Z31__device_stub__matrixMultDevicePfS_S_i
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $112, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 40(%rsp), %rax
movq %rdi, (%rax)
leaq 32(%rsp), %rdi
movq %rsi, (%rdi)
leaq 24(%rsp), %rsi
movq %rdx, (%rsi)
leaq 4(%rsp), %rdx
movl %ecx, (%rdx)
leaq 80(%rsp), %rbx
movq %rax, (%rbx)
movq %rdi, 8(%rbx)
movq %rsi, 16(%rbx)
movq %rdx, 24(%rbx)
leaq 64(%rsp), %r14
leaq 48(%rsp), %r15
leaq 16(%rsp), %r12
leaq 8(%rsp), %r13
movq %r14, %rdi
movq %r15, %rsi
movq %r12, %rdx
movq %r13, %rcx
callq __hipPopCallConfiguration
movq (%r14), %rsi
movl 8(%r14), %edx
movq (%r15), %rcx
movl 8(%r15), %r8d
movl $_Z16matrixMultDevicePfS_S_i, %edi
movq %rbx, %r9
pushq (%r13)
.cfi_adjust_cfa_offset 8
pushq (%r12)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $128, %rsp
.cfi_adjust_cfa_offset -128
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z31__device_stub__matrixMultDevicePfS_S_i, .Lfunc_end0-_Z31__device_stub__matrixMultDevicePfS_S_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, %rdi
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z16matrixMultDevicePfS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z16matrixMultDevicePfS_S_i,@object # @_Z16matrixMultDevicePfS_S_i
.section .rodata,"a",@progbits
.globl _Z16matrixMultDevicePfS_S_i
.p2align 3, 0x0
_Z16matrixMultDevicePfS_S_i:
.quad _Z31__device_stub__matrixMultDevicePfS_S_i
.size _Z16matrixMultDevicePfS_S_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z16matrixMultDevicePfS_S_i"
.size .L__unnamed_1, 28
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z31__device_stub__matrixMultDevicePfS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z16matrixMultDevicePfS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
```
| 1,917 | 2,100 |
614 |
Convert the following CUDA device assembly code to AMD device assembly:
```cudaasm
code for sm_80
Function : _Z18multiply_on_devicePfS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
MOV R1, c[0x0][0x28] ;
S2R R4, SR_CTAID.X ;
MOV R0, c[0x0][0x178] ;
ULDC.64 UR4, c[0x0][0x118] ;
HFMA2.MMA R28, -RZ, RZ, 0, 0 ;
S2R R3, SR_TID.X ;
ISETP.GE.AND P0, PT, R0, 0x1, PT ;
S2R R2, SR_CTAID.Y ;
S2R R5, SR_TID.Y ;
IMAD R4, R4, c[0x0][0x0], R3 ;
IMAD R4, R4, c[0x0][0x178], RZ ;
IMAD R2, R2, c[0x0][0x4], R5 ;
@!P0 BRA 0xbf0 ;
IADD3 R3, R0.reuse, -0x1, RZ ;
LOP3.LUT R5, R0, 0x3, RZ, 0xc0, !PT ;
ISETP.GE.U32.AND P0, PT, R3, 0x3, PT ;
MOV R28, RZ ;
MOV R3, RZ ;
@!P0 BRA 0xad0 ;
IADD3 R6, -R5, c[0x0][0x178], RZ ;
HFMA2.MMA R25, -RZ, RZ, 0, 2.384185791015625e-07 ;
ULDC.64 UR6, c[0x0][0x160] ;
HFMA2.MMA R3, -RZ, RZ, 0, 0 ;
ISETP.GT.AND P0, PT, R6, RZ, PT ;
MOV R28, RZ ;
IMAD.WIDE R24, R2, R25, c[0x0][0x168] ;
@!P0 BRA 0x940 ;
ISETP.GT.AND P1, PT, R6, 0xc, PT ;
PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ;
@!P1 BRA 0x680 ;
PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ;
MOV R12, UR6 ;
LDG.E R29, [R24.64] ;
MOV R13, UR7 ;
IMAD.WIDE R12, R4, 0x4, R12 ;
LDG.E R27, [R12.64] ;
IMAD.WIDE R10, R0, 0x4, R24 ;
LDG.E R17, [R12.64+0x4] ;
IMAD.WIDE R18, R0.reuse, 0x4, R10 ;
LDG.E R16, [R10.64] ;
LDG.E R7, [R12.64+0xc] ;
IMAD.WIDE R14, R0, 0x4, R18 ;
LDG.E R18, [R18.64] ;
IMAD.WIDE R20, R0.reuse, 0x4, R14 ;
LDG.E R26, [R14.64] ;
LDG.E R9, [R12.64+0x10] ;
LDG.E R19, [R12.64+0x8] ;
IMAD.WIDE R14, R0, 0x4, R20 ;
LDG.E R20, [R20.64] ;
IMAD.WIDE R22, R0.reuse, 0x4, R14 ;
LDG.E R8, [R14.64] ;
LDG.E R11, [R12.64+0x14] ;
IMAD.WIDE R24, R0, 0x4, R22 ;
LDG.E R10, [R22.64] ;
LDG.E R21, [R12.64+0x18] ;
FFMA R29, R29, R27, R28 ;
LDG.E R27, [R12.64+0x1c] ;
LDG.E R28, [R24.64] ;
IMAD.WIDE R14, R0, 0x4, R24 ;
FFMA R29, R16, R17, R29 ;
IMAD.WIDE R16, R0, 0x4, R14 ;
LDG.E R14, [R14.64] ;
FFMA R29, R18, R19, R29 ;
IMAD.WIDE R18, R0, 0x4, R16 ;
LDG.E R16, [R16.64] ;
FFMA R26, R26, R7, R29 ;
IMAD.WIDE R22, R0.reuse, 0x4, R18 ;
LDG.E R7, [R12.64+0x20] ;
LDG.E R29, [R12.64+0x24] ;
IMAD.WIDE R24, R0, 0x4, R22 ;
LDG.E R18, [R18.64] ;
FFMA R9, R20, R9, R26 ;
LDG.E R26, [R12.64+0x28] ;
FFMA R11, R8, R11, R9 ;
IMAD.WIDE R8, R0, 0x4, R24 ;
LDG.E R22, [R22.64] ;
LDG.E R17, [R12.64+0x2c] ;
FFMA R21, R10, R21, R11 ;
LDG.E R15, [R24.64] ;
IMAD.WIDE R10, R0, 0x4, R8 ;
LDG.E R19, [R8.64] ;
LDG.E R23, [R10.64] ;
LDG.E R24, [R12.64+0x30] ;
LDG.E R25, [R12.64+0x38] ;
LDG.E R8, [R12.64+0x3c] ;
FFMA R9, R28, R27, R21 ;
LDG.E R28, [R12.64+0x34] ;
IMAD.WIDE R20, R0, 0x4, R10 ;
LDG.E R27, [R20.64] ;
IADD3 R6, R6, -0x10, RZ ;
ISETP.GT.AND P1, PT, R6, 0xc, PT ;
FFMA R7, R14, R7, R9 ;
FFMA R7, R16, R29, R7 ;
FFMA R7, R18, R26, R7 ;
FFMA R7, R22, R17, R7 ;
UIADD3 UR6, UP0, UR6, 0x40, URZ ;
IADD3 R3, R3, 0x10, RZ ;
UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ;
FFMA R7, R15, R24, R7 ;
FFMA R28, R19, R28, R7 ;
FFMA R28, R23, R25, R28 ;
IMAD.WIDE R24, R0, 0x4, R20 ;
FFMA R28, R27, R8, R28 ;
@P1 BRA 0x1f0 ;
ISETP.GT.AND P1, PT, R6, 0x4, PT ;
@!P1 BRA 0x920 ;
IMAD.WIDE R16, R0, 0x4, R24 ;
MOV R8, UR6 ;
LDG.E R7, [R24.64] ;
MOV R9, UR7 ;
IMAD.WIDE R12, R0, 0x4, R16 ;
LDG.E R21, [R16.64] ;
IMAD.WIDE R8, R4, 0x4, R8 ;
LDG.E R23, [R12.64] ;
IMAD.WIDE R14, R0.reuse, 0x4, R12 ;
LDG.E R20, [R8.64] ;
LDG.E R22, [R8.64+0x4] ;
IMAD.WIDE R10, R0, 0x4, R14 ;
LDG.E R26, [R8.64+0x8] ;
IMAD.WIDE R16, R0.reuse, 0x4, R10 ;
LDG.E R14, [R14.64] ;
LDG.E R27, [R8.64+0xc] ;
IMAD.WIDE R18, R0, 0x4, R16 ;
LDG.E R10, [R10.64] ;
LDG.E R25, [R8.64+0x10] ;
IMAD.WIDE R12, R0, 0x4, R18 ;
LDG.E R16, [R16.64] ;
LDG.E R29, [R8.64+0x14] ;
LDG.E R24, [R18.64] ;
LDG.E R11, [R8.64+0x18] ;
LDG.E R15, [R12.64] ;
LDG.E R18, [R8.64+0x1c] ;
UIADD3 UR6, UP0, UR6, 0x20, URZ ;
PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ;
IADD3 R3, R3, 0x8, RZ ;
IADD3 R6, R6, -0x8, RZ ;
UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ;
FFMA R7, R7, R20, R28 ;
FFMA R7, R21, R22, R7 ;
FFMA R7, R23, R26, R7 ;
FFMA R7, R14, R27, R7 ;
FFMA R7, R10, R25, R7 ;
FFMA R7, R16, R29, R7 ;
FFMA R7, R24, R11, R7 ;
IMAD.WIDE R24, R0, 0x4, R12 ;
FFMA R28, R15, R18, R7 ;
ISETP.NE.OR P0, PT, R6, RZ, P0 ;
@!P0 BRA 0xad0 ;
MOV R8, UR6 ;
IMAD.WIDE R14, R0, 0x4, R24 ;
MOV R9, UR7 ;
LDG.E R25, [R24.64] ;
IMAD.WIDE R8, R4, 0x4, R8 ;
IMAD.WIDE R12, R0.reuse, 0x4, R14 ;
LDG.E R7, [R8.64] ;
LDG.E R14, [R14.64] ;
IMAD.WIDE R10, R0, 0x4, R12 ;
LDG.E R16, [R8.64+0x4] ;
LDG.E R18, [R12.64] ;
LDG.E R17, [R8.64+0x8] ;
LDG.E R19, [R8.64+0xc] ;
LDG.E R20, [R10.64] ;
IADD3 R6, R6, -0x4, RZ ;
ISETP.NE.AND P0, PT, R6, RZ, PT ;
UIADD3 UR6, UP0, UR6, 0x10, URZ ;
IADD3 R3, R3, 0x4, RZ ;
UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ;
FFMA R7, R25, R7, R28 ;
FFMA R7, R14, R16, R7 ;
IMAD.WIDE R24, R0, 0x4, R10 ;
FFMA R7, R18, R17, R7 ;
FFMA R28, R20, R19, R7 ;
@P0 BRA 0x940 ;
ISETP.NE.AND P0, PT, R5, RZ, PT ;
@!P0 BRA 0xbf0 ;
HFMA2.MMA R8, -RZ, RZ, 0, 2.384185791015625e-07 ;
IADD3 R6, R4, R3, RZ ;
IMAD R3, R3, c[0x0][0x178], R2 ;
IMAD.WIDE R6, R6, R8, c[0x0][0x160] ;
IMAD.WIDE R8, R3, R8, c[0x0][0x168] ;
MOV R10, R6 ;
MOV R6, R10 ;
LDG.E R3, [R8.64] ;
LDG.E R6, [R6.64] ;
IADD3 R5, R5, -0x1, RZ ;
IADD3 R10, P1, R10, 0x4, RZ ;
ISETP.NE.AND P0, PT, R5, RZ, PT ;
IMAD.WIDE R8, R0, 0x4, R8 ;
IADD3.X R7, RZ, R7, RZ, P1, !PT ;
FFMA R28, R3, R6, R28 ;
@P0 BRA 0xb50 ;
IADD3 R2, R2, R4, RZ ;
MOV R3, 0x4 ;
IMAD.WIDE R2, R2, R3, c[0x0][0x170] ;
STG.E [R2.64], R28 ;
EXIT ;
BRA 0xc40;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
```
|
```amdasm
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z18multiply_on_devicePfS_S_i ; -- Begin function _Z18multiply_on_devicePfS_S_i
.globl _Z18multiply_on_devicePfS_S_i
.p2align 8
.type _Z18multiply_on_devicePfS_S_i,@function
_Z18multiply_on_devicePfS_S_i: ; @_Z18multiply_on_devicePfS_S_i
; %bb.0:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x2c
s_load_b32 s2, s[0:1], 0x18
v_and_b32_e32 v1, 0x3ff, v0
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s8, s3, 0xffff
s_lshr_b32 s3, s3, 16
v_mad_u64_u32 v[2:3], null, s14, s8, v[1:2]
v_bfe_u32 v3, v0, 10, 10
s_cmp_lt_i32 s2, 1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_mad_u64_u32 v[0:1], null, s15, s3, v[3:4]
v_mul_lo_u32 v1, v2, s2
s_cbranch_scc1 .LBB0_3
; %bb.1: ; %.lr.ph.preheader
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_ashrrev_i32_e32 v2, 31, v1
v_mov_b32_e32 v6, 0
v_mov_b32_e32 v4, v0
s_mov_b32 s3, s2
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[1:2]
v_add_co_u32 v2, vcc_lo, s4, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
.LBB0_2: ; %.lr.ph
; =>This Inner Loop Header: Depth=1
v_ashrrev_i32_e32 v5, 31, v4
s_add_i32 s3, s3, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_cmp_eq_u32 s3, 0
v_lshlrev_b64 v[7:8], 2, v[4:5]
v_add_nc_u32_e32 v4, s2, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v7, vcc_lo, s6, v7
v_add_co_ci_u32_e32 v8, vcc_lo, s7, v8, vcc_lo
global_load_b32 v5, v[2:3], off
global_load_b32 v7, v[7:8], off
v_add_co_u32 v2, vcc_lo, v2, 4
v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v6, v5, v7
s_cbranch_scc0 .LBB0_2
s_branch .LBB0_4
.LBB0_3:
v_mov_b32_e32 v6, 0
.LBB0_4: ; %Flow41
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v0, v1, v0
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[0:1]
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v6, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z18multiply_on_devicePfS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z18multiply_on_devicePfS_S_i, .Lfunc_end0-_Z18multiply_on_devicePfS_S_i
; -- End function
.section .AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 308
; NumSgprs: 18
; NumVgprs: 9
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 9
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object ; @__hip_cuid_
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0 ; 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z18multiply_on_devicePfS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z18multiply_on_devicePfS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
```
| 3,583 | 3,180 |
615 |
Convert the following CUDA host assembly code to AMD host assembly:
```cudaasm
.file "tmpxft_0008bba0_00000000-6_biswas_rajarshi_lab4p1.cudafe1.cpp"
.text
.globl _ZSt21ios_base_library_initv
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3674:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3674:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z16multiply_on_hostPfS_S_
.type _Z16multiply_on_hostPfS_S_, @function
_Z16multiply_on_hostPfS_S_:
.LFB3669:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movq %rdi, %rbx
movq %rsi, %r11
movq %rdx, %r10
movl $0, %r9d
.L4:
leaq 4194304(%r11), %rcx
movq %r9, %rdi
salq $12, %rdi
leaq (%rbx,%rdi), %r8
addq %r10, %rdi
movl $0, %esi
.L8:
leaq -4194304(%rcx), %rax
movq %r8, %rdx
pxor %xmm1, %xmm1
.L5:
movss (%rdx), %xmm0
mulss (%rax), %xmm0
addss %xmm0, %xmm1
addq $4, %rdx
addq $4096, %rax
cmpq %rcx, %rax
jne .L5
movss %xmm1, (%rdi,%rsi,4)
addq $1, %rsi
addq $4, %rcx
cmpq $1024, %rsi
jne .L8
addq $1, %r9
cmpq $1024, %r9
jne .L4
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3669:
.size _Z16multiply_on_hostPfS_S_, .-_Z16multiply_on_hostPfS_S_
.globl _Z11RandomFloatff
.type _Z11RandomFloatff, @function
_Z11RandomFloatff:
.LFB3670:
.cfi_startproc
endbr64
subq $24, %rsp
.cfi_def_cfa_offset 32
movss %xmm0, 8(%rsp)
movss %xmm1, 12(%rsp)
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
mulss .LC1(%rip), %xmm0
movss 12(%rsp), %xmm1
movss 8(%rsp), %xmm2
subss %xmm2, %xmm1
mulss %xmm1, %xmm0
addss %xmm2, %xmm0
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3670:
.size _Z11RandomFloatff, .-_Z11RandomFloatff
.globl _Z43__device_stub__Z18multiply_on_devicePfS_S_iPfS_S_i
.type _Z43__device_stub__Z18multiply_on_devicePfS_S_iPfS_S_i, @function
_Z43__device_stub__Z18multiply_on_devicePfS_S_iPfS_S_i:
.LFB3696:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L17
.L13:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L18
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L17:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z18multiply_on_devicePfS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L13
.L18:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3696:
.size _Z43__device_stub__Z18multiply_on_devicePfS_S_iPfS_S_i, .-_Z43__device_stub__Z18multiply_on_devicePfS_S_iPfS_S_i
.globl _Z18multiply_on_devicePfS_S_i
.type _Z18multiply_on_devicePfS_S_i, @function
_Z18multiply_on_devicePfS_S_i:
.LFB3697:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z43__device_stub__Z18multiply_on_devicePfS_S_iPfS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _Z18multiply_on_devicePfS_S_i, .-_Z18multiply_on_devicePfS_S_i
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC4:
.string "\n**************************************************\n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC6:
.string "Size of the matrix: "
.LC7:
.string " x "
.LC8:
.string "\n"
.section .rodata.str1.8
.align 8
.LC9:
.string "Time taken by the serial version: "
.section .rodata.str1.1
.LC10:
.string " seconds\n"
.section .rodata.str1.8
.align 8
.LC11:
.string "Time taken by the CUDA version: "
.text
.globl main
.type main, @function
main:
.LFB3671:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $120, %rsp
.cfi_def_cfa_offset 176
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
movl $4194304, %edi
call _Znam@PLT
movq %rax, %r14
movl $4194304, %edi
call _Znam@PLT
movq %rax, %r15
movl $4194304, %edi
call _Znam@PLT
movq %rax, (%rsp)
movl $4194304, %edi
call _Znam@PLT
movq %rax, 8(%rsp)
movq %r14, %r12
leaq 4096(%r14), %rbp
leaq 4198400(%r14), %r13
.L22:
leaq -4096(%rbp), %rbx
.L23:
movss .LC2(%rip), %xmm1
movss .LC3(%rip), %xmm0
call _Z11RandomFloatff
movss %xmm0, (%rbx)
addq $4, %rbx
cmpq %rbp, %rbx
jne .L23
addq $4096, %rbp
cmpq %r13, %rbp
jne .L22
leaq 4194304(%r15), %rcx
movl $0, %esi
.L24:
leaq -4194304(%rcx), %rax
movq %r12, %rdx
.L25:
movss (%rdx), %xmm0
movss %xmm0, (%rax)
addq $4, %rdx
addq $4096, %rax
cmpq %rcx, %rax
jne .L25
addl $1, %esi
addq $4096, %r12
addq $4, %rcx
cmpl $1024, %esi
jne .L24
leaq .LC4(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
leaq 64(%rsp), %rbx
movq %rbx, %rsi
movl $0, %edi
call clock_gettime@PLT
movq (%rsp), %rdx
movq %r15, %rsi
movq %r14, %rdi
call _Z16multiply_on_hostPfS_S_
leaq 80(%rsp), %rsi
movl $0, %edi
call clock_gettime@PLT
pxor %xmm0, %xmm0
cvtsi2sdq 88(%rsp), %xmm0
movsd .LC5(%rip), %xmm2
mulsd %xmm2, %xmm0
pxor %xmm1, %xmm1
cvtsi2sdq 80(%rsp), %xmm1
addsd %xmm0, %xmm1
pxor %xmm0, %xmm0
cvtsi2sdq 72(%rsp), %xmm0
mulsd %xmm2, %xmm0
pxor %xmm2, %xmm2
cvtsi2sdq 64(%rsp), %xmm2
addsd %xmm2, %xmm0
subsd %xmm0, %xmm1
movq %xmm1, %r12
leaq 16(%rsp), %rdi
movl $4194304, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $4194304, %esi
call cudaMalloc@PLT
leaq 32(%rsp), %rdi
movl $4194304, %esi
call cudaMalloc@PLT
movl $32, 40(%rsp)
movl $32, 44(%rsp)
movl $1, 48(%rsp)
movl $32, 52(%rsp)
movl $32, 56(%rsp)
movl $1, 60(%rsp)
movq %rbx, %rsi
movl $0, %edi
call clock_gettime@PLT
movl $1, %ecx
movl $4194304, %edx
movq %r14, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $4194304, %edx
movq %r15, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl 48(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 40(%rsp), %rdx
movq 52(%rsp), %rdi
movl 60(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L33
.L27:
movl $2, %ecx
movl $4194304, %edx
movq 32(%rsp), %rsi
movq 8(%rsp), %r13
movq %r13, %rdi
call cudaMemcpy@PLT
leaq 80(%rsp), %rsi
movl $0, %edi
call clock_gettime@PLT
pxor %xmm0, %xmm0
cvtsi2sdq 88(%rsp), %xmm0
movsd .LC5(%rip), %xmm1
mulsd %xmm1, %xmm0
pxor %xmm2, %xmm2
cvtsi2sdq 80(%rsp), %xmm2
addsd %xmm0, %xmm2
pxor %xmm0, %xmm0
cvtsi2sdq 72(%rsp), %xmm0
mulsd %xmm1, %xmm0
pxor %xmm1, %xmm1
cvtsi2sdq 64(%rsp), %xmm1
addsd %xmm1, %xmm0
subsd %xmm0, %xmm2
movq %xmm2, %rbx
leaq .LC6(%rip), %rsi
leaq _ZSt4cout(%rip), %rbp
movq %rbp, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl $1024, %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
leaq .LC7(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl $1024, %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
leaq .LC8(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
leaq .LC9(%rip), %rsi
movq %rbp, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movq %r12, %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
leaq .LC10(%rip), %r12
movq %r12, %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
leaq .LC11(%rip), %rsi
movq %rbp, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movq %rbx, %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
movq %r12, %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
leaq .LC4(%rip), %rsi
movq %rbp, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %r14, %rdi
call free@PLT
movq %r15, %rdi
call free@PLT
movq (%rsp), %rdi
call free@PLT
movq %r13, %rdi
call free@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L34
movl $0, %eax
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L33:
.cfi_restore_state
movl $1024, %ecx
movq 32(%rsp), %rdx
movq 24(%rsp), %rsi
movq 16(%rsp), %rdi
call _Z43__device_stub__Z18multiply_on_devicePfS_S_iPfS_S_i
jmp .L27
.L34:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3671:
.size main, .-main
.section .rodata.str1.1
.LC12:
.string "_Z18multiply_on_devicePfS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3699:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC12(%rip), %rdx
movq %rdx, %rcx
leaq _Z18multiply_on_devicePfS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3699:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC1:
.long 805306368
.align 4
.LC2:
.long 1073741824
.align 4
.LC3:
.long 1065353216
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC5:
.long -400107883
.long 1041313291
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
```
|
```amdasm
.text
.file "biswas_rajarshi_lab4p1.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z33__device_stub__multiply_on_devicePfS_S_i # -- Begin function _Z33__device_stub__multiply_on_devicePfS_S_i
.type _Z33__device_stub__multiply_on_devicePfS_S_i,@function
_Z33__device_stub__multiply_on_devicePfS_S_i: # @_Z33__device_stub__multiply_on_devicePfS_S_i
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $112, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 40(%rsp), %rax
movq %rdi, (%rax)
leaq 32(%rsp), %rdi
movq %rsi, (%rdi)
leaq 24(%rsp), %rsi
movq %rdx, (%rsi)
leaq 4(%rsp), %rdx
movl %ecx, (%rdx)
leaq 80(%rsp), %rbx
movq %rax, (%rbx)
movq %rdi, 8(%rbx)
movq %rsi, 16(%rbx)
movq %rdx, 24(%rbx)
leaq 64(%rsp), %r14
leaq 48(%rsp), %r15
leaq 16(%rsp), %r12
leaq 8(%rsp), %r13
movq %r14, %rdi
movq %r15, %rsi
movq %r12, %rdx
movq %r13, %rcx
callq __hipPopCallConfiguration
movq (%r14), %rsi
movl 8(%r14), %edx
movq (%r15), %rcx
movl 8(%r15), %r8d
movl $_Z18multiply_on_devicePfS_S_i, %edi
movq %rbx, %r9
pushq (%r13)
.cfi_adjust_cfa_offset 8
pushq (%r12)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $128, %rsp
.cfi_adjust_cfa_offset -128
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z33__device_stub__multiply_on_devicePfS_S_i, .Lfunc_end0-_Z33__device_stub__multiply_on_devicePfS_S_i
.cfi_endproc
# -- End function
.globl _Z16multiply_on_hostPfS_S_ # -- Begin function _Z16multiply_on_hostPfS_S_
.type _Z16multiply_on_hostPfS_S_,@function
_Z16multiply_on_hostPfS_S_: # @_Z16multiply_on_hostPfS_S_
.cfi_startproc
# %bb.0:
xorl %eax, %eax
.LBB1_1: # %.preheader19
# =>This Loop Header: Depth=1
# Child Loop BB1_2 Depth 2
# Child Loop BB1_3 Depth 3
movq %rax, %rcx
shlq $12, %rcx
addq %rdx, %rcx
movq %rsi, %r8
xorl %r9d, %r9d
.LBB1_2: # %.preheader
# Parent Loop BB1_1 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB1_3 Depth 3
xorps %xmm0, %xmm0
movq %r8, %r10
xorl %r11d, %r11d
.LBB1_3: # Parent Loop BB1_1 Depth=1
# Parent Loop BB1_2 Depth=2
# => This Inner Loop Header: Depth=3
movss (%rdi,%r11,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
mulss (%r10), %xmm1
addss %xmm1, %xmm0
incq %r11
addq $4096, %r10 # imm = 0x1000
cmpq $1024, %r11 # imm = 0x400
jne .LBB1_3
# %bb.4: # in Loop: Header=BB1_2 Depth=2
movss %xmm0, (%rcx,%r9,4)
incq %r9
addq $4, %r8
cmpq $1024, %r9 # imm = 0x400
jne .LBB1_2
# %bb.5: # in Loop: Header=BB1_1 Depth=1
incq %rax
addq $4096, %rdi # imm = 0x1000
cmpq $1024, %rax # imm = 0x400
jne .LBB1_1
# %bb.6:
retq
.Lfunc_end1:
.size _Z16multiply_on_hostPfS_S_, .Lfunc_end1-_Z16multiply_on_hostPfS_S_
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function _Z11RandomFloatff
.LCPI2_0:
.long 0x30000000 # float 4.65661287E-10
.text
.globl _Z11RandomFloatff
.type _Z11RandomFloatff,@function
_Z11RandomFloatff: # @_Z11RandomFloatff
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
movss %xmm1, 4(%rsp) # 4-byte Spill
movss %xmm0, (%rsp) # 4-byte Spill
callq rand
xorps %xmm1, %xmm1
cvtsi2ss %eax, %xmm1
mulss .LCPI2_0(%rip), %xmm1
movss 4(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
movss (%rsp), %xmm2 # 4-byte Reload
# xmm2 = mem[0],zero,zero,zero
subss %xmm2, %xmm0
mulss %xmm1, %xmm0
addss %xmm2, %xmm0
popq %rax
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size _Z11RandomFloatff, .Lfunc_end2-_Z11RandomFloatff
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI3_0:
.long 0x30000000 # float 4.65661287E-10
.LCPI3_1:
.long 0x3f800000 # float 1
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0
.LCPI3_2:
.quad 0x3e112e0be826d695 # double 1.0000000000000001E-9
.text
.globl main
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $104, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $4194304, %edi # imm = 0x400000
callq _Znam
movq %rax, %rbp
movl $4194304, %edi # imm = 0x400000
callq _Znam
movq %rax, %r14
movl $4194304, %edi # imm = 0x400000
callq _Znam
movq %rax, %r15
movl $4194304, %edi # imm = 0x400000
callq _Znam
movq %rax, 56(%rsp) # 8-byte Spill
xorl %ebx, %ebx
movq %rbp, %r12
.LBB3_1: # %.preheader51
# =>This Loop Header: Depth=1
# Child Loop BB3_2 Depth 2
xorl %r13d, %r13d
.LBB3_2: # Parent Loop BB3_1 Depth=1
# => This Inner Loop Header: Depth=2
callq rand
movss .LCPI3_0(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
mulss %xmm1, %xmm0
movss .LCPI3_1(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero
addss %xmm1, %xmm0
movss %xmm0, (%r12,%r13,4)
incq %r13
cmpq $1024, %r13 # imm = 0x400
jne .LBB3_2
# %bb.3: # in Loop: Header=BB3_1 Depth=1
incq %rbx
addq $4096, %r12 # imm = 0x1000
cmpq $1024, %rbx # imm = 0x400
jne .LBB3_1
# %bb.4: # %.preheader.preheader
xorl %eax, %eax
movq %r14, %rcx
movq %rbp, %rdx
.LBB3_5: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB3_6 Depth 2
movq %rcx, %rsi
xorl %edi, %edi
.LBB3_6: # Parent Loop BB3_5 Depth=1
# => This Inner Loop Header: Depth=2
movss (%rdx,%rdi,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
movss %xmm0, (%rsi)
incq %rdi
addq $4096, %rsi # imm = 0x1000
cmpq $1024, %rdi # imm = 0x400
jne .LBB3_6
# %bb.7: # in Loop: Header=BB3_5 Depth=1
incq %rax
addq $4096, %rdx # imm = 0x1000
addq $4, %rcx
cmpq $1024, %rax # imm = 0x400
jne .LBB3_5
# %bb.8:
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $52, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
xorl %ebx, %ebx
leaq 72(%rsp), %rsi
xorl %edi, %edi
callq clock_gettime
movq %rbp, 64(%rsp) # 8-byte Spill
.LBB3_9: # %.preheader19.i
# =>This Loop Header: Depth=1
# Child Loop BB3_10 Depth 2
# Child Loop BB3_11 Depth 3
movq %rbx, %rcx
shlq $12, %rcx
addq %r15, %rcx
movq %r14, %rdx
xorl %esi, %esi
.LBB3_10: # %.preheader.i
# Parent Loop BB3_9 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB3_11 Depth 3
xorps %xmm0, %xmm0
movq %rdx, %rdi
xorl %r8d, %r8d
.LBB3_11: # Parent Loop BB3_9 Depth=1
# Parent Loop BB3_10 Depth=2
# => This Inner Loop Header: Depth=3
movss (%rbp,%r8,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
mulss (%rdi), %xmm1
addss %xmm1, %xmm0
incq %r8
addq $4096, %rdi # imm = 0x1000
cmpq $1024, %r8 # imm = 0x400
jne .LBB3_11
# %bb.12: # in Loop: Header=BB3_10 Depth=2
movss %xmm0, (%rcx,%rsi,4)
incq %rsi
addq $4, %rdx
cmpq $1024, %rsi # imm = 0x400
jne .LBB3_10
# %bb.13: # in Loop: Header=BB3_9 Depth=1
incq %rbx
addq $4096, %rbp # imm = 0x1000
cmpq $1024, %rbx # imm = 0x400
jne .LBB3_9
# %bb.14: # %_Z16multiply_on_hostPfS_S_.exit
leaq 88(%rsp), %r13
xorl %edi, %edi
movq %r13, %rsi
callq clock_gettime
movq (%r13), %rax
movq %rax, 8(%rsp) # 8-byte Spill
movq 8(%r13), %rbx
leaq 72(%rsp), %r13
movq (%r13), %rax
movq %rax, 16(%rsp) # 8-byte Spill
movq 8(%r13), %rax
movq %rax, 48(%rsp) # 8-byte Spill
leaq 40(%rsp), %rbp
movl $4194304, %esi # imm = 0x400000
movq %rbp, %rdi
callq hipMalloc
leaq 32(%rsp), %r12
movl $4194304, %esi # imm = 0x400000
movq %r12, %rdi
callq hipMalloc
leaq 24(%rsp), %rdi
movl $4194304, %esi # imm = 0x400000
callq hipMalloc
xorl %edi, %edi
movq %r13, %rsi
callq clock_gettime
movq (%rbp), %rdi
movl $4194304, %edx # imm = 0x400000
movq 64(%rsp), %r13 # 8-byte Reload
movq %r13, %rsi
movl $1, %ecx
callq hipMemcpy
movq (%r12), %rdi
movl $4194304, %edx # imm = 0x400000
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $137438953504, %rdi # imm = 0x2000000020
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_16
# %bb.15:
movq 40(%rsp), %rdi
movq 32(%rsp), %rsi
movq 24(%rsp), %rdx
movl $1024, %ecx # imm = 0x400
callq _Z33__device_stub__multiply_on_devicePfS_S_i
.LBB3_16:
xorps %xmm0, %xmm0
cvtsi2sd %rbx, %xmm0
movsd .LCPI3_2(%rip), %xmm3 # xmm3 = mem[0],zero
mulsd %xmm3, %xmm0
cvtsi2sdq 8(%rsp), %xmm2 # 8-byte Folded Reload
addsd %xmm0, %xmm2
xorps %xmm0, %xmm0
cvtsi2sdq 48(%rsp), %xmm0 # 8-byte Folded Reload
cvtsi2sdq 16(%rsp), %xmm1 # 8-byte Folded Reload
mulsd %xmm3, %xmm0
addsd %xmm0, %xmm1
subsd %xmm1, %xmm2
movsd %xmm2, 16(%rsp) # 8-byte Spill
movq 24(%rsp), %rsi
movl $4194304, %edx # imm = 0x400000
movq 56(%rsp), %rbx # 8-byte Reload
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
leaq 88(%rsp), %r12
xorl %edi, %edi
movq %r12, %rsi
callq clock_gettime
xorps %xmm0, %xmm0
cvtsi2sdq (%r12), %xmm0
xorps %xmm3, %xmm3
cvtsi2sdq 8(%r12), %xmm3
movsd .LCPI3_2(%rip), %xmm4 # xmm4 = mem[0],zero
mulsd %xmm4, %xmm3
xorps %xmm1, %xmm1
cvtsi2sdq 72(%rsp), %xmm1
xorps %xmm2, %xmm2
cvtsi2sdq 80(%rsp), %xmm2
addsd %xmm0, %xmm3
mulsd %xmm4, %xmm2
addsd %xmm1, %xmm2
subsd %xmm2, %xmm3
movsd %xmm3, 8(%rsp) # 8-byte Spill
movl $_ZSt4cout, %edi
movl $.L.str.1, %esi
movl $20, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl $1024, %esi # imm = 0x400
callq _ZNSolsEi
movq %rax, %r12
movl $.L.str.2, %esi
movl $3, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq %r12, %rdi
movl $1024, %esi # imm = 0x400
callq _ZNSolsEi
movl $.L.str.3, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl $.L.str.4, %esi
movl $34, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movsd 16(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
callq _ZNSo9_M_insertIdEERSoT_
movl $.L.str.5, %esi
movl $9, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl $.L.str.6, %esi
movl $32, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movsd 8(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
callq _ZNSo9_M_insertIdEERSoT_
movl $.L.str.5, %esi
movl $9, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $52, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq %r13, %rdi
callq free
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
movq %rbx, %rdi
callq free
movq 40(%rsp), %rdi
callq hipFree
movq 32(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $104, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, %rdi
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z18multiply_on_devicePfS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z18multiply_on_devicePfS_S_i,@object # @_Z18multiply_on_devicePfS_S_i
.section .rodata,"a",@progbits
.globl _Z18multiply_on_devicePfS_S_i
.p2align 3, 0x0
_Z18multiply_on_devicePfS_S_i:
.quad _Z33__device_stub__multiply_on_devicePfS_S_i
.size _Z18multiply_on_devicePfS_S_i, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "\n**************************************************\n"
.size .L.str, 53
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Size of the matrix: "
.size .L.str.1, 21
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz " x "
.size .L.str.2, 4
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "\n"
.size .L.str.3, 2
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Time taken by the serial version: "
.size .L.str.4, 35
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz " seconds\n"
.size .L.str.5, 10
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "Time taken by the CUDA version: "
.size .L.str.6, 33
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z18multiply_on_devicePfS_S_i"
.size .L__unnamed_1, 30
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z33__device_stub__multiply_on_devicePfS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z18multiply_on_devicePfS_S_i
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
```
| 5,905 | 7,894 |
618 |
Convert the following CUDA device assembly code to AMD device assembly:
```cudaasm
code for sm_80
Function : _Z12transposeRowPfS_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ;
S2R R0, SR_CTAID.Y ;
S2R R3, SR_TID.Y ;
S2R R5, SR_CTAID.X ;
S2R R7, SR_TID.X ;
IMAD R0, R0, c[0x0][0x4], R3 ;
IMAD R0, R0, c[0x0][0xc], R5 ;
IMAD R3, R0, c[0x0][0x0], R7 ;
ISETP.GE.U32.AND P0, PT, R3, c[0x0][0x174], PT ;
@P0 EXIT ;
IMAD R5, R3, c[0x0][0x170], RZ ;
IADD3 R0, R5, c[0x0][0x170], RZ ;
ISETP.GE.AND P0, PT, R5, R0, PT ;
@P0 EXIT ;
IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x170] ;
ULDC.64 UR4, c[0x0][0x118] ;
LOP3.LUT P1, R4, R2.reuse, 0x3, RZ, 0xc0, !PT ;
IADD3 R6, R2, -0x1, RZ ;
ISETP.GE.U32.AND P0, PT, R6, 0x3, PT ;
@!P1 BRA 0x240 ;
HFMA2.MMA R10, -RZ, RZ, 0, 2.384185791015625e-07 ;
IMAD.WIDE R6, R5, R10, c[0x0][0x168] ;
IMAD.MOV.U32 R8, RZ, RZ, R6 ;
MOV R11, R7 ;
IMAD.WIDE R6, R3, R10, c[0x0][0x160] ;
IMAD.MOV.U32 R9, RZ, RZ, R11 ;
LDG.E R9, [R8.64] ;
IADD3 R4, R4, -0x1, RZ ;
IADD3 R3, R3, c[0x0][0x170], RZ ;
ISETP.NE.AND P1, PT, R4, RZ, PT ;
IADD3 R5, R5, 0x1, RZ ;
IADD3 R8, P2, R8, 0x4, RZ ;
IADD3.X R11, RZ, R11, RZ, P2, !PT ;
STG.E [R6.64], R9 ;
IMAD.WIDE R6, R2, 0x4, R6 ;
@P1 BRA 0x190 ;
@!P0 EXIT ;
IMAD.MOV.U32 R16, RZ, RZ, 0x4 ;
IMAD.WIDE R6, R5, R16, c[0x0][0x168] ;
IADD3 R4, P0, R6, 0x8, RZ ;
IADD3.X R7, RZ, R7, RZ, P0, !PT ;
IMAD.MOV.U32 R6, RZ, RZ, R4 ;
LDG.E R17, [R6.64+-0x8] ;
IMAD.WIDE R8, R3, R16, c[0x0][0x160] ;
STG.E [R8.64], R17 ;
LDG.E R19, [R6.64+-0x4] ;
IMAD.WIDE R10, R2, 0x4, R8 ;
STG.E [R10.64], R19 ;
LDG.E R21, [R6.64] ;
IMAD.WIDE R12, R2, 0x4, R10 ;
STG.E [R12.64], R21 ;
LDG.E R23, [R6.64+0x4] ;
IMAD.WIDE R14, R2, 0x4, R12 ;
IADD3 R5, R5, 0x4, RZ ;
MOV R4, c[0x0][0x170] ;
ISETP.GE.AND P0, PT, R5, R0, PT ;
MOV R8, c[0x0][0x170] ;
IMAD R3, R4, 0x2, R3 ;
IADD3 R4, P1, R6, 0x10, RZ ;
IMAD R3, R8, 0x2, R3 ;
IADD3.X R7, RZ, R7, RZ, P1, !PT ;
STG.E [R14.64], R23 ;
@!P0 BRA 0x290 ;
EXIT ;
BRA 0x400;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
```
|
```amdasm
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z12transposeRowPfS_ii ; -- Begin function _Z12transposeRowPfS_ii
.globl _Z12transposeRowPfS_ii
.p2align 8
.type _Z12transposeRowPfS_ii,@function
_Z12transposeRowPfS_ii: ; @_Z12transposeRowPfS_ii
; %bb.0:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x24
s_load_b32 s5, s[0:1], 0x18
v_bfe_u32 v1, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_lshr_b32 s2, s4, 16
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, s15, s2, v[1:2]
s_load_b64 s[2:3], s[0:1], 0x10
v_mad_u64_u32 v[3:4], null, v2, s5, s[14:15]
v_and_b32_e32 v2, 0x3ff, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[0:1], null, v3, s4, v[2:3]
s_waitcnt lgkmcnt(0)
v_cmp_gt_u32_e32 vcc_lo, s3, v0
s_and_saveexec_b32 s3, vcc_lo
s_cbranch_execz .LBB0_4
; %bb.1:
v_mul_lo_u32 v2, v0, s2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v1, s2, v2
v_cmp_lt_i32_e32 vcc_lo, v2, v1
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_4
; %bb.2: ; %.lr.ph.preheader
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v3, 31, v2
v_ashrrev_i32_e32 v1, 31, v0
s_ashr_i32 s3, s2, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
s_lshl_b64 s[0:1], s[2:3], 2
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[4:5], 2, v[0:1]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s6, v2
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v3, vcc_lo
v_add_co_u32 v2, vcc_lo, s4, v4
s_delay_alu instid0(VALU_DEP_4)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v5, vcc_lo
.LBB0_3: ; %.lr.ph
; =>This Inner Loop Header: Depth=1
global_load_b32 v4, v[0:1], off
v_add_co_u32 v0, vcc_lo, v0, 4
v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
s_add_i32 s2, s2, -1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_lg_u32 s2, 0
s_waitcnt vmcnt(0)
global_store_b32 v[2:3], v4, off
v_add_co_u32 v2, vcc_lo, v2, s0
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
s_cbranch_scc1 .LBB0_3
.LBB0_4: ; %.loopexit
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z12transposeRowPfS_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z12transposeRowPfS_ii, .Lfunc_end0-_Z12transposeRowPfS_ii
; -- End function
.section .AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 292
; NumSgprs: 18
; NumVgprs: 6
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 6
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object ; @__hip_cuid_
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0 ; 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z12transposeRowPfS_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z12transposeRowPfS_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
```
| 1,301 | 3,122 |
619 |
Convert the following CUDA host assembly code to AMD host assembly:
```cudaasm
.file "tmpxft_00035c76_00000000-6_transposeRow.cudafe1.cpp"
.text
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z36__device_stub__Z12transposeRowPfS_iiPfS_ii
.type _Z36__device_stub__Z12transposeRowPfS_iiPfS_ii, @function
_Z36__device_stub__Z12transposeRowPfS_iiPfS_ii:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z12transposeRowPfS_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z36__device_stub__Z12transposeRowPfS_iiPfS_ii, .-_Z36__device_stub__Z12transposeRowPfS_iiPfS_ii
.globl _Z12transposeRowPfS_ii
.type _Z12transposeRowPfS_ii, @function
_Z12transposeRowPfS_ii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z36__device_stub__Z12transposeRowPfS_iiPfS_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z12transposeRowPfS_ii, .-_Z12transposeRowPfS_ii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z12transposeRowPfS_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z12transposeRowPfS_ii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
```
|
```amdasm
.text
.file "transposeRow.hip"
.globl _Z27__device_stub__transposeRowPfS_ii # -- Begin function _Z27__device_stub__transposeRowPfS_ii
.type _Z27__device_stub__transposeRowPfS_ii,@function
_Z27__device_stub__transposeRowPfS_ii: # @_Z27__device_stub__transposeRowPfS_ii
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $112, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 40(%rsp), %rax
movq %rdi, (%rax)
leaq 32(%rsp), %rdi
movq %rsi, (%rdi)
leaq 12(%rsp), %rsi
movl %edx, (%rsi)
leaq 8(%rsp), %rdx
movl %ecx, (%rdx)
leaq 80(%rsp), %rbx
movq %rax, (%rbx)
movq %rdi, 8(%rbx)
movq %rsi, 16(%rbx)
movq %rdx, 24(%rbx)
leaq 64(%rsp), %r14
leaq 48(%rsp), %r15
leaq 24(%rsp), %r12
leaq 16(%rsp), %r13
movq %r14, %rdi
movq %r15, %rsi
movq %r12, %rdx
movq %r13, %rcx
callq __hipPopCallConfiguration
movq (%r14), %rsi
movl 8(%r14), %edx
movq (%r15), %rcx
movl 8(%r15), %r8d
movl $_Z12transposeRowPfS_ii, %edi
movq %rbx, %r9
pushq (%r13)
.cfi_adjust_cfa_offset 8
pushq (%r12)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $128, %rsp
.cfi_adjust_cfa_offset -128
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z27__device_stub__transposeRowPfS_ii, .Lfunc_end0-_Z27__device_stub__transposeRowPfS_ii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, %rdi
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12transposeRowPfS_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z12transposeRowPfS_ii,@object # @_Z12transposeRowPfS_ii
.section .rodata,"a",@progbits
.globl _Z12transposeRowPfS_ii
.p2align 3, 0x0
_Z12transposeRowPfS_ii:
.quad _Z27__device_stub__transposeRowPfS_ii
.size _Z12transposeRowPfS_ii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z12transposeRowPfS_ii"
.size .L__unnamed_1, 23
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z27__device_stub__transposeRowPfS_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z12transposeRowPfS_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
```
| 1,906 | 2,083 |
620 |
Convert the following CUDA device assembly code to AMD device assembly:
```cudaasm
code for sm_80
Function : _Z7scatterPjS_S_S_S_S_S_S_m
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ;
S2R R0, SR_CTAID.X ;
S2R R3, SR_TID.X ;
IMAD R0, R0, 0x4, R3 ;
ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x1a0], PT ;
SHF.R.S32.HI R3, RZ, 0x1f, R0 ;
ISETP.GE.U32.AND.EX P0, PT, R3, c[0x0][0x1a4], PT, P0 ;
@P0 EXIT ;
IMAD.SHL.U32 R12, R0.reuse, 0x4, RZ ;
SHF.L.U64.HI R0, R0, 0x2, R3 ;
ULDC.64 UR4, c[0x0][0x118] ;
IADD3 R2, P0, R12, c[0x0][0x190], RZ ;
IADD3.X R3, R0, c[0x0][0x194], RZ, P0, !PT ;
LDG.E R2, [R2.64] ;
ISETP.NE.AND P0, PT, R2, RZ, PT ;
@!P0 IMAD.MOV.U32 R11, RZ, RZ, c[0x0][0x1a0] ;
@P0 IADD3 R4, P2, R12.reuse, c[0x0][0x180], RZ ;
@!P0 IMAD.MOV.U32 R6, RZ, RZ, 0x2 ;
@!P0 IADD3 R8, P1, R12, c[0x0][0x188], RZ ;
@!P0 IMAD.SHL.U32 R7, R11.reuse, 0x4, RZ ;
@P0 IADD3.X R5, R0.reuse, c[0x0][0x184], RZ, P2, !PT ;
@!P0 IADD3.X R9, R0, c[0x0][0x18c], RZ, P1, !PT ;
@!P0 SHF.L.U64.HI R11, R11, R6, c[0x0][0x1a4] ;
@P0 LDG.E R10, [R4.64] ;
@!P0 IADD3 R2, P1, R7, c[0x0][0x180], RZ ;
@!P0 IADD3 R6, P2, R7, c[0x0][0x190], RZ ;
@!P0 LDG.E R8, [R8.64] ;
@!P0 IADD3.X R3, R11.reuse, c[0x0][0x184], RZ, P1, !PT ;
@!P0 IADD3.X R7, R11, c[0x0][0x194], RZ, P2, !PT ;
@!P0 LDG.E R3, [R2.64+-0x4] ;
@!P0 LDG.E R6, [R6.64+-0x4] ;
@!P0 IADD3 R10, R8, R6, R3 ;
ISETP.GE.U32.AND P0, PT, R10, c[0x0][0x1a0], PT ;
SHF.R.S32.HI R11, RZ, 0x1f, R10 ;
ISETP.GE.U32.AND.EX P0, PT, R11, c[0x0][0x1a4], PT, P0 ;
@P0 EXIT ;
IADD3 R2, P0, R12, c[0x0][0x160], RZ ;
IADD3.X R3, R0, c[0x0][0x164], RZ, P0, !PT ;
LDG.E R3, [R2.64] ;
IMAD.SHL.U32 R8, R10.reuse, 0x4, RZ ;
SHF.L.U64.HI R10, R10, 0x2, R11 ;
IADD3 R6, P1, R12, c[0x0][0x170], RZ ;
IADD3 R4, P0, R8, c[0x0][0x168], RZ ;
IADD3.X R7, R0, c[0x0][0x174], RZ, P1, !PT ;
IADD3.X R5, R10, c[0x0][0x16c], RZ, P0, !PT ;
STG.E [R4.64], R3 ;
LDG.E R7, [R6.64] ;
IADD3 R8, P0, R8, c[0x0][0x178], RZ ;
IADD3.X R9, R10, c[0x0][0x17c], RZ, P0, !PT ;
STG.E [R8.64], R7 ;
EXIT ;
BRA 0x330;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
Function : _Z12mapPredicatePjS_S_jm
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ;
S2R R0, SR_TID.X ;
S2R R3, SR_CTAID.X ;
IMAD R0, R3, 0x4, R0 ;
ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x180], PT ;
SHF.R.S32.HI R3, RZ, 0x1f, R0 ;
ISETP.GE.U32.AND.EX P0, PT, R3, c[0x0][0x184], PT, P0 ;
@P0 EXIT ;
IMAD.SHL.U32 R6, R0.reuse, 0x4, RZ ;
SHF.L.U64.HI R7, R0, 0x2, R3 ;
ULDC.64 UR4, c[0x0][0x118] ;
IADD3 R2, P0, R6, c[0x0][0x170], RZ ;
IADD3.X R3, R7, c[0x0][0x174], RZ, P0, !PT ;
LDG.E R2, [R2.64] ;
IADD3 R4, P0, R6.reuse, c[0x0][0x168], RZ ;
IADD3 R6, P1, R6, c[0x0][0x160], RZ ;
IADD3.X R5, R7.reuse, c[0x0][0x16c], RZ, P0, !PT ;
IADD3.X R7, R7, c[0x0][0x164], RZ, P1, !PT ;
SHF.R.U32.HI R0, RZ, c[0x0][0x178], R2 ;
LOP3.LUT R9, R0, 0x1, RZ, 0xc0, !PT ;
LOP3.LUT R11, R9, 0x1, RZ, 0x3c, !PT ;
STG.E [R4.64], R9 ;
STG.E [R6.64], R11 ;
EXIT ;
BRA 0x180;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
Function : _Z7mapScanPjS_m
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ;
S2R R0, SR_TID.X ;
S2R R3, SR_CTAID.X ;
IMAD R0, R3, 0x4, R0 ;
ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x170], PT ;
SHF.R.S32.HI R5, RZ, 0x1f, R0 ;
ISETP.GE.U32.AND.EX P0, PT, R5, c[0x0][0x174], PT, P0 ;
@P0 EXIT ;
IMAD.MOV.U32 R2, RZ, RZ, 0x4 ;
LEA R4, P0, R0.reuse, c[0x0][0x160], 0x2 ;
ULDC.64 UR4, c[0x0][0x118] ;
IMAD.WIDE R2, R3, R2, c[0x0][0x168] ;
LEA.HI.X R5, R0, c[0x0][0x164], R5, 0x2, P0 ;
LDG.E R3, [R2.64] ;
LDG.E R0, [R4.64] ;
IMAD.IADD R7, R0, 0x1, R3 ;
STG.E [R4.64], R7 ;
EXIT ;
BRA 0x120;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
Function : _Z11partialScanPjS_S_m
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ;
S2R R8, SR_CTAID.X ;
ULDC.64 UR4, c[0x0][0x118] ;
BSSY B0, 0x110 ;
S2R R13, SR_TID.X ;
IMAD R0, R8, 0x4, R13 ;
ISETP.GT.AND P0, PT, R13, 0x2, PT ;
ISETP.GE.U32.AND P1, PT, R0, c[0x0][0x178], PT ;
SHF.R.S32.HI R3, RZ, 0x1f, R0 ;
ISETP.GE.U32.AND.EX P1, PT, R3, c[0x0][0x17c], PT, P1 ;
@P1 STS [R13.X4], RZ ;
@P1 BRA 0x100 ;
LEA R2, P1, R0, c[0x0][0x160], 0x2 ;
LEA.HI.X R3, R0, c[0x0][0x164], R3, 0x2, P1 ;
LDG.E R2, [R2.64] ;
STS [R13.X4], R2 ;
BSYNC B0 ;
BAR.SYNC.DEFER_BLOCKING 0x0 ;
ISETP.GT.AND P1, PT, R13, 0x1, PT ;
IMAD.MOV.U32 R15, RZ, RZ, 0x4 ;
IADD3 R5, R0, 0x1, RZ ;
SHF.R.S32.HI R10, RZ, 0x1f, R5 ;
@!P0 LDS R2, [R13.X4] ;
@!P0 LDS R3, [R13.X4+0x4] ;
@!P0 IMAD.IADD R2, R2, 0x1, R3 ;
@!P0 STS [R13.X4+0x4], R2 ;
BAR.SYNC.DEFER_BLOCKING 0x0 ;
ISETP.GE.U32.AND P0, PT, R5, c[0x0][0x178], PT ;
ISETP.GE.U32.AND.EX P0, PT, R10, c[0x0][0x17c], PT, P0 ;
IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x168] ;
ISETP.GT.OR P0, PT, R13, 0x2, P0 ;
@!P1 LDS R3, [R13.X4] ;
@!P1 LDS R4, [R13.X4+0x8] ;
@!P1 IMAD.IADD R0, R3, 0x1, R4 ;
IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x16c] ;
@!P1 STS [R13.X4+0x8], R0 ;
BAR.SYNC.DEFER_BLOCKING 0x0 ;
@!P0 LEA R6, P1, R5, c[0x0][0x168], 0x2 ;
@!P0 LEA.HI.X R7, R5, c[0x0][0x16c], R10, 0x2, P1 ;
IMAD.WIDE R4, R8, R15, c[0x0][0x170] ;
@!P0 LDS R9, [R13.X4] ;
LDS R11, [0xc] ;
@!P0 STG.E [R6.64], R9 ;
STG.E [R2.64], RZ ;
STG.E [R4.64], R11 ;
EXIT ;
BRA 0x2e0;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
```
|
```amdasm
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z11partialScanPjS_S_m ; -- Begin function _Z11partialScanPjS_S_m
.globl _Z11partialScanPjS_S_m
.p2align 8
.type _Z11partialScanPjS_S_m,@function
_Z11partialScanPjS_S_m: ; @_Z11partialScanPjS_S_m
; %bb.0:
s_load_b256 s[0:7], s[0:1], 0x0
s_mov_b32 s8, s15
v_mov_b32_e32 v6, 0
v_lshl_add_u32 v3, s8, 2, v0
s_mov_b32 s9, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v4, 31, v3
v_lshlrev_b64 v[1:2], 2, v[3:4]
s_waitcnt lgkmcnt(0)
v_cmpx_gt_u64_e64 s[6:7], v[3:4]
s_cbranch_execz .LBB0_2
; %bb.1:
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v4, vcc_lo, s0, v1
v_add_co_ci_u32_e32 v5, vcc_lo, s1, v2, vcc_lo
global_load_b32 v6, v[4:5], off
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s9
v_lshlrev_b32_e32 v4, 2, v0
v_sub_nc_u32_e32 v5, 4, v0
s_mov_b32 s0, 1
s_waitcnt vmcnt(0)
ds_store_b32 v4, v6
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
.LBB0_3: ; =>This Inner Loop Header: Depth=1
s_mov_b32 s1, exec_lo
v_cmpx_lt_i32_e64 s0, v5
s_cbranch_execz .LBB0_5
; %bb.4: ; in Loop: Header=BB0_3 Depth=1
v_lshl_add_u32 v6, s0, 2, v4
ds_load_b32 v7, v4
ds_load_b32 v8, v6
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v7, v8, v7
ds_store_b32 v6, v7
.LBB0_5: ; in Loop: Header=BB0_3 Depth=1
s_or_b32 exec_lo, exec_lo, s1
s_lshl_b32 s0, s0, 1
s_waitcnt lgkmcnt(0)
s_cmp_gt_i32 s0, 3
s_barrier
buffer_gl0_inv
s_cbranch_scc0 .LBB0_3
; %bb.6:
v_add_nc_u32_e32 v5, 1, v3
v_cmp_gt_u32_e64 s0, 3, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v6, 31, v5
v_cmp_gt_u64_e32 vcc_lo, s[6:7], v[5:6]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s1, s0, vcc_lo
s_and_saveexec_b32 s0, s1
s_cbranch_execz .LBB0_8
; %bb.7:
ds_load_b32 v3, v4
v_add_co_u32 v0, vcc_lo, s2, v1
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v2, vcc_lo
s_waitcnt lgkmcnt(0)
global_store_b32 v[0:1], v3, off offset:4
.LBB0_8:
s_or_b32 exec_lo, exec_lo, s0
v_mov_b32_e32 v0, 0
s_ashr_i32 s9, s8, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_lshl_b64 s[0:1], s[8:9], 2
s_add_u32 s0, s4, s0
ds_load_b32 v1, v0 offset:12
s_addc_u32 s1, s5, s1
global_store_b32 v0, v0, s[2:3]
s_waitcnt lgkmcnt(0)
global_store_b32 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11partialScanPjS_S_m
.amdhsa_group_segment_fixed_size 16
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 32
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z11partialScanPjS_S_m, .Lfunc_end0-_Z11partialScanPjS_S_m
; -- End function
.section .AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 356
; NumSgprs: 18
; NumVgprs: 9
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 16 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 9
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
.text
.protected _Z7mapScanPjS_m ; -- Begin function _Z7mapScanPjS_m
.globl _Z7mapScanPjS_m
.p2align 8
.type _Z7mapScanPjS_m,@function
_Z7mapScanPjS_m: ; @_Z7mapScanPjS_m
; %bb.0:
s_load_b64 s[4:5], s[0:1], 0x10
s_mov_b32 s2, s15
s_mov_b32 s3, exec_lo
v_lshl_add_u32 v0, s2, 2, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v1, 31, v0
s_waitcnt lgkmcnt(0)
v_cmpx_gt_u64_e64 s[4:5], v[0:1]
s_cbranch_execz .LBB1_2
; %bb.1:
s_load_b128 s[4:7], s[0:1], 0x0
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_ashr_i32 s3, s2, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
s_lshl_b64 s[0:1], s[2:3], 2
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
s_add_u32 s0, s6, s0
s_addc_u32 s1, s7, s1
s_load_b32 s0, s[0:1], 0x0
global_load_b32 v2, v[0:1], off
s_waitcnt vmcnt(0) lgkmcnt(0)
v_add_nc_u32_e32 v2, s0, v2
global_store_b32 v[0:1], v2, off
.LBB1_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z7mapScanPjS_m
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z7mapScanPjS_m, .Lfunc_end1-_Z7mapScanPjS_m
; -- End function
.section .AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 148
; NumSgprs: 18
; NumVgprs: 3
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 3
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
.text
.protected _Z12mapPredicatePjS_S_jm ; -- Begin function _Z12mapPredicatePjS_S_jm
.globl _Z12mapPredicatePjS_S_jm
.p2align 8
.type _Z12mapPredicatePjS_S_jm,@function
_Z12mapPredicatePjS_S_jm: ; @_Z12mapPredicatePjS_S_jm
; %bb.0:
s_load_b64 s[2:3], s[0:1], 0x20
v_lshl_add_u32 v0, s15, 2, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v1, 31, v0
s_waitcnt lgkmcnt(0)
v_cmp_gt_u64_e32 vcc_lo, s[2:3], v[0:1]
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB2_2
; %bb.1:
s_load_b64 s[2:3], s[0:1], 0x10
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v1, vcc_lo
global_load_b32 v2, v[2:3], off
s_clause 0x1
s_load_b32 s4, s[0:1], 0x18
s_load_b128 s[0:3], s[0:1], 0x0
s_waitcnt vmcnt(0) lgkmcnt(0)
v_bfe_u32 v4, v2, s4, 1
v_add_co_u32 v2, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_4)
v_xor_b32_e32 v5, 1, v4
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[2:3], v4, off
global_store_b32 v[0:1], v5, off
.LBB2_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z12mapPredicatePjS_S_jm
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 40
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end2:
.size _Z12mapPredicatePjS_S_jm, .Lfunc_end2-_Z12mapPredicatePjS_S_jm
; -- End function
.section .AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 176
; NumSgprs: 18
; NumVgprs: 6
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 6
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
.text
.protected _Z7scatterPjS_S_S_S_S_S_S_m ; -- Begin function _Z7scatterPjS_S_S_S_S_S_S_m
.globl _Z7scatterPjS_S_S_S_S_S_S_m
.p2align 8
.type _Z7scatterPjS_S_S_S_S_S_S_m,@function
_Z7scatterPjS_S_S_S_S_S_S_m: ; @_Z7scatterPjS_S_S_S_S_S_S_m
; %bb.0:
s_load_b64 s[16:17], s[0:1], 0x40
v_lshl_add_u32 v0, s15, 2, v0
s_mov_b32 s2, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v1, 31, v0
s_waitcnt lgkmcnt(0)
v_cmpx_gt_u64_e64 s[16:17], v[0:1]
s_cbranch_execz .LBB3_7
; %bb.1:
s_load_b256 s[8:15], s[0:1], 0x20
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_load_b256 s[0:7], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s12, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s13, v1, vcc_lo
global_load_b32 v2, v[2:3], off
s_waitcnt vmcnt(0)
v_cmp_ne_u32_e32 vcc_lo, 0, v2
; implicit-def: $vgpr2
s_and_saveexec_b32 s14, vcc_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s14, exec_lo, s14
s_cbranch_execz .LBB3_3
; %bb.2:
v_add_co_u32 v2, vcc_lo, s8, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s9, v1, vcc_lo
global_load_b32 v2, v[2:3], off
.LBB3_3: ; %Flow57
s_and_not1_saveexec_b32 s14, s14
s_cbranch_execz .LBB3_5
; %bb.4:
s_waitcnt vmcnt(0)
v_add_co_u32 v2, vcc_lo, s10, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s11, v1, vcc_lo
s_lshl_b64 s[10:11], s[16:17], 2
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s8, s8, s10
global_load_b32 v2, v[2:3], off
s_addc_u32 s9, s9, s11
s_add_u32 s8, s8, -4
s_addc_u32 s9, s9, -1
s_add_u32 s10, s12, s10
s_addc_u32 s11, s13, s11
s_add_u32 s10, s10, -4
s_addc_u32 s11, s11, -1
s_load_b32 s8, s[8:9], 0x0
s_load_b32 s9, s[10:11], 0x0
s_waitcnt vmcnt(0) lgkmcnt(0)
v_add3_u32 v2, s9, s8, v2
.LBB3_5:
s_or_b32 exec_lo, exec_lo, s14
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_cmp_gt_u64_e32 vcc_lo, s[16:17], v[2:3]
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB3_7
; %bb.6:
v_add_co_u32 v4, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s1, v1, vcc_lo
v_lshlrev_b64 v[2:3], 2, v[2:3]
global_load_b32 v6, v[4:5], off
v_add_co_u32 v4, vcc_lo, s2, v2
v_add_co_ci_u32_e32 v5, vcc_lo, s3, v3, vcc_lo
v_add_co_u32 v0, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
s_waitcnt vmcnt(0)
global_store_b32 v[4:5], v6, off
global_load_b32 v4, v[0:1], off
v_add_co_u32 v0, vcc_lo, s6, v2
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v3, vcc_lo
s_waitcnt vmcnt(0)
global_store_b32 v[0:1], v4, off
.LBB3_7:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z7scatterPjS_S_S_S_S_S_S_m
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 72
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 18
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end3:
.size _Z7scatterPjS_S_S_S_S_S_S_m, .Lfunc_end3-_Z7scatterPjS_S_S_S_S_S_S_m
; -- End function
.section .AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 376
; NumSgprs: 20
; NumVgprs: 7
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 20
; NumVGPRsForWavesPerEU: 7
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object ; @__hip_cuid_
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0 ; 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 8
.value_kind: by_value
.group_segment_fixed_size: 16
.kernarg_segment_align: 8
.kernarg_segment_size: 32
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11partialScanPjS_S_m
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z11partialScanPjS_S_m.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 8
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z7mapScanPjS_m
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z7mapScanPjS_m.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 8
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 40
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z12mapPredicatePjS_S_jm
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z12mapPredicatePjS_S_jm.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 40
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 48
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 56
.size: 8
.value_kind: global_buffer
- .offset: 64
.size: 8
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 72
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z7scatterPjS_S_S_S_S_S_S_m
.private_segment_fixed_size: 0
.sgpr_count: 20
.sgpr_spill_count: 0
.symbol: _Z7scatterPjS_S_S_S_S_S_S_m.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
```
| 3,420 | 9,424 |
621 |
Convert the following CUDA host assembly code to AMD host assembly:
```cudaasm
.file "tmpxft_0015f9da_00000000-6_sorter.cudafe1.cpp"
.text
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2064:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2064:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "h_testVals = [ "
.LC1:
.string "%2d "
.LC2:
.string "];\n"
.text
.globl _Z9printTestPjm
.type _Z9printTestPjm, @function
_Z9printTestPjm:
.LFB2057:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $8, %rsp
.cfi_def_cfa_offset 48
movq %rdi, %rbx
movq %rsi, %r12
leaq 0(,%rsi,4), %r13
movq %r13, %rdi
call malloc@PLT
movq %rax, %rbp
movl $2, %ecx
movq %r13, %rdx
movq %rbx, %rsi
movq %rax, %rdi
call cudaMemcpy@PLT
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
testq %r12, %r12
je .L4
movl $0, %ebx
leaq .LC1(%rip), %r13
.L5:
movl 0(%rbp,%rbx,4), %edx
movq %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq %rbx, %r12
jne .L5
.L4:
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %rbp, %rdi
call free@PLT
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size _Z9printTestPjm, .-_Z9printTestPjm
.globl _Z36__device_stub__Z11partialScanPjS_S_mPjS_S_m
.type _Z36__device_stub__Z11partialScanPjS_S_mPjS_S_m, @function
_Z36__device_stub__Z11partialScanPjS_S_mPjS_S_m:
.LFB2086:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %rcx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L12
.L8:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L13
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L12:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z11partialScanPjS_S_m(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L8
.L13:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2086:
.size _Z36__device_stub__Z11partialScanPjS_S_mPjS_S_m, .-_Z36__device_stub__Z11partialScanPjS_S_mPjS_S_m
.globl _Z11partialScanPjS_S_m
.type _Z11partialScanPjS_S_m, @function
_Z11partialScanPjS_S_m:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z36__device_stub__Z11partialScanPjS_S_mPjS_S_m
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _Z11partialScanPjS_S_m, .-_Z11partialScanPjS_S_m
.globl _Z29__device_stub__Z7mapScanPjS_mPjS_m
.type _Z29__device_stub__Z7mapScanPjS_mPjS_m, @function
_Z29__device_stub__Z7mapScanPjS_mPjS_m:
.LFB2088:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L20
.L16:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L21
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L20:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z7mapScanPjS_m(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L16
.L21:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2088:
.size _Z29__device_stub__Z7mapScanPjS_mPjS_m, .-_Z29__device_stub__Z7mapScanPjS_mPjS_m
.globl _Z7mapScanPjS_m
.type _Z7mapScanPjS_m, @function
_Z7mapScanPjS_m:
.LFB2089:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z7mapScanPjS_mPjS_m
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2089:
.size _Z7mapScanPjS_m, .-_Z7mapScanPjS_m
.globl _Z9totalScanPjS_m
.type _Z9totalScanPjS_m, @function
_Z9totalScanPjS_m:
.LFB2058:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $48, %rsp
.cfi_def_cfa_offset 96
movq %rdi, %r13
movq %rsi, %r12
movq %rdx, %rbp
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
leaq -1(%rdx), %rbx
shrq $2, %rbx
addq $1, %rbx
leaq 0(,%rbx,4), %r14
movq %rsp, %rdi
movq %r14, %rsi
call cudaMalloc@PLT
movq %r14, %rdx
movl $0, %esi
movq (%rsp), %rdi
call cudaMemset@PLT
movl $4, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl %ebx, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L30
.L25:
cmpq $1, %rbx
ja .L31
.L26:
movq (%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L32
addq $48, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L30:
.cfi_restore_state
movq %rbp, %rcx
movq (%rsp), %rdx
movq %r12, %rsi
movq %r13, %rdi
call _Z36__device_stub__Z11partialScanPjS_S_mPjS_S_m
jmp .L25
.L31:
leaq 8(%rsp), %rdi
movq %r14, %rsi
call cudaMalloc@PLT
movq %r14, %rdx
movl $0, %esi
movq 8(%rsp), %rdi
call cudaMemset@PLT
movq %rbx, %rdx
movq 8(%rsp), %rsi
movq (%rsp), %rdi
call _Z9totalScanPjS_m
movl $4, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl %ebx, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L33
.L27:
movq 8(%rsp), %rdi
call cudaFree@PLT
jmp .L26
.L33:
movq %rbp, %rdx
movq 8(%rsp), %rsi
movq %r12, %rdi
call _Z29__device_stub__Z7mapScanPjS_mPjS_m
jmp .L27
.L32:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size _Z9totalScanPjS_m, .-_Z9totalScanPjS_m
.globl _Z38__device_stub__Z12mapPredicatePjS_S_jmPjS_S_jm
.type _Z38__device_stub__Z12mapPredicatePjS_S_jmPjS_S_jm, @function
_Z38__device_stub__Z12mapPredicatePjS_S_jmPjS_S_jm:
.LFB2090:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movq %r8, 8(%rsp)
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L38
.L34:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L39
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L38:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 184
pushq 56(%rsp)
.cfi_def_cfa_offset 192
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z12mapPredicatePjS_S_jm(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L34
.L39:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2090:
.size _Z38__device_stub__Z12mapPredicatePjS_S_jmPjS_S_jm, .-_Z38__device_stub__Z12mapPredicatePjS_S_jmPjS_S_jm
.globl _Z12mapPredicatePjS_S_jm
.type _Z12mapPredicatePjS_S_jm, @function
_Z12mapPredicatePjS_S_jm:
.LFB2091:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z38__device_stub__Z12mapPredicatePjS_S_jmPjS_S_jm
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2091:
.size _Z12mapPredicatePjS_S_jm, .-_Z12mapPredicatePjS_S_jm
.globl _Z41__device_stub__Z7scatterPjS_S_S_S_S_S_S_mPjS_S_S_S_S_S_S_m
.type _Z41__device_stub__Z7scatterPjS_S_S_S_S_S_S_mPjS_S_S_S_S_S_S_m, @function
_Z41__device_stub__Z7scatterPjS_S_S_S_S_S_S_mPjS_S_S_S_S_S_S_m:
.LFB2092:
.cfi_startproc
endbr64
subq $216, %rsp
.cfi_def_cfa_offset 224
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
movq %rdx, 40(%rsp)
movq %rcx, 32(%rsp)
movq %r8, 24(%rsp)
movq %r9, 16(%rsp)
movq 224(%rsp), %rax
movq %rax, 8(%rsp)
movq 232(%rsp), %rax
movq %rax, (%rsp)
movq %fs:40, %rax
movq %rax, 200(%rsp)
xorl %eax, %eax
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 40(%rsp), %rax
movq %rax, 144(%rsp)
leaq 32(%rsp), %rax
movq %rax, 152(%rsp)
leaq 24(%rsp), %rax
movq %rax, 160(%rsp)
leaq 16(%rsp), %rax
movq %rax, 168(%rsp)
leaq 8(%rsp), %rax
movq %rax, 176(%rsp)
movq %rsp, %rax
movq %rax, 184(%rsp)
leaq 240(%rsp), %rax
movq %rax, 192(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
leaq 72(%rsp), %rcx
leaq 64(%rsp), %rdx
leaq 92(%rsp), %rsi
leaq 80(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L46
.L42:
movq 200(%rsp), %rax
subq %fs:40, %rax
jne .L47
addq $216, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L46:
.cfi_restore_state
pushq 72(%rsp)
.cfi_def_cfa_offset 232
pushq 72(%rsp)
.cfi_def_cfa_offset 240
leaq 144(%rsp), %r9
movq 108(%rsp), %rcx
movl 116(%rsp), %r8d
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
leaq _Z7scatterPjS_S_S_S_S_S_S_m(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 224
jmp .L42
.L47:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2092:
.size _Z41__device_stub__Z7scatterPjS_S_S_S_S_S_S_mPjS_S_S_S_S_S_S_m, .-_Z41__device_stub__Z7scatterPjS_S_S_S_S_S_S_mPjS_S_S_S_S_S_S_m
.globl _Z7scatterPjS_S_S_S_S_S_S_m
.type _Z7scatterPjS_S_S_S_S_S_S_m, @function
_Z7scatterPjS_S_S_S_S_S_S_m:
.LFB2093:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
pushq 40(%rsp)
.cfi_def_cfa_offset 32
pushq 40(%rsp)
.cfi_def_cfa_offset 40
pushq 40(%rsp)
.cfi_def_cfa_offset 48
call _Z41__device_stub__Z7scatterPjS_S_S_S_S_S_S_mPjS_S_S_S_S_S_S_m
addq $40, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2093:
.size _Z7scatterPjS_S_S_S_S_S_S_m, .-_Z7scatterPjS_S_S_S_S_S_S_m
.globl _Z5radixPjS_S_S_m
.type _Z5radixPjS_S_S_m, @function
_Z5radixPjS_S_S_m:
.LFB2059:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $104, %rsp
.cfi_def_cfa_offset 160
movq %rdi, %r15
movq %rsi, 8(%rsp)
movq %rdx, %r14
movq %rcx, %r13
movq %r8, %rbp
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 0(,%r8,4), %rbx
leaq -1(%r8), %r12
shrq $2, %r12
addq $1, %r12
leaq 16(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq 32(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq 40(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq 48(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq 56(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl $3, %ecx
movq %rbx, %rdx
movq %r15, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $3, %ecx
movq %rbx, %rdx
movq 8(%rsp), %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl $0, %r15d
jmp .L53
.L58:
movq %rbp, %r8
movl %r15d, %ecx
movq 16(%rsp), %rdx
movq 40(%rsp), %rsi
movq 32(%rsp), %rdi
call _Z38__device_stub__Z12mapPredicatePjS_S_jmPjS_S_jm
jmp .L51
.L52:
movl $3, %ecx
movq %rbx, %rdx
movq %r14, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $3, %ecx
movq %rbx, %rdx
movq %r13, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
addl $1, %r15d
cmpl $32, %r15d
je .L57
.L53:
movq %rbx, %rdx
movl $0, %esi
movq 48(%rsp), %rdi
call cudaMemset@PLT
movq %rbx, %rdx
movl $0, %esi
movq 56(%rsp), %rdi
call cudaMemset@PLT
movl $4, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl %r12d, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 76(%rsp), %rdx
movl $1, %ecx
movq 64(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L58
.L51:
movq %rbp, %rdx
movq 48(%rsp), %rsi
movq 32(%rsp), %rdi
call _Z9totalScanPjS_m
movq %rbp, %rdx
movq 56(%rsp), %rsi
movq 40(%rsp), %rdi
call _Z9totalScanPjS_m
movl $4, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl %r12d, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 76(%rsp), %rdx
movl $1, %ecx
movq 64(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L52
subq $8, %rsp
.cfi_def_cfa_offset 168
pushq %rbp
.cfi_def_cfa_offset 176
pushq 56(%rsp)
.cfi_def_cfa_offset 184
pushq 56(%rsp)
.cfi_def_cfa_offset 192
movq 88(%rsp), %r9
movq 80(%rsp), %r8
movq %r13, %rcx
movq 56(%rsp), %rdx
movq %r14, %rsi
movq 48(%rsp), %rdi
call _Z41__device_stub__Z7scatterPjS_S_S_S_S_S_S_mPjS_S_S_S_S_S_S_m
addq $32, %rsp
.cfi_def_cfa_offset 160
jmp .L52
.L57:
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
movq 48(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rdi
call cudaFree@PLT
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L59
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L59:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size _Z5radixPjS_S_S_m, .-_Z5radixPjS_S_S_m
.globl _Z9radixHostPjS_S_S_m
.type _Z9radixHostPjS_S_S_m, @function
_Z9radixHostPjS_S_S_m:
.LFB2060:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $56, %rsp
.cfi_def_cfa_offset 112
movq %rdi, %r15
movq %rsi, %r14
movq %rdx, %r13
movq %rcx, %r12
movq %r8, %rbp
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
leaq 0(,%r8,4), %rbx
leaq 8(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq 32(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %rbx, %rdx
movq %r15, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %rbx, %rdx
movq %r14, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movq %rbp, %r8
movq 32(%rsp), %rcx
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z5radixPjS_S_S_m
movl $2, %ecx
movq %rbx, %rdx
movq 24(%rsp), %rsi
movq %r13, %rdi
call cudaMemcpy@PLT
movl $2, %ecx
movq %rbx, %rdx
movq 32(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L63
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L63:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2060:
.size _Z9radixHostPjS_S_S_m, .-_Z9radixHostPjS_S_S_m
.section .rodata.str1.1
.LC3:
.string "h_inVals = [ "
.LC4:
.string "];\nh_inPos = [ "
.LC5:
.string "h_outVals = [ "
.LC6:
.string "];\nh_outPos = [ "
.text
.globl main
.type main, @function
main:
.LFB2061:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $24, %rsp
.cfi_def_cfa_offset 80
movl $0, %edi
call srand@PLT
movl $140, %edi
call malloc@PLT
movq %rax, %r12
movl $140, %edi
call malloc@PLT
movq %rax, %rbp
movl $140, %edi
call malloc@PLT
movq %rax, %r13
movl $140, %edi
call malloc@PLT
movq %rax, 8(%rsp)
movl $1, %eax
.L65:
movl %eax, -4(%r12,%rax,4)
addq $1, %rax
cmpq $36, %rax
jne .L65
movl $0, %eax
.L66:
movl %eax, 0(%rbp,%rax,4)
addq $1, %rax
cmpq $35, %rax
jne .L66
movl $35, %r8d
movq 8(%rsp), %rcx
movq %r13, %rdx
movq %rbp, %rsi
movq %r12, %rdi
call _Z9radixHostPjS_S_S_m
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %r12, %rbx
leaq 140(%r12), %r15
leaq .LC1(%rip), %r14
.L67:
movl (%rbx), %edx
movq %r14, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %r15, %rbx
jne .L67
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %rbp, %rbx
leaq 140(%rbp), %r15
leaq .LC1(%rip), %r14
.L68:
movl (%rbx), %edx
movq %r14, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %r15, %rbx
jne .L68
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %r13, %rbx
leaq 140(%r13), %r15
leaq .LC1(%rip), %r14
.L69:
movl (%rbx), %edx
movq %r14, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %rbx, %r15
jne .L69
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 8(%rsp), %rax
movq %rax, %rbx
leaq 140(%rax), %r15
leaq .LC1(%rip), %r14
.L70:
movl (%rbx), %edx
movq %r14, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %r15, %rbx
jne .L70
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %r12, %rdi
call free@PLT
movq %rbp, %rdi
call free@PLT
movq %r13, %rdi
call free@PLT
movq 8(%rsp), %rdi
call free@PLT
movl $0, %eax
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size main, .-main
.section .rodata.str1.1
.LC7:
.string "_Z7scatterPjS_S_S_S_S_S_S_m"
.LC8:
.string "_Z12mapPredicatePjS_S_jm"
.LC9:
.string "_Z7mapScanPjS_m"
.LC10:
.string "_Z11partialScanPjS_S_m"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2095:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _Z7scatterPjS_S_S_S_S_S_S_m(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _Z12mapPredicatePjS_S_jm(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC9(%rip), %rdx
movq %rdx, %rcx
leaq _Z7mapScanPjS_m(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC10(%rip), %rdx
movq %rdx, %rcx
leaq _Z11partialScanPjS_S_m(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2095:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
```
|
```amdasm
.text
.file "sorter.hip"
.globl _Z9printTestPjm # -- Begin function _Z9printTestPjm
.type _Z9printTestPjm,@function
_Z9printTestPjm: # @_Z9printTestPjm
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
pushq %rax
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rsi, %rbx
movq %rdi, %r15
leaq (,%rsi,4), %r12
movq %r12, %rdi
callq malloc
movq %rax, %r14
movq %rax, %rdi
movq %r15, %rsi
movq %r12, %rdx
movl $2, %ecx
callq hipMemcpy
movl $.L.str, %edi
xorl %eax, %eax
callq printf
testq %rbx, %rbx
je .LBB0_3
# %bb.1: # %.lr.ph.preheader
xorl %r15d, %r15d
.LBB0_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl (%r14,%r15,4), %esi
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
incq %r15
cmpq %r15, %rbx
jne .LBB0_2
.LBB0_3: # %._crit_edge
movl $.Lstr.2, %edi
callq puts@PLT
movq %r14, %rdi
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
jmp free # TAILCALL
.Lfunc_end0:
.size _Z9printTestPjm, .Lfunc_end0-_Z9printTestPjm
.cfi_endproc
# -- End function
.globl _Z26__device_stub__partialScanPjS_S_m # -- Begin function _Z26__device_stub__partialScanPjS_S_m
.type _Z26__device_stub__partialScanPjS_S_m,@function
_Z26__device_stub__partialScanPjS_S_m: # @_Z26__device_stub__partialScanPjS_S_m
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $112, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 40(%rsp), %rax
movq %rdi, (%rax)
leaq 32(%rsp), %rdi
movq %rsi, (%rdi)
leaq 24(%rsp), %rsi
movq %rdx, (%rsi)
leaq 16(%rsp), %rdx
movq %rcx, (%rdx)
leaq 80(%rsp), %rbx
movq %rax, (%rbx)
movq %rdi, 8(%rbx)
movq %rsi, 16(%rbx)
movq %rdx, 24(%rbx)
leaq 64(%rsp), %r14
leaq 48(%rsp), %r15
leaq 8(%rsp), %r12
movq %rsp, %r13
movq %r14, %rdi
movq %r15, %rsi
movq %r12, %rdx
movq %r13, %rcx
callq __hipPopCallConfiguration
movq (%r14), %rsi
movl 8(%r14), %edx
movq (%r15), %rcx
movl 8(%r15), %r8d
movl $_Z11partialScanPjS_S_m, %edi
movq %rbx, %r9
pushq (%r13)
.cfi_adjust_cfa_offset 8
pushq (%r12)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $128, %rsp
.cfi_adjust_cfa_offset -128
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z26__device_stub__partialScanPjS_S_m, .Lfunc_end1-_Z26__device_stub__partialScanPjS_S_m
.cfi_endproc
# -- End function
.globl _Z22__device_stub__mapScanPjS_m # -- Begin function _Z22__device_stub__mapScanPjS_m
.type _Z22__device_stub__mapScanPjS_m,@function
_Z22__device_stub__mapScanPjS_m: # @_Z22__device_stub__mapScanPjS_m
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $112, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 40(%rsp), %rax
movq %rdi, (%rax)
leaq 32(%rsp), %rcx
movq %rsi, (%rcx)
leaq 24(%rsp), %rsi
movq %rdx, (%rsi)
leaq 80(%rsp), %rbx
movq %rax, (%rbx)
movq %rcx, 8(%rbx)
movq %rsi, 16(%rbx)
leaq 64(%rsp), %r14
leaq 48(%rsp), %r15
leaq 16(%rsp), %r12
leaq 8(%rsp), %r13
movq %r14, %rdi
movq %r15, %rsi
movq %r12, %rdx
movq %r13, %rcx
callq __hipPopCallConfiguration
movq (%r14), %rsi
movl 8(%r14), %edx
movq (%r15), %rcx
movl 8(%r15), %r8d
movl $_Z7mapScanPjS_m, %edi
movq %rbx, %r9
pushq (%r13)
.cfi_adjust_cfa_offset 8
pushq (%r12)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $128, %rsp
.cfi_adjust_cfa_offset -128
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size _Z22__device_stub__mapScanPjS_m, .Lfunc_end2-_Z22__device_stub__mapScanPjS_m
.cfi_endproc
# -- End function
.globl _Z27__device_stub__mapPredicatePjS_S_jm # -- Begin function _Z27__device_stub__mapPredicatePjS_S_jm
.type _Z27__device_stub__mapPredicatePjS_S_jm,@function
_Z27__device_stub__mapPredicatePjS_S_jm: # @_Z27__device_stub__mapPredicatePjS_S_jm
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $144, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 56(%rsp), %rax
movq %rdi, (%rax)
leaq 48(%rsp), %rdi
movq %rsi, (%rdi)
leaq 40(%rsp), %rsi
movq %rdx, (%rsi)
leaq 12(%rsp), %rdx
movl %ecx, (%rdx)
leaq 32(%rsp), %rcx
movq %r8, (%rcx)
leaq 96(%rsp), %rbx
movq %rax, (%rbx)
movq %rdi, 8(%rbx)
movq %rsi, 16(%rbx)
movq %rdx, 24(%rbx)
movq %rcx, 32(%rbx)
leaq 80(%rsp), %r14
leaq 64(%rsp), %r15
leaq 24(%rsp), %r12
leaq 16(%rsp), %r13
movq %r14, %rdi
movq %r15, %rsi
movq %r12, %rdx
movq %r13, %rcx
callq __hipPopCallConfiguration
movq (%r14), %rsi
movl 8(%r14), %edx
movq (%r15), %rcx
movl 8(%r15), %r8d
movl $_Z12mapPredicatePjS_S_jm, %edi
movq %rbx, %r9
pushq (%r13)
.cfi_adjust_cfa_offset 8
pushq (%r12)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $160, %rsp
.cfi_adjust_cfa_offset -160
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size _Z27__device_stub__mapPredicatePjS_S_jm, .Lfunc_end3-_Z27__device_stub__mapPredicatePjS_S_jm
.cfi_endproc
# -- End function
.globl _Z22__device_stub__scatterPjS_S_S_S_S_S_S_m # -- Begin function _Z22__device_stub__scatterPjS_S_S_S_S_S_S_m
.type _Z22__device_stub__scatterPjS_S_S_S_S_S_S_m,@function
_Z22__device_stub__scatterPjS_S_S_S_S_S_S_m: # @_Z22__device_stub__scatterPjS_S_S_S_S_S_S_m
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $176, %rsp
.cfi_def_cfa_offset 224
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 56(%rsp), %rax
movq %rdi, (%rax)
leaq 48(%rsp), %rdi
movq %rsi, (%rdi)
leaq 40(%rsp), %rsi
movq %rdx, (%rsi)
leaq 32(%rsp), %rdx
movq %rcx, (%rdx)
leaq 24(%rsp), %rcx
movq %r8, (%rcx)
leaq 16(%rsp), %r8
movq %r9, (%r8)
leaq 96(%rsp), %rbx
movq %rax, (%rbx)
movq %rdi, 8(%rbx)
movq %rsi, 16(%rbx)
movq %rdx, 24(%rbx)
movq %rcx, 32(%rbx)
movq %r8, 40(%rbx)
leaq 224(%rsp), %rax
movq %rax, 48(%rbx)
leaq 232(%rsp), %rax
movq %rax, 56(%rbx)
leaq 240(%rsp), %rax
movq %rax, 64(%rbx)
leaq 80(%rsp), %r14
leaq 64(%rsp), %r15
leaq 8(%rsp), %r12
movq %rsp, %r13
movq %r14, %rdi
movq %r15, %rsi
movq %r12, %rdx
movq %r13, %rcx
callq __hipPopCallConfiguration
movq (%r14), %rsi
movl 8(%r14), %edx
movq (%r15), %rcx
movl 8(%r15), %r8d
movl $_Z7scatterPjS_S_S_S_S_S_S_m, %edi
movq %rbx, %r9
pushq (%r13)
.cfi_adjust_cfa_offset 8
pushq (%r12)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $192, %rsp
.cfi_adjust_cfa_offset -192
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end4:
.size _Z22__device_stub__scatterPjS_S_S_S_S_S_S_m, .Lfunc_end4-_Z22__device_stub__scatterPjS_S_S_S_S_S_S_m
.cfi_endproc
# -- End function
.globl _Z9totalScanPjS_m # -- Begin function _Z9totalScanPjS_m
.type _Z9totalScanPjS_m,@function
_Z9totalScanPjS_m: # @_Z9totalScanPjS_m
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $40, %rsp
.cfi_def_cfa_offset 96
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rdx, %rbx
movq %rsi, 16(%rsp) # 8-byte Spill
movq %rdi, 32(%rsp) # 8-byte Spill
movabsq $4294967300, %r14 # imm = 0x100000004
leaq -1(%rdx), %r15
movq %r15, %r12
shrq $2, %r12
leaq 4(,%r12,4), %r13
incq %r12
leaq 8(%rsp), %rbp
movq %rbp, %rdi
movq %r13, %rsi
callq hipMalloc
movq (%rbp), %rdi
xorl %esi, %esi
movq %r13, %rdx
callq hipMemset
movl %r12d, %eax
leaq (%rax,%r14), %rbp
addq $-4, %rbp
movq %rbp, %rdi
movl $1, %esi
movq %r14, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB5_2
# %bb.1:
movq 8(%rsp), %rdx
movq 32(%rsp), %rdi # 8-byte Reload
movq 16(%rsp), %rsi # 8-byte Reload
movq %rbx, %rcx
callq _Z26__device_stub__partialScanPjS_S_m
.LBB5_2:
cmpq $4, %r15
jb .LBB5_6
# %bb.3:
leaq 24(%rsp), %r14
movq %r14, %rdi
movq %r13, %rsi
callq hipMalloc
movq (%r14), %rdi
xorl %esi, %esi
movq %r13, %rdx
callq hipMemset
movq 8(%rsp), %rdi
movq (%r14), %rsi
movq %r12, %rdx
callq _Z9totalScanPjS_m
movq %rbp, %rdi
movl $1, %esi
movabsq $4294967300, %rdx # imm = 0x100000004
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB5_5
# %bb.4:
movq 24(%rsp), %rsi
movq 16(%rsp), %rdi # 8-byte Reload
movq %rbx, %rdx
callq _Z22__device_stub__mapScanPjS_m
.LBB5_5:
movq 24(%rsp), %rdi
callq hipFree
.LBB5_6:
movq 8(%rsp), %rdi
callq hipFree
addq $40, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end5:
.size _Z9totalScanPjS_m, .Lfunc_end5-_Z9totalScanPjS_m
.cfi_endproc
# -- End function
.globl _Z5radixPjS_S_S_m # -- Begin function _Z5radixPjS_S_S_m
.type _Z5radixPjS_S_S_m,@function
_Z5radixPjS_S_S_m: # @_Z5radixPjS_S_S_m
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $72, %rsp
.cfi_def_cfa_offset 128
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %r8, %rbx
movq %rcx, 56(%rsp) # 8-byte Spill
movq %rdx, %r15
movq %rsi, 64(%rsp) # 8-byte Spill
movq %rdi, %rbp
movabsq $4294967300, %r14 # imm = 0x100000004
leaq (,%r8,4), %r13
leaq -1(%r8), %r12
shrq $2, %r12
leaq 8(%rsp), %rdi
movq %r13, %rsi
callq hipMalloc
leaq 48(%rsp), %rdi
movq %r13, %rsi
callq hipMalloc
leaq 40(%rsp), %rdi
movq %r13, %rsi
callq hipMalloc
leaq 32(%rsp), %rdi
movq %r13, %rsi
callq hipMalloc
leaq 24(%rsp), %rdi
movq %r13, %rsi
callq hipMalloc
leaq 16(%rsp), %rdi
movq %r13, %rsi
callq hipMalloc
leaq 8(%rsp), %rax
movq (%rax), %rdi
movq %rbp, %rsi
movq %r13, %rdx
movl $3, %ecx
callq hipMemcpy
leaq 48(%rsp), %rax
movq (%rax), %rdi
movq 64(%rsp), %rsi # 8-byte Reload
movq %r13, %rdx
movl $3, %ecx
callq hipMemcpy
incl %r12d
leaq (%r12,%r14), %rbp
addq $-4, %rbp
xorl %r12d, %r12d
movabsq $4294967300, %r14 # imm = 0x100000004
.LBB6_1: # =>This Inner Loop Header: Depth=1
movq 24(%rsp), %rdi
xorl %esi, %esi
movq %r13, %rdx
callq hipMemset
movq 16(%rsp), %rdi
xorl %esi, %esi
movq %r13, %rdx
callq hipMemset
movq %rbp, %rdi
movl $1, %esi
movq %r14, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB6_3
# %bb.2: # in Loop: Header=BB6_1 Depth=1
movq 40(%rsp), %rdi
movq 32(%rsp), %rsi
movq 8(%rsp), %rdx
movl %r12d, %ecx
movq %rbx, %r8
callq _Z27__device_stub__mapPredicatePjS_S_jm
.LBB6_3: # in Loop: Header=BB6_1 Depth=1
movq 40(%rsp), %rdi
movq 24(%rsp), %rsi
movq %rbx, %rdx
callq _Z9totalScanPjS_m
movq 32(%rsp), %rdi
movq 16(%rsp), %rsi
movq %rbx, %rdx
callq _Z9totalScanPjS_m
movq %rbp, %rdi
movl $1, %esi
movq %r14, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB6_5
# %bb.4: # in Loop: Header=BB6_1 Depth=1
movq 8(%rsp), %rdi
movq 48(%rsp), %rdx
movq 24(%rsp), %r8
movq 16(%rsp), %r9
subq $8, %rsp
.cfi_adjust_cfa_offset 8
movq %r15, %rsi
movq 64(%rsp), %rcx # 8-byte Reload
pushq %rbx
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
callq _Z22__device_stub__scatterPjS_S_S_S_S_S_S_m
addq $32, %rsp
.cfi_adjust_cfa_offset -32
.LBB6_5: # in Loop: Header=BB6_1 Depth=1
movq 8(%rsp), %rdi
movq %r15, %rsi
movq %r13, %rdx
movl $3, %ecx
callq hipMemcpy
movq 48(%rsp), %rdi
movq 56(%rsp), %rsi # 8-byte Reload
movq %r13, %rdx
movl $3, %ecx
callq hipMemcpy
incl %r12d
cmpl $32, %r12d
jne .LBB6_1
# %bb.6:
movq 8(%rsp), %rdi
callq hipFree
movq 48(%rsp), %rdi
callq hipFree
movq 40(%rsp), %rdi
callq hipFree
movq 32(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
addq $72, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end6:
.size _Z5radixPjS_S_S_m, .Lfunc_end6-_Z5radixPjS_S_S_m
.cfi_endproc
# -- End function
.globl _Z9radixHostPjS_S_S_m # -- Begin function _Z9radixHostPjS_S_S_m
.type _Z9radixHostPjS_S_S_m,@function
_Z9radixHostPjS_S_S_m: # @_Z9radixHostPjS_S_S_m
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $56, %rsp
.cfi_def_cfa_offset 112
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %r8, %rbx
movq %rcx, 24(%rsp) # 8-byte Spill
movq %rdx, 16(%rsp) # 8-byte Spill
movq %rsi, %r14
movq %rdi, %r15
leaq (,%r8,4), %r12
leaq 48(%rsp), %r13
movq %r13, %rdi
movq %r12, %rsi
callq hipMalloc
leaq 40(%rsp), %rbp
movq %rbp, %rdi
movq %r12, %rsi
callq hipMalloc
leaq 8(%rsp), %rdi
movq %r12, %rsi
callq hipMalloc
leaq 32(%rsp), %rdi
movq %r12, %rsi
callq hipMalloc
movq (%r13), %rdi
movq %r15, %rsi
movq %r12, %rdx
movl $1, %ecx
callq hipMemcpy
movq (%rbp), %rdi
movq %r14, %rsi
movq %r12, %rdx
movl $1, %ecx
callq hipMemcpy
movq (%r13), %rdi
movq (%rbp), %rsi
leaq 8(%rsp), %rax
movq (%rax), %rdx
leaq 32(%rsp), %r14
movq (%r14), %rcx
movq %rbx, %r8
callq _Z5radixPjS_S_S_m
leaq 8(%rsp), %rax
movq (%rax), %rsi
movq %rax, %rbx
movq 16(%rsp), %rdi # 8-byte Reload
movq %r12, %rdx
movl $2, %ecx
callq hipMemcpy
movq (%r14), %rsi
movq 24(%rsp), %rdi # 8-byte Reload
movq %r12, %rdx
movl $2, %ecx
callq hipMemcpy
movq (%r13), %rdi
callq hipFree
movq (%rbp), %rdi
callq hipFree
movq (%rbx), %rdi
callq hipFree
movq (%r14), %rdi
callq hipFree
addq $56, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end7:
.size _Z9radixHostPjS_S_S_m, .Lfunc_end7-_Z9radixHostPjS_S_S_m
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
xorl %r13d, %r13d
xorl %edi, %edi
callq srand
movl $140, %edi
callq malloc
movq %rax, %rbx
movl $140, %edi
callq malloc
movq %rax, %r14
movl $140, %edi
callq malloc
movq %rax, %r15
movl $140, %edi
callq malloc
movq %rax, %r12
.LBB8_1: # =>This Inner Loop Header: Depth=1
leaq 1(%r13), %rax
movl %eax, (%rbx,%r13,4)
movq %rax, %r13
cmpq $35, %rax
jne .LBB8_1
# %bb.2: # %.preheader.preheader
xorl %eax, %eax
.LBB8_3: # %.preheader
# =>This Inner Loop Header: Depth=1
movl %eax, (%r14,%rax,4)
incq %rax
cmpq $35, %rax
jne .LBB8_3
# %bb.4:
movl $35, %r8d
movq %rbx, %rdi
movq %r14, %rsi
movq %r15, %rdx
movq %r12, %rcx
callq _Z9radixHostPjS_S_S_m
movl $.L.str.3, %edi
xorl %eax, %eax
callq printf
xorl %r13d, %r13d
.LBB8_5: # =>This Inner Loop Header: Depth=1
movl (%rbx,%r13,4), %esi
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
incq %r13
cmpq $35, %r13
jne .LBB8_5
# %bb.6:
movl $.L.str.4, %edi
xorl %eax, %eax
callq printf
xorl %r13d, %r13d
.LBB8_7: # =>This Inner Loop Header: Depth=1
movl (%r14,%r13,4), %esi
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
incq %r13
cmpq $35, %r13
jne .LBB8_7
# %bb.8:
movl $.Lstr.2, %edi
callq puts@PLT
movl $.L.str.5, %edi
xorl %eax, %eax
callq printf
xorl %r13d, %r13d
.LBB8_9: # =>This Inner Loop Header: Depth=1
movl (%r15,%r13,4), %esi
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
incq %r13
cmpq $35, %r13
jne .LBB8_9
# %bb.10:
movl $.L.str.6, %edi
xorl %eax, %eax
callq printf
xorl %r13d, %r13d
.LBB8_11: # =>This Inner Loop Header: Depth=1
movl (%r12,%r13,4), %esi
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
incq %r13
cmpq $35, %r13
jne .LBB8_11
# %bb.12:
movl $.Lstr.2, %edi
callq puts@PLT
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
movq %r12, %rdi
callq free
xorl %eax, %eax
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end8:
.size main, .Lfunc_end8-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
movq __hip_gpubin_handle(%rip), %rbx
testq %rbx, %rbx
jne .LBB9_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, %rbx
movq %rax, __hip_gpubin_handle(%rip)
.LBB9_2:
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11partialScanPjS_S_m, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7mapScanPjS_m, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12mapPredicatePjS_S_jm, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7scatterPjS_S_S_S_S_S_S_m, %esi
movl $.L__unnamed_4, %edx
movl $.L__unnamed_4, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end9:
.size __hip_module_ctor, .Lfunc_end9-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB10_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB10_2:
retq
.Lfunc_end10:
.size __hip_module_dtor, .Lfunc_end10-__hip_module_dtor
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "h_testVals = [ "
.size .L.str, 16
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "%2d "
.size .L.str.1, 5
.type _Z11partialScanPjS_S_m,@object # @_Z11partialScanPjS_S_m
.section .rodata,"a",@progbits
.globl _Z11partialScanPjS_S_m
.p2align 3, 0x0
_Z11partialScanPjS_S_m:
.quad _Z26__device_stub__partialScanPjS_S_m
.size _Z11partialScanPjS_S_m, 8
.type _Z7mapScanPjS_m,@object # @_Z7mapScanPjS_m
.globl _Z7mapScanPjS_m
.p2align 3, 0x0
_Z7mapScanPjS_m:
.quad _Z22__device_stub__mapScanPjS_m
.size _Z7mapScanPjS_m, 8
.type _Z12mapPredicatePjS_S_jm,@object # @_Z12mapPredicatePjS_S_jm
.globl _Z12mapPredicatePjS_S_jm
.p2align 3, 0x0
_Z12mapPredicatePjS_S_jm:
.quad _Z27__device_stub__mapPredicatePjS_S_jm
.size _Z12mapPredicatePjS_S_jm, 8
.type _Z7scatterPjS_S_S_S_S_S_S_m,@object # @_Z7scatterPjS_S_S_S_S_S_S_m
.globl _Z7scatterPjS_S_S_S_S_S_S_m
.p2align 3, 0x0
_Z7scatterPjS_S_S_S_S_S_S_m:
.quad _Z22__device_stub__scatterPjS_S_S_S_S_S_S_m
.size _Z7scatterPjS_S_S_S_S_S_S_m, 8
.type .L.str.3,@object # @.str.3
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.3:
.asciz "h_inVals = [ "
.size .L.str.3, 16
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "];\nh_inPos = [ "
.size .L.str.4, 19
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "h_outVals = [ "
.size .L.str.5, 16
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "];\nh_outPos = [ "
.size .L.str.6, 19
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z11partialScanPjS_S_m"
.size .L__unnamed_1, 23
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z7mapScanPjS_m"
.size .L__unnamed_2, 16
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z12mapPredicatePjS_S_jm"
.size .L__unnamed_3, 25
.type .L__unnamed_4,@object # @3
.L__unnamed_4:
.asciz "_Z7scatterPjS_S_S_S_S_S_S_m"
.size .L__unnamed_4, 28
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr.2,@object # @str.2
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr.2:
.asciz "];"
.size .Lstr.2, 3
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z26__device_stub__partialScanPjS_S_m
.addrsig_sym _Z22__device_stub__mapScanPjS_m
.addrsig_sym _Z27__device_stub__mapPredicatePjS_S_jm
.addrsig_sym _Z22__device_stub__scatterPjS_S_S_S_S_S_S_m
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z11partialScanPjS_S_m
.addrsig_sym _Z7mapScanPjS_m
.addrsig_sym _Z12mapPredicatePjS_S_jm
.addrsig_sym _Z7scatterPjS_S_S_S_S_S_S_m
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
```
| 12,367 | 12,719 |
624 |
Convert the following CUDA device assembly code to AMD device assembly:
```cudaasm
code for sm_80
Function : _Z1av
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ;
S2R R0, SR_TID.X ;
LOP3.LUT R0, R0, 0x1, RZ, 0xc0, !PT ;
ISETP.NE.U32.AND P0, PT, R0, 0x1, PT ;
@!P0 WARPSYNC 0xffffffff ;
@!P0 BAR.SYNC.DEFER_BLOCKING 0x0 ;
@!P0 EXIT ;
WARPSYNC 0xffffffff ;
BAR.SYNC.DEFER_BLOCKING 0x0 ;
EXIT ;
BRA 0xa0;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
```
|
```amdasm
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z1av ; -- Begin function _Z1av
.globl _Z1av
.p2align 8
.type _Z1av,@function
_Z1av: ; @_Z1av
; %bb.0:
v_and_b32_e32 v0, 1, v0
s_mov_b32 s0, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_eq_u32_e32 1, v0
s_xor_b32 s0, exec_lo, s0
; %bb.1:
s_barrier
; %bb.2: ; %Flow
s_and_not1_saveexec_b32 s0, s0
; %bb.3:
s_barrier
; %bb.4:
s_or_b32 exec_lo, exec_lo, s0
buffer_gl0_inv
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z1av
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 0
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 0
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 1
.amdhsa_next_free_sgpr 1
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z1av, .Lfunc_end0-_Z1av
; -- End function
.section .AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 48
; NumSgprs: 1
; NumVgprs: 1
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 0
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 1
; NumVGPRsForWavesPerEU: 1
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object ; @__hip_cuid_
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0 ; 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args: []
.group_segment_fixed_size: 0
.kernarg_segment_align: 4
.kernarg_segment_size: 0
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z1av
.private_segment_fixed_size: 0
.sgpr_count: 1
.sgpr_spill_count: 0
.symbol: _Z1av.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 1
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
```
| 242 | 1,589 |
625 |
Convert the following CUDA host assembly code to AMD host assembly:
```cudaasm
.file "tmpxft_001b035a_00000000-6_a.cudafe1.cpp"
.text
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z19__device_stub__Z1avv
.type _Z19__device_stub__Z1avv, @function
_Z19__device_stub__Z1avv:
.LFB2051:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z1av(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z19__device_stub__Z1avv, .-_Z19__device_stub__Z1avv
.globl _Z1av
.type _Z1av, @function
_Z1av:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z19__device_stub__Z1avv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z1av, .-_Z1av
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z1av"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z1av(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
```
|
```amdasm
.text
.file "a.hip"
.globl _Z16__device_stub__av # -- Begin function _Z16__device_stub__av
.type _Z16__device_stub__av,@function
_Z16__device_stub__av: # @_Z16__device_stub__av
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $56, %rsp
.cfi_def_cfa_offset 96
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 40(%rsp), %rbx
leaq 24(%rsp), %r14
leaq 16(%rsp), %r15
leaq 8(%rsp), %r12
movq %rbx, %rdi
movq %r14, %rsi
movq %r15, %rdx
movq %r12, %rcx
callq __hipPopCallConfiguration
movq (%rbx), %rsi
movl 8(%rbx), %edx
movq (%r14), %rcx
movl 8(%r14), %r8d
movq %rsp, %r9
movl $_Z1av, %edi
pushq (%r12)
.cfi_adjust_cfa_offset 8
pushq (%r15)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z16__device_stub__av, .Lfunc_end0-_Z16__device_stub__av
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, %rdi
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z1av, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z1av,@object # @_Z1av
.section .rodata,"a",@progbits
.globl _Z1av
.p2align 3, 0x0
_Z1av:
.quad _Z16__device_stub__av
.size _Z1av, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z1av"
.size .L__unnamed_1, 6
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z16__device_stub__av
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z1av
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
```
| 1,622 | 1,748 |
626 |
Convert the following CUDA device assembly code to AMD device assembly:
```cudaasm
code for sm_80
Function : _Z7ReversePiS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
MOV R1, c[0x0][0x28] ;
EXIT ;
BRA 0x20;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
```
|
```amdasm
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z7ReversePiS_ ; -- Begin function _Z7ReversePiS_
.globl _Z7ReversePiS_
.p2align 8
.type _Z7ReversePiS_,@function
_Z7ReversePiS_: ; @_Z7ReversePiS_
; %bb.0:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z7ReversePiS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 16
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 1
.amdhsa_next_free_sgpr 1
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z7ReversePiS_, .Lfunc_end0-_Z7ReversePiS_
; -- End function
.section .AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 4
; NumSgprs: 0
; NumVgprs: 0
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 0
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 1
; NumVGPRsForWavesPerEU: 1
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object ; @__hip_cuid_
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0 ; 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 16
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z7ReversePiS_
.private_segment_fixed_size: 0
.sgpr_count: 0
.sgpr_spill_count: 0
.symbol: _Z7ReversePiS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 0
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
```
| 119 | 1,538 |
627 |
Convert the following CUDA host assembly code to AMD host assembly:
```cudaasm
.file "tmpxft_001a2bee_00000000-6_Reverse_cud.cudafe1.cpp"
.text
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z28__device_stub__Z7ReversePiS_PiS_
.type _Z28__device_stub__Z7ReversePiS_PiS_, @function
_Z28__device_stub__Z7ReversePiS_PiS_:
.LFB2082:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z7ReversePiS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z28__device_stub__Z7ReversePiS_PiS_, .-_Z28__device_stub__Z7ReversePiS_PiS_
.globl _Z7ReversePiS_
.type _Z7ReversePiS_, @function
_Z7ReversePiS_:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z28__device_stub__Z7ReversePiS_PiS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z7ReversePiS_, .-_Z7ReversePiS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Data In: "
.LC1:
.string "%d "
.LC2:
.string "\n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC3:
.string "/home/ubuntu/Datasets/stackv2/train-structured/franckginguene/hpc_formation_scalian/main/Exercices/Cuda/Reverse_cud/Reverse_cud.cu"
.section .rodata.str1.1
.LC4:
.string "Kernel Execution Failed!"
.section .rodata.str1.8
.align 8
.LC5:
.string "Cuda error: %s in file '%s' in line %i : %s.\n"
.section .rodata.str1.1
.LC6:
.string "Data Out: "
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $80, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
leaq .LC0(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
movl $0, %ebx
leaq .LC1(%rip), %rbp
.L12:
movl %ebx, %edx
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $1, %ebx
cmpl $10, %ebx
jne .L12
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 8(%rsp)
movl $1, 12(%rsp)
movl $1, 16(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L20
.L13:
call cudaGetLastError@PLT
testl %eax, %eax
jne .L21
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 32(%rsp), %rbx
leaq 72(%rsp), %r12
leaq .LC1(%rip), %rbp
.L15:
movl (%rbx), %edx
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %r12, %rbx
jne .L15
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L22
movl $0, %eax
addq $80, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L20:
.cfi_restore_state
movl $0, %esi
movl $0, %edi
call _Z28__device_stub__Z7ReversePiS_PiS_
jmp .L13
.L21:
movl %eax, %edi
call cudaGetErrorString@PLT
subq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 120
pushq %rax
.cfi_def_cfa_offset 128
movl $49, %r9d
leaq .LC3(%rip), %r8
leaq .LC4(%rip), %rcx
leaq .LC5(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L22:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC7:
.string "_Z7ReversePiS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _Z7ReversePiS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
```
|
```amdasm
.text
.file "Reverse_cud.hip"
.globl _Z22__device_stub__ReversePiS_ # -- Begin function _Z22__device_stub__ReversePiS_
.type _Z22__device_stub__ReversePiS_,@function
_Z22__device_stub__ReversePiS_: # @_Z22__device_stub__ReversePiS_
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $80, %rsp
.cfi_def_cfa_offset 128
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 24(%rsp), %rax
movq %rdi, (%rax)
leaq 16(%rsp), %rcx
movq %rsi, (%rcx)
leaq 64(%rsp), %rbx
movq %rax, (%rbx)
movq %rcx, 8(%rbx)
leaq 48(%rsp), %r14
leaq 32(%rsp), %r15
leaq 8(%rsp), %r12
movq %rsp, %r13
movq %r14, %rdi
movq %r15, %rsi
movq %r12, %rdx
movq %r13, %rcx
callq __hipPopCallConfiguration
movq (%r14), %rsi
movl 8(%r14), %edx
movq (%r15), %rcx
movl 8(%r15), %r8d
movl $_Z7ReversePiS_, %edi
movq %rbx, %r9
pushq (%r13)
.cfi_adjust_cfa_offset 8
pushq (%r12)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $96, %rsp
.cfi_adjust_cfa_offset -96
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z22__device_stub__ReversePiS_, .Lfunc_end0-_Z22__device_stub__ReversePiS_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $48, %rsp
.cfi_def_cfa_offset 64
.cfi_offset %rbx, -16
movl $.L.str, %edi
xorl %eax, %eax
callq printf
xorl %ebx, %ebx
.LBB1_1: # =>This Inner Loop Header: Depth=1
movl $.L.str.1, %edi
movl %ebx, %esi
xorl %eax, %eax
callq printf
incl %ebx
cmpl $10, %ebx
jne .LBB1_1
# %bb.2:
movl $10, %edi
callq putchar@PLT
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
callq _Z22__device_stub__ReversePiS_
.LBB1_4:
callq hipGetLastError
testl %eax, %eax
jne .LBB1_8
# %bb.5:
movl $.L.str.6, %edi
xorl %eax, %eax
callq printf
xorl %ebx, %ebx
.LBB1_6: # =>This Inner Loop Header: Depth=1
movl (%rsp,%rbx,4), %esi
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
incq %rbx
cmpq $10, %rbx
jne .LBB1_6
# %bb.7:
movl $10, %edi
callq putchar@PLT
xorl %eax, %eax
addq $48, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.LBB1_8:
.cfi_def_cfa_offset 64
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.3, %esi
movl $.L.str.4, %edx
movl $.L.str.5, %ecx
movq %rbx, %rdi
movl $51, %r8d
movq %rax, %r9
xorl %eax, %eax
callq fprintf
movl $1, %edi
callq exit
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, %rdi
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7ReversePiS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z7ReversePiS_,@object # @_Z7ReversePiS_
.section .rodata,"a",@progbits
.globl _Z7ReversePiS_
.p2align 3, 0x0
_Z7ReversePiS_:
.quad _Z22__device_stub__ReversePiS_
.size _Z7ReversePiS_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Data In: "
.size .L.str, 11
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "%d "
.size .L.str.1, 4
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Cuda error: %s in file '%s' in line %i : %s.\n"
.size .L.str.3, 46
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Kernel Execution Failed!"
.size .L.str.4, 25
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/franckginguene/hpc_formation_scalian/main/Exercices/Cuda/Reverse_cud/Reverse_cud.hip"
.size .L.str.5, 142
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "Data Out: "
.size .L.str.6, 11
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z7ReversePiS_"
.size .L__unnamed_1, 15
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__ReversePiS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z7ReversePiS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
```
| 3,089 | 3,002 |
634 |
Convert the following CUDA device assembly code to AMD device assembly:
```cudaasm
code for sm_80
Function : _Z8dijkstraiPiS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ;
S2R R2, SR_CTAID.X ;
IADD3 R1, R1, -0x370, RZ ;
S2R R3, SR_TID.X ;
IMAD R2, R2, c[0x0][0x0], R3 ;
ISETP.GE.AND P0, PT, R2, c[0x0][0x160], PT ;
@P0 EXIT ;
IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x160] ;
IADD3 R5, R1, 0x1b8, RZ ;
ULDC.64 UR4, c[0x0][0x118] ;
LOP3.LUT R3, R4.reuse, 0x3, RZ, 0xc0, !PT ;
IADD3 R4, R4, -0x1, RZ ;
IADD3 R6, -R3, c[0x0][0x160], RZ ;
IMAD.MOV.U32 R17, RZ, RZ, c[0x0][0x160] ;
ISETP.GE.AND P1, PT, R17, 0x1, PT ;
@!P1 BRA 0x640 ;
ISETP.GE.U32.AND P0, PT, R4, 0x3, PT ;
IMAD.MOV.U32 R10, RZ, RZ, RZ ;
@!P0 BRA 0x570 ;
ISETP.GT.AND P0, PT, R6, RZ, PT ;
IMAD.MOV.U32 R10, RZ, RZ, RZ ;
IMAD.MOV.U32 R7, RZ, RZ, R6 ;
@!P0 BRA 0x4c0 ;
ISETP.GT.AND P2, PT, R7, 0xc, PT ;
PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ;
@!P2 BRA 0x380 ;
PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ;
IADD3 R12, R10.reuse, 0x4, RZ ;
IMAD R11, R10.reuse, 0x4, R1.reuse ;
IADD3 R14, R10.reuse, 0x8, RZ ;
IMAD.MOV.U32 R8, RZ, RZ, 0x7fffffff ;
IADD3 R16, R10, 0xc, RZ ;
IMAD.MOV.U32 R9, RZ, RZ, 0x7fffffff ;
STL.64 [R11+0x1b8], RZ ;
IMAD R12, R12, 0x4, R1.reuse ;
IADD3 R7, R7, -0x10, RZ ;
IMAD R14, R14, 0x4, R1.reuse ;
STL.64 [R11], R8 ;
IMAD R16, R16, 0x4, R1 ;
ISETP.GT.AND P2, PT, R7, 0xc, PT ;
STL.64 [R11+0x8], R8 ;
IADD3 R10, R10, 0x10, RZ ;
STL.64 [R11+0x1c0], RZ ;
STL.64 [R12], R8 ;
STL.64 [R12+0x1b8], RZ ;
STL.64 [R12+0x8], R8 ;
STL.64 [R12+0x1c0], RZ ;
STL.64 [R14], R8 ;
STL.64 [R14+0x1b8], RZ ;
STL.64 [R14+0x8], R8 ;
STL.64 [R14+0x1c0], RZ ;
STL.64 [R16], R8 ;
STL.64 [R16+0x8], R8 ;
STL.64 [R16+0x1b8], RZ ;
STL.64 [R16+0x1c0], RZ ;
@P2 BRA 0x1b0 ;
ISETP.GT.AND P2, PT, R7, 0x4, PT ;
@!P2 BRA 0x4a0 ;
IADD3 R12, R10.reuse, 0x4, RZ ;
IMAD R8, R10, 0x4, R1.reuse ;
PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ;
IMAD.MOV.U32 R14, RZ, RZ, 0x7fffffff ;
IADD3 R7, R7, -0x8, RZ ;
IMAD.MOV.U32 R15, RZ, RZ, 0x7fffffff ;
STL.64 [R8+0x1b8], RZ ;
IMAD R12, R12, 0x4, R1 ;
IADD3 R10, R10, 0x8, RZ ;
STL.64 [R8], R14 ;
STL.64 [R8+0x8], R14 ;
STL.64 [R8+0x1c0], RZ ;
STL.64 [R12], R14 ;
STL.64 [R12+0x8], R14 ;
STL.64 [R12+0x1b8], RZ ;
STL.64 [R12+0x1c0], RZ ;
ISETP.NE.OR P0, PT, R7, RZ, P0 ;
@!P0 BRA 0x570 ;
IMAD.MOV.U32 R12, RZ, RZ, 0x7fffffff ;
IMAD R8, R10.reuse, 0x4, R1 ;
IADD3 R7, R7, -0x4, RZ ;
IMAD.MOV.U32 R13, RZ, RZ, 0x7fffffff ;
IADD3 R10, R10, 0x4, RZ ;
STL.64 [R8+0x1b8], RZ ;
ISETP.NE.AND P0, PT, R7, RZ, PT ;
STL.64 [R8], R12 ;
STL.64 [R8+0x8], R12 ;
STL.64 [R8+0x1c0], RZ ;
@P0 BRA 0x4d0 ;
ISETP.NE.AND P0, PT, R3, RZ, PT ;
@!P0 BRA 0x640 ;
IMAD R10, R10, 0x4, R1 ;
ISETP.NE.AND P0, PT, R3, 0x1, PT ;
IMAD.MOV.U32 R7, RZ, RZ, 0x7fffffff ;
STL [R10+0x1b8], RZ ;
STL [R10], R7 ;
@!P0 BRA 0x640 ;
ISETP.NE.AND P0, PT, R3, 0x2, PT ;
STL [R10+0x4], R7 ;
STL [R10+0x1bc], RZ ;
@P0 STL [R10+0x8], R7 ;
@P0 STL [R10+0x1c0], RZ ;
IMAD R7, R2, 0x4, R1 ;
ISETP.GE.AND P0, PT, R17, 0x2, PT ;
STL [R7], RZ ;
@!P0 BRA 0x1ed0 ;
IMAD.MOV.U32 R11, RZ, RZ, RZ ;
ISETP.GE.U32.AND P2, PT, R4, 0x3, PT ;
IMAD.MOV.U32 R10, RZ, RZ, 0x7fffffff ;
IADD3 R11, R11, 0x1, RZ ;
IMAD.MOV.U32 R13, RZ, RZ, RZ ;
ISETP.GE.AND P3, PT, R11, R4, PT ;
@!P2 BRA 0x1460 ;
ISETP.GT.AND P0, PT, R6, RZ, PT ;
IMAD.MOV.U32 R10, RZ, RZ, 0x7fffffff ;
IMAD.MOV.U32 R13, RZ, RZ, RZ ;
IMAD.MOV.U32 R7, RZ, RZ, R1 ;
IMAD.MOV.U32 R16, RZ, RZ, R5 ;
IMAD.MOV.U32 R12, RZ, RZ, R6 ;
@!P0 BRA 0x1270 ;
ISETP.GT.AND P4, PT, R12, 0xc, PT ;
PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ;
@!P4 BRA 0xe70 ;
PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ;
LDL.64 R8, [R16] ;
ISETP.NE.AND P6, PT, R8, RZ, PT ;
ISETP.NE.AND P5, PT, R9, RZ, PT ;
LDL.64 R8, [R16+0x8] ;
@!P6 LDL R15, [R7] ;
@!P5 LDL R17, [R7+0x4] ;
@!P6 ISETP.GT.AND P4, PT, R15, R10, PT ;
@!P6 IMNMX R10, R10, R15, PT ;
@!P6 SEL R0, R0, R13, P4 ;
ISETP.NE.AND P6, PT, R8, RZ, PT ;
@!P5 IADD3 R15, R13, 0x1, RZ ;
@!P5 ISETP.GT.AND P4, PT, R17, R10, PT ;
@!P5 SEL R0, R0, R15, P4 ;
ISETP.NE.AND P4, PT, R9, RZ, PT ;
LDL.64 R8, [R16+0x10] ;
@!P6 LDL R15, [R7+0x8] ;
@!P4 LDL R19, [R7+0xc] ;
@!P5 IMNMX R10, R10, R17, PT ;
@!P6 IADD3 R17, R13, 0x2, RZ ;
@!P6 ISETP.GT.AND P5, PT, R15, R10, PT ;
@!P6 IMNMX R10, R10, R15, PT ;
@!P6 SEL R0, R0, R17, P5 ;
ISETP.NE.AND P6, PT, R8, RZ, PT ;
@!P4 IADD3 R15, R13, 0x3, RZ ;
@!P4 ISETP.GT.AND P5, PT, R19, R10, PT ;
@!P4 SEL R0, R0, R15, P5 ;
ISETP.NE.AND P5, PT, R9, RZ, PT ;
LDL.64 R8, [R16+0x18] ;
@!P6 LDL R15, [R7+0x10] ;
@!P5 LDL R21, [R7+0x14] ;
@!P4 IMNMX R10, R10, R19, PT ;
IADD3 R17, R13, 0x4, RZ ;
@!P6 ISETP.GT.AND P4, PT, R15, R10, PT ;
@!P6 IMNMX R10, R10, R15, PT ;
@!P6 SEL R0, R0, R17, P4 ;
ISETP.NE.AND P6, PT, R8, RZ, PT ;
@!P5 IADD3 R15, R13, 0x5, RZ ;
@!P5 ISETP.GT.AND P4, PT, R21, R10, PT ;
@!P5 SEL R0, R0, R15, P4 ;
ISETP.NE.AND P4, PT, R9, RZ, PT ;
LDL.64 R8, [R16+0x20] ;
@!P6 LDL R15, [R7+0x18] ;
@!P4 LDL R19, [R7+0x1c] ;
@!P5 IMNMX R10, R10, R21, PT ;
@!P6 IADD3 R17, R13, 0x6, RZ ;
@!P6 ISETP.GT.AND P5, PT, R15, R10, PT ;
@!P6 IMNMX R10, R10, R15, PT ;
@!P6 SEL R0, R0, R17, P5 ;
ISETP.NE.AND P6, PT, R8, RZ, PT ;
@!P4 IADD3 R15, R13, 0x7, RZ ;
@!P4 ISETP.GT.AND P5, PT, R19, R10, PT ;
@!P4 SEL R0, R0, R15, P5 ;
ISETP.NE.AND P5, PT, R9, RZ, PT ;
LDL.64 R8, [R16+0x28] ;
@!P6 LDL R15, [R7+0x20] ;
@!P5 LDL R21, [R7+0x24] ;
@!P4 IMNMX R10, R10, R19, PT ;
IADD3 R17, R13, 0x8, RZ ;
@!P6 ISETP.GT.AND P4, PT, R15, R10, PT ;
@!P6 IMNMX R10, R10, R15, PT ;
@!P6 SEL R0, R0, R17, P4 ;
ISETP.NE.AND P6, PT, R8, RZ, PT ;
@!P5 IADD3 R15, R13, 0x9, RZ ;
@!P5 ISETP.GT.AND P4, PT, R21, R10, PT ;
@!P5 SEL R0, R0, R15, P4 ;
ISETP.NE.AND P4, PT, R9, RZ, PT ;
LDL.64 R8, [R16+0x30] ;
@!P6 LDL R15, [R7+0x28] ;
@!P4 LDL R19, [R7+0x2c] ;
@!P5 IMNMX R10, R10, R21, PT ;
@!P6 IADD3 R17, R13, 0xa, RZ ;
@!P6 ISETP.GT.AND P5, PT, R15, R10, PT ;
@!P6 IMNMX R10, R10, R15, PT ;
@!P6 SEL R0, R0, R17, P5 ;
ISETP.NE.AND P6, PT, R8, RZ, PT ;
@!P4 IADD3 R15, R13, 0xb, RZ ;
@!P4 ISETP.GT.AND P5, PT, R19, R10, PT ;
@!P4 SEL R0, R0, R15, P5 ;
ISETP.NE.AND P5, PT, R9, RZ, PT ;
LDL.64 R8, [R16+0x38] ;
@!P6 LDL R15, [R7+0x30] ;
@!P5 LDL R21, [R7+0x34] ;
@!P4 IMNMX R10, R10, R19, PT ;
IADD3 R17, R13, 0xc, RZ ;
@!P6 ISETP.GT.AND P4, PT, R15, R10, PT ;
@!P6 SEL R0, R0, R17, P4 ;
ISETP.NE.AND P4, PT, R8, RZ, PT ;
@!P6 IMNMX R10, R10, R15, PT ;
@!P5 IADD3 R15, R13, 0xd, RZ ;
@!P5 ISETP.GT.AND P6, PT, R21, R10, PT ;
@!P5 SEL R0, R0, R15, P6 ;
ISETP.NE.AND P6, PT, R9, RZ, PT ;
@!P4 LDL R9, [R7+0x38] ;
@!P6 LDL R17, [R7+0x3c] ;
@!P5 IMNMX R10, R10, R21, PT ;
@!P4 IADD3 R15, R13, 0xe, RZ ;
IADD3 R12, R12, -0x10, RZ ;
IADD3 R16, R16, 0x40, RZ ;
IADD3 R7, R7, 0x40, RZ ;
@!P4 ISETP.GT.AND P5, PT, R9, R10, PT ;
@!P4 SEL R0, R0, R15, P5 ;
ISETP.GT.AND P5, PT, R12, 0xc, PT ;
@!P4 IMNMX R10, R10, R9, PT ;
@!P6 IADD3 R9, R13, 0xf, RZ ;
@!P6 ISETP.GT.AND P4, PT, R17, R10, PT ;
@!P6 IMNMX R10, R10, R17, PT ;
@!P6 SEL R0, R0, R9, P4 ;
IADD3 R13, R13, 0x10, RZ ;
@P5 BRA 0x7a0 ;
ISETP.GT.AND P4, PT, R12, 0x4, PT ;
@!P4 BRA 0x1250 ;
LDL.64 R8, [R16] ;
LDL R14, [R16+0x10] ;
ISETP.NE.AND P4, PT, R8, RZ, PT ;
ISETP.NE.AND P5, PT, R9, RZ, PT ;
LDL.64 R8, [R16+0x8] ;
@!P4 LDL R15, [R7] ;
@!P5 LDL R17, [R7+0x4] ;
ISETP.NE.AND P6, PT, R8, RZ, PT ;
@!P4 ISETP.GT.AND P0, PT, R15, R10, PT ;
@!P4 IMNMX R10, R10, R15, PT ;
@!P4 SEL R0, R0, R13, P0 ;
@!P6 LDL R15, [R7+0x8] ;
ISETP.NE.AND P4, PT, R9, RZ, PT ;
@!P5 IADD3 R9, R13, 0x1, RZ ;
@!P5 ISETP.GT.AND P0, PT, R17, R10, PT ;
@!P5 SEL R0, R0, R9, P0 ;
ISETP.NE.AND P0, PT, R14, RZ, PT ;
LDL.64 R8, [R16+0x18] ;
LDL R14, [R16+0x14] ;
@!P4 LDL R21, [R7+0xc] ;
@!P0 LDL R19, [R7+0x10] ;
@!P5 IMNMX R10, R10, R17, PT ;
@!P6 IADD3 R17, R13, 0x2, RZ ;
@!P6 ISETP.GT.AND P5, PT, R15, R10, PT ;
@!P6 IMNMX R10, R10, R15, PT ;
@!P6 SEL R0, R0, R17, P5 ;
@!P4 IADD3 R15, R13, 0x3, RZ ;
ISETP.NE.AND P5, PT, R14, RZ, PT ;
@!P4 ISETP.GT.AND P6, PT, R21, R10, PT ;
@!P4 IMNMX R10, R10, R21, PT ;
@!P4 SEL R0, R0, R15, P6 ;
ISETP.NE.AND P6, PT, R8, RZ, PT ;
IADD3 R15, R13, 0x4, RZ ;
@!P0 ISETP.GT.AND P4, PT, R19, R10, PT ;
IADD3 R8, R7, 0x10, RZ ;
@!P0 SEL R0, R0, R15, P4 ;
ISETP.NE.AND P4, PT, R9, RZ, PT ;
@!P5 LDL R7, [R8+0x4] ;
@!P6 LDL R13, [R8+0x8] ;
@!P4 LDL R17, [R8+0xc] ;
@!P0 IMNMX R10, R10, R19, PT ;
@!P5 IADD3 R9, R15, 0x1, RZ ;
IADD3 R12, R12, -0x4, RZ ;
IADD3 R16, R16, 0x10, RZ ;
IADD3 R12, R12, -0x4, RZ ;
IADD3 R16, R16, 0x10, RZ ;
@!P5 ISETP.GT.AND P0, PT, R7, R10, PT ;
@!P5 IMNMX R10, R10, R7, PT ;
@!P5 SEL R0, R0, R9, P0 ;
@!P6 IADD3 R7, R15, 0x2, RZ ;
@!P6 ISETP.GT.AND P0, PT, R13, R10, PT ;
@!P6 IMNMX R10, R10, R13, PT ;
@!P6 SEL R0, R0, R7, P0 ;
@!P4 IADD3 R7, R15, 0x3, RZ ;
@!P4 ISETP.GT.AND P5, PT, R17, R10, PT ;
PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ;
@!P4 SEL R0, R0, R7, P5 ;
@!P4 IMNMX R10, R10, R17, PT ;
IADD3 R7, R8, 0x10, RZ ;
IADD3 R13, R15, 0x4, RZ ;
ISETP.NE.OR P0, PT, R12, RZ, P0 ;
@!P0 BRA 0x1460 ;
LDL.64 R14, [R16] ;
LDL.64 R8, [R16+0x8] ;
ISETP.NE.AND P0, PT, R14, RZ, PT ;
@!P0 LDL R17, [R7] ;
ISETP.NE.AND P5, PT, R15, RZ, PT ;
ISETP.NE.AND P4, PT, R8, RZ, PT ;
@!P5 LDL R19, [R7+0x4] ;
@!P4 LDL R15, [R7+0x8] ;
@!P0 ISETP.GT.AND P6, PT, R17, R10, PT ;
@!P0 SEL R0, R0, R13, P6 ;
ISETP.NE.AND P6, PT, R9, RZ, PT ;
@!P6 LDL R21, [R7+0xc] ;
@!P0 IMNMX R10, R10, R17, PT ;
@!P5 IADD3 R9, R13, 0x1, RZ ;
@!P5 ISETP.GT.AND P0, PT, R19, R10, PT ;
@!P5 IMNMX R10, R10, R19, PT ;
@!P5 SEL R0, R0, R9, P0 ;
@!P4 IADD3 R9, R13, 0x2, RZ ;
@!P4 ISETP.GT.AND P0, PT, R15, R10, PT ;
IADD3 R12, R12, -0x4, RZ ;
@!P4 IMNMX R10, R10, R15, PT ;
@!P4 SEL R0, R0, R9, P0 ;
ISETP.NE.AND P4, PT, R12, RZ, PT ;
@!P6 IADD3 R9, R13, 0x3, RZ ;
IADD3 R16, R16, 0x10, RZ ;
IADD3 R7, R7, 0x10, RZ ;
IADD3 R13, R13, 0x4, RZ ;
@!P6 ISETP.GT.AND P0, PT, R21, R10, PT ;
@!P6 IMNMX R10, R10, R21, PT ;
@!P6 SEL R0, R0, R9, P0 ;
@P4 BRA 0x1270 ;
ISETP.NE.AND P0, PT, R3, RZ, PT ;
@!P0 BRA 0x1680 ;
IMAD R8, R13, 0x4, R1 ;
LDL.64 R14, [R8+0x1b8] ;
BSSY B0, 0x1530 ;
ISETP.NE.AND P5, PT, R3, 0x1, PT ;
ISETP.NE.AND P4, PT, R14, RZ, PT ;
@P4 BRA 0x1520 ;
LDL R7, [R8] ;
ISETP.GT.AND P4, PT, R7, R10, PT ;
IMNMX R10, R10, R7, PT ;
SEL R0, R0, R13, P4 ;
BSYNC B0 ;
BSSY B0, 0x1680 ;
@!P5 BRA 0x1670 ;
ISETP.NE.AND P4, PT, R15, RZ, PT ;
BSSY B1, 0x15f0 ;
ISETP.NE.AND P5, PT, R3, 0x2, PT ;
@P4 BRA 0x15e0 ;
LDL R9, [R8+0x4] ;
IADD3 R7, R13, 0x1, RZ ;
ISETP.GT.AND P4, PT, R9, R10, PT ;
IMNMX R10, R10, R9, PT ;
SEL R0, R0, R7, P4 ;
BSYNC B1 ;
@!P5 BRA 0x1670 ;
LDL R7, [R8+0x1c0] ;
ISETP.NE.AND P4, PT, R7, RZ, PT ;
@P4 BRA 0x1670 ;
LDL R7, [R8+0x8] ;
IADD3 R13, R13, 0x2, RZ ;
ISETP.GT.AND P4, PT, R7, R10, PT ;
SEL R0, R0, R13, P4 ;
BSYNC B0 ;
IMAD R7, R0, 0x4, R5 ;
IMAD.MOV.U32 R8, RZ, RZ, 0x1 ;
STL [R7], R8 ;
@!P1 BRA 0x1eb0 ;
IMAD.U32 R7, R0, 0x4, R1 ;
IMAD.MOV.U32 R10, RZ, RZ, RZ ;
@!P2 BRA 0x1b50 ;
IMAD.MOV.U32 R10, RZ, RZ, RZ ;
IMAD.MOV.U32 R13, RZ, RZ, R6 ;
IMAD R12, R10, 0x4, R1 ;
LDL R8, [R12+0x1b8] ;
IADD3 R13, R13, -0x4, RZ ;
IMAD.MOV.U32 R9, RZ, RZ, 0x4 ;
BSSY B0, 0x1860 ;
ISETP.NE.AND P2, PT, R13, RZ, PT ;
ISETP.NE.AND P4, PT, R8, RZ, PT ;
IMAD R8, R0, c[0x0][0x160], R10 ;
IMAD.WIDE R8, R8, R9, c[0x0][0x170] ;
@P4 BRA 0x1850 ;
LDG.E R15, [R8.64] ;
ISETP.NE.AND P4, PT, R15, RZ, PT ;
@!P4 BRA 0x1850 ;
LDL R16, [R7] ;
ISETP.NE.AND P4, PT, R16, 0x7fffffff, PT ;
@!P4 BRA 0x1850 ;
LDL R14, [R12] ;
IMAD.IADD R15, R15, 0x1, R16 ;
ISETP.GE.AND P4, PT, R15, R14, PT ;
@!P4 STL [R12], R15 ;
BSYNC B0 ;
LDL R14, [R12+0x1bc] ;
BSSY B0, 0x1950 ;
ISETP.NE.AND P4, PT, R14, RZ, PT ;
@P4 BRA 0x1940 ;
LDG.E R14, [R8.64+0x4] ;
ISETP.NE.AND P4, PT, R14, RZ, PT ;
@!P4 BRA 0x1940 ;
LDL R15, [R7] ;
ISETP.NE.AND P4, PT, R15, 0x7fffffff, PT ;
@!P4 BRA 0x1940 ;
LDL R16, [R12+0x4] ;
IMAD.IADD R15, R14, 0x1, R15 ;
ISETP.GE.AND P4, PT, R15, R16, PT ;
@!P4 STL [R12+0x4], R15 ;
BSYNC B0 ;
LDL R14, [R12+0x1c0] ;
BSSY B0, 0x1a40 ;
ISETP.NE.AND P4, PT, R14, RZ, PT ;
@P4 BRA 0x1a30 ;
LDG.E R15, [R8.64+0x8] ;
ISETP.NE.AND P4, PT, R15, RZ, PT ;
@!P4 BRA 0x1a30 ;
LDL R16, [R7] ;
ISETP.NE.AND P4, PT, R16, 0x7fffffff, PT ;
@!P4 BRA 0x1a30 ;
LDL R14, [R12+0x8] ;
IMAD.IADD R15, R15, 0x1, R16 ;
ISETP.GE.AND P4, PT, R15, R14, PT ;
@!P4 STL [R12+0x8], R15 ;
BSYNC B0 ;
LDL R14, [R12+0x1c4] ;
BSSY B0, 0x1b30 ;
ISETP.NE.AND P4, PT, R14, RZ, PT ;
@P4 BRA 0x1b20 ;
LDG.E R8, [R8.64+0xc] ;
ISETP.NE.AND P4, PT, R8, RZ, PT ;
@!P4 BRA 0x1b20 ;
LDL R9, [R7] ;
ISETP.NE.AND P4, PT, R9, 0x7fffffff, PT ;
@!P4 BRA 0x1b20 ;
LDL R14, [R12+0xc] ;
IMAD.IADD R9, R8, 0x1, R9 ;
ISETP.GE.AND P4, PT, R9, R14, PT ;
@!P4 STL [R12+0xc], R9 ;
BSYNC B0 ;
IADD3 R10, R10, 0x4, RZ ;
@P2 BRA 0x1710 ;
BSSY B0, 0x1eb0 ;
@!P0 BRA 0x1ea0 ;
IMAD R12, R10, 0x4, R1 ;
LDL R8, [R12+0x1b8] ;
IMAD.MOV.U32 R9, RZ, RZ, 0x4 ;
BSSY B1, 0x1ca0 ;
ISETP.NE.AND P0, PT, R8, RZ, PT ;
IMAD R8, R0, c[0x0][0x160], R10 ;
IMAD.WIDE R8, R8, R9, c[0x0][0x170] ;
@P0 BRA 0x1c90 ;
LDG.E R13, [R8.64] ;
ISETP.NE.AND P0, PT, R13, RZ, PT ;
@!P0 BRA 0x1c90 ;
LDL R14, [R7] ;
ISETP.NE.AND P0, PT, R14, 0x7fffffff, PT ;
@!P0 BRA 0x1c90 ;
LDL R10, [R12] ;
IMAD.IADD R13, R13, 0x1, R14 ;
ISETP.GE.AND P0, PT, R13, R10, PT ;
@!P0 STL [R12], R13 ;
BSYNC B1 ;
ISETP.NE.AND P0, PT, R3, 0x1, PT ;
@!P0 BRA 0x1ea0 ;
LDL R10, [R12+0x1bc] ;
BSSY B1, 0x1db0 ;
ISETP.NE.AND P0, PT, R10, RZ, PT ;
@P0 BRA 0x1da0 ;
LDG.E R10, [R8.64+0x4] ;
ISETP.NE.AND P0, PT, R10, RZ, PT ;
@!P0 BRA 0x1da0 ;
LDL R13, [R7] ;
ISETP.NE.AND P0, PT, R13, 0x7fffffff, PT ;
@!P0 BRA 0x1da0 ;
LDL R14, [R12+0x4] ;
IMAD.IADD R13, R10, 0x1, R13 ;
ISETP.GE.AND P0, PT, R13, R14, PT ;
@!P0 STL [R12+0x4], R13 ;
BSYNC B1 ;
ISETP.NE.AND P0, PT, R3, 0x2, PT ;
@!P0 BRA 0x1ea0 ;
LDL R10, [R12+0x1c0] ;
ISETP.NE.AND P0, PT, R10, RZ, PT ;
@P0 BRA 0x1ea0 ;
LDG.E R8, [R8.64+0x8] ;
ISETP.NE.AND P0, PT, R8, RZ, PT ;
@!P0 BRA 0x1ea0 ;
LDL R9, [R7] ;
ISETP.NE.AND P0, PT, R9, 0x7fffffff, PT ;
@!P0 BRA 0x1ea0 ;
LDL R7, [R12+0x8] ;
IMAD.IADD R8, R8, 0x1, R9 ;
ISETP.GE.AND P0, PT, R8, R7, PT ;
@!P0 STL [R12+0x8], R8 ;
BSYNC B0 ;
@P3 CALL.REL.NOINC 0x1ed0 ;
BRA 0x690 ;
@!P1 BRA 0x25d0 ;
ISETP.GE.U32.AND P0, PT, R4, 0x3, PT ;
IMAD.MOV.U32 R7, RZ, RZ, RZ ;
@!P0 BRA 0x24e0 ;
ISETP.GT.AND P0, PT, R6, RZ, PT ;
IMAD.MOV.U32 R7, RZ, RZ, RZ ;
IMAD.MOV.U32 R22, RZ, RZ, R6 ;
@!P0 BRA 0x2400 ;
ISETP.GT.AND P1, PT, R22, 0xc, PT ;
PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ;
@!P1 BRA 0x2250 ;
PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ;
IMAD R10, R7, 0x4, R1 ;
LDL.64 R24, [R10+0x8] ;
LDL.64 R28, [R10] ;
IMAD.MOV.U32 R26, RZ, RZ, 0x4 ;
IMAD R19, R2, c[0x0][0x160], R7 ;
IADD3 R20, R7.reuse, 0x4, RZ ;
IADD3 R23, R7, 0x8, RZ ;
IMAD.WIDE R18, R19, R26, c[0x0][0x168] ;
IADD3 R27, R7, 0xc, RZ ;
IMAD R11, R20, 0x4, R1.reuse ;
IMAD R14, R23, 0x4, R1 ;
LDL.64 R8, [R11] ;
LDL.64 R12, [R14] ;
LDL.64 R10, [R11+0x8] ;
LDL.64 R14, [R14+0x8] ;
STG.E [R18.64+0x8], R24 ;
STG.E [R18.64], R28 ;
STG.E [R18.64+0x4], R29 ;
IMAD R24, R27, 0x4, R1 ;
STG.E [R18.64+0xc], R25 ;
LDL.64 R16, [R24] ;
LDL.64 R18, [R24+0x8] ;
IMAD R21, R2.reuse, c[0x0][0x160], R20 ;
IMAD R29, R2, c[0x0][0x160], R23 ;
IMAD R27, R2, c[0x0][0x160], R27 ;
IMAD.WIDE R20, R21, R26, c[0x0][0x168] ;
IMAD.WIDE R28, R29, R26.reuse, c[0x0][0x168] ;
STG.E [R20.64], R8 ;
IMAD.WIDE R26, R27, R26, c[0x0][0x168] ;
STG.E [R20.64+0x4], R9 ;
IADD3 R22, R22, -0x10, RZ ;
STG.E [R20.64+0x8], R10 ;
STG.E [R20.64+0xc], R11 ;
STG.E [R28.64], R12 ;
STG.E [R28.64+0x4], R13 ;
STG.E [R28.64+0x8], R14 ;
STG.E [R28.64+0xc], R15 ;
ISETP.GT.AND P1, PT, R22, 0xc, PT ;
IADD3 R7, R7, 0x10, RZ ;
STG.E [R26.64], R16 ;
STG.E [R26.64+0x4], R17 ;
STG.E [R26.64+0x8], R18 ;
STG.E [R26.64+0xc], R19 ;
@P1 BRA 0x1f90 ;
ISETP.GT.AND P1, PT, R22, 0x4, PT ;
@!P1 BRA 0x23e0 ;
IADD3 R16, R7.reuse, 0x4, RZ ;
IMAD R20, R7, 0x4, R1 ;
IMAD R21, R16, 0x4, R1 ;
LDL.64 R14, [R20] ;
LDL.64 R12, [R20+0x8] ;
LDL.64 R10, [R21] ;
LDL.64 R8, [R21+0x8] ;
IMAD.MOV.U32 R17, RZ, RZ, 0x4 ;
PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ;
IMAD R18, R2, c[0x0][0x160], R7 ;
IADD3 R22, R22, -0x8, RZ ;
IMAD R16, R2, c[0x0][0x160], R16 ;
IADD3 R7, R7, 0x8, RZ ;
IMAD.WIDE R18, R18, R17, c[0x0][0x168] ;
IMAD.WIDE R16, R16, R17, c[0x0][0x168] ;
STG.E [R18.64], R14 ;
STG.E [R18.64+0x4], R15 ;
STG.E [R18.64+0x8], R12 ;
STG.E [R18.64+0xc], R13 ;
STG.E [R16.64], R10 ;
STG.E [R16.64+0x4], R11 ;
STG.E [R16.64+0x8], R8 ;
STG.E [R16.64+0xc], R9 ;
ISETP.NE.OR P0, PT, R22, RZ, P0 ;
@!P0 BRA 0x24e0 ;
IMAD R14, R7, 0x4, R1 ;
LDL.64 R8, [R14] ;
LDL.64 R12, [R14+0x8] ;
IMAD.MOV.U32 R11, RZ, RZ, 0x4 ;
IADD3 R22, R22, -0x4, RZ ;
IMAD R10, R2, c[0x0][0x160], R7 ;
IADD3 R7, R7, 0x4, RZ ;
ISETP.NE.AND P0, PT, R22, RZ, PT ;
IMAD.WIDE R10, R10, R11, c[0x0][0x168] ;
STG.E [R10.64], R8 ;
STG.E [R10.64+0x4], R9 ;
STG.E [R10.64+0x8], R12 ;
STG.E [R10.64+0xc], R13 ;
@P0 BRA 0x2400 ;
ISETP.NE.AND P0, PT, R3, RZ, PT ;
@!P0 BRA 0x25d0 ;
IMAD R10, R7, 0x4, R1 ;
LDL.64 R12, [R10] ;
IMAD.MOV.U32 R9, RZ, RZ, 0x4 ;
ISETP.NE.AND P0, PT, R3, 0x1, PT ;
IMAD R8, R2, c[0x0][0x160], R7 ;
IMAD.WIDE R8, R8, R9, c[0x0][0x168] ;
STG.E [R8.64], R12 ;
@!P0 BRA 0x25d0 ;
STG.E [R8.64+0x4], R13 ;
ISETP.NE.AND P0, PT, R3, 0x2, PT ;
@!P0 BRA 0x25d0 ;
LDL R7, [R10+0x8] ;
STG.E [R8.64+0x8], R7 ;
IMAD.MOV.U32 R7, RZ, RZ, c[0x0][0x0] ;
IMAD R2, R7, c[0x0][0xc], R2 ;
ISETP.GE.AND P0, PT, R2, c[0x0][0x160], PT ;
@P0 CALL.REL.NOINC 0x2620 ;
BRA 0xd0 ;
EXIT ;
BRA 0x2630;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
```
|
```amdasm
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z8dijkstraiPiS_ ; -- Begin function _Z8dijkstraiPiS_
.globl _Z8dijkstraiPiS_
.p2align 8
.type _Z8dijkstraiPiS_,@function
_Z8dijkstraiPiS_: ; @_Z8dijkstraiPiS_
; %bb.0:
s_clause 0x1
s_load_b32 s5, s[0:1], 0x24
s_load_b32 s4, s[0:1], 0x0
s_add_u32 s2, s0, 24
s_addc_u32 s3, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s7, s5, 0xffff
s_mov_b32 s5, exec_lo
v_mad_u64_u32 v[1:2], null, s15, s7, v[0:1]
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s4, v1
s_cbranch_execz .LBB0_25
; %bb.1: ; %.lr.ph92
s_load_b32 s8, s[2:3], 0x0
s_load_b128 s[0:3], s[0:1], 0x8
v_mul_lo_u32 v2, s4, v1
s_cmp_gt_i32 s4, 0
v_bfrev_b32_e32 v0, -2
v_dual_mov_b32 v5, 0 :: v_dual_mov_b32 v6, 1
s_cselect_b32 s5, -1, 0
s_cmp_gt_i32 s4, 1
; implicit-def: $vgpr7
s_cselect_b32 s6, -1, 0
s_add_i32 s9, s4, -2
s_waitcnt lgkmcnt(0)
s_mul_i32 s7, s8, s7
s_mov_b32 s8, 0
s_mul_i32 s10, s7, s4
.LBB0_2: ; =>This Loop Header: Depth=1
; Child Loop BB0_4 Depth 2
; Child Loop BB0_7 Depth 2
; Child Loop BB0_9 Depth 3
; Child Loop BB0_14 Depth 3
; Child Loop BB0_23 Depth 2
s_and_not1_b32 vcc_lo, exec_lo, s5
s_cbranch_vccnz .LBB0_5
; %bb.3: ; %.lr.ph.preheader
; in Loop: Header=BB0_2 Depth=1
v_dual_mov_b32 v3, 16 :: v_dual_mov_b32 v4, 0x1d0
s_mov_b32 s11, s4
.LBB0_4: ; %.lr.ph
; Parent Loop BB0_2 Depth=1
; => This Inner Loop Header: Depth=2
scratch_store_b32 v3, v0, off
scratch_store_b32 v4, v5, off
v_add_nc_u32_e32 v3, 4, v3
v_add_nc_u32_e32 v4, 4, v4
s_add_i32 s11, s11, -1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s11, 0
s_cbranch_scc0 .LBB0_4
.LBB0_5: ; %._crit_edge
; in Loop: Header=BB0_2 Depth=1
v_lshl_add_u32 v3, v1, 2, 16
s_and_not1_b32 vcc_lo, exec_lo, s6
scratch_store_b32 v3, v5, off
s_cbranch_vccnz .LBB0_21
; %bb.6: ; %.preheader.preheader
; in Loop: Header=BB0_2 Depth=1
s_mov_b32 s11, 0
.LBB0_7: ; %.preheader
; Parent Loop BB0_2 Depth=1
; => This Loop Header: Depth=2
; Child Loop BB0_9 Depth 3
; Child Loop BB0_14 Depth 3
s_and_not1_b32 vcc_lo, exec_lo, s5
s_cbranch_vccnz .LBB0_12
; %bb.8: ; %.lr.ph77.preheader
; in Loop: Header=BB0_7 Depth=2
v_dual_mov_b32 v3, 0x1d0 :: v_dual_mov_b32 v4, 16
v_bfrev_b32_e32 v8, -2
s_mov_b32 s12, 0
.LBB0_9: ; %.lr.ph77
; Parent Loop BB0_2 Depth=1
; Parent Loop BB0_7 Depth=2
; => This Inner Loop Header: Depth=3
scratch_load_b32 v9, v3, off
s_mov_b32 s13, exec_lo
s_waitcnt vmcnt(0)
v_cmpx_eq_u32_e32 0, v9
s_cbranch_execz .LBB0_11
; %bb.10: ; in Loop: Header=BB0_9 Depth=3
scratch_load_b32 v9, v4, off
s_waitcnt vmcnt(0)
v_cmp_gt_i32_e32 vcc_lo, v9, v8
v_min_i32_e32 v8, v9, v8
v_cndmask_b32_e32 v7, s12, v7, vcc_lo
.LBB0_11: ; in Loop: Header=BB0_9 Depth=3
s_or_b32 exec_lo, exec_lo, s13
v_add_nc_u32_e32 v3, 4, v3
v_add_nc_u32_e32 v4, 4, v4
s_add_i32 s12, s12, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s4, s12
s_cbranch_scc0 .LBB0_9
.LBB0_12: ; %._crit_edge78
; in Loop: Header=BB0_7 Depth=2
v_lshl_add_u32 v3, v7, 2, 0x1d0
s_and_not1_b32 vcc_lo, exec_lo, s5
scratch_store_b32 v3, v6, off
s_cbranch_vccnz .LBB0_19
; %bb.13: ; %.lr.ph81
; in Loop: Header=BB0_7 Depth=2
v_mul_lo_u32 v3, v7, s4
v_lshl_add_u32 v8, v7, 2, 16
v_dual_mov_b32 v9, 0x1d0 :: v_dual_mov_b32 v10, 16
s_mov_b32 s12, s4
.LBB0_14: ; Parent Loop BB0_2 Depth=1
; Parent Loop BB0_7 Depth=2
; => This Inner Loop Header: Depth=3
scratch_load_b32 v4, v9, off
s_mov_b32 s13, exec_lo
s_waitcnt vmcnt(0)
v_cmpx_eq_u32_e32 0, v4
s_cbranch_execz .LBB0_18
; %bb.15: ; in Loop: Header=BB0_14 Depth=3
v_ashrrev_i32_e32 v4, 31, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[11:12], 2, v[3:4]
v_add_co_u32 v11, vcc_lo, s2, v11
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v12, vcc_lo, s3, v12, vcc_lo
global_load_b32 v4, v[11:12], off
s_waitcnt vmcnt(0)
v_cmp_ne_u32_e32 vcc_lo, 0, v4
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_18
; %bb.16: ; in Loop: Header=BB0_14 Depth=3
scratch_load_b32 v11, v8, off
s_waitcnt vmcnt(0)
v_cmp_ne_u32_e32 vcc_lo, 0x7fffffff, v11
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_18
; %bb.17: ; in Loop: Header=BB0_14 Depth=3
scratch_load_b32 v12, v10, off
v_add_nc_u32_e32 v4, v11, v4
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_min_i32_e32 v4, v4, v12
scratch_store_b32 v10, v4, off
.LBB0_18: ; in Loop: Header=BB0_14 Depth=3
s_or_b32 exec_lo, exec_lo, s13
v_add_nc_u32_e32 v3, 1, v3
v_add_nc_u32_e32 v9, 4, v9
v_add_nc_u32_e32 v10, 4, v10
s_add_i32 s12, s12, -1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s12, 0
s_cbranch_scc0 .LBB0_14
.LBB0_19: ; %._crit_edge82
; in Loop: Header=BB0_7 Depth=2
s_add_i32 s12, s11, 1
s_cmp_eq_u32 s11, s9
s_cbranch_scc1 .LBB0_21
; %bb.20: ; in Loop: Header=BB0_7 Depth=2
s_mov_b32 s11, s12
s_branch .LBB0_7
.LBB0_21: ; %.preheader72
; in Loop: Header=BB0_2 Depth=1
s_and_not1_b32 vcc_lo, exec_lo, s5
s_cbranch_vccnz .LBB0_24
; %bb.22: ; %.lr.ph87
; in Loop: Header=BB0_2 Depth=1
v_ashrrev_i32_e32 v3, 31, v2
v_mov_b32_e32 v8, 16
s_mov_b32 s11, s4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[2:3]
v_add_co_u32 v3, vcc_lo, s0, v3
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo
.LBB0_23: ; Parent Loop BB0_2 Depth=1
; => This Inner Loop Header: Depth=2
scratch_load_b32 v9, v8, off
v_add_nc_u32_e32 v8, 4, v8
s_add_i32 s11, s11, -1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s11, 0
s_waitcnt vmcnt(0)
global_store_b32 v[3:4], v9, off
v_add_co_u32 v3, vcc_lo, v3, 4
v_add_co_ci_u32_e32 v4, vcc_lo, 0, v4, vcc_lo
s_cbranch_scc0 .LBB0_23
.LBB0_24: ; %._crit_edge88
; in Loop: Header=BB0_2 Depth=1
v_add_nc_u32_e32 v1, s7, v1
v_add_nc_u32_e32 v2, s10, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_le_i32_e32 vcc_lo, s4, v1
s_or_b32 s8, vcc_lo, s8
s_and_not1_b32 exec_lo, exec_lo, s8
s_cbranch_execnz .LBB0_2
.LBB0_25: ; %Flow141
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z8dijkstraiPiS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 912
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 1
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 13
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z8dijkstraiPiS_, .Lfunc_end0-_Z8dijkstraiPiS_
; -- End function
.section .AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 720
; NumSgprs: 18
; NumVgprs: 13
; ScratchSize: 912
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 13
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 1
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object ; @__hip_cuid_
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0 ; 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z8dijkstraiPiS_
.private_segment_fixed_size: 912
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z8dijkstraiPiS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 13
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
```
| 11,360 | 5,095 |
635 |
Convert the following CUDA host assembly code to AMD host assembly:
```cudaasm
.file "tmpxft_0017dd18_00000000-6_main.cudafe1.cpp"
.text
.globl _ZSt21ios_base_library_initv
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z30__device_stub__Z8dijkstraiPiS_iPiS_
.type _Z30__device_stub__Z8dijkstraiPiS_iPiS_, @function
_Z30__device_stub__Z8dijkstraiPiS_iPiS_:
.LFB3694:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movl %edi, 28(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z8dijkstraiPiS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3694:
.size _Z30__device_stub__Z8dijkstraiPiS_iPiS_, .-_Z30__device_stub__Z8dijkstraiPiS_iPiS_
.globl _Z8dijkstraiPiS_
.type _Z8dijkstraiPiS_, @function
_Z8dijkstraiPiS_:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z8dijkstraiPiS_iPiS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _Z8dijkstraiPiS_, .-_Z8dijkstraiPiS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z8dijkstraiPiS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3697:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z8dijkstraiPiS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .text._ZN9__gnu_cxx6__stoaIlicJiEEET0_PFT_PKT1_PPS3_DpT2_EPKcS5_PmS9_,"axG",@progbits,_ZN9__gnu_cxx6__stoaIlicJiEEET0_PFT_PKT1_PPS3_DpT2_EPKcS5_PmS9_,comdat
.weak _ZN9__gnu_cxx6__stoaIlicJiEEET0_PFT_PKT1_PPS3_DpT2_EPKcS5_PmS9_
.type _ZN9__gnu_cxx6__stoaIlicJiEEET0_PFT_PKT1_PPS3_DpT2_EPKcS5_PmS9_, @function
_ZN9__gnu_cxx6__stoaIlicJiEEET0_PFT_PKT1_PPS3_DpT2_EPKcS5_PmS9_:
.LFB3771:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA3771
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $40, %rsp
.cfi_def_cfa_offset 96
movq %rdi, %r13
movq %rsi, 8(%rsp)
movq %rdx, %rbp
movq %rcx, %r12
movl %r8d, %r14d
movq %fs:40, %rax
movq %rax, 24(%rsp)
xorl %eax, %eax
call __errno_location@PLT
movq %rax, %rbx
movl (%rax), %r15d
movl $0, (%rax)
leaq 16(%rsp), %rsi
movl %r14d, %edx
movq %rbp, %rdi
.LEHB0:
call *%r13
movq 16(%rsp), %rcx
cmpq %rbp, %rcx
je .L27
cmpl $34, (%rbx)
je .L16
movl $2147483648, %edx
addq %rax, %rdx
shrq $32, %rdx
jne .L16
testq %r12, %r12
je .L19
subq %rbp, %rcx
movq %rcx, (%r12)
.L19:
cmpl $0, (%rbx)
jne .L13
movl %r15d, (%rbx)
.L13:
movq 24(%rsp), %rdx
subq %fs:40, %rdx
jne .L28
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L27:
.cfi_restore_state
movq 24(%rsp), %rax
subq %fs:40, %rax
jne .L29
movq 8(%rsp), %rdi
call _ZSt24__throw_invalid_argumentPKc@PLT
.L29:
call __stack_chk_fail@PLT
.L16:
movq 24(%rsp), %rax
subq %fs:40, %rax
jne .L30
movq 8(%rsp), %rdi
call _ZSt20__throw_out_of_rangePKc@PLT
.LEHE0:
.L25:
endbr64
movq %rax, %rdi
cmpl $0, (%rbx)
jne .L22
movl %r15d, (%rbx)
.L22:
movq 24(%rsp), %rax
subq %fs:40, %rax
je .L23
call __stack_chk_fail@PLT
.L30:
call __stack_chk_fail@PLT
.L23:
.LEHB1:
call _Unwind_Resume@PLT
.LEHE1:
.L28:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3771:
.globl __gxx_personality_v0
.section .gcc_except_table._ZN9__gnu_cxx6__stoaIlicJiEEET0_PFT_PKT1_PPS3_DpT2_EPKcS5_PmS9_,"aG",@progbits,_ZN9__gnu_cxx6__stoaIlicJiEEET0_PFT_PKT1_PPS3_DpT2_EPKcS5_PmS9_,comdat
.LLSDA3771:
.byte 0xff
.byte 0xff
.byte 0x1
.uleb128 .LLSDACSE3771-.LLSDACSB3771
.LLSDACSB3771:
.uleb128 .LEHB0-.LFB3771
.uleb128 .LEHE0-.LEHB0
.uleb128 .L25-.LFB3771
.uleb128 0
.uleb128 .LEHB1-.LFB3771
.uleb128 .LEHE1-.LEHB1
.uleb128 0
.uleb128 0
.LLSDACSE3771:
.section .text._ZN9__gnu_cxx6__stoaIlicJiEEET0_PFT_PKT1_PPS3_DpT2_EPKcS5_PmS9_,"axG",@progbits,_ZN9__gnu_cxx6__stoaIlicJiEEET0_PFT_PKT1_PPS3_DpT2_EPKcS5_PmS9_,comdat
.size _ZN9__gnu_cxx6__stoaIlicJiEEET0_PFT_PKT1_PPS3_DpT2_EPKcS5_PmS9_, .-_ZN9__gnu_cxx6__stoaIlicJiEEET0_PFT_PKT1_PPS3_DpT2_EPKcS5_PmS9_
.section .rodata._ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "basic_string: construction from null is not valid"
.section .text._ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_,"axG",@progbits,_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC5IS3_EEPKcRKS3_,comdat
.align 2
.weak _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_
.type _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_, @function
_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_:
.LFB3998:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $24, %rsp
.cfi_def_cfa_offset 64
movq %fs:40, %rax
movq %rax, 8(%rsp)
xorl %eax, %eax
leaq 16(%rdi), %r12
movq %r12, (%rdi)
testq %rsi, %rsi
je .L40
movq %rdi, %rbx
movq %rsi, %r13
movq %rsi, %rdi
call strlen@PLT
movq %rax, %rbp
movq %rax, (%rsp)
cmpq $15, %rax
ja .L41
cmpq $1, %rax
jne .L36
movzbl 0(%r13), %eax
movb %al, 16(%rbx)
.L37:
movq (%rsp), %rax
movq %rax, 8(%rbx)
movq (%rbx), %rdx
movb $0, (%rdx,%rax)
movq 8(%rsp), %rax
subq %fs:40, %rax
jne .L42
addq $24, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L40:
.cfi_restore_state
movq 8(%rsp), %rax
subq %fs:40, %rax
jne .L43
leaq .LC1(%rip), %rdi
call _ZSt19__throw_logic_errorPKc@PLT
.L43:
call __stack_chk_fail@PLT
.L41:
movq %rsp, %rsi
movl $0, %edx
movq %rbx, %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_createERmm@PLT
movq %rax, %r12
movq %rax, (%rbx)
movq (%rsp), %rax
movq %rax, 16(%rbx)
.L35:
movq %rbp, %rdx
movq %r13, %rsi
movq %r12, %rdi
call memcpy@PLT
jmp .L37
.L36:
testq %rax, %rax
je .L37
jmp .L35
.L42:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3998:
.size _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_, .-_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_
.weak _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC1IS3_EEPKcRKS3_
.set _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC1IS3_EEPKcRKS3_,_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_
.section .rodata.str1.1
.LC2:
.string "stoi"
.LC3:
.string "------DIJKSTRA-------"
.LC4:
.string " "
.LC6:
.string "Time taken: %.2f microsekon\n"
.text
.globl main
.type main, @function
main:
.LFB3669:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA3669
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $136, %rsp
.cfi_def_cfa_offset 192
movq %rsi, 24(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 68(%rsp), %rdx
movq 8(%rsi), %rsi
leaq 80(%rsp), %rdi
.LEHB2:
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC1IS3_EEPKcRKS3_
.LEHE2:
movl $10, %r8d
movl $0, %ecx
movq 80(%rsp), %rdx
leaq .LC2(%rip), %rsi
movq __isoc23_strtol@GOTPCREL(%rip), %rdi
.LEHB3:
call _ZN9__gnu_cxx6__stoaIlicJiEEET0_PFT_PKT1_PPS3_DpT2_EPKcS5_PmS9_
.LEHE3:
movl %eax, %r12d
leaq 80(%rsp), %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
movl %r12d, %ebx
imull %r12d, %ebx
movslq %ebx, %rbx
salq $2, %rbx
leaq 40(%rsp), %rdi
movl $1, %edx
movq %rbx, %rsi
.LEHB4:
call cudaMallocManaged@PLT
leaq 48(%rsp), %rdi
movl $1, %edx
movq %rbx, %rsi
call cudaMallocManaged@PLT
movl $13517093, %edi
call srand@PLT
testl %r12d, %r12d
jle .L45
movslq %r12d, %r14
leaq 1(%r14), %rax
movq %rax, 8(%rsp)
salq $2, %r14
movl $0, %r15d
movl $0, 4(%rsp)
leal -1(%r12), %eax
movl %eax, 16(%rsp)
jmp .L48
.L46:
movq 48(%rsp), %rax
movl (%rax,%rbx), %edx
movl %edx, (%rax,%rbp)
addq $4, %rbx
addq %r14, %rbp
cmpq %r13, %rbx
je .L69
.L47:
call rand@PLT
movslq %eax, %rdx
imulq $-1307163959, %rdx, %rdx
shrq $32, %rdx
addl %eax, %edx
sarl $4, %edx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
imull $23, %edx, %edx
subl %edx, %eax
movq 48(%rsp), %rdx
movl %eax, (%rdx,%rbx)
movq %rbx, %rax
addq 48(%rsp), %rax
cmpl $0, (%rax)
jne .L46
movl $1, (%rax)
jmp .L46
.L69:
movq 8(%rsp), %rax
addq %rax, %r15
.L48:
leaq 0(,%r15,4), %rbp
movq 48(%rsp), %rax
movl $0, (%rax,%r15,4)
addl $1, 4(%rsp)
movl 4(%rsp), %edi
cmpl %r12d, %edi
je .L45
leaq 4(%rbp), %rbx
addq %r14, %rbp
movl 16(%rsp), %eax
subl %edi, %eax
leaq 2(%r15,%rax), %r13
salq $2, %r13
jmp .L47
.L45:
leaq 68(%rsp), %rdx
movq 24(%rsp), %rax
movq 16(%rax), %rsi
leaq 80(%rsp), %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC1IS3_EEPKcRKS3_
.LEHE4:
movl $10, %r8d
movl $0, %ecx
movq 80(%rsp), %rdx
leaq .LC2(%rip), %rsi
movq __isoc23_strtol@GOTPCREL(%rip), %rdi
.LEHB5:
call _ZN9__gnu_cxx6__stoaIlicJiEEET0_PFT_PKT1_PPS3_DpT2_EPKcS5_PmS9_
.LEHE5:
movl %eax, %ebx
leaq 80(%rsp), %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
leal -1(%r12,%rbx), %eax
cltd
idivl %ebx
movl %eax, %ebp
call clock@PLT
movq %rax, 24(%rsp)
movl %ebx, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl %ebp, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 68(%rsp), %rdx
movl $1, %ecx
movq 56(%rsp), %rdi
movl $1, %esi
.LEHB6:
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L70
.L49:
call cudaDeviceSynchronize@PLT
leaq .LC3(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
testl %r12d, %r12d
jle .L50
movslq %r12d, %rax
salq $2, %rax
movq %rax, 16(%rsp)
movq $0, 8(%rsp)
movl $0, 4(%rsp)
leaq _ZSt4cout(%rip), %r13
leal -1(%r12), %r14d
leaq .LC4(%rip), %r15
jmp .L51
.L70:
movq 48(%rsp), %rdx
movq 40(%rsp), %rsi
movl %r12d, %edi
call _Z30__device_stub__Z8dijkstraiPiS_iPiS_
jmp .L49
.L72:
movl $1, %edx
movq %r15, %rsi
movq %r13, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
.L52:
addl $1, %ebx
addq $4, %rbp
cmpl %r12d, %ebx
je .L71
.L53:
movq 40(%rsp), %rax
movl (%rax,%rbp), %esi
movq %r13, %rdi
call _ZNSolsEi@PLT
cmpl %ebx, %r14d
jne .L72
jmp .L52
.L71:
movq 0(%r13), %rax
movq -24(%rax), %rax
movq 240(%r13,%rax), %rbx
testq %rbx, %rbx
je .L73
cmpb $0, 56(%rbx)
je .L56
movzbl 67(%rbx), %esi
.L57:
movsbl %sil, %esi
movq %r13, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
addl $1, 4(%rsp)
movl 4(%rsp), %eax
movq 16(%rsp), %rsi
addq %rsi, 8(%rsp)
cmpl %r12d, %eax
je .L50
.L51:
movq 8(%rsp), %rbp
movl $0, %ebx
jmp .L53
.L73:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L74
call _ZSt16__throw_bad_castv@PLT
.L74:
call __stack_chk_fail@PLT
.L56:
movq %rbx, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%rbx), %rax
movl $10, %esi
movq %rbx, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L57
.L50:
call clock@PLT
movq 24(%rsp), %rdi
subq %rdi, %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
movsd .LC5(%rip), %xmm1
divsd %xmm1, %xmm0
mulsd %xmm1, %xmm0
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
movq 48(%rsp), %rdi
call cudaFree@PLT
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L75
movl $0, %eax
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L63:
.cfi_restore_state
endbr64
movq %rax, %rbx
leaq 80(%rsp), %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
movq 120(%rsp), %rax
subq %fs:40, %rax
je .L59
call __stack_chk_fail@PLT
.L59:
movq %rbx, %rdi
call _Unwind_Resume@PLT
.L64:
endbr64
movq %rax, %rbx
leaq 80(%rsp), %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
movq 120(%rsp), %rax
subq %fs:40, %rax
je .L61
call __stack_chk_fail@PLT
.L61:
movq %rbx, %rdi
call _Unwind_Resume@PLT
.LEHE6:
.L75:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.section .gcc_except_table,"a",@progbits
.LLSDA3669:
.byte 0xff
.byte 0xff
.byte 0x1
.uleb128 .LLSDACSE3669-.LLSDACSB3669
.LLSDACSB3669:
.uleb128 .LEHB2-.LFB3669
.uleb128 .LEHE2-.LEHB2
.uleb128 0
.uleb128 0
.uleb128 .LEHB3-.LFB3669
.uleb128 .LEHE3-.LEHB3
.uleb128 .L63-.LFB3669
.uleb128 0
.uleb128 .LEHB4-.LFB3669
.uleb128 .LEHE4-.LEHB4
.uleb128 0
.uleb128 0
.uleb128 .LEHB5-.LFB3669
.uleb128 .LEHE5-.LEHB5
.uleb128 .L64-.LFB3669
.uleb128 0
.uleb128 .LEHB6-.LFB3669
.uleb128 .LEHE6-.LEHB6
.uleb128 0
.uleb128 0
.LLSDACSE3669:
.text
.size main, .-main
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC5:
.long 0
.long 1093567616
.hidden DW.ref.__gxx_personality_v0
.weak DW.ref.__gxx_personality_v0
.section .data.rel.local.DW.ref.__gxx_personality_v0,"awG",@progbits,DW.ref.__gxx_personality_v0,comdat
.align 8
.type DW.ref.__gxx_personality_v0, @object
.size DW.ref.__gxx_personality_v0, 8
DW.ref.__gxx_personality_v0:
.quad __gxx_personality_v0
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
```
|
```amdasm
.text
.file "main.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z23__device_stub__dijkstraiPiS_ # -- Begin function _Z23__device_stub__dijkstraiPiS_
.type _Z23__device_stub__dijkstraiPiS_,@function
_Z23__device_stub__dijkstraiPiS_: # @_Z23__device_stub__dijkstraiPiS_
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $112, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 12(%rsp), %rax
movl %edi, (%rax)
leaq 40(%rsp), %rcx
movq %rsi, (%rcx)
leaq 32(%rsp), %rsi
movq %rdx, (%rsi)
leaq 80(%rsp), %rbx
movq %rax, (%rbx)
movq %rcx, 8(%rbx)
movq %rsi, 16(%rbx)
leaq 64(%rsp), %r14
leaq 48(%rsp), %r15
leaq 24(%rsp), %r12
leaq 16(%rsp), %r13
movq %r14, %rdi
movq %r15, %rsi
movq %r12, %rdx
movq %r13, %rcx
callq __hipPopCallConfiguration
movq (%r14), %rsi
movl 8(%r14), %edx
movq (%r15), %rcx
movl 8(%r15), %r8d
movl $_Z8dijkstraiPiS_, %edi
movq %rbx, %r9
pushq (%r13)
.cfi_adjust_cfa_offset 8
pushq (%r12)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $128, %rsp
.cfi_adjust_cfa_offset -128
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z23__device_stub__dijkstraiPiS_, .Lfunc_end0-_Z23__device_stub__dijkstraiPiS_
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI1_0:
.quad 0x412e848000000000 # double 1.0E+6
.text
.globl main
.type main,@function
main: # @main
.Lfunc_begin0:
.cfi_startproc
.cfi_personality 3, __gxx_personality_v0
.cfi_lsda 3, .Lexception0
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $120, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsi, %r15
movq 8(%rsi), %rsi
.Ltmp0:
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rdx
callq _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_
.Ltmp1:
# %bb.1:
movq 56(%rsp), %r12
callq __errno_location
movq %rax, %r14
movl (%rax), %ebp
movl $0, (%rax)
leaq 112(%rsp), %r13
movq %r12, %rdi
movq %r13, %rsi
movl $10, %edx
callq __isoc23_strtol
cmpq %r12, (%r13)
movq %r14, 16(%rsp) # 8-byte Spill
je .LBB1_2
# %bb.9:
movq %rax, %rbx
movslq %ebx, %rax
cmpq %rbx, %rax
jne .LBB1_11
# %bb.10:
movl (%r14), %eax
cmpl $34, %eax
je .LBB1_11
# %bb.13:
movq %r15, 88(%rsp) # 8-byte Spill
testl %eax, %eax
jne .LBB1_15
# %bb.14:
movl %ebp, (%r14)
.LBB1_15:
leaq 72(%rsp), %rax
movq -16(%rax), %rdi
cmpq %rax, %rdi
je .LBB1_17
# %bb.16: # %_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE11_M_is_localEv.exit.i.i
callq _ZdlPv
.LBB1_17: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev.exit
movl %ebx, %r12d
imull %r12d, %r12d
andl $-3, %r12d
shlq $2, %r12
leaq 40(%rsp), %rdi
movq %r12, %rsi
movl $1, %edx
callq hipMallocManaged
leaq 32(%rsp), %rdi
movq %r12, %rsi
movl $1, %edx
callq hipMallocManaged
movl $13517093, %edi # imm = 0xCE4125
callq srand
testl %ebx, %ebx
movq %rbx, 48(%rsp) # 8-byte Spill
jle .LBB1_21
# %bb.18: # %.lr.ph87.preheader
movl %ebx, %r14d
leaq 1(%r14), %rax
movq %rax, 96(%rsp) # 8-byte Spill
movl $1, %ebp
xorl %eax, %eax
movq %rax, 24(%rsp) # 8-byte Spill
movq %r14, %r15
xorl %ecx, %ecx
.LBB1_19: # %.lr.ph87
# =>This Loop Header: Depth=1
# Child Loop BB1_28 Depth 2
movl %ecx, %eax
imull %ebx, %eax
cltq
shlq $2, %rax
addq 32(%rsp), %rax
movl $0, (%rax,%rcx,4)
incq %rcx
movq %rcx, 104(%rsp) # 8-byte Spill
cmpq %r14, %rcx
jae .LBB1_20
# %bb.27: # %.lr.ph.preheader
# in Loop: Header=BB1_19 Depth=1
movl 24(%rsp), %ebx # 4-byte Reload
addq %rbp, %rbx
movq %r14, %r12
movq %r15, %r13
.LBB1_28: # %.lr.ph
# Parent Loop BB1_19 Depth=1
# => This Inner Loop Header: Depth=2
callq rand
cltq
imulq $-1307163959, %rax, %rcx # imm = 0xB21642C9
shrq $32, %rcx
addl %eax, %ecx
movl %ecx, %edx
shrl $31, %edx
sarl $4, %ecx
addl %edx, %ecx
leal (%rcx,%rcx,2), %edx
shll $3, %edx
subl %edx, %ecx
leal (%rax,%rcx), %edx
movq 32(%rsp), %rsi
cmpl $1, %edx
adcl %eax, %ecx
movl %ecx, (%rsi,%rbx,4)
movl %ecx, (%rsi,%r13,4)
incq %rbx
addq %r14, %r13
decq %r12
cmpq %r12, %rbp
jne .LBB1_28
.LBB1_20: # %.loopexit
# in Loop: Header=BB1_19 Depth=1
incq %rbp
movq 48(%rsp), %rbx # 8-byte Reload
movq 24(%rsp), %rax # 8-byte Reload
addl %ebx, %eax
movq %rax, 24(%rsp) # 8-byte Spill
addq 96(%rsp), %r15 # 8-byte Folded Reload
movq 104(%rsp), %rcx # 8-byte Reload
cmpq %r14, %rcx
jne .LBB1_19
.LBB1_21: # %._crit_edge
movq 88(%rsp), %rax # 8-byte Reload
movq 16(%rax), %rsi
.Ltmp3:
leaq 56(%rsp), %rdi
leaq 15(%rsp), %rdx
callq _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_
.Ltmp4:
# %bb.22:
movq 56(%rsp), %r12
movq 16(%rsp), %r14 # 8-byte Reload
movl (%r14), %ebp
movl $0, (%r14)
leaq 112(%rsp), %r13
movq %r12, %rdi
movq %r13, %rsi
movl $10, %edx
callq __isoc23_strtol
cmpq %r12, (%r13)
je .LBB1_23
# %bb.33:
movq %rax, %r15
movabsq $-4294967296, %rax # imm = 0xFFFFFFFF00000000
leaq -2147483648(%r15), %rcx
cmpq %rax, %rcx
jb .LBB1_35
# %bb.34:
movl (%r14), %eax
cmpl $34, %eax
je .LBB1_35
# %bb.37:
testl %eax, %eax
jne .LBB1_39
# %bb.38:
movl %ebp, (%r14)
.LBB1_39:
movq 56(%rsp), %rdi
leaq 72(%rsp), %rax
cmpq %rax, %rdi
je .LBB1_41
# %bb.40: # %_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE11_M_is_localEv.exit.i.i76
callq _ZdlPv
.LBB1_41: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev.exit78
leal (%rbx,%r15), %eax
decl %eax
cltd
idivl %r15d
movl %eax, %r12d
callq clock
movq %rax, 24(%rsp) # 8-byte Spill
btsq $32, %r12
movl %r15d, %edx
btsq $32, %rdx
movq %r12, %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_43
# %bb.42:
movq 40(%rsp), %rsi
movq 32(%rsp), %rdx
movl %ebx, %edi
callq _Z23__device_stub__dijkstraiPiS_
.LBB1_43:
callq hipDeviceSynchronize
movl $_ZSt4cout, %r14d
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $21, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rdi
addq %r14, %rdi
movl $10, %esi
callq _ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
testl %ebx, %ebx
jle .LBB1_50
# %bb.44: # %.preheader.lr.ph
leal -1(%rbx), %eax
movl %eax, %r12d
movl %ebx, %r13d
xorl %ebp, %ebp
xorl %r14d, %r14d
.LBB1_45: # %.lr.ph89
# =>This Loop Header: Depth=1
# Child Loop BB1_46 Depth 2
movl %ebp, %ebx
shlq $2, %rbx
xorl %r15d, %r15d
.LBB1_46: # Parent Loop BB1_45 Depth=1
# => This Inner Loop Header: Depth=2
movq 40(%rsp), %rax
addq %rbx, %rax
movl (%rax,%r15,4), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
cmpq %r15, %r12
je .LBB1_48
# %bb.47: # in Loop: Header=BB1_46 Depth=2
movl $_ZSt4cout, %edi
movl $.L.str.1, %esi
movl $1, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.LBB1_48: # in Loop: Header=BB1_46 Depth=2
incq %r15
cmpq %r15, %r13
jne .LBB1_46
# %bb.49: # %._crit_edge90
# in Loop: Header=BB1_45 Depth=1
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rdi
movl $_ZSt4cout, %eax
addq %rax, %rdi
movl $10, %esi
callq _ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
incq %r14
addl 48(%rsp), %ebp # 4-byte Folded Reload
cmpq %r13, %r14
jne .LBB1_45
.LBB1_50: # %._crit_edge92
callq clock
subq 24(%rsp), %rax # 8-byte Folded Reload
cvtsi2sd %rax, %xmm0
movsd .LCPI1_0(%rip), %xmm1 # xmm1 = mem[0],zero
divsd %xmm1, %xmm0
mulsd %xmm1, %xmm0
movl $.L.str.2, %edi
movb $1, %al
callq printf
movq 40(%rsp), %rdi
callq hipFree
movq 32(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $120, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB1_2:
.cfi_def_cfa_offset 176
.Ltmp13:
movl $.L.str.3, %edi
callq _ZSt24__throw_invalid_argumentPKc
.Ltmp14:
# %bb.3:
.LBB1_11: # %.critedge.i.i
.Ltmp11:
movl $.L.str.3, %edi
callq _ZSt20__throw_out_of_rangePKc
.Ltmp12:
# %bb.12:
.LBB1_23:
.Ltmp8:
movl $.L.str.3, %edi
callq _ZSt24__throw_invalid_argumentPKc
.Ltmp9:
# %bb.29:
.LBB1_35: # %.critedge.i.i71
.Ltmp6:
movl $.L.str.3, %edi
callq _ZSt20__throw_out_of_rangePKc
.Ltmp7:
# %bb.36:
.LBB1_51:
.Ltmp5:
jmp .LBB1_25
.LBB1_24:
.Ltmp2:
.LBB1_25:
movq %rax, %rbx
jmp .LBB1_26
.LBB1_30:
.Ltmp10:
movq %rax, %rbx
movq 16(%rsp), %rax # 8-byte Reload
cmpl $0, (%rax)
jne .LBB1_32
# %bb.31:
movq 16(%rsp), %rax # 8-byte Reload
movl %ebp, (%rax)
.LBB1_32: # %_ZZN9__gnu_cxx6__stoaIlicJiEEET0_PFT_PKT1_PPS3_DpT2_EPKcS5_PmS9_EN11_Save_errnoD2Ev.exit.i.i72
movq 56(%rsp), %rdi
leaq 72(%rsp), %rax
jmp .LBB1_7
.LBB1_4:
.Ltmp15:
movq %rax, %rbx
movq 16(%rsp), %rax # 8-byte Reload
cmpl $0, (%rax)
jne .LBB1_6
# %bb.5:
movq 16(%rsp), %rax # 8-byte Reload
movl %ebp, (%rax)
.LBB1_6: # %_ZZN9__gnu_cxx6__stoaIlicJiEEET0_PFT_PKT1_PPS3_DpT2_EPKcS5_PmS9_EN11_Save_errnoD2Ev.exit.i.i
leaq 72(%rsp), %rax
movq -16(%rax), %rdi
.LBB1_7: # %_ZZN9__gnu_cxx6__stoaIlicJiEEET0_PFT_PKT1_PPS3_DpT2_EPKcS5_PmS9_EN11_Save_errnoD2Ev.exit.i.i
cmpq %rax, %rdi
je .LBB1_26
# %bb.8: # %_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE11_M_is_localEv.exit.i.i67
callq _ZdlPv
.LBB1_26:
movq %rbx, %rdi
callq _Unwind_Resume@PLT
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
.section .gcc_except_table,"a",@progbits
.p2align 2, 0x0
GCC_except_table1:
.Lexception0:
.byte 255 # @LPStart Encoding = omit
.byte 255 # @TType Encoding = omit
.byte 1 # Call site Encoding = uleb128
.uleb128 .Lcst_end0-.Lcst_begin0
.Lcst_begin0:
.uleb128 .Ltmp0-.Lfunc_begin0 # >> Call Site 1 <<
.uleb128 .Ltmp1-.Ltmp0 # Call between .Ltmp0 and .Ltmp1
.uleb128 .Ltmp2-.Lfunc_begin0 # jumps to .Ltmp2
.byte 0 # On action: cleanup
.uleb128 .Ltmp1-.Lfunc_begin0 # >> Call Site 2 <<
.uleb128 .Ltmp3-.Ltmp1 # Call between .Ltmp1 and .Ltmp3
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp3-.Lfunc_begin0 # >> Call Site 3 <<
.uleb128 .Ltmp4-.Ltmp3 # Call between .Ltmp3 and .Ltmp4
.uleb128 .Ltmp5-.Lfunc_begin0 # jumps to .Ltmp5
.byte 0 # On action: cleanup
.uleb128 .Ltmp4-.Lfunc_begin0 # >> Call Site 4 <<
.uleb128 .Ltmp13-.Ltmp4 # Call between .Ltmp4 and .Ltmp13
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp13-.Lfunc_begin0 # >> Call Site 5 <<
.uleb128 .Ltmp12-.Ltmp13 # Call between .Ltmp13 and .Ltmp12
.uleb128 .Ltmp15-.Lfunc_begin0 # jumps to .Ltmp15
.byte 0 # On action: cleanup
.uleb128 .Ltmp8-.Lfunc_begin0 # >> Call Site 6 <<
.uleb128 .Ltmp7-.Ltmp8 # Call between .Ltmp8 and .Ltmp7
.uleb128 .Ltmp10-.Lfunc_begin0 # jumps to .Ltmp10
.byte 0 # On action: cleanup
.uleb128 .Ltmp7-.Lfunc_begin0 # >> Call Site 7 <<
.uleb128 .Lfunc_end1-.Ltmp7 # Call between .Ltmp7 and .Lfunc_end1
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.Lcst_end0:
.p2align 2, 0x0
# -- End function
.section .text._ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_,"axG",@progbits,_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_,comdat
.weak _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_ # -- Begin function _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_
.p2align 1, 0x90
.type _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_,@function
_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_: # @_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
pushq %rax
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
leaq 16(%rdi), %rax
movq %rax, (%rdi)
testq %rsi, %rsi
je .LBB2_1
# %bb.2:
movq %rsi, %rbx
movq %rdi, %r14
movq %rsi, %rdi
callq strlen
leaq (%rax,%rbx), %rdx
movq %r14, %rdi
movq %rbx, %rsi
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
jmp _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_M_constructIPKcEEvT_S8_St20forward_iterator_tag # TAILCALL
.LBB2_1:
.cfi_def_cfa_offset 32
movl $.L.str.4, %edi
callq _ZSt19__throw_logic_errorPKc
.Lfunc_end2:
.size _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_, .Lfunc_end2-_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_
.cfi_endproc
# -- End function
.section .text._ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_M_constructIPKcEEvT_S8_St20forward_iterator_tag,"axG",@progbits,_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_M_constructIPKcEEvT_S8_St20forward_iterator_tag,comdat
.weak _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_M_constructIPKcEEvT_S8_St20forward_iterator_tag # -- Begin function _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_M_constructIPKcEEvT_S8_St20forward_iterator_tag
.p2align 1, 0x90
.type _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_M_constructIPKcEEvT_S8_St20forward_iterator_tag,@function
_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_M_constructIPKcEEvT_S8_St20forward_iterator_tag: # @_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_M_constructIPKcEEvT_S8_St20forward_iterator_tag
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
pushq %rax
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rdx, %r14
movq %rsi, %r15
movq %rdi, %rbx
subq %rsi, %r14
movq %r14, (%rsp)
cmpq $15, %r14
jbe .LBB3_1
# %bb.2:
movq %rsp, %r12
movq %rbx, %rdi
movq %r12, %rsi
xorl %edx, %edx
callq _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_createERmm
movq %rax, (%rbx)
movq (%r12), %rcx
movq %rcx, 16(%rbx)
jmp .LBB3_3
.LBB3_1: # %._crit_edge
movq (%rbx), %rax
.LBB3_3:
testq %r14, %r14
je .LBB3_7
# %bb.4:
cmpq $1, %r14
jne .LBB3_6
# %bb.5:
movb (%r15), %cl
movb %cl, (%rax)
jmp .LBB3_7
.LBB3_6:
movq %rax, %rdi
movq %r15, %rsi
movq %r14, %rdx
callq memcpy@PLT
.LBB3_7: # %_ZZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_M_constructIPKcEEvT_S8_St20forward_iterator_tagEN6_GuardD2Ev.exit
movq (%rsp), %rax
movq %rax, 8(%rbx)
movq (%rbx), %rcx
movb $0, (%rcx,%rax)
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_M_constructIPKcEEvT_S8_St20forward_iterator_tag, .Lfunc_end3-_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_M_constructIPKcEEvT_S8_St20forward_iterator_tag
.cfi_endproc
# -- End function
.text
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, %rdi
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8dijkstraiPiS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z8dijkstraiPiS_,@object # @_Z8dijkstraiPiS_
.section .rodata,"a",@progbits
.globl _Z8dijkstraiPiS_
.p2align 3, 0x0
_Z8dijkstraiPiS_:
.quad _Z23__device_stub__dijkstraiPiS_
.size _Z8dijkstraiPiS_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "------DIJKSTRA-------"
.size .L.str, 22
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz " "
.size .L.str.1, 2
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Time taken: %.2f microsekon\n"
.size .L.str.2, 29
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "stoi"
.size .L.str.3, 5
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "basic_string: construction from null is not valid"
.size .L.str.4, 50
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z8dijkstraiPiS_"
.size .L__unnamed_1, 17
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z23__device_stub__dijkstraiPiS_
.addrsig_sym __gxx_personality_v0
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Unwind_Resume
.addrsig_sym _Z8dijkstraiPiS_
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
```
| 9,046 | 9,852 |
638 |
Convert the following CUDA device assembly code to AMD device assembly:
```cudaasm
code for sm_80
Function : _Z6warmupPfS_S_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
MOV R1, c[0x0][0x28] ;
S2R R6, SR_CTAID.X ;
S2R R3, SR_TID.X ;
IMAD R6, R6, c[0x0][0x0], R3 ;
IADD3 R4, R6, c[0x0][0x17c], RZ ;
ISETP.GE.U32.AND P0, PT, R4, c[0x0][0x178], PT ;
@P0 EXIT ;
HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ;
ULDC.64 UR4, c[0x0][0x118] ;
IMAD.WIDE.U32 R2, R4, R7, c[0x0][0x160] ;
IMAD.WIDE.U32 R4, R4, R7.reuse, c[0x0][0x168] ;
LDG.E R3, [R2.64] ;
LDG.E R4, [R4.64] ;
IMAD.WIDE.U32 R6, R6, R7, c[0x0][0x170] ;
FADD R9, R4, R3 ;
STG.E [R6.64], R9 ;
EXIT ;
BRA 0x110;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
```
|
```amdasm
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6warmupPfS_S_ii ; -- Begin function _Z6warmupPfS_S_ii
.globl _Z6warmupPfS_S_ii
.p2align 8
.type _Z6warmupPfS_S_ii,@function
_Z6warmupPfS_S_ii: ; @_Z6warmupPfS_S_ii
; %bb.0:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x2c
s_load_b64 s[2:3], s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
v_add_nc_u32_e32 v3, s3, v1
s_delay_alu instid0(VALU_DEP_1)
v_cmp_gt_u32_e32 vcc_lo, s2, v3
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_2
; %bb.1:
s_load_b128 s[4:7], s[0:1], 0x0
v_mov_b32_e32 v2, 0
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mov_b32_e32 v4, v2
v_lshlrev_b64 v[0:1], 2, v[1:2]
v_lshlrev_b64 v[3:4], 2, v[3:4]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v5, vcc_lo, s4, v3
v_add_co_ci_u32_e32 v6, vcc_lo, s5, v4, vcc_lo
v_add_co_u32 v3, vcc_lo, s6, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s7, v4, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v5, v[5:6], off
global_load_b32 v3, v[3:4], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_f32_e32 v2, v5, v3
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6warmupPfS_S_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6warmupPfS_S_ii, .Lfunc_end0-_Z6warmupPfS_S_ii
; -- End function
.section .AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 196
; NumSgprs: 18
; NumVgprs: 7
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 7
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object ; @__hip_cuid_
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0 ; 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6warmupPfS_S_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z6warmupPfS_S_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
```
| 434 | 2,706 |
639 |
Convert the following CUDA host assembly code to AMD host assembly:
```cudaasm
.file "tmpxft_0006f3ec_00000000-6_warmup.cudafe1.cpp"
.text
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2059:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2059:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z31__device_stub__Z6warmupPfS_S_iiPfS_S_ii
.type _Z31__device_stub__Z6warmupPfS_S_iiPfS_S_ii, @function
_Z31__device_stub__Z6warmupPfS_S_iiPfS_S_ii:
.LFB2081:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z6warmupPfS_S_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2081:
.size _Z31__device_stub__Z6warmupPfS_S_iiPfS_S_ii, .-_Z31__device_stub__Z6warmupPfS_S_iiPfS_S_ii
.globl _Z6warmupPfS_S_ii
.type _Z6warmupPfS_S_ii, @function
_Z6warmupPfS_S_ii:
.LFB2082:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z31__device_stub__Z6warmupPfS_S_iiPfS_S_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2082:
.size _Z6warmupPfS_S_ii, .-_Z6warmupPfS_S_ii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z6warmupPfS_S_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z6warmupPfS_S_ii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
```
|
```amdasm
.text
.file "warmup.hip"
.globl _Z21__device_stub__warmupPfS_S_ii # -- Begin function _Z21__device_stub__warmupPfS_S_ii
.type _Z21__device_stub__warmupPfS_S_ii,@function
_Z21__device_stub__warmupPfS_S_ii: # @_Z21__device_stub__warmupPfS_S_ii
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $128, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 40(%rsp), %rax
movq %rdi, (%rax)
leaq 32(%rsp), %rdi
movq %rsi, (%rdi)
leaq 24(%rsp), %rsi
movq %rdx, (%rsi)
leaq 4(%rsp), %rdx
movl %ecx, (%rdx)
movq %rsp, %rcx
movl %r8d, (%rcx)
leaq 80(%rsp), %rbx
movq %rax, (%rbx)
movq %rdi, 8(%rbx)
movq %rsi, 16(%rbx)
movq %rdx, 24(%rbx)
movq %rcx, 32(%rbx)
leaq 64(%rsp), %r14
leaq 48(%rsp), %r15
leaq 16(%rsp), %r12
leaq 8(%rsp), %r13
movq %r14, %rdi
movq %r15, %rsi
movq %r12, %rdx
movq %r13, %rcx
callq __hipPopCallConfiguration
movq (%r14), %rsi
movl 8(%r14), %edx
movq (%r15), %rcx
movl 8(%r15), %r8d
movl $_Z6warmupPfS_S_ii, %edi
movq %rbx, %r9
pushq (%r13)
.cfi_adjust_cfa_offset 8
pushq (%r12)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $144, %rsp
.cfi_adjust_cfa_offset -144
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z21__device_stub__warmupPfS_S_ii, .Lfunc_end0-_Z21__device_stub__warmupPfS_S_ii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, %rdi
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6warmupPfS_S_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6warmupPfS_S_ii,@object # @_Z6warmupPfS_S_ii
.section .rodata,"a",@progbits
.globl _Z6warmupPfS_S_ii
.p2align 3, 0x0
_Z6warmupPfS_S_ii:
.quad _Z21__device_stub__warmupPfS_S_ii
.size _Z6warmupPfS_S_ii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z6warmupPfS_S_ii"
.size .L__unnamed_1, 18
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__warmupPfS_S_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6warmupPfS_S_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
```
| 1,943 | 2,128 |
640 |
Convert the following CUDA device assembly code to AMD device assembly:
```cudaasm
code for sm_80
Function : _Z10add_arraysPPfS_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ;
S2R R0, SR_CTAID.X ;
S2R R3, SR_TID.X ;
IMAD R0, R0, c[0x0][0x0], R3 ;
ISETP.GE.AND P0, PT, R0, c[0x0][0x170], PT ;
@P0 EXIT ;
IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x174] ;
ULDC.64 UR8, c[0x0][0x118] ;
SHF.R.S32.HI R3, RZ, 0x1f, R0 ;
IMAD.MOV.U32 R5, RZ, RZ, RZ ;
ISETP.GE.AND P0, PT, R4, 0x1, PT ;
@!P0 BRA 0xd20 ;
IADD3 R2, R4.reuse, -0x1, RZ ;
UMOV UR4, URZ ;
LOP3.LUT R4, R4, 0x3, RZ, 0xc0, !PT ;
IMAD.MOV.U32 R5, RZ, RZ, RZ ;
ISETP.GE.U32.AND P0, PT, R2, 0x3, PT ;
@!P0 BRA 0xc00 ;
IADD3 R8, -R4, c[0x0][0x174], RZ ;
UMOV UR4, URZ ;
HFMA2.MMA R5, -RZ, RZ, 0, 0 ;
SHF.L.U64.HI R6, R0.reuse, 0x2, R3 ;
IMAD.SHL.U32 R7, R0, 0x4, RZ ;
ISETP.GT.AND P0, PT, R8, RZ, PT ;
IMAD.MOV.U32 R12, RZ, RZ, c[0x0][0x160] ;
IMAD.MOV.U32 R13, RZ, RZ, c[0x0][0x164] ;
@!P0 BRA 0xa60 ;
ISETP.GT.AND P1, PT, R8, 0xc, PT ;
PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ;
@!P1 BRA 0x750 ;
PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ;
LDG.E.64 R10, [R12.64] ;
LDG.E.64 R24, [R12.64+0x8] ;
LDG.E.64 R22, [R12.64+0x10] ;
LDG.E.64 R20, [R12.64+0x18] ;
LDG.E.64 R14, [R12.64+0x28] ;
LDG.E.64 R18, [R12.64+0x30] ;
LDG.E.64 R16, [R12.64+0x38] ;
IADD3 R26, P1, R10, R7, RZ ;
IMAD.X R27, R11, 0x1, R6, P1 ;
LDG.E.64 R10, [R12.64+0x20] ;
LDG.E R26, [R26.64] ;
IADD3 R28, P1, R24, R7, RZ ;
IMAD.X R29, R25, 0x1, R6, P1 ;
IADD3 R24, P1, R22, R7, RZ ;
IADD3.X R25, R23, R6, RZ, P1, !PT ;
LDG.E R2, [R28.64] ;
IADD3 R20, P1, R20, R7, RZ ;
LDG.E R24, [R24.64] ;
IMAD.X R21, R21, 0x1, R6, P1 ;
IADD3 R14, P1, R14, R7, RZ ;
LDG.E R23, [R20.64] ;
IMAD.X R15, R15, 0x1, R6, P1 ;
IADD3 R28, P1, R18, R7, RZ ;
LDG.E R21, [R14.64] ;
IMAD.X R29, R19, 0x1, R6, P1 ;
LDG.E R20, [R28.64] ;
LDG.E.64 R14, [R12.64+0x58] ;
IADD3 R10, P2, R10, R7, RZ ;
FADD R5, R26, R5 ;
IMAD.X R11, R11, 0x1, R6, P2 ;
LDG.E.64 R26, [R12.64+0x40] ;
IADD3 R18, P2, R16, R7, RZ ;
LDG.E R22, [R10.64] ;
IADD3.X R19, R17, R6, RZ, P2, !PT ;
LDG.E.64 R16, [R12.64+0x50] ;
LDG.E R19, [R18.64] ;
LDG.E.64 R10, [R12.64+0x48] ;
IADD3 R28, P2, R14, R7, RZ ;
IMAD.X R29, R15, 0x1, R6, P2 ;
LDG.E.64 R14, [R12.64+0x68] ;
LDG.E R9, [R28.64] ;
IADD3 R26, P1, R26, R7, RZ ;
IMAD.X R27, R27, 0x1, R6, P1 ;
LDG.E R18, [R26.64] ;
IADD3 R10, P1, R10, R7, RZ ;
IMAD.X R11, R11, 0x1, R6, P1 ;
IADD3 R26, P1, R16, R7, RZ ;
IMAD.X R27, R17, 0x1, R6, P1 ;
LDG.E R11, [R10.64] ;
LDG.E.64 R16, [R12.64+0x60] ;
LDG.E R10, [R26.64] ;
IADD3 R26, P2, R14, R7, RZ ;
IMAD.X R27, R15, 0x1, R6, P2 ;
LDG.E.64 R14, [R12.64+0x70] ;
LDG.E R26, [R26.64] ;
IADD3 R28, P1, R16, R7, RZ ;
IADD3.X R29, R17, R6, RZ, P1, !PT ;
LDG.E.64 R16, [R12.64+0x78] ;
LDG.E R25, [R28.64] ;
IADD3 R14, P1, R14, R7, RZ ;
IMAD.X R15, R15, 0x1, R6, P1 ;
LDG.E R14, [R14.64] ;
FADD R5, R5, R2 ;
FADD R24, R5, R24 ;
FADD R23, R24, R23 ;
IADD3 R16, P1, R16, R7, RZ ;
IMAD.X R17, R17, 0x1, R6, P1 ;
LDG.E R16, [R16.64] ;
FADD R22, R23, R22 ;
FADD R21, R22, R21 ;
FADD R20, R21, R20 ;
FADD R19, R20, R19 ;
FADD R18, R19, R18 ;
FADD R11, R18, R11 ;
IADD3 R8, R8, -0x10, RZ ;
FADD R10, R11, R10 ;
ISETP.GT.AND P1, PT, R8, 0xc, PT ;
FADD R10, R10, R9 ;
FADD R25, R10, R25 ;
IADD3 R12, P2, R12, 0x80, RZ ;
FADD R25, R25, R26 ;
UIADD3 UR4, UR4, 0x10, URZ ;
FADD R25, R25, R14 ;
IMAD.X R13, RZ, RZ, R13, P2 ;
FADD R5, R25, R16 ;
@P1 BRA 0x1f0 ;
ISETP.GT.AND P1, PT, R8, 0x4, PT ;
@!P1 BRA 0xa40 ;
LDG.E.64 R26, [R12.64] ;
LDG.E.64 R18, [R12.64+0x8] ;
LDG.E.64 R20, [R12.64+0x10] ;
LDG.E.64 R22, [R12.64+0x18] ;
LDG.E.64 R24, [R12.64+0x20] ;
LDG.E.64 R10, [R12.64+0x28] ;
LDG.E.64 R14, [R12.64+0x30] ;
LDG.E.64 R16, [R12.64+0x38] ;
IADD3 R26, P0, R26, R7, RZ ;
IADD3.X R27, R27, R6, RZ, P0, !PT ;
IADD3 R18, P0, R18, R7, RZ ;
LDG.E R2, [R26.64] ;
IMAD.X R19, R19, 0x1, R6, P0 ;
IADD3 R20, P0, R20, R7, RZ ;
LDG.E R18, [R18.64] ;
IMAD.X R21, R21, 0x1, R6, P0 ;
IADD3 R22, P0, R22, R7, RZ ;
LDG.E R20, [R20.64] ;
IMAD.X R23, R23, 0x1, R6.reuse, P0 ;
IADD3 R24, P0, R24, R7.reuse, RZ ;
IADD3 R10, P1, R10, R7.reuse, RZ ;
LDG.E R22, [R22.64] ;
IMAD.X R25, R25, 0x1, R6, P0 ;
IADD3 R14, P0, R14, R7, RZ ;
IADD3.X R11, R11, R6, RZ, P1, !PT ;
LDG.E R24, [R24.64] ;
IMAD.X R15, R15, 0x1, R6.reuse, P0 ;
IADD3 R16, P0, R16, R7, RZ ;
LDG.E R10, [R10.64] ;
IMAD.X R17, R17, 0x1, R6, P0 ;
LDG.E R14, [R14.64] ;
LDG.E R16, [R16.64] ;
IADD3 R12, P1, R12, 0x40, RZ ;
PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ;
IADD3 R8, R8, -0x8, RZ ;
IMAD.X R13, RZ, RZ, R13, P1 ;
UIADD3 UR4, UR4, 0x8, URZ ;
FADD R5, R5, R2 ;
FADD R5, R5, R18 ;
FADD R5, R5, R20 ;
FADD R5, R5, R22 ;
FADD R5, R5, R24 ;
FADD R5, R5, R10 ;
FADD R5, R5, R14 ;
FADD R5, R5, R16 ;
ISETP.NE.OR P0, PT, R8, RZ, P0 ;
@!P0 BRA 0xc00 ;
LDG.E.64 R14, [R12.64] ;
LDG.E.64 R18, [R12.64+0x8] ;
LDG.E.64 R16, [R12.64+0x10] ;
LDG.E.64 R10, [R12.64+0x18] ;
IADD3 R20, P0, R14, R7, RZ ;
IMAD.X R21, R15, 0x1, R6.reuse, P0 ;
IADD3 R14, P0, R18, R7.reuse, RZ ;
IADD3 R16, P1, R16, R7.reuse, RZ ;
IADD3.X R15, R19, R6, RZ, P0, !PT ;
LDG.E R20, [R20.64] ;
IADD3 R10, P0, R10, R7, RZ ;
IMAD.X R17, R17, 0x1, R6.reuse, P1 ;
LDG.E R14, [R14.64] ;
IMAD.X R11, R11, 0x1, R6, P0 ;
LDG.E R16, [R16.64] ;
LDG.E R10, [R10.64] ;
IADD3 R8, R8, -0x4, RZ ;
UIADD3 UR4, UR4, 0x4, URZ ;
IADD3 R12, P1, R12, 0x20, RZ ;
ISETP.NE.AND P0, PT, R8, RZ, PT ;
IMAD.X R13, RZ, RZ, R13, P1 ;
FADD R5, R20, R5 ;
FADD R5, R5, R14 ;
FADD R5, R5, R16 ;
FADD R5, R5, R10 ;
@P0 BRA 0xa60 ;
ISETP.NE.AND P0, PT, R4, RZ, PT ;
@!P0 BRA 0xd20 ;
SHF.L.U64.HI R11, R0, 0x2, R3 ;
UMOV UR5, 0x8 ;
ULDC.64 UR6, c[0x0][0x160] ;
UIMAD.WIDE UR4, UR4, UR5, UR6 ;
MOV R6, UR4 ;
IMAD.U32 R7, RZ, RZ, UR5 ;
LDG.E.64 R6, [R6.64] ;
IADD3 R4, R4, -0x1, RZ ;
LEA R8, P0, R0, R6, 0x2 ;
IMAD.X R9, R7, 0x1, R11, P0 ;
LDG.E R8, [R8.64] ;
ISETP.NE.AND P0, PT, R4, RZ, PT ;
UIADD3 UR4, UP0, UR4, 0x8, URZ ;
UIADD3.X UR5, URZ, UR5, URZ, UP0, !UPT ;
FADD R5, R8, R5 ;
@P0 BRA 0xc60 ;
LEA R2, P0, R0, c[0x0][0x168], 0x2 ;
LEA.HI.X R3, R0, c[0x0][0x16c], R3, 0x2, P0 ;
STG.E [R2.64], R5 ;
EXIT ;
BRA 0xd60;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
```
|
```amdasm
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10add_arraysPPfS_ii ; -- Begin function _Z10add_arraysPPfS_ii
.globl _Z10add_arraysPPfS_ii
.p2align 8
.type _Z10add_arraysPPfS_ii,@function
_Z10add_arraysPPfS_ii: ; @_Z10add_arraysPPfS_ii
; %bb.0:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b64 s[4:5], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s4, v1
s_cbranch_execz .LBB0_4
; %bb.1:
s_load_b128 s[0:3], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_cmp_lt_i32 s5, 1
s_delay_alu instid0(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
v_mov_b32_e32 v2, 0
s_cbranch_scc1 .LBB0_3
.LBB0_2: ; %.lr.ph.i
; =>This Inner Loop Header: Depth=1
s_waitcnt lgkmcnt(0)
s_load_b64 s[6:7], s[0:1], 0x0
s_add_i32 s5, s5, -1
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
s_cmp_lg_u32 s5, 0
s_waitcnt lgkmcnt(0)
v_add_co_u32 v3, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v4, vcc_lo, s7, v1, vcc_lo
global_load_b32 v3, v[3:4], off
s_waitcnt vmcnt(0)
v_add_f32_e32 v2, v2, v3
s_cbranch_scc1 .LBB0_2
.LBB0_3: ; %_Z15add_elements_atmPPfi.exit
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_store_b32 v[0:1], v2, off
.LBB0_4:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10add_arraysPPfS_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10add_arraysPPfS_ii, .Lfunc_end0-_Z10add_arraysPPfS_ii
; -- End function
.section .AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 200
; NumSgprs: 18
; NumVgprs: 5
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 5
; Occupancy: 16
; WaveLimiterHint : 1
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object ; @__hip_cuid_
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0 ; 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10add_arraysPPfS_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z10add_arraysPPfS_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
```
| 4,128 | 2,695 |
641 |
Convert the following CUDA host assembly code to AMD host assembly:
```cudaasm
.file "tmpxft_00061f27_00000000-6_add_arrays.cudafe1.cpp"
.text
.globl _ZSt21ios_base_library_initv
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3675:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3675:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string ", line "
.LC1:
.string ": "
.LC2:
.string " ("
.LC3:
.string ")"
.text
.globl _Z10cuda_checkNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEi
.type _Z10cuda_checkNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEi, @function
_Z10cuda_checkNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEi:
.LFB3669:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
movq %rdi, %rbp
movl %esi, %r12d
call cudaGetLastError@PLT
testl %eax, %eax
jne .L6
popq %rbx
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L6:
.cfi_restore_state
movl %eax, %ebx
leaq _ZSt4cout(%rip), %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq %rax, %rdi
movq 8(%rbp), %rdx
movq 0(%rbp), %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq %rax, %rdi
leaq .LC0(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl %r12d, %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
leaq .LC1(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rbp
movl %ebx, %edi
call cudaGetErrorString@PLT
movq %rax, %rsi
movq %rbp, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
leaq .LC2(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl %ebx, %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
leaq .LC3(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $1, %edi
call exit@PLT
.cfi_endproc
.LFE3669:
.size _Z10cuda_checkNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEi, .-_Z10cuda_checkNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEi
.globl _Z15add_elements_atmPPfi
.type _Z15add_elements_atmPPfi, @function
_Z15add_elements_atmPPfi:
.LFB3670:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE3670:
.size _Z15add_elements_atmPPfi, .-_Z15add_elements_atmPPfi
.globl _Z35__device_stub__Z10add_arraysPPfS_iiPPfS_ii
.type _Z35__device_stub__Z10add_arraysPPfS_iiPPfS_ii, @function
_Z35__device_stub__Z10add_arraysPPfS_iiPPfS_ii:
.LFB3697:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L13
.L9:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L14
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L13:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z10add_arraysPPfS_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L9
.L14:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3697:
.size _Z35__device_stub__Z10add_arraysPPfS_iiPPfS_ii, .-_Z35__device_stub__Z10add_arraysPPfS_iiPPfS_ii
.globl _Z10add_arraysPPfS_ii
.type _Z10add_arraysPPfS_ii, @function
_Z10add_arraysPPfS_ii:
.LFB3698:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z10add_arraysPPfS_iiPPfS_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3698:
.size _Z10add_arraysPPfS_ii, .-_Z10add_arraysPPfS_ii
.section .rodata.str1.1
.LC4:
.string "_Z10add_arraysPPfS_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3700:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z10add_arraysPPfS_ii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3700:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .text._ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_M_constructIPKcEEvT_S8_St20forward_iterator_tag,"axG",@progbits,_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_M_constructIPKcEEvT_S8_St20forward_iterator_tag,comdat
.align 2
.weak _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_M_constructIPKcEEvT_S8_St20forward_iterator_tag
.type _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_M_constructIPKcEEvT_S8_St20forward_iterator_tag, @function
_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_M_constructIPKcEEvT_S8_St20forward_iterator_tag:
.LFB4086:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $16, %rsp
.cfi_def_cfa_offset 48
movq %rdi, %rbx
movq %rsi, %r12
movq %fs:40, %rax
movq %rax, 8(%rsp)
xorl %eax, %eax
subq %rsi, %rdx
movq %rdx, %rbp
movq %rdx, (%rsp)
cmpq $15, %rdx
ja .L26
movq (%rdi), %rdi
cmpq $1, %rdx
jne .L22
movzbl (%rsi), %eax
movb %al, (%rdi)
.L23:
movq (%rsp), %rax
movq %rax, 8(%rbx)
movq (%rbx), %rdx
movb $0, (%rdx,%rax)
movq 8(%rsp), %rax
subq %fs:40, %rax
jne .L27
addq $16, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L26:
.cfi_restore_state
movq %rsp, %rsi
movl $0, %edx
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_createERmm@PLT
movq %rax, %rdi
movq %rax, (%rbx)
movq (%rsp), %rax
movq %rax, 16(%rbx)
.L21:
movq %rbp, %rdx
movq %r12, %rsi
call memcpy@PLT
jmp .L23
.L22:
testq %rdx, %rdx
je .L23
jmp .L21
.L27:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4086:
.size _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_M_constructIPKcEEvT_S8_St20forward_iterator_tag, .-_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_M_constructIPKcEEvT_S8_St20forward_iterator_tag
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC5:
.string "/home/ubuntu/Datasets/stackv2/train-structured/shiviser/TUM_GPUComputerVision/master/cuda_team_warp64/exercises/2/add_arrays.cu"
.text
.globl _Z17add_arrays_callerPPfii
.type _Z17add_arrays_callerPPfii, @function
_Z17add_arrays_callerPPfii:
.LFB3671:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA3671
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
movq %rsp, %rbp
.cfi_def_cfa_register 6
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $168, %rsp
.cfi_offset 15, -24
.cfi_offset 14, -32
.cfi_offset 13, -40
.cfi_offset 12, -48
.cfi_offset 3, -56
movq %rdi, -176(%rbp)
movl %esi, -184(%rbp)
movl %edx, -180(%rbp)
movq %fs:40, %rax
movq %rax, -56(%rbp)
xorl %eax, %eax
movl $1, -116(%rbp)
movl $1, -112(%rbp)
leal 511(%rsi), %eax
shrl $9, %eax
movl %eax, -108(%rbp)
movl $1, -104(%rbp)
movl $1, -100(%rbp)
movslq %edx, %rax
movq %rax, -200(%rbp)
salq $3, %rax
movq %rax, -168(%rbp)
addq $15, %rax
movq %rax, %rcx
andq $-16, %rcx
andq $-4096, %rax
movq %rsp, %rdx
subq %rax, %rdx
.L29:
cmpq %rdx, %rsp
je .L30
subq $4096, %rsp
orq $0, 4088(%rsp)
jmp .L29
.L30:
movq %rcx, %rax
andl $4095, %eax
subq %rax, %rsp
testq %rax, %rax
je .L31
orq $0, -8(%rsp,%rax)
.L31:
movq %rsp, %rax
movq %rax, -192(%rbp)
movl -184(%rbp), %ecx
leal 0(,%rcx,4), %edx
movl %edx, -204(%rbp)
cmpl $0, -180(%rbp)
jle .L32
movq %rax, %rbx
movq -176(%rbp), %r13
movq -168(%rbp), %rcx
addq %rcx, %rax
movq %rax, -160(%rbp)
movslq %edx, %r14
leaq -96(%rbp), %r12
leaq .LC5(%rip), %r15
jmp .L35
.L77:
movq -96(%rbp), %rdi
leaq -80(%rbp), %rax
cmpq %rax, %rdi
je .L33
movq -80(%rbp), %rax
leaq 1(%rax), %rsi
call _ZdlPvm@PLT
.L33:
movq 0(%r13), %rsi
movq -152(%rbp), %rax
movq (%rax), %rdi
movl $1, %ecx
movq %r14, %rdx
.LEHB0:
call cudaMemcpy@PLT
leaq -80(%rbp), %rax
movq %rax, -96(%rbp)
leaq 127+.LC5(%rip), %rdx
movq %r15, %rsi
movq %r12, %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_M_constructIPKcEEvT_S8_St20forward_iterator_tag
.LEHE0:
movl $75, %esi
movq %r12, %rdi
.LEHB1:
call _Z10cuda_checkNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEi
.LEHE1:
movq -96(%rbp), %rdi
leaq -80(%rbp), %rax
cmpq %rax, %rdi
je .L34
movq -80(%rbp), %rax
leaq 1(%rax), %rsi
call _ZdlPvm@PLT
.L34:
addq $8, %rbx
addq $8, %r13
movq -160(%rbp), %rax
cmpq %rax, %rbx
je .L32
.L35:
movq %rbx, -152(%rbp)
movq %r14, %rsi
movq %rbx, %rdi
.LEHB2:
call cudaMalloc@PLT
leaq -80(%rbp), %rax
movq %rax, -96(%rbp)
leaq 127+.LC5(%rip), %rdx
movq %r15, %rsi
movq %r12, %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_M_constructIPKcEEvT_S8_St20forward_iterator_tag
.LEHE2:
movl $73, %esi
movq %r12, %rdi
.LEHB3:
call _Z10cuda_checkNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEi
.LEHE3:
jmp .L77
.L32:
leaq -136(%rbp), %rdi
movq -168(%rbp), %rsi
.LEHB4:
call cudaMalloc@PLT
leaq -96(%rbp), %rbx
leaq -80(%rbp), %rax
movq %rax, -96(%rbp)
leaq 127+.LC5(%rip), %rdx
leaq -127(%rdx), %rsi
movq %rbx, %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_M_constructIPKcEEvT_S8_St20forward_iterator_tag
.LEHE4:
movl $81, %esi
movq %rbx, %rdi
.LEHB5:
call _Z10cuda_checkNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEi
.LEHE5:
movq -96(%rbp), %rdi
leaq -80(%rbp), %rax
cmpq %rax, %rdi
je .L36
movq -80(%rbp), %rax
leaq 1(%rax), %rsi
call _ZdlPvm@PLT
.L36:
movl $1, %ecx
movq -168(%rbp), %rdx
movq -192(%rbp), %rsi
movq -136(%rbp), %rdi
.LEHB6:
call cudaMemcpy@PLT
leaq -96(%rbp), %rbx
leaq -80(%rbp), %rax
movq %rax, -96(%rbp)
leaq 127+.LC5(%rip), %rdx
leaq -127(%rdx), %rsi
movq %rbx, %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_M_constructIPKcEEvT_S8_St20forward_iterator_tag
.LEHE6:
movl $83, %esi
movq %rbx, %rdi
.LEHB7:
call _Z10cuda_checkNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEi
.LEHE7:
movq -96(%rbp), %rdi
leaq -80(%rbp), %rax
cmpq %rax, %rdi
je .L37
movq -80(%rbp), %rax
leaq 1(%rax), %rsi
call _ZdlPvm@PLT
.L37:
movslq -204(%rbp), %rbx
leaq 0(,%rbx,4), %rsi
leaq -128(%rbp), %rdi
.LEHB8:
call cudaMalloc@PLT
leaq -96(%rbp), %r12
leaq -80(%rbp), %rax
movq %rax, -96(%rbp)
leaq 127+.LC5(%rip), %rdx
leaq -127(%rdx), %rsi
movq %r12, %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_M_constructIPKcEEvT_S8_St20forward_iterator_tag
.LEHE8:
movl $88, %esi
movq %r12, %rdi
.LEHB9:
call _Z10cuda_checkNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEi
.LEHE9:
movq -96(%rbp), %rdi
leaq -80(%rbp), %rax
cmpq %rax, %rdi
je .L38
movq -80(%rbp), %rax
leaq 1(%rax), %rsi
call _ZdlPvm@PLT
.L38:
movl $512, -120(%rbp)
movl -112(%rbp), %ecx
movl $0, %r9d
movl $0, %r8d
movq -120(%rbp), %rdx
movq -108(%rbp), %rdi
movl -100(%rbp), %esi
.LEHB10:
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L78
.L39:
call cudaDeviceSynchronize@PLT
leaq -96(%rbp), %r12
leaq -80(%rbp), %rax
movq %rax, -96(%rbp)
leaq 127+.LC5(%rip), %rdx
leaq -127(%rdx), %rsi
movq %r12, %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_M_constructIPKcEEvT_S8_St20forward_iterator_tag
.LEHE10:
movl $95, %esi
movq %r12, %rdi
.LEHB11:
call _Z10cuda_checkNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEi
.LEHE11:
jmp .L79
.L78:
movl -180(%rbp), %ecx
movl -184(%rbp), %edx
movq -128(%rbp), %rsi
movq -136(%rbp), %rdi
.LEHB12:
call _Z35__device_stub__Z10add_arraysPPfS_iiPPfS_ii
jmp .L39
.L79:
movq -96(%rbp), %rdi
leaq -80(%rbp), %rax
cmpq %rax, %rdi
je .L40
movq -80(%rbp), %rax
leaq 1(%rax), %rsi
call _ZdlPvm@PLT
.L40:
movq -176(%rbp), %rax
movq -200(%rbp), %rcx
movq (%rax,%rcx,8), %rdi
movl $2, %ecx
movq %rbx, %rdx
movq -128(%rbp), %rsi
call cudaMemcpy@PLT
leaq -96(%rbp), %rbx
leaq -80(%rbp), %rax
movq %rax, -96(%rbp)
leaq 127+.LC5(%rip), %rdx
leaq -127(%rdx), %rsi
movq %rbx, %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_M_constructIPKcEEvT_S8_St20forward_iterator_tag
.LEHE12:
movl $99, %esi
movq %rbx, %rdi
.LEHB13:
call _Z10cuda_checkNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEi
.LEHE13:
movq -96(%rbp), %rdi
leaq -80(%rbp), %rax
cmpq %rax, %rdi
je .L41
movq -80(%rbp), %rax
leaq 1(%rax), %rsi
call _ZdlPvm@PLT
.L41:
cmpl $0, -180(%rbp)
jle .L42
movq -192(%rbp), %r14
movq %r14, %rbx
movq -168(%rbp), %rax
addq %rax, %r14
leaq -96(%rbp), %r13
leaq -80(%rbp), %r12
leaq 127+.LC5(%rip), %r15
jmp .L44
.L80:
movq -96(%rbp), %rdi
cmpq %r12, %rdi
je .L43
movq -80(%rbp), %rax
leaq 1(%rax), %rsi
call _ZdlPvm@PLT
.L43:
addq $8, %rbx
cmpq %r14, %rbx
je .L42
.L44:
movq (%rbx), %rdi
.LEHB14:
call cudaFree@PLT
movq %r12, -96(%rbp)
movq %r15, %rdx
leaq -127(%r15), %rsi
movq %r13, %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_M_constructIPKcEEvT_S8_St20forward_iterator_tag
.LEHE14:
movl $104, %esi
movq %r13, %rdi
.LEHB15:
call _Z10cuda_checkNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEi
.LEHE15:
jmp .L80
.L42:
movq -128(%rbp), %rdi
.LEHB16:
call cudaFree@PLT
leaq -96(%rbp), %rbx
leaq -80(%rbp), %rax
movq %rax, -96(%rbp)
leaq 127+.LC5(%rip), %rdx
leaq -127(%rdx), %rsi
movq %rbx, %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_M_constructIPKcEEvT_S8_St20forward_iterator_tag
.LEHE16:
movl $107, %esi
movq %rbx, %rdi
.LEHB17:
call _Z10cuda_checkNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEi
.LEHE17:
movq -96(%rbp), %rdi
leaq -80(%rbp), %rax
cmpq %rax, %rdi
je .L28
movq -80(%rbp), %rax
leaq 1(%rax), %rsi
call _ZdlPvm@PLT
.L28:
movq -56(%rbp), %rax
subq %fs:40, %rax
jne .L81
leaq -40(%rbp), %rsp
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
popq %rbp
.cfi_remember_state
.cfi_def_cfa 7, 8
ret
.L65:
.cfi_restore_state
endbr64
movq %rax, %rbx
leaq -96(%rbp), %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
movq -56(%rbp), %rax
subq %fs:40, %rax
je .L47
call __stack_chk_fail@PLT
.L47:
movq %rbx, %rdi
.LEHB18:
call _Unwind_Resume@PLT
.L66:
endbr64
movq %rax, %rbx
leaq -96(%rbp), %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
movq -56(%rbp), %rax
subq %fs:40, %rax
je .L49
call __stack_chk_fail@PLT
.L49:
movq %rbx, %rdi
call _Unwind_Resume@PLT
.L67:
endbr64
movq %rax, %rbx
leaq -96(%rbp), %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
movq -56(%rbp), %rax
subq %fs:40, %rax
je .L51
call __stack_chk_fail@PLT
.L51:
movq %rbx, %rdi
call _Unwind_Resume@PLT
.L68:
endbr64
movq %rax, %rbx
leaq -96(%rbp), %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
movq -56(%rbp), %rax
subq %fs:40, %rax
je .L53
call __stack_chk_fail@PLT
.L53:
movq %rbx, %rdi
call _Unwind_Resume@PLT
.L69:
endbr64
movq %rax, %rbx
leaq -96(%rbp), %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
movq -56(%rbp), %rax
subq %fs:40, %rax
je .L55
call __stack_chk_fail@PLT
.L55:
movq %rbx, %rdi
call _Unwind_Resume@PLT
.L70:
endbr64
movq %rax, %rbx
leaq -96(%rbp), %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
movq -56(%rbp), %rax
subq %fs:40, %rax
je .L57
call __stack_chk_fail@PLT
.L57:
movq %rbx, %rdi
call _Unwind_Resume@PLT
.L71:
endbr64
movq %rax, %rbx
leaq -96(%rbp), %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
movq -56(%rbp), %rax
subq %fs:40, %rax
je .L59
call __stack_chk_fail@PLT
.L59:
movq %rbx, %rdi
call _Unwind_Resume@PLT
.L72:
endbr64
movq %rax, %rbx
leaq -96(%rbp), %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
movq -56(%rbp), %rax
subq %fs:40, %rax
je .L61
call __stack_chk_fail@PLT
.L61:
movq %rbx, %rdi
call _Unwind_Resume@PLT
.L73:
endbr64
movq %rax, %rbx
leaq -96(%rbp), %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
movq -56(%rbp), %rax
subq %fs:40, %rax
je .L63
call __stack_chk_fail@PLT
.L63:
movq %rbx, %rdi
call _Unwind_Resume@PLT
.LEHE18:
.L81:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3671:
.globl __gxx_personality_v0
.section .gcc_except_table,"a",@progbits
.LLSDA3671:
.byte 0xff
.byte 0xff
.byte 0x1
.uleb128 .LLSDACSE3671-.LLSDACSB3671
.LLSDACSB3671:
.uleb128 .LEHB0-.LFB3671
.uleb128 .LEHE0-.LEHB0
.uleb128 0
.uleb128 0
.uleb128 .LEHB1-.LFB3671
.uleb128 .LEHE1-.LEHB1
.uleb128 .L66-.LFB3671
.uleb128 0
.uleb128 .LEHB2-.LFB3671
.uleb128 .LEHE2-.LEHB2
.uleb128 0
.uleb128 0
.uleb128 .LEHB3-.LFB3671
.uleb128 .LEHE3-.LEHB3
.uleb128 .L65-.LFB3671
.uleb128 0
.uleb128 .LEHB4-.LFB3671
.uleb128 .LEHE4-.LEHB4
.uleb128 0
.uleb128 0
.uleb128 .LEHB5-.LFB3671
.uleb128 .LEHE5-.LEHB5
.uleb128 .L67-.LFB3671
.uleb128 0
.uleb128 .LEHB6-.LFB3671
.uleb128 .LEHE6-.LEHB6
.uleb128 0
.uleb128 0
.uleb128 .LEHB7-.LFB3671
.uleb128 .LEHE7-.LEHB7
.uleb128 .L68-.LFB3671
.uleb128 0
.uleb128 .LEHB8-.LFB3671
.uleb128 .LEHE8-.LEHB8
.uleb128 0
.uleb128 0
.uleb128 .LEHB9-.LFB3671
.uleb128 .LEHE9-.LEHB9
.uleb128 .L69-.LFB3671
.uleb128 0
.uleb128 .LEHB10-.LFB3671
.uleb128 .LEHE10-.LEHB10
.uleb128 0
.uleb128 0
.uleb128 .LEHB11-.LFB3671
.uleb128 .LEHE11-.LEHB11
.uleb128 .L70-.LFB3671
.uleb128 0
.uleb128 .LEHB12-.LFB3671
.uleb128 .LEHE12-.LEHB12
.uleb128 0
.uleb128 0
.uleb128 .LEHB13-.LFB3671
.uleb128 .LEHE13-.LEHB13
.uleb128 .L71-.LFB3671
.uleb128 0
.uleb128 .LEHB14-.LFB3671
.uleb128 .LEHE14-.LEHB14
.uleb128 0
.uleb128 0
.uleb128 .LEHB15-.LFB3671
.uleb128 .LEHE15-.LEHB15
.uleb128 .L72-.LFB3671
.uleb128 0
.uleb128 .LEHB16-.LFB3671
.uleb128 .LEHE16-.LEHB16
.uleb128 0
.uleb128 0
.uleb128 .LEHB17-.LFB3671
.uleb128 .LEHE17-.LEHB17
.uleb128 .L73-.LFB3671
.uleb128 0
.uleb128 .LEHB18-.LFB3671
.uleb128 .LEHE18-.LEHB18
.uleb128 0
.uleb128 0
.LLSDACSE3671:
.text
.size _Z17add_arrays_callerPPfii, .-_Z17add_arrays_callerPPfii
.section .rodata.str1.1
.LC7:
.string "CPU:"
.LC8:
.string " + "
.LC9:
.string " = "
.LC10:
.string "GPU:"
.text
.globl main
.type main, @function
main:
.LFB3672:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $40, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 24(%rsp)
xorl %eax, %eax
movl $80, %edi
call _Znam@PLT
movq %rax, %r15
movl $80, %edi
call _Znam@PLT
movq %rax, %r14
movl $80, %edi
call _Znam@PLT
movq %rax, %r13
movl $0, %eax
.L83:
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movss %xmm0, (%r15,%rax,4)
movslq %eax, %rdx
imulq $1717986919, %rdx, %rdx
sarq $33, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
leal (%rdx,%rdx,4), %ecx
movl %eax, %edx
subl %ecx, %edx
addl $1, %edx
pxor %xmm0, %xmm0
cvtsi2ssl %edx, %xmm0
movss %xmm0, (%r14,%rax,4)
movl $0x00000000, 0(%r13,%rax,4)
addq $1, %rax
cmpq $20, %rax
jne .L83
movl $0, %eax
.L84:
movss (%r15,%rax), %xmm0
addss (%r14,%rax), %xmm0
movss %xmm0, 0(%r13,%rax)
addq $4, %rax
cmpq $80, %rax
jne .L84
leaq .LC7(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $0, %ebx
jmp .L89
.L105:
movq 24(%rsp), %rax
subq %fs:40, %rax
jne .L103
call _ZSt16__throw_bad_castv@PLT
.L103:
call __stack_chk_fail@PLT
.L87:
movq %r12, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r12), %rax
movl $10, %esi
movq %r12, %rdi
call *48(%rax)
movl %eax, %esi
.L88:
movsbl %sil, %esi
movq %rbp, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
addq $1, %rbx
cmpq $20, %rbx
je .L104
.L89:
movl %ebx, %esi
leaq _ZSt4cout(%rip), %rdi
call _ZNSolsEi@PLT
movq %rax, %rbp
movl $2, %edx
leaq .LC1(%rip), %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
pxor %xmm0, %xmm0
cvtss2sd (%r15,%rbx,4), %xmm0
movq %rbp, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rbp
movl $3, %edx
leaq .LC8(%rip), %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
pxor %xmm0, %xmm0
cvtss2sd (%r14,%rbx,4), %xmm0
movq %rbp, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rbp
movl $3, %edx
leaq .LC9(%rip), %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
pxor %xmm0, %xmm0
cvtss2sd 0(%r13,%rbx,4), %xmm0
movq %rbp, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rbp
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbp,%rax), %r12
testq %r12, %r12
je .L105
cmpb $0, 56(%r12)
je .L87
movzbl 67(%r12), %esi
jmp .L88
.L104:
leaq _ZSt4cout(%rip), %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq %r13, %rax
leaq 80(%r13), %rdx
.L90:
movl $0x00000000, (%rax)
addq $4, %rax
cmpq %rdx, %rax
jne .L90
movq %r15, (%rsp)
movq %r14, 8(%rsp)
movq %r13, 16(%rsp)
movq %rsp, %rdi
movl $2, %edx
movl $20, %esi
call _Z17add_arrays_callerPPfii
leaq .LC10(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $0, %ebx
jmp .L95
.L108:
movq 24(%rsp), %rax
subq %fs:40, %rax
jne .L106
call _ZSt16__throw_bad_castv@PLT
.L106:
call __stack_chk_fail@PLT
.L93:
movq %r12, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r12), %rax
movl $10, %esi
movq %r12, %rdi
call *48(%rax)
movl %eax, %esi
.L94:
movsbl %sil, %esi
movq %rbp, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
addq $1, %rbx
cmpq $20, %rbx
je .L107
.L95:
movl %ebx, %esi
leaq _ZSt4cout(%rip), %rdi
call _ZNSolsEi@PLT
movq %rax, %rbp
movl $2, %edx
leaq .LC1(%rip), %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
pxor %xmm0, %xmm0
cvtss2sd (%r15,%rbx,4), %xmm0
movq %rbp, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rbp
movl $3, %edx
leaq .LC8(%rip), %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
pxor %xmm0, %xmm0
cvtss2sd (%r14,%rbx,4), %xmm0
movq %rbp, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rbp
movl $3, %edx
leaq .LC9(%rip), %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
pxor %xmm0, %xmm0
cvtss2sd 0(%r13,%rbx,4), %xmm0
movq %rbp, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rbp
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbp,%rax), %r12
testq %r12, %r12
je .L108
cmpb $0, 56(%r12)
je .L93
movzbl 67(%r12), %esi
jmp .L94
.L107:
leaq _ZSt4cout(%rip), %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq %r15, %rdi
call _ZdaPv@PLT
movq %r14, %rdi
call _ZdaPv@PLT
movq %r13, %rdi
call _ZdaPv@PLT
movq 24(%rsp), %rax
subq %fs:40, %rax
jne .L109
movl $0, %eax
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L109:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3672:
.size main, .-main
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.hidden DW.ref.__gxx_personality_v0
.weak DW.ref.__gxx_personality_v0
.section .data.rel.local.DW.ref.__gxx_personality_v0,"awG",@progbits,DW.ref.__gxx_personality_v0,comdat
.align 8
.type DW.ref.__gxx_personality_v0, @object
.size DW.ref.__gxx_personality_v0, 8
DW.ref.__gxx_personality_v0:
.quad __gxx_personality_v0
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
```
|
```amdasm
.text
.file "add_arrays.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z10cuda_checkNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEi # -- Begin function _Z10cuda_checkNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEi
.type _Z10cuda_checkNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEi,@function
_Z10cuda_checkNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEi: # @_Z10cuda_checkNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEi
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %rbp, -16
movl %esi, %ebp
movq %rdi, %r14
callq hipGetLastError
testl %eax, %eax
jne .LBB0_2
# %bb.1:
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB0_2:
.cfi_def_cfa_offset 32
movl %eax, %ebx
movl $_ZSt4cout, %edi
callq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_
movq %rax, %rdi
movq %r14, %rsi
callq _ZStlsIcSt11char_traitsIcESaIcEERSt13basic_ostreamIT_T0_ES7_RKNSt7__cxx1112basic_stringIS4_S5_T1_EE
movl $.L.str, %esi
movq %rax, %rdi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movq %rax, %rdi
movl %ebp, %esi
callq _ZNSolsEi
movl $.L.str.1, %esi
movq %rax, %rdi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movq %rax, %r14
movl %ebx, %edi
callq hipGetErrorString
movq %r14, %rdi
movq %rax, %rsi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movl $.L.str.2, %esi
movq %rax, %rdi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movq %rax, %rdi
movl %ebx, %esi
callq _ZNSolsEi
movl $.L.str.3, %esi
movq %rax, %rdi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movq %rax, %rdi
callq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_
movl $1, %edi
callq exit
.Lfunc_end0:
.size _Z10cuda_checkNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEi, .Lfunc_end0-_Z10cuda_checkNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEi
.cfi_endproc
# -- End function
.globl _Z25__device_stub__add_arraysPPfS_ii # -- Begin function _Z25__device_stub__add_arraysPPfS_ii
.type _Z25__device_stub__add_arraysPPfS_ii,@function
_Z25__device_stub__add_arraysPPfS_ii: # @_Z25__device_stub__add_arraysPPfS_ii
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $112, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 40(%rsp), %rax
movq %rdi, (%rax)
leaq 32(%rsp), %rdi
movq %rsi, (%rdi)
leaq 12(%rsp), %rsi
movl %edx, (%rsi)
leaq 8(%rsp), %rdx
movl %ecx, (%rdx)
leaq 80(%rsp), %rbx
movq %rax, (%rbx)
movq %rdi, 8(%rbx)
movq %rsi, 16(%rbx)
movq %rdx, 24(%rbx)
leaq 64(%rsp), %r14
leaq 48(%rsp), %r15
leaq 24(%rsp), %r12
leaq 16(%rsp), %r13
movq %r14, %rdi
movq %r15, %rsi
movq %r12, %rdx
movq %r13, %rcx
callq __hipPopCallConfiguration
movq (%r14), %rsi
movl 8(%r14), %edx
movq (%r15), %rcx
movl 8(%r15), %r8d
movl $_Z10add_arraysPPfS_ii, %edi
movq %rbx, %r9
pushq (%r13)
.cfi_adjust_cfa_offset 8
pushq (%r12)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $128, %rsp
.cfi_adjust_cfa_offset -128
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z25__device_stub__add_arraysPPfS_ii, .Lfunc_end1-_Z25__device_stub__add_arraysPPfS_ii
.cfi_endproc
# -- End function
.globl _Z17add_arrays_callerPPfii # -- Begin function _Z17add_arrays_callerPPfii
.type _Z17add_arrays_callerPPfii,@function
_Z17add_arrays_callerPPfii: # @_Z17add_arrays_callerPPfii
.Lfunc_begin0:
.cfi_startproc
.cfi_personality 3, __gxx_personality_v0
.cfi_lsda 3, .Lexception0
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset %rbp, -16
movq %rsp, %rbp
.cfi_def_cfa_register %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $360, %rsp # imm = 0x168
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
# kill: def $esi killed $esi def $rsi
movq %rdi, -88(%rbp) # 8-byte Spill
movl %edx, %eax
movq %rsp, %rcx
movq %rax, -80(%rbp) # 8-byte Spill
leaq 15(,%rax,8), %rax
andq $-16, %rax
subq %rax, %rcx
movq %rcx, -64(%rbp) # 8-byte Spill
movq %rcx, %rsp
movq %rsi, -104(%rbp) # 8-byte Spill
leal (,%rsi,4), %eax
cltq
movq %rax, -56(%rbp) # 8-byte Spill
movl %edx, -44(%rbp) # 4-byte Spill
testl %edx, %edx
jle .LBB2_9
# %bb.1: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_.exit69.lr.ph
leaq -352(%rbp), %r13
movq -80(%rbp), %rax # 8-byte Reload
leaq (,%rax,8), %rax
movq %rax, -112(%rbp) # 8-byte Spill
xorl %r12d, %r12d
.LBB2_2: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_.exit69
# =>This Inner Loop Header: Depth=1
movq -64(%rbp), %rax # 8-byte Reload
leaq (%rax,%r12), %r15
movq %r15, %rdi
movq -56(%rbp), %rsi # 8-byte Reload
callq hipMalloc
leaq -384(%rbp), %rbx
movq %rbx, -400(%rbp)
movl $.L.str.4, %esi
movl $.L.str.4+138, %edx
leaq -400(%rbp), %r14
movq %r14, %rdi
callq _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_M_constructIPKcEEvT_S8_St20forward_iterator_tag
.Ltmp0:
movq %r14, %rdi
movl $73, %esi
callq _Z10cuda_checkNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEi
.Ltmp1:
# %bb.3: # in Loop: Header=BB2_2 Depth=1
movq -400(%rbp), %rdi
cmpq %rbx, %rdi
je .LBB2_5
# %bb.4: # %_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE11_M_is_localEv.exit.i.i
# in Loop: Header=BB2_2 Depth=1
callq _ZdlPv
.LBB2_5: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev.exit
# in Loop: Header=BB2_2 Depth=1
movq (%r15), %rdi
movq -88(%rbp), %rax # 8-byte Reload
movq (%rax,%r12), %rsi
movq -56(%rbp), %rdx # 8-byte Reload
movl $1, %ecx
callq hipMemcpy
movq %r13, -368(%rbp)
movl $.L.str.4, %esi
movl $.L.str.4+138, %edx
leaq -368(%rbp), %r14
movq %r14, %rdi
callq _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_M_constructIPKcEEvT_S8_St20forward_iterator_tag
.Ltmp3:
movq %r14, %rdi
movl $75, %esi
callq _Z10cuda_checkNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEi
.Ltmp4:
# %bb.6: # in Loop: Header=BB2_2 Depth=1
movq -368(%rbp), %rdi
cmpq %r13, %rdi
je .LBB2_8
# %bb.7: # %_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE11_M_is_localEv.exit.i.i71
# in Loop: Header=BB2_2 Depth=1
callq _ZdlPv
.LBB2_8: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev.exit73
# in Loop: Header=BB2_2 Depth=1
addq $8, %r12
cmpq %r12, -112(%rbp) # 8-byte Folded Reload
jne .LBB2_2
.LBB2_9: # %._crit_edge
movslq -44(%rbp), %r13 # 4-byte Folded Reload
leaq (,%r13,8), %r14
leaq -96(%rbp), %rdi
movq %r14, %rsi
callq hipMalloc
leaq -320(%rbp), %rbx
movq %rbx, -16(%rbx)
.Ltmp6:
leaq -336(%rbp), %rdi
movl $.L.str.4, %esi
movl $.L.str.4+138, %edx
callq _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_M_constructIPKcEEvT_S8_St20forward_iterator_tag
.Ltmp7:
# %bb.10: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_.exit
.Ltmp9:
leaq -336(%rbp), %rdi
movl $81, %esi
callq _Z10cuda_checkNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEi
.Ltmp10:
# %bb.11:
movq -336(%rbp), %rdi
cmpq %rbx, %rdi
je .LBB2_13
# %bb.12: # %_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE11_M_is_localEv.exit.i.i80
callq _ZdlPv
.LBB2_13: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev.exit82
movq -96(%rbp), %rdi
movq -64(%rbp), %rsi # 8-byte Reload
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
leaq -288(%rbp), %rbx
movq %rbx, -16(%rbx)
.Ltmp12:
leaq -304(%rbp), %rdi
movl $.L.str.4, %esi
movl $.L.str.4+138, %edx
callq _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_M_constructIPKcEEvT_S8_St20forward_iterator_tag
.Ltmp13:
movq -104(%rbp), %r12 # 8-byte Reload
# %bb.14: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_.exit83
.Ltmp15:
leaq -304(%rbp), %rdi
movl $83, %esi
callq _Z10cuda_checkNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEi
.Ltmp16:
# %bb.15:
movq -304(%rbp), %rdi
cmpq %rbx, %rdi
je .LBB2_17
# %bb.16: # %_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE11_M_is_localEv.exit.i.i84
callq _ZdlPv
.LBB2_17: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev.exit86
movq -56(%rbp), %rax # 8-byte Reload
leaq (,%rax,4), %rsi
leaq -72(%rbp), %rdi
callq hipMalloc
leaq -256(%rbp), %rbx
movq %rbx, -16(%rbx)
.Ltmp18:
leaq -272(%rbp), %rdi
movl $.L.str.4, %esi
movl $.L.str.4+138, %edx
callq _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_M_constructIPKcEEvT_S8_St20forward_iterator_tag
.Ltmp19:
# %bb.18: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_.exit87
.Ltmp21:
leaq -272(%rbp), %rdi
movl $88, %esi
callq _Z10cuda_checkNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEi
.Ltmp22:
# %bb.19:
leal 511(%r12), %r14d
shrl $9, %r14d
movabsq $4294967296, %r15 # imm = 0x100000000
btsq $32, %r14
movq -272(%rbp), %rdi
cmpq %rbx, %rdi
je .LBB2_21
# %bb.20: # %_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE11_M_is_localEv.exit.i.i88
callq _ZdlPv
.LBB2_21: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev.exit90
addq $512, %r15 # imm = 0x200
movq %r14, %rdi
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_23
# %bb.22:
movq -96(%rbp), %rdi
movq -72(%rbp), %rsi
movl %r12d, %edx
movl -44(%rbp), %ecx # 4-byte Reload
callq _Z25__device_stub__add_arraysPPfS_ii
.LBB2_23:
callq hipDeviceSynchronize
leaq -224(%rbp), %rbx
movq %rbx, -16(%rbx)
.Ltmp24:
leaq -240(%rbp), %rdi
movl $.L.str.4, %esi
movl $.L.str.4+138, %edx
callq _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_M_constructIPKcEEvT_S8_St20forward_iterator_tag
.Ltmp25:
# %bb.24: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_.exit100
.Ltmp27:
leaq -240(%rbp), %rdi
movl $95, %esi
callq _Z10cuda_checkNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEi
.Ltmp28:
# %bb.25:
movq -240(%rbp), %rdi
cmpq %rbx, %rdi
je .LBB2_27
# %bb.26: # %_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE11_M_is_localEv.exit.i.i101
callq _ZdlPv
.LBB2_27: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev.exit103
movq -88(%rbp), %rax # 8-byte Reload
movq (%rax,%r13,8), %rdi
movq -72(%rbp), %rsi
movq -56(%rbp), %rdx # 8-byte Reload
movl $2, %ecx
callq hipMemcpy
leaq -192(%rbp), %rbx
movq %rbx, -16(%rbx)
.Ltmp30:
leaq -208(%rbp), %rdi
movl $.L.str.4, %esi
movl $.L.str.4+138, %edx
callq _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_M_constructIPKcEEvT_S8_St20forward_iterator_tag
.Ltmp31:
# %bb.28: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_.exit104
.Ltmp33:
leaq -208(%rbp), %rdi
movl $99, %esi
callq _Z10cuda_checkNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEi
.Ltmp34:
movq -80(%rbp), %r12 # 8-byte Reload
# %bb.29:
movq -208(%rbp), %rdi
cmpq %rbx, %rdi
je .LBB2_31
# %bb.30: # %_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE11_M_is_localEv.exit.i.i105
callq _ZdlPv
.LBB2_31: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev.exit107
cmpl $0, -44(%rbp) # 4-byte Folded Reload
jle .LBB2_38
# %bb.32: # %.lr.ph
leaq -160(%rbp), %rbx
xorl %r15d, %r15d
leaq -176(%rbp), %r14
.LBB2_33: # =>This Inner Loop Header: Depth=1
movq -64(%rbp), %rax # 8-byte Reload
movq (%rax,%r15,8), %rdi
callq hipFree
movq %rbx, -176(%rbp)
.Ltmp36:
movl $.L.str.4, %esi
movl $.L.str.4+138, %edx
movq %r14, %rdi
callq _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_M_constructIPKcEEvT_S8_St20forward_iterator_tag
.Ltmp37:
# %bb.34: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_.exit115
# in Loop: Header=BB2_33 Depth=1
.Ltmp39:
movq %r14, %rdi
movl $104, %esi
callq _Z10cuda_checkNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEi
.Ltmp40:
# %bb.35: # in Loop: Header=BB2_33 Depth=1
movq -176(%rbp), %rdi
cmpq %rbx, %rdi
je .LBB2_37
# %bb.36: # %_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE11_M_is_localEv.exit.i.i116
# in Loop: Header=BB2_33 Depth=1
callq _ZdlPv
.LBB2_37: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev.exit118
# in Loop: Header=BB2_33 Depth=1
incq %r15
cmpq %r15, %r12
jne .LBB2_33
.LBB2_38: # %._crit_edge144
movq -72(%rbp), %rdi
callq hipFree
leaq -128(%rbp), %rbx
movq %rbx, -16(%rbx)
.Ltmp42:
leaq -144(%rbp), %rdi
movl $.L.str.4, %esi
movl $.L.str.4+138, %edx
callq _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_M_constructIPKcEEvT_S8_St20forward_iterator_tag
.Ltmp43:
# %bb.39: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_.exit108
.Ltmp45:
leaq -144(%rbp), %rdi
movl $107, %esi
callq _Z10cuda_checkNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEi
.Ltmp46:
# %bb.40:
movq -144(%rbp), %rdi
cmpq %rbx, %rdi
je .LBB2_42
# %bb.41: # %_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE11_M_is_localEv.exit.i.i122
callq _ZdlPv
.LBB2_42: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev.exit124
leaq -40(%rbp), %rsp
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
popq %rbp
.cfi_def_cfa %rsp, 8
retq
.LBB2_43:
.cfi_def_cfa %rbp, 16
.Ltmp47:
movq %rax, %r14
movq -144(%rbp), %rdi
jmp .LBB2_59
.LBB2_44:
.Ltmp44:
jmp .LBB2_55
.LBB2_45:
.Ltmp35:
movq %rax, %r14
movq -208(%rbp), %rdi
jmp .LBB2_59
.LBB2_46:
.Ltmp32:
jmp .LBB2_55
.LBB2_47:
.Ltmp29:
movq %rax, %r14
movq -240(%rbp), %rdi
jmp .LBB2_59
.LBB2_48:
.Ltmp26:
jmp .LBB2_55
.LBB2_49:
.Ltmp23:
movq %rax, %r14
movq -272(%rbp), %rdi
jmp .LBB2_59
.LBB2_50:
.Ltmp20:
jmp .LBB2_55
.LBB2_51:
.Ltmp17:
movq %rax, %r14
movq -304(%rbp), %rdi
jmp .LBB2_59
.LBB2_52:
.Ltmp14:
jmp .LBB2_55
.LBB2_53:
.Ltmp11:
movq %rax, %r14
movq -336(%rbp), %rdi
jmp .LBB2_59
.LBB2_54:
.Ltmp8:
jmp .LBB2_55
.LBB2_56:
.Ltmp38:
.LBB2_55: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev.exit76
movq %rax, %r14
jmp .LBB2_61
.LBB2_57:
.Ltmp41:
movq %rax, %r14
movq -176(%rbp), %rdi
jmp .LBB2_59
.LBB2_58:
.Ltmp2:
movq %rax, %r14
movq -400(%rbp), %rdi
.LBB2_59:
cmpq %rbx, %rdi
je .LBB2_61
.LBB2_60: # %_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE11_M_is_localEv.exit.i.i125
callq _ZdlPv
.LBB2_61: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev.exit76
movq %r14, %rdi
callq _Unwind_Resume@PLT
.LBB2_62:
.Ltmp5:
movq %rax, %r14
movq -368(%rbp), %rdi
cmpq %r13, %rdi
jne .LBB2_60
jmp .LBB2_61
.Lfunc_end2:
.size _Z17add_arrays_callerPPfii, .Lfunc_end2-_Z17add_arrays_callerPPfii
.cfi_endproc
.section .gcc_except_table,"a",@progbits
.p2align 2, 0x0
GCC_except_table2:
.Lexception0:
.byte 255 # @LPStart Encoding = omit
.byte 255 # @TType Encoding = omit
.byte 1 # Call site Encoding = uleb128
.uleb128 .Lcst_end0-.Lcst_begin0
.Lcst_begin0:
.uleb128 .Lfunc_begin0-.Lfunc_begin0 # >> Call Site 1 <<
.uleb128 .Ltmp0-.Lfunc_begin0 # Call between .Lfunc_begin0 and .Ltmp0
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp0-.Lfunc_begin0 # >> Call Site 2 <<
.uleb128 .Ltmp1-.Ltmp0 # Call between .Ltmp0 and .Ltmp1
.uleb128 .Ltmp2-.Lfunc_begin0 # jumps to .Ltmp2
.byte 0 # On action: cleanup
.uleb128 .Ltmp1-.Lfunc_begin0 # >> Call Site 3 <<
.uleb128 .Ltmp3-.Ltmp1 # Call between .Ltmp1 and .Ltmp3
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp3-.Lfunc_begin0 # >> Call Site 4 <<
.uleb128 .Ltmp4-.Ltmp3 # Call between .Ltmp3 and .Ltmp4
.uleb128 .Ltmp5-.Lfunc_begin0 # jumps to .Ltmp5
.byte 0 # On action: cleanup
.uleb128 .Ltmp4-.Lfunc_begin0 # >> Call Site 5 <<
.uleb128 .Ltmp6-.Ltmp4 # Call between .Ltmp4 and .Ltmp6
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp6-.Lfunc_begin0 # >> Call Site 6 <<
.uleb128 .Ltmp7-.Ltmp6 # Call between .Ltmp6 and .Ltmp7
.uleb128 .Ltmp8-.Lfunc_begin0 # jumps to .Ltmp8
.byte 0 # On action: cleanup
.uleb128 .Ltmp9-.Lfunc_begin0 # >> Call Site 7 <<
.uleb128 .Ltmp10-.Ltmp9 # Call between .Ltmp9 and .Ltmp10
.uleb128 .Ltmp11-.Lfunc_begin0 # jumps to .Ltmp11
.byte 0 # On action: cleanup
.uleb128 .Ltmp10-.Lfunc_begin0 # >> Call Site 8 <<
.uleb128 .Ltmp12-.Ltmp10 # Call between .Ltmp10 and .Ltmp12
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp12-.Lfunc_begin0 # >> Call Site 9 <<
.uleb128 .Ltmp13-.Ltmp12 # Call between .Ltmp12 and .Ltmp13
.uleb128 .Ltmp14-.Lfunc_begin0 # jumps to .Ltmp14
.byte 0 # On action: cleanup
.uleb128 .Ltmp15-.Lfunc_begin0 # >> Call Site 10 <<
.uleb128 .Ltmp16-.Ltmp15 # Call between .Ltmp15 and .Ltmp16
.uleb128 .Ltmp17-.Lfunc_begin0 # jumps to .Ltmp17
.byte 0 # On action: cleanup
.uleb128 .Ltmp16-.Lfunc_begin0 # >> Call Site 11 <<
.uleb128 .Ltmp18-.Ltmp16 # Call between .Ltmp16 and .Ltmp18
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp18-.Lfunc_begin0 # >> Call Site 12 <<
.uleb128 .Ltmp19-.Ltmp18 # Call between .Ltmp18 and .Ltmp19
.uleb128 .Ltmp20-.Lfunc_begin0 # jumps to .Ltmp20
.byte 0 # On action: cleanup
.uleb128 .Ltmp21-.Lfunc_begin0 # >> Call Site 13 <<
.uleb128 .Ltmp22-.Ltmp21 # Call between .Ltmp21 and .Ltmp22
.uleb128 .Ltmp23-.Lfunc_begin0 # jumps to .Ltmp23
.byte 0 # On action: cleanup
.uleb128 .Ltmp22-.Lfunc_begin0 # >> Call Site 14 <<
.uleb128 .Ltmp24-.Ltmp22 # Call between .Ltmp22 and .Ltmp24
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp24-.Lfunc_begin0 # >> Call Site 15 <<
.uleb128 .Ltmp25-.Ltmp24 # Call between .Ltmp24 and .Ltmp25
.uleb128 .Ltmp26-.Lfunc_begin0 # jumps to .Ltmp26
.byte 0 # On action: cleanup
.uleb128 .Ltmp27-.Lfunc_begin0 # >> Call Site 16 <<
.uleb128 .Ltmp28-.Ltmp27 # Call between .Ltmp27 and .Ltmp28
.uleb128 .Ltmp29-.Lfunc_begin0 # jumps to .Ltmp29
.byte 0 # On action: cleanup
.uleb128 .Ltmp28-.Lfunc_begin0 # >> Call Site 17 <<
.uleb128 .Ltmp30-.Ltmp28 # Call between .Ltmp28 and .Ltmp30
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp30-.Lfunc_begin0 # >> Call Site 18 <<
.uleb128 .Ltmp31-.Ltmp30 # Call between .Ltmp30 and .Ltmp31
.uleb128 .Ltmp32-.Lfunc_begin0 # jumps to .Ltmp32
.byte 0 # On action: cleanup
.uleb128 .Ltmp33-.Lfunc_begin0 # >> Call Site 19 <<
.uleb128 .Ltmp34-.Ltmp33 # Call between .Ltmp33 and .Ltmp34
.uleb128 .Ltmp35-.Lfunc_begin0 # jumps to .Ltmp35
.byte 0 # On action: cleanup
.uleb128 .Ltmp34-.Lfunc_begin0 # >> Call Site 20 <<
.uleb128 .Ltmp36-.Ltmp34 # Call between .Ltmp34 and .Ltmp36
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp36-.Lfunc_begin0 # >> Call Site 21 <<
.uleb128 .Ltmp37-.Ltmp36 # Call between .Ltmp36 and .Ltmp37
.uleb128 .Ltmp38-.Lfunc_begin0 # jumps to .Ltmp38
.byte 0 # On action: cleanup
.uleb128 .Ltmp39-.Lfunc_begin0 # >> Call Site 22 <<
.uleb128 .Ltmp40-.Ltmp39 # Call between .Ltmp39 and .Ltmp40
.uleb128 .Ltmp41-.Lfunc_begin0 # jumps to .Ltmp41
.byte 0 # On action: cleanup
.uleb128 .Ltmp40-.Lfunc_begin0 # >> Call Site 23 <<
.uleb128 .Ltmp42-.Ltmp40 # Call between .Ltmp40 and .Ltmp42
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp42-.Lfunc_begin0 # >> Call Site 24 <<
.uleb128 .Ltmp43-.Ltmp42 # Call between .Ltmp42 and .Ltmp43
.uleb128 .Ltmp44-.Lfunc_begin0 # jumps to .Ltmp44
.byte 0 # On action: cleanup
.uleb128 .Ltmp45-.Lfunc_begin0 # >> Call Site 25 <<
.uleb128 .Ltmp46-.Ltmp45 # Call between .Ltmp45 and .Ltmp46
.uleb128 .Ltmp47-.Lfunc_begin0 # jumps to .Ltmp47
.byte 0 # On action: cleanup
.uleb128 .Ltmp46-.Lfunc_begin0 # >> Call Site 26 <<
.uleb128 .Lfunc_end2-.Ltmp46 # Call between .Ltmp46 and .Lfunc_end2
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.Lcst_end0:
.p2align 2, 0x0
# -- End function
.text
.globl main # -- Begin function main
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $32, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $80, %edi
callq _Znam
movq %rax, %rbx
movl $80, %edi
callq _Znam
movq %rax, %r14
movl $80, %edi
callq _Znam
movq %rax, %r15
xorps %xmm0, %xmm0
movups %xmm0, (%rax)
movups %xmm0, 16(%rax)
movups %xmm0, 32(%rax)
movups %xmm0, 48(%rax)
movups %xmm0, 64(%rax)
movb $1, %al
xorl %ecx, %ecx
.LBB3_1: # =>This Inner Loop Header: Depth=1
movzbl %cl, %edx
imull $205, %edx, %edx
shrl $10, %edx
leal (%rdx,%rdx,4), %edx
movl %eax, %esi
subb %dl, %sil
xorps %xmm0, %xmm0
cvtsi2ss %ecx, %xmm0
movss %xmm0, (%rbx,%rcx,4)
movzbl %sil, %edx
xorps %xmm0, %xmm0
cvtsi2ss %edx, %xmm0
movss %xmm0, (%r14,%rcx,4)
incq %rcx
incb %al
cmpq $20, %rcx
jne .LBB3_1
# %bb.2: # %.preheader.preheader
xorl %eax, %eax
.LBB3_3: # %.preheader
# =>This Inner Loop Header: Depth=1
movss (%rbx,%rax,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
addss (%r14,%rax,4), %xmm0
movss %xmm0, (%r15,%rax,4)
incq %rax
cmpq $20, %rax
jne .LBB3_3
# %bb.4:
movl $_ZSt4cout, %r12d
movl $_ZSt4cout, %edi
movl $.L.str.5, %esi
movl $4, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rdi
addq %r12, %rdi
movl $10, %esi
callq _ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
xorl %r12d, %r12d
.LBB3_5: # =>This Inner Loop Header: Depth=1
movl $_ZSt4cout, %edi
movl %r12d, %esi
callq _ZNSolsEi
movq %rax, %r13
movl $.L.str.1, %esi
movl $2, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
xorps %xmm0, %xmm0
cvtss2sd (%rbx,%r12,4), %xmm0
movq %r13, %rdi
callq _ZNSo9_M_insertIdEERSoT_
movq %rax, %r13
movl $.L.str.6, %esi
movl $3, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
xorps %xmm0, %xmm0
cvtss2sd (%r14,%r12,4), %xmm0
movq %r13, %rdi
callq _ZNSo9_M_insertIdEERSoT_
movq %rax, %r13
movl $.L.str.7, %esi
movl $3, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
xorps %xmm0, %xmm0
cvtss2sd (%r15,%r12,4), %xmm0
movq %r13, %rdi
callq _ZNSo9_M_insertIdEERSoT_
movq %rax, %r13
movq (%rax), %rax
movq -24(%rax), %rdi
addq %r13, %rdi
movl $10, %esi
callq _ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
movsbl %al, %esi
movq %r13, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
incq %r12
cmpq $20, %r12
jne .LBB3_5
# %bb.6:
movq _ZSt4cout(%rip), %rax
movl $_ZSt4cout, %r12d
movq -24(%rax), %rdi
addq %r12, %rdi
movl $10, %esi
callq _ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
xorps %xmm0, %xmm0
movups %xmm0, (%r15)
movups %xmm0, 16(%r15)
movups %xmm0, 32(%r15)
movups %xmm0, 48(%r15)
movups %xmm0, 64(%r15)
movq %rsp, %rdi
movq %rbx, (%rdi)
movq %r14, 8(%rdi)
movq %r15, 16(%rdi)
movl $20, %esi
movl $2, %edx
callq _Z17add_arrays_callerPPfii
movl $_ZSt4cout, %edi
movl $.L.str.8, %esi
movl $4, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rdi
addq %r12, %rdi
movl $10, %esi
callq _ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
xorl %r12d, %r12d
.LBB3_7: # =>This Inner Loop Header: Depth=1
movl $_ZSt4cout, %edi
movl %r12d, %esi
callq _ZNSolsEi
movq %rax, %r13
movl $.L.str.1, %esi
movl $2, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
xorps %xmm0, %xmm0
cvtss2sd (%rbx,%r12,4), %xmm0
movq %r13, %rdi
callq _ZNSo9_M_insertIdEERSoT_
movq %rax, %r13
movl $.L.str.6, %esi
movl $3, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
xorps %xmm0, %xmm0
cvtss2sd (%r14,%r12,4), %xmm0
movq %r13, %rdi
callq _ZNSo9_M_insertIdEERSoT_
movq %rax, %r13
movl $.L.str.7, %esi
movl $3, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
xorps %xmm0, %xmm0
cvtss2sd (%r15,%r12,4), %xmm0
movq %r13, %rdi
callq _ZNSo9_M_insertIdEERSoT_
movq %rax, %r13
movq (%rax), %rax
movq -24(%rax), %rdi
addq %r13, %rdi
movl $10, %esi
callq _ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
movsbl %al, %esi
movq %r13, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
incq %r12
cmpq $20, %r12
jne .LBB3_7
# %bb.8:
movq _ZSt4cout(%rip), %rax
movl $_ZSt4cout, %ecx
movq -24(%rax), %rdi
addq %rcx, %rdi
movl $10, %esi
callq _ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq %rbx, %rdi
callq _ZdaPv
movq %r14, %rdi
callq _ZdaPv
movq %r15, %rdi
callq _ZdaPv
xorl %eax, %eax
addq $32, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
# -- End function
.section .text._ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_M_constructIPKcEEvT_S8_St20forward_iterator_tag,"axG",@progbits,_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_M_constructIPKcEEvT_S8_St20forward_iterator_tag,comdat
.weak _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_M_constructIPKcEEvT_S8_St20forward_iterator_tag # -- Begin function _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_M_constructIPKcEEvT_S8_St20forward_iterator_tag
.p2align 1, 0x90
.type _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_M_constructIPKcEEvT_S8_St20forward_iterator_tag,@function
_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_M_constructIPKcEEvT_S8_St20forward_iterator_tag: # @_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_M_constructIPKcEEvT_S8_St20forward_iterator_tag
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
pushq %rax
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rdx, %r14
movq %rsi, %r15
movq %rdi, %rbx
subq %rsi, %r14
movq %r14, (%rsp)
cmpq $15, %r14
jbe .LBB4_1
# %bb.2:
movq %rsp, %r12
movq %rbx, %rdi
movq %r12, %rsi
xorl %edx, %edx
callq _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_createERmm
movq %rax, (%rbx)
movq (%r12), %rcx
movq %rcx, 16(%rbx)
jmp .LBB4_3
.LBB4_1: # %._crit_edge
movq (%rbx), %rax
.LBB4_3:
testq %r14, %r14
je .LBB4_7
# %bb.4:
cmpq $1, %r14
jne .LBB4_6
# %bb.5:
movb (%r15), %cl
movb %cl, (%rax)
jmp .LBB4_7
.LBB4_6:
movq %rax, %rdi
movq %r15, %rsi
movq %r14, %rdx
callq memcpy@PLT
.LBB4_7: # %_ZZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_M_constructIPKcEEvT_S8_St20forward_iterator_tagEN6_GuardD2Ev.exit
movq (%rsp), %rax
movq %rax, 8(%rbx)
movq (%rbx), %rcx
movb $0, (%rcx,%rax)
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end4:
.size _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_M_constructIPKcEEvT_S8_St20forward_iterator_tag, .Lfunc_end4-_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_M_constructIPKcEEvT_S8_St20forward_iterator_tag
.cfi_endproc
# -- End function
.text
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
jne .LBB5_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, %rdi
movq %rax, __hip_gpubin_handle(%rip)
.LBB5_2:
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10add_arraysPPfS_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end5:
.size __hip_module_ctor, .Lfunc_end5-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB6_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB6_2:
retq
.Lfunc_end6:
.size __hip_module_dtor, .Lfunc_end6-__hip_module_dtor
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz ", line "
.size .L.str, 8
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz ": "
.size .L.str.1, 3
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz " ("
.size .L.str.2, 3
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz ")"
.size .L.str.3, 2
.type _Z10add_arraysPPfS_ii,@object # @_Z10add_arraysPPfS_ii
.section .rodata,"a",@progbits
.globl _Z10add_arraysPPfS_ii
.p2align 3, 0x0
_Z10add_arraysPPfS_ii:
.quad _Z25__device_stub__add_arraysPPfS_ii
.size _Z10add_arraysPPfS_ii, 8
.type .L.str.4,@object # @.str.4
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.4:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/shiviser/TUM_GPUComputerVision/master/cuda_team_warp64/exercises/2/add_arrays.hip"
.size .L.str.4, 139
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "CPU:"
.size .L.str.5, 5
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz " + "
.size .L.str.6, 4
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz " = "
.size .L.str.7, 4
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "GPU:"
.size .L.str.8, 5
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z10add_arraysPPfS_ii"
.size .L__unnamed_1, 22
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__add_arraysPPfS_ii
.addrsig_sym __gxx_personality_v0
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Unwind_Resume
.addrsig_sym _ZSt4cout
.addrsig_sym _Z10add_arraysPPfS_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
```
| 14,505 | 16,749 |
644 |
Convert the following CUDA device assembly code to AMD device assembly:
```cudaasm
code for sm_80
Function : _Z3fooPi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
MOV R1, c[0x0][0x28] ;
S2R R2, SR_TID.X ;
HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ;
ULDC.64 UR4, c[0x0][0x118] ;
IMAD.WIDE.U32 R2, R2, R3, c[0x0][0x160] ;
LDG.E.CONSTANT R2, [R2.64] ;
ISETP.NE.AND P0, PT, R2, RZ, PT ;
@!P0 EXIT ;
BAR.SYNC.DEFER_BLOCKING 0x0 ;
EXIT ;
BRA 0xa0;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
```
|
```amdasm
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3fooPi ; -- Begin function _Z3fooPi
.globl _Z3fooPi
.p2align 8
.type _Z3fooPi,@function
_Z3fooPi: ; @_Z3fooPi
; %bb.0:
s_load_b64 s[0:1], s[0:1], 0x0
v_lshlrev_b32_e32 v0, 2, v0
s_waitcnt lgkmcnt(0)
global_load_b32 v0, v0, s[0:1]
s_mov_b32 s0, exec_lo
s_waitcnt vmcnt(0)
v_cmpx_ne_u32_e32 0, v0
s_cbranch_execz .LBB0_2
; %bb.1:
s_barrier
buffer_gl0_inv
.LBB0_2:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3fooPi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 8
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 1
.amdhsa_next_free_sgpr 2
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3fooPi, .Lfunc_end0-_Z3fooPi
; -- End function
.section .AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 56
; NumSgprs: 2
; NumVgprs: 1
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 0
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 2
; NumVGPRsForWavesPerEU: 1
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object ; @__hip_cuid_
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0 ; 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 8
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3fooPi
.private_segment_fixed_size: 0
.sgpr_count: 2
.sgpr_spill_count: 0
.symbol: _Z3fooPi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 1
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
```
| 273 | 1,626 |
645 |
Convert the following CUDA host assembly code to AMD host assembly:
```cudaasm
.file "tmpxft_00047b28_00000000-6_barrier-div-cuda.cudafe1.cpp"
.text
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z22__device_stub__Z3fooPiPi
.type _Z22__device_stub__Z3fooPiPi, @function
_Z22__device_stub__Z3fooPiPi:
.LFB2051:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z3fooPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z22__device_stub__Z3fooPiPi, .-_Z22__device_stub__Z3fooPiPi
.globl _Z3fooPi
.type _Z3fooPi, @function
_Z3fooPi:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z22__device_stub__Z3fooPiPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z3fooPi, .-_Z3fooPi
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z3fooPi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z3fooPi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
```
|
```amdasm
.text
.file "barrier-div-cuda.hip"
.globl _Z18__device_stub__fooPi # -- Begin function _Z18__device_stub__fooPi
.type _Z18__device_stub__fooPi,@function
_Z18__device_stub__fooPi: # @_Z18__device_stub__fooPi
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $64, %rsp
.cfi_def_cfa_offset 112
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 24(%rsp), %rax
movq %rdi, (%rax)
movq %rsp, %rbx
movq %rax, (%rbx)
leaq 48(%rsp), %r14
leaq 32(%rsp), %r15
leaq 16(%rsp), %r12
leaq 8(%rsp), %r13
movq %r14, %rdi
movq %r15, %rsi
movq %r12, %rdx
movq %r13, %rcx
callq __hipPopCallConfiguration
movq (%r14), %rsi
movl 8(%r14), %edx
movq (%r15), %rcx
movl 8(%r15), %r8d
movl $_Z3fooPi, %edi
movq %rbx, %r9
pushq (%r13)
.cfi_adjust_cfa_offset 8
pushq (%r12)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $80, %rsp
.cfi_adjust_cfa_offset -80
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z18__device_stub__fooPi, .Lfunc_end0-_Z18__device_stub__fooPi
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, %rdi
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3fooPi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3fooPi,@object # @_Z3fooPi
.section .rodata,"a",@progbits
.globl _Z3fooPi
.p2align 3, 0x0
_Z3fooPi:
.quad _Z18__device_stub__fooPi
.size _Z3fooPi, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z3fooPi"
.size .L__unnamed_1, 9
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__fooPi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3fooPi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
```
| 1,684 | 1,870 |
648 |
Convert the following CUDA device assembly code to AMD device assembly:
```cudaasm
code for sm_80
Function : _Z21updateDisplacements_kP6float4S0_PfS0_S0_iS0_j
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
MOV R1, c[0x0][0x28] ;
S2R R28, SR_CTAID.X ;
S2R R3, SR_TID.X ;
IMAD R28, R28, c[0x0][0x0], R3 ;
ISETP.GE.U32.AND P0, PT, R28, c[0x0][0x198], PT ;
@P0 EXIT ;
MOV R3, c[0x0][0x188] ;
ULDC.64 UR4, c[0x0][0x118] ;
HFMA2.MMA R29, -RZ, RZ, 0, 0 ;
CS2R R30, SRZ ;
ISETP.GE.AND P0, PT, R3, 0x1, PT ;
@!P0 BRA 0xb70 ;
IADD3 R0, R3.reuse, -0x1, RZ ;
CS2R R30, SRZ ;
LOP3.LUT R3, R3, 0x3, RZ, 0xc0, !PT ;
ISETP.GE.U32.AND P0, PT, R0, 0x3, PT ;
MOV R29, RZ ;
MOV R2, RZ ;
@!P0 BRA 0xa50 ;
IADD3 R0, -R3, c[0x0][0x188], RZ ;
HFMA2.MMA R33, -RZ, RZ, 0, 9.5367431640625e-07 ;
IMAD R32, R28, c[0x0][0x188], RZ ;
HFMA2.MMA R2, -RZ, RZ, 0, 0 ;
ISETP.GT.AND P0, PT, R0, RZ, PT ;
MOV R29, RZ ;
IMAD.WIDE R32, R32, R33, c[0x0][0x180] ;
@!P0 BRA 0x8e0 ;
ISETP.GT.AND P1, PT, R0, 0xc, PT ;
PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ;
@!P1 BRA 0x650 ;
PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ;
LDG.E.128 R12, [R32.64] ;
LDG.E.128 R16, [R32.64+0x10] ;
LDG.E.128 R20, [R32.64+0x20] ;
LDG.E.128 R4, [R32.64+0x30] ;
LDG.E.128 R24, [R32.64+0x40] ;
LDG.E.128 R8, [R32.64+0x50] ;
FADD R15, R12, R30 ;
FADD R12, R13, R31 ;
FADD R19, R15, R16 ;
FADD R16, R12, R17 ;
FADD R29, R14, R29 ;
LDG.E.128 R12, [R32.64+0x60] ;
FADD R23, R19, R20 ;
FADD R20, R16, R21 ;
FADD R29, R29, R18 ;
LDG.E.128 R16, [R32.64+0x70] ;
FADD R7, R23, R4 ;
FADD R4, R20, R5 ;
FADD R29, R29, R22 ;
LDG.E.128 R20, [R32.64+0x80] ;
FADD R27, R7, R24 ;
FADD R29, R29, R6 ;
FADD R24, R4, R25 ;
LDG.E.128 R4, [R32.64+0x90] ;
FADD R11, R27, R8 ;
FADD R29, R29, R26 ;
FADD R8, R24, R9 ;
LDG.E.128 R24, [R32.64+0xa0] ;
FADD R29, R29, R10 ;
FADD R15, R11, R12 ;
FADD R12, R8, R13 ;
LDG.E.128 R8, [R32.64+0xb0] ;
FADD R29, R29, R14 ;
FADD R19, R15, R16 ;
FADD R16, R12, R17 ;
LDG.E.128 R12, [R32.64+0xc0] ;
FADD R29, R29, R18 ;
FADD R23, R19, R20 ;
FADD R20, R16, R21 ;
LDG.E.128 R16, [R32.64+0xd0] ;
FADD R29, R29, R22 ;
FADD R7, R23, R4 ;
FADD R4, R20, R5 ;
LDG.E.128 R20, [R32.64+0xe0] ;
FADD R29, R29, R6 ;
FADD R27, R7, R24 ;
FADD R24, R4, R25 ;
LDG.E.128 R4, [R32.64+0xf0] ;
FADD R29, R29, R26 ;
IADD3 R0, R0, -0x10, RZ ;
ISETP.GT.AND P1, PT, R0, 0xc, PT ;
IADD3 R32, P2, R32, 0x100, RZ ;
IADD3 R2, R2, 0x10, RZ ;
IADD3.X R33, RZ, R33, RZ, P2, !PT ;
FADD R27, R27, R8 ;
FADD R24, R24, R9 ;
FADD R29, R29, R10 ;
FADD R27, R27, R12 ;
FADD R24, R24, R13 ;
FADD R29, R29, R14 ;
FADD R27, R27, R16 ;
FADD R24, R24, R17 ;
FADD R29, R29, R18 ;
FADD R27, R27, R20 ;
FADD R24, R24, R21 ;
FADD R29, R29, R22 ;
FADD R30, R27, R4 ;
FADD R31, R24, R5 ;
FADD R29, R29, R6 ;
@P1 BRA 0x1f0 ;
ISETP.GT.AND P1, PT, R0, 0x4, PT ;
@!P1 BRA 0x8c0 ;
LDG.E.128 R24, [R32.64] ;
LDG.E.128 R8, [R32.64+0x10] ;
LDG.E.128 R12, [R32.64+0x20] ;
LDG.E.128 R16, [R32.64+0x30] ;
LDG.E.128 R20, [R32.64+0x40] ;
LDG.E.128 R4, [R32.64+0x50] ;
FADD R27, R30, R24 ;
FADD R24, R31, R25 ;
FADD R11, R27, R8 ;
FADD R8, R24, R9 ;
FADD R29, R29, R26 ;
LDG.E.128 R24, [R32.64+0x60] ;
FADD R15, R11, R12 ;
FADD R29, R29, R10 ;
FADD R12, R8, R13 ;
LDG.E.128 R8, [R32.64+0x70] ;
FADD R29, R29, R14 ;
FADD R15, R15, R16 ;
FADD R12, R12, R17 ;
FADD R29, R29, R18 ;
FADD R15, R15, R20 ;
FADD R12, R12, R21 ;
FADD R29, R29, R22 ;
FADD R15, R15, R4 ;
FADD R12, R12, R5 ;
FADD R29, R29, R6 ;
IADD3 R32, P1, R32, 0x80, RZ ;
PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ;
IADD3.X R33, RZ, R33, RZ, P1, !PT ;
IADD3 R2, R2, 0x8, RZ ;
IADD3 R0, R0, -0x8, RZ ;
FADD R15, R15, R24 ;
FADD R12, R12, R25 ;
FADD R29, R29, R26 ;
FADD R30, R15, R8 ;
FADD R31, R12, R9 ;
FADD R29, R29, R10 ;
ISETP.NE.OR P0, PT, R0, RZ, P0 ;
@!P0 BRA 0xa50 ;
LDG.E.128 R4, [R32.64] ;
LDG.E.128 R8, [R32.64+0x10] ;
LDG.E.128 R12, [R32.64+0x20] ;
LDG.E.128 R16, [R32.64+0x30] ;
IADD3 R0, R0, -0x4, RZ ;
IADD3 R2, R2, 0x4, RZ ;
ISETP.NE.AND P0, PT, R0, RZ, PT ;
FADD R7, R4, R30 ;
FADD R4, R5, R31 ;
IADD3 R5, P1, R32, 0x40, RZ ;
FADD R29, R6, R29 ;
FADD R7, R7, R8 ;
IADD3.X R33, RZ, R33, RZ, P1, !PT ;
FADD R4, R4, R9 ;
MOV R32, R5 ;
FADD R29, R29, R10 ;
FADD R7, R7, R12 ;
FADD R4, R4, R13 ;
FADD R29, R29, R14 ;
FADD R30, R7, R16 ;
FADD R31, R4, R17 ;
FADD R29, R29, R18 ;
@P0 BRA 0x8e0 ;
ISETP.NE.AND P0, PT, R3, RZ, PT ;
@!P0 BRA 0xb70 ;
HFMA2.MMA R5, -RZ, RZ, 0, 9.5367431640625e-07 ;
IMAD R4, R28, c[0x0][0x188], R2 ;
IMAD.WIDE R4, R4, R5, c[0x0][0x180] ;
MOV R0, R4 ;
MOV R9, R5 ;
MOV R4, R0 ;
MOV R5, R9 ;
LDG.E.128 R4, [R4.64] ;
IADD3 R3, R3, -0x1, RZ ;
IADD3 R0, P1, R0, 0x10, RZ ;
ISETP.NE.AND P0, PT, R3, RZ, PT ;
IADD3.X R9, RZ, R9, RZ, P1, !PT ;
FADD R30, R4, R30 ;
FADD R31, R5, R31 ;
FADD R29, R6, R29 ;
@P0 BRA 0xac0 ;
MOV R3, 0x10 ;
IMAD.WIDE R8, R28, R3, c[0x0][0x178] ;
IMAD.WIDE R4, R28.reuse, R3.reuse, c[0x0][0x190] ;
LDG.E.128 R8, [R8.64] ;
IMAD.WIDE R12, R28.reuse, R3.reuse, c[0x0][0x160] ;
LDG.E.128 R4, [R4.64] ;
IMAD.WIDE R2, R28, R3, c[0x0][0x168] ;
LDG.E.128 R12, [R12.64] ;
LDG.E.128 R16, [R2.64] ;
FADD R29, R10, -R29 ;
FADD R31, R9, -R31 ;
FADD R11, R8, -R30 ;
FMUL R29, R4.reuse, R29 ;
FMUL R0, R4.reuse, R31 ;
FMUL R11, R4, R11 ;
FFMA R29, R5.reuse, R14, R29 ;
MOV R19, RZ ;
FFMA R0, R5, R13, R0 ;
FFMA R11, R5, R12, R11 ;
FFMA R18, R6.reuse, R18, R29 ;
FFMA R17, R6.reuse, R17, R0 ;
FFMA R16, R6, R16, R11 ;
STG.E.128 [R2.64], R16 ;
EXIT ;
BRA 0xcf0;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
```
|
```amdasm
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z21updateDisplacements_kP15HIP_vector_typeIfLj4EES1_PfS1_S1_iS1_j ; -- Begin function _Z21updateDisplacements_kP15HIP_vector_typeIfLj4EES1_PfS1_S1_iS1_j
.globl _Z21updateDisplacements_kP15HIP_vector_typeIfLj4EES1_PfS1_S1_iS1_j
.p2align 8
.type _Z21updateDisplacements_kP15HIP_vector_typeIfLj4EES1_PfS1_S1_iS1_j,@function
_Z21updateDisplacements_kP15HIP_vector_typeIfLj4EES1_PfS1_S1_iS1_j: ; @_Z21updateDisplacements_kP15HIP_vector_typeIfLj4EES1_PfS1_S1_iS1_j
; %bb.0:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x4c
s_load_b32 s3, s[0:1], 0x38
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_u32_e64 s3, v1
s_cbranch_execz .LBB0_5
; %bb.1: ; %.preheader
s_clause 0x1
s_load_b32 s2, s[0:1], 0x28
s_load_b128 s[4:7], s[0:1], 0x18
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v5, 0
v_mov_b32_e32 v4, 0
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s2, 1
s_cbranch_scc1 .LBB0_4
; %bb.2: ; %.lr.ph
v_mul_lo_u32 v2, v1, s2
v_dual_mov_b32 v5, 0 :: v_dual_mov_b32 v4, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[2:3], 4, v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v2, s6
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, v0, 4
v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
v_mov_b32_e32 v0, 0
.LBB0_3: ; =>This Inner Loop Header: Depth=1
global_load_b96 v[6:8], v[2:3], off offset:-4
v_add_co_u32 v2, vcc_lo, v2, 16
v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
s_add_i32 s2, s2, -1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s2, 0
s_waitcnt vmcnt(0)
v_dual_add_f32 v5, v5, v6 :: v_dual_add_f32 v4, v4, v7
v_add_f32_e32 v0, v0, v8
s_cbranch_scc0 .LBB0_3
.LBB0_4: ; %Flow110
s_load_b64 s[6:7], s[0:1], 0x30
v_ashrrev_i32_e32 v2, 31, v1
s_load_b128 s[0:3], s[0:1], 0x0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[9:10], 4, v[1:2]
v_add_co_u32 v1, vcc_lo, s4, v9
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, s5, v10, vcc_lo
global_load_b96 v[1:3], v[1:2], off
s_waitcnt lgkmcnt(0)
v_add_co_u32 v6, vcc_lo, s6, v9
v_add_co_ci_u32_e32 v7, vcc_lo, s7, v10, vcc_lo
v_add_co_u32 v11, vcc_lo, s0, v9
v_add_co_ci_u32_e32 v12, vcc_lo, s1, v10, vcc_lo
global_load_b96 v[6:8], v[6:7], off
v_add_co_u32 v15, vcc_lo, s2, v9
v_add_co_ci_u32_e32 v16, vcc_lo, s3, v10, vcc_lo
global_load_b96 v[9:11], v[11:12], off
global_load_b96 v[12:14], v[15:16], off
s_waitcnt vmcnt(3)
v_dual_sub_f32 v1, v1, v5 :: v_dual_sub_f32 v2, v2, v4
s_waitcnt vmcnt(2)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_dual_sub_f32 v3, v3, v0 :: v_dual_mul_f32 v0, v6, v1
s_waitcnt vmcnt(1)
v_dual_mul_f32 v1, v6, v2 :: v_dual_fmac_f32 v0, v7, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_dual_mul_f32 v2, v6, v3 :: v_dual_fmac_f32 v1, v7, v10
s_waitcnt vmcnt(0)
v_dual_mov_b32 v3, 0 :: v_dual_fmac_f32 v0, v8, v12
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_fmac_f32 v2, v7, v11 :: v_dual_fmac_f32 v1, v8, v13
v_fmac_f32_e32 v2, v8, v14
global_store_b128 v[15:16], v[0:3], off
.LBB0_5:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z21updateDisplacements_kP15HIP_vector_typeIfLj4EES1_PfS1_S1_iS1_j
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 320
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 17
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z21updateDisplacements_kP15HIP_vector_typeIfLj4EES1_PfS1_S1_iS1_j, .Lfunc_end0-_Z21updateDisplacements_kP15HIP_vector_typeIfLj4EES1_PfS1_S1_iS1_j
; -- End function
.section .AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 444
; NumSgprs: 18
; NumVgprs: 17
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 2
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 17
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object ; @__hip_cuid_
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0 ; 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .offset: 40
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 48
.size: 8
.value_kind: global_buffer
- .offset: 56
.size: 4
.value_kind: by_value
- .offset: 64
.size: 4
.value_kind: hidden_block_count_x
- .offset: 68
.size: 4
.value_kind: hidden_block_count_y
- .offset: 72
.size: 4
.value_kind: hidden_block_count_z
- .offset: 76
.size: 2
.value_kind: hidden_group_size_x
- .offset: 78
.size: 2
.value_kind: hidden_group_size_y
- .offset: 80
.size: 2
.value_kind: hidden_group_size_z
- .offset: 82
.size: 2
.value_kind: hidden_remainder_x
- .offset: 84
.size: 2
.value_kind: hidden_remainder_y
- .offset: 86
.size: 2
.value_kind: hidden_remainder_z
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 112
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 120
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 128
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 320
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z21updateDisplacements_kP15HIP_vector_typeIfLj4EES1_PfS1_S1_iS1_j
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z21updateDisplacements_kP15HIP_vector_typeIfLj4EES1_PfS1_S1_iS1_j.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 17
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
```
| 3,594 | 4,013 |
649 |
Convert the following CUDA host assembly code to AMD host assembly:
```cudaasm
.file "tmpxft_00074a2f_00000000-6_updateDisplacements_k.cudafe1.cpp"
.text
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z63__device_stub__Z21updateDisplacements_kP6float4S0_PfS0_S0_iS0_jP6float4S0_PfS0_S0_iS0_j
.type _Z63__device_stub__Z21updateDisplacements_kP6float4S0_PfS0_S0_iS0_jP6float4S0_PfS0_S0_iS0_j, @function
_Z63__device_stub__Z21updateDisplacements_kP6float4S0_PfS0_S0_iS0_jP6float4S0_PfS0_S0_iS0_j:
.LFB2051:
.cfi_startproc
endbr64
subq $216, %rsp
.cfi_def_cfa_offset 224
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
movq %rdx, 40(%rsp)
movq %rcx, 32(%rsp)
movq %r8, 24(%rsp)
movl %r9d, 20(%rsp)
movq 224(%rsp), %rax
movq %rax, 8(%rsp)
movq %fs:40, %rax
movq %rax, 200(%rsp)
xorl %eax, %eax
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 40(%rsp), %rax
movq %rax, 144(%rsp)
leaq 32(%rsp), %rax
movq %rax, 152(%rsp)
leaq 24(%rsp), %rax
movq %rax, 160(%rsp)
leaq 20(%rsp), %rax
movq %rax, 168(%rsp)
leaq 8(%rsp), %rax
movq %rax, 176(%rsp)
leaq 232(%rsp), %rax
movq %rax, 184(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
leaq 72(%rsp), %rcx
leaq 64(%rsp), %rdx
leaq 92(%rsp), %rsi
leaq 80(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 200(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $216, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 72(%rsp)
.cfi_def_cfa_offset 232
pushq 72(%rsp)
.cfi_def_cfa_offset 240
leaq 144(%rsp), %r9
movq 108(%rsp), %rcx
movl 116(%rsp), %r8d
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
leaq _Z21updateDisplacements_kP6float4S0_PfS0_S0_iS0_j(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 224
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z63__device_stub__Z21updateDisplacements_kP6float4S0_PfS0_S0_iS0_jP6float4S0_PfS0_S0_iS0_j, .-_Z63__device_stub__Z21updateDisplacements_kP6float4S0_PfS0_S0_iS0_jP6float4S0_PfS0_S0_iS0_j
.globl _Z21updateDisplacements_kP6float4S0_PfS0_S0_iS0_j
.type _Z21updateDisplacements_kP6float4S0_PfS0_S0_iS0_j, @function
_Z21updateDisplacements_kP6float4S0_PfS0_S0_iS0_j:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 24
pushq 24(%rsp)
.cfi_def_cfa_offset 32
call _Z63__device_stub__Z21updateDisplacements_kP6float4S0_PfS0_S0_iS0_jP6float4S0_PfS0_S0_iS0_j
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z21updateDisplacements_kP6float4S0_PfS0_S0_iS0_j, .-_Z21updateDisplacements_kP6float4S0_PfS0_S0_iS0_j
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z21updateDisplacements_kP6float4S0_PfS0_S0_iS0_j"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z21updateDisplacements_kP6float4S0_PfS0_S0_iS0_j(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
```
|
```amdasm
.text
.file "updateDisplacements_k.hip"
.globl _Z36__device_stub__updateDisplacements_kP15HIP_vector_typeIfLj4EES1_PfS1_S1_iS1_j # -- Begin function _Z36__device_stub__updateDisplacements_kP15HIP_vector_typeIfLj4EES1_PfS1_S1_iS1_j
.type _Z36__device_stub__updateDisplacements_kP15HIP_vector_typeIfLj4EES1_PfS1_S1_iS1_j,@function
_Z36__device_stub__updateDisplacements_kP15HIP_vector_typeIfLj4EES1_PfS1_S1_iS1_j: # @_Z36__device_stub__updateDisplacements_kP15HIP_vector_typeIfLj4EES1_PfS1_S1_iS1_j
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $160, %rsp
.cfi_def_cfa_offset 208
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 56(%rsp), %rax
movq %rdi, (%rax)
leaq 48(%rsp), %rdi
movq %rsi, (%rdi)
leaq 40(%rsp), %rsi
movq %rdx, (%rsi)
leaq 32(%rsp), %rdx
movq %rcx, (%rdx)
leaq 24(%rsp), %rcx
movq %r8, (%rcx)
leaq 4(%rsp), %r8
movl %r9d, (%r8)
leaq 96(%rsp), %rbx
movq %rax, (%rbx)
movq %rdi, 8(%rbx)
movq %rsi, 16(%rbx)
movq %rdx, 24(%rbx)
movq %rcx, 32(%rbx)
movq %r8, 40(%rbx)
leaq 208(%rsp), %rax
movq %rax, 48(%rbx)
leaq 216(%rsp), %rax
movq %rax, 56(%rbx)
leaq 80(%rsp), %r14
leaq 64(%rsp), %r15
leaq 16(%rsp), %r12
leaq 8(%rsp), %r13
movq %r14, %rdi
movq %r15, %rsi
movq %r12, %rdx
movq %r13, %rcx
callq __hipPopCallConfiguration
movq (%r14), %rsi
movl 8(%r14), %edx
movq (%r15), %rcx
movl 8(%r15), %r8d
movl $_Z21updateDisplacements_kP15HIP_vector_typeIfLj4EES1_PfS1_S1_iS1_j, %edi
movq %rbx, %r9
pushq (%r13)
.cfi_adjust_cfa_offset 8
pushq (%r12)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $176, %rsp
.cfi_adjust_cfa_offset -176
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z36__device_stub__updateDisplacements_kP15HIP_vector_typeIfLj4EES1_PfS1_S1_iS1_j, .Lfunc_end0-_Z36__device_stub__updateDisplacements_kP15HIP_vector_typeIfLj4EES1_PfS1_S1_iS1_j
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, %rdi
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z21updateDisplacements_kP15HIP_vector_typeIfLj4EES1_PfS1_S1_iS1_j, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z21updateDisplacements_kP15HIP_vector_typeIfLj4EES1_PfS1_S1_iS1_j,@object # @_Z21updateDisplacements_kP15HIP_vector_typeIfLj4EES1_PfS1_S1_iS1_j
.section .rodata,"a",@progbits
.globl _Z21updateDisplacements_kP15HIP_vector_typeIfLj4EES1_PfS1_S1_iS1_j
.p2align 3, 0x0
_Z21updateDisplacements_kP15HIP_vector_typeIfLj4EES1_PfS1_S1_iS1_j:
.quad _Z36__device_stub__updateDisplacements_kP15HIP_vector_typeIfLj4EES1_PfS1_S1_iS1_j
.size _Z21updateDisplacements_kP15HIP_vector_typeIfLj4EES1_PfS1_S1_iS1_j, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z21updateDisplacements_kP15HIP_vector_typeIfLj4EES1_PfS1_S1_iS1_j"
.size .L__unnamed_1, 67
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z36__device_stub__updateDisplacements_kP15HIP_vector_typeIfLj4EES1_PfS1_S1_iS1_j
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z21updateDisplacements_kP15HIP_vector_typeIfLj4EES1_PfS1_S1_iS1_j
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
```
| 2,367 | 2,573 |
652 |
Convert the following CUDA device assembly code to AMD device assembly:
```cudaasm
code for sm_80
Function : _Z17modifyArrayKernelPiS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
MOV R1, c[0x0][0x28] ;
S2R R2, SR_CTAID.X ;
S2R R3, SR_TID.X ;
IMAD R2, R2, c[0x0][0x0], R3 ;
ISETP.GT.AND P0, PT, R2, 0x5, PT ;
@P0 EXIT ;
HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ;
ULDC.64 UR4, c[0x0][0x118] ;
IMAD.WIDE R2, R2, R3, c[0x0][0x168] ;
LDG.E R0, [R2.64] ;
ISETP.GE.AND P0, PT, R0, RZ, PT ;
@!P0 EXIT ;
MOV R5, c[0x0][0x164] ;
IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x160] ;
LDG.E R5, [R4.64] ;
IMAD.IADD R7, R0, 0x1, -R5 ;
STG.E [R2.64], R7 ;
EXIT ;
BRA 0x120;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
```
|
```amdasm
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z17modifyArrayKernelPiS_ ; -- Begin function _Z17modifyArrayKernelPiS_
.globl _Z17modifyArrayKernelPiS_
.p2align 8
.type _Z17modifyArrayKernelPiS_,@function
_Z17modifyArrayKernelPiS_: ; @_Z17modifyArrayKernelPiS_
; %bb.0:
s_load_b32 s2, s[0:1], 0x1c
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e32 6, v1
s_cbranch_execz .LBB0_3
; %bb.1:
s_load_b128 s[0:3], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_load_b32 v2, v[0:1], off
s_waitcnt vmcnt(0)
v_cmp_lt_i32_e32 vcc_lo, -1, v2
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_3
; %bb.2:
s_load_b32 s0, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
v_subrev_nc_u32_e32 v2, s0, v2
global_store_b32 v[0:1], v2, off
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z17modifyArrayKernelPiS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z17modifyArrayKernelPiS_, .Lfunc_end0-_Z17modifyArrayKernelPiS_
; -- End function
.section .AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 148
; NumSgprs: 18
; NumVgprs: 3
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 3
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object ; @__hip_cuid_
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0 ; 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z17modifyArrayKernelPiS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z17modifyArrayKernelPiS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
```
| 412 | 2,433 |
653 |
Convert the following CUDA host assembly code to AMD host assembly:
```cudaasm
.file "tmpxft_0003ea3d_00000000-6_modifyArrayKernel.cudafe1.cpp"
.text
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z39__device_stub__Z17modifyArrayKernelPiS_PiS_
.type _Z39__device_stub__Z17modifyArrayKernelPiS_PiS_, @function
_Z39__device_stub__Z17modifyArrayKernelPiS_PiS_:
.LFB2051:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z17modifyArrayKernelPiS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z39__device_stub__Z17modifyArrayKernelPiS_PiS_, .-_Z39__device_stub__Z17modifyArrayKernelPiS_PiS_
.globl _Z17modifyArrayKernelPiS_
.type _Z17modifyArrayKernelPiS_, @function
_Z17modifyArrayKernelPiS_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z39__device_stub__Z17modifyArrayKernelPiS_PiS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z17modifyArrayKernelPiS_, .-_Z17modifyArrayKernelPiS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z17modifyArrayKernelPiS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z17modifyArrayKernelPiS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
```
|
```amdasm
.text
.file "modifyArrayKernel.hip"
.globl _Z32__device_stub__modifyArrayKernelPiS_ # -- Begin function _Z32__device_stub__modifyArrayKernelPiS_
.type _Z32__device_stub__modifyArrayKernelPiS_,@function
_Z32__device_stub__modifyArrayKernelPiS_: # @_Z32__device_stub__modifyArrayKernelPiS_
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $80, %rsp
.cfi_def_cfa_offset 128
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 24(%rsp), %rax
movq %rdi, (%rax)
leaq 16(%rsp), %rcx
movq %rsi, (%rcx)
leaq 64(%rsp), %rbx
movq %rax, (%rbx)
movq %rcx, 8(%rbx)
leaq 48(%rsp), %r14
leaq 32(%rsp), %r15
leaq 8(%rsp), %r12
movq %rsp, %r13
movq %r14, %rdi
movq %r15, %rsi
movq %r12, %rdx
movq %r13, %rcx
callq __hipPopCallConfiguration
movq (%r14), %rsi
movl 8(%r14), %edx
movq (%r15), %rcx
movl 8(%r15), %r8d
movl $_Z17modifyArrayKernelPiS_, %edi
movq %rbx, %r9
pushq (%r13)
.cfi_adjust_cfa_offset 8
pushq (%r12)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $96, %rsp
.cfi_adjust_cfa_offset -96
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z32__device_stub__modifyArrayKernelPiS_, .Lfunc_end0-_Z32__device_stub__modifyArrayKernelPiS_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, %rdi
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z17modifyArrayKernelPiS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z17modifyArrayKernelPiS_,@object # @_Z17modifyArrayKernelPiS_
.section .rodata,"a",@progbits
.globl _Z17modifyArrayKernelPiS_
.p2align 3, 0x0
_Z17modifyArrayKernelPiS_:
.quad _Z32__device_stub__modifyArrayKernelPiS_
.size _Z17modifyArrayKernelPiS_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z17modifyArrayKernelPiS_"
.size .L__unnamed_1, 26
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z32__device_stub__modifyArrayKernelPiS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z17modifyArrayKernelPiS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
```
| 1,788 | 1,971 |
660 |
Convert the following CUDA device assembly code to AMD device assembly:
```cudaasm
code for sm_80
Function : _Z34gpu_calculate_potential_differenceiiPKdS0_Pd
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ;
S2R R25, SR_TID.X ;
IMAD.MOV.U32 R24, RZ, RZ, c[0x0][0x164] ;
ULDC.64 UR6, c[0x0][0x118] ;
CS2R R2, SRZ ;
ISETP.GE.AND P0, PT, R24, 0x1, PT ;
STS.64 [R25.X8], RZ ;
IMAD.SHL.U32 R0, R25, 0x8, RZ ;
@!P0 BRA 0x410 ;
IADD3 R2, R24.reuse, -0x1, RZ ;
IMAD.MOV.U32 R27, RZ, RZ, RZ ;
LOP3.LUT R24, R24, 0x3, RZ, 0xc0, !PT ;
ISETP.GE.U32.AND P1, PT, R2, 0x3, PT ;
ISETP.NE.AND P0, PT, R24, RZ, PT ;
CS2R R2, SRZ ;
@!P1 BRA 0x330 ;
IADD3 R28, R25, 0xc00, RZ ;
IMAD.MOV.U32 R27, RZ, RZ, RZ ;
IADD3 R26, R24, -c[0x0][0x164], RZ ;
CS2R R2, SRZ ;
IADD3 R20, R28.reuse, -0xc00, RZ ;
IMAD.MOV.U32 R21, RZ, RZ, 0x8 ;
IADD3 R4, R28, -0x800, RZ ;
ISETP.GE.AND P2, PT, R20.reuse, c[0x0][0x160], PT ;
IMAD.WIDE R16, R20, R21.reuse, c[0x0][0x170] ;
ISETP.GE.AND P3, PT, R4, c[0x0][0x160], PT ;
IADD3 R4, R28, -0x400, RZ ;
IMAD.WIDE R20, R20, R21, c[0x0][0x168] ;
ISETP.GE.AND P4, PT, R4, c[0x0][0x160], PT ;
@!P2 LDG.E.64 R4, [R16.64] ;
@!P2 LDG.E.64 R6, [R20.64] ;
ISETP.GE.AND P1, PT, R28, c[0x0][0x160], PT ;
@!P3 LDG.E.64 R8, [R20.64+0x2000] ;
@!P3 LDG.E.64 R10, [R16.64+0x2000] ;
@!P4 LDG.E.64 R12, [R20.64+0x4000] ;
@!P4 LDG.E.64 R14, [R16.64+0x4000] ;
@!P1 LDG.E.64 R18, [R20.64+0x6000] ;
@!P1 LDG.E.64 R22, [R16.64+0x6000] ;
IADD3 R27, R27, 0x4, RZ ;
IADD3 R28, R28, 0x1000, RZ ;
@!P2 DADD R4, R4, -R6 ;
@!P2 DADD R2, R2, R4 ;
IMAD.IADD R4, R26, 0x1, R27 ;
@!P3 DADD R8, -R8, R10 ;
ISETP.NE.AND P2, PT, R4, RZ, PT ;
@!P3 DADD R2, R2, R8 ;
@!P4 DADD R12, -R12, R14 ;
@!P1 DADD R18, -R18, R22 ;
@!P4 DADD R2, R2, R12 ;
@!P1 DADD R2, R2, R18 ;
@P2 BRA 0x140 ;
@!P0 BRA 0x410 ;
IMAD R27, R27, 0x400, R25 ;
ISETP.GE.AND P0, PT, R27, c[0x0][0x160], PT ;
@!P0 IMAD.MOV.U32 R6, RZ, RZ, 0x8 ;
@!P0 IMAD.WIDE R4, R27, R6, c[0x0][0x170] ;
@!P0 IMAD.WIDE R6, R27.reuse, R6, c[0x0][0x168] ;
@!P0 LDG.E.64 R4, [R4.64] ;
@!P0 LDG.E.64 R6, [R6.64] ;
IADD3 R24, R24, -0x1, RZ ;
IADD3 R27, R27, 0x400, RZ ;
ISETP.NE.AND P1, PT, R24, RZ, PT ;
@!P0 DADD R8, -R6, R4 ;
@!P0 DADD R2, R2, R8 ;
@P1 BRA 0x350 ;
ULDC UR4, c[0x0][0x0] ;
STS.64 [R25.X8], R2 ;
USHF.R.U32.HI UR4, URZ, 0x1, UR4 ;
BAR.SYNC.DEFER_BLOCKING 0x0 ;
ISETP.NE.AND P1, PT, R25, RZ, PT ;
ISETP.NE.AND P0, PT, RZ, UR4, PT ;
@!P0 BRA 0x530 ;
IMAD.U32 R6, RZ, RZ, UR4 ;
ISETP.GE.U32.AND P0, PT, R25, R6, PT ;
@!P0 IMAD R4, R6, 0x8, R0 ;
@!P0 LDS.64 R2, [R25.X8] ;
SHF.R.U32.HI R6, RZ, 0x1, R6 ;
@!P0 LDS.64 R4, [R4] ;
@!P0 DADD R2, R2, R4 ;
@!P0 STS.64 [R25.X8], R2 ;
BAR.SYNC.DEFER_BLOCKING 0x0 ;
ISETP.NE.AND P0, PT, R6, RZ, PT ;
@P0 BRA 0x490 ;
@P1 EXIT ;
LDS.64 R2, [RZ] ;
IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x178] ;
IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x17c] ;
STG.E.64 [R4.64], R2 ;
EXIT ;
BRA 0x590;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
```
|
```amdasm
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z34gpu_calculate_potential_differenceiiPKdS0_Pd ; -- Begin function _Z34gpu_calculate_potential_differenceiiPKdS0_Pd
.globl _Z34gpu_calculate_potential_differenceiiPKdS0_Pd
.p2align 8
.type _Z34gpu_calculate_potential_differenceiiPKdS0_Pd,@function
_Z34gpu_calculate_potential_differenceiiPKdS0_Pd: ; @_Z34gpu_calculate_potential_differenceiiPKdS0_Pd
; %bb.0:
s_clause 0x2
s_load_b64 s[8:9], s[0:1], 0x0
s_load_b128 s[4:7], s[0:1], 0x8
s_load_b64 s[2:3], s[0:1], 0x18
v_mov_b32_e32 v1, 0
v_mov_b32_e32 v2, 0
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s9, 1
s_cbranch_scc1 .LBB0_5
; %bb.1: ; %.lr.ph.preheader
v_dual_mov_b32 v4, 0 :: v_dual_mov_b32 v3, v0
.LBB0_2: ; %.lr.ph
; =>This Inner Loop Header: Depth=1
s_mov_b32 s10, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s8, v3
s_cbranch_execz .LBB0_4
; %bb.3: ; in Loop: Header=BB0_2 Depth=1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[5:6], 3, v[3:4]
v_add_co_u32 v7, vcc_lo, s6, v5
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v8, vcc_lo, s7, v6, vcc_lo
v_add_co_u32 v5, vcc_lo, s4, v5
v_add_co_ci_u32_e32 v6, vcc_lo, s5, v6, vcc_lo
global_load_b64 v[7:8], v[7:8], off
global_load_b64 v[5:6], v[5:6], off
s_waitcnt vmcnt(0)
v_add_f64 v[5:6], v[7:8], -v[5:6]
s_delay_alu instid0(VALU_DEP_1)
v_add_f64 v[1:2], v[1:2], v[5:6]
.LBB0_4: ; in Loop: Header=BB0_2 Depth=1
s_or_b32 exec_lo, exec_lo, s10
v_add_nc_u32_e32 v3, 0x400, v3
s_add_i32 s9, s9, -1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s9, 0
s_cbranch_scc0 .LBB0_2
.LBB0_5: ; %._crit_edge
v_lshlrev_b32_e32 v3, 3, v0
ds_store_b64 v3, v[1:2]
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_load_b32 s0, s[0:1], 0x2c
s_waitcnt lgkmcnt(0)
s_and_b32 s0, s0, 0xffff
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_lt_u32 s0, 2
s_cbranch_scc1 .LBB0_10
; %bb.6: ; %.lr.ph28.preheader
s_lshr_b32 s0, s0, 1
.LBB0_7: ; %.lr.ph28
; =>This Inner Loop Header: Depth=1
s_mov_b32 s1, exec_lo
v_cmpx_gt_u32_e64 s0, v0
s_cbranch_execz .LBB0_9
; %bb.8: ; in Loop: Header=BB0_7 Depth=1
v_lshl_add_u32 v1, s0, 3, v3
ds_load_b64 v[1:2], v1
ds_load_b64 v[4:5], v3
s_waitcnt lgkmcnt(0)
v_add_f64 v[1:2], v[1:2], v[4:5]
ds_store_b64 v3, v[1:2]
.LBB0_9: ; in Loop: Header=BB0_7 Depth=1
s_or_b32 exec_lo, exec_lo, s1
s_lshr_b32 s1, s0, 1
s_cmp_lt_u32 s0, 2
s_mov_b32 s0, s1
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc0 .LBB0_7
.LBB0_10: ; %._crit_edge29
s_mov_b32 s0, exec_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB0_12
; %bb.11:
v_mov_b32_e32 v2, 0
ds_load_b64 v[0:1], v2
s_waitcnt lgkmcnt(0)
global_store_b64 v2, v[0:1], s[2:3]
.LBB0_12:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z34gpu_calculate_potential_differenceiiPKdS0_Pd
.amdhsa_group_segment_fixed_size 8192
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 11
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z34gpu_calculate_potential_differenceiiPKdS0_Pd, .Lfunc_end0-_Z34gpu_calculate_potential_differenceiiPKdS0_Pd
; -- End function
.section .AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 392
; NumSgprs: 13
; NumVgprs: 9
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 8192 bytes/workgroup (compile time only)
; SGPRBlocks: 1
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 13
; NumVGPRsForWavesPerEU: 9
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object ; @__hip_cuid_
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0 ; 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 8192
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z34gpu_calculate_potential_differenceiiPKdS0_Pd
.private_segment_fixed_size: 0
.sgpr_count: 13
.sgpr_spill_count: 0
.symbol: _Z34gpu_calculate_potential_differenceiiPKdS0_Pd.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
```
| 1,899 | 3,398 |
661 |
Convert the following CUDA host assembly code to AMD host assembly:
```cudaasm
.file "tmpxft_000fb809_00000000-6_gpu_calculate_potential_difference.cudafe1.cpp"
.text
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z62__device_stub__Z34gpu_calculate_potential_differenceiiPKdS0_PdiiPKdS0_Pd
.type _Z62__device_stub__Z34gpu_calculate_potential_differenceiiPKdS0_PdiiPKdS0_Pd, @function
_Z62__device_stub__Z34gpu_calculate_potential_differenceiiPKdS0_PdiiPKdS0_Pd:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 28(%rsp)
movl %esi, 24(%rsp)
movq %rdx, 16(%rsp)
movq %rcx, 8(%rsp)
movq %r8, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 24(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z34gpu_calculate_potential_differenceiiPKdS0_Pd(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z62__device_stub__Z34gpu_calculate_potential_differenceiiPKdS0_PdiiPKdS0_Pd, .-_Z62__device_stub__Z34gpu_calculate_potential_differenceiiPKdS0_PdiiPKdS0_Pd
.globl _Z34gpu_calculate_potential_differenceiiPKdS0_Pd
.type _Z34gpu_calculate_potential_differenceiiPKdS0_Pd, @function
_Z34gpu_calculate_potential_differenceiiPKdS0_Pd:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z62__device_stub__Z34gpu_calculate_potential_differenceiiPKdS0_PdiiPKdS0_Pd
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z34gpu_calculate_potential_differenceiiPKdS0_Pd, .-_Z34gpu_calculate_potential_differenceiiPKdS0_Pd
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z34gpu_calculate_potential_differenceiiPKdS0_Pd"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z34gpu_calculate_potential_differenceiiPKdS0_Pd(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
```
|
```amdasm
.text
.file "gpu_calculate_potential_difference.hip"
.globl _Z49__device_stub__gpu_calculate_potential_differenceiiPKdS0_Pd # -- Begin function _Z49__device_stub__gpu_calculate_potential_differenceiiPKdS0_Pd
.type _Z49__device_stub__gpu_calculate_potential_differenceiiPKdS0_Pd,@function
_Z49__device_stub__gpu_calculate_potential_differenceiiPKdS0_Pd: # @_Z49__device_stub__gpu_calculate_potential_differenceiiPKdS0_Pd
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $128, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 4(%rsp), %rax
movl %edi, (%rax)
movq %rsp, %rdi
movl %esi, (%rdi)
leaq 40(%rsp), %rsi
movq %rdx, (%rsi)
leaq 32(%rsp), %rdx
movq %rcx, (%rdx)
leaq 24(%rsp), %rcx
movq %r8, (%rcx)
leaq 80(%rsp), %rbx
movq %rax, (%rbx)
movq %rdi, 8(%rbx)
movq %rsi, 16(%rbx)
movq %rdx, 24(%rbx)
movq %rcx, 32(%rbx)
leaq 64(%rsp), %r14
leaq 48(%rsp), %r15
leaq 16(%rsp), %r12
leaq 8(%rsp), %r13
movq %r14, %rdi
movq %r15, %rsi
movq %r12, %rdx
movq %r13, %rcx
callq __hipPopCallConfiguration
movq (%r14), %rsi
movl 8(%r14), %edx
movq (%r15), %rcx
movl 8(%r15), %r8d
movl $_Z34gpu_calculate_potential_differenceiiPKdS0_Pd, %edi
movq %rbx, %r9
pushq (%r13)
.cfi_adjust_cfa_offset 8
pushq (%r12)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $144, %rsp
.cfi_adjust_cfa_offset -144
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z49__device_stub__gpu_calculate_potential_differenceiiPKdS0_Pd, .Lfunc_end0-_Z49__device_stub__gpu_calculate_potential_differenceiiPKdS0_Pd
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, %rdi
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z34gpu_calculate_potential_differenceiiPKdS0_Pd, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z34gpu_calculate_potential_differenceiiPKdS0_Pd,@object # @_Z34gpu_calculate_potential_differenceiiPKdS0_Pd
.section .rodata,"a",@progbits
.globl _Z34gpu_calculate_potential_differenceiiPKdS0_Pd
.p2align 3, 0x0
_Z34gpu_calculate_potential_differenceiiPKdS0_Pd:
.quad _Z49__device_stub__gpu_calculate_potential_differenceiiPKdS0_Pd
.size _Z34gpu_calculate_potential_differenceiiPKdS0_Pd, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z34gpu_calculate_potential_differenceiiPKdS0_Pd"
.size .L__unnamed_1, 49
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z49__device_stub__gpu_calculate_potential_differenceiiPKdS0_Pd
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z34gpu_calculate_potential_differenceiiPKdS0_Pd
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
```
| 2,041 | 2,227 |
662 |
Convert the following CUDA device assembly code to AMD device assembly:
```cudaasm
code for sm_80
Function : _Z11touchMemoryPf
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
MOV R1, c[0x0][0x28] ;
EXIT ;
BRA 0x20;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
```
|
```amdasm
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z11touchMemoryPf ; -- Begin function _Z11touchMemoryPf
.globl _Z11touchMemoryPf
.p2align 8
.type _Z11touchMemoryPf,@function
_Z11touchMemoryPf: ; @_Z11touchMemoryPf
; %bb.0:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11touchMemoryPf
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 8
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 1
.amdhsa_next_free_sgpr 1
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z11touchMemoryPf, .Lfunc_end0-_Z11touchMemoryPf
; -- End function
.section .AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 4
; NumSgprs: 0
; NumVgprs: 0
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 0
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 1
; NumVGPRsForWavesPerEU: 1
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object ; @__hip_cuid_
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0 ; 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 8
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11touchMemoryPf
.private_segment_fixed_size: 0
.sgpr_count: 0
.sgpr_spill_count: 0
.symbol: _Z11touchMemoryPf.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 0
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
```
| 121 | 1,522 |
663 |
Convert the following CUDA host assembly code to AMD host assembly:
```cudaasm
.file "tmpxft_001941b4_00000000-6_kernels.cudafe1.cpp"
.text
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z31__device_stub__Z11touchMemoryPfPf
.type _Z31__device_stub__Z11touchMemoryPfPf, @function
_Z31__device_stub__Z11touchMemoryPfPf:
.LFB2051:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z11touchMemoryPf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z31__device_stub__Z11touchMemoryPfPf, .-_Z31__device_stub__Z11touchMemoryPfPf
.globl _Z11touchMemoryPf
.type _Z11touchMemoryPf, @function
_Z11touchMemoryPf:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z31__device_stub__Z11touchMemoryPfPf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z11touchMemoryPf, .-_Z11touchMemoryPf
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z11touchMemoryPf"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z11touchMemoryPf(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
```
|
```amdasm
.text
.file "kernels.hip"
.globl _Z26__device_stub__touchMemoryPf # -- Begin function _Z26__device_stub__touchMemoryPf
.type _Z26__device_stub__touchMemoryPf,@function
_Z26__device_stub__touchMemoryPf: # @_Z26__device_stub__touchMemoryPf
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $64, %rsp
.cfi_def_cfa_offset 112
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 24(%rsp), %rax
movq %rdi, (%rax)
movq %rsp, %rbx
movq %rax, (%rbx)
leaq 48(%rsp), %r14
leaq 32(%rsp), %r15
leaq 16(%rsp), %r12
leaq 8(%rsp), %r13
movq %r14, %rdi
movq %r15, %rsi
movq %r12, %rdx
movq %r13, %rcx
callq __hipPopCallConfiguration
movq (%r14), %rsi
movl 8(%r14), %edx
movq (%r15), %rcx
movl 8(%r15), %r8d
movl $_Z11touchMemoryPf, %edi
movq %rbx, %r9
pushq (%r13)
.cfi_adjust_cfa_offset 8
pushq (%r12)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $80, %rsp
.cfi_adjust_cfa_offset -80
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z26__device_stub__touchMemoryPf, .Lfunc_end0-_Z26__device_stub__touchMemoryPf
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, %rdi
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11touchMemoryPf, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z11touchMemoryPf,@object # @_Z11touchMemoryPf
.section .rodata,"a",@progbits
.globl _Z11touchMemoryPf
.p2align 3, 0x0
_Z11touchMemoryPf:
.quad _Z26__device_stub__touchMemoryPf
.size _Z11touchMemoryPf, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z11touchMemoryPf"
.size .L__unnamed_1, 18
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z26__device_stub__touchMemoryPf
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z11touchMemoryPf
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
```
| 1,730 | 1,911 |
670 |
Convert the following CUDA device assembly code to AMD device assembly:
```cudaasm
code for sm_80
Function : _Z12mandelKernelffffPiiii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
MOV R1, c[0x0][0x28] ;
S2R R3, SR_CTAID.Y ;
S2R R2, SR_TID.Y ;
S2R R0, SR_CTAID.X ;
S2R R5, SR_TID.X ;
IMAD R3, R3, c[0x0][0x4], R2 ;
ISETP.GE.AND P0, PT, R3, c[0x0][0x17c], PT ;
IMAD R0, R0, c[0x0][0x0], R5 ;
ISETP.GE.OR P0, PT, R0, c[0x0][0x178], P0 ;
@P0 EXIT ;
I2F R2, R0 ;
MOV R5, c[0x0][0x180] ;
ULDC.64 UR4, c[0x0][0x118] ;
MOV R7, c[0x0][0x168] ;
ISETP.GE.AND P0, PT, R5, 0x1, PT ;
IMAD R5, R3, c[0x0][0x178], R0 ;
MOV R9, c[0x0][0x16c] ;
I2F R4, R3 ;
FFMA R2, R2, R7, c[0x0][0x160] ;
HFMA2.MMA R7, -RZ, RZ, 0, 0 ;
FFMA R4, R4, R9, c[0x0][0x164] ;
@!P0 BRA 0x270 ;
BSSY B0, 0x270 ;
MOV R7, RZ ;
MOV R3, R4 ;
MOV R0, R2 ;
FMUL R9, R3, R3 ;
FMUL R6, R0, R0 ;
FADD R8, R9, R6 ;
FSETP.GT.AND P0, PT, R8, 4, PT ;
@P0 BRA 0x260 ;
IADD3 R7, R7, 0x1, RZ ;
FADD R0, R0, R0 ;
FADD R9, -R9, R6 ;
ISETP.GE.AND P0, PT, R7, c[0x0][0x180], PT ;
FFMA R3, R0, R3, R4 ;
FADD R0, R2, R9 ;
@!P0 BRA 0x1a0 ;
BSYNC B0 ;
MOV R2, 0x4 ;
IMAD.WIDE R2, R5, R2, c[0x0][0x170] ;
STG.E [R2.64], R7 ;
EXIT ;
BRA 0x2b0;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
```
|
```amdasm
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z12mandelKernelffffPiiii ; -- Begin function _Z12mandelKernelffffPiiii
.globl _Z12mandelKernelffffPiiii
.p2align 8
.type _Z12mandelKernelffffPiiii,@function
_Z12mandelKernelffffPiiii: ; @_Z12mandelKernelffffPiiii
; %bb.0:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x34
s_load_b128 s[4:7], s[0:1], 0x18
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_lshr_b32 s3, s2, 16
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[0:1], null, s14, s2, v[2:3]
v_mad_u64_u32 v[1:2], null, s15, s3, v[3:4]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_gt_i32_e32 vcc_lo, s4, v0
v_cmp_gt_i32_e64 s2, s5, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, vcc_lo, s2
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_9
; %bb.1:
s_cmp_lt_i32 s6, 1
s_cbranch_scc1 .LBB0_7
; %bb.2: ; %.lr.ph.i.preheader
s_load_b128 s[8:11], s[0:1], 0x0
v_cvt_f32_i32_e32 v2, v0
v_cvt_f32_i32_e32 v3, v1
s_mov_b32 s2, 0
s_mov_b32 s3, 0
; implicit-def: $sgpr5
s_waitcnt lgkmcnt(0)
v_fma_f32 v2, v2, s10, s8
v_fma_f32 v3, v3, s11, s9
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mov_b32_e32 v6, v2
v_mov_b32_e32 v4, v3
.LBB0_3: ; %.lr.ph.i
; =>This Inner Loop Header: Depth=1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mul_f32_e32 v7, v4, v4
s_or_b32 s5, s5, exec_lo
v_fma_f32 v5, v6, v6, v7
s_delay_alu instid0(VALU_DEP_1)
v_cmp_nlt_f32_e32 vcc_lo, 4.0, v5
v_mov_b32_e32 v5, s3
s_and_saveexec_b32 s7, vcc_lo
s_cbranch_execz .LBB0_5
; %bb.4: ; in Loop: Header=BB0_3 Depth=1
v_mul_f32_e32 v5, v6, v6
v_add_f32_e32 v6, v6, v6
s_add_i32 s3, s3, 1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
s_cmp_eq_u32 s6, s3
v_sub_f32_e32 v7, v5, v7
s_cselect_b32 s8, -1, 0
v_mov_b32_e32 v5, s6
v_fma_f32 v4, v4, v6, v3
s_and_not1_b32 s5, s5, exec_lo
v_add_f32_e32 v6, v2, v7
s_and_b32 s8, s8, exec_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 s5, s5, s8
.LBB0_5: ; %Flow
; in Loop: Header=BB0_3 Depth=1
s_or_b32 exec_lo, exec_lo, s7
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s7, exec_lo, s5
s_or_b32 s2, s7, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s2
s_cbranch_execnz .LBB0_3
; %bb.6: ; %Flow47
s_or_b32 exec_lo, exec_lo, s2
s_branch .LBB0_8
.LBB0_7:
v_mov_b32_e32 v5, 0
.LBB0_8: ; %_Z6mandelffi.exit
s_load_b64 s[0:1], s[0:1], 0x10
v_mad_u64_u32 v[2:3], null, v1, s4, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[0:1], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v5, off
.LBB0_9:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z12mandelKernelffffPiiii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z12mandelKernelffffPiiii, .Lfunc_end0-_Z12mandelKernelffffPiiii
; -- End function
.section .AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 380
; NumSgprs: 18
; NumVgprs: 8
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 8
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object ; @__hip_cuid_
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0 ; 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z12mandelKernelffffPiiii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z12mandelKernelffffPiiii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
```
| 745 | 3,657 |
671 |
Convert the following CUDA host assembly code to AMD host assembly:
```cudaasm
.file "tmpxft_0001d0b5_00000000-6_kernel2.cudafe1.cpp"
.text
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z6mandelffi
.type _Z6mandelffi, @function
_Z6mandelffi:
.LFB2057:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2057:
.size _Z6mandelffi, .-_Z6mandelffi
.globl _Z39__device_stub__Z12mandelKernelffffPiiiiffffPiiii
.type _Z39__device_stub__Z12mandelKernelffffPiiiiffffPiiii, @function
_Z39__device_stub__Z12mandelKernelffffPiiiiffffPiiii:
.LFB2083:
.cfi_startproc
endbr64
subq $200, %rsp
.cfi_def_cfa_offset 208
movss %xmm0, 44(%rsp)
movss %xmm1, 40(%rsp)
movss %xmm2, 36(%rsp)
movss %xmm3, 32(%rsp)
movq %rdi, 24(%rsp)
movl %esi, 20(%rsp)
movl %edx, 16(%rsp)
movl %ecx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
leaq 44(%rsp), %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rax
movq %rax, 120(%rsp)
leaq 36(%rsp), %rax
movq %rax, 128(%rsp)
leaq 32(%rsp), %rax
movq %rax, 136(%rsp)
leaq 24(%rsp), %rax
movq %rax, 144(%rsp)
leaq 20(%rsp), %rax
movq %rax, 152(%rsp)
leaq 16(%rsp), %rax
movq %rax, 160(%rsp)
leaq 12(%rsp), %rax
movq %rax, 168(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L9
.L5:
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L10
addq $200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L9:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 216
pushq 56(%rsp)
.cfi_def_cfa_offset 224
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z12mandelKernelffffPiiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 208
jmp .L5
.L10:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z39__device_stub__Z12mandelKernelffffPiiiiffffPiiii, .-_Z39__device_stub__Z12mandelKernelffffPiiiiffffPiiii
.globl _Z12mandelKernelffffPiiii
.type _Z12mandelKernelffffPiiii, @function
_Z12mandelKernelffffPiiii:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z39__device_stub__Z12mandelKernelffffPiiiiffffPiiii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z12mandelKernelffffPiiii, .-_Z12mandelKernelffffPiiii
.globl _Z6hostFEffffPiiii
.type _Z6hostFEffffPiiii, @function
_Z6hostFEffffPiiii:
.LFB2058:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $80, %rsp
.cfi_def_cfa_offset 128
movss %xmm0, (%rsp)
movss %xmm1, 4(%rsp)
movss %xmm2, 8(%rsp)
movss %xmm3, 12(%rsp)
movq %rdi, %r13
movl %esi, %ebp
movl %edx, %r12d
movl %ecx, %r14d
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
pxor %xmm0, %xmm0
cvtsi2sdl %esi, %xmm0
mulsd .LC0(%rip), %xmm0
movapd %xmm0, %xmm1
movsd .LC4(%rip), %xmm3
movapd %xmm0, %xmm2
andpd %xmm3, %xmm2
movsd .LC1(%rip), %xmm4
ucomisd %xmm2, %xmm4
jbe .L14
cvttsd2siq %xmm0, %rax
pxor %xmm2, %xmm2
cvtsi2sdq %rax, %xmm2
cmpnlesd %xmm2, %xmm1
movsd .LC3(%rip), %xmm4
andpd %xmm4, %xmm1
addsd %xmm2, %xmm1
andnpd %xmm0, %xmm3
orpd %xmm3, %xmm1
.L14:
pxor %xmm0, %xmm0
cvtsi2sdl %r12d, %xmm0
mulsd .LC0(%rip), %xmm0
movapd %xmm0, %xmm4
movsd .LC4(%rip), %xmm3
movapd %xmm0, %xmm2
andpd %xmm3, %xmm2
movsd .LC1(%rip), %xmm5
ucomisd %xmm2, %xmm5
jbe .L15
cvttsd2siq %xmm0, %rax
pxor %xmm2, %xmm2
cvtsi2sdq %rax, %xmm2
cmpnlesd %xmm2, %xmm4
movsd .LC3(%rip), %xmm5
andpd %xmm5, %xmm4
addsd %xmm2, %xmm4
andnpd %xmm0, %xmm3
orpd %xmm3, %xmm4
.L15:
movl $16, 48(%rsp)
movl $16, 52(%rsp)
movl $1, 56(%rsp)
cvttsd2sil %xmm1, %eax
movl %eax, 60(%rsp)
cvttsd2sil %xmm4, %eax
movl %eax, 64(%rsp)
movl $1, 68(%rsp)
movslq %r12d, %rcx
movslq %ebp, %rdx
salq $2, %rdx
leaq 40(%rsp), %rsi
leaq 24(%rsp), %rdi
call cudaMallocPitch@PLT
movl %ebp, %ebx
imull %r12d, %ebx
sall $2, %ebx
movslq %ebx, %rbx
leaq 32(%rsp), %rdi
movl $2, %edx
movq %rbx, %rsi
call cudaHostAlloc@PLT
movl 56(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 48(%rsp), %rdx
movq 60(%rsp), %rdi
movl 68(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L19
.L16:
call cudaDeviceSynchronize@PLT
movl $2, %ecx
movq %rbx, %rdx
movq 24(%rsp), %rsi
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
movq 32(%rsp), %rbp
movq %rbx, %rdx
movq %rbp, %rsi
movq %r13, %rdi
call memcpy@PLT
movq %rbp, %rdi
call cudaFreeHost@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L20
addq $80, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
movss 4(%rsp), %xmm3
movss 12(%rsp), %xmm6
subss %xmm6, %xmm3
pxor %xmm1, %xmm1
cvtsi2ssl %r12d, %xmm1
movss (%rsp), %xmm2
movss 8(%rsp), %xmm7
subss %xmm7, %xmm2
pxor %xmm0, %xmm0
cvtsi2ssl %ebp, %xmm0
movl %r14d, %ecx
movl %r12d, %edx
movl %ebp, %esi
movq 24(%rsp), %rdi
divss %xmm1, %xmm3
divss %xmm0, %xmm2
movaps %xmm6, %xmm1
movaps %xmm7, %xmm0
call _Z39__device_stub__Z12mandelKernelffffPiiiiffffPiiii
jmp .L16
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size _Z6hostFEffffPiiii, .-_Z6hostFEffffPiiii
.section .rodata.str1.1,"aMS",@progbits,1
.LC5:
.string "_Z12mandelKernelffffPiiii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _Z12mandelKernelffffPiiii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC0:
.long 0
.long 1068498944
.align 8
.LC1:
.long 0
.long 1127219200
.align 8
.LC3:
.long 0
.long 1072693248
.align 8
.LC4:
.long -1
.long 2147483647
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
```
|
```amdasm
.text
.file "kernel2.hip"
.globl _Z27__device_stub__mandelKernelffffPiiii # -- Begin function _Z27__device_stub__mandelKernelffffPiiii
.type _Z27__device_stub__mandelKernelffffPiiii,@function
_Z27__device_stub__mandelKernelffffPiiii: # @_Z27__device_stub__mandelKernelffffPiiii
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $160, %rsp
.cfi_def_cfa_offset 208
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 36(%rsp), %rax
movss %xmm0, (%rax)
leaq 32(%rsp), %r8
movss %xmm1, (%r8)
leaq 28(%rsp), %r9
movss %xmm2, (%r9)
leaq 24(%rsp), %r10
movss %xmm3, (%r10)
leaq 56(%rsp), %r11
movq %rdi, (%r11)
leaq 20(%rsp), %rdi
movl %esi, (%rdi)
leaq 16(%rsp), %rsi
movl %edx, (%rsi)
leaq 12(%rsp), %rdx
movl %ecx, (%rdx)
leaq 96(%rsp), %rbx
movq %rax, (%rbx)
movq %r8, 8(%rbx)
movq %r9, 16(%rbx)
movq %r10, 24(%rbx)
movq %r11, 32(%rbx)
movq %rdi, 40(%rbx)
movq %rsi, 48(%rbx)
movq %rdx, 56(%rbx)
leaq 80(%rsp), %r14
leaq 64(%rsp), %r15
leaq 48(%rsp), %r12
leaq 40(%rsp), %r13
movq %r14, %rdi
movq %r15, %rsi
movq %r12, %rdx
movq %r13, %rcx
callq __hipPopCallConfiguration
movq (%r14), %rsi
movl 8(%r14), %edx
movq (%r15), %rcx
movl 8(%r15), %r8d
movl $_Z12mandelKernelffffPiiii, %edi
movq %rbx, %r9
pushq (%r13)
.cfi_adjust_cfa_offset 8
pushq (%r12)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $176, %rsp
.cfi_adjust_cfa_offset -176
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z27__device_stub__mandelKernelffffPiiii, .Lfunc_end0-_Z27__device_stub__mandelKernelffffPiiii
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z6hostFEffffPiiii
.LCPI1_0:
.quad 0x3fb0000000000000 # double 0.0625
.text
.globl _Z6hostFEffffPiiii
.type _Z6hostFEffffPiiii,@function
_Z6hostFEffffPiiii: # @_Z6hostFEffffPiiii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $40, %rsp
.cfi_def_cfa_offset 96
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %ecx, %ebp
movl %edx, %r14d
movl %esi, %r15d
movq %rdi, %rbx
movss %xmm3, 20(%rsp) # 4-byte Spill
movss %xmm2, 12(%rsp) # 4-byte Spill
movss %xmm1, 16(%rsp) # 4-byte Spill
movss %xmm0, 8(%rsp) # 4-byte Spill
xorps %xmm0, %xmm0
cvtsi2sd %esi, %xmm0
mulsd .LCPI1_0(%rip), %xmm0
callq ceil@PLT
cvttsd2si %xmm0, %r12d
xorps %xmm0, %xmm0
cvtsi2sd %r14d, %xmm0
mulsd .LCPI1_0(%rip), %xmm0
callq ceil@PLT
cvttsd2si %xmm0, %r13d
shlq $32, %r13
orq %r12, %r13
movl %r15d, %r12d
imull %r14d, %r12d
shll $2, %r12d
movslq %r15d, %rdx
shlq $2, %rdx
movslq %r14d, %rcx
movq %rsp, %rdi
leaq 32(%rsp), %rsi
callq hipMallocPitch
movslq %r12d, %r12
leaq 24(%rsp), %rdi
movq %r12, %rsi
movl $2, %edx
callq hipHostAlloc
movabsq $68719476752, %rdx # imm = 0x1000000010
movq %r13, %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
xorps %xmm0, %xmm0
cvtsi2ss %r14d, %xmm0
movss 20(%rsp), %xmm1 # 4-byte Reload
# xmm1 = mem[0],zero,zero,zero
movss 16(%rsp), %xmm3 # 4-byte Reload
# xmm3 = mem[0],zero,zero,zero
subss %xmm1, %xmm3
cvtsi2ss %r15d, %xmm4
divss %xmm0, %xmm3
movss 12(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
movss 8(%rsp), %xmm2 # 4-byte Reload
# xmm2 = mem[0],zero,zero,zero
subss %xmm0, %xmm2
divss %xmm4, %xmm2
movq (%rsp), %rdi
movl %r15d, %esi
movl %r14d, %edx
movl %ebp, %ecx
callq _Z27__device_stub__mandelKernelffffPiiii
.LBB1_2:
callq hipDeviceSynchronize
movq 24(%rsp), %rdi
movq (%rsp), %rsi
movq %r12, %rdx
movl $2, %ecx
callq hipMemcpy
movq 24(%rsp), %r14
movq %rbx, %rdi
movq %r14, %rsi
movq %r12, %rdx
callq memcpy@PLT
movq %r14, %rdi
callq hipHostFree
movq (%rsp), %rdi
callq hipFree
addq $40, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z6hostFEffffPiiii, .Lfunc_end1-_Z6hostFEffffPiiii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, %rdi
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12mandelKernelffffPiiii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z12mandelKernelffffPiiii,@object # @_Z12mandelKernelffffPiiii
.section .rodata,"a",@progbits
.globl _Z12mandelKernelffffPiiii
.p2align 3, 0x0
_Z12mandelKernelffffPiiii:
.quad _Z27__device_stub__mandelKernelffffPiiii
.size _Z12mandelKernelffffPiiii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z12mandelKernelffffPiiii"
.size .L__unnamed_1, 26
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z27__device_stub__mandelKernelffffPiiii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z12mandelKernelffffPiiii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
```
| 4,162 | 3,831 |
672 |
Convert the following CUDA device assembly code to AMD device assembly:
```cudaasm
code for sm_80
Function : _Z6modcpyPvS_mm
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ;
S2R R3, SR_CTAID.X ;
ULDC.64 UR4, c[0x0][0x170] ;
USHF.R.U64 UR4, UR4, 0x4, UR5 ;
S2R R0, SR_TID.X ;
IMAD R3, R3, c[0x0][0x0], R0 ;
ISETP.GE.AND P0, PT, R3, UR4, PT ;
@P0 EXIT ;
ULDC UR5, c[0x0][0x178] ;
IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x17c] ;
MOV R5, UR5 ;
ULDC.64 UR6, c[0x0][0x118] ;
SHF.R.U64 R0, R5, 0x4, R0 ;
IABS R2, R0.reuse ;
ISETP.NE.AND P0, PT, R0, RZ, PT ;
I2F.U32.RP R6, R2 ;
LOP3.LUT R12, RZ, R0, RZ, 0x33, !PT ;
MUFU.RCP R6, R6 ;
IADD3 R4, R6, 0xffffffe, RZ ;
F2I.FTZ.U32.TRUNC.NTZ R5, R4 ;
IMAD.MOV.U32 R4, RZ, RZ, RZ ;
IMAD.MOV R7, RZ, RZ, -R5 ;
IMAD R7, R7, R2, RZ ;
IMAD.HI.U32 R10, R5, R7, R4 ;
IABS R4, R0 ;
IMAD.MOV.U32 R8, RZ, RZ, 0x10 ;
IABS R5, R3 ;
IADD3 R6, RZ, -R4, RZ ;
ISETP.GE.AND P2, PT, R3, RZ, PT ;
IMAD.HI.U32 R4, R10, R5, RZ ;
IMAD R5, R4, R6, R5 ;
IABS R4, R0 ;
ISETP.GT.U32.AND P1, PT, R2, R5, PT ;
@!P1 IMAD.IADD R5, R5, 0x1, -R4 ;
ISETP.GT.U32.AND P1, PT, R2, R5, PT ;
@!P1 IMAD.IADD R5, R5, 0x1, -R4 ;
@!P2 IADD3 R5, -R5, RZ, RZ ;
SEL R5, R12, R5, !P0 ;
IMAD.WIDE R4, R5, R8, c[0x0][0x168] ;
LDG.E.128 R4, [R4.64] ;
IMAD.WIDE R8, R3, R8, c[0x0][0x160] ;
MOV R14, c[0x0][0xc] ;
IMAD R3, R14, c[0x0][0x0], R3 ;
ISETP.GE.AND P1, PT, R3, UR4, PT ;
STG.E.128 [R8.64], R4 ;
@!P1 BRA 0x180 ;
EXIT ;
BRA 0x2f0;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
```
|
```amdasm
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6modcpyPvS_mm ; -- Begin function _Z6modcpyPvS_mm
.globl _Z6modcpyPvS_mm
.p2align 8
.type _Z6modcpyPvS_mm,@function
_Z6modcpyPvS_mm: ; @_Z6modcpyPvS_mm
; %bb.0:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b256 s[4:11], s[0:1], 0x0
s_add_u32 s0, s0, 32
s_addc_u32 s1, s1, 0
s_mov_b32 s3, exec_lo
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
v_alignbit_b32 v0, s9, s8, 4
v_cmpx_lt_i32_e64 v1, v0
s_cbranch_execz .LBB0_3
; %bb.1: ; %.lr.ph
v_alignbit_b32 v2, s11, s10, 4
s_load_b32 s1, s[0:1], 0x0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_add_nc_u32_e32 v2, v2, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_xor_b32_e32 v3, v2, v3
v_cvt_f32_u32_e32 v2, v3
v_sub_nc_u32_e32 v4, 0, v3
s_waitcnt lgkmcnt(0)
s_mul_i32 s1, s1, s2
s_mov_b32 s2, 0
v_rcp_iflag_f32_e32 v2, v2
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v2, 0x4f7ffffe, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_u32_f32_e32 v2, v2
v_mul_lo_u32 v4, v4, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v4, v2, v4
v_add_nc_u32_e32 v4, v2, v4
.LBB0_2: ; =>This Inner Loop Header: Depth=1
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_add_nc_u32_e32 v5, v1, v2
v_lshlrev_b64 v[9:10], 4, v[1:2]
v_add_nc_u32_e32 v1, s1, v1
v_xor_b32_e32 v5, v5, v2
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v9, s0, s4, v9
v_add_co_ci_u32_e64 v10, s0, s5, v10, s0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v6, v5, v4
v_mul_lo_u32 v6, v6, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v5, v5, v6
v_sub_nc_u32_e32 v6, v5, v3
v_cmp_ge_u32_e32 vcc_lo, v5, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v5, v5, v6, vcc_lo
v_sub_nc_u32_e32 v6, v5, v3
v_cmp_ge_u32_e32 vcc_lo, v5, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v5, v5, v6, vcc_lo
v_xor_b32_e32 v5, v5, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v5, v5, v2
v_ashrrev_i32_e32 v6, 31, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[5:6], 4, v[5:6]
v_add_co_u32 v5, vcc_lo, s6, v5
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v6, vcc_lo, s7, v6, vcc_lo
v_cmp_ge_i32_e32 vcc_lo, v1, v0
global_load_b128 v[5:8], v[5:6], off
s_or_b32 s2, vcc_lo, s2
s_waitcnt vmcnt(0)
global_store_b128 v[9:10], v[5:8], off
s_and_not1_b32 exec_lo, exec_lo, s2
s_cbranch_execnz .LBB0_2
.LBB0_3: ; %Flow25
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6modcpyPvS_mm
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 11
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6modcpyPvS_mm, .Lfunc_end0-_Z6modcpyPvS_mm
; -- End function
.section .AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 380
; NumSgprs: 18
; NumVgprs: 11
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 11
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object ; @__hip_cuid_
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0 ; 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 8
.value_kind: by_value
- .offset: 24
.size: 8
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6modcpyPvS_mm
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z6modcpyPvS_mm.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 11
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
```
| 910 | 3,528 |
673 |
Convert the following CUDA host assembly code to AMD host assembly:
```cudaasm
.file "tmpxft_000844c3_00000000-6_modcpy.cudafe1.cpp"
.text
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z29__device_stub__Z6modcpyPvS_mmPvS_mm
.type _Z29__device_stub__Z6modcpyPvS_mmPvS_mm, @function
_Z29__device_stub__Z6modcpyPvS_mmPvS_mm:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %rcx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z6modcpyPvS_mm(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z29__device_stub__Z6modcpyPvS_mmPvS_mm, .-_Z29__device_stub__Z6modcpyPvS_mmPvS_mm
.globl _Z6modcpyPvS_mm
.type _Z6modcpyPvS_mm, @function
_Z6modcpyPvS_mm:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z6modcpyPvS_mmPvS_mm
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z6modcpyPvS_mm, .-_Z6modcpyPvS_mm
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z6modcpyPvS_mm"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z6modcpyPvS_mm(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
```
|
```amdasm
.text
.file "modcpy.hip"
.globl _Z21__device_stub__modcpyPvS_mm # -- Begin function _Z21__device_stub__modcpyPvS_mm
.type _Z21__device_stub__modcpyPvS_mm,@function
_Z21__device_stub__modcpyPvS_mm: # @_Z21__device_stub__modcpyPvS_mm
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $112, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 40(%rsp), %rax
movq %rdi, (%rax)
leaq 32(%rsp), %rdi
movq %rsi, (%rdi)
leaq 24(%rsp), %rsi
movq %rdx, (%rsi)
leaq 16(%rsp), %rdx
movq %rcx, (%rdx)
leaq 80(%rsp), %rbx
movq %rax, (%rbx)
movq %rdi, 8(%rbx)
movq %rsi, 16(%rbx)
movq %rdx, 24(%rbx)
leaq 64(%rsp), %r14
leaq 48(%rsp), %r15
leaq 8(%rsp), %r12
movq %rsp, %r13
movq %r14, %rdi
movq %r15, %rsi
movq %r12, %rdx
movq %r13, %rcx
callq __hipPopCallConfiguration
movq (%r14), %rsi
movl 8(%r14), %edx
movq (%r15), %rcx
movl 8(%r15), %r8d
movl $_Z6modcpyPvS_mm, %edi
movq %rbx, %r9
pushq (%r13)
.cfi_adjust_cfa_offset 8
pushq (%r12)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $128, %rsp
.cfi_adjust_cfa_offset -128
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z21__device_stub__modcpyPvS_mm, .Lfunc_end0-_Z21__device_stub__modcpyPvS_mm
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, %rdi
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6modcpyPvS_mm, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6modcpyPvS_mm,@object # @_Z6modcpyPvS_mm
.section .rodata,"a",@progbits
.globl _Z6modcpyPvS_mm
.p2align 3, 0x0
_Z6modcpyPvS_mm:
.quad _Z21__device_stub__modcpyPvS_mm
.size _Z6modcpyPvS_mm, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z6modcpyPvS_mm"
.size .L__unnamed_1, 16
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__modcpyPvS_mm
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6modcpyPvS_mm
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
```
| 1,867 | 2,055 |
676 |
Convert the following CUDA device assembly code to AMD device assembly:
```cudaasm
code for sm_80
Function : _Z17downSanple420_gpuyyPsS_mm
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ;
S2R R0, SR_CTAID.Y ;
S2R R5, SR_TID.Y ;
S2R R2, SR_CTAID.X ;
S2R R3, SR_TID.X ;
IMAD R0, R0, c[0x0][0x4], R5 ;
IMAD.SHL.U32 R0, R0, 0x2, RZ ;
IMAD R2, R2, c[0x0][0x0], R3 ;
ISETP.GE.U32.AND P1, PT, R0, c[0x0][0x188], PT ;
SHF.R.S32.HI R4, RZ, 0x1f, R0 ;
ISETP.GE.U32.AND P0, PT, R2, c[0x0][0x180], PT ;
SHF.R.S32.HI R3, RZ, 0x1f, R2 ;
ISETP.GE.U32.AND.EX P1, PT, R4, c[0x0][0x18c], PT, P1 ;
ISETP.GE.U32.OR.EX P0, PT, R3, c[0x0][0x184], P1, P0 ;
@P0 EXIT ;
ULDC UR4, c[0x0][0x180] ;
IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x184] ;
I2F R5, R0 ;
IMAD.U32 R7, RZ, RZ, UR4 ;
IADD3 R8, R0, 0x1, RZ ;
IMAD.MOV.U32 R12, RZ, RZ, c[0x0][0x160] ;
IMAD.MOV.U32 R13, RZ, RZ, -0x3e000000 ;
SHF.R.U64 R7, R7, 0x1, R4.reuse ;
SHF.R.U32.HI R4, RZ, 0x1, R4 ;
I2F R15, R8 ;
ISETP.GT.U32.AND P0, PT, R7, R2, PT ;
ISETP.GT.U32.AND.EX P0, PT, R4, R3, PT, P0 ;
SEL R3, R7, RZ, !P0 ;
IMAD.MOV.U32 R7, RZ, RZ, R5 ;
SEL R12, R12, c[0x0][0x168], P0 ;
IMAD.IADD R3, R2, 0x1, -R3 ;
IMAD.MOV.U32 R17, RZ, RZ, R15 ;
IMAD.SHL.U32 R3, R3, 0x2, RZ ;
I2F R4, R3 ;
IADD3 R2, R3, 0x1, RZ ;
I2F R6, R2 ;
IMAD.MOV.U32 R14, RZ, RZ, R4 ;
TEX.SCR.B.LL RZ, R4, R4, R12, 2D, 0x1 ;
IMAD.MOV.U32 R16, RZ, RZ, R6 ;
TEX.SCR.B.LL RZ, R7, R6, R12, 2D, 0x1 ;
TEX.SCR.B.LL RZ, R8, R14, R12, 2D, 0x1 ;
TEX.SCR.B.LL RZ, R9, R16, R12, 2D, 0x1 ;
SHF.R.S32.HI R11, RZ, 0x1, R0 ;
ULDC.64 UR4, c[0x0][0x118] ;
SHF.R.S32.HI R2, RZ, 0x1, R3 ;
SHF.R.S32.HI R0, RZ, 0x1f, R11 ;
SHF.R.S32.HI R3, RZ, 0x1f, R2 ;
IMAD R0, R0, c[0x0][0x180], RZ ;
IMAD.WIDE.U32 R2, R11, c[0x0][0x180], R2 ;
IMAD R11, R11, c[0x0][0x184], R0 ;
IMAD.MOV.U32 R6, RZ, RZ, c[0x0][0x174] ;
IMAD.IADD R3, R3, 0x1, R11 ;
SEL R6, R6, c[0x0][0x17c], P0 ;
DEPBAR.LE SB5, 0x1 ;
PRMT R10, R4, 0x9910, RZ ;
IMAD.MOV.U32 R0, RZ, RZ, R10 ;
PRMT R5, R7, 0x9910, RZ ;
IMAD.MOV.U32 R7, RZ, RZ, c[0x0][0x170] ;
PRMT R4, R8, 0x9910, RZ ;
PRMT R9, R9, 0x9910, RZ ;
IADD3 R5, R4, R0, R5 ;
SEL R7, R7, c[0x0][0x178], P0 ;
IMAD.MOV.U32 R0, RZ, RZ, R9 ;
LEA R4, P0, R2.reuse, R7, 0x1 ;
IADD3 R0, R5, 0x1, R0 ;
LEA.HI.X R5, R2, R6, R3, 0x1, P0 ;
SHF.R.U32.HI R3, RZ, 0x2, R0 ;
STG.E.U16 [R4.64], R3 ;
EXIT ;
BRA 0x450;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
```
|
```amdasm
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z17downSanple420_gpuP13__hip_textureS0_PsS1_mm ; -- Begin function _Z17downSanple420_gpuP13__hip_textureS0_PsS1_mm
.globl _Z17downSanple420_gpuP13__hip_textureS0_PsS1_mm
.p2align 8
.type _Z17downSanple420_gpuP13__hip_textureS0_PsS1_mm,@function
_Z17downSanple420_gpuP13__hip_textureS0_PsS1_mm: ; @_Z17downSanple420_gpuP13__hip_textureS0_PsS1_mm
; %bb.0:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x3c
s_load_b128 s[16:19], s[0:1], 0x20
v_and_b32_e32 v1, 0x3ff, v0
s_add_u32 s2, s0, 48
s_addc_u32 s3, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[14:15], null, s14, s4, v[1:2]
s_mov_b32 s4, exec_lo
v_ashrrev_i32_e32 v15, 31, v14
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_u64_e64 s[16:17], v[14:15]
s_cbranch_execz .LBB0_19
; %bb.1:
s_load_b32 s2, s[2:3], 0xc
s_load_b256 s[4:11], s[0:1], 0x0
v_bfe_u32 v0, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_lshr_b32 s0, s2, 16
s_delay_alu instid0(SALU_CYCLE_1)
s_mul_i32 s15, s15, s0
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_add_lshl_u32 v12, s15, v0, 1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v13, 31, v12
v_cmp_gt_u64_e32 vcc_lo, s[18:19], v[12:13]
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_19
; %bb.2:
s_lshr_b64 s[0:1], s[16:17], 1
v_dual_mov_b32 v0, s9 :: v_dual_mov_b32 v1, s5
v_cmp_gt_u64_e64 s0, s[0:1], v[14:15]
v_mov_b32_e32 v2, s4
v_alignbit_b32 v15, s17, s16, 1
s_mov_b32 s18, exec_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cndmask_b32_e64 v9, s7, v1, s0
v_cndmask_b32_e64 v8, s6, v2, s0
v_cndmask_b32_e64 v17, s11, v0, s0
v_cndmask_b32_e64 v15, v15, 0, s0
s_clause 0x3
global_load_b128 v[0:3], v[8:9], off
global_load_b128 v[4:7], v[8:9], off offset:48
global_load_b32 v13, v[8:9], off offset:40
global_load_b128 v[8:11], v[8:9], off offset:16
v_sub_nc_u32_e32 v18, v14, v15
s_waitcnt vmcnt(3)
v_bfe_u32 v16, v2, 14, 14
s_waitcnt vmcnt(2)
v_and_b32_e32 v19, 0x8000, v4
s_waitcnt vmcnt(1)
v_cvt_f32_u32_e32 v13, v13
v_and_b32_e32 v24, 0x100000, v6
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_cmp_eq_u32_e32 vcc_lo, 0, v19
v_add_nc_u32_e32 v16, 1, v16
v_lshlrev_b32_e32 v15, 1, v18
v_cvt_f32_u32_e32 v14, v16
v_cndmask_b32_e32 v16, 1.0, v13, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cvt_f32_i32_e32 v13, v15
v_cndmask_b32_e32 v21, 1.0, v14, vcc_lo
v_cvt_f32_i32_e32 v14, v12
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_rcp_f32_e32 v20, v16
v_mul_f32_e32 v23, v16, v13
v_cmp_eq_u32_e32 vcc_lo, 0, v24
v_rcp_f32_e32 v22, v21
v_mul_f32_e32 v19, v21, v14
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_floor_f32_e32 v23, v23
v_floor_f32_e32 v19, v19
s_waitcnt_depctr 0xfff
v_dual_mov_b32 v25, s8 :: v_dual_mul_f32 v26, v22, v19
v_mul_f32_e32 v23, v20, v23
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cndmask_b32_e64 v19, s10, v25, s0
v_dual_cndmask_b32 v14, v14, v26 :: v_dual_cndmask_b32 v13, v13, v23
s_waitcnt vmcnt(0)
.LBB0_3: ; =>This Loop Header: Depth=1
; Child Loop BB0_4 Depth 2
v_readfirstlane_b32 s4, v0
v_readfirstlane_b32 s5, v1
v_readfirstlane_b32 s6, v2
v_readfirstlane_b32 s7, v3
v_readfirstlane_b32 s8, v8
v_readfirstlane_b32 s9, v9
v_readfirstlane_b32 s10, v10
v_readfirstlane_b32 s11, v11
v_cmp_eq_u64_e64 s0, s[4:5], v[0:1]
v_cmp_eq_u64_e64 s1, s[6:7], v[2:3]
v_cmp_eq_u64_e64 s2, s[8:9], v[8:9]
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cmp_eq_u64_e64 s3, s[10:11], v[10:11]
s_and_b32 s0, s0, s1
s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
s_and_b32 s0, s0, s2
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
s_and_b32 s0, s0, s3
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s2, s0
s_mov_b32 s3, exec_lo
.LBB0_4: ; Parent Loop BB0_3 Depth=1
; => This Inner Loop Header: Depth=2
v_readfirstlane_b32 s12, v4
v_readfirstlane_b32 s13, v5
v_readfirstlane_b32 s14, v6
v_readfirstlane_b32 s15, v7
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_eq_u64_e64 s0, s[12:13], v[4:5]
v_cmp_eq_u64_e64 s1, s[14:15], v[6:7]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s0, s0, s1
s_and_saveexec_b32 s0, s0
image_sample_lz v23, v[13:14], s[4:11], s[12:15] dmask:0x1 dim:SQ_RSRC_IMG_2D
s_xor_b32 exec_lo, exec_lo, s0
s_cbranch_execnz .LBB0_4
; %bb.5: ; in Loop: Header=BB0_3 Depth=1
s_mov_b32 exec_lo, s3
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 exec_lo, exec_lo, s2
s_cbranch_execnz .LBB0_3
; %bb.6:
s_mov_b32 exec_lo, s18
v_or_b32_e32 v15, 1, v15
s_mov_b32 s18, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_f32_i32_e32 v15, v15
v_mul_f32_e32 v16, v16, v15
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_floor_f32_e32 v16, v16
v_mul_f32_e32 v16, v20, v16
s_waitcnt vmcnt(0)
v_bfe_i32 v20, v23, 0, 16
s_delay_alu instid0(VALU_DEP_2)
v_dual_cndmask_b32 v15, v15, v16 :: v_dual_mov_b32 v16, v14
.LBB0_7: ; =>This Loop Header: Depth=1
; Child Loop BB0_8 Depth 2
v_readfirstlane_b32 s4, v0
v_readfirstlane_b32 s5, v1
v_readfirstlane_b32 s6, v2
v_readfirstlane_b32 s7, v3
v_readfirstlane_b32 s8, v8
v_readfirstlane_b32 s9, v9
v_readfirstlane_b32 s10, v10
v_readfirstlane_b32 s11, v11
v_cmp_eq_u64_e64 s0, s[4:5], v[0:1]
v_cmp_eq_u64_e64 s1, s[6:7], v[2:3]
v_cmp_eq_u64_e64 s2, s[8:9], v[8:9]
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cmp_eq_u64_e64 s3, s[10:11], v[10:11]
s_and_b32 s0, s0, s1
s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
s_and_b32 s0, s0, s2
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
s_and_b32 s0, s0, s3
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s2, s0
s_mov_b32 s3, exec_lo
.LBB0_8: ; Parent Loop BB0_7 Depth=1
; => This Inner Loop Header: Depth=2
v_readfirstlane_b32 s12, v4
v_readfirstlane_b32 s13, v5
v_readfirstlane_b32 s14, v6
v_readfirstlane_b32 s15, v7
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_eq_u64_e64 s0, s[12:13], v[4:5]
v_cmp_eq_u64_e64 s1, s[14:15], v[6:7]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s0, s0, s1
s_and_saveexec_b32 s0, s0
image_sample_lz v14, v[15:16], s[4:11], s[12:15] dmask:0x1 dim:SQ_RSRC_IMG_2D
s_xor_b32 exec_lo, exec_lo, s0
s_cbranch_execnz .LBB0_8
; %bb.9: ; in Loop: Header=BB0_7 Depth=1
s_mov_b32 exec_lo, s3
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 exec_lo, exec_lo, s2
s_cbranch_execnz .LBB0_7
; %bb.10:
s_mov_b32 exec_lo, s18
v_or_b32_e32 v16, 1, v12
s_mov_b32 s3, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_f32_i32_e32 v16, v16
v_mul_f32_e32 v21, v21, v16
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_floor_f32_e32 v21, v21
v_mul_f32_e32 v22, v22, v21
s_waitcnt vmcnt(0)
v_bfe_i32 v21, v14, 0, 16
s_delay_alu instid0(VALU_DEP_2)
v_cndmask_b32_e32 v14, v16, v22, vcc_lo
.LBB0_11: ; =>This Loop Header: Depth=1
; Child Loop BB0_12 Depth 2
v_readfirstlane_b32 s4, v0
v_readfirstlane_b32 s5, v1
v_readfirstlane_b32 s6, v2
v_readfirstlane_b32 s7, v3
v_readfirstlane_b32 s8, v8
v_readfirstlane_b32 s9, v9
v_readfirstlane_b32 s10, v10
v_readfirstlane_b32 s11, v11
v_cmp_eq_u64_e32 vcc_lo, s[4:5], v[0:1]
v_cmp_eq_u64_e64 s0, s[6:7], v[2:3]
v_cmp_eq_u64_e64 s1, s[8:9], v[8:9]
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cmp_eq_u64_e64 s2, s[10:11], v[10:11]
s_and_b32 s0, vcc_lo, s0
s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
s_and_b32 s0, s0, s1
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
s_and_b32 s0, s0, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s1, s0
s_mov_b32 s2, exec_lo
.LBB0_12: ; Parent Loop BB0_11 Depth=1
; => This Inner Loop Header: Depth=2
v_readfirstlane_b32 s12, v4
v_readfirstlane_b32 s13, v5
v_readfirstlane_b32 s14, v6
v_readfirstlane_b32 s15, v7
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_eq_u64_e32 vcc_lo, s[12:13], v[4:5]
v_cmp_eq_u64_e64 s0, s[14:15], v[6:7]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s0, vcc_lo, s0
s_and_saveexec_b32 s0, s0
image_sample_lz v16, v[13:14], s[4:11], s[12:15] dmask:0x1 dim:SQ_RSRC_IMG_2D
s_xor_b32 exec_lo, exec_lo, s0
s_cbranch_execnz .LBB0_12
; %bb.13: ; in Loop: Header=BB0_11 Depth=1
s_mov_b32 exec_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 exec_lo, exec_lo, s1
s_cbranch_execnz .LBB0_11
; %bb.14:
s_mov_b32 exec_lo, s3
s_waitcnt vmcnt(0)
v_bfe_i32 v13, v16, 0, 16
v_mov_b32_e32 v16, v14
s_mov_b32 s3, exec_lo
.LBB0_15: ; =>This Loop Header: Depth=1
; Child Loop BB0_16 Depth 2
v_readfirstlane_b32 s4, v0
v_readfirstlane_b32 s5, v1
v_readfirstlane_b32 s6, v2
v_readfirstlane_b32 s7, v3
v_readfirstlane_b32 s8, v8
v_readfirstlane_b32 s9, v9
v_readfirstlane_b32 s10, v10
v_readfirstlane_b32 s11, v11
v_cmp_eq_u64_e32 vcc_lo, s[4:5], v[0:1]
v_cmp_eq_u64_e64 s0, s[6:7], v[2:3]
v_cmp_eq_u64_e64 s1, s[8:9], v[8:9]
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cmp_eq_u64_e64 s2, s[10:11], v[10:11]
s_and_b32 s0, vcc_lo, s0
s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
s_and_b32 s0, s0, s1
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
s_and_b32 s0, s0, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s1, s0
s_mov_b32 s2, exec_lo
.LBB0_16: ; Parent Loop BB0_15 Depth=1
; => This Inner Loop Header: Depth=2
v_readfirstlane_b32 s12, v4
v_readfirstlane_b32 s13, v5
v_readfirstlane_b32 s14, v6
v_readfirstlane_b32 s15, v7
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_eq_u64_e32 vcc_lo, s[12:13], v[4:5]
v_cmp_eq_u64_e64 s0, s[14:15], v[6:7]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s0, vcc_lo, s0
s_and_saveexec_b32 s0, s0
image_sample_lz v14, v[15:16], s[4:11], s[12:15] dmask:0x1 dim:SQ_RSRC_IMG_2D
s_xor_b32 exec_lo, exec_lo, s0
s_cbranch_execnz .LBB0_16
; %bb.17: ; in Loop: Header=BB0_15 Depth=1
s_mov_b32 exec_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 exec_lo, exec_lo, s1
s_cbranch_execnz .LBB0_15
; %bb.18:
s_mov_b32 exec_lo, s3
v_ashrrev_i32_e32 v2, 1, v12
v_add3_u32 v5, v20, v21, v13
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_4)
v_ashrrev_i32_e32 v3, 31, v2
v_mul_lo_u32 v4, v2, s17
v_mad_u64_u32 v[0:1], null, v2, s16, 0
v_bfe_i32 v2, v18, 0, 31
v_mul_lo_u32 v3, v3, s16
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add3_u32 v1, v1, v4, v3
v_ashrrev_i32_e32 v3, 31, v2
s_waitcnt vmcnt(0)
v_bfe_i32 v4, v14, 0, 16
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[0:1], 1, v[0:1]
v_lshlrev_b64 v[2:3], 1, v[2:3]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add3_u32 v4, v5, v4, 1
v_add_co_u32 v0, vcc_lo, v19, v0
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e32 v1, vcc_lo, v17, v1, vcc_lo
v_lshrrev_b32_e32 v4, 2, v4
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v0, vcc_lo, v0, v2
v_add_co_ci_u32_e32 v1, vcc_lo, v1, v3, vcc_lo
global_store_b16 v[0:1], v4, off
.LBB0_19:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z17downSanple420_gpuP13__hip_textureS0_PsS1_mm
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 304
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 27
.amdhsa_next_free_sgpr 20
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z17downSanple420_gpuP13__hip_textureS0_PsS1_mm, .Lfunc_end0-_Z17downSanple420_gpuP13__hip_textureS0_PsS1_mm
; -- End function
.section .AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1440
; NumSgprs: 22
; NumVgprs: 27
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 3
; NumSGPRsForWavesPerEU: 22
; NumVGPRsForWavesPerEU: 27
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object ; @__hip_cuid_
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0 ; 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 8
.value_kind: by_value
- .offset: 40
.size: 8
.value_kind: by_value
- .offset: 48
.size: 4
.value_kind: hidden_block_count_x
- .offset: 52
.size: 4
.value_kind: hidden_block_count_y
- .offset: 56
.size: 4
.value_kind: hidden_block_count_z
- .offset: 60
.size: 2
.value_kind: hidden_group_size_x
- .offset: 62
.size: 2
.value_kind: hidden_group_size_y
- .offset: 64
.size: 2
.value_kind: hidden_group_size_z
- .offset: 66
.size: 2
.value_kind: hidden_remainder_x
- .offset: 68
.size: 2
.value_kind: hidden_remainder_y
- .offset: 70
.size: 2
.value_kind: hidden_remainder_z
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 112
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 304
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z17downSanple420_gpuP13__hip_textureS0_PsS1_mm
.private_segment_fixed_size: 0
.sgpr_count: 22
.sgpr_spill_count: 0
.symbol: _Z17downSanple420_gpuP13__hip_textureS0_PsS1_mm.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 27
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
```
| 1,541 | 8,283 |
677 |
Convert the following CUDA host assembly code to AMD host assembly:
```cudaasm
.file "tmpxft_00061730_00000000-6_downSanple420_gpu.cudafe1.cpp"
.text
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z43__device_stub__Z17downSanple420_gpuyyPsS_mmyyPsS_mm
.type _Z43__device_stub__Z17downSanple420_gpuyyPsS_mmyyPsS_mm, @function
_Z43__device_stub__Z17downSanple420_gpuyyPsS_mmyyPsS_mm:
.LFB2051:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movq %r8, 8(%rsp)
movq %r9, (%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
movq %rsp, %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z17downSanple420_gpuyyPsS_mm(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z43__device_stub__Z17downSanple420_gpuyyPsS_mmyyPsS_mm, .-_Z43__device_stub__Z17downSanple420_gpuyyPsS_mmyyPsS_mm
.globl _Z17downSanple420_gpuyyPsS_mm
.type _Z17downSanple420_gpuyyPsS_mm, @function
_Z17downSanple420_gpuyyPsS_mm:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z43__device_stub__Z17downSanple420_gpuyyPsS_mmyyPsS_mm
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z17downSanple420_gpuyyPsS_mm, .-_Z17downSanple420_gpuyyPsS_mm
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z17downSanple420_gpuyyPsS_mm"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z17downSanple420_gpuyyPsS_mm(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
```
|
```amdasm
.text
.file "downSanple420_gpu.hip"
.globl _Z32__device_stub__downSanple420_gpuP13__hip_textureS0_PsS1_mm # -- Begin function _Z32__device_stub__downSanple420_gpuP13__hip_textureS0_PsS1_mm
.type _Z32__device_stub__downSanple420_gpuP13__hip_textureS0_PsS1_mm,@function
_Z32__device_stub__downSanple420_gpuP13__hip_textureS0_PsS1_mm: # @_Z32__device_stub__downSanple420_gpuP13__hip_textureS0_PsS1_mm
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $144, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 56(%rsp), %rax
movq %rdi, (%rax)
leaq 48(%rsp), %rdi
movq %rsi, (%rdi)
leaq 40(%rsp), %rsi
movq %rdx, (%rsi)
leaq 32(%rsp), %rdx
movq %rcx, (%rdx)
leaq 24(%rsp), %rcx
movq %r8, (%rcx)
leaq 16(%rsp), %r8
movq %r9, (%r8)
leaq 96(%rsp), %rbx
movq %rax, (%rbx)
movq %rdi, 8(%rbx)
movq %rsi, 16(%rbx)
movq %rdx, 24(%rbx)
movq %rcx, 32(%rbx)
movq %r8, 40(%rbx)
leaq 80(%rsp), %r14
leaq 64(%rsp), %r15
leaq 8(%rsp), %r12
movq %rsp, %r13
movq %r14, %rdi
movq %r15, %rsi
movq %r12, %rdx
movq %r13, %rcx
callq __hipPopCallConfiguration
movq (%r14), %rsi
movl 8(%r14), %edx
movq (%r15), %rcx
movl 8(%r15), %r8d
movl $_Z17downSanple420_gpuP13__hip_textureS0_PsS1_mm, %edi
movq %rbx, %r9
pushq (%r13)
.cfi_adjust_cfa_offset 8
pushq (%r12)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $160, %rsp
.cfi_adjust_cfa_offset -160
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z32__device_stub__downSanple420_gpuP13__hip_textureS0_PsS1_mm, .Lfunc_end0-_Z32__device_stub__downSanple420_gpuP13__hip_textureS0_PsS1_mm
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, %rdi
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z17downSanple420_gpuP13__hip_textureS0_PsS1_mm, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z17downSanple420_gpuP13__hip_textureS0_PsS1_mm,@object # @_Z17downSanple420_gpuP13__hip_textureS0_PsS1_mm
.section .rodata,"a",@progbits
.globl _Z17downSanple420_gpuP13__hip_textureS0_PsS1_mm
.p2align 3, 0x0
_Z17downSanple420_gpuP13__hip_textureS0_PsS1_mm:
.quad _Z32__device_stub__downSanple420_gpuP13__hip_textureS0_PsS1_mm
.size _Z17downSanple420_gpuP13__hip_textureS0_PsS1_mm, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z17downSanple420_gpuP13__hip_textureS0_PsS1_mm"
.size .L__unnamed_1, 48
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z32__device_stub__downSanple420_gpuP13__hip_textureS0_PsS1_mm
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z17downSanple420_gpuP13__hip_textureS0_PsS1_mm
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
```
| 2,054 | 2,395 |
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