uid
int64 2
114k
| input
stringlengths 101
58.4k
| output
stringlengths 422
72.4k
| input_tokens
int64 24
31.2k
| output_tokens
int64 182
31.2k
|
|---|---|---|---|---|
312 |
Convert the following CUDA device assembly code to AMD device assembly:
```cudaasm
code for sm_80
Function : _Z45transpose_parallel_per_element_tiled_padded16PfS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
MOV R1, c[0x0][0x28] ;
S2R R5, SR_CTAID.X ;
IMAD.MOV.U32 R8, RZ, RZ, 0x4 ;
ULDC.64 UR4, c[0x0][0x118] ;
S2R R4, SR_CTAID.Y ;
S2R R6, SR_TID.X ;
S2R R9, SR_TID.Y ;
LEA R0, R5, R6, 0x4 ;
LEA R3, R4, R9, 0x4 ;
LEA R3, R3, R0, 0xa ;
IMAD.WIDE R2, R3, R8, c[0x0][0x160] ;
LDG.E R2, [R2.64] ;
IMAD R11, R9, 0x11, R6.reuse ;
LEA R5, R5, R9, 0x4 ;
IMAD R7, R6, 0x11, R9 ;
IMAD R0, R4, 0x10, R6 ;
LEA R5, R5, R0, 0xa ;
IMAD.WIDE R4, R5, R8, c[0x0][0x168] ;
STS [R11.X4], R2 ;
BAR.SYNC.DEFER_BLOCKING 0x0 ;
LDS R7, [R7.X4] ;
STG.E [R4.64], R7 ;
EXIT ;
BRA 0x170;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
Function : _Z38transpose_parallel_per_element_tiled16PfS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
MOV R1, c[0x0][0x28] ;
S2R R5, SR_CTAID.X ;
IMAD.MOV.U32 R8, RZ, RZ, 0x4 ;
ULDC.64 UR4, c[0x0][0x118] ;
S2R R6, SR_TID.X ;
S2R R4, SR_CTAID.Y ;
S2R R9, SR_TID.Y ;
IMAD R0, R5, 0x10, R6 ;
LEA R3, R4, R9, 0x4 ;
LEA R3, R3, R0, 0xa ;
IMAD.WIDE R2, R3, R8, c[0x0][0x160] ;
LDG.E R2, [R2.64] ;
IMAD R11, R9, 0x10, R6.reuse ;
LEA R7, R6, R9.reuse, 0x4 ;
IMAD R0, R4, 0x10, R6 ;
LEA R5, R5, R9, 0x4 ;
LEA R5, R5, R0, 0xa ;
IMAD.WIDE R4, R5, R8, c[0x0][0x168] ;
STS [R11.X4], R2 ;
BAR.SYNC.DEFER_BLOCKING 0x0 ;
LDS R7, [R7.X4] ;
STG.E [R4.64], R7 ;
EXIT ;
BRA 0x170;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
Function : _Z36transpose_parallel_per_element_tiledPfS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
MOV R1, c[0x0][0x28] ;
S2R R5, SR_CTAID.X ;
IMAD.MOV.U32 R8, RZ, RZ, 0x4 ;
ULDC.64 UR4, c[0x0][0x118] ;
S2R R6, SR_TID.X ;
S2R R4, SR_CTAID.Y ;
S2R R9, SR_TID.Y ;
IMAD R0, R5, 0x20, R6 ;
LEA R3, R4, R9, 0x5 ;
LEA R3, R3, R0, 0xa ;
IMAD.WIDE R2, R3, R8, c[0x0][0x160] ;
LDG.E R2, [R2.64] ;
IMAD R11, R9, 0x20, R6.reuse ;
LEA R7, R6, R9.reuse, 0x5 ;
IMAD R0, R4, 0x20, R6 ;
LEA R5, R5, R9, 0x5 ;
LEA R5, R5, R0, 0xa ;
IMAD.WIDE R4, R5, R8, c[0x0][0x168] ;
STS [R11.X4], R2 ;
BAR.SYNC.DEFER_BLOCKING 0x0 ;
LDS R7, [R7.X4] ;
STG.E [R4.64], R7 ;
EXIT ;
BRA 0x170;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
Function : _Z30transpose_parallel_per_elementPfS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
MOV R1, c[0x0][0x28] ;
S2R R0, SR_CTAID.X ;
IMAD.MOV.U32 R4, RZ, RZ, 0x4 ;
ULDC.64 UR4, c[0x0][0x118] ;
S2R R3, SR_TID.X ;
S2R R5, SR_CTAID.Y ;
S2R R2, SR_TID.Y ;
LEA R0, R0, R3, 0x5 ;
LEA R5, R5, R2, 0x5 ;
LEA R2, R5, R0, 0xa ;
IMAD.WIDE R2, R2, R4, c[0x0][0x160] ;
LDG.E R3, [R2.64] ;
IMAD R5, R0, 0x400, R5 ;
IMAD.WIDE R4, R5, R4, c[0x0][0x168] ;
STG.E [R4.64], R3 ;
EXIT ;
BRA 0x100;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
Function : _Z26transpose_parallel_per_rowPfS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
MOV R1, c[0x0][0x28] ;
S2R R0, SR_TID.X ;
HFMA2.MMA R7, -RZ, RZ, 0, 0 ;
ULDC.64 UR4, c[0x0][0x118] ;
ULDC.64 UR8, c[0x0][0x168] ;
ULDC.64 UR6, c[0x0][0x160] ;
IMAD.SHL.U32 R6, R0, 0x400, RZ ;
MOV R2, UR6 ;
IMAD.U32 R3, RZ, RZ, UR7 ;
IMAD.WIDE R2, R0, 0x4, R2 ;
LDG.E R9, [R2.64] ;
MOV R4, UR8 ;
IMAD.U32 R5, RZ, RZ, UR9 ;
IMAD.WIDE R4, R6, 0x4, R4 ;
STG.E [R4.64], R9 ;
LDG.E R11, [R2.64+0x1000] ;
STG.E [R4.64+0x4], R11 ;
LDG.E R13, [R2.64+0x2000] ;
STG.E [R4.64+0x8], R13 ;
LDG.E R15, [R2.64+0x3000] ;
STG.E [R4.64+0xc], R15 ;
LDG.E R17, [R2.64+0x4000] ;
STG.E [R4.64+0x10], R17 ;
LDG.E R19, [R2.64+0x5000] ;
STG.E [R4.64+0x14], R19 ;
LDG.E R9, [R2.64+0x6000] ;
STG.E [R4.64+0x18], R9 ;
LDG.E R11, [R2.64+0x7000] ;
STG.E [R4.64+0x1c], R11 ;
LDG.E R13, [R2.64+0x8000] ;
STG.E [R4.64+0x20], R13 ;
LDG.E R15, [R2.64+0x9000] ;
STG.E [R4.64+0x24], R15 ;
LDG.E R17, [R2.64+0xa000] ;
STG.E [R4.64+0x28], R17 ;
LDG.E R19, [R2.64+0xb000] ;
STG.E [R4.64+0x2c], R19 ;
LDG.E R9, [R2.64+0xc000] ;
STG.E [R4.64+0x30], R9 ;
LDG.E R11, [R2.64+0xd000] ;
STG.E [R4.64+0x34], R11 ;
LDG.E R13, [R2.64+0xe000] ;
STG.E [R4.64+0x38], R13 ;
LDG.E R15, [R2.64+0xf000] ;
STG.E [R4.64+0x3c], R15 ;
LDG.E R17, [R2.64+0x10000] ;
STG.E [R4.64+0x40], R17 ;
LDG.E R19, [R2.64+0x11000] ;
STG.E [R4.64+0x44], R19 ;
LDG.E R9, [R2.64+0x12000] ;
STG.E [R4.64+0x48], R9 ;
LDG.E R11, [R2.64+0x13000] ;
STG.E [R4.64+0x4c], R11 ;
LDG.E R13, [R2.64+0x14000] ;
STG.E [R4.64+0x50], R13 ;
LDG.E R15, [R2.64+0x15000] ;
STG.E [R4.64+0x54], R15 ;
LDG.E R17, [R2.64+0x16000] ;
STG.E [R4.64+0x58], R17 ;
LDG.E R19, [R2.64+0x17000] ;
STG.E [R4.64+0x5c], R19 ;
LDG.E R9, [R2.64+0x18000] ;
STG.E [R4.64+0x60], R9 ;
LDG.E R11, [R2.64+0x19000] ;
STG.E [R4.64+0x64], R11 ;
LDG.E R13, [R2.64+0x1a000] ;
STG.E [R4.64+0x68], R13 ;
LDG.E R15, [R2.64+0x1b000] ;
STG.E [R4.64+0x6c], R15 ;
LDG.E R17, [R2.64+0x1c000] ;
STG.E [R4.64+0x70], R17 ;
LDG.E R19, [R2.64+0x1d000] ;
STG.E [R4.64+0x74], R19 ;
LDG.E R9, [R2.64+0x1e000] ;
STG.E [R4.64+0x78], R9 ;
LDG.E R11, [R2.64+0x1f000] ;
STG.E [R4.64+0x7c], R11 ;
LDG.E R13, [R2.64+0x20000] ;
STG.E [R4.64+0x80], R13 ;
LDG.E R15, [R2.64+0x21000] ;
STG.E [R4.64+0x84], R15 ;
LDG.E R17, [R2.64+0x22000] ;
STG.E [R4.64+0x88], R17 ;
LDG.E R19, [R2.64+0x23000] ;
STG.E [R4.64+0x8c], R19 ;
LDG.E R9, [R2.64+0x24000] ;
STG.E [R4.64+0x90], R9 ;
LDG.E R11, [R2.64+0x25000] ;
STG.E [R4.64+0x94], R11 ;
LDG.E R13, [R2.64+0x26000] ;
STG.E [R4.64+0x98], R13 ;
LDG.E R15, [R2.64+0x27000] ;
STG.E [R4.64+0x9c], R15 ;
LDG.E R17, [R2.64+0x28000] ;
STG.E [R4.64+0xa0], R17 ;
LDG.E R19, [R2.64+0x29000] ;
STG.E [R4.64+0xa4], R19 ;
LDG.E R9, [R2.64+0x2a000] ;
STG.E [R4.64+0xa8], R9 ;
LDG.E R11, [R2.64+0x2b000] ;
STG.E [R4.64+0xac], R11 ;
LDG.E R13, [R2.64+0x2c000] ;
STG.E [R4.64+0xb0], R13 ;
LDG.E R15, [R2.64+0x2d000] ;
STG.E [R4.64+0xb4], R15 ;
LDG.E R17, [R2.64+0x2e000] ;
STG.E [R4.64+0xb8], R17 ;
LDG.E R19, [R2.64+0x2f000] ;
STG.E [R4.64+0xbc], R19 ;
LDG.E R9, [R2.64+0x30000] ;
STG.E [R4.64+0xc0], R9 ;
LDG.E R11, [R2.64+0x31000] ;
STG.E [R4.64+0xc4], R11 ;
LDG.E R13, [R2.64+0x32000] ;
STG.E [R4.64+0xc8], R13 ;
LDG.E R15, [R2.64+0x33000] ;
STG.E [R4.64+0xcc], R15 ;
LDG.E R17, [R2.64+0x34000] ;
STG.E [R4.64+0xd0], R17 ;
LDG.E R19, [R2.64+0x35000] ;
STG.E [R4.64+0xd4], R19 ;
LDG.E R9, [R2.64+0x36000] ;
STG.E [R4.64+0xd8], R9 ;
LDG.E R11, [R2.64+0x37000] ;
STG.E [R4.64+0xdc], R11 ;
LDG.E R13, [R2.64+0x38000] ;
STG.E [R4.64+0xe0], R13 ;
LDG.E R15, [R2.64+0x39000] ;
STG.E [R4.64+0xe4], R15 ;
LDG.E R17, [R2.64+0x3a000] ;
STG.E [R4.64+0xe8], R17 ;
LDG.E R19, [R2.64+0x3b000] ;
STG.E [R4.64+0xec], R19 ;
LDG.E R9, [R2.64+0x3c000] ;
STG.E [R4.64+0xf0], R9 ;
LDG.E R11, [R2.64+0x3d000] ;
STG.E [R4.64+0xf4], R11 ;
LDG.E R13, [R2.64+0x3e000] ;
IADD3 R7, R7, 0x40, RZ ;
ISETP.NE.AND P0, PT, R7, 0x400, PT ;
STG.E [R4.64+0xf8], R13 ;
LDG.E R15, [R2.64+0x3f000] ;
UIADD3 UR6, UP1, UR6, 0x40000, URZ ;
UIADD3 UR8, UP0, UR8, 0x100, URZ ;
UIADD3.X UR7, URZ, UR7, URZ, UP1, !UPT ;
UIADD3.X UR9, URZ, UR9, URZ, UP0, !UPT ;
STG.E [R4.64+0xfc], R15 ;
@P0 BRA 0x70 ;
EXIT ;
BRA 0x950;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
Function : _Z16transpose_serialPfS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ;
IMAD.MOV.U32 R0, RZ, RZ, RZ ;
ULDC.64 UR4, c[0x0][0x118] ;
MOV R6, R0 ;
IMAD.SHL.U32 R7, R0.reuse, 0x400, RZ ;
IADD3 R0, R0, 0x1, RZ ;
HFMA2.MMA R12, -RZ, RZ, 0, 0 ;
MOV R10, c[0x0][0x160] ;
IMAD.MOV.U32 R11, RZ, RZ, c[0x0][0x164] ;
ISETP.GE.U32.AND P3, PT, R0, 0x400, PT ;
IMAD.MOV.U32 R9, RZ, RZ, c[0x0][0x16c] ;
MOV R8, c[0x0][0x168] ;
IMAD.WIDE R2, R7, 0x4, R10 ;
LDG.E R13, [R2.64] ;
IMAD.WIDE R4, R6, 0x4, R8 ;
STG.E [R4.64], R13 ;
LDG.E R15, [R2.64+0x4] ;
STG.E [R4.64+0x1000], R15 ;
LDG.E R17, [R2.64+0x8] ;
STG.E [R4.64+0x2000], R17 ;
LDG.E R19, [R2.64+0xc] ;
STG.E [R4.64+0x3000], R19 ;
LDG.E R21, [R2.64+0x10] ;
STG.E [R4.64+0x4000], R21 ;
LDG.E R23, [R2.64+0x14] ;
STG.E [R4.64+0x5000], R23 ;
LDG.E R13, [R2.64+0x18] ;
STG.E [R4.64+0x6000], R13 ;
LDG.E R15, [R2.64+0x1c] ;
STG.E [R4.64+0x7000], R15 ;
LDG.E R17, [R2.64+0x20] ;
STG.E [R4.64+0x8000], R17 ;
LDG.E R19, [R2.64+0x24] ;
STG.E [R4.64+0x9000], R19 ;
LDG.E R21, [R2.64+0x28] ;
STG.E [R4.64+0xa000], R21 ;
LDG.E R23, [R2.64+0x2c] ;
STG.E [R4.64+0xb000], R23 ;
LDG.E R13, [R2.64+0x30] ;
STG.E [R4.64+0xc000], R13 ;
LDG.E R15, [R2.64+0x34] ;
STG.E [R4.64+0xd000], R15 ;
LDG.E R17, [R2.64+0x38] ;
STG.E [R4.64+0xe000], R17 ;
LDG.E R19, [R2.64+0x3c] ;
STG.E [R4.64+0xf000], R19 ;
LDG.E R21, [R2.64+0x40] ;
STG.E [R4.64+0x10000], R21 ;
LDG.E R23, [R2.64+0x44] ;
STG.E [R4.64+0x11000], R23 ;
LDG.E R13, [R2.64+0x48] ;
STG.E [R4.64+0x12000], R13 ;
LDG.E R15, [R2.64+0x4c] ;
STG.E [R4.64+0x13000], R15 ;
LDG.E R17, [R2.64+0x50] ;
STG.E [R4.64+0x14000], R17 ;
LDG.E R19, [R2.64+0x54] ;
STG.E [R4.64+0x15000], R19 ;
LDG.E R21, [R2.64+0x58] ;
STG.E [R4.64+0x16000], R21 ;
LDG.E R23, [R2.64+0x5c] ;
STG.E [R4.64+0x17000], R23 ;
LDG.E R13, [R2.64+0x60] ;
STG.E [R4.64+0x18000], R13 ;
LDG.E R15, [R2.64+0x64] ;
STG.E [R4.64+0x19000], R15 ;
LDG.E R17, [R2.64+0x68] ;
STG.E [R4.64+0x1a000], R17 ;
LDG.E R19, [R2.64+0x6c] ;
STG.E [R4.64+0x1b000], R19 ;
LDG.E R21, [R2.64+0x70] ;
STG.E [R4.64+0x1c000], R21 ;
LDG.E R23, [R2.64+0x74] ;
STG.E [R4.64+0x1d000], R23 ;
LDG.E R13, [R2.64+0x78] ;
STG.E [R4.64+0x1e000], R13 ;
LDG.E R15, [R2.64+0x7c] ;
STG.E [R4.64+0x1f000], R15 ;
LDG.E R17, [R2.64+0x80] ;
STG.E [R4.64+0x20000], R17 ;
LDG.E R19, [R2.64+0x84] ;
STG.E [R4.64+0x21000], R19 ;
LDG.E R21, [R2.64+0x88] ;
STG.E [R4.64+0x22000], R21 ;
LDG.E R23, [R2.64+0x8c] ;
STG.E [R4.64+0x23000], R23 ;
LDG.E R13, [R2.64+0x90] ;
STG.E [R4.64+0x24000], R13 ;
LDG.E R15, [R2.64+0x94] ;
STG.E [R4.64+0x25000], R15 ;
LDG.E R17, [R2.64+0x98] ;
STG.E [R4.64+0x26000], R17 ;
LDG.E R19, [R2.64+0x9c] ;
STG.E [R4.64+0x27000], R19 ;
LDG.E R21, [R2.64+0xa0] ;
STG.E [R4.64+0x28000], R21 ;
LDG.E R23, [R2.64+0xa4] ;
STG.E [R4.64+0x29000], R23 ;
LDG.E R13, [R2.64+0xa8] ;
STG.E [R4.64+0x2a000], R13 ;
LDG.E R15, [R2.64+0xac] ;
STG.E [R4.64+0x2b000], R15 ;
LDG.E R17, [R2.64+0xb0] ;
STG.E [R4.64+0x2c000], R17 ;
LDG.E R19, [R2.64+0xb4] ;
STG.E [R4.64+0x2d000], R19 ;
LDG.E R21, [R2.64+0xb8] ;
STG.E [R4.64+0x2e000], R21 ;
LDG.E R23, [R2.64+0xbc] ;
STG.E [R4.64+0x2f000], R23 ;
LDG.E R13, [R2.64+0xc0] ;
STG.E [R4.64+0x30000], R13 ;
LDG.E R15, [R2.64+0xc4] ;
STG.E [R4.64+0x31000], R15 ;
LDG.E R17, [R2.64+0xc8] ;
STG.E [R4.64+0x32000], R17 ;
LDG.E R19, [R2.64+0xcc] ;
STG.E [R4.64+0x33000], R19 ;
LDG.E R21, [R2.64+0xd0] ;
STG.E [R4.64+0x34000], R21 ;
LDG.E R23, [R2.64+0xd4] ;
STG.E [R4.64+0x35000], R23 ;
LDG.E R13, [R2.64+0xd8] ;
STG.E [R4.64+0x36000], R13 ;
LDG.E R15, [R2.64+0xdc] ;
STG.E [R4.64+0x37000], R15 ;
LDG.E R17, [R2.64+0xe0] ;
STG.E [R4.64+0x38000], R17 ;
LDG.E R19, [R2.64+0xe4] ;
STG.E [R4.64+0x39000], R19 ;
LDG.E R21, [R2.64+0xe8] ;
STG.E [R4.64+0x3a000], R21 ;
LDG.E R23, [R2.64+0xec] ;
STG.E [R4.64+0x3b000], R23 ;
LDG.E R13, [R2.64+0xf0] ;
STG.E [R4.64+0x3c000], R13 ;
LDG.E R15, [R2.64+0xf4] ;
STG.E [R4.64+0x3d000], R15 ;
LDG.E R17, [R2.64+0xf8] ;
IADD3 R12, R12, 0x40, RZ ;
ISETP.NE.AND P0, PT, R12, 0x400, PT ;
STG.E [R4.64+0x3e000], R17 ;
LDG.E R19, [R2.64+0xfc] ;
IADD3 R10, P2, R10, 0x100, RZ ;
IADD3 R8, P1, R8, 0x40000, RZ ;
IMAD.X R11, RZ, RZ, R11, P2 ;
IADD3.X R9, RZ, R9, RZ, P1, !PT ;
STG.E [R4.64+0x3f000], R19 ;
@P0 BRA 0xc0 ;
@!P3 BRA 0x30 ;
EXIT ;
BRA 0x970;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
```
|
```amdasm
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z16transpose_serialPfS_ ; -- Begin function _Z16transpose_serialPfS_
.globl _Z16transpose_serialPfS_
.p2align 8
.type _Z16transpose_serialPfS_,@function
_Z16transpose_serialPfS_: ; @_Z16transpose_serialPfS_
; %bb.0:
s_load_b128 s[0:3], s[0:1], 0x0
v_mov_b32_e32 v0, 0
s_mov_b32 s8, 0
.LBB0_1: ; %.preheader
; =>This Loop Header: Depth=1
; Child Loop BB0_2 Depth 2
s_mov_b64 s[4:5], 0
s_waitcnt lgkmcnt(0)
s_mov_b64 s[6:7], s[2:3]
.LBB0_2: ; Parent Loop BB0_1 Depth=1
; => This Inner Loop Header: Depth=2
s_add_u32 s10, s0, s4
s_addc_u32 s11, s1, s5
s_add_u32 s4, s4, 4
global_load_b32 v1, v0, s[10:11]
s_addc_u32 s5, s5, 0
s_waitcnt vmcnt(0)
global_store_b32 v0, v1, s[6:7]
s_add_u32 s6, s6, 0x1000
s_addc_u32 s7, s7, 0
s_cmpk_eq_i32 s4, 0x1000
s_cbranch_scc0 .LBB0_2
; %bb.3: ; in Loop: Header=BB0_1 Depth=1
s_add_i32 s8, s8, 1
s_add_u32 s2, s2, 4
s_addc_u32 s3, s3, 0
s_add_u32 s0, s0, 0x1000
s_addc_u32 s1, s1, 0
s_cmpk_eq_i32 s8, 0x400
s_cbranch_scc0 .LBB0_1
; %bb.4:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z16transpose_serialPfS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 16
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 12
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z16transpose_serialPfS_, .Lfunc_end0-_Z16transpose_serialPfS_
; -- End function
.section .AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 128
; NumSgprs: 12
; NumVgprs: 2
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 1
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 12
; NumVGPRsForWavesPerEU: 2
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
.text
.protected _Z26transpose_parallel_per_rowPfS_ ; -- Begin function _Z26transpose_parallel_per_rowPfS_
.globl _Z26transpose_parallel_per_rowPfS_
.p2align 8
.type _Z26transpose_parallel_per_rowPfS_,@function
_Z26transpose_parallel_per_rowPfS_: ; @_Z26transpose_parallel_per_rowPfS_
; %bb.0:
s_load_b128 s[0:3], s[0:1], 0x0
v_lshlrev_b32_e32 v1, 2, v0
v_lshlrev_b32_e32 v2, 12, v0
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v0, s0, s0, v1
v_add_co_ci_u32_e64 v1, null, s1, 0, s0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v2, s0, s2, v2
v_add_co_ci_u32_e64 v3, null, s3, 0, s0
s_mov_b64 s[0:1], 0
.LBB1_1: ; =>This Inner Loop Header: Depth=1
global_load_b32 v6, v[0:1], off
v_add_co_u32 v4, vcc_lo, v2, s0
v_add_co_ci_u32_e32 v5, vcc_lo, s1, v3, vcc_lo
v_add_co_u32 v0, vcc_lo, 0x1000, v0
v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
s_add_u32 s0, s0, 4
s_addc_u32 s1, s1, 0
s_cmpk_eq_i32 s0, 0x1000
s_waitcnt vmcnt(0)
global_store_b32 v[4:5], v6, off
s_cbranch_scc0 .LBB1_1
; %bb.2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z26transpose_parallel_per_rowPfS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 16
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 4
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z26transpose_parallel_per_rowPfS_, .Lfunc_end1-_Z26transpose_parallel_per_rowPfS_
; -- End function
.section .AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 140
; NumSgprs: 6
; NumVgprs: 7
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 0
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 6
; NumVGPRsForWavesPerEU: 7
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
.text
.protected _Z30transpose_parallel_per_elementPfS_ ; -- Begin function _Z30transpose_parallel_per_elementPfS_
.globl _Z30transpose_parallel_per_elementPfS_
.p2align 8
.type _Z30transpose_parallel_per_elementPfS_,@function
_Z30transpose_parallel_per_elementPfS_: ; @_Z30transpose_parallel_per_elementPfS_
; %bb.0:
v_and_b32_e32 v1, 0x3ff, v0
v_bfe_u32 v0, v0, 10, 10
s_load_b128 s[0:3], s[0:1], 0x0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshl_add_u32 v2, s14, 5, v1
v_lshl_add_u32 v3, s15, 5, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshl_add_u32 v0, v3, 10, v2
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_load_b32 v4, v[0:1], off
v_lshl_add_u32 v0, v2, 10, v3
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[0:1]
v_add_co_u32 v0, vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
s_waitcnt vmcnt(0)
global_store_b32 v[0:1], v4, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z30transpose_parallel_per_elementPfS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 16
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end2:
.size _Z30transpose_parallel_per_elementPfS_, .Lfunc_end2-_Z30transpose_parallel_per_elementPfS_
; -- End function
.section .AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 164
; NumSgprs: 18
; NumVgprs: 5
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 5
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
.text
.protected _Z36transpose_parallel_per_element_tiledPfS_ ; -- Begin function _Z36transpose_parallel_per_element_tiledPfS_
.globl _Z36transpose_parallel_per_element_tiledPfS_
.p2align 8
.type _Z36transpose_parallel_per_element_tiledPfS_,@function
_Z36transpose_parallel_per_element_tiledPfS_: ; @_Z36transpose_parallel_per_element_tiledPfS_
; %bb.0:
v_bfe_u32 v2, v0, 10, 10
s_lshl_b32 s4, s15, 5
v_and_b32_e32 v3, 0x3ff, v0
s_load_b128 s[0:3], s[0:1], 0x0
s_lshl_b32 s5, s14, 5
v_add_lshl_u32 v0, s4, v2, 10
v_lshlrev_b32_e32 v4, 2, v2
v_add_lshl_u32 v5, s5, v2, 10
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add3_u32 v0, s5, v3, v0
v_lshl_add_u32 v4, v3, 7, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v1, 31, v0
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_load_b32 v1, v[0:1], off
v_lshlrev_b32_e32 v0, 2, v3
s_delay_alu instid0(VALU_DEP_1)
v_lshl_add_u32 v2, v2, 7, v0
v_add3_u32 v0, s4, v3, v5
s_waitcnt vmcnt(0)
ds_store_b32 v2, v1
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
ds_load_b32 v2, v4
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[0:1]
v_add_co_u32 v0, vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
s_waitcnt lgkmcnt(0)
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z36transpose_parallel_per_element_tiledPfS_
.amdhsa_group_segment_fixed_size 4096
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 16
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end3:
.size _Z36transpose_parallel_per_element_tiledPfS_, .Lfunc_end3-_Z36transpose_parallel_per_element_tiledPfS_
; -- End function
.section .AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 232
; NumSgprs: 18
; NumVgprs: 6
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 4096 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 6
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
.text
.protected _Z38transpose_parallel_per_element_tiled16PfS_ ; -- Begin function _Z38transpose_parallel_per_element_tiled16PfS_
.globl _Z38transpose_parallel_per_element_tiled16PfS_
.p2align 8
.type _Z38transpose_parallel_per_element_tiled16PfS_,@function
_Z38transpose_parallel_per_element_tiled16PfS_: ; @_Z38transpose_parallel_per_element_tiled16PfS_
; %bb.0:
v_bfe_u32 v2, v0, 10, 10
s_lshl_b32 s4, s15, 4
v_and_b32_e32 v3, 0x3ff, v0
s_load_b128 s[0:3], s[0:1], 0x0
s_lshl_b32 s5, s14, 4
v_add_lshl_u32 v0, s4, v2, 10
v_lshlrev_b32_e32 v4, 2, v2
v_add_lshl_u32 v5, s5, v2, 10
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add3_u32 v0, s5, v3, v0
v_lshl_add_u32 v4, v3, 6, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v1, 31, v0
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_load_b32 v1, v[0:1], off
v_lshlrev_b32_e32 v0, 2, v3
s_delay_alu instid0(VALU_DEP_1)
v_lshl_add_u32 v2, v2, 6, v0
v_add3_u32 v0, s4, v3, v5
s_waitcnt vmcnt(0)
ds_store_b32 v2, v1
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
ds_load_b32 v2, v4
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[0:1]
v_add_co_u32 v0, vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
s_waitcnt lgkmcnt(0)
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z38transpose_parallel_per_element_tiled16PfS_
.amdhsa_group_segment_fixed_size 1024
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 16
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end4:
.size _Z38transpose_parallel_per_element_tiled16PfS_, .Lfunc_end4-_Z38transpose_parallel_per_element_tiled16PfS_
; -- End function
.section .AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 232
; NumSgprs: 18
; NumVgprs: 6
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 1024 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 6
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
.text
.protected _Z45transpose_parallel_per_element_tiled_padded16PfS_ ; -- Begin function _Z45transpose_parallel_per_element_tiled_padded16PfS_
.globl _Z45transpose_parallel_per_element_tiled_padded16PfS_
.p2align 8
.type _Z45transpose_parallel_per_element_tiled_padded16PfS_,@function
_Z45transpose_parallel_per_element_tiled_padded16PfS_: ; @_Z45transpose_parallel_per_element_tiled_padded16PfS_
; %bb.0:
v_bfe_u32 v2, v0, 10, 10
s_lshl_b32 s4, s15, 4
v_and_b32_e32 v3, 0x3ff, v0
s_load_b128 s[0:3], s[0:1], 0x0
s_lshl_b32 s5, s14, 4
v_add_lshl_u32 v0, s4, v2, 10
v_lshlrev_b32_e32 v4, 2, v2
v_add_lshl_u32 v5, s5, v2, 10
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add3_u32 v0, s5, v3, v0
v_mad_u32_u24 v4, 0x44, v3, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v1, 31, v0
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_load_b32 v1, v[0:1], off
v_lshlrev_b32_e32 v0, 2, v3
s_delay_alu instid0(VALU_DEP_1)
v_mad_u32_u24 v2, 0x44, v2, v0
v_add3_u32 v0, s4, v3, v5
s_waitcnt vmcnt(0)
ds_store_b32 v2, v1
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
ds_load_b32 v2, v4
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[0:1]
v_add_co_u32 v0, vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
s_waitcnt lgkmcnt(0)
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z45transpose_parallel_per_element_tiled_padded16PfS_
.amdhsa_group_segment_fixed_size 1088
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 16
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end5:
.size _Z45transpose_parallel_per_element_tiled_padded16PfS_, .Lfunc_end5-_Z45transpose_parallel_per_element_tiled_padded16PfS_
; -- End function
.section .AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 240
; NumSgprs: 18
; NumVgprs: 6
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 1088 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 6
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object ; @__hip_cuid_
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0 ; 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 16
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z16transpose_serialPfS_
.private_segment_fixed_size: 0
.sgpr_count: 12
.sgpr_spill_count: 0
.symbol: _Z16transpose_serialPfS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 16
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z26transpose_parallel_per_rowPfS_
.private_segment_fixed_size: 0
.sgpr_count: 6
.sgpr_spill_count: 0
.symbol: _Z26transpose_parallel_per_rowPfS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 16
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z30transpose_parallel_per_elementPfS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z30transpose_parallel_per_elementPfS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 4096
.kernarg_segment_align: 8
.kernarg_segment_size: 16
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z36transpose_parallel_per_element_tiledPfS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z36transpose_parallel_per_element_tiledPfS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 1024
.kernarg_segment_align: 8
.kernarg_segment_size: 16
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z38transpose_parallel_per_element_tiled16PfS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z38transpose_parallel_per_element_tiled16PfS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 1088
.kernarg_segment_align: 8
.kernarg_segment_size: 16
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z45transpose_parallel_per_element_tiled_padded16PfS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z45transpose_parallel_per_element_tiled_padded16PfS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
```
| 7,833 | 11,825 |
313 |
Convert the following CUDA host assembly code to AMD host assembly:
```cudaasm
.file "tmpxft_001715a2_00000000-6_transpose.cudafe1.cpp"
.text
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2072:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2072:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .text._ZN8GpuTimer7ElapsedEv,"axG",@progbits,_ZN8GpuTimer7ElapsedEv,comdat
.align 2
.weak _ZN8GpuTimer7ElapsedEv
.type _ZN8GpuTimer7ElapsedEv, @function
_ZN8GpuTimer7ElapsedEv:
.LFB2065:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $16, %rsp
.cfi_def_cfa_offset 32
movq %rdi, %rbx
movq %fs:40, %rax
movq %rax, 8(%rsp)
xorl %eax, %eax
movq 8(%rdi), %rdi
call cudaEventSynchronize@PLT
movq 8(%rbx), %rdx
movq (%rbx), %rsi
leaq 4(%rsp), %rdi
call cudaEventElapsedTime@PLT
movss 4(%rsp), %xmm0
movq 8(%rsp), %rax
subq %fs:40, %rax
jne .L6
addq $16, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L6:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2065:
.size _ZN8GpuTimer7ElapsedEv, .-_ZN8GpuTimer7ElapsedEv
.text
.globl _Z16compare_matricesPfS_
.type _Z16compare_matricesPfS_, @function
_Z16compare_matricesPfS_:
.LFB2066:
.cfi_startproc
endbr64
movl $4096, %edx
.L8:
leaq -4096(%rdx), %rax
.L11:
movss (%rdi,%rax), %xmm0
ucomiss (%rsi,%rax), %xmm0
jp .L12
jne .L12
addq $4, %rax
cmpq %rdx, %rax
jne .L11
addq $4096, %rdx
cmpq $4198400, %rdx
jne .L8
movl $0, %eax
ret
.L12:
movl $1, %eax
ret
.cfi_endproc
.LFE2066:
.size _Z16compare_matricesPfS_, .-_Z16compare_matricesPfS_
.globl _Z11fill_matrixPf
.type _Z11fill_matrixPf, @function
_Z11fill_matrixPf:
.LFB2067:
.cfi_startproc
endbr64
movl $0, %eax
.L17:
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movss %xmm0, (%rdi,%rax,4)
addq $1, %rax
cmpq $1048576, %rax
jne .L17
ret
.cfi_endproc
.LFE2067:
.size _Z11fill_matrixPf, .-_Z11fill_matrixPf
.globl _Z13transpose_CPUPfS_
.type _Z13transpose_CPUPfS_, @function
_Z13transpose_CPUPfS_:
.LFB2068:
.cfi_startproc
endbr64
leaq 4194304(%rsi), %rcx
movl $0, %esi
.L20:
leaq -4194304(%rcx), %rax
movq %rdi, %rdx
.L21:
movss (%rdx), %xmm0
movss %xmm0, (%rax)
addq $4, %rdx
addq $4096, %rax
cmpq %rcx, %rax
jne .L21
addl $1, %esi
addq $4096, %rdi
addq $4, %rcx
cmpl $1024, %esi
jne .L20
ret
.cfi_endproc
.LFE2068:
.size _Z13transpose_CPUPfS_, .-_Z13transpose_CPUPfS_
.globl _Z38__device_stub__Z16transpose_serialPfS_PfS_
.type _Z38__device_stub__Z16transpose_serialPfS_PfS_, @function
_Z38__device_stub__Z16transpose_serialPfS_PfS_:
.LFB2094:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L28
.L24:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L29
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L28:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z16transpose_serialPfS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L24
.L29:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2094:
.size _Z38__device_stub__Z16transpose_serialPfS_PfS_, .-_Z38__device_stub__Z16transpose_serialPfS_PfS_
.globl _Z16transpose_serialPfS_
.type _Z16transpose_serialPfS_, @function
_Z16transpose_serialPfS_:
.LFB2095:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z38__device_stub__Z16transpose_serialPfS_PfS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2095:
.size _Z16transpose_serialPfS_, .-_Z16transpose_serialPfS_
.globl _Z48__device_stub__Z26transpose_parallel_per_rowPfS_PfS_
.type _Z48__device_stub__Z26transpose_parallel_per_rowPfS_PfS_, @function
_Z48__device_stub__Z26transpose_parallel_per_rowPfS_PfS_:
.LFB2096:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L36
.L32:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L37
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L36:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z26transpose_parallel_per_rowPfS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L32
.L37:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2096:
.size _Z48__device_stub__Z26transpose_parallel_per_rowPfS_PfS_, .-_Z48__device_stub__Z26transpose_parallel_per_rowPfS_PfS_
.globl _Z26transpose_parallel_per_rowPfS_
.type _Z26transpose_parallel_per_rowPfS_, @function
_Z26transpose_parallel_per_rowPfS_:
.LFB2097:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z48__device_stub__Z26transpose_parallel_per_rowPfS_PfS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2097:
.size _Z26transpose_parallel_per_rowPfS_, .-_Z26transpose_parallel_per_rowPfS_
.globl _Z52__device_stub__Z30transpose_parallel_per_elementPfS_PfS_
.type _Z52__device_stub__Z30transpose_parallel_per_elementPfS_PfS_, @function
_Z52__device_stub__Z30transpose_parallel_per_elementPfS_PfS_:
.LFB2098:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L44
.L40:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L45
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L44:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z30transpose_parallel_per_elementPfS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L40
.L45:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2098:
.size _Z52__device_stub__Z30transpose_parallel_per_elementPfS_PfS_, .-_Z52__device_stub__Z30transpose_parallel_per_elementPfS_PfS_
.globl _Z30transpose_parallel_per_elementPfS_
.type _Z30transpose_parallel_per_elementPfS_, @function
_Z30transpose_parallel_per_elementPfS_:
.LFB2099:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z52__device_stub__Z30transpose_parallel_per_elementPfS_PfS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2099:
.size _Z30transpose_parallel_per_elementPfS_, .-_Z30transpose_parallel_per_elementPfS_
.globl _Z58__device_stub__Z36transpose_parallel_per_element_tiledPfS_PfS_
.type _Z58__device_stub__Z36transpose_parallel_per_element_tiledPfS_PfS_, @function
_Z58__device_stub__Z36transpose_parallel_per_element_tiledPfS_PfS_:
.LFB2100:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L52
.L48:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L53
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L52:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z36transpose_parallel_per_element_tiledPfS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L48
.L53:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2100:
.size _Z58__device_stub__Z36transpose_parallel_per_element_tiledPfS_PfS_, .-_Z58__device_stub__Z36transpose_parallel_per_element_tiledPfS_PfS_
.globl _Z36transpose_parallel_per_element_tiledPfS_
.type _Z36transpose_parallel_per_element_tiledPfS_, @function
_Z36transpose_parallel_per_element_tiledPfS_:
.LFB2101:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z58__device_stub__Z36transpose_parallel_per_element_tiledPfS_PfS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2101:
.size _Z36transpose_parallel_per_element_tiledPfS_, .-_Z36transpose_parallel_per_element_tiledPfS_
.globl _Z60__device_stub__Z38transpose_parallel_per_element_tiled16PfS_PfS_
.type _Z60__device_stub__Z38transpose_parallel_per_element_tiled16PfS_PfS_, @function
_Z60__device_stub__Z38transpose_parallel_per_element_tiled16PfS_PfS_:
.LFB2102:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L60
.L56:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L61
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L60:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z38transpose_parallel_per_element_tiled16PfS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L56
.L61:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2102:
.size _Z60__device_stub__Z38transpose_parallel_per_element_tiled16PfS_PfS_, .-_Z60__device_stub__Z38transpose_parallel_per_element_tiled16PfS_PfS_
.globl _Z38transpose_parallel_per_element_tiled16PfS_
.type _Z38transpose_parallel_per_element_tiled16PfS_, @function
_Z38transpose_parallel_per_element_tiled16PfS_:
.LFB2103:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z60__device_stub__Z38transpose_parallel_per_element_tiled16PfS_PfS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2103:
.size _Z38transpose_parallel_per_element_tiled16PfS_, .-_Z38transpose_parallel_per_element_tiled16PfS_
.globl _Z67__device_stub__Z45transpose_parallel_per_element_tiled_padded16PfS_PfS_
.type _Z67__device_stub__Z45transpose_parallel_per_element_tiled_padded16PfS_PfS_, @function
_Z67__device_stub__Z45transpose_parallel_per_element_tiled_padded16PfS_PfS_:
.LFB2104:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L68
.L64:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L69
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L68:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z45transpose_parallel_per_element_tiled_padded16PfS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L64
.L69:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2104:
.size _Z67__device_stub__Z45transpose_parallel_per_element_tiled_padded16PfS_PfS_, .-_Z67__device_stub__Z45transpose_parallel_per_element_tiled_padded16PfS_PfS_
.globl _Z45transpose_parallel_per_element_tiled_padded16PfS_
.type _Z45transpose_parallel_per_element_tiled_padded16PfS_, @function
_Z45transpose_parallel_per_element_tiled_padded16PfS_:
.LFB2105:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z67__device_stub__Z45transpose_parallel_per_element_tiled_padded16PfS_PfS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2105:
.size _Z45transpose_parallel_per_element_tiled_padded16PfS_, .-_Z45transpose_parallel_per_element_tiled_padded16PfS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Failed"
.LC1:
.string "Success"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC2:
.string "transpose_serial: %g ms.\nVerifying transpose...%s\n"
.align 8
.LC3:
.string "transpose_parallel_per_row: %g ms.\nVerifying transpose...%s\n"
.align 8
.LC4:
.string "transpose_parallel_per_element: %g ms.\nVerifying transpose...%s\n"
.align 8
.LC5:
.string "transpose_parallel_per_element_tiled %dx%d: %g ms.\nVerifying ...%s\n"
.align 8
.LC6:
.string "transpose_parallel_per_element_tiled 16x16: %g ms.\nVerifying ...%s\n"
.align 8
.LC7:
.string "transpose_parallel_per_element_tiled_padded 16x16: %g ms.\nVerifying...%s\n"
.text
.globl main
.type main, @function
main:
.LFB2069:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA2069
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $136, %rsp
.cfi_def_cfa_offset 176
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
movl $4194304, %edi
call malloc@PLT
movq %rax, %r12
movl $4194304, %edi
call malloc@PLT
movq %rax, %rbx
movl $4194304, %edi
call malloc@PLT
movq %rax, %rbp
movq %r12, %rdi
call _Z11fill_matrixPf
movq %rbp, %rsi
movq %r12, %rdi
call _Z13transpose_CPUPfS_
leaq 8(%rsp), %rdi
movl $4194304, %esi
.LEHB0:
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $4194304, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $4194304, %edx
movq %r12, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
leaq 96(%rsp), %rdi
call cudaEventCreate@PLT
leaq 104(%rsp), %rdi
call cudaEventCreate@PLT
.LEHE0:
movl $0, %esi
movq 96(%rsp), %rdi
.LEHB1:
call cudaEventRecord@PLT
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 84(%rsp), %rdx
movl $1, %ecx
movq 72(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L73
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z38__device_stub__Z16transpose_serialPfS_PfS_
.L73:
movl $0, %esi
movq 104(%rsp), %rdi
call cudaEventRecord@PLT
movl $2, %ecx
movl $4194304, %edx
movq 16(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
movq %rbp, %rsi
movq %rbx, %rdi
call _Z16compare_matricesPfS_
testl %eax, %eax
leaq .LC1(%rip), %r13
leaq .LC0(%rip), %rax
cmovne %rax, %r13
leaq 96(%rsp), %rdi
call _ZN8GpuTimer7ElapsedEv
cvtss2sd %xmm0, %xmm0
movq %r13, %rdx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl $0, %esi
movq 96(%rsp), %rdi
call cudaEventRecord@PLT
movl $1024, 84(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 84(%rsp), %rdx
movl $1, %ecx
movq 72(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L75
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z48__device_stub__Z26transpose_parallel_per_rowPfS_PfS_
.L75:
movl $0, %esi
movq 104(%rsp), %rdi
call cudaEventRecord@PLT
movl $2, %ecx
movl $4194304, %edx
movq 16(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
movq %rbp, %rsi
movq %rbx, %rdi
call _Z16compare_matricesPfS_
testl %eax, %eax
leaq .LC1(%rip), %r13
leaq .LC0(%rip), %rax
cmovne %rax, %r13
leaq 96(%rsp), %rdi
call _ZN8GpuTimer7ElapsedEv
cvtss2sd %xmm0, %xmm0
movq %r13, %rdx
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl $32, 24(%rsp)
movl $32, 28(%rsp)
movl $1, 32(%rsp)
movl $32, 36(%rsp)
movl $32, 40(%rsp)
movl $1, 44(%rsp)
movl $0, %esi
movq 96(%rsp), %rdi
call cudaEventRecord@PLT
movl 44(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 36(%rsp), %rdx
movq 24(%rsp), %rdi
movl 32(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L77
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z52__device_stub__Z30transpose_parallel_per_elementPfS_PfS_
.L77:
movl $0, %esi
movq 104(%rsp), %rdi
call cudaEventRecord@PLT
movl $2, %ecx
movl $4194304, %edx
movq 16(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
movq %rbp, %rsi
movq %rbx, %rdi
call _Z16compare_matricesPfS_
testl %eax, %eax
leaq .LC1(%rip), %r13
leaq .LC0(%rip), %rax
cmovne %rax, %r13
leaq 96(%rsp), %rdi
call _ZN8GpuTimer7ElapsedEv
cvtss2sd %xmm0, %xmm0
movq %r13, %rdx
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl $32, 48(%rsp)
movl $32, 52(%rsp)
movl $1, 56(%rsp)
movl $32, 60(%rsp)
movl $32, 64(%rsp)
movl $1, 68(%rsp)
movl $0, %esi
movq 96(%rsp), %rdi
call cudaEventRecord@PLT
movl 68(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 60(%rsp), %rdx
movq 48(%rsp), %rdi
movl 56(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L79
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z58__device_stub__Z36transpose_parallel_per_element_tiledPfS_PfS_
.L79:
movl $0, %esi
movq 104(%rsp), %rdi
call cudaEventRecord@PLT
movl $2, %ecx
movl $4194304, %edx
movq 16(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
movq %rbp, %rsi
movq %rbx, %rdi
call _Z16compare_matricesPfS_
testl %eax, %eax
leaq .LC1(%rip), %r13
leaq .LC0(%rip), %rax
cmovne %rax, %r13
leaq 96(%rsp), %rdi
call _ZN8GpuTimer7ElapsedEv
cvtss2sd %xmm0, %xmm0
movq %r13, %r8
movl $32, %ecx
movl $32, %edx
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl $64, 72(%rsp)
movl $64, 76(%rsp)
movl $1, 80(%rsp)
movl $16, 84(%rsp)
movl $16, 88(%rsp)
movl $1, 92(%rsp)
movl $0, %esi
movq 96(%rsp), %rdi
call cudaEventRecord@PLT
movl 92(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 84(%rsp), %rdx
movq 72(%rsp), %rdi
movl 80(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L81
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z60__device_stub__Z38transpose_parallel_per_element_tiled16PfS_PfS_
.L81:
movl $0, %esi
movq 104(%rsp), %rdi
call cudaEventRecord@PLT
movl $2, %ecx
movl $4194304, %edx
movq 16(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
movq %rbp, %rsi
movq %rbx, %rdi
call _Z16compare_matricesPfS_
testl %eax, %eax
leaq .LC1(%rip), %r13
leaq .LC0(%rip), %rax
cmovne %rax, %r13
leaq 96(%rsp), %rdi
call _ZN8GpuTimer7ElapsedEv
cvtss2sd %xmm0, %xmm0
movq %r13, %rdx
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl $0, %esi
movq 96(%rsp), %rdi
call cudaEventRecord@PLT
movl 92(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 84(%rsp), %rdx
movq 72(%rsp), %rdi
movl 80(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L83
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z67__device_stub__Z45transpose_parallel_per_element_tiled_padded16PfS_PfS_
.L83:
movl $0, %esi
movq 104(%rsp), %rdi
call cudaEventRecord@PLT
movl $2, %ecx
movl $4194304, %edx
movq 16(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
movq %rbp, %rsi
movq %rbx, %rdi
call _Z16compare_matricesPfS_
testl %eax, %eax
leaq .LC1(%rip), %r13
leaq .LC0(%rip), %rax
cmovne %rax, %r13
leaq 96(%rsp), %rdi
call _ZN8GpuTimer7ElapsedEv
cvtss2sd %xmm0, %xmm0
movq %r13, %rdx
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
.LEHE1:
movq %r12, %rdi
call free@PLT
movq %rbx, %rdi
call free@PLT
movq %rbp, %rdi
call free@PLT
movq 96(%rsp), %rdi
call cudaEventDestroy@PLT
movq 104(%rsp), %rdi
call cudaEventDestroy@PLT
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L97
movl $0, %eax
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L94:
.cfi_restore_state
endbr64
movq %rax, %rbx
movq 96(%rsp), %rdi
call cudaEventDestroy@PLT
movq 104(%rsp), %rdi
call cudaEventDestroy@PLT
movq 120(%rsp), %rax
subq %fs:40, %rax
je .L86
call __stack_chk_fail@PLT
.L86:
movq %rbx, %rdi
.LEHB2:
call _Unwind_Resume@PLT
.LEHE2:
.L97:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2069:
.globl __gxx_personality_v0
.section .gcc_except_table,"a",@progbits
.LLSDA2069:
.byte 0xff
.byte 0xff
.byte 0x1
.uleb128 .LLSDACSE2069-.LLSDACSB2069
.LLSDACSB2069:
.uleb128 .LEHB0-.LFB2069
.uleb128 .LEHE0-.LEHB0
.uleb128 0
.uleb128 0
.uleb128 .LEHB1-.LFB2069
.uleb128 .LEHE1-.LEHB1
.uleb128 .L94-.LFB2069
.uleb128 0
.uleb128 .LEHB2-.LFB2069
.uleb128 .LEHE2-.LEHB2
.uleb128 0
.uleb128 0
.LLSDACSE2069:
.text
.size main, .-main
.section .rodata.str1.8
.align 8
.LC8:
.string "_Z45transpose_parallel_per_element_tiled_padded16PfS_"
.align 8
.LC9:
.string "_Z38transpose_parallel_per_element_tiled16PfS_"
.align 8
.LC10:
.string "_Z36transpose_parallel_per_element_tiledPfS_"
.align 8
.LC11:
.string "_Z30transpose_parallel_per_elementPfS_"
.align 8
.LC12:
.string "_Z26transpose_parallel_per_rowPfS_"
.section .rodata.str1.1
.LC13:
.string "_Z16transpose_serialPfS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2107:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _Z45transpose_parallel_per_element_tiled_padded16PfS_(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC9(%rip), %rdx
movq %rdx, %rcx
leaq _Z38transpose_parallel_per_element_tiled16PfS_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC10(%rip), %rdx
movq %rdx, %rcx
leaq _Z36transpose_parallel_per_element_tiledPfS_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC11(%rip), %rdx
movq %rdx, %rcx
leaq _Z30transpose_parallel_per_elementPfS_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC12(%rip), %rdx
movq %rdx, %rcx
leaq _Z26transpose_parallel_per_rowPfS_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC13(%rip), %rdx
movq %rdx, %rcx
leaq _Z16transpose_serialPfS_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2107:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.hidden DW.ref.__gxx_personality_v0
.weak DW.ref.__gxx_personality_v0
.section .data.rel.local.DW.ref.__gxx_personality_v0,"awG",@progbits,DW.ref.__gxx_personality_v0,comdat
.align 8
.type DW.ref.__gxx_personality_v0, @object
.size DW.ref.__gxx_personality_v0, 8
DW.ref.__gxx_personality_v0:
.quad __gxx_personality_v0
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
```
|
```amdasm
.text
.file "transpose.hip"
.globl _Z16compare_matricesPfS_ # -- Begin function _Z16compare_matricesPfS_
.type _Z16compare_matricesPfS_,@function
_Z16compare_matricesPfS_: # @_Z16compare_matricesPfS_
.cfi_startproc
# %bb.0:
movb $1, %al
xorl %edx, %edx
movl $4096, %ecx # imm = 0x1000
.LBB0_1: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB0_3 Depth 2
xorl %r8d, %r8d
.LBB0_3: # Parent Loop BB0_1 Depth=1
# => This Inner Loop Header: Depth=2
movss (%rdi,%r8,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
ucomiss (%rsi,%r8,4), %xmm0
jne .LBB0_5
jp .LBB0_5
# %bb.2: # in Loop: Header=BB0_3 Depth=2
incq %r8
cmpq $1024, %r8 # imm = 0x400
jne .LBB0_3
# %bb.4: # in Loop: Header=BB0_1 Depth=1
cmpq $1023, %rdx # imm = 0x3FF
leaq 1(%rdx), %r8
setb %al
addq %rcx, %rsi
addq %rcx, %rdi
movq %r8, %rdx
cmpq $1024, %r8 # imm = 0x400
jne .LBB0_1
.LBB0_5: # %.loopexit
movzbl %al, %eax
andl $1, %eax
retq
.Lfunc_end0:
.size _Z16compare_matricesPfS_, .Lfunc_end0-_Z16compare_matricesPfS_
.cfi_endproc
# -- End function
.globl _Z11fill_matrixPf # -- Begin function _Z11fill_matrixPf
.type _Z11fill_matrixPf,@function
_Z11fill_matrixPf: # @_Z11fill_matrixPf
.cfi_startproc
# %bb.0:
xorl %eax, %eax
.LBB1_1: # =>This Inner Loop Header: Depth=1
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movss %xmm0, (%rdi,%rax,4)
incq %rax
cmpq $1048576, %rax # imm = 0x100000
jne .LBB1_1
# %bb.2:
retq
.Lfunc_end1:
.size _Z11fill_matrixPf, .Lfunc_end1-_Z11fill_matrixPf
.cfi_endproc
# -- End function
.globl _Z13transpose_CPUPfS_ # -- Begin function _Z13transpose_CPUPfS_
.type _Z13transpose_CPUPfS_,@function
_Z13transpose_CPUPfS_: # @_Z13transpose_CPUPfS_
.cfi_startproc
# %bb.0:
xorl %eax, %eax
.LBB2_1: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB2_2 Depth 2
movq %rsi, %rcx
xorl %edx, %edx
.LBB2_2: # Parent Loop BB2_1 Depth=1
# => This Inner Loop Header: Depth=2
movss (%rdi,%rdx,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
movss %xmm0, (%rcx)
incq %rdx
addq $4096, %rcx # imm = 0x1000
cmpq $1024, %rdx # imm = 0x400
jne .LBB2_2
# %bb.3: # in Loop: Header=BB2_1 Depth=1
incq %rax
addq $4096, %rdi # imm = 0x1000
addq $4, %rsi
cmpq $1024, %rax # imm = 0x400
jne .LBB2_1
# %bb.4:
retq
.Lfunc_end2:
.size _Z13transpose_CPUPfS_, .Lfunc_end2-_Z13transpose_CPUPfS_
.cfi_endproc
# -- End function
.globl _Z31__device_stub__transpose_serialPfS_ # -- Begin function _Z31__device_stub__transpose_serialPfS_
.type _Z31__device_stub__transpose_serialPfS_,@function
_Z31__device_stub__transpose_serialPfS_: # @_Z31__device_stub__transpose_serialPfS_
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $80, %rsp
.cfi_def_cfa_offset 128
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 24(%rsp), %rax
movq %rdi, (%rax)
leaq 16(%rsp), %rcx
movq %rsi, (%rcx)
leaq 64(%rsp), %rbx
movq %rax, (%rbx)
movq %rcx, 8(%rbx)
leaq 48(%rsp), %r14
leaq 32(%rsp), %r15
leaq 8(%rsp), %r12
movq %rsp, %r13
movq %r14, %rdi
movq %r15, %rsi
movq %r12, %rdx
movq %r13, %rcx
callq __hipPopCallConfiguration
movq (%r14), %rsi
movl 8(%r14), %edx
movq (%r15), %rcx
movl 8(%r15), %r8d
movl $_Z16transpose_serialPfS_, %edi
movq %rbx, %r9
pushq (%r13)
.cfi_adjust_cfa_offset 8
pushq (%r12)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $96, %rsp
.cfi_adjust_cfa_offset -96
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size _Z31__device_stub__transpose_serialPfS_, .Lfunc_end3-_Z31__device_stub__transpose_serialPfS_
.cfi_endproc
# -- End function
.globl _Z41__device_stub__transpose_parallel_per_rowPfS_ # -- Begin function _Z41__device_stub__transpose_parallel_per_rowPfS_
.type _Z41__device_stub__transpose_parallel_per_rowPfS_,@function
_Z41__device_stub__transpose_parallel_per_rowPfS_: # @_Z41__device_stub__transpose_parallel_per_rowPfS_
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $80, %rsp
.cfi_def_cfa_offset 128
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 24(%rsp), %rax
movq %rdi, (%rax)
leaq 16(%rsp), %rcx
movq %rsi, (%rcx)
leaq 64(%rsp), %rbx
movq %rax, (%rbx)
movq %rcx, 8(%rbx)
leaq 48(%rsp), %r14
leaq 32(%rsp), %r15
leaq 8(%rsp), %r12
movq %rsp, %r13
movq %r14, %rdi
movq %r15, %rsi
movq %r12, %rdx
movq %r13, %rcx
callq __hipPopCallConfiguration
movq (%r14), %rsi
movl 8(%r14), %edx
movq (%r15), %rcx
movl 8(%r15), %r8d
movl $_Z26transpose_parallel_per_rowPfS_, %edi
movq %rbx, %r9
pushq (%r13)
.cfi_adjust_cfa_offset 8
pushq (%r12)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $96, %rsp
.cfi_adjust_cfa_offset -96
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end4:
.size _Z41__device_stub__transpose_parallel_per_rowPfS_, .Lfunc_end4-_Z41__device_stub__transpose_parallel_per_rowPfS_
.cfi_endproc
# -- End function
.globl _Z45__device_stub__transpose_parallel_per_elementPfS_ # -- Begin function _Z45__device_stub__transpose_parallel_per_elementPfS_
.type _Z45__device_stub__transpose_parallel_per_elementPfS_,@function
_Z45__device_stub__transpose_parallel_per_elementPfS_: # @_Z45__device_stub__transpose_parallel_per_elementPfS_
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $80, %rsp
.cfi_def_cfa_offset 128
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 24(%rsp), %rax
movq %rdi, (%rax)
leaq 16(%rsp), %rcx
movq %rsi, (%rcx)
leaq 64(%rsp), %rbx
movq %rax, (%rbx)
movq %rcx, 8(%rbx)
leaq 48(%rsp), %r14
leaq 32(%rsp), %r15
leaq 8(%rsp), %r12
movq %rsp, %r13
movq %r14, %rdi
movq %r15, %rsi
movq %r12, %rdx
movq %r13, %rcx
callq __hipPopCallConfiguration
movq (%r14), %rsi
movl 8(%r14), %edx
movq (%r15), %rcx
movl 8(%r15), %r8d
movl $_Z30transpose_parallel_per_elementPfS_, %edi
movq %rbx, %r9
pushq (%r13)
.cfi_adjust_cfa_offset 8
pushq (%r12)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $96, %rsp
.cfi_adjust_cfa_offset -96
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end5:
.size _Z45__device_stub__transpose_parallel_per_elementPfS_, .Lfunc_end5-_Z45__device_stub__transpose_parallel_per_elementPfS_
.cfi_endproc
# -- End function
.globl _Z51__device_stub__transpose_parallel_per_element_tiledPfS_ # -- Begin function _Z51__device_stub__transpose_parallel_per_element_tiledPfS_
.type _Z51__device_stub__transpose_parallel_per_element_tiledPfS_,@function
_Z51__device_stub__transpose_parallel_per_element_tiledPfS_: # @_Z51__device_stub__transpose_parallel_per_element_tiledPfS_
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $80, %rsp
.cfi_def_cfa_offset 128
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 24(%rsp), %rax
movq %rdi, (%rax)
leaq 16(%rsp), %rcx
movq %rsi, (%rcx)
leaq 64(%rsp), %rbx
movq %rax, (%rbx)
movq %rcx, 8(%rbx)
leaq 48(%rsp), %r14
leaq 32(%rsp), %r15
leaq 8(%rsp), %r12
movq %rsp, %r13
movq %r14, %rdi
movq %r15, %rsi
movq %r12, %rdx
movq %r13, %rcx
callq __hipPopCallConfiguration
movq (%r14), %rsi
movl 8(%r14), %edx
movq (%r15), %rcx
movl 8(%r15), %r8d
movl $_Z36transpose_parallel_per_element_tiledPfS_, %edi
movq %rbx, %r9
pushq (%r13)
.cfi_adjust_cfa_offset 8
pushq (%r12)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $96, %rsp
.cfi_adjust_cfa_offset -96
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end6:
.size _Z51__device_stub__transpose_parallel_per_element_tiledPfS_, .Lfunc_end6-_Z51__device_stub__transpose_parallel_per_element_tiledPfS_
.cfi_endproc
# -- End function
.globl _Z53__device_stub__transpose_parallel_per_element_tiled16PfS_ # -- Begin function _Z53__device_stub__transpose_parallel_per_element_tiled16PfS_
.type _Z53__device_stub__transpose_parallel_per_element_tiled16PfS_,@function
_Z53__device_stub__transpose_parallel_per_element_tiled16PfS_: # @_Z53__device_stub__transpose_parallel_per_element_tiled16PfS_
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $80, %rsp
.cfi_def_cfa_offset 128
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 24(%rsp), %rax
movq %rdi, (%rax)
leaq 16(%rsp), %rcx
movq %rsi, (%rcx)
leaq 64(%rsp), %rbx
movq %rax, (%rbx)
movq %rcx, 8(%rbx)
leaq 48(%rsp), %r14
leaq 32(%rsp), %r15
leaq 8(%rsp), %r12
movq %rsp, %r13
movq %r14, %rdi
movq %r15, %rsi
movq %r12, %rdx
movq %r13, %rcx
callq __hipPopCallConfiguration
movq (%r14), %rsi
movl 8(%r14), %edx
movq (%r15), %rcx
movl 8(%r15), %r8d
movl $_Z38transpose_parallel_per_element_tiled16PfS_, %edi
movq %rbx, %r9
pushq (%r13)
.cfi_adjust_cfa_offset 8
pushq (%r12)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $96, %rsp
.cfi_adjust_cfa_offset -96
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end7:
.size _Z53__device_stub__transpose_parallel_per_element_tiled16PfS_, .Lfunc_end7-_Z53__device_stub__transpose_parallel_per_element_tiled16PfS_
.cfi_endproc
# -- End function
.globl _Z60__device_stub__transpose_parallel_per_element_tiled_padded16PfS_ # -- Begin function _Z60__device_stub__transpose_parallel_per_element_tiled_padded16PfS_
.type _Z60__device_stub__transpose_parallel_per_element_tiled_padded16PfS_,@function
_Z60__device_stub__transpose_parallel_per_element_tiled_padded16PfS_: # @_Z60__device_stub__transpose_parallel_per_element_tiled_padded16PfS_
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $80, %rsp
.cfi_def_cfa_offset 128
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 24(%rsp), %rax
movq %rdi, (%rax)
leaq 16(%rsp), %rcx
movq %rsi, (%rcx)
leaq 64(%rsp), %rbx
movq %rax, (%rbx)
movq %rcx, 8(%rbx)
leaq 48(%rsp), %r14
leaq 32(%rsp), %r15
leaq 8(%rsp), %r12
movq %rsp, %r13
movq %r14, %rdi
movq %r15, %rsi
movq %r12, %rdx
movq %r13, %rcx
callq __hipPopCallConfiguration
movq (%r14), %rsi
movl 8(%r14), %edx
movq (%r15), %rcx
movl 8(%r15), %r8d
movl $_Z45transpose_parallel_per_element_tiled_padded16PfS_, %edi
movq %rbx, %r9
pushq (%r13)
.cfi_adjust_cfa_offset 8
pushq (%r12)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $96, %rsp
.cfi_adjust_cfa_offset -96
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end8:
.size _Z60__device_stub__transpose_parallel_per_element_tiled_padded16PfS_, .Lfunc_end8-_Z60__device_stub__transpose_parallel_per_element_tiled_padded16PfS_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.type main,@function
main: # @main
.Lfunc_begin0:
.cfi_startproc
.cfi_personality 3, __gxx_personality_v0
.cfi_lsda 3, .Lexception0
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $40, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $4194304, %edi # imm = 0x400000
callq malloc
movq %rax, %rbx
movl $4194304, %edi # imm = 0x400000
callq malloc
movq %rax, %r14
movl $4194304, %edi # imm = 0x400000
callq malloc
movq %rax, %r15
xorl %eax, %eax
.LBB9_1: # =>This Inner Loop Header: Depth=1
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movss %xmm0, (%rbx,%rax,4)
incq %rax
cmpq $1048576, %rax # imm = 0x100000
jne .LBB9_1
# %bb.2: # %.preheader.i.preheader
xorl %eax, %eax
movq %rbx, %rcx
movq %r15, %rdx
.LBB9_3: # %.preheader.i
# =>This Loop Header: Depth=1
# Child Loop BB9_4 Depth 2
movq %rdx, %rsi
xorl %edi, %edi
.LBB9_4: # Parent Loop BB9_3 Depth=1
# => This Inner Loop Header: Depth=2
movss (%rcx,%rdi,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
movss %xmm0, (%rsi)
incq %rdi
addq $4096, %rsi # imm = 0x1000
cmpq $1024, %rdi # imm = 0x400
jne .LBB9_4
# %bb.5: # in Loop: Header=BB9_3 Depth=1
incq %rax
addq $4, %rdx
addq $4096, %rcx # imm = 0x1000
cmpq $1024, %rax # imm = 0x400
jne .LBB9_3
# %bb.6: # %_Z13transpose_CPUPfS_.exit
leaq 32(%rsp), %r12
movl $4194304, %esi # imm = 0x400000
movq %r12, %rdi
callq hipMalloc
leaq 24(%rsp), %rdi
movl $4194304, %esi # imm = 0x400000
callq hipMalloc
movq (%r12), %rdi
movl $4194304, %edx # imm = 0x400000
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
leaq 8(%rsp), %rdi
callq hipEventCreate
leaq 16(%rsp), %r12
movq %r12, %rdi
callq hipEventCreate
movq -8(%r12), %rdi
.Ltmp0:
xorl %esi, %esi
callq hipEventRecord
.Ltmp1:
# %bb.7: # %_ZN8GpuTimer5StartEv.exit
.Ltmp2:
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
.Ltmp3:
# %bb.8:
testl %eax, %eax
jne .LBB9_10
# %bb.9:
movq 32(%rsp), %rdi
movq 24(%rsp), %rsi
.Ltmp4:
callq _Z31__device_stub__transpose_serialPfS_
.Ltmp5:
.LBB9_10:
movq 16(%rsp), %rdi
.Ltmp6:
xorl %esi, %esi
callq hipEventRecord
.Ltmp7:
# %bb.11: # %_ZN8GpuTimer4StopEv.exit
movq 24(%rsp), %rsi
.Ltmp8:
movl $4194304, %edx # imm = 0x400000
movq %r14, %rdi
movl $2, %ecx
callq hipMemcpy
.Ltmp9:
# %bb.12:
movq 16(%rsp), %rdi
.Ltmp10:
callq hipEventSynchronize
.Ltmp11:
# %bb.13: # %.noexc
movq 8(%rsp), %rsi
movq 16(%rsp), %rdx
.Ltmp12:
leaq 4(%rsp), %rdi
callq hipEventElapsedTime
.Ltmp13:
# %bb.14:
cvtss2sd 4(%rsp), %xmm0
movb $1, %al
xorl %edi, %edi
movl $4096, %ecx # imm = 0x1000
movq %r14, %rdx
movq %r15, %rsi
.LBB9_15: # %.preheader.i86
# =>This Loop Header: Depth=1
# Child Loop BB9_17 Depth 2
xorl %r8d, %r8d
.LBB9_17: # Parent Loop BB9_15 Depth=1
# => This Inner Loop Header: Depth=2
movss (%rdx,%r8,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
ucomiss (%rsi,%r8,4), %xmm1
jne .LBB9_19
jp .LBB9_19
# %bb.16: # in Loop: Header=BB9_17 Depth=2
incq %r8
cmpq $1024, %r8 # imm = 0x400
jne .LBB9_17
# %bb.18: # in Loop: Header=BB9_15 Depth=1
cmpq $1023, %rdi # imm = 0x3FF
leaq 1(%rdi), %r8
setb %al
addq %rcx, %rsi
addq %rcx, %rdx
movq %r8, %rdi
cmpq $1024, %r8 # imm = 0x400
jne .LBB9_15
.LBB9_19: # %_Z16compare_matricesPfS_.exit
movl $.L.str.1, %ecx
movl $.L.str.2, %esi
testb $1, %al
cmovneq %rcx, %rsi
movl $.L.str, %edi
movb $1, %al
callq printf
movq 8(%rsp), %rdi
.Ltmp14:
xorl %esi, %esi
callq hipEventRecord
.Ltmp15:
# %bb.20: # %_ZN8GpuTimer5StartEv.exit90
.Ltmp16:
movabsq $4294967297, %rdi # imm = 0x100000001
movabsq $4294968320, %rdx # imm = 0x100000400
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
.Ltmp17:
# %bb.21:
testl %eax, %eax
jne .LBB9_23
# %bb.22:
movq 32(%rsp), %rdi
movq 24(%rsp), %rsi
.Ltmp18:
callq _Z41__device_stub__transpose_parallel_per_rowPfS_
.Ltmp19:
.LBB9_23:
movq 16(%rsp), %rdi
.Ltmp20:
xorl %esi, %esi
callq hipEventRecord
.Ltmp21:
# %bb.24: # %_ZN8GpuTimer4StopEv.exit92
movq 24(%rsp), %rsi
.Ltmp22:
movl $4194304, %edx # imm = 0x400000
movq %r14, %rdi
movl $2, %ecx
callq hipMemcpy
.Ltmp23:
# %bb.25:
movq 16(%rsp), %rdi
.Ltmp24:
callq hipEventSynchronize
.Ltmp25:
# %bb.26: # %.noexc93
movq 8(%rsp), %rsi
movq 16(%rsp), %rdx
.Ltmp26:
leaq 4(%rsp), %rdi
callq hipEventElapsedTime
.Ltmp27:
# %bb.27:
xorps %xmm0, %xmm0
cvtss2sd 4(%rsp), %xmm0
movb $1, %al
xorl %edi, %edi
movl $4096, %ecx # imm = 0x1000
movq %r14, %rdx
movq %r15, %rsi
.LBB9_28: # %.preheader.i96
# =>This Loop Header: Depth=1
# Child Loop BB9_30 Depth 2
xorl %r8d, %r8d
.LBB9_30: # Parent Loop BB9_28 Depth=1
# => This Inner Loop Header: Depth=2
movss (%rdx,%r8,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
ucomiss (%rsi,%r8,4), %xmm1
jne .LBB9_32
jp .LBB9_32
# %bb.29: # in Loop: Header=BB9_30 Depth=2
incq %r8
cmpq $1024, %r8 # imm = 0x400
jne .LBB9_30
# %bb.31: # in Loop: Header=BB9_28 Depth=1
cmpq $1023, %rdi # imm = 0x3FF
leaq 1(%rdi), %r8
setb %al
addq %rcx, %rsi
addq %rcx, %rdx
movq %r8, %rdi
cmpq $1024, %r8 # imm = 0x400
jne .LBB9_28
.LBB9_32: # %_Z16compare_matricesPfS_.exit104
movl $.L.str.1, %ecx
movl $.L.str.2, %esi
testb $1, %al
cmovneq %rcx, %rsi
movl $.L.str.3, %edi
movb $1, %al
callq printf
movq 8(%rsp), %rdi
.Ltmp29:
xorl %esi, %esi
callq hipEventRecord
.Ltmp30:
# %bb.33: # %_ZN8GpuTimer5StartEv.exit106
.Ltmp31:
movabsq $137438953504, %rdi # imm = 0x2000000020
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
.Ltmp32:
# %bb.34:
testl %eax, %eax
jne .LBB9_36
# %bb.35:
movq 32(%rsp), %rdi
movq 24(%rsp), %rsi
.Ltmp33:
callq _Z45__device_stub__transpose_parallel_per_elementPfS_
.Ltmp34:
.LBB9_36:
movq 16(%rsp), %rdi
.Ltmp35:
xorl %esi, %esi
callq hipEventRecord
.Ltmp36:
# %bb.37: # %_ZN8GpuTimer4StopEv.exit108
movq 24(%rsp), %rsi
.Ltmp37:
movl $4194304, %edx # imm = 0x400000
movq %r14, %rdi
movl $2, %ecx
callq hipMemcpy
.Ltmp38:
# %bb.38:
movq 16(%rsp), %rdi
.Ltmp39:
callq hipEventSynchronize
.Ltmp40:
# %bb.39: # %.noexc109
movq 8(%rsp), %rsi
movq 16(%rsp), %rdx
.Ltmp41:
leaq 4(%rsp), %rdi
callq hipEventElapsedTime
.Ltmp42:
# %bb.40:
xorps %xmm0, %xmm0
cvtss2sd 4(%rsp), %xmm0
movb $1, %al
xorl %edi, %edi
movl $4096, %ecx # imm = 0x1000
movq %r14, %rdx
movq %r15, %rsi
.LBB9_41: # %.preheader.i112
# =>This Loop Header: Depth=1
# Child Loop BB9_43 Depth 2
xorl %r8d, %r8d
.LBB9_43: # Parent Loop BB9_41 Depth=1
# => This Inner Loop Header: Depth=2
movss (%rdx,%r8,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
ucomiss (%rsi,%r8,4), %xmm1
jne .LBB9_45
jp .LBB9_45
# %bb.42: # in Loop: Header=BB9_43 Depth=2
incq %r8
cmpq $1024, %r8 # imm = 0x400
jne .LBB9_43
# %bb.44: # in Loop: Header=BB9_41 Depth=1
cmpq $1023, %rdi # imm = 0x3FF
leaq 1(%rdi), %r8
setb %al
addq %rcx, %rsi
addq %rcx, %rdx
movq %r8, %rdi
cmpq $1024, %r8 # imm = 0x400
jne .LBB9_41
.LBB9_45: # %_Z16compare_matricesPfS_.exit120
movl $.L.str.1, %ecx
movl $.L.str.2, %esi
testb $1, %al
cmovneq %rcx, %rsi
movl $.L.str.4, %edi
movb $1, %al
callq printf
movq 8(%rsp), %rdi
.Ltmp44:
xorl %esi, %esi
callq hipEventRecord
.Ltmp45:
# %bb.46: # %_ZN8GpuTimer5StartEv.exit122
.Ltmp46:
movabsq $137438953504, %rdi # imm = 0x2000000020
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
.Ltmp47:
# %bb.47:
testl %eax, %eax
jne .LBB9_49
# %bb.48:
movq 32(%rsp), %rdi
movq 24(%rsp), %rsi
.Ltmp48:
callq _Z51__device_stub__transpose_parallel_per_element_tiledPfS_
.Ltmp49:
.LBB9_49:
movq 16(%rsp), %rdi
.Ltmp50:
xorl %esi, %esi
callq hipEventRecord
.Ltmp51:
# %bb.50: # %_ZN8GpuTimer4StopEv.exit124
movq 24(%rsp), %rsi
.Ltmp52:
movl $4194304, %edx # imm = 0x400000
movq %r14, %rdi
movl $2, %ecx
callq hipMemcpy
.Ltmp53:
# %bb.51:
movq 16(%rsp), %rdi
.Ltmp54:
callq hipEventSynchronize
.Ltmp55:
# %bb.52: # %.noexc125
movq 8(%rsp), %rsi
movq 16(%rsp), %rdx
.Ltmp56:
leaq 4(%rsp), %rdi
callq hipEventElapsedTime
.Ltmp57:
# %bb.53:
xorps %xmm0, %xmm0
cvtss2sd 4(%rsp), %xmm0
movb $1, %al
xorl %edi, %edi
movl $4096, %ecx # imm = 0x1000
movq %r14, %rdx
movq %r15, %rsi
.LBB9_54: # %.preheader.i128
# =>This Loop Header: Depth=1
# Child Loop BB9_56 Depth 2
xorl %r8d, %r8d
.LBB9_56: # Parent Loop BB9_54 Depth=1
# => This Inner Loop Header: Depth=2
movss (%rdx,%r8,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
ucomiss (%rsi,%r8,4), %xmm1
jne .LBB9_58
jp .LBB9_58
# %bb.55: # in Loop: Header=BB9_56 Depth=2
incq %r8
cmpq $1024, %r8 # imm = 0x400
jne .LBB9_56
# %bb.57: # in Loop: Header=BB9_54 Depth=1
cmpq $1023, %rdi # imm = 0x3FF
leaq 1(%rdi), %r8
setb %al
addq %rcx, %rsi
addq %rcx, %rdx
movq %r8, %rdi
cmpq $1024, %r8 # imm = 0x400
jne .LBB9_54
.LBB9_58: # %_Z16compare_matricesPfS_.exit136
movl $.L.str.1, %edx
movl $.L.str.2, %ecx
testb $1, %al
cmovneq %rdx, %rcx
movl $.L.str.5, %edi
movl $32, %esi
movl $32, %edx
movb $1, %al
callq printf
movq 8(%rsp), %rdi
.Ltmp59:
xorl %esi, %esi
callq hipEventRecord
.Ltmp60:
# %bb.59: # %_ZN8GpuTimer5StartEv.exit138
.Ltmp61:
movabsq $274877907008, %rdi # imm = 0x4000000040
movabsq $68719476752, %rdx # imm = 0x1000000010
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
.Ltmp62:
# %bb.60:
testl %eax, %eax
jne .LBB9_62
# %bb.61:
movq 32(%rsp), %rdi
movq 24(%rsp), %rsi
.Ltmp63:
callq _Z53__device_stub__transpose_parallel_per_element_tiled16PfS_
.Ltmp64:
.LBB9_62:
movq 16(%rsp), %rdi
.Ltmp65:
xorl %esi, %esi
callq hipEventRecord
.Ltmp66:
# %bb.63: # %_ZN8GpuTimer4StopEv.exit140
movq 24(%rsp), %rsi
.Ltmp67:
movl $4194304, %edx # imm = 0x400000
movq %r14, %rdi
movl $2, %ecx
callq hipMemcpy
.Ltmp68:
# %bb.64:
movq 16(%rsp), %rdi
.Ltmp69:
callq hipEventSynchronize
.Ltmp70:
# %bb.65: # %.noexc141
movq 8(%rsp), %rsi
movq 16(%rsp), %rdx
.Ltmp71:
leaq 4(%rsp), %rdi
callq hipEventElapsedTime
.Ltmp72:
# %bb.66:
xorps %xmm0, %xmm0
cvtss2sd 4(%rsp), %xmm0
movb $1, %al
xorl %edi, %edi
movl $4096, %ecx # imm = 0x1000
movq %r14, %rdx
movq %r15, %rsi
.LBB9_67: # %.preheader.i144
# =>This Loop Header: Depth=1
# Child Loop BB9_69 Depth 2
xorl %r8d, %r8d
.LBB9_69: # Parent Loop BB9_67 Depth=1
# => This Inner Loop Header: Depth=2
movss (%rdx,%r8,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
ucomiss (%rsi,%r8,4), %xmm1
jne .LBB9_71
jp .LBB9_71
# %bb.68: # in Loop: Header=BB9_69 Depth=2
incq %r8
cmpq $1024, %r8 # imm = 0x400
jne .LBB9_69
# %bb.70: # in Loop: Header=BB9_67 Depth=1
cmpq $1023, %rdi # imm = 0x3FF
leaq 1(%rdi), %r8
setb %al
addq %rcx, %rsi
addq %rcx, %rdx
movq %r8, %rdi
cmpq $1024, %r8 # imm = 0x400
jne .LBB9_67
.LBB9_71: # %_Z16compare_matricesPfS_.exit152
movl $.L.str.1, %ecx
movl $.L.str.2, %esi
testb $1, %al
cmovneq %rcx, %rsi
movl $.L.str.6, %edi
movb $1, %al
callq printf
movq 8(%rsp), %rdi
.Ltmp73:
xorl %esi, %esi
callq hipEventRecord
.Ltmp74:
# %bb.72: # %_ZN8GpuTimer5StartEv.exit154
.Ltmp75:
movabsq $274877907008, %rdi # imm = 0x4000000040
movabsq $68719476752, %rdx # imm = 0x1000000010
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
.Ltmp76:
# %bb.73:
testl %eax, %eax
jne .LBB9_75
# %bb.74:
movq 32(%rsp), %rdi
movq 24(%rsp), %rsi
.Ltmp77:
callq _Z60__device_stub__transpose_parallel_per_element_tiled_padded16PfS_
.Ltmp78:
.LBB9_75:
movq 16(%rsp), %rdi
.Ltmp79:
xorl %esi, %esi
callq hipEventRecord
.Ltmp80:
# %bb.76: # %_ZN8GpuTimer4StopEv.exit156
movq 24(%rsp), %rsi
.Ltmp81:
movl $4194304, %edx # imm = 0x400000
movq %r14, %rdi
movl $2, %ecx
callq hipMemcpy
.Ltmp82:
# %bb.77:
movq 16(%rsp), %rdi
.Ltmp83:
callq hipEventSynchronize
.Ltmp84:
# %bb.78: # %.noexc157
movq 8(%rsp), %rsi
movq 16(%rsp), %rdx
.Ltmp85:
leaq 4(%rsp), %rdi
callq hipEventElapsedTime
.Ltmp86:
# %bb.79:
xorps %xmm0, %xmm0
cvtss2sd 4(%rsp), %xmm0
movb $1, %al
xorl %edi, %edi
movl $4096, %ecx # imm = 0x1000
movq %r14, %rdx
movq %r15, %rsi
.LBB9_80: # %.preheader.i160
# =>This Loop Header: Depth=1
# Child Loop BB9_82 Depth 2
xorl %r8d, %r8d
.LBB9_82: # Parent Loop BB9_80 Depth=1
# => This Inner Loop Header: Depth=2
movss (%rdx,%r8,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
ucomiss (%rsi,%r8,4), %xmm1
jne .LBB9_84
jp .LBB9_84
# %bb.81: # in Loop: Header=BB9_82 Depth=2
incq %r8
cmpq $1024, %r8 # imm = 0x400
jne .LBB9_82
# %bb.83: # in Loop: Header=BB9_80 Depth=1
cmpq $1023, %rdi # imm = 0x3FF
leaq 1(%rdi), %r8
setb %al
addq %rcx, %rsi
addq %rcx, %rdx
movq %r8, %rdi
cmpq $1024, %r8 # imm = 0x400
jne .LBB9_80
.LBB9_84: # %_Z16compare_matricesPfS_.exit168
movl $.L.str.1, %ecx
movl $.L.str.2, %esi
testb $1, %al
cmovneq %rcx, %rsi
movl $.L.str.7, %edi
movb $1, %al
callq printf
movq 32(%rsp), %rdi
.Ltmp87:
callq hipFree
.Ltmp88:
# %bb.85:
movq 24(%rsp), %rdi
.Ltmp89:
callq hipFree
.Ltmp90:
# %bb.86:
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
leaq 8(%rsp), %rdi
callq _ZN8GpuTimerD2Ev
xorl %eax, %eax
addq $40, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB9_90:
.cfi_def_cfa_offset 80
.Ltmp58:
jmp .LBB9_88
.LBB9_89:
.Ltmp43:
jmp .LBB9_88
.LBB9_87:
.Ltmp28:
jmp .LBB9_88
.LBB9_91:
.Ltmp91:
.LBB9_88:
movq %rax, %rbx
leaq 8(%rsp), %rdi
callq _ZN8GpuTimerD2Ev
movq %rbx, %rdi
callq _Unwind_Resume@PLT
.Lfunc_end9:
.size main, .Lfunc_end9-main
.cfi_endproc
.section .gcc_except_table,"a",@progbits
.p2align 2, 0x0
GCC_except_table9:
.Lexception0:
.byte 255 # @LPStart Encoding = omit
.byte 255 # @TType Encoding = omit
.byte 1 # Call site Encoding = uleb128
.uleb128 .Lcst_end0-.Lcst_begin0
.Lcst_begin0:
.uleb128 .Lfunc_begin0-.Lfunc_begin0 # >> Call Site 1 <<
.uleb128 .Ltmp0-.Lfunc_begin0 # Call between .Lfunc_begin0 and .Ltmp0
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp0-.Lfunc_begin0 # >> Call Site 2 <<
.uleb128 .Ltmp27-.Ltmp0 # Call between .Ltmp0 and .Ltmp27
.uleb128 .Ltmp28-.Lfunc_begin0 # jumps to .Ltmp28
.byte 0 # On action: cleanup
.uleb128 .Ltmp29-.Lfunc_begin0 # >> Call Site 3 <<
.uleb128 .Ltmp42-.Ltmp29 # Call between .Ltmp29 and .Ltmp42
.uleb128 .Ltmp43-.Lfunc_begin0 # jumps to .Ltmp43
.byte 0 # On action: cleanup
.uleb128 .Ltmp44-.Lfunc_begin0 # >> Call Site 4 <<
.uleb128 .Ltmp57-.Ltmp44 # Call between .Ltmp44 and .Ltmp57
.uleb128 .Ltmp58-.Lfunc_begin0 # jumps to .Ltmp58
.byte 0 # On action: cleanup
.uleb128 .Ltmp59-.Lfunc_begin0 # >> Call Site 5 <<
.uleb128 .Ltmp90-.Ltmp59 # Call between .Ltmp59 and .Ltmp90
.uleb128 .Ltmp91-.Lfunc_begin0 # jumps to .Ltmp91
.byte 0 # On action: cleanup
.uleb128 .Ltmp90-.Lfunc_begin0 # >> Call Site 6 <<
.uleb128 .Lfunc_end9-.Ltmp90 # Call between .Ltmp90 and .Lfunc_end9
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.Lcst_end0:
.p2align 2, 0x0
# -- End function
.section .text._ZN8GpuTimerD2Ev,"axG",@progbits,_ZN8GpuTimerD2Ev,comdat
.weak _ZN8GpuTimerD2Ev # -- Begin function _ZN8GpuTimerD2Ev
.p2align 1, 0x90
.type _ZN8GpuTimerD2Ev,@function
_ZN8GpuTimerD2Ev: # @_ZN8GpuTimerD2Ev
.Lfunc_begin1:
.cfi_startproc
.cfi_personality 3, __gxx_personality_v0
.cfi_lsda 3, .Lexception1
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
movq %rdi, %rbx
movq (%rdi), %rdi
.Ltmp92:
callq hipEventDestroy
.Ltmp93:
# %bb.1:
movq 8(%rbx), %rdi
.Ltmp94:
callq hipEventDestroy
.Ltmp95:
# %bb.2:
popq %rbx
.cfi_def_cfa_offset 8
retq
.LBB10_3:
.cfi_def_cfa_offset 16
.Ltmp96:
movq %rax, %rdi
callq __clang_call_terminate
.Lfunc_end10:
.size _ZN8GpuTimerD2Ev, .Lfunc_end10-_ZN8GpuTimerD2Ev
.cfi_endproc
.section .gcc_except_table._ZN8GpuTimerD2Ev,"aG",@progbits,_ZN8GpuTimerD2Ev,comdat
.p2align 2, 0x0
GCC_except_table10:
.Lexception1:
.byte 255 # @LPStart Encoding = omit
.byte 3 # @TType Encoding = udata4
.uleb128 .Lttbase0-.Lttbaseref0
.Lttbaseref0:
.byte 1 # Call site Encoding = uleb128
.uleb128 .Lcst_end1-.Lcst_begin1
.Lcst_begin1:
.uleb128 .Ltmp92-.Lfunc_begin1 # >> Call Site 1 <<
.uleb128 .Ltmp95-.Ltmp92 # Call between .Ltmp92 and .Ltmp95
.uleb128 .Ltmp96-.Lfunc_begin1 # jumps to .Ltmp96
.byte 1 # On action: 1
.Lcst_end1:
.byte 1 # >> Action Record 1 <<
# Catch TypeInfo 1
.byte 0 # No further actions
.p2align 2, 0x0
# >> Catch TypeInfos <<
.long 0 # TypeInfo 1
.Lttbase0:
.p2align 2, 0x0
# -- End function
.section .text.__clang_call_terminate,"axG",@progbits,__clang_call_terminate,comdat
.hidden __clang_call_terminate # -- Begin function __clang_call_terminate
.weak __clang_call_terminate
.type __clang_call_terminate,@function
__clang_call_terminate: # @__clang_call_terminate
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
callq __cxa_begin_catch
callq _ZSt9terminatev
.Lfunc_end11:
.size __clang_call_terminate, .Lfunc_end11-__clang_call_terminate
.cfi_endproc
# -- End function
.text
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
movq __hip_gpubin_handle(%rip), %rbx
testq %rbx, %rbx
jne .LBB12_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, %rbx
movq %rax, __hip_gpubin_handle(%rip)
.LBB12_2:
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z16transpose_serialPfS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z26transpose_parallel_per_rowPfS_, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z30transpose_parallel_per_elementPfS_, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z36transpose_parallel_per_element_tiledPfS_, %esi
movl $.L__unnamed_4, %edx
movl $.L__unnamed_4, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z38transpose_parallel_per_element_tiled16PfS_, %esi
movl $.L__unnamed_5, %edx
movl $.L__unnamed_5, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z45transpose_parallel_per_element_tiled_padded16PfS_, %esi
movl $.L__unnamed_6, %edx
movl $.L__unnamed_6, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end12:
.size __hip_module_ctor, .Lfunc_end12-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB13_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB13_2:
retq
.Lfunc_end13:
.size __hip_module_dtor, .Lfunc_end13-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z16transpose_serialPfS_,@object # @_Z16transpose_serialPfS_
.section .rodata,"a",@progbits
.globl _Z16transpose_serialPfS_
.p2align 3, 0x0
_Z16transpose_serialPfS_:
.quad _Z31__device_stub__transpose_serialPfS_
.size _Z16transpose_serialPfS_, 8
.type _Z26transpose_parallel_per_rowPfS_,@object # @_Z26transpose_parallel_per_rowPfS_
.globl _Z26transpose_parallel_per_rowPfS_
.p2align 3, 0x0
_Z26transpose_parallel_per_rowPfS_:
.quad _Z41__device_stub__transpose_parallel_per_rowPfS_
.size _Z26transpose_parallel_per_rowPfS_, 8
.type _Z30transpose_parallel_per_elementPfS_,@object # @_Z30transpose_parallel_per_elementPfS_
.globl _Z30transpose_parallel_per_elementPfS_
.p2align 3, 0x0
_Z30transpose_parallel_per_elementPfS_:
.quad _Z45__device_stub__transpose_parallel_per_elementPfS_
.size _Z30transpose_parallel_per_elementPfS_, 8
.type _Z36transpose_parallel_per_element_tiledPfS_,@object # @_Z36transpose_parallel_per_element_tiledPfS_
.globl _Z36transpose_parallel_per_element_tiledPfS_
.p2align 3, 0x0
_Z36transpose_parallel_per_element_tiledPfS_:
.quad _Z51__device_stub__transpose_parallel_per_element_tiledPfS_
.size _Z36transpose_parallel_per_element_tiledPfS_, 8
.type _Z38transpose_parallel_per_element_tiled16PfS_,@object # @_Z38transpose_parallel_per_element_tiled16PfS_
.globl _Z38transpose_parallel_per_element_tiled16PfS_
.p2align 3, 0x0
_Z38transpose_parallel_per_element_tiled16PfS_:
.quad _Z53__device_stub__transpose_parallel_per_element_tiled16PfS_
.size _Z38transpose_parallel_per_element_tiled16PfS_, 8
.type _Z45transpose_parallel_per_element_tiled_padded16PfS_,@object # @_Z45transpose_parallel_per_element_tiled_padded16PfS_
.globl _Z45transpose_parallel_per_element_tiled_padded16PfS_
.p2align 3, 0x0
_Z45transpose_parallel_per_element_tiled_padded16PfS_:
.quad _Z60__device_stub__transpose_parallel_per_element_tiled_padded16PfS_
.size _Z45transpose_parallel_per_element_tiled_padded16PfS_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "transpose_serial: %g ms.\nVerifying transpose...%s\n"
.size .L.str, 51
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Failed"
.size .L.str.1, 7
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Success"
.size .L.str.2, 8
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "transpose_parallel_per_row: %g ms.\nVerifying transpose...%s\n"
.size .L.str.3, 61
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "transpose_parallel_per_element: %g ms.\nVerifying transpose...%s\n"
.size .L.str.4, 65
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "transpose_parallel_per_element_tiled %dx%d: %g ms.\nVerifying ...%s\n"
.size .L.str.5, 68
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "transpose_parallel_per_element_tiled 16x16: %g ms.\nVerifying ...%s\n"
.size .L.str.6, 68
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "transpose_parallel_per_element_tiled_padded 16x16: %g ms.\nVerifying...%s\n"
.size .L.str.7, 74
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z16transpose_serialPfS_"
.size .L__unnamed_1, 25
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z26transpose_parallel_per_rowPfS_"
.size .L__unnamed_2, 35
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z30transpose_parallel_per_elementPfS_"
.size .L__unnamed_3, 39
.type .L__unnamed_4,@object # @3
.L__unnamed_4:
.asciz "_Z36transpose_parallel_per_element_tiledPfS_"
.size .L__unnamed_4, 45
.type .L__unnamed_5,@object # @4
.L__unnamed_5:
.asciz "_Z38transpose_parallel_per_element_tiled16PfS_"
.size .L__unnamed_5, 47
.type .L__unnamed_6,@object # @5
.L__unnamed_6:
.asciz "_Z45transpose_parallel_per_element_tiled_padded16PfS_"
.size .L__unnamed_6, 54
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z31__device_stub__transpose_serialPfS_
.addrsig_sym _Z41__device_stub__transpose_parallel_per_rowPfS_
.addrsig_sym _Z45__device_stub__transpose_parallel_per_elementPfS_
.addrsig_sym _Z51__device_stub__transpose_parallel_per_element_tiledPfS_
.addrsig_sym _Z53__device_stub__transpose_parallel_per_element_tiled16PfS_
.addrsig_sym _Z60__device_stub__transpose_parallel_per_element_tiled_padded16PfS_
.addrsig_sym __gxx_personality_v0
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Unwind_Resume
.addrsig_sym _Z16transpose_serialPfS_
.addrsig_sym _Z26transpose_parallel_per_rowPfS_
.addrsig_sym _Z30transpose_parallel_per_elementPfS_
.addrsig_sym _Z36transpose_parallel_per_element_tiledPfS_
.addrsig_sym _Z38transpose_parallel_per_element_tiled16PfS_
.addrsig_sym _Z45transpose_parallel_per_element_tiled_padded16PfS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
```
| 13,016 | 18,868 |
316 |
Convert the following CUDA device assembly code to AMD device assembly:
```cudaasm
code for sm_80
Function : _Z4kaddPfS_S_j
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
MOV R1, c[0x0][0x28] ;
S2R R2, SR_CTAID.X ;
ISETP.NE.AND P0, PT, RZ, c[0x0][0x178], PT ;
S2R R3, SR_TID.X ;
@!P0 EXIT ;
MOV R7, c[0x0][0x178] ;
ULDC.64 UR4, c[0x0][0x118] ;
HFMA2.MMA R5, -RZ, RZ, 0, 0 ;
IMAD R2, R2, c[0x0][0x0], R3 ;
IADD3 R4, R7, -0x1, RZ ;
LOP3.LUT R0, R7, 0x3, RZ, 0xc0, !PT ;
ISETP.GE.U32.AND P1, PT, R4, 0x3, PT ;
ISETP.NE.AND P0, PT, R0, RZ, PT ;
@!P1 BRA 0x360 ;
IMAD R3, R2, R7, 0x3 ;
IADD3 R4, R0, -c[0x0][0x178], RZ ;
MOV R5, RZ ;
IADD3 R13, R3, -0x3, RZ ;
MOV R6, 0x4 ;
IMAD.WIDE.U32 R10, R13, R6, c[0x0][0x168] ;
IMAD.WIDE.U32 R8, R13, R6.reuse, c[0x0][0x160] ;
LDG.E R10, [R10.64] ;
LDG.E R9, [R8.64] ;
IADD3 R19, R3, -0x2, RZ ;
IMAD.WIDE.U32 R12, R13, R6, c[0x0][0x170] ;
IMAD.WIDE.U32 R16, R19, R6, c[0x0][0x168] ;
IMAD.WIDE.U32 R14, R19, R6, c[0x0][0x160] ;
FADD R7, R10, R9 ;
STG.E [R12.64], R7 ;
LDG.E R16, [R16.64] ;
LDG.E R15, [R14.64] ;
IADD3 R23, R3, -0x1, RZ ;
IMAD.WIDE.U32 R10, R19, R6, c[0x0][0x170] ;
IMAD.WIDE.U32 R18, R23, R6, c[0x0][0x168] ;
IMAD.WIDE.U32 R8, R23, R6, c[0x0][0x160] ;
FADD R21, R16, R15 ;
STG.E [R10.64], R21 ;
LDG.E R18, [R18.64] ;
LDG.E R9, [R8.64] ;
IMAD.WIDE.U32 R12, R23, R6, c[0x0][0x170] ;
IMAD.WIDE.U32 R14, R3, R6, c[0x0][0x160] ;
IMAD.WIDE.U32 R16, R3, R6, c[0x0][0x168] ;
FADD R23, R18, R9 ;
STG.E [R12.64], R23 ;
LDG.E R15, [R14.64] ;
LDG.E R16, [R16.64] ;
IADD3 R5, R5, 0x4, RZ ;
IMAD.WIDE.U32 R6, R3.reuse, R6, c[0x0][0x170] ;
IADD3 R3, R3, 0x4, RZ ;
IADD3 R8, R4, R5, RZ ;
ISETP.NE.AND P1, PT, R8, RZ, PT ;
FADD R11, R16, R15 ;
STG.E [R6.64], R11 ;
@P1 BRA 0x110 ;
@!P0 EXIT ;
IMAD R8, R2, c[0x0][0x178], R5 ;
HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ;
IMAD.WIDE.U32 R2, R8, R7, c[0x0][0x160] ;
IMAD.WIDE.U32 R4, R8, R7.reuse, c[0x0][0x168] ;
LDG.E R3, [R2.64] ;
LDG.E R4, [R4.64] ;
IADD3 R0, R0, -0x1, RZ ;
IMAD.WIDE.U32 R6, R8.reuse, R7, c[0x0][0x170] ;
IADD3 R8, R8, 0x1, RZ ;
ISETP.NE.AND P0, PT, R0, RZ, PT ;
FADD R9, R4, R3 ;
STG.E [R6.64], R9 ;
@P0 BRA 0x380 ;
EXIT ;
BRA 0x450;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
```
|
```amdasm
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object ; @__hip_cuid_
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0 ; 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
```
| 1,426 | 306 |
317 |
Convert the following CUDA host assembly code to AMD host assembly:
```cudaasm
.file "tmpxft_000eda5d_00000000-6_kernel.cudafe1.cpp"
.text
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2059:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2059:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z28__device_stub__Z4kaddPfS_S_jPfS_S_j
.type _Z28__device_stub__Z4kaddPfS_S_jPfS_S_j, @function
_Z28__device_stub__Z4kaddPfS_S_jPfS_S_j:
.LFB2081:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z4kaddPfS_S_j(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2081:
.size _Z28__device_stub__Z4kaddPfS_S_jPfS_S_j, .-_Z28__device_stub__Z4kaddPfS_S_jPfS_S_j
.globl _Z4kaddPfS_S_j
.type _Z4kaddPfS_S_j, @function
_Z4kaddPfS_S_j:
.LFB2082:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z28__device_stub__Z4kaddPfS_S_jPfS_S_j
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2082:
.size _Z4kaddPfS_S_j, .-_Z4kaddPfS_S_j
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z4kaddPfS_S_j"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z4kaddPfS_S_j(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
```
|
```amdasm
.text
.file "kernel.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
```
| 1,887 | 183 |
324 |
Convert the following CUDA device assembly code to AMD device assembly:
```cudaasm
code for sm_80
Function : _Z11sumaenlagpuPiS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
MOV R1, c[0x0][0x28] ;
S2R R6, SR_TID.X ;
S2R R3, SR_CTAID.X ;
IMAD R6, R3, c[0x0][0x0], R6 ;
ISETP.GE.AND P0, PT, R6, c[0x0][0x178], PT ;
@P0 EXIT ;
HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ;
ULDC.64 UR4, c[0x0][0x118] ;
IMAD.WIDE R4, R6, R7, c[0x0][0x168] ;
IMAD.WIDE R2, R6.reuse, R7.reuse, c[0x0][0x160] ;
LDG.E R4, [R4.64] ;
LDG.E R3, [R2.64] ;
IMAD.WIDE R6, R6, R7, c[0x0][0x170] ;
IADD3 R9, R4, R3, RZ ;
STG.E [R6.64], R9 ;
EXIT ;
BRA 0x100;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
```
|
```amdasm
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z11sumaenlagpuPiS_S_i ; -- Begin function _Z11sumaenlagpuPiS_S_i
.globl _Z11sumaenlagpuPiS_S_i
.p2align 8
.type _Z11sumaenlagpuPiS_S_i,@function
_Z11sumaenlagpuPiS_S_i: ; @_Z11sumaenlagpuPiS_S_i
; %bb.0:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
; %bb.1:
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v2, v3, v2
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11sumaenlagpuPiS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z11sumaenlagpuPiS_S_i, .Lfunc_end0-_Z11sumaenlagpuPiS_S_i
; -- End function
.section .AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 180
; NumSgprs: 18
; NumVgprs: 6
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 6
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object ; @__hip_cuid_
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0 ; 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11sumaenlagpuPiS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z11sumaenlagpuPiS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
```
| 407 | 2,603 |
325 |
Convert the following CUDA host assembly code to AMD host assembly:
```cudaasm
.file "tmpxft_001a7056_00000000-6_sumaenlagpu.cudafe1.cpp"
.text
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z36__device_stub__Z11sumaenlagpuPiS_S_iPiS_S_i
.type _Z36__device_stub__Z11sumaenlagpuPiS_S_iPiS_S_i, @function
_Z36__device_stub__Z11sumaenlagpuPiS_S_iPiS_S_i:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z11sumaenlagpuPiS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z36__device_stub__Z11sumaenlagpuPiS_S_iPiS_S_i, .-_Z36__device_stub__Z11sumaenlagpuPiS_S_iPiS_S_i
.globl _Z11sumaenlagpuPiS_S_i
.type _Z11sumaenlagpuPiS_S_i, @function
_Z11sumaenlagpuPiS_S_i:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z36__device_stub__Z11sumaenlagpuPiS_S_iPiS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z11sumaenlagpuPiS_S_i, .-_Z11sumaenlagpuPiS_S_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z11sumaenlagpuPiS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z11sumaenlagpuPiS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
```
|
```amdasm
.text
.file "sumaenlagpu.hip"
.globl _Z26__device_stub__sumaenlagpuPiS_S_i # -- Begin function _Z26__device_stub__sumaenlagpuPiS_S_i
.type _Z26__device_stub__sumaenlagpuPiS_S_i,@function
_Z26__device_stub__sumaenlagpuPiS_S_i: # @_Z26__device_stub__sumaenlagpuPiS_S_i
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $112, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 40(%rsp), %rax
movq %rdi, (%rax)
leaq 32(%rsp), %rdi
movq %rsi, (%rdi)
leaq 24(%rsp), %rsi
movq %rdx, (%rsi)
leaq 4(%rsp), %rdx
movl %ecx, (%rdx)
leaq 80(%rsp), %rbx
movq %rax, (%rbx)
movq %rdi, 8(%rbx)
movq %rsi, 16(%rbx)
movq %rdx, 24(%rbx)
leaq 64(%rsp), %r14
leaq 48(%rsp), %r15
leaq 16(%rsp), %r12
leaq 8(%rsp), %r13
movq %r14, %rdi
movq %r15, %rsi
movq %r12, %rdx
movq %r13, %rcx
callq __hipPopCallConfiguration
movq (%r14), %rsi
movl 8(%r14), %edx
movq (%r15), %rcx
movl 8(%r15), %r8d
movl $_Z11sumaenlagpuPiS_S_i, %edi
movq %rbx, %r9
pushq (%r13)
.cfi_adjust_cfa_offset 8
pushq (%r12)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $128, %rsp
.cfi_adjust_cfa_offset -128
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z26__device_stub__sumaenlagpuPiS_S_i, .Lfunc_end0-_Z26__device_stub__sumaenlagpuPiS_S_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, %rdi
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11sumaenlagpuPiS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z11sumaenlagpuPiS_S_i,@object # @_Z11sumaenlagpuPiS_S_i
.section .rodata,"a",@progbits
.globl _Z11sumaenlagpuPiS_S_i
.p2align 3, 0x0
_Z11sumaenlagpuPiS_S_i:
.quad _Z26__device_stub__sumaenlagpuPiS_S_i
.size _Z11sumaenlagpuPiS_S_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z11sumaenlagpuPiS_S_i"
.size .L__unnamed_1, 23
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z26__device_stub__sumaenlagpuPiS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z11sumaenlagpuPiS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
```
| 1,915 | 2,103 |
326 |
Convert the following CUDA device assembly code to AMD device assembly:
```cudaasm
code for sm_80
Function : _Z3dotPiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ;
S2R R2, SR_CTAID.X ;
IMAD.MOV.U32 R3, RZ, RZ, 0x4 ;
ULDC.64 UR4, c[0x0][0x118] ;
S2R R7, SR_TID.X ;
IMAD R2, R2, c[0x0][0x0], R7 ;
IMAD.WIDE R4, R2, R3, c[0x0][0x168] ;
IMAD.WIDE R2, R2, R3, c[0x0][0x160] ;
LDG.E R4, [R4.64] ;
LDG.E R3, [R2.64] ;
ISETP.NE.AND P0, PT, R7, RZ, PT ;
IMAD R0, R4, R3, RZ ;
STS [R7.X4], R0 ;
BAR.SYNC.DEFER_BLOCKING 0x0 ;
@P0 EXIT ;
LDS.128 R8, [RZ] ;
IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x170] ;
IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x174] ;
LDS.128 R24, [0x10] ;
LDS.128 R4, [0x20] ;
LDS.128 R20, [0x30] ;
LDS.128 R16, [0x40] ;
LDS.128 R12, [0x50] ;
IADD3 R8, R10, R9, R8 ;
IADD3 R24, R24, R11, R8 ;
LDS.128 R8, [0x60] ;
IADD3 R24, R26, R25, R24 ;
IADD3 R4, R4, R27, R24 ;
LDS.128 R24, [0x70] ;
IADD3 R4, R6, R5, R4 ;
IADD3 R20, R20, R7, R4 ;
LDS.128 R4, [0x80] ;
IADD3 R20, R22, R21, R20 ;
IADD3 R16, R16, R23, R20 ;
LDS.128 R20, [0x90] ;
IADD3 R16, R18, R17, R16 ;
IADD3 R12, R12, R19, R16 ;
LDS.128 R16, [0xa0] ;
IADD3 R12, R14, R13, R12 ;
IADD3 R8, R8, R15, R12 ;
LDS.128 R12, [0xb0] ;
IADD3 R8, R10, R9, R8 ;
IADD3 R24, R24, R11, R8 ;
LDS.128 R8, [0xc0] ;
IADD3 R24, R26, R25, R24 ;
IADD3 R4, R4, R27, R24 ;
LDS.128 R24, [0xd0] ;
IADD3 R4, R6, R5, R4 ;
IADD3 R20, R20, R7, R4 ;
LDS.128 R4, [0xe0] ;
IADD3 R20, R22, R21, R20 ;
IADD3 R16, R16, R23, R20 ;
LDS.128 R20, [0xf0] ;
IADD3 R16, R18, R17, R16 ;
IADD3 R12, R12, R19, R16 ;
LDS.128 R16, [0x100] ;
IADD3 R12, R14, R13, R12 ;
IADD3 R8, R8, R15, R12 ;
LDS.128 R12, [0x110] ;
IADD3 R8, R10, R9, R8 ;
IADD3 R24, R24, R11, R8 ;
LDS.128 R8, [0x120] ;
IADD3 R24, R26, R25, R24 ;
IADD3 R4, R4, R27, R24 ;
LDS.128 R24, [0x130] ;
IADD3 R4, R6, R5, R4 ;
IADD3 R20, R20, R7, R4 ;
LDS.128 R4, [0x140] ;
IADD3 R20, R22, R21, R20 ;
IADD3 R16, R16, R23, R20 ;
LDS.128 R20, [0x150] ;
IADD3 R16, R18, R17, R16 ;
IADD3 R12, R12, R19, R16 ;
LDS.128 R16, [0x160] ;
IADD3 R12, R14, R13, R12 ;
IADD3 R8, R8, R15, R12 ;
LDS.128 R12, [0x170] ;
IADD3 R8, R10, R9, R8 ;
IADD3 R24, R24, R11, R8 ;
LDS.128 R8, [0x180] ;
IADD3 R24, R26, R25, R24 ;
IADD3 R4, R4, R27, R24 ;
LDS.128 R24, [0x190] ;
IADD3 R4, R6, R5, R4 ;
IADD3 R20, R20, R7, R4 ;
LDS.128 R4, [0x1a0] ;
IADD3 R20, R22, R21, R20 ;
IADD3 R16, R16, R23, R20 ;
LDS.128 R20, [0x1b0] ;
IADD3 R16, R18, R17, R16 ;
IADD3 R12, R12, R19, R16 ;
LDS.128 R16, [0x1c0] ;
IADD3 R12, R14, R13, R12 ;
IADD3 R8, R8, R15, R12 ;
LDS.128 R12, [0x1d0] ;
IADD3 R8, R10, R9, R8 ;
IADD3 R24, R24, R11, R8 ;
LDS.128 R8, [0x1e0] ;
IADD3 R24, R26, R25, R24 ;
IADD3 R4, R4, R27, R24 ;
LDS.128 R24, [0x1f0] ;
IADD3 R4, R6, R5, R4 ;
IADD3 R20, R20, R7, R4 ;
LDS.128 R4, [0x200] ;
IADD3 R20, R22, R21, R20 ;
IADD3 R16, R16, R23, R20 ;
LDS.128 R20, [0x210] ;
IADD3 R16, R18, R17, R16 ;
IADD3 R12, R12, R19, R16 ;
LDS.128 R16, [0x220] ;
IADD3 R12, R14, R13, R12 ;
IADD3 R8, R8, R15, R12 ;
LDS.128 R12, [0x230] ;
IADD3 R8, R10, R9, R8 ;
IADD3 R24, R24, R11, R8 ;
LDS.128 R8, [0x240] ;
IADD3 R24, R26, R25, R24 ;
IADD3 R4, R4, R27, R24 ;
LDS.128 R24, [0x250] ;
IADD3 R4, R6, R5, R4 ;
IADD3 R20, R20, R7, R4 ;
LDS.128 R4, [0x260] ;
IADD3 R20, R22, R21, R20 ;
IADD3 R16, R16, R23, R20 ;
LDS.128 R20, [0x270] ;
IADD3 R16, R18, R17, R16 ;
IADD3 R12, R12, R19, R16 ;
LDS.128 R16, [0x280] ;
IADD3 R12, R14, R13, R12 ;
IADD3 R8, R8, R15, R12 ;
LDS.128 R12, [0x290] ;
IADD3 R8, R10, R9, R8 ;
IADD3 R24, R24, R11, R8 ;
LDS.128 R8, [0x2a0] ;
IADD3 R24, R26, R25, R24 ;
IADD3 R4, R4, R27, R24 ;
LDS.128 R24, [0x2b0] ;
IADD3 R4, R6, R5, R4 ;
IADD3 R20, R20, R7, R4 ;
LDS.128 R4, [0x2c0] ;
IADD3 R20, R22, R21, R20 ;
IADD3 R16, R16, R23, R20 ;
LDS.128 R20, [0x2d0] ;
IADD3 R16, R18, R17, R16 ;
IADD3 R12, R12, R19, R16 ;
LDS.128 R16, [0x2e0] ;
IADD3 R12, R14, R13, R12 ;
IADD3 R8, R8, R15, R12 ;
LDS.128 R12, [0x2f0] ;
IADD3 R8, R10, R9, R8 ;
IADD3 R24, R24, R11, R8 ;
LDS.128 R8, [0x300] ;
IADD3 R24, R26, R25, R24 ;
IADD3 R4, R4, R27, R24 ;
LDS.128 R24, [0x310] ;
IADD3 R4, R6, R5, R4 ;
IADD3 R20, R20, R7, R4 ;
LDS.128 R4, [0x320] ;
IADD3 R20, R22, R21, R20 ;
IADD3 R16, R16, R23, R20 ;
LDS.128 R20, [0x330] ;
IADD3 R16, R18, R17, R16 ;
IADD3 R12, R12, R19, R16 ;
LDS.128 R16, [0x340] ;
IADD3 R12, R14, R13, R12 ;
IADD3 R8, R8, R15, R12 ;
LDS.128 R12, [0x350] ;
IADD3 R8, R10, R9, R8 ;
IADD3 R24, R24, R11, R8 ;
LDS.128 R8, [0x360] ;
IADD3 R24, R26, R25, R24 ;
IADD3 R4, R4, R27, R24 ;
LDS.128 R24, [0x370] ;
IADD3 R4, R6, R5, R4 ;
IADD3 R20, R20, R7, R4 ;
LDS.128 R4, [0x380] ;
IADD3 R20, R22, R21, R20 ;
IADD3 R16, R16, R23, R20 ;
LDS.128 R20, [0x390] ;
IADD3 R16, R18, R17, R16 ;
IADD3 R12, R12, R19, R16 ;
LDS.128 R16, [0x3a0] ;
IADD3 R12, R14, R13, R12 ;
IADD3 R8, R8, R15, R12 ;
LDS.128 R12, [0x3b0] ;
IADD3 R8, R10, R9, R8 ;
IADD3 R24, R24, R11, R8 ;
LDS.128 R8, [0x3c0] ;
IADD3 R24, R26, R25, R24 ;
IADD3 R4, R4, R27, R24 ;
LDS.128 R24, [0x3d0] ;
IADD3 R4, R6, R5, R4 ;
IADD3 R20, R20, R7, R4 ;
LDS.128 R4, [0x3e0] ;
IADD3 R20, R22, R21, R20 ;
IADD3 R16, R16, R23, R20 ;
LDS.128 R20, [0x3f0] ;
IADD3 R16, R18, R17, R16 ;
IADD3 R12, R12, R19, R16 ;
LDS.128 R16, [0x400] ;
IADD3 R12, R14, R13, R12 ;
IADD3 R8, R8, R15, R12 ;
LDS.128 R12, [0x410] ;
IADD3 R8, R10, R9, R8 ;
IADD3 R24, R24, R11, R8 ;
LDS.128 R8, [0x420] ;
IADD3 R24, R26, R25, R24 ;
IADD3 R4, R4, R27, R24 ;
LDS.128 R24, [0x430] ;
IADD3 R4, R6, R5, R4 ;
IADD3 R20, R20, R7, R4 ;
LDS.128 R4, [0x440] ;
IADD3 R20, R22, R21, R20 ;
IADD3 R16, R16, R23, R20 ;
LDS.128 R20, [0x450] ;
IADD3 R16, R18, R17, R16 ;
IADD3 R12, R12, R19, R16 ;
LDS.128 R16, [0x460] ;
IADD3 R12, R14, R13, R12 ;
IADD3 R8, R8, R15, R12 ;
LDS.128 R12, [0x470] ;
IADD3 R8, R10, R9, R8 ;
IADD3 R24, R24, R11, R8 ;
LDS.128 R8, [0x480] ;
IADD3 R24, R26, R25, R24 ;
IADD3 R4, R4, R27, R24 ;
LDS.128 R24, [0x490] ;
IADD3 R4, R6, R5, R4 ;
IADD3 R20, R20, R7, R4 ;
LDS.128 R4, [0x4a0] ;
IADD3 R20, R22, R21, R20 ;
IADD3 R16, R16, R23, R20 ;
LDS.128 R20, [0x4b0] ;
IADD3 R16, R18, R17, R16 ;
IADD3 R12, R12, R19, R16 ;
LDS.128 R16, [0x4c0] ;
IADD3 R12, R14, R13, R12 ;
IADD3 R8, R8, R15, R12 ;
LDS.128 R12, [0x4d0] ;
IADD3 R8, R10, R9, R8 ;
IADD3 R24, R24, R11, R8 ;
LDS.128 R8, [0x4e0] ;
IADD3 R24, R26, R25, R24 ;
IADD3 R4, R4, R27, R24 ;
LDS.128 R24, [0x4f0] ;
IADD3 R4, R6, R5, R4 ;
IADD3 R20, R20, R7, R4 ;
LDS.128 R4, [0x500] ;
IADD3 R20, R22, R21, R20 ;
IADD3 R16, R16, R23, R20 ;
LDS.128 R20, [0x510] ;
IADD3 R16, R18, R17, R16 ;
IADD3 R12, R12, R19, R16 ;
LDS.128 R16, [0x520] ;
IADD3 R12, R14, R13, R12 ;
IADD3 R8, R8, R15, R12 ;
LDS.128 R12, [0x530] ;
IADD3 R8, R10, R9, R8 ;
IADD3 R24, R24, R11, R8 ;
LDS.128 R8, [0x540] ;
IADD3 R24, R26, R25, R24 ;
IADD3 R4, R4, R27, R24 ;
LDS.128 R24, [0x550] ;
IADD3 R4, R6, R5, R4 ;
IADD3 R20, R20, R7, R4 ;
LDS.128 R4, [0x560] ;
IADD3 R20, R22, R21, R20 ;
IADD3 R16, R16, R23, R20 ;
LDS.128 R20, [0x570] ;
IADD3 R16, R18, R17, R16 ;
IADD3 R12, R12, R19, R16 ;
LDS.128 R16, [0x580] ;
IADD3 R12, R14, R13, R12 ;
IADD3 R8, R8, R15, R12 ;
LDS.128 R12, [0x590] ;
IADD3 R8, R10, R9, R8 ;
IADD3 R24, R24, R11, R8 ;
LDS.128 R8, [0x5a0] ;
IADD3 R24, R26, R25, R24 ;
IADD3 R4, R4, R27, R24 ;
LDS.128 R24, [0x5b0] ;
IADD3 R4, R6, R5, R4 ;
IADD3 R20, R20, R7, R4 ;
LDS.128 R4, [0x5c0] ;
IADD3 R20, R22, R21, R20 ;
IADD3 R16, R16, R23, R20 ;
LDS.128 R20, [0x5d0] ;
IADD3 R16, R18, R17, R16 ;
IADD3 R12, R12, R19, R16 ;
LDS.128 R16, [0x5e0] ;
IADD3 R12, R14, R13, R12 ;
IADD3 R8, R8, R15, R12 ;
LDS.128 R12, [0x5f0] ;
IADD3 R8, R10, R9, R8 ;
IADD3 R24, R24, R11, R8 ;
LDS.128 R8, [0x600] ;
IADD3 R24, R26, R25, R24 ;
IADD3 R4, R4, R27, R24 ;
LDS.128 R24, [0x610] ;
IADD3 R4, R6, R5, R4 ;
IADD3 R20, R20, R7, R4 ;
LDS.128 R4, [0x620] ;
IADD3 R20, R22, R21, R20 ;
IADD3 R16, R16, R23, R20 ;
LDS.128 R20, [0x630] ;
IADD3 R16, R18, R17, R16 ;
IADD3 R12, R12, R19, R16 ;
LDS.128 R16, [0x640] ;
IADD3 R12, R14, R13, R12 ;
IADD3 R8, R8, R15, R12 ;
LDS.128 R12, [0x650] ;
IADD3 R8, R10, R9, R8 ;
IADD3 R24, R24, R11, R8 ;
LDS.128 R8, [0x660] ;
IADD3 R24, R26, R25, R24 ;
IADD3 R4, R4, R27, R24 ;
LDS.128 R24, [0x670] ;
IADD3 R4, R6, R5, R4 ;
IADD3 R20, R20, R7, R4 ;
LDS.128 R4, [0x680] ;
IADD3 R20, R22, R21, R20 ;
IADD3 R16, R16, R23, R20 ;
LDS.128 R20, [0x690] ;
IADD3 R16, R18, R17, R16 ;
IADD3 R12, R12, R19, R16 ;
LDS.128 R16, [0x6a0] ;
IADD3 R12, R14, R13, R12 ;
IADD3 R8, R8, R15, R12 ;
LDS.128 R12, [0x6b0] ;
IADD3 R8, R10, R9, R8 ;
IADD3 R24, R24, R11, R8 ;
LDS.128 R8, [0x6c0] ;
IADD3 R24, R26, R25, R24 ;
IADD3 R4, R4, R27, R24 ;
LDS.128 R24, [0x6d0] ;
IADD3 R4, R6, R5, R4 ;
IADD3 R20, R20, R7, R4 ;
LDS.128 R4, [0x6e0] ;
IADD3 R20, R22, R21, R20 ;
IADD3 R16, R16, R23, R20 ;
LDS.128 R20, [0x6f0] ;
IADD3 R16, R18, R17, R16 ;
IADD3 R12, R12, R19, R16 ;
LDS.128 R16, [0x700] ;
IADD3 R12, R14, R13, R12 ;
IADD3 R8, R8, R15, R12 ;
LDS.128 R12, [0x710] ;
IADD3 R8, R10, R9, R8 ;
IADD3 R24, R24, R11, R8 ;
LDS.128 R8, [0x720] ;
IADD3 R24, R26, R25, R24 ;
IADD3 R4, R4, R27, R24 ;
LDS.128 R24, [0x730] ;
IADD3 R4, R6, R5, R4 ;
IADD3 R20, R20, R7, R4 ;
LDS.128 R4, [0x740] ;
IADD3 R20, R22, R21, R20 ;
IADD3 R16, R16, R23, R20 ;
LDS.128 R20, [0x750] ;
IADD3 R16, R18, R17, R16 ;
IADD3 R12, R12, R19, R16 ;
LDS.128 R16, [0x760] ;
IADD3 R12, R14, R13, R12 ;
IADD3 R8, R8, R15, R12 ;
LDS.128 R12, [0x770] ;
IADD3 R8, R10, R9, R8 ;
IADD3 R24, R24, R11, R8 ;
LDS.128 R8, [0x780] ;
IADD3 R24, R26, R25, R24 ;
IADD3 R4, R4, R27, R24 ;
LDS.128 R24, [0x790] ;
IADD3 R4, R6, R5, R4 ;
IADD3 R20, R20, R7, R4 ;
LDS.128 R4, [0x7a0] ;
IADD3 R20, R22, R21, R20 ;
IADD3 R16, R16, R23, R20 ;
LDS.128 R20, [0x7b0] ;
IADD3 R16, R18, R17, R16 ;
IADD3 R12, R12, R19, R16 ;
LDS.128 R16, [0x7c0] ;
IADD3 R12, R14, R13, R12 ;
IADD3 R8, R8, R15, R12 ;
LDS.128 R12, [0x7d0] ;
IADD3 R8, R10, R9, R8 ;
IADD3 R24, R24, R11, R8 ;
LDS.128 R8, [0x7e0] ;
IADD3 R24, R26, R25, R24 ;
IADD3 R4, R4, R27, R24 ;
LDS.128 R24, [0x7f0] ;
IADD3 R4, R6, R5, R4 ;
IADD3 R4, R20, R7, R4 ;
IADD3 R4, R22, R21, R4 ;
IADD3 R4, R16, R23, R4 ;
IADD3 R4, R18, R17, R4 ;
IADD3 R4, R12, R19, R4 ;
IADD3 R4, R14, R13, R4 ;
IADD3 R4, R8, R15, R4 ;
IADD3 R4, R10, R9, R4 ;
IADD3 R4, R24, R11, R4 ;
IADD3 R4, R26, R25, R4 ;
IMAD.IADD R27, R4, 0x1, R27 ;
RED.E.ADD.STRONG.GPU [R2.64], R27 ;
EXIT ;
BRA 0x1930;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
```
|
```amdasm
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3dotPiS_S_ ; -- Begin function _Z3dotPiS_S_
.globl _Z3dotPiS_S_
.p2align 8
.type _Z3dotPiS_S_,@function
_Z3dotPiS_S_: ; @_Z3dotPiS_S_
; %bb.0:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b128 s[4:7], s[0:1], 0x0
s_mov_b32 s3, exec_lo
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, 0
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[1:2], 2, v[1:2]
v_add_co_u32 v3, vcc_lo, s4, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v2, vcc_lo
v_add_co_u32 v1, vcc_lo, s6, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s7, v2, vcc_lo
global_load_b32 v3, v[3:4], off
global_load_b32 v1, v[1:2], off
v_lshlrev_b32_e32 v2, 2, v0
s_waitcnt vmcnt(0)
v_mul_lo_u32 v1, v1, v3
ds_store_b32 v2, v1
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB0_5
; %bb.1: ; %.preheader.preheader
s_load_b64 s[0:1], s[0:1], 0x10
v_mov_b32_e32 v0, 0
.LBB0_2: ; %.preheader
; =>This Inner Loop Header: Depth=1
v_mov_b32_e32 v1, s2
s_add_i32 s2, s2, 4
s_delay_alu instid0(SALU_CYCLE_1)
s_cmpk_eq_i32 s2, 0x800
ds_load_b32 v1, v1
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v0, v1, v0
s_cbranch_scc0 .LBB0_2
; %bb.3:
s_mov_b32 s2, exec_lo
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mbcnt_lo_u32_b32 v1, s2, 0
v_cmp_eq_u32_e32 vcc_lo, 0, v1
s_and_b32 s3, exec_lo, vcc_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_mov_b32 exec_lo, s3
s_cbranch_execz .LBB0_5
; %bb.4:
s_bcnt1_i32_b32 s2, s2
v_mov_b32_e32 v1, 0
v_mul_lo_u32 v0, v0, s2
global_atomic_add_u32 v1, v0, s[0:1]
.LBB0_5:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3dotPiS_S_
.amdhsa_group_segment_fixed_size 2048
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3dotPiS_S_, .Lfunc_end0-_Z3dotPiS_S_
; -- End function
.section .AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 280
; NumSgprs: 18
; NumVgprs: 5
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 2048 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 5
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object ; @__hip_cuid_
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0 ; 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 2048
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3dotPiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z3dotPiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
```
| 7,224 | 2,861 |
327 |
Convert the following CUDA host assembly code to AMD host assembly:
```cudaasm
.file "tmpxft_00012728_00000000-6_dot.cudafe1.cpp"
.text
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z26__device_stub__Z3dotPiS_S_PiS_S_
.type _Z26__device_stub__Z3dotPiS_S_PiS_S_, @function
_Z26__device_stub__Z3dotPiS_S_PiS_S_:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z3dotPiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z26__device_stub__Z3dotPiS_S_PiS_S_, .-_Z26__device_stub__Z3dotPiS_S_PiS_S_
.globl _Z3dotPiS_S_
.type _Z3dotPiS_S_, @function
_Z3dotPiS_S_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z3dotPiS_S_PiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z3dotPiS_S_, .-_Z3dotPiS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z3dotPiS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z3dotPiS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
```
|
```amdasm
.text
.file "dot.hip"
.globl _Z18__device_stub__dotPiS_S_ # -- Begin function _Z18__device_stub__dotPiS_S_
.type _Z18__device_stub__dotPiS_S_,@function
_Z18__device_stub__dotPiS_S_: # @_Z18__device_stub__dotPiS_S_
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $112, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 40(%rsp), %rax
movq %rdi, (%rax)
leaq 32(%rsp), %rcx
movq %rsi, (%rcx)
leaq 24(%rsp), %rsi
movq %rdx, (%rsi)
leaq 80(%rsp), %rbx
movq %rax, (%rbx)
movq %rcx, 8(%rbx)
movq %rsi, 16(%rbx)
leaq 64(%rsp), %r14
leaq 48(%rsp), %r15
leaq 16(%rsp), %r12
leaq 8(%rsp), %r13
movq %r14, %rdi
movq %r15, %rsi
movq %r12, %rdx
movq %r13, %rcx
callq __hipPopCallConfiguration
movq (%r14), %rsi
movl 8(%r14), %edx
movq (%r15), %rcx
movl 8(%r15), %r8d
movl $_Z3dotPiS_S_, %edi
movq %rbx, %r9
pushq (%r13)
.cfi_adjust_cfa_offset 8
pushq (%r12)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $128, %rsp
.cfi_adjust_cfa_offset -128
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z18__device_stub__dotPiS_S_, .Lfunc_end0-_Z18__device_stub__dotPiS_S_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, %rdi
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3dotPiS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3dotPiS_S_,@object # @_Z3dotPiS_S_
.section .rodata,"a",@progbits
.globl _Z3dotPiS_S_
.p2align 3, 0x0
_Z3dotPiS_S_:
.quad _Z18__device_stub__dotPiS_S_
.size _Z3dotPiS_S_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z3dotPiS_S_"
.size .L__unnamed_1, 13
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__dotPiS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3dotPiS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
```
| 1,811 | 1,989 |
332 |
Convert the following CUDA device assembly code to AMD device assembly:
```cudaasm
code for sm_80
Function : _Z10sum_atomiciPiS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
MOV R1, c[0x0][0x28] ;
S2R R2, SR_CTAID.X ;
S2R R3, SR_TID.X ;
IMAD R2, R2, c[0x0][0x0], R3 ;
ISETP.GE.AND P0, PT, R2, c[0x0][0x160], PT ;
@P0 EXIT ;
HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ;
ULDC.64 UR6, c[0x0][0x118] ;
IMAD.WIDE R2, R2, R3, c[0x0][0x170] ;
LDG.E R2, [R2.64] ;
VOTEU.ANY UR4, UPT, PT ;
IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x168] ;
UFLO.U32 UR4, UR4 ;
S2R R0, SR_LANEID ;
MOV R5, c[0x0][0x16c] ;
ISETP.EQ.U32.AND P0, PT, R0, UR4, PT ;
REDUX.SUM UR5, R2 ;
IMAD.U32 R7, RZ, RZ, UR5 ;
@P0 RED.E.ADD.STRONG.GPU [R4.64], R7 ;
EXIT ;
BRA 0x140;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
```
|
```amdasm
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10sum_atomiciPiS_ ; -- Begin function _Z10sum_atomiciPiS_
.globl _Z10sum_atomiciPiS_
.p2align 8
.type _Z10sum_atomiciPiS_,@function
_Z10sum_atomiciPiS_: ; @_Z10sum_atomiciPiS_
; %bb.0:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s3, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_5
; %bb.1:
s_load_b128 s[0:3], s[0:1], 0x8
v_ashrrev_i32_e32 v2, 31, v1
s_mov_b32 s4, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
s_mov_b32 s2, 0
global_load_b32 v0, v[0:1], off
.LBB0_2: ; %ComputeLoop
; =>This Inner Loop Header: Depth=1
s_ctz_i32_b32 s3, s4
s_waitcnt vmcnt(0)
v_readlane_b32 s5, v0, s3
s_lshl_b32 s3, 1, s3
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_and_not1_b32 s4, s4, s3
s_add_i32 s2, s2, s5
s_cmp_lg_u32 s4, 0
s_cbranch_scc1 .LBB0_2
; %bb.3: ; %ComputeEnd
v_mbcnt_lo_u32_b32 v0, exec_lo, 0
s_mov_b32 s3, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_eq_u32_e32 0, v0
s_xor_b32 s3, exec_lo, s3
s_cbranch_execz .LBB0_5
; %bb.4:
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
global_atomic_add_u32 v0, v1, s[0:1]
.LBB0_5: ; %Flow13
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10sum_atomiciPiS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10sum_atomiciPiS_, .Lfunc_end0-_Z10sum_atomiciPiS_
; -- End function
.section .AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 216
; NumSgprs: 18
; NumVgprs: 3
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 3
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object ; @__hip_cuid_
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0 ; 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10sum_atomiciPiS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z10sum_atomiciPiS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
```
| 448 | 2,706 |
333 |
Convert the following CUDA host assembly code to AMD host assembly:
```cudaasm
.file "tmpxft_000c8f46_00000000-6_kernel_functions_for_atomic.cudafe1.cpp"
.text
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z33__device_stub__Z10sum_atomiciPiS_iPiS_
.type _Z33__device_stub__Z10sum_atomiciPiS_iPiS_, @function
_Z33__device_stub__Z10sum_atomiciPiS_iPiS_:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movl %edi, 28(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z10sum_atomiciPiS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z33__device_stub__Z10sum_atomiciPiS_iPiS_, .-_Z33__device_stub__Z10sum_atomiciPiS_iPiS_
.globl _Z10sum_atomiciPiS_
.type _Z10sum_atomiciPiS_, @function
_Z10sum_atomiciPiS_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z10sum_atomiciPiS_iPiS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z10sum_atomiciPiS_, .-_Z10sum_atomiciPiS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z10sum_atomiciPiS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z10sum_atomiciPiS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
```
|
```amdasm
.text
.file "kernel_functions_for_atomic.hip"
.globl _Z25__device_stub__sum_atomiciPiS_ # -- Begin function _Z25__device_stub__sum_atomiciPiS_
.type _Z25__device_stub__sum_atomiciPiS_,@function
_Z25__device_stub__sum_atomiciPiS_: # @_Z25__device_stub__sum_atomiciPiS_
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $112, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 12(%rsp), %rax
movl %edi, (%rax)
leaq 40(%rsp), %rcx
movq %rsi, (%rcx)
leaq 32(%rsp), %rsi
movq %rdx, (%rsi)
leaq 80(%rsp), %rbx
movq %rax, (%rbx)
movq %rcx, 8(%rbx)
movq %rsi, 16(%rbx)
leaq 64(%rsp), %r14
leaq 48(%rsp), %r15
leaq 24(%rsp), %r12
leaq 16(%rsp), %r13
movq %r14, %rdi
movq %r15, %rsi
movq %r12, %rdx
movq %r13, %rcx
callq __hipPopCallConfiguration
movq (%r14), %rsi
movl 8(%r14), %edx
movq (%r15), %rcx
movl 8(%r15), %r8d
movl $_Z10sum_atomiciPiS_, %edi
movq %rbx, %r9
pushq (%r13)
.cfi_adjust_cfa_offset 8
pushq (%r12)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $128, %rsp
.cfi_adjust_cfa_offset -128
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z25__device_stub__sum_atomiciPiS_, .Lfunc_end0-_Z25__device_stub__sum_atomiciPiS_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, %rdi
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10sum_atomiciPiS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10sum_atomiciPiS_,@object # @_Z10sum_atomiciPiS_
.section .rodata,"a",@progbits
.globl _Z10sum_atomiciPiS_
.p2align 3, 0x0
_Z10sum_atomiciPiS_:
.quad _Z25__device_stub__sum_atomiciPiS_
.size _Z10sum_atomiciPiS_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z10sum_atomiciPiS_"
.size .L__unnamed_1, 20
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__sum_atomiciPiS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10sum_atomiciPiS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
```
| 1,835 | 2,018 |
334 |
Convert the following CUDA device assembly code to AMD device assembly:
```cudaasm
code for sm_80
Function : _Z28kernel_vec_equals_minus_vec1PdS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
MOV R1, c[0x0][0x28] ;
S2R R4, SR_TID.X ;
S2R R3, SR_CTAID.X ;
IMAD R4, R3, c[0x0][0x0], R4 ;
ISETP.GE.AND P0, PT, R4, c[0x0][0x170], PT ;
@P0 EXIT ;
HFMA2.MMA R5, -RZ, RZ, 0, 4.76837158203125e-07 ;
ULDC.64 UR4, c[0x0][0x118] ;
IMAD.WIDE R2, R4, R5, c[0x0][0x168] ;
LDG.E.64 R2, [R2.64] ;
IMAD.WIDE R4, R4, R5, c[0x0][0x160] ;
DADD R6, -RZ, -R2 ;
STG.E.64 [R4.64], R6 ;
EXIT ;
BRA 0xe0;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
```
|
```amdasm
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z28kernel_vec_equals_minus_vec1PdS_i ; -- Begin function _Z28kernel_vec_equals_minus_vec1PdS_i
.globl _Z28kernel_vec_equals_minus_vec1PdS_i
.p2align 8
.type _Z28kernel_vec_equals_minus_vec1PdS_i,@function
_Z28kernel_vec_equals_minus_vec1PdS_i: ; @_Z28kernel_vec_equals_minus_vec1PdS_i
; %bb.0:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s3, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
; %bb.1:
s_load_b128 s[0:3], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 3, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_load_b64 v[2:3], v[2:3], off
s_waitcnt vmcnt(0)
v_xor_b32_e32 v3, 0x80000000, v3
global_store_b64 v[0:1], v[2:3], off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z28kernel_vec_equals_minus_vec1PdS_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z28kernel_vec_equals_minus_vec1PdS_i, .Lfunc_end0-_Z28kernel_vec_equals_minus_vec1PdS_i
; -- End function
.section .AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 156
; NumSgprs: 18
; NumVgprs: 4
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 4
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object ; @__hip_cuid_
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0 ; 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z28kernel_vec_equals_minus_vec1PdS_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z28kernel_vec_equals_minus_vec1PdS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
```
| 354 | 2,518 |
335 |
Convert the following CUDA host assembly code to AMD host assembly:
```cudaasm
.file "tmpxft_00073d79_00000000-6_kernel_vec_equals_minus_vec1.cudafe1.cpp"
.text
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z51__device_stub__Z28kernel_vec_equals_minus_vec1PdS_iPdS_i
.type _Z51__device_stub__Z28kernel_vec_equals_minus_vec1PdS_iPdS_i, @function
_Z51__device_stub__Z28kernel_vec_equals_minus_vec1PdS_iPdS_i:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z28kernel_vec_equals_minus_vec1PdS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z51__device_stub__Z28kernel_vec_equals_minus_vec1PdS_iPdS_i, .-_Z51__device_stub__Z28kernel_vec_equals_minus_vec1PdS_iPdS_i
.globl _Z28kernel_vec_equals_minus_vec1PdS_i
.type _Z28kernel_vec_equals_minus_vec1PdS_i, @function
_Z28kernel_vec_equals_minus_vec1PdS_i:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z51__device_stub__Z28kernel_vec_equals_minus_vec1PdS_iPdS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z28kernel_vec_equals_minus_vec1PdS_i, .-_Z28kernel_vec_equals_minus_vec1PdS_i
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z28kernel_vec_equals_minus_vec1PdS_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z28kernel_vec_equals_minus_vec1PdS_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
```
|
```amdasm
.text
.file "kernel_vec_equals_minus_vec1.hip"
.globl _Z43__device_stub__kernel_vec_equals_minus_vec1PdS_i # -- Begin function _Z43__device_stub__kernel_vec_equals_minus_vec1PdS_i
.type _Z43__device_stub__kernel_vec_equals_minus_vec1PdS_i,@function
_Z43__device_stub__kernel_vec_equals_minus_vec1PdS_i: # @_Z43__device_stub__kernel_vec_equals_minus_vec1PdS_i
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $112, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 40(%rsp), %rax
movq %rdi, (%rax)
leaq 32(%rsp), %rcx
movq %rsi, (%rcx)
leaq 12(%rsp), %rsi
movl %edx, (%rsi)
leaq 80(%rsp), %rbx
movq %rax, (%rbx)
movq %rcx, 8(%rbx)
movq %rsi, 16(%rbx)
leaq 64(%rsp), %r14
leaq 48(%rsp), %r15
leaq 24(%rsp), %r12
leaq 16(%rsp), %r13
movq %r14, %rdi
movq %r15, %rsi
movq %r12, %rdx
movq %r13, %rcx
callq __hipPopCallConfiguration
movq (%r14), %rsi
movl 8(%r14), %edx
movq (%r15), %rcx
movl 8(%r15), %r8d
movl $_Z28kernel_vec_equals_minus_vec1PdS_i, %edi
movq %rbx, %r9
pushq (%r13)
.cfi_adjust_cfa_offset 8
pushq (%r12)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $128, %rsp
.cfi_adjust_cfa_offset -128
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z43__device_stub__kernel_vec_equals_minus_vec1PdS_i, .Lfunc_end0-_Z43__device_stub__kernel_vec_equals_minus_vec1PdS_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, %rdi
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z28kernel_vec_equals_minus_vec1PdS_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z28kernel_vec_equals_minus_vec1PdS_i,@object # @_Z28kernel_vec_equals_minus_vec1PdS_i
.section .rodata,"a",@progbits
.globl _Z28kernel_vec_equals_minus_vec1PdS_i
.p2align 3, 0x0
_Z28kernel_vec_equals_minus_vec1PdS_i:
.quad _Z43__device_stub__kernel_vec_equals_minus_vec1PdS_i
.size _Z28kernel_vec_equals_minus_vec1PdS_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z28kernel_vec_equals_minus_vec1PdS_i"
.size .L__unnamed_1, 38
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z43__device_stub__kernel_vec_equals_minus_vec1PdS_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z28kernel_vec_equals_minus_vec1PdS_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
```
| 1,915 | 2,103 |
336 |
Convert the following CUDA device assembly code to AMD device assembly:
```cudaasm
code for sm_80
```
|
```amdasm
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object ; @__hip_cuid_
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0 ; 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
```
| 24 | 306 |
337 |
Convert the following CUDA host assembly code to AMD host assembly:
```cudaasm
.file "tmpxft_0002f241_00000000-6_pgm_utility.cudafe1.cpp"
.text
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "w"
.LC3:
.string "P2\n"
.LC4:
.string "
.LC5:
.string "%d %d\n"
.LC6:
.string "%d\n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC7:
.string "\nImpossibile creare il file %s\n"
.text
.globl _Z11write_imagePciP4meshPd
.type _Z11write_imagePciP4meshPd, @function
_Z11write_imagePciP4meshPd:
.LFB2057:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
movq %rdi, %r14
movq %rcx, %r13
movl 28(%rdx), %r12d
movl 24(%rdx), %ebx
movslq %esi, %rsi
leaq 0(,%rsi,4), %rdi
call malloc@PLT
movq %rax, %rbp
testl %ebx, %ebx
jle .L5
movl $0, %r8d
movl $0, %r9d
movslq %r12d, %r10
movsd .LC0(%rip), %xmm2
movsd .LC1(%rip), %xmm1
jmp .L4
.L6:
movslq %edx, %rdi
movl %ecx, 0(%rbp,%rdi,4)
.L7:
addq $8, %rax
addl %ebx, %edx
cmpq %rsi, %rax
je .L20
.L8:
movapd %xmm2, %xmm0
subsd (%rax), %xmm0
mulsd %xmm1, %xmm0
cvttsd2sil %xmm0, %ecx
cmpl $255, %ecx
jle .L6
movslq %edx, %rcx
movl $255, 0(%rbp,%rcx,4)
jmp .L7
.L20:
addl %r12d, %r9d
.L10:
addl $1, %r8d
cmpl %r8d, %ebx
je .L5
.L4:
testl %r12d, %r12d
jle .L10
movslq %r9d, %rcx
leaq 0(%r13,%rcx,8), %rax
movl %r8d, %edx
addq %r10, %rcx
leaq 0(%r13,%rcx,8), %rsi
jmp .L8
.L5:
leaq .LC2(%rip), %rsi
movq %r14, %rdi
call fopen@PLT
movq %rax, %r13
testq %rax, %rax
je .L11
leaq .LC3(%rip), %rdx
movl $2, %esi
movq %rax, %rdi
movl $0, %eax
call __fprintf_chk@PLT
leaq .LC4(%rip), %rdx
movl $2, %esi
movq %r13, %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %r12d, %r8d
movl %ebx, %ecx
leaq .LC5(%rip), %rdx
movl $2, %esi
movq %r13, %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $255, %ecx
leaq .LC6(%rip), %rdx
movl $2, %esi
movq %r13, %rdi
movl $0, %eax
call __fprintf_chk@PLT
imull %ebx, %r12d
testl %r12d, %r12d
jle .L12
movq %rbp, %rbx
movslq %r12d, %r12
leaq 0(%rbp,%r12,4), %r14
leaq .LC6(%rip), %r12
.L13:
movl (%rbx), %ecx
movq %r12, %rdx
movl $2, %esi
movq %r13, %rdi
movl $0, %eax
call __fprintf_chk@PLT
addq $4, %rbx
cmpq %r14, %rbx
jne .L13
.L12:
movq %r13, %rdi
call fclose@PLT
movq %rbp, %rdi
call free@PLT
movl $0, %eax
.L3:
popq %rbx
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore_state
movq %r14, %rdx
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %rbp, %rdi
call free@PLT
movl $-1, %eax
jmp .L3
.cfi_endproc
.LFE2057:
.size _Z11write_imagePciP4meshPd, .-_Z11write_imagePciP4meshPd
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC0:
.long 0
.long 1072693248
.align 8
.LC1:
.long 0
.long 1081073664
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
```
|
```amdasm
.text
.file "pgm_utility.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
```
| 2,458 | 186 |
338 |
Convert the following CUDA device assembly code to AMD device assembly:
```cudaasm
code for sm_80
Function : _Z12Complex_multP6float2PKS_S2_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
MOV R1, c[0x0][0x28] ;
S2R R6, SR_TID.X ;
HFMA2.MMA R7, -RZ, RZ, 0, 4.76837158203125e-07 ;
ULDC.64 UR4, c[0x0][0x118] ;
S2R R3, SR_CTAID.X ;
IMAD R6, R3, c[0x0][0x0], R6 ;
IMAD.WIDE R2, R6, R7, c[0x0][0x168] ;
IMAD.WIDE R4, R6.reuse, R7.reuse, c[0x0][0x170] ;
LDG.E.64 R8, [R2.64] ;
LDG.E.64 R10, [R4.64] ;
IMAD.WIDE R6, R6, R7, c[0x0][0x160] ;
FMUL R13, R9, R11 ;
FFMA R13, R8, R10, R13 ;
STG.E [R6.64], R13 ;
LDG.E R0, [R2.64] ;
LDG.E R8, [R4.64] ;
FMUL R0, R11, R0 ;
FFMA R9, R9, R8, -R0 ;
STG.E [R6.64+0x4], R9 ;
EXIT ;
BRA 0x140;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
```
|
```amdasm
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z12Complex_multP15HIP_vector_typeIfLj2EEPKS0_S3_ ; -- Begin function _Z12Complex_multP15HIP_vector_typeIfLj2EEPKS0_S3_
.globl _Z12Complex_multP15HIP_vector_typeIfLj2EEPKS0_S3_
.p2align 8
.type _Z12Complex_multP15HIP_vector_typeIfLj2EEPKS0_S3_,@function
_Z12Complex_multP15HIP_vector_typeIfLj2EEPKS0_S3_: ; @_Z12Complex_multP15HIP_vector_typeIfLj2EEPKS0_S3_
; %bb.0:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x24
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 3, v[1:2]
v_add_co_u32 v2, vcc_lo, s6, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s1, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s4, v0
global_load_b64 v[6:7], v[2:3], off
global_load_b64 v[8:9], v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
s_waitcnt vmcnt(0)
v_mul_f32_e32 v7, v7, v9
s_delay_alu instid0(VALU_DEP_1)
v_fmac_f32_e32 v7, v6, v8
global_store_b32 v[0:1], v7, off
global_load_b64 v[2:3], v[2:3], off
global_load_b64 v[4:5], v[4:5], off
s_waitcnt vmcnt(0)
v_mul_f32_e32 v2, v2, v5
s_delay_alu instid0(VALU_DEP_1)
v_fma_f32 v2, v3, v4, -v2
global_store_b32 v[0:1], v2, off offset:4
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z12Complex_multP15HIP_vector_typeIfLj2EEPKS0_S3_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 10
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z12Complex_multP15HIP_vector_typeIfLj2EEPKS0_S3_, .Lfunc_end0-_Z12Complex_multP15HIP_vector_typeIfLj2EEPKS0_S3_
; -- End function
.section .AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 204
; NumSgprs: 18
; NumVgprs: 10
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 10
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object ; @__hip_cuid_
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0 ; 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z12Complex_multP15HIP_vector_typeIfLj2EEPKS0_S3_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z12Complex_multP15HIP_vector_typeIfLj2EEPKS0_S3_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 10
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
```
| 462 | 2,759 |
339 |
Convert the following CUDA host assembly code to AMD host assembly:
```cudaasm
.file "tmpxft_000bcaa7_00000000-6_vectorAdd.cudafe1.cpp"
.text
.globl _ZSt21ios_base_library_initv
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB4099:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4099:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z3nowv
.type _Z3nowv, @function
_Z3nowv:
.LFB4092:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _ZNSt6chrono3_V212system_clock3nowEv@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4092:
.size _Z3nowv, .-_Z3nowv
.globl _Z45__device_stub__Z12Complex_multP6float2PKS_S2_P6float2PKS_S2_
.type _Z45__device_stub__Z12Complex_multP6float2PKS_S2_P6float2PKS_S2_, @function
_Z45__device_stub__Z12Complex_multP6float2PKS_S2_P6float2PKS_S2_:
.LFB4121:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L9
.L5:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L10
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L9:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z12Complex_multP6float2PKS_S2_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L5
.L10:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4121:
.size _Z45__device_stub__Z12Complex_multP6float2PKS_S2_P6float2PKS_S2_, .-_Z45__device_stub__Z12Complex_multP6float2PKS_S2_P6float2PKS_S2_
.globl _Z12Complex_multP6float2PKS_S2_
.type _Z12Complex_multP6float2PKS_S2_, @function
_Z12Complex_multP6float2PKS_S2_:
.LFB4122:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z45__device_stub__Z12Complex_multP6float2PKS_S2_P6float2PKS_S2_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4122:
.size _Z12Complex_multP6float2PKS_S2_, .-_Z12Complex_multP6float2PKS_S2_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "VIDEO MEM: "
.LC2:
.string " ms"
.LC3:
.string "COPY DATA: "
.LC4:
.string "FFT: "
.LC5:
.string "cMULT: "
.LC6:
.string "IFFT: "
.LC7:
.string "COPY FROM VIDEO: "
.text
.globl FFT_GPU
.type FFT_GPU, @function
FFT_GPU:
.LFB4094:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $88, %rsp
.cfi_def_cfa_offset 144
movq %rdi, %r14
movq %rsi, 8(%rsp)
movl %edx, %r12d
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
call _ZNSt6chrono3_V212system_clock3nowEv@PLT
movq %rax, %rbp
movslq %r12d, %r15
leaq 0(,%r15,8), %rbx
leaq 24(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq 32(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq 20(%rsp), %rdi
movl $1, %ecx
movl $41, %edx
movl %r12d, %esi
call cufftPlan1d@PLT
call _ZNSt6chrono3_V212system_clock3nowEv@PLT
movq %rax, %r12
movl $11, %edx
leaq .LC0(%rip), %rsi
leaq _ZSt4cout(%rip), %r13
movq %r13, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq %r12, %rax
subq %rbp, %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
divsd .LC1(%rip), %xmm0
movq %r13, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rbp
movl $3, %edx
leaq .LC2(%rip), %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq 0(%rbp), %rax
movq -24(%rax), %rax
movq 240(%rbp,%rax), %r13
testq %r13, %r13
je .L44
cmpb $0, 56(%r13)
je .L16
movzbl 67(%r13), %esi
.L17:
movsbl %sil, %esi
movq %rbp, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movl $1, %ecx
movq %rbx, %rdx
movq %r14, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %rbx, %rdx
movq 8(%rsp), %rsi
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
call _ZNSt6chrono3_V212system_clock3nowEv@PLT
movq %rax, %rbp
movl $11, %edx
leaq .LC3(%rip), %rsi
leaq _ZSt4cout(%rip), %r13
movq %r13, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
subq %r12, %rbp
pxor %xmm0, %xmm0
cvtsi2sdq %rbp, %xmm0
divsd .LC1(%rip), %xmm0
movq %r13, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rbp
movl $3, %edx
leaq .LC2(%rip), %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq 0(%rbp), %rax
movq -24(%rax), %rax
movq 240(%rbp,%rax), %r12
testq %r12, %r12
je .L45
cmpb $0, 56(%r12)
je .L20
movzbl 67(%r12), %esi
.L21:
movsbl %sil, %esi
movq %rbp, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
call _ZNSt6chrono3_V212system_clock3nowEv@PLT
movq %rax, %r12
movq 24(%rsp), %rsi
movl $-1, %ecx
movq %rsi, %rdx
movl 20(%rsp), %edi
call cufftExecC2C@PLT
movq 32(%rsp), %rsi
movl $-1, %ecx
movq %rsi, %rdx
movl 20(%rsp), %edi
call cufftExecC2C@PLT
call _ZNSt6chrono3_V212system_clock3nowEv@PLT
movq %rax, %rbp
movl $5, %edx
leaq .LC4(%rip), %rsi
leaq _ZSt4cout(%rip), %r13
movq %r13, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
subq %r12, %rbp
pxor %xmm0, %xmm0
cvtsi2sdq %rbp, %xmm0
divsd .LC1(%rip), %xmm0
movq %r13, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rbp
movl $3, %edx
leaq .LC2(%rip), %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq 0(%rbp), %rax
movq -24(%rax), %rax
movq 240(%rbp,%rax), %r12
testq %r12, %r12
je .L46
cmpb $0, 56(%r12)
je .L24
movzbl 67(%r12), %esi
.L25:
movsbl %sil, %esi
movq %rbp, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
leaq 40(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
call _ZNSt6chrono3_V212system_clock3nowEv@PLT
movq %rax, %r12
movl $192, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $256, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 60(%rsp), %rdx
movl $1, %ecx
movq 48(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L47
.L26:
call _ZNSt6chrono3_V212system_clock3nowEv@PLT
movq %rax, %rbp
movl $7, %edx
leaq .LC5(%rip), %rsi
leaq _ZSt4cout(%rip), %r13
movq %r13, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
subq %r12, %rbp
pxor %xmm0, %xmm0
cvtsi2sdq %rbp, %xmm0
divsd .LC1(%rip), %xmm0
movq %r13, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rbp
movl $3, %edx
leaq .LC2(%rip), %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq 0(%rbp), %rax
movq -24(%rax), %rax
movq 240(%rbp,%rax), %r12
testq %r12, %r12
je .L48
cmpb $0, 56(%r12)
je .L29
movzbl 67(%r12), %esi
.L30:
movsbl %sil, %esi
movq %rbp, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
call _ZNSt6chrono3_V212system_clock3nowEv@PLT
movq %rax, %r12
movq 40(%rsp), %rsi
movl $1, %ecx
movq %rsi, %rdx
movl 20(%rsp), %edi
call cufftExecC2C@PLT
call _ZNSt6chrono3_V212system_clock3nowEv@PLT
movq %rax, %rbp
movl $6, %edx
leaq .LC6(%rip), %rsi
leaq _ZSt4cout(%rip), %r13
movq %r13, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
subq %r12, %rbp
pxor %xmm0, %xmm0
cvtsi2sdq %rbp, %xmm0
divsd .LC1(%rip), %xmm0
movq %r13, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rbp
movl $3, %edx
leaq .LC2(%rip), %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq 0(%rbp), %rax
movq -24(%rax), %rax
movq 240(%rbp,%rax), %r12
testq %r12, %r12
je .L49
cmpb $0, 56(%r12)
je .L33
movzbl 67(%r12), %esi
.L34:
movsbl %sil, %esi
movq %rbp, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
shrq $60, %r15
jne .L35
movq %rbx, %rdi
call _Znam@PLT
movq %rax, %rbp
call _ZNSt6chrono3_V212system_clock3nowEv@PLT
movq %rax, %r12
movl $2, %ecx
movq %rbx, %rdx
movq 40(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
call _ZNSt6chrono3_V212system_clock3nowEv@PLT
movq %rax, %rbx
movl $17, %edx
leaq .LC7(%rip), %rsi
leaq _ZSt4cout(%rip), %r13
movq %r13, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
subq %r12, %rbx
pxor %xmm0, %xmm0
cvtsi2sdq %rbx, %xmm0
divsd .LC1(%rip), %xmm0
movq %r13, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rbx
movl $3, %edx
leaq .LC2(%rip), %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq (%rbx), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %r12
testq %r12, %r12
je .L50
cmpb $0, 56(%r12)
je .L38
movzbl 67(%r12), %esi
.L39:
movsbl %sil, %esi
movq %rbx, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L51
movq %rbp, %rax
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L44:
.cfi_restore_state
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L52
call _ZSt16__throw_bad_castv@PLT
.L52:
call __stack_chk_fail@PLT
.L16:
movq %r13, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq 0(%r13), %rax
movl $10, %esi
movq %r13, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L17
.L45:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L53
call _ZSt16__throw_bad_castv@PLT
.L53:
call __stack_chk_fail@PLT
.L20:
movq %r12, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r12), %rax
movl $10, %esi
movq %r12, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L21
.L46:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L54
call _ZSt16__throw_bad_castv@PLT
.L54:
call __stack_chk_fail@PLT
.L24:
movq %r12, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r12), %rax
movl $10, %esi
movq %r12, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L25
.L47:
movq 32(%rsp), %rdx
movq 24(%rsp), %rsi
movq 40(%rsp), %rdi
call _Z45__device_stub__Z12Complex_multP6float2PKS_S2_P6float2PKS_S2_
jmp .L26
.L48:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L55
call _ZSt16__throw_bad_castv@PLT
.L55:
call __stack_chk_fail@PLT
.L29:
movq %r12, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r12), %rax
movl $10, %esi
movq %r12, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L30
.L49:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L56
call _ZSt16__throw_bad_castv@PLT
.L56:
call __stack_chk_fail@PLT
.L33:
movq %r12, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r12), %rax
movl $10, %esi
movq %r12, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L34
.L50:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L57
call _ZSt16__throw_bad_castv@PLT
.L57:
call __stack_chk_fail@PLT
.L38:
movq %r12, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r12), %rax
movl $10, %esi
movq %r12, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L39
.L35:
movq 72(%rsp), %rax
subq %fs:40, %rax
je .L40
call __stack_chk_fail@PLT
.L40:
call __cxa_throw_bad_array_new_length@PLT
.L51:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4094:
.size FFT_GPU, .-FFT_GPU
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC8:
.string "_Z12Complex_multP6float2PKS_S2_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB4124:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _Z12Complex_multP6float2PKS_S2_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4124:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC1:
.long 0
.long 1093567616
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
```
|
```amdasm
.text
.file "vectorAdd.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z27__device_stub__Complex_multP15HIP_vector_typeIfLj2EEPKS0_S3_ # -- Begin function _Z27__device_stub__Complex_multP15HIP_vector_typeIfLj2EEPKS0_S3_
.type _Z27__device_stub__Complex_multP15HIP_vector_typeIfLj2EEPKS0_S3_,@function
_Z27__device_stub__Complex_multP15HIP_vector_typeIfLj2EEPKS0_S3_: # @_Z27__device_stub__Complex_multP15HIP_vector_typeIfLj2EEPKS0_S3_
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $112, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 40(%rsp), %rax
movq %rdi, (%rax)
leaq 32(%rsp), %rcx
movq %rsi, (%rcx)
leaq 24(%rsp), %rsi
movq %rdx, (%rsi)
leaq 80(%rsp), %rbx
movq %rax, (%rbx)
movq %rcx, 8(%rbx)
movq %rsi, 16(%rbx)
leaq 64(%rsp), %r14
leaq 48(%rsp), %r15
leaq 16(%rsp), %r12
leaq 8(%rsp), %r13
movq %r14, %rdi
movq %r15, %rsi
movq %r12, %rdx
movq %r13, %rcx
callq __hipPopCallConfiguration
movq (%r14), %rsi
movl 8(%r14), %edx
movq (%r15), %rcx
movl 8(%r15), %r8d
movl $_Z12Complex_multP15HIP_vector_typeIfLj2EEPKS0_S3_, %edi
movq %rbx, %r9
pushq (%r13)
.cfi_adjust_cfa_offset 8
pushq (%r12)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $128, %rsp
.cfi_adjust_cfa_offset -128
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z27__device_stub__Complex_multP15HIP_vector_typeIfLj2EEPKS0_S3_, .Lfunc_end0-_Z27__device_stub__Complex_multP15HIP_vector_typeIfLj2EEPKS0_S3_
.cfi_endproc
# -- End function
.globl _Z3nowv # -- Begin function _Z3nowv
.type _Z3nowv,@function
_Z3nowv: # @_Z3nowv
.cfi_startproc
# %bb.0:
jmp _ZNSt6chrono3_V212system_clock3nowEv # TAILCALL
.Lfunc_end1:
.size _Z3nowv, .Lfunc_end1-_Z3nowv
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function FFT_GPU
.LCPI2_0:
.quad 0x412e848000000000 # double 1.0E+6
.text
.globl FFT_GPU
.type FFT_GPU,@function
FFT_GPU: # @FFT_GPU
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $40, %rsp
.cfi_def_cfa_offset 96
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %edx, %ebx
movq %rsi, %r13
movq %rdi, %rbp
callq _ZNSt6chrono3_V212system_clock3nowEv
movq %rax, %r15
movl %ebx, 20(%rsp) # 4-byte Spill
movslq %ebx, %r14
leaq (,%r14,8), %rbx
leaq 32(%rsp), %r12
movq %r12, %rdi
movq %rbx, %rsi
callq hipMalloc
leaq 8(%rsp), %rdi
movq %rbx, %rsi
callq hipMalloc
leaq 24(%rsp), %rdi
movl %r14d, %esi
movl $41, %edx
movl $1, %ecx
callq hipfftPlan1d
callq _ZNSt6chrono3_V212system_clock3nowEv
movq %rax, %r14
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $11, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq %r14, %rax
subq %r15, %rax
cvtsi2sd %rax, %xmm0
divsd .LCPI2_0(%rip), %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq %rax, %r15
movl $.L.str.1, %esi
movl $3, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq (%r15), %rax
movq -24(%rax), %rdi
addq %r15, %rdi
movl $10, %esi
callq _ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
movsbl %al, %esi
movq %r15, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq (%r12), %rdi
movq %rbp, %rsi
movq %rbx, %rdx
movl $1, %ecx
callq hipMemcpy
leaq 8(%rsp), %rax
movq (%rax), %rdi
movq %r13, %rsi
movq %rbx, %rdx
movl $1, %ecx
callq hipMemcpy
callq _ZNSt6chrono3_V212system_clock3nowEv
movq %rax, %r15
movl $_ZSt4cout, %edi
movl $.L.str.2, %esi
movl $11, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
subq %r14, %r15
xorps %xmm0, %xmm0
cvtsi2sd %r15, %xmm0
divsd .LCPI2_0(%rip), %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq %rax, %r14
movl $.L.str.1, %esi
movl $3, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq (%r14), %rax
movq -24(%rax), %rdi
addq %r14, %rdi
movl $10, %esi
callq _ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
movsbl %al, %esi
movq %r14, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
callq _ZNSt6chrono3_V212system_clock3nowEv
movq %rax, %r14
leaq 24(%rsp), %r15
movq (%r15), %rdi
movq (%r12), %rdx
movq %rdx, %rsi
movl $-1, %ecx
callq hipfftExecC2C
movq (%r15), %rdi
leaq 8(%rsp), %rax
movq (%rax), %rdx
movq %rdx, %rsi
movl $-1, %ecx
callq hipfftExecC2C
callq _ZNSt6chrono3_V212system_clock3nowEv
movq %rax, %r15
movl $_ZSt4cout, %edi
movl $.L.str.3, %esi
movl $5, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
subq %r14, %r15
xorps %xmm0, %xmm0
cvtsi2sd %r15, %xmm0
divsd .LCPI2_0(%rip), %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq %rax, %r14
movl $.L.str.1, %esi
movl $3, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq (%r14), %rax
movq -24(%rax), %rdi
addq %r14, %rdi
movl $10, %esi
callq _ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
movsbl %al, %esi
movq %r14, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq %rsp, %rdi
movq %rbx, %rsi
callq hipMalloc
callq _ZNSt6chrono3_V212system_clock3nowEv
movq %rax, %r14
movabsq $4294967488, %rdx # imm = 0x1000000C0
leaq 64(%rdx), %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_2
# %bb.1:
movq (%rsp), %rdi
movq 32(%rsp), %rsi
movq 8(%rsp), %rdx
callq _Z27__device_stub__Complex_multP15HIP_vector_typeIfLj2EEPKS0_S3_
.LBB2_2:
callq _ZNSt6chrono3_V212system_clock3nowEv
movq %rax, %r15
movl $_ZSt4cout, %edi
movl $.L.str.4, %esi
movl $7, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
subq %r14, %r15
xorps %xmm0, %xmm0
cvtsi2sd %r15, %xmm0
movsd .LCPI2_0(%rip), %xmm1 # xmm1 = mem[0],zero
divsd %xmm1, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq %rax, %r14
movl $.L.str.1, %esi
movl $3, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq (%r14), %rax
movq -24(%rax), %rdi
addq %r14, %rdi
movl $10, %esi
callq _ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
movsbl %al, %esi
movq %r14, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq 32(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
callq _ZNSt6chrono3_V212system_clock3nowEv
movq %rax, %r14
movq 24(%rsp), %rdi
movq (%rsp), %rdx
movq %rdx, %rsi
movl $1, %ecx
callq hipfftExecC2C
callq _ZNSt6chrono3_V212system_clock3nowEv
movq %rax, %r15
movl $_ZSt4cout, %edi
movl $.L.str.5, %esi
movl $6, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
subq %r14, %r15
xorps %xmm0, %xmm0
cvtsi2sd %r15, %xmm0
divsd .LCPI2_0(%rip), %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq %rax, %r14
movl $.L.str.1, %esi
movl $3, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq (%r14), %rax
movq -24(%rax), %rdi
addq %r14, %rdi
movl $10, %esi
callq _ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
movsbl %al, %esi
movq %r14, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
cmpl $0, 20(%rsp) # 4-byte Folded Reload
movq $-1, %rdi
cmovnsq %rbx, %rdi
callq _Znam
movq %rax, %r14
callq _ZNSt6chrono3_V212system_clock3nowEv
movq %rax, %r15
movq (%rsp), %rsi
movq %r14, %rdi
movq %rbx, %rdx
movl $2, %ecx
callq hipMemcpy
callq _ZNSt6chrono3_V212system_clock3nowEv
movq %rax, %rbx
movl $_ZSt4cout, %edi
movl $.L.str.6, %esi
movl $17, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
subq %r15, %rbx
xorps %xmm0, %xmm0
cvtsi2sd %rbx, %xmm0
divsd .LCPI2_0(%rip), %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq %rax, %rbx
movl $.L.str.1, %esi
movl $3, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq (%rbx), %rax
movq -24(%rax), %rdi
addq %rbx, %rdi
movl $10, %esi
callq _ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
movsbl %al, %esi
movq %rbx, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq (%rsp), %rdi
callq hipFree
movq %r14, %rax
addq $40, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size FFT_GPU, .Lfunc_end2-FFT_GPU
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, %rdi
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12Complex_multP15HIP_vector_typeIfLj2EEPKS0_S3_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z12Complex_multP15HIP_vector_typeIfLj2EEPKS0_S3_,@object # @_Z12Complex_multP15HIP_vector_typeIfLj2EEPKS0_S3_
.section .rodata,"a",@progbits
.globl _Z12Complex_multP15HIP_vector_typeIfLj2EEPKS0_S3_
.p2align 3, 0x0
_Z12Complex_multP15HIP_vector_typeIfLj2EEPKS0_S3_:
.quad _Z27__device_stub__Complex_multP15HIP_vector_typeIfLj2EEPKS0_S3_
.size _Z12Complex_multP15HIP_vector_typeIfLj2EEPKS0_S3_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "VIDEO MEM: "
.size .L.str, 12
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz " ms"
.size .L.str.1, 4
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "COPY DATA: "
.size .L.str.2, 12
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "FFT: "
.size .L.str.3, 6
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "cMULT: "
.size .L.str.4, 8
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "IFFT: "
.size .L.str.5, 7
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "COPY FROM VIDEO: "
.size .L.str.6, 18
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z12Complex_multP15HIP_vector_typeIfLj2EEPKS0_S3_"
.size .L__unnamed_1, 50
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section .deplibs,"MS",@llvm_dependent_libraries,1
.ascii "cufft.lib"
.byte 0
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z27__device_stub__Complex_multP15HIP_vector_typeIfLj2EEPKS0_S3_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z12Complex_multP15HIP_vector_typeIfLj2EEPKS0_S3_
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
```
| 7,439 | 6,571 |
342 |
Convert the following CUDA device assembly code to AMD device assembly:
```cudaasm
code for sm_80
Function : _Z13getWordCountsPcPiS0_S_S0_S0_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ;
S2R R0, SR_CTAID.X ;
IMAD.MOV.U32 R7, RZ, RZ, 0x4 ;
ULDC.64 UR6, c[0x0][0x118] ;
S2R R3, SR_TID.X ;
IMAD R0, R0, c[0x0][0x0], R3 ;
IMAD.WIDE.U32 R6, R0, R7, c[0x0][0x170] ;
LDG.E R2, [R6.64] ;
ISETP.GE.AND P0, PT, R2, 0x1, PT ;
@!P0 EXIT ;
ULDC.64 UR4, c[0x0][0x188] ;
IMAD R0, R0, 0xc8, RZ ;
UIADD3 UR4, UP0, UR4, 0x28, URZ ;
IMAD.MOV.U32 R17, RZ, RZ, RZ ;
IMAD.MOV.U32 R14, RZ, RZ, RZ ;
UIADD3.X UR5, URZ, UR5, URZ, UP0, !UPT ;
IMAD.U32 R4, RZ, RZ, UR4 ;
IMAD.U32 R5, RZ, RZ, UR5 ;
SHF.R.S32.HI R3, RZ, 0x1f, R17 ;
IADD3 R2, P0, P1, R17, c[0x0][0x160], R0 ;
IADD3.X R3, R3, c[0x0][0x164], RZ, P0, P1 ;
LDG.E.U8 R9, [R2.64] ;
YIELD ;
BSSY B0, 0x320 ;
IADD3 R8, R9, -0x41, RZ ;
LOP3.LUT R8, R8, 0xff, RZ, 0xc0, !PT ;
ISETP.GT.U32.AND P0, PT, R8, 0x19, PT ;
@!P0 IADD3 R9, R9, 0x20, RZ ;
LOP3.LUT R8, R9.reuse, 0xff, RZ, 0xc0, !PT ;
@!P0 STG.E.U8 [R2.64], R9 ;
LOP3.LUT R10, R9, 0xffff, RZ, 0xc0, !PT ;
ISETP.GT.U32.AND P1, PT, R8, 0x2e, PT ;
LOP3.LUT R12, R10, 0xff, RZ, 0xc0, !PT ;
@P1 BRA 0x280 ;
UMOV UR4, 0x1 ;
IMAD.U32 R9, RZ, RZ, UR4 ;
SHF.L.U64.HI R8, R9, R12, RZ ;
LOP3.LUT P0, RZ, R8, 0x4003, RZ, 0xc0, !PT ;
IMAD.MOV.U32 R8, RZ, RZ, R14 ;
@P0 BRA 0x310 ;
ISETP.NE.AND P0, PT, R14, 0x1, PT ;
IMAD.MOV.U32 R8, RZ, RZ, 0x1 ;
PRMT R9, R10, 0x8880, RZ ;
SEL R18, R18, RZ, !P0 ;
SEL R19, R2, R19, P0 ;
SEL R21, R3, R21, P0 ;
IMAD.IADD R18, R18, 0x1, R9 ;
SEL R23, R2, R23, P0 ;
SEL R25, R3, R25, P0 ;
BSYNC B0 ;
ISETP.NE.AND P0, PT, R8, RZ, PT ;
BSSY B0, 0x1100 ;
IMAD.MOV.U32 R14, RZ, RZ, RZ ;
@!P0 BRA 0x10f0 ;
IMAD.MOV.U32 R14, RZ, RZ, R8 ;
@P1 BRA 0x10f0 ;
IMAD.MOV.U32 R11, RZ, RZ, 0x1 ;
IMAD.MOV.U32 R14, RZ, RZ, R8 ;
SHF.L.U64.HI R12, R11, R12, RZ ;
LOP3.LUT P0, RZ, R12, 0x4003, RZ, 0xc0, !PT ;
@!P0 BRA 0x10f0 ;
IMAD.HI R8, R18, 0x66666667, RZ ;
BSSY B1, 0x4c0 ;
SHF.R.U32.HI R9, RZ, 0x1f, R8 ;
LEA.HI.SX32 R9, R8, R9, 0x1e ;
IMAD.MOV.U32 R8, RZ, RZ, 0x4 ;
IMAD R27, R9, -0xa, R18 ;
IMAD.WIDE R8, R27, R8, c[0x0][0x188] ;
SHF.R.S32.HI R16, RZ, 0x1f, R27 ;
IMAD.MOV.U32 R18, RZ, RZ, R27 ;
IMAD.MOV.U32 R10, RZ, RZ, RZ ;
YIELD ;
ATOMG.E.CAS.STRONG.GPU PT, R10, [R8], R10, R11 ;
ISETP.NE.AND P0, PT, R10, RZ, PT ;
@!P0 BRA 0x460 ;
BSYNC B1 ;
IMAD R11, R18, 0x14, RZ ;
IADD3 R10, P0, R11, c[0x0][0x178], RZ ;
LEA.HI.X.SX32 R11, R11, c[0x0][0x17c], 0x1, P0 ;
LDG.E.U8 R12, [R10.64] ;
ISETP.NE.AND P0, PT, R12, RZ, PT ;
@!P0 BRA 0xf00 ;
LEA R8, P0, R27.reuse, c[0x0][0x180], 0x2 ;
BSSY B1, 0xa90 ;
IMAD.MOV.U32 R15, RZ, RZ, R18 ;
LEA.HI.X R9, R27, c[0x0][0x184], R16, 0x2, P0 ;
ISETP.NE.U32.AND P1, PT, R19, R2, PT ;
IMAD R20, R15, 0x14, RZ ;
YIELD ;
BSSY B2, 0x810 ;
ISETP.NE.AND.EX P1, PT, R21, R3, PT, P1 ;
IMAD.MOV.U32 R26, RZ, RZ, RZ ;
PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ;
IMAD.MOV.U32 R24, RZ, RZ, RZ ;
SHF.R.S32.HI R14, RZ, 0x1f, R20 ;
@!P1 BRA 0x800 ;
IMAD.MOV.U32 R26, RZ, RZ, RZ ;
IMAD.MOV.U32 R24, RZ, RZ, RZ ;
IMAD.MOV.U32 R22, RZ, RZ, 0x1 ;
IMAD.MOV.U32 R12, RZ, RZ, R20 ;
IMAD.MOV.U32 R13, RZ, RZ, R14 ;
IMAD.MOV.U32 R28, RZ, RZ, R23 ;
IMAD.MOV.U32 R11, RZ, RZ, R25 ;
IADD3 R12, P0, R12, c[0x0][0x178], RZ ;
IMAD.MOV.U32 R10, RZ, RZ, R28 ;
IADD3.X R13, R13, c[0x0][0x17c], RZ, P0, !PT ;
LDG.E.U8 R10, [R10.64] ;
LDG.E.U8 R13, [R12.64] ;
PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ;
ISETP.NE.AND P2, PT, R13, R10, PT ;
@P2 BRA 0x800 ;
IADD3 R11, P2, R22, R19, RZ ;
IMAD.MOV.U32 R29, RZ, RZ, R22.reuse ;
SHF.R.S32.HI R10, RZ, 0x1f, R22 ;
ISETP.NE.U32.AND P0, PT, R11, R2, PT ;
IADD3 R26, P4, R26, 0x1, RZ ;
IMAD.X R11, R10, 0x1, R21, P2 ;
IADD3 R28, P2, R22, R23, RZ ;
IADD3 R12, P3, R20, R22, RZ ;
IMAD.X R24, RZ, RZ, R24, P4 ;
ISETP.NE.AND.EX P0, PT, R11, R3, PT, P0 ;
IMAD.X R11, R10, 0x1, R25, P2 ;
IADD3 R22, R22, 0x1, RZ ;
IMAD.X R13, R14, 0x1, R10, P3 ;
@P0 BRA 0x670 ;
PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ;
IMAD.MOV.U32 R26, RZ, RZ, R29 ;
IMAD.MOV.U32 R24, RZ, RZ, R10 ;
BSYNC B2 ;
IADD3 R10, P2, P3, R26, c[0x0][0x178], R20 ;
IMAD.SHL.U32 R20, R27, 0x4, RZ ;
IADD3.X R11, R24, c[0x0][0x17c], R14, P2, P3 ;
LDG.E.U8 R10, [R10.64] ;
SHF.L.U64.HI R16, R27, 0x2, R16 ;
IMAD.MOV.U32 R12, RZ, RZ, 0x1 ;
IADD3 R26, P2, R20, c[0x0][0x188], RZ ;
IMAD.MOV.U32 R13, RZ, RZ, RZ ;
IADD3.X R27, R16, c[0x0][0x18c], RZ, P2, !PT ;
IMAD.MOV.U32 R14, RZ, RZ, RZ ;
ATOMG.E.CAS.STRONG.GPU PT, RZ, [R26], R12, R13 ;
ISETP.NE.OR P0, PT, R10, RZ, P0 ;
@!P0 BREAK B1 ;
@!P0 BRA 0xeb0 ;
LDG.E R27, [R8.64] ;
BSSY B2, 0xa30 ;
ISETP.NE.AND P0, PT, R27, -0x1, PT ;
@!P0 BRA 0xa00 ;
LEA R8, P0, R27, c[0x0][0x188], 0x2 ;
BSSY B3, 0x9f0 ;
SHF.R.S32.HI R16, RZ, 0x1f, R27.reuse ;
IMAD.MOV.U32 R15, RZ, RZ, R27 ;
LEA.HI.X R9, R27, c[0x0][0x18c], R16, 0x2, P0 ;
IMAD.MOV.U32 R10, RZ, RZ, RZ ;
YIELD ;
IMAD.MOV.U32 R11, RZ, RZ, 0x1 ;
ATOMG.E.CAS.STRONG.GPU PT, R10, [R8], R10, R11 ;
ISETP.NE.AND P0, PT, R10, RZ, PT ;
@!P0 BRA 0x980 ;
BSYNC B3 ;
BRA 0xa20 ;
SHF.R.S32.HI R16, RZ, 0x1f, R15.reuse ;
IMAD.MOV.U32 R27, RZ, RZ, R15 ;
BSYNC B2 ;
LEA R8, P0, R27, c[0x0][0x180], 0x2 ;
LEA.HI.X R9, R27, c[0x0][0x184], R16, 0x2, P0 ;
LDG.E R10, [R8.64] ;
ISETP.NE.AND P0, PT, R10, -0x1, PT ;
@P0 BRA 0x560 ;
BSYNC B1 ;
BSSY B1, 0xb10 ;
IMAD.MOV.U32 R10, RZ, RZ, RZ ;
YIELD ;
IMAD.MOV.U32 R11, RZ, RZ, 0x1 ;
ATOMG.E.CAS.STRONG.GPU PT, R10, [R4], R10, R11 ;
ISETP.NE.AND P0, PT, R10, RZ, PT ;
@!P0 BRA 0xaa0 ;
BSYNC B1 ;
BSSY B1, 0xbf0 ;
IMAD.MOV.U32 R13, RZ, RZ, RZ ;
IMAD R12, R13, 0x14, RZ ;
IADD3 R11, R12, 0xc8, RZ ;
IADD3 R10, P0, R11, c[0x0][0x178], RZ ;
LEA.HI.X.SX32 R11, R11, c[0x0][0x17c], 0x1, P0 ;
LDG.E.U8 R10, [R10.64] ;
ISETP.LT.U32.AND P3, PT, R13.reuse, 0xc8, PT ;
IMAD.MOV.U32 R27, RZ, RZ, R13 ;
ISETP.GE.U32.AND P2, PT, R13.reuse, 0xc8, PT ;
IADD3 R13, R13, 0x1, RZ ;
ISETP.NE.AND P0, PT, R10, RZ, PT ;
@P0 BRA P3, 0xb30 ;
BSYNC B1 ;
BSSY B1, 0xe50 ;
@P2 BRA 0xe40 ;
IADD3 R15, R27.reuse, 0xa, RZ ;
IMAD.MOV.U32 R10, RZ, RZ, R8 ;
BSSY B2, 0xde0 ;
IMAD.MOV.U32 R11, RZ, RZ, R9 ;
IMAD.WIDE R8, R27, 0x4, R4 ;
STG.E [R10.64], R15 ;
@!P1 BRA 0xdd0 ;
IADD3 R14, P0, R12.reuse, c[0x0][0x178], RZ ;
IMAD.MOV.U32 R22, RZ, RZ, RZ ;
IMAD.MOV.U32 R16, RZ, RZ, RZ ;
LEA.HI.X.SX32 R29, R12, c[0x0][0x17c], 0x1, P0 ;
IMAD.MOV.U32 R20, RZ, RZ, RZ ;
IMAD.MOV.U32 R10, RZ, RZ, R23 ;
IMAD.MOV.U32 R11, RZ, RZ, R25 ;
LDG.E.U8 R11, [R10.64] ;
IADD3 R12, P0, R16, R14, RZ ;
IADD3 R16, R22, 0x1, RZ ;
IMAD.X R13, R20, 0x1, R29, P0 ;
IADD3 R22, P1, R16, R19, RZ ;
SHF.R.S32.HI R20, RZ, 0x1f, R16 ;
ISETP.NE.U32.AND P0, PT, R22, R2, PT ;
IMAD.X R22, R20, 0x1, R21, P1 ;
IADD3 R10, P1, R16, R23, RZ ;
ISETP.NE.AND.EX P0, PT, R22, R3, PT, P0 ;
IMAD.MOV.U32 R22, RZ, RZ, R16 ;
STG.E.U8 [R12.64+0xc8], R11 ;
IMAD.X R11, R20, 0x1, R25, P1 ;
@P0 BRA 0xcf0 ;
BSYNC B2 ;
IMAD.MOV.U32 R2, RZ, RZ, 0x4 ;
IMAD.MOV.U32 R10, RZ, RZ, 0x1 ;
IMAD.MOV.U32 R11, RZ, RZ, RZ ;
IMAD.WIDE R2, R15, R2, c[0x0][0x168] ;
ATOMG.E.CAS.STRONG.GPU PT, RZ, [R8], R10, R11 ;
STG.E [R2.64], R18 ;
BSYNC B1 ;
IMAD.WIDE R2, R27, 0x4, R4 ;
IMAD.MOV.U32 R8, RZ, RZ, 0x1 ;
IMAD.MOV.U32 R9, RZ, RZ, RZ ;
ATOMG.E.CAS.STRONG.GPU PT, RZ, [R2], R8, R9 ;
IMAD.MOV.U32 R14, RZ, RZ, RZ ;
BRA 0x10f0 ;
IADD3 R2, P0, R20, c[0x0][0x168], RZ ;
IADD3.X R3, R16, c[0x0][0x16c], RZ, P0, !PT ;
RED.E.ADD.STRONG.GPU [R2.64], R12 ;
STG.E [R2.64], R18 ;
BRA 0x10f0 ;
ISETP.NE.U32.AND P0, PT, R19, R2, PT ;
BSSY B1, 0x1080 ;
ISETP.NE.AND.EX P0, PT, R21, R3, PT, P0 ;
@!P0 BRA 0x1070 ;
IMAD.MOV.U32 R24, RZ, RZ, RZ ;
IMAD.MOV.U32 R22, RZ, RZ, RZ ;
IMAD.MOV.U32 R20, RZ, RZ, RZ ;
IMAD.MOV.U32 R12, RZ, RZ, R23 ;
IMAD.MOV.U32 R13, RZ, RZ, R25 ;
LDG.E.U8 R13, [R12.64] ;
IADD3 R14, P0, R22, R10, RZ ;
IADD3 R22, R24, 0x1, RZ ;
IMAD.X R15, R20, 0x1, R11, P0 ;
IADD3 R29, P1, R22, R19, RZ ;
IMAD.MOV.U32 R24, RZ, RZ, R22.reuse ;
SHF.R.S32.HI R20, RZ, 0x1f, R22 ;
ISETP.NE.U32.AND P0, PT, R29, R2, PT ;
IMAD.X R29, R20, 0x1, R21, P1 ;
IADD3 R12, P1, R22, R23, RZ ;
ISETP.NE.AND.EX P0, PT, R29, R3, PT, P0 ;
STG.E.U8 [R14.64], R13 ;
IMAD.X R13, R20, 0x1, R25, P1 ;
@P0 BRA 0xf90 ;
BSYNC B1 ;
LEA R2, P0, R27.reuse, c[0x0][0x168], 0x2 ;
IMAD.MOV.U32 R10, RZ, RZ, 0x1 ;
IMAD.MOV.U32 R11, RZ, RZ, RZ ;
LEA.HI.X R3, R27, c[0x0][0x16c], R16, 0x2, P0 ;
ATOMG.E.CAS.STRONG.GPU PT, RZ, [R8], R10, R11 ;
IMAD.MOV.U32 R14, RZ, RZ, RZ ;
STG.E [R2.64], R18 ;
BSYNC B0 ;
LDG.E R2, [R6.64] ;
IADD3 R17, R17, 0x1, RZ ;
ISETP.GE.AND P0, PT, R17, R2, PT ;
@P0 CALL.REL.NOINC 0x1150 ;
BRA 0x120 ;
EXIT ;
BRA 0x1160;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
```
|
```amdasm
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z13getWordCountsPcPiS0_S_S0_S0_ ; -- Begin function _Z13getWordCountsPcPiS0_S_S0_S0_
.globl _Z13getWordCountsPcPiS0_S_S0_S0_
.p2align 8
.type _Z13getWordCountsPcPiS0_S_S0_S0_,@function
_Z13getWordCountsPcPiS0_S_S0_S0_: ; @_Z13getWordCountsPcPiS0_S_S0_S0_
; %bb.0:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x3c
s_load_b256 s[4:11], s[0:1], 0x0
s_mov_b32 s3, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
v_mov_b32_e32 v2, 0
s_mov_b32 s2, exec_lo
v_lshlrev_b64 v[3:4], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v3, vcc_lo, s8, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s9, v4, vcc_lo
global_load_b32 v0, v[3:4], off
s_waitcnt vmcnt(0)
v_cmpx_lt_i32_e32 0, v0
s_cbranch_execz .LBB0_57
; %bb.1: ; %.lr.ph197
s_load_b128 s[12:15], s[0:1], 0x20
v_mul_lo_u32 v0, 0xc8, v1
v_dual_mov_b32 v1, 1 :: v_dual_mov_b32 v8, v2
s_mov_b32 s1, 0
s_mov_b32 s24, 0
; implicit-def: $vgpr5_vgpr6
; implicit-def: $vgpr7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v0, s0, s4, v0
v_add_co_ci_u32_e64 v20, null, s5, 0, s0
s_waitcnt lgkmcnt(0)
s_add_u32 s4, s14, 40
s_addc_u32 s5, s15, 0
s_add_u32 s22, s6, 40
s_addc_u32 s23, s7, 0
s_add_u32 s8, s10, 0xc8
s_addc_u32 s9, s11, 0
.LBB0_2: ; =>This Loop Header: Depth=1
; Child Loop BB0_17 Depth 2
; Child Loop BB0_20 Depth 2
; Child Loop BB0_22 Depth 3
; Child Loop BB0_29 Depth 3
; Child Loop BB0_37 Depth 2
; Child Loop BB0_39 Depth 2
; Child Loop BB0_43 Depth 2
; Child Loop BB0_52 Depth 2
v_add_co_u32 v9, vcc_lo, v0, s24
v_add_co_ci_u32_e32 v10, vcc_lo, 0, v20, vcc_lo
s_mov_b32 s0, exec_lo
global_load_u8 v12, v[9:10], off
s_waitcnt vmcnt(0)
v_add_nc_u16 v11, v12, 0xffbf
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_and_b32_e32 v11, 0xff, v11
v_cmpx_gt_u16_e32 26, v11
s_cbranch_execz .LBB0_4
; %bb.3: ; in Loop: Header=BB0_2 Depth=1
v_or_b32_e32 v12, 32, v12
global_store_b8 v[9:10], v12, off
.LBB0_4: ; in Loop: Header=BB0_2 Depth=1
s_or_b32 exec_lo, exec_lo, s0
v_and_b32_e32 v11, 0xff, v12
s_mov_b32 s0, 0
s_mov_b32 s2, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_lt_i16_e32 45, v11
s_xor_b32 s2, exec_lo, s2
; %bb.5: ; %LeafBlock275
; in Loop: Header=BB0_2 Depth=1
v_cmp_ne_u16_e32 vcc_lo, 46, v11
s_and_b32 s0, vcc_lo, exec_lo
; %bb.6: ; %Flow304
; in Loop: Header=BB0_2 Depth=1
s_and_not1_saveexec_b32 s2, s2
; %bb.7: ; %LeafBlock
; in Loop: Header=BB0_2 Depth=1
v_sub_nc_u16 v13, v11, 32
s_and_not1_b32 s0, s0, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_lt_u16_e32 vcc_lo, 1, v13
s_and_b32 s16, vcc_lo, exec_lo
s_or_b32 s0, s0, s16
; %bb.8: ; %Flow305
; in Loop: Header=BB0_2 Depth=1
s_or_b32 exec_lo, exec_lo, s2
s_and_saveexec_b32 s2, s0
; %bb.9: ; in Loop: Header=BB0_2 Depth=1
v_cmp_eq_u32_e32 vcc_lo, 1, v8
v_bfe_i32 v12, v12, 0, 8
v_dual_mov_b32 v8, 1 :: v_dual_cndmask_b32 v7, 0, v7
v_dual_cndmask_b32 v6, v10, v6 :: v_dual_cndmask_b32 v5, v9, v5
s_delay_alu instid0(VALU_DEP_2)
v_add_nc_u32_e32 v7, v7, v12
; %bb.10: ; in Loop: Header=BB0_2 Depth=1
s_or_b32 exec_lo, exec_lo, s2
s_delay_alu instid0(VALU_DEP_3)
v_cmp_ne_u32_e32 vcc_lo, 0, v8
v_mov_b32_e32 v8, 0
s_and_saveexec_b32 s25, vcc_lo
s_cbranch_execz .LBB0_56
; %bb.11: ; %NodeBlock282
; in Loop: Header=BB0_2 Depth=1
s_mov_b32 s0, 0
s_mov_b32 s2, exec_lo
; implicit-def: $sgpr16
v_cmpx_lt_i16_e32 45, v11
s_xor_b32 s2, exec_lo, s2
; %bb.12: ; %LeafBlock280
; in Loop: Header=BB0_2 Depth=1
v_cmp_eq_u16_e32 vcc_lo, 46, v11
s_mov_b32 s16, 1
; implicit-def: $vgpr11
s_and_b32 s0, vcc_lo, exec_lo
; %bb.13: ; %Flow300
; in Loop: Header=BB0_2 Depth=1
s_or_saveexec_b32 s2, s2
v_mov_b32_e32 v8, s16
s_xor_b32 exec_lo, exec_lo, s2
; %bb.14: ; %LeafBlock277
; in Loop: Header=BB0_2 Depth=1
v_sub_nc_u16 v8, v11, 32
s_and_not1_b32 s0, s0, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_cmp_gt_u16_e32 vcc_lo, 2, v8
v_mov_b32_e32 v8, 1
s_and_b32 s16, vcc_lo, exec_lo
s_or_b32 s0, s0, s16
; %bb.15: ; %Flow301
; in Loop: Header=BB0_2 Depth=1
s_or_b32 exec_lo, exec_lo, s2
s_and_saveexec_b32 s26, s0
s_cbranch_execz .LBB0_55
; %bb.16: ; in Loop: Header=BB0_2 Depth=1
v_mul_hi_i32 v8, 0x66666667, v7
s_mov_b32 s0, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshrrev_b32_e32 v11, 31, v8
v_ashrrev_i32_e32 v8, 2, v8
v_add_nc_u32_e32 v8, v8, v11
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v8, v8, 10
v_sub_nc_u32_e32 v7, v7, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v8, 31, v7
v_lshlrev_b64 v[11:12], 2, v[7:8]
v_dual_mov_b32 v17, v8 :: v_dual_mov_b32 v16, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v13, vcc_lo, s14, v11
v_add_co_ci_u32_e32 v14, vcc_lo, s15, v12, vcc_lo
.LBB0_17: ; Parent Loop BB0_2 Depth=1
; => This Inner Loop Header: Depth=2
global_atomic_cmpswap_b32 v8, v[13:14], v[1:2], off glc
s_waitcnt vmcnt(0)
v_cmp_ne_u32_e32 vcc_lo, 0, v8
s_or_b32 s0, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s0
s_cbranch_execnz .LBB0_17
; %bb.18: ; in Loop: Header=BB0_2 Depth=1
s_or_b32 exec_lo, exec_lo, s0
v_mul_i32_i24_e32 v8, 20, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v15, 31, v8
v_add_co_u32 v18, vcc_lo, s10, v8
v_add_co_ci_u32_e32 v19, vcc_lo, s11, v15, vcc_lo
global_load_u8 v8, v[18:19], off
s_waitcnt vmcnt(0)
v_cmp_ne_u16_e32 vcc_lo, 0, v8
; implicit-def: $vgpr8
s_and_saveexec_b32 s0, vcc_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s27, exec_lo, s0
s_cbranch_execz .LBB0_49
; %bb.19: ; %.preheader164
; in Loop: Header=BB0_2 Depth=1
v_add_co_u32 v13, vcc_lo, s12, v11
v_cmp_ne_u64_e64 s0, v[5:6], v[9:10]
v_add_co_ci_u32_e32 v14, vcc_lo, s13, v12, vcc_lo
v_mov_b32_e32 v15, v7
s_mov_b32 s2, 0
; implicit-def: $sgpr18
; implicit-def: $sgpr19
.LBB0_20: ; Parent Loop BB0_2 Depth=1
; => This Loop Header: Depth=2
; Child Loop BB0_22 Depth 3
; Child Loop BB0_29 Depth 3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_4)
v_mul_lo_u32 v8, v15, 20
v_dual_mov_b32 v11, v16 :: v_dual_mov_b32 v12, v17
v_mov_b32_e32 v16, 0
v_mov_b32_e32 v17, 0
s_mov_b32 s16, 0
v_ashrrev_i32_e32 v18, 31, v8
v_add_co_u32 v8, vcc_lo, s10, v8
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v18, vcc_lo, s11, v18, vcc_lo
s_and_saveexec_b32 s20, s0
s_cbranch_execz .LBB0_26
; %bb.21: ; %.lr.ph.preheader
; in Loop: Header=BB0_20 Depth=2
s_mov_b64 s[16:17], 0
s_mov_b32 s21, 0
; implicit-def: $sgpr28
; implicit-def: $sgpr30
; implicit-def: $sgpr29
.LBB0_22: ; %.lr.ph
; Parent Loop BB0_2 Depth=1
; Parent Loop BB0_20 Depth=2
; => This Inner Loop Header: Depth=3
v_add_co_u32 v16, vcc_lo, v8, s16
v_add_co_ci_u32_e32 v17, vcc_lo, s17, v18, vcc_lo
v_add_co_u32 v21, vcc_lo, v5, s16
v_add_co_ci_u32_e32 v22, vcc_lo, s17, v6, vcc_lo
s_or_b32 s29, s29, exec_lo
global_load_u8 v16, v[16:17], off
flat_load_u8 v17, v[21:22]
s_or_b32 s30, s30, exec_lo
s_waitcnt vmcnt(0) lgkmcnt(0)
v_cmp_eq_u16_e32 vcc_lo, v16, v17
v_dual_mov_b32 v16, s16 :: v_dual_mov_b32 v17, s17
s_and_saveexec_b32 s31, vcc_lo
; %bb.23: ; in Loop: Header=BB0_22 Depth=3
s_add_u32 s16, s16, 1
s_addc_u32 s17, s17, 0
v_add_co_u32 v16, vcc_lo, v5, s16
v_add_co_ci_u32_e32 v17, vcc_lo, s17, v6, vcc_lo
s_and_not1_b32 s30, s30, exec_lo
s_and_not1_b32 s29, s29, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_cmp_eq_u64_e32 vcc_lo, v[16:17], v[9:10]
v_dual_mov_b32 v16, s16 :: v_dual_mov_b32 v17, s17
s_and_b32 s33, vcc_lo, exec_lo
s_or_b32 s30, s30, s33
; %bb.24: ; %Flow291
; in Loop: Header=BB0_22 Depth=3
s_or_b32 exec_lo, exec_lo, s31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s31, exec_lo, s30
s_or_b32 s21, s31, s21
s_and_not1_b32 s28, s28, exec_lo
s_and_b32 s31, s29, exec_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 s28, s28, s31
s_and_not1_b32 exec_lo, exec_lo, s21
s_cbranch_execnz .LBB0_22
; %bb.25: ; %Flow292
; in Loop: Header=BB0_20 Depth=2
s_or_b32 exec_lo, exec_lo, s21
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 s16, s28, exec_lo
.LBB0_26: ; %Flow293
; in Loop: Header=BB0_20 Depth=2
s_or_b32 exec_lo, exec_lo, s20
v_add_co_u32 v16, vcc_lo, v8, v16
v_add_co_ci_u32_e32 v17, vcc_lo, v18, v17, vcc_lo
v_lshlrev_b64 v[18:19], 2, v[11:12]
s_mov_b32 s17, -1
s_or_b32 s19, s19, exec_lo
global_load_u8 v8, v[16:17], off
v_dual_mov_b32 v16, v2 :: v_dual_mov_b32 v17, v1
v_add_co_u32 v18, vcc_lo, s14, v18
v_add_co_ci_u32_e32 v19, vcc_lo, s15, v19, vcc_lo
global_atomic_cmpswap_b32 v[18:19], v[16:17], off
; implicit-def: $vgpr16_vgpr17
s_waitcnt vmcnt(0)
v_cmp_ne_u16_e32 vcc_lo, 0, v8
s_or_b32 s20, s16, vcc_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s16, s20
s_cbranch_execz .LBB0_34
; %bb.27: ; in Loop: Header=BB0_20 Depth=2
global_load_b32 v18, v[13:14], off
s_mov_b32 s17, exec_lo
; implicit-def: $vgpr16_vgpr17
s_waitcnt vmcnt(0)
v_cmpx_ne_u32_e32 -1, v18
s_xor_b32 s17, exec_lo, s17
s_cbranch_execz .LBB0_31
; %bb.28: ; %.preheader
; in Loop: Header=BB0_20 Depth=2
v_ashrrev_i32_e32 v19, 31, v18
v_mov_b32_e32 v16, v18
s_mov_b32 s20, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mov_b32_e32 v17, v19
v_lshlrev_b64 v[13:14], 2, v[18:19]
v_add_co_u32 v13, vcc_lo, s14, v13
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v14, vcc_lo, s15, v14, vcc_lo
.LBB0_29: ; Parent Loop BB0_2 Depth=1
; Parent Loop BB0_20 Depth=2
; => This Inner Loop Header: Depth=3
global_atomic_cmpswap_b32 v8, v[13:14], v[1:2], off glc
s_waitcnt vmcnt(0)
v_cmp_ne_u32_e32 vcc_lo, 0, v8
s_or_b32 s20, vcc_lo, s20
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s20
s_cbranch_execnz .LBB0_29
; %bb.30: ; %Flow289
; in Loop: Header=BB0_20 Depth=2
s_or_b32 exec_lo, exec_lo, s20
; implicit-def: $vgpr15
.LBB0_31: ; %Flow290
; in Loop: Header=BB0_20 Depth=2
s_and_not1_saveexec_b32 s17, s17
; %bb.32: ; %..loopexit_crit_edge
; in Loop: Header=BB0_20 Depth=2
v_ashrrev_i32_e32 v16, 31, v15
s_delay_alu instid0(VALU_DEP_1)
v_dual_mov_b32 v18, v15 :: v_dual_mov_b32 v17, v16
v_mov_b32_e32 v16, v15
; %bb.33: ; %.loopexit
; in Loop: Header=BB0_20 Depth=2
s_or_b32 exec_lo, exec_lo, s17
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[13:14], 2, v[16:17]
v_mov_b32_e32 v15, v18
s_and_not1_b32 s19, s19, exec_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v13, vcc_lo, s12, v13
v_add_co_ci_u32_e32 v14, vcc_lo, s13, v14, vcc_lo
global_load_b32 v8, v[13:14], off
s_waitcnt vmcnt(0)
v_cmp_eq_u32_e32 vcc_lo, -1, v8
s_or_not1_b32 s17, vcc_lo, exec_lo
.LBB0_34: ; %Flow294
; in Loop: Header=BB0_20 Depth=2
s_or_b32 exec_lo, exec_lo, s16
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s16, exec_lo, s17
s_or_b32 s2, s16, s2
s_and_not1_b32 s16, s18, exec_lo
s_and_b32 s17, s19, exec_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 s18, s16, s17
s_and_not1_b32 exec_lo, exec_lo, s2
s_cbranch_execnz .LBB0_20
; %bb.35: ; %loop.exit.guard
; in Loop: Header=BB0_2 Depth=1
s_or_b32 exec_lo, exec_lo, s2
s_xor_b32 s16, s18, -1
; implicit-def: $sgpr2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_saveexec_b32 s17, s16
s_xor_b32 s28, exec_lo, s17
s_cbranch_execz .LBB0_46
; %bb.36: ; %.critedge.preheader
; in Loop: Header=BB0_2 Depth=1
s_mov_b32 s2, 0
.LBB0_37: ; %.critedge
; Parent Loop BB0_2 Depth=1
; => This Inner Loop Header: Depth=2
global_atomic_cmpswap_b32 v8, v2, v[1:2], s[4:5] glc
s_waitcnt vmcnt(0)
v_cmp_ne_u32_e32 vcc_lo, 0, v8
s_or_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s2
s_cbranch_execnz .LBB0_37
; %bb.38: ; %.preheader163.preheader
; in Loop: Header=BB0_2 Depth=1
s_or_b32 exec_lo, exec_lo, s2
s_mov_b32 s16, -1
s_mov_b64 s[20:21], s[8:9]
.LBB0_39: ; %.preheader163
; Parent Loop BB0_2 Depth=1
; => This Inner Loop Header: Depth=2
global_load_u8 v8, v2, s[20:21]
s_add_i32 s16, s16, 1
s_mov_b64 s[18:19], s[20:21]
s_cmpk_lt_u32 s16, 0xc8
s_cselect_b32 s2, -1, 0
s_waitcnt vmcnt(0)
v_cmp_ne_u16_e32 vcc_lo, 0, v8
s_and_b32 s17, s2, vcc_lo
s_add_u32 s20, s18, 20
s_addc_u32 s21, s19, 0
s_and_b32 vcc_lo, exec_lo, s17
s_cbranch_vccnz .LBB0_39
; %bb.40: ; in Loop: Header=BB0_2 Depth=1
s_mov_b64 s[20:21], 0xd2
s_and_not1_b32 vcc_lo, exec_lo, s2
s_cbranch_vccnz .LBB0_45
; %bb.41: ; in Loop: Header=BB0_2 Depth=1
s_add_i32 s2, s16, 10
s_delay_alu instid0(SALU_CYCLE_1)
v_mov_b32_e32 v8, s2
global_store_b32 v[13:14], v8, off
s_and_saveexec_b32 s17, s0
s_cbranch_execz .LBB0_44
; %bb.42: ; %.lr.ph185.preheader
; in Loop: Header=BB0_2 Depth=1
v_dual_mov_b32 v14, v6 :: v_dual_mov_b32 v13, v5
s_mov_b32 s0, 0
.LBB0_43: ; %.lr.ph185
; Parent Loop BB0_2 Depth=1
; => This Inner Loop Header: Depth=2
flat_load_u8 v8, v[13:14]
v_add_co_u32 v13, vcc_lo, v13, 1
v_add_co_ci_u32_e32 v14, vcc_lo, 0, v14, vcc_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmp_eq_u64_e32 vcc_lo, v[13:14], v[9:10]
s_waitcnt vmcnt(0) lgkmcnt(0)
global_store_b8 v2, v8, s[18:19]
s_add_u32 s18, s18, 1
s_addc_u32 s19, s19, 0
s_or_b32 s0, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s0
s_cbranch_execnz .LBB0_43
.LBB0_44: ; %Flow285
; in Loop: Header=BB0_2 Depth=1
s_or_b32 exec_lo, exec_lo, s17
s_mov_b32 s17, s3
v_dual_mov_b32 v8, v2 :: v_dual_mov_b32 v9, v1
s_lshl_b64 s[16:17], s[16:17], 2
s_mov_b64 s[20:21], s[2:3]
s_add_u32 s18, s4, s16
s_addc_u32 s19, s5, s17
s_add_u32 s16, s22, s16
global_atomic_cmpswap_b32 v2, v[8:9], s[18:19]
s_addc_u32 s17, s23, s17
global_store_b32 v2, v7, s[16:17]
.LBB0_45: ; %._crit_edge205
; in Loop: Header=BB0_2 Depth=1
s_lshl_b64 s[16:17], s[20:21], 2
v_dual_mov_b32 v8, v2 :: v_dual_mov_b32 v9, v1
s_add_u32 s16, s14, s16
s_addc_u32 s17, s15, s17
s_mov_b32 s2, 0
global_atomic_cmpswap_b32 v2, v[8:9], s[16:17]
.LBB0_46: ; %Flow287
; in Loop: Header=BB0_2 Depth=1
s_or_saveexec_b32 s0, s28
v_mov_b32_e32 v8, s2
s_xor_b32 exec_lo, exec_lo, s0
s_cbranch_execz .LBB0_48
; %bb.47: ; in Loop: Header=BB0_2 Depth=1
v_lshlrev_b64 v[8:9], 2, v[11:12]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v10, vcc_lo, s6, v8
v_add_co_ci_u32_e32 v11, vcc_lo, s7, v9, vcc_lo
v_mov_b32_e32 v8, 0
global_atomic_add_u32 v[10:11], v1, off
global_store_b32 v[10:11], v7, off
.LBB0_48: ; %Flow288
; in Loop: Header=BB0_2 Depth=1
s_or_b32 exec_lo, exec_lo, s0
; implicit-def: $vgpr13_vgpr14
; implicit-def: $vgpr11_vgpr12
; implicit-def: $vgpr9_vgpr10
; implicit-def: $vgpr18_vgpr19
.LBB0_49: ; %Flow298
; in Loop: Header=BB0_2 Depth=1
s_and_not1_saveexec_b32 s2, s27
s_cbranch_execz .LBB0_54
; %bb.50: ; %.preheader162
; in Loop: Header=BB0_2 Depth=1
s_mov_b32 s16, exec_lo
v_cmpx_ne_u64_e64 v[5:6], v[9:10]
s_cbranch_execz .LBB0_53
; %bb.51: ; %.lr.ph189.preheader
; in Loop: Header=BB0_2 Depth=1
v_dual_mov_b32 v16, v6 :: v_dual_mov_b32 v15, v5
s_mov_b32 s17, 0
.LBB0_52: ; %.lr.ph189
; Parent Loop BB0_2 Depth=1
; => This Inner Loop Header: Depth=2
flat_load_u8 v8, v[15:16]
v_add_co_u32 v15, vcc_lo, v15, 1
v_add_co_ci_u32_e32 v16, vcc_lo, 0, v16, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
v_cmp_eq_u64_e32 vcc_lo, v[15:16], v[9:10]
s_or_b32 s17, vcc_lo, s17
s_waitcnt vmcnt(0) lgkmcnt(0)
global_store_b8 v[18:19], v8, off
v_add_co_u32 v18, s0, v18, 1
v_add_co_ci_u32_e64 v19, s0, 0, v19, s0
s_and_not1_b32 exec_lo, exec_lo, s17
s_cbranch_execnz .LBB0_52
.LBB0_53: ; %Flow296
; in Loop: Header=BB0_2 Depth=1
s_or_b32 exec_lo, exec_lo, s16
v_dual_mov_b32 v8, 0 :: v_dual_mov_b32 v9, v1
global_atomic_cmpswap_b32 v[13:14], v[8:9], off
v_add_co_u32 v9, vcc_lo, s6, v11
v_add_co_ci_u32_e32 v10, vcc_lo, s7, v12, vcc_lo
global_store_b32 v[9:10], v7, off
.LBB0_54: ; %Flow299
; in Loop: Header=BB0_2 Depth=1
s_or_b32 exec_lo, exec_lo, s2
.LBB0_55: ; %Flow302
; in Loop: Header=BB0_2 Depth=1
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s26
.LBB0_56: ; %Flow303
; in Loop: Header=BB0_2 Depth=1
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s25
global_load_b32 v9, v[3:4], off
s_add_i32 s24, s24, 1
s_waitcnt vmcnt(0)
v_cmp_ge_i32_e32 vcc_lo, s24, v9
s_or_b32 s1, vcc_lo, s1
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s1
s_cbranch_execnz .LBB0_2
.LBB0_57: ; %._crit_edge198
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13getWordCountsPcPiS0_S_S0_S0_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 304
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 23
.amdhsa_next_free_sgpr 34
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z13getWordCountsPcPiS0_S_S0_S0_, .Lfunc_end0-_Z13getWordCountsPcPiS0_S_S0_S0_
; -- End function
.section .AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1864
; NumSgprs: 36
; NumVgprs: 23
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 4
; VGPRBlocks: 2
; NumSGPRsForWavesPerEU: 36
; NumVGPRsForWavesPerEU: 23
; Occupancy: 16
; WaveLimiterHint : 1
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object ; @__hip_cuid_
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0 ; 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 40
.size: 8
.value_kind: global_buffer
- .offset: 48
.size: 4
.value_kind: hidden_block_count_x
- .offset: 52
.size: 4
.value_kind: hidden_block_count_y
- .offset: 56
.size: 4
.value_kind: hidden_block_count_z
- .offset: 60
.size: 2
.value_kind: hidden_group_size_x
- .offset: 62
.size: 2
.value_kind: hidden_group_size_y
- .offset: 64
.size: 2
.value_kind: hidden_group_size_z
- .offset: 66
.size: 2
.value_kind: hidden_remainder_x
- .offset: 68
.size: 2
.value_kind: hidden_remainder_y
- .offset: 70
.size: 2
.value_kind: hidden_remainder_z
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 112
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 304
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13getWordCountsPcPiS0_S_S0_S0_
.private_segment_fixed_size: 0
.sgpr_count: 36
.sgpr_spill_count: 0
.symbol: _Z13getWordCountsPcPiS0_S_S0_S0_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 23
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
```
| 5,567 | 11,165 |
343 |
Convert the following CUDA host assembly code to AMD host assembly:
```cudaasm
.file "tmpxft_001ae296_00000000-6_p5.cudafe1.cpp"
.text
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z46__device_stub__Z13getWordCountsPcPiS0_S_S0_S0_PcPiS0_S_S0_S0_
.type _Z46__device_stub__Z13getWordCountsPcPiS0_S_S0_S0_PcPiS0_S_S0_S0_, @function
_Z46__device_stub__Z13getWordCountsPcPiS0_S_S0_S0_PcPiS0_S_S0_S0_:
.LFB2082:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movq %r8, 8(%rsp)
movq %r9, (%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
movq %rsp, %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z13getWordCountsPcPiS0_S_S0_S0_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z46__device_stub__Z13getWordCountsPcPiS0_S_S0_S0_PcPiS0_S_S0_S0_, .-_Z46__device_stub__Z13getWordCountsPcPiS0_S_S0_S0_PcPiS0_S_S0_S0_
.globl _Z13getWordCountsPcPiS0_S_S0_S0_
.type _Z13getWordCountsPcPiS0_S_S0_S0_, @function
_Z13getWordCountsPcPiS0_S_S0_S0_:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z46__device_stub__Z13getWordCountsPcPiS0_S_S0_S0_PcPiS0_S_S0_S0_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z13getWordCountsPcPiS0_S_S0_S0_, .-_Z13getWordCountsPcPiS0_S_S0_S0_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "\nAttempting to open %s"
.LC1:
.string "r"
.LC2:
.string "failed to open sample.txt"
.LC3:
.string "%s"
.LC4:
.string "%s\n"
.LC5:
.string "\nNo Of Words : \n"
.LC6:
.string "%s:[%d]\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $104, %rsp
.cfi_def_cfa_offset 160
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
movl $10, %edi
call malloc@PLT
movq %rax, %r12
movl $2000, %edi
call malloc@PLT
movq %rax, %r14
movl $800, %edi
call malloc@PLT
movq %rax, (%rsp)
movl $40, %edi
call malloc@PLT
movq %rax, %r15
movl $4000, %edi
call malloc@PLT
movq %rax, 8(%rsp)
leaq 16(%rsp), %rdi
movl $2000, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $800, %esi
call cudaMalloc@PLT
leaq 32(%rsp), %rdi
movl $40, %esi
call cudaMalloc@PLT
leaq 40(%rsp), %rdi
movl $4000, %esi
call cudaMalloc@PLT
leaq 48(%rsp), %rdi
movl $800, %esi
call cudaMalloc@PLT
leaq 56(%rsp), %rdi
movl $800, %esi
call cudaMalloc@PLT
movl $800, %edx
movl $0, %esi
movq 24(%rsp), %rdi
call cudaMemset@PLT
movl $4000, %edx
movl $0, %esi
movq 40(%rsp), %rdi
call cudaMemset@PLT
movl $800, %edx
movl $-1, %esi
movq 48(%rsp), %rdi
call cudaMemset@PLT
movl $800, %edx
movl $0, %esi
movq 56(%rsp), %rdi
call cudaMemset@PLT
movl $0, %ebp
movl $0, %r13d
jmp .L12
.L14:
movq %r12, %rdx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC1(%rip), %rsi
movq %r12, %rdi
call fopen@PLT
movq %rax, %rbx
testq %rax, %rax
je .L24
movl $2000, %esi
cmpq %rsi, %rbp
cmovnb %rbp, %rsi
subq %rbp, %rsi
leaq (%r14,%rbp), %rdi
movq %rax, %r8
movl $1, %ecx
movl $200, %edx
call __fread_chk@PLT
movq %rbx, %rdi
call ftell@PLT
movl %eax, (%r15,%r13,4)
movq %rbx, %rdi
call fclose@PLT
addq $1, %r13
addq $200, %rbp
.L12:
movq %r12, %rsi
leaq .LC3(%rip), %rdi
movl $0, %eax
call __isoc23_scanf@PLT
cmpl $-1, %eax
jne .L14
testl %r13d, %r13d
jle .L15
movslq %r13d, %rax
leaq (%rax,%rax,4), %rax
leaq (%rax,%rax,4), %rax
leaq (%r14,%rax,8), %r12
movq %r14, %rbx
leaq .LC4(%rip), %rbp
.L16:
movq %rbx, %rdx
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $200, %rbx
cmpq %r12, %rbx
jne .L16
.L15:
movl $1, %ecx
movl $2000, %edx
movq %r14, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $40, %edx
movq %r15, %rsi
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
movl %r13d, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 76(%rsp), %rdx
movl $1, %ecx
movq 64(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L25
.L17:
call cudaThreadSynchronize@PLT
movl $2, %ecx
movl $800, %edx
movq 24(%rsp), %rsi
movq (%rsp), %rbp
movq %rbp, %rdi
call cudaMemcpy@PLT
movl $2, %ecx
movl $4000, %edx
movq 40(%rsp), %rsi
movq 8(%rsp), %rbx
movq %rbx, %rdi
call cudaMemcpy@PLT
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 4000(%rbx), %r12
leaq .LC6(%rip), %r13
jmp .L19
.L24:
leaq .LC2(%rip), %rdi
call perror@PLT
movl $0, %edi
call exit@PLT
.L25:
movq 56(%rsp), %r9
movq 48(%rsp), %r8
movq 40(%rsp), %rcx
movq 32(%rsp), %rdx
movq 24(%rsp), %rsi
movq 16(%rsp), %rdi
call _Z46__device_stub__Z13getWordCountsPcPiS0_S_S0_S0_PcPiS0_S_S0_S0_
jmp .L17
.L18:
addq $20, %rbx
addq $4, %rbp
cmpq %r12, %rbx
je .L26
.L19:
cmpb $0, (%rbx)
je .L18
movl 0(%rbp), %ecx
movq %rbx, %rdx
movq %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L18
.L26:
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
movq %r14, %rdi
call free@PLT
movq (%rsp), %rdi
call free@PLT
movq 8(%rsp), %rdi
call free@PLT
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L27
movl $0, %eax
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L27:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC7:
.string "_Z13getWordCountsPcPiS0_S_S0_S0_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _Z13getWordCountsPcPiS0_S_S0_S0_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
```
|
```amdasm
.text
.file "p5.hip"
.globl _Z28__device_stub__getWordCountsPcPiS0_S_S0_S0_ # -- Begin function _Z28__device_stub__getWordCountsPcPiS0_S_S0_S0_
.type _Z28__device_stub__getWordCountsPcPiS0_S_S0_S0_,@function
_Z28__device_stub__getWordCountsPcPiS0_S_S0_S0_: # @_Z28__device_stub__getWordCountsPcPiS0_S_S0_S0_
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $144, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 56(%rsp), %rax
movq %rdi, (%rax)
leaq 48(%rsp), %rdi
movq %rsi, (%rdi)
leaq 40(%rsp), %rsi
movq %rdx, (%rsi)
leaq 32(%rsp), %rdx
movq %rcx, (%rdx)
leaq 24(%rsp), %rcx
movq %r8, (%rcx)
leaq 16(%rsp), %r8
movq %r9, (%r8)
leaq 96(%rsp), %rbx
movq %rax, (%rbx)
movq %rdi, 8(%rbx)
movq %rsi, 16(%rbx)
movq %rdx, 24(%rbx)
movq %rcx, 32(%rbx)
movq %r8, 40(%rbx)
leaq 80(%rsp), %r14
leaq 64(%rsp), %r15
leaq 8(%rsp), %r12
movq %rsp, %r13
movq %r14, %rdi
movq %r15, %rsi
movq %r12, %rdx
movq %r13, %rcx
callq __hipPopCallConfiguration
movq (%r14), %rsi
movl 8(%r14), %edx
movq (%r15), %rcx
movl 8(%r15), %r8d
movl $_Z13getWordCountsPcPiS0_S_S0_S0_, %edi
movq %rbx, %r9
pushq (%r13)
.cfi_adjust_cfa_offset 8
pushq (%r12)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $160, %rsp
.cfi_adjust_cfa_offset -160
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z28__device_stub__getWordCountsPcPiS0_S_S0_S0_, .Lfunc_end0-_Z28__device_stub__getWordCountsPcPiS0_S_S0_S0_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $72, %rsp
.cfi_def_cfa_offset 128
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movabsq $4294967296, %r15 # imm = 0x100000000
movl $10, %edi
callq malloc
movq %rax, %rbp
movl $2000, %edi # imm = 0x7D0
callq malloc
movq %rax, 16(%rsp) # 8-byte Spill
movl $800, %edi # imm = 0x320
callq malloc
movq %rax, %r14
movl $40, %edi
callq malloc
movq %rax, %r13
movl $4000, %edi # imm = 0xFA0
callq malloc
movq %rax, 56(%rsp) # 8-byte Spill
leaq 32(%rsp), %rdi
movl $2000, %esi # imm = 0x7D0
callq hipMalloc
leaq 8(%rsp), %rdi
movl $800, %esi # imm = 0x320
callq hipMalloc
leaq 48(%rsp), %rdi
movl $40, %esi
callq hipMalloc
leaq 24(%rsp), %rbx
movl $4000, %esi # imm = 0xFA0
movq %rbx, %rdi
callq hipMalloc
leaq 64(%rsp), %r12
movl $800, %esi # imm = 0x320
movq %r12, %rdi
callq hipMalloc
leaq 40(%rsp), %rdi
movl $800, %esi # imm = 0x320
callq hipMalloc
leaq 8(%rsp), %rax
movq (%rax), %rdi
movl $800, %edx # imm = 0x320
xorl %esi, %esi
callq hipMemset
movq (%rbx), %rdi
movl $4000, %edx # imm = 0xFA0
xorl %esi, %esi
callq hipMemset
movq (%r12), %rdi
movl $800, %edx # imm = 0x320
movl $-1, %esi
callq hipMemset
leaq 40(%rsp), %rax
movq (%rax), %rdi
movl $800, %edx # imm = 0x320
xorl %esi, %esi
callq hipMemset
movl $.L.str, %edi
movq %rbp, %rsi
xorl %eax, %eax
callq __isoc23_scanf
movq %r15, %rbx
cmpl $-1, %eax
movq 16(%rsp), %rsi # 8-byte Reload
je .LBB1_8
# %bb.1: # %.lr.ph.preheader
movq %rsi, %rbx
xorl %r12d, %r12d
.LBB1_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl $.L.str.1, %edi
movq %rbp, %rsi
xorl %eax, %eax
callq printf
movl $.L.str.2, %esi
movq %rbp, %rdi
callq fopen
testq %rax, %rax
je .LBB1_15
# %bb.3: # in Loop: Header=BB1_2 Depth=1
movq %rax, %r15
movl $200, %esi
movl $1, %edx
movq %rbx, %rdi
movq %rax, %rcx
callq fread
movq %r15, %rdi
callq ftell
movl %eax, (%r13,%r12,4)
movq %r15, %rdi
callq fclose
incq %r12
movl $.L.str, %edi
movq %rbp, %rsi
xorl %eax, %eax
callq __isoc23_scanf
addq $200, %rbx
cmpl $-1, %eax
jne .LBB1_2
# %bb.4: # %.preheader
movabsq $4294967296, %r15 # imm = 0x100000000
movq %r15, %rbx
testl %r12d, %r12d
movq 16(%rsp), %rsi # 8-byte Reload
je .LBB1_8
# %bb.5: # %.lr.ph50.preheader
movl %r12d, %ebp
movq %rsi, %rbx
.LBB1_6: # %.lr.ph50
# =>This Inner Loop Header: Depth=1
movq %rbx, %rdi
callq puts@PLT
addq $200, %rbx
decl %ebp
jne .LBB1_6
# %bb.7: # %._crit_edge.loopexit
movl %r12d, %ebx
movabsq $4294967296, %r15 # imm = 0x100000000
orq %r15, %rbx
movq 16(%rsp), %rsi # 8-byte Reload
.LBB1_8: # %._crit_edge
movq 32(%rsp), %rdi
movl $2000, %edx # imm = 0x7D0
movl $1, %ecx
movq %rsi, %r12
callq hipMemcpy
movq 48(%rsp), %rdi
movl $40, %edx
movq %r13, %rsi
movl $1, %ecx
callq hipMemcpy
incq %r15
movq %r15, %rdi
movl $1, %esi
movq %rbx, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_10
# %bb.9:
movq 32(%rsp), %rdi
movq 8(%rsp), %rsi
movq 48(%rsp), %rdx
movq 24(%rsp), %rcx
movq 64(%rsp), %r8
movq 40(%rsp), %r9
callq _Z28__device_stub__getWordCountsPcPiS0_S_S0_S0_
.LBB1_10:
callq hipDeviceSynchronize
movq 8(%rsp), %rsi
movl $800, %edx # imm = 0x320
movq %r14, %rdi
movl $2, %ecx
callq hipMemcpy
movq 24(%rsp), %rsi
movl $4000, %edx # imm = 0xFA0
movq 56(%rsp), %r13 # 8-byte Reload
movq %r13, %rdi
movl $2, %ecx
callq hipMemcpy
movl $.Lstr, %edi
callq puts@PLT
movq %r13, %rbx
xorl %r15d, %r15d
.LBB1_11: # =>This Inner Loop Header: Depth=1
cmpb $0, (%rbx)
je .LBB1_13
# %bb.12: # in Loop: Header=BB1_11 Depth=1
movl (%r14,%r15,4), %edx
movl $.L.str.6, %edi
movq %rbx, %rsi
xorl %eax, %eax
callq printf
.LBB1_13: # in Loop: Header=BB1_11 Depth=1
incq %r15
addq $20, %rbx
cmpq $200, %r15
jne .LBB1_11
# %bb.14:
movq 32(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
movq %r12, %rdi
callq free
movq %r14, %rdi
callq free
movq %r13, %rdi
callq free
xorl %eax, %eax
addq $72, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB1_15:
.cfi_def_cfa_offset 128
movl $.L.str.3, %edi
callq perror
xorl %edi, %edi
callq exit
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, %rdi
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13getWordCountsPcPiS0_S_S0_S0_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z13getWordCountsPcPiS0_S_S0_S0_,@object # @_Z13getWordCountsPcPiS0_S_S0_S0_
.section .rodata,"a",@progbits
.globl _Z13getWordCountsPcPiS0_S_S0_S0_
.p2align 3, 0x0
_Z13getWordCountsPcPiS0_S_S0_S0_:
.quad _Z28__device_stub__getWordCountsPcPiS0_S_S0_S0_
.size _Z13getWordCountsPcPiS0_S_S0_S0_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%s"
.size .L.str, 3
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "\nAttempting to open %s"
.size .L.str.1, 23
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "r"
.size .L.str.2, 2
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "failed to open sample.txt"
.size .L.str.3, 26
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "%s:[%d]\n"
.size .L.str.6, 9
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z13getWordCountsPcPiS0_S_S0_S0_"
.size .L__unnamed_1, 33
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "\nNo Of Words : "
.size .Lstr, 16
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z28__device_stub__getWordCountsPcPiS0_S_S0_S0_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z13getWordCountsPcPiS0_S_S0_S0_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
```
| 4,652 | 5,266 |
348 |
Convert the following CUDA device assembly code to AMD device assembly:
```cudaasm
code for sm_80
Function : _Z34naive_normalized_cross_correlationPfPhS0_iiiiiiif
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ;
S2R R0, SR_CTAID.X ;
S2R R3, SR_TID.X ;
S2R R2, SR_CTAID.Y ;
S2R R5, SR_TID.Y ;
IMAD R0, R0, c[0x0][0x0], R3 ;
ISETP.GE.AND P0, PT, R0, c[0x0][0x17c], PT ;
IMAD R3, R2, c[0x0][0x4], R5 ;
ISETP.GE.OR P0, PT, R3, c[0x0][0x178], P0 ;
@P0 EXIT ;
IMAD.MOV R2, RZ, RZ, -c[0x0][0x180] ;
ULDC.64 UR8, c[0x0][0x118] ;
IMAD.MOV R22, RZ, RZ, -c[0x0][0x188] ;
IMAD.MOV.U32 R12, RZ, RZ, RZ ;
ISETP.GT.AND P1, PT, R2, c[0x0][0x180], PT ;
ISETP.GT.OR P0, PT, R22, c[0x0][0x188], P1 ;
@P0 BRA 0x720 ;
IMAD.MOV.U32 R17, RZ, RZ, c[0x0][0x188] ;
IMNMX R18, R22, c[0x0][0x188], !PT ;
ULDC.64 UR6, c[0x0][0x178] ;
IADD3 R4, R0, -c[0x0][0x188], RZ ;
UIADD3 UR4, UR7, -0x1, URZ ;
IADD3 R21, -R17.reuse, 0x1, RZ ;
IMAD.MOV.U32 R12, RZ, RZ, RZ ;
IADD3 R19, -R17, 0x2, RZ ;
IMAD.MOV.U32 R20, RZ, RZ, R2 ;
IADD3 R18, R18, c[0x0][0x188], RZ ;
IMAD.IADD R5, R0.reuse, 0x1, R21 ;
IMNMX R4, RZ, R4, !PT ;
IMAD.IADD R6, R0, 0x1, R19 ;
IADD3 R15, R18, 0x1, RZ ;
UIADD3 UR5, UR6, -0x1, URZ ;
IMNMX R5, RZ, R5, !PT ;
IMNMX R6, RZ, R6, !PT ;
IADD3 R17, -R17, 0x3, RZ ;
IMNMX R16, R4, UR4, PT ;
LOP3.LUT R15, R15, 0x3, RZ, 0xc0, !PT ;
IMNMX R14, R5, UR4, PT ;
IMNMX R13, R6, UR4, PT ;
ISETP.NE.AND P3, PT, R15, RZ, PT ;
IMAD.IADD R4, R3, 0x1, R20 ;
ISETP.GE.AND P0, PT, R20, c[0x0][0x180], PT ;
IMAD.MOV.U32 R25, RZ, RZ, R22 ;
ISETP.GE.U32.AND P2, PT, R18, 0x3, PT ;
IMNMX R4, RZ, R4, !PT ;
IMNMX R23, R4, UR5, PT ;
@!P3 BRA 0x470 ;
IMAD R5, R23, c[0x0][0x17c], R16 ;
IADD3 R4, P3, R5, c[0x0][0x168], RZ ;
LEA.HI.X.SX32 R5, R5, c[0x0][0x16c], 0x1, P3 ;
LDG.E.U8 R4, [R4.64] ;
ISETP.NE.AND P3, PT, R15, 0x1, PT ;
IMAD.MOV.U32 R25, RZ, RZ, R21 ;
I2F.U16 R7, R4 ;
FADD R12, R12, R7 ;
@!P3 BRA 0x470 ;
ISETP.NE.AND P3, PT, R15, 0x2, PT ;
IMAD R5, R23, c[0x0][0x17c], R14 ;
IADD3 R4, P4, R5, c[0x0][0x168], RZ ;
LEA.HI.X.SX32 R5, R5, c[0x0][0x16c], 0x1, P4 ;
@P3 IMAD R7, R23, c[0x0][0x17c], R13 ;
LDG.E.U8 R4, [R4.64] ;
@P3 IADD3 R6, P4, R7, c[0x0][0x168], RZ ;
@P3 LEA.HI.X.SX32 R7, R7, c[0x0][0x16c], 0x1, P4 ;
@P3 LDG.E.U8 R6, [R6.64] ;
IMAD.MOV.U32 R25, RZ, RZ, R19 ;
@P3 IMAD.MOV.U32 R25, RZ, RZ, R17 ;
I2F.U16 R9, R4 ;
@P3 I2F.U16 R11, R6 ;
FADD R12, R12, R9 ;
@P3 FADD R12, R12, R11 ;
IADD3 R20, R20, 0x1, RZ ;
@!P2 BRA 0x710 ;
IMAD.IADD R4, R0, 0x1, R25 ;
IADD3 R27, R25, 0x3, RZ ;
IMNMX R5, RZ, R4, !PT ;
IADD3 R6, R4.reuse, 0x1, RZ ;
IADD3 R7, R4, 0x2, RZ ;
IMNMX R4, R5, UR4, PT ;
IMAD.IADD R5, R0, 0x1, R27 ;
IMNMX R6, RZ, R6, !PT ;
IMNMX R7, RZ, R7, !PT ;
IMAD R4, R23, c[0x0][0x17c], R4 ;
IMNMX R6, R6, UR4, PT ;
IMNMX R9, RZ, R5, !PT ;
IMNMX R10, R7, UR4, PT ;
IMAD R5, R23, c[0x0][0x17c], R6 ;
IADD3 R8, P2, R4.reuse, c[0x0][0x168], RZ ;
IMNMX R6, R9, UR4, PT ;
IMAD R7, R23, c[0x0][0x17c], R10 ;
LEA.HI.X.SX32 R9, R4, c[0x0][0x16c], 0x1, P2 ;
IADD3 R4, P2, R5, c[0x0][0x168], RZ ;
IMAD R11, R23, c[0x0][0x17c], R6 ;
IADD3 R6, P3, R7, c[0x0][0x168], RZ ;
LDG.E.U8 R8, [R8.64] ;
LEA.HI.X.SX32 R5, R5, c[0x0][0x16c], 0x1, P2 ;
IADD3 R10, P2, R11, c[0x0][0x168], RZ ;
LEA.HI.X.SX32 R7, R7, c[0x0][0x16c], 0x1, P3 ;
LDG.E.U8 R4, [R4.64] ;
LEA.HI.X.SX32 R11, R11, c[0x0][0x16c], 0x1, P2 ;
LDG.E.U8 R6, [R6.64] ;
LDG.E.U8 R10, [R10.64] ;
ISETP.GE.AND P2, PT, R27, c[0x0][0x188], PT ;
IADD3 R25, R25, 0x4, RZ ;
I2F.U16 R29, R8 ;
I2F.U16 R24, R4 ;
I2F.U16 R26, R6 ;
FADD R29, R29, R12 ;
I2F.U16 R28, R10 ;
FADD R24, R29, R24 ;
FADD R24, R24, R26 ;
FADD R12, R24, R28 ;
@!P2 BRA 0x490 ;
@!P0 BRA 0x270 ;
I2F R5, c[0x0][0x190] ;
BSSY B0, 0x810 ;
MUFU.RCP R4, R5 ;
FCHK P0, R12, R5 ;
FFMA R7, -R5, R4, 1 ;
FFMA R7, R4, R7, R4 ;
FFMA R4, R7, R12, RZ ;
FFMA R6, -R5, R4, R12 ;
FFMA R4, R7, R6, R4 ;
@!P0 BRA 0x800 ;
IMAD.MOV.U32 R9, RZ, RZ, R5 ;
MOV R4, 0x7f0 ;
CALL.REL.NOINC 0x1610 ;
IMAD.MOV.U32 R4, RZ, RZ, R7 ;
BSYNC B0 ;
CS2R R6, SRZ ;
IMAD.MOV.U32 R22, RZ, RZ, RZ ;
IMAD.MOV.U32 R5, RZ, RZ, RZ ;
@P1 BRA 0x1230 ;
IMAD.MOV R8, RZ, RZ, -c[0x0][0x188] ;
ISETP.GT.AND P0, PT, R8, c[0x0][0x188], PT ;
@P0 BRA 0x1230 ;
IMAD.MOV.U32 R14, RZ, RZ, c[0x0][0x188] ;
IMNMX R10, R8, c[0x0][0x188], !PT ;
ULDC.64 UR6, c[0x0][0x178] ;
IADD3 R12, R0, -c[0x0][0x188], RZ ;
UIADD3 UR4, UR7, -0x1, URZ ;
IADD3 R11, -R14.reuse, 0x1, RZ ;
IMAD.MOV.U32 R5, RZ, RZ, RZ ;
IADD3 R13, -R14, 0x2, RZ ;
IMAD.MOV.U32 R22, RZ, RZ, RZ ;
IADD3 R10, R10, c[0x0][0x188], RZ ;
IMAD.IADD R15, R0.reuse, 0x1, R11 ;
IMNMX R18, RZ, R12, !PT ;
IMAD.IADD R16, R0, 0x1, R13 ;
IADD3 R19, R10, 0x1, RZ ;
IMAD.MOV.U32 R6, RZ, RZ, RZ ;
IMNMX R15, RZ, R15, !PT ;
UIADD3 UR6, UR6, -0x1, URZ ;
IMNMX R16, RZ, R16, !PT ;
IADD3 R9, R0, 0x3, RZ ;
IADD3 R12, -R14, 0x3, RZ ;
IMNMX R18, R18, UR4, PT ;
LOP3.LUT R19, R19, 0x3, RZ, 0xc0, !PT ;
IMNMX R20, R15, UR4, PT ;
IMNMX R21, R16, UR4, PT ;
ISETP.NE.AND P2, PT, R19, RZ, PT ;
IMAD.IADD R14, R3, 0x1, R2 ;
IADD3 R26, R2.reuse, c[0x0][0x180], RZ ;
IMAD.MOV.U32 R27, RZ, RZ, R8 ;
ISETP.GE.AND P0, PT, R2, c[0x0][0x180], PT ;
IMNMX R14, RZ, R14, !PT ;
IMAD R26, R26, c[0x0][0x18c], RZ ;
ISETP.GE.U32.AND P1, PT, R10, 0x3, PT ;
IMNMX R23, R14, UR6, PT ;
@!P2 BRA 0xd60 ;
IMAD R17, R23, c[0x0][0x17c], R18 ;
IADD3 R14, P3, R26, c[0x0][0x170], RZ ;
IADD3 R16, P2, R17.reuse, c[0x0][0x168], RZ ;
LEA.HI.X.SX32 R15, R26, c[0x0][0x174], 0x1, P3 ;
LEA.HI.X.SX32 R17, R17, c[0x0][0x16c], 0x1, P2 ;
LDG.E.U8 R24, [R14.64] ;
LDG.E.U8 R16, [R16.64] ;
ISETP.NE.AND P2, PT, R19, 0x1, PT ;
I2F.U16 R24, R24 ;
I2F.U16 R25, R16 ;
FADD R28, R24, -c[0x0][0x194] ;
FADD R27, R25.reuse, -R4 ;
FFMA R6, R25, R28.reuse, R6 ;
FFMA R22, R27, R27, R22 ;
FFMA R5, R28, R28, R5 ;
IMAD.MOV.U32 R27, RZ, RZ, R11 ;
@!P2 BRA 0xd60 ;
ISETP.NE.AND P3, PT, R19, 0x2, PT ;
IMAD R17, R23, c[0x0][0x17c], R20 ;
LDG.E.U8 R27, [R14.64+0x1] ;
IADD3 R16, P2, R17, c[0x0][0x168], RZ ;
@P3 IMAD R25, R23, c[0x0][0x17c], R21 ;
LEA.HI.X.SX32 R17, R17, c[0x0][0x16c], 0x1, P2 ;
@P3 LDG.E.U8 R28, [R14.64+0x2] ;
@P3 IADD3 R24, P2, R25.reuse, c[0x0][0x168], RZ ;
LDG.E.U8 R16, [R16.64] ;
@P3 LEA.HI.X.SX32 R25, R25, c[0x0][0x16c], 0x1, P2 ;
@P3 LDG.E.U8 R24, [R24.64] ;
I2F.U16 R27, R27 ;
I2F.U16 R29, R16 ;
@P3 I2F.U16 R28, R28 ;
@P3 I2F.U16 R17, R24 ;
FADD R15, R29, -R4 ;
FADD R14, R27, -c[0x0][0x194] ;
FFMA R22, R15, R15, R22 ;
FFMA R5, R14, R14.reuse, R5 ;
@P3 FADD R28, R28, -c[0x0][0x194] ;
FFMA R6, R29, R14, R6 ;
IMAD.MOV.U32 R27, RZ, RZ, R13 ;
@P3 FADD R15, R17.reuse, -R4 ;
@P3 FFMA R5, R28, R28.reuse, R5 ;
@P3 FFMA R6, R17, R28, R6 ;
@P3 FFMA R22, R15, R15, R22 ;
@P3 IMAD.MOV.U32 R27, RZ, RZ, R12 ;
IADD3 R2, R2, 0x1, RZ ;
@!P1 BRA 0x1220 ;
IADD3 R16, R26, c[0x0][0x188], R27.reuse ;
IMAD.IADD R24, R9, 0x1, R27.reuse ;
IADD3 R25, R27, -0x1, RZ ;
IMAD.IADD R14, R0, 0x1, R27 ;
IADD3 R17, P1, R16, c[0x0][0x170], RZ ;
LEA.HI.X.SX32 R16, R16, c[0x0][0x174], 0x1, P1 ;
IMNMX R14, RZ, R14, !PT ;
IMNMX R14, R14, UR4, PT ;
IMAD R15, R23, c[0x0][0x17c], R14 ;
IADD3 R14, P1, R15.reuse, c[0x0][0x168], RZ ;
IADD3 R26, R24, -0x2, RZ ;
LEA.HI.X.SX32 R15, R15, c[0x0][0x16c], 0x1, P1 ;
IMNMX R26, RZ, R26, !PT ;
LDG.E.U8 R27, [R14.64] ;
IMAD.MOV.U32 R14, RZ, RZ, R17 ;
IMAD.MOV.U32 R15, RZ, RZ, R16 ;
IMNMX R16, R26, UR4, PT ;
LDG.E.U8 R26, [R14.64] ;
IMAD R17, R23, c[0x0][0x17c], R16 ;
LDG.E.U8 R28, [R14.64+0x1] ;
IADD3 R16, P1, R17, c[0x0][0x168], RZ ;
LEA.HI.X.SX32 R17, R17, c[0x0][0x16c], 0x1, P1 ;
LDG.E.U8 R16, [R16.64] ;
I2F.U16 R27, R27 ;
I2F.U16 R26, R26 ;
FADD R29, R27, -R4 ;
FFMA R29, R29, R29, R22 ;
FADD R22, R26, -c[0x0][0x194] ;
FFMA R6, R27, R22.reuse, R6 ;
I2F.U16 R27, R16 ;
FFMA R22, R22, R22, R5 ;
I2F.U16 R17, R28 ;
FADD R5, R27, -R4 ;
IMNMX R16, RZ, R24, !PT ;
LDG.E.U8 R28, [R14.64+0x2] ;
FFMA R5, R5, R5, R29 ;
IADD3 R29, R24, -0x1, RZ ;
IMNMX R29, RZ, R29, !PT ;
IMNMX R29, R29, UR4, PT ;
FADD R17, R17, -c[0x0][0x194] ;
IMAD R29, R23, c[0x0][0x17c], R29 ;
FFMA R6, R27, R17, R6 ;
IADD3 R26, P1, R29, c[0x0][0x168], RZ ;
LEA.HI.X.SX32 R27, R29, c[0x0][0x16c], 0x1, P1 ;
IMNMX R16, R16, UR4, PT ;
FFMA R22, R17, R17, R22 ;
LDG.E.U8 R29, [R14.64+0x3] ;
LDG.E.U8 R26, [R26.64] ;
IMAD R17, R23, c[0x0][0x17c], R16 ;
IADD3 R16, P1, R17, c[0x0][0x168], RZ ;
LEA.HI.X.SX32 R17, R17, c[0x0][0x16c], 0x1, P1 ;
LDG.E.U8 R16, [R16.64] ;
IADD3 R25, R25, 0x4, RZ ;
ISETP.GE.AND P1, PT, R25, c[0x0][0x188], PT ;
I2F.U16 R28, R28 ;
I2F.U16 R17, R26 ;
FADD R27, R17, -R4 ;
FFMA R5, R27, R27, R5 ;
I2F.U16 R27, R16 ;
FADD R26, R28, -c[0x0][0x194] ;
I2F.U16 R29, R29 ;
FFMA R6, R17, R26.reuse, R6 ;
FFMA R26, R26, R26, R22 ;
FADD R22, R27, -R4 ;
FFMA R22, R22, R22, R5 ;
FADD R5, R29, -c[0x0][0x194] ;
IADD3 R17, P2, R14, 0x4, RZ ;
FFMA R6, R27, R5.reuse, R6 ;
FFMA R5, R5, R5, R26 ;
IADD3 R26, R24.reuse, 0x4, RZ ;
IMAD.X R16, RZ, RZ, R15, P2 ;
IADD3 R14, R24, 0x1, RZ ;
IMAD.MOV.U32 R24, RZ, RZ, R26 ;
@!P1 BRA 0xde0 ;
@!P0 BRA 0xa00 ;
FSETP.NEU.AND P0, PT, R5, RZ, PT ;
BSSY B0, 0x1460 ;
IMAD R0, R3, c[0x0][0x17c], R0 ;
FSETP.EQ.OR P0, PT, R22, RZ, !P0 ;
@P0 BRA 0x1450 ;
FMUL R2, R5, R22 ;
BSSY B1, 0x1370 ;
MUFU.RSQ R5, R2 ;
IADD3 R3, R2, -0xd000000, RZ ;
ISETP.GT.U32.AND P0, PT, R3, 0x727fffff, PT ;
@!P0 BRA 0x1320 ;
MOV R10, 0x1300 ;
CALL.REL.NOINC 0x14a0 ;
IMAD.MOV.U32 R3, RZ, RZ, R4 ;
BRA 0x1360 ;
FMUL.FTZ R3, R2, R5 ;
FMUL.FTZ R4, R5, 0.5 ;
FFMA R2, -R3, R3, R2 ;
FFMA R3, R2, R4, R3 ;
BSYNC B1 ;
MUFU.RCP R2, R3 ;
BSSY B1, 0x1450 ;
FCHK P0, R6, R3 ;
FFMA R5, R2, -R3, 1 ;
FFMA R5, R2, R5, R2 ;
FFMA R2, R5, R6, RZ ;
FFMA R4, R2, -R3, R6 ;
FFMA R7, R5, R4, R2 ;
@!P0 BRA 0x1440 ;
IMAD.MOV.U32 R12, RZ, RZ, R6 ;
MOV R4, 0x1440 ;
IMAD.MOV.U32 R9, RZ, RZ, R3 ;
CALL.REL.NOINC 0x1610 ;
BSYNC B1 ;
BSYNC B0 ;
IMAD.MOV.U32 R3, RZ, RZ, 0x4 ;
IMAD.WIDE R2, R0, R3, c[0x0][0x160] ;
STG.E [R2.64], R7 ;
EXIT ;
LOP3.LUT P0, RZ, R2, 0x7fffffff, RZ, 0xc0, !PT ;
@!P0 IMAD.MOV.U32 R3, RZ, RZ, R2 ;
@!P0 BRA 0x15d0 ;
FSETP.GEU.FTZ.AND P0, PT, R2, RZ, PT ;
@!P0 IMAD.MOV.U32 R3, RZ, RZ, 0x7fffffff ;
@!P0 BRA 0x15d0 ;
FSETP.GTU.FTZ.AND P0, PT, |R2|, +INF , PT ;
@P0 FADD.FTZ R3, R2, 1 ;
@P0 BRA 0x15d0 ;
FSETP.NEU.FTZ.AND P0, PT, |R2|, +INF , PT ;
@P0 FFMA R4, R2, 1.84467440737095516160e+19, RZ ;
@P0 MUFU.RSQ R3, R4 ;
@P0 FMUL.FTZ R5, R4, R3 ;
@P0 FMUL.FTZ R9, R3, 0.5 ;
@P0 FADD.FTZ R7, -R5.reuse, -RZ ;
@!P0 IMAD.MOV.U32 R3, RZ, RZ, R2 ;
@P0 FFMA R8, R5, R7, R4 ;
@P0 FFMA R8, R8, R9, R5 ;
@P0 FMUL.FTZ R3, R8, 2.3283064365386962891e-10 ;
IMAD.MOV.U32 R4, RZ, RZ, R3 ;
IMAD.MOV.U32 R2, RZ, RZ, R10 ;
IMAD.MOV.U32 R3, RZ, RZ, 0x0 ;
RET.REL.NODEC R2 0x0 ;
SHF.R.U32.HI R6, RZ, 0x17, R9.reuse ;
BSSY B2, 0x1c70 ;
SHF.R.U32.HI R5, RZ, 0x17, R12.reuse ;
LOP3.LUT R13, R6, 0xff, RZ, 0xc0, !PT ;
IMAD.MOV.U32 R6, RZ, RZ, R9 ;
LOP3.LUT R11, R5, 0xff, RZ, 0xc0, !PT ;
IMAD.MOV.U32 R5, RZ, RZ, R12 ;
IADD3 R10, R13, -0x1, RZ ;
IADD3 R8, R11, -0x1, RZ ;
ISETP.GT.U32.AND P0, PT, R10, 0xfd, PT ;
ISETP.GT.U32.OR P0, PT, R8, 0xfd, P0 ;
@!P0 IMAD.MOV.U32 R7, RZ, RZ, RZ ;
@!P0 BRA 0x1850 ;
FSETP.GTU.FTZ.AND P0, PT, |R12|, +INF , PT ;
FSETP.GTU.FTZ.AND P2, PT, |R9|, +INF , PT ;
PLOP3.LUT P0, PT, P0, P2, PT, 0xa8, 0x0 ;
@P0 BRA 0x1c50 ;
LOP3.LUT P0, RZ, R6, 0x7fffffff, R5, 0xc8, !PT ;
@!P0 BRA 0x1c30 ;
FSETP.NEU.FTZ.AND P2, PT, |R12|.reuse, +INF , PT ;
FSETP.NEU.FTZ.AND P3, PT, |R9|, +INF , PT ;
FSETP.NEU.FTZ.AND P0, PT, |R12|, +INF , PT ;
@!P3 BRA !P2, 0x1c30 ;
LOP3.LUT P2, RZ, R5, 0x7fffffff, RZ, 0xc0, !PT ;
PLOP3.LUT P2, PT, P3, P2, PT, 0x2a, 0x0 ;
@P2 BRA 0x1c10 ;
LOP3.LUT P2, RZ, R6, 0x7fffffff, RZ, 0xc0, !PT ;
PLOP3.LUT P0, PT, P0, P2, PT, 0x2a, 0x0 ;
@P0 BRA 0x1be0 ;
ISETP.GE.AND P0, PT, R8, RZ, PT ;
ISETP.GE.AND P2, PT, R10, RZ, PT ;
@P0 IMAD.MOV.U32 R7, RZ, RZ, RZ ;
@!P0 IMAD.MOV.U32 R7, RZ, RZ, -0x40 ;
@!P0 FFMA R5, R12, 1.84467440737095516160e+19, RZ ;
@!P2 FFMA R6, R9, 1.84467440737095516160e+19, RZ ;
@!P2 IADD3 R7, R7, 0x40, RZ ;
LEA R9, R13, 0xc0800000, 0x17 ;
BSSY B3, 0x1bd0 ;
IMAD.IADD R9, R6, 0x1, -R9 ;
IADD3 R6, R11, -0x7f, RZ ;
MUFU.RCP R8, R9 ;
FADD.FTZ R10, -R9, -RZ ;
IMAD R5, R6, -0x800000, R5 ;
FFMA R11, R8, R10, 1 ;
FFMA R12, R8, R11, R8 ;
FFMA R8, R5, R12, RZ ;
FFMA R11, R10, R8, R5 ;
FFMA R11, R12, R11, R8 ;
IADD3 R8, R6, 0x7f, -R13 ;
FFMA R10, R10, R11, R5 ;
IMAD.IADD R8, R8, 0x1, R7 ;
FFMA R5, R12, R10, R11 ;
SHF.R.U32.HI R6, RZ, 0x17, R5 ;
LOP3.LUT R6, R6, 0xff, RZ, 0xc0, !PT ;
IMAD.IADD R13, R6, 0x1, R8 ;
IADD3 R6, R13, -0x1, RZ ;
ISETP.GE.U32.AND P0, PT, R6, 0xfe, PT ;
@!P0 BRA 0x1bb0 ;
ISETP.GT.AND P0, PT, R13, 0xfe, PT ;
@P0 BRA 0x1b80 ;
ISETP.GE.AND P0, PT, R13, 0x1, PT ;
@P0 BRA 0x1bc0 ;
ISETP.GE.AND P0, PT, R13, -0x18, PT ;
LOP3.LUT R5, R5, 0x80000000, RZ, 0xc0, !PT ;
@!P0 BRA 0x1bc0 ;
FFMA.RZ R6, R12.reuse, R10.reuse, R11.reuse ;
IADD3 R9, R13.reuse, 0x20, RZ ;
FFMA.RM R7, R12, R10.reuse, R11.reuse ;
ISETP.NE.AND P3, PT, R13.reuse, RZ, PT ;
LOP3.LUT R8, R6, 0x7fffff, RZ, 0xc0, !PT ;
FFMA.RP R6, R12, R10, R11 ;
ISETP.NE.AND P2, PT, R13, RZ, PT ;
IMAD.MOV R10, RZ, RZ, -R13 ;
LOP3.LUT R8, R8, 0x800000, RZ, 0xfc, !PT ;
FSETP.NEU.FTZ.AND P0, PT, R6, R7, PT ;
SHF.L.U32 R9, R8, R9, RZ ;
SEL R7, R10, RZ, P3 ;
ISETP.NE.AND P2, PT, R9, RZ, P2 ;
SHF.R.U32.HI R7, RZ, R7, R8 ;
PLOP3.LUT P0, PT, P0, P2, PT, 0xa8, 0x0 ;
SHF.R.U32.HI R9, RZ, 0x1, R7 ;
SEL R6, RZ, 0x1, !P0 ;
LOP3.LUT R6, R6, 0x1, R9, 0xf8, !PT ;
LOP3.LUT R6, R6, R7, RZ, 0xc0, !PT ;
IMAD.IADD R6, R9, 0x1, R6 ;
LOP3.LUT R5, R6, R5, RZ, 0xfc, !PT ;
BRA 0x1bc0 ;
LOP3.LUT R5, R5, 0x80000000, RZ, 0xc0, !PT ;
LOP3.LUT R5, R5, 0x7f800000, RZ, 0xfc, !PT ;
BRA 0x1bc0 ;
IMAD R5, R8, 0x800000, R5 ;
BSYNC B3 ;
BRA 0x1c60 ;
LOP3.LUT R5, R6, 0x80000000, R5, 0x48, !PT ;
LOP3.LUT R5, R5, 0x7f800000, RZ, 0xfc, !PT ;
BRA 0x1c60 ;
LOP3.LUT R5, R6, 0x80000000, R5, 0x48, !PT ;
BRA 0x1c60 ;
MUFU.RSQ R5, -QNAN ;
BRA 0x1c60 ;
FADD.FTZ R5, R12, R9 ;
BSYNC B2 ;
IMAD.MOV.U32 R7, RZ, RZ, R5 ;
IMAD.MOV.U32 R5, RZ, RZ, 0x0 ;
RET.REL.NODEC R4 0x0 ;
BRA 0x1ca0;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
```
|
```amdasm
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z34naive_normalized_cross_correlationPfPhS0_iiiiiiif ; -- Begin function _Z34naive_normalized_cross_correlationPfPhS0_iiiiiiif
.globl _Z34naive_normalized_cross_correlationPfPhS0_iiiiiiif
.p2align 8
.type _Z34naive_normalized_cross_correlationPfPhS0_iiiiiiif,@function
_Z34naive_normalized_cross_correlationPfPhS0_iiiiiiif: ; @_Z34naive_normalized_cross_correlationPfPhS0_iiiiiiif
; %bb.0:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x44
s_load_b128 s[4:7], s[0:1], 0x18
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_lshr_b32 s3, s2, 16
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[0:1], null, s14, s2, v[2:3]
v_mad_u64_u32 v[1:2], null, s15, s3, v[3:4]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_gt_i32_e32 vcc_lo, s5, v0
v_cmp_gt_i32_e64 s2, s4, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, vcc_lo, s2
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_18
; %bb.1:
s_clause 0x2
s_load_b128 s[12:15], s[0:1], 0x28
s_load_b128 s[8:11], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
s_sub_i32 s2, 0, s6
v_mov_b32_e32 v6, 0
s_cmp_gt_i32 s6, -1
s_cselect_b32 s3, -1, 0
s_cmp_lt_i32 s6, 0
s_waitcnt lgkmcnt(0)
v_subrev_nc_u32_e32 v2, s12, v0
s_cbranch_scc1 .LBB0_8
; %bb.2: ; %.lr.ph136
s_cmp_gt_i32 s12, -1
v_subrev_nc_u32_e32 v3, s12, v0
v_mov_b32_e32 v6, 0
s_cselect_b32 s7, -1, 0
s_lshl_b32 s18, s12, 1
s_add_i32 s16, s5, -1
s_add_i32 s17, s4, -1
s_or_b32 s18, s18, 1
s_mov_b32 s19, s2
.LBB0_3: ; =>This Loop Header: Depth=1
; Child Loop BB0_5 Depth 2
s_and_not1_b32 vcc_lo, exec_lo, s7
s_cbranch_vccnz .LBB0_6
; %bb.4: ; %.lr.ph
; in Loop: Header=BB0_3 Depth=1
v_dual_mov_b32 v5, v3 :: v_dual_add_nc_u32 v4, s19, v1
s_mov_b32 s20, s18
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_maxmin_i32 v4, v4, 0, s17
v_mul_lo_u32 v4, v4, s5
.LBB0_5: ; Parent Loop BB0_3 Depth=1
; => This Inner Loop Header: Depth=2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_maxmin_i32 v7, v5, 0, s16
s_add_i32 s20, s20, -1
s_cmp_eq_u32 s20, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v7, v7, v4
v_ashrrev_i32_e32 v8, 31, v7
v_add_co_u32 v7, vcc_lo, s10, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v8, vcc_lo, s11, v8, vcc_lo
global_load_u8 v7, v[7:8], off
s_waitcnt vmcnt(0)
v_cvt_f32_ubyte0_e32 v7, v7
v_dual_add_f32 v6, v6, v7 :: v_dual_add_nc_u32 v5, 1, v5
s_cbranch_scc0 .LBB0_5
.LBB0_6: ; %._crit_edge
; in Loop: Header=BB0_3 Depth=1
s_add_i32 s20, s19, 1
s_cmp_eq_u32 s19, s6
s_cbranch_scc1 .LBB0_8
; %bb.7: ; in Loop: Header=BB0_3 Depth=1
s_mov_b32 s19, s20
s_branch .LBB0_3
.LBB0_8: ; %._crit_edge137
v_dual_mov_b32 v3, 0 :: v_dual_mov_b32 v4, 0
v_mov_b32_e32 v5, 0
s_and_not1_b32 vcc_lo, exec_lo, s3
s_mov_b32 s3, 0
s_cbranch_vccnz .LBB0_15
; %bb.9: ; %.lr.ph156
v_cvt_f32_i32_e32 v5, s14
s_cmp_gt_i32 s12, -1
s_cselect_b32 s7, -1, 0
s_lshl_b32 s12, s12, 1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_div_scale_f32 v3, null, v5, v5, v6
v_div_scale_f32 v8, vcc_lo, v6, v5, v6
s_add_i32 s14, s5, -1
v_rcp_f32_e32 v4, v3
s_add_i32 s4, s4, -1
s_or_b32 s12, s12, 1
s_waitcnt_depctr 0xfff
v_fma_f32 v7, -v3, v4, 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v4, v7, v4
v_mul_f32_e32 v9, v8, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v7, -v3, v9, v8
v_fmac_f32_e32 v9, v7, v4
v_mov_b32_e32 v7, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_fma_f32 v8, -v3, v9, v8
v_mov_b32_e32 v3, 0
v_div_fmas_f32 v8, v8, v4, v9
v_mov_b32_e32 v4, 0
s_delay_alu instid0(VALU_DEP_2)
v_div_fixup_f32 v6, v8, v5, v6
v_mov_b32_e32 v5, 0
.LBB0_10: ; =>This Loop Header: Depth=1
; Child Loop BB0_12 Depth 2
s_and_not1_b32 vcc_lo, exec_lo, s7
s_cbranch_vccnz .LBB0_13
; %bb.11: ; %.lr.ph145
; in Loop: Header=BB0_10 Depth=1
v_dual_mov_b32 v9, v2 :: v_dual_add_nc_u32 v8, s2, v1
s_mov_b32 s16, s3
s_mov_b32 s17, s12
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_maxmin_i32 v8, v8, 0, s4
v_mul_lo_u32 v8, v8, s5
.LBB0_12: ; Parent Loop BB0_10 Depth=1
; => This Inner Loop Header: Depth=2
v_maxmin_i32 v10, v9, 0, s14
s_ashr_i32 s19, s16, 31
s_add_u32 s18, s0, s16
s_addc_u32 s19, s1, s19
s_add_i32 s17, s17, -1
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v10, v10, v8
s_add_i32 s16, s16, 1
s_cmp_eq_u32 s17, 0
v_add_nc_u32_e32 v9, 1, v9
v_ashrrev_i32_e32 v11, 31, v10
v_add_co_u32 v10, vcc_lo, s10, v10
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v11, vcc_lo, s11, v11, vcc_lo
global_load_u8 v12, v7, s[18:19]
global_load_u8 v10, v[10:11], off
s_waitcnt vmcnt(1)
v_cvt_f32_ubyte0_e32 v11, v12
s_waitcnt vmcnt(0)
v_cvt_f32_ubyte0_e32 v10, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_subrev_f32 v11, s15, v11 :: v_dual_sub_f32 v12, v10, v6
v_dual_fmac_f32 v5, v11, v11 :: v_dual_fmac_f32 v4, v12, v12
v_fmac_f32_e32 v3, v11, v10
s_cbranch_scc0 .LBB0_12
.LBB0_13: ; %._crit_edge146
; in Loop: Header=BB0_10 Depth=1
s_add_i32 s16, s2, 1
s_add_i32 s3, s3, s13
s_cmp_eq_u32 s2, s6
s_cbranch_scc1 .LBB0_15
; %bb.14: ; in Loop: Header=BB0_10 Depth=1
s_mov_b32 s2, s16
s_branch .LBB0_10
.LBB0_15: ; %Flow249
v_cmp_neq_f32_e32 vcc_lo, 0, v4
v_cmp_neq_f32_e64 s0, 0, v5
v_mov_b32_e32 v2, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s0, vcc_lo, s0
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_17
; %bb.16:
v_mul_f32_e32 v2, v5, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_f32_e32 v4, 0x4f800000, v2
v_cmp_gt_f32_e32 vcc_lo, 0xf800000, v2
v_cndmask_b32_e32 v2, v2, v4, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
v_sqrt_f32_e32 v4, v2
s_waitcnt_depctr 0xfff
v_add_nc_u32_e32 v5, -1, v4
v_add_nc_u32_e32 v6, 1, v4
v_fma_f32 v7, -v5, v4, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v8, -v6, v4, v2
v_cmp_ge_f32_e64 s0, 0, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cndmask_b32_e64 v4, v4, v5, s0
v_cmp_lt_f32_e64 s0, 0, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e64 v4, v4, v6, s0
v_mul_f32_e32 v5, 0x37800000, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v4, v4, v5, vcc_lo
v_cmp_class_f32_e64 vcc_lo, v2, 0x260
v_cndmask_b32_e32 v2, v4, v2, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_scale_f32 v4, null, v2, v2, v3
v_rcp_f32_e32 v5, v4
s_waitcnt_depctr 0xfff
v_fma_f32 v6, -v4, v5, 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v5, v6, v5
v_div_scale_f32 v6, vcc_lo, v3, v2, v3
v_mul_f32_e32 v7, v6, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v8, -v4, v7, v6
v_fmac_f32_e32 v7, v8, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v4, -v4, v7, v6
v_div_fmas_f32 v4, v4, v5, v7
s_delay_alu instid0(VALU_DEP_1)
v_div_fixup_f32 v2, v4, v2, v3
.LBB0_17:
s_or_b32 exec_lo, exec_lo, s1
v_mad_u64_u32 v[3:4], null, v1, s5, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v4, 31, v3
v_lshlrev_b64 v[0:1], 2, v[3:4]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s8, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s9, v1, vcc_lo
global_store_b32 v[0:1], v2, off
.LBB0_18:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z34naive_normalized_cross_correlationPfPhS0_iiiiiiif
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 312
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 13
.amdhsa_next_free_sgpr 21
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z34naive_normalized_cross_correlationPfPhS0_iiiiiiif, .Lfunc_end0-_Z34naive_normalized_cross_correlationPfPhS0_iiiiiiif
; -- End function
.section .AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1024
; NumSgprs: 23
; NumVgprs: 13
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 23
; NumVGPRsForWavesPerEU: 13
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object ; @__hip_cuid_
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0 ; 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 36
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: by_value
- .offset: 44
.size: 4
.value_kind: by_value
- .offset: 48
.size: 4
.value_kind: by_value
- .offset: 52
.size: 4
.value_kind: by_value
- .offset: 56
.size: 4
.value_kind: hidden_block_count_x
- .offset: 60
.size: 4
.value_kind: hidden_block_count_y
- .offset: 64
.size: 4
.value_kind: hidden_block_count_z
- .offset: 68
.size: 2
.value_kind: hidden_group_size_x
- .offset: 70
.size: 2
.value_kind: hidden_group_size_y
- .offset: 72
.size: 2
.value_kind: hidden_group_size_z
- .offset: 74
.size: 2
.value_kind: hidden_remainder_x
- .offset: 76
.size: 2
.value_kind: hidden_remainder_y
- .offset: 78
.size: 2
.value_kind: hidden_remainder_z
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 112
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 120
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 312
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z34naive_normalized_cross_correlationPfPhS0_iiiiiiif
.private_segment_fixed_size: 0
.sgpr_count: 23
.sgpr_spill_count: 0
.symbol: _Z34naive_normalized_cross_correlationPfPhS0_iiiiiiif.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 13
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
```
| 9,217 | 6,564 |
349 |
Convert the following CUDA host assembly code to AMD host assembly:
```cudaasm
.file "tmpxft_000a5d66_00000000-6_naive_normalized_cross_correlation.cudafe1.cpp"
.text
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z67__device_stub__Z34naive_normalized_cross_correlationPfPhS0_iiiiiiifPfPhS0_iiiiiiif
.type _Z67__device_stub__Z34naive_normalized_cross_correlationPfPhS0_iiiiiiifPfPhS0_iiiiiiif, @function
_Z67__device_stub__Z34naive_normalized_cross_correlationPfPhS0_iiiiiiifPfPhS0_iiiiiiif:
.LFB2051:
.cfi_startproc
endbr64
subq $216, %rsp
.cfi_def_cfa_offset 224
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
movss %xmm0, 8(%rsp)
movq %fs:40, %rax
movq %rax, 200(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
leaq 224(%rsp), %rax
movq %rax, 160(%rsp)
leaq 232(%rsp), %rax
movq %rax, 168(%rsp)
leaq 240(%rsp), %rax
movq %rax, 176(%rsp)
leaq 248(%rsp), %rax
movq %rax, 184(%rsp)
leaq 8(%rsp), %rax
movq %rax, 192(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 200(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $216, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 232
pushq 56(%rsp)
.cfi_def_cfa_offset 240
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z34naive_normalized_cross_correlationPfPhS0_iiiiiiif(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 224
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z67__device_stub__Z34naive_normalized_cross_correlationPfPhS0_iiiiiiifPfPhS0_iiiiiiif, .-_Z67__device_stub__Z34naive_normalized_cross_correlationPfPhS0_iiiiiiifPfPhS0_iiiiiiif
.globl _Z34naive_normalized_cross_correlationPfPhS0_iiiiiiif
.type _Z34naive_normalized_cross_correlationPfPhS0_iiiiiiif, @function
_Z34naive_normalized_cross_correlationPfPhS0_iiiiiiif:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 24
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 40
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 48
call _Z67__device_stub__Z34naive_normalized_cross_correlationPfPhS0_iiiiiiifPfPhS0_iiiiiiif
addq $40, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z34naive_normalized_cross_correlationPfPhS0_iiiiiiif, .-_Z34naive_normalized_cross_correlationPfPhS0_iiiiiiif
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z34naive_normalized_cross_correlationPfPhS0_iiiiiiif"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z34naive_normalized_cross_correlationPfPhS0_iiiiiiif(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
```
|
```amdasm
.text
.file "naive_normalized_cross_correlation.hip"
.globl _Z49__device_stub__naive_normalized_cross_correlationPfPhS0_iiiiiiif # -- Begin function _Z49__device_stub__naive_normalized_cross_correlationPfPhS0_iiiiiiif
.type _Z49__device_stub__naive_normalized_cross_correlationPfPhS0_iiiiiiif,@function
_Z49__device_stub__naive_normalized_cross_correlationPfPhS0_iiiiiiif: # @_Z49__device_stub__naive_normalized_cross_correlationPfPhS0_iiiiiiif
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $192, %rsp
.cfi_def_cfa_offset 240
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 56(%rsp), %rax
movq %rdi, (%rax)
leaq 48(%rsp), %rdi
movq %rsi, (%rdi)
leaq 40(%rsp), %rsi
movq %rdx, (%rsi)
leaq 20(%rsp), %rdx
movl %ecx, (%rdx)
leaq 16(%rsp), %rcx
movl %r8d, (%rcx)
leaq 12(%rsp), %r8
movl %r9d, (%r8)
leaq 8(%rsp), %r9
movss %xmm0, (%r9)
leaq 96(%rsp), %rbx
movq %rax, (%rbx)
movq %rdi, 8(%rbx)
movq %rsi, 16(%rbx)
movq %rdx, 24(%rbx)
movq %rcx, 32(%rbx)
movq %r8, 40(%rbx)
leaq 240(%rsp), %rax
movq %rax, 48(%rbx)
leaq 248(%rsp), %rax
movq %rax, 56(%rbx)
leaq 256(%rsp), %rax
movq %rax, 64(%rbx)
leaq 264(%rsp), %rax
movq %rax, 72(%rbx)
movq %r9, 80(%rbx)
leaq 80(%rsp), %r14
leaq 64(%rsp), %r15
leaq 32(%rsp), %r12
leaq 24(%rsp), %r13
movq %r14, %rdi
movq %r15, %rsi
movq %r12, %rdx
movq %r13, %rcx
callq __hipPopCallConfiguration
movq (%r14), %rsi
movl 8(%r14), %edx
movq (%r15), %rcx
movl 8(%r15), %r8d
movl $_Z34naive_normalized_cross_correlationPfPhS0_iiiiiiif, %edi
movq %rbx, %r9
pushq (%r13)
.cfi_adjust_cfa_offset 8
pushq (%r12)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $208, %rsp
.cfi_adjust_cfa_offset -208
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z49__device_stub__naive_normalized_cross_correlationPfPhS0_iiiiiiif, .Lfunc_end0-_Z49__device_stub__naive_normalized_cross_correlationPfPhS0_iiiiiiif
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, %rdi
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z34naive_normalized_cross_correlationPfPhS0_iiiiiiif, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z34naive_normalized_cross_correlationPfPhS0_iiiiiiif,@object # @_Z34naive_normalized_cross_correlationPfPhS0_iiiiiiif
.section .rodata,"a",@progbits
.globl _Z34naive_normalized_cross_correlationPfPhS0_iiiiiiif
.p2align 3, 0x0
_Z34naive_normalized_cross_correlationPfPhS0_iiiiiiif:
.quad _Z49__device_stub__naive_normalized_cross_correlationPfPhS0_iiiiiiif
.size _Z34naive_normalized_cross_correlationPfPhS0_iiiiiiif, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z34naive_normalized_cross_correlationPfPhS0_iiiiiiif"
.size .L__unnamed_1, 54
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z49__device_stub__naive_normalized_cross_correlationPfPhS0_iiiiiiif
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z34naive_normalized_cross_correlationPfPhS0_iiiiiiif
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
```
| 2,406 | 2,468 |
350 |
Convert the following CUDA device assembly code to AMD device assembly:
```cudaasm
code for sm_80
Function : _Z15assign_thru_gpuPdS_Pii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ;
S2R R0, SR_CTAID.X ;
S2R R3, SR_TID.X ;
IMAD R0, R0, c[0x0][0x0], R3 ;
ISETP.GE.AND P0, PT, R0, c[0x0][0x178], PT ;
@P0 EXIT ;
IMAD.MOV.U32 R7, RZ, RZ, c[0x0][0x0] ;
ULDC.64 UR4, c[0x0][0x118] ;
BSSY B0, 0x860 ;
IMAD.MOV.U32 R6, RZ, RZ, RZ ;
IMAD R7, R7, c[0x0][0xc], RZ ;
I2F.U32.RP R5, R7 ;
IMAD.IADD R2, R0, 0x1, R7 ;
IADD3 R9, RZ, -R7, RZ ;
ISETP.NE.U32.AND P2, PT, R7, RZ, PT ;
LOP3.LUT R4, RZ, R2, RZ, 0x33, !PT ;
IMAD.MOV.U32 R2, RZ, RZ, RZ ;
IADD3 R4, R4, c[0x0][0x178], R7 ;
MUFU.RCP R5, R5 ;
IADD3 R3, R5, 0xffffffe, RZ ;
F2I.FTZ.U32.TRUNC.NTZ R3, R3 ;
IMAD R9, R9, R3, RZ ;
IMAD.HI.U32 R9, R3, R9, R2 ;
IMAD.HI.U32 R9, R9, R4, RZ ;
IADD3 R2, -R9, RZ, RZ ;
IMAD R2, R7, R2, R4 ;
ISETP.GE.U32.AND P0, PT, R2, R7, PT ;
@P0 IMAD.IADD R2, R2, 0x1, -R7 ;
@P0 IADD3 R9, R9, 0x1, RZ ;
ISETP.GT.U32.AND P0, PT, R7, R4, PT ;
ISETP.GE.U32.AND P1, PT, R2, R7, PT ;
@P1 IADD3 R9, R9, 0x1, RZ ;
@!P2 LOP3.LUT R9, RZ, R7, RZ, 0x33, !PT ;
IADD3 R9, R9, 0x1, RZ ;
LOP3.LUT R8, R9, 0x1, RZ, 0xc0, !PT ;
@P0 BRA 0x850 ;
IADD3 R9, R9, -R8, RZ ;
IMAD.MOV.U32 R6, RZ, RZ, RZ ;
MOV R2, c[0x0][0x168] ;
IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x16c] ;
HFMA2.MMA R13, -RZ, RZ, 0, 2.384185791015625e-07 ;
IMAD R14, R7, R6, R0 ;
IMAD.WIDE R4, R14, R13, c[0x0][0x170] ;
LDG.E R15, [R4.64] ;
ISETP.NE.AND P0, PT, R15, RZ, PT ;
@!P0 LDG.E.64 R18, [R2.64] ;
IMAD.MOV.U32 R12, RZ, RZ, 0x8 ;
@!P0 IMAD R11, R14, 0x3, RZ ;
@!P0 IMAD.WIDE R10, R11, R12, c[0x0][0x160] ;
@!P0 STG.E.64 [R10.64], R18 ;
@!P0 LDG.E.64 R20, [R2.64+0x8] ;
@!P0 STG.E.64 [R10.64+0x8], R20 ;
@!P0 LDG.E.64 R22, [R2.64+0x10] ;
@!P0 STG.E.64 [R10.64+0x10], R22 ;
@!P0 LDG.E R15, [R4.64] ;
ISETP.NE.AND P0, PT, R15, 0x1, PT ;
@!P0 LDG.E.64 R24, [R2.64+0x18] ;
@!P0 IMAD R17, R14, 0x3, RZ ;
@!P0 IMAD.WIDE R16, R17, R12, c[0x0][0x160] ;
@!P0 STG.E.64 [R16.64], R24 ;
@!P0 LDG.E.64 R18, [R2.64+0x20] ;
@!P0 STG.E.64 [R16.64+0x8], R18 ;
@!P0 LDG.E.64 R20, [R2.64+0x28] ;
@!P0 STG.E.64 [R16.64+0x10], R20 ;
@!P0 LDG.E R15, [R4.64] ;
ISETP.NE.AND P0, PT, R15, 0x2, PT ;
@!P0 LDG.E.64 R22, [R2.64+0x30] ;
@!P0 IMAD R11, R14, 0x3, RZ ;
@!P0 IMAD.WIDE R10, R11, R12, c[0x0][0x160] ;
@!P0 STG.E.64 [R10.64], R22 ;
@!P0 LDG.E.64 R24, [R2.64+0x38] ;
@!P0 STG.E.64 [R10.64+0x8], R24 ;
@!P0 LDG.E.64 R18, [R2.64+0x40] ;
@!P0 STG.E.64 [R10.64+0x10], R18 ;
@!P0 LDG.E R15, [R4.64] ;
ISETP.NE.AND P0, PT, R15, 0x3, PT ;
@!P0 LDG.E.64 R20, [R2.64+0x48] ;
@!P0 IMAD R17, R14, 0x3, RZ ;
@!P0 IMAD.WIDE R16, R17, R12, c[0x0][0x160] ;
@!P0 STG.E.64 [R16.64], R20 ;
@!P0 LDG.E.64 R22, [R2.64+0x50] ;
IADD3 R14, R7, R14, RZ ;
@!P0 STG.E.64 [R16.64+0x8], R22 ;
@!P0 LDG.E.64 R24, [R2.64+0x58] ;
IMAD.WIDE R10, R14, R13, c[0x0][0x170] ;
@!P0 STG.E.64 [R16.64+0x10], R24 ;
LDG.E R26, [R10.64] ;
ISETP.NE.AND P0, PT, R26, RZ, PT ;
@!P0 LDG.E.64 R4, [R2.64] ;
IMAD R13, R14, 0x3, RZ ;
IMAD.WIDE R12, R13, R12, c[0x0][0x160] ;
@!P0 STG.E.64 [R12.64], R4 ;
@!P0 LDG.E.64 R14, [R2.64+0x8] ;
@!P0 STG.E.64 [R12.64+0x8], R14 ;
@!P0 LDG.E.64 R18, [R2.64+0x10] ;
@!P0 STG.E.64 [R12.64+0x10], R18 ;
@!P0 LDG.E R26, [R10.64] ;
BSSY B1, 0x6d0 ;
IADD3 R9, R9, -0x2, RZ ;
ISETP.NE.AND P0, PT, R26, 0x1, PT ;
@P0 BRA 0x6c0 ;
LDG.E.64 R4, [R2.64+0x18] ;
STG.E.64 [R12.64], R4 ;
LDG.E.64 R14, [R2.64+0x20] ;
STG.E.64 [R12.64+0x8], R14 ;
LDG.E.64 R16, [R2.64+0x28] ;
STG.E.64 [R12.64+0x10], R16 ;
LDG.E R26, [R10.64] ;
BSYNC B1 ;
ISETP.NE.AND P0, PT, R26, 0x2, PT ;
BSSY B1, 0x790 ;
ISETP.NE.AND P1, PT, R9, RZ, PT ;
@P0 BRA 0x780 ;
LDG.E.64 R4, [R2.64+0x30] ;
STG.E.64 [R12.64], R4 ;
LDG.E.64 R14, [R2.64+0x38] ;
STG.E.64 [R12.64+0x8], R14 ;
LDG.E.64 R16, [R2.64+0x40] ;
STG.E.64 [R12.64+0x10], R16 ;
LDG.E R26, [R10.64] ;
BSYNC B1 ;
ISETP.NE.AND P0, PT, R26, 0x3, PT ;
BSSY B1, 0x830 ;
@P0 BRA 0x820 ;
LDG.E.64 R4, [R2.64+0x48] ;
STG.E.64 [R12.64], R4 ;
LDG.E.64 R10, [R2.64+0x50] ;
STG.E.64 [R12.64+0x8], R10 ;
LDG.E.64 R14, [R2.64+0x58] ;
STG.E.64 [R12.64+0x10], R14 ;
BSYNC B1 ;
IADD3 R6, R6, 0x2, RZ ;
@P1 BRA 0x280 ;
BSYNC B0 ;
ISETP.NE.AND P0, PT, R8, RZ, PT ;
@!P0 EXIT ;
IMAD.MOV.U32 R3, RZ, RZ, 0x4 ;
IMAD R0, R7, R6, R0 ;
IMAD.WIDE R6, R0, R3, c[0x0][0x170] ;
LDG.E R14, [R6.64] ;
MOV R3, 0x8 ;
IMAD R2, R0, 0x3, RZ ;
BSSY B0, 0x9c0 ;
IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x168] ;
MOV R5, c[0x0][0x16c] ;
IMAD.WIDE R2, R2, R3, c[0x0][0x160] ;
ISETP.NE.AND P0, PT, R14, RZ, PT ;
@P0 BRA 0x9b0 ;
LDG.E.64 R8, [R4.64] ;
STG.E.64 [R2.64], R8 ;
LDG.E.64 R10, [R4.64+0x8] ;
STG.E.64 [R2.64+0x8], R10 ;
LDG.E.64 R12, [R4.64+0x10] ;
STG.E.64 [R2.64+0x10], R12 ;
LDG.E R14, [R6.64] ;
BSYNC B0 ;
ISETP.NE.AND P0, PT, R14, 0x1, PT ;
BSSY B0, 0xa70 ;
@P0 BRA 0xa60 ;
LDG.E.64 R8, [R4.64+0x18] ;
STG.E.64 [R2.64], R8 ;
LDG.E.64 R10, [R4.64+0x20] ;
STG.E.64 [R2.64+0x8], R10 ;
LDG.E.64 R12, [R4.64+0x28] ;
STG.E.64 [R2.64+0x10], R12 ;
LDG.E R14, [R6.64] ;
BSYNC B0 ;
ISETP.NE.AND P0, PT, R14, 0x2, PT ;
BSSY B0, 0xb20 ;
@P0 BRA 0xb10 ;
LDG.E.64 R8, [R4.64+0x30] ;
STG.E.64 [R2.64], R8 ;
LDG.E.64 R10, [R4.64+0x38] ;
STG.E.64 [R2.64+0x8], R10 ;
LDG.E.64 R12, [R4.64+0x40] ;
STG.E.64 [R2.64+0x10], R12 ;
LDG.E R14, [R6.64] ;
BSYNC B0 ;
ISETP.NE.AND P0, PT, R14, 0x3, PT ;
@P0 EXIT ;
LDG.E.64 R6, [R4.64+0x48] ;
STG.E.64 [R2.64], R6 ;
LDG.E.64 R8, [R4.64+0x50] ;
STG.E.64 [R2.64+0x8], R8 ;
LDG.E.64 R10, [R4.64+0x58] ;
STG.E.64 [R2.64+0x10], R10 ;
EXIT ;
BRA 0xbb0;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
Function : _Z16computeCentroidsPdPiS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ;
S2R R6, SR_CTAID.X ;
S2R R3, SR_TID.X ;
IMAD R6, R6, c[0x0][0x0], R3 ;
ISETP.GT.AND P0, PT, R6, 0x3, PT ;
@P0 EXIT ;
ISETP.LT.AND P0, PT, RZ, c[0x0][0x178], PT ;
@!P0 EXIT ;
IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x178] ;
ULDC.64 UR4, c[0x0][0x118] ;
IMAD.MOV.U32 R3, RZ, RZ, 0x8 ;
IMAD R2, R6, 0x3, RZ ;
LOP3.LUT R5, R5, 0x3, RZ, 0xc0, !PT ;
IMAD.MOV.U32 R4, RZ, RZ, R6 ;
IMAD.WIDE R2, R2, R3, c[0x0][0x170] ;
IADD3 R0, -R5, c[0x0][0x178], RZ ;
IMAD.MOV.U32 R7, RZ, RZ, c[0x0][0x0] ;
ISETP.NE.AND P0, PT, R5, RZ, PT ;
IMAD.MOV.U32 R8, RZ, RZ, c[0x0][0x178] ;
CS2R R10, SRZ ;
IMAD R4, R7, c[0x0][0xc], R4 ;
CS2R R12, SRZ ;
IMAD.MOV.U32 R18, RZ, RZ, RZ ;
IADD3 R7, R8, -0x1, RZ ;
ISETP.GE.AND P1, PT, R4, 0x4, PT ;
CS2R R8, SRZ ;
ISETP.GE.U32.AND P2, PT, R7, 0x3, PT ;
IMAD.MOV.U32 R7, RZ, RZ, RZ ;
@!P2 BRA 0x4d0 ;
IMAD.MOV.U32 R18, RZ, RZ, RZ ;
CS2R R8, SRZ ;
IMAD.MOV.U32 R19, RZ, RZ, R0 ;
IMAD.MOV.U32 R20, RZ, RZ, 0x4 ;
IMAD.WIDE R20, R7, R20, c[0x0][0x168] ;
LDG.E R15, [R20.64] ;
LDG.E R17, [R20.64+0x4] ;
IMAD R14, R7, 0x3, RZ ;
LDG.E R27, [R20.64+0x8] ;
LDG.E R29, [R20.64+0xc] ;
ISETP.NE.AND P4, PT, R15, R6, PT ;
IMAD.MOV.U32 R15, RZ, RZ, 0x8 ;
IMAD.WIDE R14, R14, R15, c[0x0][0x160] ;
ISETP.NE.AND P5, PT, R17, R6, PT ;
@!P4 LDG.E.64 R22, [R14.64+0x8] ;
@!P4 LDG.E.64 R24, [R14.64] ;
@!P4 LDG.E.64 R16, [R14.64+0x10] ;
ISETP.NE.AND P3, PT, R27, R6, PT ;
@!P5 LDG.E.64 R26, [R14.64+0x28] ;
ISETP.NE.AND P2, PT, R29, R6, PT ;
@!P3 LDG.E.64 R20, [R14.64+0x38] ;
@!P4 DADD R10, R10, R22 ;
@!P5 LDG.E.64 R22, [R14.64+0x18] ;
@!P4 DADD R12, R12, R24 ;
@!P5 LDG.E.64 R24, [R14.64+0x20] ;
@!P4 DADD R8, R8, R16 ;
@!P3 LDG.E.64 R16, [R14.64+0x30] ;
@!P5 DADD R8, R8, R26 ;
@!P2 LDG.E.64 R26, [R14.64+0x58] ;
@!P5 DADD R12, R12, R22 ;
@!P3 LDG.E.64 R22, [R14.64+0x40] ;
@!P5 DADD R10, R10, R24 ;
@!P2 LDG.E.64 R24, [R14.64+0x48] ;
@!P3 DADD R12, R12, R16 ;
@!P2 LDG.E.64 R16, [R14.64+0x50] ;
IADD3 R19, R19, -0x4, RZ ;
@!P4 IADD3 R18, R18, 0x1, RZ ;
ISETP.NE.AND P4, PT, R19, RZ, PT ;
@!P3 DADD R10, R10, R20 ;
@!P5 IADD3 R18, R18, 0x1, RZ ;
@!P3 IADD3 R18, R18, 0x1, RZ ;
IADD3 R7, R7, 0x4, RZ ;
@!P2 IADD3 R18, R18, 0x1, RZ ;
@!P3 DADD R8, R8, R22 ;
@!P2 DADD R12, R12, R24 ;
@!P2 DADD R10, R10, R16 ;
@!P2 DADD R8, R8, R26 ;
@P4 BRA 0x200 ;
IMAD.MOV.U32 R14, RZ, RZ, R12 ;
IMAD.MOV.U32 R15, RZ, RZ, R13 ;
@!P0 BRA 0x7d0 ;
IMAD.MOV.U32 R16, RZ, RZ, 0x4 ;
IMAD.WIDE R16, R7, R16, c[0x0][0x168] ;
LDG.E R13, [R16.64] ;
IMAD R12, R7, 0x3, RZ ;
BSSY B0, 0x620 ;
ISETP.NE.AND P2, PT, R5, 0x1, PT ;
ISETP.NE.AND P0, PT, R13, R6, PT ;
IMAD.MOV.U32 R13, RZ, RZ, 0x8 ;
IMAD.WIDE R12, R12, R13, c[0x0][0x160] ;
@P0 BRA 0x610 ;
LDG.E.64 R20, [R12.64] ;
LDG.E.64 R22, [R12.64+0x8] ;
LDG.E.64 R24, [R12.64+0x10] ;
IADD3 R18, R18, 0x1, RZ ;
DADD R14, R20, R14 ;
DADD R10, R22, R10 ;
DADD R8, R24, R8 ;
BSYNC B0 ;
BSSY B0, 0x7d0 ;
@!P2 BRA 0x7c0 ;
LDG.E R7, [R16.64+0x4] ;
BSSY B1, 0x710 ;
ISETP.NE.AND P2, PT, R5, 0x2, PT ;
ISETP.NE.AND P0, PT, R7, R6, PT ;
@P0 BRA 0x700 ;
LDG.E.64 R20, [R12.64+0x18] ;
LDG.E.64 R22, [R12.64+0x20] ;
LDG.E.64 R24, [R12.64+0x28] ;
IADD3 R18, R18, 0x1, RZ ;
DADD R14, R20, R14 ;
DADD R10, R22, R10 ;
DADD R8, R24, R8 ;
BSYNC B1 ;
@!P2 BRA 0x7c0 ;
LDG.E R17, [R16.64+0x8] ;
ISETP.NE.AND P0, PT, R17, R6, PT ;
@P0 BRA 0x7c0 ;
LDG.E.64 R16, [R12.64+0x30] ;
LDG.E.64 R20, [R12.64+0x38] ;
LDG.E.64 R22, [R12.64+0x40] ;
IADD3 R18, R18, 0x1, RZ ;
DADD R14, R16, R14 ;
DADD R10, R20, R10 ;
DADD R8, R22, R8 ;
BSYNC B0 ;
ISETP.NE.AND P0, PT, R18, RZ, PT ;
BSSY B0, 0xc90 ;
@!P0 BRA 0xc80 ;
I2F.F64 R12, R18 ;
IMAD.MOV.U32 R16, RZ, RZ, 0x1 ;
FSETP.GEU.AND P2, PT, |R15|, 6.5827683646048100446e-37, PT ;
BSSY B1, 0x970 ;
MUFU.RCP64H R17, R13 ;
DFMA R20, -R12, R16, 1 ;
DFMA R20, R20, R20, R20 ;
DFMA R20, R16, R20, R16 ;
DFMA R16, -R12, R20, 1 ;
DFMA R16, R20, R16, R20 ;
DMUL R20, R16, R14 ;
DFMA R22, -R12, R20, R14 ;
DFMA R16, R16, R22, R20 ;
FFMA R7, RZ, R13, R17 ;
FSETP.GT.AND P0, PT, |R7|, 1.469367938527859385e-39, PT ;
@P0 BRA P2, 0x960 ;
IMAD.MOV.U32 R20, RZ, RZ, R12 ;
MOV R28, 0x940 ;
IMAD.MOV.U32 R21, RZ, RZ, R13 ;
CALL.REL.NOINC 0xcb0 ;
IMAD.MOV.U32 R16, RZ, RZ, R14 ;
IMAD.MOV.U32 R17, RZ, RZ, R15 ;
BSYNC B1 ;
MUFU.RCP64H R15, R13 ;
IMAD.MOV.U32 R14, RZ, RZ, 0x1 ;
STG.E.64 [R2.64], R16 ;
FSETP.GEU.AND P2, PT, |R11|, 6.5827683646048100446e-37, PT ;
BSSY B1, 0xae0 ;
DFMA R18, -R12, R14, 1 ;
DFMA R18, R18, R18, R18 ;
DFMA R18, R14, R18, R14 ;
DFMA R14, -R12, R18, 1 ;
DFMA R20, R18, R14, R18 ;
DMUL R14, R20, R10 ;
DFMA R18, -R12, R14, R10 ;
DFMA R14, R20, R18, R14 ;
FFMA R7, RZ, R13, R15 ;
FSETP.GT.AND P0, PT, |R7|, 1.469367938527859385e-39, PT ;
@P0 BRA P2, 0xad0 ;
IMAD.MOV.U32 R14, RZ, RZ, R10 ;
MOV R28, 0xad0 ;
IMAD.MOV.U32 R15, RZ, RZ, R11 ;
IMAD.MOV.U32 R20, RZ, RZ, R12 ;
IMAD.MOV.U32 R21, RZ, RZ, R13 ;
CALL.REL.NOINC 0xcb0 ;
BSYNC B1 ;
MUFU.RCP64H R11, R13 ;
IMAD.MOV.U32 R10, RZ, RZ, 0x1 ;
STG.E.64 [R2.64+0x8], R14 ;
FSETP.GEU.AND P2, PT, |R9|, 6.5827683646048100446e-37, PT ;
BSSY B1, 0xc70 ;
DFMA R16, -R12, R10, 1 ;
DFMA R16, R16, R16, R16 ;
DFMA R16, R10, R16, R10 ;
DFMA R10, -R12, R16, 1 ;
DFMA R18, R16, R10, R16 ;
DMUL R10, R18, R8 ;
DFMA R16, -R12, R10, R8 ;
DFMA R10, R18, R16, R10 ;
FFMA R7, RZ, R13, R11 ;
FSETP.GT.AND P0, PT, |R7|, 1.469367938527859385e-39, PT ;
@P0 BRA P2, 0xc60 ;
IMAD.MOV.U32 R14, RZ, RZ, R8 ;
MOV R28, 0xc40 ;
IMAD.MOV.U32 R15, RZ, RZ, R9 ;
IMAD.MOV.U32 R20, RZ, RZ, R12 ;
IMAD.MOV.U32 R21, RZ, RZ, R13 ;
CALL.REL.NOINC 0xcb0 ;
IMAD.MOV.U32 R10, RZ, RZ, R14 ;
IMAD.MOV.U32 R11, RZ, RZ, R15 ;
BSYNC B1 ;
STG.E.64 [R2.64+0x10], R10 ;
BSYNC B0 ;
@!P1 BRA 0x100 ;
EXIT ;
IMAD.MOV.U32 R17, RZ, RZ, R15 ;
FSETP.GEU.AND P0, PT, |R21|.reuse, 1.469367938527859385e-39, PT ;
IMAD.MOV.U32 R16, RZ, RZ, R14 ;
LOP3.LUT R18, R21, 0x800fffff, RZ, 0xc0, !PT ;
IMAD.MOV.U32 R29, RZ, RZ, 0x1ca00000 ;
FSETP.GEU.AND P3, PT, |R17|.reuse, 1.469367938527859385e-39, PT ;
IMAD.MOV.U32 R22, RZ, RZ, 0x1 ;
LOP3.LUT R19, R18, 0x3ff00000, RZ, 0xfc, !PT ;
IMAD.MOV.U32 R18, RZ, RZ, R20 ;
LOP3.LUT R7, R17, 0x7ff00000, RZ, 0xc0, !PT ;
BSSY B2, 0x1260 ;
LOP3.LUT R30, R21, 0x7ff00000, RZ, 0xc0, !PT ;
@!P0 DMUL R18, R20, 8.98846567431157953865e+307 ;
ISETP.GE.U32.AND P2, PT, R7, R30, PT ;
@!P3 LOP3.LUT R14, R21, 0x7ff00000, RZ, 0xc0, !PT ;
@!P3 IMAD.MOV.U32 R24, RZ, RZ, RZ ;
MUFU.RCP64H R23, R19 ;
SEL R15, R29, 0x63400000, !P2 ;
@!P3 ISETP.GE.U32.AND P4, PT, R7, R14, PT ;
IMAD.MOV.U32 R14, RZ, RZ, R16 ;
LOP3.LUT R15, R15, 0x800fffff, R17, 0xf8, !PT ;
@!P3 SEL R25, R29, 0x63400000, !P4 ;
@!P0 LOP3.LUT R30, R19, 0x7ff00000, RZ, 0xc0, !PT ;
@!P3 LOP3.LUT R25, R25, 0x80000000, R17, 0xf8, !PT ;
@!P3 LOP3.LUT R25, R25, 0x100000, RZ, 0xfc, !PT ;
@!P3 DFMA R14, R14, 2, -R24 ;
DFMA R24, R22, -R18, 1 ;
DFMA R24, R24, R24, R24 ;
DFMA R22, R22, R24, R22 ;
DFMA R24, R22, -R18, 1 ;
DFMA R22, R22, R24, R22 ;
DMUL R24, R22, R14 ;
DFMA R26, R24, -R18, R14 ;
DFMA R26, R22, R26, R24 ;
IMAD.MOV.U32 R25, RZ, RZ, R7 ;
@!P3 LOP3.LUT R25, R15, 0x7ff00000, RZ, 0xc0, !PT ;
IADD3 R22, R25, -0x1, RZ ;
ISETP.GT.U32.AND P0, PT, R22, 0x7feffffe, PT ;
IADD3 R22, R30, -0x1, RZ ;
ISETP.GT.U32.OR P0, PT, R22, 0x7feffffe, P0 ;
@P0 BRA 0x1100 ;
LOP3.LUT R22, R21, 0x7ff00000, RZ, 0xc0, !PT ;
ISETP.GE.U32.AND P0, PT, R7.reuse, R22, PT ;
IMAD.IADD R16, R7, 0x1, -R22 ;
SEL R7, R29, 0x63400000, !P0 ;
IMNMX R16, R16, -0x46a00000, !PT ;
IMNMX R16, R16, 0x46a00000, PT ;
IMAD.IADD R7, R16, 0x1, -R7 ;
IMAD.MOV.U32 R16, RZ, RZ, RZ ;
IADD3 R17, R7, 0x7fe00000, RZ ;
DMUL R22, R26, R16 ;
FSETP.GTU.AND P0, PT, |R23|, 1.469367938527859385e-39, PT ;
@P0 BRA 0x1250 ;
DFMA R14, R26, -R18, R14 ;
IMAD.MOV.U32 R16, RZ, RZ, RZ ;
FSETP.NEU.AND P0, PT, R15.reuse, RZ, PT ;
LOP3.LUT R21, R15, 0x80000000, R21, 0x48, !PT ;
LOP3.LUT R17, R21, R17, RZ, 0xfc, !PT ;
@!P0 BRA 0x1250 ;
IMAD.MOV R15, RZ, RZ, -R7 ;
DMUL.RP R16, R26, R16 ;
IMAD.MOV.U32 R14, RZ, RZ, RZ ;
IADD3 R7, -R7, -0x43300000, RZ ;
DFMA R14, R22, -R14, R26 ;
LOP3.LUT R21, R17, R21, RZ, 0x3c, !PT ;
FSETP.NEU.AND P0, PT, |R15|, R7, PT ;
FSEL R22, R16, R22, !P0 ;
FSEL R23, R21, R23, !P0 ;
BRA 0x1250 ;
DSETP.NAN.AND P0, PT, R16, R16, PT ;
@P0 BRA 0x1230 ;
DSETP.NAN.AND P0, PT, R20, R20, PT ;
@P0 BRA 0x1200 ;
ISETP.NE.AND P0, PT, R25, R30, PT ;
IMAD.MOV.U32 R22, RZ, RZ, 0x0 ;
IMAD.MOV.U32 R23, RZ, RZ, -0x80000 ;
@!P0 BRA 0x1250 ;
ISETP.NE.AND P0, PT, R25, 0x7ff00000, PT ;
LOP3.LUT R23, R17, 0x80000000, R21, 0x48, !PT ;
ISETP.EQ.OR P0, PT, R30, RZ, !P0 ;
@P0 LOP3.LUT R7, R23, 0x7ff00000, RZ, 0xfc, !PT ;
@!P0 IMAD.MOV.U32 R22, RZ, RZ, RZ ;
@P0 IMAD.MOV.U32 R22, RZ, RZ, RZ ;
@P0 IMAD.MOV.U32 R23, RZ, RZ, R7 ;
BRA 0x1250 ;
LOP3.LUT R23, R21, 0x80000, RZ, 0xfc, !PT ;
IMAD.MOV.U32 R22, RZ, RZ, R20 ;
BRA 0x1250 ;
LOP3.LUT R23, R17, 0x80000, RZ, 0xfc, !PT ;
IMAD.MOV.U32 R22, RZ, RZ, R16 ;
BSYNC B2 ;
IMAD.MOV.U32 R29, RZ, RZ, 0x0 ;
IMAD.MOV.U32 R14, RZ, RZ, R22 ;
IMAD.MOV.U32 R15, RZ, RZ, R23 ;
RET.REL.NODEC R28 0x0 ;
BRA 0x12a0;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
Function : _Z20findclosestcentroidsPdS_Pii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ;
S2R R32, SR_CTAID.X ;
S2R R3, SR_TID.X ;
IMAD R32, R32, c[0x0][0x0], R3 ;
ISETP.GE.AND P0, PT, R32, c[0x0][0x178], PT ;
@P0 EXIT ;
IMAD.MOV.U32 R3, RZ, RZ, 0x8 ;
HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ;
IMAD R2, R32, 0x3, RZ ;
ULDC.64 UR4, c[0x0][0x118] ;
IMAD.MOV.U32 R33, RZ, RZ, c[0x0][0x0] ;
IMAD.WIDE R2, R2, R3, c[0x0][0x160] ;
IMAD R33, R33, c[0x0][0xc], RZ ;
IADD3 R10, P0, R2, 0x10, RZ ;
IMAD.WIDE R6, R32, R7, c[0x0][0x170] ;
IMAD R5, R33, 0x3, RZ ;
IMAD.X R11, RZ, RZ, R3, P0 ;
IMAD.MOV.U32 R8, RZ, RZ, c[0x0][0x168] ;
LDG.E.64 R12, [R10.64+-0x10] ;
IMAD.MOV.U32 R9, RZ, RZ, c[0x0][0x16c] ;
LDG.E.64 R14, [R10.64+-0x8] ;
LDG.E.64 R2, [R8.64] ;
LDG.E.64 R18, [R8.64+0x8] ;
LDG.E.64 R20, [R8.64+0x10] ;
LDG.E.64 R16, [R10.64] ;
BSSY B0, 0x380 ;
DADD R2, -R2, R12 ;
DADD R18, -R18, R14 ;
DFMA R2, R2, R2, RZ ;
DADD R20, -R20, R16 ;
DFMA R2, R18, R18, R2 ;
DFMA R2, R20, R20, R2 ;
MUFU.RSQ64H R23, R3 ;
IADD3 R22, R3, -0x3500000, RZ ;
IMAD.MOV.U32 R21, RZ, RZ, 0x3fd80000 ;
MOV R20, 0x0 ;
DMUL R18, R22, R22 ;
DFMA R18, R2, -R18, 1 ;
DFMA R20, R18, R20, 0.5 ;
DMUL R18, R22, R18 ;
ISETP.GE.U32.AND P0, PT, R22, 0x7ca00000, PT ;
DFMA R26, R20, R18, R22 ;
DMUL R24, R2, R26 ;
IADD3 R21, R27, -0x100000, RZ ;
IMAD.MOV.U32 R20, RZ, RZ, R26 ;
DFMA R28, R24, -R24, R2 ;
DFMA R18, R28, R20, R24 ;
@!P0 BRA 0x370 ;
IMAD.MOV.U32 R4, RZ, RZ, R26 ;
MOV R0, R28 ;
IMAD.MOV.U32 R23, RZ, RZ, R21 ;
MOV R26, 0x350 ;
CALL.REL.NOINC 0xaf0 ;
IMAD.MOV.U32 R18, RZ, RZ, R22 ;
IMAD.MOV.U32 R19, RZ, RZ, R23 ;
BSYNC B0 ;
LDG.E.64 R2, [R8.64+0x18] ;
LDG.E.64 R20, [R8.64+0x20] ;
LDG.E.64 R22, [R8.64+0x28] ;
BSSY B0, 0x5a0 ;
DADD R2, R12, -R2 ;
DADD R20, R14, -R20 ;
DFMA R2, R2, R2, RZ ;
DADD R22, R16, -R22 ;
DFMA R2, R20, R20, R2 ;
DFMA R2, R22, R22, R2 ;
MOV R22, 0x0 ;
IMAD.MOV.U32 R23, RZ, RZ, 0x3fd80000 ;
MUFU.RSQ64H R27, R3 ;
IADD3 R26, R3, -0x3500000, RZ ;
ISETP.GE.U32.AND P0, PT, R26, 0x7ca00000, PT ;
DMUL R20, R26, R26 ;
DFMA R20, R2, -R20, 1 ;
DFMA R22, R20, R22, 0.5 ;
DMUL R20, R26, R20 ;
DFMA R30, R22, R20, R26 ;
DMUL R24, R2, R30 ;
IADD3 R23, R31, -0x100000, RZ ;
IMAD.MOV.U32 R22, RZ, RZ, R30 ;
DFMA R28, R24, -R24, R2 ;
DFMA R20, R28, R22, R24 ;
@!P0 BRA 0x590 ;
IMAD.MOV.U32 R22, RZ, RZ, R26 ;
MOV R0, R28 ;
IMAD.MOV.U32 R4, RZ, RZ, R30 ;
MOV R26, 0x570 ;
CALL.REL.NOINC 0xaf0 ;
IMAD.MOV.U32 R20, RZ, RZ, R22 ;
IMAD.MOV.U32 R21, RZ, RZ, R23 ;
BSYNC B0 ;
LDG.E.64 R2, [R8.64+0x30] ;
LDG.E.64 R22, [R8.64+0x38] ;
LDG.E.64 R24, [R8.64+0x40] ;
MOV R26, 0x0 ;
IMAD.MOV.U32 R27, RZ, RZ, 0x3fd80000 ;
BSSY B0, 0x7c0 ;
DADD R2, R12, -R2 ;
DADD R22, R14, -R22 ;
DFMA R2, R2, R2, RZ ;
DADD R24, R16, -R24 ;
DFMA R2, R22, R22, R2 ;
DFMA R2, R24, R24, R2 ;
MUFU.RSQ64H R23, R3 ;
IADD3 R22, R3, -0x3500000, RZ ;
ISETP.GE.U32.AND P0, PT, R22, 0x7ca00000, PT ;
DMUL R24, R22, R22 ;
DFMA R24, R2, -R24, 1 ;
DFMA R26, R24, R26, 0.5 ;
DMUL R24, R22, R24 ;
DFMA R34, R26, R24, R22 ;
DMUL R24, R2, R34 ;
IADD3 R27, R35, -0x100000, RZ ;
IMAD.MOV.U32 R26, RZ, RZ, R34 ;
DFMA R28, R24, -R24, R2 ;
DFMA R30, R28, R26, R24 ;
@!P0 BRA 0x7b0 ;
IMAD.MOV.U32 R4, RZ, RZ, R34 ;
MOV R0, R28 ;
IMAD.MOV.U32 R23, RZ, RZ, R27 ;
MOV R26, 0x790 ;
CALL.REL.NOINC 0xaf0 ;
IMAD.MOV.U32 R30, RZ, RZ, R22 ;
IMAD.MOV.U32 R31, RZ, RZ, R23 ;
BSYNC B0 ;
LDG.E.64 R2, [R8.64+0x48] ;
LDG.E.64 R22, [R8.64+0x50] ;
LDG.E.64 R24, [R8.64+0x58] ;
BSSY B0, 0x9e0 ;
DADD R2, R12, -R2 ;
DADD R22, R14, -R22 ;
MOV R14, 0x0 ;
IMAD.MOV.U32 R15, RZ, RZ, 0x3fd80000 ;
DFMA R2, R2, R2, RZ ;
DADD R24, R16, -R24 ;
DFMA R2, R22, R22, R2 ;
DFMA R2, R24, R24, R2 ;
MUFU.RSQ64H R23, R3 ;
IADD3 R22, R3, -0x3500000, RZ ;
ISETP.GE.U32.AND P0, PT, R22, 0x7ca00000, PT ;
DMUL R12, R22, R22 ;
DFMA R12, R2, -R12, 1 ;
DFMA R8, R12, R14, 0.5 ;
DMUL R12, R22, R12 ;
DFMA R14, R8, R12, R22 ;
DMUL R24, R2, R14 ;
IADD3 R9, R15, -0x100000, RZ ;
IMAD.MOV.U32 R8, RZ, RZ, R14 ;
DFMA R28, R24, -R24, R2 ;
DFMA R12, R28, R8, R24 ;
@!P0 BRA 0x9d0 ;
IMAD.MOV.U32 R4, RZ, RZ, R14 ;
MOV R0, R28 ;
IMAD.MOV.U32 R23, RZ, RZ, R9 ;
MOV R26, 0x9b0 ;
CALL.REL.NOINC 0xaf0 ;
IMAD.MOV.U32 R12, RZ, RZ, R22 ;
MOV R13, R23 ;
BSYNC B0 ;
DSETP.GEU.AND P1, PT, R20, R18, PT ;
IMAD.IADD R32, R33, 0x1, R32 ;
IMAD.WIDE R10, R5, 0x8, R10 ;
FSEL R2, R20, R18, !P1 ;
FSEL R3, R21, R19, !P1 ;
SEL R0, RZ, 0x1, P1 ;
DSETP.GEU.AND P0, PT, R30, R2, PT ;
FSEL R2, R30, R2, !P0 ;
FSEL R3, R31, R3, !P0 ;
SEL R0, R0, 0x2, P0 ;
ISETP.GE.AND P0, PT, R32, c[0x0][0x178], PT ;
DSETP.GEU.AND P1, PT, R12, R2, PT ;
SEL R3, R0, 0x3, P1 ;
STG.E [R6.64], R3 ;
IMAD.WIDE R6, R33, 0x4, R6 ;
@!P0 BRA 0x110 ;
EXIT ;
ISETP.GE.U32.AND P0, PT, R22, -0x3400000, PT ;
BSSY B1, 0xd60 ;
IMAD.MOV.U32 R28, RZ, RZ, R0 ;
MOV R22, R4 ;
@!P0 BRA 0xbc0 ;
DFMA.RM R22, R28, R22, R24 ;
IADD3 R24, P0, R22, 0x1, RZ ;
IMAD.X R25, RZ, RZ, R23, P0 ;
DFMA.RP R2, -R22, R24, R2 ;
DSETP.GT.AND P0, PT, R2, RZ, PT ;
FSEL R22, R24, R22, P0 ;
FSEL R23, R25, R23, P0 ;
BRA 0xd50 ;
DSETP.NE.AND P0, PT, R2, RZ, PT ;
@!P0 BRA 0xd40 ;
ISETP.GE.AND P0, PT, R3, RZ, PT ;
@!P0 IMAD.MOV.U32 R22, RZ, RZ, 0x0 ;
@!P0 MOV R23, 0xfff80000 ;
@!P0 BRA 0xd50 ;
ISETP.GT.AND P0, PT, R3, 0x7fefffff, PT ;
@P0 BRA 0xd40 ;
DMUL R2, R2, 8.11296384146066816958e+31 ;
IMAD.MOV.U32 R22, RZ, RZ, RZ ;
MOV R29, 0x3fd80000 ;
IMAD.MOV.U32 R28, RZ, RZ, 0x0 ;
MUFU.RSQ64H R23, R3 ;
DMUL R24, R22, R22 ;
DFMA R24, R2, -R24, 1 ;
DFMA R28, R24, R28, 0.5 ;
DMUL R24, R22, R24 ;
DFMA R24, R28, R24, R22 ;
DMUL R22, R2, R24 ;
IADD3 R25, R25, -0x100000, RZ ;
DFMA R28, R22, -R22, R2 ;
DFMA R22, R24, R28, R22 ;
IADD3 R23, R23, -0x3500000, RZ ;
BRA 0xd50 ;
DADD R22, R2, R2 ;
BSYNC B1 ;
IMAD.MOV.U32 R27, RZ, RZ, 0x0 ;
RET.REL.NODEC R26 0x0 ;
BRA 0xd80;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
```
|
```amdasm
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z20findclosestcentroidsPdS_Pii ; -- Begin function _Z20findclosestcentroidsPdS_Pii
.globl _Z20findclosestcentroidsPdS_Pii
.p2align 8
.type _Z20findclosestcentroidsPdS_Pii,@function
_Z20findclosestcentroidsPdS_Pii: ; @_Z20findclosestcentroidsPdS_Pii
; %bb.0:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x2c
s_load_b32 s10, s[0:1], 0x18
s_add_u32 s2, s0, 32
s_addc_u32 s3, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s8, s4, 0xffff
s_mov_b32 s4, exec_lo
v_mad_u64_u32 v[8:9], null, s15, s8, v[0:1]
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s10, v8
s_cbranch_execz .LBB0_9
; %bb.1: ; %.lr.ph.preheader
s_load_b32 s11, s[2:3], 0x0
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[2:3], s[0:1], 0x10
v_lshl_add_u32 v9, v8, 1, v8
v_mov_b32_e32 v12, v8
s_mov_b32 s12, 0
s_mov_b32 s14, 0
; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
s_waitcnt lgkmcnt(0)
s_mul_i32 s11, s11, s8
s_delay_alu instid0(SALU_CYCLE_1)
s_mul_i32 s13, s11, 3
.LBB0_2: ; %.lr.ph
; =>This Loop Header: Depth=1
; Child Loop BB0_3 Depth 2
; Child Loop BB0_4 Depth 3
; Child Loop BB0_7 Depth 2
v_ashrrev_i32_e32 v10, 31, v9
s_mov_b64 s[8:9], s[6:7]
s_mov_b32 s15, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[10:11], 3, v[9:10]
v_add_co_u32 v13, vcc_lo, s4, v10
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v14, vcc_lo, s5, v11, vcc_lo
.LBB0_3: ; %.preheader
; Parent Loop BB0_2 Depth=1
; => This Loop Header: Depth=2
; Child Loop BB0_4 Depth 3
v_mov_b32_e32 v10, 0
v_mov_b32_e32 v11, 0
s_mov_b64 s[0:1], 0
.LBB0_4: ; Parent Loop BB0_2 Depth=1
; Parent Loop BB0_3 Depth=2
; => This Inner Loop Header: Depth=3
s_delay_alu instid0(SALU_CYCLE_1)
v_add_co_u32 v15, vcc_lo, v13, s0
v_add_co_ci_u32_e32 v16, vcc_lo, s1, v14, vcc_lo
s_add_u32 s16, s8, s0
s_addc_u32 s17, s9, s1
s_add_u32 s0, s0, 8
global_load_b64 v[15:16], v[15:16], off
s_load_b64 s[16:17], s[16:17], 0x0
s_addc_u32 s1, s1, 0
s_cmp_lg_u32 s0, 24
s_waitcnt vmcnt(0) lgkmcnt(0)
v_add_f64 v[15:16], v[15:16], -s[16:17]
s_delay_alu instid0(VALU_DEP_1)
v_fma_f64 v[10:11], v[15:16], v[15:16], v[10:11]
s_cbranch_scc1 .LBB0_4
; %bb.5: ; in Loop: Header=BB0_3 Depth=2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_cmp_gt_f64_e32 vcc_lo, 0x10000000, v[10:11]
s_cmp_eq_u32 s15, 3
v_cndmask_b32_e64 v15, 0, 1, vcc_lo
v_lshlrev_b32_e32 v15, 8, v15
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ldexp_f64 v[10:11], v[10:11], v15
v_rsq_f64_e32 v[15:16], v[10:11]
s_waitcnt_depctr 0xfff
v_mul_f64 v[17:18], v[10:11], v[15:16]
v_mul_f64 v[15:16], v[15:16], 0.5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[19:20], -v[15:16], v[17:18], 0.5
v_fma_f64 v[17:18], v[17:18], v[19:20], v[17:18]
v_fma_f64 v[15:16], v[15:16], v[19:20], v[15:16]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[19:20], -v[17:18], v[17:18], v[10:11]
v_fma_f64 v[17:18], v[19:20], v[15:16], v[17:18]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[19:20], -v[17:18], v[17:18], v[10:11]
v_fma_f64 v[15:16], v[19:20], v[15:16], v[17:18]
v_cndmask_b32_e64 v17, 0, 0xffffff80, vcc_lo
v_cmp_class_f64_e64 vcc_lo, v[10:11], 0x260
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ldexp_f64 v[15:16], v[15:16], v17
v_dual_cndmask_b32 v10, v15, v10 :: v_dual_cndmask_b32 v11, v16, v11
s_cselect_b32 vcc_lo, -1, 0
s_cmp_eq_u32 s15, 2
s_cselect_b32 s0, -1, 0
s_cmp_eq_u32 s15, 1
v_cndmask_b32_e32 v7, v7, v11, vcc_lo
s_cselect_b32 s1, -1, 0
s_cmp_eq_u32 s15, 0
v_cndmask_b32_e32 v6, v6, v10, vcc_lo
s_cselect_b32 vcc_lo, -1, 0
v_cndmask_b32_e64 v5, v5, v11, s0
v_cndmask_b32_e32 v0, v0, v10, vcc_lo
v_cndmask_b32_e64 v4, v4, v10, s0
v_cndmask_b32_e64 v3, v3, v11, s1
v_cndmask_b32_e64 v2, v2, v10, s1
v_cndmask_b32_e32 v1, v1, v11, vcc_lo
s_add_i32 s15, s15, 1
s_add_u32 s8, s8, 24
s_addc_u32 s9, s9, 0
s_cmp_lg_u32 s15, 4
s_cbranch_scc1 .LBB0_3
; %bb.6: ; in Loop: Header=BB0_2 Depth=1
v_mov_b32_e32 v11, v1
v_dual_mov_b32 v13, 0 :: v_dual_mov_b32 v10, v0
s_mov_b64 s[0:1], 0
.LBB0_7: ; Parent Loop BB0_2 Depth=1
; => This Inner Loop Header: Depth=2
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s0, 1
s_cselect_b32 vcc_lo, -1, 0
s_cmp_eq_u32 s0, 2
v_dual_cndmask_b32 v14, v1, v3 :: v_dual_cndmask_b32 v15, v0, v2
s_cselect_b32 vcc_lo, -1, 0
s_cmp_eq_u32 s0, 3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v14, v14, v5, vcc_lo
v_cndmask_b32_e32 v16, v15, v4, vcc_lo
s_cselect_b32 vcc_lo, -1, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_cndmask_b32 v15, v14, v7 :: v_dual_cndmask_b32 v14, v16, v6
v_cmp_lt_f64_e32 vcc_lo, v[14:15], v[10:11]
v_cndmask_b32_e64 v13, v13, s0, vcc_lo
v_dual_cndmask_b32 v11, v11, v15 :: v_dual_cndmask_b32 v10, v10, v14
s_add_u32 s0, s0, 1
s_addc_u32 s1, s1, 0
s_cmp_lg_u32 s0, 4
s_cbranch_scc1 .LBB0_7
; %bb.8: ; in Loop: Header=BB0_2 Depth=1
v_mad_u64_u32 v[10:11], null, s14, s11, v[8:9]
v_add_nc_u32_e32 v12, s11, v12
v_add_nc_u32_e32 v9, s13, v9
s_add_i32 s14, s14, 1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
v_cmp_le_i32_e32 vcc_lo, s10, v12
v_ashrrev_i32_e32 v11, 31, v10
s_or_b32 s12, vcc_lo, s12
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[10:11], 2, v[10:11]
v_add_co_u32 v10, s0, s2, v10
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v11, s0, s3, v11, s0
global_store_b32 v[10:11], v13, off
s_and_not1_b32 exec_lo, exec_lo, s12
s_cbranch_execnz .LBB0_2
.LBB0_9: ; %Flow87
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z20findclosestcentroidsPdS_Pii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 21
.amdhsa_next_free_sgpr 18
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z20findclosestcentroidsPdS_Pii, .Lfunc_end0-_Z20findclosestcentroidsPdS_Pii
; -- End function
.section .AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 744
; NumSgprs: 20
; NumVgprs: 21
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 2
; NumSGPRsForWavesPerEU: 20
; NumVGPRsForWavesPerEU: 21
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
.text
.protected _Z16computeCentroidsPdPiS_i ; -- Begin function _Z16computeCentroidsPdPiS_i
.globl _Z16computeCentroidsPdPiS_i
.p2align 8
.type _Z16computeCentroidsPdPiS_i,@function
_Z16computeCentroidsPdPiS_i: ; @_Z16computeCentroidsPdPiS_i
; %bb.0:
s_load_b32 s4, s[0:1], 0x2c
s_add_u32 s2, s0, 32
s_addc_u32 s3, s1, 0
s_mov_b32 s5, exec_lo
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[6:7], null, s15, s4, v[0:1]
v_cmpx_gt_i32_e32 4, v6
s_cbranch_execz .LBB1_13
; %bb.1: ; %.preheader46.lr.ph
s_clause 0x1
s_load_b32 s14, s[0:1], 0x18
s_load_b64 s[6:7], s[0:1], 0x10
v_lshl_add_u32 v0, v6, 1, v6
s_load_b32 s20, s[2:3], 0x0
s_load_b128 s[16:19], s[0:1], 0x0
v_dual_mov_b32 v13, 0 :: v_dual_mov_b32 v14, v6
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v1, 31, v0
s_mov_b32 s5, 0
s_mov_b32 s21, 0
v_lshlrev_b64 v[0:1], 3, v[0:1]
s_waitcnt lgkmcnt(0)
s_cmp_gt_i32 s14, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v7, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v8, vcc_lo, s7, v1, vcc_lo
s_cselect_b32 s15, -1, 0
s_mul_i32 s20, s20, s4
.LBB1_2: ; %.preheader46
; =>This Loop Header: Depth=1
; Child Loop BB1_4 Depth 2
; Child Loop BB1_6 Depth 3
; Child Loop BB1_11 Depth 2
s_mov_b32 s4, s5
s_mov_b32 s6, s5
s_mov_b32 s7, s5
s_mov_b32 s8, s5
s_mov_b32 s9, s5
v_dual_mov_b32 v0, s4 :: v_dual_mov_b32 v1, s5
v_dual_mov_b32 v2, s6 :: v_dual_mov_b32 v3, s7
v_dual_mov_b32 v4, s8 :: v_dual_mov_b32 v5, s9
v_mov_b32_e32 v9, 0
s_and_not1_b32 vcc_lo, exec_lo, s15
s_cbranch_vccnz .LBB1_9
; %bb.3: ; %.lr.ph.preheader
; in Loop: Header=BB1_2 Depth=1
s_mov_b32 s8, 0
s_delay_alu instid0(SALU_CYCLE_1)
s_mov_b32 s9, s8
s_mov_b32 s10, s8
s_mov_b32 s11, s8
s_mov_b32 s12, s8
s_mov_b32 s13, s8
v_dual_mov_b32 v9, 0 :: v_dual_mov_b32 v0, s8
v_dual_mov_b32 v1, s9 :: v_dual_mov_b32 v2, s10
v_dual_mov_b32 v3, s11 :: v_dual_mov_b32 v4, s12
v_mov_b32_e32 v5, s13
s_mov_b32 s4, s8
.LBB1_4: ; %.lr.ph
; Parent Loop BB1_2 Depth=1
; => This Loop Header: Depth=2
; Child Loop BB1_6 Depth 3
s_delay_alu instid0(SALU_CYCLE_1)
s_lshl_b64 s[0:1], s[4:5], 2
s_mov_b32 s10, exec_lo
s_add_u32 s0, s18, s0
s_addc_u32 s1, s19, s1
s_load_b32 s0, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
v_cmpx_eq_u32_e64 s0, v6
s_cbranch_execz .LBB1_8
; %bb.5: ; in Loop: Header=BB1_4 Depth=2
s_mov_b32 s9, s5
s_mov_b64 s[6:7], 0
s_lshl_b64 s[0:1], s[8:9], 3
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s2, s16, s0
s_addc_u32 s3, s17, s1
.LBB1_6: ; Parent Loop BB1_2 Depth=1
; Parent Loop BB1_4 Depth=2
; => This Inner Loop Header: Depth=3
global_load_b64 v[10:11], v13, s[2:3]
s_cmp_eq_u32 s6, 1
s_cselect_b32 vcc_lo, -1, 0
s_cmp_eq_u32 s6, 2
v_dual_cndmask_b32 v12, v1, v3 :: v_dual_cndmask_b32 v15, v0, v2
s_cselect_b32 s0, -1, 0
s_cmp_eq_u32 s6, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cndmask_b32_e64 v16, v12, v5, s0
v_cndmask_b32_e64 v15, v15, v4, s0
s_cselect_b32 s1, -1, 0
s_add_u32 s6, s6, 1
s_addc_u32 s7, s7, 0
s_add_u32 s2, s2, 8
s_addc_u32 s3, s3, 0
s_cmp_lg_u32 s6, 3
s_waitcnt vmcnt(0)
v_add_f64 v[10:11], v[15:16], v[10:11]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cndmask_b32_e64 v5, v5, v11, s0
v_cndmask_b32_e64 v4, v4, v10, s0
v_dual_cndmask_b32 v3, v3, v11 :: v_dual_cndmask_b32 v2, v2, v10
v_cndmask_b32_e64 v1, v1, v11, s1
v_cndmask_b32_e64 v0, v0, v10, s1
s_cbranch_scc1 .LBB1_6
; %bb.7: ; %.loopexit.loopexit
; in Loop: Header=BB1_4 Depth=2
v_add_nc_u32_e32 v9, 1, v9
.LBB1_8: ; %Flow82
; in Loop: Header=BB1_4 Depth=2
s_or_b32 exec_lo, exec_lo, s10
s_add_i32 s4, s4, 1
s_add_i32 s8, s8, 3
s_cmp_lg_u32 s4, s14
s_cbranch_scc1 .LBB1_4
.LBB1_9: ; %._crit_edge
; in Loop: Header=BB1_2 Depth=1
s_mov_b32 s2, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_ne_u32_e32 0, v9
s_cbranch_execz .LBB1_12
; %bb.10: ; %.preheader
; in Loop: Header=BB1_2 Depth=1
v_cvt_f64_i32_e32 v[9:10], v9
v_dual_mov_b32 v12, v8 :: v_dual_mov_b32 v11, v7
s_mov_b64 s[0:1], 0
.LBB1_11: ; Parent Loop BB1_2 Depth=1
; => This Inner Loop Header: Depth=2
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s0, 1
s_cselect_b32 vcc_lo, -1, 0
s_cmp_eq_u32 s0, 2
v_cndmask_b32_e32 v15, v1, v3, vcc_lo
v_cndmask_b32_e32 v17, v0, v2, vcc_lo
s_cselect_b32 vcc_lo, -1, 0
s_add_u32 s0, s0, 1
s_addc_u32 s1, s1, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_dual_cndmask_b32 v16, v15, v5 :: v_dual_cndmask_b32 v15, v17, v4
s_cmp_lg_u32 s0, 3
v_div_scale_f64 v[17:18], null, v[9:10], v[9:10], v[15:16]
v_div_scale_f64 v[23:24], vcc_lo, v[15:16], v[9:10], v[15:16]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f64_e32 v[19:20], v[17:18]
s_waitcnt_depctr 0xfff
v_fma_f64 v[21:22], -v[17:18], v[19:20], 1.0
v_fma_f64 v[19:20], v[19:20], v[21:22], v[19:20]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[21:22], -v[17:18], v[19:20], 1.0
v_fma_f64 v[19:20], v[19:20], v[21:22], v[19:20]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f64 v[21:22], v[23:24], v[19:20]
v_fma_f64 v[17:18], -v[17:18], v[21:22], v[23:24]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fmas_f64 v[17:18], v[17:18], v[19:20], v[21:22]
v_div_fixup_f64 v[15:16], v[17:18], v[9:10], v[15:16]
global_store_b64 v[11:12], v[15:16], off
v_add_co_u32 v11, vcc_lo, v11, 8
v_add_co_ci_u32_e32 v12, vcc_lo, 0, v12, vcc_lo
s_cbranch_scc1 .LBB1_11
.LBB1_12: ; %Flow81
; in Loop: Header=BB1_2 Depth=1
s_or_b32 exec_lo, exec_lo, s2
v_add_nc_u32_e32 v14, s20, v14
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_lt_i32_e32 vcc_lo, 3, v14
s_or_b32 s21, vcc_lo, s21
s_and_not1_b32 exec_lo, exec_lo, s21
s_cbranch_execnz .LBB1_2
.LBB1_13: ; %._crit_edge58
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z16computeCentroidsPdPiS_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 25
.amdhsa_next_free_sgpr 22
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z16computeCentroidsPdPiS_i, .Lfunc_end1-_Z16computeCentroidsPdPiS_i
; -- End function
.section .AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 760
; NumSgprs: 24
; NumVgprs: 25
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 3
; NumSGPRsForWavesPerEU: 24
; NumVGPRsForWavesPerEU: 25
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
.text
.protected _Z15assign_thru_gpuPdS_Pii ; -- Begin function _Z15assign_thru_gpuPdS_Pii
.globl _Z15assign_thru_gpuPdS_Pii
.p2align 8
.type _Z15assign_thru_gpuPdS_Pii,@function
_Z15assign_thru_gpuPdS_Pii: ; @_Z15assign_thru_gpuPdS_Pii
; %bb.0:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x2c
s_load_b32 s8, s[0:1], 0x18
s_add_u32 s2, s0, 32
s_addc_u32 s3, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s9, s4, 0xffff
s_mov_b32 s4, exec_lo
v_mad_u64_u32 v[1:2], null, s15, s9, v[0:1]
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s8, v1
s_cbranch_execz .LBB2_8
; %bb.1: ; %.lr.ph.preheader
s_load_b32 s2, s[2:3], 0x0
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
v_lshl_add_u32 v2, v1, 1, v1
v_dual_mov_b32 v5, 0 :: v_dual_mov_b32 v0, v1
s_mov_b32 s10, 0
s_mov_b32 s12, 0
s_waitcnt lgkmcnt(0)
s_mul_i32 s9, s2, s9
s_delay_alu instid0(SALU_CYCLE_1)
s_mul_i32 s11, s9, 3
.LBB2_2: ; %.lr.ph
; =>This Loop Header: Depth=1
; Child Loop BB2_3 Depth 2
; Child Loop BB2_5 Depth 3
v_mad_u64_u32 v[3:4], null, s12, s9, v[1:2]
s_mov_b32 s13, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v4, 31, v3
v_lshlrev_b64 v[3:4], 2, v[3:4]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v3, vcc_lo, s0, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo
global_load_b32 v6, v[3:4], off
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[7:8], 3, v[2:3]
v_add_co_u32 v3, vcc_lo, s4, v7
s_waitcnt vmcnt(0)
v_lshl_add_u32 v4, v6, 1, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
v_lshlrev_b64 v[9:10], 3, v[4:5]
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v8, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v7, vcc_lo, s6, v9
v_add_co_ci_u32_e32 v8, vcc_lo, s7, v10, vcc_lo
.LBB2_3: ; Parent Loop BB2_2 Depth=1
; => This Loop Header: Depth=2
; Child Loop BB2_5 Depth 3
s_mov_b32 s14, exec_lo
v_cmpx_eq_u32_e64 s13, v6
s_cbranch_execz .LBB2_6
; %bb.4: ; %.preheader.preheader
; in Loop: Header=BB2_3 Depth=2
s_mov_b64 s[2:3], 0
.LBB2_5: ; %.preheader
; Parent Loop BB2_2 Depth=1
; Parent Loop BB2_3 Depth=2
; => This Inner Loop Header: Depth=3
s_delay_alu instid0(SALU_CYCLE_1)
v_add_co_u32 v9, vcc_lo, v7, s2
v_add_co_ci_u32_e32 v10, vcc_lo, s3, v8, vcc_lo
v_add_co_u32 v11, vcc_lo, v3, s2
v_add_co_ci_u32_e32 v12, vcc_lo, s3, v4, vcc_lo
global_load_b64 v[9:10], v[9:10], off
s_add_u32 s2, s2, 8
s_addc_u32 s3, s3, 0
s_cmp_lg_u32 s2, 24
s_waitcnt vmcnt(0)
global_store_b64 v[11:12], v[9:10], off
s_cbranch_scc1 .LBB2_5
.LBB2_6: ; %Flow46
; in Loop: Header=BB2_3 Depth=2
s_or_b32 exec_lo, exec_lo, s14
s_add_i32 s13, s13, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_lg_u32 s13, 4
s_cbranch_scc1 .LBB2_3
; %bb.7: ; in Loop: Header=BB2_2 Depth=1
v_add_nc_u32_e32 v0, s9, v0
v_add_nc_u32_e32 v2, s11, v2
s_add_i32 s12, s12, 1
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_le_i32_e32 vcc_lo, s8, v0
s_or_b32 s10, vcc_lo, s10
s_and_not1_b32 exec_lo, exec_lo, s10
s_cbranch_execnz .LBB2_2
.LBB2_8: ; %Flow48
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z15assign_thru_gpuPdS_Pii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 13
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end2:
.size _Z15assign_thru_gpuPdS_Pii, .Lfunc_end2-_Z15assign_thru_gpuPdS_Pii
; -- End function
.section .AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 404
; NumSgprs: 18
; NumVgprs: 13
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 13
; Occupancy: 16
; WaveLimiterHint : 1
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object ; @__hip_cuid_
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0 ; 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z20findclosestcentroidsPdS_Pii
.private_segment_fixed_size: 0
.sgpr_count: 20
.sgpr_spill_count: 0
.symbol: _Z20findclosestcentroidsPdS_Pii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 21
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z16computeCentroidsPdPiS_i
.private_segment_fixed_size: 0
.sgpr_count: 24
.sgpr_spill_count: 0
.symbol: _Z16computeCentroidsPdPiS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 25
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z15assign_thru_gpuPdS_Pii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z15assign_thru_gpuPdS_Pii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 13
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
```
| 13,916 | 13,695 |
351 |
Convert the following CUDA host assembly code to AMD host assembly:
```cudaasm
.file "tmpxft_0012da87_00000000-6_k_cudapart.cudafe1.cpp"
.text
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2076:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2076:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "Unable to determine cuda Device count, error is %d count is %d \n"
.align 8
.LC1:
.string "Unable to have rank %d set to cuda device %d, error is %d \n"
.text
.globl cuda_init
.type cuda_init, @function
cuda_init:
.LFB2070:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $24, %rsp
.cfi_def_cfa_offset 48
movl %edi, %ebx
movl %esi, %ebp
movq %fs:40, %rax
movq %rax, 8(%rsp)
xorl %eax, %eax
movl $-1, 4(%rsp)
leaq 4(%rsp), %rdi
call cudaGetDeviceCount@PLT
testl %eax, %eax
jne .L8
movl %ebp, %eax
cltd
idivl 4(%rsp)
movl %edx, %edi
call cudaSetDevice@PLT
movl %eax, %r8d
testl %eax, %eax
jne .L9
movq $0, num(%rip)
movq $0, centroids_c(%rip)
movq $0, centroids_cresult(%rip)
movq $0, idx(%rip)
movslq %ebx, %rbx
leaq (%rbx,%rbx,2), %rsi
salq $3, %rsi
movl $1, %edx
leaq num(%rip), %rdi
call cudaMallocManaged@PLT
movl $1, %edx
movl $96, %esi
leaq centroids_c(%rip), %rdi
call cudaMallocManaged@PLT
movl $1, %edx
movl $96, %esi
leaq centroids_cresult(%rip), %rdi
call cudaMallocManaged@PLT
leaq 0(,%rbx,4), %rsi
movl $1, %edx
leaq idx(%rip), %rdi
call cudaMallocManaged@PLT
movq 8(%rsp), %rax
subq %fs:40, %rax
jne .L10
addq $24, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L8:
.cfi_restore_state
movl 4(%rsp), %ecx
movl %eax, %edx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $-1, %edi
call exit@PLT
.L9:
movl %ebp, %eax
cltd
idivl 4(%rsp)
movl %edx, %ecx
movl %ebp, %edx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $-1, %edi
call exit@PLT
.L10:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2070:
.size cuda_init, .-cuda_init
.globl cuda_free
.type cuda_free, @function
cuda_free:
.LFB2073:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
movq %rsi, %r12
movq %rdx, %rbp
movq %rcx, %rbx
call cudaFree@PLT
movq %r12, %rdi
call cudaFree@PLT
movq %rbp, %rdi
call cudaFree@PLT
movq %rbx, %rdi
call cudaFree@PLT
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2073:
.size cuda_free, .-cuda_free
.globl _Z45__device_stub__Z20findclosestcentroidsPdS_PiiPdS_Pii
.type _Z45__device_stub__Z20findclosestcentroidsPdS_PiiPdS_Pii, @function
_Z45__device_stub__Z20findclosestcentroidsPdS_PiiPdS_Pii:
.LFB2098:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L17
.L13:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L18
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L17:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z20findclosestcentroidsPdS_Pii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L13
.L18:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2098:
.size _Z45__device_stub__Z20findclosestcentroidsPdS_PiiPdS_Pii, .-_Z45__device_stub__Z20findclosestcentroidsPdS_PiiPdS_Pii
.globl _Z20findclosestcentroidsPdS_Pii
.type _Z20findclosestcentroidsPdS_Pii, @function
_Z20findclosestcentroidsPdS_Pii:
.LFB2099:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z45__device_stub__Z20findclosestcentroidsPdS_PiiPdS_Pii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2099:
.size _Z20findclosestcentroidsPdS_Pii, .-_Z20findclosestcentroidsPdS_Pii
.globl _Z41__device_stub__Z16computeCentroidsPdPiS_iPdPiS_i
.type _Z41__device_stub__Z16computeCentroidsPdPiS_iPdPiS_i, @function
_Z41__device_stub__Z16computeCentroidsPdPiS_iPdPiS_i:
.LFB2100:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L25
.L21:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L26
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L25:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z16computeCentroidsPdPiS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L21
.L26:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2100:
.size _Z41__device_stub__Z16computeCentroidsPdPiS_iPdPiS_i, .-_Z41__device_stub__Z16computeCentroidsPdPiS_iPdPiS_i
.globl _Z16computeCentroidsPdPiS_i
.type _Z16computeCentroidsPdPiS_i, @function
_Z16computeCentroidsPdPiS_i:
.LFB2101:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z41__device_stub__Z16computeCentroidsPdPiS_iPdPiS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2101:
.size _Z16computeCentroidsPdPiS_i, .-_Z16computeCentroidsPdPiS_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "%s \n"
.text
.globl k_means_kernel_launch
.type k_means_kernel_launch, @function
k_means_kernel_launch:
.LFB2071:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $56, %rsp
.cfi_def_cfa_offset 96
movq %rdi, %rbx
movq %rsi, %r12
movq %rdx, %rbp
movl %ecx, %r13d
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movl %r9d, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl %r8d, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L34
.L30:
leaq 12(%rsp), %rdi
call cudaGetDeviceCount@PLT
call cudaDeviceSynchronize@PLT
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $32, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L35
.L31:
call cudaDeviceSynchronize@PLT
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L36
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L34:
.cfi_restore_state
movl %r13d, %ecx
movq %rbp, %rdx
movq %r12, %rsi
movq %rbx, %rdi
call _Z45__device_stub__Z20findclosestcentroidsPdS_PiiPdS_Pii
jmp .L30
.L35:
movl %r13d, %ecx
movq %r12, %rdx
movq %rbp, %rsi
movq %rbx, %rdi
call _Z41__device_stub__Z16computeCentroidsPdPiS_iPdPiS_i
jmp .L31
.L36:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2071:
.size k_means_kernel_launch, .-k_means_kernel_launch
.globl _Z40__device_stub__Z15assign_thru_gpuPdS_PiiPdS_Pii
.type _Z40__device_stub__Z15assign_thru_gpuPdS_PiiPdS_Pii, @function
_Z40__device_stub__Z15assign_thru_gpuPdS_PiiPdS_Pii:
.LFB2102:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L41
.L37:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L42
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L41:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z15assign_thru_gpuPdS_Pii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L37
.L42:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2102:
.size _Z40__device_stub__Z15assign_thru_gpuPdS_PiiPdS_Pii, .-_Z40__device_stub__Z15assign_thru_gpuPdS_PiiPdS_Pii
.globl _Z15assign_thru_gpuPdS_Pii
.type _Z15assign_thru_gpuPdS_Pii, @function
_Z15assign_thru_gpuPdS_Pii:
.LFB2103:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z40__device_stub__Z15assign_thru_gpuPdS_PiiPdS_Pii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2103:
.size _Z15assign_thru_gpuPdS_Pii, .-_Z15assign_thru_gpuPdS_Pii
.globl assign
.type assign, @function
assign:
.LFB2072:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $40, %rsp
.cfi_def_cfa_offset 80
movq %rdi, %rbx
movq %rsi, %rbp
movq %rdx, %r12
movl %ecx, %r13d
movl %r9d, 20(%rsp)
movl $1, 24(%rsp)
movl %r8d, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L48
.L46:
call cudaDeviceSynchronize@PLT
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L48:
.cfi_restore_state
movl %r13d, %ecx
movq %r12, %rdx
movq %rbp, %rsi
movq %rbx, %rdi
call _Z40__device_stub__Z15assign_thru_gpuPdS_PiiPdS_Pii
jmp .L46
.cfi_endproc
.LFE2072:
.size assign, .-assign
.section .rodata.str1.1
.LC3:
.string "_Z15assign_thru_gpuPdS_Pii"
.LC4:
.string "_Z16computeCentroidsPdPiS_i"
.section .rodata.str1.8
.align 8
.LC5:
.string "_Z20findclosestcentroidsPdS_Pii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2105:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z15assign_thru_gpuPdS_Pii(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z16computeCentroidsPdPiS_i(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _Z20findclosestcentroidsPdS_Pii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2105:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
```
|
```amdasm
.text
.file "k_cudapart.hip"
.globl _Z35__device_stub__findclosestcentroidsPdS_Pii # -- Begin function _Z35__device_stub__findclosestcentroidsPdS_Pii
.type _Z35__device_stub__findclosestcentroidsPdS_Pii,@function
_Z35__device_stub__findclosestcentroidsPdS_Pii: # @_Z35__device_stub__findclosestcentroidsPdS_Pii
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $112, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 40(%rsp), %rax
movq %rdi, (%rax)
leaq 32(%rsp), %rdi
movq %rsi, (%rdi)
leaq 24(%rsp), %rsi
movq %rdx, (%rsi)
leaq 4(%rsp), %rdx
movl %ecx, (%rdx)
leaq 80(%rsp), %rbx
movq %rax, (%rbx)
movq %rdi, 8(%rbx)
movq %rsi, 16(%rbx)
movq %rdx, 24(%rbx)
leaq 64(%rsp), %r14
leaq 48(%rsp), %r15
leaq 16(%rsp), %r12
leaq 8(%rsp), %r13
movq %r14, %rdi
movq %r15, %rsi
movq %r12, %rdx
movq %r13, %rcx
callq __hipPopCallConfiguration
movq (%r14), %rsi
movl 8(%r14), %edx
movq (%r15), %rcx
movl 8(%r15), %r8d
movl $_Z20findclosestcentroidsPdS_Pii, %edi
movq %rbx, %r9
pushq (%r13)
.cfi_adjust_cfa_offset 8
pushq (%r12)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $128, %rsp
.cfi_adjust_cfa_offset -128
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z35__device_stub__findclosestcentroidsPdS_Pii, .Lfunc_end0-_Z35__device_stub__findclosestcentroidsPdS_Pii
.cfi_endproc
# -- End function
.globl _Z31__device_stub__computeCentroidsPdPiS_i # -- Begin function _Z31__device_stub__computeCentroidsPdPiS_i
.type _Z31__device_stub__computeCentroidsPdPiS_i,@function
_Z31__device_stub__computeCentroidsPdPiS_i: # @_Z31__device_stub__computeCentroidsPdPiS_i
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $112, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 40(%rsp), %rax
movq %rdi, (%rax)
leaq 32(%rsp), %rdi
movq %rsi, (%rdi)
leaq 24(%rsp), %rsi
movq %rdx, (%rsi)
leaq 4(%rsp), %rdx
movl %ecx, (%rdx)
leaq 80(%rsp), %rbx
movq %rax, (%rbx)
movq %rdi, 8(%rbx)
movq %rsi, 16(%rbx)
movq %rdx, 24(%rbx)
leaq 64(%rsp), %r14
leaq 48(%rsp), %r15
leaq 16(%rsp), %r12
leaq 8(%rsp), %r13
movq %r14, %rdi
movq %r15, %rsi
movq %r12, %rdx
movq %r13, %rcx
callq __hipPopCallConfiguration
movq (%r14), %rsi
movl 8(%r14), %edx
movq (%r15), %rcx
movl 8(%r15), %r8d
movl $_Z16computeCentroidsPdPiS_i, %edi
movq %rbx, %r9
pushq (%r13)
.cfi_adjust_cfa_offset 8
pushq (%r12)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $128, %rsp
.cfi_adjust_cfa_offset -128
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z31__device_stub__computeCentroidsPdPiS_i, .Lfunc_end1-_Z31__device_stub__computeCentroidsPdPiS_i
.cfi_endproc
# -- End function
.globl _Z30__device_stub__assign_thru_gpuPdS_Pii # -- Begin function _Z30__device_stub__assign_thru_gpuPdS_Pii
.type _Z30__device_stub__assign_thru_gpuPdS_Pii,@function
_Z30__device_stub__assign_thru_gpuPdS_Pii: # @_Z30__device_stub__assign_thru_gpuPdS_Pii
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $112, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 40(%rsp), %rax
movq %rdi, (%rax)
leaq 32(%rsp), %rdi
movq %rsi, (%rdi)
leaq 24(%rsp), %rsi
movq %rdx, (%rsi)
leaq 4(%rsp), %rdx
movl %ecx, (%rdx)
leaq 80(%rsp), %rbx
movq %rax, (%rbx)
movq %rdi, 8(%rbx)
movq %rsi, 16(%rbx)
movq %rdx, 24(%rbx)
leaq 64(%rsp), %r14
leaq 48(%rsp), %r15
leaq 16(%rsp), %r12
leaq 8(%rsp), %r13
movq %r14, %rdi
movq %r15, %rsi
movq %r12, %rdx
movq %r13, %rcx
callq __hipPopCallConfiguration
movq (%r14), %rsi
movl 8(%r14), %edx
movq (%r15), %rcx
movl 8(%r15), %r8d
movl $_Z15assign_thru_gpuPdS_Pii, %edi
movq %rbx, %r9
pushq (%r13)
.cfi_adjust_cfa_offset 8
pushq (%r12)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $128, %rsp
.cfi_adjust_cfa_offset -128
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size _Z30__device_stub__assign_thru_gpuPdS_Pii, .Lfunc_end2-_Z30__device_stub__assign_thru_gpuPdS_Pii
.cfi_endproc
# -- End function
.globl cuda_init # -- Begin function cuda_init
.type cuda_init,@function
cuda_init: # @cuda_init
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $16, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %rbp, -16
movl %esi, %ebx
movl %edi, %ebp
leaq 12(%rsp), %r14
movl $-1, (%r14)
movq %r14, %rdi
callq hipGetDeviceCount
movl (%r14), %ecx
testl %eax, %eax
jne .LBB3_3
# %bb.1:
movl %ebx, %eax
cltd
idivl %ecx
movl %edx, %edi
callq hipSetDevice
testl %eax, %eax
jne .LBB3_5
# %bb.2:
xorl %eax, %eax
movq %rax, num(%rip)
movq %rax, centroids_c(%rip)
movq %rax, centroids_cresult(%rip)
movq %rax, idx(%rip)
movslq %ebp, %rbx
leaq (,%rbx,8), %rax
leaq (%rax,%rax,2), %rsi
movl $num, %edi
movl $1, %edx
callq hipMallocManaged
movl $centroids_c, %edi
movl $96, %esi
movl $1, %edx
callq hipMallocManaged
movl $centroids_cresult, %edi
movl $96, %esi
movl $1, %edx
callq hipMallocManaged
shlq $2, %rbx
movl $idx, %edi
movq %rbx, %rsi
movl $1, %edx
callq hipMallocManaged
addq $16, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB3_3:
.cfi_def_cfa_offset 48
movl $.L.str, %edi
movl %eax, %esi
movl %ecx, %edx
xorl %eax, %eax
callq printf
jmp .LBB3_4
.LBB3_5:
movl %eax, %ecx
movl %ebx, %eax
cltd
idivl 12(%rsp)
movl $.L.str.1, %edi
movl %ebx, %esi
xorl %eax, %eax
callq printf
.LBB3_4:
movl $-1, %edi
callq exit
.Lfunc_end3:
.size cuda_init, .Lfunc_end3-cuda_init
.cfi_endproc
# -- End function
.globl k_means_kernel_launch # -- Begin function k_means_kernel_launch
.type k_means_kernel_launch,@function
k_means_kernel_launch: # @k_means_kernel_launch
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $16, %rsp
.cfi_def_cfa_offset 64
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl %ecx, %ebx
movq %rdx, %r15
movq %rsi, %r14
movq %rdi, %r12
movabsq $4294967296, %r13 # imm = 0x100000000
movl %r8d, %edi
btsq $32, %rdi
movl %r9d, %edx
btsq $32, %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_2
# %bb.1:
movq %r12, %rdi
movq %r14, %rsi
movq %r15, %rdx
movl %ebx, %ecx
callq _Z35__device_stub__findclosestcentroidsPdS_Pii
.LBB4_2:
leaq 12(%rsp), %rdi
callq hipGetDeviceCount
callq hipDeviceSynchronize
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.2, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
leaq 1(%r13), %rdi
addq $32, %r13
movl $1, %esi
movq %r13, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_4
# %bb.3:
movq %r12, %rdi
movq %r15, %rsi
movq %r14, %rdx
movl %ebx, %ecx
callq _Z31__device_stub__computeCentroidsPdPiS_i
.LBB4_4:
callq hipDeviceSynchronize
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.2, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
addq $16, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end4:
.size k_means_kernel_launch, .Lfunc_end4-k_means_kernel_launch
.cfi_endproc
# -- End function
.globl assign # -- Begin function assign
.type assign,@function
assign: # @assign
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
pushq %rax
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl %ecx, %ebx
movq %rdx, %r14
movq %rsi, %r15
movq %rdi, %r12
movl %r8d, %edi
btsq $32, %rdi
movl %r9d, %edx
btsq $32, %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB5_2
# %bb.1:
movq %r12, %rdi
movq %r15, %rsi
movq %r14, %rdx
movl %ebx, %ecx
callq _Z30__device_stub__assign_thru_gpuPdS_Pii
.LBB5_2:
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
jmp hipDeviceSynchronize # TAILCALL
.Lfunc_end5:
.size assign, .Lfunc_end5-assign
.cfi_endproc
# -- End function
.globl cuda_free # -- Begin function cuda_free
.type cuda_free,@function
cuda_free: # @cuda_free
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rcx, %rbx
movq %rdx, %r14
movq %rsi, %r15
callq hipFree
movq %r15, %rdi
callq hipFree
movq %r14, %rdi
callq hipFree
movq %rbx, %rdi
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
jmp hipFree # TAILCALL
.Lfunc_end6:
.size cuda_free, .Lfunc_end6-cuda_free
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
movq __hip_gpubin_handle(%rip), %rbx
testq %rbx, %rbx
jne .LBB7_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, %rbx
movq %rax, __hip_gpubin_handle(%rip)
.LBB7_2:
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z20findclosestcentroidsPdS_Pii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z16computeCentroidsPdPiS_i, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15assign_thru_gpuPdS_Pii, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end7:
.size __hip_module_ctor, .Lfunc_end7-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB8_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB8_2:
retq
.Lfunc_end8:
.size __hip_module_dtor, .Lfunc_end8-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z20findclosestcentroidsPdS_Pii,@object # @_Z20findclosestcentroidsPdS_Pii
.section .rodata,"a",@progbits
.globl _Z20findclosestcentroidsPdS_Pii
.p2align 3, 0x0
_Z20findclosestcentroidsPdS_Pii:
.quad _Z35__device_stub__findclosestcentroidsPdS_Pii
.size _Z20findclosestcentroidsPdS_Pii, 8
.type _Z16computeCentroidsPdPiS_i,@object # @_Z16computeCentroidsPdPiS_i
.globl _Z16computeCentroidsPdPiS_i
.p2align 3, 0x0
_Z16computeCentroidsPdPiS_i:
.quad _Z31__device_stub__computeCentroidsPdPiS_i
.size _Z16computeCentroidsPdPiS_i, 8
.type _Z15assign_thru_gpuPdS_Pii,@object # @_Z15assign_thru_gpuPdS_Pii
.globl _Z15assign_thru_gpuPdS_Pii
.p2align 3, 0x0
_Z15assign_thru_gpuPdS_Pii:
.quad _Z30__device_stub__assign_thru_gpuPdS_Pii
.size _Z15assign_thru_gpuPdS_Pii, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Unable to determine cuda Device count, error is %d count is %d \n"
.size .L.str, 65
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Unable to have rank %d set to cuda device %d, error is %d \n"
.size .L.str.1, 60
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "%s \n"
.size .L.str.2, 5
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z20findclosestcentroidsPdS_Pii"
.size .L__unnamed_1, 32
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z16computeCentroidsPdPiS_i"
.size .L__unnamed_2, 28
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z15assign_thru_gpuPdS_Pii"
.size .L__unnamed_3, 27
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z35__device_stub__findclosestcentroidsPdS_Pii
.addrsig_sym _Z31__device_stub__computeCentroidsPdPiS_i
.addrsig_sym _Z30__device_stub__assign_thru_gpuPdS_Pii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z20findclosestcentroidsPdS_Pii
.addrsig_sym _Z16computeCentroidsPdPiS_i
.addrsig_sym _Z15assign_thru_gpuPdS_Pii
.addrsig_sym num
.addrsig_sym centroids_c
.addrsig_sym centroids_cresult
.addrsig_sym idx
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
```
| 7,228 | 7,434 |
358 |
Convert the following CUDA device assembly code to AMD device assembly:
```cudaasm
code for sm_80
Function : DrawLineKernel
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ;
S2R R0, SR_CTAID.Y ;
S2R R3, SR_CTAID.X ;
S2R R5, SR_TID.X ;
IMAD R0, R0, c[0x0][0xc], R3 ;
IMAD R0, R0, c[0x0][0x0], R5 ;
ISETP.GE.AND P0, PT, R0, c[0x0][0x168], PT ;
@P0 EXIT ;
I2F R3, R0 ;
IMAD.MOV.U32 R5, RZ, RZ, c[0x3][0xc] ;
BSSY B0, 0x170 ;
MUFU.RCP R2, c[0x3][0xc] ;
FCHK P0, R3, c[0x3][0xc] ;
FFMA R5, R2, -R5, 1 ;
FFMA R2, R2, R5, R2 ;
FFMA R4, R3, R2, RZ ;
FFMA R5, R4, -c[0x3][0xc], R3 ;
FFMA R2, R2, R5, R4 ;
@!P0 BRA 0x160 ;
MOV R2, 0x150 ;
CALL.REL.NOINC 0x280 ;
IMAD.MOV.U32 R2, RZ, RZ, R4 ;
BSYNC B0 ;
IMAD.MOV.U32 R3, RZ, RZ, c[0x3][0x4] ;
FADD R2, R2, c[0x3][0x14] ;
FFMA R2, R2, R3, c[0x3][0x8] ;
FADD R2, R2, -c[0x3][0x18] ;
FMUL R2, R2, c[0x3][0x10] ;
F2I.TRUNC.NTZ R2, R2 ;
IADD3 R5, -R2, c[0x3][0x0], RZ ;
ISETP.GE.AND P0, PT, R5, 0x1, PT ;
ISETP.LT.OR P0, PT, R2, 0x1, !P0 ;
@P0 EXIT ;
IMAD.MOV.U32 R3, RZ, RZ, 0x4 ;
ULDC.64 UR4, c[0x0][0x118] ;
IMAD R2, R5, c[0x3][0x0], R0 ;
IMAD.MOV.U32 R5, RZ, RZ, -0x10000 ;
IMAD.WIDE R2, R2, R3, c[0x0][0x160] ;
STG.E [R2.64], R5 ;
EXIT ;
IMAD.MOV.U32 R11, RZ, RZ, c[0x3][0xc] ;
SHF.R.U32.HI R4, RZ, 0x17, R3.reuse ;
BSSY B1, 0x8f0 ;
IMAD.MOV.U32 R6, RZ, RZ, R3 ;
SHF.R.U32.HI R5, RZ, 0x17, R11 ;
IMAD.MOV.U32 R7, RZ, RZ, c[0x3][0xc] ;
LOP3.LUT R4, R4, 0xff, RZ, 0xc0, !PT ;
LOP3.LUT R5, R5, 0xff, RZ, 0xc0, !PT ;
IADD3 R9, R4, -0x1, RZ ;
IADD3 R10, R5, -0x1, RZ ;
ISETP.GT.U32.AND P0, PT, R10, 0xfd, PT ;
ISETP.GT.U32.OR P0, PT, R9, 0xfd, P0 ;
@!P0 IMAD.MOV.U32 R8, RZ, RZ, RZ ;
@!P0 BRA 0x4d0 ;
FSETP.GTU.FTZ.AND P1, PT, |R11|, +INF , PT ;
FSETP.GTU.FTZ.AND P0, PT, |R3|, +INF , PT ;
PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ;
@P0 BRA 0x8d0 ;
LOP3.LUT P0, RZ, R7, 0x7fffffff, R6, 0xc8, !PT ;
@!P0 BRA 0x8b0 ;
FSETP.NEU.FTZ.AND P2, PT, |R3|, +INF , PT ;
FSETP.NEU.FTZ.AND P1, PT, |R11|, +INF , PT ;
FSETP.NEU.FTZ.AND P0, PT, |R3|, +INF , PT ;
@!P1 BRA !P2, 0x8b0 ;
LOP3.LUT P2, RZ, R6, 0x7fffffff, RZ, 0xc0, !PT ;
PLOP3.LUT P1, PT, P1, P2, PT, 0x2a, 0x0 ;
@P1 BRA 0x890 ;
LOP3.LUT P1, RZ, R7, 0x7fffffff, RZ, 0xc0, !PT ;
PLOP3.LUT P0, PT, P0, P1, PT, 0x2a, 0x0 ;
@P0 BRA 0x860 ;
ISETP.GE.AND P0, PT, R9, RZ, PT ;
ISETP.GE.AND P1, PT, R10, RZ, PT ;
@P0 IMAD.MOV.U32 R8, RZ, RZ, RZ ;
@!P0 IMAD.MOV.U32 R8, RZ, RZ, -0x40 ;
@!P0 FFMA R6, R3, 1.84467440737095516160e+19, RZ ;
@!P1 FFMA R7, R11, 1.84467440737095516160e+19, RZ ;
@!P1 IADD3 R8, R8, 0x40, RZ ;
LEA R10, R5, 0xc0800000, 0x17 ;
BSSY B2, 0x850 ;
IADD3 R4, R4, -0x7f, RZ ;
IMAD.IADD R10, R7, 0x1, -R10 ;
IADD3 R5, R4.reuse, 0x7f, -R5 ;
IMAD R6, R4, -0x800000, R6 ;
MUFU.RCP R3, R10 ;
FADD.FTZ R7, -R10, -RZ ;
IMAD.IADD R5, R5, 0x1, R8 ;
FFMA R12, R3, R7, 1 ;
FFMA R9, R3, R12, R3 ;
FFMA R3, R6, R9, RZ ;
FFMA R12, R7, R3, R6 ;
FFMA R12, R9, R12, R3 ;
FFMA R7, R7, R12, R6 ;
FFMA R3, R9, R7, R12 ;
SHF.R.U32.HI R4, RZ, 0x17, R3 ;
LOP3.LUT R4, R4, 0xff, RZ, 0xc0, !PT ;
IMAD.IADD R8, R4, 0x1, R5 ;
IADD3 R4, R8, -0x1, RZ ;
ISETP.GE.U32.AND P0, PT, R4, 0xfe, PT ;
@!P0 BRA 0x830 ;
ISETP.GT.AND P0, PT, R8, 0xfe, PT ;
@P0 BRA 0x800 ;
ISETP.GE.AND P0, PT, R8, 0x1, PT ;
@P0 BRA 0x840 ;
ISETP.GE.AND P0, PT, R8, -0x18, PT ;
LOP3.LUT R3, R3, 0x80000000, RZ, 0xc0, !PT ;
@!P0 BRA 0x840 ;
FFMA.RZ R4, R9.reuse, R7.reuse, R12.reuse ;
ISETP.NE.AND P2, PT, R8.reuse, RZ, PT ;
FFMA.RM R5, R9.reuse, R7.reuse, R12.reuse ;
ISETP.NE.AND P1, PT, R8, RZ, PT ;
LOP3.LUT R6, R4, 0x7fffff, RZ, 0xc0, !PT ;
FFMA.RP R4, R9, R7, R12 ;
IADD3 R7, R8, 0x20, RZ ;
IMAD.MOV R8, RZ, RZ, -R8 ;
LOP3.LUT R6, R6, 0x800000, RZ, 0xfc, !PT ;
FSETP.NEU.FTZ.AND P0, PT, R4, R5, PT ;
SHF.L.U32 R7, R6, R7, RZ ;
SEL R5, R8, RZ, P2 ;
ISETP.NE.AND P1, PT, R7, RZ, P1 ;
SHF.R.U32.HI R5, RZ, R5, R6 ;
PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ;
SHF.R.U32.HI R7, RZ, 0x1, R5 ;
SEL R4, RZ, 0x1, !P0 ;
LOP3.LUT R4, R4, 0x1, R7, 0xf8, !PT ;
LOP3.LUT R4, R4, R5, RZ, 0xc0, !PT ;
IMAD.IADD R4, R7, 0x1, R4 ;
LOP3.LUT R3, R4, R3, RZ, 0xfc, !PT ;
BRA 0x840 ;
LOP3.LUT R3, R3, 0x80000000, RZ, 0xc0, !PT ;
LOP3.LUT R3, R3, 0x7f800000, RZ, 0xfc, !PT ;
BRA 0x840 ;
IMAD R3, R5, 0x800000, R3 ;
BSYNC B2 ;
BRA 0x8e0 ;
LOP3.LUT R3, R7, 0x80000000, R6, 0x48, !PT ;
LOP3.LUT R3, R3, 0x7f800000, RZ, 0xfc, !PT ;
BRA 0x8e0 ;
LOP3.LUT R3, R7, 0x80000000, R6, 0x48, !PT ;
BRA 0x8e0 ;
MUFU.RSQ R3, -QNAN ;
BRA 0x8e0 ;
FADD.FTZ R3, R3, c[0x3][0xc] ;
BSYNC B1 ;
IMAD.MOV.U32 R4, RZ, RZ, R3 ;
IMAD.MOV.U32 R3, RZ, RZ, 0x0 ;
RET.REL.NODEC R2 0x0 ;
BRA 0x920;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
```
|
```amdasm
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected DrawLineKernel ; -- Begin function DrawLineKernel
.globl DrawLineKernel
.p2align 8
.type DrawLineKernel,@function
DrawLineKernel: ; @DrawLineKernel
; %bb.0:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x10
s_load_b32 s5, s[0:1], 0x1c
s_getpc_b64 s[2:3]
s_add_u32 s2, s2, D_XSCALE@rel32@lo+4
s_addc_u32 s3, s3, D_XSCALE@rel32@hi+12
s_load_b32 s8, s[2:3], 0x0
s_waitcnt lgkmcnt(0)
s_mul_i32 s2, s4, s15
s_and_b32 s3, s5, 0xffff
s_add_i32 s2, s2, s14
s_delay_alu instid0(SALU_CYCLE_1)
v_mad_u64_u32 v[1:2], null, s2, s3, v[0:1]
s_getpc_b64 s[2:3]
s_add_u32 s2, s2, D_XMIN@rel32@lo+4
s_addc_u32 s3, s3, D_XMIN@rel32@hi+12
s_getpc_b64 s[4:5]
s_add_u32 s4, s4, D_K@rel32@lo+4
s_addc_u32 s5, s5, D_K@rel32@hi+12
s_load_b32 s9, s[2:3], 0x0
s_getpc_b64 s[6:7]
s_add_u32 s6, s6, D_Q@rel32@lo+4
s_addc_u32 s7, s7, D_Q@rel32@hi+12
s_load_b32 s10, s[4:5], 0x0
s_load_b32 s6, s[6:7], 0x0
v_cvt_f32_i32_e32 v0, v1
s_getpc_b64 s[2:3]
s_add_u32 s2, s2, D_YMIN@rel32@lo+4
s_addc_u32 s3, s3, D_YMIN@rel32@hi+12
s_getpc_b64 s[4:5]
s_add_u32 s4, s4, D_YSCALE@rel32@lo+4
s_addc_u32 s5, s5, D_YSCALE@rel32@hi+12
s_load_b32 s7, s[2:3], 0x0
s_load_b32 s4, s[4:5], 0x0
v_div_scale_f32 v2, null, s8, s8, v0
v_div_scale_f32 v5, vcc_lo, v0, s8, v0
s_getpc_b64 s[2:3]
s_add_u32 s2, s2, D_SIZE@rel32@lo+4
s_addc_u32 s3, s3, D_SIZE@rel32@hi+12
v_rcp_f32_e32 v3, v2
s_load_b32 s3, s[2:3], 0x0
s_load_b32 s2, s[0:1], 0x8
s_waitcnt_depctr 0xfff
v_fma_f32 v4, -v2, v3, 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v3, v4, v3
v_mul_f32_e32 v4, v5, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v6, -v2, v4, v5
v_fmac_f32_e32 v4, v6, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v2, -v2, v4, v5
v_div_fmas_f32 v2, v2, v3, v4
s_waitcnt lgkmcnt(0)
v_cmp_gt_i32_e32 vcc_lo, s2, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fixup_f32 v0, v2, s8, v0
v_add_f32_e32 v0, s9, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v0, s10, v0, s6
v_subrev_f32_e32 v0, s7, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v0, s4, v0
v_cvt_i32_f32_e32 v2, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v0, s3, v2
v_min_i32_e32 v2, v2, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_lt_i32_e64 s2, 0, v2
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s4, s2
s_cbranch_execz .LBB0_2
; %bb.1:
s_load_b64 s[0:1], s[0:1], 0x0
v_mad_u64_u32 v[2:3], null, v0, s3, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[0:1], 2, v[2:3]
v_mov_b32_e32 v2, 0xffff0000
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v2, off
.LBB0_2: ; %.critedge
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel DrawLineKernel
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size DrawLineKernel, .Lfunc_end0-DrawLineKernel
; -- End function
.section .AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 512
; NumSgprs: 18
; NumVgprs: 7
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 7
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.protected D_SIZE ; @D_SIZE
.type D_SIZE,@object
.section .bss,"aw",@nobits
.globl D_SIZE
.p2align 2, 0x0
D_SIZE:
.long 0 ; 0x0
.size D_SIZE, 4
.protected D_K ; @D_K
.type D_K,@object
.globl D_K
.p2align 2, 0x0
D_K:
.long 0x00000000 ; float 0
.size D_K, 4
.protected D_Q ; @D_Q
.type D_Q,@object
.globl D_Q
.p2align 2, 0x0
D_Q:
.long 0x00000000 ; float 0
.size D_Q, 4
.protected D_XSCALE ; @D_XSCALE
.type D_XSCALE,@object
.globl D_XSCALE
.p2align 2, 0x0
D_XSCALE:
.long 0x00000000 ; float 0
.size D_XSCALE, 4
.protected D_YSCALE ; @D_YSCALE
.type D_YSCALE,@object
.globl D_YSCALE
.p2align 2, 0x0
D_YSCALE:
.long 0x00000000 ; float 0
.size D_YSCALE, 4
.protected D_XMIN ; @D_XMIN
.type D_XMIN,@object
.globl D_XMIN
.p2align 2, 0x0
D_XMIN:
.long 0x00000000 ; float 0
.size D_XMIN, 4
.protected D_YMIN ; @D_YMIN
.type D_YMIN,@object
.globl D_YMIN
.p2align 2, 0x0
D_YMIN:
.long 0x00000000 ; float 0
.size D_YMIN, 4
.type __hip_cuid_,@object ; @__hip_cuid_
.globl __hip_cuid_
__hip_cuid_:
.byte 0 ; 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym D_SIZE
.addrsig_sym D_K
.addrsig_sym D_Q
.addrsig_sym D_XSCALE
.addrsig_sym D_YSCALE
.addrsig_sym D_XMIN
.addrsig_sym D_YMIN
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: DrawLineKernel
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: DrawLineKernel.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
```
| 2,956 | 4,131 |
359 |
Convert the following CUDA host assembly code to AMD host assembly:
```cudaasm
.file "tmpxft_000ef1bb_00000000-6_DrawLineKernel.cudafe1.cpp"
.text
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z35__device_stub__Z14DrawLineKernelPjiPji
.type _Z35__device_stub__Z14DrawLineKernelPjiPji, @function
_Z35__device_stub__Z14DrawLineKernelPjiPji:
.LFB2051:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq DrawLineKernel(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z35__device_stub__Z14DrawLineKernelPjiPji, .-_Z35__device_stub__Z14DrawLineKernelPjiPji
.globl DrawLineKernel
.type DrawLineKernel, @function
DrawLineKernel:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z14DrawLineKernelPjiPji
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size DrawLineKernel, .-DrawLineKernel
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "DrawLineKernel"
.LC1:
.string "D_SIZE"
.LC2:
.string "D_K"
.LC3:
.string "D_Q"
.LC4:
.string "D_XSCALE"
.LC5:
.string "D_YSCALE"
.LC6:
.string "D_XMIN"
.LC7:
.string "D_YMIN"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq DrawLineKernel(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $4, %r9d
movl $0, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _ZL6D_SIZE(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $4, %r9d
movl $0, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _ZL3D_K(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $4, %r9d
movl $0, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _ZL3D_Q(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $4, %r9d
movl $0, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _ZL8D_XSCALE(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $4, %r9d
movl $0, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _ZL8D_YSCALE(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $4, %r9d
movl $0, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _ZL6D_XMIN(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $4, %r9d
movl $0, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _ZL6D_YMIN(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZL6D_YMIN
.comm _ZL6D_YMIN,4,4
.local _ZL6D_XMIN
.comm _ZL6D_XMIN,4,4
.local _ZL8D_YSCALE
.comm _ZL8D_YSCALE,4,4
.local _ZL8D_XSCALE
.comm _ZL8D_XSCALE,4,4
.local _ZL3D_Q
.comm _ZL3D_Q,4,4
.local _ZL3D_K
.comm _ZL3D_K,4,4
.local _ZL6D_SIZE
.comm _ZL6D_SIZE,4,4
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
```
|
```amdasm
.text
.file "DrawLineKernel.hip"
.globl __device_stub__DrawLineKernel # -- Begin function __device_stub__DrawLineKernel
.type __device_stub__DrawLineKernel,@function
__device_stub__DrawLineKernel: # @__device_stub__DrawLineKernel
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $80, %rsp
.cfi_def_cfa_offset 128
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 24(%rsp), %rax
movq %rdi, (%rax)
leaq 4(%rsp), %rcx
movl %esi, (%rcx)
leaq 64(%rsp), %rbx
movq %rax, (%rbx)
movq %rcx, 8(%rbx)
leaq 48(%rsp), %r14
leaq 32(%rsp), %r15
leaq 16(%rsp), %r12
leaq 8(%rsp), %r13
movq %r14, %rdi
movq %r15, %rsi
movq %r12, %rdx
movq %r13, %rcx
callq __hipPopCallConfiguration
movq (%r14), %rsi
movl 8(%r14), %edx
movq (%r15), %rcx
movl 8(%r15), %r8d
movl $DrawLineKernel, %edi
movq %rbx, %r9
pushq (%r13)
.cfi_adjust_cfa_offset 8
pushq (%r12)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $96, %rsp
.cfi_adjust_cfa_offset -96
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size __device_stub__DrawLineKernel, .Lfunc_end0-__device_stub__DrawLineKernel
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
movq __hip_gpubin_handle(%rip), %rbx
testq %rbx, %rbx
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, %rbx
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
subq $32, %rsp
.cfi_adjust_cfa_offset 32
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $DrawLineKernel, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
addq $32, %rsp
.cfi_adjust_cfa_offset -32
movl $D_SIZE, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movl $4, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
pushq $0
.cfi_adjust_cfa_offset 8
pushq $1
.cfi_adjust_cfa_offset 8
callq __hipRegisterVar
addq $16, %rsp
.cfi_adjust_cfa_offset -16
movl $D_K, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movl $4, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
pushq $0
.cfi_adjust_cfa_offset 8
pushq $1
.cfi_adjust_cfa_offset 8
callq __hipRegisterVar
addq $16, %rsp
.cfi_adjust_cfa_offset -16
movl $D_Q, %esi
movl $.L__unnamed_4, %edx
movl $.L__unnamed_4, %ecx
movl $4, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
pushq $0
.cfi_adjust_cfa_offset 8
pushq $1
.cfi_adjust_cfa_offset 8
callq __hipRegisterVar
addq $16, %rsp
.cfi_adjust_cfa_offset -16
movl $D_XSCALE, %esi
movl $.L__unnamed_5, %edx
movl $.L__unnamed_5, %ecx
movl $4, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
pushq $0
.cfi_adjust_cfa_offset 8
pushq $1
.cfi_adjust_cfa_offset 8
callq __hipRegisterVar
addq $16, %rsp
.cfi_adjust_cfa_offset -16
movl $D_YSCALE, %esi
movl $.L__unnamed_6, %edx
movl $.L__unnamed_6, %ecx
movl $4, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
pushq $0
.cfi_adjust_cfa_offset 8
pushq $1
.cfi_adjust_cfa_offset 8
callq __hipRegisterVar
addq $16, %rsp
.cfi_adjust_cfa_offset -16
movl $D_XMIN, %esi
movl $.L__unnamed_7, %edx
movl $.L__unnamed_7, %ecx
movl $4, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
pushq $0
.cfi_adjust_cfa_offset 8
pushq $1
.cfi_adjust_cfa_offset 8
callq __hipRegisterVar
addq $16, %rsp
.cfi_adjust_cfa_offset -16
movl $D_YMIN, %esi
movl $.L__unnamed_8, %edx
movl $.L__unnamed_8, %ecx
movl $4, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
pushq $0
.cfi_adjust_cfa_offset 8
pushq $1
.cfi_adjust_cfa_offset 8
callq __hipRegisterVar
addq $16, %rsp
.cfi_adjust_cfa_offset -16
movl $__hip_module_dtor, %edi
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type D_SIZE,@object # @D_SIZE
.local D_SIZE
.comm D_SIZE,4,4
.type D_K,@object # @D_K
.local D_K
.comm D_K,4,4
.type D_Q,@object # @D_Q
.local D_Q
.comm D_Q,4,4
.type D_XSCALE,@object # @D_XSCALE
.local D_XSCALE
.comm D_XSCALE,4,4
.type D_YSCALE,@object # @D_YSCALE
.local D_YSCALE
.comm D_YSCALE,4,4
.type D_XMIN,@object # @D_XMIN
.local D_XMIN
.comm D_XMIN,4,4
.type D_YMIN,@object # @D_YMIN
.local D_YMIN
.comm D_YMIN,4,4
.type DrawLineKernel,@object # @DrawLineKernel
.section .rodata,"a",@progbits
.globl DrawLineKernel
.p2align 3, 0x0
DrawLineKernel:
.quad __device_stub__DrawLineKernel
.size DrawLineKernel, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "DrawLineKernel"
.size .L__unnamed_1, 15
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "D_SIZE"
.size .L__unnamed_2, 7
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "D_K"
.size .L__unnamed_3, 4
.type .L__unnamed_4,@object # @3
.L__unnamed_4:
.asciz "D_Q"
.size .L__unnamed_4, 4
.type .L__unnamed_5,@object # @4
.L__unnamed_5:
.asciz "D_XSCALE"
.size .L__unnamed_5, 9
.type .L__unnamed_6,@object # @5
.L__unnamed_6:
.asciz "D_YSCALE"
.size .L__unnamed_6, 9
.type .L__unnamed_7,@object # @6
.L__unnamed_7:
.asciz "D_XMIN"
.size .L__unnamed_7, 7
.type .L__unnamed_8,@object # @7
.L__unnamed_8:
.asciz "D_YMIN"
.size .L__unnamed_8, 7
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __device_stub__DrawLineKernel
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym D_SIZE
.addrsig_sym D_K
.addrsig_sym D_Q
.addrsig_sym D_XSCALE
.addrsig_sym D_YSCALE
.addrsig_sym D_XMIN
.addrsig_sym D_YMIN
.addrsig_sym DrawLineKernel
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
```
| 2,964 | 3,445 |
362 |
Convert the following CUDA device assembly code to AMD device assembly:
```cudaasm
code for sm_80
Function : _Z15matrixMulKernelPfS_S_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
MOV R1, c[0x0][0x28] ;
S2R R3, SR_CTAID.Y ;
S2R R2, SR_TID.Y ;
S2R R0, SR_CTAID.X ;
S2R R5, SR_TID.X ;
IMAD R3, R3, c[0x0][0x4], R2 ;
ISETP.GE.AND P0, PT, R3, c[0x0][0x17c], PT ;
IMAD R0, R0, c[0x0][0x0], R5 ;
ISETP.GE.OR P0, PT, R0, c[0x0][0x178], P0 ;
@P0 EXIT ;
MOV R2, c[0x0][0x178] ;
ULDC.64 UR4, c[0x0][0x118] ;
HFMA2.MMA R28, -RZ, RZ, 0, 0 ;
IMAD R3, R3, c[0x0][0x178], RZ ;
ISETP.GE.AND P0, PT, R2, 0x1, PT ;
@!P0 BRA 0xc00 ;
IADD3 R4, R2.reuse, -0x1, RZ ;
LOP3.LUT R5, R2, 0x3, RZ, 0xc0, !PT ;
ISETP.GE.U32.AND P0, PT, R4, 0x3, PT ;
MOV R28, RZ ;
MOV R4, RZ ;
@!P0 BRA 0xb00 ;
IADD3 R6, -R5, c[0x0][0x178], RZ ;
HFMA2.MMA R25, -RZ, RZ, 0, 2.384185791015625e-07 ;
ULDC.64 UR6, c[0x0][0x168] ;
HFMA2.MMA R4, -RZ, RZ, 0, 0 ;
ISETP.GT.AND P0, PT, R6, RZ, PT ;
MOV R28, RZ ;
IMAD.WIDE R24, R0, R25, c[0x0][0x170] ;
@!P0 BRA 0x970 ;
ISETP.GT.AND P1, PT, R6, 0xc, PT ;
PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ;
@!P1 BRA 0x6b0 ;
PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ;
MOV R12, UR6 ;
LDG.E R29, [R24.64] ;
MOV R13, UR7 ;
IMAD.WIDE R12, R3, 0x4, R12 ;
LDG.E R27, [R12.64] ;
IMAD.WIDE R10, R2, 0x4, R24 ;
LDG.E R17, [R12.64+0x4] ;
IMAD.WIDE R18, R2.reuse, 0x4, R10 ;
LDG.E R16, [R10.64] ;
LDG.E R7, [R12.64+0xc] ;
IMAD.WIDE R14, R2, 0x4, R18 ;
LDG.E R18, [R18.64] ;
IMAD.WIDE R20, R2.reuse, 0x4, R14 ;
LDG.E R26, [R14.64] ;
LDG.E R9, [R12.64+0x10] ;
LDG.E R19, [R12.64+0x8] ;
IMAD.WIDE R14, R2, 0x4, R20 ;
LDG.E R20, [R20.64] ;
IMAD.WIDE R22, R2.reuse, 0x4, R14 ;
LDG.E R8, [R14.64] ;
LDG.E R11, [R12.64+0x14] ;
IMAD.WIDE R24, R2, 0x4, R22 ;
LDG.E R10, [R22.64] ;
LDG.E R21, [R12.64+0x18] ;
FFMA R29, R29, R27, R28 ;
LDG.E R27, [R12.64+0x1c] ;
LDG.E R28, [R24.64] ;
IMAD.WIDE R14, R2, 0x4, R24 ;
FFMA R29, R16, R17, R29 ;
IMAD.WIDE R16, R2, 0x4, R14 ;
LDG.E R14, [R14.64] ;
FFMA R29, R18, R19, R29 ;
IMAD.WIDE R18, R2, 0x4, R16 ;
LDG.E R16, [R16.64] ;
FFMA R26, R26, R7, R29 ;
IMAD.WIDE R22, R2.reuse, 0x4, R18 ;
LDG.E R7, [R12.64+0x20] ;
LDG.E R29, [R12.64+0x24] ;
IMAD.WIDE R24, R2, 0x4, R22 ;
LDG.E R18, [R18.64] ;
FFMA R9, R20, R9, R26 ;
LDG.E R26, [R12.64+0x28] ;
FFMA R11, R8, R11, R9 ;
IMAD.WIDE R8, R2, 0x4, R24 ;
LDG.E R22, [R22.64] ;
LDG.E R17, [R12.64+0x2c] ;
FFMA R21, R10, R21, R11 ;
LDG.E R15, [R24.64] ;
IMAD.WIDE R10, R2, 0x4, R8 ;
LDG.E R19, [R8.64] ;
LDG.E R23, [R10.64] ;
LDG.E R24, [R12.64+0x30] ;
LDG.E R25, [R12.64+0x38] ;
LDG.E R8, [R12.64+0x3c] ;
FFMA R9, R28, R27, R21 ;
LDG.E R28, [R12.64+0x34] ;
IMAD.WIDE R20, R2, 0x4, R10 ;
LDG.E R27, [R20.64] ;
IADD3 R6, R6, -0x10, RZ ;
ISETP.GT.AND P1, PT, R6, 0xc, PT ;
FFMA R7, R14, R7, R9 ;
FFMA R7, R16, R29, R7 ;
FFMA R7, R18, R26, R7 ;
FFMA R7, R22, R17, R7 ;
UIADD3 UR6, UP0, UR6, 0x40, URZ ;
IADD3 R4, R4, 0x10, RZ ;
UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ;
FFMA R7, R15, R24, R7 ;
FFMA R28, R19, R28, R7 ;
FFMA R28, R23, R25, R28 ;
IMAD.WIDE R24, R2, 0x4, R20 ;
FFMA R28, R27, R8, R28 ;
@P1 BRA 0x220 ;
ISETP.GT.AND P1, PT, R6, 0x4, PT ;
@!P1 BRA 0x950 ;
IMAD.WIDE R16, R2, 0x4, R24 ;
MOV R8, UR6 ;
LDG.E R7, [R24.64] ;
MOV R9, UR7 ;
IMAD.WIDE R12, R2.reuse, 0x4, R16 ;
LDG.E R21, [R16.64] ;
IMAD.WIDE R8, R3, 0x4, R8 ;
LDG.E R23, [R12.64] ;
IMAD.WIDE R14, R2.reuse, 0x4, R12 ;
LDG.E R20, [R8.64] ;
LDG.E R22, [R8.64+0x4] ;
IMAD.WIDE R10, R2, 0x4, R14 ;
LDG.E R26, [R8.64+0x8] ;
IMAD.WIDE R16, R2.reuse, 0x4, R10 ;
LDG.E R14, [R14.64] ;
LDG.E R27, [R8.64+0xc] ;
IMAD.WIDE R18, R2, 0x4, R16 ;
LDG.E R10, [R10.64] ;
LDG.E R25, [R8.64+0x10] ;
IMAD.WIDE R12, R2, 0x4, R18 ;
LDG.E R16, [R16.64] ;
LDG.E R29, [R8.64+0x14] ;
LDG.E R24, [R18.64] ;
LDG.E R11, [R8.64+0x18] ;
LDG.E R15, [R12.64] ;
LDG.E R18, [R8.64+0x1c] ;
UIADD3 UR6, UP0, UR6, 0x20, URZ ;
PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ;
IADD3 R4, R4, 0x8, RZ ;
IADD3 R6, R6, -0x8, RZ ;
UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ;
FFMA R7, R7, R20, R28 ;
FFMA R7, R21, R22, R7 ;
FFMA R7, R23, R26, R7 ;
FFMA R7, R14, R27, R7 ;
FFMA R7, R10, R25, R7 ;
FFMA R7, R16, R29, R7 ;
FFMA R7, R24, R11, R7 ;
IMAD.WIDE R24, R2, 0x4, R12 ;
FFMA R28, R15, R18, R7 ;
ISETP.NE.OR P0, PT, R6, RZ, P0 ;
@!P0 BRA 0xb00 ;
MOV R8, UR6 ;
IMAD.WIDE R14, R2, 0x4, R24 ;
MOV R9, UR7 ;
LDG.E R25, [R24.64] ;
IMAD.WIDE R8, R3, 0x4, R8 ;
IMAD.WIDE R12, R2.reuse, 0x4, R14 ;
LDG.E R7, [R8.64] ;
LDG.E R14, [R14.64] ;
IMAD.WIDE R10, R2, 0x4, R12 ;
LDG.E R16, [R8.64+0x4] ;
LDG.E R18, [R12.64] ;
LDG.E R17, [R8.64+0x8] ;
LDG.E R19, [R8.64+0xc] ;
LDG.E R20, [R10.64] ;
IADD3 R6, R6, -0x4, RZ ;
ISETP.NE.AND P0, PT, R6, RZ, PT ;
UIADD3 UR6, UP0, UR6, 0x10, URZ ;
IADD3 R4, R4, 0x4, RZ ;
UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ;
FFMA R7, R25, R7, R28 ;
FFMA R7, R14, R16, R7 ;
IMAD.WIDE R24, R2, 0x4, R10 ;
FFMA R7, R18, R17, R7 ;
FFMA R28, R20, R19, R7 ;
@P0 BRA 0x970 ;
ISETP.NE.AND P0, PT, R5, RZ, PT ;
@!P0 BRA 0xc00 ;
HFMA2.MMA R9, -RZ, RZ, 0, 2.384185791015625e-07 ;
IADD3 R6, R3, R4, RZ ;
IMAD R4, R4, c[0x0][0x178], R0 ;
IMAD.WIDE R6, R6, R9, c[0x0][0x168] ;
IMAD.WIDE R8, R4, R9, c[0x0][0x170] ;
LDG.E R11, [R8.64] ;
LDG.E R4, [R6.64] ;
IADD3 R5, R5, -0x1, RZ ;
ISETP.NE.AND P0, PT, R5, RZ, PT ;
IMAD.WIDE R8, R2, 0x4, R8 ;
IADD3 R6, P1, R6, 0x4, RZ ;
IADD3.X R7, RZ, R7, RZ, P1, !PT ;
FFMA R28, R11, R4, R28 ;
@P0 BRA 0xb70 ;
IADD3 R3, R0, R3, RZ ;
MOV R2, 0x4 ;
IMAD.WIDE R2, R3, R2, c[0x0][0x160] ;
STG.E [R2.64], R28 ;
EXIT ;
BRA 0xc50;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
```
|
```amdasm
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z15matrixMulKernelPfS_S_ii ; -- Begin function _Z15matrixMulKernelPfS_S_ii
.globl _Z15matrixMulKernelPfS_S_ii
.p2align 8
.type _Z15matrixMulKernelPfS_S_ii,@function
_Z15matrixMulKernelPfS_S_ii: ; @_Z15matrixMulKernelPfS_S_ii
; %bb.0:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b64 s[8:9], s[0:1], 0x18
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_lshr_b32 s3, s2, 16
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[0:1], null, s14, s2, v[2:3]
v_mad_u64_u32 v[1:2], null, s15, s3, v[3:4]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_gt_i32_e32 vcc_lo, s8, v0
v_cmp_gt_i32_e64 s2, s9, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, vcc_lo, s2
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_6
; %bb.1: ; %.preheader
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
v_mul_lo_u32 v1, v1, s8
s_cmp_lt_i32 s8, 1
s_cbranch_scc1 .LBB0_4
; %bb.2: ; %.lr.ph.preheader
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
v_ashrrev_i32_e32 v2, 31, v1
v_mov_b32_e32 v6, 0
v_mov_b32_e32 v4, v0
s_mov_b32 s2, s8
v_lshlrev_b64 v[2:3], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s6, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v3, vcc_lo
.LBB0_3: ; %.lr.ph
; =>This Inner Loop Header: Depth=1
v_ashrrev_i32_e32 v5, 31, v4
s_add_i32 s2, s2, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_cmp_eq_u32 s2, 0
v_lshlrev_b64 v[7:8], 2, v[4:5]
v_add_nc_u32_e32 v4, s8, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v7, vcc_lo, s0, v7
v_add_co_ci_u32_e32 v8, vcc_lo, s1, v8, vcc_lo
global_load_b32 v5, v[2:3], off
global_load_b32 v7, v[7:8], off
v_add_co_u32 v2, vcc_lo, v2, 4
v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v6, v5, v7
s_cbranch_scc0 .LBB0_3
s_branch .LBB0_5
.LBB0_4:
v_mov_b32_e32 v6, 0
.LBB0_5: ; %Flow51
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v0, v1, v0
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
global_store_b32 v[0:1], v6, off
.LBB0_6:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z15matrixMulKernelPfS_S_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z15matrixMulKernelPfS_S_ii, .Lfunc_end0-_Z15matrixMulKernelPfS_S_ii
; -- End function
.section .AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 344
; NumSgprs: 18
; NumVgprs: 9
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 9
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object ; @__hip_cuid_
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0 ; 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z15matrixMulKernelPfS_S_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z15matrixMulKernelPfS_S_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
```
| 3,633 | 3,381 |
363 |
Convert the following CUDA host assembly code to AMD host assembly:
```cudaasm
.file "tmpxft_0019650f_00000000-6_testmul.cudafe1.cpp"
.text
.globl _ZSt21ios_base_library_initv
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3674:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3674:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z12constantInitPfif
.type _Z12constantInitPfif, @function
_Z12constantInitPfif:
.LFB3669:
.cfi_startproc
endbr64
testl %esi, %esi
jle .L8
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
movq %rdi, %rbx
movslq %esi, %rsi
leaq (%rdi,%rsi,4), %rbp
.L5:
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2sdl %eax, %xmm0
divsd .LC0(%rip), %xmm0
cvtsd2ss %xmm0, %xmm0
movss %xmm0, (%rbx)
addq $4, %rbx
cmpq %rbp, %rbx
jne .L5
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L8:
.cfi_restore 3
.cfi_restore 6
ret
.cfi_endproc
.LFE3669:
.size _Z12constantInitPfif, .-_Z12constantInitPfif
.globl _Z41__device_stub__Z15matrixMulKernelPfS_S_iiPfS_S_ii
.type _Z41__device_stub__Z15matrixMulKernelPfS_S_iiPfS_S_ii, @function
_Z41__device_stub__Z15matrixMulKernelPfS_S_iiPfS_S_ii:
.LFB3696:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z15matrixMulKernelPfS_S_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3696:
.size _Z41__device_stub__Z15matrixMulKernelPfS_S_iiPfS_S_ii, .-_Z41__device_stub__Z15matrixMulKernelPfS_S_iiPfS_S_ii
.globl _Z15matrixMulKernelPfS_S_ii
.type _Z15matrixMulKernelPfS_S_ii, @function
_Z15matrixMulKernelPfS_S_ii:
.LFB3697:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z41__device_stub__Z15matrixMulKernelPfS_S_iiPfS_S_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _Z15matrixMulKernelPfS_S_ii, .-_Z15matrixMulKernelPfS_S_ii
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "Result = PASS"
.LC2:
.string "Result = FAIL"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC5:
.string "Checking computed result for correctness: \n"
.section .rodata.str1.1
.LC6:
.string "%f "
.LC7:
.string "\n"
.section .rodata.str1.8
.align 8
.LC13:
.string "Error! Matrix[%05d]=%.8f, ref=%.8f error term is > %E\n"
.section .rodata.str1.1
.LC14:
.string "%s\n"
.text
.globl _Z9matrixMulv
.type _Z9matrixMulv, @function
_Z9matrixMulv:
.LFB3670:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $72, %rsp
.cfi_def_cfa_offset 128
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl $16, %edi
call malloc@PLT
movq %rax, %r13
movl $16, %edi
call malloc@PLT
movq %rax, %r12
movl $16, %edi
call malloc@PLT
movq %rax, %rbp
movss .LC3(%rip), %xmm0
movl $4, %esi
movq %r13, %rdi
call _Z12constantInitPfif
movss .LC4(%rip), %xmm0
movl $4, %esi
movq %r12, %rdi
call _Z12constantInitPfif
leaq 8(%rsp), %rdi
movl $16, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $16, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $16, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $16, %edx
movq %r13, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $16, %edx
movq %r12, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $16, 32(%rsp)
movl $16, 36(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 32(%rsp), %rdx
movl $1, %ecx
movq 44(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L36
.L20:
movl $2, %ecx
movl $16, %edx
movq 24(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %r13, %rbx
leaq 16(%r13), %r15
leaq .LC6(%rip), %r14
.L21:
pxor %xmm0, %xmm0
cvtss2sd (%rbx), %xmm0
movq %r14, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %r15, %rbx
jne .L21
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %r12, %rbx
leaq 16(%r12), %r15
leaq .LC6(%rip), %r14
.L22:
pxor %xmm0, %xmm0
cvtss2sd (%rbx), %xmm0
movq %r14, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %r15, %rbx
jne .L22
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %rbp, %rbx
leaq 16(%rbp), %r15
leaq .LC6(%rip), %r14
.L23:
pxor %xmm0, %xmm0
cvtss2sd (%rbx), %xmm0
movq %r14, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %rbx, %r15
jne .L23
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %ebx
movl $1, %eax
jmp .L26
.L36:
movl $2, %r8d
movl $2, %ecx
movq 16(%rsp), %rdx
movq 8(%rsp), %rsi
movq 24(%rsp), %rdi
call _Z41__device_stub__Z15matrixMulKernelPfS_S_iiPfS_S_ii
jmp .L20
.L24:
addq $1, %rbx
cmpq $4, %rbx
je .L37
.L26:
movss 0(%rbp,%rbx,4), %xmm0
movaps %xmm0, %xmm1
subss .LC8(%rip), %xmm1
andps .LC9(%rip), %xmm1
cvtss2sd %xmm1, %xmm1
movaps %xmm0, %xmm2
andps .LC9(%rip), %xmm2
cvtss2sd %xmm2, %xmm2
divsd %xmm2, %xmm1
mulsd .LC10(%rip), %xmm1
comisd .LC11(%rip), %xmm1
jbe .L24
cvtss2sd %xmm0, %xmm0
movsd .LC11(%rip), %xmm2
movsd .LC12(%rip), %xmm1
movl %ebx, %edx
leaq .LC13(%rip), %rsi
movl $2, %edi
movl $3, %eax
call __printf_chk@PLT
movl $0, %eax
jmp .L24
.L37:
testb %al, %al
leaq .LC2(%rip), %rdx
leaq .LC1(%rip), %rax
cmovne %rax, %rdx
leaq .LC14(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %r13, %rdi
call free@PLT
movq %r12, %rdi
call free@PLT
movq %rbp, %rdi
call free@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L38
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L38:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3670:
.size _Z9matrixMulv, .-_Z9matrixMulv
.globl main
.type main, @function
main:
.LFB3671:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z9matrixMulv
movl $0, %eax
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3671:
.size main, .-main
.section .rodata.str1.1
.LC15:
.string "_Z15matrixMulKernelPfS_S_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3699:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC15(%rip), %rdx
movq %rdx, %rcx
leaq _Z15matrixMulKernelPfS_S_ii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3699:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC0:
.long -4194304
.long 1105199103
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC3:
.long 1065353216
.align 4
.LC4:
.long 1008981770
.align 4
.LC8:
.long 1017370378
.section .rodata.cst16,"aM",@progbits,16
.align 16
.LC9:
.long 2147483647
.long 0
.long 0
.long 0
.section .rodata.cst8
.align 8
.LC10:
.long 0
.long 1071644672
.align 8
.LC11:
.long -1598689907
.long 1051772663
.align 8
.LC12:
.long 0
.long 1074790400
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
```
|
```amdasm
.text
.file "testmul.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z30__device_stub__matrixMulKernelPfS_S_ii # -- Begin function _Z30__device_stub__matrixMulKernelPfS_S_ii
.type _Z30__device_stub__matrixMulKernelPfS_S_ii,@function
_Z30__device_stub__matrixMulKernelPfS_S_ii: # @_Z30__device_stub__matrixMulKernelPfS_S_ii
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $128, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 40(%rsp), %rax
movq %rdi, (%rax)
leaq 32(%rsp), %rdi
movq %rsi, (%rdi)
leaq 24(%rsp), %rsi
movq %rdx, (%rsi)
leaq 4(%rsp), %rdx
movl %ecx, (%rdx)
movq %rsp, %rcx
movl %r8d, (%rcx)
leaq 80(%rsp), %rbx
movq %rax, (%rbx)
movq %rdi, 8(%rbx)
movq %rsi, 16(%rbx)
movq %rdx, 24(%rbx)
movq %rcx, 32(%rbx)
leaq 64(%rsp), %r14
leaq 48(%rsp), %r15
leaq 16(%rsp), %r12
leaq 8(%rsp), %r13
movq %r14, %rdi
movq %r15, %rsi
movq %r12, %rdx
movq %r13, %rcx
callq __hipPopCallConfiguration
movq (%r14), %rsi
movl 8(%r14), %edx
movq (%r15), %rcx
movl 8(%r15), %r8d
movl $_Z15matrixMulKernelPfS_S_ii, %edi
movq %rbx, %r9
pushq (%r13)
.cfi_adjust_cfa_offset 8
pushq (%r12)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $144, %rsp
.cfi_adjust_cfa_offset -144
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z30__device_stub__matrixMulKernelPfS_S_ii, .Lfunc_end0-_Z30__device_stub__matrixMulKernelPfS_S_ii
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z12constantInitPfif
.LCPI1_0:
.quad 0x41dfffffffc00000 # double 2147483647
.text
.globl _Z12constantInitPfif
.type _Z12constantInitPfif,@function
_Z12constantInitPfif: # @_Z12constantInitPfif
.cfi_startproc
# %bb.0:
testl %esi, %esi
jle .LBB1_4
# %bb.1: # %.lr.ph.preheader
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rdi, %rbx
movl %esi, %r14d
xorl %r15d, %r15d
.LBB1_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
callq rand
xorps %xmm0, %xmm0
cvtsi2sd %eax, %xmm0
divsd .LCPI1_0(%rip), %xmm0
cvtsd2ss %xmm0, %xmm0
movss %xmm0, (%rbx,%r15,4)
incq %r15
cmpq %r15, %r14
jne .LBB1_2
# %bb.3:
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r14
.cfi_restore %r15
.LBB1_4: # %._crit_edge
retq
.Lfunc_end1:
.size _Z12constantInitPfif, .Lfunc_end1-_Z12constantInitPfif
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z9matrixMulv
.LCPI2_0:
.quad 0x41dfffffffc00000 # double 2147483647
.LCPI2_4:
.quad 0x3fe0000000000000 # double 0.5
.LCPI2_5:
.quad 0x3eb0c6f7a0b5ed8d # double 9.9999999999999995E-7
.LCPI2_6:
.quad 0x4010000000000000 # double 4
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0
.LCPI2_1:
.long 0xbca3d70a # float -0.0199999996
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0
.LCPI2_2:
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.LCPI2_3:
.quad 0x7fffffffffffffff # double NaN
.quad 0x7fffffffffffffff # double NaN
.text
.globl _Z9matrixMulv
.type _Z9matrixMulv,@function
_Z9matrixMulv: # @_Z9matrixMulv
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $32, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $16, %edi
callq malloc
movq %rax, %rbx
movl $16, %edi
callq malloc
movq %rax, %r14
movl $16, %edi
callq malloc
movq %rax, %r15
xorl %r12d, %r12d
.LBB2_1: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
callq rand
movsd .LCPI2_0(%rip), %xmm1 # xmm1 = mem[0],zero
xorps %xmm0, %xmm0
cvtsi2sd %eax, %xmm0
divsd %xmm1, %xmm0
cvtsd2ss %xmm0, %xmm0
movss %xmm0, (%rbx,%r12,4)
incq %r12
cmpq $4, %r12
jne .LBB2_1
# %bb.2: # %.lr.ph.i78.preheader
xorl %r12d, %r12d
.LBB2_3: # %.lr.ph.i78
# =>This Inner Loop Header: Depth=1
callq rand
xorps %xmm0, %xmm0
cvtsi2sd %eax, %xmm0
divsd .LCPI2_0(%rip), %xmm0
cvtsd2ss %xmm0, %xmm0
movss %xmm0, (%r14,%r12,4)
incq %r12
cmpq $4, %r12
jne .LBB2_3
# %bb.4: # %_Z12constantInitPfif.exit82
leaq 24(%rsp), %r12
movl $16, %esi
movq %r12, %rdi
callq hipMalloc
leaq 16(%rsp), %r13
movl $16, %esi
movq %r13, %rdi
callq hipMalloc
leaq 8(%rsp), %rdi
movl $16, %esi
callq hipMalloc
movq (%r12), %rdi
movl $16, %edx
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq (%r13), %rdi
movl $16, %edx
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $4294967297, %rdi # imm = 0x100000001
movabsq $68719476752, %rdx # imm = 0x1000000010
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_6
# %bb.5:
movq 8(%rsp), %rdi
movq 24(%rsp), %rsi
movq 16(%rsp), %rdx
movl $2, %ecx
movl $2, %r8d
callq _Z30__device_stub__matrixMulKernelPfS_S_ii
.LBB2_6:
movq 8(%rsp), %rsi
movl $16, %edx
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
movl $.Lstr, %edi
callq puts@PLT
xorl %r12d, %r12d
.LBB2_7: # =>This Inner Loop Header: Depth=1
xorps %xmm0, %xmm0
cvtss2sd (%rbx,%r12,4), %xmm0
movl $.L.str.1, %edi
movb $1, %al
callq printf
incq %r12
cmpq $4, %r12
jne .LBB2_7
# %bb.8:
movl $10, %edi
callq putchar@PLT
xorl %r12d, %r12d
.LBB2_9: # =>This Inner Loop Header: Depth=1
xorps %xmm0, %xmm0
cvtss2sd (%r14,%r12,4), %xmm0
movl $.L.str.1, %edi
movb $1, %al
callq printf
incq %r12
cmpq $4, %r12
jne .LBB2_9
# %bb.10:
movl $10, %edi
callq putchar@PLT
xorl %r12d, %r12d
.LBB2_11: # =>This Inner Loop Header: Depth=1
xorps %xmm0, %xmm0
cvtss2sd (%r15,%r12,4), %xmm0
movl $.L.str.1, %edi
movb $1, %al
callq printf
incq %r12
cmpq $4, %r12
jne .LBB2_11
# %bb.12:
movl $10, %edi
callq putchar@PLT
movb $1, %al
xorl %r12d, %r12d
movss .LCPI2_1(%rip), %xmm3 # xmm3 = mem[0],zero,zero,zero
movaps .LCPI2_2(%rip), %xmm4 # xmm4 = [NaN,NaN,NaN,NaN]
movaps .LCPI2_3(%rip), %xmm5 # xmm5 = [NaN,NaN]
movsd .LCPI2_4(%rip), %xmm6 # xmm6 = mem[0],zero
movsd .LCPI2_5(%rip), %xmm2 # xmm2 = mem[0],zero
.LBB2_13: # =>This Inner Loop Header: Depth=1
movss (%r15,%r12,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
xorps %xmm0, %xmm0
cvtss2sd %xmm1, %xmm0
addss %xmm3, %xmm1
andps %xmm4, %xmm1
cvtss2sd %xmm1, %xmm1
movaps %xmm0, %xmm7
andps %xmm5, %xmm7
divsd %xmm7, %xmm1
mulsd %xmm6, %xmm1
ucomisd %xmm2, %xmm1
jbe .LBB2_15
# %bb.14: # in Loop: Header=BB2_13 Depth=1
movl $.L.str.3, %edi
movl %r12d, %esi
movsd .LCPI2_6(%rip), %xmm1 # xmm1 = mem[0],zero
movb $3, %al
callq printf
movsd .LCPI2_5(%rip), %xmm2 # xmm2 = mem[0],zero
movsd .LCPI2_4(%rip), %xmm6 # xmm6 = mem[0],zero
movaps .LCPI2_3(%rip), %xmm5 # xmm5 = [NaN,NaN]
movaps .LCPI2_2(%rip), %xmm4 # xmm4 = [NaN,NaN,NaN,NaN]
movss .LCPI2_1(%rip), %xmm3 # xmm3 = mem[0],zero,zero,zero
xorl %eax, %eax
.LBB2_15: # in Loop: Header=BB2_13 Depth=1
incq %r12
cmpq $4, %r12
jne .LBB2_13
# %bb.16:
testb $1, %al
movl $.L.str.6, %eax
movl $.L.str.5, %edi
cmoveq %rax, %rdi
callq puts@PLT
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
addq $32, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size _Z9matrixMulv, .Lfunc_end2-_Z9matrixMulv
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
callq _Z9matrixMulv
xorl %eax, %eax
popq %rcx
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, %rdi
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15matrixMulKernelPfS_S_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z15matrixMulKernelPfS_S_ii,@object # @_Z15matrixMulKernelPfS_S_ii
.section .rodata,"a",@progbits
.globl _Z15matrixMulKernelPfS_S_ii
.p2align 3, 0x0
_Z15matrixMulKernelPfS_S_ii:
.quad _Z30__device_stub__matrixMulKernelPfS_S_ii
.size _Z15matrixMulKernelPfS_S_ii, 8
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "%f "
.size .L.str.1, 4
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Error! Matrix[%05d]=%.8f, ref=%.8f error term is > %E\n"
.size .L.str.3, 55
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "Result = PASS"
.size .L.str.5, 14
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "Result = FAIL"
.size .L.str.6, 14
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z15matrixMulKernelPfS_S_ii"
.size .L__unnamed_1, 28
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Checking computed result for correctness: "
.size .Lstr, 43
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z30__device_stub__matrixMulKernelPfS_S_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z15matrixMulKernelPfS_S_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
```
| 5,259 | 6,092 |
368 |
Convert the following CUDA device assembly code to AMD device assembly:
```cudaasm
code for sm_80
Function : _Z6vevAddiPfS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
MOV R1, c[0x0][0x28] ;
S2R R6, SR_CTAID.X ;
S2R R3, SR_TID.X ;
IMAD R6, R6, c[0x0][0x0], R3 ;
ISETP.GE.AND P0, PT, R6, c[0x0][0x160], PT ;
@P0 EXIT ;
HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ;
ULDC.64 UR4, c[0x0][0x118] ;
IMAD.WIDE R4, R6, R7, c[0x0][0x170] ;
IMAD.WIDE R2, R6.reuse, R7.reuse, c[0x0][0x168] ;
LDG.E R4, [R4.64] ;
LDG.E R3, [R2.64] ;
IMAD.WIDE R6, R6, R7, c[0x0][0x178] ;
FADD R9, R4, R3 ;
STG.E [R6.64], R9 ;
EXIT ;
BRA 0x100;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
```
|
```amdasm
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6vevAddiPfS_S_ ; -- Begin function _Z6vevAddiPfS_S_
.globl _Z6vevAddiPfS_S_
.p2align 8
.type _Z6vevAddiPfS_S_,@function
_Z6vevAddiPfS_S_: ; @_Z6vevAddiPfS_S_
; %bb.0:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
; %bb.1:
s_load_b128 s[4:7], s[0:1], 0x8
v_ashrrev_i32_e32 v2, 31, v1
s_load_b64 s[0:1], s[0:1], 0x18
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_f32_e32 v2, v2, v3
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6vevAddiPfS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6vevAddiPfS_S_, .Lfunc_end0-_Z6vevAddiPfS_S_
; -- End function
.section .AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 180
; NumSgprs: 18
; NumVgprs: 6
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 6
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object ; @__hip_cuid_
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0 ; 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6vevAddiPfS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z6vevAddiPfS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
```
| 402 | 2,592 |
369 |
Convert the following CUDA host assembly code to AMD host assembly:
```cudaasm
.file "tmpxft_0014c264_00000000-6_vevAdd.cudafe1.cpp"
.text
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z30__device_stub__Z6vevAddiPfS_S_iPfS_S_
.type _Z30__device_stub__Z6vevAddiPfS_S_iPfS_S_, @function
_Z30__device_stub__Z6vevAddiPfS_S_iPfS_S_:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 28(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %rcx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z6vevAddiPfS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z30__device_stub__Z6vevAddiPfS_S_iPfS_S_, .-_Z30__device_stub__Z6vevAddiPfS_S_iPfS_S_
.globl _Z6vevAddiPfS_S_
.type _Z6vevAddiPfS_S_, @function
_Z6vevAddiPfS_S_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z6vevAddiPfS_S_iPfS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z6vevAddiPfS_S_, .-_Z6vevAddiPfS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z6vevAddiPfS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z6vevAddiPfS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
```
|
```amdasm
.text
.file "vevAdd.hip"
.globl _Z21__device_stub__vevAddiPfS_S_ # -- Begin function _Z21__device_stub__vevAddiPfS_S_
.type _Z21__device_stub__vevAddiPfS_S_,@function
_Z21__device_stub__vevAddiPfS_S_: # @_Z21__device_stub__vevAddiPfS_S_
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $112, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 4(%rsp), %rax
movl %edi, (%rax)
leaq 40(%rsp), %rdi
movq %rsi, (%rdi)
leaq 32(%rsp), %rsi
movq %rdx, (%rsi)
leaq 24(%rsp), %rdx
movq %rcx, (%rdx)
leaq 80(%rsp), %rbx
movq %rax, (%rbx)
movq %rdi, 8(%rbx)
movq %rsi, 16(%rbx)
movq %rdx, 24(%rbx)
leaq 64(%rsp), %r14
leaq 48(%rsp), %r15
leaq 16(%rsp), %r12
leaq 8(%rsp), %r13
movq %r14, %rdi
movq %r15, %rsi
movq %r12, %rdx
movq %r13, %rcx
callq __hipPopCallConfiguration
movq (%r14), %rsi
movl 8(%r14), %edx
movq (%r15), %rcx
movl 8(%r15), %r8d
movl $_Z6vevAddiPfS_S_, %edi
movq %rbx, %r9
pushq (%r13)
.cfi_adjust_cfa_offset 8
pushq (%r12)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $128, %rsp
.cfi_adjust_cfa_offset -128
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z21__device_stub__vevAddiPfS_S_, .Lfunc_end0-_Z21__device_stub__vevAddiPfS_S_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, %rdi
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6vevAddiPfS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6vevAddiPfS_S_,@object # @_Z6vevAddiPfS_S_
.section .rodata,"a",@progbits
.globl _Z6vevAddiPfS_S_
.p2align 3, 0x0
_Z6vevAddiPfS_S_:
.quad _Z21__device_stub__vevAddiPfS_S_
.size _Z6vevAddiPfS_S_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z6vevAddiPfS_S_"
.size .L__unnamed_1, 17
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__vevAddiPfS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6vevAddiPfS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
```
| 1,906 | 2,098 |
370 |
Convert the following CUDA device assembly code to AMD device assembly:
```cudaasm
code for sm_80
Function : _Z13meanFilterGPUPhS_iisi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ;
S2R R0, SR_CTAID.Y ;
S2R R3, SR_TID.Y ;
S2R R5, SR_CTAID.X ;
S2R R2, SR_TID.X ;
IMAD R0, R0, c[0x0][0x4], R3 ;
ISETP.GE.AND P0, PT, R0, c[0x0][0x174], PT ;
IMAD R5, R5, c[0x0][0x0], R2 ;
ISETP.GE.OR P0, PT, R5, c[0x0][0x170], P0 ;
@P0 EXIT ;
ULDC UR4, c[0x0][0x17c] ;
IMAD.MOV.U32 R2, RZ, RZ, 0x1 ;
ULEA.HI UR4, UR4, UR4, URZ, 0x1 ;
BSSY B0, 0xad0 ;
IMAD.MOV.U32 R13, RZ, RZ, RZ ;
USHF.R.S32.HI UR4, URZ, 0x1, UR4 ;
IADD3 R4, R0.reuse, UR4, RZ ;
IADD3 R7, R0, -UR4, RZ ;
ISETP.GE.AND P0, PT, R4, c[0x0][0x174], PT ;
IMNMX R7, RZ, R7, !PT ;
IADD3 R6, R5.reuse, UR4, RZ ;
IADD3 R9, R5, -UR4, RZ ;
ULDC.64 UR4, c[0x0][0x118] ;
ISETP.GE.AND P1, PT, R6, c[0x0][0x170], PT ;
IMNMX R9, RZ, R9, !PT ;
@P0 IADD3 R4, -R2, c[0x0][0x174], RZ ;
ISETP.GT.AND P0, PT, R7, R4, PT ;
@P1 IADD3 R6, -R2, c[0x0][0x170], RZ ;
@P0 BRA 0xac0 ;
LDC.U16 R2, c[0x0][0x178] ;
PRMT R2, R2, 0x9910, RZ ;
ISETP.NE.AND P0, PT, R2, 0x8, PT ;
@!P0 BRA 0x3d0 ;
IMAD.MOV.U32 R13, RZ, RZ, RZ ;
IMAD.MOV.U32 R11, RZ, RZ, R7 ;
LDC.U16 R2, c[0x0][0x178] ;
BSSY B1, 0x3a0 ;
ISETP.GE.AND P1, PT, R11.reuse, R4, PT ;
IADD3 R14, R11, 0x1, RZ ;
PRMT R2, R2, 0x9910, RZ ;
ISETP.NE.AND P0, PT, R2, 0x18, PT ;
ISETP.LT.OR P0, PT, R6, R9, P0 ;
@P0 BRA 0x390 ;
IMAD.MOV.U32 R8, RZ, RZ, R9 ;
IMAD R2, R11, c[0x0][0x170], R8 ;
IMAD R3, R2, 0x3, RZ ;
IADD3 R2, P0, R3, c[0x0][0x160], RZ ;
LEA.HI.X.SX32 R3, R3, c[0x0][0x164], 0x1, P0 ;
LDG.E.U8 R10, [R2.64] ;
LDG.E.U8 R15, [R2.64+0x1] ;
LDG.E.U8 R12, [R2.64+0x2] ;
ISETP.GE.AND P0, PT, R8.reuse, R6, PT ;
IADD3 R8, R8, 0x1, RZ ;
IMAD R15, R10, 0x100, R15 ;
IMAD.U32 R12, R15, 0x100, R12 ;
IMAD.IADD R13, R12, 0x1, R13 ;
@!P0 BRA 0x2c0 ;
BSYNC B1 ;
IMAD.MOV.U32 R11, RZ, RZ, R14 ;
@!P1 BRA 0x230 ;
BRA 0xac0 ;
IMAD.IADD R2, R6, 0x1, -R9 ;
IADD3 R12, -R9.reuse, 0x1, R6 ;
IMAD.MOV.U32 R13, RZ, RZ, RZ ;
IADD3 R8, R9.reuse, 0x1, RZ ;
IMAD.MOV.U32 R11, RZ, RZ, R7 ;
ISETP.GE.U32.AND P1, PT, R2, 0x3, PT ;
IADD3 R10, R9, 0x2, RZ ;
IADD3 R24, R9, 0x3, RZ ;
LOP3.LUT R12, R12, 0x3, RZ, 0xc0, !PT ;
ISETP.GE.AND P0, PT, R6, R9, PT ;
BSSY B1, 0xa90 ;
@!P0 BRA 0xa80 ;
ISETP.NE.AND P0, PT, R12, RZ, PT ;
BSSY B2, 0x5d0 ;
IMAD.MOV.U32 R14, RZ, RZ, R9 ;
@!P0 BRA 0x5c0 ;
IMAD R3, R11, c[0x0][0x170], R9 ;
IADD3 R2, P0, R3, c[0x0][0x160], RZ ;
LEA.HI.X.SX32 R3, R3, c[0x0][0x164], 0x1, P0 ;
LDG.E.U8 R16, [R2.64] ;
ISETP.NE.AND P0, PT, R12, 0x1, PT ;
IMAD.MOV.U32 R14, RZ, RZ, R8 ;
IMAD.IADD R13, R13, 0x1, R16 ;
@!P0 BRA 0x5c0 ;
ISETP.NE.AND P0, PT, R12, 0x2, PT ;
LDG.E.U8 R16, [R2.64+0x1] ;
@P0 LDG.E.U8 R18, [R2.64+0x2] ;
IMAD.MOV.U32 R14, RZ, RZ, R10 ;
@P0 IMAD.MOV.U32 R14, RZ, RZ, R24 ;
IMAD.IADD R13, R13, 0x1, R16 ;
@P0 IMAD.IADD R13, R13, 0x1, R18 ;
BSYNC B2 ;
@!P1 BRA 0xa80 ;
IADD3 R15, R14, -0x1, RZ ;
IMAD R3, R11, c[0x0][0x170], R14 ;
BSSY B2, 0x890 ;
IMAD.IADD R14, R6, 0x1, -R15 ;
IADD3 R2, P0, R3, c[0x0][0x160], RZ ;
ISETP.GT.AND P2, PT, R14, 0xc, PT ;
LEA.HI.X.SX32 R3, R3, c[0x0][0x164], 0x1, P0 ;
PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ;
@!P2 BRA 0x880 ;
PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ;
IADD3 R14, R6, -0xc, RZ ;
LDG.E.U8 R18, [R2.64] ;
LDG.E.U8 R21, [R2.64+0x1] ;
LDG.E.U8 R22, [R2.64+0x2] ;
LDG.E.U8 R23, [R2.64+0x3] ;
LDG.E.U8 R19, [R2.64+0x4] ;
LDG.E.U8 R20, [R2.64+0x5] ;
LDG.E.U8 R16, [R2.64+0x6] ;
LDG.E.U8 R17, [R2.64+0x7] ;
LDG.E.U8 R26, [R2.64+0xc] ;
IADD3 R21, R21, R13, R18 ;
LDG.E.U8 R13, [R2.64+0x8] ;
LDG.E.U8 R18, [R2.64+0x9] ;
IADD3 R23, R23, R21, R22 ;
LDG.E.U8 R21, [R2.64+0xa] ;
LDG.E.U8 R22, [R2.64+0xb] ;
IADD3 R25, R20, R23, R19 ;
LDG.E.U8 R23, [R2.64+0xd] ;
LDG.E.U8 R19, [R2.64+0xe] ;
LDG.E.U8 R20, [R2.64+0xf] ;
IADD3 R15, R15, 0x10, RZ ;
IADD3 R16, R17, R25, R16 ;
ISETP.GE.AND P2, PT, R15, R14, PT ;
IADD3 R13, R18, R16, R13 ;
IADD3 R16, P3, R2, 0x10, RZ ;
IADD3 R13, R22, R13, R21 ;
IMAD.X R17, RZ, RZ, R3, P3 ;
IADD3 R13, R23, R13, R26 ;
IMAD.MOV.U32 R2, RZ, RZ, R16 ;
IMAD.MOV.U32 R3, RZ, RZ, R17 ;
IADD3 R13, R20, R13, R19 ;
@!P2 BRA 0x690 ;
BSYNC B2 ;
IMAD.IADD R14, R6, 0x1, -R15 ;
BSSY B2, 0xa00 ;
ISETP.GT.AND P2, PT, R14, 0x4, PT ;
@!P2 BRA 0x9f0 ;
LDG.E.U8 R14, [R2.64] ;
LDG.E.U8 R16, [R2.64+0x1] ;
LDG.E.U8 R17, [R2.64+0x2] ;
LDG.E.U8 R18, [R2.64+0x3] ;
LDG.E.U8 R19, [R2.64+0x4] ;
LDG.E.U8 R20, [R2.64+0x5] ;
LDG.E.U8 R21, [R2.64+0x6] ;
LDG.E.U8 R22, [R2.64+0x7] ;
PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ;
IADD3 R15, R15, 0x8, RZ ;
IADD3 R14, R16, R13, R14 ;
IADD3 R16, P2, R2, 0x8, RZ ;
IMAD.MOV.U32 R2, RZ, RZ, R16 ;
IADD3 R14, R18, R14, R17 ;
IMAD.X R17, RZ, RZ, R3, P2 ;
IMAD.MOV.U32 R3, RZ, RZ, R17 ;
IADD3 R14, R20, R14, R19 ;
IADD3 R13, R22, R14, R21 ;
BSYNC B2 ;
ISETP.LT.OR P0, PT, R15, R6, P0 ;
@!P0 BRA 0xa80 ;
LDG.E.U8 R14, [R2.64] ;
LDG.E.U8 R15, [R2.64+0x1] ;
LDG.E.U8 R16, [R2.64+0x2] ;
LDG.E.U8 R17, [R2.64+0x3] ;
IADD3 R13, R15, R13, R14 ;
IADD3 R13, R17, R13, R16 ;
BSYNC B1 ;
ISETP.GE.AND P0, PT, R11.reuse, R4, PT ;
IADD3 R11, R11, 0x1, RZ ;
@!P0 BRA 0x460 ;
BSYNC B0 ;
IADD3 R6, R6, 0x1, -R9 ;
IADD3 R7, R4, 0x1, -R7 ;
IABS R10, R13 ;
IMAD R6, R6, R7, RZ ;
IABS R7, R6.reuse ;
IABS R11, R6.reuse ;
I2F.RP R4, R7 ;
LOP3.LUT R13, R13, R6, RZ, 0x3c, !PT ;
ISETP.GE.AND P0, PT, R13, RZ, PT ;
MUFU.RCP R4, R4 ;
IADD3 R2, R4, 0xffffffe, RZ ;
IMAD.MOV R4, RZ, RZ, -R11 ;
F2I.FTZ.U32.TRUNC.NTZ R3, R2 ;
IMAD.MOV.U32 R2, RZ, RZ, RZ ;
IMAD.MOV R8, RZ, RZ, -R3 ;
IMAD R9, R8, R7, RZ ;
IMAD.MOV.U32 R8, RZ, RZ, R10 ;
IMAD.HI.U32 R3, R3, R9, R2 ;
IMAD.HI.U32 R3, R3, R8, RZ ;
IMAD R2, R3, R4, R8 ;
LDC.U16 R4, c[0x0][0x178] ;
ISETP.GT.U32.AND P2, PT, R7, R2, PT ;
@!P2 IMAD.IADD R2, R2, 0x1, -R7 ;
@!P2 IADD3 R3, R3, 0x1, RZ ;
ISETP.NE.AND P2, PT, R6, RZ, PT ;
ISETP.GE.U32.AND P1, PT, R2, R7, PT ;
PRMT R2, R4, 0x9910, RZ ;
@P1 IADD3 R3, R3, 0x1, RZ ;
ISETP.NE.AND P1, PT, R2, 0x8, PT ;
IMAD.MOV.U32 R9, RZ, RZ, R3 ;
@!P0 IMAD.MOV R9, RZ, RZ, -R9 ;
@!P2 LOP3.LUT R9, RZ, R6, RZ, 0x33, !PT ;
@!P1 BRA 0xda0 ;
ISETP.NE.AND P0, PT, R2, 0x18, PT ;
@P0 EXIT ;
IMAD R0, R0, c[0x0][0x170], R5 ;
SHF.R.U32.HI R5, RZ, 0x10, R9.reuse ;
SHF.R.U32.HI R7, RZ, 0x8, R9 ;
IMAD R0, R0, 0x3, RZ ;
IADD3 R2, P0, R0, c[0x0][0x168], RZ ;
LEA.HI.X.SX32 R3, R0, c[0x0][0x16c], 0x1, P0 ;
STG.E.U8 [R2.64], R5 ;
STG.E.U8 [R2.64+0x1], R7 ;
STG.E.U8 [R2.64+0x2], R9 ;
EXIT ;
IMAD R0, R0, c[0x0][0x170], R5 ;
IADD3 R2, P0, R0, c[0x0][0x168], RZ ;
LEA.HI.X.SX32 R3, R0, c[0x0][0x16c], 0x1, P0 ;
STG.E.U8 [R2.64], R9 ;
EXIT ;
BRA 0xdf0;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
```
|
```amdasm
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z13meanFilterGPUPhS_iisi ; -- Begin function _Z13meanFilterGPUPhS_iisi
.globl _Z13meanFilterGPUPhS_iisi
.p2align 8
.type _Z13meanFilterGPUPhS_iisi,@function
_Z13meanFilterGPUPhS_iisi: ; @_Z13meanFilterGPUPhS_iisi
; %bb.0:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b128 s[4:7], s[0:1], 0x10
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_lshr_b32 s3, s2, 16
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[0:1], null, s14, s2, v[2:3]
v_mad_u64_u32 v[1:2], null, s15, s3, v[3:4]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_gt_i32_e32 vcc_lo, s4, v0
v_cmp_gt_i32_e64 s2, s5, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, vcc_lo, s2
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_25
; %bb.1:
s_load_b128 s[8:11], s[0:1], 0x0
s_lshr_b32 s2, s7, 31
s_add_i32 s1, s5, -1
s_add_i32 s2, s7, s2
v_mov_b32_e32 v8, 0
s_ashr_i32 s0, s2, 1
s_mov_b32 s2, 0
v_subrev_nc_u32_e32 v2, s0, v1
v_add_nc_u32_e32 v3, s0, v1
v_subrev_nc_u32_e32 v4, s0, v0
v_add_nc_u32_e32 v5, s0, v0
s_add_i32 s0, s4, -1
v_max_i32_e32 v2, 0, v2
v_min_i32_e32 v3, s1, v3
v_max_i32_e32 v4, 0, v4
v_min_i32_e32 v5, s0, v5
s_mov_b32 s1, exec_lo
s_delay_alu instid0(VALU_DEP_3)
v_cmpx_ge_i32_e64 v3, v2
s_cbranch_execz .LBB0_18
; %bb.2: ; %.preheader.lr.ph
v_mul_lo_u32 v6, s4, v2
v_cmp_ge_i32_e64 s0, v5, v4
v_mov_b32_e32 v9, v2
s_mul_i32 s3, s4, 3
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_mov_b32 v8, 0 :: v_dual_add_nc_u32 v7, v4, v6
v_lshl_add_u32 v7, v7, 1, v7
.LBB0_3: ; %.preheader
; =>This Loop Header: Depth=1
; Child Loop BB0_5 Depth 2
s_and_saveexec_b32 s5, s0
s_cbranch_execz .LBB0_16
; %bb.4: ; %.lr.ph
; in Loop: Header=BB0_3 Depth=1
s_delay_alu instid0(VALU_DEP_1)
v_dual_mov_b32 v10, v7 :: v_dual_mov_b32 v11, v4
s_mov_b32 s7, 0
.LBB0_5: ; %NodeBlock143
; Parent Loop BB0_3 Depth=1
; => This Inner Loop Header: Depth=2
v_cmp_lt_i16_e64 s12, s6, 24
v_mov_b32_e32 v12, v8
s_delay_alu instid0(VALU_DEP_2)
s_and_b32 vcc_lo, exec_lo, s12
s_cbranch_vccnz .LBB0_9
; %bb.6: ; %LeafBlock141
; in Loop: Header=BB0_5 Depth=2
v_cmp_eq_u16_e64 s12, s6, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mov_b32_e32 v8, v12
s_and_b32 vcc_lo, exec_lo, s12
s_cbranch_vccz .LBB0_8
; %bb.7: ; in Loop: Header=BB0_5 Depth=2
v_ashrrev_i32_e32 v8, 31, v10
s_waitcnt lgkmcnt(0)
v_add_co_u32 v13, vcc_lo, s8, v10
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v14, vcc_lo, s9, v8, vcc_lo
s_clause 0x1
global_load_u16 v8, v[13:14], off
global_load_u8 v13, v[13:14], off offset:2
s_waitcnt vmcnt(1)
v_and_b32_e32 v14, 0xff, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_perm_b32 v8, v14, v8, 0x504010c
s_waitcnt vmcnt(0)
v_or_b32_e32 v8, v8, v13
s_delay_alu instid0(VALU_DEP_1)
v_add_nc_u32_e32 v8, v8, v12
.LBB0_8: ; %Flow148
; in Loop: Header=BB0_5 Depth=2
s_mov_b32 s12, 0
s_branch .LBB0_10
.LBB0_9: ; in Loop: Header=BB0_5 Depth=2
s_mov_b32 s12, -1
; implicit-def: $vgpr8
.LBB0_10: ; %Flow150
; in Loop: Header=BB0_5 Depth=2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 vcc_lo, exec_lo, s12
s_cbranch_vccnz .LBB0_14
; %bb.11: ; %LeafBlock139
; in Loop: Header=BB0_5 Depth=2
v_cmp_ne_u16_e64 s12, s6, 8
s_delay_alu instid0(VALU_DEP_1)
s_and_b32 vcc_lo, exec_lo, s12
s_cbranch_vccnz .LBB0_13
; %bb.12: ; in Loop: Header=BB0_5 Depth=2
v_add_nc_u32_e32 v8, v6, v11
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v14, 31, v8
s_waitcnt lgkmcnt(0)
v_add_co_u32 v13, vcc_lo, s8, v8
v_add_co_ci_u32_e32 v14, vcc_lo, s9, v14, vcc_lo
global_load_u8 v8, v[13:14], off
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v12, v12, v8
.LBB0_13: ; %Flow149
; in Loop: Header=BB0_5 Depth=2
s_delay_alu instid0(VALU_DEP_1)
v_mov_b32_e32 v8, v12
.LBB0_14: ; in Loop: Header=BB0_5 Depth=2
v_add_nc_u32_e32 v12, 1, v11
v_cmp_ge_i32_e32 vcc_lo, v11, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_dual_mov_b32 v11, v12 :: v_dual_add_nc_u32 v10, 3, v10
s_or_b32 s7, vcc_lo, s7
s_and_not1_b32 exec_lo, exec_lo, s7
s_cbranch_execnz .LBB0_5
; %bb.15: ; %Flow151
; in Loop: Header=BB0_3 Depth=1
s_or_b32 exec_lo, exec_lo, s7
.LBB0_16: ; %Flow152
; in Loop: Header=BB0_3 Depth=1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
s_or_b32 exec_lo, exec_lo, s5
v_add_nc_u32_e32 v10, 1, v9
v_cmp_ge_i32_e32 vcc_lo, v9, v3
v_add_nc_u32_e32 v7, s3, v7
v_dual_mov_b32 v9, v10 :: v_dual_add_nc_u32 v6, s4, v6
s_or_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s2
s_cbranch_execnz .LBB0_3
; %bb.17: ; %Flow153
s_or_b32 exec_lo, exec_lo, s2
.LBB0_18: ; %Flow154
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(VALU_DEP_4)
s_or_b32 exec_lo, exec_lo, s1
v_sub_nc_u32_e32 v4, v5, v4
v_sub_nc_u32_e32 v5, v3, v2
v_ashrrev_i32_e32 v6, 31, v8
v_cmp_lt_i16_e64 s0, s6, 24
v_add_nc_u32_e32 v2, 1, v4
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v7, v8, v6
v_mad_u64_u32 v[3:4], null, v2, v5, v[2:3]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_xor_b32_e32 v7, v7, v6
v_ashrrev_i32_e32 v2, 31, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v3, v3, v2
v_xor_b32_e32 v3, v3, v2
v_xor_b32_e32 v2, v6, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cvt_f32_u32_e32 v4, v3
v_sub_nc_u32_e32 v5, 0, v3
v_rcp_iflag_f32_e32 v4, v4
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v4, 0x4f7ffffe, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_u32_f32_e32 v4, v4
v_mul_lo_u32 v5, v5, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v5, v4, v5
v_add_nc_u32_e32 v4, v4, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v4, v7, v4
v_mul_lo_u32 v5, v4, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v5, v7, v5
v_add_nc_u32_e32 v7, 1, v4
v_sub_nc_u32_e32 v8, v5, v3
v_cmp_ge_u32_e32 vcc_lo, v5, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_cndmask_b32 v5, v5, v8 :: v_dual_cndmask_b32 v4, v4, v7
v_cmp_ge_u32_e32 vcc_lo, v5, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v7, 1, v4
v_cndmask_b32_e32 v3, v4, v7, vcc_lo
s_and_b32 vcc_lo, exec_lo, s0
s_mov_b32 s0, -1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_xor_b32_e32 v3, v3, v2
v_sub_nc_u32_e32 v2, v3, v2
s_cbranch_vccnz .LBB0_22
; %bb.19: ; %LeafBlock137
v_cmp_eq_u16_e64 s0, s6, 24
s_delay_alu instid0(VALU_DEP_1)
s_and_b32 vcc_lo, exec_lo, s0
s_cbranch_vccz .LBB0_21
; %bb.20:
v_mad_u64_u32 v[3:4], null, v1, s4, v[0:1]
v_lshrrev_b32_e32 v4, 8, v2
v_lshrrev_b32_e32 v5, 16, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
v_lshlrev_b16 v6, 8, v4
v_lshl_add_u32 v3, v3, 1, v3
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_and_b32_e32 v5, 0xff, v5
v_ashrrev_i32_e32 v4, 31, v3
s_waitcnt lgkmcnt(0)
v_add_co_u32 v3, vcc_lo, s10, v3
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_or_b32_e32 v5, v5, v6
v_add_co_ci_u32_e32 v4, vcc_lo, s11, v4, vcc_lo
s_clause 0x1
global_store_b8 v[3:4], v2, off offset:2
global_store_b16 v[3:4], v5, off
.LBB0_21: ; %Flow
s_mov_b32 s0, 0
.LBB0_22: ; %Flow146
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 vcc_lo, exec_lo, s0
s_cbranch_vccnz .LBB0_25
; %bb.23: ; %LeafBlock
v_cmp_eq_u16_e64 s0, s6, 8
s_delay_alu instid0(VALU_DEP_1)
s_and_b32 vcc_lo, exec_lo, s0
s_cbranch_vccz .LBB0_25
; %bb.24:
v_mad_u64_u32 v[3:4], null, v1, s4, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v1, 31, v3
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s10, v3
v_add_co_ci_u32_e32 v1, vcc_lo, s11, v1, vcc_lo
global_store_b8 v[0:1], v2, off
.LBB0_25:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13meanFilterGPUPhS_iisi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 15
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z13meanFilterGPUPhS_iisi, .Lfunc_end0-_Z13meanFilterGPUPhS_iisi
; -- End function
.section .AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1008
; NumSgprs: 18
; NumVgprs: 15
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 15
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object ; @__hip_cuid_
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0 ; 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 2
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13meanFilterGPUPhS_iisi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z13meanFilterGPUPhS_iisi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 15
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
```
| 4,327 | 6,508 |
371 |
Convert the following CUDA host assembly code to AMD host assembly:
```cudaasm
.file "tmpxft_00061f4e_00000000-6_16_ENG_081_mean_filter.cudafe1.cpp"
.text
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z13meanFilterCPUPhS_iisi
.type _Z13meanFilterCPUPhS_iisi, @function
_Z13meanFilterCPUPhS_iisi:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
movq %rsi, -48(%rsp)
movl %edx, %eax
movl %ecx, %edx
leal -1(%r9), %ecx
movl %ecx, %esi
shrl $31, %esi
addl %esi, %ecx
sarl %ecx
testl %edx, %edx
je .L3
movq %rdi, %r12
movl %r8d, %r14d
movl %ecx, %r10d
movslq %edx, %rbp
movslq %eax, %r15
leal (%rax,%rax,2), %r9d
movl $0, %edi
movl $1, %r8d
leal -1(%rcx), %ebx
leal -1(%rdx), %r11d
subl $1, %eax
movl %eax, -40(%rsp)
movq %r8, %rcx
movq %r12, %r13
jmp .L15
.L23:
movzbl (%r15,%rdx), %esi
addl %esi, %eax
.L9:
addq $1, %rdx
addl $3, %ecx
cmpq %rdx, %rdi
jb .L22
.L10:
cmpw $8, %r14w
je .L23
cmpw $24, %r14w
jne .L9
movslq %ecx, %r8
movzbl 0(%r13,%r8), %ebx
sall $16, %ebx
movzbl 2(%r13,%r8), %esi
orl %ebx, %esi
movzbl 1(%r13,%r8), %r8d
sall $8, %r8d
orl %r8d, %esi
addl %esi, %eax
jmp .L9
.L22:
movq -112(%rsp), %rbx
.L7:
addq $1, %r11
addq %r10, %rbx
addl %r9d, %ebp
cmpq %r11, -104(%rsp)
jb .L24
.L11:
cmpq %r12, %rdi
jb .L7
movl %ebp, %ecx
movq %r12, %rdx
leaq 0(%r13,%rbx), %r15
movq %rbx, -112(%rsp)
jmp .L10
.L24:
movl -96(%rsp), %edx
movl -92(%rsp), %ecx
movq -88(%rsp), %rsi
movq %r10, %r15
movl -80(%rsp), %r8d
.L6:
subl %edx, %ecx
addl $1, %ecx
movl -60(%rsp), %ebx
imull %ebx, %ecx
cltd
idivl %ecx
cmpw $8, %r14w
je .L25
cmpw $24, %r14w
je .L26
.L13:
addq $1, %rsi
addl $3, -76(%rsp)
cmpq %r15, %rsi
je .L27
.L14:
movl %esi, -64(%rsp)
movl %esi, %edx
subl %r8d, %edx
movl $0, %eax
cmovs %eax, %edx
leal (%r8,%rsi), %eax
movl -40(%rsp), %ebx
cmpl %eax, %ebx
cmovle %ebx, %eax
movl %eax, %ecx
movq -72(%rsp), %r11
cmpq %r11, -104(%rsp)
jb .L16
movslq %edx, %r12
movq -56(%rsp), %rbx
leaq (%rbx,%r12), %rax
leal (%rax,%rax,2), %ebp
movl $0, %eax
movslq %ecx, %rdi
movl %edx, -96(%rsp)
movl %ecx, -92(%rsp)
movq %rsi, -88(%rsp)
movq %r15, %r10
movl %r8d, -80(%rsp)
jmp .L11
.L16:
movl $0, %eax
jmp .L6
.L25:
movl -64(%rsp), %edx
movl -36(%rsp), %ebx
addl %ebx, %edx
movslq %edx, %rdx
movq -48(%rsp), %rdi
movb %al, (%rdi,%rdx)
jmp .L13
.L26:
movslq -76(%rsp), %rdx
movl %eax, %ecx
sarl $16, %ecx
movq -48(%rsp), %rdi
movb %cl, (%rdi,%rdx)
movzbl %ah, %ebx
movb %bl, 1(%rdi,%rdx)
movb %al, 2(%rdi,%rdx)
jmp .L13
.L27:
movq -32(%rsp), %rbp
movq -24(%rsp), %rcx
movq -16(%rsp), %rdi
movl %r8d, %r10d
movl -8(%rsp), %ebx
movl -4(%rsp), %r11d
.L5:
leaq 1(%rcx), %rax
addq %r15, %rdi
cmpq %rcx, %rbp
je .L3
movq %rax, %rcx
.L15:
movl %ecx, %edx
subl %r10d, %edx
subl $1, %edx
movl $0, %eax
cmovs %eax, %edx
leal (%rbx,%rcx), %eax
cmpl %r11d, %eax
cmovg %r11d, %eax
testq %r15, %r15
je .L5
movl %edi, -36(%rsp)
leal (%rdi,%rdi,2), %esi
movl %esi, -76(%rsp)
movslq %edx, %rsi
movq %rsi, -72(%rsp)
imulq %r15, %rsi
movq %rsi, -56(%rsp)
movl $0, %esi
movslq %eax, %r8
movq %r8, -104(%rsp)
subl %edx, %eax
addl $1, %eax
movl %eax, -60(%rsp)
movq %rbp, -32(%rsp)
movq %rcx, -24(%rsp)
movq %rdi, -16(%rsp)
movl %r10d, %r8d
movl %ebx, -8(%rsp)
movl %r11d, -4(%rsp)
jmp .L14
.L3:
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size _Z13meanFilterCPUPhS_iisi, .-_Z13meanFilterCPUPhS_iisi
.globl _Z39__device_stub__Z13meanFilterGPUPhS_iisiPhS_iisi
.type _Z39__device_stub__Z13meanFilterGPUPhS_iisiPhS_iisi, @function
_Z39__device_stub__Z13meanFilterGPUPhS_iisiPhS_iisi:
.LFB2083:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r9d, (%rsp)
movw %r8w, 4(%rsp)
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 4(%rsp), %rax
movq %rax, 128(%rsp)
movq %rsp, %rax
movq %rax, 136(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L32
.L28:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L33
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L32:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 184
pushq 40(%rsp)
.cfi_def_cfa_offset 192
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z13meanFilterGPUPhS_iisi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L28
.L33:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z39__device_stub__Z13meanFilterGPUPhS_iisiPhS_iisi, .-_Z39__device_stub__Z13meanFilterGPUPhS_iisiPhS_iisi
.globl _Z13meanFilterGPUPhS_iisi
.type _Z13meanFilterGPUPhS_iisi, @function
_Z13meanFilterGPUPhS_iisi:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movswl %r8w, %r8d
call _Z39__device_stub__Z13meanFilterGPUPhS_iisiPhS_iisi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z13meanFilterGPUPhS_iisi, .-_Z13meanFilterGPUPhS_iisi
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "rb"
.LC1:
.string "imgWidtht : %d\n"
.LC2:
.string "imgHeight : %d\n"
.LC3:
.string "bitsPerPixel : %d\n"
.LC4:
.string "image size : %d\n"
.LC5:
.string "offset : %d\n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC6:
.string "%d pixelBeforeFilter:%d cpuFilteredPixel:%d gpuFilteredPixel:%d\n"
.text
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $104, %rsp
.cfi_def_cfa_offset 160
movq %rsi, %rbx
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
movl $54, %edi
call malloc@PLT
movq %rax, %r15
movq %rax, 24(%rsp)
movq 8(%rbx), %rdi
leaq .LC0(%rip), %rsi
call fopen@PLT
movq %rax, %r14
movq %rax, 8(%rsp)
movq 16(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, 16(%rsp)
movq %r14, %r8
movl $54, %ecx
movl $1, %edx
movl $54, %esi
movq %r15, %rdi
call __fread_chk@PLT
movq %r15, %rax
movl 18(%r15), %ebx
movl 22(%r15), %r15d
movzwl 28(%rax), %edx
movw %dx, 6(%rsp)
movl 10(%rax), %ebp
cmpw $8, %dx
je .L48
cmpw $24, 6(%rsp)
je .L49
.L38:
movl %ebx, %edx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %r15d, %edx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movswl 6(%rsp), %eax
movl %eax, 40(%rsp)
movl %eax, %edx
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 44(%rsp), %r14d
movl %r14d, %edx
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %ebp, %edx
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
subl $54, %ebp
movslq %ebp, %rbp
movq %rbp, %rdi
call malloc@PLT
movq %rax, 32(%rsp)
movq 8(%rsp), %r12
movq %r12, %r8
movq %rbp, %rcx
movl $1, %edx
movq %rbp, %rsi
movq %rax, %rdi
call __fread_chk@PLT
movslq %r14d, %r14
movq %r14, %rdi
call malloc@PLT
movq %rax, %rbp
movq %r12, %r8
movq %r14, %rcx
movl $1, %edx
movq %r14, %rsi
movq %rax, %rdi
call __fread_chk@PLT
movq %r14, %rdi
call malloc@PLT
movq %rax, %r13
movq %r14, %rdi
call malloc@PLT
movq %rax, %r12
leaq 56(%rsp), %rdi
movq %r14, %rsi
call cudaMalloc@PLT
leaq 48(%rsp), %rdi
movq %r14, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %r14, %rdx
movq %rbp, %rsi
movq 56(%rsp), %rdi
call cudaMemcpy@PLT
movl 16(%rsp), %r9d
movl 40(%rsp), %r8d
movl %r15d, %ecx
movl %ebx, %edx
movq %r13, %rsi
movq %rbp, %rdi
call _Z13meanFilterCPUPhS_iisi
movl $32, 64(%rsp)
movl $32, 68(%rsp)
leal 31(%rbx), %eax
testl %ebx, %ebx
cmovns %ebx, %eax
sarl $5, %eax
movl %eax, 76(%rsp)
leal 31(%r15), %eax
testl %r15d, %r15d
cmovns %r15d, %eax
sarl $5, %eax
movl %eax, 80(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 64(%rsp), %rdx
movl $1, %ecx
movq 76(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L50
.L39:
movl $2, %ecx
movq %r14, %rdx
movq 48(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
cmpw $8, 6(%rsp)
je .L51
cmpw $24, 6(%rsp)
je .L52
.L41:
movq 8(%rsp), %rdi
call fclose@PLT
movq %rbp, %rdi
call free@PLT
movq 32(%rsp), %rdi
call free@PLT
movq 24(%rsp), %rdi
call free@PLT
movq %r13, %rdi
call free@PLT
movq %r12, %rdi
call free@PLT
movq 56(%rsp), %rdi
call cudaFree@PLT
movq 48(%rsp), %rdi
call cudaFree@PLT
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L53
movl $0, %eax
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L48:
.cfi_restore_state
movl %r15d, %eax
imull %ebx, %eax
movl %eax, 44(%rsp)
jmp .L38
.L49:
movl %r15d, %eax
imull %ebx, %eax
imull $3, %eax, %eax
movl %eax, 44(%rsp)
jmp .L38
.L50:
movl 16(%rsp), %r9d
movl 40(%rsp), %r8d
movl %r15d, %ecx
movl %ebx, %edx
movq 48(%rsp), %rsi
movq 56(%rsp), %rdi
call _Z39__device_stub__Z13meanFilterGPUPhS_iisiPhS_iisi
jmp .L39
.L51:
testq %r14, %r14
je .L41
movl $0, %ebx
leaq .LC6(%rip), %r15
.L42:
movzbl 0(%rbp,%rbx), %ecx
movzbl (%r12,%rbx), %r9d
movzbl 0(%r13,%rbx), %r8d
movq %rbx, %rdx
movq %r15, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq %rbx, %r14
jne .L42
jmp .L41
.L52:
movl 44(%rsp), %r15d
testl %r15d, %r15d
jle .L41
movl $0, %ebx
leaq .LC6(%rip), %r14
.L43:
movzbl (%r12,%rbx), %r9d
sall $16, %r9d
movzbl 1(%r12,%rbx), %eax
sall $8, %eax
orl %eax, %r9d
movzbl 2(%r12,%rbx), %esi
movzbl 0(%r13,%rbx), %r8d
sall $16, %r8d
movzbl 1(%r13,%rbx), %eax
sall $8, %eax
orl %eax, %r8d
movzbl 2(%r13,%rbx), %edx
movzbl 0(%rbp,%rbx), %ecx
sall $16, %ecx
movzbl 1(%rbp,%rbx), %eax
sall $8, %eax
orl %eax, %ecx
movzbl 2(%rbp,%rbx), %eax
orl %eax, %ecx
orl %esi, %r9d
orl %edx, %r8d
movl %ebx, %edx
movq %r14, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $3, %rbx
cmpl %ebx, %r15d
jg .L43
jmp .L41
.L53:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.1
.LC7:
.string "_Z13meanFilterGPUPhS_iisi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _Z13meanFilterGPUPhS_iisi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
```
|
```amdasm
.text
.file "16_ENG_081_mean_filter.hip"
.globl _Z13meanFilterCPUPhS_iisi # -- Begin function _Z13meanFilterCPUPhS_iisi
.type _Z13meanFilterCPUPhS_iisi,@function
_Z13meanFilterCPUPhS_iisi: # @_Z13meanFilterCPUPhS_iisi
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $16, %rsp
.cfi_def_cfa_offset 72
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
# kill: def $r9d killed $r9d def $r9
movl %r8d, -88(%rsp) # 4-byte Spill
movl %edx, -124(%rsp) # 4-byte Spill
movq %rsi, -72(%rsp) # 8-byte Spill
testl %ecx, %ecx
je .LBB0_12
# %bb.1: # %.lr.ph111
movl %ecx, %edx
movl %r9d, %eax
decl %eax
shrl $31, %eax
addl %r9d, %eax
decl %eax
sarl %eax
movslq %ecx, %rcx
movq %rcx, -32(%rsp) # 8-byte Spill
movabsq $12884901888, %rbx # imm = 0x300000000
decl %edx
movl %edx, -100(%rsp) # 4-byte Spill
movslq -124(%rsp), %rcx # 4-byte Folded Reload
leal -1(%rcx), %edx
movl %edx, -92(%rsp) # 4-byte Spill
movq %rax, -56(%rsp) # 8-byte Spill
movl %eax, %edx
negl %edx
movq %rcx, -112(%rsp) # 8-byte Spill
movq %rcx, %rax
shlq $32, %rax
leaq (%rax,%rax,2), %rax
movq %rax, -8(%rsp) # 8-byte Spill
movl %edx, -104(%rsp) # 4-byte Spill
xorl %eax, %eax
movq %rax, -120(%rsp) # 8-byte Spill
.LBB0_2: # =>This Loop Header: Depth=1
# Child Loop BB0_4 Depth 2
# Child Loop BB0_6 Depth 3
# Child Loop BB0_13 Depth 4
testl %edx, %edx
movl $0, %eax
movl %edx, -96(%rsp) # 4-byte Spill
cmovgl %edx, %eax
cmpl $0, -124(%rsp) # 4-byte Folded Reload
je .LBB0_11
# %bb.3: # %.lr.ph107
# in Loop: Header=BB0_2 Depth=1
movq -112(%rsp), %rdx # 8-byte Reload
imulq %rdx, %rax
movq %rax, -16(%rsp) # 8-byte Spill
addq %rdi, %rax
movq %rax, -24(%rsp) # 8-byte Spill
movq -56(%rsp), %rcx # 8-byte Reload
movq -120(%rsp), %rsi # 8-byte Reload
leal (%rcx,%rsi), %r8d
movl -100(%rsp), %eax # 4-byte Reload
cmpl %eax, %r8d
cmovgel %eax, %r8d
movl %esi, %r9d
subl %ecx, %r9d
testl %r9d, %r9d
movl $0, %eax
cmovlel %eax, %r9d
movl %r8d, -80(%rsp) # 4-byte Spill
movslq %r8d, %rax
movq %rax, (%rsp) # 8-byte Spill
# kill: def $eax killed $eax killed $rax
movq %r9, -48(%rsp) # 8-byte Spill
subl %r9d, %eax
incl %eax
movl %eax, -84(%rsp) # 4-byte Spill
imulq %rdx, %rsi
movq %rsi, -64(%rsp) # 8-byte Spill
movl -104(%rsp), %ecx # 4-byte Reload
xorl %r9d, %r9d
.LBB0_4: # Parent Loop BB0_2 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB0_6 Depth 3
# Child Loop BB0_13 Depth 4
xorl %eax, %eax
testl %ecx, %ecx
movl $0, %r8d
movl %ecx, -76(%rsp) # 4-byte Spill
cmovgl %ecx, %r8d
movq -56(%rsp), %rcx # 8-byte Reload
leal (%rcx,%r9), %r15d
movq %r9, -40(%rsp) # 8-byte Spill
movl %r9d, %r11d
subl %ecx, %r11d
testl %r11d, %r11d
cmovlel %eax, %r11d
movl -92(%rsp), %ecx # 4-byte Reload
cmpl %ecx, %r15d
cmovgel %ecx, %r15d
movswl -88(%rsp), %esi # 2-byte Folded Reload
movq -48(%rsp), %rcx # 8-byte Reload
cmpl %ecx, -80(%rsp) # 4-byte Folded Reload
jb .LBB0_8
# %bb.5: # %.lr.ph102
# in Loop: Header=BB0_4 Depth=2
addq -16(%rsp), %r8 # 8-byte Folded Reload
imulq %rbx, %r8
movl %r11d, %eax
movq %rax, 8(%rsp) # 8-byte Spill
movslq %r15d, %rbp
xorl %eax, %eax
movq -24(%rsp), %r13 # 8-byte Reload
movq -48(%rsp), %r10 # 8-byte Reload
.LBB0_6: # Parent Loop BB0_2 Depth=1
# Parent Loop BB0_4 Depth=2
# => This Loop Header: Depth=3
# Child Loop BB0_13 Depth 4
movq %r8, %rdx
movq 8(%rsp), %r9 # 8-byte Reload
cmpl %r11d, %r15d
jb .LBB0_7
.LBB0_13: # Parent Loop BB0_2 Depth=1
# Parent Loop BB0_4 Depth=2
# Parent Loop BB0_6 Depth=3
# => This Inner Loop Header: Depth=4
cmpl $24, %esi
je .LBB0_16
# %bb.14: # in Loop: Header=BB0_13 Depth=4
cmpl $8, %esi
jne .LBB0_17
# %bb.15: # in Loop: Header=BB0_13 Depth=4
movzbl (%r13,%r9), %r14d
addl %r14d, %eax
jmp .LBB0_17
.LBB0_16: # in Loop: Header=BB0_13 Depth=4
movq %rdx, %r14
sarq $32, %r14
movzbl (%rdi,%r14), %ecx
movzbl 1(%rdi,%r14), %r12d
movzbl 2(%rdi,%r14), %r14d
shll $16, %ecx
shll $8, %r12d
orl %ecx, %r12d
orl %r14d, %r12d
addl %r12d, %eax
.LBB0_17: # in Loop: Header=BB0_13 Depth=4
incq %r9
addq %rbx, %rdx
cmpq %rbp, %r9
jbe .LBB0_13
.LBB0_7: # %._crit_edge
# in Loop: Header=BB0_6 Depth=3
incq %r10
addq -8(%rsp), %r8 # 8-byte Folded Reload
addq -112(%rsp), %r13 # 8-byte Folded Reload
cmpq (%rsp), %r10 # 8-byte Folded Reload
jbe .LBB0_6
.LBB0_8: # %._crit_edge103
# in Loop: Header=BB0_4 Depth=2
subl %r11d, %r15d
incl %r15d
imull -84(%rsp), %r15d # 4-byte Folded Reload
cltd
idivl %r15d
cmpl $8, %esi
je .LBB0_18
# %bb.9: # %._crit_edge103
# in Loop: Header=BB0_4 Depth=2
cmpl $24, %esi
movq -40(%rsp), %r9 # 8-byte Reload
jne .LBB0_19
# %bb.10: # in Loop: Header=BB0_4 Depth=2
movq -64(%rsp), %rcx # 8-byte Reload
addq %r9, %rcx
movl %eax, %edx
shrl $16, %edx
imulq %rbx, %rcx
sarq $32, %rcx
movq -72(%rsp), %rsi # 8-byte Reload
movb %dl, (%rsi,%rcx)
movb %ah, 1(%rsi,%rcx)
movb %al, 2(%rsi,%rcx)
jmp .LBB0_19
.LBB0_18: # in Loop: Header=BB0_4 Depth=2
movq -64(%rsp), %rcx # 8-byte Reload
movq -40(%rsp), %r9 # 8-byte Reload
addl %r9d, %ecx
movslq %ecx, %rcx
movq -72(%rsp), %rdx # 8-byte Reload
movb %al, (%rdx,%rcx)
.LBB0_19: # in Loop: Header=BB0_4 Depth=2
incq %r9
movl -76(%rsp), %ecx # 4-byte Reload
incl %ecx
cmpq -112(%rsp), %r9 # 8-byte Folded Reload
jne .LBB0_4
.LBB0_11: # %._crit_edge108
# in Loop: Header=BB0_2 Depth=1
movq -120(%rsp), %rcx # 8-byte Reload
incq %rcx
movl -96(%rsp), %edx # 4-byte Reload
incl %edx
movq %rcx, %rax
movq %rcx, -120(%rsp) # 8-byte Spill
cmpq -32(%rsp), %rcx # 8-byte Folded Reload
jne .LBB0_2
.LBB0_12: # %._crit_edge112
addq $16, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z13meanFilterCPUPhS_iisi, .Lfunc_end0-_Z13meanFilterCPUPhS_iisi
.cfi_endproc
# -- End function
.globl _Z28__device_stub__meanFilterGPUPhS_iisi # -- Begin function _Z28__device_stub__meanFilterGPUPhS_iisi
.type _Z28__device_stub__meanFilterGPUPhS_iisi,@function
_Z28__device_stub__meanFilterGPUPhS_iisi: # @_Z28__device_stub__meanFilterGPUPhS_iisi
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $128, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 40(%rsp), %rax
movq %rdi, (%rax)
leaq 32(%rsp), %rdi
movq %rsi, (%rdi)
leaq 12(%rsp), %rsi
movl %edx, (%rsi)
leaq 8(%rsp), %rdx
movl %ecx, (%rdx)
leaq 2(%rsp), %rcx
movw %r8w, (%rcx)
leaq 4(%rsp), %r8
movl %r9d, (%r8)
leaq 80(%rsp), %rbx
movq %rax, (%rbx)
movq %rdi, 8(%rbx)
movq %rsi, 16(%rbx)
movq %rdx, 24(%rbx)
movq %rcx, 32(%rbx)
movq %r8, 40(%rbx)
leaq 64(%rsp), %r14
leaq 48(%rsp), %r15
leaq 24(%rsp), %r12
leaq 16(%rsp), %r13
movq %r14, %rdi
movq %r15, %rsi
movq %r12, %rdx
movq %r13, %rcx
callq __hipPopCallConfiguration
movq (%r14), %rsi
movl 8(%r14), %edx
movq (%r15), %rcx
movl 8(%r15), %r8d
movl $_Z13meanFilterGPUPhS_iisi, %edi
movq %rbx, %r9
pushq (%r13)
.cfi_adjust_cfa_offset 8
pushq (%r12)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $144, %rsp
.cfi_adjust_cfa_offset -144
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z28__device_stub__meanFilterGPUPhS_iisi, .Lfunc_end1-_Z28__device_stub__meanFilterGPUPhS_iisi
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $72, %rsp
.cfi_def_cfa_offset 128
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsi, %rbx
movl $54, %edi
callq malloc
movq %rax, %r14
movq 8(%rbx), %rdi
movl $.L.str, %esi
callq fopen
movq %rax, %r15
movq 16(%rbx), %rdi
callq atoi
movl %eax, %ebp
movl $1, %esi
movl $54, %edx
movq %r14, %rdi
movq %r15, %rcx
callq fread
movl 18(%r14), %esi
movl 22(%r14), %r12d
movswl 28(%r14), %eax
movq %r14, 64(%rsp) # 8-byte Spill
movslq 10(%r14), %rbx
movl %eax, %r14d
cmpl $8, %eax
movl %ebp, 12(%rsp) # 4-byte Spill
jne .LBB2_2
# %bb.1:
movl %r12d, %ebp
imull %esi, %ebp
jmp .LBB2_4
.LBB2_2:
# implicit-def: $ebp
cmpw $24, %r14w
jne .LBB2_4
# %bb.3:
movl %r12d, %eax
imull %esi, %eax
leal (%rax,%rax,2), %ebp
.LBB2_4:
movl $.L.str.1, %edi
xorl %eax, %eax
movq %rsi, 16(%rsp) # 8-byte Spill
callq printf
movl $.L.str.2, %edi
movl %r12d, %esi
xorl %eax, %eax
callq printf
movl $.L.str.3, %edi
movl %r14d, %esi
xorl %eax, %eax
callq printf
movl $.L.str.4, %edi
movl %ebp, %esi
xorl %eax, %eax
callq printf
movl $.L.str.5, %edi
movl %ebx, %esi
xorl %eax, %eax
callq printf
addq $-54, %rbx
movq %rbx, %rdi
callq malloc
movl $1, %esi
movq %rax, 48(%rsp) # 8-byte Spill
movq %rax, %rdi
movq %rbx, %rdx
movq %r15, %rcx
callq fread
movl %ebp, 8(%rsp) # 4-byte Spill
movslq %ebp, %rbx
movq %rbx, %rdi
callq malloc
movq %r12, 40(%rsp) # 8-byte Spill
movq %rax, %r12
movl $1, %esi
movq %rax, %rdi
movq %rbx, %rdx
movq %r15, 56(%rsp) # 8-byte Spill
movq %r15, %rcx
callq fread
movq %rbx, %rdi
callq malloc
movq %rax, %r13
movq %rbx, %rdi
callq malloc
movq %rax, %r15
leaq 32(%rsp), %rbp
movq %rbp, %rdi
movq %rbx, %rsi
callq hipMalloc
leaq 24(%rsp), %rdi
movq %rbx, %rsi
callq hipMalloc
movq (%rbp), %rdi
movq %r12, %rsi
movq %rbx, %rdx
movl $1, %ecx
callq hipMemcpy
movq %r12, %rdi
movq %r13, %rsi
movq 16(%rsp), %rdx # 8-byte Reload
# kill: def $edx killed $edx killed $rdx
movq 40(%rsp), %rbp # 8-byte Reload
movl %ebp, %ecx
movl %r14d, %r8d
movl 12(%rsp), %r9d # 4-byte Reload
callq _Z13meanFilterCPUPhS_iisi
movq 16(%rsp), %rcx # 8-byte Reload
leal 31(%rcx), %eax
testl %ecx, %ecx
cmovnsl %ecx, %eax
sarl $5, %eax
leal 31(%rbp), %edi
testl %ebp, %ebp
cmovnsl %ebp, %edi
sarl $5, %edi
shlq $32, %rdi
orq %rax, %rdi
movabsq $137438953504, %rdx # imm = 0x2000000020
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_6
# %bb.5:
movq 32(%rsp), %rdi
movq 24(%rsp), %rsi
movq 16(%rsp), %rdx # 8-byte Reload
# kill: def $edx killed $edx killed $rdx
movl %ebp, %ecx
movl %r14d, %r8d
movl 12(%rsp), %r9d # 4-byte Reload
callq _Z28__device_stub__meanFilterGPUPhS_iisi
.LBB2_6:
movq 24(%rsp), %rsi
movq %r15, %rdi
movq %rbx, %rdx
movl $2, %ecx
callq hipMemcpy
cmpw $8, %r14w
jne .LBB2_10
# %bb.7: # %.preheader
cmpl $0, 8(%rsp) # 4-byte Folded Reload
je .LBB2_14
# %bb.8: # %.lr.ph108.preheader
xorl %r14d, %r14d
.LBB2_9: # %.lr.ph108
# =>This Inner Loop Header: Depth=1
movzbl (%r12,%r14), %edx
movzbl (%r13,%r14), %ecx
movzbl (%r15,%r14), %r8d
movl $.L.str.6, %edi
movq %r14, %rsi
xorl %eax, %eax
callq printf
incq %r14
cmpq %r14, %rbx
jne .LBB2_9
jmp .LBB2_14
.LBB2_10:
cmpw $24, %r14w
movl 8(%rsp), %ebp # 4-byte Reload
jne .LBB2_14
# %bb.11:
testl %ebp, %ebp
jle .LBB2_14
# %bb.12: # %.lr.ph.preheader
xorl %ebx, %ebx
.LBB2_13: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movzbl (%r12,%rbx), %eax
shll $16, %eax
movzbl 1(%r12,%rbx), %ecx
shll $8, %ecx
orl %eax, %ecx
movzbl 2(%r12,%rbx), %edx
orl %ecx, %edx
movzbl (%r13,%rbx), %eax
shll $16, %eax
movzbl 1(%r13,%rbx), %esi
shll $8, %esi
orl %eax, %esi
movzbl 2(%r13,%rbx), %ecx
orl %esi, %ecx
movzbl (%r15,%rbx), %eax
shll $16, %eax
movzbl 1(%r15,%rbx), %esi
shll $8, %esi
orl %eax, %esi
movzbl 2(%r15,%rbx), %r8d
orl %esi, %r8d
movl $.L.str.6, %edi
movl %ebx, %esi
xorl %eax, %eax
callq printf
addq $3, %rbx
cmpl %ebx, %ebp
jg .LBB2_13
.LBB2_14: # %.loopexit
movq 56(%rsp), %rdi # 8-byte Reload
callq fclose
movq %r12, %rdi
callq free
movq 48(%rsp), %rdi # 8-byte Reload
callq free
movq 64(%rsp), %rdi # 8-byte Reload
callq free
movq %r13, %rdi
callq free
movq %r15, %rdi
callq free
movq 32(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $72, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, %rdi
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13meanFilterGPUPhS_iisi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z13meanFilterGPUPhS_iisi,@object # @_Z13meanFilterGPUPhS_iisi
.section .rodata,"a",@progbits
.globl _Z13meanFilterGPUPhS_iisi
.p2align 3, 0x0
_Z13meanFilterGPUPhS_iisi:
.quad _Z28__device_stub__meanFilterGPUPhS_iisi
.size _Z13meanFilterGPUPhS_iisi, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "rb"
.size .L.str, 3
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "imgWidtht : %d\n"
.size .L.str.1, 16
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "imgHeight : %d\n"
.size .L.str.2, 16
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "bitsPerPixel : %d\n"
.size .L.str.3, 19
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "image size : %d\n"
.size .L.str.4, 17
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "offset : %d\n"
.size .L.str.5, 13
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "%d pixelBeforeFilter:%d cpuFilteredPixel:%d gpuFilteredPixel:%d\n"
.size .L.str.6, 68
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z13meanFilterGPUPhS_iisi"
.size .L__unnamed_1, 26
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z28__device_stub__meanFilterGPUPhS_iisi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z13meanFilterGPUPhS_iisi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
```
| 7,337 | 8,763 |
372 |
Convert the following CUDA device assembly code to AMD device assembly:
```cudaasm
code for sm_80
Function : _Z8ReducePIPfi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ;
S2R R0, SR_TID.X ;
BSSY B0, 0x370 ;
S2R R11, SR_CTAID.X ;
STS [R0.X4], RZ ;
IMAD R10, R11, c[0x0][0x0], R0 ;
ISETP.GE.AND P0, PT, R10, c[0x0][0x168], PT ;
@P0 BRA 0x360 ;
IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x0] ;
IMAD R2, R2, c[0x0][0xc], RZ ;
ISETP.GE.AND P0, PT, R2, c[0x0][0x168], PT ;
@!P0 BRA 0x4e0 ;
I2F.F64 R4, c[0x0][0x168] ;
IMAD.MOV.U32 R2, RZ, RZ, 0x1 ;
BSSY B1, 0x230 ;
MUFU.RCP64H R3, R5 ;
DFMA R6, -R4, R2, 1 ;
DFMA R8, R6, R6, R6 ;
I2F.F64 R6, R10 ;
DFMA R8, R2, R8, R2 ;
DFMA R2, -R4, R8, 1 ;
DFMA R2, R8, R2, R8 ;
DADD R6, R6, 0.5 ;
DMUL R8, R6, R2 ;
FSETP.GEU.AND P1, PT, |R7|, 6.5827683646048100446e-37, PT ;
DFMA R12, -R4, R8, R6 ;
DFMA R2, R2, R12, R8 ;
FFMA R8, RZ, R5, R3 ;
FSETP.GT.AND P0, PT, |R8|, 1.469367938527859385e-39, PT ;
@P0 BRA P1, 0x220 ;
MOV R10, 0x200 ;
CALL.REL.NOINC 0x4f0 ;
IMAD.MOV.U32 R2, RZ, RZ, R12 ;
IMAD.MOV.U32 R3, RZ, RZ, R13 ;
BSYNC B1 ;
F2F.F32.F64 R2, R2 ;
UMOV UR4, 0x40800000 ;
BSSY B2, 0x340 ;
IMAD.U32 R8, RZ, RZ, UR4 ;
FFMA R7, R2, R2, 1 ;
MUFU.RCP R4, R7 ;
FCHK P0, R8, R7 ;
FFMA R5, -R7, R4, 1 ;
FFMA R5, R4, R5, R4 ;
FFMA R4, R5, 4, RZ ;
FFMA R6, -R7, R4, 4 ;
FFMA R4, R5, R6, R4 ;
@!P0 BRA 0x330 ;
MOV R2, 0x320 ;
CALL.REL.NOINC 0xab0 ;
IMAD.MOV.U32 R4, RZ, RZ, R5 ;
BSYNC B2 ;
FADD R3, RZ, R4 ;
STS [R0.X4], R3 ;
BSYNC B0 ;
SHF.R.U32.HI R2, RZ, 0x1, R11 ;
ISETP.NE.AND P1, PT, R0, RZ, PT ;
ISETP.NE.AND P0, PT, R2, RZ, PT ;
@!P0 BRA 0x470 ;
IMAD.IADD R3, R2, 0x1, R0 ;
IMAD.SHL.U32 R3, R3, 0x4, RZ ;
ISETP.GE.U32.AND P0, PT, R0, R2, PT ;
WARPSYNC 0xffffffff ;
IADD3 R2, R2, 0x1, RZ ;
@!P0 LDS R4, [R0.X4] ;
@!P0 LDS R5, [R3] ;
IADD3 R3, R3, 0x4, RZ ;
@!P0 FADD R5, R4, R5 ;
@!P0 STS [R0.X4], R5 ;
BAR.SYNC.DEFER_BLOCKING 0x0 ;
BRA 0x3d0 ;
@P1 EXIT ;
LDS R5, [RZ] ;
IMAD.MOV.U32 R2, RZ, RZ, 0x4 ;
ULDC.64 UR4, c[0x0][0x118] ;
IMAD.WIDE.U32 R2, R11, R2, c[0x0][0x160] ;
STG.E [R2.64], R5 ;
EXIT ;
BRA 0x4e0 ;
FSETP.GEU.AND P0, PT, |R5|.reuse, 1.469367938527859385e-39, PT ;
IMAD.MOV.U32 R13, RZ, RZ, 0x1ca00000 ;
LOP3.LUT R2, R5, 0x800fffff, RZ, 0xc0, !PT ;
IMAD.MOV.U32 R14, RZ, RZ, 0x1 ;
FSETP.GEU.AND P2, PT, |R7|.reuse, 1.469367938527859385e-39, PT ;
IMAD.MOV.U32 R8, RZ, RZ, R6 ;
LOP3.LUT R3, R2, 0x3ff00000, RZ, 0xfc, !PT ;
IMAD.MOV.U32 R2, RZ, RZ, R4 ;
LOP3.LUT R12, R7, 0x7ff00000, RZ, 0xc0, !PT ;
BSSY B2, 0xa80 ;
LOP3.LUT R17, R5, 0x7ff00000, RZ, 0xc0, !PT ;
@!P0 DMUL R2, R4, 8.98846567431157953865e+307 ;
ISETP.GE.U32.AND P1, PT, R12.reuse, R17, PT ;
IMAD.MOV.U32 R16, RZ, RZ, R12 ;
@!P2 LOP3.LUT R9, R5, 0x7ff00000, RZ, 0xc0, !PT ;
@!P2 IMAD.MOV.U32 R20, RZ, RZ, RZ ;
MUFU.RCP64H R15, R3 ;
@!P2 ISETP.GE.U32.AND P3, PT, R12, R9, PT ;
SEL R9, R13, 0x63400000, !P1 ;
@!P2 SEL R21, R13, 0x63400000, !P3 ;
LOP3.LUT R9, R9, 0x800fffff, R7.reuse, 0xf8, !PT ;
@!P2 LOP3.LUT R21, R21, 0x80000000, R7, 0xf8, !PT ;
@!P0 LOP3.LUT R17, R3, 0x7ff00000, RZ, 0xc0, !PT ;
@!P2 LOP3.LUT R21, R21, 0x100000, RZ, 0xfc, !PT ;
DFMA R18, R14, -R2, 1 ;
IADD3 R22, R17, -0x1, RZ ;
@!P2 DFMA R8, R8, 2, -R20 ;
DFMA R18, R18, R18, R18 ;
DFMA R14, R14, R18, R14 ;
@!P2 LOP3.LUT R16, R9, 0x7ff00000, RZ, 0xc0, !PT ;
IADD3 R20, R16, -0x1, RZ ;
DFMA R18, R14, -R2, 1 ;
ISETP.GT.U32.AND P0, PT, R20, 0x7feffffe, PT ;
DFMA R14, R14, R18, R14 ;
ISETP.GT.U32.OR P0, PT, R22, 0x7feffffe, P0 ;
DMUL R18, R14, R8 ;
DFMA R20, R18, -R2, R8 ;
DFMA R14, R14, R20, R18 ;
@P0 BRA 0x920 ;
LOP3.LUT R7, R5, 0x7ff00000, RZ, 0xc0, !PT ;
ISETP.GE.U32.AND P0, PT, R12.reuse, R7, PT ;
IMAD.IADD R6, R12, 0x1, -R7 ;
SEL R13, R13, 0x63400000, !P0 ;
IMNMX R6, R6, -0x46a00000, !PT ;
IMNMX R6, R6, 0x46a00000, PT ;
IMAD.IADD R16, R6, 0x1, -R13 ;
IMAD.MOV.U32 R6, RZ, RZ, RZ ;
IADD3 R7, R16, 0x7fe00000, RZ ;
DMUL R12, R14, R6 ;
FSETP.GTU.AND P0, PT, |R13|, 1.469367938527859385e-39, PT ;
@P0 BRA 0xa70 ;
DFMA R2, R14, -R2, R8 ;
IMAD.MOV.U32 R6, RZ, RZ, RZ ;
FSETP.NEU.AND P0, PT, R3.reuse, RZ, PT ;
LOP3.LUT R5, R3, 0x80000000, R5, 0x48, !PT ;
LOP3.LUT R7, R5, R7, RZ, 0xfc, !PT ;
@!P0 BRA 0xa70 ;
IMAD.MOV R3, RZ, RZ, -R16 ;
DMUL.RP R6, R14, R6 ;
IMAD.MOV.U32 R2, RZ, RZ, RZ ;
DFMA R2, R12, -R2, R14 ;
LOP3.LUT R5, R7, R5, RZ, 0x3c, !PT ;
IADD3 R2, -R16, -0x43300000, RZ ;
FSETP.NEU.AND P0, PT, |R3|, R2, PT ;
FSEL R12, R6, R12, !P0 ;
FSEL R13, R5, R13, !P0 ;
BRA 0xa70 ;
DSETP.NAN.AND P0, PT, R6, R6, PT ;
@P0 BRA 0xa50 ;
DSETP.NAN.AND P0, PT, R4, R4, PT ;
@P0 BRA 0xa20 ;
ISETP.NE.AND P0, PT, R16, R17, PT ;
IMAD.MOV.U32 R12, RZ, RZ, 0x0 ;
IMAD.MOV.U32 R13, RZ, RZ, -0x80000 ;
@!P0 BRA 0xa70 ;
ISETP.NE.AND P0, PT, R16, 0x7ff00000, PT ;
LOP3.LUT R13, R7, 0x80000000, R5, 0x48, !PT ;
ISETP.EQ.OR P0, PT, R17, RZ, !P0 ;
@P0 LOP3.LUT R2, R13, 0x7ff00000, RZ, 0xfc, !PT ;
@!P0 IMAD.MOV.U32 R12, RZ, RZ, RZ ;
@P0 IMAD.MOV.U32 R12, RZ, RZ, RZ ;
@P0 IMAD.MOV.U32 R13, RZ, RZ, R2 ;
BRA 0xa70 ;
LOP3.LUT R13, R5, 0x80000, RZ, 0xfc, !PT ;
IMAD.MOV.U32 R12, RZ, RZ, R4 ;
BRA 0xa70 ;
LOP3.LUT R13, R7, 0x80000, RZ, 0xfc, !PT ;
IMAD.MOV.U32 R12, RZ, RZ, R6 ;
BSYNC B2 ;
IMAD.MOV.U32 R2, RZ, RZ, R10 ;
IMAD.MOV.U32 R3, RZ, RZ, 0x0 ;
RET.REL.NODEC R2 0x0 ;
SHF.R.U32.HI R3, RZ, 0x17, R7.reuse ;
BSSY B1, 0x10a0 ;
BSSY B3, 0xc90 ;
IMAD.MOV.U32 R5, RZ, RZ, R7 ;
LOP3.LUT R9, R3, 0xff, RZ, 0xc0, !PT ;
IADD3 R6, R9, -0x1, RZ ;
ISETP.GT.U32.AND P0, PT, R6, 0xfd, PT ;
@!P0 IMAD.MOV.U32 R4, RZ, RZ, RZ ;
@!P0 BRA 0xc80 ;
FSETP.GTU.FTZ.AND P0, PT, |R7|, +INF , PT ;
IMAD.MOV.U32 R3, RZ, RZ, R7 ;
@P0 BREAK B3 ;
@P0 BRA 0x1080 ;
IMAD.MOV.U32 R4, RZ, RZ, 0x40800000 ;
LOP3.LUT P0, RZ, R5, 0x7fffffff, R4, 0xc8, !PT ;
@!P0 BREAK B3 ;
@!P0 BRA 0x1060 ;
FSETP.NEU.FTZ.AND P0, PT, |R3|, +INF , PT ;
LOP3.LUT P1, RZ, R4, 0x7fffffff, RZ, 0xc0, !PT ;
PLOP3.LUT P0, PT, P0, P1, PT, 0x2a, 0x0 ;
@P0 BREAK B3 ;
@P0 BRA 0x1040 ;
LOP3.LUT P0, RZ, R5, 0x7fffffff, RZ, 0xc0, !PT ;
@!P0 BREAK B3 ;
@!P0 BRA 0x1010 ;
ISETP.GE.AND P0, PT, R6, RZ, PT ;
IMAD.MOV.U32 R4, RZ, RZ, RZ ;
@!P0 FFMA R5, R3, 1.84467440737095516160e+19, RZ ;
@!P0 IADD3 R4, R4, 0x40, RZ ;
BSYNC B3 ;
LEA R6, R9, 0xc0800000, 0x17 ;
UMOV UR4, 0x40800000 ;
IADD3 R4, R4, 0x81, -R9 ;
UIADD3 UR4, UR4, -0x1000000, URZ ;
BSSY B3, 0x1000 ;
IMAD.IADD R6, R5, 0x1, -R6 ;
MUFU.RCP R3, R6 ;
FADD.FTZ R8, -R6, -RZ ;
FFMA R10, R3, R8, 1 ;
FFMA R7, R3, R10, R3 ;
FFMA R3, R7, UR4, RZ ;
FFMA R10, R8, R3, UR4 ;
FFMA R10, R7, R10, R3 ;
FFMA R8, R8, R10, UR4 ;
FFMA R5, R7, R8, R10 ;
SHF.R.U32.HI R3, RZ, 0x17, R5 ;
LOP3.LUT R3, R3, 0xff, RZ, 0xc0, !PT ;
IMAD.IADD R9, R3, 0x1, R4 ;
IADD3 R3, R9, -0x1, RZ ;
ISETP.GE.U32.AND P0, PT, R3, 0xfe, PT ;
@!P0 BRA 0xfe0 ;
ISETP.GT.AND P0, PT, R9, 0xfe, PT ;
@P0 BRA 0xfb0 ;
ISETP.GE.AND P0, PT, R9, 0x1, PT ;
@P0 BRA 0xff0 ;
ISETP.GE.AND P0, PT, R9, -0x18, PT ;
LOP3.LUT R5, R5, 0x80000000, RZ, 0xc0, !PT ;
@!P0 BRA 0xff0 ;
FFMA.RZ R3, R7, R8.reuse, R10.reuse ;
ISETP.NE.AND P2, PT, R9, RZ, PT ;
FFMA.RM R4, R7, R8.reuse, R10.reuse ;
ISETP.NE.AND P1, PT, R9, RZ, PT ;
LOP3.LUT R6, R3, 0x7fffff, RZ, 0xc0, !PT ;
FFMA.RP R3, R7, R8, R10 ;
IADD3 R7, R9, 0x20, RZ ;
IMAD.MOV R8, RZ, RZ, -R9 ;
LOP3.LUT R6, R6, 0x800000, RZ, 0xfc, !PT ;
FSETP.NEU.FTZ.AND P0, PT, R3, R4, PT ;
SHF.L.U32 R7, R6, R7, RZ ;
SEL R3, R8, RZ, P2 ;
ISETP.NE.AND P1, PT, R7, RZ, P1 ;
SHF.R.U32.HI R3, RZ, R3, R6 ;
PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ;
SHF.R.U32.HI R7, RZ, 0x1, R3 ;
SEL R4, RZ, 0x1, !P0 ;
LOP3.LUT R4, R4, 0x1, R7, 0xf8, !PT ;
LOP3.LUT R4, R4, R3, RZ, 0xc0, !PT ;
IMAD.IADD R4, R7, 0x1, R4 ;
LOP3.LUT R5, R4, R5, RZ, 0xfc, !PT ;
BRA 0xff0 ;
LOP3.LUT R5, R5, 0x80000000, RZ, 0xc0, !PT ;
LOP3.LUT R5, R5, 0x7f800000, RZ, 0xfc, !PT ;
BRA 0xff0 ;
IMAD R5, R4, 0x800000, R5 ;
BSYNC B3 ;
BRA 0x1090 ;
LOP3.LUT R5, R5, 0x80000000, R4, 0x48, !PT ;
LOP3.LUT R5, R5, 0x7f800000, RZ, 0xfc, !PT ;
BRA 0x1090 ;
LOP3.LUT R5, R5, 0x80000000, R4, 0x48, !PT ;
BRA 0x1090 ;
MUFU.RSQ R5, -QNAN ;
BRA 0x1090 ;
FADD.FTZ R5, R3, 4 ;
BSYNC B1 ;
IMAD.MOV.U32 R3, RZ, RZ, 0x0 ;
RET.REL.NODEC R2 0x0 ;
BRA 0x10c0;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
```
|
```amdasm
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z8ReducePIPfi ; -- Begin function _Z8ReducePIPfi
.globl _Z8ReducePIPfi
.p2align 8
.type _Z8ReducePIPfi,@function
_Z8ReducePIPfi: ; @_Z8ReducePIPfi
; %bb.0:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x1c
s_load_b32 s6, s[0:1], 0x8
s_add_u32 s4, s0, 16
s_mov_b32 s2, s15
s_addc_u32 s5, s1, 0
v_mov_b32_e32 v5, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s7, s3, 0xffff
s_mov_b32 s3, exec_lo
v_mad_u64_u32 v[3:4], null, s2, s7, v[0:1]
v_lshl_add_u32 v4, v0, 2, 0
ds_store_b32 v4, v5
v_cmpx_gt_i32_e64 s6, v3
s_cbranch_execz .LBB0_4
; %bb.1: ; %.lr.ph
v_cvt_f64_i32_e32 v[1:2], s6
s_load_b32 s4, s[4:5], 0x0
s_waitcnt lgkmcnt(0)
s_mul_i32 s4, s4, s7
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_ge_i32 s4, s6
s_cselect_b32 s5, -1, 0
.LBB0_2: ; =>This Inner Loop Header: Depth=1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_f64_i32_e32 v[6:7], v3
v_add_f64 v[6:7], v[6:7], 0.5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_div_scale_f64 v[8:9], null, v[1:2], v[1:2], v[6:7]
v_div_scale_f64 v[14:15], vcc_lo, v[6:7], v[1:2], v[6:7]
v_rcp_f64_e32 v[10:11], v[8:9]
s_waitcnt_depctr 0xfff
v_fma_f64 v[12:13], -v[8:9], v[10:11], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[10:11], v[10:11], v[12:13], v[10:11]
v_fma_f64 v[12:13], -v[8:9], v[10:11], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[10:11], v[10:11], v[12:13], v[10:11]
v_mul_f64 v[12:13], v[14:15], v[10:11]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[8:9], -v[8:9], v[12:13], v[14:15]
v_div_fmas_f64 v[8:9], v[8:9], v[10:11], v[12:13]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fixup_f64 v[6:7], v[8:9], v[1:2], v[6:7]
v_cvt_f32_f64_e32 v3, v[6:7]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v3, v3, v3, 1.0
v_div_scale_f32 v6, null, v3, v3, 4.0
v_div_scale_f32 v9, vcc_lo, 4.0, v3, 4.0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f32_e32 v7, v6
s_waitcnt_depctr 0xfff
v_fma_f32 v8, -v6, v7, 1.0
v_fmac_f32_e32 v7, v8, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v8, v9, v7
v_fma_f32 v10, -v6, v8, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v8, v10, v7
v_fma_f32 v6, -v6, v8, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_div_fmas_f32 v6, v6, v7, v8
s_and_not1_b32 vcc_lo, exec_lo, s5
v_div_fixup_f32 v6, v6, v3, 4.0
v_mov_b32_e32 v3, s4
s_delay_alu instid0(VALU_DEP_2)
v_add_f32_e32 v5, v6, v5
s_cbranch_vccnz .LBB0_2
; %bb.3: ; %._crit_edge
ds_store_b32 v4, v5
.LBB0_4: ; %Flow29
s_or_b32 exec_lo, exec_lo, s3
s_cmp_lt_u32 s2, 2
s_mov_b32 s3, -1
s_cbranch_scc1 .LBB0_12
; %bb.5: ; %.lr.ph18.preheader
v_lshlrev_b32_e32 v1, 2, v0
s_lshr_b32 s3, s2, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_lshl_b32 s4, s3, 2
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_add3_u32 v1, 0, s4, v1
s_mov_b32 s4, 0
.LBB0_6: ; %.lr.ph18
; =>This Inner Loop Header: Depth=1
v_cmp_le_u32_e64 s5, s3, v0
s_mov_b32 s6, exec_lo
v_cmpx_gt_u32_e64 s3, v0
s_cbranch_execz .LBB0_8
; %bb.7: ; in Loop: Header=BB0_6 Depth=1
ds_load_b32 v2, v1
ds_load_b32 v3, v4
s_or_b32 s5, s5, exec_lo
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v2, v2, v3
ds_store_b32 v4, v2
.LBB0_8: ; %Flow
; in Loop: Header=BB0_6 Depth=1
s_or_b32 exec_lo, exec_lo, s6
s_mov_b32 s7, -1
s_and_saveexec_b32 s6, s5
s_cbranch_execz .LBB0_10
; %bb.9: ; in Loop: Header=BB0_6 Depth=1
v_add_nc_u32_e32 v1, 4, v1
s_add_i32 s3, s3, 1
s_xor_b32 s7, exec_lo, -1
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
.LBB0_10: ; %Flow24
; in Loop: Header=BB0_6 Depth=1
s_or_b32 exec_lo, exec_lo, s6
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s5, exec_lo, s7
s_or_b32 s4, s5, s4
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s4
s_cbranch_execnz .LBB0_6
; %bb.11: ; %Flow25
s_or_b32 exec_lo, exec_lo, s4
s_mov_b32 s3, 0
.LBB0_12: ; %Flow27
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 vcc_lo, exec_lo, s3
s_cbranch_vccz .LBB0_15
; %bb.13: ; %._crit_edge19
s_mov_b32 s3, 0
s_mov_b32 s4, exec_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB0_15
; %bb.14:
v_mov_b32_e32 v0, 0
s_load_b64 s[0:1], s[0:1], 0x0
s_lshl_b64 s[2:3], s[2:3], 2
ds_load_b32 v1, v0
s_waitcnt lgkmcnt(0)
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
global_store_b32 v0, v1, s[0:1]
.LBB0_15: ; %UnifiedReturnBlock
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z8ReducePIPfi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 16
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z8ReducePIPfi, .Lfunc_end0-_Z8ReducePIPfi
; -- End function
.section .AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 652
; NumSgprs: 18
; NumVgprs: 16
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 16
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object ; @__hip_cuid_
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0 ; 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
- .offset: 136
.size: 4
.value_kind: hidden_dynamic_lds_size
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z8ReducePIPfi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z8ReducePIPfi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 16
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
```
| 5,281 | 4,464 |
373 |
Convert the following CUDA host assembly code to AMD host assembly:
```cudaasm
.file "tmpxft_000ceddb_00000000-6_ReducePI.cudafe1.cpp"
.text
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z28__device_stub__Z8ReducePIPfiPfi
.type _Z28__device_stub__Z8ReducePIPfiPfi, @function
_Z28__device_stub__Z8ReducePIPfiPfi:
.LFB2051:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z8ReducePIPfi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z28__device_stub__Z8ReducePIPfiPfi, .-_Z28__device_stub__Z8ReducePIPfiPfi
.globl _Z8ReducePIPfi
.type _Z8ReducePIPfi, @function
_Z8ReducePIPfi:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z28__device_stub__Z8ReducePIPfiPfi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z8ReducePIPfi, .-_Z8ReducePIPfi
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z8ReducePIPfi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z8ReducePIPfi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
```
|
```amdasm
.text
.file "ReducePI.hip"
.globl _Z23__device_stub__ReducePIPfi # -- Begin function _Z23__device_stub__ReducePIPfi
.type _Z23__device_stub__ReducePIPfi,@function
_Z23__device_stub__ReducePIPfi: # @_Z23__device_stub__ReducePIPfi
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $80, %rsp
.cfi_def_cfa_offset 128
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 24(%rsp), %rax
movq %rdi, (%rax)
leaq 4(%rsp), %rcx
movl %esi, (%rcx)
leaq 64(%rsp), %rbx
movq %rax, (%rbx)
movq %rcx, 8(%rbx)
leaq 48(%rsp), %r14
leaq 32(%rsp), %r15
leaq 16(%rsp), %r12
leaq 8(%rsp), %r13
movq %r14, %rdi
movq %r15, %rsi
movq %r12, %rdx
movq %r13, %rcx
callq __hipPopCallConfiguration
movq (%r14), %rsi
movl 8(%r14), %edx
movq (%r15), %rcx
movl 8(%r15), %r8d
movl $_Z8ReducePIPfi, %edi
movq %rbx, %r9
pushq (%r13)
.cfi_adjust_cfa_offset 8
pushq (%r12)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $96, %rsp
.cfi_adjust_cfa_offset -96
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z23__device_stub__ReducePIPfi, .Lfunc_end0-_Z23__device_stub__ReducePIPfi
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, %rdi
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8ReducePIPfi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z8ReducePIPfi,@object # @_Z8ReducePIPfi
.section .rodata,"a",@progbits
.globl _Z8ReducePIPfi
.p2align 3, 0x0
_Z8ReducePIPfi:
.quad _Z23__device_stub__ReducePIPfi
.size _Z8ReducePIPfi, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z8ReducePIPfi"
.size .L__unnamed_1, 15
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z23__device_stub__ReducePIPfi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z8ReducePIPfi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
```
| 1,736 | 1,924 |
378 |
Convert the following CUDA device assembly code to AMD device assembly:
```cudaasm
code for sm_80
Function : _Z11CrashKernelPdiii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
MOV R1, c[0x0][0x28] ;
S2R R0, SR_TID.X ;
S2R R3, SR_CTAID.X ;
S2R R2, SR_CTAID.Y ;
S2R R5, SR_TID.Y ;
IMAD R0, R3, c[0x0][0x0], R0 ;
ISETP.GE.AND P0, PT, R0, c[0x0][0x16c], PT ;
IMAD R3, R2, c[0x0][0x4], R5 ;
ISETP.GE.OR P0, PT, R3, c[0x0][0x168], P0 ;
@P0 EXIT ;
HFMA2.MMA R2, -RZ, RZ, 0, 4.76837158203125e-07 ;
IMAD R3, R3, c[0x0][0x16c], R0 ;
ULDC.64 UR4, c[0x0][0x118] ;
IMAD.WIDE R2, R3, R2, c[0x0][0x160] ;
LDG.E.64 R4, [R2.64] ;
DSETP.GEU.AND P0, PT, R4, RZ, PT ;
@P0 STG.E.64 [R2.64], RZ ;
@P0 EXIT ;
MOV R4, 0x0 ;
MOV R5, 0x3ff00000 ;
STG.E.64 [R2.64], R4 ;
EXIT ;
BRA 0x160;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
```
|
```amdasm
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z11CrashKernelPdiii ; -- Begin function _Z11CrashKernelPdiii
.globl _Z11CrashKernelPdiii
.p2align 8
.type _Z11CrashKernelPdiii,@function
_Z11CrashKernelPdiii: ; @_Z11CrashKernelPdiii
; %bb.0:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x24
s_load_b64 s[2:3], s[0:1], 0x8
v_bfe_u32 v2, v0, 10, 10
v_and_b32_e32 v3, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s5, s4, 16
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[0:1], null, s15, s5, v[2:3]
v_mad_u64_u32 v[1:2], null, s14, s4, v[3:4]
v_cmp_gt_i32_e32 vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_i32_e64 s2, s3, v1
s_and_b32 s2, s2, vcc_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s4, s2
s_cbranch_execz .LBB0_2
; %bb.1: ; %.sink.split
s_load_b64 s[0:1], s[0:1], 0x0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, v0, s3, v[1:2]
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 3, v[2:3]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_load_b64 v[2:3], v[0:1], off
s_waitcnt vmcnt(0)
v_cmp_gt_f64_e32 vcc_lo, 0, v[2:3]
v_mov_b32_e32 v2, 0
v_cndmask_b32_e64 v3, 0, 0x3ff00000, vcc_lo
global_store_b64 v[0:1], v[2:3], off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11CrashKernelPdiii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z11CrashKernelPdiii, .Lfunc_end0-_Z11CrashKernelPdiii
; -- End function
.section .AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 212
; NumSgprs: 18
; NumVgprs: 5
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 5
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object ; @__hip_cuid_
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0 ; 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11CrashKernelPdiii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z11CrashKernelPdiii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
```
| 476 | 2,730 |
379 |
Convert the following CUDA host assembly code to AMD host assembly:
```cudaasm
.file "tmpxft_000651f2_00000000-6_CrashKernel.cudafe1.cpp"
.text
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z34__device_stub__Z11CrashKernelPdiiiPdiii
.type _Z34__device_stub__Z11CrashKernelPdiiiPdiii, @function
_Z34__device_stub__Z11CrashKernelPdiiiPdiii:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movl %esi, 20(%rsp)
movl %edx, 16(%rsp)
movl %ecx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 12(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z11CrashKernelPdiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z34__device_stub__Z11CrashKernelPdiiiPdiii, .-_Z34__device_stub__Z11CrashKernelPdiiiPdiii
.globl _Z11CrashKernelPdiii
.type _Z11CrashKernelPdiii, @function
_Z11CrashKernelPdiii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z34__device_stub__Z11CrashKernelPdiiiPdiii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z11CrashKernelPdiii, .-_Z11CrashKernelPdiii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z11CrashKernelPdiii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z11CrashKernelPdiii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
```
|
```amdasm
.text
.file "CrashKernel.hip"
.globl _Z26__device_stub__CrashKernelPdiii # -- Begin function _Z26__device_stub__CrashKernelPdiii
.type _Z26__device_stub__CrashKernelPdiii,@function
_Z26__device_stub__CrashKernelPdiii: # @_Z26__device_stub__CrashKernelPdiii
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $112, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 40(%rsp), %rax
movq %rdi, (%rax)
leaq 20(%rsp), %rdi
movl %esi, (%rdi)
leaq 16(%rsp), %rsi
movl %edx, (%rsi)
leaq 12(%rsp), %rdx
movl %ecx, (%rdx)
leaq 80(%rsp), %rbx
movq %rax, (%rbx)
movq %rdi, 8(%rbx)
movq %rsi, 16(%rbx)
movq %rdx, 24(%rbx)
leaq 64(%rsp), %r14
leaq 48(%rsp), %r15
leaq 32(%rsp), %r12
leaq 24(%rsp), %r13
movq %r14, %rdi
movq %r15, %rsi
movq %r12, %rdx
movq %r13, %rcx
callq __hipPopCallConfiguration
movq (%r14), %rsi
movl 8(%r14), %edx
movq (%r15), %rcx
movl 8(%r15), %r8d
movl $_Z11CrashKernelPdiii, %edi
movq %rbx, %r9
pushq (%r13)
.cfi_adjust_cfa_offset 8
pushq (%r12)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $128, %rsp
.cfi_adjust_cfa_offset -128
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z26__device_stub__CrashKernelPdiii, .Lfunc_end0-_Z26__device_stub__CrashKernelPdiii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, %rdi
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11CrashKernelPdiii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z11CrashKernelPdiii,@object # @_Z11CrashKernelPdiii
.section .rodata,"a",@progbits
.globl _Z11CrashKernelPdiii
.p2align 3, 0x0
_Z11CrashKernelPdiii:
.quad _Z26__device_stub__CrashKernelPdiii
.size _Z11CrashKernelPdiii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z11CrashKernelPdiii"
.size .L__unnamed_1, 21
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z26__device_stub__CrashKernelPdiii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z11CrashKernelPdiii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
```
| 1,882 | 2,066 |
380 |
Convert the following CUDA device assembly code to AMD device assembly:
```cudaasm
code for sm_80
```
|
```amdasm
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object ; @__hip_cuid_
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0 ; 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
```
| 24 | 306 |
381 |
Convert the following CUDA host assembly code to AMD host assembly:
```cudaasm
.file "tmpxft_0016dbfb_00000000-6_cuda.cudafe1.cpp"
.text
.globl _ZSt21ios_base_library_initv
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "Failed to retrieve the number of CUDA enabled devices"
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "Found "
.LC2:
.string " CUDA enabled devices"
.text
.globl use_cuda
.type use_cuda, @function
use_cuda:
.LFB3669:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $24, %rsp
.cfi_def_cfa_offset 48
movq %fs:40, %rax
movq %rax, 8(%rsp)
xorl %eax, %eax
movl $0, 4(%rsp)
leaq 4(%rsp), %rdi
call cudaGetDeviceCount@PLT
testl %eax, %eax
jne .L16
movl $6, %edx
leaq .LC1(%rip), %rsi
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl 4(%rsp), %esi
movq %rbx, %rdi
call _ZNSolsEi@PLT
movq %rax, %rbx
movl $21, %edx
leaq .LC2(%rip), %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq (%rbx), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %rbp
testq %rbp, %rbp
je .L17
cmpb $0, 56(%rbp)
je .L12
movzbl 67(%rbp), %esi
.L13:
movsbl %sil, %esi
movq %rbx, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movl $0, %eax
.L3:
movq 8(%rsp), %rdx
subq %fs:40, %rdx
jne .L18
addq $24, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L16:
.cfi_restore_state
movl $53, %edx
leaq .LC0(%rip), %rsi
leaq _ZSt4cerr(%rip), %rbx
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq _ZSt4cerr(%rip), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %rbx
testq %rbx, %rbx
je .L19
cmpb $0, 56(%rbx)
je .L7
movzbl 67(%rbx), %esi
.L8:
movsbl %sil, %esi
leaq _ZSt4cerr(%rip), %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movl $1, %eax
jmp .L3
.L19:
movq 8(%rsp), %rax
subq %fs:40, %rax
jne .L20
call _ZSt16__throw_bad_castv@PLT
.L20:
call __stack_chk_fail@PLT
.L7:
movq %rbx, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%rbx), %rax
movl $10, %esi
movq %rbx, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L8
.L17:
movq 8(%rsp), %rax
subq %fs:40, %rax
jne .L21
call _ZSt16__throw_bad_castv@PLT
.L21:
call __stack_chk_fail@PLT
.L12:
movq %rbp, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq 0(%rbp), %rax
movl $10, %esi
movq %rbp, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L13
.L18:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size use_cuda, .-use_cuda
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
```
|
```amdasm
.text
.file "cuda.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl use_cuda # -- Begin function use_cuda
.type use_cuda,@function
use_cuda: # @use_cuda
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
pushq %rax
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -24
.cfi_offset %rbp, -16
leaq 4(%rsp), %rdi
movl $0, (%rdi)
callq hipGetDeviceCount
testl %eax, %eax
je .LBB0_2
# %bb.1:
movl $_ZSt4cerr, %ebx
movl $_ZSt4cerr, %edi
movl $.L.str, %esi
movl $53, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $1, %ebp
jmp .LBB0_3
.LBB0_2:
movl $_ZSt4cout, %edi
movl $.L.str.1, %esi
movl $6, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl 4(%rsp), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movq %rax, %rbx
movl $.L.str.2, %esi
movl $21, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
xorl %ebp, %ebp
.LBB0_3:
movq (%rbx), %rax
movq -24(%rax), %rdi
addq %rbx, %rdi
movl $10, %esi
callq _ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
movsbl %al, %esi
movq %rbx, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl %ebp, %eax
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size use_cuda, .Lfunc_end0-use_cuda
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Failed to retrieve the number of CUDA enabled devices"
.size .L.str, 54
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Found "
.size .L.str.1, 7
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz " CUDA enabled devices"
.size .L.str.2, 22
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _ZSt4cerr
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_cuid_
```
| 2,111 | 1,070 |
394 |
Convert the following CUDA device assembly code to AMD device assembly:
```cudaasm
code for sm_80
Function : _Z12convolution3PKfPfii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ;
S2R R0, SR_TID.X ;
IMAD.MOV.U32 R8, RZ, RZ, c[0x0][0x170] ;
ULDC.64 UR6, c[0x0][0x118] ;
BSSY B0, 0x190 ;
S2R R7, SR_CTAID.X ;
LEA.HI R2, R8, c[0x0][0x170], RZ, 0x1 ;
SHF.R.S32.HI R3, RZ, 0x1, R2 ;
IADD3 R5, -R3, c[0x0][0x0], RZ ;
ISETP.GE.U32.AND P0, PT, R0, R5, PT ;
IMAD R2, R7, c[0x0][0x0], R0 ;
@!P0 BRA 0x180 ;
IADD3 R5, R7, -0x1, RZ ;
BSSY B1, 0x170 ;
HFMA2.MMA R4, -RZ, RZ, 0, 0 ;
IADD3 R7, R3, -c[0x0][0x0], R0.reuse ;
IMAD R5, R5, c[0x0][0x0], R0 ;
ISETP.GE.AND P0, PT, R5, RZ, PT ;
@!P0 BRA 0x160 ;
IMAD.MOV.U32 R4, RZ, RZ, 0x4 ;
IMAD.WIDE R4, R5, R4, c[0x0][0x160] ;
LDG.E R4, [R4.64] ;
BSYNC B1 ;
STS [R7.X4], R4 ;
BSYNC B0 ;
MOV R9, 0x4 ;
IMAD.WIDE.U32 R4, R2, R9, c[0x0][0x160] ;
LDG.E R4, [R4.64] ;
IMAD.IADD R7, R3, 0x1, R0 ;
ISETP.GE.U32.AND P0, PT, R0, R3, PT ;
BSSY B0, 0x2d0 ;
STS [R7.X4], R4 ;
@P0 BRA 0x2c0 ;
IADD3 R4, R2, c[0x0][0x0], RZ ;
BSSY B1, 0x2b0 ;
SHF.L.U32 R7, R7, 0x2, RZ ;
IMAD.MOV.U32 R5, RZ, RZ, RZ ;
ISETP.GE.AND P0, PT, R4, c[0x0][0x174], PT ;
IMAD R6, R9, c[0x0][0x0], R7 ;
@P0 BRA 0x2a0 ;
IMAD.WIDE R4, R4, R9, c[0x0][0x160] ;
LDG.E R5, [R4.64] ;
BSYNC B1 ;
STS [R6], R5 ;
BSYNC B0 ;
BAR.SYNC.DEFER_BLOCKING 0x0 ;
ISETP.GE.AND P0, PT, R8, 0x1, PT ;
HFMA2.MMA R7, -RZ, RZ, 0, 0 ;
@!P0 BRA 0xaa0 ;
IADD3 R3, R8.reuse, -0x1, RZ ;
UMOV UR4, URZ ;
IMAD.MOV.U32 R7, RZ, RZ, RZ ;
ISETP.GE.U32.AND P0, PT, R3, 0x3, PT ;
LOP3.LUT R3, R8, 0x3, RZ, 0xc0, !PT ;
@!P0 BRA 0x9d0 ;
IADD3 R5, -R3, c[0x0][0x170], RZ ;
UMOV UR4, URZ ;
HFMA2.MMA R7, -RZ, RZ, 0, 0 ;
UMOV UR5, URZ ;
ISETP.GT.AND P0, PT, R5, RZ, PT ;
LEA R4, R0, 0x8, 0x2 ;
@!P0 BRA 0x8d0 ;
ISETP.GT.AND P1, PT, R5, 0xc, PT ;
PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ;
@!P1 BRA 0x700 ;
PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ;
LDS R10, [R4+-0x8] ;
ULDC.64 UR8, c[0x3][UR5] ;
IADD3 R5, R5, -0x10, RZ ;
UIADD3 UR4, UR4, 0x10, URZ ;
LDS R9, [R4+-0x4] ;
ISETP.GT.AND P1, PT, R5, 0xc, PT ;
LDS R12, [R4] ;
LDS R14, [R4+0x4] ;
LDS R16, [R4+0x8] ;
LDS R18, [R4+0xc] ;
LDS R20, [R4+0x10] ;
LDS R22, [R4+0x14] ;
LDS R8, [R4+0x18] ;
LDS R6, [R4+0x1c] ;
FFMA R10, R10, UR8, R7 ;
LDS R11, [R4+0x24] ;
FFMA R9, R9, UR9, R10 ;
LDS R7, [R4+0x20] ;
ULDC.64 UR8, c[0x3][UR5+0x8] ;
FFMA R9, R12, UR8, R9 ;
LDS R13, [R4+0x28] ;
FFMA R9, R14, UR9, R9 ;
LDS R15, [R4+0x2c] ;
ULDC.64 UR8, c[0x3][UR5+0x10] ;
FFMA R9, R16, UR8, R9 ;
LDS R17, [R4+0x30] ;
FFMA R9, R18, UR9, R9 ;
LDS R19, [R4+0x34] ;
ULDC.64 UR8, c[0x3][UR5+0x18] ;
FFMA R9, R20, UR8, R9 ;
FFMA R9, R22, UR9, R9 ;
ULDC.64 UR8, c[0x3][UR5+0x20] ;
IADD3 R4, R4, 0x40, RZ ;
FFMA R9, R8, UR8, R9 ;
FFMA R6, R6, UR9, R9 ;
ULDC.64 UR8, c[0x3][UR5+0x28] ;
FFMA R6, R7, UR8, R6 ;
FFMA R6, R11, UR9, R6 ;
ULDC.64 UR8, c[0x3][UR5+0x30] ;
FFMA R6, R13, UR8, R6 ;
FFMA R6, R15, UR9, R6 ;
ULDC.64 UR8, c[0x3][UR5+0x38] ;
UIADD3 UR5, UR5, 0x40, URZ ;
FFMA R6, R17, UR8, R6 ;
FFMA R7, R19, UR9, R6 ;
@P1 BRA 0x420 ;
ISETP.GT.AND P1, PT, R5, 0x4, PT ;
@!P1 BRA 0x8b0 ;
LDS R6, [R4+-0x8] ;
ULDC.64 UR8, c[0x3][UR5] ;
PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ;
UIADD3 UR4, UR4, 0x8, URZ ;
LDS R9, [R4+-0x4] ;
IADD3 R5, R5, -0x8, RZ ;
LDS R11, [R4] ;
LDS R13, [R4+0x4] ;
LDS R15, [R4+0x8] ;
LDS R17, [R4+0xc] ;
LDS R19, [R4+0x10] ;
LDS R21, [R4+0x14] ;
IADD3 R4, R4, 0x20, RZ ;
FFMA R6, R6, UR8, R7 ;
FFMA R6, R9, UR9, R6 ;
ULDC.64 UR8, c[0x3][UR5+0x8] ;
FFMA R6, R11, UR8, R6 ;
FFMA R6, R13, UR9, R6 ;
ULDC.64 UR8, c[0x3][UR5+0x10] ;
FFMA R6, R15, UR8, R6 ;
FFMA R6, R17, UR9, R6 ;
ULDC.64 UR8, c[0x3][UR5+0x18] ;
UIADD3 UR5, UR5, 0x20, URZ ;
FFMA R6, R19, UR8, R6 ;
FFMA R7, R21, UR9, R6 ;
ISETP.NE.OR P0, PT, R5, RZ, P0 ;
@!P0 BRA 0x9d0 ;
LDS R6, [R4+-0x8] ;
IADD3 R5, R5, -0x4, RZ ;
ULDC.64 UR8, c[0x3][UR5] ;
LDS R9, [R4+-0x4] ;
ISETP.NE.AND P0, PT, R5, RZ, PT ;
UIADD3 UR4, UR4, 0x4, URZ ;
LDS R11, [R4] ;
LDS R13, [R4+0x4] ;
IADD3 R4, R4, 0x10, RZ ;
FFMA R6, R6, UR8, R7 ;
FFMA R6, R9, UR9, R6 ;
ULDC.64 UR8, c[0x3][UR5+0x8] ;
UIADD3 UR5, UR5, 0x10, URZ ;
FFMA R6, R11, UR8, R6 ;
FFMA R7, R13, UR9, R6 ;
@P0 BRA 0x8d0 ;
ISETP.NE.AND P0, PT, R3, RZ, PT ;
@!P0 BRA 0xaa0 ;
IADD3 R0, R0, UR4, RZ ;
USHF.L.U32 UR5, UR4, 0x2, URZ ;
IMAD.SHL.U32 R0, R0, 0x4, RZ ;
LDS R4, [R0] ;
IADD3 R3, R3, -0x1, RZ ;
ULDC UR4, c[0x3][UR5] ;
UIADD3 UR5, UR5, 0x4, URZ ;
ISETP.NE.AND P0, PT, R3, RZ, PT ;
IADD3 R0, R0, 0x4, RZ ;
FFMA R7, R4, UR4, R7 ;
@P0 BRA 0xa20 ;
LEA R4, P0, R2, c[0x0][0x168], 0x2 ;
LEA.HI.X R5, R2, c[0x0][0x16c], RZ, 0x2, P0 ;
STG.E [R4.64], R7 ;
EXIT ;
BRA 0xae0;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
Function : _Z12convolution2PKfPfii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ;
S2R R6, SR_CTAID.X ;
IMAD.MOV.U32 R9, RZ, RZ, c[0x0][0x170] ;
ULDC.64 UR6, c[0x0][0x118] ;
IMAD.MOV.U32 R5, RZ, RZ, RZ ;
S2R R7, SR_TID.X ;
ISETP.GE.AND P0, PT, R9, 0x1, PT ;
IMAD R4, R6, c[0x0][0x0], R7 ;
@!P0 BRA 0x4f0 ;
IADD3 R2, R9.reuse, -0x1, RZ ;
UMOV UR4, URZ ;
LOP3.LUT R0, R9.reuse, 0x3, RZ, 0xc0, !PT ;
IMAD.MOV.U32 R5, RZ, RZ, RZ ;
ISETP.GE.U32.AND P0, PT, R2, 0x3, PT ;
LEA.HI R9, R9, c[0x0][0x170], RZ, 0x1 ;
ISETP.NE.AND P4, PT, R0, RZ, PT ;
SHF.R.S32.HI R9, RZ, 0x1, R9 ;
@!P0 BRA 0x390 ;
IMAD.IADD R2, R4, 0x1, -R9 ;
IADD3 R19, R0, -c[0x0][0x170], RZ ;
IMAD.MOV.U32 R3, RZ, RZ, 0x4 ;
IADD3 R8, -R9, 0x3, R4 ;
IMAD.MOV.U32 R5, RZ, RZ, RZ ;
UMOV UR4, URZ ;
IMAD.WIDE R2, R2, R3, c[0x0][0x160] ;
IMAD.MOV.U32 R18, RZ, RZ, RZ ;
IADD3 R10, R8.reuse, -0x3, RZ ;
IADD3 R11, R8, -0x2, RZ ;
ISETP.GE.AND P0, PT, R10, c[0x0][0x174], PT ;
IADD3 R12, R8, -0x1, RZ ;
ISETP.LT.OR P0, PT, R10, RZ, P0 ;
ISETP.GE.AND P1, PT, R11, c[0x0][0x174], PT ;
ISETP.GE.AND P2, PT, R12.reuse, c[0x0][0x174], PT ;
ISETP.LT.OR P1, PT, R11, RZ, P1 ;
ISETP.LT.OR P2, PT, R12, RZ, P2 ;
ISETP.GE.AND P3, PT, R8, c[0x0][0x174], PT ;
@!P0 LDG.E R10, [R2.64] ;
ISETP.LT.OR P3, PT, R8, RZ, P3 ;
@!P1 LDG.E R13, [R2.64+0x4] ;
@!P2 LDG.E R15, [R2.64+0x8] ;
@!P3 LDG.E R17, [R2.64+0xc] ;
@!P0 LDC R11, c[0x3][R18] ;
UIADD3 UR4, UR4, 0x4, URZ ;
@!P1 LDC R12, c[0x3][R18+0x4] ;
@!P2 LDC R14, c[0x3][R18+0x8] ;
@!P3 LDC R16, c[0x3][R18+0xc] ;
IADD3 R8, R8, 0x4, RZ ;
IADD3 R18, R18, 0x10, RZ ;
@!P0 FFMA R5, R10, R11, R5 ;
IADD3 R10, R19, UR4, RZ ;
ISETP.NE.AND P0, PT, R10, RZ, PT ;
@!P1 FFMA R5, R12, R13, R5 ;
IADD3 R2, P1, R2, 0x10, RZ ;
@!P2 FFMA R5, R14, R15, R5 ;
IMAD.X R3, RZ, RZ, R3, P1 ;
@!P3 FFMA R5, R16, R17, R5 ;
@P0 BRA 0x1a0 ;
@!P4 BRA 0x4f0 ;
IADD3 R7, R7, UR4, RZ ;
IMAD.MOV.U32 R3, RZ, RZ, 0x4 ;
USHF.L.U32 UR4, UR4, 0x2, URZ ;
IMAD R6, R6, c[0x0][0x0], R7 ;
IMAD.IADD R6, R6, 0x1, -R9 ;
IMAD.U32 R9, RZ, RZ, UR4 ;
IMAD.WIDE R2, R6, R3, c[0x0][0x160] ;
IMAD.MOV.U32 R7, RZ, RZ, R2 ;
ISETP.GE.AND P0, PT, R6, c[0x0][0x174], PT ;
ISETP.LT.OR P0, PT, R6, RZ, P0 ;
@!P0 IMAD.MOV.U32 R2, RZ, RZ, R7 ;
@!P0 LDG.E R2, [R2.64] ;
@!P0 LDC R8, c[0x3][R9] ;
IADD3 R0, R0, -0x1, RZ ;
IADD3 R7, P2, R7, 0x4, RZ ;
ISETP.NE.AND P1, PT, R0, RZ, PT ;
IADD3 R6, R6, 0x1, RZ ;
IADD3 R9, R9, 0x4, RZ ;
IMAD.X R3, RZ, RZ, R3, P2 ;
@!P0 FFMA R5, R8, R2, R5 ;
@P1 BRA 0x420 ;
IMAD.MOV.U32 R3, RZ, RZ, 0x4 ;
IMAD.WIDE.U32 R2, R4, R3, c[0x0][0x168] ;
STG.E [R2.64], R5 ;
EXIT ;
BRA 0x530;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
Function : _Z12convolution1PKfS0_Pfii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ;
S2R R8, SR_CTAID.X ;
IMAD.MOV.U32 R9, RZ, RZ, c[0x0][0x178] ;
ULDC.64 UR4, c[0x0][0x118] ;
IMAD.MOV.U32 R7, RZ, RZ, RZ ;
S2R R11, SR_TID.X ;
ISETP.GE.AND P0, PT, R9, 0x1, PT ;
IMAD R0, R8, c[0x0][0x0], R11 ;
@!P0 BRA 0x580 ;
IADD3 R2, R9.reuse, -0x1, RZ ;
IMAD.MOV.U32 R7, RZ, RZ, RZ ;
LOP3.LUT R6, R9.reuse, 0x3, RZ, 0xc0, !PT ;
IMAD.MOV.U32 R10, RZ, RZ, RZ ;
ISETP.GE.U32.AND P0, PT, R2, 0x3, PT ;
LEA.HI R9, R9, c[0x0][0x178], RZ, 0x1 ;
ISETP.NE.AND P4, PT, R6, RZ, PT ;
SHF.R.S32.HI R9, RZ, 0x1, R9 ;
@!P0 BRA 0x400 ;
IADD3 R2, R0, -R9, RZ ;
IMAD.MOV.U32 R3, RZ, RZ, 0x4 ;
HFMA2.MMA R10, -RZ, RZ, 0, 0 ;
IADD3 R13, R6, -c[0x0][0x178], RZ ;
IMAD.MOV.U32 R7, RZ, RZ, RZ ;
IADD3 R21, -R9, 0x3, R0 ;
IMAD.WIDE R2, R2, R3, c[0x0][0x160] ;
IMAD.MOV.U32 R15, RZ, RZ, R3 ;
IMAD.MOV.U32 R14, RZ, RZ, R2 ;
IMAD.MOV.U32 R12, RZ, RZ, c[0x0][0x168] ;
IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x16c] ;
IADD3 R2, R21.reuse, -0x3, RZ ;
IADD3 R4, R21, -0x2, RZ ;
ISETP.GE.AND P0, PT, R2, c[0x0][0x17c], PT ;
IADD3 R5, R21, -0x1, RZ ;
ISETP.LT.OR P0, PT, R2, RZ, P0 ;
ISETP.GE.AND P1, PT, R4.reuse, c[0x0][0x17c], PT ;
ISETP.GE.AND P2, PT, R5.reuse, c[0x0][0x17c], PT ;
ISETP.LT.OR P1, PT, R4, RZ, P1 ;
IMAD.MOV.U32 R4, RZ, RZ, R14 ;
ISETP.LT.OR P2, PT, R5, RZ, P2 ;
IMAD.MOV.U32 R5, RZ, RZ, R15 ;
MOV R2, R12 ;
ISETP.GE.AND P3, PT, R21.reuse, c[0x0][0x17c], PT ;
@!P0 LDG.E R12, [R4.64] ;
ISETP.LT.OR P3, PT, R21, RZ, P3 ;
@!P0 LDG.E R14, [R2.64] ;
@!P1 LDG.E R16, [R2.64+0x4] ;
@!P1 LDG.E R15, [R4.64+0x4] ;
@!P2 LDG.E R18, [R2.64+0x8] ;
@!P2 LDG.E R17, [R4.64+0x8] ;
@!P3 LDG.E R20, [R2.64+0xc] ;
@!P3 LDG.E R19, [R4.64+0xc] ;
IADD3 R10, R10, 0x4, RZ ;
IADD3 R21, R21, 0x4, RZ ;
@!P0 FFMA R7, R12, R14, R7 ;
IMAD.IADD R12, R13, 0x1, R10 ;
ISETP.NE.AND P0, PT, R12, RZ, PT ;
@!P1 FFMA R7, R16, R15, R7 ;
IADD3 R14, P1, R4, 0x10, RZ ;
IADD3 R12, P5, R2, 0x10, RZ ;
@!P2 FFMA R7, R18, R17, R7 ;
IMAD.X R15, RZ, RZ, R5, P1 ;
IMAD.X R3, RZ, RZ, R3, P5 ;
@!P3 FFMA R7, R20, R19, R7 ;
@P0 BRA 0x1d0 ;
@!P4 BRA 0x580 ;
IMAD.IADD R11, R11, 0x1, R10 ;
MOV R3, 0x4 ;
IMAD R8, R8, c[0x0][0x0], R11 ;
IMAD.WIDE R10, R10, R3, c[0x0][0x168] ;
IMAD.IADD R8, R8, 0x1, -R9 ;
IMAD.WIDE R2, R8, R3, c[0x0][0x160] ;
IMAD.MOV.U32 R9, RZ, RZ, R2 ;
ISETP.GE.AND P0, PT, R8, c[0x0][0x17c], PT ;
ISETP.LT.OR P0, PT, R8, RZ, P0 ;
@!P0 IMAD.MOV.U32 R2, RZ, RZ, R9 ;
@!P0 MOV R5, R11 ;
@!P0 IMAD.MOV.U32 R4, RZ, RZ, R10 ;
@!P0 LDG.E R2, [R2.64] ;
@!P0 LDG.E R4, [R4.64] ;
IADD3 R6, R6, -0x1, RZ ;
IADD3 R10, P2, R10, 0x4, RZ ;
ISETP.NE.AND P1, PT, R6, RZ, PT ;
IADD3 R9, P3, R9, 0x4, RZ ;
IMAD.X R11, RZ, RZ, R11, P2 ;
IADD3 R8, R8, 0x1, RZ ;
IMAD.X R3, RZ, RZ, R3, P3 ;
@!P0 FFMA R7, R2, R4, R7 ;
@P1 BRA 0x480 ;
IMAD.MOV.U32 R3, RZ, RZ, 0x4 ;
IMAD.WIDE.U32 R2, R0, R3, c[0x0][0x170] ;
STG.E [R2.64], R7 ;
EXIT ;
BRA 0x5c0;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
```
|
```amdasm
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z12convolution1PKfS0_Pfii ; -- Begin function _Z12convolution1PKfS0_Pfii
.globl _Z12convolution1PKfS0_Pfii
.p2align 8
.type _Z12convolution1PKfS0_Pfii,@function
_Z12convolution1PKfS0_Pfii: ; @_Z12convolution1PKfS0_Pfii
; %bb.0:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b256 s[4:11], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s0, s2, 0xffff
s_cmp_lt_i32 s10, 1
v_mad_u64_u32 v[1:2], null, s15, s0, v[0:1]
s_cbranch_scc1 .LBB0_5
; %bb.1: ; %.lr.ph.preheader
s_lshr_b32 s0, s10, 31
v_mov_b32_e32 v3, 0
s_add_i32 s0, s10, s0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_ashr_i32 s0, s0, 1
v_mov_b32_e32 v0, v3
s_delay_alu instid0(VALU_DEP_3)
v_subrev_nc_u32_e32 v2, s0, v1
.LBB0_2: ; %.lr.ph
; =>This Inner Loop Header: Depth=1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_lt_i32_e32 vcc_lo, -1, v2
v_cmp_gt_i32_e64 s0, s11, v2
s_and_b32 s1, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s0, s1
s_cbranch_execz .LBB0_4
; %bb.3: ; in Loop: Header=BB0_2 Depth=1
v_lshlrev_b64 v[4:5], 2, v[2:3]
s_load_b32 s1, s[6:7], 0x0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v4, vcc_lo, s4, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v5, vcc_lo
global_load_b32 v4, v[4:5], off
s_waitcnt vmcnt(0) lgkmcnt(0)
v_fmac_f32_e32 v0, s1, v4
.LBB0_4: ; in Loop: Header=BB0_2 Depth=1
s_or_b32 exec_lo, exec_lo, s0
s_add_i32 s10, s10, -1
v_add_nc_u32_e32 v2, 1, v2
s_add_u32 s6, s6, 4
s_addc_u32 s7, s7, 0
s_cmp_eq_u32 s10, 0
s_cbranch_scc0 .LBB0_2
s_branch .LBB0_6
.LBB0_5:
v_mov_b32_e32 v0, 0
.LBB0_6: ; %Flow42
v_mov_b32_e32 v2, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[1:2], 2, v[1:2]
v_add_co_u32 v1, vcc_lo, s8, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, s9, v2, vcc_lo
global_store_b32 v[1:2], v0, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z12convolution1PKfS0_Pfii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z12convolution1PKfS0_Pfii, .Lfunc_end0-_Z12convolution1PKfS0_Pfii
; -- End function
.section .AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 248
; NumSgprs: 18
; NumVgprs: 6
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 6
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
.text
.protected _Z12convolution2PKfPfii ; -- Begin function _Z12convolution2PKfPfii
.globl _Z12convolution2PKfPfii
.p2align 8
.type _Z12convolution2PKfPfii,@function
_Z12convolution2PKfPfii: ; @_Z12convolution2PKfPfii
; %bb.0:
s_clause 0x2
s_load_b32 s8, s[0:1], 0x24
s_load_b64 s[2:3], s[0:1], 0x10
s_load_b128 s[4:7], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s0, s8, 0xffff
s_cmp_lt_i32 s2, 1
v_mad_u64_u32 v[1:2], null, s15, s0, v[0:1]
s_cbranch_scc1 .LBB1_5
; %bb.1: ; %.lr.ph.preheader
s_lshr_b32 s0, s2, 31
v_mov_b32_e32 v3, 0
s_add_i32 s0, s2, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_ashr_i32 s0, s0, 1
s_getpc_b64 s[8:9]
s_add_u32 s8, s8, c_M@rel32@lo+4
s_addc_u32 s9, s9, c_M@rel32@hi+12
v_subrev_nc_u32_e32 v2, s0, v1
v_mov_b32_e32 v0, v3
.LBB1_2: ; %.lr.ph
; =>This Inner Loop Header: Depth=1
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_lt_i32_e32 vcc_lo, -1, v2
v_cmp_gt_i32_e64 s0, s3, v2
s_and_b32 s1, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s0, s1
s_cbranch_execz .LBB1_4
; %bb.3: ; in Loop: Header=BB1_2 Depth=1
v_lshlrev_b64 v[4:5], 2, v[2:3]
s_load_b32 s1, s[8:9], 0x0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v4, vcc_lo, s4, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v5, vcc_lo
global_load_b32 v4, v[4:5], off
s_waitcnt vmcnt(0) lgkmcnt(0)
v_fmac_f32_e32 v0, s1, v4
.LBB1_4: ; in Loop: Header=BB1_2 Depth=1
s_or_b32 exec_lo, exec_lo, s0
s_add_i32 s2, s2, -1
v_add_nc_u32_e32 v2, 1, v2
s_add_u32 s8, s8, 4
s_addc_u32 s9, s9, 0
s_cmp_eq_u32 s2, 0
s_cbranch_scc0 .LBB1_2
s_branch .LBB1_6
.LBB1_5:
v_mov_b32_e32 v0, 0
.LBB1_6: ; %Flow37
v_mov_b32_e32 v2, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[1:2], 2, v[1:2]
v_add_co_u32 v1, vcc_lo, s6, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, s7, v2, vcc_lo
global_store_b32 v[1:2], v0, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z12convolution2PKfPfii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z12convolution2PKfPfii, .Lfunc_end1-_Z12convolution2PKfPfii
; -- End function
.section .AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 272
; NumSgprs: 18
; NumVgprs: 6
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 6
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
.text
.protected _Z12convolution3PKfPfii ; -- Begin function _Z12convolution3PKfPfii
.globl _Z12convolution3PKfPfii
.p2align 8
.type _Z12convolution3PKfPfii,@function
_Z12convolution3PKfPfii: ; @_Z12convolution3PKfPfii
; %bb.0:
s_clause 0x2
s_load_b64 s[4:5], s[0:1], 0x10
s_load_b32 s6, s[0:1], 0x24
s_load_b128 s[0:3], s[0:1], 0x0
; implicit-def: $vgpr5
s_waitcnt lgkmcnt(0)
s_lshr_b32 s7, s4, 31
s_and_b32 s6, s6, 0xffff
s_add_i32 s7, s4, s7
s_mul_i32 s15, s15, s6
s_ashr_i32 s7, s7, 1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_sub_i32 s8, s6, s7
v_cmp_le_u32_e32 vcc_lo, s8, v0
s_and_saveexec_b32 s8, vcc_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s8, exec_lo, s8
s_cbranch_execz .LBB2_4
; %bb.1:
s_sub_i32 s9, s15, s6
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_dual_mov_b32 v2, 0 :: v_dual_add_nc_u32 v1, s9, v0
s_mov_b32 s9, exec_lo
v_cmpx_lt_i32_e32 -1, v1
s_cbranch_execz .LBB2_3
; %bb.2:
v_mov_b32_e32 v2, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[1:2], 2, v[1:2]
v_add_co_u32 v1, vcc_lo, s0, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
global_load_b32 v2, v[1:2], off
.LBB2_3:
s_or_b32 exec_lo, exec_lo, s9
v_add_nc_u32_e32 v5, s7, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_subrev_nc_u32_e32 v1, s6, v5
v_lshlrev_b32_e32 v1, 2, v1
s_waitcnt vmcnt(0)
ds_store_b32 v1, v2
.LBB2_4: ; %Flow51
s_and_not1_saveexec_b32 s8, s8
; %bb.5: ; %._crit_edge33
v_add_nc_u32_e32 v5, s7, v0
; %bb.6:
s_or_b32 exec_lo, exec_lo, s8
v_dual_mov_b32 v4, 0 :: v_dual_add_nc_u32 v3, s15, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b32_e32 v5, 2, v5
v_lshlrev_b64 v[1:2], 2, v[3:4]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v6, vcc_lo, s0, v1
v_add_co_ci_u32_e32 v7, vcc_lo, s1, v2, vcc_lo
v_cmp_gt_u32_e32 vcc_lo, s7, v0
global_load_b32 v6, v[6:7], off
s_waitcnt vmcnt(0)
ds_store_b32 v5, v6
s_and_saveexec_b32 s7, vcc_lo
s_cbranch_execz .LBB2_10
; %bb.7:
v_add_nc_u32_e32 v3, s6, v3
s_delay_alu instid0(VALU_DEP_1)
v_cmp_gt_i32_e32 vcc_lo, s5, v3
s_and_saveexec_b32 s5, vcc_lo
s_cbranch_execz .LBB2_9
; %bb.8:
v_ashrrev_i32_e32 v4, 31, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[3:4]
v_add_co_u32 v3, vcc_lo, s0, v3
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo
global_load_b32 v4, v[3:4], off
.LBB2_9:
s_or_b32 exec_lo, exec_lo, s5
v_lshl_add_u32 v3, s6, 2, v5
s_waitcnt vmcnt(0)
ds_store_b32 v3, v4
.LBB2_10: ; %Flow50
s_or_b32 exec_lo, exec_lo, s7
s_cmp_lt_i32 s4, 1
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB2_13
; %bb.11: ; %.lr.ph.preheader
v_dual_mov_b32 v0, 0 :: v_dual_lshlrev_b32 v3, 2, v0
s_getpc_b64 s[0:1]
s_add_u32 s0, s0, c_M@rel32@lo+4
s_addc_u32 s1, s1, c_M@rel32@hi+12
.LBB2_12: ; %.lr.ph
; =>This Inner Loop Header: Depth=1
ds_load_b32 v4, v3
s_load_b32 s5, s[0:1], 0x0
s_add_i32 s4, s4, -1
v_add_nc_u32_e32 v3, 4, v3
s_add_u32 s0, s0, 4
s_addc_u32 s1, s1, 0
s_cmp_eq_u32 s4, 0
s_waitcnt lgkmcnt(0)
v_fmac_f32_e32 v0, s5, v4
s_cbranch_scc0 .LBB2_12
s_branch .LBB2_14
.LBB2_13:
v_mov_b32_e32 v0, 0
.LBB2_14: ; %Flow49
v_add_co_u32 v1, vcc_lo, s2, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s3, v2, vcc_lo
global_store_b32 v[1:2], v0, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z12convolution3PKfPfii
.amdhsa_group_segment_fixed_size 272
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end2:
.size _Z12convolution3PKfPfii, .Lfunc_end2-_Z12convolution3PKfPfii
; -- End function
.section .AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 496
; NumSgprs: 18
; NumVgprs: 8
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 272 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 8
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.protected c_M ; @c_M
.type c_M,@object
.section .bss,"aw",@nobits
.globl c_M
.p2align 4, 0x0
c_M:
.zero 20
.size c_M, 20
.type __hip_cuid_,@object ; @__hip_cuid_
.globl __hip_cuid_
__hip_cuid_:
.byte 0 ; 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym c_M
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z12convolution1PKfS0_Pfii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z12convolution1PKfS0_Pfii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z12convolution2PKfPfii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z12convolution2PKfPfii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 272
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z12convolution3PKfPfii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z12convolution3PKfPfii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
```
| 6,692 | 9,375 |
395 |
Convert the following CUDA host assembly code to AMD host assembly:
```cudaasm
.file "tmpxft_0014b803_00000000-6_main.cudafe1.cpp"
.text
.globl _ZSt21ios_base_library_initv
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB4074:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4074:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z40__device_stub__Z12convolution1PKfS0_PfiiPKfS0_Pfii
.type _Z40__device_stub__Z12convolution1PKfS0_PfiiPKfS0_Pfii, @function
_Z40__device_stub__Z12convolution1PKfS0_PfiiPKfS0_Pfii:
.LFB4096:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z12convolution1PKfS0_Pfii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4096:
.size _Z40__device_stub__Z12convolution1PKfS0_PfiiPKfS0_Pfii, .-_Z40__device_stub__Z12convolution1PKfS0_PfiiPKfS0_Pfii
.globl _Z12convolution1PKfS0_Pfii
.type _Z12convolution1PKfS0_Pfii, @function
_Z12convolution1PKfS0_Pfii:
.LFB4097:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z40__device_stub__Z12convolution1PKfS0_PfiiPKfS0_Pfii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4097:
.size _Z12convolution1PKfS0_Pfii, .-_Z12convolution1PKfS0_Pfii
.globl _Z37__device_stub__Z12convolution2PKfPfiiPKfPfii
.type _Z37__device_stub__Z12convolution2PKfPfiiPKfPfii, @function
_Z37__device_stub__Z12convolution2PKfPfiiPKfPfii:
.LFB4098:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z12convolution2PKfPfii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4098:
.size _Z37__device_stub__Z12convolution2PKfPfiiPKfPfii, .-_Z37__device_stub__Z12convolution2PKfPfiiPKfPfii
.globl _Z12convolution2PKfPfii
.type _Z12convolution2PKfPfii, @function
_Z12convolution2PKfPfii:
.LFB4099:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z37__device_stub__Z12convolution2PKfPfiiPKfPfii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4099:
.size _Z12convolution2PKfPfii, .-_Z12convolution2PKfPfii
.globl _Z37__device_stub__Z12convolution3PKfPfiiPKfPfii
.type _Z37__device_stub__Z12convolution3PKfPfiiPKfPfii, @function
_Z37__device_stub__Z12convolution3PKfPfiiPKfPfii:
.LFB4100:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L23
.L19:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L24
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z12convolution3PKfPfii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L19
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4100:
.size _Z37__device_stub__Z12convolution3PKfPfiiPKfPfii, .-_Z37__device_stub__Z12convolution3PKfPfiiPKfPfii
.globl _Z12convolution3PKfPfii
.type _Z12convolution3PKfPfii, @function
_Z12convolution3PKfPfii:
.LFB4101:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z37__device_stub__Z12convolution3PKfPfiiPKfPfii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4101:
.size _Z12convolution3PKfPfii, .-_Z12convolution3PKfPfii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z12convolution3PKfPfii"
.LC1:
.string "_Z12convolution2PKfPfii"
.LC2:
.string "_Z12convolution1PKfS0_Pfii"
.LC3:
.string "c_M"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB4103:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z12convolution3PKfPfii(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z12convolution2PKfPfii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z12convolution1PKfS0_Pfii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $20, %r9d
movl $0, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _ZL3c_M(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4103:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .text._ZNSt6vectorIfSaIfEED2Ev,"axG",@progbits,_ZNSt6vectorIfSaIfEED5Ev,comdat
.align 2
.weak _ZNSt6vectorIfSaIfEED2Ev
.type _ZNSt6vectorIfSaIfEED2Ev, @function
_ZNSt6vectorIfSaIfEED2Ev:
.LFB4418:
.cfi_startproc
endbr64
movq (%rdi), %rax
testq %rax, %rax
je .L32
subq $8, %rsp
.cfi_def_cfa_offset 16
movq 16(%rdi), %rsi
subq %rax, %rsi
movq %rax, %rdi
call _ZdlPvm@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.L32:
ret
.cfi_endproc
.LFE4418:
.size _ZNSt6vectorIfSaIfEED2Ev, .-_ZNSt6vectorIfSaIfEED2Ev
.weak _ZNSt6vectorIfSaIfEED1Ev
.set _ZNSt6vectorIfSaIfEED1Ev,_ZNSt6vectorIfSaIfEED2Ev
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC5:
.string "---------------------------------------------"
.align 8
.LC6:
.string " GPU PROPERTIES "
.section .rodata.str1.1
.LC7:
.string "Device Name: "
.LC8:
.string "Memory Clock Rate: "
.LC10:
.string " GHz"
.LC11:
.string "Memory Bandwidth: "
.LC12:
.string " GB/s"
.LC13:
.string "Number of SM: "
.LC14:
.string "Max Threads per SM: "
.LC15:
.string "Registers per Block: "
.LC16:
.string "Shared Memory per Block: "
.LC17:
.string " B"
.section .rodata.str1.8
.align 8
.LC18:
.string "Total Global Memory per Block: "
.section .rodata.str1.1
.LC20:
.string " GB"
.section .rodata.str1.8
.align 8
.LC21:
.string "cannot create std::vector larger than max_size()"
.section .rodata.str1.1
.LC27:
.string "Wrong inputs!"
.LC28:
.string "Closing..."
.text
.globl main
.type main, @function
main:
.LFB4071:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA4071
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $1208, %rsp
.cfi_def_cfa_offset 1264
movq %rsi, %r14
movq %fs:40, %rax
movq %rax, 1192(%rsp)
xorl %eax, %eax
leaq 160(%rsp), %rbp
movl $0, %esi
movq %rbp, %rdi
.LEHB0:
call cudaGetDeviceProperties_v2@PLT
leaq .LC5(%rip), %r12
movq %r12, %rsi
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq .LC6(%rip), %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq %r12, %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq .LC7(%rip), %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movq %rbp, %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq .LC8(%rip), %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
pxor %xmm0, %xmm0
cvtsi2sdl 768(%rsp), %xmm0
divsd .LC9(%rip), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
leaq .LC10(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq .LC11(%rip), %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
pxor %xmm0, %xmm0
cvtsi2sdl 768(%rsp), %xmm0
addsd %xmm0, %xmm0
movl 772(%rsp), %eax
leal 7(%rax), %edx
testl %eax, %eax
cmovns %eax, %edx
sarl $3, %edx
pxor %xmm1, %xmm1
cvtsi2sdl %edx, %xmm1
mulsd %xmm1, %xmm0
divsd .LC9(%rip), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
leaq .LC12(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq .LC13(%rip), %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl 548(%rsp), %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq .LC14(%rip), %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl 784(%rsp), %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq .LC15(%rip), %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl 464(%rsp), %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq .LC16(%rip), %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movq 456(%rsp), %rsi
call _ZNSo9_M_insertImEERSoT_@PLT
movq %rax, %rdi
leaq .LC17(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq .LC18(%rip), %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movq 448(%rsp), %rdx
testq %rdx, %rdx
js .L36
pxor %xmm0, %xmm0
cvtsi2sdq %rdx, %xmm0
.L37:
divsd .LC19(%rip), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
leaq .LC20(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq _ZSt4cout(%rip), %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq 8(%r14), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %rbp
movl %eax, %r15d
movslq %eax, %r13
movq %r13, %rax
shrq $61, %rax
jne .L66
testq %r13, %r13
je .L40
leaq 0(,%r13,4), %rbx
movq %rbx, %rdi
call _Znwm@PLT
.LEHE0:
movq %rax, %r12
movq %rax, 32(%rsp)
leaq (%rax,%rbx), %rdx
movq %rdx, 48(%rsp)
movss .LC22(%rip), %xmm0
.L41:
movss %xmm0, (%rax)
addq $4, %rax
cmpq %rdx, %rax
jne .L41
movq %rdx, 40(%rsp)
movq %r12, %rax
pxor %xmm0, %xmm0
movss .LC22(%rip), %xmm1
.L42:
movss %xmm0, (%rax)
addss %xmm1, %xmm0
addq $4, %rax
cmpq %rdx, %rax
jne .L42
.L56:
movq %rsp, %rdi
movq %rbx, %rsi
.LEHB1:
call cudaMalloc@PLT
.LEHE1:
jmp .L67
.L36:
movq %rdx, %rax
shrq %rax
andl $1, %edx
orq %rdx, %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
addsd %xmm0, %xmm0
jmp .L37
.L66:
movq 1192(%rsp), %rax
subq %fs:40, %rax
jne .L68
leaq .LC21(%rip), %rdi
.LEHB2:
call _ZSt20__throw_length_errorPKc@PLT
.LEHE2:
.L68:
call __stack_chk_fail@PLT
.L67:
movl $1, %ecx
movq %rbx, %rdx
movq %r12, %rsi
movq (%rsp), %rdi
.LEHB3:
call cudaMemcpy@PLT
movss .LC22(%rip), %xmm0
movss %xmm0, 128(%rsp)
movss %xmm0, 132(%rsp)
movl $0x40000000, 136(%rsp)
movss %xmm0, 140(%rsp)
movss %xmm0, 144(%rsp)
movq $0, 72(%rsp)
movq $0, 80(%rsp)
movl $20, %edi
call _Znwm@PLT
.LEHE3:
movq %rax, %rsi
movq %rax, 64(%rsp)
leaq 20(%rax), %rax
movq %rax, 80(%rsp)
movdqa 128(%rsp), %xmm5
movups %xmm5, (%rsi)
movl 144(%rsp), %edx
movl %edx, 16(%rsi)
movq %rax, 72(%rsp)
movl $1, %r8d
movl $0, %ecx
movl $20, %edx
leaq _ZL3c_M(%rip), %rdi
.LEHB4:
call cudaMemcpyToSymbol@PLT
leaq 8(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
pxor %xmm0, %xmm0
cvtsi2ssl %ebp, %xmm0
mulss .LC24(%rip), %xmm0
movaps %xmm0, %xmm3
movss .LC29(%rip), %xmm2
movaps %xmm0, %xmm1
andps %xmm2, %xmm1
movss .LC25(%rip), %xmm4
ucomiss %xmm1, %xmm4
jbe .L43
cvttss2sil %xmm0, %eax
pxor %xmm1, %xmm1
cvtsi2ssl %eax, %xmm1
cmpnless %xmm1, %xmm3
movss .LC22(%rip), %xmm4
andps %xmm4, %xmm3
addss %xmm1, %xmm3
andnps %xmm0, %xmm2
orps %xmm2, %xmm3
.L43:
cvttss2sil %xmm3, %ebp
movq 16(%r14), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
cmpl $1, %eax
je .L69
cmpl $2, %eax
je .L70
leaq .LC27(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
jmp .L71
.L69:
movl $64, 96(%rsp)
movl $1, 100(%rsp)
movl $1, 104(%rsp)
movl %ebp, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 96(%rsp), %rdx
movl $1, %ecx
movq 20(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L46
movl %r15d, %ecx
movl $5, %edx
movq 8(%rsp), %rsi
movq (%rsp), %rdi
call _Z37__device_stub__Z12convolution2PKfPfiiPKfPfii
jmp .L46
.L70:
movl $64, 96(%rsp)
movl $1, 100(%rsp)
movl $1, 104(%rsp)
movl %ebp, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 96(%rsp), %rdx
movl $1, %ecx
movq 20(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L72
.L46:
movq $0, 104(%rsp)
movq $0, 112(%rsp)
testq %r13, %r13
je .L49
movq %rbx, %rdi
call _Znwm@PLT
jmp .L73
.L72:
movl %r15d, %ecx
movl $5, %edx
movq 8(%rsp), %rsi
movq (%rsp), %rdi
call _Z37__device_stub__Z12convolution3PKfPfiiPKfPfii
jmp .L46
.L71:
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
.LEHE4:
jmp .L46
.L73:
movq %rax, %rdi
movq %rax, 96(%rsp)
leaq (%rax,%rbx), %rax
movq %rax, 112(%rsp)
movl $0x00000000, (%rdi)
leaq 4(%rdi), %rdx
cmpq $1, %r13
je .L50
cmpq %rdx, %rax
je .L50
.L51:
movl $0x00000000, (%rdx)
addq $4, %rdx
cmpq %rdx, %rax
jne .L51
movq %rax, %rdx
jmp .L50
.L75:
movq (%rsp), %rdi
.LEHB5:
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
leaq .LC28(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
.LEHE5:
leaq 96(%rsp), %rdi
call _ZNSt6vectorIfSaIfEED1Ev
leaq 64(%rsp), %rdi
call _ZNSt6vectorIfSaIfEED1Ev
leaq 32(%rsp), %rdi
call _ZNSt6vectorIfSaIfEED1Ev
movq 1192(%rsp), %rax
subq %fs:40, %rax
jne .L74
movl $0, %eax
addq $1208, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L60:
.cfi_restore_state
endbr64
movq %rax, %rbx
leaq 96(%rsp), %rdi
call _ZNSt6vectorIfSaIfEED1Ev
.L53:
leaq 64(%rsp), %rdi
call _ZNSt6vectorIfSaIfEED1Ev
.L54:
leaq 32(%rsp), %rdi
call _ZNSt6vectorIfSaIfEED1Ev
movq 1192(%rsp), %rax
subq %fs:40, %rax
je .L55
call __stack_chk_fail@PLT
.L59:
endbr64
movq %rax, %rbx
jmp .L53
.L58:
endbr64
movq %rax, %rbx
jmp .L54
.L55:
movq %rbx, %rdi
.LEHB6:
call _Unwind_Resume@PLT
.LEHE6:
.L49:
movq $0, 96(%rsp)
movq %rbx, 112(%rsp)
movl $0, %edi
movl $0, %edx
.L50:
movq %rdx, 104(%rsp)
movl $2, %ecx
movq %rbx, %rdx
movq 8(%rsp), %rsi
.LEHB7:
call cudaMemcpy@PLT
.LEHE7:
jmp .L75
.L40:
movq $0, 32(%rsp)
movq $0, 48(%rsp)
movq $0, 40(%rsp)
movq %r13, %rbx
movl $0, %r12d
jmp .L56
.L74:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4071:
.globl __gxx_personality_v0
.section .gcc_except_table,"a",@progbits
.LLSDA4071:
.byte 0xff
.byte 0xff
.byte 0x1
.uleb128 .LLSDACSE4071-.LLSDACSB4071
.LLSDACSB4071:
.uleb128 .LEHB0-.LFB4071
.uleb128 .LEHE0-.LEHB0
.uleb128 0
.uleb128 0
.uleb128 .LEHB1-.LFB4071
.uleb128 .LEHE1-.LEHB1
.uleb128 .L58-.LFB4071
.uleb128 0
.uleb128 .LEHB2-.LFB4071
.uleb128 .LEHE2-.LEHB2
.uleb128 0
.uleb128 0
.uleb128 .LEHB3-.LFB4071
.uleb128 .LEHE3-.LEHB3
.uleb128 .L58-.LFB4071
.uleb128 0
.uleb128 .LEHB4-.LFB4071
.uleb128 .LEHE4-.LEHB4
.uleb128 .L59-.LFB4071
.uleb128 0
.uleb128 .LEHB5-.LFB4071
.uleb128 .LEHE5-.LEHB5
.uleb128 .L60-.LFB4071
.uleb128 0
.uleb128 .LEHB6-.LFB4071
.uleb128 .LEHE6-.LEHB6
.uleb128 0
.uleb128 0
.uleb128 .LEHB7-.LFB4071
.uleb128 .LEHE7-.LEHB7
.uleb128 .L60-.LFB4071
.uleb128 0
.LLSDACSE4071:
.text
.size main, .-main
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZL3c_M
.comm _ZL3c_M,20,16
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC9:
.long 0
.long 1093567616
.align 8
.LC19:
.long 0
.long 1104006501
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC22:
.long 1065353216
.align 4
.LC24:
.long 1015021568
.align 4
.LC25:
.long 1258291200
.align 4
.LC29:
.long 2147483647
.hidden DW.ref.__gxx_personality_v0
.weak DW.ref.__gxx_personality_v0
.section .data.rel.local.DW.ref.__gxx_personality_v0,"awG",@progbits,DW.ref.__gxx_personality_v0,comdat
.align 8
.type DW.ref.__gxx_personality_v0, @object
.size DW.ref.__gxx_personality_v0, 8
DW.ref.__gxx_personality_v0:
.quad __gxx_personality_v0
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
```
|
```amdasm
.text
.file "main.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z27__device_stub__convolution1PKfS0_Pfii # -- Begin function _Z27__device_stub__convolution1PKfS0_Pfii
.type _Z27__device_stub__convolution1PKfS0_Pfii,@function
_Z27__device_stub__convolution1PKfS0_Pfii: # @_Z27__device_stub__convolution1PKfS0_Pfii
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $128, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 40(%rsp), %rax
movq %rdi, (%rax)
leaq 32(%rsp), %rdi
movq %rsi, (%rdi)
leaq 24(%rsp), %rsi
movq %rdx, (%rsi)
leaq 4(%rsp), %rdx
movl %ecx, (%rdx)
movq %rsp, %rcx
movl %r8d, (%rcx)
leaq 80(%rsp), %rbx
movq %rax, (%rbx)
movq %rdi, 8(%rbx)
movq %rsi, 16(%rbx)
movq %rdx, 24(%rbx)
movq %rcx, 32(%rbx)
leaq 64(%rsp), %r14
leaq 48(%rsp), %r15
leaq 16(%rsp), %r12
leaq 8(%rsp), %r13
movq %r14, %rdi
movq %r15, %rsi
movq %r12, %rdx
movq %r13, %rcx
callq __hipPopCallConfiguration
movq (%r14), %rsi
movl 8(%r14), %edx
movq (%r15), %rcx
movl 8(%r15), %r8d
movl $_Z12convolution1PKfS0_Pfii, %edi
movq %rbx, %r9
pushq (%r13)
.cfi_adjust_cfa_offset 8
pushq (%r12)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $144, %rsp
.cfi_adjust_cfa_offset -144
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z27__device_stub__convolution1PKfS0_Pfii, .Lfunc_end0-_Z27__device_stub__convolution1PKfS0_Pfii
.cfi_endproc
# -- End function
.globl _Z27__device_stub__convolution2PKfPfii # -- Begin function _Z27__device_stub__convolution2PKfPfii
.type _Z27__device_stub__convolution2PKfPfii,@function
_Z27__device_stub__convolution2PKfPfii: # @_Z27__device_stub__convolution2PKfPfii
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $112, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 40(%rsp), %rax
movq %rdi, (%rax)
leaq 32(%rsp), %rdi
movq %rsi, (%rdi)
leaq 12(%rsp), %rsi
movl %edx, (%rsi)
leaq 8(%rsp), %rdx
movl %ecx, (%rdx)
leaq 80(%rsp), %rbx
movq %rax, (%rbx)
movq %rdi, 8(%rbx)
movq %rsi, 16(%rbx)
movq %rdx, 24(%rbx)
leaq 64(%rsp), %r14
leaq 48(%rsp), %r15
leaq 24(%rsp), %r12
leaq 16(%rsp), %r13
movq %r14, %rdi
movq %r15, %rsi
movq %r12, %rdx
movq %r13, %rcx
callq __hipPopCallConfiguration
movq (%r14), %rsi
movl 8(%r14), %edx
movq (%r15), %rcx
movl 8(%r15), %r8d
movl $_Z12convolution2PKfPfii, %edi
movq %rbx, %r9
pushq (%r13)
.cfi_adjust_cfa_offset 8
pushq (%r12)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $128, %rsp
.cfi_adjust_cfa_offset -128
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z27__device_stub__convolution2PKfPfii, .Lfunc_end1-_Z27__device_stub__convolution2PKfPfii
.cfi_endproc
# -- End function
.globl _Z27__device_stub__convolution3PKfPfii # -- Begin function _Z27__device_stub__convolution3PKfPfii
.type _Z27__device_stub__convolution3PKfPfii,@function
_Z27__device_stub__convolution3PKfPfii: # @_Z27__device_stub__convolution3PKfPfii
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $112, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 40(%rsp), %rax
movq %rdi, (%rax)
leaq 32(%rsp), %rdi
movq %rsi, (%rdi)
leaq 12(%rsp), %rsi
movl %edx, (%rsi)
leaq 8(%rsp), %rdx
movl %ecx, (%rdx)
leaq 80(%rsp), %rbx
movq %rax, (%rbx)
movq %rdi, 8(%rbx)
movq %rsi, 16(%rbx)
movq %rdx, 24(%rbx)
leaq 64(%rsp), %r14
leaq 48(%rsp), %r15
leaq 24(%rsp), %r12
leaq 16(%rsp), %r13
movq %r14, %rdi
movq %r15, %rsi
movq %r12, %rdx
movq %r13, %rcx
callq __hipPopCallConfiguration
movq (%r14), %rsi
movl 8(%r14), %edx
movq (%r15), %rcx
movl 8(%r15), %r8d
movl $_Z12convolution3PKfPfii, %edi
movq %rbx, %r9
pushq (%r13)
.cfi_adjust_cfa_offset 8
pushq (%r12)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $128, %rsp
.cfi_adjust_cfa_offset -128
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size _Z27__device_stub__convolution3PKfPfii, .Lfunc_end2-_Z27__device_stub__convolution3PKfPfii
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI3_0:
.quad 0x412e848000000000 # double 1.0E+6
.LCPI3_3:
.quad 0x41cdcd6500000000 # double 1.0E+9
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0
.LCPI3_1:
.long 1127219200 # 0x43300000
.long 1160773632 # 0x45300000
.long 0 # 0x0
.long 0 # 0x0
.LCPI3_2:
.quad 0x4330000000000000 # double 4503599627370496
.quad 0x4530000000000000 # double 1.9342813113834067E+25
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0
.LCPI3_4:
.long 0x3f800000 # float 1
.LCPI3_5:
.long 0x3c800000 # float 0.015625
.text
.globl main
.type main,@function
main: # @main
.Lfunc_begin0:
.cfi_startproc
.cfi_personality 3, __gxx_personality_v0
.cfi_lsda 3, .Lexception0
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $1576, %rsp # imm = 0x628
.cfi_def_cfa_offset 1632
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsi, %rbx
leaq 104(%rsp), %r14
movq %r14, %rdi
xorl %esi, %esi
callq hipGetDevicePropertiesR0600
movl $_ZSt4cout, %r12d
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $45, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rdi
addq %r12, %rdi
movl $10, %esi
callq _ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str.1, %esi
movl $45, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rdi
addq %r12, %rdi
movl $10, %esi
callq _ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $45, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rdi
addq %r12, %rdi
movl $10, %esi
callq _ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str.2, %esi
movl $13, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq %r14, %rdi
callq strlen
movl $_ZSt4cout, %edi
movq %r14, %rsi
movq %rax, %rdx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rdi
addq %r12, %rdi
movl $10, %esi
callq _ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str.3, %esi
movl $19, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
cvtsi2sdl 608(%r14), %xmm0
divsd .LCPI3_0(%rip), %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq %rax, %r15
movl $.L.str.4, %esi
movl $4, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq (%r15), %rax
movq -24(%rax), %rdi
addq %r15, %rdi
movl $10, %esi
callq _ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
movsbl %al, %esi
movq %r15, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str.5, %esi
movl $18, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
cvtsi2sdl 608(%r14), %xmm1
addsd %xmm1, %xmm1
movl 612(%r14), %eax
leal 7(%rax), %ecx
testl %eax, %eax
cmovnsl %eax, %ecx
sarl $3, %ecx
xorps %xmm0, %xmm0
cvtsi2sd %ecx, %xmm0
mulsd %xmm1, %xmm0
divsd .LCPI3_0(%rip), %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq %rax, %r15
movl $.L.str.6, %esi
movl $5, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq (%r15), %rax
movq -24(%rax), %rdi
addq %r15, %rdi
movl $10, %esi
callq _ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
movsbl %al, %esi
movq %r15, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str.7, %esi
movl $14, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl 388(%r14), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movq %rax, %r15
movq (%rax), %rax
movq -24(%rax), %rdi
addq %r15, %rdi
movl $10, %esi
callq _ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
movsbl %al, %esi
movq %r15, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str.8, %esi
movl $20, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl 624(%r14), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movq %rax, %r15
movq (%rax), %rax
movq -24(%rax), %rdi
addq %r15, %rdi
movl $10, %esi
callq _ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
movsbl %al, %esi
movq %r15, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str.9, %esi
movl $21, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl 304(%r14), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movq %rax, %r15
movq (%rax), %rax
movq -24(%rax), %rdi
addq %r15, %rdi
movl $10, %esi
callq _ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
movsbl %al, %esi
movq %r15, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str.10, %esi
movl $25, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq 296(%r14), %rsi
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertImEERSoT_
movq %rax, %r15
movl $.L.str.11, %esi
movl $2, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq (%r15), %rax
movq -24(%rax), %rdi
addq %r15, %rdi
movl $10, %esi
callq _ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
movsbl %al, %esi
movq %r15, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str.12, %esi
movl $31, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movsd 288(%r14), %xmm1 # xmm1 = mem[0],zero
unpcklps .LCPI3_1(%rip), %xmm1 # xmm1 = xmm1[0],mem[0],xmm1[1],mem[1]
subpd .LCPI3_2(%rip), %xmm1
movapd %xmm1, %xmm0
unpckhpd %xmm1, %xmm0 # xmm0 = xmm0[1],xmm1[1]
addsd %xmm1, %xmm0
divsd .LCPI3_3(%rip), %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq %rax, %r14
movl $.L.str.13, %esi
movl $3, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq (%r14), %rax
movq -24(%rax), %rdi
addq %r14, %rdi
movl $10, %esi
callq _ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
movsbl %al, %esi
movq %r14, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rdi
addq %r12, %rdi
movl $10, %esi
callq _ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq 8(%rbx), %rdi
callq atoi
movl %eax, %ebp
movslq %eax, %r14
leaq 56(%rsp), %rdx
movl $1065353216, (%rdx) # imm = 0x3F800000
leaq 80(%rsp), %r15
leaq 32(%rsp), %rcx
movq %r15, %rdi
movq %r14, %rsi
callq _ZNSt6vectorIfSaIfEEC2EmRKfRKS0_
movq (%r15), %rax
movq 8(%r15), %rcx
cmpq %rcx, %rax
je .LBB3_3
# %bb.1: # %.lr.ph.i.preheader
xorpd %xmm0, %xmm0
movss .LCPI3_4(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero
.LBB3_2: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
movss %xmm0, (%rax)
addss %xmm1, %xmm0
addq $4, %rax
cmpq %rcx, %rax
jne .LBB3_2
.LBB3_3: # %_ZSt4iotaIN9__gnu_cxx17__normal_iteratorIPfSt6vectorIfSaIfEEEEfEvT_S7_T0_.exit
leaq (,%r14,4), %r15
.Ltmp0:
leaq 24(%rsp), %rdi
movq %r15, %rsi
callq hipMalloc
.Ltmp1:
# %bb.4:
movq 24(%rsp), %rdi
movq 80(%rsp), %rsi
.Ltmp2:
movq %r15, %rdx
movl $1, %ecx
callq hipMemcpy
.Ltmp3:
# %bb.5:
movupd .Lconstinit(%rip), %xmm0
leaq 32(%rsp), %rsi
movapd %xmm0, (%rsi)
movl $1065353216, 16(%rsi) # imm = 0x3F800000
.Ltmp5:
leaq 56(%rsp), %rdi
leaq 16(%rsp), %rcx
movl $5, %edx
callq _ZNSt6vectorIfSaIfEEC2ESt16initializer_listIfERKS0_
.Ltmp6:
# %bb.6:
movq 56(%rsp), %rsi
movq 64(%rsp), %r12
subq %rsi, %r12
movq %r12, %rdx
shlq $30, %rdx
sarq $30, %rdx
.Ltmp8:
movl $c_M, %edi
xorl %ecx, %ecx
movl $1, %r8d
callq hipMemcpyToSymbol
.Ltmp9:
# %bb.7: # %_Z17hipMemcpyToSymbolIA5_fE10hipError_tRKT_PKvmm13hipMemcpyKind.exit
.Ltmp11:
leaq 16(%rsp), %rdi
movq %r15, %rsi
callq hipMalloc
.Ltmp12:
# %bb.8:
xorps %xmm0, %xmm0
cvtsi2ss %ebp, %xmm0
shrq $2, %r12
mulss .LCPI3_5(%rip), %xmm0
callq ceilf@PLT
cvttss2si %xmm0, %r13d
movq 16(%rbx), %rdi
callq atoi
cmpl $2, %eax
je .LBB3_13
# %bb.9:
cmpl $1, %eax
jne .LBB3_16
# %bb.10:
movl %r13d, %edi
btsq $32, %rdi
.Ltmp18:
movabsq $4294967360, %rdx # imm = 0x100000040
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
.Ltmp19:
# %bb.11:
testl %eax, %eax
jne .LBB3_20
# %bb.12:
movq 24(%rsp), %rdi
movq 16(%rsp), %rsi
.Ltmp20:
movl %r12d, %edx
movl %ebp, %ecx
callq _Z27__device_stub__convolution2PKfPfii
.Ltmp21:
jmp .LBB3_20
.LBB3_13:
movl %r13d, %edi
btsq $32, %rdi
.Ltmp14:
movabsq $4294967360, %rdx # imm = 0x100000040
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
.Ltmp15:
# %bb.14:
testl %eax, %eax
jne .LBB3_20
# %bb.15:
movq 24(%rsp), %rdi
movq 16(%rsp), %rsi
.Ltmp16:
movl %r12d, %edx
movl %ebp, %ecx
callq _Z27__device_stub__convolution3PKfPfii
.Ltmp17:
jmp .LBB3_20
.LBB3_16:
.Ltmp22:
movl $_ZSt4cout, %ebx
movl $_ZSt4cout, %edi
movl $.L.str.14, %esi
movl $13, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp23:
# %bb.17: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit
movq _ZSt4cout(%rip), %rax
addq -24(%rax), %rbx
.Ltmp24:
movq %rbx, %rdi
movl $10, %esi
callq _ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
.Ltmp25:
# %bb.18: # %.noexc
.Ltmp26:
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
.Ltmp27:
# %bb.19: # %.noexc61
.Ltmp28:
movq %rax, %rdi
callq _ZNSo5flushEv
.Ltmp29:
.LBB3_20: # %_ZNSolsEPFRSoS_E.exit
.Ltmp31:
leaq 32(%rsp), %rdi
leaq 15(%rsp), %rdx
movq %r14, %rsi
callq _ZNSt6vectorIfSaIfEEC2EmRKS0_
.Ltmp32:
# %bb.21:
movq 32(%rsp), %rdi
movq 16(%rsp), %rsi
.Ltmp34:
movq %r15, %rdx
movl $2, %ecx
callq hipMemcpy
.Ltmp35:
# %bb.22:
movq 24(%rsp), %rdi
.Ltmp36:
callq hipFree
.Ltmp37:
# %bb.23:
movq 16(%rsp), %rdi
.Ltmp38:
callq hipFree
.Ltmp39:
# %bb.24:
.Ltmp40:
movl $_ZSt4cout, %ebx
movl $_ZSt4cout, %edi
movl $.L.str.15, %esi
movl $10, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp41:
# %bb.25: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit49
movq _ZSt4cout(%rip), %rax
addq -24(%rax), %rbx
.Ltmp42:
movq %rbx, %rdi
movl $10, %esi
callq _ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
.Ltmp43:
# %bb.26: # %.noexc63
.Ltmp44:
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
.Ltmp45:
# %bb.27: # %.noexc64
.Ltmp46:
movq %rax, %rdi
callq _ZNSo5flushEv
.Ltmp47:
# %bb.28: # %_ZNSolsEPFRSoS_E.exit50
movq 32(%rsp), %rdi
testq %rdi, %rdi
je .LBB3_30
# %bb.29:
callq _ZdlPv
.LBB3_30: # %_ZNSt6vectorIfSaIfEED2Ev.exit
movq 56(%rsp), %rdi
testq %rdi, %rdi
je .LBB3_32
# %bb.31:
callq _ZdlPv
.LBB3_32: # %_ZNSt6vectorIfSaIfEED2Ev.exit52
movq 80(%rsp), %rdi
testq %rdi, %rdi
je .LBB3_34
# %bb.33:
callq _ZdlPv
.LBB3_34: # %_ZNSt6vectorIfSaIfEED2Ev.exit54
xorl %eax, %eax
addq $1576, %rsp # imm = 0x628
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB3_35:
.cfi_def_cfa_offset 1632
.Ltmp33:
jmp .LBB3_38
.LBB3_36:
.Ltmp13:
jmp .LBB3_38
.LBB3_37:
.Ltmp10:
jmp .LBB3_38
.LBB3_39:
.Ltmp7:
jmp .LBB3_41
.LBB3_40:
.Ltmp4:
.LBB3_41:
movq %rax, %rbx
jmp .LBB3_47
.LBB3_42:
.Ltmp30:
.LBB3_38:
movq %rax, %rbx
jmp .LBB3_45
.LBB3_43:
.Ltmp48:
movq %rax, %rbx
movq 32(%rsp), %rdi
testq %rdi, %rdi
je .LBB3_45
# %bb.44:
callq _ZdlPv
.LBB3_45:
movq 56(%rsp), %rdi
testq %rdi, %rdi
je .LBB3_47
# %bb.46:
callq _ZdlPv
.LBB3_47:
movq 80(%rsp), %rdi
testq %rdi, %rdi
je .LBB3_49
# %bb.48:
callq _ZdlPv
.LBB3_49: # %_ZNSt6vectorIfSaIfEED2Ev.exit60
movq %rbx, %rdi
callq _Unwind_Resume@PLT
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
.section .gcc_except_table,"a",@progbits
.p2align 2, 0x0
GCC_except_table3:
.Lexception0:
.byte 255 # @LPStart Encoding = omit
.byte 255 # @TType Encoding = omit
.byte 1 # Call site Encoding = uleb128
.uleb128 .Lcst_end0-.Lcst_begin0
.Lcst_begin0:
.uleb128 .Lfunc_begin0-.Lfunc_begin0 # >> Call Site 1 <<
.uleb128 .Ltmp0-.Lfunc_begin0 # Call between .Lfunc_begin0 and .Ltmp0
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp0-.Lfunc_begin0 # >> Call Site 2 <<
.uleb128 .Ltmp3-.Ltmp0 # Call between .Ltmp0 and .Ltmp3
.uleb128 .Ltmp4-.Lfunc_begin0 # jumps to .Ltmp4
.byte 0 # On action: cleanup
.uleb128 .Ltmp5-.Lfunc_begin0 # >> Call Site 3 <<
.uleb128 .Ltmp6-.Ltmp5 # Call between .Ltmp5 and .Ltmp6
.uleb128 .Ltmp7-.Lfunc_begin0 # jumps to .Ltmp7
.byte 0 # On action: cleanup
.uleb128 .Ltmp8-.Lfunc_begin0 # >> Call Site 4 <<
.uleb128 .Ltmp9-.Ltmp8 # Call between .Ltmp8 and .Ltmp9
.uleb128 .Ltmp10-.Lfunc_begin0 # jumps to .Ltmp10
.byte 0 # On action: cleanup
.uleb128 .Ltmp11-.Lfunc_begin0 # >> Call Site 5 <<
.uleb128 .Ltmp12-.Ltmp11 # Call between .Ltmp11 and .Ltmp12
.uleb128 .Ltmp13-.Lfunc_begin0 # jumps to .Ltmp13
.byte 0 # On action: cleanup
.uleb128 .Ltmp12-.Lfunc_begin0 # >> Call Site 6 <<
.uleb128 .Ltmp18-.Ltmp12 # Call between .Ltmp12 and .Ltmp18
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp18-.Lfunc_begin0 # >> Call Site 7 <<
.uleb128 .Ltmp29-.Ltmp18 # Call between .Ltmp18 and .Ltmp29
.uleb128 .Ltmp30-.Lfunc_begin0 # jumps to .Ltmp30
.byte 0 # On action: cleanup
.uleb128 .Ltmp31-.Lfunc_begin0 # >> Call Site 8 <<
.uleb128 .Ltmp32-.Ltmp31 # Call between .Ltmp31 and .Ltmp32
.uleb128 .Ltmp33-.Lfunc_begin0 # jumps to .Ltmp33
.byte 0 # On action: cleanup
.uleb128 .Ltmp34-.Lfunc_begin0 # >> Call Site 9 <<
.uleb128 .Ltmp47-.Ltmp34 # Call between .Ltmp34 and .Ltmp47
.uleb128 .Ltmp48-.Lfunc_begin0 # jumps to .Ltmp48
.byte 0 # On action: cleanup
.uleb128 .Ltmp47-.Lfunc_begin0 # >> Call Site 10 <<
.uleb128 .Lfunc_end3-.Ltmp47 # Call between .Ltmp47 and .Lfunc_end3
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.Lcst_end0:
.p2align 2, 0x0
# -- End function
.section .text._ZNSt6vectorIfSaIfEEC2EmRKfRKS0_,"axG",@progbits,_ZNSt6vectorIfSaIfEEC2EmRKfRKS0_,comdat
.weak _ZNSt6vectorIfSaIfEEC2EmRKfRKS0_ # -- Begin function _ZNSt6vectorIfSaIfEEC2EmRKfRKS0_
.p2align 1, 0x90
.type _ZNSt6vectorIfSaIfEEC2EmRKfRKS0_,@function
_ZNSt6vectorIfSaIfEEC2EmRKfRKS0_: # @_ZNSt6vectorIfSaIfEEC2EmRKfRKS0_
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
pushq %rax
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rsi, %rax
shrq $61, %rax
jne .LBB4_6
# %bb.1: # %_ZNSt6vectorIfSaIfEE17_S_check_init_lenEmRKS0_.exit
movq %rsi, %r14
movq %rdi, %rbx
xorps %xmm0, %xmm0
movups %xmm0, (%rdi)
movq $0, 16(%rdi)
testq %rsi, %rsi
je .LBB4_2
# %bb.3:
movq %rdx, %r15
xorl %r12d, %r12d
movq %rbx, %rdi
movq %r14, %rsi
xorl %edx, %edx
callq _ZNSt15__new_allocatorIfE8allocateEmPKv
movq %rax, (%rbx)
leaq (%rax,%r14,4), %rcx
movq %rcx, 16(%rbx)
movss (%r15), %xmm0 # xmm0 = mem[0],zero,zero,zero
shlq $2, %r14
.LBB4_4: # %.lr.ph.i.i.i.i.i.i.i.i
# =>This Inner Loop Header: Depth=1
movss %xmm0, (%rax,%r12)
addq $4, %r12
cmpq %r12, %r14
jne .LBB4_4
jmp .LBB4_5
.LBB4_2: # %_ZNSt12_Vector_baseIfSaIfEEC2EmRKS0_.exit.thread
movups %xmm0, (%rbx)
movq $0, 16(%rbx)
xorl %ecx, %ecx
.LBB4_5: # %.loopexit
movq %rcx, 8(%rbx)
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB4_6:
.cfi_def_cfa_offset 48
movl $.L.str.16, %edi
callq _ZSt20__throw_length_errorPKc
.Lfunc_end4:
.size _ZNSt6vectorIfSaIfEEC2EmRKfRKS0_, .Lfunc_end4-_ZNSt6vectorIfSaIfEEC2EmRKfRKS0_
.cfi_endproc
# -- End function
.section .text._ZNSt6vectorIfSaIfEEC2ESt16initializer_listIfERKS0_,"axG",@progbits,_ZNSt6vectorIfSaIfEEC2ESt16initializer_listIfERKS0_,comdat
.weak _ZNSt6vectorIfSaIfEEC2ESt16initializer_listIfERKS0_ # -- Begin function _ZNSt6vectorIfSaIfEEC2ESt16initializer_listIfERKS0_
.p2align 1, 0x90
.type _ZNSt6vectorIfSaIfEEC2ESt16initializer_listIfERKS0_,@function
_ZNSt6vectorIfSaIfEEC2ESt16initializer_listIfERKS0_: # @_ZNSt6vectorIfSaIfEEC2ESt16initializer_listIfERKS0_
.Lfunc_begin1:
.cfi_startproc
.cfi_personality 3, __gxx_personality_v0
.cfi_lsda 3, .Lexception1
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
pushq %rax
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movq %rdi, %rbx
xorps %xmm0, %xmm0
movups %xmm0, (%rdi)
movq $0, 16(%rdi)
leaq (%rsi,%rdx,4), %rdx
.Ltmp49:
callq _ZNSt6vectorIfSaIfEE19_M_range_initializeIPKfEEvT_S5_St20forward_iterator_tag
.Ltmp50:
# %bb.1:
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.LBB5_2:
.cfi_def_cfa_offset 32
.Ltmp51:
movq %rax, %r14
movq (%rbx), %rdi
testq %rdi, %rdi
je .LBB5_4
# %bb.3:
callq _ZdlPv
.LBB5_4: # %_ZNSt12_Vector_baseIfSaIfEED2Ev.exit
movq %r14, %rdi
callq _Unwind_Resume@PLT
.Lfunc_end5:
.size _ZNSt6vectorIfSaIfEEC2ESt16initializer_listIfERKS0_, .Lfunc_end5-_ZNSt6vectorIfSaIfEEC2ESt16initializer_listIfERKS0_
.cfi_endproc
.section .gcc_except_table._ZNSt6vectorIfSaIfEEC2ESt16initializer_listIfERKS0_,"aG",@progbits,_ZNSt6vectorIfSaIfEEC2ESt16initializer_listIfERKS0_,comdat
.p2align 2, 0x0
GCC_except_table5:
.Lexception1:
.byte 255 # @LPStart Encoding = omit
.byte 255 # @TType Encoding = omit
.byte 1 # Call site Encoding = uleb128
.uleb128 .Lcst_end1-.Lcst_begin1
.Lcst_begin1:
.uleb128 .Ltmp49-.Lfunc_begin1 # >> Call Site 1 <<
.uleb128 .Ltmp50-.Ltmp49 # Call between .Ltmp49 and .Ltmp50
.uleb128 .Ltmp51-.Lfunc_begin1 # jumps to .Ltmp51
.byte 0 # On action: cleanup
.uleb128 .Ltmp50-.Lfunc_begin1 # >> Call Site 2 <<
.uleb128 .Lfunc_end5-.Ltmp50 # Call between .Ltmp50 and .Lfunc_end5
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.Lcst_end1:
.p2align 2, 0x0
# -- End function
.section .text._ZNSt6vectorIfSaIfEEC2EmRKS0_,"axG",@progbits,_ZNSt6vectorIfSaIfEEC2EmRKS0_,comdat
.weak _ZNSt6vectorIfSaIfEEC2EmRKS0_ # -- Begin function _ZNSt6vectorIfSaIfEEC2EmRKS0_
.p2align 1, 0x90
.type _ZNSt6vectorIfSaIfEEC2EmRKS0_,@function
_ZNSt6vectorIfSaIfEEC2EmRKS0_: # @_ZNSt6vectorIfSaIfEEC2EmRKS0_
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rsi, %rax
shrq $61, %rax
jne .LBB6_7
# %bb.1: # %_ZNSt6vectorIfSaIfEE17_S_check_init_lenEmRKS0_.exit
movq %rsi, %r14
movq %rdi, %rbx
xorps %xmm0, %xmm0
movups %xmm0, (%rdi)
movq $0, 16(%rdi)
testq %rsi, %rsi
je .LBB6_2
# %bb.3:
movq %rbx, %rdi
movq %r14, %rsi
xorl %edx, %edx
callq _ZNSt15__new_allocatorIfE8allocateEmPKv
movq %rax, (%rbx)
leaq (%rax,%r14,4), %r15
movq %r15, 16(%rbx)
movl $0, (%rax)
addq $4, %rax
cmpq $1, %r14
jne .LBB6_5
# %bb.4:
movq %rax, %r15
jmp .LBB6_6
.LBB6_2: # %_ZNSt12_Vector_baseIfSaIfEEC2EmRKS0_.exit.thread
movups %xmm0, (%rbx)
movq $0, 16(%rbx)
xorl %r15d, %r15d
jmp .LBB6_6
.LBB6_5: # %_ZSt6fill_nIPfmfET_S1_T0_RKT1_.exit.loopexit.i.i.i.i
leaq -4(,%r14,4), %rdx
movq %rax, %rdi
xorl %esi, %esi
callq memset@PLT
.LBB6_6:
movq %r15, 8(%rbx)
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB6_7:
.cfi_def_cfa_offset 32
movl $.L.str.16, %edi
callq _ZSt20__throw_length_errorPKc
.Lfunc_end6:
.size _ZNSt6vectorIfSaIfEEC2EmRKS0_, .Lfunc_end6-_ZNSt6vectorIfSaIfEEC2EmRKS0_
.cfi_endproc
# -- End function
.section .text._ZNSt15__new_allocatorIfE8allocateEmPKv,"axG",@progbits,_ZNSt15__new_allocatorIfE8allocateEmPKv,comdat
.weak _ZNSt15__new_allocatorIfE8allocateEmPKv # -- Begin function _ZNSt15__new_allocatorIfE8allocateEmPKv
.p2align 1, 0x90
.type _ZNSt15__new_allocatorIfE8allocateEmPKv,@function
_ZNSt15__new_allocatorIfE8allocateEmPKv: # @_ZNSt15__new_allocatorIfE8allocateEmPKv
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
movq %rsi, %rax
shrq $61, %rax
jne .LBB7_1
# %bb.3:
shlq $2, %rsi
movq %rsi, %rdi
popq %rax
.cfi_def_cfa_offset 8
jmp _Znwm # TAILCALL
.LBB7_1:
.cfi_def_cfa_offset 16
shrq $62, %rsi
je .LBB7_2
# %bb.4:
callq _ZSt28__throw_bad_array_new_lengthv
.LBB7_2:
callq _ZSt17__throw_bad_allocv
.Lfunc_end7:
.size _ZNSt15__new_allocatorIfE8allocateEmPKv, .Lfunc_end7-_ZNSt15__new_allocatorIfE8allocateEmPKv
.cfi_endproc
# -- End function
.section .text._ZNSt6vectorIfSaIfEE19_M_range_initializeIPKfEEvT_S5_St20forward_iterator_tag,"axG",@progbits,_ZNSt6vectorIfSaIfEE19_M_range_initializeIPKfEEvT_S5_St20forward_iterator_tag,comdat
.weak _ZNSt6vectorIfSaIfEE19_M_range_initializeIPKfEEvT_S5_St20forward_iterator_tag # -- Begin function _ZNSt6vectorIfSaIfEE19_M_range_initializeIPKfEEvT_S5_St20forward_iterator_tag
.p2align 1, 0x90
.type _ZNSt6vectorIfSaIfEE19_M_range_initializeIPKfEEvT_S5_St20forward_iterator_tag,@function
_ZNSt6vectorIfSaIfEE19_M_range_initializeIPKfEEvT_S5_St20forward_iterator_tag: # @_ZNSt6vectorIfSaIfEE19_M_range_initializeIPKfEEvT_S5_St20forward_iterator_tag
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rdx, %r14
subq %rsi, %r14
movq %r14, %r13
sarq $2, %r13
movq %r13, %rax
shrq $61, %rax
jne .LBB8_9
# %bb.1: # %_ZNSt6vectorIfSaIfEE17_S_check_init_lenEmRKS0_.exit
movq %rsi, %r15
movq %rdi, %rbx
cmpq %rsi, %rdx
je .LBB8_2
# %bb.3:
movq %rbx, %rdi
movq %r13, %rsi
xorl %edx, %edx
callq _ZNSt15__new_allocatorIfE8allocateEmPKv
movq %rax, %r12
jmp .LBB8_4
.LBB8_2:
xorl %r12d, %r12d
.LBB8_4: # %_ZNSt12_Vector_baseIfSaIfEE11_M_allocateEm.exit
movq %r12, (%rbx)
leaq (%r12,%r13,4), %rax
movq %rax, 16(%rbx)
cmpq $5, %r14
jl .LBB8_6
# %bb.5:
movq %r12, %rdi
movq %r15, %rsi
movq %r14, %rdx
callq memmove@PLT
.LBB8_8: # %_ZSt22__uninitialized_copy_aIPKfPffET0_T_S4_S3_RSaIT1_E.exit
addq %r14, %r12
movq %r12, 8(%rbx)
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB8_6:
.cfi_def_cfa_offset 48
cmpq $4, %r14
jne .LBB8_8
# %bb.7:
movss (%r15), %xmm0 # xmm0 = mem[0],zero,zero,zero
movss %xmm0, (%r12)
jmp .LBB8_8
.LBB8_9:
movl $.L.str.16, %edi
callq _ZSt20__throw_length_errorPKc
.Lfunc_end8:
.size _ZNSt6vectorIfSaIfEE19_M_range_initializeIPKfEEvT_S5_St20forward_iterator_tag, .Lfunc_end8-_ZNSt6vectorIfSaIfEE19_M_range_initializeIPKfEEvT_S5_St20forward_iterator_tag
.cfi_endproc
# -- End function
.text
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
movq __hip_gpubin_handle(%rip), %rbx
testq %rbx, %rbx
jne .LBB9_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, %rbx
movq %rax, __hip_gpubin_handle(%rip)
.LBB9_2:
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12convolution1PKfS0_Pfii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12convolution2PKfPfii, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12convolution3PKfPfii, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $0, 8(%rsp)
movl $1, (%rsp)
movl $c_M, %esi
movl $.L__unnamed_4, %edx
movl $.L__unnamed_4, %ecx
movl $20, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
callq __hipRegisterVar
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end9:
.size __hip_module_ctor, .Lfunc_end9-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB10_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB10_2:
retq
.Lfunc_end10:
.size __hip_module_dtor, .Lfunc_end10-__hip_module_dtor
.cfi_endproc
# -- End function
.type c_M,@object # @c_M
.local c_M
.comm c_M,20,16
.type _Z12convolution1PKfS0_Pfii,@object # @_Z12convolution1PKfS0_Pfii
.section .rodata,"a",@progbits
.globl _Z12convolution1PKfS0_Pfii
.p2align 3, 0x0
_Z12convolution1PKfS0_Pfii:
.quad _Z27__device_stub__convolution1PKfS0_Pfii
.size _Z12convolution1PKfS0_Pfii, 8
.type _Z12convolution2PKfPfii,@object # @_Z12convolution2PKfPfii
.globl _Z12convolution2PKfPfii
.p2align 3, 0x0
_Z12convolution2PKfPfii:
.quad _Z27__device_stub__convolution2PKfPfii
.size _Z12convolution2PKfPfii, 8
.type _Z12convolution3PKfPfii,@object # @_Z12convolution3PKfPfii
.globl _Z12convolution3PKfPfii
.p2align 3, 0x0
_Z12convolution3PKfPfii:
.quad _Z27__device_stub__convolution3PKfPfii
.size _Z12convolution3PKfPfii, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "---------------------------------------------"
.size .L.str, 46
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz " GPU PROPERTIES "
.size .L.str.1, 46
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Device Name: "
.size .L.str.2, 14
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Memory Clock Rate: "
.size .L.str.3, 20
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz " GHz"
.size .L.str.4, 5
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "Memory Bandwidth: "
.size .L.str.5, 19
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz " GB/s"
.size .L.str.6, 6
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "Number of SM: "
.size .L.str.7, 15
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "Max Threads per SM: "
.size .L.str.8, 21
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "Registers per Block: "
.size .L.str.9, 22
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "Shared Memory per Block: "
.size .L.str.10, 26
.type .L.str.11,@object # @.str.11
.L.str.11:
.asciz " B"
.size .L.str.11, 3
.type .L.str.12,@object # @.str.12
.L.str.12:
.asciz "Total Global Memory per Block: "
.size .L.str.12, 32
.type .L.str.13,@object # @.str.13
.L.str.13:
.asciz " GB"
.size .L.str.13, 4
.type .Lconstinit,@object # @constinit
.section .rodata,"a",@progbits
.p2align 2, 0x0
.Lconstinit:
.long 0x3f800000 # float 1
.long 0x3f800000 # float 1
.long 0x40000000 # float 2
.long 0x3f800000 # float 1
.long 0x3f800000 # float 1
.size .Lconstinit, 20
.type .L.str.14,@object # @.str.14
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.14:
.asciz "Wrong inputs!"
.size .L.str.14, 14
.type .L.str.15,@object # @.str.15
.L.str.15:
.asciz "Closing..."
.size .L.str.15, 11
.type .L.str.16,@object # @.str.16
.L.str.16:
.asciz "cannot create std::vector larger than max_size()"
.size .L.str.16, 49
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z12convolution1PKfS0_Pfii"
.size .L__unnamed_1, 27
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z12convolution2PKfPfii"
.size .L__unnamed_2, 24
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z12convolution3PKfPfii"
.size .L__unnamed_3, 24
.type .L__unnamed_4,@object # @3
.L__unnamed_4:
.asciz "c_M"
.size .L__unnamed_4, 4
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z27__device_stub__convolution1PKfS0_Pfii
.addrsig_sym _Z27__device_stub__convolution2PKfPfii
.addrsig_sym _Z27__device_stub__convolution3PKfPfii
.addrsig_sym __gxx_personality_v0
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Unwind_Resume
.addrsig_sym c_M
.addrsig_sym _Z12convolution1PKfS0_Pfii
.addrsig_sym _Z12convolution2PKfPfii
.addrsig_sym _Z12convolution3PKfPfii
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
```
| 11,431 | 18,586 |
398 |
Convert the following CUDA device assembly code to AMD device assembly:
```cudaasm
code for sm_80
Function : _Z9play_gameiiPcS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ;
S2R R0, SR_CTAID.X ;
ULDC.64 UR4, c[0x0][0x160] ;
UIMAD UR4, UR5, UR4, URZ ;
S2R R3, SR_TID.X ;
IMAD R0, R0, c[0x0][0x0], R3 ;
ISETP.GE.AND P0, PT, R0, UR4, PT ;
@P0 EXIT ;
IABS R5, c[0x0][0x164] ;
ULDC.64 UR4, c[0x0][0x118] ;
BSSY B1, 0xe70 ;
IMAD.MOV.U32 R9, RZ, RZ, RZ ;
I2F.RP R4, R5 ;
MUFU.RCP R4, R4 ;
IADD3 R2, R4, 0xffffffe, RZ ;
F2I.FTZ.U32.TRUNC.NTZ R3, R2 ;
IMAD.MOV.U32 R2, RZ, RZ, RZ ;
IMAD.MOV R6, RZ, RZ, -R3 ;
IMAD R7, R6, R5, RZ ;
IABS R6, R0 ;
IMAD.HI.U32 R3, R3, R7, R2 ;
LOP3.LUT R2, R0, c[0x0][0x164], RZ, 0x3c, !PT ;
ISETP.GE.AND P2, PT, R2, RZ, PT ;
IMAD.HI.U32 R3, R3, R6, RZ ;
LOP3.LUT R2, RZ, c[0x0][0x164], RZ, 0x33, !PT ;
IMAD.MOV R4, RZ, RZ, -R3 ;
IMAD R4, R5, R4, R6 ;
ISETP.GT.U32.AND P1, PT, R5, R4, PT ;
@!P1 IMAD.IADD R4, R4, 0x1, -R5 ;
@!P1 IADD3 R3, R3, 0x1, RZ ;
ISETP.GE.U32.AND P0, PT, R4, R5, PT ;
@P0 IADD3 R3, R3, 0x1, RZ ;
ISETP.NE.AND P0, PT, RZ, c[0x0][0x164], PT ;
@!P2 IMAD.MOV R3, RZ, RZ, -R3 ;
SEL R3, R2, R3, !P0 ;
IADD3 R11, R3.reuse, -0x1, RZ ;
IADD3 R8, R3, 0x1, RZ ;
ISETP.GT.U32.AND P1, PT, R11, R8, PT ;
@P1 BRA 0xe60 ;
ISETP.GE.AND P2, PT, R0, RZ, PT ;
IMAD.IADD R3, R4, 0x1, -R5 ;
ISETP.GT.U32.AND P1, PT, R5, R4.reuse, PT ;
IMAD.MOV.U32 R9, RZ, RZ, RZ ;
SHF.R.S32.HI R10, RZ, 0x1f, R11 ;
SEL R3, R3, R4, !P1 ;
SHF.R.S32.HI R15, RZ, 0x1f, R8 ;
@!P2 IMAD.MOV R3, RZ, RZ, -R3 ;
SEL R2, R2, R3, !P0 ;
IADD3 R12, R2.reuse, 0x1, RZ ;
IADD3 R13, R2, -0x1, RZ ;
SHF.R.S32.HI R14, RZ, 0x1f, R12 ;
SHF.R.S32.HI R17, RZ, 0x1f, R13 ;
ISETP.GT.U32.AND P0, PT, R13, R12, PT ;
BSSY B0, 0xe10 ;
@P0 BRA 0xe00 ;
ISETP.GE.U32.AND P1, PT, R13, R12, PT ;
BSSY B2, 0x580 ;
SHF.R.S32.HI R2, RZ, 0x1f, R11 ;
IMAD.MOV.U32 R21, RZ, RZ, R13 ;
ISETP.GE.U32.AND.EX P1, PT, R17, R14, PT, P1 ;
IMAD.MOV.U32 R19, RZ, RZ, R17 ;
LOP3.LUT R2, R2, c[0x0][0x160], RZ, 0xc0, !PT ;
PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ;
IMAD.IADD R2, R2, 0x1, R11 ;
ISETP.NE.AND P2, PT, R2, c[0x0][0x160], PT ;
SEL R16, R2, RZ, P2 ;
@!P1 BRA 0x570 ;
SHF.R.S32.HI R2, RZ, 0x1f, R21 ;
BSSY B3, 0x560 ;
LOP3.LUT R2, R2, c[0x0][0x164], RZ, 0xc0, !PT ;
IMAD.IADD R2, R2, 0x1, R21 ;
IADD3 R21, P2, R21, 0x1, RZ ;
ISETP.NE.AND P0, PT, R2, c[0x0][0x164], PT ;
SEL R3, R2, RZ, P0 ;
PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ;
IMAD R3, R16, c[0x0][0x164], R3 ;
ISETP.NE.AND P1, PT, R3, R0, PT ;
@!P1 BRA 0x550 ;
IADD3 R2, P1, R3, c[0x0][0x168], RZ ;
LEA.HI.X.SX32 R3, R3, c[0x0][0x16c], 0x1, P1 ;
LDG.E.U8 R2, [R2.64] ;
IADD3 R4, R9, 0x1, RZ ;
ISETP.NE.AND P1, PT, R2, 0x58, PT ;
@P1 IMAD.MOV R4, RZ, RZ, R9 ;
IMAD.MOV.U32 R9, RZ, RZ, R4 ;
BSYNC B3 ;
IMAD.X R19, RZ, RZ, R19, P2 ;
BSYNC B2 ;
IADD3 R2, P3, R12.reuse, -R21.reuse, RZ ;
BSSY B2, 0xa40 ;
ISETP.GT.U32.AND P1, PT, R12, R21, PT ;
ISETP.LE.U32.AND P2, PT, R2, 0x2, PT ;
IMAD.X R2, R14.reuse, 0x1, ~R19, P3 ;
ISETP.GT.U32.AND.EX P1, PT, R14, R19, PT, P1 ;
ISETP.LE.U32.OR.EX P1, PT, R2, RZ, !P1, P2 ;
@P1 BRA 0xa30 ;
IADD3 R20, P1, R12, -0x2, RZ ;
PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ;
IADD3.X R18, R14, -0x1, RZ, P1, !PT ;
SHF.R.S32.HI R2, RZ, 0x1f, R21 ;
IADD3 R5, R21, 0x1, RZ ;
LOP3.LUT R2, R2, c[0x0][0x164], RZ, 0xc0, !PT ;
SHF.R.S32.HI R3, RZ, 0x1f, R5 ;
IADD3 R7, R21, 0x2, RZ ;
IMAD.IADD R2, R2, 0x1, R21 ;
LOP3.LUT R4, R3, c[0x0][0x164], RZ, 0xc0, !PT ;
IADD3 R23, R21, 0x3, RZ ;
ISETP.NE.AND P1, PT, R2, c[0x0][0x164], PT ;
IMAD.IADD R4, R4, 0x1, R5 ;
SEL R3, R2, RZ, P1 ;
SHF.R.S32.HI R2, RZ, 0x1f, R7 ;
ISETP.NE.AND P2, PT, R4, c[0x0][0x164], PT ;
IMAD R3, R16, c[0x0][0x164], R3 ;
LOP3.LUT R2, R2, c[0x0][0x164], RZ, 0xc0, !PT ;
SEL R5, R4, RZ, P2 ;
ISETP.NE.AND P1, PT, R3, R0, PT ;
IMAD.IADD R4, R2, 0x1, R7 ;
SHF.R.S32.HI R2, RZ, 0x1f, R23 ;
IMAD R5, R16, c[0x0][0x164], R5 ;
ISETP.NE.AND P2, PT, R4, c[0x0][0x164], PT ;
LOP3.LUT R6, R2, c[0x0][0x164], RZ, 0xc0, !PT ;
ISETP.NE.AND P3, PT, R5, R0, PT ;
SEL R7, R4, RZ, P2 ;
IMAD.IADD R6, R6, 0x1, R23 ;
@P1 IADD3 R2, P4, R3, c[0x0][0x168], RZ ;
IMAD R23, R16, c[0x0][0x164], R7 ;
@P1 LEA.HI.X.SX32 R3, R3, c[0x0][0x16c], 0x1, P4 ;
ISETP.NE.AND P2, PT, R6.reuse, c[0x0][0x164], PT ;
ISETP.NE.AND P4, PT, R23, R0, PT ;
@P1 LDG.E.U8 R22, [R2.64] ;
@P3 IADD3 R4, P5, R5.reuse, c[0x0][0x168], RZ ;
SEL R7, R6, RZ, P2 ;
@P3 LEA.HI.X.SX32 R5, R5, c[0x0][0x16c], 0x1, P5 ;
IMAD R25, R16, c[0x0][0x164], R7 ;
@P3 LDG.E.U8 R4, [R4.64] ;
@P4 IADD3 R6, P5, R23, c[0x0][0x168], RZ ;
ISETP.NE.AND P2, PT, R25, R0, PT ;
@P4 LEA.HI.X.SX32 R7, R23, c[0x0][0x16c], 0x1, P5 ;
@P4 LDG.E.U8 R6, [R6.64] ;
@P2 IADD3 R2, P5, R25, c[0x0][0x168], RZ ;
@P2 LEA.HI.X.SX32 R3, R25, c[0x0][0x16c], 0x1, P5 ;
@P2 LDG.E.U8 R2, [R2.64] ;
ISETP.NE.AND P6, PT, R22, 0x58, P1 ;
@P1 IADD3 R22, R9, 0x1, RZ ;
ISETP.NE.AND P5, PT, R4, 0x58, P3 ;
@P6 IMAD.MOV R22, RZ, RZ, R9 ;
@P1 IMAD.MOV.U32 R9, RZ, RZ, R22 ;
ISETP.NE.AND P1, PT, R6, 0x58, P4 ;
@P3 IADD3 R4, R9, 0x1, RZ ;
@P5 IMAD.MOV R4, RZ, RZ, R9 ;
@P3 IMAD.MOV.U32 R9, RZ, RZ, R4 ;
@P4 IADD3 R4, R9, 0x1, RZ ;
@P1 IMAD.MOV R4, RZ, RZ, R9 ;
IADD3 R21, P1, R21, 0x4, RZ ;
ISETP.NE.AND P3, PT, R2, 0x58, P2 ;
@P4 IMAD.MOV.U32 R9, RZ, RZ, R4 ;
IMAD.X R19, RZ, RZ, R19, P1 ;
ISETP.GE.U32.AND P1, PT, R21, R20, PT ;
@P2 IADD3 R2, R9, 0x1, RZ ;
ISETP.GE.U32.AND.EX P1, PT, R19, R18, PT, P1 ;
@P3 IMAD.MOV R2, RZ, RZ, R9 ;
@P2 IMAD.MOV.U32 R9, RZ, RZ, R2 ;
@!P1 BRA 0x630 ;
BSYNC B2 ;
IADD3 R2, P3, R12.reuse, -R21.reuse, RZ ;
BSSY B2, 0xce0 ;
ISETP.GT.U32.AND P2, PT, R12, R21, PT ;
ISETP.LE.U32.AND P1, PT, R2, RZ, PT ;
IMAD.X R2, R14.reuse, 0x1, ~R19, P3 ;
ISETP.GT.U32.AND.EX P2, PT, R14, R19, PT, P2 ;
ISETP.LE.U32.OR.EX P1, PT, R2, RZ, !P2, P1 ;
@P1 BRA 0xcd0 ;
SHF.R.S32.HI R2, RZ, 0x1f, R21 ;
IADD3 R6, P1, R21, 0x1, RZ ;
LOP3.LUT R2, R2, c[0x0][0x164], RZ, 0xc0, !PT ;
IMAD.IADD R4, R2, 0x1, R21 ;
SHF.R.S32.HI R2, RZ, 0x1f, R6 ;
ISETP.NE.AND P0, PT, R4, c[0x0][0x164], PT ;
LOP3.LUT R3, R2, c[0x0][0x164], RZ, 0xc0, !PT ;
SEL R5, R4, RZ, P0 ;
IMAD.IADD R3, R3, 0x1, R6 ;
IMAD R5, R16, c[0x0][0x164], R5 ;
ISETP.NE.AND P2, PT, R3, c[0x0][0x164], PT ;
ISETP.NE.AND P0, PT, R5, R0, PT ;
SEL R3, R3, RZ, P2 ;
IMAD R3, R16, c[0x0][0x164], R3 ;
ISETP.NE.AND P2, PT, R3, R0, PT ;
@P0 IADD3 R4, P3, R5, c[0x0][0x168], RZ ;
@P0 LEA.HI.X.SX32 R5, R5, c[0x0][0x16c], 0x1, P3 ;
@P0 LDG.E.U8 R4, [R4.64] ;
@P2 IADD3 R2, P3, R3, c[0x0][0x168], RZ ;
@P2 LEA.HI.X.SX32 R3, R3, c[0x0][0x16c], 0x1, P3 ;
@P2 LDG.E.U8 R2, [R2.64] ;
@P0 IADD3 R7, R9, 0x1, RZ ;
IMAD.X R19, RZ, RZ, R19, P1 ;
ISETP.NE.AND P3, PT, R4, 0x58, P0 ;
ISETP.NE.AND P4, PT, R2, 0x58, P2 ;
@P3 IMAD.MOV R7, RZ, RZ, R9 ;
IADD3 R21, P3, R6, 0x1, RZ ;
@P0 IMAD.MOV.U32 R9, RZ, RZ, R7 ;
PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ;
IMAD.X R19, RZ, RZ, R19, P3 ;
@P2 IADD3 R7, R9, 0x1, RZ ;
@P4 IMAD.MOV R7, RZ, RZ, R9 ;
@P2 IMAD.MOV.U32 R9, RZ, RZ, R7 ;
BSYNC B2 ;
ISETP.LE.U32.AND P1, PT, R21, R12, PT ;
ISETP.LE.U32.OR.EX P0, PT, R19, R14, P0, P1 ;
@!P0 BRA 0xe00 ;
SHF.R.S32.HI R2, RZ, 0x1f, R21 ;
LOP3.LUT R2, R2, c[0x0][0x164], RZ, 0xc0, !PT ;
IMAD.IADD R2, R2, 0x1, R21 ;
ISETP.NE.AND P0, PT, R2, c[0x0][0x164], PT ;
SEL R3, R2, RZ, P0 ;
IMAD R3, R16, c[0x0][0x164], R3 ;
ISETP.NE.AND P0, PT, R3, R0, PT ;
@!P0 BRA 0xe00 ;
IADD3 R2, P0, R3, c[0x0][0x168], RZ ;
LEA.HI.X.SX32 R3, R3, c[0x0][0x16c], 0x1, P0 ;
LDG.E.U8 R2, [R2.64] ;
IADD3 R4, R9, 0x1, RZ ;
ISETP.NE.AND P0, PT, R2, 0x58, PT ;
@P0 IMAD.MOV R4, RZ, RZ, R9 ;
IMAD.MOV.U32 R9, RZ, RZ, R4 ;
BSYNC B0 ;
IADD3 R11, P0, R11, 0x1, RZ ;
IMAD.X R10, RZ, RZ, R10, P0 ;
ISETP.GT.U32.AND P0, PT, R11, R8, PT ;
ISETP.GT.U32.AND.EX P0, PT, R10, R15, PT, P0 ;
@!P0 BRA 0x340 ;
BSYNC B1 ;
SHF.R.S32.HI R3, RZ, 0x1f, R0 ;
IADD3 R4, P0, R0, c[0x0][0x168], RZ ;
IADD3.X R5, R3, c[0x0][0x16c], RZ, P0, !PT ;
LDG.E.U8 R4, [R4.64] ;
IADD3 R2, P1, R0, c[0x0][0x170], RZ ;
IADD3.X R3, R3, c[0x0][0x174], RZ, P1, !PT ;
ISETP.NE.AND P0, PT, R4, 0x58, PT ;
@!P0 BRA 0xf60 ;
ISETP.NE.AND P0, PT, R9, 0x3, PT ;
IMAD.MOV.U32 R0, RZ, RZ, 0x2d ;
@P0 STG.E.U8 [R2.64], R0 ;
@P0 EXIT ;
IMAD.MOV.U32 R0, RZ, RZ, 0x58 ;
STG.E.U8 [R2.64], R0 ;
EXIT ;
LOP3.LUT R9, R9, 0xfffffffe, RZ, 0xc0, !PT ;
IMAD.MOV.U32 R0, RZ, RZ, 0x2d ;
ISETP.NE.AND P0, PT, R9, 0x2, PT ;
@P0 STG.E.U8 [R2.64], R0 ;
@P0 EXIT ;
IMAD.MOV.U32 R0, RZ, RZ, 0x58 ;
STG.E.U8 [R2.64], R0 ;
EXIT ;
BRA 0xfe0;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
```
|
```amdasm
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9play_gameiiPcS_ ; -- Begin function _Z9play_gameiiPcS_
.globl _Z9play_gameiiPcS_
.p2align 8
.type _Z9play_gameiiPcS_,@function
_Z9play_gameiiPcS_: ; @_Z9play_gameiiPcS_
; %bb.0:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x24
s_load_b64 s[2:3], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1)
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
s_mul_i32 s4, s3, s2
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_cmp_gt_i32_e32 vcc_lo, s4, v1
s_and_saveexec_b32 s4, vcc_lo
s_cbranch_execz .LBB0_22
; %bb.1:
s_ashr_i32 s4, s3, 31
v_ashrrev_i32_e32 v2, 31, v1
s_add_i32 s5, s3, s4
s_mov_b32 s8, 0
s_xor_b32 s5, s5, s4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v4, v1, v2
v_cvt_f32_u32_e32 v0, s5
s_sub_i32 s6, 0, s5
v_xor_b32_e32 v4, v4, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v0, v0
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v0, 0x4f7ffffe, v0
v_cvt_u32_f32_e32 v0, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v3, s6, v0
v_mul_hi_u32 v3, v0, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v0, v0, v3
v_mul_hi_u32 v0, v4, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v3, v0, s5
v_sub_nc_u32_e32 v3, v4, v3
v_add_nc_u32_e32 v4, 1, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v5, s5, v3
v_cmp_le_u32_e32 vcc_lo, s5, v3
v_dual_cndmask_b32 v3, v3, v5 :: v_dual_cndmask_b32 v0, v0, v4
v_xor_b32_e32 v5, s4, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cmp_le_u32_e32 vcc_lo, s5, v3
v_add_nc_u32_e32 v4, 1, v0
s_load_b128 s[4:7], s[0:1], 0x8
s_mov_b32 s1, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v0, v0, v4, vcc_lo
v_xor_b32_e32 v0, v0, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v4, v0, v5
v_dual_mov_b32 v0, 0 :: v_dual_add_nc_u32 v3, -1, v4
v_add_nc_u32_e32 v5, 1, v4
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_le_u32_e64 v3, v5
s_cbranch_execz .LBB0_11
; %bb.2: ; %.lr.ph70
v_mul_lo_u32 v0, v4, s3
v_mul_lo_u32 v4, s3, v5
v_ashrrev_i32_e32 v6, 31, v5
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_sub_nc_u32_e32 v0, v1, v0
v_sub_nc_u32_e32 v8, v4, v1
v_ashrrev_i32_e32 v4, 31, v3
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_add_nc_u32_e32 v7, -1, v0
v_dual_mov_b32 v0, 0 :: v_dual_add_nc_u32 v9, 1, v0
v_add_nc_u32_e32 v13, 1, v8
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_ashrrev_i32_e32 v8, 31, v7
v_ashrrev_i32_e32 v10, 31, v9
v_cmp_le_u32_e32 vcc_lo, v7, v9
.LBB0_3: ; =>This Loop Header: Depth=1
; Child Loop BB0_5 Depth 2
s_and_saveexec_b32 s9, vcc_lo
s_cbranch_execz .LBB0_9
; %bb.4: ; %.lr.ph
; in Loop: Header=BB0_3 Depth=1
v_ashrrev_i32_e32 v11, 31, v3
v_mov_b32_e32 v15, v13
s_mov_b32 s10, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_and_b32_e32 v11, s2, v11
v_add_nc_u32_e32 v11, v11, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_ne_u32_e64 s0, s2, v11
v_cndmask_b32_e64 v11, 0, v11, s0
s_delay_alu instid0(VALU_DEP_1)
v_mul_lo_u32 v14, v11, s3
v_dual_mov_b32 v12, v8 :: v_dual_mov_b32 v11, v7
.LBB0_5: ; Parent Loop BB0_3 Depth=1
; => This Inner Loop Header: Depth=2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v16, 31, v11
s_mov_b32 s11, exec_lo
v_and_b32_e32 v16, s3, v16
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v17, v16, v11
v_cmp_ne_u32_e64 s0, v16, v15
v_cndmask_b32_e64 v16, 0, v17, s0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v16, v16, v14
v_cmpx_ne_u32_e64 v16, v1
s_cbranch_execz .LBB0_7
; %bb.6: ; in Loop: Header=BB0_5 Depth=2
v_ashrrev_i32_e32 v17, 31, v16
s_waitcnt lgkmcnt(0)
v_add_co_u32 v16, s0, s4, v16
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e64 v17, s0, s5, v17, s0
global_load_u8 v16, v[16:17], off
s_waitcnt vmcnt(0)
v_cmp_eq_u16_e64 s0, 0x58, v16
v_add_co_ci_u32_e64 v0, s0, 0, v0, s0
.LBB0_7: ; in Loop: Header=BB0_5 Depth=2
s_or_b32 exec_lo, exec_lo, s11
v_add_co_u32 v11, s0, v11, 1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_co_ci_u32_e64 v12, s0, 0, v12, s0
v_add_nc_u32_e32 v15, -1, v15
v_cmp_gt_u64_e64 s0, v[11:12], v[9:10]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_or_b32 s10, s0, s10
s_and_not1_b32 exec_lo, exec_lo, s10
s_cbranch_execnz .LBB0_5
; %bb.8: ; %Flow108
; in Loop: Header=BB0_3 Depth=1
s_or_b32 exec_lo, exec_lo, s10
.LBB0_9: ; %Flow109
; in Loop: Header=BB0_3 Depth=1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
s_or_b32 exec_lo, exec_lo, s9
v_add_co_u32 v3, s0, v3, 1
v_add_co_ci_u32_e64 v4, s0, 0, v4, s0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_u64_e64 s0, v[3:4], v[5:6]
s_or_b32 s8, s0, s8
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s8
s_cbranch_execnz .LBB0_3
; %bb.10: ; %Flow110
s_or_b32 exec_lo, exec_lo, s8
.LBB0_11: ; %Flow111
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s1
s_waitcnt lgkmcnt(0)
v_add_co_u32 v3, vcc_lo, s4, v1
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v2, vcc_lo
s_mov_b32 s0, exec_lo
global_load_u8 v3, v[3:4], off
s_waitcnt vmcnt(0)
v_cmpx_ne_u16_e32 0x58, v3
s_xor_b32 s1, exec_lo, s0
s_cbranch_execz .LBB0_17
; %bb.12:
v_cmp_ne_u32_e32 vcc_lo, 3, v0
v_add_co_u32 v0, s0, s6, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_add_co_ci_u32_e64 v1, s0, s7, v2, s0
s_and_saveexec_b32 s0, vcc_lo
s_xor_b32 s0, exec_lo, s0
s_cbranch_execz .LBB0_14
; %bb.13:
v_mov_b32_e32 v2, 45
global_store_b8 v[0:1], v2, off
; implicit-def: $vgpr0_vgpr1
.LBB0_14: ; %Flow
s_and_not1_saveexec_b32 s0, s0
s_cbranch_execz .LBB0_16
; %bb.15:
v_mov_b32_e32 v2, 0x58
global_store_b8 v[0:1], v2, off
.LBB0_16: ; %Flow103
s_or_b32 exec_lo, exec_lo, s0
; implicit-def: $vgpr0
; implicit-def: $vgpr1_vgpr2
.LBB0_17: ; %Flow106
s_and_not1_saveexec_b32 s0, s1
s_cbranch_execz .LBB0_22
; %bb.18:
v_add_nc_u32_e32 v0, -4, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_lt_u32_e32 vcc_lo, -3, v0
v_add_co_u32 v0, s0, s6, v1
v_add_co_ci_u32_e64 v1, s0, s7, v2, s0
s_and_saveexec_b32 s0, vcc_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s0, exec_lo, s0
s_cbranch_execz .LBB0_20
; %bb.19:
v_mov_b32_e32 v2, 0x58
global_store_b8 v[0:1], v2, off
; implicit-def: $vgpr0_vgpr1
.LBB0_20: ; %Flow104
s_and_not1_saveexec_b32 s0, s0
s_cbranch_execz .LBB0_22
; %bb.21:
v_mov_b32_e32 v2, 45
global_store_b8 v[0:1], v2, off
.LBB0_22:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9play_gameiiPcS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 18
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9play_gameiiPcS_, .Lfunc_end0-_Z9play_gameiiPcS_
; -- End function
.section .AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 888
; NumSgprs: 18
; NumVgprs: 18
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 2
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 18
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object ; @__hip_cuid_
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0 ; 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9play_gameiiPcS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z9play_gameiiPcS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 18
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
```
| 5,438 | 5,785 |
399 |
Convert the following CUDA host assembly code to AMD host assembly:
```cudaasm
.file "tmpxft_0018d8d4_00000000-6_grid.cudafe1.cpp"
.text
.globl _ZSt21ios_base_library_initv
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB4190:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4190:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "\n"
.text
.globl _Z10print_gridiiPc
.type _Z10print_gridiiPc, @function
_Z10print_gridiiPc:
.LFB4176:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $56, %rsp
.cfi_def_cfa_offset 112
movl %edi, %ebx
movl %esi, %r14d
movq %rdx, %r15
movq %rdx, 24(%rsp)
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movl $1, %edx
leaq .LC0(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movslq %ebx, %rax
movq %rax, 16(%rsp)
testl %ebx, %ebx
je .L3
movslq %r14d, %r14
leaq (%r15,%r14), %r12
movl $0, %r15d
movq $0, 8(%rsp)
leaq _ZSt4cout(%rip), %rbp
leaq 39(%rsp), %r13
jmp .L5
.L6:
movsbl %sil, %esi
movq %rbp, %rdi
call _ZNSo3putEc@PLT
.L7:
addq $1, %rbx
cmpq %r12, %rbx
je .L10
.L8:
movzbl (%rbx), %esi
movb %sil, 39(%rsp)
movq 0(%rbp), %rax
movq -24(%rax), %rax
cmpq $0, 16(%rbp,%rax)
je .L6
movl $1, %edx
movq %r13, %rsi
movq %rbp, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
jmp .L7
.L10:
movl $1, %edx
leaq .LC0(%rip), %rsi
movq %rbp, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
addq $1, 8(%rsp)
movq 8(%rsp), %rax
addq %r14, %r12
addq %r14, %r15
movq 16(%rsp), %rcx
cmpq %rcx, %rax
je .L3
.L5:
movq 24(%rsp), %rax
leaq (%rax,%r15), %rbx
testq %r14, %r14
jne .L8
jmp .L10
.L3:
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L15
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4176:
.size _Z10print_gridiiPc, .-_Z10print_gridiiPc
.globl _Z32__device_stub__Z9play_gameiiPcS_iiPcS_
.type _Z32__device_stub__Z9play_gameiiPcS_iiPcS_, @function
_Z32__device_stub__Z9play_gameiiPcS_iiPcS_:
.LFB4212:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 28(%rsp)
movl %esi, 24(%rsp)
movq %rdx, 16(%rsp)
movq %rcx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 24(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L20
.L16:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L21
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L20:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9play_gameiiPcS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L16
.L21:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4212:
.size _Z32__device_stub__Z9play_gameiiPcS_iiPcS_, .-_Z32__device_stub__Z9play_gameiiPcS_iiPcS_
.globl _Z9play_gameiiPcS_
.type _Z9play_gameiiPcS_, @function
_Z9play_gameiiPcS_:
.LFB4213:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z9play_gameiiPcS_iiPcS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4213:
.size _Z9play_gameiiPcS_, .-_Z9play_gameiiPcS_
.section .rodata.str1.1
.LC1:
.string "_Z9play_gameiiPcS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB4215:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z9play_gameiiPcS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4215:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .rodata._ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_.str1.8,"aMS",@progbits,1
.align 8
.LC2:
.string "basic_string: construction from null is not valid"
.section .text._ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_,"axG",@progbits,_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC5IS3_EEPKcRKS3_,comdat
.align 2
.weak _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_
.type _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_, @function
_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_:
.LFB4534:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $24, %rsp
.cfi_def_cfa_offset 64
movq %fs:40, %rax
movq %rax, 8(%rsp)
xorl %eax, %eax
leaq 16(%rdi), %r12
movq %r12, (%rdi)
testq %rsi, %rsi
je .L35
movq %rdi, %rbx
movq %rsi, %r13
movq %rsi, %rdi
call strlen@PLT
movq %rax, %rbp
movq %rax, (%rsp)
cmpq $15, %rax
ja .L36
cmpq $1, %rax
jne .L31
movzbl 0(%r13), %eax
movb %al, 16(%rbx)
.L32:
movq (%rsp), %rax
movq %rax, 8(%rbx)
movq (%rbx), %rdx
movb $0, (%rdx,%rax)
movq 8(%rsp), %rax
subq %fs:40, %rax
jne .L37
addq $24, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L35:
.cfi_restore_state
movq 8(%rsp), %rax
subq %fs:40, %rax
jne .L38
leaq .LC2(%rip), %rdi
call _ZSt19__throw_logic_errorPKc@PLT
.L38:
call __stack_chk_fail@PLT
.L36:
movq %rsp, %rsi
movl $0, %edx
movq %rbx, %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_createERmm@PLT
movq %rax, %r12
movq %rax, (%rbx)
movq (%rsp), %rax
movq %rax, 16(%rbx)
.L30:
movq %rbp, %rdx
movq %r13, %rsi
movq %r12, %rdi
call memcpy@PLT
jmp .L32
.L31:
testq %rax, %rax
je .L32
jmp .L30
.L37:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4534:
.size _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_, .-_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_
.weak _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC1IS3_EEPKcRKS3_
.set _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC1IS3_EEPKcRKS3_,_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_
.section .text._ZNSt6vectorIcSaIcEED2Ev,"axG",@progbits,_ZNSt6vectorIcSaIcEED5Ev,comdat
.align 2
.weak _ZNSt6vectorIcSaIcEED2Ev
.type _ZNSt6vectorIcSaIcEED2Ev, @function
_ZNSt6vectorIcSaIcEED2Ev:
.LFB4544:
.cfi_startproc
endbr64
movq (%rdi), %rax
testq %rax, %rax
je .L42
subq $8, %rsp
.cfi_def_cfa_offset 16
movq 16(%rdi), %rsi
subq %rax, %rsi
movq %rax, %rdi
call _ZdlPvm@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.L42:
ret
.cfi_endproc
.LFE4544:
.size _ZNSt6vectorIcSaIcEED2Ev, .-_ZNSt6vectorIcSaIcEED2Ev
.weak _ZNSt6vectorIcSaIcEED1Ev
.set _ZNSt6vectorIcSaIcEED1Ev,_ZNSt6vectorIcSaIcEED2Ev
.section .rodata._ZNSt6vectorIcSaIcEE17_M_realloc_insertIJRKcEEEvN9__gnu_cxx17__normal_iteratorIPcS1_EEDpOT_.str1.1,"aMS",@progbits,1
.LC3:
.string "vector::_M_realloc_insert"
.section .text._ZNSt6vectorIcSaIcEE17_M_realloc_insertIJRKcEEEvN9__gnu_cxx17__normal_iteratorIPcS1_EEDpOT_,"axG",@progbits,_ZNSt6vectorIcSaIcEE17_M_realloc_insertIJRKcEEEvN9__gnu_cxx17__normal_iteratorIPcS1_EEDpOT_,comdat
.align 2
.weak _ZNSt6vectorIcSaIcEE17_M_realloc_insertIJRKcEEEvN9__gnu_cxx17__normal_iteratorIPcS1_EEDpOT_
.type _ZNSt6vectorIcSaIcEE17_M_realloc_insertIJRKcEEEvN9__gnu_cxx17__normal_iteratorIPcS1_EEDpOT_, @function
_ZNSt6vectorIcSaIcEE17_M_realloc_insertIJRKcEEEvN9__gnu_cxx17__normal_iteratorIPcS1_EEDpOT_:
.LFB4732:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $40, %rsp
.cfi_def_cfa_offset 96
movq %rsi, 8(%rsp)
movq %rdx, 24(%rsp)
movq 8(%rdi), %r12
movq (%rdi), %r13
movq %r12, %rdx
subq %r13, %rdx
movabsq $9223372036854775807, %rax
cmpq %rax, %rdx
je .L60
movq %rdi, %rbp
testq %rdx, %rdx
movl $1, %eax
cmovne %rdx, %rax
addq %rdx, %rax
jc .L47
movabsq $9223372036854775807, %rdx
cmpq %rdx, %rax
cmovbe %rax, %rdx
movq %rdx, 16(%rsp)
movq 8(%rsp), %r15
subq %r13, %r15
movq %r15, %r14
movl $0, %ebx
testq %rax, %rax
je .L48
jmp .L55
.L60:
leaq .LC3(%rip), %rdi
call _ZSt20__throw_length_errorPKc@PLT
.L61:
movq %r14, %rdx
movq %r13, %rsi
movq %rbx, %rdi
call memmove@PLT
leaq 1(%rbx,%r14), %r14
movq 8(%rsp), %rax
subq %rax, %r12
testq %r12, %r12
jg .L50
addq %r12, %r14
movq 16(%rbp), %rsi
subq %r13, %rsi
jmp .L54
.L47:
movq 8(%rsp), %r15
subq %r13, %r15
movq %r15, %r14
movabsq $9223372036854775807, %rax
movq %rax, 16(%rsp)
.L55:
movq 16(%rsp), %rdi
call _Znwm@PLT
movq %rax, %rbx
.L48:
movq 24(%rsp), %rax
movzbl (%rax), %eax
movb %al, (%rbx,%r14)
testq %r15, %r15
jg .L61
leaq 1(%rbx,%r14), %r14
movq 8(%rsp), %rax
subq %rax, %r12
testq %r12, %r12
jle .L52
.L50:
movq %r12, %rdx
movq 8(%rsp), %rsi
movq %r14, %rdi
call memcpy@PLT
.L52:
addq %r12, %r14
testq %r13, %r13
je .L53
movq 16(%rbp), %rsi
subq %r13, %rsi
.L54:
movq %r13, %rdi
call _ZdlPvm@PLT
.L53:
movq %rbx, 0(%rbp)
movq %r14, 8(%rbp)
movq 16(%rsp), %rax
addq %rax, %rbx
movq %rbx, 16(%rbp)
addq $40, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4732:
.size _ZNSt6vectorIcSaIcEE17_M_realloc_insertIJRKcEEEvN9__gnu_cxx17__normal_iteratorIPcS1_EEDpOT_, .-_ZNSt6vectorIcSaIcEE17_M_realloc_insertIJRKcEEEvN9__gnu_cxx17__normal_iteratorIPcS1_EEDpOT_
.section .rodata.str1.1
.LC4:
.string ".txt"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC5:
.string "Error: You must specify a .txt file as the last parameter (./cugol -i 100 -v input.txt)\n"
.section .rodata.str1.1
.LC6:
.string "i:v:"
.text
.globl main
.type main, @function
main:
.LFB4177:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA4177
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $680, %rsp
.cfi_def_cfa_offset 736
movl %edi, %r12d
movq %rsi, %rbx
movq %fs:40, %rax
movq %rax, 664(%rsp)
xorl %eax, %eax
leaq 80(%rsp), %rbp
leaq 112(%rsp), %rdi
movq %rbp, %rdx
leaq .LC4(%rip), %rsi
.LEHB0:
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC1IS3_EEPKcRKS3_
.LEHE0:
movslq %r12d, %rax
leaq -8(%rbx,%rax,8), %r14
movq (%r14), %rsi
leaq 144(%rsp), %rdi
movq %rbp, %rdx
.LEHB1:
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC1IS3_EEPKcRKS3_
leaq 144(%rsp), %rbp
movq 120(%rsp), %rcx
movl $0, %edx
movq 112(%rsp), %rsi
movq %rbp, %rdi
call _ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE4findEPKcmm@PLT
movq %rax, %r15
movq %rbp, %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
movl $0, %ebp
movl $1, 28(%rsp)
leaq .LC6(%rip), %r13
cmpq $-1, %r15
jne .L63
leaq .LC5(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
.LEHE1:
jmp .L100
.L65:
movq 16(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movl %eax, 28(%rsp)
.L63:
movq %r13, %rdx
movq %rbx, %rsi
movl %r12d, %edi
call getopt@PLT
cmpl $-1, %eax
je .L101
cmpl $105, %eax
je .L65
cmpl $118, %eax
movl $1, %eax
cmove %eax, %ebp
jmp .L63
.L101:
movq $0, 80(%rsp)
movq $0, 88(%rsp)
movq $0, 96(%rsp)
leaq 144(%rsp), %rdi
.LEHB2:
call _ZNSt14basic_ifstreamIcSt11char_traitsIcEEC1Ev@PLT
.LEHE2:
movq (%r14), %rsi
leaq 144(%rsp), %rdi
movl $8, %edx
.LEHB3:
call _ZNSt14basic_ifstreamIcSt11char_traitsIcEE4openEPKcSt13_Ios_Openmode@PLT
movl 432(%rsp), %r12d
andl $2, %r12d
jne .L89
leaq 144(%rsp), %rbx
jmp .L73
.L104:
cmpl $10, %eax
jne .L102
.L69:
addl $1, %r12d
.L70:
leaq 39(%rsp), %rsi
movq %rbx, %rdi
call _ZStrsIcSt11char_traitsIcEERSt13basic_istreamIT_T0_ES6_RS3_@PLT
jmp .L103
.L102:
movq %rbx, %rdi
call _ZNSi4peekEv@PLT
cmpl $13, %eax
jne .L70
jmp .L69
.L103:
movq 88(%rsp), %rsi
cmpq 96(%rsp), %rsi
je .L71
movzbl 39(%rsp), %eax
movb %al, (%rsi)
addq $1, %rsi
movq %rsi, 88(%rsp)
.L72:
testb $2, 432(%rsp)
jne .L68
.L73:
movq %rbx, %rdi
call _ZNSi4peekEv@PLT
jmp .L104
.L71:
leaq 39(%rsp), %rdx
leaq 80(%rsp), %rdi
call _ZNSt6vectorIcSaIcEE17_M_realloc_insertIJRKcEEEvN9__gnu_cxx17__normal_iteratorIPcS1_EEDpOT_
jmp .L72
.L89:
movl $0, %r12d
.L68:
leaq 144(%rsp), %rdi
call _ZNSt14basic_ifstreamIcSt11char_traitsIcEE5closeEv@PLT
leal 1(%r12), %edi
movl %edi, 12(%rsp)
movq 80(%rsp), %rbx
movq 88(%rsp), %rax
subq %rbx, %rax
movslq %edi, %rcx
movl $0, %edx
divq %rcx
movl %eax, 24(%rsp)
imull %eax, %edi
movl %edi, %r14d
movslq %edi, %r12
movq %r12, %rdi
call malloc@PLT
movq %rax, %r13
movq %r12, %rdi
call malloc@PLT
movq %rax, 16(%rsp)
testq %r12, %r12
je .L74
movl $0, %eax
.L75:
movzbl (%rbx,%rax), %edx
movb %dl, 0(%r13,%rax)
addq $1, %rax
cmpq %rax, %r12
jne .L75
.L74:
movq %r13, %rdx
movl 24(%rsp), %esi
movl 12(%rsp), %edi
call _Z10print_gridiiPc
leaq 40(%rsp), %rdi
movq %r12, %rsi
call cudaMalloc@PLT
leaq 48(%rsp), %rdi
movq %r12, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %r12, %rdx
movq %r13, %rsi
movq 40(%rsp), %rdi
call cudaMemcpy@PLT
movl 28(%rsp), %eax
movslq %eax, %r15
testl %eax, %eax
je .L76
leal 1022(%r14), %eax
addl $511, %r14d
cmovs %eax, %r14d
sarl $9, %r14d
movl $0, %ebx
jmp .L79
.L106:
testl %eax, %eax
jne .L77
movq 48(%rsp), %rcx
movq 40(%rsp), %rdx
movl 24(%rsp), %esi
movl 12(%rsp), %edi
call _Z32__device_stub__Z9play_gameiiPcS_iiPcS_
.L77:
call cudaDeviceSynchronize@PLT
testb %bpl, %bpl
jne .L105
.L78:
movq 40(%rsp), %rax
movq 48(%rsp), %rdx
movq %rdx, 40(%rsp)
movq %rax, 48(%rsp)
addq $1, %rbx
cmpq %r15, %rbx
je .L76
.L79:
movl $512, 68(%rsp)
movl $1, 72(%rsp)
movl %r14d, 56(%rsp)
movl $1, 60(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 68(%rsp), %rdx
movl $1, %ecx
movq 56(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
jmp .L106
.L105:
movl $2, %ecx
movq %r12, %rdx
movq 48(%rsp), %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movq 16(%rsp), %rdx
movl 24(%rsp), %esi
movl 12(%rsp), %edi
call _Z10print_gridiiPc
jmp .L78
.L76:
movl $2, %ecx
movq %r12, %rdx
movq 48(%rsp), %rsi
movq 16(%rsp), %rbx
movq %rbx, %rdi
call cudaMemcpy@PLT
testb %bpl, %bpl
jne .L80
movq %rbx, %rdx
movl 24(%rsp), %esi
movl 12(%rsp), %edi
call _Z10print_gridiiPc
.L80:
movq %r13, %rdi
call free@PLT
movq 16(%rsp), %rdi
call free@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
movq 48(%rsp), %rdi
call cudaFree@PLT
.LEHE3:
leaq 144(%rsp), %rdi
call _ZNSt14basic_ifstreamIcSt11char_traitsIcEED1Ev@PLT
leaq 80(%rsp), %rdi
call _ZNSt6vectorIcSaIcEED1Ev
movl $0, %ebx
.L64:
leaq 112(%rsp), %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
movq 664(%rsp), %rax
subq %fs:40, %rax
jne .L107
movl %ebx, %eax
addq $680, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L100:
.cfi_restore_state
movl $1, %ebx
jmp .L64
.L92:
endbr64
movq %rax, %rbx
leaq 144(%rsp), %rdi
call _ZNSt14basic_ifstreamIcSt11char_traitsIcEED1Ev@PLT
.L82:
leaq 80(%rsp), %rdi
call _ZNSt6vectorIcSaIcEED1Ev
.L83:
leaq 112(%rsp), %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
movq 664(%rsp), %rax
subq %fs:40, %rax
je .L84
call __stack_chk_fail@PLT
.L91:
endbr64
movq %rax, %rbx
jmp .L82
.L90:
endbr64
movq %rax, %rbx
jmp .L83
.L84:
movq %rbx, %rdi
.LEHB4:
call _Unwind_Resume@PLT
.LEHE4:
.L107:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4177:
.globl __gxx_personality_v0
.section .gcc_except_table,"a",@progbits
.LLSDA4177:
.byte 0xff
.byte 0xff
.byte 0x1
.uleb128 .LLSDACSE4177-.LLSDACSB4177
.LLSDACSB4177:
.uleb128 .LEHB0-.LFB4177
.uleb128 .LEHE0-.LEHB0
.uleb128 0
.uleb128 0
.uleb128 .LEHB1-.LFB4177
.uleb128 .LEHE1-.LEHB1
.uleb128 .L90-.LFB4177
.uleb128 0
.uleb128 .LEHB2-.LFB4177
.uleb128 .LEHE2-.LEHB2
.uleb128 .L91-.LFB4177
.uleb128 0
.uleb128 .LEHB3-.LFB4177
.uleb128 .LEHE3-.LEHB3
.uleb128 .L92-.LFB4177
.uleb128 0
.uleb128 .LEHB4-.LFB4177
.uleb128 .LEHE4-.LEHB4
.uleb128 0
.uleb128 0
.LLSDACSE4177:
.text
.size main, .-main
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.hidden DW.ref.__gxx_personality_v0
.weak DW.ref.__gxx_personality_v0
.section .data.rel.local.DW.ref.__gxx_personality_v0,"awG",@progbits,DW.ref.__gxx_personality_v0,comdat
.align 8
.type DW.ref.__gxx_personality_v0, @object
.size DW.ref.__gxx_personality_v0, 8
DW.ref.__gxx_personality_v0:
.quad __gxx_personality_v0
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
```
|
```amdasm
.text
.file "grid.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z24__device_stub__play_gameiiPcS_ # -- Begin function _Z24__device_stub__play_gameiiPcS_
.type _Z24__device_stub__play_gameiiPcS_,@function
_Z24__device_stub__play_gameiiPcS_: # @_Z24__device_stub__play_gameiiPcS_
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $112, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 12(%rsp), %rax
movl %edi, (%rax)
leaq 8(%rsp), %rdi
movl %esi, (%rdi)
leaq 40(%rsp), %rsi
movq %rdx, (%rsi)
leaq 32(%rsp), %rdx
movq %rcx, (%rdx)
leaq 80(%rsp), %rbx
movq %rax, (%rbx)
movq %rdi, 8(%rbx)
movq %rsi, 16(%rbx)
movq %rdx, 24(%rbx)
leaq 64(%rsp), %r14
leaq 48(%rsp), %r15
leaq 24(%rsp), %r12
leaq 16(%rsp), %r13
movq %r14, %rdi
movq %r15, %rsi
movq %r12, %rdx
movq %r13, %rcx
callq __hipPopCallConfiguration
movq (%r14), %rsi
movl 8(%r14), %edx
movq (%r15), %rcx
movl 8(%r15), %r8d
movl $_Z9play_gameiiPcS_, %edi
movq %rbx, %r9
pushq (%r13)
.cfi_adjust_cfa_offset 8
pushq (%r12)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $128, %rsp
.cfi_adjust_cfa_offset -128
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z24__device_stub__play_gameiiPcS_, .Lfunc_end0-_Z24__device_stub__play_gameiiPcS_
.cfi_endproc
# -- End function
.globl _Z10print_gridiiPc # -- Begin function _Z10print_gridiiPc
.type _Z10print_gridiiPc,@function
_Z10print_gridiiPc: # @_Z10print_gridiiPc
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
pushq %rax
.cfi_def_cfa_offset 64
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rdx, %rbx
movl %esi, 4(%rsp) # 4-byte Spill
movl %edi, %r14d
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $1, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
testl %r14d, %r14d
je .LBB1_7
# %bb.1: # %.preheader.lr.ph
movslq %r14d, %r15
movslq 4(%rsp), %r12 # 4-byte Folded Reload
xorl %r13d, %r13d
leaq 3(%rsp), %r14
.LBB1_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB1_4 Depth 2
cmpl $0, 4(%rsp) # 4-byte Folded Reload
je .LBB1_6
# %bb.3: # %.lr.ph
# in Loop: Header=BB1_2 Depth=1
xorl %ebp, %ebp
.LBB1_4: # Parent Loop BB1_2 Depth=1
# => This Inner Loop Header: Depth=2
movb (%rbx,%rbp), %al
movb %al, 3(%rsp)
movq _ZSt4cout(%rip), %rcx
movq -24(%rcx), %rcx
cmpq $0, _ZSt4cout+16(%rcx)
je .LBB1_8
# %bb.5: # in Loop: Header=BB1_4 Depth=2
movl $_ZSt4cout, %edi
movl $1, %edx
movq %r14, %rsi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
jmp .LBB1_9
.LBB1_8: # in Loop: Header=BB1_4 Depth=2
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
.LBB1_9: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_c.exit
# in Loop: Header=BB1_4 Depth=2
incq %rbp
cmpq %rbp, %r12
jne .LBB1_4
.LBB1_6: # %._crit_edge
# in Loop: Header=BB1_2 Depth=1
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $1, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
incq %r13
addq %r12, %rbx
cmpq %r15, %r13
jne .LBB1_2
.LBB1_7: # %._crit_edge13
addq $8, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z10print_gridiiPc, .Lfunc_end1-_Z10print_gridiiPc
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.type main,@function
main: # @main
.Lfunc_begin0:
.cfi_startproc
.cfi_personality 3, __gxx_personality_v0
.cfi_lsda 3, .Lexception0
# %bb.0: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_.exit
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $632, %rsp # imm = 0x278
.cfi_def_cfa_offset 688
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsi, %rbx
movl %edi, %ebp
leaq 96(%rsp), %rax
movq %rax, -16(%rax)
leaq 80(%rsp), %rdi
movl $.L.str.1, %esi
movl $.L.str.1+4, %edx
callq _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_M_constructIPKcEEvT_S8_St20forward_iterator_tag
movslq %ebp, %r12
movq -8(%rbx,%r12,8), %rsi
.Ltmp0:
leaq 112(%rsp), %rdi
leaq 48(%rsp), %rdx
callq _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_
.Ltmp1:
# %bb.1:
movq 80(%rsp), %rsi
movq 88(%rsp), %rcx
leaq 112(%rsp), %r15
movq %r15, %rdi
xorl %edx, %edx
callq _ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE4findEPKcmm
movq %rax, %r14
movq (%r15), %rdi
leaq 128(%rsp), %rax
cmpq %rax, %rdi
je .LBB2_3
# %bb.2: # %_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE11_M_is_localEv.exit.i.i
callq _ZdlPv
.LBB2_3: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev.exit
cmpq $-1, %r14
je .LBB2_59
# %bb.4: # %.preheader94
movl $1, %r14d
movb $1, %al
movl %eax, 12(%rsp) # 4-byte Spill
.LBB2_5: # =>This Inner Loop Header: Depth=1
movl $.L.str.3, %edx
movl %ebp, %edi
movq %rbx, %rsi
callq getopt
cmpl $-1, %eax
je .LBB2_10
# %bb.6: # in Loop: Header=BB2_5 Depth=1
cmpl $118, %eax
je .LBB2_9
# %bb.7: # in Loop: Header=BB2_5 Depth=1
cmpl $105, %eax
jne .LBB2_5
# %bb.8: # in Loop: Header=BB2_5 Depth=1
movq 16(%rbx), %rdi
callq atoi
movl %eax, %r14d
jmp .LBB2_5
.LBB2_9: # in Loop: Header=BB2_5 Depth=1
movl $0, 12(%rsp) # 4-byte Folded Spill
jmp .LBB2_5
.LBB2_10:
xorps %xmm0, %xmm0
movaps %xmm0, 48(%rsp)
movq $0, 64(%rsp)
.Ltmp3:
leaq 112(%rsp), %rdi
callq _ZNSt14basic_ifstreamIcSt11char_traitsIcEEC1Ev
.Ltmp4:
# %bb.11:
movl %r14d, 44(%rsp) # 4-byte Spill
movq -8(%rbx,%r12,8), %rsi
.Ltmp6:
leaq 112(%rsp), %rdi
movl $8, %edx
callq _ZNSt14basic_ifstreamIcSt11char_traitsIcEE4openEPKcSt13_Ios_Openmode
.Ltmp7:
# %bb.12: # %.preheader93
movq 112(%rsp), %rax
movq -24(%rax), %rax
xorl %ebx, %ebx
testb $2, 144(%rsp,%rax)
jne .LBB2_27
# %bb.13: # %.lr.ph
xorl %ebx, %ebx
leaq 112(%rsp), %r14
leaq 11(%rsp), %r15
leaq 48(%rsp), %r12
.LBB2_14: # =>This Inner Loop Header: Depth=1
.Ltmp8:
movq %r14, %rdi
callq _ZNSi4peekEv
.Ltmp9:
# %bb.15: # in Loop: Header=BB2_14 Depth=1
cmpl $10, %eax
je .LBB2_18
# %bb.16: # in Loop: Header=BB2_14 Depth=1
.Ltmp10:
movq %r14, %rdi
callq _ZNSi4peekEv
.Ltmp11:
# %bb.17: # in Loop: Header=BB2_14 Depth=1
cmpl $13, %eax
jne .LBB2_19
.LBB2_18: # in Loop: Header=BB2_14 Depth=1
incl %ebx
.LBB2_19: # in Loop: Header=BB2_14 Depth=1
.Ltmp12:
movq %r14, %rdi
movq %r15, %rsi
callq _ZStrsIcSt11char_traitsIcEERSt13basic_istreamIT_T0_ES6_RS3_
.Ltmp13:
# %bb.20: # in Loop: Header=BB2_14 Depth=1
movq 56(%rsp), %rsi
cmpq 64(%rsp), %rsi
je .LBB2_25
# %bb.21: # in Loop: Header=BB2_14 Depth=1
movb 11(%rsp), %al
movb %al, (%rsi)
incq 56(%rsp)
jmp .LBB2_26
.LBB2_25: # in Loop: Header=BB2_14 Depth=1
.Ltmp14:
movq %r12, %rdi
movq %r15, %rdx
callq _ZNSt6vectorIcSaIcEE17_M_realloc_insertIJRKcEEEvN9__gnu_cxx17__normal_iteratorIPcS1_EEDpOT_
.Ltmp15:
.LBB2_26: # %_ZNSt6vectorIcSaIcEE9push_backERKc.exit
# in Loop: Header=BB2_14 Depth=1
movq 112(%rsp), %rax
movq -24(%rax), %rax
testb $2, 144(%rsp,%rax)
je .LBB2_14
.LBB2_27: # %._crit_edge
.Ltmp17:
leaq 112(%rsp), %rdi
callq _ZNSt14basic_ifstreamIcSt11char_traitsIcEE5closeEv
.Ltmp18:
# %bb.28:
incl %ebx
movq 48(%rsp), %r14
movq 56(%rsp), %rax
subq %r14, %rax
movslq %ebx, %rcx
xorl %edx, %edx
divq %rcx
movl %ebx, %ebp
movq %rax, 32(%rsp) # 8-byte Spill
imull %eax, %ebp
movslq %ebp, %r13
movq %r13, %rdi
callq malloc
movq %rax, %r15
movq %r13, %rdi
callq malloc
movq %rax, %r12
testl %r13d, %r13d
je .LBB2_31
# %bb.29: # %.lr.ph101.preheader
xorl %eax, %eax
.LBB2_30: # %.lr.ph101
# =>This Inner Loop Header: Depth=1
movb (%r14,%rax), %cl
movb %cl, (%r15,%rax)
incq %rax
cmpq %r13, %rax
jb .LBB2_30
.LBB2_31: # %._crit_edge102
.Ltmp20:
movl %ebx, %edi
movq 32(%rsp), %rsi # 8-byte Reload
# kill: def $esi killed $esi killed $rsi
movq %r15, %rdx
callq _Z10print_gridiiPc
.Ltmp21:
# %bb.32:
.Ltmp23:
leaq 24(%rsp), %rdi
movq %r13, %rsi
callq hipMalloc
.Ltmp24:
movl 44(%rsp), %r14d # 4-byte Reload
# %bb.33:
.Ltmp25:
leaq 16(%rsp), %rdi
movq %r13, %rsi
callq hipMalloc
.Ltmp26:
# %bb.34:
movq 24(%rsp), %rdi
.Ltmp27:
movq %r15, %rsi
movq %r13, %rdx
movl $1, %ecx
callq hipMemcpy
.Ltmp28:
# %bb.35: # %.preheader
testl %r14d, %r14d
je .LBB2_36
# %bb.46: # %.lr.ph104
leal 511(%rbp), %eax
addl $1022, %ebp # imm = 0x3FE
testl %eax, %eax
cmovnsl %eax, %ebp
movslq %r14d, %r14
sarl $9, %ebp
btsq $32, %rbp
.LBB2_47: # =>This Inner Loop Header: Depth=1
.Ltmp29:
movq %rbp, %rdi
movl $1, %esi
movabsq $4294967808, %rdx # imm = 0x100000200
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
.Ltmp30:
# %bb.48: # in Loop: Header=BB2_47 Depth=1
testl %eax, %eax
jne .LBB2_50
# %bb.49: # in Loop: Header=BB2_47 Depth=1
movq 24(%rsp), %rdx
movq 16(%rsp), %rcx
.Ltmp31:
movl %ebx, %edi
movq 32(%rsp), %rsi # 8-byte Reload
# kill: def $esi killed $esi killed $rsi
callq _Z24__device_stub__play_gameiiPcS_
.Ltmp32:
.LBB2_50: # in Loop: Header=BB2_47 Depth=1
.Ltmp33:
callq hipDeviceSynchronize
.Ltmp34:
# %bb.51: # in Loop: Header=BB2_47 Depth=1
testb $1, 12(%rsp) # 1-byte Folded Reload
jne .LBB2_54
# %bb.52: # in Loop: Header=BB2_47 Depth=1
movq 16(%rsp), %rsi
.Ltmp35:
movq %r12, %rdi
movq %r13, %rdx
movl $2, %ecx
callq hipMemcpy
.Ltmp36:
# %bb.53: # in Loop: Header=BB2_47 Depth=1
.Ltmp37:
movl %ebx, %edi
movq 32(%rsp), %rsi # 8-byte Reload
# kill: def $esi killed $esi killed $rsi
movq %r12, %rdx
callq _Z10print_gridiiPc
.Ltmp38:
.LBB2_54: # in Loop: Header=BB2_47 Depth=1
movq 24(%rsp), %rsi
movq 16(%rsp), %rax
movq %rax, 24(%rsp)
movq %rsi, 16(%rsp)
decq %r14
jne .LBB2_47
jmp .LBB2_37
.LBB2_59:
movl $1, %ebx
.Ltmp49:
movl $_ZSt4cout, %edi
movl $.L.str.2, %esi
movl $88, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp50:
jmp .LBB2_60
.LBB2_36: # %.preheader.._crit_edge105_crit_edge
movq 16(%rsp), %rsi
.LBB2_37: # %._crit_edge105
.Ltmp40:
movq %r12, %rdi
movq %r13, %rdx
movl $2, %ecx
callq hipMemcpy
.Ltmp41:
# %bb.38:
testb $1, 12(%rsp) # 1-byte Folded Reload
je .LBB2_40
# %bb.39:
.Ltmp42:
movl %ebx, %edi
movq 32(%rsp), %rsi # 8-byte Reload
# kill: def $esi killed $esi killed $rsi
movq %r12, %rdx
callq _Z10print_gridiiPc
.Ltmp43:
.LBB2_40:
movq %r15, %rdi
callq free
movq %r12, %rdi
callq free
movq 24(%rsp), %rdi
.Ltmp44:
callq hipFree
.Ltmp45:
# %bb.41:
movq 16(%rsp), %rdi
.Ltmp46:
callq hipFree
.Ltmp47:
# %bb.42:
leaq 112(%rsp), %rdi
callq _ZNSt14basic_ifstreamIcSt11char_traitsIcEED1Ev
movq 48(%rsp), %rdi
testq %rdi, %rdi
je .LBB2_44
# %bb.43:
callq _ZdlPv
.LBB2_44: # %_ZNSt6vectorIcSaIcEED2Ev.exit
xorl %ebx, %ebx
.LBB2_60: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit
movq 80(%rsp), %rdi
leaq 96(%rsp), %rax
cmpq %rax, %rdi
je .LBB2_62
# %bb.61: # %_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE11_M_is_localEv.exit.i.i83
callq _ZdlPv
.LBB2_62: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev.exit85
movl %ebx, %eax
addq $632, %rsp # imm = 0x278
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB2_68:
.cfi_def_cfa_offset 688
.Ltmp51:
jmp .LBB2_64
.LBB2_45:
.Ltmp22:
jmp .LBB2_56
.LBB2_22:
.Ltmp5:
movq %rax, %rbx
jmp .LBB2_57
.LBB2_63:
.Ltmp2:
.LBB2_64:
movq %rax, %rbx
jmp .LBB2_65
.LBB2_24: # %.loopexit.split-lp
.Ltmp19:
jmp .LBB2_56
.LBB2_55:
.Ltmp48:
jmp .LBB2_56
.LBB2_23: # %.loopexit
.Ltmp16:
jmp .LBB2_56
.LBB2_69:
.Ltmp39:
.LBB2_56:
movq %rax, %rbx
leaq 112(%rsp), %rdi
callq _ZNSt14basic_ifstreamIcSt11char_traitsIcEED1Ev
.LBB2_57:
movq 48(%rsp), %rdi
testq %rdi, %rdi
je .LBB2_65
# %bb.58:
callq _ZdlPv
.LBB2_65:
movq 80(%rsp), %rdi
leaq 96(%rsp), %rax
cmpq %rax, %rdi
je .LBB2_67
# %bb.66: # %_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE11_M_is_localEv.exit.i.i86
callq _ZdlPv
.LBB2_67: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev.exit88
movq %rbx, %rdi
callq _Unwind_Resume@PLT
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
.section .gcc_except_table,"a",@progbits
.p2align 2, 0x0
GCC_except_table2:
.Lexception0:
.byte 255 # @LPStart Encoding = omit
.byte 255 # @TType Encoding = omit
.byte 1 # Call site Encoding = uleb128
.uleb128 .Lcst_end0-.Lcst_begin0
.Lcst_begin0:
.uleb128 .Lfunc_begin0-.Lfunc_begin0 # >> Call Site 1 <<
.uleb128 .Ltmp0-.Lfunc_begin0 # Call between .Lfunc_begin0 and .Ltmp0
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp0-.Lfunc_begin0 # >> Call Site 2 <<
.uleb128 .Ltmp1-.Ltmp0 # Call between .Ltmp0 and .Ltmp1
.uleb128 .Ltmp2-.Lfunc_begin0 # jumps to .Ltmp2
.byte 0 # On action: cleanup
.uleb128 .Ltmp3-.Lfunc_begin0 # >> Call Site 3 <<
.uleb128 .Ltmp4-.Ltmp3 # Call between .Ltmp3 and .Ltmp4
.uleb128 .Ltmp5-.Lfunc_begin0 # jumps to .Ltmp5
.byte 0 # On action: cleanup
.uleb128 .Ltmp6-.Lfunc_begin0 # >> Call Site 4 <<
.uleb128 .Ltmp7-.Ltmp6 # Call between .Ltmp6 and .Ltmp7
.uleb128 .Ltmp19-.Lfunc_begin0 # jumps to .Ltmp19
.byte 0 # On action: cleanup
.uleb128 .Ltmp8-.Lfunc_begin0 # >> Call Site 5 <<
.uleb128 .Ltmp15-.Ltmp8 # Call between .Ltmp8 and .Ltmp15
.uleb128 .Ltmp16-.Lfunc_begin0 # jumps to .Ltmp16
.byte 0 # On action: cleanup
.uleb128 .Ltmp17-.Lfunc_begin0 # >> Call Site 6 <<
.uleb128 .Ltmp18-.Ltmp17 # Call between .Ltmp17 and .Ltmp18
.uleb128 .Ltmp19-.Lfunc_begin0 # jumps to .Ltmp19
.byte 0 # On action: cleanup
.uleb128 .Ltmp20-.Lfunc_begin0 # >> Call Site 7 <<
.uleb128 .Ltmp21-.Ltmp20 # Call between .Ltmp20 and .Ltmp21
.uleb128 .Ltmp22-.Lfunc_begin0 # jumps to .Ltmp22
.byte 0 # On action: cleanup
.uleb128 .Ltmp23-.Lfunc_begin0 # >> Call Site 8 <<
.uleb128 .Ltmp28-.Ltmp23 # Call between .Ltmp23 and .Ltmp28
.uleb128 .Ltmp48-.Lfunc_begin0 # jumps to .Ltmp48
.byte 0 # On action: cleanup
.uleb128 .Ltmp29-.Lfunc_begin0 # >> Call Site 9 <<
.uleb128 .Ltmp38-.Ltmp29 # Call between .Ltmp29 and .Ltmp38
.uleb128 .Ltmp39-.Lfunc_begin0 # jumps to .Ltmp39
.byte 0 # On action: cleanup
.uleb128 .Ltmp49-.Lfunc_begin0 # >> Call Site 10 <<
.uleb128 .Ltmp50-.Ltmp49 # Call between .Ltmp49 and .Ltmp50
.uleb128 .Ltmp51-.Lfunc_begin0 # jumps to .Ltmp51
.byte 0 # On action: cleanup
.uleb128 .Ltmp40-.Lfunc_begin0 # >> Call Site 11 <<
.uleb128 .Ltmp47-.Ltmp40 # Call between .Ltmp40 and .Ltmp47
.uleb128 .Ltmp48-.Lfunc_begin0 # jumps to .Ltmp48
.byte 0 # On action: cleanup
.uleb128 .Ltmp47-.Lfunc_begin0 # >> Call Site 12 <<
.uleb128 .Lfunc_end2-.Ltmp47 # Call between .Ltmp47 and .Lfunc_end2
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.Lcst_end0:
.p2align 2, 0x0
# -- End function
.section .text._ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_,"axG",@progbits,_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_,comdat
.weak _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_ # -- Begin function _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_
.p2align 1, 0x90
.type _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_,@function
_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_: # @_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
pushq %rax
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
leaq 16(%rdi), %rax
movq %rax, (%rdi)
testq %rsi, %rsi
je .LBB3_1
# %bb.2:
movq %rsi, %rbx
movq %rdi, %r14
movq %rsi, %rdi
callq strlen
leaq (%rax,%rbx), %rdx
movq %r14, %rdi
movq %rbx, %rsi
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
jmp _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_M_constructIPKcEEvT_S8_St20forward_iterator_tag # TAILCALL
.LBB3_1:
.cfi_def_cfa_offset 32
movl $.L.str.4, %edi
callq _ZSt19__throw_logic_errorPKc
.Lfunc_end3:
.size _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_, .Lfunc_end3-_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_
.cfi_endproc
# -- End function
.section .text._ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_M_constructIPKcEEvT_S8_St20forward_iterator_tag,"axG",@progbits,_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_M_constructIPKcEEvT_S8_St20forward_iterator_tag,comdat
.weak _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_M_constructIPKcEEvT_S8_St20forward_iterator_tag # -- Begin function _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_M_constructIPKcEEvT_S8_St20forward_iterator_tag
.p2align 1, 0x90
.type _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_M_constructIPKcEEvT_S8_St20forward_iterator_tag,@function
_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_M_constructIPKcEEvT_S8_St20forward_iterator_tag: # @_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_M_constructIPKcEEvT_S8_St20forward_iterator_tag
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
pushq %rax
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rdx, %r14
movq %rsi, %r15
movq %rdi, %rbx
subq %rsi, %r14
movq %r14, (%rsp)
cmpq $15, %r14
jbe .LBB4_1
# %bb.2:
movq %rsp, %r12
movq %rbx, %rdi
movq %r12, %rsi
xorl %edx, %edx
callq _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_createERmm
movq %rax, (%rbx)
movq (%r12), %rcx
movq %rcx, 16(%rbx)
jmp .LBB4_3
.LBB4_1: # %._crit_edge
movq (%rbx), %rax
.LBB4_3:
testq %r14, %r14
je .LBB4_7
# %bb.4:
cmpq $1, %r14
jne .LBB4_6
# %bb.5:
movb (%r15), %cl
movb %cl, (%rax)
jmp .LBB4_7
.LBB4_6:
movq %rax, %rdi
movq %r15, %rsi
movq %r14, %rdx
callq memcpy@PLT
.LBB4_7: # %_ZZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_M_constructIPKcEEvT_S8_St20forward_iterator_tagEN6_GuardD2Ev.exit
movq (%rsp), %rax
movq %rax, 8(%rbx)
movq (%rbx), %rcx
movb $0, (%rcx,%rax)
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end4:
.size _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_M_constructIPKcEEvT_S8_St20forward_iterator_tag, .Lfunc_end4-_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_M_constructIPKcEEvT_S8_St20forward_iterator_tag
.cfi_endproc
# -- End function
.section .text._ZNSt6vectorIcSaIcEE17_M_realloc_insertIJRKcEEEvN9__gnu_cxx17__normal_iteratorIPcS1_EEDpOT_,"axG",@progbits,_ZNSt6vectorIcSaIcEE17_M_realloc_insertIJRKcEEEvN9__gnu_cxx17__normal_iteratorIPcS1_EEDpOT_,comdat
.weak _ZNSt6vectorIcSaIcEE17_M_realloc_insertIJRKcEEEvN9__gnu_cxx17__normal_iteratorIPcS1_EEDpOT_ # -- Begin function _ZNSt6vectorIcSaIcEE17_M_realloc_insertIJRKcEEEvN9__gnu_cxx17__normal_iteratorIPcS1_EEDpOT_
.p2align 1, 0x90
.type _ZNSt6vectorIcSaIcEE17_M_realloc_insertIJRKcEEEvN9__gnu_cxx17__normal_iteratorIPcS1_EEDpOT_,@function
_ZNSt6vectorIcSaIcEE17_M_realloc_insertIJRKcEEEvN9__gnu_cxx17__normal_iteratorIPcS1_EEDpOT_: # @_ZNSt6vectorIcSaIcEE17_M_realloc_insertIJRKcEEEvN9__gnu_cxx17__normal_iteratorIPcS1_EEDpOT_
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $24, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rdi, %rbx
movabsq $9223372036854775807, %rax # imm = 0x7FFFFFFFFFFFFFFF
movq (%rdi), %rdi
movq 8(%rbx), %r14
movq %r14, %rcx
subq %rdi, %rcx
cmpq %rax, %rcx
je .LBB5_11
# %bb.1: # %_ZNKSt6vectorIcSaIcEE12_M_check_lenEmPKc.exit
cmpq $1, %rcx
movq %rcx, %r8
adcq $0, %r8
leaq (%r8,%rcx), %r12
cmpq %rax, %r12
cmovaeq %rax, %r12
addq %rcx, %r8
cmovbq %rax, %r12
movq %rsi, 16(%rsp) # 8-byte Spill
movq %rsi, %r15
movq %rdi, 8(%rsp) # 8-byte Spill
subq %rdi, %r15
testq %r12, %r12
je .LBB5_2
# %bb.3:
movq %r12, %rdi
movq %rdx, %r13
callq _Znwm
movq %r13, %rdx
movq %rax, %rbp
jmp .LBB5_4
.LBB5_2:
xorl %ebp, %ebp
.LBB5_4: # %_ZNSt12_Vector_baseIcSaIcEE11_M_allocateEm.exit
leaq (%r15,%rbp), %r13
movb (%rdx), %al
movb %al, (%rbp,%r15)
testq %r15, %r15
jle .LBB5_6
# %bb.5:
movq %rbp, %rdi
movq 8(%rsp), %rsi # 8-byte Reload
movq %r15, %rdx
callq memmove@PLT
.LBB5_6: # %_ZNSt6vectorIcSaIcEE11_S_relocateEPcS2_S2_RS0_.exit
incq %r13
movq 16(%rsp), %rsi # 8-byte Reload
subq %rsi, %r14
testq %r14, %r14
jle .LBB5_8
# %bb.7:
movq %r13, %rdi
movq %r14, %rdx
callq memmove@PLT
.LBB5_8: # %_ZNSt6vectorIcSaIcEE11_S_relocateEPcS2_S2_RS0_.exit16
movq 8(%rsp), %rdi # 8-byte Reload
testq %rdi, %rdi
je .LBB5_10
# %bb.9:
callq _ZdlPv
.LBB5_10: # %_ZNSt12_Vector_baseIcSaIcEE13_M_deallocateEPcm.exit
addq %r14, %r13
movq %rbp, (%rbx)
movq %r13, 8(%rbx)
addq %rbp, %r12
movq %r12, 16(%rbx)
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB5_11:
.cfi_def_cfa_offset 80
movl $.L.str.5, %edi
callq _ZSt20__throw_length_errorPKc
.Lfunc_end5:
.size _ZNSt6vectorIcSaIcEE17_M_realloc_insertIJRKcEEEvN9__gnu_cxx17__normal_iteratorIPcS1_EEDpOT_, .Lfunc_end5-_ZNSt6vectorIcSaIcEE17_M_realloc_insertIJRKcEEEvN9__gnu_cxx17__normal_iteratorIPcS1_EEDpOT_
.cfi_endproc
# -- End function
.text
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
jne .LBB6_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, %rdi
movq %rax, __hip_gpubin_handle(%rip)
.LBB6_2:
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9play_gameiiPcS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end6:
.size __hip_module_ctor, .Lfunc_end6-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB7_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB7_2:
retq
.Lfunc_end7:
.size __hip_module_dtor, .Lfunc_end7-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9play_gameiiPcS_,@object # @_Z9play_gameiiPcS_
.section .rodata,"a",@progbits
.globl _Z9play_gameiiPcS_
.p2align 3, 0x0
_Z9play_gameiiPcS_:
.quad _Z24__device_stub__play_gameiiPcS_
.size _Z9play_gameiiPcS_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "\n"
.size .L.str, 2
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz ".txt"
.size .L.str.1, 5
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Error: You must specify a .txt file as the last parameter (./cugol -i 100 -v input.txt)\n"
.size .L.str.2, 89
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "i:v:"
.size .L.str.3, 5
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "basic_string: construction from null is not valid"
.size .L.str.4, 50
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "vector::_M_realloc_insert"
.size .L.str.5, 26
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z9play_gameiiPcS_"
.size .L__unnamed_1, 19
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__play_gameiiPcS_
.addrsig_sym __gxx_personality_v0
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Unwind_Resume
.addrsig_sym _Z9play_gameiiPcS_
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
```
| 10,701 | 13,718 |
402 |
Convert the following CUDA device assembly code to AMD device assembly:
```cudaasm
code for sm_80
```
|
```amdasm
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object ; @__hip_cuid_
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0 ; 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
```
| 24 | 306 |
403 |
Convert the following CUDA host assembly code to AMD host assembly:
```cudaasm
.file "tmpxft_0010becb_00000000-6_test.cudafe1.cpp"
.text
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2030:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl main
.type main, @function
main:
.LFB2027:
.cfi_startproc
endbr64
subq $24, %rsp
.cfi_def_cfa_offset 32
movq %fs:40, %rax
movq %rax, 8(%rsp)
xorl %eax, %eax
movq %rsp, %rdi
movl $100, %esi
call cudaMalloc@PLT
movq (%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rax
subq %fs:40, %rax
jne .L6
movl $0, %eax
addq $24, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L6:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2027:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2053:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2053:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
```
|
```amdasm
.text
.file "test.hip"
.globl main # -- Begin function main
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $16, %rsp
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -16
leaq 8(%rsp), %rbx
movl $100, %esi
movq %rbx, %rdi
callq hipMalloc
movq (%rbx), %rdi
callq hipFree
xorl %eax, %eax
addq $16, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
```
| 981 | 406 |
406 |
Convert the following CUDA device assembly code to AMD device assembly:
```cudaasm
code for sm_80
Function : _Z13jmeint_kernelPfS_S_S_S_S_Pbi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
MOV R1, c[0x0][0x28] ;
EXIT ;
BRA 0x20;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
```
|
```amdasm
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z13jmeint_kernelPfS_S_S_S_S_Pbi ; -- Begin function _Z13jmeint_kernelPfS_S_S_S_S_Pbi
.globl _Z13jmeint_kernelPfS_S_S_S_S_Pbi
.p2align 8
.type _Z13jmeint_kernelPfS_S_S_S_S_Pbi,@function
_Z13jmeint_kernelPfS_S_S_S_S_Pbi: ; @_Z13jmeint_kernelPfS_S_S_S_S_Pbi
; %bb.0:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13jmeint_kernelPfS_S_S_S_S_Pbi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 60
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 1
.amdhsa_next_free_sgpr 1
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z13jmeint_kernelPfS_S_S_S_S_Pbi, .Lfunc_end0-_Z13jmeint_kernelPfS_S_S_S_S_Pbi
; -- End function
.section .AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 4
; NumSgprs: 0
; NumVgprs: 0
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 0
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 1
; NumVGPRsForWavesPerEU: 1
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object ; @__hip_cuid_
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0 ; 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 40
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 48
.size: 8
.value_kind: global_buffer
- .offset: 56
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 60
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13jmeint_kernelPfS_S_S_S_S_Pbi
.private_segment_fixed_size: 0
.sgpr_count: 0
.sgpr_spill_count: 0
.symbol: _Z13jmeint_kernelPfS_S_S_S_S_Pbi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 0
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
```
| 130 | 1,858 |
407 |
Convert the following CUDA host assembly code to AMD host assembly:
```cudaasm
.file "tmpxft_0013a166_00000000-6_main.cudafe1.cpp"
.text
.globl _ZSt21ios_base_library_initv
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3808:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3808:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z19newComputeIntervalsffffffffPfS_
.type _Z19newComputeIntervalsffffffffPfS_, @function
_Z19newComputeIntervalsffffffffPfS_:
.LFB3800:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE3800:
.size _Z19newComputeIntervalsffffffffPfS_, .-_Z19newComputeIntervalsffffffffPfS_
.globl _Z12edgeEdgeTestPfS_S_iiff
.type _Z12edgeEdgeTestPfS_S_iiff, @function
_Z12edgeEdgeTestPfS_S_iiff:
.LFB3801:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE3801:
.size _Z12edgeEdgeTestPfS_S_iiff, .-_Z12edgeEdgeTestPfS_S_iiff
.globl _Z10pointInTriPfS_S_S_ii
.type _Z10pointInTriPfS_S_S_ii, @function
_Z10pointInTriPfS_S_S_ii:
.LFB3802:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE3802:
.size _Z10pointInTriPfS_S_S_ii, .-_Z10pointInTriPfS_S_S_ii
.globl _Z14coplanarTriTriPfS_S_S_S_S_S_
.type _Z14coplanarTriTriPfS_S_S_S_S_S_, @function
_Z14coplanarTriTriPfS_S_S_S_S_S_:
.LFB3803:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE3803:
.size _Z14coplanarTriTriPfS_S_S_S_S_S_, .-_Z14coplanarTriTriPfS_S_S_S_S_S_
.globl _Z18jmeint_kernel_implPfS_S_S_S_S_
.type _Z18jmeint_kernel_implPfS_S_S_S_S_, @function
_Z18jmeint_kernel_implPfS_S_S_S_S_:
.LFB3804:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE3804:
.size _Z18jmeint_kernel_implPfS_S_S_S_S_, .-_Z18jmeint_kernel_implPfS_S_S_S_S_
.globl _Z46__device_stub__Z13jmeint_kernelPfS_S_S_S_S_PbiPfS_S_S_S_S_Pbi
.type _Z46__device_stub__Z13jmeint_kernelPfS_S_S_S_S_PbiPfS_S_S_S_S_Pbi, @function
_Z46__device_stub__Z13jmeint_kernelPfS_S_S_S_S_PbiPfS_S_S_S_S_Pbi:
.LFB3830:
.cfi_startproc
endbr64
subq $216, %rsp
.cfi_def_cfa_offset 224
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
movq %rdx, 40(%rsp)
movq %rcx, 32(%rsp)
movq %r8, 24(%rsp)
movq %r9, 16(%rsp)
movq 224(%rsp), %rax
movq %rax, 8(%rsp)
movq %fs:40, %rax
movq %rax, 200(%rsp)
xorl %eax, %eax
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 40(%rsp), %rax
movq %rax, 144(%rsp)
leaq 32(%rsp), %rax
movq %rax, 152(%rsp)
leaq 24(%rsp), %rax
movq %rax, 160(%rsp)
leaq 16(%rsp), %rax
movq %rax, 168(%rsp)
leaq 8(%rsp), %rax
movq %rax, 176(%rsp)
leaq 232(%rsp), %rax
movq %rax, 184(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
leaq 72(%rsp), %rcx
leaq 64(%rsp), %rdx
leaq 92(%rsp), %rsi
leaq 80(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L17
.L13:
movq 200(%rsp), %rax
subq %fs:40, %rax
jne .L18
addq $216, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L17:
.cfi_restore_state
pushq 72(%rsp)
.cfi_def_cfa_offset 232
pushq 72(%rsp)
.cfi_def_cfa_offset 240
leaq 144(%rsp), %r9
movq 108(%rsp), %rcx
movl 116(%rsp), %r8d
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
leaq _Z13jmeint_kernelPfS_S_S_S_S_Pbi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 224
jmp .L13
.L18:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3830:
.size _Z46__device_stub__Z13jmeint_kernelPfS_S_S_S_S_PbiPfS_S_S_S_S_Pbi, .-_Z46__device_stub__Z13jmeint_kernelPfS_S_S_S_S_PbiPfS_S_S_S_S_Pbi
.globl _Z13jmeint_kernelPfS_S_S_S_S_Pbi
.type _Z13jmeint_kernelPfS_S_S_S_S_Pbi, @function
_Z13jmeint_kernelPfS_S_S_S_S_Pbi:
.LFB3831:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 24
pushq 24(%rsp)
.cfi_def_cfa_offset 32
call _Z46__device_stub__Z13jmeint_kernelPfS_S_S_S_S_PbiPfS_S_S_S_S_Pbi
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3831:
.size _Z13jmeint_kernelPfS_S_S_S_S_Pbi, .-_Z13jmeint_kernelPfS_S_S_S_S_Pbi
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z13jmeint_kernelPfS_S_S_S_S_Pbi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3833:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z13jmeint_kernelPfS_S_S_S_S_Pbi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3833:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .rodata.str1.8
.align 8
.LC1:
.string "Usage: ./jmeint.out <input file locations> <output file>"
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "
.LC3:
.string "Memory allocation fails!!!"
.section .rodata.str1.8
.align 8
.LC4:
.string "
.align 8
.LC5:
.string "
.align 8
.LC6:
.string "
.align 8
.LC7:
.string "Something was wrong! Error code: "
.align 8
.LC8:
.string "
.section .rodata.str1.1
.LC9:
.string "
.LC10:
.string "Thank you..."
.text
.globl main
.type main, @function
main:
.LFB3805:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA3805
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
movq %rsp, %rbp
.cfi_def_cfa_register 6
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $1224, %rsp
.cfi_offset 15, -24
.cfi_offset 14, -32
.cfi_offset 13, -40
.cfi_offset 12, -48
.cfi_offset 3, -56
movq %fs:40, %rax
movq %rax, -56(%rbp)
xorl %eax, %eax
cmpl $3, %edi
jne .L77
movq %rsi, %rbx
movl $0, -1192(%rbp)
movq 8(%rsi), %rsi
leaq -576(%rbp), %rdi
movl $8, %edx
.LEHB0:
call _ZNSt14basic_ifstreamIcSt11char_traitsIcEEC1EPKcSt13_Ios_Openmode@PLT
.LEHE0:
movq 16(%rbx), %rsi
leaq -1088(%rbp), %rdi
movl $16, %edx
.LEHB1:
call _ZNSt14basic_ofstreamIcSt11char_traitsIcEEC1EPKcSt13_Ios_Openmode@PLT
.LEHE1:
jmp .L78
.L77:
leaq .LC1(%rip), %rsi
leaq _ZSt4cerr(%rip), %rdi
.LEHB2:
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
.LEHE2:
movl $1, %edi
call exit@PLT
.L78:
leaq -456(%rbp), %rdi
call _ZNKSt12__basic_fileIcE7is_openEv@PLT
testb %al, %al
je .L25
leaq -1192(%rbp), %rsi
leaq -576(%rbp), %rdi
.LEHB3:
call _ZNSirsERi@PLT
leaq .LC2(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl -1192(%rbp), %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
.L25:
movslq -1192(%rbp), %rdi
leaq _ZSt7nothrow(%rip), %rsi
call _ZnamRKSt9nothrow_t@PLT
movq %rax, -1248(%rbp)
movslq -1192(%rbp), %rax
movabsq $768614336404564650, %rdx
cmpq %rax, %rdx
jb .L26
leaq (%rax,%rax,2), %rdi
salq $2, %rdi
leaq _ZSt7nothrow(%rip), %rsi
call _ZnamRKSt9nothrow_t@PLT
movq %rax, %r15
testq %rax, %rax
je .L79
movslq -1192(%rbp), %rax
movabsq $768614336404564650, %rdx
cmpq %rax, %rdx
jb .L30
leaq (%rax,%rax,2), %rdi
salq $2, %rdi
leaq _ZSt7nothrow(%rip), %rsi
call _ZnamRKSt9nothrow_t@PLT
movq %rax, %r14
testq %rax, %rax
je .L80
movslq -1192(%rbp), %rax
movabsq $768614336404564650, %rdx
cmpq %rax, %rdx
jb .L34
leaq (%rax,%rax,2), %rdi
salq $2, %rdi
leaq _ZSt7nothrow(%rip), %rsi
call _ZnamRKSt9nothrow_t@PLT
movq %rax, %r13
testq %rax, %rax
je .L81
movslq -1192(%rbp), %rax
movabsq $768614336404564650, %rdx
cmpq %rax, %rdx
jb .L38
leaq (%rax,%rax,2), %rdi
salq $2, %rdi
leaq _ZSt7nothrow(%rip), %rsi
call _ZnamRKSt9nothrow_t@PLT
movq %rax, -1216(%rbp)
testq %rax, %rax
je .L82
movslq -1192(%rbp), %rax
movabsq $768614336404564650, %rdx
cmpq %rax, %rdx
jb .L42
leaq (%rax,%rax,2), %rdi
salq $2, %rdi
leaq _ZSt7nothrow(%rip), %rsi
call _ZnamRKSt9nothrow_t@PLT
movq %rax, -1224(%rbp)
testq %rax, %rax
je .L83
movslq -1192(%rbp), %rax
movabsq $768614336404564650, %rdx
cmpq %rax, %rdx
jb .L46
leaq (%rax,%rax,2), %rdi
salq $2, %rdi
leaq _ZSt7nothrow(%rip), %rsi
call _ZnamRKSt9nothrow_t@PLT
movq %rax, -1232(%rbp)
testq %rax, %rax
je .L84
leaq -1184(%rbp), %rdi
call cudaEventCreate@PLT
jmp .L85
.L26:
movq -56(%rbp), %rax
subq %fs:40, %rax
je .L29
call __stack_chk_fail@PLT
.L29:
call __cxa_throw_bad_array_new_length@PLT
.L79:
leaq .LC3(%rip), %rsi
leaq _ZSt4cerr(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $1, %edi
call exit@PLT
.L30:
movq -56(%rbp), %rax
subq %fs:40, %rax
je .L33
call __stack_chk_fail@PLT
.L33:
call __cxa_throw_bad_array_new_length@PLT
.L80:
leaq .LC3(%rip), %rsi
leaq _ZSt4cerr(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $1, %edi
call exit@PLT
.L34:
movq -56(%rbp), %rax
subq %fs:40, %rax
je .L37
call __stack_chk_fail@PLT
.L37:
call __cxa_throw_bad_array_new_length@PLT
.L81:
leaq .LC3(%rip), %rsi
leaq _ZSt4cerr(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $1, %edi
call exit@PLT
.L38:
movq -56(%rbp), %rax
subq %fs:40, %rax
je .L41
call __stack_chk_fail@PLT
.L41:
call __cxa_throw_bad_array_new_length@PLT
.L82:
leaq .LC3(%rip), %rsi
leaq _ZSt4cerr(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $1, %edi
call exit@PLT
.L42:
movq -56(%rbp), %rax
subq %fs:40, %rax
je .L45
call __stack_chk_fail@PLT
.L45:
call __cxa_throw_bad_array_new_length@PLT
.L83:
leaq .LC3(%rip), %rsi
leaq _ZSt4cerr(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $1, %edi
call exit@PLT
.L46:
movq -56(%rbp), %rax
subq %fs:40, %rax
je .L49
call __stack_chk_fail@PLT
.L49:
call __cxa_throw_bad_array_new_length@PLT
.L84:
leaq .LC3(%rip), %rsi
leaq _ZSt4cerr(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $1, %edi
call exit@PLT
.L85:
leaq -1176(%rbp), %rdi
call cudaEventCreate@PLT
cmpl $0, -1192(%rbp)
jle .L50
movl $4, %ebx
movq $8, -1208(%rbp)
movl $0, %r12d
movl $0, -1236(%rbp)
leaq -576(%rbp), %rax
movq %rax, -1256(%rbp)
jmp .L51
.L86:
movq %rax, %rdi
leaq (%r15,%rbx), %rsi
call _ZNSi10_M_extractIfEERSiRT_@PLT
movq %rax, %rdi
movq -1208(%rbp), %rax
leaq (%r15,%rax), %rsi
call _ZNSi10_M_extractIfEERSiRT_@PLT
movq %rax, %rdi
leaq (%r12,%r14), %rsi
call _ZNSi10_M_extractIfEERSiRT_@PLT
movq %rax, %rdi
leaq (%r14,%rbx), %rsi
call _ZNSi10_M_extractIfEERSiRT_@PLT
movq %rax, %rdi
movq -1208(%rbp), %rax
leaq (%r14,%rax), %rsi
call _ZNSi10_M_extractIfEERSiRT_@PLT
movq %rax, %rdi
leaq (%r12,%r13), %rsi
call _ZNSi10_M_extractIfEERSiRT_@PLT
movq %rax, %rdi
leaq 0(%r13,%rbx), %rsi
call _ZNSi10_M_extractIfEERSiRT_@PLT
movq %rax, %rdi
movq -1208(%rbp), %rax
leaq 0(%r13,%rax), %rsi
call _ZNSi10_M_extractIfEERSiRT_@PLT
movq %rax, %rdi
movq -1216(%rbp), %rcx
leaq (%r12,%rcx), %rsi
call _ZNSi10_M_extractIfEERSiRT_@PLT
movq %rax, %rdi
movq -1216(%rbp), %rcx
leaq (%rcx,%rbx), %rsi
call _ZNSi10_M_extractIfEERSiRT_@PLT
movq %rax, %rdi
movq -1216(%rbp), %rcx
movq -1208(%rbp), %rax
leaq (%rcx,%rax), %rsi
call _ZNSi10_M_extractIfEERSiRT_@PLT
movq %rax, %rdi
movq -1224(%rbp), %rcx
leaq (%r12,%rcx), %rsi
call _ZNSi10_M_extractIfEERSiRT_@PLT
movq %rax, %rdi
movq -1224(%rbp), %rcx
leaq (%rcx,%rbx), %rsi
call _ZNSi10_M_extractIfEERSiRT_@PLT
movq %rax, %rdi
movq -1224(%rbp), %rcx
movq -1208(%rbp), %rax
leaq (%rcx,%rax), %rsi
call _ZNSi10_M_extractIfEERSiRT_@PLT
movq %rax, %rdi
movq -1232(%rbp), %rdx
leaq (%r12,%rdx), %rsi
call _ZNSi10_M_extractIfEERSiRT_@PLT
movq %rax, %rdi
movq -1232(%rbp), %rdx
leaq (%rdx,%rbx), %rsi
call _ZNSi10_M_extractIfEERSiRT_@PLT
movq %rax, %rdi
movq -1232(%rbp), %rdx
movq -1208(%rbp), %rax
leaq (%rdx,%rax), %rsi
call _ZNSi10_M_extractIfEERSiRT_@PLT
addl $1, -1236(%rbp)
movl -1236(%rbp), %ecx
addq $12, %r12
addq $12, -1208(%rbp)
addq $12, %rbx
cmpl %ecx, -1192(%rbp)
jle .L50
.L51:
leaq (%r12,%r15), %rsi
movq -1256(%rbp), %rdi
call _ZNSi10_M_extractIfEERSiRT_@PLT
jmp .L86
.L50:
leaq .LC4(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl -1192(%rbp), %eax
leal (%rax,%rax,2), %esi
movslq %esi, %rsi
salq $2, %rsi
leaq -1168(%rbp), %rdi
call cudaMalloc@PLT
movl -1192(%rbp), %eax
leal (%rax,%rax,2), %esi
movslq %esi, %rsi
salq $2, %rsi
leaq -1160(%rbp), %rdi
call cudaMalloc@PLT
movl -1192(%rbp), %eax
leal (%rax,%rax,2), %esi
movslq %esi, %rsi
salq $2, %rsi
leaq -1152(%rbp), %rdi
call cudaMalloc@PLT
movl -1192(%rbp), %eax
leal (%rax,%rax,2), %esi
movslq %esi, %rsi
salq $2, %rsi
leaq -1144(%rbp), %rdi
call cudaMalloc@PLT
movl -1192(%rbp), %eax
leal (%rax,%rax,2), %esi
movslq %esi, %rsi
salq $2, %rsi
leaq -1136(%rbp), %rdi
call cudaMalloc@PLT
movl -1192(%rbp), %eax
leal (%rax,%rax,2), %esi
movslq %esi, %rsi
salq $2, %rsi
leaq -1128(%rbp), %rdi
call cudaMalloc@PLT
movslq -1192(%rbp), %rsi
leaq -1120(%rbp), %rdi
call cudaMalloc@PLT
leaq .LC5(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl -1192(%rbp), %eax
leal (%rax,%rax,2), %edx
movslq %edx, %rdx
salq $2, %rdx
movl $1, %ecx
movq %r15, %rsi
movq -1168(%rbp), %rdi
call cudaMemcpy@PLT
movl -1192(%rbp), %eax
leal (%rax,%rax,2), %edx
movslq %edx, %rdx
salq $2, %rdx
movl $1, %ecx
movq %r14, %rsi
movq -1160(%rbp), %rdi
call cudaMemcpy@PLT
movl -1192(%rbp), %eax
leal (%rax,%rax,2), %edx
movslq %edx, %rdx
salq $2, %rdx
movl $1, %ecx
movq %r13, %rsi
movq -1152(%rbp), %rdi
call cudaMemcpy@PLT
movl -1192(%rbp), %eax
leal (%rax,%rax,2), %edx
movslq %edx, %rdx
salq $2, %rdx
movl $1, %ecx
movq -1216(%rbp), %rsi
movq -1144(%rbp), %rdi
call cudaMemcpy@PLT
movl -1192(%rbp), %eax
leal (%rax,%rax,2), %edx
movslq %edx, %rdx
salq $2, %rdx
movl $1, %ecx
movq -1224(%rbp), %rsi
movq -1136(%rbp), %rdi
call cudaMemcpy@PLT
movl -1192(%rbp), %eax
leal (%rax,%rax,2), %edx
movslq %edx, %rdx
salq $2, %rdx
movl $1, %ecx
movq -1232(%rbp), %rsi
movq -1128(%rbp), %rdi
call cudaMemcpy@PLT
leaq .LC6(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $512, -1112(%rbp)
movl $1, -1108(%rbp)
movl $1, -1104(%rbp)
movl -1192(%rbp), %edx
leal 511(%rdx), %eax
testl %edx, %edx
cmovns %edx, %eax
sarl $9, %eax
movl %eax, -1100(%rbp)
movl $1, -1096(%rbp)
movl $1, -1092(%rbp)
movl $0, %esi
movq -1184(%rbp), %rdi
call cudaEventRecord@PLT
movl -1104(%rbp), %ecx
movl $0, %r9d
movl $0, %r8d
movq -1112(%rbp), %rdx
movq -1100(%rbp), %rdi
movl -1092(%rbp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L52
movl -1192(%rbp), %eax
pushq %rax
pushq -1120(%rbp)
movq -1128(%rbp), %r9
movq -1136(%rbp), %r8
movq -1144(%rbp), %rcx
movq -1152(%rbp), %rdx
movq -1160(%rbp), %rsi
movq -1168(%rbp), %rdi
.cfi_escape 0x2e,0x10
call _Z46__device_stub__Z13jmeint_kernelPfS_S_S_S_S_PbiPfS_S_S_S_S_Pbi
addq $16, %rsp
.L52:
.cfi_escape 0x2e,0
call cudaDeviceSynchronize@PLT
movl %eax, %ebx
testl %eax, %eax
je .L53
leaq .LC7(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl %ebx, %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
.L53:
movl $0, %esi
movq -1176(%rbp), %rdi
call cudaEventRecord@PLT
movq -1176(%rbp), %rdi
call cudaEventSynchronize@PLT
leaq -1188(%rbp), %rdi
movq -1176(%rbp), %rdx
movq -1184(%rbp), %rsi
call cudaEventElapsedTime@PLT
movq -1184(%rbp), %rdi
call cudaEventDestroy@PLT
movq -1176(%rbp), %rdi
call cudaEventDestroy@PLT
leaq .LC8(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
pxor %xmm0, %xmm0
cvtss2sd -1188(%rbp), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq .LC9(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movslq -1192(%rbp), %rdx
movl $2, %ecx
movq -1120(%rbp), %rsi
movq -1248(%rbp), %rdi
call cudaMemcpy@PLT
cmpl $0, -1192(%rbp)
jle .L54
movq $0, -1208(%rbp)
leaq -1088(%rbp), %r12
jmp .L59
.L90:
movq -1088(%rbp), %rax
movq -24(%rax), %rax
movq -848(%rbp,%rax), %rbx
testq %rbx, %rbx
je .L87
cmpb $0, 56(%rbx)
je .L57
movzbl 67(%rbx), %esi
.L58:
movsbl %sil, %esi
movq %r12, %rdi
call _ZNSo3putEc@PLT
jmp .L88
.L87:
movq -56(%rbp), %rax
subq %fs:40, %rax
jne .L89
call _ZSt16__throw_bad_castv@PLT
.L66:
endbr64
movq %rax, %rbx
leaq -1088(%rbp), %rdi
call _ZNSt14basic_ofstreamIcSt11char_traitsIcEED1Ev@PLT
.L62:
leaq -576(%rbp), %rdi
call _ZNSt14basic_ifstreamIcSt11char_traitsIcEED1Ev@PLT
movq -56(%rbp), %rax
subq %fs:40, %rax
je .L63
call __stack_chk_fail@PLT
.L89:
call __stack_chk_fail@PLT
.L57:
movq %rbx, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%rbx), %rax
movl $10, %esi
movq %rbx, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L58
.L88:
movq %rax, %rdi
call _ZNSo5flushEv@PLT
addq $1, -1208(%rbp)
movq -1208(%rbp), %rax
cmpl %eax, -1192(%rbp)
jle .L54
.L59:
movq -1248(%rbp), %rax
movq -1208(%rbp), %rbx
movzbl (%rax,%rbx), %esi
movq %r12, %rdi
call _ZNSo9_M_insertIbEERSoT_@PLT
jmp .L90
.L54:
leaq -576(%rbp), %rdi
call _ZNSt14basic_ifstreamIcSt11char_traitsIcEE5closeEv@PLT
leaq -1088(%rbp), %rdi
call _ZNSt14basic_ofstreamIcSt11char_traitsIcEE5closeEv@PLT
movq %r15, %rdi
call _ZdaPv@PLT
movq %r14, %rdi
call _ZdaPv@PLT
movq %r13, %rdi
call _ZdaPv@PLT
movq -1216(%rbp), %rdi
call _ZdaPv@PLT
movq -1224(%rbp), %rdi
call _ZdaPv@PLT
movq -1232(%rbp), %rdi
call _ZdaPv@PLT
movq -1248(%rbp), %rax
testq %rax, %rax
je .L60
movq %rax, %rdi
call _ZdaPv@PLT
.L60:
movq -1168(%rbp), %rdi
call cudaFree@PLT
movq -1160(%rbp), %rdi
call cudaFree@PLT
movq -1152(%rbp), %rdi
call cudaFree@PLT
movq -1144(%rbp), %rdi
call cudaFree@PLT
movq -1136(%rbp), %rdi
call cudaFree@PLT
movq -1128(%rbp), %rdi
call cudaFree@PLT
movq -1120(%rbp), %rdi
call cudaFree@PLT
leaq .LC10(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
.LEHE3:
leaq -1088(%rbp), %rdi
call _ZNSt14basic_ofstreamIcSt11char_traitsIcEED1Ev@PLT
leaq -576(%rbp), %rdi
call _ZNSt14basic_ifstreamIcSt11char_traitsIcEED1Ev@PLT
movq -56(%rbp), %rax
subq %fs:40, %rax
jne .L91
movl $0, %eax
leaq -40(%rbp), %rsp
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
popq %rbp
.cfi_remember_state
.cfi_def_cfa 7, 8
ret
.L65:
.cfi_restore_state
endbr64
movq %rax, %rbx
jmp .L62
.L63:
movq %rbx, %rdi
.LEHB4:
call _Unwind_Resume@PLT
.LEHE4:
.L91:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3805:
.globl __gxx_personality_v0
.section .gcc_except_table,"a",@progbits
.LLSDA3805:
.byte 0xff
.byte 0xff
.byte 0x1
.uleb128 .LLSDACSE3805-.LLSDACSB3805
.LLSDACSB3805:
.uleb128 .LEHB0-.LFB3805
.uleb128 .LEHE0-.LEHB0
.uleb128 0
.uleb128 0
.uleb128 .LEHB1-.LFB3805
.uleb128 .LEHE1-.LEHB1
.uleb128 .L65-.LFB3805
.uleb128 0
.uleb128 .LEHB2-.LFB3805
.uleb128 .LEHE2-.LEHB2
.uleb128 0
.uleb128 0
.uleb128 .LEHB3-.LFB3805
.uleb128 .LEHE3-.LEHB3
.uleb128 .L66-.LFB3805
.uleb128 0
.uleb128 .LEHB4-.LFB3805
.uleb128 .LEHE4-.LEHB4
.uleb128 0
.uleb128 0
.LLSDACSE3805:
.text
.size main, .-main
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.hidden DW.ref.__gxx_personality_v0
.weak DW.ref.__gxx_personality_v0
.section .data.rel.local.DW.ref.__gxx_personality_v0,"awG",@progbits,DW.ref.__gxx_personality_v0,comdat
.align 8
.type DW.ref.__gxx_personality_v0, @object
.size DW.ref.__gxx_personality_v0, 8
DW.ref.__gxx_personality_v0:
.quad __gxx_personality_v0
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
```
|
```amdasm
.text
.file "main.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z28__device_stub__jmeint_kernelPfS_S_S_S_S_Pbi # -- Begin function _Z28__device_stub__jmeint_kernelPfS_S_S_S_S_Pbi
.type _Z28__device_stub__jmeint_kernelPfS_S_S_S_S_Pbi,@function
_Z28__device_stub__jmeint_kernelPfS_S_S_S_S_Pbi: # @_Z28__device_stub__jmeint_kernelPfS_S_S_S_S_Pbi
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $160, %rsp
.cfi_def_cfa_offset 208
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 56(%rsp), %rax
movq %rdi, (%rax)
leaq 48(%rsp), %rdi
movq %rsi, (%rdi)
leaq 40(%rsp), %rsi
movq %rdx, (%rsi)
leaq 32(%rsp), %rdx
movq %rcx, (%rdx)
leaq 24(%rsp), %rcx
movq %r8, (%rcx)
leaq 16(%rsp), %r8
movq %r9, (%r8)
leaq 96(%rsp), %rbx
movq %rax, (%rbx)
movq %rdi, 8(%rbx)
movq %rsi, 16(%rbx)
movq %rdx, 24(%rbx)
movq %rcx, 32(%rbx)
movq %r8, 40(%rbx)
leaq 208(%rsp), %rax
movq %rax, 48(%rbx)
leaq 216(%rsp), %rax
movq %rax, 56(%rbx)
leaq 80(%rsp), %r14
leaq 64(%rsp), %r15
leaq 8(%rsp), %r12
movq %rsp, %r13
movq %r14, %rdi
movq %r15, %rsi
movq %r12, %rdx
movq %r13, %rcx
callq __hipPopCallConfiguration
movq (%r14), %rsi
movl 8(%r14), %edx
movq (%r15), %rcx
movl 8(%r15), %r8d
movl $_Z13jmeint_kernelPfS_S_S_S_S_Pbi, %edi
movq %rbx, %r9
pushq (%r13)
.cfi_adjust_cfa_offset 8
pushq (%r12)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $176, %rsp
.cfi_adjust_cfa_offset -176
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z28__device_stub__jmeint_kernelPfS_S_S_S_S_Pbi, .Lfunc_end0-_Z28__device_stub__jmeint_kernelPfS_S_S_S_S_Pbi
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.type main,@function
main: # @main
.Lfunc_begin0:
.cfi_startproc
.cfi_personality 3, __gxx_personality_v0
.cfi_lsda 3, .Lexception0
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $1144, %rsp # imm = 0x478
.cfi_def_cfa_offset 1200
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
cmpl $3, %edi
jne .LBB1_112
# %bb.1:
movq %rsi, %rbx
movl $0, 4(%rsp)
movq 8(%rsi), %rsi
.cfi_escape 0x2e, 0x00
leaq 624(%rsp), %rdi
movl $8, %edx
callq _ZNSt14basic_ifstreamIcSt11char_traitsIcEEC1EPKcSt13_Ios_Openmode
movq 16(%rbx), %rsi
.Ltmp0:
.cfi_escape 0x2e, 0x00
leaq 112(%rsp), %rdi
movl $16, %edx
callq _ZNSt14basic_ofstreamIcSt11char_traitsIcEEC1EPKcSt13_Ios_Openmode
.Ltmp1:
# %bb.2:
leaq 744(%rsp), %rdi
.cfi_escape 0x2e, 0x00
callq _ZNKSt12__basic_fileIcE7is_openEv
testb %al, %al
je .LBB1_9
# %bb.3:
.Ltmp3:
.cfi_escape 0x2e, 0x00
leaq 624(%rsp), %rdi
leaq 4(%rsp), %rsi
callq _ZNSirsERi
.Ltmp4:
# %bb.4:
.Ltmp5:
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
movl $.L.str.1, %esi
movl $14, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp6:
# %bb.5: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit
movl 4(%rsp), %esi
.Ltmp7:
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
callq _ZNSolsEi
.Ltmp8:
# %bb.6:
movq %rax, %rbx
movq (%rax), %rax
movq -24(%rax), %rdi
addq %rbx, %rdi
.Ltmp9:
.cfi_escape 0x2e, 0x00
movl $10, %esi
callq _ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
.Ltmp10:
# %bb.7: # %.noexc
.Ltmp11:
.cfi_escape 0x2e, 0x00
movsbl %al, %esi
movq %rbx, %rdi
callq _ZNSo3putEc
.Ltmp12:
# %bb.8: # %.noexc147
.Ltmp13:
.cfi_escape 0x2e, 0x00
movq %rax, %rdi
callq _ZNSo5flushEv
.Ltmp14:
.LBB1_9: # %_ZNSolsEPFRSoS_E.exit
movslq 4(%rsp), %rbx
.cfi_escape 0x2e, 0x00
movl $_ZSt7nothrow, %esi
movq %rbx, %rdi
callq _ZnamRKSt9nothrow_t
movq %rax, %r15
movl $12, %ecx
movq %rbx, %rax
mulq %rcx
movq $-1, %rbx
cmovnoq %rax, %rbx
.cfi_escape 0x2e, 0x00
movl $_ZSt7nothrow, %esi
movq %rbx, %rdi
callq _ZnamRKSt9nothrow_t
movq %rax, 16(%rsp) # 8-byte Spill
testq %rax, %rax
je .LBB1_113
# %bb.10:
.cfi_escape 0x2e, 0x00
movl $_ZSt7nothrow, %esi
movq %rbx, %rdi
callq _ZnamRKSt9nothrow_t
movq %rax, 8(%rsp) # 8-byte Spill
testq %rax, %rax
je .LBB1_117
# %bb.11:
.cfi_escape 0x2e, 0x00
movl $_ZSt7nothrow, %esi
movq %rbx, %rdi
callq _ZnamRKSt9nothrow_t
testq %rax, %rax
je .LBB1_120
# %bb.12:
movq %rax, %r13
.cfi_escape 0x2e, 0x00
movl $_ZSt7nothrow, %esi
movq %rbx, %rdi
callq _ZnamRKSt9nothrow_t
testq %rax, %rax
je .LBB1_123
# %bb.13:
movq %rax, %rbp
.cfi_escape 0x2e, 0x00
movl $_ZSt7nothrow, %esi
movq %rbx, %rdi
callq _ZnamRKSt9nothrow_t
testq %rax, %rax
je .LBB1_126
# %bb.14:
movq %rax, %r14
.cfi_escape 0x2e, 0x00
movl $_ZSt7nothrow, %esi
movq %rbx, %rdi
callq _ZnamRKSt9nothrow_t
testq %rax, %rax
je .LBB1_129
# %bb.15:
.Ltmp15:
movq %rax, %rbx
movq %r15, 32(%rsp) # 8-byte Spill
.cfi_escape 0x2e, 0x00
leaq 96(%rsp), %rdi
callq hipEventCreate
.Ltmp16:
# %bb.16:
.Ltmp17:
.cfi_escape 0x2e, 0x00
leaq 24(%rsp), %rdi
callq hipEventCreate
.Ltmp18:
# %bb.17: # %.preheader183
cmpl $0, 4(%rsp)
jle .LBB1_38
# %bb.18: # %.lr.ph.preheader
xorl %r15d, %r15d
xorl %r12d, %r12d
.LBB1_19: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movq 16(%rsp), %rax # 8-byte Reload
leaq (%rax,%r15), %rsi
.Ltmp20:
.cfi_escape 0x2e, 0x00
leaq 624(%rsp), %rdi
callq _ZNSi10_M_extractIfEERSiRT_
.Ltmp21:
# %bb.20: # %_ZNSirsERf.exit
# in Loop: Header=BB1_19 Depth=1
movq 16(%rsp), %rcx # 8-byte Reload
leaq (%rcx,%r15), %rsi
addq $4, %rsi
.Ltmp22:
.cfi_escape 0x2e, 0x00
movq %rax, %rdi
callq _ZNSi10_M_extractIfEERSiRT_
.Ltmp23:
# %bb.21: # %_ZNSirsERf.exit115
# in Loop: Header=BB1_19 Depth=1
movq 16(%rsp), %rcx # 8-byte Reload
leaq (%rcx,%r15), %rsi
addq $8, %rsi
.Ltmp24:
.cfi_escape 0x2e, 0x00
movq %rax, %rdi
callq _ZNSi10_M_extractIfEERSiRT_
.Ltmp25:
# %bb.22: # %_ZNSirsERf.exit116
# in Loop: Header=BB1_19 Depth=1
movq 8(%rsp), %rcx # 8-byte Reload
leaq (%rcx,%r15), %rsi
.Ltmp26:
.cfi_escape 0x2e, 0x00
movq %rax, %rdi
callq _ZNSi10_M_extractIfEERSiRT_
.Ltmp27:
# %bb.23: # %_ZNSirsERf.exit117
# in Loop: Header=BB1_19 Depth=1
movq 8(%rsp), %rcx # 8-byte Reload
leaq (%rcx,%r15), %rsi
addq $4, %rsi
.Ltmp28:
.cfi_escape 0x2e, 0x00
movq %rax, %rdi
callq _ZNSi10_M_extractIfEERSiRT_
.Ltmp29:
# %bb.24: # %_ZNSirsERf.exit118
# in Loop: Header=BB1_19 Depth=1
movq 8(%rsp), %rcx # 8-byte Reload
leaq (%rcx,%r15), %rsi
addq $8, %rsi
.Ltmp30:
.cfi_escape 0x2e, 0x00
movq %rax, %rdi
callq _ZNSi10_M_extractIfEERSiRT_
.Ltmp31:
# %bb.25: # %_ZNSirsERf.exit119
# in Loop: Header=BB1_19 Depth=1
leaq (%r15,%r13), %rsi
.Ltmp32:
.cfi_escape 0x2e, 0x00
movq %rax, %rdi
callq _ZNSi10_M_extractIfEERSiRT_
.Ltmp33:
# %bb.26: # %_ZNSirsERf.exit120
# in Loop: Header=BB1_19 Depth=1
leaq (%r15,%r13), %rsi
addq $4, %rsi
.Ltmp34:
.cfi_escape 0x2e, 0x00
movq %rax, %rdi
callq _ZNSi10_M_extractIfEERSiRT_
.Ltmp35:
# %bb.27: # %_ZNSirsERf.exit121
# in Loop: Header=BB1_19 Depth=1
leaq (%r15,%r13), %rsi
addq $8, %rsi
.Ltmp36:
.cfi_escape 0x2e, 0x00
movq %rax, %rdi
callq _ZNSi10_M_extractIfEERSiRT_
.Ltmp37:
# %bb.28: # %_ZNSirsERf.exit122
# in Loop: Header=BB1_19 Depth=1
leaq (%r15,%rbp), %rsi
.Ltmp38:
.cfi_escape 0x2e, 0x00
movq %rax, %rdi
callq _ZNSi10_M_extractIfEERSiRT_
.Ltmp39:
# %bb.29: # %_ZNSirsERf.exit123
# in Loop: Header=BB1_19 Depth=1
leaq (%r15,%rbp), %rsi
addq $4, %rsi
.Ltmp40:
.cfi_escape 0x2e, 0x00
movq %rax, %rdi
callq _ZNSi10_M_extractIfEERSiRT_
.Ltmp41:
# %bb.30: # %_ZNSirsERf.exit124
# in Loop: Header=BB1_19 Depth=1
leaq (%r15,%rbp), %rsi
addq $8, %rsi
.Ltmp42:
.cfi_escape 0x2e, 0x00
movq %rax, %rdi
callq _ZNSi10_M_extractIfEERSiRT_
.Ltmp43:
# %bb.31: # %_ZNSirsERf.exit125
# in Loop: Header=BB1_19 Depth=1
leaq (%r14,%r15), %rsi
.Ltmp44:
.cfi_escape 0x2e, 0x00
movq %rax, %rdi
callq _ZNSi10_M_extractIfEERSiRT_
.Ltmp45:
# %bb.32: # %_ZNSirsERf.exit126
# in Loop: Header=BB1_19 Depth=1
leaq (%r14,%r15), %rsi
addq $4, %rsi
.Ltmp46:
.cfi_escape 0x2e, 0x00
movq %rax, %rdi
callq _ZNSi10_M_extractIfEERSiRT_
.Ltmp47:
# %bb.33: # %_ZNSirsERf.exit127
# in Loop: Header=BB1_19 Depth=1
leaq (%r14,%r15), %rsi
addq $8, %rsi
.Ltmp48:
.cfi_escape 0x2e, 0x00
movq %rax, %rdi
callq _ZNSi10_M_extractIfEERSiRT_
.Ltmp49:
# %bb.34: # %_ZNSirsERf.exit128
# in Loop: Header=BB1_19 Depth=1
leaq (%rbx,%r15), %rsi
.Ltmp50:
.cfi_escape 0x2e, 0x00
movq %rax, %rdi
callq _ZNSi10_M_extractIfEERSiRT_
.Ltmp51:
# %bb.35: # %_ZNSirsERf.exit129
# in Loop: Header=BB1_19 Depth=1
leaq (%rbx,%r15), %rsi
addq $4, %rsi
.Ltmp52:
.cfi_escape 0x2e, 0x00
movq %rax, %rdi
callq _ZNSi10_M_extractIfEERSiRT_
.Ltmp53:
# %bb.36: # %_ZNSirsERf.exit130
# in Loop: Header=BB1_19 Depth=1
leaq (%rbx,%r15), %rsi
addq $8, %rsi
.Ltmp54:
.cfi_escape 0x2e, 0x00
movq %rax, %rdi
callq _ZNSi10_M_extractIfEERSiRT_
.Ltmp55:
# %bb.37: # %_ZNSirsERf.exit131
# in Loop: Header=BB1_19 Depth=1
incq %r12
movslq 4(%rsp), %rax
addq $12, %r15
cmpq %rax, %r12
jl .LBB1_19
.LBB1_38: # %._crit_edge
.Ltmp57:
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %r15d
movl $_ZSt4cout, %edi
movl $.L.str.3, %esi
movl $35, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp58:
# %bb.39: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit132
movq _ZSt4cout(%rip), %rax
addq -24(%rax), %r15
.Ltmp59:
.cfi_escape 0x2e, 0x00
movq %r15, %rdi
movl $10, %esi
callq _ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
.Ltmp60:
# %bb.40: # %.noexc149
.Ltmp61:
.cfi_escape 0x2e, 0x00
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
.Ltmp62:
# %bb.41: # %.noexc150
.Ltmp63:
.cfi_escape 0x2e, 0x00
movq %rax, %rdi
callq _ZNSo5flushEv
.Ltmp64:
# %bb.42: # %_ZNSolsEPFRSoS_E.exit133
movslq 4(%rsp), %rax
shlq $2, %rax
leaq (%rax,%rax,2), %rsi
.Ltmp66:
.cfi_escape 0x2e, 0x00
leaq 88(%rsp), %rdi
callq hipMalloc
.Ltmp67:
leaq 112(%rsp), %r12
# %bb.43:
movslq 4(%rsp), %rax
shlq $2, %rax
leaq (%rax,%rax,2), %rsi
.Ltmp68:
.cfi_escape 0x2e, 0x00
leaq 80(%rsp), %rdi
callq hipMalloc
.Ltmp69:
# %bb.44:
movslq 4(%rsp), %rax
shlq $2, %rax
leaq (%rax,%rax,2), %rsi
.Ltmp70:
.cfi_escape 0x2e, 0x00
leaq 72(%rsp), %rdi
callq hipMalloc
.Ltmp71:
# %bb.45:
movslq 4(%rsp), %rax
shlq $2, %rax
leaq (%rax,%rax,2), %rsi
.Ltmp72:
.cfi_escape 0x2e, 0x00
leaq 64(%rsp), %rdi
callq hipMalloc
.Ltmp73:
# %bb.46:
movslq 4(%rsp), %rax
shlq $2, %rax
leaq (%rax,%rax,2), %rsi
.Ltmp74:
.cfi_escape 0x2e, 0x00
leaq 56(%rsp), %rdi
callq hipMalloc
.Ltmp75:
# %bb.47:
movslq 4(%rsp), %rax
shlq $2, %rax
leaq (%rax,%rax,2), %rsi
.Ltmp76:
.cfi_escape 0x2e, 0x00
leaq 48(%rsp), %rdi
callq hipMalloc
.Ltmp77:
# %bb.48:
movslq 4(%rsp), %rsi
.Ltmp78:
.cfi_escape 0x2e, 0x00
leaq 40(%rsp), %rdi
callq hipMalloc
.Ltmp79:
# %bb.49:
.Ltmp80:
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %r15d
movl $_ZSt4cout, %edi
movl $.L.str.4, %esi
movl $37, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp81:
# %bb.50: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit134
movq _ZSt4cout(%rip), %rax
addq -24(%rax), %r15
.Ltmp82:
.cfi_escape 0x2e, 0x00
movq %r15, %rdi
movl $10, %esi
callq _ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
.Ltmp83:
# %bb.51: # %.noexc153
.Ltmp84:
.cfi_escape 0x2e, 0x00
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
.Ltmp85:
# %bb.52: # %.noexc154
.Ltmp86:
.cfi_escape 0x2e, 0x00
movq %rax, %rdi
callq _ZNSo5flushEv
.Ltmp87:
# %bb.53: # %_ZNSolsEPFRSoS_E.exit135
movq 88(%rsp), %rdi
movslq 4(%rsp), %rax
shlq $2, %rax
leaq (%rax,%rax,2), %rdx
.Ltmp88:
.cfi_escape 0x2e, 0x00
movq 16(%rsp), %rsi # 8-byte Reload
movl $1, %ecx
callq hipMemcpy
.Ltmp89:
# %bb.54:
movq 80(%rsp), %rdi
movslq 4(%rsp), %rax
shlq $2, %rax
leaq (%rax,%rax,2), %rdx
.Ltmp90:
.cfi_escape 0x2e, 0x00
movq 8(%rsp), %rsi # 8-byte Reload
movl $1, %ecx
callq hipMemcpy
.Ltmp91:
# %bb.55:
movq 72(%rsp), %rdi
movslq 4(%rsp), %rax
shlq $2, %rax
leaq (%rax,%rax,2), %rdx
.Ltmp92:
.cfi_escape 0x2e, 0x00
movq %r13, %rsi
movl $1, %ecx
callq hipMemcpy
.Ltmp93:
# %bb.56:
movq 64(%rsp), %rdi
movslq 4(%rsp), %rax
shlq $2, %rax
leaq (%rax,%rax,2), %rdx
.Ltmp94:
.cfi_escape 0x2e, 0x00
movq %rbp, %rsi
movl $1, %ecx
callq hipMemcpy
.Ltmp95:
# %bb.57:
movq 56(%rsp), %rdi
movslq 4(%rsp), %rax
shlq $2, %rax
leaq (%rax,%rax,2), %rdx
.Ltmp96:
.cfi_escape 0x2e, 0x00
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
.Ltmp97:
# %bb.58:
movq 48(%rsp), %rdi
movslq 4(%rsp), %rax
shlq $2, %rax
leaq (%rax,%rax,2), %rdx
.Ltmp98:
.cfi_escape 0x2e, 0x00
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
.Ltmp99:
# %bb.59:
.Ltmp100:
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %r15d
movl $_ZSt4cout, %edi
movl $.L.str.5, %esi
movl $31, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp101:
# %bb.60: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit136
movq _ZSt4cout(%rip), %rax
addq -24(%rax), %r15
.Ltmp102:
.cfi_escape 0x2e, 0x00
movq %r15, %rdi
movl $10, %esi
callq _ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
.Ltmp103:
# %bb.61: # %.noexc157
.Ltmp104:
.cfi_escape 0x2e, 0x00
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
.Ltmp105:
# %bb.62: # %.noexc158
.Ltmp106:
.cfi_escape 0x2e, 0x00
movq %rax, %rdi
callq _ZNSo5flushEv
.Ltmp107:
# %bb.63: # %_ZNSolsEPFRSoS_E.exit137
movl 4(%rsp), %r15d
movq 96(%rsp), %rdi
.Ltmp109:
.cfi_escape 0x2e, 0x00
xorl %esi, %esi
callq hipEventRecord
.Ltmp110:
# %bb.64:
leal 511(%r15), %edi
testl %r15d, %r15d
cmovnsl %r15d, %edi
sarl $9, %edi
btsq $32, %rdi
.Ltmp111:
.cfi_escape 0x2e, 0x00
movabsq $4294967808, %rdx # imm = 0x100000200
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
.Ltmp112:
# %bb.65:
testl %eax, %eax
jne .LBB1_67
# %bb.66:
movq 88(%rsp), %rdi
movq 80(%rsp), %rsi
movq 72(%rsp), %rdx
movq 64(%rsp), %rcx
movq 56(%rsp), %r8
movq 48(%rsp), %r9
movl 4(%rsp), %eax
.Ltmp113:
.cfi_escape 0x2e, 0x10
pushq %rax
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq _Z28__device_stub__jmeint_kernelPfS_S_S_S_S_Pbi
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.Ltmp114:
.LBB1_67:
.Ltmp115:
.cfi_escape 0x2e, 0x00
callq hipDeviceSynchronize
.Ltmp116:
# %bb.68:
movl %eax, %r15d
testl %eax, %eax
je .LBB1_74
# %bb.69:
.Ltmp117:
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
movl $.L.str.6, %esi
movl $33, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp118:
# %bb.70: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit138
.Ltmp119:
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
movl %r15d, %esi
callq _ZNSolsEi
.Ltmp120:
# %bb.71:
movq %rax, %r15
movq (%rax), %rax
movq -24(%rax), %rdi
addq %r15, %rdi
.Ltmp121:
.cfi_escape 0x2e, 0x00
movl $10, %esi
callq _ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
.Ltmp122:
# %bb.72: # %.noexc161
.Ltmp123:
.cfi_escape 0x2e, 0x00
movsbl %al, %esi
movq %r15, %rdi
callq _ZNSo3putEc
.Ltmp124:
# %bb.73: # %.noexc162
.Ltmp125:
.cfi_escape 0x2e, 0x00
movq %rax, %rdi
callq _ZNSo5flushEv
.Ltmp126:
.LBB1_74: # %_ZNSolsEPFRSoS_E.exit139
movq 24(%rsp), %rdi
.Ltmp127:
.cfi_escape 0x2e, 0x00
xorl %esi, %esi
callq hipEventRecord
.Ltmp128:
# %bb.75:
movq 24(%rsp), %rdi
.Ltmp129:
.cfi_escape 0x2e, 0x00
callq hipEventSynchronize
.Ltmp130:
# %bb.76:
movq 96(%rsp), %rsi
movq 24(%rsp), %rdx
.Ltmp132:
.cfi_escape 0x2e, 0x00
leaq 108(%rsp), %rdi
callq hipEventElapsedTime
.Ltmp133:
# %bb.77:
movq 96(%rsp), %rdi
.Ltmp134:
.cfi_escape 0x2e, 0x00
callq hipEventDestroy
.Ltmp135:
# %bb.78:
movq 24(%rsp), %rdi
.Ltmp136:
.cfi_escape 0x2e, 0x00
callq hipEventDestroy
.Ltmp137:
# %bb.79:
.Ltmp138:
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
movl $.L.str.7, %esi
movl $36, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp139:
# %bb.80: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit140
cvtss2sd 108(%rsp), %xmm0
.Ltmp140:
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
.Ltmp141:
# %bb.81: # %_ZNSolsEf.exit
movq %rax, %r15
movq (%rax), %rax
movq -24(%rax), %rdi
addq %r15, %rdi
.Ltmp142:
.cfi_escape 0x2e, 0x00
movl $10, %esi
callq _ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
.Ltmp143:
# %bb.82: # %.noexc165
.Ltmp144:
.cfi_escape 0x2e, 0x00
movsbl %al, %esi
movq %r15, %rdi
callq _ZNSo3putEc
.Ltmp145:
# %bb.83: # %.noexc166
.Ltmp146:
.cfi_escape 0x2e, 0x00
movq %rax, %rdi
callq _ZNSo5flushEv
.Ltmp147:
# %bb.84: # %_ZNSolsEPFRSoS_E.exit141
.Ltmp148:
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %r15d
movl $_ZSt4cout, %edi
movl $.L.str.8, %esi
movl $29, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp149:
# %bb.85: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit142
movq _ZSt4cout(%rip), %rax
addq -24(%rax), %r15
.Ltmp150:
.cfi_escape 0x2e, 0x00
movq %r15, %rdi
movl $10, %esi
callq _ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
.Ltmp151:
# %bb.86: # %.noexc169
.Ltmp152:
.cfi_escape 0x2e, 0x00
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
.Ltmp153:
# %bb.87: # %.noexc170
.Ltmp154:
.cfi_escape 0x2e, 0x00
movq %rax, %rdi
callq _ZNSo5flushEv
.Ltmp155:
# %bb.88: # %_ZNSolsEPFRSoS_E.exit143
movq 40(%rsp), %rsi
movslq 4(%rsp), %rdx
.Ltmp156:
.cfi_escape 0x2e, 0x00
movq 32(%rsp), %rdi # 8-byte Reload
movl $2, %ecx
callq hipMemcpy
.Ltmp157:
# %bb.89: # %.preheader
cmpl $0, 4(%rsp)
jle .LBB1_96
# %bb.90: # %.lr.ph186.preheader
xorl %r15d, %r15d
.LBB1_91: # %.lr.ph186
# =>This Inner Loop Header: Depth=1
movq 32(%rsp), %rax # 8-byte Reload
movzbl (%rax,%r15), %esi
.Ltmp158:
.cfi_escape 0x2e, 0x00
movq %r12, %rdi
callq _ZNSo9_M_insertIbEERSoT_
.Ltmp159:
# %bb.92: # %_ZNSolsEb.exit
# in Loop: Header=BB1_91 Depth=1
movq 112(%rsp), %rax
movq -24(%rax), %rdi
addq %r12, %rdi
.Ltmp160:
.cfi_escape 0x2e, 0x00
movl $10, %esi
callq _ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
.Ltmp161:
# %bb.93: # %.noexc173
# in Loop: Header=BB1_91 Depth=1
.Ltmp162:
.cfi_escape 0x2e, 0x00
movsbl %al, %esi
movq %r12, %rdi
callq _ZNSo3putEc
.Ltmp163:
# %bb.94: # %.noexc174
# in Loop: Header=BB1_91 Depth=1
.Ltmp164:
.cfi_escape 0x2e, 0x00
movq %rax, %rdi
callq _ZNSo5flushEv
.Ltmp165:
# %bb.95: # %_ZNSolsEPFRSoS_E.exit144
# in Loop: Header=BB1_91 Depth=1
incq %r15
movslq 4(%rsp), %rax
cmpq %rax, %r15
jl .LBB1_91
.LBB1_96: # %._crit_edge187
.Ltmp167:
.cfi_escape 0x2e, 0x00
leaq 624(%rsp), %rdi
callq _ZNSt14basic_ifstreamIcSt11char_traitsIcEE5closeEv
.Ltmp168:
# %bb.97:
.Ltmp169:
.cfi_escape 0x2e, 0x00
leaq 112(%rsp), %rdi
callq _ZNSt14basic_ofstreamIcSt11char_traitsIcEE5closeEv
.Ltmp170:
# %bb.98:
.cfi_escape 0x2e, 0x00
movq 16(%rsp), %rdi # 8-byte Reload
callq _ZdaPv
.cfi_escape 0x2e, 0x00
movq 8(%rsp), %rdi # 8-byte Reload
callq _ZdaPv
.cfi_escape 0x2e, 0x00
movq %r13, %rdi
callq _ZdaPv
.cfi_escape 0x2e, 0x00
movq %rbp, %rdi
callq _ZdaPv
.cfi_escape 0x2e, 0x00
movq %r14, %rdi
callq _ZdaPv
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
callq _ZdaPv
movq 32(%rsp), %rdi # 8-byte Reload
testq %rdi, %rdi
je .LBB1_100
# %bb.99:
.cfi_escape 0x2e, 0x00
callq _ZdaPv
.LBB1_100:
movq 88(%rsp), %rdi
.Ltmp171:
.cfi_escape 0x2e, 0x00
callq hipFree
.Ltmp172:
# %bb.101:
movq 80(%rsp), %rdi
.Ltmp173:
.cfi_escape 0x2e, 0x00
callq hipFree
.Ltmp174:
# %bb.102:
movq 72(%rsp), %rdi
.Ltmp175:
.cfi_escape 0x2e, 0x00
callq hipFree
.Ltmp176:
# %bb.103:
movq 64(%rsp), %rdi
.Ltmp177:
.cfi_escape 0x2e, 0x00
callq hipFree
.Ltmp178:
# %bb.104:
movq 56(%rsp), %rdi
.Ltmp179:
.cfi_escape 0x2e, 0x00
callq hipFree
.Ltmp180:
# %bb.105:
movq 48(%rsp), %rdi
.Ltmp181:
.cfi_escape 0x2e, 0x00
callq hipFree
.Ltmp182:
# %bb.106:
movq 40(%rsp), %rdi
.Ltmp183:
.cfi_escape 0x2e, 0x00
callq hipFree
.Ltmp184:
# %bb.107:
.Ltmp185:
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %ebx
movl $_ZSt4cout, %edi
movl $.L.str.9, %esi
movl $12, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp186:
# %bb.108: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit145
movq _ZSt4cout(%rip), %rax
addq -24(%rax), %rbx
.Ltmp187:
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
movl $10, %esi
callq _ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
.Ltmp188:
# %bb.109: # %.noexc177
.Ltmp189:
.cfi_escape 0x2e, 0x00
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
.Ltmp190:
# %bb.110: # %.noexc178
.Ltmp191:
.cfi_escape 0x2e, 0x00
movq %rax, %rdi
callq _ZNSo5flushEv
.Ltmp192:
# %bb.111: # %_ZNSolsEPFRSoS_E.exit146
movq _ZTTSt14basic_ofstreamIcSt11char_traitsIcEE(%rip), %rax
leaq 120(%rsp), %rdi
movq %rax, -8(%rdi)
movq _ZTTSt14basic_ofstreamIcSt11char_traitsIcEE+24(%rip), %rcx
movq -24(%rax), %rax
movq %rcx, 112(%rsp,%rax)
.cfi_escape 0x2e, 0x00
callq _ZNSt13basic_filebufIcSt11char_traitsIcEED2Ev
leaq 360(%rsp), %rdi
.cfi_escape 0x2e, 0x00
callq _ZNSt8ios_baseD2Ev
.cfi_escape 0x2e, 0x00
leaq 624(%rsp), %rdi
callq _ZNSt14basic_ifstreamIcSt11char_traitsIcEED1Ev
xorl %eax, %eax
addq $1144, %rsp # imm = 0x478
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB1_112:
.cfi_def_cfa_offset 1200
.cfi_escape 0x2e, 0x00
movl $_ZSt4cerr, %edi
movl $.L.str, %esi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
.cfi_escape 0x2e, 0x00
movq %rax, %rdi
callq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_
.cfi_escape 0x2e, 0x00
.LBB1_116: # %_ZNSolsEPFRSoS_E.exit104
movl $1, %edi
callq exit
.LBB1_113:
.Ltmp214:
.cfi_escape 0x2e, 0x00
movl $_ZSt4cerr, %edi
movl $.L.str.2, %esi
movl $26, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp215:
# %bb.114: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit103
.Ltmp216:
.cfi_escape 0x2e, 0x00
movl $_ZSt4cerr, %edi
callq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_
.Ltmp217:
# %bb.115: # %_ZNSolsEPFRSoS_E.exit104
.cfi_escape 0x2e, 0x00
jmp .LBB1_116
.LBB1_117:
.Ltmp210:
.cfi_escape 0x2e, 0x00
movl $_ZSt4cerr, %edi
movl $.L.str.2, %esi
movl $26, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp211:
# %bb.118: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit105
.Ltmp212:
.cfi_escape 0x2e, 0x00
movl $_ZSt4cerr, %edi
callq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_
.Ltmp213:
# %bb.119: # %_ZNSolsEPFRSoS_E.exit106
.cfi_escape 0x2e, 0x00
jmp .LBB1_116
.LBB1_120:
.Ltmp206:
.cfi_escape 0x2e, 0x00
movl $_ZSt4cerr, %edi
movl $.L.str.2, %esi
movl $26, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp207:
# %bb.121: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit107
.Ltmp208:
.cfi_escape 0x2e, 0x00
movl $_ZSt4cerr, %edi
callq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_
.Ltmp209:
# %bb.122: # %_ZNSolsEPFRSoS_E.exit108
.cfi_escape 0x2e, 0x00
jmp .LBB1_116
.LBB1_123:
.Ltmp202:
.cfi_escape 0x2e, 0x00
movl $_ZSt4cerr, %edi
movl $.L.str.2, %esi
movl $26, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp203:
# %bb.124: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit109
.Ltmp204:
.cfi_escape 0x2e, 0x00
movl $_ZSt4cerr, %edi
callq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_
.Ltmp205:
# %bb.125: # %_ZNSolsEPFRSoS_E.exit110
.cfi_escape 0x2e, 0x00
jmp .LBB1_116
.LBB1_126:
.Ltmp198:
.cfi_escape 0x2e, 0x00
movl $_ZSt4cerr, %edi
movl $.L.str.2, %esi
movl $26, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp199:
# %bb.127: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit111
.Ltmp200:
.cfi_escape 0x2e, 0x00
movl $_ZSt4cerr, %edi
callq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_
.Ltmp201:
# %bb.128: # %_ZNSolsEPFRSoS_E.exit112
.cfi_escape 0x2e, 0x00
jmp .LBB1_116
.LBB1_129:
.Ltmp194:
.cfi_escape 0x2e, 0x00
movl $_ZSt4cerr, %edi
movl $.L.str.2, %esi
movl $26, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp195:
# %bb.130: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit113
.Ltmp196:
.cfi_escape 0x2e, 0x00
movl $_ZSt4cerr, %edi
callq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_
.Ltmp197:
# %bb.131: # %_ZNSolsEPFRSoS_E.exit114
.cfi_escape 0x2e, 0x00
jmp .LBB1_116
.LBB1_132:
.Ltmp2:
movq %rax, %rbx
jmp .LBB1_142
.LBB1_133:
.Ltmp19:
jmp .LBB1_141
.LBB1_134: # %.loopexit.split-lp
.Ltmp65:
jmp .LBB1_141
.LBB1_135:
.Ltmp218:
jmp .LBB1_141
.LBB1_136:
.Ltmp131:
jmp .LBB1_141
.LBB1_137:
.Ltmp108:
jmp .LBB1_141
.LBB1_138:
.Ltmp193:
jmp .LBB1_141
.LBB1_139:
.Ltmp166:
jmp .LBB1_141
.LBB1_140: # %.loopexit
.Ltmp56:
.LBB1_141:
movq %rax, %rbx
.cfi_escape 0x2e, 0x00
leaq 112(%rsp), %rdi
callq _ZNSt14basic_ofstreamIcSt11char_traitsIcEED1Ev
.LBB1_142:
.cfi_escape 0x2e, 0x00
leaq 624(%rsp), %rdi
callq _ZNSt14basic_ifstreamIcSt11char_traitsIcEED1Ev
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
callq _Unwind_Resume@PLT
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
.section .gcc_except_table,"a",@progbits
.p2align 2, 0x0
GCC_except_table1:
.Lexception0:
.byte 255 # @LPStart Encoding = omit
.byte 255 # @TType Encoding = omit
.byte 1 # Call site Encoding = uleb128
.uleb128 .Lcst_end0-.Lcst_begin0
.Lcst_begin0:
.uleb128 .Lfunc_begin0-.Lfunc_begin0 # >> Call Site 1 <<
.uleb128 .Ltmp0-.Lfunc_begin0 # Call between .Lfunc_begin0 and .Ltmp0
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp0-.Lfunc_begin0 # >> Call Site 2 <<
.uleb128 .Ltmp1-.Ltmp0 # Call between .Ltmp0 and .Ltmp1
.uleb128 .Ltmp2-.Lfunc_begin0 # jumps to .Ltmp2
.byte 0 # On action: cleanup
.uleb128 .Ltmp3-.Lfunc_begin0 # >> Call Site 3 <<
.uleb128 .Ltmp14-.Ltmp3 # Call between .Ltmp3 and .Ltmp14
.uleb128 .Ltmp218-.Lfunc_begin0 # jumps to .Ltmp218
.byte 0 # On action: cleanup
.uleb128 .Ltmp15-.Lfunc_begin0 # >> Call Site 4 <<
.uleb128 .Ltmp18-.Ltmp15 # Call between .Ltmp15 and .Ltmp18
.uleb128 .Ltmp19-.Lfunc_begin0 # jumps to .Ltmp19
.byte 0 # On action: cleanup
.uleb128 .Ltmp20-.Lfunc_begin0 # >> Call Site 5 <<
.uleb128 .Ltmp55-.Ltmp20 # Call between .Ltmp20 and .Ltmp55
.uleb128 .Ltmp56-.Lfunc_begin0 # jumps to .Ltmp56
.byte 0 # On action: cleanup
.uleb128 .Ltmp57-.Lfunc_begin0 # >> Call Site 6 <<
.uleb128 .Ltmp64-.Ltmp57 # Call between .Ltmp57 and .Ltmp64
.uleb128 .Ltmp65-.Lfunc_begin0 # jumps to .Ltmp65
.byte 0 # On action: cleanup
.uleb128 .Ltmp66-.Lfunc_begin0 # >> Call Site 7 <<
.uleb128 .Ltmp107-.Ltmp66 # Call between .Ltmp66 and .Ltmp107
.uleb128 .Ltmp108-.Lfunc_begin0 # jumps to .Ltmp108
.byte 0 # On action: cleanup
.uleb128 .Ltmp109-.Lfunc_begin0 # >> Call Site 8 <<
.uleb128 .Ltmp130-.Ltmp109 # Call between .Ltmp109 and .Ltmp130
.uleb128 .Ltmp131-.Lfunc_begin0 # jumps to .Ltmp131
.byte 0 # On action: cleanup
.uleb128 .Ltmp132-.Lfunc_begin0 # >> Call Site 9 <<
.uleb128 .Ltmp157-.Ltmp132 # Call between .Ltmp132 and .Ltmp157
.uleb128 .Ltmp193-.Lfunc_begin0 # jumps to .Ltmp193
.byte 0 # On action: cleanup
.uleb128 .Ltmp158-.Lfunc_begin0 # >> Call Site 10 <<
.uleb128 .Ltmp165-.Ltmp158 # Call between .Ltmp158 and .Ltmp165
.uleb128 .Ltmp166-.Lfunc_begin0 # jumps to .Ltmp166
.byte 0 # On action: cleanup
.uleb128 .Ltmp167-.Lfunc_begin0 # >> Call Site 11 <<
.uleb128 .Ltmp192-.Ltmp167 # Call between .Ltmp167 and .Ltmp192
.uleb128 .Ltmp193-.Lfunc_begin0 # jumps to .Ltmp193
.byte 0 # On action: cleanup
.uleb128 .Ltmp192-.Lfunc_begin0 # >> Call Site 12 <<
.uleb128 .Ltmp214-.Ltmp192 # Call between .Ltmp192 and .Ltmp214
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp214-.Lfunc_begin0 # >> Call Site 13 <<
.uleb128 .Ltmp197-.Ltmp214 # Call between .Ltmp214 and .Ltmp197
.uleb128 .Ltmp218-.Lfunc_begin0 # jumps to .Ltmp218
.byte 0 # On action: cleanup
.uleb128 .Ltmp197-.Lfunc_begin0 # >> Call Site 14 <<
.uleb128 .Lfunc_end1-.Ltmp197 # Call between .Ltmp197 and .Lfunc_end1
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.Lcst_end0:
.p2align 2, 0x0
# -- End function
.text
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, %rdi
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13jmeint_kernelPfS_S_S_S_S_Pbi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z13jmeint_kernelPfS_S_S_S_S_Pbi,@object # @_Z13jmeint_kernelPfS_S_S_S_S_Pbi
.section .rodata,"a",@progbits
.globl _Z13jmeint_kernelPfS_S_S_S_S_Pbi
.p2align 3, 0x0
_Z13jmeint_kernelPfS_S_S_S_S_Pbi:
.quad _Z28__device_stub__jmeint_kernelPfS_S_S_S_S_Pbi
.size _Z13jmeint_kernelPfS_S_S_S_S_Pbi, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Usage: ./jmeint.out <input file locations> <output file>"
.size .L.str, 57
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "# Data Size = "
.size .L.str.1, 15
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Memory allocation fails!!!"
.size .L.str.2, 27
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "# Coordinates are read from file..."
.size .L.str.3, 36
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "# Memory allocation on GPU is done..."
.size .L.str.4, 38
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "# Data are transfered to GPU..."
.size .L.str.5, 32
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "Something was wrong! Error code: "
.size .L.str.6, 34
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "# Elapsed Time in `jmeint` kernel = "
.size .L.str.7, 37
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "# GPU computation is done ..."
.size .L.str.8, 30
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "Thank you..."
.size .L.str.9, 13
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z13jmeint_kernelPfS_S_S_S_S_Pbi"
.size .L__unnamed_1, 33
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z28__device_stub__jmeint_kernelPfS_S_S_S_S_Pbi
.addrsig_sym __gxx_personality_v0
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Unwind_Resume
.addrsig_sym _Z13jmeint_kernelPfS_S_S_S_S_Pbi
.addrsig_sym _ZSt4cerr
.addrsig_sym _ZSt4cout
.addrsig_sym _ZSt7nothrow
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
```
| 12,302 | 17,973 |
410 |
Convert the following CUDA device assembly code to AMD device assembly:
```cudaasm
code for sm_80
```
|
```amdasm
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object ; @__hip_cuid_
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0 ; 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
```
| 24 | 306 |
411 |
Convert the following CUDA host assembly code to AMD host assembly:
```cudaasm
.file "tmpxft_00026c17_00000000-6_cuda_RandomForest_Constants.cudafe1.cpp"
.text
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
```
|
```amdasm
.text
.file "cuda_RandomForest_Constants.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
```
| 751 | 188 |
412 |
Convert the following CUDA device assembly code to AMD device assembly:
```cudaasm
code for sm_80
Function : _Z6VecAddPfS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
MOV R1, c[0x0][0x28] ;
S2R R6, SR_TID.X ;
HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ;
ULDC.64 UR4, c[0x0][0x118] ;
IMAD.WIDE R2, R6, R7, c[0x0][0x160] ;
IMAD.WIDE R4, R6.reuse, R7.reuse, c[0x0][0x168] ;
LDG.E R0, [R2.64] ;
LDG.E R9, [R4.64] ;
IMAD.WIDE R6, R6, R7, c[0x0][0x170] ;
FADD R9, R0, R9 ;
STG.E [R6.64], R9 ;
LDG.E R0, [R2.64] ;
LDG.E R11, [R4.64] ;
FADD R11, R0, R11 ;
STG.E [R6.64], R11 ;
EXIT ;
BRA 0x100;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
```
|
```amdasm
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6VecAddPfS_S_ ; -- Begin function _Z6VecAddPfS_S_
.globl _Z6VecAddPfS_S_
.p2align 8
.type _Z6VecAddPfS_S_,@function
_Z6VecAddPfS_S_: ; @_Z6VecAddPfS_S_
; %bb.0:
s_load_b128 s[4:7], s[0:1], 0x0
v_lshlrev_b32_e32 v0, 2, v0
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_clause 0x1
global_load_b32 v1, v0, s[4:5]
global_load_b32 v2, v0, s[6:7]
s_waitcnt vmcnt(0)
v_add_f32_e32 v1, v1, v2
global_store_b32 v0, v1, s[0:1]
s_clause 0x1
global_load_b32 v1, v0, s[4:5]
global_load_b32 v2, v0, s[6:7]
s_waitcnt vmcnt(0)
v_add_f32_e32 v1, v1, v2
global_store_b32 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6VecAddPfS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 8
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6VecAddPfS_S_, .Lfunc_end0-_Z6VecAddPfS_S_
; -- End function
.section .AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 108
; NumSgprs: 8
; NumVgprs: 3
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 0
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 8
; NumVGPRsForWavesPerEU: 3
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object ; @__hip_cuid_
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0 ; 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6VecAddPfS_S_
.private_segment_fixed_size: 0
.sgpr_count: 8
.sgpr_spill_count: 0
.symbol: _Z6VecAddPfS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
```
| 390 | 1,868 |
413 |
Convert the following CUDA host assembly code to AMD host assembly:
```cudaasm
.file "tmpxft_000473ee_00000000-6_vecadd-1-TestbyLPF.cudafe1.cpp"
.text
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z29__device_stub__Z6VecAddPfS_S_PfS_S_
.type _Z29__device_stub__Z6VecAddPfS_S_PfS_S_, @function
_Z29__device_stub__Z6VecAddPfS_S_PfS_S_:
.LFB2082:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z6VecAddPfS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z29__device_stub__Z6VecAddPfS_S_PfS_S_, .-_Z29__device_stub__Z6VecAddPfS_S_PfS_S_
.globl _Z6VecAddPfS_S_
.type _Z6VecAddPfS_S_, @function
_Z6VecAddPfS_S_:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z6VecAddPfS_S_PfS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z6VecAddPfS_S_, .-_Z6VecAddPfS_S_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC3:
.string "[Pthread%d]\t%.2f + %.2f = %.2f\n"
.align 8
.LC4:
.string "[MemoryV%d]\t%.2f + %.2f = %.2f\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $72, %rsp
.cfi_def_cfa_offset 128
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl $40, %edi
call malloc@PLT
movq %rax, %r12
movl $40, %edi
call malloc@PLT
movq %rax, %rbp
movl $40, %edi
call malloc@PLT
movq %rax, %r13
movl $0, %eax
movss .LC0(%rip), %xmm1
.L12:
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
addss %xmm1, %xmm0
movss %xmm0, (%r12,%rax,4)
addq $1, %rax
cmpq $10, %rax
jne .L12
movl $0, %eax
movss .LC1(%rip), %xmm1
.L13:
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
addss %xmm1, %xmm0
movss %xmm0, 0(%rbp,%rax,4)
addq $1, %rax
cmpq $10, %rax
jne .L13
leaq 8(%rsp), %rdi
movl $40, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $40, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $40, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $40, %edx
movq %r12, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $40, %edx
movq %rbp, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $40, %edx
movq %r13, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl $5, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L26
.L14:
movl $2, %ecx
movl $40, %edx
movq 24(%rsp), %rsi
movq %r13, %rdi
call cudaMemcpy@PLT
movl $0, %ebx
leaq .LC4(%rip), %r15
leaq .LC3(%rip), %r14
jmp .L18
.L26:
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z29__device_stub__Z6VecAddPfS_S_PfS_S_
jmp .L14
.L24:
pxor %xmm0, %xmm0
cvtss2sd (%r12,%rbx,4), %xmm0
cvtss2sd %xmm2, %xmm2
pxor %xmm1, %xmm1
cvtss2sd 0(%rbp,%rbx,4), %xmm1
movq %r15, %rsi
movl $2, %edi
movl $3, %eax
call __printf_chk@PLT
.L17:
addq $1, %rbx
cmpq $10, %rbx
je .L27
.L18:
movl %ebx, %edx
movss 0(%r13,%rbx,4), %xmm2
pxor %xmm3, %xmm3
comiss %xmm3, %xmm2
jbe .L24
pxor %xmm0, %xmm0
cvtss2sd (%r12,%rbx,4), %xmm0
cvtss2sd %xmm2, %xmm2
pxor %xmm1, %xmm1
cvtss2sd 0(%rbp,%rbx,4), %xmm1
movq %r14, %rsi
movl $2, %edi
movl $3, %eax
call __printf_chk@PLT
jmp .L17
.L27:
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq %r12, %rdi
call free@PLT
movq %rbp, %rdi
call free@PLT
movq %r13, %rdi
call free@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L28
movl $0, %eax
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L28:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC5:
.string "_Z6VecAddPfS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _Z6VecAddPfS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC0:
.long 1065353216
.align 4
.LC1:
.long 1120403456
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
```
|
```amdasm
.text
.file "vecadd-1-TestbyLPF.hip"
.globl _Z21__device_stub__VecAddPfS_S_ # -- Begin function _Z21__device_stub__VecAddPfS_S_
.type _Z21__device_stub__VecAddPfS_S_,@function
_Z21__device_stub__VecAddPfS_S_: # @_Z21__device_stub__VecAddPfS_S_
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $112, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 40(%rsp), %rax
movq %rdi, (%rax)
leaq 32(%rsp), %rcx
movq %rsi, (%rcx)
leaq 24(%rsp), %rsi
movq %rdx, (%rsi)
leaq 80(%rsp), %rbx
movq %rax, (%rbx)
movq %rcx, 8(%rbx)
movq %rsi, 16(%rbx)
leaq 64(%rsp), %r14
leaq 48(%rsp), %r15
leaq 16(%rsp), %r12
leaq 8(%rsp), %r13
movq %r14, %rdi
movq %r15, %rsi
movq %r12, %rdx
movq %r13, %rcx
callq __hipPopCallConfiguration
movq (%r14), %rsi
movl 8(%r14), %edx
movq (%r15), %rcx
movl 8(%r15), %r8d
movl $_Z6VecAddPfS_S_, %edi
movq %rbx, %r9
pushq (%r13)
.cfi_adjust_cfa_offset 8
pushq (%r12)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $128, %rsp
.cfi_adjust_cfa_offset -128
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z21__device_stub__VecAddPfS_S_, .Lfunc_end0-_Z21__device_stub__VecAddPfS_S_
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI1_0:
.long 0x00000000 # float 0
.text
.globl main
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $24, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $40, %edi
callq malloc
movq %rax, %rbx
movl $40, %edi
callq malloc
movq %rax, %r14
movl $40, %edi
callq malloc
movq %rax, %r15
xorl %eax, %eax
.LBB1_1: # =>This Inner Loop Header: Depth=1
leaq 1(%rax), %rcx
xorps %xmm0, %xmm0
cvtsi2ss %ecx, %xmm0
movss %xmm0, (%rbx,%rax,4)
movq %rcx, %rax
cmpq $10, %rcx
jne .LBB1_1
# %bb.2: # %.preheader.preheader
xorl %eax, %eax
.LBB1_3: # %.preheader
# =>This Inner Loop Header: Depth=1
leal 100(%rax), %ecx
xorps %xmm0, %xmm0
cvtsi2ss %ecx, %xmm0
movss %xmm0, (%r14,%rax,4)
incq %rax
cmpq $10, %rax
jne .LBB1_3
# %bb.4:
leaq 16(%rsp), %r12
movl $40, %esi
movq %r12, %rdi
callq hipMalloc
leaq 8(%rsp), %r13
movl $40, %esi
movq %r13, %rdi
callq hipMalloc
movq %rsp, %rbp
movl $40, %esi
movq %rbp, %rdi
callq hipMalloc
movq (%r12), %rdi
movl $40, %edx
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq (%r13), %rdi
movl $40, %edx
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movq (%rbp), %rdi
movl $40, %edx
movq %r15, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 4(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_6
# %bb.5:
movq 16(%rsp), %rdi
movq 8(%rsp), %rsi
movq (%rsp), %rdx
callq _Z21__device_stub__VecAddPfS_S_
.LBB1_6:
movq (%rsp), %rsi
movl $40, %edx
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
xorl %r12d, %r12d
.LBB1_7: # =>This Inner Loop Header: Depth=1
movss (%r15,%r12,4), %xmm2 # xmm2 = mem[0],zero,zero,zero
ucomiss .LCPI1_0(%rip), %xmm2
movl $.L.str, %edi
ja .LBB1_9
# %bb.8: # in Loop: Header=BB1_7 Depth=1
movl $.L.str.1, %edi
.LBB1_9: # in Loop: Header=BB1_7 Depth=1
xorps %xmm0, %xmm0
cvtss2sd (%rbx,%r12,4), %xmm0
xorps %xmm1, %xmm1
cvtss2sd (%r14,%r12,4), %xmm1
cvtss2sd %xmm2, %xmm2
movl %r12d, %esi
movb $3, %al
callq printf
incq %r12
cmpq $10, %r12
jne .LBB1_7
# %bb.10:
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipFree
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
xorl %eax, %eax
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, %rdi
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6VecAddPfS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6VecAddPfS_S_,@object # @_Z6VecAddPfS_S_
.section .rodata,"a",@progbits
.globl _Z6VecAddPfS_S_
.p2align 3, 0x0
_Z6VecAddPfS_S_:
.quad _Z21__device_stub__VecAddPfS_S_
.size _Z6VecAddPfS_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "[Pthread%d]\t%.2f + %.2f = %.2f\n"
.size .L.str, 33
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "[MemoryV%d]\t%.2f + %.2f = %.2f\n"
.size .L.str.1, 33
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z6VecAddPfS_S_"
.size .L__unnamed_1, 16
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__VecAddPfS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6VecAddPfS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
```
| 3,779 | 3,835 |
416 |
Convert the following CUDA device assembly code to AMD device assembly:
```cudaasm
code for sm_80
Function : _Z11addArrayGPUPiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
MOV R1, c[0x0][0x28] ;
S2R R6, SR_TID.X ;
HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ;
ULDC.64 UR4, c[0x0][0x118] ;
IMAD.WIDE R2, R6, R7, c[0x0][0x160] ;
IMAD.WIDE R4, R6.reuse, R7.reuse, c[0x0][0x168] ;
LDG.E R2, [R2.64] ;
LDG.E R5, [R4.64] ;
IMAD.WIDE R6, R6, R7, c[0x0][0x170] ;
IADD3 R9, R2, R5, RZ ;
STG.E [R6.64], R9 ;
EXIT ;
BRA 0xc0;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
```
|
```amdasm
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z11addArrayGPUPiS_S_ ; -- Begin function _Z11addArrayGPUPiS_S_
.globl _Z11addArrayGPUPiS_S_
.p2align 8
.type _Z11addArrayGPUPiS_S_,@function
_Z11addArrayGPUPiS_S_: ; @_Z11addArrayGPUPiS_S_
; %bb.0:
s_load_b128 s[4:7], s[0:1], 0x0
v_lshlrev_b32_e32 v0, 2, v0
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_clause 0x1
global_load_b32 v1, v0, s[4:5]
global_load_b32 v2, v0, s[6:7]
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v1, v2, v1
global_store_b32 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11addArrayGPUPiS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 8
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z11addArrayGPUPiS_S_, .Lfunc_end0-_Z11addArrayGPUPiS_S_
; -- End function
.section .AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 72
; NumSgprs: 8
; NumVgprs: 3
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 0
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 8
; NumVGPRsForWavesPerEU: 3
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object ; @__hip_cuid_
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0 ; 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11addArrayGPUPiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 8
.sgpr_spill_count: 0
.symbol: _Z11addArrayGPUPiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
```
| 330 | 1,807 |
417 |
Convert the following CUDA host assembly code to AMD host assembly:
```cudaasm
.file "tmpxft_00063aff_00000000-6_main.cudafe1.cpp"
.text
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z5check9cudaError
.type _Z5check9cudaError, @function
_Z5check9cudaError:
.LFB2057:
.cfi_startproc
endbr64
testl %edi, %edi
jne .L9
ret
.L9:
subq $8, %rsp
.cfi_def_cfa_offset 16
call cudaGetErrorString@PLT
movq %rax, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size _Z5check9cudaError, .-_Z5check9cudaError
.globl _Z35__device_stub__Z11addArrayGPUPiS_S_PiS_S_
.type _Z35__device_stub__Z11addArrayGPUPiS_S_PiS_S_, @function
_Z35__device_stub__Z11addArrayGPUPiS_S_PiS_S_:
.LFB2083:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L14
.L10:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L15
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z11addArrayGPUPiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L10
.L15:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z35__device_stub__Z11addArrayGPUPiS_S_PiS_S_, .-_Z35__device_stub__Z11addArrayGPUPiS_S_PiS_S_
.globl _Z11addArrayGPUPiS_S_
.type _Z11addArrayGPUPiS_S_, @function
_Z11addArrayGPUPiS_S_:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z11addArrayGPUPiS_S_PiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z11addArrayGPUPiS_S_, .-_Z11addArrayGPUPiS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%d %d %d %d %d"
.text
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
movl $1, 48(%rsp)
movl $2, 52(%rsp)
movl $3, 56(%rsp)
movl $4, 60(%rsp)
movl $5, 64(%rsp)
movl $10, 80(%rsp)
movl $20, 84(%rsp)
movl $30, 88(%rsp)
movl $40, 92(%rsp)
movl $50, 96(%rsp)
movq %rsp, %rdi
movl $20, %esi
call cudaMalloc@PLT
leaq 8(%rsp), %rdi
movl $20, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $20, %esi
call cudaMalloc@PLT
leaq 48(%rsp), %rsi
movl $1, %ecx
movl $20, %edx
movq (%rsp), %rdi
call cudaMemcpy@PLT
leaq 80(%rsp), %rsi
movl $1, %ecx
movl $20, %edx
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $5, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 36(%rsp), %rdx
movl $1, %ecx
movq 24(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L22
.L19:
leaq 112(%rsp), %rdi
movl $2, %ecx
movl $20, %edx
movq 16(%rsp), %rsi
call cudaMemcpy@PLT
subq $8, %rsp
.cfi_def_cfa_offset 168
movl 136(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 176
movl 140(%rsp), %r9d
movl 136(%rsp), %r8d
movl 132(%rsp), %ecx
movl 128(%rsp), %edx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
movq (%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L23
movl $0, %eax
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L22:
.cfi_restore_state
movq 16(%rsp), %rdx
movq 8(%rsp), %rsi
movq (%rsp), %rdi
call _Z35__device_stub__Z11addArrayGPUPiS_S_PiS_S_
jmp .L19
.L23:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.1
.LC1:
.string "_Z11addArrayGPUPiS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z11addArrayGPUPiS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
```
|
```amdasm
.text
.file "main.hip"
.globl _Z5check10hipError_t # -- Begin function _Z5check10hipError_t
.type _Z5check10hipError_t,@function
_Z5check10hipError_t: # @_Z5check10hipError_t
.cfi_startproc
# %bb.0:
testl %edi, %edi
je .LBB0_1
# %bb.2:
pushq %rax
.cfi_def_cfa_offset 16
callq hipGetErrorString
movq %rax, %rdi
xorl %eax, %eax
popq %rcx
.cfi_def_cfa_offset 8
jmp printf # TAILCALL
.LBB0_1:
retq
.Lfunc_end0:
.size _Z5check10hipError_t, .Lfunc_end0-_Z5check10hipError_t
.cfi_endproc
# -- End function
.globl _Z26__device_stub__addArrayGPUPiS_S_ # -- Begin function _Z26__device_stub__addArrayGPUPiS_S_
.type _Z26__device_stub__addArrayGPUPiS_S_,@function
_Z26__device_stub__addArrayGPUPiS_S_: # @_Z26__device_stub__addArrayGPUPiS_S_
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $112, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 40(%rsp), %rax
movq %rdi, (%rax)
leaq 32(%rsp), %rcx
movq %rsi, (%rcx)
leaq 24(%rsp), %rsi
movq %rdx, (%rsi)
leaq 80(%rsp), %rbx
movq %rax, (%rbx)
movq %rcx, 8(%rbx)
movq %rsi, 16(%rbx)
leaq 64(%rsp), %r14
leaq 48(%rsp), %r15
leaq 16(%rsp), %r12
leaq 8(%rsp), %r13
movq %r14, %rdi
movq %r15, %rsi
movq %r12, %rdx
movq %r13, %rcx
callq __hipPopCallConfiguration
movq (%r14), %rsi
movl 8(%r14), %edx
movq (%r15), %rcx
movl 8(%r15), %r8d
movl $_Z11addArrayGPUPiS_S_, %edi
movq %rbx, %r9
pushq (%r13)
.cfi_adjust_cfa_offset 8
pushq (%r12)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $128, %rsp
.cfi_adjust_cfa_offset -128
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z26__device_stub__addArrayGPUPiS_S_, .Lfunc_end1-_Z26__device_stub__addArrayGPUPiS_S_
.cfi_endproc
# -- End function
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0 # -- Begin function main
.LCPI2_0:
.long 1 # 0x1
.long 2 # 0x2
.long 3 # 0x3
.long 4 # 0x4
.LCPI2_1:
.long 10 # 0xa
.long 20 # 0x14
.long 30 # 0x1e
.long 40 # 0x28
.text
.globl main
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $120, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movaps .LCPI2_0(%rip), %xmm0 # xmm0 = [1,2,3,4]
leaq 96(%rsp), %r14
movaps %xmm0, (%r14)
movl $5, 16(%r14)
movaps .LCPI2_1(%rip), %xmm0 # xmm0 = [10,20,30,40]
leaq 64(%rsp), %rbx
movaps %xmm0, (%rbx)
movl $50, 16(%rbx)
leaq 24(%rsp), %r15
movl $20, %esi
movq %r15, %rdi
callq hipMalloc
leaq 16(%rsp), %r12
movl $20, %esi
movq %r12, %rdi
callq hipMalloc
leaq 8(%rsp), %rdi
movl $20, %esi
callq hipMalloc
movq (%r15), %rdi
movl $20, %edx
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movq (%r12), %rdi
movl $20, %edx
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 4(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_2
# %bb.1:
movq 24(%rsp), %rdi
movq 16(%rsp), %rsi
movq 8(%rsp), %rdx
callq _Z26__device_stub__addArrayGPUPiS_S_
.LBB2_2:
movq 8(%rsp), %rsi
leaq 32(%rsp), %rbx
movl $20, %edx
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
movl (%rbx), %esi
movl 4(%rbx), %edx
movl 8(%rbx), %ecx
movl 12(%rbx), %r8d
movl 16(%rbx), %r9d
movl $.L.str, %edi
xorl %eax, %eax
callq printf
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $120, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, %rdi
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11addArrayGPUPiS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z11addArrayGPUPiS_S_,@object # @_Z11addArrayGPUPiS_S_
.section .rodata,"a",@progbits
.globl _Z11addArrayGPUPiS_S_
.p2align 3, 0x0
_Z11addArrayGPUPiS_S_:
.quad _Z26__device_stub__addArrayGPUPiS_S_
.size _Z11addArrayGPUPiS_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%d %d %d %d %d"
.size .L.str, 15
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z11addArrayGPUPiS_S_"
.size .L__unnamed_1, 22
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z26__device_stub__addArrayGPUPiS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z11addArrayGPUPiS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
```
| 3,084 | 3,513 |
418 |
Convert the following CUDA device assembly code to AMD device assembly:
```cudaasm
code for sm_80
Function : _Z3addPiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
MOV R1, c[0x0][0x28] ;
S2R R6, SR_CTAID.X ;
S2R R3, SR_TID.X ;
IMAD R6, R6, c[0x0][0x0], R3 ;
ISETP.GT.AND P0, PT, R6, 0x9, PT ;
@P0 EXIT ;
HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ;
ULDC.64 UR4, c[0x0][0x118] ;
IMAD.WIDE R4, R6, R7, c[0x0][0x168] ;
IMAD.WIDE R2, R6.reuse, R7.reuse, c[0x0][0x160] ;
LDG.E R4, [R4.64] ;
LDG.E R3, [R2.64] ;
IMAD.WIDE R6, R6, R7, c[0x0][0x170] ;
IADD3 R9, R4, R3, RZ ;
STG.E [R6.64], R9 ;
EXIT ;
BRA 0x100;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
```
|
```amdasm
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3addPiS_S_ ; -- Begin function _Z3addPiS_S_
.globl _Z3addPiS_S_
.p2align 8
.type _Z3addPiS_S_,@function
_Z3addPiS_S_: ; @_Z3addPiS_S_
; %bb.0:
s_load_b32 s2, s[0:1], 0x24
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e32 10, v1
s_cbranch_execz .LBB0_2
; %bb.1:
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v2, v3, v2
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3addPiS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3addPiS_S_, .Lfunc_end0-_Z3addPiS_S_
; -- End function
.section .AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 164
; NumSgprs: 18
; NumVgprs: 6
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 6
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object ; @__hip_cuid_
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0 ; 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3addPiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z3addPiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
```
| 395 | 2,497 |
419 |
Convert the following CUDA host assembly code to AMD host assembly:
```cudaasm
.file "tmpxft_001a9806_00000000-6_add.cudafe1.cpp"
.text
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z26__device_stub__Z3addPiS_S_PiS_S_
.type _Z26__device_stub__Z3addPiS_S_PiS_S_, @function
_Z26__device_stub__Z3addPiS_S_PiS_S_:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z3addPiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z26__device_stub__Z3addPiS_S_PiS_S_, .-_Z26__device_stub__Z3addPiS_S_PiS_S_
.globl _Z3addPiS_S_
.type _Z3addPiS_S_, @function
_Z3addPiS_S_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z3addPiS_S_PiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z3addPiS_S_, .-_Z3addPiS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z3addPiS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z3addPiS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
```
|
```amdasm
.text
.file "add.hip"
.globl _Z18__device_stub__addPiS_S_ # -- Begin function _Z18__device_stub__addPiS_S_
.type _Z18__device_stub__addPiS_S_,@function
_Z18__device_stub__addPiS_S_: # @_Z18__device_stub__addPiS_S_
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $112, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 40(%rsp), %rax
movq %rdi, (%rax)
leaq 32(%rsp), %rcx
movq %rsi, (%rcx)
leaq 24(%rsp), %rsi
movq %rdx, (%rsi)
leaq 80(%rsp), %rbx
movq %rax, (%rbx)
movq %rcx, 8(%rbx)
movq %rsi, 16(%rbx)
leaq 64(%rsp), %r14
leaq 48(%rsp), %r15
leaq 16(%rsp), %r12
leaq 8(%rsp), %r13
movq %r14, %rdi
movq %r15, %rsi
movq %r12, %rdx
movq %r13, %rcx
callq __hipPopCallConfiguration
movq (%r14), %rsi
movl 8(%r14), %edx
movq (%r15), %rcx
movl 8(%r15), %r8d
movl $_Z3addPiS_S_, %edi
movq %rbx, %r9
pushq (%r13)
.cfi_adjust_cfa_offset 8
pushq (%r12)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $128, %rsp
.cfi_adjust_cfa_offset -128
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z18__device_stub__addPiS_S_, .Lfunc_end0-_Z18__device_stub__addPiS_S_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, %rdi
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3addPiS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3addPiS_S_,@object # @_Z3addPiS_S_
.section .rodata,"a",@progbits
.globl _Z3addPiS_S_
.p2align 3, 0x0
_Z3addPiS_S_:
.quad _Z18__device_stub__addPiS_S_
.size _Z3addPiS_S_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z3addPiS_S_"
.size .L__unnamed_1, 13
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__addPiS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3addPiS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
```
| 1,811 | 1,989 |
422 |
Convert the following CUDA device assembly code to AMD device assembly:
```cudaasm
code for sm_80
Function : _Z22countNumOfPrimerKernelPiPb
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ;
S2UR UR4, SR_CTAID.X ;
S2R R0, SR_TID.Y ;
BSSY B0, 0x2b0 ;
S2R R3, SR_CTAID.Y ;
S2R R5, SR_TID.X ;
IADD3 R0, R0, UR4, RZ ;
ULDC.64 UR4, c[0x0][0x118] ;
IMAD R0, R3, c[0x0][0x4], R0 ;
IMAD R0, R0, c[0x0][0x0], R5 ;
IADD3 R0, R0, 0x2, RZ ;
ISETP.GE.AND P0, PT, R0, 0x3, PT ;
@!P0 BRA 0x2a0 ;
ISETP.GE.AND P0, PT, R0, RZ, PT ;
IMAD.MOV.U32 R5, RZ, RZ, 0x2 ;
IABS R6, R0.reuse ;
IABS R9, R0 ;
IABS R8, R5.reuse ;
IABS R10, R5 ;
I2F.RP R4, R8 ;
IMAD.MOV R10, RZ, RZ, -R10 ;
MUFU.RCP R4, R4 ;
IADD3 R2, R4, 0xffffffe, RZ ;
F2I.FTZ.U32.TRUNC.NTZ R3, R2 ;
IMAD.MOV.U32 R2, RZ, RZ, RZ ;
IMAD.MOV R7, RZ, RZ, -R3 ;
IMAD R7, R7, R8, RZ ;
IMAD.HI.U32 R3, R3, R7, R2 ;
IMAD.HI.U32 R3, R3, R6, RZ ;
IMAD R3, R3, R10, R9 ;
ISETP.GT.U32.AND P1, PT, R8, R3, PT ;
@!P1 IMAD.IADD R3, R3, 0x1, -R8 ;
ISETP.NE.AND P1, PT, R5, RZ, PT ;
ISETP.GT.U32.AND P2, PT, R8, R3, PT ;
@!P2 IMAD.IADD R3, R3, 0x1, -R8 ;
@!P0 IMAD.MOV R3, RZ, RZ, -R3 ;
@!P1 LOP3.LUT R3, RZ, R5, RZ, 0x33, !PT ;
ISETP.NE.AND P1, PT, R3, RZ, PT ;
@!P1 EXIT ;
IADD3 R5, R5, 0x1, RZ ;
ISETP.GE.AND P1, PT, R5, R0, PT ;
@!P1 BRA 0x110 ;
BSYNC B0 ;
IADD3 R2, P0, R0, c[0x0][0x168], RZ ;
IMAD.MOV.U32 R4, RZ, RZ, 0x1 ;
LEA.HI.X.SX32 R3, R0, c[0x0][0x16c], 0x1, P0 ;
PRMT R0, R4, 0x7610, R0 ;
STG.E.U8 [R2.64], R0 ;
EXIT ;
BRA 0x310;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
```
|
```amdasm
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z22countNumOfPrimerKernelPiPb ; -- Begin function _Z22countNumOfPrimerKernelPiPb
.globl _Z22countNumOfPrimerKernelPiPb
.p2align 8
.type _Z22countNumOfPrimerKernelPiPb,@function
_Z22countNumOfPrimerKernelPiPb: ; @_Z22countNumOfPrimerKernelPiPb
; %bb.0:
s_load_b32 s2, s[0:1], 0x1c
v_bfe_u32 v1, v0, 10, 10
v_and_b32_e32 v0, 0x3ff, v0
s_mov_b32 s4, -1
s_waitcnt lgkmcnt(0)
s_lshr_b32 s3, s2, 16
s_and_b32 s2, s2, 0xffff
s_mul_i32 s15, s15, s3
s_mov_b32 s3, 2
v_add3_u32 v1, s15, s14, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mul_lo_u32 v1, v1, s2
s_mov_b32 s2, exec_lo
v_add3_u32 v0, v0, v1, 2
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_lt_i32_e32 2, v0
s_cbranch_execz .LBB0_6
; %bb.1: ; %.lr.ph.preheader
s_mov_b32 s4, 0
; implicit-def: $sgpr5
; implicit-def: $sgpr7
; implicit-def: $sgpr6
.LBB0_2: ; %.lr.ph
; =>This Inner Loop Header: Depth=1
v_cvt_f32_u32_e32 v1, s3
s_sub_i32 s8, 0, s3
s_or_b32 s6, s6, exec_lo
s_or_b32 s7, s7, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v1, v1
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v1, 0x4f7ffffe, v1
v_cvt_u32_f32_e32 v1, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mul_lo_u32 v2, s8, v1
s_mov_b32 s8, exec_lo
v_mul_hi_u32 v2, v1, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v1, v1, v2
v_mul_hi_u32 v1, v0, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v1, v1, s3
v_sub_nc_u32_e32 v1, v0, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v2, s3, v1
v_cmp_le_u32_e32 vcc_lo, s3, v1
v_cndmask_b32_e32 v1, v1, v2, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v2, s3, v1
v_cmp_le_u32_e32 vcc_lo, s3, v1
v_cndmask_b32_e32 v1, v1, v2, vcc_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_ne_u32_e32 0, v1
; %bb.3: ; in Loop: Header=BB0_2 Depth=1
s_add_i32 s3, s3, 1
s_and_not1_b32 s7, s7, exec_lo
v_cmp_eq_u32_e32 vcc_lo, s3, v0
s_and_not1_b32 s6, s6, exec_lo
s_and_b32 s9, vcc_lo, exec_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 s7, s7, s9
; %bb.4: ; %Flow
; in Loop: Header=BB0_2 Depth=1
s_or_b32 exec_lo, exec_lo, s8
s_xor_b32 s8, s6, -1
s_and_b32 s9, exec_lo, s7
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
s_or_b32 s4, s9, s4
s_and_not1_b32 s5, s5, exec_lo
s_and_b32 s8, s8, exec_lo
s_or_b32 s5, s5, s8
s_and_not1_b32 exec_lo, exec_lo, s4
s_cbranch_execnz .LBB0_2
; %bb.5: ; %loop.exit.guard
s_or_b32 exec_lo, exec_lo, s4
s_delay_alu instid0(SALU_CYCLE_1)
s_or_not1_b32 s4, s5, exec_lo
.LBB0_6: ; %Flow18
s_or_b32 exec_lo, exec_lo, s2
s_and_saveexec_b32 s2, s4
s_cbranch_execz .LBB0_8
; %bb.7: ; %.critedge
s_load_b64 s[0:1], s[0:1], 0x8
v_ashrrev_i32_e32 v1, 31, v0
v_mov_b32_e32 v2, 1
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b8 v[0:1], v2, off
.LBB0_8: ; %.loopexit
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z22countNumOfPrimerKernelPiPb
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z22countNumOfPrimerKernelPiPb, .Lfunc_end0-_Z22countNumOfPrimerKernelPiPb
; -- End function
.section .AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 384
; NumSgprs: 18
; NumVgprs: 3
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 3
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object ; @__hip_cuid_
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0 ; 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z22countNumOfPrimerKernelPiPb
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z22countNumOfPrimerKernelPiPb.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
```
| 939 | 3,549 |
423 |
Convert the following CUDA host assembly code to AMD host assembly:
```cudaasm
.file "tmpxft_000399e4_00000000-6_num_prime.cudafe1.cpp"
.text
.globl _ZSt21ios_base_library_initv
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z44__device_stub__Z22countNumOfPrimerKernelPiPbPiPb
.type _Z44__device_stub__Z22countNumOfPrimerKernelPiPbPiPb, @function
_Z44__device_stub__Z22countNumOfPrimerKernelPiPbPiPb:
.LFB3694:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z22countNumOfPrimerKernelPiPb(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3694:
.size _Z44__device_stub__Z22countNumOfPrimerKernelPiPbPiPb, .-_Z44__device_stub__Z22countNumOfPrimerKernelPiPbPiPb
.globl _Z22countNumOfPrimerKernelPiPb
.type _Z22countNumOfPrimerKernelPiPb, @function
_Z22countNumOfPrimerKernelPiPb:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z44__device_stub__Z22countNumOfPrimerKernelPiPbPiPb
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _Z22countNumOfPrimerKernelPiPb, .-_Z22countNumOfPrimerKernelPiPb
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "USAGE: num_prime <number of blocks> <integer>"
.align 8
.LC1:
.string "num_blocks: %d, num_thread: %d\n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "prime: "
.section .rodata.str1.8
.align 8
.LC3:
.string "Number of primes between 0 and "
.section .rodata.str1.1
.LC4:
.string " is: "
.LC6:
.string "Time cost: %.2lf s.\n"
.text
.globl main
.type main, @function
main:
.LFB3669:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $104, %rsp
.cfi_def_cfa_offset 160
movl %edi, %ebp
movq %rsi, %rbx
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 48(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
cmpl $3, %ebp
jne .L32
movq 8(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq 16(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %rbx
movl %eax, 12(%rsp)
movl $0, %edi
call cudaSetDevice@PLT
movslq %ebx, %r12
movabsq $2305843009213693950, %rax
cmpq %r12, %rax
jb .L14
leaq 0(,%r12,4), %r13
movq %r13, %rdi
call _Znam@PLT
movq %rax, %r14
movq %r13, %rdi
call _Znam@PLT
movq %rax, 16(%rsp)
movq %r12, %rdi
call _Znam@PLT
movq %rax, %rbp
movq %r12, %rdi
call _Znam@PLT
movq %rax, 24(%rsp)
testl %ebx, %ebx
jle .L16
leal -1(%rbx), %edx
addq $2, %rdx
movl $1, %eax
.L18:
movl %eax, -4(%r14,%rax,4)
movb $0, -1(%rbp,%rax)
addq $1, %rax
cmpq %rdx, %rax
jne .L18
.L16:
leaq 16(%rsp), %rdi
movq %r13, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %r13, %rdx
movq %r14, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
leaq 24(%rsp), %rdi
movq %r12, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %r12, %rdx
movq %rbp, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movslq %ebx, %r13
imulq $274877907, %r13, %r13
sarq $38, %r13
movl %ebx, %eax
sarl $31, %eax
subl %eax, %r13d
movl %r13d, %ecx
movl $1000, %edx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %r13d, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1000, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 64(%rsp), %rdx
movl $1, %ecx
movq 36(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L33
.L19:
call cudaThreadSynchronize@PLT
movl $2, %ecx
movq %r12, %rdx
movq 24(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
testl %ebx, %ebx
jle .L28
leal -1(%rbx), %r15d
movl $0, %ebx
movl $0, 8(%rsp)
jmp .L26
.L32:
leaq .LC0(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $-1, %eax
jmp .L11
.L14:
movq 88(%rsp), %rax
subq %fs:40, %rax
je .L17
call __stack_chk_fail@PLT
.L17:
call __cxa_throw_bad_array_new_length@PLT
.L33:
movq 24(%rsp), %rsi
movq 16(%rsp), %rdi
call _Z44__device_stub__Z22countNumOfPrimerKernelPiPbPiPb
jmp .L19
.L35:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L34
call _ZSt16__throw_bad_castv@PLT
.L34:
call __stack_chk_fail@PLT
.L24:
movq %r13, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq 0(%r13), %rax
movl $10, %esi
movq %r13, %rdi
call *48(%rax)
movl %eax, %esi
.L25:
movsbl %sil, %esi
movq %r12, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
.L21:
leaq 1(%rbx), %rax
cmpq %r15, %rbx
je .L20
movq %rax, %rbx
.L26:
cmpb $0, 0(%rbp,%rbx)
je .L21
addl $1, 8(%rsp)
movl $7, %edx
leaq .LC2(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl %ebx, %esi
leaq _ZSt4cout(%rip), %rdi
call _ZNSolsEi@PLT
movq %rax, %r12
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%r12,%rax), %r13
testq %r13, %r13
je .L35
cmpb $0, 56(%r13)
je .L24
movzbl 67(%r13), %esi
jmp .L25
.L28:
movl $0, 8(%rsp)
.L20:
leaq .LC3(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl 12(%rsp), %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
leaq .LC4(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl 8(%rsp), %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq %r14, %rdi
call _ZdaPv@PLT
movq %rbp, %rdi
call _ZdaPv@PLT
leaq 64(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
movq 64(%rsp), %rax
subq 48(%rsp), %rax
imulq $1000000, %rax, %rax
addq 72(%rsp), %rax
subq 56(%rsp), %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
divsd .LC5(%rip), %xmm0
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl $0, %eax
.L11:
movq 88(%rsp), %rdx
subq %fs:40, %rdx
jne .L36
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L36:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size main, .-main
.section .rodata.str1.8
.align 8
.LC7:
.string "_Z22countNumOfPrimerKernelPiPb"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3697:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _Z22countNumOfPrimerKernelPiPb(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC5:
.long 0
.long 1090021888
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
```
|
```amdasm
.text
.file "num_prime.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z37__device_stub__countNumOfPrimerKernelPiPb # -- Begin function _Z37__device_stub__countNumOfPrimerKernelPiPb
.type _Z37__device_stub__countNumOfPrimerKernelPiPb,@function
_Z37__device_stub__countNumOfPrimerKernelPiPb: # @_Z37__device_stub__countNumOfPrimerKernelPiPb
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $80, %rsp
.cfi_def_cfa_offset 128
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 24(%rsp), %rax
movq %rdi, (%rax)
leaq 16(%rsp), %rcx
movq %rsi, (%rcx)
leaq 64(%rsp), %rbx
movq %rax, (%rbx)
movq %rcx, 8(%rbx)
leaq 48(%rsp), %r14
leaq 32(%rsp), %r15
leaq 8(%rsp), %r12
movq %rsp, %r13
movq %r14, %rdi
movq %r15, %rsi
movq %r12, %rdx
movq %r13, %rcx
callq __hipPopCallConfiguration
movq (%r14), %rsi
movl 8(%r14), %edx
movq (%r15), %rcx
movl 8(%r15), %r8d
movl $_Z22countNumOfPrimerKernelPiPb, %edi
movq %rbx, %r9
pushq (%r13)
.cfi_adjust_cfa_offset 8
pushq (%r12)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $96, %rsp
.cfi_adjust_cfa_offset -96
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z37__device_stub__countNumOfPrimerKernelPiPb, .Lfunc_end0-_Z37__device_stub__countNumOfPrimerKernelPiPb
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI1_0:
.quad 0x40f86a0000000000 # double 1.0E+5
.text
.globl main
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $56, %rsp
.cfi_def_cfa_offset 112
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsi, %rbx
movl %edi, %ebp
leaq 24(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
cmpl $3, %ebp
jne .LBB1_1
# %bb.2:
movq 16(%rbx), %rdi
callq atoi
movl %eax, %ebx
xorl %edi, %edi
callq hipSetDevice
movl %ebx, 4(%rsp) # 4-byte Spill
movslq %ebx, %r15
leaq (,%r15,4), %r12
testl %r15d, %r15d
movq $-1, %r14
cmovnsq %r12, %r14
movq %r14, %rdi
callq _Znam
movq %rax, %rbx
movq %r14, %rdi
callq _Znam
movq %rax, 16(%rsp)
movq %r15, %rdi
callq _Znam
movq %rax, %r14
movq %r15, %rdi
callq _Znam
movq %rax, 8(%rsp)
testl %r15d, %r15d
jle .LBB1_5
# %bb.3: # %.lr.ph.preheader
movl 4(%rsp), %r13d # 4-byte Reload
xorl %ebp, %ebp
movq %r14, %rdi
xorl %esi, %esi
movq %r13, %rdx
callq memset@PLT
.LBB1_4: # %.lr.ph
# =>This Inner Loop Header: Depth=1
leaq 1(%rbp), %rax
movl %eax, (%rbx,%rbp,4)
movq %rax, %rbp
cmpq %rax, %r13
jne .LBB1_4
.LBB1_5: # %._crit_edge
leaq 16(%rsp), %r13
movq %r13, %rdi
movq %r12, %rsi
callq hipMalloc
movq (%r13), %rdi
movq %rbx, %rsi
movq %r12, %rdx
movl $1, %ecx
callq hipMemcpy
leaq 8(%rsp), %r12
movq %r12, %rdi
movq %r15, %rsi
callq hipMalloc
movq (%r12), %rdi
movq %r14, %rsi
movq %r15, %rdx
movl $1, %ecx
callq hipMemcpy
imulq $274877907, %r15, %r13 # imm = 0x10624DD3
movq %r13, %rax
shrq $63, %rax
sarq $38, %r13
addl %eax, %r13d
xorl %r12d, %r12d
movl $.L.str.1, %edi
movl $1000, %esi # imm = 0x3E8
movl %r13d, %edx
xorl %eax, %eax
callq printf
btsq $32, %r13
movabsq $4294967296, %rdi # imm = 0x100000000
orq $1000, %rdi # imm = 0x3E8
movl $1, %esi
movq %r13, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_7
# %bb.6:
movq 16(%rsp), %rdi
movq 8(%rsp), %rsi
callq _Z37__device_stub__countNumOfPrimerKernelPiPb
.LBB1_7:
callq hipDeviceSynchronize
movq 8(%rsp), %rsi
movq %r14, %rdi
movq %r15, %rdx
movl $2, %ecx
callq hipMemcpy
cmpl $0, 4(%rsp) # 4-byte Folded Reload
jle .LBB1_12
# %bb.8: # %.lr.ph64.preheader
movl 4(%rsp), %ebp # 4-byte Reload
xorl %r15d, %r15d
xorl %r12d, %r12d
.LBB1_9: # %.lr.ph64
# =>This Inner Loop Header: Depth=1
cmpb $0, (%r14,%r15)
je .LBB1_11
# %bb.10: # in Loop: Header=BB1_9 Depth=1
incl %r12d
movl $_ZSt4cout, %edi
movl $.L.str.2, %esi
movl $7, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl %r15d, %esi
callq _ZNSolsEi
movq %rax, %r13
movq (%rax), %rax
movq -24(%rax), %rdi
addq %r13, %rdi
movl $10, %esi
callq _ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
movsbl %al, %esi
movq %r13, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
.LBB1_11: # in Loop: Header=BB1_9 Depth=1
incq %r15
cmpq %r15, %rbp
jne .LBB1_9
.LBB1_12: # %._crit_edge65
movl $_ZSt4cout, %edi
movl $.L.str.3, %esi
movl $31, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl 4(%rsp), %esi # 4-byte Reload
callq _ZNSolsEi
movq %rax, %r15
movl $.L.str.4, %esi
movl $5, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq %r15, %rdi
movl %r12d, %esi
callq _ZNSolsEi
movq %rax, %r15
movq (%rax), %rax
movq -24(%rax), %rdi
addq %r15, %rdi
movl $10, %esi
callq _ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
movsbl %al, %esi
movq %r15, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq %rbx, %rdi
callq _ZdaPv
movq %r14, %rdi
callq _ZdaPv
xorl %ebx, %ebx
leaq 40(%rsp), %r14
movq %r14, %rdi
xorl %esi, %esi
callq gettimeofday
movq (%r14), %rax
subq 24(%rsp), %rax
imulq $1000000, %rax, %rax # imm = 0xF4240
addq 8(%r14), %rax
subq 32(%rsp), %rax
cvtsi2sd %rax, %xmm0
divsd .LCPI1_0(%rip), %xmm0
movl $.L.str.5, %edi
movb $1, %al
callq printf
jmp .LBB1_13
.LBB1_1:
movl $_ZSt4cout, %ebx
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $45, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rdi
addq %rbx, %rdi
movl $10, %esi
callq _ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $-1, %ebx
.LBB1_13:
movl %ebx, %eax
addq $56, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, %rdi
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z22countNumOfPrimerKernelPiPb, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z22countNumOfPrimerKernelPiPb,@object # @_Z22countNumOfPrimerKernelPiPb
.section .rodata,"a",@progbits
.globl _Z22countNumOfPrimerKernelPiPb
.p2align 3, 0x0
_Z22countNumOfPrimerKernelPiPb:
.quad _Z37__device_stub__countNumOfPrimerKernelPiPb
.size _Z22countNumOfPrimerKernelPiPb, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "USAGE: num_prime <number of blocks> <integer>"
.size .L.str, 46
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "num_blocks: %d, num_thread: %d\n"
.size .L.str.1, 32
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "prime: "
.size .L.str.2, 8
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Number of primes between 0 and "
.size .L.str.3, 32
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz " is: "
.size .L.str.4, 6
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "Time cost: %.2lf s.\n"
.size .L.str.5, 21
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z22countNumOfPrimerKernelPiPb"
.size .L__unnamed_1, 31
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z37__device_stub__countNumOfPrimerKernelPiPb
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z22countNumOfPrimerKernelPiPb
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
```
| 4,945 | 5,313 |
428 |
Convert the following CUDA device assembly code to AMD device assembly:
```cudaasm
code for sm_80
Function : _Z9histogramPiPhiii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ;
S2R R0, SR_CTAID.X ;
ULDC UR4, c[0x0][0xc] ;
ULDC UR5, c[0x0][0x0] ;
S2R R3, SR_TID.X ;
UIMAD UR4, UR4, UR5, URZ ;
S2R R2, SR_CTAID.Y ;
S2R R5, SR_TID.Y ;
IMAD R0, R0, c[0x0][0x0], R3 ;
ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x174], PT ;
IMAD R3, R2, c[0x0][0x4], R5 ;
IMAD R5, R3.reuse, UR4, R0 ;
ISETP.GE.U32.OR P0, PT, R3, c[0x0][0x170], P0 ;
ULDC.64 UR4, c[0x0][0x118] ;
ISETP.GE.AND P1, PT, R5, c[0x0][0x178], PT ;
@!P1 IMAD.MOV.U32 R2, RZ, RZ, 0x4 ;
@!P1 IMAD.WIDE R2, R5, R2, c[0x0][0x160] ;
@!P1 STG.E [R2.64], RZ ;
BAR.SYNC.DEFER_BLOCKING 0x0 ;
@P0 EXIT ;
IADD3 R4, P0, R5, c[0x0][0x168], RZ ;
LEA.HI.X.SX32 R5, R5, c[0x0][0x16c], 0x1, P0 ;
LDG.E.U8 R2, [R4.64] ;
HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ;
MOV R7, 0x1 ;
IMAD.WIDE.U32 R2, R2, R3, c[0x0][0x160] ;
RED.E.ADD.STRONG.GPU [R2.64], R7 ;
EXIT ;
BRA 0x1c0;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
```
|
```amdasm
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9histogramPiPhiii ; -- Begin function _Z9histogramPiPhiii
.globl _Z9histogramPiPhiii
.p2align 8
.type _Z9histogramPiPhiii,@function
_Z9histogramPiPhiii: ; @_Z9histogramPiPhiii
; %bb.0:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x20
s_load_b256 s[4:11], s[0:1], 0x0
v_and_b32_e32 v1, 0x3ff, v0
v_bfe_u32 v0, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s1, s2, 0xffff
s_lshr_b32 s0, s2, 16
v_mad_u64_u32 v[2:3], null, s14, s1, v[1:2]
v_mad_u64_u32 v[3:4], null, s15, s0, v[0:1]
s_mul_i32 s3, s3, s1
s_mov_b32 s0, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[0:1], null, s3, v3, v[2:3]
v_ashrrev_i32_e32 v1, 31, v0
v_cmpx_gt_i32_e64 s10, v0
s_cbranch_execz .LBB0_2
; %bb.1:
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[4:5], 2, v[0:1]
v_mov_b32_e32 v6, 0
v_add_co_u32 v4, vcc_lo, s4, v4
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v5, vcc_lo
global_store_b32 v[4:5], v6, off
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s0
v_cmp_gt_u32_e32 vcc_lo, s8, v3
v_cmp_gt_u32_e64 s0, s9, v2
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
s_and_b32 s0, s0, vcc_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_4
; %bb.3:
v_add_co_u32 v0, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
global_load_u8 v0, v[0:1], off
s_waitcnt vmcnt(0)
v_dual_mov_b32 v1, 1 :: v_dual_lshlrev_b32 v0, 2, v0
global_atomic_add_u32 v0, v1, s[4:5]
.LBB0_4:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9histogramPiPhiii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9histogramPiPhiii, .Lfunc_end0-_Z9histogramPiPhiii
; -- End function
.section .AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 252
; NumSgprs: 18
; NumVgprs: 7
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 7
; Occupancy: 16
; WaveLimiterHint : 1
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object ; @__hip_cuid_
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0 ; 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9histogramPiPhiii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z9histogramPiPhiii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
```
| 655 | 2,794 |
429 |
Convert the following CUDA host assembly code to AMD host assembly:
```cudaasm
.file "tmpxft_0013c855_00000000-6_histogram.cudafe1.cpp"
.text
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z33__device_stub__Z9histogramPiPhiiiPiPhiii
.type _Z33__device_stub__Z9histogramPiPhiiiPiPhiii, @function
_Z33__device_stub__Z9histogramPiPhiiiPiPhiii:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 4(%rsp), %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9histogramPiPhiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z33__device_stub__Z9histogramPiPhiiiPiPhiii, .-_Z33__device_stub__Z9histogramPiPhiiiPiPhiii
.globl _Z9histogramPiPhiii
.type _Z9histogramPiPhiii, @function
_Z9histogramPiPhiii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z9histogramPiPhiiiPiPhiii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z9histogramPiPhiii, .-_Z9histogramPiPhiii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z9histogramPiPhiii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z9histogramPiPhiii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
```
|
```amdasm
.text
.file "histogram.hip"
.globl _Z24__device_stub__histogramPiPhiii # -- Begin function _Z24__device_stub__histogramPiPhiii
.type _Z24__device_stub__histogramPiPhiii,@function
_Z24__device_stub__histogramPiPhiii: # @_Z24__device_stub__histogramPiPhiii
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $128, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 40(%rsp), %rax
movq %rdi, (%rax)
leaq 32(%rsp), %rdi
movq %rsi, (%rdi)
leaq 12(%rsp), %rsi
movl %edx, (%rsi)
leaq 8(%rsp), %rdx
movl %ecx, (%rdx)
leaq 4(%rsp), %rcx
movl %r8d, (%rcx)
leaq 80(%rsp), %rbx
movq %rax, (%rbx)
movq %rdi, 8(%rbx)
movq %rsi, 16(%rbx)
movq %rdx, 24(%rbx)
movq %rcx, 32(%rbx)
leaq 64(%rsp), %r14
leaq 48(%rsp), %r15
leaq 24(%rsp), %r12
leaq 16(%rsp), %r13
movq %r14, %rdi
movq %r15, %rsi
movq %r12, %rdx
movq %r13, %rcx
callq __hipPopCallConfiguration
movq (%r14), %rsi
movl 8(%r14), %edx
movq (%r15), %rcx
movl 8(%r15), %r8d
movl $_Z9histogramPiPhiii, %edi
movq %rbx, %r9
pushq (%r13)
.cfi_adjust_cfa_offset 8
pushq (%r12)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $144, %rsp
.cfi_adjust_cfa_offset -144
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z24__device_stub__histogramPiPhiii, .Lfunc_end0-_Z24__device_stub__histogramPiPhiii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, %rdi
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9histogramPiPhiii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9histogramPiPhiii,@object # @_Z9histogramPiPhiii
.section .rodata,"a",@progbits
.globl _Z9histogramPiPhiii
.p2align 3, 0x0
_Z9histogramPiPhiii:
.quad _Z24__device_stub__histogramPiPhiii
.size _Z9histogramPiPhiii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z9histogramPiPhiii"
.size .L__unnamed_1, 20
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__histogramPiPhiii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9histogramPiPhiii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
```
| 1,887 | 2,076 |
432 |
Convert the following CUDA device assembly code to AMD device assembly:
```cudaasm
code for sm_80
Function : _Z8multiplyPfS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
MOV R1, c[0x0][0x28] ;
S2R R2, SR_TID.X ;
S2R R3, SR_CTAID.X ;
IMAD R2, R3, c[0x0][0x0], R2 ;
ISETP.GE.AND P0, PT, R2, c[0x0][0x170], PT ;
@P0 EXIT ;
HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ;
ULDC.64 UR4, c[0x0][0x118] ;
IMAD.WIDE R4, R2, R3, c[0x0][0x168] ;
IMAD.WIDE R2, R2, R3, c[0x0][0x160] ;
LDG.E R4, [R4.64] ;
LDG.E R7, [R2.64] ;
FMUL R7, R4, R7 ;
STG.E [R2.64], R7 ;
EXIT ;
BRA 0xf0;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
```
|
```amdasm
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z8multiplyPfS_i ; -- Begin function _Z8multiplyPfS_i
.globl _Z8multiplyPfS_i
.p2align 8
.type _Z8multiplyPfS_i,@function
_Z8multiplyPfS_i: ; @_Z8multiplyPfS_i
; %bb.0:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s3, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
; %bb.1:
s_load_b128 s[0:3], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_load_b32 v4, v[2:3], off
global_load_b32 v0, v[0:1], off
s_waitcnt vmcnt(0)
v_mul_f32_e32 v0, v4, v0
global_store_b32 v[2:3], v0, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z8multiplyPfS_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z8multiplyPfS_i, .Lfunc_end0-_Z8multiplyPfS_i
; -- End function
.section .AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 160
; NumSgprs: 18
; NumVgprs: 5
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 5
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object ; @__hip_cuid_
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0 ; 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z8multiplyPfS_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z8multiplyPfS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
```
| 353 | 2,454 |
433 |
Convert the following CUDA host assembly code to AMD host assembly:
```cudaasm
.file "tmpxft_0012b7c8_00000000-6_assign1.cudafe1.cpp"
.text
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2065:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2065:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z13random_floatsPfi
.type _Z13random_floatsPfi, @function
_Z13random_floatsPfi:
.LFB2058:
.cfi_startproc
endbr64
testl %esi, %esi
jle .L8
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
movq %rdi, %rbx
movslq %esi, %rsi
leaq (%rdi,%rsi,4), %rbp
.L5:
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
mulss .LC0(%rip), %xmm0
movss %xmm0, (%rbx)
addq $4, %rbx
cmpq %rbp, %rbx
jne .L5
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L8:
.cfi_restore 3
.cfi_restore 6
ret
.cfi_endproc
.LFE2058:
.size _Z13random_floatsPfi, .-_Z13random_floatsPfi
.globl _Z11CPU_big_dotPfS_i
.type _Z11CPU_big_dotPfS_i, @function
_Z11CPU_big_dotPfS_i:
.LFB2059:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
movq %rdi, %rbp
movq %rsi, %r12
movl %edx, %ebx
movl $4, %edi
call malloc@PLT
movl $0x00000000, (%rax)
testl %ebx, %ebx
jle .L11
movslq %ebx, %rcx
salq $2, %rcx
movl $0, %edx
pxor %xmm1, %xmm1
.L13:
movss 0(%rbp,%rdx), %xmm0
mulss (%r12,%rdx), %xmm0
addss %xmm0, %xmm1
addq $4, %rdx
cmpq %rcx, %rdx
jne .L13
movss %xmm1, (%rax)
.L11:
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2059:
.size _Z11CPU_big_dotPfS_i, .-_Z11CPU_big_dotPfS_i
.globl _Z11start_timerv
.type _Z11start_timerv, @function
_Z11start_timerv:
.LFB2061:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
movq %fs:40, %rax
movq %rax, 24(%rsp)
xorl %eax, %eax
movq %rsp, %rdi
movl $0, %esi
call gettimeofday@PLT
imulq $1000000, (%rsp), %rax
addq 8(%rsp), %rax
movq 24(%rsp), %rdx
subq %fs:40, %rdx
jne .L19
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2061:
.size _Z11start_timerv, .-_Z11start_timerv
.section .rodata.str1.1,"aMS",@progbits,1
.LC3:
.string "%s: %.5f sec\n"
.text
.globl _Z10stop_timerxPc
.type _Z10stop_timerxPc, @function
_Z10stop_timerxPc:
.LFB2062:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $32, %rsp
.cfi_def_cfa_offset 64
movq %rdi, %r12
movq %rsi, %rbp
movq %fs:40, %rax
movq %rax, 24(%rsp)
xorl %eax, %eax
movq %rsp, %rdi
movl $0, %esi
call gettimeofday@PLT
imulq $1000000, (%rsp), %rbx
addq 8(%rsp), %rbx
subq %r12, %rbx
pxor %xmm0, %xmm0
cvtsi2ssq %rbx, %xmm0
divss .LC2(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movq %rbp, %rdx
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 24(%rsp), %rax
subq %fs:40, %rax
jne .L23
movq %rbx, %rax
addq $32, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2062:
.size _Z10stop_timerxPc, .-_Z10stop_timerxPc
.globl _Z30__device_stub__Z8multiplyPfS_iPfS_i
.type _Z30__device_stub__Z8multiplyPfS_iPfS_i, @function
_Z30__device_stub__Z8multiplyPfS_iPfS_i:
.LFB2087:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L28
.L24:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L29
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L28:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z8multiplyPfS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L24
.L29:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2087:
.size _Z30__device_stub__Z8multiplyPfS_iPfS_i, .-_Z30__device_stub__Z8multiplyPfS_iPfS_i
.globl _Z8multiplyPfS_i
.type _Z8multiplyPfS_i, @function
_Z8multiplyPfS_i:
.LFB2088:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z8multiplyPfS_iPfS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2088:
.size _Z8multiplyPfS_i, .-_Z8multiplyPfS_i
.globl _Z11GPU_big_dotPfS_i
.type _Z11GPU_big_dotPfS_i, @function
_Z11GPU_big_dotPfS_i:
.LFB2060:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $56, %rsp
.cfi_def_cfa_offset 112
movq %rdi, %r12
movq %rsi, %r15
movl %edx, %ebx
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movl $4, %edi
call malloc@PLT
movq %rax, %rbp
movl $0x00000000, (%rax)
movslq %ebx, %r13
leal 0(,%rbx,4), %r14d
movslq %r14d, %r14
movq %rsp, %rdi
movq %r14, %rsi
call cudaMalloc@PLT
leaq 8(%rsp), %rdi
movq %r14, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %r14, %rdx
movq %r12, %rsi
movq (%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %r14, %rdx
movq %r15, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $512, 28(%rsp)
movl $1, 32(%rsp)
leal 1022(%rbx), %eax
movl %ebx, %edx
addl $511, %edx
cmovns %edx, %eax
sarl $9, %eax
movl %eax, 16(%rsp)
movl $1, 20(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L39
.L33:
movl $2, %ecx
movq %r14, %rdx
movq (%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
testl %ebx, %ebx
jle .L34
movss 0(%rbp), %xmm0
movq %r12, %rax
leaq (%r12,%r13,4), %rdx
.L35:
addss (%rax), %xmm0
addq $4, %rax
cmpq %rdx, %rax
jne .L35
movss %xmm0, 0(%rbp)
.L34:
movq (%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L40
movq %rbp, %rax
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L39:
.cfi_restore_state
movl %ebx, %edx
movq 8(%rsp), %rsi
movq (%rsp), %rdi
call _Z30__device_stub__Z8multiplyPfS_iPfS_i
jmp .L33
.L40:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2060:
.size _Z11GPU_big_dotPfS_i, .-_Z11GPU_big_dotPfS_i
.section .rodata.str1.1
.LC4:
.string "\ncpu result: %f\n"
.LC5:
.string "gpu result: %f\n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC7:
.string "difference between 2 results is: %f < 1.0e-6 ===> correct.\n"
.section .rodata.str1.1
.LC8:
.string "\nCPU/GPU speedup: %f\n"
.section .rodata.str1.8
.align 8
.LC9:
.string "difference between 2 results is: %f > 1.0e-6 ===> incorrect.\nExit Now!\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $56, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movl $4194304, %edi
call malloc@PLT
movq %rax, %rbp
movl $1048576, %esi
movq %rax, %rdi
call _Z13random_floatsPfi
movl $4194304, %edi
call malloc@PLT
movq %rax, %rbx
movl $1048576, %esi
movq %rax, %rdi
call _Z13random_floatsPfi
movabsq $7308613717771767875, %rax
movq %rax, 10(%rsp)
movabsq $28542640894320741, %rax
movq %rax, 17(%rsp)
movabsq $7308613717771767879, %rcx
movq %rcx, 25(%rsp)
movq %rax, 32(%rsp)
call _Z11start_timerv
movq %rax, %r12
movl $1048576, %edx
movq %rbx, %rsi
movq %rbp, %rdi
call _Z11CPU_big_dotPfS_i
movq %rax, %r13
leaq 10(%rsp), %rsi
movq %r12, %rdi
call _Z10stop_timerxPc
movq %rax, %r15
call _Z11start_timerv
movq %rax, %r14
movl $1048576, %edx
movq %rbx, %rsi
movq %rbp, %rdi
call _Z11GPU_big_dotPfS_i
movq %rax, %r12
leaq 25(%rsp), %rsi
movq %r14, %rdi
call _Z10stop_timerxPc
movq %rax, %r14
pxor %xmm0, %xmm0
cvtss2sd 0(%r13), %xmm0
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
pxor %xmm0, %xmm0
cvtss2sd (%r12), %xmm0
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movss 0(%r13), %xmm0
subss (%r12), %xmm0
cvtss2sd %xmm0, %xmm0
movsd .LC6(%rip), %xmm1
comisd %xmm0, %xmm1
jb .L46
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
pxor %xmm0, %xmm0
cvtsi2sdq %r15, %xmm0
pxor %xmm1, %xmm1
cvtsi2sdq %r14, %xmm1
divsd %xmm1, %xmm0
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq %rbp, %rdi
call free@PLT
movq %rbx, %rdi
call free@PLT
movq %r13, %rdi
call free@PLT
movq %r12, %rdi
call free@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L49
movl $0, %eax
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L46:
.cfi_restore_state
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl $-1, %edi
call exit@PLT
.L49:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC10:
.string "_Z8multiplyPfS_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2090:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC10(%rip), %rdx
movq %rdx, %rcx
leaq _Z8multiplyPfS_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2090:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC0:
.long 805306368
.align 4
.LC2:
.long 1232348160
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC6:
.long -1598689907
.long 1051772663
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
```
|
```amdasm
.text
.file "assign1.hip"
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI0_0:
.long 0x30000000 # float 4.65661287E-10
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0
.LCPI0_1:
.quad 0x3eb0c6f7a0b5ed8d # double 9.9999999999999995E-7
.text
.globl main
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $64, %rsp
.cfi_def_cfa_offset 112
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $4194304, %edi # imm = 0x400000
callq malloc
movq %rax, %rbx
xorl %r14d, %r14d
.LBB0_1: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
callq rand
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
mulss .LCPI0_0(%rip), %xmm0
movss %xmm0, (%rbx,%r14,4)
incq %r14
cmpq $1048576, %r14 # imm = 0x100000
jne .LBB0_1
# %bb.2: # %_Z13random_floatsPfi.exit
movl $4194304, %edi # imm = 0x400000
callq malloc
movq %rax, %r14
xorl %r15d, %r15d
.LBB0_3: # %.lr.ph.i22
# =>This Inner Loop Header: Depth=1
callq rand
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
mulss .LCPI0_0(%rip), %xmm0
movss %xmm0, (%r14,%r15,4)
incq %r15
cmpq $1048576, %r15 # imm = 0x100000
jne .LBB0_3
# %bb.4: # %_Z13random_floatsPfi.exit26
movabsq $7308613717771767875, %rax # imm = 0x656D697420555043
movq %rax, 33(%rsp)
movl $1634956576, %eax # imm = 0x61737520
movl %eax, 41(%rsp)
movw $25959, %cx # imm = 0x6567
movw %cx, 45(%rsp)
xorl %r12d, %r12d
movb %r12b, 47(%rsp)
movabsq $7308613717771767879, %rdx # imm = 0x656D697420555047
movq %rdx, 18(%rsp)
movl %eax, 26(%rsp)
movw %cx, 30(%rsp)
movb %r12b, 32(%rsp)
leaq 48(%rsp), %r15
movq %r15, %rdi
xorl %esi, %esi
callq gettimeofday
movq (%r15), %rcx
movq 8(%r15), %rax
xorps %xmm1, %xmm1
.LBB0_5: # =>This Inner Loop Header: Depth=1
movss (%rbx,%r12,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
mulss (%r14,%r12,4), %xmm0
addss %xmm0, %xmm1
incq %r12
cmpq $1048576, %r12 # imm = 0x100000
jne .LBB0_5
# %bb.6: # %_Z11CPU_big_dotPfS_i.exit
imulq $1000000, %rcx, %rdi # imm = 0xF4240
addq %rax, %rdi
leaq 33(%rsp), %rsi
movss %xmm1, 8(%rsp) # 4-byte Spill
callq _Z10stop_timerxPc
movq %rax, %r12
leaq 48(%rsp), %r15
movq %r15, %rdi
xorl %esi, %esi
callq gettimeofday
imulq $1000000, (%r15), %r13 # imm = 0xF4240
addq 8(%r15), %r13
movq %rbx, %rdi
movq %r14, %rsi
movl $1048576, %edx # imm = 0x100000
callq _Z11GPU_big_dotPfS_i
movq %rax, %r15
leaq 18(%rsp), %rsi
movq %r13, %rdi
callq _Z10stop_timerxPc
movq %rax, %r13
xorps %xmm0, %xmm0
cvtss2sd 8(%rsp), %xmm0 # 4-byte Folded Reload
movl $.L.str, %edi
movb $1, %al
callq printf
movss (%r15), %xmm0 # xmm0 = mem[0],zero,zero,zero
movss %xmm0, 12(%rsp) # 4-byte Spill
cvtss2sd %xmm0, %xmm0
movl $.L.str.1, %edi
movb $1, %al
callq printf
movss 8(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
subss 12(%rsp), %xmm0 # 4-byte Folded Reload
cvtss2sd %xmm0, %xmm0
movsd .LCPI0_1(%rip), %xmm1 # xmm1 = mem[0],zero
ucomisd %xmm0, %xmm1
jb .LBB0_8
# %bb.7:
movl $.L.str.2, %edi
movb $1, %al
callq printf
xorps %xmm0, %xmm0
cvtsi2sd %r12, %xmm0
xorps %xmm1, %xmm1
cvtsi2sd %r13, %xmm1
divsd %xmm1, %xmm0
movl $.L.str.4, %edi
movb $1, %al
callq printf
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
xorl %eax, %eax
addq $64, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB0_8:
.cfi_def_cfa_offset 112
movl $.L.str.3, %edi
movb $1, %al
callq printf
movl $-1, %edi
callq exit
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function _Z13random_floatsPfi
.LCPI1_0:
.long 0x30000000 # float 4.65661287E-10
.text
.globl _Z13random_floatsPfi
.type _Z13random_floatsPfi,@function
_Z13random_floatsPfi: # @_Z13random_floatsPfi
.cfi_startproc
# %bb.0:
testl %esi, %esi
jle .LBB1_4
# %bb.1: # %.lr.ph.preheader
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rdi, %rbx
movl %esi, %r14d
xorl %r15d, %r15d
.LBB1_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
callq rand
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
mulss .LCPI1_0(%rip), %xmm0
movss %xmm0, (%rbx,%r15,4)
incq %r15
cmpq %r15, %r14
jne .LBB1_2
# %bb.3:
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r14
.cfi_restore %r15
.LBB1_4: # %._crit_edge
retq
.Lfunc_end1:
.size _Z13random_floatsPfi, .Lfunc_end1-_Z13random_floatsPfi
.cfi_endproc
# -- End function
.globl _Z11start_timerv # -- Begin function _Z11start_timerv
.type _Z11start_timerv,@function
_Z11start_timerv: # @_Z11start_timerv
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $16, %rsp
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -16
movq %rsp, %rbx
movq %rbx, %rdi
xorl %esi, %esi
callq gettimeofday
imulq $1000000, (%rbx), %rax # imm = 0xF4240
addq 8(%rbx), %rax
addq $16, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size _Z11start_timerv, .Lfunc_end2-_Z11start_timerv
.cfi_endproc
# -- End function
.globl _Z11CPU_big_dotPfS_i # -- Begin function _Z11CPU_big_dotPfS_i
.type _Z11CPU_big_dotPfS_i,@function
_Z11CPU_big_dotPfS_i: # @_Z11CPU_big_dotPfS_i
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %rbp, -16
movl %edx, %ebp
movq %rsi, %rbx
movq %rdi, %r14
movl $4, %edi
callq malloc
movl $0, (%rax)
testl %ebp, %ebp
jle .LBB3_4
# %bb.1: # %.lr.ph
movl %ebp, %ecx
xorps %xmm0, %xmm0
xorl %edx, %edx
.LBB3_2: # =>This Inner Loop Header: Depth=1
movss (%r14,%rdx,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
mulss (%rbx,%rdx,4), %xmm1
addss %xmm1, %xmm0
incq %rdx
cmpq %rdx, %rcx
jne .LBB3_2
# %bb.3: # %._crit_edge
movss %xmm0, (%rax)
.LBB3_4:
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size _Z11CPU_big_dotPfS_i, .Lfunc_end3-_Z11CPU_big_dotPfS_i
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function _Z10stop_timerxPc
.LCPI4_0:
.long 0x49742400 # float 1.0E+6
.text
.globl _Z10stop_timerxPc
.type _Z10stop_timerxPc,@function
_Z10stop_timerxPc: # @_Z10stop_timerxPc
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $16, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rsi, %rbx
movq %rdi, %r14
movq %rsp, %r15
movq %r15, %rdi
xorl %esi, %esi
callq gettimeofday
imulq $1000000, (%r15), %rax # imm = 0xF4240
movq 8(%r15), %r15
subq %r14, %r15
addq %rax, %r15
cvtsi2ss %r15, %xmm0
divss .LCPI4_0(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movl $.L.str.5, %edi
movq %rbx, %rsi
movb $1, %al
callq printf
movq %r15, %rax
addq $16, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end4:
.size _Z10stop_timerxPc, .Lfunc_end4-_Z10stop_timerxPc
.cfi_endproc
# -- End function
.globl _Z11GPU_big_dotPfS_i # -- Begin function _Z11GPU_big_dotPfS_i
.type _Z11GPU_big_dotPfS_i,@function
_Z11GPU_big_dotPfS_i: # @_Z11GPU_big_dotPfS_i
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $24, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %edx, %r15d
movq %rsi, %r13
movq %rdi, %r14
movl $4, %edi
callq malloc
movq %rax, 16(%rsp) # 8-byte Spill
movl $0, (%rax)
leal (,%r15,4), %eax
movslq %eax, %r12
movq %rsp, %rbp
movq %rbp, %rdi
movq %r12, %rsi
callq hipMalloc
leaq 8(%rsp), %rbx
movq %rbx, %rdi
movq %r12, %rsi
callq hipMalloc
movq (%rbp), %rdi
movq %r14, %rsi
movq %r12, %rdx
movl $1, %ecx
callq hipMemcpy
movq (%rbx), %rdi
movq %r13, %rsi
movq %r12, %rdx
movl $1, %ecx
callq hipMemcpy
leal 511(%r15), %eax
leal 1022(%r15), %edi
testl %eax, %eax
cmovnsl %eax, %edi
sarl $9, %edi
btsq $32, %rdi
movabsq $4294967296, %rdx # imm = 0x100000000
orq $512, %rdx # imm = 0x200
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB5_2
# %bb.1:
movq (%rsp), %rdi
movq 8(%rsp), %rsi
movl %r15d, %edx
callq _Z23__device_stub__multiplyPfS_i
.LBB5_2:
movq (%rsp), %rsi
movq %r14, %rdi
movq %r12, %rdx
movl $2, %ecx
callq hipMemcpy
testl %r15d, %r15d
movq 16(%rsp), %rbx # 8-byte Reload
jle .LBB5_6
# %bb.3: # %.lr.ph
movl %r15d, %eax
xorps %xmm0, %xmm0
xorl %ecx, %ecx
.LBB5_4: # =>This Inner Loop Header: Depth=1
addss (%r14,%rcx,4), %xmm0
incq %rcx
cmpq %rcx, %rax
jne .LBB5_4
# %bb.5: # %._crit_edge
movss %xmm0, (%rbx)
.LBB5_6:
movq (%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq %rbx, %rax
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end5:
.size _Z11GPU_big_dotPfS_i, .Lfunc_end5-_Z11GPU_big_dotPfS_i
.cfi_endproc
# -- End function
.globl _Z23__device_stub__multiplyPfS_i # -- Begin function _Z23__device_stub__multiplyPfS_i
.type _Z23__device_stub__multiplyPfS_i,@function
_Z23__device_stub__multiplyPfS_i: # @_Z23__device_stub__multiplyPfS_i
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $112, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 40(%rsp), %rax
movq %rdi, (%rax)
leaq 32(%rsp), %rcx
movq %rsi, (%rcx)
leaq 12(%rsp), %rsi
movl %edx, (%rsi)
leaq 80(%rsp), %rbx
movq %rax, (%rbx)
movq %rcx, 8(%rbx)
movq %rsi, 16(%rbx)
leaq 64(%rsp), %r14
leaq 48(%rsp), %r15
leaq 24(%rsp), %r12
leaq 16(%rsp), %r13
movq %r14, %rdi
movq %r15, %rsi
movq %r12, %rdx
movq %r13, %rcx
callq __hipPopCallConfiguration
movq (%r14), %rsi
movl 8(%r14), %edx
movq (%r15), %rcx
movl 8(%r15), %r8d
movl $_Z8multiplyPfS_i, %edi
movq %rbx, %r9
pushq (%r13)
.cfi_adjust_cfa_offset 8
pushq (%r12)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $128, %rsp
.cfi_adjust_cfa_offset -128
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end6:
.size _Z23__device_stub__multiplyPfS_i, .Lfunc_end6-_Z23__device_stub__multiplyPfS_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
jne .LBB7_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, %rdi
movq %rax, __hip_gpubin_handle(%rip)
.LBB7_2:
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8multiplyPfS_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end7:
.size __hip_module_ctor, .Lfunc_end7-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB8_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB8_2:
retq
.Lfunc_end8:
.size __hip_module_dtor, .Lfunc_end8-__hip_module_dtor
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "\ncpu result: %f\n"
.size .L.str, 17
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "gpu result: %f\n"
.size .L.str.1, 16
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "difference between 2 results is: %f < 1.0e-6 ===> correct.\n"
.size .L.str.2, 60
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "difference between 2 results is: %f > 1.0e-6 ===> incorrect.\nExit Now!\n"
.size .L.str.3, 72
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "\nCPU/GPU speedup: %f\n"
.size .L.str.4, 22
.type _Z8multiplyPfS_i,@object # @_Z8multiplyPfS_i
.section .rodata,"a",@progbits
.globl _Z8multiplyPfS_i
.p2align 3, 0x0
_Z8multiplyPfS_i:
.quad _Z23__device_stub__multiplyPfS_i
.size _Z8multiplyPfS_i, 8
.type .L.str.5,@object # @.str.5
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.5:
.asciz "%s: %.5f sec\n"
.size .L.str.5, 14
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z8multiplyPfS_i"
.size .L__unnamed_1, 17
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z23__device_stub__multiplyPfS_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z8multiplyPfS_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
```
| 6,640 | 7,880 |
436 |
Convert the following CUDA device assembly code to AMD device assembly:
```cudaasm
code for sm_80
```
|
```amdasm
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object ; @__hip_cuid_
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0 ; 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
```
| 24 | 306 |
437 |
Convert the following CUDA host assembly code to AMD host assembly:
```cudaasm
.file "tmpxft_000032e2_00000000-6_hardware.cudafe1.cpp"
.text
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
```
|
```amdasm
.text
.file "hardware.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
```
| 747 | 183 |
438 |
Convert the following CUDA device assembly code to AMD device assembly:
```cudaasm
code for sm_80
```
|
```amdasm
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object ; @__hip_cuid_
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0 ; 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
```
| 24 | 306 |
439 |
Convert the following CUDA host assembly code to AMD host assembly:
```cudaasm
.file "tmpxft_001138bb_00000000-6_main.cudafe1.cpp"
.text
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z13reduction_seqPii
.type _Z13reduction_seqPii, @function
_Z13reduction_seqPii:
.LFB2058:
.cfi_startproc
endbr64
testl %esi, %esi
jle .L6
movq %rdi, %rax
movslq %esi, %rdx
leaq (%rdi,%rdx,4), %rcx
movl $0, %edx
.L5:
addl (%rax), %edx
addq $4, %rax
cmpq %rcx, %rax
jne .L5
.L4:
pxor %xmm0, %xmm0
cvtsi2sdl %edx, %xmm0
pxor %xmm1, %xmm1
cvtsi2sdl %esi, %xmm1
divsd %xmm1, %xmm0
ret
.L6:
movl $0, %edx
jmp .L4
.cfi_endproc
.LFE2058:
.size _Z13reduction_seqPii, .-_Z13reduction_seqPii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Sequential version...\n"
.LC1:
.string "Average: %f\n"
.LC2:
.string "OpenCL version...\n"
.LC3:
.string "CUDA version...\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
movl N(%rip), %ebx
movslq %ebx, %rdi
salq $2, %rdi
call malloc@PLT
movq %rax, %rbp
testl %ebx, %ebx
jle .L9
movl $0, %ebx
.L10:
call rand@PLT
movslq %eax, %rdx
imulq $1374389535, %rdx, %rdx
sarq $37, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
imull $100, %edx, %edx
subl %edx, %eax
movl %eax, 0(%rbp,%rbx,4)
addq $1, %rbx
cmpl %ebx, N(%rip)
jg .L10
.L9:
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl N(%rip), %esi
movq %rbp, %rdi
call _Z13reduction_seqPii
leaq .LC1(%rip), %rbx
movq %rbx, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl N(%rip), %esi
movq %rbp, %rdi
call _Z16reduction_openclPii@PLT
movq %rbx, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl N(%rip), %esi
movq %rbp, %rdi
call _Z14reduction_cudaPii@PLT
movq %rbx, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq %rbp, %rdi
call free@PLT
movl $0, %eax
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl N
.data
.align 4
.type N, @object
.size N, 4
N:
.long 8388608
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
```
|
```amdasm
.text
.file "main.hip"
.globl main # -- Begin function main
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
pushq %rax
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movslq N(%rip), %r14
leaq (,%r14,4), %rdi
callq malloc
movq %rax, %rbx
testq %r14, %r14
jle .LBB0_3
# %bb.1: # %.lr.ph.preheader
xorl %r14d, %r14d
.LBB0_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
callq rand
cltq
imulq $1374389535, %rax, %rcx # imm = 0x51EB851F
movq %rcx, %rdx
shrq $63, %rdx
sarq $37, %rcx
addl %edx, %ecx
imull $100, %ecx, %ecx
subl %ecx, %eax
movl %eax, (%rbx,%r14,4)
incq %r14
movslq N(%rip), %rax
cmpq %rax, %r14
jl .LBB0_2
.LBB0_3: # %._crit_edge
movl $.Lstr, %edi
callq puts@PLT
movl N(%rip), %eax
testl %eax, %eax
jle .LBB0_4
# %bb.5: # %.lr.ph.preheader.i
xorl %ecx, %ecx
xorl %edx, %edx
.LBB0_6: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
addl (%rbx,%rcx,4), %edx
incq %rcx
cmpq %rcx, %rax
jne .LBB0_6
# %bb.7: # %._crit_edge.loopexit.i
cvtsi2sd %edx, %xmm0
jmp .LBB0_8
.LBB0_4:
xorpd %xmm0, %xmm0
.LBB0_8: # %_Z13reduction_seqPii.exit
cvtsi2sd %eax, %xmm1
divsd %xmm1, %xmm0
movl $.L.str.1, %edi
movb $1, %al
callq printf
movl $.Lstr.1, %edi
callq puts@PLT
movl N(%rip), %esi
movq %rbx, %rdi
callq _Z16reduction_openclPii
movl $.L.str.1, %edi
movb $1, %al
callq printf
movl $.Lstr.2, %edi
callq puts@PLT
movl N(%rip), %esi
movq %rbx, %rdi
callq _Z14reduction_cudaPii
movl $.L.str.1, %edi
movb $1, %al
callq printf
movq %rbx, %rdi
callq free
xorl %eax, %eax
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.globl _Z13reduction_seqPii # -- Begin function _Z13reduction_seqPii
.type _Z13reduction_seqPii,@function
_Z13reduction_seqPii: # @_Z13reduction_seqPii
.cfi_startproc
# %bb.0:
testl %esi, %esi
jle .LBB1_1
# %bb.2: # %.lr.ph.preheader
movl %esi, %eax
xorl %ecx, %ecx
xorl %edx, %edx
.LBB1_3: # %.lr.ph
# =>This Inner Loop Header: Depth=1
addl (%rdi,%rcx,4), %edx
incq %rcx
cmpq %rcx, %rax
jne .LBB1_3
# %bb.4: # %._crit_edge.loopexit
cvtsi2sd %edx, %xmm0
jmp .LBB1_5
.LBB1_1:
xorpd %xmm0, %xmm0
.LBB1_5: # %._crit_edge
cvtsi2sd %esi, %xmm1
divsd %xmm1, %xmm0
retq
.Lfunc_end1:
.size _Z13reduction_seqPii, .Lfunc_end1-_Z13reduction_seqPii
.cfi_endproc
# -- End function
.type N,@object # @N
.data
.globl N
.p2align 2, 0x0
N:
.long 8388608 # 0x800000
.size N, 4
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "Average: %f\n"
.size .L.str.1, 13
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Sequential version..."
.size .Lstr, 22
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "OpenCL version..."
.size .Lstr.1, 18
.type .Lstr.2,@object # @str.2
.Lstr.2:
.asciz "CUDA version..."
.size .Lstr.2, 16
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
```
| 1,932 | 1,738 |
444 |
Convert the following CUDA device assembly code to AMD device assembly:
```cudaasm
code for sm_80
Function : _Z4blurP6uchar3S0_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ;
S2R R3, SR_CTAID.Y ;
S2R R0, SR_TID.Y ;
S2R R2, SR_CTAID.X ;
S2R R5, SR_TID.X ;
IMAD R3, R3, c[0x0][0x4], R0 ;
ISETP.GE.AND P0, PT, R3, c[0x0][0x174], PT ;
IMAD R2, R2, c[0x0][0x0], R5 ;
ISETP.GE.OR P0, PT, R2, c[0x0][0x170], P0 ;
@P0 EXIT ;
UMOV UR5, 0x3 ;
ULDC.64 UR6, c[0x0][0x170] ;
UIADD3 UR4, -UR5, UR6, URZ ;
ISETP.GE.AND P0, PT, R2, UR4, PT ;
UIADD3 UR4, -UR5, UR7, URZ ;
ISETP.LT.OR P0, PT, R2, 0x4, P0 ;
ISETP.LT.OR P0, PT, R3, 0x4, P0 ;
ISETP.GE.OR P0, PT, R3, UR4, P0 ;
@P0 EXIT ;
IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x170] ;
ULDC.64 UR4, c[0x0][0x118] ;
IMAD R3, R3, c[0x0][0x170], RZ ;
IMAD.MOV.U32 R4, RZ, RZ, 0x3 ;
IMAD R5, R0, -0x3, R3 ;
IADD3 R5, R2, R5, RZ ;
IADD3 R7, R5, 0x2, RZ ;
IMAD.WIDE R6, R7, R4, c[0x0][0x160] ;
LDG.E.U8 R8, [R6.64+-0x9] ;
LDG.E.U8 R9, [R6.64+-0x6] ;
LDG.E.U8 R11, [R6.64+-0x3] ;
IADD3 R3, R2, R3, RZ ;
IMAD.WIDE R2, R3, R4, c[0x0][0x168] ;
IMAD R8, R9, 0x2, R8 ;
IMAD.IADD R11, R8, 0x1, R11 ;
IMAD.WIDE R8, R0, 0x3, R6 ;
SHF.R.U32.HI R13, RZ, 0x2, R11 ;
STG.E.U8 [R2.64], R13 ;
LDG.E.U8 R10, [R8.64] ;
LDG.E.U8 R15, [R8.64+-0x3] ;
LDG.E.U8 R12, [R8.64+-0x6] ;
LDG.E.U8 R7, [R8.64+-0x9] ;
LDG.E.U8 R6, [R8.64+-0xc] ;
IADD3 R5, R5, -0x1, RZ ;
IMAD.WIDE R4, R5, R4, c[0x0][0x160] ;
IMAD.WIDE R4, R0, 0x3, R4 ;
IMAD.WIDE R4, R0, 0x3, R4 ;
PRMT R10, R15, 0x7604, R10 ;
PRMT R7, R7, 0x7604, R12 ;
PRMT R7, R7, 0x1054, R10 ;
IDP.4A.U8.U8 R7, R7, c[0x2][0x0], RZ ;
IMAD R6, R6, 0x3, R7 ;
IMAD.IADD R6, R11, 0x1, R6 ;
IMAD.HI R7, R6, 0x6bca1af3, RZ ;
SHF.R.U32.HI R8, RZ, 0x1f, R7 ;
LEA.HI R7, R7, R8, RZ, 0x1c ;
STG.E.U8 [R2.64], R7 ;
LDG.E.U8 R11, [R4.64+0x9] ;
LDG.E.U8 R12, [R4.64+0x6] ;
LDG.E.U8 R13, [R4.64+0x3] ;
LDG.E.U8 R14, [R4.64] ;
LDG.E.U8 R10, [R4.64+0xc] ;
LDG.E.U8 R8, [R4.64+-0x3] ;
LDG.E.U8 R9, [R4.64+-0x6] ;
PRMT R11, R12, 0x7604, R11 ;
PRMT R14, R14, 0x7604, R13 ;
PRMT R11, R14, 0x1054, R11 ;
IDP.4A.U8.U8 R11, R11, c[0x2][0x4], R10 ;
IMAD R8, R8, 0xd, R11 ;
IADD3 R8, R8, R6, R9 ;
IMAD.HI R6, R8, 0x749cb29, RZ ;
SHF.R.U32.HI R7, RZ, 0x1f, R6 ;
LEA.HI R9, R6, R7, RZ, 0x1d ;
IMAD.WIDE R6, R0, 0x3, R4 ;
STG.E.U8 [R2.64], R9 ;
LDG.E.U8 R10, [R6.64+0x9] ;
LDG.E.U8 R11, [R6.64+0x6] ;
LDG.E.U8 R12, [R6.64+0x3] ;
LDG.E.U8 R13, [R6.64] ;
LDG.E.U8 R4, [R6.64+-0x3] ;
LDG.E.U8 R15, [R6.64+0xc] ;
LDG.E.U8 R5, [R6.64+-0x6] ;
IMAD.WIDE R6, R0, 0x3, R6 ;
PRMT R10, R11, 0x7604, R10 ;
PRMT R13, R13, 0x7604, R12 ;
PRMT R10, R13, 0x1054, R10 ;
IMAD R15, R4, 0xb, R15 ;
IDP.4A.U8.U8 R10, R10, c[0x2][0x8], RZ ;
LEA R5, R5, R8, 0x1 ;
IMAD.U32 R10, R15, 0x2, R10 ;
IMAD.IADD R5, R5, 0x1, R10 ;
IMAD.HI R4, R5, 0x300c0301, RZ ;
SHF.R.U32.HI R9, RZ, 0x1f, R4 ;
LEA.HI R9, R4, R9, RZ, 0x19 ;
STG.E.U8 [R2.64], R9 ;
LDG.E.U8 R11, [R6.64+0x9] ;
LDG.E.U8 R12, [R6.64+0x6] ;
LDG.E.U8 R13, [R6.64+0x3] ;
LDG.E.U8 R14, [R6.64] ;
LDG.E.U8 R10, [R6.64+0xc] ;
LDG.E.U8 R8, [R6.64+-0x3] ;
LDG.E.U8 R4, [R6.64+-0x6] ;
IMAD.WIDE R6, R0, 0x3, R6 ;
PRMT R11, R12, 0x7604, R11 ;
PRMT R14, R14, 0x7604, R13 ;
PRMT R11, R14, 0x1054, R11 ;
IDP.4A.U8.U8 R11, R11, c[0x2][0x4], R10 ;
IMAD R8, R8, 0xd, R11 ;
IADD3 R5, R8, R5, R4 ;
HFMA2.MMA R4, -RZ, RZ, 0, 0 ;
IMAD.HI R4, R5, -0x724cf039, R4 ;
SHF.R.U32.HI R9, RZ, 0x1f, R4 ;
LEA.HI R9, R4, R9, RZ, 0x17 ;
STG.E.U8 [R2.64], R9 ;
LDG.E.U8 R8, [R6.64+0x9] ;
LDG.E.U8 R11, [R6.64+0x6] ;
LDG.E.U8 R10, [R6.64+0x3] ;
LDG.E.U8 R13, [R6.64] ;
LDG.E.U8 R4, [R6.64+-0x3] ;
IMAD.WIDE R6, R0, 0x3, R6 ;
PRMT R8, R11, 0x7604, R8 ;
PRMT R13, R13, 0x7604, R10 ;
PRMT R8, R13, 0x1054, R8 ;
IDP.4A.U8.U8 R11, R8, c[0x2][0xc], RZ ;
IMAD R4, R4, 0x3, R11 ;
IMAD.IADD R5, R5, 0x1, R4 ;
IMAD.MOV.U32 R4, RZ, RZ, RZ ;
IMAD.HI R4, R5, -0x78bc1a6b, R4 ;
SHF.R.U32.HI R9, RZ, 0x1f, R4 ;
LEA.HI R9, R4, R9, RZ, 0x17 ;
STG.E.U8 [R2.64], R9 ;
LDG.E.U8 R4, [R6.64] ;
LDG.E.U8 R11, [R6.64+0x3] ;
LDG.E.U8 R13, [R6.64+0x6] ;
IADD3 R4, R5, R4, RZ ;
IMAD R4, R11, 0x2, R4 ;
IADD3 R4, R4, R13, RZ ;
IMAD.HI R4, R4, 0x10d6b155, RZ ;
SHF.R.U32.HI R5, RZ, 0x1f, R4 ;
LEA.HI R5, R4, R5, RZ, 0x1a ;
STG.E.U8 [R2.64], R5 ;
STG.E.U8 [R2.64+0x1], R5 ;
STG.E.U8 [R2.64+0x2], R5 ;
EXIT ;
BRA 0x8f0;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
```
|
```amdasm
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z4blurP15HIP_vector_typeIhLj3EES1_ii ; -- Begin function _Z4blurP15HIP_vector_typeIhLj3EES1_ii
.globl _Z4blurP15HIP_vector_typeIhLj3EES1_ii
.p2align 8
.type _Z4blurP15HIP_vector_typeIhLj3EES1_ii,@function
_Z4blurP15HIP_vector_typeIhLj3EES1_ii: ; @_Z4blurP15HIP_vector_typeIhLj3EES1_ii
; %bb.0:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b64 s[4:5], s[0:1], 0x10
v_and_b32_e32 v1, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
s_mul_i32 s14, s14, s3
s_mov_b32 s3, exec_lo
v_add_nc_u32_e32 v2, s14, v1
v_cmpx_gt_i32_e64 s4, v2
s_cbranch_execz .LBB0_7
; %bb.1:
v_bfe_u32 v0, v0, 10, 10
s_lshr_b32 s2, s2, 16
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[3:4], null, s15, s2, v[0:1]
v_cmp_lt_i32_e64 s2, 3, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_gt_i32_e32 vcc_lo, s5, v3
s_and_b32 s2, s2, vcc_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 exec_lo, exec_lo, s2
s_cbranch_execz .LBB0_7
; %bb.2:
s_add_i32 s2, s4, -3
s_add_i32 s3, s5, -3
v_cmp_gt_i32_e32 vcc_lo, s2, v2
v_cmp_gt_i32_e64 s2, s3, v3
v_cmp_lt_i32_e64 s3, 3, v3
s_delay_alu instid0(VALU_DEP_2)
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
s_and_b32 s2, s2, s3
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 exec_lo, exec_lo, s2
s_cbranch_execz .LBB0_7
; %bb.3: ; %.preheader54
s_load_b128 s[0:3], s[0:1], 0x0
v_add_nc_u32_e32 v0, -3, v3
v_mad_u64_u32 v[4:5], null, v3, s4, v[2:3]
s_mov_b32 s5, 0
s_mov_b32 s8, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[2:3], null, s4, v0, v[1:2]
s_waitcnt lgkmcnt(0)
v_mad_i64_i32 v[0:1], null, v4, 3, s[2:3]
s_delay_alu instid0(VALU_DEP_2)
v_add3_u32 v4, v2, s14, -3
v_mov_b32_e32 v2, 0
s_getpc_b64 s[2:3]
s_add_u32 s2, s2, __const._Z4blurP15HIP_vector_typeIhLj3EES1_ii.matrix@rel32@lo+4
s_addc_u32 s3, s3, __const._Z4blurP15HIP_vector_typeIhLj3EES1_ii.matrix@rel32@hi+12
.LBB0_4: ; %.preheader
; =>This Loop Header: Depth=1
; Child Loop BB0_5 Depth 2
v_mov_b32_e32 v5, v4
s_mov_b64 s[6:7], 0
.LBB0_5: ; Parent Loop BB0_4 Depth=1
; => This Inner Loop Header: Depth=2
s_delay_alu instid0(VALU_DEP_1)
v_mad_i64_i32 v[6:7], null, v5, 3, s[0:1]
s_add_u32 s10, s2, s6
s_addc_u32 s11, s3, s7
v_add_nc_u32_e32 v5, 1, v5
s_load_b32 s9, s[10:11], 0x0
global_load_u8 v7, v[6:7], off
v_mov_b32_e32 v6, v2
s_waitcnt lgkmcnt(0)
s_add_i32 s8, s9, s8
s_add_u32 s6, s6, 28
s_addc_u32 s7, s7, 0
s_cmpk_eq_i32 s6, 0xc4
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[2:3], null, s9, v7, v[6:7]
s_cbranch_scc0 .LBB0_5
; %bb.6: ; in Loop: Header=BB0_4 Depth=1
s_ashr_i32 s6, s8, 31
s_delay_alu instid0(VALU_DEP_1)
v_ashrrev_i32_e32 v6, 31, v2
s_add_i32 s7, s8, s6
s_add_i32 s5, s5, 1
s_xor_b32 s7, s7, s6
v_add_nc_u32_e32 v4, s4, v4
v_cvt_f32_u32_e32 v3, s7
s_sub_i32 s9, 0, s7
v_add_nc_u32_e32 v7, v2, v6
s_add_u32 s2, s2, 4
s_addc_u32 s3, s3, 0
v_rcp_iflag_f32_e32 v3, v3
s_cmp_eq_u32 s5, 7
v_xor_b32_e32 v7, v7, v6
v_xor_b32_e32 v6, s6, v6
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v3, 0x4f7ffffe, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_u32_f32_e32 v3, v3
v_mul_lo_u32 v5, s9, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v5, v3, v5
v_add_nc_u32_e32 v3, v3, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v3, v7, v3
v_mul_lo_u32 v5, v3, s7
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v5, v7, v5
v_add_nc_u32_e32 v7, 1, v3
v_subrev_nc_u32_e32 v8, s7, v5
v_cmp_le_u32_e32 vcc_lo, s7, v5
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cndmask_b32_e32 v3, v3, v7, vcc_lo
v_cndmask_b32_e32 v5, v5, v8, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v7, 1, v3
v_cmp_le_u32_e32 vcc_lo, s7, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v3, v3, v7, vcc_lo
v_xor_b32_e32 v3, v3, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v3, v3, v6
v_and_b32_e32 v6, 0xff, v3
v_lshlrev_b16 v5, 8, v3
s_delay_alu instid0(VALU_DEP_1)
v_or_b32_e32 v5, v6, v5
s_clause 0x1
global_store_b8 v[0:1], v3, off offset:2
global_store_b16 v[0:1], v5, off
s_cbranch_scc0 .LBB0_4
.LBB0_7: ; %.loopexit
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z4blurP15HIP_vector_typeIhLj3EES1_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z4blurP15HIP_vector_typeIhLj3EES1_ii, .Lfunc_end0-_Z4blurP15HIP_vector_typeIhLj3EES1_ii
; -- End function
.section .AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 608
; NumSgprs: 18
; NumVgprs: 9
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 9
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __const._Z4blurP15HIP_vector_typeIhLj3EES1_ii.matrix,@object ; @__const._Z4blurP15HIP_vector_typeIhLj3EES1_ii.matrix
.section .rodata,"a",@progbits
.p2align 4, 0x0
__const._Z4blurP15HIP_vector_typeIhLj3EES1_ii.matrix:
.long 0 ; 0x0
.long 0 ; 0x0
.long 1 ; 0x1
.long 2 ; 0x2
.long 1 ; 0x1
.long 0 ; 0x0
.long 0 ; 0x0
.long 0 ; 0x0
.long 3 ; 0x3
.long 13 ; 0xd
.long 22 ; 0x16
.long 13 ; 0xd
.long 3 ; 0x3
.long 0 ; 0x0
.long 1 ; 0x1
.long 3 ; 0x3
.long 59 ; 0x3b
.long 97 ; 0x61
.long 59 ; 0x3b
.long 13 ; 0xd
.long 1 ; 0x1
.long 2 ; 0x2
.long 22 ; 0x16
.long 97 ; 0x61
.long 159 ; 0x9f
.long 97 ; 0x61
.long 22 ; 0x16
.long 2 ; 0x2
.long 1 ; 0x1
.long 3 ; 0x3
.long 59 ; 0x3b
.long 97 ; 0x61
.long 59 ; 0x3b
.long 3 ; 0x3
.long 1 ; 0x1
.long 0 ; 0x0
.long 3 ; 0x3
.long 13 ; 0xd
.long 22 ; 0x16
.long 13 ; 0xd
.long 3 ; 0x3
.long 0 ; 0x0
.long 0 ; 0x0
.long 0 ; 0x0
.long 1 ; 0x1
.long 2 ; 0x2
.long 1 ; 0x1
.long 0 ; 0x0
.long 0 ; 0x0
.size __const._Z4blurP15HIP_vector_typeIhLj3EES1_ii.matrix, 196
.type __hip_cuid_,@object ; @__hip_cuid_
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0 ; 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z4blurP15HIP_vector_typeIhLj3EES1_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z4blurP15HIP_vector_typeIhLj3EES1_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
```
| 2,921 | 5,193 |
445 |
Convert the following CUDA host assembly code to AMD host assembly:
```cudaasm
.file "tmpxft_001391bf_00000000-6_blur.cudafe1.cpp"
.text
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z34__device_stub__Z4blurP6uchar3S0_iiP6uchar3S0_ii
.type _Z34__device_stub__Z4blurP6uchar3S0_iiP6uchar3S0_ii, @function
_Z34__device_stub__Z4blurP6uchar3S0_iiP6uchar3S0_ii:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z4blurP6uchar3S0_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z34__device_stub__Z4blurP6uchar3S0_iiP6uchar3S0_ii, .-_Z34__device_stub__Z4blurP6uchar3S0_iiP6uchar3S0_ii
.globl _Z4blurP6uchar3S0_ii
.type _Z4blurP6uchar3S0_ii, @function
_Z4blurP6uchar3S0_ii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z34__device_stub__Z4blurP6uchar3S0_iiP6uchar3S0_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z4blurP6uchar3S0_ii, .-_Z4blurP6uchar3S0_ii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z4blurP6uchar3S0_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z4blurP6uchar3S0_ii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
```
|
```amdasm
.text
.file "blur.hip"
.globl _Z19__device_stub__blurP15HIP_vector_typeIhLj3EES1_ii # -- Begin function _Z19__device_stub__blurP15HIP_vector_typeIhLj3EES1_ii
.type _Z19__device_stub__blurP15HIP_vector_typeIhLj3EES1_ii,@function
_Z19__device_stub__blurP15HIP_vector_typeIhLj3EES1_ii: # @_Z19__device_stub__blurP15HIP_vector_typeIhLj3EES1_ii
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $112, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 40(%rsp), %rax
movq %rdi, (%rax)
leaq 32(%rsp), %rdi
movq %rsi, (%rdi)
leaq 12(%rsp), %rsi
movl %edx, (%rsi)
leaq 8(%rsp), %rdx
movl %ecx, (%rdx)
leaq 80(%rsp), %rbx
movq %rax, (%rbx)
movq %rdi, 8(%rbx)
movq %rsi, 16(%rbx)
movq %rdx, 24(%rbx)
leaq 64(%rsp), %r14
leaq 48(%rsp), %r15
leaq 24(%rsp), %r12
leaq 16(%rsp), %r13
movq %r14, %rdi
movq %r15, %rsi
movq %r12, %rdx
movq %r13, %rcx
callq __hipPopCallConfiguration
movq (%r14), %rsi
movl 8(%r14), %edx
movq (%r15), %rcx
movl 8(%r15), %r8d
movl $_Z4blurP15HIP_vector_typeIhLj3EES1_ii, %edi
movq %rbx, %r9
pushq (%r13)
.cfi_adjust_cfa_offset 8
pushq (%r12)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $128, %rsp
.cfi_adjust_cfa_offset -128
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z19__device_stub__blurP15HIP_vector_typeIhLj3EES1_ii, .Lfunc_end0-_Z19__device_stub__blurP15HIP_vector_typeIhLj3EES1_ii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, %rdi
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z4blurP15HIP_vector_typeIhLj3EES1_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z4blurP15HIP_vector_typeIhLj3EES1_ii,@object # @_Z4blurP15HIP_vector_typeIhLj3EES1_ii
.section .rodata,"a",@progbits
.globl _Z4blurP15HIP_vector_typeIhLj3EES1_ii
.p2align 3, 0x0
_Z4blurP15HIP_vector_typeIhLj3EES1_ii:
.quad _Z19__device_stub__blurP15HIP_vector_typeIhLj3EES1_ii
.size _Z4blurP15HIP_vector_typeIhLj3EES1_ii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z4blurP15HIP_vector_typeIhLj3EES1_ii"
.size .L__unnamed_1, 38
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z19__device_stub__blurP15HIP_vector_typeIhLj3EES1_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z4blurP15HIP_vector_typeIhLj3EES1_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
```
| 1,936 | 2,251 |
446 |
Convert the following CUDA device assembly code to AMD device assembly:
```cudaasm
code for sm_80
Function : _Z20compareWithOneKernelPfPKd
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ;
S2R R0, SR_TID.X ;
HFMA2.MMA R3, -RZ, RZ, 0, 4.76837158203125e-07 ;
ULDC.64 UR4, c[0x0][0x118] ;
IMAD.WIDE R2, R0, R3, c[0x0][0x168] ;
LDG.E.64 R2, [R2.64] ;
DSETP.NEU.AND P0, PT, R2, 1, PT ;
@P0 EXIT ;
SHF.R.S32.HI R3, RZ, 0x1f, R0 ;
LEA R2, P0, R0, c[0x0][0x160], 0x2 ;
LEA.HI.X R3, R0, c[0x0][0x164], R3, 0x2, P0 ;
LDG.E R0, [R2.64] ;
FADD R5, R0, 1 ;
STG.E [R2.64], R5 ;
EXIT ;
BRA 0xf0;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
```
|
```amdasm
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z20compareWithOneKernelPfPKd ; -- Begin function _Z20compareWithOneKernelPfPKd
.globl _Z20compareWithOneKernelPfPKd
.p2align 8
.type _Z20compareWithOneKernelPfPKd,@function
_Z20compareWithOneKernelPfPKd: ; @_Z20compareWithOneKernelPfPKd
; %bb.0:
s_load_b128 s[0:3], s[0:1], 0x0
v_lshlrev_b32_e32 v1, 3, v0
s_waitcnt lgkmcnt(0)
global_load_b64 v[1:2], v1, s[2:3]
s_mov_b32 s2, exec_lo
s_waitcnt vmcnt(0)
v_cmpx_eq_f64_e32 1.0, v[1:2]
s_cbranch_execz .LBB0_2
; %bb.1:
v_lshlrev_b32_e32 v0, 2, v0
global_load_b32 v1, v0, s[0:1]
s_waitcnt vmcnt(0)
v_add_f32_e32 v1, 1.0, v1
global_store_b32 v0, v1, s[0:1]
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z20compareWithOneKernelPfPKd
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 16
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 4
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z20compareWithOneKernelPfPKd, .Lfunc_end0-_Z20compareWithOneKernelPfPKd
; -- End function
.section .AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 80
; NumSgprs: 4
; NumVgprs: 3
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 0
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 4
; NumVGPRsForWavesPerEU: 3
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object ; @__hip_cuid_
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0 ; 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 16
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z20compareWithOneKernelPfPKd
.private_segment_fixed_size: 0
.sgpr_count: 4
.sgpr_spill_count: 0
.symbol: _Z20compareWithOneKernelPfPKd.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
```
| 389 | 1,838 |
447 |
Convert the following CUDA host assembly code to AMD host assembly:
```cudaasm
.file "tmpxft_0009ecbb_00000000-6_compareWithOneKernel.cudafe1.cpp"
.text
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z43__device_stub__Z20compareWithOneKernelPfPKdPfPKd
.type _Z43__device_stub__Z20compareWithOneKernelPfPKdPfPKd, @function
_Z43__device_stub__Z20compareWithOneKernelPfPKdPfPKd:
.LFB2051:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z20compareWithOneKernelPfPKd(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z43__device_stub__Z20compareWithOneKernelPfPKdPfPKd, .-_Z43__device_stub__Z20compareWithOneKernelPfPKdPfPKd
.globl _Z20compareWithOneKernelPfPKd
.type _Z20compareWithOneKernelPfPKd, @function
_Z20compareWithOneKernelPfPKd:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z43__device_stub__Z20compareWithOneKernelPfPKdPfPKd
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z20compareWithOneKernelPfPKd, .-_Z20compareWithOneKernelPfPKd
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z20compareWithOneKernelPfPKd"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z20compareWithOneKernelPfPKd(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
```
|
```amdasm
.text
.file "compareWithOneKernel.hip"
.globl _Z35__device_stub__compareWithOneKernelPfPKd # -- Begin function _Z35__device_stub__compareWithOneKernelPfPKd
.type _Z35__device_stub__compareWithOneKernelPfPKd,@function
_Z35__device_stub__compareWithOneKernelPfPKd: # @_Z35__device_stub__compareWithOneKernelPfPKd
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $80, %rsp
.cfi_def_cfa_offset 128
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 24(%rsp), %rax
movq %rdi, (%rax)
leaq 16(%rsp), %rcx
movq %rsi, (%rcx)
leaq 64(%rsp), %rbx
movq %rax, (%rbx)
movq %rcx, 8(%rbx)
leaq 48(%rsp), %r14
leaq 32(%rsp), %r15
leaq 8(%rsp), %r12
movq %rsp, %r13
movq %r14, %rdi
movq %r15, %rsi
movq %r12, %rdx
movq %r13, %rcx
callq __hipPopCallConfiguration
movq (%r14), %rsi
movl 8(%r14), %edx
movq (%r15), %rcx
movl 8(%r15), %r8d
movl $_Z20compareWithOneKernelPfPKd, %edi
movq %rbx, %r9
pushq (%r13)
.cfi_adjust_cfa_offset 8
pushq (%r12)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $96, %rsp
.cfi_adjust_cfa_offset -96
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z35__device_stub__compareWithOneKernelPfPKd, .Lfunc_end0-_Z35__device_stub__compareWithOneKernelPfPKd
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, %rdi
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z20compareWithOneKernelPfPKd, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z20compareWithOneKernelPfPKd,@object # @_Z20compareWithOneKernelPfPKd
.section .rodata,"a",@progbits
.globl _Z20compareWithOneKernelPfPKd
.p2align 3, 0x0
_Z20compareWithOneKernelPfPKd:
.quad _Z35__device_stub__compareWithOneKernelPfPKd
.size _Z20compareWithOneKernelPfPKd, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z20compareWithOneKernelPfPKd"
.size .L__unnamed_1, 30
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z35__device_stub__compareWithOneKernelPfPKd
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z20compareWithOneKernelPfPKd
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
```
| 1,831 | 2,021 |
448 |
Convert the following CUDA device assembly code to AMD device assembly:
```cudaasm
code for sm_80
Function : _Z11calculatePiPdli
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ;
IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x170] ;
S2R R7, SR_CTAID.X ;
S2R R0, SR_TID.X ;
SHF.R.S32.HI R6, RZ, 0x1f, R4 ;
LOP3.LUT R2, R6, c[0x0][0x16c], RZ, 0xfc, !PT ;
ISETP.NE.U32.AND P0, PT, R2, RZ, PT ;
IMAD R7, R7, c[0x0][0x0], R0 ;
@!P0 BRA 0xc0 ;
MOV R0, 0xb0 ;
CALL.REL.NOINC 0x1ee0 ;
BRA 0x1f0 ;
I2F.U32.RP R0, c[0x0][0x170] ;
ISETP.NE.U32.AND P2, PT, RZ, c[0x0][0x170], PT ;
IMAD.MOV.U32 R11, RZ, RZ, RZ ;
MUFU.RCP R0, R0 ;
IADD3 R2, R0, 0xffffffe, RZ ;
F2I.FTZ.U32.TRUNC.NTZ R3, R2 ;
IMAD.MOV.U32 R2, RZ, RZ, RZ ;
IMAD.MOV R5, RZ, RZ, -R3 ;
IMAD R5, R5, c[0x0][0x170], RZ ;
IMAD.HI.U32 R3, R3, R5, R2 ;
IMAD.HI.U32 R10, R3, c[0x0][0x168], RZ ;
IMAD.MOV R3, RZ, RZ, -R10 ;
IMAD R3, R4, R3, c[0x0][0x168] ;
ISETP.GE.U32.AND P0, PT, R3, c[0x0][0x170], PT ;
@P0 IADD3 R3, R3, -c[0x0][0x170], RZ ;
@P0 IADD3 R10, R10, 0x1, RZ ;
ISETP.GE.U32.AND P1, PT, R3, c[0x0][0x170], PT ;
@P1 IADD3 R10, R10, 0x1, RZ ;
@!P2 LOP3.LUT R10, RZ, c[0x0][0x170], RZ, 0x33, !PT ;
SHF.R.S32.HI R4, RZ, 0x1f, R7 ;
IMAD R3, R11, R7.reuse, RZ ;
BSSY B1, 0x780 ;
IMAD.WIDE.U32 R8, R10, R7, RZ ;
CS2R R24, SRZ ;
IMAD R3, R4, R10, R3 ;
IADD3 R0, P3, R8, 0x2, RZ ;
IADD3 R5, P1, P2, R10, -0x1, R8 ;
IMAD.IADD R3, R9, 0x1, R3 ;
LOP3.LUT R27, RZ, R8, RZ, 0x33, !PT ;
ISETP.GT.U32.AND P0, PT, R5, R0, PT ;
IMAD.X R9, RZ, RZ, R3.reuse, P3 ;
IADD3.X R2, R11, -0x1, R3, P1, P2 ;
LOP3.LUT R28, RZ, R3, RZ, 0x33, !PT ;
ISETP.GT.AND.EX P0, PT, R2, R9, PT, P0 ;
SEL R0, R5, R0, P0 ;
SEL R9, R2, R9, P0 ;
IADD3 R27, P0, R27, R0, RZ ;
IMAD.X R28, R28, 0x1, R9, P0 ;
SHF.R.U64 R0, R27, 0x1, R28 ;
IADD3 R0, R0, 0x1, RZ ;
LOP3.LUT R29, R0, 0x3, RZ, 0xc0, !PT ;
IMAD.MOV.U32 R0, RZ, RZ, R8 ;
ISETP.NE.U32.AND P0, PT, R29, RZ, PT ;
ISETP.NE.AND.EX P0, PT, RZ, RZ, PT, P0 ;
@!P0 BRA 0x770 ;
IADD3 R29, P0, RZ, -R29, RZ ;
IMAD.SHL.U32 R31, R0.reuse, 0x2, RZ ;
SHF.L.U64.HI R30, R0, 0x1, R3 ;
CS2R R24, SRZ ;
IMAD.X R32, RZ, RZ, -0x1, P0 ;
IADD3 R16, P0, R31, 0x1, RZ ;
IMAD.MOV.U32 R8, RZ, RZ, 0x1 ;
BSSY B2, 0x580 ;
IMAD.X R17, RZ, RZ, R30, P0 ;
IADD3 R29, P0, R29, 0x1, RZ ;
I2F.F64.S64 R16, R16 ;
IMAD.X R32, RZ, RZ, R32, P0 ;
ISETP.NE.U32.AND P0, PT, R29, RZ, PT ;
ISETP.NE.AND.EX P0, PT, R32, RZ, PT, P0 ;
MUFU.RCP64H R9, R17 ;
DFMA R10, -R16, R8, 1 ;
DFMA R10, R10, R10, R10 ;
DFMA R10, R8, R10, R8 ;
DFMA R8, -R16, R10, 1 ;
DFMA R8, R10, R8, R10 ;
DMUL R34, R8, 4 ;
DFMA R10, -R16, R34, 4 ;
DFMA R34, R8, R10, R34 ;
FFMA R8, RZ, R17, R35 ;
FSETP.GT.AND P1, PT, |R8|, 1.469367938527859385e-39, PT ;
@P1 BRA 0x570 ;
IMAD.MOV.U32 R18, RZ, RZ, RZ ;
MOV R8, 0x570 ;
IMAD.MOV.U32 R19, RZ, RZ, 0x40100000 ;
CALL.REL.NOINC 0x1910 ;
BSYNC B2 ;
IADD3 R16, P1, R31, 0x3, RZ ;
IMAD.MOV.U32 R8, RZ, RZ, 0x1 ;
BSSY B2, 0x710 ;
DADD R24, R34, R24 ;
IMAD.X R17, RZ, RZ, R30, P1 ;
I2F.F64.S64 R16, R16 ;
MUFU.RCP64H R9, R17 ;
DFMA R10, -R16, R8, 1 ;
DFMA R10, R10, R10, R10 ;
DFMA R8, R8, R10, R8 ;
DFMA R10, -R16, R8, 1 ;
DFMA R8, R8, R10, R8 ;
DMUL R10, R8, 4 ;
DFMA R12, -R16, R10, 4 ;
DFMA R8, R8, R12, R10 ;
FFMA R10, RZ, R17, R9 ;
FSETP.GT.AND P1, PT, |R10|, 1.469367938527859385e-39, PT ;
@P1 BRA 0x700 ;
IMAD.MOV.U32 R18, RZ, RZ, RZ ;
MOV R8, 0x6e0 ;
IMAD.MOV.U32 R19, RZ, RZ, 0x40100000 ;
CALL.REL.NOINC 0x1910 ;
IMAD.MOV.U32 R8, RZ, RZ, R34 ;
IMAD.MOV.U32 R9, RZ, RZ, R35 ;
BSYNC B2 ;
IADD3 R0, P1, R0, 0x2, RZ ;
DADD R24, R24, -R8 ;
IADD3 R31, P2, R31, 0x4, RZ ;
IMAD.X R3, RZ, RZ, R3, P1 ;
IMAD.X R30, RZ, RZ, R30, P2 ;
@P0 BRA 0x3e0 ;
BSYNC B1 ;
ISETP.GE.U32.AND P0, PT, R27, 0x6, PT ;
ULDC.64 UR10, c[0x0][0x118] ;
BSSY B1, 0x1480 ;
ISETP.GE.U32.AND.EX P0, PT, R28, RZ, PT, P0 ;
@!P0 BRA 0x1470 ;
SHF.L.U64.HI R27, R0.reuse, 0x1, R3 ;
IMAD.SHL.U32 R28, R0, 0x2, RZ ;
IADD3 R16, P0, R28, 0x1, RZ ;
IMAD.MOV.U32 R8, RZ, RZ, 0x1 ;
BSSY B2, 0x950 ;
IMAD.X R17, RZ, RZ, R27, P0 ;
I2F.F64.S64 R16, R16 ;
MUFU.RCP64H R9, R17 ;
DFMA R10, -R16, R8, 1 ;
DFMA R10, R10, R10, R10 ;
DFMA R10, R8, R10, R8 ;
DFMA R8, -R16, R10, 1 ;
DFMA R8, R10, R8, R10 ;
DMUL R34, R8, 4 ;
DFMA R10, -R16, R34, 4 ;
DFMA R34, R8, R10, R34 ;
FFMA R8, RZ, R17, R35 ;
FSETP.GT.AND P0, PT, |R8|, 1.469367938527859385e-39, PT ;
@P0 BRA 0x940 ;
IMAD.MOV.U32 R18, RZ, RZ, RZ ;
MOV R8, 0x940 ;
IMAD.MOV.U32 R19, RZ, RZ, 0x40100000 ;
CALL.REL.NOINC 0x1910 ;
BSYNC B2 ;
IADD3 R16, P0, R28, 0x3, RZ ;
IMAD.MOV.U32 R8, RZ, RZ, 0x1 ;
BSSY B2, 0xae0 ;
DADD R24, R34, R24 ;
IMAD.X R17, RZ, RZ, R27, P0 ;
I2F.F64.S64 R16, R16 ;
MUFU.RCP64H R9, R17 ;
DFMA R10, -R16, R8, 1 ;
DFMA R10, R10, R10, R10 ;
DFMA R10, R8, R10, R8 ;
DFMA R8, -R16, R10, 1 ;
DFMA R8, R10, R8, R10 ;
DMUL R10, R8, 4 ;
DFMA R12, -R16, R10, 4 ;
DFMA R8, R8, R12, R10 ;
FFMA R10, RZ, R17, R9 ;
FSETP.GT.AND P0, PT, |R10|, 1.469367938527859385e-39, PT ;
@P0 BRA 0xad0 ;
IMAD.MOV.U32 R18, RZ, RZ, RZ ;
MOV R8, 0xab0 ;
IMAD.MOV.U32 R19, RZ, RZ, 0x40100000 ;
CALL.REL.NOINC 0x1910 ;
IMAD.MOV.U32 R8, RZ, RZ, R34 ;
IMAD.MOV.U32 R9, RZ, RZ, R35 ;
BSYNC B2 ;
IADD3 R16, P0, R28, 0x5, RZ ;
IMAD.MOV.U32 R10, RZ, RZ, 0x1 ;
BSSY B2, 0xc50 ;
DADD R24, R24, -R8 ;
IMAD.X R17, RZ, RZ, R27, P0 ;
I2F.F64.S64 R16, R16 ;
MUFU.RCP64H R11, R17 ;
DFMA R12, -R16, R10, 1 ;
DFMA R12, R12, R12, R12 ;
DFMA R12, R10, R12, R10 ;
DFMA R10, -R16, R12, 1 ;
DFMA R10, R12, R10, R12 ;
DMUL R34, R10, 4 ;
DFMA R12, -R16, R34, 4 ;
DFMA R34, R10, R12, R34 ;
FFMA R10, RZ, R17, R35 ;
FSETP.GT.AND P0, PT, |R10|, 1.469367938527859385e-39, PT ;
@P0 BRA 0xc40 ;
IMAD.MOV.U32 R18, RZ, RZ, RZ ;
MOV R8, 0xc40 ;
IMAD.MOV.U32 R19, RZ, RZ, 0x40100000 ;
CALL.REL.NOINC 0x1910 ;
BSYNC B2 ;
IADD3 R16, P0, R28, 0x7, RZ ;
IMAD.MOV.U32 R8, RZ, RZ, 0x1 ;
BSSY B2, 0xde0 ;
DADD R24, R24, R34 ;
IMAD.X R17, RZ, RZ, R27, P0 ;
I2F.F64.S64 R16, R16 ;
MUFU.RCP64H R9, R17 ;
DFMA R10, -R16, R8, 1 ;
DFMA R10, R10, R10, R10 ;
DFMA R10, R8, R10, R8 ;
DFMA R8, -R16, R10, 1 ;
DFMA R8, R10, R8, R10 ;
DMUL R10, R8, 4 ;
DFMA R12, -R16, R10, 4 ;
DFMA R8, R8, R12, R10 ;
FFMA R10, RZ, R17, R9 ;
FSETP.GT.AND P0, PT, |R10|, 1.469367938527859385e-39, PT ;
@P0 BRA 0xdd0 ;
IMAD.MOV.U32 R18, RZ, RZ, RZ ;
MOV R8, 0xdb0 ;
IMAD.MOV.U32 R19, RZ, RZ, 0x40100000 ;
CALL.REL.NOINC 0x1910 ;
IMAD.MOV.U32 R8, RZ, RZ, R34 ;
IMAD.MOV.U32 R9, RZ, RZ, R35 ;
BSYNC B2 ;
IADD3 R16, P0, R28, 0x9, RZ ;
IMAD.MOV.U32 R10, RZ, RZ, 0x1 ;
BSSY B2, 0xf50 ;
DADD R24, R24, -R8 ;
IMAD.X R17, RZ, RZ, R27, P0 ;
I2F.F64.S64 R16, R16 ;
MUFU.RCP64H R11, R17 ;
DFMA R12, -R16, R10, 1 ;
DFMA R12, R12, R12, R12 ;
DFMA R12, R10, R12, R10 ;
DFMA R10, -R16, R12, 1 ;
DFMA R10, R12, R10, R12 ;
DMUL R34, R10, 4 ;
DFMA R12, -R16, R34, 4 ;
DFMA R34, R10, R12, R34 ;
FFMA R10, RZ, R17, R35 ;
FSETP.GT.AND P0, PT, |R10|, 1.469367938527859385e-39, PT ;
@P0 BRA 0xf40 ;
IMAD.MOV.U32 R18, RZ, RZ, RZ ;
MOV R8, 0xf40 ;
IMAD.MOV.U32 R19, RZ, RZ, 0x40100000 ;
CALL.REL.NOINC 0x1910 ;
BSYNC B2 ;
IADD3 R16, P0, R28, 0xb, RZ ;
IMAD.MOV.U32 R8, RZ, RZ, 0x1 ;
BSSY B2, 0x10e0 ;
DADD R24, R24, R34 ;
IMAD.X R17, RZ, RZ, R27, P0 ;
I2F.F64.S64 R16, R16 ;
MUFU.RCP64H R9, R17 ;
DFMA R10, -R16, R8, 1 ;
DFMA R10, R10, R10, R10 ;
DFMA R10, R8, R10, R8 ;
DFMA R8, -R16, R10, 1 ;
DFMA R8, R10, R8, R10 ;
DMUL R10, R8, 4 ;
DFMA R12, -R16, R10, 4 ;
DFMA R8, R8, R12, R10 ;
FFMA R10, RZ, R17, R9 ;
FSETP.GT.AND P0, PT, |R10|, 1.469367938527859385e-39, PT ;
@P0 BRA 0x10d0 ;
IMAD.MOV.U32 R18, RZ, RZ, RZ ;
MOV R8, 0x10b0 ;
IMAD.MOV.U32 R19, RZ, RZ, 0x40100000 ;
CALL.REL.NOINC 0x1910 ;
IMAD.MOV.U32 R8, RZ, RZ, R34 ;
IMAD.MOV.U32 R9, RZ, RZ, R35 ;
BSYNC B2 ;
IADD3 R16, P0, R28, 0xd, RZ ;
IMAD.MOV.U32 R10, RZ, RZ, 0x1 ;
BSSY B2, 0x1250 ;
DADD R24, R24, -R8 ;
IMAD.X R17, RZ, RZ, R27, P0 ;
I2F.F64.S64 R16, R16 ;
MUFU.RCP64H R11, R17 ;
DFMA R12, -R16, R10, 1 ;
DFMA R12, R12, R12, R12 ;
DFMA R12, R10, R12, R10 ;
DFMA R10, -R16, R12, 1 ;
DFMA R10, R12, R10, R12 ;
DMUL R34, R10, 4 ;
DFMA R12, -R16, R34, 4 ;
DFMA R34, R10, R12, R34 ;
FFMA R10, RZ, R17, R35 ;
FSETP.GT.AND P0, PT, |R10|, 1.469367938527859385e-39, PT ;
@P0 BRA 0x1240 ;
IMAD.MOV.U32 R18, RZ, RZ, RZ ;
MOV R8, 0x1240 ;
IMAD.MOV.U32 R19, RZ, RZ, 0x40100000 ;
CALL.REL.NOINC 0x1910 ;
BSYNC B2 ;
IADD3 R16, P0, R28, 0xf, RZ ;
IMAD.MOV.U32 R8, RZ, RZ, 0x1 ;
BSSY B2, 0x13e0 ;
DADD R24, R24, R34 ;
IMAD.X R17, RZ, RZ, R27, P0 ;
I2F.F64.S64 R16, R16 ;
MUFU.RCP64H R9, R17 ;
DFMA R10, -R16, R8, 1 ;
DFMA R10, R10, R10, R10 ;
DFMA R10, R8, R10, R8 ;
DFMA R8, -R16, R10, 1 ;
DFMA R8, R10, R8, R10 ;
DMUL R10, R8, 4 ;
DFMA R12, -R16, R10, 4 ;
DFMA R8, R8, R12, R10 ;
FFMA R10, RZ, R17, R9 ;
FSETP.GT.AND P0, PT, |R10|, 1.469367938527859385e-39, PT ;
@P0 BRA 0x13d0 ;
IMAD.MOV.U32 R18, RZ, RZ, RZ ;
MOV R8, 0x13b0 ;
IMAD.MOV.U32 R19, RZ, RZ, 0x40100000 ;
CALL.REL.NOINC 0x1910 ;
IMAD.MOV.U32 R8, RZ, RZ, R34 ;
IMAD.MOV.U32 R9, RZ, RZ, R35 ;
BSYNC B2 ;
IADD3 R0, P0, R0, 0x8, RZ ;
DADD R24, R24, -R8 ;
IADD3 R28, P1, R28, 0x10, RZ ;
IMAD.X R3, RZ, RZ, R3, P0 ;
ISETP.GE.U32.AND P0, PT, R0, R5, PT ;
IMAD.X R27, RZ, RZ, R27, P1 ;
ISETP.GE.AND.EX P0, PT, R3, R2, PT, P0 ;
@P0 CALL.REL.NOINC 0x1470 ;
BRA 0x7f0 ;
BSYNC B1 ;
LEA R2, P1, R7, c[0x0][0x160], 0x3 ;
IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x170] ;
LEA.HI.X R3, R7, c[0x0][0x164], R4, 0x3, P1 ;
ISETP.GE.AND P0, PT, R0, 0x2, PT ;
STG.E.64 [R2.64], R24 ;
BAR.SYNC.DEFER_BLOCKING 0x0 ;
ISETP.NE.OR P0, PT, R7, RZ, !P0 ;
@P0 EXIT ;
IADD3 R18, R0.reuse, -0x1, RZ ;
UMOV UR6, 0x1 ;
IADD3 R0, P0, R0, -0x2, RZ ;
UMOV UR5, URZ ;
LOP3.LUT R18, R18, 0x3, RZ, 0xc0, !PT ;
IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x160] ;
ISETP.GE.U32.AND P1, PT, R0, 0x3, PT ;
IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x164] ;
IADD3.X R0, R6, -0x1, RZ, P0, !PT ;
ISETP.NE.U32.AND P0, PT, R18, RZ, PT ;
ISETP.GE.U32.AND.EX P1, PT, R0, RZ, PT, P1 ;
ISETP.NE.AND.EX P0, PT, RZ, RZ, PT, P0 ;
@!P1 BRA 0x17b0 ;
LDG.E.64 R4, [R2.64] ;
IADD3 R16, P1, R18, -c[0x0][0x170], RZ ;
UMOV UR6, 0x1 ;
UMOV UR5, URZ ;
IMAD.X R17, RZ, RZ, ~R6, P1 ;
UMOV UR12, 0x8 ;
UMOV UR4, URZ ;
ULDC.64 UR8, c[0x0][0x160] ;
UIADD3 UR7, UP0, UR12, UR8, URZ ;
UIADD3.X UR8, UR4, UR9, URZ, UP0, !UPT ;
IMAD.U32 R6, RZ, RZ, UR7 ;
IMAD.U32 R7, RZ, RZ, UR8 ;
LDG.E.64 R8, [R6.64] ;
LDG.E.64 R10, [R6.64+0x8] ;
LDG.E.64 R12, [R6.64+0x10] ;
LDG.E.64 R14, [R6.64+0x18] ;
UIADD3 UR6, UP0, UR6, 0x4, URZ ;
UIADD3.X UR5, URZ, UR5, URZ, UP0, !UPT ;
IADD3 R0, P2, R16, UR6, RZ ;
UIADD3 UR12, UP0, UR12, 0x20, URZ ;
ISETP.NE.U32.AND P1, PT, R0, RZ, PT ;
UIADD3.X UR4, URZ, UR4, URZ, UP0, !UPT ;
IADD3.X R0, R17, UR5, RZ, P2, !PT ;
ISETP.NE.AND.EX P1, PT, R0, RZ, PT, P1 ;
DADD R8, R8, R4 ;
DADD R8, R8, R10 ;
DADD R8, R8, R12 ;
DADD R4, R8, R14 ;
STG.E.64 [R2.64], R4 ;
@P1 BRA 0x1640 ;
@!P0 EXIT ;
LDG.E.64 R4, [R2.64] ;
IADD3 R0, P0, RZ, -R18, RZ ;
USHF.L.U64.HI UR7, UR6, 0x3, UR5 ;
USHF.L.U32 UR6, UR6, 0x3, URZ ;
IMAD.X R8, RZ, RZ, -0x1, P0 ;
ULDC.64 UR4, c[0x0][0x160] ;
UIADD3 UR4, UP0, UR6, UR4, URZ ;
UIADD3.X UR5, UR7, UR5, URZ, UP0, !UPT ;
IMAD.U32 R6, RZ, RZ, UR4 ;
IMAD.U32 R7, RZ, RZ, UR5 ;
LDG.E.64 R6, [R6.64] ;
IADD3 R0, P0, R0, 0x1, RZ ;
UIADD3 UR6, UP0, UR6, 0x8, URZ ;
IMAD.X R8, RZ, RZ, R8, P0 ;
ISETP.NE.U32.AND P0, PT, R0, RZ, PT ;
UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ;
ISETP.NE.AND.EX P0, PT, R8, RZ, PT, P0 ;
DADD R4, R6, R4 ;
STG.E.64 [R2.64], R4 ;
@P0 BRA 0x1810 ;
EXIT ;
FSETP.GEU.AND P1, PT, |R17|.reuse, 1.469367938527859385e-39, PT ;
IMAD.MOV.U32 R10, RZ, RZ, 0x1 ;
LOP3.LUT R14, R17.reuse, 0x800fffff, RZ, 0xc0, !PT ;
IMAD.MOV.U32 R20, RZ, RZ, R18 ;
LOP3.LUT R12, R17, 0x7ff00000, RZ, 0xc0, !PT ;
LOP3.LUT R15, R14, 0x3ff00000, RZ, 0xfc, !PT ;
IMAD.MOV.U32 R14, RZ, RZ, R16 ;
LOP3.LUT R9, R19, 0x7ff00000, RZ, 0xc0, !PT ;
ISETP.GE.U32.AND P2, PT, R9, R12, PT ;
@!P1 DMUL R14, R16, 8.98846567431157953865e+307 ;
MUFU.RCP64H R11, R15 ;
DFMA R22, R10, -R14, 1 ;
DFMA R22, R22, R22, R22 ;
DFMA R22, R10, R22, R10 ;
IMAD.MOV.U32 R10, RZ, RZ, 0x1ca00000 ;
IMAD.MOV.U32 R11, RZ, RZ, R9 ;
DFMA R34, R22.reuse, -R14, 1 ;
SEL R21, R10, 0x63400000, !P2 ;
FSETP.GEU.AND P2, PT, |R19|, 1.469367938527859385e-39, PT ;
LOP3.LUT R21, R21, 0x800fffff, R19, 0xf8, !PT ;
DFMA R34, R22, R34, R22 ;
@P2 BRA 0x1af0 ;
LOP3.LUT R22, R17, 0x7ff00000, RZ, 0xc0, !PT ;
ISETP.GE.U32.AND P2, PT, R9, R22, PT ;
IMAD.MOV.U32 R22, RZ, RZ, RZ ;
SEL R11, R10, 0x63400000, !P2 ;
LOP3.LUT R11, R11, 0x80000000, R19, 0xf8, !PT ;
LOP3.LUT R23, R11, 0x100000, RZ, 0xfc, !PT ;
DFMA R20, R20, 2, -R22 ;
LOP3.LUT R11, R21, 0x7ff00000, RZ, 0xc0, !PT ;
@!P1 LOP3.LUT R12, R15, 0x7ff00000, RZ, 0xc0, !PT ;
DMUL R36, R34, R20 ;
IADD3 R13, R11, -0x1, RZ ;
BSSY B0, 0x1ec0 ;
IADD3 R26, R12, -0x1, RZ ;
ISETP.GT.U32.AND P1, PT, R13, 0x7feffffe, PT ;
DFMA R22, R36, -R14, R20 ;
ISETP.GT.U32.OR P1, PT, R26, 0x7feffffe, P1 ;
DFMA R22, R34, R22, R36 ;
@P1 BRA 0x1d60 ;
LOP3.LUT R12, R17, 0x7ff00000, RZ, 0xc0, !PT ;
ISETP.GE.U32.AND P1, PT, R9.reuse, R12, PT ;
IMAD.IADD R11, R9, 0x1, -R12 ;
IMAD.MOV.U32 R12, RZ, RZ, RZ ;
SEL R10, R10, 0x63400000, !P1 ;
IMNMX R11, R11, -0x46a00000, !PT ;
IMNMX R11, R11, 0x46a00000, PT ;
IMAD.IADD R10, R11, 0x1, -R10 ;
IADD3 R13, R10, 0x7fe00000, RZ ;
DMUL R34, R22, R12 ;
FSETP.GTU.AND P1, PT, |R35|, 1.469367938527859385e-39, PT ;
@P1 BRA 0x1eb0 ;
DFMA R14, R22, -R14, R20 ;
IMAD.MOV.U32 R14, RZ, RZ, RZ ;
FSETP.NEU.AND P1, PT, R15.reuse, RZ, PT ;
LOP3.LUT R16, R15, 0x80000000, R17, 0x48, !PT ;
LOP3.LUT R15, R16, R13, RZ, 0xfc, !PT ;
@!P1 BRA 0x1eb0 ;
IMAD.MOV R13, RZ, RZ, -R10 ;
IADD3 R10, -R10, -0x43300000, RZ ;
IMAD.MOV.U32 R12, RZ, RZ, RZ ;
DFMA R12, R34, -R12, R22 ;
DMUL.RP R22, R22, R14 ;
FSETP.NEU.AND P1, PT, |R13|, R10, PT ;
FSEL R10, R22, R34, !P1 ;
LOP3.LUT R16, R23, R16, RZ, 0x3c, !PT ;
IMAD.MOV.U32 R34, RZ, RZ, R10 ;
FSEL R35, R16, R35, !P1 ;
BRA 0x1eb0 ;
DSETP.NAN.AND P1, PT, R18, R18, PT ;
@P1 BRA 0x1e90 ;
DSETP.NAN.AND P1, PT, R16, R16, PT ;
@P1 BRA 0x1e60 ;
ISETP.NE.AND P1, PT, R11, R12, PT ;
IMAD.MOV.U32 R34, RZ, RZ, 0x0 ;
IMAD.MOV.U32 R35, RZ, RZ, -0x80000 ;
@!P1 BRA 0x1eb0 ;
ISETP.NE.AND P1, PT, R11, 0x7ff00000, PT ;
LOP3.LUT R35, R19, 0x80000000, R17, 0x48, !PT ;
ISETP.EQ.OR P1, PT, R12, RZ, !P1 ;
@P1 LOP3.LUT R9, R35, 0x7ff00000, RZ, 0xfc, !PT ;
@!P1 IMAD.MOV.U32 R34, RZ, RZ, RZ ;
@P1 IMAD.MOV.U32 R34, RZ, RZ, RZ ;
@P1 IMAD.MOV.U32 R35, RZ, RZ, R9 ;
BRA 0x1eb0 ;
LOP3.LUT R35, R17, 0x80000, RZ, 0xfc, !PT ;
IMAD.MOV.U32 R34, RZ, RZ, R16 ;
BRA 0x1eb0 ;
LOP3.LUT R35, R19, 0x80000, RZ, 0xfc, !PT ;
IMAD.MOV.U32 R34, RZ, RZ, R18 ;
BSYNC B0 ;
IMAD.MOV.U32 R9, RZ, RZ, 0x0 ;
RET.REL.NODEC R8 0x0 ;
IADD3 R2, P1, RZ, -c[0x0][0x170], RZ ;
ISETP.GE.AND P0, PT, R6, RZ, PT ;
ISETP.LE.AND P3, PT, RZ, c[0x0][0x16c], PT ;
IMAD.X R3, RZ, RZ, ~R6, P1 ;
SEL R2, R2, c[0x0][0x170], !P0 ;
SEL R3, R3, R6, !P0 ;
I2F.U64.RP R10, R2 ;
MUFU.RCP R10, R10 ;
IADD3 R4, R10, 0x1ffffffe, RZ ;
F2I.U64.TRUNC R4, R4 ;
IMAD.WIDE.U32 R8, R4, R2, RZ ;
IMAD R9, R4, R3, R9 ;
IADD3 R11, P0, RZ, -R8, RZ ;
IMAD R9, R5, R2, R9 ;
IMAD.HI.U32 R8, R4, R11, RZ ;
IMAD.X R13, RZ, RZ, ~R9, P0 ;
IMAD.MOV.U32 R9, RZ, RZ, R4 ;
IMAD R15, R5, R13.reuse, RZ ;
IMAD.WIDE.U32 R8, P0, R4, R13, R8 ;
IMAD.HI.U32 R13, R5, R13, RZ ;
IMAD.HI.U32 R8, P1, R5, R11, R8 ;
IADD3 R9, P2, R15, R8, RZ ;
IMAD.X R8, R13, 0x1, R5, P0 ;
IADD3 R15, P4, RZ, -c[0x0][0x168], RZ ;
IMAD.WIDE.U32 R4, R9, R2, RZ ;
IADD3.X R11, RZ, RZ, R8, P2, P1 ;
SEL R15, R15, c[0x0][0x168], !P3 ;
IMAD R5, R9, R3, R5 ;
IADD3 R13, P0, RZ, -R4, RZ ;
IMAD.X R10, RZ, RZ, ~c[0x0][0x16c], P4 ;
IMAD R5, R11, R2, R5 ;
IMAD.HI.U32 R8, R9, R13, RZ ;
SEL R10, R10, c[0x0][0x16c], !P3 ;
IMAD.X R4, RZ, RZ, ~R5, P0 ;
IMAD.MOV.U32 R5, RZ, RZ, RZ ;
IMAD.WIDE.U32 R8, P0, R9, R4, R8 ;
IMAD.HI.U32 R9, P1, R11, R13, R8 ;
IMAD R8, R11.reuse, R4.reuse, RZ ;
IMAD.HI.U32 R4, R11, R4, RZ ;
IADD3 R9, P2, R8, R9, RZ ;
IMAD.X R11, R4, 0x1, R11, P0 ;
IMAD.HI.U32 R4, R9, R15, RZ ;
IADD3.X R11, RZ, RZ, R11, P2, P1 ;
IMAD.WIDE.U32 R4, R9, R10, R4 ;
IMAD R9, R11.reuse, R10, RZ ;
IMAD.HI.U32 R4, P0, R11, R15, R4 ;
IMAD.HI.U32 R8, R11, R10, RZ ;
IADD3 R9, P1, R9, R4, RZ ;
IMAD.X R8, RZ, RZ, R8, P0 ;
IMAD.WIDE.U32 R4, R9, R2, RZ ;
IMAD.X R11, RZ, RZ, R8, P1 ;
IADD3 R15, P1, -R4, R15, RZ ;
IMAD R5, R9.reuse, R3, R5 ;
IADD3 R4, P2, R9, 0x1, RZ ;
ISETP.GE.U32.AND P0, PT, R15, R2.reuse, PT ;
IMAD R5, R11, R2.reuse, R5 ;
IMAD.X R8, RZ, RZ, R11, P2 ;
IMAD.X R17, R10, 0x1, ~R5, P1 ;
IADD3 R5, P1, R15, -R2, RZ ;
ISETP.GE.U32.AND.EX P0, PT, R17.reuse, R3, PT, P0 ;
IMAD.X R13, R17, 0x1, ~R3, P1 ;
SEL R5, R5, R15, P0 ;
SEL R9, R4, R9, P0 ;
SEL R13, R13, R17, P0 ;
ISETP.GE.U32.AND P1, PT, R5, R2, PT ;
SEL R2, R8, R11, P0 ;
IADD3 R10, P2, R9, 0x1, RZ ;
ISETP.GE.U32.AND.EX P0, PT, R13, R3, PT, P1 ;
LOP3.LUT R4, R6, c[0x0][0x16c], RZ, 0x3c, !PT ;
IMAD.X R11, RZ, RZ, R2, P2 ;
SEL R10, R10, R9, P0 ;
ISETP.GE.AND P1, PT, R4, RZ, PT ;
SEL R11, R11, R2, P0 ;
IADD3 R3, P2, RZ, -R10, RZ ;
ISETP.NE.U32.AND P0, PT, RZ, c[0x0][0x170], PT ;
SEL R10, R3, R10, !P1 ;
IMAD.X R2, RZ, RZ, ~R11, P2 ;
ISETP.NE.AND.EX P0, PT, R6, RZ, PT, P0 ;
IMAD.MOV.U32 R3, RZ, RZ, 0x0 ;
SEL R11, R2, R11, !P1 ;
IMAD.MOV.U32 R2, RZ, RZ, R0 ;
SEL R10, R10, 0xffffffff, P0 ;
SEL R11, R11, 0xffffffff, P0 ;
RET.REL.NODEC R2 0x0 ;
BRA 0x2420;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
```
|
```amdasm
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z11calculatePiPdli ; -- Begin function _Z11calculatePiPdli
.globl _Z11calculatePiPdli
.p2align 8
.type _Z11calculatePiPdli,@function
_Z11calculatePiPdli: ; @_Z11calculatePiPdli
; %bb.0:
s_clause 0x1
s_load_b32 s10, s[0:1], 0x10
s_load_b32 s2, s[0:1], 0x24
s_waitcnt lgkmcnt(0)
s_ashr_i32 s11, s10, 31
s_and_b32 s12, s2, 0xffff
s_add_u32 s4, s10, s11
s_mov_b32 s2, s11
s_mov_b32 s3, s11
s_addc_u32 s5, s11, s11
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_xor_b64 s[8:9], s[4:5], s[2:3]
v_cvt_f32_u32_e32 v1, s8
v_cvt_f32_u32_e32 v2, s9
s_sub_u32 s13, 0, s8
s_subb_u32 s14, 0, s9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmamk_f32 v1, v2, 0x4f800000, v1
v_rcp_f32_e32 v1, v1
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v1, 0x5f7ffffc, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v2, 0x2f800000, v1
v_trunc_f32_e32 v2, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_fmamk_f32 v1, v2, 0xcf800000, v1
v_cvt_u32_f32_e32 v2, v2
v_cvt_u32_f32_e32 v1, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_readfirstlane_b32 s4, v2
v_readfirstlane_b32 s5, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
s_mul_i32 s6, s13, s4
s_mul_hi_u32 s16, s13, s5
s_mul_i32 s7, s14, s5
s_add_i32 s6, s16, s6
s_mul_i32 s17, s13, s5
s_add_i32 s6, s6, s7
s_mul_hi_u32 s16, s5, s17
s_mul_hi_u32 s18, s4, s17
s_mul_i32 s7, s4, s17
s_mul_hi_u32 s17, s5, s6
s_mul_i32 s5, s5, s6
s_mul_hi_u32 s19, s4, s6
s_add_u32 s5, s16, s5
s_addc_u32 s16, 0, s17
s_add_u32 s5, s5, s7
s_mul_i32 s6, s4, s6
s_addc_u32 s5, s16, s18
s_addc_u32 s7, s19, 0
s_add_u32 s5, s5, s6
s_addc_u32 s6, 0, s7
v_add_co_u32 v1, s5, v1, s5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
s_cmp_lg_u32 s5, 0
s_addc_u32 s17, s4, s6
v_readfirstlane_b32 s16, v1
s_load_b128 s[4:7], s[0:1], 0x0
s_mul_i32 s0, s13, s17
s_delay_alu instid0(VALU_DEP_1)
s_mul_hi_u32 s1, s13, s16
s_mul_i32 s14, s14, s16
s_add_i32 s0, s1, s0
s_mul_i32 s13, s13, s16
s_add_i32 s0, s0, s14
s_mul_hi_u32 s1, s17, s13
s_mul_i32 s18, s17, s13
s_mul_hi_u32 s13, s16, s13
s_mul_hi_u32 s19, s16, s0
s_mul_i32 s16, s16, s0
s_mul_hi_u32 s14, s17, s0
s_add_u32 s13, s13, s16
s_addc_u32 s16, 0, s19
s_add_u32 s13, s13, s18
s_mul_i32 s0, s17, s0
s_addc_u32 s1, s16, s1
s_addc_u32 s13, s14, 0
s_add_u32 s0, s1, s0
s_addc_u32 s1, 0, s13
v_add_co_u32 v1, s0, v1, s0
s_delay_alu instid0(VALU_DEP_1)
s_cmp_lg_u32 s0, 0
s_addc_u32 s13, s17, s1
s_waitcnt lgkmcnt(0)
s_ashr_i32 s0, s7, 31
v_readfirstlane_b32 s14, v1
s_add_u32 s6, s6, s0
s_mov_b32 s1, s0
s_addc_u32 s7, s7, s0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_xor_b64 s[6:7], s[6:7], s[0:1]
s_mul_i32 s17, s6, s13
s_mul_hi_u32 s18, s6, s14
s_mul_hi_u32 s16, s6, s13
s_mul_hi_u32 s20, s7, s14
s_mul_i32 s14, s7, s14
s_add_u32 s17, s18, s17
s_addc_u32 s16, 0, s16
s_mul_hi_u32 s19, s7, s13
s_add_u32 s14, s17, s14
s_mul_i32 s13, s7, s13
s_addc_u32 s14, s16, s20
s_addc_u32 s16, s19, 0
s_add_u32 s13, s14, s13
s_addc_u32 s14, 0, s16
s_mul_i32 s19, s8, s13
s_mul_hi_u32 s16, s8, s13
s_mul_i32 s18, s8, s14
v_sub_co_u32 v1, s6, s6, s19
s_mul_i32 s17, s9, s13
s_add_i32 s16, s16, s18
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_add_i32 s16, s16, s17
v_sub_co_u32 v2, s18, v1, s8
s_sub_i32 s17, s7, s16
s_cmp_lg_u32 s6, 0
s_subb_u32 s17, s17, s9
s_cmp_lg_u32 s18, 0
v_readfirstlane_b32 s18, v2
s_subb_u32 s17, s17, 0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
s_cmp_ge_u32 s17, s9
s_cselect_b32 s19, -1, 0
s_cmp_ge_u32 s18, s8
s_cselect_b32 s18, -1, 0
s_cmp_eq_u32 s17, s9
s_cselect_b32 s17, s18, s19
s_add_u32 s18, s13, 1
s_addc_u32 s19, s14, 0
s_add_u32 s20, s13, 2
s_addc_u32 s21, s14, 0
s_cmp_lg_u32 s17, 0
s_cselect_b32 s17, s20, s18
s_cselect_b32 s18, s21, s19
s_cmp_lg_u32 s6, 0
v_readfirstlane_b32 s6, v1
s_subb_u32 s7, s7, s16
v_mad_u64_u32 v[1:2], null, s15, s12, v[0:1]
s_cmp_ge_u32 s7, s9
s_cselect_b32 s16, -1, 0
s_cmp_ge_u32 s6, s8
s_cselect_b32 s6, -1, 0
s_cmp_eq_u32 s7, s9
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_ashrrev_i32_e32 v2, 31, v1
s_cselect_b32 s6, s6, s16
s_cmp_lg_u32 s6, 0
s_cselect_b32 s7, s18, s14
s_cselect_b32 s6, s17, s13
s_xor_b64 s[0:1], s[0:1], s[2:3]
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_xor_b64 s[2:3], s[6:7], s[0:1]
s_sub_u32 s0, s2, s0
s_subb_u32 s1, s3, s1
v_mul_lo_u32 v0, s0, v2
v_mad_u64_u32 v[5:6], null, s0, v1, 0
v_mul_lo_u32 v3, s1, v1
s_add_u32 s0, s0, -1
s_addc_u32 s1, s1, -1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v7, vcc_lo, s0, v5
v_add3_u32 v6, v6, v0, v3
v_mov_b32_e32 v3, 0
v_mov_b32_e32 v4, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[9:10], 1, v[5:6]
v_add_co_ci_u32_e32 v8, vcc_lo, s1, v6, vcc_lo
s_mov_b32 s1, 0
v_add_co_u32 v0, vcc_lo, v9, 3
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v9, vcc_lo, 0, v10, vcc_lo
.LBB0_1: ; =>This Inner Loop Header: Depth=1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v14, vcc_lo, v0, -2
v_add_co_ci_u32_e32 v10, vcc_lo, -1, v9, vcc_lo
v_cvt_f64_i32_e32 v[12:13], v9
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_cvt_f64_u32_e32 v[14:15], v14
v_cvt_f64_u32_e32 v[16:17], v0
v_cvt_f64_i32_e32 v[10:11], v10
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ldexp_f64 v[12:13], v[12:13], 32
v_ldexp_f64 v[10:11], v[10:11], 32
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f64 v[12:13], v[12:13], v[16:17]
v_add_f64 v[10:11], v[10:11], v[14:15]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_div_scale_f64 v[16:17], null, v[12:13], v[12:13], 4.0
v_div_scale_f64 v[14:15], null, v[10:11], v[10:11], 4.0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_rcp_f64_e32 v[20:21], v[16:17]
v_rcp_f64_e32 v[18:19], v[14:15]
s_waitcnt_depctr 0xfff
v_fma_f64 v[24:25], -v[16:17], v[20:21], 1.0
v_fma_f64 v[22:23], -v[14:15], v[18:19], 1.0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_fma_f64 v[20:21], v[20:21], v[24:25], v[20:21]
v_div_scale_f64 v[24:25], vcc_lo, 4.0, v[10:11], 4.0
v_fma_f64 v[18:19], v[18:19], v[22:23], v[18:19]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f64 v[26:27], -v[16:17], v[20:21], 1.0
v_fma_f64 v[22:23], -v[14:15], v[18:19], 1.0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f64 v[20:21], v[20:21], v[26:27], v[20:21]
v_fma_f64 v[18:19], v[18:19], v[22:23], v[18:19]
v_div_scale_f64 v[22:23], s0, 4.0, v[12:13], 4.0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_f64 v[26:27], v[24:25], v[18:19]
v_mul_f64 v[28:29], v[22:23], v[20:21]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f64 v[14:15], -v[14:15], v[26:27], v[24:25]
v_fma_f64 v[16:17], -v[16:17], v[28:29], v[22:23]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_div_fmas_f64 v[14:15], v[14:15], v[18:19], v[26:27]
s_mov_b32 vcc_lo, s0
v_add_co_u32 v0, s0, v0, 4
v_div_fmas_f64 v[16:17], v[16:17], v[20:21], v[28:29]
v_add_co_u32 v5, vcc_lo, v5, 2
v_add_co_ci_u32_e32 v6, vcc_lo, 0, v6, vcc_lo
v_add_co_ci_u32_e64 v9, s0, 0, v9, s0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_2)
v_cmp_ge_i64_e32 vcc_lo, v[5:6], v[7:8]
s_or_b32 s1, vcc_lo, s1
v_div_fixup_f64 v[10:11], v[14:15], v[10:11], 4.0
v_div_fixup_f64 v[12:13], v[16:17], v[12:13], 4.0
v_add_f64 v[3:4], v[3:4], v[10:11]
s_delay_alu instid0(VALU_DEP_1)
v_add_f64 v[3:4], v[3:4], -v[12:13]
s_and_not1_b32 exec_lo, exec_lo, s1
s_cbranch_execnz .LBB0_1
; %bb.2:
s_or_b32 exec_lo, exec_lo, s1
v_lshlrev_b64 v[5:6], 3, v[1:2]
v_cmp_eq_u32_e32 vcc_lo, 0, v1
s_cmp_gt_i32 s10, 1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v0, s0, s4, v5
v_add_co_ci_u32_e64 v1, s0, s5, v6, s0
s_cselect_b32 s0, -1, 0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 s0, vcc_lo, s0
global_store_b64 v[0:1], v[3:4], off
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_6
; %bb.3: ; %.lr.ph
v_mov_b32_e32 v2, 0
s_add_u32 s0, s10, -1
s_addc_u32 s1, s11, -1
s_add_u32 s2, s4, 8
s_addc_u32 s3, s5, 0
global_load_b64 v[0:1], v2, s[4:5]
.LBB0_4: ; =>This Inner Loop Header: Depth=1
global_load_b64 v[3:4], v2, s[2:3]
s_add_u32 s0, s0, -1
s_addc_u32 s1, s1, -1
s_add_u32 s2, s2, 8
s_addc_u32 s3, s3, 0
s_cmp_lg_u64 s[0:1], 0
s_waitcnt vmcnt(0)
v_add_f64 v[0:1], v[0:1], v[3:4]
s_cbranch_scc1 .LBB0_4
; %bb.5: ; %..loopexit_crit_edge
v_mov_b32_e32 v2, 0
global_store_b64 v2, v[0:1], s[4:5]
.LBB0_6: ; %.loopexit
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11calculatePiPdli
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 30
.amdhsa_next_free_sgpr 22
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z11calculatePiPdli, .Lfunc_end0-_Z11calculatePiPdli
; -- End function
.section .AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1296
; NumSgprs: 24
; NumVgprs: 30
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 3
; NumSGPRsForWavesPerEU: 24
; NumVGPRsForWavesPerEU: 30
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object ; @__hip_cuid_
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0 ; 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 8
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11calculatePiPdli
.private_segment_fixed_size: 0
.sgpr_count: 24
.sgpr_spill_count: 0
.symbol: _Z11calculatePiPdli.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 30
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
```
| 11,350 | 7,345 |
449 |
Convert the following CUDA host assembly code to AMD host assembly:
```cudaasm
.file "tmpxft_00188938_00000000-6_Cuda_pi.cudafe1.cpp"
.text
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z33__device_stub__Z11calculatePiPdliPdli
.type _Z33__device_stub__Z11calculatePiPdliPdli, @function
_Z33__device_stub__Z11calculatePiPdliPdli:
.LFB2082:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z11calculatePiPdli(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z33__device_stub__Z11calculatePiPdliPdli, .-_Z33__device_stub__Z11calculatePiPdliPdli
.globl _Z11calculatePiPdli
.type _Z11calculatePiPdli, @function
_Z11calculatePiPdli:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z11calculatePiPdliPdli
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z11calculatePiPdli, .-_Z11calculatePiPdli
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "Failed to allocate host vectors!\n"
.align 8
.LC2:
.string "Failed to allocate device vector C (error code %s)!\n"
.align 8
.LC3:
.string "Failed to copy vector C from device to host (error code %s)!\n"
.align 8
.LC4:
.string "CUDA kernel launch with %d blocks of %d threads Total: %i "
.align 8
.LC5:
.string "Failed to launch vectorAdd kernel (error code %s)!\n"
.align 8
.LC6:
.string "Failed to free device vector C (error code %s)!\n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC7:
.string "Calculated pi: %.12f"
.section .rodata.str1.8
.align 8
.LC8:
.string "Failed to deinitialize the device! error=%s\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $48, %rsp
.cfi_def_cfa_offset 64
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movl $65536, %edi
call malloc@PLT
testq %rax, %rax
je .L24
movq %rax, %rbx
leaq 65536(%rax), %rdx
.L13:
movq $0x000000000, (%rax)
addq $8, %rax
cmpq %rdx, %rax
jne .L13
leaq 8(%rsp), %rdi
movl $65536, %esi
call cudaMalloc@PLT
testl %eax, %eax
jne .L25
movl $1, %ecx
movl $65536, %edx
movq %rbx, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L26
movl $8192, %r8d
movl $16, %ecx
movl $512, %edx
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $16, 28(%rsp)
movl $1, 32(%rsp)
movl $512, 16(%rsp)
movl $1, 20(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L27
.L16:
call cudaGetLastError@PLT
testl %eax, %eax
jne .L28
movl $2, %ecx
movl $65536, %edx
movq 8(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L29
movq 8(%rsp), %rdi
call cudaFree@PLT
testl %eax, %eax
jne .L30
movsd (%rbx), %xmm0
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq %rbx, %rdi
call free@PLT
call cudaDeviceReset@PLT
testl %eax, %eax
jne .L31
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L32
movl $0, %eax
addq $48, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L24:
.cfi_restore_state
leaq .LC0(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L25:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L26:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC3(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L27:
movl $8192, %edx
movabsq $16000000000, %rsi
movq 8(%rsp), %rdi
call _Z33__device_stub__Z11calculatePiPdliPdli
jmp .L16
.L28:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC5(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L29:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC3(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L30:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC6(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L31:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC8(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L32:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC9:
.string "_Z11calculatePiPdli"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC9(%rip), %rdx
movq %rdx, %rcx
leaq _Z11calculatePiPdli(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
```
|
```amdasm
.text
.file "Cuda_pi.hip"
.globl _Z26__device_stub__calculatePiPdli # -- Begin function _Z26__device_stub__calculatePiPdli
.type _Z26__device_stub__calculatePiPdli,@function
_Z26__device_stub__calculatePiPdli: # @_Z26__device_stub__calculatePiPdli
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $112, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 40(%rsp), %rax
movq %rdi, (%rax)
leaq 32(%rsp), %rcx
movq %rsi, (%rcx)
leaq 12(%rsp), %rsi
movl %edx, (%rsi)
leaq 80(%rsp), %rbx
movq %rax, (%rbx)
movq %rcx, 8(%rbx)
movq %rsi, 16(%rbx)
leaq 64(%rsp), %r14
leaq 48(%rsp), %r15
leaq 24(%rsp), %r12
leaq 16(%rsp), %r13
movq %r14, %rdi
movq %r15, %rsi
movq %r12, %rdx
movq %r13, %rcx
callq __hipPopCallConfiguration
movq (%r14), %rsi
movl 8(%r14), %edx
movq (%r15), %rcx
movl 8(%r15), %r8d
movl $_Z11calculatePiPdli, %edi
movq %rbx, %r9
pushq (%r13)
.cfi_adjust_cfa_offset 8
pushq (%r12)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $128, %rsp
.cfi_adjust_cfa_offset -128
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z26__device_stub__calculatePiPdli, .Lfunc_end0-_Z26__device_stub__calculatePiPdli
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $16, %rsp
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -16
movl $1, %edi
movl $65536, %esi # imm = 0x10000
callq calloc@PLT
testq %rax, %rax
je .LBB1_11
# %bb.1: # %.preheader.preheader
movq %rax, %rbx
leaq 8(%rsp), %rdi
movl $65536, %esi # imm = 0x10000
callq hipMalloc
testl %eax, %eax
jne .LBB1_12
# %bb.2:
movq 8(%rsp), %rdi
movl $65536, %edx # imm = 0x10000
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB1_10
# %bb.3:
movl $.L.str.3, %edi
movl $512, %esi # imm = 0x200
movl $16, %edx
movl $8192, %ecx # imm = 0x2000
xorl %eax, %eax
callq printf
movabsq $4294967312, %rdx # imm = 0x100000010
leaq 496(%rdx), %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_5
# %bb.4:
movq 8(%rsp), %rdi
movabsq $16000000000, %rsi # imm = 0x3B9ACA000
movl $8192, %edx # imm = 0x2000
callq _Z26__device_stub__calculatePiPdli
.LBB1_5:
callq hipGetLastError
testl %eax, %eax
jne .LBB1_13
# %bb.6:
movq 8(%rsp), %rsi
movl $65536, %edx # imm = 0x10000
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB1_10
# %bb.7:
movq 8(%rsp), %rdi
callq hipFree
testl %eax, %eax
jne .LBB1_14
# %bb.8:
movsd (%rbx), %xmm0 # xmm0 = mem[0],zero
movl $.L.str.6, %edi
movb $1, %al
callq printf
movq %rbx, %rdi
callq free
callq hipDeviceReset
testl %eax, %eax
jne .LBB1_15
# %bb.9:
xorl %eax, %eax
addq $16, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.LBB1_10:
.cfi_def_cfa_offset 32
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.2, %esi
jmp .LBB1_16
.LBB1_11:
movq stderr(%rip), %rcx
movl $.L.str, %edi
movl $33, %esi
movl $1, %edx
callq fwrite@PLT
jmp .LBB1_17
.LBB1_12:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.1, %esi
jmp .LBB1_16
.LBB1_13:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.4, %esi
jmp .LBB1_16
.LBB1_14:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.5, %esi
jmp .LBB1_16
.LBB1_15:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.7, %esi
.LBB1_16:
movq %rbx, %rdi
movq %rax, %rdx
xorl %eax, %eax
callq fprintf
.LBB1_17:
movl $1, %edi
callq exit
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, %rdi
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11calculatePiPdli, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z11calculatePiPdli,@object # @_Z11calculatePiPdli
.section .rodata,"a",@progbits
.globl _Z11calculatePiPdli
.p2align 3, 0x0
_Z11calculatePiPdli:
.quad _Z26__device_stub__calculatePiPdli
.size _Z11calculatePiPdli, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Failed to allocate host vectors!\n"
.size .L.str, 34
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Failed to allocate device vector C (error code %s)!\n"
.size .L.str.1, 53
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Failed to copy vector C from device to host (error code %s)!\n"
.size .L.str.2, 62
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "CUDA kernel launch with %d blocks of %d threads Total: %i "
.size .L.str.3, 65
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Failed to launch vectorAdd kernel (error code %s)!\n"
.size .L.str.4, 52
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "Failed to free device vector C (error code %s)!\n"
.size .L.str.5, 49
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "Calculated pi: %.12f"
.size .L.str.6, 21
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "Failed to deinitialize the device! error=%s\n"
.size .L.str.7, 45
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z11calculatePiPdli"
.size .L__unnamed_1, 20
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z26__device_stub__calculatePiPdli
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z11calculatePiPdli
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
```
| 3,733 | 3,797 |
450 |
Convert the following CUDA device assembly code to AMD device assembly:
```cudaasm
code for sm_80
Function : _Z26fast_variance_delta_kernelPfS_S_S_iiiS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
MOV R1, c[0x0][0x28] ;
S2R R8, SR_TID.X ;
HFMA2.MMA R2, -RZ, RZ, 0, 5.9604644775390625e-08 ;
ULDC.64 UR6, c[0x0][0x118] ;
S2R R0, SR_CTAID.X ;
ISETP.LE.AND P0, PT, R2, c[0x0][0x188], PT ;
ISETP.GT.OR P0, PT, R2, c[0x0][0x180], !P0 ;
STS [R8.X4], RZ ;
@P0 BRA 0x770 ;
MOV R10, 0x1 ;
MOV R5, 0x4 ;
IADD3 R10, -R10, c[0x0][0x188], RZ ;
MOV R13, RZ ;
IMAD.WIDE R4, R0, R5, c[0x0][0x170] ;
LEA.HI R12, R10, 0x1, RZ, 0x17 ;
MOV R9, RZ ;
LOP3.LUT R11, R12, 0x3, RZ, 0xc0, !PT ;
IADD3 R12, R12, -R11, RZ ;
ISETP.GE.U32.AND P2, PT, R10, 0x600, PT ;
IMAD R3, R9.reuse, c[0x0][0x184], R0 ;
IADD3 R9, R9, 0x1, RZ ;
UMOV UR4, URZ ;
ISETP.NE.AND P0, PT, R11, RZ, PT ;
IMAD R14, R3, c[0x0][0x188], R8 ;
ISETP.GE.AND P1, PT, R9, c[0x0][0x180], PT ;
@!P2 BRA 0x480 ;
MOV R15, R12 ;
UMOV UR4, URZ ;
IADD3 R16, R8, UR4, RZ ;
HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ;
IADD3 R2, R14, UR4, RZ ;
ISETP.GE.AND P3, PT, R16.reuse, c[0x0][0x188], PT ;
IADD3 R6, R16.reuse, 0x200, RZ ;
IADD3 R17, R16, 0x400, RZ ;
ISETP.GE.AND P4, PT, R6, c[0x0][0x188], PT ;
IMAD.WIDE R6, R2, R3, c[0x0][0x160] ;
ISETP.GE.AND P5, PT, R17, c[0x0][0x188], PT ;
IADD3 R16, R16, 0x600, RZ ;
IMAD.WIDE R2, R2, R3, c[0x0][0x168] ;
@!P3 LDG.E R27, [R4.64] ;
@!P3 LDG.E R28, [R6.64] ;
ISETP.GE.AND P2, PT, R16, c[0x0][0x188], PT ;
@!P3 LDG.E R24, [R2.64] ;
@!P4 LDG.E R23, [R4.64] ;
@!P4 LDG.E R18, [R6.64+0x800] ;
@!P4 LDG.E R19, [R2.64+0x800] ;
@!P5 LDG.E R21, [R4.64] ;
@!P5 LDG.E R16, [R6.64+0x1000] ;
@!P5 LDG.E R17, [R2.64+0x1000] ;
@!P2 LDG.E R25, [R6.64+0x1800] ;
@!P2 LDG.E R20, [R4.64] ;
@!P2 LDG.E R22, [R2.64+0x1800] ;
MOV R26, RZ ;
UIADD3 UR4, UR4, 0x800, URZ ;
IADD3 R15, R15, -0x4, RZ ;
@!P3 FADD R27, -R27, R28 ;
@!P3 FMUL R26, R24, R27 ;
HFMA2.MMA R24, -RZ, RZ, 0, 0 ;
ISETP.NE.AND P3, PT, R15, RZ, PT ;
FADD R13, R26, R13 ;
@!P4 FADD R18, -R23, R18 ;
@!P4 FMUL R24, R18, R19 ;
MOV R18, RZ ;
FADD R7, R13, R24 ;
HFMA2.MMA R13, -RZ, RZ, 0, 0 ;
@!P5 FADD R16, -R21, R16 ;
@!P5 FMUL R18, R16, R17 ;
FADD R18, R7, R18 ;
@!P2 FADD R25, -R20, R25 ;
@!P2 FMUL R13, R25, R22 ;
FADD R13, R18, R13 ;
@P3 BRA 0x1c0 ;
@!P0 BRA 0x750 ;
IADD3 R16, R8, UR4, RZ ;
BSSY B0, 0x590 ;
IADD3 R6, R14, UR4, RZ ;
HFMA2.MMA R14, -RZ, RZ, 0, 0 ;
ISETP.GE.AND P0, PT, R16, c[0x0][0x188], PT ;
MOV R7, 0x4 ;
ISETP.NE.AND P2, PT, R11, 0x1, PT ;
IMAD.WIDE R2, R6, R7, c[0x0][0x168] ;
IMAD.WIDE R6, R6, R7, c[0x0][0x160] ;
@P0 BRA 0x580 ;
LDG.E R18, [R4.64] ;
LDG.E R15, [R6.64] ;
LDG.E R14, [R2.64] ;
FADD R15, -R18, R15 ;
FMUL R14, R14, R15 ;
BSYNC B0 ;
FADD R13, R13, R14 ;
@!P2 BRA 0x750 ;
IADD3 R14, R16, 0x200, RZ ;
BSSY B0, 0x670 ;
ISETP.NE.AND P2, PT, R11, 0x2, PT ;
ISETP.GE.AND P0, PT, R14, c[0x0][0x188], PT ;
MOV R14, RZ ;
@P0 BRA 0x660 ;
LDG.E R17, [R4.64] ;
LDG.E R14, [R6.64+0x800] ;
LDG.E R15, [R2.64+0x800] ;
FADD R14, -R17, R14 ;
FMUL R14, R14, R15 ;
BSYNC B0 ;
FADD R13, R13, R14 ;
@!P2 BRA 0x750 ;
IADD3 R14, R16, 0x400, RZ ;
BSSY B0, 0x740 ;
ISETP.GE.AND P0, PT, R14, c[0x0][0x188], PT ;
HFMA2.MMA R14, -RZ, RZ, 0, 0 ;
@P0 BRA 0x730 ;
LDG.E R6, [R6.64+0x1000] ;
LDG.E R15, [R4.64] ;
LDG.E R3, [R2.64+0x1000] ;
FADD R14, -R15, R6 ;
FMUL R14, R14, R3 ;
BSYNC B0 ;
FADD R13, R13, R14 ;
@!P1 BRA 0x120 ;
STS [R8.X4], R13 ;
BAR.SYNC.DEFER_BLOCKING 0x0 ;
ISETP.NE.AND P0, PT, R8, RZ, PT ;
@P0 EXIT ;
LDS.128 R4, [RZ] ;
MOV R3, 0x4 ;
LDS.128 R8, [0x10] ;
IMAD.WIDE R2, R0, R3, c[0x0][0x190] ;
LDS.128 R16, [0x20] ;
LDS.128 R12, [0x30] ;
STG.E [R2.64], RZ ;
FADD R4, RZ, R4 ;
FADD R5, R4, R5 ;
FADD R6, R5, R6 ;
FADD R7, R6, R7 ;
FADD R8, R7, R8 ;
LDS.128 R4, [0x40] ;
FADD R9, R8, R9 ;
FADD R10, R9, R10 ;
FADD R11, R10, R11 ;
FADD R16, R11, R16 ;
LDS.128 R8, [0x50] ;
FADD R17, R16, R17 ;
FADD R18, R17, R18 ;
FADD R19, R18, R19 ;
FADD R12, R19, R12 ;
LDS.128 R16, [0x60] ;
FADD R13, R12, R13 ;
FADD R14, R13, R14 ;
FADD R15, R14, R15 ;
FADD R4, R15, R4 ;
LDS.128 R12, [0x70] ;
FADD R5, R4, R5 ;
FADD R6, R5, R6 ;
FADD R7, R6, R7 ;
FADD R8, R7, R8 ;
LDS.128 R4, [0x80] ;
FADD R9, R8, R9 ;
FADD R10, R9, R10 ;
FADD R11, R10, R11 ;
FADD R16, R11, R16 ;
LDS.128 R8, [0x90] ;
FADD R17, R16, R17 ;
FADD R18, R17, R18 ;
FADD R19, R18, R19 ;
FADD R12, R19, R12 ;
LDS.128 R16, [0xa0] ;
FADD R13, R12, R13 ;
FADD R14, R13, R14 ;
FADD R15, R14, R15 ;
FADD R4, R15, R4 ;
LDS.128 R12, [0xb0] ;
FADD R5, R4, R5 ;
FADD R6, R5, R6 ;
FADD R7, R6, R7 ;
FADD R8, R7, R8 ;
LDS.128 R4, [0xc0] ;
FADD R9, R8, R9 ;
FADD R10, R9, R10 ;
FADD R11, R10, R11 ;
FADD R16, R11, R16 ;
LDS.128 R8, [0xd0] ;
FADD R17, R16, R17 ;
FADD R18, R17, R18 ;
FADD R19, R18, R19 ;
FADD R12, R19, R12 ;
LDS.128 R16, [0xe0] ;
FADD R13, R12, R13 ;
FADD R14, R13, R14 ;
FADD R15, R14, R15 ;
FADD R4, R15, R4 ;
LDS.128 R12, [0xf0] ;
FADD R5, R4, R5 ;
FADD R6, R5, R6 ;
FADD R7, R6, R7 ;
FADD R8, R7, R8 ;
LDS.128 R4, [0x100] ;
FADD R9, R8, R9 ;
FADD R10, R9, R10 ;
FADD R11, R10, R11 ;
FADD R16, R11, R16 ;
LDS.128 R8, [0x110] ;
FADD R17, R16, R17 ;
FADD R18, R17, R18 ;
FADD R19, R18, R19 ;
FADD R12, R19, R12 ;
LDS.128 R16, [0x120] ;
FADD R13, R12, R13 ;
FADD R14, R13, R14 ;
FADD R15, R14, R15 ;
FADD R4, R15, R4 ;
LDS.128 R12, [0x130] ;
FADD R5, R4, R5 ;
FADD R6, R5, R6 ;
FADD R7, R6, R7 ;
FADD R8, R7, R8 ;
LDS.128 R4, [0x140] ;
FADD R9, R8, R9 ;
FADD R10, R9, R10 ;
FADD R11, R10, R11 ;
FADD R16, R11, R16 ;
LDS.128 R8, [0x150] ;
FADD R17, R16, R17 ;
FADD R18, R17, R18 ;
FADD R19, R18, R19 ;
FADD R12, R19, R12 ;
LDS.128 R16, [0x160] ;
FADD R13, R12, R13 ;
FADD R14, R13, R14 ;
FADD R15, R14, R15 ;
FADD R4, R15, R4 ;
LDS.128 R12, [0x170] ;
FADD R5, R4, R5 ;
FADD R6, R5, R6 ;
FADD R7, R6, R7 ;
FADD R8, R7, R8 ;
LDS.128 R4, [0x180] ;
FADD R9, R8, R9 ;
FADD R10, R9, R10 ;
FADD R11, R10, R11 ;
FADD R16, R11, R16 ;
LDS.128 R8, [0x190] ;
FADD R17, R16, R17 ;
FADD R18, R17, R18 ;
FADD R19, R18, R19 ;
FADD R12, R19, R12 ;
LDS.128 R16, [0x1a0] ;
FADD R13, R12, R13 ;
FADD R14, R13, R14 ;
FADD R15, R14, R15 ;
FADD R4, R15, R4 ;
LDS.128 R12, [0x1b0] ;
FADD R5, R4, R5 ;
FADD R6, R5, R6 ;
FADD R7, R6, R7 ;
FADD R8, R7, R8 ;
LDS.128 R4, [0x1c0] ;
FADD R9, R8, R9 ;
FADD R10, R9, R10 ;
FADD R11, R10, R11 ;
FADD R16, R11, R16 ;
LDS.128 R8, [0x1d0] ;
FADD R17, R16, R17 ;
FADD R18, R17, R18 ;
FADD R19, R18, R19 ;
FADD R12, R19, R12 ;
LDS.128 R16, [0x1e0] ;
FADD R13, R12, R13 ;
FADD R14, R13, R14 ;
FADD R15, R14, R15 ;
FADD R4, R15, R4 ;
LDS.128 R12, [0x1f0] ;
FADD R5, R4, R5 ;
FADD R6, R5, R6 ;
FADD R7, R6, R7 ;
FADD R8, R7, R8 ;
LDS.128 R4, [0x200] ;
FADD R9, R8, R9 ;
FADD R10, R9, R10 ;
FADD R11, R10, R11 ;
FADD R16, R11, R16 ;
LDS.128 R8, [0x210] ;
FADD R17, R16, R17 ;
FADD R18, R17, R18 ;
FADD R19, R18, R19 ;
FADD R12, R19, R12 ;
LDS.128 R16, [0x220] ;
FADD R13, R12, R13 ;
FADD R14, R13, R14 ;
FADD R15, R14, R15 ;
FADD R4, R15, R4 ;
LDS.128 R12, [0x230] ;
FADD R5, R4, R5 ;
FADD R6, R5, R6 ;
FADD R7, R6, R7 ;
FADD R8, R7, R8 ;
LDS.128 R4, [0x240] ;
FADD R9, R8, R9 ;
FADD R10, R9, R10 ;
FADD R11, R10, R11 ;
FADD R16, R11, R16 ;
LDS.128 R8, [0x250] ;
FADD R17, R16, R17 ;
FADD R18, R17, R18 ;
FADD R19, R18, R19 ;
FADD R12, R19, R12 ;
LDS.128 R16, [0x260] ;
FADD R13, R12, R13 ;
FADD R14, R13, R14 ;
FADD R15, R14, R15 ;
FADD R4, R15, R4 ;
LDS.128 R12, [0x270] ;
FADD R5, R4, R5 ;
FADD R6, R5, R6 ;
FADD R7, R6, R7 ;
FADD R8, R7, R8 ;
LDS.128 R4, [0x280] ;
FADD R9, R8, R9 ;
FADD R10, R9, R10 ;
FADD R11, R10, R11 ;
FADD R16, R11, R16 ;
LDS.128 R8, [0x290] ;
FADD R17, R16, R17 ;
FADD R18, R17, R18 ;
FADD R19, R18, R19 ;
FADD R12, R19, R12 ;
LDS.128 R16, [0x2a0] ;
FADD R13, R12, R13 ;
FADD R14, R13, R14 ;
FADD R15, R14, R15 ;
FADD R4, R15, R4 ;
LDS.128 R12, [0x2b0] ;
FADD R5, R4, R5 ;
FADD R6, R5, R6 ;
FADD R7, R6, R7 ;
FADD R8, R7, R8 ;
LDS.128 R4, [0x2c0] ;
FADD R9, R8, R9 ;
FADD R10, R9, R10 ;
FADD R11, R10, R11 ;
FADD R16, R11, R16 ;
LDS.128 R8, [0x2d0] ;
FADD R17, R16, R17 ;
FADD R18, R17, R18 ;
FADD R19, R18, R19 ;
FADD R12, R19, R12 ;
LDS.128 R16, [0x2e0] ;
FADD R13, R12, R13 ;
FADD R14, R13, R14 ;
FADD R15, R14, R15 ;
FADD R4, R15, R4 ;
LDS.128 R12, [0x2f0] ;
FADD R5, R4, R5 ;
FADD R6, R5, R6 ;
FADD R7, R6, R7 ;
FADD R8, R7, R8 ;
LDS.128 R4, [0x300] ;
FADD R9, R8, R9 ;
FADD R10, R9, R10 ;
FADD R11, R10, R11 ;
FADD R16, R11, R16 ;
LDS.128 R8, [0x310] ;
FADD R17, R16, R17 ;
FADD R18, R17, R18 ;
FADD R19, R18, R19 ;
FADD R12, R19, R12 ;
LDS.128 R16, [0x320] ;
FADD R13, R12, R13 ;
FADD R14, R13, R14 ;
FADD R15, R14, R15 ;
FADD R4, R15, R4 ;
LDS.128 R12, [0x330] ;
FADD R5, R4, R5 ;
FADD R6, R5, R6 ;
FADD R7, R6, R7 ;
FADD R8, R7, R8 ;
LDS.128 R4, [0x340] ;
FADD R9, R8, R9 ;
FADD R10, R9, R10 ;
FADD R11, R10, R11 ;
FADD R16, R11, R16 ;
LDS.128 R8, [0x350] ;
FADD R17, R16, R17 ;
FADD R18, R17, R18 ;
FADD R19, R18, R19 ;
FADD R12, R19, R12 ;
LDS.128 R16, [0x360] ;
FADD R13, R12, R13 ;
FADD R14, R13, R14 ;
FADD R15, R14, R15 ;
FADD R4, R15, R4 ;
LDS.128 R12, [0x370] ;
FADD R5, R4, R5 ;
FADD R6, R5, R6 ;
FADD R7, R6, R7 ;
FADD R8, R7, R8 ;
LDS.128 R4, [0x380] ;
FADD R9, R8, R9 ;
FADD R10, R9, R10 ;
FADD R11, R10, R11 ;
FADD R16, R11, R16 ;
LDS.128 R8, [0x390] ;
FADD R17, R16, R17 ;
FADD R18, R17, R18 ;
FADD R19, R18, R19 ;
FADD R12, R19, R12 ;
LDS.128 R16, [0x3a0] ;
FADD R13, R12, R13 ;
FADD R14, R13, R14 ;
FADD R15, R14, R15 ;
FADD R4, R15, R4 ;
LDS.128 R12, [0x3b0] ;
FADD R5, R4, R5 ;
FADD R6, R5, R6 ;
FADD R7, R6, R7 ;
FADD R8, R7, R8 ;
LDS.128 R4, [0x3c0] ;
FADD R9, R8, R9 ;
FADD R10, R9, R10 ;
FADD R11, R10, R11 ;
FADD R16, R11, R16 ;
LDS.128 R8, [0x3d0] ;
FADD R17, R16, R17 ;
FADD R18, R17, R18 ;
FADD R19, R18, R19 ;
FADD R12, R19, R12 ;
LDS.128 R16, [0x3e0] ;
FADD R13, R12, R13 ;
FADD R14, R13, R14 ;
FADD R15, R14, R15 ;
FADD R4, R15, R4 ;
LDS.128 R12, [0x3f0] ;
FADD R5, R4, R5 ;
FADD R6, R5, R6 ;
FADD R7, R6, R7 ;
FADD R8, R7, R8 ;
LDS.128 R4, [0x400] ;
FADD R9, R8, R9 ;
FADD R10, R9, R10 ;
FADD R11, R10, R11 ;
FADD R16, R11, R16 ;
LDS.128 R8, [0x410] ;
FADD R17, R16, R17 ;
FADD R18, R17, R18 ;
FADD R19, R18, R19 ;
FADD R12, R19, R12 ;
LDS.128 R16, [0x420] ;
FADD R13, R12, R13 ;
FADD R14, R13, R14 ;
FADD R15, R14, R15 ;
FADD R4, R15, R4 ;
LDS.128 R12, [0x430] ;
FADD R5, R4, R5 ;
FADD R6, R5, R6 ;
FADD R7, R6, R7 ;
FADD R8, R7, R8 ;
LDS.128 R4, [0x440] ;
FADD R9, R8, R9 ;
FADD R10, R9, R10 ;
FADD R11, R10, R11 ;
FADD R16, R11, R16 ;
LDS.128 R8, [0x450] ;
FADD R17, R16, R17 ;
FADD R18, R17, R18 ;
FADD R19, R18, R19 ;
FADD R12, R19, R12 ;
LDS.128 R16, [0x460] ;
FADD R13, R12, R13 ;
FADD R14, R13, R14 ;
FADD R15, R14, R15 ;
FADD R4, R15, R4 ;
LDS.128 R12, [0x470] ;
FADD R5, R4, R5 ;
FADD R6, R5, R6 ;
FADD R7, R6, R7 ;
FADD R8, R7, R8 ;
LDS.128 R4, [0x480] ;
FADD R9, R8, R9 ;
FADD R10, R9, R10 ;
FADD R11, R10, R11 ;
FADD R16, R11, R16 ;
LDS.128 R8, [0x490] ;
FADD R17, R16, R17 ;
FADD R18, R17, R18 ;
FADD R19, R18, R19 ;
FADD R12, R19, R12 ;
LDS.128 R16, [0x4a0] ;
FADD R13, R12, R13 ;
FADD R14, R13, R14 ;
FADD R15, R14, R15 ;
FADD R4, R15, R4 ;
LDS.128 R12, [0x4b0] ;
FADD R5, R4, R5 ;
FADD R6, R5, R6 ;
FADD R7, R6, R7 ;
FADD R8, R7, R8 ;
LDS.128 R4, [0x4c0] ;
FADD R9, R8, R9 ;
FADD R10, R9, R10 ;
FADD R11, R10, R11 ;
FADD R16, R11, R16 ;
LDS.128 R8, [0x4d0] ;
FADD R17, R16, R17 ;
FADD R18, R17, R18 ;
FADD R19, R18, R19 ;
FADD R12, R19, R12 ;
LDS.128 R16, [0x4e0] ;
FADD R13, R12, R13 ;
FADD R14, R13, R14 ;
FADD R15, R14, R15 ;
FADD R4, R15, R4 ;
LDS.128 R12, [0x4f0] ;
FADD R5, R4, R5 ;
FADD R6, R5, R6 ;
FADD R7, R6, R7 ;
FADD R8, R7, R8 ;
LDS.128 R4, [0x500] ;
FADD R9, R8, R9 ;
FADD R10, R9, R10 ;
FADD R11, R10, R11 ;
FADD R16, R11, R16 ;
LDS.128 R8, [0x510] ;
FADD R17, R16, R17 ;
FADD R18, R17, R18 ;
FADD R19, R18, R19 ;
FADD R12, R19, R12 ;
LDS.128 R16, [0x520] ;
FADD R13, R12, R13 ;
FADD R14, R13, R14 ;
FADD R15, R14, R15 ;
FADD R4, R15, R4 ;
LDS.128 R12, [0x530] ;
FADD R5, R4, R5 ;
FADD R6, R5, R6 ;
FADD R7, R6, R7 ;
FADD R8, R7, R8 ;
LDS.128 R4, [0x540] ;
FADD R9, R8, R9 ;
FADD R10, R9, R10 ;
FADD R11, R10, R11 ;
FADD R16, R11, R16 ;
LDS.128 R8, [0x550] ;
FADD R17, R16, R17 ;
FADD R18, R17, R18 ;
FADD R19, R18, R19 ;
FADD R12, R19, R12 ;
LDS.128 R16, [0x560] ;
FADD R13, R12, R13 ;
FADD R14, R13, R14 ;
FADD R15, R14, R15 ;
FADD R4, R15, R4 ;
LDS.128 R12, [0x570] ;
FADD R5, R4, R5 ;
FADD R6, R5, R6 ;
FADD R7, R6, R7 ;
FADD R8, R7, R8 ;
LDS.128 R4, [0x580] ;
FADD R9, R8, R9 ;
FADD R10, R9, R10 ;
FADD R11, R10, R11 ;
FADD R16, R11, R16 ;
LDS.128 R8, [0x590] ;
FADD R17, R16, R17 ;
FADD R18, R17, R18 ;
FADD R19, R18, R19 ;
FADD R12, R19, R12 ;
LDS.128 R16, [0x5a0] ;
FADD R13, R12, R13 ;
FADD R14, R13, R14 ;
FADD R15, R14, R15 ;
FADD R4, R15, R4 ;
LDS.128 R12, [0x5b0] ;
FADD R5, R4, R5 ;
FADD R6, R5, R6 ;
FADD R7, R6, R7 ;
FADD R8, R7, R8 ;
LDS.128 R4, [0x5c0] ;
FADD R9, R8, R9 ;
FADD R10, R9, R10 ;
FADD R11, R10, R11 ;
FADD R16, R11, R16 ;
LDS.128 R8, [0x5d0] ;
FADD R17, R16, R17 ;
FADD R18, R17, R18 ;
FADD R19, R18, R19 ;
FADD R12, R19, R12 ;
LDS.128 R16, [0x5e0] ;
FADD R13, R12, R13 ;
FADD R14, R13, R14 ;
FADD R15, R14, R15 ;
FADD R4, R15, R4 ;
LDS.128 R12, [0x5f0] ;
FADD R5, R4, R5 ;
FADD R6, R5, R6 ;
FADD R7, R6, R7 ;
FADD R8, R7, R8 ;
LDS.128 R4, [0x600] ;
FADD R9, R8, R9 ;
FADD R10, R9, R10 ;
FADD R11, R10, R11 ;
FADD R16, R11, R16 ;
LDS.128 R8, [0x610] ;
FADD R17, R16, R17 ;
FADD R18, R17, R18 ;
FADD R19, R18, R19 ;
FADD R12, R19, R12 ;
LDS.128 R16, [0x620] ;
FADD R13, R12, R13 ;
FADD R14, R13, R14 ;
FADD R15, R14, R15 ;
FADD R4, R15, R4 ;
LDS.128 R12, [0x630] ;
FADD R5, R4, R5 ;
FADD R6, R5, R6 ;
FADD R7, R6, R7 ;
FADD R8, R7, R8 ;
LDS.128 R4, [0x640] ;
FADD R9, R8, R9 ;
FADD R10, R9, R10 ;
FADD R11, R10, R11 ;
FADD R16, R11, R16 ;
LDS.128 R8, [0x650] ;
FADD R17, R16, R17 ;
FADD R18, R17, R18 ;
FADD R19, R18, R19 ;
FADD R12, R19, R12 ;
LDS.128 R16, [0x660] ;
FADD R13, R12, R13 ;
FADD R14, R13, R14 ;
FADD R15, R14, R15 ;
FADD R4, R15, R4 ;
LDS.128 R12, [0x670] ;
FADD R5, R4, R5 ;
FADD R6, R5, R6 ;
FADD R7, R6, R7 ;
FADD R8, R7, R8 ;
LDS.128 R4, [0x680] ;
FADD R9, R8, R9 ;
FADD R10, R9, R10 ;
FADD R11, R10, R11 ;
FADD R16, R11, R16 ;
LDS.128 R8, [0x690] ;
FADD R17, R16, R17 ;
FADD R18, R17, R18 ;
FADD R19, R18, R19 ;
FADD R12, R19, R12 ;
LDS.128 R16, [0x6a0] ;
FADD R13, R12, R13 ;
FADD R14, R13, R14 ;
FADD R15, R14, R15 ;
FADD R4, R15, R4 ;
LDS.128 R12, [0x6b0] ;
FADD R5, R4, R5 ;
FADD R6, R5, R6 ;
FADD R7, R6, R7 ;
FADD R8, R7, R8 ;
LDS.128 R4, [0x6c0] ;
FADD R9, R8, R9 ;
FADD R10, R9, R10 ;
FADD R11, R10, R11 ;
FADD R16, R11, R16 ;
LDS.128 R8, [0x6d0] ;
FADD R17, R16, R17 ;
FADD R18, R17, R18 ;
FADD R19, R18, R19 ;
FADD R12, R19, R12 ;
LDS.128 R16, [0x6e0] ;
FADD R13, R12, R13 ;
FADD R14, R13, R14 ;
FADD R15, R14, R15 ;
FADD R4, R15, R4 ;
LDS.128 R12, [0x6f0] ;
FADD R5, R4, R5 ;
FADD R6, R5, R6 ;
FADD R7, R6, R7 ;
FADD R8, R7, R8 ;
LDS.128 R4, [0x700] ;
FADD R9, R8, R9 ;
FADD R10, R9, R10 ;
FADD R11, R10, R11 ;
FADD R16, R11, R16 ;
LDS.128 R8, [0x710] ;
FADD R17, R16, R17 ;
FADD R18, R17, R18 ;
FADD R19, R18, R19 ;
FADD R12, R19, R12 ;
LDS.128 R16, [0x720] ;
FADD R13, R12, R13 ;
FADD R14, R13, R14 ;
FADD R15, R14, R15 ;
FADD R4, R15, R4 ;
LDS.128 R12, [0x730] ;
FADD R5, R4, R5 ;
FADD R6, R5, R6 ;
FADD R7, R6, R7 ;
FADD R8, R7, R8 ;
LDS.128 R4, [0x740] ;
FADD R9, R8, R9 ;
FADD R10, R9, R10 ;
FADD R11, R10, R11 ;
FADD R16, R11, R16 ;
LDS.128 R8, [0x750] ;
FADD R17, R16, R17 ;
FADD R18, R17, R18 ;
FADD R19, R18, R19 ;
FADD R12, R19, R12 ;
LDS.128 R16, [0x760] ;
FADD R13, R12, R13 ;
FADD R14, R13, R14 ;
FADD R15, R14, R15 ;
FADD R4, R15, R4 ;
LDS.128 R12, [0x770] ;
FADD R5, R4, R5 ;
FADD R6, R5, R6 ;
FADD R7, R6, R7 ;
FADD R8, R7, R8 ;
LDS.128 R4, [0x780] ;
FADD R9, R8, R9 ;
FADD R10, R9, R10 ;
FADD R11, R10, R11 ;
FADD R16, R11, R16 ;
LDS.128 R8, [0x790] ;
FADD R17, R16, R17 ;
FADD R18, R17, R18 ;
FADD R19, R18, R19 ;
FADD R12, R19, R12 ;
LDS.128 R16, [0x7a0] ;
FADD R13, R12, R13 ;
FADD R14, R13, R14 ;
FADD R15, R14, R15 ;
FADD R4, R4, R15 ;
LDS.128 R12, [0x7b0] ;
FADD R5, R4, R5 ;
FADD R6, R5, R6 ;
FADD R7, R6, R7 ;
FADD R8, R7, R8 ;
LDS.128 R4, [0x7c0] ;
FADD R9, R8, R9 ;
FADD R10, R9, R10 ;
FADD R11, R10, R11 ;
FADD R16, R11, R16 ;
LDS.128 R8, [0x7d0] ;
FADD R17, R16, R17 ;
FADD R18, R17, R18 ;
FADD R19, R18, R19 ;
FADD R12, R19, R12 ;
LDS.128 R16, [0x7e0] ;
FADD R13, R12, R13 ;
FADD R14, R13, R14 ;
FADD R15, R14, R15 ;
FADD R4, R15, R4 ;
LDS.128 R12, [0x7f0] ;
FADD R5, R4, R5 ;
LEA R4, P0, R0, c[0x0][0x178], 0x2 ;
FADD R6, R5, R6 ;
SHF.R.S32.HI R5, RZ, 0x1f, R0 ;
FADD R7, R6, R7 ;
LEA.HI.X R5, R0, c[0x0][0x17c], R5, 0x2, P0 ;
FADD R8, R7, R8 ;
FADD R9, R8, R9 ;
FADD R10, R9, R10 ;
FADD R11, R10, R11 ;
FADD R16, R11, R16 ;
FADD R17, R16, R17 ;
FADD R18, R17, R18 ;
FADD R19, R18, R19 ;
FADD R12, R19, R12 ;
FADD R13, R12, R13 ;
FADD R14, R13, R14 ;
FADD R15, R14, R15 ;
STG.E [R2.64], R15 ;
LDG.E R0, [R4.64] ;
HFMA2.MMA R7, -RZ, RZ, 1.875, 0 ;
FADD R6, R0, 9.9999997473787516356e-06 ;
FSETP.NEU.AND P0, PT, R6, 1, PT ;
@!P0 BRA 0x34e0 ;
FSETP.GTU.AND P0, PT, |R6|, +INF , PT ;
@P0 BRA 0x34d0 ;
FSETP.NEU.AND P0, PT, |R6|, +INF , PT ;
FSETP.EQ.OR P0, PT, R6, RZ, !P0 ;
@P0 BRA 0x3490 ;
FMUL R5, |R6|.reuse, 16777216 ;
FSETP.GEU.AND P0, PT, |R6|, 1.175494350822287508e-38, PT ;
MOV R11, 0x3a2c32e4 ;
FSEL R5, R5, |R6|, !P0 ;
FSETP.GEU.AND P2, PT, R0, -9.9999997473787516356e-06, PT ;
IADD3 R4, R5, -0x3f3504f3, RZ ;
LOP3.LUT R4, R4, 0xff800000, RZ, 0xc0, !PT ;
IADD3 R5, R5, -R4, RZ ;
I2F R4, R4 ;
FADD R7, R5.reuse, 1 ;
FADD R6, R5, -1 ;
FSEL R5, RZ, -24, P0 ;
MUFU.RCP R7, R7 ;
FADD R8, R6, R6 ;
FFMA R5, R4, 1.1920928955078125e-07, R5 ;
FMUL R9, R7, R8 ;
FADD R10, R6, -R9 ;
FMUL R8, R9.reuse, R9 ;
FFMA R12, R9, 1.4426950216293334961, R5 ;
FADD R10, R10, R10 ;
FFMA R11, R8, R11, 0.0032181653659790754318 ;
FADD R4, R5, -R12 ;
FFMA R10, R6, -R9, R10 ;
HFMA2.MMA R6, -RZ, RZ, 0.64013671875, -15.109375 ;
FFMA R11, R8.reuse, R11, 0.018033718690276145935 ;
FFMA R5, R9, 1.4426950216293334961, R4 ;
FMUL R10, R7, R10 ;
FFMA R11, R8, R11, 0.12022458761930465698 ;
FFMA R4, R10, 1.4426950216293334961, R5 ;
FMUL R8, R8, R11 ;
FFMA R4, R9, 1.9251366722983220825e-08, R4 ;
FMUL R5, R8, 3 ;
FFMA R4, R10, R5, R4 ;
FFMA R9, R9, R8, R4 ;
FADD R5, R12, R9 ;
FMUL R4, R5.reuse, -1.5 ;
FADD R12, -R12, R5 ;
FRND R7, R4 ;
FFMA R5, R5, -1.5, -R4 ;
FSETP.GT.AND P1, PT, |R4|, 152, PT ;
FADD R12, R9, -R12 ;
FFMA R12, R12, -1.5, R5 ;
F2I.NTZ R9, R4 ;
FADD R5, R4, -R7 ;
FSETP.GT.AND P0, PT, R7, RZ, PT ;
FADD R5, R5, R12 ;
FFMA R6, R5, R6, 0.0013391353422775864601 ;
FFMA R6, R5, R6, 0.0096188392490148544312 ;
FFMA R6, R5, R6, 0.055503588169813156128 ;
FFMA R8, R5.reuse, R6, 0.24022644758224487305 ;
SEL R6, RZ, 0x83000000, P0 ;
FSETP.GEU.AND P0, PT, R4, RZ, PT ;
FFMA R10, R5, R8, 0.69314718246459960938 ;
IADD3 R8, R6, 0x7f000000, RZ ;
LEA R9, R9, -R6, 0x17 ;
FFMA R5, R5, R10, 1 ;
FSEL R7, RZ, +INF , !P0 ;
FMUL R8, R8, R5 ;
@!P1 FMUL R7, R9, R8 ;
@P2 BRA 0x34e0 ;
MOV R7, 0x7fffffff ;
BRA 0x34e0 ;
FADD R6, R6, R6 ;
LOP3.LUT R6, R6, 0x7f800000, RZ, 0x3c, !PT ;
LOP3.LUT R7, R6, 0x7fffffff, RZ, 0xc0, !PT ;
BRA 0x34e0 ;
FADD R7, R6, -1.5 ;
FMUL R0, R7, -0.5 ;
FMUL R15, R15, R0 ;
STG.E [R2.64], R15 ;
EXIT ;
BRA 0x3520;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
```
|
```amdasm
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z26fast_variance_delta_kernelPfS_S_S_iiiS_ ; -- Begin function _Z26fast_variance_delta_kernelPfS_S_S_iiiS_
.globl _Z26fast_variance_delta_kernelPfS_S_S_iiiS_
.p2align 8
.type _Z26fast_variance_delta_kernelPfS_S_S_iiiS_,@function
_Z26fast_variance_delta_kernelPfS_S_S_iiiS_: ; @_Z26fast_variance_delta_kernelPfS_S_S_iiiS_
; %bb.0:
s_mov_b32 s2, s15
s_clause 0x1
s_load_b128 s[12:15], s[0:1], 0x20
s_load_b256 s[4:11], s[0:1], 0x0
v_dual_mov_b32 v4, 0 :: v_dual_lshlrev_b32 v3, 2, v0
ds_store_b32 v3, v4
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s12, 1
s_cbranch_scc1 .LBB0_9
; %bb.1: ; %.preheader.lr.ph
s_cmp_gt_i32 s14, 0
v_mad_u64_u32 v[1:2], null, s2, s14, v[0:1]
s_cselect_b32 s15, -1, 0
s_ashr_i32 s3, s2, 31
s_mov_b32 s16, 0
s_lshl_b64 s[18:19], s[2:3], 2
s_mul_i32 s3, s14, s13
s_add_u32 s8, s8, s18
s_addc_u32 s9, s9, s19
.LBB0_2: ; %.preheader
; =>This Loop Header: Depth=1
; Child Loop BB0_4 Depth 2
s_and_not1_b32 vcc_lo, exec_lo, s15
s_cbranch_vccnz .LBB0_8
; %bb.3: ; %.lr.ph
; in Loop: Header=BB0_2 Depth=1
s_mov_b32 s13, 0
.LBB0_4: ; Parent Loop BB0_2 Depth=1
; => This Inner Loop Header: Depth=2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v2, s13, v0
v_cmp_gt_i32_e32 vcc_lo, s14, v2
v_mov_b32_e32 v2, 0
s_and_saveexec_b32 s17, vcc_lo
s_cbranch_execz .LBB0_6
; %bb.5: ; in Loop: Header=BB0_4 Depth=2
v_add_nc_u32_e32 v5, s13, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v6, 31, v5
v_lshlrev_b64 v[5:6], 2, v[5:6]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v7, vcc_lo, s4, v5
v_add_co_ci_u32_e32 v8, vcc_lo, s5, v6, vcc_lo
v_add_co_u32 v5, vcc_lo, s6, v5
v_add_co_ci_u32_e32 v6, vcc_lo, s7, v6, vcc_lo
global_load_b32 v2, v[7:8], off
global_load_b32 v5, v[5:6], off
s_load_b32 s18, s[8:9], 0x0
s_waitcnt vmcnt(1) lgkmcnt(0)
v_subrev_f32_e32 v2, s18, v2
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_mul_f32_e32 v2, v5, v2
.LBB0_6: ; in Loop: Header=BB0_4 Depth=2
s_or_b32 exec_lo, exec_lo, s17
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_add_f32_e32 v4, v2, v4
s_addk_i32 s13, 0x200
s_cmp_lt_i32 s13, s14
s_cbranch_scc1 .LBB0_4
; %bb.7: ; %._crit_edge
; in Loop: Header=BB0_2 Depth=1
ds_store_b32 v3, v4
.LBB0_8: ; in Loop: Header=BB0_2 Depth=1
v_add_nc_u32_e32 v1, s3, v1
s_add_i32 s16, s16, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_lg_u32 s16, s12
s_cbranch_scc1 .LBB0_2
.LBB0_9: ; %._crit_edge44
s_mov_b32 s3, 0
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_mov_b32 s4, exec_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB0_13
; %bb.10:
v_mov_b32_e32 v0, 0
.LBB0_11: ; =>This Inner Loop Header: Depth=1
v_mov_b32_e32 v1, s3
s_add_i32 s3, s3, 4
s_delay_alu instid0(SALU_CYCLE_1)
s_cmpk_lg_i32 s3, 0x800
ds_load_b32 v1, v1
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v0, v1, v0
s_cbranch_scc1 .LBB0_11
; %bb.12:
s_load_b64 s[0:1], s[0:1], 0x30
s_ashr_i32 s3, s2, 31
v_mov_b32_e32 v1, 0
s_lshl_b64 s[2:3], s[2:3], 2
s_waitcnt lgkmcnt(0)
s_add_u32 s4, s0, s2
s_addc_u32 s5, s1, s3
s_add_u32 s0, s10, s2
s_addc_u32 s1, s11, s3
global_store_b32 v1, v0, s[4:5]
global_load_b32 v2, v1, s[0:1]
s_mov_b32 s0, 0x3e76c4e1
s_waitcnt vmcnt(0)
v_add_f32_e32 v2, 0x3727c5ac, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_frexp_mant_f32_e64 v3, |v2|
v_cmp_gt_f32_e32 vcc_lo, 0x3f2aaaab, v3
v_cndmask_b32_e64 v4, 0, 1, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ldexp_f32 v3, v3, v4
v_add_f32_e32 v6, -1.0, v3
v_add_f32_e32 v4, 1.0, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f32_e32 v5, v4
s_waitcnt_depctr 0xfff
v_dual_mul_f32 v7, v6, v5 :: v_dual_add_f32 v8, -1.0, v4
v_mul_f32_e32 v9, v4, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_f32_e32 v3, v3, v8
v_fma_f32 v4, v7, v4, -v9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v4, v7, v3
v_add_f32_e32 v3, v9, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_sub_f32 v8, v6, v3 :: v_dual_sub_f32 v9, v3, v9
v_sub_f32_e32 v4, v9, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_f32_e32 v6, v6, v8
v_sub_f32_e32 v3, v6, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v3, v4, v3
v_add_f32_e32 v3, v8, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v3, v5, v3
v_add_f32_e32 v4, v7, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mul_f32_e32 v6, v4, v4
v_sub_f32_e32 v5, v4, v7
v_sub_f32_e32 v3, v3, v5
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v5, v4, v4, -v6
v_add_f32_e32 v7, v3, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v5, v4, v7
v_add_f32_e32 v7, v6, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_fmaak_f32 v8, s0, v7, 0x3e91f4c4
v_sub_f32_e32 v6, v7, v6
v_dual_fmaak_f32 v8, v7, v8, 0x3ecccdef :: v_dual_sub_f32 v5, v5, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v9, v7, v8
v_fma_f32 v6, v7, v8, -v9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_fmac_f32 v6, v5, v8 :: v_dual_mul_f32 v11, v4, v7
v_add_f32_e32 v8, v9, v6
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v12, v7, v4, -v11
v_dual_sub_f32 v9, v8, v9 :: v_dual_fmac_f32 v12, v7, v3
v_add_f32_e32 v10, 0x3f2aaaaa, v8
v_ldexp_f32 v3, v3, 1
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_sub_f32_e32 v6, v6, v9
v_fmac_f32_e32 v12, v5, v4
v_ldexp_f32 v4, v4, 1
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_f32_e32 v6, 0x31739010, v6
v_add_f32_e32 v9, 0xbf2aaaaa, v10
v_sub_f32_e32 v8, v8, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v6, v6, v8
v_add_f32_e32 v5, v10, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_add_f32 v7, v11, v12 :: v_dual_sub_f32 v8, v10, v5
v_mul_f32_e32 v9, v7, v5
v_sub_f32_e32 v10, v7, v11
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f32_e32 v6, v6, v8
v_fma_f32 v8, v7, v5, -v9
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_f32_e32 v10, v12, v10
v_fmac_f32_e32 v8, v7, v6
v_frexp_exp_i32_f32_e32 v6, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fmac_f32_e32 v8, v10, v5
v_subrev_co_ci_u32_e32 v5, vcc_lo, 0, v6, vcc_lo
v_cmp_eq_f32_e32 vcc_lo, 1.0, v2
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f32_e32 v6, v9, v8
v_cvt_f32_i32_e32 v5, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_sub_f32_e32 v9, v6, v9
v_add_f32_e32 v7, v4, v6
v_sub_f32_e32 v8, v8, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_mul_f32 v10, 0x3f317218, v5 :: v_dual_add_f32 v3, v3, v8
v_fma_f32 v9, 0x3f317218, v5, -v10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_fmamk_f32 v5, v5, 0xb102e308, v9 :: v_dual_sub_f32 v4, v7, v4
v_sub_f32_e32 v4, v6, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_add_f32 v3, v3, v4 :: v_dual_add_f32 v4, v10, v5
v_add_f32_e32 v6, v7, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_f32_e32 v10, v4, v10
v_sub_f32_e32 v5, v5, v10
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v8, v4, v6
v_sub_f32_e32 v9, v8, v4
v_sub_f32_e32 v7, v6, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_f32_e32 v11, v8, v9
v_dual_sub_f32 v3, v3, v7 :: v_dual_sub_f32 v6, v6, v9
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_f32_e32 v4, v4, v11
v_dual_add_f32 v7, v5, v3 :: v_dual_add_f32 v4, v6, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_f32_e32 v6, v7, v5
v_add_f32_e32 v4, v7, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_sub_f32_e32 v7, v7, v6
v_sub_f32_e32 v3, v3, v6
v_sub_f32_e32 v5, v5, v7
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v9, v8, v4
v_dual_add_f32 v3, v3, v5 :: v_dual_sub_f32 v6, v9, v8
v_cndmask_b32_e64 v5, 0xbfc00000, 1.0, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_f32_e32 v4, v4, v6
v_cmp_gt_f32_e64 s2, 0, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v3, v3, v4
v_add_f32_e32 v4, v9, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_sub_f32 v6, v4, v9 :: v_dual_mul_f32 v7, v5, v4
v_sub_f32_e32 v3, v3, v6
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_fma_f32 v4, v5, v4, -v7
v_cmp_class_f32_e64 vcc_lo, v7, 0x204
v_fmac_f32_e32 v4, v5, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v3, v7, v4
v_cndmask_b32_e32 v6, v3, v7, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_cmp_eq_f32_e32 vcc_lo, 0x42b17218, v6
v_cndmask_b32_e64 v8, 0, 0x37000000, vcc_lo
v_cmp_neq_f32_e64 vcc_lo, 0x7f800000, |v6|
v_sub_f32_e32 v9, v6, v8
v_trunc_f32_e32 v6, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_mul_f32 v10, 0x3fb8aa3b, v9 :: v_dual_sub_f32 v3, v3, v7
v_fma_f32 v11, 0x3fb8aa3b, v9, -v10
v_rndne_f32_e32 v12, v10
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_f32_e32 v3, v4, v3
v_dual_fmamk_f32 v11, v9, 0x32a5705f, v11 :: v_dual_sub_f32 v10, v10, v12
v_cvt_i32_f32_e32 v7, v12
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v10, v10, v11
v_exp_f32_e32 v10, v10
s_waitcnt_depctr 0xfff
v_ldexp_f32 v4, v10, v7
v_cndmask_b32_e32 v3, 0, v3, vcc_lo
v_cmp_ngt_f32_e32 vcc_lo, 0xc2ce8ed0, v9
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_dual_mul_f32 v7, 0.5, v5 :: v_dual_cndmask_b32 v4, 0, v4
v_cmp_nlt_f32_e32 vcc_lo, 0x42b17218, v9
v_trunc_f32_e32 v10, v7
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_dual_add_f32 v3, v8, v3 :: v_dual_cndmask_b32 v4, 0x7f800000, v4
v_cmp_eq_f32_e32 vcc_lo, v6, v5
v_cmp_neq_f32_e64 s0, v10, v7
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_fma_f32 v3, v4, v3, v4
v_cmp_eq_f32_e64 s1, 0x7f800000, v4
s_and_b32 s0, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cndmask_b32_e64 v6, 1.0, v2, s0
v_cndmask_b32_e64 v3, v3, v4, s1
v_cmp_eq_f32_e64 s1, 0, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_bfi_b32 v3, 0x7fffffff, v3, v6
s_xor_b32 s2, s1, s2
v_cndmask_b32_e64 v6, 0, v2, s0
v_cndmask_b32_e64 v4, 0x7f800000, 0, s2
v_cmp_class_f32_e64 s0, v2, 0x204
v_cndmask_b32_e32 v5, 0x7fc00000, v3, vcc_lo
v_cmp_gt_f32_e32 vcc_lo, 0, v2
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_bfi_b32 v4, 0x7fffffff, v4, v6
v_cndmask_b32_e32 v3, v3, v5, vcc_lo
s_or_b32 vcc_lo, s1, s0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v3, v3, v4, vcc_lo
v_cmp_o_f32_e32 vcc_lo, v2, v2
v_mul_f32_e32 v3, -0.5, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v2, 0x7fc00000, v3, vcc_lo
v_mul_f32_e32 v0, v0, v2
global_store_b32 v1, v0, s[4:5]
.LBB0_13:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z26fast_variance_delta_kernelPfS_S_S_iiiS_
.amdhsa_group_segment_fixed_size 2048
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 56
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 13
.amdhsa_next_free_sgpr 20
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z26fast_variance_delta_kernelPfS_S_S_iiiS_, .Lfunc_end0-_Z26fast_variance_delta_kernelPfS_S_S_iiiS_
; -- End function
.section .AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1512
; NumSgprs: 22
; NumVgprs: 13
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 2048 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 22
; NumVGPRsForWavesPerEU: 13
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object ; @__hip_cuid_
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0 ; 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 36
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 48
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 2048
.kernarg_segment_align: 8
.kernarg_segment_size: 56
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z26fast_variance_delta_kernelPfS_S_S_iiiS_
.private_segment_fixed_size: 0
.sgpr_count: 22
.sgpr_spill_count: 0
.symbol: _Z26fast_variance_delta_kernelPfS_S_S_iiiS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 13
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
```
| 12,909 | 8,322 |
451 |
Convert the following CUDA host assembly code to AMD host assembly:
```cudaasm
.file "tmpxft_00172c08_00000000-6_fast_variance_delta_kernel.cudafe1.cpp"
.text
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z57__device_stub__Z26fast_variance_delta_kernelPfS_S_S_iiiS_PfS_S_S_iiiS_
.type _Z57__device_stub__Z26fast_variance_delta_kernelPfS_S_S_iiiS_PfS_S_S_iiiS_, @function
_Z57__device_stub__Z26fast_variance_delta_kernelPfS_S_S_iiiS_PfS_S_S_iiiS_:
.LFB2051:
.cfi_startproc
endbr64
subq $200, %rsp
.cfi_def_cfa_offset 208
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movl %r8d, 12(%rsp)
movl %r9d, 8(%rsp)
movq 216(%rsp), %rax
movq %rax, (%rsp)
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 12(%rsp), %rax
movq %rax, 144(%rsp)
leaq 8(%rsp), %rax
movq %rax, 152(%rsp)
leaq 208(%rsp), %rax
movq %rax, 160(%rsp)
movq %rsp, %rax
movq %rax, 168(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 216
pushq 56(%rsp)
.cfi_def_cfa_offset 224
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z26fast_variance_delta_kernelPfS_S_S_iiiS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 208
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z57__device_stub__Z26fast_variance_delta_kernelPfS_S_S_iiiS_PfS_S_S_iiiS_, .-_Z57__device_stub__Z26fast_variance_delta_kernelPfS_S_S_iiiS_PfS_S_S_iiiS_
.globl _Z26fast_variance_delta_kernelPfS_S_S_iiiS_
.type _Z26fast_variance_delta_kernelPfS_S_S_iiiS_, @function
_Z26fast_variance_delta_kernelPfS_S_S_iiiS_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
pushq 24(%rsp)
.cfi_def_cfa_offset 24
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
call _Z57__device_stub__Z26fast_variance_delta_kernelPfS_S_S_iiiS_PfS_S_S_iiiS_
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z26fast_variance_delta_kernelPfS_S_S_iiiS_, .-_Z26fast_variance_delta_kernelPfS_S_S_iiiS_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z26fast_variance_delta_kernelPfS_S_S_iiiS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z26fast_variance_delta_kernelPfS_S_S_iiiS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
```
|
```amdasm
.text
.file "fast_variance_delta_kernel.hip"
.globl _Z41__device_stub__fast_variance_delta_kernelPfS_S_S_iiiS_ # -- Begin function _Z41__device_stub__fast_variance_delta_kernelPfS_S_S_iiiS_
.type _Z41__device_stub__fast_variance_delta_kernelPfS_S_S_iiiS_,@function
_Z41__device_stub__fast_variance_delta_kernelPfS_S_S_iiiS_: # @_Z41__device_stub__fast_variance_delta_kernelPfS_S_S_iiiS_
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $160, %rsp
.cfi_def_cfa_offset 208
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 56(%rsp), %rax
movq %rdi, (%rax)
leaq 48(%rsp), %rdi
movq %rsi, (%rdi)
leaq 40(%rsp), %rsi
movq %rdx, (%rsi)
leaq 32(%rsp), %rdx
movq %rcx, (%rdx)
leaq 12(%rsp), %rcx
movl %r8d, (%rcx)
leaq 8(%rsp), %r8
movl %r9d, (%r8)
leaq 96(%rsp), %rbx
movq %rax, (%rbx)
movq %rdi, 8(%rbx)
movq %rsi, 16(%rbx)
movq %rdx, 24(%rbx)
movq %rcx, 32(%rbx)
movq %r8, 40(%rbx)
leaq 208(%rsp), %rax
movq %rax, 48(%rbx)
leaq 216(%rsp), %rax
movq %rax, 56(%rbx)
leaq 80(%rsp), %r14
leaq 64(%rsp), %r15
leaq 24(%rsp), %r12
leaq 16(%rsp), %r13
movq %r14, %rdi
movq %r15, %rsi
movq %r12, %rdx
movq %r13, %rcx
callq __hipPopCallConfiguration
movq (%r14), %rsi
movl 8(%r14), %edx
movq (%r15), %rcx
movl 8(%r15), %r8d
movl $_Z26fast_variance_delta_kernelPfS_S_S_iiiS_, %edi
movq %rbx, %r9
pushq (%r13)
.cfi_adjust_cfa_offset 8
pushq (%r12)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $176, %rsp
.cfi_adjust_cfa_offset -176
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z41__device_stub__fast_variance_delta_kernelPfS_S_S_iiiS_, .Lfunc_end0-_Z41__device_stub__fast_variance_delta_kernelPfS_S_S_iiiS_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, %rdi
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z26fast_variance_delta_kernelPfS_S_S_iiiS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z26fast_variance_delta_kernelPfS_S_S_iiiS_,@object # @_Z26fast_variance_delta_kernelPfS_S_S_iiiS_
.section .rodata,"a",@progbits
.globl _Z26fast_variance_delta_kernelPfS_S_S_iiiS_
.p2align 3, 0x0
_Z26fast_variance_delta_kernelPfS_S_S_iiiS_:
.quad _Z41__device_stub__fast_variance_delta_kernelPfS_S_S_iiiS_
.size _Z26fast_variance_delta_kernelPfS_S_S_iiiS_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z26fast_variance_delta_kernelPfS_S_S_iiiS_"
.size .L__unnamed_1, 44
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z41__device_stub__fast_variance_delta_kernelPfS_S_S_iiiS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z26fast_variance_delta_kernelPfS_S_S_iiiS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
```
| 2,204 | 2,310 |
452 |
Convert the following CUDA device assembly code to AMD device assembly:
```cudaasm
code for sm_80
```
|
```amdasm
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object ; @__hip_cuid_
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0 ; 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
```
| 24 | 306 |
453 |
Convert the following CUDA host assembly code to AMD host assembly:
```cudaasm
.file "tmpxft_0015c7e4_00000000-6_vec.cudafe1.cpp"
.text
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2055:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2055:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.align 2
.globl _ZN3VecC2Ev
.type _ZN3VecC2Ev, @function
_ZN3VecC2Ev:
.LFB2028:
.cfi_startproc
endbr64
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $0x00000000, (%rdi)
movl $0x00000000, 4(%rdi)
movq $0, 8(%rsp)
movq 8(%rsp), %rdi
call free@PLT
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2028:
.size _ZN3VecC2Ev, .-_ZN3VecC2Ev
.globl _ZN3VecC1Ev
.set _ZN3VecC1Ev,_ZN3VecC2Ev
.align 2
.globl _ZN3VecC2ERKS_
.type _ZN3VecC2ERKS_, @function
_ZN3VecC2ERKS_:
.LFB2031:
.cfi_startproc
endbr64
subq $24, %rsp
.cfi_def_cfa_offset 32
movq $0, 8(%rsp)
movq 8(%rsp), %rdi
call free@PLT
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2031:
.size _ZN3VecC2ERKS_, .-_ZN3VecC2ERKS_
.globl _ZN3VecC1ERKS_
.set _ZN3VecC1ERKS_,_ZN3VecC2ERKS_
.align 2
.globl _ZN3VecC2Eff
.type _ZN3VecC2Eff, @function
_ZN3VecC2Eff:
.LFB2034:
.cfi_startproc
endbr64
subq $24, %rsp
.cfi_def_cfa_offset 32
movss %xmm0, (%rdi)
movss %xmm1, 4(%rdi)
movq $0, 8(%rsp)
movq 8(%rsp), %rdi
call free@PLT
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2034:
.size _ZN3VecC2Eff, .-_ZN3VecC2Eff
.globl _ZN3VecC1Eff
.set _ZN3VecC1Eff,_ZN3VecC2Eff
.align 2
.globl _ZNK3VecplERKS_
.type _ZNK3VecplERKS_, @function
_ZNK3VecplERKS_:
.LFB2036:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2036:
.size _ZNK3VecplERKS_, .-_ZNK3VecplERKS_
.align 2
.globl _ZNK3VecmiERKS_
.type _ZNK3VecmiERKS_, @function
_ZNK3VecmiERKS_:
.LFB2037:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2037:
.size _ZNK3VecmiERKS_, .-_ZNK3VecmiERKS_
.align 2
.globl _ZNK3VecmlEf
.type _ZNK3VecmlEf, @function
_ZNK3VecmlEf:
.LFB2038:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2038:
.size _ZNK3VecmlEf, .-_ZNK3VecmlEf
.align 2
.globl _ZNK3VecdvEf
.type _ZNK3VecdvEf, @function
_ZNK3VecdvEf:
.LFB2039:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2039:
.size _ZNK3VecdvEf, .-_ZNK3VecdvEf
.align 2
.globl _ZN3VecpLERKS_
.type _ZN3VecpLERKS_, @function
_ZN3VecpLERKS_:
.LFB2040:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2040:
.size _ZN3VecpLERKS_, .-_ZN3VecpLERKS_
.align 2
.globl _ZN3VecmIERKS_
.type _ZN3VecmIERKS_, @function
_ZN3VecmIERKS_:
.LFB2041:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2041:
.size _ZN3VecmIERKS_, .-_ZN3VecmIERKS_
.align 2
.globl _ZN3VecmLEf
.type _ZN3VecmLEf, @function
_ZN3VecmLEf:
.LFB2042:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2042:
.size _ZN3VecmLEf, .-_ZN3VecmLEf
.align 2
.globl _ZN3VecdVEf
.type _ZN3VecdVEf, @function
_ZN3VecdVEf:
.LFB2043:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2043:
.size _ZN3VecdVEf, .-_ZN3VecdVEf
.align 2
.globl _ZNK3Vec13LengthSquaredEv
.type _ZNK3Vec13LengthSquaredEv, @function
_ZNK3Vec13LengthSquaredEv:
.LFB2044:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2044:
.size _ZNK3Vec13LengthSquaredEv, .-_ZNK3Vec13LengthSquaredEv
.align 2
.globl _ZNK3Vec9GetLengthEv
.type _ZNK3Vec9GetLengthEv, @function
_ZNK3Vec9GetLengthEv:
.LFB2045:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2045:
.size _ZNK3Vec9GetLengthEv, .-_ZNK3Vec9GetLengthEv
.align 2
.globl _ZNK3Vec10NormalizedEv
.type _ZNK3Vec10NormalizedEv, @function
_ZNK3Vec10NormalizedEv:
.LFB2046:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2046:
.size _ZNK3Vec10NormalizedEv, .-_ZNK3Vec10NormalizedEv
.align 2
.globl _ZN3Vec9NormalizeEv
.type _ZN3Vec9NormalizeEv, @function
_ZN3Vec9NormalizeEv:
.LFB2047:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2047:
.size _ZN3Vec9NormalizeEv, .-_ZN3Vec9NormalizeEv
.align 2
.globl _ZN3Vec5LimitEf
.type _ZN3Vec5LimitEf, @function
_ZN3Vec5LimitEf:
.LFB2048:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2048:
.size _ZN3Vec5LimitEf, .-_ZN3Vec5LimitEf
.align 2
.globl _ZN3Vec9SetLengthEf
.type _ZN3Vec9SetLengthEf, @function
_ZN3Vec9SetLengthEf:
.LFB2049:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2049:
.size _ZN3Vec9SetLengthEf, .-_ZN3Vec9SetLengthEf
.align 2
.globl _ZNK3Vec4PerpEv
.type _ZNK3Vec4PerpEv, @function
_ZNK3Vec4PerpEv:
.LFB2050:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2050:
.size _ZNK3Vec4PerpEv, .-_ZNK3Vec4PerpEv
.align 2
.globl _ZN3Vec9DirectionERKS_S1_
.type _ZN3Vec9DirectionERKS_S1_, @function
_ZN3Vec9DirectionERKS_S1_:
.LFB2051:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2051:
.size _ZN3Vec9DirectionERKS_S1_, .-_ZN3Vec9DirectionERKS_S1_
.align 2
.globl _ZN3Vec15DistanceSquaredERKS_S1_
.type _ZN3Vec15DistanceSquaredERKS_S1_, @function
_ZN3Vec15DistanceSquaredERKS_S1_:
.LFB2052:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2052:
.size _ZN3Vec15DistanceSquaredERKS_S1_, .-_ZN3Vec15DistanceSquaredERKS_S1_
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2078:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2078:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
```
|
```amdasm
.text
.file "vec.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
```
| 4,408 | 183 |
454 |
Convert the following CUDA device assembly code to AMD device assembly:
```cudaasm
code for sm_80
Function : _Z12myHelloOnGPUPi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
MOV R1, c[0x0][0x28] ;
S2R R2, SR_TID.X ;
HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ;
ULDC.64 UR4, c[0x0][0x118] ;
S2R R3, SR_CTAID.X ;
LOP3.LUT R0, RZ, R2, RZ, 0x33, !PT ;
IMAD R2, R3, c[0x0][0x0], R2 ;
IADD3 R5, R0, c[0x0][0x0], RZ ;
IMAD.WIDE.U32 R2, R2, R7, c[0x0][0x160] ;
STG.E [R2.64], R5 ;
EXIT ;
BRA 0xb0;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
```
|
```amdasm
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z12myHelloOnGPUPi ; -- Begin function _Z12myHelloOnGPUPi
.globl _Z12myHelloOnGPUPi
.p2align 8
.type _Z12myHelloOnGPUPi,@function
_Z12myHelloOnGPUPi: ; @_Z12myHelloOnGPUPi
; %bb.0:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x14
s_load_b64 s[0:1], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
v_mov_b32_e32 v2, 0
v_xad_u32 v3, v0, -1, s2
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v1
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v2, vcc_lo
global_store_b32 v[0:1], v3, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z12myHelloOnGPUPi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 264
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z12myHelloOnGPUPi, .Lfunc_end0-_Z12myHelloOnGPUPi
; -- End function
.section .AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 100
; NumSgprs: 18
; NumVgprs: 4
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 4
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object ; @__hip_cuid_
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0 ; 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: hidden_block_count_x
- .offset: 12
.size: 4
.value_kind: hidden_block_count_y
- .offset: 16
.size: 4
.value_kind: hidden_block_count_z
- .offset: 20
.size: 2
.value_kind: hidden_group_size_x
- .offset: 22
.size: 2
.value_kind: hidden_group_size_y
- .offset: 24
.size: 2
.value_kind: hidden_group_size_z
- .offset: 26
.size: 2
.value_kind: hidden_remainder_x
- .offset: 28
.size: 2
.value_kind: hidden_remainder_y
- .offset: 30
.size: 2
.value_kind: hidden_remainder_z
- .offset: 48
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 72
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 264
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z12myHelloOnGPUPi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z12myHelloOnGPUPi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
```
| 316 | 2,223 |
455 |
Convert the following CUDA host assembly code to AMD host assembly:
```cudaasm
.file "tmpxft_0017c903_00000000-6_task5.cudafe1.cpp"
.text
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z32__device_stub__Z12myHelloOnGPUPiPi
.type _Z32__device_stub__Z12myHelloOnGPUPiPi, @function
_Z32__device_stub__Z12myHelloOnGPUPiPi:
.LFB2082:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z12myHelloOnGPUPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z32__device_stub__Z12myHelloOnGPUPiPi, .-_Z32__device_stub__Z12myHelloOnGPUPiPi
.globl _Z12myHelloOnGPUPi
.type _Z12myHelloOnGPUPi, @function
_Z12myHelloOnGPUPi:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z12myHelloOnGPUPiPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z12myHelloOnGPUPi, .-_Z12myHelloOnGPUPi
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%d "
.LC1:
.string "\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $48, %rsp
.cfi_def_cfa_offset 80
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movl $64, %edi
call malloc@PLT
movq %rax, %rbp
leaq 8(%rsp), %rdi
movl $64, %esi
call cudaMalloc@PLT
movl $4, 28(%rsp)
movl $1, 32(%rsp)
movl $4, 16(%rsp)
movl $1, 20(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L17
.L12:
movl $2, %ecx
movl $64, %edx
movq 8(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
movq %rbp, %rbx
addq $64, %rbp
leaq .LC0(%rip), %r12
.L13:
movl (%rbx), %edx
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %rbp, %rbx
jne .L13
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L18
movl $0, %eax
addq $48, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L17:
.cfi_restore_state
movq 8(%rsp), %rdi
call _Z32__device_stub__Z12myHelloOnGPUPiPi
jmp .L12
.L18:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC2:
.string "_Z12myHelloOnGPUPi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z12myHelloOnGPUPi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
```
|
```amdasm
.text
.file "task5.hip"
.globl _Z27__device_stub__myHelloOnGPUPi # -- Begin function _Z27__device_stub__myHelloOnGPUPi
.type _Z27__device_stub__myHelloOnGPUPi,@function
_Z27__device_stub__myHelloOnGPUPi: # @_Z27__device_stub__myHelloOnGPUPi
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $64, %rsp
.cfi_def_cfa_offset 112
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 24(%rsp), %rax
movq %rdi, (%rax)
movq %rsp, %rbx
movq %rax, (%rbx)
leaq 48(%rsp), %r14
leaq 32(%rsp), %r15
leaq 16(%rsp), %r12
leaq 8(%rsp), %r13
movq %r14, %rdi
movq %r15, %rsi
movq %r12, %rdx
movq %r13, %rcx
callq __hipPopCallConfiguration
movq (%r14), %rsi
movl 8(%r14), %edx
movq (%r15), %rcx
movl 8(%r15), %r8d
movl $_Z12myHelloOnGPUPi, %edi
movq %rbx, %r9
pushq (%r13)
.cfi_adjust_cfa_offset 8
pushq (%r12)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $80, %rsp
.cfi_adjust_cfa_offset -80
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z27__device_stub__myHelloOnGPUPi, .Lfunc_end0-_Z27__device_stub__myHelloOnGPUPi
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
pushq %rax
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movl $64, %edi
callq malloc
movq %rax, %rbx
movq %rsp, %rdi
movl $64, %esi
callq hipMalloc
movabsq $4294967300, %rdi # imm = 0x100000004
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq (%rsp), %rdi
callq _Z27__device_stub__myHelloOnGPUPi
.LBB1_2:
movq (%rsp), %rsi
movl $64, %edx
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
xorl %r14d, %r14d
.LBB1_3: # =>This Inner Loop Header: Depth=1
movl (%rbx,%r14,4), %esi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
incq %r14
cmpq $16, %r14
jne .LBB1_3
# %bb.4:
movl $10, %edi
callq putchar@PLT
xorl %eax, %eax
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, %rdi
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12myHelloOnGPUPi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z12myHelloOnGPUPi,@object # @_Z12myHelloOnGPUPi
.section .rodata,"a",@progbits
.globl _Z12myHelloOnGPUPi
.p2align 3, 0x0
_Z12myHelloOnGPUPi:
.quad _Z27__device_stub__myHelloOnGPUPi
.size _Z12myHelloOnGPUPi, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%d "
.size .L.str, 4
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z12myHelloOnGPUPi"
.size .L__unnamed_1, 19
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z27__device_stub__myHelloOnGPUPi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z12myHelloOnGPUPi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
```
| 2,574 | 2,577 |
458 |
Convert the following CUDA device assembly code to AMD device assembly:
```cudaasm
code for sm_80
Function : _Z8copy_memPhS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ;
S2R R2, SR_CTAID.Y ;
ULDC.64 UR4, c[0x0][0x118] ;
S2R R3, SR_TID.Y ;
S2R R7, SR_CTAID.X ;
S2R R0, SR_TID.X ;
IMAD R2, R2, 0x20, R3 ;
IMAD R7, R2, c[0x0][0xc], R7 ;
IMAD R2, R7, 0x20, R0 ;
IMAD R4, R2, 0x3, RZ ;
SHF.R.S32.HI R5, RZ, 0x1f, R4 ;
IADD3 R2, P0, R4, c[0x0][0x160], RZ ;
IADD3.X R3, R5, c[0x0][0x164], RZ, P0, !PT ;
LDG.E.U8 R9, [R2.64] ;
IADD3 R4, P0, R4, c[0x0][0x168], RZ ;
IADD3.X R5, R5, c[0x0][0x16c], RZ, P0, !PT ;
STG.E.U8 [R4.64], R9 ;
LDG.E.U8 R11, [R2.64+0x1] ;
IMAD.MOV.U32 R12, RZ, RZ, c[0x0][0xc] ;
IMAD R15, R12, 0x8, R7 ;
IMAD R6, R15, 0x20, R0 ;
STG.E.U8 [R4.64+0x1], R11 ;
LDG.E.U8 R13, [R2.64+0x2] ;
IMAD R8, R6, 0x3, RZ ;
SHF.R.S32.HI R10, RZ, 0x1f, R8 ;
IADD3 R6, P0, R8, c[0x0][0x160], RZ ;
IADD3.X R7, R10, c[0x0][0x164], RZ, P0, !PT ;
STG.E.U8 [R4.64+0x2], R13 ;
LDG.E.U8 R17, [R6.64] ;
IADD3 R8, P0, R8, c[0x0][0x168], RZ ;
IADD3.X R9, R10, c[0x0][0x16c], RZ, P0, !PT ;
STG.E.U8 [R8.64], R17 ;
LDG.E.U8 R11, [R6.64+0x1] ;
IMAD R15, R12, 0x8, R15 ;
IMAD R2, R15, 0x20, R0 ;
IMAD R10, R2, 0x3, RZ ;
STG.E.U8 [R8.64+0x1], R11 ;
LDG.E.U8 R19, [R6.64+0x2] ;
SHF.R.S32.HI R5, RZ, 0x1f, R10 ;
IADD3 R2, P0, R10, c[0x0][0x160], RZ ;
IADD3.X R3, R5, c[0x0][0x164], RZ, P0, !PT ;
STG.E.U8 [R8.64+0x2], R19 ;
LDG.E.U8 R13, [R2.64] ;
IADD3 R4, P0, R10, c[0x0][0x168], RZ ;
IADD3.X R5, R5, c[0x0][0x16c], RZ, P0, !PT ;
STG.E.U8 [R4.64], R13 ;
LDG.E.U8 R11, [R2.64+0x1] ;
IMAD R15, R12, 0x8, R15 ;
IMAD R15, R15, 0x20, R0 ;
IMAD R15, R15, 0x3, RZ ;
STG.E.U8 [R4.64+0x1], R11 ;
LDG.E.U8 R17, [R2.64+0x2] ;
SHF.R.S32.HI R0, RZ, 0x1f, R15 ;
IADD3 R6, P0, R15, c[0x0][0x160], RZ ;
IADD3.X R7, R0, c[0x0][0x164], RZ, P0, !PT ;
STG.E.U8 [R4.64+0x2], R17 ;
LDG.E.U8 R13, [R6.64] ;
IADD3 R8, P0, R15, c[0x0][0x168], RZ ;
IADD3.X R9, R0, c[0x0][0x16c], RZ, P0, !PT ;
STG.E.U8 [R8.64], R13 ;
LDG.E.U8 R3, [R6.64+0x1] ;
STG.E.U8 [R8.64+0x1], R3 ;
LDG.E.U8 R11, [R6.64+0x2] ;
STG.E.U8 [R8.64+0x2], R11 ;
EXIT ;
BRA 0x410;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
```
|
```amdasm
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z8copy_memPhS_ ; -- Begin function _Z8copy_memPhS_
.globl _Z8copy_memPhS_
.p2align 8
.type _Z8copy_memPhS_,@function
_Z8copy_memPhS_: ; @_Z8copy_memPhS_
; %bb.0:
s_load_b32 s6, s[0:1], 0x10
v_bfe_u32 v1, v0, 10, 10
s_load_b128 s[0:3], s[0:1], 0x0
v_and_b32_e32 v0, 0x3ff, v0
s_lshl_b32 s4, s14, 5
s_mov_b32 s7, 0
v_lshl_add_u32 v1, s15, 5, v1
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mul_lo_u32 v1, s6, v1
s_mulk_i32 s6, 0x300
v_lshlrev_b32_e32 v1, 5, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add3_u32 v0, v0, v1, s4
v_lshl_add_u32 v0, v0, 1, v0
.LBB0_1: ; %.preheader
; =>This Loop Header: Depth=1
; Child Loop BB0_2 Depth 2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v4, 31, v0
v_add_co_u32 v1, vcc_lo, s0, v0
s_mov_b64 s[4:5], 0
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v4, vcc_lo
v_add_co_u32 v3, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v4, vcc_lo, s3, v4, vcc_lo
.LBB0_2: ; Parent Loop BB0_1 Depth=1
; => This Inner Loop Header: Depth=2
v_add_co_u32 v5, vcc_lo, v1, s4
s_delay_alu instid0(VALU_DEP_4)
v_add_co_ci_u32_e32 v6, vcc_lo, s5, v2, vcc_lo
global_load_u8 v7, v[5:6], off
v_add_co_u32 v5, vcc_lo, v3, s4
v_add_co_ci_u32_e32 v6, vcc_lo, s5, v4, vcc_lo
s_add_u32 s4, s4, 1
s_addc_u32 s5, s5, 0
s_cmp_eq_u32 s4, 3
s_waitcnt vmcnt(0)
global_store_b8 v[5:6], v7, off
s_cbranch_scc0 .LBB0_2
; %bb.3: ; in Loop: Header=BB0_1 Depth=1
v_add_nc_u32_e32 v0, s6, v0
s_add_i32 s4, s7, 8
s_cmp_gt_u32 s7, 23
s_mov_b32 s7, s4
s_cbranch_scc0 .LBB0_1
; %bb.4:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z8copy_memPhS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z8copy_memPhS_, .Lfunc_end0-_Z8copy_memPhS_
; -- End function
.section .AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 224
; NumSgprs: 18
; NumVgprs: 8
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 8
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object ; @__hip_cuid_
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0 ; 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z8copy_memPhS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z8copy_memPhS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
```
| 1,482 | 2,764 |
459 |
Convert the following CUDA host assembly code to AMD host assembly:
```cudaasm
.file "tmpxft_00096a1c_00000000-6_copy_mem.cudafe1.cpp"
.text
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z29__device_stub__Z8copy_memPhS_PhS_
.type _Z29__device_stub__Z8copy_memPhS_PhS_, @function
_Z29__device_stub__Z8copy_memPhS_PhS_:
.LFB2051:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z8copy_memPhS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z29__device_stub__Z8copy_memPhS_PhS_, .-_Z29__device_stub__Z8copy_memPhS_PhS_
.globl _Z8copy_memPhS_
.type _Z8copy_memPhS_, @function
_Z8copy_memPhS_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z8copy_memPhS_PhS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z8copy_memPhS_, .-_Z8copy_memPhS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z8copy_memPhS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z8copy_memPhS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
```
|
```amdasm
.text
.file "copy_mem.hip"
.globl _Z23__device_stub__copy_memPhS_ # -- Begin function _Z23__device_stub__copy_memPhS_
.type _Z23__device_stub__copy_memPhS_,@function
_Z23__device_stub__copy_memPhS_: # @_Z23__device_stub__copy_memPhS_
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $80, %rsp
.cfi_def_cfa_offset 128
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 24(%rsp), %rax
movq %rdi, (%rax)
leaq 16(%rsp), %rcx
movq %rsi, (%rcx)
leaq 64(%rsp), %rbx
movq %rax, (%rbx)
movq %rcx, 8(%rbx)
leaq 48(%rsp), %r14
leaq 32(%rsp), %r15
leaq 8(%rsp), %r12
movq %rsp, %r13
movq %r14, %rdi
movq %r15, %rsi
movq %r12, %rdx
movq %r13, %rcx
callq __hipPopCallConfiguration
movq (%r14), %rsi
movl 8(%r14), %edx
movq (%r15), %rcx
movl 8(%r15), %r8d
movl $_Z8copy_memPhS_, %edi
movq %rbx, %r9
pushq (%r13)
.cfi_adjust_cfa_offset 8
pushq (%r12)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $96, %rsp
.cfi_adjust_cfa_offset -96
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z23__device_stub__copy_memPhS_, .Lfunc_end0-_Z23__device_stub__copy_memPhS_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, %rdi
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8copy_memPhS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z8copy_memPhS_,@object # @_Z8copy_memPhS_
.section .rodata,"a",@progbits
.globl _Z8copy_memPhS_
.p2align 3, 0x0
_Z8copy_memPhS_:
.quad _Z23__device_stub__copy_memPhS_
.size _Z8copy_memPhS_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z8copy_memPhS_"
.size .L__unnamed_1, 16
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z23__device_stub__copy_memPhS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z8copy_memPhS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
```
| 1,754 | 1,945 |
460 |
Convert the following CUDA device assembly code to AMD device assembly:
```cudaasm
code for sm_80
Function : _Z10matrix_mulPfS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
MOV R1, c[0x0][0x28] ;
S2R R4, SR_CTAID.Y ;
MOV R0, c[0x0][0x178] ;
ULDC.64 UR4, c[0x0][0x118] ;
HFMA2.MMA R28, -RZ, RZ, 0, 0 ;
S2R R3, SR_TID.Y ;
ISETP.GE.AND P0, PT, R0, 0x1, PT ;
S2R R2, SR_CTAID.X ;
S2R R5, SR_TID.X ;
IMAD R4, R4, c[0x0][0x4], R3 ;
IMAD R4, R4, c[0x0][0x178], RZ ;
IMAD R2, R2, c[0x0][0x0], R5 ;
@!P0 BRA 0xbf0 ;
IADD3 R3, R0.reuse, -0x1, RZ ;
LOP3.LUT R5, R0, 0x3, RZ, 0xc0, !PT ;
ISETP.GE.U32.AND P0, PT, R3, 0x3, PT ;
MOV R28, RZ ;
MOV R3, RZ ;
@!P0 BRA 0xad0 ;
IADD3 R6, -R5, c[0x0][0x178], RZ ;
HFMA2.MMA R25, -RZ, RZ, 0, 2.384185791015625e-07 ;
ULDC.64 UR6, c[0x0][0x160] ;
HFMA2.MMA R3, -RZ, RZ, 0, 0 ;
ISETP.GT.AND P0, PT, R6, RZ, PT ;
MOV R28, RZ ;
IMAD.WIDE R24, R2, R25, c[0x0][0x168] ;
@!P0 BRA 0x940 ;
ISETP.GT.AND P1, PT, R6, 0xc, PT ;
PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ;
@!P1 BRA 0x680 ;
PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ;
MOV R12, UR6 ;
LDG.E R29, [R24.64] ;
MOV R13, UR7 ;
IMAD.WIDE R12, R4, 0x4, R12 ;
LDG.E R27, [R12.64] ;
IMAD.WIDE R10, R0, 0x4, R24 ;
LDG.E R17, [R12.64+0x4] ;
IMAD.WIDE R18, R0.reuse, 0x4, R10 ;
LDG.E R16, [R10.64] ;
LDG.E R7, [R12.64+0xc] ;
IMAD.WIDE R14, R0, 0x4, R18 ;
LDG.E R18, [R18.64] ;
IMAD.WIDE R20, R0.reuse, 0x4, R14 ;
LDG.E R26, [R14.64] ;
LDG.E R9, [R12.64+0x10] ;
LDG.E R19, [R12.64+0x8] ;
IMAD.WIDE R14, R0, 0x4, R20 ;
LDG.E R20, [R20.64] ;
IMAD.WIDE R22, R0.reuse, 0x4, R14 ;
LDG.E R8, [R14.64] ;
LDG.E R11, [R12.64+0x14] ;
IMAD.WIDE R24, R0, 0x4, R22 ;
LDG.E R10, [R22.64] ;
LDG.E R21, [R12.64+0x18] ;
FFMA R29, R29, R27, R28 ;
LDG.E R27, [R12.64+0x1c] ;
LDG.E R28, [R24.64] ;
IMAD.WIDE R14, R0, 0x4, R24 ;
FFMA R29, R16, R17, R29 ;
IMAD.WIDE R16, R0, 0x4, R14 ;
LDG.E R14, [R14.64] ;
FFMA R29, R18, R19, R29 ;
IMAD.WIDE R18, R0, 0x4, R16 ;
LDG.E R16, [R16.64] ;
FFMA R26, R26, R7, R29 ;
IMAD.WIDE R22, R0.reuse, 0x4, R18 ;
LDG.E R7, [R12.64+0x20] ;
LDG.E R29, [R12.64+0x24] ;
IMAD.WIDE R24, R0, 0x4, R22 ;
LDG.E R18, [R18.64] ;
FFMA R9, R20, R9, R26 ;
LDG.E R26, [R12.64+0x28] ;
FFMA R11, R8, R11, R9 ;
IMAD.WIDE R8, R0, 0x4, R24 ;
LDG.E R22, [R22.64] ;
LDG.E R17, [R12.64+0x2c] ;
FFMA R21, R10, R21, R11 ;
LDG.E R15, [R24.64] ;
IMAD.WIDE R10, R0, 0x4, R8 ;
LDG.E R19, [R8.64] ;
LDG.E R23, [R10.64] ;
LDG.E R24, [R12.64+0x30] ;
LDG.E R25, [R12.64+0x38] ;
LDG.E R8, [R12.64+0x3c] ;
FFMA R9, R28, R27, R21 ;
LDG.E R28, [R12.64+0x34] ;
IMAD.WIDE R20, R0, 0x4, R10 ;
LDG.E R27, [R20.64] ;
IADD3 R6, R6, -0x10, RZ ;
ISETP.GT.AND P1, PT, R6, 0xc, PT ;
FFMA R7, R14, R7, R9 ;
FFMA R7, R16, R29, R7 ;
FFMA R7, R18, R26, R7 ;
FFMA R7, R22, R17, R7 ;
UIADD3 UR6, UP0, UR6, 0x40, URZ ;
IADD3 R3, R3, 0x10, RZ ;
UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ;
FFMA R7, R15, R24, R7 ;
FFMA R28, R19, R28, R7 ;
FFMA R28, R23, R25, R28 ;
IMAD.WIDE R24, R0, 0x4, R20 ;
FFMA R28, R27, R8, R28 ;
@P1 BRA 0x1f0 ;
ISETP.GT.AND P1, PT, R6, 0x4, PT ;
@!P1 BRA 0x920 ;
IMAD.WIDE R16, R0, 0x4, R24 ;
MOV R8, UR6 ;
LDG.E R7, [R24.64] ;
MOV R9, UR7 ;
IMAD.WIDE R12, R0, 0x4, R16 ;
LDG.E R21, [R16.64] ;
IMAD.WIDE R8, R4, 0x4, R8 ;
LDG.E R23, [R12.64] ;
IMAD.WIDE R14, R0.reuse, 0x4, R12 ;
LDG.E R20, [R8.64] ;
LDG.E R22, [R8.64+0x4] ;
IMAD.WIDE R10, R0, 0x4, R14 ;
LDG.E R26, [R8.64+0x8] ;
IMAD.WIDE R16, R0.reuse, 0x4, R10 ;
LDG.E R14, [R14.64] ;
LDG.E R27, [R8.64+0xc] ;
IMAD.WIDE R18, R0, 0x4, R16 ;
LDG.E R10, [R10.64] ;
LDG.E R25, [R8.64+0x10] ;
IMAD.WIDE R12, R0, 0x4, R18 ;
LDG.E R16, [R16.64] ;
LDG.E R29, [R8.64+0x14] ;
LDG.E R24, [R18.64] ;
LDG.E R11, [R8.64+0x18] ;
LDG.E R15, [R12.64] ;
LDG.E R18, [R8.64+0x1c] ;
UIADD3 UR6, UP0, UR6, 0x20, URZ ;
PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ;
IADD3 R3, R3, 0x8, RZ ;
IADD3 R6, R6, -0x8, RZ ;
UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ;
FFMA R7, R7, R20, R28 ;
FFMA R7, R21, R22, R7 ;
FFMA R7, R23, R26, R7 ;
FFMA R7, R14, R27, R7 ;
FFMA R7, R10, R25, R7 ;
FFMA R7, R16, R29, R7 ;
FFMA R7, R24, R11, R7 ;
IMAD.WIDE R24, R0, 0x4, R12 ;
FFMA R28, R15, R18, R7 ;
ISETP.NE.OR P0, PT, R6, RZ, P0 ;
@!P0 BRA 0xad0 ;
MOV R8, UR6 ;
IMAD.WIDE R14, R0, 0x4, R24 ;
MOV R9, UR7 ;
LDG.E R25, [R24.64] ;
IMAD.WIDE R8, R4, 0x4, R8 ;
IMAD.WIDE R12, R0.reuse, 0x4, R14 ;
LDG.E R7, [R8.64] ;
LDG.E R14, [R14.64] ;
IMAD.WIDE R10, R0, 0x4, R12 ;
LDG.E R16, [R8.64+0x4] ;
LDG.E R18, [R12.64] ;
LDG.E R17, [R8.64+0x8] ;
LDG.E R19, [R8.64+0xc] ;
LDG.E R20, [R10.64] ;
IADD3 R6, R6, -0x4, RZ ;
ISETP.NE.AND P0, PT, R6, RZ, PT ;
UIADD3 UR6, UP0, UR6, 0x10, URZ ;
IADD3 R3, R3, 0x4, RZ ;
UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ;
FFMA R7, R25, R7, R28 ;
FFMA R7, R14, R16, R7 ;
IMAD.WIDE R24, R0, 0x4, R10 ;
FFMA R7, R18, R17, R7 ;
FFMA R28, R20, R19, R7 ;
@P0 BRA 0x940 ;
ISETP.NE.AND P0, PT, R5, RZ, PT ;
@!P0 BRA 0xbf0 ;
HFMA2.MMA R8, -RZ, RZ, 0, 2.384185791015625e-07 ;
IADD3 R6, R4, R3, RZ ;
IMAD R3, R3, c[0x0][0x178], R2 ;
IMAD.WIDE R6, R6, R8, c[0x0][0x160] ;
IMAD.WIDE R8, R3, R8, c[0x0][0x168] ;
MOV R10, R6 ;
MOV R6, R10 ;
LDG.E R3, [R8.64] ;
LDG.E R6, [R6.64] ;
IADD3 R5, R5, -0x1, RZ ;
IADD3 R10, P1, R10, 0x4, RZ ;
ISETP.NE.AND P0, PT, R5, RZ, PT ;
IMAD.WIDE R8, R0, 0x4, R8 ;
IADD3.X R7, RZ, R7, RZ, P1, !PT ;
FFMA R28, R3, R6, R28 ;
@P0 BRA 0xb50 ;
IADD3 R2, R2, R4, RZ ;
MOV R3, 0x4 ;
IMAD.WIDE R2, R2, R3, c[0x0][0x170] ;
STG.E [R2.64], R28 ;
EXIT ;
BRA 0xc40;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
```
|
```amdasm
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10matrix_mulPfS_S_i ; -- Begin function _Z10matrix_mulPfS_S_i
.globl _Z10matrix_mulPfS_S_i
.p2align 8
.type _Z10matrix_mulPfS_S_i,@function
_Z10matrix_mulPfS_S_i: ; @_Z10matrix_mulPfS_S_i
; %bb.0:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x2c
s_load_b32 s2, s[0:1], 0x18
v_bfe_u32 v1, v0, 10, 10
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_lshr_b32 s8, s3, 16
s_and_b32 s3, s3, 0xffff
v_mad_u64_u32 v[2:3], null, s15, s8, v[1:2]
v_and_b32_e32 v3, 0x3ff, v0
s_cmp_lt_i32 s2, 1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_mad_u64_u32 v[0:1], null, s14, s3, v[3:4]
v_mul_lo_u32 v1, v2, s2
s_cbranch_scc1 .LBB0_3
; %bb.1: ; %.lr.ph.preheader
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_ashrrev_i32_e32 v2, 31, v1
v_mov_b32_e32 v6, 0
v_mov_b32_e32 v4, v0
s_mov_b32 s3, s2
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[1:2]
v_add_co_u32 v2, vcc_lo, s4, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
.LBB0_2: ; %.lr.ph
; =>This Inner Loop Header: Depth=1
v_ashrrev_i32_e32 v5, 31, v4
s_add_i32 s3, s3, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_cmp_eq_u32 s3, 0
v_lshlrev_b64 v[7:8], 2, v[4:5]
v_add_nc_u32_e32 v4, s2, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v7, vcc_lo, s6, v7
v_add_co_ci_u32_e32 v8, vcc_lo, s7, v8, vcc_lo
global_load_b32 v5, v[2:3], off
global_load_b32 v7, v[7:8], off
v_add_co_u32 v2, vcc_lo, v2, 4
v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v6, v5, v7
s_cbranch_scc0 .LBB0_2
s_branch .LBB0_4
.LBB0_3:
v_mov_b32_e32 v6, 0
.LBB0_4: ; %Flow42
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v0, v1, v0
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[0:1]
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v6, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10matrix_mulPfS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10matrix_mulPfS_S_i, .Lfunc_end0-_Z10matrix_mulPfS_S_i
; -- End function
.section .AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 308
; NumSgprs: 18
; NumVgprs: 9
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 9
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object ; @__hip_cuid_
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0 ; 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10matrix_mulPfS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z10matrix_mulPfS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
```
| 3,582 | 3,170 |
461 |
Convert the following CUDA host assembly code to AMD host assembly:
```cudaasm
.file "tmpxft_00049ab7_00000000-6_matrix_mul.cudafe1.cpp"
.text
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z35__device_stub__Z10matrix_mulPfS_S_iPfS_S_i
.type _Z35__device_stub__Z10matrix_mulPfS_S_iPfS_S_i, @function
_Z35__device_stub__Z10matrix_mulPfS_S_iPfS_S_i:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z10matrix_mulPfS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z35__device_stub__Z10matrix_mulPfS_S_iPfS_S_i, .-_Z35__device_stub__Z10matrix_mulPfS_S_iPfS_S_i
.globl _Z10matrix_mulPfS_S_i
.type _Z10matrix_mulPfS_S_i, @function
_Z10matrix_mulPfS_S_i:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z10matrix_mulPfS_S_iPfS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z10matrix_mulPfS_S_i, .-_Z10matrix_mulPfS_S_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z10matrix_mulPfS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z10matrix_mulPfS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
```
|
```amdasm
.text
.file "matrix_mul.hip"
.globl _Z25__device_stub__matrix_mulPfS_S_i # -- Begin function _Z25__device_stub__matrix_mulPfS_S_i
.type _Z25__device_stub__matrix_mulPfS_S_i,@function
_Z25__device_stub__matrix_mulPfS_S_i: # @_Z25__device_stub__matrix_mulPfS_S_i
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $112, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 40(%rsp), %rax
movq %rdi, (%rax)
leaq 32(%rsp), %rdi
movq %rsi, (%rdi)
leaq 24(%rsp), %rsi
movq %rdx, (%rsi)
leaq 4(%rsp), %rdx
movl %ecx, (%rdx)
leaq 80(%rsp), %rbx
movq %rax, (%rbx)
movq %rdi, 8(%rbx)
movq %rsi, 16(%rbx)
movq %rdx, 24(%rbx)
leaq 64(%rsp), %r14
leaq 48(%rsp), %r15
leaq 16(%rsp), %r12
leaq 8(%rsp), %r13
movq %r14, %rdi
movq %r15, %rsi
movq %r12, %rdx
movq %r13, %rcx
callq __hipPopCallConfiguration
movq (%r14), %rsi
movl 8(%r14), %edx
movq (%r15), %rcx
movl 8(%r15), %r8d
movl $_Z10matrix_mulPfS_S_i, %edi
movq %rbx, %r9
pushq (%r13)
.cfi_adjust_cfa_offset 8
pushq (%r12)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $128, %rsp
.cfi_adjust_cfa_offset -128
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z25__device_stub__matrix_mulPfS_S_i, .Lfunc_end0-_Z25__device_stub__matrix_mulPfS_S_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, %rdi
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10matrix_mulPfS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10matrix_mulPfS_S_i,@object # @_Z10matrix_mulPfS_S_i
.section .rodata,"a",@progbits
.globl _Z10matrix_mulPfS_S_i
.p2align 3, 0x0
_Z10matrix_mulPfS_S_i:
.quad _Z25__device_stub__matrix_mulPfS_S_i
.size _Z10matrix_mulPfS_S_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z10matrix_mulPfS_S_i"
.size .L__unnamed_1, 22
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__matrix_mulPfS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10matrix_mulPfS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
```
| 1,903 | 2,083 |
462 |
Convert the following CUDA device assembly code to AMD device assembly:
```cudaasm
code for sm_80
Function : _Z3sumPfS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ;
S2R R0, SR_CTAID.X ;
ULDC.64 UR4, c[0x0][0x118] ;
BSSY B0, 0xf0 ;
S2R R3, SR_TID.X ;
IMAD R2, R0, c[0x0][0x0], R3 ;
ISETP.GT.AND P1, PT, R2.reuse, 0x3fff, PT ;
ISETP.GT.AND P0, PT, R2, 0x3eff, PT ;
ISETP.GT.OR P0, PT, R3, 0xff, P0 ;
@P1 BRA 0xe0 ;
IMAD.MOV.U32 R5, RZ, RZ, 0x4 ;
IMAD.WIDE R4, R2, R5, c[0x0][0x160] ;
LDG.E R4, [R4.64] ;
STS [R3.X4], R4 ;
BSYNC B0 ;
BAR.SYNC.DEFER_BLOCKING 0x0 ;
ISETP.GT.AND P1, PT, R2, 0x3f7f, PT ;
ISETP.GT.OR P1, PT, R3, 0x7f, P1 ;
@!P0 LDS R4, [R3.X4] ;
@!P0 LDS R5, [R3.X4+0x400] ;
@!P0 FADD R4, R4, R5 ;
@!P0 STS [R3.X4], R4 ;
BAR.SYNC.DEFER_BLOCKING 0x0 ;
ISETP.GT.AND P0, PT, R2, 0x3fbf, PT ;
ISETP.GT.OR P0, PT, R3, 0x3f, P0 ;
@!P1 LDS R5, [R3.X4] ;
@!P1 LDS R6, [R3.X4+0x200] ;
@!P1 FADD R6, R5, R6 ;
@!P1 STS [R3.X4], R6 ;
BAR.SYNC.DEFER_BLOCKING 0x0 ;
ISETP.GT.AND P1, PT, R2, 0x3fdf, PT ;
ISETP.GT.OR P1, PT, R3, 0x1f, P1 ;
@!P0 LDS R5, [R3.X4] ;
@!P0 LDS R8, [R3.X4+0x100] ;
@!P0 FADD R8, R5, R8 ;
@!P0 STS [R3.X4], R8 ;
BAR.SYNC.DEFER_BLOCKING 0x0 ;
ISETP.GT.AND P0, PT, R2, 0x3fef, PT ;
ISETP.GT.OR P0, PT, R3, 0xf, P0 ;
@!P1 LDS R4, [R3.X4] ;
@!P1 LDS R5, [R3.X4+0x80] ;
@!P1 FADD R4, R4, R5 ;
@!P1 STS [R3.X4], R4 ;
BAR.SYNC.DEFER_BLOCKING 0x0 ;
ISETP.GT.AND P1, PT, R2, 0x3ff7, PT ;
ISETP.GT.OR P1, PT, R3, 0x7, P1 ;
@!P0 LDS R5, [R3.X4] ;
@!P0 LDS R6, [R3.X4+0x40] ;
@!P0 FADD R6, R5, R6 ;
@!P0 STS [R3.X4], R6 ;
BAR.SYNC.DEFER_BLOCKING 0x0 ;
ISETP.GT.AND P0, PT, R2, 0x3ffb, PT ;
ISETP.GT.OR P0, PT, R3, 0x3, P0 ;
@!P1 LDS R5, [R3.X4] ;
@!P1 LDS R8, [R3.X4+0x20] ;
@!P1 FADD R8, R5, R8 ;
@!P1 STS [R3.X4], R8 ;
BAR.SYNC.DEFER_BLOCKING 0x0 ;
ISETP.GT.AND P1, PT, R2, 0x3ffd, PT ;
ISETP.GT.OR P1, PT, R3, 0x1, P1 ;
@!P0 LDS R4, [R3.X4] ;
@!P0 LDS R5, [R3.X4+0x10] ;
@!P0 FADD R4, R4, R5 ;
@!P0 STS [R3.X4], R4 ;
BAR.SYNC.DEFER_BLOCKING 0x0 ;
ISETP.GT.AND P0, PT, R2, 0x3ffe, PT ;
ISETP.GT.OR P0, PT, R3, RZ, P0 ;
@!P1 LDS R5, [R3.X4] ;
@!P1 LDS R6, [R3.X4+0x8] ;
@!P1 FADD R6, R5, R6 ;
@!P1 STS [R3.X4], R6 ;
BAR.SYNC.DEFER_BLOCKING 0x0 ;
ISETP.NE.AND P1, PT, R3, RZ, PT ;
@!P0 LDS R2, [R3.X4] ;
@!P0 LDS R5, [R3.X4+0x4] ;
@!P0 FADD R2, R2, R5 ;
@!P0 STS [R3.X4], R2 ;
BAR.SYNC.DEFER_BLOCKING 0x0 ;
@P1 EXIT ;
LDS R5, [RZ] ;
IMAD.MOV.U32 R3, RZ, RZ, 0x4 ;
IMAD.WIDE.U32 R2, R0, R3, c[0x0][0x168] ;
STG.E [R2.64], R5 ;
EXIT ;
BRA 0x540;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
```
|
```amdasm
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3sumPfS_ ; -- Begin function _Z3sumPfS_
.globl _Z3sumPfS_
.p2align 8
.type _Z3sumPfS_,@function
_Z3sumPfS_: ; @_Z3sumPfS_
; %bb.0:
s_clause 0x1
s_load_b32 s5, s[0:1], 0x1c
s_load_b128 s[0:3], s[0:1], 0x0
s_mov_b32 s4, s15
v_lshlrev_b32_e32 v3, 2, v0
s_waitcnt lgkmcnt(0)
s_and_b32 s5, s5, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s4, s5, v[0:1]
s_mov_b32 s5, exec_lo
v_cmpx_gt_i32_e32 0x4000, v1
s_cbranch_execz .LBB0_2
; %bb.1:
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[4:5], 2, v[1:2]
v_add_co_u32 v4, vcc_lo, s0, v4
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v5, vcc_lo, s1, v5, vcc_lo
global_load_b32 v2, v[4:5], off
s_waitcnt vmcnt(0)
ds_store_b32 v3, v2
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s5
v_cmp_gt_u32_e32 vcc_lo, 0x100, v0
v_cmp_gt_i32_e64 s0, 0x3f00, v1
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_and_b32 s1, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s0, s1
s_cbranch_execz .LBB0_4
; %bb.3:
ds_load_2addr_stride64_b32 v[4:5], v3 offset1:4
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v2, v5, v4
ds_store_b32 v3, v2
.LBB0_4:
s_or_b32 exec_lo, exec_lo, s0
v_cmp_gt_u32_e32 vcc_lo, 0x80, v0
v_cmp_gt_i32_e64 s0, 0x3f80, v1
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_and_b32 s1, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s0, s1
s_cbranch_execz .LBB0_6
; %bb.5:
ds_load_2addr_stride64_b32 v[4:5], v3 offset1:2
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v2, v5, v4
ds_store_b32 v3, v2
.LBB0_6:
s_or_b32 exec_lo, exec_lo, s0
v_cmp_gt_u32_e32 vcc_lo, 64, v0
v_cmp_gt_i32_e64 s0, 0x3fc0, v1
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_and_b32 s1, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s0, s1
s_cbranch_execz .LBB0_8
; %bb.7:
ds_load_2addr_stride64_b32 v[4:5], v3 offset1:1
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v2, v5, v4
ds_store_b32 v3, v2
.LBB0_8:
s_or_b32 exec_lo, exec_lo, s0
v_cmp_gt_u32_e32 vcc_lo, 32, v0
v_cmp_gt_i32_e64 s0, 0x3fe0, v1
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_and_b32 s1, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s0, s1
s_cbranch_execz .LBB0_10
; %bb.9:
ds_load_2addr_b32 v[4:5], v3 offset1:32
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v2, v5, v4
ds_store_b32 v3, v2
.LBB0_10:
s_or_b32 exec_lo, exec_lo, s0
v_cmp_gt_u32_e32 vcc_lo, 16, v0
v_cmp_gt_i32_e64 s0, 0x3ff0, v1
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_and_b32 s1, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s0, s1
s_cbranch_execz .LBB0_12
; %bb.11:
ds_load_2addr_b32 v[4:5], v3 offset1:16
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v2, v5, v4
ds_store_b32 v3, v2
.LBB0_12:
s_or_b32 exec_lo, exec_lo, s0
v_cmp_gt_u32_e32 vcc_lo, 8, v0
v_cmp_gt_i32_e64 s0, 0x3ff8, v1
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_and_b32 s1, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s0, s1
s_cbranch_execz .LBB0_14
; %bb.13:
ds_load_2addr_b32 v[4:5], v3 offset1:8
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v2, v5, v4
ds_store_b32 v3, v2
.LBB0_14:
s_or_b32 exec_lo, exec_lo, s0
v_cmp_gt_u32_e32 vcc_lo, 4, v0
v_cmp_gt_i32_e64 s0, 0x3ffc, v1
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_and_b32 s1, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s0, s1
s_cbranch_execz .LBB0_16
; %bb.15:
ds_load_2addr_b32 v[4:5], v3 offset1:4
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v2, v5, v4
ds_store_b32 v3, v2
.LBB0_16:
s_or_b32 exec_lo, exec_lo, s0
v_cmp_gt_u32_e32 vcc_lo, 2, v0
v_cmp_gt_i32_e64 s0, 0x3ffe, v1
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_and_b32 s1, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s0, s1
s_cbranch_execz .LBB0_18
; %bb.17:
ds_load_2addr_b32 v[4:5], v3 offset1:2
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v2, v5, v4
ds_store_b32 v3, v2
.LBB0_18:
s_or_b32 exec_lo, exec_lo, s0
v_cmp_eq_u32_e32 vcc_lo, 0, v0
v_cmp_gt_i32_e64 s0, 0x3fff, v1
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_and_b32 s1, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s0, s1
s_cbranch_execz .LBB0_20
; %bb.19:
v_mov_b32_e32 v2, 0
ds_load_b64 v[0:1], v2
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v0, v1, v0
ds_store_b32 v2, v0
.LBB0_20:
s_or_b32 exec_lo, exec_lo, s0
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_and_saveexec_b32 s0, vcc_lo
s_cbranch_execz .LBB0_22
; %bb.21:
v_mov_b32_e32 v0, 0
s_mov_b32 s5, 0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_lshl_b64 s[0:1], s[4:5], 2
s_add_u32 s0, s2, s0
ds_load_b32 v1, v0
s_addc_u32 s1, s3, s1
s_waitcnt lgkmcnt(0)
global_store_b32 v0, v1, s[0:1]
.LBB0_22:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3sumPfS_
.amdhsa_group_segment_fixed_size 2048
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3sumPfS_, .Lfunc_end0-_Z3sumPfS_
; -- End function
.section .AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 900
; NumSgprs: 18
; NumVgprs: 6
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 2048 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 6
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object ; @__hip_cuid_
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0 ; 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 2048
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3sumPfS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z3sumPfS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
```
| 1,507 | 4,391 |
463 |
Convert the following CUDA host assembly code to AMD host assembly:
```cudaasm
.file "tmpxft_000a9c00_00000000-6_q2.cudafe1.cpp"
.text
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z13random_floatsPfi
.type _Z13random_floatsPfi, @function
_Z13random_floatsPfi:
.LFB2057:
.cfi_startproc
endbr64
testl %esi, %esi
jle .L8
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
movq %rdi, %rbx
movslq %esi, %rsi
leaq (%rdi,%rsi,4), %rbp
.L5:
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
mulss .LC0(%rip), %xmm0
mulss .LC1(%rip), %xmm0
movss %xmm0, (%rbx)
addq $4, %rbx
cmpq %rbp, %rbx
jne .L5
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L8:
.cfi_restore 3
.cfi_restore 6
ret
.cfi_endproc
.LFE2057:
.size _Z13random_floatsPfi, .-_Z13random_floatsPfi
.section .rodata.str1.1,"aMS",@progbits,1
.LC3:
.string "Sequential Sum = %f\n"
.text
.globl _Z8checkSumPff
.type _Z8checkSumPff, @function
_Z8checkSumPff:
.LFB2058:
.cfi_startproc
endbr64
subq $24, %rsp
.cfi_def_cfa_offset 32
movss %xmm0, 12(%rsp)
movq %rdi, %rax
leaq 65536(%rdi), %rdx
movl $0x00000000, 8(%rsp)
.L12:
movss 8(%rsp), %xmm1
addss (%rax), %xmm1
movss %xmm1, 8(%rsp)
addq $4, %rax
cmpq %rdx, %rax
jne .L12
pxor %xmm0, %xmm0
cvtss2sd %xmm1, %xmm0
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movss 8(%rsp), %xmm0
subss 12(%rsp), %xmm0
andps .LC4(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
comisd .LC5(%rip), %xmm0
setbe %al
movzbl %al, %eax
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size _Z8checkSumPff, .-_Z8checkSumPff
.globl _Z24__device_stub__Z3sumPfS_PfS_
.type _Z24__device_stub__Z3sumPfS_PfS_, @function
_Z24__device_stub__Z3sumPfS_PfS_:
.LFB2084:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L19
.L15:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L20
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z3sumPfS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L15
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z24__device_stub__Z3sumPfS_PfS_, .-_Z24__device_stub__Z3sumPfS_PfS_
.globl _Z3sumPfS_
.type _Z3sumPfS_, @function
_Z3sumPfS_:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z24__device_stub__Z3sumPfS_PfS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z3sumPfS_, .-_Z3sumPfS_
.section .rodata.str1.1
.LC6:
.string "Final Sum = %f\n"
.text
.globl main
.type main, @function
main:
.LFB2059:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $72, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl $65536, %edi
call malloc@PLT
movq %rax, %rbp
movl $128, %edi
call malloc@PLT
movq %rax, %rbx
movl $16384, %esi
movq %rbp, %rdi
call _Z13random_floatsPfi
leaq 16(%rsp), %rdi
movl $65536, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $128, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $65536, %edx
movq %rbp, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $512, 44(%rsp)
movl $1, 48(%rsp)
movl $32, 32(%rsp)
movl $1, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L29
.L24:
movl $2, %ecx
movl $128, %edx
movq 24(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
movq %rbx, %rax
leaq 128(%rbx), %rdx
movl $0x00000000, 12(%rsp)
.L25:
movss 12(%rsp), %xmm1
addss (%rax), %xmm1
movss %xmm1, 12(%rsp)
addq $4, %rax
cmpq %rdx, %rax
jne .L25
pxor %xmm0, %xmm0
cvtss2sd %xmm1, %xmm0
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movss 12(%rsp), %xmm0
movq %rbp, %rdi
call _Z8checkSumPff
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L30
movl $0, %eax
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L29:
.cfi_restore_state
movq 24(%rsp), %rsi
movq 16(%rsp), %rdi
call _Z24__device_stub__Z3sumPfS_PfS_
jmp .L24
.L30:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size main, .-main
.section .rodata.str1.1
.LC7:
.string "_Z3sumPfS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _Z3sumPfS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC0:
.long 805306368
.align 4
.LC1:
.long 1084227584
.section .rodata.cst16,"aM",@progbits,16
.align 16
.LC4:
.long 2147483647
.long 0
.long 0
.long 0
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC5:
.long -1717986918
.long 1069128089
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
```
|
```amdasm
.text
.file "q2.hip"
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function _Z13random_floatsPfi
.LCPI0_0:
.long 0x30000000 # float 4.65661287E-10
.LCPI0_1:
.long 0x40a00000 # float 5
.text
.globl _Z13random_floatsPfi
.type _Z13random_floatsPfi,@function
_Z13random_floatsPfi: # @_Z13random_floatsPfi
.cfi_startproc
# %bb.0:
testl %esi, %esi
jle .LBB0_4
# %bb.1: # %.lr.ph.preheader
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rdi, %rbx
movl %esi, %r14d
xorl %r15d, %r15d
.LBB0_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
callq rand
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
mulss .LCPI0_0(%rip), %xmm0
mulss .LCPI0_1(%rip), %xmm0
movss %xmm0, (%rbx,%r15,4)
incq %r15
cmpq %r15, %r14
jne .LBB0_2
# %bb.3:
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r14
.cfi_restore %r15
.LBB0_4: # %._crit_edge
retq
.Lfunc_end0:
.size _Z13random_floatsPfi, .Lfunc_end0-_Z13random_floatsPfi
.cfi_endproc
# -- End function
.globl _Z18__device_stub__sumPfS_ # -- Begin function _Z18__device_stub__sumPfS_
.type _Z18__device_stub__sumPfS_,@function
_Z18__device_stub__sumPfS_: # @_Z18__device_stub__sumPfS_
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $80, %rsp
.cfi_def_cfa_offset 128
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 24(%rsp), %rax
movq %rdi, (%rax)
leaq 16(%rsp), %rcx
movq %rsi, (%rcx)
leaq 64(%rsp), %rbx
movq %rax, (%rbx)
movq %rcx, 8(%rbx)
leaq 48(%rsp), %r14
leaq 32(%rsp), %r15
leaq 8(%rsp), %r12
movq %rsp, %r13
movq %r14, %rdi
movq %r15, %rsi
movq %r12, %rdx
movq %r13, %rcx
callq __hipPopCallConfiguration
movq (%r14), %rsi
movl 8(%r14), %edx
movq (%r15), %rcx
movl 8(%r15), %r8d
movl $_Z3sumPfS_, %edi
movq %rbx, %r9
pushq (%r13)
.cfi_adjust_cfa_offset 8
pushq (%r12)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $96, %rsp
.cfi_adjust_cfa_offset -96
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z18__device_stub__sumPfS_, .Lfunc_end1-_Z18__device_stub__sumPfS_
.cfi_endproc
# -- End function
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0 # -- Begin function _Z8checkSumPff
.LCPI2_0:
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0
.LCPI2_1:
.quad 0x3fb999999999999a # double 0.10000000000000001
.text
.globl _Z8checkSumPff
.type _Z8checkSumPff,@function
_Z8checkSumPff: # @_Z8checkSumPff
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
movss %xmm0, 12(%rsp) # 4-byte Spill
xorps %xmm0, %xmm0
xorl %eax, %eax
.LBB2_1: # =>This Inner Loop Header: Depth=1
addss (%rdi,%rax,4), %xmm0
incq %rax
cmpq $16384, %rax # imm = 0x4000
jne .LBB2_1
# %bb.2:
movaps %xmm0, 16(%rsp) # 16-byte Spill
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
movaps 16(%rsp), %xmm0 # 16-byte Reload
subss 12(%rsp), %xmm0 # 4-byte Folded Reload
andps .LCPI2_0(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
xorl %eax, %eax
ucomisd .LCPI2_1(%rip), %xmm0
setbe %al
addq $40, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size _Z8checkSumPff, .Lfunc_end2-_Z8checkSumPff
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI3_0:
.long 0x30000000 # float 4.65661287E-10
.LCPI3_1:
.long 0x40a00000 # float 5
.text
.globl main
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $32, %rsp
.cfi_def_cfa_offset 64
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $65536, %edi # imm = 0x10000
callq malloc
movq %rax, %rbx
movl $128, %edi
callq malloc
movq %rax, %r14
xorl %r15d, %r15d
.LBB3_1: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
callq rand
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
mulss .LCPI3_0(%rip), %xmm0
mulss .LCPI3_1(%rip), %xmm0
movss %xmm0, (%rbx,%r15,4)
incq %r15
cmpq $16384, %r15 # imm = 0x4000
jne .LBB3_1
# %bb.2: # %_Z13random_floatsPfi.exit
leaq 24(%rsp), %r15
movl $65536, %esi # imm = 0x10000
movq %r15, %rdi
callq hipMalloc
leaq 16(%rsp), %rdi
movl $128, %esi
callq hipMalloc
movq (%r15), %rdi
movl $65536, %edx # imm = 0x10000
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $4294967328, %rdi # imm = 0x100000020
leaq 480(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_4
# %bb.3:
movq 24(%rsp), %rdi
movq 16(%rsp), %rsi
callq _Z18__device_stub__sumPfS_
.LBB3_4:
movq 16(%rsp), %rsi
movl $128, %edx
movq %r14, %rdi
movl $2, %ecx
callq hipMemcpy
xorps %xmm0, %xmm0
xorl %eax, %eax
.LBB3_5: # =>This Inner Loop Header: Depth=1
addss (%r14,%rax,4), %xmm0
incq %rax
cmpq $32, %rax
jne .LBB3_5
# %bb.6:
movss %xmm0, 12(%rsp) # 4-byte Spill
cvtss2sd %xmm0, %xmm0
movl $.L.str.1, %edi
movb $1, %al
callq printf
movq %rbx, %rdi
movss 12(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
callq _Z8checkSumPff
xorl %eax, %eax
addq $32, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, %rdi
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3sumPfS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3sumPfS_,@object # @_Z3sumPfS_
.section .rodata,"a",@progbits
.globl _Z3sumPfS_
.p2align 3, 0x0
_Z3sumPfS_:
.quad _Z18__device_stub__sumPfS_
.size _Z3sumPfS_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Sequential Sum = %f\n"
.size .L.str, 21
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Final Sum = %f\n"
.size .L.str.1, 16
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z3sumPfS_"
.size .L__unnamed_1, 11
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__sumPfS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3sumPfS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
```
| 3,758 | 4,457 |
466 |
Convert the following CUDA device assembly code to AMD device assembly:
```cudaasm
code for sm_80
Function : _Z10add_kernelPiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ;
IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x160] ;
MOV R5, c[0x0][0x16c] ;
IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x168] ;
MOV R3, c[0x0][0x164] ;
ULDC.64 UR4, c[0x0][0x118] ;
LDG.E R5, [R4.64] ;
LDG.E R2, [R2.64] ;
IMAD.MOV.U32 R6, RZ, RZ, c[0x0][0x170] ;
MOV R7, c[0x0][0x174] ;
IADD3 R9, R2, R5, RZ ;
STG.E [R6.64], R9 ;
EXIT ;
BRA 0xd0;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
```
|
```amdasm
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10add_kernelPiS_S_ ; -- Begin function _Z10add_kernelPiS_S_
.globl _Z10add_kernelPiS_S_
.p2align 8
.type _Z10add_kernelPiS_S_,@function
_Z10add_kernelPiS_S_: ; @_Z10add_kernelPiS_S_
; %bb.0:
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_load_b32 s2, s[4:5], 0x0
s_load_b32 s3, s[6:7], 0x0
s_waitcnt lgkmcnt(0)
s_add_i32 s2, s3, s2
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
global_store_b32 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10add_kernelPiS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 8
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10add_kernelPiS_S_, .Lfunc_end0-_Z10add_kernelPiS_S_
; -- End function
.section .AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 80
; NumSgprs: 8
; NumVgprs: 2
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 0
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 8
; NumVGPRsForWavesPerEU: 2
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object ; @__hip_cuid_
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0 ; 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10add_kernelPiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 8
.sgpr_spill_count: 0
.symbol: _Z10add_kernelPiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
```
| 342 | 1,805 |
467 |
Convert the following CUDA host assembly code to AMD host assembly:
```cudaasm
.file "tmpxft_001b61ab_00000000-6_k_add.cudafe1.cpp"
.text
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z34__device_stub__Z10add_kernelPiS_S_PiS_S_
.type _Z34__device_stub__Z10add_kernelPiS_S_PiS_S_, @function
_Z34__device_stub__Z10add_kernelPiS_S_PiS_S_:
.LFB2082:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z10add_kernelPiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z34__device_stub__Z10add_kernelPiS_S_PiS_S_, .-_Z34__device_stub__Z10add_kernelPiS_S_PiS_S_
.globl _Z10add_kernelPiS_S_
.type _Z10add_kernelPiS_S_, @function
_Z10add_kernelPiS_S_:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z34__device_stub__Z10add_kernelPiS_S_PiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z10add_kernelPiS_S_, .-_Z10add_kernelPiS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "res: %d\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
movl $4, (%rsp)
movl $2, 4(%rsp)
movq %rsp, %rsi
movl $1, %ecx
movl $4, %edx
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
leaq 4(%rsp), %rsi
movl $1, %ecx
movl $4, %edx
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L15
.L12:
leaq 44(%rsp), %rdi
movl $2, %ecx
movl $4, %edx
movq 24(%rsp), %rsi
call cudaMemcpy@PLT
movl 44(%rsp), %edx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L16
movl $0, %eax
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z34__device_stub__Z10add_kernelPiS_S_PiS_S_
jmp .L12
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC1:
.string "_Z10add_kernelPiS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z10add_kernelPiS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
```
|
```amdasm
.text
.file "k_add.hip"
.globl _Z25__device_stub__add_kernelPiS_S_ # -- Begin function _Z25__device_stub__add_kernelPiS_S_
.type _Z25__device_stub__add_kernelPiS_S_,@function
_Z25__device_stub__add_kernelPiS_S_: # @_Z25__device_stub__add_kernelPiS_S_
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $112, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 40(%rsp), %rax
movq %rdi, (%rax)
leaq 32(%rsp), %rcx
movq %rsi, (%rcx)
leaq 24(%rsp), %rsi
movq %rdx, (%rsi)
leaq 80(%rsp), %rbx
movq %rax, (%rbx)
movq %rcx, 8(%rbx)
movq %rsi, 16(%rbx)
leaq 64(%rsp), %r14
leaq 48(%rsp), %r15
leaq 16(%rsp), %r12
leaq 8(%rsp), %r13
movq %r14, %rdi
movq %r15, %rsi
movq %r12, %rdx
movq %r13, %rcx
callq __hipPopCallConfiguration
movq (%r14), %rsi
movl 8(%r14), %edx
movq (%r15), %rcx
movl 8(%r15), %r8d
movl $_Z10add_kernelPiS_S_, %edi
movq %rbx, %r9
pushq (%r13)
.cfi_adjust_cfa_offset 8
pushq (%r12)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $128, %rsp
.cfi_adjust_cfa_offset -128
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z25__device_stub__add_kernelPiS_S_, .Lfunc_end0-_Z25__device_stub__add_kernelPiS_S_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $48, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 24(%rsp), %rbx
movl $4, %esi
movq %rbx, %rdi
callq hipMalloc
leaq 16(%rsp), %r14
movl $4, %esi
movq %r14, %rdi
callq hipMalloc
leaq 8(%rsp), %rdi
movl $4, %esi
callq hipMalloc
leaq 44(%rsp), %rsi
movl $4, (%rsi)
leaq 40(%rsp), %r15
movl $2, (%r15)
movq (%rbx), %rdi
movl $4, %edx
movl $1, %ecx
callq hipMemcpy
movq (%r14), %rdi
movl $4, %edx
movq %r15, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq 24(%rsp), %rdi
movq 16(%rsp), %rsi
movq 8(%rsp), %rdx
callq _Z25__device_stub__add_kernelPiS_S_
.LBB1_2:
movq 8(%rsp), %rsi
leaq 36(%rsp), %rbx
movl $4, %edx
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
movl (%rbx), %esi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $48, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, %rdi
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10add_kernelPiS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10add_kernelPiS_S_,@object # @_Z10add_kernelPiS_S_
.section .rodata,"a",@progbits
.globl _Z10add_kernelPiS_S_
.p2align 3, 0x0
_Z10add_kernelPiS_S_:
.quad _Z25__device_stub__add_kernelPiS_S_
.size _Z10add_kernelPiS_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "res: %d\n"
.size .L.str, 9
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z10add_kernelPiS_S_"
.size .L__unnamed_1, 21
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__add_kernelPiS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10add_kernelPiS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
```
| 2,644 | 2,886 |
474 |
Convert the following CUDA device assembly code to AMD device assembly:
```cudaasm
code for sm_80
Function : _Z5task2Pi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
MOV R1, c[0x0][0x28] ;
S2R R5, SR_TID.X ;
HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ;
ULDC.64 UR4, c[0x0][0x118] ;
S2R R0, SR_CTAID.X ;
IMAD R2, R0, c[0x0][0x0], R5 ;
IADD3 R5, R5, R0, RZ ;
IMAD.WIDE R2, R2, R3, c[0x0][0x160] ;
STG.E [R2.64], R5 ;
EXIT ;
BRA 0xa0;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
```
|
```amdasm
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z5task2Pi ; -- Begin function _Z5task2Pi
.globl _Z5task2Pi
.p2align 8
.type _Z5task2Pi,@function
_Z5task2Pi: ; @_Z5task2Pi
; %bb.0:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x14
s_load_b64 s[0:1], s[0:1], 0x0
v_add_nc_u32_e32 v3, s15, v0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[1:2], 2, v[1:2]
v_add_co_u32 v0, vcc_lo, s0, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v2, vcc_lo
global_store_b32 v[0:1], v3, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z5task2Pi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 264
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z5task2Pi, .Lfunc_end0-_Z5task2Pi
; -- End function
.section .AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 100
; NumSgprs: 18
; NumVgprs: 4
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 4
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object ; @__hip_cuid_
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0 ; 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: hidden_block_count_x
- .offset: 12
.size: 4
.value_kind: hidden_block_count_y
- .offset: 16
.size: 4
.value_kind: hidden_block_count_z
- .offset: 20
.size: 2
.value_kind: hidden_group_size_x
- .offset: 22
.size: 2
.value_kind: hidden_group_size_y
- .offset: 24
.size: 2
.value_kind: hidden_group_size_z
- .offset: 26
.size: 2
.value_kind: hidden_remainder_x
- .offset: 28
.size: 2
.value_kind: hidden_remainder_y
- .offset: 30
.size: 2
.value_kind: hidden_remainder_z
- .offset: 48
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 72
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 264
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z5task2Pi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z5task2Pi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
```
| 278 | 2,200 |
475 |
Convert the following CUDA host assembly code to AMD host assembly:
```cudaasm
.file "tmpxft_000bdbb5_00000000-6_task2.cudafe1.cpp"
.text
.globl _ZSt21ios_base_library_initv
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z24__device_stub__Z5task2PiPi
.type _Z24__device_stub__Z5task2PiPi, @function
_Z24__device_stub__Z5task2PiPi:
.LFB3694:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z5task2Pi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3694:
.size _Z24__device_stub__Z5task2PiPi, .-_Z24__device_stub__Z5task2PiPi
.globl _Z5task2Pi
.type _Z5task2Pi, @function
_Z5task2Pi:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z24__device_stub__Z5task2PiPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _Z5task2Pi, .-_Z5task2Pi
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string " "
.text
.globl main
.type main, @function
main:
.LFB3669:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $48, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movl $64, %edi
call _Znam@PLT
movq %rax, %r14
leaq 8(%rsp), %rdi
movl $64, %esi
call cudaMalloc@PLT
movl $8, 28(%rsp)
movl $1, 32(%rsp)
movl $2, 16(%rsp)
movl $1, 20(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L17
.L12:
call cudaDeviceSynchronize@PLT
movl $2, %ecx
movl $64, %edx
movq 8(%rsp), %rsi
movq %r14, %rdi
call cudaMemcpy@PLT
leaq 4(%r14), %rbx
leaq 64(%r14), %r13
leaq _ZSt4cout(%rip), %r12
leaq .LC0(%rip), %rbp
.L13:
movl (%rbx), %esi
movq %r12, %rdi
call _ZNSolsEi@PLT
movq %rax, %rdi
movl $1, %edx
movq %rbp, %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
addq $4, %rbx
cmpq %rbx, %r13
jne .L13
leaq _ZSt4cout(%rip), %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq %r14, %rdi
call _ZdaPv@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L18
movl $0, %eax
addq $48, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L17:
.cfi_restore_state
movq 8(%rsp), %rdi
call _Z24__device_stub__Z5task2PiPi
jmp .L12
.L18:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size main, .-main
.section .rodata.str1.1
.LC1:
.string "_Z5task2Pi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3697:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z5task2Pi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
```
|
```amdasm
.text
.file "task2.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z20__device_stub__task2Pi # -- Begin function _Z20__device_stub__task2Pi
.type _Z20__device_stub__task2Pi,@function
_Z20__device_stub__task2Pi: # @_Z20__device_stub__task2Pi
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $64, %rsp
.cfi_def_cfa_offset 112
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 24(%rsp), %rax
movq %rdi, (%rax)
movq %rsp, %rbx
movq %rax, (%rbx)
leaq 48(%rsp), %r14
leaq 32(%rsp), %r15
leaq 16(%rsp), %r12
leaq 8(%rsp), %r13
movq %r14, %rdi
movq %r15, %rsi
movq %r12, %rdx
movq %r13, %rcx
callq __hipPopCallConfiguration
movq (%r14), %rsi
movl 8(%r14), %edx
movq (%r15), %rcx
movl 8(%r15), %r8d
movl $_Z5task2Pi, %edi
movq %rbx, %r9
pushq (%r13)
.cfi_adjust_cfa_offset 8
pushq (%r12)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $80, %rsp
.cfi_adjust_cfa_offset -80
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z20__device_stub__task2Pi, .Lfunc_end0-_Z20__device_stub__task2Pi
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
pushq %rax
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movl $64, %edi
callq _Znam
movq %rax, %rbx
movq %rsp, %rdi
movl $64, %esi
callq hipMalloc
movabsq $4294967298, %rdi # imm = 0x100000002
leaq 6(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq (%rsp), %rdi
callq _Z20__device_stub__task2Pi
.LBB1_2:
callq hipDeviceSynchronize
movq (%rsp), %rsi
movl $64, %edx
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
movl $1, %r14d
.LBB1_3: # =>This Inner Loop Header: Depth=1
movl (%rbx,%r14,4), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movl $.L.str, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
incq %r14
cmpq $16, %r14
jne .LBB1_3
# %bb.4:
movq _ZSt4cout(%rip), %rax
movl $_ZSt4cout, %ecx
movq -24(%rax), %rdi
addq %rcx, %rdi
movl $10, %esi
callq _ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq (%rsp), %rdi
callq hipFree
movq %rbx, %rdi
callq _ZdaPv
xorl %eax, %eax
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, %rdi
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z5task2Pi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z5task2Pi,@object # @_Z5task2Pi
.section .rodata,"a",@progbits
.globl _Z5task2Pi
.p2align 3, 0x0
_Z5task2Pi:
.quad _Z20__device_stub__task2Pi
.size _Z5task2Pi, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz " "
.size .L.str, 2
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z5task2Pi"
.size .L__unnamed_1, 11
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z20__device_stub__task2Pi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z5task2Pi
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
```
| 2,751 | 2,776 |
478 |
Convert the following CUDA device assembly code to AMD device assembly:
```cudaasm
code for sm_80
Function : _Z14distanceKernelPfS_f
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
MOV R1, c[0x0][0x28] ;
S2R R0, SR_CTAID.X ;
HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ;
ULDC.64 UR4, c[0x0][0x118] ;
S2R R3, SR_TID.X ;
IMAD R0, R0, c[0x0][0x0], R3 ;
IMAD.WIDE R2, R0, R5, c[0x0][0x168] ;
LDG.E R2, [R2.64] ;
BSSY B0, 0x170 ;
FADD R4, -R2, c[0x0][0x170] ;
FMUL R4, R4, R4 ;
MUFU.RSQ R5, R4 ;
IADD3 R6, R4, -0xd000000, RZ ;
ISETP.GT.U32.AND P0, PT, R6, 0x727fffff, PT ;
@!P0 BRA 0x120 ;
MOV R8, 0x110 ;
CALL.REL.NOINC 0x1b0 ;
BRA 0x160 ;
FMUL.FTZ R3, R4, R5 ;
FMUL.FTZ R5, R5, 0.5 ;
FFMA R4, -R3, R3, R4 ;
FFMA R5, R4, R5, R3 ;
BSYNC B0 ;
HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ;
IMAD.WIDE R2, R0, R3, c[0x0][0x160] ;
STG.E [R2.64], R5 ;
EXIT ;
LOP3.LUT P0, RZ, R4, 0x7fffffff, RZ, 0xc0, !PT ;
@!P0 MOV R2, R4 ;
@!P0 BRA 0x2e0 ;
FSETP.GEU.FTZ.AND P0, PT, R4, RZ, PT ;
@!P0 MOV R2, 0x7fffffff ;
@!P0 BRA 0x2e0 ;
FSETP.GTU.FTZ.AND P0, PT, |R4|, +INF , PT ;
@P0 FADD.FTZ R2, R4, 1 ;
@P0 BRA 0x2e0 ;
FSETP.NEU.FTZ.AND P0, PT, |R4|, +INF , PT ;
@P0 FFMA R3, R4, 1.84467440737095516160e+19, RZ ;
@P0 MUFU.RSQ R2, R3 ;
@P0 FMUL.FTZ R6, R3, R2 ;
@P0 FMUL.FTZ R7, R2, 0.5 ;
@!P0 MOV R2, R4 ;
@P0 FADD.FTZ R5, -R6, -RZ ;
@P0 FFMA R5, R6, R5, R3 ;
@P0 FFMA R5, R5, R7, R6 ;
@P0 FMUL.FTZ R2, R5, 2.3283064365386962891e-10 ;
HFMA2.MMA R3, -RZ, RZ, 0, 0 ;
MOV R5, R2 ;
MOV R2, R8 ;
RET.REL.NODEC R2 0x0 ;
BRA 0x320;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
```
|
```amdasm
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z14distanceKernelPfS_f ; -- Begin function _Z14distanceKernelPfS_f
.globl _Z14distanceKernelPfS_f
.p2align 8
.type _Z14distanceKernelPfS_f,@function
_Z14distanceKernelPfS_f: ; @_Z14distanceKernelPfS_f
; %bb.0:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x24
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b32 s0, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
v_add_co_u32 v2, vcc_lo, s6, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v1, vcc_lo
global_load_b32 v2, v[2:3], off
s_waitcnt vmcnt(0)
v_sub_f32_e32 v2, s0, v2
v_mul_f32_e32 v2, v2, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_f32_e32 v3, 0x4f800000, v2
v_cmp_gt_f32_e32 vcc_lo, 0xf800000, v2
v_cndmask_b32_e32 v2, v2, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
v_sqrt_f32_e32 v3, v2
s_waitcnt_depctr 0xfff
v_add_nc_u32_e32 v4, -1, v3
v_add_nc_u32_e32 v5, 1, v3
v_fma_f32 v6, -v4, v3, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v7, -v5, v3, v2
v_cmp_ge_f32_e64 s0, 0, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cndmask_b32_e64 v3, v3, v4, s0
v_cmp_lt_f32_e64 s0, 0, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e64 v3, v3, v5, s0
v_mul_f32_e32 v4, 0x37800000, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v3, v3, v4, vcc_lo
v_cmp_class_f32_e64 vcc_lo, v2, 0x260
v_cndmask_b32_e32 v2, v3, v2, vcc_lo
v_add_co_u32 v0, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z14distanceKernelPfS_f
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z14distanceKernelPfS_f, .Lfunc_end0-_Z14distanceKernelPfS_f
; -- End function
.section .AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 272
; NumSgprs: 18
; NumVgprs: 8
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 8
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object ; @__hip_cuid_
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0 ; 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z14distanceKernelPfS_f
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z14distanceKernelPfS_f.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
```
| 980 | 2,982 |
479 |
Convert the following CUDA host assembly code to AMD host assembly:
```cudaasm
.file "tmpxft_0002cfe3_00000000-6_kernel.cudafe1.cpp"
.text
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z5scaleii
.type _Z5scaleii, @function
_Z5scaleii:
.LFB2057:
.cfi_startproc
endbr64
pxor %xmm0, %xmm0
cvtsi2ssl %edi, %xmm0
subl $1, %esi
pxor %xmm1, %xmm1
cvtsi2ssl %esi, %xmm1
divss %xmm1, %xmm0
ret
.cfi_endproc
.LFE2057:
.size _Z5scaleii, .-_Z5scaleii
.globl _Z8distanceff
.type _Z8distanceff, @function
_Z8distanceff:
.LFB2058:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2058:
.size _Z8distanceff, .-_Z8distanceff
.globl _Z37__device_stub__Z14distanceKernelPfS_fPfS_f
.type _Z37__device_stub__Z14distanceKernelPfS_fPfS_f, @function
_Z37__device_stub__Z14distanceKernelPfS_fPfS_f:
.LFB2084:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movss %xmm0, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L10
.L6:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L11
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L10:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z14distanceKernelPfS_f(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L6
.L11:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z37__device_stub__Z14distanceKernelPfS_fPfS_f, .-_Z37__device_stub__Z14distanceKernelPfS_fPfS_f
.globl _Z14distanceKernelPfS_f
.type _Z14distanceKernelPfS_f, @function
_Z14distanceKernelPfS_f:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z37__device_stub__Z14distanceKernelPfS_fPfS_f
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z14distanceKernelPfS_f, .-_Z14distanceKernelPfS_f
.globl main
.type main, @function
main:
.LFB2059:
.cfi_startproc
endbr64
subq $56, %rsp
.cfi_def_cfa_offset 64
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movq $0, (%rsp)
movq $0, 8(%rsp)
movq %rsp, %rdi
movl $1, %edx
movl $256, %esi
call cudaMallocManaged@PLT
leaq 8(%rsp), %rdi
movl $1, %edx
movl $256, %esi
call cudaMallocManaged@PLT
movl $0, %eax
movss .LC0(%rip), %xmm1
.L15:
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
divss %xmm1, %xmm0
movq (%rsp), %rdx
movss %xmm0, (%rdx,%rax,4)
addq $1, %rax
cmpq $64, %rax
jne .L15
movl $32, 28(%rsp)
movl $1, 32(%rsp)
movl $2, 16(%rsp)
movl $1, 20(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L20
.L16:
call cudaDeviceSynchronize@PLT
movq (%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L21
movl $0, %eax
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L20:
.cfi_restore_state
movss .LC1(%rip), %xmm0
movq (%rsp), %rsi
movq 8(%rsp), %rdi
call _Z37__device_stub__Z14distanceKernelPfS_fPfS_f
jmp .L16
.L21:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "_Z14distanceKernelPfS_f"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z14distanceKernelPfS_f(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC0:
.long 1115422720
.align 4
.LC1:
.long 1056964608
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
```
|
```amdasm
.text
.file "kernel.hip"
.globl _Z5scaleii # -- Begin function _Z5scaleii
.type _Z5scaleii,@function
_Z5scaleii: # @_Z5scaleii
.cfi_startproc
# %bb.0:
cvtsi2ss %edi, %xmm0
decl %esi
cvtsi2ss %esi, %xmm1
divss %xmm1, %xmm0
retq
.Lfunc_end0:
.size _Z5scaleii, .Lfunc_end0-_Z5scaleii
.cfi_endproc
# -- End function
.globl _Z29__device_stub__distanceKernelPfS_f # -- Begin function _Z29__device_stub__distanceKernelPfS_f
.type _Z29__device_stub__distanceKernelPfS_f,@function
_Z29__device_stub__distanceKernelPfS_f: # @_Z29__device_stub__distanceKernelPfS_f
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $112, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 40(%rsp), %rax
movq %rdi, (%rax)
leaq 32(%rsp), %rcx
movq %rsi, (%rcx)
leaq 12(%rsp), %rdx
movss %xmm0, (%rdx)
leaq 80(%rsp), %rbx
movq %rax, (%rbx)
movq %rcx, 8(%rbx)
movq %rdx, 16(%rbx)
leaq 64(%rsp), %r14
leaq 48(%rsp), %r15
leaq 24(%rsp), %r12
leaq 16(%rsp), %r13
movq %r14, %rdi
movq %r15, %rsi
movq %r12, %rdx
movq %r13, %rcx
callq __hipPopCallConfiguration
movq (%r14), %rsi
movl 8(%r14), %edx
movq (%r15), %rcx
movl 8(%r15), %r8d
movl $_Z14distanceKernelPfS_f, %edi
movq %rbx, %r9
pushq (%r13)
.cfi_adjust_cfa_offset 8
pushq (%r12)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $128, %rsp
.cfi_adjust_cfa_offset -128
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z29__device_stub__distanceKernelPfS_f, .Lfunc_end1-_Z29__device_stub__distanceKernelPfS_f
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI2_0:
.long 0x427c0000 # float 63
.LCPI2_1:
.long 0x3f000000 # float 0.5
.text
.globl main
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $16, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
xorl %r15d, %r15d
leaq 8(%rsp), %rbx
movq %r15, (%rbx)
movq %rsp, %r14
movq %r15, (%r14)
movl $256, %esi # imm = 0x100
movq %rbx, %rdi
movl $1, %edx
callq hipMallocManaged
movl $256, %esi # imm = 0x100
movq %r14, %rdi
movl $1, %edx
callq hipMallocManaged
movq (%rbx), %rax
movss .LCPI2_0(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero
.LBB2_1: # =>This Inner Loop Header: Depth=1
xorps %xmm1, %xmm1
cvtsi2ss %r15d, %xmm1
divss %xmm0, %xmm1
movss %xmm1, (%rax,%r15,4)
incq %r15
cmpq $64, %r15
jne .LBB2_1
# %bb.2:
movabsq $4294967298, %rdi # imm = 0x100000002
leaq 30(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_4
# %bb.3:
movq (%rsp), %rdi
movq 8(%rsp), %rsi
movss .LCPI2_1(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero
callq _Z29__device_stub__distanceKernelPfS_f
.LBB2_4:
callq hipDeviceSynchronize
movq 8(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $16, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, %rdi
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z14distanceKernelPfS_f, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z14distanceKernelPfS_f,@object # @_Z14distanceKernelPfS_f
.section .rodata,"a",@progbits
.globl _Z14distanceKernelPfS_f
.p2align 3, 0x0
_Z14distanceKernelPfS_f:
.quad _Z29__device_stub__distanceKernelPfS_f
.size _Z14distanceKernelPfS_f, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z14distanceKernelPfS_f"
.size .L__unnamed_1, 24
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z29__device_stub__distanceKernelPfS_f
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z14distanceKernelPfS_f
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
```
| 2,879 | 3,075 |
480 |
Convert the following CUDA device assembly code to AMD device assembly:
```cudaasm
code for sm_80
Function : _Z9selectPrePfS_S_S_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ;
S2R R0, SR_TID.X ;
IMAD.MOV.U32 R3, RZ, RZ, 0x4 ;
ULDC.64 UR4, c[0x0][0x118] ;
IMAD.WIDE R2, R0, R3, c[0x0][0x160] ;
LDG.E R5, [R2.64] ;
BSSY B0, 0x140 ;
IADD3 R4, R5, 0x1800000, RZ ;
LOP3.LUT R4, R4, 0x7f800000, RZ, 0xc0, !PT ;
ISETP.GT.U32.AND P0, PT, R4, 0x1ffffff, PT ;
@P0 BRA 0xf0 ;
MOV R4, 0xd0 ;
CALL.REL.NOINC 0x350 ;
IMAD.MOV.U32 R13, RZ, RZ, R6 ;
BRA 0x130 ;
MUFU.RCP R4, R5 ;
FFMA R6, R5, R4, -1 ;
FADD.FTZ R13, -R6, -RZ ;
FFMA R13, R4, R13, R4 ;
BSYNC B0 ;
IMAD.MOV.U32 R11, RZ, RZ, 0x4 ;
IMAD.WIDE R6, R0, R11, c[0x0][0x168] ;
STG.E [R6.64], R13 ;
BAR.SYNC.DEFER_BLOCKING 0x0 ;
LDG.E R3, [R2.64] ;
IMAD.WIDE R8, R0, R11, c[0x0][0x170] ;
IMAD R10, R0, 0xa, RZ ;
IMAD.WIDE R4, R10.reuse, R11.reuse, c[0x0][0x178] ;
STG.E [R8.64], R3 ;
BAR.SYNC.DEFER_BLOCKING 0x0 ;
LDG.E R15, [R4.64] ;
IMAD.WIDE R10, R10, R11, c[0x0][0x180] ;
STG.E [R10.64], R15 ;
LDG.E R7, [R4.64+0x4] ;
STG.E [R10.64+0x4], R7 ;
LDG.E R13, [R4.64+0x8] ;
STG.E [R10.64+0x8], R13 ;
LDG.E R17, [R4.64+0xc] ;
STG.E [R10.64+0xc], R17 ;
LDG.E R3, [R4.64+0x10] ;
STG.E [R10.64+0x10], R3 ;
LDG.E R9, [R4.64+0x14] ;
STG.E [R10.64+0x14], R9 ;
LDG.E R15, [R4.64+0x18] ;
STG.E [R10.64+0x18], R15 ;
LDG.E R7, [R4.64+0x1c] ;
STG.E [R10.64+0x1c], R7 ;
LDG.E R13, [R4.64+0x20] ;
STG.E [R10.64+0x20], R13 ;
LDG.E R17, [R4.64+0x24] ;
STG.E [R10.64+0x24], R17 ;
BAR.SYNC.DEFER_BLOCKING 0x0 ;
EXIT ;
IMAD.SHL.U32 R6, R5, 0x2, RZ ;
BSSY B1, 0x670 ;
SHF.R.U32.HI R6, RZ, 0x18, R6 ;
ISETP.NE.U32.AND P0, PT, R6, RZ, PT ;
@P0 BRA 0x440 ;
IMAD.SHL.U32 R6, R5, 0x2, RZ ;
ISETP.NE.AND P0, PT, R6, RZ, PT ;
@P0 FFMA R7, R5, 1.84467440737095516160e+19, RZ ;
@!P0 MUFU.RCP R6, R5 ;
@P0 MUFU.RCP R8, R7 ;
@P0 FFMA R9, R7, R8, -1 ;
@P0 FADD.FTZ R9, -R9, -RZ ;
@P0 FFMA R9, R8, R9, R8 ;
@P0 FFMA R6, R9, 1.84467440737095516160e+19, RZ ;
BRA 0x660 ;
IADD3 R7, R6, -0xfd, RZ ;
ISETP.GT.U32.AND P0, PT, R7, 0x1, PT ;
@P0 BRA 0x650 ;
LOP3.LUT R8, R5, 0x7fffff, RZ, 0xc0, !PT ;
IMAD.MOV.U32 R12, RZ, RZ, 0x3 ;
LOP3.LUT R8, R8, 0x3f800000, RZ, 0xfc, !PT ;
SHF.L.U32 R13, R12, R7, RZ ;
MUFU.RCP R9, R8 ;
FFMA R10, R8, R9, -1 ;
FADD.FTZ R10, -R10, -RZ ;
FFMA.RM R11, R9.reuse, R10.reuse, R9.reuse ;
FFMA.RP R10, R9, R10, R9 ;
LOP3.LUT R9, R11.reuse, 0x7fffff, RZ, 0xc0, !PT ;
FSETP.NEU.FTZ.AND P0, PT, R11, R10, PT ;
LOP3.LUT R10, R9, 0x800000, RZ, 0xfc, !PT ;
SEL R9, RZ, 0xffffffff, !P0 ;
LOP3.LUT R8, R13, R10, RZ, 0xc0, !PT ;
IMAD.MOV R9, RZ, RZ, -R9 ;
SHF.R.U32.HI R8, RZ, R7, R8 ;
LOP3.LUT P1, RZ, R9, R7, R10, 0xf8, !PT ;
LOP3.LUT P0, RZ, R8.reuse, 0x1, RZ, 0xc0, !PT ;
LOP3.LUT P2, RZ, R8, 0x2, RZ, 0xc0, !PT ;
PLOP3.LUT P0, PT, P0, P1, P2, 0xe0, 0x0 ;
LOP3.LUT P1, RZ, R5, 0x7fffff, RZ, 0xc0, !PT ;
SEL R7, RZ, 0x1, !P0 ;
IMAD.MOV R7, RZ, RZ, -R7 ;
ISETP.GE.AND P0, PT, R7, RZ, PT ;
IADD3 R7, R6, -0xfc, RZ ;
SHF.R.U32.HI R6, RZ, R7, R10 ;
@!P0 IADD3 R6, R6, 0x1, RZ ;
@!P1 IMAD.SHL.U32 R6, R6, 0x2, RZ ;
LOP3.LUT R6, R6, 0x80000000, R5, 0xf8, !PT ;
BRA 0x660 ;
MUFU.RCP R6, R5 ;
BSYNC B1 ;
IMAD.MOV.U32 R5, RZ, RZ, 0x0 ;
RET.REL.NODEC R4 0x0 ;
BRA 0x690;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
```
|
```amdasm
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9selectPrePfS_S_S_S_ ; -- Begin function _Z9selectPrePfS_S_S_S_
.globl _Z9selectPrePfS_S_S_S_
.p2align 8
.type _Z9selectPrePfS_S_S_S_,@function
_Z9selectPrePfS_S_S_S_: ; @_Z9selectPrePfS_S_S_S_
; %bb.0:
s_load_b256 s[4:11], s[0:1], 0x0
v_lshlrev_b32_e32 v4, 2, v0
v_mul_u32_u24_e32 v0, 10, v0
s_load_b64 s[2:3], s[0:1], 0x20
s_mov_b64 s[0:1], 0
s_waitcnt lgkmcnt(0)
global_load_b32 v1, v4, s[4:5]
s_waitcnt vmcnt(0)
v_div_scale_f32 v2, null, v1, v1, 1.0
v_div_scale_f32 v6, vcc_lo, 1.0, v1, 1.0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f32_e32 v3, v2
s_waitcnt_depctr 0xfff
v_fma_f32 v5, -v2, v3, 1.0
v_fmac_f32_e32 v3, v5, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v5, v6, v3
v_fma_f32 v7, -v2, v5, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v5, v7, v3
v_fma_f32 v2, -v2, v5, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fmas_f32 v2, v2, v3, v5
v_div_fixup_f32 v1, v2, v1, 1.0
v_lshlrev_b32_e32 v2, 2, v0
global_store_b32 v4, v1, s[6:7]
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
global_load_b32 v5, v4, s[4:5]
v_add_co_u32 v0, s4, s10, v2
v_add_co_u32 v2, s2, s2, v2
v_add_co_ci_u32_e64 v1, null, s11, 0, s4
v_add_co_ci_u32_e64 v3, null, s3, 0, s2
s_waitcnt vmcnt(0)
global_store_b32 v4, v5, s[8:9]
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
.LBB0_1: ; =>This Inner Loop Header: Depth=1
v_add_co_u32 v4, vcc_lo, v0, s0
v_add_co_ci_u32_e32 v5, vcc_lo, s1, v1, vcc_lo
global_load_b32 v6, v[4:5], off
v_add_co_u32 v4, vcc_lo, v2, s0
v_add_co_ci_u32_e32 v5, vcc_lo, s1, v3, vcc_lo
s_add_u32 s0, s0, 4
s_addc_u32 s1, s1, 0
s_cmp_eq_u32 s0, 40
s_waitcnt vmcnt(0)
global_store_b32 v[4:5], v6, off
s_cbranch_scc0 .LBB0_1
; %bb.2:
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9selectPrePfS_S_S_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 40
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 12
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9selectPrePfS_S_S_S_, .Lfunc_end0-_Z9selectPrePfS_S_S_S_
; -- End function
.section .AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 312
; NumSgprs: 14
; NumVgprs: 8
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 1
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 14
; NumVGPRsForWavesPerEU: 8
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.protected c_LB ; @c_LB
.type c_LB,@object
.section .bss,"aw",@nobits
.globl c_LB
.p2align 4, 0x0
c_LB:
.zero 40
.size c_LB, 40
.protected c_UB ; @c_UB
.type c_UB,@object
.globl c_UB
.p2align 4, 0x0
c_UB:
.zero 40
.size c_UB, 40
.protected c_a ; @c_a
.type c_a,@object
.globl c_a
.p2align 3, 0x0
c_a:
.quad 0
.size c_a, 8
.protected c_aa ; @c_aa
.type c_aa,@object
.globl c_aa
.p2align 3, 0x0
c_aa:
.quad 0
.size c_aa, 8
.protected c_aaa ; @c_aaa
.type c_aaa,@object
.globl c_aaa
.p2align 3, 0x0
c_aaa:
.quad 0
.size c_aaa, 8
.protected c_aRow ; @c_aRow
.type c_aRow,@object
.globl c_aRow
.p2align 2, 0x0
c_aRow:
.long 0 ; 0x0
.size c_aRow, 4
.protected c_aaaRow ; @c_aaaRow
.type c_aaaRow,@object
.globl c_aaaRow
.p2align 2, 0x0
c_aaaRow:
.long 0 ; 0x0
.size c_aaaRow, 4
.protected c_Dysum ; @c_Dysum
.type c_Dysum,@object
.globl c_Dysum
.p2align 4, 0x0
c_Dysum:
.zero 36
.size c_Dysum, 36
.type __hip_cuid_,@object ; @__hip_cuid_
.globl __hip_cuid_
__hip_cuid_:
.byte 0 ; 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 40
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9selectPrePfS_S_S_S_
.private_segment_fixed_size: 0
.sgpr_count: 14
.sgpr_spill_count: 0
.symbol: _Z9selectPrePfS_S_S_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
```
| 2,143 | 3,111 |
481 |
Convert the following CUDA host assembly code to AMD host assembly:
```cudaasm
.file "tmpxft_00088871_00000000-6_selectPre.cudafe1.cpp"
.text
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z36__device_stub__Z9selectPrePfS_S_S_S_PfS_S_S_S_
.type _Z36__device_stub__Z9selectPrePfS_S_S_S_PfS_S_S_S_, @function
_Z36__device_stub__Z9selectPrePfS_S_S_S_PfS_S_S_S_:
.LFB2051:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movq %r8, 8(%rsp)
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 184
pushq 56(%rsp)
.cfi_def_cfa_offset 192
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z9selectPrePfS_S_S_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z36__device_stub__Z9selectPrePfS_S_S_S_PfS_S_S_S_, .-_Z36__device_stub__Z9selectPrePfS_S_S_S_PfS_S_S_S_
.globl _Z9selectPrePfS_S_S_S_
.type _Z9selectPrePfS_S_S_S_, @function
_Z9selectPrePfS_S_S_S_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z36__device_stub__Z9selectPrePfS_S_S_S_PfS_S_S_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z9selectPrePfS_S_S_S_, .-_Z9selectPrePfS_S_S_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z9selectPrePfS_S_S_S_"
.LC1:
.string "c_LB"
.LC2:
.string "c_UB"
.LC3:
.string "c_a"
.LC4:
.string "c_aa"
.LC5:
.string "c_aaa"
.LC6:
.string "c_aRow"
.LC7:
.string "c_aaaRow"
.LC8:
.string "c_Dysum"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z9selectPrePfS_S_S_S_(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $40, %r9d
movl $0, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _ZL4c_LB(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $40, %r9d
movl $0, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _ZL4c_UB(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $8, %r9d
movl $0, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _ZL3c_a(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $8, %r9d
movl $0, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _ZL4c_aa(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $8, %r9d
movl $0, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _ZL5c_aaa(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $4, %r9d
movl $0, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _ZL6c_aRow(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $4, %r9d
movl $0, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _ZL8c_aaaRow(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $36, %r9d
movl $0, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _ZL7c_Dysum(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl G
.bss
.align 4
.type G, @object
.size G, 4
G:
.zero 4
.globl fval
.align 4
.type fval, @object
.size fval, 4
fval:
.zero 4
.globl aveFitnessOfGen
.align 32
.type aveFitnessOfGen, @object
.size aveFitnessOfGen, 2000
aveFitnessOfGen:
.zero 2000
.globl bestIndexOfGen
.align 4
.type bestIndexOfGen, @object
.size bestIndexOfGen, 4
bestIndexOfGen:
.zero 4
.globl bestFitnessOfGen
.align 4
.type bestFitnessOfGen, @object
.size bestFitnessOfGen, 4
bestFitnessOfGen:
.zero 4
.local _ZL7c_Dysum
.comm _ZL7c_Dysum,36,32
.local _ZL8c_aaaRow
.comm _ZL8c_aaaRow,4,4
.local _ZL6c_aRow
.comm _ZL6c_aRow,4,4
.local _ZL5c_aaa
.comm _ZL5c_aaa,8,8
.local _ZL4c_aa
.comm _ZL4c_aa,8,8
.local _ZL3c_a
.comm _ZL3c_a,8,8
.local _ZL4c_UB
.comm _ZL4c_UB,40,32
.local _ZL4c_LB
.comm _ZL4c_LB,40,32
.globl Dysum
.align 32
.type Dysum, @object
.size Dysum, 36
Dysum:
.zero 36
.globl aaaRow
.align 4
.type aaaRow, @object
.size aaaRow, 4
aaaRow:
.zero 4
.globl aRow
.align 4
.type aRow, @object
.size aRow, 4
aRow:
.zero 4
.globl aaa
.align 8
.type aaa, @object
.size aaa, 8
aaa:
.zero 8
.globl aa
.align 8
.type aa, @object
.size aa, 8
aa:
.zero 8
.globl a
.align 8
.type a, @object
.size a, 8
a:
.zero 8
.globl UB
.data
.align 32
.type UB, @object
.size UB, 40
UB:
.long 1084227584
.long 1082130432
.long 1084227584
.long 1082130432
.long 1084227584
.long 1084227584
.long 1084227584
.long 1084227584
.long 1084227584
.long 1082130432
.globl LB
.align 32
.type LB, @object
.size LB, 40
LB:
.long 1056964608
.long 1056964608
.long 1056964608
.long 1056964608
.long 1056964608
.long 1056964608
.long 1056964608
.long 1056964608
.long 1056964608
.long 1056964608
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
```
|
```amdasm
.text
.file "selectPre.hip"
.globl _Z24__device_stub__selectPrePfS_S_S_S_ # -- Begin function _Z24__device_stub__selectPrePfS_S_S_S_
.type _Z24__device_stub__selectPrePfS_S_S_S_,@function
_Z24__device_stub__selectPrePfS_S_S_S_: # @_Z24__device_stub__selectPrePfS_S_S_S_
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $144, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 56(%rsp), %rax
movq %rdi, (%rax)
leaq 48(%rsp), %rdi
movq %rsi, (%rdi)
leaq 40(%rsp), %rsi
movq %rdx, (%rsi)
leaq 32(%rsp), %rdx
movq %rcx, (%rdx)
leaq 24(%rsp), %rcx
movq %r8, (%rcx)
leaq 96(%rsp), %rbx
movq %rax, (%rbx)
movq %rdi, 8(%rbx)
movq %rsi, 16(%rbx)
movq %rdx, 24(%rbx)
movq %rcx, 32(%rbx)
leaq 80(%rsp), %r14
leaq 64(%rsp), %r15
leaq 16(%rsp), %r12
leaq 8(%rsp), %r13
movq %r14, %rdi
movq %r15, %rsi
movq %r12, %rdx
movq %r13, %rcx
callq __hipPopCallConfiguration
movq (%r14), %rsi
movl 8(%r14), %edx
movq (%r15), %rcx
movl 8(%r15), %r8d
movl $_Z9selectPrePfS_S_S_S_, %edi
movq %rbx, %r9
pushq (%r13)
.cfi_adjust_cfa_offset 8
pushq (%r12)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $160, %rsp
.cfi_adjust_cfa_offset -160
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z24__device_stub__selectPrePfS_S_S_S_, .Lfunc_end0-_Z24__device_stub__selectPrePfS_S_S_S_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
movq __hip_gpubin_handle(%rip), %rbx
testq %rbx, %rbx
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, %rbx
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
subq $32, %rsp
.cfi_adjust_cfa_offset 32
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9selectPrePfS_S_S_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
addq $32, %rsp
.cfi_adjust_cfa_offset -32
movl $c_LB, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movl $40, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
pushq $0
.cfi_adjust_cfa_offset 8
pushq $0
.cfi_adjust_cfa_offset 8
callq __hipRegisterVar
addq $16, %rsp
.cfi_adjust_cfa_offset -16
movl $c_UB, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movl $40, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
pushq $0
.cfi_adjust_cfa_offset 8
pushq $0
.cfi_adjust_cfa_offset 8
callq __hipRegisterVar
addq $16, %rsp
.cfi_adjust_cfa_offset -16
movl $c_a, %esi
movl $.L__unnamed_4, %edx
movl $.L__unnamed_4, %ecx
movl $8, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
pushq $0
.cfi_adjust_cfa_offset 8
pushq $0
.cfi_adjust_cfa_offset 8
callq __hipRegisterVar
addq $16, %rsp
.cfi_adjust_cfa_offset -16
movl $c_aa, %esi
movl $.L__unnamed_5, %edx
movl $.L__unnamed_5, %ecx
movl $8, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
pushq $0
.cfi_adjust_cfa_offset 8
pushq $0
.cfi_adjust_cfa_offset 8
callq __hipRegisterVar
addq $16, %rsp
.cfi_adjust_cfa_offset -16
movl $c_aaa, %esi
movl $.L__unnamed_6, %edx
movl $.L__unnamed_6, %ecx
movl $8, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
pushq $0
.cfi_adjust_cfa_offset 8
pushq $0
.cfi_adjust_cfa_offset 8
callq __hipRegisterVar
addq $16, %rsp
.cfi_adjust_cfa_offset -16
movl $c_aRow, %esi
movl $.L__unnamed_7, %edx
movl $.L__unnamed_7, %ecx
movl $4, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
pushq $0
.cfi_adjust_cfa_offset 8
pushq $0
.cfi_adjust_cfa_offset 8
callq __hipRegisterVar
addq $16, %rsp
.cfi_adjust_cfa_offset -16
movl $c_aaaRow, %esi
movl $.L__unnamed_8, %edx
movl $.L__unnamed_8, %ecx
movl $4, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
pushq $0
.cfi_adjust_cfa_offset 8
pushq $0
.cfi_adjust_cfa_offset 8
callq __hipRegisterVar
addq $16, %rsp
.cfi_adjust_cfa_offset -16
movl $c_Dysum, %esi
movl $.L__unnamed_9, %edx
movl $.L__unnamed_9, %ecx
movl $36, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
pushq $0
.cfi_adjust_cfa_offset 8
pushq $0
.cfi_adjust_cfa_offset 8
callq __hipRegisterVar
addq $16, %rsp
.cfi_adjust_cfa_offset -16
movl $__hip_module_dtor, %edi
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type LB,@object # @LB
.data
.globl LB
.p2align 4, 0x0
LB:
.long 0x3f000000 # float 0.5
.long 0x3f000000 # float 0.5
.long 0x3f000000 # float 0.5
.long 0x3f000000 # float 0.5
.long 0x3f000000 # float 0.5
.long 0x3f000000 # float 0.5
.long 0x3f000000 # float 0.5
.long 0x3f000000 # float 0.5
.long 0x3f000000 # float 0.5
.long 0x3f000000 # float 0.5
.size LB, 40
.type UB,@object # @UB
.globl UB
.p2align 4, 0x0
UB:
.long 0x40a00000 # float 5
.long 0x40800000 # float 4
.long 0x40a00000 # float 5
.long 0x40800000 # float 4
.long 0x40a00000 # float 5
.long 0x40a00000 # float 5
.long 0x40a00000 # float 5
.long 0x40a00000 # float 5
.long 0x40a00000 # float 5
.long 0x40800000 # float 4
.size UB, 40
.type a,@object # @a
.bss
.globl a
.p2align 3, 0x0
a:
.quad 0
.size a, 8
.type aa,@object # @aa
.globl aa
.p2align 3, 0x0
aa:
.quad 0
.size aa, 8
.type aaa,@object # @aaa
.globl aaa
.p2align 3, 0x0
aaa:
.quad 0
.size aaa, 8
.type aRow,@object # @aRow
.globl aRow
.p2align 2, 0x0
aRow:
.long 0 # 0x0
.size aRow, 4
.type aaaRow,@object # @aaaRow
.globl aaaRow
.p2align 2, 0x0
aaaRow:
.long 0 # 0x0
.size aaaRow, 4
.type Dysum,@object # @Dysum
.globl Dysum
.p2align 4, 0x0
Dysum:
.zero 36
.size Dysum, 36
.type c_LB,@object # @c_LB
.local c_LB
.comm c_LB,40,16
.type c_UB,@object # @c_UB
.local c_UB
.comm c_UB,40,16
.type c_a,@object # @c_a
.local c_a
.comm c_a,8,8
.type c_aa,@object # @c_aa
.local c_aa
.comm c_aa,8,8
.type c_aaa,@object # @c_aaa
.local c_aaa
.comm c_aaa,8,8
.type c_aRow,@object # @c_aRow
.local c_aRow
.comm c_aRow,4,4
.type c_aaaRow,@object # @c_aaaRow
.local c_aaaRow
.comm c_aaaRow,4,4
.type c_Dysum,@object # @c_Dysum
.local c_Dysum
.comm c_Dysum,36,16
.type bestFitnessOfGen,@object # @bestFitnessOfGen
.globl bestFitnessOfGen
.p2align 2, 0x0
bestFitnessOfGen:
.long 0x00000000 # float 0
.size bestFitnessOfGen, 4
.type bestIndexOfGen,@object # @bestIndexOfGen
.globl bestIndexOfGen
.p2align 2, 0x0
bestIndexOfGen:
.long 0 # 0x0
.size bestIndexOfGen, 4
.type aveFitnessOfGen,@object # @aveFitnessOfGen
.globl aveFitnessOfGen
.p2align 4, 0x0
aveFitnessOfGen:
.zero 2000
.size aveFitnessOfGen, 2000
.type fval,@object # @fval
.globl fval
.p2align 2, 0x0
fval:
.long 0x00000000 # float 0
.size fval, 4
.type G,@object # @G
.globl G
.p2align 2, 0x0
G:
.long 0 # 0x0
.size G, 4
.type _Z9selectPrePfS_S_S_S_,@object # @_Z9selectPrePfS_S_S_S_
.section .rodata,"a",@progbits
.globl _Z9selectPrePfS_S_S_S_
.p2align 3, 0x0
_Z9selectPrePfS_S_S_S_:
.quad _Z24__device_stub__selectPrePfS_S_S_S_
.size _Z9selectPrePfS_S_S_S_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z9selectPrePfS_S_S_S_"
.size .L__unnamed_1, 23
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "c_LB"
.size .L__unnamed_2, 5
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "c_UB"
.size .L__unnamed_3, 5
.type .L__unnamed_4,@object # @3
.L__unnamed_4:
.asciz "c_a"
.size .L__unnamed_4, 4
.type .L__unnamed_5,@object # @4
.L__unnamed_5:
.asciz "c_aa"
.size .L__unnamed_5, 5
.type .L__unnamed_6,@object # @5
.L__unnamed_6:
.asciz "c_aaa"
.size .L__unnamed_6, 6
.type .L__unnamed_7,@object # @6
.L__unnamed_7:
.asciz "c_aRow"
.size .L__unnamed_7, 7
.type .L__unnamed_8,@object # @7
.L__unnamed_8:
.asciz "c_aaaRow"
.size .L__unnamed_8, 9
.type .L__unnamed_9,@object # @8
.L__unnamed_9:
.asciz "c_Dysum"
.size .L__unnamed_9, 8
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__selectPrePfS_S_S_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym c_LB
.addrsig_sym c_UB
.addrsig_sym c_a
.addrsig_sym c_aa
.addrsig_sym c_aaa
.addrsig_sym c_aRow
.addrsig_sym c_aaaRow
.addrsig_sym c_Dysum
.addrsig_sym _Z9selectPrePfS_S_S_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
```
| 4,148 | 5,026 |
484 |
Convert the following CUDA device assembly code to AMD device assembly:
```cudaasm
code for sm_80
Function : _Z7cu_kronPKfS0_Pfiiiii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ;
IABS R4, c[0x0][0x17c] ;
S2R R13, SR_CTAID.X ;
IABS R7, c[0x0][0x184] ;
ULDC.64 UR6, c[0x0][0x180] ;
I2F.RP R0, R4 ;
S2R R8, SR_TID.X ;
ULDC.64 UR8, c[0x0][0x178] ;
ULOP3.LUT UR4, UR7, UR9, URZ, 0x3c, !UPT ;
ULOP3.LUT UR5, UR6, UR8, URZ, 0x3c, !UPT ;
ISETP.LE.AND P0, PT, RZ, UR4, PT ;
ISETP.LE.AND P1, PT, RZ, UR5, PT ;
MUFU.RCP R0, R0 ;
IMAD R13, R13, c[0x0][0x0], R8 ;
ISETP.GE.AND P2, PT, R13, c[0x0][0x188], PT ;
IADD3 R2, R0, 0xffffffe, RZ ;
F2I.FTZ.U32.TRUNC.NTZ R3, R2 ;
IMAD.MOV.U32 R2, RZ, RZ, RZ ;
IMAD.MOV R5, RZ, RZ, -R3 ;
IMAD R5, R5, R4, RZ ;
IMAD.HI.U32 R6, R3, R5, R2 ;
IMAD.MOV.U32 R5, RZ, RZ, R7 ;
IMAD.HI.U32 R6, R6, R5, RZ ;
IMAD.MOV R3, RZ, RZ, -R6 ;
IMAD.MOV.U32 R0, RZ, RZ, R5.reuse ;
IMAD R3, R4, R3, R5 ;
@P2 EXIT ;
IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x0] ;
IABS R7, c[0x0][0x178] ;
ULDC.64 UR4, c[0x0][0x118] ;
ISETP.GT.U32.AND P5, PT, R4, R3, PT ;
IMAD R2, R2, c[0x0][0xc], RZ ;
I2F.RP R12, R7 ;
BSSY B0, 0xbb0 ;
IMAD.IADD R10, R13, 0x1, R2 ;
ISETP.NE.U32.AND P4, PT, R2, RZ, PT ;
I2F.U32.RP R14, R2 ;
LOP3.LUT R15, RZ, R10, RZ, 0x33, !PT ;
IMAD.MOV.U32 R10, RZ, RZ, RZ ;
@!P5 IADD3 R6, R6, 0x1, RZ ;
@!P5 IMAD.IADD R3, R3, 0x1, -R4 ;
IADD3 R15, R15, c[0x0][0x188], R2 ;
ISETP.NE.AND P5, PT, RZ, c[0x0][0x17c], PT ;
MUFU.RCP R12, R12 ;
MUFU.RCP R14, R14 ;
IADD3 R8, R12, 0xffffffe, RZ ;
IABS R12, c[0x0][0x180] ;
F2I.FTZ.U32.TRUNC.NTZ R9, R8 ;
IADD3 R11, R14, 0xffffffe, RZ ;
IMAD.MOV.U32 R8, RZ, RZ, RZ ;
F2I.FTZ.U32.TRUNC.NTZ R11, R11 ;
IMAD.MOV R14, RZ, RZ, -R9 ;
IADD3 R17, RZ, -R11, RZ ;
IMAD R17, R17, R2, RZ ;
IMAD.HI.U32 R10, R11, R17, R10 ;
IMAD R11, R14, R7, RZ ;
IMAD.HI.U32 R8, R9, R11, R8 ;
IMAD.HI.U32 R9, R10, R15, RZ ;
IMAD.MOV.U32 R11, RZ, RZ, R12 ;
IMAD.MOV R12, RZ, RZ, -R9 ;
IMAD.HI.U32 R8, R8, R11, RZ ;
IMAD R15, R2, R12, R15 ;
IMAD.MOV R10, RZ, RZ, -R8 ;
ISETP.GE.U32.AND P3, PT, R15, R2, PT ;
IMAD R10, R7, R10, R11 ;
ISETP.GT.U32.AND P2, PT, R7, R10, PT ;
@P3 IADD3 R15, R15, -R2.reuse, RZ ;
@P3 IADD3 R9, R9, 0x1, RZ ;
ISETP.GE.U32.AND P6, PT, R15, R2, PT ;
ISETP.GE.U32.AND P3, PT, R3, R4, PT ;
@!P2 IMAD.IADD R10, R10, 0x1, -R7 ;
@!P2 IADD3 R8, R8, 0x1, RZ ;
ISETP.GE.U32.AND P2, PT, R10, R7, PT ;
@P6 IADD3 R9, R9, 0x1, RZ ;
@!P4 LOP3.LUT R9, RZ, R2, RZ, 0x33, !PT ;
@P3 IADD3 R6, R6, 0x1, RZ ;
IADD3 R7, R9, 0x1, RZ ;
ISETP.NE.AND P4, PT, RZ, c[0x0][0x178], PT ;
IMAD.MOV.U32 R4, RZ, RZ, R6 ;
LOP3.LUT P3, R15, R7, 0x3, RZ, 0xc0, !PT ;
@P2 IADD3 R8, R8, 0x1, RZ ;
@!P0 IMAD.MOV R4, RZ, RZ, -R4 ;
ISETP.GE.U32.AND P2, PT, R9, 0x3, PT ;
@!P5 LOP3.LUT R4, RZ, c[0x0][0x17c], RZ, 0x33, !PT ;
IMAD.MOV.U32 R3, RZ, RZ, R8 ;
@!P1 IMAD.MOV R3, RZ, RZ, -R3 ;
@!P4 LOP3.LUT R3, RZ, c[0x0][0x178], RZ, 0x33, !PT ;
@!P3 BRA 0xba0 ;
I2F.RP R8, R5 ;
HFMA2.MMA R10, -RZ, RZ, 0, 2.384185791015625e-07 ;
ISETP.NE.AND P0, PT, R4, RZ, PT ;
LOP3.LUT R14, RZ, R4, RZ, 0x33, !PT ;
MUFU.RCP R8, R8 ;
IADD3 R9, R8, 0xffffffe, RZ ;
F2I.FTZ.U32.TRUNC.NTZ R7, R9 ;
IMAD.MOV R6, RZ, RZ, -R7 ;
IMAD R11, R6, R5, RZ ;
IMAD.MOV.U32 R6, RZ, RZ, RZ ;
IMAD.HI.U32 R12, R7, R11, R6 ;
IMAD.WIDE R6, R13, R10, c[0x0][0x170] ;
IABS R16, R3 ;
IABS R11, R13 ;
I2F.RP R10, R16 ;
IABS R17, R4.reuse ;
IMAD.HI.U32 R18, R12, R11, RZ ;
IABS R5, c[0x0][0x184] ;
IABS R23, R4 ;
IMAD.MOV R8, RZ, RZ, -R18 ;
I2F.RP R19, R17 ;
IMAD R11, R5, R8, R11 ;
LOP3.LUT R8, R13, c[0x0][0x184], RZ, 0x3c, !PT ;
IMAD.MOV R23, RZ, RZ, -R23 ;
MUFU.RCP R10, R10 ;
ISETP.GT.U32.AND P3, PT, R0, R11, PT ;
ISETP.GE.AND P4, PT, R8, RZ, PT ;
MOV R8, RZ ;
MUFU.RCP R19, R19 ;
@!P3 IMAD.IADD R11, R11, 0x1, -R5 ;
@!P3 IADD3 R18, R18, 0x1, RZ ;
IADD3 R9, R10, 0xffffffe, RZ ;
ISETP.GE.U32.AND P1, PT, R11, R0, PT ;
ISETP.NE.AND P3, PT, RZ, c[0x0][0x184], PT ;
F2I.FTZ.U32.TRUNC.NTZ R9, R9 ;
IADD3 R11, R19, 0xffffffe, RZ ;
F2I.FTZ.U32.TRUNC.NTZ R11, R11 ;
@P1 IADD3 R18, R18, 0x1, RZ ;
@!P4 IMAD.MOV R18, RZ, RZ, -R18 ;
@!P3 LOP3.LUT R18, RZ, c[0x0][0x184], RZ, 0x33, !PT ;
IMAD.MOV R19, RZ, RZ, -R9 ;
IMAD R19, R19, R16, RZ ;
IMAD.MOV R10, RZ, RZ, -R18 ;
IMAD.HI.U32 R8, R9, R19, R8 ;
IABS R19, R3 ;
IMAD.MOV R22, RZ, RZ, -R11 ;
IMAD R9, R10, c[0x0][0x184], R13 ;
IMAD R21, R22, R17, RZ ;
IMAD.MOV.U32 R10, RZ, RZ, RZ ;
IABS R22, R9 ;
IMAD.MOV R20, RZ, RZ, -R19 ;
IABS R19, R18 ;
IMAD.HI.U32 R10, R11, R21, R10 ;
IMAD.MOV.U32 R21, RZ, RZ, R22 ;
IMAD.MOV.U32 R11, RZ, RZ, R20 ;
MOV R20, R23 ;
IMAD.HI.U32 R8, R8, R19, RZ ;
IMAD.HI.U32 R10, R10, R21, RZ ;
IMAD R19, R8, R11, R19 ;
LOP3.LUT R11, R18, R3, RZ, 0x3c, !PT ;
IMAD R20, R10, R20, R21 ;
ISETP.GT.U32.AND P1, PT, R16, R19, PT ;
ISETP.GT.U32.AND P5, PT, R17, R20, PT ;
ISETP.GE.AND P3, PT, R11, RZ, PT ;
@!P1 IMAD.IADD R19, R19, 0x1, -R16 ;
@!P1 IADD3 R8, R8, 0x1, RZ ;
@!P5 IMAD.IADD R20, R20, 0x1, -R17 ;
@!P5 IADD3 R10, R10, 0x1, RZ ;
ISETP.GE.U32.AND P6, PT, R19, R16, PT ;
ISETP.GE.U32.AND P4, PT, R20, R17, PT ;
LOP3.LUT R16, R9, R4, RZ, 0x3c, !PT ;
ISETP.NE.AND P5, PT, R3, RZ, PT ;
ISETP.GE.AND P1, PT, R16, RZ, PT ;
@P6 IADD3 R8, R8, 0x1, RZ ;
@P4 IADD3 R10, R10, 0x1, RZ ;
IMAD.MOV.U32 R17, RZ, RZ, R8 ;
@!P1 IMAD.MOV R10, RZ, RZ, -R10 ;
@!P3 IMAD.MOV R17, RZ, RZ, -R17 ;
@!P5 LOP3.LUT R17, RZ, R3, RZ, 0x33, !PT ;
SEL R10, R14, R10, !P0 ;
IMAD.MOV R8, RZ, RZ, -R17 ;
IADD3 R11, -R10, RZ, RZ ;
IMAD R18, R3, R8, R18 ;
IMAD R9, R4.reuse, R11, R9 ;
IMAD.MOV.U32 R11, RZ, RZ, 0x4 ;
IMAD R8, R17, c[0x0][0x17c], R10 ;
IMAD R10, R4, R18, R9 ;
IMAD.WIDE R8, R8, R11, c[0x0][0x160] ;
IMAD.WIDE R10, R10, R11, c[0x0][0x168] ;
LDG.E R9, [R8.64] ;
LDG.E R10, [R10.64] ;
IADD3 R15, R15, -0x1, RZ ;
IMAD.IADD R13, R13, 0x1, R2 ;
ISETP.NE.AND P1, PT, R15, RZ, PT ;
FMUL R17, R10, R9 ;
STG.E [R6.64], R17 ;
IMAD.WIDE R6, R2, 0x4, R6 ;
@P1 BRA 0x640 ;
BSYNC B0 ;
@!P2 EXIT ;
I2F.RP R8, R5 ;
IMAD.MOV.U32 R6, RZ, RZ, RZ ;
ISETP.NE.AND P0, PT, R4, RZ, PT ;
MUFU.RCP R8, R8 ;
IADD3 R7, R8, 0xffffffe, RZ ;
F2I.FTZ.U32.TRUNC.NTZ R7, R7 ;
IMAD.MOV R0, RZ, RZ, -R7 ;
IMAD R9, R0, R5, RZ ;
LOP3.LUT R0, RZ, R4, RZ, 0x33, !PT ;
IMAD.HI.U32 R6, R7, R9, R6 ;
IABS R7, c[0x0][0x184] ;
IABS R10, R13 ;
I2F.RP R11, R7 ;
IADD3 R23, R13, R2, RZ ;
IMAD.HI.U32 R14, R6, R10, RZ ;
IABS R21, R4 ;
IABS R20, R3 ;
IMAD.MOV R6, RZ, RZ, -R14 ;
LOP3.LUT R22, RZ, c[0x0][0x184], RZ, 0x33, !PT ;
LOP3.LUT R28, RZ, R4, RZ, 0x33, !PT ;
IMAD R10, R7, R6, R10 ;
MUFU.RCP R11, R11 ;
ISETP.GT.U32.AND P2, PT, R5, R10, PT ;
@!P2 IMAD.IADD R10, R10, 0x1, -R7.reuse ;
@!P2 IADD3 R14, R14, 0x1, RZ ;
IADD3 R8, R11, 0xffffffe, RZ ;
I2F.RP R11, R20 ;
ISETP.GE.U32.AND P3, PT, R10, R5, PT ;
IMAD.MOV.U32 R5, RZ, RZ, R7 ;
F2I.FTZ.U32.TRUNC.NTZ R9, R8 ;
@P3 IADD3 R14, R14, 0x1, RZ ;
MUFU.RCP R11, R11 ;
IMAD.MOV.U32 R8, RZ, RZ, RZ ;
IMAD.MOV R12, RZ, RZ, -R9 ;
IMAD R15, R12, R7, RZ ;
IABS R12, R23 ;
IMAD.HI.U32 R6, R9, R15, R8 ;
I2F.RP R15, R21 ;
IMAD.MOV.U32 R9, RZ, RZ, R12 ;
IMAD.HI.U32 R8, R6, R9, RZ ;
IMAD.MOV R12, RZ, RZ, -R8 ;
IMAD R10, R7, R12, R9 ;
IADD3 R9, R11, 0xffffffe, RZ ;
MUFU.RCP R15, R15 ;
ISETP.GT.U32.AND P5, PT, R5, R10, PT ;
F2I.FTZ.U32.TRUNC.NTZ R9, R9 ;
@!P5 IMAD.IADD R10, R10, 0x1, -R7 ;
IADD3 R12, R15, 0xffffffe, RZ ;
@!P5 IADD3 R8, R8, 0x1, RZ ;
ISETP.GE.U32.AND P1, PT, R10, R5, PT ;
F2I.FTZ.U32.TRUNC.NTZ R11, R12 ;
LOP3.LUT R10, R23, c[0x0][0x184], RZ, 0x3c, !PT ;
IADD3 R17, RZ, -R9, RZ ;
ISETP.GE.AND P4, PT, R10, RZ, PT ;
LOP3.LUT R10, R13, c[0x0][0x184], RZ, 0x3c, !PT ;
IMAD R17, R17, R20, RZ ;
ISETP.GE.AND P5, PT, R10, RZ, PT ;
@P1 IADD3 R8, R8, 0x1, RZ ;
ISETP.NE.AND P1, PT, RZ, c[0x0][0x184], PT ;
IMAD.MOV R10, RZ, RZ, -R11 ;
IMAD.MOV.U32 R15, RZ, RZ, R8 ;
IMAD R19, R10, R21, RZ ;
@!P4 IMAD.MOV R15, RZ, RZ, -R15 ;
IMAD.MOV.U32 R10, RZ, RZ, RZ ;
IMAD.MOV.U32 R8, RZ, RZ, RZ ;
SEL R12, R22, R15, !P1 ;
IMAD.HI.U32 R19, R11, R19, R10 ;
IABS R11, R3 ;
IABS R15, R4 ;
IMAD.MOV R10, RZ, RZ, -R12 ;
IABS R27, R12 ;
IMAD.HI.U32 R8, R9, R17, R8 ;
IMAD R9, R10, c[0x0][0x184], R23 ;
IADD3 R10, RZ, -R11, RZ ;
@!P5 IMAD.MOV R14, RZ, RZ, -R14 ;
IMAD.MOV R11, RZ, RZ, -R15 ;
IABS R18, R9 ;
IMAD.HI.U32 R15, R8, R27, RZ ;
SEL R16, R22, R14, !P1 ;
IMAD R27, R15, R10, R27 ;
IABS R25, R16 ;
IMAD.HI.U32 R14, R19, R18, RZ ;
LOP3.LUT R24, R16, R3, RZ, 0x3c, !PT ;
ISETP.GT.U32.AND P3, PT, R20, R27, PT ;
IMAD R18, R14, R11, R18 ;
IMAD.HI.U32 R17, R8, R25, RZ ;
ISETP.GT.U32.AND P5, PT, R21, R18, PT ;
IMAD R25, R17, R10, R25 ;
ISETP.GT.U32.AND P2, PT, R20, R25, PT ;
@!P3 IMAD.IADD R27, R27, 0x1, -R20 ;
@!P3 IADD3 R15, R15, 0x1, RZ ;
ISETP.GE.U32.AND P4, PT, R27, R20, PT ;
@!P5 IMAD.IADD R18, R18, 0x1, -R21 ;
@!P5 IADD3 R14, R14, 0x1, RZ ;
ISETP.GE.U32.AND P6, PT, R18, R21, PT ;
@!P2 IMAD.IADD R25, R25, 0x1, -R20 ;
LOP3.LUT R18, R12, R3, RZ, 0x3c, !PT ;
@!P2 IADD3 R17, R17, 0x1, RZ ;
ISETP.GE.AND P3, PT, R18, RZ, PT ;
LOP3.LUT R18, R9, R4, RZ, 0x3c, !PT ;
@P4 IADD3 R15, R15, 0x1, RZ ;
ISETP.GE.AND P4, PT, R18, RZ, PT ;
ISETP.GE.U32.AND P5, PT, R25, R20, PT ;
@P6 IADD3 R14, R14, 0x1, RZ ;
ISETP.NE.AND P6, PT, R3, RZ, PT ;
@!P3 IMAD.MOV R15, RZ, RZ, -R15 ;
LOP3.LUT R18, RZ, R3, RZ, 0x33, !PT ;
ISETP.GE.AND P3, PT, R24, RZ, PT ;
SEL R27, R18, R15, !P6 ;
@!P4 IADD3 R14, -R14, RZ, RZ ;
ISETP.NE.AND P4, PT, R4, RZ, PT ;
IMAD.MOV R15, RZ, RZ, -R27 ;
@P5 IADD3 R17, R17, 0x1, RZ ;
SEL R24, R28, R14, !P4 ;
IMAD R15, R3, R15, R12 ;
IMAD.MOV.U32 R25, RZ, RZ, R17 ;
IMAD.MOV R12, RZ, RZ, -R16 ;
IMAD R14, R27, c[0x0][0x17c], R24.reuse ;
IMAD.MOV R24, RZ, RZ, -R24 ;
@!P3 IMAD.MOV R25, RZ, RZ, -R25 ;
IMAD R17, R12, c[0x0][0x184], R13 ;
IMAD R12, R4, R24, R9 ;
SEL R9, R18, R25, !P6 ;
IABS R24, R17 ;
IMAD.MOV R25, RZ, RZ, -R9 ;
IMAD R25, R3, R25, R16 ;
IMAD.HI.U32 R16, R19, R24, RZ ;
IMAD R24, R16, R11, R24 ;
ISETP.GT.U32.AND P3, PT, R21, R24, PT ;
@!P3 IADD3 R24, R24, -R21.reuse, RZ ;
@!P3 IADD3 R16, R16, 0x1, RZ ;
ISETP.GE.U32.AND P2, PT, R24, R21, PT ;
LOP3.LUT R24, R17, R4, RZ, 0x3c, !PT ;
ISETP.GE.AND P5, PT, R24, RZ, PT ;
@P2 IADD3 R16, R16, 0x1, RZ ;
@!P5 IMAD.MOV R16, RZ, RZ, -R16 ;
SEL R16, R28, R16, !P4 ;
IMAD.MOV R24, RZ, RZ, -R16.reuse ;
IMAD R26, R9, c[0x0][0x17c], R16 ;
IMAD R17, R4.reuse, R24, R17 ;
IMAD.MOV.U32 R9, RZ, RZ, 0x4 ;
IMAD R24, R4, R25, R17 ;
IMAD.WIDE R26, R26, R9, c[0x0][0x160] ;
IMAD.WIDE R24, R24, R9, c[0x0][0x168] ;
LDG.E R27, [R26.64] ;
LDG.E R24, [R24.64] ;
IMAD R16, R4, R15, R12 ;
IMAD.WIDE R12, R13, R9, c[0x0][0x170] ;
IMAD.WIDE R14, R14, R9, c[0x0][0x160] ;
IMAD.WIDE R16, R16, R9, c[0x0][0x168] ;
IMAD.IADD R23, R23, 0x1, R2 ;
IABS R26, R23 ;
FMUL R29, R24, R27 ;
STG.E [R12.64], R29 ;
LDG.E R14, [R14.64] ;
LDG.E R17, [R16.64] ;
IMAD.HI.U32 R24, R6, R26, RZ ;
IMAD.MOV R25, RZ, RZ, -R24 ;
LOP3.LUT R15, R23, c[0x0][0x184], RZ, 0x3c, !PT ;
IMAD.WIDE R12, R2, 0x4, R12 ;
ISETP.GE.AND P5, PT, R15, RZ, PT ;
IMAD R26, R7, R25, R26 ;
ISETP.GT.U32.AND P3, PT, R5, R26, PT ;
@!P3 IMAD.IADD R26, R26, 0x1, -R7 ;
@!P3 IADD3 R24, R24, 0x1, RZ ;
ISETP.GE.U32.AND P2, PT, R26, R5, PT ;
@P2 IADD3 R24, R24, 0x1, RZ ;
@!P5 IADD3 R24, -R24, RZ, RZ ;
SEL R16, R22, R24, !P1 ;
IABS R27, R16 ;
IMAD.MOV R24, RZ, RZ, -R16 ;
IMAD R15, R24, c[0x0][0x184], R23 ;
IABS R26, R15 ;
LOP3.LUT R25, R15, R4, RZ, 0x3c, !PT ;
IMAD.HI.U32 R24, R19, R26, RZ ;
ISETP.GE.AND P5, PT, R25, RZ, PT ;
IMAD R26, R24, R11, R26 ;
IMAD.HI.U32 R25, R8, R27, RZ ;
ISETP.GT.U32.AND P3, PT, R21, R26, PT ;
IMAD R27, R25, R10, R27 ;
@!P3 IMAD.IADD R26, R26, 0x1, -R21 ;
@!P3 IADD3 R24, R24, 0x1, RZ ;
ISETP.GT.U32.AND P3, PT, R20, R27, PT ;
ISETP.GE.U32.AND P2, PT, R26, R21, PT ;
@!P3 IMAD.IADD R27, R27, 0x1, -R20 ;
@!P3 IADD3 R25, R25, 0x1, RZ ;
@P2 IADD3 R24, R24, 0x1, RZ ;
ISETP.GE.U32.AND P2, PT, R27, R20, PT ;
@!P5 IMAD.MOV R24, RZ, RZ, -R24 ;
SEL R28, R28, R24, !P4 ;
LOP3.LUT R24, R16, R3, RZ, 0x3c, !PT ;
@P2 IADD3 R25, R25, 0x1, RZ ;
ISETP.GE.AND P4, PT, R24, RZ, PT ;
@!P4 IMAD.MOV R25, RZ, RZ, -R25 ;
SEL R25, R18, R25, !P6 ;
IMAD.MOV R24, RZ, RZ, -R25 ;
IMAD R24, R3, R24, R16 ;
IADD3 R16, -R28, RZ, RZ ;
IMAD R15, R4.reuse, R16, R15 ;
IMAD R16, R25, c[0x0][0x17c], R28 ;
IMAD R24, R4, R24, R15 ;
FMUL R25, R17, R14 ;
IMAD.WIDE R14, R24, R9, c[0x0][0x168] ;
STG.E [R12.64], R25 ;
IMAD.WIDE R16, R16, R9, c[0x0][0x160] ;
LDG.E R14, [R14.64] ;
LDG.E R17, [R16.64] ;
IMAD.IADD R23, R23, 0x1, R2 ;
IABS R26, R23 ;
IMAD.HI.U32 R24, R6, R26, RZ ;
IMAD.MOV R27, RZ, RZ, -R24 ;
IMAD R26, R7, R27, R26 ;
ISETP.GT.U32.AND P3, PT, R5, R26, PT ;
@!P3 IMAD.IADD R26, R26, 0x1, -R7 ;
LOP3.LUT R7, R23, c[0x0][0x184], RZ, 0x3c, !PT ;
@!P3 IADD3 R24, R24, 0x1, RZ ;
ISETP.GE.U32.AND P2, PT, R26, R5, PT ;
ISETP.GE.AND P4, PT, R7, RZ, PT ;
@P2 IADD3 R24, R24, 0x1, RZ ;
@!P4 IMAD.MOV R24, RZ, RZ, -R24 ;
SEL R22, R22, R24, !P1 ;
IABS R25, R22 ;
IMAD.MOV R16, RZ, RZ, -R22 ;
IMAD R7, R16, c[0x0][0x184], R23 ;
IMAD.HI.U32 R15, R8, R25, RZ ;
IABS R16, R7 ;
IMAD.HI.U32 R8, R19, R16, RZ ;
IMAD R19, R15, R10, R25 ;
IMAD R10, R8, R11, R16 ;
LOP3.LUT R11, R7, R4, RZ, 0x3c, !PT ;
ISETP.GT.U32.AND P5, PT, R20, R19, PT ;
ISETP.GT.U32.AND P4, PT, R21, R10, PT ;
@!P5 IMAD.IADD R19, R19, 0x1, -R20 ;
@!P5 IADD3 R15, R15, 0x1, RZ ;
@!P4 IADD3 R10, R10, -R21.reuse, RZ ;
ISETP.GE.U32.AND P3, PT, R19, R20, PT ;
ISETP.GE.U32.AND P2, PT, R10, R21, PT ;
LOP3.LUT R10, R22, R3, RZ, 0x3c, !PT ;
ISETP.GE.AND P5, PT, R11, RZ, PT ;
ISETP.GE.AND P1, PT, R10, RZ, PT ;
@!P4 IADD3 R8, R8, 0x1, RZ ;
@P3 IADD3 R15, R15, 0x1, RZ ;
@P2 IADD3 R8, R8, 0x1, RZ ;
@!P5 IMAD.MOV R8, RZ, RZ, -R8 ;
@!P1 IMAD.MOV R15, RZ, RZ, -R15 ;
SEL R8, R0, R8, !P0 ;
SEL R15, R18, R15, !P6 ;
IMAD.MOV R11, RZ, RZ, -R8 ;
IMAD.MOV R10, RZ, RZ, -R15 ;
IMAD R7, R4.reuse, R11, R7 ;
IMAD R10, R3, R10, R22 ;
IMAD R8, R15, c[0x0][0x17c], R8 ;
IMAD R16, R4, R10, R7 ;
IMAD.WIDE R10, R2, 0x4, R12 ;
FMUL R7, R14, R17 ;
IMAD.WIDE R14, R16, R9, c[0x0][0x168] ;
STG.E [R10.64], R7 ;
IMAD.WIDE R8, R8, R9, c[0x0][0x160] ;
LDG.E R14, [R14.64] ;
LDG.E R9, [R8.64] ;
IMAD.WIDE R16, R2, 0x4, R10 ;
IMAD.IADD R13, R23, 0x1, R2 ;
ISETP.GE.AND P1, PT, R13, c[0x0][0x188], PT ;
FMUL R19, R14, R9 ;
STG.E [R16.64], R19 ;
@P1 CALL.REL.NOINC 0x1c70 ;
BRA 0xc60 ;
EXIT ;
BRA 0x1c80;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
```
|
```amdasm
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z7cu_kronPKfS0_Pfiiiii ; -- Begin function _Z7cu_kronPKfS0_Pfiiiii
.globl _Z7cu_kronPKfS0_Pfiiiii
.p2align 8
.type _Z7cu_kronPKfS0_Pfiiiii,@function
_Z7cu_kronPKfS0_Pfiiiii: ; @_Z7cu_kronPKfS0_Pfiiiii
; %bb.0:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x3c
s_load_b32 s12, s[0:1], 0x28
s_add_u32 s2, s0, 48
s_addc_u32 s3, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s19, s4, 0xffff
s_mov_b32 s4, exec_lo
v_mad_u64_u32 v[1:2], null, s15, s19, v[0:1]
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s12, v1
s_cbranch_execz .LBB0_3
; %bb.1: ; %.lr.ph.preheader
s_load_b128 s[4:7], s[0:1], 0x18
s_load_b32 s20, s[2:3], 0x0
s_waitcnt lgkmcnt(0)
s_ashr_i32 s8, s5, 31
s_ashr_i32 s13, s7, 31
s_add_i32 s9, s5, s8
s_add_i32 s14, s7, s13
s_xor_b32 s9, s9, s8
s_xor_b32 s14, s14, s13
v_cvt_f32_u32_e32 v0, s9
s_sub_i32 s11, 0, s9
s_xor_b32 s8, s13, s8
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v0, v0
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v0, 0x4f7ffffe, v0
v_cvt_u32_f32_e32 v0, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s10, v0
s_mul_i32 s11, s11, s10
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_hi_u32 s11, s10, s11
s_add_i32 s10, s10, s11
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_hi_u32 s10, s14, s10
s_mul_i32 s11, s10, s9
s_add_i32 s15, s10, 1
s_sub_i32 s11, s14, s11
s_delay_alu instid0(SALU_CYCLE_1)
s_sub_i32 s16, s11, s9
s_cmp_ge_u32 s11, s9
s_cselect_b32 s10, s15, s10
s_cselect_b32 s11, s16, s11
s_add_i32 s15, s10, 1
s_cmp_ge_u32 s11, s9
s_cselect_b32 s9, s15, s10
s_ashr_i32 s10, s4, 31
s_ashr_i32 s16, s6, 31
s_add_i32 s4, s4, s10
s_add_i32 s6, s6, s16
s_xor_b32 s11, s4, s10
s_xor_b32 s6, s6, s16
v_cvt_f32_u32_e32 v0, s11
s_sub_i32 s15, 0, s11
s_xor_b32 s10, s16, s10
s_xor_b32 s9, s9, s8
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v0, v0
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v0, 0x4f7ffffe, v0
v_cvt_u32_f32_e32 v0, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_readfirstlane_b32 s4, v0
v_cvt_f32_u32_e32 v0, s14
s_mul_i32 s15, s15, s4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_rcp_iflag_f32_e32 v0, v0
s_mul_hi_u32 s15, s4, s15
s_add_i32 s4, s4, s15
s_delay_alu instid0(SALU_CYCLE_1)
s_mul_hi_u32 s15, s6, s4
s_sub_i32 s4, s9, s8
s_mul_i32 s16, s15, s11
s_add_i32 s8, s15, 1
s_sub_i32 s6, s6, s16
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v0, 0x4f7ffffe, v0
s_sub_i32 s9, s6, s11
s_cmp_ge_u32 s6, s11
s_cselect_b32 s8, s8, s15
s_cselect_b32 s6, s9, s6
s_add_i32 s9, s8, 1
s_cmp_ge_u32 s6, s11
v_cvt_u32_f32_e32 v0, v0
s_cselect_b32 s6, s9, s8
s_ashr_i32 s15, s4, 31
s_xor_b32 s6, s6, s10
s_add_i32 s8, s4, s15
s_sub_i32 s6, s6, s10
s_xor_b32 s17, s8, s15
s_ashr_i32 s16, s6, 31
v_cvt_f32_u32_e32 v2, s17
s_add_i32 s9, s6, s16
s_sub_i32 s2, 0, s14
s_xor_b32 s18, s9, s16
v_mul_lo_u32 v4, s2, v0
v_cvt_f32_u32_e32 v3, s18
v_rcp_iflag_f32_e32 v2, v2
s_sub_i32 s2, 0, s17
s_sub_i32 s3, 0, s18
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_rcp_iflag_f32_e32 v3, v3
v_mul_hi_u32 v4, v0, v4
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v2, 0x4f7ffffe, v2
v_dual_mul_f32 v3, 0x4f7ffffe, v3 :: v_dual_add_nc_u32 v0, v0, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cvt_u32_f32_e32 v2, v2
v_cvt_u32_f32_e32 v3, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_lo_u32 v5, s2, v2
v_mul_lo_u32 v6, s3, v3
s_clause 0x1
s_load_b128 s[8:11], s[0:1], 0x0
s_load_b64 s[2:3], s[0:1], 0x10
s_mul_i32 s1, s20, s19
s_mov_b32 s19, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_mul_hi_u32 v5, v2, v5
s_sub_i32 s20, 0, s7
v_mul_hi_u32 v6, v3, v6
v_add_nc_u32_e32 v4, v2, v5
s_delay_alu instid0(VALU_DEP_2)
v_add_nc_u32_e32 v3, v3, v6
.LBB0_2: ; %.lr.ph
; =>This Inner Loop Header: Depth=1
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v5, v1, v2
v_xor_b32_e32 v5, v5, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v6, v5, v0
v_mul_lo_u32 v7, v6, s14
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v5, v5, v7
v_add_nc_u32_e32 v7, 1, v6
v_subrev_nc_u32_e32 v8, s14, v5
v_cmp_le_u32_e32 vcc_lo, s14, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_dual_cndmask_b32 v6, v6, v7 :: v_dual_cndmask_b32 v5, v5, v8
v_xor_b32_e32 v8, s13, v2
v_add_nc_u32_e32 v7, 1, v6
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_le_u32_e32 vcc_lo, s14, v5
v_cndmask_b32_e32 v5, v6, v7, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_xor_b32_e32 v7, v5, v8
v_sub_nc_u32_e32 v9, v7, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v10, 31, v9
v_mad_u64_u32 v[5:6], null, s20, v9, v[1:2]
v_add_nc_u32_e32 v6, v9, v10
v_mul_lo_u32 v9, v9, s7
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_ashrrev_i32_e32 v11, 31, v5
v_xor_b32_e32 v6, v6, v10
v_xor_b32_e32 v10, s16, v10
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_sub_nc_u32_e32 v9, v11, v9
v_mul_hi_u32 v12, v6, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v9, v1, v9
v_mul_lo_u32 v13, v12, s18
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_xor_b32_e32 v9, v9, v11
v_mul_hi_u32 v14, v9, v4
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v6, v6, v13
v_add_nc_u32_e32 v13, 1, v12
v_subrev_nc_u32_e32 v15, s18, v6
v_cmp_le_u32_e32 vcc_lo, s18, v6
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cndmask_b32_e32 v12, v12, v13, vcc_lo
v_cndmask_b32_e32 v6, v6, v15, vcc_lo
v_mul_lo_u32 v13, v14, s17
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_nc_u32_e32 v15, 1, v12
v_cmp_le_u32_e32 vcc_lo, s18, v6
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_sub_nc_u32_e32 v9, v9, v13
v_cndmask_b32_e32 v6, v12, v15, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v13, s17, v9
v_xor_b32_e32 v6, v6, v10
v_cmp_le_u32_e32 vcc_lo, s17, v9
v_add_nc_u32_e32 v12, 1, v14
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v10, v6, v10
v_dual_cndmask_b32 v9, v9, v13 :: v_dual_cndmask_b32 v12, v14, v12
v_xor_b32_e32 v6, s15, v11
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_mul_lo_u32 v13, v10, s6
v_cmp_le_u32_e32 vcc_lo, s17, v9
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_nc_u32_e32 v11, 1, v12
v_add_nc_u32_e32 v7, v7, v6
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v9, v12, v11, vcc_lo
v_sub_nc_u32_e32 v7, v7, v13
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_xor_b32_e32 v9, v9, v6
v_sub_nc_u32_e32 v7, v7, v8
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v6, v9, v6
v_sub_nc_u32_e32 v11, v7, v9
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[7:8], null, v10, s5, v[6:7]
v_mad_u64_u32 v[9:10], null, s4, v11, v[5:6]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v8, 31, v7
v_ashrrev_i32_e32 v10, 31, v9
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[5:6], 2, v[7:8]
v_lshlrev_b64 v[7:8], 2, v[9:10]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v5, vcc_lo, s8, v5
v_add_co_ci_u32_e32 v6, vcc_lo, s9, v6, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v7, vcc_lo, s10, v7
v_add_co_ci_u32_e32 v8, vcc_lo, s11, v8, vcc_lo
global_load_b32 v9, v[5:6], off
global_load_b32 v7, v[7:8], off
v_lshlrev_b64 v[5:6], 2, v[1:2]
v_add_nc_u32_e32 v1, s1, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cmp_le_i32_e32 vcc_lo, s12, v1
v_add_co_u32 v5, s0, s2, v5
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v6, s0, s3, v6, s0
s_or_b32 s19, vcc_lo, s19
s_waitcnt vmcnt(0)
v_mul_f32_e32 v2, v9, v7
global_store_b32 v[5:6], v2, off
s_and_not1_b32 exec_lo, exec_lo, s19
s_cbranch_execnz .LBB0_2
.LBB0_3: ; %._crit_edge
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z7cu_kronPKfS0_Pfiiiii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 304
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 16
.amdhsa_next_free_sgpr 21
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z7cu_kronPKfS0_Pfiiiii, .Lfunc_end0-_Z7cu_kronPKfS0_Pfiiiii
; -- End function
.section .AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1132
; NumSgprs: 23
; NumVgprs: 16
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 23
; NumVGPRsForWavesPerEU: 16
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object ; @__hip_cuid_
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0 ; 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 36
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: by_value
- .offset: 48
.size: 4
.value_kind: hidden_block_count_x
- .offset: 52
.size: 4
.value_kind: hidden_block_count_y
- .offset: 56
.size: 4
.value_kind: hidden_block_count_z
- .offset: 60
.size: 2
.value_kind: hidden_group_size_x
- .offset: 62
.size: 2
.value_kind: hidden_group_size_y
- .offset: 64
.size: 2
.value_kind: hidden_group_size_z
- .offset: 66
.size: 2
.value_kind: hidden_remainder_x
- .offset: 68
.size: 2
.value_kind: hidden_remainder_y
- .offset: 70
.size: 2
.value_kind: hidden_remainder_z
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 112
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 304
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z7cu_kronPKfS0_Pfiiiii
.private_segment_fixed_size: 0
.sgpr_count: 23
.sgpr_spill_count: 0
.symbol: _Z7cu_kronPKfS0_Pfiiiii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 16
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
```
| 9,210 | 7,045 |
485 |
Convert the following CUDA host assembly code to AMD host assembly:
```cudaasm
.file "tmpxft_000d19be_00000000-6_cu_kron.cudafe1.cpp"
.text
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z37__device_stub__Z7cu_kronPKfS0_PfiiiiiPKfS0_Pfiiiii
.type _Z37__device_stub__Z7cu_kronPKfS0_PfiiiiiPKfS0_Pfiiiii, @function
_Z37__device_stub__Z7cu_kronPKfS0_PfiiiiiPKfS0_Pfiiiii:
.LFB2051:
.cfi_startproc
endbr64
subq $200, %rsp
.cfi_def_cfa_offset 208
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
leaq 208(%rsp), %rax
movq %rax, 160(%rsp)
leaq 216(%rsp), %rax
movq %rax, 168(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 216
pushq 56(%rsp)
.cfi_def_cfa_offset 224
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z7cu_kronPKfS0_Pfiiiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 208
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z37__device_stub__Z7cu_kronPKfS0_PfiiiiiPKfS0_Pfiiiii, .-_Z37__device_stub__Z7cu_kronPKfS0_PfiiiiiPKfS0_Pfiiiii
.globl _Z7cu_kronPKfS0_Pfiiiii
.type _Z7cu_kronPKfS0_Pfiiiii, @function
_Z7cu_kronPKfS0_Pfiiiii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 24
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
call _Z37__device_stub__Z7cu_kronPKfS0_PfiiiiiPKfS0_Pfiiiii
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z7cu_kronPKfS0_Pfiiiii, .-_Z7cu_kronPKfS0_Pfiiiii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z7cu_kronPKfS0_Pfiiiii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z7cu_kronPKfS0_Pfiiiii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
```
|
```amdasm
.text
.file "cu_kron.hip"
.globl _Z22__device_stub__cu_kronPKfS0_Pfiiiii # -- Begin function _Z22__device_stub__cu_kronPKfS0_Pfiiiii
.type _Z22__device_stub__cu_kronPKfS0_Pfiiiii,@function
_Z22__device_stub__cu_kronPKfS0_Pfiiiii: # @_Z22__device_stub__cu_kronPKfS0_Pfiiiii
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $160, %rsp
.cfi_def_cfa_offset 208
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 56(%rsp), %rax
movq %rdi, (%rax)
leaq 48(%rsp), %rdi
movq %rsi, (%rdi)
leaq 40(%rsp), %rsi
movq %rdx, (%rsi)
leaq 20(%rsp), %rdx
movl %ecx, (%rdx)
leaq 16(%rsp), %rcx
movl %r8d, (%rcx)
leaq 12(%rsp), %r8
movl %r9d, (%r8)
leaq 96(%rsp), %rbx
movq %rax, (%rbx)
movq %rdi, 8(%rbx)
movq %rsi, 16(%rbx)
movq %rdx, 24(%rbx)
movq %rcx, 32(%rbx)
movq %r8, 40(%rbx)
leaq 208(%rsp), %rax
movq %rax, 48(%rbx)
leaq 216(%rsp), %rax
movq %rax, 56(%rbx)
leaq 80(%rsp), %r14
leaq 64(%rsp), %r15
leaq 32(%rsp), %r12
leaq 24(%rsp), %r13
movq %r14, %rdi
movq %r15, %rsi
movq %r12, %rdx
movq %r13, %rcx
callq __hipPopCallConfiguration
movq (%r14), %rsi
movl 8(%r14), %edx
movq (%r15), %rcx
movl 8(%r15), %r8d
movl $_Z7cu_kronPKfS0_Pfiiiii, %edi
movq %rbx, %r9
pushq (%r13)
.cfi_adjust_cfa_offset 8
pushq (%r12)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $176, %rsp
.cfi_adjust_cfa_offset -176
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z22__device_stub__cu_kronPKfS0_Pfiiiii, .Lfunc_end0-_Z22__device_stub__cu_kronPKfS0_Pfiiiii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, %rdi
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7cu_kronPKfS0_Pfiiiii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z7cu_kronPKfS0_Pfiiiii,@object # @_Z7cu_kronPKfS0_Pfiiiii
.section .rodata,"a",@progbits
.globl _Z7cu_kronPKfS0_Pfiiiii
.p2align 3, 0x0
_Z7cu_kronPKfS0_Pfiiiii:
.quad _Z22__device_stub__cu_kronPKfS0_Pfiiiii
.size _Z7cu_kronPKfS0_Pfiiiii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z7cu_kronPKfS0_Pfiiiii"
.size .L__unnamed_1, 24
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__cu_kronPKfS0_Pfiiiii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z7cu_kronPKfS0_Pfiiiii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
```
| 2,157 | 2,277 |
486 |
Convert the following CUDA device assembly code to AMD device assembly:
```cudaasm
code for sm_80
Function : _Z12kernelDeductPdS_S_m
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ;
S2R R0, SR_CTAID.X ;
S2R R3, SR_TID.X ;
IMAD R0, R0, c[0x0][0x0], R3 ;
ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x178], PT ;
ISETP.GE.U32.AND.EX P0, PT, RZ, c[0x0][0x17c], PT, P0 ;
@P0 EXIT ;
IMAD.MOV.U32 R11, RZ, RZ, RZ ;
ULDC.64 UR4, c[0x0][0x118] ;
IMAD.MOV.U32 R10, RZ, RZ, c[0x0][0xc] ;
IMAD.SHL.U32 R8, R0.reuse, 0x8, RZ ;
SHF.L.U64.HI R9, R0, 0x3, R11 ;
IADD3 R4, P1, R8.reuse, c[0x0][0x160], RZ ;
IADD3 R6, P0, R8, c[0x0][0x168], RZ ;
IADD3.X R5, R9.reuse, c[0x0][0x164], RZ, P1, !PT ;
IADD3.X R7, R9, c[0x0][0x16c], RZ, P0, !PT ;
LDG.E.64 R4, [R4.64] ;
LDG.E.64 R2, [R6.64] ;
IADD3 R8, P0, R8, c[0x0][0x170], RZ ;
IMAD R13, R10, c[0x0][0x0], RZ ;
IADD3.X R9, R9, c[0x0][0x174], RZ, P0, !PT ;
IADD3 R0, P0, R13, R0, RZ ;
IMAD.X R11, RZ, RZ, R11, P0 ;
ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x178], PT ;
ISETP.GE.U32.AND.EX P0, PT, R11, c[0x0][0x17c], PT, P0 ;
DADD R2, -R2, R4 ;
STG.E.64 [R8.64], R2 ;
@!P0 BRA 0xa0 ;
EXIT ;
BRA 0x1d0;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
```
|
```amdasm
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z12kernelDeductPdS_S_m ; -- Begin function _Z12kernelDeductPdS_S_m
.globl _Z12kernelDeductPdS_S_m
.p2align 8
.type _Z12kernelDeductPdS_S_m,@function
_Z12kernelDeductPdS_S_m: ; @_Z12kernelDeductPdS_S_m
; %bb.0:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b256 s[4:11], s[0:1], 0x0
s_add_u32 s0, s0, 32
s_addc_u32 s1, s1, 0
s_mov_b32 s3, exec_lo
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
v_mov_b32_e32 v2, 0
v_cmpx_gt_u64_e64 s[10:11], v[1:2]
s_cbranch_execz .LBB0_3
; %bb.1: ; %.lr.ph.preheader
s_load_b32 s0, s[0:1], 0x0
v_lshlrev_b64 v[3:4], 3, v[1:2]
s_mov_b32 s3, 0
s_waitcnt lgkmcnt(0)
s_mul_i32 s2, s0, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_lshl_b64 s[12:13], s[2:3], 3
.LBB0_2: ; %.lr.ph
; =>This Inner Loop Header: Depth=1
s_delay_alu instid0(VALU_DEP_1)
v_add_co_u32 v5, vcc_lo, s4, v3
v_add_co_ci_u32_e32 v6, vcc_lo, s5, v4, vcc_lo
v_add_co_u32 v7, vcc_lo, s6, v3
v_add_co_ci_u32_e32 v8, vcc_lo, s7, v4, vcc_lo
v_add_co_u32 v1, vcc_lo, v1, s2
global_load_b64 v[5:6], v[5:6], off
global_load_b64 v[7:8], v[7:8], off
v_add_co_ci_u32_e32 v2, vcc_lo, 0, v2, vcc_lo
s_waitcnt vmcnt(0)
v_add_f64 v[5:6], v[5:6], -v[7:8]
v_add_co_u32 v7, vcc_lo, s8, v3
v_add_co_ci_u32_e32 v8, vcc_lo, s9, v4, vcc_lo
v_cmp_le_u64_e32 vcc_lo, s[10:11], v[1:2]
v_add_co_u32 v3, s0, v3, s12
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v4, s0, s13, v4, s0
s_or_b32 s3, vcc_lo, s3
global_store_b64 v[7:8], v[5:6], off
s_and_not1_b32 exec_lo, exec_lo, s3
s_cbranch_execnz .LBB0_2
.LBB0_3: ; %._crit_edge
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z12kernelDeductPdS_S_m
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z12kernelDeductPdS_S_m, .Lfunc_end0-_Z12kernelDeductPdS_S_m
; -- End function
.section .AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 244
; NumSgprs: 18
; NumVgprs: 9
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 9
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object ; @__hip_cuid_
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0 ; 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 8
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z12kernelDeductPdS_S_m
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z12kernelDeductPdS_S_m.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
```
| 740 | 2,868 |
487 |
Convert the following CUDA host assembly code to AMD host assembly:
```cudaasm
.file "tmpxft_0013de78_00000000-6_pgp1.cudafe1.cpp"
.text
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z37__device_stub__Z12kernelDeductPdS_S_mPdS_S_m
.type _Z37__device_stub__Z12kernelDeductPdS_S_mPdS_S_m, @function
_Z37__device_stub__Z12kernelDeductPdS_S_mPdS_S_m:
.LFB2082:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %rcx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z12kernelDeductPdS_S_m(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z37__device_stub__Z12kernelDeductPdS_S_mPdS_S_m, .-_Z37__device_stub__Z12kernelDeductPdS_S_mPdS_S_m
.globl _Z12kernelDeductPdS_S_m
.type _Z12kernelDeductPdS_S_m, @function
_Z12kernelDeductPdS_S_m:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z37__device_stub__Z12kernelDeductPdS_S_mPdS_S_m
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z12kernelDeductPdS_S_m, .-_Z12kernelDeductPdS_S_m
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%lu\n"
.LC1:
.string "%lf"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC2:
.string "cudaSetDevice check failed. You must have at least one Nvidia GPU!"
.section .rodata.str1.1
.LC3:
.string "ERROR: %s\n"
.LC4:
.string "Can't allocate video memory"
.section .rodata.str1.8
.align 8
.LC5:
.string "Can't copy from ram to videomemory"
.align 8
.LC6:
.string "Can't copy from videomemory to ram"
.section .rodata.str1.1
.LC7:
.string "%.10e "
.LC8:
.string "\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $72, %rsp
.cfi_def_cfa_offset 128
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movq %rsp, %rsi
leaq .LC0(%rip), %rdi
call __isoc23_scanf@PLT
movq (%rsp), %rbp
leaq 0(,%rbp,8), %rbx
movq %rbx, %rdi
call malloc@PLT
movq %rax, %r12
movq %rbx, %rdi
call malloc@PLT
movq %rax, %r13
movq %rbx, %rdi
call malloc@PLT
movq %rax, %r14
testq %rbp, %rbp
je .L12
movq %r12, %rbp
movl $0, %ebx
leaq .LC1(%rip), %r15
.L13:
movq %rbp, %rsi
movq %r15, %rdi
movl $0, %eax
call __isoc23_scanf@PLT
addq $1, %rbx
movq (%rsp), %rax
addq $8, %rbp
cmpq %rax, %rbx
jb .L13
testq %rax, %rax
je .L12
movq %r13, %rbp
movl $0, %ebx
leaq .LC1(%rip), %r15
.L14:
movq %rbp, %rsi
movq %r15, %rdi
movl $0, %eax
call __isoc23_scanf@PLT
addq $1, %rbx
addq $8, %rbp
cmpq (%rsp), %rbx
jb .L14
.L12:
movl $0, %edi
call cudaSetDevice@PLT
testl %eax, %eax
jne .L30
movq (%rsp), %rax
leaq 0(,%rax,8), %rsi
leaq 8(%rsp), %rdi
call cudaMalloc@PLT
testl %eax, %eax
jne .L31
movq (%rsp), %rax
leaq 0(,%rax,8), %rsi
leaq 16(%rsp), %rdi
call cudaMalloc@PLT
testl %eax, %eax
jne .L32
movq (%rsp), %rax
leaq 0(,%rax,8), %rsi
leaq 24(%rsp), %rdi
call cudaMalloc@PLT
testl %eax, %eax
jne .L33
movq (%rsp), %rax
leaq 0(,%rax,8), %rdx
movl $1, %ecx
movq %r12, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L34
movq (%rsp), %rax
leaq 0(,%rax,8), %rdx
movl $1, %ecx
movq %r13, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L35
movl $512, 44(%rsp)
movl $1, 48(%rsp)
movl $16384, 32(%rsp)
movl $1, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L36
.L22:
movq (%rsp), %rax
leaq 0(,%rax,8), %rdx
movl $2, %ecx
movq 24(%rsp), %rsi
movq %r14, %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L37
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movl $0, %ebx
leaq .LC7(%rip), %rbp
.L24:
cmpq (%rsp), %rbx
jnb .L38
movsd (%r14,%rbx,8), %xmm0
movq %rbp, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $1, %rbx
jmp .L24
.L30:
leaq .LC2(%rip), %rdx
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
.L16:
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L39
movl $0, %eax
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L31:
.cfi_restore_state
leaq .LC4(%rip), %rdx
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L16
.L32:
leaq .LC4(%rip), %rdx
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L16
.L33:
leaq .LC4(%rip), %rdx
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L16
.L34:
leaq .LC5(%rip), %rdx
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L16
.L35:
leaq .LC5(%rip), %rdx
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L16
.L36:
movq (%rsp), %rcx
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z37__device_stub__Z12kernelDeductPdS_S_mPdS_S_m
jmp .L22
.L37:
leaq .LC6(%rip), %rdx
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L16
.L38:
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L16
.L39:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC9:
.string "_Z12kernelDeductPdS_S_m"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC9(%rip), %rdx
movq %rdx, %rcx
leaq _Z12kernelDeductPdS_S_m(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
```
|
```amdasm
.text
.file "pgp1.hip"
.globl _Z27__device_stub__kernelDeductPdS_S_m # -- Begin function _Z27__device_stub__kernelDeductPdS_S_m
.type _Z27__device_stub__kernelDeductPdS_S_m,@function
_Z27__device_stub__kernelDeductPdS_S_m: # @_Z27__device_stub__kernelDeductPdS_S_m
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $112, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 40(%rsp), %rax
movq %rdi, (%rax)
leaq 32(%rsp), %rdi
movq %rsi, (%rdi)
leaq 24(%rsp), %rsi
movq %rdx, (%rsi)
leaq 16(%rsp), %rdx
movq %rcx, (%rdx)
leaq 80(%rsp), %rbx
movq %rax, (%rbx)
movq %rdi, 8(%rbx)
movq %rsi, 16(%rbx)
movq %rdx, 24(%rbx)
leaq 64(%rsp), %r14
leaq 48(%rsp), %r15
leaq 8(%rsp), %r12
movq %rsp, %r13
movq %r14, %rdi
movq %r15, %rsi
movq %r12, %rdx
movq %r13, %rcx
callq __hipPopCallConfiguration
movq (%r14), %rsi
movl 8(%r14), %edx
movq (%r15), %rcx
movl 8(%r15), %r8d
movl $_Z12kernelDeductPdS_S_m, %edi
movq %rbx, %r9
pushq (%r13)
.cfi_adjust_cfa_offset 8
pushq (%r12)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $128, %rsp
.cfi_adjust_cfa_offset -128
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z27__device_stub__kernelDeductPdS_S_m, .Lfunc_end0-_Z27__device_stub__kernelDeductPdS_S_m
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $32, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rsp, %rbx
movl $.L.str, %edi
movq %rbx, %rsi
xorl %eax, %eax
callq __isoc23_scanf
movq (%rbx), %r12
leaq (,%r12,8), %rbx
movq %rbx, %rdi
callq malloc
movq %rax, %r15
movq %rbx, %rdi
callq malloc
movq %rax, %r14
movq %rbx, %rdi
callq malloc
movq %rax, %rbx
testq %r12, %r12
je .LBB1_6
# %bb.1: # %.lr.ph.preheader
movq %r15, %r12
xorl %r13d, %r13d
.LBB1_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl $.L.str.1, %edi
movq %r12, %rsi
xorl %eax, %eax
callq __isoc23_scanf
incq %r13
movq (%rsp), %rax
addq $8, %r12
cmpq %rax, %r13
jb .LBB1_2
# %bb.3: # %.preheader
testq %rax, %rax
je .LBB1_6
# %bb.4: # %.lr.ph39.preheader
movq %r14, %r12
xorl %r13d, %r13d
.LBB1_5: # %.lr.ph39
# =>This Inner Loop Header: Depth=1
movl $.L.str.1, %edi
movq %r12, %rsi
xorl %eax, %eax
callq __isoc23_scanf
incq %r13
addq $8, %r12
cmpq (%rsp), %r13
jb .LBB1_5
.LBB1_6: # %._crit_edge
xorl %edi, %edi
callq hipSetDevice
testl %eax, %eax
je .LBB1_8
# %bb.7:
movl $.L.str.2, %edi
movl $.L.str.3, %esi
jmp .LBB1_10
.LBB1_8:
movq (%rsp), %rsi
shlq $3, %rsi
leaq 24(%rsp), %rdi
callq hipMalloc
testl %eax, %eax
jne .LBB1_9
# %bb.11:
movq (%rsp), %rsi
shlq $3, %rsi
leaq 16(%rsp), %rdi
callq hipMalloc
testl %eax, %eax
jne .LBB1_9
# %bb.12:
movq (%rsp), %rsi
shlq $3, %rsi
leaq 8(%rsp), %rdi
callq hipMalloc
testl %eax, %eax
je .LBB1_13
.LBB1_9:
movl $.L.str.2, %edi
movl $.L.str.4, %esi
.LBB1_10:
xorl %eax, %eax
callq printf
.LBB1_24:
xorl %eax, %eax
addq $32, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB1_13:
.cfi_def_cfa_offset 80
movq 24(%rsp), %rdi
movq (%rsp), %rdx
shlq $3, %rdx
movq %r15, %rsi
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB1_14
# %bb.15:
movq 16(%rsp), %rdi
movq (%rsp), %rdx
shlq $3, %rdx
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
je .LBB1_16
.LBB1_14:
movl $.L.str.2, %edi
movl $.L.str.5, %esi
jmp .LBB1_10
.LBB1_16:
movabsq $4294967808, %rdx # imm = 0x100000200
leaq 15872(%rdx), %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_18
# %bb.17:
movq 24(%rsp), %rdi
movq 16(%rsp), %rsi
movq 8(%rsp), %rdx
movq (%rsp), %rcx
callq _Z27__device_stub__kernelDeductPdS_S_m
.LBB1_18:
movq 8(%rsp), %rsi
movq (%rsp), %rdx
shlq $3, %rdx
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
je .LBB1_20
# %bb.19:
movl $.L.str.2, %edi
movl $.L.str.6, %esi
jmp .LBB1_10
.LBB1_20:
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
cmpq $0, (%rsp)
je .LBB1_23
# %bb.21: # %.lr.ph42.preheader
xorl %r14d, %r14d
.LBB1_22: # %.lr.ph42
# =>This Inner Loop Header: Depth=1
movsd (%rbx,%r14,8), %xmm0 # xmm0 = mem[0],zero
movl $.L.str.7, %edi
movb $1, %al
callq printf
incq %r14
cmpq (%rsp), %r14
jb .LBB1_22
.LBB1_23: # %._crit_edge43
movl $10, %edi
callq putchar@PLT
jmp .LBB1_24
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, %rdi
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12kernelDeductPdS_S_m, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z12kernelDeductPdS_S_m,@object # @_Z12kernelDeductPdS_S_m
.section .rodata,"a",@progbits
.globl _Z12kernelDeductPdS_S_m
.p2align 3, 0x0
_Z12kernelDeductPdS_S_m:
.quad _Z27__device_stub__kernelDeductPdS_S_m
.size _Z12kernelDeductPdS_S_m, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%lu\n"
.size .L.str, 5
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "%lf"
.size .L.str.1, 4
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "ERROR: %s\n"
.size .L.str.2, 11
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "hipSetDevice check failed. You must have at least one Nvidia GPU!"
.size .L.str.3, 66
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Can't allocate video memory"
.size .L.str.4, 28
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "Can't copy from ram to videomemory"
.size .L.str.5, 35
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "Can't copy from videomemory to ram"
.size .L.str.6, 35
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "%.10e "
.size .L.str.7, 7
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z12kernelDeductPdS_S_m"
.size .L__unnamed_1, 24
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z27__device_stub__kernelDeductPdS_S_m
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z12kernelDeductPdS_S_m
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
```
| 4,424 | 4,519 |
490 |
Convert the following CUDA device assembly code to AMD device assembly:
```cudaasm
code for sm_80
Function : _Z13unpack_bottomiiiPdS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ;
S2R R7, SR_CTAID.X ;
IMAD.MOV.U32 R6, RZ, RZ, c[0x0][0x168] ;
S2R R2, SR_TID.X ;
IMAD.SHL.U32 R0, R6, 0x2, RZ ;
IADD3 R4, -R0, c[0x0][0x160], RZ ;
IMAD R7, R7, c[0x0][0x0], R2 ;
IMAD R2, R4, c[0x0][0x180], RZ ;
ISETP.GE.AND P0, PT, R7, R2, PT ;
@P0 EXIT ;
HFMA2.MMA R5, -RZ, RZ, 0, 4.76837158203125e-07 ;
ULDC.64 UR4, c[0x0][0x118] ;
IMAD.WIDE R2, R7, R5, c[0x0][0x178] ;
LDG.E.64 R2, [R2.64] ;
IABS R11, R4.reuse ;
IABS R14, R4 ;
I2F.RP R10, R11 ;
IADD3 R6, R6, -c[0x0][0x180], RZ ;
IMAD R6, R6, c[0x0][0x160], R7 ;
MUFU.RCP R10, R10 ;
IADD3 R8, R10, 0xffffffe, RZ ;
IADD3 R10, RZ, -R14, RZ ;
F2I.FTZ.U32.TRUNC.NTZ R9, R8 ;
IMAD.MOV.U32 R8, RZ, RZ, RZ ;
IMAD.MOV R12, RZ, RZ, -R9 ;
IMAD R13, R12, R11, RZ ;
IABS R12, R7 ;
IMAD.HI.U32 R9, R9, R13, R8 ;
IMAD.HI.U32 R9, R9, R12, RZ ;
IMAD R8, R9, R10, R12 ;
ISETP.GT.U32.AND P2, PT, R11, R8, PT ;
@!P2 IMAD.IADD R8, R8, 0x1, -R11 ;
@!P2 IADD3 R9, R9, 0x1, RZ ;
ISETP.NE.AND P2, PT, R4, RZ, PT ;
ISETP.GE.U32.AND P0, PT, R8, R11, PT ;
LOP3.LUT R8, R7, R4, RZ, 0x3c, !PT ;
ISETP.GE.AND P1, PT, R8, RZ, PT ;
@P0 IADD3 R9, R9, 0x1, RZ ;
@!P1 IADD3 R9, -R9, RZ, RZ ;
@!P2 LOP3.LUT R9, RZ, R4, RZ, 0x33, !PT ;
IMAD R4, R0, R9, R6 ;
IMAD.WIDE R4, R4, R5, c[0x0][0x170] ;
STG.E.64 [R4.64], R2 ;
EXIT ;
BRA 0x2c0;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
```
|
```amdasm
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z13unpack_bottomiiiPdS_i ; -- Begin function _Z13unpack_bottomiiiPdS_i
.globl _Z13unpack_bottomiiiPdS_i
.p2align 8
.type _Z13unpack_bottomiiiPdS_i,@function
_Z13unpack_bottomiiiPdS_i: ; @_Z13unpack_bottomiiiPdS_i
; %bb.0:
s_clause 0x3
s_load_b32 s2, s[0:1], 0x34
s_load_b32 s5, s[0:1], 0x8
s_load_b32 s4, s[0:1], 0x0
s_load_b32 s6, s[0:1], 0x20
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_lshl_b32 s7, s5, 1
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_sub_i32 s8, s4, s7
s_delay_alu instid0(SALU_CYCLE_1)
s_mul_i32 s2, s8, s6
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_cmp_gt_i32_e32 vcc_lo, s2, v1
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_2
; %bb.1:
s_load_b128 s[0:3], s[0:1], 0x10
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 3, v[1:2]
v_add_nc_u32_e32 v6, v1, v2
v_xor_b32_e32 v6, v6, v2
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v3, vcc_lo, s2, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s3, v4, vcc_lo
s_ashr_i32 s2, s8, 31
s_delay_alu instid0(SALU_CYCLE_1)
s_add_i32 s8, s8, s2
global_load_b64 v[3:4], v[3:4], off
s_xor_b32 s3, s8, s2
v_xor_b32_e32 v2, s2, v2
v_cvt_f32_u32_e32 v0, s3
s_sub_i32 s8, 0, s3
s_sub_i32 s2, s5, s6
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_mul_i32 s2, s2, s4
v_rcp_iflag_f32_e32 v0, v0
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v0, 0x4f7ffffe, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_u32_f32_e32 v0, v0
v_mul_lo_u32 v5, s8, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v5, v0, v5
v_add_nc_u32_e32 v0, v0, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v0, v6, v0
v_mul_lo_u32 v5, v0, s3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v5, v6, v5
v_add_nc_u32_e32 v6, 1, v0
v_subrev_nc_u32_e32 v7, s3, v5
v_cmp_le_u32_e32 vcc_lo, s3, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_cndmask_b32 v5, v5, v7 :: v_dual_cndmask_b32 v0, v0, v6
v_cmp_le_u32_e32 vcc_lo, s3, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v6, 1, v0
v_cndmask_b32_e32 v0, v0, v6, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_xor_b32_e32 v0, v0, v2
v_sub_nc_u32_e32 v0, v0, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v0, s7, v0
v_add3_u32 v0, v1, s2, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v1, 31, v0
v_lshlrev_b64 v[0:1], 3, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
global_store_b64 v[0:1], v[3:4], off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13unpack_bottomiiiPdS_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z13unpack_bottomiiiPdS_i, .Lfunc_end0-_Z13unpack_bottomiiiPdS_i
; -- End function
.section .AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 392
; NumSgprs: 18
; NumVgprs: 8
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 8
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object ; @__hip_cuid_
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0 ; 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .offset: 8
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13unpack_bottomiiiPdS_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z13unpack_bottomiiiPdS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
```
| 951 | 3,613 |
491 |
Convert the following CUDA host assembly code to AMD host assembly:
```cudaasm
.file "tmpxft_00087400_00000000-6_unpack_bottom.cudafe1.cpp"
.text
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z39__device_stub__Z13unpack_bottomiiiPdS_iiiiPdS_i
.type _Z39__device_stub__Z13unpack_bottomiiiPdS_iiiiPdS_i, @function
_Z39__device_stub__Z13unpack_bottomiiiPdS_iiiiPdS_i:
.LFB2051:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movl %edi, 28(%rsp)
movl %esi, 24(%rsp)
movl %edx, 20(%rsp)
movq %rcx, 8(%rsp)
movq %r8, (%rsp)
movl %r9d, 16(%rsp)
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 24(%rsp), %rax
movq %rax, 104(%rsp)
leaq 20(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 184
pushq 40(%rsp)
.cfi_def_cfa_offset 192
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z13unpack_bottomiiiPdS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z39__device_stub__Z13unpack_bottomiiiPdS_iiiiPdS_i, .-_Z39__device_stub__Z13unpack_bottomiiiPdS_iiiiPdS_i
.globl _Z13unpack_bottomiiiPdS_i
.type _Z13unpack_bottomiiiPdS_i, @function
_Z13unpack_bottomiiiPdS_i:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z39__device_stub__Z13unpack_bottomiiiPdS_iiiiPdS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z13unpack_bottomiiiPdS_i, .-_Z13unpack_bottomiiiPdS_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z13unpack_bottomiiiPdS_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z13unpack_bottomiiiPdS_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
```
|
```amdasm
.text
.file "unpack_bottom.hip"
.globl _Z28__device_stub__unpack_bottomiiiPdS_i # -- Begin function _Z28__device_stub__unpack_bottomiiiPdS_i
.type _Z28__device_stub__unpack_bottomiiiPdS_i,@function
_Z28__device_stub__unpack_bottomiiiPdS_i: # @_Z28__device_stub__unpack_bottomiiiPdS_i
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $128, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 12(%rsp), %rax
movl %edi, (%rax)
leaq 8(%rsp), %rdi
movl %esi, (%rdi)
leaq 4(%rsp), %rsi
movl %edx, (%rsi)
leaq 40(%rsp), %rdx
movq %rcx, (%rdx)
leaq 32(%rsp), %rcx
movq %r8, (%rcx)
movq %rsp, %r8
movl %r9d, (%r8)
leaq 80(%rsp), %rbx
movq %rax, (%rbx)
movq %rdi, 8(%rbx)
movq %rsi, 16(%rbx)
movq %rdx, 24(%rbx)
movq %rcx, 32(%rbx)
movq %r8, 40(%rbx)
leaq 64(%rsp), %r14
leaq 48(%rsp), %r15
leaq 24(%rsp), %r12
leaq 16(%rsp), %r13
movq %r14, %rdi
movq %r15, %rsi
movq %r12, %rdx
movq %r13, %rcx
callq __hipPopCallConfiguration
movq (%r14), %rsi
movl 8(%r14), %edx
movq (%r15), %rcx
movl 8(%r15), %r8d
movl $_Z13unpack_bottomiiiPdS_i, %edi
movq %rbx, %r9
pushq (%r13)
.cfi_adjust_cfa_offset 8
pushq (%r12)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $144, %rsp
.cfi_adjust_cfa_offset -144
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z28__device_stub__unpack_bottomiiiPdS_i, .Lfunc_end0-_Z28__device_stub__unpack_bottomiiiPdS_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, %rdi
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13unpack_bottomiiiPdS_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z13unpack_bottomiiiPdS_i,@object # @_Z13unpack_bottomiiiPdS_i
.section .rodata,"a",@progbits
.globl _Z13unpack_bottomiiiPdS_i
.p2align 3, 0x0
_Z13unpack_bottomiiiPdS_i:
.quad _Z28__device_stub__unpack_bottomiiiPdS_i
.size _Z13unpack_bottomiiiPdS_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z13unpack_bottomiiiPdS_i"
.size .L__unnamed_1, 26
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z28__device_stub__unpack_bottomiiiPdS_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z13unpack_bottomiiiPdS_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
```
| 1,981 | 2,153 |
492 |
Convert the following CUDA device assembly code to AMD device assembly:
```cudaasm
code for sm_80
Function : _Z25create_escape_carry_indexPclS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ;
IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x0] ;
IMAD R0, R0, c[0x0][0xc], RZ ;
IADD3 R5, P0, R0, c[0x0][0x168], RZ ;
SHF.R.S32.HI R6, RZ, 0x1f, R0 ;
IADD3 R5, P1, R5, -0x1, RZ ;
IADD3.X R7, R6, c[0x0][0x16c], RZ, P0, !PT ;
IADD3.X R7, R7, -0x1, RZ, P1, !PT ;
LOP3.LUT R2, R7, R6, RZ, 0xfc, !PT ;
ISETP.NE.U32.AND P0, PT, R2, RZ, PT ;
@!P0 BRA 0xe0 ;
MOV R4, 0xd0 ;
CALL.REL.NOINC 0x1000 ;
BRA 0x210 ;
I2F.U32.RP R4, R0 ;
IMAD.MOV R7, RZ, RZ, -R0 ;
ISETP.NE.U32.AND P2, PT, R0, RZ, PT ;
MUFU.RCP R4, R4 ;
IADD3 R2, R4, 0xffffffe, RZ ;
F2I.FTZ.U32.TRUNC.NTZ R3, R2 ;
IMAD.MOV.U32 R2, RZ, RZ, RZ ;
IMAD R7, R7, R3, RZ ;
IMAD.HI.U32 R6, R3, R7, R2 ;
IMAD.HI.U32 R2, R6, R5, RZ ;
IMAD.MOV R3, RZ, RZ, -R2 ;
IMAD R5, R0, R3, R5 ;
IMAD.MOV.U32 R3, RZ, RZ, RZ ;
ISETP.GE.U32.AND P0, PT, R5, R0, PT ;
@P0 IMAD.IADD R5, R5, 0x1, -R0 ;
@P0 IADD3 R2, R2, 0x1, RZ ;
ISETP.GE.U32.AND P1, PT, R5, R0, PT ;
@P1 IADD3 R2, R2, 0x1, RZ ;
@!P2 LOP3.LUT R2, RZ, R0, RZ, 0x33, !PT ;
S2R R0, SR_TID.X ;
ISETP.GT.U32.AND P0, PT, R2, 0x40, PT ;
ULDC.64 UR4, c[0x0][0x118] ;
BSSY B2, 0xfb0 ;
S2R R5, SR_CTAID.X ;
ISETP.GT.AND.EX P0, PT, R3, RZ, PT, P0 ;
SEL R2, R2, 0x40, P0 ;
SEL R3, R3, RZ, P0 ;
IADD3 R11, P0, R2, 0x3f, RZ ;
LOP3.LUT R2, R11, 0xffffffc0, RZ, 0xc0, !PT ;
IMAD.X R12, RZ, RZ, R3, P0 ;
ISETP.EQ.U32.AND P1, PT, R2, RZ, PT ;
LOP3.LUT R3, R12, 0x7fffffff, RZ, 0xc0, !PT ;
IMAD R0, R5, c[0x0][0x0], R0 ;
IMAD R4, R3, R0.reuse, RZ ;
SHF.R.S32.HI R5, RZ, 0x1f, R0 ;
IMAD.WIDE.U32 R6, R2, R0, RZ ;
IMAD R9, R5, R2, R4.reuse ;
ISETP.GE.U32.AND P0, PT, R6, c[0x0][0x168], PT ;
PRMT R4, RZ, 0x7610, R4 ;
IMAD.IADD R8, R7, 0x1, R9 ;
ISETP.GE.AND.EX P0, PT, R8, c[0x0][0x16c], PT, P0 ;
ISETP.EQ.OR.EX P0, PT, R3, RZ, P0, P1 ;
@P0 BRA 0xfa0 ;
SHF.R.U32.HI R7, RZ, 0x6, R12.reuse ;
BSSY B1, 0xe80 ;
LEA R10, P0, R0.reuse, 0x40, 0x6 ;
SHF.R.U64 R11, R11, 0x6, R12 ;
LOP3.LUT R7, R7, 0x1ffffff, RZ, 0xc0, !PT ;
LEA.HI.X R4, R0, RZ, R5, 0x6, P0 ;
IMAD.WIDE.U32 R2, R11, R0, RZ ;
IMAD R14, R7, R0, RZ ;
IMAD R4, R4, R11.reuse, RZ ;
IMAD.SHL.U32 R12, R2, 0x40, RZ ;
IMAD R9, R5, R11, R14 ;
IMAD R13, R10, R7, R4 ;
LOP3.LUT R7, R12, 0x1, RZ, 0xfc, !PT ;
IMAD.WIDE.U32 R10, R10, R11, RZ ;
IMAD.IADD R9, R3, 0x1, R9 ;
ISETP.GT.U32.AND P0, PT, R10, R7, PT ;
IMAD.IADD R4, R11, 0x1, R13 ;
SHF.L.U64.HI R9, R2, 0x6, R9 ;
IADD3 R2, P1, R12, -c[0x0][0x168], RZ ;
ISETP.GT.AND.EX P0, PT, R4, R9, PT, P0 ;
IADD3.X R3, R9, ~c[0x0][0x16c], RZ, P1, !PT ;
SEL R7, R10, R7, P0 ;
SEL R4, R4, R9, P0 ;
IADD3 R7, P0, -R7, R12, RZ ;
IMAD.X R4, R9, 0x1, ~R4, P0 ;
ISETP.GT.U32.AND P0, PT, R7, R2, PT ;
ISETP.GT.U32.AND.EX P0, PT, R4, R3, PT, P0 ;
SEL R2, R7, R2, P0 ;
SEL R3, R4, R3, P0 ;
ISETP.GT.U32.AND P0, PT, R2, -0x4, PT ;
IMAD.MOV R9, RZ, RZ, -R2 ;
PRMT R4, RZ, 0x7610, R4 ;
ISETP.GT.U32.AND.EX P0, PT, R3, -0x1, PT, P0 ;
LOP3.LUT R9, R9, 0x3, RZ, 0xc0, !PT ;
@P0 BRA 0xe70 ;
IADD3 R12, P0, R9, R2, RZ ;
IMAD.MOV.U32 R11, RZ, RZ, c[0x0][0x160] ;
BSSY B0, 0xd20 ;
PRMT R4, RZ, 0x7610, R4 ;
IMAD.X R10, RZ, RZ, R3, P0 ;
IADD3 R11, P1, R11, 0x1, RZ ;
ISETP.GE.AND P0, PT, R10, RZ, PT ;
IMAD.X R7, RZ, RZ, c[0x0][0x164], P1 ;
@P0 BRA 0xd10 ;
IADD3 R2, P0, RZ, -R12, RZ ;
BSSY B3, 0xa70 ;
ISETP.GT.U32.AND P1, PT, R2, 0xc, PT ;
IMAD.X R2, RZ, RZ, ~R10, P0 ;
PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ;
ISETP.GT.AND.EX P1, PT, R2, RZ, PT, P1 ;
@!P1 BRA 0xa60 ;
PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ;
IADD3 R2, P1, R6, R11, RZ ;
IMAD.X R3, R8, 0x1, R7, P1 ;
LDG.E.U8 R13, [R2.64+-0x1] ;
LDG.E.U8 R26, [R2.64] ;
LDG.E.U8 R27, [R2.64+0x1] ;
LDG.E.U8 R25, [R2.64+0x2] ;
LDG.E.U8 R23, [R2.64+0x3] ;
LDG.E.U8 R22, [R2.64+0x4] ;
LDG.E.U8 R21, [R2.64+0x5] ;
LDG.E.U8 R20, [R2.64+0x6] ;
LDG.E.U8 R19, [R2.64+0x7] ;
LDG.E.U8 R18, [R2.64+0x8] ;
LDG.E.U8 R17, [R2.64+0x9] ;
LDG.E.U8 R16, [R2.64+0xa] ;
LDG.E.U8 R15, [R2.64+0xb] ;
LDG.E.U8 R14, [R2.64+0xc] ;
LDG.E.U8 R24, [R2.64+0xe] ;
ISETP.NE.AND P1, PT, R13, 0x5c, PT ;
LDG.E.U8 R13, [R2.64+0xd] ;
ISETP.NE.AND P2, PT, R26, 0x5c, PT ;
SEL R4, R4, 0x1, !P1 ;
ISETP.NE.AND P1, PT, R27, 0x5c, PT ;
SEL R4, R4, RZ, !P2 ;
ISETP.NE.AND P2, PT, R25, 0x5c, PT ;
SEL R4, R4, 0x1, !P1 ;
ISETP.NE.AND P1, PT, R23, 0x5c, PT ;
SEL R4, R4, RZ, !P2 ;
ISETP.NE.AND P2, PT, R22, 0x5c, PT ;
SEL R4, R4, 0x1, !P1 ;
ISETP.NE.AND P1, PT, R21, 0x5c, PT ;
SEL R4, R4, RZ, !P2 ;
ISETP.NE.AND P2, PT, R20, 0x5c, PT ;
SEL R4, R4, 0x1, !P1 ;
ISETP.NE.AND P1, PT, R19, 0x5c, PT ;
SEL R4, R4, RZ, !P2 ;
ISETP.NE.AND P2, PT, R18, 0x5c, PT ;
SEL R4, R4, 0x1, !P1 ;
ISETP.NE.AND P1, PT, R17, 0x5c, PT ;
SEL R4, R4, RZ, !P2 ;
ISETP.NE.AND P2, PT, R16, 0x5c, PT ;
SEL R4, R4, 0x1, !P1 ;
ISETP.NE.AND P1, PT, R15, 0x5c, PT ;
SEL R4, R4, RZ, !P2 ;
SEL R4, R4, 0x1, !P1 ;
IADD3 R12, P1, R12, 0x10, RZ ;
IMAD.X R10, RZ, RZ, R10, P1 ;
ISETP.GE.U32.AND P1, PT, R12, -0xc, PT ;
ISETP.NE.AND P2, PT, R14, 0x5c, PT ;
ISETP.GE.AND.EX P1, PT, R10, -0x1, PT, P1 ;
SEL R4, R4, RZ, !P2 ;
ISETP.NE.AND P2, PT, R24, 0x5c, PT ;
ISETP.NE.AND P3, PT, R13, 0x5c, PT ;
SEL R4, R4, 0x1, !P3 ;
IADD3 R6, P3, R6, 0x10, RZ ;
SEL R4, R4, RZ, !P2 ;
IMAD.X R8, RZ, RZ, R8, P3 ;
@!P1 BRA 0x6d0 ;
BSYNC B3 ;
IADD3 R2, P2, RZ, -R12, RZ ;
BSSY B3, 0xcd0 ;
ISETP.GT.U32.AND P1, PT, R2, 0x4, PT ;
IMAD.X R2, RZ, RZ, ~R10, P2 ;
ISETP.GT.AND.EX P1, PT, R2, RZ, PT, P1 ;
@!P1 BRA 0xcc0 ;
IADD3 R2, P0, R11, R6, RZ ;
IMAD.X R3, R7, 0x1, R8, P0 ;
LDG.E.U8 R20, [R2.64+-0x1] ;
LDG.E.U8 R13, [R2.64] ;
LDG.E.U8 R14, [R2.64+0x1] ;
LDG.E.U8 R15, [R2.64+0x2] ;
LDG.E.U8 R16, [R2.64+0x3] ;
LDG.E.U8 R17, [R2.64+0x4] ;
LDG.E.U8 R18, [R2.64+0x5] ;
LDG.E.U8 R19, [R2.64+0x6] ;
IADD3 R12, P3, R12, 0x8, RZ ;
IADD3 R6, P2, R6, 0x8, RZ ;
IMAD.X R10, RZ, RZ, R10, P3 ;
IMAD.X R8, RZ, RZ, R8, P2 ;
ISETP.NE.AND P0, PT, R20, 0x5c, PT ;
ISETP.NE.AND P1, PT, R13, 0x5c, PT ;
SEL R4, R4, 0x1, !P0 ;
ISETP.NE.AND P0, PT, R14, 0x5c, PT ;
SEL R4, R4, RZ, !P1 ;
ISETP.NE.AND P1, PT, R15, 0x5c, PT ;
SEL R4, R4, 0x1, !P0 ;
ISETP.NE.AND P0, PT, R16, 0x5c, PT ;
SEL R4, R4, RZ, !P1 ;
ISETP.NE.AND P1, PT, R17, 0x5c, PT ;
SEL R4, R4, 0x1, !P0 ;
ISETP.NE.AND P0, PT, R18, 0x5c, PT ;
SEL R4, R4, RZ, !P1 ;
ISETP.NE.AND P1, PT, R19, 0x5c, PT ;
SEL R4, R4, 0x1, !P0 ;
PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ;
SEL R4, R4, RZ, !P1 ;
BSYNC B3 ;
ISETP.NE.U32.AND P1, PT, R12, RZ, PT ;
ISETP.NE.OR.EX P0, PT, R10, RZ, P0, P1 ;
@!P0 BREAK B0 ;
@!P0 BRA 0xe70 ;
BSYNC B0 ;
IADD3 R2, P0, R6, R11, RZ ;
IMAD.X R3, R8, 0x1, R7, P0 ;
LDG.E.U8 R16, [R2.64+-0x1] ;
LDG.E.U8 R13, [R2.64] ;
LDG.E.U8 R14, [R2.64+0x1] ;
LDG.E.U8 R15, [R2.64+0x2] ;
ISETP.NE.AND P0, PT, R16, 0x5c, PT ;
SEL R4, R4, 0x1, !P0 ;
IADD3 R12, P0, R12, 0x4, RZ ;
ISETP.NE.AND P1, PT, R13, 0x5c, PT ;
ISETP.NE.AND P2, PT, R14, 0x5c, PT ;
IMAD.X R10, RZ, RZ, R10, P0 ;
ISETP.NE.U32.AND P0, PT, R12, RZ, PT ;
SEL R4, R4, RZ, !P1 ;
ISETP.NE.AND.EX P0, PT, R10, RZ, PT, P0 ;
SEL R4, R4, 0x1, !P2 ;
IADD3 R6, P2, R6, 0x4, RZ ;
ISETP.NE.AND P1, PT, R15, 0x5c, PT ;
IMAD.X R8, RZ, RZ, R8, P2 ;
SEL R4, R4, RZ, !P1 ;
@P0 BRA 0xd20 ;
BSYNC B1 ;
ISETP.NE.U32.AND P0, PT, R9, RZ, PT ;
ISETP.NE.AND.EX P0, PT, RZ, RZ, PT, P0 ;
@!P0 BRA 0xfa0 ;
IADD3 R9, P1, RZ, -R9, RZ ;
IADD3 R2, P0, R6, c[0x0][0x160], RZ ;
IMAD.X R6, RZ, RZ, -0x1, P1 ;
IADD3.X R3, R8, c[0x0][0x164], RZ, P0, !PT ;
LDG.E.U8 R7, [R2.64] ;
IADD3 R9, P0, R9, 0x1, RZ ;
LOP3.LUT R4, R4, 0x1, RZ, 0x3c, !PT ;
IMAD.X R6, RZ, RZ, R6, P0 ;
ISETP.NE.U32.AND P0, PT, R9, RZ, PT ;
IADD3 R2, P2, R2, 0x1, RZ ;
ISETP.NE.AND.EX P0, PT, R6, RZ, PT, P0 ;
IMAD.X R3, RZ, RZ, R3, P2 ;
ISETP.NE.AND P1, PT, R7, 0x5c, PT ;
SEL R4, R4, RZ, !P1 ;
@P0 BRA 0xef0 ;
BSYNC B2 ;
WARPSYNC 0xffffffff ;
IADD3 R2, P0, R0, c[0x0][0x170], RZ ;
IADD3.X R3, R5, c[0x0][0x174], RZ, P0, !PT ;
STG.E.U8 [R2.64], R4 ;
EXIT ;
IADD3 R3, P1, RZ, -R0.reuse, RZ ;
ISETP.GE.AND P0, PT, R6, RZ, PT ;
ISETP.GE.AND P3, PT, R7, RZ, PT ;
IMAD.X R9, RZ, RZ, ~R6, P1 ;
SEL R2, R3, R0, !P0 ;
SEL R3, R9, R6, !P0 ;
I2F.U64.RP R12, R2 ;
MUFU.RCP R12, R12 ;
IADD3 R8, R12, 0x1ffffffe, RZ ;
F2I.U64.TRUNC R8, R8 ;
IMAD.WIDE.U32 R10, R8, R2, RZ ;
IMAD R11, R8, R3, R11 ;
IADD3 R13, P0, RZ, -R10, RZ ;
IMAD R11, R9, R2, R11 ;
IMAD.HI.U32 R10, R8, R13, RZ ;
IMAD.X R15, RZ, RZ, ~R11, P0 ;
IMAD.MOV.U32 R11, RZ, RZ, R8 ;
IMAD R17, R9, R15.reuse, RZ ;
IMAD.WIDE.U32 R10, P0, R8, R15, R10 ;
IMAD.HI.U32 R15, R9, R15, RZ ;
IMAD.HI.U32 R10, P1, R9, R13, R10 ;
IADD3 R11, P2, R17, R10, RZ ;
IMAD.X R10, R15, 0x1, R9, P0 ;
IMAD.WIDE.U32 R8, R11, R2, RZ ;
IADD3.X R13, RZ, RZ, R10, P2, P1 ;
IMAD R9, R11, R3, R9 ;
IADD3 R15, P0, RZ, -R8, RZ ;
IADD3 R8, P4, RZ, -R5, RZ ;
IMAD R9, R13, R2, R9 ;
IMAD.HI.U32 R10, R11, R15, RZ ;
SEL R5, R8, R5, !P3 ;
IMAD.X R12, RZ, RZ, ~R9, P0 ;
IMAD.WIDE.U32 R10, P0, R11, R12, R10 ;
IMAD R9, R13.reuse, R12, RZ ;
IMAD.HI.U32 R10, P1, R13, R15, R10 ;
IMAD.HI.U32 R8, R13, R12, RZ ;
IADD3 R10, P2, R9, R10, RZ ;
IMAD.X R12, RZ, RZ, ~R7, P4 ;
IMAD.X R13, R8, 0x1, R13, P0 ;
IMAD.HI.U32 R8, R10, R5, RZ ;
SEL R12, R12, R7.reuse, !P3 ;
IADD3.X R13, RZ, RZ, R13, P2, P1 ;
IMAD.MOV.U32 R9, RZ, RZ, RZ ;
LOP3.LUT R7, R6, R7, RZ, 0x3c, !PT ;
IMAD.WIDE.U32 R8, R10, R12, R8 ;
IMAD R11, R13.reuse, R12, RZ ;
IMAD.HI.U32 R8, P0, R13, R5, R8 ;
IMAD.HI.U32 R10, R13, R12, RZ ;
IADD3 R11, P1, R11, R8, RZ ;
IMAD.X R10, RZ, RZ, R10, P0 ;
IMAD.WIDE.U32 R8, R11, R2, RZ ;
IMAD.X R13, RZ, RZ, R10, P1 ;
IADD3 R15, P1, -R8, R5, RZ ;
IMAD R9, R11.reuse, R3, R9 ;
IADD3 R8, P2, R11, 0x1, RZ ;
ISETP.GE.U32.AND P0, PT, R15, R2.reuse, PT ;
IMAD R9, R13, R2.reuse, R9 ;
IMAD.X R10, RZ, RZ, R13, P2 ;
IMAD.X R17, R12, 0x1, ~R9, P1 ;
IADD3 R5, P1, R15, -R2, RZ ;
ISETP.GE.U32.AND.EX P0, PT, R17.reuse, R3, PT, P0 ;
IMAD.X R9, R17, 0x1, ~R3, P1 ;
SEL R5, R5, R15, P0 ;
SEL R11, R8, R11, P0 ;
SEL R9, R9, R17, P0 ;
ISETP.GE.U32.AND P1, PT, R5, R2, PT ;
SEL R8, R10, R13, P0 ;
IADD3 R2, P2, R11, 0x1, RZ ;
ISETP.GE.U32.AND.EX P0, PT, R9, R3, PT, P1 ;
ISETP.GE.AND P1, PT, R7, RZ, PT ;
IMAD.X R3, RZ, RZ, R8, P2 ;
SEL R2, R2, R11, P0 ;
SEL R3, R3, R8, P0 ;
IADD3 R5, P2, RZ, -R2.reuse, RZ ;
ISETP.NE.U32.AND P0, PT, R0, RZ, PT ;
SEL R2, R5, R2, !P1 ;
IMAD.X R0, RZ, RZ, ~R3, P2 ;
ISETP.NE.AND.EX P0, PT, R6, RZ, PT, P0 ;
IMAD.MOV.U32 R5, RZ, RZ, 0x0 ;
SEL R3, R0, R3, !P1 ;
SEL R2, R2, 0xffffffff, P0 ;
SEL R3, R3, 0xffffffff, P0 ;
RET.REL.NODEC R4 0x0 ;
BRA 0x1530;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
```
|
```amdasm
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z25create_escape_carry_indexPclS_ ; -- Begin function _Z25create_escape_carry_indexPclS_
.globl _Z25create_escape_carry_indexPclS_
.p2align 8
.type _Z25create_escape_carry_indexPclS_,@function
_Z25create_escape_carry_indexPclS_: ; @_Z25create_escape_carry_indexPclS_
; %bb.0:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s3, s[0:1], 0x18
s_load_b128 s[4:7], s[0:1], 0x0
v_mov_b32_e32 v6, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s14, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1)
s_mul_i32 s8, s3, s14
s_load_b64 s[2:3], s[0:1], 0x10
s_ashr_i32 s0, s8, 31
s_add_u32 s9, s6, s8
s_addc_u32 s10, s7, s0
s_add_u32 s12, s9, -1
s_addc_u32 s13, s10, -1
s_add_u32 s8, s8, s0
s_mov_b32 s1, s0
s_addc_u32 s9, s0, s0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_xor_b64 s[8:9], s[8:9], s[0:1]
v_cvt_f32_u32_e32 v1, s8
v_cvt_f32_u32_e32 v2, s9
s_sub_u32 s16, 0, s8
s_subb_u32 s17, 0, s9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmamk_f32 v1, v2, 0x4f800000, v1
v_rcp_f32_e32 v1, v1
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v1, 0x5f7ffffc, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v2, 0x2f800000, v1
v_trunc_f32_e32 v2, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_fmamk_f32 v1, v2, 0xcf800000, v1
v_cvt_u32_f32_e32 v2, v2
v_cvt_u32_f32_e32 v1, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_readfirstlane_b32 s10, v2
v_readfirstlane_b32 s11, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
s_mul_i32 s18, s16, s10
s_mul_hi_u32 s20, s16, s11
s_mul_i32 s19, s17, s11
s_add_i32 s18, s20, s18
s_mul_i32 s21, s16, s11
s_add_i32 s18, s18, s19
s_mul_hi_u32 s20, s11, s21
s_mul_hi_u32 s22, s10, s21
s_mul_i32 s19, s10, s21
s_mul_hi_u32 s21, s11, s18
s_mul_i32 s11, s11, s18
s_mul_hi_u32 s23, s10, s18
s_add_u32 s11, s20, s11
s_addc_u32 s20, 0, s21
s_add_u32 s11, s11, s19
s_mul_i32 s18, s10, s18
s_addc_u32 s11, s20, s22
s_addc_u32 s19, s23, 0
s_add_u32 s11, s11, s18
s_addc_u32 s18, 0, s19
v_add_co_u32 v1, s11, v1, s11
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
s_cmp_lg_u32 s11, 0
s_addc_u32 s10, s10, s18
v_readfirstlane_b32 s11, v1
s_mul_i32 s18, s16, s10
s_delay_alu instid0(VALU_DEP_1)
s_mul_hi_u32 s19, s16, s11
s_mul_i32 s17, s17, s11
s_add_i32 s18, s19, s18
s_mul_i32 s16, s16, s11
s_add_i32 s18, s18, s17
s_mul_hi_u32 s19, s10, s16
s_mul_i32 s20, s10, s16
s_mul_hi_u32 s16, s11, s16
s_mul_hi_u32 s21, s11, s18
s_mul_i32 s11, s11, s18
s_mul_hi_u32 s17, s10, s18
s_add_u32 s11, s16, s11
s_addc_u32 s16, 0, s21
s_add_u32 s11, s11, s20
s_mul_i32 s18, s10, s18
s_addc_u32 s11, s16, s19
s_addc_u32 s16, s17, 0
s_add_u32 s11, s11, s18
s_addc_u32 s16, 0, s16
v_add_co_u32 v1, s11, v1, s11
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
s_cmp_lg_u32 s11, 0
s_addc_u32 s16, s10, s16
s_ashr_i32 s10, s13, 31
v_readfirstlane_b32 s17, v1
s_add_u32 s12, s12, s10
s_mov_b32 s11, s10
s_addc_u32 s13, s13, s10
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_xor_b64 s[12:13], s[12:13], s[10:11]
s_mul_i32 s19, s12, s16
s_mul_hi_u32 s20, s12, s17
s_mul_hi_u32 s18, s12, s16
s_mul_hi_u32 s22, s13, s17
s_mul_i32 s17, s13, s17
s_add_u32 s19, s20, s19
s_addc_u32 s18, 0, s18
s_mul_hi_u32 s21, s13, s16
s_add_u32 s17, s19, s17
s_mul_i32 s16, s13, s16
s_addc_u32 s17, s18, s22
s_addc_u32 s18, s21, 0
s_add_u32 s16, s17, s16
s_addc_u32 s17, 0, s18
s_mul_i32 s21, s8, s16
s_mul_hi_u32 s18, s8, s16
s_mul_i32 s20, s8, s17
v_sub_co_u32 v1, s12, s12, s21
s_mul_i32 s19, s9, s16
s_add_i32 s18, s18, s20
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_add_i32 s18, s18, s19
v_sub_co_u32 v2, s20, v1, s8
s_sub_i32 s19, s13, s18
s_cmp_lg_u32 s12, 0
s_subb_u32 s19, s19, s9
s_cmp_lg_u32 s20, 0
v_readfirstlane_b32 s20, v2
s_subb_u32 s19, s19, 0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
s_cmp_ge_u32 s19, s9
s_cselect_b32 s21, -1, 0
s_cmp_ge_u32 s20, s8
s_cselect_b32 s20, -1, 0
s_cmp_eq_u32 s19, s9
s_cselect_b32 s19, s20, s21
s_add_u32 s20, s16, 1
s_addc_u32 s21, s17, 0
s_add_u32 s22, s16, 2
s_addc_u32 s23, s17, 0
s_cmp_lg_u32 s19, 0
s_cselect_b32 s19, s22, s20
s_cselect_b32 s20, s23, s21
s_cmp_lg_u32 s12, 0
v_readfirstlane_b32 s12, v1
s_subb_u32 s13, s13, s18
v_mad_u64_u32 v[1:2], null, s15, s14, v[0:1]
s_cmp_ge_u32 s13, s9
s_cselect_b32 s18, -1, 0
s_cmp_ge_u32 s12, s8
s_cselect_b32 s8, -1, 0
s_cmp_eq_u32 s13, s9
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_ashrrev_i32_e32 v0, 31, v1
s_cselect_b32 s8, s8, s18
s_cmp_lg_u32 s8, 0
s_cselect_b32 s9, s20, s17
s_cselect_b32 s8, s19, s16
s_xor_b64 s[0:1], s[10:11], s[0:1]
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_xor_b64 s[8:9], s[8:9], s[0:1]
s_sub_u32 s0, s8, s0
s_subb_u32 s1, s9, s1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_i64_e64 s8, s[0:1], 64
s_and_b32 s8, s8, exec_lo
s_cselect_b32 s0, s0, 64
s_cselect_b32 s1, s1, 0
s_add_u32 s0, s0, 63
s_addc_u32 s1, s1, 0
s_and_not1_b32 s0, s0, 63
s_bitset0_b32 s1, 31
v_mul_lo_u32 v4, s0, v0
v_mul_lo_u32 v5, s1, v1
v_mad_u64_u32 v[2:3], null, s0, v1, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add3_u32 v3, v3, v4, v5
v_add_co_u32 v4, vcc_lo, v2, s0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v5, vcc_lo, s1, v3, vcc_lo
s_mov_b32 s1, exec_lo
v_cmp_gt_i64_e32 vcc_lo, s[6:7], v[4:5]
v_cndmask_b32_e32 v5, s7, v5, vcc_lo
v_cndmask_b32_e32 v4, s6, v4, vcc_lo
s_mov_b32 s6, 0
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_lt_i64_e64 v[2:3], v[4:5]
s_cbranch_execz .LBB0_4
; %bb.1: ; %.lr.ph.preheader
v_mov_b32_e32 v6, 0
.LBB0_2: ; %.lr.ph
; =>This Inner Loop Header: Depth=1
v_add_co_u32 v7, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v8, vcc_lo, s5, v3, vcc_lo
v_add_co_u32 v2, vcc_lo, v2, 1
v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
global_load_u8 v7, v[7:8], off
v_xor_b32_e32 v6, 1, v6
v_cmp_ge_i64_e32 vcc_lo, v[2:3], v[4:5]
s_or_b32 s6, vcc_lo, s6
s_waitcnt vmcnt(0)
v_cmp_eq_u16_e64 s0, 0x5c, v7
s_delay_alu instid0(VALU_DEP_1)
v_cndmask_b32_e64 v6, 0, v6, s0
s_and_not1_b32 exec_lo, exec_lo, s6
s_cbranch_execnz .LBB0_2
; %bb.3: ; %Flow
s_or_b32 exec_lo, exec_lo, s6
.LBB0_4: ; %Flow32
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s1
s_waitcnt lgkmcnt(0)
v_add_co_u32 v1, vcc_lo, s2, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s3, v0, vcc_lo
global_store_b8 v[1:2], v6, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z25create_escape_carry_indexPclS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 24
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z25create_escape_carry_indexPclS_, .Lfunc_end0-_Z25create_escape_carry_indexPclS_
; -- End function
.section .AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 956
; NumSgprs: 26
; NumVgprs: 9
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 3
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 26
; NumVGPRsForWavesPerEU: 9
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object ; @__hip_cuid_
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0 ; 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 8
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z25create_escape_carry_indexPclS_
.private_segment_fixed_size: 0
.sgpr_count: 26
.sgpr_spill_count: 0
.symbol: _Z25create_escape_carry_indexPclS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
```
| 6,691 | 5,887 |
493 |
Convert the following CUDA host assembly code to AMD host assembly:
```cudaasm
.file "tmpxft_000a76bc_00000000-6_create_escape_carry_index.cudafe1.cpp"
.text
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z48__device_stub__Z25create_escape_carry_indexPclS_PclS_
.type _Z48__device_stub__Z25create_escape_carry_indexPclS_PclS_, @function
_Z48__device_stub__Z25create_escape_carry_indexPclS_PclS_:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z25create_escape_carry_indexPclS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z48__device_stub__Z25create_escape_carry_indexPclS_PclS_, .-_Z48__device_stub__Z25create_escape_carry_indexPclS_PclS_
.globl _Z25create_escape_carry_indexPclS_
.type _Z25create_escape_carry_indexPclS_, @function
_Z25create_escape_carry_indexPclS_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z48__device_stub__Z25create_escape_carry_indexPclS_PclS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z25create_escape_carry_indexPclS_, .-_Z25create_escape_carry_indexPclS_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z25create_escape_carry_indexPclS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z25create_escape_carry_indexPclS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
```
|
```amdasm
.text
.file "create_escape_carry_index.hip"
.globl _Z40__device_stub__create_escape_carry_indexPclS_ # -- Begin function _Z40__device_stub__create_escape_carry_indexPclS_
.type _Z40__device_stub__create_escape_carry_indexPclS_,@function
_Z40__device_stub__create_escape_carry_indexPclS_: # @_Z40__device_stub__create_escape_carry_indexPclS_
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $112, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 40(%rsp), %rax
movq %rdi, (%rax)
leaq 32(%rsp), %rcx
movq %rsi, (%rcx)
leaq 24(%rsp), %rsi
movq %rdx, (%rsi)
leaq 80(%rsp), %rbx
movq %rax, (%rbx)
movq %rcx, 8(%rbx)
movq %rsi, 16(%rbx)
leaq 64(%rsp), %r14
leaq 48(%rsp), %r15
leaq 16(%rsp), %r12
leaq 8(%rsp), %r13
movq %r14, %rdi
movq %r15, %rsi
movq %r12, %rdx
movq %r13, %rcx
callq __hipPopCallConfiguration
movq (%r14), %rsi
movl 8(%r14), %edx
movq (%r15), %rcx
movl 8(%r15), %r8d
movl $_Z25create_escape_carry_indexPclS_, %edi
movq %rbx, %r9
pushq (%r13)
.cfi_adjust_cfa_offset 8
pushq (%r12)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $128, %rsp
.cfi_adjust_cfa_offset -128
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z40__device_stub__create_escape_carry_indexPclS_, .Lfunc_end0-_Z40__device_stub__create_escape_carry_indexPclS_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, %rdi
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z25create_escape_carry_indexPclS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z25create_escape_carry_indexPclS_,@object # @_Z25create_escape_carry_indexPclS_
.section .rodata,"a",@progbits
.globl _Z25create_escape_carry_indexPclS_
.p2align 3, 0x0
_Z25create_escape_carry_indexPclS_:
.quad _Z40__device_stub__create_escape_carry_indexPclS_
.size _Z25create_escape_carry_indexPclS_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z25create_escape_carry_indexPclS_"
.size .L__unnamed_1, 35
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z40__device_stub__create_escape_carry_indexPclS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z25create_escape_carry_indexPclS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
```
| 1,883 | 2,071 |
494 |
Convert the following CUDA device assembly code to AMD device assembly:
```cudaasm
code for sm_80
Function : _Z8simulateifPfS_S_S_S_S_S_S_Pi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
MOV R1, c[0x0][0x28] ;
S2R R7, SR_CTAID.X ;
MOV R5, c[0x0][0x160] ;
ULDC.64 UR4, c[0x0][0x118] ;
BSSY B0, 0x590 ;
S2R R0, SR_TID.X ;
HFMA2.MMA R6, -RZ, RZ, 0, 0 ;
S2R R12, SR_CTAID.Y ;
S2R R3, SR_TID.Y ;
IMAD R7, R7, c[0x0][0x0], R0 ;
IADD3 R0, R5, -0x1, RZ ;
ISETP.GE.AND P0, PT, R7, R0, PT ;
IMAD R12, R12, c[0x0][0x4], R3 ;
IMAD.MOV.U32 R3, RZ, RZ, RZ ;
ISETP.GE.OR P0, PT, R12, R0, P0 ;
ISETP.EQ.OR P0, PT, R12, RZ, P0 ;
ISETP.EQ.OR P0, PT, R7, RZ, P0 ;
@P0 BRA 0x580 ;
IMAD.MOV.U32 R18, RZ, RZ, 0x4 ;
IMAD R0, R12, c[0x0][0x160], R7 ;
IMAD.WIDE R10, R0, R18, c[0x0][0x168] ;
LDG.E R10, [R10.64] ;
FSETP.NEU.AND P0, PT, R10, 3.40282346638528859812e+38, PT ;
@!P0 BRA 0x580 ;
SHF.R.S32.HI R9, RZ, 0x1f, R0 ;
SHF.L.U32 R2, R0.reuse, 0x2, RZ ;
SHF.L.U64.HI R0, R0, 0x2, R9 ;
IADD3 R8, P0, R2, c[0x0][0x170], RZ ;
IADD3.X R9, R0, c[0x0][0x174], RZ, P0, !PT ;
LDG.E R4, [R8.64] ;
FSETP.NEU.AND P0, PT, R4, 3.40282346638528859812e+38, PT ;
@!P0 BRA 0x580 ;
IMAD R12, R12, R5, -c[0x0][0x160] ;
IMAD.IADD R7, R7, 0x1, R12 ;
IMAD.WIDE R12, R7, R18, c[0x0][0x178] ;
IMAD.WIDE R18, R7, R18, c[0x0][0x180] ;
IMAD.WIDE R8, R5.reuse, 0x4, R12 ;
LDG.E R12, [R12.64] ;
IMAD.WIDE R6, R5.reuse, 0x4, R18 ;
LDG.E R22, [R8.64+0x4] ;
IMAD.WIDE R16, R5.reuse, 0x4, R8 ;
LDG.E R18, [R18.64] ;
IMAD.WIDE R20, R5, 0x4, R6 ;
LDG.E R17, [R16.64] ;
LDG.E R21, [R20.64] ;
LDG.E R15, [R8.64] ;
LDG.E R24, [R6.64+0x4] ;
LDG.E R23, [R6.64+-0x4] ;
LDG.E R14, [R6.64] ;
LDG.E R3, [R8.64+-0x4] ;
F2F.F64.F32 R10, R10 ;
F2F.F64.F32 R4, R4 ;
FADD R17, R12, R17 ;
FADD R22, R22, R17 ;
FADD R17, R18, R21 ;
F2F.F64.F32 R12, R15 ;
FADD R24, R24, R17 ;
FADD R23, R23, R24 ;
FFMA R23, R14, -4, R23 ;
FADD R22, R3, R22 ;
FMUL R6, R23, c[0x0][0x164] ;
FFMA R22, R15, -4, R22 ;
DFMA R16, R10, c[0x2][0x0], R12 ;
F2F.F64.F32 R12, R6 ;
FMUL R3, R22, c[0x0][0x164] ;
F2F.F64.F32 R8, R14 ;
F2F.F64.F32 R18, R3 ;
DMUL R10, R10, c[0x2][0x8] ;
DMUL R12, R12, c[0x2][0x0] ;
DFMA R8, R4, c[0x2][0x0], R8 ;
DFMA R12, R4, c[0x2][0x8], R12 ;
DFMA R10, R18, c[0x2][0x0], R10 ;
F2F.F32.F64 R7, R16 ;
IADD3 R4, P0, R2, c[0x0][0x198], RZ ;
F2F.F32.F64 R9, R8 ;
IADD3 R14, P1, R2, c[0x0][0x1a0], RZ ;
F2F.F32.F64 R11, R10 ;
IADD3 R18, P2, R2, c[0x0][0x188], RZ ;
F2F.F32.F64 R13, R12 ;
IADD3 R16, P3, R2, c[0x0][0x190], RZ ;
IADD3.X R5, R0.reuse, c[0x0][0x19c], RZ, P0, !PT ;
IADD3.X R15, R0.reuse, c[0x0][0x1a4], RZ, P1, !PT ;
IADD3.X R19, R0.reuse, c[0x0][0x18c], RZ, P2, !PT ;
IADD3.X R17, R0, c[0x0][0x194], RZ, P3, !PT ;
STG.E [R4.64], R7 ;
STG.E [R14.64], R9 ;
STG.E [R18.64], R11 ;
STG.E [R16.64], R13 ;
BSYNC B0 ;
F2F.F64.F32 R2, |R3| ;
BSSY B0, 0x610 ;
DSETP.GT.AND P0, PT, R2, c[0x2][0x10], PT ;
@P0 BRA 0x600 ;
F2F.F64.F32 R6, |R6| ;
DSETP.GT.AND P0, PT, R6, c[0x2][0x10], PT ;
@!P0 EXIT ;
BSYNC B0 ;
MOV R2, c[0x0][0x1a8] ;
IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x1ac] ;
LDG.E R0, [R2.64] ;
IADD3 R5, R0, 0x1, RZ ;
STG.E [R2.64], R5 ;
EXIT ;
BRA 0x670;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
```
|
```amdasm
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z8simulateifPfS_S_S_S_S_S_S_Pi ; -- Begin function _Z8simulateifPfS_S_S_S_S_S_S_Pi
.globl _Z8simulateifPfS_S_S_S_S_S_S_Pi
.p2align 8
.type _Z8simulateifPfS_S_S_S_S_S_S_Pi,@function
_Z8simulateifPfS_S_S_S_S_S_S_Pi: ; @_Z8simulateifPfS_S_S_S_S_S_S_Pi
; %bb.0:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x5c
s_load_b64 s[20:21], s[0:1], 0x0
v_bfe_u32 v3, v0, 10, 10
v_dual_mov_b32 v6, 0 :: v_dual_mov_b32 v5, 0
s_mov_b32 s22, exec_lo
s_waitcnt lgkmcnt(0)
s_lshr_b32 s3, s2, 16
s_delay_alu instid0(SALU_CYCLE_1)
v_mad_u64_u32 v[1:2], null, s15, s3, v[3:4]
s_add_i32 s3, s20, -1
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_8
; %bb.1:
v_dual_mov_b32 v5, 0 :: v_dual_and_b32 v0, 0x3ff, v0
s_and_b32 s2, s2, 0xffff
v_cmp_ne_u32_e32 vcc_lo, 0, v1
v_mov_b32_e32 v6, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, s14, s2, v[0:1]
v_cmp_ne_u32_e64 s2, 0, v2
v_cmp_gt_i32_e64 s3, s3, v2
s_delay_alu instid0(VALU_DEP_2)
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
s_and_b32 s3, s2, s3
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s2, s3
s_cbranch_execz .LBB0_7
; %bb.2:
v_mul_lo_u32 v7, v1, s20
s_load_b512 s[4:19], s[0:1], 0x8
v_mov_b32_e32 v6, 0
s_mov_b32 s3, exec_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_mov_b32 v5, 0 :: v_dual_add_nc_u32 v0, v7, v2
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v3, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v1, vcc_lo
global_load_b32 v3, v[3:4], off
s_waitcnt vmcnt(0)
v_cmpx_neq_f32_e32 0x7f7fffff, v3
s_cbranch_execz .LBB0_6
; %bb.3:
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
s_mov_b32 s4, exec_lo
v_mov_b32_e32 v6, 0
global_load_b32 v4, v[4:5], off
v_mov_b32_e32 v5, 0
s_waitcnt vmcnt(0)
v_cmpx_neq_f32_e32 0x7f7fffff, v4
s_cbranch_execz .LBB0_5
; %bb.4:
v_subrev_nc_u32_e32 v5, s20, v7
v_add_co_u32 v9, vcc_lo, s8, v0
v_add_co_ci_u32_e32 v10, vcc_lo, s9, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v5, v5, v2
s_mov_b32 s6, 0x47ae147b
s_mov_b32 s7, 0x3f847ae1
v_ashrrev_i32_e32 v6, 31, v5
v_lshl_add_u32 v7, s20, 1, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[5:6], 2, v[5:6]
v_ashrrev_i32_e32 v8, 31, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[7:8], 2, v[7:8]
v_add_co_u32 v11, vcc_lo, s8, v5
s_delay_alu instid0(VALU_DEP_4)
v_add_co_ci_u32_e32 v12, vcc_lo, s9, v6, vcc_lo
v_add_co_u32 v5, vcc_lo, s10, v5
v_add_co_ci_u32_e32 v6, vcc_lo, s11, v6, vcc_lo
global_load_b32 v2, v[11:12], off
v_add_co_u32 v11, vcc_lo, s8, v7
v_add_co_ci_u32_e32 v12, vcc_lo, s9, v8, vcc_lo
global_load_b32 v13, v[5:6], off
v_add_co_u32 v5, vcc_lo, s10, v7
v_add_co_ci_u32_e32 v6, vcc_lo, s11, v8, vcc_lo
global_load_b32 v14, v[11:12], off
v_add_co_u32 v11, vcc_lo, s10, v0
v_add_co_ci_u32_e32 v12, vcc_lo, s11, v1, vcc_lo
global_load_b32 v5, v[5:6], off
global_load_b96 v[6:8], v[9:10], off offset:-4
global_load_b96 v[9:11], v[11:12], off offset:-4
s_mov_b32 s8, 0xd916872b
s_mov_b32 s9, 0x3feff7ce
s_waitcnt vmcnt(2)
v_dual_add_f32 v2, v2, v14 :: v_dual_add_f32 v5, v13, v5
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_1)
v_add_f32_e32 v2, v8, v2
v_cvt_f64_f32_e32 v[15:16], v7
v_cvt_f64_f32_e32 v[13:14], v4
s_waitcnt vmcnt(0)
v_cvt_f64_f32_e32 v[17:18], v10
v_dual_add_f32 v5, v11, v5 :: v_dual_add_f32 v2, v6, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v2, -4.0, v7
v_dual_add_f32 v6, v9, v5 :: v_dual_mul_f32 v5, s21, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_fmac_f32_e32 v6, -4.0, v10
v_cvt_f64_f32_e32 v[2:3], v3
v_cvt_f64_f32_e32 v[8:9], v5
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v6, s21, v6
v_cvt_f64_f32_e32 v[11:12], v6
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_f64 v[7:8], v[8:9], s[6:7]
v_mul_f64 v[9:10], v[11:12], s[6:7]
v_fma_f64 v[11:12], v[2:3], s[6:7], v[15:16]
v_fma_f64 v[15:16], v[13:14], s[6:7], v[17:18]
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_fma_f64 v[2:3], v[2:3], s[8:9], v[7:8]
v_fma_f64 v[7:8], v[13:14], s[8:9], v[9:10]
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_cvt_f32_f64_e32 v4, v[11:12]
v_cvt_f32_f64_e32 v11, v[15:16]
s_delay_alu instid0(VALU_DEP_4)
v_cvt_f32_f64_e32 v12, v[2:3]
v_add_co_u32 v2, vcc_lo, s16, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s17, v1, vcc_lo
v_cvt_f32_f64_e32 v13, v[7:8]
v_add_co_u32 v7, vcc_lo, s18, v0
v_add_co_ci_u32_e32 v8, vcc_lo, s19, v1, vcc_lo
v_add_co_u32 v9, vcc_lo, s12, v0
v_add_co_ci_u32_e32 v10, vcc_lo, s13, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s14, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s15, v1, vcc_lo
global_store_b32 v[2:3], v4, off
global_store_b32 v[7:8], v11, off
global_store_b32 v[9:10], v12, off
global_store_b32 v[0:1], v13, off
.LBB0_5: ; %Flow
s_or_b32 exec_lo, exec_lo, s4
.LBB0_6: ; %Flow155
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s3
.LBB0_7: ; %Flow156
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s2
.LBB0_8:
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
s_or_b32 exec_lo, exec_lo, s22
v_cvt_f64_f32_e64 v[0:1], |v5|
v_cvt_f64_f32_e64 v[2:3], |v6|
s_mov_b32 s2, 0xd2f1a9fc
s_mov_b32 s3, 0x3f50624d
v_max_f64 v[0:1], v[0:1], v[2:3]
s_delay_alu instid0(VALU_DEP_1)
v_cmp_lt_f64_e32 vcc_lo, s[2:3], v[0:1]
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_10
; %bb.9:
s_load_b64 s[0:1], s[0:1], 0x48
s_waitcnt lgkmcnt(0)
s_load_b32 s2, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_add_i32 s2, s2, 1
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
global_store_b32 v0, v1, s[0:1]
.LBB0_10:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z8simulateifPfS_S_S_S_S_S_S_Pi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 336
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 19
.amdhsa_next_free_sgpr 23
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z8simulateifPfS_S_S_S_S_S_S_Pi, .Lfunc_end0-_Z8simulateifPfS_S_S_S_S_S_S_Pi
; -- End function
.section .AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 912
; NumSgprs: 25
; NumVgprs: 19
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 3
; VGPRBlocks: 2
; NumSGPRsForWavesPerEU: 25
; NumVGPRsForWavesPerEU: 19
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object ; @__hip_cuid_
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0 ; 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 40
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 48
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 56
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 64
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 72
.size: 8
.value_kind: global_buffer
- .offset: 80
.size: 4
.value_kind: hidden_block_count_x
- .offset: 84
.size: 4
.value_kind: hidden_block_count_y
- .offset: 88
.size: 4
.value_kind: hidden_block_count_z
- .offset: 92
.size: 2
.value_kind: hidden_group_size_x
- .offset: 94
.size: 2
.value_kind: hidden_group_size_y
- .offset: 96
.size: 2
.value_kind: hidden_group_size_z
- .offset: 98
.size: 2
.value_kind: hidden_remainder_x
- .offset: 100
.size: 2
.value_kind: hidden_remainder_y
- .offset: 102
.size: 2
.value_kind: hidden_remainder_z
- .offset: 120
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 128
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 136
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 144
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 336
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z8simulateifPfS_S_S_S_S_S_S_Pi
.private_segment_fixed_size: 0
.sgpr_count: 25
.sgpr_spill_count: 0
.symbol: _Z8simulateifPfS_S_S_S_S_S_S_Pi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 19
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
```
| 2,082 | 5,695 |
495 |
Convert the following CUDA host assembly code to AMD host assembly:
```cudaasm
.file "tmpxft_0012b95c_00000000-6_springs.cudafe1.cpp"
.text
.globl _ZSt21ios_base_library_initv
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z45__device_stub__Z8simulateifPfS_S_S_S_S_S_S_PiifPfS_S_S_S_S_S_S_Pi
.type _Z45__device_stub__Z8simulateifPfS_S_S_S_S_S_S_PiifPfS_S_S_S_S_S_S_Pi, @function
_Z45__device_stub__Z8simulateifPfS_S_S_S_S_S_S_PiifPfS_S_S_S_S_S_S_Pi:
.LFB3694:
.cfi_startproc
endbr64
subq $248, %rsp
.cfi_def_cfa_offset 256
movl %edi, 76(%rsp)
movss %xmm0, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movq %rcx, 48(%rsp)
movq %r8, 40(%rsp)
movq %r9, 32(%rsp)
movq 256(%rsp), %rax
movq %rax, 24(%rsp)
movq 264(%rsp), %rax
movq %rax, 16(%rsp)
movq 272(%rsp), %rax
movq %rax, 8(%rsp)
movq 280(%rsp), %rax
movq %rax, (%rsp)
movq %fs:40, %rax
movq %rax, 232(%rsp)
xorl %eax, %eax
leaq 76(%rsp), %rax
movq %rax, 144(%rsp)
leaq 72(%rsp), %rax
movq %rax, 152(%rsp)
leaq 64(%rsp), %rax
movq %rax, 160(%rsp)
leaq 56(%rsp), %rax
movq %rax, 168(%rsp)
leaq 48(%rsp), %rax
movq %rax, 176(%rsp)
leaq 40(%rsp), %rax
movq %rax, 184(%rsp)
leaq 32(%rsp), %rax
movq %rax, 192(%rsp)
leaq 24(%rsp), %rax
movq %rax, 200(%rsp)
leaq 16(%rsp), %rax
movq %rax, 208(%rsp)
leaq 8(%rsp), %rax
movq %rax, 216(%rsp)
movq %rsp, %rax
movq %rax, 224(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
movl $1, 104(%rsp)
movl $1, 108(%rsp)
movl $1, 112(%rsp)
movl $1, 116(%rsp)
leaq 88(%rsp), %rcx
leaq 80(%rsp), %rdx
leaq 108(%rsp), %rsi
leaq 96(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 232(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $248, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 88(%rsp)
.cfi_def_cfa_offset 264
pushq 88(%rsp)
.cfi_def_cfa_offset 272
leaq 160(%rsp), %r9
movq 124(%rsp), %rcx
movl 132(%rsp), %r8d
movq 112(%rsp), %rsi
movl 120(%rsp), %edx
leaq _Z8simulateifPfS_S_S_S_S_S_S_Pi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 256
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3694:
.size _Z45__device_stub__Z8simulateifPfS_S_S_S_S_S_S_PiifPfS_S_S_S_S_S_S_Pi, .-_Z45__device_stub__Z8simulateifPfS_S_S_S_S_S_S_PiifPfS_S_S_S_S_S_S_Pi
.globl _Z8simulateifPfS_S_S_S_S_S_S_Pi
.type _Z8simulateifPfS_S_S_S_S_S_S_Pi, @function
_Z8simulateifPfS_S_S_S_S_S_S_Pi:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
pushq 40(%rsp)
.cfi_def_cfa_offset 24
pushq 40(%rsp)
.cfi_def_cfa_offset 32
pushq 40(%rsp)
.cfi_def_cfa_offset 40
pushq 40(%rsp)
.cfi_def_cfa_offset 48
call _Z45__device_stub__Z8simulateifPfS_S_S_S_S_S_S_PiifPfS_S_S_S_S_S_S_Pi
addq $40, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _Z8simulateifPfS_S_S_S_S_S_S_Pi, .-_Z8simulateifPfS_S_S_S_S_S_S_Pi
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC2:
.string "Failed to launch simulate kernel (error code %s)!\n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC3:
.string " "
.text
.globl main
.type main, @function
main:
.LFB3669:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $232, %rsp
.cfi_def_cfa_offset 288
movq %fs:40, %rax
movq %rax, 216(%rsp)
xorl %eax, %eax
leaq 100(%rsp), %rsi
leaq _ZSt3cin(%rip), %rdi
call _ZNSirsERi@PLT
movq %rax, %rdi
leaq 104(%rsp), %rsi
call _ZNSirsERi@PLT
movq %rax, %rdi
leaq 108(%rsp), %rsi
call _ZNSi10_M_extractIfEERSiRT_@PLT
movl 100(%rsp), %r13d
movl %r13d, %r15d
imull %r13d, %r15d
movl %r15d, 44(%rsp)
movslq %r15d, %r12
leaq 0(,%r12,4), %r14
movq %r14, %rdi
call malloc@PLT
movq %rax, %rbp
movq %r14, %rdi
call malloc@PLT
movq %rax, %rbx
movq %r14, %rdi
call malloc@PLT
movq %rax, 56(%rsp)
movq %r14, %rdi
call malloc@PLT
movq %rax, 64(%rsp)
testl %r15d, %r15d
jle .L12
movq %rax, %rdi
movl $0, %ecx
movss .LC1(%rip), %xmm1
movq 56(%rsp), %rsi
jmp .L15
.L37:
movss %xmm1, 0(%rbp,%rcx,4)
movss %xmm1, (%rbx,%rcx,4)
.L13:
addq $1, %rcx
cmpq %rcx, %r12
je .L12
.L15:
movl %ecx, %eax
cltd
idivl %r13d
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movss %xmm0, (%rsi,%rcx,4)
pxor %xmm0, %xmm0
cvtsi2ssl %edx, %xmm0
movss %xmm0, (%rdi,%rcx,4)
movl $0x00000000, 0(%rbp,%rcx,4)
movl $0x00000000, (%rbx,%rcx,4)
testl %eax, %eax
je .L37
testl %edx, %edx
jne .L13
jmp .L37
.L12:
cmpl $0, 104(%rsp)
jle .L16
movl $0, %r15d
leaq 184(%rsp), %rax
movq %rax, 16(%rsp)
leaq 192(%rsp), %rax
movq %rax, 24(%rsp)
movl .LC1(%rip), %r13d
movq %r14, 32(%rsp)
movq 56(%rsp), %r14
movl %r15d, 8(%rsp)
movq 64(%rsp), %r15
jmp .L21
.L18:
addq $1, %rcx
cmpq %rcx, %r12
je .L17
.L20:
movl %ecx, %eax
cltd
idivl %esi
pxor %xmm1, %xmm1
cvtsi2ssl %eax, %xmm1
movaps %xmm4, %xmm0
subss %xmm1, %xmm0
pxor %xmm2, %xmm2
cvtsi2ssl %edx, %xmm2
movaps %xmm3, %xmm1
subss %xmm2, %xmm1
mulss %xmm0, %xmm0
mulss %xmm1, %xmm1
addss %xmm1, %xmm0
comiss %xmm0, %xmm5
jb .L18
movss %xmm4, (%r14,%rcx,4)
movss %xmm3, (%r15,%rcx,4)
movl %r13d, 0(%rbp,%rcx,4)
movl %r13d, (%rbx,%rcx,4)
jmp .L18
.L17:
addl $1, 8(%rsp)
movl 8(%rsp), %eax
cmpl %eax, 104(%rsp)
jle .L44
.L21:
movq 16(%rsp), %rsi
leaq _ZSt3cin(%rip), %rdi
call _ZNSi10_M_extractIfEERSiRT_@PLT
movq %rax, %rdi
movq 24(%rsp), %rsi
call _ZNSi10_M_extractIfEERSiRT_@PLT
movq %rax, %rdi
leaq 204(%rsp), %rsi
call _ZNSi10_M_extractIfEERSiRT_@PLT
cmpl $0, 44(%rsp)
jle .L17
movl 100(%rsp), %esi
movss 184(%rsp), %xmm4
movss 192(%rsp), %xmm3
movss 204(%rsp), %xmm5
mulss %xmm5, %xmm5
movl $0, %ecx
jmp .L20
.L44:
movq 32(%rsp), %r14
.L16:
movq $0, 120(%rsp)
leaq 120(%rsp), %rdi
movq %r14, %rsi
call cudaMalloc@PLT
movq $0, 128(%rsp)
leaq 128(%rsp), %rdi
movq %r14, %rsi
call cudaMalloc@PLT
movq $0, 136(%rsp)
leaq 136(%rsp), %rdi
movq %r14, %rsi
call cudaMalloc@PLT
movq $0, 144(%rsp)
leaq 144(%rsp), %rdi
movq %r14, %rsi
call cudaMalloc@PLT
movq $0, 152(%rsp)
leaq 152(%rsp), %rdi
movq %r14, %rsi
call cudaMalloc@PLT
movq $0, 160(%rsp)
leaq 160(%rsp), %rdi
movq %r14, %rsi
call cudaMalloc@PLT
movq $0, 168(%rsp)
leaq 168(%rsp), %rdi
movq %r14, %rsi
call cudaMalloc@PLT
movq $0, 176(%rsp)
leaq 176(%rsp), %rdi
movq %r14, %rsi
call cudaMalloc@PLT
movq $0, 184(%rsp)
leaq 184(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
movl $1, 112(%rsp)
leaq 112(%rsp), %rsi
movl $1, %ecx
movl $4, %edx
movq 184(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %r14, %rdx
movq %rbp, %rsi
movq 120(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %r14, %rdx
movq %rbx, %rsi
movq 128(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %r14, %rdx
movq 56(%rsp), %r13
movq %r13, %rsi
movq 136(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %r14, %rdx
movq 64(%rsp), %r15
movq %r15, %rsi
movq 144(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %r14, %rdx
movq %rbp, %rsi
movq 152(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %r14, %rdx
movq %rbx, %rsi
movq 160(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %r14, %rdx
movq %r13, %rsi
movq 168(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %r14, %rdx
movq %r15, %rsi
movq 176(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, 200(%rsp)
movl 100(%rsp), %eax
leal 15(%rax), %edx
shrl $4, %edx
movl %edx, 204(%rsp)
addl $31, %eax
shrl $5, %eax
movl %eax, 208(%rsp)
movl $1, 212(%rsp)
movl $0, 8(%rsp)
movl $1, %r12d
leaq 116(%rsp), %rax
movq %rax, 48(%rsp)
movq %r14, 72(%rsp)
movq %rbp, 80(%rsp)
movq %rbx, 88(%rsp)
jmp .L25
.L22:
movq 152(%rsp), %rax
movq %rax, 16(%rsp)
movq 160(%rsp), %rax
movq %rax, 24(%rsp)
movq 168(%rsp), %rax
movq %rax, 32(%rsp)
movq 176(%rsp), %rbx
movq 120(%rsp), %rbp
movq 128(%rsp), %r13
movq 136(%rsp), %r14
movq 144(%rsp), %r15
.L23:
xorl $1, %r12d
movl $16, 192(%rsp)
movl $32, 196(%rsp)
movl 200(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 192(%rsp), %rdx
movq 204(%rsp), %rdi
movl 212(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L45
.L24:
movl $2, %ecx
movl $4, %edx
movq 184(%rsp), %rsi
movq 48(%rsp), %rdi
call cudaMemcpy@PLT
movl 116(%rsp), %eax
movl 8(%rsp), %ebx
cmpl %ebx, %eax
je .L46
movl %eax, 8(%rsp)
.L25:
testb %r12b, %r12b
je .L22
movq 120(%rsp), %rax
movq %rax, 16(%rsp)
movq 128(%rsp), %rax
movq %rax, 24(%rsp)
movq 136(%rsp), %rax
movq %rax, 32(%rsp)
movq 144(%rsp), %rbx
movq 152(%rsp), %rbp
movq 160(%rsp), %r13
movq 168(%rsp), %r14
movq 176(%rsp), %r15
jmp .L23
.L45:
pushq 184(%rsp)
.cfi_def_cfa_offset 296
pushq %r15
.cfi_def_cfa_offset 304
pushq %r14
.cfi_def_cfa_offset 312
pushq %r13
.cfi_def_cfa_offset 320
movq %rbp, %r9
movq %rbx, %r8
movq 64(%rsp), %rcx
movq 56(%rsp), %rdx
movq 48(%rsp), %rsi
movss 140(%rsp), %xmm0
movl 132(%rsp), %edi
call _Z45__device_stub__Z8simulateifPfS_S_S_S_S_S_S_PiifPfS_S_S_S_S_S_S_Pi
addq $32, %rsp
.cfi_def_cfa_offset 288
jmp .L24
.L46:
movq 72(%rsp), %r14
movq 80(%rsp), %rbp
movq 88(%rsp), %rbx
call cudaDeviceSynchronize@PLT
call cudaGetLastError@PLT
testl %eax, %eax
jne .L47
testb %r12b, %r12b
je .L27
movl $2, %ecx
movq %r14, %rdx
movq 152(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
movl $2, %ecx
movq %r14, %rdx
movq 160(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
movl $2, %ecx
movq %r14, %rdx
movq 168(%rsp), %rsi
movq 56(%rsp), %rdi
call cudaMemcpy@PLT
movq 176(%rsp), %rsi
.L28:
movl $2, %ecx
movq %r14, %rdx
movq 64(%rsp), %r12
movq %r12, %rdi
call cudaMemcpy@PLT
movq 120(%rsp), %rdi
call cudaFree@PLT
movq 128(%rsp), %rdi
call cudaFree@PLT
movq 136(%rsp), %rdi
call cudaFree@PLT
movq 144(%rsp), %rdi
call cudaFree@PLT
movq 152(%rsp), %rdi
call cudaFree@PLT
movq 160(%rsp), %rdi
call cudaFree@PLT
movq 168(%rsp), %rdi
call cudaFree@PLT
movq 176(%rsp), %rdi
call cudaFree@PLT
movq 184(%rsp), %rdi
call cudaFree@PLT
cmpl $0, 44(%rsp)
jle .L29
movq 56(%rsp), %rax
movq %rax, %r13
leaq (%r14,%rax), %r15
leaq _ZSt4cout(%rip), %r14
movq %rbp, 8(%rsp)
movq %rbx, 16(%rsp)
jmp .L34
.L47:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L27:
movl $2, %ecx
movq %r14, %rdx
movq 120(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
movl $2, %ecx
movq %r14, %rdx
movq 128(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
movl $2, %ecx
movq %r14, %rdx
movq 136(%rsp), %rsi
movq 56(%rsp), %rdi
call cudaMemcpy@PLT
movq 144(%rsp), %rsi
jmp .L28
.L50:
movq 216(%rsp), %rax
subq %fs:40, %rax
jne .L48
call _ZSt16__throw_bad_castv@PLT
.L48:
call __stack_chk_fail@PLT
.L32:
movq %rbp, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq 0(%rbp), %rax
movl $10, %esi
movq %rbp, %rdi
call *48(%rax)
movl %eax, %esi
.L33:
movsbl %sil, %esi
movq %rbx, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
addq $4, %r13
addq $4, %r12
cmpq %r15, %r13
je .L49
.L34:
pxor %xmm0, %xmm0
cvtss2sd 0(%r13), %xmm0
movq %r14, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rbx
movl $1, %edx
leaq .LC3(%rip), %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
pxor %xmm0, %xmm0
cvtss2sd (%r12), %xmm0
movq %rbx, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rbx
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %rbp
testq %rbp, %rbp
je .L50
cmpb $0, 56(%rbp)
je .L32
movzbl 67(%rbp), %esi
jmp .L33
.L49:
movq 8(%rsp), %rbp
movq 16(%rsp), %rbx
.L29:
movq 56(%rsp), %rdi
call free@PLT
movq 64(%rsp), %rdi
call free@PLT
movq %rbp, %rdi
call free@PLT
movq %rbx, %rdi
call free@PLT
movq 216(%rsp), %rax
subq %fs:40, %rax
jne .L51
movl $0, %eax
addq $232, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L51:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size main, .-main
.section .rodata.str1.8
.align 8
.LC4:
.string "_Z8simulateifPfS_S_S_S_S_S_S_Pi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3697:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z8simulateifPfS_S_S_S_S_S_S_Pi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC1:
.long 2139095039
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
```
|
```amdasm
.text
.file "springs.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z23__device_stub__simulateifPfS_S_S_S_S_S_S_Pi # -- Begin function _Z23__device_stub__simulateifPfS_S_S_S_S_S_S_Pi
.type _Z23__device_stub__simulateifPfS_S_S_S_S_S_S_Pi,@function
_Z23__device_stub__simulateifPfS_S_S_S_S_S_S_Pi: # @_Z23__device_stub__simulateifPfS_S_S_S_S_S_S_Pi
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $192, %rsp
.cfi_def_cfa_offset 240
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 4(%rsp), %rax
movl %edi, (%rax)
movq %rsp, %rdi
movss %xmm0, (%rdi)
leaq 56(%rsp), %r10
movq %rsi, (%r10)
leaq 48(%rsp), %rsi
movq %rdx, (%rsi)
leaq 40(%rsp), %rdx
movq %rcx, (%rdx)
leaq 32(%rsp), %rcx
movq %r8, (%rcx)
leaq 24(%rsp), %r8
movq %r9, (%r8)
leaq 96(%rsp), %rbx
movq %rax, (%rbx)
movq %rdi, 8(%rbx)
movq %r10, 16(%rbx)
movq %rsi, 24(%rbx)
movq %rdx, 32(%rbx)
movq %rcx, 40(%rbx)
movq %r8, 48(%rbx)
leaq 240(%rsp), %rax
movq %rax, 56(%rbx)
leaq 248(%rsp), %rax
movq %rax, 64(%rbx)
leaq 256(%rsp), %rax
movq %rax, 72(%rbx)
leaq 264(%rsp), %rax
movq %rax, 80(%rbx)
leaq 80(%rsp), %r14
leaq 64(%rsp), %r15
leaq 16(%rsp), %r12
leaq 8(%rsp), %r13
movq %r14, %rdi
movq %r15, %rsi
movq %r12, %rdx
movq %r13, %rcx
callq __hipPopCallConfiguration
movq (%r14), %rsi
movl 8(%r14), %edx
movq (%r15), %rcx
movl 8(%r15), %r8d
movl $_Z8simulateifPfS_S_S_S_S_S_S_Pi, %edi
movq %rbx, %r9
pushq (%r13)
.cfi_adjust_cfa_offset 8
pushq (%r12)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $208, %rsp
.cfi_adjust_cfa_offset -208
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z23__device_stub__simulateifPfS_S_S_S_S_S_S_Pi, .Lfunc_end0-_Z23__device_stub__simulateifPfS_S_S_S_S_S_S_Pi
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $200, %rsp
.cfi_def_cfa_offset 256
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
leaq 12(%rsp), %rbx
movl $_ZSt3cin, %edi
movq %rbx, %rsi
callq _ZNSirsERi
leaq 44(%rsp), %rsi
movq %rax, %rdi
callq _ZNSirsERi
leaq 124(%rsp), %rsi
movq %rax, %rdi
callq _ZNSi10_M_extractIfEERSiRT_
movl (%rbx), %ebp
movl %ebp, %r14d
imull %r14d, %r14d
leaq (,%r14,4), %r13
movq %r13, %rdi
callq malloc
movq %rax, %r12
movq %r13, %rdi
callq malloc
movq %rax, %rbx
movq %r13, %rdi
callq malloc
movq %rax, %r15
movq %r13, 136(%rsp) # 8-byte Spill
movq %r13, %rdi
callq malloc
movq %rax, %r9
movl %ebp, 8(%rsp) # 4-byte Spill
testl %ebp, %ebp
je .LBB1_6
# %bb.1: # %.lr.ph.preheader
cmpl $1, %r14d
movl %r14d, %esi
adcl $0, %esi
xorl %edi, %edi
movl $2139095039, %r8d # imm = 0x7F7FFFFF
xorl %ecx, %ecx
.LBB1_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl %ecx, %eax
cltd
idivl 8(%rsp) # 4-byte Folded Reload
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movss %xmm0, (%r15,%rcx,4)
xorps %xmm0, %xmm0
cvtsi2ss %edx, %xmm0
movss %xmm0, (%r9,%rcx,4)
movl %edi, (%r12,%rcx,4)
movl %edi, (%rbx,%rcx,4)
testl %eax, %eax
je .LBB1_4
# %bb.3: # %.lr.ph
# in Loop: Header=BB1_2 Depth=1
testl %edx, %edx
jne .LBB1_5
.LBB1_4: # in Loop: Header=BB1_2 Depth=1
movl %r8d, (%r12,%rcx,4)
movl %r8d, (%rbx,%rcx,4)
.LBB1_5: # in Loop: Header=BB1_2 Depth=1
incq %rcx
cmpq %rcx, %rsi
jne .LBB1_2
.LBB1_6: # %.preheader
movq %r9, 96(%rsp) # 8-byte Spill
movq %r15, 104(%rsp) # 8-byte Spill
movq %r14, 128(%rsp) # 8-byte Spill
movq %rbx, 48(%rsp) # 8-byte Spill
cmpl $0, 44(%rsp)
jle .LBB1_14
# %bb.7: # %.lr.ph135
movq 128(%rsp), %rbx # 8-byte Reload
cmpl $1, %ebx
# kill: def $ebx killed $ebx killed $rbx def $rbx
adcl $0, %ebx
xorl %r14d, %r14d
leaq 24(%rsp), %rbp
leaq 16(%rsp), %r13
movl $2139095039, %r15d # imm = 0x7F7FFFFF
.LBB1_8: # =>This Loop Header: Depth=1
# Child Loop BB1_10 Depth 2
movl $_ZSt3cin, %edi
leaq 32(%rsp), %rsi
callq _ZNSi10_M_extractIfEERSiRT_
movq %rax, %rdi
movq %rbp, %rsi
callq _ZNSi10_M_extractIfEERSiRT_
movq %rax, %rdi
movq %r13, %rsi
callq _ZNSi10_M_extractIfEERSiRT_
cmpl $0, 8(%rsp) # 4-byte Folded Reload
movq 48(%rsp), %rdi # 8-byte Reload
movq 104(%rsp), %r8 # 8-byte Reload
movq 96(%rsp), %r9 # 8-byte Reload
je .LBB1_13
# %bb.9: # %.lr.ph133
# in Loop: Header=BB1_8 Depth=1
movl 12(%rsp), %esi
movss 32(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
movss 24(%rsp), %xmm1 # xmm1 = mem[0],zero,zero,zero
movss 16(%rsp), %xmm2 # xmm2 = mem[0],zero,zero,zero
mulss %xmm2, %xmm2
xorl %ecx, %ecx
.LBB1_10: # Parent Loop BB1_8 Depth=1
# => This Inner Loop Header: Depth=2
movl %ecx, %eax
cltd
idivl %esi
xorps %xmm3, %xmm3
cvtsi2ss %eax, %xmm3
movaps %xmm0, %xmm4
xorps %xmm5, %xmm5
cvtsi2ss %edx, %xmm5
subss %xmm3, %xmm4
mulss %xmm4, %xmm4
movaps %xmm1, %xmm3
subss %xmm5, %xmm3
mulss %xmm3, %xmm3
addss %xmm4, %xmm3
ucomiss %xmm3, %xmm2
jb .LBB1_12
# %bb.11: # in Loop: Header=BB1_10 Depth=2
movss %xmm0, (%r8,%rcx,4)
movss %xmm1, (%r9,%rcx,4)
movl %r15d, (%r12,%rcx,4)
movl %r15d, (%rdi,%rcx,4)
.LBB1_12: # in Loop: Header=BB1_10 Depth=2
incq %rcx
cmpq %rcx, %rbx
jne .LBB1_10
.LBB1_13: # %._crit_edge
# in Loop: Header=BB1_8 Depth=1
incl %r14d
cmpl 44(%rsp), %r14d
jl .LBB1_8
.LBB1_14: # %._crit_edge136
xorl %ebp, %ebp
leaq 32(%rsp), %r14
movq %rbp, (%r14)
movq %r14, %rdi
movq 136(%rsp), %r13 # 8-byte Reload
movq %r13, %rsi
callq hipMalloc
leaq 24(%rsp), %r15
movq %rbp, (%r15)
movq %r15, %rdi
movq %r13, %rsi
callq hipMalloc
leaq 16(%rsp), %rdi
movq %rbp, (%rdi)
movq %r13, %rsi
callq hipMalloc
leaq 88(%rsp), %rdi
movq %rbp, (%rdi)
movq %r13, %rsi
callq hipMalloc
leaq 80(%rsp), %rdi
movq %rbp, (%rdi)
movq %r13, %rsi
callq hipMalloc
leaq 72(%rsp), %rdi
movq %rbp, (%rdi)
movq %r13, %rsi
callq hipMalloc
leaq 64(%rsp), %rdi
movq %rbp, (%rdi)
movq %r13, %rsi
callq hipMalloc
leaq 56(%rsp), %rdi
movq %rbp, (%rdi)
movq %r13, %rsi
callq hipMalloc
leaq 112(%rsp), %rbx
xorl %eax, %eax
movq %rax, 144(%rsp) # 8-byte Spill
movq %rbp, (%rbx)
movl $4, %esi
movq %rbx, %rdi
callq hipMalloc
leaq 196(%rsp), %rsi
movl $1, (%rsi)
movq (%rbx), %rdi
movl $4, %edx
movl $1, %ecx
callq hipMemcpy
movq (%r14), %rdi
movq %r12, %rsi
movq %r13, %rdx
movl $1, %ecx
callq hipMemcpy
movq (%r15), %rdi
movq 48(%rsp), %rbx # 8-byte Reload
movq %rbx, %rsi
movq %r13, %rdx
movl $1, %ecx
callq hipMemcpy
leaq 16(%rsp), %rax
movq (%rax), %rdi
movq 104(%rsp), %r14 # 8-byte Reload
movq %r14, %rsi
movq %r13, %rdx
movl $1, %ecx
callq hipMemcpy
leaq 88(%rsp), %rax
movq (%rax), %rdi
movq 96(%rsp), %r15 # 8-byte Reload
movq %r15, %rsi
movq %r13, %rdx
movl $1, %ecx
callq hipMemcpy
leaq 80(%rsp), %rax
movq (%rax), %rdi
movq %r12, 152(%rsp) # 8-byte Spill
movq %r12, %rsi
movq %r13, %rdx
movl $1, %ecx
callq hipMemcpy
leaq 72(%rsp), %rax
movq (%rax), %rdi
movq %rbx, %rsi
movq %r13, %rdx
movl $1, %ecx
callq hipMemcpy
leaq 64(%rsp), %rax
movq (%rax), %rdi
movq %r14, %rsi
movq %r13, %rdx
movl $1, %ecx
callq hipMemcpy
leaq 56(%rsp), %rax
movq (%rax), %rdi
movq %r15, %rsi
movq %r13, %rdx
movl $1, %ecx
callq hipMemcpy
movl 12(%rsp), %ecx
leal 15(%rcx), %eax
shrl $4, %eax
addl $31, %ecx
shrl $5, %ecx
shlq $32, %rcx
orq %rax, %rcx
movq %rcx, 160(%rsp) # 8-byte Spill
movb $1, %bl
.LBB1_15: # =>This Inner Loop Header: Depth=1
movl %ebx, %r15d
movq 32(%rsp), %rax
movq %rax, 184(%rsp) # 8-byte Spill
movq 80(%rsp), %r13
movq 24(%rsp), %rax
movq %rax, 176(%rsp) # 8-byte Spill
movq 72(%rsp), %rbp
movq 16(%rsp), %rax
movq %rax, 168(%rsp) # 8-byte Spill
movq 64(%rsp), %rbx
movq 88(%rsp), %r12
movq 56(%rsp), %r14
movq 160(%rsp), %rdi # 8-byte Reload
movl $1, %esi
movabsq $137438953488, %rdx # imm = 0x2000000010
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_17
# %bb.16: # in Loop: Header=BB1_15 Depth=1
testb $1, %r15b
movq %r12, %rax
cmovneq %r14, %rax
movq 168(%rsp), %rsi # 8-byte Reload
movq %rsi, %r10
cmovneq %rbx, %r10
movq 176(%rsp), %rdx # 8-byte Reload
movq %rdx, %r11
cmovneq %rbp, %r11
movq 184(%rsp), %rcx # 8-byte Reload
movq %rcx, %r9
cmovneq %r13, %r9
cmovneq %r12, %r14
cmovneq %rsi, %rbx
cmovneq %rdx, %rbp
cmovneq %rcx, %r13
movl 12(%rsp), %edi
movss 124(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
movq %r13, %rsi
movq %rbp, %rdx
movq %rbx, %rcx
movq %r14, %r8
pushq 112(%rsp)
.cfi_adjust_cfa_offset 8
pushq %rax
.cfi_adjust_cfa_offset 8
pushq %r10
.cfi_adjust_cfa_offset 8
pushq %r11
.cfi_adjust_cfa_offset 8
callq _Z23__device_stub__simulateifPfS_S_S_S_S_S_S_Pi
addq $32, %rsp
.cfi_adjust_cfa_offset -32
.LBB1_17: # in Loop: Header=BB1_15 Depth=1
movl %r15d, %ebx
xorb $1, %bl
movq 112(%rsp), %rsi
movl $4, %edx
leaq 120(%rsp), %rdi
movl $2, %ecx
callq hipMemcpy
movl 120(%rsp), %eax
cmpl 144(%rsp), %eax # 4-byte Folded Reload
# kill: def $eax killed $eax def $rax
movq %rax, 144(%rsp) # 8-byte Spill
jne .LBB1_15
# %bb.18:
callq hipDeviceSynchronize
callq hipGetLastError
testl %eax, %eax
jne .LBB1_23
# %bb.19:
testb $1, %r15b
leaq 32(%rsp), %rax
leaq 80(%rsp), %rcx
cmovneq %rax, %rcx
movq (%rcx), %rsi
leaq 24(%rsp), %rax
leaq 72(%rsp), %r13
cmovneq %rax, %r13
leaq 16(%rsp), %rax
leaq 64(%rsp), %r12
cmovneq %rax, %r12
leaq 88(%rsp), %rax
leaq 56(%rsp), %r14
cmovneq %rax, %r14
movq 152(%rsp), %r15 # 8-byte Reload
movq %r15, %rdi
movq 136(%rsp), %rbx # 8-byte Reload
movq %rbx, %rdx
movl $2, %ecx
callq hipMemcpy
movq (%r13), %rsi
movq 48(%rsp), %rdi # 8-byte Reload
movq %rbx, %rdx
movl $2, %ecx
callq hipMemcpy
movq (%r12), %rsi
movq 104(%rsp), %r13 # 8-byte Reload
movq %r13, %rdi
movq %rbx, %rdx
movl $2, %ecx
callq hipMemcpy
movq (%r14), %rsi
movq 96(%rsp), %rbp # 8-byte Reload
movq %rbp, %rdi
movq %rbx, %rdx
movl $2, %ecx
callq hipMemcpy
movq 32(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 88(%rsp), %rdi
callq hipFree
movq 80(%rsp), %rdi
callq hipFree
movq 72(%rsp), %rdi
callq hipFree
movq 64(%rsp), %rdi
callq hipFree
movq 56(%rsp), %rdi
callq hipFree
movq 112(%rsp), %rdi
callq hipFree
cmpl $0, 8(%rsp) # 4-byte Folded Reload
movq 128(%rsp), %r12 # 8-byte Reload
je .LBB1_22
# %bb.20: # %.lr.ph139.preheader
cmpl $1, %r12d
adcl $0, %r12d
xorl %r14d, %r14d
.LBB1_21: # %.lr.ph139
# =>This Inner Loop Header: Depth=1
xorps %xmm0, %xmm0
cvtss2sd (%r13,%r14,4), %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq %rax, %rbx
movl $.L.str.1, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
xorps %xmm0, %xmm0
cvtss2sd (%rbp,%r14,4), %xmm0
movq %rbx, %rdi
callq _ZNSo9_M_insertIdEERSoT_
movq %rax, %rbx
movq (%rax), %rax
movq -24(%rax), %rdi
addq %rbx, %rdi
movl $10, %esi
callq _ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
movsbl %al, %esi
movq %rbx, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
incq %r14
cmpq %r14, %r12
jne .LBB1_21
.LBB1_22: # %._crit_edge140
movq %r13, %rdi
callq free
movq %rbp, %rdi
callq free
movq %r15, %rdi
callq free
movq 48(%rsp), %rdi # 8-byte Reload
callq free
xorl %eax, %eax
addq $200, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB1_23:
.cfi_def_cfa_offset 256
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %esi
movq %rbx, %rdi
movq %rax, %rdx
xorl %eax, %eax
callq fprintf
movl $1, %edi
callq exit
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, %rdi
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8simulateifPfS_S_S_S_S_S_S_Pi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z8simulateifPfS_S_S_S_S_S_S_Pi,@object # @_Z8simulateifPfS_S_S_S_S_S_S_Pi
.section .rodata,"a",@progbits
.globl _Z8simulateifPfS_S_S_S_S_S_S_Pi
.p2align 3, 0x0
_Z8simulateifPfS_S_S_S_S_S_S_Pi:
.quad _Z23__device_stub__simulateifPfS_S_S_S_S_S_S_Pi
.size _Z8simulateifPfS_S_S_S_S_S_S_Pi, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Failed to launch simulate kernel (error code %s)!\n"
.size .L.str, 51
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz " "
.size .L.str.1, 2
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z8simulateifPfS_S_S_S_S_S_S_Pi"
.size .L__unnamed_1, 32
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z23__device_stub__simulateifPfS_S_S_S_S_S_S_Pi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z8simulateifPfS_S_S_S_S_S_S_Pi
.addrsig_sym _ZSt3cin
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
```
| 7,917 | 8,280 |
496 |
Convert the following CUDA device assembly code to AMD device assembly:
```cudaasm
code for sm_80
Function : _Z8testInitPf
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
MOV R1, c[0x0][0x28] ;
S2R R2, SR_CTAID.X ;
HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ;
MOV R7, 0x3f800000 ;
ULDC.64 UR4, c[0x0][0x118] ;
S2R R3, SR_TID.X ;
IMAD R2, R2, c[0x0][0x0], R3 ;
IMAD.WIDE R2, R2, R5, c[0x0][0x160] ;
STG.E [R2.64], R7 ;
EXIT ;
BRA 0xa0;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
Function : _Z5helloPiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
MOV R1, c[0x0][0x28] ;
S2R R13, SR_CTAID.X ;
HFMA2.MMA R6, -RZ, RZ, 0, 2.384185791015625e-07 ;
ULDC.64 UR4, c[0x0][0x118] ;
S2R R0, SR_TID.X ;
S2R R2, SR_TID.Y ;
S2R R4, SR_TID.Z ;
IMAD R9, R13, c[0x0][0x0], R0 ;
IMAD R11, R13, c[0x0][0x4], R2 ;
IMAD.WIDE R2, R9, R6, c[0x0][0x160] ;
IMAD R13, R13, c[0x0][0x8], R4 ;
STG.E [R2.64], R9 ;
IMAD.WIDE R4, R11, R6, c[0x0][0x168] ;
IMAD.WIDE R6, R13, R6, c[0x0][0x170] ;
STG.E [R4.64], R11 ;
STG.E [R6.64], R13 ;
EXIT ;
BRA 0x110;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
```
|
```amdasm
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z5helloPiS_S_ ; -- Begin function _Z5helloPiS_S_
.globl _Z5helloPiS_S_
.p2align 8
.type _Z5helloPiS_S_,@function
_Z5helloPiS_S_: ; @_Z5helloPiS_S_
; %bb.0:
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x24
s_load_b128 s[4:7], s[0:1], 0x0
v_and_b32_e32 v1, 0x3ff, v0
v_bfe_u32 v2, v0, 10, 10
v_bfe_u32 v0, v0, 20, 10
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_lshr_b32 s8, s2, 16
s_and_b32 s2, s2, 0xffff
s_and_b32 s3, s3, 0xffff
v_mad_u64_u32 v[3:4], null, s15, s2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_mad_u64_u32 v[5:6], null, s15, s8, v[2:3]
v_mad_u64_u32 v[1:2], null, s15, s3, v[0:1]
v_ashrrev_i32_e32 v4, 31, v3
v_ashrrev_i32_e32 v6, 31, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
v_lshlrev_b64 v[7:8], 2, v[3:4]
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[9:10], 2, v[5:6]
v_lshlrev_b64 v[11:12], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_add_co_u32 v6, vcc_lo, s4, v7
v_add_co_ci_u32_e32 v7, vcc_lo, s5, v8, vcc_lo
v_add_co_u32 v8, vcc_lo, s6, v9
v_add_co_ci_u32_e32 v9, vcc_lo, s7, v10, vcc_lo
v_add_co_u32 v10, vcc_lo, s0, v11
v_add_co_ci_u32_e32 v11, vcc_lo, s1, v12, vcc_lo
global_store_b32 v[6:7], v3, off
global_store_b32 v[8:9], v5, off
global_store_b32 v[10:11], v1, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z5helloPiS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 2
.amdhsa_next_free_vgpr 13
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z5helloPiS_S_, .Lfunc_end0-_Z5helloPiS_S_
; -- End function
.section .AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 224
; NumSgprs: 18
; NumVgprs: 13
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 13
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 2
.text
.protected _Z8testInitPf ; -- Begin function _Z8testInitPf
.globl _Z8testInitPf
.p2align 8
.type _Z8testInitPf,@function
_Z8testInitPf: ; @_Z8testInitPf
; %bb.0:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x14
s_load_b64 s[0:1], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[0:1], 2, v[1:2]
v_mov_b32_e32 v2, 1.0
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z8testInitPf
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 264
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z8testInitPf, .Lfunc_end1-_Z8testInitPf
; -- End function
.section .AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 100
; NumSgprs: 18
; NumVgprs: 3
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 3
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object ; @__hip_cuid_
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0 ; 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z5helloPiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z5helloPiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 13
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: hidden_block_count_x
- .offset: 12
.size: 4
.value_kind: hidden_block_count_y
- .offset: 16
.size: 4
.value_kind: hidden_block_count_z
- .offset: 20
.size: 2
.value_kind: hidden_group_size_x
- .offset: 22
.size: 2
.value_kind: hidden_group_size_y
- .offset: 24
.size: 2
.value_kind: hidden_group_size_z
- .offset: 26
.size: 2
.value_kind: hidden_remainder_x
- .offset: 28
.size: 2
.value_kind: hidden_remainder_y
- .offset: 30
.size: 2
.value_kind: hidden_remainder_z
- .offset: 48
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 72
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 264
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z8testInitPf
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z8testInitPf.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
```
| 676 | 4,630 |
497 |
Convert the following CUDA host assembly code to AMD host assembly:
```cudaasm
.file "tmpxft_0018368c_00000000-6_TestDemo.cudafe1.cpp"
.text
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z28__device_stub__Z5helloPiS_S_PiS_S_
.type _Z28__device_stub__Z5helloPiS_S_PiS_S_, @function
_Z28__device_stub__Z5helloPiS_S_PiS_S_:
.LFB2082:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z5helloPiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z28__device_stub__Z5helloPiS_S_PiS_S_, .-_Z28__device_stub__Z5helloPiS_S_PiS_S_
.globl _Z5helloPiS_S_
.type _Z5helloPiS_S_, @function
_Z5helloPiS_S_:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z28__device_stub__Z5helloPiS_S_PiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z5helloPiS_S_, .-_Z5helloPiS_S_
.globl _Z27__device_stub__Z8testInitPfPf
.type _Z27__device_stub__Z8testInitPfPf, @function
_Z27__device_stub__Z8testInitPfPf:
.LFB2084:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z8testInitPf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z27__device_stub__Z8testInitPfPf, .-_Z27__device_stub__Z8testInitPfPf
.globl _Z8testInitPf
.type _Z8testInitPf, @function
_Z8testInitPf:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z27__device_stub__Z8testInitPfPf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z8testInitPf, .-_Z8testInitPf
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "\n"
.LC1:
.string "%d=%f "
.LC2:
.string "%d=%d "
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $464, %rsp
.cfi_def_cfa_offset 496
movq %fs:40, %rax
movq %rax, 456(%rsp)
xorl %eax, %eax
leaq 64(%rsp), %rdi
movl $16, %ecx
rep stosq
leaq 192(%rsp), %rdi
movl $16, %ecx
rep stosq
leaq 320(%rsp), %rdi
movl $16, %ecx
rep stosq
movl $32000000, %edi
call malloc@PLT
movq %rax, %rbp
leaq 32(%rsp), %rdi
movl $32000000, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $32000000, %edx
movq %rbp, %rsi
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
leaq 8(%rsp), %rdi
movl $128, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $128, %esi
call cudaMalloc@PLT
leaq 192(%rsp), %rsi
movl $1, %ecx
movl $128, %edx
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
leaq 64(%rsp), %rsi
movl $1, %ecx
movl $128, %edx
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
leaq 24(%rsp), %rdi
movl $128, %esi
call cudaMalloc@PLT
leaq 320(%rsp), %rsi
movl $1, %ecx
movl $128, %edx
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl $200, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $200, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 52(%rsp), %rdx
movl $1, %ecx
movq 40(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L32
.L20:
movl $4, 40(%rsp)
movl $4, 44(%rsp)
movl $4, 48(%rsp)
movl $2, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 40(%rsp), %rdx
movl $4, %ecx
movq 52(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L33
.L21:
movl $2, %ecx
movl $32000000, %edx
movq 32(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
leaq 64(%rsp), %rdi
movl $2, %ecx
movl $128, %edx
movq 16(%rsp), %rsi
call cudaMemcpy@PLT
leaq 192(%rsp), %rdi
movl $2, %ecx
movl $128, %edx
movq 8(%rsp), %rsi
call cudaMemcpy@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
leaq 320(%rsp), %rdi
movl $2, %ecx
movl $128, %edx
movq 24(%rsp), %rsi
call cudaMemcpy@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %ebx
leaq .LC1(%rip), %r12
.L22:
pxor %xmm0, %xmm0
cvtss2sd 0(%rbp,%rbx,4), %xmm0
movl %ebx, %edx
movq %r12, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq $32, %rbx
jne .L22
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %ebx
leaq .LC2(%rip), %rbp
.L23:
movl 192(%rsp,%rbx,4), %ecx
movl %ebx, %edx
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq $32, %rbx
jne .L23
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %ebx
leaq .LC2(%rip), %rbp
.L24:
movl 64(%rsp,%rbx,4), %ecx
movl %ebx, %edx
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq $32, %rbx
jne .L24
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %ebx
leaq .LC2(%rip), %rbp
.L25:
movl 320(%rsp,%rbx,4), %ecx
movl %ebx, %edx
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq $32, %rbx
jne .L25
movq 456(%rsp), %rax
subq %fs:40, %rax
jne .L34
movl $0, %eax
addq $464, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L32:
.cfi_restore_state
movq %rbp, %rdi
call _Z27__device_stub__Z8testInitPfPf
jmp .L20
.L33:
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z28__device_stub__Z5helloPiS_S_PiS_S_
jmp .L21
.L34:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC3:
.string "_Z8testInitPf"
.LC4:
.string "_Z5helloPiS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z8testInitPf(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z5helloPiS_S_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
```
|
```amdasm
.text
.file "TestDemo.hip"
.globl _Z20__device_stub__helloPiS_S_ # -- Begin function _Z20__device_stub__helloPiS_S_
.type _Z20__device_stub__helloPiS_S_,@function
_Z20__device_stub__helloPiS_S_: # @_Z20__device_stub__helloPiS_S_
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $112, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 40(%rsp), %rax
movq %rdi, (%rax)
leaq 32(%rsp), %rcx
movq %rsi, (%rcx)
leaq 24(%rsp), %rsi
movq %rdx, (%rsi)
leaq 80(%rsp), %rbx
movq %rax, (%rbx)
movq %rcx, 8(%rbx)
movq %rsi, 16(%rbx)
leaq 64(%rsp), %r14
leaq 48(%rsp), %r15
leaq 16(%rsp), %r12
leaq 8(%rsp), %r13
movq %r14, %rdi
movq %r15, %rsi
movq %r12, %rdx
movq %r13, %rcx
callq __hipPopCallConfiguration
movq (%r14), %rsi
movl 8(%r14), %edx
movq (%r15), %rcx
movl 8(%r15), %r8d
movl $_Z5helloPiS_S_, %edi
movq %rbx, %r9
pushq (%r13)
.cfi_adjust_cfa_offset 8
pushq (%r12)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $128, %rsp
.cfi_adjust_cfa_offset -128
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z20__device_stub__helloPiS_S_, .Lfunc_end0-_Z20__device_stub__helloPiS_S_
.cfi_endproc
# -- End function
.globl _Z23__device_stub__testInitPf # -- Begin function _Z23__device_stub__testInitPf
.type _Z23__device_stub__testInitPf,@function
_Z23__device_stub__testInitPf: # @_Z23__device_stub__testInitPf
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $64, %rsp
.cfi_def_cfa_offset 112
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 24(%rsp), %rax
movq %rdi, (%rax)
movq %rsp, %rbx
movq %rax, (%rbx)
leaq 48(%rsp), %r14
leaq 32(%rsp), %r15
leaq 16(%rsp), %r12
leaq 8(%rsp), %r13
movq %r14, %rdi
movq %r15, %rsi
movq %r12, %rdx
movq %r13, %rcx
callq __hipPopCallConfiguration
movq (%r14), %rsi
movl 8(%r14), %edx
movq (%r15), %rcx
movl 8(%r15), %r8d
movl $_Z8testInitPf, %edi
movq %rbx, %r9
pushq (%r13)
.cfi_adjust_cfa_offset 8
pushq (%r12)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $80, %rsp
.cfi_adjust_cfa_offset -80
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z23__device_stub__testInitPf, .Lfunc_end1-_Z23__device_stub__testInitPf
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $424, %rsp # imm = 0x1A8
.cfi_def_cfa_offset 480
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movabsq $4294967496, %r14 # imm = 0x1000000C8
xorps %xmm0, %xmm0
leaq 288(%rsp), %r15
movaps %xmm0, 112(%r15)
movaps %xmm0, 96(%r15)
movaps %xmm0, 80(%r15)
movaps %xmm0, 64(%r15)
movaps %xmm0, 48(%r15)
movaps %xmm0, 32(%r15)
movaps %xmm0, 16(%r15)
movaps %xmm0, (%r15)
leaq 160(%rsp), %r13
movaps %xmm0, 112(%r13)
movaps %xmm0, 96(%r13)
movaps %xmm0, 80(%r13)
movaps %xmm0, 64(%r13)
movaps %xmm0, 48(%r13)
movaps %xmm0, 32(%r13)
movaps %xmm0, 16(%r13)
movaps %xmm0, (%r13)
leaq 32(%rsp), %r12
movaps %xmm0, 112(%r12)
movaps %xmm0, 96(%r12)
movaps %xmm0, 80(%r12)
movaps %xmm0, 64(%r12)
movaps %xmm0, 48(%r12)
movaps %xmm0, 32(%r12)
movaps %xmm0, 16(%r12)
movaps %xmm0, (%r12)
movl $32000000, %edi # imm = 0x1E84800
callq malloc
movq %rax, %rbx
leaq 24(%rsp), %rbp
movl $32000000, %esi # imm = 0x1E84800
movq %rbp, %rdi
callq hipMalloc
movq (%rbp), %rdi
movl $32000000, %edx # imm = 0x1E84800
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
leaq 16(%rsp), %rbp
movl $128, %esi
movq %rbp, %rdi
callq hipMalloc
movq %rsp, %rdi
movl $128, %esi
callq hipMalloc
movq (%rbp), %rdi
movl $128, %edx
movq %r13, %rsi
movl $1, %ecx
callq hipMemcpy
movq %rsp, %rax
movq (%rax), %rdi
movl $128, %edx
movq %r15, %rsi
movl $1, %ecx
callq hipMemcpy
leaq 8(%rsp), %r15
movl $128, %esi
movq %r15, %rdi
callq hipMalloc
movq (%r15), %rdi
movl $128, %edx
movq %r12, %rsi
movl $1, %ecx
callq hipMemcpy
movq %r14, %rdi
movl $1, %esi
movq %r14, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_2
# %bb.1:
movq %rbx, %rdi
callq _Z23__device_stub__testInitPf
.LBB2_2:
addq $-198, %r14
movabsq $17179869188, %rdx # imm = 0x400000004
movq %r14, %rdi
movl $1, %esi
movl $4, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_4
# %bb.3:
movq 16(%rsp), %rdi
movq (%rsp), %rsi
movq 8(%rsp), %rdx
callq _Z20__device_stub__helloPiS_S_
.LBB2_4:
movq 24(%rsp), %rsi
movl $32000000, %edx # imm = 0x1E84800
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
movq 24(%rsp), %rdi
callq hipFree
movq (%rsp), %rsi
leaq 288(%rsp), %rdi
movl $128, %edx
movl $2, %ecx
callq hipMemcpy
movq 16(%rsp), %rsi
leaq 160(%rsp), %rdi
movl $128, %edx
movl $2, %ecx
callq hipMemcpy
movq (%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rsi
leaq 32(%rsp), %rdi
movl $128, %edx
movl $2, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
callq hipFree
movl $10, %edi
callq putchar@PLT
xorl %r14d, %r14d
.LBB2_5: # =>This Inner Loop Header: Depth=1
xorps %xmm0, %xmm0
cvtss2sd (%rbx,%r14,4), %xmm0
movl $.L.str.1, %edi
movl %r14d, %esi
movb $1, %al
callq printf
incq %r14
cmpq $32, %r14
jne .LBB2_5
# %bb.6:
movl $10, %edi
callq putchar@PLT
xorl %ebx, %ebx
.LBB2_7: # =>This Inner Loop Header: Depth=1
movl 160(%rsp,%rbx,4), %edx
movl $.L.str.2, %edi
movl %ebx, %esi
xorl %eax, %eax
callq printf
incq %rbx
cmpq $32, %rbx
jne .LBB2_7
# %bb.8:
movl $10, %edi
callq putchar@PLT
xorl %ebx, %ebx
.LBB2_9: # =>This Inner Loop Header: Depth=1
movl 288(%rsp,%rbx,4), %edx
movl $.L.str.2, %edi
movl %ebx, %esi
xorl %eax, %eax
callq printf
incq %rbx
cmpq $32, %rbx
jne .LBB2_9
# %bb.10:
movl $10, %edi
callq putchar@PLT
xorl %ebx, %ebx
.LBB2_11: # =>This Inner Loop Header: Depth=1
movl 32(%rsp,%rbx,4), %edx
movl $.L.str.2, %edi
movl %ebx, %esi
xorl %eax, %eax
callq printf
incq %rbx
cmpq $32, %rbx
jne .LBB2_11
# %bb.12:
xorl %eax, %eax
addq $424, %rsp # imm = 0x1A8
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
movq __hip_gpubin_handle(%rip), %rbx
testq %rbx, %rbx
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, %rbx
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z5helloPiS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8testInitPf, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z5helloPiS_S_,@object # @_Z5helloPiS_S_
.section .rodata,"a",@progbits
.globl _Z5helloPiS_S_
.p2align 3, 0x0
_Z5helloPiS_S_:
.quad _Z20__device_stub__helloPiS_S_
.size _Z5helloPiS_S_, 8
.type _Z8testInitPf,@object # @_Z8testInitPf
.globl _Z8testInitPf
.p2align 3, 0x0
_Z8testInitPf:
.quad _Z23__device_stub__testInitPf
.size _Z8testInitPf, 8
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "%d=%f "
.size .L.str.1, 7
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "%d=%d "
.size .L.str.2, 7
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z5helloPiS_S_"
.size .L__unnamed_1, 15
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z8testInitPf"
.size .L__unnamed_2, 14
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z20__device_stub__helloPiS_S_
.addrsig_sym _Z23__device_stub__testInitPf
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z5helloPiS_S_
.addrsig_sym _Z8testInitPf
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
```
| 5,010 | 5,629 |
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