uid
int64 2
114k
| input
stringlengths 101
58.4k
| output
stringlengths 422
72.4k
| input_tokens
int64 24
31.2k
| output_tokens
int64 182
31.2k
|
|---|---|---|---|---|
154 |
Convert the following CUDA device assembly code to AMD device assembly:
```cudaasm
code for sm_80
Function : _Z27update_veloc_elastic_kernelPfPKfif
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
MOV R1, c[0x0][0x28] ;
S2R R0, SR_CTAID.Y ;
S2R R3, SR_CTAID.X ;
S2R R5, SR_TID.X ;
IMAD R0, R0, c[0x0][0xc], R3 ;
IMAD R0, R0, c[0x0][0x0], R5 ;
ISETP.GE.AND P0, PT, R0, c[0x0][0x170], PT ;
@P0 EXIT ;
HFMA2.MMA R17, -RZ, RZ, 0, 2.384185791015625e-07 ;
ULDC.64 UR4, c[0x0][0x118] ;
IMAD.WIDE R2, R0, R17, c[0x0][0x160] ;
IMAD.WIDE R4, R0, R17, c[0x0][0x168] ;
LDG.E R7, [R2.64] ;
LDG.E R6, [R4.64] ;
IMAD.WIDE R8, R17, c[0x0][0x170], R4 ;
MOV R15, c[0x0][0x170] ;
FFMA R13, R6, c[0x0][0x174], R7 ;
IMAD.WIDE R6, R17, c[0x0][0x170], R2 ;
STG.E [R2.64], R13 ;
LDG.E R8, [R8.64] ;
LDG.E R11, [R6.64] ;
LEA R0, R15, R0, 0x1 ;
IMAD.WIDE R4, R0, R17, c[0x0][0x160] ;
FFMA R15, R8, c[0x0][0x174], R11 ;
IMAD.WIDE R10, R0, R17, c[0x0][0x168] ;
STG.E [R6.64], R15 ;
LDG.E R10, [R10.64] ;
LDG.E R17, [R4.64] ;
FFMA R17, R10, c[0x0][0x174], R17 ;
STG.E [R4.64], R17 ;
EXIT ;
BRA 0x1f0;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
```
|
```amdasm
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z27update_veloc_elastic_kernelPfPKfif ; -- Begin function _Z27update_veloc_elastic_kernelPfPKfif
.globl _Z27update_veloc_elastic_kernelPfPKfif
.p2align 8
.type _Z27update_veloc_elastic_kernelPfPKfif,@function
_Z27update_veloc_elastic_kernelPfPKfif: ; @_Z27update_veloc_elastic_kernelPfPKfif
; %bb.0:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x18
s_load_b32 s3, s[0:1], 0x24
s_load_b64 s[4:5], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_mul_i32 s2, s2, s15
s_and_b32 s3, s3, 0xffff
s_add_i32 s2, s2, s14
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s2, s3, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s4, v1
s_cbranch_execz .LBB0_2
; %bb.1:
s_load_b128 s[0:3], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_ashr_i32 s7, s4, 31
s_mov_b32 s6, s4
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_lshl_b64 s[6:7], s[6:7], 2
v_lshlrev_b64 v[2:3], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v4, vcc_lo, s0, v2
v_add_co_ci_u32_e32 v5, vcc_lo, s1, v3, vcc_lo
v_add_co_u32 v2, vcc_lo, s2, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_4)
v_add_co_u32 v6, vcc_lo, v4, s6
global_load_b32 v0, v[4:5], off
global_load_b32 v8, v[2:3], off
v_add_co_ci_u32_e32 v7, vcc_lo, s7, v5, vcc_lo
v_add_co_u32 v2, vcc_lo, v2, s6
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v3, vcc_lo
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v0, s5, v8
global_store_b32 v[4:5], v0, off
global_load_b32 v4, v[6:7], off
global_load_b32 v5, v[2:3], off
v_add3_u32 v0, s4, s4, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v1, 31, v0
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v4, s5, v5
global_store_b32 v[6:7], v4, off
global_load_b32 v4, v[2:3], off
global_load_b32 v0, v[0:1], off
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v4, s5, v0
global_store_b32 v[2:3], v4, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z27update_veloc_elastic_kernelPfPKfif
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z27update_veloc_elastic_kernelPfPKfif, .Lfunc_end0-_Z27update_veloc_elastic_kernelPfPKfif
; -- End function
.section .AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 332
; NumSgprs: 18
; NumVgprs: 9
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 9
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object ; @__hip_cuid_
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0 ; 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z27update_veloc_elastic_kernelPfPKfif
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z27update_veloc_elastic_kernelPfPKfif.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
```
| 692 | 3,149 |
155 |
Convert the following CUDA host assembly code to AMD host assembly:
```cudaasm
.file "tmpxft_0018e294_00000000-6_update_veloc_elastic_kernel.cudafe1.cpp"
.text
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z52__device_stub__Z27update_veloc_elastic_kernelPfPKfifPfPKfif
.type _Z52__device_stub__Z27update_veloc_elastic_kernelPfPKfifPfPKfif, @function
_Z52__device_stub__Z27update_veloc_elastic_kernelPfPKfifPfPKfif:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movss %xmm0, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z27update_veloc_elastic_kernelPfPKfif(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z52__device_stub__Z27update_veloc_elastic_kernelPfPKfifPfPKfif, .-_Z52__device_stub__Z27update_veloc_elastic_kernelPfPKfifPfPKfif
.globl _Z27update_veloc_elastic_kernelPfPKfif
.type _Z27update_veloc_elastic_kernelPfPKfif, @function
_Z27update_veloc_elastic_kernelPfPKfif:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z52__device_stub__Z27update_veloc_elastic_kernelPfPKfifPfPKfif
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z27update_veloc_elastic_kernelPfPKfif, .-_Z27update_veloc_elastic_kernelPfPKfif
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z27update_veloc_elastic_kernelPfPKfif"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z27update_veloc_elastic_kernelPfPKfif(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
```
|
```amdasm
.text
.file "update_veloc_elastic_kernel.hip"
.globl _Z42__device_stub__update_veloc_elastic_kernelPfPKfif # -- Begin function _Z42__device_stub__update_veloc_elastic_kernelPfPKfif
.type _Z42__device_stub__update_veloc_elastic_kernelPfPKfif,@function
_Z42__device_stub__update_veloc_elastic_kernelPfPKfif: # @_Z42__device_stub__update_veloc_elastic_kernelPfPKfif
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $112, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 40(%rsp), %rax
movq %rdi, (%rax)
leaq 32(%rsp), %rcx
movq %rsi, (%rcx)
leaq 12(%rsp), %rsi
movl %edx, (%rsi)
leaq 8(%rsp), %rdx
movss %xmm0, (%rdx)
leaq 80(%rsp), %rbx
movq %rax, (%rbx)
movq %rcx, 8(%rbx)
movq %rsi, 16(%rbx)
movq %rdx, 24(%rbx)
leaq 64(%rsp), %r14
leaq 48(%rsp), %r15
leaq 24(%rsp), %r12
leaq 16(%rsp), %r13
movq %r14, %rdi
movq %r15, %rsi
movq %r12, %rdx
movq %r13, %rcx
callq __hipPopCallConfiguration
movq (%r14), %rsi
movl 8(%r14), %edx
movq (%r15), %rcx
movl 8(%r15), %r8d
movl $_Z27update_veloc_elastic_kernelPfPKfif, %edi
movq %rbx, %r9
pushq (%r13)
.cfi_adjust_cfa_offset 8
pushq (%r12)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $128, %rsp
.cfi_adjust_cfa_offset -128
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z42__device_stub__update_veloc_elastic_kernelPfPKfif, .Lfunc_end0-_Z42__device_stub__update_veloc_elastic_kernelPfPKfif
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, %rdi
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z27update_veloc_elastic_kernelPfPKfif, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z27update_veloc_elastic_kernelPfPKfif,@object # @_Z27update_veloc_elastic_kernelPfPKfif
.section .rodata,"a",@progbits
.globl _Z27update_veloc_elastic_kernelPfPKfif
.p2align 3, 0x0
_Z27update_veloc_elastic_kernelPfPKfif:
.quad _Z42__device_stub__update_veloc_elastic_kernelPfPKfif
.size _Z27update_veloc_elastic_kernelPfPKfif, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z27update_veloc_elastic_kernelPfPKfif"
.size .L__unnamed_1, 39
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z42__device_stub__update_veloc_elastic_kernelPfPKfif
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z27update_veloc_elastic_kernelPfPKfif
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
```
| 1,971 | 2,158 |
156 |
Convert the following CUDA device assembly code to AMD device assembly:
```cudaasm
code for sm_80
Function : _Z15reduce_partialsPfi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
MOV R1, c[0x0][0x28] ;
MOV R4, c[0x0][0x168] ;
S2R R0, SR_CTAID.X ;
SHF.L.U32 R4, R4, 0x1, RZ ;
S2R R7, SR_TID.X ;
IABS R6, R4.reuse ;
IABS R9, R4 ;
I2F.RP R5, R6 ;
MUFU.RCP R5, R5 ;
IMAD R0, R0, c[0x0][0x0], R7 ;
ISETP.GE.AND P2, PT, R0, RZ, PT ;
IADD3 R2, R5, 0xffffffe, RZ ;
F2I.FTZ.U32.TRUNC.NTZ R3, R2 ;
HFMA2.MMA R2, -RZ, RZ, 0, 0 ;
IADD3 R8, RZ, -R3, RZ ;
MOV R7, R8 ;
IABS R8, R0 ;
IMAD R7, R7, R6, RZ ;
IMAD.HI.U32 R3, R3, R7, R2 ;
IADD3 R2, RZ, -R9, RZ ;
IMAD.HI.U32 R3, R3, R8, RZ ;
IMAD R3, R3, R2, R8 ;
ISETP.GT.U32.AND P0, PT, R6, R3, PT ;
@!P0 IADD3 R3, R3, -R6, RZ ;
ISETP.NE.AND P0, PT, R4, RZ, PT ;
ISETP.GT.U32.AND P1, PT, R6, R3, PT ;
@!P1 IADD3 R3, R3, -R6, RZ ;
@!P2 IADD3 R3, -R3, RZ, RZ ;
@!P0 LOP3.LUT R3, RZ, R4, RZ, 0x33, !PT ;
ISETP.NE.AND P0, PT, R3, RZ, PT ;
@P0 EXIT ;
ISETP.NE.AND P0, PT, RZ, c[0x0][0x168], PT ;
ULDC.64 UR4, c[0x0][0x118] ;
MOV R6, 0x3f800000 ;
@!P0 BRA 0x510 ;
HFMA2.MMA R3, -RZ, RZ, 0.771484375, 0.21533203125 ;
MOV R5, 0x34000000 ;
FFMA R2, RZ, -RZ, RZ ;
FFMA R5, R5, 8388608, RZ ;
FFMA R3, RZ, R3, 0.0032181653659790754318 ;
FFMA R6, RZ, 1.4426950216293334961, R5 ;
FFMA R4, RZ, R3, 0.018033718690276145935 ;
FADD R5, R5, -R6 ;
FMUL R3, R2, 0.5 ;
FFMA R4, RZ, R4, 0.12022458761930465698 ;
FFMA R2, RZ, 1.4426950216293334961, R5 ;
FMUL R4, RZ, R4 ;
FFMA R5, R3, 1.4426950216293334961, R2 ;
I2F R2, c[0x0][0x168] ;
FMUL R8, R4, 3 ;
FFMA R5, RZ, 1.9251366722983220825e-08, R5 ;
FFMA R5, R3, R8, R5 ;
MOV R8, 0x391fcb8e ;
FFMA R5, RZ, R4, R5 ;
FADD R3, R6, R5 ;
FSETP.GTU.AND P2, PT, |R2|, +INF , PT ;
FMUL R4, R2, R3.reuse ;
FADD R6, -R6, R3 ;
FRND R7, R4 ;
FFMA R3, R2, R3, -R4 ;
FSETP.GT.AND P0, PT, |R4|, 152, PT ;
FADD R6, R5, -R6 ;
FFMA R6, R2, R6, R3 ;
FADD R3, R4, -R7 ;
FSETP.GT.AND P1, PT, R7, RZ, PT ;
FADD R3, R3, R6 ;
SEL R5, RZ, 0x83000000, P1 ;
FSETP.GEU.AND P1, PT, R4, RZ, PT ;
FFMA R6, R3, R8, 0.0013391353422775864601 ;
IADD3 R7, R5, 0x7f000000, RZ ;
FFMA R8, R3.reuse, R6, 0.0096188392490148544312 ;
F2I.NTZ R6, R4 ;
FFMA R8, R3, R8, 0.055503588169813156128 ;
FFMA R8, R3, R8, 0.24022644758224487305 ;
FFMA R8, R3, R8, 0.69314718246459960938 ;
FFMA R8, R3, R8, 1 ;
LEA R5, R6, -R5, 0x17 ;
FMUL R8, R7, R8 ;
FSEL R6, RZ, +INF , !P1 ;
@!P0 FMUL R6, R5, R8 ;
@P2 FADD R6, R2, 2 ;
F2I.TRUNC.NTZ R5, R6 ;
MOV R3, 0x4 ;
IMAD.WIDE R2, R0, R3, c[0x0][0x160] ;
LDG.E R7, [R2.64] ;
IMAD.WIDE R4, R5, 0x4, R2 ;
LDG.E R4, [R4.64] ;
FADD R7, R4, R7 ;
STG.E [R2.64], R7 ;
EXIT ;
BRA 0x5a0;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
Function : _Z12square_arrayPfi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
MOV R1, c[0x0][0x28] ;
S2R R2, SR_CTAID.X ;
S2R R3, SR_TID.X ;
IMAD R2, R2, c[0x0][0x0], R3 ;
ISETP.GE.AND P0, PT, R2, c[0x0][0x168], PT ;
@P0 EXIT ;
HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ;
ULDC.64 UR4, c[0x0][0x118] ;
IMAD.WIDE R2, R2, R3, c[0x0][0x160] ;
LDG.E R0, [R2.64] ;
FMUL R5, R0, R0 ;
STG.E [R2.64], R5 ;
EXIT ;
BRA 0xd0;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
```
|
```amdasm
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z12square_arrayPfi ; -- Begin function _Z12square_arrayPfi
.globl _Z12square_arrayPfi
.p2align 8
.type _Z12square_arrayPfi,@function
_Z12square_arrayPfi: ; @_Z12square_arrayPfi
; %bb.0:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x1c
s_load_b32 s3, s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
; %bb.1:
s_load_b64 s[0:1], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_load_b32 v2, v[0:1], off
s_waitcnt vmcnt(0)
v_mul_f32_e32 v2, v2, v2
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z12square_arrayPfi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z12square_arrayPfi, .Lfunc_end0-_Z12square_arrayPfi
; -- End function
.section .AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 140
; NumSgprs: 18
; NumVgprs: 3
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 3
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
.text
.protected _Z15reduce_partialsPfi ; -- Begin function _Z15reduce_partialsPfi
.globl _Z15reduce_partialsPfi
.p2align 8
.type _Z15reduce_partialsPfi,@function
_Z15reduce_partialsPfi: ; @_Z15reduce_partialsPfi
; %bb.0:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x8
s_load_b32 s3, s[0:1], 0x1c
s_waitcnt lgkmcnt(0)
s_lshl_b32 s4, s2, 1
s_bfe_i32 s5, s2, 0x1001e
s_and_b32 s3, s3, 0xffff
s_add_i32 s4, s4, s5
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_xor_b32 s4, s4, s5
v_cvt_f32_u32_e32 v1, s4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v1, v1
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v1, 0x4f7ffffe, v1
v_cvt_u32_f32_e32 v3, v1
v_mad_u64_u32 v[1:2], null, s15, s3, v[0:1]
s_sub_i32 s3, 0, s4
s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
v_mul_lo_u32 v0, s3, v3
s_mov_b32 s3, exec_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v2, 31, v1
v_mul_hi_u32 v0, v3, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v4, v1, v2
v_xor_b32_e32 v4, v4, v2
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v0, v3, v0
v_mul_hi_u32 v0, v4, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v0, v0, s4
v_sub_nc_u32_e32 v0, v4, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v3, s4, v0
v_cmp_le_u32_e32 vcc_lo, s4, v0
v_cndmask_b32_e32 v0, v0, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v3, s4, v0
v_cmp_le_u32_e32 vcc_lo, s4, v0
v_cndmask_b32_e32 v0, v0, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_xor_b32_e32 v0, v0, v2
v_sub_nc_u32_e32 v0, v0, v2
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB1_2
; %bb.1:
s_cmp_eq_u32 s2, 0
s_load_b64 s[0:1], s[0:1], 0x0
s_cselect_b32 s3, -1, 0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cndmask_b32_e64 v0, 2.0, 1.0, s3
s_mov_b32 s3, 0x3e76c4e1
v_frexp_mant_f32_e32 v3, v0
v_frexp_exp_i32_f32_e32 v0, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_cmp_gt_f32_e32 vcc_lo, 0x3f2aaaab, v3
v_cndmask_b32_e64 v4, 0, 1, vcc_lo
v_subrev_co_ci_u32_e32 v0, vcc_lo, 0, v0, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ldexp_f32 v3, v3, v4
v_cvt_f32_i32_e32 v0, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_f32_e32 v6, -1.0, v3
v_add_f32_e32 v4, 1.0, v3
v_rcp_f32_e32 v5, v4
s_waitcnt_depctr 0xfff
v_dual_mul_f32 v7, v6, v5 :: v_dual_add_f32 v8, -1.0, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_f32_e32 v9, v4, v7
v_sub_f32_e32 v3, v3, v8
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v4, v7, v4, -v9
v_fmac_f32_e32 v4, v7, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v3, v9, v4
v_dual_sub_f32 v8, v6, v3 :: v_dual_sub_f32 v9, v3, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_f32_e32 v4, v9, v4
v_sub_f32_e32 v6, v6, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_f32_e32 v3, v6, v3
v_add_f32_e32 v3, v4, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v3, v8, v3
v_mul_f32_e32 v3, v5, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v4, v7, v3
v_mul_f32_e32 v6, v4, v4
v_sub_f32_e32 v5, v4, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_sub_f32_e32 v3, v3, v5
v_fma_f32 v5, v4, v4, -v6
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v7, v3, v3
v_fmac_f32_e32 v5, v4, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v7, v6, v5
v_fmaak_f32 v8, s3, v7, 0x3e91f4c4
v_sub_f32_e32 v6, v7, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_fmaak_f32 v8, v7, v8, 0x3ecccdef :: v_dual_sub_f32 v5, v5, v6
v_mul_f32_e32 v9, v7, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v6, v7, v8, -v9
v_dual_fmac_f32 v6, v5, v8 :: v_dual_mul_f32 v11, v4, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f32_e32 v8, v9, v6
v_fma_f32 v12, v7, v4, -v11
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_dual_sub_f32 v9, v8, v9 :: v_dual_fmac_f32 v12, v7, v3
v_add_f32_e32 v10, 0x3f2aaaaa, v8
v_ldexp_f32 v3, v3, 1
v_sub_f32_e32 v6, v6, v9
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_fmac_f32_e32 v12, v5, v4
v_ldexp_f32 v4, v4, 1
v_add_f32_e32 v6, 0x31739010, v6
v_add_f32_e32 v9, 0xbf2aaaaa, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_f32_e32 v8, v8, v9
v_add_f32_e32 v6, v6, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v5, v10, v6
v_dual_add_f32 v7, v11, v12 :: v_dual_sub_f32 v8, v10, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_mul_f32_e32 v9, v7, v5
v_sub_f32_e32 v10, v7, v11
v_add_f32_e32 v6, v6, v8
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_fma_f32 v8, v7, v5, -v9
v_sub_f32_e32 v10, v12, v10
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v8, v7, v6
v_fmac_f32_e32 v8, v10, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v5, v9, v8
v_sub_f32_e32 v7, v5, v9
v_mul_f32_e32 v9, 0x3f317218, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_f32_e32 v7, v8, v7
v_fma_f32 v8, 0x3f317218, v0, -v9
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_add_f32 v3, v3, v7 :: v_dual_add_f32 v6, v4, v5
v_sub_f32_e32 v4, v6, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_f32_e32 v4, v5, v4
v_add_f32_e32 v3, v3, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_add_f32 v5, v6, v3 :: v_dual_fmamk_f32 v0, v0, 0xb102e308, v8
v_sub_f32_e32 v6, v5, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_sub_f32 v3, v3, v6 :: v_dual_add_f32 v4, v9, v0
v_add_f32_e32 v7, v4, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_sub_f32 v9, v4, v9 :: v_dual_sub_f32 v8, v7, v4
v_sub_f32_e32 v10, v7, v8
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_sub_f32 v5, v5, v8 :: v_dual_sub_f32 v0, v0, v9
v_add_f32_e32 v6, v0, v3
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_f32_e32 v4, v4, v10
v_add_f32_e32 v4, v5, v4
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_f32_e32 v5, v6, v0
v_dual_add_f32 v4, v6, v4 :: v_dual_sub_f32 v3, v3, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v8, v7, v4
v_dual_sub_f32 v6, v6, v5 :: v_dual_sub_f32 v5, v8, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_f32_e32 v0, v0, v6
v_dual_add_f32 v0, v3, v0 :: v_dual_sub_f32 v3, v4, v5
v_cvt_f32_i32_e32 v4, s2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v0, v0, v3
v_add_f32_e32 v3, v8, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
v_sub_f32_e32 v5, v3, v8
v_mul_f32_e32 v6, v3, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_f32_e32 v0, v0, v5
v_fma_f32 v3, v4, v3, -v6
v_cmp_class_f32_e64 vcc_lo, v6, 0x204
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v3, v4, v0
v_add_f32_e32 v0, v6, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v4, v0, v6, vcc_lo
v_sub_f32_e32 v0, v0, v6
v_cmp_eq_f32_e32 vcc_lo, 0x42b17218, v4
v_cndmask_b32_e64 v5, 0, 0x37000000, vcc_lo
v_cmp_neq_f32_e64 vcc_lo, 0x7f800000, |v4|
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_f32_e32 v7, v4, v5
v_mul_f32_e32 v8, 0x3fb8aa3b, v7
v_sub_f32_e32 v0, v3, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_fma_f32 v9, 0x3fb8aa3b, v7, -v8
v_rndne_f32_e32 v10, v8
v_cndmask_b32_e32 v0, 0, v0, vcc_lo
v_cmp_ngt_f32_e32 vcc_lo, 0xc2ce8ed0, v7
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_dual_fmamk_f32 v9, v7, 0x32a5705f, v9 :: v_dual_sub_f32 v8, v8, v10
v_cvt_i32_f32_e32 v6, v10
v_add_f32_e32 v0, v5, v0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v8, v8, v9
v_exp_f32_e32 v8, v8
s_waitcnt_depctr 0xfff
v_ldexp_f32 v3, v8, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v3, 0, v3, vcc_lo
v_cmp_nlt_f32_e32 vcc_lo, 0x42b17218, v7
v_cndmask_b32_e32 v3, 0x7f800000, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_fma_f32 v0, v3, v0, v3
v_cmp_eq_f32_e32 vcc_lo, 0x7f800000, v3
v_cndmask_b32_e32 v0, v0, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cvt_i32_f32_e64 v3, |v0|
v_lshlrev_b64 v[0:1], 2, v[1:2]
v_ashrrev_i32_e32 v4, 31, v3
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[3:4]
v_add_co_u32 v2, vcc_lo, v0, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, v1, v3, vcc_lo
s_clause 0x1
global_load_b32 v4, v[0:1], off
global_load_b32 v2, v[2:3], off
s_waitcnt vmcnt(0)
v_add_f32_e32 v2, v4, v2
global_store_b32 v[0:1], v2, off
.LBB1_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z15reduce_partialsPfi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 13
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z15reduce_partialsPfi, .Lfunc_end1-_Z15reduce_partialsPfi
; -- End function
.section .AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1252
; NumSgprs: 18
; NumVgprs: 13
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 13
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object ; @__hip_cuid_
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0 ; 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z12square_arrayPfi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z12square_arrayPfi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z15reduce_partialsPfi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z15reduce_partialsPfi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 13
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
```
| 2,068 | 9,511 |
157 |
Convert the following CUDA host assembly code to AMD host assembly:
```cudaasm
.file "tmpxft_00095671_00000000-6_hel.cudafe1.cpp"
.text
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z33__device_stub__Z12square_arrayPfiPfi
.type _Z33__device_stub__Z12square_arrayPfiPfi, @function
_Z33__device_stub__Z12square_arrayPfiPfi:
.LFB2084:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z12square_arrayPfi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z33__device_stub__Z12square_arrayPfiPfi, .-_Z33__device_stub__Z12square_arrayPfiPfi
.globl _Z12square_arrayPfi
.type _Z12square_arrayPfi, @function
_Z12square_arrayPfi:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z12square_arrayPfiPfi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z12square_arrayPfi, .-_Z12square_arrayPfi
.globl _Z36__device_stub__Z15reduce_partialsPfiPfi
.type _Z36__device_stub__Z15reduce_partialsPfiPfi, @function
_Z36__device_stub__Z15reduce_partialsPfiPfi:
.LFB2086:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z15reduce_partialsPfi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2086:
.size _Z36__device_stub__Z15reduce_partialsPfiPfi, .-_Z36__device_stub__Z15reduce_partialsPfiPfi
.globl _Z15reduce_partialsPfi
.type _Z15reduce_partialsPfi, @function
_Z15reduce_partialsPfi:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z36__device_stub__Z15reduce_partialsPfiPfi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _Z15reduce_partialsPfi, .-_Z15reduce_partialsPfi
.globl _Z12reduce_arrayPf
.type _Z12reduce_arrayPf, @function
_Z12reduce_arrayPf:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $32, %rsp
.cfi_def_cfa_offset 48
movq %rdi, %rbx
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $0, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L22
.L19:
addq $32, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L22:
.cfi_restore_state
movl $0, %esi
movq %rbx, %rdi
call _Z36__device_stub__Z15reduce_partialsPfiPfi
jmp .L19
.cfi_endproc
.LFE2057:
.size _Z12reduce_arrayPf, .-_Z12reduce_arrayPf
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%d %f\n"
.text
.globl main
.type main, @function
main:
.LFB2059:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $16, %rsp
.cfi_def_cfa_offset 48
movq %fs:40, %rax
movq %rax, 8(%rsp)
xorl %eax, %eax
movl $64, %edi
call malloc@PLT
movq %rax, %rbp
movq %rsp, %rdi
movl $64, %esi
call cudaMalloc@PLT
movl $0, %eax
.L24:
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movss %xmm0, 0(%rbp,%rax,4)
addq $1, %rax
cmpq $16, %rax
jne .L24
movl $1, %ecx
movl $64, %edx
movq %rbp, %rsi
movq (%rsp), %rdi
call cudaMemcpy@PLT
movq (%rsp), %rdi
call _Z12reduce_arrayPf
movl $2, %ecx
movl $64, %edx
movq (%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
movl $0, %ebx
leaq .LC0(%rip), %r12
.L25:
pxor %xmm0, %xmm0
cvtss2sd 0(%rbp,%rbx,4), %xmm0
movl %ebx, %edx
movq %r12, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq $16, %rbx
jne .L25
movq %rbp, %rdi
call free@PLT
movq (%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rax
subq %fs:40, %rax
jne .L30
movl $0, %eax
addq $16, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L30:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size main, .-main
.section .rodata.str1.1
.LC1:
.string "_Z15reduce_partialsPfi"
.LC2:
.string "_Z12square_arrayPfi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2089:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z15reduce_partialsPfi(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z12square_arrayPfi(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2089:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
```
|
```amdasm
.text
.file "hel.hip"
.globl _Z27__device_stub__square_arrayPfi # -- Begin function _Z27__device_stub__square_arrayPfi
.type _Z27__device_stub__square_arrayPfi,@function
_Z27__device_stub__square_arrayPfi: # @_Z27__device_stub__square_arrayPfi
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $80, %rsp
.cfi_def_cfa_offset 128
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 24(%rsp), %rax
movq %rdi, (%rax)
leaq 4(%rsp), %rcx
movl %esi, (%rcx)
leaq 64(%rsp), %rbx
movq %rax, (%rbx)
movq %rcx, 8(%rbx)
leaq 48(%rsp), %r14
leaq 32(%rsp), %r15
leaq 16(%rsp), %r12
leaq 8(%rsp), %r13
movq %r14, %rdi
movq %r15, %rsi
movq %r12, %rdx
movq %r13, %rcx
callq __hipPopCallConfiguration
movq (%r14), %rsi
movl 8(%r14), %edx
movq (%r15), %rcx
movl 8(%r15), %r8d
movl $_Z12square_arrayPfi, %edi
movq %rbx, %r9
pushq (%r13)
.cfi_adjust_cfa_offset 8
pushq (%r12)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $96, %rsp
.cfi_adjust_cfa_offset -96
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z27__device_stub__square_arrayPfi, .Lfunc_end0-_Z27__device_stub__square_arrayPfi
.cfi_endproc
# -- End function
.globl _Z30__device_stub__reduce_partialsPfi # -- Begin function _Z30__device_stub__reduce_partialsPfi
.type _Z30__device_stub__reduce_partialsPfi,@function
_Z30__device_stub__reduce_partialsPfi: # @_Z30__device_stub__reduce_partialsPfi
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $80, %rsp
.cfi_def_cfa_offset 128
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 24(%rsp), %rax
movq %rdi, (%rax)
leaq 4(%rsp), %rcx
movl %esi, (%rcx)
leaq 64(%rsp), %rbx
movq %rax, (%rbx)
movq %rcx, 8(%rbx)
leaq 48(%rsp), %r14
leaq 32(%rsp), %r15
leaq 16(%rsp), %r12
leaq 8(%rsp), %r13
movq %r14, %rdi
movq %r15, %rsi
movq %r12, %rdx
movq %r13, %rcx
callq __hipPopCallConfiguration
movq (%r14), %rsi
movl 8(%r14), %edx
movq (%r15), %rcx
movl 8(%r15), %r8d
movl $_Z15reduce_partialsPfi, %edi
movq %rbx, %r9
pushq (%r13)
.cfi_adjust_cfa_offset 8
pushq (%r12)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $96, %rsp
.cfi_adjust_cfa_offset -96
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z30__device_stub__reduce_partialsPfi, .Lfunc_end1-_Z30__device_stub__reduce_partialsPfi
.cfi_endproc
# -- End function
.globl _Z12reduce_arrayPf # -- Begin function _Z12reduce_arrayPf
.type _Z12reduce_arrayPf,@function
_Z12reduce_arrayPf: # @_Z12reduce_arrayPf
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
movq %rdi, %rbx
movabsq $4294967296, %rdi # imm = 0x100000000
leaq 1(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
je .LBB2_2
# %bb.1:
popq %rbx
.cfi_def_cfa_offset 8
retq
.LBB2_2:
.cfi_def_cfa_offset 16
movq %rbx, %rdi
xorl %esi, %esi
popq %rbx
.cfi_def_cfa_offset 8
jmp _Z30__device_stub__reduce_partialsPfi # TAILCALL
.Lfunc_end2:
.size _Z12reduce_arrayPf, .Lfunc_end2-_Z12reduce_arrayPf
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
pushq %rax
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movl $64, %edi
callq malloc
movq %rax, %rbx
movq %rsp, %rdi
movl $64, %esi
callq hipMalloc
xorl %eax, %eax
.LBB3_1: # =>This Inner Loop Header: Depth=1
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movss %xmm0, (%rbx,%rax,4)
incq %rax
cmpq $16, %rax
jne .LBB3_1
# %bb.2:
movq (%rsp), %rdi
movl $64, %edx
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq (%rsp), %rdi
callq _Z12reduce_arrayPf
movq (%rsp), %rsi
movl $64, %edx
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
xorl %r14d, %r14d
.LBB3_3: # =>This Inner Loop Header: Depth=1
xorps %xmm0, %xmm0
cvtss2sd (%rbx,%r14,4), %xmm0
movl $.L.str, %edi
movl %r14d, %esi
movb $1, %al
callq printf
incq %r14
cmpq $16, %r14
jne .LBB3_3
# %bb.4:
movq %rbx, %rdi
callq free
movq (%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
movq __hip_gpubin_handle(%rip), %rbx
testq %rbx, %rbx
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, %rbx
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12square_arrayPfi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15reduce_partialsPfi, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z12square_arrayPfi,@object # @_Z12square_arrayPfi
.section .rodata,"a",@progbits
.globl _Z12square_arrayPfi
.p2align 3, 0x0
_Z12square_arrayPfi:
.quad _Z27__device_stub__square_arrayPfi
.size _Z12square_arrayPfi, 8
.type _Z15reduce_partialsPfi,@object # @_Z15reduce_partialsPfi
.globl _Z15reduce_partialsPfi
.p2align 3, 0x0
_Z15reduce_partialsPfi:
.quad _Z30__device_stub__reduce_partialsPfi
.size _Z15reduce_partialsPfi, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%d %f\n"
.size .L.str, 7
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z12square_arrayPfi"
.size .L__unnamed_1, 20
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z15reduce_partialsPfi"
.size .L__unnamed_2, 23
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z27__device_stub__square_arrayPfi
.addrsig_sym _Z30__device_stub__reduce_partialsPfi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z12square_arrayPfi
.addrsig_sym _Z15reduce_partialsPfi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
```
| 3,966 | 4,118 |
158 |
Convert the following CUDA device assembly code to AMD device assembly:
```cudaasm
code for sm_80
```
|
```amdasm
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object ; @__hip_cuid_
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0 ; 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
```
| 24 | 306 |
159 |
Convert the following CUDA host assembly code to AMD host assembly:
```cudaasm
.file "tmpxft_000662f0_00000000-6_cpp11Features.cudafe1.cpp"
.text
.section .text._ZN1SaSERKS_,"axG",@progbits,_ZN1SaSERKS_,comdat
.align 2
.weak _ZN1SaSERKS_
.type _ZN1SaSERKS_, @function
_ZN1SaSERKS_:
.LFB2171:
.cfi_startproc
endbr64
movq %rdi, %rax
ret
.cfi_endproc
.LFE2171:
.size _ZN1SaSERKS_, .-_ZN1SaSERKS_
.text
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2033:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2033:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.align 2
.globl _ZN1SC2Ev
.type _ZN1SC2Ev, @function
_ZN1SC2Ev:
.LFB2028:
.cfi_startproc
endbr64
leaq 16+_ZTV1S(%rip), %rax
movq %rax, (%rdi)
ret
.cfi_endproc
.LFE2028:
.size _ZN1SC2Ev, .-_ZN1SC2Ev
.globl _ZN1SC1Ev
.set _ZN1SC1Ev,_ZN1SC2Ev
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2056:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2056:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.weak _ZTS1S
.section .rodata._ZTS1S,"aG",@progbits,_ZTS1S,comdat
.type _ZTS1S, @object
.size _ZTS1S, 3
_ZTS1S:
.string "1S"
.weak _ZTI1S
.section .data.rel.ro._ZTI1S,"awG",@progbits,_ZTI1S,comdat
.align 8
.type _ZTI1S, @object
.size _ZTI1S, 16
_ZTI1S:
.quad _ZTVN10__cxxabiv117__class_type_infoE+16
.quad _ZTS1S
.weak _ZTV1S
.section .data.rel.ro.local._ZTV1S,"awG",@progbits,_ZTV1S,comdat
.align 8
.type _ZTV1S, @object
.size _ZTV1S, 24
_ZTV1S:
.quad 0
.quad _ZTI1S
.quad _ZN1SaSERKS_
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
```
|
```amdasm
.text
.file "cpp11Features.hip"
.globl _ZN1SC2Ev # -- Begin function _ZN1SC2Ev
.p2align 1, 0x90
.type _ZN1SC2Ev,@function
_ZN1SC2Ev: # @_ZN1SC2Ev
.cfi_startproc
# %bb.0:
movq $_ZTV1S+16, (%rdi)
retq
.Lfunc_end0:
.size _ZN1SC2Ev, .Lfunc_end0-_ZN1SC2Ev
.cfi_endproc
# -- End function
.section .text._ZN1SaSERKS_,"axG",@progbits,_ZN1SaSERKS_,comdat
.weak _ZN1SaSERKS_ # -- Begin function _ZN1SaSERKS_
.p2align 1, 0x90
.type _ZN1SaSERKS_,@function
_ZN1SaSERKS_: # @_ZN1SaSERKS_
.cfi_startproc
# %bb.0:
movq %rdi, %rax
retq
.Lfunc_end1:
.size _ZN1SaSERKS_, .Lfunc_end1-_ZN1SaSERKS_
.cfi_endproc
# -- End function
.type _ZTV1S,@object # @_ZTV1S
.section .rodata._ZTV1S,"aG",@progbits,_ZTV1S,comdat
.weak _ZTV1S
.p2align 3, 0x0
_ZTV1S:
.quad 0
.quad _ZTI1S
.quad _ZN1SaSERKS_
.size _ZTV1S, 24
.type _ZTS1S,@object # @_ZTS1S
.section .rodata._ZTS1S,"aG",@progbits,_ZTS1S,comdat
.weak _ZTS1S
_ZTS1S:
.asciz "1S"
.size _ZTS1S, 3
.type _ZTI1S,@object # @_ZTI1S
.section .rodata._ZTI1S,"aG",@progbits,_ZTI1S,comdat
.weak _ZTI1S
.p2align 3, 0x0
_ZTI1S:
.quad _ZTVN10__cxxabiv117__class_type_infoE+16
.quad _ZTS1S
.size _ZTI1S, 16
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.globl _ZN1SC1Ev
.type _ZN1SC1Ev,@function
.set _ZN1SC1Ev, _ZN1SC2Ev
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _ZTVN10__cxxabiv117__class_type_infoE
.addrsig_sym _ZTS1S
.addrsig_sym _ZTI1S
.addrsig_sym __hip_cuid_
```
| 1,291 | 862 |
160 |
Convert the following CUDA device assembly code to AMD device assembly:
```cudaasm
code for sm_80
Function : _Z20ker_gkylCartFieldAbsjjPd
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
MOV R1, c[0x0][0x28] ;
S2R R0, SR_CTAID.X ;
ULDC.64 UR4, c[0x0][0x160] ;
UIADD3 UR4, UR5, UR4, URZ ;
S2R R3, SR_TID.X ;
IMAD R0, R0, c[0x0][0x0], R3 ;
IADD3 R0, R0, c[0x0][0x160], RZ ;
ISETP.GE.U32.AND P0, PT, R0, UR4, PT ;
@P0 EXIT ;
ULDC.64 UR6, c[0x0][0x118] ;
HFMA2.MMA R3, -RZ, RZ, 0, 4.76837158203125e-07 ;
IMAD.WIDE R2, R0, R3, c[0x0][0x168] ;
LDG.E.64 R4, [R2.64] ;
MOV R7, c[0x0][0x0] ;
IMAD R0, R7, c[0x0][0xc], R0 ;
ISETP.GE.U32.AND P0, PT, R0, UR4, PT ;
DADD R4, -RZ, |R4| ;
STG.E.64 [R2.64], R4 ;
@!P0 BRA 0xa0 ;
EXIT ;
BRA 0x140;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
```
|
```amdasm
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z20ker_gkylCartFieldAbsjjPd ; -- Begin function _Z20ker_gkylCartFieldAbsjjPd
.globl _Z20ker_gkylCartFieldAbsjjPd
.p2align 8
.type _Z20ker_gkylCartFieldAbsjjPd,@function
_Z20ker_gkylCartFieldAbsjjPd: ; @_Z20ker_gkylCartFieldAbsjjPd
; %bb.0:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x1c
s_load_b64 s[6:7], s[0:1], 0x0
s_add_u32 s2, s0, 16
s_addc_u32 s3, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s5, s4, 0xffff
s_add_i32 s4, s7, s6
s_mul_i32 s15, s15, s5
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add3_u32 v0, s15, s6, v0
s_mov_b32 s6, exec_lo
v_cmpx_gt_u32_e64 s4, v0
s_cbranch_execz .LBB0_3
; %bb.1: ; %.lr.ph
s_load_b32 s2, s[2:3], 0x0
s_load_b64 s[0:1], s[0:1], 0x8
s_mov_b32 s3, 0
s_waitcnt lgkmcnt(0)
s_mul_i32 s2, s2, s5
.LBB0_2: ; =>This Inner Loop Header: Depth=1
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[1:2], 3, v[0:1]
v_add_nc_u32_e32 v0, s2, v0
v_add_co_u32 v1, vcc_lo, s0, v1
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
v_cmp_le_u32_e32 vcc_lo, s4, v0
global_load_b64 v[3:4], v[1:2], off
s_or_b32 s3, vcc_lo, s3
s_waitcnt vmcnt(0)
v_and_b32_e32 v4, 0x7fffffff, v4
global_store_b64 v[1:2], v[3:4], off
s_and_not1_b32 exec_lo, exec_lo, s3
s_cbranch_execnz .LBB0_2
.LBB0_3: ; %Flow17
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z20ker_gkylCartFieldAbsjjPd
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z20ker_gkylCartFieldAbsjjPd, .Lfunc_end0-_Z20ker_gkylCartFieldAbsjjPd
; -- End function
.section .AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 196
; NumSgprs: 18
; NumVgprs: 5
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 5
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object ; @__hip_cuid_
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0 ; 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z20ker_gkylCartFieldAbsjjPd
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z20ker_gkylCartFieldAbsjjPd.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
```
| 456 | 2,680 |
161 |
Convert the following CUDA host assembly code to AMD host assembly:
```cudaasm
.file "tmpxft_000922c4_00000000-6_ker_gkylCartFieldAbs.cudafe1.cpp"
.text
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z42__device_stub__Z20ker_gkylCartFieldAbsjjPdjjPd
.type _Z42__device_stub__Z20ker_gkylCartFieldAbsjjPdjjPd, @function
_Z42__device_stub__Z20ker_gkylCartFieldAbsjjPdjjPd:
.LFB2051:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 12(%rsp)
movl %esi, 8(%rsp)
movq %rdx, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 8(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rax
movq %rax, 96(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z20ker_gkylCartFieldAbsjjPd(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z42__device_stub__Z20ker_gkylCartFieldAbsjjPdjjPd, .-_Z42__device_stub__Z20ker_gkylCartFieldAbsjjPdjjPd
.globl _Z20ker_gkylCartFieldAbsjjPd
.type _Z20ker_gkylCartFieldAbsjjPd, @function
_Z20ker_gkylCartFieldAbsjjPd:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z42__device_stub__Z20ker_gkylCartFieldAbsjjPdjjPd
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z20ker_gkylCartFieldAbsjjPd, .-_Z20ker_gkylCartFieldAbsjjPd
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z20ker_gkylCartFieldAbsjjPd"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z20ker_gkylCartFieldAbsjjPd(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
```
|
```amdasm
.text
.file "ker_gkylCartFieldAbs.hip"
.globl _Z35__device_stub__ker_gkylCartFieldAbsjjPd # -- Begin function _Z35__device_stub__ker_gkylCartFieldAbsjjPd
.type _Z35__device_stub__ker_gkylCartFieldAbsjjPd,@function
_Z35__device_stub__ker_gkylCartFieldAbsjjPd: # @_Z35__device_stub__ker_gkylCartFieldAbsjjPd
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $96, %rsp
.cfi_def_cfa_offset 144
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 4(%rsp), %rax
movl %edi, (%rax)
movq %rsp, %rcx
movl %esi, (%rcx)
leaq 24(%rsp), %rsi
movq %rdx, (%rsi)
leaq 64(%rsp), %rbx
movq %rax, (%rbx)
movq %rcx, 8(%rbx)
movq %rsi, 16(%rbx)
leaq 48(%rsp), %r14
leaq 32(%rsp), %r15
leaq 16(%rsp), %r12
leaq 8(%rsp), %r13
movq %r14, %rdi
movq %r15, %rsi
movq %r12, %rdx
movq %r13, %rcx
callq __hipPopCallConfiguration
movq (%r14), %rsi
movl 8(%r14), %edx
movq (%r15), %rcx
movl 8(%r15), %r8d
movl $_Z20ker_gkylCartFieldAbsjjPd, %edi
movq %rbx, %r9
pushq (%r13)
.cfi_adjust_cfa_offset 8
pushq (%r12)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $112, %rsp
.cfi_adjust_cfa_offset -112
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z35__device_stub__ker_gkylCartFieldAbsjjPd, .Lfunc_end0-_Z35__device_stub__ker_gkylCartFieldAbsjjPd
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, %rdi
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z20ker_gkylCartFieldAbsjjPd, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z20ker_gkylCartFieldAbsjjPd,@object # @_Z20ker_gkylCartFieldAbsjjPd
.section .rodata,"a",@progbits
.globl _Z20ker_gkylCartFieldAbsjjPd
.p2align 3, 0x0
_Z20ker_gkylCartFieldAbsjjPd:
.quad _Z35__device_stub__ker_gkylCartFieldAbsjjPd
.size _Z20ker_gkylCartFieldAbsjjPd, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z20ker_gkylCartFieldAbsjjPd"
.size .L__unnamed_1, 29
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z35__device_stub__ker_gkylCartFieldAbsjjPd
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z20ker_gkylCartFieldAbsjjPd
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
```
| 1,894 | 2,097 |
162 |
Convert the following CUDA device assembly code to AMD device assembly:
```cudaasm
code for sm_80
Function : _Z25GaussianEliminationSharediPfPKfS1_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ;
S2R R0, SR_CTAID.X ;
IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x160] ;
ULDC.64 UR6, c[0x0][0x118] ;
ISETP.GE.AND P1, PT, R4, 0x1, PT ;
@!P1 BRA 0xca0 ;
LOP3.LUT R2, R4.reuse, 0x3, RZ, 0xc0, !PT ;
IMAD.MOV.U32 R5, RZ, RZ, RZ ;
IADD3 R4, R4, -0x1, RZ ;
IADD3 R3, -R2, c[0x0][0x160], RZ ;
ISETP.GE.U32.AND P3, PT, R4, 0x3, PT ;
IMAD.MOV.U32 R6, RZ, RZ, RZ ;
@!P3 BRA 0x460 ;
ISETP.GT.AND P0, PT, R3, RZ, PT ;
IMAD.MOV.U32 R6, RZ, RZ, RZ ;
IMAD.MOV.U32 R7, RZ, RZ, R3 ;
@!P0 BRA 0x3c0 ;
ISETP.GT.AND P2, PT, R7, 0xc, PT ;
PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ;
@!P2 BRA 0x2b0 ;
PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ;
IMAD R8, R5, 0x9, R6 ;
IADD3 R7, R7, -0x10, RZ ;
IADD3 R6, R6, 0x10, RZ ;
IMAD.SHL.U32 R8, R8, 0x4, RZ ;
ISETP.GT.AND P2, PT, R7, 0xc, PT ;
STS [R8], RZ ;
STS [R8+0x4], RZ ;
STS [R8+0x8], RZ ;
STS [R8+0xc], RZ ;
STS [R8+0x10], RZ ;
STS [R8+0x14], RZ ;
STS [R8+0x18], RZ ;
STS [R8+0x1c], RZ ;
STS [R8+0x20], RZ ;
STS [R8+0x24], RZ ;
STS [R8+0x28], RZ ;
STS [R8+0x2c], RZ ;
STS [R8+0x30], RZ ;
STS [R8+0x34], RZ ;
STS [R8+0x38], RZ ;
STS [R8+0x3c], RZ ;
@P2 BRA 0x150 ;
ISETP.GT.AND P2, PT, R7, 0x4, PT ;
@!P2 BRA 0x3a0 ;
IMAD R8, R5, 0x9, R6 ;
PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ;
IADD3 R7, R7, -0x8, RZ ;
IMAD.SHL.U32 R8, R8, 0x4, RZ ;
IADD3 R6, R6, 0x8, RZ ;
STS [R8], RZ ;
STS [R8+0x4], RZ ;
STS [R8+0x8], RZ ;
STS [R8+0xc], RZ ;
STS [R8+0x10], RZ ;
STS [R8+0x14], RZ ;
STS [R8+0x18], RZ ;
STS [R8+0x1c], RZ ;
ISETP.NE.OR P0, PT, R7, RZ, P0 ;
@!P0 BRA 0x460 ;
IMAD R8, R5, 0x9, R6 ;
IADD3 R7, R7, -0x4, RZ ;
IADD3 R6, R6, 0x4, RZ ;
IMAD.SHL.U32 R8, R8, 0x4, RZ ;
ISETP.NE.AND P0, PT, R7, RZ, PT ;
STS [R8], RZ ;
STS [R8+0x4], RZ ;
STS [R8+0x8], RZ ;
STS [R8+0xc], RZ ;
@P0 BRA 0x3c0 ;
ISETP.NE.AND P2, PT, R2, RZ, PT ;
@!P2 BRA 0x500 ;
IMAD R6, R5, 0x9, R6 ;
ISETP.NE.AND P0, PT, R2, 0x1, PT ;
IMAD.SHL.U32 R6, R6, 0x4, RZ ;
STS [R6], RZ ;
@!P0 BRA 0x500 ;
ISETP.NE.AND P0, PT, R2, 0x2, PT ;
STS [R6+0x4], RZ ;
@P0 STS [R6+0x8], RZ ;
IADD3 R5, R5, 0x1, RZ ;
ISETP.GE.AND P0, PT, R5, c[0x0][0x160], PT ;
@!P0 BRA 0xa0 ;
IMAD.MOV.U32 R5, RZ, RZ, RZ ;
@!P3 BRA 0xbe0 ;
ISETP.GT.AND P0, PT, R3, RZ, PT ;
IMAD.MOV.U32 R5, RZ, RZ, RZ ;
@!P0 BRA 0xad0 ;
ISETP.GT.AND P3, PT, R3, 0xc, PT ;
PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ;
@!P3 BRA 0x8e0 ;
PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ;
IADD3 R7, R5.reuse, 0x4, RZ ;
IMAD.MOV.U32 R10, RZ, RZ, 0x4 ;
IADD3 R9, R5.reuse, 0x8, RZ ;
IMAD R16, R0.reuse, c[0x0][0x160], R5 ;
IADD3 R11, R5, 0xc, RZ ;
IMAD R7, R0.reuse, c[0x0][0x160], R7 ;
IMAD R6, R0.reuse, c[0x0][0x160], R9 ;
IMAD R11, R0, c[0x0][0x160], R11 ;
IMAD.WIDE R8, R7, R10, c[0x0][0x170] ;
IMAD.WIDE R16, R16, R10.reuse, c[0x0][0x170] ;
LDG.E R15, [R8.64] ;
IMAD.WIDE R6, R6, R10.reuse, c[0x0][0x170] ;
LDG.E R12, [R16.64] ;
IMAD.WIDE R10, R11, R10, c[0x0][0x170] ;
LDG.E R4, [R16.64+0x4] ;
LDG.E R13, [R16.64+0x8] ;
LDG.E R14, [R16.64+0xc] ;
LDG.E R18, [R8.64+0x4] ;
LDG.E R19, [R8.64+0x8] ;
LDG.E R20, [R8.64+0xc] ;
LDG.E R22, [R6.64] ;
LDG.E R24, [R6.64+0x4] ;
LDG.E R26, [R6.64+0x8] ;
LDG.E R16, [R6.64+0xc] ;
LDG.E R28, [R10.64] ;
LDG.E R17, [R10.64+0x4] ;
LDG.E R21, [R10.64+0x8] ;
LDG.E R23, [R10.64+0xc] ;
IMAD R25, R5, 0x9, R5 ;
IMAD.SHL.U32 R9, R25, 0x4, RZ ;
IADD3 R3, R3, -0x10, RZ ;
ISETP.GT.AND P3, PT, R3, 0xc, PT ;
IADD3 R5, R5, 0x10, RZ ;
STS [R9+0xa0], R15 ;
STS [R9], R12 ;
STS [R9+0x28], R4 ;
STS [R9+0x50], R13 ;
STS [R9+0x78], R14 ;
STS [R9+0xc8], R18 ;
STS [R9+0xf0], R19 ;
STS [R9+0x118], R20 ;
STS [R9+0x140], R22 ;
STS [R9+0x168], R24 ;
STS [R9+0x190], R26 ;
STS [R9+0x1b8], R16 ;
STS [R9+0x1e0], R28 ;
STS [R9+0x208], R17 ;
STS [R9+0x230], R21 ;
STS [R9+0x258], R23 ;
@P3 BRA 0x5c0 ;
ISETP.GT.AND P3, PT, R3, 0x4, PT ;
@!P3 BRA 0xab0 ;
IADD3 R7, R5, 0x4, RZ ;
IMAD.MOV.U32 R9, RZ, RZ, 0x4 ;
IMAD R6, R0.reuse, c[0x0][0x160], R5 ;
IMAD R8, R0, c[0x0][0x160], R7 ;
IMAD.WIDE R6, R6, R9, c[0x0][0x170] ;
IMAD.WIDE R8, R8, R9, c[0x0][0x170] ;
LDG.E R4, [R6.64] ;
LDG.E R10, [R6.64+0x4] ;
LDG.E R12, [R6.64+0x8] ;
LDG.E R14, [R6.64+0xc] ;
LDG.E R16, [R8.64] ;
LDG.E R18, [R8.64+0x4] ;
LDG.E R20, [R8.64+0x8] ;
LDG.E R22, [R8.64+0xc] ;
IMAD R11, R5, 0x9, R5 ;
PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ;
IADD3 R3, R3, -0x8, RZ ;
IMAD.SHL.U32 R11, R11, 0x4, RZ ;
IADD3 R5, R5, 0x8, RZ ;
STS [R11], R4 ;
STS [R11+0x28], R10 ;
STS [R11+0x50], R12 ;
STS [R11+0x78], R14 ;
STS [R11+0xa0], R16 ;
STS [R11+0xc8], R18 ;
STS [R11+0xf0], R20 ;
STS [R11+0x118], R22 ;
ISETP.NE.OR P0, PT, R3, RZ, P0 ;
@!P0 BRA 0xbe0 ;
IMAD.MOV.U32 R7, RZ, RZ, 0x4 ;
IMAD R6, R0, c[0x0][0x160], R5 ;
IMAD.WIDE R6, R6, R7, c[0x0][0x170] ;
LDG.E R4, [R6.64] ;
LDG.E R8, [R6.64+0x4] ;
LDG.E R9, [R6.64+0x8] ;
LDG.E R10, [R6.64+0xc] ;
IMAD R11, R5, 0x9, R5 ;
IADD3 R3, R3, -0x4, RZ ;
IADD3 R5, R5, 0x4, RZ ;
IMAD.SHL.U32 R11, R11, 0x4, RZ ;
ISETP.NE.AND P0, PT, R3, RZ, PT ;
STS [R11], R4 ;
STS [R11+0x28], R8 ;
STS [R11+0x50], R9 ;
STS [R11+0x78], R10 ;
@P0 BRA 0xad0 ;
@!P2 BRA 0xca0 ;
IMAD.MOV.U32 R7, RZ, RZ, 0x4 ;
IMAD R6, R0, c[0x0][0x160], R5 ;
IMAD.WIDE R6, R6, R7, c[0x0][0x170] ;
LDG.E R6, [R6.64] ;
IMAD R3, R5.reuse, 0x9, R5 ;
IADD3 R2, R2, -0x1, RZ ;
IADD3 R5, R5, 0x1, RZ ;
IMAD.SHL.U32 R3, R3, 0x4, RZ ;
ISETP.NE.AND P0, PT, R2, RZ, PT ;
STS [R3], R6 ;
@P0 BRA 0xbf0 ;
IMAD.MOV.U32 R6, RZ, RZ, c[0x0][0x160] ;
ISETP.GE.AND P0, PT, R6, 0x2, PT ;
@!P0 BRA 0x18c0 ;
IADD3 R2, R6.reuse, -0x2, RZ ;
IMAD.MOV.U32 R7, RZ, RZ, RZ ;
IADD3 R9, R6, -0x1, RZ ;
ISETP.GE.U32.AND P0, PT, R2, 0x3, PT ;
LOP3.LUT R8, R9, 0x3, RZ, 0xc0, !PT ;
@!P0 BRA 0x17c0 ;
IMAD.IADD R9, R9, 0x1, -R8 ;
IMAD.MOV.U32 R7, RZ, RZ, RZ ;
ISETP.GT.AND P0, PT, R9, RZ, PT ;
@!P0 BRA 0x1620 ;
ISETP.GT.AND P2, PT, R9, 0xc, PT ;
PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ;
@!P2 BRA 0x1310 ;
PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ;
IMAD R2, R0, c[0x0][0x160], R7 ;
IADD3 R3, R7, 0x4, RZ ;
IMAD.MOV.U32 R13, RZ, RZ, 0x4 ;
IMAD.SHL.U32 R2, R2, 0x2, RZ ;
IMAD R3, R0, c[0x0][0x160], R3 ;
IMAD.WIDE R4, R2, R13, c[0x0][0x178] ;
IMAD.SHL.U32 R2, R3, 0x2, RZ ;
LDG.E R25, [R4.64+0x4] ;
IMAD.WIDE R2, R2, R13, c[0x0][0x178] ;
LDG.E R23, [R4.64+0x8] ;
LDG.E R17, [R4.64+0xc] ;
LDG.E R15, [R4.64+0x10] ;
LDG.E R19, [R4.64+0x14] ;
LDG.E R21, [R4.64+0x18] ;
LDG.E R20, [R4.64+0x1c] ;
LDG.E R26, [R4.64+0x20] ;
LDG.E R28, [R2.64+0x4] ;
LDG.E R12, [R2.64+0x8] ;
LDG.E R16, [R2.64+0x10] ;
IADD3 R11, R7.reuse, 0x8, RZ ;
IMAD R14, R7, 0x9, R7 ;
LDG.E R18, [R2.64+0xc] ;
IMAD R10, R0, c[0x0][0x160], R11 ;
SHF.L.U32 R11, R14, 0x2, RZ ;
LDG.E R22, [R2.64+0x14] ;
IMAD.SHL.U32 R27, R10, 0x2, RZ ;
LDG.E R10, [R2.64+0x18] ;
LDG.E R14, [R2.64+0x1c] ;
LDG.E R24, [R2.64+0x20] ;
IADD3 R3, R7, 0xc, RZ ;
IMAD R3, R0, c[0x0][0x160], R3 ;
IMAD.SHL.U32 R2, R3, 0x2, RZ ;
IMAD.WIDE R4, R27, R13, c[0x0][0x178] ;
IMAD.WIDE R2, R2, R13, c[0x0][0x178] ;
LDG.E R27, [R4.64+0x4] ;
LDG.E R29, [R4.64+0x8] ;
LDG.E R13, [R2.64+0x10] ;
STS [R11+0x4], R25 ;
STS [R11+0x24], R23 ;
STS [R11+0x2c], R17 ;
STS [R11+0x4c], R15 ;
STS [R11+0x54], R19 ;
STS [R11+0x74], R21 ;
LDG.E R15, [R4.64+0xc] ;
LDG.E R17, [R4.64+0x10] ;
LDG.E R19, [R4.64+0x14] ;
LDG.E R25, [R4.64+0x18] ;
LDG.E R23, [R4.64+0x1c] ;
LDG.E R21, [R4.64+0x20] ;
STS [R11+0x7c], R20 ;
STS [R11+0x9c], R26 ;
STS [R11+0xa4], R28 ;
STS [R11+0xc4], R12 ;
STS [R11+0xec], R16 ;
LDG.E R4, [R2.64+0x4] ;
LDG.E R5, [R2.64+0x8] ;
LDG.E R20, [R2.64+0xc] ;
LDG.E R26, [R2.64+0x14] ;
LDG.E R28, [R2.64+0x18] ;
LDG.E R12, [R2.64+0x1c] ;
LDG.E R16, [R2.64+0x20] ;
IADD3 R9, R9, -0x10, RZ ;
STS [R11+0xcc], R18 ;
STS [R11+0xf4], R22 ;
STS [R11+0x114], R10 ;
STS [R11+0x11c], R14 ;
STS [R11+0x13c], R24 ;
STS [R11+0x144], R27 ;
STS [R11+0x164], R29 ;
STS [R11+0x22c], R13 ;
ISETP.GT.AND P2, PT, R9, 0xc, PT ;
IADD3 R7, R7, 0x10, RZ ;
STS [R11+0x16c], R15 ;
STS [R11+0x18c], R17 ;
STS [R11+0x194], R19 ;
STS [R11+0x1b4], R25 ;
STS [R11+0x1bc], R23 ;
STS [R11+0x1dc], R21 ;
STS [R11+0x1e4], R4 ;
STS [R11+0x204], R5 ;
STS [R11+0x20c], R20 ;
STS [R11+0x234], R26 ;
STS [R11+0x254], R28 ;
STS [R11+0x25c], R12 ;
STS [R11+0x27c], R16 ;
@P2 BRA 0xdb0 ;
ISETP.GT.AND P2, PT, R9, 0x4, PT ;
@!P2 BRA 0x1600 ;
IADD3 R3, R7, 0x4, RZ ;
IMAD R2, R0.reuse, c[0x0][0x160], R7 ;
IMAD.MOV.U32 R10, RZ, RZ, 0x4 ;
IMAD R3, R0, c[0x0][0x160], R3 ;
IMAD.SHL.U32 R2, R2, 0x2, RZ ;
IMAD.SHL.U32 R3, R3, 0x2, RZ ;
IMAD.WIDE R4, R2, R10, c[0x0][0x178] ;
IMAD.WIDE R2, R3, R10, c[0x0][0x178] ;
LDG.E R12, [R4.64+0x8] ;
LDG.E R10, [R4.64+0x4] ;
LDG.E R14, [R4.64+0xc] ;
LDG.E R16, [R4.64+0x10] ;
LDG.E R18, [R4.64+0x14] ;
LDG.E R20, [R4.64+0x18] ;
LDG.E R22, [R4.64+0x1c] ;
LDG.E R24, [R4.64+0x20] ;
LDG.E R26, [R2.64+0x4] ;
LDG.E R28, [R2.64+0x8] ;
LDG.E R13, [R2.64+0xc] ;
LDG.E R15, [R2.64+0x10] ;
LDG.E R17, [R2.64+0x14] ;
LDG.E R19, [R2.64+0x18] ;
LDG.E R21, [R2.64+0x1c] ;
LDG.E R23, [R2.64+0x20] ;
IMAD R11, R7, 0x9, R7 ;
IMAD.SHL.U32 R11, R11, 0x4, RZ ;
PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ;
IADD3 R9, R9, -0x8, RZ ;
IADD3 R7, R7, 0x8, RZ ;
STS [R11+0x24], R12 ;
STS [R11+0x4], R10 ;
STS [R11+0x2c], R14 ;
STS [R11+0x4c], R16 ;
STS [R11+0x54], R18 ;
STS [R11+0x74], R20 ;
STS [R11+0x7c], R22 ;
STS [R11+0x9c], R24 ;
STS [R11+0xa4], R26 ;
STS [R11+0xc4], R28 ;
STS [R11+0xcc], R13 ;
STS [R11+0xec], R15 ;
STS [R11+0xf4], R17 ;
STS [R11+0x114], R19 ;
STS [R11+0x11c], R21 ;
STS [R11+0x13c], R23 ;
ISETP.NE.OR P0, PT, R9, RZ, P0 ;
@!P0 BRA 0x17c0 ;
IMAD R2, R0, c[0x0][0x160], R7 ;
IMAD.MOV.U32 R3, RZ, RZ, 0x4 ;
IMAD.SHL.U32 R2, R2, 0x2, RZ ;
IMAD.WIDE R2, R2, R3, c[0x0][0x178] ;
LDG.E R4, [R2.64+0x4] ;
LDG.E R5, [R2.64+0x8] ;
LDG.E R10, [R2.64+0xc] ;
LDG.E R11, [R2.64+0x10] ;
LDG.E R12, [R2.64+0x14] ;
LDG.E R13, [R2.64+0x18] ;
LDG.E R14, [R2.64+0x1c] ;
LDG.E R15, [R2.64+0x20] ;
IMAD R16, R7, 0x9, R7 ;
IADD3 R9, R9, -0x4, RZ ;
IADD3 R7, R7, 0x4, RZ ;
IMAD.SHL.U32 R16, R16, 0x4, RZ ;
ISETP.NE.AND P0, PT, R9, RZ, PT ;
STS [R16+0x4], R4 ;
STS [R16+0x24], R5 ;
STS [R16+0x2c], R10 ;
STS [R16+0x4c], R11 ;
STS [R16+0x54], R12 ;
STS [R16+0x74], R13 ;
STS [R16+0x7c], R14 ;
STS [R16+0x9c], R15 ;
@P0 BRA 0x1620 ;
ISETP.NE.AND P0, PT, R8, RZ, PT ;
@!P0 BRA 0x18c0 ;
IMAD R2, R0, c[0x0][0x160], R7 ;
IMAD.MOV.U32 R3, RZ, RZ, 0x4 ;
LEA R2, R2, 0x1, 0x1 ;
IMAD.WIDE R2, R2, R3, c[0x0][0x178] ;
LDG.E R4, [R2.64] ;
LDG.E R5, [R2.64+0x4] ;
IMAD R9, R7.reuse, 0x9, R7 ;
IADD3 R8, R8, -0x1, RZ ;
IADD3 R7, R7, 0x1, RZ ;
IMAD.SHL.U32 R9, R9, 0x4, RZ ;
ISETP.NE.AND P0, PT, R8, RZ, PT ;
STS [R9+0x4], R4 ;
STS [R9+0x24], R5 ;
@P0 BRA 0x17e0 ;
PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ;
@!P1 BRA 0x2c20 ;
ISETP.GT.AND P1, PT, R6, 0x1, PT ;
PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ;
@!P1 BRA 0x2c20 ;
LOP3.LUT R2, R6.reuse, 0x3, RZ, 0xc0, !PT ;
IMAD.MOV.U32 R5, RZ, RZ, RZ ;
IADD3 R3, R6, -0x1, RZ ;
IMAD.MOV.U32 R4, RZ, RZ, 0x1 ;
IADD3 R6, -R2, c[0x0][0x160], RZ ;
IMAD R12, R0, c[0x0][0x160], R5 ;
IMAD.MOV.U32 R13, RZ, RZ, 0x4 ;
IMAD R8, R5, 0x24, RZ ;
IMAD.MOV.U32 R7, RZ, RZ, R4 ;
IMAD.WIDE R12, R12, R13, c[0x0][0x180] ;
IMAD R9, R5, 0x4, R8 ;
LDS R17, [R9] ;
IMAD R10, R7, 0x24, RZ ;
IMAD R18, R5, 0x4, R10 ;
LDS R18, [R18] ;
MUFU.RCP R14, R17 ;
FCHK P0, R18, R17 ;
FFMA R11, -R17, R14, 1 ;
FFMA R15, R14, R11, R14 ;
IMAD.MOV.U32 R11, RZ, RZ, RZ ;
FFMA R14, R18, R15, RZ ;
FFMA R16, -R17, R14, R18 ;
FFMA R14, R15, R16, R14 ;
@!P0 BRA 0x1ac0 ;
MOV R14, 0x1ab0 ;
CALL.REL.NOINC 0x4740 ;
IMAD.MOV.U32 R14, RZ, RZ, R18 ;
ISETP.GE.U32.AND P0, PT, R3, 0x3, PT ;
F2F.F64.F32 R14, R14 ;
@!P0 BRA 0x2900 ;
ISETP.GT.AND P0, PT, R6, RZ, PT ;
IMAD.MOV.U32 R11, RZ, RZ, RZ ;
IMAD.MOV.U32 R20, RZ, RZ, R6 ;
@!P0 BRA 0x26e0 ;
ISETP.GT.AND P1, PT, R20, 0xc, PT ;
PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ;
@!P1 BRA 0x22d0 ;
PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ;
LEA R21, R11.reuse, R10, 0x2 ;
IMAD R22, R11.reuse, 0x4, R8 ;
IADD3 R20, R20, -0x10, RZ ;
IADD3 R11, R11, 0x10, RZ ;
LDS R23, [R21] ;
ISETP.GT.AND P1, PT, R20, 0xc, PT ;
LDS R28, [R22] ;
LDS R29, [R21+0x4] ;
F2F.F64.F32 R18, R23 ;
F2F.F64.F32 R16, R28 ;
LDS R23, [R21+0x8] ;
DFMA R24, -R14, R16, R18 ;
F2F.F64.F32 R18, R29 ;
F2F.F32.F64 R24, R24 ;
LDS R29, [R21+0xc] ;
STS [R21], R24 ;
LDS R16, [R22+0x4] ;
F2F.F64.F32 R16, R16 ;
DFMA R26, -R14, R16, R18 ;
F2F.F64.F32 R18, R23 ;
F2F.F32.F64 R26, R26 ;
LDS R23, [R21+0x10] ;
STS [R21+0x4], R26 ;
LDS R28, [R22+0x8] ;
F2F.F64.F32 R16, R28 ;
DFMA R24, -R14, R16, R18 ;
F2F.F64.F32 R18, R29 ;
F2F.F32.F64 R24, R24 ;
LDS R29, [R21+0x14] ;
STS [R21+0x8], R24 ;
LDS R16, [R22+0xc] ;
F2F.F64.F32 R16, R16 ;
DFMA R26, -R14, R16, R18 ;
F2F.F64.F32 R18, R23 ;
F2F.F32.F64 R26, R26 ;
LDS R23, [R21+0x18] ;
STS [R21+0xc], R26 ;
LDS R28, [R22+0x10] ;
F2F.F64.F32 R16, R28 ;
DFMA R24, -R14, R16, R18 ;
F2F.F64.F32 R18, R29 ;
F2F.F32.F64 R24, R24 ;
LDS R29, [R21+0x1c] ;
STS [R21+0x10], R24 ;
LDS R16, [R22+0x14] ;
F2F.F64.F32 R16, R16 ;
DFMA R26, -R14, R16, R18 ;
F2F.F64.F32 R18, R23 ;
F2F.F32.F64 R26, R26 ;
LDS R23, [R21+0x20] ;
STS [R21+0x14], R26 ;
LDS R28, [R22+0x18] ;
F2F.F64.F32 R16, R28 ;
DFMA R24, -R14, R16, R18 ;
F2F.F64.F32 R18, R29 ;
F2F.F32.F64 R24, R24 ;
LDS R29, [R21+0x24] ;
STS [R21+0x18], R24 ;
LDS R16, [R22+0x1c] ;
F2F.F64.F32 R16, R16 ;
DFMA R26, -R14, R16, R18 ;
F2F.F64.F32 R18, R23 ;
F2F.F32.F64 R26, R26 ;
LDS R23, [R21+0x28] ;
STS [R21+0x1c], R26 ;
LDS R28, [R22+0x20] ;
F2F.F64.F32 R16, R28 ;
DFMA R24, -R14, R16, R18 ;
F2F.F64.F32 R18, R29 ;
F2F.F32.F64 R24, R24 ;
LDS R29, [R21+0x2c] ;
STS [R21+0x20], R24 ;
LDS R16, [R22+0x24] ;
F2F.F64.F32 R16, R16 ;
DFMA R26, -R14, R16, R18 ;
F2F.F64.F32 R18, R23 ;
F2F.F32.F64 R26, R26 ;
LDS R23, [R21+0x30] ;
STS [R21+0x24], R26 ;
LDS R28, [R22+0x28] ;
F2F.F64.F32 R16, R28 ;
DFMA R24, -R14, R16, R18 ;
F2F.F64.F32 R18, R29 ;
F2F.F32.F64 R24, R24 ;
LDS R29, [R21+0x34] ;
STS [R21+0x28], R24 ;
LDS R16, [R22+0x2c] ;
F2F.F64.F32 R16, R16 ;
DFMA R26, -R14, R16, R18 ;
F2F.F64.F32 R18, R23 ;
F2F.F32.F64 R26, R26 ;
LDS R23, [R21+0x38] ;
STS [R21+0x2c], R26 ;
LDS R28, [R22+0x30] ;
F2F.F64.F32 R16, R28 ;
DFMA R24, -R14, R16, R18 ;
F2F.F64.F32 R18, R29 ;
F2F.F32.F64 R24, R24 ;
STS [R21+0x30], R24 ;
LDS R16, [R22+0x34] ;
F2F.F64.F32 R16, R16 ;
DFMA R26, -R14, R16, R18 ;
F2F.F64.F32 R18, R23 ;
F2F.F32.F64 R26, R26 ;
STS [R21+0x34], R26 ;
LDS R28, [R22+0x38] ;
F2F.F64.F32 R16, R28 ;
DFMA R24, -R14, R16, R18 ;
LDS R18, [R21+0x3c] ;
F2F.F32.F64 R24, R24 ;
STS [R21+0x38], R24 ;
LDS R29, [R22+0x3c] ;
F2F.F64.F32 R18, R18 ;
F2F.F64.F32 R16, R29 ;
DFMA R16, -R14, R16, R18 ;
F2F.F32.F64 R16, R16 ;
STS [R21+0x3c], R16 ;
@P1 BRA 0x1b70 ;
ISETP.GT.AND P1, PT, R20, 0x4, PT ;
@!P1 BRA 0x26c0 ;
IMAD R21, R11.reuse, 0x4, R10 ;
PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ;
IMAD R22, R11.reuse, 0x4, R8 ;
IADD3 R20, R20, -0x8, RZ ;
LDS R23, [R21] ;
IADD3 R11, R11, 0x8, RZ ;
LDS R28, [R22] ;
LDS R29, [R21+0x4] ;
F2F.F64.F32 R18, R23 ;
F2F.F64.F32 R16, R28 ;
LDS R23, [R21+0x8] ;
DFMA R24, -R14, R16, R18 ;
F2F.F64.F32 R18, R29 ;
F2F.F32.F64 R24, R24 ;
LDS R29, [R21+0xc] ;
STS [R21], R24 ;
LDS R16, [R22+0x4] ;
F2F.F64.F32 R16, R16 ;
DFMA R26, -R14, R16, R18 ;
F2F.F64.F32 R18, R23 ;
F2F.F32.F64 R26, R26 ;
LDS R23, [R21+0x10] ;
STS [R21+0x4], R26 ;
LDS R28, [R22+0x8] ;
F2F.F64.F32 R16, R28 ;
DFMA R24, -R14, R16, R18 ;
F2F.F64.F32 R18, R29 ;
F2F.F32.F64 R24, R24 ;
LDS R29, [R21+0x14] ;
STS [R21+0x8], R24 ;
LDS R16, [R22+0xc] ;
F2F.F64.F32 R16, R16 ;
DFMA R26, -R14, R16, R18 ;
F2F.F64.F32 R18, R23 ;
F2F.F32.F64 R26, R26 ;
LDS R23, [R21+0x18] ;
STS [R21+0xc], R26 ;
LDS R28, [R22+0x10] ;
F2F.F64.F32 R16, R28 ;
DFMA R24, -R14, R16, R18 ;
F2F.F64.F32 R16, R29 ;
F2F.F32.F64 R24, R24 ;
STS [R21+0x10], R24 ;
LDS R18, [R22+0x14] ;
F2F.F64.F32 R18, R18 ;
DFMA R26, -R14, R18, R16 ;
F2F.F64.F32 R16, R23 ;
F2F.F32.F64 R26, R26 ;
STS [R21+0x14], R26 ;
LDS R28, [R22+0x18] ;
F2F.F64.F32 R18, R28 ;
DFMA R24, -R14, R18, R16 ;
LDS R19, [R21+0x1c] ;
F2F.F32.F64 R24, R24 ;
STS [R21+0x18], R24 ;
LDS R29, [R22+0x1c] ;
F2F.F64.F32 R18, R19 ;
F2F.F64.F32 R16, R29 ;
DFMA R16, -R14, R16, R18 ;
F2F.F32.F64 R16, R16 ;
STS [R21+0x1c], R16 ;
ISETP.NE.OR P0, PT, R20, RZ, P0 ;
@!P0 BRA 0x2900 ;
IMAD R21, R11.reuse, 0x4, R10 ;
IADD3 R20, R20, -0x4, RZ ;
IMAD R22, R11.reuse, 0x4, R8 ;
IADD3 R11, R11, 0x4, RZ ;
LDS R23, [R21] ;
ISETP.NE.AND P0, PT, R20, RZ, PT ;
LDS R28, [R22] ;
LDS R29, [R21+0x4] ;
F2F.F64.F32 R18, R23 ;
F2F.F64.F32 R16, R28 ;
LDS R23, [R21+0x8] ;
DFMA R24, -R14, R16, R18 ;
F2F.F64.F32 R18, R29 ;
F2F.F32.F64 R24, R24 ;
STS [R21], R24 ;
LDS R16, [R22+0x4] ;
F2F.F64.F32 R16, R16 ;
DFMA R26, -R14, R16, R18 ;
F2F.F64.F32 R18, R23 ;
F2F.F32.F64 R26, R26 ;
STS [R21+0x4], R26 ;
LDS R28, [R22+0x8] ;
F2F.F64.F32 R16, R28 ;
DFMA R24, -R14, R16, R18 ;
LDS R18, [R21+0xc] ;
F2F.F32.F64 R24, R24 ;
STS [R21+0x8], R24 ;
LDS R29, [R22+0xc] ;
F2F.F64.F32 R18, R18 ;
F2F.F64.F32 R16, R29 ;
DFMA R16, -R14, R16, R18 ;
F2F.F32.F64 R16, R16 ;
STS [R21+0xc], R16 ;
@P0 BRA 0x26e0 ;
ISETP.NE.AND P0, PT, R2, RZ, PT ;
@!P0 BRA 0x2ad0 ;
IMAD R18, R11.reuse, 0x4, R10 ;
ISETP.NE.AND P0, PT, R2, 0x1, PT ;
IMAD R19, R11, 0x4, R8 ;
LDS R20, [R18] ;
LDS R16, [R19] ;
F2F.F64.F32 R10, R20 ;
F2F.F64.F32 R16, R16 ;
DFMA R10, -R14, R16, R10 ;
F2F.F32.F64 R11, R10 ;
STS [R18], R11 ;
@!P0 BRA 0x2ad0 ;
LDS R20, [R18+0x4] ;
ISETP.NE.AND P0, PT, R2, 0x2, PT ;
LDS R16, [R19+0x4] ;
F2F.F64.F32 R10, R20 ;
F2F.F64.F32 R16, R16 ;
DFMA R10, -R14, R16, R10 ;
F2F.F32.F64 R11, R10 ;
STS [R18+0x4], R11 ;
@!P0 BRA 0x2ad0 ;
LDS R19, [R19+0x8] ;
LDS R16, [R18+0x8] ;
F2F.F64.F32 R10, R19 ;
F2F.F64.F32 R16, R16 ;
DFMA R10, -R14, R10, R16 ;
F2F.F32.F64 R11, R10 ;
STS [R18+0x8], R11 ;
IMAD.MOV.U32 R11, RZ, RZ, 0x4 ;
LDG.E R20, [R12.64] ;
IMAD R10, R0, c[0x0][0x160], R7 ;
IMAD.WIDE R10, R10, R11, c[0x0][0x180] ;
LDG.E R18, [R10.64] ;
IADD3 R7, R7, 0x1, RZ ;
ISETP.GE.AND P0, PT, R7, c[0x0][0x160], PT ;
F2F.F64.F32 R16, R20 ;
F2F.F64.F32 R18, R18 ;
DFMA R16, -R14, R16, R18 ;
F2F.F32.F64 R17, R16 ;
STG.E [R10.64], R17 ;
@P0 CALL.REL.NOINC 0x2bb0 ;
BRA 0x19c0 ;
IADD3 R7, R4, 0x1, RZ ;
IMAD.MOV.U32 R5, RZ, RZ, R4 ;
ISETP.GE.AND P0, PT, R7, c[0x0][0x160], PT ;
IMAD.MOV.U32 R4, RZ, RZ, R7 ;
@P0 CALL.REL.NOINC 0x2c10 ;
BRA 0x1960 ;
PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ;
BAR.SYNC.DEFER_BLOCKING 0x0 ;
@!P0 EXIT ;
IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x160] ;
IMAD.MOV.U32 R2, RZ, RZ, RZ ;
IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x160] ;
IMAD R4, R0, R5, 0x3 ;
IADD3 R6, R3.reuse, -0x1, RZ ;
IMAD R7, R3, 0x9, R3.reuse ;
CS2R R18, SRZ ;
IMAD.MOV.U32 R5, RZ, RZ, R3 ;
ISETP.GE.U32.AND P0, PT, R6, c[0x0][0x160], PT ;
IMAD.SHL.U32 R7, R7, 0x4, RZ ;
IMAD.MOV.U32 R3, RZ, RZ, R6 ;
@P0 BRA 0x3f70 ;
IADD3 R6, R2.reuse, 0x1, RZ ;
IMAD.MOV.U32 R9, RZ, RZ, R3 ;
ISETP.GE.U32.AND P1, PT, R2, 0x3, PT ;
CS2R R18, SRZ ;
LOP3.LUT P0, R8, R6, 0x3, RZ, 0xc0, !PT ;
@!P0 BRA 0x2f20 ;
IMAD.MOV.U32 R15, RZ, RZ, 0x4 ;
LDS R6, [R7+-0x28] ;
IMAD R10, R0, c[0x0][0x160], R3 ;
IMAD.WIDE.U32 R10, R10, R15, c[0x0][0x168] ;
LDG.E R11, [R10.64] ;
ISETP.NE.AND P0, PT, R8, 0x1, PT ;
IMAD.MOV.U32 R9, RZ, RZ, R5 ;
FMUL R6, R6, R11 ;
F2F.F64.F32 R18, R6 ;
DADD R18, RZ, R18 ;
@!P0 BRA 0x2f20 ;
ISETP.NE.AND P0, PT, R8, 0x2, PT ;
IMAD R10, R0, c[0x0][0x160], R5 ;
IADD3 R9, R5, 0x1, RZ ;
LDS R13, [R7+-0x24] ;
IMAD.WIDE.U32 R10, R10, R15, c[0x0][0x168] ;
LDG.E R10, [R10.64] ;
@P0 IMAD R14, R0, c[0x0][0x160], R9 ;
@P0 LDS R17, [R7+-0x20] ;
@P0 IMAD.WIDE.U32 R14, R14, R15, c[0x0][0x168] ;
@P0 LDG.E R14, [R14.64] ;
@P0 IADD3 R9, R5, 0x2, RZ ;
FMUL R13, R10, R13 ;
F2F.F64.F32 R12, R13 ;
@P0 FMUL R17, R14, R17 ;
@P0 F2F.F64.F32 R16, R17 ;
DADD R18, R18, R12 ;
@P0 DADD R18, R18, R16 ;
@!P1 BRA 0x3f70 ;
ISETP.GE.U32.AND P1, PT, R9, c[0x0][0x160], PT ;
IMAD R6, R5, 0x9, R9.reuse ;
PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ;
IMAD.IADD R8, R4, 0x1, R9 ;
LEA R6, R6, 0xffffffdc, 0x2 ;
@!P1 BRA 0x3190 ;
HFMA2.MMA R17, -RZ, RZ, 0, 2.384185791015625e-07 ;
IMAD R14, R0, c[0x0][0x160], R9 ;
IADD3 R10, R8.reuse, -0x2, RZ ;
LDS R20, [R6] ;
IADD3 R12, R8, -0x1, RZ ;
LDS R21, [R6+0x4] ;
IMAD.WIDE.U32 R14, R14, R17.reuse, c[0x0][0x168] ;
LDS R23, [R6+0x8] ;
IMAD.WIDE.U32 R10, R10, R17.reuse, c[0x0][0x168] ;
LDS R25, [R6+0xc] ;
LDG.E R15, [R14.64] ;
IMAD.WIDE.U32 R12, R12, R17, c[0x0][0x168] ;
LDG.E R10, [R10.64] ;
IMAD.WIDE.U32 R16, R8, R17, c[0x0][0x168] ;
LDG.E R12, [R12.64] ;
LDG.E R16, [R16.64] ;
PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ;
IADD3 R9, R9, 0x4, RZ ;
IADD3 R6, R6, 0x10, RZ ;
IADD3 R8, R8, 0x4, RZ ;
FMUL R20, R15, R20 ;
F2F.F64.F32 R14, R20 ;
FMUL R21, R10, R21 ;
FMUL R12, R12, R23 ;
F2F.F64.F32 R10, R21 ;
FMUL R16, R16, R25 ;
F2F.F64.F32 R12, R12 ;
DADD R14, R18, R14 ;
F2F.F64.F32 R18, R16 ;
DADD R10, R14, R10 ;
DADD R10, R10, R12 ;
DADD R18, R10, R18 ;
ISETP.GE.U32.AND P1, PT, R9.reuse, c[0x0][0x160], PT ;
IADD3 R10, -R9, c[0x0][0x160], RZ ;
ISETP.LE.U32.OR P1, PT, R10, 0xc, P1 ;
@P1 BRA 0x3980 ;
PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ;
ULDC UR4, c[0x0][0x160] ;
UIADD3 UR4, UR4, -0xc, URZ ;
IMAD.MOV.U32 R17, RZ, RZ, 0x4 ;
IMAD R26, R0, c[0x0][0x160], R9 ;
IMAD.WIDE.U32 R26, R26, R17, c[0x0][0x168] ;
IADD3 R14, R8, -0x2, RZ ;
LDG.E R26, [R26.64] ;
IMAD.WIDE.U32 R14, R14, R17, c[0x0][0x168] ;
IADD3 R10, R8, -0x1, RZ ;
LDG.E R16, [R14.64] ;
IMAD.WIDE.U32 R10, R10, R17.reuse, c[0x0][0x168] ;
IADD3 R21, R9, 0x4, RZ ;
IADD3 R22, R8.reuse, 0x3, RZ ;
IMAD.WIDE.U32 R28, R8.reuse, R17, c[0x0][0x168] ;
IADD3 R24, R8, 0x2, RZ ;
LDG.E R10, [R10.64] ;
LDG.E R13, [R28.64] ;
IMAD R20, R0, c[0x0][0x160], R21 ;
LDS R27, [R6+0x8] ;
IMAD.WIDE.U32 R20, R20, R17, c[0x0][0x168] ;
LDG.E R12, [R20.64] ;
IMAD.WIDE.U32 R22, R22, R17, c[0x0][0x168] ;
IMAD.WIDE.U32 R24, R24, R17, c[0x0][0x168] ;
LDG.E R14, [R22.64] ;
LDS R21, [R6] ;
LDG.E R15, [R24.64] ;
LDS R23, [R6+0x4] ;
IADD3 R28, R8, 0x4, RZ ;
IMAD.WIDE.U32 R28, R28, R17, c[0x0][0x168] ;
LDG.E R11, [R28.64] ;
IADD3 R25, R9, 0x8, RZ ;
IADD3 R24, R8, 0x6, RZ ;
IMAD R25, R0, c[0x0][0x160], R25 ;
IADD3 R28, R8, 0x8, RZ ;
IMAD.WIDE.U32 R28, R28, R17, c[0x0][0x168] ;
FMUL R26, R26, R21 ;
F2F.F64.F32 R20, R26 ;
FMUL R16, R16, R23 ;
IMAD.WIDE.U32 R22, R25, R17, c[0x0][0x168] ;
IMAD.WIDE.U32 R24, R24, R17, c[0x0][0x168] ;
LDG.E R23, [R22.64] ;
DADD R20, R20, R18 ;
F2F.F64.F32 R18, R16 ;
FMUL R10, R10, R27 ;
IADD3 R26, R8, 0x7, RZ ;
LDG.E R22, [R28.64] ;
LDG.E R16, [R24.64] ;
IMAD.WIDE.U32 R26, R26, R17, c[0x0][0x168] ;
LDG.E R26, [R26.64] ;
F2F.F64.F32 R24, R10 ;
DADD R18, R20, R18 ;
IADD3 R21, R9, 0xc, RZ ;
IMAD R20, R0, c[0x0][0x160], R21 ;
IMAD.WIDE.U32 R20, R20, R17, c[0x0][0x168] ;
DADD R24, R18, R24 ;
IADD3 R18, R8, 0xa, RZ ;
LDG.E R20, [R20.64] ;
IADD3 R10, R8, 0xb, RZ ;
IMAD.WIDE.U32 R18, R18, R17, c[0x0][0x168] ;
IMAD.WIDE.U32 R28, R10, R17, c[0x0][0x168] ;
LDG.E R19, [R18.64] ;
IADD3 R10, R8, 0xc, RZ ;
LDS R21, [R6+0x1c] ;
LDG.E R18, [R28.64] ;
IMAD.WIDE.U32 R28, R10, R17, c[0x0][0x168] ;
LDS R17, [R6+0xc] ;
LDG.E R10, [R28.64] ;
FMUL R17, R13, R17 ;
LDS R13, [R6+0x10] ;
FMUL R27, R12, R13 ;
F2F.F64.F32 R12, R17 ;
LDS R17, [R6+0x14] ;
DADD R12, R24, R12 ;
F2F.F64.F32 R24, R27 ;
LDS R27, [R6+0x18] ;
DADD R24, R12, R24 ;
FMUL R29, R15, R17 ;
LDS R17, [R6+0x24] ;
F2F.F64.F32 R12, R29 ;
FMUL R28, R14, R27 ;
DADD R12, R24, R12 ;
LDS R27, [R6+0x28] ;
F2F.F64.F32 R14, R28 ;
FMUL R11, R11, R21 ;
LDS R21, [R6+0x30] ;
LDS R24, [R6+0x34] ;
LDS R28, [R6+0x20] ;
LDS R25, [R6+0x3c] ;
DADD R14, R12, R14 ;
F2F.F64.F32 R12, R11 ;
LDS R11, [R6+0x2c] ;
DADD R14, R14, R12 ;
FMUL R28, R23, R28 ;
LDS R23, [R6+0x38] ;
FMUL R29, R16, R17 ;
F2F.F64.F32 R16, R28 ;
F2F.F64.F32 R12, R29 ;
FMUL R28, R26, R27 ;
FMUL R11, R22, R11 ;
DADD R14, R14, R16 ;
F2F.F64.F32 R16, R28 ;
DADD R14, R14, R12 ;
F2F.F64.F32 R26, R11 ;
FMUL R20, R20, R21 ;
F2F.F64.F32 R12, R20 ;
DADD R16, R14, R16 ;
FMUL R24, R19, R24 ;
F2F.F64.F32 R14, R24 ;
DADD R26, R16, R26 ;
FMUL R23, R18, R23 ;
F2F.F64.F32 R16, R23 ;
DADD R12, R26, R12 ;
IADD3 R9, R9, 0x10, RZ ;
FMUL R10, R10, R25 ;
ISETP.GE.U32.AND P1, PT, R9, UR4, PT ;
F2F.F64.F32 R18, R10 ;
DADD R12, R12, R14 ;
DADD R12, R12, R16 ;
IADD3 R6, R6, 0x40, RZ ;
IADD3 R8, R8, 0x10, RZ ;
DADD R18, R12, R18 ;
@!P1 BRA 0x3200 ;
ISETP.GE.U32.AND P1, PT, R9.reuse, c[0x0][0x160], PT ;
IADD3 R10, -R9, c[0x0][0x160], RZ ;
ISETP.LE.U32.OR P1, PT, R10, 0x4, P1 ;
@P1 BRA 0x3d90 ;
IMAD.MOV.U32 R13, RZ, RZ, 0x4 ;
IADD3 R14, R8, -0x2, RZ ;
IMAD R10, R0, c[0x0][0x160], R9 ;
IADD3 R20, R8, -0x1, RZ ;
LDS R28, [R6] ;
IMAD.WIDE.U32 R10, R10, R13.reuse, c[0x0][0x168] ;
IADD3 R23, R9, 0x4, RZ ;
LDS R29, [R6+0x8] ;
IMAD.WIDE.U32 R14, R14, R13, c[0x0][0x168] ;
LDG.E R10, [R10.64] ;
LDG.E R17, [R14.64] ;
IMAD.WIDE.U32 R20, R20, R13, c[0x0][0x168] ;
IMAD.WIDE.U32 R26, R8, R13.reuse, c[0x0][0x168] ;
LDG.E R16, [R20.64] ;
IMAD R24, R0, c[0x0][0x160], R23 ;
IADD3 R22, R8, 0x2, RZ ;
LDG.E R26, [R26.64] ;
IMAD.WIDE.U32 R24, R24, R13.reuse, c[0x0][0x168] ;
IADD3 R14, R8, 0x3, RZ ;
LDS R11, [R6+0x14] ;
IMAD.WIDE.U32 R22, R22, R13, c[0x0][0x168] ;
LDG.E R24, [R24.64] ;
IADD3 R12, R8, 0x4, RZ ;
IMAD.WIDE.U32 R14, R14, R13.reuse, c[0x0][0x168] ;
LDG.E R22, [R22.64] ;
IMAD.WIDE.U32 R12, R12, R13, c[0x0][0x168] ;
LDG.E R21, [R14.64] ;
LDG.E R20, [R12.64] ;
PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ;
IADD3 R9, R9, 0x8, RZ ;
LDS R27, [R6+0xc] ;
IADD3 R8, R8, 0x8, RZ ;
LDS R25, [R6+0x10] ;
LDS R12, [R6+0x4] ;
LDS R23, [R6+0x1c] ;
FMUL R28, R10, R28 ;
LDS R10, [R6+0x18] ;
F2F.F64.F32 R14, R28 ;
FMUL R17, R17, R12 ;
FMUL R29, R16, R29 ;
IADD3 R6, R6, 0x20, RZ ;
F2F.F64.F32 R12, R17 ;
FMUL R26, R26, R27 ;
F2F.F64.F32 R16, R29 ;
DADD R18, R18, R14 ;
FMUL R24, R24, R25 ;
FMUL R22, R22, R11 ;
F2F.F64.F32 R14, R26 ;
DADD R12, R18, R12 ;
FMUL R20, R20, R23 ;
F2F.F64.F32 R18, R24 ;
DADD R16, R12, R16 ;
FMUL R21, R21, R10 ;
F2F.F64.F32 R12, R22 ;
DADD R14, R16, R14 ;
F2F.F64.F32 R10, R21 ;
DADD R14, R14, R18 ;
F2F.F64.F32 R18, R20 ;
DADD R12, R14, R12 ;
DADD R10, R12, R10 ;
DADD R18, R10, R18 ;
ISETP.LT.U32.OR P0, PT, R9, c[0x0][0x160], P0 ;
@!P0 BRA 0x3f70 ;
IMAD.MOV.U32 R17, RZ, RZ, 0x4 ;
IADD3 R12, R8, -0x2, RZ ;
IMAD R10, R0, c[0x0][0x160], R9 ;
IADD3 R14, R8, -0x1, RZ ;
LDS R9, [R6] ;
IMAD.WIDE.U32 R10, R10, R17.reuse, c[0x0][0x168] ;
LDS R21, [R6+0x4] ;
IMAD.WIDE.U32 R12, R12, R17, c[0x0][0x168] ;
LDG.E R10, [R10.64] ;
IMAD.WIDE.U32 R14, R14, R17.reuse, c[0x0][0x168] ;
LDG.E R12, [R12.64] ;
IMAD.WIDE.U32 R16, R8, R17, c[0x0][0x168] ;
LDG.E R14, [R14.64] ;
LDG.E R16, [R16.64] ;
LDS R23, [R6+0x8] ;
LDS R25, [R6+0xc] ;
FMUL R20, R10, R9 ;
F2F.F64.F32 R8, R20 ;
FMUL R10, R12, R21 ;
FMUL R12, R14, R23 ;
F2F.F64.F32 R10, R10 ;
FMUL R16, R16, R25 ;
F2F.F64.F32 R12, R12 ;
DADD R8, R18, R8 ;
F2F.F64.F32 R18, R16 ;
DADD R8, R8, R10 ;
DADD R8, R8, R12 ;
DADD R18, R8, R18 ;
IMAD.MOV.U32 R13, RZ, RZ, 0x4 ;
LDS R8, [R7+-0x28] ;
IMAD R20, R0, c[0x0][0x160], R3 ;
IMAD.WIDE R12, R20, R13, c[0x0][0x180] ;
LDG.E R21, [R12.64] ;
IMAD.MOV.U32 R14, RZ, RZ, 0x1 ;
F2F.F64.F32 R8, R8 ;
MUFU.RCP64H R15, R9 ;
DFMA R10, -R8, R14, 1 ;
DFMA R16, R10, R10, R10 ;
DFMA R16, R14, R16, R14 ;
DFMA R14, -R8, R16, 1 ;
DFMA R14, R16, R14, R16 ;
F2F.F64.F32 R10, R21 ;
DADD R10, R10, -R18 ;
DMUL R6, R10, R14 ;
FSETP.GEU.AND P1, PT, |R11|, 6.5827683646048100446e-37, PT ;
DFMA R12, -R8, R6, R10 ;
DFMA R6, R14, R12, R6 ;
FFMA R12, RZ, R9, R7 ;
FSETP.GT.AND P0, PT, |R12|, 1.469367938527859385e-39, PT ;
@P0 BRA P1, 0x40f0 ;
MOV R22, 0x40f0 ;
CALL.REL.NOINC 0x4180 ;
F2F.F32.F64 R7, R6 ;
IMAD.MOV.U32 R21, RZ, RZ, 0x4 ;
ISETP.GT.AND P0, PT, R5, 0x1, PT ;
IADD3 R2, R2, 0x1, RZ ;
IMAD.WIDE R20, R20, R21, c[0x0][0x168] ;
STG.E [R20.64], R7 ;
@!P0 CALL.REL.NOINC 0x4170 ;
BRA 0x2c80 ;
EXIT ;
FSETP.GEU.AND P0, PT, |R9|.reuse, 1.469367938527859385e-39, PT ;
IMAD.MOV.U32 R12, RZ, RZ, 0x1 ;
LOP3.LUT R6, R9.reuse, 0x800fffff, RZ, 0xc0, !PT ;
IMAD.MOV.U32 R23, RZ, RZ, 0x1ca00000 ;
LOP3.LUT R21, R9, 0x7ff00000, RZ, 0xc0, !PT ;
LOP3.LUT R7, R6, 0x3ff00000, RZ, 0xfc, !PT ;
IMAD.MOV.U32 R6, RZ, RZ, R8 ;
LOP3.LUT R24, R11, 0x7ff00000, RZ, 0xc0, !PT ;
ISETP.GE.U32.AND P1, PT, R24, R21, PT ;
@!P0 DMUL R6, R8, 8.98846567431157953865e+307 ;
IMAD.MOV.U32 R26, RZ, RZ, R24 ;
SEL R17, R23, 0x63400000, !P1 ;
FSETP.GEU.AND P1, PT, |R11|, 1.469367938527859385e-39, PT ;
MUFU.RCP64H R13, R7 ;
@!P0 LOP3.LUT R21, R7, 0x7ff00000, RZ, 0xc0, !PT ;
DFMA R14, R12, -R6, 1 ;
DFMA R14, R14, R14, R14 ;
DFMA R12, R12, R14, R12 ;
DFMA R14, R12, -R6, 1 ;
DFMA R14, R12, R14, R12 ;
LOP3.LUT R13, R17, 0x800fffff, R11, 0xf8, !PT ;
IMAD.MOV.U32 R12, RZ, RZ, R10 ;
@P1 BRA 0x4370 ;
LOP3.LUT R17, R9, 0x7ff00000, RZ, 0xc0, !PT ;
IMAD.MOV.U32 R16, RZ, RZ, RZ ;
ISETP.GE.U32.AND P0, PT, R24, R17, PT ;
SEL R17, R23, 0x63400000, !P0 ;
LOP3.LUT R17, R17, 0x80000000, R11, 0xf8, !PT ;
LOP3.LUT R17, R17, 0x100000, RZ, 0xfc, !PT ;
DFMA R12, R12, 2, -R16 ;
LOP3.LUT R26, R13, 0x7ff00000, RZ, 0xc0, !PT ;
IADD3 R18, R26, -0x1, RZ ;
DMUL R16, R14, R12 ;
IADD3 R25, R21, -0x1, RZ ;
ISETP.GT.U32.AND P0, PT, R18, 0x7feffffe, PT ;
DFMA R18, R16, -R6, R12 ;
ISETP.GT.U32.OR P0, PT, R25, 0x7feffffe, P0 ;
DFMA R18, R14, R18, R16 ;
@P0 BRA 0x45b0 ;
LOP3.LUT R11, R9, 0x7ff00000, RZ, 0xc0, !PT ;
ISETP.GE.U32.AND P0, PT, R24.reuse, R11, PT ;
IMAD.IADD R10, R24, 0x1, -R11 ;
SEL R23, R23, 0x63400000, !P0 ;
IMNMX R10, R10, -0x46a00000, !PT ;
IMNMX R10, R10, 0x46a00000, PT ;
IMAD.IADD R16, R10, 0x1, -R23 ;
IMAD.MOV.U32 R10, RZ, RZ, RZ ;
IADD3 R11, R16, 0x7fe00000, RZ ;
DMUL R14, R18, R10 ;
FSETP.GTU.AND P0, PT, |R15|, 1.469367938527859385e-39, PT ;
@P0 BRA 0x4700 ;
DFMA R6, R18, -R6, R12 ;
IMAD.MOV.U32 R10, RZ, RZ, RZ ;
FSETP.NEU.AND P0, PT, R7.reuse, RZ, PT ;
LOP3.LUT R9, R7, 0x80000000, R9, 0x48, !PT ;
LOP3.LUT R11, R9, R11, RZ, 0xfc, !PT ;
@!P0 BRA 0x4700 ;
IMAD.MOV R7, RZ, RZ, -R16 ;
DMUL.RP R10, R18, R10 ;
IMAD.MOV.U32 R6, RZ, RZ, RZ ;
DFMA R6, R14, -R6, R18 ;
LOP3.LUT R9, R11, R9, RZ, 0x3c, !PT ;
IADD3 R6, -R16, -0x43300000, RZ ;
FSETP.NEU.AND P0, PT, |R7|, R6, PT ;
FSEL R14, R10, R14, !P0 ;
FSEL R15, R9, R15, !P0 ;
BRA 0x4700 ;
DSETP.NAN.AND P0, PT, R10, R10, PT ;
@P0 BRA 0x46e0 ;
DSETP.NAN.AND P0, PT, R8, R8, PT ;
@P0 BRA 0x46b0 ;
ISETP.NE.AND P0, PT, R26, R21, PT ;
IMAD.MOV.U32 R14, RZ, RZ, 0x0 ;
IMAD.MOV.U32 R15, RZ, RZ, -0x80000 ;
@!P0 BRA 0x4700 ;
ISETP.NE.AND P0, PT, R26, 0x7ff00000, PT ;
LOP3.LUT R15, R11, 0x80000000, R9, 0x48, !PT ;
ISETP.EQ.OR P0, PT, R21, RZ, !P0 ;
@P0 LOP3.LUT R6, R15, 0x7ff00000, RZ, 0xfc, !PT ;
@!P0 MOV R14, RZ ;
@P0 IMAD.MOV.U32 R14, RZ, RZ, RZ ;
@P0 IMAD.MOV.U32 R15, RZ, RZ, R6 ;
BRA 0x4700 ;
LOP3.LUT R15, R9, 0x80000, RZ, 0xfc, !PT ;
IMAD.MOV.U32 R14, RZ, RZ, R8 ;
BRA 0x4700 ;
LOP3.LUT R15, R11, 0x80000, RZ, 0xfc, !PT ;
IMAD.MOV.U32 R14, RZ, RZ, R10 ;
IMAD.MOV.U32 R23, RZ, RZ, 0x0 ;
IMAD.MOV.U32 R6, RZ, RZ, R14 ;
IMAD.MOV.U32 R7, RZ, RZ, R15 ;
RET.REL.NODEC R22 0x0 ;
SHF.R.U32.HI R15, RZ, 0x17, R17.reuse ;
IMAD.MOV.U32 R21, RZ, RZ, R17 ;
SHF.R.U32.HI R16, RZ, 0x17, R18 ;
LOP3.LUT R15, R15, 0xff, RZ, 0xc0, !PT ;
LOP3.LUT R23, R16, 0xff, RZ, 0xc0, !PT ;
IADD3 R22, R15, -0x1, RZ ;
IADD3 R20, R23, -0x1, RZ ;
ISETP.GT.U32.AND P0, PT, R22, 0xfd, PT ;
ISETP.GT.U32.OR P0, PT, R20, 0xfd, P0 ;
@!P0 IMAD.MOV.U32 R16, RZ, RZ, RZ ;
@!P0 BRA 0x4970 ;
FSETP.GTU.FTZ.AND P0, PT, |R18|, +INF , PT ;
IMAD.MOV.U32 R19, RZ, RZ, R18 ;
FSETP.GTU.FTZ.AND P1, PT, |R17|, +INF , PT ;
PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ;
@P0 BRA 0x4d50 ;
LOP3.LUT P0, RZ, R21, 0x7fffffff, R18, 0xc8, !PT ;
@!P0 BRA 0x4d30 ;
FSETP.NEU.FTZ.AND P1, PT, |R19|, +INF , PT ;
FSETP.NEU.FTZ.AND P2, PT, |R17|, +INF , PT ;
FSETP.NEU.FTZ.AND P0, PT, |R19|, +INF , PT ;
@!P2 BRA !P1, 0x4d30 ;
LOP3.LUT P1, RZ, R18, 0x7fffffff, RZ, 0xc0, !PT ;
PLOP3.LUT P1, PT, P2, P1, PT, 0x2a, 0x0 ;
@P1 BRA 0x4d10 ;
LOP3.LUT P1, RZ, R21, 0x7fffffff, RZ, 0xc0, !PT ;
PLOP3.LUT P0, PT, P0, P1, PT, 0x2a, 0x0 ;
@P0 BRA 0x4ce0 ;
ISETP.GE.AND P0, PT, R20, RZ, PT ;
ISETP.GE.AND P1, PT, R22, RZ, PT ;
@P0 IMAD.MOV.U32 R16, RZ, RZ, RZ ;
@!P0 IMAD.MOV.U32 R16, RZ, RZ, -0x40 ;
@!P0 FFMA R18, R19, 1.84467440737095516160e+19, RZ ;
@!P1 FFMA R21, R17, 1.84467440737095516160e+19, RZ ;
@!P1 IADD3 R16, R16, 0x40, RZ ;
LEA R20, R15, 0xc0800000, 0x17 ;
IMAD.IADD R22, R21, 0x1, -R20 ;
IADD3 R21, R23, -0x7f, RZ ;
MUFU.RCP R17, R22 ;
FADD.FTZ R19, -R22, -RZ ;
IMAD R18, R21.reuse, -0x800000, R18 ;
IADD3 R21, R21, 0x7f, -R15 ;
IMAD.IADD R21, R21, 0x1, R16 ;
FFMA R20, R17, R19, 1 ;
FFMA R17, R17, R20, R17 ;
FFMA R20, R18, R17, RZ ;
FFMA R23, R19, R20, R18 ;
FFMA R20, R17, R23, R20 ;
FFMA R19, R19, R20, R18 ;
FFMA R18, R17, R19, R20 ;
SHF.R.U32.HI R15, RZ, 0x17, R18 ;
LOP3.LUT R15, R15, 0xff, RZ, 0xc0, !PT ;
IMAD.IADD R22, R15, 0x1, R21 ;
IADD3 R15, R22, -0x1, RZ ;
ISETP.GE.U32.AND P0, PT, R15, 0xfe, PT ;
@!P0 BRA 0x4cc0 ;
ISETP.GT.AND P0, PT, R22, 0xfe, PT ;
@P0 BRA 0x4c90 ;
ISETP.GE.AND P0, PT, R22, 0x1, PT ;
@P0 BRA 0x4d60 ;
ISETP.GE.AND P0, PT, R22, -0x18, PT ;
LOP3.LUT R18, R18, 0x80000000, RZ, 0xc0, !PT ;
@!P0 BRA 0x4d60 ;
FFMA.RZ R15, R17, R19.reuse, R20.reuse ;
ISETP.NE.AND P2, PT, R22.reuse, RZ, PT ;
ISETP.NE.AND P1, PT, R22.reuse, RZ, PT ;
LOP3.LUT R16, R15, 0x7fffff, RZ, 0xc0, !PT ;
FFMA.RP R15, R17.reuse, R19.reuse, R20.reuse ;
FFMA.RM R20, R17, R19, R20 ;
IADD3 R17, R22, 0x20, RZ ;
IMAD.MOV R19, RZ, RZ, -R22 ;
LOP3.LUT R16, R16, 0x800000, RZ, 0xfc, !PT ;
FSETP.NEU.FTZ.AND P0, PT, R15, R20, PT ;
SHF.L.U32 R17, R16, R17, RZ ;
SEL R15, R19, RZ, P2 ;
ISETP.NE.AND P1, PT, R17, RZ, P1 ;
SHF.R.U32.HI R15, RZ, R15, R16 ;
PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ;
SHF.R.U32.HI R17, RZ, 0x1, R15 ;
SEL R16, RZ, 0x1, !P0 ;
LOP3.LUT R16, R16, 0x1, R17, 0xf8, !PT ;
LOP3.LUT R16, R16, R15, RZ, 0xc0, !PT ;
IMAD.IADD R17, R17, 0x1, R16 ;
LOP3.LUT R18, R17, R18, RZ, 0xfc, !PT ;
BRA 0x4d60 ;
LOP3.LUT R18, R18, 0x80000000, RZ, 0xc0, !PT ;
LOP3.LUT R18, R18, 0x7f800000, RZ, 0xfc, !PT ;
BRA 0x4d60 ;
IMAD R18, R21, 0x800000, R18 ;
BRA 0x4d60 ;
LOP3.LUT R18, R21, 0x80000000, R18, 0x48, !PT ;
LOP3.LUT R18, R18, 0x7f800000, RZ, 0xfc, !PT ;
BRA 0x4d60 ;
LOP3.LUT R18, R21, 0x80000000, R18, 0x48, !PT ;
BRA 0x4d60 ;
MUFU.RSQ R18, -QNAN ;
BRA 0x4d60 ;
FADD.FTZ R18, R19, R17 ;
IMAD.MOV.U32 R15, RZ, RZ, 0x0 ;
RET.REL.NODEC R14 0x0 ;
BRA 0x4d80;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
```
|
```amdasm
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z25GaussianEliminationSharediPfPKfS1_S_ ; -- Begin function _Z25GaussianEliminationSharediPfPKfS1_S_
.globl _Z25GaussianEliminationSharediPfPKfS1_S_
.p2align 8
.type _Z25GaussianEliminationSharediPfPKfS1_S_,@function
_Z25GaussianEliminationSharediPfPKfS1_S_: ; @_Z25GaussianEliminationSharediPfPKfS1_S_
; %bb.0:
s_clause 0x1
s_load_b32 s12, s[0:1], 0x0
s_load_b256 s[4:11], s[0:1], 0x8
s_mov_b32 s0, 0
s_waitcnt lgkmcnt(0)
s_cmp_gt_i32 s12, 0
s_mul_i32 s2, s15, s12
s_cselect_b32 s13, -1, 0
s_cmp_lt_i32 s12, 1
s_cbranch_scc1 .LBB0_7
; %bb.1: ; %.preheader108.preheader
v_mov_b32_e32 v0, 0
s_mov_b32 s1, 0
.LBB0_2: ; %.preheader108
; =>This Loop Header: Depth=1
; Child Loop BB0_3 Depth 2
s_mov_b32 s3, s0
s_mov_b32 s14, s12
.LBB0_3: ; %.lr.ph
; Parent Loop BB0_2 Depth=1
; => This Inner Loop Header: Depth=2
v_mov_b32_e32 v1, s3
s_add_i32 s14, s14, -1
s_add_i32 s3, s3, 4
s_cmp_eq_u32 s14, 0
ds_store_b32 v1, v0
s_cbranch_scc0 .LBB0_3
; %bb.4: ; %._crit_edge
; in Loop: Header=BB0_2 Depth=1
s_add_i32 s1, s1, 1
s_add_i32 s0, s0, 36
s_cmp_eq_u32 s1, s12
s_cbranch_scc0 .LBB0_2
; %bb.5: ; %.preheader107
s_ashr_i32 s3, s2, 31
s_delay_alu instid0(SALU_CYCLE_1)
s_lshl_b64 s[0:1], s[2:3], 2
s_mov_b32 s3, 0
s_add_u32 s0, s6, s0
s_addc_u32 s1, s7, s1
s_mov_b32 s6, s12
.LBB0_6: ; =>This Inner Loop Header: Depth=1
s_load_b32 s7, s[0:1], 0x0
v_mov_b32_e32 v0, s3
s_add_i32 s6, s6, -1
s_add_u32 s0, s0, 4
s_addc_u32 s1, s1, 0
s_add_i32 s3, s3, 40
s_cmp_eq_u32 s6, 0
s_waitcnt lgkmcnt(0)
v_mov_b32_e32 v1, s7
ds_store_b32 v0, v1
s_cbranch_scc0 .LBB0_6
.LBB0_7: ; %.preheader106
s_add_i32 s3, s12, -1
s_cmp_lt_i32 s12, 2
s_cbranch_scc1 .LBB0_10
; %bb.8: ; %.lr.ph114
s_lshl_b32 s0, s2, 1
s_mov_b32 s6, 4
s_mov_b32 s7, s3
.LBB0_9: ; =>This Inner Loop Header: Depth=1
s_ashr_i32 s1, s0, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_lshl_b64 s[16:17], s[0:1], 2
s_add_u32 s16, s8, s16
s_addc_u32 s17, s9, s17
s_add_i32 s7, s7, -1
s_load_b64 s[16:17], s[16:17], 0x4
v_mov_b32_e32 v0, s6
s_add_i32 s6, s6, 40
s_add_i32 s0, s0, 2
s_cmp_eq_u32 s7, 0
s_waitcnt lgkmcnt(0)
v_dual_mov_b32 v1, s16 :: v_dual_mov_b32 v2, s17
ds_store_2addr_b32 v0, v1, v2 offset1:8
s_cbranch_scc0 .LBB0_9
.LBB0_10: ; %.preheader105
v_cndmask_b32_e64 v0, 0, 1, s13
s_and_not1_b32 vcc_lo, exec_lo, s13
s_delay_alu instid0(VALU_DEP_1)
v_cmp_ne_u32_e64 s0, 1, v0
s_cbranch_vccnz .LBB0_18
; %bb.11: ; %.lr.ph123
v_mov_b32_e32 v2, 0
s_mov_b32 s1, 0
s_mov_b32 s9, 0
s_mov_b32 s8, 36
.LBB0_12: ; =>This Loop Header: Depth=1
; Child Loop BB0_14 Depth 2
; Child Loop BB0_15 Depth 3
s_mov_b32 s6, s9
s_add_i32 s9, s9, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_ge_i32 s9, s12
s_cbranch_scc1 .LBB0_17
; %bb.13: ; %.lr.ph121
; in Loop: Header=BB0_12 Depth=1
s_add_i32 s16, s6, s2
s_lshl_b32 s13, s6, 2
s_mul_i32 s14, s6, 36
s_ashr_i32 s17, s16, 31
s_add_i32 s14, s14, s13
s_lshl_b64 s[6:7], s[16:17], 2
v_mov_b32_e32 v3, s14
s_add_u32 s6, s10, s6
s_addc_u32 s7, s11, s7
s_mov_b32 s14, s8
s_mov_b32 s16, s9
.LBB0_14: ; %.lr.ph117.preheader
; Parent Loop BB0_12 Depth=1
; => This Loop Header: Depth=2
; Child Loop BB0_15 Depth 3
s_delay_alu instid0(SALU_CYCLE_1)
s_mul_i32 s17, s16, 36
s_mov_b32 s18, s14
s_add_i32 s17, s17, s13
s_mov_b32 s19, s12
v_mov_b32_e32 v0, s17
s_mov_b32 s17, s1
ds_load_b32 v0, v0
ds_load_b32 v1, v3
s_waitcnt lgkmcnt(0)
v_div_scale_f32 v4, null, v1, v1, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f32_e32 v5, v4
s_waitcnt_depctr 0xfff
v_fma_f32 v6, -v4, v5, 1.0
v_fmac_f32_e32 v5, v6, v5
v_div_scale_f32 v6, vcc_lo, v0, v1, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v7, v6, v5
v_fma_f32 v8, -v4, v7, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v7, v8, v5
v_fma_f32 v4, -v4, v7, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fmas_f32 v4, v4, v5, v7
v_div_fixup_f32 v0, v4, v1, v0
s_delay_alu instid0(VALU_DEP_1)
v_cvt_f64_f32_e32 v[0:1], v0
.LBB0_15: ; %.lr.ph117
; Parent Loop BB0_12 Depth=1
; Parent Loop BB0_14 Depth=2
; => This Inner Loop Header: Depth=3
v_mov_b32_e32 v8, s18
v_mov_b32_e32 v4, s17
s_add_i32 s19, s19, -1
s_add_i32 s18, s18, 4
s_add_i32 s17, s17, 4
ds_load_b32 v5, v8
ds_load_b32 v6, v4
s_cmp_eq_u32 s19, 0
s_waitcnt lgkmcnt(1)
v_cvt_f64_f32_e32 v[4:5], v5
s_waitcnt lgkmcnt(0)
v_cvt_f64_f32_e32 v[6:7], v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[4:5], -v[0:1], v[6:7], v[4:5]
v_cvt_f32_f64_e32 v4, v[4:5]
ds_store_b32 v8, v4
s_cbranch_scc0 .LBB0_15
; %bb.16: ; %._crit_edge118
; in Loop: Header=BB0_14 Depth=2
s_add_i32 s18, s16, s2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_ashr_i32 s19, s18, 31
s_lshl_b64 s[18:19], s[18:19], 2
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s18, s10, s18
s_addc_u32 s19, s11, s19
s_add_i32 s16, s16, 1
s_clause 0x1
global_load_b32 v4, v2, s[18:19]
global_load_b32 v6, v2, s[6:7]
s_add_i32 s14, s14, 36
s_cmp_ge_i32 s16, s12
s_waitcnt vmcnt(1)
v_cvt_f64_f32_e32 v[4:5], v4
s_waitcnt vmcnt(0)
v_cvt_f64_f32_e32 v[6:7], v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[0:1], -v[0:1], v[6:7], v[4:5]
v_cvt_f32_f64_e32 v0, v[0:1]
global_store_b32 v2, v0, s[18:19]
s_cbranch_scc0 .LBB0_14
.LBB0_17: ; %.loopexit
; in Loop: Header=BB0_12 Depth=1
s_add_i32 s8, s8, 36
s_add_i32 s1, s1, 36
s_cmp_lg_u32 s9, s12
s_cbranch_scc1 .LBB0_12
.LBB0_18: ; %._crit_edge124
s_delay_alu instid0(VALU_DEP_1)
s_and_b32 vcc_lo, exec_lo, s0
s_waitcnt lgkmcnt(0)
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
s_cbranch_vccnz .LBB0_24
; %bb.19: ; %.preheader.lr.ph
v_mov_b32_e32 v1, 0
s_add_i32 s15, s15, 1
s_mul_i32 s1, s12, 40
s_mul_i32 s0, s12, s15
s_sub_i32 s1, s1, 40
s_mov_b32 s6, -1
.LBB0_20: ; %.preheader
; =>This Loop Header: Depth=1
; Child Loop BB0_22 Depth 2
v_mov_b32_e32 v2, 0
v_mov_b32_e32 v3, 0
s_cmp_ge_u32 s3, s12
s_cbranch_scc1 .LBB0_23
; %bb.21: ; %.lr.ph127.preheader
; in Loop: Header=BB0_20 Depth=1
v_mov_b32_e32 v2, 0
v_dual_mov_b32 v3, 0 :: v_dual_mov_b32 v4, s6
s_mov_b32 s7, s1
.LBB0_22: ; %.lr.ph127
; Parent Loop BB0_20 Depth=1
; => This Inner Loop Header: Depth=2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v0, s0, v4
v_add_co_u32 v4, s8, v4, 1
v_lshlrev_b64 v[5:6], 2, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v5, vcc_lo, s4, v5
v_add_co_ci_u32_e32 v6, vcc_lo, s5, v6, vcc_lo
s_and_b32 vcc_lo, exec_lo, s8
global_load_b32 v0, v[5:6], off
v_mov_b32_e32 v5, s7
s_add_i32 s7, s7, 4
ds_load_b32 v5, v5
s_waitcnt vmcnt(0) lgkmcnt(0)
v_mul_f32_e32 v0, v5, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_f64_f32_e32 v[5:6], v0
v_add_f64 v[2:3], v[2:3], v[5:6]
s_cbranch_vccz .LBB0_22
.LBB0_23: ; %._crit_edge128
; in Loop: Header=BB0_20 Depth=1
s_add_i32 s8, s3, s2
s_mul_i32 s7, s3, 36
s_ashr_i32 s9, s8, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_lshl_b64 s[8:9], s[8:9], 2
s_add_u32 s14, s10, s8
s_addc_u32 s15, s11, s9
s_lshl_b32 s13, s3, 2
global_load_b32 v0, v1, s[14:15]
s_add_i32 s7, s7, s13
s_add_u32 s8, s4, s8
s_addc_u32 s9, s5, s9
s_add_i32 s6, s6, -1
s_sub_i32 s1, s1, 40
s_waitcnt vmcnt(0)
v_cvt_f64_f32_e32 v[4:5], v0
v_mov_b32_e32 v0, s7
s_add_i32 s7, s3, -1
s_cmp_lt_i32 s3, 1
s_mov_b32 s3, s7
ds_load_b32 v0, v0
s_waitcnt lgkmcnt(0)
v_cvt_f64_f32_e32 v[6:7], v0
v_add_f64 v[2:3], v[4:5], -v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_scale_f64 v[4:5], null, v[6:7], v[6:7], v[2:3]
v_rcp_f64_e32 v[8:9], v[4:5]
s_waitcnt_depctr 0xfff
v_fma_f64 v[10:11], -v[4:5], v[8:9], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[8:9], v[8:9], v[10:11], v[8:9]
v_fma_f64 v[10:11], -v[4:5], v[8:9], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_fma_f64 v[8:9], v[8:9], v[10:11], v[8:9]
v_div_scale_f64 v[10:11], vcc_lo, v[2:3], v[6:7], v[2:3]
v_mul_f64 v[12:13], v[10:11], v[8:9]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[4:5], -v[4:5], v[12:13], v[10:11]
v_div_fmas_f64 v[4:5], v[4:5], v[8:9], v[12:13]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fixup_f64 v[2:3], v[4:5], v[6:7], v[2:3]
v_cvt_f32_f64_e32 v0, v[2:3]
global_store_b32 v1, v0, s[8:9]
s_cbranch_scc0 .LBB0_20
.LBB0_24: ; %._crit_edge131
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z25GaussianEliminationSharediPfPKfS1_S_
.amdhsa_group_segment_fixed_size 324
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 40
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 14
.amdhsa_next_free_sgpr 20
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z25GaussianEliminationSharediPfPKfS1_S_, .Lfunc_end0-_Z25GaussianEliminationSharediPfPKfS1_S_
; -- End function
.section .AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1172
; NumSgprs: 22
; NumVgprs: 14
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 324 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 22
; NumVGPRsForWavesPerEU: 14
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object ; @__hip_cuid_
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0 ; 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 324
.kernarg_segment_align: 8
.kernarg_segment_size: 40
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z25GaussianEliminationSharediPfPKfS1_S_
.private_segment_fixed_size: 0
.sgpr_count: 22
.sgpr_spill_count: 0
.symbol: _Z25GaussianEliminationSharediPfPKfS1_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 14
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
```
| 23,273 | 6,644 |
163 |
Convert the following CUDA host assembly code to AMD host assembly:
```cudaasm
.file "tmpxft_001ab8c1_00000000-6_GaussianEliminationShared.cudafe1.cpp"
.text
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z54__device_stub__Z25GaussianEliminationSharediPfPKfS1_S_iPfPKfS1_S_
.type _Z54__device_stub__Z25GaussianEliminationSharediPfPKfS1_S_iPfPKfS1_S_, @function
_Z54__device_stub__Z25GaussianEliminationSharediPfPKfS1_S_iPfPKfS1_S_:
.LFB2051:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movl %edi, 44(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movq %r8, 8(%rsp)
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 44(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 184
pushq 56(%rsp)
.cfi_def_cfa_offset 192
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z25GaussianEliminationSharediPfPKfS1_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z54__device_stub__Z25GaussianEliminationSharediPfPKfS1_S_iPfPKfS1_S_, .-_Z54__device_stub__Z25GaussianEliminationSharediPfPKfS1_S_iPfPKfS1_S_
.globl _Z25GaussianEliminationSharediPfPKfS1_S_
.type _Z25GaussianEliminationSharediPfPKfS1_S_, @function
_Z25GaussianEliminationSharediPfPKfS1_S_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z54__device_stub__Z25GaussianEliminationSharediPfPKfS1_S_iPfPKfS1_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z25GaussianEliminationSharediPfPKfS1_S_, .-_Z25GaussianEliminationSharediPfPKfS1_S_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z25GaussianEliminationSharediPfPKfS1_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z25GaussianEliminationSharediPfPKfS1_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
```
|
```amdasm
.text
.file "GaussianEliminationShared.hip"
.globl _Z40__device_stub__GaussianEliminationSharediPfPKfS1_S_ # -- Begin function _Z40__device_stub__GaussianEliminationSharediPfPKfS1_S_
.type _Z40__device_stub__GaussianEliminationSharediPfPKfS1_S_,@function
_Z40__device_stub__GaussianEliminationSharediPfPKfS1_S_: # @_Z40__device_stub__GaussianEliminationSharediPfPKfS1_S_
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $144, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 12(%rsp), %rax
movl %edi, (%rax)
leaq 56(%rsp), %rdi
movq %rsi, (%rdi)
leaq 48(%rsp), %rsi
movq %rdx, (%rsi)
leaq 40(%rsp), %rdx
movq %rcx, (%rdx)
leaq 32(%rsp), %rcx
movq %r8, (%rcx)
leaq 96(%rsp), %rbx
movq %rax, (%rbx)
movq %rdi, 8(%rbx)
movq %rsi, 16(%rbx)
movq %rdx, 24(%rbx)
movq %rcx, 32(%rbx)
leaq 80(%rsp), %r14
leaq 64(%rsp), %r15
leaq 24(%rsp), %r12
leaq 16(%rsp), %r13
movq %r14, %rdi
movq %r15, %rsi
movq %r12, %rdx
movq %r13, %rcx
callq __hipPopCallConfiguration
movq (%r14), %rsi
movl 8(%r14), %edx
movq (%r15), %rcx
movl 8(%r15), %r8d
movl $_Z25GaussianEliminationSharediPfPKfS1_S_, %edi
movq %rbx, %r9
pushq (%r13)
.cfi_adjust_cfa_offset 8
pushq (%r12)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $160, %rsp
.cfi_adjust_cfa_offset -160
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z40__device_stub__GaussianEliminationSharediPfPKfS1_S_, .Lfunc_end0-_Z40__device_stub__GaussianEliminationSharediPfPKfS1_S_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, %rdi
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z25GaussianEliminationSharediPfPKfS1_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z25GaussianEliminationSharediPfPKfS1_S_,@object # @_Z25GaussianEliminationSharediPfPKfS1_S_
.section .rodata,"a",@progbits
.globl _Z25GaussianEliminationSharediPfPKfS1_S_
.p2align 3, 0x0
_Z25GaussianEliminationSharediPfPKfS1_S_:
.quad _Z40__device_stub__GaussianEliminationSharediPfPKfS1_S_
.size _Z25GaussianEliminationSharediPfPKfS1_S_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z25GaussianEliminationSharediPfPKfS1_S_"
.size .L__unnamed_1, 41
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z40__device_stub__GaussianEliminationSharediPfPKfS1_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z25GaussianEliminationSharediPfPKfS1_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
```
| 2,060 | 2,236 |
164 |
Convert the following CUDA device assembly code to AMD device assembly:
```cudaasm
code for sm_80
Function : _Z9matrixMulPdS_S_jjj
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
MOV R1, c[0x0][0x28] ;
S2R R9, SR_CTAID.X ;
S2R R22, SR_TID.X ;
S2R R3, SR_CTAID.Y ;
S2R R2, SR_TID.Y ;
IMAD R0, R9, c[0x0][0x0], R22 ;
ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x17c], PT ;
IMAD R3, R3, c[0x0][0x4], R2 ;
ISETP.GE.U32.OR P0, PT, R3, c[0x0][0x178], P0 ;
@P0 EXIT ;
ISETP.NE.AND P0, PT, RZ, c[0x0][0x180], PT ;
ULDC.64 UR4, c[0x0][0x118] ;
CS2R R28, SRZ ;
@!P0 BRA 0x4f0 ;
MOV R2, c[0x0][0x180] ;
CS2R R28, SRZ ;
IADD3 R5, R2.reuse, -0x1, RZ ;
LOP3.LUT R4, R2, 0x3, RZ, 0xc0, !PT ;
ISETP.GE.U32.AND P1, PT, R5, 0x3, PT ;
IMAD.MOV.U32 R5, RZ, RZ, RZ ;
ISETP.NE.AND P0, PT, R4, RZ, PT ;
@!P1 BRA 0x410 ;
IADD3 R22, R22, c[0x0][0x17c], RZ ;
IMAD R23, R3, R2, 0x3 ;
MOV R7, c[0x0][0x17c] ;
IMAD.MOV.U32 R5, RZ, RZ, RZ ;
IADD3 R24, R4, -c[0x0][0x180], RZ ;
IMAD R22, R9, c[0x0][0x0], R22 ;
MOV R26, R0 ;
CS2R R28, SRZ ;
IMAD R2, R7.reuse, 0x2, R0.reuse ;
IMAD R6, R7, 0x3, R0 ;
HFMA2.MMA R19, -RZ, RZ, 0, 4.76837158203125e-07 ;
IADD3 R8, R23, -0x3, RZ ;
IMAD.WIDE.U32 R8, R8, R19, c[0x0][0x160] ;
IMAD.WIDE.U32 R20, R26, R19.reuse, c[0x0][0x168] ;
LDG.E.64 R8, [R8.64] ;
LDG.E.64 R10, [R20.64] ;
IADD3 R16, R23.reuse, -0x2, RZ ;
IMAD.WIDE.U32 R14, R22, R19, c[0x0][0x168] ;
IADD3 R12, R23, -0x1, RZ ;
IMAD.WIDE.U32 R16, R16, R19.reuse, c[0x0][0x160] ;
LDG.E.64 R14, [R14.64] ;
LDG.E.64 R16, [R16.64] ;
IMAD.WIDE.U32 R12, R12, R19, c[0x0][0x160] ;
IMAD.WIDE.U32 R20, R23, R19.reuse, c[0x0][0x160] ;
LDG.E.64 R12, [R12.64] ;
LDG.E.64 R20, [R20.64] ;
DFMA R8, R10, R8, R28 ;
IMAD.WIDE.U32 R10, R2, R19, c[0x0][0x168] ;
IMAD.WIDE.U32 R18, R6, R19, c[0x0][0x168] ;
LDG.E.64 R10, [R10.64] ;
LDG.E.64 R18, [R18.64] ;
IADD3 R5, R5, 0x4, RZ ;
DFMA R8, R14, R16, R8 ;
IMAD.IADD R14, R24, 0x1, R5 ;
ISETP.NE.AND P1, PT, R14, RZ, PT ;
IMAD R2, R7.reuse, 0x4, R2 ;
LEA R22, R7.reuse, R22, 0x2 ;
IMAD R6, R7.reuse, 0x4, R6 ;
LEA R26, R7, R26, 0x2 ;
IADD3 R23, R23, 0x4, RZ ;
DFMA R8, R10, R12, R8 ;
DFMA R28, R18, R20, R8 ;
@P1 BRA 0x200 ;
@!P0 BRA 0x4f0 ;
IMAD R2, R5, c[0x0][0x17c], R0 ;
IMAD R5, R3, c[0x0][0x180], R5 ;
MOV R8, 0x8 ;
IMAD.WIDE.U32 R6, R5, R8, c[0x0][0x160] ;
IMAD.WIDE.U32 R8, R2, R8, c[0x0][0x168] ;
LDG.E.64 R6, [R6.64] ;
LDG.E.64 R8, [R8.64] ;
IADD3 R4, R4, -0x1, RZ ;
IADD3 R5, R5, 0x1, RZ ;
ISETP.NE.AND P0, PT, R4, RZ, PT ;
IADD3 R2, R2, c[0x0][0x17c], RZ ;
DFMA R28, R8, R6, R28 ;
@P0 BRA 0x440 ;
IMAD.MOV.U32 R2, RZ, RZ, 0x8 ;
IMAD R3, R3, c[0x0][0x17c], R0 ;
IMAD.WIDE.U32 R2, R3, R2, c[0x0][0x170] ;
STG.E.64 [R2.64], R28 ;
EXIT ;
BRA 0x540;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
```
|
```amdasm
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9matrixMulPdS_S_jjj ; -- Begin function _Z9matrixMulPdS_S_jjj
.globl _Z9matrixMulPdS_S_jjj
.p2align 8
.type _Z9matrixMulPdS_S_jjj,@function
_Z9matrixMulPdS_S_jjj: ; @_Z9matrixMulPdS_S_jjj
; %bb.0:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x34
s_load_b128 s[4:7], s[0:1], 0x18
v_bfe_u32 v2, v0, 10, 10
v_and_b32_e32 v3, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s3, s2, 16
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[0:1], null, s15, s3, v[2:3]
v_mad_u64_u32 v[1:2], null, s14, s2, v[3:4]
v_cmp_gt_u32_e32 vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_u32_e64 s2, s5, v1
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_6
; %bb.1: ; %.preheader
s_clause 0x1
s_load_b128 s[8:11], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
s_cmp_eq_u32 s6, 0
s_cbranch_scc1 .LBB0_4
; %bb.2: ; %.lr.ph
v_mul_lo_u32 v4, v0, s6
v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v5, 0
v_dual_mov_b32 v3, 0 :: v_dual_mov_b32 v6, v1
.LBB0_3: ; =>This Inner Loop Header: Depth=1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
v_mov_b32_e32 v7, v5
v_lshlrev_b64 v[8:9], 3, v[4:5]
v_add_nc_u32_e32 v4, 1, v4
s_add_i32 s6, s6, -1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s6, 0
v_lshlrev_b64 v[10:11], 3, v[6:7]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v7, vcc_lo, s8, v8
v_add_co_ci_u32_e32 v8, vcc_lo, s9, v9, vcc_lo
v_add_nc_u32_e32 v6, s5, v6
s_delay_alu instid0(VALU_DEP_4)
v_add_co_u32 v9, vcc_lo, s10, v10
v_add_co_ci_u32_e32 v10, vcc_lo, s11, v11, vcc_lo
global_load_b64 v[7:8], v[7:8], off
global_load_b64 v[9:10], v[9:10], off
s_waitcnt vmcnt(0)
v_fma_f64 v[2:3], v[7:8], v[9:10], v[2:3]
s_cbranch_scc0 .LBB0_3
s_branch .LBB0_5
.LBB0_4:
v_mov_b32_e32 v2, 0
v_mov_b32_e32 v3, 0
.LBB0_5: ; %Flow54
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[4:5], null, v0, s5, v[1:2]
v_mov_b32_e32 v5, 0
v_lshlrev_b64 v[0:1], 3, v[4:5]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b64 v[0:1], v[2:3], off
.LBB0_6:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9matrixMulPdS_S_jjj
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 12
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9matrixMulPdS_S_jjj, .Lfunc_end0-_Z9matrixMulPdS_S_jjj
; -- End function
.section .AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 340
; NumSgprs: 18
; NumVgprs: 12
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 12
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object ; @__hip_cuid_
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0 ; 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9matrixMulPdS_S_jjj
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z9matrixMulPdS_S_jjj.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 12
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
```
| 1,764 | 3,293 |
165 |
Convert the following CUDA host assembly code to AMD host assembly:
```cudaasm
.file "tmpxft_00040f91_00000000-6_ee16b105_6.cudafe1.cpp"
.text
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2063:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2063:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "/home/ubuntu/Datasets/stackv2/train-structured/anantshah200/CS6023/master/Assignment2/ee16b105_6.cu"
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "%s in %s at line %d"
.text
.globl _Z13error_handler9cudaErrori
.type _Z13error_handler9cudaErrori, @function
_Z13error_handler9cudaErrori:
.LFB2057:
.cfi_startproc
endbr64
testl %edi, %edi
jne .L8
ret
.L8:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movl %esi, %ebx
call cudaGetErrorString@PLT
movq %rax, %rdx
movl %ebx, %r8d
leaq .LC0(%rip), %rcx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.cfi_endproc
.LFE2057:
.size _Z13error_handler9cudaErrori, .-_Z13error_handler9cudaErrori
.globl _Z11fill_matrixPdjj
.type _Z11fill_matrixPdjj, @function
_Z11fill_matrixPdjj:
.LFB2058:
.cfi_startproc
endbr64
movq %rdi, %r9
movl $0, %r8d
movl $0, %r10d
movss .LC2(%rip), %xmm3
movss .LC3(%rip), %xmm2
testl %esi, %esi
jne .L10
ret
.L17:
movl %r10d, %eax
pxor %xmm1, %xmm1
cvtsi2ssq %rax, %xmm1
mulss %xmm3, %xmm1
movl $0, %eax
.L16:
leal (%r8,%rax), %ecx
movl %eax, %edi
pxor %xmm0, %xmm0
cvtsi2ssq %rdi, %xmm0
mulss %xmm2, %xmm0
addss %xmm1, %xmm0
cvtss2sd %xmm0, %xmm0
movsd %xmm0, (%r9,%rcx,8)
addl $1, %eax
cmpl %eax, %edx
jne .L16
.L18:
addl $1, %r10d
addl %edx, %r8d
cmpl %r10d, %esi
je .L9
.L10:
testl %edx, %edx
jne .L17
jmp .L18
.L9:
ret
.cfi_endproc
.LFE2058:
.size _Z11fill_matrixPdjj, .-_Z11fill_matrixPdjj
.section .rodata.str1.1
.LC4:
.string "a"
.LC5:
.string "assignment2_out"
.LC6:
.string "%4.4f "
.LC7:
.string "\n"
.text
.globl _Z20print_matrix_to_filePdjj
.type _Z20print_matrix_to_filePdjj, @function
_Z20print_matrix_to_filePdjj:
.LFB2059:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $24, %rsp
.cfi_def_cfa_offset 80
movq %rdi, %r13
movl %esi, %ebx
movl %esi, 12(%rsp)
movl %edx, %r15d
leaq .LC4(%rip), %rsi
leaq .LC5(%rip), %rdi
call fopen@PLT
movq %rax, %r12
movl %r15d, %ebp
movl $0, 8(%rsp)
leaq .LC6(%rip), %r14
testl %ebx, %ebx
jne .L23
.L24:
movq %r12, %rdi
call fclose@PLT
addq $24, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L25:
.cfi_restore_state
movl %ebx, %eax
movsd 0(%r13,%rax,8), %xmm0
movq %r14, %rdx
movl $2, %esi
movq %r12, %rdi
movl $1, %eax
call __fprintf_chk@PLT
addl $1, %ebx
cmpl %ebp, %ebx
jne .L25
.L27:
leaq .LC7(%rip), %rdx
movl $2, %esi
movq %r12, %rdi
movl $0, %eax
call __fprintf_chk@PLT
addl $1, 8(%rsp)
movl 8(%rsp), %eax
addl %r15d, %ebp
cmpl %eax, 12(%rsp)
je .L24
.L23:
movl %ebp, %ebx
subl %r15d, %ebx
testl %r15d, %r15d
jne .L25
jmp .L27
.cfi_endproc
.LFE2059:
.size _Z20print_matrix_to_filePdjj, .-_Z20print_matrix_to_filePdjj
.globl _Z35__device_stub__Z9matrixMulPdS_S_jjjPdS_S_jjj
.type _Z35__device_stub__Z9matrixMulPdS_S_jjjPdS_S_jjj, @function
_Z35__device_stub__Z9matrixMulPdS_S_jjjPdS_S_jjj:
.LFB2085:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L37
.L33:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L38
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L37:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z9matrixMulPdS_S_jjj(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L33
.L38:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2085:
.size _Z35__device_stub__Z9matrixMulPdS_S_jjjPdS_S_jjj, .-_Z35__device_stub__Z9matrixMulPdS_S_jjjPdS_S_jjj
.globl _Z9matrixMulPdS_S_jjj
.type _Z9matrixMulPdS_S_jjj, @function
_Z9matrixMulPdS_S_jjj:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z9matrixMulPdS_S_jjjPdS_S_jjj
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _Z9matrixMulPdS_S_jjj, .-_Z9matrixMulPdS_S_jjj
.section .rodata.str1.8
.align 8
.LC8:
.string "error : Invalid number of arguments\n"
.section .rodata.str1.1
.LC11:
.string "Run-Time(seconds) : %.4f"
.text
.globl main
.type main, @function
main:
.LFB2060:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $80, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
cmpl $1, %edi
jne .L46
leaq 32(%rsp), %rdi
call cudaEventCreate@PLT
leaq 40(%rsp), %rdi
call cudaEventCreate@PLT
movl $268435456, %edi
call malloc@PLT
movq %rax, %r12
movl $1073741824, %edi
call malloc@PLT
movq %rax, %rbp
movl $536870912, %edi
call malloc@PLT
movq %rax, %rbx
movl $8192, %edx
movl $4096, %esi
movq %r12, %rdi
call _Z11fill_matrixPdjj
movl $16384, %edx
movl $8192, %esi
movq %rbp, %rdi
call _Z11fill_matrixPdjj
leaq 8(%rsp), %rdi
movl $268435456, %esi
call cudaMalloc@PLT
movl %eax, %edi
movl $107, %esi
call _Z13error_handler9cudaErrori
leaq 16(%rsp), %rdi
movl $1073741824, %esi
call cudaMalloc@PLT
movl %eax, %edi
movl $108, %esi
call _Z13error_handler9cudaErrori
leaq 24(%rsp), %rdi
movl $536870912, %esi
call cudaMalloc@PLT
movl %eax, %edi
movl $109, %esi
call _Z13error_handler9cudaErrori
movl $1, %ecx
movl $268435456, %edx
movq %r12, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %edi
movl $113, %esi
call _Z13error_handler9cudaErrori
movl $1, %ecx
movl $1073741824, %edx
movq %rbp, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %edi
movl $114, %esi
call _Z13error_handler9cudaErrori
movl $16, 48(%rsp)
movl $16, 52(%rsp)
movl $1, 56(%rsp)
movl $1024, 60(%rsp)
movl $256, 64(%rsp)
movl $1, 68(%rsp)
movl $0, %esi
movq 32(%rsp), %rdi
call cudaEventRecord@PLT
movl 56(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 48(%rsp), %rdx
movq 60(%rsp), %rdi
movl 68(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L47
.L43:
movl $0, %esi
movq 40(%rsp), %rdi
call cudaEventRecord@PLT
movl $2, %ecx
movl $536870912, %edx
movq 24(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
movl %eax, %edi
movl $125, %esi
call _Z13error_handler9cudaErrori
movq 40(%rsp), %rdi
call cudaEventSynchronize@PLT
movl $0x00000000, 4(%rsp)
leaq 4(%rsp), %rdi
movq 40(%rsp), %rdx
movq 32(%rsp), %rsi
call cudaEventElapsedTime@PLT
movss 4(%rsp), %xmm0
divss .LC10(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl $16384, %edx
movl $4096, %esi
movq %rbx, %rdi
call _Z20print_matrix_to_filePdjj
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq %r12, %rdi
call free@PLT
movq %rbp, %rdi
call free@PLT
movq %rbx, %rdi
call free@PLT
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L48
movl $0, %eax
addq $80, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L46:
.cfi_restore_state
leaq .LC8(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L47:
movl $8192, %r9d
movl $16384, %r8d
movl $4096, %ecx
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z35__device_stub__Z9matrixMulPdS_S_jjjPdS_S_jjj
jmp .L43
.L48:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2060:
.size main, .-main
.section .rodata.str1.1
.LC12:
.string "_Z9matrixMulPdS_S_jjj"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2088:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC12(%rip), %rdx
movq %rdx, %rcx
leaq _Z9matrixMulPdS_S_jjj(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2088:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC2:
.long 1074161254
.align 4
.LC3:
.long 1078774989
.align 4
.LC10:
.long 1148846080
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
```
|
```amdasm
.text
.file "ee16b105_6.hip"
.globl _Z13error_handler10hipError_ti # -- Begin function _Z13error_handler10hipError_ti
.type _Z13error_handler10hipError_ti,@function
_Z13error_handler10hipError_ti: # @_Z13error_handler10hipError_ti
.cfi_startproc
# %bb.0:
testl %edi, %edi
jne .LBB0_2
# %bb.1:
retq
.LBB0_2:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
movl %esi, %ebx
callq hipGetErrorString
movl $.L.str, %edi
movl $.L.str.1, %edx
movq %rax, %rsi
movl %ebx, %ecx
xorl %eax, %eax
callq printf
movl $1, %edi
callq exit
.Lfunc_end0:
.size _Z13error_handler10hipError_ti, .Lfunc_end0-_Z13error_handler10hipError_ti
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function _Z11fill_matrixPdjj
.LCPI1_0:
.long 0x40066666 # float 2.0999999
.LCPI1_1:
.long 0x404ccccd # float 3.20000005
.text
.globl _Z11fill_matrixPdjj
.type _Z11fill_matrixPdjj,@function
_Z11fill_matrixPdjj: # @_Z11fill_matrixPdjj
.cfi_startproc
# %bb.0:
testl %esi, %esi
je .LBB1_6
# %bb.1: # %.preheader.lr.ph
movl %edx, %eax
xorl %ecx, %ecx
movss .LCPI1_0(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero
movss .LCPI1_1(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero
xorl %r8d, %r8d
.LBB1_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB1_4 Depth 2
testl %edx, %edx
je .LBB1_5
# %bb.3: # %.lr.ph
# in Loop: Header=BB1_2 Depth=1
movl %r8d, %r9d
xorps %xmm2, %xmm2
cvtsi2ss %r9, %xmm2
mulss %xmm0, %xmm2
xorl %r9d, %r9d
.LBB1_4: # Parent Loop BB1_2 Depth=1
# => This Inner Loop Header: Depth=2
movl %r9d, %r10d
xorps %xmm3, %xmm3
cvtsi2ss %r10, %xmm3
mulss %xmm1, %xmm3
addss %xmm2, %xmm3
cvtss2sd %xmm3, %xmm3
leal (%rcx,%r9), %r10d
movsd %xmm3, (%rdi,%r10,8)
incq %r9
cmpq %r9, %rax
jne .LBB1_4
.LBB1_5: # %._crit_edge
# in Loop: Header=BB1_2 Depth=1
incl %r8d
addq %rax, %rcx
cmpl %esi, %r8d
jne .LBB1_2
.LBB1_6: # %._crit_edge15
retq
.Lfunc_end1:
.size _Z11fill_matrixPdjj, .Lfunc_end1-_Z11fill_matrixPdjj
.cfi_endproc
# -- End function
.globl _Z20print_matrix_to_filePdjj # -- Begin function _Z20print_matrix_to_filePdjj
.type _Z20print_matrix_to_filePdjj,@function
_Z20print_matrix_to_filePdjj: # @_Z20print_matrix_to_filePdjj
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $24, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %edx, %ebx
movl %esi, %ebp
movq %rdi, %r14
movl $.L.str.2, %edi
movl $.L.str.3, %esi
callq fopen
movq %rax, %r15
movl %ebp, 12(%rsp) # 4-byte Spill
testl %ebp, %ebp
je .LBB2_4
# %bb.1: # %.preheader.lr.ph
movl %ebx, %ecx
movl %ebx, %eax
movq %rax, 16(%rsp) # 8-byte Spill
xorl %ebx, %ebx
xorl %ebp, %ebp
movl %ecx, 8(%rsp) # 4-byte Spill
.LBB2_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB2_5 Depth 2
movq 16(%rsp), %r12 # 8-byte Reload
movl %ebx, %r13d
testl %ecx, %ecx
je .LBB2_3
.LBB2_5: # Parent Loop BB2_2 Depth=1
# => This Inner Loop Header: Depth=2
movl %r13d, %eax
movsd (%r14,%rax,8), %xmm0 # xmm0 = mem[0],zero
movl $.L.str.4, %esi
movq %r15, %rdi
movb $1, %al
callq fprintf
incl %r13d
decq %r12
jne .LBB2_5
.LBB2_3: # %._crit_edge
# in Loop: Header=BB2_2 Depth=1
movl $10, %edi
movq %r15, %rsi
callq fputc@PLT
incl %ebp
movl 8(%rsp), %ecx # 4-byte Reload
addl %ecx, %ebx
cmpl 12(%rsp), %ebp # 4-byte Folded Reload
jne .LBB2_2
.LBB2_4: # %._crit_edge17
movq %r15, %rdi
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
jmp fclose # TAILCALL
.Lfunc_end2:
.size _Z20print_matrix_to_filePdjj, .Lfunc_end2-_Z20print_matrix_to_filePdjj
.cfi_endproc
# -- End function
.globl _Z24__device_stub__matrixMulPdS_S_jjj # -- Begin function _Z24__device_stub__matrixMulPdS_S_jjj
.type _Z24__device_stub__matrixMulPdS_S_jjj,@function
_Z24__device_stub__matrixMulPdS_S_jjj: # @_Z24__device_stub__matrixMulPdS_S_jjj
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $144, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 56(%rsp), %rax
movq %rdi, (%rax)
leaq 48(%rsp), %rdi
movq %rsi, (%rdi)
leaq 40(%rsp), %rsi
movq %rdx, (%rsi)
leaq 20(%rsp), %rdx
movl %ecx, (%rdx)
leaq 16(%rsp), %rcx
movl %r8d, (%rcx)
leaq 12(%rsp), %r8
movl %r9d, (%r8)
leaq 96(%rsp), %rbx
movq %rax, (%rbx)
movq %rdi, 8(%rbx)
movq %rsi, 16(%rbx)
movq %rdx, 24(%rbx)
movq %rcx, 32(%rbx)
movq %r8, 40(%rbx)
leaq 80(%rsp), %r14
leaq 64(%rsp), %r15
leaq 32(%rsp), %r12
leaq 24(%rsp), %r13
movq %r14, %rdi
movq %r15, %rsi
movq %r12, %rdx
movq %r13, %rcx
callq __hipPopCallConfiguration
movq (%r14), %rsi
movl 8(%r14), %edx
movq (%r15), %rcx
movl 8(%r15), %r8d
movl $_Z9matrixMulPdS_S_jjj, %edi
movq %rbx, %r9
pushq (%r13)
.cfi_adjust_cfa_offset 8
pushq (%r12)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $160, %rsp
.cfi_adjust_cfa_offset -160
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size _Z24__device_stub__matrixMulPdS_S_jjj, .Lfunc_end3-_Z24__device_stub__matrixMulPdS_S_jjj
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI4_0:
.long 0x40066666 # float 2.0999999
.LCPI4_1:
.long 0x404ccccd # float 3.20000005
.LCPI4_2:
.long 0x447a0000 # float 1000
.text
.globl main
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $48, %rsp
.cfi_def_cfa_offset 96
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
cmpl $1, %edi
jne .LBB4_12
# %bb.1:
leaq 16(%rsp), %rdi
callq hipEventCreate
movq %rsp, %rdi
callq hipEventCreate
movl $268435456, %edi # imm = 0x10000000
callq malloc
movq %rax, %rbx
movl $1073741824, %edi # imm = 0x40000000
callq malloc
movq %rax, %r14
movl $536870912, %edi # imm = 0x20000000
callq malloc
movq %rax, %r15
xorl %eax, %eax
movss .LCPI4_0(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero
movss .LCPI4_1(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero
movq %rbx, %rcx
.LBB4_2: # %.preheader.i
# =>This Loop Header: Depth=1
# Child Loop BB4_3 Depth 2
movl %eax, %edx
xorps %xmm2, %xmm2
cvtsi2ss %rdx, %xmm2
mulss %xmm0, %xmm2
xorl %edx, %edx
.LBB4_3: # Parent Loop BB4_2 Depth=1
# => This Inner Loop Header: Depth=2
movl %edx, %esi
xorps %xmm3, %xmm3
cvtsi2ss %rsi, %xmm3
mulss %xmm1, %xmm3
addss %xmm2, %xmm3
cvtss2sd %xmm3, %xmm3
movsd %xmm3, (%rcx,%rdx,8)
incq %rdx
cmpq $8192, %rdx # imm = 0x2000
jne .LBB4_3
# %bb.4: # %._crit_edge.i
# in Loop: Header=BB4_2 Depth=1
incl %eax
addq $65536, %rcx # imm = 0x10000
cmpl $4096, %eax # imm = 0x1000
jne .LBB4_2
# %bb.5: # %.preheader.i26.preheader
xorl %eax, %eax
movq %r14, %rcx
.LBB4_6: # %.preheader.i26
# =>This Loop Header: Depth=1
# Child Loop BB4_7 Depth 2
movl %eax, %edx
xorps %xmm2, %xmm2
cvtsi2ss %rdx, %xmm2
mulss %xmm0, %xmm2
xorl %edx, %edx
.LBB4_7: # Parent Loop BB4_6 Depth=1
# => This Inner Loop Header: Depth=2
movl %edx, %esi
xorps %xmm3, %xmm3
cvtsi2ss %rsi, %xmm3
mulss %xmm1, %xmm3
addss %xmm2, %xmm3
cvtss2sd %xmm3, %xmm3
movsd %xmm3, (%rcx,%rdx,8)
incq %rdx
cmpq $16384, %rdx # imm = 0x4000
jne .LBB4_7
# %bb.8: # %._crit_edge.i31
# in Loop: Header=BB4_6 Depth=1
incl %eax
addq $131072, %rcx # imm = 0x20000
cmpl $8192, %eax # imm = 0x2000
jne .LBB4_6
# %bb.9: # %_Z11fill_matrixPdjj.exit33
leaq 32(%rsp), %r13
movl $268435456, %esi # imm = 0x10000000
movq %r13, %rdi
callq hipMalloc
movl %eax, %edi
movl $109, %esi
callq _Z13error_handler10hipError_ti
leaq 24(%rsp), %r12
movl $1073741824, %esi # imm = 0x40000000
movq %r12, %rdi
callq hipMalloc
movl %eax, %edi
movl $110, %esi
callq _Z13error_handler10hipError_ti
leaq 8(%rsp), %rdi
movl $536870912, %esi # imm = 0x20000000
callq hipMalloc
movl %eax, %edi
movl $111, %esi
callq _Z13error_handler10hipError_ti
movq (%r13), %rdi
movl $268435456, %edx # imm = 0x10000000
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movl %eax, %edi
movl $115, %esi
callq _Z13error_handler10hipError_ti
movq (%r12), %rdi
movl $1073741824, %edx # imm = 0x40000000
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movl %eax, %edi
movl $116, %esi
callq _Z13error_handler10hipError_ti
movq 16(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movabsq $1099511628800, %rdi # imm = 0x10000000400
movabsq $68719476752, %rdx # imm = 0x1000000010
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_11
# %bb.10:
movq 32(%rsp), %rdi
movq 24(%rsp), %rsi
movq 8(%rsp), %rdx
movl $4096, %ecx # imm = 0x1000
movl $16384, %r8d # imm = 0x4000
movl $8192, %r9d # imm = 0x2000
callq _Z24__device_stub__matrixMulPdS_S_jjj
.LBB4_11:
movq (%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 8(%rsp), %rsi
movl $536870912, %edx # imm = 0x20000000
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
movl %eax, %edi
movl $127, %esi
callq _Z13error_handler10hipError_ti
movq (%rsp), %rdi
callq hipEventSynchronize
leaq 44(%rsp), %r12
movl $0, (%r12)
movq 16(%rsp), %rsi
movq (%rsp), %rdx
movq %r12, %rdi
callq hipEventElapsedTime
movss (%r12), %xmm0 # xmm0 = mem[0],zero,zero,zero
divss .LCPI4_2(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movl $.L.str.7, %edi
movb $1, %al
callq printf
movq %r15, %rdi
movl $4096, %esi # imm = 0x1000
movl $16384, %edx # imm = 0x4000
callq _Z20print_matrix_to_filePdjj
movq 32(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
xorl %eax, %eax
addq $48, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB4_12:
.cfi_def_cfa_offset 96
movl $.Lstr, %edi
callq puts@PLT
movl $1, %edi
callq exit
.Lfunc_end4:
.size main, .Lfunc_end4-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
jne .LBB5_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, %rdi
movq %rax, __hip_gpubin_handle(%rip)
.LBB5_2:
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9matrixMulPdS_S_jjj, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end5:
.size __hip_module_ctor, .Lfunc_end5-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB6_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB6_2:
retq
.Lfunc_end6:
.size __hip_module_dtor, .Lfunc_end6-__hip_module_dtor
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%s in %s at line %d"
.size .L.str, 20
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/anantshah200/CS6023/master/Assignment2/ee16b105_6.hip"
.size .L.str.1, 111
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "assignment2_out"
.size .L.str.2, 16
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "a"
.size .L.str.3, 2
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "%4.4f "
.size .L.str.4, 7
.type _Z9matrixMulPdS_S_jjj,@object # @_Z9matrixMulPdS_S_jjj
.section .rodata,"a",@progbits
.globl _Z9matrixMulPdS_S_jjj
.p2align 3, 0x0
_Z9matrixMulPdS_S_jjj:
.quad _Z24__device_stub__matrixMulPdS_S_jjj
.size _Z9matrixMulPdS_S_jjj, 8
.type .L.str.7,@object # @.str.7
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.7:
.asciz "Run-Time(seconds) : %.4f"
.size .L.str.7, 25
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z9matrixMulPdS_S_jjj"
.size .L__unnamed_1, 22
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "error : Invalid number of arguments"
.size .Lstr, 36
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__matrixMulPdS_S_jjj
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9matrixMulPdS_S_jjj
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
```
| 5,695 | 7,511 |
166 |
Convert the following CUDA device assembly code to AMD device assembly:
```cudaasm
code for sm_80
Function : _Z12simpleKernelPfS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
MOV R1, c[0x0][0x28] ;
S2R R4, SR_CTAID.X ;
HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ;
ULDC.64 UR4, c[0x0][0x118] ;
S2R R3, SR_TID.X ;
IMAD R4, R4, c[0x0][0x0], R3 ;
IMAD.WIDE R2, R4, R5, c[0x0][0x168] ;
LDG.E R2, [R2.64] ;
IMAD.WIDE R4, R4, R5, c[0x0][0x160] ;
FMUL R7, R2, R2 ;
STG.E [R4.64], R7 ;
EXIT ;
BRA 0xc0;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
```
|
```amdasm
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z12simpleKernelPfS_ ; -- Begin function _Z12simpleKernelPfS_
.globl _Z12simpleKernelPfS_
.p2align 8
.type _Z12simpleKernelPfS_,@function
_Z12simpleKernelPfS_: ; @_Z12simpleKernelPfS_
; %bb.0:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x1c
s_load_b128 s[0:3], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
v_add_co_u32 v2, vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_load_b32 v2, v[2:3], off
s_waitcnt vmcnt(0)
v_mul_f32_e32 v2, v2, v2
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z12simpleKernelPfS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z12simpleKernelPfS_, .Lfunc_end0-_Z12simpleKernelPfS_
; -- End function
.section .AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 124
; NumSgprs: 18
; NumVgprs: 4
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 4
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object ; @__hip_cuid_
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0 ; 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z12simpleKernelPfS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z12simpleKernelPfS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
```
| 313 | 2,339 |
167 |
Convert the following CUDA host assembly code to AMD host assembly:
```cudaasm
.file "tmpxft_0000bb17_00000000-6_two_device_test.cudafe1.cpp"
.text
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z34__device_stub__Z12simpleKernelPfS_PfS_
.type _Z34__device_stub__Z12simpleKernelPfS_PfS_, @function
_Z34__device_stub__Z12simpleKernelPfS_PfS_:
.LFB2083:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z12simpleKernelPfS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z34__device_stub__Z12simpleKernelPfS_PfS_, .-_Z34__device_stub__Z12simpleKernelPfS_PfS_
.globl _Z12simpleKernelPfS_
.type _Z12simpleKernelPfS_, @function
_Z12simpleKernelPfS_:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z34__device_stub__Z12simpleKernelPfS_PfS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z12simpleKernelPfS_, .-_Z12simpleKernelPfS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%d: %f\n"
.text
.globl _Z7executev
.type _Z7executev, @function
_Z7executev:
.LFB2057:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $56, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movl $256, %edi
call malloc@PLT
movq %rax, %r12
movl $256, %edi
call malloc@PLT
movq %rax, %rbp
movq %rsp, %rdi
movl $256, %esi
call cudaMalloc@PLT
leaq 8(%rsp), %rdi
movl $256, %esi
call cudaMalloc@PLT
movl $0, %eax
.L12:
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movss %xmm0, (%r12,%rax,4)
addq $1, %rax
cmpq $64, %rax
jne .L12
movl $1, %ecx
movl $256, %edx
movq %r12, %rsi
movq (%rsp), %rdi
call cudaMemcpy@PLT
movl $64, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L19
.L13:
movl $2, %ecx
movl $256, %edx
movq 8(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
movl $0, %ebx
leaq .LC0(%rip), %r13
.L14:
pxor %xmm0, %xmm0
cvtss2sd 0(%rbp,%rbx,4), %xmm0
movl %ebx, %edx
movq %r13, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq $64, %rbx
jne .L14
movq 8(%rsp), %rdi
call cudaFree@PLT
movq (%rsp), %rdi
call cudaFree@PLT
movq %r12, %rdi
call free@PLT
movq %rbp, %rdi
call free@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L20
movl $0, %eax
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
movq (%rsp), %rsi
movq 8(%rsp), %rdi
call _Z34__device_stub__Z12simpleKernelPfS_PfS_
jmp .L13
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size _Z7executev, .-_Z7executev
.section .rodata.str1.1
.LC1:
.string "\nSetting device..."
.text
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq .LC1(%rip), %rbx
movq %rbx, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %edi
call cudaSetDevice@PLT
call _Z7executev
movq %rbx, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call cudaSetDevice@PLT
call _Z7executev
movl $0, %eax
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.1
.LC2:
.string "_Z12simpleKernelPfS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z12simpleKernelPfS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
```
|
```amdasm
.text
.file "two_device_test.hip"
.globl _Z27__device_stub__simpleKernelPfS_ # -- Begin function _Z27__device_stub__simpleKernelPfS_
.type _Z27__device_stub__simpleKernelPfS_,@function
_Z27__device_stub__simpleKernelPfS_: # @_Z27__device_stub__simpleKernelPfS_
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $80, %rsp
.cfi_def_cfa_offset 128
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 24(%rsp), %rax
movq %rdi, (%rax)
leaq 16(%rsp), %rcx
movq %rsi, (%rcx)
leaq 64(%rsp), %rbx
movq %rax, (%rbx)
movq %rcx, 8(%rbx)
leaq 48(%rsp), %r14
leaq 32(%rsp), %r15
leaq 8(%rsp), %r12
movq %rsp, %r13
movq %r14, %rdi
movq %r15, %rsi
movq %r12, %rdx
movq %r13, %rcx
callq __hipPopCallConfiguration
movq (%r14), %rsi
movl 8(%r14), %edx
movq (%r15), %rcx
movl 8(%r15), %r8d
movl $_Z12simpleKernelPfS_, %edi
movq %rbx, %r9
pushq (%r13)
.cfi_adjust_cfa_offset 8
pushq (%r12)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $96, %rsp
.cfi_adjust_cfa_offset -96
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z27__device_stub__simpleKernelPfS_, .Lfunc_end0-_Z27__device_stub__simpleKernelPfS_
.cfi_endproc
# -- End function
.globl _Z7executev # -- Begin function _Z7executev
.type _Z7executev,@function
_Z7executev: # @_Z7executev
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $16, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $256, %edi # imm = 0x100
callq malloc
movq %rax, %rbx
movl $256, %edi # imm = 0x100
callq malloc
movq %rax, %r14
leaq 8(%rsp), %rdi
movl $256, %esi # imm = 0x100
callq hipMalloc
movq %rsp, %rdi
movl $256, %esi # imm = 0x100
callq hipMalloc
xorl %eax, %eax
.LBB1_1: # =>This Inner Loop Header: Depth=1
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movss %xmm0, (%rbx,%rax,4)
incq %rax
cmpq $64, %rax
jne .LBB1_1
# %bb.2:
movq 8(%rsp), %rdi
movl $256, %edx # imm = 0x100
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 63(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq (%rsp), %rdi
movq 8(%rsp), %rsi
callq _Z27__device_stub__simpleKernelPfS_
.LBB1_4:
movq (%rsp), %rsi
movl $256, %edx # imm = 0x100
movq %r14, %rdi
movl $2, %ecx
callq hipMemcpy
xorl %r15d, %r15d
.LBB1_5: # =>This Inner Loop Header: Depth=1
xorps %xmm0, %xmm0
cvtss2sd (%r14,%r15,4), %xmm0
movl $.L.str, %edi
movl %r15d, %esi
movb $1, %al
callq printf
incq %r15
cmpq $64, %r15
jne .LBB1_5
# %bb.6:
movq (%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
xorl %eax, %eax
addq $16, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z7executev, .Lfunc_end1-_Z7executev
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
xorl %edi, %edi
callq hipSetDevice
callq _Z7executev
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
movl $1, %edi
callq hipSetDevice
callq _Z7executev
xorl %eax, %eax
popq %rcx
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, %rdi
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12simpleKernelPfS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z12simpleKernelPfS_,@object # @_Z12simpleKernelPfS_
.section .rodata,"a",@progbits
.globl _Z12simpleKernelPfS_
.p2align 3, 0x0
_Z12simpleKernelPfS_:
.quad _Z27__device_stub__simpleKernelPfS_
.size _Z12simpleKernelPfS_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%d: %f\n"
.size .L.str, 8
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "\nSetting device..."
.size .L.str.1, 19
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z12simpleKernelPfS_"
.size .L__unnamed_1, 21
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z27__device_stub__simpleKernelPfS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z12simpleKernelPfS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
```
| 3,194 | 3,299 |
170 |
Convert the following CUDA device assembly code to AMD device assembly:
```cudaasm
code for sm_80
Function : _Z11gen_normpdfiffPf
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ;
S2R R0, SR_CTAID.X ;
S2R R3, SR_TID.X ;
IMAD R0, R0, c[0x0][0x0], R3 ;
ISETP.GE.AND P0, PT, R0, c[0x0][0x160], PT ;
@P0 EXIT ;
I2F R2, R0 ;
IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x168] ;
MOV R4, 0x652b82fe ;
IMAD.MOV.U32 R5, RZ, RZ, 0x3ff71547 ;
MOV R11, 0x3e5ade15 ;
IMAD.MOV.U32 R10, RZ, RZ, 0x69ce2bdf ;
BSSY B0, 0x310 ;
FFMA R12, R2, R3, c[0x0][0x164] ;
F2F.F64.F32 R2, R12 ;
DMUL R2, R2, R2 ;
DMUL R2, R2, -0.5 ;
DFMA R4, R2, R4, 6.75539944105574400000e+15 ;
FSETP.GEU.AND P0, PT, |R3|, 4.1917929649353027344, PT ;
DADD R6, R4, -6.75539944105574400000e+15 ;
DFMA R8, R6, c[0x2][0x0], R2 ;
DFMA R6, R6, c[0x2][0x8], R8 ;
DFMA R8, R6, R10, c[0x2][0x10] ;
DFMA R8, R6, R8, c[0x2][0x18] ;
DFMA R8, R6, R8, c[0x2][0x20] ;
DFMA R8, R6, R8, c[0x2][0x28] ;
DFMA R8, R6, R8, c[0x2][0x30] ;
DFMA R8, R6, R8, c[0x2][0x38] ;
DFMA R8, R6, R8, c[0x2][0x40] ;
DFMA R8, R6, R8, c[0x2][0x48] ;
DFMA R8, R6, R8, c[0x2][0x50] ;
DFMA R8, R6, R8, 1 ;
DFMA R8, R6, R8, 1 ;
IMAD R7, R4, 0x100000, R9 ;
MOV R6, R8 ;
@!P0 BRA 0x300 ;
FSETP.GEU.AND P1, PT, |R3|, 4.2275390625, PT ;
DADD R6, R2, +INF ;
DSETP.GEU.AND P0, PT, R2, RZ, PT ;
FSEL R6, R6, RZ, P0 ;
@!P1 LEA.HI R5, R4, R4, RZ, 0x1 ;
FSEL R7, R7, RZ, P0 ;
@!P1 SHF.R.S32.HI R5, RZ, 0x1, R5 ;
@!P1 LEA R9, R5, R9, 0x14 ;
@!P1 IMAD.IADD R2, R4, 0x1, -R5 ;
@!P1 LEA R3, R2, 0x3ff00000, 0x14 ;
@!P1 IMAD.MOV.U32 R2, RZ, RZ, RZ ;
@!P1 DMUL R6, R8, R2 ;
BSYNC B0 ;
DMUL R6, R6, c[0x2][0x58] ;
MOV R3, 0x4 ;
ULDC.64 UR4, c[0x0][0x118] ;
IMAD.WIDE R2, R0, R3, c[0x0][0x170] ;
F2F.F32.F64 R7, R6 ;
STG.E [R2.64], R7 ;
EXIT ;
BRA 0x380;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
Function : _Z11gen_normpdfiddPd
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ;
S2R R0, SR_CTAID.X ;
S2R R3, SR_TID.X ;
IMAD R0, R0, c[0x0][0x0], R3 ;
ISETP.GE.AND P0, PT, R0, c[0x0][0x160], PT ;
@P0 EXIT ;
I2F.F64 R2, R0 ;
IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x170] ;
MOV R5, c[0x0][0x174] ;
IMAD.MOV.U32 R11, RZ, RZ, 0x3e5ade15 ;
MOV R10, 0x69ce2bdf ;
BSSY B0, 0x320 ;
DFMA R2, R2, R4, c[0x0][0x168] ;
IMAD.MOV.U32 R4, RZ, RZ, 0x652b82fe ;
IMAD.MOV.U32 R5, RZ, RZ, 0x3ff71547 ;
DMUL R2, R2, R2 ;
DMUL R2, R2, -0.5 ;
DFMA R4, R2, R4, 6.75539944105574400000e+15 ;
FSETP.GEU.AND P0, PT, |R3|, 4.1917929649353027344, PT ;
DADD R6, R4, -6.75539944105574400000e+15 ;
DFMA R8, R6, c[0x2][0x0], R2 ;
DFMA R6, R6, c[0x2][0x8], R8 ;
DFMA R8, R6, R10, c[0x2][0x10] ;
MOV R11, 0x8 ;
DFMA R8, R6, R8, c[0x2][0x18] ;
DFMA R8, R6, R8, c[0x2][0x20] ;
DFMA R8, R6, R8, c[0x2][0x28] ;
DFMA R8, R6, R8, c[0x2][0x30] ;
DFMA R8, R6, R8, c[0x2][0x38] ;
DFMA R8, R6, R8, c[0x2][0x40] ;
DFMA R8, R6, R8, c[0x2][0x48] ;
DFMA R8, R6, R8, c[0x2][0x50] ;
DFMA R8, R6, R8, 1 ;
DFMA R8, R6, R8, 1 ;
IMAD R7, R4, 0x100000, R9 ;
IMAD.MOV.U32 R6, RZ, RZ, R8 ;
@!P0 BRA 0x310 ;
FSETP.GEU.AND P1, PT, |R3|, 4.2275390625, PT ;
DADD R6, R2, +INF ;
DSETP.GEU.AND P0, PT, R2, RZ, PT ;
FSEL R6, R6, RZ, P0 ;
@!P1 LEA.HI R5, R4, R4, RZ, 0x1 ;
FSEL R7, R7, RZ, P0 ;
@!P1 SHF.R.S32.HI R5, RZ, 0x1, R5 ;
@!P1 IADD3 R2, R4, -R5, RZ ;
@!P1 IMAD R9, R5, 0x100000, R9 ;
@!P1 LEA R3, R2, 0x3ff00000, 0x14 ;
@!P1 MOV R2, RZ ;
@!P1 DMUL R6, R8, R2 ;
BSYNC B0 ;
DMUL R6, R6, c[0x2][0x58] ;
IMAD.WIDE R2, R0, R11, c[0x0][0x178] ;
ULDC.64 UR4, c[0x0][0x118] ;
STG.E.64 [R2.64], R6 ;
EXIT ;
BRA 0x370;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
```
|
```amdasm
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object ; @__hip_cuid_
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0 ; 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
```
| 2,398 | 306 |
171 |
Convert the following CUDA host assembly code to AMD host assembly:
```cudaasm
.file "tmpxft_001afdbb_00000000-6_helper_functions.cudafe1.cpp"
.text
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2031:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2031:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z7normpdfdd
.type _Z7normpdfdd, @function
_Z7normpdfdd:
.LFB2027:
.cfi_startproc
endbr64
subq $24, %rsp
.cfi_def_cfa_offset 32
movsd %xmm1, 8(%rsp)
divsd %xmm1, %xmm0
movapd %xmm0, %xmm1
xorpd .LC0(%rip), %xmm1
mulsd %xmm1, %xmm0
mulsd .LC1(%rip), %xmm0
call exp@PLT
mulsd .LC2(%rip), %xmm0
divsd 8(%rsp), %xmm0
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2027:
.size _Z7normpdfdd, .-_Z7normpdfdd
.globl _Z7normpdfff
.type _Z7normpdfff, @function
_Z7normpdfff:
.LFB2028:
.cfi_startproc
endbr64
subq $24, %rsp
.cfi_def_cfa_offset 32
movss %xmm1, 12(%rsp)
divss %xmm1, %xmm0
movaps %xmm0, %xmm3
xorps .LC3(%rip), %xmm3
mulss %xmm3, %xmm0
mulss .LC4(%rip), %xmm0
call expf@PLT
cvtss2sd %xmm0, %xmm0
mulsd .LC2(%rip), %xmm0
pxor %xmm1, %xmm1
cvtss2sd 12(%rsp), %xmm1
divsd %xmm1, %xmm0
cvtsd2ss %xmm0, %xmm0
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2028:
.size _Z7normpdfff, .-_Z7normpdfff
.globl _Z34__device_stub__Z11gen_normpdfiddPdiddPd
.type _Z34__device_stub__Z11gen_normpdfiddPdiddPd, @function
_Z34__device_stub__Z11gen_normpdfiddPdiddPd:
.LFB2053:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 28(%rsp)
movsd %xmm0, 16(%rsp)
movsd %xmm1, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L11
.L7:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L12
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z11gen_normpdfiddPd(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L7
.L12:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2053:
.size _Z34__device_stub__Z11gen_normpdfiddPdiddPd, .-_Z34__device_stub__Z11gen_normpdfiddPdiddPd
.globl _Z11gen_normpdfiddPd
.type _Z11gen_normpdfiddPd, @function
_Z11gen_normpdfiddPd:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z34__device_stub__Z11gen_normpdfiddPdiddPd
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _Z11gen_normpdfiddPd, .-_Z11gen_normpdfiddPd
.globl _Z34__device_stub__Z11gen_normpdfiffPfiffPf
.type _Z34__device_stub__Z11gen_normpdfiffPfiffPf, @function
_Z34__device_stub__Z11gen_normpdfiffPfiffPf:
.LFB2055:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 28(%rsp)
movss %xmm0, 24(%rsp)
movss %xmm1, 20(%rsp)
movq %rsi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 24(%rsp), %rax
movq %rax, 104(%rsp)
leaq 20(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L19
.L15:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L20
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z11gen_normpdfiffPf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L15
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2055:
.size _Z34__device_stub__Z11gen_normpdfiffPfiffPf, .-_Z34__device_stub__Z11gen_normpdfiffPfiffPf
.globl _Z11gen_normpdfiffPf
.type _Z11gen_normpdfiffPf, @function
_Z11gen_normpdfiffPf:
.LFB2056:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z34__device_stub__Z11gen_normpdfiffPfiffPf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2056:
.size _Z11gen_normpdfiffPf, .-_Z11gen_normpdfiffPf
.section .rodata.str1.1,"aMS",@progbits,1
.LC5:
.string "_Z11gen_normpdfiffPf"
.LC6:
.string "_Z11gen_normpdfiddPd"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2058:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _Z11gen_normpdfiffPf(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _Z11gen_normpdfiddPd(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst16,"aM",@progbits,16
.align 16
.LC0:
.long 0
.long -2147483648
.long 0
.long 0
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC1:
.long 0
.long 1071644672
.align 8
.LC2:
.long 869545558
.long 1071220805
.section .rodata.cst16
.align 16
.LC3:
.long -2147483648
.long 0
.long 0
.long 0
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC4:
.long 1056964608
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
```
|
```amdasm
.text
.file "helper_functions.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
```
| 3,741 | 184 |
172 |
Convert the following CUDA device assembly code to AMD device assembly:
```cudaasm
code for sm_80
```
|
```amdasm
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object ; @__hip_cuid_
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0 ; 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
```
| 24 | 306 |
173 |
Convert the following CUDA host assembly code to AMD host assembly:
```cudaasm
.file "tmpxft_00081a81_00000000-6_MockElementKernel.cudafe1.cpp"
.text
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
```
|
```amdasm
.text
.file "MockElementKernel.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
```
| 749 | 185 |
178 |
Convert the following CUDA device assembly code to AMD device assembly:
```cudaasm
code for sm_80
Function : _Z3incv
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
MOV R1, c[0x0][0x28] ;
S2R R2, SR_CTAID.X ;
HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ;
ULDC.64 UR4, c[0x0][0x118] ;
IMAD.WIDE R2, R2, R3, c[0x4][0x8] ;
LDG.E R0, [R2.64] ;
IADD3 R5, R0, 0x1, RZ ;
STG.E [R2.64], R5 ;
EXIT ;
BRA 0x90;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
Function : _Z18helloWorldOnDevicev
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
MOV R1, c[0x0][0x28] ;
S2R R6, SR_CTAID.X ;
HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ;
ULDC.64 UR4, c[0x0][0x118] ;
LDC.U8 R7, c[0x3][R6] ;
IADD3 R4, P0, R6, c[0x4][0x0], RZ ;
IMAD.WIDE R2, R6.reuse, R3, c[0x4][0x8] ;
LEA.HI.X.SX32 R5, R6, c[0x4][0x4], 0x1, P0 ;
STG.E.U8 [R4.64], R7 ;
LDG.E R0, [R2.64] ;
IMAD R9, R0, R0, RZ ;
STG.E [R2.64], R9 ;
EXIT ;
BRA 0xd0;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
```
|
```amdasm
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z18helloWorldOnDevicev ; -- Begin function _Z18helloWorldOnDevicev
.globl _Z18helloWorldOnDevicev
.p2align 8
.type _Z18helloWorldOnDevicev,@function
_Z18helloWorldOnDevicev: ; @_Z18helloWorldOnDevicev
; %bb.0:
s_getpc_b64 s[2:3]
s_add_u32 s2, s2, hw@rel32@lo+4
s_addc_u32 s3, s3, hw@rel32@hi+12
v_mov_b32_e32 v0, 0
s_ashr_i32 s1, s15, 31
s_add_u32 s2, s15, s2
s_addc_u32 s3, s1, s3
s_mov_b32 s0, s15
global_load_u8 v1, v0, s[2:3]
s_getpc_b64 s[2:3]
s_add_u32 s2, s2, name_device@rel32@lo+4
s_addc_u32 s3, s3, name_device@rel32@hi+12
s_add_u32 s2, s15, s2
s_addc_u32 s3, s1, s3
s_getpc_b64 s[4:5]
s_add_u32 s4, s4, tab_d@rel32@lo+4
s_addc_u32 s5, s5, tab_d@rel32@hi+12
s_lshl_b64 s[0:1], s[0:1], 2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
s_add_u32 s0, s0, s4
s_addc_u32 s1, s1, s5
s_load_b32 s4, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_mul_i32 s4, s4, s4
v_mov_b32_e32 v2, s4
s_waitcnt vmcnt(0)
s_clause 0x1
global_store_b8 v0, v1, s[2:3]
global_store_b32 v0, v2, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z18helloWorldOnDevicev
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 0
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 0
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 16
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z18helloWorldOnDevicev, .Lfunc_end0-_Z18helloWorldOnDevicev
; -- End function
.section .AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 168
; NumSgprs: 16
; NumVgprs: 3
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 1
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 16
; NumVGPRsForWavesPerEU: 3
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
.text
.protected _Z3incv ; -- Begin function _Z3incv
.globl _Z3incv
.p2align 8
.type _Z3incv,@function
_Z3incv: ; @_Z3incv
; %bb.0:
s_getpc_b64 s[2:3]
s_add_u32 s2, s2, tab_d@rel32@lo+4
s_addc_u32 s3, s3, tab_d@rel32@hi+12
s_mov_b32 s0, s15
s_ashr_i32 s1, s15, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_lshl_b64 s[0:1], s[0:1], 2
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
s_load_b32 s2, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_add_i32 s2, s2, 1
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
global_store_b32 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3incv
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 0
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 0
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 16
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z3incv, .Lfunc_end1-_Z3incv
; -- End function
.section .AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 92
; NumSgprs: 16
; NumVgprs: 2
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 1
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 16
; NumVGPRsForWavesPerEU: 2
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.protected name_device ; @name_device
.type name_device,@object
.section .bss,"aw",@nobits
.globl name_device
name_device:
.zero 14
.size name_device, 14
.protected tab_d ; @tab_d
.type tab_d,@object
.globl tab_d
.p2align 4, 0x0
tab_d:
.zero 56
.size tab_d, 56
.protected hw ; @hw
.type hw,@object
.data
.globl hw
hw:
.asciz "Hello World!\n"
.size hw, 14
.type __hip_cuid_,@object ; @__hip_cuid_
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0 ; 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym name_device
.addrsig_sym tab_d
.addrsig_sym hw
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args: []
.group_segment_fixed_size: 0
.kernarg_segment_align: 4
.kernarg_segment_size: 0
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z18helloWorldOnDevicev
.private_segment_fixed_size: 0
.sgpr_count: 16
.sgpr_spill_count: 0
.symbol: _Z18helloWorldOnDevicev.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args: []
.group_segment_fixed_size: 0
.kernarg_segment_align: 4
.kernarg_segment_size: 0
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3incv
.private_segment_fixed_size: 0
.sgpr_count: 16
.sgpr_spill_count: 0
.symbol: _Z3incv.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
```
| 584 | 3,627 |
179 |
Convert the following CUDA host assembly code to AMD host assembly:
```cudaasm
.file "tmpxft_00064642_00000000-6_app2_back1.cudafe1.cpp"
.text
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z37__device_stub__Z18helloWorldOnDevicevv
.type _Z37__device_stub__Z18helloWorldOnDevicevv, @function
_Z37__device_stub__Z18helloWorldOnDevicevv:
.LFB2082:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z18helloWorldOnDevicev(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z37__device_stub__Z18helloWorldOnDevicevv, .-_Z37__device_stub__Z18helloWorldOnDevicevv
.globl _Z18helloWorldOnDevicev
.type _Z18helloWorldOnDevicev, @function
_Z18helloWorldOnDevicev:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z37__device_stub__Z18helloWorldOnDevicevv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z18helloWorldOnDevicev, .-_Z18helloWorldOnDevicev
.globl _Z21__device_stub__Z3incvv
.type _Z21__device_stub__Z3incvv, @function
_Z21__device_stub__Z3incvv:
.LFB2084:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z3incv(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z21__device_stub__Z3incvv, .-_Z21__device_stub__Z3incvv
.globl _Z3incv
.type _Z3incv, @function
_Z3incv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z21__device_stub__Z3incvv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z3incv, .-_Z3incv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "\n\nGot from GPU: %s\n"
.LC1:
.string "Hello World!\n"
.LC2:
.string "Hello test: PASSED\n"
.LC3:
.string "Hello test: FAILED\n"
.LC4:
.string "FAILED!\n"
.LC5:
.string "tab_h1[%d] = %d\n"
.LC6:
.string "tab_d"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $184, %rsp
.cfi_def_cfa_offset 208
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
.L20:
movl %eax, 32(%rsp,%rax,4)
addq $1, %rax
cmpq $14, %rax
jne .L20
leaq 32(%rsp), %rsi
movl $1, %r8d
movl $0, %ecx
movl $56, %edx
leaq _ZL5tab_d(%rip), %rdi
call cudaMemcpyToSymbol@PLT
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $14, 8(%rsp)
movl $1, 12(%rsp)
movl $1, 16(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L36
.L21:
call cudaThreadSynchronize@PLT
leaq 154(%rsp), %rbx
movl $2, %r8d
movl $0, %ecx
movl $13, %edx
leaq _ZL11name_device(%rip), %rsi
movq %rbx, %rdi
call cudaMemcpyFromSymbol@PLT
leaq 96(%rsp), %rdi
movl $2, %r8d
movl $0, %ecx
movl $56, %edx
leaq _ZL5tab_d(%rip), %rsi
call cudaMemcpyFromSymbol@PLT
movq %rbx, %rdx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC1(%rip), %rsi
movq %rbx, %rdi
call strcmp@PLT
testl %eax, %eax
jne .L22
leaq .LC2(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
.L24:
movl $0, %ebx
leaq .LC5(%rip), %rbp
.L23:
movl %ebx, %edx
movl 96(%rsp,%rbx,4), %ecx
movl 32(%rsp,%rbx,4), %eax
imull %eax, %eax
cmpl %eax, %ecx
jne .L37
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq $14, %rbx
jne .L23
.L26:
leaq 32(%rsp), %rsi
movl $1, %r8d
movl $0, %ecx
movl $56, %edx
leaq .LC6(%rip), %rdi
call cudaMemcpyToSymbol@PLT
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $14, 8(%rsp)
movl $1, 12(%rsp)
movl $1, 16(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L38
.L27:
call cudaThreadSynchronize@PLT
leaq 96(%rsp), %rdi
movl $2, %r8d
movl $0, %ecx
movl $56, %edx
leaq .LC6(%rip), %rsi
call cudaMemcpyFromSymbol@PLT
movl $0, %ebx
leaq .LC5(%rip), %rbp
.L30:
movl %ebx, %edx
movl 96(%rsp,%rbx,4), %ecx
movl 32(%rsp,%rbx,4), %eax
addl $1, %eax
cmpl %eax, %ecx
jne .L39
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq $14, %rbx
jne .L30
.L29:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L40
movl $0, %eax
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L36:
.cfi_restore_state
call _Z37__device_stub__Z18helloWorldOnDevicevv
jmp .L21
.L22:
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L24
.L37:
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L26
.L38:
call _Z21__device_stub__Z3incvv
jmp .L27
.L39:
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L29
.L40:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC7:
.string "_Z3incv"
.LC8:
.string "_Z18helloWorldOnDevicev"
.LC9:
.string "name_device"
.LC10:
.string "hw"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _Z3incv(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _Z18helloWorldOnDevicev(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $14, %r9d
movl $0, %r8d
leaq .LC9(%rip), %rdx
movq %rdx, %rcx
leaq _ZL11name_device(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $56, %r9d
movl $0, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _ZL5tab_d(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $14, %r9d
movl $0, %r8d
leaq .LC10(%rip), %rdx
movq %rdx, %rcx
leaq _ZL2hw(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZL2hw
.comm _ZL2hw,14,8
.local _ZL5tab_d
.comm _ZL5tab_d,56,32
.local _ZL11name_device
.comm _ZL11name_device,14,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
```
|
```amdasm
.text
.file "app2_back1.hip"
.globl _Z33__device_stub__helloWorldOnDevicev # -- Begin function _Z33__device_stub__helloWorldOnDevicev
.type _Z33__device_stub__helloWorldOnDevicev,@function
_Z33__device_stub__helloWorldOnDevicev: # @_Z33__device_stub__helloWorldOnDevicev
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $56, %rsp
.cfi_def_cfa_offset 96
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 40(%rsp), %rbx
leaq 24(%rsp), %r14
leaq 16(%rsp), %r15
leaq 8(%rsp), %r12
movq %rbx, %rdi
movq %r14, %rsi
movq %r15, %rdx
movq %r12, %rcx
callq __hipPopCallConfiguration
movq (%rbx), %rsi
movl 8(%rbx), %edx
movq (%r14), %rcx
movl 8(%r14), %r8d
movq %rsp, %r9
movl $_Z18helloWorldOnDevicev, %edi
pushq (%r12)
.cfi_adjust_cfa_offset 8
pushq (%r15)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z33__device_stub__helloWorldOnDevicev, .Lfunc_end0-_Z33__device_stub__helloWorldOnDevicev
.cfi_endproc
# -- End function
.globl _Z18__device_stub__incv # -- Begin function _Z18__device_stub__incv
.type _Z18__device_stub__incv,@function
_Z18__device_stub__incv: # @_Z18__device_stub__incv
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $56, %rsp
.cfi_def_cfa_offset 96
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 40(%rsp), %rbx
leaq 24(%rsp), %r14
leaq 16(%rsp), %r15
leaq 8(%rsp), %r12
movq %rbx, %rdi
movq %r14, %rsi
movq %r15, %rdx
movq %r12, %rcx
callq __hipPopCallConfiguration
movq (%rbx), %rsi
movl 8(%rbx), %edx
movq (%r14), %rcx
movl 8(%r14), %r8d
movq %rsp, %r9
movl $_Z3incv, %edi
pushq (%r12)
.cfi_adjust_cfa_offset 8
pushq (%r15)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z18__device_stub__incv, .Lfunc_end1-_Z18__device_stub__incv
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $144, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
xorl %eax, %eax
.LBB2_1: # =>This Inner Loop Header: Depth=1
movl %eax, (%rsp,%rax,4)
incq %rax
cmpq $14, %rax
jne .LBB2_1
# %bb.2:
movabsq $4294967297, %rbx # imm = 0x100000001
movq %rsp, %rsi
movl $tab_d, %edi
movl $56, %edx
xorl %ecx, %ecx
movl $1, %r8d
callq hipMemcpyToSymbol
leaq 13(%rbx), %r14
movq %r14, %rdi
movl $1, %esi
movq %rbx, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_4
# %bb.3:
callq _Z33__device_stub__helloWorldOnDevicev
.LBB2_4:
callq hipDeviceSynchronize
leaq 130(%rsp), %r15
movl $name_device, %esi
movl $13, %edx
movq %r15, %rdi
xorl %ecx, %ecx
movl $2, %r8d
callq hipMemcpyFromSymbol
leaq 64(%rsp), %rdi
movl $tab_d, %esi
movl $56, %edx
xorl %ecx, %ecx
movl $2, %r8d
callq hipMemcpyFromSymbol
movl $.L.str, %edi
movq %r15, %rsi
xorl %eax, %eax
callq printf
movabsq $8022916924116329800, %rax # imm = 0x6F57206F6C6C6548
xorq (%r15), %rax
movabsq $2851464966991703, %rcx # imm = 0xA21646C726F57
xorq 6(%r15), %rcx
orq %rax, %rcx
movl $.Lstr.1, %eax
movl $.Lstr, %edi
cmoveq %rax, %rdi
callq puts@PLT
xorl %r15d, %r15d
.LBB2_5: # =>This Inner Loop Header: Depth=1
movl 64(%rsp,%r15,4), %edx
movl (%rsp,%r15,4), %eax
imull %eax, %eax
cmpl %eax, %edx
jne .LBB2_6
# %bb.7: # in Loop: Header=BB2_5 Depth=1
movl $.L.str.5, %edi
movl %r15d, %esi
xorl %eax, %eax
callq printf
incq %r15
cmpq $14, %r15
jne .LBB2_5
jmp .LBB2_8
.LBB2_6:
movl $.Lstr.3, %edi
callq puts@PLT
.LBB2_8: # %.loopexit41
movq %rsp, %rsi
movl $.L.str.6, %edi
movl $56, %edx
xorl %ecx, %ecx
movl $1, %r8d
callq hipMemcpyToSymbol
movq %r14, %rdi
movl $1, %esi
movq %rbx, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_10
# %bb.9:
callq _Z18__device_stub__incv
.LBB2_10:
callq hipDeviceSynchronize
leaq 64(%rsp), %rdi
movl $.L.str.6, %esi
movl $56, %edx
xorl %ecx, %ecx
movl $2, %r8d
callq hipMemcpyFromSymbol
xorl %ebx, %ebx
.LBB2_11: # =>This Inner Loop Header: Depth=1
movl 64(%rsp,%rbx,4), %edx
movl (%rsp,%rbx,4), %eax
incl %eax
cmpl %eax, %edx
jne .LBB2_12
# %bb.13: # in Loop: Header=BB2_11 Depth=1
movl $.L.str.5, %edi
movl %ebx, %esi
xorl %eax, %eax
callq printf
incq %rbx
cmpq $14, %rbx
jne .LBB2_11
jmp .LBB2_14
.LBB2_12:
movl $.Lstr.3, %edi
callq puts@PLT
.LBB2_14: # %.loopexit
xorl %eax, %eax
addq $144, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
movq __hip_gpubin_handle(%rip), %rbx
testq %rbx, %rbx
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, %rbx
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z18helloWorldOnDevicev, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3incv, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $0, 8(%rsp)
movl $0, (%rsp)
movl $name_device, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movl $14, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
callq __hipRegisterVar
movl $0, 8(%rsp)
movl $0, (%rsp)
movl $tab_d, %esi
movl $.L.str.6, %edx
movl $.L.str.6, %ecx
movl $56, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
callq __hipRegisterVar
movl $0, 8(%rsp)
movl $1, (%rsp)
movl $hw, %esi
movl $.L__unnamed_4, %edx
movl $.L__unnamed_4, %ecx
movl $14, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
callq __hipRegisterVar
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type name_device,@object # @name_device
.local name_device
.comm name_device,14,1
.type tab_d,@object # @tab_d
.local tab_d
.comm tab_d,56,16
.type hw,@object # @hw
.local hw
.comm hw,14,1
.type _Z18helloWorldOnDevicev,@object # @_Z18helloWorldOnDevicev
.section .rodata,"a",@progbits
.globl _Z18helloWorldOnDevicev
.p2align 3, 0x0
_Z18helloWorldOnDevicev:
.quad _Z33__device_stub__helloWorldOnDevicev
.size _Z18helloWorldOnDevicev, 8
.type _Z3incv,@object # @_Z3incv
.globl _Z3incv
.p2align 3, 0x0
_Z3incv:
.quad _Z18__device_stub__incv
.size _Z3incv, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "\n\nGot from GPU: %s\n"
.size .L.str, 20
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Hello World!\n"
.size .L.str.1, 14
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "tab_h1[%d] = %d\n"
.size .L.str.5, 17
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "tab_d"
.size .L.str.6, 6
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z18helloWorldOnDevicev"
.size .L__unnamed_1, 24
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z3incv"
.size .L__unnamed_2, 8
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "name_device"
.size .L__unnamed_3, 12
.type .L__unnamed_4,@object # @3
.L__unnamed_4:
.asciz "hw"
.size .L__unnamed_4, 3
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Hello test: FAILED"
.size .Lstr, 19
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "Hello test: PASSED"
.size .Lstr.1, 19
.type .Lstr.3,@object # @str.3
.Lstr.3:
.asciz "FAILED!"
.size .Lstr.3, 8
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z33__device_stub__helloWorldOnDevicev
.addrsig_sym _Z18__device_stub__incv
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym name_device
.addrsig_sym tab_d
.addrsig_sym hw
.addrsig_sym _Z18helloWorldOnDevicev
.addrsig_sym _Z3incv
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
```
| 4,905 | 5,194 |
180 |
Convert the following CUDA device assembly code to AMD device assembly:
```cudaasm
code for sm_80
Function : _Z10ddftKerneljjP7double2S0_S0_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ;
UMOV UR6, 0x1 ;
ULDC UR4, c[0x0][0x160] ;
USHF.L.U32 UR6, UR6, UR4, URZ ;
USHF.R.S32.HI UR7, URZ, 0x1f, UR6 ;
ISETP.NE.U32.AND P0, PT, RZ, UR7, PT ;
@!P0 BRA 0xc0 ;
MOV R0, 0x90 ;
CALL.REL.NOINC 0xde0 ;
IMAD.MOV.U32 R2, RZ, RZ, R4 ;
IMAD.MOV.U32 R3, RZ, RZ, R5 ;
BRA 0x220 ;
I2F.U32.RP R0, c[0x0][0x164] ;
ULDC UR9, c[0x0][0x164] ;
IMAD.MOV.U32 R3, RZ, RZ, RZ ;
UMOV UR4, URZ ;
UISETP.NE.U32.AND UP2, UPT, URZ, UR9, UPT ;
MUFU.RCP R0, R0 ;
IADD3 R2, R0, 0xffffffe, RZ ;
F2I.FTZ.U32.TRUNC.NTZ R2, R2 ;
R2UR UR5, R2 ;
UIADD3 UR8, URZ, -UR5, URZ ;
UIMAD UR8, UR8, UR9, URZ ;
UIMAD.WIDE.U32 UR4, UR5, UR8, UR4 ;
UIMAD.WIDE.U32 UR4, UR5, UR6, URZ ;
UIADD3 UR4, -UR5, URZ, URZ ;
UIMAD UR4, UR4, UR9, UR6 ;
UISETP.GE.U32.AND UP0, UPT, UR4, UR9, UPT ;
@UP0 UIADD3 UR4, UR4, -UR9, URZ ;
@UP0 UIADD3 UR5, UR5, 0x1, URZ ;
UISETP.GE.U32.AND UP1, UPT, UR4, UR9, UPT ;
@UP1 UIADD3 UR5, UR5, 0x1, URZ ;
@!UP2 ULOP3.LUT UR5, URZ, UR9, URZ, 0x33, !UPT ;
IMAD.U32 R2, RZ, RZ, UR5 ;
S2R R5, SR_TID.X ;
IADD3 R7, P0, R5, 0x1, RZ ;
IMAD.X R9, RZ, RZ, RZ, P0 ;
IMAD R0, R3, R7.reuse, RZ ;
IMAD R3, R5, R2, RZ ;
IMAD.WIDE.U32 R6, R2, R7, RZ ;
SHF.R.S32.HI R5, RZ, 0x1f, R3 ;
IMAD R9, R2, R9, R0 ;
ISETP.GT.U32.AND P0, PT, R6, R3, PT ;
IMAD.IADD R4, R7, 0x1, R9 ;
ISETP.GT.AND.EX P0, PT, R4, R5, PT, P0 ;
@!P0 EXIT ;
UISETP.GT.AND UP0, UPT, UR6, 0x1, UPT ;
IMAD.MOV.U32 R2, RZ, RZ, R3 ;
ULDC.64 UR4, c[0x0][0x170] ;
ULEA UR4, UP1, UR6, UR4, 0x4 ;
PLOP3.LUT P0, PT, PT, PT, UP0, 0x80, 0x0 ;
ULDC.64 UR12, c[0x0][0x118] ;
ULEA.HI.X UR5, UR6, UR5, UR7, 0x4, UP1 ;
IMAD.U32 R8, RZ, RZ, UR4 ;
UIADD3 UR6, UP0, UR6, -0x1, URZ ;
IMAD.U32 R9, RZ, RZ, UR5 ;
UIADD3.X UR9, UR7, -0x1, URZ, UP0, !UPT ;
@P0 BRA 0x450 ;
LDG.E.128 R12, [R8.64+-0x10] ;
LEA R10, P0, R2, c[0x0][0x168], 0x4 ;
LEA.HI.X R11, R2, c[0x0][0x16c], R5, 0x4, P0 ;
IADD3 R2, R3, 0x1, RZ ;
ISETP.GT.U32.AND P0, PT, R6, R2, PT ;
IMAD.MOV.U32 R3, RZ, RZ, R2.reuse ;
SHF.R.S32.HI R5, RZ, 0x1f, R2 ;
ISETP.GT.AND.EX P0, PT, R4, R5, PT, P0 ;
STG.E.128 [R10.64], R12 ;
@P0 BRA 0x3a0 ;
EXIT ;
UMOV UR4, 0x1 ;
ULDC UR5, c[0x0][0x160] ;
ULOP3.LUT UR15, UR6, 0x3, URZ, 0xc0, !UPT ;
USHF.L.U32 UR4, UR4, UR5, URZ ;
UIADD3 UR8, UP0, -UR15, UR6, URZ ;
UIADD3 UR14, UP1, UR4, -0x2, URZ ;
UIADD3.X UR9, UR9, -0x1, URZ, UP0, !UPT ;
ULEA.HI.X.SX32 UR6, UR4, 0xffffffff, 0x1, UP1 ;
LDG.E.128 R12, [R8.64+-0x10] ;
IMAD.SHL.U32 R22, R2.reuse, 0x10, RZ ;
SHF.L.U64.HI R16, R2, 0x4, R5 ;
UISETP.GE.U32.AND UP0, UPT, UR14, 0x3, UPT ;
IMAD.MOV.U32 R0, RZ, RZ, RZ ;
IADD3 R10, P0, R22.reuse, c[0x0][0x168], RZ ;
UISETP.GE.U32.AND.EX UP0, UPT, UR6, URZ, UPT, UP0 ;
IADD3 R22, P1, R22, c[0x0][0x178], RZ ;
IADD3.X R11, R16.reuse, c[0x0][0x16c], RZ, P0, !PT ;
ISETP.NE.U32.AND P0, PT, RZ, UR15, PT ;
PLOP3.LUT P2, PT, PT, PT, UP0, 0x80, 0x0 ;
ISETP.NE.AND.EX P0, PT, RZ, RZ, PT, P0 ;
IADD3.X R23, R16, c[0x0][0x17c], RZ, P1, !PT ;
STG.E.128 [R10.64], R12 ;
@!P2 BRA 0x9d0 ;
LDG.E.64 R22, [R22.64] ;
LEA R16, P1, R2, c[0x0][0x178], 0x4 ;
IMAD.MOV.U32 R0, RZ, RZ, RZ ;
IMAD.U32 R18, RZ, RZ, UR8 ;
LEA.HI.X R17, R2, c[0x0][0x17c], R5, 0x4, P1 ;
IMAD.U32 R19, RZ, RZ, UR9 ;
IMAD.MOV.U32 R26, RZ, RZ, R14 ;
IMAD.MOV.U32 R27, RZ, RZ, R15 ;
IMAD.MOV.U32 R30, RZ, RZ, R12 ;
IMAD.MOV.U32 R31, RZ, RZ, R13 ;
SHF.R.S32.HI R12, RZ, 0x1f, R0 ;
LDG.E.64 R24, [R16.64+0x8] ;
IADD3 R13, P1, -R0, UR14, RZ ;
IADD3.X R12, ~R12, UR6, RZ, P1, !PT ;
LEA R20, P1, R13, c[0x0][0x170], 0x4 ;
LEA.HI.X R21, R13, c[0x0][0x174], R12, 0x4, P1 ;
LDG.E.128 R12, [R20.64] ;
DMUL R28, R24, R26 ;
DFMA R28, R22, R30, -R28 ;
DADD R28, R28, R12 ;
STG.E.64 [R10.64], R28 ;
LDG.E.64 R22, [R16.64] ;
DMUL R24, R24, R28 ;
DFMA R24, R22, R26, R24 ;
DADD R24, R14, R24 ;
STG.E.64 [R10.64+0x8], R24 ;
LDG.E.64 R26, [R16.64+0x8] ;
LDG.E.128 R12, [R20.64+-0x10] ;
DMUL R30, R24, R26 ;
DFMA R30, R28, R22, -R30 ;
DADD R30, R30, R12 ;
STG.E.64 [R10.64], R30 ;
LDG.E.64 R22, [R16.64] ;
DMUL R26, R26, R30 ;
DFMA R26, R24, R22, R26 ;
DADD R26, R14, R26 ;
STG.E.64 [R10.64+0x8], R26 ;
LDG.E.64 R24, [R16.64+0x8] ;
LDG.E.128 R12, [R20.64+-0x20] ;
DMUL R28, R26, R24 ;
DFMA R28, R30, R22, -R28 ;
DADD R28, R28, R12 ;
STG.E.64 [R10.64], R28 ;
LDG.E.64 R22, [R16.64] ;
DMUL R24, R24, R28 ;
DFMA R24, R26, R22, R24 ;
DADD R24, R14, R24 ;
STG.E.64 [R10.64+0x8], R24 ;
LDG.E.64 R26, [R16.64+0x8] ;
LDG.E.128 R12, [R20.64+-0x30] ;
DMUL R30, R24, R26 ;
DFMA R30, R28, R22, -R30 ;
DADD R30, R30, R12 ;
STG.E.64 [R10.64], R30 ;
LDG.E.64 R22, [R16.64] ;
DMUL R26, R26, R30 ;
IADD3 R18, P1, R18, -0x4, RZ ;
IADD3.X R19, R19, -0x1, RZ, P1, !PT ;
ISETP.NE.U32.AND P1, PT, R18, RZ, PT ;
ISETP.NE.AND.EX P1, PT, R19, RZ, PT, P1 ;
IADD3 R0, R0, 0x4, RZ ;
DFMA R26, R24, R22, R26 ;
DADD R26, R14, R26 ;
STG.E.64 [R10.64+0x8], R26 ;
@P1 BRA 0x660 ;
@!P0 BRA 0xd70 ;
R2UR UR5, R0 ;
LEA R24, P0, R2.reuse, c[0x0][0x178], 0x4 ;
ULDC.64 UR10, c[0x0][0x170] ;
LDG.E.128 R12, [R10.64] ;
LEA.HI.X R25, R2, c[0x0][0x17c], R5, 0x4, P0 ;
LDG.E.128 R16, [R24.64] ;
USHF.R.S32.HI UR4, URZ, 0x1f, UR5 ;
UIADD3 UR5, UP0, -UR5, UR14, URZ ;
UIADD3.X UR7, ~UR4, UR6, URZ, UP0, !UPT ;
ULEA UR4, UP0, UR5, UR10, 0x4 ;
ULEA.HI.X UR5, UR5, UR11, UR7, 0x4, UP0 ;
IMAD.U32 R22, RZ, RZ, UR4 ;
IMAD.U32 R23, RZ, RZ, UR5 ;
LDG.E.128 R20, [R22.64] ;
DMUL R26, R18, R14 ;
DFMA R12, R16, R12, -R26 ;
DADD R20, R12, R20 ;
STG.E.64 [R10.64], R20 ;
LDG.E.64 R16, [R24.64] ;
DMUL R18, R18, R20 ;
UISETP.NE.U32.AND UP0, UPT, UR15, 0x1, UPT ;
UISETP.NE.AND.EX UP0, UPT, URZ, URZ, UPT, UP0 ;
PLOP3.LUT P0, PT, PT, PT, UP0, 0x80, 0x0 ;
DFMA R18, R16, R14, R18 ;
DADD R26, R22, R18 ;
STG.E.64 [R10.64+0x8], R26 ;
@!P0 BRA 0xd70 ;
LDG.E.64 R22, [R24.64+0x8] ;
IMAD.U32 R12, RZ, RZ, UR4 ;
IMAD.U32 R13, RZ, RZ, UR5 ;
LDG.E.128 R12, [R12.64+-0x10] ;
DMUL R18, R26, R22 ;
DFMA R16, R20, R16, -R18 ;
DADD R16, R16, R12 ;
STG.E.64 [R10.64], R16 ;
LDG.E.64 R18, [R24.64] ;
DMUL R22, R22, R16 ;
UISETP.NE.U32.AND UP0, UPT, UR15, 0x2, UPT ;
UISETP.NE.AND.EX UP0, UPT, URZ, URZ, UPT, UP0 ;
PLOP3.LUT P0, PT, PT, PT, UP0, 0x80, 0x0 ;
DFMA R22, R26, R18, R22 ;
DADD R26, R14, R22 ;
STG.E.64 [R10.64+0x8], R26 ;
@!P0 BRA 0xd70 ;
LDG.E.64 R20, [R24.64+0x8] ;
IMAD.U32 R28, RZ, RZ, UR4 ;
IMAD.U32 R29, RZ, RZ, UR5 ;
LDG.E.128 R12, [R28.64+-0x20] ;
DMUL R22, R26, R20 ;
DFMA R22, R16, R18, -R22 ;
DADD R12, R22, R12 ;
STG.E.64 [R10.64], R12 ;
LDG.E.64 R16, [R24.64] ;
DMUL R20, R20, R12 ;
DFMA R16, R26, R16, R20 ;
DADD R14, R14, R16 ;
STG.E.64 [R10.64+0x8], R14 ;
IADD3 R2, R3, 0x1, RZ ;
ISETP.GT.U32.AND P0, PT, R6, R2, PT ;
IMAD.MOV.U32 R3, RZ, RZ, R2.reuse ;
SHF.R.S32.HI R5, RZ, 0x1f, R2 ;
ISETP.GT.AND.EX P0, PT, R4, R5, PT, P0 ;
@P0 BRA 0x4d0 ;
EXIT ;
ULDC UR4, c[0x0][0x164] ;
UMOV UR5, URZ ;
I2F.U64.RP R6, UR4 ;
MUFU.RCP R6, R6 ;
IADD3 R2, R6, 0x1ffffffe, RZ ;
F2I.U64.TRUNC R2, R2 ;
IMAD.WIDE.U32 R4, R2, c[0x0][0x164], RZ ;
IMAD R5, R3, c[0x0][0x164], R5 ;
IADD3 R7, P0, RZ, -R4, RZ ;
IMAD.HI.U32 R4, R2, R7, RZ ;
IMAD.X R9, RZ, RZ, ~R5, P0 ;
IMAD.MOV.U32 R5, RZ, RZ, R2 ;
IMAD R11, R3, R9.reuse, RZ ;
IMAD.WIDE.U32 R4, P0, R2, R9, R4 ;
IMAD.HI.U32 R9, R3, R9, RZ ;
IMAD.HI.U32 R4, P1, R3, R7, R4 ;
IADD3 R5, P2, R11, R4, RZ ;
IMAD.X R4, R9, 0x1, R3, P0 ;
IADD3 R9, P4, RZ, -UR6, RZ ;
IMAD.WIDE.U32 R2, R5, c[0x0][0x164], RZ ;
IADD3.X R7, RZ, RZ, R4, P2, P1 ;
ISETP.LE.AND P1, PT, RZ, UR7, PT ;
IMAD.X R8, RZ, RZ, ~UR7, P4 ;
IADD3 R11, P0, RZ, -R2, RZ ;
IMAD R2, R7, c[0x0][0x164], R3 ;
SEL R9, R9, UR6, !P1 ;
IMAD.MOV.U32 R3, RZ, RZ, RZ ;
SEL R8, R8, UR7, !P1 ;
IMAD.HI.U32 R4, R5, R11, RZ ;
IMAD.X R2, RZ, RZ, ~R2, P0 ;
IMAD.WIDE.U32 R4, P0, R5, R2, R4 ;
IMAD.HI.U32 R5, P2, R7, R11, R4 ;
IMAD R4, R7.reuse, R2.reuse, RZ ;
IMAD.HI.U32 R2, R7, R2, RZ ;
IADD3 R5, P3, R4, R5, RZ ;
IMAD.X R7, R2, 0x1, R7, P0 ;
IMAD.HI.U32 R2, R5, R9, RZ ;
IADD3.X R7, RZ, RZ, R7, P3, P2 ;
IMAD.WIDE.U32 R2, R5, R8, R2 ;
IMAD R5, R7.reuse, R8, RZ ;
IMAD.HI.U32 R2, P0, R7, R9, R2 ;
IMAD.HI.U32 R7, R7, R8, RZ ;
IADD3 R4, P2, R5, R2, RZ ;
IMAD.X R2, RZ, RZ, R7, P0 ;
IMAD.X R5, RZ, RZ, R2, P2 ;
IMAD.WIDE.U32 R2, R4, c[0x0][0x164], RZ ;
IMAD R3, R5, c[0x0][0x164], R3 ;
IADD3 R9, P0, -R2, R9, RZ ;
IADD3 R6, P2, R9.reuse, -c[0x0][0x164], RZ ;
IMAD.X R8, R8, 0x1, ~R3, P0 ;
ISETP.GE.U32.AND P0, PT, R9, c[0x0][0x164], PT ;
IADD3 R3, P3, R4, 0x1, RZ ;
ISETP.GE.U32.AND.EX P0, PT, R8.reuse, RZ, PT, P0 ;
IADD3.X R7, R8, -0x1, RZ, P2, !PT ;
IMAD.X R2, RZ, RZ, R5, P3 ;
SEL R6, R6, R9, P0 ;
SEL R3, R3, R4, P0 ;
SEL R7, R7, R8, P0 ;
ISETP.GE.U32.AND P2, PT, R6, c[0x0][0x164], PT ;
SEL R2, R2, R5, P0 ;
IADD3 R4, P3, R3, 0x1, RZ ;
ISETP.GE.U32.AND.EX P0, PT, R7, RZ, PT, P2 ;
IMAD.X R5, RZ, RZ, R2, P3 ;
SEL R4, R4, R3, P0 ;
SEL R5, R5, R2, P0 ;
IADD3 R3, P2, RZ, -R4.reuse, RZ ;
ISETP.NE.U32.AND P0, PT, RZ, c[0x0][0x164], PT ;
SEL R4, R3, R4, !P1 ;
IMAD.X R2, RZ, RZ, ~R5, P2 ;
ISETP.NE.AND.EX P0, PT, RZ, RZ, PT, P0 ;
IMAD.MOV.U32 R3, RZ, RZ, 0x0 ;
SEL R5, R2, R5, !P1 ;
IMAD.MOV.U32 R2, RZ, RZ, R0 ;
SEL R4, R4, 0xffffffff, P0 ;
SEL R5, R5, 0xffffffff, P0 ;
RET.REL.NODEC R2 0x0 ;
BRA 0x12a0;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
```
|
```amdasm
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10ddftKerneljjP15HIP_vector_typeIdLj2EES1_S1_ ; -- Begin function _Z10ddftKerneljjP15HIP_vector_typeIdLj2EES1_S1_
.globl _Z10ddftKerneljjP15HIP_vector_typeIdLj2EES1_S1_
.p2align 8
.type _Z10ddftKerneljjP15HIP_vector_typeIdLj2EES1_S1_,@function
_Z10ddftKerneljjP15HIP_vector_typeIdLj2EES1_S1_: ; @_Z10ddftKerneljjP15HIP_vector_typeIdLj2EES1_S1_
; %bb.0:
s_load_b64 s[2:3], s[0:1], 0x0
v_cvt_f32_ubyte0_e32 v1, 0
v_add_nc_u32_e32 v6, 1, v0
s_waitcnt lgkmcnt(0)
v_cvt_f32_u32_e32 v2, s3
s_lshl_b32 s8, 1, s2
s_mov_b32 s2, s3
s_ashr_i32 s9, s8, 31
s_sub_u32 s2, 0, s3
v_fmamk_f32 v1, v1, 0x4f800000, v2
s_subb_u32 s6, 0, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f32_e32 v1, v1
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v1, 0x5f7ffffc, v1
v_mul_f32_e32 v2, 0x2f800000, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_trunc_f32_e32 v2, v2
v_fmamk_f32 v1, v2, 0xcf800000, v1
v_cvt_u32_f32_e32 v2, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cvt_u32_f32_e32 v1, v1
v_readfirstlane_b32 s4, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_readfirstlane_b32 s5, v1
s_mul_i32 s7, s2, s4
s_delay_alu instid0(VALU_DEP_1)
s_mul_hi_u32 s11, s2, s5
s_mul_i32 s10, s6, s5
s_add_i32 s7, s11, s7
s_mul_i32 s12, s2, s5
s_add_i32 s7, s7, s10
s_mul_hi_u32 s11, s5, s12
s_mul_hi_u32 s13, s4, s12
s_mul_i32 s10, s4, s12
s_mul_hi_u32 s12, s5, s7
s_mul_i32 s5, s5, s7
s_mul_hi_u32 s14, s4, s7
s_add_u32 s5, s11, s5
s_addc_u32 s11, 0, s12
s_add_u32 s5, s5, s10
s_mul_i32 s7, s4, s7
s_addc_u32 s5, s11, s13
s_addc_u32 s10, s14, 0
s_add_u32 s5, s5, s7
s_addc_u32 s7, 0, s10
v_add_co_u32 v1, s5, v1, s5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
s_cmp_lg_u32 s5, 0
s_addc_u32 s7, s4, s7
v_readfirstlane_b32 s5, v1
s_mul_i32 s10, s2, s7
s_mov_b32 s4, s9
s_delay_alu instid0(VALU_DEP_1)
s_mul_hi_u32 s11, s2, s5
s_mul_i32 s6, s6, s5
s_add_i32 s10, s11, s10
s_mul_i32 s2, s2, s5
s_add_i32 s10, s10, s6
s_mul_hi_u32 s11, s7, s2
s_mul_i32 s12, s7, s2
s_mul_hi_u32 s2, s5, s2
s_mul_hi_u32 s13, s5, s10
s_mul_i32 s5, s5, s10
s_mul_hi_u32 s6, s7, s10
s_add_u32 s2, s2, s5
s_addc_u32 s5, 0, s13
s_add_u32 s2, s2, s12
s_mul_i32 s10, s7, s10
s_addc_u32 s2, s5, s11
s_addc_u32 s5, s6, 0
s_add_u32 s2, s2, s10
s_addc_u32 s6, 0, s5
v_add_co_u32 v1, s2, v1, s2
s_delay_alu instid0(VALU_DEP_1)
s_cmp_lg_u32 s2, 0
s_mov_b32 s5, s9
s_addc_u32 s2, s7, s6
s_add_u32 s6, s8, s9
v_readfirstlane_b32 s10, v1
s_addc_u32 s7, s9, s9
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_xor_b64 s[4:5], s[6:7], s[4:5]
s_mul_i32 s7, s4, s2
s_delay_alu instid0(VALU_DEP_1)
s_mul_hi_u32 s11, s4, s10
s_mul_hi_u32 s6, s4, s2
s_mul_hi_u32 s13, s5, s10
s_mul_i32 s10, s5, s10
s_add_u32 s7, s11, s7
s_addc_u32 s6, 0, s6
s_mul_hi_u32 s12, s5, s2
s_add_u32 s7, s7, s10
s_mul_i32 s2, s5, s2
s_addc_u32 s6, s6, s13
s_addc_u32 s7, s12, 0
s_add_u32 s6, s6, s2
s_addc_u32 s7, 0, s7
s_mul_i32 s11, s3, s6
s_add_u32 s10, s6, 1
v_sub_co_u32 v1, s4, s4, s11
s_mul_hi_u32 s2, s3, s6
s_addc_u32 s12, s7, 0
s_mul_i32 s13, s3, s7
s_add_u32 s14, s6, 2
s_addc_u32 s11, s7, 0
s_add_i32 s2, s2, s13
s_cmp_lg_u32 s4, 0
v_sub_co_u32 v2, s4, v1, s3
s_subb_u32 s2, s5, s2
s_cmp_lg_u32 s4, 0
v_mov_b32_e32 v3, s14
s_delay_alu instid0(VALU_DEP_2)
v_cmp_le_u32_e32 vcc_lo, s3, v2
s_subb_u32 s4, s2, 0
v_mov_b32_e32 v4, s11
s_cmp_eq_u32 s4, 0
v_cndmask_b32_e64 v2, 0, -1, vcc_lo
s_cselect_b32 vcc_lo, -1, 0
s_cmp_eq_u32 s2, 0
s_cselect_b32 s2, -1, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_cndmask_b32_e32 v2, -1, v2, vcc_lo
v_cmp_le_u32_e32 vcc_lo, s3, v1
v_cndmask_b32_e64 v1, 0, -1, vcc_lo
v_cmp_ne_u32_e32 vcc_lo, 0, v2
s_delay_alu instid0(VALU_DEP_2)
v_cndmask_b32_e64 v1, -1, v1, s2
v_cndmask_b32_e32 v2, s10, v3, vcc_lo
v_cndmask_b32_e32 v3, s12, v4, vcc_lo
s_mov_b32 s10, 0
s_mov_b32 s2, exec_lo
v_cmp_ne_u32_e32 vcc_lo, 0, v1
v_cndmask_b32_e32 v2, s6, v2, vcc_lo
v_cndmask_b32_e32 v1, s7, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_xor_b32_e32 v2, s9, v2
v_xor_b32_e32 v1, s9, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_co_u32 v7, vcc_lo, v2, s9
v_subrev_co_ci_u32_e32 v8, vcc_lo, s9, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[4:5], null, v7, v6, 0
v_mov_b32_e32 v1, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[2:3], null, v8, v6, v[1:2]
v_mul_lo_u32 v6, v0, v7
v_mov_b32_e32 v5, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v7, 31, v6
v_cmpx_gt_i64_e64 v[4:5], v[6:7]
s_cbranch_execz .LBB0_6
; %bb.1: ; %.lr.ph52
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x8
s_load_b64 s[0:1], s[0:1], 0x18
s_lshl_b64 s[2:3], s[8:9], 4
s_add_i32 s11, s8, -1
v_mov_b32_e32 v11, 0
s_waitcnt lgkmcnt(0)
s_add_u32 s6, s2, s6
s_addc_u32 s7, s3, s7
s_add_u32 s2, s6, -16
s_addc_u32 s3, s7, -1
s_cmp_gt_i32 s8, 1
s_cselect_b32 s12, -1, 0
s_add_u32 s6, s6, 0xffffffe0
s_addc_u32 s7, s7, -1
.LBB0_2: ; =>This Loop Header: Depth=1
; Child Loop BB0_4 Depth 2
global_load_b128 v[0:3], v11, s[2:3]
v_lshlrev_b64 v[9:10], 4, v[6:7]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v7, vcc_lo, s4, v9
v_add_co_ci_u32_e32 v8, vcc_lo, s5, v10, vcc_lo
s_and_not1_b32 vcc_lo, exec_lo, s12
s_waitcnt vmcnt(0)
global_store_b128 v[7:8], v[0:3], off
s_cbranch_vccnz .LBB0_5
; %bb.3: ; %.lr.ph
; in Loop: Header=BB0_2 Depth=1
global_load_b128 v[0:3], v[7:8], off
v_add_co_u32 v9, vcc_lo, s0, v9
v_add_co_ci_u32_e32 v10, vcc_lo, s1, v10, vcc_lo
s_mov_b32 s13, 0
s_mov_b64 s[8:9], s[6:7]
.LBB0_4: ; Parent Loop BB0_2 Depth=1
; => This Inner Loop Header: Depth=2
global_load_b128 v[12:15], v[9:10], off
global_load_b64 v[16:17], v11, s[8:9]
s_waitcnt vmcnt(1)
v_mul_f64 v[14:15], v[2:3], v[14:15]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_fma_f64 v[0:1], v[0:1], v[12:13], -v[14:15]
s_waitcnt vmcnt(0)
v_add_f64 v[0:1], v[16:17], v[0:1]
global_store_b64 v[7:8], v[0:1], off
global_load_b128 v[12:15], v[9:10], off
global_load_b64 v[16:17], v11, s[8:9] offset:8
s_add_u32 s8, s8, -16
s_addc_u32 s9, s9, -1
s_add_i32 s13, s13, 1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
s_cmp_ge_u32 s13, s11
s_waitcnt vmcnt(1)
v_mul_f64 v[14:15], v[0:1], v[14:15]
v_fma_f64 v[2:3], v[2:3], v[12:13], v[14:15]
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_add_f64 v[2:3], v[16:17], v[2:3]
global_store_b64 v[7:8], v[2:3], off offset:8
s_cbranch_scc0 .LBB0_4
.LBB0_5: ; %._crit_edge
; in Loop: Header=BB0_2 Depth=1
v_add_nc_u32_e32 v6, 1, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v7, 31, v6
v_cmp_le_i64_e32 vcc_lo, v[4:5], v[6:7]
s_or_b32 s10, vcc_lo, s10
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s10
s_cbranch_execnz .LBB0_2
.LBB0_6: ; %Flow78
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10ddftKerneljjP15HIP_vector_typeIdLj2EES1_S1_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 32
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 18
.amdhsa_next_free_sgpr 15
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10ddftKerneljjP15HIP_vector_typeIdLj2EES1_S1_, .Lfunc_end0-_Z10ddftKerneljjP15HIP_vector_typeIdLj2EES1_S1_
; -- End function
.section .AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1016
; NumSgprs: 17
; NumVgprs: 18
; ScratchSize: 0
; MemoryBound: 1
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 2
; NumSGPRsForWavesPerEU: 17
; NumVGPRsForWavesPerEU: 18
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object ; @__hip_cuid_
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0 ; 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 32
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10ddftKerneljjP15HIP_vector_typeIdLj2EES1_S1_
.private_segment_fixed_size: 0
.sgpr_count: 17
.sgpr_spill_count: 0
.symbol: _Z10ddftKerneljjP15HIP_vector_typeIdLj2EES1_S1_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 18
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
```
| 5,945 | 5,846 |
181 |
Convert the following CUDA host assembly code to AMD host assembly:
```cudaasm
.file "tmpxft_001b22d2_00000000-6_ddft_test.cudafe1.cpp"
.text
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z45__device_stub__Z10ddftKerneljjP7double2S0_S0_jjP7double2S0_S0_
.type _Z45__device_stub__Z10ddftKerneljjP7double2S0_S0_jjP7double2S0_S0_, @function
_Z45__device_stub__Z10ddftKerneljjP7double2S0_S0_jjP7double2S0_S0_:
.LFB2106:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 28(%rsp)
movl %esi, 24(%rsp)
movq %rdx, 16(%rsp)
movq %rcx, 8(%rsp)
movq %r8, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 24(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z10ddftKerneljjP7double2S0_S0_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2106:
.size _Z45__device_stub__Z10ddftKerneljjP7double2S0_S0_jjP7double2S0_S0_, .-_Z45__device_stub__Z10ddftKerneljjP7double2S0_S0_jjP7double2S0_S0_
.globl _Z10ddftKerneljjP7double2S0_S0_
.type _Z10ddftKerneljjP7double2S0_S0_, @function
_Z10ddftKerneljjP7double2S0_S0_:
.LFB2107:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z45__device_stub__Z10ddftKerneljjP7double2S0_S0_jjP7double2S0_S0_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2107:
.size _Z10ddftKerneljjP7double2S0_S0_, .-_Z10ddftKerneljjP7double2S0_S0_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "cudaSetDevice failed! Do you have a CUDA-capable GPU installed?"
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "cudaMalloc failed!"
.LC3:
.string "cudaMemcpy failed!"
.LC4:
.string "addKernel launch failed: %s\n"
.section .rodata.str1.8
.align 8
.LC5:
.string "cudaDeviceSynchronize returned error code %d after launching addKernel!\n"
.text
.globl _Z8cudaDDFTjjP7double2S0_
.type _Z8cudaDDFTjjP7double2S0_, @function
_Z8cudaDDFTjjP7double2S0_:
.LFB2081:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $136, %rsp
.cfi_def_cfa_offset 192
movl %edi, %r15d
movl %esi, 36(%rsp)
movq %rdx, 40(%rsp)
movq %rcx, 16(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
movl $1, %r12d
movl %edi, %ecx
sall %cl, %r12d
movslq %r12d, %r14
salq $4, %r14
movq %r14, %rdi
call malloc@PLT
movq %rax, 24(%rsp)
testl %r12d, %r12d
jle .L12
pxor %xmm0, %xmm0
cvtsi2sdl %r12d, %xmm0
movsd .LC0(%rip), %xmm1
divsd %xmm0, %xmm1
movsd %xmm1, 8(%rsp)
movq %rax, %rbp
movl $0, %ebx
leaq 56(%rsp), %r13
.L13:
leaq 48(%rsp), %rsi
pxor %xmm0, %xmm0
cvtsi2sdl %ebx, %xmm0
mulsd 8(%rsp), %xmm0
movq %r13, %rdi
call sincos@PLT
movsd 48(%rsp), %xmm0
movsd %xmm0, 0(%rbp)
movsd 56(%rsp), %xmm0
movsd %xmm0, 8(%rbp)
addl $1, %ebx
addq $16, %rbp
cmpl %ebx, %r12d
jne .L13
.L12:
movl $0, %edi
call cudaSetDevice@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L27
leaq 80(%rsp), %rdi
movq %r14, %rsi
call cudaMalloc@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L28
leaq 72(%rsp), %rdi
movq %r14, %rsi
call cudaMalloc@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L29
leaq 88(%rsp), %rdi
movq %r14, %rsi
call cudaMalloc@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L30
movl $1, %ecx
movq %r14, %rdx
movq 16(%rsp), %rsi
movq 72(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L31
movl $1, %ecx
movq %r14, %rdx
movq 24(%rsp), %rsi
movq 88(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L32
movl 36(%rsp), %eax
movl %eax, 108(%rsp)
movl $1, 112(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 108(%rsp), %rdx
movl $1, %ecx
movq 96(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L33
.L21:
call cudaGetLastError@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L34
call cudaDeviceSynchronize@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L35
movl $2, %ecx
movq %r14, %rdx
movq 80(%rsp), %rsi
movq 40(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %ebx
testl %eax, %eax
je .L15
leaq .LC3(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L15
.L27:
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
.L15:
movq 80(%rsp), %rdi
call cudaFree@PLT
movq 72(%rsp), %rdi
call cudaFree@PLT
movq 88(%rsp), %rdi
call cudaFree@PLT
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L36
movl %ebx, %eax
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L28:
.cfi_restore_state
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L15
.L29:
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L15
.L30:
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L15
.L31:
leaq .LC3(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L15
.L32:
leaq .LC3(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L15
.L33:
movq 88(%rsp), %r8
movq 72(%rsp), %rcx
movq 80(%rsp), %rdx
movl 36(%rsp), %esi
movl %r15d, %edi
call _Z45__device_stub__Z10ddftKerneljjP7double2S0_S0_jjP7double2S0_S0_
jmp .L21
.L34:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC4(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L15
.L35:
movl %eax, %ecx
leaq .LC5(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L15
.L36:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2081:
.size _Z8cudaDDFTjjP7double2S0_, .-_Z8cudaDDFTjjP7double2S0_
.section .rodata.str1.1
.LC6:
.string "w"
.LC7:
.string "init.txt"
.LC11:
.string "%19.12e\t%19.12e\t%19.12e\n"
.LC12:
.string "addWithCuda failed!"
.LC13:
.string "output.txt"
.LC14:
.string "cudaDeviceReset failed!"
.text
.globl main
.type main, @function
main:
.LFB2080:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $24, %rsp
.cfi_def_cfa_offset 80
movl $0, %edi
call malloc@PLT
movq %rax, %r15
movl $0, %edi
call malloc@PLT
movq %rax, %r12
leaq .LC6(%rip), %rsi
leaq .LC7(%rip), %rdi
call fopen@PLT
movq %rax, %r13
movq %r15, %rbp
movl $0, %ebx
leaq .LC11(%rip), %r14
.L40:
movl %ebx, %eax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
movsd %xmm0, 8(%rsp)
addsd %xmm0, %xmm0
mulsd .LC8(%rip), %xmm0
mulsd .LC9(%rip), %xmm0
call sin@PLT
movapd %xmm0, %xmm1
movsd %xmm0, 0(%rbp)
movq $0x000000000, 8(%rbp)
movsd .LC0(%rip), %xmm0
mulsd 8(%rsp), %xmm0
mulsd .LC9(%rip), %xmm0
pxor %xmm2, %xmm2
movq %r14, %rdx
movl $2, %esi
movq %r13, %rdi
movl $3, %eax
call __fprintf_chk@PLT
addl $1, %ebx
addq $16, %rbp
cmpl $1024, %ebx
jne .L40
movq %r13, %rdi
call fclose@PLT
movq %r15, %rcx
movq %r12, %rdx
movl $16, %esi
movl $10, %edi
call _Z8cudaDDFTjjP7double2S0_
movl %eax, %ebx
testl %eax, %eax
jne .L50
leaq .LC6(%rip), %rsi
leaq .LC13(%rip), %rdi
call fopen@PLT
movq %rax, %rbp
leaq .LC11(%rip), %r13
.L45:
movl %ebx, %eax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
mulsd .LC0(%rip), %xmm0
mulsd .LC9(%rip), %xmm0
movsd 8(%r12), %xmm2
movsd (%r12), %xmm1
movq %r13, %rdx
movl $2, %esi
movq %rbp, %rdi
movl $3, %eax
call __fprintf_chk@PLT
addl $1, %ebx
addq $16, %r12
cmpl $1024, %ebx
jne .L45
movq %rbp, %rdi
call fclose@PLT
call cudaDeviceReset@PLT
movl %eax, %edx
movl $0, %eax
testl %edx, %edx
jne .L51
.L37:
addq $24, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L50:
.cfi_restore_state
leaq .LC12(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %eax
jmp .L37
.L51:
leaq .LC14(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
call __fprintf_chk@PLT
movl $1, %eax
jmp .L37
.cfi_endproc
.LFE2080:
.size main, .-main
.section .rodata.str1.8
.align 8
.LC15:
.string "_Z10ddftKerneljjP7double2S0_S0_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2109:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC15(%rip), %rdx
movq %rdx, %rcx
leaq _Z10ddftKerneljjP7double2S0_S0_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2109:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC0:
.long 1413754136
.long 1075388923
.align 8
.LC8:
.long 1413754136
.long 1074340347
.align 8
.LC9:
.long 0
.long 1062207488
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
```
|
```amdasm
.text
.file "ddft_test.hip"
.globl _Z25__device_stub__ddftKerneljjP15HIP_vector_typeIdLj2EES1_S1_ # -- Begin function _Z25__device_stub__ddftKerneljjP15HIP_vector_typeIdLj2EES1_S1_
.type _Z25__device_stub__ddftKerneljjP15HIP_vector_typeIdLj2EES1_S1_,@function
_Z25__device_stub__ddftKerneljjP15HIP_vector_typeIdLj2EES1_S1_: # @_Z25__device_stub__ddftKerneljjP15HIP_vector_typeIdLj2EES1_S1_
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $128, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 4(%rsp), %rax
movl %edi, (%rax)
movq %rsp, %rdi
movl %esi, (%rdi)
leaq 40(%rsp), %rsi
movq %rdx, (%rsi)
leaq 32(%rsp), %rdx
movq %rcx, (%rdx)
leaq 24(%rsp), %rcx
movq %r8, (%rcx)
leaq 80(%rsp), %rbx
movq %rax, (%rbx)
movq %rdi, 8(%rbx)
movq %rsi, 16(%rbx)
movq %rdx, 24(%rbx)
movq %rcx, 32(%rbx)
leaq 64(%rsp), %r14
leaq 48(%rsp), %r15
leaq 16(%rsp), %r12
leaq 8(%rsp), %r13
movq %r14, %rdi
movq %r15, %rsi
movq %r12, %rdx
movq %r13, %rcx
callq __hipPopCallConfiguration
movq (%r14), %rsi
movl 8(%r14), %edx
movq (%r15), %rcx
movl 8(%r15), %r8d
movl $_Z10ddftKerneljjP15HIP_vector_typeIdLj2EES1_S1_, %edi
movq %rbx, %r9
pushq (%r13)
.cfi_adjust_cfa_offset 8
pushq (%r12)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $144, %rsp
.cfi_adjust_cfa_offset -144
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z25__device_stub__ddftKerneljjP15HIP_vector_typeIdLj2EES1_S1_, .Lfunc_end0-_Z25__device_stub__ddftKerneljjP15HIP_vector_typeIdLj2EES1_S1_
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI1_0:
.quad 0x400921fb54442d18 # double 3.1415926535897931
.LCPI1_1:
.quad 0x3f50000000000000 # double 9.765625E-4
.LCPI1_2:
.quad 0x401921fb54442d18 # double 6.2831853071795862
.text
.globl main
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $16, %rsp
.cfi_def_cfa_offset 64
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
callq malloc
movq %rax, %r14
callq malloc
movq %rax, %rbx
movl $.L.str, %edi
movl $.L.str.1, %esi
callq fopen
movq %rax, %r15
movq %r14, %r12
addq $8, %r12
xorl %r13d, %r13d
.LBB1_1: # =>This Inner Loop Header: Depth=1
movl %r13d, %eax
xorps %xmm0, %xmm0
cvtsi2sd %rax, %xmm0
movsd %xmm0, 8(%rsp) # 8-byte Spill
addsd %xmm0, %xmm0
mulsd .LCPI1_0(%rip), %xmm0
movsd .LCPI1_1(%rip), %xmm1 # xmm1 = mem[0],zero
mulsd %xmm1, %xmm0
callq sin
movapd %xmm0, %xmm1
movsd %xmm0, -8(%r12)
movq $0, (%r12)
movsd 8(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
mulsd .LCPI1_2(%rip), %xmm0
mulsd .LCPI1_1(%rip), %xmm0
movl $.L.str.2, %esi
xorps %xmm2, %xmm2
movq %r15, %rdi
movb $3, %al
callq fprintf
incq %r13
addq $16, %r12
cmpq $1024, %r13 # imm = 0x400
jne .LBB1_1
# %bb.2:
movq %r15, %rdi
callq fclose
movl $10, %edi
movl $16, %esi
movq %rbx, %rdx
movq %r14, %rcx
callq _Z8cudaDDFTjjP15HIP_vector_typeIdLj2EES1_
testl %eax, %eax
jne .LBB1_3
# %bb.4:
movl $.L.str.4, %edi
movl $.L.str.1, %esi
callq fopen
movq %rax, %r14
addq $8, %rbx
xorl %r15d, %r15d
.LBB1_5: # =>This Inner Loop Header: Depth=1
movl %r15d, %eax
xorps %xmm0, %xmm0
cvtsi2sd %rax, %xmm0
mulsd .LCPI1_2(%rip), %xmm0
mulsd .LCPI1_1(%rip), %xmm0
movsd -8(%rbx), %xmm1 # xmm1 = mem[0],zero
movsd (%rbx), %xmm2 # xmm2 = mem[0],zero
movl $.L.str.2, %esi
movq %r14, %rdi
movb $3, %al
callq fprintf
incq %r15
addq $16, %rbx
cmpq $1024, %r15 # imm = 0x400
jne .LBB1_5
# %bb.6:
movq %r14, %rdi
callq fclose
callq hipDeviceReset
movl %eax, %ecx
xorl %eax, %eax
testl %ecx, %ecx
jne .LBB1_7
.LBB1_9:
addq $16, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB1_3:
.cfi_def_cfa_offset 64
movq stderr(%rip), %rcx
movl $.L.str.3, %edi
movl $19, %esi
jmp .LBB1_8
.LBB1_7:
movq stderr(%rip), %rcx
movl $.L.str.5, %edi
movl $22, %esi
.LBB1_8:
movl $1, %edx
callq fwrite@PLT
movl $1, %eax
jmp .LBB1_9
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z8cudaDDFTjjP15HIP_vector_typeIdLj2EES1_
.LCPI2_0:
.quad 0x401921fb54442d18 # double 6.2831853071795862
.text
.globl _Z8cudaDDFTjjP15HIP_vector_typeIdLj2EES1_
.type _Z8cudaDDFTjjP15HIP_vector_typeIdLj2EES1_,@function
_Z8cudaDDFTjjP15HIP_vector_typeIdLj2EES1_: # @_Z8cudaDDFTjjP15HIP_vector_typeIdLj2EES1_
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $72, %rsp
.cfi_def_cfa_offset 128
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rcx, 48(%rsp) # 8-byte Spill
movq %rdx, 40(%rsp) # 8-byte Spill
movl %edi, %r15d
movl $1, %r12d
movl %r15d, %ecx
shll %cl, %r12d
movl %esi, 36(%rsp) # 4-byte Spill
movl $1, %ebp
movslq %r12d, %r14
shlq $4, %r14
movq %r14, %rdi
callq malloc
movq %rax, %rbx
cmpl $31, %r15d
je .LBB2_3
# %bb.1: # %.lr.ph
cvtsi2sd %r12d, %xmm0
movsd .LCPI2_0(%rip), %xmm1 # xmm1 = mem[0],zero
divsd %xmm0, %xmm1
movsd %xmm1, 56(%rsp) # 8-byte Spill
cmpl $2, %r12d
cmovgel %r12d, %ebp
leaq 8(%rbx), %r12
xorl %r13d, %r13d
.LBB2_2: # =>This Inner Loop Header: Depth=1
xorps %xmm0, %xmm0
cvtsi2sd %r13d, %xmm0
mulsd 56(%rsp), %xmm0 # 8-byte Folded Reload
movsd %xmm0, 64(%rsp) # 8-byte Spill
callq cos
movsd %xmm0, -8(%r12)
movsd 64(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
callq sin
movsd %xmm0, (%r12)
incq %r13
addq $16, %r12
cmpq %r13, %rbp
jne .LBB2_2
.LBB2_3: # %._crit_edge
xorl %edi, %edi
callq hipSetDevice
testl %eax, %eax
jne .LBB2_4
# %bb.5:
leaq 16(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB2_6
# %bb.9:
leaq 24(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB2_6
# %bb.10:
leaq 8(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB2_6
# %bb.11:
movq 24(%rsp), %rdi
movq 48(%rsp), %rsi # 8-byte Reload
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB2_12
# %bb.13:
movq 8(%rsp), %rdi
movq %rbx, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB2_12
# %bb.14:
movl 36(%rsp), %ebx # 4-byte Reload
movl %ebx, %edx
btsq $32, %rdx
movabsq $4294967296, %rdi # imm = 0x100000000
orq $1, %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_16
# %bb.15:
movq 16(%rsp), %rdx
movq 24(%rsp), %rcx
movq 8(%rsp), %r8
movl %r15d, %edi
movl %ebx, %esi
callq _Z25__device_stub__ddftKerneljjP15HIP_vector_typeIdLj2EES1_S1_
.LBB2_16:
callq hipGetLastError
testl %eax, %eax
jne .LBB2_17
# %bb.18:
callq hipDeviceSynchronize
testl %eax, %eax
jne .LBB2_19
# %bb.20:
movq 16(%rsp), %rsi
movq 40(%rsp), %rdi # 8-byte Reload
movq %r14, %rdx
movl $2, %ecx
callq hipMemcpy
xorl %ebp, %ebp
testl %eax, %eax
je .LBB2_22
# %bb.21:
movl %eax, %ebx
movq stderr(%rip), %rcx
movl $.L.str.8, %edi
movl $17, %esi
movl $1, %edx
callq fwrite@PLT
movl %ebx, %ebp
jmp .LBB2_22
.LBB2_6:
movl %eax, %ebp
movq stderr(%rip), %rcx
movl $.L.str.7, %edi
jmp .LBB2_7
.LBB2_12:
movl %eax, %ebp
movq stderr(%rip), %rcx
movl $.L.str.8, %edi
.LBB2_7:
movl $17, %esi
.LBB2_8:
movl $1, %edx
callq fwrite@PLT
.LBB2_22:
movq 16(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movl %ebp, %eax
addq $72, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB2_4:
.cfi_def_cfa_offset 128
movl %eax, %ebp
movq stderr(%rip), %rcx
movl $.L.str.6, %edi
movl $63, %esi
jmp .LBB2_8
.LBB2_17:
movl %eax, %ebp
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.9, %esi
movq %rbx, %rdi
movq %rax, %rdx
xorl %eax, %eax
callq fprintf
jmp .LBB2_22
.LBB2_19:
movl %eax, %ebp
movq stderr(%rip), %rdi
movl $.L.str.10, %esi
movl %eax, %edx
xorl %eax, %eax
callq fprintf
jmp .LBB2_22
.Lfunc_end2:
.size _Z8cudaDDFTjjP15HIP_vector_typeIdLj2EES1_, .Lfunc_end2-_Z8cudaDDFTjjP15HIP_vector_typeIdLj2EES1_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, %rdi
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10ddftKerneljjP15HIP_vector_typeIdLj2EES1_S1_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10ddftKerneljjP15HIP_vector_typeIdLj2EES1_S1_,@object # @_Z10ddftKerneljjP15HIP_vector_typeIdLj2EES1_S1_
.section .rodata,"a",@progbits
.globl _Z10ddftKerneljjP15HIP_vector_typeIdLj2EES1_S1_
.p2align 3, 0x0
_Z10ddftKerneljjP15HIP_vector_typeIdLj2EES1_S1_:
.quad _Z25__device_stub__ddftKerneljjP15HIP_vector_typeIdLj2EES1_S1_
.size _Z10ddftKerneljjP15HIP_vector_typeIdLj2EES1_S1_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "init.txt"
.size .L.str, 9
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "w"
.size .L.str.1, 2
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "%19.12e\t%19.12e\t%19.12e\n"
.size .L.str.2, 25
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "addWithCuda failed!"
.size .L.str.3, 20
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "output.txt"
.size .L.str.4, 11
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "hipDeviceReset failed!"
.size .L.str.5, 23
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "hipSetDevice failed! Do you have a CUDA-capable GPU installed?"
.size .L.str.6, 64
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "hipMalloc failed!"
.size .L.str.7, 18
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "hipMemcpy failed!"
.size .L.str.8, 18
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "addKernel launch failed: %s\n"
.size .L.str.9, 29
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "hipDeviceSynchronize returned error code %d after launching addKernel!\n"
.size .L.str.10, 72
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z10ddftKerneljjP15HIP_vector_typeIdLj2EES1_S1_"
.size .L__unnamed_1, 48
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__ddftKerneljjP15HIP_vector_typeIdLj2EES1_S1_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10ddftKerneljjP15HIP_vector_typeIdLj2EES1_S1_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
```
| 6,202 | 6,928 |
182 |
Convert the following CUDA device assembly code to AMD device assembly:
```cudaasm
code for sm_80
Function : _Z10addVectorsPiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
MOV R1, c[0x0][0x28] ;
S2R R0, SR_CTAID.X ;
S2R R3, SR_TID.X ;
IMAD R0, R0, c[0x0][0x0], R3 ;
ISETP.GT.AND P0, PT, R0, 0xf423f, PT ;
@P0 EXIT ;
ULDC.64 UR4, c[0x0][0x118] ;
HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ;
IMAD.WIDE R2, R0, R7, c[0x0][0x160] ;
IMAD.WIDE R4, R0.reuse, R7.reuse, c[0x0][0x168] ;
LDG.E R3, [R2.64] ;
LDG.E R4, [R4.64] ;
IMAD.WIDE R6, R0, R7, c[0x0][0x170] ;
MOV R11, c[0x0][0xc] ;
IMAD R0, R11, c[0x0][0x0], R0 ;
ISETP.GE.AND P0, PT, R0, 0xf4240, PT ;
IADD3 R9, R4, R3, RZ ;
STG.E [R6.64], R9 ;
@!P0 BRA 0x70 ;
EXIT ;
BRA 0x140;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
```
|
```amdasm
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10addVectorsPiS_S_ ; -- Begin function _Z10addVectorsPiS_S_
.globl _Z10addVectorsPiS_S_
.p2align 8
.type _Z10addVectorsPiS_S_,@function
_Z10addVectorsPiS_S_: ; @_Z10addVectorsPiS_S_
; %bb.0:
s_load_b32 s4, s[0:1], 0x24
s_add_u32 s2, s0, 24
s_addc_u32 s3, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s8, s4, 0xffff
s_mov_b32 s4, exec_lo
v_mad_u64_u32 v[1:2], null, s15, s8, v[0:1]
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e32 0xf4240, v1
s_cbranch_execz .LBB0_3
; %bb.1: ; %.lr.ph
s_load_b32 s9, s[2:3], 0x0
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[2:3], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_mul_i32 s1, s9, s8
s_mov_b32 s8, 0
.LBB0_2: ; =>This Inner Loop Header: Depth=1
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[2:3], 2, v[1:2]
v_add_nc_u32_e32 v1, s1, v1
v_add_co_u32 v4, vcc_lo, s4, v2
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v3, vcc_lo
v_add_co_u32 v6, vcc_lo, s6, v2
v_add_co_ci_u32_e32 v7, vcc_lo, s7, v3, vcc_lo
v_cmp_lt_i32_e32 vcc_lo, 0xf423f, v1
global_load_b32 v0, v[4:5], off
global_load_b32 v4, v[6:7], off
v_add_co_u32 v2, s0, s2, v2
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v3, s0, s3, v3, s0
s_or_b32 s8, vcc_lo, s8
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v0, v4, v0
global_store_b32 v[2:3], v0, off
s_and_not1_b32 exec_lo, exec_lo, s8
s_cbranch_execnz .LBB0_2
.LBB0_3: ; %Flow19
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10addVectorsPiS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10addVectorsPiS_S_, .Lfunc_end0-_Z10addVectorsPiS_S_
; -- End function
.section .AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 228
; NumSgprs: 18
; NumVgprs: 8
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 8
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object ; @__hip_cuid_
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0 ; 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10addVectorsPiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z10addVectorsPiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
```
| 464 | 2,713 |
183 |
Convert the following CUDA host assembly code to AMD host assembly:
```cudaasm
.file "tmpxft_000dee87_00000000-6_01-vector-add.cudafe1.cpp"
.text
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z34__device_stub__Z10addVectorsPiS_S_PiS_S_
.type _Z34__device_stub__Z10addVectorsPiS_S_PiS_S_, @function
_Z34__device_stub__Z10addVectorsPiS_S_PiS_S_:
.LFB2082:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z10addVectorsPiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z34__device_stub__Z10addVectorsPiS_S_PiS_S_, .-_Z34__device_stub__Z10addVectorsPiS_S_PiS_S_
.globl _Z10addVectorsPiS_S_
.type _Z10addVectorsPiS_S_, @function
_Z10addVectorsPiS_S_:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z34__device_stub__Z10addVectorsPiS_S_PiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z10addVectorsPiS_S_, .-_Z10addVectorsPiS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Failed to launch kernel: %s\n"
.LC1:
.string "%d "
.LC2:
.string "\n"
.LC3:
.string "Done\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $72, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rdi
movl $1, %edx
movl $4000000, %esi
call cudaMallocManaged@PLT
leaq 16(%rsp), %rdi
movl $1, %edx
movl $4000000, %esi
call cudaMallocManaged@PLT
leaq 24(%rsp), %rdi
movl $1, %edx
movl $4000000, %esi
call cudaMallocManaged@PLT
movl $0, %ebx
.L12:
call rand@PLT
movslq %eax, %rdx
imulq $1717986919, %rdx, %rdx
sarq $34, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
leal (%rdx,%rdx,4), %edx
addl %edx, %edx
subl %edx, %eax
movq 8(%rsp), %rdx
movl %eax, (%rdx,%rbx)
call rand@PLT
movslq %eax, %rdx
imulq $1717986919, %rdx, %rdx
sarq $34, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
leal (%rdx,%rdx,4), %edx
addl %edx, %edx
subl %edx, %eax
movq 16(%rsp), %rdx
movl %eax, (%rdx,%rbx)
addq $4, %rbx
cmpq $4000000, %rbx
jne .L12
movl $256, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $3907, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L20
.L13:
call cudaGetLastError@PLT
testl %eax, %eax
jne .L21
call cudaDeviceSynchronize@PLT
movl $0, %ebx
leaq .LC1(%rip), %rbp
.L15:
movq 24(%rsp), %rax
movl (%rax,%rbx), %edx
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq $4000000, %rbx
jne .L15
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L22
movl $0, %eax
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L20:
.cfi_restore_state
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z34__device_stub__Z10addVectorsPiS_S_PiS_S_
jmp .L13
.L21:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC0(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L22:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC4:
.string "_Z10addVectorsPiS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z10addVectorsPiS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
```
|
```amdasm
.text
.file "01-vector-add.hip"
.globl _Z25__device_stub__addVectorsPiS_S_ # -- Begin function _Z25__device_stub__addVectorsPiS_S_
.type _Z25__device_stub__addVectorsPiS_S_,@function
_Z25__device_stub__addVectorsPiS_S_: # @_Z25__device_stub__addVectorsPiS_S_
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $112, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 40(%rsp), %rax
movq %rdi, (%rax)
leaq 32(%rsp), %rcx
movq %rsi, (%rcx)
leaq 24(%rsp), %rsi
movq %rdx, (%rsi)
leaq 80(%rsp), %rbx
movq %rax, (%rbx)
movq %rcx, 8(%rbx)
movq %rsi, 16(%rbx)
leaq 64(%rsp), %r14
leaq 48(%rsp), %r15
leaq 16(%rsp), %r12
leaq 8(%rsp), %r13
movq %r14, %rdi
movq %r15, %rsi
movq %r12, %rdx
movq %r13, %rcx
callq __hipPopCallConfiguration
movq (%r14), %rsi
movl 8(%r14), %edx
movq (%r15), %rcx
movl 8(%r15), %r8d
movl $_Z10addVectorsPiS_S_, %edi
movq %rbx, %r9
pushq (%r13)
.cfi_adjust_cfa_offset 8
pushq (%r12)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $128, %rsp
.cfi_adjust_cfa_offset -128
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z25__device_stub__addVectorsPiS_S_, .Lfunc_end0-_Z25__device_stub__addVectorsPiS_S_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
leaq 24(%rsp), %rdi
movl $4000000, %esi # imm = 0x3D0900
movl $1, %edx
callq hipMallocManaged
leaq 16(%rsp), %rdi
movl $4000000, %esi # imm = 0x3D0900
movl $1, %edx
callq hipMallocManaged
leaq 8(%rsp), %rdi
movl $4000000, %esi # imm = 0x3D0900
movl $1, %edx
callq hipMallocManaged
xorl %ebx, %ebx
.LBB1_1: # =>This Inner Loop Header: Depth=1
callq rand
cltq
imulq $1717986919, %rax, %rcx # imm = 0x66666667
movq %rcx, %rdx
shrq $63, %rdx
sarq $34, %rcx
addl %edx, %ecx
addl %ecx, %ecx
leal (%rcx,%rcx,4), %ecx
subl %ecx, %eax
movq 24(%rsp), %rcx
movl %eax, (%rcx,%rbx,4)
callq rand
cltq
imulq $1717986919, %rax, %rcx # imm = 0x66666667
movq %rcx, %rdx
shrq $63, %rdx
sarq $34, %rcx
addl %edx, %ecx
addl %ecx, %ecx
leal (%rcx,%rcx,4), %ecx
subl %ecx, %eax
movq 16(%rsp), %rcx
movl %eax, (%rcx,%rbx,4)
incq %rbx
cmpq $1000000, %rbx # imm = 0xF4240
jne .LBB1_1
# %bb.2:
movabsq $4294967552, %rdx # imm = 0x100000100
leaq 3651(%rdx), %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq 24(%rsp), %rdi
movq 16(%rsp), %rsi
movq 8(%rsp), %rdx
callq _Z25__device_stub__addVectorsPiS_S_
.LBB1_4:
callq hipGetLastError
testl %eax, %eax
jne .LBB1_8
# %bb.5:
callq hipDeviceSynchronize
xorl %ebx, %ebx
.LBB1_6: # =>This Inner Loop Header: Depth=1
movq 8(%rsp), %rax
movl (%rax,%rbx,4), %esi
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
incq %rbx
cmpq $1000000, %rbx # imm = 0xF4240
jne .LBB1_6
# %bb.7:
movl $10, %edi
callq putchar@PLT
movl $.Lstr, %edi
callq puts@PLT
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.LBB1_8:
.cfi_def_cfa_offset 48
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %esi
movq %rbx, %rdi
movq %rax, %rdx
xorl %eax, %eax
callq fprintf
movl $1, %edi
callq exit
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, %rdi
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10addVectorsPiS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10addVectorsPiS_S_,@object # @_Z10addVectorsPiS_S_
.section .rodata,"a",@progbits
.globl _Z10addVectorsPiS_S_
.p2align 3, 0x0
_Z10addVectorsPiS_S_:
.quad _Z25__device_stub__addVectorsPiS_S_
.size _Z10addVectorsPiS_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Failed to launch kernel: %s\n"
.size .L.str, 29
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "%d "
.size .L.str.1, 4
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z10addVectorsPiS_S_"
.size .L__unnamed_1, 21
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Done"
.size .Lstr, 5
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__addVectorsPiS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10addVectorsPiS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
```
| 3,286 | 3,413 |
184 |
Convert the following CUDA device assembly code to AMD device assembly:
```cudaasm
code for sm_80
Function : _Z13reduce_kernelPiS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ;
ULDC UR4, c[0x0][0x0] ;
IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x170] ;
USHF.R.U32.HI UR4, URZ, 0x1, UR4 ;
ULDC.64 UR10, c[0x0][0x118] ;
ISETP.NE.AND P0, PT, RZ, UR4, PT ;
@!P0 BRA 0xce0 ;
S2R R16, SR_TID.X ;
IADD3 R0, R4.reuse, -0x1, RZ ;
LOP3.LUT R3, R4, 0x3, RZ, 0xc0, !PT ;
ISETP.GE.U32.AND P1, PT, R0, 0x3, PT ;
IADD3 R0, -R3, c[0x0][0x170], RZ ;
IMAD R2, R16, c[0x0][0x170], RZ ;
IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x170] ;
ULDC UR5, c[0x0][0x170] ;
BSSY B0, 0xca0 ;
UIMAD UR5, UR4, UR5, URZ ;
ISETP.GE.AND P0, PT, R4, 0x1, PT ;
ISETP.GE.OR P0, PT, R2, UR5, !P0 ;
@P0 BRA 0xc90 ;
IMAD.MOV.U32 R5, RZ, RZ, RZ ;
@!P1 BRA 0xb10 ;
ISETP.GT.AND P0, PT, R0, RZ, PT ;
HFMA2.MMA R5, -RZ, RZ, 0, 0 ;
IADD3 R7, R16, UR4, RZ ;
IMAD.MOV.U32 R14, RZ, RZ, c[0x0][0x160] ;
IMAD.MOV.U32 R15, RZ, RZ, c[0x0][0x164] ;
IMAD.MOV.U32 R6, RZ, RZ, R0 ;
IMAD R7, R7, c[0x0][0x170], RZ ;
@!P0 BRA 0x970 ;
ISETP.GT.AND P2, PT, R6, 0xc, PT ;
PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ;
@!P2 BRA 0x6c0 ;
PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ;
MOV R9, R15 ;
IMAD.MOV.U32 R8, RZ, RZ, R14 ;
IMAD.WIDE R12, R7, 0x4, R8 ;
IMAD.WIDE R10, R2, 0x4, R8 ;
LDG.E R15, [R12.64] ;
LDG.E R14, [R10.64] ;
IMAD.IADD R15, R14, 0x1, R15 ;
LDG.E R14, [R10.64+0x4] ;
STG.E [R10.64], R15 ;
LDG.E R17, [R12.64+0x4] ;
IMAD.IADD R17, R14, 0x1, R17 ;
LDG.E R14, [R10.64+0x8] ;
STG.E [R10.64+0x4], R17 ;
LDG.E R19, [R12.64+0x8] ;
IMAD.IADD R19, R14, 0x1, R19 ;
LDG.E R14, [R10.64+0xc] ;
STG.E [R10.64+0x8], R19 ;
LDG.E R21, [R12.64+0xc] ;
IMAD.IADD R21, R14, 0x1, R21 ;
LDG.E R14, [R10.64+0x10] ;
STG.E [R10.64+0xc], R21 ;
LDG.E R15, [R12.64+0x10] ;
IADD3 R15, R14, R15, RZ ;
LDG.E R14, [R10.64+0x14] ;
STG.E [R10.64+0x10], R15 ;
LDG.E R17, [R12.64+0x14] ;
IMAD.IADD R17, R14, 0x1, R17 ;
LDG.E R14, [R10.64+0x18] ;
STG.E [R10.64+0x14], R17 ;
LDG.E R19, [R12.64+0x18] ;
IMAD.IADD R19, R14, 0x1, R19 ;
LDG.E R14, [R10.64+0x1c] ;
STG.E [R10.64+0x18], R19 ;
LDG.E R21, [R12.64+0x1c] ;
IMAD.IADD R21, R14, 0x1, R21 ;
LDG.E R14, [R10.64+0x20] ;
STG.E [R10.64+0x1c], R21 ;
LDG.E R15, [R12.64+0x20] ;
IMAD.IADD R15, R14, 0x1, R15 ;
LDG.E R14, [R10.64+0x24] ;
STG.E [R10.64+0x20], R15 ;
LDG.E R17, [R12.64+0x24] ;
IADD3 R17, R14, R17, RZ ;
LDG.E R14, [R10.64+0x28] ;
STG.E [R10.64+0x24], R17 ;
LDG.E R19, [R12.64+0x28] ;
IMAD.IADD R19, R14, 0x1, R19 ;
LDG.E R14, [R10.64+0x2c] ;
STG.E [R10.64+0x28], R19 ;
LDG.E R21, [R12.64+0x2c] ;
IMAD.IADD R21, R14, 0x1, R21 ;
LDG.E R14, [R10.64+0x30] ;
STG.E [R10.64+0x2c], R21 ;
LDG.E R15, [R12.64+0x30] ;
IMAD.IADD R15, R14, 0x1, R15 ;
LDG.E R14, [R10.64+0x34] ;
STG.E [R10.64+0x30], R15 ;
LDG.E R17, [R12.64+0x34] ;
IMAD.IADD R17, R14, 0x1, R17 ;
LDG.E R14, [R10.64+0x38] ;
STG.E [R10.64+0x34], R17 ;
LDG.E R19, [R12.64+0x38] ;
IADD3 R19, R14, R19, RZ ;
LDG.E R14, [R10.64+0x3c] ;
STG.E [R10.64+0x38], R19 ;
LDG.E R21, [R12.64+0x3c] ;
IADD3 R6, R6, -0x10, RZ ;
IADD3 R5, R5, 0x10, RZ ;
ISETP.GT.AND P2, PT, R6, 0xc, PT ;
IMAD.IADD R21, R14, 0x1, R21 ;
IADD3 R14, P3, R8, 0x40, RZ ;
STG.E [R10.64+0x3c], R21 ;
IMAD.X R15, RZ, RZ, R9, P3 ;
@P2 BRA 0x220 ;
ISETP.GT.AND P2, PT, R6, 0x4, PT ;
@!P2 BRA 0x950 ;
IMAD.WIDE R8, R2, 0x4, R14 ;
IMAD.WIDE R10, R7, 0x4, R14 ;
LDG.E R12, [R8.64] ;
LDG.E R13, [R10.64] ;
IMAD.IADD R13, R12, 0x1, R13 ;
LDG.E R12, [R8.64+0x4] ;
STG.E [R8.64], R13 ;
LDG.E R17, [R10.64+0x4] ;
IMAD.IADD R17, R12, 0x1, R17 ;
LDG.E R12, [R8.64+0x8] ;
STG.E [R8.64+0x4], R17 ;
LDG.E R19, [R10.64+0x8] ;
IADD3 R19, R12, R19, RZ ;
LDG.E R12, [R8.64+0xc] ;
STG.E [R8.64+0x8], R19 ;
LDG.E R21, [R10.64+0xc] ;
IMAD.IADD R21, R12, 0x1, R21 ;
LDG.E R12, [R8.64+0x10] ;
STG.E [R8.64+0xc], R21 ;
LDG.E R13, [R10.64+0x10] ;
IMAD.IADD R13, R12, 0x1, R13 ;
LDG.E R12, [R8.64+0x14] ;
STG.E [R8.64+0x10], R13 ;
LDG.E R17, [R10.64+0x14] ;
IMAD.IADD R17, R12, 0x1, R17 ;
LDG.E R12, [R8.64+0x18] ;
STG.E [R8.64+0x14], R17 ;
LDG.E R19, [R10.64+0x18] ;
IMAD.IADD R19, R12, 0x1, R19 ;
LDG.E R12, [R8.64+0x1c] ;
STG.E [R8.64+0x18], R19 ;
LDG.E R21, [R10.64+0x1c] ;
IADD3 R14, P2, R14, 0x20, RZ ;
PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ;
IADD3 R5, R5, 0x8, RZ ;
IMAD.X R15, RZ, RZ, R15, P2 ;
IADD3 R6, R6, -0x8, RZ ;
IADD3 R21, R12, R21, RZ ;
STG.E [R8.64+0x1c], R21 ;
ISETP.NE.OR P0, PT, R6, RZ, P0 ;
@!P0 BRA 0xb10 ;
IMAD.MOV.U32 R8, RZ, RZ, R14 ;
IMAD.MOV.U32 R9, RZ, RZ, R15 ;
IMAD.WIDE R12, R7, 0x4, R8 ;
IMAD.WIDE R10, R2, 0x4, R8 ;
LDG.E R15, [R12.64] ;
LDG.E R14, [R10.64] ;
IMAD.IADD R15, R14, 0x1, R15 ;
LDG.E R14, [R10.64+0x4] ;
STG.E [R10.64], R15 ;
LDG.E R17, [R12.64+0x4] ;
IADD3 R17, R14, R17, RZ ;
LDG.E R14, [R10.64+0x8] ;
STG.E [R10.64+0x4], R17 ;
LDG.E R19, [R12.64+0x8] ;
IMAD.IADD R19, R14, 0x1, R19 ;
LDG.E R14, [R10.64+0xc] ;
STG.E [R10.64+0x8], R19 ;
LDG.E R21, [R12.64+0xc] ;
IADD3 R6, R6, -0x4, RZ ;
IADD3 R5, R5, 0x4, RZ ;
ISETP.NE.AND P0, PT, R6, RZ, PT ;
IMAD.IADD R21, R14, 0x1, R21 ;
IADD3 R14, P2, R8, 0x10, RZ ;
STG.E [R10.64+0xc], R21 ;
IMAD.X R15, RZ, RZ, R9, P2 ;
@P0 BRA 0x970 ;
ISETP.NE.AND P0, PT, R3, RZ, PT ;
@!P0 BRA 0xc90 ;
HFMA2.MMA R9, -RZ, RZ, 0, 2.384185791015625e-07 ;
IADD3 R8, R16, UR4, RZ ;
IMAD.IADD R6, R2, 0x1, R5 ;
IMAD R8, R8, c[0x0][0x170], R5 ;
IMAD.WIDE R6, R6, R9, c[0x0][0x160] ;
IMAD.WIDE R8, R8, R9, c[0x0][0x160] ;
LDG.E R5, [R6.64] ;
LDG.E R10, [R8.64] ;
ISETP.NE.AND P0, PT, R3, 0x1, PT ;
IMAD.IADD R5, R5, 0x1, R10 ;
STG.E [R6.64], R5 ;
@!P0 BRA 0xc90 ;
LDG.E R5, [R6.64+0x4] ;
LDG.E R10, [R8.64+0x4] ;
ISETP.NE.AND P0, PT, R3, 0x2, PT ;
IMAD.IADD R5, R5, 0x1, R10 ;
STG.E [R6.64+0x4], R5 ;
@!P0 BRA 0xc90 ;
LDG.E R8, [R8.64+0x8] ;
LDG.E R5, [R6.64+0x8] ;
IMAD.IADD R5, R5, 0x1, R8 ;
STG.E [R6.64+0x8], R5 ;
BSYNC B0 ;
USHF.R.S32.HI UR4, URZ, 0x1, UR4 ;
BAR.SYNC.DEFER_BLOCKING 0x0 ;
ISETP.NE.AND P0, PT, RZ, UR4, PT ;
@P0 BRA 0xd0 ;
ISETP.GE.AND P0, PT, R4, 0x1, PT ;
@!P0 EXIT ;
IADD3 R0, R4, -0x1, RZ ;
UMOV UR4, URZ ;
ISETP.GE.U32.AND P0, PT, R0, 0x3, PT ;
LOP3.LUT R0, R4, 0x3, RZ, 0xc0, !PT ;
@!P0 BRA 0x1400 ;
IADD3 R6, -R0, c[0x0][0x170], RZ ;
UMOV UR4, URZ ;
IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x168] ;
MOV R5, c[0x0][0x16c] ;
IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x160] ;
ISETP.GT.AND P0, PT, R6, RZ, PT ;
IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x164] ;
@!P0 BRA 0x12c0 ;
ISETP.GT.AND P1, PT, R6, 0xc, PT ;
PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ;
@!P1 BRA 0x10d0 ;
PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ;
LDG.E R7, [R2.64] ;
STG.E [R4.64], R7 ;
LDG.E R9, [R2.64+0x4] ;
STG.E [R4.64+0x4], R9 ;
LDG.E R11, [R2.64+0x8] ;
STG.E [R4.64+0x8], R11 ;
LDG.E R13, [R2.64+0xc] ;
STG.E [R4.64+0xc], R13 ;
LDG.E R15, [R2.64+0x10] ;
STG.E [R4.64+0x10], R15 ;
LDG.E R17, [R2.64+0x14] ;
STG.E [R4.64+0x14], R17 ;
LDG.E R7, [R2.64+0x18] ;
STG.E [R4.64+0x18], R7 ;
LDG.E R9, [R2.64+0x1c] ;
STG.E [R4.64+0x1c], R9 ;
LDG.E R11, [R2.64+0x20] ;
STG.E [R4.64+0x20], R11 ;
LDG.E R13, [R2.64+0x24] ;
STG.E [R4.64+0x24], R13 ;
LDG.E R15, [R2.64+0x28] ;
STG.E [R4.64+0x28], R15 ;
LDG.E R17, [R2.64+0x2c] ;
STG.E [R4.64+0x2c], R17 ;
LDG.E R7, [R2.64+0x30] ;
STG.E [R4.64+0x30], R7 ;
LDG.E R9, [R2.64+0x34] ;
STG.E [R4.64+0x34], R9 ;
LDG.E R11, [R2.64+0x38] ;
IADD3 R6, R6, -0x10, RZ ;
ISETP.GT.AND P1, PT, R6, 0xc, PT ;
IADD3 R10, P2, R2, 0x40, RZ ;
STG.E [R4.64+0x38], R11 ;
LDG.E R13, [R2.64+0x3c] ;
IADD3 R8, P3, R4, 0x40, RZ ;
IMAD.X R7, RZ, RZ, R3, P2 ;
UIADD3 UR4, UR4, 0x10, URZ ;
IMAD.X R9, RZ, RZ, R5, P3 ;
MOV R2, R10 ;
IMAD.MOV.U32 R3, RZ, RZ, R7 ;
STG.E [R4.64+0x3c], R13 ;
IMAD.MOV.U32 R4, RZ, RZ, R8 ;
IMAD.MOV.U32 R5, RZ, RZ, R9 ;
@P1 BRA 0xe10 ;
ISETP.GT.AND P1, PT, R6, 0x4, PT ;
@!P1 BRA 0x12a0 ;
LDG.E R7, [R2.64] ;
STG.E [R4.64], R7 ;
LDG.E R9, [R2.64+0x4] ;
STG.E [R4.64+0x4], R9 ;
LDG.E R11, [R2.64+0x8] ;
STG.E [R4.64+0x8], R11 ;
LDG.E R13, [R2.64+0xc] ;
STG.E [R4.64+0xc], R13 ;
LDG.E R15, [R2.64+0x10] ;
STG.E [R4.64+0x10], R15 ;
LDG.E R17, [R2.64+0x14] ;
STG.E [R4.64+0x14], R17 ;
LDG.E R7, [R2.64+0x18] ;
IADD3 R10, P1, R2, 0x20, RZ ;
IADD3 R8, P2, R4, 0x20, RZ ;
STG.E [R4.64+0x18], R7 ;
LDG.E R9, [R2.64+0x1c] ;
IMAD.X R13, RZ, RZ, R3, P1 ;
IADD3.X R11, RZ, R5, RZ, P2, !PT ;
UIADD3 UR4, UR4, 0x8, URZ ;
PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ;
IADD3 R6, R6, -0x8, RZ ;
IMAD.MOV.U32 R2, RZ, RZ, R10 ;
IMAD.MOV.U32 R3, RZ, RZ, R13 ;
STG.E [R4.64+0x1c], R9 ;
IMAD.MOV.U32 R4, RZ, RZ, R8 ;
MOV R5, R11 ;
ISETP.NE.OR P0, PT, R6, RZ, P0 ;
@!P0 BRA 0x1400 ;
LDG.E R7, [R2.64] ;
STG.E [R4.64], R7 ;
LDG.E R9, [R2.64+0x4] ;
STG.E [R4.64+0x4], R9 ;
LDG.E R11, [R2.64+0x8] ;
IADD3 R6, R6, -0x4, RZ ;
ISETP.NE.AND P0, PT, R6, RZ, PT ;
IADD3 R10, P1, R2, 0x10, RZ ;
STG.E [R4.64+0x8], R11 ;
LDG.E R13, [R2.64+0xc] ;
IADD3 R8, P2, R4, 0x10, RZ ;
IMAD.X R7, RZ, RZ, R3, P1 ;
UIADD3 UR4, UR4, 0x4, URZ ;
IMAD.X R9, RZ, RZ, R5, P2 ;
IMAD.MOV.U32 R2, RZ, RZ, R10 ;
MOV R3, R7 ;
STG.E [R4.64+0xc], R13 ;
IMAD.MOV.U32 R4, RZ, RZ, R8 ;
IMAD.MOV.U32 R5, RZ, RZ, R9 ;
@P0 BRA 0x12c0 ;
ISETP.NE.AND P0, PT, R0, RZ, PT ;
@!P0 EXIT ;
UMOV UR5, 0x4 ;
ULDC.64 UR6, c[0x0][0x168] ;
ULDC.64 UR8, c[0x0][0x160] ;
UIMAD.WIDE UR6, UR4, UR5, UR6 ;
UIMAD.WIDE UR4, UR4, UR5, UR8 ;
MOV R3, UR5 ;
IMAD.U32 R2, RZ, RZ, UR4 ;
LDG.E R3, [R2.64] ;
IMAD.U32 R4, RZ, RZ, UR6 ;
IADD3 R0, R0, -0x1, RZ ;
IMAD.U32 R5, RZ, RZ, UR7 ;
UIADD3 UR6, UP0, UR6, 0x4, URZ ;
ISETP.NE.AND P0, PT, R0, RZ, PT ;
UIADD3 UR4, UP1, UR4, 0x4, URZ ;
UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ;
UIADD3.X UR5, URZ, UR5, URZ, UP1, !UPT ;
STG.E [R4.64], R3 ;
@P0 BRA 0x1470 ;
EXIT ;
BRA 0x1550;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
Function : _Z18hist_reduce_kernelPfPiiif
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ;
S2R R0, SR_CTAID.X ;
IMAD.MOV.U32 R3, RZ, RZ, 0x4 ;
ULDC.64 UR4, c[0x0][0x118] ;
S2R R7, SR_TID.X ;
IMAD R4, R0, c[0x0][0x0], R7 ;
IMAD.WIDE R2, R4, R3, c[0x0][0x160] ;
LDG.E R2, [R2.64] ;
ISETP.GE.AND P0, PT, R4, c[0x0][0x170], PT ;
STS [R7.X4], R2 ;
BAR.SYNC.DEFER_BLOCKING 0x0 ;
@P0 EXIT ;
LDS R3, [R7.X4] ;
MUFU.RCP R2, c[0x0][0x178] ;
IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x178] ;
BSSY B0, 0x1a0 ;
FFMA R5, R2, -R5, 1 ;
FFMA R2, R2, R5, R2 ;
FCHK P0, R3, c[0x0][0x178] ;
FFMA R4, R3, R2, RZ ;
FFMA R5, R4, -c[0x0][0x178], R3 ;
FFMA R4, R2, R5, R4 ;
@!P0 BRA 0x190 ;
MOV R2, 0x190 ;
CALL.REL.NOINC 0x210 ;
BSYNC B0 ;
F2I.FLOOR.NTZ R3, R4 ;
IMAD.MOV.U32 R2, RZ, RZ, 0x4 ;
IMAD.MOV.U32 R5, RZ, RZ, 0x1 ;
IMAD R3, R0, c[0x0][0x174], R3 ;
IMAD.WIDE R2, R3, R2, c[0x0][0x168] ;
RED.E.ADD.STRONG.GPU [R2.64], R5 ;
EXIT ;
IMAD.MOV.U32 R11, RZ, RZ, c[0x0][0x178] ;
SHF.R.U32.HI R4, RZ, 0x17, R3.reuse ;
BSSY B1, 0x880 ;
IMAD.MOV.U32 R6, RZ, RZ, R3 ;
SHF.R.U32.HI R5, RZ, 0x17, R11 ;
IMAD.MOV.U32 R7, RZ, RZ, c[0x0][0x178] ;
LOP3.LUT R4, R4, 0xff, RZ, 0xc0, !PT ;
LOP3.LUT R5, R5, 0xff, RZ, 0xc0, !PT ;
IADD3 R9, R4, -0x1, RZ ;
IADD3 R10, R5, -0x1, RZ ;
ISETP.GT.U32.AND P0, PT, R10, 0xfd, PT ;
ISETP.GT.U32.OR P0, PT, R9, 0xfd, P0 ;
@!P0 IMAD.MOV.U32 R8, RZ, RZ, RZ ;
@!P0 BRA 0x460 ;
FSETP.GTU.FTZ.AND P1, PT, |R11|, +INF , PT ;
FSETP.GTU.FTZ.AND P0, PT, |R3|, +INF , PT ;
PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ;
@P0 BRA 0x860 ;
LOP3.LUT P0, RZ, R7, 0x7fffffff, R6, 0xc8, !PT ;
@!P0 BRA 0x840 ;
FSETP.NEU.FTZ.AND P2, PT, |R3|, +INF , PT ;
FSETP.NEU.FTZ.AND P1, PT, |R11|, +INF , PT ;
FSETP.NEU.FTZ.AND P0, PT, |R3|, +INF , PT ;
@!P1 BRA !P2, 0x840 ;
LOP3.LUT P2, RZ, R6, 0x7fffffff, RZ, 0xc0, !PT ;
PLOP3.LUT P1, PT, P1, P2, PT, 0x2a, 0x0 ;
@P1 BRA 0x820 ;
LOP3.LUT P1, RZ, R7, 0x7fffffff, RZ, 0xc0, !PT ;
PLOP3.LUT P0, PT, P0, P1, PT, 0x2a, 0x0 ;
@P0 BRA 0x7f0 ;
ISETP.GE.AND P0, PT, R9, RZ, PT ;
ISETP.GE.AND P1, PT, R10, RZ, PT ;
@P0 IMAD.MOV.U32 R8, RZ, RZ, RZ ;
@!P0 IMAD.MOV.U32 R8, RZ, RZ, -0x40 ;
@!P0 FFMA R6, R3, 1.84467440737095516160e+19, RZ ;
@!P1 FFMA R7, R11, 1.84467440737095516160e+19, RZ ;
@!P1 IADD3 R8, R8, 0x40, RZ ;
LEA R10, R5, 0xc0800000, 0x17 ;
BSSY B2, 0x7e0 ;
IADD3 R4, R4, -0x7f, RZ ;
IMAD.IADD R10, R7, 0x1, -R10 ;
IADD3 R5, R4.reuse, 0x7f, -R5 ;
IMAD R6, R4, -0x800000, R6 ;
MUFU.RCP R3, R10 ;
FADD.FTZ R7, -R10, -RZ ;
IMAD.IADD R5, R5, 0x1, R8 ;
FFMA R12, R3, R7, 1 ;
FFMA R9, R3, R12, R3 ;
FFMA R3, R6, R9, RZ ;
FFMA R12, R7, R3, R6 ;
FFMA R12, R9, R12, R3 ;
FFMA R7, R7, R12, R6 ;
FFMA R3, R9, R7, R12 ;
SHF.R.U32.HI R4, RZ, 0x17, R3 ;
LOP3.LUT R4, R4, 0xff, RZ, 0xc0, !PT ;
IMAD.IADD R8, R4, 0x1, R5 ;
IADD3 R4, R8, -0x1, RZ ;
ISETP.GE.U32.AND P0, PT, R4, 0xfe, PT ;
@!P0 BRA 0x7c0 ;
ISETP.GT.AND P0, PT, R8, 0xfe, PT ;
@P0 BRA 0x790 ;
ISETP.GE.AND P0, PT, R8, 0x1, PT ;
@P0 BRA 0x7d0 ;
ISETP.GE.AND P0, PT, R8, -0x18, PT ;
LOP3.LUT R3, R3, 0x80000000, RZ, 0xc0, !PT ;
@!P0 BRA 0x7d0 ;
FFMA.RZ R4, R9.reuse, R7.reuse, R12.reuse ;
ISETP.NE.AND P2, PT, R8.reuse, RZ, PT ;
FFMA.RM R5, R9.reuse, R7.reuse, R12.reuse ;
ISETP.NE.AND P1, PT, R8, RZ, PT ;
LOP3.LUT R6, R4, 0x7fffff, RZ, 0xc0, !PT ;
FFMA.RP R4, R9, R7, R12 ;
IADD3 R7, R8, 0x20, RZ ;
IMAD.MOV R8, RZ, RZ, -R8 ;
LOP3.LUT R6, R6, 0x800000, RZ, 0xfc, !PT ;
FSETP.NEU.FTZ.AND P0, PT, R4, R5, PT ;
SHF.L.U32 R7, R6, R7, RZ ;
SEL R5, R8, RZ, P2 ;
ISETP.NE.AND P1, PT, R7, RZ, P1 ;
SHF.R.U32.HI R5, RZ, R5, R6 ;
PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ;
SHF.R.U32.HI R7, RZ, 0x1, R5 ;
SEL R4, RZ, 0x1, !P0 ;
LOP3.LUT R4, R4, 0x1, R7, 0xf8, !PT ;
LOP3.LUT R4, R4, R5, RZ, 0xc0, !PT ;
IMAD.IADD R4, R7, 0x1, R4 ;
LOP3.LUT R3, R4, R3, RZ, 0xfc, !PT ;
BRA 0x7d0 ;
LOP3.LUT R3, R3, 0x80000000, RZ, 0xc0, !PT ;
LOP3.LUT R3, R3, 0x7f800000, RZ, 0xfc, !PT ;
BRA 0x7d0 ;
IMAD R3, R5, 0x800000, R3 ;
BSYNC B2 ;
BRA 0x870 ;
LOP3.LUT R3, R7, 0x80000000, R6, 0x48, !PT ;
LOP3.LUT R3, R3, 0x7f800000, RZ, 0xfc, !PT ;
BRA 0x870 ;
LOP3.LUT R3, R7, 0x80000000, R6, 0x48, !PT ;
BRA 0x870 ;
MUFU.RSQ R3, -QNAN ;
BRA 0x870 ;
FADD.FTZ R3, R3, c[0x0][0x178] ;
BSYNC B1 ;
IMAD.MOV.U32 R4, RZ, RZ, R3 ;
IMAD.MOV.U32 R3, RZ, RZ, 0x0 ;
RET.REL.NODEC R2 0x0 ;
BRA 0x8b0;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
Function : _Z16histogram_kernelPfPiii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ;
S2R R2, SR_TID.X ;
ISETP.GE.AND P0, PT, R2, c[0x0][0x170], PT ;
@P0 EXIT ;
IMAD.MOV.U32 R3, RZ, RZ, 0x4 ;
ULDC.64 UR4, c[0x0][0x118] ;
IMAD.WIDE R2, R2, R3, c[0x0][0x160] ;
LDG.E R3, [R2.64] ;
I2F R4, c[0x0][0x174] ;
BSSY B0, 0x160 ;
MUFU.RCP R5, R4 ;
FFMA R0, -R4, R5, 1 ;
FFMA R0, R5, R0, R5 ;
FCHK P0, R3, R4 ;
FFMA R5, R3, R0, RZ ;
FFMA R6, -R4, R5, R3 ;
FFMA R0, R0, R6, R5 ;
@!P0 BRA 0x150 ;
MOV R0, 0x140 ;
CALL.REL.NOINC 0x1e0 ;
IMAD.MOV.U32 R0, RZ, RZ, R4 ;
BSYNC B0 ;
FRND.FLOOR R0, R0 ;
IMAD.MOV.U32 R3, RZ, RZ, 0x4 ;
IMAD.MOV.U32 R5, RZ, RZ, 0x1 ;
FADD R4, R0, 1 ;
F2I.TRUNC.NTZ R2, R4 ;
IMAD.WIDE R2, R2, R3, c[0x0][0x168] ;
RED.E.ADD.STRONG.GPU [R2.64], R5 ;
EXIT ;
SHF.R.U32.HI R5, RZ, 0x17, R4.reuse ;
BSSY B1, 0x840 ;
SHF.R.U32.HI R2, RZ, 0x17, R3.reuse ;
IMAD.MOV.U32 R6, RZ, RZ, R3 ;
LOP3.LUT R5, R5, 0xff, RZ, 0xc0, !PT ;
IMAD.MOV.U32 R7, RZ, RZ, R4 ;
LOP3.LUT R2, R2, 0xff, RZ, 0xc0, !PT ;
IADD3 R10, R5, -0x1, RZ ;
IADD3 R9, R2, -0x1, RZ ;
ISETP.GT.U32.AND P0, PT, R10, 0xfd, PT ;
ISETP.GT.U32.OR P0, PT, R9, 0xfd, P0 ;
@!P0 IMAD.MOV.U32 R8, RZ, RZ, RZ ;
@!P0 BRA 0x420 ;
FSETP.GTU.FTZ.AND P0, PT, |R3|, +INF , PT ;
FSETP.GTU.FTZ.AND P1, PT, |R4|, +INF , PT ;
PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ;
@P0 BRA 0x820 ;
LOP3.LUT P0, RZ, R7, 0x7fffffff, R6, 0xc8, !PT ;
@!P0 BRA 0x800 ;
FSETP.NEU.FTZ.AND P2, PT, |R3|.reuse, +INF , PT ;
FSETP.NEU.FTZ.AND P1, PT, |R4|, +INF , PT ;
FSETP.NEU.FTZ.AND P0, PT, |R3|, +INF , PT ;
@!P1 BRA !P2, 0x800 ;
LOP3.LUT P2, RZ, R6, 0x7fffffff, RZ, 0xc0, !PT ;
PLOP3.LUT P1, PT, P1, P2, PT, 0x2a, 0x0 ;
@P1 BRA 0x7e0 ;
LOP3.LUT P1, RZ, R7, 0x7fffffff, RZ, 0xc0, !PT ;
PLOP3.LUT P0, PT, P0, P1, PT, 0x2a, 0x0 ;
@P0 BRA 0x7b0 ;
ISETP.GE.AND P0, PT, R9, RZ, PT ;
ISETP.GE.AND P1, PT, R10, RZ, PT ;
@P0 IMAD.MOV.U32 R8, RZ, RZ, RZ ;
@!P0 IMAD.MOV.U32 R8, RZ, RZ, -0x40 ;
@!P0 FFMA R6, R3, 1.84467440737095516160e+19, RZ ;
@!P1 FFMA R7, R4, 1.84467440737095516160e+19, RZ ;
@!P1 IADD3 R8, R8, 0x40, RZ ;
LEA R4, R5, 0xc0800000, 0x17 ;
BSSY B2, 0x7a0 ;
IADD3 R2, R2, -0x7f, RZ ;
IMAD.IADD R4, R7, 0x1, -R4 ;
IADD3 R5, R2.reuse, 0x7f, -R5 ;
IMAD R6, R2, -0x800000, R6 ;
MUFU.RCP R3, R4 ;
FADD.FTZ R7, -R4, -RZ ;
IMAD.IADD R5, R5, 0x1, R8 ;
FFMA R10, R3, R7, 1 ;
FFMA R9, R3, R10, R3 ;
FFMA R3, R6, R9, RZ ;
FFMA R10, R7, R3, R6 ;
FFMA R10, R9, R10, R3 ;
FFMA R6, R7, R10, R6 ;
FFMA R3, R9, R6, R10 ;
SHF.R.U32.HI R2, RZ, 0x17, R3 ;
LOP3.LUT R2, R2, 0xff, RZ, 0xc0, !PT ;
IMAD.IADD R8, R2, 0x1, R5 ;
IADD3 R2, R8, -0x1, RZ ;
ISETP.GE.U32.AND P0, PT, R2, 0xfe, PT ;
@!P0 BRA 0x780 ;
ISETP.GT.AND P0, PT, R8, 0xfe, PT ;
@P0 BRA 0x750 ;
ISETP.GE.AND P0, PT, R8, 0x1, PT ;
@P0 BRA 0x790 ;
ISETP.GE.AND P0, PT, R8, -0x18, PT ;
LOP3.LUT R3, R3, 0x80000000, RZ, 0xc0, !PT ;
@!P0 BRA 0x790 ;
FFMA.RZ R2, R9.reuse, R6.reuse, R10.reuse ;
IADD3 R7, R8.reuse, 0x20, RZ ;
FFMA.RM R5, R9.reuse, R6.reuse, R10.reuse ;
ISETP.NE.AND P2, PT, R8, RZ, PT ;
LOP3.LUT R4, R2, 0x7fffff, RZ, 0xc0, !PT ;
FFMA.RP R2, R9, R6, R10 ;
ISETP.NE.AND P1, PT, R8, RZ, PT ;
IMAD.MOV R6, RZ, RZ, -R8 ;
LOP3.LUT R4, R4, 0x800000, RZ, 0xfc, !PT ;
FSETP.NEU.FTZ.AND P0, PT, R2, R5, PT ;
SHF.L.U32 R7, R4, R7, RZ ;
SEL R5, R6, RZ, P2 ;
ISETP.NE.AND P1, PT, R7, RZ, P1 ;
SHF.R.U32.HI R5, RZ, R5, R4 ;
PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ;
SHF.R.U32.HI R7, RZ, 0x1, R5 ;
SEL R2, RZ, 0x1, !P0 ;
LOP3.LUT R2, R2, 0x1, R7, 0xf8, !PT ;
LOP3.LUT R2, R2, R5, RZ, 0xc0, !PT ;
IMAD.IADD R2, R7, 0x1, R2 ;
LOP3.LUT R3, R2, R3, RZ, 0xfc, !PT ;
BRA 0x790 ;
LOP3.LUT R3, R3, 0x80000000, RZ, 0xc0, !PT ;
LOP3.LUT R3, R3, 0x7f800000, RZ, 0xfc, !PT ;
BRA 0x790 ;
IMAD R3, R5, 0x800000, R3 ;
BSYNC B2 ;
BRA 0x830 ;
LOP3.LUT R3, R7, 0x80000000, R6, 0x48, !PT ;
LOP3.LUT R3, R3, 0x7f800000, RZ, 0xfc, !PT ;
BRA 0x830 ;
LOP3.LUT R3, R7, 0x80000000, R6, 0x48, !PT ;
BRA 0x830 ;
MUFU.RSQ R3, -QNAN ;
BRA 0x830 ;
FADD.FTZ R3, R3, R4 ;
BSYNC B1 ;
IMAD.MOV.U32 R4, RZ, RZ, R3 ;
IMAD.MOV.U32 R2, RZ, RZ, R0 ;
IMAD.MOV.U32 R3, RZ, RZ, 0x0 ;
RET.REL.NODEC R2 0x0 ;
BRA 0x880;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
```
|
```amdasm
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z16histogram_kernelPfPiii ; -- Begin function _Z16histogram_kernelPfPiii
.globl _Z16histogram_kernelPfPiii
.p2align 8
.type _Z16histogram_kernelPfPiii,@function
_Z16histogram_kernelPfPiii: ; @_Z16histogram_kernelPfPiii
; %bb.0:
s_load_b64 s[2:3], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
v_cmp_gt_i32_e32 vcc_lo, s2, v0
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_2
; %bb.1:
s_load_b128 s[4:7], s[0:1], 0x0
v_lshlrev_b32_e32 v0, 2, v0
v_cvt_f32_i32_e32 v1, s3
s_waitcnt lgkmcnt(0)
global_load_b32 v0, v0, s[4:5]
s_waitcnt vmcnt(0)
v_div_scale_f32 v2, null, v1, v1, v0
v_div_scale_f32 v5, vcc_lo, v0, v1, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f32_e32 v3, v2
s_waitcnt_depctr 0xfff
v_fma_f32 v4, -v2, v3, 1.0
v_fmac_f32_e32 v3, v4, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v4, v5, v3
v_fma_f32 v6, -v2, v4, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v4, v6, v3
v_fma_f32 v2, -v2, v4, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fmas_f32 v2, v2, v3, v4
v_div_fixup_f32 v0, v2, v1, v0
v_mov_b32_e32 v2, 1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_floor_f32_e32 v0, v0
v_add_f32_e32 v0, 1.0, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_i32_f32_e32 v0, v0
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[0:1]
v_add_co_u32 v0, vcc_lo, s6, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
global_atomic_add_u32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z16histogram_kernelPfPiii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 8
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z16histogram_kernelPfPiii, .Lfunc_end0-_Z16histogram_kernelPfPiii
; -- End function
.section .AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 224
; NumSgprs: 10
; NumVgprs: 7
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 1
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 10
; NumVGPRsForWavesPerEU: 7
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
.text
.protected _Z18hist_reduce_kernelPfPiiif ; -- Begin function _Z18hist_reduce_kernelPfPiiif
.globl _Z18hist_reduce_kernelPfPiiif
.p2align 8
.type _Z18hist_reduce_kernelPfPiiif,@function
_Z18hist_reduce_kernelPfPiiif: ; @_Z18hist_reduce_kernelPfPiiif
; %bb.0:
s_clause 0x1
s_load_b32 s8, s[0:1], 0x2c
s_load_b256 s[0:7], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s7, s8, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[1:2], null, s15, s7, v[0:1]
v_lshl_add_u32 v0, v0, 2, 0
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[1:2]
v_add_co_u32 v2, vcc_lo, s0, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
s_mov_b32 s0, exec_lo
global_load_b32 v2, v[2:3], off
s_waitcnt vmcnt(0)
ds_store_b32 v0, v2
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_cmpx_gt_i32_e64 s4, v1
s_cbranch_execz .LBB1_2
; %bb.1:
ds_load_b32 v0, v0
s_waitcnt lgkmcnt(0)
v_div_scale_f32 v1, null, s6, s6, v0
v_div_scale_f32 v4, vcc_lo, v0, s6, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f32_e32 v2, v1
s_waitcnt_depctr 0xfff
v_fma_f32 v3, -v1, v2, 1.0
v_fmac_f32_e32 v2, v3, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v3, v4, v2
v_fma_f32 v5, -v1, v3, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v3, v5, v2
v_fma_f32 v1, -v1, v3, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fmas_f32 v1, v1, v2, v3
v_div_fixup_f32 v0, v1, s6, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_floor_f32_e32 v0, v0
v_cvt_i32_f32_e32 v0, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s5, v[0:1]
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[0:1], 2, v[1:2]
v_mov_b32_e32 v2, 1
v_add_co_u32 v0, vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_atomic_add_u32 v[0:1], v2, off
.LBB1_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z18hist_reduce_kernelPfPiiif
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z18hist_reduce_kernelPfPiiif, .Lfunc_end1-_Z18hist_reduce_kernelPfPiiif
; -- End function
.section .AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 320
; NumSgprs: 18
; NumVgprs: 6
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 6
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
.text
.protected _Z13reduce_kernelPiS_i ; -- Begin function _Z13reduce_kernelPiS_i
.globl _Z13reduce_kernelPiS_i
.p2align 8
.type _Z13reduce_kernelPiS_i,@function
_Z13reduce_kernelPiS_i: ; @_Z13reduce_kernelPiS_i
; %bb.0:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x24
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b32 s0, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s1, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_lt_u32 s1, 2
s_cbranch_scc1 .LBB2_6
; %bb.1: ; %.lr.ph34
v_mul_lo_u32 v0, v0, s0
s_lshr_b32 s1, s1, 1
s_cmp_lt_i32 s0, 1
s_cselect_b32 s2, -1, 0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_xor_b32 s2, s2, -1
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[1:2], 2, v[0:1]
v_add_co_u32 v1, vcc_lo, s4, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, s5, v2, vcc_lo
.LBB2_2: ; =>This Loop Header: Depth=1
; Child Loop BB2_4 Depth 2
s_mul_i32 s8, s1, s0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_gt_i32_e32 vcc_lo, s8, v0
s_and_b32 s9, vcc_lo, s2
s_and_saveexec_b32 s3, s9
s_cbranch_execz .LBB2_5
; %bb.3: ; %.lr.ph
; in Loop: Header=BB2_2 Depth=1
v_dual_mov_b32 v6, v2 :: v_dual_add_nc_u32 v3, s8, v0
v_mov_b32_e32 v5, v1
s_mov_b32 s8, s0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v4, 31, v3
v_lshlrev_b64 v[3:4], 2, v[3:4]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v3, vcc_lo, s4, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
.LBB2_4: ; Parent Loop BB2_2 Depth=1
; => This Inner Loop Header: Depth=2
global_load_b32 v7, v[3:4], off
global_load_b32 v8, v[5:6], off
s_add_i32 s8, s8, -1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_lg_u32 s8, 0
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v7, v8, v7
global_store_b32 v[5:6], v7, off
v_add_co_u32 v5, vcc_lo, v5, 4
v_add_co_ci_u32_e32 v6, vcc_lo, 0, v6, vcc_lo
v_add_co_u32 v3, vcc_lo, v3, 4
v_add_co_ci_u32_e32 v4, vcc_lo, 0, v4, vcc_lo
s_cbranch_scc1 .LBB2_4
.LBB2_5: ; %Flow60
; in Loop: Header=BB2_2 Depth=1
s_or_b32 exec_lo, exec_lo, s3
s_lshr_b32 s3, s1, 1
s_cmp_lt_u32 s1, 2
s_mov_b32 s1, s3
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
s_cbranch_scc0 .LBB2_2
.LBB2_6: ; %.preheader
s_cmp_lt_i32 s0, 1
s_cbranch_scc1 .LBB2_9
; %bb.7: ; %.lr.ph36.preheader
v_mov_b32_e32 v0, 0
.LBB2_8: ; %.lr.ph36
; =>This Inner Loop Header: Depth=1
global_load_b32 v1, v0, s[4:5]
s_add_i32 s0, s0, -1
s_add_u32 s4, s4, 4
s_addc_u32 s5, s5, 0
s_waitcnt vmcnt(0)
global_store_b32 v0, v1, s[6:7]
s_add_u32 s6, s6, 4
s_addc_u32 s7, s7, 0
s_cmp_eq_u32 s0, 0
s_cbranch_scc0 .LBB2_8
.LBB2_9: ; %._crit_edge
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13reduce_kernelPiS_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 10
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end2:
.size _Z13reduce_kernelPiS_i, .Lfunc_end2-_Z13reduce_kernelPiS_i
; -- End function
.section .AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 364
; NumSgprs: 12
; NumVgprs: 9
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 1
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 12
; NumVGPRsForWavesPerEU: 9
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object ; @__hip_cuid_
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0 ; 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z16histogram_kernelPfPiii
.private_segment_fixed_size: 0
.sgpr_count: 10
.sgpr_spill_count: 0
.symbol: _Z16histogram_kernelPfPiii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
- .offset: 152
.size: 4
.value_kind: hidden_dynamic_lds_size
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z18hist_reduce_kernelPfPiiif
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z18hist_reduce_kernelPfPiiif.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13reduce_kernelPiS_i
.private_segment_fixed_size: 0
.sgpr_count: 12
.sgpr_spill_count: 0
.symbol: _Z13reduce_kernelPiS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
```
| 12,006 | 8,403 |
185 |
Convert the following CUDA host assembly code to AMD host assembly:
```cudaasm
.file "tmpxft_00120198_00000000-6_hist.cudafe1.cpp"
.text
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z12genRandArrayi
.type _Z12genRandArrayi, @function
_Z12genRandArrayi:
.LFB2058:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
movl %edi, %ebx
movslq %edi, %rbp
salq $2, %rbp
movq %rbp, %rdi
call malloc@PLT
movq %rax, %r12
movq %rbp, %rcx
movq %rbp, %rdx
movl $0, %esi
movq %rax, %rdi
call __memset_chk@PLT
testl %ebx, %ebx
jle .L3
movq %r12, %rbx
addq %r12, %rbp
.L5:
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
mulss .LC0(%rip), %xmm0
movss %xmm0, (%rbx)
addq $4, %rbx
cmpq %rbp, %rbx
jne .L5
.L3:
movq %r12, %rax
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size _Z12genRandArrayi, .-_Z12genRandArrayi
.globl _Z40__device_stub__Z16histogram_kernelPfPiiiPfPiii
.type _Z40__device_stub__Z16histogram_kernelPfPiiiPfPiii, @function
_Z40__device_stub__Z16histogram_kernelPfPiiiPfPiii:
.LFB2084:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L12
.L8:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L13
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L12:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z16histogram_kernelPfPiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L8
.L13:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z40__device_stub__Z16histogram_kernelPfPiiiPfPiii, .-_Z40__device_stub__Z16histogram_kernelPfPiiiPfPiii
.globl _Z16histogram_kernelPfPiii
.type _Z16histogram_kernelPfPiii, @function
_Z16histogram_kernelPfPiii:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z40__device_stub__Z16histogram_kernelPfPiiiPfPiii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z16histogram_kernelPfPiii, .-_Z16histogram_kernelPfPiii
.globl _Z43__device_stub__Z18hist_reduce_kernelPfPiiifPfPiiif
.type _Z43__device_stub__Z18hist_reduce_kernelPfPiiifPfPiiif, @function
_Z43__device_stub__Z18hist_reduce_kernelPfPiiifPfPiiif:
.LFB2086:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movss %xmm0, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 4(%rsp), %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L20
.L16:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L21
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L20:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z18hist_reduce_kernelPfPiiif(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L16
.L21:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2086:
.size _Z43__device_stub__Z18hist_reduce_kernelPfPiiifPfPiiif, .-_Z43__device_stub__Z18hist_reduce_kernelPfPiiifPfPiiif
.globl _Z18hist_reduce_kernelPfPiiif
.type _Z18hist_reduce_kernelPfPiiif, @function
_Z18hist_reduce_kernelPfPiiif:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z43__device_stub__Z18hist_reduce_kernelPfPiiifPfPiiif
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _Z18hist_reduce_kernelPfPiiif, .-_Z18hist_reduce_kernelPfPiiif
.globl _Z36__device_stub__Z13reduce_kernelPiS_iPiS_i
.type _Z36__device_stub__Z13reduce_kernelPiS_iPiS_i, @function
_Z36__device_stub__Z13reduce_kernelPiS_iPiS_i:
.LFB2088:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L28
.L24:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L29
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L28:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z13reduce_kernelPiS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L24
.L29:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2088:
.size _Z36__device_stub__Z13reduce_kernelPiS_iPiS_i, .-_Z36__device_stub__Z13reduce_kernelPiS_iPiS_i
.globl _Z13reduce_kernelPiS_i
.type _Z13reduce_kernelPiS_i, @function
_Z13reduce_kernelPiS_i:
.LFB2089:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z36__device_stub__Z13reduce_kernelPiS_iPiS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2089:
.size _Z13reduce_kernelPiS_i, .-_Z13reduce_kernelPiS_i
.globl _Z9histogramPfPiS0_iifi
.type _Z9histogramPfPiS0_iifi, @function
_Z9histogramPfPiS0_iifi:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $104, %rsp
.cfi_def_cfa_offset 160
movq %rdi, (%rsp)
movq %rsi, 8(%rsp)
movq %rdx, 16(%rsp)
movl %ecx, 24(%rsp)
movl %r8d, %r14d
movss %xmm0, 28(%rsp)
movl %r9d, %ebp
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
movslq %ecx, %r13
salq $2, %r13
leaq 40(%rsp), %rdi
movq %r13, %rsi
call cudaMalloc@PLT
movslq %ebp, %r12
movslq %r14d, %rbx
salq $2, %rbx
movq %r12, %r15
imulq %rbx, %r15
leaq 48(%rsp), %rdi
movq %r15, %rsi
call cudaMalloc@PLT
leaq 56(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movq %r15, %rdx
movl $0, %esi
movq 48(%rsp), %rdi
call cudaMemset@PLT
movq %rbx, %rdx
movl $0, %esi
movq 48(%rsp), %rdi
call cudaMemset@PLT
movl $1, %ecx
movq %r13, %rdx
movq (%rsp), %rsi
movq 40(%rsp), %rdi
call cudaMemcpy@PLT
salq $2, %r12
movl %ebp, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl %ebp, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $0, %r9d
movq %r12, %r8
movq 76(%rsp), %rdx
movl $1, %ecx
movq 64(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L37
.L33:
movl %ebp, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $0, %r9d
movq %r12, %r8
movq 76(%rsp), %rdx
movl $1, %ecx
movq 64(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L38
.L34:
movl $2, %ecx
movq %r15, %rdx
movq 48(%rsp), %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $2, %ecx
movq %rbx, %rdx
movq 56(%rsp), %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
movq 48(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rdi
call cudaFree@PLT
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L39
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L37:
.cfi_restore_state
movss 28(%rsp), %xmm0
movl %r14d, %ecx
movl 24(%rsp), %edx
movq 48(%rsp), %rsi
movq 40(%rsp), %rdi
call _Z43__device_stub__Z18hist_reduce_kernelPfPiiifPfPiiif
jmp .L33
.L38:
movl %r14d, %edx
movq 56(%rsp), %rsi
movq 48(%rsp), %rdi
call _Z36__device_stub__Z13reduce_kernelPiS_iPiS_i
jmp .L34
.L39:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size _Z9histogramPfPiS0_iifi, .-_Z9histogramPfPiS0_iifi
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "%d "
.LC3:
.string "\n"
.text
.globl main
.type main, @function
main:
.LFB2059:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
movl $65536, %edi
call _Z12genRandArrayi
movq %rax, %rbx
movl $10240, %edi
call malloc@PLT
movq %rax, %r14
movl $40, %edi
call malloc@PLT
movq %rax, %r13
movl $10240, %edx
movl $0, %esi
movq %r14, %rdi
call memset@PLT
pxor %xmm0, %xmm0
movups %xmm0, 0(%r13)
movups %xmm0, 16(%r13)
movq $0, 32(%r13)
movl $256, %r9d
movss .LC1(%rip), %xmm0
movl $10, %r8d
movl $65536, %ecx
movq %r13, %rdx
movq %r14, %rsi
movq %rbx, %rdi
call _Z9histogramPfPiS0_iifi
movq %r13, %rbx
leaq 40(%r13), %r12
leaq .LC2(%rip), %rbp
.L41:
movl (%rbx), %edx
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %r12, %rbx
jne .L41
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %r14, %rdi
call free@PLT
movq %r13, %rdi
call free@PLT
movl $0, %eax
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2059:
.size main, .-main
.section .rodata.str1.1
.LC5:
.string "_Z13reduce_kernelPiS_i"
.LC6:
.string "_Z18hist_reduce_kernelPfPiiif"
.LC7:
.string "_Z16histogram_kernelPfPiii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2091:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _Z13reduce_kernelPiS_i(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _Z18hist_reduce_kernelPfPiiif(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _Z16histogram_kernelPfPiii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2091:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC0:
.long 805306368
.align 4
.LC1:
.long 1036831949
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
```
|
```amdasm
.text
.file "hist.hip"
.globl _Z31__device_stub__histogram_kernelPfPiii # -- Begin function _Z31__device_stub__histogram_kernelPfPiii
.type _Z31__device_stub__histogram_kernelPfPiii,@function
_Z31__device_stub__histogram_kernelPfPiii: # @_Z31__device_stub__histogram_kernelPfPiii
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $112, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 40(%rsp), %rax
movq %rdi, (%rax)
leaq 32(%rsp), %rdi
movq %rsi, (%rdi)
leaq 12(%rsp), %rsi
movl %edx, (%rsi)
leaq 8(%rsp), %rdx
movl %ecx, (%rdx)
leaq 80(%rsp), %rbx
movq %rax, (%rbx)
movq %rdi, 8(%rbx)
movq %rsi, 16(%rbx)
movq %rdx, 24(%rbx)
leaq 64(%rsp), %r14
leaq 48(%rsp), %r15
leaq 24(%rsp), %r12
leaq 16(%rsp), %r13
movq %r14, %rdi
movq %r15, %rsi
movq %r12, %rdx
movq %r13, %rcx
callq __hipPopCallConfiguration
movq (%r14), %rsi
movl 8(%r14), %edx
movq (%r15), %rcx
movl 8(%r15), %r8d
movl $_Z16histogram_kernelPfPiii, %edi
movq %rbx, %r9
pushq (%r13)
.cfi_adjust_cfa_offset 8
pushq (%r12)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $128, %rsp
.cfi_adjust_cfa_offset -128
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z31__device_stub__histogram_kernelPfPiii, .Lfunc_end0-_Z31__device_stub__histogram_kernelPfPiii
.cfi_endproc
# -- End function
.globl _Z33__device_stub__hist_reduce_kernelPfPiiif # -- Begin function _Z33__device_stub__hist_reduce_kernelPfPiiif
.type _Z33__device_stub__hist_reduce_kernelPfPiiif,@function
_Z33__device_stub__hist_reduce_kernelPfPiiif: # @_Z33__device_stub__hist_reduce_kernelPfPiiif
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $128, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 40(%rsp), %rax
movq %rdi, (%rax)
leaq 32(%rsp), %rdi
movq %rsi, (%rdi)
leaq 12(%rsp), %rsi
movl %edx, (%rsi)
leaq 8(%rsp), %rdx
movl %ecx, (%rdx)
leaq 4(%rsp), %rcx
movss %xmm0, (%rcx)
leaq 80(%rsp), %rbx
movq %rax, (%rbx)
movq %rdi, 8(%rbx)
movq %rsi, 16(%rbx)
movq %rdx, 24(%rbx)
movq %rcx, 32(%rbx)
leaq 64(%rsp), %r14
leaq 48(%rsp), %r15
leaq 24(%rsp), %r12
leaq 16(%rsp), %r13
movq %r14, %rdi
movq %r15, %rsi
movq %r12, %rdx
movq %r13, %rcx
callq __hipPopCallConfiguration
movq (%r14), %rsi
movl 8(%r14), %edx
movq (%r15), %rcx
movl 8(%r15), %r8d
movl $_Z18hist_reduce_kernelPfPiiif, %edi
movq %rbx, %r9
pushq (%r13)
.cfi_adjust_cfa_offset 8
pushq (%r12)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $144, %rsp
.cfi_adjust_cfa_offset -144
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z33__device_stub__hist_reduce_kernelPfPiiif, .Lfunc_end1-_Z33__device_stub__hist_reduce_kernelPfPiiif
.cfi_endproc
# -- End function
.globl _Z28__device_stub__reduce_kernelPiS_i # -- Begin function _Z28__device_stub__reduce_kernelPiS_i
.type _Z28__device_stub__reduce_kernelPiS_i,@function
_Z28__device_stub__reduce_kernelPiS_i: # @_Z28__device_stub__reduce_kernelPiS_i
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $112, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 40(%rsp), %rax
movq %rdi, (%rax)
leaq 32(%rsp), %rcx
movq %rsi, (%rcx)
leaq 12(%rsp), %rsi
movl %edx, (%rsi)
leaq 80(%rsp), %rbx
movq %rax, (%rbx)
movq %rcx, 8(%rbx)
movq %rsi, 16(%rbx)
leaq 64(%rsp), %r14
leaq 48(%rsp), %r15
leaq 24(%rsp), %r12
leaq 16(%rsp), %r13
movq %r14, %rdi
movq %r15, %rsi
movq %r12, %rdx
movq %r13, %rcx
callq __hipPopCallConfiguration
movq (%r14), %rsi
movl 8(%r14), %edx
movq (%r15), %rcx
movl 8(%r15), %r8d
movl $_Z13reduce_kernelPiS_i, %edi
movq %rbx, %r9
pushq (%r13)
.cfi_adjust_cfa_offset 8
pushq (%r12)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $128, %rsp
.cfi_adjust_cfa_offset -128
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size _Z28__device_stub__reduce_kernelPiS_i, .Lfunc_end2-_Z28__device_stub__reduce_kernelPiS_i
.cfi_endproc
# -- End function
.globl _Z9histogramPfPiS0_iifi # -- Begin function _Z9histogramPfPiS0_iifi
.type _Z9histogramPfPiS0_iifi,@function
_Z9histogramPfPiS0_iifi: # @_Z9histogramPfPiS0_iifi
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $72, %rsp
.cfi_def_cfa_offset 128
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %r9d, %ebx
movss %xmm0, 44(%rsp) # 4-byte Spill
movl %r8d, %ebp
movq %rdx, 64(%rsp) # 8-byte Spill
movq %rsi, 56(%rsp) # 8-byte Spill
movq %rdi, 48(%rsp) # 8-byte Spill
movl %ecx, 40(%rsp) # 4-byte Spill
movslq %ecx, %r14
shlq $2, %r14
leaq 32(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
movslq %ebx, %r12
leaq (,%r12,4), %rbx
movl %ebp, 12(%rsp) # 4-byte Spill
movslq %ebp, %r15
movq %rbx, %rsi
imulq %r15, %rsi
leaq 16(%rsp), %rbp
movq %rbp, %rdi
callq hipMalloc
shlq $2, %r15
leaq 24(%rsp), %rdi
movq %r15, %rsi
callq hipMalloc
movq (%rbp), %rdi
movq %r15, %r13
imulq %r12, %r13
xorl %esi, %esi
movq %r13, %rdx
callq hipMemset
movq (%rbp), %rdi
xorl %esi, %esi
movq %r15, %rdx
callq hipMemset
leaq 32(%rsp), %rax
movq (%rax), %rdi
movq 48(%rsp), %rsi # 8-byte Reload
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
movl %r12d, %r14d
btsq $32, %r14
movq %r14, %rdi
movl $1, %esi
movq %r14, %rdx
movl $1, %ecx
movq %rbx, %r8
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_2
# %bb.1:
movq 32(%rsp), %rdi
movq 16(%rsp), %rsi
movl 40(%rsp), %edx # 4-byte Reload
movl 12(%rsp), %ecx # 4-byte Reload
movss 44(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
callq _Z33__device_stub__hist_reduce_kernelPfPiiif
.LBB3_2:
movabsq $4294967296, %rdi # imm = 0x100000000
incq %rdi
movl $1, %esi
movq %r14, %rdx
movl $1, %ecx
movq %rbx, %r8
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_4
# %bb.3:
movq 16(%rsp), %rdi
movq 24(%rsp), %rsi
movl 12(%rsp), %edx # 4-byte Reload
callq _Z28__device_stub__reduce_kernelPiS_i
.LBB3_4:
movq 16(%rsp), %rsi
movq 56(%rsp), %rdi # 8-byte Reload
movq %r13, %rdx
movl $2, %ecx
callq hipMemcpy
movq 24(%rsp), %rsi
movq 64(%rsp), %rdi # 8-byte Reload
movq %r15, %rdx
movl $2, %ecx
callq hipMemcpy
movq 32(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
addq $72, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size _Z9histogramPfPiS0_iifi, .Lfunc_end3-_Z9histogramPfPiS0_iifi
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function _Z12genRandArrayi
.LCPI4_0:
.long 0x30000000 # float 4.65661287E-10
.text
.globl _Z12genRandArrayi
.type _Z12genRandArrayi,@function
_Z12genRandArrayi: # @_Z12genRandArrayi
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
pushq %rax
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %edi, %ebp
movslq %edi, %r14
leaq (,%r14,4), %rsi
movl $1, %edi
callq calloc@PLT
movq %rax, %rbx
testl %r14d, %r14d
jle .LBB4_3
# %bb.1: # %.lr.ph.preheader
movl %ebp, %r14d
xorl %r15d, %r15d
.LBB4_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
callq rand
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
mulss .LCPI4_0(%rip), %xmm0
movss %xmm0, (%rbx,%r15,4)
incq %r15
cmpq %r15, %r14
jne .LBB4_2
.LBB4_3: # %._crit_edge
movq %rbx, %rax
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end4:
.size _Z12genRandArrayi, .Lfunc_end4-_Z12genRandArrayi
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI5_0:
.long 0x3dcccccd # float 0.100000001
.text
.globl main
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $65536, %edi # imm = 0x10000
callq _Z12genRandArrayi
movq %rax, %r15
movl $1, %edi
movl $10240, %esi # imm = 0x2800
callq calloc@PLT
movq %rax, %rbx
movl $1, %edi
movl $40, %esi
callq calloc@PLT
movq %rax, %r14
movss .LCPI5_0(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero
movq %r15, %rdi
movq %rbx, %rsi
movq %rax, %rdx
movl $65536, %ecx # imm = 0x10000
movl $10, %r8d
movl $256, %r9d # imm = 0x100
callq _Z9histogramPfPiS0_iifi
xorl %r15d, %r15d
.LBB5_1: # =>This Inner Loop Header: Depth=1
movl (%r14,%r15,4), %esi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
incq %r15
cmpq $10, %r15
jne .LBB5_1
# %bb.2:
movl $10, %edi
callq putchar@PLT
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
xorl %eax, %eax
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end5:
.size main, .Lfunc_end5-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
movq __hip_gpubin_handle(%rip), %rbx
testq %rbx, %rbx
jne .LBB6_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, %rbx
movq %rax, __hip_gpubin_handle(%rip)
.LBB6_2:
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z16histogram_kernelPfPiii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z18hist_reduce_kernelPfPiiif, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13reduce_kernelPiS_i, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end6:
.size __hip_module_ctor, .Lfunc_end6-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB7_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB7_2:
retq
.Lfunc_end7:
.size __hip_module_dtor, .Lfunc_end7-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z16histogram_kernelPfPiii,@object # @_Z16histogram_kernelPfPiii
.section .rodata,"a",@progbits
.globl _Z16histogram_kernelPfPiii
.p2align 3, 0x0
_Z16histogram_kernelPfPiii:
.quad _Z31__device_stub__histogram_kernelPfPiii
.size _Z16histogram_kernelPfPiii, 8
.type _Z18hist_reduce_kernelPfPiiif,@object # @_Z18hist_reduce_kernelPfPiiif
.globl _Z18hist_reduce_kernelPfPiiif
.p2align 3, 0x0
_Z18hist_reduce_kernelPfPiiif:
.quad _Z33__device_stub__hist_reduce_kernelPfPiiif
.size _Z18hist_reduce_kernelPfPiiif, 8
.type _Z13reduce_kernelPiS_i,@object # @_Z13reduce_kernelPiS_i
.globl _Z13reduce_kernelPiS_i
.p2align 3, 0x0
_Z13reduce_kernelPiS_i:
.quad _Z28__device_stub__reduce_kernelPiS_i
.size _Z13reduce_kernelPiS_i, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%d "
.size .L.str, 4
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z16histogram_kernelPfPiii"
.size .L__unnamed_1, 27
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z18hist_reduce_kernelPfPiiif"
.size .L__unnamed_2, 30
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z13reduce_kernelPiS_i"
.size .L__unnamed_3, 23
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z31__device_stub__histogram_kernelPfPiii
.addrsig_sym _Z33__device_stub__hist_reduce_kernelPfPiiif
.addrsig_sym _Z28__device_stub__reduce_kernelPiS_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z16histogram_kernelPfPiii
.addrsig_sym _Z18hist_reduce_kernelPfPiiif
.addrsig_sym _Z13reduce_kernelPiS_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
```
| 7,136 | 7,514 |
188 |
Convert the following CUDA device assembly code to AMD device assembly:
```cudaasm
code for sm_80
```
|
```amdasm
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object ; @__hip_cuid_
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0 ; 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
```
| 24 | 306 |
189 |
Convert the following CUDA host assembly code to AMD host assembly:
```cudaasm
.file "tmpxft_0015ebf2_00000000-6_input.cudafe1.cpp"
.text
.globl _ZSt21ios_base_library_initv
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB4633:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4633:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .text._ZN3ops5InputD2Ev,"axG",@progbits,_ZN3ops5InputD5Ev,comdat
.align 2
.weak _ZN3ops5InputD2Ev
.type _ZN3ops5InputD2Ev, @function
_ZN3ops5InputD2Ev:
.LFB5596:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movq %rdi, %rbx
leaq 16+_ZTVN3ops2OpE(%rip), %rax
movq %rax, (%rdi)
movq 88(%rdi), %rdi
testq %rdi, %rdi
je .L4
movq 104(%rbx), %rsi
subq %rdi, %rsi
call _ZdlPvm@PLT
.L4:
movq 64(%rbx), %rdi
testq %rdi, %rdi
je .L5
movq 80(%rbx), %rsi
subq %rdi, %rsi
call _ZdlPvm@PLT
.L5:
movq 40(%rbx), %rdi
testq %rdi, %rdi
je .L6
movq 56(%rbx), %rsi
subq %rdi, %rsi
call _ZdlPvm@PLT
.L6:
movq 8(%rbx), %rdi
leaq 24(%rbx), %rax
cmpq %rax, %rdi
je .L3
movq 24(%rbx), %rsi
addq $1, %rsi
call _ZdlPvm@PLT
.L3:
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE5596:
.size _ZN3ops5InputD2Ev, .-_ZN3ops5InputD2Ev
.weak _ZN3ops5InputD1Ev
.set _ZN3ops5InputD1Ev,_ZN3ops5InputD2Ev
.section .text._ZN3ops5InputD0Ev,"axG",@progbits,_ZN3ops5InputD5Ev,comdat
.align 2
.weak _ZN3ops5InputD0Ev
.type _ZN3ops5InputD0Ev, @function
_ZN3ops5InputD0Ev:
.LFB5598:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movq %rdi, %rbx
leaq 16+_ZTVN3ops2OpE(%rip), %rax
movq %rax, (%rdi)
movq 88(%rdi), %rdi
testq %rdi, %rdi
je .L10
movq 104(%rbx), %rsi
subq %rdi, %rsi
call _ZdlPvm@PLT
.L10:
movq 64(%rbx), %rdi
testq %rdi, %rdi
je .L11
movq 80(%rbx), %rsi
subq %rdi, %rsi
call _ZdlPvm@PLT
.L11:
movq 40(%rbx), %rdi
testq %rdi, %rdi
je .L12
movq 56(%rbx), %rsi
subq %rdi, %rsi
call _ZdlPvm@PLT
.L12:
movq 8(%rbx), %rdi
leaq 24(%rbx), %rax
cmpq %rax, %rdi
je .L13
movq 24(%rbx), %rax
leaq 1(%rax), %rsi
call _ZdlPvm@PLT
.L13:
movl $128, %esi
movq %rbx, %rdi
call _ZdlPvm@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE5598:
.size _ZN3ops5InputD0Ev, .-_ZN3ops5InputD0Ev
.text
.align 2
.globl _ZN3ops5Input7compileEv
.type _ZN3ops5Input7compileEv, @function
_ZN3ops5Input7compileEv:
.LFB4619:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA4619
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
movq %rsp, %rbp
.cfi_def_cfa_register 6
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $104, %rsp
.cfi_offset 15, -24
.cfi_offset 14, -32
.cfi_offset 13, -40
.cfi_offset 12, -48
.cfi_offset 3, -56
movq %rdi, %rbx
movq %fs:40, %rax
movq %rax, -56(%rbp)
xorl %eax, %eax
.LEHB0:
call _ZN3ops5Graph8instanceEv@PLT
movq %rax, %r13
call _ZN3ops5Graph8instanceEv@PLT
movq %rax, %rdi
call _ZN3ops5Graph16input_shapes_getEv@PLT
leaq 8(%rax), %rdx
movq 16(%rax), %rax
testq %rax, %rax
je .L38
movq %rdx, %r15
jmp .L19
.L17:
movq 24(%rax), %rax
.L18:
testq %rax, %rax
je .L46
.L19:
cmpq %rbx, 32(%rax)
jb .L17
movq %rax, %r15
movq 16(%rax), %rax
jmp .L18
.L46:
cmpq %r15, %rdx
je .L16
cmpq 32(%r15), %rbx
cmovnb %r15, %rdx
movq %rdx, %r15
.L16:
movq 48(%r15), %rax
movq $0, -144(%rbp)
movq $0, -136(%rbp)
movq $0, -128(%rbp)
subq 40(%r15), %rax
movq %rax, %r14
je .L39
movabsq $9223372036854775804, %rax
cmpq %r14, %rax
jb .L47
movq %r14, %rdi
call _Znwm@PLT
.LEHE0:
movq %rax, %r12
.L20:
movq %r12, -144(%rbp)
movq %r12, -136(%rbp)
leaq (%r12,%r14), %rax
movq %rax, -128(%rbp)
movq 40(%r15), %rsi
movq 48(%r15), %rdx
subq %rsi, %rdx
movq %rdx, %r15
cmpq $4, %rdx
jle .L23
movq %r12, %rdi
call memmove@PLT
.L24:
addq %r15, %r12
movq %r12, -136(%rbp)
leaq -144(%rbp), %rdi
.LEHB1:
call _ZNK3ops5Shape5totalEv@PLT
.LEHE1:
jmp .L48
.L38:
movq %rdx, %r15
jmp .L16
.L47:
movq -56(%rbp), %rax
subq %fs:40, %rax
jne .L49
.LEHB2:
call _ZSt28__throw_bad_array_new_lengthv@PLT
.LEHE2:
.L49:
call __stack_chk_fail@PLT
.L39:
movl $0, %r12d
jmp .L20
.L23:
cmpq $4, %rdx
jne .L24
movl (%rsi), %eax
movl %eax, (%r12)
jmp .L24
.L48:
movslq %eax, %rdi
.LEHB3:
call _Z12tensor_allocm@PLT
.LEHE3:
movq %rax, %r14
movq %rax, 120(%rbx)
movq $0, -80(%rbp)
movq $0, -72(%rbp)
movq $0, -64(%rbp)
movl $8, %edi
.LEHB4:
call _Znwm@PLT
.LEHE4:
movq %rax, -80(%rbp)
leaq 8(%rax), %rdx
movq %rdx, -64(%rbp)
movq %r14, (%rax)
movq %rdx, -72(%rbp)
movq $0, -112(%rbp)
movq $0, -104(%rbp)
movq $0, -96(%rbp)
leaq -80(%rbp), %rcx
leaq -112(%rbp), %rdx
subq $8, %rsp
pushq %r14
leaq -144(%rbp), %r9
movl $0, %r8d
movq %rbx, %rsi
movq %r13, %rdi
.LEHB5:
.cfi_escape 0x2e,0x10
call _ZN3ops5Graph12add_compiledEPNS_2OpESt6vectorIPN2rt4NodeESaIS6_EES3_IPfSaIS9_EES6_RKNS_5ShapeES9_@PLT
.LEHE5:
addq $16, %rsp
movq -112(%rbp), %rdi
testq %rdi, %rdi
je .L29
movq -96(%rbp), %rsi
subq %rdi, %rsi
call _ZdlPvm@PLT
.L29:
movq -80(%rbp), %rdi
testq %rdi, %rdi
je .L30
movq -64(%rbp), %rsi
subq %rdi, %rsi
call _ZdlPvm@PLT
.L30:
movq -144(%rbp), %rdi
testq %rdi, %rdi
je .L15
movq -128(%rbp), %rsi
subq %rdi, %rsi
call _ZdlPvm@PLT
.L15:
movq -56(%rbp), %rax
subq %fs:40, %rax
jne .L50
leaq -40(%rbp), %rsp
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
popq %rbp
.cfi_remember_state
.cfi_def_cfa 7, 8
ret
.L42:
.cfi_restore_state
endbr64
movq %rax, %rbx
movq -80(%rbp), %rdi
movq -64(%rbp), %rsi
subq %rdi, %rsi
testq %rdi, %rdi
je .L28
call _ZdlPvm@PLT
.L28:
movq -144(%rbp), %rdi
movq -128(%rbp), %rsi
subq %rdi, %rsi
testq %rdi, %rdi
je .L35
call _ZdlPvm@PLT
.L35:
movq -56(%rbp), %rax
subq %fs:40, %rax
je .L36
call __stack_chk_fail@PLT
.L41:
endbr64
movq %rax, %rbx
movq -112(%rbp), %rdi
movq -96(%rbp), %rsi
subq %rdi, %rsi
testq %rdi, %rdi
je .L33
call _ZdlPvm@PLT
.L33:
movq -80(%rbp), %rdi
movq -64(%rbp), %rsi
subq %rdi, %rsi
testq %rdi, %rdi
je .L28
call _ZdlPvm@PLT
jmp .L28
.L40:
endbr64
movq %rax, %rbx
jmp .L28
.L36:
movq %rbx, %rdi
.LEHB6:
call _Unwind_Resume@PLT
.LEHE6:
.L50:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4619:
.globl __gxx_personality_v0
.section .gcc_except_table,"a",@progbits
.LLSDA4619:
.byte 0xff
.byte 0xff
.byte 0x1
.uleb128 .LLSDACSE4619-.LLSDACSB4619
.LLSDACSB4619:
.uleb128 .LEHB0-.LFB4619
.uleb128 .LEHE0-.LEHB0
.uleb128 0
.uleb128 0
.uleb128 .LEHB1-.LFB4619
.uleb128 .LEHE1-.LEHB1
.uleb128 .L40-.LFB4619
.uleb128 0
.uleb128 .LEHB2-.LFB4619
.uleb128 .LEHE2-.LEHB2
.uleb128 0
.uleb128 0
.uleb128 .LEHB3-.LFB4619
.uleb128 .LEHE3-.LEHB3
.uleb128 .L40-.LFB4619
.uleb128 0
.uleb128 .LEHB4-.LFB4619
.uleb128 .LEHE4-.LEHB4
.uleb128 .L42-.LFB4619
.uleb128 0
.uleb128 .LEHB5-.LFB4619
.uleb128 .LEHE5-.LEHB5
.uleb128 .L41-.LFB4619
.uleb128 0
.uleb128 .LEHB6-.LFB4619
.uleb128 .LEHE6-.LEHB6
.uleb128 0
.uleb128 0
.LLSDACSE4619:
.text
.size _ZN3ops5Input7compileEv, .-_ZN3ops5Input7compileEv
.globl _ZN3ops40_GLOBAL__N__bc94d801_8_input_cu_8eebd9b59unique_idEv
.hidden _ZN3ops40_GLOBAL__N__bc94d801_8_input_cu_8eebd9b59unique_idEv
.type _ZN3ops40_GLOBAL__N__bc94d801_8_input_cu_8eebd9b59unique_idEv, @function
_ZN3ops40_GLOBAL__N__bc94d801_8_input_cu_8eebd9b59unique_idEv:
.LFB4601:
.cfi_startproc
endbr64
movq _ZZN3ops40_GLOBAL__N__bc94d801_8_input_cu_8eebd9b59unique_idEvE3res(%rip), %rax
leaq 1(%rax), %rdx
movq %rdx, _ZZN3ops40_GLOBAL__N__bc94d801_8_input_cu_8eebd9b59unique_idEvE3res(%rip)
ret
.cfi_endproc
.LFE4601:
.size _ZN3ops40_GLOBAL__N__bc94d801_8_input_cu_8eebd9b59unique_idEv, .-_ZN3ops40_GLOBAL__N__bc94d801_8_input_cu_8eebd9b59unique_idEv
.align 2
.globl _ZNK3ops5Input8input_idEv
.type _ZNK3ops5Input8input_idEv, @function
_ZNK3ops5Input8input_idEv:
.LFB4618:
.cfi_startproc
endbr64
movq 112(%rdi), %rax
ret
.cfi_endproc
.LFE4618:
.size _ZNK3ops5Input8input_idEv, .-_ZNK3ops5Input8input_idEv
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB4656:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4656:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .text._ZNSt6vectorIPN3ops2OpESaIS2_EED2Ev,"axG",@progbits,_ZNSt6vectorIPN3ops2OpESaIS2_EED5Ev,comdat
.align 2
.weak _ZNSt6vectorIPN3ops2OpESaIS2_EED2Ev
.type _ZNSt6vectorIPN3ops2OpESaIS2_EED2Ev, @function
_ZNSt6vectorIPN3ops2OpESaIS2_EED2Ev:
.LFB4993:
.cfi_startproc
endbr64
movq (%rdi), %rax
testq %rax, %rax
je .L58
subq $8, %rsp
.cfi_def_cfa_offset 16
movq 16(%rdi), %rsi
subq %rax, %rsi
movq %rax, %rdi
call _ZdlPvm@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.L58:
ret
.cfi_endproc
.LFE4993:
.size _ZNSt6vectorIPN3ops2OpESaIS2_EED2Ev, .-_ZNSt6vectorIPN3ops2OpESaIS2_EED2Ev
.weak _ZNSt6vectorIPN3ops2OpESaIS2_EED1Ev
.set _ZNSt6vectorIPN3ops2OpESaIS2_EED1Ev,_ZNSt6vectorIPN3ops2OpESaIS2_EED2Ev
.text
.align 2
.globl _ZN3ops5InputC2ERKNS_5ShapeE
.type _ZN3ops5InputC2ERKNS_5ShapeE, @function
_ZN3ops5InputC2ERKNS_5ShapeE:
.LFB4616:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA4616
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $112, %rsp
.cfi_def_cfa_offset 128
movq %rdi, %rbx
movq %rsi, %rdx
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
movq $0, 32(%rsp)
movq $0, 40(%rsp)
movq $0, 48(%rsp)
movq $0, (%rsp)
movq $0, 8(%rsp)
movq $0, 16(%rsp)
leaq 64(%rsp), %rsi
leaq 80(%rsp), %rax
movq %rax, 64(%rsp)
movl $1970302569, 80(%rsp)
movb $116, 84(%rsp)
movq $5, 72(%rsp)
movb $0, 85(%rsp)
movq %rsp, %rcx
leaq 32(%rsp), %r8
.LEHB7:
call _ZN3ops2OpC2ERKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEERKNS_5ShapeESt6vectorIPS0_SaISD_EESF_@PLT
.LEHE7:
movq 64(%rsp), %rdi
leaq 80(%rsp), %rax
cmpq %rax, %rdi
je .L62
movq 80(%rsp), %rax
leaq 1(%rax), %rsi
call _ZdlPvm@PLT
.L62:
movq (%rsp), %rdi
testq %rdi, %rdi
je .L63
movq 16(%rsp), %rsi
subq %rdi, %rsi
call _ZdlPvm@PLT
.L63:
movq 32(%rsp), %rdi
testq %rdi, %rdi
je .L64
movq 48(%rsp), %rsi
subq %rdi, %rsi
call _ZdlPvm@PLT
.L64:
leaq 16+_ZTVN3ops5InputE(%rip), %rax
movq %rax, (%rbx)
call _ZN3ops40_GLOBAL__N__bc94d801_8_input_cu_8eebd9b59unique_idEv
movq %rax, 112(%rbx)
movq $0, 120(%rbx)
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L71
addq $112, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L68:
.cfi_restore_state
endbr64
movq %rax, %rbx
leaq 64(%rsp), %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
movq %rsp, %rdi
call _ZNSt6vectorIPN3ops2OpESaIS2_EED1Ev
leaq 32(%rsp), %rdi
call _ZNSt6vectorIPN3ops2OpESaIS2_EED1Ev
movq 104(%rsp), %rax
subq %fs:40, %rax
je .L66
call __stack_chk_fail@PLT
.L66:
movq %rbx, %rdi
.LEHB8:
call _Unwind_Resume@PLT
.LEHE8:
.L71:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4616:
.section .gcc_except_table
.LLSDA4616:
.byte 0xff
.byte 0xff
.byte 0x1
.uleb128 .LLSDACSE4616-.LLSDACSB4616
.LLSDACSB4616:
.uleb128 .LEHB7-.LFB4616
.uleb128 .LEHE7-.LEHB7
.uleb128 .L68-.LFB4616
.uleb128 0
.uleb128 .LEHB8-.LFB4616
.uleb128 .LEHE8-.LEHB8
.uleb128 0
.uleb128 0
.LLSDACSE4616:
.text
.size _ZN3ops5InputC2ERKNS_5ShapeE, .-_ZN3ops5InputC2ERKNS_5ShapeE
.globl _ZN3ops5InputC1ERKNS_5ShapeE
.set _ZN3ops5InputC1ERKNS_5ShapeE,_ZN3ops5InputC2ERKNS_5ShapeE
.weak _ZTSN3ops5InputE
.section .rodata._ZTSN3ops5InputE,"aG",@progbits,_ZTSN3ops5InputE,comdat
.align 8
.type _ZTSN3ops5InputE, @object
.size _ZTSN3ops5InputE, 13
_ZTSN3ops5InputE:
.string "N3ops5InputE"
.weak _ZTIN3ops5InputE
.section .data.rel.ro._ZTIN3ops5InputE,"awG",@progbits,_ZTIN3ops5InputE,comdat
.align 8
.type _ZTIN3ops5InputE, @object
.size _ZTIN3ops5InputE, 24
_ZTIN3ops5InputE:
.quad _ZTVN10__cxxabiv120__si_class_type_infoE+16
.quad _ZTSN3ops5InputE
.quad _ZTIN3ops2OpE
.weak _ZTVN3ops5InputE
.section .data.rel.ro._ZTVN3ops5InputE,"awG",@progbits,_ZTVN3ops5InputE,comdat
.align 8
.type _ZTVN3ops5InputE, @object
.size _ZTVN3ops5InputE, 48
_ZTVN3ops5InputE:
.quad 0
.quad _ZTIN3ops5InputE
.quad _ZN3ops5InputD1Ev
.quad _ZN3ops5InputD0Ev
.quad _ZN3ops5Input7compileEv
.quad _ZN3ops2Op10child_gradEmPS0_
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZZN3ops40_GLOBAL__N__bc94d801_8_input_cu_8eebd9b59unique_idEvE3res
.comm _ZZN3ops40_GLOBAL__N__bc94d801_8_input_cu_8eebd9b59unique_idEvE3res,8,8
.hidden DW.ref.__gxx_personality_v0
.weak DW.ref.__gxx_personality_v0
.section .data.rel.local.DW.ref.__gxx_personality_v0,"awG",@progbits,DW.ref.__gxx_personality_v0,comdat
.align 8
.type DW.ref.__gxx_personality_v0, @object
.size DW.ref.__gxx_personality_v0, 8
DW.ref.__gxx_personality_v0:
.quad __gxx_personality_v0
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
```
|
```amdasm
.text
.file "input.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _ZN3ops5InputC2ERKNS_5ShapeE # -- Begin function _ZN3ops5InputC2ERKNS_5ShapeE
.p2align 1, 0x90
.type _ZN3ops5InputC2ERKNS_5ShapeE,@function
_ZN3ops5InputC2ERKNS_5ShapeE: # @_ZN3ops5InputC2ERKNS_5ShapeE
.Lfunc_begin0:
.cfi_startproc
.cfi_personality 3, __gxx_personality_v0
.cfi_lsda 3, .Lexception0
# %bb.0: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_.exit
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $88, %rsp
.cfi_def_cfa_offset 128
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rsi, %r14
movq %rdi, %rbx
leaq 72(%rsp), %r12
movq %r12, -16(%r12)
leaq 56(%rsp), %r15
movl $.L.str, %esi
movl $.L.str+5, %edx
movq %r15, %rdi
callq _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_M_constructIPKcEEvT_S8_St20forward_iterator_tag
xorl %eax, %eax
leaq 32(%rsp), %rcx
movq %rax, 16(%rcx)
xorps %xmm0, %xmm0
movaps %xmm0, (%rcx)
movq %rsp, %r8
movaps %xmm0, (%r8)
movq %rax, 16(%r8)
.Ltmp0:
movq %rbx, %rdi
movq %r15, %rsi
movq %r14, %rdx
callq _ZN3ops2OpC2ERKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEERKNS_5ShapeESt6vectorIPS0_SaISD_EESF_
.Ltmp1:
# %bb.1:
movq (%rsp), %rdi
testq %rdi, %rdi
je .LBB0_3
# %bb.2:
callq _ZdlPv
.LBB0_3: # %_ZNSt6vectorIPN3ops2OpESaIS2_EED2Ev.exit
movq 32(%rsp), %rdi
testq %rdi, %rdi
je .LBB0_5
# %bb.4:
callq _ZdlPv
.LBB0_5: # %_ZNSt6vectorIPN3ops2OpESaIS2_EED2Ev.exit6
movq 56(%rsp), %rdi
cmpq %r12, %rdi
je .LBB0_7
# %bb.6: # %_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE11_M_is_localEv.exit.i.i
callq _ZdlPv
.LBB0_7: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev.exit
movq $_ZTVN3ops5InputE+16, (%rbx)
movq _ZZN3ops12_GLOBAL__N_19unique_idEvE3res(%rip), %rax
leaq 1(%rax), %rcx
movq %rcx, _ZZN3ops12_GLOBAL__N_19unique_idEvE3res(%rip)
movq %rax, 112(%rbx)
movq $0, 120(%rbx)
addq $88, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB0_8:
.cfi_def_cfa_offset 128
.Ltmp2:
movq %rax, %rbx
movq (%rsp), %rdi
testq %rdi, %rdi
je .LBB0_10
# %bb.9:
callq _ZdlPv
.LBB0_10: # %_ZNSt6vectorIPN3ops2OpESaIS2_EED2Ev.exit8
movq 32(%rsp), %rdi
testq %rdi, %rdi
je .LBB0_12
# %bb.11:
callq _ZdlPv
.LBB0_12: # %_ZNSt6vectorIPN3ops2OpESaIS2_EED2Ev.exit10
movq 56(%rsp), %rdi
cmpq %r12, %rdi
je .LBB0_14
# %bb.13: # %_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE11_M_is_localEv.exit.i.i11
callq _ZdlPv
.LBB0_14: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev.exit13
movq %rbx, %rdi
callq _Unwind_Resume@PLT
.Lfunc_end0:
.size _ZN3ops5InputC2ERKNS_5ShapeE, .Lfunc_end0-_ZN3ops5InputC2ERKNS_5ShapeE
.cfi_endproc
.section .gcc_except_table,"a",@progbits
.p2align 2, 0x0
GCC_except_table0:
.Lexception0:
.byte 255 # @LPStart Encoding = omit
.byte 255 # @TType Encoding = omit
.byte 1 # Call site Encoding = uleb128
.uleb128 .Lcst_end0-.Lcst_begin0
.Lcst_begin0:
.uleb128 .Lfunc_begin0-.Lfunc_begin0 # >> Call Site 1 <<
.uleb128 .Ltmp0-.Lfunc_begin0 # Call between .Lfunc_begin0 and .Ltmp0
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp0-.Lfunc_begin0 # >> Call Site 2 <<
.uleb128 .Ltmp1-.Ltmp0 # Call between .Ltmp0 and .Ltmp1
.uleb128 .Ltmp2-.Lfunc_begin0 # jumps to .Ltmp2
.byte 0 # On action: cleanup
.uleb128 .Ltmp1-.Lfunc_begin0 # >> Call Site 3 <<
.uleb128 .Lfunc_end0-.Ltmp1 # Call between .Ltmp1 and .Lfunc_end0
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.Lcst_end0:
.p2align 2, 0x0
# -- End function
.text
.globl _ZNK3ops5Input8input_idEv # -- Begin function _ZNK3ops5Input8input_idEv
.p2align 1, 0x90
.type _ZNK3ops5Input8input_idEv,@function
_ZNK3ops5Input8input_idEv: # @_ZNK3ops5Input8input_idEv
.cfi_startproc
# %bb.0:
movq 112(%rdi), %rax
retq
.Lfunc_end1:
.size _ZNK3ops5Input8input_idEv, .Lfunc_end1-_ZNK3ops5Input8input_idEv
.cfi_endproc
# -- End function
.globl _ZN3ops5Input7compileEv # -- Begin function _ZN3ops5Input7compileEv
.p2align 1, 0x90
.type _ZN3ops5Input7compileEv,@function
_ZN3ops5Input7compileEv: # @_ZN3ops5Input7compileEv
.Lfunc_begin1:
.cfi_startproc
.cfi_personality 3, __gxx_personality_v0
.cfi_lsda 3, .Lexception1
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $96, %rsp
.cfi_def_cfa_offset 128
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rdi, %rbx
callq _ZN3ops5Graph8instanceEv
movq %rax, %r14
callq _ZN3ops5Graph8instanceEv
movq %rax, %rdi
callq _ZN3ops5Graph16input_shapes_getEv
movq 16(%rax), %rcx
addq $8, %rax
testq %rcx, %rcx
je .LBB2_5
# %bb.1: # %.lr.ph.i.i.i.preheader
movq %rax, %rdx
.LBB2_2: # %.lr.ph.i.i.i
# =>This Inner Loop Header: Depth=1
xorl %esi, %esi
cmpq %rbx, 32(%rcx)
setb %sil
cmovaeq %rcx, %rdx
movq 16(%rcx,%rsi,8), %rcx
testq %rcx, %rcx
jne .LBB2_2
# %bb.3: # %_ZNKSt8_Rb_treeIPN3ops5InputESt4pairIKS2_NS0_5ShapeEESt10_Select1stIS6_ESt4lessIS2_ESaIS6_EE14_M_lower_boundEPKSt13_Rb_tree_nodeIS6_EPKSt18_Rb_tree_node_baseRS4_.exit.i.i
cmpq %rax, %rdx
je .LBB2_5
# %bb.4:
cmpq %rbx, 32(%rdx)
cmovbeq %rdx, %rax
.LBB2_5: # %_ZNKSt3mapIPN3ops5InputENS0_5ShapeESt4lessIS2_ESaISt4pairIKS2_S3_EEE4findERS7_.exit
addq $40, %rax
leaq 64(%rsp), %r15
movq %r15, %rdi
movq %rax, %rsi
callq _ZNSt6vectorIiSaIiEEC2ERKS1_
.Ltmp3:
movq %r15, %rdi
callq _ZNK3ops5Shape5totalEv
.Ltmp4:
# %bb.6:
movslq %eax, %rdi
.Ltmp5:
callq _Z12tensor_allocm
.Ltmp6:
# %bb.7:
movq %rax, 120(%rbx)
xorps %xmm0, %xmm0
movaps %xmm0, 16(%rsp)
movq $0, 32(%rsp)
leaq 88(%rsp), %rsi
movq %rax, (%rsi)
.Ltmp8:
leaq 40(%rsp), %rdi
leaq 15(%rsp), %rcx
movl $1, %edx
callq _ZNSt6vectorIPfSaIS0_EEC2ESt16initializer_listIS0_ERKS1_
.Ltmp9:
# %bb.8:
movq 120(%rbx), %rax
.Ltmp11:
movq %rax, (%rsp)
leaq 16(%rsp), %rdx
leaq 40(%rsp), %rcx
leaq 64(%rsp), %r9
movq %r14, %rdi
movq %rbx, %rsi
xorl %r8d, %r8d
callq _ZN3ops5Graph12add_compiledEPNS_2OpESt6vectorIPN2rt4NodeESaIS6_EES3_IPfSaIS9_EES6_RKNS_5ShapeES9_
.Ltmp12:
# %bb.9:
movq 40(%rsp), %rdi
testq %rdi, %rdi
je .LBB2_11
# %bb.10:
callq _ZdlPv
.LBB2_11: # %_ZNSt6vectorIPfSaIS0_EED2Ev.exit
movq 16(%rsp), %rdi
testq %rdi, %rdi
je .LBB2_13
# %bb.12:
callq _ZdlPv
.LBB2_13: # %_ZNSt6vectorIPN2rt4NodeESaIS2_EED2Ev.exit
movq 64(%rsp), %rdi
testq %rdi, %rdi
je .LBB2_15
# %bb.14:
callq _ZdlPv
.LBB2_15: # %_ZN3ops5ShapeD2Ev.exit
addq $96, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB2_18:
.cfi_def_cfa_offset 128
.Ltmp13:
movq %rax, %rbx
movq 40(%rsp), %rdi
testq %rdi, %rdi
je .LBB2_20
# %bb.19:
callq _ZdlPv
jmp .LBB2_20
.LBB2_17:
.Ltmp10:
movq %rax, %rbx
.LBB2_20: # %_ZNSt6vectorIPfSaIS0_EED2Ev.exit11
movq 16(%rsp), %rdi
testq %rdi, %rdi
je .LBB2_22
# %bb.21:
callq _ZdlPv
jmp .LBB2_22
.LBB2_16:
.Ltmp7:
movq %rax, %rbx
.LBB2_22: # %_ZNSt6vectorIPN2rt4NodeESaIS2_EED2Ev.exit13
movq 64(%rsp), %rdi
testq %rdi, %rdi
je .LBB2_24
# %bb.23:
callq _ZdlPv
.LBB2_24: # %_ZN3ops5ShapeD2Ev.exit15
movq %rbx, %rdi
callq _Unwind_Resume@PLT
.Lfunc_end2:
.size _ZN3ops5Input7compileEv, .Lfunc_end2-_ZN3ops5Input7compileEv
.cfi_endproc
.section .gcc_except_table,"a",@progbits
.p2align 2, 0x0
GCC_except_table2:
.Lexception1:
.byte 255 # @LPStart Encoding = omit
.byte 255 # @TType Encoding = omit
.byte 1 # Call site Encoding = uleb128
.uleb128 .Lcst_end1-.Lcst_begin1
.Lcst_begin1:
.uleb128 .Lfunc_begin1-.Lfunc_begin1 # >> Call Site 1 <<
.uleb128 .Ltmp3-.Lfunc_begin1 # Call between .Lfunc_begin1 and .Ltmp3
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp3-.Lfunc_begin1 # >> Call Site 2 <<
.uleb128 .Ltmp6-.Ltmp3 # Call between .Ltmp3 and .Ltmp6
.uleb128 .Ltmp7-.Lfunc_begin1 # jumps to .Ltmp7
.byte 0 # On action: cleanup
.uleb128 .Ltmp8-.Lfunc_begin1 # >> Call Site 3 <<
.uleb128 .Ltmp9-.Ltmp8 # Call between .Ltmp8 and .Ltmp9
.uleb128 .Ltmp10-.Lfunc_begin1 # jumps to .Ltmp10
.byte 0 # On action: cleanup
.uleb128 .Ltmp11-.Lfunc_begin1 # >> Call Site 4 <<
.uleb128 .Ltmp12-.Ltmp11 # Call between .Ltmp11 and .Ltmp12
.uleb128 .Ltmp13-.Lfunc_begin1 # jumps to .Ltmp13
.byte 0 # On action: cleanup
.uleb128 .Ltmp12-.Lfunc_begin1 # >> Call Site 5 <<
.uleb128 .Lfunc_end2-.Ltmp12 # Call between .Ltmp12 and .Lfunc_end2
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.Lcst_end1:
.p2align 2, 0x0
# -- End function
.section .text._ZNSt6vectorIPfSaIS0_EEC2ESt16initializer_listIS0_ERKS1_,"axG",@progbits,_ZNSt6vectorIPfSaIS0_EEC2ESt16initializer_listIS0_ERKS1_,comdat
.weak _ZNSt6vectorIPfSaIS0_EEC2ESt16initializer_listIS0_ERKS1_ # -- Begin function _ZNSt6vectorIPfSaIS0_EEC2ESt16initializer_listIS0_ERKS1_
.p2align 1, 0x90
.type _ZNSt6vectorIPfSaIS0_EEC2ESt16initializer_listIS0_ERKS1_,@function
_ZNSt6vectorIPfSaIS0_EEC2ESt16initializer_listIS0_ERKS1_: # @_ZNSt6vectorIPfSaIS0_EEC2ESt16initializer_listIS0_ERKS1_
.Lfunc_begin2:
.cfi_startproc
.cfi_personality 3, __gxx_personality_v0
.cfi_lsda 3, .Lexception2
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
pushq %rax
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movq %rdi, %rbx
xorps %xmm0, %xmm0
movups %xmm0, (%rdi)
movq $0, 16(%rdi)
leaq (%rsi,%rdx,8), %rdx
.Ltmp14:
callq _ZNSt6vectorIPfSaIS0_EE19_M_range_initializeIPKS0_EEvT_S6_St20forward_iterator_tag
.Ltmp15:
# %bb.1:
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.LBB3_2:
.cfi_def_cfa_offset 32
.Ltmp16:
movq %rax, %r14
movq (%rbx), %rdi
testq %rdi, %rdi
je .LBB3_4
# %bb.3:
callq _ZdlPv
.LBB3_4: # %_ZNSt12_Vector_baseIPfSaIS0_EED2Ev.exit
movq %r14, %rdi
callq _Unwind_Resume@PLT
.Lfunc_end3:
.size _ZNSt6vectorIPfSaIS0_EEC2ESt16initializer_listIS0_ERKS1_, .Lfunc_end3-_ZNSt6vectorIPfSaIS0_EEC2ESt16initializer_listIS0_ERKS1_
.cfi_endproc
.section .gcc_except_table._ZNSt6vectorIPfSaIS0_EEC2ESt16initializer_listIS0_ERKS1_,"aG",@progbits,_ZNSt6vectorIPfSaIS0_EEC2ESt16initializer_listIS0_ERKS1_,comdat
.p2align 2, 0x0
GCC_except_table3:
.Lexception2:
.byte 255 # @LPStart Encoding = omit
.byte 255 # @TType Encoding = omit
.byte 1 # Call site Encoding = uleb128
.uleb128 .Lcst_end2-.Lcst_begin2
.Lcst_begin2:
.uleb128 .Ltmp14-.Lfunc_begin2 # >> Call Site 1 <<
.uleb128 .Ltmp15-.Ltmp14 # Call between .Ltmp14 and .Ltmp15
.uleb128 .Ltmp16-.Lfunc_begin2 # jumps to .Ltmp16
.byte 0 # On action: cleanup
.uleb128 .Ltmp15-.Lfunc_begin2 # >> Call Site 2 <<
.uleb128 .Lfunc_end3-.Ltmp15 # Call between .Ltmp15 and .Lfunc_end3
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.Lcst_end2:
.p2align 2, 0x0
# -- End function
.section .text._ZN3ops2OpD2Ev,"axG",@progbits,_ZN3ops2OpD2Ev,comdat
.weak _ZN3ops2OpD2Ev # -- Begin function _ZN3ops2OpD2Ev
.p2align 1, 0x90
.type _ZN3ops2OpD2Ev,@function
_ZN3ops2OpD2Ev: # @_ZN3ops2OpD2Ev
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
movq %rdi, %rbx
movq $_ZTVN3ops2OpE+16, (%rdi)
movq 88(%rdi), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
callq _ZdlPv
.LBB4_2: # %_ZNSt6vectorIPN3ops2OpESaIS2_EED2Ev.exit
movq 64(%rbx), %rdi
testq %rdi, %rdi
je .LBB4_4
# %bb.3:
callq _ZdlPv
.LBB4_4: # %_ZNSt6vectorIPN3ops2OpESaIS2_EED2Ev.exit2
movq 40(%rbx), %rdi
testq %rdi, %rdi
je .LBB4_6
# %bb.5:
callq _ZdlPv
.LBB4_6: # %_ZN3ops5ShapeD2Ev.exit
movq 8(%rbx), %rdi
addq $24, %rbx
cmpq %rbx, %rdi
je .LBB4_7
# %bb.8: # %_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE11_M_is_localEv.exit.i.i
popq %rbx
.cfi_def_cfa_offset 8
jmp _ZdlPv # TAILCALL
.LBB4_7: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev.exit
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end4:
.size _ZN3ops2OpD2Ev, .Lfunc_end4-_ZN3ops2OpD2Ev
.cfi_endproc
# -- End function
.section .text._ZN3ops5InputD0Ev,"axG",@progbits,_ZN3ops5InputD0Ev,comdat
.weak _ZN3ops5InputD0Ev # -- Begin function _ZN3ops5InputD0Ev
.p2align 1, 0x90
.type _ZN3ops5InputD0Ev,@function
_ZN3ops5InputD0Ev: # @_ZN3ops5InputD0Ev
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
movq %rdi, %rbx
callq _ZN3ops2OpD2Ev
movq %rbx, %rdi
popq %rbx
.cfi_def_cfa_offset 8
jmp _ZdlPv # TAILCALL
.Lfunc_end5:
.size _ZN3ops5InputD0Ev, .Lfunc_end5-_ZN3ops5InputD0Ev
.cfi_endproc
# -- End function
.section .text._ZNSt6vectorIiSaIiEEC2ERKS1_,"axG",@progbits,_ZNSt6vectorIiSaIiEEC2ERKS1_,comdat
.weak _ZNSt6vectorIiSaIiEEC2ERKS1_ # -- Begin function _ZNSt6vectorIiSaIiEEC2ERKS1_
.p2align 1, 0x90
.type _ZNSt6vectorIiSaIiEEC2ERKS1_,@function
_ZNSt6vectorIiSaIiEEC2ERKS1_: # @_ZNSt6vectorIiSaIiEEC2ERKS1_
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
pushq %rax
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rsi, %r14
movq %rdi, %rbx
movq 8(%rsi), %rax
movq (%rsi), %rcx
movq %rax, %r12
subq %rcx, %r12
sarq $2, %r12
xorps %xmm0, %xmm0
movups %xmm0, (%rdi)
movq $0, 16(%rdi)
cmpq %rcx, %rax
je .LBB6_1
# %bb.2:
movq %rbx, %rdi
movq %r12, %rsi
xorl %edx, %edx
callq _ZNSt15__new_allocatorIiE8allocateEmPKv
movq %rax, %r15
jmp .LBB6_3
.LBB6_1:
xorl %r15d, %r15d
.LBB6_3:
movq %r15, (%rbx)
movq %r15, 8(%rbx)
leaq (%r15,%r12,4), %rax
movq %rax, 16(%rbx)
movq (%r14), %rsi
movq 8(%r14), %r14
subq %rsi, %r14
cmpq $5, %r14
jl .LBB6_5
# %bb.4:
movq %r15, %rdi
movq %r14, %rdx
callq memmove@PLT
.LBB6_7:
addq %r14, %r15
movq %r15, 8(%rbx)
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB6_5:
.cfi_def_cfa_offset 48
cmpq $4, %r14
jne .LBB6_7
# %bb.6:
movl (%rsi), %eax
movl %eax, (%r15)
jmp .LBB6_7
.Lfunc_end6:
.size _ZNSt6vectorIiSaIiEEC2ERKS1_, .Lfunc_end6-_ZNSt6vectorIiSaIiEEC2ERKS1_
.cfi_endproc
# -- End function
.section .text._ZNSt15__new_allocatorIiE8allocateEmPKv,"axG",@progbits,_ZNSt15__new_allocatorIiE8allocateEmPKv,comdat
.weak _ZNSt15__new_allocatorIiE8allocateEmPKv # -- Begin function _ZNSt15__new_allocatorIiE8allocateEmPKv
.p2align 1, 0x90
.type _ZNSt15__new_allocatorIiE8allocateEmPKv,@function
_ZNSt15__new_allocatorIiE8allocateEmPKv: # @_ZNSt15__new_allocatorIiE8allocateEmPKv
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
movq %rsi, %rax
shrq $61, %rax
jne .LBB7_1
# %bb.3:
shlq $2, %rsi
movq %rsi, %rdi
popq %rax
.cfi_def_cfa_offset 8
jmp _Znwm # TAILCALL
.LBB7_1:
.cfi_def_cfa_offset 16
shrq $62, %rsi
je .LBB7_2
# %bb.4:
callq _ZSt28__throw_bad_array_new_lengthv
.LBB7_2:
callq _ZSt17__throw_bad_allocv
.Lfunc_end7:
.size _ZNSt15__new_allocatorIiE8allocateEmPKv, .Lfunc_end7-_ZNSt15__new_allocatorIiE8allocateEmPKv
.cfi_endproc
# -- End function
.section .text._ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_M_constructIPKcEEvT_S8_St20forward_iterator_tag,"axG",@progbits,_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_M_constructIPKcEEvT_S8_St20forward_iterator_tag,comdat
.weak _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_M_constructIPKcEEvT_S8_St20forward_iterator_tag # -- Begin function _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_M_constructIPKcEEvT_S8_St20forward_iterator_tag
.p2align 1, 0x90
.type _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_M_constructIPKcEEvT_S8_St20forward_iterator_tag,@function
_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_M_constructIPKcEEvT_S8_St20forward_iterator_tag: # @_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_M_constructIPKcEEvT_S8_St20forward_iterator_tag
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
pushq %rax
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rdx, %r14
movq %rsi, %r15
movq %rdi, %rbx
subq %rsi, %r14
movq %r14, (%rsp)
cmpq $15, %r14
jbe .LBB8_1
# %bb.2:
movq %rsp, %r12
movq %rbx, %rdi
movq %r12, %rsi
xorl %edx, %edx
callq _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_createERmm
movq %rax, (%rbx)
movq (%r12), %rcx
movq %rcx, 16(%rbx)
jmp .LBB8_3
.LBB8_1: # %._crit_edge
movq (%rbx), %rax
.LBB8_3:
testq %r14, %r14
je .LBB8_7
# %bb.4:
cmpq $1, %r14
jne .LBB8_6
# %bb.5:
movb (%r15), %cl
movb %cl, (%rax)
jmp .LBB8_7
.LBB8_6:
movq %rax, %rdi
movq %r15, %rsi
movq %r14, %rdx
callq memcpy@PLT
.LBB8_7: # %_ZZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_M_constructIPKcEEvT_S8_St20forward_iterator_tagEN6_GuardD2Ev.exit
movq (%rsp), %rax
movq %rax, 8(%rbx)
movq (%rbx), %rcx
movb $0, (%rcx,%rax)
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end8:
.size _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_M_constructIPKcEEvT_S8_St20forward_iterator_tag, .Lfunc_end8-_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_M_constructIPKcEEvT_S8_St20forward_iterator_tag
.cfi_endproc
# -- End function
.section .text._ZNSt6vectorIPfSaIS0_EE19_M_range_initializeIPKS0_EEvT_S6_St20forward_iterator_tag,"axG",@progbits,_ZNSt6vectorIPfSaIS0_EE19_M_range_initializeIPKS0_EEvT_S6_St20forward_iterator_tag,comdat
.weak _ZNSt6vectorIPfSaIS0_EE19_M_range_initializeIPKS0_EEvT_S6_St20forward_iterator_tag # -- Begin function _ZNSt6vectorIPfSaIS0_EE19_M_range_initializeIPKS0_EEvT_S6_St20forward_iterator_tag
.p2align 1, 0x90
.type _ZNSt6vectorIPfSaIS0_EE19_M_range_initializeIPKS0_EEvT_S6_St20forward_iterator_tag,@function
_ZNSt6vectorIPfSaIS0_EE19_M_range_initializeIPKS0_EEvT_S6_St20forward_iterator_tag: # @_ZNSt6vectorIPfSaIS0_EE19_M_range_initializeIPKS0_EEvT_S6_St20forward_iterator_tag
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rdx, %r14
subq %rsi, %r14
movq %r14, %r13
sarq $3, %r13
movq %r13, %rax
shrq $60, %rax
jne .LBB9_9
# %bb.1: # %_ZNSt6vectorIPfSaIS0_EE17_S_check_init_lenEmRKS1_.exit
movq %rsi, %r15
movq %rdi, %rbx
cmpq %rsi, %rdx
je .LBB9_2
# %bb.3:
movq %rbx, %rdi
movq %r13, %rsi
xorl %edx, %edx
callq _ZNSt15__new_allocatorIPfE8allocateEmPKv
movq %rax, %r12
jmp .LBB9_4
.LBB9_2:
xorl %r12d, %r12d
.LBB9_4: # %_ZNSt12_Vector_baseIPfSaIS0_EE11_M_allocateEm.exit
movq %r12, (%rbx)
leaq (%r12,%r13,8), %rax
movq %rax, 16(%rbx)
cmpq $9, %r14
jl .LBB9_6
# %bb.5:
movq %r12, %rdi
movq %r15, %rsi
movq %r14, %rdx
callq memmove@PLT
.LBB9_8: # %_ZSt22__uninitialized_copy_aIPKPfPS0_S0_ET0_T_S5_S4_RSaIT1_E.exit
addq %r14, %r12
movq %r12, 8(%rbx)
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB9_6:
.cfi_def_cfa_offset 48
cmpq $8, %r14
jne .LBB9_8
# %bb.7:
movq (%r15), %rax
movq %rax, (%r12)
jmp .LBB9_8
.LBB9_9:
movl $.L.str.2, %edi
callq _ZSt20__throw_length_errorPKc
.Lfunc_end9:
.size _ZNSt6vectorIPfSaIS0_EE19_M_range_initializeIPKS0_EEvT_S6_St20forward_iterator_tag, .Lfunc_end9-_ZNSt6vectorIPfSaIS0_EE19_M_range_initializeIPKS0_EEvT_S6_St20forward_iterator_tag
.cfi_endproc
# -- End function
.section .text._ZNSt15__new_allocatorIPfE8allocateEmPKv,"axG",@progbits,_ZNSt15__new_allocatorIPfE8allocateEmPKv,comdat
.weak _ZNSt15__new_allocatorIPfE8allocateEmPKv # -- Begin function _ZNSt15__new_allocatorIPfE8allocateEmPKv
.p2align 1, 0x90
.type _ZNSt15__new_allocatorIPfE8allocateEmPKv,@function
_ZNSt15__new_allocatorIPfE8allocateEmPKv: # @_ZNSt15__new_allocatorIPfE8allocateEmPKv
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
movq %rsi, %rax
shrq $60, %rax
jne .LBB10_1
# %bb.3:
shlq $3, %rsi
movq %rsi, %rdi
popq %rax
.cfi_def_cfa_offset 8
jmp _Znwm # TAILCALL
.LBB10_1:
.cfi_def_cfa_offset 16
shrq $61, %rsi
je .LBB10_2
# %bb.4:
callq _ZSt28__throw_bad_array_new_lengthv
.LBB10_2:
callq _ZSt17__throw_bad_allocv
.Lfunc_end10:
.size _ZNSt15__new_allocatorIPfE8allocateEmPKv, .Lfunc_end10-_ZNSt15__new_allocatorIPfE8allocateEmPKv
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "input"
.size .L.str, 6
.type _ZTVN3ops5InputE,@object # @_ZTVN3ops5InputE
.section .rodata,"a",@progbits
.globl _ZTVN3ops5InputE
.p2align 3, 0x0
_ZTVN3ops5InputE:
.quad 0
.quad _ZTIN3ops5InputE
.quad _ZN3ops2OpD2Ev
.quad _ZN3ops5InputD0Ev
.quad _ZN3ops5Input7compileEv
.quad _ZN3ops2Op10child_gradEmPS0_
.size _ZTVN3ops5InputE, 48
.type _ZTSN3ops5InputE,@object # @_ZTSN3ops5InputE
.globl _ZTSN3ops5InputE
_ZTSN3ops5InputE:
.asciz "N3ops5InputE"
.size _ZTSN3ops5InputE, 13
.type _ZTIN3ops5InputE,@object # @_ZTIN3ops5InputE
.globl _ZTIN3ops5InputE
.p2align 3, 0x0
_ZTIN3ops5InputE:
.quad _ZTVN10__cxxabiv120__si_class_type_infoE+16
.quad _ZTSN3ops5InputE
.quad _ZTIN3ops2OpE
.size _ZTIN3ops5InputE, 24
.type _ZZN3ops12_GLOBAL__N_19unique_idEvE3res,@object # @_ZZN3ops12_GLOBAL__N_19unique_idEvE3res
.local _ZZN3ops12_GLOBAL__N_19unique_idEvE3res
.comm _ZZN3ops12_GLOBAL__N_19unique_idEvE3res,8,8
.type .L.str.2,@object # @.str.2
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.2:
.asciz "cannot create std::vector larger than max_size()"
.size .L.str.2, 49
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.globl _ZN3ops5InputC1ERKNS_5ShapeE
.type _ZN3ops5InputC1ERKNS_5ShapeE,@function
.set _ZN3ops5InputC1ERKNS_5ShapeE, _ZN3ops5InputC2ERKNS_5ShapeE
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __gxx_personality_v0
.addrsig_sym _Unwind_Resume
.addrsig_sym _ZTVN10__cxxabiv120__si_class_type_infoE
.addrsig_sym _ZTSN3ops5InputE
.addrsig_sym _ZTIN3ops2OpE
.addrsig_sym _ZTIN3ops5InputE
.addrsig_sym __hip_cuid_
```
| 7,667 | 11,696 |
194 |
Convert the following CUDA device assembly code to AMD device assembly:
```cudaasm
code for sm_80
Function : _Z5EuleridPdS_S_S_S_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
MOV R1, c[0x0][0x28] ;
S2R R3, SR_TID.X ;
HFMA2.MMA R0, -RZ, RZ, 0, 4.76837158203125e-07 ;
ULDC.64 UR4, c[0x0][0x118] ;
S2R R2, SR_CTAID.X ;
IMAD R3, R2, c[0x0][0x0], R3 ;
IMAD.WIDE R4, R3, R0, c[0x0][0x170] ;
LDG.E.64 R6, [R4.64] ;
LDG.E.64 R8, [R4.64+0x80000] ;
MOV R2, c[0x0][0x160] ;
IMAD.WIDE R10, R3, R0, c[0x0][0x178] ;
SHF.L.U32 R2, R2, 0x10, RZ ;
DFMA R6, R8, c[0x0][0x168], R6 ;
IMAD.WIDE R8, R2, 0x8, R4 ;
STG.E.64 [R8.64], R6 ;
LDG.E.64 R12, [R10.64] ;
LDG.E.64 R14, [R10.64+0x80000] ;
IMAD.WIDE R4, R3, R0, c[0x0][0x180] ;
DFMA R12, R14, c[0x0][0x168], R12 ;
IMAD.WIDE R14, R2, 0x8, R10 ;
STG.E.64 [R14.64], R12 ;
LDG.E.64 R16, [R4.64] ;
LDG.E.64 R18, [R4.64+0x80000] ;
IMAD.WIDE R6, R3, R0, c[0x0][0x188] ;
DFMA R16, R18, c[0x0][0x168], R16 ;
IMAD.WIDE R18, R2, 0x8, R4 ;
STG.E.64 [R18.64], R16 ;
LDG.E.64 R8, [R6.64] ;
LDG.E.64 R10, [R6.64+0x80000] ;
IMAD.WIDE R12, R3, R0, c[0x0][0x190] ;
DFMA R8, R10, c[0x0][0x168], R8 ;
IMAD.WIDE R10, R2, 0x8, R6 ;
STG.E.64 [R10.64], R8 ;
LDG.E.64 R4, [R12.64] ;
LDG.E.64 R14, [R12.64+0x80000] ;
IMAD.WIDE R2, R2, 0x8, R12 ;
DFMA R4, R14, c[0x0][0x168], R4 ;
STG.E.64 [R2.64], R4 ;
EXIT ;
BRA 0x270;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
Function : _Z16ZeitDiffMitEuleriiiPdS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_P10SingleCellid
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
MOV R1, c[0x0][0x28] ;
S2R R7, SR_TID.X ;
HFMA2.MMA R0, -RZ, RZ, 0, 4.76837158203125e-07 ;
ULDC.64 UR4, c[0x0][0x118] ;
S2R R2, SR_CTAID.X ;
IADD3 R6, RZ, -c[0x0][0x168], RZ ;
IMAD R7, R2, c[0x0][0x0], R7 ;
IMAD.WIDE R8, R7.reuse, R0, c[0x0][0x1b8] ;
IADD3 R13, R7, c[0x0][0x160], RZ ;
LDG.E.64 R8, [R8.64] ;
IMAD.WIDE R2, R13, R0, c[0x0][0x178] ;
IMAD.WIDE R4, R13, R0, c[0x0][0x170] ;
LDG.E.64 R2, [R2.64] ;
LEA R11, R6, R13, 0x10 ;
LDG.E.64 R4, [R4.64] ;
IMAD.WIDE R18, R11, R0, c[0x0][0x170] ;
LDG.E.64 R22, [R18.64] ;
MOV R6, 0x10000 ;
IMAD.WIDE R24, R13, R0, c[0x0][0x180] ;
IMAD.WIDE R16, R13, R0, c[0x0][0x190] ;
IMAD.WIDE R18, R7, R0.reuse, c[0x0][0x1d8] ;
LDG.E.64 R16, [R16.64] ;
IMAD.WIDE R20, R11, R0, c[0x0][0x178] ;
DMUL R14, R8, c[0x2][0x10] ;
IMAD R9, R6, c[0x0][0x164], R13 ;
DFMA R14, R2, 588, -R14 ;
DFMA R14, R4, -175, R14 ;
DADD R14, -R4, R14 ;
IMAD.WIDE R28, R9, R0, c[0x0][0x170] ;
DFMA R22, R14, c[0x0][0x218], R22 ;
IMAD.WIDE R14, R13, R0, c[0x0][0x188] ;
LDG.E.64 R12, [R24.64] ;
LDG.E.64 R14, [R14.64] ;
STG.E.64 [R28.64], R22 ;
LDG.E.64 R18, [R18.64] ;
LDG.E.64 R20, [R20.64] ;
DMUL R26, R2, c[0x2][0x8] ;
DFMA R26, R2, R26, 1 ;
DMUL R4, R4, c[0x2][0x0] ;
IMAD.WIDE R22, R7, R0, c[0x0][0x1e0] ;
DMUL R26, R12, R26 ;
DFMA R4, R2, R4, -R26 ;
DFMA R2, -RZ, R2, R18 ;
DFMA R2, R2, c[0x2][0x18], -R4 ;
IMAD.WIDE R18, R9, R0, c[0x0][0x178] ;
DFMA R2, R2, c[0x0][0x218], R20 ;
STG.E.64 [R18.64], R2 ;
LDG.E.64 R22, [R22.64] ;
IMAD.WIDE R20, R11, R0, c[0x0][0x180] ;
LDG.E.64 R20, [R20.64] ;
IMAD.WIDE R24, R7, R0, c[0x0][0x1a8] ;
IMAD.WIDE R2, R11, R0, c[0x0][0x188] ;
DFMA R12, -RZ, R12, R22 ;
DADD R12, R4, R12 ;
IMAD.WIDE R4, R9, R0, c[0x0][0x180] ;
DFMA R12, R12, c[0x0][0x218], R20 ;
STG.E.64 [R4.64], R12 ;
LDG.E.64 R24, [R24.64] ;
LDG.E.64 R2, [R2.64] ;
IMAD.WIDE R6, R7, R0, c[0x0][0x1b0] ;
IMAD.WIDE R4, R11, R0, c[0x0][0x190] ;
DMUL R18, R24, c[0x2][0x10] ;
DFMA R18, R14, 175, R18 ;
DADD R18, -R14, -R18 ;
IMAD.WIDE R14, R9, R0, c[0x0][0x188] ;
DFMA R18, R18, c[0x0][0x218], R2 ;
STG.E.64 [R14.64], R18 ;
LDG.E.64 R6, [R6.64] ;
LDG.E.64 R4, [R4.64] ;
IMAD.WIDE R8, R9, R0, c[0x0][0x190] ;
DMUL R2, R6, c[0x2][0x10] ;
DFMA R2, R16, 175, R2 ;
DADD R2, -R16, -R2 ;
DFMA R2, R2, c[0x0][0x218], R4 ;
STG.E.64 [R8.64], R2 ;
EXIT ;
BRA 0x4c0;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
Function : _Z8ZeitDiffiiPdS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_P10SingleCelli
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
MOV R1, c[0x0][0x28] ;
S2R R5, SR_TID.X ;
HFMA2.MMA R0, -RZ, RZ, 0, 4.76837158203125e-07 ;
ULDC.64 UR4, c[0x0][0x118] ;
S2R R2, SR_CTAID.X ;
IMAD R5, R2, c[0x0][0x0], R5 ;
IMAD.WIDE R12, R5.reuse, R0, c[0x0][0x1b0] ;
IADD3 R15, R5, c[0x0][0x160], RZ ;
LDG.E.64 R12, [R12.64] ;
IMAD.WIDE R2, R15, R0, c[0x0][0x170] ;
IMAD.WIDE R8, R15, R0, c[0x0][0x168] ;
LDG.E.64 R2, [R2.64] ;
LDG.E.64 R8, [R8.64] ;
MOV R4, c[0x0][0x164] ;
LEA R11, R4, R15, 0x10 ;
IMAD.WIDE R22, R5, R0, c[0x0][0x1d0] ;
IMAD.WIDE R20, R11, R0, c[0x0][0x168] ;
DMUL R6, R12, c[0x2][0x10] ;
IMAD.WIDE R12, R15, R0, c[0x0][0x180] ;
DFMA R6, R2, 588, -R6 ;
LDG.E.64 R12, [R12.64] ;
DFMA R16, R8, -175, R6 ;
IMAD.WIDE R6, R15, R0, c[0x0][0x178] ;
IMAD.WIDE R14, R15, R0, c[0x0][0x188] ;
DADD R18, -R8, R16 ;
LDG.E.64 R6, [R6.64] ;
LDG.E.64 R14, [R14.64] ;
STG.E.64 [R20.64], R18 ;
LDG.E.64 R22, [R22.64] ;
DMUL R16, R2, c[0x2][0x8] ;
DFMA R16, R2, R16, 1 ;
DMUL R8, R8, c[0x2][0x0] ;
IMAD.WIDE R24, R5, R0, c[0x0][0x1d8] ;
DMUL R16, R6, R16 ;
DFMA R8, R2, R8, -R16 ;
DFMA R2, -RZ, R2, R22 ;
IMAD.WIDE R16, R11, R0, c[0x0][0x170] ;
DFMA R2, R2, c[0x2][0x18], -R8 ;
STG.E.64 [R16.64], R2 ;
LDG.E.64 R24, [R24.64] ;
IMAD.WIDE R18, R5, R0, c[0x0][0x1a0] ;
DFMA R6, -RZ, R6, R24 ;
DADD R6, R8, R6 ;
IMAD.WIDE R8, R11, R0, c[0x0][0x178] ;
STG.E.64 [R8.64], R6 ;
LDG.E.64 R18, [R18.64] ;
IMAD.WIDE R2, R11, R0, c[0x0][0x180] ;
IMAD.WIDE R4, R5, R0, c[0x0][0x1a8] ;
DMUL R20, R18, c[0x2][0x10] ;
DFMA R20, R12, 175, R20 ;
DADD R20, -R12, -R20 ;
STG.E.64 [R2.64], R20 ;
LDG.E.64 R4, [R4.64] ;
IMAD.WIDE R6, R11, R0, c[0x0][0x188] ;
DMUL R12, R4, c[0x2][0x10] ;
DFMA R12, R14, 175, R12 ;
DADD R12, -R14, -R12 ;
STG.E.64 [R6.64], R12 ;
EXIT ;
BRA 0x3b0;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
```
|
```amdasm
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object ; @__hip_cuid_
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0 ; 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
```
| 3,909 | 306 |
195 |
Convert the following CUDA host assembly code to AMD host assembly:
```cudaasm
.file "tmpxft_000d1bc0_00000000-6_Dynamics.cudafe1.cpp"
.text
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2877:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2877:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z79__device_stub__Z8ZeitDiffiiPdS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_P10SingleCelliiiPdS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_P10SingleCelli
.type _Z79__device_stub__Z8ZeitDiffiiPdS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_P10SingleCelliiiPdS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_P10SingleCelli, @function
_Z79__device_stub__Z8ZeitDiffiiPdS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_P10SingleCelliiiPdS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_P10SingleCelli:
.LFB2899:
.cfi_startproc
endbr64
subq $440, %rsp
.cfi_def_cfa_offset 448
movl %edi, 172(%rsp)
movl %esi, 168(%rsp)
movq %rdx, 160(%rsp)
movq %rcx, 152(%rsp)
movq %r8, 144(%rsp)
movq %r9, 136(%rsp)
movq 448(%rsp), %rax
movq %rax, 128(%rsp)
movq 456(%rsp), %rax
movq %rax, 120(%rsp)
movq 464(%rsp), %rax
movq %rax, 112(%rsp)
movq 472(%rsp), %rax
movq %rax, 104(%rsp)
movq 480(%rsp), %rax
movq %rax, 96(%rsp)
movq 488(%rsp), %rax
movq %rax, 88(%rsp)
movq 496(%rsp), %rax
movq %rax, 80(%rsp)
movq 504(%rsp), %rax
movq %rax, 72(%rsp)
movq 512(%rsp), %rax
movq %rax, 64(%rsp)
movq 520(%rsp), %rax
movq %rax, 56(%rsp)
movq 528(%rsp), %rax
movq %rax, 48(%rsp)
movq 536(%rsp), %rax
movq %rax, 40(%rsp)
movq 544(%rsp), %rax
movq %rax, 32(%rsp)
movq 552(%rsp), %rax
movq %rax, 24(%rsp)
movq 560(%rsp), %rax
movq %rax, 16(%rsp)
movq 568(%rsp), %rax
movq %rax, 8(%rsp)
movq %fs:40, %rax
movq %rax, 424(%rsp)
xorl %eax, %eax
leaq 172(%rsp), %rax
movq %rax, 240(%rsp)
leaq 168(%rsp), %rax
movq %rax, 248(%rsp)
leaq 160(%rsp), %rax
movq %rax, 256(%rsp)
leaq 152(%rsp), %rax
movq %rax, 264(%rsp)
leaq 144(%rsp), %rax
movq %rax, 272(%rsp)
leaq 136(%rsp), %rax
movq %rax, 280(%rsp)
leaq 128(%rsp), %rax
movq %rax, 288(%rsp)
leaq 120(%rsp), %rax
movq %rax, 296(%rsp)
leaq 112(%rsp), %rax
movq %rax, 304(%rsp)
leaq 104(%rsp), %rax
movq %rax, 312(%rsp)
leaq 96(%rsp), %rax
movq %rax, 320(%rsp)
leaq 88(%rsp), %rax
movq %rax, 328(%rsp)
leaq 80(%rsp), %rax
movq %rax, 336(%rsp)
leaq 72(%rsp), %rax
movq %rax, 344(%rsp)
leaq 64(%rsp), %rax
movq %rax, 352(%rsp)
leaq 56(%rsp), %rax
movq %rax, 360(%rsp)
leaq 48(%rsp), %rax
movq %rax, 368(%rsp)
leaq 40(%rsp), %rax
movq %rax, 376(%rsp)
leaq 32(%rsp), %rax
movq %rax, 384(%rsp)
leaq 24(%rsp), %rax
movq %rax, 392(%rsp)
leaq 16(%rsp), %rax
movq %rax, 400(%rsp)
leaq 8(%rsp), %rax
movq %rax, 408(%rsp)
leaq 576(%rsp), %rax
movq %rax, 416(%rsp)
movl $1, 192(%rsp)
movl $1, 196(%rsp)
movl $1, 200(%rsp)
movl $1, 204(%rsp)
movl $1, 208(%rsp)
movl $1, 212(%rsp)
leaq 184(%rsp), %rcx
leaq 176(%rsp), %rdx
leaq 204(%rsp), %rsi
leaq 192(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 424(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $440, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 184(%rsp)
.cfi_def_cfa_offset 456
pushq 184(%rsp)
.cfi_def_cfa_offset 464
leaq 256(%rsp), %r9
movq 220(%rsp), %rcx
movl 228(%rsp), %r8d
movq 208(%rsp), %rsi
movl 216(%rsp), %edx
leaq _Z8ZeitDiffiiPdS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_P10SingleCelli(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 448
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2899:
.size _Z79__device_stub__Z8ZeitDiffiiPdS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_P10SingleCelliiiPdS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_P10SingleCelli, .-_Z79__device_stub__Z8ZeitDiffiiPdS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_P10SingleCelliiiPdS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_P10SingleCelli
.globl _Z8ZeitDiffiiPdS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_P10SingleCelli
.type _Z8ZeitDiffiiPdS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_P10SingleCelli, @function
_Z8ZeitDiffiiPdS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_P10SingleCelli:
.LFB2900:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
movl 152(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
pushq 152(%rsp)
.cfi_def_cfa_offset 40
pushq 152(%rsp)
.cfi_def_cfa_offset 48
pushq 152(%rsp)
.cfi_def_cfa_offset 56
pushq 152(%rsp)
.cfi_def_cfa_offset 64
pushq 152(%rsp)
.cfi_def_cfa_offset 72
pushq 152(%rsp)
.cfi_def_cfa_offset 80
pushq 152(%rsp)
.cfi_def_cfa_offset 88
pushq 152(%rsp)
.cfi_def_cfa_offset 96
pushq 152(%rsp)
.cfi_def_cfa_offset 104
pushq 152(%rsp)
.cfi_def_cfa_offset 112
pushq 152(%rsp)
.cfi_def_cfa_offset 120
pushq 152(%rsp)
.cfi_def_cfa_offset 128
pushq 152(%rsp)
.cfi_def_cfa_offset 136
pushq 152(%rsp)
.cfi_def_cfa_offset 144
pushq 152(%rsp)
.cfi_def_cfa_offset 152
pushq 152(%rsp)
.cfi_def_cfa_offset 160
call _Z79__device_stub__Z8ZeitDiffiiPdS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_P10SingleCelliiiPdS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_P10SingleCelli
addq $152, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2900:
.size _Z8ZeitDiffiiPdS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_P10SingleCelli, .-_Z8ZeitDiffiiPdS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_P10SingleCelli
.globl _Z90__device_stub__Z16ZeitDiffMitEuleriiiPdS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_P10SingleCellidiiiPdS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_P10SingleCellid
.type _Z90__device_stub__Z16ZeitDiffMitEuleriiiPdS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_P10SingleCellidiiiPdS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_P10SingleCellid, @function
_Z90__device_stub__Z16ZeitDiffMitEuleriiiPdS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_P10SingleCellidiiiPdS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_P10SingleCellid:
.LFB2901:
.cfi_startproc
endbr64
subq $472, %rsp
.cfi_def_cfa_offset 480
movl %edi, 188(%rsp)
movl %esi, 184(%rsp)
movl %edx, 180(%rsp)
movq %rcx, 168(%rsp)
movq %r8, 160(%rsp)
movq %r9, 152(%rsp)
movsd %xmm0, 8(%rsp)
movq 480(%rsp), %rax
movq %rax, 144(%rsp)
movq 488(%rsp), %rax
movq %rax, 136(%rsp)
movq 496(%rsp), %rax
movq %rax, 128(%rsp)
movq 504(%rsp), %rax
movq %rax, 120(%rsp)
movq 512(%rsp), %rax
movq %rax, 112(%rsp)
movq 520(%rsp), %rax
movq %rax, 104(%rsp)
movq 528(%rsp), %rax
movq %rax, 96(%rsp)
movq 536(%rsp), %rax
movq %rax, 88(%rsp)
movq 544(%rsp), %rax
movq %rax, 80(%rsp)
movq 552(%rsp), %rax
movq %rax, 72(%rsp)
movq 560(%rsp), %rax
movq %rax, 64(%rsp)
movq 568(%rsp), %rax
movq %rax, 56(%rsp)
movq 576(%rsp), %rax
movq %rax, 48(%rsp)
movq 584(%rsp), %rax
movq %rax, 40(%rsp)
movq 592(%rsp), %rax
movq %rax, 32(%rsp)
movq 600(%rsp), %rax
movq %rax, 24(%rsp)
movq 608(%rsp), %rax
movq %rax, 16(%rsp)
movq %fs:40, %rax
movq %rax, 456(%rsp)
xorl %eax, %eax
leaq 188(%rsp), %rax
movq %rax, 256(%rsp)
leaq 184(%rsp), %rax
movq %rax, 264(%rsp)
leaq 180(%rsp), %rax
movq %rax, 272(%rsp)
leaq 168(%rsp), %rax
movq %rax, 280(%rsp)
leaq 160(%rsp), %rax
movq %rax, 288(%rsp)
leaq 152(%rsp), %rax
movq %rax, 296(%rsp)
leaq 144(%rsp), %rax
movq %rax, 304(%rsp)
leaq 136(%rsp), %rax
movq %rax, 312(%rsp)
leaq 128(%rsp), %rax
movq %rax, 320(%rsp)
leaq 120(%rsp), %rax
movq %rax, 328(%rsp)
leaq 112(%rsp), %rax
movq %rax, 336(%rsp)
leaq 104(%rsp), %rax
movq %rax, 344(%rsp)
leaq 96(%rsp), %rax
movq %rax, 352(%rsp)
leaq 88(%rsp), %rax
movq %rax, 360(%rsp)
leaq 80(%rsp), %rax
movq %rax, 368(%rsp)
leaq 72(%rsp), %rax
movq %rax, 376(%rsp)
leaq 64(%rsp), %rax
movq %rax, 384(%rsp)
leaq 56(%rsp), %rax
movq %rax, 392(%rsp)
leaq 48(%rsp), %rax
movq %rax, 400(%rsp)
leaq 40(%rsp), %rax
movq %rax, 408(%rsp)
leaq 32(%rsp), %rax
movq %rax, 416(%rsp)
leaq 24(%rsp), %rax
movq %rax, 424(%rsp)
leaq 16(%rsp), %rax
movq %rax, 432(%rsp)
leaq 616(%rsp), %rax
movq %rax, 440(%rsp)
leaq 8(%rsp), %rax
movq %rax, 448(%rsp)
movl $1, 208(%rsp)
movl $1, 212(%rsp)
movl $1, 216(%rsp)
movl $1, 220(%rsp)
movl $1, 224(%rsp)
movl $1, 228(%rsp)
leaq 200(%rsp), %rcx
leaq 192(%rsp), %rdx
leaq 220(%rsp), %rsi
leaq 208(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 456(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $472, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 200(%rsp)
.cfi_def_cfa_offset 488
pushq 200(%rsp)
.cfi_def_cfa_offset 496
leaq 272(%rsp), %r9
movq 236(%rsp), %rcx
movl 244(%rsp), %r8d
movq 224(%rsp), %rsi
movl 232(%rsp), %edx
leaq _Z16ZeitDiffMitEuleriiiPdS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_P10SingleCellid(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 480
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2901:
.size _Z90__device_stub__Z16ZeitDiffMitEuleriiiPdS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_P10SingleCellidiiiPdS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_P10SingleCellid, .-_Z90__device_stub__Z16ZeitDiffMitEuleriiiPdS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_P10SingleCellidiiiPdS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_P10SingleCellid
.globl _Z16ZeitDiffMitEuleriiiPdS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_P10SingleCellid
.type _Z16ZeitDiffMitEuleriiiPdS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_P10SingleCellid, @function
_Z16ZeitDiffMitEuleriiiPdS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_P10SingleCellid:
.LFB2902:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl 152(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 24
pushq 152(%rsp)
.cfi_def_cfa_offset 32
pushq 152(%rsp)
.cfi_def_cfa_offset 40
pushq 152(%rsp)
.cfi_def_cfa_offset 48
pushq 152(%rsp)
.cfi_def_cfa_offset 56
pushq 152(%rsp)
.cfi_def_cfa_offset 64
pushq 152(%rsp)
.cfi_def_cfa_offset 72
pushq 152(%rsp)
.cfi_def_cfa_offset 80
pushq 152(%rsp)
.cfi_def_cfa_offset 88
pushq 152(%rsp)
.cfi_def_cfa_offset 96
pushq 152(%rsp)
.cfi_def_cfa_offset 104
pushq 152(%rsp)
.cfi_def_cfa_offset 112
pushq 152(%rsp)
.cfi_def_cfa_offset 120
pushq 152(%rsp)
.cfi_def_cfa_offset 128
pushq 152(%rsp)
.cfi_def_cfa_offset 136
pushq 152(%rsp)
.cfi_def_cfa_offset 144
pushq 152(%rsp)
.cfi_def_cfa_offset 152
pushq 152(%rsp)
.cfi_def_cfa_offset 160
call _Z90__device_stub__Z16ZeitDiffMitEuleriiiPdS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_P10SingleCellidiiiPdS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_P10SingleCellid
addq $152, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2902:
.size _Z16ZeitDiffMitEuleriiiPdS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_P10SingleCellid, .-_Z16ZeitDiffMitEuleriiiPdS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_P10SingleCellid
.globl _Z36__device_stub__Z5EuleridPdS_S_S_S_S_idPdS_S_S_S_S_
.type _Z36__device_stub__Z5EuleridPdS_S_S_S_S_idPdS_S_S_S_S_, @function
_Z36__device_stub__Z5EuleridPdS_S_S_S_S_idPdS_S_S_S_S_:
.LFB2903:
.cfi_startproc
endbr64
subq $216, %rsp
.cfi_def_cfa_offset 224
movl %edi, 60(%rsp)
movsd %xmm0, 48(%rsp)
movq %rsi, 40(%rsp)
movq %rdx, 32(%rsp)
movq %rcx, 24(%rsp)
movq %r8, 16(%rsp)
movq %r9, 8(%rsp)
movq 224(%rsp), %rax
movq %rax, (%rsp)
movq %fs:40, %rax
movq %rax, 200(%rsp)
xorl %eax, %eax
leaq 60(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 40(%rsp), %rax
movq %rax, 144(%rsp)
leaq 32(%rsp), %rax
movq %rax, 152(%rsp)
leaq 24(%rsp), %rax
movq %rax, 160(%rsp)
leaq 16(%rsp), %rax
movq %rax, 168(%rsp)
leaq 8(%rsp), %rax
movq %rax, 176(%rsp)
movq %rsp, %rax
movq %rax, 184(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
leaq 72(%rsp), %rcx
leaq 64(%rsp), %rdx
leaq 92(%rsp), %rsi
leaq 80(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L23
.L19:
movq 200(%rsp), %rax
subq %fs:40, %rax
jne .L24
addq $216, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
pushq 72(%rsp)
.cfi_def_cfa_offset 232
pushq 72(%rsp)
.cfi_def_cfa_offset 240
leaq 144(%rsp), %r9
movq 108(%rsp), %rcx
movl 116(%rsp), %r8d
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
leaq _Z5EuleridPdS_S_S_S_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 224
jmp .L19
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2903:
.size _Z36__device_stub__Z5EuleridPdS_S_S_S_S_idPdS_S_S_S_S_, .-_Z36__device_stub__Z5EuleridPdS_S_S_S_S_idPdS_S_S_S_S_
.globl _Z5EuleridPdS_S_S_S_S_
.type _Z5EuleridPdS_S_S_S_S_, @function
_Z5EuleridPdS_S_S_S_S_:
.LFB2904:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
pushq 24(%rsp)
.cfi_def_cfa_offset 32
call _Z36__device_stub__Z5EuleridPdS_S_S_S_S_idPdS_S_S_S_S_
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2904:
.size _Z5EuleridPdS_S_S_S_S_, .-_Z5EuleridPdS_S_S_S_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z5EuleridPdS_S_S_S_S_"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "_Z16ZeitDiffMitEuleriiiPdS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_P10SingleCellid"
.align 8
.LC2:
.string "_Z8ZeitDiffiiPdS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_P10SingleCelli"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2906:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z5EuleridPdS_S_S_S_S_(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z16ZeitDiffMitEuleriiiPdS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_P10SingleCellid(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z8ZeitDiffiiPdS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_P10SingleCelli(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2906:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
```
|
```amdasm
.text
.file "Dynamics.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
```
| 8,053 | 183 |
196 |
Convert the following CUDA device assembly code to AMD device assembly:
```cudaasm
code for sm_80
Function : _Z12change_thetaiPK6float3P6float4S3_S3_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
MOV R1, c[0x0][0x28] ;
S2R R0, SR_CTAID.X ;
S2R R3, SR_TID.X ;
IMAD R0, R0, c[0x0][0x0], R3 ;
ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x160], PT ;
@P0 EXIT ;
HFMA2.MMA R3, -RZ, RZ, 0, 7.152557373046875e-07 ;
SHF.L.U32 R2, R0, 0x2, RZ ;
ULDC.64 UR4, c[0x0][0x118] ;
IMAD.WIDE.U32 R2, R2, R3, c[0x0][0x168] ;
LDG.E R9, [R2.64] ;
HFMA2.MMA R21, -RZ, RZ, 0, 9.5367431640625e-07 ;
IMAD.WIDE.U32 R4, R0, R21, c[0x0][0x170] ;
STG.E [R4.64], R9 ;
LDG.E R11, [R2.64+0xc] ;
STG.E [R4.64+0x4], R11 ;
LDG.E R13, [R2.64+0x18] ;
STG.E [R4.64+0x8], R13 ;
LDG.E R15, [R2.64+0x24] ;
IMAD.WIDE.U32 R6, R0, R21, c[0x0][0x178] ;
STG.E [R4.64+0xc], R15 ;
LDG.E R17, [R2.64+0x4] ;
STG.E [R6.64], R17 ;
LDG.E R19, [R2.64+0x10] ;
STG.E [R6.64+0x4], R19 ;
LDG.E R9, [R2.64+0x1c] ;
STG.E [R6.64+0x8], R9 ;
LDG.E R11, [R2.64+0x28] ;
IMAD.WIDE.U32 R4, R0, R21, c[0x0][0x180] ;
STG.E [R6.64+0xc], R11 ;
LDG.E R13, [R2.64+0x8] ;
STG.E [R4.64], R13 ;
LDG.E R15, [R2.64+0x14] ;
STG.E [R4.64+0x4], R15 ;
LDG.E R17, [R2.64+0x20] ;
STG.E [R4.64+0x8], R17 ;
LDG.E R19, [R2.64+0x2c] ;
STG.E [R4.64+0xc], R19 ;
EXIT ;
BRA 0x270;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
```
|
```amdasm
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z12change_thetaiPK15HIP_vector_typeIfLj3EEPS_IfLj4EES4_S4_ ; -- Begin function _Z12change_thetaiPK15HIP_vector_typeIfLj3EEPS_IfLj4EES4_S4_
.globl _Z12change_thetaiPK15HIP_vector_typeIfLj3EEPS_IfLj4EES4_S4_
.p2align 8
.type _Z12change_thetaiPK15HIP_vector_typeIfLj3EEPS_IfLj4EES4_S4_,@function
_Z12change_thetaiPK15HIP_vector_typeIfLj3EEPS_IfLj4EES4_S4_: ; @_Z12change_thetaiPK15HIP_vector_typeIfLj3EEPS_IfLj4EES4_S4_
; %bb.0:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x34
s_load_b32 s3, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_u32_e64 s3, v1
s_cbranch_execz .LBB0_2
; %bb.1:
s_load_b256 s[0:7], s[0:1], 0x8
v_lshlrev_b32_e32 v0, 2, v1
v_mov_b32_e32 v2, 0
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[3:4], null, v0, 12, s[0:1]
v_lshlrev_b64 v[0:1], 4, v[1:2]
s_delay_alu instid0(VALU_DEP_1)
v_add_co_u32 v5, vcc_lo, s2, v0
global_load_b32 v7, v[3:4], off
v_add_co_ci_u32_e32 v6, vcc_lo, s3, v1, vcc_lo
s_waitcnt vmcnt(0)
global_store_b32 v[5:6], v7, off
global_load_b32 v2, v[3:4], off offset:12
s_waitcnt vmcnt(0)
global_store_b32 v[5:6], v2, off offset:4
global_load_b32 v2, v[3:4], off offset:24
s_waitcnt vmcnt(0)
global_store_b32 v[5:6], v2, off offset:8
global_load_b32 v2, v[3:4], off offset:36
s_waitcnt vmcnt(0)
global_store_b32 v[5:6], v2, off offset:12
global_load_b32 v2, v[3:4], off offset:4
v_add_co_u32 v5, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v6, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
s_waitcnt vmcnt(0)
global_store_b32 v[5:6], v2, off
global_load_b32 v2, v[3:4], off offset:16
s_waitcnt vmcnt(0)
global_store_b32 v[5:6], v2, off offset:4
global_load_b32 v2, v[3:4], off offset:28
s_waitcnt vmcnt(0)
global_store_b32 v[5:6], v2, off offset:8
global_load_b32 v2, v[3:4], off offset:40
s_waitcnt vmcnt(0)
global_store_b32 v[5:6], v2, off offset:12
global_load_b32 v2, v[3:4], off offset:8
s_waitcnt vmcnt(0)
global_store_b32 v[0:1], v2, off
global_load_b32 v2, v[3:4], off offset:20
s_waitcnt vmcnt(0)
global_store_b32 v[0:1], v2, off offset:4
global_load_b32 v2, v[3:4], off offset:32
s_waitcnt vmcnt(0)
global_store_b32 v[0:1], v2, off offset:8
global_load_b32 v2, v[3:4], off offset:44
s_waitcnt vmcnt(0)
global_store_b32 v[0:1], v2, off offset:12
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z12change_thetaiPK15HIP_vector_typeIfLj3EEPS_IfLj4EES4_S4_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z12change_thetaiPK15HIP_vector_typeIfLj3EEPS_IfLj4EES4_S4_, .Lfunc_end0-_Z12change_thetaiPK15HIP_vector_typeIfLj3EEPS_IfLj4EES4_S4_
; -- End function
.section .AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 392
; NumSgprs: 18
; NumVgprs: 8
; ScratchSize: 0
; MemoryBound: 1
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 8
; Occupancy: 16
; WaveLimiterHint : 1
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object ; @__hip_cuid_
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0 ; 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z12change_thetaiPK15HIP_vector_typeIfLj3EEPS_IfLj4EES4_S4_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z12change_thetaiPK15HIP_vector_typeIfLj3EEPS_IfLj4EES4_S4_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
```
| 872 | 3,321 |
197 |
Convert the following CUDA host assembly code to AMD host assembly:
```cudaasm
.file "tmpxft_0003f770_00000000-6_change_theta.cudafe1.cpp"
.text
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z54__device_stub__Z12change_thetaiPK6float3P6float4S3_S3_iPK6float3P6float4S3_S3_
.type _Z54__device_stub__Z12change_thetaiPK6float3P6float4S3_S3_iPK6float3P6float4S3_S3_, @function
_Z54__device_stub__Z12change_thetaiPK6float3P6float4S3_S3_iPK6float3P6float4S3_S3_:
.LFB2051:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movl %edi, 44(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movq %r8, 8(%rsp)
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 44(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 184
pushq 56(%rsp)
.cfi_def_cfa_offset 192
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z12change_thetaiPK6float3P6float4S3_S3_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z54__device_stub__Z12change_thetaiPK6float3P6float4S3_S3_iPK6float3P6float4S3_S3_, .-_Z54__device_stub__Z12change_thetaiPK6float3P6float4S3_S3_iPK6float3P6float4S3_S3_
.globl _Z12change_thetaiPK6float3P6float4S3_S3_
.type _Z12change_thetaiPK6float3P6float4S3_S3_, @function
_Z12change_thetaiPK6float3P6float4S3_S3_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z54__device_stub__Z12change_thetaiPK6float3P6float4S3_S3_iPK6float3P6float4S3_S3_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z12change_thetaiPK6float3P6float4S3_S3_, .-_Z12change_thetaiPK6float3P6float4S3_S3_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z12change_thetaiPK6float3P6float4S3_S3_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z12change_thetaiPK6float3P6float4S3_S3_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
```
|
```amdasm
.text
.file "change_theta.hip"
.globl _Z27__device_stub__change_thetaiPK15HIP_vector_typeIfLj3EEPS_IfLj4EES4_S4_ # -- Begin function _Z27__device_stub__change_thetaiPK15HIP_vector_typeIfLj3EEPS_IfLj4EES4_S4_
.type _Z27__device_stub__change_thetaiPK15HIP_vector_typeIfLj3EEPS_IfLj4EES4_S4_,@function
_Z27__device_stub__change_thetaiPK15HIP_vector_typeIfLj3EEPS_IfLj4EES4_S4_: # @_Z27__device_stub__change_thetaiPK15HIP_vector_typeIfLj3EEPS_IfLj4EES4_S4_
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $144, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 12(%rsp), %rax
movl %edi, (%rax)
leaq 56(%rsp), %rdi
movq %rsi, (%rdi)
leaq 48(%rsp), %rsi
movq %rdx, (%rsi)
leaq 40(%rsp), %rdx
movq %rcx, (%rdx)
leaq 32(%rsp), %rcx
movq %r8, (%rcx)
leaq 96(%rsp), %rbx
movq %rax, (%rbx)
movq %rdi, 8(%rbx)
movq %rsi, 16(%rbx)
movq %rdx, 24(%rbx)
movq %rcx, 32(%rbx)
leaq 80(%rsp), %r14
leaq 64(%rsp), %r15
leaq 24(%rsp), %r12
leaq 16(%rsp), %r13
movq %r14, %rdi
movq %r15, %rsi
movq %r12, %rdx
movq %r13, %rcx
callq __hipPopCallConfiguration
movq (%r14), %rsi
movl 8(%r14), %edx
movq (%r15), %rcx
movl 8(%r15), %r8d
movl $_Z12change_thetaiPK15HIP_vector_typeIfLj3EEPS_IfLj4EES4_S4_, %edi
movq %rbx, %r9
pushq (%r13)
.cfi_adjust_cfa_offset 8
pushq (%r12)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $160, %rsp
.cfi_adjust_cfa_offset -160
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z27__device_stub__change_thetaiPK15HIP_vector_typeIfLj3EEPS_IfLj4EES4_S4_, .Lfunc_end0-_Z27__device_stub__change_thetaiPK15HIP_vector_typeIfLj3EEPS_IfLj4EES4_S4_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, %rdi
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12change_thetaiPK15HIP_vector_typeIfLj3EEPS_IfLj4EES4_S4_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z12change_thetaiPK15HIP_vector_typeIfLj3EEPS_IfLj4EES4_S4_,@object # @_Z12change_thetaiPK15HIP_vector_typeIfLj3EEPS_IfLj4EES4_S4_
.section .rodata,"a",@progbits
.globl _Z12change_thetaiPK15HIP_vector_typeIfLj3EEPS_IfLj4EES4_S4_
.p2align 3, 0x0
_Z12change_thetaiPK15HIP_vector_typeIfLj3EEPS_IfLj4EES4_S4_:
.quad _Z27__device_stub__change_thetaiPK15HIP_vector_typeIfLj3EEPS_IfLj4EES4_S4_
.size _Z12change_thetaiPK15HIP_vector_typeIfLj3EEPS_IfLj4EES4_S4_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z12change_thetaiPK15HIP_vector_typeIfLj3EEPS_IfLj4EES4_S4_"
.size .L__unnamed_1, 60
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z27__device_stub__change_thetaiPK15HIP_vector_typeIfLj3EEPS_IfLj4EES4_S4_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z12change_thetaiPK15HIP_vector_typeIfLj3EEPS_IfLj4EES4_S4_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
```
| 2,116 | 2,450 |
202 |
Convert the following CUDA device assembly code to AMD device assembly:
```cudaasm
code for sm_80
Function : vmuldiv_sp
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ;
S2R R0, SR_TID.X ;
IMAD.MOV.U32 R7, RZ, RZ, 0x4 ;
ULDC.64 UR4, c[0x0][0x118] ;
S2R R3, SR_CTAID.X ;
IMAD R0, R3, c[0x0][0x0], R0 ;
IMAD.WIDE R4, R0, R7, c[0x0][0x168] ;
LDG.E R4, [R4.64] ;
IMAD.WIDE R2, R0, R7, c[0x0][0x160] ;
LDG.E R3, [R2.64] ;
BSSY B0, 0x160 ;
MUFU.RCP R7, R4 ;
FCHK P0, R3, R4 ;
FFMA R6, -R4, R7, 1 ;
FFMA R6, R7, R6, R7 ;
FFMA R7, R3, R6, RZ ;
FFMA R8, -R4, R7, R3 ;
FFMA R6, R6, R8, R7 ;
@!P0 BRA 0x150 ;
MOV R2, 0x150 ;
CALL.REL.NOINC 0x1c0 ;
BSYNC B0 ;
IMAD.MOV.U32 R3, RZ, RZ, 0x4 ;
IMAD.WIDE R2, R0, R3, c[0x0][0x170] ;
LDG.E R5, [R2.64] ;
FMUL R5, R5, R6 ;
STG.E [R2.64], R5 ;
EXIT ;
SHF.R.U32.HI R6, RZ, 0x17, R4.reuse ;
BSSY B1, 0x820 ;
SHF.R.U32.HI R5, RZ, 0x17, R3.reuse ;
IMAD.MOV.U32 R7, RZ, RZ, R3 ;
LOP3.LUT R6, R6, 0xff, RZ, 0xc0, !PT ;
IMAD.MOV.U32 R8, RZ, RZ, R4 ;
LOP3.LUT R5, R5, 0xff, RZ, 0xc0, !PT ;
IADD3 R11, R6, -0x1, RZ ;
IADD3 R10, R5, -0x1, RZ ;
ISETP.GT.U32.AND P0, PT, R11, 0xfd, PT ;
ISETP.GT.U32.OR P0, PT, R10, 0xfd, P0 ;
@!P0 IMAD.MOV.U32 R9, RZ, RZ, RZ ;
@!P0 BRA 0x400 ;
FSETP.GTU.FTZ.AND P0, PT, |R3|, +INF , PT ;
FSETP.GTU.FTZ.AND P1, PT, |R4|, +INF , PT ;
PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ;
@P0 BRA 0x800 ;
LOP3.LUT P0, RZ, R8, 0x7fffffff, R7, 0xc8, !PT ;
@!P0 BRA 0x7e0 ;
FSETP.NEU.FTZ.AND P2, PT, |R3|.reuse, +INF , PT ;
FSETP.NEU.FTZ.AND P1, PT, |R4|, +INF , PT ;
FSETP.NEU.FTZ.AND P0, PT, |R3|, +INF , PT ;
@!P1 BRA !P2, 0x7e0 ;
LOP3.LUT P2, RZ, R7, 0x7fffffff, RZ, 0xc0, !PT ;
PLOP3.LUT P1, PT, P1, P2, PT, 0x2a, 0x0 ;
@P1 BRA 0x7c0 ;
LOP3.LUT P1, RZ, R8, 0x7fffffff, RZ, 0xc0, !PT ;
PLOP3.LUT P0, PT, P0, P1, PT, 0x2a, 0x0 ;
@P0 BRA 0x790 ;
ISETP.GE.AND P0, PT, R10, RZ, PT ;
ISETP.GE.AND P1, PT, R11, RZ, PT ;
@P0 IMAD.MOV.U32 R9, RZ, RZ, RZ ;
@!P0 IMAD.MOV.U32 R9, RZ, RZ, -0x40 ;
@!P0 FFMA R7, R3, 1.84467440737095516160e+19, RZ ;
@!P1 FFMA R8, R4, 1.84467440737095516160e+19, RZ ;
@!P1 IADD3 R9, R9, 0x40, RZ ;
LEA R3, R6, 0xc0800000, 0x17 ;
BSSY B2, 0x780 ;
IADD3 R5, R5, -0x7f, RZ ;
IMAD.IADD R8, R8, 0x1, -R3 ;
IADD3 R6, R5.reuse, 0x7f, -R6 ;
IMAD R7, R5, -0x800000, R7 ;
MUFU.RCP R3, R8 ;
FADD.FTZ R4, -R8, -RZ ;
IMAD.IADD R6, R6, 0x1, R9 ;
FFMA R10, R3, R4, 1 ;
FFMA R12, R3, R10, R3 ;
FFMA R3, R7, R12, RZ ;
FFMA R10, R4, R3, R7 ;
FFMA R11, R12, R10, R3 ;
FFMA R7, R4, R11, R7 ;
FFMA R3, R12, R7, R11 ;
SHF.R.U32.HI R4, RZ, 0x17, R3 ;
LOP3.LUT R4, R4, 0xff, RZ, 0xc0, !PT ;
IMAD.IADD R8, R4, 0x1, R6 ;
IADD3 R4, R8, -0x1, RZ ;
ISETP.GE.U32.AND P0, PT, R4, 0xfe, PT ;
@!P0 BRA 0x760 ;
ISETP.GT.AND P0, PT, R8, 0xfe, PT ;
@P0 BRA 0x730 ;
ISETP.GE.AND P0, PT, R8, 0x1, PT ;
@P0 BRA 0x770 ;
ISETP.GE.AND P0, PT, R8, -0x18, PT ;
LOP3.LUT R3, R3, 0x80000000, RZ, 0xc0, !PT ;
@!P0 BRA 0x770 ;
FFMA.RZ R4, R12, R7.reuse, R11.reuse ;
ISETP.NE.AND P2, PT, R8, RZ, PT ;
FFMA.RM R5, R12, R7.reuse, R11.reuse ;
ISETP.NE.AND P1, PT, R8, RZ, PT ;
LOP3.LUT R6, R4, 0x7fffff, RZ, 0xc0, !PT ;
FFMA.RP R4, R12, R7, R11 ;
IADD3 R7, R8, 0x20, RZ ;
IMAD.MOV R8, RZ, RZ, -R8 ;
LOP3.LUT R6, R6, 0x800000, RZ, 0xfc, !PT ;
FSETP.NEU.FTZ.AND P0, PT, R4, R5, PT ;
SHF.L.U32 R7, R6, R7, RZ ;
SEL R5, R8, RZ, P2 ;
ISETP.NE.AND P1, PT, R7, RZ, P1 ;
SHF.R.U32.HI R5, RZ, R5, R6 ;
PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ;
SHF.R.U32.HI R7, RZ, 0x1, R5 ;
SEL R4, RZ, 0x1, !P0 ;
LOP3.LUT R4, R4, 0x1, R7, 0xf8, !PT ;
LOP3.LUT R4, R4, R5, RZ, 0xc0, !PT ;
IMAD.IADD R4, R7, 0x1, R4 ;
LOP3.LUT R3, R4, R3, RZ, 0xfc, !PT ;
BRA 0x770 ;
LOP3.LUT R3, R3, 0x80000000, RZ, 0xc0, !PT ;
LOP3.LUT R3, R3, 0x7f800000, RZ, 0xfc, !PT ;
BRA 0x770 ;
IMAD R3, R6, 0x800000, R3 ;
BSYNC B2 ;
BRA 0x810 ;
LOP3.LUT R3, R8, 0x80000000, R7, 0x48, !PT ;
LOP3.LUT R3, R3, 0x7f800000, RZ, 0xfc, !PT ;
BRA 0x810 ;
LOP3.LUT R3, R8, 0x80000000, R7, 0x48, !PT ;
BRA 0x810 ;
MUFU.RSQ R3, -QNAN ;
BRA 0x810 ;
FADD.FTZ R3, R3, R4 ;
BSYNC B1 ;
IMAD.MOV.U32 R6, RZ, RZ, R3 ;
IMAD.MOV.U32 R3, RZ, RZ, 0x0 ;
RET.REL.NODEC R2 0x0 ;
BRA 0x850;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
Function : vmuldiv_dp
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ;
S2R R10, SR_TID.X ;
IMAD.MOV.U32 R5, RZ, RZ, 0x8 ;
ULDC.64 UR4, c[0x0][0x118] ;
S2R R3, SR_CTAID.X ;
IMAD R10, R3, c[0x0][0x0], R10 ;
IMAD.WIDE R6, R10, R5, c[0x0][0x168] ;
LDG.E.64 R6, [R6.64] ;
IMAD.WIDE R4, R10, R5, c[0x0][0x160] ;
LDG.E.64 R4, [R4.64] ;
IMAD.MOV.U32 R2, RZ, RZ, 0x1 ;
BSSY B0, 0x1e0 ;
MUFU.RCP64H R3, R7 ;
FSETP.GEU.AND P1, PT, |R5|, 6.5827683646048100446e-37, PT ;
DFMA R8, -R6, R2, 1 ;
DFMA R8, R8, R8, R8 ;
DFMA R8, R2, R8, R2 ;
DFMA R2, -R6, R8, 1 ;
DFMA R2, R8, R2, R8 ;
DMUL R8, R4, R2 ;
DFMA R12, -R6, R8, R4 ;
DFMA R2, R2, R12, R8 ;
FFMA R0, RZ, R7, R3 ;
FSETP.GT.AND P0, PT, |R0|, 1.469367938527859385e-39, PT ;
@P0 BRA P1, 0x1d0 ;
MOV R0, 0x1b0 ;
CALL.REL.NOINC 0x240 ;
IMAD.MOV.U32 R2, RZ, RZ, R12 ;
IMAD.MOV.U32 R3, RZ, RZ, R13 ;
BSYNC B0 ;
IMAD.MOV.U32 R11, RZ, RZ, 0x8 ;
IMAD.WIDE R10, R10, R11, c[0x0][0x170] ;
LDG.E.64 R4, [R10.64] ;
DMUL R4, R4, R2 ;
STG.E.64 [R10.64], R4 ;
EXIT ;
FSETP.GEU.AND P0, PT, |R7|.reuse, 1.469367938527859385e-39, PT ;
IMAD.MOV.U32 R12, RZ, RZ, 0x1ca00000 ;
LOP3.LUT R2, R7, 0x800fffff, RZ, 0xc0, !PT ;
IMAD.MOV.U32 R14, RZ, RZ, 0x1 ;
FSETP.GEU.AND P2, PT, |R5|.reuse, 1.469367938527859385e-39, PT ;
BSSY B1, 0x7d0 ;
LOP3.LUT R3, R2, 0x3ff00000, RZ, 0xfc, !PT ;
IMAD.MOV.U32 R2, RZ, RZ, R6 ;
LOP3.LUT R11, R5, 0x7ff00000, RZ, 0xc0, !PT ;
LOP3.LUT R16, R7, 0x7ff00000, RZ, 0xc0, !PT ;
@!P0 DMUL R2, R6, 8.98846567431157953865e+307 ;
ISETP.GE.U32.AND P1, PT, R11, R16, PT ;
IMAD.MOV.U32 R17, RZ, RZ, R11 ;
@!P2 LOP3.LUT R8, R7, 0x7ff00000, RZ, 0xc0, !PT ;
@!P2 IMAD.MOV.U32 R20, RZ, RZ, RZ ;
MUFU.RCP64H R15, R3 ;
SEL R9, R12, 0x63400000, !P1 ;
@!P2 ISETP.GE.U32.AND P3, PT, R11, R8, PT ;
IMAD.MOV.U32 R8, RZ, RZ, R4 ;
LOP3.LUT R9, R9, 0x800fffff, R5, 0xf8, !PT ;
@!P2 SEL R13, R12, 0x63400000, !P3 ;
@!P0 LOP3.LUT R16, R3, 0x7ff00000, RZ, 0xc0, !PT ;
@!P2 LOP3.LUT R13, R13, 0x80000000, R5, 0xf8, !PT ;
IADD3 R22, R16, -0x1, RZ ;
@!P2 LOP3.LUT R21, R13, 0x100000, RZ, 0xfc, !PT ;
DFMA R18, R14, -R2, 1 ;
@!P2 DFMA R8, R8, 2, -R20 ;
DFMA R18, R18, R18, R18 ;
DFMA R14, R14, R18, R14 ;
@!P2 LOP3.LUT R17, R9, 0x7ff00000, RZ, 0xc0, !PT ;
IADD3 R13, R17, -0x1, RZ ;
DFMA R18, R14, -R2, 1 ;
ISETP.GT.U32.AND P0, PT, R13, 0x7feffffe, PT ;
DFMA R14, R14, R18, R14 ;
ISETP.GT.U32.OR P0, PT, R22, 0x7feffffe, P0 ;
DMUL R18, R14, R8 ;
DFMA R20, R18, -R2, R8 ;
DFMA R14, R14, R20, R18 ;
@P0 BRA 0x670 ;
LOP3.LUT R16, R7, 0x7ff00000, RZ, 0xc0, !PT ;
ISETP.GE.U32.AND P0, PT, R11.reuse, R16, PT ;
IMAD.IADD R4, R11, 0x1, -R16 ;
SEL R11, R12, 0x63400000, !P0 ;
IMNMX R4, R4, -0x46a00000, !PT ;
IMNMX R4, R4, 0x46a00000, PT ;
IMAD.IADD R11, R4, 0x1, -R11 ;
IMAD.MOV.U32 R4, RZ, RZ, RZ ;
IADD3 R5, R11, 0x7fe00000, RZ ;
DMUL R12, R14, R4 ;
FSETP.GTU.AND P0, PT, |R13|, 1.469367938527859385e-39, PT ;
@P0 BRA 0x7c0 ;
DFMA R2, R14, -R2, R8 ;
IMAD.MOV.U32 R4, RZ, RZ, RZ ;
FSETP.NEU.AND P0, PT, R3.reuse, RZ, PT ;
LOP3.LUT R7, R3, 0x80000000, R7, 0x48, !PT ;
LOP3.LUT R5, R7, R5, RZ, 0xfc, !PT ;
@!P0 BRA 0x7c0 ;
IMAD.MOV R3, RZ, RZ, -R11 ;
DMUL.RP R4, R14, R4 ;
IMAD.MOV.U32 R2, RZ, RZ, RZ ;
IADD3 R11, -R11, -0x43300000, RZ ;
DFMA R2, R12, -R2, R14 ;
LOP3.LUT R7, R5, R7, RZ, 0x3c, !PT ;
FSETP.NEU.AND P0, PT, |R3|, R11, PT ;
FSEL R12, R4, R12, !P0 ;
FSEL R13, R7, R13, !P0 ;
BRA 0x7c0 ;
DSETP.NAN.AND P0, PT, R4, R4, PT ;
@P0 BRA 0x7a0 ;
DSETP.NAN.AND P0, PT, R6, R6, PT ;
@P0 BRA 0x770 ;
ISETP.NE.AND P0, PT, R17, R16, PT ;
IMAD.MOV.U32 R12, RZ, RZ, 0x0 ;
IMAD.MOV.U32 R13, RZ, RZ, -0x80000 ;
@!P0 BRA 0x7c0 ;
ISETP.NE.AND P0, PT, R17, 0x7ff00000, PT ;
LOP3.LUT R13, R5, 0x80000000, R7, 0x48, !PT ;
ISETP.EQ.OR P0, PT, R16, RZ, !P0 ;
@P0 LOP3.LUT R2, R13, 0x7ff00000, RZ, 0xfc, !PT ;
@!P0 IMAD.MOV.U32 R12, RZ, RZ, RZ ;
@P0 IMAD.MOV.U32 R12, RZ, RZ, RZ ;
@P0 IMAD.MOV.U32 R13, RZ, RZ, R2 ;
BRA 0x7c0 ;
LOP3.LUT R13, R7, 0x80000, RZ, 0xfc, !PT ;
IMAD.MOV.U32 R12, RZ, RZ, R6 ;
BRA 0x7c0 ;
LOP3.LUT R13, R5, 0x80000, RZ, 0xfc, !PT ;
IMAD.MOV.U32 R12, RZ, RZ, R4 ;
BSYNC B1 ;
IMAD.MOV.U32 R2, RZ, RZ, R0 ;
IMAD.MOV.U32 R3, RZ, RZ, 0x0 ;
RET.REL.NODEC R2 0x0 ;
BRA 0x800;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
```
|
```amdasm
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected vmuldiv_dp ; -- Begin function vmuldiv_dp
.globl vmuldiv_dp
.p2align 8
.type vmuldiv_dp,@function
vmuldiv_dp: ; @vmuldiv_dp
; %bb.0:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x24
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 3, v[1:2]
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b64 v[2:3], v[2:3], off
global_load_b64 v[4:5], v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_load_b64 v[10:11], v[0:1], off
s_waitcnt vmcnt(1)
v_div_scale_f64 v[6:7], null, v[4:5], v[4:5], v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f64_e32 v[8:9], v[6:7]
s_waitcnt_depctr 0xfff
v_fma_f64 v[12:13], -v[6:7], v[8:9], 1.0
v_fma_f64 v[8:9], v[8:9], v[12:13], v[8:9]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[12:13], -v[6:7], v[8:9], 1.0
v_fma_f64 v[8:9], v[8:9], v[12:13], v[8:9]
v_div_scale_f64 v[12:13], vcc_lo, v[2:3], v[4:5], v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f64 v[14:15], v[12:13], v[8:9]
v_fma_f64 v[6:7], -v[6:7], v[14:15], v[12:13]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fmas_f64 v[6:7], v[6:7], v[8:9], v[14:15]
v_div_fixup_f64 v[2:3], v[6:7], v[4:5], v[2:3]
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_mul_f64 v[2:3], v[10:11], v[2:3]
global_store_b64 v[0:1], v[2:3], off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel vmuldiv_dp
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 16
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size vmuldiv_dp, .Lfunc_end0-vmuldiv_dp
; -- End function
.section .AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 276
; NumSgprs: 18
; NumVgprs: 16
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 16
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
.text
.protected vmuldiv_sp ; -- Begin function vmuldiv_sp
.globl vmuldiv_sp
.p2align 8
.type vmuldiv_sp,@function
vmuldiv_sp: ; @vmuldiv_sp
; %bb.0:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x24
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_load_b32 v4, v[0:1], off
s_waitcnt vmcnt(1)
v_div_scale_f32 v5, null, v3, v3, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f32_e32 v6, v5
s_waitcnt_depctr 0xfff
v_fma_f32 v7, -v5, v6, 1.0
v_fmac_f32_e32 v6, v7, v6
v_div_scale_f32 v7, vcc_lo, v2, v3, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v8, v7, v6
v_fma_f32 v9, -v5, v8, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v8, v9, v6
v_fma_f32 v5, -v5, v8, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fmas_f32 v5, v5, v6, v8
v_div_fixup_f32 v2, v5, v3, v2
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_mul_f32_e32 v2, v4, v2
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel vmuldiv_sp
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 10
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size vmuldiv_sp, .Lfunc_end1-vmuldiv_sp
; -- End function
.section .AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 260
; NumSgprs: 18
; NumVgprs: 10
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 10
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object ; @__hip_cuid_
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0 ; 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: vmuldiv_dp
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: vmuldiv_dp.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 16
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: vmuldiv_sp
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: vmuldiv_sp.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 10
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
```
| 5,513 | 5,450 |
203 |
Convert the following CUDA host assembly code to AMD host assembly:
```cudaasm
.file "tmpxft_000f0830_00000000-6_vecop.cudafe1.cpp"
.text
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z36__device_stub__Z10vmuldiv_dpPKdS0_PdPKdS0_Pd
.type _Z36__device_stub__Z10vmuldiv_dpPKdS0_PdPKdS0_Pd, @function
_Z36__device_stub__Z10vmuldiv_dpPKdS0_PdPKdS0_Pd:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq vmuldiv_dp(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z36__device_stub__Z10vmuldiv_dpPKdS0_PdPKdS0_Pd, .-_Z36__device_stub__Z10vmuldiv_dpPKdS0_PdPKdS0_Pd
.globl vmuldiv_dp
.type vmuldiv_dp, @function
vmuldiv_dp:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z36__device_stub__Z10vmuldiv_dpPKdS0_PdPKdS0_Pd
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size vmuldiv_dp, .-vmuldiv_dp
.globl _Z36__device_stub__Z10vmuldiv_spPKfS0_PfPKfS0_Pf
.type _Z36__device_stub__Z10vmuldiv_spPKfS0_PfPKfS0_Pf, @function
_Z36__device_stub__Z10vmuldiv_spPKfS0_PfPKfS0_Pf:
.LFB2053:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq vmuldiv_sp(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2053:
.size _Z36__device_stub__Z10vmuldiv_spPKfS0_PfPKfS0_Pf, .-_Z36__device_stub__Z10vmuldiv_spPKfS0_PfPKfS0_Pf
.globl vmuldiv_sp
.type vmuldiv_sp, @function
vmuldiv_sp:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z36__device_stub__Z10vmuldiv_spPKfS0_PfPKfS0_Pf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size vmuldiv_sp, .-vmuldiv_sp
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "vmuldiv_sp"
.LC1:
.string "vmuldiv_dp"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2056:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq vmuldiv_sp(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq vmuldiv_dp(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2056:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
```
|
```amdasm
.text
.file "vecop.hip"
.globl __device_stub__vmuldiv_dp # -- Begin function __device_stub__vmuldiv_dp
.type __device_stub__vmuldiv_dp,@function
__device_stub__vmuldiv_dp: # @__device_stub__vmuldiv_dp
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $112, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 40(%rsp), %rax
movq %rdi, (%rax)
leaq 32(%rsp), %rcx
movq %rsi, (%rcx)
leaq 24(%rsp), %rsi
movq %rdx, (%rsi)
leaq 80(%rsp), %rbx
movq %rax, (%rbx)
movq %rcx, 8(%rbx)
movq %rsi, 16(%rbx)
leaq 64(%rsp), %r14
leaq 48(%rsp), %r15
leaq 16(%rsp), %r12
leaq 8(%rsp), %r13
movq %r14, %rdi
movq %r15, %rsi
movq %r12, %rdx
movq %r13, %rcx
callq __hipPopCallConfiguration
movq (%r14), %rsi
movl 8(%r14), %edx
movq (%r15), %rcx
movl 8(%r15), %r8d
movl $vmuldiv_dp, %edi
movq %rbx, %r9
pushq (%r13)
.cfi_adjust_cfa_offset 8
pushq (%r12)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $128, %rsp
.cfi_adjust_cfa_offset -128
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size __device_stub__vmuldiv_dp, .Lfunc_end0-__device_stub__vmuldiv_dp
.cfi_endproc
# -- End function
.globl __device_stub__vmuldiv_sp # -- Begin function __device_stub__vmuldiv_sp
.type __device_stub__vmuldiv_sp,@function
__device_stub__vmuldiv_sp: # @__device_stub__vmuldiv_sp
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $112, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 40(%rsp), %rax
movq %rdi, (%rax)
leaq 32(%rsp), %rcx
movq %rsi, (%rcx)
leaq 24(%rsp), %rsi
movq %rdx, (%rsi)
leaq 80(%rsp), %rbx
movq %rax, (%rbx)
movq %rcx, 8(%rbx)
movq %rsi, 16(%rbx)
leaq 64(%rsp), %r14
leaq 48(%rsp), %r15
leaq 16(%rsp), %r12
leaq 8(%rsp), %r13
movq %r14, %rdi
movq %r15, %rsi
movq %r12, %rdx
movq %r13, %rcx
callq __hipPopCallConfiguration
movq (%r14), %rsi
movl 8(%r14), %edx
movq (%r15), %rcx
movl 8(%r15), %r8d
movl $vmuldiv_sp, %edi
movq %rbx, %r9
pushq (%r13)
.cfi_adjust_cfa_offset 8
pushq (%r12)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $128, %rsp
.cfi_adjust_cfa_offset -128
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size __device_stub__vmuldiv_sp, .Lfunc_end1-__device_stub__vmuldiv_sp
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
movq __hip_gpubin_handle(%rip), %rbx
testq %rbx, %rbx
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, %rbx
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $vmuldiv_dp, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $vmuldiv_sp, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type vmuldiv_dp,@object # @vmuldiv_dp
.section .rodata,"a",@progbits
.globl vmuldiv_dp
.p2align 3, 0x0
vmuldiv_dp:
.quad __device_stub__vmuldiv_dp
.size vmuldiv_dp, 8
.type vmuldiv_sp,@object # @vmuldiv_sp
.globl vmuldiv_sp
.p2align 3, 0x0
vmuldiv_sp:
.quad __device_stub__vmuldiv_sp
.size vmuldiv_sp, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "vmuldiv_dp"
.size .L__unnamed_1, 11
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "vmuldiv_sp"
.size .L__unnamed_2, 11
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __device_stub__vmuldiv_dp
.addrsig_sym __device_stub__vmuldiv_sp
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym vmuldiv_dp
.addrsig_sym vmuldiv_sp
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
```
| 2,923 | 3,013 |
204 |
Convert the following CUDA device assembly code to AMD device assembly:
```cudaasm
code for sm_80
Function : _Z10update_srciiiPf
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ;
I2F.F64 R10, c[0x0][0x168] ;
ULDC.64 UR4, c[0x0][0x118] ;
IADD3 R1, R1, -0x30, RZ ;
DMUL R10, R10, c[0x2][0x0] ;
LOP3.LUT R0, R11, 0x7fffffff, RZ, 0xc0, !PT ;
ISETP.EQ.AND P1, PT, R10, RZ, PT ;
ISETP.NE.AND P0, PT, R0, 0x7ff00000, PT ;
@!P0 BRA P1, 0x170 ;
DMUL R4, R10, c[0x2][0x8] ;
DSETP.GE.AND P0, PT, |R10|, 2.14748364800000000000e+09, PT ;
F2I.F64 R0, R4 ;
I2F.F64 R6, R0 ;
STL [R1], R0 ;
DFMA R2, -R6, c[0x2][0x10], R10 ;
DFMA R2, -R6, c[0x2][0x18], R2 ;
DFMA R2, -R6, c[0x2][0x20], R2 ;
@!P0 BRA 0x190 ;
IADD3 R13, R1, c[0x0][0x20], RZ ;
MOV R12, 0x150 ;
CALL.REL.NOINC 0x420 ;
LDL R0, [R1] ;
BRA 0x190 ;
DMUL R2, RZ, R10 ;
IMAD.MOV.U32 R0, RZ, RZ, RZ ;
IMAD.SHL.U32 R4, R0, 0x8, RZ ;
IMAD.MOV.U32 R15, RZ, RZ, 0x8 ;
LOP3.LUT R4, R4, 0x8, RZ, 0xc0, !PT ;
IMAD.WIDE R14, R4, R15, c[0x4][0x0] ;
LDG.E.64.CONSTANT R16, [R14.64+0x8] ;
LDG.E.64.CONSTANT R18, [R14.64+0x10] ;
LDG.E.64.CONSTANT R12, [R14.64+0x18] ;
LDG.E.64.CONSTANT R10, [R14.64+0x20] ;
LDG.E.64.CONSTANT R8, [R14.64+0x28] ;
LDG.E.64.CONSTANT R6, [R14.64+0x30] ;
R2P PR, R0, 0x3 ;
IMAD.MOV.U32 R20, RZ, RZ, 0x79785eba ;
DMUL R4, R2, R2 ;
IMAD.MOV.U32 R0, RZ, RZ, 0x3de5db65 ;
FSEL R20, -R20, 4.2945490664224492434e-19, !P0 ;
FSEL R21, R0, -0.082518599927425384521, !P0 ;
IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x160] ;
DFMA R16, R4, R20, R16 ;
DFMA R16, R4, R16, R18 ;
DFMA R12, R4, R16, R12 ;
DFMA R10, R4, R12, R10 ;
DFMA R8, R4, R10, R8 ;
DFMA R6, R4, R8, R6 ;
DFMA R2, R6, R2, R2 ;
@P0 DFMA R2, R4, R6, 1 ;
IMAD.MOV.U32 R7, RZ, RZ, 0x2 ;
IMAD.MOV.U32 R4, RZ, RZ, RZ ;
IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x160] ;
@P1 DFMA R2, R2, -1, RZ ;
IMAD.MOV.U32 R6, RZ, RZ, c[0x0][0x164] ;
IMAD.HI.U32 R0, R7, R0, R4 ;
IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x164] ;
SHF.R.S32.HI R0, RZ, 0x1, R0 ;
F2F.F32.F64 R3, R2 ;
IMAD.HI.U32 R4, R7, R6, R4 ;
SHF.R.S32.HI R5, RZ, 0x1, R4 ;
IMAD.MOV.U32 R4, RZ, RZ, 0x4 ;
IMAD R5, R0, c[0x0][0x164], R5 ;
IMAD.WIDE R4, R5, R4, c[0x0][0x170] ;
STG.E [R4.64], R3 ;
EXIT ;
SHF.R.U32.HI R0, RZ, 0x14, R11.reuse ;
IMAD.MOV.U32 R2, RZ, RZ, R10 ;
IMAD.MOV.U32 R9, RZ, RZ, R11 ;
LOP3.LUT R0, R0, 0x7ff, RZ, 0xc0, !PT ;
ISETP.NE.AND P0, PT, R0, 0x7ff, PT ;
@!P0 BRA 0xd70 ;
IADD3 R15, R0, -0x400, RZ ;
CS2R R16, SRZ ;
IADD3 R5, R1, 0x8, RZ ;
SHF.R.U32.HI R4, RZ, 0x6, R15 ;
LOP3.LUT P2, R15, R15, 0x3f, RZ, 0xc0, !PT ;
IADD3 R3, -R4.reuse, 0x10, RZ ;
IADD3 R0, -R4, 0x13, RZ ;
ISETP.GT.AND P0, PT, R3, 0xe, PT ;
IADD3 R4, -R4, 0xf, RZ ;
SEL R0, R0, 0x12, !P0 ;
IMAD.MOV.U32 R7, RZ, RZ, R4 ;
ISETP.GT.AND P0, PT, R3, R0, PT ;
@P0 BRA 0x790 ;
IMAD.MOV.U32 R7, RZ, RZ, 0x8 ;
SHF.L.U64.HI R19, R2.reuse, 0xb, R9 ;
IMAD.SHL.U32 R23, R2, 0x800, RZ ;
CS2R R16, SRZ ;
IMAD.WIDE R6, R4, R7, c[0x4][0x8] ;
LOP3.LUT R19, R19, 0x80000000, RZ, 0xfc, !PT ;
ULDC.64 UR6, c[0x0][0x118] ;
IMAD.MOV.U32 R9, RZ, RZ, R7 ;
IMAD.MOV.U32 R21, RZ, RZ, R5 ;
IMAD.MOV.U32 R7, RZ, RZ, R4 ;
IMAD.MOV.U32 R2, RZ, RZ, R6 ;
IMAD.MOV.U32 R3, RZ, RZ, R9 ;
LDG.E.64.CONSTANT R2, [R2.64] ;
IADD3 R7, R7, 0x1, RZ ;
IMAD.WIDE.U32 R16, P3, R2, R23, R16 ;
IMAD R25, R2.reuse, R19.reuse, RZ ;
IMAD.HI.U32 R8, R2, R19, RZ ;
IADD3 R17, P0, R25, R17, RZ ;
IMAD R14, R3.reuse, R23.reuse, RZ ;
IMAD.HI.U32 R25, R3, R23, RZ ;
IADD3 R17, P1, R14, R17, RZ ;
IMAD.X R8, RZ, RZ, R8, P3 ;
ISETP.GE.AND P3, PT, R7, R0, PT ;
IMAD.HI.U32 R2, R3, R19.reuse, RZ ;
STL.64 [R21], R16 ;
IADD3.X R8, P0, R25, R8, RZ, P0, !PT ;
IMAD R3, R3, R19, RZ ;
IMAD.X R2, RZ, RZ, R2, P0 ;
IADD3.X R8, P1, R3, R8, RZ, P1, !PT ;
IADD3 R6, P0, R6, 0x8, RZ ;
IMAD.X R3, RZ, RZ, R2, P1 ;
IADD3 R21, R21, 0x8, RZ ;
IMAD.X R9, RZ, RZ, R9, P0 ;
IMAD.MOV.U32 R16, RZ, RZ, R8 ;
IMAD.MOV.U32 R17, RZ, RZ, R3 ;
@!P3 BRA 0x5f0 ;
IMAD.IADD R4, R7, 0x1, -R4 ;
IMAD R19, R4, 0x8, R5 ;
STL.64 [R19], R16 ;
LDL.64 R2, [R1+0x18] ;
@P2 LDL.64 R6, [R1+0x10] ;
LDL.64 R4, [R1+0x20] ;
@P2 IADD3 R0, -R15, 0x40, RZ ;
@P2 SHF.L.U32 R9, R2.reuse, R15.reuse, RZ ;
@P2 SHF.R.U64 R10, R2, R0.reuse, R3 ;
@P2 SHF.R.U64 R6, R6, R0, R7 ;
@P2 SHF.L.U64.HI R8, R2, R15, R3 ;
@P2 LOP3.LUT R2, R6, R9, RZ, 0xfc, !PT ;
@P2 SHF.L.U32 R9, R4, R15, RZ ;
@P2 SHF.R.U32.HI R7, RZ, R0.reuse, R7 ;
IMAD.SHL.U32 R6, R2, 0x4, RZ ;
@P2 SHF.L.U64.HI R15, R4, R15, R5 ;
@P2 SHF.R.U32.HI R0, RZ, R0, R3 ;
@P2 LOP3.LUT R4, R9, R10, RZ, 0xfc, !PT ;
@P2 LOP3.LUT R3, R7, R8, RZ, 0xfc, !PT ;
@P2 LOP3.LUT R5, R15, R0, RZ, 0xfc, !PT ;
IMAD.SHL.U32 R17, R4, 0x4, RZ ;
SHF.L.U64.HI R9, R2, 0x2, R3 ;
SHF.R.U32.HI R2, RZ, 0x1e, R3 ;
IADD3 RZ, P0, RZ, -R6, RZ ;
LOP3.LUT R0, RZ, R9, RZ, 0x33, !PT ;
LOP3.LUT R17, R2, R17, RZ, 0xfc, !PT ;
SHF.L.U64.HI R8, R4, 0x2, R5 ;
IADD3.X R4, P0, RZ, R0, RZ, P0, !PT ;
LOP3.LUT R0, RZ, R17, RZ, 0x33, !PT ;
LOP3.LUT R3, RZ, R8, RZ, 0x33, !PT ;
IADD3.X R0, P0, RZ, R0, RZ, P0, !PT ;
SHF.R.U32.HI R2, RZ, 0x1d, R5 ;
IMAD.X R3, RZ, RZ, R3, P0 ;
LOP3.LUT P1, RZ, R2.reuse, 0x1, RZ, 0xc0, !PT ;
LOP3.LUT R2, R2, 0x1, RZ, 0xc0, !PT ;
SEL R3, R8, R3, !P1 ;
SEL R17, R17, R0, !P1 ;
ISETP.NE.U32.AND P0, PT, R3, RZ, PT ;
SEL R4, R9, R4, !P1 ;
SEL R7, R17, R3, !P0 ;
@P1 IMAD.MOV R6, RZ, RZ, -R6 ;
LEA.HI R5, R5, R2, RZ, 0x2 ;
FLO.U32 R7, R7 ;
IADD3 R8, -R7.reuse, 0x1f, RZ ;
IADD3 R0, -R7, 0x3f, RZ ;
@P0 IMAD.MOV R0, RZ, RZ, R8 ;
ISETP.NE.U32.AND P0, PT, R0.reuse, RZ, PT ;
IADD3 R9, -R0, 0x40, RZ ;
ISETP.NE.AND.EX P0, PT, RZ, RZ, PT, P0 ;
SHF.L.U32 R15, R17.reuse, R0.reuse, RZ ;
SHF.R.U64 R6, R6, R9, R4 ;
SHF.L.U64.HI R7, R17, R0, R3 ;
SHF.R.U32.HI R4, RZ, R9, R4 ;
@P0 LOP3.LUT R17, R6, R15, RZ, 0xfc, !PT ;
@P0 LOP3.LUT R3, R4, R7, RZ, 0xfc, !PT ;
IMAD.MOV.U32 R7, RZ, RZ, RZ ;
IMAD.WIDE.U32 R8, R17, 0x2168c235, RZ ;
IMAD.MOV.U32 R6, RZ, RZ, R9 ;
IADD3 RZ, P0, R8, R8, RZ ;
IMAD.HI.U32 R4, R3, -0x36f0255e, RZ ;
IMAD.WIDE.U32 R6, R17, -0x36f0255e, R6 ;
IMAD R9, R3.reuse, -0x36f0255e, RZ ;
IMAD.WIDE.U32 R6, P2, R3, 0x2168c235, R6 ;
IMAD.X R3, RZ, RZ, R4, P2 ;
IADD3 R4, P2, R9, R7, RZ ;
IADD3.X RZ, P0, R6, R6, RZ, P0, !PT ;
ISETP.GT.U32.AND P3, PT, R4.reuse, RZ, PT ;
IMAD.X R3, RZ, RZ, R3, P2 ;
IADD3.X R7, P2, R4, R4, RZ, P0, !PT ;
ISETP.GT.AND.EX P0, PT, R3.reuse, RZ, PT, P3 ;
IMAD.X R6, R3, 0x1, R3, P2 ;
LOP3.LUT P2, RZ, R11, 0x80000000, RZ, 0xc0, !PT ;
SEL R7, R7, R4, P0 ;
SEL R4, R6, R3, P0 ;
IADD3 R3, P3, R7, 0x1, RZ ;
IMAD.MOV R7, RZ, RZ, -R5 ;
IADD3 R6, R13, -c[0x0][0x20], RZ ;
SEL R9, RZ, 0x1, !P0 ;
IMAD.X R4, RZ, RZ, R4, P3 ;
LOP3.LUT R11, R11, 0x80000000, RZ, 0xc0, !PT ;
@P2 IMAD.MOV.U32 R5, RZ, RZ, R7 ;
IMAD.MOV.U32 R7, RZ, RZ, RZ ;
SHF.R.U64 R2, R3, 0xa, R4 ;
IMAD.IADD R0, R9, 0x1, R0 ;
STL [R6], R5 ;
@P1 LOP3.LUT R11, R11, 0x80000000, RZ, 0x3c, !PT ;
IADD3 R2, P2, R2, 0x1, RZ ;
LEA.HI.X R3, R4, RZ, RZ, 0x16, P2 ;
SHF.R.U64 R2, R2, 0x1, R3 ;
IADD3 R2, P0, P2, R2, RZ, -R7 ;
IMAD.SHL.U32 R7, R0, 0x100000, RZ ;
SHF.R.U32.HI R0, RZ, 0x1, R3 ;
IADD3.X R0, R0, 0x3fe00000, ~R7, P0, P2 ;
LOP3.LUT R9, R0, R11, RZ, 0xfc, !PT ;
IMAD.MOV.U32 R13, RZ, RZ, 0x0 ;
IMAD.MOV.U32 R3, RZ, RZ, R9 ;
RET.REL.NODEC R12 0x0 ;
BRA 0xda0;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
Function : _Z6updateiiPfS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ;
IABS R7, c[0x0][0x164] ;
S2R R2, SR_CTAID.X ;
UMOV UR5, 0x1 ;
I2F.RP R0, R7 ;
S2R R3, SR_TID.X ;
ULDC.64 UR6, c[0x0][0x160] ;
UIADD3 UR4, -UR5, UR6, URZ ;
MUFU.RCP R0, R0 ;
IMAD R2, R2, c[0x0][0x0], R3 ;
IADD3 R4, R0, 0xffffffe, RZ ;
IABS R0, R2 ;
F2I.FTZ.U32.TRUNC.NTZ R5, R4 ;
HFMA2.MMA R4, -RZ, RZ, 0, 0 ;
IMAD.MOV R6, RZ, RZ, -R5 ;
IMAD R3, R6, R7, RZ ;
IMAD.HI.U32 R5, R5, R3, R4 ;
IMAD.HI.U32 R5, R5, R0, RZ ;
IMAD.MOV R3, RZ, RZ, -R5 ;
IMAD R0, R7, R3, R0 ;
ISETP.GT.U32.AND P2, PT, R7, R0, PT ;
@!P2 IADD3 R0, R0, -R7.reuse, RZ ;
@!P2 IADD3 R5, R5, 0x1, RZ ;
ISETP.GE.U32.AND P0, PT, R0, R7, PT ;
LOP3.LUT R0, R2, c[0x0][0x164], RZ, 0x3c, !PT ;
ISETP.NE.AND P2, PT, RZ, c[0x0][0x164], PT ;
ISETP.GE.AND P1, PT, R0, RZ, PT ;
@P0 IADD3 R5, R5, 0x1, RZ ;
@!P1 IMAD.MOV R5, RZ, RZ, -R5 ;
@!P2 LOP3.LUT R5, RZ, c[0x0][0x164], RZ, 0x33, !PT ;
IADD3 R3, -R5.reuse, RZ, RZ ;
ISETP.GE.AND P0, PT, R5, UR4, PT ;
UIADD3 UR4, -UR5, UR7, URZ ;
IMAD R0, R3, c[0x0][0x164], R2 ;
ISETP.LT.OR P0, PT, R5, 0x1, P0 ;
ISETP.LT.OR P0, PT, R0, 0x1, P0 ;
ISETP.GE.OR P0, PT, R0, UR4, P0 ;
@P0 EXIT ;
IADD3 R6, R2.reuse, c[0x0][0x164], RZ ;
IMAD.MOV.U32 R3, RZ, RZ, 0x4 ;
IADD3 R4, R2, -c[0x0][0x164], RZ ;
ULDC.64 UR4, c[0x0][0x118] ;
IMAD.WIDE R6, R6, R3, c[0x0][0x170] ;
IMAD.WIDE R4, R4, R3.reuse, c[0x0][0x170] ;
LDG.E R6, [R6.64] ;
IMAD.WIDE R8, R2.reuse, R3.reuse, c[0x0][0x170] ;
LDG.E R5, [R4.64] ;
LDG.E R11, [R8.64+-0x4] ;
LDG.E R13, [R8.64+0x4] ;
LDG.E R15, [R8.64] ;
IMAD.WIDE R2, R2, R3, c[0x0][0x168] ;
LDG.E R12, [R2.64] ;
FADD R0, R6, R5 ;
FADD R0, R0, R11 ;
FADD R0, R0, R13 ;
FADD R10, R15.reuse, R15 ;
FFMA R0, R15, -4, R0 ;
F2F.F64.F32 R10, R10 ;
F2F.F64.F32 R4, R0 ;
F2F.F64.F32 R6, R12 ;
DFMA R4, R4, 0.25, R10 ;
DADD R4, R4, -R6 ;
F2F.F32.F64 R5, R4 ;
STG.E [R2.64], R5 ;
EXIT ;
BRA 0x410;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
```
|
```amdasm
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6updateiiPfS_ ; -- Begin function _Z6updateiiPfS_
.globl _Z6updateiiPfS_
.p2align 8
.type _Z6updateiiPfS_,@function
_Z6updateiiPfS_: ; @_Z6updateiiPfS_
; %bb.0:
s_clause 0x1
s_load_b64 s[4:5], s[0:1], 0x0
s_load_b32 s2, s[0:1], 0x24
s_waitcnt lgkmcnt(0)
s_ashr_i32 s3, s5, 31
s_and_b32 s2, s2, 0xffff
s_add_i32 s6, s5, s3
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_xor_b32 s6, s6, s3
v_cvt_f32_u32_e32 v1, s6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v1, v1
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v1, 0x4f7ffffe, v1
v_cvt_u32_f32_e32 v3, v1
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_sub_i32 s2, 0, s6
s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
v_mul_lo_u32 v0, s2, v3
s_add_i32 s2, s4, -1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v2, 31, v1
v_mul_hi_u32 v0, v3, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v4, v1, v2
v_xor_b32_e32 v4, v4, v2
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v0, v3, v0
v_mul_hi_u32 v0, v4, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v3, v0, s6
v_sub_nc_u32_e32 v3, v4, v3
v_add_nc_u32_e32 v4, 1, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v5, s6, v3
v_cmp_le_u32_e32 vcc_lo, s6, v3
v_dual_cndmask_b32 v3, v3, v5 :: v_dual_cndmask_b32 v0, v0, v4
v_xor_b32_e32 v5, s3, v2
s_add_i32 s3, s5, -1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cmp_le_u32_e32 vcc_lo, s6, v3
v_add_nc_u32_e32 v4, 1, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v0, v0, v4, vcc_lo
v_xor_b32_e32 v0, v0, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v0, v0, v5
v_mul_lo_u32 v3, v0, s5
v_cmp_gt_i32_e32 vcc_lo, s2, v0
v_cmp_lt_i32_e64 s4, 0, v0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v3, v1, v3
v_cmp_gt_i32_e64 s2, s3, v3
v_cmp_lt_i32_e64 s3, 0, v3
s_delay_alu instid0(VALU_DEP_2)
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
s_and_b32 s2, s2, s3
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, s4, s2
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_2
; %bb.1:
s_load_b128 s[0:3], s[0:1], 0x8
v_subrev_nc_u32_e32 v3, s5, v1
v_add_nc_u32_e32 v5, s5, v1
v_lshlrev_b64 v[7:8], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_ashrrev_i32_e32 v4, 31, v3
v_ashrrev_i32_e32 v6, 31, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[3:4], 2, v[3:4]
v_lshlrev_b64 v[0:1], 2, v[5:6]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v2, vcc_lo, s2, v3
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v4, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s2, v7
v_add_co_ci_u32_e32 v5, vcc_lo, s3, v8, vcc_lo
s_clause 0x2
global_load_b32 v6, v[2:3], off
global_load_b32 v9, v[0:1], off
global_load_b96 v[0:2], v[4:5], off offset:-4
v_add_co_u32 v3, vcc_lo, s0, v7
v_add_co_ci_u32_e32 v4, vcc_lo, s1, v8, vcc_lo
global_load_b32 v7, v[3:4], off
s_waitcnt vmcnt(2)
v_add_f32_e32 v5, v6, v9
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v0, v5, v0
v_add_f32_e32 v2, v0, v2
v_add_f32_e32 v0, v1, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fmac_f32_e32 v2, -4.0, v1
v_cvt_f64_f32_e32 v[0:1], v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_f64_f32_e32 v[5:6], v2
v_fma_f64 v[0:1], 0x3fd00000, v[5:6], v[0:1]
s_waitcnt vmcnt(0)
v_cvt_f64_f32_e32 v[5:6], v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[0:1], v[0:1], -v[5:6]
v_cvt_f32_f64_e32 v0, v[0:1]
global_store_b32 v[3:4], v0, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6updateiiPfS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 10
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6updateiiPfS_, .Lfunc_end0-_Z6updateiiPfS_
; -- End function
.section .AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 560
; NumSgprs: 18
; NumVgprs: 10
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 10
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
.text
.protected _Z10update_srciiiPf ; -- Begin function _Z10update_srciiiPf
.globl _Z10update_srciiiPf
.p2align 8
.type _Z10update_srciiiPf,@function
_Z10update_srciiiPf: ; @_Z10update_srciiiPf
; %bb.0:
s_load_b128 s[4:7], s[0:1], 0x0
s_mov_b32 s2, 0x9999999a
s_mov_b32 s3, 0x3fb99999
s_waitcnt lgkmcnt(0)
v_cvt_f64_i32_e32 v[0:1], s6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f64 v[0:1], v[0:1], s[2:3]
v_cmp_ngt_f64_e64 s2, 0x41d00000, |v[0:1]|
s_delay_alu instid0(VALU_DEP_1)
s_and_b32 vcc_lo, exec_lo, s2
s_cbranch_vccz .LBB1_2
; %bb.1:
v_ldexp_f64 v[2:3], |v[0:1]|, 0xffffff80
v_cmp_le_f64_e64 vcc_lo, 0x7b000000, |v[0:1]|
v_trig_preop_f64 v[4:5], |v[0:1]|, 0
v_and_b32_e32 v6, 0x7fffffff, v1
v_trig_preop_f64 v[16:17], |v[0:1]|, 2
s_mov_b32 s6, 0
s_mov_b32 s8, 0x33145c07
s_mov_b32 s9, 0x3c91a626
v_dual_cndmask_b32 v3, v6, v3 :: v_dual_cndmask_b32 v2, v0, v2
v_trig_preop_f64 v[6:7], |v[0:1]|, 1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
v_mul_f64 v[8:9], v[4:5], v[2:3]
v_mul_f64 v[22:23], v[16:17], v[2:3]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_mul_f64 v[10:11], v[6:7], v[2:3]
v_fma_f64 v[4:5], v[4:5], v[2:3], -v[8:9]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
v_fma_f64 v[6:7], v[6:7], v[2:3], -v[10:11]
v_fma_f64 v[2:3], v[16:17], v[2:3], -v[22:23]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[12:13], v[10:11], v[4:5]
v_add_f64 v[14:15], v[12:13], -v[10:11]
v_add_f64 v[20:21], v[8:9], v[12:13]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_f64 v[18:19], v[12:13], -v[14:15]
v_add_f64 v[4:5], v[4:5], -v[14:15]
v_ldexp_f64 v[14:15], v[20:21], -2
v_add_f64 v[8:9], v[20:21], -v[8:9]
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_add_f64 v[10:11], v[10:11], -v[18:19]
v_add_f64 v[18:19], v[22:23], v[6:7]
v_cmp_neq_f64_e64 vcc_lo, 0x7ff00000, |v[14:15]|
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_f64 v[8:9], v[12:13], -v[8:9]
v_add_f64 v[4:5], v[4:5], v[10:11]
v_fract_f64_e32 v[10:11], v[14:15]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f64 v[12:13], v[18:19], v[4:5]
v_dual_cndmask_b32 v11, 0, v11 :: v_dual_cndmask_b32 v10, 0, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_ldexp_f64 v[10:11], v[10:11], 2
v_add_f64 v[14:15], v[8:9], v[12:13]
v_add_f64 v[24:25], v[12:13], -v[18:19]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f64 v[20:21], v[14:15], v[10:11]
v_add_f64 v[30:31], v[12:13], -v[24:25]
v_add_f64 v[4:5], v[4:5], -v[24:25]
v_add_f64 v[8:9], v[14:15], -v[8:9]
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_cmp_gt_f64_e32 vcc_lo, 0, v[20:21]
v_add_f64 v[20:21], v[18:19], -v[22:23]
s_and_b32 s2, vcc_lo, exec_lo
s_cselect_b32 s7, 0x40100000, 0
v_add_f64 v[28:29], v[18:19], -v[20:21]
v_add_f64 v[10:11], v[10:11], s[6:7]
v_add_f64 v[6:7], v[6:7], -v[20:21]
v_add_f64 v[18:19], v[18:19], -v[30:31]
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_f64 v[20:21], v[22:23], -v[28:29]
v_add_f64 v[26:27], v[14:15], v[10:11]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f64 v[4:5], v[4:5], v[18:19]
v_add_f64 v[6:7], v[6:7], v[20:21]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cvt_i32_f64_e32 v26, v[26:27]
v_add_f64 v[4:5], v[6:7], v[4:5]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_cvt_f64_i32_e32 v[24:25], v26
v_add_f64 v[6:7], v[12:13], -v[8:9]
v_add_f64 v[2:3], v[2:3], v[4:5]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f64 v[10:11], v[10:11], -v[24:25]
v_add_f64 v[2:3], v[6:7], v[2:3]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[16:17], v[14:15], v[10:11]
v_add_f64 v[4:5], v[16:17], -v[10:11]
v_cmp_le_f64_e32 vcc_lo, 0.5, v[16:17]
s_delay_alu instid0(VALU_DEP_2)
v_add_f64 v[4:5], v[14:15], -v[4:5]
s_and_b32 s2, vcc_lo, exec_lo
s_cselect_b32 s7, 0x3ff00000, 0
v_add_co_ci_u32_e64 v6, s2, 0, v26, vcc_lo
s_mov_b32 s2, 0x54442d18
s_mov_b32 s3, 0x3ff921fb
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_f64 v[2:3], v[2:3], v[4:5]
v_add_f64 v[4:5], v[16:17], -s[6:7]
v_add_f64 v[7:8], v[4:5], v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_f64 v[9:10], v[7:8], s[2:3]
v_add_f64 v[4:5], v[7:8], -v[4:5]
v_fma_f64 v[11:12], v[7:8], s[2:3], -v[9:10]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f64 v[2:3], v[2:3], -v[4:5]
v_fma_f64 v[4:5], v[7:8], s[8:9], v[11:12]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[4:5], v[2:3], s[2:3], v[4:5]
v_add_f64 v[2:3], v[9:10], v[4:5]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[7:8], v[2:3], -v[9:10]
v_add_f64 v[4:5], v[4:5], -v[7:8]
s_branch .LBB1_3
.LBB1_2:
s_mov_b32 s6, -1
; implicit-def: $vgpr6
; implicit-def: $vgpr2_vgpr3
; implicit-def: $vgpr4_vgpr5
.LBB1_3: ; %Flow
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 vcc_lo, exec_lo, s6
s_cbranch_vccnz .LBB1_5
; %bb.4:
s_mov_b32 s2, 0x6dc9c883
s_mov_b32 s3, 0x3fe45f30
s_mov_b32 s7, 0xbc91a626
v_mul_f64 v[2:3], |v[0:1]|, s[2:3]
s_mov_b32 s2, 0x54442d18
s_mov_b32 s3, 0xbff921fb
s_mov_b32 s6, 0x33145c00
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_rndne_f64_e32 v[6:7], v[2:3]
v_fma_f64 v[2:3], v[6:7], s[2:3], |v[0:1]|
v_mul_f64 v[4:5], v[6:7], s[6:7]
s_mov_b32 s2, 0x252049c0
s_mov_b32 s3, 0xb97b839a
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f64 v[10:11], v[6:7], s[6:7], v[2:3]
v_add_f64 v[8:9], v[2:3], v[4:5]
s_mov_b32 s7, 0x3c91a626
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f64 v[2:3], v[2:3], -v[8:9]
v_add_f64 v[8:9], v[8:9], -v[10:11]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_f64 v[2:3], v[2:3], v[4:5]
v_fma_f64 v[4:5], v[6:7], s[6:7], v[4:5]
v_add_f64 v[2:3], v[8:9], v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[2:3], v[2:3], -v[4:5]
v_fma_f64 v[4:5], v[6:7], s[2:3], v[2:3]
v_cvt_i32_f64_e32 v6, v[6:7]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[2:3], v[10:11], v[4:5]
v_add_f64 v[8:9], v[2:3], -v[10:11]
s_delay_alu instid0(VALU_DEP_1)
v_add_f64 v[4:5], v[4:5], -v[8:9]
.LBB1_5: ; %_ZL3sind.exit
v_mul_f64 v[7:8], v[2:3], v[2:3]
s_mov_b32 s2, 0xb42fdfa7
s_mov_b32 s6, 0xf9a43bb8
s_mov_b32 s3, 0xbe5ae600
s_mov_b32 s7, 0x3de5e0b2
s_mov_b32 s8, 0x796cde01
s_mov_b32 s9, 0x3ec71de3
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_f64 v[17:18], v[4:5], 0.5
s_load_b64 s[0:1], s[0:1], 0x10
v_fma_f64 v[9:10], v[7:8], s[6:7], s[2:3]
s_mov_b32 s2, 0x9037ab78
s_mov_b32 s6, 0x46cc5e42
s_mov_b32 s3, 0x3e21eeb6
s_mov_b32 s7, 0xbda907db
v_mul_f64 v[13:14], v[7:8], 0.5
v_fma_f64 v[11:12], v[7:8], s[6:7], s[2:3]
s_mov_b32 s2, 0xa17f65f6
s_mov_b32 s6, 0x19e83e5c
s_mov_b32 s3, 0xbe927e4f
s_mov_b32 s7, 0xbf2a01a0
v_mul_f64 v[19:20], v[2:3], -v[7:8]
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_fma_f64 v[9:10], v[7:8], v[9:10], s[8:9]
v_add_f64 v[15:16], -v[13:14], 1.0
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_fma_f64 v[11:12], v[7:8], v[11:12], s[2:3]
s_mov_b32 s2, 0x19f4ec90
s_mov_b32 s3, 0x3efa01a0
v_fma_f64 v[9:10], v[7:8], v[9:10], s[6:7]
s_mov_b32 s6, 0x11110bb3
s_mov_b32 s7, 0x3f811111
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f64 v[21:22], -v[15:16], 1.0
v_fma_f64 v[11:12], v[7:8], v[11:12], s[2:3]
s_mov_b32 s2, 0x16c16967
s_mov_b32 s3, 0xbf56c16c
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_fma_f64 v[9:10], v[7:8], v[9:10], s[6:7]
v_add_f64 v[13:14], v[21:22], -v[13:14]
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_fma_f64 v[11:12], v[7:8], v[11:12], s[2:3]
s_mov_b32 s3, 0x3fa55555
s_mov_b32 s2, 0x55555555
v_fma_f64 v[9:10], v[19:20], v[9:10], v[17:18]
v_mul_f64 v[17:18], v[7:8], v[7:8]
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_fma_f64 v[13:14], v[2:3], -v[4:5], v[13:14]
v_fma_f64 v[11:12], v[7:8], v[11:12], s[2:3]
s_mov_b32 s3, 0xbfc55555
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f64 v[4:5], v[7:8], v[9:10], -v[4:5]
v_fma_f64 v[7:8], v[17:18], v[11:12], v[13:14]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
v_fma_f64 v[4:5], v[19:20], s[2:3], v[4:5]
v_cmp_class_f64_e64 s2, v[0:1], 0x1f8
v_lshlrev_b32_e32 v0, 30, v6
s_lshr_b32 s3, s5, 31
s_add_i32 s3, s5, s3
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f64 v[7:8], v[15:16], v[7:8]
v_xor_b32_e32 v0, v0, v1
s_ashr_i32 s3, s3, 1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_and_b32_e32 v0, 0x80000000, v0
v_add_f64 v[2:3], v[2:3], -v[4:5]
v_and_b32_e32 v4, 1, v6
v_cmp_eq_u32_e32 vcc_lo, 0, v4
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_cndmask_b32 v1, v8, v3 :: v_dual_cndmask_b32 v2, v7, v2
v_xor_b32_e32 v1, v1, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cndmask_b32_e64 v0, 0, v2, s2
v_cndmask_b32_e64 v1, 0x7ff80000, v1, s2
s_lshr_b32 s2, s4, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s2, s4, s2
s_ashr_i32 s2, s2, 1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_cvt_f32_f64_e32 v0, v[0:1]
v_mov_b32_e32 v1, 0
s_mul_i32 s2, s2, s5
s_add_i32 s2, s2, s3
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_ashr_i32 s3, s2, 31
s_lshl_b64 s[2:3], s[2:3], 2
s_waitcnt lgkmcnt(0)
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
global_store_b32 v1, v0, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10update_srciiiPf
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 32
.amdhsa_next_free_sgpr 10
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z10update_srciiiPf, .Lfunc_end1-_Z10update_srciiiPf
; -- End function
.section .AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1608
; NumSgprs: 12
; NumVgprs: 32
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 1
; VGPRBlocks: 3
; NumSGPRsForWavesPerEU: 12
; NumVGPRsForWavesPerEU: 32
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object ; @__hip_cuid_
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0 ; 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6updateiiPfS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z6updateiiPfS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 10
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .offset: 8
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10update_srciiiPf
.private_segment_fixed_size: 0
.sgpr_count: 12
.sgpr_spill_count: 0
.symbol: _Z10update_srciiiPf.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 32
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
```
| 5,997 | 11,765 |
205 |
Convert the following CUDA host assembly code to AMD host assembly:
```cudaasm
.file "tmpxft_000ebea5_00000000-6_update.cudafe1.cpp"
.text
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z29__device_stub__Z6updateiiPfS_iiPfS_
.type _Z29__device_stub__Z6updateiiPfS_iiPfS_, @function
_Z29__device_stub__Z6updateiiPfS_iiPfS_:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 28(%rsp)
movl %esi, 24(%rsp)
movq %rdx, 16(%rsp)
movq %rcx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 24(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z6updateiiPfS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z29__device_stub__Z6updateiiPfS_iiPfS_, .-_Z29__device_stub__Z6updateiiPfS_iiPfS_
.globl _Z6updateiiPfS_
.type _Z6updateiiPfS_, @function
_Z6updateiiPfS_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z6updateiiPfS_iiPfS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z6updateiiPfS_, .-_Z6updateiiPfS_
.globl _Z33__device_stub__Z10update_srciiiPfiiiPf
.type _Z33__device_stub__Z10update_srciiiPfiiiPf, @function
_Z33__device_stub__Z10update_srciiiPfiiiPf:
.LFB2053:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 28(%rsp)
movl %esi, 24(%rsp)
movl %edx, 20(%rsp)
movq %rcx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 24(%rsp), %rax
movq %rax, 104(%rsp)
leaq 20(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z10update_srciiiPf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2053:
.size _Z33__device_stub__Z10update_srciiiPfiiiPf, .-_Z33__device_stub__Z10update_srciiiPfiiiPf
.globl _Z10update_srciiiPf
.type _Z10update_srciiiPf, @function
_Z10update_srciiiPf:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z10update_srciiiPfiiiPf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _Z10update_srciiiPf, .-_Z10update_srciiiPf
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z10update_srciiiPf"
.LC1:
.string "_Z6updateiiPfS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2056:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z10update_srciiiPf(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z6updateiiPfS_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2056:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
```
|
```amdasm
.text
.file "update.hip"
.globl _Z21__device_stub__updateiiPfS_ # -- Begin function _Z21__device_stub__updateiiPfS_
.type _Z21__device_stub__updateiiPfS_,@function
_Z21__device_stub__updateiiPfS_: # @_Z21__device_stub__updateiiPfS_
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $112, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 12(%rsp), %rax
movl %edi, (%rax)
leaq 8(%rsp), %rdi
movl %esi, (%rdi)
leaq 40(%rsp), %rsi
movq %rdx, (%rsi)
leaq 32(%rsp), %rdx
movq %rcx, (%rdx)
leaq 80(%rsp), %rbx
movq %rax, (%rbx)
movq %rdi, 8(%rbx)
movq %rsi, 16(%rbx)
movq %rdx, 24(%rbx)
leaq 64(%rsp), %r14
leaq 48(%rsp), %r15
leaq 24(%rsp), %r12
leaq 16(%rsp), %r13
movq %r14, %rdi
movq %r15, %rsi
movq %r12, %rdx
movq %r13, %rcx
callq __hipPopCallConfiguration
movq (%r14), %rsi
movl 8(%r14), %edx
movq (%r15), %rcx
movl 8(%r15), %r8d
movl $_Z6updateiiPfS_, %edi
movq %rbx, %r9
pushq (%r13)
.cfi_adjust_cfa_offset 8
pushq (%r12)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $128, %rsp
.cfi_adjust_cfa_offset -128
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z21__device_stub__updateiiPfS_, .Lfunc_end0-_Z21__device_stub__updateiiPfS_
.cfi_endproc
# -- End function
.globl _Z25__device_stub__update_srciiiPf # -- Begin function _Z25__device_stub__update_srciiiPf
.type _Z25__device_stub__update_srciiiPf,@function
_Z25__device_stub__update_srciiiPf: # @_Z25__device_stub__update_srciiiPf
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $112, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 20(%rsp), %rax
movl %edi, (%rax)
leaq 16(%rsp), %rdi
movl %esi, (%rdi)
leaq 12(%rsp), %rsi
movl %edx, (%rsi)
leaq 40(%rsp), %rdx
movq %rcx, (%rdx)
leaq 80(%rsp), %rbx
movq %rax, (%rbx)
movq %rdi, 8(%rbx)
movq %rsi, 16(%rbx)
movq %rdx, 24(%rbx)
leaq 64(%rsp), %r14
leaq 48(%rsp), %r15
leaq 32(%rsp), %r12
leaq 24(%rsp), %r13
movq %r14, %rdi
movq %r15, %rsi
movq %r12, %rdx
movq %r13, %rcx
callq __hipPopCallConfiguration
movq (%r14), %rsi
movl 8(%r14), %edx
movq (%r15), %rcx
movl 8(%r15), %r8d
movl $_Z10update_srciiiPf, %edi
movq %rbx, %r9
pushq (%r13)
.cfi_adjust_cfa_offset 8
pushq (%r12)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $128, %rsp
.cfi_adjust_cfa_offset -128
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z25__device_stub__update_srciiiPf, .Lfunc_end1-_Z25__device_stub__update_srciiiPf
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
movq __hip_gpubin_handle(%rip), %rbx
testq %rbx, %rbx
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, %rbx
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6updateiiPfS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10update_srciiiPf, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6updateiiPfS_,@object # @_Z6updateiiPfS_
.section .rodata,"a",@progbits
.globl _Z6updateiiPfS_
.p2align 3, 0x0
_Z6updateiiPfS_:
.quad _Z21__device_stub__updateiiPfS_
.size _Z6updateiiPfS_, 8
.type _Z10update_srciiiPf,@object # @_Z10update_srciiiPf
.globl _Z10update_srciiiPf
.p2align 3, 0x0
_Z10update_srciiiPf:
.quad _Z25__device_stub__update_srciiiPf
.size _Z10update_srciiiPf, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z6updateiiPfS_"
.size .L__unnamed_1, 16
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z10update_srciiiPf"
.size .L__unnamed_2, 20
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__updateiiPfS_
.addrsig_sym _Z25__device_stub__update_srciiiPf
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6updateiiPfS_
.addrsig_sym _Z10update_srciiiPf
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
```
| 2,973 | 3,234 |
206 |
Convert the following CUDA device assembly code to AMD device assembly:
```cudaasm
code for sm_80
Function : _Z13subVectorsGpuPfS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
MOV R1, c[0x0][0x28] ;
S2R R3, SR_CTAID.X ;
S2R R0, SR_TID.X ;
IMAD R3, R3, c[0x0][0x0], R0 ;
ISETP.GE.AND P0, PT, R3, c[0x0][0x178], PT ;
@P0 EXIT ;
MOV R0, c[0x0][0x0] ;
ULDC.64 UR4, c[0x0][0x118] ;
BSSY B0, 0x340 ;
IMAD R0, R0, c[0x0][0xc], RZ ;
I2F.U32.RP R6, R0 ;
IADD3 R9, RZ, -R0, RZ ;
IADD3 R2, R0.reuse, R3, RZ ;
ISETP.NE.U32.AND P2, PT, R0, RZ, PT ;
LOP3.LUT R7, RZ, R2, RZ, 0x33, !PT ;
IADD3 R7, R7, c[0x0][0x178], R0 ;
MUFU.RCP R6, R6 ;
IADD3 R4, R6, 0xffffffe, RZ ;
F2I.FTZ.U32.TRUNC.NTZ R5, R4 ;
HFMA2.MMA R4, -RZ, RZ, 0, 0 ;
IMAD R9, R9, R5, RZ ;
IMAD.HI.U32 R2, R5, R9, R4 ;
IMAD.HI.U32 R2, R2, R7, RZ ;
IADD3 R4, -R2, RZ, RZ ;
IMAD R7, R0, R4, R7 ;
ISETP.GE.U32.AND P0, PT, R7, R0, PT ;
@P0 IADD3 R7, -R0, R7, RZ ;
@P0 IADD3 R2, R2, 0x1, RZ ;
ISETP.GE.U32.AND P1, PT, R7, R0, PT ;
@P1 IADD3 R2, R2, 0x1, RZ ;
@!P2 LOP3.LUT R2, RZ, R0, RZ, 0x33, !PT ;
IADD3 R4, R2.reuse, 0x1, RZ ;
ISETP.GE.U32.AND P1, PT, R2, 0x3, PT ;
LOP3.LUT P0, R4, R4, 0x3, RZ, 0xc0, !PT ;
@!P0 BRA 0x330 ;
MOV R8, 0x4 ;
MOV R2, R4 ;
IMAD.WIDE R4, R3, R8, c[0x0][0x160] ;
IMAD.WIDE R6, R3, R8, c[0x0][0x170] ;
IMAD.WIDE R8, R3, R8, c[0x0][0x168] ;
LDG.E R10, [R6.64] ;
LDG.E R11, [R8.64] ;
IADD3 R2, R2, -0x1, RZ ;
IADD3 R3, R0, R3, RZ ;
ISETP.NE.AND P0, PT, R2, RZ, PT ;
IMAD.WIDE R6, R0, 0x4, R6 ;
IMAD.WIDE R8, R0, 0x4, R8 ;
FADD R11, -R10, R11 ;
STG.E [R4.64], R11 ;
IMAD.WIDE R4, R0, 0x4, R4 ;
@P0 BRA 0x280 ;
BSYNC B0 ;
@!P1 EXIT ;
HFMA2.MMA R8, -RZ, RZ, 0, 2.384185791015625e-07 ;
IMAD.WIDE R6, R3, R8, c[0x0][0x170] ;
IMAD.WIDE R4, R3.reuse, R8.reuse, c[0x0][0x168] ;
LDG.E R2, [R6.64] ;
LDG.E R11, [R4.64] ;
IMAD.WIDE R8, R3, R8, c[0x0][0x160] ;
IMAD.WIDE R12, R0, 0x4, R6 ;
FADD R19, -R2, R11 ;
IMAD.WIDE R10, R0, 0x4, R4 ;
STG.E [R8.64], R19 ;
LDG.E R2, [R12.64] ;
LDG.E R17, [R10.64] ;
IMAD.WIDE R14, R0, 0x4, R8 ;
IMAD.WIDE R6, R0, 0x4, R12 ;
IMAD.WIDE R4, R0, 0x4, R10 ;
FADD R21, -R2, R17 ;
STG.E [R14.64], R21 ;
LDG.E R2, [R6.64] ;
LDG.E R23, [R4.64] ;
IMAD.WIDE R16, R0, 0x4, R14 ;
IMAD.WIDE R12, R0, 0x4, R6 ;
IMAD.WIDE R8, R0, 0x4, R4 ;
FADD R23, -R2, R23 ;
STG.E [R16.64], R23 ;
LDG.E R12, [R12.64] ;
LDG.E R9, [R8.64] ;
IMAD.WIDE R10, R0.reuse, 0x4, R16 ;
IADD3 R3, R0, R3, R0 ;
IADD3 R3, R0, R3, R0 ;
ISETP.GE.AND P0, PT, R3, c[0x0][0x178], PT ;
FADD R15, -R12, R9 ;
STG.E [R10.64], R15 ;
@!P0 BRA 0x350 ;
EXIT ;
BRA 0x570;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
Function : _Z13addVectorsGpuPfS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
MOV R1, c[0x0][0x28] ;
S2R R3, SR_CTAID.X ;
S2R R0, SR_TID.X ;
IMAD R3, R3, c[0x0][0x0], R0 ;
ISETP.GE.AND P0, PT, R3, c[0x0][0x178], PT ;
@P0 EXIT ;
MOV R0, c[0x0][0x0] ;
ULDC.64 UR4, c[0x0][0x118] ;
BSSY B0, 0x340 ;
IMAD R0, R0, c[0x0][0xc], RZ ;
I2F.U32.RP R6, R0 ;
IADD3 R9, RZ, -R0, RZ ;
IADD3 R2, R0.reuse, R3, RZ ;
ISETP.NE.U32.AND P2, PT, R0, RZ, PT ;
LOP3.LUT R7, RZ, R2, RZ, 0x33, !PT ;
IADD3 R7, R7, c[0x0][0x178], R0 ;
MUFU.RCP R6, R6 ;
IADD3 R4, R6, 0xffffffe, RZ ;
F2I.FTZ.U32.TRUNC.NTZ R5, R4 ;
HFMA2.MMA R4, -RZ, RZ, 0, 0 ;
IMAD R9, R9, R5, RZ ;
IMAD.HI.U32 R2, R5, R9, R4 ;
IMAD.HI.U32 R2, R2, R7, RZ ;
IADD3 R4, -R2, RZ, RZ ;
IMAD R7, R0, R4, R7 ;
ISETP.GE.U32.AND P0, PT, R7, R0, PT ;
@P0 IADD3 R7, -R0, R7, RZ ;
@P0 IADD3 R2, R2, 0x1, RZ ;
ISETP.GE.U32.AND P1, PT, R7, R0, PT ;
@P1 IADD3 R2, R2, 0x1, RZ ;
@!P2 LOP3.LUT R2, RZ, R0, RZ, 0x33, !PT ;
IADD3 R4, R2.reuse, 0x1, RZ ;
ISETP.GE.U32.AND P1, PT, R2, 0x3, PT ;
LOP3.LUT P0, R4, R4, 0x3, RZ, 0xc0, !PT ;
@!P0 BRA 0x330 ;
MOV R8, 0x4 ;
MOV R2, R4 ;
IMAD.WIDE R4, R3, R8, c[0x0][0x160] ;
IMAD.WIDE R6, R3, R8, c[0x0][0x170] ;
IMAD.WIDE R8, R3, R8, c[0x0][0x168] ;
LDG.E R10, [R6.64] ;
LDG.E R11, [R8.64] ;
IADD3 R2, R2, -0x1, RZ ;
IADD3 R3, R0, R3, RZ ;
ISETP.NE.AND P0, PT, R2, RZ, PT ;
IMAD.WIDE R6, R0, 0x4, R6 ;
IMAD.WIDE R8, R0, 0x4, R8 ;
FADD R11, R10, R11 ;
STG.E [R4.64], R11 ;
IMAD.WIDE R4, R0, 0x4, R4 ;
@P0 BRA 0x280 ;
BSYNC B0 ;
@!P1 EXIT ;
HFMA2.MMA R8, -RZ, RZ, 0, 2.384185791015625e-07 ;
IMAD.WIDE R6, R3, R8, c[0x0][0x170] ;
IMAD.WIDE R4, R3.reuse, R8.reuse, c[0x0][0x168] ;
LDG.E R2, [R6.64] ;
LDG.E R11, [R4.64] ;
IMAD.WIDE R8, R3, R8, c[0x0][0x160] ;
IMAD.WIDE R12, R0, 0x4, R6 ;
FADD R19, R2, R11 ;
IMAD.WIDE R10, R0, 0x4, R4 ;
STG.E [R8.64], R19 ;
LDG.E R2, [R12.64] ;
LDG.E R17, [R10.64] ;
IMAD.WIDE R14, R0, 0x4, R8 ;
IMAD.WIDE R6, R0, 0x4, R12 ;
IMAD.WIDE R4, R0, 0x4, R10 ;
FADD R21, R2, R17 ;
STG.E [R14.64], R21 ;
LDG.E R2, [R6.64] ;
LDG.E R23, [R4.64] ;
IMAD.WIDE R16, R0, 0x4, R14 ;
IMAD.WIDE R12, R0, 0x4, R6 ;
IMAD.WIDE R8, R0, 0x4, R4 ;
FADD R23, R2, R23 ;
STG.E [R16.64], R23 ;
LDG.E R12, [R12.64] ;
LDG.E R9, [R8.64] ;
IMAD.WIDE R10, R0.reuse, 0x4, R16 ;
IADD3 R3, R0, R3, R0 ;
IADD3 R3, R0, R3, R0 ;
ISETP.GE.AND P0, PT, R3, c[0x0][0x178], PT ;
FADD R15, R12, R9 ;
STG.E [R10.64], R15 ;
@!P0 BRA 0x350 ;
EXIT ;
BRA 0x570;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
Function : _Z13dotVectorsGpufPfS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
MOV R1, c[0x0][0x28] ;
EXIT ;
BRA 0x20;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
```
|
```amdasm
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z13dotVectorsGpufPfS_i ; -- Begin function _Z13dotVectorsGpufPfS_i
.globl _Z13dotVectorsGpufPfS_i
.p2align 8
.type _Z13dotVectorsGpufPfS_i,@function
_Z13dotVectorsGpufPfS_i: ; @_Z13dotVectorsGpufPfS_i
; %bb.0:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13dotVectorsGpufPfS_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 28
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 1
.amdhsa_next_free_sgpr 1
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z13dotVectorsGpufPfS_i, .Lfunc_end0-_Z13dotVectorsGpufPfS_i
; -- End function
.section .AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 4
; NumSgprs: 0
; NumVgprs: 0
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 0
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 1
; NumVGPRsForWavesPerEU: 1
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
.text
.protected _Z13addVectorsGpuPfS_S_i ; -- Begin function _Z13addVectorsGpuPfS_S_i
.globl _Z13addVectorsGpuPfS_S_i
.p2align 8
.type _Z13addVectorsGpuPfS_S_i,@function
_Z13addVectorsGpuPfS_S_i: ; @_Z13addVectorsGpuPfS_S_i
; %bb.0:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x2c
s_load_b32 s12, s[0:1], 0x18
s_add_u32 s2, s0, 32
s_addc_u32 s3, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s8, s4, 0xffff
s_mov_b32 s4, exec_lo
v_mad_u64_u32 v[1:2], null, s15, s8, v[0:1]
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s12, v1
s_cbranch_execz .LBB1_3
; %bb.1: ; %.lr.ph.preheader
s_load_b32 s9, s[2:3], 0x0
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[2:3], s[0:1], 0x10
v_ashrrev_i32_e32 v2, 31, v1
s_mov_b32 s1, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_lshlrev_b64 v[2:3], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_mul_i32 s8, s9, s8
s_ashr_i32 s9, s8, 31
s_delay_alu instid0(SALU_CYCLE_1)
s_lshl_b64 s[10:11], s[8:9], 2
.LBB1_2: ; %.lr.ph
; =>This Inner Loop Header: Depth=1
s_delay_alu instid0(VALU_DEP_1)
v_add_co_u32 v4, vcc_lo, s6, v2
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v3, vcc_lo
v_add_co_u32 v6, vcc_lo, s2, v2
v_add_co_ci_u32_e32 v7, vcc_lo, s3, v3, vcc_lo
global_load_b32 v0, v[4:5], off
global_load_b32 v6, v[6:7], off
v_add_nc_u32_e32 v1, s8, v1
v_add_co_u32 v4, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v3, vcc_lo
v_add_co_u32 v2, vcc_lo, v2, s10
v_add_co_ci_u32_e32 v3, vcc_lo, s11, v3, vcc_lo
s_waitcnt vmcnt(0)
v_add_f32_e32 v0, v0, v6
v_cmp_le_i32_e64 s0, s12, v1
global_store_b32 v[4:5], v0, off
s_or_b32 s1, s0, s1
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s1
s_cbranch_execnz .LBB1_2
.LBB1_3: ; %Flow26
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13addVectorsGpuPfS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z13addVectorsGpuPfS_S_i, .Lfunc_end1-_Z13addVectorsGpuPfS_S_i
; -- End function
.section .AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 260
; NumSgprs: 18
; NumVgprs: 8
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 8
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
.text
.protected _Z13subVectorsGpuPfS_S_i ; -- Begin function _Z13subVectorsGpuPfS_S_i
.globl _Z13subVectorsGpuPfS_S_i
.p2align 8
.type _Z13subVectorsGpuPfS_S_i,@function
_Z13subVectorsGpuPfS_S_i: ; @_Z13subVectorsGpuPfS_S_i
; %bb.0:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x2c
s_load_b32 s12, s[0:1], 0x18
s_add_u32 s2, s0, 32
s_addc_u32 s3, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s8, s4, 0xffff
s_mov_b32 s4, exec_lo
v_mad_u64_u32 v[1:2], null, s15, s8, v[0:1]
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s12, v1
s_cbranch_execz .LBB2_3
; %bb.1: ; %.lr.ph.preheader
s_load_b32 s9, s[2:3], 0x0
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[2:3], s[0:1], 0x10
v_ashrrev_i32_e32 v2, 31, v1
s_mov_b32 s1, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_lshlrev_b64 v[2:3], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_mul_i32 s8, s9, s8
s_ashr_i32 s9, s8, 31
s_delay_alu instid0(SALU_CYCLE_1)
s_lshl_b64 s[10:11], s[8:9], 2
.LBB2_2: ; %.lr.ph
; =>This Inner Loop Header: Depth=1
s_delay_alu instid0(VALU_DEP_1)
v_add_co_u32 v4, vcc_lo, s6, v2
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v3, vcc_lo
v_add_co_u32 v6, vcc_lo, s2, v2
v_add_co_ci_u32_e32 v7, vcc_lo, s3, v3, vcc_lo
global_load_b32 v0, v[4:5], off
global_load_b32 v6, v[6:7], off
v_add_nc_u32_e32 v1, s8, v1
v_add_co_u32 v4, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v3, vcc_lo
v_add_co_u32 v2, vcc_lo, v2, s10
v_add_co_ci_u32_e32 v3, vcc_lo, s11, v3, vcc_lo
s_waitcnt vmcnt(0)
v_sub_f32_e32 v0, v0, v6
v_cmp_le_i32_e64 s0, s12, v1
global_store_b32 v[4:5], v0, off
s_or_b32 s1, s0, s1
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s1
s_cbranch_execnz .LBB2_2
.LBB2_3: ; %Flow26
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13subVectorsGpuPfS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end2:
.size _Z13subVectorsGpuPfS_S_i, .Lfunc_end2-_Z13subVectorsGpuPfS_S_i
; -- End function
.section .AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 260
; NumSgprs: 18
; NumVgprs: 8
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 8
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object ; @__hip_cuid_
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0 ; 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 28
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13dotVectorsGpufPfS_i
.private_segment_fixed_size: 0
.sgpr_count: 0
.sgpr_spill_count: 0
.symbol: _Z13dotVectorsGpufPfS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 0
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13addVectorsGpuPfS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z13addVectorsGpuPfS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13subVectorsGpuPfS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z13subVectorsGpuPfS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
```
| 3,333 | 6,878 |
207 |
Convert the following CUDA host assembly code to AMD host assembly:
```cudaasm
.file "tmpxft_0006be3e_00000000-6_pprjct.cudafe1.cpp"
.text
.globl _ZSt21ios_base_library_initv
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3678:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3678:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z7initVecPfi
.type _Z7initVecPfi, @function
_Z7initVecPfi:
.LFB3669:
.cfi_startproc
endbr64
testl %esi, %esi
jle .L8
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
movq %rdi, %rbx
movslq %esi, %rsi
leaq (%rdi,%rsi,4), %rbp
.L5:
call rand@PLT
movslq %eax, %rdx
imulq $1374389535, %rdx, %rdx
sarq $37, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
imull $100, %edx, %edx
subl %edx, %eax
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movss %xmm0, (%rbx)
addq $4, %rbx
cmpq %rbp, %rbx
jne .L5
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L8:
.cfi_restore 3
.cfi_restore 6
ret
.cfi_endproc
.LFE3669:
.size _Z7initVecPfi, .-_Z7initVecPfi
.globl _Z8initWithfPfi
.type _Z8initWithfPfi, @function
_Z8initWithfPfi:
.LFB3670:
.cfi_startproc
endbr64
testl %esi, %esi
jle .L11
movq %rdi, %rax
movslq %esi, %rsi
leaq (%rdi,%rsi,4), %rdx
.L13:
movss %xmm0, (%rax)
addq $4, %rax
cmpq %rdx, %rax
jne .L13
.L11:
ret
.cfi_endproc
.LFE3670:
.size _Z8initWithfPfi, .-_Z8initWithfPfi
.globl _Z13dotVectorsCPUfPfS_i
.type _Z13dotVectorsCPUfPfS_i, @function
_Z13dotVectorsCPUfPfS_i:
.LFB3671:
.cfi_startproc
endbr64
testl %edx, %edx
jle .L15
movl $0, %eax
.L17:
addl $1, %eax
cmpl %eax, %edx
jne .L17
.L15:
ret
.cfi_endproc
.LFE3671:
.size _Z13dotVectorsCPUfPfS_i, .-_Z13dotVectorsCPUfPfS_i
.globl _Z13addVectorsCPUPfS_S_i
.type _Z13addVectorsCPUPfS_S_i, @function
_Z13addVectorsCPUPfS_S_i:
.LFB3672:
.cfi_startproc
endbr64
testl %ecx, %ecx
jle .L19
movslq %ecx, %rcx
salq $2, %rcx
movl $0, %eax
.L21:
movss (%rsi,%rax), %xmm0
addss (%rdx,%rax), %xmm0
movss %xmm0, (%rdi,%rax)
addq $4, %rax
cmpq %rcx, %rax
jne .L21
.L19:
ret
.cfi_endproc
.LFE3672:
.size _Z13addVectorsCPUPfS_S_i, .-_Z13addVectorsCPUPfS_S_i
.globl _Z13subVectorsCPUPfS_S_i
.type _Z13subVectorsCPUPfS_S_i, @function
_Z13subVectorsCPUPfS_S_i:
.LFB3673:
.cfi_startproc
endbr64
testl %ecx, %ecx
jle .L23
movslq %ecx, %rcx
salq $2, %rcx
movl $0, %eax
.L25:
movss (%rsi,%rax), %xmm0
subss (%rdx,%rax), %xmm0
movss %xmm0, (%rdi,%rax)
addq $4, %rax
cmpq %rcx, %rax
jne .L25
.L23:
ret
.cfi_endproc
.LFE3673:
.size _Z13subVectorsCPUPfS_S_i, .-_Z13subVectorsCPUPfS_S_i
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "\nDo You want to improve your score? (y/n)"
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "\n"
.LC2:
.string " %c"
.LC3:
.string "\nWrong answer! Give y or n!"
.text
.globl _Z10ask_repeatv
.type _Z10ask_repeatv, @function
_Z10ask_repeatv:
.LFB3674:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $24, %rsp
.cfi_def_cfa_offset 64
movq %fs:40, %rax
movq %rax, 8(%rsp)
xorl %eax, %eax
leaq .LC0(%rip), %r12
leaq .LC1(%rip), %rbp
leaq .LC2(%rip), %rbx
leaq .LC3(%rip), %r13
jmp .L29
.L34:
movq %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
.L29:
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 7(%rsp), %rsi
movq %rbx, %rdi
movl $0, %eax
call __isoc23_scanf@PLT
movzbl 7(%rsp), %eax
andl $-33, %eax
cmpb $89, %al
je .L31
cmpb $78, %al
jne .L34
movl $0, %eax
jmp .L27
.L31:
movl $1, %eax
.L27:
movq 8(%rsp), %rdx
subq %fs:40, %rdx
jne .L35
addq $24, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L35:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3674:
.size _Z10ask_repeatv, .-_Z10ask_repeatv
.globl _Z37__device_stub__Z13dotVectorsGpufPfS_ifPfS_i
.type _Z37__device_stub__Z13dotVectorsGpufPfS_ifPfS_i, @function
_Z37__device_stub__Z13dotVectorsGpufPfS_ifPfS_i:
.LFB3700:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movss %xmm0, 28(%rsp)
movq %rdi, 16(%rsp)
movq %rsi, 8(%rsp)
movl %edx, 24(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 24(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L40
.L36:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L41
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L40:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z13dotVectorsGpufPfS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L36
.L41:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3700:
.size _Z37__device_stub__Z13dotVectorsGpufPfS_ifPfS_i, .-_Z37__device_stub__Z13dotVectorsGpufPfS_ifPfS_i
.globl _Z13dotVectorsGpufPfS_i
.type _Z13dotVectorsGpufPfS_i, @function
_Z13dotVectorsGpufPfS_i:
.LFB3701:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z37__device_stub__Z13dotVectorsGpufPfS_ifPfS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3701:
.size _Z13dotVectorsGpufPfS_i, .-_Z13dotVectorsGpufPfS_i
.globl _Z38__device_stub__Z13addVectorsGpuPfS_S_iPfS_S_i
.type _Z38__device_stub__Z13addVectorsGpuPfS_S_iPfS_S_i, @function
_Z38__device_stub__Z13addVectorsGpuPfS_S_iPfS_S_i:
.LFB3702:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L48
.L44:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L49
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L48:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z13addVectorsGpuPfS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L44
.L49:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3702:
.size _Z38__device_stub__Z13addVectorsGpuPfS_S_iPfS_S_i, .-_Z38__device_stub__Z13addVectorsGpuPfS_S_iPfS_S_i
.globl _Z13addVectorsGpuPfS_S_i
.type _Z13addVectorsGpuPfS_S_i, @function
_Z13addVectorsGpuPfS_S_i:
.LFB3703:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z38__device_stub__Z13addVectorsGpuPfS_S_iPfS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3703:
.size _Z13addVectorsGpuPfS_S_i, .-_Z13addVectorsGpuPfS_S_i
.globl _Z38__device_stub__Z13subVectorsGpuPfS_S_iPfS_S_i
.type _Z38__device_stub__Z13subVectorsGpuPfS_S_iPfS_S_i, @function
_Z38__device_stub__Z13subVectorsGpuPfS_S_iPfS_S_i:
.LFB3704:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L56
.L52:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L57
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L56:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z13subVectorsGpuPfS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L52
.L57:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3704:
.size _Z38__device_stub__Z13subVectorsGpuPfS_S_iPfS_S_i, .-_Z38__device_stub__Z13subVectorsGpuPfS_S_iPfS_S_i
.globl _Z13subVectorsGpuPfS_S_i
.type _Z13subVectorsGpuPfS_S_i, @function
_Z13subVectorsGpuPfS_S_i:
.LFB3705:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z38__device_stub__Z13subVectorsGpuPfS_S_iPfS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3705:
.size _Z13subVectorsGpuPfS_S_i, .-_Z13subVectorsGpuPfS_S_i
.section .rodata.str1.8
.align 8
.LC4:
.string "Give the length of vectors you want to work with:"
.section .rodata.str1.1
.LC5:
.string "%d"
.section .rodata.str1.8
.align 8
.LC6:
.string "Choose mathematical operations:\n"
.section .rodata.str1.1
.LC7:
.string "Type '*' for dotting vectors\n"
.LC8:
.string "Type '+' for adding vectors\n"
.section .rodata.str1.8
.align 8
.LC9:
.string "Type '-' for subtracting vectors\n"
.align 8
.LC11:
.string "\nTime elapsed dotting vectors on CPU is: %f"
.align 8
.LC13:
.string "\nTime elapsed on single-threaded vector dotting: %f \n"
.align 8
.LC14:
.string "\nTime elapsed adding vectors on CPU is: %f"
.align 8
.LC15:
.string "\nTime elapsed on single-threaded vector addition: %f \n"
.align 8
.LC16:
.string "\nTime elapsed subtracting vectors on CPU is: %f"
.align 8
.LC17:
.string "\nTime elapsed on single-threaded vector subtracting: %f \n"
.align 8
.LC18:
.string "Error! operator is not correct\n"
.section .rodata.str1.1
.LC19:
.string "Quiting..."
.section .rodata.str1.8
.align 8
.LC20:
.string "\nGive the size of block you want to use:"
.align 8
.LC21:
.string "Give the number of threads per block you want to use:"
.align 8
.LC22:
.string "\nTime elapsed on your size vectors dot product: %f\n"
.align 8
.LC23:
.string "\nTime elapsed on your size vectors addition: %f\n"
.align 8
.LC24:
.string "\nTime elapsed on your size vectors subtraction: %f\n"
.section .rodata.str1.1
.LC25:
.string "Error!\n"
.text
.globl main
.type main, @function
main:
.LFB3675:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $120, %rsp
.cfi_def_cfa_offset 160
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 4(%rsp), %rdi
call cudaGetDevice@PLT
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 12(%rsp), %rsi
leaq .LC5(%rip), %rdi
movl $0, %eax
call __isoc23_scanf@PLT
movslq 12(%rsp), %rbx
salq $2, %rbx
leaq 40(%rsp), %rdi
movl $1, %edx
movq %rbx, %rsi
call cudaMallocManaged@PLT
leaq 48(%rsp), %rdi
movl $1, %edx
movq %rbx, %rsi
call cudaMallocManaged@PLT
movl $0, %ecx
movl $-1, %edx
movq %rbx, %rsi
movq 40(%rsp), %rdi
call cudaMemPrefetchAsync@PLT
movl $0, %ecx
movl $-1, %edx
movq %rbx, %rsi
movq 48(%rsp), %rdi
call cudaMemPrefetchAsync@PLT
movl 12(%rsp), %esi
movq 40(%rsp), %rdi
call _Z7initVecPfi
movl 12(%rsp), %esi
movq 48(%rsp), %rdi
call _Z7initVecPfi
movl $0, %ecx
movl 4(%rsp), %edx
movq %rbx, %rsi
movq 40(%rsp), %rdi
call cudaMemPrefetchAsync@PLT
movl $0, %ecx
movl 4(%rsp), %edx
movq %rbx, %rsi
movq 48(%rsp), %rdi
call cudaMemPrefetchAsync@PLT
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 3(%rsp), %rsi
leaq .LC2(%rip), %rdi
movl $0, %eax
call __isoc23_scanf@PLT
movzbl 3(%rsp), %eax
cmpb $43, %al
je .L61
cmpb $45, %al
je .L62
cmpb $42, %al
jne .L63
call clock@PLT
movq %rax, %rbx
call clock@PLT
subq %rbx, %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
divsd .LC10(%rip), %xmm0
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
leaq 24(%rsp), %rdi
call cudaEventCreate@PLT
leaq 32(%rsp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq 24(%rsp), %rdi
call cudaEventRecord@PLT
movl $1, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 92(%rsp), %rdx
movl $1, %ecx
movq 80(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L80
.L64:
call cudaDeviceSynchronize@PLT
movl $0, %esi
movq 32(%rsp), %rdi
call cudaEventRecord@PLT
movq 32(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 8(%rsp), %rdi
movq 32(%rsp), %rdx
movq 24(%rsp), %rsi
call cudaEventElapsedTime@PLT
pxor %xmm0, %xmm0
cvtss2sd 8(%rsp), %xmm0
leaq .LC13(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
.L65:
leaq .LC20(%rip), %r13
leaq 16(%rsp), %r12
leaq .LC5(%rip), %rbx
leaq .LC21(%rip), %rbp
jmp .L67
.L80:
movl 12(%rsp), %edx
movq 48(%rsp), %rsi
movq 40(%rsp), %rdi
pxor %xmm0, %xmm0
call _Z37__device_stub__Z13dotVectorsGpufPfS_ifPfS_i
jmp .L64
.L61:
leaq 56(%rsp), %rdi
movl $1, %edx
movq %rbx, %rsi
call cudaMallocManaged@PLT
movl $0, %ecx
movl $-1, %edx
movq %rbx, %rsi
movq 56(%rsp), %rdi
call cudaMemPrefetchAsync@PLT
movl 12(%rsp), %esi
movq 56(%rsp), %rdi
pxor %xmm0, %xmm0
call _Z8initWithfPfi
movl $0, %ecx
movl 4(%rsp), %edx
movq %rbx, %rsi
movq 56(%rsp), %rdi
call cudaMemPrefetchAsync@PLT
call clock@PLT
movq %rax, %rbx
movl 12(%rsp), %ecx
movq 48(%rsp), %rdx
movq 40(%rsp), %rsi
movq 56(%rsp), %rdi
call _Z13addVectorsCPUPfS_S_i
call clock@PLT
subq %rbx, %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
divsd .LC10(%rip), %xmm0
leaq .LC14(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
leaq 24(%rsp), %rdi
call cudaEventCreate@PLT
leaq 32(%rsp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq 24(%rsp), %rdi
call cudaEventRecord@PLT
movl 12(%rsp), %esi
movq 56(%rsp), %rdi
pxor %xmm0, %xmm0
call _Z8initWithfPfi
movl $1, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 92(%rsp), %rdx
movl $1, %ecx
movq 80(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L81
.L66:
call cudaDeviceSynchronize@PLT
movl $0, %esi
movq 32(%rsp), %rdi
call cudaEventRecord@PLT
movq 32(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 8(%rsp), %rdi
movq 32(%rsp), %rdx
movq 24(%rsp), %rsi
call cudaEventElapsedTime@PLT
pxor %xmm0, %xmm0
cvtss2sd 8(%rsp), %xmm0
leaq .LC15(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
jmp .L65
.L81:
movl 12(%rsp), %ecx
movq 48(%rsp), %rdx
movq 40(%rsp), %rsi
movq 56(%rsp), %rdi
call _Z38__device_stub__Z13addVectorsGpuPfS_S_iPfS_S_i
jmp .L66
.L62:
leaq 56(%rsp), %rdi
movl $1, %edx
movq %rbx, %rsi
call cudaMallocManaged@PLT
movl $0, %ecx
movl $-1, %edx
movq %rbx, %rsi
movq 56(%rsp), %rdi
call cudaMemPrefetchAsync@PLT
movl 12(%rsp), %esi
movq 56(%rsp), %rdi
pxor %xmm0, %xmm0
call _Z8initWithfPfi
movl $0, %ecx
movl 4(%rsp), %edx
movq %rbx, %rsi
movq 56(%rsp), %rdi
call cudaMemPrefetchAsync@PLT
call clock@PLT
movq %rax, %rbx
movl 12(%rsp), %ecx
movq 48(%rsp), %rdx
movq 40(%rsp), %rsi
movq 56(%rsp), %rdi
call _Z13subVectorsCPUPfS_S_i
call clock@PLT
subq %rbx, %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
divsd .LC10(%rip), %xmm0
leaq .LC16(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
leaq 24(%rsp), %rdi
call cudaEventCreate@PLT
leaq 32(%rsp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq 24(%rsp), %rdi
call cudaEventRecord@PLT
movl 12(%rsp), %esi
movq 56(%rsp), %rdi
pxor %xmm0, %xmm0
call _Z8initWithfPfi
movl $1, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 92(%rsp), %rdx
movl $1, %ecx
movq 80(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L82
.L68:
call cudaDeviceSynchronize@PLT
movl $0, %esi
movq 32(%rsp), %rdi
call cudaEventRecord@PLT
movq 32(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 8(%rsp), %rdi
movq 32(%rsp), %rdx
movq 24(%rsp), %rsi
call cudaEventElapsedTime@PLT
pxor %xmm0, %xmm0
cvtss2sd 8(%rsp), %xmm0
leaq .LC17(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
jmp .L65
.L82:
movl 12(%rsp), %ecx
movq 48(%rsp), %rdx
movq 40(%rsp), %rsi
movq 56(%rsp), %rdi
call _Z38__device_stub__Z13subVectorsGpuPfS_S_iPfS_S_i
jmp .L68
.L63:
leaq .LC18(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC19(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L69
.L73:
movl $0, %esi
movq 72(%rsp), %rdi
call cudaEventRecord@PLT
movq 72(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 92(%rsp), %rdi
movq 72(%rsp), %rdx
movq 64(%rsp), %rsi
call cudaEventElapsedTime@PLT
pxor %xmm0, %xmm0
cvtss2sd 92(%rsp), %xmm0
leaq .LC22(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
call cudaDeviceSynchronize@PLT
call _Z10ask_repeatv
.L74:
testb %al, %al
je .L83
.L67:
movq %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %r12, %rsi
movq %rbx, %rdi
movl $0, %eax
call __isoc23_scanf@PLT
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 20(%rsp), %rsi
movq %rbx, %rdi
movl $0, %eax
call __isoc23_scanf@PLT
movzbl 3(%rsp), %eax
cmpb $43, %al
je .L70
cmpb $45, %al
je .L71
cmpb $42, %al
jne .L72
leaq 64(%rsp), %rdi
call cudaEventCreate@PLT
leaq 72(%rsp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq 64(%rsp), %rdi
call cudaEventRecord@PLT
movl 20(%rsp), %eax
movl %eax, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
movl 16(%rsp), %eax
movl %eax, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 92(%rsp), %rdx
movl $1, %ecx
movq 80(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L73
movl 12(%rsp), %edx
movq 48(%rsp), %rsi
movq 40(%rsp), %rdi
pxor %xmm0, %xmm0
call _Z37__device_stub__Z13dotVectorsGpufPfS_ifPfS_i
jmp .L73
.L70:
leaq 64(%rsp), %rdi
call cudaEventCreate@PLT
leaq 72(%rsp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq 64(%rsp), %rdi
call cudaEventRecord@PLT
movl 12(%rsp), %esi
movq 56(%rsp), %rdi
pxor %xmm0, %xmm0
call _Z8initWithfPfi
movl 20(%rsp), %eax
movl %eax, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
movl 16(%rsp), %eax
movl %eax, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 92(%rsp), %rdx
movl $1, %ecx
movq 80(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L84
.L75:
movl $0, %esi
movq 72(%rsp), %rdi
call cudaEventRecord@PLT
movq 72(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 92(%rsp), %rdi
movq 72(%rsp), %rdx
movq 64(%rsp), %rsi
call cudaEventElapsedTime@PLT
pxor %xmm0, %xmm0
cvtss2sd 92(%rsp), %xmm0
leaq .LC23(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
call cudaDeviceSynchronize@PLT
call _Z10ask_repeatv
jmp .L74
.L84:
movl 12(%rsp), %ecx
movq 48(%rsp), %rdx
movq 40(%rsp), %rsi
movq 56(%rsp), %rdi
call _Z38__device_stub__Z13addVectorsGpuPfS_S_iPfS_S_i
jmp .L75
.L71:
leaq 64(%rsp), %rdi
call cudaEventCreate@PLT
leaq 72(%rsp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq 64(%rsp), %rdi
call cudaEventRecord@PLT
movl 12(%rsp), %esi
movq 56(%rsp), %rdi
pxor %xmm0, %xmm0
call _Z8initWithfPfi
movl 20(%rsp), %eax
movl %eax, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
movl 16(%rsp), %eax
movl %eax, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 92(%rsp), %rdx
movl $1, %ecx
movq 80(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L85
.L76:
movl $0, %esi
movq 72(%rsp), %rdi
call cudaEventRecord@PLT
movq 72(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 92(%rsp), %rdi
movq 72(%rsp), %rdx
movq 64(%rsp), %rsi
call cudaEventElapsedTime@PLT
pxor %xmm0, %xmm0
cvtss2sd 92(%rsp), %xmm0
leaq .LC24(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
call cudaDeviceSynchronize@PLT
call _Z10ask_repeatv
jmp .L74
.L85:
movl 12(%rsp), %ecx
movq 48(%rsp), %rdx
movq 40(%rsp), %rsi
movq 56(%rsp), %rdi
call _Z38__device_stub__Z13subVectorsGpuPfS_S_iPfS_S_i
jmp .L76
.L72:
leaq .LC25(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC19(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
.L69:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L86
movl $0, %eax
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L83:
.cfi_restore_state
leaq .LC19(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
jmp .L69
.L86:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3675:
.size main, .-main
.section .rodata.str1.1
.LC26:
.string "_Z13subVectorsGpuPfS_S_i"
.LC27:
.string "_Z13addVectorsGpuPfS_S_i"
.LC28:
.string "_Z13dotVectorsGpufPfS_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3707:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC26(%rip), %rdx
movq %rdx, %rcx
leaq _Z13subVectorsGpuPfS_S_i(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC27(%rip), %rdx
movq %rdx, %rcx
leaq _Z13addVectorsGpuPfS_S_i(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC28(%rip), %rdx
movq %rdx, %rcx
leaq _Z13dotVectorsGpufPfS_i(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3707:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC10:
.long 0
.long 1093567616
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
```
|
```amdasm
.text
.file "pprjct.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z7initVecPfi # -- Begin function _Z7initVecPfi
.type _Z7initVecPfi,@function
_Z7initVecPfi: # @_Z7initVecPfi
.cfi_startproc
# %bb.0:
testl %esi, %esi
jle .LBB0_4
# %bb.1: # %.lr.ph.preheader
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rdi, %rbx
movl %esi, %r14d
xorl %r15d, %r15d
.LBB0_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
callq rand
cltq
imulq $1374389535, %rax, %rcx # imm = 0x51EB851F
movq %rcx, %rdx
shrq $63, %rdx
sarq $37, %rcx
addl %edx, %ecx
imull $100, %ecx, %ecx
subl %ecx, %eax
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movss %xmm0, (%rbx,%r15,4)
incq %r15
cmpq %r15, %r14
jne .LBB0_2
# %bb.3:
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r14
.cfi_restore %r15
.LBB0_4: # %._crit_edge
retq
.Lfunc_end0:
.size _Z7initVecPfi, .Lfunc_end0-_Z7initVecPfi
.cfi_endproc
# -- End function
.globl _Z8initWithfPfi # -- Begin function _Z8initWithfPfi
.type _Z8initWithfPfi,@function
_Z8initWithfPfi: # @_Z8initWithfPfi
.cfi_startproc
# %bb.0:
testl %esi, %esi
jle .LBB1_3
# %bb.1: # %.lr.ph.preheader
movl %esi, %eax
xorl %ecx, %ecx
.LBB1_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movss %xmm0, (%rdi,%rcx,4)
incq %rcx
cmpq %rcx, %rax
jne .LBB1_2
.LBB1_3: # %._crit_edge
retq
.Lfunc_end1:
.size _Z8initWithfPfi, .Lfunc_end1-_Z8initWithfPfi
.cfi_endproc
# -- End function
.globl _Z13dotVectorsCPUfPfS_i # -- Begin function _Z13dotVectorsCPUfPfS_i
.type _Z13dotVectorsCPUfPfS_i,@function
_Z13dotVectorsCPUfPfS_i: # @_Z13dotVectorsCPUfPfS_i
.cfi_startproc
# %bb.0:
retq
.Lfunc_end2:
.size _Z13dotVectorsCPUfPfS_i, .Lfunc_end2-_Z13dotVectorsCPUfPfS_i
.cfi_endproc
# -- End function
.globl _Z28__device_stub__dotVectorsGpufPfS_i # -- Begin function _Z28__device_stub__dotVectorsGpufPfS_i
.type _Z28__device_stub__dotVectorsGpufPfS_i,@function
_Z28__device_stub__dotVectorsGpufPfS_i: # @_Z28__device_stub__dotVectorsGpufPfS_i
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $112, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 12(%rsp), %rax
movss %xmm0, (%rax)
leaq 40(%rsp), %rcx
movq %rdi, (%rcx)
leaq 32(%rsp), %rdi
movq %rsi, (%rdi)
leaq 8(%rsp), %rsi
movl %edx, (%rsi)
leaq 80(%rsp), %rbx
movq %rax, (%rbx)
movq %rcx, 8(%rbx)
movq %rdi, 16(%rbx)
movq %rsi, 24(%rbx)
leaq 64(%rsp), %r14
leaq 48(%rsp), %r15
leaq 24(%rsp), %r12
leaq 16(%rsp), %r13
movq %r14, %rdi
movq %r15, %rsi
movq %r12, %rdx
movq %r13, %rcx
callq __hipPopCallConfiguration
movq (%r14), %rsi
movl 8(%r14), %edx
movq (%r15), %rcx
movl 8(%r15), %r8d
movl $_Z13dotVectorsGpufPfS_i, %edi
movq %rbx, %r9
pushq (%r13)
.cfi_adjust_cfa_offset 8
pushq (%r12)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $128, %rsp
.cfi_adjust_cfa_offset -128
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size _Z28__device_stub__dotVectorsGpufPfS_i, .Lfunc_end3-_Z28__device_stub__dotVectorsGpufPfS_i
.cfi_endproc
# -- End function
.globl _Z13addVectorsCPUPfS_S_i # -- Begin function _Z13addVectorsCPUPfS_S_i
.type _Z13addVectorsCPUPfS_S_i,@function
_Z13addVectorsCPUPfS_S_i: # @_Z13addVectorsCPUPfS_S_i
.cfi_startproc
# %bb.0:
testl %ecx, %ecx
jle .LBB4_3
# %bb.1: # %.lr.ph.preheader
movl %ecx, %eax
xorl %ecx, %ecx
.LBB4_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movss (%rsi,%rcx,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
addss (%rdx,%rcx,4), %xmm0
movss %xmm0, (%rdi,%rcx,4)
incq %rcx
cmpq %rcx, %rax
jne .LBB4_2
.LBB4_3: # %._crit_edge
retq
.Lfunc_end4:
.size _Z13addVectorsCPUPfS_S_i, .Lfunc_end4-_Z13addVectorsCPUPfS_S_i
.cfi_endproc
# -- End function
.globl _Z28__device_stub__addVectorsGpuPfS_S_i # -- Begin function _Z28__device_stub__addVectorsGpuPfS_S_i
.type _Z28__device_stub__addVectorsGpuPfS_S_i,@function
_Z28__device_stub__addVectorsGpuPfS_S_i: # @_Z28__device_stub__addVectorsGpuPfS_S_i
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $112, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 40(%rsp), %rax
movq %rdi, (%rax)
leaq 32(%rsp), %rdi
movq %rsi, (%rdi)
leaq 24(%rsp), %rsi
movq %rdx, (%rsi)
leaq 4(%rsp), %rdx
movl %ecx, (%rdx)
leaq 80(%rsp), %rbx
movq %rax, (%rbx)
movq %rdi, 8(%rbx)
movq %rsi, 16(%rbx)
movq %rdx, 24(%rbx)
leaq 64(%rsp), %r14
leaq 48(%rsp), %r15
leaq 16(%rsp), %r12
leaq 8(%rsp), %r13
movq %r14, %rdi
movq %r15, %rsi
movq %r12, %rdx
movq %r13, %rcx
callq __hipPopCallConfiguration
movq (%r14), %rsi
movl 8(%r14), %edx
movq (%r15), %rcx
movl 8(%r15), %r8d
movl $_Z13addVectorsGpuPfS_S_i, %edi
movq %rbx, %r9
pushq (%r13)
.cfi_adjust_cfa_offset 8
pushq (%r12)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $128, %rsp
.cfi_adjust_cfa_offset -128
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end5:
.size _Z28__device_stub__addVectorsGpuPfS_S_i, .Lfunc_end5-_Z28__device_stub__addVectorsGpuPfS_S_i
.cfi_endproc
# -- End function
.globl _Z13subVectorsCPUPfS_S_i # -- Begin function _Z13subVectorsCPUPfS_S_i
.type _Z13subVectorsCPUPfS_S_i,@function
_Z13subVectorsCPUPfS_S_i: # @_Z13subVectorsCPUPfS_S_i
.cfi_startproc
# %bb.0:
testl %ecx, %ecx
jle .LBB6_3
# %bb.1: # %.lr.ph.preheader
movl %ecx, %eax
xorl %ecx, %ecx
.LBB6_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movss (%rsi,%rcx,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
subss (%rdx,%rcx,4), %xmm0
movss %xmm0, (%rdi,%rcx,4)
incq %rcx
cmpq %rcx, %rax
jne .LBB6_2
.LBB6_3: # %._crit_edge
retq
.Lfunc_end6:
.size _Z13subVectorsCPUPfS_S_i, .Lfunc_end6-_Z13subVectorsCPUPfS_S_i
.cfi_endproc
# -- End function
.globl _Z28__device_stub__subVectorsGpuPfS_S_i # -- Begin function _Z28__device_stub__subVectorsGpuPfS_S_i
.type _Z28__device_stub__subVectorsGpuPfS_S_i,@function
_Z28__device_stub__subVectorsGpuPfS_S_i: # @_Z28__device_stub__subVectorsGpuPfS_S_i
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $112, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 40(%rsp), %rax
movq %rdi, (%rax)
leaq 32(%rsp), %rdi
movq %rsi, (%rdi)
leaq 24(%rsp), %rsi
movq %rdx, (%rsi)
leaq 4(%rsp), %rdx
movl %ecx, (%rdx)
leaq 80(%rsp), %rbx
movq %rax, (%rbx)
movq %rdi, 8(%rbx)
movq %rsi, 16(%rbx)
movq %rdx, 24(%rbx)
leaq 64(%rsp), %r14
leaq 48(%rsp), %r15
leaq 16(%rsp), %r12
leaq 8(%rsp), %r13
movq %r14, %rdi
movq %r15, %rsi
movq %r12, %rdx
movq %r13, %rcx
callq __hipPopCallConfiguration
movq (%r14), %rsi
movl 8(%r14), %edx
movq (%r15), %rcx
movl 8(%r15), %r8d
movl $_Z13subVectorsGpuPfS_S_i, %edi
movq %rbx, %r9
pushq (%r13)
.cfi_adjust_cfa_offset 8
pushq (%r12)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $128, %rsp
.cfi_adjust_cfa_offset -128
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end7:
.size _Z28__device_stub__subVectorsGpuPfS_S_i, .Lfunc_end7-_Z28__device_stub__subVectorsGpuPfS_S_i
.cfi_endproc
# -- End function
.globl _Z10ask_repeatv # -- Begin function _Z10ask_repeatv
.type _Z10ask_repeatv,@function
_Z10ask_repeatv: # @_Z10ask_repeatv
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
pushq %rax
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
leaq 7(%rsp), %rbx
movabsq $8800387991553, %r14 # imm = 0x80100000801
.LBB8_1: # =>This Inner Loop Header: Depth=1
movl $.L.str, %edi
xorl %eax, %eax
callq printf
movl $10, %edi
callq putchar@PLT
movl $.L.str.2, %edi
movq %rbx, %rsi
xorl %eax, %eax
callq __isoc23_scanf
movzbl 7(%rsp), %eax
leal -78(%rax), %ecx
cmpl $43, %ecx
ja .LBB8_3
# %bb.2: # in Loop: Header=BB8_1 Depth=1
btq %rcx, %r14
jb .LBB8_4
.LBB8_3: # in Loop: Header=BB8_1 Depth=1
movl $.L.str.3, %edi
xorl %eax, %eax
callq printf
jmp .LBB8_1
.LBB8_4:
andb $-33, %al
cmpb $89, %al
sete %al
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.Lfunc_end8:
.size _Z10ask_repeatv, .Lfunc_end8-_Z10ask_repeatv
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI9_0:
.quad 0x412e848000000000 # double 1.0E+6
.text
.globl main
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $88, %rsp
.cfi_def_cfa_offset 144
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
leaq 52(%rsp), %rdi
callq hipGetDevice
movl $.L.str.4, %edi
xorl %eax, %eax
callq printf
movq %rsp, %r14
movl $.L.str.5, %edi
movq %r14, %rsi
xorl %eax, %eax
callq __isoc23_scanf
movslq (%r14), %rbx
shlq $2, %rbx
leaq 32(%rsp), %r15
movq %r15, %rdi
movq %rbx, %rsi
movl $1, %edx
callq hipMallocManaged
leaq 24(%rsp), %r12
movq %r12, %rdi
movq %rbx, %rsi
movl $1, %edx
callq hipMallocManaged
movq (%r15), %rdi
movq %rbx, %rsi
movl $-1, %edx
xorl %ecx, %ecx
callq hipMemPrefetchAsync
movq (%r12), %rdi
movq %rbx, %rsi
movl $-1, %edx
xorl %ecx, %ecx
callq hipMemPrefetchAsync
movl (%r14), %r14d
testl %r14d, %r14d
jle .LBB9_6
# %bb.1: # %.lr.ph.preheader.i
movq 32(%rsp), %r15
xorl %r12d, %r12d
.LBB9_2: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
callq rand
cltq
imulq $1374389535, %rax, %rcx # imm = 0x51EB851F
movq %rcx, %rdx
shrq $63, %rdx
sarq $37, %rcx
addl %edx, %ecx
imull $100, %ecx, %ecx
subl %ecx, %eax
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movss %xmm0, (%r15,%r12,4)
incq %r12
cmpq %r12, %r14
jne .LBB9_2
# %bb.3: # %_Z7initVecPfi.exit
movl (%rsp), %r14d
testl %r14d, %r14d
jle .LBB9_6
# %bb.4: # %.lr.ph.preheader.i63
movq 24(%rsp), %r15
xorl %r12d, %r12d
.LBB9_5: # %.lr.ph.i65
# =>This Inner Loop Header: Depth=1
callq rand
cltq
imulq $1374389535, %rax, %rcx # imm = 0x51EB851F
movq %rcx, %rdx
shrq $63, %rdx
sarq $37, %rcx
addl %edx, %ecx
imull $100, %ecx, %ecx
subl %ecx, %eax
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movss %xmm0, (%r15,%r12,4)
incq %r12
cmpq %r12, %r14
jne .LBB9_5
.LBB9_6: # %_Z7initVecPfi.exit69
movabsq $4294967296, %rbp # imm = 0x100000000
movq 32(%rsp), %rdi
movl 52(%rsp), %edx
movq %rbx, %rsi
xorl %ecx, %ecx
callq hipMemPrefetchAsync
movq 24(%rsp), %rdi
movl 52(%rsp), %edx
movq %rbx, %rsi
xorl %ecx, %ecx
callq hipMemPrefetchAsync
movl $.Lstr, %edi
callq puts@PLT
movl $.Lstr.1, %edi
callq puts@PLT
movl $.Lstr.2, %edi
callq puts@PLT
movl $.Lstr.3, %edi
callq puts@PLT
leaq 7(%rsp), %r14
movl $.L.str.2, %edi
movq %r14, %rsi
xorl %eax, %eax
callq __isoc23_scanf
movzbl (%r14), %eax
cmpl $45, %eax
je .LBB9_22
# %bb.7: # %_Z7initVecPfi.exit69
cmpl $43, %eax
je .LBB9_12
# %bb.8: # %_Z7initVecPfi.exit69
cmpl $42, %eax
jne .LBB9_39
# %bb.9:
callq clock
movq %rax, %rbx
callq clock
subq %rbx, %rax
xorps %xmm0, %xmm0
cvtsi2sd %rax, %xmm0
divsd .LCPI9_0(%rip), %xmm0
movl $.L.str.10, %edi
movb $1, %al
callq printf
leaq 80(%rsp), %rbx
movq %rbx, %rdi
callq hipEventCreate
leaq 16(%rsp), %rdi
callq hipEventCreate
movq (%rbx), %rdi
xorl %esi, %esi
callq hipEventRecord
leaq 1(%rbp), %rdi
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB9_11
# %bb.10:
movq 32(%rsp), %rdi
movq 24(%rsp), %rsi
movl (%rsp), %edx
xorpd %xmm0, %xmm0
callq _Z28__device_stub__dotVectorsGpufPfS_i
.LBB9_11:
callq hipDeviceSynchronize
movq 16(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 16(%rsp), %rdi
callq hipEventSynchronize
movq 80(%rsp), %rsi
movq 16(%rsp), %rdx
leaq 68(%rsp), %rdi
callq hipEventElapsedTime
movl $.L.str.11, %edi
jmp .LBB9_32
.LBB9_12:
leaq 8(%rsp), %r14
movq %r14, %rdi
movq %rbx, %rsi
movl $1, %edx
callq hipMallocManaged
movq (%r14), %rdi
movq %rbx, %rsi
movl $-1, %edx
xorl %ecx, %ecx
callq hipMemPrefetchAsync
movq (%r14), %r14
movl (%rsp), %edx
testl %edx, %edx
jle .LBB9_14
# %bb.13: # %.lr.ph.preheader.i70
shlq $2, %rdx
movq %r14, %rdi
xorl %esi, %esi
callq memset@PLT
.LBB9_14: # %_Z8initWithfPfi.exit
movl 52(%rsp), %edx
movq %r14, %rdi
movq %rbx, %rsi
xorl %ecx, %ecx
callq hipMemPrefetchAsync
callq clock
movq %rax, %rbx
movl (%rsp), %eax
testl %eax, %eax
jle .LBB9_17
# %bb.15: # %.lr.ph.preheader.i76
movq 8(%rsp), %rcx
movq 32(%rsp), %rdx
movq 24(%rsp), %rsi
xorl %edi, %edi
.LBB9_16: # %.lr.ph.i78
# =>This Inner Loop Header: Depth=1
movss (%rdx,%rdi,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
addss (%rsi,%rdi,4), %xmm0
movss %xmm0, (%rcx,%rdi,4)
incq %rdi
cmpq %rdi, %rax
jne .LBB9_16
.LBB9_17: # %_Z13addVectorsCPUPfS_S_i.exit
callq clock
subq %rbx, %rax
xorps %xmm0, %xmm0
cvtsi2sd %rax, %xmm0
divsd .LCPI9_0(%rip), %xmm0
movl $.L.str.12, %edi
movb $1, %al
callq printf
leaq 80(%rsp), %rbx
movq %rbx, %rdi
callq hipEventCreate
leaq 16(%rsp), %rdi
callq hipEventCreate
movq (%rbx), %rdi
xorl %esi, %esi
callq hipEventRecord
movl (%rsp), %edx
testl %edx, %edx
jle .LBB9_19
# %bb.18: # %.lr.ph.preheader.i82
movq 8(%rsp), %rdi
shlq $2, %rdx
xorl %esi, %esi
callq memset@PLT
.LBB9_19: # %_Z8initWithfPfi.exit88
leaq 1(%rbp), %rdi
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB9_21
# %bb.20:
movq 8(%rsp), %rdi
movq 32(%rsp), %rsi
movq 24(%rsp), %rdx
movl (%rsp), %ecx
callq _Z28__device_stub__addVectorsGpuPfS_S_i
.LBB9_21:
callq hipDeviceSynchronize
movq 16(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 16(%rsp), %rdi
callq hipEventSynchronize
movq 80(%rsp), %rsi
movq 16(%rsp), %rdx
leaq 68(%rsp), %rdi
callq hipEventElapsedTime
movl $.L.str.13, %edi
jmp .LBB9_32
.LBB9_22:
leaq 8(%rsp), %r14
movq %r14, %rdi
movq %rbx, %rsi
movl $1, %edx
callq hipMallocManaged
movq (%r14), %rdi
movq %rbx, %rsi
movl $-1, %edx
xorl %ecx, %ecx
callq hipMemPrefetchAsync
movq (%r14), %r14
movl (%rsp), %edx
testl %edx, %edx
jle .LBB9_24
# %bb.23: # %.lr.ph.preheader.i89
shlq $2, %rdx
movq %r14, %rdi
xorl %esi, %esi
callq memset@PLT
.LBB9_24: # %_Z8initWithfPfi.exit95
movl 52(%rsp), %edx
movq %r14, %rdi
movq %rbx, %rsi
xorl %ecx, %ecx
callq hipMemPrefetchAsync
callq clock
movq %rax, %rbx
movl (%rsp), %eax
testl %eax, %eax
jle .LBB9_27
# %bb.25: # %.lr.ph.preheader.i96
movq 8(%rsp), %rcx
movq 32(%rsp), %rdx
movq 24(%rsp), %rsi
xorl %edi, %edi
.LBB9_26: # %.lr.ph.i98
# =>This Inner Loop Header: Depth=1
movss (%rdx,%rdi,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
subss (%rsi,%rdi,4), %xmm0
movss %xmm0, (%rcx,%rdi,4)
incq %rdi
cmpq %rdi, %rax
jne .LBB9_26
.LBB9_27: # %_Z13subVectorsCPUPfS_S_i.exit
callq clock
subq %rbx, %rax
xorps %xmm0, %xmm0
cvtsi2sd %rax, %xmm0
divsd .LCPI9_0(%rip), %xmm0
movl $.L.str.14, %edi
movb $1, %al
callq printf
leaq 80(%rsp), %rbx
movq %rbx, %rdi
callq hipEventCreate
leaq 16(%rsp), %rdi
callq hipEventCreate
movq (%rbx), %rdi
xorl %esi, %esi
callq hipEventRecord
movl (%rsp), %edx
testl %edx, %edx
jle .LBB9_29
# %bb.28: # %.lr.ph.preheader.i102
movq 8(%rsp), %rdi
shlq $2, %rdx
xorl %esi, %esi
callq memset@PLT
.LBB9_29: # %_Z8initWithfPfi.exit108
leaq 1(%rbp), %rdi
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB9_31
# %bb.30:
movq 8(%rsp), %rdi
movq 32(%rsp), %rsi
movq 24(%rsp), %rdx
movl (%rsp), %ecx
callq _Z28__device_stub__subVectorsGpuPfS_S_i
.LBB9_31:
callq hipDeviceSynchronize
movq 16(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 16(%rsp), %rdi
callq hipEventSynchronize
movq 80(%rsp), %rsi
movq 16(%rsp), %rdx
leaq 68(%rsp), %rdi
callq hipEventElapsedTime
movl $.L.str.15, %edi
.LBB9_32:
xorps %xmm0, %xmm0
cvtss2sd 68(%rsp), %xmm0
movb $1, %al
callq printf
leaq 64(%rsp), %rbx
leaq 60(%rsp), %r14
leaq 72(%rsp), %r15
leaq 40(%rsp), %r12
leaq 56(%rsp), %r13
.LBB9_33: # %.backedge
# =>This Inner Loop Header: Depth=1
movl $.L.str.18, %edi
xorl %eax, %eax
callq printf
movl $.L.str.5, %edi
movq %rbx, %rsi
xorl %eax, %eax
callq __isoc23_scanf
movl $.L.str.19, %edi
xorl %eax, %eax
callq printf
movl $.L.str.5, %edi
movq %r14, %rsi
xorl %eax, %eax
callq __isoc23_scanf
movzbl 7(%rsp), %eax
cmpl $45, %eax
je .LBB9_48
# %bb.34: # %.backedge
# in Loop: Header=BB9_33 Depth=1
cmpl $43, %eax
je .LBB9_41
# %bb.35: # %.backedge
# in Loop: Header=BB9_33 Depth=1
cmpl $42, %eax
jne .LBB9_53
# %bb.36: # in Loop: Header=BB9_33 Depth=1
movq %r15, %rdi
callq hipEventCreate
movq %r12, %rdi
callq hipEventCreate
movq 72(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movl 64(%rsp), %edi
movl 60(%rsp), %edx
orq %rbp, %rdi
orq %rbp, %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB9_38
# %bb.37: # in Loop: Header=BB9_33 Depth=1
movq 32(%rsp), %rdi
movq 24(%rsp), %rsi
movl (%rsp), %edx
xorps %xmm0, %xmm0
callq _Z28__device_stub__dotVectorsGpufPfS_i
.LBB9_38: # in Loop: Header=BB9_33 Depth=1
movq 40(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 40(%rsp), %rdi
callq hipEventSynchronize
movq 72(%rsp), %rsi
movq 40(%rsp), %rdx
movq %r13, %rdi
callq hipEventElapsedTime
xorps %xmm0, %xmm0
cvtss2sd 56(%rsp), %xmm0
movl $.L.str.20, %edi
jmp .LBB9_46
.LBB9_41: # in Loop: Header=BB9_33 Depth=1
movq %r15, %rdi
callq hipEventCreate
movq %r12, %rdi
callq hipEventCreate
movq 72(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movl (%rsp), %edx
testl %edx, %edx
jle .LBB9_43
# %bb.42: # %.lr.ph.preheader.i109
# in Loop: Header=BB9_33 Depth=1
movq 8(%rsp), %rdi
shlq $2, %rdx
xorl %esi, %esi
callq memset@PLT
.LBB9_43: # %_Z8initWithfPfi.exit115
# in Loop: Header=BB9_33 Depth=1
movl 64(%rsp), %edi
movl 60(%rsp), %edx
orq %rbp, %rdi
orq %rbp, %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB9_45
# %bb.44: # in Loop: Header=BB9_33 Depth=1
movq 8(%rsp), %rdi
movq 32(%rsp), %rsi
movq 24(%rsp), %rdx
movl (%rsp), %ecx
callq _Z28__device_stub__addVectorsGpuPfS_S_i
.LBB9_45: # in Loop: Header=BB9_33 Depth=1
movq 40(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 40(%rsp), %rdi
callq hipEventSynchronize
movq 72(%rsp), %rsi
movq 40(%rsp), %rdx
movq %r13, %rdi
callq hipEventElapsedTime
xorps %xmm0, %xmm0
cvtss2sd 56(%rsp), %xmm0
movl $.L.str.21, %edi
jmp .LBB9_46
.LBB9_48: # in Loop: Header=BB9_33 Depth=1
movq %r15, %rdi
callq hipEventCreate
movq %r12, %rdi
callq hipEventCreate
movq 72(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movl (%rsp), %edx
testl %edx, %edx
jle .LBB9_50
# %bb.49: # %.lr.ph.preheader.i116
# in Loop: Header=BB9_33 Depth=1
movq 8(%rsp), %rdi
shlq $2, %rdx
xorl %esi, %esi
callq memset@PLT
.LBB9_50: # %_Z8initWithfPfi.exit122
# in Loop: Header=BB9_33 Depth=1
movl 64(%rsp), %edi
movl 60(%rsp), %edx
orq %rbp, %rdi
orq %rbp, %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB9_52
# %bb.51: # in Loop: Header=BB9_33 Depth=1
movq 8(%rsp), %rdi
movq 32(%rsp), %rsi
movq 24(%rsp), %rdx
movl (%rsp), %ecx
callq _Z28__device_stub__subVectorsGpuPfS_S_i
.LBB9_52: # in Loop: Header=BB9_33 Depth=1
movq 40(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 40(%rsp), %rdi
callq hipEventSynchronize
movq 72(%rsp), %rsi
movq 40(%rsp), %rdx
movq %r13, %rdi
callq hipEventElapsedTime
xorps %xmm0, %xmm0
cvtss2sd 56(%rsp), %xmm0
movl $.L.str.22, %edi
.LBB9_46: # in Loop: Header=BB9_33 Depth=1
movb $1, %al
callq printf
callq hipDeviceSynchronize
callq _Z10ask_repeatv
testb %al, %al
jne .LBB9_33
jmp .LBB9_47
.LBB9_39:
movl $.Lstr.5, %edi
jmp .LBB9_40
.LBB9_53: # %.thread
movl $.Lstr.4, %edi
.LBB9_40:
callq puts@PLT
.LBB9_47:
movl $.L.str.17, %edi
xorl %eax, %eax
callq printf
xorl %eax, %eax
addq $88, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end9:
.size main, .Lfunc_end9-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
movq __hip_gpubin_handle(%rip), %rbx
testq %rbx, %rbx
jne .LBB10_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, %rbx
movq %rax, __hip_gpubin_handle(%rip)
.LBB10_2:
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13dotVectorsGpufPfS_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13addVectorsGpuPfS_S_i, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13subVectorsGpuPfS_S_i, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end10:
.size __hip_module_ctor, .Lfunc_end10-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB11_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB11_2:
retq
.Lfunc_end11:
.size __hip_module_dtor, .Lfunc_end11-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z13dotVectorsGpufPfS_i,@object # @_Z13dotVectorsGpufPfS_i
.section .rodata,"a",@progbits
.globl _Z13dotVectorsGpufPfS_i
.p2align 3, 0x0
_Z13dotVectorsGpufPfS_i:
.quad _Z28__device_stub__dotVectorsGpufPfS_i
.size _Z13dotVectorsGpufPfS_i, 8
.type _Z13addVectorsGpuPfS_S_i,@object # @_Z13addVectorsGpuPfS_S_i
.globl _Z13addVectorsGpuPfS_S_i
.p2align 3, 0x0
_Z13addVectorsGpuPfS_S_i:
.quad _Z28__device_stub__addVectorsGpuPfS_S_i
.size _Z13addVectorsGpuPfS_S_i, 8
.type _Z13subVectorsGpuPfS_S_i,@object # @_Z13subVectorsGpuPfS_S_i
.globl _Z13subVectorsGpuPfS_S_i
.p2align 3, 0x0
_Z13subVectorsGpuPfS_S_i:
.quad _Z28__device_stub__subVectorsGpuPfS_S_i
.size _Z13subVectorsGpuPfS_S_i, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "\nDo You want to improve your score? (y/n)"
.size .L.str, 42
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz " %c"
.size .L.str.2, 4
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "\nWrong answer! Give y or n!"
.size .L.str.3, 28
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Give the length of vectors you want to work with:"
.size .L.str.4, 50
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "%d"
.size .L.str.5, 3
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "\nTime elapsed dotting vectors on CPU is: %f"
.size .L.str.10, 44
.type .L.str.11,@object # @.str.11
.L.str.11:
.asciz "\nTime elapsed on single-threaded vector dotting: %f \n"
.size .L.str.11, 54
.type .L.str.12,@object # @.str.12
.L.str.12:
.asciz "\nTime elapsed adding vectors on CPU is: %f"
.size .L.str.12, 43
.type .L.str.13,@object # @.str.13
.L.str.13:
.asciz "\nTime elapsed on single-threaded vector addition: %f \n"
.size .L.str.13, 55
.type .L.str.14,@object # @.str.14
.L.str.14:
.asciz "\nTime elapsed subtracting vectors on CPU is: %f"
.size .L.str.14, 48
.type .L.str.15,@object # @.str.15
.L.str.15:
.asciz "\nTime elapsed on single-threaded vector subtracting: %f \n"
.size .L.str.15, 58
.type .L.str.17,@object # @.str.17
.L.str.17:
.asciz "Quiting..."
.size .L.str.17, 11
.type .L.str.18,@object # @.str.18
.L.str.18:
.asciz "\nGive the size of block you want to use:"
.size .L.str.18, 41
.type .L.str.19,@object # @.str.19
.L.str.19:
.asciz "Give the number of threads per block you want to use:"
.size .L.str.19, 54
.type .L.str.20,@object # @.str.20
.L.str.20:
.asciz "\nTime elapsed on your size vectors dot product: %f\n"
.size .L.str.20, 52
.type .L.str.21,@object # @.str.21
.L.str.21:
.asciz "\nTime elapsed on your size vectors addition: %f\n"
.size .L.str.21, 49
.type .L.str.22,@object # @.str.22
.L.str.22:
.asciz "\nTime elapsed on your size vectors subtraction: %f\n"
.size .L.str.22, 52
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z13dotVectorsGpufPfS_i"
.size .L__unnamed_1, 24
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z13addVectorsGpuPfS_S_i"
.size .L__unnamed_2, 25
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z13subVectorsGpuPfS_S_i"
.size .L__unnamed_3, 25
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Choose mathematical operations:"
.size .Lstr, 32
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "Type '*' for dotting vectors"
.size .Lstr.1, 29
.type .Lstr.2,@object # @str.2
.Lstr.2:
.asciz "Type '+' for adding vectors"
.size .Lstr.2, 28
.type .Lstr.3,@object # @str.3
.Lstr.3:
.asciz "Type '-' for subtracting vectors"
.size .Lstr.3, 33
.type .Lstr.4,@object # @str.4
.Lstr.4:
.asciz "Error!"
.size .Lstr.4, 7
.type .Lstr.5,@object # @str.5
.Lstr.5:
.asciz "Error! operator is not correct"
.size .Lstr.5, 31
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z28__device_stub__dotVectorsGpufPfS_i
.addrsig_sym _Z28__device_stub__addVectorsGpuPfS_S_i
.addrsig_sym _Z28__device_stub__subVectorsGpuPfS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z13dotVectorsGpufPfS_i
.addrsig_sym _Z13addVectorsGpuPfS_S_i
.addrsig_sym _Z13subVectorsGpuPfS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
```
| 12,814 | 14,741 |
208 |
Convert the following CUDA device assembly code to AMD device assembly:
```cudaasm
code for sm_80
Function : _Z4fillPim
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
MOV R1, c[0x0][0x28] ;
S2R R5, SR_TID.X ;
HFMA2.MMA R2, -RZ, RZ, 0, 2.384185791015625e-07 ;
ULDC.64 UR4, c[0x0][0x118] ;
IMAD.WIDE.U32 R2, R5, R2, c[0x0][0x160] ;
STG.E [R2.64], R5 ;
EXIT ;
BRA 0x70;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
```
|
```amdasm
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z4fillPim ; -- Begin function _Z4fillPim
.globl _Z4fillPim
.p2align 8
.type _Z4fillPim,@function
_Z4fillPim: ; @_Z4fillPim
; %bb.0:
s_load_b64 s[0:1], s[0:1], 0x0
v_lshlrev_b32_e32 v1, 2, v0
s_waitcnt lgkmcnt(0)
global_store_b32 v1, v0, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z4fillPim
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 16
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 2
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z4fillPim, .Lfunc_end0-_Z4fillPim
; -- End function
.section .AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 36
; NumSgprs: 2
; NumVgprs: 2
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 0
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 2
; NumVGPRsForWavesPerEU: 2
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object ; @__hip_cuid_
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0 ; 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 8
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 16
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z4fillPim
.private_segment_fixed_size: 0
.sgpr_count: 2
.sgpr_spill_count: 0
.symbol: _Z4fillPim.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
```
| 224 | 1,616 |
209 |
Convert the following CUDA host assembly code to AMD host assembly:
```cudaasm
.file "tmpxft_00171588_00000000-6_05-errors.cudafe1.cpp"
.text
.globl _ZSt21ios_base_library_initv
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB4035:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4035:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z24__device_stub__Z4fillPimPim
.type _Z24__device_stub__Z4fillPimPim, @function
_Z24__device_stub__Z4fillPimPim:
.LFB4057:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z4fillPim(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4057:
.size _Z24__device_stub__Z4fillPimPim, .-_Z24__device_stub__Z4fillPimPim
.globl _Z4fillPim
.type _Z4fillPim, @function
_Z4fillPim:
.LFB4058:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z24__device_stub__Z4fillPimPim
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4058:
.size _Z4fillPim, .-_Z4fillPim
.globl main
.type main, @function
main:
.LFB4032:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA4032
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $56, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movl $400, %edi
.LEHB0:
call _Znwm@PLT
.LEHE0:
movq %rax, %r13
leaq 400(%rax), %rdx
movl $0, (%rax)
leaq 4(%rax), %rax
.L12:
movl $0, (%rax)
addq $4, %rax
cmpq %rdx, %rax
jne .L12
movq $0, 8(%rsp)
leaq 8(%rsp), %rdi
movl $400, %esi
.LEHB1:
call cudaMalloc@PLT
movl $1025, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L13
movl $100, %esi
movq 8(%rsp), %rdi
call _Z24__device_stub__Z4fillPimPim
.L13:
call cudaDeviceSynchronize@PLT
call cudaGetLastError@PLT
testl %eax, %eax
je .L14
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
.L14:
call cudaDeviceSynchronize@PLT
call cudaGetLastError@PLT
testl %eax, %eax
je .L15
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rsi
leaq _ZSt4cerr(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
.L15:
movl $2, %ecx
movl $400, %edx
movq 8(%rsp), %rsi
movq %r13, %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L16
.L18:
movq %r13, %r12
leaq 400(%r13), %r15
leaq _ZSt4cout(%rip), %r14
jmp .L17
.L16:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rsi
leaq _ZSt4cerr(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
jmp .L18
.L35:
movq %rax, %rbx
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %rbp
testq %rbp, %rbp
je .L31
cmpb $0, 56(%rbp)
je .L21
movzbl 67(%rbp), %esi
.L22:
movsbl %sil, %esi
movq %rbx, %rdi
call _ZNSo3putEc@PLT
jmp .L32
.L31:
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L33
call _ZSt16__throw_bad_castv@PLT
.L26:
endbr64
movq %rax, %rbx
movl $400, %esi
movq %r13, %rdi
call _ZdlPvm@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
je .L24
call __stack_chk_fail@PLT
.L33:
call __stack_chk_fail@PLT
.L21:
movq %rbp, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq 0(%rbp), %rax
movl $10, %esi
movq %rbp, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L22
.L32:
movq %rax, %rdi
call _ZNSo5flushEv@PLT
addq $4, %r12
cmpq %r12, %r15
je .L34
.L17:
movl (%r12), %esi
movq %r14, %rdi
call _ZNSolsEi@PLT
.LEHE1:
jmp .L35
.L34:
movl $400, %esi
movq %r13, %rdi
call _ZdlPvm@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L36
movl $0, %eax
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L24:
.cfi_restore_state
movq %rbx, %rdi
.LEHB2:
call _Unwind_Resume@PLT
.LEHE2:
.L36:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4032:
.globl __gxx_personality_v0
.section .gcc_except_table,"a",@progbits
.LLSDA4032:
.byte 0xff
.byte 0xff
.byte 0x1
.uleb128 .LLSDACSE4032-.LLSDACSB4032
.LLSDACSB4032:
.uleb128 .LEHB0-.LFB4032
.uleb128 .LEHE0-.LEHB0
.uleb128 0
.uleb128 0
.uleb128 .LEHB1-.LFB4032
.uleb128 .LEHE1-.LEHB1
.uleb128 .L26-.LFB4032
.uleb128 0
.uleb128 .LEHB2-.LFB4032
.uleb128 .LEHE2-.LEHB2
.uleb128 0
.uleb128 0
.LLSDACSE4032:
.text
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z4fillPim"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB4060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z4fillPim(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4060:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.hidden DW.ref.__gxx_personality_v0
.weak DW.ref.__gxx_personality_v0
.section .data.rel.local.DW.ref.__gxx_personality_v0,"awG",@progbits,DW.ref.__gxx_personality_v0,comdat
.align 8
.type DW.ref.__gxx_personality_v0, @object
.size DW.ref.__gxx_personality_v0, 8
DW.ref.__gxx_personality_v0:
.quad __gxx_personality_v0
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
```
|
```amdasm
.text
.file "05-errors.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z19__device_stub__fillPim # -- Begin function _Z19__device_stub__fillPim
.type _Z19__device_stub__fillPim,@function
_Z19__device_stub__fillPim: # @_Z19__device_stub__fillPim
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $80, %rsp
.cfi_def_cfa_offset 128
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 24(%rsp), %rax
movq %rdi, (%rax)
leaq 16(%rsp), %rcx
movq %rsi, (%rcx)
leaq 64(%rsp), %rbx
movq %rax, (%rbx)
movq %rcx, 8(%rbx)
leaq 48(%rsp), %r14
leaq 32(%rsp), %r15
leaq 8(%rsp), %r12
movq %rsp, %r13
movq %r14, %rdi
movq %r15, %rsi
movq %r12, %rdx
movq %r13, %rcx
callq __hipPopCallConfiguration
movq (%r14), %rsi
movl 8(%r14), %edx
movq (%r15), %rcx
movl 8(%r15), %r8d
movl $_Z4fillPim, %edi
movq %rbx, %r9
pushq (%r13)
.cfi_adjust_cfa_offset 8
pushq (%r12)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $96, %rsp
.cfi_adjust_cfa_offset -96
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z19__device_stub__fillPim, .Lfunc_end0-_Z19__device_stub__fillPim
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.type main,@function
main: # @main
.Lfunc_begin0:
.cfi_startproc
.cfi_personality 3, __gxx_personality_v0
.cfi_lsda 3, .Lexception0
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $16, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $400, %edi # imm = 0x190
callq _Znwm
movq %rax, %rbx
movl $400, %edx # imm = 0x190
movq %rax, %rdi
xorl %esi, %esi
callq memset@PLT
leaq 8(%rsp), %rdi
movq $0, (%rdi)
.Ltmp0:
movl $400, %esi # imm = 0x190
callq hipMalloc
.Ltmp1:
# %bb.1: # %_ZL9hipMallocIiE10hipError_tPPT_m.exit
.Ltmp2:
movabsq $4294967297, %rdi # imm = 0x100000001
movabsq $4294968321, %rdx # imm = 0x100000401
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
.Ltmp3:
# %bb.2:
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq 8(%rsp), %rdi
.Ltmp4:
movl $100, %esi
callq _Z19__device_stub__fillPim
.Ltmp5:
.LBB1_4:
.Ltmp6:
callq hipDeviceSynchronize
.Ltmp7:
# %bb.5:
.Ltmp9:
callq hipGetLastError
.Ltmp10:
# %bb.6:
testl %eax, %eax
je .LBB1_12
# %bb.7:
.Ltmp11:
movl %eax, %edi
callq hipGetErrorString
.Ltmp12:
# %bb.8:
movq %rax, %r14
testq %rax, %rax
je .LBB1_9
# %bb.11:
movq %r14, %rdi
callq strlen
.Ltmp13:
movl $_ZSt4cout, %edi
movq %r14, %rsi
movq %rax, %rdx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp14:
jmp .LBB1_12
.LBB1_9:
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
leaq _ZSt4cout(%rax), %rdi
movl 32(%rdi), %esi
orl $1, %esi
.Ltmp15:
callq _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate
.Ltmp16:
.LBB1_12: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit
.Ltmp17:
callq hipDeviceSynchronize
.Ltmp18:
# %bb.13:
.Ltmp20:
callq hipGetLastError
.Ltmp21:
# %bb.14:
testl %eax, %eax
je .LBB1_20
# %bb.15:
.Ltmp22:
movl %eax, %edi
callq hipGetErrorString
.Ltmp23:
# %bb.16:
movq %rax, %r14
testq %rax, %rax
je .LBB1_17
# %bb.19:
movq %r14, %rdi
callq strlen
.Ltmp24:
movl $_ZSt4cerr, %edi
movq %r14, %rsi
movq %rax, %rdx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp25:
jmp .LBB1_20
.LBB1_17:
movq _ZSt4cerr(%rip), %rax
movq -24(%rax), %rax
leaq _ZSt4cerr(%rax), %rdi
movl 32(%rdi), %esi
orl $1, %esi
.Ltmp26:
callq _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate
.Ltmp27:
.LBB1_20: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit31
movq 8(%rsp), %rsi
.Ltmp28:
movl $400, %edx # imm = 0x190
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
.Ltmp29:
# %bb.21:
testl %eax, %eax
je .LBB1_22
# %bb.29:
.Ltmp30:
movl %eax, %edi
callq hipGetErrorString
.Ltmp31:
# %bb.30:
movq %rax, %r14
testq %rax, %rax
je .LBB1_31
# %bb.32:
movq %r14, %rdi
callq strlen
.Ltmp32:
movl $_ZSt4cerr, %edi
movq %r14, %rsi
movq %rax, %rdx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp33:
jmp .LBB1_22
.LBB1_31:
movq _ZSt4cerr(%rip), %rax
movq -24(%rax), %rax
leaq _ZSt4cerr(%rax), %rdi
movl 32(%rdi), %esi
orl $1, %esi
.Ltmp34:
callq _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate
.Ltmp35:
.LBB1_22: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit35.preheader
xorl %r15d, %r15d
.LBB1_23: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit35
# =>This Inner Loop Header: Depth=1
movl (%rbx,%r15), %esi
.Ltmp37:
movl $_ZSt4cout, %edi
callq _ZNSolsEi
.Ltmp38:
# %bb.24: # in Loop: Header=BB1_23 Depth=1
movq %rax, %r14
movq (%rax), %rax
movq -24(%rax), %rdi
addq %r14, %rdi
.Ltmp39:
movl $10, %esi
callq _ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
.Ltmp40:
# %bb.25: # %.noexc40
# in Loop: Header=BB1_23 Depth=1
.Ltmp41:
movsbl %al, %esi
movq %r14, %rdi
callq _ZNSo3putEc
.Ltmp42:
# %bb.26: # %.noexc41
# in Loop: Header=BB1_23 Depth=1
.Ltmp43:
movq %rax, %rdi
callq _ZNSo5flushEv
.Ltmp44:
# %bb.27: # %_ZNSolsEPFRSoS_E.exit
# in Loop: Header=BB1_23 Depth=1
addq $4, %r15
cmpq $400, %r15 # imm = 0x190
jne .LBB1_23
# %bb.28: # %_ZNSt6vectorIiSaIiEED2Ev.exit
movq %rbx, %rdi
callq _ZdlPv
xorl %eax, %eax
addq $16, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB1_10:
.cfi_def_cfa_offset 48
.Ltmp19:
jmp .LBB1_34
.LBB1_35:
.Ltmp8:
jmp .LBB1_34
.LBB1_18:
.Ltmp36:
jmp .LBB1_34
.LBB1_33:
.Ltmp45:
.LBB1_34: # %_ZNSt6vectorIiSaIiEED2Ev.exit38
movq %rax, %r14
movq %rbx, %rdi
callq _ZdlPv
movq %r14, %rdi
callq _Unwind_Resume@PLT
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
.section .gcc_except_table,"a",@progbits
.p2align 2, 0x0
GCC_except_table1:
.Lexception0:
.byte 255 # @LPStart Encoding = omit
.byte 255 # @TType Encoding = omit
.byte 1 # Call site Encoding = uleb128
.uleb128 .Lcst_end0-.Lcst_begin0
.Lcst_begin0:
.uleb128 .Lfunc_begin0-.Lfunc_begin0 # >> Call Site 1 <<
.uleb128 .Ltmp0-.Lfunc_begin0 # Call between .Lfunc_begin0 and .Ltmp0
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp0-.Lfunc_begin0 # >> Call Site 2 <<
.uleb128 .Ltmp7-.Ltmp0 # Call between .Ltmp0 and .Ltmp7
.uleb128 .Ltmp8-.Lfunc_begin0 # jumps to .Ltmp8
.byte 0 # On action: cleanup
.uleb128 .Ltmp9-.Lfunc_begin0 # >> Call Site 3 <<
.uleb128 .Ltmp18-.Ltmp9 # Call between .Ltmp9 and .Ltmp18
.uleb128 .Ltmp19-.Lfunc_begin0 # jumps to .Ltmp19
.byte 0 # On action: cleanup
.uleb128 .Ltmp20-.Lfunc_begin0 # >> Call Site 4 <<
.uleb128 .Ltmp35-.Ltmp20 # Call between .Ltmp20 and .Ltmp35
.uleb128 .Ltmp36-.Lfunc_begin0 # jumps to .Ltmp36
.byte 0 # On action: cleanup
.uleb128 .Ltmp37-.Lfunc_begin0 # >> Call Site 5 <<
.uleb128 .Ltmp44-.Ltmp37 # Call between .Ltmp37 and .Ltmp44
.uleb128 .Ltmp45-.Lfunc_begin0 # jumps to .Ltmp45
.byte 0 # On action: cleanup
.uleb128 .Ltmp44-.Lfunc_begin0 # >> Call Site 6 <<
.uleb128 .Lfunc_end1-.Ltmp44 # Call between .Ltmp44 and .Lfunc_end1
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.Lcst_end0:
.p2align 2, 0x0
# -- End function
.text
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, %rdi
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z4fillPim, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z4fillPim,@object # @_Z4fillPim
.section .rodata,"a",@progbits
.globl _Z4fillPim
.p2align 3, 0x0
_Z4fillPim:
.quad _Z19__device_stub__fillPim
.size _Z4fillPim, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z4fillPim"
.size .L__unnamed_1, 11
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z19__device_stub__fillPim
.addrsig_sym __gxx_personality_v0
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Unwind_Resume
.addrsig_sym _Z4fillPim
.addrsig_sym _ZSt4cout
.addrsig_sym _ZSt4cerr
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
```
| 4,055 | 5,259 |
212 |
Convert the following CUDA device assembly code to AMD device assembly:
```cudaasm
code for sm_80
Function : _Z6MataddPcS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
MOV R1, c[0x0][0x28] ;
EXIT ;
BRA 0x20;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
```
|
```amdasm
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6MataddPcS_i ; -- Begin function _Z6MataddPcS_i
.globl _Z6MataddPcS_i
.p2align 8
.type _Z6MataddPcS_i,@function
_Z6MataddPcS_i: ; @_Z6MataddPcS_i
; %bb.0:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6MataddPcS_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 20
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 1
.amdhsa_next_free_sgpr 1
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6MataddPcS_i, .Lfunc_end0-_Z6MataddPcS_i
; -- End function
.section .AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 4
; NumSgprs: 0
; NumVgprs: 0
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 0
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 1
; NumVGPRsForWavesPerEU: 1
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object ; @__hip_cuid_
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0 ; 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 20
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6MataddPcS_i
.private_segment_fixed_size: 0
.sgpr_count: 0
.sgpr_spill_count: 0
.symbol: _Z6MataddPcS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 0
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
```
| 122 | 1,596 |
213 |
Convert the following CUDA host assembly code to AMD host assembly:
```cudaasm
.file "tmpxft_001bb4b1_00000000-6_hw7p1_4.cudafe1.cpp"
.text
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z28__device_stub__Z6MataddPcS_iPcS_i
.type _Z28__device_stub__Z6MataddPcS_iPcS_i, @function
_Z28__device_stub__Z6MataddPcS_iPcS_i:
.LFB2082:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z6MataddPcS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z28__device_stub__Z6MataddPcS_iPcS_i, .-_Z28__device_stub__Z6MataddPcS_iPcS_i
.globl _Z6MataddPcS_i
.type _Z6MataddPcS_i, @function
_Z6MataddPcS_i:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z28__device_stub__Z6MataddPcS_iPcS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z6MataddPcS_i, .-_Z6MataddPcS_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "\n The value of N is %d"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC2:
.string "\n The Host to Device time for location A in microseconds for 2 to power %d is %f respectively \n"
.align 8
.LC3:
.string "\n The Device to Host time for location B in microseconds for 2 to power %d is %f respectively \n"
.align 8
.LC4:
.string "\n The total data transfer time in microseconds for 2 to power %d is %f respectively \n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $104, %rsp
.cfi_def_cfa_offset 160
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
movl $0, %r13d
leaq .LC1(%rip), %r15
leaq .LC2(%rip), %r14
jmp .L15
.L14:
movl $2, %ecx
movq %rbp, %rdx
movq 56(%rsp), %rsi
movq 40(%rsp), %rdi
call cudaMemcpy@PLT
movl $0, %esi
movq 24(%rsp), %rdi
call cudaEventRecord@PLT
movq 24(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 64(%rsp), %rdi
movq 8(%rsp), %rdx
movq (%rsp), %rsi
call cudaEventElapsedTime@PLT
leaq 76(%rsp), %rdi
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
call cudaEventElapsedTime@PLT
pxor %xmm0, %xmm0
cvtss2sd 64(%rsp), %xmm0
movl %r13d, %edx
movq %r14, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
pxor %xmm0, %xmm0
cvtss2sd 76(%rsp), %xmm0
movl %r13d, %edx
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movss 64(%rsp), %xmm0
addss 76(%rsp), %xmm0
cvtss2sd %xmm0, %xmm0
movl %r13d, %edx
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
movq 48(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rdi
call cudaFree@PLT
addl $1, %r13d
cmpl $26, %r13d
je .L20
.L15:
pxor %xmm1, %xmm1
cvtsi2sdl %r13d, %xmm1
movsd .LC0(%rip), %xmm0
call pow@PLT
cvttsd2sil %xmm0, %r12d
movslq %r12d, %rbp
movl %r12d, %edx
movq %r15, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %rsp, %rdi
call cudaEventCreate@PLT
leaq 8(%rsp), %rdi
call cudaEventCreate@PLT
leaq 16(%rsp), %rdi
call cudaEventCreate@PLT
leaq 24(%rsp), %rdi
call cudaEventCreate@PLT
leaq 32(%rsp), %rdi
movl $0, %edx
movq %rbp, %rsi
call cudaHostAlloc@PLT
leaq 40(%rsp), %rdi
movl $0, %edx
movq %rbp, %rsi
call cudaHostAlloc@PLT
testl %r12d, %r12d
jle .L12
movl $0, %ebx
.L13:
call rand@PLT
movslq %eax, %rdx
imulq $1717986919, %rdx, %rdx
sarq $35, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
leal (%rdx,%rdx,4), %edx
sall $2, %edx
subl %edx, %eax
subl $10, %eax
movq 32(%rsp), %rdx
movb %al, (%rdx,%rbx)
addq $1, %rbx
cmpq %rbx, %rbp
jne .L13
.L12:
leaq 48(%rsp), %rdi
movq %rbp, %rsi
call cudaMalloc@PLT
leaq 56(%rsp), %rdi
movq %rbp, %rsi
call cudaMalloc@PLT
movl $0, %esi
movq (%rsp), %rdi
call cudaEventRecord@PLT
movl $1, %ecx
movq %rbp, %rdx
movq 32(%rsp), %rsi
movq 48(%rsp), %rdi
call cudaMemcpy@PLT
movl $0, %esi
movq 8(%rsp), %rdi
call cudaEventRecord@PLT
movq 8(%rsp), %rdi
call cudaEventSynchronize@PLT
movl $0, %esi
movq 16(%rsp), %rdi
call cudaEventRecord@PLT
movl $16, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leal 30(%r12), %eax
movl %r12d, %edx
addl $15, %edx
cmovns %edx, %eax
sarl $4, %eax
movl %eax, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 76(%rsp), %rdx
movl $1, %ecx
movq 64(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L14
movl %r12d, %edx
movq 56(%rsp), %rsi
movq 48(%rsp), %rdi
call _Z28__device_stub__Z6MataddPcS_iPcS_i
jmp .L14
.L20:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L21
movl $0, %eax
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L21:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC5:
.string "_Z6MataddPcS_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _Z6MataddPcS_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC0:
.long 0
.long 1073741824
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
```
|
```amdasm
.text
.file "hw7p1_4.hip"
.globl _Z21__device_stub__MataddPcS_i # -- Begin function _Z21__device_stub__MataddPcS_i
.type _Z21__device_stub__MataddPcS_i,@function
_Z21__device_stub__MataddPcS_i: # @_Z21__device_stub__MataddPcS_i
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $112, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 40(%rsp), %rax
movq %rdi, (%rax)
leaq 32(%rsp), %rcx
movq %rsi, (%rcx)
leaq 12(%rsp), %rsi
movl %edx, (%rsi)
leaq 80(%rsp), %rbx
movq %rax, (%rbx)
movq %rcx, 8(%rbx)
movq %rsi, 16(%rbx)
leaq 64(%rsp), %r14
leaq 48(%rsp), %r15
leaq 24(%rsp), %r12
leaq 16(%rsp), %r13
movq %r14, %rdi
movq %r15, %rsi
movq %r12, %rdx
movq %r13, %rcx
callq __hipPopCallConfiguration
movq (%r14), %rsi
movl 8(%r14), %edx
movq (%r15), %rcx
movl 8(%r15), %r8d
movl $_Z6MataddPcS_i, %edi
movq %rbx, %r9
pushq (%r13)
.cfi_adjust_cfa_offset 8
pushq (%r12)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $128, %rsp
.cfi_adjust_cfa_offset -128
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z21__device_stub__MataddPcS_i, .Lfunc_end0-_Z21__device_stub__MataddPcS_i
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI1_0:
.quad 0x3ff0000000000000 # double 1
.text
.globl main
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $72, %rsp
.cfi_def_cfa_offset 128
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movabsq $4294967296, %rax # imm = 0x100000000
leaq 16(%rax), %r15
xorl %ebp, %ebp
.LBB1_1: # =>This Loop Header: Depth=1
# Child Loop BB1_3 Depth 2
movsd .LCPI1_0(%rip), %xmm0 # xmm0 = mem[0],zero
movl %ebp, %edi
callq ldexp@PLT
cvttsd2si %xmm0, %r14d
movslq %r14d, %rbx
movl $.L.str, %edi
movl %ebx, %esi
xorl %eax, %eax
callq printf
leaq 64(%rsp), %rdi
callq hipEventCreate
leaq 40(%rsp), %rdi
callq hipEventCreate
leaq 56(%rsp), %rdi
callq hipEventCreate
leaq 32(%rsp), %rdi
callq hipEventCreate
leaq 24(%rsp), %rdi
movq %rbx, %rsi
xorl %edx, %edx
callq hipHostMalloc
leaq 48(%rsp), %rdi
movq %rbx, %rsi
xorl %edx, %edx
callq hipHostMalloc
testl %ebx, %ebx
jle .LBB1_4
# %bb.2: # %.lr.ph.preheader
# in Loop: Header=BB1_1 Depth=1
movl %r14d, %r12d
xorl %r13d, %r13d
.LBB1_3: # %.lr.ph
# Parent Loop BB1_1 Depth=1
# => This Inner Loop Header: Depth=2
callq rand
cltq
imulq $1717986919, %rax, %rcx # imm = 0x66666667
movq %rcx, %rdx
shrq $63, %rdx
sarq $35, %rcx
addl %edx, %ecx
shll $2, %ecx
leal (%rcx,%rcx,4), %ecx
subl %ecx, %eax
addb $-10, %al
movq 24(%rsp), %rcx
movb %al, (%rcx,%r13)
incq %r13
cmpq %r13, %r12
jne .LBB1_3
.LBB1_4: # %._crit_edge
# in Loop: Header=BB1_1 Depth=1
leaq 16(%rsp), %rdi
movq %rbx, %rsi
callq hipMalloc
leaq 8(%rsp), %rdi
movq %rbx, %rsi
callq hipMalloc
movq 64(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 16(%rsp), %rdi
movq 24(%rsp), %rsi
movq %rbx, %rdx
movl $1, %ecx
callq hipMemcpy
movq 40(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 40(%rsp), %rdi
callq hipEventSynchronize
leal 15(%r14), %eax
leal 30(%r14), %r12d
testl %eax, %eax
cmovnsl %eax, %r12d
sarl $4, %r12d
movq 56(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movabsq $4294967296, %rax # imm = 0x100000000
orq %rax, %r12
movq %r12, %rdi
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_6
# %bb.5: # in Loop: Header=BB1_1 Depth=1
movq 16(%rsp), %rdi
movq 8(%rsp), %rsi
movl %r14d, %edx
callq _Z21__device_stub__MataddPcS_i
.LBB1_6: # in Loop: Header=BB1_1 Depth=1
movq 48(%rsp), %rdi
movq 8(%rsp), %rsi
movq %rbx, %rdx
movl $2, %ecx
callq hipMemcpy
movq 32(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 32(%rsp), %rdi
callq hipEventSynchronize
movq 64(%rsp), %rsi
movq 40(%rsp), %rdx
leaq 4(%rsp), %rdi
callq hipEventElapsedTime
movq 56(%rsp), %rsi
movq 32(%rsp), %rdx
movq %rsp, %rdi
callq hipEventElapsedTime
cvtss2sd 4(%rsp), %xmm0
movl $.L.str.1, %edi
movl %ebp, %esi
movb $1, %al
callq printf
xorps %xmm0, %xmm0
cvtss2sd (%rsp), %xmm0
movl $.L.str.2, %edi
movl %ebp, %esi
movb $1, %al
callq printf
movss 4(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
addss (%rsp), %xmm0
cvtss2sd %xmm0, %xmm0
movl $.L.str.3, %edi
movl %ebp, %esi
movb $1, %al
callq printf
movq 24(%rsp), %rdi
callq hipFree
movq 48(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
incl %ebp
cmpl $26, %ebp
jne .LBB1_1
# %bb.7:
xorl %eax, %eax
addq $72, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, %rdi
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6MataddPcS_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6MataddPcS_i,@object # @_Z6MataddPcS_i
.section .rodata,"a",@progbits
.globl _Z6MataddPcS_i
.p2align 3, 0x0
_Z6MataddPcS_i:
.quad _Z21__device_stub__MataddPcS_i
.size _Z6MataddPcS_i, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "\n The value of N is %d"
.size .L.str, 23
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "\n The Host to Device time for location A in microseconds for 2 to power %d is %f respectively \n"
.size .L.str.1, 97
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "\n The Device to Host time for location B in microseconds for 2 to power %d is %f respectively \n"
.size .L.str.2, 97
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "\n The total data transfer time in microseconds for 2 to power %d is %f respectively \n"
.size .L.str.3, 87
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z6MataddPcS_i"
.size .L__unnamed_1, 15
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__MataddPcS_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6MataddPcS_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
```
| 4,162 | 4,437 |
214 |
Convert the following CUDA device assembly code to AMD device assembly:
```cudaasm
code for sm_80
```
|
```amdasm
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object ; @__hip_cuid_
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0 ; 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
```
| 24 | 306 |
215 |
Convert the following CUDA host assembly code to AMD host assembly:
```cudaasm
.file "tmpxft_0013957a_00000000-6_test_cuda.cudafe1.cpp"
.text
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "ran1 = %e\nran2 = %e\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $32, %rsp
.cfi_def_cfa_offset 48
movq %fs:40, %rax
movq %rax, 24(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rdi
movl $100, %esi
call curandCreateGenerator@PLT
movl $1234, %esi
movq 8(%rsp), %rdi
call curandSetPseudoRandomGeneratorSeed@PLT
movl $8, %edi
call malloc@PLT
movq %rax, %rbx
leaq 16(%rsp), %rdi
movl $8, %esi
call cudaMalloc@PLT
movl $2, %edx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call curandGenerateUniform@PLT
movl $2, %ecx
movl $8, %edx
movq 16(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
pxor %xmm0, %xmm0
cvtss2sd (%rbx), %xmm0
pxor %xmm1, %xmm1
cvtss2sd 4(%rbx), %xmm1
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $2, %eax
call __printf_chk@PLT
movq 8(%rsp), %rdi
call curandDestroyGenerator@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq %rbx, %rdi
call free@PLT
movq 24(%rsp), %rax
subq %fs:40, %rax
jne .L6
movl $0, %eax
addq $32, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L6:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
```
|
```amdasm
.text
.file "test_cuda.hip"
.globl main # -- Begin function main
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $16, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 8(%rsp), %rbx
movq %rbx, %rdi
movl $400, %esi # imm = 0x190
callq hiprandCreateGenerator
movq (%rbx), %rdi
movl $1234, %esi # imm = 0x4D2
callq hiprandSetPseudoRandomGeneratorSeed
movl $8, %edi
callq malloc
movq %rax, %r14
movq %rsp, %r15
movl $8, %esi
movq %r15, %rdi
callq hipMalloc
movq (%rbx), %rdi
movq (%r15), %rsi
movl $2, %edx
callq hiprandGenerateUniform
movq (%r15), %rsi
movl $8, %edx
movq %r14, %rdi
movl $2, %ecx
callq hipMemcpy
cvtss2sd (%r14), %xmm0
cvtss2sd 4(%r14), %xmm1
movl $.L.str, %edi
movb $2, %al
callq printf
movq (%rbx), %rdi
callq hiprandDestroyGenerator
movq (%r15), %rdi
callq hipFree
movq %r14, %rdi
callq free
xorl %eax, %eax
addq $16, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "ran1 = %e\nran2 = %e\n"
.size .L.str, 21
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
```
| 1,394 | 871 |
218 |
Convert the following CUDA device assembly code to AMD device assembly:
```cudaasm
code for sm_80
Function : _Z8multMatsPfS_S_iii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
MOV R1, c[0x0][0x28] ;
S2R R0, SR_CTAID.X ;
S2R R5, SR_TID.X ;
S2R R3, SR_CTAID.Y ;
S2R R2, SR_TID.Y ;
IMAD R0, R0, c[0x0][0x0], R5 ;
ISETP.GE.AND P0, PT, R0, c[0x0][0x180], PT ;
IMAD R3, R3, c[0x0][0x4], R2 ;
ISETP.GE.OR P0, PT, R3, c[0x0][0x178], P0 ;
@P0 EXIT ;
MOV R2, c[0x0][0x17c] ;
ULDC.64 UR4, c[0x0][0x118] ;
HFMA2.MMA R24, -RZ, RZ, 0, 0 ;
ISETP.GE.AND P0, PT, R2, 0x1, PT ;
@!P0 BRA 0xc00 ;
IADD3 R4, R2.reuse, -0x1, RZ ;
LOP3.LUT R5, R2, 0x3, RZ, 0xc0, !PT ;
ISETP.GE.U32.AND P0, PT, R4, 0x3, PT ;
MOV R24, RZ ;
MOV R4, RZ ;
@!P0 BRA 0xb00 ;
IADD3 R6, -R5, c[0x0][0x17c], RZ ;
HFMA2.MMA R9, -RZ, RZ, 0, 2.384185791015625e-07 ;
ULDC.64 UR6, c[0x0][0x160] ;
HFMA2.MMA R4, -RZ, RZ, 0, 0 ;
ISETP.GT.AND P0, PT, R6, RZ, PT ;
IMAD R7, R3, c[0x0][0x17c], RZ ;
MOV R24, RZ ;
IMAD.WIDE R8, R0, R9, c[0x0][0x168] ;
@!P0 BRA 0x970 ;
ISETP.GT.AND P1, PT, R6, 0xc, PT ;
PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ;
@!P1 BRA 0x6b0 ;
PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ;
MOV R14, UR6 ;
LDG.E R11, [R8.64] ;
MOV R15, UR7 ;
IMAD.WIDE R14, R7, 0x4, R14 ;
LDG.E R10, [R14.64] ;
IMAD.WIDE R8, R2, 0x4, R8 ;
LDG.E R18, [R14.64+0x4] ;
IMAD.WIDE R22, R2.reuse, 0x4, R8 ;
LDG.E R19, [R8.64] ;
LDG.E R28, [R22.64] ;
IMAD.WIDE R26, R2, 0x4, R22 ;
LDG.E R29, [R14.64+0x8] ;
IMAD.WIDE R12, R2.reuse, 0x4, R26 ;
LDG.E R16, [R26.64] ;
LDG.E R17, [R14.64+0xc] ;
LDG.E R20, [R14.64+0x10] ;
LDG.E R21, [R12.64] ;
LDG.E R8, [R14.64+0x14] ;
LDG.E R26, [R14.64+0x1c] ;
IMAD.WIDE R12, R2, 0x4, R12 ;
LDG.E R9, [R12.64] ;
IMAD.WIDE R22, R2, 0x4, R12 ;
FFMA R12, R11, R10, R24 ;
LDG.E R10, [R14.64+0x18] ;
IMAD.WIDE R24, R2, 0x4, R22 ;
LDG.E R11, [R22.64] ;
LDG.E R27, [R24.64] ;
FFMA R12, R19, R18, R12 ;
IMAD.WIDE R18, R2, 0x4, R24 ;
LDG.E R23, [R14.64+0x20] ;
FFMA R28, R28, R29, R12 ;
IMAD.WIDE R12, R2, 0x4, R18 ;
LDG.E R25, [R14.64+0x24] ;
FFMA R28, R16, R17, R28 ;
LDG.E R18, [R18.64] ;
IMAD.WIDE R16, R2, 0x4, R12 ;
LDG.E R12, [R12.64] ;
FFMA R28, R21, R20, R28 ;
LDG.E R22, [R16.64] ;
IMAD.WIDE R20, R2, 0x4, R16 ;
LDG.E R29, [R14.64+0x28] ;
LDG.E R19, [R14.64+0x2c] ;
LDG.E R24, [R14.64+0x30] ;
FFMA R28, R9, R8, R28 ;
IMAD.WIDE R8, R2, 0x4, R20 ;
LDG.E R20, [R20.64] ;
LDG.E R21, [R14.64+0x38] ;
FFMA R28, R11, R10, R28 ;
IMAD.WIDE R10, R2, 0x4, R8 ;
LDG.E R8, [R8.64] ;
FFMA R13, R27, R26, R28 ;
IMAD.WIDE R26, R2.reuse, 0x4, R10 ;
LDG.E R10, [R10.64] ;
LDG.E R9, [R14.64+0x34] ;
IMAD.WIDE R16, R2, 0x4, R26 ;
LDG.E R28, [R26.64] ;
LDG.E R11, [R16.64] ;
LDG.E R26, [R14.64+0x3c] ;
FFMA R13, R18, R23, R13 ;
FFMA R12, R12, R25, R13 ;
IADD3 R6, R6, -0x10, RZ ;
FFMA R12, R22, R29, R12 ;
ISETP.GT.AND P1, PT, R6, 0xc, PT ;
FFMA R19, R20, R19, R12 ;
UIADD3 UR6, UP0, UR6, 0x40, URZ ;
IADD3 R4, R4, 0x10, RZ ;
UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ;
FFMA R8, R8, R24, R19 ;
FFMA R8, R10, R9, R8 ;
FFMA R8, R28, R21, R8 ;
FFMA R24, R11, R26, R8 ;
IMAD.WIDE R8, R2, 0x4, R16 ;
@P1 BRA 0x220 ;
ISETP.GT.AND P1, PT, R6, 0x4, PT ;
@!P1 BRA 0x950 ;
IMAD.WIDE R16, R2, 0x4, R8 ;
MOV R10, UR6 ;
LDG.E R23, [R8.64] ;
MOV R11, UR7 ;
IMAD.WIDE R12, R2.reuse, 0x4, R16 ;
LDG.E R16, [R16.64] ;
IMAD.WIDE R10, R7, 0x4, R10 ;
LDG.E R26, [R12.64] ;
IMAD.WIDE R14, R2.reuse, 0x4, R12 ;
LDG.E R22, [R10.64] ;
LDG.E R25, [R10.64+0x4] ;
IMAD.WIDE R18, R2, 0x4, R14 ;
LDG.E R27, [R10.64+0x8] ;
IMAD.WIDE R20, R2.reuse, 0x4, R18 ;
LDG.E R14, [R14.64] ;
LDG.E R29, [R10.64+0xc] ;
IMAD.WIDE R8, R2, 0x4, R20 ;
LDG.E R18, [R18.64] ;
LDG.E R28, [R10.64+0x10] ;
IMAD.WIDE R12, R2, 0x4, R8 ;
LDG.E R20, [R20.64] ;
LDG.E R15, [R10.64+0x14] ;
LDG.E R17, [R8.64] ;
LDG.E R19, [R10.64+0x1c] ;
LDG.E R8, [R10.64+0x18] ;
LDG.E R9, [R12.64] ;
UIADD3 UR6, UP0, UR6, 0x20, URZ ;
PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ;
IADD3 R4, R4, 0x8, RZ ;
IADD3 R6, R6, -0x8, RZ ;
UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ;
FFMA R22, R23, R22, R24 ;
FFMA R16, R16, R25, R22 ;
FFMA R16, R26, R27, R16 ;
FFMA R29, R14, R29, R16 ;
FFMA R18, R18, R28, R29 ;
FFMA R15, R20, R15, R18 ;
FFMA R8, R17, R8, R15 ;
FFMA R24, R9, R19, R8 ;
IMAD.WIDE R8, R2, 0x4, R12 ;
ISETP.NE.OR P0, PT, R6, RZ, P0 ;
@!P0 BRA 0xb00 ;
MOV R12, UR6 ;
IMAD.WIDE R10, R2, 0x4, R8 ;
MOV R13, UR7 ;
LDG.E R9, [R8.64] ;
IMAD.WIDE R12, R7, 0x4, R12 ;
IMAD.WIDE R14, R2.reuse, 0x4, R10 ;
LDG.E R18, [R12.64] ;
LDG.E R11, [R10.64] ;
IMAD.WIDE R16, R2, 0x4, R14 ;
LDG.E R19, [R12.64+0x4] ;
LDG.E R21, [R14.64] ;
LDG.E R20, [R12.64+0x8] ;
LDG.E R22, [R12.64+0xc] ;
LDG.E R23, [R16.64] ;
IADD3 R6, R6, -0x4, RZ ;
ISETP.NE.AND P0, PT, R6, RZ, PT ;
UIADD3 UR6, UP0, UR6, 0x10, URZ ;
IADD3 R4, R4, 0x4, RZ ;
UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ;
FFMA R18, R9, R18, R24 ;
FFMA R18, R11, R19, R18 ;
IMAD.WIDE R8, R2, 0x4, R16 ;
FFMA R18, R21, R20, R18 ;
FFMA R24, R23, R22, R18 ;
@P0 BRA 0x970 ;
ISETP.NE.AND P0, PT, R5, RZ, PT ;
@!P0 BRA 0xc00 ;
HFMA2.MMA R9, -RZ, RZ, 0, 2.384185791015625e-07 ;
IMAD R6, R3, c[0x0][0x17c], R4 ;
IMAD R4, R4, c[0x0][0x17c], R0 ;
IMAD.WIDE R6, R6, R9, c[0x0][0x160] ;
IMAD.WIDE R8, R4, R9, c[0x0][0x168] ;
LDG.E R11, [R8.64] ;
LDG.E R4, [R6.64] ;
IADD3 R5, R5, -0x1, RZ ;
ISETP.NE.AND P0, PT, R5, RZ, PT ;
IMAD.WIDE R8, R2, 0x4, R8 ;
IADD3 R6, P1, R6, 0x4, RZ ;
IADD3.X R7, RZ, R7, RZ, P1, !PT ;
FFMA R24, R11, R4, R24 ;
@P0 BRA 0xb70 ;
MOV R2, 0x4 ;
IMAD R3, R3, c[0x0][0x180], R0 ;
IMAD.WIDE R2, R3, R2, c[0x0][0x170] ;
STG.E [R2.64], R24 ;
EXIT ;
BRA 0xc50;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
```
|
```amdasm
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z8multMatsPfS_S_iii ; -- Begin function _Z8multMatsPfS_S_iii
.globl _Z8multMatsPfS_S_iii
.p2align 8
.type _Z8multMatsPfS_S_iii,@function
_Z8multMatsPfS_S_iii: ; @_Z8multMatsPfS_S_iii
; %bb.0:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x34
s_load_b128 s[4:7], s[0:1], 0x18
v_bfe_u32 v2, v0, 10, 10
v_and_b32_e32 v3, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s3, s2, 16
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[0:1], null, s15, s3, v[2:3]
v_mad_u64_u32 v[1:2], null, s14, s2, v[3:4]
v_cmp_gt_i32_e32 vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_i32_e64 s2, s6, v1
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_6
; %bb.1: ; %.preheader
s_clause 0x1
s_load_b128 s[8:11], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
s_cmp_lt_i32 s5, 1
s_cbranch_scc1 .LBB0_4
; %bb.2: ; %.lr.ph
v_mul_lo_u32 v2, v0, s5
v_mov_b32_e32 v6, 0
v_mov_b32_e32 v4, v1
s_mov_b32 s2, s5
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s8, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s9, v3, vcc_lo
.LBB0_3: ; =>This Inner Loop Header: Depth=1
v_ashrrev_i32_e32 v5, 31, v4
s_add_i32 s2, s2, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_cmp_eq_u32 s2, 0
v_lshlrev_b64 v[7:8], 2, v[4:5]
v_add_nc_u32_e32 v4, s5, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v7, vcc_lo, s10, v7
v_add_co_ci_u32_e32 v8, vcc_lo, s11, v8, vcc_lo
global_load_b32 v5, v[2:3], off
global_load_b32 v7, v[7:8], off
v_add_co_u32 v2, vcc_lo, v2, 4
v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v6, v5, v7
s_cbranch_scc0 .LBB0_3
s_branch .LBB0_5
.LBB0_4:
v_mov_b32_e32 v6, 0
.LBB0_5: ; %Flow54
v_mad_u64_u32 v[2:3], null, v0, s6, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[0:1], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v6, off
.LBB0_6:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z8multMatsPfS_S_iii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z8multMatsPfS_S_iii, .Lfunc_end0-_Z8multMatsPfS_S_iii
; -- End function
.section .AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 344
; NumSgprs: 18
; NumVgprs: 9
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 9
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object ; @__hip_cuid_
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0 ; 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z8multMatsPfS_S_iii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z8multMatsPfS_S_iii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
```
| 3,674 | 3,378 |
219 |
Convert the following CUDA host assembly code to AMD host assembly:
```cudaasm
.file "tmpxft_0002e128_00000000-6_simple_mult.cudafe1.cpp"
.text
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z34__device_stub__Z8multMatsPfS_S_iiiPfS_S_iii
.type _Z34__device_stub__Z8multMatsPfS_S_iiiPfS_S_iii, @function
_Z34__device_stub__Z8multMatsPfS_S_iiiPfS_S_iii:
.LFB2082:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z8multMatsPfS_S_iii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z34__device_stub__Z8multMatsPfS_S_iiiPfS_S_iii, .-_Z34__device_stub__Z8multMatsPfS_S_iiiPfS_S_iii
.globl _Z8multMatsPfS_S_iii
.type _Z8multMatsPfS_S_iii, @function
_Z8multMatsPfS_S_iii:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z34__device_stub__Z8multMatsPfS_S_iiiPfS_S_iii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z8multMatsPfS_S_iii, .-_Z8multMatsPfS_S_iii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "CUDA kernel launch with %d blocks of %d threads\n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "Inactive Threads %d \n"
.section .rodata.str1.8
.align 8
.LC4:
.string "Elapsed Time: %f milliseconds\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $80, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
leaq 32(%rsp), %rdi
call cudaEventCreate@PLT
leaq 40(%rsp), %rdi
call cudaEventCreate@PLT
movl $1048576, %edi
call malloc@PLT
movq %rax, %rbx
movl $1048576, %edi
call malloc@PLT
movq %rax, %rbp
movl $1048576, %edi
call malloc@PLT
movq %rax, %r12
movq %rbx, %rax
leaq 1048576(%rbx), %rdx
movss .LC0(%rip), %xmm0
.L12:
movss %xmm0, (%rax)
addq $4, %rax
cmpq %rdx, %rax
jne .L12
movq %rbp, %rax
leaq 1048576(%rbp), %rdx
movss .LC0(%rip), %xmm0
.L13:
movss %xmm0, (%rax)
addq $4, %rax
cmpq %rdx, %rax
jne .L13
leaq 8(%rsp), %rdi
movl $1048576, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $1048576, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $1048576, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $1048576, %edx
movq %rbx, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $1048576, %edx
movq %rbp, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $32, %ecx
movl $8192, %edx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %edx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %esi
movq 32(%rsp), %rdi
call cudaEventRecord@PLT
movl $32, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $8192, 48(%rsp)
movl $1, 52(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 60(%rsp), %rdx
movl $1, %ecx
movq 48(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L19
.L14:
call cudaThreadSynchronize@PLT
movl $0, %esi
movq 40(%rsp), %rdi
call cudaEventRecord@PLT
movl $2, %ecx
movl $1048576, %edx
movq 24(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
movq 40(%rsp), %rdi
call cudaEventSynchronize@PLT
movl $0x00000000, 60(%rsp)
leaq 60(%rsp), %rdi
movq 40(%rsp), %rdx
movq 32(%rsp), %rsi
call cudaEventElapsedTime@PLT
pxor %xmm0, %xmm0
cvtss2sd 60(%rsp), %xmm0
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 32(%rsp), %rdi
call cudaEventDestroy@PLT
movq 40(%rsp), %rdi
call cudaEventDestroy@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq %rbx, %rdi
call free@PLT
movq %rbp, %rdi
call free@PLT
movq %r12, %rdi
call free@PLT
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L20
movl $0, %eax
addq $80, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
movl $512, %r9d
movl $512, %r8d
movl $512, %ecx
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z34__device_stub__Z8multMatsPfS_S_iiiPfS_S_iii
jmp .L14
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC5:
.string "_Z8multMatsPfS_S_iii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _Z8multMatsPfS_S_iii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC0:
.long 1065353216
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
```
|
```amdasm
.text
.file "simple_mult.hip"
.globl _Z23__device_stub__multMatsPfS_S_iii # -- Begin function _Z23__device_stub__multMatsPfS_S_iii
.type _Z23__device_stub__multMatsPfS_S_iii,@function
_Z23__device_stub__multMatsPfS_S_iii: # @_Z23__device_stub__multMatsPfS_S_iii
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $144, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 56(%rsp), %rax
movq %rdi, (%rax)
leaq 48(%rsp), %rdi
movq %rsi, (%rdi)
leaq 40(%rsp), %rsi
movq %rdx, (%rsi)
leaq 20(%rsp), %rdx
movl %ecx, (%rdx)
leaq 16(%rsp), %rcx
movl %r8d, (%rcx)
leaq 12(%rsp), %r8
movl %r9d, (%r8)
leaq 96(%rsp), %rbx
movq %rax, (%rbx)
movq %rdi, 8(%rbx)
movq %rsi, 16(%rbx)
movq %rdx, 24(%rbx)
movq %rcx, 32(%rbx)
movq %r8, 40(%rbx)
leaq 80(%rsp), %r14
leaq 64(%rsp), %r15
leaq 32(%rsp), %r12
leaq 24(%rsp), %r13
movq %r14, %rdi
movq %r15, %rsi
movq %r12, %rdx
movq %r13, %rcx
callq __hipPopCallConfiguration
movq (%r14), %rsi
movl 8(%r14), %edx
movq (%r15), %rcx
movl 8(%r15), %r8d
movl $_Z8multMatsPfS_S_iii, %edi
movq %rbx, %r9
pushq (%r13)
.cfi_adjust_cfa_offset 8
pushq (%r12)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $160, %rsp
.cfi_adjust_cfa_offset -160
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z23__device_stub__multMatsPfS_S_iii, .Lfunc_end0-_Z23__device_stub__multMatsPfS_S_iii
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $48, %rsp
.cfi_def_cfa_offset 96
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 8(%rsp), %rdi
callq hipEventCreate
movq %rsp, %rdi
callq hipEventCreate
movl $1048576, %edi # imm = 0x100000
callq malloc
movq %rax, %rbx
movl $1048576, %edi # imm = 0x100000
callq malloc
movq %rax, %r14
movl $1048576, %edi # imm = 0x100000
callq malloc
movq %rax, %r15
xorl %eax, %eax
.LBB1_1: # =>This Inner Loop Header: Depth=1
movl $1065353216, (%rbx,%rax,4) # imm = 0x3F800000
incq %rax
cmpq $262144, %rax # imm = 0x40000
jne .LBB1_1
# %bb.2: # %.preheader.preheader
xorl %eax, %eax
.LBB1_3: # %.preheader
# =>This Inner Loop Header: Depth=1
movl $1065353216, (%r14,%rax,4) # imm = 0x3F800000
incq %rax
cmpq $262144, %rax # imm = 0x40000
jne .LBB1_3
# %bb.4:
leaq 32(%rsp), %r12
movl $1048576, %esi # imm = 0x100000
movq %r12, %rdi
callq hipMalloc
leaq 24(%rsp), %r13
movl $1048576, %esi # imm = 0x100000
movq %r13, %rdi
callq hipMalloc
leaq 16(%rsp), %rdi
movl $1048576, %esi # imm = 0x100000
callq hipMalloc
movq (%r12), %rdi
movl $1048576, %edx # imm = 0x100000
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq (%r13), %rdi
movl $1048576, %edx # imm = 0x100000
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movl $.L.str, %edi
movl $8192, %esi # imm = 0x2000
movl $32, %edx
xorl %eax, %eax
callq printf
movl $.L.str.1, %edi
xorl %esi, %esi
xorl %eax, %eax
callq printf
movq 8(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movabsq $4294967328, %rdx # imm = 0x100000020
leaq 8160(%rdx), %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_6
# %bb.5:
movq 32(%rsp), %rdi
movq 24(%rsp), %rsi
movq 16(%rsp), %rdx
movl $512, %ecx # imm = 0x200
movl $512, %r8d # imm = 0x200
movl $512, %r9d # imm = 0x200
callq _Z23__device_stub__multMatsPfS_S_iii
.LBB1_6:
callq hipDeviceSynchronize
movq (%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 16(%rsp), %rsi
movl $1048576, %edx # imm = 0x100000
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
movq (%rsp), %rdi
callq hipEventSynchronize
leaq 44(%rsp), %r12
movl $0, (%r12)
movq 8(%rsp), %rsi
movq (%rsp), %rdx
movq %r12, %rdi
callq hipEventElapsedTime
cvtss2sd (%r12), %xmm0
movl $.L.str.2, %edi
movb $1, %al
callq printf
movq 8(%rsp), %rdi
callq hipEventDestroy
movq (%rsp), %rdi
callq hipEventDestroy
movq 32(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
xorl %eax, %eax
addq $48, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, %rdi
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8multMatsPfS_S_iii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z8multMatsPfS_S_iii,@object # @_Z8multMatsPfS_S_iii
.section .rodata,"a",@progbits
.globl _Z8multMatsPfS_S_iii
.p2align 3, 0x0
_Z8multMatsPfS_S_iii:
.quad _Z23__device_stub__multMatsPfS_S_iii
.size _Z8multMatsPfS_S_iii, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "CUDA kernel launch with %d blocks of %d threads\n"
.size .L.str, 49
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Inactive Threads %d \n"
.size .L.str.1, 22
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Elapsed Time: %f milliseconds\n"
.size .L.str.2, 31
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z8multMatsPfS_S_iii"
.size .L__unnamed_1, 21
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z23__device_stub__multMatsPfS_S_iii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z8multMatsPfS_S_iii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
```
| 3,819 | 4,153 |
220 |
Convert the following CUDA device assembly code to AMD device assembly:
```cudaasm
code for sm_80
Function : _Z16minimum_distancePfS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
MOV R1, c[0x0][0x28] ;
S2R R7, SR_TID.Y ;
S2UR UR4, SR_CTAID.Y ;
IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x170] ;
MOV R3, c[0x0][0x174] ;
ULDC.64 UR8, c[0x0][0x118] ;
ULDC UR5, c[0x0][0x4] ;
ISETP.NE.AND P0, PT, R7, RZ, PT ;
UIMAD UR4, UR4, UR5, URZ ;
IADD3 R4, R7, UR4, RZ ;
ISETP.GE.AND P1, PT, R4, c[0x0][0x178], PT ;
@!P0 IMAD.MOV.U32 R5, RZ, RZ, 0x41200000 ;
@!P0 STG.E [R2.64], R5 ;
MEMBAR.SC.GPU ;
ERRBAR;
CCTL.IVALL ;
@!P1 BRA 0x2a0 ;
ULDC UR5, c[0x0][0x4] ;
USHF.R.U32.HI UR5, URZ, 0x1, UR5 ;
ISETP.NE.AND P1, PT, RZ, UR5, PT ;
@!P1 BRA 0x230 ;
MOV R0, UR5 ;
IMAD.SHL.U32 R5, R7, 0x4, RZ ;
ISETP.GE.U32.AND P1, PT, R7, R0, PT ;
@P1 BRA 0x1e0 ;
LEA R6, R0, R5, 0x2 ;
LDS R4, [R7.X4] ;
LDS R6, [R6] ;
FSETP.GT.AND P1, PT, R4, R6, PT ;
@P1 STS [R7.X4], R6 ;
SHF.R.U32.HI R0, RZ, 0x1, R0 ;
WARPSYNC 0xffffffff ;
BAR.SYNC.DEFER_BLOCKING 0x0 ;
ISETP.NE.AND P1, PT, R0, RZ, PT ;
@P1 BRA 0x170 ;
@P0 EXIT ;
LDG.E R0, [R2.64] ;
LDS R5, [RZ] ;
FSETP.GT.AND P0, PT, R0, R5, PT ;
@!P0 EXIT ;
STG.E [R2.64], R5 ;
EXIT ;
IADD3 R6, R4, 0x1, RZ ;
ISETP.GE.AND P0, PT, R6, c[0x0][0x178], PT ;
@P0 EXIT ;
LOP3.LUT R2, RZ, UR4, RZ, 0x33, !PT ;
S2R R0, SR_TID.X ;
UMOV UR5, 0x2 ;
IMAD.MOV.U32 R11, RZ, RZ, 0x4 ;
IADD3 R2, -R7, c[0x0][0x178], R2 ;
ULDC UR6, c[0x0][0x178] ;
UIADD3 UR5, -UR4, UR6, -UR5 ;
LOP3.LUT P0, R12, R2, 0x3, RZ, 0xc0, !PT ;
IMAD.WIDE R2, R4, R11, c[0x0][0x160] ;
IADD3 R7, -R7, UR5, RZ ;
IMAD.WIDE R4, R4, R11, c[0x0][0x168] ;
@!P0 BRA 0x5b0 ;
IMAD.WIDE R8, R6, R11, c[0x0][0x168] ;
IMAD.WIDE R10, R6, R11, c[0x0][0x160] ;
LDG.E R15, [R4.64] ;
LDG.E R16, [R8.64] ;
LDG.E R14, [R10.64] ;
LDG.E R13, [R2.64] ;
BSSY B0, 0x500 ;
FADD R15, -R15, R16 ;
FADD R13, -R13, R14 ;
FMUL R14, R15, R15 ;
FFMA R18, R13, R13, R14 ;
MUFU.RSQ R15, R18 ;
IADD3 R13, R18, -0xd000000, RZ ;
ISETP.GT.U32.AND P0, PT, R13, 0x727fffff, PT ;
@!P0 BRA 0x4b0 ;
MOV R19, 0x4a0 ;
CALL.REL.NOINC 0xd20 ;
BRA 0x4f0 ;
FMUL.FTZ R13, R18, R15 ;
FMUL.FTZ R15, R15, 0.5 ;
FFMA R14, -R13, R13, R18 ;
FFMA R13, R14, R15, R13 ;
BSYNC B0 ;
IADD3 R12, R12, -0x1, RZ ;
STS [R0.X4], R13 ;
WARPSYNC 0xffffffff ;
BAR.SYNC.DEFER_BLOCKING 0x0 ;
ISETP.NE.AND P0, PT, R12, RZ, PT ;
IADD3 R8, P1, R8, 0x4, RZ ;
IADD3 R10, P2, R10, 0x4, RZ ;
IADD3 R6, R6, 0x1, RZ ;
IADD3.X R9, RZ, R9, RZ, P1, !PT ;
IADD3.X R11, RZ, R11, RZ, P2, !PT ;
@P0 BRA 0x3b0 ;
ISETP.GE.U32.AND P0, PT, R7, 0x3, PT ;
@!P0 EXIT ;
IMAD.MOV.U32 R9, RZ, RZ, 0x4 ;
IMAD.WIDE R8, R6, R9, c[0x2][0x0] ;
IADD3 R10, P0, R8.reuse, c[0x0][0x160], RZ ;
IADD3 R8, P1, R8, c[0x0][0x168], RZ ;
IADD3.X R11, R9.reuse, c[0x0][0x164], RZ, P0, !PT ;
IADD3.X R9, R9, c[0x0][0x16c], RZ, P1, !PT ;
LDG.E R13, [R4.64] ;
LDG.E R14, [R8.64+-0x8] ;
LDG.E R7, [R2.64] ;
LDG.E R12, [R10.64+-0x8] ;
BSSY B0, 0x790 ;
FADD R13, -R13, R14 ;
FADD R7, -R7, R12 ;
FMUL R12, R13, R13 ;
FFMA R18, R7, R7, R12 ;
MUFU.RSQ R13, R18 ;
IADD3 R7, R18, -0xd000000, RZ ;
ISETP.GT.U32.AND P0, PT, R7, 0x727fffff, PT ;
@!P0 BRA 0x740 ;
MOV R19, 0x720 ;
CALL.REL.NOINC 0xd20 ;
MOV R7, R13 ;
BRA 0x780 ;
FMUL.FTZ R7, R18, R13 ;
FMUL.FTZ R13, R13, 0.5 ;
FFMA R12, -R7, R7, R18 ;
FFMA R7, R12, R13, R7 ;
BSYNC B0 ;
STS [R0.X4], R7 ;
WARPSYNC 0xffffffff ;
BAR.SYNC.DEFER_BLOCKING 0x0 ;
LDG.E R14, [R4.64] ;
LDG.E R15, [R8.64+-0x4] ;
LDG.E R12, [R2.64] ;
LDG.E R13, [R10.64+-0x4] ;
BSSY B0, 0x940 ;
FADD R14, -R14, R15 ;
FADD R12, -R12, R13 ;
FMUL R13, R14, R14 ;
FFMA R18, R12, R12, R13 ;
MUFU.RSQ R13, R18 ;
IADD3 R7, R18, -0xd000000, RZ ;
ISETP.GT.U32.AND P0, PT, R7, 0x727fffff, PT ;
@!P0 BRA 0x8f0 ;
BSSY B1, 0x8d0 ;
MOV R19, 0x8c0 ;
CALL.REL.NOINC 0xd20 ;
BSYNC B1 ;
MOV R7, R13 ;
BRA 0x930 ;
FMUL.FTZ R7, R18, R13 ;
FMUL.FTZ R13, R13, 0.5 ;
FFMA R12, -R7, R7, R18 ;
FFMA R7, R12, R13, R7 ;
BSYNC B0 ;
STS [R0.X4], R7 ;
BAR.SYNC.DEFER_BLOCKING 0x0 ;
LDG.E R14, [R4.64] ;
LDG.E R15, [R8.64] ;
LDG.E R12, [R2.64] ;
LDG.E R13, [R10.64] ;
BSSY B0, 0xae0 ;
FADD R14, -R14, R15 ;
FADD R12, -R12, R13 ;
FMUL R13, R14, R14 ;
FFMA R18, R12, R12, R13 ;
MUFU.RSQ R13, R18 ;
IADD3 R12, R18, -0xd000000, RZ ;
ISETP.GT.U32.AND P0, PT, R12, 0x727fffff, PT ;
@!P0 BRA 0xa90 ;
BSSY B1, 0xa70 ;
MOV R19, 0xa60 ;
CALL.REL.NOINC 0xd20 ;
BSYNC B1 ;
IMAD.MOV.U32 R7, RZ, RZ, R13 ;
BRA 0xad0 ;
FMUL.FTZ R7, R18, R13 ;
FMUL.FTZ R13, R13, 0.5 ;
FFMA R12, -R7, R7, R18 ;
FFMA R7, R12, R13, R7 ;
BSYNC B0 ;
STS [R0.X4], R7 ;
BAR.SYNC.DEFER_BLOCKING 0x0 ;
LDG.E R14, [R4.64] ;
LDG.E R15, [R8.64+0x4] ;
LDG.E R12, [R2.64] ;
LDG.E R13, [R10.64+0x4] ;
BSSY B0, 0xc80 ;
FADD R14, -R14, R15 ;
FADD R12, -R12, R13 ;
FMUL R13, R14, R14 ;
FFMA R18, R12, R12, R13 ;
MUFU.RSQ R13, R18 ;
IADD3 R12, R18, -0xd000000, RZ ;
ISETP.GT.U32.AND P0, PT, R12, 0x727fffff, PT ;
@!P0 BRA 0xc30 ;
BSSY B1, 0xc10 ;
MOV R19, 0xc00 ;
CALL.REL.NOINC 0xd20 ;
BSYNC B1 ;
MOV R7, R13 ;
BRA 0xc70 ;
FMUL.FTZ R7, R18, R13 ;
FMUL.FTZ R13, R13, 0.5 ;
FFMA R12, -R7, R7, R18 ;
FFMA R7, R12, R13, R7 ;
BSYNC B0 ;
IADD3 R6, R6, 0x4, RZ ;
STS [R0.X4], R7 ;
BAR.SYNC.DEFER_BLOCKING 0x0 ;
ISETP.GE.AND P0, PT, R6, c[0x0][0x178], PT ;
IADD3 R8, P2, R8, 0x10, RZ ;
IADD3 R10, P1, R10, 0x10, RZ ;
IMAD.X R9, RZ, RZ, R9, P2 ;
IADD3.X R11, RZ, R11, RZ, P1, !PT ;
@!P0 BRA 0x630 ;
EXIT ;
LOP3.LUT P0, RZ, R18, 0x7fffffff, RZ, 0xc0, !PT ;
@!P0 MOV R13, R18 ;
@!P0 BRA 0xe50 ;
FSETP.GEU.FTZ.AND P0, PT, R18, RZ, PT ;
@!P0 MOV R13, 0x7fffffff ;
@!P0 BRA 0xe50 ;
FSETP.GTU.FTZ.AND P0, PT, |R18|, +INF , PT ;
@P0 FADD.FTZ R13, R18, 1 ;
@P0 BRA 0xe50 ;
FSETP.NEU.FTZ.AND P0, PT, |R18|, +INF , PT ;
@P0 FFMA R14, R18, 1.84467440737095516160e+19, RZ ;
@P0 MUFU.RSQ R13, R14 ;
@P0 FMUL.FTZ R15, R14, R13 ;
@P0 FMUL.FTZ R17, R13, 0.5 ;
@P0 FADD.FTZ R16, -R15.reuse, -RZ ;
@!P0 IMAD.MOV.U32 R13, RZ, RZ, R18 ;
@P0 FFMA R16, R15, R16, R14 ;
@P0 FFMA R16, R16, R17, R15 ;
@P0 FMUL.FTZ R13, R16, 2.3283064365386962891e-10 ;
HFMA2.MMA R15, -RZ, RZ, 0, 0 ;
MOV R14, R19 ;
RET.REL.NODEC R14 0x0 ;
BRA 0xe80;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
```
|
```amdasm
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z16minimum_distancePfS_S_i ; -- Begin function _Z16minimum_distancePfS_S_i
.globl _Z16minimum_distancePfS_S_i
.p2align 8
.type _Z16minimum_distancePfS_S_i,@function
_Z16minimum_distancePfS_S_i: ; @_Z16minimum_distancePfS_S_i
; %bb.0:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b64 s[4:5], s[0:1], 0x10
v_bfe_u32 v1, v0, 10, 10
s_delay_alu instid0(VALU_DEP_1)
v_cmp_eq_u32_e32 vcc_lo, 0, v1
s_waitcnt lgkmcnt(0)
s_lshr_b32 s2, s2, 16
s_and_saveexec_b32 s3, vcc_lo
s_cbranch_execz .LBB0_2
; %bb.1:
v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v3, 0x41200000
global_store_b32 v2, v3, s[4:5]
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s3
s_load_b32 s3, s[0:1], 0x18
s_and_b32 s7, 0xffff, s2
s_mov_b32 s6, exec_lo
v_mad_u64_u32 v[2:3], null, s15, s7, v[1:2]
s_waitcnt lgkmcnt(0)
s_waitcnt_vscnt null, 0x0
buffer_gl1_inv
buffer_gl0_inv
v_cmpx_le_i32_e64 s3, v2
s_xor_b32 s6, exec_lo, s6
s_cbranch_execz .LBB0_13
; %bb.3: ; %.critedge
s_cmp_lt_u32 s7, 2
s_cbranch_scc1 .LBB0_9
; %bb.4: ; %.lr.ph41
v_lshl_add_u32 v0, v1, 2, 0
.LBB0_5: ; =>This Inner Loop Header: Depth=1
s_mov_b32 s8, s7
s_lshr_b32 s7, s7, 1
s_mov_b32 s9, exec_lo
v_cmpx_gt_u32_e64 s7, v1
s_cbranch_execz .LBB0_8
; %bb.6: ; in Loop: Header=BB0_5 Depth=1
v_lshl_add_u32 v2, s7, 2, v0
ds_load_b32 v3, v0
ds_load_b32 v2, v2
s_waitcnt lgkmcnt(0)
v_cmp_gt_f32_e64 s2, v3, v2
s_delay_alu instid0(VALU_DEP_1)
s_and_b32 exec_lo, exec_lo, s2
s_cbranch_execz .LBB0_8
; %bb.7: ; in Loop: Header=BB0_5 Depth=1
ds_store_b32 v0, v2
.LBB0_8: ; in Loop: Header=BB0_5 Depth=1
s_or_b32 exec_lo, exec_lo, s9
s_cmp_lt_u32 s8, 4
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc0 .LBB0_5
.LBB0_9: ; %._crit_edge42
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_12
; %bb.10:
v_mov_b32_e32 v0, 0
global_load_b32 v2, v0, s[4:5]
ds_load_b32 v1, v0
s_waitcnt vmcnt(0) lgkmcnt(0)
v_cmp_ngt_f32_e32 vcc_lo, v2, v1
s_cbranch_vccnz .LBB0_12
; %bb.11:
global_store_b32 v0, v1, s[4:5]
.LBB0_12: ; %Flow57
s_or_b32 exec_lo, exec_lo, s2
; implicit-def: $vgpr2_vgpr3
; implicit-def: $vgpr0
.LBB0_13: ; %Flow63
s_and_not1_saveexec_b32 s2, s6
s_cbranch_execz .LBB0_17
; %bb.14: ; %.preheader
v_add_nc_u32_e32 v8, 1, v2
s_mov_b32 s2, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s3, v8
s_cbranch_execz .LBB0_17
; %bb.15: ; %.lr.ph
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v3, 31, v2
v_and_b32_e32 v0, 0x3ff, v0
s_mov_b32 s2, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[2:3], 2, v[2:3]
v_lshl_add_u32 v9, v0, 2, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v6, vcc_lo, v2, 4
v_add_co_ci_u32_e32 v7, vcc_lo, 0, v3, vcc_lo
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v3, vcc_lo
v_add_co_u32 v2, vcc_lo, s6, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v3, vcc_lo
v_add_co_u32 v4, vcc_lo, s4, v6
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v7, vcc_lo
v_add_co_u32 v6, vcc_lo, s6, v6
v_add_co_ci_u32_e32 v7, vcc_lo, s7, v7, vcc_lo
.LBB0_16: ; =>This Inner Loop Header: Depth=1
global_load_b32 v10, v[6:7], off
global_load_b32 v11, v[2:3], off
global_load_b32 v12, v[4:5], off
global_load_b32 v13, v[0:1], off
v_add_nc_u32_e32 v8, 1, v8
v_add_co_u32 v4, s0, v4, 4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e64 v5, s0, 0, v5, s0
v_add_co_u32 v6, s0, v6, 4
v_add_co_ci_u32_e64 v7, s0, 0, v7, s0
s_waitcnt vmcnt(0)
v_dual_sub_f32 v10, v10, v11 :: v_dual_sub_f32 v11, v12, v13
v_cmp_le_i32_e64 s0, s3, v8
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_f32_e32 v10, v10, v10
s_or_b32 s2, s0, s2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v10, v11, v11
v_mul_f32_e32 v11, 0x4f800000, v10
v_cmp_gt_f32_e32 vcc_lo, 0xf800000, v10
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v10, v10, v11, vcc_lo
v_sqrt_f32_e32 v11, v10
s_waitcnt_depctr 0xfff
v_add_nc_u32_e32 v13, 1, v11
v_add_nc_u32_e32 v12, -1, v11
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v15, -v13, v11, v10
v_fma_f32 v14, -v12, v11, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_ge_f32_e64 s1, 0, v14
v_cndmask_b32_e64 v11, v11, v12, s1
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_lt_f32_e64 s1, 0, v15
v_cndmask_b32_e64 v11, v11, v13, s1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v12, 0x37800000, v11
v_cndmask_b32_e32 v11, v11, v12, vcc_lo
v_cmp_class_f32_e64 vcc_lo, v10, 0x260
s_delay_alu instid0(VALU_DEP_2)
v_cndmask_b32_e32 v10, v11, v10, vcc_lo
ds_store_b32 v9, v10
s_waitcnt lgkmcnt(0)
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
s_and_not1_b32 exec_lo, exec_lo, s2
s_cbranch_execnz .LBB0_16
.LBB0_17: ; %._crit_edge
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z16minimum_distancePfS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 16
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z16minimum_distancePfS_S_i, .Lfunc_end0-_Z16minimum_distancePfS_S_i
; -- End function
.section .AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 760
; NumSgprs: 18
; NumVgprs: 16
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 16
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object ; @__hip_cuid_
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0 ; 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
- .offset: 152
.size: 4
.value_kind: hidden_dynamic_lds_size
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z16minimum_distancePfS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z16minimum_distancePfS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 16
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
```
| 3,840 | 4,700 |
221 |
Convert the following CUDA host assembly code to AMD host assembly:
```cudaasm
.file "tmpxft_000bd9bd_00000000-6_sidney.cudafe1.cpp"
.text
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z41__device_stub__Z16minimum_distancePfS_S_iPfS_S_i
.type _Z41__device_stub__Z16minimum_distancePfS_S_iPfS_S_i, @function
_Z41__device_stub__Z16minimum_distancePfS_S_iPfS_S_i:
.LFB2083:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z16minimum_distancePfS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z41__device_stub__Z16minimum_distancePfS_S_iPfS_S_i, .-_Z41__device_stub__Z16minimum_distancePfS_S_iPfS_S_i
.globl _Z16minimum_distancePfS_S_i
.type _Z16minimum_distancePfS_S_i, @function
_Z16minimum_distancePfS_S_i:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z41__device_stub__Z16minimum_distancePfS_S_iPfS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z16minimum_distancePfS_S_i, .-_Z16minimum_distancePfS_S_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Use: %s <number of points>\n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "Maximum number of points allowed: %d\n"
.section .rodata.str1.1
.LC3:
.string "Number of Points = %d\n"
.LC4:
.string "GPU Host-to-device = %f ms \n"
.LC5:
.string "GPU execution time = %f ms \n"
.LC6:
.string "GPU Device-to-host = %f ms \n"
.LC7:
.string "Minimum distance (GPU) = %e\n"
.LC9:
.string "CPU execution time = %f ms\n"
.LC10:
.string "Minimum distance (CPU) = %e\n"
.text
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $152, %rsp
.cfi_def_cfa_offset 208
movl %edi, %ebx
movq %rsi, %rbp
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
movl $0, 20(%rsp)
leaq 48(%rsp), %rdi
call cudaEventCreate@PLT
leaq 56(%rsp), %rdi
call cudaEventCreate@PLT
cmpl $2, %ebx
je .L12
movq 0(%rbp), %rdx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %edi
call exit@PLT
.L12:
movq 8(%rbp), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %r13
movl %eax, num_points(%rip)
cmpl $1048576, %eax
jle .L13
movl $1048576, %edx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %edi
call exit@PLT
.L13:
leal 0(,%rax,4), %r14d
movslq %r14d, %r14
movq %r14, %rdi
call malloc@PLT
movq %rax, %rbp
movq %r14, %rdi
call malloc@PLT
movq %rax, %rbx
movl $4, %edi
call malloc@PLT
movq %rax, %r12
testl %r13d, %r13d
jle .L14
movl $0, %r13d
.L15:
leaq 20(%rsp), %r15
movq %r15, %rdi
call rand_r@PLT
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
mulss .LC2(%rip), %xmm0
movss %xmm0, 0(%rbp,%r13,4)
movq %r15, %rdi
call rand_r@PLT
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
mulss .LC2(%rip), %xmm0
movss %xmm0, (%rbx,%r13,4)
addq $1, %r13
cmpl %r13d, num_points(%rip)
jg .L15
.L14:
leaq 24(%rsp), %rdi
movq %r14, %rsi
call cudaMalloc@PLT
leaq 32(%rsp), %rdi
movq %r14, %rsi
call cudaMalloc@PLT
leaq 40(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
movl $0, %esi
movq 48(%rsp), %rdi
call cudaEventRecord@PLT
movl $1, %ecx
movq %r14, %rdx
movq %rbp, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %r14, %rdx
movq %rbx, %rsi
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
movl $0, %esi
movq 56(%rsp), %rdi
call cudaEventRecord@PLT
movq 56(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 96(%rsp), %rdi
movq 56(%rsp), %rdx
movq 48(%rsp), %rsi
call cudaEventElapsedTime@PLT
movl $0, %esi
movq 48(%rsp), %rdi
call cudaEventRecord@PLT
movl $16, threads(%rip)
movl num_points(%rip), %eax
movl $16, %ecx
cltd
idivl %ecx
movl %eax, blocks(%rip)
movl $16, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl %eax, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 80(%rsp), %rdx
movl $1, %ecx
movq 64(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L28
.L16:
movl $0, %esi
movq 56(%rsp), %rdi
call cudaEventRecord@PLT
movq 56(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 100(%rsp), %rdi
movq 56(%rsp), %rdx
movq 48(%rsp), %rsi
call cudaEventElapsedTime@PLT
movl $0, %esi
movq 48(%rsp), %rdi
call cudaEventRecord@PLT
movl $2, %ecx
movl $4, %edx
movq 40(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
movl $0, %esi
movq 56(%rsp), %rdi
call cudaEventRecord@PLT
movq 56(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 104(%rsp), %rdi
movq 56(%rsp), %rdx
movq 48(%rsp), %rsi
call cudaEventElapsedTime@PLT
movl num_points(%rip), %edx
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
pxor %xmm0, %xmm0
cvtss2sd 96(%rsp), %xmm0
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
pxor %xmm0, %xmm0
cvtss2sd 100(%rsp), %xmm0
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
pxor %xmm0, %xmm0
cvtss2sd 104(%rsp), %xmm0
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
pxor %xmm0, %xmm0
cvtss2sd (%r12), %xmm0
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
leaq 64(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
movss 4(%rbp), %xmm0
subss 0(%rbp), %xmm0
movss 4(%rbx), %xmm1
subss (%rbx), %xmm1
mulss %xmm0, %xmm0
mulss %xmm1, %xmm1
addss %xmm1, %xmm0
call sqrtf@PLT
movss %xmm0, 12(%rsp)
movl num_points(%rip), %edx
testl %edx, %edx
jle .L17
movslq %edx, %rsi
movl $1, %ecx
jmp .L21
.L28:
movl num_points(%rip), %ecx
movq 40(%rsp), %rdx
movq 32(%rsp), %rsi
movq 24(%rsp), %rdi
call _Z41__device_stub__Z16minimum_distancePfS_S_iPfS_S_i
jmp .L16
.L24:
movq %rax, %rcx
.L21:
cmpl %ecx, %edx
jle .L18
movss -4(%rbp,%rcx,4), %xmm3
movss -4(%rbx,%rcx,4), %xmm2
movq %rcx, %rax
.L20:
movss 0(%rbp,%rax,4), %xmm0
subss %xmm3, %xmm0
movss (%rbx,%rax,4), %xmm1
subss %xmm2, %xmm1
mulss %xmm0, %xmm0
mulss %xmm1, %xmm1
addss %xmm1, %xmm0
sqrtss %xmm0, %xmm0
minss 12(%rsp), %xmm0
movss %xmm0, 12(%rsp)
addq $1, %rax
cmpl %eax, %edx
jg .L20
.L18:
leaq 1(%rcx), %rax
cmpq %rcx, %rsi
jne .L24
.L17:
leaq 80(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
movq 80(%rsp), %rax
subq 64(%rsp), %rax
imulq $1000, %rax, %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
movq 88(%rsp), %rax
subq 72(%rsp), %rax
pxor %xmm1, %xmm1
cvtsi2sdq %rax, %xmm1
mulsd .LC8(%rip), %xmm1
addsd %xmm1, %xmm0
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 108(%rsp)
cvtss2sd %xmm0, %xmm0
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
pxor %xmm0, %xmm0
cvtss2sd 12(%rsp), %xmm0
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
movq %rbp, %rdi
call free@PLT
movq %rbx, %rdi
call free@PLT
movq %r12, %rdi
call free@PLT
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L29
movl $0, %eax
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L29:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.1
.LC11:
.string "_Z16minimum_distancePfS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC11(%rip), %rdx
movq %rdx, %rcx
leaq _Z16minimum_distancePfS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl num_points
.bss
.align 4
.type num_points, @object
.size num_points, 4
num_points:
.zero 4
.globl threads
.align 4
.type threads, @object
.size threads, 4
threads:
.zero 4
.globl blocks
.align 4
.type blocks, @object
.size blocks, 4
blocks:
.zero 4
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC2:
.long 805306368
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC8:
.long -1598689907
.long 1051772663
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
```
|
```amdasm
.text
.file "sidney.hip"
.globl _Z31__device_stub__minimum_distancePfS_S_i # -- Begin function _Z31__device_stub__minimum_distancePfS_S_i
.type _Z31__device_stub__minimum_distancePfS_S_i,@function
_Z31__device_stub__minimum_distancePfS_S_i: # @_Z31__device_stub__minimum_distancePfS_S_i
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $112, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 40(%rsp), %rax
movq %rdi, (%rax)
leaq 32(%rsp), %rdi
movq %rsi, (%rdi)
leaq 24(%rsp), %rsi
movq %rdx, (%rsi)
leaq 4(%rsp), %rdx
movl %ecx, (%rdx)
leaq 80(%rsp), %rbx
movq %rax, (%rbx)
movq %rdi, 8(%rbx)
movq %rsi, 16(%rbx)
movq %rdx, 24(%rbx)
leaq 64(%rsp), %r14
leaq 48(%rsp), %r15
leaq 16(%rsp), %r12
leaq 8(%rsp), %r13
movq %r14, %rdi
movq %r15, %rsi
movq %r12, %rdx
movq %r13, %rcx
callq __hipPopCallConfiguration
movq (%r14), %rsi
movl 8(%r14), %edx
movq (%r15), %rcx
movl 8(%r15), %r8d
movl $_Z16minimum_distancePfS_S_i, %edi
movq %rbx, %r9
pushq (%r13)
.cfi_adjust_cfa_offset 8
pushq (%r12)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $128, %rsp
.cfi_adjust_cfa_offset -128
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z31__device_stub__minimum_distancePfS_S_i, .Lfunc_end0-_Z31__device_stub__minimum_distancePfS_S_i
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI1_0:
.long 0x30000000 # float 4.65661287E-10
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0
.LCPI1_1:
.quad 0x3eb0c6f7a0b5ed8d # double 9.9999999999999995E-7
.text
.globl main
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $120, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsi, %rbx
movl %edi, %ebp
movl $0, 28(%rsp)
leaq 8(%rsp), %rdi
callq hipEventCreate
movq %rsp, %rdi
callq hipEventCreate
cmpl $2, %ebp
jne .LBB1_16
# %bb.1:
movq 8(%rbx), %rdi
callq atoi
movl %eax, num_points(%rip)
cmpl $1048577, %eax # imm = 0x100001
jge .LBB1_17
# %bb.2:
movl %eax, %r13d
leal (,%r13,4), %eax
movslq %eax, %r12
movq %r12, %rdi
callq malloc
movq %rax, %rbx
movq %r12, %rdi
callq malloc
movq %rax, %r14
movl $4, %edi
callq malloc
movq %rax, %r15
testl %r13d, %r13d
jle .LBB1_5
# %bb.3: # %.lr.ph.preheader
xorl %ebp, %ebp
leaq 28(%rsp), %r13
.LBB1_4: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movq %r13, %rdi
callq rand_r
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movss .LCPI1_0(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero
mulss %xmm1, %xmm0
movss %xmm0, (%rbx,%rbp,4)
movq %r13, %rdi
callq rand_r
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
mulss .LCPI1_0(%rip), %xmm0
movss %xmm0, (%r14,%rbp,4)
incq %rbp
movslq num_points(%rip), %rax
cmpq %rax, %rbp
jl .LBB1_4
.LBB1_5: # %._crit_edge
leaq 40(%rsp), %r13
movq %r13, %rdi
movq %r12, %rsi
callq hipMalloc
leaq 32(%rsp), %rbp
movq %rbp, %rdi
movq %r12, %rsi
callq hipMalloc
leaq 16(%rsp), %rdi
movl $4, %esi
callq hipMalloc
movq 8(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq (%r13), %rdi
movq %rbx, %rsi
movq %r12, %rdx
movl $1, %ecx
callq hipMemcpy
movq (%rbp), %rdi
movq %r14, %rsi
movq %r12, %rdx
movl $1, %ecx
callq hipMemcpy
movq (%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq (%rsp), %rdi
callq hipEventSynchronize
movq 8(%rsp), %rsi
movq (%rsp), %rdx
leaq 64(%rsp), %rdi
callq hipEventElapsedTime
movq 8(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movl $16, threads(%rip)
movl num_points(%rip), %eax
leal 15(%rax), %edi
testl %eax, %eax
cmovnsl %eax, %edi
sarl $4, %edi
movl %edi, blocks(%rip)
btsq $32, %rdi
movabsq $4294967296, %rdx # imm = 0x100000000
orq $16, %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_7
# %bb.6:
movq 40(%rsp), %rdi
movq 32(%rsp), %rsi
movq 16(%rsp), %rdx
movl num_points(%rip), %ecx
callq _Z31__device_stub__minimum_distancePfS_S_i
.LBB1_7:
movq (%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq (%rsp), %rdi
callq hipEventSynchronize
leaq 68(%rsp), %rdi
movq 8(%rsp), %rsi
movq (%rsp), %rdx
callq hipEventElapsedTime
movq 8(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 16(%rsp), %rsi
movl $4, %edx
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
movq (%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq (%rsp), %rdi
callq hipEventSynchronize
leaq 72(%rsp), %r12
movq 8(%rsp), %rsi
movq (%rsp), %rdx
movq %r12, %rdi
callq hipEventElapsedTime
movl num_points(%rip), %esi
movl $.L.str.2, %edi
xorl %eax, %eax
callq printf
cvtss2sd -8(%r12), %xmm0
movl $.L.str.3, %edi
movb $1, %al
callq printf
xorps %xmm0, %xmm0
cvtss2sd -4(%r12), %xmm0
movl $.L.str.4, %edi
movb $1, %al
callq printf
xorps %xmm0, %xmm0
cvtss2sd (%r12), %xmm0
movl $.L.str.5, %edi
movb $1, %al
callq printf
xorps %xmm0, %xmm0
cvtss2sd (%r15), %xmm0
movl $.L.str.6, %edi
movb $1, %al
callq printf
leaq 48(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
movss 4(%rbx), %xmm0 # xmm0 = mem[0],zero,zero,zero
subss (%rbx), %xmm0
movss 4(%r14), %xmm1 # xmm1 = mem[0],zero,zero,zero
subss (%r14), %xmm1
mulss %xmm0, %xmm0
mulss %xmm1, %xmm1
addss %xmm0, %xmm1
xorps %xmm0, %xmm0
sqrtss %xmm1, %xmm0
movl num_points(%rip), %eax
testl %eax, %eax
jle .LBB1_14
# %bb.8: # %.lr.ph72
xorl %edi, %edi
movq %rax, %rcx
movq %rbx, %rdx
movq %r14, %rsi
.LBB1_9: # =>This Loop Header: Depth=1
# Child Loop BB1_11 Depth 2
movq %rdi, %r8
incq %rdi
cmpq %rax, %rdi
jae .LBB1_12
# %bb.10: # %.lr.ph68
# in Loop: Header=BB1_9 Depth=1
movss (%rbx,%r8,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
movss (%r14,%r8,4), %xmm2 # xmm2 = mem[0],zero,zero,zero
movl $1, %r8d
.LBB1_11: # Parent Loop BB1_9 Depth=1
# => This Inner Loop Header: Depth=2
movss (%rdx,%r8,4), %xmm3 # xmm3 = mem[0],zero,zero,zero
subss %xmm1, %xmm3
movss (%rsi,%r8,4), %xmm4 # xmm4 = mem[0],zero,zero,zero
subss %xmm2, %xmm4
mulss %xmm3, %xmm3
mulss %xmm4, %xmm4
addss %xmm3, %xmm4
xorps %xmm3, %xmm3
sqrtss %xmm4, %xmm3
minss %xmm0, %xmm3
incq %r8
movaps %xmm3, %xmm0
cmpq %r8, %rcx
jne .LBB1_11
jmp .LBB1_13
.LBB1_12: # in Loop: Header=BB1_9 Depth=1
movaps %xmm0, %xmm3
.LBB1_13: # %.loopexit
# in Loop: Header=BB1_9 Depth=1
addq $4, %rsi
addq $4, %rdx
decq %rcx
movaps %xmm3, %xmm0
cmpq %rax, %rdi
jne .LBB1_9
jmp .LBB1_15
.LBB1_14:
movaps %xmm0, %xmm3
.LBB1_15: # %._crit_edge73
movss %xmm3, 24(%rsp) # 4-byte Spill
leaq 104(%rsp), %r12
movq %r12, %rdi
xorl %esi, %esi
callq gettimeofday
movq (%r12), %rax
subq 48(%rsp), %rax
movq 8(%r12), %rcx
imulq $1000, %rax, %rax # imm = 0x3E8
xorps %xmm0, %xmm0
cvtsi2sd %rax, %xmm0
subq 56(%rsp), %rcx
xorps %xmm1, %xmm1
cvtsi2sd %rcx, %xmm1
mulsd .LCPI1_1(%rip), %xmm1
addsd %xmm0, %xmm1
xorps %xmm0, %xmm0
cvtsd2ss %xmm1, %xmm0
movss %xmm0, 76(%rsp)
cvtss2sd %xmm0, %xmm0
movl $.L.str.7, %edi
movb $1, %al
callq printf
xorps %xmm0, %xmm0
cvtss2sd 24(%rsp), %xmm0 # 4-byte Folded Reload
movl $.L.str.8, %edi
movb $1, %al
callq printf
movq 40(%rsp), %rdi
callq hipFree
movq 32(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
xorl %eax, %eax
addq $120, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB1_16:
.cfi_def_cfa_offset 176
movq (%rbx), %rsi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
jmp .LBB1_18
.LBB1_17:
movl $.L.str.1, %edi
movl $1048576, %esi # imm = 0x100000
xorl %eax, %eax
callq printf
.LBB1_18:
xorl %edi, %edi
callq exit
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, %rdi
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z16minimum_distancePfS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type blocks,@object # @blocks
.bss
.globl blocks
.p2align 2, 0x0
blocks:
.long 0 # 0x0
.size blocks, 4
.type threads,@object # @threads
.globl threads
.p2align 2, 0x0
threads:
.long 0 # 0x0
.size threads, 4
.type num_points,@object # @num_points
.globl num_points
.p2align 2, 0x0
num_points:
.long 0 # 0x0
.size num_points, 4
.type _Z16minimum_distancePfS_S_i,@object # @_Z16minimum_distancePfS_S_i
.section .rodata,"a",@progbits
.globl _Z16minimum_distancePfS_S_i
.p2align 3, 0x0
_Z16minimum_distancePfS_S_i:
.quad _Z31__device_stub__minimum_distancePfS_S_i
.size _Z16minimum_distancePfS_S_i, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Use: %s <number of points>\n"
.size .L.str, 28
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Maximum number of points allowed: %d\n"
.size .L.str.1, 38
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Number of Points = %d\n"
.size .L.str.2, 23
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "GPU Host-to-device = %f ms \n"
.size .L.str.3, 29
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "GPU execution time = %f ms \n"
.size .L.str.4, 29
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "GPU Device-to-host = %f ms \n"
.size .L.str.5, 29
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "Minimum distance (GPU) = %e\n"
.size .L.str.6, 29
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "CPU execution time = %f ms\n"
.size .L.str.7, 28
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "Minimum distance (CPU) = %e\n"
.size .L.str.8, 29
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z16minimum_distancePfS_S_i"
.size .L__unnamed_1, 28
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z31__device_stub__minimum_distancePfS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z16minimum_distancePfS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
```
| 5,628 | 6,407 |
224 |
Convert the following CUDA device assembly code to AMD device assembly:
```cudaasm
code for sm_80
```
|
```amdasm
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object ; @__hip_cuid_
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0 ; 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
```
| 24 | 306 |
225 |
Convert the following CUDA host assembly code to AMD host assembly:
```cudaasm
.file "tmpxft_000f302b_00000000-6_main.cudafe1.cpp"
.text
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "No CUDA Support device found!"
.LC1:
.string "Device %d : %s\n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC2:
.string "Number of multiprocessors: %d\n"
.section .rodata.str1.1
.LC3:
.string "clock rate : %d\n"
.LC4:
.string "Compute capability : %d.%d\n"
.section .rodata.str1.8
.align 8
.LC6:
.string "Total amount of global memory : %4.2f KB\n"
.align 8
.LC7:
.string "Total amount of constant memory : %4.2f KB\n"
.align 8
.LC8:
.string "Total amount of shared memory per block : %4.2f KB\n"
.align 8
.LC9:
.string "Total amount of shared memory per MP : %4.2f KB\n"
.section .rodata.str1.1
.LC10:
.string "Warp size : %d\n"
.section .rodata.str1.8
.align 8
.LC11:
.string "Maximum number of threads per block: %d\n"
.align 8
.LC12:
.string "Maximum number of threads per multiprocessor: %d\n"
.align 8
.LC13:
.string "Maximum number of warps per multiprocessor: %d\n"
.align 8
.LC14:
.string "Maximum Grid size : (%d, %d, %d)\n"
.align 8
.LC15:
.string "Maximum block dimension : (%d, %d, %d)\n"
.text
.globl _Z12query_devicev
.type _Z12query_devicev, @function
_Z12query_devicev:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $1056, %rsp
.cfi_def_cfa_offset 1072
movq %fs:40, %rax
movq %rax, 1048(%rsp)
xorl %eax, %eax
movl $0, 12(%rsp)
leaq 12(%rsp), %rdi
call cudaGetDeviceCount@PLT
cmpl $0, 12(%rsp)
je .L15
.L4:
leaq 16(%rsp), %rbx
movl $0, %esi
movq %rbx, %rdi
call cudaGetDeviceProperties_v2@PLT
movq %rbx, %rcx
movl $0, %edx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 404(%rsp), %edx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 364(%rsp), %edx
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 380(%rsp), %ecx
movl 376(%rsp), %edx
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 304(%rsp), %rax
testq %rax, %rax
js .L5
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
.L6:
mulsd .LC5(%rip), %xmm0
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 368(%rsp), %rax
testq %rax, %rax
js .L7
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
.L8:
mulsd .LC5(%rip), %xmm0
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 312(%rsp), %rax
testq %rax, %rax
js .L9
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
.L10:
mulsd .LC5(%rip), %xmm0
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 656(%rsp), %rax
testq %rax, %rax
js .L11
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
.L12:
mulsd .LC5(%rip), %xmm0
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl 324(%rsp), %edx
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 336(%rsp), %edx
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 640(%rsp), %edx
leaq .LC12(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 640(%rsp), %eax
leal 31(%rax), %edx
testl %eax, %eax
cmovns %eax, %edx
sarl $5, %edx
leaq .LC13(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 360(%rsp), %r8d
movl 356(%rsp), %ecx
movl 352(%rsp), %edx
leaq .LC14(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 348(%rsp), %r8d
movl 344(%rsp), %ecx
movl 340(%rsp), %edx
leaq .LC15(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 1048(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $1056, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L4
.L5:
movq %rax, %rdx
shrq %rdx
andl $1, %eax
orq %rax, %rdx
pxor %xmm0, %xmm0
cvtsi2sdq %rdx, %xmm0
addsd %xmm0, %xmm0
jmp .L6
.L7:
movq %rax, %rdx
shrq %rdx
andl $1, %eax
orq %rax, %rdx
pxor %xmm0, %xmm0
cvtsi2sdq %rdx, %xmm0
addsd %xmm0, %xmm0
jmp .L8
.L9:
movq %rax, %rdx
shrq %rdx
andl $1, %eax
orq %rax, %rdx
pxor %xmm0, %xmm0
cvtsi2sdq %rdx, %xmm0
addsd %xmm0, %xmm0
jmp .L10
.L11:
movq %rax, %rdx
shrq %rdx
andl $1, %eax
orq %rax, %rdx
pxor %xmm0, %xmm0
cvtsi2sdq %rdx, %xmm0
addsd %xmm0, %xmm0
jmp .L12
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size _Z12query_devicev, .-_Z12query_devicev
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z12query_devicev
movl $0, %eax
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC5:
.long 0
.long 1062207488
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
```
|
```amdasm
.text
.file "main.hip"
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0 # -- Begin function _Z12query_devicev
.LCPI0_0:
.long 1127219200 # 0x43300000
.long 1160773632 # 0x45300000
.long 0 # 0x0
.long 0 # 0x0
.LCPI0_1:
.quad 0x4330000000000000 # double 4503599627370496
.quad 0x4530000000000000 # double 1.9342813113834067E+25
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0
.LCPI0_2:
.quad 0x3f50000000000000 # double 9.765625E-4
.text
.globl _Z12query_devicev
.type _Z12query_devicev,@function
_Z12query_devicev: # @_Z12query_devicev
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $1488, %rsp # imm = 0x5D0
.cfi_def_cfa_offset 1504
.cfi_offset %rbx, -16
leaq 12(%rsp), %rbx
movl $0, (%rbx)
movq %rbx, %rdi
callq hipGetDeviceCount
cmpl $0, (%rbx)
jne .LBB0_2
# %bb.1:
movl $.L.str, %edi
xorl %eax, %eax
callq printf
.LBB0_2:
leaq 16(%rsp), %rbx
movq %rbx, %rdi
xorl %esi, %esi
callq hipGetDevicePropertiesR0600
movl $.L.str.1, %edi
xorl %esi, %esi
movq %rbx, %rdx
xorl %eax, %eax
callq printf
movl 388(%rbx), %esi
movl $.L.str.2, %edi
xorl %eax, %eax
callq printf
movl 348(%rbx), %esi
movl $.L.str.3, %edi
xorl %eax, %eax
callq printf
movl 360(%rbx), %esi
movl 364(%rbx), %edx
movl $.L.str.4, %edi
xorl %eax, %eax
callq printf
movsd 288(%rbx), %xmm1 # xmm1 = mem[0],zero
unpcklps .LCPI0_0(%rip), %xmm1 # xmm1 = xmm1[0],mem[0],xmm1[1],mem[1]
subpd .LCPI0_1(%rip), %xmm1
movapd %xmm1, %xmm0
unpckhpd %xmm1, %xmm0 # xmm0 = xmm0[1],xmm1[1]
addsd %xmm1, %xmm0
mulsd .LCPI0_2(%rip), %xmm0
movl $.L.str.5, %edi
movb $1, %al
callq printf
movsd 352(%rbx), %xmm1 # xmm1 = mem[0],zero
unpcklps .LCPI0_0(%rip), %xmm1 # xmm1 = xmm1[0],mem[0],xmm1[1],mem[1]
subpd .LCPI0_1(%rip), %xmm1
movapd %xmm1, %xmm0
unpckhpd %xmm1, %xmm0 # xmm0 = xmm0[1],xmm1[1]
addsd %xmm1, %xmm0
mulsd .LCPI0_2(%rip), %xmm0
movl $.L.str.6, %edi
movb $1, %al
callq printf
movsd 296(%rbx), %xmm1 # xmm1 = mem[0],zero
unpcklps .LCPI0_0(%rip), %xmm1 # xmm1 = xmm1[0],mem[0],xmm1[1],mem[1]
subpd .LCPI0_1(%rip), %xmm1
movapd %xmm1, %xmm0
unpckhpd %xmm1, %xmm0 # xmm0 = xmm0[1],xmm1[1]
addsd %xmm1, %xmm0
mulsd .LCPI0_2(%rip), %xmm0
movl $.L.str.7, %edi
movb $1, %al
callq printf
movsd 640(%rbx), %xmm1 # xmm1 = mem[0],zero
unpcklps .LCPI0_0(%rip), %xmm1 # xmm1 = xmm1[0],mem[0],xmm1[1],mem[1]
subpd .LCPI0_1(%rip), %xmm1
movapd %xmm1, %xmm0
unpckhpd %xmm1, %xmm0 # xmm0 = xmm0[1],xmm1[1]
addsd %xmm1, %xmm0
mulsd .LCPI0_2(%rip), %xmm0
movl $.L.str.8, %edi
movb $1, %al
callq printf
movl 308(%rbx), %esi
movl $.L.str.9, %edi
xorl %eax, %eax
callq printf
movl 320(%rbx), %esi
movl $.L.str.10, %edi
xorl %eax, %eax
callq printf
movl 624(%rbx), %esi
movl $.L.str.11, %edi
xorl %eax, %eax
callq printf
movl 624(%rbx), %eax
leal 31(%rax), %esi
testl %eax, %eax
cmovnsl %eax, %esi
sarl $5, %esi
movl $.L.str.12, %edi
xorl %eax, %eax
callq printf
movl 336(%rbx), %esi
movl 340(%rbx), %edx
movl 344(%rbx), %ecx
movl $.L.str.13, %edi
xorl %eax, %eax
callq printf
movl 324(%rbx), %esi
movl 328(%rbx), %edx
movl 332(%rbx), %ecx
movl $.L.str.14, %edi
xorl %eax, %eax
callq printf
addq $1488, %rsp # imm = 0x5D0
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z12query_devicev, .Lfunc_end0-_Z12query_devicev
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
callq _Z12query_devicev
xorl %eax, %eax
popq %rcx
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "No CUDA Support device found!"
.size .L.str, 30
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Device %d : %s\n"
.size .L.str.1, 16
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Number of multiprocessors: %d\n"
.size .L.str.2, 31
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "clock rate : %d\n"
.size .L.str.3, 17
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Compute capability : %d.%d\n"
.size .L.str.4, 28
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "Total amount of global memory : %4.2f KB\n"
.size .L.str.5, 42
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "Total amount of constant memory : %4.2f KB\n"
.size .L.str.6, 44
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "Total amount of shared memory per block : %4.2f KB\n"
.size .L.str.7, 52
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "Total amount of shared memory per MP : %4.2f KB\n"
.size .L.str.8, 49
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "Warp size : %d\n"
.size .L.str.9, 16
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "Maximum number of threads per block: %d\n"
.size .L.str.10, 41
.type .L.str.11,@object # @.str.11
.L.str.11:
.asciz "Maximum number of threads per multiprocessor: %d\n"
.size .L.str.11, 50
.type .L.str.12,@object # @.str.12
.L.str.12:
.asciz "Maximum number of warps per multiprocessor: %d\n"
.size .L.str.12, 48
.type .L.str.13,@object # @.str.13
.L.str.13:
.asciz "Maximum Grid size : (%d, %d, %d)\n"
.size .L.str.13, 34
.type .L.str.14,@object # @.str.14
.L.str.14:
.asciz "Maximum block dimension : (%d, %d, %d)\n"
.size .L.str.14, 40
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
```
| 3,187 | 2,960 |
228 |
Convert the following CUDA device assembly code to AMD device assembly:
```cudaasm
code for sm_80
Function : _Z14matrixVectMultPfS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
MOV R1, c[0x0][0x28] ;
S2R R0, SR_CTAID.X ;
S2R R3, SR_TID.X ;
IMAD R0, R0, c[0x0][0x0], R3 ;
ISETP.GE.AND P0, PT, R0, c[0x0][0x178], PT ;
@P0 EXIT ;
MOV R2, c[0x0][0x178] ;
ULDC.64 UR4, c[0x0][0x118] ;
HFMA2.MMA R15, -RZ, RZ, 0, 0 ;
ISETP.GE.AND P0, PT, R2, 0x1, PT ;
@!P0 BRA 0xb70 ;
IADD3 R3, R2.reuse, -0x1, RZ ;
LOP3.LUT R2, R2, 0x3, RZ, 0xc0, !PT ;
ISETP.GE.U32.AND P0, PT, R3, 0x3, PT ;
MOV R3, RZ ;
MOV R15, RZ ;
@!P0 BRA 0xa60 ;
IADD3 R4, -R2, c[0x0][0x178], RZ ;
HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ;
MOV R3, RZ ;
HFMA2.MMA R15, -RZ, RZ, 0, 0 ;
ISETP.GT.AND P0, PT, R4, RZ, PT ;
MOV R12, c[0x0][0x168] ;
MOV R13, c[0x0][0x16c] ;
IMAD.WIDE R26, R0, R5, c[0x0][0x160] ;
@!P0 BRA 0x8e0 ;
ISETP.GT.AND P1, PT, R4, 0xc, PT ;
PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ;
@!P1 BRA 0x640 ;
PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ;
LDG.E R28, [R26.64] ;
IMAD.WIDE R18, R5, c[0x0][0x178], R26 ;
LDG.E R14, [R12.64] ;
IMAD.WIDE R24, R5.reuse, c[0x0][0x178], R18 ;
LDG.E R16, [R18.64] ;
LDG.E R17, [R12.64+0x4] ;
IMAD.WIDE R26, R5, c[0x0][0x178], R24 ;
LDG.E R6, [R24.64] ;
LDG.E R7, [R12.64+0x8] ;
IMAD.WIDE R22, R5, c[0x0][0x178], R26 ;
LDG.E R8, [R12.64+0xc] ;
LDG.E R9, [R26.64] ;
IMAD.WIDE R20, R5, c[0x0][0x178], R22 ;
LDG.E R10, [R22.64] ;
LDG.E R11, [R12.64+0x10] ;
LDG.E R18, [R12.64+0x14] ;
LDG.E R19, [R20.64] ;
LDG.E R24, [R12.64+0x18] ;
LDG.E R26, [R12.64+0x1c] ;
IMAD.WIDE R20, R5, c[0x0][0x178], R20 ;
LDG.E R25, [R20.64] ;
IMAD.WIDE R22, R5, c[0x0][0x178], R20 ;
LDG.E R27, [R22.64] ;
LDG.E R21, [R12.64+0x20] ;
LDG.E R20, [R12.64+0x24] ;
FFMA R28, R14, R28, R15 ;
IMAD.WIDE R14, R5, c[0x0][0x178], R22 ;
LDG.E R23, [R12.64+0x28] ;
FFMA R28, R17, R16, R28 ;
IMAD.WIDE R16, R5, c[0x0][0x178], R14 ;
LDG.E R14, [R14.64] ;
FFMA R28, R7, R6, R28 ;
IMAD.WIDE R6, R5, c[0x0][0x178], R16 ;
LDG.E R17, [R16.64] ;
FFMA R28, R8, R9, R28 ;
LDG.E R22, [R6.64] ;
IMAD.WIDE R8, R5, c[0x0][0x178], R6 ;
LDG.E R15, [R12.64+0x2c] ;
FFMA R29, R11, R10, R28 ;
LDG.E R16, [R12.64+0x30] ;
IMAD.WIDE R10, R5, c[0x0][0x178], R8 ;
LDG.E R28, [R8.64] ;
FFMA R29, R18, R19, R29 ;
IMAD.WIDE R18, R5.reuse, c[0x0][0x178], R10 ;
LDG.E R11, [R10.64] ;
IMAD.WIDE R6, R5, c[0x0][0x178], R18 ;
FFMA R29, R24, R25, R29 ;
LDG.E R24, [R18.64] ;
IMAD.WIDE R8, R5, c[0x0][0x178], R6 ;
LDG.E R25, [R12.64+0x34] ;
LDG.E R10, [R8.64] ;
FFMA R18, R26, R27, R29 ;
LDG.E R26, [R12.64+0x38] ;
LDG.E R27, [R6.64] ;
LDG.E R29, [R12.64+0x3c] ;
IADD3 R4, R4, -0x10, RZ ;
ISETP.GT.AND P1, PT, R4, 0xc, PT ;
IADD3 R12, P2, R12, 0x40, RZ ;
IADD3 R3, R3, 0x10, RZ ;
IADD3.X R13, RZ, R13, RZ, P2, !PT ;
FFMA R14, R21, R14, R18 ;
FFMA R14, R20, R17, R14 ;
FFMA R14, R23, R22, R14 ;
FFMA R14, R15, R28, R14 ;
FFMA R11, R16, R11, R14 ;
FFMA R11, R25, R24, R11 ;
FFMA R11, R26, R27, R11 ;
IMAD.WIDE R26, R5, c[0x0][0x178], R8 ;
FFMA R15, R29, R10, R11 ;
@P1 BRA 0x1e0 ;
ISETP.GT.AND P1, PT, R4, 0x4, PT ;
@!P1 BRA 0x8c0 ;
IMAD.WIDE R28, R5.reuse, c[0x0][0x178], R26 ;
LDG.E R14, [R26.64] ;
LDG.E R20, [R12.64] ;
IMAD.WIDE R18, R5, c[0x0][0x178], R28 ;
LDG.E R21, [R28.64] ;
IMAD.WIDE R10, R5.reuse, c[0x0][0x178], R18 ;
LDG.E R22, [R12.64+0x4] ;
LDG.E R24, [R18.64] ;
IMAD.WIDE R6, R5, c[0x0][0x178], R10 ;
LDG.E R23, [R12.64+0x8] ;
IMAD.WIDE R8, R5.reuse, c[0x0][0x178], R6 ;
LDG.E R10, [R10.64] ;
LDG.E R25, [R12.64+0xc] ;
IMAD.WIDE R16, R5, c[0x0][0x178], R8 ;
LDG.E R7, [R6.64] ;
LDG.E R26, [R12.64+0x10] ;
IMAD.WIDE R18, R5, c[0x0][0x178], R16 ;
LDG.E R9, [R8.64] ;
LDG.E R28, [R12.64+0x14] ;
LDG.E R27, [R16.64] ;
LDG.E R6, [R12.64+0x18] ;
LDG.E R11, [R12.64+0x1c] ;
LDG.E R29, [R18.64] ;
IADD3 R8, P1, R12, 0x20, RZ ;
PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ;
IADD3 R3, R3, 0x8, RZ ;
IADD3.X R13, RZ, R13, RZ, P1, !PT ;
IADD3 R4, R4, -0x8, RZ ;
MOV R12, R8 ;
FFMA R14, R20, R14, R15 ;
FFMA R14, R22, R21, R14 ;
FFMA R14, R23, R24, R14 ;
FFMA R10, R25, R10, R14 ;
FFMA R7, R26, R7, R10 ;
FFMA R7, R28, R9, R7 ;
FFMA R6, R6, R27, R7 ;
IMAD.WIDE R26, R5, c[0x0][0x178], R18 ;
FFMA R15, R11, R29, R6 ;
ISETP.NE.OR P0, PT, R4, RZ, P0 ;
@!P0 BRA 0xa60 ;
IMAD.WIDE R8, R5.reuse, c[0x0][0x178], R26 ;
LDG.E R14, [R12.64] ;
LDG.E R26, [R26.64] ;
IMAD.WIDE R10, R5, c[0x0][0x178], R8 ;
LDG.E R16, [R8.64] ;
LDG.E R17, [R12.64+0x4] ;
IMAD.WIDE R6, R5, c[0x0][0x178], R10 ;
LDG.E R19, [R12.64+0x8] ;
LDG.E R18, [R10.64] ;
LDG.E R21, [R12.64+0xc] ;
LDG.E R20, [R6.64] ;
IADD3 R4, R4, -0x4, RZ ;
ISETP.NE.AND P0, PT, R4, RZ, PT ;
IADD3 R8, P1, R12, 0x10, RZ ;
IADD3.X R9, RZ, R13, RZ, P1, !PT ;
IADD3 R3, R3, 0x4, RZ ;
MOV R12, R8 ;
MOV R13, R9 ;
FFMA R14, R14, R26, R15 ;
FFMA R14, R17, R16, R14 ;
IMAD.WIDE R26, R5, c[0x0][0x178], R6 ;
FFMA R14, R19, R18, R14 ;
FFMA R15, R21, R20, R14 ;
@P0 BRA 0x8e0 ;
ISETP.NE.AND P0, PT, R2, RZ, PT ;
@!P0 BRA 0xb70 ;
HFMA2.MMA R9, -RZ, RZ, 0, 2.384185791015625e-07 ;
IMAD R6, R3, c[0x0][0x178], R0 ;
IMAD.WIDE R4, R3, R9, c[0x0][0x168] ;
IMAD.WIDE R6, R6, R9, c[0x0][0x160] ;
MOV R8, R4 ;
MOV R4, R8 ;
LDG.E R3, [R6.64] ;
LDG.E R4, [R4.64] ;
IADD3 R2, R2, -0x1, RZ ;
IADD3 R8, P1, R8, 0x4, RZ ;
ISETP.NE.AND P0, PT, R2, RZ, PT ;
IMAD.WIDE R6, R9, c[0x0][0x178], R6 ;
IADD3.X R5, RZ, R5, RZ, P1, !PT ;
FFMA R15, R4, R3, R15 ;
@P0 BRA 0xad0 ;
MOV R3, 0x4 ;
IMAD.WIDE R2, R0, R3, c[0x0][0x170] ;
STG.E [R2.64], R15 ;
EXIT ;
BRA 0xbb0;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
```
|
```amdasm
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z14matrixVectMultPfS_S_i ; -- Begin function _Z14matrixVectMultPfS_S_i
.globl _Z14matrixVectMultPfS_S_i
.p2align 8
.type _Z14matrixVectMultPfS_S_i,@function
_Z14matrixVectMultPfS_S_i: ; @_Z14matrixVectMultPfS_S_i
; %bb.0:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x2c
s_load_b32 s2, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s3, v[0:1]
s_mov_b32 s3, exec_lo
v_cmpx_gt_i32_e64 s2, v1
s_cbranch_execz .LBB0_5
; %bb.1: ; %.preheader
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
v_mov_b32_e32 v0, 0
s_cmp_lt_i32 s2, 1
s_cbranch_scc1 .LBB0_4
; %bb.2: ; %.lr.ph.preheader
v_mov_b32_e32 v2, v1
s_mov_b32 s3, s2
.LBB0_3: ; %.lr.ph
; =>This Inner Loop Header: Depth=1
s_delay_alu instid0(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
s_waitcnt lgkmcnt(0)
s_load_b32 s8, s[6:7], 0x0
s_add_i32 s3, s3, -1
s_add_u32 s6, s6, 4
s_addc_u32 s7, s7, 0
v_lshlrev_b64 v[3:4], 2, v[2:3]
v_add_nc_u32_e32 v2, s2, v2
s_cmp_lg_u32 s3, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v3, vcc_lo, s4, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
global_load_b32 v3, v[3:4], off
s_waitcnt vmcnt(0) lgkmcnt(0)
v_fmac_f32_e32 v0, s8, v3
s_cbranch_scc1 .LBB0_3
.LBB0_4: ; %._crit_edge
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v1, vcc_lo, s0, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
global_store_b32 v[1:2], v0, off
.LBB0_5:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z14matrixVectMultPfS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z14matrixVectMultPfS_S_i, .Lfunc_end0-_Z14matrixVectMultPfS_S_i
; -- End function
.section .AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 240
; NumSgprs: 18
; NumVgprs: 5
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 5
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object ; @__hip_cuid_
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0 ; 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z14matrixVectMultPfS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z14matrixVectMultPfS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
```
| 3,682 | 2,883 |
229 |
Convert the following CUDA host assembly code to AMD host assembly:
```cudaasm
.file "tmpxft_0010c490_00000000-6_cap-3-2.cudafe1.cpp"
.text
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2064:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2064:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%f"
.text
.globl _Z11Read_matrixPfi
.type _Z11Read_matrixPfi, @function
_Z11Read_matrixPfi:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $24, %rsp
.cfi_def_cfa_offset 80
movl %esi, 12(%rsp)
testl %esi, %esi
jle .L3
movslq %esi, %r14
leaq 0(,%r14,4), %r15
leaq (%rdi,%r15), %rbp
negq %r14
salq $2, %r14
movl $0, %r13d
leaq .LC0(%rip), %r12
.L5:
leaq 0(%rbp,%r14), %rbx
.L6:
movq %rbx, %rsi
movq %r12, %rdi
movl $0, %eax
call __isoc23_scanf@PLT
addq $4, %rbx
cmpq %rbp, %rbx
jne .L6
addl $1, %r13d
addq %r15, %rbp
cmpl %r13d, 12(%rsp)
jne .L5
.L3:
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size _Z11Read_matrixPfi, .-_Z11Read_matrixPfi
.globl _Z11Read_vectorPfi
.type _Z11Read_vectorPfi, @function
_Z11Read_vectorPfi:
.LFB2058:
.cfi_startproc
endbr64
testl %esi, %esi
jle .L14
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
movq %rdi, %rbx
movslq %esi, %rsi
leaq (%rdi,%rsi,4), %r12
leaq .LC0(%rip), %rbp
.L11:
movq %rbx, %rsi
movq %rbp, %rdi
movl $0, %eax
call __isoc23_scanf@PLT
addq $4, %rbx
cmpq %r12, %rbx
jne .L11
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore 3
.cfi_restore 6
.cfi_restore 12
ret
.cfi_endproc
.LFE2058:
.size _Z11Read_vectorPfi, .-_Z11Read_vectorPfi
.section .rodata.str1.1
.LC1:
.string "%s\n"
.LC2:
.string "%.1f "
.LC3:
.string "\n"
.text
.globl _Z12Print_matrixPcPfi
.type _Z12Print_matrixPcPfi, @function
_Z12Print_matrixPcPfi:
.LFB2059:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $24, %rsp
.cfi_def_cfa_offset 80
movq %rsi, %rbp
movl %edx, %ebx
movl %edx, 12(%rsp)
movq %rdi, %rdx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
testl %ebx, %ebx
jle .L17
movslq %ebx, %r14
leaq 0(,%r14,4), %r15
addq %r15, %rbp
negq %r14
salq $2, %r14
movl $0, %r13d
leaq .LC2(%rip), %r12
.L19:
leaq 0(%rbp,%r14), %rbx
.L20:
pxor %xmm0, %xmm0
cvtss2sd (%rbx), %xmm0
movq %r12, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %rbp, %rbx
jne .L20
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $1, %r13d
addq %r15, %rbp
cmpl %r13d, 12(%rsp)
jne .L19
.L17:
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2059:
.size _Z12Print_matrixPcPfi, .-_Z12Print_matrixPcPfi
.globl _Z12Print_vectorPcPfi
.type _Z12Print_vectorPcPfi, @function
_Z12Print_vectorPcPfi:
.LFB2060:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $8, %rsp
.cfi_def_cfa_offset 48
movq %rsi, %r12
movl %edx, %ebp
movq %rdi, %rdx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
testl %ebp, %ebp
jle .L23
movq %r12, %rbx
movslq %ebp, %rbp
leaq (%r12,%rbp,4), %r13
leaq .LC2(%rip), %r12
leaq .LC3(%rip), %rbp
.L25:
pxor %xmm0, %xmm0
cvtss2sd (%rbx), %xmm0
movq %r12, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %r13, %rbx
jne .L25
.L23:
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _Z12Print_vectorPcPfi, .-_Z12Print_vectorPcPfi
.globl _Z39__device_stub__Z14matrixVectMultPfS_S_iPfS_S_i
.type _Z39__device_stub__Z14matrixVectMultPfS_S_iPfS_S_i, @function
_Z39__device_stub__Z14matrixVectMultPfS_S_iPfS_S_i:
.LFB2086:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L32
.L28:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L33
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L32:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z14matrixVectMultPfS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L28
.L33:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2086:
.size _Z39__device_stub__Z14matrixVectMultPfS_S_iPfS_S_i, .-_Z39__device_stub__Z14matrixVectMultPfS_S_iPfS_S_i
.globl _Z14matrixVectMultPfS_S_i
.type _Z14matrixVectMultPfS_S_i, @function
_Z14matrixVectMultPfS_S_i:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z39__device_stub__Z14matrixVectMultPfS_S_iPfS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _Z14matrixVectMultPfS_S_i, .-_Z14matrixVectMultPfS_S_i
.section .rodata.str1.1
.LC4:
.string "size = %d"
.LC5:
.string "Matrix A: \n"
.LC6:
.string "Vector B: \n"
.LC7:
.string "A ="
.LC8:
.string "B ="
.LC9:
.string "Result ="
.text
.globl main
.type main, @function
main:
.LFB2061:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $88, %rsp
.cfi_def_cfa_offset 144
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movq 8(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %rbp
movl %eax, %r13d
movl %eax, %edx
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %ebp, %r12d
imull %ebp, %r12d
sall $2, %r12d
movslq %r12d, %r12
movq %r12, %rdi
call malloc@PLT
movq %rax, %r15
leal 0(,%rbp,4), %ebx
movslq %ebx, %rbx
movq %rbx, %rdi
call malloc@PLT
movq %rax, %r14
movq %rbx, %rdi
call malloc@PLT
movq %rax, 8(%rsp)
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %ebp, %esi
movq %r15, %rdi
call _Z11Read_matrixPfi
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %ebp, %esi
movq %r14, %rdi
call _Z11Read_vectorPfi
movl %ebp, %edx
movq %r15, %rsi
leaq .LC7(%rip), %rdi
call _Z12Print_matrixPcPfi
movl %ebp, %edx
movq %r14, %rsi
leaq .LC8(%rip), %rdi
call _Z12Print_vectorPcPfi
leaq 24(%rsp), %rdi
movq %r12, %rsi
call cudaMalloc@PLT
leaq 32(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq 40(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %r12, %rdx
movq %r15, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %rbx, %rdx
movq %r14, %rsi
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
movl %ebp, 60(%rsp)
movl $1, 64(%rsp)
movl %ebp, 48(%rsp)
movl $1, 52(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 60(%rsp), %rdx
movl $1, %ecx
movq 48(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L40
.L37:
movl $2, %ecx
movq %rbx, %rdx
movq 40(%rsp), %rsi
movq 8(%rsp), %rbx
movq %rbx, %rdi
call cudaMemcpy@PLT
movl %r13d, %edx
movq %rbx, %rsi
leaq .LC9(%rip), %rdi
call _Z12Print_vectorPcPfi
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
movq %r15, %rdi
call free@PLT
movq %r14, %rdi
call free@PLT
movq %rbx, %rdi
call free@PLT
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L41
movl $0, %eax
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L40:
.cfi_restore_state
movl %ebp, %ecx
movq 40(%rsp), %rdx
movq 32(%rsp), %rsi
movq 24(%rsp), %rdi
call _Z39__device_stub__Z14matrixVectMultPfS_S_iPfS_S_i
jmp .L37
.L41:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2061:
.size main, .-main
.section .rodata.str1.1
.LC10:
.string "_Z14matrixVectMultPfS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2089:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC10(%rip), %rdx
movq %rdx, %rcx
leaq _Z14matrixVectMultPfS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2089:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
```
|
```amdasm
.text
.file "cap-3-2.hip"
.globl _Z29__device_stub__matrixVectMultPfS_S_i # -- Begin function _Z29__device_stub__matrixVectMultPfS_S_i
.type _Z29__device_stub__matrixVectMultPfS_S_i,@function
_Z29__device_stub__matrixVectMultPfS_S_i: # @_Z29__device_stub__matrixVectMultPfS_S_i
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $112, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 40(%rsp), %rax
movq %rdi, (%rax)
leaq 32(%rsp), %rdi
movq %rsi, (%rdi)
leaq 24(%rsp), %rsi
movq %rdx, (%rsi)
leaq 4(%rsp), %rdx
movl %ecx, (%rdx)
leaq 80(%rsp), %rbx
movq %rax, (%rbx)
movq %rdi, 8(%rbx)
movq %rsi, 16(%rbx)
movq %rdx, 24(%rbx)
leaq 64(%rsp), %r14
leaq 48(%rsp), %r15
leaq 16(%rsp), %r12
leaq 8(%rsp), %r13
movq %r14, %rdi
movq %r15, %rsi
movq %r12, %rdx
movq %r13, %rcx
callq __hipPopCallConfiguration
movq (%r14), %rsi
movl 8(%r14), %edx
movq (%r15), %rcx
movl 8(%r15), %r8d
movl $_Z14matrixVectMultPfS_S_i, %edi
movq %rbx, %r9
pushq (%r13)
.cfi_adjust_cfa_offset 8
pushq (%r12)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $128, %rsp
.cfi_adjust_cfa_offset -128
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z29__device_stub__matrixVectMultPfS_S_i, .Lfunc_end0-_Z29__device_stub__matrixVectMultPfS_S_i
.cfi_endproc
# -- End function
.globl _Z11Read_matrixPfi # -- Begin function _Z11Read_matrixPfi
.type _Z11Read_matrixPfi,@function
_Z11Read_matrixPfi: # @_Z11Read_matrixPfi
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
pushq %rax
.cfi_def_cfa_offset 64
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rdi, (%rsp) # 8-byte Spill
testl %esi, %esi
jle .LBB1_5
# %bb.1: # %.preheader.lr.ph
movl %esi, %ebx
movl %esi, %r14d
xorl %ebp, %ebp
xorl %r13d, %r13d
.LBB1_2: # %.lr.ph
# =>This Loop Header: Depth=1
# Child Loop BB1_3 Depth 2
movl %ebp, %eax
movq (%rsp), %rcx # 8-byte Reload
leaq (%rcx,%rax,4), %r15
movq %r14, %r12
.LBB1_3: # Parent Loop BB1_2 Depth=1
# => This Inner Loop Header: Depth=2
movl $.L.str, %edi
movq %r15, %rsi
xorl %eax, %eax
callq __isoc23_scanf
addq $4, %r15
decq %r12
jne .LBB1_3
# %bb.4: # %._crit_edge
# in Loop: Header=BB1_2 Depth=1
incq %r13
addl %ebx, %ebp
cmpq %r14, %r13
jne .LBB1_2
.LBB1_5: # %._crit_edge13
addq $8, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z11Read_matrixPfi, .Lfunc_end1-_Z11Read_matrixPfi
.cfi_endproc
# -- End function
.globl _Z11Read_vectorPfi # -- Begin function _Z11Read_vectorPfi
.type _Z11Read_vectorPfi,@function
_Z11Read_vectorPfi: # @_Z11Read_vectorPfi
.cfi_startproc
# %bb.0:
testl %esi, %esi
jle .LBB2_4
# %bb.1: # %.lr.ph.preheader
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
pushq %rax
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movq %rdi, %rbx
movl %esi, %r14d
.LBB2_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl $.L.str, %edi
movq %rbx, %rsi
xorl %eax, %eax
callq __isoc23_scanf
addq $4, %rbx
decq %r14
jne .LBB2_2
# %bb.3:
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r14
.LBB2_4: # %._crit_edge
retq
.Lfunc_end2:
.size _Z11Read_vectorPfi, .Lfunc_end2-_Z11Read_vectorPfi
.cfi_endproc
# -- End function
.globl _Z12Print_matrixPcPfi # -- Begin function _Z12Print_matrixPcPfi
.type _Z12Print_matrixPcPfi,@function
_Z12Print_matrixPcPfi: # @_Z12Print_matrixPcPfi
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
pushq %rax
.cfi_def_cfa_offset 64
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %edx, %ebx
movq %rsi, (%rsp) # 8-byte Spill
callq puts@PLT
testl %ebx, %ebx
jle .LBB3_5
# %bb.1: # %.preheader.lr.ph
movl %ebx, %r15d
xorl %r12d, %r12d
xorl %r13d, %r13d
.LBB3_2: # %.lr.ph
# =>This Loop Header: Depth=1
# Child Loop BB3_3 Depth 2
movl %r12d, %eax
movq (%rsp), %rcx # 8-byte Reload
leaq (%rcx,%rax,4), %rbp
xorl %r14d, %r14d
.LBB3_3: # Parent Loop BB3_2 Depth=1
# => This Inner Loop Header: Depth=2
xorps %xmm0, %xmm0
cvtss2sd (%rbp,%r14,4), %xmm0
movl $.L.str.2, %edi
movb $1, %al
callq printf
incq %r14
cmpq %r14, %r15
jne .LBB3_3
# %bb.4: # %._crit_edge
# in Loop: Header=BB3_2 Depth=1
movl $10, %edi
callq putchar@PLT
incq %r13
addl %ebx, %r12d
cmpq %r15, %r13
jne .LBB3_2
.LBB3_5: # %._crit_edge14
addq $8, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size _Z12Print_matrixPcPfi, .Lfunc_end3-_Z12Print_matrixPcPfi
.cfi_endproc
# -- End function
.globl _Z12Print_vectorPcPfi # -- Begin function _Z12Print_vectorPcPfi
.type _Z12Print_vectorPcPfi,@function
_Z12Print_vectorPcPfi: # @_Z12Print_vectorPcPfi
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
pushq %rax
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %edx, %ebp
movq %rsi, %rbx
callq puts@PLT
testl %ebp, %ebp
jle .LBB4_3
# %bb.1: # %.lr.ph.preheader
movl %ebp, %r14d
xorl %r15d, %r15d
.LBB4_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
xorps %xmm0, %xmm0
cvtss2sd (%rbx,%r15,4), %xmm0
movl $.L.str.2, %edi
movb $1, %al
callq printf
movl $10, %edi
callq putchar@PLT
incq %r15
cmpq %r15, %r14
jne .LBB4_2
.LBB4_3: # %._crit_edge
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end4:
.size _Z12Print_vectorPcPfi, .Lfunc_end4-_Z12Print_vectorPcPfi
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $72, %rsp
.cfi_def_cfa_offset 128
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq 8(%rsi), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r13
movl $.L.str.4, %edi
movl %r13d, %esi
xorl %eax, %eax
callq printf
movl %r13d, %eax
imull %r13d, %eax
shll $2, %eax
leal (,%r13,4), %ebp
movslq %eax, %rdi
movq %rdi, 48(%rsp) # 8-byte Spill
callq malloc
movq %rax, %rbx
movslq %ebp, %r14
movq %r14, %rdi
callq malloc
movq %rax, %rbp
movq %r14, 56(%rsp) # 8-byte Spill
movq %r14, %rdi
callq malloc
movq %rax, 64(%rsp) # 8-byte Spill
movl $.Lstr, %edi
callq puts@PLT
testl %r13d, %r13d
jle .LBB5_1
# %bb.2: # %.preheader.lr.ph.i
movq %rbp, 32(%rsp) # 8-byte Spill
movq %r13, 40(%rsp) # 8-byte Spill
movl %r13d, %r14d
xorl %ebp, %ebp
xorl %r13d, %r13d
.LBB5_3: # %.lr.ph.i
# =>This Loop Header: Depth=1
# Child Loop BB5_4 Depth 2
movl %ebp, %eax
leaq (%rbx,%rax,4), %r15
movq %r14, %r12
.LBB5_4: # Parent Loop BB5_3 Depth=1
# => This Inner Loop Header: Depth=2
movl $.L.str, %edi
movq %r15, %rsi
xorl %eax, %eax
callq __isoc23_scanf
addq $4, %r15
decq %r12
jne .LBB5_4
# %bb.5: # %._crit_edge.i
# in Loop: Header=BB5_3 Depth=1
incq %r13
addl 40(%rsp), %ebp # 4-byte Folded Reload
cmpq %r14, %r13
jne .LBB5_3
# %bb.6: # %_Z11Read_matrixPfi.exit
movl $.Lstr.1, %edi
callq puts@PLT
movq 32(%rsp), %r15 # 8-byte Reload
movq %r14, %r12
.LBB5_7: # %.lr.ph.i37
# =>This Inner Loop Header: Depth=1
movl $.L.str, %edi
movq %r15, %rsi
xorl %eax, %eax
callq __isoc23_scanf
addq $4, %r15
decq %r12
jne .LBB5_7
# %bb.8:
movq 40(%rsp), %r13 # 8-byte Reload
movq 32(%rsp), %rbp # 8-byte Reload
jmp .LBB5_9
.LBB5_1: # %_Z11Read_matrixPfi.exit.thread
movl $.Lstr.1, %edi
callq puts@PLT
movl %r13d, %r14d
.LBB5_9: # %_Z11Read_vectorPfi.exit
movl $.L.str.7, %edi
movq %rbx, %rsi
movl %r13d, %edx
callq _Z12Print_matrixPcPfi
movl $.L.str.8, %edi
movq %rbp, %rsi
movl %r13d, %edx
callq _Z12Print_vectorPcPfi
movq %rbx, %r12
leaq 24(%rsp), %rdi
movq 48(%rsp), %rbx # 8-byte Reload
movq %rbx, %rsi
callq hipMalloc
leaq 16(%rsp), %rdi
movq 56(%rsp), %r15 # 8-byte Reload
movq %r15, %rsi
callq hipMalloc
leaq 8(%rsp), %rdi
movq %r15, %rsi
callq hipMalloc
leaq 24(%rsp), %rax
movq (%rax), %rdi
movq %r12, %rsi
movq %rbx, %rdx
movl $1, %ecx
callq hipMemcpy
leaq 16(%rsp), %rax
movq (%rax), %rdi
movq %rbp, %rsi
movq %r15, %rdx
movl $1, %ecx
callq hipMemcpy
btsq $32, %r14
movq %r14, %rdi
movl $1, %esi
movq %r14, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB5_11
# %bb.10:
movq 24(%rsp), %rdi
movq 16(%rsp), %rsi
movq 8(%rsp), %rdx
movl %r13d, %ecx
callq _Z29__device_stub__matrixVectMultPfS_S_i
.LBB5_11:
movq 8(%rsp), %rsi
movq 64(%rsp), %r14 # 8-byte Reload
movq %r14, %rdi
movq %r15, %rdx
movl $2, %ecx
callq hipMemcpy
movl $.L.str.9, %edi
movq %r14, %rsi
movl %r13d, %edx
callq _Z12Print_vectorPcPfi
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq %r12, %rdi
callq free
movq %rbp, %rdi
callq free
movq %r14, %rdi
callq free
xorl %eax, %eax
addq $72, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end5:
.size main, .Lfunc_end5-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
jne .LBB6_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, %rdi
movq %rax, __hip_gpubin_handle(%rip)
.LBB6_2:
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z14matrixVectMultPfS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end6:
.size __hip_module_ctor, .Lfunc_end6-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB7_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB7_2:
retq
.Lfunc_end7:
.size __hip_module_dtor, .Lfunc_end7-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z14matrixVectMultPfS_S_i,@object # @_Z14matrixVectMultPfS_S_i
.section .rodata,"a",@progbits
.globl _Z14matrixVectMultPfS_S_i
.p2align 3, 0x0
_Z14matrixVectMultPfS_S_i:
.quad _Z29__device_stub__matrixVectMultPfS_S_i
.size _Z14matrixVectMultPfS_S_i, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%f"
.size .L.str, 3
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "%.1f "
.size .L.str.2, 6
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "size = %d"
.size .L.str.4, 10
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "A ="
.size .L.str.7, 4
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "B ="
.size .L.str.8, 4
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "Result ="
.size .L.str.9, 9
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z14matrixVectMultPfS_S_i"
.size .L__unnamed_1, 26
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Matrix A: "
.size .Lstr, 11
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "Vector B: "
.size .Lstr.1, 11
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z29__device_stub__matrixVectMultPfS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z14matrixVectMultPfS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
```
| 6,295 | 7,352 |
240 |
Convert the following CUDA device assembly code to AMD device assembly:
```cudaasm
code for sm_80
Function : vector_add
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
MOV R1, c[0x0][0x28] ;
S2R R6, SR_CTAID.X ;
S2R R3, SR_TID.X ;
IMAD R6, R6, c[0x0][0x0], R3 ;
ISETP.GE.AND P0, PT, R6, c[0x0][0x178], PT ;
@P0 EXIT ;
HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ;
ULDC.64 UR4, c[0x0][0x118] ;
IMAD.WIDE R4, R6, R7, c[0x0][0x168] ;
IMAD.WIDE R2, R6.reuse, R7.reuse, c[0x0][0x160] ;
LDG.E R4, [R4.64] ;
LDG.E R3, [R2.64] ;
IMAD.WIDE R6, R6, R7, c[0x0][0x170] ;
FADD R9, R4, R3 ;
STG.E [R6.64], R9 ;
EXIT ;
BRA 0x100;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
Function : kernel1
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
MOV R1, c[0x0][0x28] ;
EXIT ;
BRA 0x20;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
```
|
```amdasm
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object ; @__hip_cuid_
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0 ; 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
```
| 484 | 306 |
241 |
Convert the following CUDA host assembly code to AMD host assembly:
```cudaasm
.file "tmpxft_000e66ba_00000000-6_kernel.cudafe1.cpp"
.text
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z26__device_stub__Z7kernel1PiPi
.type _Z26__device_stub__Z7kernel1PiPi, @function
_Z26__device_stub__Z7kernel1PiPi:
.LFB2051:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq kernel1(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z26__device_stub__Z7kernel1PiPi, .-_Z26__device_stub__Z7kernel1PiPi
.globl kernel1
.type kernel1, @function
kernel1:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z7kernel1PiPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size kernel1, .-kernel1
.globl _Z35__device_stub__Z10vector_addPfS_S_iPfS_S_i
.type _Z35__device_stub__Z10vector_addPfS_S_iPfS_S_i, @function
_Z35__device_stub__Z10vector_addPfS_S_iPfS_S_i:
.LFB2053:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq vector_add(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2053:
.size _Z35__device_stub__Z10vector_addPfS_S_iPfS_S_i, .-_Z35__device_stub__Z10vector_addPfS_S_iPfS_S_i
.globl vector_add
.type vector_add, @function
vector_add:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z10vector_addPfS_S_iPfS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size vector_add, .-vector_add
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "vector_add"
.LC1:
.string "kernel1"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2056:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq vector_add(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq kernel1(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2056:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
```
|
```amdasm
.text
.file "kernel.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
```
| 2,748 | 183 |
244 |
Convert the following CUDA device assembly code to AMD device assembly:
```cudaasm
code for sm_80
Function : _Z20Mask_Subtract_KernelPiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ;
S2R R0, SR_CTAID.X ;
HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ;
ULDC.64 UR4, c[0x0][0x118] ;
S2R R3, SR_TID.X ;
IMAD R0, R0, c[0x0][0x0], R3 ;
IMAD.WIDE R2, R0, R5, c[0x0][0x168] ;
LDG.E R2, [R2.64] ;
IMAD.WIDE R4, R0, R5, c[0x0][0x170] ;
ISETP.NE.AND P0, PT, R2, RZ, PT ;
@P0 STG.E [R4.64], RZ ;
@P0 EXIT ;
SHF.R.S32.HI R3, RZ, 0x1f, R0 ;
LEA R2, P0, R0, c[0x0][0x160], 0x2 ;
LEA.HI.X R3, R0, c[0x0][0x164], R3, 0x2, P0 ;
LDG.E R3, [R2.64] ;
STG.E [R4.64], R3 ;
EXIT ;
BRA 0x120;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
```
|
```amdasm
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z20Mask_Subtract_KernelPiS_S_ ; -- Begin function _Z20Mask_Subtract_KernelPiS_S_
.globl _Z20Mask_Subtract_KernelPiS_S_
.p2align 8
.type _Z20Mask_Subtract_KernelPiS_S_,@function
_Z20Mask_Subtract_KernelPiS_S_: ; @_Z20Mask_Subtract_KernelPiS_S_
; %bb.0:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x24
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
v_add_co_u32 v2, vcc_lo, s6, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v1, vcc_lo
global_load_b32 v2, v[2:3], off
s_waitcnt vmcnt(0)
v_cmp_eq_u32_e32 vcc_lo, 0, v2
v_mov_b32_e32 v2, 0
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_2
; %bb.1:
v_add_co_u32 v2, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
global_load_b32 v2, v[2:3], off
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s2
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z20Mask_Subtract_KernelPiS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z20Mask_Subtract_KernelPiS_S_, .Lfunc_end0-_Z20Mask_Subtract_KernelPiS_S_
; -- End function
.section .AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 172
; NumSgprs: 18
; NumVgprs: 4
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 4
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object ; @__hip_cuid_
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0 ; 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z20Mask_Subtract_KernelPiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z20Mask_Subtract_KernelPiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
```
| 462 | 2,567 |
245 |
Convert the following CUDA host assembly code to AMD host assembly:
```cudaasm
.file "tmpxft_00071861_00000000-6_Mask_Subtract_Kernel.cudafe1.cpp"
.text
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z44__device_stub__Z20Mask_Subtract_KernelPiS_S_PiS_S_
.type _Z44__device_stub__Z20Mask_Subtract_KernelPiS_S_PiS_S_, @function
_Z44__device_stub__Z20Mask_Subtract_KernelPiS_S_PiS_S_:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z20Mask_Subtract_KernelPiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z44__device_stub__Z20Mask_Subtract_KernelPiS_S_PiS_S_, .-_Z44__device_stub__Z20Mask_Subtract_KernelPiS_S_PiS_S_
.globl _Z20Mask_Subtract_KernelPiS_S_
.type _Z20Mask_Subtract_KernelPiS_S_, @function
_Z20Mask_Subtract_KernelPiS_S_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z44__device_stub__Z20Mask_Subtract_KernelPiS_S_PiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z20Mask_Subtract_KernelPiS_S_, .-_Z20Mask_Subtract_KernelPiS_S_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z20Mask_Subtract_KernelPiS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z20Mask_Subtract_KernelPiS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
```
|
```amdasm
.text
.file "Mask_Subtract_Kernel.hip"
.globl _Z35__device_stub__Mask_Subtract_KernelPiS_S_ # -- Begin function _Z35__device_stub__Mask_Subtract_KernelPiS_S_
.type _Z35__device_stub__Mask_Subtract_KernelPiS_S_,@function
_Z35__device_stub__Mask_Subtract_KernelPiS_S_: # @_Z35__device_stub__Mask_Subtract_KernelPiS_S_
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $112, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 40(%rsp), %rax
movq %rdi, (%rax)
leaq 32(%rsp), %rcx
movq %rsi, (%rcx)
leaq 24(%rsp), %rsi
movq %rdx, (%rsi)
leaq 80(%rsp), %rbx
movq %rax, (%rbx)
movq %rcx, 8(%rbx)
movq %rsi, 16(%rbx)
leaq 64(%rsp), %r14
leaq 48(%rsp), %r15
leaq 16(%rsp), %r12
leaq 8(%rsp), %r13
movq %r14, %rdi
movq %r15, %rsi
movq %r12, %rdx
movq %r13, %rcx
callq __hipPopCallConfiguration
movq (%r14), %rsi
movl 8(%r14), %edx
movq (%r15), %rcx
movl 8(%r15), %r8d
movl $_Z20Mask_Subtract_KernelPiS_S_, %edi
movq %rbx, %r9
pushq (%r13)
.cfi_adjust_cfa_offset 8
pushq (%r12)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $128, %rsp
.cfi_adjust_cfa_offset -128
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z35__device_stub__Mask_Subtract_KernelPiS_S_, .Lfunc_end0-_Z35__device_stub__Mask_Subtract_KernelPiS_S_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, %rdi
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z20Mask_Subtract_KernelPiS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z20Mask_Subtract_KernelPiS_S_,@object # @_Z20Mask_Subtract_KernelPiS_S_
.section .rodata,"a",@progbits
.globl _Z20Mask_Subtract_KernelPiS_S_
.p2align 3, 0x0
_Z20Mask_Subtract_KernelPiS_S_:
.quad _Z35__device_stub__Mask_Subtract_KernelPiS_S_
.size _Z20Mask_Subtract_KernelPiS_S_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z20Mask_Subtract_KernelPiS_S_"
.size .L__unnamed_1, 31
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z35__device_stub__Mask_Subtract_KernelPiS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z20Mask_Subtract_KernelPiS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
```
| 1,891 | 2,071 |
248 |
Convert the following CUDA device assembly code to AMD device assembly:
```cudaasm
code for sm_80
Function : _Z19gpu_constant_memoryPfS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
MOV R1, c[0x0][0x28] ;
S2R R4, SR_TID.X ;
HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ;
ULDC.64 UR4, c[0x0][0x118] ;
IMAD.WIDE R2, R4, R5, c[0x0][0x160] ;
LDG.E R3, [R2.64] ;
I2F R0, c[0x3][0x0] ;
IMAD.WIDE R4, R4, R5, c[0x0][0x168] ;
I2F R6, c[0x3][0x4] ;
FFMA R7, R0, R3, R6 ;
STG.E [R4.64], R7 ;
EXIT ;
BRA 0xc0;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
```
|
```amdasm
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z19gpu_constant_memoryPfS_ ; -- Begin function _Z19gpu_constant_memoryPfS_
.globl _Z19gpu_constant_memoryPfS_
.p2align 8
.type _Z19gpu_constant_memoryPfS_,@function
_Z19gpu_constant_memoryPfS_: ; @_Z19gpu_constant_memoryPfS_
; %bb.0:
s_load_b128 s[0:3], s[0:1], 0x0
v_lshlrev_b32_e32 v0, 2, v0
s_waitcnt lgkmcnt(0)
global_load_b32 v1, v0, s[0:1]
s_getpc_b64 s[0:1]
s_add_u32 s0, s0, constant_f@rel32@lo+4
s_addc_u32 s1, s1, constant_f@rel32@hi+12
s_getpc_b64 s[4:5]
s_add_u32 s4, s4, constant_g@rel32@lo+4
s_addc_u32 s5, s5, constant_g@rel32@hi+12
s_load_b32 s0, s[0:1], 0x0
s_load_b32 s1, s[4:5], 0x0
s_waitcnt lgkmcnt(0)
v_cvt_f32_i32_e32 v2, s0
v_cvt_f32_i32_e32 v3, s1
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_fmac_f32_e32 v3, v1, v2
global_store_b32 v0, v3, s[2:3]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z19gpu_constant_memoryPfS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 16
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 6
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z19gpu_constant_memoryPfS_, .Lfunc_end0-_Z19gpu_constant_memoryPfS_
; -- End function
.section .AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 124
; NumSgprs: 6
; NumVgprs: 4
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 0
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 6
; NumVGPRsForWavesPerEU: 4
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.protected constant_f ; @constant_f
.type constant_f,@object
.section .bss,"aw",@nobits
.globl constant_f
.p2align 2, 0x0
constant_f:
.long 0 ; 0x0
.size constant_f, 4
.protected constant_g ; @constant_g
.type constant_g,@object
.globl constant_g
.p2align 2, 0x0
constant_g:
.long 0 ; 0x0
.size constant_g, 4
.type __hip_cuid_,@object ; @__hip_cuid_
.globl __hip_cuid_
__hip_cuid_:
.byte 0 ; 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym constant_f
.addrsig_sym constant_g
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 16
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z19gpu_constant_memoryPfS_
.private_segment_fixed_size: 0
.sgpr_count: 6
.sgpr_spill_count: 0
.symbol: _Z19gpu_constant_memoryPfS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
```
| 318 | 2,069 |
249 |
Convert the following CUDA host assembly code to AMD host assembly:
```cudaasm
.file "tmpxft_001772fc_00000000-6_3_05_memory_constant_gpu.cudafe1.cpp"
.text
.globl _ZSt21ios_base_library_initv
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z41__device_stub__Z19gpu_constant_memoryPfS_PfS_
.type _Z41__device_stub__Z19gpu_constant_memoryPfS_PfS_, @function
_Z41__device_stub__Z19gpu_constant_memoryPfS_PfS_:
.LFB3694:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z19gpu_constant_memoryPfS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3694:
.size _Z41__device_stub__Z19gpu_constant_memoryPfS_PfS_, .-_Z41__device_stub__Z19gpu_constant_memoryPfS_PfS_
.globl _Z19gpu_constant_memoryPfS_
.type _Z19gpu_constant_memoryPfS_, @function
_Z19gpu_constant_memoryPfS_:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z41__device_stub__Z19gpu_constant_memoryPfS_PfS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _Z19gpu_constant_memoryPfS_, .-_Z19gpu_constant_memoryPfS_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC5:
.string "Use of Constant memory on GPU \n"
.align 8
.LC6:
.string "The expression for input %f is %f\n"
.text
.globl main
.type main, @function
main:
.LFB3669:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $120, %rsp
.cfi_def_cfa_offset 144
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
movl $2, (%rsp)
movl $20, 4(%rsp)
leaq 8(%rsp), %rdi
movl $20, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $20, %esi
call cudaMalloc@PLT
movl $0x00000000, 48(%rsp)
movl $0x3f800000, 52(%rsp)
movl $0x40000000, 56(%rsp)
movl $0x40400000, 60(%rsp)
movl $0x40800000, 64(%rsp)
leaq 48(%rsp), %rsi
movl $1, %ecx
movl $20, %edx
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movq %rsp, %rsi
movl $1, %r8d
movl $0, %ecx
movl $4, %edx
leaq _ZL10constant_f(%rip), %rdi
call cudaMemcpyToSymbol@PLT
leaq 4(%rsp), %rsi
movl $1, %r8d
movl $0, %ecx
movl $4, %edx
leaq _ZL10constant_g(%rip), %rdi
call cudaMemcpyToSymbol@PLT
movl $5, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 36(%rsp), %rdx
movl $1, %ecx
movq 24(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L17
.L12:
leaq 80(%rsp), %rdi
movl $2, %ecx
movl $20, %edx
movq 16(%rsp), %rsi
call cudaMemcpy@PLT
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %ebx
leaq .LC6(%rip), %rbp
.L13:
pxor %xmm0, %xmm0
cvtss2sd 48(%rsp,%rbx), %xmm0
pxor %xmm1, %xmm1
cvtss2sd 80(%rsp,%rbx), %xmm1
movq %rbp, %rsi
movl $2, %edi
movl $2, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq $20, %rbx
jne .L13
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L18
movl $0, %eax
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L17:
.cfi_restore_state
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z41__device_stub__Z19gpu_constant_memoryPfS_PfS_
jmp .L12
.L18:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC7:
.string "_Z19gpu_constant_memoryPfS_"
.LC8:
.string "constant_f"
.LC9:
.string "constant_g"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3697:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _Z19gpu_constant_memoryPfS_(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $4, %r9d
movl $0, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _ZL10constant_f(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $4, %r9d
movl $0, %r8d
leaq .LC9(%rip), %rdx
movq %rdx, %rcx
leaq _ZL10constant_g(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZL10constant_g
.comm _ZL10constant_g,4,4
.local _ZL10constant_f
.comm _ZL10constant_f,4,4
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
```
|
```amdasm
.text
.file "3_05_memory_constant_gpu.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z34__device_stub__gpu_constant_memoryPfS_ # -- Begin function _Z34__device_stub__gpu_constant_memoryPfS_
.type _Z34__device_stub__gpu_constant_memoryPfS_,@function
_Z34__device_stub__gpu_constant_memoryPfS_: # @_Z34__device_stub__gpu_constant_memoryPfS_
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $80, %rsp
.cfi_def_cfa_offset 128
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 24(%rsp), %rax
movq %rdi, (%rax)
leaq 16(%rsp), %rcx
movq %rsi, (%rcx)
leaq 64(%rsp), %rbx
movq %rax, (%rbx)
movq %rcx, 8(%rbx)
leaq 48(%rsp), %r14
leaq 32(%rsp), %r15
leaq 8(%rsp), %r12
movq %rsp, %r13
movq %r14, %rdi
movq %r15, %rsi
movq %r12, %rdx
movq %r13, %rcx
callq __hipPopCallConfiguration
movq (%r14), %rsi
movl 8(%r14), %edx
movq (%r15), %rcx
movl 8(%r15), %r8d
movl $_Z19gpu_constant_memoryPfS_, %edi
movq %rbx, %r9
pushq (%r13)
.cfi_adjust_cfa_offset 8
pushq (%r12)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $96, %rsp
.cfi_adjust_cfa_offset -96
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z34__device_stub__gpu_constant_memoryPfS_, .Lfunc_end0-_Z34__device_stub__gpu_constant_memoryPfS_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $96, %rsp
.cfi_def_cfa_offset 112
.cfi_offset %rbx, -16
movl $2, 28(%rsp)
movl $20, 24(%rsp)
leaq 16(%rsp), %rdi
movl $20, %esi
callq hipMalloc
leaq 8(%rsp), %rdi
movl $20, %esi
callq hipMalloc
xorl %eax, %eax
.LBB1_1: # =>This Inner Loop Header: Depth=1
movl %eax, %ecx
xorps %xmm0, %xmm0
cvtsi2ss %rcx, %xmm0
movss %xmm0, 32(%rsp,%rax,4)
incq %rax
cmpq $5, %rax
jne .LBB1_1
# %bb.2:
movq 16(%rsp), %rdi
leaq 32(%rsp), %rsi
movl $20, %edx
movl $1, %ecx
callq hipMemcpy
leaq 28(%rsp), %rsi
movl $constant_f, %edi
movl $4, %edx
xorl %ecx, %ecx
movl $1, %r8d
callq hipMemcpyToSymbol
leaq 24(%rsp), %rsi
movl $constant_g, %edi
movl $4, %edx
xorl %ecx, %ecx
movl $1, %r8d
callq hipMemcpyToSymbol
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 4(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq 16(%rsp), %rdi
movq 8(%rsp), %rsi
callq _Z34__device_stub__gpu_constant_memoryPfS_
.LBB1_4:
movq 8(%rsp), %rsi
leaq 64(%rsp), %rdi
movl $20, %edx
movl $2, %ecx
callq hipMemcpy
movl $.Lstr, %edi
callq puts@PLT
xorl %ebx, %ebx
.LBB1_5: # =>This Inner Loop Header: Depth=1
xorps %xmm0, %xmm0
cvtss2sd 32(%rsp,%rbx,4), %xmm0
xorps %xmm1, %xmm1
cvtss2sd 64(%rsp,%rbx,4), %xmm1
movl $.L.str.1, %edi
movb $2, %al
callq printf
incq %rbx
cmpq $5, %rbx
jne .LBB1_5
# %bb.6:
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $96, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
movq __hip_gpubin_handle(%rip), %rbx
testq %rbx, %rbx
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, %rbx
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
subq $32, %rsp
.cfi_adjust_cfa_offset 32
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z19gpu_constant_memoryPfS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
addq $32, %rsp
.cfi_adjust_cfa_offset -32
movl $constant_f, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movl $4, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
pushq $0
.cfi_adjust_cfa_offset 8
pushq $1
.cfi_adjust_cfa_offset 8
callq __hipRegisterVar
addq $16, %rsp
.cfi_adjust_cfa_offset -16
movl $constant_g, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movl $4, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
pushq $0
.cfi_adjust_cfa_offset 8
pushq $1
.cfi_adjust_cfa_offset 8
callq __hipRegisterVar
addq $16, %rsp
.cfi_adjust_cfa_offset -16
movl $__hip_module_dtor, %edi
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type constant_f,@object # @constant_f
.local constant_f
.comm constant_f,4,4
.type constant_g,@object # @constant_g
.local constant_g
.comm constant_g,4,4
.type _Z19gpu_constant_memoryPfS_,@object # @_Z19gpu_constant_memoryPfS_
.section .rodata,"a",@progbits
.globl _Z19gpu_constant_memoryPfS_
.p2align 3, 0x0
_Z19gpu_constant_memoryPfS_:
.quad _Z34__device_stub__gpu_constant_memoryPfS_
.size _Z19gpu_constant_memoryPfS_, 8
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "The expression for input %f is %f\n"
.size .L.str.1, 35
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z19gpu_constant_memoryPfS_"
.size .L__unnamed_1, 28
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "constant_f"
.size .L__unnamed_2, 11
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "constant_g"
.size .L__unnamed_3, 11
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Use of Constant memory on GPU "
.size .Lstr, 31
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z34__device_stub__gpu_constant_memoryPfS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym constant_f
.addrsig_sym constant_g
.addrsig_sym _Z19gpu_constant_memoryPfS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
```
| 3,424 | 3,583 |
250 |
Convert the following CUDA device assembly code to AMD device assembly:
```cudaasm
code for sm_80
Function : _Z15calcIntegralGPUPfflii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ;
S2R R0, SR_CTAID.X ;
S2R R3, SR_TID.X ;
IMAD R0, R0, c[0x0][0x0], R3 ;
ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x170], PT ;
SHF.R.S32.HI R3, RZ, 0x1f, R0 ;
ISETP.GE.AND.EX P0, PT, R3, c[0x0][0x174], PT, P0 ;
@P0 EXIT ;
LEA R2, P0, R0, c[0x0][0x160], 0x2 ;
ULDC.64 UR6, c[0x0][0x118] ;
LEA.HI.X R3, R0, c[0x0][0x164], R3, 0x2, P0 ;
LDG.E R5, [R2.64] ;
BSSY B2, 0x280 ;
I2F R4, R0 ;
UMOV UR4, 0x40800000 ;
BSSY B1, 0x200 ;
IMAD.U32 R9, RZ, RZ, UR4 ;
FADD R4, R4, 0.5 ;
FMUL R4, R4, c[0x0][0x168] ;
FFMA R8, R4, R4, 1 ;
MUFU.RCP R4, R8 ;
FCHK P0, R9, R8 ;
FFMA R7, -R8, R4, 1 ;
FFMA R7, R4, R7, R4 ;
FFMA R4, R7, 4, RZ ;
FFMA R6, -R8, R4, 4 ;
FFMA R4, R7, R6, R4 ;
@!P0 BRA 0x1f0 ;
MOV R4, 0x1e0 ;
CALL.REL.NOINC 0x2a0 ;
IMAD.MOV.U32 R4, RZ, RZ, R8 ;
BSYNC B1 ;
IMAD.MOV.U32 R7, RZ, RZ, c[0x0][0x17c] ;
FADD R5, R4, R5 ;
IMAD R0, R7, c[0x0][0x178], R0 ;
ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x170], PT ;
SHF.R.S32.HI R6, RZ, 0x1f, R0 ;
ISETP.GE.AND.EX P0, PT, R6, c[0x0][0x174], PT, P0 ;
@!P0 BRA 0xd0 ;
BSYNC B2 ;
STG.E [R2.64], R5 ;
EXIT ;
SHF.R.U32.HI R6, RZ, 0x17, R8 ;
BSSY B0, 0x880 ;
BSSY B3, 0x470 ;
LOP3.LUT R10, R6, 0xff, RZ, 0xc0, !PT ;
IADD3 R9, R10, -0x1, RZ ;
ISETP.GT.U32.AND P0, PT, R9, 0xfd, PT ;
@!P0 IMAD.MOV.U32 R7, RZ, RZ, RZ ;
@!P0 BRA 0x460 ;
FSETP.GTU.FTZ.AND P0, PT, |R8|, +INF , PT ;
IMAD.MOV.U32 R6, RZ, RZ, R8 ;
@P0 BREAK B3 ;
@P0 BRA 0x860 ;
IMAD.MOV.U32 R7, RZ, RZ, 0x40800000 ;
LOP3.LUT P0, RZ, R8, 0x7fffffff, R7, 0xc8, !PT ;
@!P0 BREAK B3 ;
@!P0 BRA 0x840 ;
FSETP.NEU.FTZ.AND P0, PT, |R6|, +INF , PT ;
LOP3.LUT P1, RZ, R7, 0x7fffffff, RZ, 0xc0, !PT ;
PLOP3.LUT P0, PT, P0, P1, PT, 0x2a, 0x0 ;
@P0 BREAK B3 ;
@P0 BRA 0x820 ;
LOP3.LUT P0, RZ, R8, 0x7fffffff, RZ, 0xc0, !PT ;
@!P0 BREAK B3 ;
@!P0 BRA 0x7f0 ;
ISETP.GE.AND P0, PT, R9, RZ, PT ;
IMAD.MOV.U32 R7, RZ, RZ, RZ ;
@!P0 FFMA R8, R6, 1.84467440737095516160e+19, RZ ;
@!P0 IADD3 R7, R7, 0x40, RZ ;
BSYNC B3 ;
LEA R9, R10, 0xc0800000, 0x17 ;
UMOV UR4, 0x40800000 ;
IADD3 R7, R7, 0x81, -R10 ;
UIADD3 UR4, UR4, -0x1000000, URZ ;
BSSY B3, 0x7e0 ;
IMAD.IADD R9, R8, 0x1, -R9 ;
MUFU.RCP R6, R9 ;
FADD.FTZ R11, -R9, -RZ ;
FFMA R13, R6, R11, 1 ;
FFMA R12, R6, R13, R6 ;
FFMA R6, R12, UR4, RZ ;
FFMA R13, R11, R6, UR4 ;
FFMA R13, R12, R13, R6 ;
FFMA R11, R11, R13, UR4 ;
FFMA R6, R12, R11, R13 ;
SHF.R.U32.HI R8, RZ, 0x17, R6 ;
LOP3.LUT R8, R8, 0xff, RZ, 0xc0, !PT ;
IMAD.IADD R14, R8, 0x1, R7 ;
IADD3 R8, R14, -0x1, RZ ;
ISETP.GE.U32.AND P0, PT, R8, 0xfe, PT ;
@!P0 BRA 0x7c0 ;
ISETP.GT.AND P0, PT, R14, 0xfe, PT ;
@P0 BRA 0x790 ;
ISETP.GE.AND P0, PT, R14, 0x1, PT ;
@P0 BRA 0x7d0 ;
ISETP.GE.AND P0, PT, R14, -0x18, PT ;
LOP3.LUT R6, R6, 0x80000000, RZ, 0xc0, !PT ;
@!P0 BRA 0x7d0 ;
FFMA.RZ R7, R12, R11.reuse, R13.reuse ;
IADD3 R10, R14, 0x20, RZ ;
FFMA.RM R8, R12, R11.reuse, R13.reuse ;
ISETP.NE.AND P2, PT, R14, RZ, PT ;
LOP3.LUT R9, R7, 0x7fffff, RZ, 0xc0, !PT ;
FFMA.RP R7, R12, R11, R13 ;
ISETP.NE.AND P1, PT, R14, RZ, PT ;
IMAD.MOV R11, RZ, RZ, -R14 ;
LOP3.LUT R9, R9, 0x800000, RZ, 0xfc, !PT ;
FSETP.NEU.FTZ.AND P0, PT, R7, R8, PT ;
SHF.L.U32 R10, R9, R10, RZ ;
SEL R8, R11, RZ, P2 ;
ISETP.NE.AND P1, PT, R10, RZ, P1 ;
SHF.R.U32.HI R8, RZ, R8, R9 ;
PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ;
SHF.R.U32.HI R10, RZ, 0x1, R8 ;
SEL R7, RZ, 0x1, !P0 ;
LOP3.LUT R7, R7, 0x1, R10, 0xf8, !PT ;
LOP3.LUT R7, R7, R8, RZ, 0xc0, !PT ;
IMAD.IADD R7, R10, 0x1, R7 ;
LOP3.LUT R6, R7, R6, RZ, 0xfc, !PT ;
BRA 0x7d0 ;
LOP3.LUT R6, R6, 0x80000000, RZ, 0xc0, !PT ;
LOP3.LUT R6, R6, 0x7f800000, RZ, 0xfc, !PT ;
BRA 0x7d0 ;
IMAD R6, R7, 0x800000, R6 ;
BSYNC B3 ;
BRA 0x870 ;
LOP3.LUT R6, R8, 0x80000000, R7, 0x48, !PT ;
LOP3.LUT R6, R6, 0x7f800000, RZ, 0xfc, !PT ;
BRA 0x870 ;
LOP3.LUT R6, R8, 0x80000000, R7, 0x48, !PT ;
BRA 0x870 ;
MUFU.RSQ R6, -QNAN ;
BRA 0x870 ;
FADD.FTZ R6, R6, 4 ;
BSYNC B0 ;
IMAD.MOV.U32 R8, RZ, RZ, R6 ;
IMAD.MOV.U32 R6, RZ, RZ, R4 ;
IMAD.MOV.U32 R7, RZ, RZ, 0x0 ;
RET.REL.NODEC R6 0x0 ;
BRA 0x8c0;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
```
|
```amdasm
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z15calcIntegralGPUPfflii ; -- Begin function _Z15calcIntegralGPUPfflii
.globl _Z15calcIntegralGPUPfflii
.p2align 8
.type _Z15calcIntegralGPUPfflii,@function
_Z15calcIntegralGPUPfflii: ; @_Z15calcIntegralGPUPfflii
; %bb.0:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x2c
s_load_b64 s[2:3], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
s_mul_i32 s15, s15, s4
s_mov_b32 s4, exec_lo
v_add_nc_u32_e32 v1, s15, v0
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i64_e64 s[2:3], v[1:2]
s_cbranch_execz .LBB0_4
; %bb.1: ; %.lr.ph
s_load_b64 s[6:7], s[0:1], 0x0
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_clause 0x1
s_load_b32 s4, s[0:1], 0x8
s_load_b64 s[0:1], s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_add_co_u32 v1, vcc_lo, s6, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s7, v2, vcc_lo
s_mul_i32 s1, s1, s0
s_mov_b32 s6, 0
v_add3_u32 v0, s15, s1, v0
global_load_b32 v5, v[1:2], off
s_ashr_i32 s5, s1, 31
v_ashrrev_i32_e32 v4, 31, v0
v_sub_co_u32 v3, vcc_lo, v0, s1
s_delay_alu instid0(VALU_DEP_2)
v_subrev_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
.LBB0_2: ; =>This Inner Loop Header: Depth=1
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cvt_f32_i32_e32 v0, v3
v_add_co_u32 v3, s0, v3, s1
v_add_f32_e32 v0, 0.5, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v0, s4, v0
v_fma_f32 v0, v0, v0, 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_div_scale_f32 v6, null, v0, v0, 4.0
v_div_scale_f32 v9, vcc_lo, 4.0, v0, 4.0
v_rcp_f32_e32 v7, v6
s_waitcnt_depctr 0xfff
v_fma_f32 v8, -v6, v7, 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v7, v8, v7
v_mul_f32_e32 v8, v9, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v10, -v6, v8, v9
v_fmac_f32_e32 v8, v10, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v6, -v6, v8, v9
v_div_fmas_f32 v6, v6, v7, v8
v_add_co_ci_u32_e64 v4, vcc_lo, s5, v4, s0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_div_fixup_f32 v0, v6, v0, 4.0
v_cmp_le_i64_e32 vcc_lo, s[2:3], v[3:4]
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_add_f32_e32 v5, v0, v5
s_or_b32 s6, vcc_lo, s6
s_and_not1_b32 exec_lo, exec_lo, s6
s_cbranch_execnz .LBB0_2
; %bb.3: ; %._crit_edge
s_or_b32 exec_lo, exec_lo, s6
global_store_b32 v[1:2], v5, off
.LBB0_4: ; %Flow
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z15calcIntegralGPUPfflii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 11
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z15calcIntegralGPUPfflii, .Lfunc_end0-_Z15calcIntegralGPUPfflii
; -- End function
.section .AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 364
; NumSgprs: 18
; NumVgprs: 11
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 11
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object ; @__hip_cuid_
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0 ; 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 16
.size: 8
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z15calcIntegralGPUPfflii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z15calcIntegralGPUPfflii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 11
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
```
| 2,696 | 3,397 |
251 |
Convert the following CUDA host assembly code to AMD host assembly:
```cudaasm
.file "tmpxft_00107ea0_00000000-6_calcIntegralGPU.cudafe1.cpp"
.text
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2030:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z1ff
.type _Z1ff, @function
_Z1ff:
.LFB2027:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2027:
.size _Z1ff, .-_Z1ff
.globl _Z39__device_stub__Z15calcIntegralGPUPffliiPfflii
.type _Z39__device_stub__Z15calcIntegralGPUPffliiPfflii, @function
_Z39__device_stub__Z15calcIntegralGPUPffliiPfflii:
.LFB2052:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movss %xmm0, 20(%rsp)
movq %rsi, 8(%rsp)
movl %edx, 16(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 16(%rsp), %rax
movq %rax, 120(%rsp)
leaq 4(%rsp), %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L9
.L5:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L10
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L9:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z15calcIntegralGPUPfflii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L5
.L10:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2052:
.size _Z39__device_stub__Z15calcIntegralGPUPffliiPfflii, .-_Z39__device_stub__Z15calcIntegralGPUPffliiPfflii
.globl _Z15calcIntegralGPUPfflii
.type _Z15calcIntegralGPUPfflii, @function
_Z15calcIntegralGPUPfflii:
.LFB2053:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z39__device_stub__Z15calcIntegralGPUPffliiPfflii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2053:
.size _Z15calcIntegralGPUPfflii, .-_Z15calcIntegralGPUPfflii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z15calcIntegralGPUPfflii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2055:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z15calcIntegralGPUPfflii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2055:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
```
|
```amdasm
.text
.file "calcIntegralGPU.hip"
.globl _Z30__device_stub__calcIntegralGPUPfflii # -- Begin function _Z30__device_stub__calcIntegralGPUPfflii
.type _Z30__device_stub__calcIntegralGPUPfflii,@function
_Z30__device_stub__calcIntegralGPUPfflii: # @_Z30__device_stub__calcIntegralGPUPfflii
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $128, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 40(%rsp), %rax
movq %rdi, (%rax)
leaq 12(%rsp), %rdi
movss %xmm0, (%rdi)
leaq 32(%rsp), %r8
movq %rsi, (%r8)
leaq 8(%rsp), %rsi
movl %edx, (%rsi)
leaq 4(%rsp), %rdx
movl %ecx, (%rdx)
leaq 80(%rsp), %rbx
movq %rax, (%rbx)
movq %rdi, 8(%rbx)
movq %r8, 16(%rbx)
movq %rsi, 24(%rbx)
movq %rdx, 32(%rbx)
leaq 64(%rsp), %r14
leaq 48(%rsp), %r15
leaq 24(%rsp), %r12
leaq 16(%rsp), %r13
movq %r14, %rdi
movq %r15, %rsi
movq %r12, %rdx
movq %r13, %rcx
callq __hipPopCallConfiguration
movq (%r14), %rsi
movl 8(%r14), %edx
movq (%r15), %rcx
movl 8(%r15), %r8d
movl $_Z15calcIntegralGPUPfflii, %edi
movq %rbx, %r9
pushq (%r13)
.cfi_adjust_cfa_offset 8
pushq (%r12)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $144, %rsp
.cfi_adjust_cfa_offset -144
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z30__device_stub__calcIntegralGPUPfflii, .Lfunc_end0-_Z30__device_stub__calcIntegralGPUPfflii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, %rdi
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15calcIntegralGPUPfflii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z15calcIntegralGPUPfflii,@object # @_Z15calcIntegralGPUPfflii
.section .rodata,"a",@progbits
.globl _Z15calcIntegralGPUPfflii
.p2align 3, 0x0
_Z15calcIntegralGPUPfflii:
.quad _Z30__device_stub__calcIntegralGPUPfflii
.size _Z15calcIntegralGPUPfflii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z15calcIntegralGPUPfflii"
.size .L__unnamed_1, 26
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z30__device_stub__calcIntegralGPUPfflii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z15calcIntegralGPUPfflii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
```
| 2,086 | 2,119 |
252 |
Convert the following CUDA device assembly code to AMD device assembly:
```cudaasm
code for sm_80
Function : _Z11gaussjordanPdS_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ;
S2R R13, SR_CTAID.Y ;
S2R R2, SR_TID.Y ;
S2R R0, SR_CTAID.X ;
S2R R3, SR_TID.X ;
IMAD R13, R13, c[0x0][0x4], R2 ;
ISETP.GE.AND P0, PT, R13, c[0x0][0x170], PT ;
IMAD R0, R0, c[0x0][0x0], R3 ;
ISETP.GE.OR P0, PT, R0, c[0x0][0x170], P0 ;
ISETP.EQ.OR P0, PT, R0, c[0x0][0x174], P0 ;
@P0 EXIT ;
MOV R4, c[0x0][0x174] ;
IMAD.MOV.U32 R5, RZ, RZ, 0x8 ;
ULDC.64 UR4, c[0x0][0x118] ;
IMAD R14, R0, c[0x0][0x170], R13.reuse ;
IMAD R12, R4, c[0x0][0x170], R13 ;
IMAD R4, R0, c[0x0][0x170], R4 ;
IMAD.WIDE R8, R14, R5, c[0x0][0x168] ;
IMAD.WIDE R2, R12, R5.reuse, c[0x0][0x168] ;
LDG.E.64 R10, [R8.64] ;
IMAD.WIDE R4, R4, R5, c[0x0][0x160] ;
LDG.E.64 R2, [R2.64] ;
LDG.E.64 R6, [R4.64] ;
ISETP.NE.AND P0, PT, R13, c[0x0][0x174], PT ;
DFMA R6, R6, -R2, R10 ;
STG.E.64 [R8.64], R6 ;
@!P0 EXIT ;
SHF.R.S32.HI R3, RZ, 0x1f, R12 ;
LDG.E.64 R4, [R4.64] ;
LEA R10, P0, R12, c[0x0][0x160], 0x3 ;
SHF.R.S32.HI R7, RZ, 0x1f, R14 ;
LEA R6, P1, R14, c[0x0][0x160], 0x3 ;
LEA.HI.X R11, R12, c[0x0][0x164], R3, 0x3, P0 ;
LEA.HI.X R7, R14, c[0x0][0x164], R7, 0x3, P1 ;
LDG.E.64 R2, [R10.64] ;
LDG.E.64 R8, [R6.64] ;
DFMA R2, R4, -R2, R8 ;
STG.E.64 [R6.64], R2 ;
EXIT ;
BRA 0x270;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
```
|
```amdasm
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z11gaussjordanPdS_ii ; -- Begin function _Z11gaussjordanPdS_ii
.globl _Z11gaussjordanPdS_ii
.p2align 8
.type _Z11gaussjordanPdS_ii,@function
_Z11gaussjordanPdS_ii: ; @_Z11gaussjordanPdS_ii
; %bb.0:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b64 s[4:5], s[0:1], 0x10
v_and_b32_e32 v1, 0x3ff, v0
v_bfe_u32 v4, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_lshr_b32 s3, s2, 16
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[2:3], null, s14, s2, v[1:2]
v_mad_u64_u32 v[0:1], null, s15, s3, v[4:5]
v_cmp_ne_u32_e64 s2, s5, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_max_i32_e32 v1, v2, v0
v_cmp_gt_i32_e32 vcc_lo, s4, v1
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, s2, vcc_lo
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_3
; %bb.1:
v_mul_lo_u32 v4, v2, s4
s_load_b128 s[0:3], s[0:1], 0x0
v_mad_u64_u32 v[1:2], null, s5, s4, v[0:1]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_nc_u32_e32 v3, s5, v4
v_add_nc_u32_e32 v5, v4, v0
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_ashrrev_i32_e32 v4, 31, v3
v_ashrrev_i32_e32 v6, 31, v5
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[1:2], 3, v[1:2]
v_lshlrev_b64 v[3:4], 3, v[3:4]
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[5:6], 3, v[5:6]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v7, vcc_lo, s2, v1
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_ci_u32_e32 v8, vcc_lo, s3, v2, vcc_lo
v_add_co_u32 v3, vcc_lo, s0, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo
v_add_co_u32 v9, vcc_lo, s2, v5
v_add_co_ci_u32_e32 v10, vcc_lo, s3, v6, vcc_lo
global_load_b64 v[11:12], v[3:4], off
s_clause 0x1
global_load_b64 v[7:8], v[7:8], off
global_load_b64 v[13:14], v[9:10], off
v_cmp_ne_u32_e32 vcc_lo, s5, v0
s_waitcnt vmcnt(0)
v_fma_f64 v[7:8], -v[7:8], v[11:12], v[13:14]
global_store_b64 v[9:10], v[7:8], off
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_3
; %bb.2:
v_add_co_u32 v5, vcc_lo, s0, v5
v_add_co_ci_u32_e32 v6, vcc_lo, s1, v6, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v1
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v2, vcc_lo
s_clause 0x2
global_load_b64 v[7:8], v[5:6], off
global_load_b64 v[0:1], v[0:1], off
global_load_b64 v[2:3], v[3:4], off
s_waitcnt vmcnt(0)
v_fma_f64 v[0:1], -v[0:1], v[2:3], v[7:8]
global_store_b64 v[5:6], v[0:1], off
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11gaussjordanPdS_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 15
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z11gaussjordanPdS_ii, .Lfunc_end0-_Z11gaussjordanPdS_ii
; -- End function
.section .AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 380
; NumSgprs: 18
; NumVgprs: 15
; ScratchSize: 0
; MemoryBound: 1
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 15
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object ; @__hip_cuid_
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0 ; 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11gaussjordanPdS_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z11gaussjordanPdS_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 15
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
```
| 906 | 3,408 |
253 |
Convert the following CUDA host assembly code to AMD host assembly:
```cudaasm
.file "tmpxft_0015c2be_00000000-6_gaussjordan.cudafe1.cpp"
.text
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z35__device_stub__Z11gaussjordanPdS_iiPdS_ii
.type _Z35__device_stub__Z11gaussjordanPdS_iiPdS_ii, @function
_Z35__device_stub__Z11gaussjordanPdS_iiPdS_ii:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z11gaussjordanPdS_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z35__device_stub__Z11gaussjordanPdS_iiPdS_ii, .-_Z35__device_stub__Z11gaussjordanPdS_iiPdS_ii
.globl _Z11gaussjordanPdS_ii
.type _Z11gaussjordanPdS_ii, @function
_Z11gaussjordanPdS_ii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z11gaussjordanPdS_iiPdS_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z11gaussjordanPdS_ii, .-_Z11gaussjordanPdS_ii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z11gaussjordanPdS_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z11gaussjordanPdS_ii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
```
|
```amdasm
.text
.file "gaussjordan.hip"
.globl _Z26__device_stub__gaussjordanPdS_ii # -- Begin function _Z26__device_stub__gaussjordanPdS_ii
.type _Z26__device_stub__gaussjordanPdS_ii,@function
_Z26__device_stub__gaussjordanPdS_ii: # @_Z26__device_stub__gaussjordanPdS_ii
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $112, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 40(%rsp), %rax
movq %rdi, (%rax)
leaq 32(%rsp), %rdi
movq %rsi, (%rdi)
leaq 12(%rsp), %rsi
movl %edx, (%rsi)
leaq 8(%rsp), %rdx
movl %ecx, (%rdx)
leaq 80(%rsp), %rbx
movq %rax, (%rbx)
movq %rdi, 8(%rbx)
movq %rsi, 16(%rbx)
movq %rdx, 24(%rbx)
leaq 64(%rsp), %r14
leaq 48(%rsp), %r15
leaq 24(%rsp), %r12
leaq 16(%rsp), %r13
movq %r14, %rdi
movq %r15, %rsi
movq %r12, %rdx
movq %r13, %rcx
callq __hipPopCallConfiguration
movq (%r14), %rsi
movl 8(%r14), %edx
movq (%r15), %rcx
movl 8(%r15), %r8d
movl $_Z11gaussjordanPdS_ii, %edi
movq %rbx, %r9
pushq (%r13)
.cfi_adjust_cfa_offset 8
pushq (%r12)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $128, %rsp
.cfi_adjust_cfa_offset -128
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z26__device_stub__gaussjordanPdS_ii, .Lfunc_end0-_Z26__device_stub__gaussjordanPdS_ii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, %rdi
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11gaussjordanPdS_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z11gaussjordanPdS_ii,@object # @_Z11gaussjordanPdS_ii
.section .rodata,"a",@progbits
.globl _Z11gaussjordanPdS_ii
.p2align 3, 0x0
_Z11gaussjordanPdS_ii:
.quad _Z26__device_stub__gaussjordanPdS_ii
.size _Z11gaussjordanPdS_ii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z11gaussjordanPdS_ii"
.size .L__unnamed_1, 22
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z26__device_stub__gaussjordanPdS_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z11gaussjordanPdS_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
```
| 1,934 | 2,121 |
254 |
Convert the following CUDA device assembly code to AMD device assembly:
```cudaasm
code for sm_80
Function : _Z10kernel_modi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
MOV R1, c[0x0][0x28] ;
BAR.SYNC.DEFER_BLOCKING 0x0 ;
EXIT ;
BRA 0x30;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
```
|
```amdasm
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10kernel_modi ; -- Begin function _Z10kernel_modi
.globl _Z10kernel_modi
.p2align 8
.type _Z10kernel_modi,@function
_Z10kernel_modi: ; @_Z10kernel_modi
; %bb.0:
s_barrier
buffer_gl0_inv
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10kernel_modi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 4
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 1
.amdhsa_next_free_sgpr 1
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10kernel_modi, .Lfunc_end0-_Z10kernel_modi
; -- End function
.section .AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 16
; NumSgprs: 0
; NumVgprs: 0
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 0
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 1
; NumVGPRsForWavesPerEU: 1
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object ; @__hip_cuid_
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0 ; 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 4
.kernarg_segment_size: 4
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10kernel_modi
.private_segment_fixed_size: 0
.sgpr_count: 0
.sgpr_spill_count: 0
.symbol: _Z10kernel_modi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 0
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
```
| 130 | 1,512 |
255 |
Convert the following CUDA host assembly code to AMD host assembly:
```cudaasm
.file "tmpxft_000504e6_00000000-6_lab5.cudafe1.cpp"
.text
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z29__device_stub__Z10kernel_modii
.type _Z29__device_stub__Z10kernel_modii, @function
_Z29__device_stub__Z10kernel_modii:
.LFB2082:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movl %edi, 12(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z10kernel_modi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z29__device_stub__Z10kernel_modii, .-_Z29__device_stub__Z10kernel_modii
.globl _Z10kernel_modi
.type _Z10kernel_modi, @function
_Z10kernel_modi:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z10kernel_modii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z10kernel_modi, .-_Z10kernel_modi
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "["
.LC2:
.string "%i, "
.LC3:
.string "\n["
.LC4:
.string "%f, "
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $312, %rsp
.cfi_def_cfa_offset 352
movq %fs:40, %rax
movq %rax, 296(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rdi
call cudaEventCreate@PLT
leaq 16(%rsp), %rdi
call cudaEventCreate@PLT
leaq 176(%rsp), %rbp
movq %rbp, %r12
movl $0, %ebx
jmp .L13
.L12:
movl $0, %esi
movq 16(%rsp), %rdi
call cudaEventRecord@PLT
movq 16(%rsp), %rdi
call cudaEventSynchronize@PLT
movq 16(%rsp), %rdx
movq 8(%rsp), %rsi
movq %r12, %rdi
call cudaEventElapsedTime@PLT
addq $1, %rbx
addq $4, %r12
cmpq $30, %rbx
je .L21
.L13:
pxor %xmm2, %xmm2
cvtsi2sdl %ebx, %xmm2
movapd %xmm2, %xmm1
movq %xmm2, %r13
movsd .LC0(%rip), %xmm0
call pow@PLT
cvttsd2sil %xmm0, %eax
movl %eax, 48(%rsp,%rbx,4)
movl $0, %esi
movq 8(%rsp), %rdi
call cudaEventRecord@PLT
movl $32, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 36(%rsp), %rdx
movl $1, %ecx
movq 24(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L12
movq %r13, %xmm1
movsd .LC0(%rip), %xmm0
call pow@PLT
cvttsd2sil %xmm0, %edi
call _Z29__device_stub__Z10kernel_modii
jmp .L12
.L21:
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 48(%rsp), %rbx
leaq 168(%rsp), %r13
leaq .LC2(%rip), %r12
.L14:
movl (%rbx), %edx
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %r13, %rbx
jne .L14
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 120(%rbp), %r12
leaq .LC4(%rip), %rbx
.L15:
pxor %xmm0, %xmm0
cvtss2sd 0(%rbp), %xmm0
movq %rbx, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $4, %rbp
cmpq %r12, %rbp
jne .L15
movq 296(%rsp), %rax
subq %fs:40, %rax
jne .L22
movl $0, %eax
addq $312, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L22:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC5:
.string "_Z10kernel_modi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _Z10kernel_modi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC0:
.long 0
.long 1073741824
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
```
|
```amdasm
.text
.file "lab5.hip"
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI0_0:
.quad 0x3ff0000000000000 # double 1
.text
.globl main
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $264, %rsp # imm = 0x108
.cfi_def_cfa_offset 304
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movabsq $4294967297, %rbx # imm = 0x100000001
leaq 8(%rsp), %rdi
callq hipEventCreate
movq %rsp, %rdi
callq hipEventCreate
leaq 16(%rsp), %r14
xorl %r15d, %r15d
leaq 31(%rbx), %r12
.LBB0_1: # =>This Inner Loop Header: Depth=1
movsd .LCPI0_0(%rip), %xmm0 # xmm0 = mem[0],zero
movl %r15d, %edi
callq ldexp@PLT
cvttsd2si %xmm0, %eax
movl %eax, 144(%rsp,%r15,4)
movq 8(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq %rbx, %rdi
movl $1, %esi
movq %r12, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB0_3
# %bb.2: # in Loop: Header=BB0_1 Depth=1
movsd .LCPI0_0(%rip), %xmm0 # xmm0 = mem[0],zero
movl %r15d, %edi
callq ldexp@PLT
cvttsd2si %xmm0, %edi
callq _Z25__device_stub__kernel_modi
.LBB0_3: # in Loop: Header=BB0_1 Depth=1
movq (%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq (%rsp), %rdi
callq hipEventSynchronize
movq 8(%rsp), %rsi
movq (%rsp), %rdx
movq %r14, %rdi
callq hipEventElapsedTime
incq %r15
addq $4, %r14
cmpq $30, %r15
jne .LBB0_1
# %bb.4:
movl $91, %edi
callq putchar@PLT
xorl %ebx, %ebx
.LBB0_5: # =>This Inner Loop Header: Depth=1
movl 144(%rsp,%rbx,4), %esi
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
incq %rbx
cmpq $30, %rbx
jne .LBB0_5
# %bb.6:
xorl %ebx, %ebx
movl $.L.str.2, %edi
xorl %eax, %eax
callq printf
.LBB0_7: # =>This Inner Loop Header: Depth=1
xorps %xmm0, %xmm0
cvtss2sd 16(%rsp,%rbx,4), %xmm0
movl $.L.str.3, %edi
movb $1, %al
callq printf
incq %rbx
cmpq $30, %rbx
jne .LBB0_7
# %bb.8:
xorl %eax, %eax
addq $264, %rsp # imm = 0x108
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.globl _Z25__device_stub__kernel_modi # -- Begin function _Z25__device_stub__kernel_modi
.type _Z25__device_stub__kernel_modi,@function
_Z25__device_stub__kernel_modi: # @_Z25__device_stub__kernel_modi
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $80, %rsp
.cfi_def_cfa_offset 128
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 12(%rsp), %rax
movl %edi, (%rax)
leaq 16(%rsp), %rbx
movq %rax, (%rbx)
leaq 64(%rsp), %r14
leaq 48(%rsp), %r15
leaq 40(%rsp), %r12
leaq 32(%rsp), %r13
movq %r14, %rdi
movq %r15, %rsi
movq %r12, %rdx
movq %r13, %rcx
callq __hipPopCallConfiguration
movq (%r14), %rsi
movl 8(%r14), %edx
movq (%r15), %rcx
movl 8(%r15), %r8d
movl $_Z10kernel_modi, %edi
movq %rbx, %r9
pushq (%r13)
.cfi_adjust_cfa_offset 8
pushq (%r12)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $96, %rsp
.cfi_adjust_cfa_offset -96
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z25__device_stub__kernel_modi, .Lfunc_end1-_Z25__device_stub__kernel_modi
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, %rdi
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10kernel_modi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10kernel_modi,@object # @_Z10kernel_modi
.section .rodata,"a",@progbits
.globl _Z10kernel_modi
.p2align 3, 0x0
_Z10kernel_modi:
.quad _Z25__device_stub__kernel_modi
.size _Z10kernel_modi, 8
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "%i, "
.size .L.str.1, 5
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "\n["
.size .L.str.2, 3
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "%f, "
.size .L.str.3, 5
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z10kernel_modi"
.size .L__unnamed_1, 16
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__kernel_modi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10kernel_modi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
```
| 3,129 | 3,292 |
256 |
Convert the following CUDA device assembly code to AMD device assembly:
```cudaasm
code for sm_80
```
|
```amdasm
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object ; @__hip_cuid_
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0 ; 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
```
| 24 | 306 |
257 |
Convert the following CUDA host assembly code to AMD host assembly:
```cudaasm
.file "tmpxft_000dcb8b_00000000-6_cuda_c_interface.cudafe1.cpp"
.text
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2065:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2065:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "\n Error in cudaSetDevice: %s \n"
.text
.globl cuda_set_device
.type cuda_set_device, @function
cuda_set_device:
.LFB2057:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call cudaSetDevice@PLT
testl %eax, %eax
jne .L6
movl $0, %eax
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L6:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.cfi_endproc
.LFE2057:
.size cuda_set_device, .-cuda_set_device
.section .rodata.str1.8
.align 8
.LC1:
.string "\n Error in cudaGetDeviceCount: %s \n"
.text
.globl cuda_get_device_count
.type cuda_get_device_count, @function
cuda_get_device_count:
.LFB2058:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call cudaGetDeviceCount@PLT
testl %eax, %eax
jne .L10
movl $0, %eax
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L10:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.cfi_endproc
.LFE2058:
.size cuda_get_device_count, .-cuda_get_device_count
.section .rodata.str1.8
.align 8
.LC2:
.string "\n Error in cudaDeviceSynchronize: %s \n"
.text
.globl cuda_device_synchronize
.type cuda_device_synchronize, @function
cuda_device_synchronize:
.LFB2059:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call cudaDeviceSynchronize@PLT
testl %eax, %eax
jne .L14
.L12:
movl $0, %eax
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L12
.cfi_endproc
.LFE2059:
.size cuda_device_synchronize, .-cuda_device_synchronize
.section .rodata.str1.1,"aMS",@progbits,1
.LC3:
.string "\n Error in cudaMalloc: %s \n"
.text
.globl cuda_malloc
.type cuda_malloc, @function
cuda_malloc:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call cudaMalloc@PLT
testl %eax, %eax
jne .L18
movl $0, %eax
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L18:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.cfi_endproc
.LFE2060:
.size cuda_malloc, .-cuda_malloc
.section .rodata.str1.1
.LC4:
.string "\n Error in cudaFree: %s \n"
.text
.globl cuda_free
.type cuda_free, @function
cuda_free:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call cudaFree@PLT
testl %eax, %eax
jne .L22
movl $0, %eax
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L22:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.cfi_endproc
.LFE2061:
.size cuda_free, .-cuda_free
.section .rodata.str1.1
.LC5:
.string "\n Error in cudaMemcpy: %s \n"
.text
.globl cuda_memcpy
.type cuda_memcpy, @function
cuda_memcpy:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl $2, %eax
cmpl $1, %ecx
je .L24
cmpl $2, %ecx
je .L27
testl %ecx, %ecx
movl $1, %ecx
cmove %ecx, %eax
.L24:
movl %eax, %ecx
call cudaMemcpy@PLT
testl %eax, %eax
jne .L30
movl $0, %eax
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L27:
.cfi_restore_state
movl $3, %eax
jmp .L24
.L30:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.cfi_endproc
.LFE2062:
.size cuda_memcpy, .-cuda_memcpy
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2088:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2088:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
```
|
```amdasm
.text
.file "cuda_c_interface.hip"
.globl cuda_set_device # -- Begin function cuda_set_device
.type cuda_set_device,@function
cuda_set_device: # @cuda_set_device
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
callq hipSetDevice
testl %eax, %eax
jne .LBB0_2
# %bb.1:
xorl %eax, %eax
popq %rcx
.cfi_def_cfa_offset 8
retq
.LBB0_2:
.cfi_def_cfa_offset 16
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
movl $1, %edi
callq exit
.Lfunc_end0:
.size cuda_set_device, .Lfunc_end0-cuda_set_device
.cfi_endproc
# -- End function
.globl cuda_get_device_count # -- Begin function cuda_get_device_count
.type cuda_get_device_count,@function
cuda_get_device_count: # @cuda_get_device_count
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
callq hipGetDeviceCount
testl %eax, %eax
jne .LBB1_2
# %bb.1:
xorl %eax, %eax
popq %rcx
.cfi_def_cfa_offset 8
retq
.LBB1_2:
.cfi_def_cfa_offset 16
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.1, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
movl $1, %edi
callq exit
.Lfunc_end1:
.size cuda_get_device_count, .Lfunc_end1-cuda_get_device_count
.cfi_endproc
# -- End function
.globl cuda_device_synchronize # -- Begin function cuda_device_synchronize
.type cuda_device_synchronize,@function
cuda_device_synchronize: # @cuda_device_synchronize
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
callq hipDeviceSynchronize
testl %eax, %eax
je .LBB2_2
# %bb.1:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.2, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
.LBB2_2:
xorl %eax, %eax
popq %rcx
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size cuda_device_synchronize, .Lfunc_end2-cuda_device_synchronize
.cfi_endproc
# -- End function
.globl cuda_malloc # -- Begin function cuda_malloc
.type cuda_malloc,@function
cuda_malloc: # @cuda_malloc
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
callq hipMalloc
testl %eax, %eax
jne .LBB3_2
# %bb.1:
xorl %eax, %eax
popq %rcx
.cfi_def_cfa_offset 8
retq
.LBB3_2:
.cfi_def_cfa_offset 16
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.3, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
movl $1, %edi
callq exit
.Lfunc_end3:
.size cuda_malloc, .Lfunc_end3-cuda_malloc
.cfi_endproc
# -- End function
.globl cuda_free # -- Begin function cuda_free
.type cuda_free,@function
cuda_free: # @cuda_free
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
callq hipFree
testl %eax, %eax
jne .LBB4_2
# %bb.1:
xorl %eax, %eax
popq %rcx
.cfi_def_cfa_offset 8
retq
.LBB4_2:
.cfi_def_cfa_offset 16
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.4, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
movl $1, %edi
callq exit
.Lfunc_end4:
.size cuda_free, .Lfunc_end4-cuda_free
.cfi_endproc
# -- End function
.globl cuda_memcpy # -- Begin function cuda_memcpy
.type cuda_memcpy,@function
cuda_memcpy: # @cuda_memcpy
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
xorl %eax, %eax
cmpl $1, %ecx
sete %al
incl %eax
cmpl $2, %ecx
movl $3, %ecx
cmovnel %eax, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB5_2
# %bb.1:
xorl %eax, %eax
popq %rcx
.cfi_def_cfa_offset 8
retq
.LBB5_2:
.cfi_def_cfa_offset 16
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.5, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
movl $1, %edi
callq exit
.Lfunc_end5:
.size cuda_memcpy, .Lfunc_end5-cuda_memcpy
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "\n Error in cudaSetDevice: %s \n"
.size .L.str, 31
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "\n Error in cudaGetDeviceCount: %s \n"
.size .L.str.1, 36
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "\n Error in cudaDeviceSynchronize: %s \n"
.size .L.str.2, 39
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "\n Error in cudaMalloc: %s \n"
.size .L.str.3, 28
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "\n Error in cudaFree: %s \n"
.size .L.str.4, 26
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "\n Error in cudaMemcpy: %s \n"
.size .L.str.5, 28
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
```
| 2,495 | 1,966 |
258 |
Convert the following CUDA device assembly code to AMD device assembly:
```cudaasm
code for sm_80
Function : _Z8PDH_CudaP8atomdescP10hist_entryxd
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ;
S2R R8, SR_CTAID.X ;
S2R R3, SR_TID.X ;
IMAD R8, R8, c[0x0][0x0], R3 ;
IADD3 R0, R8, 0x1, RZ ;
ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x170], PT ;
SHF.R.S32.HI R2, RZ, 0x1f, R0 ;
ISETP.GE.AND.EX P0, PT, R2, c[0x0][0x174], PT, P0 ;
@P0 EXIT ;
IMAD.MOV.U32 R9, RZ, RZ, 0x18 ;
ULDC.64 UR4, c[0x0][0x118] ;
IMAD.MOV.U32 R11, RZ, RZ, R2 ;
IMAD.MOV.U32 R10, RZ, RZ, R0 ;
IMAD.WIDE R8, R8, R9, c[0x0][0x160] ;
IMAD.MOV.U32 R3, RZ, RZ, 0x18 ;
LDG.E.64 R12, [R8.64+0x8] ;
IMAD R11, R11, 0x18, RZ ;
IMAD.WIDE.U32 R2, R10, R3, c[0x0][0x160] ;
LDG.E.64 R6, [R8.64] ;
IMAD.IADD R3, R3, 0x1, R11 ;
LDG.E.64 R16, [R8.64+0x10] ;
LDG.E.64 R10, [R2.64+0x8] ;
LDG.E.64 R4, [R2.64] ;
LDG.E.64 R14, [R2.64+0x10] ;
YIELD ;
BSSY B0, 0x350 ;
DADD R10, -R10, R12 ;
DADD R4, -R4, R6 ;
DMUL R10, R10, R10 ;
DADD R14, -R14, R16 ;
DFMA R6, R4, R4, R10 ;
DFMA R6, R14, R14, R6 ;
MUFU.RSQ64H R5, R7 ;
IADD3 R4, R7, -0x3500000, RZ ;
IMAD.MOV.U32 R12, RZ, RZ, 0x0 ;
IMAD.MOV.U32 R13, RZ, RZ, 0x3fd80000 ;
DMUL R10, R4, R4 ;
DFMA R10, R6, -R10, 1 ;
DFMA R2, R10, R12, 0.5 ;
DMUL R10, R4, R10 ;
ISETP.GE.U32.AND P0, PT, R4, 0x7ca00000, PT ;
DFMA R12, R2, R10, R4 ;
DMUL R14, R6, R12 ;
IADD3 R11, R13, -0x100000, RZ ;
IMAD.MOV.U32 R10, RZ, RZ, R12 ;
DFMA R16, R14, -R14, R6 ;
DFMA R2, R16, R10, R14 ;
@!P0 BRA 0x340 ;
MOV R2, 0x320 ;
CALL.REL.NOINC 0xb70 ;
IMAD.MOV.U32 R2, RZ, RZ, R4 ;
IMAD.MOV.U32 R3, RZ, RZ, R5 ;
BSYNC B0 ;
MUFU.RCP64H R5, c[0x0][0x17c] ;
IMAD.MOV.U32 R10, RZ, RZ, c[0x0][0x178] ;
FSETP.GEU.AND P1, PT, |R3|, 6.5827683646048100446e-37, PT ;
IMAD.MOV.U32 R11, RZ, RZ, c[0x0][0x17c] ;
BSSY B0, 0x4b0 ;
IMAD.MOV.U32 R4, RZ, RZ, 0x1 ;
DFMA R6, R4, -R10, 1 ;
DFMA R6, R6, R6, R6 ;
DFMA R6, R4, R6, R4 ;
DFMA R4, R6, -R10, 1 ;
DFMA R4, R6, R4, R6 ;
DMUL R6, R4, R2 ;
DFMA R10, R6, -c[0x0][0x178], R2 ;
DFMA R4, R4, R10, R6 ;
FFMA R6, RZ, c[0x0][0x17c], R5 ;
FSETP.GT.AND P0, PT, |R6|, 1.469367938527859385e-39, PT ;
@P0 BRA P1, 0x4a0 ;
IMAD.MOV.U32 R4, RZ, RZ, R2 ;
MOV R16, 0x4a0 ;
IMAD.MOV.U32 R5, RZ, RZ, R3 ;
CALL.REL.NOINC 0x580 ;
BSYNC B0 ;
F2I.F64.TRUNC R2, R4 ;
IADD3 R10, R0, 0x1, RZ ;
IMAD.MOV.U32 R3, RZ, RZ, 0x8 ;
IMAD.MOV.U32 R6, RZ, RZ, 0x1 ;
ISETP.GE.U32.AND P0, PT, R10, c[0x0][0x170], PT ;
IMAD.MOV.U32 R7, RZ, RZ, 0x0 ;
SHF.R.S32.HI R11, RZ, 0x1f, R10 ;
ISETP.GE.AND.EX P0, PT, R11, c[0x0][0x174], PT, P0 ;
IMAD.WIDE R2, R2, R3, c[0x0][0x168] ;
MOV R0, R10 ;
RED.E.ADD.64.STRONG.GPU [R2.64], R6 ;
@!P0 BRA 0xe0 ;
EXIT ;
IMAD.MOV.U32 R18, RZ, RZ, c[0x0][0x17c] ;
FSETP.GEU.AND P2, PT, |R5|.reuse, 1.469367938527859385e-39, PT ;
IMAD.MOV.U32 R17, RZ, RZ, 0x1ca00000 ;
LOP3.LUT R20, R5, 0x7ff00000, RZ, 0xc0, !PT ;
IMAD.MOV.U32 R10, RZ, RZ, 0x1 ;
FSETP.GEU.AND P0, PT, |R18|.reuse, 1.469367938527859385e-39, PT ;
BSSY B1, 0xb30 ;
LOP3.LUT R6, R18.reuse, 0x800fffff, RZ, 0xc0, !PT ;
IMAD.MOV.U32 R21, RZ, RZ, R20 ;
LOP3.LUT R19, R18, 0x7ff00000, RZ, 0xc0, !PT ;
LOP3.LUT R7, R6, 0x3ff00000, RZ, 0xfc, !PT ;
IMAD.MOV.U32 R6, RZ, RZ, c[0x0][0x178] ;
ISETP.GE.U32.AND P1, PT, R20, R19, PT ;
IMAD.MOV.U32 R22, RZ, RZ, R19 ;
SEL R17, R17, 0x63400000, !P1 ;
@!P0 IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x178] ;
@!P0 IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x17c] ;
@!P2 LOP3.LUT R12, R17, 0x80000000, R5, 0xf8, !PT ;
@!P2 LOP3.LUT R13, R12, 0x100000, RZ, 0xfc, !PT ;
@!P0 DMUL R6, R2, 8.98846567431157953865e+307 ;
@!P2 IMAD.MOV.U32 R12, RZ, RZ, RZ ;
MUFU.RCP64H R11, R7 ;
@!P0 LOP3.LUT R22, R7, 0x7ff00000, RZ, 0xc0, !PT ;
IADD3 R23, R22, -0x1, RZ ;
DFMA R2, R10, -R6, 1 ;
DFMA R14, R2, R2, R2 ;
LOP3.LUT R3, R17, 0x800fffff, R5, 0xf8, !PT ;
IMAD.MOV.U32 R2, RZ, RZ, R4 ;
DFMA R10, R10, R14, R10 ;
@!P2 DFMA R2, R2, 2, -R12 ;
DFMA R12, R10, -R6, 1 ;
@!P2 LOP3.LUT R21, R3, 0x7ff00000, RZ, 0xc0, !PT ;
DFMA R10, R10, R12, R10 ;
IADD3 R14, R21, -0x1, RZ ;
DMUL R12, R10, R2 ;
ISETP.GT.U32.AND P0, PT, R14, 0x7feffffe, PT ;
ISETP.GT.U32.OR P0, PT, R23, 0x7feffffe, P0 ;
DFMA R14, R12, -R6, R2 ;
DFMA R14, R10, R14, R12 ;
@P0 BRA 0x9a0 ;
IMAD.IADD R19, R20, 0x1, -R19 ;
IMNMX R19, R19, -0x46a00000, !PT ;
IMNMX R4, R19, 0x46a00000, PT ;
IMAD.IADD R17, R4, 0x1, -R17 ;
IMAD.MOV.U32 R4, RZ, RZ, RZ ;
IADD3 R5, R17, 0x7fe00000, RZ ;
DMUL R10, R14, R4 ;
FSETP.GTU.AND P0, PT, |R11|, 1.469367938527859385e-39, PT ;
@P0 BRA 0xb20 ;
DFMA R2, R14, -R6, R2 ;
MOV R4, RZ ;
FSETP.NEU.AND P0, PT, R3.reuse, RZ, PT ;
LOP3.LUT R2, R3, c[0x0][0x17c], RZ, 0x3c, !PT ;
LOP3.LUT R7, R2, 0x80000000, RZ, 0xc0, !PT ;
LOP3.LUT R5, R7, R5, RZ, 0xfc, !PT ;
@!P0 BRA 0xb20 ;
IMAD.MOV R3, RZ, RZ, -R17 ;
DMUL.RP R4, R14, R4 ;
IMAD.MOV.U32 R2, RZ, RZ, RZ ;
DFMA R2, R10, -R2, R14 ;
LOP3.LUT R7, R5, R7, RZ, 0x3c, !PT ;
IADD3 R2, -R17, -0x43300000, RZ ;
FSETP.NEU.AND P0, PT, |R3|, R2, PT ;
FSEL R10, R4, R10, !P0 ;
FSEL R11, R7, R11, !P0 ;
BRA 0xb20 ;
DSETP.NAN.AND P0, PT, R4, R4, PT ;
@P0 BRA 0xb00 ;
IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x178] ;
IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x17c] ;
DSETP.NAN.AND P0, PT, R2, c[0x0][0x178], PT ;
@P0 BRA 0xad0 ;
ISETP.NE.AND P0, PT, R21, R22, PT ;
IMAD.MOV.U32 R10, RZ, RZ, 0x0 ;
IMAD.MOV.U32 R11, RZ, RZ, -0x80000 ;
@!P0 BRA 0xb20 ;
ISETP.NE.AND P0, PT, R21, 0x7ff00000, PT ;
LOP3.LUT R4, R5, c[0x0][0x17c], RZ, 0x3c, !PT ;
ISETP.EQ.OR P0, PT, R22, RZ, !P0 ;
LOP3.LUT R11, R4, 0x80000000, RZ, 0xc0, !PT ;
@P0 LOP3.LUT R2, R11, 0x7ff00000, RZ, 0xfc, !PT ;
@!P0 IMAD.MOV.U32 R10, RZ, RZ, RZ ;
@P0 IMAD.MOV.U32 R10, RZ, RZ, RZ ;
@P0 IMAD.MOV.U32 R11, RZ, RZ, R2 ;
BRA 0xb20 ;
LOP3.LUT R11, R18, 0x80000, RZ, 0xfc, !PT ;
IMAD.MOV.U32 R10, RZ, RZ, c[0x0][0x178] ;
BRA 0xb20 ;
LOP3.LUT R11, R5, 0x80000, RZ, 0xfc, !PT ;
IMAD.MOV.U32 R10, RZ, RZ, R4 ;
BSYNC B1 ;
IMAD.MOV.U32 R17, RZ, RZ, 0x0 ;
MOV R5, R11 ;
IMAD.MOV.U32 R4, RZ, RZ, R10 ;
RET.REL.NODEC R16 0x0 ;
ISETP.GE.U32.AND P0, PT, R4, -0x3400000, PT ;
BSSY B1, 0xdf0 ;
IMAD.MOV.U32 R10, RZ, RZ, R12 ;
IMAD.MOV.U32 R4, RZ, RZ, R16 ;
IMAD.MOV.U32 R5, RZ, RZ, R17 ;
@!P0 BRA 0xc50 ;
DFMA.RM R4, R4, R10, R14 ;
IADD3 R10, P0, R4, 0x1, RZ ;
IMAD.X R11, RZ, RZ, R5, P0 ;
DFMA.RP R6, -R4, R10, R6 ;
DSETP.GT.AND P0, PT, R6, RZ, PT ;
FSEL R4, R10, R4, P0 ;
FSEL R5, R11, R5, P0 ;
BRA 0xde0 ;
DSETP.NE.AND P0, PT, R6, RZ, PT ;
@!P0 BRA 0xdd0 ;
ISETP.GE.AND P0, PT, R7, RZ, PT ;
@!P0 IMAD.MOV.U32 R4, RZ, RZ, 0x0 ;
@!P0 IMAD.MOV.U32 R5, RZ, RZ, -0x80000 ;
@!P0 BRA 0xde0 ;
ISETP.GT.AND P0, PT, R7, 0x7fefffff, PT ;
@P0 BRA 0xdd0 ;
DMUL R4, R6, 8.11296384146066816958e+31 ;
IMAD.MOV.U32 R12, RZ, RZ, 0x0 ;
IMAD.MOV.U32 R6, RZ, RZ, RZ ;
IMAD.MOV.U32 R13, RZ, RZ, 0x3fd80000 ;
MUFU.RSQ64H R7, R5 ;
DMUL R10, R6, R6 ;
DFMA R10, R4, -R10, 1 ;
DFMA R12, R10, R12, 0.5 ;
DMUL R10, R6, R10 ;
DFMA R10, R12, R10, R6 ;
DMUL R6, R4, R10 ;
IADD3 R11, R11, -0x100000, RZ ;
DFMA R12, R6, -R6, R4 ;
DFMA R4, R10, R12, R6 ;
IADD3 R5, R5, -0x3500000, RZ ;
BRA 0xde0 ;
DADD R4, R6, R6 ;
BSYNC B1 ;
IMAD.MOV.U32 R3, RZ, RZ, 0x0 ;
RET.REL.NODEC R2 0x0 ;
BRA 0xe10;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
```
|
```amdasm
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z8PDH_CudaP8atomdescP10hist_entryxd ; -- Begin function _Z8PDH_CudaP8atomdescP10hist_entryxd
.globl _Z8PDH_CudaP8atomdescP10hist_entryxd
.p2align 8
.type _Z8PDH_CudaP8atomdescP10hist_entryxd,@function
_Z8PDH_CudaP8atomdescP10hist_entryxd: ; @_Z8PDH_CudaP8atomdescP10hist_entryxd
; %bb.0:
s_clause 0x1
s_load_b32 s8, s[0:1], 0x2c
s_load_b256 s[0:7], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s8, s8, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, s15, s8, v[0:1]
s_mov_b32 s8, exec_lo
v_add_nc_u32_e32 v4, 1, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v5, 31, v4
v_cmpx_gt_i64_e64 s[4:5], v[4:5]
s_cbranch_execz .LBB0_3
; %bb.1: ; %.lr.ph
v_add_nc_u32_e32 v3, 2, v2
v_mad_i64_i32 v[0:1], null, v2, 24, s[0:1]
s_mov_b32 s8, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v6, 31, v3
v_add_co_u32 v2, vcc_lo, v3, -1
v_add_co_ci_u32_e32 v3, vcc_lo, -1, v6, vcc_lo
.LBB0_2: ; =>This Inner Loop Header: Depth=1
v_mad_u64_u32 v[12:13], null, v4, 24, s[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mov_b32_e32 v4, v13
v_mad_u64_u32 v[8:9], null, v5, 24, v[4:5]
s_clause 0x1
global_load_b64 v[14:15], v[0:1], off offset:16
global_load_b128 v[4:7], v[0:1], off
v_mov_b32_e32 v13, v8
s_clause 0x1
global_load_b128 v[8:11], v[12:13], off
global_load_b64 v[12:13], v[12:13], off offset:16
s_waitcnt vmcnt(1)
v_add_f64 v[6:7], v[6:7], -v[10:11]
v_add_f64 v[4:5], v[4:5], -v[8:9]
s_waitcnt vmcnt(0)
v_add_f64 v[8:9], v[14:15], -v[12:13]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f64 v[6:7], v[6:7], v[6:7]
v_fma_f64 v[4:5], v[4:5], v[4:5], v[6:7]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[4:5], v[8:9], v[8:9], v[4:5]
v_cmp_gt_f64_e32 vcc_lo, 0x10000000, v[4:5]
v_cndmask_b32_e64 v6, 0, 1, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b32_e32 v6, 8, v6
v_ldexp_f64 v[4:5], v[4:5], v6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_rsq_f64_e32 v[6:7], v[4:5]
s_waitcnt_depctr 0xfff
v_mul_f64 v[8:9], v[4:5], v[6:7]
v_mul_f64 v[6:7], v[6:7], 0.5
v_fma_f64 v[10:11], -v[6:7], v[8:9], 0.5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_fma_f64 v[8:9], v[8:9], v[10:11], v[8:9]
v_fma_f64 v[6:7], v[6:7], v[10:11], v[6:7]
v_fma_f64 v[10:11], -v[8:9], v[8:9], v[4:5]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[8:9], v[10:11], v[6:7], v[8:9]
v_fma_f64 v[10:11], -v[8:9], v[8:9], v[4:5]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_fma_f64 v[6:7], v[10:11], v[6:7], v[8:9]
v_cndmask_b32_e64 v8, 0, 0xffffff80, vcc_lo
v_cmp_class_f64_e64 vcc_lo, v[4:5], 0x260
v_ldexp_f64 v[6:7], v[6:7], v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_cndmask_b32 v5, v7, v5 :: v_dual_cndmask_b32 v4, v6, v4
v_div_scale_f64 v[6:7], null, s[6:7], s[6:7], v[4:5]
v_div_scale_f64 v[12:13], vcc_lo, v[4:5], s[6:7], v[4:5]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f64_e32 v[8:9], v[6:7]
s_waitcnt_depctr 0xfff
v_fma_f64 v[10:11], -v[6:7], v[8:9], 1.0
v_fma_f64 v[8:9], v[8:9], v[10:11], v[8:9]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[10:11], -v[6:7], v[8:9], 1.0
v_fma_f64 v[8:9], v[8:9], v[10:11], v[8:9]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f64 v[10:11], v[12:13], v[8:9]
v_fma_f64 v[6:7], -v[6:7], v[10:11], v[12:13]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fmas_f64 v[6:7], v[6:7], v[8:9], v[10:11]
v_div_fixup_f64 v[4:5], v[6:7], s[6:7], v[4:5]
v_mov_b32_e32 v6, 1
v_mov_b32_e32 v7, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_i32_f64_e32 v4, v[4:5]
v_ashrrev_i32_e32 v5, 31, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[4:5], 3, v[4:5]
v_add_co_u32 v4, vcc_lo, s2, v4
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v5, vcc_lo, s3, v5, vcc_lo
v_add_co_u32 v2, vcc_lo, v2, 1
v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
global_atomic_add_u64 v[4:5], v[6:7], off
v_mov_b32_e32 v4, v2
v_ashrrev_i32_e32 v5, 31, v2
v_cmp_le_i64_e32 vcc_lo, s[4:5], v[2:3]
s_or_b32 s8, vcc_lo, s8
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s8
s_cbranch_execnz .LBB0_2
.LBB0_3: ; %._crit_edge
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z8PDH_CudaP8atomdescP10hist_entryxd
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 16
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z8PDH_CudaP8atomdescP10hist_entryxd, .Lfunc_end0-_Z8PDH_CudaP8atomdescP10hist_entryxd
; -- End function
.section .AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 624
; NumSgprs: 18
; NumVgprs: 16
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 16
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object ; @__hip_cuid_
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0 ; 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 8
.value_kind: by_value
- .offset: 24
.size: 8
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z8PDH_CudaP8atomdescP10hist_entryxd
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z8PDH_CudaP8atomdescP10hist_entryxd.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 16
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
```
| 4,722 | 4,637 |
259 |
Convert the following CUDA host assembly code to AMD host assembly:
```cudaasm
.file "tmpxft_000d9c9b_00000000-6_proj1-danielsawyer.cudafe1.cpp"
.text
.globl _ZSt21ios_base_library_initv
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3680:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3680:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z12p2p_distanceii
.type _Z12p2p_distanceii, @function
_Z12p2p_distanceii:
.LFB3669:
.cfi_startproc
endbr64
movq atom_list(%rip), %rax
movslq %edi, %rdi
leaq (%rdi,%rdi,2), %rdx
leaq (%rax,%rdx,8), %rdx
movslq %esi, %rsi
leaq (%rsi,%rsi,2), %rcx
leaq (%rax,%rcx,8), %rax
movsd (%rdx), %xmm1
subsd (%rax), %xmm1
movsd 8(%rdx), %xmm2
subsd 8(%rax), %xmm2
movsd 16(%rdx), %xmm0
subsd 16(%rax), %xmm0
mulsd %xmm1, %xmm1
mulsd %xmm2, %xmm2
addsd %xmm2, %xmm1
mulsd %xmm0, %xmm0
addsd %xmm1, %xmm0
sqrtsd %xmm0, %xmm0
ret
.cfi_endproc
.LFE3669:
.size _Z12p2p_distanceii, .-_Z12p2p_distanceii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "Running time for CPU version: %ld.%06ld\n"
.text
.globl _Z19report_running_timev
.type _Z19report_running_timev, @function
_Z19report_running_timev:
.LFB3670:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
leaq Idunno(%rip), %rsi
leaq endTime(%rip), %rdi
call gettimeofday@PLT
movq endTime(%rip), %rbp
subq startTime(%rip), %rbp
movq 8+endTime(%rip), %rbx
subq 8+startTime(%rip), %rbx
js .L7
.L5:
movq %rbx, %rcx
movq %rbp, %rdx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
pxor %xmm0, %xmm0
cvtsi2sdq %rbx, %xmm0
divsd .LC1(%rip), %xmm0
pxor %xmm1, %xmm1
cvtsi2sdq %rbp, %xmm1
addsd %xmm1, %xmm0
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
subq $1, %rbp
addq $1000000, %rbx
jmp .L5
.cfi_endproc
.LFE3670:
.size _Z19report_running_timev, .-_Z19report_running_timev
.section .rodata.str1.8
.align 8
.LC2:
.string "\nRunning time for GPU version: %ld.%06ld\n"
.text
.globl _Z19report_running_timei
.type _Z19report_running_timei, @function
_Z19report_running_timei:
.LFB3671:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
leaq Idunno(%rip), %rsi
leaq endTime(%rip), %rdi
call gettimeofday@PLT
movq endTime(%rip), %rbp
subq startTime(%rip), %rbp
movq 8+endTime(%rip), %rbx
subq 8+startTime(%rip), %rbx
js .L11
.L9:
movq %rbx, %rcx
movq %rbp, %rdx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
pxor %xmm0, %xmm0
cvtsi2sdq %rbx, %xmm0
divsd .LC1(%rip), %xmm0
pxor %xmm1, %xmm1
cvtsi2sdq %rbp, %xmm1
addsd %xmm1, %xmm0
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore_state
subq $1, %rbp
addq $1000000, %rbx
jmp .L9
.cfi_endproc
.LFE3671:
.size _Z19report_running_timei, .-_Z19report_running_timei
.section .rodata.str1.1,"aMS",@progbits,1
.LC3:
.string "\n%02d: "
.LC4:
.string "%15lld "
.LC5:
.string "\n T:%lld \n"
.LC6:
.string "| "
.text
.globl _Z16output_histogramv
.type _Z16output_histogramv, @function
_Z16output_histogramv:
.LFB3672:
.cfi_startproc
endbr64
cmpl $0, num_buckets(%rip)
jle .L20
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $8, %rsp
.cfi_def_cfa_offset 64
movl $0, %ebx
movl $0, %ebp
leaq .LC3(%rip), %r15
leaq .LC4(%rip), %r12
leaq .LC6(%rip), %r13
leaq .LC5(%rip), %r14
jmp .L17
.L24:
movl %ebx, %edx
movq %r15, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L14
.L25:
movq %r14, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
.L16:
addq $1, %rbx
cmpl %ebx, num_buckets(%rip)
jle .L23
.L17:
movslq %ebx, %rax
imulq $1717986919, %rax, %rax
sarq $33, %rax
movl %ebx, %edx
sarl $31, %edx
subl %edx, %eax
leal (%rax,%rax,4), %eax
cmpl %ebx, %eax
je .L24
.L14:
movq histogram(%rip), %rax
movq (%rax,%rbx,8), %rdx
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq histogram(%rip), %rax
movq %rbp, %rdx
addq (%rax,%rbx,8), %rdx
movq %rdx, %rbp
movl num_buckets(%rip), %eax
subl $1, %eax
cmpl %ebx, %eax
je .L25
movq %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L16
.L23:
addq $8, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L20:
.cfi_restore 3
.cfi_restore 6
.cfi_restore 12
.cfi_restore 13
.cfi_restore 14
.cfi_restore 15
ret
.cfi_endproc
.LFE3672:
.size _Z16output_histogramv, .-_Z16output_histogramv
.globl _Z16output_histogramP10hist_entry
.type _Z16output_histogramP10hist_entry, @function
_Z16output_histogramP10hist_entry:
.LFB3673:
.cfi_startproc
endbr64
cmpl $0, num_buckets(%rip)
jle .L34
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $8, %rsp
.cfi_def_cfa_offset 64
movq %rdi, %rbp
movl $0, %ebx
movl $0, %r12d
leaq .LC4(%rip), %r13
leaq .LC6(%rip), %r14
leaq .LC5(%rip), %r15
jmp .L31
.L38:
movl %ebx, %edx
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L28
.L39:
movq %r15, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
.L30:
addq $1, %rbx
cmpl %ebx, num_buckets(%rip)
jle .L37
.L31:
movslq %ebx, %rax
imulq $1717986919, %rax, %rax
sarq $33, %rax
movl %ebx, %edx
sarl $31, %edx
subl %edx, %eax
leal (%rax,%rax,4), %eax
cmpl %ebx, %eax
je .L38
.L28:
movq 0(%rbp,%rbx,8), %rdx
movq %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %r12, %rdx
addq 0(%rbp,%rbx,8), %rdx
movq %rdx, %r12
movl num_buckets(%rip), %eax
subl $1, %eax
cmpl %ebx, %eax
je .L39
movq %r14, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L30
.L37:
addq $8, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L34:
.cfi_restore 3
.cfi_restore 6
.cfi_restore 12
.cfi_restore 13
.cfi_restore 14
.cfi_restore 15
ret
.cfi_endproc
.LFE3673:
.size _Z16output_histogramP10hist_entry, .-_Z16output_histogramP10hist_entry
.globl _Z16output_histogramP10hist_entryS0_
.type _Z16output_histogramP10hist_entryS0_, @function
_Z16output_histogramP10hist_entryS0_:
.LFB3674:
.cfi_startproc
endbr64
cmpl $0, num_buckets(%rip)
jle .L48
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $8, %rsp
.cfi_def_cfa_offset 64
movq %rdi, %rbp
movq %rsi, %r12
movl $0, %ebx
movl $0, %r14d
movl $0, %r13d
leaq .LC4(%rip), %r15
jmp .L45
.L52:
movl %ebx, %edx
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L42
.L53:
subq %rcx, %rdx
movq %rdx, %rax
negq %rax
cmovns %rax, %rdx
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
.L44:
addq $1, %rbx
cmpl %ebx, num_buckets(%rip)
jle .L51
.L45:
movslq %ebx, %rax
imulq $1717986919, %rax, %rax
sarq $33, %rax
movl %ebx, %edx
sarl $31, %edx
subl %edx, %eax
leal (%rax,%rax,4), %eax
cmpl %ebx, %eax
je .L52
.L42:
movq 0(%rbp,%rbx,8), %rax
subq (%r12,%rbx,8), %rax
movq %rax, %rdx
negq %rdx
cmovs %rax, %rdx
movq %r15, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %r13, %rdx
addq 0(%rbp,%rbx,8), %rdx
movq %rdx, %r13
movq %r14, %rcx
addq (%r12,%rbx,8), %rcx
movq %rcx, %r14
movl num_buckets(%rip), %eax
subl $1, %eax
cmpl %ebx, %eax
je .L53
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L44
.L51:
addq $8, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L48:
.cfi_restore 3
.cfi_restore 6
.cfi_restore 12
.cfi_restore 13
.cfi_restore 14
.cfi_restore 15
ret
.cfi_endproc
.LFE3674:
.size _Z16output_histogramP10hist_entryS0_, .-_Z16output_histogramP10hist_entryS0_
.globl _Z12PDH_baselinev
.type _Z12PDH_baselinev, @function
_Z12PDH_baselinev:
.LFB3675:
.cfi_startproc
endbr64
cmpq $0, PDH_acnt(%rip)
jle .L61
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
movl $1, %r13d
movl $0, %r14d
.L57:
movl %r14d, %r12d
movl %r13d, %ebx
cmpq %r13, PDH_acnt(%rip)
jle .L55
movq %r13, %rbp
.L56:
movl %ebx, %esi
movl %r12d, %edi
call _Z12p2p_distanceii
divsd PDH_res(%rip), %xmm0
cvttsd2sil %xmm0, %eax
cltq
movq histogram(%rip), %rdx
addq $1, (%rdx,%rax,8)
addl $1, %ebx
movq PDH_acnt(%rip), %rax
addq $1, %rbp
cmpq %rbp, %rax
jg .L56
addq $1, %r14
addq $1, %r13
cmpq %r14, %rax
jg .L57
.L55:
movl $0, %eax
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L61:
.cfi_restore 3
.cfi_restore 6
.cfi_restore 12
.cfi_restore 13
.cfi_restore 14
movl $0, %eax
ret
.cfi_endproc
.LFE3675:
.size _Z12PDH_baselinev, .-_Z12PDH_baselinev
.globl _Z50__device_stub__Z8PDH_CudaP8atomdescP10hist_entryxdP8atomdescP10hist_entryxd
.type _Z50__device_stub__Z8PDH_CudaP8atomdescP10hist_entryxdP8atomdescP10hist_entryxd, @function
_Z50__device_stub__Z8PDH_CudaP8atomdescP10hist_entryxdP8atomdescP10hist_entryxd:
.LFB3702:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movsd %xmm0, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L68
.L64:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L69
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L68:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z8PDH_CudaP8atomdescP10hist_entryxd(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L64
.L69:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3702:
.size _Z50__device_stub__Z8PDH_CudaP8atomdescP10hist_entryxdP8atomdescP10hist_entryxd, .-_Z50__device_stub__Z8PDH_CudaP8atomdescP10hist_entryxdP8atomdescP10hist_entryxd
.globl _Z8PDH_CudaP8atomdescP10hist_entryxd
.type _Z8PDH_CudaP8atomdescP10hist_entryxd, @function
_Z8PDH_CudaP8atomdescP10hist_entryxd:
.LFB3703:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z50__device_stub__Z8PDH_CudaP8atomdescP10hist_entryxdP8atomdescP10hist_entryxd
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3703:
.size _Z8PDH_CudaP8atomdescP10hist_entryxd, .-_Z8PDH_CudaP8atomdescP10hist_entryxd
.globl _Z8CudaPrepP10hist_entry
.type _Z8CudaPrepP10hist_entry, @function
_Z8CudaPrepP10hist_entry:
.LFB3676:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $1096, %rsp
.cfi_def_cfa_offset 1136
movq %rdi, %r12
movq %fs:40, %rax
movq %rax, 1080(%rsp)
xorl %eax, %eax
movq PDH_acnt(%rip), %rax
leal (%rax,%rax,2), %ebx
sall $3, %ebx
movl num_buckets(%rip), %eax
leal 0(,%rax,8), %ebp
movl $0, %edi
call cudaSetDevice@PLT
leaq 48(%rsp), %rdi
movl $0, %esi
call cudaGetDeviceProperties_v2@PLT
movl 356(%rsp), %r13d
movl $1, 28(%rsp)
movl $1, 32(%rsp)
pxor %xmm0, %xmm0
cvtsi2ssq PDH_acnt(%rip), %xmm0
movl %r13d, %eax
pxor %xmm1, %xmm1
cvtsi2ssq %rax, %xmm1
divss %xmm1, %xmm0
movaps %xmm0, %xmm3
movss .LC10(%rip), %xmm2
movaps %xmm0, %xmm1
andps %xmm2, %xmm1
movss .LC7(%rip), %xmm4
ucomiss %xmm1, %xmm4
jbe .L75
cvttss2sil %xmm0, %eax
pxor %xmm1, %xmm1
cvtsi2ssl %eax, %xmm1
cmpnless %xmm1, %xmm3
movss .LC9(%rip), %xmm4
andps %xmm4, %xmm3
addss %xmm1, %xmm3
andnps %xmm0, %xmm2
orps %xmm2, %xmm3
.L75:
cvttss2siq %xmm3, %rax
movl %eax, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movslq %ebp, %rbp
leaq 8(%rsp), %rdi
movq %rbp, %rsi
call cudaMalloc@PLT
movslq %ebx, %rbx
leaq 16(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %rbx, %rdx
movq atom_list(%rip), %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movq %rbp, %rdx
movl $0, %esi
movq 8(%rsp), %rdi
call cudaMemset@PLT
movl %r13d, 24(%rsp)
movl 32(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 24(%rsp), %rdx
movq 36(%rsp), %rdi
movl 44(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L79
.L76:
movl $2, %ecx
movq %rbp, %rdx
movq 8(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 1080(%rsp), %rax
subq %fs:40, %rax
jne .L80
addq $1096, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L79:
.cfi_restore_state
movsd PDH_res(%rip), %xmm0
movq PDH_acnt(%rip), %rdx
movq 8(%rsp), %rsi
movq 16(%rsp), %rdi
call _Z50__device_stub__Z8PDH_CudaP8atomdescP10hist_entryxdP8atomdescP10hist_entryxd
jmp .L76
.L80:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3676:
.size _Z8CudaPrepP10hist_entry, .-_Z8CudaPrepP10hist_entry
.section .rodata.str1.8
.align 8
.LC14:
.string "\nCPU vs GPU Histogram Differences\n"
.text
.globl main
.type main, @function
main:
.LFB3677:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
movq %rsi, %rbx
movq 8(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
cltq
movq %rax, PDH_acnt(%rip)
movq 16(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, PDH_res(%rip)
movsd .LC11(%rip), %xmm1
divsd %xmm0, %xmm1
cvttsd2sil %xmm1, %edi
addl $1, %edi
movl %edi, num_buckets(%rip)
movslq %edi, %rdi
salq $3, %rdi
call malloc@PLT
movq %rax, histogram(%rip)
movq PDH_acnt(%rip), %rax
leaq (%rax,%rax,2), %rdi
salq $3, %rdi
call malloc@PLT
movq %rax, atom_list(%rip)
movl $1, %edi
call srand@PLT
cmpq $0, PDH_acnt(%rip)
jle .L82
movl $0, %ebx
movl $0, %ebp
.L83:
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2sdl %eax, %xmm0
divsd .LC12(%rip), %xmm0
mulsd .LC13(%rip), %xmm0
movq atom_list(%rip), %rax
movsd %xmm0, (%rax,%rbx)
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2sdl %eax, %xmm0
divsd .LC12(%rip), %xmm0
mulsd .LC13(%rip), %xmm0
movq atom_list(%rip), %rax
movsd %xmm0, 8(%rax,%rbx)
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2sdl %eax, %xmm0
divsd .LC12(%rip), %xmm0
mulsd .LC13(%rip), %xmm0
movq atom_list(%rip), %rax
movsd %xmm0, 16(%rax,%rbx)
addq $1, %rbp
addq $24, %rbx
cmpq %rbp, PDH_acnt(%rip)
jg .L83
.L82:
leaq Idunno(%rip), %r12
movq %r12, %rsi
leaq startTime(%rip), %rbp
movq %rbp, %rdi
call gettimeofday@PLT
call _Z12PDH_baselinev
call _Z19report_running_timev
call _Z16output_histogramv
movslq num_buckets(%rip), %rdi
salq $3, %rdi
call malloc@PLT
movq %rax, %rbx
movq %r12, %rsi
movq %rbp, %rdi
call gettimeofday@PLT
movq %rbx, %rdi
call _Z8CudaPrepP10hist_entry
movl $1, %edi
call _Z19report_running_timei
movq %rbx, %rdi
call _Z16output_histogramP10hist_entry
leaq .LC14(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %rbx, %rsi
movq histogram(%rip), %rdi
call _Z16output_histogramP10hist_entryS0_
movq histogram(%rip), %rdi
call free@PLT
movq atom_list(%rip), %rdi
call free@PLT
movl $0, %eax
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3677:
.size main, .-main
.section .rodata.str1.8
.align 8
.LC15:
.string "_Z8PDH_CudaP8atomdescP10hist_entryxd"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3705:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC15(%rip), %rdx
movq %rdx, %rcx
leaq _Z8PDH_CudaP8atomdescP10hist_entryxd(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3705:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl endTime
.bss
.align 16
.type endTime, @object
.size endTime, 16
endTime:
.zero 16
.globl startTime
.align 16
.type startTime, @object
.size startTime, 16
startTime:
.zero 16
.globl Idunno
.align 8
.type Idunno, @object
.size Idunno, 8
Idunno:
.zero 8
.globl atom_list
.align 8
.type atom_list, @object
.size atom_list, 8
atom_list:
.zero 8
.globl PDH_res
.align 8
.type PDH_res, @object
.size PDH_res, 8
PDH_res:
.zero 8
.globl num_buckets
.align 4
.type num_buckets, @object
.size num_buckets, 4
num_buckets:
.zero 4
.globl PDH_acnt
.align 8
.type PDH_acnt, @object
.size PDH_acnt, 8
PDH_acnt:
.zero 8
.globl histogram
.align 8
.type histogram, @object
.size histogram, 8
histogram:
.zero 8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC1:
.long 0
.long 1093567616
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC7:
.long 1258291200
.align 4
.LC9:
.long 1065353216
.align 4
.LC10:
.long 2147483647
.section .rodata.cst8
.align 8
.LC11:
.long 0
.long 1088648064
.align 8
.LC12:
.long -4194304
.long 1105199103
.align 8
.LC13:
.long 0
.long 1087796736
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
```
|
```amdasm
.text
.file "proj1-danielsawyer.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z12p2p_distanceii # -- Begin function _Z12p2p_distanceii
.type _Z12p2p_distanceii,@function
_Z12p2p_distanceii: # @_Z12p2p_distanceii
.cfi_startproc
# %bb.0:
movq atom_list(%rip), %rax
movslq %edi, %rcx
leaq (%rcx,%rcx,2), %rcx
movslq %esi, %rdx
leaq (%rdx,%rdx,2), %rdx
movsd (%rax,%rcx,8), %xmm0 # xmm0 = mem[0],zero
movsd 8(%rax,%rcx,8), %xmm1 # xmm1 = mem[0],zero
subsd (%rax,%rdx,8), %xmm0
movsd 16(%rax,%rcx,8), %xmm2 # xmm2 = mem[0],zero
mulsd %xmm0, %xmm0
subsd 8(%rax,%rdx,8), %xmm1
mulsd %xmm1, %xmm1
addsd %xmm0, %xmm1
subsd 16(%rax,%rdx,8), %xmm2
mulsd %xmm2, %xmm2
addsd %xmm1, %xmm2
xorps %xmm0, %xmm0
sqrtsd %xmm2, %xmm0
retq
.Lfunc_end0:
.size _Z12p2p_distanceii, .Lfunc_end0-_Z12p2p_distanceii
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z19report_running_timev
.LCPI1_0:
.quad 0x412e848000000000 # double 1.0E+6
.text
.globl _Z19report_running_timev
.type _Z19report_running_timev,@function
_Z19report_running_timev: # @_Z19report_running_timev
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
pushq %rax
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movl $endTime, %edi
movl $Idunno, %esi
callq gettimeofday
movq endTime(%rip), %rax
subq startTime(%rip), %rax
movq endTime+8(%rip), %rcx
subq startTime+8(%rip), %rcx
leaq 1000000(%rcx), %rbx
movq %rcx, %r14
sarq $63, %r14
addq %rax, %r14
testq %rcx, %rcx
cmovnsq %rcx, %rbx
movl $.L.str, %edi
movq %r14, %rsi
movq %rbx, %rdx
xorl %eax, %eax
callq printf
cvtsi2sd %r14, %xmm1
cvtsi2sd %rbx, %xmm0
divsd .LCPI1_0(%rip), %xmm0
addsd %xmm1, %xmm0
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z19report_running_timev, .Lfunc_end1-_Z19report_running_timev
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z19report_running_timei
.LCPI2_0:
.quad 0x412e848000000000 # double 1.0E+6
.text
.globl _Z19report_running_timei
.type _Z19report_running_timei,@function
_Z19report_running_timei: # @_Z19report_running_timei
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
pushq %rax
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movl $endTime, %edi
movl $Idunno, %esi
callq gettimeofday
movq endTime(%rip), %rax
subq startTime(%rip), %rax
movq endTime+8(%rip), %rcx
subq startTime+8(%rip), %rcx
leaq 1000000(%rcx), %rbx
movq %rcx, %r14
sarq $63, %r14
addq %rax, %r14
testq %rcx, %rcx
cmovnsq %rcx, %rbx
movl $.L.str.1, %edi
movq %r14, %rsi
movq %rbx, %rdx
xorl %eax, %eax
callq printf
cvtsi2sd %r14, %xmm1
cvtsi2sd %rbx, %xmm0
divsd .LCPI2_0(%rip), %xmm0
addsd %xmm1, %xmm0
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size _Z19report_running_timei, .Lfunc_end2-_Z19report_running_timei
.cfi_endproc
# -- End function
.globl _Z16output_histogramv # -- Begin function _Z16output_histogramv
.type _Z16output_histogramv,@function
_Z16output_histogramv: # @_Z16output_histogramv
.cfi_startproc
# %bb.0:
cmpl $0, num_buckets(%rip)
jle .LBB3_9
# %bb.1: # %.lr.ph.preheader
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $3435973837, %r15d # imm = 0xCCCCCCCD
xorl %ebx, %ebx
xorl %r14d, %r14d
.LBB3_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl %ebx, %eax
imulq %r15, %rax
shrq $34, %rax
leal (%rax,%rax,4), %eax
cmpl %eax, %ebx
jne .LBB3_4
# %bb.3: # in Loop: Header=BB3_2 Depth=1
movl $.L.str.2, %edi
movl %ebx, %esi
xorl %eax, %eax
callq printf
.LBB3_4: # in Loop: Header=BB3_2 Depth=1
movq histogram(%rip), %rax
movq (%rax,%rbx,8), %rsi
movl $.L.str.3, %edi
xorl %eax, %eax
callq printf
movq histogram(%rip), %rax
addq (%rax,%rbx,8), %r14
movl num_buckets(%rip), %eax
decl %eax
cmpq %rax, %rbx
jne .LBB3_6
# %bb.5: # in Loop: Header=BB3_2 Depth=1
movl $.L.str.4, %edi
movq %r14, %rsi
xorl %eax, %eax
callq printf
jmp .LBB3_7
.LBB3_6: # in Loop: Header=BB3_2 Depth=1
movl $.L.str.5, %edi
xorl %eax, %eax
callq printf
.LBB3_7: # in Loop: Header=BB3_2 Depth=1
incq %rbx
movslq num_buckets(%rip), %rax
cmpq %rax, %rbx
jl .LBB3_2
# %bb.8:
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r14
.cfi_restore %r15
.LBB3_9: # %._crit_edge
retq
.Lfunc_end3:
.size _Z16output_histogramv, .Lfunc_end3-_Z16output_histogramv
.cfi_endproc
# -- End function
.globl _Z16output_histogramP10hist_entry # -- Begin function _Z16output_histogramP10hist_entry
.type _Z16output_histogramP10hist_entry,@function
_Z16output_histogramP10hist_entry: # @_Z16output_histogramP10hist_entry
.cfi_startproc
# %bb.0:
cmpl $0, num_buckets(%rip)
jle .LBB4_9
# %bb.1: # %.lr.ph.preheader
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
pushq %rax
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rdi, %rbx
movl $3435973837, %r12d # imm = 0xCCCCCCCD
xorl %r14d, %r14d
xorl %r15d, %r15d
.LBB4_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl %r14d, %eax
imulq %r12, %rax
shrq $34, %rax
leal (%rax,%rax,4), %eax
cmpl %eax, %r14d
jne .LBB4_4
# %bb.3: # in Loop: Header=BB4_2 Depth=1
movl $.L.str.2, %edi
movl %r14d, %esi
xorl %eax, %eax
callq printf
.LBB4_4: # in Loop: Header=BB4_2 Depth=1
movq (%rbx,%r14,8), %rsi
movl $.L.str.3, %edi
xorl %eax, %eax
callq printf
addq (%rbx,%r14,8), %r15
movl num_buckets(%rip), %eax
decl %eax
cmpq %rax, %r14
jne .LBB4_6
# %bb.5: # in Loop: Header=BB4_2 Depth=1
movl $.L.str.4, %edi
movq %r15, %rsi
xorl %eax, %eax
callq printf
jmp .LBB4_7
.LBB4_6: # in Loop: Header=BB4_2 Depth=1
movl $.L.str.5, %edi
xorl %eax, %eax
callq printf
.LBB4_7: # in Loop: Header=BB4_2 Depth=1
incq %r14
movslq num_buckets(%rip), %rax
cmpq %rax, %r14
jl .LBB4_2
# %bb.8:
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r12
.cfi_restore %r14
.cfi_restore %r15
.LBB4_9: # %._crit_edge
retq
.Lfunc_end4:
.size _Z16output_histogramP10hist_entry, .Lfunc_end4-_Z16output_histogramP10hist_entry
.cfi_endproc
# -- End function
.globl _Z16output_histogramP10hist_entryS0_ # -- Begin function _Z16output_histogramP10hist_entryS0_
.type _Z16output_histogramP10hist_entryS0_,@function
_Z16output_histogramP10hist_entryS0_: # @_Z16output_histogramP10hist_entryS0_
.cfi_startproc
# %bb.0:
cmpl $0, num_buckets(%rip)
jle .LBB5_9
# %bb.1: # %.lr.ph.preheader
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
pushq %rax
.cfi_def_cfa_offset 64
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsi, %rbx
movq %rdi, %r14
movl $3435973837, %r12d # imm = 0xCCCCCCCD
xorl %r15d, %r15d
xorl %r13d, %r13d
xorl %ebp, %ebp
.LBB5_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl %r15d, %eax
imulq %r12, %rax
shrq $34, %rax
leal (%rax,%rax,4), %eax
cmpl %eax, %r15d
jne .LBB5_4
# %bb.3: # in Loop: Header=BB5_2 Depth=1
movl $.L.str.2, %edi
movl %r15d, %esi
xorl %eax, %eax
callq printf
.LBB5_4: # in Loop: Header=BB5_2 Depth=1
movq (%r14,%r15,8), %rax
subq (%rbx,%r15,8), %rax
movq %rax, %rsi
negq %rsi
cmovsq %rax, %rsi
movl $.L.str.3, %edi
xorl %eax, %eax
callq printf
addq (%r14,%r15,8), %rbp
addq (%rbx,%r15,8), %r13
movl num_buckets(%rip), %eax
decl %eax
cmpq %rax, %r15
jne .LBB5_6
# %bb.5: # in Loop: Header=BB5_2 Depth=1
movq %rbp, %rax
subq %r13, %rax
movq %rax, %rsi
negq %rsi
cmovsq %rax, %rsi
movl $.L.str.4, %edi
xorl %eax, %eax
callq printf
jmp .LBB5_7
.LBB5_6: # in Loop: Header=BB5_2 Depth=1
movl $.L.str.5, %edi
xorl %eax, %eax
callq printf
.LBB5_7: # in Loop: Header=BB5_2 Depth=1
incq %r15
movslq num_buckets(%rip), %rax
cmpq %rax, %r15
jl .LBB5_2
# %bb.8:
addq $8, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r12
.cfi_restore %r13
.cfi_restore %r14
.cfi_restore %r15
.cfi_restore %rbp
.LBB5_9: # %._crit_edge
retq
.Lfunc_end5:
.size _Z16output_histogramP10hist_entryS0_, .Lfunc_end5-_Z16output_histogramP10hist_entryS0_
.cfi_endproc
# -- End function
.globl _Z12PDH_baselinev # -- Begin function _Z12PDH_baselinev
.type _Z12PDH_baselinev,@function
_Z12PDH_baselinev: # @_Z12PDH_baselinev
.cfi_startproc
# %bb.0:
movq PDH_acnt(%rip), %rax
testq %rax, %rax
jle .LBB6_7
# %bb.1: # %.lr.ph11
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $16, %rsp
.cfi_def_cfa_offset 64
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movsd PDH_res(%rip), %xmm1 # xmm1 = mem[0],zero
movl $1, %r15d
movq histogram(%rip), %r12
xorl %r13d, %r13d
movsd %xmm1, 8(%rsp) # 8-byte Spill
.LBB6_3: # =>This Loop Header: Depth=1
# Child Loop BB6_5 Depth 2
movq %r13, %rbx
incq %r13
cmpq %r13, %rax
jle .LBB6_2
# %bb.4: # %.lr.ph.preheader
# in Loop: Header=BB6_3 Depth=1
movq %r15, %r14
.LBB6_5: # %.lr.ph
# Parent Loop BB6_3 Depth=1
# => This Inner Loop Header: Depth=2
movl %ebx, %edi
movl %r14d, %esi
callq _Z12p2p_distanceii
movsd 8(%rsp), %xmm1 # 8-byte Reload
# xmm1 = mem[0],zero
divsd %xmm1, %xmm0
cvttsd2si %xmm0, %eax
cltq
incq (%r12,%rax,8)
incq %r14
movq PDH_acnt(%rip), %rax
cmpq %r14, %rax
jg .LBB6_5
.LBB6_2: # %.loopexit
# in Loop: Header=BB6_3 Depth=1
incq %r15
cmpq %r13, %rax
jg .LBB6_3
# %bb.6:
addq $16, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r12
.cfi_restore %r13
.cfi_restore %r14
.cfi_restore %r15
.LBB6_7: # %._crit_edge
xorl %eax, %eax
retq
.Lfunc_end6:
.size _Z12PDH_baselinev, .Lfunc_end6-_Z12PDH_baselinev
.cfi_endproc
# -- End function
.globl _Z23__device_stub__PDH_CudaP8atomdescP10hist_entryxd # -- Begin function _Z23__device_stub__PDH_CudaP8atomdescP10hist_entryxd
.type _Z23__device_stub__PDH_CudaP8atomdescP10hist_entryxd,@function
_Z23__device_stub__PDH_CudaP8atomdescP10hist_entryxd: # @_Z23__device_stub__PDH_CudaP8atomdescP10hist_entryxd
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $112, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 40(%rsp), %rax
movq %rdi, (%rax)
leaq 32(%rsp), %rcx
movq %rsi, (%rcx)
leaq 24(%rsp), %rsi
movq %rdx, (%rsi)
leaq 16(%rsp), %rdx
movsd %xmm0, (%rdx)
leaq 80(%rsp), %rbx
movq %rax, (%rbx)
movq %rcx, 8(%rbx)
movq %rsi, 16(%rbx)
movq %rdx, 24(%rbx)
leaq 64(%rsp), %r14
leaq 48(%rsp), %r15
leaq 8(%rsp), %r12
movq %rsp, %r13
movq %r14, %rdi
movq %r15, %rsi
movq %r12, %rdx
movq %r13, %rcx
callq __hipPopCallConfiguration
movq (%r14), %rsi
movl 8(%r14), %edx
movq (%r15), %rcx
movl 8(%r15), %r8d
movl $_Z8PDH_CudaP8atomdescP10hist_entryxd, %edi
movq %rbx, %r9
pushq (%r13)
.cfi_adjust_cfa_offset 8
pushq (%r12)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $128, %rsp
.cfi_adjust_cfa_offset -128
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end7:
.size _Z23__device_stub__PDH_CudaP8atomdescP10hist_entryxd, .Lfunc_end7-_Z23__device_stub__PDH_CudaP8atomdescP10hist_entryxd
.cfi_endproc
# -- End function
.globl _Z8CudaPrepP10hist_entry # -- Begin function _Z8CudaPrepP10hist_entry
.type _Z8CudaPrepP10hist_entry,@function
_Z8CudaPrepP10hist_entry: # @_Z8CudaPrepP10hist_entry
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $1496, %rsp # imm = 0x5D8
.cfi_def_cfa_offset 1552
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rdi, 16(%rsp) # 8-byte Spill
movq PDH_acnt(%rip), %rbx
movl num_buckets(%rip), %ebp
shll $3, %ebp
xorl %edi, %edi
callq hipSetDevice
leaq 24(%rsp), %r14
movq %r14, %rdi
xorl %esi, %esi
callq hipGetDevicePropertiesR0600
cvtsi2ssq PDH_acnt(%rip), %xmm0
movl 308(%r14), %r15d
cvtsi2ss %r15, %xmm1
btsq $32, %r15
divss %xmm1, %xmm0
callq ceilf@PLT
cvttss2si %xmm0, %rax
movl %eax, %r12d
btsq $32, %r12
movslq %ebp, %r14
movq %rsp, %r13
movq %r13, %rdi
movq %r14, %rsi
callq hipMalloc
shlq $35, %rbx
leaq (%rbx,%rbx,2), %rbp
sarq $32, %rbp
leaq 8(%rsp), %rbx
movq %rbx, %rdi
movq %rbp, %rsi
callq hipMalloc
movq (%rbx), %rdi
movq atom_list(%rip), %rsi
movq %rbp, %rdx
movl $1, %ecx
callq hipMemcpy
movq (%r13), %rdi
xorl %esi, %esi
movq %r14, %rdx
callq hipMemset
movq %r12, %rdi
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB8_2
# %bb.1:
movq 8(%rsp), %rdi
movq (%rsp), %rsi
movq PDH_acnt(%rip), %rdx
movsd PDH_res(%rip), %xmm0 # xmm0 = mem[0],zero
callq _Z23__device_stub__PDH_CudaP8atomdescP10hist_entryxd
.LBB8_2:
movq (%rsp), %rsi
movq 16(%rsp), %rdi # 8-byte Reload
movq %r14, %rdx
movl $2, %ecx
callq hipMemcpy
movq (%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
addq $1496, %rsp # imm = 0x5D8
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end8:
.size _Z8CudaPrepP10hist_entry, .Lfunc_end8-_Z8CudaPrepP10hist_entry
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI9_0:
.quad 0x40e3738000000000 # double 39836
.LCPI9_1:
.quad 0x41dfffffffc00000 # double 2147483647
.LCPI9_2:
.quad 0x40d6760000000000 # double 23000
.text
.globl main
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
pushq %rax
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movq %rsi, %rbx
movq 8(%rsi), %rdi
callq atoi
movslq %eax, %r14
movq %r14, PDH_acnt(%rip)
movq 16(%rbx), %rdi
callq atof
movsd %xmm0, PDH_res(%rip)
movsd .LCPI9_0(%rip), %xmm1 # xmm1 = mem[0],zero
divsd %xmm0, %xmm1
cvttsd2si %xmm1, %eax
leal 1(%rax), %ecx
movl %ecx, num_buckets(%rip)
cltq
leaq 8(,%rax,8), %rdi
callq malloc
movq %rax, histogram(%rip)
shlq $3, %r14
leaq (%r14,%r14,2), %rdi
callq malloc
movq %rax, atom_list(%rip)
movl $1, %edi
callq srand
cmpq $0, PDH_acnt(%rip)
jle .LBB9_3
# %bb.1: # %.lr.ph.preheader
xorl %ebx, %ebx
xorl %r14d, %r14d
.LBB9_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
callq rand
xorps %xmm0, %xmm0
cvtsi2sd %eax, %xmm0
movsd .LCPI9_1(%rip), %xmm1 # xmm1 = mem[0],zero
divsd %xmm1, %xmm0
movsd .LCPI9_2(%rip), %xmm1 # xmm1 = mem[0],zero
mulsd %xmm1, %xmm0
movq atom_list(%rip), %rax
movsd %xmm0, (%rax,%rbx)
callq rand
xorps %xmm0, %xmm0
cvtsi2sd %eax, %xmm0
divsd .LCPI9_1(%rip), %xmm0
mulsd .LCPI9_2(%rip), %xmm0
movq atom_list(%rip), %rax
movsd %xmm0, 8(%rax,%rbx)
callq rand
xorps %xmm0, %xmm0
cvtsi2sd %eax, %xmm0
divsd .LCPI9_1(%rip), %xmm0
mulsd .LCPI9_2(%rip), %xmm0
movq atom_list(%rip), %rax
movsd %xmm0, 16(%rax,%rbx)
incq %r14
addq $24, %rbx
cmpq %r14, PDH_acnt(%rip)
jg .LBB9_2
.LBB9_3: # %._crit_edge
movl $startTime, %edi
movl $Idunno, %esi
callq gettimeofday
callq _Z12PDH_baselinev
callq _Z19report_running_timev
callq _Z16output_histogramv
movslq num_buckets(%rip), %rdi
shlq $3, %rdi
callq malloc
movq %rax, %rbx
movl $startTime, %edi
movl $Idunno, %esi
callq gettimeofday
movq %rbx, %rdi
callq _Z8CudaPrepP10hist_entry
callq _Z19report_running_timei
movq %rbx, %rdi
callq _Z16output_histogramP10hist_entry
movl $.Lstr, %edi
callq puts@PLT
movq histogram(%rip), %rdi
movq %rbx, %rsi
callq _Z16output_histogramP10hist_entryS0_
movq histogram(%rip), %rdi
callq free
movq atom_list(%rip), %rdi
callq free
xorl %eax, %eax
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.Lfunc_end9:
.size main, .Lfunc_end9-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
jne .LBB10_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, %rdi
movq %rax, __hip_gpubin_handle(%rip)
.LBB10_2:
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8PDH_CudaP8atomdescP10hist_entryxd, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end10:
.size __hip_module_ctor, .Lfunc_end10-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB11_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB11_2:
retq
.Lfunc_end11:
.size __hip_module_dtor, .Lfunc_end11-__hip_module_dtor
.cfi_endproc
# -- End function
.type histogram,@object # @histogram
.bss
.globl histogram
.p2align 3, 0x0
histogram:
.quad 0
.size histogram, 8
.type PDH_acnt,@object # @PDH_acnt
.globl PDH_acnt
.p2align 3, 0x0
PDH_acnt:
.quad 0 # 0x0
.size PDH_acnt, 8
.type num_buckets,@object # @num_buckets
.globl num_buckets
.p2align 2, 0x0
num_buckets:
.long 0 # 0x0
.size num_buckets, 4
.type PDH_res,@object # @PDH_res
.globl PDH_res
.p2align 3, 0x0
PDH_res:
.quad 0x0000000000000000 # double 0
.size PDH_res, 8
.type atom_list,@object # @atom_list
.globl atom_list
.p2align 3, 0x0
atom_list:
.quad 0
.size atom_list, 8
.type Idunno,@object # @Idunno
.globl Idunno
.p2align 2, 0x0
Idunno:
.zero 8
.size Idunno, 8
.type startTime,@object # @startTime
.globl startTime
.p2align 3, 0x0
startTime:
.zero 16
.size startTime, 16
.type endTime,@object # @endTime
.globl endTime
.p2align 3, 0x0
endTime:
.zero 16
.size endTime, 16
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Running time for CPU version: %ld.%06ld\n"
.size .L.str, 41
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "\nRunning time for GPU version: %ld.%06ld\n"
.size .L.str.1, 42
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "\n%02d: "
.size .L.str.2, 8
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "%15lld "
.size .L.str.3, 8
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "\n T:%lld \n"
.size .L.str.4, 11
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "| "
.size .L.str.5, 3
.type _Z8PDH_CudaP8atomdescP10hist_entryxd,@object # @_Z8PDH_CudaP8atomdescP10hist_entryxd
.section .rodata,"a",@progbits
.globl _Z8PDH_CudaP8atomdescP10hist_entryxd
.p2align 3, 0x0
_Z8PDH_CudaP8atomdescP10hist_entryxd:
.quad _Z23__device_stub__PDH_CudaP8atomdescP10hist_entryxd
.size _Z8PDH_CudaP8atomdescP10hist_entryxd, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z8PDH_CudaP8atomdescP10hist_entryxd"
.size .L__unnamed_1, 37
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "\nCPU vs GPU Histogram Differences"
.size .Lstr, 34
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z23__device_stub__PDH_CudaP8atomdescP10hist_entryxd
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym Idunno
.addrsig_sym startTime
.addrsig_sym endTime
.addrsig_sym _Z8PDH_CudaP8atomdescP10hist_entryxd
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
```
| 10,552 | 11,219 |
260 |
Convert the following CUDA device assembly code to AMD device assembly:
```cudaasm
code for sm_80
Function : _Z20populate_reverse_padPKdPdS0_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ;
S2R R0, SR_CTAID.X ;
IMAD.MOV.U32 R5, RZ, RZ, 0x8 ;
ULDC.64 UR4, c[0x0][0x118] ;
S2R R3, SR_TID.X ;
IMAD R0, R0, c[0x0][0x0], R3 ;
IMAD.WIDE R2, R0.reuse, R5, c[0x0][0x168] ;
ISETP.GE.AND P0, PT, R0, c[0x0][0x178], PT ;
@!P0 BRA 0xd0 ;
ISETP.GE.AND P0, PT, R0, c[0x0][0x17c], PT ;
@P0 EXIT ;
STG.E.64 [R2.64], RZ ;
EXIT ;
LOP3.LUT R0, RZ, R0, RZ, 0x33, !PT ;
MOV R6, c[0x0][0x170] ;
IADD3 R0, R0, c[0x0][0x178], RZ ;
MOV R7, c[0x0][0x174] ;
IMAD.WIDE R4, R0, R5, c[0x0][0x160] ;
LDG.E.64 R6, [R6.64] ;
LDG.E.64 R4, [R4.64] ;
DADD R8, R4, -R6 ;
STG.E.64 [R2.64], R8 ;
EXIT ;
BRA 0x170;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
```
|
```amdasm
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z20populate_reverse_padPKdPdS0_ii ; -- Begin function _Z20populate_reverse_padPKdPdS0_ii
.globl _Z20populate_reverse_padPKdPdS0_ii
.p2align 8
.type _Z20populate_reverse_padPKdPdS0_ii,@function
_Z20populate_reverse_padPKdPdS0_ii: ; @_Z20populate_reverse_padPKdPdS0_ii
; %bb.0:
s_clause 0x1
s_load_b32 s8, s[0:1], 0x2c
s_load_b256 s[0:7], s[0:1], 0x0
s_mov_b32 s10, 0
s_mov_b32 s11, exec_lo
s_waitcnt lgkmcnt(0)
s_and_b32 s8, s8, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s8, v[0:1]
; implicit-def: $sgpr8_sgpr9
v_cmpx_le_i32_e64 s6, v1
s_xor_b32 s11, exec_lo, s11
; %bb.1:
v_cmp_gt_i32_e32 vcc_lo, s7, v1
s_mov_b64 s[8:9], 0
s_and_b32 s10, vcc_lo, exec_lo
; %bb.2: ; %Flow
s_or_saveexec_b32 s7, s11
v_dual_mov_b32 v3, s8 :: v_dual_mov_b32 v4, s9
s_xor_b32 exec_lo, exec_lo, s7
s_cbranch_execz .LBB0_4
; %bb.3:
v_xad_u32 v2, v1, -1, s6
s_or_b32 s10, s10, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[2:3], 3, v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s0, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
s_load_b64 s[0:1], s[4:5], 0x0
global_load_b64 v[2:3], v[2:3], off
s_waitcnt vmcnt(0) lgkmcnt(0)
v_add_f64 v[3:4], v[2:3], -s[0:1]
.LBB0_4: ; %Flow32
s_or_b32 exec_lo, exec_lo, s7
s_and_saveexec_b32 s0, s10
s_cbranch_execz .LBB0_6
; %bb.5: ; %.sink.split
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 3, v[1:2]
v_add_co_u32 v0, vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_store_b64 v[0:1], v[3:4], off
.LBB0_6:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z20populate_reverse_padPKdPdS0_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z20populate_reverse_padPKdPdS0_ii, .Lfunc_end0-_Z20populate_reverse_padPKdPdS0_ii
; -- End function
.section .AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 232
; NumSgprs: 18
; NumVgprs: 5
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 5
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object ; @__hip_cuid_
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0 ; 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z20populate_reverse_padPKdPdS0_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z20populate_reverse_padPKdPdS0_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
```
| 506 | 2,953 |
261 |
Convert the following CUDA host assembly code to AMD host assembly:
```cudaasm
.file "tmpxft_0003b533_00000000-6_populate_reverse_pad.cudafe1.cpp"
.text
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z48__device_stub__Z20populate_reverse_padPKdPdS0_iiPKdPdS0_ii
.type _Z48__device_stub__Z20populate_reverse_padPKdPdS0_iiPKdPdS0_ii, @function
_Z48__device_stub__Z20populate_reverse_padPKdPdS0_iiPKdPdS0_ii:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z20populate_reverse_padPKdPdS0_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z48__device_stub__Z20populate_reverse_padPKdPdS0_iiPKdPdS0_ii, .-_Z48__device_stub__Z20populate_reverse_padPKdPdS0_iiPKdPdS0_ii
.globl _Z20populate_reverse_padPKdPdS0_ii
.type _Z20populate_reverse_padPKdPdS0_ii, @function
_Z20populate_reverse_padPKdPdS0_ii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z48__device_stub__Z20populate_reverse_padPKdPdS0_iiPKdPdS0_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z20populate_reverse_padPKdPdS0_ii, .-_Z20populate_reverse_padPKdPdS0_ii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z20populate_reverse_padPKdPdS0_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z20populate_reverse_padPKdPdS0_ii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
```
|
```amdasm
.text
.file "populate_reverse_pad.hip"
.globl _Z35__device_stub__populate_reverse_padPKdPdS0_ii # -- Begin function _Z35__device_stub__populate_reverse_padPKdPdS0_ii
.type _Z35__device_stub__populate_reverse_padPKdPdS0_ii,@function
_Z35__device_stub__populate_reverse_padPKdPdS0_ii: # @_Z35__device_stub__populate_reverse_padPKdPdS0_ii
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $128, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 40(%rsp), %rax
movq %rdi, (%rax)
leaq 32(%rsp), %rdi
movq %rsi, (%rdi)
leaq 24(%rsp), %rsi
movq %rdx, (%rsi)
leaq 4(%rsp), %rdx
movl %ecx, (%rdx)
movq %rsp, %rcx
movl %r8d, (%rcx)
leaq 80(%rsp), %rbx
movq %rax, (%rbx)
movq %rdi, 8(%rbx)
movq %rsi, 16(%rbx)
movq %rdx, 24(%rbx)
movq %rcx, 32(%rbx)
leaq 64(%rsp), %r14
leaq 48(%rsp), %r15
leaq 16(%rsp), %r12
leaq 8(%rsp), %r13
movq %r14, %rdi
movq %r15, %rsi
movq %r12, %rdx
movq %r13, %rcx
callq __hipPopCallConfiguration
movq (%r14), %rsi
movl 8(%r14), %edx
movq (%r15), %rcx
movl 8(%r15), %r8d
movl $_Z20populate_reverse_padPKdPdS0_ii, %edi
movq %rbx, %r9
pushq (%r13)
.cfi_adjust_cfa_offset 8
pushq (%r12)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $144, %rsp
.cfi_adjust_cfa_offset -144
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z35__device_stub__populate_reverse_padPKdPdS0_ii, .Lfunc_end0-_Z35__device_stub__populate_reverse_padPKdPdS0_ii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, %rdi
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z20populate_reverse_padPKdPdS0_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z20populate_reverse_padPKdPdS0_ii,@object # @_Z20populate_reverse_padPKdPdS0_ii
.section .rodata,"a",@progbits
.globl _Z20populate_reverse_padPKdPdS0_ii
.p2align 3, 0x0
_Z20populate_reverse_padPKdPdS0_ii:
.quad _Z35__device_stub__populate_reverse_padPKdPdS0_ii
.size _Z20populate_reverse_padPKdPdS0_ii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z20populate_reverse_padPKdPdS0_ii"
.size .L__unnamed_1, 35
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z35__device_stub__populate_reverse_padPKdPdS0_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z20populate_reverse_padPKdPdS0_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
```
| 2,018 | 2,190 |
262 |
Convert the following CUDA device assembly code to AMD device assembly:
```cudaasm
code for sm_80
Function : _Z15process_kernel1PfS_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ;
S2R R0, SR_CTAID.X ;
S2R R3, SR_TID.X ;
S2R R5, SR_CTAID.Y ;
S2R R2, SR_TID.Y ;
IMAD R0, R0, c[0x0][0x0], R3 ;
ISETP.GE.AND P0, PT, R0, c[0x0][0x174], PT ;
IMAD.MOV.U32 R0, RZ, RZ, 0x1 ;
IMAD R5, R5, c[0x0][0x4], R2 ;
ISETP.GE.OR P0, PT, R5, c[0x0][0x170], P0 ;
ISETP.GT.OR P0, PT, R0, c[0x0][0x170], P0 ;
ISETP.GT.OR P0, PT, R0, c[0x0][0x174], P0 ;
@P0 EXIT ;
IMAD.MOV.U32 R4, RZ, RZ, 0x1 ;
ULDC.64 UR6, c[0x0][0x118] ;
IMAD.MOV.U32 R2, RZ, RZ, RZ ;
IADD3 R4, -R4, c[0x0][0x174], RZ ;
SHF.R.U32.HI R0, RZ, 0x1, R4 ;
IADD3 R3, R0, 0x1, RZ ;
LOP3.LUT R3, R3, 0x3, RZ, 0xc0, !PT ;
IMAD.IADD R0, R0, 0x1, -R3 ;
ISETP.GE.U32.AND P0, PT, R4, 0x6, PT ;
IMAD R6, R5, R2, RZ ;
IADD3 R2, R2, 0x1, RZ ;
UMOV UR4, URZ ;
ISETP.GE.AND P1, PT, R2, c[0x0][0x170], PT ;
@!P0 BRA 0xc50 ;
ISETP.GT.AND P0, PT, R0, -0x1, PT ;
UMOV UR4, URZ ;
IADD3 R7, R6, 0x1, RZ ;
ULDC.64 UR10, c[0x0][0x168] ;
IMAD.MOV.U32 R8, RZ, RZ, R0 ;
ULDC.64 UR8, c[0x0][0x160] ;
@!P0 BRA 0xa70 ;
IADD3 R9, R8, 0x1, RZ ;
PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ;
ISETP.GT.AND P2, PT, R9, 0xc, PT ;
@!P2 BRA 0x750 ;
PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ;
IMAD.U32 R10, RZ, RZ, UR8 ;
IMAD.U32 R11, RZ, RZ, UR9 ;
IMAD.WIDE R10, R7, 0x4, R10 ;
LDG.E R9, [R10.64] ;
IMAD.U32 R12, RZ, RZ, UR10 ;
IMAD.U32 R13, RZ, RZ, UR11 ;
IMAD.WIDE R12, R6, 0x4, R12 ;
STG.E [R12.64], R9 ;
LDG.E R15, [R10.64+-0x4] ;
STG.E [R12.64+0x4], R15 ;
LDG.E R17, [R10.64+0x8] ;
STG.E [R12.64+0x8], R17 ;
LDG.E R19, [R10.64+0x4] ;
STG.E [R12.64+0xc], R19 ;
LDG.E R21, [R10.64+0x10] ;
STG.E [R12.64+0x10], R21 ;
LDG.E R23, [R10.64+0xc] ;
STG.E [R12.64+0x14], R23 ;
LDG.E R9, [R10.64+0x18] ;
STG.E [R12.64+0x18], R9 ;
LDG.E R15, [R10.64+0x14] ;
STG.E [R12.64+0x1c], R15 ;
LDG.E R17, [R10.64+0x20] ;
STG.E [R12.64+0x20], R17 ;
LDG.E R19, [R10.64+0x1c] ;
STG.E [R12.64+0x24], R19 ;
LDG.E R21, [R10.64+0x28] ;
STG.E [R12.64+0x28], R21 ;
LDG.E R23, [R10.64+0x24] ;
STG.E [R12.64+0x2c], R23 ;
LDG.E R9, [R10.64+0x30] ;
STG.E [R12.64+0x30], R9 ;
LDG.E R15, [R10.64+0x2c] ;
STG.E [R12.64+0x34], R15 ;
LDG.E R17, [R10.64+0x38] ;
STG.E [R12.64+0x38], R17 ;
LDG.E R19, [R10.64+0x34] ;
STG.E [R12.64+0x3c], R19 ;
LDG.E R21, [R10.64+0x40] ;
STG.E [R12.64+0x40], R21 ;
LDG.E R23, [R10.64+0x3c] ;
STG.E [R12.64+0x44], R23 ;
LDG.E R9, [R10.64+0x48] ;
STG.E [R12.64+0x48], R9 ;
LDG.E R15, [R10.64+0x44] ;
STG.E [R12.64+0x4c], R15 ;
LDG.E R17, [R10.64+0x50] ;
STG.E [R12.64+0x50], R17 ;
LDG.E R19, [R10.64+0x4c] ;
STG.E [R12.64+0x54], R19 ;
LDG.E R21, [R10.64+0x58] ;
STG.E [R12.64+0x58], R21 ;
LDG.E R23, [R10.64+0x54] ;
STG.E [R12.64+0x5c], R23 ;
LDG.E R9, [R10.64+0x60] ;
STG.E [R12.64+0x60], R9 ;
LDG.E R15, [R10.64+0x5c] ;
STG.E [R12.64+0x64], R15 ;
LDG.E R17, [R10.64+0x68] ;
STG.E [R12.64+0x68], R17 ;
LDG.E R19, [R10.64+0x64] ;
STG.E [R12.64+0x6c], R19 ;
LDG.E R21, [R10.64+0x70] ;
STG.E [R12.64+0x70], R21 ;
LDG.E R23, [R10.64+0x6c] ;
STG.E [R12.64+0x74], R23 ;
LDG.E R9, [R10.64+0x78] ;
IADD3 R8, R8, -0x10, RZ ;
ISETP.GT.AND P2, PT, R8, 0xb, PT ;
STG.E [R12.64+0x78], R9 ;
LDG.E R15, [R10.64+0x74] ;
UIADD3 UR8, UP0, UR8, 0x80, URZ ;
UIADD3 UR10, UP1, UR10, 0x80, URZ ;
UIADD3 UR4, UR4, 0x20, URZ ;
UIADD3.X UR9, URZ, UR9, URZ, UP0, !UPT ;
UIADD3.X UR11, URZ, UR11, URZ, UP1, !UPT ;
STG.E [R12.64+0x7c], R15 ;
@P2 BRA 0x270 ;
IADD3 R9, R8, 0x1, RZ ;
ISETP.GT.AND P2, PT, R9, 0x4, PT ;
@!P2 BRA 0xa50 ;
IMAD.U32 R10, RZ, RZ, UR8 ;
IMAD.U32 R11, RZ, RZ, UR9 ;
IMAD.WIDE R10, R7, 0x4, R10 ;
LDG.E R9, [R10.64] ;
IMAD.U32 R12, RZ, RZ, UR10 ;
IMAD.U32 R13, RZ, RZ, UR11 ;
IMAD.WIDE R12, R6, 0x4, R12 ;
STG.E [R12.64], R9 ;
LDG.E R15, [R10.64+-0x4] ;
STG.E [R12.64+0x4], R15 ;
LDG.E R17, [R10.64+0x8] ;
STG.E [R12.64+0x8], R17 ;
LDG.E R19, [R10.64+0x4] ;
STG.E [R12.64+0xc], R19 ;
LDG.E R21, [R10.64+0x10] ;
STG.E [R12.64+0x10], R21 ;
LDG.E R23, [R10.64+0xc] ;
STG.E [R12.64+0x14], R23 ;
LDG.E R9, [R10.64+0x18] ;
STG.E [R12.64+0x18], R9 ;
LDG.E R15, [R10.64+0x14] ;
STG.E [R12.64+0x1c], R15 ;
LDG.E R17, [R10.64+0x20] ;
STG.E [R12.64+0x20], R17 ;
LDG.E R19, [R10.64+0x1c] ;
STG.E [R12.64+0x24], R19 ;
LDG.E R21, [R10.64+0x28] ;
STG.E [R12.64+0x28], R21 ;
LDG.E R23, [R10.64+0x24] ;
STG.E [R12.64+0x2c], R23 ;
LDG.E R9, [R10.64+0x30] ;
STG.E [R12.64+0x30], R9 ;
LDG.E R15, [R10.64+0x2c] ;
STG.E [R12.64+0x34], R15 ;
LDG.E R17, [R10.64+0x38] ;
STG.E [R12.64+0x38], R17 ;
LDG.E R19, [R10.64+0x34] ;
UIADD3 UR8, UP0, UR8, 0x40, URZ ;
PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ;
UIADD3 UR10, UP1, UR10, 0x40, URZ ;
IADD3 R8, R8, -0x8, RZ ;
UIADD3 UR4, UR4, 0x10, URZ ;
UIADD3.X UR9, URZ, UR9, URZ, UP0, !UPT ;
UIADD3.X UR11, URZ, UR11, URZ, UP1, !UPT ;
STG.E [R12.64+0x3c], R19 ;
ISETP.NE.OR P0, PT, R8, -0x1, P0 ;
@!P0 BRA 0xc50 ;
IMAD.U32 R10, RZ, RZ, UR8 ;
IMAD.U32 R11, RZ, RZ, UR9 ;
IMAD.WIDE R10, R7, 0x4, R10 ;
LDG.E R9, [R10.64] ;
IMAD.U32 R12, RZ, RZ, UR10 ;
IMAD.U32 R13, RZ, RZ, UR11 ;
IMAD.WIDE R12, R6, 0x4, R12 ;
STG.E [R12.64], R9 ;
LDG.E R15, [R10.64+-0x4] ;
STG.E [R12.64+0x4], R15 ;
LDG.E R17, [R10.64+0x8] ;
STG.E [R12.64+0x8], R17 ;
LDG.E R19, [R10.64+0x4] ;
STG.E [R12.64+0xc], R19 ;
LDG.E R21, [R10.64+0x10] ;
STG.E [R12.64+0x10], R21 ;
LDG.E R23, [R10.64+0xc] ;
STG.E [R12.64+0x14], R23 ;
LDG.E R9, [R10.64+0x18] ;
IADD3 R8, R8, -0x4, RZ ;
ISETP.NE.AND P0, PT, R8, -0x1, PT ;
STG.E [R12.64+0x18], R9 ;
LDG.E R15, [R10.64+0x14] ;
UIADD3 UR8, UP0, UR8, 0x20, URZ ;
UIADD3 UR10, UP1, UR10, 0x20, URZ ;
UIADD3 UR4, UR4, 0x8, URZ ;
UIADD3.X UR9, URZ, UR9, URZ, UP0, !UPT ;
UIADD3.X UR11, URZ, UR11, URZ, UP1, !UPT ;
STG.E [R12.64+0x1c], R15 ;
@P0 BRA 0xa70 ;
ISETP.NE.AND P0, PT, R3, RZ, PT ;
@!P0 BRA 0xdb0 ;
IADD3 R8, R6, UR4, RZ ;
IMAD.MOV.U32 R9, RZ, RZ, 0x4 ;
IMAD.WIDE R6, R8, R9, c[0x0][0x160] ;
LDG.E R11, [R6.64+0x4] ;
IMAD.WIDE R8, R8, R9, c[0x0][0x168] ;
ISETP.NE.AND P0, PT, R3, 0x1, PT ;
STG.E [R8.64], R11 ;
LDG.E R13, [R6.64] ;
STG.E [R8.64+0x4], R13 ;
@!P0 BRA 0xdb0 ;
LDG.E R11, [R6.64+0xc] ;
ISETP.NE.AND P0, PT, R3, 0x2, PT ;
STG.E [R8.64+0x8], R11 ;
LDG.E R13, [R6.64+0x8] ;
STG.E [R8.64+0xc], R13 ;
@!P0 BRA 0xdb0 ;
LDG.E R11, [R6.64+0x14] ;
STG.E [R8.64+0x10], R11 ;
LDG.E R13, [R6.64+0x10] ;
STG.E [R8.64+0x14], R13 ;
@!P1 BRA 0x150 ;
EXIT ;
BRA 0xdd0;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
```
|
```amdasm
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z15process_kernel1PfS_ii ; -- Begin function _Z15process_kernel1PfS_ii
.globl _Z15process_kernel1PfS_ii
.p2align 8
.type _Z15process_kernel1PfS_ii,@function
_Z15process_kernel1PfS_ii: ; @_Z15process_kernel1PfS_ii
; %bb.0:
s_clause 0x1
s_load_b32 s6, s[0:1], 0x24
s_load_b64 s[2:3], s[0:1], 0x10
v_bfe_u32 v3, v0, 10, 10
s_add_u32 s4, s0, 24
s_addc_u32 s5, s1, 0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s6, s6, 16
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s6, v[3:4]
s_mov_b32 s6, exec_lo
v_cmpx_gt_i32_e64 s2, v1
s_cbranch_execz .LBB0_7
; %bb.1:
s_load_b32 s4, s[4:5], 0xc
v_and_b32_e32 v0, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_cmp_gt_i32 s2, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, s14, s4, v[0:1]
s_cselect_b32 s5, -1, 0
s_mov_b32 s4, 0
v_cmp_gt_i32_e32 vcc_lo, s3, v2
s_and_b32 s5, vcc_lo, s5
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 exec_lo, exec_lo, s5
s_cbranch_execz .LBB0_7
; %bb.2: ; %.preheader.lr.ph
s_load_b128 s[8:11], s[0:1], 0x0
s_cmp_gt_i32 s3, 0
v_mov_b32_e32 v2, 0
s_cselect_b32 s0, -1, 0
s_waitcnt lgkmcnt(0)
s_add_u32 s1, s10, 4
s_addc_u32 s5, s11, 0
s_add_u32 s6, s8, 4
s_addc_u32 s7, s9, 0
.LBB0_3: ; %.preheader
; =>This Loop Header: Depth=1
; Child Loop BB0_5 Depth 2
s_and_not1_b32 vcc_lo, exec_lo, s0
s_cbranch_vccnz .LBB0_6
; %bb.4: ; %.lr.ph
; in Loop: Header=BB0_3 Depth=1
v_ashrrev_i32_e32 v3, 31, v2
s_mov_b32 s8, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[5:6], 2, v[2:3]
v_add_co_u32 v3, vcc_lo, s1, v5
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v6, vcc_lo
v_add_co_u32 v5, vcc_lo, s6, v5
v_add_co_ci_u32_e32 v6, vcc_lo, s7, v6, vcc_lo
.LBB0_5: ; Parent Loop BB0_3 Depth=1
; => This Inner Loop Header: Depth=2
global_load_b32 v0, v[5:6], off
s_add_i32 s8, s8, 2
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_ge_i32 s8, s3
s_waitcnt vmcnt(0)
global_store_b32 v[3:4], v0, off offset:-4
global_load_b32 v0, v[5:6], off offset:-4
v_add_co_u32 v5, vcc_lo, v5, 8
v_add_co_ci_u32_e32 v6, vcc_lo, 0, v6, vcc_lo
s_waitcnt vmcnt(0)
global_store_b32 v[3:4], v0, off
v_add_co_u32 v3, vcc_lo, v3, 8
v_add_co_ci_u32_e32 v4, vcc_lo, 0, v4, vcc_lo
s_cbranch_scc0 .LBB0_5
.LBB0_6: ; %._crit_edge
; in Loop: Header=BB0_3 Depth=1
v_add_nc_u32_e32 v2, v2, v1
s_add_i32 s4, s4, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s4, s2
s_cbranch_scc0 .LBB0_3
.LBB0_7: ; %.loopexit
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z15process_kernel1PfS_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z15process_kernel1PfS_ii, .Lfunc_end0-_Z15process_kernel1PfS_ii
; -- End function
.section .AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 352
; NumSgprs: 18
; NumVgprs: 7
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 7
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object ; @__hip_cuid_
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0 ; 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z15process_kernel1PfS_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z15process_kernel1PfS_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
```
| 4,369 | 3,333 |
263 |
Convert the following CUDA host assembly code to AMD host assembly:
```cudaasm
.file "tmpxft_0003ca70_00000000-6_week_4_2.cudafe1.cpp"
.text
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%.1f "
.LC1:
.string "\n"
.text
.globl _Z11print_arrayPfii
.type _Z11print_arrayPfii, @function
_Z11print_arrayPfii:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $40, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 16(%rsp)
movl %esi, 12(%rsp)
testl %esi, %esi
jle .L3
movl %edx, %r15d
movl $0, %r14d
movl $0, %r13d
movslq %edx, %rax
movq %rax, 24(%rsp)
leaq .LC0(%rip), %r12
jmp .L5
.L7:
movslq %r14d, %rax
movq 16(%rsp), %rcx
leaq (%rcx,%rax,4), %rbx
movq 24(%rsp), %rdx
addq %rdx, %rax
leaq (%rcx,%rax,4), %rbp
.L6:
pxor %xmm0, %xmm0
cvtss2sd (%rbx), %xmm0
movq %r12, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %rbp, %rbx
jne .L6
.L8:
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $1, %r13d
addl %r15d, %r14d
cmpl %r13d, 12(%rsp)
je .L3
.L5:
testl %r15d, %r15d
jg .L7
jmp .L8
.L3:
addq $40, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size _Z11print_arrayPfii, .-_Z11print_arrayPfii
.globl _Z39__device_stub__Z15process_kernel1PfS_iiPfS_ii
.type _Z39__device_stub__Z15process_kernel1PfS_iiPfS_ii, @function
_Z39__device_stub__Z15process_kernel1PfS_iiPfS_ii:
.LFB2083:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z15process_kernel1PfS_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z39__device_stub__Z15process_kernel1PfS_iiPfS_ii, .-_Z39__device_stub__Z15process_kernel1PfS_iiPfS_ii
.globl _Z15process_kernel1PfS_ii
.type _Z15process_kernel1PfS_ii, @function
_Z15process_kernel1PfS_ii:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z39__device_stub__Z15process_kernel1PfS_iiPfS_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z15process_kernel1PfS_ii, .-_Z15process_kernel1PfS_ii
.section .rodata.str1.1
.LC2:
.string "%d"
.LC3:
.string "%d %d"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC4:
.string "Failed to allocate host vectors!\n"
.section .rodata.str1.1
.LC5:
.string "%f"
.section .rodata.str1.8
.align 8
.LC6:
.string "Failed to allocate device vector d_input (error code %s)!\n"
.align 8
.LC7:
.string "Failed to allocate device vector d_output (error code %s)!\n"
.align 8
.LC8:
.string "Failed to copy vector h_input from host to device (error code %s)!\n"
.align 8
.LC9:
.string "Failed to launch process_kernel1 kernel (error code %s)!\n"
.align 8
.LC10:
.string "Failed to copy vector d_output from device to host (error code %s)!\n"
.align 8
.LC11:
.string "Failed to free device vector d_input (error code %s)!\n"
.align 8
.LC12:
.string "Failed to free device vector d_output (error code %s)!\n"
.align 8
.LC13:
.string "Failed to deinitialize the device! error=%s\n"
.text
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $88, %rsp
.cfi_def_cfa_offset 144
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
leaq 20(%rsp), %rsi
leaq .LC2(%rip), %rdi
call __isoc23_scanf@PLT
leaq 28(%rsp), %rdx
leaq 24(%rsp), %rsi
leaq .LC3(%rip), %rdi
movl $0, %eax
call __isoc23_scanf@PLT
movl 24(%rsp), %eax
imull 28(%rsp), %eax
movl %eax, 12(%rsp)
movslq %eax, %r13
salq $2, %r13
movq %r13, %rdi
call malloc@PLT
movq %rax, %r14
movq %r13, %rdi
call malloc@PLT
testq %r14, %r14
je .L20
movq %rax, %r15
testq %rax, %rax
je .L20
movq %r14, %rbp
movl $0, %ebx
leaq .LC5(%rip), %r12
cmpl $0, 12(%rsp)
jle .L22
.L23:
movq %rbp, %rsi
movq %r12, %rdi
movl $0, %eax
call __isoc23_scanf@PLT
addl $1, %ebx
addq $4, %rbp
movl 28(%rsp), %eax
imull 24(%rsp), %eax
cmpl %ebx, %eax
jg .L23
.L22:
movq $0, 32(%rsp)
leaq 32(%rsp), %rdi
movq %r13, %rsi
call cudaMalloc@PLT
testl %eax, %eax
jne .L37
movq $0, 40(%rsp)
leaq 40(%rsp), %rdi
movq %r13, %rsi
call cudaMalloc@PLT
testl %eax, %eax
jne .L38
movl $1, %ecx
movq %r13, %rdx
movq %r14, %rsi
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L39
movl 24(%rsp), %eax
imull 28(%rsp), %eax
leal 30(%rax), %edx
addl $15, %eax
cmovs %edx, %eax
sarl $4, %eax
movl $16, 60(%rsp)
movl $1, 64(%rsp)
movl %eax, 48(%rsp)
movl $1, 52(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 60(%rsp), %rdx
movl $1, %ecx
movq 48(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L40
.L27:
call cudaGetLastError@PLT
testl %eax, %eax
jne .L41
movl $2, %ecx
movq %r13, %rdx
movq 40(%rsp), %rsi
movq %r15, %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L42
movl 24(%rsp), %edx
movl 28(%rsp), %esi
movq %r15, %rdi
call _Z11print_arrayPfii
movq 32(%rsp), %rdi
call cudaFree@PLT
testl %eax, %eax
jne .L43
movq 40(%rsp), %rdi
call cudaFree@PLT
testl %eax, %eax
jne .L44
movq %r14, %rdi
call free@PLT
movq %r15, %rdi
call free@PLT
call cudaDeviceReset@PLT
testl %eax, %eax
jne .L45
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L46
movl $0, %eax
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L20:
.cfi_restore_state
leaq .LC4(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L37:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC6(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L38:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC7(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L39:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC8(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L40:
movl 24(%rsp), %ecx
movl 28(%rsp), %edx
movq 40(%rsp), %rsi
movq 32(%rsp), %rdi
call _Z39__device_stub__Z15process_kernel1PfS_iiPfS_ii
jmp .L27
.L41:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC9(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L42:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC10(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L43:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC11(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L44:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC12(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L45:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC13(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L46:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.1
.LC14:
.string "_Z15process_kernel1PfS_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC14(%rip), %rdx
movq %rdx, %rcx
leaq _Z15process_kernel1PfS_ii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
```
|
```amdasm
.text
.file "week_4_2.hip"
.globl _Z11print_arrayPfii # -- Begin function _Z11print_arrayPfii
.type _Z11print_arrayPfii,@function
_Z11print_arrayPfii: # @_Z11print_arrayPfii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $24, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rdi, 8(%rsp) # 8-byte Spill
testl %esi, %esi
jle .LBB0_6
# %bb.1: # %.preheader.lr.ph
movl %edx, %ebx
movl %esi, %eax
movq %rax, 16(%rsp) # 8-byte Spill
movl %edx, %r12d
xorl %r13d, %r13d
xorl %ebp, %ebp
.LBB0_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB0_4 Depth 2
testl %ebx, %ebx
jle .LBB0_5
# %bb.3: # %.lr.ph
# in Loop: Header=BB0_2 Depth=1
movl %r13d, %eax
movq 8(%rsp), %rcx # 8-byte Reload
leaq (%rcx,%rax,4), %r14
xorl %r15d, %r15d
.LBB0_4: # Parent Loop BB0_2 Depth=1
# => This Inner Loop Header: Depth=2
xorps %xmm0, %xmm0
cvtss2sd (%r14,%r15,4), %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
incq %r15
cmpq %r15, %r12
jne .LBB0_4
.LBB0_5: # %._crit_edge
# in Loop: Header=BB0_2 Depth=1
movl $10, %edi
callq putchar@PLT
incq %rbp
addl %ebx, %r13d
cmpq 16(%rsp), %rbp # 8-byte Folded Reload
jne .LBB0_2
.LBB0_6: # %._crit_edge13
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z11print_arrayPfii, .Lfunc_end0-_Z11print_arrayPfii
.cfi_endproc
# -- End function
.globl _Z30__device_stub__process_kernel1PfS_ii # -- Begin function _Z30__device_stub__process_kernel1PfS_ii
.type _Z30__device_stub__process_kernel1PfS_ii,@function
_Z30__device_stub__process_kernel1PfS_ii: # @_Z30__device_stub__process_kernel1PfS_ii
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $112, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 40(%rsp), %rax
movq %rdi, (%rax)
leaq 32(%rsp), %rdi
movq %rsi, (%rdi)
leaq 12(%rsp), %rsi
movl %edx, (%rsi)
leaq 8(%rsp), %rdx
movl %ecx, (%rdx)
leaq 80(%rsp), %rbx
movq %rax, (%rbx)
movq %rdi, 8(%rbx)
movq %rsi, 16(%rbx)
movq %rdx, 24(%rbx)
leaq 64(%rsp), %r14
leaq 48(%rsp), %r15
leaq 24(%rsp), %r12
leaq 16(%rsp), %r13
movq %r14, %rdi
movq %r15, %rsi
movq %r12, %rdx
movq %r13, %rcx
callq __hipPopCallConfiguration
movq (%r14), %rsi
movl 8(%r14), %edx
movq (%r15), %rcx
movl 8(%r15), %r8d
movl $_Z15process_kernel1PfS_ii, %edi
movq %rbx, %r9
pushq (%r13)
.cfi_adjust_cfa_offset 8
pushq (%r12)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $128, %rsp
.cfi_adjust_cfa_offset -128
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z30__device_stub__process_kernel1PfS_ii, .Lfunc_end1-_Z30__device_stub__process_kernel1PfS_ii
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $32, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 28(%rsp), %rsi
movl $.L.str.2, %edi
xorl %eax, %eax
callq __isoc23_scanf
leaq 4(%rsp), %rbx
movq %rsp, %r14
movl $.L.str.3, %edi
movq %rbx, %rsi
movq %r14, %rdx
xorl %eax, %eax
callq __isoc23_scanf
movslq (%rbx), %rax
movslq (%r14), %r12
imulq %rax, %r12
leaq (,%r12,4), %r15
movq %r15, %rdi
callq malloc
movq %rax, %rbx
movq %r15, %rdi
callq malloc
testq %rbx, %rbx
je .LBB2_16
# %bb.1:
movq %rax, %r14
testq %rax, %rax
je .LBB2_16
# %bb.2: # %.preheader
testl %r12d, %r12d
jle .LBB2_5
# %bb.3: # %.lr.ph.preheader
movq %rbx, %r12
xorl %r13d, %r13d
.LBB2_4: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl $.L.str.5, %edi
movq %r12, %rsi
xorl %eax, %eax
callq __isoc23_scanf
incq %r13
movslq (%rsp), %rax
movslq 4(%rsp), %rcx
imulq %rax, %rcx
addq $4, %r12
cmpq %rcx, %r13
jl .LBB2_4
.LBB2_5: # %._crit_edge
leaq 16(%rsp), %rdi
movq $0, (%rdi)
movq %r15, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB2_17
# %bb.6:
leaq 8(%rsp), %rdi
movq $0, (%rdi)
movq %r15, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB2_18
# %bb.7:
movq 16(%rsp), %rdi
movq %rbx, %rsi
movq %r15, %rdx
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB2_19
# %bb.8:
movl (%rsp), %edi
imull 4(%rsp), %edi
leal 15(%rdi), %eax
addl $30, %edi
testl %eax, %eax
cmovnsl %eax, %edi
sarl $4, %edi
btsq $32, %rdi
movabsq $4294967296, %rdx # imm = 0x100000000
orq $16, %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_10
# %bb.9:
movq 16(%rsp), %rdi
movq 8(%rsp), %rsi
movl (%rsp), %edx
movl 4(%rsp), %ecx
callq _Z30__device_stub__process_kernel1PfS_ii
.LBB2_10:
callq hipGetLastError
testl %eax, %eax
jne .LBB2_20
# %bb.11:
movq 8(%rsp), %rsi
movq %r14, %rdi
movq %r15, %rdx
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB2_21
# %bb.12:
movl (%rsp), %esi
movl 4(%rsp), %edx
movq %r14, %rdi
callq _Z11print_arrayPfii
movq 16(%rsp), %rdi
callq hipFree
testl %eax, %eax
jne .LBB2_22
# %bb.13:
movq 8(%rsp), %rdi
callq hipFree
testl %eax, %eax
jne .LBB2_23
# %bb.14:
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
callq hipDeviceReset
testl %eax, %eax
jne .LBB2_24
# %bb.15:
xorl %eax, %eax
addq $32, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB2_16:
.cfi_def_cfa_offset 80
movq stderr(%rip), %rcx
movl $.L.str.4, %edi
movl $33, %esi
movl $1, %edx
callq fwrite@PLT
jmp .LBB2_26
.LBB2_17:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.6, %esi
jmp .LBB2_25
.LBB2_18:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.7, %esi
jmp .LBB2_25
.LBB2_19:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.8, %esi
jmp .LBB2_25
.LBB2_20:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.9, %esi
jmp .LBB2_25
.LBB2_21:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.10, %esi
jmp .LBB2_25
.LBB2_22:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.11, %esi
jmp .LBB2_25
.LBB2_23:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.12, %esi
jmp .LBB2_25
.LBB2_24:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.13, %esi
.LBB2_25:
movq %rbx, %rdi
movq %rax, %rdx
xorl %eax, %eax
callq fprintf
.LBB2_26:
movl $1, %edi
callq exit
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, %rdi
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15process_kernel1PfS_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%.1f "
.size .L.str, 6
.type _Z15process_kernel1PfS_ii,@object # @_Z15process_kernel1PfS_ii
.section .rodata,"a",@progbits
.globl _Z15process_kernel1PfS_ii
.p2align 3, 0x0
_Z15process_kernel1PfS_ii:
.quad _Z30__device_stub__process_kernel1PfS_ii
.size _Z15process_kernel1PfS_ii, 8
.type .L.str.2,@object # @.str.2
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.2:
.asciz "%d"
.size .L.str.2, 3
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "%d %d"
.size .L.str.3, 6
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Failed to allocate host vectors!\n"
.size .L.str.4, 34
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "%f"
.size .L.str.5, 3
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "Failed to allocate device vector d_input (error code %s)!\n"
.size .L.str.6, 59
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "Failed to allocate device vector d_output (error code %s)!\n"
.size .L.str.7, 60
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "Failed to copy vector h_input from host to device (error code %s)!\n"
.size .L.str.8, 68
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "Failed to launch process_kernel1 kernel (error code %s)!\n"
.size .L.str.9, 58
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "Failed to copy vector d_output from device to host (error code %s)!\n"
.size .L.str.10, 69
.type .L.str.11,@object # @.str.11
.L.str.11:
.asciz "Failed to free device vector d_input (error code %s)!\n"
.size .L.str.11, 55
.type .L.str.12,@object # @.str.12
.L.str.12:
.asciz "Failed to free device vector d_output (error code %s)!\n"
.size .L.str.12, 56
.type .L.str.13,@object # @.str.13
.L.str.13:
.asciz "Failed to deinitialize the device! error=%s\n"
.size .L.str.13, 45
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z15process_kernel1PfS_ii"
.size .L__unnamed_1, 26
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z30__device_stub__process_kernel1PfS_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z15process_kernel1PfS_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
```
| 5,682 | 6,010 |
264 |
Convert the following CUDA device assembly code to AMD device assembly:
```cudaasm
code for sm_80
Function : _Z30vector_elemwise_div_f32_kernelPKfiPf
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ;
S2R R2, SR_TID.X ;
S2R R3, SR_CTAID.X ;
IMAD R2, R3, c[0x0][0x0], R2 ;
ISETP.GE.AND P0, PT, R2, c[0x0][0x168], PT ;
@P0 EXIT ;
IMAD.MOV.U32 R3, RZ, RZ, 0x4 ;
ULDC.64 UR4, c[0x0][0x118] ;
IMAD.WIDE R4, R2, R3, c[0x0][0x160] ;
LDG.E R4, [R4.64] ;
IMAD.WIDE R2, R2, R3, c[0x0][0x170] ;
LDG.E R7, [R2.64] ;
BSSY B0, 0x180 ;
MUFU.RCP R9, R4 ;
FCHK P0, R7, R4 ;
FFMA R0, -R4, R9, 1 ;
FFMA R0, R9, R0, R9 ;
FFMA R9, R7, R0, RZ ;
FFMA R6, -R4, R9, R7 ;
FFMA R9, R0, R6, R9 ;
@!P0 BRA 0x170 ;
MOV R0, 0x170 ;
CALL.REL.NOINC 0x1a0 ;
BSYNC B0 ;
STG.E [R2.64], R9 ;
EXIT ;
SHF.R.U32.HI R6, RZ, 0x17, R4.reuse ;
BSSY B1, 0x800 ;
SHF.R.U32.HI R5, RZ, 0x17, R7.reuse ;
IMAD.MOV.U32 R8, RZ, RZ, R7 ;
LOP3.LUT R6, R6, 0xff, RZ, 0xc0, !PT ;
IMAD.MOV.U32 R9, RZ, RZ, R4 ;
LOP3.LUT R5, R5, 0xff, RZ, 0xc0, !PT ;
IADD3 R12, R6, -0x1, RZ ;
IADD3 R11, R5, -0x1, RZ ;
ISETP.GT.U32.AND P0, PT, R12, 0xfd, PT ;
ISETP.GT.U32.OR P0, PT, R11, 0xfd, P0 ;
@!P0 IMAD.MOV.U32 R10, RZ, RZ, RZ ;
@!P0 BRA 0x3e0 ;
FSETP.GTU.FTZ.AND P0, PT, |R7|, +INF , PT ;
FSETP.GTU.FTZ.AND P1, PT, |R4|, +INF , PT ;
PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ;
@P0 BRA 0x7e0 ;
LOP3.LUT P0, RZ, R9, 0x7fffffff, R8, 0xc8, !PT ;
@!P0 BRA 0x7c0 ;
FSETP.NEU.FTZ.AND P2, PT, |R7|.reuse, +INF , PT ;
FSETP.NEU.FTZ.AND P1, PT, |R4|, +INF , PT ;
FSETP.NEU.FTZ.AND P0, PT, |R7|, +INF , PT ;
@!P1 BRA !P2, 0x7c0 ;
LOP3.LUT P2, RZ, R8, 0x7fffffff, RZ, 0xc0, !PT ;
PLOP3.LUT P1, PT, P1, P2, PT, 0x2a, 0x0 ;
@P1 BRA 0x7a0 ;
LOP3.LUT P1, RZ, R9, 0x7fffffff, RZ, 0xc0, !PT ;
PLOP3.LUT P0, PT, P0, P1, PT, 0x2a, 0x0 ;
@P0 BRA 0x770 ;
ISETP.GE.AND P0, PT, R11, RZ, PT ;
ISETP.GE.AND P1, PT, R12, RZ, PT ;
@P0 IMAD.MOV.U32 R10, RZ, RZ, RZ ;
@!P0 IMAD.MOV.U32 R10, RZ, RZ, -0x40 ;
@!P0 FFMA R8, R7, 1.84467440737095516160e+19, RZ ;
@!P1 FFMA R9, R4, 1.84467440737095516160e+19, RZ ;
@!P1 IADD3 R10, R10, 0x40, RZ ;
LEA R4, R6, 0xc0800000, 0x17 ;
BSSY B2, 0x760 ;
IADD3 R5, R5, -0x7f, RZ ;
IMAD.IADD R9, R9, 0x1, -R4 ;
IMAD R8, R5, -0x800000, R8 ;
MUFU.RCP R4, R9 ;
FADD.FTZ R7, -R9, -RZ ;
FFMA R11, R4, R7, 1 ;
FFMA R13, R4, R11, R4 ;
FFMA R4, R8, R13, RZ ;
FFMA R11, R7, R4, R8 ;
FFMA R12, R13, R11, R4 ;
FFMA R8, R7, R12, R8 ;
IADD3 R7, R5, 0x7f, -R6 ;
FFMA R4, R13, R8, R12 ;
IMAD.IADD R7, R7, 0x1, R10 ;
SHF.R.U32.HI R5, RZ, 0x17, R4 ;
LOP3.LUT R5, R5, 0xff, RZ, 0xc0, !PT ;
IMAD.IADD R9, R5, 0x1, R7 ;
IADD3 R5, R9, -0x1, RZ ;
ISETP.GE.U32.AND P0, PT, R5, 0xfe, PT ;
@!P0 BRA 0x740 ;
ISETP.GT.AND P0, PT, R9, 0xfe, PT ;
@P0 BRA 0x710 ;
ISETP.GE.AND P0, PT, R9, 0x1, PT ;
@P0 BRA 0x750 ;
ISETP.GE.AND P0, PT, R9, -0x18, PT ;
LOP3.LUT R4, R4, 0x80000000, RZ, 0xc0, !PT ;
@!P0 BRA 0x750 ;
FFMA.RZ R5, R13, R8.reuse, R12.reuse ;
ISETP.NE.AND P2, PT, R9, RZ, PT ;
FFMA.RM R6, R13, R8.reuse, R12.reuse ;
ISETP.NE.AND P1, PT, R9, RZ, PT ;
LOP3.LUT R7, R5, 0x7fffff, RZ, 0xc0, !PT ;
FFMA.RP R5, R13, R8, R12 ;
IADD3 R8, R9, 0x20, RZ ;
IMAD.MOV R9, RZ, RZ, -R9 ;
LOP3.LUT R7, R7, 0x800000, RZ, 0xfc, !PT ;
FSETP.NEU.FTZ.AND P0, PT, R5, R6, PT ;
SHF.L.U32 R8, R7, R8, RZ ;
SEL R6, R9, RZ, P2 ;
ISETP.NE.AND P1, PT, R8, RZ, P1 ;
SHF.R.U32.HI R6, RZ, R6, R7 ;
PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ;
SHF.R.U32.HI R8, RZ, 0x1, R6 ;
SEL R5, RZ, 0x1, !P0 ;
LOP3.LUT R5, R5, 0x1, R8, 0xf8, !PT ;
LOP3.LUT R5, R5, R6, RZ, 0xc0, !PT ;
IMAD.IADD R5, R8, 0x1, R5 ;
LOP3.LUT R4, R5, R4, RZ, 0xfc, !PT ;
BRA 0x750 ;
LOP3.LUT R4, R4, 0x80000000, RZ, 0xc0, !PT ;
LOP3.LUT R4, R4, 0x7f800000, RZ, 0xfc, !PT ;
BRA 0x750 ;
IMAD R4, R7, 0x800000, R4 ;
BSYNC B2 ;
BRA 0x7f0 ;
LOP3.LUT R4, R9, 0x80000000, R8, 0x48, !PT ;
LOP3.LUT R4, R4, 0x7f800000, RZ, 0xfc, !PT ;
BRA 0x7f0 ;
LOP3.LUT R4, R9, 0x80000000, R8, 0x48, !PT ;
BRA 0x7f0 ;
MUFU.RSQ R4, -QNAN ;
BRA 0x7f0 ;
FADD.FTZ R4, R7, R4 ;
BSYNC B1 ;
IMAD.MOV.U32 R9, RZ, RZ, R4 ;
IMAD.MOV.U32 R4, RZ, RZ, R0 ;
IMAD.MOV.U32 R5, RZ, RZ, 0x0 ;
RET.REL.NODEC R4 0x0 ;
BRA 0x840;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
Function : _Z31vector_elemwise_mult_f32_kernelPKfiPf
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
MOV R1, c[0x0][0x28] ;
S2R R4, SR_TID.X ;
S2R R3, SR_CTAID.X ;
IMAD R4, R3, c[0x0][0x0], R4 ;
ISETP.GE.AND P0, PT, R4, c[0x0][0x168], PT ;
@P0 EXIT ;
HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ;
ULDC.64 UR4, c[0x0][0x118] ;
IMAD.WIDE R2, R4, R5, c[0x0][0x160] ;
IMAD.WIDE R4, R4, R5, c[0x0][0x170] ;
LDG.E R3, [R2.64] ;
LDG.E R0, [R4.64] ;
FMUL R7, R0, R3 ;
STG.E [R4.64], R7 ;
EXIT ;
BRA 0xf0;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
Function : _Z28vector_avg_online_f32_kernelPKfifPf
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
MOV R1, c[0x0][0x28] ;
S2R R2, SR_TID.X ;
S2R R3, SR_CTAID.X ;
IMAD R2, R3, c[0x0][0x0], R2 ;
ISETP.GE.AND P0, PT, R2, c[0x0][0x168], PT ;
@P0 EXIT ;
HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ;
ULDC.64 UR4, c[0x0][0x118] ;
IMAD.WIDE R4, R2, R3, c[0x0][0x160] ;
IMAD.WIDE R2, R2, R3, c[0x0][0x170] ;
LDG.E R4, [R4.64] ;
LDG.E R7, [R2.64] ;
FADD R0, R4, -R7 ;
FFMA R7, R0, c[0x0][0x16c], R7 ;
STG.E [R2.64], R7 ;
EXIT ;
BRA 0x100;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
Function : _Z21vector_add_f32_kernelPKfiffPf
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
MOV R1, c[0x0][0x28] ;
S2R R2, SR_TID.X ;
S2R R3, SR_CTAID.X ;
IMAD R2, R3, c[0x0][0x0], R2 ;
ISETP.GE.AND P0, PT, R2, c[0x0][0x168], PT ;
@P0 EXIT ;
HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ;
ULDC.64 UR4, c[0x0][0x118] ;
IMAD.WIDE R4, R2, R3, c[0x0][0x178] ;
IMAD.WIDE R2, R2, R3, c[0x0][0x160] ;
LDG.E R0, [R4.64] ;
LDG.E R2, [R2.64] ;
FMUL R7, R0, c[0x0][0x170] ;
FFMA R7, R2, c[0x0][0x16c], R7 ;
STG.E [R4.64], R7 ;
EXIT ;
BRA 0x100;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
Function : _Z21vector_set_f32_kernelPKfifPf
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
MOV R1, c[0x0][0x28] ;
S2R R4, SR_TID.X ;
S2R R3, SR_CTAID.X ;
IMAD R4, R3, c[0x0][0x0], R4 ;
ISETP.GE.AND P0, PT, R4, c[0x0][0x168], PT ;
@P0 EXIT ;
HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ;
ULDC.64 UR4, c[0x0][0x118] ;
IMAD.WIDE R2, R4, R5, c[0x0][0x160] ;
LDG.E R2, [R2.64] ;
IMAD.WIDE R4, R4, R5, c[0x0][0x170] ;
FMUL R7, R2, c[0x0][0x16c] ;
STG.E [R4.64], R7 ;
EXIT ;
BRA 0xe0;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
Function : _Z21vector_exp_f32_kernelPfi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
MOV R1, c[0x0][0x28] ;
S2R R2, SR_TID.X ;
S2R R3, SR_CTAID.X ;
IMAD R2, R3, c[0x0][0x0], R2 ;
ISETP.GE.AND P0, PT, R2, c[0x0][0x168], PT ;
@P0 EXIT ;
HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ;
ULDC.64 UR4, c[0x0][0x118] ;
IMAD.WIDE R2, R2, R3, c[0x0][0x160] ;
LDG.E R0, [R2.64] ;
HFMA2.MMA R5, -RZ, RZ, 0.96630859375, -0.0022525787353515625 ;
MOV R7, 0x437c0000 ;
FFMA.SAT R4, R0, R5, 0.5 ;
FFMA.RM R4, R4, R7, 12582913 ;
FADD R5, R4.reuse, -12583039 ;
SHF.L.U32 R4, R4, 0x17, RZ ;
FFMA R5, R0, 1.4426950216293334961, -R5 ;
FFMA R5, R0, 1.925963033500011079e-08, R5 ;
MUFU.EX2 R5, R5 ;
FMUL R7, R4, R5 ;
STG.E [R2.64], R7 ;
EXIT ;
BRA 0x160;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
Function : _Z23vector_scale_f32_kernelPfif
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
MOV R1, c[0x0][0x28] ;
S2R R2, SR_TID.X ;
S2R R3, SR_CTAID.X ;
IMAD R2, R3, c[0x0][0x0], R2 ;
ISETP.GE.AND P0, PT, R2, c[0x0][0x168], PT ;
@P0 EXIT ;
HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ;
ULDC.64 UR4, c[0x0][0x118] ;
IMAD.WIDE R2, R2, R3, c[0x0][0x160] ;
LDG.E R0, [R2.64] ;
FMUL R5, R0, c[0x0][0x16c] ;
STG.E [R2.64], R5 ;
EXIT ;
BRA 0xd0;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
```
|
```amdasm
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z23vector_scale_f32_kernelPfif ; -- Begin function _Z23vector_scale_f32_kernelPfif
.globl _Z23vector_scale_f32_kernelPfif
.p2align 8
.type _Z23vector_scale_f32_kernelPfif,@function
_Z23vector_scale_f32_kernelPfif: ; @_Z23vector_scale_f32_kernelPfif
; %bb.0:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x1c
s_load_b64 s[2:3], s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
v_cmp_gt_i32_e32 vcc_lo, s2, v1
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_2
; %bb.1:
s_load_b64 s[0:1], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_load_b32 v2, v[0:1], off
s_waitcnt vmcnt(0)
v_mul_f32_e32 v2, s3, v2
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z23vector_scale_f32_kernelPfif
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z23vector_scale_f32_kernelPfif, .Lfunc_end0-_Z23vector_scale_f32_kernelPfif
; -- End function
.section .AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 136
; NumSgprs: 18
; NumVgprs: 3
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 3
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
.text
.protected _Z21vector_exp_f32_kernelPfi ; -- Begin function _Z21vector_exp_f32_kernelPfi
.globl _Z21vector_exp_f32_kernelPfi
.p2align 8
.type _Z21vector_exp_f32_kernelPfi,@function
_Z21vector_exp_f32_kernelPfi: ; @_Z21vector_exp_f32_kernelPfi
; %bb.0:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x1c
s_load_b32 s3, s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB1_2
; %bb.1:
s_load_b64 s[0:1], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_load_b32 v2, v[0:1], off
s_waitcnt vmcnt(0)
v_mul_f32_e32 v3, 0x3fb8aa3b, v2
v_cmp_ngt_f32_e32 vcc_lo, 0xc2ce8ed0, v2
v_fma_f32 v4, 0x3fb8aa3b, v2, -v3
v_rndne_f32_e32 v5, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_fmamk_f32 v4, v2, 0x32a5705f, v4 :: v_dual_sub_f32 v3, v3, v5
v_add_f32_e32 v3, v3, v4
v_cvt_i32_f32_e32 v4, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_exp_f32_e32 v3, v3
s_waitcnt_depctr 0xfff
v_ldexp_f32 v3, v3, v4
v_cndmask_b32_e32 v3, 0, v3, vcc_lo
v_cmp_nlt_f32_e32 vcc_lo, 0x42b17218, v2
s_delay_alu instid0(VALU_DEP_2)
v_cndmask_b32_e32 v2, 0x7f800000, v3, vcc_lo
global_store_b32 v[0:1], v2, off
.LBB1_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z21vector_exp_f32_kernelPfi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z21vector_exp_f32_kernelPfi, .Lfunc_end1-_Z21vector_exp_f32_kernelPfi
; -- End function
.section .AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 236
; NumSgprs: 18
; NumVgprs: 6
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 6
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
.text
.protected _Z21vector_set_f32_kernelPKfifPf ; -- Begin function _Z21vector_set_f32_kernelPKfifPf
.globl _Z21vector_set_f32_kernelPKfifPf
.p2align 8
.type _Z21vector_set_f32_kernelPKfifPf,@function
_Z21vector_set_f32_kernelPKfifPf: ; @_Z21vector_set_f32_kernelPKfifPf
; %bb.0:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x24
s_load_b64 s[2:3], s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
v_cmp_gt_i32_e32 vcc_lo, s2, v1
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB2_2
; %bb.1:
s_load_b64 s[4:5], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_load_b32 v2, v[2:3], off
s_waitcnt vmcnt(0)
v_mul_f32_e32 v2, s3, v2
global_store_b32 v[0:1], v2, off
.LBB2_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z21vector_set_f32_kernelPKfifPf
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end2:
.size _Z21vector_set_f32_kernelPKfifPf, .Lfunc_end2-_Z21vector_set_f32_kernelPKfifPf
; -- End function
.section .AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 156
; NumSgprs: 18
; NumVgprs: 4
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 4
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
.text
.protected _Z21vector_add_f32_kernelPKfiffPf ; -- Begin function _Z21vector_add_f32_kernelPKfiffPf
.globl _Z21vector_add_f32_kernelPKfiffPf
.p2align 8
.type _Z21vector_add_f32_kernelPKfiffPf,@function
_Z21vector_add_f32_kernelPKfiffPf: ; @_Z21vector_add_f32_kernelPKfiffPf
; %bb.0:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b128 s[4:7], s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s4, v1
s_cbranch_execz .LBB3_2
; %bb.1:
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x18
s_load_b64 s[0:1], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_load_b32 v4, v[2:3], off
global_load_b32 v0, v[0:1], off
s_waitcnt vmcnt(1)
v_mul_f32_e32 v1, s6, v4
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_fmac_f32_e32 v1, s5, v0
global_store_b32 v[2:3], v1, off
.LBB3_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z21vector_add_f32_kernelPKfiffPf
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end3:
.size _Z21vector_add_f32_kernelPKfiffPf, .Lfunc_end3-_Z21vector_add_f32_kernelPKfiffPf
; -- End function
.section .AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 184
; NumSgprs: 18
; NumVgprs: 5
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 5
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
.text
.protected _Z28vector_avg_online_f32_kernelPKfifPf ; -- Begin function _Z28vector_avg_online_f32_kernelPKfifPf
.globl _Z28vector_avg_online_f32_kernelPKfifPf
.p2align 8
.type _Z28vector_avg_online_f32_kernelPKfifPf,@function
_Z28vector_avg_online_f32_kernelPKfifPf: ; @_Z28vector_avg_online_f32_kernelPKfifPf
; %bb.0:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x24
s_load_b64 s[2:3], s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
v_cmp_gt_i32_e32 vcc_lo, s2, v1
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB4_2
; %bb.1:
s_clause 0x1
s_load_b64 s[4:5], s[0:1], 0x10
s_load_b64 s[0:1], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_load_b32 v4, v[2:3], off
global_load_b32 v0, v[0:1], off
s_waitcnt vmcnt(0)
v_sub_f32_e32 v0, v0, v4
s_delay_alu instid0(VALU_DEP_1)
v_fmac_f32_e32 v4, s3, v0
global_store_b32 v[2:3], v4, off
.LBB4_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z28vector_avg_online_f32_kernelPKfifPf
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end4:
.size _Z28vector_avg_online_f32_kernelPKfifPf, .Lfunc_end4-_Z28vector_avg_online_f32_kernelPKfifPf
; -- End function
.section .AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 176
; NumSgprs: 18
; NumVgprs: 5
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 5
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
.text
.protected _Z31vector_elemwise_mult_f32_kernelPKfiPf ; -- Begin function _Z31vector_elemwise_mult_f32_kernelPKfiPf
.globl _Z31vector_elemwise_mult_f32_kernelPKfiPf
.p2align 8
.type _Z31vector_elemwise_mult_f32_kernelPKfiPf,@function
_Z31vector_elemwise_mult_f32_kernelPKfiPf: ; @_Z31vector_elemwise_mult_f32_kernelPKfiPf
; %bb.0:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s3, s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB5_2
; %bb.1:
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[0:1], off
s_waitcnt vmcnt(0)
v_mul_f32_e32 v2, v2, v3
global_store_b32 v[0:1], v2, off
.LBB5_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z31vector_elemwise_mult_f32_kernelPKfiPf
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end5:
.size _Z31vector_elemwise_mult_f32_kernelPKfiPf, .Lfunc_end5-_Z31vector_elemwise_mult_f32_kernelPKfiPf
; -- End function
.section .AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 172
; NumSgprs: 18
; NumVgprs: 4
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 4
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
.text
.protected _Z30vector_elemwise_div_f32_kernelPKfiPf ; -- Begin function _Z30vector_elemwise_div_f32_kernelPKfiPf
.globl _Z30vector_elemwise_div_f32_kernelPKfiPf
.p2align 8
.type _Z30vector_elemwise_div_f32_kernelPKfiPf,@function
_Z30vector_elemwise_div_f32_kernelPKfiPf: ; @_Z30vector_elemwise_div_f32_kernelPKfiPf
; %bb.0:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s3, s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB6_2
; %bb.1:
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x10
s_load_b64 s[0:1], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_load_b32 v4, v[2:3], off
global_load_b32 v0, v[0:1], off
s_waitcnt vmcnt(0)
v_div_scale_f32 v1, null, v0, v0, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f32_e32 v5, v1
s_waitcnt_depctr 0xfff
v_fma_f32 v6, -v1, v5, 1.0
v_fmac_f32_e32 v5, v6, v5
v_div_scale_f32 v6, vcc_lo, v4, v0, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v7, v6, v5
v_fma_f32 v8, -v1, v7, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v7, v8, v5
v_fma_f32 v1, -v1, v7, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fmas_f32 v1, v1, v5, v7
v_div_fixup_f32 v0, v1, v0, v4
global_store_b32 v[2:3], v0, off
.LBB6_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z30vector_elemwise_div_f32_kernelPKfiPf
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end6:
.size _Z30vector_elemwise_div_f32_kernelPKfiPf, .Lfunc_end6-_Z30vector_elemwise_div_f32_kernelPKfiPf
; -- End function
.section .AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 260
; NumSgprs: 18
; NumVgprs: 9
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 9
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object ; @__hip_cuid_
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0 ; 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z23vector_scale_f32_kernelPfif
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z23vector_scale_f32_kernelPfif.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z21vector_exp_f32_kernelPfi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z21vector_exp_f32_kernelPfi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z21vector_set_f32_kernelPKfifPf
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z21vector_set_f32_kernelPKfifPf.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z21vector_add_f32_kernelPKfiffPf
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z21vector_add_f32_kernelPKfiffPf.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z28vector_avg_online_f32_kernelPKfifPf
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z28vector_avg_online_f32_kernelPKfifPf.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z31vector_elemwise_mult_f32_kernelPKfiPf
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z31vector_elemwise_mult_f32_kernelPKfiPf.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z30vector_elemwise_div_f32_kernelPKfiPf
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z30vector_elemwise_div_f32_kernelPKfiPf.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
```
| 4,925 | 16,726 |
265 |
Convert the following CUDA host assembly code to AMD host assembly:
```cudaasm
.file "tmpxft_000479ed_00000000-6_vector_kernels.cudafe1.cpp"
.text
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2036:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2036:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z45__device_stub__Z23vector_scale_f32_kernelPfifPfif
.type _Z45__device_stub__Z23vector_scale_f32_kernelPfifPfif, @function
_Z45__device_stub__Z23vector_scale_f32_kernelPfifPfif:
.LFB2058:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movss %xmm0, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rax
movq %rax, 96(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z23vector_scale_f32_kernelPfif(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size _Z45__device_stub__Z23vector_scale_f32_kernelPfifPfif, .-_Z45__device_stub__Z23vector_scale_f32_kernelPfifPfif
.globl _Z23vector_scale_f32_kernelPfif
.type _Z23vector_scale_f32_kernelPfif, @function
_Z23vector_scale_f32_kernelPfif:
.LFB2059:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z45__device_stub__Z23vector_scale_f32_kernelPfifPfif
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2059:
.size _Z23vector_scale_f32_kernelPfif, .-_Z23vector_scale_f32_kernelPfif
.globl array_cuda_vector_scale_f32
.type array_cuda_vector_scale_f32, @function
array_cuda_vector_scale_f32:
.LFB2027:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $56, %rsp
.cfi_def_cfa_offset 80
movq %rdi, %rbp
movl %esi, %ebx
movss %xmm0, 12(%rsp)
movq %rdx, %r9
movl $1024, 36(%rsp)
movl $1, 40(%rsp)
leal 2046(%rsi), %eax
movl %esi, %edx
addl $1023, %edx
cmovns %edx, %eax
sarl $10, %eax
movl %eax, 24(%rsp)
movl $1, 28(%rsp)
movl $0, %r8d
movq 36(%rsp), %rdx
movl $1, %ecx
movq 24(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L14
.L11:
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
movss 12(%rsp), %xmm0
movl %ebx, %esi
movq %rbp, %rdi
call _Z45__device_stub__Z23vector_scale_f32_kernelPfifPfif
jmp .L11
.cfi_endproc
.LFE2027:
.size array_cuda_vector_scale_f32, .-array_cuda_vector_scale_f32
.globl _Z42__device_stub__Z21vector_exp_f32_kernelPfiPfi
.type _Z42__device_stub__Z21vector_exp_f32_kernelPfiPfi, @function
_Z42__device_stub__Z21vector_exp_f32_kernelPfiPfi:
.LFB2060:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L19
.L15:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L20
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z21vector_exp_f32_kernelPfi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L15
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2060:
.size _Z42__device_stub__Z21vector_exp_f32_kernelPfiPfi, .-_Z42__device_stub__Z21vector_exp_f32_kernelPfiPfi
.globl _Z21vector_exp_f32_kernelPfi
.type _Z21vector_exp_f32_kernelPfi, @function
_Z21vector_exp_f32_kernelPfi:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z42__device_stub__Z21vector_exp_f32_kernelPfiPfi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _Z21vector_exp_f32_kernelPfi, .-_Z21vector_exp_f32_kernelPfi
.globl array_cuda_vector_exp_f32
.type array_cuda_vector_exp_f32, @function
array_cuda_vector_exp_f32:
.LFB2028:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $40, %rsp
.cfi_def_cfa_offset 64
movq %rdi, %rbp
movl %esi, %ebx
movq %rdx, %r9
movl $1024, 20(%rsp)
movl $1, 24(%rsp)
leal 2046(%rsi), %eax
movl %esi, %edx
addl $1023, %edx
cmovns %edx, %eax
sarl $10, %eax
movl %eax, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L26
.L23:
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L26:
.cfi_restore_state
movl %ebx, %esi
movq %rbp, %rdi
call _Z42__device_stub__Z21vector_exp_f32_kernelPfiPfi
jmp .L23
.cfi_endproc
.LFE2028:
.size array_cuda_vector_exp_f32, .-array_cuda_vector_exp_f32
.globl _Z46__device_stub__Z21vector_set_f32_kernelPKfifPfPKfifPf
.type _Z46__device_stub__Z21vector_set_f32_kernelPKfifPfPKfifPf, @function
_Z46__device_stub__Z21vector_set_f32_kernelPKfifPfPKfifPf:
.LFB2062:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movl %esi, 20(%rsp)
movss %xmm0, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L31
.L27:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L32
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L31:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z21vector_set_f32_kernelPKfifPf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L27
.L32:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2062:
.size _Z46__device_stub__Z21vector_set_f32_kernelPKfifPfPKfifPf, .-_Z46__device_stub__Z21vector_set_f32_kernelPKfifPfPKfifPf
.globl _Z21vector_set_f32_kernelPKfifPf
.type _Z21vector_set_f32_kernelPKfifPf, @function
_Z21vector_set_f32_kernelPKfifPf:
.LFB2063:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z46__device_stub__Z21vector_set_f32_kernelPKfifPfPKfifPf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2063:
.size _Z21vector_set_f32_kernelPKfifPf, .-_Z21vector_set_f32_kernelPKfifPf
.globl array_cuda_vector_set_f32
.type array_cuda_vector_set_f32, @function
array_cuda_vector_set_f32:
.LFB2029:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $48, %rsp
.cfi_def_cfa_offset 80
movq %rdi, %rbp
movl %esi, %ebx
movss %xmm0, 12(%rsp)
movq %rdx, %r12
movq %rcx, %r9
movl $1024, 36(%rsp)
movl $1, 40(%rsp)
leal 2046(%rsi), %eax
movl %esi, %edx
addl $1023, %edx
cmovns %edx, %eax
sarl $10, %eax
movl %eax, 24(%rsp)
movl $1, 28(%rsp)
movl $0, %r8d
movq 36(%rsp), %rdx
movl $1, %ecx
movq 24(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L38
.L35:
addq $48, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L38:
.cfi_restore_state
movq %r12, %rdx
movss 12(%rsp), %xmm0
movl %ebx, %esi
movq %rbp, %rdi
call _Z46__device_stub__Z21vector_set_f32_kernelPKfifPfPKfifPf
jmp .L35
.cfi_endproc
.LFE2029:
.size array_cuda_vector_set_f32, .-array_cuda_vector_set_f32
.globl _Z47__device_stub__Z21vector_add_f32_kernelPKfiffPfPKfiffPf
.type _Z47__device_stub__Z21vector_add_f32_kernelPKfiffPfPKfiffPf, @function
_Z47__device_stub__Z21vector_add_f32_kernelPKfiffPfPKfiffPf:
.LFB2064:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movl %esi, 20(%rsp)
movss %xmm0, 16(%rsp)
movss %xmm1, 12(%rsp)
movq %rdx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 12(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L43
.L39:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L44
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L43:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z21vector_add_f32_kernelPKfiffPf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L39
.L44:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2064:
.size _Z47__device_stub__Z21vector_add_f32_kernelPKfiffPfPKfiffPf, .-_Z47__device_stub__Z21vector_add_f32_kernelPKfiffPfPKfiffPf
.globl _Z21vector_add_f32_kernelPKfiffPf
.type _Z21vector_add_f32_kernelPKfiffPf, @function
_Z21vector_add_f32_kernelPKfiffPf:
.LFB2065:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z47__device_stub__Z21vector_add_f32_kernelPKfiffPfPKfiffPf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2065:
.size _Z21vector_add_f32_kernelPKfiffPf, .-_Z21vector_add_f32_kernelPKfiffPf
.globl array_cuda_vector_add_f32
.type array_cuda_vector_add_f32, @function
array_cuda_vector_add_f32:
.LFB2030:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $48, %rsp
.cfi_def_cfa_offset 80
movq %rdi, %rbp
movl %esi, %ebx
movss %xmm0, 8(%rsp)
movss %xmm1, 12(%rsp)
movq %rdx, %r12
movq %rcx, %r9
movl $1024, 36(%rsp)
movl $1, 40(%rsp)
leal 2046(%rsi), %eax
movl %esi, %edx
addl $1023, %edx
cmovns %edx, %eax
sarl $10, %eax
movl %eax, 24(%rsp)
movl $1, 28(%rsp)
movl $0, %r8d
movq 36(%rsp), %rdx
movl $1, %ecx
movq 24(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L50
.L47:
addq $48, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L50:
.cfi_restore_state
movq %r12, %rdx
movss 12(%rsp), %xmm1
movss 8(%rsp), %xmm0
movl %ebx, %esi
movq %rbp, %rdi
call _Z47__device_stub__Z21vector_add_f32_kernelPKfiffPfPKfiffPf
jmp .L47
.cfi_endproc
.LFE2030:
.size array_cuda_vector_add_f32, .-array_cuda_vector_add_f32
.globl _Z53__device_stub__Z28vector_avg_online_f32_kernelPKfifPfPKfifPf
.type _Z53__device_stub__Z28vector_avg_online_f32_kernelPKfifPfPKfifPf, @function
_Z53__device_stub__Z28vector_avg_online_f32_kernelPKfifPfPKfifPf:
.LFB2066:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movl %esi, 20(%rsp)
movss %xmm0, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L55
.L51:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L56
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L55:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z28vector_avg_online_f32_kernelPKfifPf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L51
.L56:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2066:
.size _Z53__device_stub__Z28vector_avg_online_f32_kernelPKfifPfPKfifPf, .-_Z53__device_stub__Z28vector_avg_online_f32_kernelPKfifPfPKfifPf
.globl _Z28vector_avg_online_f32_kernelPKfifPf
.type _Z28vector_avg_online_f32_kernelPKfifPf, @function
_Z28vector_avg_online_f32_kernelPKfifPf:
.LFB2067:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z53__device_stub__Z28vector_avg_online_f32_kernelPKfifPfPKfifPf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2067:
.size _Z28vector_avg_online_f32_kernelPKfifPf, .-_Z28vector_avg_online_f32_kernelPKfifPf
.globl array_cuda_vector_avg_online_f32
.type array_cuda_vector_avg_online_f32, @function
array_cuda_vector_avg_online_f32:
.LFB2031:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $48, %rsp
.cfi_def_cfa_offset 80
movq %rdi, %rbp
movl %esi, %ebx
movss %xmm0, 12(%rsp)
movq %rdx, %r12
movq %rcx, %r9
movl $1024, 36(%rsp)
movl $1, 40(%rsp)
leal 2046(%rsi), %eax
movl %esi, %edx
addl $1023, %edx
cmovns %edx, %eax
sarl $10, %eax
movl %eax, 24(%rsp)
movl $1, 28(%rsp)
movl $0, %r8d
movq 36(%rsp), %rdx
movl $1, %ecx
movq 24(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L62
.L59:
addq $48, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L62:
.cfi_restore_state
movq %r12, %rdx
movss 12(%rsp), %xmm0
movl %ebx, %esi
movq %rbp, %rdi
call _Z53__device_stub__Z28vector_avg_online_f32_kernelPKfifPfPKfifPf
jmp .L59
.cfi_endproc
.LFE2031:
.size array_cuda_vector_avg_online_f32, .-array_cuda_vector_avg_online_f32
.globl _Z55__device_stub__Z31vector_elemwise_mult_f32_kernelPKfiPfPKfiPf
.type _Z55__device_stub__Z31vector_elemwise_mult_f32_kernelPKfiPfPKfiPf, @function
_Z55__device_stub__Z31vector_elemwise_mult_f32_kernelPKfiPfPKfiPf:
.LFB2068:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movl %esi, 20(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L67
.L63:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L68
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L67:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z31vector_elemwise_mult_f32_kernelPKfiPf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L63
.L68:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2068:
.size _Z55__device_stub__Z31vector_elemwise_mult_f32_kernelPKfiPfPKfiPf, .-_Z55__device_stub__Z31vector_elemwise_mult_f32_kernelPKfiPfPKfiPf
.globl _Z31vector_elemwise_mult_f32_kernelPKfiPf
.type _Z31vector_elemwise_mult_f32_kernelPKfiPf, @function
_Z31vector_elemwise_mult_f32_kernelPKfiPf:
.LFB2069:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z55__device_stub__Z31vector_elemwise_mult_f32_kernelPKfiPfPKfiPf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2069:
.size _Z31vector_elemwise_mult_f32_kernelPKfiPf, .-_Z31vector_elemwise_mult_f32_kernelPKfiPf
.globl array_cuda_vector_elemwise_mult_f32
.type array_cuda_vector_elemwise_mult_f32, @function
array_cuda_vector_elemwise_mult_f32:
.LFB2032:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $32, %rsp
.cfi_def_cfa_offset 64
movq %rdi, %rbp
movl %esi, %ebx
movq %rdx, %r12
movq %rcx, %r9
movl $1024, 20(%rsp)
movl $1, 24(%rsp)
leal 2046(%rsi), %eax
movl %esi, %edx
addl $1023, %edx
cmovns %edx, %eax
sarl $10, %eax
movl %eax, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L74
.L71:
addq $32, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L74:
.cfi_restore_state
movq %r12, %rdx
movl %ebx, %esi
movq %rbp, %rdi
call _Z55__device_stub__Z31vector_elemwise_mult_f32_kernelPKfiPfPKfiPf
jmp .L71
.cfi_endproc
.LFE2032:
.size array_cuda_vector_elemwise_mult_f32, .-array_cuda_vector_elemwise_mult_f32
.globl _Z54__device_stub__Z30vector_elemwise_div_f32_kernelPKfiPfPKfiPf
.type _Z54__device_stub__Z30vector_elemwise_div_f32_kernelPKfiPfPKfiPf, @function
_Z54__device_stub__Z30vector_elemwise_div_f32_kernelPKfiPfPKfiPf:
.LFB2070:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movl %esi, 20(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L79
.L75:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L80
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L79:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z30vector_elemwise_div_f32_kernelPKfiPf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L75
.L80:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2070:
.size _Z54__device_stub__Z30vector_elemwise_div_f32_kernelPKfiPfPKfiPf, .-_Z54__device_stub__Z30vector_elemwise_div_f32_kernelPKfiPfPKfiPf
.globl _Z30vector_elemwise_div_f32_kernelPKfiPf
.type _Z30vector_elemwise_div_f32_kernelPKfiPf, @function
_Z30vector_elemwise_div_f32_kernelPKfiPf:
.LFB2071:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z54__device_stub__Z30vector_elemwise_div_f32_kernelPKfiPfPKfiPf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2071:
.size _Z30vector_elemwise_div_f32_kernelPKfiPf, .-_Z30vector_elemwise_div_f32_kernelPKfiPf
.globl array_cuda_vector_elemwise_div_f32
.type array_cuda_vector_elemwise_div_f32, @function
array_cuda_vector_elemwise_div_f32:
.LFB2033:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $32, %rsp
.cfi_def_cfa_offset 64
movq %rdi, %rbp
movl %esi, %ebx
movq %rdx, %r12
movq %rcx, %r9
movl $1024, 20(%rsp)
movl $1, 24(%rsp)
leal 2046(%rsi), %eax
movl %esi, %edx
addl $1023, %edx
cmovns %edx, %eax
sarl $10, %eax
movl %eax, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L86
.L83:
addq $32, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L86:
.cfi_restore_state
movq %r12, %rdx
movl %ebx, %esi
movq %rbp, %rdi
call _Z54__device_stub__Z30vector_elemwise_div_f32_kernelPKfiPfPKfiPf
jmp .L83
.cfi_endproc
.LFE2033:
.size array_cuda_vector_elemwise_div_f32, .-array_cuda_vector_elemwise_div_f32
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z30vector_elemwise_div_f32_kernelPKfiPf"
.align 8
.LC1:
.string "_Z31vector_elemwise_mult_f32_kernelPKfiPf"
.align 8
.LC2:
.string "_Z28vector_avg_online_f32_kernelPKfifPf"
.align 8
.LC3:
.string "_Z21vector_add_f32_kernelPKfiffPf"
.align 8
.LC4:
.string "_Z21vector_set_f32_kernelPKfifPf"
.section .rodata.str1.1,"aMS",@progbits,1
.LC5:
.string "_Z21vector_exp_f32_kernelPfi"
.section .rodata.str1.8
.align 8
.LC6:
.string "_Z23vector_scale_f32_kernelPfif"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2073:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z30vector_elemwise_div_f32_kernelPKfiPf(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z31vector_elemwise_mult_f32_kernelPKfiPf(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z28vector_avg_online_f32_kernelPKfifPf(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z21vector_add_f32_kernelPKfiffPf(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z21vector_set_f32_kernelPKfifPf(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _Z21vector_exp_f32_kernelPfi(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _Z23vector_scale_f32_kernelPfif(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2073:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
```
|
```amdasm
.text
.file "vector_kernels.hip"
.globl _Z38__device_stub__vector_scale_f32_kernelPfif # -- Begin function _Z38__device_stub__vector_scale_f32_kernelPfif
.type _Z38__device_stub__vector_scale_f32_kernelPfif,@function
_Z38__device_stub__vector_scale_f32_kernelPfif: # @_Z38__device_stub__vector_scale_f32_kernelPfif
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $96, %rsp
.cfi_def_cfa_offset 144
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 24(%rsp), %rax
movq %rdi, (%rax)
leaq 4(%rsp), %rcx
movl %esi, (%rcx)
movq %rsp, %rdx
movss %xmm0, (%rdx)
leaq 64(%rsp), %rbx
movq %rax, (%rbx)
movq %rcx, 8(%rbx)
movq %rdx, 16(%rbx)
leaq 48(%rsp), %r14
leaq 32(%rsp), %r15
leaq 16(%rsp), %r12
leaq 8(%rsp), %r13
movq %r14, %rdi
movq %r15, %rsi
movq %r12, %rdx
movq %r13, %rcx
callq __hipPopCallConfiguration
movq (%r14), %rsi
movl 8(%r14), %edx
movq (%r15), %rcx
movl 8(%r15), %r8d
movl $_Z23vector_scale_f32_kernelPfif, %edi
movq %rbx, %r9
pushq (%r13)
.cfi_adjust_cfa_offset 8
pushq (%r12)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $112, %rsp
.cfi_adjust_cfa_offset -112
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z38__device_stub__vector_scale_f32_kernelPfif, .Lfunc_end0-_Z38__device_stub__vector_scale_f32_kernelPfif
.cfi_endproc
# -- End function
.globl array_cuda_vector_scale_f32 # -- Begin function array_cuda_vector_scale_f32
.type array_cuda_vector_scale_f32,@function
array_cuda_vector_scale_f32: # @array_cuda_vector_scale_f32
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
pushq %rax
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movq %rdx, %r9
movss %xmm0, 4(%rsp) # 4-byte Spill
movl %esi, %ebx
movq %rdi, %r14
leal 1023(%rbx), %eax
leal 2046(%rbx), %edi
testl %eax, %eax
cmovnsl %eax, %edi
sarl $10, %edi
btsq $32, %rdi
movabsq $4294967296, %rdx # imm = 0x100000000
orq $1024, %rdx # imm = 0x400
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
callq __hipPushCallConfiguration
testl %eax, %eax
je .LBB1_2
# %bb.1:
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.LBB1_2:
.cfi_def_cfa_offset 32
movq %r14, %rdi
movl %ebx, %esi
movss 4(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
jmp _Z38__device_stub__vector_scale_f32_kernelPfif # TAILCALL
.Lfunc_end1:
.size array_cuda_vector_scale_f32, .Lfunc_end1-array_cuda_vector_scale_f32
.cfi_endproc
# -- End function
.globl _Z36__device_stub__vector_exp_f32_kernelPfi # -- Begin function _Z36__device_stub__vector_exp_f32_kernelPfi
.type _Z36__device_stub__vector_exp_f32_kernelPfi,@function
_Z36__device_stub__vector_exp_f32_kernelPfi: # @_Z36__device_stub__vector_exp_f32_kernelPfi
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $80, %rsp
.cfi_def_cfa_offset 128
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 24(%rsp), %rax
movq %rdi, (%rax)
leaq 4(%rsp), %rcx
movl %esi, (%rcx)
leaq 64(%rsp), %rbx
movq %rax, (%rbx)
movq %rcx, 8(%rbx)
leaq 48(%rsp), %r14
leaq 32(%rsp), %r15
leaq 16(%rsp), %r12
leaq 8(%rsp), %r13
movq %r14, %rdi
movq %r15, %rsi
movq %r12, %rdx
movq %r13, %rcx
callq __hipPopCallConfiguration
movq (%r14), %rsi
movl 8(%r14), %edx
movq (%r15), %rcx
movl 8(%r15), %r8d
movl $_Z21vector_exp_f32_kernelPfi, %edi
movq %rbx, %r9
pushq (%r13)
.cfi_adjust_cfa_offset 8
pushq (%r12)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $96, %rsp
.cfi_adjust_cfa_offset -96
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size _Z36__device_stub__vector_exp_f32_kernelPfi, .Lfunc_end2-_Z36__device_stub__vector_exp_f32_kernelPfi
.cfi_endproc
# -- End function
.globl array_cuda_vector_exp_f32 # -- Begin function array_cuda_vector_exp_f32
.type array_cuda_vector_exp_f32,@function
array_cuda_vector_exp_f32: # @array_cuda_vector_exp_f32
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
pushq %rax
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movq %rdx, %r9
movl %esi, %ebx
movq %rdi, %r14
leal 1023(%rbx), %eax
leal 2046(%rbx), %edi
testl %eax, %eax
cmovnsl %eax, %edi
sarl $10, %edi
btsq $32, %rdi
movabsq $4294967296, %rdx # imm = 0x100000000
orq $1024, %rdx # imm = 0x400
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
callq __hipPushCallConfiguration
testl %eax, %eax
je .LBB3_2
# %bb.1:
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.LBB3_2:
.cfi_def_cfa_offset 32
movq %r14, %rdi
movl %ebx, %esi
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
jmp _Z36__device_stub__vector_exp_f32_kernelPfi # TAILCALL
.Lfunc_end3:
.size array_cuda_vector_exp_f32, .Lfunc_end3-array_cuda_vector_exp_f32
.cfi_endproc
# -- End function
.globl _Z36__device_stub__vector_set_f32_kernelPKfifPf # -- Begin function _Z36__device_stub__vector_set_f32_kernelPKfifPf
.type _Z36__device_stub__vector_set_f32_kernelPKfifPf,@function
_Z36__device_stub__vector_set_f32_kernelPKfifPf: # @_Z36__device_stub__vector_set_f32_kernelPKfifPf
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $112, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 40(%rsp), %rax
movq %rdi, (%rax)
leaq 12(%rsp), %rcx
movl %esi, (%rcx)
leaq 8(%rsp), %rsi
movss %xmm0, (%rsi)
leaq 32(%rsp), %rdi
movq %rdx, (%rdi)
leaq 80(%rsp), %rbx
movq %rax, (%rbx)
movq %rcx, 8(%rbx)
movq %rsi, 16(%rbx)
movq %rdi, 24(%rbx)
leaq 64(%rsp), %r14
leaq 48(%rsp), %r15
leaq 24(%rsp), %r12
leaq 16(%rsp), %r13
movq %r14, %rdi
movq %r15, %rsi
movq %r12, %rdx
movq %r13, %rcx
callq __hipPopCallConfiguration
movq (%r14), %rsi
movl 8(%r14), %edx
movq (%r15), %rcx
movl 8(%r15), %r8d
movl $_Z21vector_set_f32_kernelPKfifPf, %edi
movq %rbx, %r9
pushq (%r13)
.cfi_adjust_cfa_offset 8
pushq (%r12)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $128, %rsp
.cfi_adjust_cfa_offset -128
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end4:
.size _Z36__device_stub__vector_set_f32_kernelPKfifPf, .Lfunc_end4-_Z36__device_stub__vector_set_f32_kernelPKfifPf
.cfi_endproc
# -- End function
.globl array_cuda_vector_set_f32 # -- Begin function array_cuda_vector_set_f32
.type array_cuda_vector_set_f32,@function
array_cuda_vector_set_f32: # @array_cuda_vector_set_f32
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $16, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rcx, %r9
movq %rdx, %rbx
movss %xmm0, 12(%rsp) # 4-byte Spill
movl %esi, %r14d
movq %rdi, %r15
leal 1023(%r14), %eax
leal 2046(%r14), %edi
testl %eax, %eax
cmovnsl %eax, %edi
sarl $10, %edi
btsq $32, %rdi
movabsq $4294967296, %rdx # imm = 0x100000000
orq $1024, %rdx # imm = 0x400
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
callq __hipPushCallConfiguration
testl %eax, %eax
je .LBB5_2
# %bb.1:
addq $16, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB5_2:
.cfi_def_cfa_offset 48
movq %r15, %rdi
movl %r14d, %esi
movss 12(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
movq %rbx, %rdx
addq $16, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
jmp _Z36__device_stub__vector_set_f32_kernelPKfifPf # TAILCALL
.Lfunc_end5:
.size array_cuda_vector_set_f32, .Lfunc_end5-array_cuda_vector_set_f32
.cfi_endproc
# -- End function
.globl _Z36__device_stub__vector_add_f32_kernelPKfiffPf # -- Begin function _Z36__device_stub__vector_add_f32_kernelPKfiffPf
.type _Z36__device_stub__vector_add_f32_kernelPKfiffPf,@function
_Z36__device_stub__vector_add_f32_kernelPKfiffPf: # @_Z36__device_stub__vector_add_f32_kernelPKfiffPf
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $128, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 40(%rsp), %rax
movq %rdi, (%rax)
leaq 12(%rsp), %rcx
movl %esi, (%rcx)
leaq 8(%rsp), %rsi
movss %xmm0, (%rsi)
leaq 4(%rsp), %rdi
movss %xmm1, (%rdi)
leaq 32(%rsp), %r8
movq %rdx, (%r8)
leaq 80(%rsp), %rbx
movq %rax, (%rbx)
movq %rcx, 8(%rbx)
movq %rsi, 16(%rbx)
movq %rdi, 24(%rbx)
movq %r8, 32(%rbx)
leaq 64(%rsp), %r14
leaq 48(%rsp), %r15
leaq 24(%rsp), %r12
leaq 16(%rsp), %r13
movq %r14, %rdi
movq %r15, %rsi
movq %r12, %rdx
movq %r13, %rcx
callq __hipPopCallConfiguration
movq (%r14), %rsi
movl 8(%r14), %edx
movq (%r15), %rcx
movl 8(%r15), %r8d
movl $_Z21vector_add_f32_kernelPKfiffPf, %edi
movq %rbx, %r9
pushq (%r13)
.cfi_adjust_cfa_offset 8
pushq (%r12)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $144, %rsp
.cfi_adjust_cfa_offset -144
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end6:
.size _Z36__device_stub__vector_add_f32_kernelPKfiffPf, .Lfunc_end6-_Z36__device_stub__vector_add_f32_kernelPKfiffPf
.cfi_endproc
# -- End function
.globl array_cuda_vector_add_f32 # -- Begin function array_cuda_vector_add_f32
.type array_cuda_vector_add_f32,@function
array_cuda_vector_add_f32: # @array_cuda_vector_add_f32
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $16, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rcx, %r9
movq %rdx, %rbx
movss %xmm1, 12(%rsp) # 4-byte Spill
movss %xmm0, 8(%rsp) # 4-byte Spill
movl %esi, %r14d
movq %rdi, %r15
leal 1023(%r14), %eax
leal 2046(%r14), %edi
testl %eax, %eax
cmovnsl %eax, %edi
sarl $10, %edi
btsq $32, %rdi
movabsq $4294967296, %rdx # imm = 0x100000000
orq $1024, %rdx # imm = 0x400
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
callq __hipPushCallConfiguration
testl %eax, %eax
je .LBB7_2
# %bb.1:
addq $16, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB7_2:
.cfi_def_cfa_offset 48
movq %r15, %rdi
movl %r14d, %esi
movss 8(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
movss 12(%rsp), %xmm1 # 4-byte Reload
# xmm1 = mem[0],zero,zero,zero
movq %rbx, %rdx
addq $16, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
jmp _Z36__device_stub__vector_add_f32_kernelPKfiffPf # TAILCALL
.Lfunc_end7:
.size array_cuda_vector_add_f32, .Lfunc_end7-array_cuda_vector_add_f32
.cfi_endproc
# -- End function
.globl _Z43__device_stub__vector_avg_online_f32_kernelPKfifPf # -- Begin function _Z43__device_stub__vector_avg_online_f32_kernelPKfifPf
.type _Z43__device_stub__vector_avg_online_f32_kernelPKfifPf,@function
_Z43__device_stub__vector_avg_online_f32_kernelPKfifPf: # @_Z43__device_stub__vector_avg_online_f32_kernelPKfifPf
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $112, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 40(%rsp), %rax
movq %rdi, (%rax)
leaq 12(%rsp), %rcx
movl %esi, (%rcx)
leaq 8(%rsp), %rsi
movss %xmm0, (%rsi)
leaq 32(%rsp), %rdi
movq %rdx, (%rdi)
leaq 80(%rsp), %rbx
movq %rax, (%rbx)
movq %rcx, 8(%rbx)
movq %rsi, 16(%rbx)
movq %rdi, 24(%rbx)
leaq 64(%rsp), %r14
leaq 48(%rsp), %r15
leaq 24(%rsp), %r12
leaq 16(%rsp), %r13
movq %r14, %rdi
movq %r15, %rsi
movq %r12, %rdx
movq %r13, %rcx
callq __hipPopCallConfiguration
movq (%r14), %rsi
movl 8(%r14), %edx
movq (%r15), %rcx
movl 8(%r15), %r8d
movl $_Z28vector_avg_online_f32_kernelPKfifPf, %edi
movq %rbx, %r9
pushq (%r13)
.cfi_adjust_cfa_offset 8
pushq (%r12)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $128, %rsp
.cfi_adjust_cfa_offset -128
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end8:
.size _Z43__device_stub__vector_avg_online_f32_kernelPKfifPf, .Lfunc_end8-_Z43__device_stub__vector_avg_online_f32_kernelPKfifPf
.cfi_endproc
# -- End function
.globl array_cuda_vector_avg_online_f32 # -- Begin function array_cuda_vector_avg_online_f32
.type array_cuda_vector_avg_online_f32,@function
array_cuda_vector_avg_online_f32: # @array_cuda_vector_avg_online_f32
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $16, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rcx, %r9
movq %rdx, %rbx
movss %xmm0, 12(%rsp) # 4-byte Spill
movl %esi, %r14d
movq %rdi, %r15
leal 1023(%r14), %eax
leal 2046(%r14), %edi
testl %eax, %eax
cmovnsl %eax, %edi
sarl $10, %edi
btsq $32, %rdi
movabsq $4294967296, %rdx # imm = 0x100000000
orq $1024, %rdx # imm = 0x400
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
callq __hipPushCallConfiguration
testl %eax, %eax
je .LBB9_2
# %bb.1:
addq $16, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB9_2:
.cfi_def_cfa_offset 48
movq %r15, %rdi
movl %r14d, %esi
movss 12(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
movq %rbx, %rdx
addq $16, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
jmp _Z43__device_stub__vector_avg_online_f32_kernelPKfifPf # TAILCALL
.Lfunc_end9:
.size array_cuda_vector_avg_online_f32, .Lfunc_end9-array_cuda_vector_avg_online_f32
.cfi_endproc
# -- End function
.globl _Z46__device_stub__vector_elemwise_mult_f32_kernelPKfiPf # -- Begin function _Z46__device_stub__vector_elemwise_mult_f32_kernelPKfiPf
.type _Z46__device_stub__vector_elemwise_mult_f32_kernelPKfiPf,@function
_Z46__device_stub__vector_elemwise_mult_f32_kernelPKfiPf: # @_Z46__device_stub__vector_elemwise_mult_f32_kernelPKfiPf
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $112, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 40(%rsp), %rax
movq %rdi, (%rax)
leaq 12(%rsp), %rcx
movl %esi, (%rcx)
leaq 32(%rsp), %rsi
movq %rdx, (%rsi)
leaq 80(%rsp), %rbx
movq %rax, (%rbx)
movq %rcx, 8(%rbx)
movq %rsi, 16(%rbx)
leaq 64(%rsp), %r14
leaq 48(%rsp), %r15
leaq 24(%rsp), %r12
leaq 16(%rsp), %r13
movq %r14, %rdi
movq %r15, %rsi
movq %r12, %rdx
movq %r13, %rcx
callq __hipPopCallConfiguration
movq (%r14), %rsi
movl 8(%r14), %edx
movq (%r15), %rcx
movl 8(%r15), %r8d
movl $_Z31vector_elemwise_mult_f32_kernelPKfiPf, %edi
movq %rbx, %r9
pushq (%r13)
.cfi_adjust_cfa_offset 8
pushq (%r12)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $128, %rsp
.cfi_adjust_cfa_offset -128
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end10:
.size _Z46__device_stub__vector_elemwise_mult_f32_kernelPKfiPf, .Lfunc_end10-_Z46__device_stub__vector_elemwise_mult_f32_kernelPKfiPf
.cfi_endproc
# -- End function
.globl array_cuda_vector_elemwise_mult_f32 # -- Begin function array_cuda_vector_elemwise_mult_f32
.type array_cuda_vector_elemwise_mult_f32,@function
array_cuda_vector_elemwise_mult_f32: # @array_cuda_vector_elemwise_mult_f32
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rcx, %r9
movq %rdx, %rbx
movl %esi, %r14d
movq %rdi, %r15
leal 1023(%r14), %eax
leal 2046(%r14), %edi
testl %eax, %eax
cmovnsl %eax, %edi
sarl $10, %edi
btsq $32, %rdi
movabsq $4294967296, %rdx # imm = 0x100000000
orq $1024, %rdx # imm = 0x400
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
callq __hipPushCallConfiguration
testl %eax, %eax
je .LBB11_2
# %bb.1:
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB11_2:
.cfi_def_cfa_offset 32
movq %r15, %rdi
movl %r14d, %esi
movq %rbx, %rdx
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
jmp _Z46__device_stub__vector_elemwise_mult_f32_kernelPKfiPf # TAILCALL
.Lfunc_end11:
.size array_cuda_vector_elemwise_mult_f32, .Lfunc_end11-array_cuda_vector_elemwise_mult_f32
.cfi_endproc
# -- End function
.globl _Z45__device_stub__vector_elemwise_div_f32_kernelPKfiPf # -- Begin function _Z45__device_stub__vector_elemwise_div_f32_kernelPKfiPf
.type _Z45__device_stub__vector_elemwise_div_f32_kernelPKfiPf,@function
_Z45__device_stub__vector_elemwise_div_f32_kernelPKfiPf: # @_Z45__device_stub__vector_elemwise_div_f32_kernelPKfiPf
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $112, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 40(%rsp), %rax
movq %rdi, (%rax)
leaq 12(%rsp), %rcx
movl %esi, (%rcx)
leaq 32(%rsp), %rsi
movq %rdx, (%rsi)
leaq 80(%rsp), %rbx
movq %rax, (%rbx)
movq %rcx, 8(%rbx)
movq %rsi, 16(%rbx)
leaq 64(%rsp), %r14
leaq 48(%rsp), %r15
leaq 24(%rsp), %r12
leaq 16(%rsp), %r13
movq %r14, %rdi
movq %r15, %rsi
movq %r12, %rdx
movq %r13, %rcx
callq __hipPopCallConfiguration
movq (%r14), %rsi
movl 8(%r14), %edx
movq (%r15), %rcx
movl 8(%r15), %r8d
movl $_Z30vector_elemwise_div_f32_kernelPKfiPf, %edi
movq %rbx, %r9
pushq (%r13)
.cfi_adjust_cfa_offset 8
pushq (%r12)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $128, %rsp
.cfi_adjust_cfa_offset -128
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end12:
.size _Z45__device_stub__vector_elemwise_div_f32_kernelPKfiPf, .Lfunc_end12-_Z45__device_stub__vector_elemwise_div_f32_kernelPKfiPf
.cfi_endproc
# -- End function
.globl array_cuda_vector_elemwise_div_f32 # -- Begin function array_cuda_vector_elemwise_div_f32
.type array_cuda_vector_elemwise_div_f32,@function
array_cuda_vector_elemwise_div_f32: # @array_cuda_vector_elemwise_div_f32
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rcx, %r9
movq %rdx, %rbx
movl %esi, %r14d
movq %rdi, %r15
leal 1023(%r14), %eax
leal 2046(%r14), %edi
testl %eax, %eax
cmovnsl %eax, %edi
sarl $10, %edi
btsq $32, %rdi
movabsq $4294967296, %rdx # imm = 0x100000000
orq $1024, %rdx # imm = 0x400
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
callq __hipPushCallConfiguration
testl %eax, %eax
je .LBB13_2
# %bb.1:
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB13_2:
.cfi_def_cfa_offset 32
movq %r15, %rdi
movl %r14d, %esi
movq %rbx, %rdx
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
jmp _Z45__device_stub__vector_elemwise_div_f32_kernelPKfiPf # TAILCALL
.Lfunc_end13:
.size array_cuda_vector_elemwise_div_f32, .Lfunc_end13-array_cuda_vector_elemwise_div_f32
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
movq __hip_gpubin_handle(%rip), %rbx
testq %rbx, %rbx
jne .LBB14_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, %rbx
movq %rax, __hip_gpubin_handle(%rip)
.LBB14_2:
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z23vector_scale_f32_kernelPfif, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z21vector_exp_f32_kernelPfi, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z21vector_set_f32_kernelPKfifPf, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z21vector_add_f32_kernelPKfiffPf, %esi
movl $.L__unnamed_4, %edx
movl $.L__unnamed_4, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z28vector_avg_online_f32_kernelPKfifPf, %esi
movl $.L__unnamed_5, %edx
movl $.L__unnamed_5, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z31vector_elemwise_mult_f32_kernelPKfiPf, %esi
movl $.L__unnamed_6, %edx
movl $.L__unnamed_6, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z30vector_elemwise_div_f32_kernelPKfiPf, %esi
movl $.L__unnamed_7, %edx
movl $.L__unnamed_7, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end14:
.size __hip_module_ctor, .Lfunc_end14-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB15_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB15_2:
retq
.Lfunc_end15:
.size __hip_module_dtor, .Lfunc_end15-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z23vector_scale_f32_kernelPfif,@object # @_Z23vector_scale_f32_kernelPfif
.section .rodata,"a",@progbits
.globl _Z23vector_scale_f32_kernelPfif
.p2align 3, 0x0
_Z23vector_scale_f32_kernelPfif:
.quad _Z38__device_stub__vector_scale_f32_kernelPfif
.size _Z23vector_scale_f32_kernelPfif, 8
.type _Z21vector_exp_f32_kernelPfi,@object # @_Z21vector_exp_f32_kernelPfi
.globl _Z21vector_exp_f32_kernelPfi
.p2align 3, 0x0
_Z21vector_exp_f32_kernelPfi:
.quad _Z36__device_stub__vector_exp_f32_kernelPfi
.size _Z21vector_exp_f32_kernelPfi, 8
.type _Z21vector_set_f32_kernelPKfifPf,@object # @_Z21vector_set_f32_kernelPKfifPf
.globl _Z21vector_set_f32_kernelPKfifPf
.p2align 3, 0x0
_Z21vector_set_f32_kernelPKfifPf:
.quad _Z36__device_stub__vector_set_f32_kernelPKfifPf
.size _Z21vector_set_f32_kernelPKfifPf, 8
.type _Z21vector_add_f32_kernelPKfiffPf,@object # @_Z21vector_add_f32_kernelPKfiffPf
.globl _Z21vector_add_f32_kernelPKfiffPf
.p2align 3, 0x0
_Z21vector_add_f32_kernelPKfiffPf:
.quad _Z36__device_stub__vector_add_f32_kernelPKfiffPf
.size _Z21vector_add_f32_kernelPKfiffPf, 8
.type _Z28vector_avg_online_f32_kernelPKfifPf,@object # @_Z28vector_avg_online_f32_kernelPKfifPf
.globl _Z28vector_avg_online_f32_kernelPKfifPf
.p2align 3, 0x0
_Z28vector_avg_online_f32_kernelPKfifPf:
.quad _Z43__device_stub__vector_avg_online_f32_kernelPKfifPf
.size _Z28vector_avg_online_f32_kernelPKfifPf, 8
.type _Z31vector_elemwise_mult_f32_kernelPKfiPf,@object # @_Z31vector_elemwise_mult_f32_kernelPKfiPf
.globl _Z31vector_elemwise_mult_f32_kernelPKfiPf
.p2align 3, 0x0
_Z31vector_elemwise_mult_f32_kernelPKfiPf:
.quad _Z46__device_stub__vector_elemwise_mult_f32_kernelPKfiPf
.size _Z31vector_elemwise_mult_f32_kernelPKfiPf, 8
.type _Z30vector_elemwise_div_f32_kernelPKfiPf,@object # @_Z30vector_elemwise_div_f32_kernelPKfiPf
.globl _Z30vector_elemwise_div_f32_kernelPKfiPf
.p2align 3, 0x0
_Z30vector_elemwise_div_f32_kernelPKfiPf:
.quad _Z45__device_stub__vector_elemwise_div_f32_kernelPKfiPf
.size _Z30vector_elemwise_div_f32_kernelPKfiPf, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z23vector_scale_f32_kernelPfif"
.size .L__unnamed_1, 32
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z21vector_exp_f32_kernelPfi"
.size .L__unnamed_2, 29
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z21vector_set_f32_kernelPKfifPf"
.size .L__unnamed_3, 33
.type .L__unnamed_4,@object # @3
.L__unnamed_4:
.asciz "_Z21vector_add_f32_kernelPKfiffPf"
.size .L__unnamed_4, 34
.type .L__unnamed_5,@object # @4
.L__unnamed_5:
.asciz "_Z28vector_avg_online_f32_kernelPKfifPf"
.size .L__unnamed_5, 40
.type .L__unnamed_6,@object # @5
.L__unnamed_6:
.asciz "_Z31vector_elemwise_mult_f32_kernelPKfiPf"
.size .L__unnamed_6, 42
.type .L__unnamed_7,@object # @6
.L__unnamed_7:
.asciz "_Z30vector_elemwise_div_f32_kernelPKfiPf"
.size .L__unnamed_7, 41
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z38__device_stub__vector_scale_f32_kernelPfif
.addrsig_sym _Z36__device_stub__vector_exp_f32_kernelPfi
.addrsig_sym _Z36__device_stub__vector_set_f32_kernelPKfifPf
.addrsig_sym _Z36__device_stub__vector_add_f32_kernelPKfiffPf
.addrsig_sym _Z43__device_stub__vector_avg_online_f32_kernelPKfifPf
.addrsig_sym _Z46__device_stub__vector_elemwise_mult_f32_kernelPKfiPf
.addrsig_sym _Z45__device_stub__vector_elemwise_div_f32_kernelPKfiPf
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z23vector_scale_f32_kernelPfif
.addrsig_sym _Z21vector_exp_f32_kernelPfi
.addrsig_sym _Z21vector_set_f32_kernelPKfifPf
.addrsig_sym _Z21vector_add_f32_kernelPKfiffPf
.addrsig_sym _Z28vector_avg_online_f32_kernelPKfifPf
.addrsig_sym _Z31vector_elemwise_mult_f32_kernelPKfiPf
.addrsig_sym _Z30vector_elemwise_div_f32_kernelPKfiPf
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
```
| 13,034 | 14,322 |
266 |
Convert the following CUDA device assembly code to AMD device assembly:
```cudaasm
code for sm_80
Function : _Z14sumArraysOnGPUPfS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
MOV R1, c[0x0][0x28] ;
S2R R6, SR_CTAID.X ;
S2R R3, SR_TID.X ;
IMAD R6, R6, c[0x0][0x0], R3 ;
ISETP.GE.AND P0, PT, R6, c[0x0][0x178], PT ;
@P0 EXIT ;
HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ;
ULDC.64 UR4, c[0x0][0x118] ;
IMAD.WIDE R4, R6, R7, c[0x0][0x168] ;
IMAD.WIDE R2, R6.reuse, R7.reuse, c[0x0][0x160] ;
LDG.E R4, [R4.64] ;
LDG.E R3, [R2.64] ;
IMAD.WIDE R6, R6, R7, c[0x0][0x170] ;
FADD R9, R4, R3 ;
STG.E [R6.64], R9 ;
EXIT ;
BRA 0x100;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
```
|
```amdasm
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z14sumArraysOnGPUPfS_S_i ; -- Begin function _Z14sumArraysOnGPUPfS_S_i
.globl _Z14sumArraysOnGPUPfS_S_i
.p2align 8
.type _Z14sumArraysOnGPUPfS_S_i,@function
_Z14sumArraysOnGPUPfS_S_i: ; @_Z14sumArraysOnGPUPfS_S_i
; %bb.0:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
; %bb.1:
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_f32_e32 v2, v2, v3
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z14sumArraysOnGPUPfS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z14sumArraysOnGPUPfS_S_i, .Lfunc_end0-_Z14sumArraysOnGPUPfS_S_i
; -- End function
.section .AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 180
; NumSgprs: 18
; NumVgprs: 6
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 6
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object ; @__hip_cuid_
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0 ; 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z14sumArraysOnGPUPfS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z14sumArraysOnGPUPfS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
```
| 404 | 2,612 |
267 |
Convert the following CUDA host assembly code to AMD host assembly:
```cudaasm
.file "tmpxft_0011f3f4_00000000-6_sumArraysOnGPU.cudafe1.cpp"
.text
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z39__device_stub__Z14sumArraysOnGPUPfS_S_iPfS_S_i
.type _Z39__device_stub__Z14sumArraysOnGPUPfS_S_iPfS_S_i, @function
_Z39__device_stub__Z14sumArraysOnGPUPfS_S_iPfS_S_i:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z14sumArraysOnGPUPfS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z39__device_stub__Z14sumArraysOnGPUPfS_S_iPfS_S_i, .-_Z39__device_stub__Z14sumArraysOnGPUPfS_S_iPfS_S_i
.globl _Z14sumArraysOnGPUPfS_S_i
.type _Z14sumArraysOnGPUPfS_S_i, @function
_Z14sumArraysOnGPUPfS_S_i:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z39__device_stub__Z14sumArraysOnGPUPfS_S_iPfS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z14sumArraysOnGPUPfS_S_i, .-_Z14sumArraysOnGPUPfS_S_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z14sumArraysOnGPUPfS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z14sumArraysOnGPUPfS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
```
|
```amdasm
.text
.file "sumArraysOnGPU.hip"
.globl _Z29__device_stub__sumArraysOnGPUPfS_S_i # -- Begin function _Z29__device_stub__sumArraysOnGPUPfS_S_i
.type _Z29__device_stub__sumArraysOnGPUPfS_S_i,@function
_Z29__device_stub__sumArraysOnGPUPfS_S_i: # @_Z29__device_stub__sumArraysOnGPUPfS_S_i
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $112, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 40(%rsp), %rax
movq %rdi, (%rax)
leaq 32(%rsp), %rdi
movq %rsi, (%rdi)
leaq 24(%rsp), %rsi
movq %rdx, (%rsi)
leaq 4(%rsp), %rdx
movl %ecx, (%rdx)
leaq 80(%rsp), %rbx
movq %rax, (%rbx)
movq %rdi, 8(%rbx)
movq %rsi, 16(%rbx)
movq %rdx, 24(%rbx)
leaq 64(%rsp), %r14
leaq 48(%rsp), %r15
leaq 16(%rsp), %r12
leaq 8(%rsp), %r13
movq %r14, %rdi
movq %r15, %rsi
movq %r12, %rdx
movq %r13, %rcx
callq __hipPopCallConfiguration
movq (%r14), %rsi
movl 8(%r14), %edx
movq (%r15), %rcx
movl 8(%r15), %r8d
movl $_Z14sumArraysOnGPUPfS_S_i, %edi
movq %rbx, %r9
pushq (%r13)
.cfi_adjust_cfa_offset 8
pushq (%r12)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $128, %rsp
.cfi_adjust_cfa_offset -128
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z29__device_stub__sumArraysOnGPUPfS_S_i, .Lfunc_end0-_Z29__device_stub__sumArraysOnGPUPfS_S_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, %rdi
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z14sumArraysOnGPUPfS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z14sumArraysOnGPUPfS_S_i,@object # @_Z14sumArraysOnGPUPfS_S_i
.section .rodata,"a",@progbits
.globl _Z14sumArraysOnGPUPfS_S_i
.p2align 3, 0x0
_Z14sumArraysOnGPUPfS_S_i:
.quad _Z29__device_stub__sumArraysOnGPUPfS_S_i
.size _Z14sumArraysOnGPUPfS_S_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z14sumArraysOnGPUPfS_S_i"
.size .L__unnamed_1, 26
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z29__device_stub__sumArraysOnGPUPfS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z14sumArraysOnGPUPfS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
```
| 1,934 | 2,119 |
272 |
Convert the following CUDA device assembly code to AMD device assembly:
```cudaasm
code for sm_80
Function : _Z13kernel_add_sqPfPKfS1_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
MOV R1, c[0x0][0x28] ;
S2R R6, SR_TID.X ;
S2R R3, SR_CTAID.X ;
IMAD R6, R3, c[0x0][0x0], R6 ;
ISETP.GE.AND P0, PT, R6, c[0x0][0x178], PT ;
@P0 EXIT ;
HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ;
ULDC.64 UR4, c[0x0][0x118] ;
IMAD.WIDE R4, R6, R7, c[0x0][0x170] ;
IMAD.WIDE R2, R6.reuse, R7.reuse, c[0x0][0x168] ;
LDG.E R4, [R4.64] ;
LDG.E R2, [R2.64] ;
IMAD.WIDE R6, R6, R7, c[0x0][0x160] ;
FMUL R9, R4, R4 ;
FFMA R9, R2, R2, R9 ;
STG.E [R6.64], R9 ;
EXIT ;
BRA 0x110;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
```
|
```amdasm
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z13kernel_add_sqPfPKfS1_i ; -- Begin function _Z13kernel_add_sqPfPKfS1_i
.globl _Z13kernel_add_sqPfPKfS1_i
.p2align 8
.type _Z13kernel_add_sqPfPKfS1_i,@function
_Z13kernel_add_sqPfPKfS1_i: ; @_Z13kernel_add_sqPfPKfS1_i
; %bb.0:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
; %bb.1:
s_clause 0x1
s_load_b64 s[4:5], s[0:1], 0x10
s_load_b128 s[0:3], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s3, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(1)
v_mul_f32_e32 v2, v2, v2
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_fmac_f32_e32 v2, v3, v3
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13kernel_add_sqPfPKfS1_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z13kernel_add_sqPfPKfS1_i, .Lfunc_end0-_Z13kernel_add_sqPfPKfS1_i
; -- End function
.section .AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 196
; NumSgprs: 18
; NumVgprs: 6
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 6
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object ; @__hip_cuid_
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0 ; 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13kernel_add_sqPfPKfS1_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z13kernel_add_sqPfPKfS1_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
```
| 417 | 2,671 |
273 |
Convert the following CUDA host assembly code to AMD host assembly:
```cudaasm
.file "tmpxft_00059222_00000000-6_trig.cudafe1.cpp"
.text
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata._Z5CHECK9cudaError.str1.1,"aMS",@progbits,1
.LC0:
.string "Error: %d %s\n"
.section .text._Z5CHECK9cudaError,"axG",@progbits,_Z5CHECK9cudaError,comdat
.weak _Z5CHECK9cudaError
.type _Z5CHECK9cudaError, @function
_Z5CHECK9cudaError:
.LFB2057:
.cfi_startproc
endbr64
testl %edi, %edi
jne .L8
movl $0, %eax
ret
.L8:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movl %edi, %ebx
call cudaGetErrorString@PLT
movq %rax, %rcx
movl %ebx, %edx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.cfi_endproc
.LFE2057:
.size _Z5CHECK9cudaError, .-_Z5CHECK9cudaError
.text
.globl _Z40__device_stub__Z13kernel_add_sqPfPKfS1_iPfPKfS1_i
.type _Z40__device_stub__Z13kernel_add_sqPfPKfS1_iPfPKfS1_i, @function
_Z40__device_stub__Z13kernel_add_sqPfPKfS1_iPfPKfS1_i:
.LFB2083:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L13
.L9:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L14
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L13:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z13kernel_add_sqPfPKfS1_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L9
.L14:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z40__device_stub__Z13kernel_add_sqPfPKfS1_iPfPKfS1_i, .-_Z40__device_stub__Z13kernel_add_sqPfPKfS1_iPfPKfS1_i
.globl _Z13kernel_add_sqPfPKfS1_i
.type _Z13kernel_add_sqPfPKfS1_i, @function
_Z13kernel_add_sqPfPKfS1_i:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z40__device_stub__Z13kernel_add_sqPfPKfS1_iPfPKfS1_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z13kernel_add_sqPfPKfS1_i, .-_Z13kernel_add_sqPfPKfS1_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "=== sin(i) + cos(i)\n"
.LC2:
.string "%0.2f = %0.2f + %0.2f\n"
.text
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $80, %rsp
.cfi_def_cfa_offset 128
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $4194304, %edi
call malloc@PLT
movq %rax, %r12
movl $4194304, %edi
call malloc@PLT
movq %rax, %rbp
movl $4194304, %edi
call malloc@PLT
movq %rax, %r14
movl $0, %ebx
leaq 8(%rsp), %r13
.L18:
movq %rsp, %rsi
pxor %xmm0, %xmm0
cvtsi2sdl %ebx, %xmm0
movq %r13, %rdi
call sincos@PLT
pxor %xmm0, %xmm0
cvtsd2ss 8(%rsp), %xmm0
movss %xmm0, (%r12,%rbx,4)
pxor %xmm0, %xmm0
cvtsd2ss (%rsp), %xmm0
movss %xmm0, 0(%rbp,%rbx,4)
addq $1, %rbx
cmpq $1048576, %rbx
jne .L18
leaq 24(%rsp), %rdi
movl $4194304, %esi
call cudaMalloc@PLT
movl %eax, %edi
call _Z5CHECK9cudaError
leaq 32(%rsp), %rdi
movl $4194304, %esi
call cudaMalloc@PLT
movl %eax, %edi
call _Z5CHECK9cudaError
leaq 40(%rsp), %rdi
movl $4194304, %esi
call cudaMalloc@PLT
movl %eax, %edi
call _Z5CHECK9cudaError
movl $1, %ecx
movl $4194304, %edx
movq %r12, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %edi
call _Z5CHECK9cudaError
movl $1, %ecx
movl $4194304, %edx
movq %rbp, %rsi
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %edi
call _Z5CHECK9cudaError
movl $256, 60(%rsp)
movl $1, 64(%rsp)
movl $4096, 48(%rsp)
movl $1, 52(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 60(%rsp), %rdx
movl $1, %ecx
movq 48(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L25
.L19:
movl $2, %ecx
movl $4194304, %edx
movq 40(%rsp), %rsi
movq %r14, %rdi
call cudaMemcpy@PLT
movl %eax, %edi
call _Z5CHECK9cudaError
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %ebx
leaq .LC2(%rip), %r13
.L20:
pxor %xmm0, %xmm0
cvtss2sd (%r14,%rbx), %xmm0
pxor %xmm2, %xmm2
cvtss2sd 0(%rbp,%rbx), %xmm2
pxor %xmm1, %xmm1
cvtss2sd (%r12,%rbx), %xmm1
movq %r13, %rsi
movl $2, %edi
movl $3, %eax
call __printf_chk@PLT
addq $131072, %rbx
cmpq $4194304, %rbx
jne .L20
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
movq %r12, %rdi
call free@PLT
movq %rbp, %rdi
call free@PLT
movq %r14, %rdi
call free@PLT
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L26
movl $0, %eax
addq $80, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L25:
.cfi_restore_state
movl $1048576, %ecx
movq 32(%rsp), %rdx
movq 24(%rsp), %rsi
movq 40(%rsp), %rdi
call _Z40__device_stub__Z13kernel_add_sqPfPKfS1_iPfPKfS1_i
jmp .L19
.L26:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.1
.LC3:
.string "_Z13kernel_add_sqPfPKfS1_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z13kernel_add_sqPfPKfS1_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
```
|
```amdasm
.text
.file "trig.hip"
.globl _Z28__device_stub__kernel_add_sqPfPKfS1_i # -- Begin function _Z28__device_stub__kernel_add_sqPfPKfS1_i
.type _Z28__device_stub__kernel_add_sqPfPKfS1_i,@function
_Z28__device_stub__kernel_add_sqPfPKfS1_i: # @_Z28__device_stub__kernel_add_sqPfPKfS1_i
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $112, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 40(%rsp), %rax
movq %rdi, (%rax)
leaq 32(%rsp), %rdi
movq %rsi, (%rdi)
leaq 24(%rsp), %rsi
movq %rdx, (%rsi)
leaq 4(%rsp), %rdx
movl %ecx, (%rdx)
leaq 80(%rsp), %rbx
movq %rax, (%rbx)
movq %rdi, 8(%rbx)
movq %rsi, 16(%rbx)
movq %rdx, 24(%rbx)
leaq 64(%rsp), %r14
leaq 48(%rsp), %r15
leaq 16(%rsp), %r12
leaq 8(%rsp), %r13
movq %r14, %rdi
movq %r15, %rsi
movq %r12, %rdx
movq %r13, %rcx
callq __hipPopCallConfiguration
movq (%r14), %rsi
movl 8(%r14), %edx
movq (%r15), %rcx
movl 8(%r15), %r8d
movl $_Z13kernel_add_sqPfPKfS1_i, %edi
movq %rbx, %r9
pushq (%r13)
.cfi_adjust_cfa_offset 8
pushq (%r12)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $128, %rsp
.cfi_adjust_cfa_offset -128
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z28__device_stub__kernel_add_sqPfPKfS1_i, .Lfunc_end0-_Z28__device_stub__kernel_add_sqPfPKfS1_i
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $32, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $4194304, %edi # imm = 0x400000
callq malloc
movq %rax, %rbx
movl $4194304, %edi # imm = 0x400000
callq malloc
movq %rax, %r14
movl $4194304, %edi # imm = 0x400000
callq malloc
movq %rax, %r15
xorl %r12d, %r12d
.LBB1_1: # =>This Inner Loop Header: Depth=1
xorps %xmm0, %xmm0
cvtsi2sd %r12d, %xmm0
movsd %xmm0, 24(%rsp) # 8-byte Spill
callq sin
cvtsd2ss %xmm0, %xmm0
movss %xmm0, (%rbx,%r12,4)
movsd 24(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
callq cos
cvtsd2ss %xmm0, %xmm0
movss %xmm0, (%r14,%r12,4)
incq %r12
cmpq $1048576, %r12 # imm = 0x100000
jne .LBB1_1
# %bb.2:
leaq 16(%rsp), %rdi
movl $4194304, %esi # imm = 0x400000
callq hipMalloc
testl %eax, %eax
jne .LBB1_13
# %bb.3: # %_Z5CHECK10hipError_t.exit
leaq 8(%rsp), %rdi
movl $4194304, %esi # imm = 0x400000
callq hipMalloc
testl %eax, %eax
jne .LBB1_13
# %bb.4: # %_Z5CHECK10hipError_t.exit34
movq %rsp, %rdi
movl $4194304, %esi # imm = 0x400000
callq hipMalloc
testl %eax, %eax
jne .LBB1_13
# %bb.5: # %_Z5CHECK10hipError_t.exit36
movq 16(%rsp), %rdi
movl $4194304, %edx # imm = 0x400000
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB1_13
# %bb.6: # %_Z5CHECK10hipError_t.exit38
movq 8(%rsp), %rdi
movl $4194304, %edx # imm = 0x400000
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB1_13
# %bb.7: # %_Z5CHECK10hipError_t.exit40
movabsq $4294967552, %rdx # imm = 0x100000100
leaq 3840(%rdx), %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_9
# %bb.8:
movq (%rsp), %rdi
movq 16(%rsp), %rsi
movq 8(%rsp), %rdx
movl $1048576, %ecx # imm = 0x100000
callq _Z28__device_stub__kernel_add_sqPfPKfS1_i
.LBB1_9:
movq (%rsp), %rsi
movl $4194304, %edx # imm = 0x400000
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB1_13
# %bb.10: # %_Z5CHECK10hipError_t.exit42
movl $.Lstr, %edi
callq puts@PLT
movq $-32768, %r12 # imm = 0x8000
.LBB1_11: # =>This Inner Loop Header: Depth=1
xorps %xmm0, %xmm0
cvtss2sd 131072(%r15,%r12,4), %xmm0
xorps %xmm1, %xmm1
cvtss2sd 131072(%rbx,%r12,4), %xmm1
xorps %xmm2, %xmm2
cvtss2sd 131072(%r14,%r12,4), %xmm2
movl $.L.str.1, %edi
movb $3, %al
callq printf
addq $32768, %r12 # imm = 0x8000
cmpq $1015808, %r12 # imm = 0xF8000
jb .LBB1_11
# %bb.12:
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipFree
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
xorl %eax, %eax
addq $32, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB1_13:
.cfi_def_cfa_offset 80
movl %eax, %ebp
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.2, %edi
movl %ebp, %esi
movq %rax, %rdx
xorl %eax, %eax
callq printf
movl $1, %edi
callq exit
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, %rdi
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13kernel_add_sqPfPKfS1_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z13kernel_add_sqPfPKfS1_i,@object # @_Z13kernel_add_sqPfPKfS1_i
.section .rodata,"a",@progbits
.globl _Z13kernel_add_sqPfPKfS1_i
.p2align 3, 0x0
_Z13kernel_add_sqPfPKfS1_i:
.quad _Z28__device_stub__kernel_add_sqPfPKfS1_i
.size _Z13kernel_add_sqPfPKfS1_i, 8
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "%0.2f = %0.2f + %0.2f\n"
.size .L.str.1, 23
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Error: %d %s\n"
.size .L.str.2, 14
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z13kernel_add_sqPfPKfS1_i"
.size .L__unnamed_1, 27
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "=== sin(i) + cos(i)"
.size .Lstr, 20
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z28__device_stub__kernel_add_sqPfPKfS1_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z13kernel_add_sqPfPKfS1_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
```
| 4,032 | 4,309 |
274 |
Convert the following CUDA device assembly code to AMD device assembly:
```cudaasm
code for sm_80
Function : _Z27cuda_rotate_internal_kernelPfPKffii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ;
S2R R6, SR_CTAID.X ;
IADD3 R1, R1, -0x20, RZ ;
S2R R3, SR_TID.X ;
IMAD R6, R6, c[0x0][0x0], R3 ;
ISETP.GE.AND P0, PT, R6, c[0x0][0x178], PT ;
@P0 EXIT ;
IMAD.MOV.U32 R9, RZ, RZ, c[0x0][0x170] ;
I2F R5, c[0x0][0x178] ;
IMAD.MOV.U32 R10, RZ, RZ, 0x3f000000 ;
ULDC UR4, c[0x0][0x174] ;
SHF.R.U32.HI R0, RZ, 0x17, R9 ;
ULDC UR5, c[0x0][0x178] ;
UIMAD UR4, UR4, UR5, URZ ;
LOP3.LUT R0, R0, 0xff, RZ, 0xc0, !PT ;
I2F R3, c[0x0][0x174] ;
ULDC.64 UR6, c[0x0][0x118] ;
IADD3 R7, R0, -0x80, RZ ;
SHF.R.U32.HI R2, RZ, 0x5, R7 ;
LOP3.LUT R7, R7, 0x1f, RZ, 0xc0, !PT ;
IADD3 R8, -R2.reuse, 0x5, RZ ;
IADD3 R4, -R2, 0x4, RZ ;
FFMA R2, R5, R10.reuse, -0.5 ;
IADD3 R11, -R7, 0x20, RZ ;
FMUL R5, R9, 0.63661974668502807617 ;
FFMA R0, R3, R10, -0.5 ;
IMAD.SHL.U32 R10, R9.reuse, 0x100, RZ ;
F2I.NTZ R5, R5 ;
IMAD R3, R8, 0x4, R1.reuse ;
LOP3.LUT R8, R9.reuse, 0x80000000, RZ, 0xc0, !PT ;
IMAD R4, R4, 0x4, R1 ;
LOP3.LUT R9, R9, 0x80000000, RZ, 0xc, !PT ;
LOP3.LUT R10, R10, 0x80000000, RZ, 0xfc, !PT ;
IMAD.MOV.U32 R12, RZ, RZ, c[0x0][0x174] ;
ISETP.GE.AND P0, PT, R12, 0x1, PT ;
@!P0 BRA 0x1770 ;
I2F R20, R5 ;
IMAD.MOV.U32 R13, RZ, RZ, c[0x0][0x170] ;
I2F R15, R6 ;
FFMA R13, R20, -1.5707962512969970703, R13 ;
FFMA R17, R20.reuse, -7.5497894158615963534e-08, R13 ;
IMAD.MOV.U32 R13, RZ, RZ, RZ ;
FADD R12, R15, -R2 ;
FFMA R20, R20, -5.3903029534742383927e-15, R17 ;
IMAD.MOV.U32 R21, RZ, RZ, c[0x0][0x170] ;
I2F R15, R13 ;
IMAD.MOV.U32 R18, RZ, RZ, R5 ;
IMAD.MOV.U32 R19, RZ, RZ, R20 ;
FSETP.GE.AND P0, PT, |R21|, 105615, PT ;
FADD R22, R15, -R0 ;
@!P0 BRA 0x640 ;
FSETP.NEU.AND P1, PT, |R21|, +INF , PT ;
@!P1 BRA 0x620 ;
IMAD.MOV.U32 R19, RZ, RZ, RZ ;
IMAD.MOV.U32 R27, RZ, RZ, RZ ;
IMAD.MOV.U32 R23, RZ, RZ, RZ ;
IMAD.MOV.U32 R14, RZ, RZ, c[0x4][0x0] ;
IMAD.MOV.U32 R15, RZ, RZ, c[0x4][0x4] ;
IMAD.MOV.U32 R18, RZ, RZ, R1 ;
LDG.E.CONSTANT R17, [R14.64] ;
IADD3 R23, R23, 0x1, RZ ;
ISETP.NE.AND P1, PT, R23, 0x6, PT ;
IADD3 R14, P3, R14, 0x4, RZ ;
IADD3.X R15, RZ, R15, RZ, P3, !PT ;
IMAD.WIDE.U32 R16, R17, R10, RZ ;
IADD3 R25, P2, R16, R19, RZ ;
STL [R18], R25 ;
IMAD.X R19, R17, 0x1, R27, P2 ;
IADD3 R18, R18, 0x4, RZ ;
@P1 BRA 0x3b0 ;
ISETP.NE.AND P1, PT, R7, RZ, PT ;
STL [R1+0x18], R19 ;
LDL R18, [R3+0x4] ;
LDL R14, [R3] ;
@P1 LDL R24, [R4] ;
ISETP.NE.AND P2, PT, R8, RZ, PT ;
@P1 SHF.L.U32 R15, R18, R7, RZ ;
@P1 SHF.R.U32.HI R16, RZ, R11, R14 ;
@P1 SHF.L.U32 R17, R14, R7, RZ ;
@P1 SHF.R.U32.HI R24, RZ, R11, R24 ;
@P1 IMAD.IADD R18, R15, 0x1, R16 ;
@P1 IMAD.IADD R14, R24, 0x1, R17 ;
SHF.L.U32.HI R15, R14.reuse, 0x2, R18 ;
IMAD.SHL.U32 R14, R14, 0x4, RZ ;
SHF.R.U32.HI R19, RZ, 0x1f, R15 ;
ISETP.NE.AND P1, PT, R19, RZ, PT ;
LEA.HI R18, R18, R19, RZ, 0x2 ;
SEL R23, R9, R8, P1 ;
IMAD.MOV R19, RZ, RZ, -R18 ;
@P2 IMAD.MOV.U32 R18, RZ, RZ, R19 ;
@P1 LOP3.LUT R15, RZ, R15, RZ, 0x33, !PT ;
@P1 LOP3.LUT R14, RZ, R14, RZ, 0x33, !PT ;
ISETP.NE.AND P1, PT, R23, RZ, PT ;
I2F.F64.S64 R14, R14 ;
DMUL R16, R14, c[0x2][0x0] ;
F2F.F32.F64 R16, R16 ;
FSEL R19, R16, -R16, !P1 ;
BRA 0x640 ;
FMUL R19, RZ, c[0x0][0x170] ;
IMAD.MOV.U32 R18, RZ, RZ, RZ ;
IADD3 R17, R18, 0x1, RZ ;
IMAD.MOV.U32 R23, RZ, RZ, 0x3c0885e4 ;
FMUL R27, R19, R19 ;
LOP3.LUT P2, RZ, R17.reuse, 0x1, RZ, 0xc0, !PT ;
IMAD.MOV.U32 R24, RZ, RZ, 0x3e2aaaa8 ;
LOP3.LUT P1, RZ, R17, 0x2, RZ, 0xc0, !PT ;
IMAD.MOV.U32 R14, RZ, RZ, -0x46b2bead ;
FSEL R15, R23, 0.041666727513074874878, !P2 ;
IMAD.MOV.U32 R18, RZ, RZ, R5 ;
FSEL R17, -R24, -0.4999999701976776123, !P2 ;
@P2 IMAD.MOV.U32 R16, RZ, RZ, 0x37cbac00 ;
@P2 FFMA R14, R27, R16, -0.0013887860113754868507 ;
FSEL R16, R19, 1, !P2 ;
IMAD.MOV.U32 R19, RZ, RZ, R20 ;
FFMA R14, R27.reuse, R14, R15 ;
FFMA R25, R16, R27, RZ ;
FFMA R14, R27, R14, R17 ;
FFMA R25, R14, R25, R16 ;
@P1 FFMA R25, R25, -1, RZ ;
@!P0 BRA 0xa80 ;
FSETP.NEU.AND P1, PT, |R21|, +INF , PT ;
@!P1 BRA 0xa60 ;
CS2R R26, SRZ ;
CS2R R14, SRZ ;
IMAD.SHL.U32 R28, R14.reuse, 0x4, RZ ;
SHF.L.U64.HI R15, R14, 0x2, R15 ;
IADD3 R16, P1, R28, c[0x4][0x0], RZ ;
IADD3.X R17, R15, c[0x4][0x4], RZ, P1, !PT ;
LDG.E.CONSTANT R17, [R16.64] ;
IMAD.IADD R28, R1, 0x1, R28 ;
IADD3 R14, R14, 0x1, RZ ;
ISETP.NE.AND P1, PT, R14, 0x6, PT ;
SHF.R.S32.HI R15, RZ, 0x1f, R14 ;
IMAD.WIDE.U32 R18, R17, R10, RZ ;
IADD3 R29, P2, R18, R26, RZ ;
IADD3.X R26, R19, R27, RZ, P2, !PT ;
STL [R28], R29 ;
@P1 BRA 0x7c0 ;
ISETP.NE.AND P1, PT, R7, RZ, PT ;
STL [R1+0x18], R26 ;
LDL R18, [R3+0x4] ;
LDL R14, [R3] ;
@P1 LDL R28, [R4] ;
ISETP.NE.AND P2, PT, R8, RZ, PT ;
@P1 SHF.L.U32 R15, R18, R7, RZ ;
@P1 SHF.R.U32.HI R16, RZ, R11, R14 ;
@P1 SHF.L.U32 R17, R14, R7, RZ ;
@P1 SHF.R.U32.HI R28, RZ, R11, R28 ;
@P1 IMAD.IADD R18, R15, 0x1, R16 ;
@P1 IMAD.IADD R14, R28, 0x1, R17 ;
SHF.L.U32.HI R15, R14.reuse, 0x2, R18 ;
IMAD.SHL.U32 R14, R14, 0x4, RZ ;
SHF.R.U32.HI R19, RZ, 0x1f, R15 ;
ISETP.NE.AND P1, PT, R19, RZ, PT ;
LEA.HI R18, R18, R19, RZ, 0x2 ;
SEL R26, R9, R8, P1 ;
IMAD.MOV R19, RZ, RZ, -R18 ;
@P2 IMAD.MOV.U32 R18, RZ, RZ, R19 ;
@P1 LOP3.LUT R15, RZ, R15, RZ, 0x33, !PT ;
@P1 LOP3.LUT R14, RZ, R14, RZ, 0x33, !PT ;
ISETP.NE.AND P1, PT, R26, RZ, PT ;
I2F.F64.S64 R14, R14 ;
DMUL R16, R14, c[0x2][0x0] ;
F2F.F32.F64 R16, R16 ;
FSEL R19, R16, -R16, !P1 ;
BRA 0xa80 ;
FMUL R19, RZ, c[0x0][0x170] ;
IMAD.MOV.U32 R18, RZ, RZ, RZ ;
LOP3.LUT P2, RZ, R18.reuse, 0x1, RZ, 0xc0, !PT ;
FMUL R27, R19, R19 ;
LOP3.LUT P1, RZ, R18, 0x2, RZ, 0xc0, !PT ;
IMAD.MOV.U32 R14, RZ, RZ, -0x46b2bead ;
FSEL R15, R23, 0.041666727513074874878, !P2 ;
IMAD.MOV.U32 R18, RZ, RZ, R5 ;
FSEL R17, -R24, -0.4999999701976776123, !P2 ;
@P2 IMAD.MOV.U32 R16, RZ, RZ, 0x37cbac00 ;
@P2 FFMA R14, R27, R16, -0.0013887860113754868507 ;
FSEL R16, R19, 1, !P2 ;
IMAD.MOV.U32 R19, RZ, RZ, R20 ;
FFMA R14, R27.reuse, R14, R15 ;
FFMA R15, R16, R27, RZ ;
FFMA R14, R27, R14, R17 ;
FFMA R15, R14, R15, R16 ;
@P1 FFMA R15, R15, -1, RZ ;
FMUL R15, R12, R15 ;
FFMA R25, R22, R25, -R15 ;
@!P0 BRA 0xeb0 ;
FSETP.NEU.AND P1, PT, |R21|, +INF , PT ;
@!P1 BRA 0xe90 ;
CS2R R26, SRZ ;
CS2R R14, SRZ ;
IMAD.SHL.U32 R28, R14.reuse, 0x4, RZ ;
SHF.L.U64.HI R15, R14, 0x2, R15 ;
IADD3 R16, P1, R28, c[0x4][0x0], RZ ;
IADD3.X R17, R15, c[0x4][0x4], RZ, P1, !PT ;
LDG.E.CONSTANT R17, [R16.64] ;
IMAD.IADD R28, R1, 0x1, R28 ;
IADD3 R14, R14, 0x1, RZ ;
ISETP.NE.AND P1, PT, R14, 0x6, PT ;
SHF.R.S32.HI R15, RZ, 0x1f, R14 ;
IMAD.WIDE.U32 R18, R17, R10, RZ ;
IADD3 R29, P2, R18, R26, RZ ;
STL [R28], R29 ;
IMAD.X R26, R19, 0x1, R27, P2 ;
@P1 BRA 0xbf0 ;
ISETP.NE.AND P1, PT, R7, RZ, PT ;
STL [R1+0x18], R26 ;
LDL R18, [R3+0x4] ;
LDL R14, [R3] ;
@P1 LDL R28, [R4] ;
ISETP.NE.AND P2, PT, R8, RZ, PT ;
@P1 SHF.L.U32 R15, R18, R7, RZ ;
@P1 SHF.R.U32.HI R16, RZ, R11, R14 ;
@P1 SHF.L.U32 R17, R14, R7, RZ ;
@P1 SHF.R.U32.HI R28, RZ, R11, R28 ;
@P1 IMAD.IADD R18, R15, 0x1, R16 ;
@P1 IADD3 R14, R28, R17, RZ ;
SHF.L.U32.HI R15, R14.reuse, 0x2, R18 ;
IMAD.SHL.U32 R14, R14, 0x4, RZ ;
SHF.R.U32.HI R19, RZ, 0x1f, R15 ;
ISETP.NE.AND P1, PT, R19, RZ, PT ;
LEA.HI R18, R18, R19, RZ, 0x2 ;
SEL R26, R9, R8, P1 ;
IMAD.MOV R19, RZ, RZ, -R18 ;
@P2 IMAD.MOV.U32 R18, RZ, RZ, R19 ;
@P1 LOP3.LUT R15, RZ, R15, RZ, 0x33, !PT ;
@P1 LOP3.LUT R14, RZ, R14, RZ, 0x33, !PT ;
ISETP.NE.AND P1, PT, R26, RZ, PT ;
I2F.F64.S64 R14, R14 ;
DMUL R16, R14, c[0x2][0x0] ;
F2F.F32.F64 R16, R16 ;
FSEL R19, R16, -R16, !P1 ;
BRA 0xeb0 ;
FMUL R19, RZ, c[0x0][0x170] ;
IMAD.MOV.U32 R18, RZ, RZ, RZ ;
LOP3.LUT P2, RZ, R18.reuse, 0x1, RZ, 0xc0, !PT ;
FMUL R27, R19, R19 ;
LOP3.LUT P1, RZ, R18, 0x2, RZ, 0xc0, !PT ;
IMAD.MOV.U32 R14, RZ, RZ, -0x46b2bead ;
FSEL R15, R23, 0.041666727513074874878, !P2 ;
IMAD.MOV.U32 R18, RZ, RZ, R5 ;
FSEL R17, -R24, -0.4999999701976776123, !P2 ;
@P2 IMAD.MOV.U32 R16, RZ, RZ, 0x37cbac00 ;
@P2 FFMA R14, R27, R16, -0.0013887860113754868507 ;
FSEL R16, R19, 1, !P2 ;
IMAD.MOV.U32 R19, RZ, RZ, R20 ;
FFMA R14, R27.reuse, R14, R15 ;
FFMA R15, R16, R27, RZ ;
FFMA R14, R27, R14, R17 ;
FFMA R15, R14, R15, R16 ;
@P1 FFMA R15, R15, -1, RZ ;
FMUL R27, R22, R15 ;
@!P0 BRA 0x12e0 ;
FSETP.NEU.AND P0, PT, |R21|, +INF , PT ;
@!P0 BRA 0x12c0 ;
IMAD.MOV.U32 R21, RZ, RZ, RZ ;
CS2R R16, SRZ ;
IMAD.MOV.U32 R29, RZ, RZ, RZ ;
IMAD.SHL.U32 R22, R16.reuse, 0x4, RZ ;
SHF.L.U64.HI R15, R16, 0x2, R17 ;
IADD3 R14, P0, R22, c[0x4][0x0], RZ ;
IADD3.X R15, R15, c[0x4][0x4], RZ, P0, !PT ;
LDG.E.CONSTANT R15, [R14.64] ;
IMAD.IADD R22, R1, 0x1, R22 ;
IADD3 R16, R16, 0x1, RZ ;
ISETP.NE.AND P0, PT, R16, 0x6, PT ;
SHF.R.S32.HI R17, RZ, 0x1f, R16 ;
IMAD.WIDE.U32 R18, R15, R10, RZ ;
IADD3 R18, P1, R18, R21, RZ ;
STL [R22], R18 ;
IMAD.X R21, R19, 0x1, R29, P1 ;
@P0 BRA 0x1020 ;
ISETP.NE.AND P0, PT, R7, RZ, PT ;
STL [R1+0x18], R21 ;
LDL R18, [R3+0x4] ;
LDL R14, [R3] ;
@P0 LDL R22, [R4] ;
ISETP.NE.AND P1, PT, R8, RZ, PT ;
@P0 SHF.L.U32 R15, R18, R7, RZ ;
@P0 SHF.R.U32.HI R16, RZ, R11, R14 ;
@P0 SHF.L.U32 R17, R14, R7, RZ ;
@P0 SHF.R.U32.HI R22, RZ, R11, R22 ;
@P0 IMAD.IADD R18, R15, 0x1, R16 ;
@P0 IADD3 R14, R22, R17, RZ ;
SHF.L.U32.HI R15, R14.reuse, 0x2, R18 ;
IMAD.SHL.U32 R14, R14, 0x4, RZ ;
SHF.R.U32.HI R19, RZ, 0x1f, R15 ;
ISETP.NE.AND P0, PT, R19, RZ, PT ;
LEA.HI R18, R18, R19, RZ, 0x2 ;
SEL R21, R9, R8, P0 ;
IMAD.MOV R19, RZ, RZ, -R18 ;
@P1 IMAD.MOV.U32 R18, RZ, RZ, R19 ;
@P0 LOP3.LUT R15, RZ, R15, RZ, 0x33, !PT ;
@P0 LOP3.LUT R14, RZ, R14, RZ, 0x33, !PT ;
ISETP.NE.AND P0, PT, R21, RZ, PT ;
I2F.F64.S64 R14, R14 ;
DMUL R16, R14, c[0x2][0x0] ;
F2F.F32.F64 R16, R16 ;
FSEL R19, R16, -R16, !P0 ;
BRA 0x12e0 ;
FMUL R19, RZ, c[0x0][0x170] ;
IMAD.MOV.U32 R18, RZ, RZ, RZ ;
IADD3 R15, R18, 0x1, RZ ;
FMUL R21, R19, R19 ;
IMAD.MOV.U32 R14, RZ, RZ, -0x46b2bead ;
LOP3.LUT P1, RZ, R15, 0x1, RZ, 0xc0, !PT ;
FADD R25, R25, R0 ;
LOP3.LUT P0, RZ, R15, 0x2, RZ, 0xc0, !PT ;
FSEL R23, R23, 0.041666727513074874878, !P1 ;
F2I.FLOOR.NTZ R18, R25 ;
FSEL R15, -R24, -0.4999999701976776123, !P1 ;
IMAD.MOV.U32 R24, RZ, RZ, 0x4 ;
@P1 IMAD.MOV.U32 R16, RZ, RZ, 0x37cbac00 ;
@P1 FFMA R14, R21, R16, -0.0013887860113754868507 ;
FSEL R16, R19, 1, !P1 ;
FFMA R14, R21.reuse, R14, R23 ;
FFMA R17, R16, R21, RZ ;
FFMA R14, R21, R14, R15 ;
FFMA R14, R14, R17, R16 ;
@P0 FFMA R14, R14, -1, RZ ;
FFMA R19, R12, R14, R27 ;
FADD R19, R19, R2 ;
F2I.FLOOR.NTZ R21, R19 ;
IMAD R15, R21, c[0x0][0x174], R18 ;
IMAD.WIDE R16, R15.reuse, R24, c[0x0][0x168] ;
ISETP.GE.AND P0, PT, R15, UR4, PT ;
ISETP.LT.OR P0, PT, R15, RZ, P0 ;
@!P0 LDG.E R14, [R16.64] ;
IADD3 R15, R15, 0x1, RZ ;
IMAD.MOV.U32 R22, RZ, RZ, c[0x0][0x174] ;
@!P0 IADD3 R26, R18, 0x1, RZ ;
ISETP.GE.AND P1, PT, R15, UR4, PT ;
ISETP.LT.OR P1, PT, R15, RZ, P1 ;
IMAD R15, R21, R22, c[0x0][0x174] ;
@!P0 I2F R26, R26 ;
IMAD.IADD R23, R18, 0x1, R15 ;
@!P1 LDG.E R27, [R16.64+0x4] ;
ISETP.GE.AND P2, PT, R23.reuse, UR4, PT ;
IMAD.MOV.U32 R22, RZ, RZ, RZ ;
IADD3 R28, R23.reuse, 0x1, RZ ;
ISETP.LT.OR P2, PT, R23, RZ, P2 ;
@!P0 FADD R15, -R25, R26 ;
IMAD R17, R6, c[0x0][0x174], R13 ;
IMAD.WIDE R16, R17, R24, c[0x0][0x160] ;
@!P0 FFMA R22, R15, R14, RZ ;
IMAD.WIDE R14, R23, R24, c[0x0][0x168] ;
ISETP.GE.AND P0, PT, R28.reuse, UR4, PT ;
LDG.E R24, [R16.64] ;
@!P2 LDG.E R23, [R14.64] ;
ISETP.LT.OR P0, PT, R28, RZ, P0 ;
@!P0 LDG.E R26, [R14.64+0x4] ;
@!P1 I2F R28, R18 ;
@!P1 FADD R28, R25, -R28 ;
@!P1 FFMA R22, R28, R27, R22 ;
@!P2 IADD3 R27, R18, 0x1, RZ ;
@!P2 I2F R27, R27 ;
IMAD.MOV.U32 R15, RZ, RZ, RZ ;
IADD3 R14, R21, 0x1, RZ ;
@!P0 I2F R28, R18 ;
@!P2 FADD R29, -R25, R27 ;
I2F R14, R14 ;
@!P0 FADD R28, R25, -R28 ;
IADD3 R13, R13, 0x1, RZ ;
@!P2 FFMA R15, R29, R23, RZ ;
I2F R23, R21 ;
@!P0 FFMA R15, R28, R26, R15 ;
FADD R26, R19.reuse, -R23 ;
FADD R19, -R19, R14 ;
FMUL R26, R26, R15 ;
FFMA R19, R19, R22, R26 ;
FADD R19, R19, R24 ;
STG.E [R16.64], R19 ;
ISETP.GE.AND P0, PT, R13, c[0x0][0x174], PT ;
@P0 CALL.REL.NOINC 0x1770 ;
BRA 0x2c0 ;
IMAD.MOV.U32 R13, RZ, RZ, c[0x0][0x0] ;
IMAD R6, R13, c[0x0][0xc], R6 ;
ISETP.GE.AND P0, PT, R6, c[0x0][0x178], PT ;
@P0 CALL.REL.NOINC 0x17c0 ;
BRA 0x210 ;
EXIT ;
BRA 0x17d0;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
```
|
```amdasm
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z27cuda_rotate_internal_kernelPfPKffii ; -- Begin function _Z27cuda_rotate_internal_kernelPfPKffii
.globl _Z27cuda_rotate_internal_kernelPfPKffii
.p2align 8
.type _Z27cuda_rotate_internal_kernelPfPKffii,@function
_Z27cuda_rotate_internal_kernelPfPKffii: ; @_Z27cuda_rotate_internal_kernelPfPKffii
; %bb.0:
s_clause 0x1
s_load_b32 s8, s[0:1], 0x2c
s_load_b128 s[4:7], s[0:1], 0x10
s_add_u32 s2, s0, 32
s_addc_u32 s3, s1, 0
s_waitcnt lgkmcnt(0)
s_mov_b32 s7, exec_lo
s_and_b32 s12, s8, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s12, v[0:1]
v_cmpx_gt_i32_e64 s6, v1
s_cbranch_execz .LBB0_14
; %bb.1: ; %.preheader.lr.ph
s_and_b32 s13, s4, 0x7fffffff
v_cmp_gt_f32_e64 vcc_lo, 0x48000000, |s4|
s_and_b32 s7, s13, 0x7fffff
s_lshr_b32 s8, s13, 23
s_bitset1_b32 s7, 23
s_addk_i32 s8, 0xff88
s_mul_hi_u32 s9, s7, 0xfe5163ab
s_mul_i32 s10, s7, 0x3c439041
s_mul_hi_u32 s11, s7, 0x3c439041
s_add_u32 s9, s9, s10
s_addc_u32 s10, 0, s11
s_mul_i32 s11, s7, 0xdb629599
s_mul_hi_u32 s14, s7, 0xdb629599
s_add_u32 s10, s10, s11
s_addc_u32 s11, 0, s14
s_mul_i32 s14, s7, 0xf534ddc0
s_mul_hi_u32 s15, s7, 0xf534ddc0
s_add_u32 s11, s11, s14
s_addc_u32 s14, 0, s15
s_mul_i32 s15, s7, 0xfc2757d1
s_mul_hi_u32 s16, s7, 0xfc2757d1
s_add_u32 s14, s14, s15
s_addc_u32 s15, 0, s16
s_mul_i32 s16, s7, 0x4e441529
s_mul_hi_u32 s17, s7, 0x4e441529
s_add_u32 s15, s15, s16
s_addc_u32 s16, 0, s17
s_cmp_gt_u32 s8, 63
s_mul_i32 s17, s7, 0xfe5163ab
s_mul_hi_u32 s18, s7, 0xa2f9836e
s_mul_i32 s7, s7, 0xa2f9836e
s_cselect_b32 s19, s10, s14
s_cselect_b32 s9, s9, s11
s_cselect_b32 s10, s17, s10
s_add_u32 s7, s16, s7
s_addc_u32 s16, 0, s18
s_cmp_gt_u32 s8, 63
s_load_b32 s2, s[2:3], 0x0
s_cselect_b32 s17, 0xffffffc0, 0
s_cselect_b32 s11, s11, s15
s_cselect_b32 s14, s14, s7
s_cselect_b32 s15, s15, s16
s_cmp_gt_i32 s5, 0
s_mul_i32 s3, s6, s5
s_cselect_b32 s7, -1, 0
s_add_i32 s17, s17, s8
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_gt_u32 s17, 31
s_cselect_b32 s8, 0xffffffe0, 0
s_cselect_b32 s16, s11, s14
s_cselect_b32 s14, s14, s15
s_cselect_b32 s11, s19, s11
s_cselect_b32 s15, s9, s19
s_cselect_b32 s9, s10, s9
s_add_i32 s8, s8, s17
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_gt_u32 s8, 31
s_waitcnt lgkmcnt(0)
s_mul_i32 s2, s2, s12
s_cselect_b32 s10, 0xffffffe0, 0
s_cselect_b32 s14, s16, s14
s_cselect_b32 s16, s11, s16
s_cselect_b32 s11, s15, s11
s_cselect_b32 s9, s9, s15
s_add_i32 s10, s10, s8
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
s_sub_i32 s8, 32, s10
s_cmp_eq_u32 s10, 0
v_mov_b32_e32 v0, s8
s_cselect_b32 s10, -1, 0
v_alignbit_b32 v2, s14, s16, v0
v_alignbit_b32 v3, s16, s11, v0
v_alignbit_b32 v0, s11, s9, v0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_readfirstlane_b32 s8, v2
v_cndmask_b32_e64 v2, v3, s16, s10
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cndmask_b32_e64 v0, v0, s11, s10
s_cselect_b32 s8, s14, s8
s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
v_alignbit_b32 v3, s8, v2, 30
s_bfe_u32 s14, s8, 0x1001d
s_delay_alu instid0(VALU_DEP_2)
v_alignbit_b32 v2, v2, v0, 30
s_sub_i32 s15, 0, s14
v_alignbit_b32 v0, v0, s9, 30
v_xor_b32_e32 v3, s15, v3
s_lshr_b32 s9, s8, 29
v_xor_b32_e32 v2, s15, v2
s_lshl_b32 s9, s9, 31
v_xor_b32_e32 v0, s15, v0
v_clz_i32_u32_e32 v4, v3
s_or_b32 s10, s9, 0.5
s_lshr_b32 s8, s8, 30
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_add_i32 s14, s14, s8
v_min_u32_e32 v4, 32, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v5, 31, v4
v_lshlrev_b32_e32 v6, 23, v4
v_alignbit_b32 v3, v3, v2, v5
v_alignbit_b32 v0, v2, v0, v5
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v6, s10, v6
s_mov_b32 s10, 0x37d75334
v_alignbit_b32 v2, v3, v0, 9
v_lshrrev_b32_e32 v3, 9, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_clz_i32_u32_e32 v5, v2
v_min_u32_e32 v5, 32, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v7, 31, v5
v_add_nc_u32_e32 v4, v5, v4
v_alignbit_b32 v0, v2, v0, v7
v_or_b32_e32 v2, v3, v6
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_lshlrev_b32_e32 v3, 23, v4
v_mul_f32_e64 v4, 0x3f22f983, |s4|
v_lshrrev_b32_e32 v0, 9, v0
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_f32_e32 v5, 0x3fc90fda, v2
v_sub_nc_u32_e32 v0, v0, v3
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_rndne_f32_e32 v3, v4
v_fma_f32 v4, 0x3fc90fda, v2, -v5
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_nc_u32_e32 v0, 0x33000000, v0
v_fma_f32 v6, 0xbfc90fda, v3, |s4|
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_fmamk_f32 v2, v2, 0x33a22168, v4
v_or_b32_e32 v0, s9, v0
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_fmamk_f32 v4, v3, 0xb3a22168, v6
s_mov_b32 s9, 0xb94c1982
v_fmac_f32_e32 v2, 0x3fc90fda, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_fmamk_f32 v0, v3, 0xa7c234c4, v4
v_cvt_i32_f32_e32 v3, v3
v_dual_add_f32 v2, v5, v2 :: v_dual_cndmask_b32 v3, s14, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v0, v2, v0, vcc_lo
v_and_b32_e32 v6, 1, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_f32_e32 v2, v0, v0
v_cmp_eq_u32_e32 vcc_lo, 0, v6
v_cvt_f32_i32_e32 v6, s6
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_2)
v_fmaak_f32 v4, s9, v2, 0x3c0881c4
v_fmaak_f32 v5, s10, v2, 0xbab64f3b
s_load_b128 s[8:11], s[0:1], 0x0
s_mov_b32 s1, 0
v_fmaak_f32 v4, v2, v4, 0xbe2aaa9d
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fmaak_f32 v5, v2, v5, 0x3d2aabf7
v_mul_f32_e32 v4, v2, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_fmaak_f32 v5, v2, v5, 0xbf000004 :: v_dual_fmac_f32 v0, v0, v4
v_fma_f32 v2, v2, v5, 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_4)
v_cndmask_b32_e64 v4, -v0, v2, vcc_lo
v_cndmask_b32_e32 v0, v2, v0, vcc_lo
v_lshlrev_b32_e32 v2, 30, v3
v_cvt_f32_i32_e32 v3, s5
v_cmp_class_f32_e64 vcc_lo, s4, 0x1f8
v_xor_b32_e32 v0, s4, v0
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_and_b32_e32 v2, 0x80000000, v2
s_mul_i32 s4, s2, s5
v_xor_b32_e32 v5, s13, v0
s_delay_alu instid0(VALU_DEP_2)
v_xor_b32_e32 v7, v2, v4
v_mul_lo_u32 v0, s5, v1
v_fma_f32 v4, v3, 0.5, -0.5
v_mov_b32_e32 v3, 0
v_xor_b32_e32 v2, v5, v2
v_fma_f32 v5, v6, 0.5, -0.5
v_cndmask_b32_e32 v6, 0x7fc00000, v7, vcc_lo
s_delay_alu instid0(VALU_DEP_3)
v_cndmask_b32_e32 v7, 0x7fc00000, v2, vcc_lo
.LBB0_2: ; %.preheader
; =>This Loop Header: Depth=1
; Child Loop BB0_4 Depth 2
s_and_not1_b32 vcc_lo, exec_lo, s7
s_cbranch_vccnz .LBB0_13
; %bb.3: ; %.lr.ph
; in Loop: Header=BB0_2 Depth=1
v_cvt_f32_i32_e32 v2, v1
s_mov_b32 s12, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_f32_e32 v2, v2, v5
v_mul_f32_e32 v8, v2, v7
v_mul_f32_e32 v9, v2, v6
.LBB0_4: ; %_ZL4cosff.exit
; Parent Loop BB0_2 Depth=1
; => This Inner Loop Header: Depth=2
v_cvt_f32_i32_e32 v2, s12
v_mov_b32_e32 v12, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_f32_e32 v2, v2, v4
v_fma_f32 v10, v2, v7, v9
v_fma_f32 v2, v2, v6, -v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v15, v4, v2
v_floor_f32_e32 v2, v15
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_i32_f32_e32 v16, v2
v_dual_add_f32 v10, v5, v10 :: v_dual_add_nc_u32 v13, 1, v16
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_floor_f32_e32 v11, v10
v_cvt_f32_i32_e32 v14, v13
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_i32_f32_e32 v11, v11
v_mul_lo_u32 v17, v11, s5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_nc_u32_e32 v2, v17, v16
v_sub_f32_e32 v14, v14, v15
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_lt_i32_e32 vcc_lo, -1, v2
v_cmp_gt_i32_e64 s0, s3, v2
s_and_b32 s13, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s0, s13
s_cbranch_execz .LBB0_6
; %bb.5: ; in Loop: Header=BB0_4 Depth=2
v_lshlrev_b64 v[18:19], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v18, vcc_lo, s10, v18
v_add_co_ci_u32_e32 v19, vcc_lo, s11, v19, vcc_lo
global_load_b32 v2, v[18:19], off
s_waitcnt vmcnt(0)
v_fma_f32 v12, v14, v2, 0
.LBB0_6: ; in Loop: Header=BB0_4 Depth=2
s_or_b32 exec_lo, exec_lo, s0
v_cvt_f32_i32_e32 v18, v16
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_sub_f32 v15, v15, v18 :: v_dual_add_nc_u32 v2, v17, v13
v_cmp_lt_i32_e32 vcc_lo, -1, v2
v_cmp_gt_i32_e64 s0, s3, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s13, vcc_lo, s0
s_and_saveexec_b32 s0, s13
s_cbranch_execz .LBB0_8
; %bb.7: ; in Loop: Header=BB0_4 Depth=2
v_lshlrev_b64 v[18:19], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v18, vcc_lo, s10, v18
v_add_co_ci_u32_e32 v19, vcc_lo, s11, v19, vcc_lo
global_load_b32 v2, v[18:19], off
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v12, v15, v2
.LBB0_8: ; in Loop: Header=BB0_4 Depth=2
s_or_b32 exec_lo, exec_lo, s0
v_add_nc_u32_e32 v17, s5, v17
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v2, v17, v16
v_mov_b32_e32 v16, 0
v_cmp_lt_i32_e32 vcc_lo, -1, v2
v_cmp_gt_i32_e64 s0, s3, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s13, vcc_lo, s0
s_and_saveexec_b32 s0, s13
s_cbranch_execz .LBB0_10
; %bb.9: ; in Loop: Header=BB0_4 Depth=2
v_lshlrev_b64 v[18:19], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v18, vcc_lo, s10, v18
v_add_co_ci_u32_e32 v19, vcc_lo, s11, v19, vcc_lo
global_load_b32 v2, v[18:19], off
s_waitcnt vmcnt(0)
v_fma_f32 v16, v14, v2, 0
.LBB0_10: ; in Loop: Header=BB0_4 Depth=2
s_or_b32 exec_lo, exec_lo, s0
v_add_nc_u32_e32 v2, v17, v13
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_lt_i32_e32 vcc_lo, -1, v2
v_cmp_gt_i32_e64 s0, s3, v2
s_and_b32 s13, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s0, s13
s_cbranch_execz .LBB0_12
; %bb.11: ; in Loop: Header=BB0_4 Depth=2
v_lshlrev_b64 v[13:14], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v13, vcc_lo, s10, v13
v_add_co_ci_u32_e32 v14, vcc_lo, s11, v14, vcc_lo
global_load_b32 v2, v[13:14], off
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v16, v15, v2
.LBB0_12: ; in Loop: Header=BB0_4 Depth=2
s_or_b32 exec_lo, exec_lo, s0
v_add_nc_u32_e32 v15, 1, v11
v_cvt_f32_i32_e32 v11, v11
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_cvt_f32_i32_e32 v15, v15
v_add_nc_u32_e32 v13, s12, v0
v_sub_f32_e32 v11, v10, v11
s_add_i32 s12, s12, 1
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_sub_f32_e32 v10, v15, v10
v_ashrrev_i32_e32 v14, 31, v13
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_f32_e32 v11, v11, v16
s_cmp_eq_u32 s5, s12
v_lshlrev_b64 v[13:14], 2, v[13:14]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_fmac_f32_e32 v11, v10, v12
s_waitcnt lgkmcnt(0)
v_add_co_u32 v13, vcc_lo, s8, v13
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v14, vcc_lo, s9, v14, vcc_lo
global_load_b32 v2, v[13:14], off
s_waitcnt vmcnt(0)
v_add_f32_e32 v2, v2, v11
global_store_b32 v[13:14], v2, off
s_cbranch_scc0 .LBB0_4
.LBB0_13: ; %._crit_edge
; in Loop: Header=BB0_2 Depth=1
v_add_nc_u32_e32 v1, s2, v1
v_add_nc_u32_e32 v0, s4, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_le_i32_e32 vcc_lo, s6, v1
s_or_b32 s1, vcc_lo, s1
s_and_not1_b32 exec_lo, exec_lo, s1
s_cbranch_execnz .LBB0_2
.LBB0_14: ; %._crit_edge129
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z27cuda_rotate_internal_kernelPfPKffii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 20
.amdhsa_next_free_sgpr 20
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z27cuda_rotate_internal_kernelPfPKffii, .Lfunc_end0-_Z27cuda_rotate_internal_kernelPfPKffii
; -- End function
.section .AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1696
; NumSgprs: 22
; NumVgprs: 20
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 2
; NumSGPRsForWavesPerEU: 22
; NumVGPRsForWavesPerEU: 20
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object ; @__hip_cuid_
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0 ; 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z27cuda_rotate_internal_kernelPfPKffii
.private_segment_fixed_size: 0
.sgpr_count: 22
.sgpr_spill_count: 0
.symbol: _Z27cuda_rotate_internal_kernelPfPKffii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 20
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
```
| 8,169 | 9,101 |
275 |
Convert the following CUDA host assembly code to AMD host assembly:
```cudaasm
.file "tmpxft_0008841f_00000000-6_cuda_rotate_internal_kernel.cudafe1.cpp"
.text
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z53__device_stub__Z27cuda_rotate_internal_kernelPfPKffiiPfPKffii
.type _Z53__device_stub__Z27cuda_rotate_internal_kernelPfPKffiiPfPKffii, @function
_Z53__device_stub__Z27cuda_rotate_internal_kernelPfPKffiiPfPKffii:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movss %xmm0, 12(%rsp)
movl %edx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 4(%rsp), %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z27cuda_rotate_internal_kernelPfPKffii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z53__device_stub__Z27cuda_rotate_internal_kernelPfPKffiiPfPKffii, .-_Z53__device_stub__Z27cuda_rotate_internal_kernelPfPKffiiPfPKffii
.globl _Z27cuda_rotate_internal_kernelPfPKffii
.type _Z27cuda_rotate_internal_kernelPfPKffii, @function
_Z27cuda_rotate_internal_kernelPfPKffii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z53__device_stub__Z27cuda_rotate_internal_kernelPfPKffiiPfPKffii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z27cuda_rotate_internal_kernelPfPKffii, .-_Z27cuda_rotate_internal_kernelPfPKffii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z27cuda_rotate_internal_kernelPfPKffii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z27cuda_rotate_internal_kernelPfPKffii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
```
|
```amdasm
.text
.file "cuda_rotate_internal_kernel.hip"
.globl _Z42__device_stub__cuda_rotate_internal_kernelPfPKffii # -- Begin function _Z42__device_stub__cuda_rotate_internal_kernelPfPKffii
.type _Z42__device_stub__cuda_rotate_internal_kernelPfPKffii,@function
_Z42__device_stub__cuda_rotate_internal_kernelPfPKffii: # @_Z42__device_stub__cuda_rotate_internal_kernelPfPKffii
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $128, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 40(%rsp), %rax
movq %rdi, (%rax)
leaq 32(%rsp), %rdi
movq %rsi, (%rdi)
leaq 12(%rsp), %rsi
movss %xmm0, (%rsi)
leaq 8(%rsp), %r8
movl %edx, (%r8)
leaq 4(%rsp), %rdx
movl %ecx, (%rdx)
leaq 80(%rsp), %rbx
movq %rax, (%rbx)
movq %rdi, 8(%rbx)
movq %rsi, 16(%rbx)
movq %r8, 24(%rbx)
movq %rdx, 32(%rbx)
leaq 64(%rsp), %r14
leaq 48(%rsp), %r15
leaq 24(%rsp), %r12
leaq 16(%rsp), %r13
movq %r14, %rdi
movq %r15, %rsi
movq %r12, %rdx
movq %r13, %rcx
callq __hipPopCallConfiguration
movq (%r14), %rsi
movl 8(%r14), %edx
movq (%r15), %rcx
movl 8(%r15), %r8d
movl $_Z27cuda_rotate_internal_kernelPfPKffii, %edi
movq %rbx, %r9
pushq (%r13)
.cfi_adjust_cfa_offset 8
pushq (%r12)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $144, %rsp
.cfi_adjust_cfa_offset -144
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z42__device_stub__cuda_rotate_internal_kernelPfPKffii, .Lfunc_end0-_Z42__device_stub__cuda_rotate_internal_kernelPfPKffii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, %rdi
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z27cuda_rotate_internal_kernelPfPKffii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z27cuda_rotate_internal_kernelPfPKffii,@object # @_Z27cuda_rotate_internal_kernelPfPKffii
.section .rodata,"a",@progbits
.globl _Z27cuda_rotate_internal_kernelPfPKffii
.p2align 3, 0x0
_Z27cuda_rotate_internal_kernelPfPKffii:
.quad _Z42__device_stub__cuda_rotate_internal_kernelPfPKffii
.size _Z27cuda_rotate_internal_kernelPfPKffii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z27cuda_rotate_internal_kernelPfPKffii"
.size .L__unnamed_1, 40
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z42__device_stub__cuda_rotate_internal_kernelPfPKffii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z27cuda_rotate_internal_kernelPfPKffii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
```
| 1,976 | 2,156 |
280 |
Convert the following CUDA device assembly code to AMD device assembly:
```cudaasm
code for sm_80
Function : _Z4testv
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
MOV R1, c[0x0][0x28] ;
EXIT ;
BRA 0x20;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
```
|
```amdasm
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z4testv ; -- Begin function _Z4testv
.globl _Z4testv
.p2align 8
.type _Z4testv,@function
_Z4testv: ; @_Z4testv
; %bb.0:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z4testv
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 0
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 0
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 1
.amdhsa_next_free_sgpr 1
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z4testv, .Lfunc_end0-_Z4testv
; -- End function
.section .AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 4
; NumSgprs: 0
; NumVgprs: 0
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 0
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 1
; NumVGPRsForWavesPerEU: 1
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object ; @__hip_cuid_
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0 ; 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args: []
.group_segment_fixed_size: 0
.kernarg_segment_align: 4
.kernarg_segment_size: 0
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z4testv
.private_segment_fixed_size: 0
.sgpr_count: 0
.sgpr_spill_count: 0
.symbol: _Z4testv.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 0
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
```
| 118 | 1,457 |
281 |
Convert the following CUDA host assembly code to AMD host assembly:
```cudaasm
.file "tmpxft_000e0f4f_00000000-6_test.cudafe1.cpp"
.text
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2030:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl cutest
.type cutest, @function
cutest:
.LFB2027:
.cfi_startproc
endbr64
ret
.cfi_endproc
.LFE2027:
.size cutest, .-cutest
.globl _Z22__device_stub__Z4testvv
.type _Z22__device_stub__Z4testvv, @function
_Z22__device_stub__Z4testvv:
.LFB2052:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L8
.L4:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L9
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L8:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z4testv(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L4
.L9:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2052:
.size _Z22__device_stub__Z4testvv, .-_Z22__device_stub__Z4testvv
.globl _Z4testv
.type _Z4testv, @function
_Z4testv:
.LFB2053:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z22__device_stub__Z4testvv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2053:
.size _Z4testv, .-_Z4testv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z4testv"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2055:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z4testv(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2055:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
```
|
```amdasm
.text
.file "test.hip"
.globl _Z19__device_stub__testv # -- Begin function _Z19__device_stub__testv
.type _Z19__device_stub__testv,@function
_Z19__device_stub__testv: # @_Z19__device_stub__testv
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $56, %rsp
.cfi_def_cfa_offset 96
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 40(%rsp), %rbx
leaq 24(%rsp), %r14
leaq 16(%rsp), %r15
leaq 8(%rsp), %r12
movq %rbx, %rdi
movq %r14, %rsi
movq %r15, %rdx
movq %r12, %rcx
callq __hipPopCallConfiguration
movq (%rbx), %rsi
movl 8(%rbx), %edx
movq (%r14), %rcx
movl 8(%r14), %r8d
movq %rsp, %r9
movl $_Z4testv, %edi
pushq (%r12)
.cfi_adjust_cfa_offset 8
pushq (%r15)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z19__device_stub__testv, .Lfunc_end0-_Z19__device_stub__testv
.cfi_endproc
# -- End function
.globl cutest # -- Begin function cutest
.type cutest,@function
cutest: # @cutest
.cfi_startproc
# %bb.0:
retq
.Lfunc_end1:
.size cutest, .Lfunc_end1-cutest
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, %rdi
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z4testv, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z4testv,@object # @_Z4testv
.section .rodata,"a",@progbits
.globl _Z4testv
.p2align 3, 0x0
_Z4testv:
.quad _Z19__device_stub__testv
.size _Z4testv, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z4testv"
.size .L__unnamed_1, 9
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z19__device_stub__testv
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z4testv
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
```
| 1,693 | 1,844 |
284 |
Convert the following CUDA device assembly code to AMD device assembly:
```cudaasm
code for sm_80
Function : _Z7reduce1PiS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ;
S2R R6, SR_CTAID.X ;
HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ;
ULDC.64 UR6, c[0x0][0x118] ;
S2R R7, SR_TID.X ;
IMAD R2, R6, c[0x0][0x0], R7 ;
IMAD.WIDE.U32 R2, R2, R3, c[0x0][0x160] ;
LDG.E R2, [R2.64] ;
ULDC UR4, c[0x0][0x0] ;
ISETP.NE.AND P0, PT, R7, RZ, PT ;
USHF.R.U32.HI UR4, URZ, 0x1, UR4 ;
ISETP.NE.AND P1, PT, RZ, UR4, PT ;
STS [R7.X4], R2 ;
BAR.SYNC.DEFER_BLOCKING 0x0 ;
@!P1 BRA 0x1b0 ;
IMAD.SHL.U32 R0, R7, 0x4, RZ ;
MOV R3, UR4 ;
ISETP.GE.U32.AND P1, PT, R7, R3, PT ;
@!P1 IMAD R2, R3, 0x4, R0 ;
@!P1 LDS R4, [R7.X4] ;
SHF.R.U32.HI R3, RZ, 0x1, R3 ;
@!P1 LDS R5, [R2] ;
@!P1 IADD3 R4, R4, R5, RZ ;
@!P1 STS [R7.X4], R4 ;
BAR.SYNC.DEFER_BLOCKING 0x0 ;
ISETP.NE.AND P1, PT, R3, RZ, PT ;
@P1 BRA 0x110 ;
@P0 EXIT ;
LDS R5, [RZ] ;
IMAD.MOV.U32 R3, RZ, RZ, 0x4 ;
IMAD.WIDE.U32 R2, R6, R3, c[0x0][0x168] ;
STG.E [R2.64], R5 ;
EXIT ;
BRA 0x210;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
```
|
```amdasm
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z7reduce1PiS_ ; -- Begin function _Z7reduce1PiS_
.globl _Z7reduce1PiS_
.p2align 8
.type _Z7reduce1PiS_,@function
_Z7reduce1PiS_: ; @_Z7reduce1PiS_
; %bb.0:
s_clause 0x1
s_load_b32 s5, s[0:1], 0x1c
s_load_b128 s[0:3], s[0:1], 0x0
s_mov_b32 s4, s15
s_waitcnt lgkmcnt(0)
s_and_b32 s5, s5, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s4, s5, v[0:1]
v_mov_b32_e32 v2, 0
s_cmp_lt_u32 s5, 2
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v1, vcc_lo, s0, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
global_load_b32 v2, v[1:2], off
v_lshl_add_u32 v1, v0, 2, 0
s_waitcnt vmcnt(0)
ds_store_b32 v1, v2
s_waitcnt lgkmcnt(0)
s_barrier
.LBB0_1: ; =>This Inner Loop Header: Depth=1
buffer_gl0_inv
s_cbranch_scc1 .LBB0_5
; %bb.2: ; %.lr.ph
; in Loop: Header=BB0_1 Depth=1
s_lshr_b32 s0, s5, 1
s_mov_b32 s1, exec_lo
v_cmpx_gt_u32_e64 s0, v0
s_cbranch_execz .LBB0_4
; %bb.3: ; in Loop: Header=BB0_1 Depth=1
v_lshl_add_u32 v2, s0, 2, v1
ds_load_b32 v2, v2
ds_load_b32 v3, v1
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v2, v3, v2
ds_store_b32 v1, v2
.LBB0_4: ; in Loop: Header=BB0_1 Depth=1
s_or_b32 exec_lo, exec_lo, s1
s_waitcnt lgkmcnt(0)
s_barrier
s_cmp_lt_u32 s5, 4
s_mov_b32 s5, s0
s_branch .LBB0_1
.LBB0_5: ; %._crit_edge
s_mov_b32 s0, exec_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB0_7
; %bb.6:
v_mov_b32_e32 v0, 0
s_mov_b32 s5, 0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_lshl_b64 s[0:1], s[4:5], 2
s_add_u32 s0, s2, s0
ds_load_b32 v1, v0
s_addc_u32 s1, s3, s1
s_waitcnt lgkmcnt(0)
global_store_b32 v0, v1, s[0:1]
.LBB0_7:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z7reduce1PiS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z7reduce1PiS_, .Lfunc_end0-_Z7reduce1PiS_
; -- End function
.section .AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 280
; NumSgprs: 18
; NumVgprs: 4
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 4
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object ; @__hip_cuid_
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0 ; 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
- .offset: 136
.size: 4
.value_kind: hidden_dynamic_lds_size
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z7reduce1PiS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z7reduce1PiS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
```
| 668 | 2,827 |
285 |
Convert the following CUDA host assembly code to AMD host assembly:
```cudaasm
.file "tmpxft_00012d9a_00000000-6_sequential_addressing.cudafe1.cpp"
.text
.globl _ZSt21ios_base_library_initv
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z28__device_stub__Z7reduce1PiS_PiS_
.type _Z28__device_stub__Z7reduce1PiS_PiS_, @function
_Z28__device_stub__Z7reduce1PiS_PiS_:
.LFB3694:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z7reduce1PiS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3694:
.size _Z28__device_stub__Z7reduce1PiS_PiS_, .-_Z28__device_stub__Z7reduce1PiS_PiS_
.globl _Z7reduce1PiS_
.type _Z7reduce1PiS_, @function
_Z7reduce1PiS_:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z28__device_stub__Z7reduce1PiS_PiS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _Z7reduce1PiS_, .-_Z7reduce1PiS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "final result = "
.LC1:
.string "\n"
.text
.globl main
.type main, @function
main:
.LFB3669:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $48, %rsp
.cfi_def_cfa_offset 64
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movq %rsp, %rdi
movl $1, %edx
movl $1073741824, %esi
call cudaMallocManaged@PLT
leaq 8(%rsp), %rdi
movl $1, %edx
movl $1073741824, %esi
call cudaMallocManaged@PLT
movl $0, %eax
.L12:
movq (%rsp), %rdx
movl $2, (%rdx,%rax)
movq 8(%rsp), %rdx
movl $0, (%rdx,%rax)
addq $4, %rax
cmpq $1073741824, %rax
jne .L12
movl $128, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $2097152, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $0, %r9d
movl $512, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L19
.L13:
call cudaDeviceSynchronize@PLT
movq 8(%rsp), %rax
leaq 8388608(%rax), %rcx
movl $0, %edx
.L14:
movl %edx, %ebx
addl (%rax), %ebx
movl %ebx, %edx
addq $4, %rax
cmpq %rcx, %rax
jne .L14
leaq .LC0(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl %ebx, %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
leaq .LC1(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq (%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L20
movl $0, %eax
addq $48, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
movq 8(%rsp), %rsi
movq (%rsp), %rdi
call _Z28__device_stub__Z7reduce1PiS_PiS_
jmp .L13
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size main, .-main
.section .rodata.str1.1
.LC2:
.string "_Z7reduce1PiS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3697:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z7reduce1PiS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
```
|
```amdasm
.text
.file "sequential_addressing.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z22__device_stub__reduce1PiS_ # -- Begin function _Z22__device_stub__reduce1PiS_
.type _Z22__device_stub__reduce1PiS_,@function
_Z22__device_stub__reduce1PiS_: # @_Z22__device_stub__reduce1PiS_
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $80, %rsp
.cfi_def_cfa_offset 128
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 24(%rsp), %rax
movq %rdi, (%rax)
leaq 16(%rsp), %rcx
movq %rsi, (%rcx)
leaq 64(%rsp), %rbx
movq %rax, (%rbx)
movq %rcx, 8(%rbx)
leaq 48(%rsp), %r14
leaq 32(%rsp), %r15
leaq 8(%rsp), %r12
movq %rsp, %r13
movq %r14, %rdi
movq %r15, %rsi
movq %r12, %rdx
movq %r13, %rcx
callq __hipPopCallConfiguration
movq (%r14), %rsi
movl 8(%r14), %edx
movq (%r15), %rcx
movl 8(%r15), %r8d
movl $_Z7reduce1PiS_, %edi
movq %rbx, %r9
pushq (%r13)
.cfi_adjust_cfa_offset 8
pushq (%r12)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $96, %rsp
.cfi_adjust_cfa_offset -96
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z22__device_stub__reduce1PiS_, .Lfunc_end0-_Z22__device_stub__reduce1PiS_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $24, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
leaq 16(%rsp), %rbx
movl $1073741824, %esi # imm = 0x40000000
movq %rbx, %rdi
movl $1, %edx
callq hipMallocManaged
leaq 8(%rsp), %r14
movl $1073741824, %esi # imm = 0x40000000
movq %r14, %rdi
movl $1, %edx
callq hipMallocManaged
movq (%rbx), %rax
xorl %ecx, %ecx
movq (%r14), %rdx
.LBB1_1: # =>This Inner Loop Header: Depth=1
movl $2, (%rax,%rcx,4)
movl $0, (%rdx,%rcx,4)
incq %rcx
cmpq $268435456, %rcx # imm = 0x10000000
jne .LBB1_1
# %bb.2:
movabsq $4294967424, %rdx # imm = 0x100000080
leaq 2097024(%rdx), %rdi
xorl %ebx, %ebx
movl $512, %r8d # imm = 0x200
movl $1, %esi
movl $1, %ecx
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq 16(%rsp), %rdi
movq 8(%rsp), %rsi
callq _Z22__device_stub__reduce1PiS_
.LBB1_4:
callq hipDeviceSynchronize
movq 8(%rsp), %rax
xorl %ecx, %ecx
.LBB1_5: # =>This Inner Loop Header: Depth=1
addl (%rax,%rcx,4), %ebx
incq %rcx
cmpq $2097152, %rcx # imm = 0x200000
jne .LBB1_5
# %bb.6:
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $15, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl %ebx, %esi
callq _ZNSolsEi
movl $.L.str.1, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $24, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, %rdi
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7reduce1PiS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z7reduce1PiS_,@object # @_Z7reduce1PiS_
.section .rodata,"a",@progbits
.globl _Z7reduce1PiS_
.p2align 3, 0x0
_Z7reduce1PiS_:
.quad _Z22__device_stub__reduce1PiS_
.size _Z7reduce1PiS_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "final result = "
.size .L.str, 16
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "\n"
.size .L.str.1, 2
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z7reduce1PiS_"
.size .L__unnamed_1, 15
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__reduce1PiS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z7reduce1PiS_
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
```
| 2,753 | 3,077 |
290 |
Convert the following CUDA device assembly code to AMD device assembly:
```cudaasm
code for sm_80
Function : _Z24k_reorder_send_buf_totaliiPjS_P6float4S1_S1_S1_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ;
S2R R0, SR_CTAID.X ;
S2R R3, SR_TID.X ;
IMAD R0, R0, 0x200, R3 ;
ISETP.GE.AND P0, PT, R0, c[0x0][0x160], PT ;
@P0 EXIT ;
IMAD.MOV.U32 R3, RZ, RZ, 0x4 ;
ULDC.64 UR4, c[0x0][0x118] ;
IMAD.WIDE R2, R0, R3, c[0x0][0x168] ;
LDG.E R2, [R2.64] ;
ISETP.NE.AND P0, PT, R2, 0xa, PT ;
@P0 EXIT ;
SHF.R.S32.HI R3, RZ, 0x1f, R0 ;
IMAD.SHL.U32 R12, R0.reuse, 0x10, RZ ;
LEA R10, P0, R0, c[0x0][0x170], 0x2 ;
LEA.HI.X R11, R0.reuse, c[0x0][0x174], R3.reuse, 0x2, P0 ;
SHF.L.U64.HI R0, R0, 0x4, R3 ;
IADD3 R4, P0, R12, c[0x0][0x178], RZ ;
LDG.E R10, [R10.64] ;
IADD3.X R5, R0, c[0x0][0x17c], RZ, P0, !PT ;
LDG.E.128 R4, [R4.64] ;
IMAD.MOV.U32 R9, RZ, RZ, 0x10 ;
IADD3 R12, P0, R12, c[0x0][0x180], RZ ;
IADD3.X R13, R0, c[0x0][0x184], RZ, P0, !PT ;
IMAD.WIDE R2, R10, R9, c[0x0][0x188] ;
STG.E.128 [R2.64], R4 ;
LDG.E.128 R12, [R12.64] ;
IMAD.WIDE R8, R10, R9, c[0x0][0x190] ;
STG.E.128 [R8.64], R12 ;
EXIT ;
BRA 0x1e0;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
```
|
```amdasm
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.section .text._ZL24k_reorder_send_buf_totaliiPjS_P15HIP_vector_typeIfLj4EES2_S2_S2_,"axG",@progbits,_ZL24k_reorder_send_buf_totaliiPjS_P15HIP_vector_typeIfLj4EES2_S2_S2_,comdat
.globl _ZL24k_reorder_send_buf_totaliiPjS_P15HIP_vector_typeIfLj4EES2_S2_S2_ ; -- Begin function _ZL24k_reorder_send_buf_totaliiPjS_P15HIP_vector_typeIfLj4EES2_S2_S2_
.p2align 8
.type _ZL24k_reorder_send_buf_totaliiPjS_P15HIP_vector_typeIfLj4EES2_S2_S2_,@function
_ZL24k_reorder_send_buf_totaliiPjS_P15HIP_vector_typeIfLj4EES2_S2_S2_: ; @_ZL24k_reorder_send_buf_totaliiPjS_P15HIP_vector_typeIfLj4EES2_S2_S2_
; %bb.0:
s_load_b32 s2, s[0:1], 0x0
v_lshl_add_u32 v0, s15, 9, v0
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_cmp_gt_i32_e32 vcc_lo, s2, v0
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_3
; %bb.1:
s_load_b256 s[4:11], s[0:1], 0x8
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[0:1]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v4, vcc_lo, s4, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v3, vcc_lo
global_load_b32 v4, v[4:5], off
s_waitcnt vmcnt(0)
v_cmp_eq_u32_e32 vcc_lo, 10, v4
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_3
; %bb.2:
v_add_co_u32 v2, vcc_lo, s6, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v3, vcc_lo
v_lshlrev_b64 v[6:7], 4, v[0:1]
s_load_b128 s[0:3], s[0:1], 0x28
global_load_b32 v4, v[2:3], off
v_add_co_u32 v0, vcc_lo, s8, v6
v_add_co_ci_u32_e32 v1, vcc_lo, s9, v7, vcc_lo
global_load_b128 v[0:3], v[0:1], off
s_waitcnt vmcnt(1)
v_ashrrev_i32_e32 v5, 31, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[4:5], 4, v[4:5]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v8, vcc_lo, s0, v4
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v9, vcc_lo, s1, v5, vcc_lo
v_add_co_u32 v6, vcc_lo, s10, v6
v_add_co_ci_u32_e32 v7, vcc_lo, s11, v7, vcc_lo
s_waitcnt vmcnt(0)
global_store_b128 v[8:9], v[0:3], off
v_add_co_u32 v4, vcc_lo, s2, v4
global_load_b128 v[0:3], v[6:7], off
v_add_co_ci_u32_e32 v5, vcc_lo, s3, v5, vcc_lo
s_waitcnt vmcnt(0)
global_store_b128 v[4:5], v[0:3], off
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _ZL24k_reorder_send_buf_totaliiPjS_P15HIP_vector_typeIfLj4EES2_S2_S2_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 56
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 10
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.section .text._ZL24k_reorder_send_buf_totaliiPjS_P15HIP_vector_typeIfLj4EES2_S2_S2_,"axG",@progbits,_ZL24k_reorder_send_buf_totaliiPjS_P15HIP_vector_typeIfLj4EES2_S2_S2_,comdat
.Lfunc_end0:
.size _ZL24k_reorder_send_buf_totaliiPjS_P15HIP_vector_typeIfLj4EES2_S2_S2_, .Lfunc_end0-_ZL24k_reorder_send_buf_totaliiPjS_P15HIP_vector_typeIfLj4EES2_S2_S2_
; -- End function
.section .AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 268
; NumSgprs: 18
; NumVgprs: 10
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 10
; Occupancy: 16
; WaveLimiterHint : 1
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object ; @__hip_cuid_
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0 ; 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 40
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 48
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 56
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _ZL24k_reorder_send_buf_totaliiPjS_P15HIP_vector_typeIfLj4EES2_S2_S2_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _ZL24k_reorder_send_buf_totaliiPjS_P15HIP_vector_typeIfLj4EES2_S2_S2_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 10
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
```
| 746 | 3,030 |
291 |
Convert the following CUDA host assembly code to AMD host assembly:
```cudaasm
.file "tmpxft_0013ac2f_00000000-6_k_reorder_send_buf_total.cudafe1.cpp"
.text
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.type _ZL24k_reorder_send_buf_totaliiPjS_P6float4S1_S1_S1_, @function
_ZL24k_reorder_send_buf_totaliiPjS_P6float4S1_S1_S1_:
.LFB2052:
.cfi_startproc
endbr64
subq $216, %rsp
.cfi_def_cfa_offset 224
movq %fs:40, %rax
movq %rax, 200(%rsp)
xorl %eax, %eax
movl %edi, 8(%rsp)
movl %esi, 12(%rsp)
movq %rdx, 16(%rsp)
movq %rcx, 24(%rsp)
movq %r8, 32(%rsp)
movq %r9, 40(%rsp)
movq 224(%rsp), %rax
movq %rax, 48(%rsp)
movq 232(%rsp), %rax
movq %rax, 56(%rsp)
leaq 8(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 24(%rsp), %rax
movq %rax, 152(%rsp)
leaq 32(%rsp), %rax
movq %rax, 160(%rsp)
leaq 40(%rsp), %rax
movq %rax, 168(%rsp)
leaq 48(%rsp), %rax
movq %rax, 176(%rsp)
leaq 56(%rsp), %rax
movq %rax, 184(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
leaq 72(%rsp), %rcx
leaq 64(%rsp), %rdx
leaq 92(%rsp), %rsi
leaq 80(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 200(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $216, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 72(%rsp)
.cfi_def_cfa_offset 232
pushq 72(%rsp)
.cfi_def_cfa_offset 240
leaq 144(%rsp), %r9
movq 108(%rsp), %rcx
movl 116(%rsp), %r8d
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
leaq _ZL24k_reorder_send_buf_totaliiPjS_P6float4S1_S1_S1_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 224
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2052:
.size _ZL24k_reorder_send_buf_totaliiPjS_P6float4S1_S1_S1_, .-_ZL24k_reorder_send_buf_totaliiPjS_P6float4S1_S1_S1_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z24k_reorder_send_buf_totaliiPjS_P6float4S1_S1_S1_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _ZL24k_reorder_send_buf_totaliiPjS_P6float4S1_S1_S1_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
```
|
```amdasm
.text
.file "k_reorder_send_buf_total.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
```
| 1,951 | 187 |
296 |
Convert the following CUDA device assembly code to AMD device assembly:
```cudaasm
code for sm_80
Function : _Z21ComputeBiasTermKernelPffS_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ;
S2R R0, SR_CTAID.Y ;
S2R R3, SR_CTAID.X ;
S2R R5, SR_TID.X ;
IMAD R0, R0, c[0x0][0xc], R3 ;
IMAD R0, R0, c[0x0][0x0], R5 ;
ISETP.GE.AND P0, PT, R0, c[0x0][0x17c], PT ;
@P0 EXIT ;
I2F R3, c[0x0][0x178] ;
ULDC.64 UR4, c[0x0][0x118] ;
IADD3 R2, R3, 0x1800000, RZ ;
LOP3.LUT R2, R2, 0x7f800000, RZ, 0xc0, !PT ;
ISETP.GT.U32.AND P0, PT, R2, 0x1ffffff, PT ;
@P0 BRA 0x110 ;
MOV R2, 0x100 ;
CALL.REL.NOINC 0x1d0 ;
BRA 0x150 ;
MUFU.RCP R4, R3 ;
FFMA R2, R3, R4, -1 ;
FADD.FTZ R5, -R2, -RZ ;
FFMA R4, R4, R5, R4 ;
IMAD.MOV.U32 R5, RZ, RZ, 0x4 ;
IMAD.WIDE R2, R0, R5, c[0x0][0x170] ;
LDG.E R3, [R2.64] ;
FADD R6, -R3, R4 ;
IMAD.WIDE R4, R0, R5, c[0x0][0x160] ;
FMUL R7, R6, c[0x0][0x168] ;
STG.E [R4.64], R7 ;
EXIT ;
IMAD.SHL.U32 R4, R3, 0x2, RZ ;
SHF.R.U32.HI R4, RZ, 0x18, R4 ;
ISETP.NE.U32.AND P0, PT, R4, RZ, PT ;
@P0 BRA 0x2c0 ;
IMAD.SHL.U32 R4, R3, 0x2, RZ ;
ISETP.NE.AND P0, PT, R4, RZ, PT ;
@!P0 MUFU.RCP R4, R3 ;
@!P0 BRA 0x4e0 ;
FFMA R3, R3, 1.84467440737095516160e+19, RZ ;
MUFU.RCP R4, R3 ;
FFMA R5, R3, R4, -1 ;
FADD.FTZ R5, -R5, -RZ ;
FFMA R4, R4, R5, R4 ;
FFMA R4, R4, 1.84467440737095516160e+19, RZ ;
BRA 0x4e0 ;
IADD3 R5, R4, -0xfd, RZ ;
ISETP.GT.U32.AND P0, PT, R5, 0x1, PT ;
@P0 BRA 0x4d0 ;
LOP3.LUT R6, R3, 0x7fffff, RZ, 0xc0, !PT ;
IMAD.MOV.U32 R10, RZ, RZ, 0x3 ;
LOP3.LUT R6, R6, 0x3f800000, RZ, 0xfc, !PT ;
SHF.L.U32 R11, R10, R5, RZ ;
MUFU.RCP R7, R6 ;
FFMA R8, R6, R7, -1 ;
FADD.FTZ R8, -R8, -RZ ;
FFMA.RM R9, R7.reuse, R8.reuse, R7.reuse ;
FFMA.RP R8, R7, R8, R7 ;
LOP3.LUT R7, R9.reuse, 0x7fffff, RZ, 0xc0, !PT ;
FSETP.NEU.FTZ.AND P0, PT, R9, R8, PT ;
LOP3.LUT R8, R7, 0x800000, RZ, 0xfc, !PT ;
SEL R7, RZ, 0xffffffff, !P0 ;
LOP3.LUT R6, R11, R8, RZ, 0xc0, !PT ;
IMAD.MOV R7, RZ, RZ, -R7 ;
SHF.R.U32.HI R6, RZ, R5, R6 ;
LOP3.LUT P1, RZ, R7, R5, R8, 0xf8, !PT ;
LOP3.LUT P0, RZ, R6.reuse, 0x1, RZ, 0xc0, !PT ;
LOP3.LUT P2, RZ, R6, 0x2, RZ, 0xc0, !PT ;
PLOP3.LUT P0, PT, P0, P1, P2, 0xe0, 0x0 ;
LOP3.LUT P1, RZ, R3, 0x7fffff, RZ, 0xc0, !PT ;
SEL R5, RZ, 0x1, !P0 ;
IMAD.MOV R5, RZ, RZ, -R5 ;
ISETP.GE.AND P0, PT, R5, RZ, PT ;
IADD3 R5, R4, -0xfc, RZ ;
SHF.R.U32.HI R4, RZ, R5, R8 ;
@!P0 IADD3 R4, R4, 0x1, RZ ;
@!P1 IMAD.SHL.U32 R4, R4, 0x2, RZ ;
LOP3.LUT R4, R4, 0x80000000, R3, 0xf8, !PT ;
BRA 0x4e0 ;
MUFU.RCP R4, R3 ;
IMAD.MOV.U32 R3, RZ, RZ, 0x0 ;
RET.REL.NODEC R2 0x0 ;
BRA 0x500;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
```
|
```amdasm
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z21ComputeBiasTermKernelPffS_ii ; -- Begin function _Z21ComputeBiasTermKernelPffS_ii
.globl _Z21ComputeBiasTermKernelPffS_ii
.p2align 8
.type _Z21ComputeBiasTermKernelPffS_ii,@function
_Z21ComputeBiasTermKernelPffS_ii: ; @_Z21ComputeBiasTermKernelPffS_ii
; %bb.0:
s_clause 0x2
s_load_b32 s4, s[0:1], 0x20
s_load_b32 s5, s[0:1], 0x2c
s_load_b64 s[2:3], s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_mul_i32 s4, s4, s15
s_and_b32 s5, s5, 0xffff
s_add_i32 s4, s4, s14
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s4, s5, v[0:1]
v_cmp_gt_i32_e32 vcc_lo, s3, v1
s_and_saveexec_b32 s3, vcc_lo
s_cbranch_execz .LBB0_2
; %bb.1:
s_load_b64 s[4:5], s[0:1], 0x10
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
global_load_b32 v2, v[2:3], off
v_cvt_f32_i32_e32 v3, s2
s_clause 0x1
s_load_b32 s2, s[0:1], 0x8
s_load_b64 s[0:1], s[0:1], 0x0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_div_scale_f32 v4, null, v3, v3, 1.0
v_div_scale_f32 v7, vcc_lo, 1.0, v3, 1.0
v_rcp_f32_e32 v5, v4
s_waitcnt_depctr 0xfff
v_fma_f32 v6, -v4, v5, 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v5, v6, v5
v_mul_f32_e32 v6, v7, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v8, -v4, v6, v7
v_fmac_f32_e32 v6, v8, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v4, -v4, v6, v7
v_div_fmas_f32 v4, v4, v5, v6
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_div_fixup_f32 v3, v4, v3, 1.0
s_waitcnt vmcnt(0)
v_sub_f32_e32 v2, v3, v2
s_delay_alu instid0(VALU_DEP_1)
v_mul_f32_e32 v2, s2, v2
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z21ComputeBiasTermKernelPffS_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z21ComputeBiasTermKernelPffS_ii, .Lfunc_end0-_Z21ComputeBiasTermKernelPffS_ii
; -- End function
.section .AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 296
; NumSgprs: 18
; NumVgprs: 9
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 9
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object ; @__hip_cuid_
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0 ; 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z21ComputeBiasTermKernelPffS_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z21ComputeBiasTermKernelPffS_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
```
| 1,657 | 3,103 |
297 |
Convert the following CUDA host assembly code to AMD host assembly:
```cudaasm
.file "tmpxft_0016879d_00000000-6_ComputeBiasTermKernel.cudafe1.cpp"
.text
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z46__device_stub__Z21ComputeBiasTermKernelPffS_iiPffS_ii
.type _Z46__device_stub__Z21ComputeBiasTermKernelPffS_iiPffS_ii, @function
_Z46__device_stub__Z21ComputeBiasTermKernelPffS_iiPffS_ii:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movss %xmm0, 20(%rsp)
movq %rsi, 8(%rsp)
movl %edx, 16(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 16(%rsp), %rax
movq %rax, 120(%rsp)
leaq 4(%rsp), %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z21ComputeBiasTermKernelPffS_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z46__device_stub__Z21ComputeBiasTermKernelPffS_iiPffS_ii, .-_Z46__device_stub__Z21ComputeBiasTermKernelPffS_iiPffS_ii
.globl _Z21ComputeBiasTermKernelPffS_ii
.type _Z21ComputeBiasTermKernelPffS_ii, @function
_Z21ComputeBiasTermKernelPffS_ii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z46__device_stub__Z21ComputeBiasTermKernelPffS_iiPffS_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z21ComputeBiasTermKernelPffS_ii, .-_Z21ComputeBiasTermKernelPffS_ii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z21ComputeBiasTermKernelPffS_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z21ComputeBiasTermKernelPffS_ii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
```
|
```amdasm
.text
.file "ComputeBiasTermKernel.hip"
.globl _Z36__device_stub__ComputeBiasTermKernelPffS_ii # -- Begin function _Z36__device_stub__ComputeBiasTermKernelPffS_ii
.type _Z36__device_stub__ComputeBiasTermKernelPffS_ii,@function
_Z36__device_stub__ComputeBiasTermKernelPffS_ii: # @_Z36__device_stub__ComputeBiasTermKernelPffS_ii
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $128, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 40(%rsp), %rax
movq %rdi, (%rax)
leaq 12(%rsp), %rdi
movss %xmm0, (%rdi)
leaq 32(%rsp), %r8
movq %rsi, (%r8)
leaq 8(%rsp), %rsi
movl %edx, (%rsi)
leaq 4(%rsp), %rdx
movl %ecx, (%rdx)
leaq 80(%rsp), %rbx
movq %rax, (%rbx)
movq %rdi, 8(%rbx)
movq %r8, 16(%rbx)
movq %rsi, 24(%rbx)
movq %rdx, 32(%rbx)
leaq 64(%rsp), %r14
leaq 48(%rsp), %r15
leaq 24(%rsp), %r12
leaq 16(%rsp), %r13
movq %r14, %rdi
movq %r15, %rsi
movq %r12, %rdx
movq %r13, %rcx
callq __hipPopCallConfiguration
movq (%r14), %rsi
movl 8(%r14), %edx
movq (%r15), %rcx
movl 8(%r15), %r8d
movl $_Z21ComputeBiasTermKernelPffS_ii, %edi
movq %rbx, %r9
pushq (%r13)
.cfi_adjust_cfa_offset 8
pushq (%r12)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $144, %rsp
.cfi_adjust_cfa_offset -144
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z36__device_stub__ComputeBiasTermKernelPffS_ii, .Lfunc_end0-_Z36__device_stub__ComputeBiasTermKernelPffS_ii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, %rdi
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z21ComputeBiasTermKernelPffS_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z21ComputeBiasTermKernelPffS_ii,@object # @_Z21ComputeBiasTermKernelPffS_ii
.section .rodata,"a",@progbits
.globl _Z21ComputeBiasTermKernelPffS_ii
.p2align 3, 0x0
_Z21ComputeBiasTermKernelPffS_ii:
.quad _Z36__device_stub__ComputeBiasTermKernelPffS_ii
.size _Z21ComputeBiasTermKernelPffS_ii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z21ComputeBiasTermKernelPffS_ii"
.size .L__unnamed_1, 33
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z36__device_stub__ComputeBiasTermKernelPffS_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z21ComputeBiasTermKernelPffS_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
```
| 1,977 | 2,156 |
298 |
Convert the following CUDA device assembly code to AMD device assembly:
```cudaasm
code for sm_80
Function : _Z3addPiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
MOV R1, c[0x0][0x28] ;
S2R R3, SR_CTAID.X ;
S2R R0, SR_TID.X ;
IMAD R3, R3, c[0x0][0x0], R0 ;
ISETP.GT.AND P0, PT, R3, 0xf, PT ;
@P0 EXIT ;
MOV R0, c[0x0][0xc] ;
ULDC.64 UR4, c[0x0][0x118] ;
BSSY B0, 0x310 ;
IMAD R0, R0, c[0x0][0x0], RZ ;
I2F.U32.RP R2, R0 ;
IADD3 R7, RZ, -R0, RZ ;
ISETP.NE.U32.AND P2, PT, R0, RZ, PT ;
MUFU.RCP R2, R2 ;
IADD3 R4, R2, 0xffffffe, RZ ;
F2I.FTZ.U32.TRUNC.NTZ R5, R4 ;
IMAD.MOV.U32 R4, RZ, RZ, RZ ;
IMAD R7, R7, R5, RZ ;
IMAD.HI.U32 R6, R5, R7, R4 ;
IADD3 R5, -R3, 0xf, RZ ;
IMAD.HI.U32 R6, R6, R5, RZ ;
IADD3 R2, -R6, RZ, RZ ;
IMAD R5, R0, R2, R5 ;
ISETP.GE.U32.AND P0, PT, R5, R0, PT ;
@P0 IADD3 R5, -R0, R5, RZ ;
@P0 IADD3 R6, R6, 0x1, RZ ;
ISETP.GE.U32.AND P1, PT, R5, R0, PT ;
@P1 IADD3 R6, R6, 0x1, RZ ;
@!P2 LOP3.LUT R6, RZ, R0, RZ, 0x33, !PT ;
IADD3 R2, R6.reuse, 0x1, RZ ;
ISETP.GE.U32.AND P1, PT, R6, 0x3, PT ;
LOP3.LUT P0, R2, R2, 0x3, RZ, 0xc0, !PT ;
@!P0 BRA 0x300 ;
IMAD.MOV.U32 R8, RZ, RZ, 0x4 ;
IMAD.WIDE R4, R3, R8, c[0x0][0x170] ;
IMAD.WIDE R6, R3, R8, c[0x0][0x168] ;
IMAD.WIDE R8, R3, R8, c[0x0][0x160] ;
LDG.E R10, [R6.64] ;
LDG.E R11, [R8.64] ;
IADD3 R2, R2, -0x1, RZ ;
IADD3 R3, R0, R3, RZ ;
ISETP.NE.AND P0, PT, R2, RZ, PT ;
IMAD.WIDE R6, R0, 0x4, R6 ;
IMAD.WIDE R8, R0, 0x4, R8 ;
IADD3 R11, R10, R11, RZ ;
STG.E [R4.64], R11 ;
IMAD.WIDE R4, R0, 0x4, R4 ;
@P0 BRA 0x250 ;
BSYNC B0 ;
@!P1 EXIT ;
HFMA2.MMA R8, -RZ, RZ, 0, 2.384185791015625e-07 ;
IMAD.WIDE R6, R3, R8, c[0x0][0x168] ;
IMAD.WIDE R4, R3.reuse, R8.reuse, c[0x0][0x160] ;
LDG.E R2, [R6.64] ;
LDG.E R11, [R4.64] ;
IMAD.WIDE R8, R3, R8, c[0x0][0x170] ;
IMAD.WIDE R12, R0, 0x4, R6 ;
IMAD.IADD R19, R2, 0x1, R11 ;
IMAD.WIDE R10, R0, 0x4, R4 ;
STG.E [R8.64], R19 ;
LDG.E R2, [R12.64] ;
LDG.E R17, [R10.64] ;
IMAD.WIDE R14, R0, 0x4, R8 ;
IMAD.WIDE R6, R0, 0x4, R12 ;
IMAD.WIDE R4, R0, 0x4, R10 ;
IADD3 R21, R2, R17, RZ ;
STG.E [R14.64], R21 ;
LDG.E R2, [R6.64] ;
LDG.E R23, [R4.64] ;
IMAD.WIDE R16, R0, 0x4, R14 ;
IMAD.WIDE R12, R0, 0x4, R6 ;
IMAD.WIDE R8, R0, 0x4, R4 ;
IADD3 R23, R2, R23, RZ ;
STG.E [R16.64], R23 ;
LDG.E R12, [R12.64] ;
LDG.E R9, [R8.64] ;
IMAD.WIDE R10, R0.reuse, 0x4, R16 ;
IADD3 R3, R0, R3, R0 ;
IADD3 R3, R0, R3, R0 ;
ISETP.GE.AND P0, PT, R3, 0x10, PT ;
IADD3 R15, R12, R9, RZ ;
STG.E [R10.64], R15 ;
@!P0 BRA 0x320 ;
EXIT ;
BRA 0x540;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
```
|
```amdasm
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3addPiS_S_ ; -- Begin function _Z3addPiS_S_
.globl _Z3addPiS_S_
.p2align 8
.type _Z3addPiS_S_,@function
_Z3addPiS_S_: ; @_Z3addPiS_S_
; %bb.0:
s_load_b32 s4, s[0:1], 0x24
s_add_u32 s2, s0, 24
s_addc_u32 s3, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s8, s4, 0xffff
s_mov_b32 s4, exec_lo
v_mad_u64_u32 v[1:2], null, s15, s8, v[0:1]
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e32 16, v1
s_cbranch_execz .LBB0_3
; %bb.1: ; %.lr.ph.preheader
s_load_b32 s9, s[2:3], 0x0
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[2:3], s[0:1], 0x10
v_ashrrev_i32_e32 v2, 31, v1
s_mov_b32 s1, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_lshlrev_b64 v[2:3], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_mul_i32 s8, s9, s8
s_ashr_i32 s9, s8, 31
s_delay_alu instid0(SALU_CYCLE_1)
s_lshl_b64 s[10:11], s[8:9], 2
.LBB0_2: ; %.lr.ph
; =>This Inner Loop Header: Depth=1
s_delay_alu instid0(VALU_DEP_1)
v_add_co_u32 v4, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v3, vcc_lo
v_add_co_u32 v6, vcc_lo, s6, v2
v_add_co_ci_u32_e32 v7, vcc_lo, s7, v3, vcc_lo
v_add_nc_u32_e32 v1, s8, v1
global_load_b32 v0, v[4:5], off
global_load_b32 v6, v[6:7], off
v_add_co_u32 v4, vcc_lo, s2, v2
v_add_co_ci_u32_e32 v5, vcc_lo, s3, v3, vcc_lo
v_add_co_u32 v2, vcc_lo, v2, s10
v_cmp_lt_i32_e64 s0, 15, v1
v_add_co_ci_u32_e32 v3, vcc_lo, s11, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_2)
s_or_b32 s1, s0, s1
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v0, v6, v0
global_store_b32 v[4:5], v0, off
s_and_not1_b32 exec_lo, exec_lo, s1
s_cbranch_execnz .LBB0_2
.LBB0_3: ; %Flow24
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3addPiS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3addPiS_S_, .Lfunc_end0-_Z3addPiS_S_
; -- End function
.section .AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 244
; NumSgprs: 18
; NumVgprs: 8
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 8
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object ; @__hip_cuid_
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0 ; 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3addPiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z3addPiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
```
| 1,587 | 2,794 |
299 |
Convert the following CUDA host assembly code to AMD host assembly:
```cudaasm
.file "tmpxft_000f608d_00000000-6_task7.cudafe1.cpp"
.text
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z26__device_stub__Z3addPiS_S_PiS_S_
.type _Z26__device_stub__Z3addPiS_S_PiS_S_, @function
_Z26__device_stub__Z3addPiS_S_PiS_S_:
.LFB2082:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z3addPiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z26__device_stub__Z3addPiS_S_PiS_S_, .-_Z26__device_stub__Z3addPiS_S_PiS_S_
.globl _Z3addPiS_S_
.type _Z3addPiS_S_, @function
_Z3addPiS_S_:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z3addPiS_S_PiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z3addPiS_S_, .-_Z3addPiS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "a[%d] + b[%d] = %d\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $64, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl $64, %edi
call malloc@PLT
movq %rax, %r12
movl $64, %edi
call malloc@PLT
movq %rax, %rbx
movl $64, %edi
call malloc@PLT
movq %rax, %rbp
movl $0, %eax
.L12:
movl $1, (%rbx,%rax)
movl $1, (%r12,%rax)
addq $4, %rax
cmpq $64, %rax
jne .L12
leaq 8(%rsp), %rdi
movl $64, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $64, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $64, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $64, %edx
movq %r12, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $64, %edx
movq %rbx, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $2, 32(%rsp)
movl $1, 36(%rsp)
movl $4, 44(%rsp)
movl $1, 48(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L19
.L13:
movl $2, %ecx
movl $64, %edx
movq 24(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
movl $0, %ebx
leaq .LC0(%rip), %r12
.L14:
movl %ebx, %edx
movl 0(%rbp,%rbx,4), %r8d
movl %ebx, %ecx
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq $16, %rbx
jne .L14
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L20
movl $0, %eax
addq $64, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z26__device_stub__Z3addPiS_S_PiS_S_
jmp .L13
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC1:
.string "_Z3addPiS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z3addPiS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
```
|
```amdasm
.text
.file "task7.hip"
.globl _Z18__device_stub__addPiS_S_ # -- Begin function _Z18__device_stub__addPiS_S_
.type _Z18__device_stub__addPiS_S_,@function
_Z18__device_stub__addPiS_S_: # @_Z18__device_stub__addPiS_S_
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $112, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 40(%rsp), %rax
movq %rdi, (%rax)
leaq 32(%rsp), %rcx
movq %rsi, (%rcx)
leaq 24(%rsp), %rsi
movq %rdx, (%rsi)
leaq 80(%rsp), %rbx
movq %rax, (%rbx)
movq %rcx, 8(%rbx)
movq %rsi, 16(%rbx)
leaq 64(%rsp), %r14
leaq 48(%rsp), %r15
leaq 16(%rsp), %r12
leaq 8(%rsp), %r13
movq %r14, %rdi
movq %r15, %rsi
movq %r12, %rdx
movq %r13, %rcx
callq __hipPopCallConfiguration
movq (%r14), %rsi
movl 8(%r14), %edx
movq (%r15), %rcx
movl 8(%r15), %r8d
movl $_Z3addPiS_S_, %edi
movq %rbx, %r9
pushq (%r13)
.cfi_adjust_cfa_offset 8
pushq (%r12)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $128, %rsp
.cfi_adjust_cfa_offset -128
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z18__device_stub__addPiS_S_, .Lfunc_end0-_Z18__device_stub__addPiS_S_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $32, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $64, %edi
callq malloc
movq %rax, %r15
movl $64, %edi
callq malloc
movq %rax, %r14
movl $64, %edi
callq malloc
movq %rax, %rbx
xorl %eax, %eax
movl $1, %ecx
.LBB1_1: # =>This Inner Loop Header: Depth=1
movl %ecx, (%r14,%rax,4)
movl %ecx, (%r15,%rax,4)
incq %rax
cmpq $16, %rax
jne .LBB1_1
# %bb.2:
leaq 24(%rsp), %r12
movl $64, %esi
movq %r12, %rdi
callq hipMalloc
leaq 16(%rsp), %r13
movl $64, %esi
movq %r13, %rdi
callq hipMalloc
leaq 8(%rsp), %rdi
movl $64, %esi
callq hipMalloc
movq (%r12), %rdi
movl $64, %edx
movq %r15, %rsi
movl $1, %ecx
callq hipMemcpy
movq (%r13), %rdi
movl $64, %edx
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $4294967298, %rdi # imm = 0x100000002
leaq 2(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq 24(%rsp), %rdi
movq 16(%rsp), %rsi
movq 8(%rsp), %rdx
callq _Z18__device_stub__addPiS_S_
.LBB1_4:
movq 8(%rsp), %rsi
movl $64, %edx
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
xorl %r14d, %r14d
.LBB1_5: # =>This Inner Loop Header: Depth=1
movl (%rbx,%r14,4), %ecx
movl $.L.str, %edi
movl %r14d, %esi
movl %r14d, %edx
xorl %eax, %eax
callq printf
incq %r14
cmpq $16, %r14
jne .LBB1_5
# %bb.6:
xorl %eax, %eax
addq $32, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, %rdi
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3addPiS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3addPiS_S_,@object # @_Z3addPiS_S_
.section .rodata,"a",@progbits
.globl _Z3addPiS_S_
.p2align 3, 0x0
_Z3addPiS_S_:
.quad _Z18__device_stub__addPiS_S_
.size _Z3addPiS_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "a[%d] + b[%d] = %d\n"
.size .L.str, 20
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z3addPiS_S_"
.size .L__unnamed_1, 13
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__addPiS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3addPiS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
```
| 2,910 | 3,157 |
300 |
Convert the following CUDA device assembly code to AMD device assembly:
```cudaasm
code for sm_80
Function : _Z17FindMaxMinPerGridiiPfS_S_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ;
S2R R0, SR_TID.X ;
IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x164] ;
ULDC.64 UR12, c[0x0][0x118] ;
BSSY B0, 0x1030 ;
ISETP.GE.AND P1, PT, R2.reuse, 0x2, PT ;
IADD3 R3, R2, -0x1, RZ ;
ISETP.GE.U32.OR P0, PT, R0, c[0x0][0x160], !P1 ;
@P0 BRA 0x1020 ;
IADD3 R4, R2, -0x2, RZ ;
IMAD.MOV.U32 R5, RZ, RZ, RZ ;
ISETP.GE.U32.AND P0, PT, R4, 0x3, PT ;
LOP3.LUT R4, R3, 0x3, RZ, 0xc0, !PT ;
@!P0 BRA 0xf30 ;
IMAD.IADD R6, R3, 0x1, -R4 ;
IMAD.MOV.U32 R5, RZ, RZ, RZ ;
ISETP.GT.AND P0, PT, R6, RZ, PT ;
@!P0 BRA 0xd10 ;
ISETP.GT.AND P2, PT, R6, 0xc, PT ;
PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ;
@!P2 BRA 0x8f0 ;
PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ;
IMAD R27, R5, c[0x0][0x160], R0 ;
IMAD.MOV.U32 R24, RZ, RZ, 0x4 ;
IADD3 R11, R27.reuse, c[0x0][0x160], RZ ;
IMAD.WIDE.U32 R22, R27, R24, c[0x0][0x168] ;
IMAD.WIDE.U32 R26, R27, R24.reuse, c[0x0][0x170] ;
IADD3 R17, R11.reuse, c[0x0][0x160], RZ ;
LDG.E R22, [R22.64] ;
IMAD.WIDE.U32 R12, R11.reuse, R24.reuse, c[0x0][0x168] ;
LDG.E R29, [R26.64] ;
IMAD.WIDE.U32 R10, R11, R24.reuse, c[0x0][0x170] ;
IADD3 R15, R5, 0x4, RZ ;
LDG.E R12, [R12.64] ;
IMAD.WIDE.U32 R8, R17, R24, c[0x0][0x168] ;
LDG.E R21, [R10.64] ;
IADD3 R7, R17.reuse, c[0x0][0x160], RZ ;
IMAD.WIDE.U32 R16, R17, R24.reuse, c[0x0][0x170] ;
LDG.E R8, [R8.64] ;
IMAD R15, R15, c[0x0][0x160], R0 ;
IMAD.WIDE.U32 R26, R7.reuse, R24.reuse, c[0x0][0x170] ;
LDG.E R28, [R16.64] ;
IMAD.WIDE.U32 R18, R7, R24.reuse, c[0x0][0x168] ;
IADD3 R7, R15.reuse, c[0x0][0x160], RZ ;
LDG.E R26, [R26.64] ;
IMAD.WIDE.U32 R10, R15, R24, c[0x0][0x170] ;
LDG.E R14, [R18.64] ;
IMAD.WIDE.U32 R16, R15, R24.reuse, c[0x0][0x168] ;
LDG.E R9, [R10.64] ;
LDG.E R15, [R16.64] ;
IMAD.WIDE.U32 R18, R7, R24, c[0x0][0x170] ;
LDG.E R18, [R18.64] ;
IMAD.WIDE.U32 R16, R7.reuse, R24, c[0x0][0x168] ;
IADD3 R7, R7, c[0x0][0x160], RZ ;
LDG.E R13, [R16.64] ;
IMAD.WIDE.U32 R10, R7.reuse, R24, c[0x0][0x168] ;
IADD3 R19, R7, c[0x0][0x160], RZ ;
LDG.E R25, [R10.64] ;
IMAD.WIDE.U32 R16, R7, R24, c[0x0][0x170] ;
LDG.E R27, [R16.64] ;
IMAD.WIDE.U32 R10, R19, R24, c[0x0][0x168] ;
LDG.E R20, [R10.64] ;
IMAD R7, R5.reuse, 0x10, R0.reuse ;
IADD3 R23, R5.reuse, 0x8, RZ ;
IADD3 R17, R5, 0xc, RZ ;
STS [R7.X4+0x600], R29 ;
IMAD R29, R23, c[0x0][0x160], R0 ;
STS [R7.X4], R22 ;
IMAD.WIDE.U32 R10, R29, R24, c[0x0][0x170] ;
STS [R7.X4+0x640], R21 ;
LDG.E R10, [R10.64] ;
IMAD.WIDE.U32 R22, R29, R24, c[0x0][0x168] ;
IMAD R21, R17, c[0x0][0x160], R0 ;
STS [R7.X4+0x80], R8 ;
IADD3 R11, R29, c[0x0][0x160], RZ ;
STS [R7.X4+0x40], R12 ;
LDG.E R8, [R22.64] ;
IMAD.WIDE.U32 R16, R11, R24, c[0x0][0x168] ;
STS [R7.X4+0x680], R28 ;
LDG.E R16, [R16.64] ;
IMAD.WIDE.U32 R22, R21, R24, c[0x0][0x168] ;
IMAD.WIDE.U32 R28, R21.reuse, R24.reuse, c[0x0][0x170] ;
LDG.E R12, [R22.64] ;
IADD3 R21, R21, c[0x0][0x160], RZ ;
IADD3 R17, R11.reuse, c[0x0][0x160], RZ ;
STS [R7.X4+0x6c0], R26 ;
IMAD.WIDE.U32 R22, R11, R24, c[0x0][0x170] ;
STS [R7.X4+0xc0], R14 ;
LDG.E R26, [R22.64] ;
LDG.E R14, [R28.64] ;
IMAD.WIDE.U32 R22, R21, R24, c[0x0][0x168] ;
STS [R7.X4+0x700], R9 ;
IMAD.WIDE.U32 R28, R17, R24, c[0x0][0x168] ;
STS [R7.X4+0x740], R18 ;
LDG.E R9, [R22.64] ;
LDG.E R11, [R28.64] ;
IMAD.WIDE.U32 R18, R19, R24, c[0x0][0x170] ;
IMAD.WIDE.U32 R22, R17, R24.reuse, c[0x0][0x170] ;
STS [R7.X4+0x100], R15 ;
IMAD.WIDE.U32 R28, R21.reuse, R24, c[0x0][0x170] ;
IADD3 R21, R21, c[0x0][0x160], RZ ;
STS [R7.X4+0x180], R25 ;
LDG.E R15, [R22.64] ;
IADD3 R25, R21, c[0x0][0x160], RZ ;
IADD3 R23, R17, c[0x0][0x160], RZ ;
LDG.E R17, [R18.64] ;
STS [R7.X4+0x140], R13 ;
IMAD.WIDE.U32 R18, R21, R24, c[0x0][0x168] ;
STS [R7.X4+0x780], R27 ;
LDG.E R13, [R28.64] ;
STS [R7.X4+0x1c0], R20 ;
LDG.E R27, [R18.64] ;
IMAD.WIDE.U32 R28, R23, R24, c[0x0][0x168] ;
IMAD.WIDE.U32 R20, R21, R24.reuse, c[0x0][0x170] ;
LDG.E R28, [R28.64] ;
IMAD.WIDE.U32 R18, R23, R24.reuse, c[0x0][0x170] ;
LDG.E R21, [R20.64] ;
IMAD.WIDE.U32 R22, R25.reuse, R24.reuse, c[0x0][0x168] ;
LDG.E R18, [R18.64] ;
IMAD.WIDE.U32 R24, R25, R24, c[0x0][0x170] ;
LDG.E R22, [R22.64] ;
LDG.E R24, [R24.64] ;
IADD3 R6, R6, -0x10, RZ ;
ISETP.GT.AND P2, PT, R6, 0xc, PT ;
IADD3 R5, R5, 0x10, RZ ;
STS [R7.X4+0x800], R10 ;
STS [R7.X4+0x200], R8 ;
STS [R7.X4+0x240], R16 ;
STS [R7.X4+0x300], R12 ;
STS [R7.X4+0x840], R26 ;
STS [R7.X4+0x900], R14 ;
STS [R7.X4+0x340], R9 ;
STS [R7.X4+0x280], R11 ;
STS [R7.X4+0x880], R15 ;
STS [R7.X4+0x7c0], R17 ;
STS [R7.X4+0x940], R13 ;
STS [R7.X4+0x380], R27 ;
STS [R7.X4+0x2c0], R28 ;
STS [R7.X4+0x980], R21 ;
STS [R7.X4+0x8c0], R18 ;
STS [R7.X4+0x3c0], R22 ;
STS [R7.X4+0x9c0], R24 ;
@P2 BRA 0x160 ;
ISETP.GT.AND P2, PT, R6, 0x4, PT ;
@!P2 BRA 0xcf0 ;
IMAD R17, R5.reuse, c[0x0][0x160], R0 ;
IADD3 R9, R5, 0x4, RZ ;
IMAD.MOV.U32 R24, RZ, RZ, 0x4 ;
IADD3 R25, R17, c[0x0][0x160], RZ ;
IMAD R11, R9, c[0x0][0x160], R0 ;
IMAD.WIDE.U32 R22, R17, R24, c[0x0][0x168] ;
IADD3 R29, R11, c[0x0][0x160], RZ ;
IMAD.WIDE.U32 R16, R17, R24.reuse, c[0x0][0x170] ;
LDG.E R7, [R22.64] ;
IMAD.WIDE.U32 R20, R25.reuse, R24.reuse, c[0x0][0x168] ;
LDG.E R8, [R16.64] ;
IMAD.WIDE.U32 R12, R25.reuse, R24.reuse, c[0x0][0x170] ;
IADD3 R25, R25, c[0x0][0x160], RZ ;
LDG.E R9, [R20.64] ;
IMAD.WIDE.U32 R26, R11, R24, c[0x0][0x170] ;
LDG.E R10, [R12.64] ;
IMAD.WIDE.U32 R14, R25.reuse, R24.reuse, c[0x0][0x168] ;
LDG.E R26, [R26.64] ;
IMAD.WIDE.U32 R22, R25.reuse, R24, c[0x0][0x170] ;
IADD3 R25, R25, c[0x0][0x160], RZ ;
IMAD.WIDE.U32 R16, R29.reuse, R24.reuse, c[0x0][0x168] ;
IADD3 R21, R29.reuse, c[0x0][0x160], RZ ;
LDG.E R28, [R22.64] ;
IMAD.WIDE.U32 R12, R29, R24.reuse, c[0x0][0x170] ;
LDG.E R27, [R14.64] ;
IMAD.WIDE.U32 R18, R11, R24.reuse, c[0x0][0x168] ;
LDG.E R29, [R16.64] ;
LDG.E R11, [R18.64] ;
IMAD.WIDE.U32 R14, R25, R24, c[0x0][0x168] ;
LDG.E R12, [R12.64] ;
IMAD.WIDE.U32 R16, R25, R24.reuse, c[0x0][0x170] ;
IADD3 R25, R21.reuse, c[0x0][0x160], RZ ;
LDG.E R14, [R14.64] ;
IMAD.WIDE.U32 R18, R21, R24, c[0x0][0x168] ;
LDG.E R16, [R16.64] ;
IMAD.WIDE.U32 R20, R21, R24, c[0x0][0x170] ;
LDG.E R18, [R18.64] ;
IMAD.WIDE.U32 R22, R25, R24, c[0x0][0x168] ;
LDG.E R20, [R20.64] ;
IMAD.WIDE.U32 R24, R25, R24, c[0x0][0x170] ;
LDG.E R22, [R22.64] ;
LDG.E R24, [R24.64] ;
IMAD R13, R5.reuse, 0x10, R0 ;
PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ;
IADD3 R6, R6, -0x8, RZ ;
IADD3 R5, R5, 0x8, RZ ;
STS [R13.X4], R7 ;
STS [R13.X4+0x600], R8 ;
STS [R13.X4+0x40], R9 ;
STS [R13.X4+0x640], R10 ;
STS [R13.X4+0x700], R26 ;
STS [R13.X4+0x680], R28 ;
STS [R13.X4+0x80], R27 ;
STS [R13.X4+0x140], R29 ;
STS [R13.X4+0x100], R11 ;
STS [R13.X4+0x740], R12 ;
STS [R13.X4+0xc0], R14 ;
STS [R13.X4+0x6c0], R16 ;
STS [R13.X4+0x180], R18 ;
STS [R13.X4+0x780], R20 ;
STS [R13.X4+0x1c0], R22 ;
STS [R13.X4+0x7c0], R24 ;
ISETP.NE.OR P0, PT, R6, RZ, P0 ;
@!P0 BRA 0xf30 ;
IMAD R18, R5, c[0x0][0x160], R0 ;
IMAD.MOV.U32 R9, RZ, RZ, 0x4 ;
IADD3 R16, R18.reuse, c[0x0][0x160], RZ ;
IMAD.WIDE.U32 R22, R18, R9, c[0x0][0x168] ;
IADD3 R12, R16.reuse, c[0x0][0x160], RZ ;
IMAD.WIDE.U32 R20, R16, R9.reuse, c[0x0][0x168] ;
LDG.E R7, [R22.64] ;
IADD3 R8, R12.reuse, c[0x0][0x160], RZ ;
IMAD.WIDE.U32 R14, R12, R9.reuse, c[0x0][0x168] ;
LDG.E R20, [R20.64] ;
IMAD.WIDE.U32 R18, R18, R9.reuse, c[0x0][0x170] ;
LDG.E R14, [R14.64] ;
IMAD.WIDE.U32 R16, R16, R9, c[0x0][0x170] ;
LDG.E R18, [R18.64] ;
IMAD.WIDE.U32 R12, R12, R9.reuse, c[0x0][0x170] ;
LDG.E R16, [R16.64] ;
IMAD.WIDE.U32 R10, R8.reuse, R9.reuse, c[0x0][0x168] ;
LDG.E R12, [R12.64] ;
IMAD.WIDE.U32 R8, R8, R9, c[0x0][0x170] ;
LDG.E R10, [R10.64] ;
LDG.E R8, [R8.64] ;
IMAD R19, R5, 0x10, R0 ;
IADD3 R6, R6, -0x4, RZ ;
ISETP.NE.AND P0, PT, R6, RZ, PT ;
IADD3 R5, R5, 0x4, RZ ;
STS [R19.X4], R7 ;
STS [R19.X4+0x40], R20 ;
STS [R19.X4+0x80], R14 ;
STS [R19.X4+0x600], R18 ;
STS [R19.X4+0x640], R16 ;
STS [R19.X4+0x680], R12 ;
STS [R19.X4+0xc0], R10 ;
STS [R19.X4+0x6c0], R8 ;
@P0 BRA 0xd10 ;
ISETP.NE.AND P0, PT, R4, RZ, PT ;
@!P0 BRA 0x1020 ;
IMAD.MOV.U32 R9, RZ, RZ, 0x4 ;
IMAD R8, R5, c[0x0][0x160], R0 ;
IMAD.WIDE.U32 R6, R8, R9, c[0x0][0x168] ;
IMAD.WIDE.U32 R8, R8, R9, c[0x0][0x170] ;
LDG.E R6, [R6.64] ;
LDG.E R8, [R8.64] ;
IMAD R11, R5.reuse, 0x10, R0 ;
IADD3 R4, R4, -0x1, RZ ;
IADD3 R5, R5, 0x1, RZ ;
ISETP.NE.AND P0, PT, R4, RZ, PT ;
STS [R11.X4], R6 ;
STS [R11.X4+0x600], R8 ;
@P0 BRA 0xf50 ;
BSYNC B0 ;
IMAD.MOV.U32 R6, RZ, RZ, c[0x0][0x160] ;
ISETP.LT.OR P0, PT, R6, 0x11, !P1 ;
@P0 BRA 0x18a0 ;
IADD3 R4, R6, 0xf, RZ ;
IMAD.MOV.U32 R7, RZ, RZ, 0x4 ;
IADD3 R2, R2, -0x2, RZ ;
SHF.R.S32.HI R5, RZ, 0x1f, R4 ;
IMAD.WIDE R6, R7, R6, c[0x2][0x0] ;
ISETP.GE.U32.AND P0, PT, R2, 0x3, PT ;
LOP3.LUT R2, R3, 0x3, RZ, 0xc0, !PT ;
LEA.HI R4, R5, R4, RZ, 0x4 ;
IMAD.MOV.U32 R5, RZ, RZ, 0x1 ;
IMAD.IADD R3, R3, 0x1, -R2 ;
SHF.R.S32.HI R4, RZ, 0x4, R4 ;
IMAD R8, R5.reuse, 0x10, R0 ;
IADD3 R5, R5, 0x1, RZ ;
BSSY B0, 0x1890 ;
ISETP.GE.AND P3, PT, R8, c[0x0][0x160], PT ;
ISETP.GE.AND P2, PT, R5, R4, PT ;
@P3 BRA 0x1880 ;
ISETP.NE.AND P3, PT, R2, RZ, PT ;
IMAD.MOV.U32 R9, RZ, RZ, RZ ;
@!P0 BRA 0x1590 ;
IMAD.MOV.U32 R9, RZ, RZ, RZ ;
IMAD.MOV.U32 R10, RZ, RZ, R3 ;
IMAD.MOV.U32 R17, RZ, RZ, 0x4 ;
IMAD R12, R9, c[0x0][0x160], R8 ;
IMAD.WIDE R16, R12, R17, c[0x0][0x168] ;
LDG.E R11, [R16.64] ;
IMAD.MOV.U32 R19, RZ, RZ, c[0x0][0x160] ;
SHF.R.S32.HI R13, RZ, 0x1f, R12 ;
LEA R22, P4, R12, c[0x0][0x170], 0x2 ;
IMAD.WIDE R26, R19, 0x4, R16 ;
LEA.HI.X R23, R12, c[0x0][0x174], R13, 0x2, P4 ;
IADD3 R24, P5, R6, R26, RZ ;
LDG.E R13, [R26.64] ;
IMAD.WIDE R20, R19, 0x4, R22 ;
IADD3 R14, P4, R26, -0x40, RZ ;
LDG.E R12, [R22.64] ;
IMAD.X R25, R7, 0x1, R27, P5 ;
IADD3 R16, P5, R20, -0x40, RZ ;
IADD3.X R15, R27, -0x1, RZ, P4, !PT ;
IADD3.X R17, R21, -0x1, RZ, P5, !PT ;
IADD3 R18, P4, R6.reuse, R20, RZ ;
IMAD.WIDE R14, R19.reuse, 0x4, R14 ;
LDG.E R22, [R24.64+-0x40] ;
IMAD.WIDE R16, R19, 0x4, R16 ;
LDG.E R23, [R20.64] ;
IADD3 R14, P5, R6, R14, RZ ;
IMAD.X R19, R7.reuse, 0x1, R21, P4 ;
IADD3 R16, P4, R6, R16, RZ ;
IMAD.X R15, R7.reuse, 0x1, R15, P5 ;
LDG.E R18, [R18.64+-0x40] ;
IMAD.X R17, R7, 0x1, R17, P4 ;
LDG.E R14, [R14.64] ;
LDG.E R26, [R16.64] ;
IMAD R20, R9, 0x10, R0 ;
IMAD.SHL.U32 R25, R20, 0x4, RZ ;
LDS R20, [R25] ;
LDS R21, [R25+0x600] ;
LDS R24, [R25+0x640] ;
LDS R15, [R25+0x80] ;
LDS R19, [R25+0xc0] ;
LDS R16, [R25+0x6c0] ;
LDS R17, [R25+0x680] ;
IADD3 R10, R10, -0x4, RZ ;
IADD3 R9, R9, 0x4, RZ ;
FSETP.GEU.AND P4, PT, R20, R11, PT ;
LDS R20, [R25+0x40] ;
@!P4 STS [R25], R11 ;
FSETP.GT.AND P4, PT, R21, R12, PT ;
FSETP.GEU.AND P6, PT, R15, R22, PT ;
FSETP.GT.AND P5, PT, R24, R23, PT ;
@P4 STS [R25+0x600], R12 ;
FSETP.GEU.AND P4, PT, R20, R13, PT ;
@P5 STS [R25+0x640], R23 ;
FSETP.GEU.AND P5, PT, R19, R14, PT ;
@!P6 STS [R25+0x80], R22 ;
FSETP.GT.AND P6, PT, R16, R26, PT ;
@!P4 STS [R25+0x40], R13 ;
FSETP.GT.AND P4, PT, R17, R18, PT ;
@!P5 STS [R25+0xc0], R14 ;
@P6 STS [R25+0x6c0], R26 ;
@P4 STS [R25+0x680], R18 ;
ISETP.NE.AND P4, PT, R10, RZ, PT ;
@P4 BRA 0x11c0 ;
@!P3 BRA 0x1880 ;
IMAD R17, R9, c[0x0][0x160], R8 ;
IMAD.MOV.U32 R8, RZ, RZ, 0x4 ;
SHF.R.S32.HI R14, RZ, 0x1f, R17 ;
IMAD.WIDE R10, R17.reuse, R8, c[0x0][0x168] ;
LEA R12, P3, R17, c[0x0][0x170], 0x2 ;
LEA.HI.X R13, R17, c[0x0][0x174], R14, 0x2, P3 ;
LDG.E R10, [R10.64] ;
LDG.E R12, [R12.64] ;
IMAD R9, R9, 0x10, R0 ;
IMAD.SHL.U32 R9, R9, 0x4, RZ ;
LDS R15, [R9+0x600] ;
LDS R14, [R9] ;
FSETP.GEU.AND P3, PT, R14, R10, PT ;
FSETP.GT.AND P4, PT, R15, R12, PT ;
@!P3 STS [R9], R10 ;
ISETP.NE.AND P3, PT, R2, 0x1, PT ;
@P4 STS [R9+0x600], R12 ;
@!P3 BRA 0x1880 ;
IADD3 R17, R17, c[0x0][0x160], RZ ;
LDS R15, [R9+0x640] ;
SHF.R.S32.HI R14, RZ, 0x1f, R17 ;
IMAD.WIDE R10, R17.reuse, R8, c[0x0][0x168] ;
LEA R12, P3, R17, c[0x0][0x170], 0x2 ;
LEA.HI.X R13, R17, c[0x0][0x174], R14, 0x2, P3 ;
LDG.E R10, [R10.64] ;
LDG.E R12, [R12.64] ;
LDS R14, [R9+0x40] ;
FSETP.GEU.AND P3, PT, R14, R10, PT ;
FSETP.GT.AND P4, PT, R15, R12, PT ;
@!P3 STS [R9+0x40], R10 ;
ISETP.NE.AND P3, PT, R2, 0x2, PT ;
@P4 STS [R9+0x640], R12 ;
@!P3 BRA 0x1880 ;
IADD3 R17, R17, c[0x0][0x160], RZ ;
SHF.R.S32.HI R14, RZ, 0x1f, R17 ;
IMAD.WIDE R10, R17.reuse, R8, c[0x0][0x168] ;
LEA R12, P3, R17.reuse, c[0x0][0x170], 0x2 ;
LDS R8, [R9+0x80] ;
LEA.HI.X R13, R17, c[0x0][0x174], R14, 0x2, P3 ;
LDG.E R10, [R10.64] ;
LDG.E R12, [R12.64] ;
LDS R14, [R9+0x680] ;
FSETP.GEU.AND P3, PT, R8, R10, PT ;
FSETP.GT.AND P4, PT, R14, R12, PT ;
@!P3 STS [R9+0x80], R10 ;
@P4 STS [R9+0x680], R12 ;
BSYNC B0 ;
@!P2 BRA 0x1110 ;
IMAD.MOV.U32 R2, RZ, RZ, 0x1 ;
BAR.SYNC.DEFER_BLOCKING 0x0 ;
ISETP.LE.AND P0, PT, R2, c[0x0][0x188], PT ;
@!P0 BRA 0x2db0 ;
IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x164] ;
UMOV UR4, 0x1 ;
IADD3 R3, R2.reuse, -0x1, RZ ;
IADD3 R4, R2, -0x2, RZ ;
IMAD.SHL.U32 R2, R0, 0x4, RZ ;
LOP3.LUT R3, R3, 0x3, RZ, 0xc0, !PT ;
ISETP.GE.U32.AND P2, PT, R4, 0x3, PT ;
IMAD.MOV.U32 R4, RZ, RZ, RZ ;
IADD3 R5, R2.reuse, 0x80, RZ ;
IADD3 R6, R2, 0x680, RZ ;
IADD3 R7, -R3, c[0x0][0x164], RZ ;
LOP3.LUT P0, RZ, R0, UR4, RZ, 0xc0, !PT ;
BSSY B0, 0x2d50 ;
@P0 BRA 0x2d40 ;
IMAD.MOV.U32 R11, RZ, RZ, 0x1 ;
SHF.L.U32 R11, R11, R4, RZ ;
IMAD.IADD R8, R11, 0x1, R0 ;
ISETP.GE.OR P0, PT, R8, c[0x0][0x160], !P1 ;
@P0 BRA 0x2d40 ;
IMAD.MOV.U32 R9, RZ, RZ, RZ ;
@!P2 BRA 0x2b20 ;
ISETP.GT.AND P0, PT, R7, 0x1, PT ;
IMAD R10, R11, 0x4, R2 ;
IMAD.MOV.U32 R9, RZ, RZ, RZ ;
IMAD.MOV.U32 R12, RZ, RZ, R6 ;
IADD3 R13, R10, 0x600, RZ ;
IMAD.MOV.U32 R11, RZ, RZ, R5 ;
IMAD.MOV.U32 R14, RZ, RZ, R7 ;
@!P0 BRA 0x28a0 ;
IADD3 R15, R14, -0x1, RZ ;
PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ;
ISETP.GT.AND P3, PT, R15, 0xc, PT ;
@!P3 BRA 0x2380 ;
PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ;
LDS R15, [R11+-0x80] ;
IADD3 R14, R14, -0x10, RZ ;
IADD3 R9, R9, 0x10, RZ ;
LDS R16, [R10] ;
FSETP.GEU.AND P3, PT, R15, R16, PT ;
@!P3 STS [R11+-0x80], R16 ;
LDS R17, [R13] ;
LDS R15, [R12+-0x80] ;
FSETP.GT.AND P3, PT, R15, R17, PT ;
@P3 STS [R12+-0x80], R17 ;
LDS R18, [R10+0x40] ;
LDS R15, [R11+-0x40] ;
FSETP.GEU.AND P3, PT, R15, R18, PT ;
@!P3 STS [R11+-0x40], R18 ;
LDS R19, [R13+0x40] ;
LDS R15, [R12+-0x40] ;
FSETP.GT.AND P3, PT, R15, R19, PT ;
@P3 STS [R12+-0x40], R19 ;
LDS R16, [R10+0x80] ;
LDS R15, [R11] ;
FSETP.GEU.AND P3, PT, R15, R16, PT ;
@!P3 STS [R11], R16 ;
LDS R17, [R13+0x80] ;
LDS R15, [R12] ;
FSETP.GT.AND P3, PT, R15, R17, PT ;
@P3 STS [R12], R17 ;
LDS R18, [R10+0xc0] ;
LDS R15, [R11+0x40] ;
FSETP.GEU.AND P3, PT, R15, R18, PT ;
@!P3 STS [R11+0x40], R18 ;
LDS R19, [R13+0xc0] ;
LDS R15, [R12+0x40] ;
FSETP.GT.AND P3, PT, R15, R19, PT ;
@P3 STS [R12+0x40], R19 ;
LDS R16, [R10+0x100] ;
LDS R15, [R11+0x80] ;
FSETP.GEU.AND P3, PT, R15, R16, PT ;
@!P3 STS [R11+0x80], R16 ;
LDS R17, [R13+0x100] ;
LDS R15, [R12+0x80] ;
FSETP.GT.AND P3, PT, R15, R17, PT ;
@P3 STS [R12+0x80], R17 ;
LDS R18, [R10+0x140] ;
LDS R15, [R11+0xc0] ;
FSETP.GEU.AND P3, PT, R15, R18, PT ;
@!P3 STS [R11+0xc0], R18 ;
LDS R19, [R13+0x140] ;
LDS R15, [R12+0xc0] ;
FSETP.GT.AND P3, PT, R15, R19, PT ;
@P3 STS [R12+0xc0], R19 ;
LDS R16, [R10+0x180] ;
LDS R15, [R11+0x100] ;
FSETP.GEU.AND P3, PT, R15, R16, PT ;
@!P3 STS [R11+0x100], R16 ;
LDS R17, [R13+0x180] ;
LDS R15, [R12+0x100] ;
FSETP.GT.AND P3, PT, R15, R17, PT ;
@P3 STS [R12+0x100], R17 ;
LDS R18, [R10+0x1c0] ;
LDS R15, [R11+0x140] ;
FSETP.GEU.AND P3, PT, R15, R18, PT ;
@!P3 STS [R11+0x140], R18 ;
LDS R19, [R13+0x1c0] ;
LDS R15, [R12+0x140] ;
FSETP.GT.AND P3, PT, R15, R19, PT ;
@P3 STS [R12+0x140], R19 ;
LDS R16, [R10+0x200] ;
LDS R15, [R11+0x180] ;
FSETP.GEU.AND P3, PT, R15, R16, PT ;
@!P3 STS [R11+0x180], R16 ;
LDS R17, [R13+0x200] ;
LDS R15, [R12+0x180] ;
FSETP.GT.AND P3, PT, R15, R17, PT ;
@P3 STS [R12+0x180], R17 ;
LDS R18, [R10+0x240] ;
LDS R15, [R11+0x1c0] ;
FSETP.GEU.AND P3, PT, R15, R18, PT ;
@!P3 STS [R11+0x1c0], R18 ;
LDS R19, [R13+0x240] ;
LDS R15, [R12+0x1c0] ;
FSETP.GT.AND P3, PT, R15, R19, PT ;
@P3 STS [R12+0x1c0], R19 ;
LDS R16, [R10+0x280] ;
LDS R15, [R11+0x200] ;
FSETP.GEU.AND P3, PT, R15, R16, PT ;
@!P3 STS [R11+0x200], R16 ;
LDS R17, [R13+0x280] ;
LDS R15, [R12+0x200] ;
FSETP.GT.AND P3, PT, R15, R17, PT ;
@P3 STS [R12+0x200], R17 ;
LDS R18, [R10+0x2c0] ;
LDS R15, [R11+0x240] ;
FSETP.GEU.AND P3, PT, R15, R18, PT ;
@!P3 STS [R11+0x240], R18 ;
LDS R19, [R13+0x2c0] ;
LDS R15, [R12+0x240] ;
FSETP.GT.AND P3, PT, R15, R19, PT ;
@P3 STS [R12+0x240], R19 ;
LDS R16, [R10+0x300] ;
LDS R15, [R11+0x280] ;
FSETP.GEU.AND P3, PT, R15, R16, PT ;
@!P3 STS [R11+0x280], R16 ;
LDS R17, [R13+0x300] ;
LDS R15, [R12+0x280] ;
FSETP.GT.AND P3, PT, R15, R17, PT ;
@P3 STS [R12+0x280], R17 ;
LDS R18, [R10+0x340] ;
LDS R15, [R11+0x2c0] ;
FSETP.GEU.AND P3, PT, R15, R18, PT ;
@!P3 STS [R11+0x2c0], R18 ;
LDS R19, [R13+0x340] ;
LDS R15, [R12+0x2c0] ;
FSETP.GT.AND P3, PT, R15, R19, PT ;
@P3 STS [R12+0x2c0], R19 ;
LDS R16, [R10+0x380] ;
LDS R15, [R11+0x300] ;
FSETP.GEU.AND P3, PT, R15, R16, PT ;
@!P3 STS [R11+0x300], R16 ;
LDS R17, [R13+0x380] ;
LDS R15, [R12+0x300] ;
FSETP.GT.AND P3, PT, R15, R17, PT ;
@P3 STS [R12+0x300], R17 ;
LDS R18, [R10+0x3c0] ;
LDS R15, [R11+0x340] ;
IADD3 R10, R10, 0x400, RZ ;
FSETP.GEU.AND P3, PT, R15, R18, PT ;
@!P3 STS [R11+0x340], R18 ;
LDS R19, [R13+0x3c0] ;
LDS R15, [R12+0x340] ;
IADD3 R11, R11, 0x400, RZ ;
IADD3 R13, R13, 0x400, RZ ;
FSETP.GT.AND P3, PT, R15, R19, PT ;
@P3 STS [R12+0x340], R19 ;
ISETP.GT.AND P3, PT, R14, 0xd, PT ;
IADD3 R12, R12, 0x400, RZ ;
@P3 BRA 0x1b00 ;
IADD3 R15, R14, -0x1, RZ ;
ISETP.GT.AND P3, PT, R15, 0x4, PT ;
@!P3 BRA 0x2880 ;
LDS R16, [R10] ;
IADD3 R9, R9, 0x4, RZ ;
IADD3 R14, R14, -0x4, RZ ;
LDS R15, [R11+-0x80] ;
IADD3 R9, R9, 0x4, RZ ;
IADD3 R14, R14, -0x4, RZ ;
FSETP.GEU.AND P0, PT, R15, R16, PT ;
@!P0 STS [R11+-0x80], R16 ;
LDS R17, [R13] ;
LDS R15, [R12+-0x80] ;
FSETP.GT.AND P0, PT, R15, R17, PT ;
@P0 STS [R12+-0x80], R17 ;
LDS R18, [R10+0x40] ;
LDS R15, [R11+-0x40] ;
FSETP.GEU.AND P0, PT, R15, R18, PT ;
@!P0 STS [R11+-0x40], R18 ;
LDS R19, [R13+0x40] ;
LDS R15, [R12+-0x40] ;
FSETP.GT.AND P0, PT, R15, R19, PT ;
@P0 STS [R12+-0x40], R19 ;
LDS R16, [R10+0x80] ;
LDS R15, [R11] ;
FSETP.GEU.AND P0, PT, R15, R16, PT ;
@!P0 STS [R11], R16 ;
LDS R17, [R13+0x80] ;
LDS R15, [R12] ;
FSETP.GT.AND P0, PT, R15, R17, PT ;
@P0 STS [R12], R17 ;
LDS R18, [R10+0xc0] ;
LDS R15, [R11+0x40] ;
FSETP.GEU.AND P0, PT, R15, R18, PT ;
@!P0 STS [R11+0x40], R18 ;
LDS R19, [R13+0xc0] ;
LDS R15, [R12+0x40] ;
FSETP.GT.AND P0, PT, R15, R19, PT ;
@P0 STS [R12+0x40], R19 ;
LDS R20, [R10+0x100] ;
LDS R15, [R11+0x80] ;
FSETP.GEU.AND P0, PT, R15, R20, PT ;
@!P0 STS [R11+0x80], R20 ;
LDS R22, [R13+0x100] ;
LDS R15, [R12+0x80] ;
FSETP.GT.AND P0, PT, R15, R22, PT ;
IADD3 R15, R12, 0x100, RZ ;
@P0 STS [R15+-0x80], R22 ;
LDS R21, [R10+0x140] ;
LDS R16, [R11+0xc0] ;
FSETP.GEU.AND P0, PT, R16, R21, PT ;
IADD3 R16, R11, 0x100, RZ ;
@!P0 STS [R16+-0x40], R21 ;
LDS R18, [R13+0x140] ;
LDS R17, [R12+0xc0] ;
FSETP.GT.AND P0, PT, R17, R18, PT ;
@P0 STS [R15+-0x40], R18 ;
LDS R19, [R10+0x180] ;
LDS R17, [R11+0x100] ;
IADD3 R18, R10, 0x100, RZ ;
FSETP.GEU.AND P0, PT, R17, R19, PT ;
@!P0 STS [R16], R19 ;
LDS R20, [R13+0x180] ;
LDS R17, [R12+0x100] ;
FSETP.GT.AND P0, PT, R17, R20, PT ;
@P0 STS [R15], R20 ;
LDS R17, [R11+0x140] ;
LDS R21, [R10+0x1c0] ;
IADD3 R11, R16, 0x100, RZ ;
IADD3 R10, R18, 0x100, RZ ;
FSETP.GEU.AND P0, PT, R17, R21, PT ;
@!P0 STS [R16+0x40], R21 ;
LDS R17, [R12+0x140] ;
LDS R22, [R13+0x1c0] ;
IADD3 R12, R15, 0x100, RZ ;
FSETP.GT.AND P0, PT, R17, R22, PT ;
IADD3 R17, R13, 0x100, RZ ;
IADD3 R13, R17, 0x100, RZ ;
@P0 STS [R15+0x40], R22 ;
PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ;
ISETP.NE.OR P0, PT, R14, 0x1, P0 ;
@!P0 BRA 0x2b20 ;
LDS R15, [R11+-0x80] ;
IADD3 R14, R14, -0x4, RZ ;
IADD3 R9, R9, 0x4, RZ ;
LDS R16, [R10] ;
FSETP.GEU.AND P0, PT, R15, R16, PT ;
@!P0 STS [R11+-0x80], R16 ;
LDS R17, [R13] ;
LDS R15, [R12+-0x80] ;
FSETP.GT.AND P0, PT, R15, R17, PT ;
@P0 STS [R12+-0x80], R17 ;
LDS R18, [R10+0x40] ;
LDS R15, [R11+-0x40] ;
FSETP.GEU.AND P0, PT, R15, R18, PT ;
@!P0 STS [R11+-0x40], R18 ;
LDS R19, [R13+0x40] ;
LDS R15, [R12+-0x40] ;
FSETP.GT.AND P0, PT, R15, R19, PT ;
@P0 STS [R12+-0x40], R19 ;
LDS R16, [R10+0x80] ;
LDS R15, [R11] ;
FSETP.GEU.AND P0, PT, R15, R16, PT ;
@!P0 STS [R11], R16 ;
LDS R17, [R13+0x80] ;
LDS R15, [R12] ;
FSETP.GT.AND P0, PT, R15, R17, PT ;
@P0 STS [R12], R17 ;
LDS R18, [R10+0xc0] ;
LDS R15, [R11+0x40] ;
IADD3 R10, R10, 0x100, RZ ;
FSETP.GEU.AND P0, PT, R15, R18, PT ;
@!P0 STS [R11+0x40], R18 ;
LDS R19, [R13+0xc0] ;
LDS R15, [R12+0x40] ;
IADD3 R11, R11, 0x100, RZ ;
IADD3 R13, R13, 0x100, RZ ;
FSETP.GT.AND P0, PT, R15, R19, PT ;
@P0 STS [R12+0x40], R19 ;
ISETP.NE.AND P0, PT, R14, 0x1, PT ;
IADD3 R12, R12, 0x100, RZ ;
@P0 BRA 0x28a0 ;
ISETP.NE.AND P0, PT, R3, RZ, PT ;
@!P0 BRA 0x2d40 ;
IMAD R8, R9.reuse, 0x10, R8 ;
IMAD R9, R9, 0x10, R0 ;
IMAD.SHL.U32 R10, R8, 0x4, RZ ;
IMAD.SHL.U32 R9, R9, 0x4, RZ ;
LDS R11, [R10] ;
LDS R8, [R9] ;
FSETP.GEU.AND P0, PT, R8, R11, PT ;
LDS R8, [R9+0x600] ;
@!P0 STS [R9], R11 ;
LDS R12, [R10+0x600] ;
FSETP.GT.AND P0, PT, R8, R12, PT ;
@P0 STS [R9+0x600], R12 ;
ISETP.NE.AND P0, PT, R3, 0x1, PT ;
@!P0 BRA 0x2d40 ;
LDS R11, [R10+0x40] ;
LDS R8, [R9+0x40] ;
FSETP.GEU.AND P0, PT, R8, R11, PT ;
LDS R8, [R9+0x640] ;
@!P0 STS [R9+0x40], R11 ;
LDS R12, [R10+0x640] ;
FSETP.GT.AND P0, PT, R8, R12, PT ;
@P0 STS [R9+0x640], R12 ;
ISETP.NE.AND P0, PT, R3, 0x2, PT ;
@!P0 BRA 0x2d40 ;
LDS R11, [R10+0x80] ;
LDS R8, [R9+0x80] ;
FSETP.GEU.AND P0, PT, R8, R11, PT ;
LDS R8, [R9+0x680] ;
@!P0 STS [R9+0x80], R11 ;
LDS R12, [R10+0x680] ;
FSETP.GT.AND P0, PT, R8, R12, PT ;
@P0 STS [R9+0x680], R12 ;
BSYNC B0 ;
IADD3 R4, R4, 0x1, RZ ;
BAR.SYNC.DEFER_BLOCKING 0x0 ;
ULEA UR4, UR4, 0x1, 0x1 ;
ISETP.GE.AND P0, PT, R4, c[0x0][0x188], PT ;
@P0 CALL.REL.NOINC 0x2db0 ;
BRA 0x1990 ;
ISETP.NE.OR P1, PT, R0, RZ, !P1 ;
@P1 EXIT ;
IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x164] ;
UMOV UR4, URZ ;
IADD3 R2, R0.reuse, -0x2, RZ ;
IADD3 R0, R0, -0x1, RZ ;
ISETP.GE.U32.AND P0, PT, R2, 0x3, PT ;
LOP3.LUT R0, R0, 0x3, RZ, 0xc0, !PT ;
@!P0 BRA 0x3910 ;
IADD3 R6, -R0, c[0x0][0x164], RZ ;
UMOV UR4, URZ ;
IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x180] ;
UMOV UR5, URZ ;
ISETP.GT.AND P0, PT, R6, 0x1, PT ;
UMOV UR6, 0x600 ;
IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x184] ;
IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x178] ;
IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x17c] ;
@!P0 BRA 0x3730 ;
IADD3 R7, R6, -0x1, RZ ;
PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ;
ISETP.GT.AND P1, PT, R7, 0xc, PT ;
@!P1 BRA 0x3410 ;
PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ;
LDS R7, [UR5] ;
IADD3 R6, R6, -0x10, RZ ;
UIADD3 UR4, UR4, 0x10, URZ ;
LDS R9, [UR6] ;
ISETP.GT.AND P1, PT, R6, 0xd, PT ;
LDS R11, [UR5+0x40] ;
LDS R13, [UR6+0x40] ;
LDS R15, [UR5+0x80] ;
LDS R17, [UR6+0x80] ;
LDS R19, [UR5+0xc0] ;
LDS R21, [UR6+0xc0] ;
LDS R23, [UR5+0x100] ;
LDS R25, [UR6+0x100] ;
LDS R27, [UR5+0x140] ;
LDS R29, [UR6+0x140] ;
STG.E [R2.64], R7 ;
LDS R8, [UR5+0x180] ;
STG.E [R4.64], R9 ;
LDS R7, [UR6+0x180] ;
STG.E [R2.64+0x4], R11 ;
LDS R9, [UR5+0x1c0] ;
STG.E [R4.64+0x4], R13 ;
LDS R11, [UR6+0x1c0] ;
STG.E [R2.64+0x8], R15 ;
LDS R13, [UR5+0x200] ;
STG.E [R4.64+0x8], R17 ;
LDS R15, [UR6+0x200] ;
STG.E [R2.64+0xc], R19 ;
LDS R17, [UR5+0x240] ;
STG.E [R4.64+0xc], R21 ;
LDS R19, [UR6+0x240] ;
STG.E [R2.64+0x10], R23 ;
LDS R21, [UR5+0x280] ;
STG.E [R4.64+0x10], R25 ;
LDS R23, [UR6+0x280] ;
STG.E [R2.64+0x14], R27 ;
LDS R25, [UR5+0x2c0] ;
STG.E [R4.64+0x14], R29 ;
LDS R27, [UR6+0x2c0] ;
LDS R29, [UR5+0x300] ;
LDS R10, [UR6+0x300] ;
LDS R12, [UR5+0x340] ;
LDS R14, [UR6+0x340] ;
LDS R16, [UR5+0x380] ;
LDS R18, [UR6+0x380] ;
LDS R20, [UR5+0x3c0] ;
UIADD3 UR5, UR5, 0x400, URZ ;
LDS R22, [UR6+0x3c0] ;
UIADD3 UR6, UR6, 0x400, URZ ;
STG.E [R2.64+0x18], R8 ;
STG.E [R4.64+0x18], R7 ;
STG.E [R2.64+0x1c], R9 ;
STG.E [R4.64+0x1c], R11 ;
STG.E [R2.64+0x20], R13 ;
IADD3 R7, P3, R4, 0x40, RZ ;
STG.E [R4.64+0x20], R15 ;
IADD3 R9, P2, R2, 0x40, RZ ;
IMAD.X R8, RZ, RZ, R5, P3 ;
STG.E [R2.64+0x24], R17 ;
STG.E [R4.64+0x24], R19 ;
STG.E [R2.64+0x28], R21 ;
STG.E [R4.64+0x28], R23 ;
STG.E [R2.64+0x2c], R25 ;
STG.E [R4.64+0x2c], R27 ;
STG.E [R2.64+0x30], R29 ;
STG.E [R4.64+0x30], R10 ;
STG.E [R2.64+0x34], R12 ;
STG.E [R4.64+0x34], R14 ;
STG.E [R2.64+0x38], R16 ;
IMAD.X R10, RZ, RZ, R3, P2 ;
STG.E [R4.64+0x38], R18 ;
STG.E [R2.64+0x3c], R20 ;
STG.E [R4.64+0x3c], R22 ;
IMAD.MOV.U32 R2, RZ, RZ, R9 ;
IMAD.MOV.U32 R3, RZ, RZ, R10 ;
IMAD.MOV.U32 R4, RZ, RZ, R7 ;
IMAD.MOV.U32 R5, RZ, RZ, R8 ;
@P1 BRA 0x2f30 ;
IADD3 R7, R6, -0x1, RZ ;
ISETP.GT.AND P1, PT, R7, 0x4, PT ;
@!P1 BRA 0x3710 ;
LDS R7, [UR5] ;
PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ;
UIADD3 UR4, UR4, 0x8, URZ ;
IADD3 R6, R6, -0x8, RZ ;
LDS R9, [UR6] ;
LDS R11, [UR5+0x40] ;
LDS R13, [UR6+0x40] ;
LDS R15, [UR5+0x80] ;
LDS R17, [UR6+0x80] ;
LDS R19, [UR5+0xc0] ;
LDS R21, [UR6+0xc0] ;
LDS R23, [UR5+0x100] ;
LDS R25, [UR6+0x100] ;
LDS R27, [UR5+0x140] ;
LDS R29, [UR6+0x140] ;
LDS R8, [UR5+0x180] ;
LDS R10, [UR6+0x180] ;
LDS R12, [UR5+0x1c0] ;
UIADD3 UR5, UR5, 0x200, URZ ;
LDS R14, [UR6+0x1c0] ;
UIADD3 UR6, UR6, 0x200, URZ ;
STG.E [R2.64], R7 ;
STG.E [R4.64], R9 ;
STG.E [R2.64+0x4], R11 ;
STG.E [R4.64+0x4], R13 ;
IADD3 R7, P2, R4, 0x20, RZ ;
STG.E [R2.64+0x8], R15 ;
IADD3 R9, P1, R2, 0x20, RZ ;
STG.E [R4.64+0x8], R17 ;
IMAD.X R16, RZ, RZ, R3, P1 ;
STG.E [R2.64+0xc], R19 ;
STG.E [R4.64+0xc], R21 ;
STG.E [R2.64+0x10], R23 ;
STG.E [R4.64+0x10], R25 ;
STG.E [R2.64+0x14], R27 ;
STG.E [R4.64+0x14], R29 ;
STG.E [R2.64+0x18], R8 ;
STG.E [R4.64+0x18], R10 ;
STG.E [R2.64+0x1c], R12 ;
IMAD.X R8, RZ, RZ, R5, P2 ;
STG.E [R4.64+0x1c], R14 ;
IMAD.MOV.U32 R2, RZ, RZ, R9 ;
IMAD.MOV.U32 R3, RZ, RZ, R16 ;
IMAD.MOV.U32 R4, RZ, RZ, R7 ;
IMAD.MOV.U32 R5, RZ, RZ, R8 ;
ISETP.NE.OR P0, PT, R6, 0x1, P0 ;
@!P0 BRA 0x3910 ;
LDS R7, [UR5] ;
IADD3 R6, R6, -0x4, RZ ;
UIADD3 UR4, UR4, 0x4, URZ ;
IADD3 R10, P1, R2, 0x10, RZ ;
LDS R9, [UR6] ;
ISETP.NE.AND P0, PT, R6, 0x1, PT ;
LDS R11, [UR5+0x40] ;
LDS R13, [UR6+0x40] ;
LDS R15, [UR5+0x80] ;
LDS R17, [UR6+0x80] ;
LDS R19, [UR5+0xc0] ;
UIADD3 UR5, UR5, 0x100, URZ ;
LDS R21, [UR6+0xc0] ;
UIADD3 UR6, UR6, 0x100, URZ ;
STG.E [R2.64], R7 ;
STG.E [R4.64], R9 ;
STG.E [R2.64+0x4], R11 ;
IADD3 R7, P2, R4, 0x10, RZ ;
STG.E [R4.64+0x4], R13 ;
STG.E [R2.64+0x8], R15 ;
IMAD.X R8, RZ, RZ, R5, P2 ;
IMAD.X R11, RZ, RZ, R3, P1 ;
STG.E [R4.64+0x8], R17 ;
STG.E [R2.64+0xc], R19 ;
STG.E [R4.64+0xc], R21 ;
IMAD.MOV.U32 R2, RZ, RZ, R10 ;
IMAD.MOV.U32 R3, RZ, RZ, R11 ;
IMAD.MOV.U32 R4, RZ, RZ, R7 ;
IMAD.MOV.U32 R5, RZ, RZ, R8 ;
@P0 BRA 0x3730 ;
ISETP.NE.AND P0, PT, R0, RZ, PT ;
@!P0 EXIT ;
UMOV UR5, 0x4 ;
ULDC.64 UR6, c[0x0][0x180] ;
USHF.L.U32 UR10, UR4, 0x6, URZ ;
ULDC.64 UR8, c[0x0][0x178] ;
UIMAD.WIDE UR6, UR4, UR5, UR6 ;
UIMAD.WIDE UR4, UR4, UR5, UR8 ;
UIADD3 UR8, UR10, 0x600, URZ ;
LDS R7, [UR10] ;
IMAD.U32 R2, RZ, RZ, UR4 ;
IADD3 R0, R0, -0x1, RZ ;
IMAD.U32 R3, RZ, RZ, UR5 ;
LDS R9, [UR8] ;
IMAD.U32 R4, RZ, RZ, UR6 ;
ISETP.NE.AND P0, PT, R0, RZ, PT ;
IMAD.U32 R5, RZ, RZ, UR7 ;
UIADD3 UR6, UP0, UR6, 0x4, URZ ;
UIADD3 UR4, UP1, UR4, 0x4, URZ ;
UIADD3 UR10, UR10, 0x40, URZ ;
UIADD3 UR8, UR8, 0x40, URZ ;
UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ;
UIADD3.X UR5, URZ, UR5, URZ, UP1, !UPT ;
STG.E [R2.64], R7 ;
STG.E [R4.64], R9 ;
@P0 BRA 0x39a0 ;
EXIT ;
BRA 0x3ac0;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
```
|
```amdasm
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z17FindMaxMinPerGridiiPfS_S_S_i ; -- Begin function _Z17FindMaxMinPerGridiiPfS_S_S_i
.globl _Z17FindMaxMinPerGridiiPfS_S_S_i
.p2align 8
.type _Z17FindMaxMinPerGridiiPfS_S_S_i,@function
_Z17FindMaxMinPerGridiiPfS_S_S_i: ; @_Z17FindMaxMinPerGridiiPfS_S_S_i
; %bb.0:
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x0
s_load_b256 s[4:11], s[0:1], 0x8
v_lshlrev_b32_e32 v4, 2, v0
s_waitcnt lgkmcnt(0)
v_cmp_gt_u32_e32 vcc_lo, s2, v0
s_cmp_gt_i32 s3, 1
s_cselect_b32 s14, -1, 0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s13, vcc_lo, s14
s_and_saveexec_b32 s12, s13
s_cbranch_execz .LBB0_3
; %bb.1: ; %.lr.ph.preheader
v_dual_mov_b32 v2, 0 :: v_dual_lshlrev_b32 v3, 2, v0
v_mov_b32_e32 v1, v0
s_add_i32 s13, s3, -1
.LBB0_2: ; %.lr.ph
; =>This Inner Loop Header: Depth=1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_lshlrev_b64 v[5:6], 2, v[1:2]
v_add_nc_u32_e32 v1, s2, v1
s_add_i32 s13, s13, -1
s_cmp_lg_u32 s13, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v7, vcc_lo, s4, v5
v_add_co_ci_u32_e32 v8, vcc_lo, s5, v6, vcc_lo
v_add_co_u32 v5, vcc_lo, s6, v5
v_add_co_ci_u32_e32 v6, vcc_lo, s7, v6, vcc_lo
global_load_b32 v7, v[7:8], off
global_load_b32 v5, v[5:6], off
s_waitcnt vmcnt(0)
ds_store_2addr_stride64_b32 v3, v7, v5 offset1:6
v_add_nc_u32_e32 v3, 64, v3
s_cbranch_scc1 .LBB0_2
.LBB0_3: ; %Flow190
s_or_b32 exec_lo, exec_lo, s12
s_cmp_lt_i32 s2, 17
s_cbranch_scc1 .LBB0_13
; %bb.4: ; %.lr.ph104
s_add_i32 s12, s2, 15
v_add_nc_u32_e32 v1, 16, v0
s_ashr_i32 s13, s12, 31
v_lshlrev_b32_e32 v5, 2, v0
s_lshr_b32 s13, s13, 28
s_mov_b32 s17, 1
s_add_i32 s13, s12, s13
s_mov_b32 s12, s2
s_ashr_i32 s13, s13, 4
s_cmp_lt_i32 s3, 2
s_cselect_b32 s18, -1, 0
s_max_i32 s15, s13, 2
s_ashr_i32 s13, s2, 31
s_add_i32 s16, s3, -1
s_lshl_b64 s[12:13], s[12:13], 2
s_xor_b32 s18, s18, -1
.LBB0_5: ; =>This Loop Header: Depth=1
; Child Loop BB0_7 Depth 2
v_lshl_add_u32 v2, s17, 4, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_gt_i32_e32 vcc_lo, s2, v2
s_and_b32 s20, vcc_lo, s18
s_and_saveexec_b32 s19, s20
s_cbranch_execz .LBB0_12
; %bb.6: ; %.lr.ph102.preheader
; in Loop: Header=BB0_5 Depth=1
v_ashrrev_i32_e32 v2, 31, v1
v_mov_b32_e32 v6, v5
s_mov_b32 s20, s16
s_delay_alu instid0(VALU_DEP_2)
v_lshlrev_b64 v[2:3], 2, v[1:2]
.LBB0_7: ; %.lr.ph102
; Parent Loop BB0_5 Depth=1
; => This Inner Loop Header: Depth=2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v7, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v8, vcc_lo, s5, v3, vcc_lo
s_mov_b32 s21, exec_lo
global_load_b32 v7, v[7:8], off
ds_load_b32 v8, v6
s_waitcnt vmcnt(0) lgkmcnt(0)
v_cmpx_lt_f32_e32 v8, v7
s_cbranch_execz .LBB0_9
; %bb.8: ; in Loop: Header=BB0_7 Depth=2
ds_store_b32 v6, v7
.LBB0_9: ; in Loop: Header=BB0_7 Depth=2
s_or_b32 exec_lo, exec_lo, s21
v_add_co_u32 v7, vcc_lo, s6, v2
v_add_co_ci_u32_e32 v8, vcc_lo, s7, v3, vcc_lo
s_mov_b32 s21, exec_lo
global_load_b32 v7, v[7:8], off
ds_load_b32 v8, v6 offset:1536
s_waitcnt vmcnt(0) lgkmcnt(0)
v_cmpx_gt_f32_e32 v8, v7
s_cbranch_execz .LBB0_11
; %bb.10: ; in Loop: Header=BB0_7 Depth=2
ds_store_b32 v6, v7 offset:1536
.LBB0_11: ; in Loop: Header=BB0_7 Depth=2
s_or_b32 exec_lo, exec_lo, s21
v_add_co_u32 v2, vcc_lo, v2, s12
v_add_co_ci_u32_e32 v3, vcc_lo, s13, v3, vcc_lo
v_add_nc_u32_e32 v6, 64, v6
s_add_i32 s20, s20, -1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_lg_u32 s20, 0
s_cbranch_scc1 .LBB0_7
.LBB0_12: ; %Flow186
; in Loop: Header=BB0_5 Depth=1
s_or_b32 exec_lo, exec_lo, s19
v_add_nc_u32_e32 v1, 16, v1
s_add_i32 s17, s17, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s17, s15
s_cbranch_scc0 .LBB0_5
.LBB0_13: ; %._crit_edge
s_load_b32 s0, s[0:1], 0x28
s_mov_b32 s1, 1
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cmp_lt_i32 s0, 1
s_cbranch_scc1 .LBB0_24
; %bb.14: ; %.lr.ph110
s_cmp_lt_i32 s3, 2
s_mov_b32 s5, 0
s_cselect_b32 s6, -1, 0
s_add_i32 s4, s3, -1
s_xor_b32 s6, s6, -1
.LBB0_15: ; =>This Loop Header: Depth=1
; Child Loop BB0_18 Depth 2
v_and_b32_e32 v1, s1, v0
s_mov_b32 s7, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_eq_u32_e32 0, v1
s_cbranch_execz .LBB0_23
; %bb.16: ; in Loop: Header=BB0_15 Depth=1
v_lshl_add_u32 v1, 1, s5, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_gt_i32_e32 vcc_lo, s2, v1
s_and_b32 s12, vcc_lo, s6
s_and_b32 exec_lo, exec_lo, s12
s_cbranch_execz .LBB0_23
; %bb.17: ; %.lr.ph106.preheader
; in Loop: Header=BB0_15 Depth=1
v_dual_mov_b32 v2, v4 :: v_dual_lshlrev_b32 v1, 2, v1
s_mov_b32 s12, s4
.LBB0_18: ; %.lr.ph106
; Parent Loop BB0_15 Depth=1
; => This Inner Loop Header: Depth=2
ds_load_b32 v5, v2
ds_load_b32 v3, v1
s_mov_b32 s13, exec_lo
s_waitcnt lgkmcnt(0)
v_cmpx_lt_f32_e32 v5, v3
s_cbranch_execz .LBB0_20
; %bb.19: ; in Loop: Header=BB0_18 Depth=2
ds_store_b32 v2, v3
.LBB0_20: ; in Loop: Header=BB0_18 Depth=2
s_or_b32 exec_lo, exec_lo, s13
ds_load_b32 v5, v2 offset:1536
ds_load_b32 v3, v1 offset:1536
s_mov_b32 s13, exec_lo
s_waitcnt lgkmcnt(0)
v_cmpx_gt_f32_e32 v5, v3
s_cbranch_execz .LBB0_22
; %bb.21: ; in Loop: Header=BB0_18 Depth=2
ds_store_b32 v2, v3 offset:1536
.LBB0_22: ; in Loop: Header=BB0_18 Depth=2
s_or_b32 exec_lo, exec_lo, s13
v_add_nc_u32_e32 v2, 64, v2
v_add_nc_u32_e32 v1, 64, v1
s_add_i32 s12, s12, -1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_lg_u32 s12, 0
s_cbranch_scc1 .LBB0_18
.LBB0_23: ; %.loopexit95
; in Loop: Header=BB0_15 Depth=1
s_or_b32 exec_lo, exec_lo, s7
s_lshl_b32 s1, s1, 1
s_add_i32 s5, s5, 1
s_or_b32 s1, s1, 1
s_cmp_eq_u32 s5, s0
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc0 .LBB0_15
.LBB0_24: ; %._crit_edge111
v_cmp_eq_u32_e32 vcc_lo, 0, v0
s_mov_b32 s0, 0
s_and_b32 s1, vcc_lo, s14
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s2, s1
s_cbranch_execz .LBB0_27
; %bb.25: ; %.lr.ph113.preheader
v_mov_b32_e32 v0, 0
s_add_i32 s1, s3, -1
.LBB0_26: ; %.lr.ph113
; =>This Inner Loop Header: Depth=1
v_mov_b32_e32 v1, s0
s_add_i32 s1, s1, -1
s_add_i32 s0, s0, 64
ds_load_2addr_stride64_b32 v[1:2], v1 offset1:6
s_waitcnt lgkmcnt(0)
s_clause 0x1
global_store_b32 v0, v1, s[8:9]
global_store_b32 v0, v2, s[10:11]
s_add_u32 s8, s8, 4
s_addc_u32 s9, s9, 0
s_add_u32 s10, s10, 4
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s1, 0
s_cbranch_scc1 .LBB0_26
.LBB0_27: ; %.loopexit
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z17FindMaxMinPerGridiiPfS_S_S_i
.amdhsa_group_segment_fixed_size 3072
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 44
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 22
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z17FindMaxMinPerGridiiPfS_S_S_i, .Lfunc_end0-_Z17FindMaxMinPerGridiiPfS_S_S_i
; -- End function
.section .AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 840
; NumSgprs: 24
; NumVgprs: 9
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 3072 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 24
; NumVGPRsForWavesPerEU: 9
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object ; @__hip_cuid_
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0 ; 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .offset: 40
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 3072
.kernarg_segment_align: 8
.kernarg_segment_size: 44
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z17FindMaxMinPerGridiiPfS_S_S_i
.private_segment_fixed_size: 0
.sgpr_count: 24
.sgpr_spill_count: 0
.symbol: _Z17FindMaxMinPerGridiiPfS_S_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
```
| 18,447 | 5,261 |
301 |
Convert the following CUDA host assembly code to AMD host assembly:
```cudaasm
.file "tmpxft_00068eae_00000000-6_FindMaxMinPerGrid.cudafe1.cpp"
.text
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z46__device_stub__Z17FindMaxMinPerGridiiPfS_S_S_iiiPfS_S_S_i
.type _Z46__device_stub__Z17FindMaxMinPerGridiiPfS_S_S_iiiPfS_S_S_i, @function
_Z46__device_stub__Z17FindMaxMinPerGridiiPfS_S_S_iiiPfS_S_S_i:
.LFB2051:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movl %edi, 44(%rsp)
movl %esi, 40(%rsp)
movq %rdx, 32(%rsp)
movq %rcx, 24(%rsp)
movq %r8, 16(%rsp)
movq %r9, 8(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 44(%rsp), %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rax
movq %rax, 120(%rsp)
leaq 32(%rsp), %rax
movq %rax, 128(%rsp)
leaq 24(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 8(%rsp), %rax
movq %rax, 152(%rsp)
leaq 192(%rsp), %rax
movq %rax, 160(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z17FindMaxMinPerGridiiPfS_S_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z46__device_stub__Z17FindMaxMinPerGridiiPfS_S_S_iiiPfS_S_S_i, .-_Z46__device_stub__Z17FindMaxMinPerGridiiPfS_S_S_iiiPfS_S_S_i
.globl _Z17FindMaxMinPerGridiiPfS_S_S_i
.type _Z17FindMaxMinPerGridiiPfS_S_S_i, @function
_Z17FindMaxMinPerGridiiPfS_S_S_i:
.LFB2052:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
call _Z46__device_stub__Z17FindMaxMinPerGridiiPfS_S_S_iiiPfS_S_S_i
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z17FindMaxMinPerGridiiPfS_S_S_i, .-_Z17FindMaxMinPerGridiiPfS_S_S_i
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z17FindMaxMinPerGridiiPfS_S_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z17FindMaxMinPerGridiiPfS_S_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
```
|
```amdasm
.text
.file "FindMaxMinPerGrid.hip"
.globl _Z32__device_stub__FindMaxMinPerGridiiPfS_S_S_i # -- Begin function _Z32__device_stub__FindMaxMinPerGridiiPfS_S_S_i
.type _Z32__device_stub__FindMaxMinPerGridiiPfS_S_S_i,@function
_Z32__device_stub__FindMaxMinPerGridiiPfS_S_S_i: # @_Z32__device_stub__FindMaxMinPerGridiiPfS_S_S_i
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $160, %rsp
.cfi_def_cfa_offset 208
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 12(%rsp), %rax
movl %edi, (%rax)
leaq 8(%rsp), %rdi
movl %esi, (%rdi)
leaq 56(%rsp), %rsi
movq %rdx, (%rsi)
leaq 48(%rsp), %rdx
movq %rcx, (%rdx)
leaq 40(%rsp), %rcx
movq %r8, (%rcx)
leaq 32(%rsp), %r8
movq %r9, (%r8)
leaq 96(%rsp), %rbx
movq %rax, (%rbx)
movq %rdi, 8(%rbx)
movq %rsi, 16(%rbx)
movq %rdx, 24(%rbx)
movq %rcx, 32(%rbx)
movq %r8, 40(%rbx)
leaq 208(%rsp), %rax
movq %rax, 48(%rbx)
leaq 80(%rsp), %r14
leaq 64(%rsp), %r15
leaq 24(%rsp), %r12
leaq 16(%rsp), %r13
movq %r14, %rdi
movq %r15, %rsi
movq %r12, %rdx
movq %r13, %rcx
callq __hipPopCallConfiguration
movq (%r14), %rsi
movl 8(%r14), %edx
movq (%r15), %rcx
movl 8(%r15), %r8d
movl $_Z17FindMaxMinPerGridiiPfS_S_S_i, %edi
movq %rbx, %r9
pushq (%r13)
.cfi_adjust_cfa_offset 8
pushq (%r12)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $176, %rsp
.cfi_adjust_cfa_offset -176
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z32__device_stub__FindMaxMinPerGridiiPfS_S_S_i, .Lfunc_end0-_Z32__device_stub__FindMaxMinPerGridiiPfS_S_S_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, %rdi
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z17FindMaxMinPerGridiiPfS_S_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z17FindMaxMinPerGridiiPfS_S_S_i,@object # @_Z17FindMaxMinPerGridiiPfS_S_S_i
.section .rodata,"a",@progbits
.globl _Z17FindMaxMinPerGridiiPfS_S_S_i
.p2align 3, 0x0
_Z17FindMaxMinPerGridiiPfS_S_S_i:
.quad _Z32__device_stub__FindMaxMinPerGridiiPfS_S_S_i
.size _Z17FindMaxMinPerGridiiPfS_S_S_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z17FindMaxMinPerGridiiPfS_S_S_i"
.size .L__unnamed_1, 33
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z32__device_stub__FindMaxMinPerGridiiPfS_S_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z17FindMaxMinPerGridiiPfS_S_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
```
| 2,128 | 2,276 |
302 |
Convert the following CUDA device assembly code to AMD device assembly:
```cudaasm
code for sm_80
Function : _Z3addPiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ;
IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x160] ;
MOV R5, c[0x0][0x16c] ;
IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x168] ;
MOV R3, c[0x0][0x164] ;
ULDC.64 UR4, c[0x0][0x118] ;
LDG.E R5, [R4.64] ;
LDG.E R2, [R2.64] ;
IMAD.MOV.U32 R6, RZ, RZ, c[0x0][0x170] ;
MOV R7, c[0x0][0x174] ;
IADD3 R9, R2, R5, RZ ;
STG.E [R6.64], R9 ;
EXIT ;
BRA 0xd0;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
```
|
```amdasm
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3addPiS_S_ ; -- Begin function _Z3addPiS_S_
.globl _Z3addPiS_S_
.p2align 8
.type _Z3addPiS_S_,@function
_Z3addPiS_S_: ; @_Z3addPiS_S_
; %bb.0:
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_load_b32 s2, s[4:5], 0x0
s_load_b32 s3, s[6:7], 0x0
s_waitcnt lgkmcnt(0)
s_add_i32 s2, s3, s2
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
global_store_b32 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3addPiS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 8
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3addPiS_S_, .Lfunc_end0-_Z3addPiS_S_
; -- End function
.section .AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 80
; NumSgprs: 8
; NumVgprs: 2
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 0
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 8
; NumVGPRsForWavesPerEU: 2
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object ; @__hip_cuid_
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0 ; 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3addPiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 8
.sgpr_spill_count: 0
.symbol: _Z3addPiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
```
| 340 | 1,783 |
303 |
Convert the following CUDA host assembly code to AMD host assembly:
```cudaasm
.file "tmpxft_00051007_00000000-6_example1.cudafe1.cpp"
.text
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z26__device_stub__Z3addPiS_S_PiS_S_
.type _Z26__device_stub__Z3addPiS_S_PiS_S_, @function
_Z26__device_stub__Z3addPiS_S_PiS_S_:
.LFB2082:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z3addPiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z26__device_stub__Z3addPiS_S_PiS_S_, .-_Z26__device_stub__Z3addPiS_S_PiS_S_
.globl _Z3addPiS_S_
.type _Z3addPiS_S_, @function
_Z3addPiS_S_:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z3addPiS_S_PiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z3addPiS_S_, .-_Z3addPiS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%d + %d = %d\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
movl $7, (%rsp)
movl $2, 4(%rsp)
movq %rsp, %rsi
movl $1, %ecx
movl $4, %edx
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
leaq 4(%rsp), %rsi
movl $1, %ecx
movl $4, %edx
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L15
.L12:
leaq 44(%rsp), %rdi
movl $2, %ecx
movl $4, %edx
movq 24(%rsp), %rsi
call cudaMemcpy@PLT
movl 44(%rsp), %r8d
movl 4(%rsp), %ecx
movl (%rsp), %edx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L16
movl $0, %eax
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z26__device_stub__Z3addPiS_S_PiS_S_
jmp .L12
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC1:
.string "_Z3addPiS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z3addPiS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
```
|
```amdasm
.text
.file "example1.hip"
.globl _Z18__device_stub__addPiS_S_ # -- Begin function _Z18__device_stub__addPiS_S_
.type _Z18__device_stub__addPiS_S_,@function
_Z18__device_stub__addPiS_S_: # @_Z18__device_stub__addPiS_S_
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $112, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 40(%rsp), %rax
movq %rdi, (%rax)
leaq 32(%rsp), %rcx
movq %rsi, (%rcx)
leaq 24(%rsp), %rsi
movq %rdx, (%rsi)
leaq 80(%rsp), %rbx
movq %rax, (%rbx)
movq %rcx, 8(%rbx)
movq %rsi, 16(%rbx)
leaq 64(%rsp), %r14
leaq 48(%rsp), %r15
leaq 16(%rsp), %r12
leaq 8(%rsp), %r13
movq %r14, %rdi
movq %r15, %rsi
movq %r12, %rdx
movq %r13, %rcx
callq __hipPopCallConfiguration
movq (%r14), %rsi
movl 8(%r14), %edx
movq (%r15), %rcx
movl 8(%r15), %r8d
movl $_Z3addPiS_S_, %edi
movq %rbx, %r9
pushq (%r13)
.cfi_adjust_cfa_offset 8
pushq (%r12)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $128, %rsp
.cfi_adjust_cfa_offset -128
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z18__device_stub__addPiS_S_, .Lfunc_end0-_Z18__device_stub__addPiS_S_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $48, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 32(%rsp), %rbx
movl $4, %esi
movq %rbx, %rdi
callq hipMalloc
leaq 24(%rsp), %r14
movl $4, %esi
movq %r14, %rdi
callq hipMalloc
leaq 16(%rsp), %rdi
movl $4, %esi
callq hipMalloc
leaq 12(%rsp), %rsi
movl $7, (%rsi)
leaq 8(%rsp), %r15
movl $2, (%r15)
movq (%rbx), %rdi
movl $4, %edx
movl $1, %ecx
callq hipMemcpy
movq (%r14), %rdi
movl $4, %edx
movq %r15, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq 32(%rsp), %rdi
movq 24(%rsp), %rsi
movq 16(%rsp), %rdx
callq _Z18__device_stub__addPiS_S_
.LBB1_2:
movq 16(%rsp), %rsi
leaq 44(%rsp), %rbx
movl $4, %edx
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
movl 12(%rsp), %esi
movl 8(%rsp), %edx
movl (%rbx), %ecx
movl $.L.str, %edi
xorl %eax, %eax
callq printf
xorl %eax, %eax
addq $48, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, %rdi
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3addPiS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3addPiS_S_,@object # @_Z3addPiS_S_
.section .rodata,"a",@progbits
.globl _Z3addPiS_S_
.p2align 3, 0x0
_Z3addPiS_S_:
.quad _Z18__device_stub__addPiS_S_
.size _Z3addPiS_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%d + %d = %d\n"
.size .L.str, 14
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z3addPiS_S_"
.size .L__unnamed_1, 13
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__addPiS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3addPiS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
```
| 2,583 | 2,834 |
304 |
Convert the following CUDA device assembly code to AMD device assembly:
```cudaasm
code for sm_80
```
|
```amdasm
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object ; @__hip_cuid_
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0 ; 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
```
| 24 | 306 |
305 |
Convert the following CUDA host assembly code to AMD host assembly:
```cudaasm
.file "tmpxft_000fc589_00000000-6_main.cudafe1.cpp"
.text
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2030:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl main
.type main, @function
main:
.LFB2027:
.cfi_startproc
endbr64
movl $0, %eax
ret
.cfi_endproc
.LFE2027:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2053:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2053:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
```
|
```amdasm
.text
.file "main.hip"
.globl main # -- Begin function main
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
xorl %eax, %eax
retq
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
```
| 809 | 260 |
306 |
Convert the following CUDA device assembly code to AMD device assembly:
```cudaasm
code for sm_80
Function : _Z17find_closest_minePfS_PiiiS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ;
S2R R9, SR_CTAID.X ;
HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ;
ULDC.64 UR6, c[0x0][0x118] ;
S2R R0, SR_TID.X ;
S2R R10, SR_CTAID.Y ;
ISETP.LE.AND P0, PT, R5, c[0x0][0x17c], PT ;
IMAD R9, R9, c[0x0][0xc], R0 ;
IMAD R0, R10, c[0x0][0x17c], R9 ;
IMAD.WIDE.U32 R2, R0, R5, c[0x0][0x170] ;
STG.E [R2.64], R9 ;
@!P0 BRA 0x250 ;
LEA R4, P0, R0, c[0x0][0x168], 0x2 ;
ULDC UR4, c[0x0][0x17c] ;
LEA.HI.X R5, R0, c[0x0][0x16c], RZ, 0x2, P0 ;
ULEA.HI UR5, UR4, UR4, URZ, 0x1 ;
IMAD.U32 R6, RZ, RZ, UR4 ;
BAR.SYNC.DEFER_BLOCKING 0x0 ;
USHF.R.S32.HI UR4, URZ, 0x1, UR5 ;
ISETP.GT.AND P0, PT, R6, 0x7, PT ;
BSSY B0, 0x240 ;
ISETP.GE.AND P1, PT, R9, UR4, PT ;
@P1 BRA 0x230 ;
HFMA2.MMA R6, -RZ, RZ, 0, 2.384185791015625e-07 ;
IADD3 R11, R0, UR4, RZ ;
LDG.E R8, [R4.64] ;
IMAD.WIDE.U32 R6, R11, R6, c[0x0][0x168] ;
LDG.E R13, [R6.64] ;
FSETP.GEU.AND P1, PT, R8, R13, PT ;
@P1 BRA 0x230 ;
LEA R6, P1, R11.reuse, c[0x0][0x170], 0x2 ;
STG.E [R4.64], R13 ;
LEA.HI.X R7, R11, c[0x0][0x174], RZ, 0x2, P1 ;
LDG.E R7, [R6.64] ;
STG.E [R2.64], R7 ;
BSYNC B0 ;
@P0 BRA 0xf0 ;
IMAD.MOV.U32 R9, RZ, RZ, 0x4 ;
IMAD.WIDE.U32 R2, R10, R9, c[0x0][0x170] ;
LDG.E R0, [R2.64] ;
SHF.L.U32 R0, R0, 0x1, RZ ;
IMAD.WIDE R4, R0, R9, c[0x0][0x160] ;
LDG.E R5, [R4.64] ;
IMAD.SHL.U32 R6, R10, 0x4, RZ ;
IMAD.WIDE.U32 R6, R6, R9, c[0x0][0x180] ;
STG.E [R6.64], R5 ;
LDG.E R0, [R2.64] ;
LEA R0, R0, 0x1, 0x1 ;
IMAD.WIDE R8, R0, R9, c[0x0][0x160] ;
LDG.E R9, [R8.64] ;
STG.E [R6.64+0x4], R9 ;
EXIT ;
BRA 0x340;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
```
|
```amdasm
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z17find_closest_minePfS_PiiiS_ ; -- Begin function _Z17find_closest_minePfS_PiiiS_
.globl _Z17find_closest_minePfS_PiiiS_
.p2align 8
.type _Z17find_closest_minePfS_PiiiS_,@function
_Z17find_closest_minePfS_PiiiS_: ; @_Z17find_closest_minePfS_PiiiS_
; %bb.0:
s_clause 0x2
s_load_b32 s4, s[0:1], 0x28
s_load_b32 s3, s[0:1], 0x1c
s_load_b64 s[8:9], s[0:1], 0x10
s_mov_b32 s2, s15
s_waitcnt lgkmcnt(0)
v_mad_u64_u32 v[2:3], null, s4, s14, v[0:1]
s_load_b128 s[4:7], s[0:1], 0x0
v_mov_b32_e32 v1, 0
s_cmp_lt_i32 s3, 4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[3:4], null, s2, s3, v[2:3]
v_mov_b32_e32 v4, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[6:7], 2, v[3:4]
v_add_co_u32 v4, vcc_lo, s8, v6
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v5, vcc_lo, s9, v7, vcc_lo
global_store_b32 v[4:5], v2, off
s_cbranch_scc1 .LBB0_6
; %bb.1: ; %.lr.ph
s_waitcnt lgkmcnt(0)
v_add_co_u32 v6, vcc_lo, s6, v6
v_add_co_ci_u32_e32 v7, vcc_lo, s7, v7, vcc_lo
.LBB0_2: ; =>This Inner Loop Header: Depth=1
s_mov_b32 s10, s3
s_lshr_b32 s3, s3, 1
s_mov_b32 s11, exec_lo
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
v_cmpx_gt_i32_e64 s3, v2
s_cbranch_execz .LBB0_5
; %bb.3: ; in Loop: Header=BB0_2 Depth=1
v_add_nc_u32_e32 v0, s3, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[8:9], 2, v[0:1]
v_add_co_u32 v10, vcc_lo, s6, v8
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v11, vcc_lo, s7, v9, vcc_lo
s_clause 0x1
global_load_b32 v12, v[6:7], off
global_load_b32 v0, v[10:11], off
s_waitcnt vmcnt(0)
v_cmp_lt_f32_e32 vcc_lo, v12, v0
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_5
; %bb.4: ; in Loop: Header=BB0_2 Depth=1
v_add_co_u32 v8, vcc_lo, s8, v8
v_add_co_ci_u32_e32 v9, vcc_lo, s9, v9, vcc_lo
global_load_b32 v8, v[8:9], off
global_store_b32 v[6:7], v0, off
s_waitcnt vmcnt(0)
global_store_b32 v[4:5], v8, off
.LBB0_5: ; in Loop: Header=BB0_2 Depth=1
s_or_b32 exec_lo, exec_lo, s11
s_cmp_lt_u32 s10, 8
s_cbranch_scc0 .LBB0_2
.LBB0_6: ; %._crit_edge
s_mov_b32 s3, 0
s_load_b64 s[0:1], s[0:1], 0x20
s_waitcnt lgkmcnt(0)
s_lshl_b64 s[6:7], s[2:3], 2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
s_add_u32 s6, s8, s6
s_addc_u32 s7, s9, s7
global_load_b32 v0, v1, s[6:7]
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s6, v0
s_lshl_b32 s6, s6, 1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_ashr_i32 s7, s6, 31
s_lshl_b64 s[6:7], s[6:7], 2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
s_add_u32 s4, s4, s6
s_addc_u32 s5, s5, s7
s_lshl_b32 s2, s2, 2
global_load_b32 v0, v1, s[4:5]
s_lshl_b64 s[2:3], s[2:3], 2
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
s_waitcnt vmcnt(0)
global_store_b32 v1, v0, s[0:1]
global_load_b32 v0, v1, s[4:5] offset:4
s_waitcnt vmcnt(0)
global_store_b32 v1, v0, s[0:1] offset:4
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z17find_closest_minePfS_PiiiS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 13
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z17find_closest_minePfS_PiiiS_, .Lfunc_end0-_Z17find_closest_minePfS_PiiiS_
; -- End function
.section .AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 436
; NumSgprs: 18
; NumVgprs: 13
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 13
; Occupancy: 16
; WaveLimiterHint : 1
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object ; @__hip_cuid_
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0 ; 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z17find_closest_minePfS_PiiiS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z17find_closest_minePfS_PiiiS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 13
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
```
| 1,123 | 3,652 |
307 |
Convert the following CUDA host assembly code to AMD host assembly:
```cudaasm
.file "tmpxft_001b0a87_00000000-6_find_closest_mine.cudafe1.cpp"
.text
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z45__device_stub__Z17find_closest_minePfS_PiiiS_PfS_PiiiS_
.type _Z45__device_stub__Z17find_closest_minePfS_PiiiS_PfS_PiiiS_, @function
_Z45__device_stub__Z17find_closest_minePfS_PiiiS_PfS_PiiiS_:
.LFB2051:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movq %r9, 8(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 8(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z17find_closest_minePfS_PiiiS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z45__device_stub__Z17find_closest_minePfS_PiiiS_PfS_PiiiS_, .-_Z45__device_stub__Z17find_closest_minePfS_PiiiS_PfS_PiiiS_
.globl _Z17find_closest_minePfS_PiiiS_
.type _Z17find_closest_minePfS_PiiiS_, @function
_Z17find_closest_minePfS_PiiiS_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z45__device_stub__Z17find_closest_minePfS_PiiiS_PfS_PiiiS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z17find_closest_minePfS_PiiiS_, .-_Z17find_closest_minePfS_PiiiS_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z17find_closest_minePfS_PiiiS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z17find_closest_minePfS_PiiiS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
```
|
```amdasm
.text
.file "find_closest_mine.hip"
.globl _Z32__device_stub__find_closest_minePfS_PiiiS_ # -- Begin function _Z32__device_stub__find_closest_minePfS_PiiiS_
.type _Z32__device_stub__find_closest_minePfS_PiiiS_,@function
_Z32__device_stub__find_closest_minePfS_PiiiS_: # @_Z32__device_stub__find_closest_minePfS_PiiiS_
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $144, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 56(%rsp), %rax
movq %rdi, (%rax)
leaq 48(%rsp), %rdi
movq %rsi, (%rdi)
leaq 40(%rsp), %rsi
movq %rdx, (%rsi)
leaq 12(%rsp), %rdx
movl %ecx, (%rdx)
leaq 8(%rsp), %rcx
movl %r8d, (%rcx)
leaq 32(%rsp), %r8
movq %r9, (%r8)
leaq 96(%rsp), %rbx
movq %rax, (%rbx)
movq %rdi, 8(%rbx)
movq %rsi, 16(%rbx)
movq %rdx, 24(%rbx)
movq %rcx, 32(%rbx)
movq %r8, 40(%rbx)
leaq 80(%rsp), %r14
leaq 64(%rsp), %r15
leaq 24(%rsp), %r12
leaq 16(%rsp), %r13
movq %r14, %rdi
movq %r15, %rsi
movq %r12, %rdx
movq %r13, %rcx
callq __hipPopCallConfiguration
movq (%r14), %rsi
movl 8(%r14), %edx
movq (%r15), %rcx
movl 8(%r15), %r8d
movl $_Z17find_closest_minePfS_PiiiS_, %edi
movq %rbx, %r9
pushq (%r13)
.cfi_adjust_cfa_offset 8
pushq (%r12)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $160, %rsp
.cfi_adjust_cfa_offset -160
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z32__device_stub__find_closest_minePfS_PiiiS_, .Lfunc_end0-_Z32__device_stub__find_closest_minePfS_PiiiS_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, %rdi
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z17find_closest_minePfS_PiiiS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z17find_closest_minePfS_PiiiS_,@object # @_Z17find_closest_minePfS_PiiiS_
.section .rodata,"a",@progbits
.globl _Z17find_closest_minePfS_PiiiS_
.p2align 3, 0x0
_Z17find_closest_minePfS_PiiiS_:
.quad _Z32__device_stub__find_closest_minePfS_PiiiS_
.size _Z17find_closest_minePfS_PiiiS_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z17find_closest_minePfS_PiiiS_"
.size .L__unnamed_1, 32
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z32__device_stub__find_closest_minePfS_PiiiS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z17find_closest_minePfS_PiiiS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
```
| 2,060 | 2,239 |
310 |
Convert the following CUDA device assembly code to AMD device assembly:
```cudaasm
code for sm_80
Function : _Z10hello_cudav
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ;
MOV R0, 0x0 ;
IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x8] ;
CS2R R6, SRZ ;
IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0xc] ;
LDC.64 R2, c[0x4][R0] ;
LEPC R8 ;
MOV R11, 0xe0 ;
MOV R20, 0x60 ;
MOV R21, 0x0 ;
MOV R0, 0x0 ;
IADD3 R20, P0, P1, -R20, R11, R8 ;
IADD3.X R21, ~R0, R21, R9, P0, P1 ;
CALL.ABS.NOINC R2 ;
EXIT ;
BRA 0xf0;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
```
|
```amdasm
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10hello_cudav ; -- Begin function _Z10hello_cudav
.globl _Z10hello_cudav
.p2align 8
.type _Z10hello_cudav,@function
_Z10hello_cudav: ; @_Z10hello_cudav
; %bb.0:
s_load_b64 s[2:3], s[0:1], 0x50
v_mbcnt_lo_u32_b32 v2, -1, 0
v_mov_b32_e32 v0, 0
v_mov_b32_e32 v1, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mov_b32_e32 v7, v2
;;#ASMSTART
;;#ASMEND
v_readfirstlane_b32 s0, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_eq_u32_e64 s0, s0, v7
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_6
; %bb.1:
v_mov_b32_e32 v3, 0
s_mov_b32 s4, exec_lo
s_waitcnt lgkmcnt(0)
global_load_b64 v[10:11], v3, s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
s_clause 0x1
global_load_b64 v[0:1], v3, s[2:3] offset:40
global_load_b64 v[4:5], v3, s[2:3]
s_waitcnt vmcnt(1)
v_and_b32_e32 v0, v0, v10
v_and_b32_e32 v1, v1, v11
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_hi_u32 v6, v0, 24
v_mul_lo_u32 v1, v1, 24
v_mul_lo_u32 v0, v0, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v1, v6, v1
s_waitcnt vmcnt(0)
v_add_co_u32 v0, vcc_lo, v4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, v5, v1, vcc_lo
global_load_b64 v[8:9], v[0:1], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[0:1], v3, v[8:11], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmpx_ne_u64_e64 v[0:1], v[10:11]
s_cbranch_execz .LBB0_5
; %bb.2: ; %.preheader3.i.i.i.preheader
s_mov_b32 s5, 0
.LBB0_3: ; %.preheader3.i.i.i
; =>This Inner Loop Header: Depth=1
s_sleep 1
s_clause 0x1
global_load_b64 v[4:5], v3, s[2:3] offset:40
global_load_b64 v[8:9], v3, s[2:3]
v_dual_mov_b32 v11, v1 :: v_dual_mov_b32 v10, v0
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_and_b32_e32 v4, v4, v10
v_and_b32_e32 v6, v5, v11
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[0:1], null, v4, 24, v[8:9]
v_mad_u64_u32 v[4:5], null, v6, 24, v[1:2]
s_delay_alu instid0(VALU_DEP_1)
v_mov_b32_e32 v1, v4
global_load_b64 v[8:9], v[0:1], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[0:1], v3, v[8:11], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmp_eq_u64_e32 vcc_lo, v[0:1], v[10:11]
s_or_b32 s5, vcc_lo, s5
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s5
s_cbranch_execnz .LBB0_3
; %bb.4: ; %Flow258
s_or_b32 exec_lo, exec_lo, s5
.LBB0_5: ; %Flow260
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s4
.LBB0_6: ; %.loopexit4.i.i.i
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s1
v_mov_b32_e32 v8, 0
v_readfirstlane_b32 s4, v0
v_readfirstlane_b32 s5, v1
s_mov_b32 s10, exec_lo
s_waitcnt lgkmcnt(0)
s_clause 0x1
global_load_b64 v[9:10], v8, s[2:3] offset:40
global_load_b128 v[3:6], v8, s[2:3]
s_waitcnt vmcnt(1)
v_readfirstlane_b32 s6, v9
v_readfirstlane_b32 s7, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b64 s[6:7], s[4:5], s[6:7]
s_mul_i32 s1, s7, 24
s_mul_hi_u32 s8, s6, 24
s_mul_i32 s9, s6, 24
s_and_saveexec_b32 s11, s0
s_cbranch_execz .LBB0_8
; %bb.7:
v_dual_mov_b32 v9, s10 :: v_dual_mov_b32 v10, v8
s_add_i32 s10, s8, s1
s_waitcnt vmcnt(0)
v_add_co_u32 v0, vcc_lo, v3, s9
v_add_co_ci_u32_e32 v1, vcc_lo, s10, v4, vcc_lo
v_dual_mov_b32 v11, 2 :: v_dual_mov_b32 v12, 1
global_store_b128 v[0:1], v[9:12], off offset:8
.LBB0_8:
s_or_b32 exec_lo, exec_lo, s11
s_lshl_b64 s[6:7], s[6:7], 12
v_lshlrev_b64 v[0:1], 6, v[7:8]
s_waitcnt vmcnt(0)
v_add_co_u32 v5, vcc_lo, v5, s6
v_add_co_ci_u32_e32 v6, vcc_lo, s7, v6, vcc_lo
s_mov_b32 s12, 0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v5, v0
s_mov_b32 s13, s12
s_mov_b32 s14, s12
s_mov_b32 s15, s12
v_add_co_ci_u32_e32 v1, vcc_lo, v6, v1, vcc_lo
v_dual_mov_b32 v7, 33 :: v_dual_mov_b32 v10, v8
v_mov_b32_e32 v9, v8
v_dual_mov_b32 v11, s12 :: v_dual_mov_b32 v14, s15
v_dual_mov_b32 v12, s13 :: v_dual_mov_b32 v13, s14
s_clause 0x3
global_store_b128 v[0:1], v[7:10], off
global_store_b128 v[0:1], v[11:14], off offset:16
global_store_b128 v[0:1], v[11:14], off offset:32
global_store_b128 v[0:1], v[11:14], off offset:48
s_and_saveexec_b32 s6, s0
s_cbranch_execz .LBB0_16
; %bb.9:
v_mov_b32_e32 v11, 0
s_mov_b32 s7, exec_lo
s_clause 0x1
global_load_b64 v[14:15], v11, s[2:3] offset:32 glc
global_load_b64 v[5:6], v11, s[2:3] offset:40
v_dual_mov_b32 v12, s4 :: v_dual_mov_b32 v13, s5
s_waitcnt vmcnt(0)
v_and_b32_e32 v6, s5, v6
v_and_b32_e32 v5, s4, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_lo_u32 v6, v6, 24
v_mul_hi_u32 v7, v5, 24
v_mul_lo_u32 v5, v5, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v6, v7, v6
v_add_co_u32 v9, vcc_lo, v3, v5
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v10, vcc_lo, v4, v6, vcc_lo
global_store_b64 v[9:10], v[14:15], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[7:8], v11, v[12:15], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmpx_ne_u64_e64 v[7:8], v[14:15]
s_cbranch_execz .LBB0_12
; %bb.10: ; %.preheader1.i.i.i.preheader
s_mov_b32 s10, 0
.LBB0_11: ; %.preheader1.i.i.i
; =>This Inner Loop Header: Depth=1
v_dual_mov_b32 v5, s4 :: v_dual_mov_b32 v6, s5
s_sleep 1
global_store_b64 v[9:10], v[7:8], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[5:6], v11, v[5:8], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[5:6], v[7:8]
v_dual_mov_b32 v8, v6 :: v_dual_mov_b32 v7, v5
s_or_b32 s10, vcc_lo, s10
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s10
s_cbranch_execnz .LBB0_11
.LBB0_12: ; %Flow256
s_or_b32 exec_lo, exec_lo, s7
v_mov_b32_e32 v8, 0
s_mov_b32 s10, exec_lo
s_mov_b32 s7, exec_lo
v_mbcnt_lo_u32_b32 v7, s10, 0
global_load_b64 v[5:6], v8, s[2:3] offset:16
v_cmpx_eq_u32_e32 0, v7
s_cbranch_execz .LBB0_14
; %bb.13:
s_bcnt1_i32_b32 s10, s10
s_delay_alu instid0(SALU_CYCLE_1)
v_mov_b32_e32 v7, s10
s_waitcnt vmcnt(0)
global_atomic_add_u64 v[5:6], v[7:8], off offset:8
.LBB0_14:
s_or_b32 exec_lo, exec_lo, s7
s_waitcnt vmcnt(0)
global_load_b64 v[7:8], v[5:6], off offset:16
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, 0, v[7:8]
s_cbranch_vccnz .LBB0_16
; %bb.15:
global_load_b32 v5, v[5:6], off offset:24
v_mov_b32_e32 v6, 0
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s7, v5
s_waitcnt_vscnt null, 0x0
global_store_b64 v[7:8], v[5:6], off
s_and_b32 m0, s7, 0xff
s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_16: ; %Flow257
s_or_b32 exec_lo, exec_lo, s6
s_add_i32 s8, s8, s1
v_add_co_u32 v3, vcc_lo, v3, s9
v_add_co_ci_u32_e32 v4, vcc_lo, s8, v4, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v3, vcc_lo, v3, 20
v_add_co_ci_u32_e32 v4, vcc_lo, 0, v4, vcc_lo
.LBB0_17: ; =>This Inner Loop Header: Depth=1
v_mov_b32_e32 v5, 1
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_19
; %bb.18: ; in Loop: Header=BB0_17 Depth=1
global_load_b32 v5, v[3:4], off glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_and_b32_e32 v5, 1, v5
.LBB0_19: ; in Loop: Header=BB0_17 Depth=1
s_or_b32 exec_lo, exec_lo, s1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s1, v5
s_cmp_eq_u32 s1, 0
s_cbranch_scc1 .LBB0_21
; %bb.20: ; in Loop: Header=BB0_17 Depth=1
s_mov_b32 s1, 0
s_sleep 1
s_branch .LBB0_22
.LBB0_21: ; in Loop: Header=BB0_17 Depth=1
s_mov_b32 s1, -1
.LBB0_22: ; %Flow251
; in Loop: Header=BB0_17 Depth=1
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 vcc_lo, exec_lo, s1
s_cbranch_vccnz .LBB0_17
; %bb.23:
global_load_b64 v[0:1], v[0:1], off
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_27
; %bb.24:
v_mov_b32_e32 v9, 0
s_clause 0x2
global_load_b64 v[5:6], v9, s[2:3] offset:40
global_load_b64 v[10:11], v9, s[2:3] offset:24 glc
global_load_b64 v[7:8], v9, s[2:3]
s_waitcnt vmcnt(2)
v_add_co_u32 v12, vcc_lo, v5, 1
v_add_co_ci_u32_e32 v13, vcc_lo, 0, v6, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v3, vcc_lo, v12, s4
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v13, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_eq_u64_e32 vcc_lo, 0, v[3:4]
v_dual_cndmask_b32 v4, v4, v13 :: v_dual_cndmask_b32 v3, v3, v12
v_and_b32_e32 v6, v4, v6
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_and_b32_e32 v5, v3, v5
v_mul_lo_u32 v6, v6, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_hi_u32 v12, v5, 24
v_mul_lo_u32 v5, v5, 24
v_add_nc_u32_e32 v6, v12, v6
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_co_u32 v7, vcc_lo, v7, v5
v_mov_b32_e32 v5, v10
v_add_co_ci_u32_e32 v8, vcc_lo, v8, v6, vcc_lo
v_mov_b32_e32 v6, v11
global_store_b64 v[7:8], v[10:11], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[5:6], v9, v[3:6], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_ne_u64_e32 vcc_lo, v[5:6], v[10:11]
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_27
; %bb.25: ; %.preheader.i.i.i.preheader
s_mov_b32 s0, 0
.LBB0_26: ; %.preheader.i.i.i
; =>This Inner Loop Header: Depth=1
s_sleep 1
global_store_b64 v[7:8], v[5:6], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[10:11], v9, v[3:6], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[10:11], v[5:6]
v_dual_mov_b32 v5, v10 :: v_dual_mov_b32 v6, v11
s_or_b32 s0, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s0
s_cbranch_execnz .LBB0_26
.LBB0_27: ; %__ockl_printf_begin.exit
s_or_b32 exec_lo, exec_lo, s1
s_getpc_b64 s[4:5]
s_add_u32 s4, s4, .str@rel32@lo+4
s_addc_u32 s5, s5, .str@rel32@hi+12
s_mov_b32 s0, -1
s_cmp_lg_u64 s[4:5], 0
s_cbranch_scc0 .LBB0_113
; %bb.28:
s_waitcnt vmcnt(0)
v_dual_mov_b32 v8, v1 :: v_dual_and_b32 v7, -3, v0
v_dual_mov_b32 v28, 0 :: v_dual_mov_b32 v5, 2
v_mov_b32_e32 v6, 1
s_mov_b64 s[6:7], 19
.LBB0_29: ; =>This Loop Header: Depth=1
; Child Loop BB0_32 Depth 2
; Child Loop BB0_39 Depth 2
; Child Loop BB0_47 Depth 2
; Child Loop BB0_55 Depth 2
; Child Loop BB0_63 Depth 2
; Child Loop BB0_71 Depth 2
; Child Loop BB0_79 Depth 2
; Child Loop BB0_87 Depth 2
; Child Loop BB0_95 Depth 2
; Child Loop BB0_101 Depth 2
; Child Loop BB0_110 Depth 2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_lt_u64_e64 s0, s[6:7], 56
; implicit-def: $sgpr15
s_and_b32 s0, s0, exec_lo
s_cselect_b32 s8, s6, 56
s_cselect_b32 s9, s7, 0
s_cmp_gt_u32 s8, 7
s_mov_b32 s0, -1
s_cbranch_scc1 .LBB0_34
; %bb.30: ; in Loop: Header=BB0_29 Depth=1
s_waitcnt vmcnt(0)
v_mov_b32_e32 v9, 0
v_mov_b32_e32 v10, 0
s_cmp_eq_u32 s8, 0
s_cbranch_scc1 .LBB0_33
; %bb.31: ; %.preheader31.i.preheader
; in Loop: Header=BB0_29 Depth=1
s_lshl_b64 s[0:1], s[8:9], 3
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], s[4:5]
.LBB0_32: ; %.preheader31.i
; Parent Loop BB0_29 Depth=1
; => This Inner Loop Header: Depth=2
global_load_u8 v3, v28, s[12:13]
s_waitcnt vmcnt(0)
v_and_b32_e32 v27, 0xffff, v3
s_delay_alu instid0(VALU_DEP_1)
v_lshlrev_b64 v[3:4], s10, v[27:28]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_add_u32 s12, s12, 1
s_addc_u32 s13, s13, 0
s_cmp_lg_u32 s0, s10
v_or_b32_e32 v9, v3, v9
v_or_b32_e32 v10, v4, v10
s_cbranch_scc1 .LBB0_32
.LBB0_33: ; %Flow226
; in Loop: Header=BB0_29 Depth=1
s_mov_b32 s0, 0
s_mov_b32 s15, 0
.LBB0_34: ; %Flow228
; in Loop: Header=BB0_29 Depth=1
s_and_not1_b32 vcc_lo, exec_lo, s0
s_mov_b64 s[0:1], s[4:5]
s_cbranch_vccnz .LBB0_36
; %bb.35: ; in Loop: Header=BB0_29 Depth=1
global_load_b64 v[9:10], v28, s[4:5]
s_add_i32 s15, s8, -8
s_add_u32 s0, s4, 8
s_addc_u32 s1, s5, 0
.LBB0_36: ; %.loopexit32.i
; in Loop: Header=BB0_29 Depth=1
s_cmp_gt_u32 s15, 7
s_cbranch_scc1 .LBB0_41
; %bb.37: ; in Loop: Header=BB0_29 Depth=1
v_mov_b32_e32 v11, 0
v_mov_b32_e32 v12, 0
s_cmp_eq_u32 s15, 0
s_cbranch_scc1 .LBB0_40
; %bb.38: ; %.preheader29.i.preheader
; in Loop: Header=BB0_29 Depth=1
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_39: ; %.preheader29.i
; Parent Loop BB0_29 Depth=1
; => This Inner Loop Header: Depth=2
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v3, v28, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v27, 0xffff, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], s10, v[27:28]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s15, s12
v_or_b32_e32 v11, v3, v11
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v12, v4, v12
s_cbranch_scc1 .LBB0_39
.LBB0_40: ; %Flow221
; in Loop: Header=BB0_29 Depth=1
s_mov_b32 s10, 0
s_mov_b32 s14, 0
s_branch .LBB0_42
.LBB0_41: ; in Loop: Header=BB0_29 Depth=1
s_mov_b32 s10, -1
; implicit-def: $vgpr11_vgpr12
; implicit-def: $sgpr14
.LBB0_42: ; %Flow223
; in Loop: Header=BB0_29 Depth=1
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 vcc_lo, exec_lo, s10
s_cbranch_vccnz .LBB0_44
; %bb.43: ; in Loop: Header=BB0_29 Depth=1
global_load_b64 v[11:12], v28, s[0:1]
s_add_i32 s14, s15, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_44: ; %.loopexit30.i
; in Loop: Header=BB0_29 Depth=1
s_cmp_gt_u32 s14, 7
s_cbranch_scc1 .LBB0_49
; %bb.45: ; in Loop: Header=BB0_29 Depth=1
v_mov_b32_e32 v13, 0
v_mov_b32_e32 v14, 0
s_cmp_eq_u32 s14, 0
s_cbranch_scc1 .LBB0_48
; %bb.46: ; %.preheader27.i.preheader
; in Loop: Header=BB0_29 Depth=1
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_47: ; %.preheader27.i
; Parent Loop BB0_29 Depth=1
; => This Inner Loop Header: Depth=2
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v3, v28, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v27, 0xffff, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], s10, v[27:28]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s14, s12
v_or_b32_e32 v13, v3, v13
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v14, v4, v14
s_cbranch_scc1 .LBB0_47
.LBB0_48: ; %Flow216
; in Loop: Header=BB0_29 Depth=1
s_mov_b32 s10, 0
s_mov_b32 s15, 0
s_branch .LBB0_50
.LBB0_49: ; in Loop: Header=BB0_29 Depth=1
s_mov_b32 s10, -1
; implicit-def: $sgpr15
.LBB0_50: ; %Flow218
; in Loop: Header=BB0_29 Depth=1
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 vcc_lo, exec_lo, s10
s_cbranch_vccnz .LBB0_52
; %bb.51: ; in Loop: Header=BB0_29 Depth=1
global_load_b64 v[13:14], v28, s[0:1]
s_add_i32 s15, s14, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_52: ; %.loopexit28.i
; in Loop: Header=BB0_29 Depth=1
s_cmp_gt_u32 s15, 7
s_cbranch_scc1 .LBB0_57
; %bb.53: ; in Loop: Header=BB0_29 Depth=1
v_mov_b32_e32 v15, 0
v_mov_b32_e32 v16, 0
s_cmp_eq_u32 s15, 0
s_cbranch_scc1 .LBB0_56
; %bb.54: ; %.preheader25.i.preheader
; in Loop: Header=BB0_29 Depth=1
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_55: ; %.preheader25.i
; Parent Loop BB0_29 Depth=1
; => This Inner Loop Header: Depth=2
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v3, v28, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v27, 0xffff, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], s10, v[27:28]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s15, s12
v_or_b32_e32 v15, v3, v15
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v16, v4, v16
s_cbranch_scc1 .LBB0_55
.LBB0_56: ; %Flow211
; in Loop: Header=BB0_29 Depth=1
s_mov_b32 s10, 0
s_mov_b32 s14, 0
s_branch .LBB0_58
.LBB0_57: ; in Loop: Header=BB0_29 Depth=1
s_mov_b32 s10, -1
; implicit-def: $vgpr15_vgpr16
; implicit-def: $sgpr14
.LBB0_58: ; %Flow213
; in Loop: Header=BB0_29 Depth=1
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 vcc_lo, exec_lo, s10
s_cbranch_vccnz .LBB0_60
; %bb.59: ; in Loop: Header=BB0_29 Depth=1
global_load_b64 v[15:16], v28, s[0:1]
s_add_i32 s14, s15, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_60: ; %.loopexit26.i
; in Loop: Header=BB0_29 Depth=1
s_cmp_gt_u32 s14, 7
s_cbranch_scc1 .LBB0_65
; %bb.61: ; in Loop: Header=BB0_29 Depth=1
v_mov_b32_e32 v17, 0
v_mov_b32_e32 v18, 0
s_cmp_eq_u32 s14, 0
s_cbranch_scc1 .LBB0_64
; %bb.62: ; %.preheader23.i.preheader
; in Loop: Header=BB0_29 Depth=1
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_63: ; %.preheader23.i
; Parent Loop BB0_29 Depth=1
; => This Inner Loop Header: Depth=2
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v3, v28, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v27, 0xffff, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], s10, v[27:28]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s14, s12
v_or_b32_e32 v17, v3, v17
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v18, v4, v18
s_cbranch_scc1 .LBB0_63
.LBB0_64: ; %Flow206
; in Loop: Header=BB0_29 Depth=1
s_mov_b32 s10, 0
s_mov_b32 s15, 0
s_branch .LBB0_66
.LBB0_65: ; in Loop: Header=BB0_29 Depth=1
s_mov_b32 s10, -1
; implicit-def: $sgpr15
.LBB0_66: ; %Flow208
; in Loop: Header=BB0_29 Depth=1
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 vcc_lo, exec_lo, s10
s_cbranch_vccnz .LBB0_68
; %bb.67: ; in Loop: Header=BB0_29 Depth=1
global_load_b64 v[17:18], v28, s[0:1]
s_add_i32 s15, s14, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_68: ; %.loopexit24.i
; in Loop: Header=BB0_29 Depth=1
s_cmp_gt_u32 s15, 7
s_cbranch_scc1 .LBB0_73
; %bb.69: ; in Loop: Header=BB0_29 Depth=1
v_mov_b32_e32 v19, 0
v_mov_b32_e32 v20, 0
s_cmp_eq_u32 s15, 0
s_cbranch_scc1 .LBB0_72
; %bb.70: ; %.preheader21.i.preheader
; in Loop: Header=BB0_29 Depth=1
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_71: ; %.preheader21.i
; Parent Loop BB0_29 Depth=1
; => This Inner Loop Header: Depth=2
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v3, v28, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v27, 0xffff, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], s10, v[27:28]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s15, s12
v_or_b32_e32 v19, v3, v19
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v20, v4, v20
s_cbranch_scc1 .LBB0_71
.LBB0_72: ; %Flow201
; in Loop: Header=BB0_29 Depth=1
s_mov_b32 s10, 0
s_mov_b32 s14, 0
s_branch .LBB0_74
.LBB0_73: ; in Loop: Header=BB0_29 Depth=1
s_mov_b32 s10, -1
; implicit-def: $vgpr19_vgpr20
; implicit-def: $sgpr14
.LBB0_74: ; %Flow203
; in Loop: Header=BB0_29 Depth=1
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 vcc_lo, exec_lo, s10
s_cbranch_vccnz .LBB0_76
; %bb.75: ; in Loop: Header=BB0_29 Depth=1
global_load_b64 v[19:20], v28, s[0:1]
s_add_i32 s14, s15, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_76: ; %.loopexit22.i
; in Loop: Header=BB0_29 Depth=1
s_cmp_gt_u32 s14, 7
s_cbranch_scc1 .LBB0_81
; %bb.77: ; in Loop: Header=BB0_29 Depth=1
v_mov_b32_e32 v21, 0
v_mov_b32_e32 v22, 0
s_cmp_eq_u32 s14, 0
s_cbranch_scc1 .LBB0_80
; %bb.78: ; %.preheader.i.preheader
; in Loop: Header=BB0_29 Depth=1
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], s[0:1]
.LBB0_79: ; %.preheader.i
; Parent Loop BB0_29 Depth=1
; => This Inner Loop Header: Depth=2
global_load_u8 v3, v28, s[12:13]
s_add_i32 s14, s14, -1
s_waitcnt vmcnt(0)
v_and_b32_e32 v27, 0xffff, v3
s_delay_alu instid0(VALU_DEP_1)
v_lshlrev_b64 v[3:4], s10, v[27:28]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_add_u32 s12, s12, 1
s_addc_u32 s13, s13, 0
s_cmp_lg_u32 s14, 0
v_or_b32_e32 v21, v3, v21
v_or_b32_e32 v22, v4, v22
s_cbranch_scc1 .LBB0_79
.LBB0_80: ; %Flow196
; in Loop: Header=BB0_29 Depth=1
s_mov_b32 s10, 0
s_branch .LBB0_82
.LBB0_81: ; in Loop: Header=BB0_29 Depth=1
s_mov_b32 s10, -1
.LBB0_82: ; %Flow198
; in Loop: Header=BB0_29 Depth=1
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 vcc_lo, exec_lo, s10
s_cbranch_vccnz .LBB0_84
; %bb.83: ; in Loop: Header=BB0_29 Depth=1
global_load_b64 v[21:22], v28, s[0:1]
.LBB0_84: ; %.loopexit.i
; in Loop: Header=BB0_29 Depth=1
v_mov_b32_e32 v27, v2
v_mov_b32_e32 v3, 0
v_mov_b32_e32 v4, 0
;;#ASMSTART
;;#ASMEND
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s0, v27
v_cmp_eq_u32_e64 s0, s0, v27
s_delay_alu instid0(VALU_DEP_1)
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_90
; %bb.85: ; in Loop: Header=BB0_29 Depth=1
global_load_b64 v[25:26], v28, s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
s_clause 0x1
global_load_b64 v[3:4], v28, s[2:3] offset:40
global_load_b64 v[23:24], v28, s[2:3]
s_mov_b32 s10, exec_lo
s_waitcnt vmcnt(1)
v_and_b32_e32 v4, v4, v26
v_and_b32_e32 v3, v3, v25
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_lo_u32 v4, v4, 24
v_mul_hi_u32 v29, v3, 24
v_mul_lo_u32 v3, v3, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v4, v29, v4
s_waitcnt vmcnt(0)
v_add_co_u32 v3, vcc_lo, v23, v3
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v4, vcc_lo, v24, v4, vcc_lo
global_load_b64 v[23:24], v[3:4], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[3:4], v28, v[23:26], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmpx_ne_u64_e64 v[3:4], v[25:26]
s_cbranch_execz .LBB0_89
; %bb.86: ; %.preheader3.i.i19.i.preheader
; in Loop: Header=BB0_29 Depth=1
s_mov_b32 s11, 0
.LBB0_87: ; %.preheader3.i.i19.i
; Parent Loop BB0_29 Depth=1
; => This Inner Loop Header: Depth=2
s_sleep 1
s_clause 0x1
global_load_b64 v[23:24], v28, s[2:3] offset:40
global_load_b64 v[29:30], v28, s[2:3]
v_dual_mov_b32 v26, v4 :: v_dual_mov_b32 v25, v3
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_and_b32_e32 v23, v23, v25
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[3:4], null, v23, 24, v[29:30]
v_and_b32_e32 v29, v24, v26
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[23:24], null, v29, 24, v[4:5]
v_mov_b32_e32 v4, v23
global_load_b64 v[23:24], v[3:4], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[3:4], v28, v[23:26], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmp_eq_u64_e32 vcc_lo, v[3:4], v[25:26]
s_or_b32 s11, vcc_lo, s11
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s11
s_cbranch_execnz .LBB0_87
; %bb.88: ; %Flow191
; in Loop: Header=BB0_29 Depth=1
s_or_b32 exec_lo, exec_lo, s11
.LBB0_89: ; %Flow193
; in Loop: Header=BB0_29 Depth=1
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s10
.LBB0_90: ; %.loopexit4.i.i14.i
; in Loop: Header=BB0_29 Depth=1
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s1
s_clause 0x1
global_load_b64 v[29:30], v28, s[2:3] offset:40
global_load_b128 v[23:26], v28, s[2:3]
v_readfirstlane_b32 s10, v3
v_readfirstlane_b32 s11, v4
s_mov_b32 s16, exec_lo
s_waitcnt vmcnt(1)
v_readfirstlane_b32 s12, v29
v_readfirstlane_b32 s13, v30
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b64 s[12:13], s[10:11], s[12:13]
s_mul_i32 s1, s13, 24
s_mul_hi_u32 s14, s12, 24
s_mul_i32 s15, s12, 24
s_and_saveexec_b32 s17, s0
s_cbranch_execz .LBB0_92
; %bb.91: ; in Loop: Header=BB0_29 Depth=1
v_dual_mov_b32 v3, s16 :: v_dual_mov_b32 v4, v28
s_add_i32 s16, s14, s1
s_waitcnt vmcnt(0)
v_add_co_u32 v29, vcc_lo, v23, s15
v_add_co_ci_u32_e32 v30, vcc_lo, s16, v24, vcc_lo
global_store_b128 v[29:30], v[3:6], off offset:8
.LBB0_92: ; in Loop: Header=BB0_29 Depth=1
s_or_b32 exec_lo, exec_lo, s17
v_cmp_gt_u64_e64 vcc_lo, s[6:7], 56
v_or_b32_e32 v3, 2, v7
s_lshl_b64 s[12:13], s[12:13], 12
s_lshl_b32 s16, s8, 2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_add_i32 s16, s16, 28
v_cndmask_b32_e32 v7, v3, v7, vcc_lo
v_lshlrev_b64 v[3:4], 6, v[27:28]
s_waitcnt vmcnt(0)
v_add_co_u32 v25, vcc_lo, v25, s12
v_add_co_ci_u32_e32 v26, vcc_lo, s13, v26, vcc_lo
s_and_b32 s16, s16, 0x1e0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_co_u32 v3, vcc_lo, v25, v3
v_and_or_b32 v7, 0xffffff1f, v7, s16
v_add_co_ci_u32_e32 v4, vcc_lo, v26, v4, vcc_lo
s_clause 0x3
global_store_b128 v[3:4], v[7:10], off
global_store_b128 v[3:4], v[11:14], off offset:16
global_store_b128 v[3:4], v[15:18], off offset:32
global_store_b128 v[3:4], v[19:22], off offset:48
s_and_saveexec_b32 s12, s0
s_cbranch_execz .LBB0_100
; %bb.93: ; in Loop: Header=BB0_29 Depth=1
s_clause 0x1
global_load_b64 v[15:16], v28, s[2:3] offset:32 glc
global_load_b64 v[7:8], v28, s[2:3] offset:40
v_dual_mov_b32 v13, s10 :: v_dual_mov_b32 v14, s11
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s16, v7
v_readfirstlane_b32 s17, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b64 s[16:17], s[16:17], s[10:11]
s_mul_i32 s13, s17, 24
s_mul_hi_u32 s17, s16, 24
s_mul_i32 s16, s16, 24
s_add_i32 s17, s17, s13
v_add_co_u32 v11, vcc_lo, v23, s16
v_add_co_ci_u32_e32 v12, vcc_lo, s17, v24, vcc_lo
s_mov_b32 s13, exec_lo
global_store_b64 v[11:12], v[15:16], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[9:10], v28, v[13:16], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmpx_ne_u64_e64 v[9:10], v[15:16]
s_cbranch_execz .LBB0_96
; %bb.94: ; %.preheader1.i.i17.i.preheader
; in Loop: Header=BB0_29 Depth=1
s_mov_b32 s16, 0
.LBB0_95: ; %.preheader1.i.i17.i
; Parent Loop BB0_29 Depth=1
; => This Inner Loop Header: Depth=2
v_dual_mov_b32 v7, s10 :: v_dual_mov_b32 v8, s11
s_sleep 1
global_store_b64 v[11:12], v[9:10], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[7:8], v28, v[7:10], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[7:8], v[9:10]
v_dual_mov_b32 v10, v8 :: v_dual_mov_b32 v9, v7
s_or_b32 s16, vcc_lo, s16
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s16
s_cbranch_execnz .LBB0_95
.LBB0_96: ; %Flow189
; in Loop: Header=BB0_29 Depth=1
s_or_b32 exec_lo, exec_lo, s13
global_load_b64 v[7:8], v28, s[2:3] offset:16
s_mov_b32 s16, exec_lo
s_mov_b32 s13, exec_lo
v_mbcnt_lo_u32_b32 v9, s16, 0
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_eq_u32_e32 0, v9
s_cbranch_execz .LBB0_98
; %bb.97: ; in Loop: Header=BB0_29 Depth=1
s_bcnt1_i32_b32 s16, s16
s_delay_alu instid0(SALU_CYCLE_1)
v_mov_b32_e32 v27, s16
s_waitcnt vmcnt(0)
global_atomic_add_u64 v[7:8], v[27:28], off offset:8
.LBB0_98: ; in Loop: Header=BB0_29 Depth=1
s_or_b32 exec_lo, exec_lo, s13
s_waitcnt vmcnt(0)
global_load_b64 v[9:10], v[7:8], off offset:16
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, 0, v[9:10]
s_cbranch_vccnz .LBB0_100
; %bb.99: ; in Loop: Header=BB0_29 Depth=1
global_load_b32 v27, v[7:8], off offset:24
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s13, v27
s_waitcnt_vscnt null, 0x0
global_store_b64 v[9:10], v[27:28], off
s_and_b32 m0, s13, 0xff
s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_100: ; %Flow190
; in Loop: Header=BB0_29 Depth=1
s_or_b32 exec_lo, exec_lo, s12
s_add_i32 s14, s14, s1
v_add_co_u32 v7, vcc_lo, v23, s15
v_add_co_ci_u32_e32 v8, vcc_lo, s14, v24, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v7, vcc_lo, v7, 20
v_add_co_ci_u32_e32 v8, vcc_lo, 0, v8, vcc_lo
.LBB0_101: ; Parent Loop BB0_29 Depth=1
; => This Inner Loop Header: Depth=2
v_mov_b32_e32 v9, 1
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_103
; %bb.102: ; in Loop: Header=BB0_101 Depth=2
global_load_b32 v9, v[7:8], off glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_and_b32_e32 v9, 1, v9
.LBB0_103: ; in Loop: Header=BB0_101 Depth=2
s_or_b32 exec_lo, exec_lo, s1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s1, v9
s_cmp_eq_u32 s1, 0
s_cbranch_scc1 .LBB0_105
; %bb.104: ; in Loop: Header=BB0_101 Depth=2
s_mov_b32 s1, 0
s_sleep 1
s_branch .LBB0_106
.LBB0_105: ; in Loop: Header=BB0_101 Depth=2
s_mov_b32 s1, -1
.LBB0_106: ; %Flow184
; in Loop: Header=BB0_101 Depth=2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 vcc_lo, exec_lo, s1
s_cbranch_vccnz .LBB0_101
; %bb.107: ; in Loop: Header=BB0_29 Depth=1
global_load_b128 v[7:10], v[3:4], off
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_111
; %bb.108: ; in Loop: Header=BB0_29 Depth=1
s_clause 0x2
global_load_b64 v[3:4], v28, s[2:3] offset:40
global_load_b64 v[13:14], v28, s[2:3] offset:24 glc
global_load_b64 v[11:12], v28, s[2:3]
s_waitcnt vmcnt(2)
v_add_co_u32 v15, vcc_lo, v3, 1
v_add_co_ci_u32_e32 v16, vcc_lo, 0, v4, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v9, vcc_lo, v15, s10
v_add_co_ci_u32_e32 v10, vcc_lo, s11, v16, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_eq_u64_e32 vcc_lo, 0, v[9:10]
v_dual_cndmask_b32 v10, v10, v16 :: v_dual_cndmask_b32 v9, v9, v15
v_and_b32_e32 v4, v10, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_and_b32_e32 v3, v9, v3
v_mul_hi_u32 v15, v3, 24
v_mul_lo_u32 v3, v3, 24
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_add_co_u32 v3, vcc_lo, v11, v3
v_mov_b32_e32 v11, v13
v_mul_lo_u32 v4, v4, 24
v_add_nc_u32_e32 v4, v15, v4
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e32 v4, vcc_lo, v12, v4, vcc_lo
v_mov_b32_e32 v12, v14
global_store_b64 v[3:4], v[13:14], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[11:12], v28, v[9:12], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_ne_u64_e32 vcc_lo, v[11:12], v[13:14]
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_111
; %bb.109: ; %.preheader.i.i16.i.preheader
; in Loop: Header=BB0_29 Depth=1
s_mov_b32 s0, 0
.LBB0_110: ; %.preheader.i.i16.i
; Parent Loop BB0_29 Depth=1
; => This Inner Loop Header: Depth=2
s_sleep 1
global_store_b64 v[3:4], v[11:12], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[13:14], v28, v[9:12], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[13:14], v[11:12]
v_dual_mov_b32 v11, v13 :: v_dual_mov_b32 v12, v14
s_or_b32 s0, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s0
s_cbranch_execnz .LBB0_110
.LBB0_111: ; %__ockl_hostcall_preview.exit20.i
; in Loop: Header=BB0_29 Depth=1
s_or_b32 exec_lo, exec_lo, s1
s_sub_u32 s6, s6, s8
s_subb_u32 s7, s7, s9
s_add_u32 s4, s4, s8
s_addc_u32 s5, s5, s9
s_cmp_lg_u64 s[6:7], 0
s_cbranch_scc1 .LBB0_29
; %bb.112: ; %Flow229
s_mov_b32 s0, 0
.LBB0_113: ; %Flow245
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 vcc_lo, exec_lo, s0
s_cbranch_vccz .LBB0_141
; %bb.114:
;;#ASMSTART
;;#ASMEND
v_readfirstlane_b32 s0, v2
s_waitcnt vmcnt(0)
v_mov_b32_e32 v8, 0
v_mov_b32_e32 v9, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_eq_u32_e64 s0, s0, v2
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_120
; %bb.115:
v_mov_b32_e32 v3, 0
s_mov_b32 s4, exec_lo
global_load_b64 v[6:7], v3, s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
s_clause 0x1
global_load_b64 v[4:5], v3, s[2:3] offset:40
global_load_b64 v[8:9], v3, s[2:3]
s_waitcnt vmcnt(1)
v_and_b32_e32 v4, v4, v6
v_and_b32_e32 v5, v5, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_hi_u32 v10, v4, 24
v_mul_lo_u32 v5, v5, 24
v_mul_lo_u32 v4, v4, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v5, v10, v5
s_waitcnt vmcnt(0)
v_add_co_u32 v4, vcc_lo, v8, v4
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v5, vcc_lo, v9, v5, vcc_lo
global_load_b64 v[4:5], v[4:5], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[8:9], v3, v[4:7], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmpx_ne_u64_e64 v[8:9], v[6:7]
s_cbranch_execz .LBB0_119
; %bb.116: ; %.preheader3.i.i.i6.preheader
s_mov_b32 s5, 0
.LBB0_117: ; %.preheader3.i.i.i6
; =>This Inner Loop Header: Depth=1
s_sleep 1
s_clause 0x1
global_load_b64 v[4:5], v3, s[2:3] offset:40
global_load_b64 v[10:11], v3, s[2:3]
v_dual_mov_b32 v6, v8 :: v_dual_mov_b32 v7, v9
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_and_b32_e32 v4, v4, v6
v_and_b32_e32 v5, v5, v7
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[8:9], null, v4, 24, v[10:11]
v_mov_b32_e32 v4, v9
s_delay_alu instid0(VALU_DEP_1)
v_mad_u64_u32 v[9:10], null, v5, 24, v[4:5]
global_load_b64 v[4:5], v[8:9], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[8:9], v3, v[4:7], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmp_eq_u64_e32 vcc_lo, v[8:9], v[6:7]
s_or_b32 s5, vcc_lo, s5
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s5
s_cbranch_execnz .LBB0_117
; %bb.118: ; %Flow242
s_or_b32 exec_lo, exec_lo, s5
.LBB0_119: ; %Flow244
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s4
.LBB0_120: ; %.loopexit4.i.i.i1
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s1
v_mov_b32_e32 v3, 0
v_readfirstlane_b32 s4, v8
v_readfirstlane_b32 s5, v9
s_mov_b32 s10, exec_lo
s_clause 0x1
global_load_b64 v[10:11], v3, s[2:3] offset:40
global_load_b128 v[4:7], v3, s[2:3]
s_waitcnt vmcnt(1)
v_readfirstlane_b32 s6, v10
v_readfirstlane_b32 s7, v11
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b64 s[6:7], s[4:5], s[6:7]
s_mul_i32 s1, s7, 24
s_mul_hi_u32 s8, s6, 24
s_mul_i32 s9, s6, 24
s_and_saveexec_b32 s11, s0
s_cbranch_execz .LBB0_122
; %bb.121:
v_dual_mov_b32 v8, s10 :: v_dual_mov_b32 v9, v3
s_add_i32 s10, s8, s1
s_waitcnt vmcnt(0)
v_add_co_u32 v12, vcc_lo, v4, s9
v_add_co_ci_u32_e32 v13, vcc_lo, s10, v5, vcc_lo
v_dual_mov_b32 v10, 2 :: v_dual_mov_b32 v11, 1
global_store_b128 v[12:13], v[8:11], off offset:8
.LBB0_122:
s_or_b32 exec_lo, exec_lo, s11
s_lshl_b64 s[6:7], s[6:7], 12
v_lshlrev_b64 v[8:9], 6, v[2:3]
s_waitcnt vmcnt(0)
v_add_co_u32 v2, vcc_lo, v6, s6
v_add_co_ci_u32_e32 v6, vcc_lo, s7, v7, vcc_lo
s_mov_b32 s12, 0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_u32 v10, vcc_lo, v2, v8
s_mov_b32 s13, s12
s_mov_b32 s14, s12
s_mov_b32 s15, s12
v_and_or_b32 v0, 0xffffff1d, v0, 34
v_add_co_ci_u32_e32 v11, vcc_lo, v6, v9, vcc_lo
v_mov_b32_e32 v2, v3
v_dual_mov_b32 v6, s12 :: v_dual_mov_b32 v9, s15
v_dual_mov_b32 v7, s13 :: v_dual_mov_b32 v8, s14
s_clause 0x3
global_store_b128 v[10:11], v[0:3], off
global_store_b128 v[10:11], v[6:9], off offset:16
global_store_b128 v[10:11], v[6:9], off offset:32
global_store_b128 v[10:11], v[6:9], off offset:48
s_and_saveexec_b32 s6, s0
s_cbranch_execz .LBB0_130
; %bb.123:
v_dual_mov_b32 v8, 0 :: v_dual_mov_b32 v9, s4
v_mov_b32_e32 v10, s5
s_clause 0x1
global_load_b64 v[11:12], v8, s[2:3] offset:32 glc
global_load_b64 v[0:1], v8, s[2:3] offset:40
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s10, v0
v_readfirstlane_b32 s11, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b64 s[10:11], s[10:11], s[4:5]
s_mul_i32 s7, s11, 24
s_mul_hi_u32 s11, s10, 24
s_mul_i32 s10, s10, 24
s_add_i32 s11, s11, s7
v_add_co_u32 v6, vcc_lo, v4, s10
v_add_co_ci_u32_e32 v7, vcc_lo, s11, v5, vcc_lo
s_mov_b32 s7, exec_lo
global_store_b64 v[6:7], v[11:12], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v8, v[9:12], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmpx_ne_u64_e64 v[2:3], v[11:12]
s_cbranch_execz .LBB0_126
; %bb.124: ; %.preheader1.i.i.i4.preheader
s_mov_b32 s10, 0
.LBB0_125: ; %.preheader1.i.i.i4
; =>This Inner Loop Header: Depth=1
v_dual_mov_b32 v0, s4 :: v_dual_mov_b32 v1, s5
s_sleep 1
global_store_b64 v[6:7], v[2:3], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[0:1], v8, v[0:3], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[0:1], v[2:3]
v_dual_mov_b32 v3, v1 :: v_dual_mov_b32 v2, v0
s_or_b32 s10, vcc_lo, s10
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s10
s_cbranch_execnz .LBB0_125
.LBB0_126: ; %Flow240
s_or_b32 exec_lo, exec_lo, s7
v_mov_b32_e32 v3, 0
s_mov_b32 s10, exec_lo
s_mov_b32 s7, exec_lo
v_mbcnt_lo_u32_b32 v2, s10, 0
global_load_b64 v[0:1], v3, s[2:3] offset:16
v_cmpx_eq_u32_e32 0, v2
s_cbranch_execz .LBB0_128
; %bb.127:
s_bcnt1_i32_b32 s10, s10
s_delay_alu instid0(SALU_CYCLE_1)
v_mov_b32_e32 v2, s10
s_waitcnt vmcnt(0)
global_atomic_add_u64 v[0:1], v[2:3], off offset:8
.LBB0_128:
s_or_b32 exec_lo, exec_lo, s7
s_waitcnt vmcnt(0)
global_load_b64 v[2:3], v[0:1], off offset:16
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, 0, v[2:3]
s_cbranch_vccnz .LBB0_130
; %bb.129:
global_load_b32 v0, v[0:1], off offset:24
v_mov_b32_e32 v1, 0
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s7, v0
s_waitcnt_vscnt null, 0x0
global_store_b64 v[2:3], v[0:1], off
s_and_b32 m0, s7, 0xff
s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_130: ; %Flow241
s_or_b32 exec_lo, exec_lo, s6
s_add_i32 s8, s8, s1
v_add_co_u32 v0, vcc_lo, v4, s9
v_add_co_ci_u32_e32 v1, vcc_lo, s8, v5, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v0, 20
v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
.LBB0_131: ; =>This Inner Loop Header: Depth=1
v_mov_b32_e32 v2, 1
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_133
; %bb.132: ; in Loop: Header=BB0_131 Depth=1
global_load_b32 v2, v[0:1], off glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_and_b32_e32 v2, 1, v2
.LBB0_133: ; in Loop: Header=BB0_131 Depth=1
s_or_b32 exec_lo, exec_lo, s1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s1, v2
s_cmp_eq_u32 s1, 0
s_cbranch_scc1 .LBB0_135
; %bb.134: ; in Loop: Header=BB0_131 Depth=1
s_mov_b32 s1, 0
s_sleep 1
s_branch .LBB0_136
.LBB0_135: ; in Loop: Header=BB0_131 Depth=1
s_mov_b32 s1, -1
.LBB0_136: ; %Flow235
; in Loop: Header=BB0_131 Depth=1
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 vcc_lo, exec_lo, s1
s_cbranch_vccnz .LBB0_131
; %bb.137:
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_141
; %bb.138:
v_mov_b32_e32 v6, 0
s_clause 0x2
global_load_b64 v[2:3], v6, s[2:3] offset:40
global_load_b64 v[7:8], v6, s[2:3] offset:24 glc
global_load_b64 v[4:5], v6, s[2:3]
s_waitcnt vmcnt(2)
v_add_co_u32 v9, vcc_lo, v2, 1
v_add_co_ci_u32_e32 v10, vcc_lo, 0, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v9, s4
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v10, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_eq_u64_e32 vcc_lo, 0, v[0:1]
v_dual_cndmask_b32 v1, v1, v10 :: v_dual_cndmask_b32 v0, v0, v9
v_and_b32_e32 v3, v1, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_and_b32_e32 v2, v0, v2
v_mul_lo_u32 v3, v3, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_hi_u32 v9, v2, 24
v_mul_lo_u32 v2, v2, 24
v_add_nc_u32_e32 v3, v9, v3
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_co_u32 v4, vcc_lo, v4, v2
v_mov_b32_e32 v2, v7
v_add_co_ci_u32_e32 v5, vcc_lo, v5, v3, vcc_lo
v_mov_b32_e32 v3, v8
global_store_b64 v[4:5], v[7:8], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v6, v[0:3], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_ne_u64_e32 vcc_lo, v[2:3], v[7:8]
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_141
; %bb.139: ; %.preheader.i.i.i3.preheader
s_mov_b32 s0, 0
.LBB0_140: ; %.preheader.i.i.i3
; =>This Inner Loop Header: Depth=1
s_sleep 1
global_store_b64 v[4:5], v[2:3], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[7:8], v6, v[0:3], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[7:8], v[2:3]
v_dual_mov_b32 v2, v7 :: v_dual_mov_b32 v3, v8
s_or_b32 s0, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s0
s_cbranch_execnz .LBB0_140
.LBB0_141: ; %__ockl_printf_append_string_n.exit
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10hello_cudav
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 256
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 31
.amdhsa_next_free_sgpr 18
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10hello_cudav, .Lfunc_end0-_Z10hello_cudav
; -- End function
.section .AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 5284
; NumSgprs: 20
; NumVgprs: 31
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 3
; NumSGPRsForWavesPerEU: 20
; NumVGPRsForWavesPerEU: 31
; Occupancy: 16
; WaveLimiterHint : 1
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type .str,@object ; @.str
.section .rodata.str1.1,"aMS",@progbits,1
.str:
.asciz "Hello CUDA world!\n"
.size .str, 19
.type __hip_cuid_,@object ; @__hip_cuid_
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0 ; 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: hidden_block_count_x
- .offset: 4
.size: 4
.value_kind: hidden_block_count_y
- .offset: 8
.size: 4
.value_kind: hidden_block_count_z
- .offset: 12
.size: 2
.value_kind: hidden_group_size_x
- .offset: 14
.size: 2
.value_kind: hidden_group_size_y
- .offset: 16
.size: 2
.value_kind: hidden_group_size_z
- .offset: 18
.size: 2
.value_kind: hidden_remainder_x
- .offset: 20
.size: 2
.value_kind: hidden_remainder_y
- .offset: 22
.size: 2
.value_kind: hidden_remainder_z
- .offset: 40
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 48
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 64
.size: 2
.value_kind: hidden_grid_dims
- .offset: 80
.size: 8
.value_kind: hidden_hostcall_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 256
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10hello_cudav
.private_segment_fixed_size: 0
.sgpr_count: 20
.sgpr_spill_count: 0
.symbol: _Z10hello_cudav.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 31
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
```
| 314 | 23,849 |
311 |
Convert the following CUDA host assembly code to AMD host assembly:
```cudaasm
.file "tmpxft_00106919_00000000-6_hello_cuda.cudafe1.cpp"
.text
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z29__device_stub__Z10hello_cudavv
.type _Z29__device_stub__Z10hello_cudavv, @function
_Z29__device_stub__Z10hello_cudavv:
.LFB2082:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z10hello_cudav(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z29__device_stub__Z10hello_cudavv, .-_Z29__device_stub__Z10hello_cudavv
.globl _Z10hello_cudav
.type _Z10hello_cudav, @function
_Z10hello_cudav:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z10hello_cudavv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z10hello_cudav, .-_Z10hello_cudav
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
movl $20, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L14
.L12:
call cudaDeviceSynchronize@PLT
call cudaDeviceReset@PLT
movl $0, %eax
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
call _Z29__device_stub__Z10hello_cudavv
jmp .L12
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z10hello_cudav"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z10hello_cudav(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
```
|
```amdasm
.text
.file "hello_cuda.hip"
.globl _Z25__device_stub__hello_cudav # -- Begin function _Z25__device_stub__hello_cudav
.type _Z25__device_stub__hello_cudav,@function
_Z25__device_stub__hello_cudav: # @_Z25__device_stub__hello_cudav
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $56, %rsp
.cfi_def_cfa_offset 96
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 40(%rsp), %rbx
leaq 24(%rsp), %r14
leaq 16(%rsp), %r15
leaq 8(%rsp), %r12
movq %rbx, %rdi
movq %r14, %rsi
movq %r15, %rdx
movq %r12, %rcx
callq __hipPopCallConfiguration
movq (%rbx), %rsi
movl 8(%rbx), %edx
movq (%r14), %rcx
movl 8(%r14), %r8d
movq %rsp, %r9
movl $_Z10hello_cudav, %edi
pushq (%r12)
.cfi_adjust_cfa_offset 8
pushq (%r15)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z25__device_stub__hello_cudav, .Lfunc_end0-_Z25__device_stub__hello_cudav
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 19(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
callq _Z25__device_stub__hello_cudav
.LBB1_2:
callq hipDeviceSynchronize
callq hipDeviceReset
xorl %eax, %eax
popq %rcx
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, %rdi
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10hello_cudav, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10hello_cudav,@object # @_Z10hello_cudav
.section .rodata,"a",@progbits
.globl _Z10hello_cudav
.p2align 3, 0x0
_Z10hello_cudav:
.quad _Z25__device_stub__hello_cudav
.size _Z10hello_cudav, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z10hello_cudav"
.size .L__unnamed_1, 16
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__hello_cudav
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10hello_cudav
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
```
| 1,985 | 2,090 |
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