uid
int64 2
114k
| input
stringlengths 101
58.4k
| output
stringlengths 422
72.4k
| input_tokens
int64 24
31.2k
| output_tokens
int64 182
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|
|---|---|---|---|---|
113,648 |
Convert the following CUDA device assembly code to AMD device assembly:
```cudaasm
code for sm_80
Function : _Z21laplacianFilterKernelPKfPfii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
MOV R1, c[0x0][0x28] ;
S2R R3, SR_CTAID.Y ;
UMOV UR7, 0x1 ;
ULDC.64 UR10, c[0x0][0x170] ;
S2R R14, SR_TID.Y ;
UIADD3 UR4, -UR7, UR11, URZ ;
ULDC.64 UR8, c[0x0][0x0] ;
S2R R2, SR_CTAID.X ;
UIADD3 UR6, -UR7, UR9, URZ ;
UIADD3 UR5, -UR7, UR10, URZ ;
S2R R17, SR_TID.X ;
IMAD R3, R3, c[0x0][0x4], R14 ;
ISETP.GE.AND P0, PT, R3.reuse, 0x1, PT ;
ISETP.GE.AND P2, PT, R3.reuse, UR4, PT ;
IMAD R2, R2, c[0x0][0x0], R17 ;
ISETP.NE.OR P0, PT, R14.reuse, RZ, !P0 ;
UIADD3 UR4, -UR7, UR8, URZ ;
ISETP.NE.OR P2, PT, R14, UR6, P2 ;
IMAD R0, R3.reuse, c[0x0][0x170], R2 ;
ISETP.GE.AND P1, PT, R3, c[0x0][0x174], PT ;
HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ;
ISETP.GE.AND P3, PT, R2.reuse, 0x1, PT ;
ULDC.64 UR8, c[0x0][0x118] ;
ISETP.GE.AND P4, PT, R2, UR5, PT ;
ISETP.LT.AND P1, PT, R2, c[0x0][0x170], !P1 ;
ISETP.NE.OR P3, PT, R17.reuse, RZ, !P3 ;
ISETP.NE.OR P4, PT, R17, UR4, P4 ;
IMAD.WIDE R4, R0.reuse, R3, c[0x0][0x160] ;
@!P0 IADD3 R6, R0.reuse, -c[0x0][0x170], RZ ;
@!P2 IADD3 R8, R0, c[0x0][0x170], RZ ;
@!P0 IMAD.WIDE R6, R6, R3.reuse, c[0x0][0x160] ;
@P1 LDG.E R13, [R4.64] ;
@!P2 IMAD.WIDE R8, R8, R3, c[0x0][0x160] ;
@!P3 LDG.E R15, [R4.64+-0x4] ;
@!P4 LDG.E R12, [R4.64+0x4] ;
@!P0 LDG.E R6, [R6.64] ;
@!P2 LDG.E R8, [R8.64] ;
SHF.L.U32 R10, R14, 0x7, RZ ;
SHF.L.U32 R11, R17, 0x2, RZ ;
@!P2 MOV R16, c[0x0][0x4] ;
IADD3 R2, R10, R11.reuse, RZ ;
@!P4 IMAD R5, R3, c[0x0][0x0], R10 ;
@!P2 LEA R11, R16, R11, 0x7 ;
@!P1 STS [R2+0x84], RZ ;
ISETP.GE.U32.AND P5, PT, R17, UR4, PT ;
ISETP.EQ.OR P5, PT, R17, RZ, P5 ;
ISETP.EQ.OR P5, PT, R14, RZ, P5 ;
ISETP.GE.U32.OR P5, PT, R14, UR6, P5 ;
@P1 STS [R2+0x84], R13 ;
@!P3 STS [R10+0x80], R15 ;
@!P4 STS [R5+0x84], R12 ;
@!P0 STS [R17.X4+0x4], R6 ;
@!P2 STS [R11+0x84], R8 ;
BAR.SYNC.DEFER_BLOCKING 0x0 ;
@P5 EXIT ;
LDS R5, [R2+-0x84] ;
LDS R7, [R2+-0x80] ;
LDS R8, [R2+-0x7c] ;
LDS R9, [R2+-0x78] ;
LDS R10, [R2+-0x74] ;
LDS R11, [R2+-0x4] ;
LDS R12, [R2] ;
LDS R13, [R2+0x4] ;
LDS R14, [R2+0x8] ;
LDS R4, [R2+0xc] ;
FFMA R6, R5, c[0x3][0x0], RZ ;
LDS R16, [R2+0x10c] ;
FFMA R7, R7, c[0x3][0x4], R6 ;
LDS R5, [R2+0x7c] ;
FFMA R8, R8, c[0x3][0x8], R7 ;
LDS R6, [R2+0x80] ;
FFMA R9, R9, c[0x3][0xc], R8 ;
LDS R7, [R2+0x84] ;
FFMA R10, R10, c[0x3][0x10], R9 ;
LDS R8, [R2+0x88] ;
FFMA R11, R11, c[0x3][0x14], R10 ;
LDS R9, [R2+0x8c] ;
FFMA R12, R12, c[0x3][0x18], R11 ;
LDS R10, [R2+0xfc] ;
FFMA R13, R13, c[0x3][0x1c], R12 ;
LDS R11, [R2+0x100] ;
FFMA R13, R14, c[0x3][0x20], R13 ;
LDS R12, [R2+0x104] ;
FFMA R4, R4, c[0x3][0x24], R13 ;
LDS R14, [R2+0x108] ;
LDS R13, [R2+0x184] ;
FFMA R5, R5, c[0x3][0x28], R4 ;
LDS R4, [R2+0x17c] ;
FFMA R6, R6, c[0x3][0x2c], R5 ;
LDS R5, [R2+0x180] ;
FFMA R7, R7, c[0x3][0x30], R6 ;
LDS R6, [R2+0x18c] ;
FFMA R8, R8, c[0x3][0x34], R7 ;
LDS R7, [R2+0x188] ;
FFMA R9, R9, c[0x3][0x38], R8 ;
FFMA R10, R10, c[0x3][0x3c], R9 ;
FFMA R11, R11, c[0x3][0x40], R10 ;
FFMA R11, R12, c[0x3][0x44], R11 ;
FFMA R11, R14, c[0x3][0x48], R11 ;
FFMA R11, R16, c[0x3][0x4c], R11 ;
FFMA R4, R4, c[0x3][0x50], R11 ;
FFMA R4, R5, c[0x3][0x54], R4 ;
FFMA R4, R13, c[0x3][0x58], R4 ;
FFMA R7, R7, c[0x3][0x5c], R4 ;
IMAD.WIDE R4, R0, R3, c[0x0][0x168] ;
FFMA R7, R6, c[0x3][0x60], R7 ;
STG.E [R4.64], R7 ;
EXIT ;
BRA 0x6c0;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
```
|
```amdasm
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z21laplacianFilterKernelPKfPfii ; -- Begin function _Z21laplacianFilterKernelPKfPfii
.globl _Z21laplacianFilterKernelPKfPfii
.p2align 8
.type _Z21laplacianFilterKernelPKfPfii,@function
_Z21laplacianFilterKernelPKfPfii: ; @_Z21laplacianFilterKernelPKfPfii
; %bb.0:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b64 s[8:9], s[0:1], 0x10
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_load_b128 s[4:7], s[0:1], 0x0
v_mov_b32_e32 v8, 0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s3, s2, 16
s_and_b32 s2, s2, 0xffff
v_mad_u64_u32 v[4:5], null, s15, s3, v[3:4]
v_mad_u64_u32 v[6:7], null, s14, s2, v[2:3]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_gt_i32_e64 s0, s9, v4
v_mad_u64_u32 v[0:1], null, v4, s8, v[6:7]
v_cmp_gt_i32_e32 vcc_lo, s8, v6
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
s_and_b32 s1, vcc_lo, s0
v_ashrrev_i32_e32 v1, 31, v0
s_and_saveexec_b32 s0, s1
s_cbranch_execz .LBB0_2
; %bb.1:
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[7:8], 2, v[0:1]
v_add_co_u32 v7, vcc_lo, s4, v7
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v8, vcc_lo, s5, v8, vcc_lo
global_load_b32 v8, v[7:8], off
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s0
v_lshlrev_b32_e32 v5, 2, v2
v_cmp_eq_u32_e32 vcc_lo, 0, v2
v_cmp_lt_i32_e64 s0, 0, v6
v_lshlrev_b32_e32 v7, 7, v3
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_lshl_add_u32 v9, v3, 7, v5
s_and_b32 s0, vcc_lo, s0
s_waitcnt vmcnt(0)
ds_store_b32 v9, v8 offset:132
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_4
; %bb.3:
v_lshlrev_b64 v[8:9], 2, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v8, s0, s4, v8
v_add_co_ci_u32_e64 v9, s0, s5, v9, s0
global_load_b32 v8, v[8:9], off offset:-4
s_waitcnt vmcnt(0)
ds_store_b32 v7, v8 offset:128
.LBB0_4:
s_or_b32 exec_lo, exec_lo, s1
s_add_i32 s10, s2, -1
s_add_i32 s1, s8, -1
v_cmp_eq_u32_e64 s0, s10, v2
v_cmp_gt_i32_e64 s1, s1, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s0, s0, s1
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_6
; %bb.5:
v_lshlrev_b64 v[8:9], 2, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v8, s0, s4, v8
v_add_co_ci_u32_e64 v9, s0, s5, v9, s0
global_load_b32 v6, v[8:9], off offset:4
v_lshl_add_u32 v8, s2, 2, v7
s_waitcnt vmcnt(0)
ds_store_b32 v8, v6 offset:132
.LBB0_6:
s_or_b32 exec_lo, exec_lo, s1
v_cmp_eq_u32_e64 s0, 0, v3
v_cmp_lt_i32_e64 s1, 0, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s1, s0, s1
s_and_saveexec_b32 s2, s1
s_cbranch_execz .LBB0_8
; %bb.7:
v_subrev_nc_u32_e32 v8, s8, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v9, 31, v8
v_lshlrev_b64 v[8:9], 2, v[8:9]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v8, s1, s4, v8
v_add_co_ci_u32_e64 v9, s1, s5, v9, s1
global_load_b32 v6, v[8:9], off
s_waitcnt vmcnt(0)
ds_store_b32 v5, v6 offset:4
.LBB0_8:
s_or_b32 exec_lo, exec_lo, s2
s_add_i32 s11, s3, -1
s_add_i32 s2, s9, -1
v_cmp_eq_u32_e64 s1, s11, v3
v_cmp_gt_i32_e64 s2, s2, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s1, s1, s2
s_and_saveexec_b32 s2, s1
s_cbranch_execz .LBB0_10
; %bb.9:
v_add_nc_u32_e32 v8, s8, v0
v_lshl_add_u32 v6, s3, 7, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v9, 31, v8
v_lshlrev_b64 v[8:9], 2, v[8:9]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v8, s1, s4, v8
v_add_co_ci_u32_e64 v9, s1, s5, v9, s1
global_load_b32 v4, v[8:9], off
s_waitcnt vmcnt(0)
ds_store_b32 v6, v4 offset:132
.LBB0_10:
s_or_b32 exec_lo, exec_lo, s2
v_cmp_le_u32_e64 s1, s10, v2
v_cmp_le_u32_e64 s2, s11, v3
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_or_b32 s1, s1, s2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_or_b32 s1, vcc_lo, s1
s_or_b32 s0, s0, s1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_xor_b32 s0, s0, -1
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_16
; %bb.11: ; %.preheader.preheader
v_add3_u32 v3, v7, v5, 0xffffff7c
v_mov_b32_e32 v2, 0
s_mov_b32 s4, -2
s_getpc_b64 s[0:1]
s_add_u32 s0, s0, laplacianFilter@rel32@lo+4
s_addc_u32 s1, s1, laplacianFilter@rel32@hi+12
.LBB0_12: ; %.preheader
; =>This Loop Header: Depth=1
; Child Loop BB0_13 Depth 2
s_movk_i32 s5, 0xffec
s_mov_b64 s[2:3], s[0:1]
.LBB0_13: ; Parent Loop BB0_12 Depth=1
; => This Inner Loop Header: Depth=2
v_add_nc_u32_e32 v4, s5, v3
s_load_b32 s8, s[2:3], 0x0
s_add_u32 s2, s2, 4
s_addc_u32 s3, s3, 0
s_add_i32 s5, s5, 4
ds_load_b32 v4, v4 offset:20
s_cmp_eq_u32 s5, 0
s_waitcnt lgkmcnt(0)
v_fmac_f32_e32 v2, s8, v4
s_cbranch_scc0 .LBB0_13
; %bb.14: ; in Loop: Header=BB0_12 Depth=1
s_add_i32 s4, s4, 1
v_add_nc_u32_e32 v3, 0x80, v3
s_add_u32 s0, s0, 20
s_addc_u32 s1, s1, 0
s_cmp_eq_u32 s4, 3
s_cbranch_scc0 .LBB0_12
; %bb.15:
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
global_store_b32 v[0:1], v2, off
.LBB0_16:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z21laplacianFilterKernelPKfPfii
.amdhsa_group_segment_fixed_size 4096
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 10
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z21laplacianFilterKernelPKfPfii, .Lfunc_end0-_Z21laplacianFilterKernelPKfPfii
; -- End function
.section .AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 812
; NumSgprs: 18
; NumVgprs: 10
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 4096 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 10
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.protected laplacianFilter ; @laplacianFilter
.type laplacianFilter,@object
.data
.globl laplacianFilter
.p2align 4, 0x0
laplacianFilter:
.long 0xbf800000 ; float -1
.long 0xbf800000 ; float -1
.long 0xbf800000 ; float -1
.long 0xbf800000 ; float -1
.long 0xbf800000 ; float -1
.long 0xbf800000 ; float -1
.long 0xbf800000 ; float -1
.long 0xbf800000 ; float -1
.long 0xbf800000 ; float -1
.long 0xbf800000 ; float -1
.long 0xbf800000 ; float -1
.long 0xbf800000 ; float -1
.long 0x41c00000 ; float 24
.long 0xbf800000 ; float -1
.long 0xbf800000 ; float -1
.long 0xbf800000 ; float -1
.long 0xbf800000 ; float -1
.long 0xbf800000 ; float -1
.long 0xbf800000 ; float -1
.long 0xbf800000 ; float -1
.long 0xbf800000 ; float -1
.long 0xbf800000 ; float -1
.long 0xbf800000 ; float -1
.long 0xbf800000 ; float -1
.long 0xbf800000 ; float -1
.size laplacianFilter, 100
.type __hip_cuid_,@object ; @__hip_cuid_
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0 ; 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym laplacianFilter
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 4096
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z21laplacianFilterKernelPKfPfii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z21laplacianFilterKernelPKfPfii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 10
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
```
| 2,246 | 5,415 |
113,649 |
Convert the following CUDA host assembly code to AMD host assembly:
```cudaasm
.file "tmpxft_00038e35_00000000-6_cuda_code_064619.cudafe1.cpp"
.text
.globl _ZSt21ios_base_library_initv
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3638:
.cfi_startproc
endbr64
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
jmp __cudaUnregisterFatBinary@PLT
.cfi_endproc
.LFE3638:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.align 2
.type _ZNSolsEPFRSoS_E.isra.0, @function
_ZNSolsEPFRSoS_E.isra.0:
.LFB4292:
.cfi_startproc
jmp *%rsi
.cfi_endproc
.LFE4292:
.size _ZNSolsEPFRSoS_E.isra.0, .-_ZNSolsEPFRSoS_E.isra.0
.globl _Z46__device_stub__Z21laplacianFilterKernelPKfPfiiPKfPfii
.type _Z46__device_stub__Z21laplacianFilterKernelPKfPfiiPKfPfii, @function
_Z46__device_stub__Z21laplacianFilterKernelPKfPfiiPKfPfii:
.LFB3660:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
leaq 56(%rsp), %rdi
movq %rsi, 16(%rsp)
leaq 68(%rsp), %rsi
movl %edx, 12(%rsp)
leaq 40(%rsp), %rdx
movl %ecx, 8(%rsp)
leaq 48(%rsp), %rcx
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movl $1, 64(%rsp)
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 12(%rsp), %rax
movq %rax, 120(%rsp)
leaq 8(%rsp), %rax
movq %rax, 128(%rsp)
movabsq $4294967297, %rax
movq %rax, 56(%rsp)
movq %rax, 68(%rsp)
movl $1, 76(%rsp)
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
jne .L3
pushq 48(%rsp)
.cfi_def_cfa_offset 168
leaq _Z21laplacianFilterKernelPKfPfii(%rip), %rdi
pushq 48(%rsp)
.cfi_def_cfa_offset 176
movq 84(%rsp), %rcx
movl 92(%rsp), %r8d
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
leaq 120(%rsp), %r9
call cudaLaunchKernel@PLT
popq %rax
.cfi_def_cfa_offset 168
popq %rdx
.cfi_def_cfa_offset 160
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
je .L5
call __stack_chk_fail@PLT
.L5:
addq $152, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3660:
.size _Z46__device_stub__Z21laplacianFilterKernelPKfPfiiPKfPfii, .-_Z46__device_stub__Z21laplacianFilterKernelPKfPfiiPKfPfii
.globl _Z21laplacianFilterKernelPKfPfii
.type _Z21laplacianFilterKernelPKfPfii, @function
_Z21laplacianFilterKernelPKfPfii:
.LFB3661:
.cfi_startproc
endbr64
jmp _Z46__device_stub__Z21laplacianFilterKernelPKfPfiiPKfPfii
.cfi_endproc
.LFE3661:
.size _Z21laplacianFilterKernelPKfPfii, .-_Z21laplacianFilterKernelPKfPfii
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "Error allocating d_input: "
.LC2:
.string "Error allocating d_output: "
.LC3:
.string "Error copying input data to device: "
.LC4:
.string "Error launching kernel: "
.LC5:
.string "Error copying output data to host: "
.LC6:
.string "Laplacian filter applied successfully!"
.section .text.startup,"ax",@progbits
.globl main
.type main, @function
main:
.LFB3635:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
movl $16777216, %edi
xorl %r12d, %r12d
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $48, %rsp
.cfi_def_cfa_offset 80
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
call _Znam@PLT
movl $16777216, %edi
movq %rax, %rbx
call _Znam@PLT
movq %rax, %rbp
.L10:
call rand@PLT
cvtsi2ssl %eax, %xmm0
mulss .LC0(%rip), %xmm0
movss %xmm0, (%rbx,%r12,4)
incq %r12
cmpq $1048576, %r12
jne .L10
movq %rsp, %rdi
movl $4194304, %esi
call cudaMalloc@PLT
movl %eax, %r12d
testl %eax, %eax
je .L11
leaq .LC1(%rip), %rsi
leaq _ZSt4cerr(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movl %r12d, %edi
movq %rax, %rbx
call cudaGetErrorString@PLT
movq %rbx, %rdi
movq %rax, %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@GOTPCREL(%rip), %rsi
movq %rax, %rdi
call _ZNSolsEPFRSoS_E.isra.0
jmp .L12
.L11:
leaq 8(%rsp), %rdi
movl $4194304, %esi
call cudaMalloc@PLT
movl %eax, %r12d
testl %eax, %eax
je .L13
leaq .LC2(%rip), %rsi
leaq _ZSt4cerr(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movl %r12d, %edi
movq %rax, %rbx
call cudaGetErrorString@PLT
movq %rbx, %rdi
movq %rax, %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@GOTPCREL(%rip), %rsi
movq %rax, %rdi
call _ZNSolsEPFRSoS_E.isra.0
movq (%rsp), %rdi
.L22:
call cudaFree@PLT
.L12:
orl $-1, %eax
jmp .L9
.L13:
movq (%rsp), %rdi
movq %rbx, %rsi
movl $1, %ecx
movl $4194304, %edx
call cudaMemcpy@PLT
leaq .LC3(%rip), %rsi
movl %eax, %r12d
testl %eax, %eax
jne .L23
xorl %r9d, %r9d
xorl %r8d, %r8d
movl $1, %ecx
movl $1, %esi
movabsq $128849018910, %rdx
movabsq $150323855395, %rdi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L16
movq 8(%rsp), %rsi
movq (%rsp), %rdi
movl $1024, %ecx
movl $1024, %edx
call _Z46__device_stub__Z21laplacianFilterKernelPKfPfiiPKfPfii
.L16:
call cudaGetLastError@PLT
leaq .LC4(%rip), %rsi
movl %eax, %r12d
testl %eax, %eax
jne .L23
movq 8(%rsp), %rsi
movl $2, %ecx
movl $4194304, %edx
movq %rbp, %rdi
call cudaMemcpy@PLT
movl %eax, %r12d
testl %eax, %eax
je .L18
leaq .LC5(%rip), %rsi
.L23:
leaq _ZSt4cerr(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movl %r12d, %edi
movq %rax, %rbx
call cudaGetErrorString@PLT
movq %rbx, %rdi
movq %rax, %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@GOTPCREL(%rip), %rsi
movq %rax, %rdi
call _ZNSolsEPFRSoS_E.isra.0
movq (%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
jmp .L22
.L18:
movq (%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq %rbx, %rdi
call _ZdaPv@PLT
movq %rbp, %rdi
call _ZdaPv@PLT
leaq .LC6(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@GOTPCREL(%rip), %rsi
movq %rax, %rdi
call _ZNSolsEPFRSoS_E.isra.0
xorl %eax, %eax
.L9:
movq 40(%rsp), %rdx
subq %fs:40, %rdx
je .L19
call __stack_chk_fail@PLT
.L19:
addq $48, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3635:
.size main, .-main
.section .rodata.str1.1
.LC7:
.string "_Z21laplacianFilterKernelPKfPfii"
.LC8:
.string "laplacianFilter"
.section .text.startup
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3663:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
pushq $0
.cfi_def_cfa_offset 24
xorl %r9d, %r9d
orl $-1, %r8d
pushq $0
.cfi_def_cfa_offset 32
leaq .LC7(%rip), %rdx
movq %rax, %rdi
movq %rax, %rbx
pushq $0
.cfi_def_cfa_offset 40
movq %rdx, %rcx
leaq _Z21laplacianFilterKernelPKfPfii(%rip), %rsi
pushq $0
.cfi_def_cfa_offset 48
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq %rbx, %rdi
xorl %r8d, %r8d
pushq $0
.cfi_def_cfa_offset 24
leaq .LC8(%rip), %rdx
movl $100, %r9d
leaq _ZL15laplacianFilter(%rip), %rsi
pushq $1
.cfi_def_cfa_offset 32
movq %rdx, %rcx
call __cudaRegisterVar@PLT
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
popq %rax
.cfi_def_cfa_offset 24
popq %rdx
.cfi_def_cfa_offset 16
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit@PLT
.cfi_endproc
.LFE3663:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZL15laplacianFilter
.comm _ZL15laplacianFilter,100,32
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC0:
.long 805306368
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
```
|
```amdasm
.text
.file "cuda_code_064619.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z36__device_stub__laplacianFilterKernelPKfPfii # -- Begin function _Z36__device_stub__laplacianFilterKernelPKfPfii
.type _Z36__device_stub__laplacianFilterKernelPKfPfii,@function
_Z36__device_stub__laplacianFilterKernelPKfPfii: # @_Z36__device_stub__laplacianFilterKernelPKfPfii
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $112, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 40(%rsp), %rax
movq %rdi, (%rax)
leaq 32(%rsp), %rdi
movq %rsi, (%rdi)
leaq 12(%rsp), %rsi
movl %edx, (%rsi)
leaq 8(%rsp), %rdx
movl %ecx, (%rdx)
leaq 80(%rsp), %rbx
movq %rax, (%rbx)
movq %rdi, 8(%rbx)
movq %rsi, 16(%rbx)
movq %rdx, 24(%rbx)
leaq 64(%rsp), %r14
leaq 48(%rsp), %r15
leaq 24(%rsp), %r12
leaq 16(%rsp), %r13
movq %r14, %rdi
movq %r15, %rsi
movq %r12, %rdx
movq %r13, %rcx
callq __hipPopCallConfiguration
movq (%r14), %rsi
movl 8(%r14), %edx
movq (%r15), %rcx
movl 8(%r15), %r8d
movl $_Z21laplacianFilterKernelPKfPfii, %edi
movq %rbx, %r9
pushq (%r13)
.cfi_adjust_cfa_offset 8
pushq (%r12)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $128, %rsp
.cfi_adjust_cfa_offset -128
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z36__device_stub__laplacianFilterKernelPKfPfii, .Lfunc_end0-_Z36__device_stub__laplacianFilterKernelPKfPfii
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI1_0:
.long 0x30000000 # float 4.65661287E-10
.text
.globl main
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $24, %rsp
.cfi_def_cfa_offset 64
.cfi_offset %rbx, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $16777216, %edi # imm = 0x1000000
callq _Znam
movq %rax, %rbx
movl $16777216, %edi # imm = 0x1000000
callq _Znam
movq %rax, %r14
xorl %r15d, %r15d
.LBB1_1: # =>This Inner Loop Header: Depth=1
callq rand
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
mulss .LCPI1_0(%rip), %xmm0
movss %xmm0, (%rbx,%r15,4)
incq %r15
cmpq $1048576, %r15 # imm = 0x100000
jne .LBB1_1
# %bb.2:
leaq 8(%rsp), %rdi
movl $4194304, %esi # imm = 0x400000
callq hipMalloc
testl %eax, %eax
je .LBB1_5
# %bb.3:
movl %eax, %ebp
movl $_ZSt4cerr, %edi
movl $.L.str, %esi
movl $26, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl %ebp, %edi
callq hipGetErrorString
testq %rax, %rax
je .LBB1_8
# %bb.4:
movq %rax, %rbx
movq %rax, %rdi
callq strlen
movl $_ZSt4cerr, %edi
movq %rbx, %rsi
movq %rax, %rdx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
jmp .LBB1_9
.LBB1_5:
leaq 16(%rsp), %rdi
movl $4194304, %esi # imm = 0x400000
callq hipMalloc
testl %eax, %eax
je .LBB1_10
# %bb.6:
movl %eax, %ebp
movl $_ZSt4cerr, %edi
movl $.L.str.1, %esi
movl $27, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl %ebp, %edi
callq hipGetErrorString
testq %rax, %rax
je .LBB1_12
# %bb.7:
movq %rax, %rbx
movq %rax, %rdi
callq strlen
movl $_ZSt4cerr, %edi
movq %rbx, %rsi
movq %rax, %rdx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
jmp .LBB1_13
.LBB1_8:
movq _ZSt4cerr(%rip), %rax
movq -24(%rax), %rax
leaq _ZSt4cerr(%rax), %rdi
movl 32(%rdi), %esi
orl $1, %esi
callq _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate
.LBB1_9: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit
movq _ZSt4cerr(%rip), %rax
movl $_ZSt4cerr, %ecx
movq -24(%rax), %rdi
addq %rcx, %rdi
movl $10, %esi
callq _ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
movsbl %al, %esi
movl $_ZSt4cerr, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
jmp .LBB1_24
.LBB1_10:
movq 8(%rsp), %rdi
movl $4194304, %edx # imm = 0x400000
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
je .LBB1_14
# %bb.11:
movl %eax, %ebp
movl $_ZSt4cerr, %edi
movl $.L.str.2, %esi
movl $36, %edx
jmp .LBB1_18
.LBB1_12:
movq _ZSt4cerr(%rip), %rax
movq -24(%rax), %rax
leaq _ZSt4cerr(%rax), %rdi
movl 32(%rdi), %esi
orl $1, %esi
callq _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate
.LBB1_13: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit36
movq _ZSt4cerr(%rip), %rax
movl $_ZSt4cerr, %ecx
movq -24(%rax), %rdi
addq %rcx, %rdi
movl $10, %esi
callq _ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
movsbl %al, %esi
movl $_ZSt4cerr, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq 8(%rsp), %rdi
jmp .LBB1_23
.LBB1_14:
movabsq $150323855395, %rdi # imm = 0x2300000023
movabsq $128849018910, %rdx # imm = 0x1E0000001E
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_16
# %bb.15:
movq 8(%rsp), %rdi
movq 16(%rsp), %rsi
movl $1024, %edx # imm = 0x400
movl $1024, %ecx # imm = 0x400
callq _Z36__device_stub__laplacianFilterKernelPKfPfii
.LBB1_16:
callq hipGetLastError
testl %eax, %eax
je .LBB1_26
# %bb.17:
movl %eax, %ebp
movl $_ZSt4cerr, %edi
movl $.L.str.3, %esi
movl $24, %edx
.LBB1_18:
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl %ebp, %edi
callq hipGetErrorString
testq %rax, %rax
je .LBB1_20
# %bb.19:
movq %rax, %rbx
movq %rax, %rdi
callq strlen
movl $_ZSt4cerr, %edi
movq %rbx, %rsi
movq %rax, %rdx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
jmp .LBB1_21
.LBB1_20:
movq _ZSt4cerr(%rip), %rax
movq -24(%rax), %rax
leaq _ZSt4cerr(%rax), %rdi
movl 32(%rdi), %esi
orl $1, %esi
callq _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate
.LBB1_21: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit38
movq _ZSt4cerr(%rip), %rax
movl $_ZSt4cerr, %ecx
movq -24(%rax), %rdi
addq %rcx, %rdi
movl $10, %esi
callq _ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
movsbl %al, %esi
movl $_ZSt4cerr, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
.LBB1_22:
movq 8(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
.LBB1_23:
callq hipFree
.LBB1_24:
movl $-1, %eax
.LBB1_25:
addq $24, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB1_26:
.cfi_def_cfa_offset 64
movq 16(%rsp), %rsi
movl $4194304, %edx # imm = 0x400000
movq %r14, %rdi
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
je .LBB1_28
# %bb.27:
movl %eax, %ebp
movl $_ZSt4cerr, %edi
movl $.L.str.4, %esi
movl $35, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl %ebp, %edi
callq hipGetErrorString
movl $_ZSt4cerr, %edi
movq %rax, %rsi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movq %rax, %rdi
callq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_
jmp .LBB1_22
.LBB1_28:
movq 8(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq %rbx, %rdi
callq _ZdaPv
movq %r14, %rdi
callq _ZdaPv
movl $_ZSt4cout, %edi
movl $.L.str.5, %esi
movl $38, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
callq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_
xorl %eax, %eax
jmp .LBB1_25
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
movq __hip_gpubin_handle(%rip), %rbx
testq %rbx, %rbx
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, %rbx
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z21laplacianFilterKernelPKfPfii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $0, 8(%rsp)
movl $1, (%rsp)
movl $laplacianFilter, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movl $100, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
callq __hipRegisterVar
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type laplacianFilter,@object # @laplacianFilter
.local laplacianFilter
.comm laplacianFilter,100,16
.type _Z21laplacianFilterKernelPKfPfii,@object # @_Z21laplacianFilterKernelPKfPfii
.section .rodata,"a",@progbits
.globl _Z21laplacianFilterKernelPKfPfii
.p2align 3, 0x0
_Z21laplacianFilterKernelPKfPfii:
.quad _Z36__device_stub__laplacianFilterKernelPKfPfii
.size _Z21laplacianFilterKernelPKfPfii, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Error allocating d_input: "
.size .L.str, 27
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Error allocating d_output: "
.size .L.str.1, 28
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Error copying input data to device: "
.size .L.str.2, 37
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Error launching kernel: "
.size .L.str.3, 25
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Error copying output data to host: "
.size .L.str.4, 36
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "Laplacian filter applied successfully!"
.size .L.str.5, 39
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z21laplacianFilterKernelPKfPfii"
.size .L__unnamed_1, 33
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "laplacianFilter"
.size .L__unnamed_2, 16
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z36__device_stub__laplacianFilterKernelPKfPfii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym laplacianFilter
.addrsig_sym _Z21laplacianFilterKernelPKfPfii
.addrsig_sym _ZSt4cerr
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
```
| 4,347 | 6,076 |
113,650 |
Convert the following CUDA device assembly code to AMD device assembly:
```cudaasm
code for sm_80
Function : _Z21clothSimulationKernelPfS_S_ff
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
MOV R1, c[0x0][0x28] ;
S2R R9, SR_CTAID.Y ;
S2R R2, SR_TID.Y ;
S2R R0, SR_CTAID.X ;
S2R R3, SR_TID.X ;
IMAD R9, R9, c[0x0][0x4], R2 ;
ISETP.GT.AND P0, PT, R9, 0xff, PT ;
IMAD R0, R0, c[0x0][0x0], R3 ;
ISETP.GT.OR P0, PT, R0, 0xff, P0 ;
@P0 EXIT ;
HFMA2.MMA R13, -RZ, RZ, 0, 2.384185791015625e-07 ;
LEA R6, R9, R0, 0x8 ;
ULDC.64 UR4, c[0x0][0x118] ;
IMAD.WIDE R4, R6, R13, c[0x0][0x170] ;
IMAD.WIDE R2, R6, R13, c[0x0][0x168] ;
LDG.E R4, [R4.64] ;
LDG.E R7, [R2.64] ;
ISETP.NE.AND P0, PT, R0, 0xff, PT ;
FFMA R7, R4, c[0x0][0x178], R7 ;
FMUL R11, R7, c[0x0][0x17c] ;
IMAD.WIDE R6, R6, R13, c[0x0][0x160] ;
STG.E [R2.64], R11 ;
LDG.E R8, [R6.64] ;
ISETP.NE.AND P0, PT, R0, RZ, P0 ;
ISETP.NE.AND P1, PT, R9.reuse, 0xff, PT ;
ISETP.NE.AND P0, PT, R9, RZ, P0 ;
FFMA R5, R11, c[0x0][0x178], R8 ;
STG.E [R6.64], R5 ;
@P0 EXIT P1 ;
STG.E [R6.64], RZ ;
STG.E [R2.64], RZ ;
EXIT ;
BRA 0x200;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
```
|
```amdasm
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z21clothSimulationKernelPfS_S_ff ; -- Begin function _Z21clothSimulationKernelPfS_S_ff
.globl _Z21clothSimulationKernelPfS_S_ff
.p2align 8
.type _Z21clothSimulationKernelPfS_S_ff,@function
_Z21clothSimulationKernelPfS_S_ff: ; @_Z21clothSimulationKernelPfS_S_ff
; %bb.0:
s_load_b32 s2, s[0:1], 0x2c
v_and_b32_e32 v1, 0x3ff, v0
v_bfe_u32 v4, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_lshr_b32 s3, s2, 16
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, s14, s2, v[1:2]
v_mad_u64_u32 v[0:1], null, s15, s3, v[4:5]
s_mov_b32 s2, exec_lo
v_max_i32_e32 v1, v2, v0
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e32 0x100, v1
s_cbranch_execz .LBB0_3
; %bb.1:
s_load_b256 s[0:7], s[0:1], 0x0
v_lshl_add_u32 v3, v0, 8, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v4, 31, v3
v_lshlrev_b64 v[5:6], 2, v[3:4]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v3, vcc_lo, s2, v5
v_add_co_ci_u32_e32 v4, vcc_lo, s3, v6, vcc_lo
v_add_co_u32 v7, vcc_lo, s4, v5
v_add_co_ci_u32_e32 v8, vcc_lo, s5, v6, vcc_lo
v_add_co_u32 v5, vcc_lo, s0, v5
global_load_b32 v1, v[3:4], off
global_load_b32 v7, v[7:8], off
v_add_co_ci_u32_e32 v6, vcc_lo, s1, v6, vcc_lo
v_cmp_eq_u32_e32 vcc_lo, 0, v2
v_cmp_eq_u32_e64 s0, 0xff, v2
v_cmp_eq_u32_e64 s1, 0, v0
v_cmp_eq_u32_e64 s2, 0xff, v0
s_delay_alu instid0(VALU_DEP_3)
s_or_b32 s0, vcc_lo, s0
s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
s_or_b32 s0, s0, s1
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
s_or_b32 s0, s2, s0
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v1, s6, v7
s_delay_alu instid0(VALU_DEP_1)
v_mul_f32_e32 v1, s7, v1
global_store_b32 v[3:4], v1, off
global_load_b32 v7, v[5:6], off
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v7, s6, v1
global_store_b32 v[5:6], v7, off
s_and_b32 exec_lo, exec_lo, s0
s_cbranch_execz .LBB0_3
; %bb.2:
v_mov_b32_e32 v0, 0
global_store_b32 v[5:6], v0, off
global_store_b32 v[3:4], v0, off
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z21clothSimulationKernelPfS_S_ff
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z21clothSimulationKernelPfS_S_ff, .Lfunc_end0-_Z21clothSimulationKernelPfS_S_ff
; -- End function
.section .AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 324
; NumSgprs: 18
; NumVgprs: 9
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 9
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object ; @__hip_cuid_
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0 ; 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z21clothSimulationKernelPfS_S_ff
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z21clothSimulationKernelPfS_S_ff.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
```
| 676 | 3,090 |
113,651 |
Convert the following CUDA host assembly code to AMD host assembly:
```cudaasm
.file "tmpxft_00123cc8_00000000-6_cuda_code_039448.cudafe1.cpp"
.text
.globl _ZSt21ios_base_library_initv
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3638:
.cfi_startproc
endbr64
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
jmp __cudaUnregisterFatBinary@PLT
.cfi_endproc
.LFE3638:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.align 2
.type _ZNSolsEPFRSoS_E.isra.0, @function
_ZNSolsEPFRSoS_E.isra.0:
.LFB4292:
.cfi_startproc
jmp *%rsi
.cfi_endproc
.LFE4292:
.size _ZNSolsEPFRSoS_E.isra.0, .-_ZNSolsEPFRSoS_E.isra.0
.globl _Z47__device_stub__Z21clothSimulationKernelPfS_S_ffPfS_S_ff
.type _Z47__device_stub__Z21clothSimulationKernelPfS_S_ffPfS_S_ff, @function
_Z47__device_stub__Z21clothSimulationKernelPfS_S_ffPfS_S_ff:
.LFB3660:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
leaq 40(%rsp), %rcx
leaq 48(%rsp), %rdi
movq %rsi, 16(%rsp)
leaq 60(%rsp), %rsi
movq %rdx, 8(%rsp)
leaq 32(%rsp), %rdx
movss %xmm0, 4(%rsp)
movss %xmm1, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movl $1, 56(%rsp)
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movabsq $4294967297, %rax
movq %rax, 48(%rsp)
movq %rax, 60(%rsp)
movl $1, 68(%rsp)
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
jne .L3
pushq 40(%rsp)
.cfi_def_cfa_offset 168
leaq _Z21clothSimulationKernelPfS_S_ff(%rip), %rdi
pushq 40(%rsp)
.cfi_def_cfa_offset 176
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq 112(%rsp), %r9
call cudaLaunchKernel@PLT
popq %rax
.cfi_def_cfa_offset 168
popq %rdx
.cfi_def_cfa_offset 160
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
je .L5
call __stack_chk_fail@PLT
.L5:
addq $152, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3660:
.size _Z47__device_stub__Z21clothSimulationKernelPfS_S_ffPfS_S_ff, .-_Z47__device_stub__Z21clothSimulationKernelPfS_S_ffPfS_S_ff
.globl _Z21clothSimulationKernelPfS_S_ff
.type _Z21clothSimulationKernelPfS_S_ff, @function
_Z21clothSimulationKernelPfS_S_ff:
.LFB3661:
.cfi_startproc
endbr64
jmp _Z47__device_stub__Z21clothSimulationKernelPfS_S_ffPfS_S_ff
.cfi_endproc
.LFE3661:
.size _Z21clothSimulationKernelPfS_S_ff, .-_Z21clothSimulationKernelPfS_S_ff
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Failed to allocate device memory for positions"
.LC1:
.string "Failed to allocate device memory for velocities"
.LC2:
.string "Failed to allocate device memory for forces"
.LC3:
.string "Failed to copy positions from host to device"
.LC4:
.string "Failed to copy velocities from host to device"
.LC5:
.string "Failed to copy forces from host to device"
.LC8:
.string "Kernel launch failed: "
.LC9:
.string "Failed to copy positions from device to host"
.LC10:
.string "Cloth simulation completed successfully."
.section .text.startup,"ax",@progbits
.globl main
.type main, @function
main:
.LFB3635:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
movl $262144, %edi
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $64, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
call _Znam@PLT
movl $262144, %edi
movq %rax, %rbx
call _Znam@PLT
movl $262144, %edi
movq %rax, %r12
call _Znam@PLT
movl $65536, %ecx
movq %rbx, %rdi
movl $262144, %esi
movq %rax, %rbp
xorl %eax, %eax
rep stosl
movl $65536, %ecx
movq %r12, %rdi
rep stosl
movl $65536, %ecx
movq %rbp, %rdi
rep stosl
leaq 8(%rsp), %rdi
call cudaMalloc@PLT
testl %eax, %eax
je .L10
leaq .LC0(%rip), %rsi
leaq _ZSt4cerr(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@GOTPCREL(%rip), %rsi
movq %rax, %rdi
call _ZNSolsEPFRSoS_E.isra.0
jmp .L11
.L10:
leaq 16(%rsp), %rdi
movl $262144, %esi
call cudaMalloc@PLT
testl %eax, %eax
je .L12
leaq .LC1(%rip), %rsi
leaq _ZSt4cerr(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@GOTPCREL(%rip), %rsi
movq %rax, %rdi
call _ZNSolsEPFRSoS_E.isra.0
movq 8(%rsp), %rdi
.L24:
call cudaFree@PLT
.L11:
orl $-1, %eax
jmp .L9
.L12:
leaq 24(%rsp), %rdi
movl $262144, %esi
call cudaMalloc@PLT
testl %eax, %eax
je .L14
leaq .LC2(%rip), %rsi
leaq _ZSt4cerr(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@GOTPCREL(%rip), %rsi
movq %rax, %rdi
call _ZNSolsEPFRSoS_E.isra.0
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
jmp .L24
.L14:
movq 8(%rsp), %rdi
movq %rbx, %rsi
movl $1, %ecx
movl $262144, %edx
call cudaMemcpy@PLT
leaq .LC3(%rip), %rsi
testl %eax, %eax
jne .L25
movq 16(%rsp), %rdi
movq %r12, %rsi
movl $1, %ecx
movl $262144, %edx
call cudaMemcpy@PLT
leaq .LC4(%rip), %rsi
testl %eax, %eax
jne .L25
movq 24(%rsp), %rdi
movl $1, %ecx
movl $262144, %edx
movq %rbp, %rsi
call cudaMemcpy@PLT
testl %eax, %eax
je .L17
leaq .LC5(%rip), %rsi
.L25:
leaq _ZSt4cerr(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@GOTPCREL(%rip), %rsi
movq %rax, %rdi
call _ZNSolsEPFRSoS_E.isra.0
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
jmp .L24
.L17:
xorl %r9d, %r9d
xorl %r8d, %r8d
movl $1, %ecx
movl $1, %esi
movabsq $68719476752, %rdi
movq %rdi, %rdx
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L18
movss .LC6(%rip), %xmm1
movss .LC7(%rip), %xmm0
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z47__device_stub__Z21clothSimulationKernelPfS_S_ffPfS_S_ff
.L18:
call cudaGetLastError@PLT
movl %eax, %r13d
testl %eax, %eax
je .L19
leaq .LC8(%rip), %rsi
leaq _ZSt4cerr(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movl %r13d, %edi
movq %rax, %r14
call cudaGetErrorString@PLT
movq %r14, %rdi
movq %rax, %rsi
jmp .L23
.L19:
movq 8(%rsp), %rsi
movl $2, %ecx
movl $262144, %edx
movq %rbx, %rdi
call cudaMemcpy@PLT
testl %eax, %eax
je .L20
leaq .LC9(%rip), %rsi
leaq _ZSt4cerr(%rip), %rdi
.L23:
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@GOTPCREL(%rip), %rsi
movq %rax, %rdi
call _ZNSolsEPFRSoS_E.isra.0
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq %rbx, %rdi
call _ZdaPv@PLT
movq %r12, %rdi
call _ZdaPv@PLT
movq %rbp, %rdi
call _ZdaPv@PLT
jmp .L11
.L20:
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq %rbx, %rdi
call _ZdaPv@PLT
movq %r12, %rdi
call _ZdaPv@PLT
movq %rbp, %rdi
call _ZdaPv@PLT
leaq .LC10(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@GOTPCREL(%rip), %rsi
movq %rax, %rdi
call _ZNSolsEPFRSoS_E.isra.0
xorl %eax, %eax
.L9:
movq 56(%rsp), %rdx
subq %fs:40, %rdx
je .L21
call __stack_chk_fail@PLT
.L21:
addq $64, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3635:
.size main, .-main
.section .rodata.str1.1
.LC11:
.string "_Z21clothSimulationKernelPfS_S_ff"
.section .text.startup
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3663:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
pushq $0
.cfi_def_cfa_offset 24
xorl %r9d, %r9d
orl $-1, %r8d
pushq $0
.cfi_def_cfa_offset 32
leaq .LC11(%rip), %rdx
movq %rax, %rdi
leaq _Z21clothSimulationKernelPfS_S_ff(%rip), %rsi
pushq $0
.cfi_def_cfa_offset 40
movq %rdx, %rcx
pushq $0
.cfi_def_cfa_offset 48
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFunction@PLT
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
addq $32, %rsp
.cfi_def_cfa_offset 16
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
popq %rdx
.cfi_def_cfa_offset 8
jmp atexit@PLT
.cfi_endproc
.LFE3663:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC6:
.long 1065185444
.align 4
.LC7:
.long 1008981770
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
```
|
```amdasm
.text
.file "cuda_code_039448.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z36__device_stub__clothSimulationKernelPfS_S_ff # -- Begin function _Z36__device_stub__clothSimulationKernelPfS_S_ff
.type _Z36__device_stub__clothSimulationKernelPfS_S_ff,@function
_Z36__device_stub__clothSimulationKernelPfS_S_ff: # @_Z36__device_stub__clothSimulationKernelPfS_S_ff
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $128, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 40(%rsp), %rax
movq %rdi, (%rax)
leaq 32(%rsp), %rcx
movq %rsi, (%rcx)
leaq 24(%rsp), %rsi
movq %rdx, (%rsi)
leaq 4(%rsp), %rdx
movss %xmm0, (%rdx)
movq %rsp, %rdi
movss %xmm1, (%rdi)
leaq 80(%rsp), %rbx
movq %rax, (%rbx)
movq %rcx, 8(%rbx)
movq %rsi, 16(%rbx)
movq %rdx, 24(%rbx)
movq %rdi, 32(%rbx)
leaq 64(%rsp), %r14
leaq 48(%rsp), %r15
leaq 16(%rsp), %r12
leaq 8(%rsp), %r13
movq %r14, %rdi
movq %r15, %rsi
movq %r12, %rdx
movq %r13, %rcx
callq __hipPopCallConfiguration
movq (%r14), %rsi
movl 8(%r14), %edx
movq (%r15), %rcx
movl 8(%r15), %r8d
movl $_Z21clothSimulationKernelPfS_S_ff, %edi
movq %rbx, %r9
pushq (%r13)
.cfi_adjust_cfa_offset 8
pushq (%r12)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $144, %rsp
.cfi_adjust_cfa_offset -144
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z36__device_stub__clothSimulationKernelPfS_S_ff, .Lfunc_end0-_Z36__device_stub__clothSimulationKernelPfS_S_ff
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI1_0:
.long 0x3c23d70a # float 0.00999999977
.LCPI1_1:
.long 0x3f7d70a4 # float 0.990000009
.text
.globl main
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $24, %rsp
.cfi_def_cfa_offset 64
.cfi_offset %rbx, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $262144, %edi # imm = 0x40000
callq _Znam
movq %rax, %r15
movl $262144, %edi # imm = 0x40000
callq _Znam
movq %rax, %r14
movl $262144, %edi # imm = 0x40000
callq _Znam
movq %rax, %rbx
movl $262144, %edx # imm = 0x40000
movq %r15, %rdi
xorl %esi, %esi
callq memset@PLT
movl $262144, %edx # imm = 0x40000
movq %r14, %rdi
xorl %esi, %esi
callq memset@PLT
movl $262144, %edx # imm = 0x40000
movq %rbx, %rdi
xorl %esi, %esi
callq memset@PLT
movq %rsp, %rdi
movl $262144, %esi # imm = 0x40000
callq hipMalloc
testl %eax, %eax
je .LBB1_2
# %bb.1:
movl $_ZSt4cerr, %ebx
movl $_ZSt4cerr, %edi
movl $.L.str, %esi
movl $46, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cerr(%rip), %rax
movq -24(%rax), %rdi
addq %rbx, %rdi
movl $10, %esi
callq _ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
movsbl %al, %esi
movl $_ZSt4cerr, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
jmp .LBB1_15
.LBB1_2:
leaq 8(%rsp), %rdi
movl $262144, %esi # imm = 0x40000
callq hipMalloc
testl %eax, %eax
je .LBB1_4
# %bb.3:
movl $_ZSt4cerr, %ebx
movl $_ZSt4cerr, %edi
movl $.L.str.1, %esi
movl $47, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cerr(%rip), %rax
movq -24(%rax), %rdi
addq %rbx, %rdi
movl $10, %esi
callq _ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
movsbl %al, %esi
movl $_ZSt4cerr, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq (%rsp), %rdi
jmp .LBB1_14
.LBB1_4:
leaq 16(%rsp), %rdi
movl $262144, %esi # imm = 0x40000
callq hipMalloc
testl %eax, %eax
je .LBB1_6
# %bb.5:
movl $_ZSt4cerr, %ebx
movl $_ZSt4cerr, %edi
movl $.L.str.2, %esi
movl $43, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cerr(%rip), %rax
movq -24(%rax), %rdi
addq %rbx, %rdi
movl $10, %esi
callq _ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
movsbl %al, %esi
movl $_ZSt4cerr, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq (%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
jmp .LBB1_14
.LBB1_6:
movq (%rsp), %rdi
movl $262144, %edx # imm = 0x40000
movq %r15, %rsi
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
je .LBB1_8
# %bb.7:
movl $_ZSt4cerr, %ebx
movl $_ZSt4cerr, %edi
movl $.L.str.3, %esi
movl $44, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cerr(%rip), %rax
movq -24(%rax), %rdi
addq %rbx, %rdi
movl $10, %esi
callq _ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
movsbl %al, %esi
movl $_ZSt4cerr, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
jmp .LBB1_13
.LBB1_8:
movq 8(%rsp), %rdi
movl $262144, %edx # imm = 0x40000
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
je .LBB1_10
# %bb.9:
movl $_ZSt4cerr, %edi
movl $.L.str.4, %esi
movl $45, %edx
jmp .LBB1_12
.LBB1_10:
movq 16(%rsp), %rdi
movl $262144, %edx # imm = 0x40000
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
je .LBB1_17
# %bb.11:
movl $_ZSt4cerr, %edi
movl $.L.str.5, %esi
movl $41, %edx
.LBB1_12:
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cerr, %edi
callq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_
.LBB1_13:
movq (%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
.LBB1_14:
callq hipFree
.LBB1_15:
movl $-1, %eax
.LBB1_16:
addq $24, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB1_17:
.cfi_def_cfa_offset 64
movabsq $68719476752, %rdi # imm = 0x1000000010
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_19
# %bb.18:
movq (%rsp), %rdi
movq 8(%rsp), %rsi
movq 16(%rsp), %rdx
movss .LCPI1_0(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero
movss .LCPI1_1(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero
callq _Z36__device_stub__clothSimulationKernelPfS_S_ff
.LBB1_19:
callq hipGetLastError
testl %eax, %eax
je .LBB1_21
# %bb.20:
movl %eax, %ebp
movl $_ZSt4cerr, %edi
movl $.L.str.6, %esi
movl $22, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl %ebp, %edi
callq hipGetErrorString
movl $_ZSt4cerr, %edi
movq %rax, %rsi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movq %rax, %rdi
jmp .LBB1_23
.LBB1_21:
movq (%rsp), %rsi
movl $262144, %edx # imm = 0x40000
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
je .LBB1_24
# %bb.22:
movl $_ZSt4cerr, %edi
movl $.L.str.7, %esi
movl $44, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cerr, %edi
.LBB1_23:
callq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_
movq (%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq %r15, %rdi
callq _ZdaPv
movq %r14, %rdi
callq _ZdaPv
movq %rbx, %rdi
callq _ZdaPv
jmp .LBB1_15
.LBB1_24:
movq (%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq %r15, %rdi
callq _ZdaPv
movq %r14, %rdi
callq _ZdaPv
movq %rbx, %rdi
callq _ZdaPv
movl $_ZSt4cout, %edi
movl $.L.str.8, %esi
movl $40, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
callq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_
xorl %eax, %eax
jmp .LBB1_16
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, %rdi
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z21clothSimulationKernelPfS_S_ff, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z21clothSimulationKernelPfS_S_ff,@object # @_Z21clothSimulationKernelPfS_S_ff
.section .rodata,"a",@progbits
.globl _Z21clothSimulationKernelPfS_S_ff
.p2align 3, 0x0
_Z21clothSimulationKernelPfS_S_ff:
.quad _Z36__device_stub__clothSimulationKernelPfS_S_ff
.size _Z21clothSimulationKernelPfS_S_ff, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Failed to allocate device memory for positions"
.size .L.str, 47
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Failed to allocate device memory for velocities"
.size .L.str.1, 48
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Failed to allocate device memory for forces"
.size .L.str.2, 44
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Failed to copy positions from host to device"
.size .L.str.3, 45
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Failed to copy velocities from host to device"
.size .L.str.4, 46
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "Failed to copy forces from host to device"
.size .L.str.5, 42
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "Kernel launch failed: "
.size .L.str.6, 23
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "Failed to copy positions from device to host"
.size .L.str.7, 45
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "Cloth simulation completed successfully."
.size .L.str.8, 41
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z21clothSimulationKernelPfS_S_ff"
.size .L__unnamed_1, 34
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z36__device_stub__clothSimulationKernelPfS_S_ff
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z21clothSimulationKernelPfS_S_ff
.addrsig_sym _ZSt4cerr
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
```
| 4,838 | 6,022 |
113,652 |
Convert the following CUDA device assembly code to AMD device assembly:
```cudaasm
code for sm_80
Function : _Z19divergenceReductionPfS_S_ff
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ;
S2R R0, SR_CTAID.X ;
S2R R3, SR_TID.X ;
IMAD R0, R0, c[0x0][0x0], R3 ;
ISETP.GT.AND P0, PT, R0, 0x3ffe, PT ;
@P0 EXIT ;
IMAD.MOV.U32 R5, RZ, RZ, 0x4 ;
ULDC.64 UR4, c[0x0][0x118] ;
IMAD.WIDE R4, R0, R5, c[0x0][0x160] ;
LDG.E R2, [R4.64] ;
LDG.E R3, [R4.64+0x4] ;
MUFU.RCP R6, c[0x0][0x178] ;
IMAD.MOV.U32 R7, RZ, RZ, c[0x0][0x178] ;
BSSY B0, 0x1c0 ;
FFMA R7, R6, -R7, 1 ;
FADD R3, -R2, R3 ;
FFMA R2, R6, R7, R6 ;
FCHK P0, R3, c[0x0][0x178] ;
FFMA R6, R3, R2, RZ ;
FFMA R7, R6, -c[0x0][0x178], R3 ;
FFMA R2, R2, R7, R6 ;
@!P0 BRA 0x1b0 ;
IMAD.MOV.U32 R7, RZ, RZ, R3 ;
MOV R4, 0x1a0 ;
IMAD.MOV.U32 R6, RZ, RZ, c[0x0][0x178] ;
CALL.REL.NOINC 0x360 ;
IMAD.MOV.U32 R2, RZ, RZ, R3 ;
BSYNC B0 ;
IMAD.MOV.U32 R5, RZ, RZ, 0x4 ;
IMAD.WIDE R4, R0, R5, c[0x0][0x168] ;
LDG.E R3, [R4.64] ;
LDG.E R6, [R4.64+0x4] ;
MUFU.RCP R7, c[0x0][0x17c] ;
IMAD.MOV.U32 R8, RZ, RZ, c[0x0][0x17c] ;
BSSY B0, 0x310 ;
FFMA R8, R7, -R8, 1 ;
FFMA R8, R7, R8, R7 ;
FADD R3, -R3, R6 ;
FCHK P0, R3, c[0x0][0x17c] ;
FFMA R6, R3, R8, RZ ;
FFMA R7, R6, -c[0x0][0x17c], R3 ;
FFMA R7, R8, R7, R6 ;
@!P0 BRA 0x300 ;
IMAD.MOV.U32 R7, RZ, RZ, R3 ;
MOV R4, 0x2f0 ;
IMAD.MOV.U32 R6, RZ, RZ, c[0x0][0x17c] ;
CALL.REL.NOINC 0x360 ;
IMAD.MOV.U32 R7, RZ, RZ, R3 ;
BSYNC B0 ;
IMAD.MOV.U32 R3, RZ, RZ, 0x4 ;
FADD R7, R7, R2 ;
IMAD.WIDE R2, R0, R3, c[0x0][0x170] ;
STG.E [R2.64], R7 ;
EXIT ;
SHF.R.U32.HI R5, RZ, 0x17, R6 ;
BSSY B1, 0x9b0 ;
SHF.R.U32.HI R3, RZ, 0x17, R7.reuse ;
LOP3.LUT R11, R5, 0xff, RZ, 0xc0, !PT ;
LOP3.LUT R9, R3, 0xff, RZ, 0xc0, !PT ;
IMAD.MOV.U32 R3, RZ, RZ, R7 ;
IADD3 R10, R11, -0x1, RZ ;
IADD3 R8, R9, -0x1, RZ ;
ISETP.GT.U32.AND P0, PT, R10, 0xfd, PT ;
ISETP.GT.U32.OR P0, PT, R8, 0xfd, P0 ;
@!P0 IMAD.MOV.U32 R5, RZ, RZ, RZ ;
@!P0 BRA 0x590 ;
FSETP.GTU.FTZ.AND P0, PT, |R7|, +INF , PT ;
FSETP.GTU.FTZ.AND P1, PT, |R6|, +INF , PT ;
PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ;
@P0 BRA 0x990 ;
LOP3.LUT P0, RZ, R6, 0x7fffffff, R3, 0xc8, !PT ;
@!P0 BRA 0x970 ;
FSETP.NEU.FTZ.AND P2, PT, |R7|.reuse, +INF , PT ;
FSETP.NEU.FTZ.AND P1, PT, |R6|, +INF , PT ;
FSETP.NEU.FTZ.AND P0, PT, |R7|, +INF , PT ;
@!P1 BRA !P2, 0x970 ;
LOP3.LUT P2, RZ, R3, 0x7fffffff, RZ, 0xc0, !PT ;
PLOP3.LUT P1, PT, P1, P2, PT, 0x2a, 0x0 ;
@P1 BRA 0x950 ;
LOP3.LUT P1, RZ, R6, 0x7fffffff, RZ, 0xc0, !PT ;
PLOP3.LUT P0, PT, P0, P1, PT, 0x2a, 0x0 ;
@P0 BRA 0x920 ;
ISETP.GE.AND P0, PT, R8, RZ, PT ;
ISETP.GE.AND P1, PT, R10, RZ, PT ;
@P0 IMAD.MOV.U32 R5, RZ, RZ, RZ ;
@!P0 IMAD.MOV.U32 R5, RZ, RZ, -0x40 ;
@!P0 FFMA R3, R7, 1.84467440737095516160e+19, RZ ;
@!P1 FFMA R6, R6, 1.84467440737095516160e+19, RZ ;
@!P1 IADD3 R5, R5, 0x40, RZ ;
LEA R7, R11, 0xc0800000, 0x17 ;
BSSY B2, 0x910 ;
IMAD.IADD R7, R6, 0x1, -R7 ;
IADD3 R6, R9, -0x7f, RZ ;
MUFU.RCP R8, R7 ;
FADD.FTZ R10, -R7, -RZ ;
IMAD R3, R6, -0x800000, R3 ;
FFMA R9, R8, R10, 1 ;
FFMA R12, R8, R9, R8 ;
FFMA R8, R3, R12, RZ ;
FFMA R9, R10, R8, R3 ;
FFMA R9, R12, R9, R8 ;
IADD3 R8, R6, 0x7f, -R11 ;
FFMA R10, R10, R9, R3 ;
IMAD.IADD R8, R8, 0x1, R5 ;
FFMA R3, R12, R10, R9 ;
SHF.R.U32.HI R6, RZ, 0x17, R3 ;
LOP3.LUT R6, R6, 0xff, RZ, 0xc0, !PT ;
IMAD.IADD R11, R6, 0x1, R8 ;
IADD3 R5, R11, -0x1, RZ ;
ISETP.GE.U32.AND P0, PT, R5, 0xfe, PT ;
@!P0 BRA 0x8f0 ;
ISETP.GT.AND P0, PT, R11, 0xfe, PT ;
@P0 BRA 0x8c0 ;
ISETP.GE.AND P0, PT, R11, 0x1, PT ;
@P0 BRA 0x900 ;
ISETP.GE.AND P0, PT, R11, -0x18, PT ;
LOP3.LUT R3, R3, 0x80000000, RZ, 0xc0, !PT ;
@!P0 BRA 0x900 ;
FFMA.RZ R5, R12.reuse, R10.reuse, R9.reuse ;
IADD3 R8, R11.reuse, 0x20, RZ ;
FFMA.RM R6, R12.reuse, R10.reuse, R9.reuse ;
ISETP.NE.AND P2, PT, R11, RZ, PT ;
LOP3.LUT R7, R5, 0x7fffff, RZ, 0xc0, !PT ;
FFMA.RP R5, R12, R10, R9 ;
ISETP.NE.AND P1, PT, R11, RZ, PT ;
IMAD.MOV R9, RZ, RZ, -R11 ;
LOP3.LUT R7, R7, 0x800000, RZ, 0xfc, !PT ;
FSETP.NEU.FTZ.AND P0, PT, R5, R6, PT ;
SHF.L.U32 R8, R7, R8, RZ ;
SEL R6, R9, RZ, P2 ;
ISETP.NE.AND P1, PT, R8, RZ, P1 ;
SHF.R.U32.HI R6, RZ, R6, R7 ;
PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ;
SHF.R.U32.HI R8, RZ, 0x1, R6 ;
SEL R5, RZ, 0x1, !P0 ;
LOP3.LUT R5, R5, 0x1, R8, 0xf8, !PT ;
LOP3.LUT R5, R5, R6, RZ, 0xc0, !PT ;
IMAD.IADD R8, R8, 0x1, R5 ;
LOP3.LUT R3, R8, R3, RZ, 0xfc, !PT ;
BRA 0x900 ;
LOP3.LUT R3, R3, 0x80000000, RZ, 0xc0, !PT ;
LOP3.LUT R3, R3, 0x7f800000, RZ, 0xfc, !PT ;
BRA 0x900 ;
IMAD R3, R8, 0x800000, R3 ;
BSYNC B2 ;
BRA 0x9a0 ;
LOP3.LUT R3, R6, 0x80000000, R3, 0x48, !PT ;
LOP3.LUT R3, R3, 0x7f800000, RZ, 0xfc, !PT ;
BRA 0x9a0 ;
LOP3.LUT R3, R6, 0x80000000, R3, 0x48, !PT ;
BRA 0x9a0 ;
MUFU.RSQ R3, -QNAN ;
BRA 0x9a0 ;
FADD.FTZ R3, R7, R6 ;
BSYNC B1 ;
IMAD.MOV.U32 R5, RZ, RZ, 0x0 ;
RET.REL.NODEC R4 0x0 ;
BRA 0x9d0;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
```
|
```amdasm
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z19divergenceReductionPfS_S_ff ; -- Begin function _Z19divergenceReductionPfS_S_ff
.globl _Z19divergenceReductionPfS_S_ff
.p2align 8
.type _Z19divergenceReductionPfS_S_ff,@function
_Z19divergenceReductionPfS_S_ff: ; @_Z19divergenceReductionPfS_S_ff
; %bb.0:
s_load_b32 s2, s[0:1], 0x2c
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e32 0x3fff, v1
s_cbranch_execz .LBB0_2
; %bb.1:
s_load_b256 s[0:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s3, v1, vcc_lo
global_load_b64 v[2:3], v[2:3], off
global_load_b64 v[4:5], v[4:5], off
s_waitcnt vmcnt(0)
v_dual_sub_f32 v2, v3, v2 :: v_dual_sub_f32 v3, v5, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_div_scale_f32 v4, null, s6, s6, v2
v_div_scale_f32 v5, null, s7, s7, v3
v_div_scale_f32 v10, vcc_lo, v2, s6, v2
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_rcp_f32_e32 v6, v4
v_rcp_f32_e32 v7, v5
s_waitcnt_depctr 0xfff
v_fma_f32 v8, -v4, v6, 1.0
v_fma_f32 v9, -v5, v7, 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_dual_fmac_f32 v6, v8, v6 :: v_dual_fmac_f32 v7, v9, v7
v_div_scale_f32 v8, s0, v3, s7, v3
v_mul_f32_e32 v9, v10, v6
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_f32_e32 v11, v8, v7
v_fma_f32 v12, -v4, v9, v10
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v13, -v5, v11, v8
v_fmac_f32_e32 v9, v12, v6
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fmac_f32_e32 v11, v13, v7
v_fma_f32 v4, -v4, v9, v10
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v5, -v5, v11, v8
v_div_fmas_f32 v4, v4, v6, v9
s_mov_b32 vcc_lo, s0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_div_fmas_f32 v5, v5, v7, v11
v_add_co_u32 v0, vcc_lo, s4, v0
v_div_fixup_f32 v2, v4, s6, v2
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fixup_f32 v3, v5, s7, v3
v_add_f32_e32 v2, v2, v3
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z19divergenceReductionPfS_S_ff
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 14
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z19divergenceReductionPfS_S_ff, .Lfunc_end0-_Z19divergenceReductionPfS_S_ff
; -- End function
.section .AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 356
; NumSgprs: 18
; NumVgprs: 14
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 14
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object ; @__hip_cuid_
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0 ; 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z19divergenceReductionPfS_S_ff
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z19divergenceReductionPfS_S_ff.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 14
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
```
| 3,129 | 3,387 |
113,653 |
Convert the following CUDA host assembly code to AMD host assembly:
```cudaasm
.file "tmpxft_0000ba2e_00000000-6_cuda_code_083801.cudafe1.cpp"
.text
.globl _ZSt21ios_base_library_initv
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3852:
.cfi_startproc
endbr64
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
jmp __cudaUnregisterFatBinary@PLT
.cfi_endproc
.LFE3852:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z45__device_stub__Z19divergenceReductionPfS_S_ffPfS_S_ff
.type _Z45__device_stub__Z19divergenceReductionPfS_S_ffPfS_S_ff, @function
_Z45__device_stub__Z19divergenceReductionPfS_S_ffPfS_S_ff:
.LFB3874:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
leaq 40(%rsp), %rcx
leaq 48(%rsp), %rdi
movq %rsi, 16(%rsp)
leaq 60(%rsp), %rsi
movq %rdx, 8(%rsp)
leaq 32(%rsp), %rdx
movss %xmm0, 4(%rsp)
movss %xmm1, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movl $1, 56(%rsp)
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movabsq $4294967297, %rax
movq %rax, 48(%rsp)
movq %rax, 60(%rsp)
movl $1, 68(%rsp)
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
jne .L2
pushq 40(%rsp)
.cfi_def_cfa_offset 168
leaq _Z19divergenceReductionPfS_S_ff(%rip), %rdi
pushq 40(%rsp)
.cfi_def_cfa_offset 176
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq 112(%rsp), %r9
call cudaLaunchKernel@PLT
popq %rax
.cfi_def_cfa_offset 168
popq %rdx
.cfi_def_cfa_offset 160
.L2:
movq 136(%rsp), %rax
subq %fs:40, %rax
je .L4
call __stack_chk_fail@PLT
.L4:
addq $152, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3874:
.size _Z45__device_stub__Z19divergenceReductionPfS_S_ffPfS_S_ff, .-_Z45__device_stub__Z19divergenceReductionPfS_S_ffPfS_S_ff
.globl _Z19divergenceReductionPfS_S_ff
.type _Z19divergenceReductionPfS_S_ff, @function
_Z19divergenceReductionPfS_S_ff:
.LFB3875:
.cfi_startproc
endbr64
jmp _Z45__device_stub__Z19divergenceReductionPfS_S_ffPfS_S_ff
.cfi_endproc
.LFE3875:
.size _Z19divergenceReductionPfS_S_ff, .-_Z19divergenceReductionPfS_S_ff
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "CUDA error: "
.section .text.startup,"ax",@progbits
.globl main
.type main, @function
main:
.LFB3849:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
xorl %edi, %edi
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $72, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
call cudaSetDevice@PLT
movl $65536, %edi
call _Znam@PLT
movl $65536, %edi
movq %rax, %rbp
call _Znam@PLT
movl $65536, %edi
movq %rax, %rbx
call _Znam@PLT
leaq 8(%rsp), %rdi
movl $65536, %esi
movq %rax, %r12
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $65536, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $65536, %esi
call cudaMalloc@PLT
movss .LC0(%rip), %xmm0
xorl %eax, %eax
.L9:
movss %xmm0, 0(%rbp,%rax)
movss %xmm0, (%rbx,%rax)
addq $4, %rax
cmpq $65536, %rax
jne .L9
movq 8(%rsp), %rdi
movl $1, %ecx
movl $65536, %edx
movq %rbp, %rsi
call cudaMemcpy@PLT
movq 16(%rsp), %rdi
movl $1, %ecx
movq %rbx, %rsi
movl $65536, %edx
call cudaMemcpy@PLT
movl $16777217, %edx
xorl %r9d, %r9d
xorl %r8d, %r8d
movl $67108865, %edi
salq $8, %rdx
movl $1, %ecx
movl $1, %esi
salq $6, %rdi
call __cudaPushCallConfiguration@PLT
movss .LC0(%rip), %xmm0
testl %eax, %eax
jne .L10
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movaps %xmm0, %xmm1
movq 8(%rsp), %rdi
call _Z45__device_stub__Z19divergenceReductionPfS_S_ffPfS_S_ff
.L10:
call cudaGetLastError@PLT
movl %eax, %r13d
testl %eax, %eax
je .L11
leaq .LC1(%rip), %rsi
leaq _ZSt4cerr(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movl %r13d, %edi
movq %rax, %rbx
call cudaGetErrorString@PLT
movq %rbx, %rdi
movq %rax, %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
orl $-1, %eax
jmp .L8
.L11:
movq 24(%rsp), %rsi
movl $2, %ecx
movl $65536, %edx
movq %r12, %rdi
call cudaMemcpy@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq %rbp, %rdi
call _ZdaPv@PLT
movq %rbx, %rdi
call _ZdaPv@PLT
movq %r12, %rdi
call _ZdaPv@PLT
xorl %eax, %eax
.L8:
movq 56(%rsp), %rdx
subq %fs:40, %rdx
je .L13
call __stack_chk_fail@PLT
.L13:
addq $72, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3849:
.size main, .-main
.section .rodata.str1.1
.LC2:
.string "_Z19divergenceReductionPfS_S_ff"
.LC3:
.string "precalc_xorwow_matrix"
.LC4:
.string "precalc_xorwow_offset_matrix"
.LC5:
.string "mrg32k3aM1"
.LC6:
.string "mrg32k3aM2"
.LC7:
.string "mrg32k3aM1SubSeq"
.LC8:
.string "mrg32k3aM2SubSeq"
.LC9:
.string "mrg32k3aM1Seq"
.LC10:
.string "mrg32k3aM2Seq"
.LC11:
.string "__cr_lgamma_table"
.section .text.startup
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3877:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
pushq $0
.cfi_def_cfa_offset 24
xorl %r9d, %r9d
orl $-1, %r8d
pushq $0
.cfi_def_cfa_offset 32
leaq .LC2(%rip), %rdx
movq %rax, %rdi
movq %rax, %rbx
pushq $0
.cfi_def_cfa_offset 40
movq %rdx, %rcx
leaq _Z19divergenceReductionPfS_S_ff(%rip), %rsi
pushq $0
.cfi_def_cfa_offset 48
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq %rbx, %rdi
xorl %r8d, %r8d
pushq $0
.cfi_def_cfa_offset 24
leaq .LC3(%rip), %rdx
movl $102400, %r9d
leaq _ZL21precalc_xorwow_matrix(%rip), %rsi
pushq $0
.cfi_def_cfa_offset 32
movq %rdx, %rcx
call __cudaRegisterVar@PLT
popq %rax
.cfi_def_cfa_offset 24
popq %rdx
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
leaq .LC4(%rip), %rdx
movq %rbx, %rdi
xorl %r8d, %r8d
movq %rdx, %rcx
movl $102400, %r9d
leaq _ZL28precalc_xorwow_offset_matrix(%rip), %rsi
call __cudaRegisterVar@PLT
popq %rcx
.cfi_def_cfa_offset 24
popq %rsi
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
leaq .LC5(%rip), %rdx
movq %rbx, %rdi
xorl %r8d, %r8d
movq %rdx, %rcx
movl $2304, %r9d
leaq _ZL10mrg32k3aM1(%rip), %rsi
call __cudaRegisterVar@PLT
popq %rdi
.cfi_def_cfa_offset 24
popq %r8
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
leaq .LC6(%rip), %rdx
movq %rbx, %rdi
xorl %r8d, %r8d
movq %rdx, %rcx
movl $2304, %r9d
leaq _ZL10mrg32k3aM2(%rip), %rsi
call __cudaRegisterVar@PLT
popq %r9
.cfi_def_cfa_offset 24
popq %r10
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
leaq .LC7(%rip), %rdx
movq %rbx, %rdi
xorl %r8d, %r8d
movq %rdx, %rcx
movl $2016, %r9d
leaq _ZL16mrg32k3aM1SubSeq(%rip), %rsi
call __cudaRegisterVar@PLT
popq %r11
.cfi_def_cfa_offset 24
popq %rax
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
leaq .LC8(%rip), %rdx
movq %rbx, %rdi
xorl %r8d, %r8d
movq %rdx, %rcx
movl $2016, %r9d
leaq _ZL16mrg32k3aM2SubSeq(%rip), %rsi
call __cudaRegisterVar@PLT
popq %rax
.cfi_def_cfa_offset 24
popq %rdx
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
leaq .LC9(%rip), %rdx
movq %rbx, %rdi
xorl %r8d, %r8d
movq %rdx, %rcx
movl $2304, %r9d
leaq _ZL13mrg32k3aM1Seq(%rip), %rsi
call __cudaRegisterVar@PLT
popq %rcx
.cfi_def_cfa_offset 24
popq %rsi
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
leaq .LC10(%rip), %rdx
movq %rbx, %rdi
xorl %r8d, %r8d
movq %rdx, %rcx
movl $2304, %r9d
leaq _ZL13mrg32k3aM2Seq(%rip), %rsi
call __cudaRegisterVar@PLT
popq %rdi
.cfi_def_cfa_offset 24
popq %r8
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
leaq .LC11(%rip), %rdx
movq %rbx, %rdi
xorl %r8d, %r8d
movl $72, %r9d
movq %rdx, %rcx
leaq _ZL17__cr_lgamma_table(%rip), %rsi
call __cudaRegisterVar@PLT
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
popq %r9
.cfi_def_cfa_offset 24
popq %r10
.cfi_def_cfa_offset 16
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit@PLT
.cfi_endproc
.LFE3877:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZL17__cr_lgamma_table
.comm _ZL17__cr_lgamma_table,72,32
.local _ZL13mrg32k3aM2Seq
.comm _ZL13mrg32k3aM2Seq,2304,32
.local _ZL13mrg32k3aM1Seq
.comm _ZL13mrg32k3aM1Seq,2304,32
.local _ZL16mrg32k3aM2SubSeq
.comm _ZL16mrg32k3aM2SubSeq,2016,32
.local _ZL16mrg32k3aM1SubSeq
.comm _ZL16mrg32k3aM1SubSeq,2016,32
.local _ZL10mrg32k3aM2
.comm _ZL10mrg32k3aM2,2304,32
.local _ZL10mrg32k3aM1
.comm _ZL10mrg32k3aM1,2304,32
.local _ZL28precalc_xorwow_offset_matrix
.comm _ZL28precalc_xorwow_offset_matrix,102400,32
.local _ZL21precalc_xorwow_matrix
.comm _ZL21precalc_xorwow_matrix,102400,32
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC0:
.long 1065353216
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
```
|
```amdasm
.text
.file "cuda_code_083801.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z34__device_stub__divergenceReductionPfS_S_ff # -- Begin function _Z34__device_stub__divergenceReductionPfS_S_ff
.type _Z34__device_stub__divergenceReductionPfS_S_ff,@function
_Z34__device_stub__divergenceReductionPfS_S_ff: # @_Z34__device_stub__divergenceReductionPfS_S_ff
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $128, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 40(%rsp), %rax
movq %rdi, (%rax)
leaq 32(%rsp), %rcx
movq %rsi, (%rcx)
leaq 24(%rsp), %rsi
movq %rdx, (%rsi)
leaq 4(%rsp), %rdx
movss %xmm0, (%rdx)
movq %rsp, %rdi
movss %xmm1, (%rdi)
leaq 80(%rsp), %rbx
movq %rax, (%rbx)
movq %rcx, 8(%rbx)
movq %rsi, 16(%rbx)
movq %rdx, 24(%rbx)
movq %rdi, 32(%rbx)
leaq 64(%rsp), %r14
leaq 48(%rsp), %r15
leaq 16(%rsp), %r12
leaq 8(%rsp), %r13
movq %r14, %rdi
movq %r15, %rsi
movq %r12, %rdx
movq %r13, %rcx
callq __hipPopCallConfiguration
movq (%r14), %rsi
movl 8(%r14), %edx
movq (%r15), %rcx
movl 8(%r15), %r8d
movl $_Z19divergenceReductionPfS_S_ff, %edi
movq %rbx, %r9
pushq (%r13)
.cfi_adjust_cfa_offset 8
pushq (%r12)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $144, %rsp
.cfi_adjust_cfa_offset -144
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z34__device_stub__divergenceReductionPfS_S_ff, .Lfunc_end0-_Z34__device_stub__divergenceReductionPfS_S_ff
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI1_0:
.long 0x3f800000 # float 1
.text
.globl main
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $32, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
xorl %r12d, %r12d
xorl %edi, %edi
callq hipSetDevice
movl $65536, %edi # imm = 0x10000
callq _Znam
movq %rax, %rbx
movl $65536, %edi # imm = 0x10000
callq _Znam
movq %rax, %r14
movl $65536, %edi # imm = 0x10000
callq _Znam
movq %rax, %r15
leaq 24(%rsp), %rdi
movl $65536, %esi # imm = 0x10000
callq hipMalloc
leaq 16(%rsp), %rdi
movl $65536, %esi # imm = 0x10000
callq hipMalloc
leaq 8(%rsp), %rdi
movl $65536, %esi # imm = 0x10000
callq hipMalloc
movl $1065353216, %eax # imm = 0x3F800000
.LBB1_1: # =>This Inner Loop Header: Depth=1
movl %eax, (%rbx,%r12,4)
movl %eax, (%r14,%r12,4)
incq %r12
cmpq $16384, %r12 # imm = 0x4000
jne .LBB1_1
# %bb.2:
movq 24(%rsp), %rdi
movl $65536, %edx # imm = 0x10000
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
movl $65536, %edx # imm = 0x10000
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $4294967360, %rdi # imm = 0x100000040
leaq 192(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq 24(%rsp), %rdi
movq 16(%rsp), %rsi
movq 8(%rsp), %rdx
movss .LCPI1_0(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero
movaps %xmm0, %xmm1
callq _Z34__device_stub__divergenceReductionPfS_S_ff
.LBB1_4:
callq hipGetLastError
testl %eax, %eax
je .LBB1_9
# %bb.5:
movl %eax, %ebp
movl $_ZSt4cerr, %edi
movl $.L.str, %esi
movl $12, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl %ebp, %edi
callq hipGetErrorString
testq %rax, %rax
je .LBB1_6
# %bb.7:
movq %rax, %rbx
movq %rax, %rdi
callq strlen
movl $_ZSt4cerr, %edi
movq %rbx, %rsi
movq %rax, %rdx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
jmp .LBB1_8
.LBB1_9:
movq 8(%rsp), %rsi
movl $65536, %edx # imm = 0x10000
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq %rbx, %rdi
callq _ZdaPv
movq %r14, %rdi
callq _ZdaPv
movq %r15, %rdi
callq _ZdaPv
xorl %eax, %eax
jmp .LBB1_10
.LBB1_6:
movq _ZSt4cerr(%rip), %rax
movq -24(%rax), %rax
leaq _ZSt4cerr(%rax), %rdi
movl 32(%rdi), %esi
orl $1, %esi
callq _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate
.LBB1_8: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit
movq _ZSt4cerr(%rip), %rax
movl $_ZSt4cerr, %ecx
movq -24(%rax), %rdi
addq %rcx, %rdi
movl $10, %esi
callq _ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
movsbl %al, %esi
movl $_ZSt4cerr, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $-1, %eax
.LBB1_10:
addq $32, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, %rdi
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z19divergenceReductionPfS_S_ff, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z19divergenceReductionPfS_S_ff,@object # @_Z19divergenceReductionPfS_S_ff
.section .rodata,"a",@progbits
.globl _Z19divergenceReductionPfS_S_ff
.p2align 3, 0x0
_Z19divergenceReductionPfS_S_ff:
.quad _Z34__device_stub__divergenceReductionPfS_S_ff
.size _Z19divergenceReductionPfS_S_ff, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "CUDA error: "
.size .L.str, 13
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z19divergenceReductionPfS_S_ff"
.size .L__unnamed_1, 32
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z34__device_stub__divergenceReductionPfS_S_ff
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z19divergenceReductionPfS_S_ff
.addrsig_sym _ZSt4cerr
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
```
| 5,463 | 4,200 |
113,654 |
Convert the following CUDA device assembly code to AMD device assembly:
```cudaasm
code for sm_80
Function : _Z24homomorphicEncryptKernelPKfPfif
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
MOV R1, c[0x0][0x28] ;
S2R R4, SR_CTAID.X ;
S2R R3, SR_TID.X ;
IMAD R4, R4, c[0x0][0x0], R3 ;
ISETP.GE.AND P0, PT, R4, c[0x0][0x170], PT ;
@P0 EXIT ;
HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ;
ULDC.64 UR4, c[0x0][0x118] ;
IMAD.WIDE R2, R4, R5, c[0x0][0x160] ;
LDG.E R2, [R2.64] ;
IMAD.WIDE R4, R4, R5, c[0x0][0x168] ;
FADD R7, R2, c[0x0][0x174] ;
STG.E [R4.64], R7 ;
EXIT ;
BRA 0xe0;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
```
|
```amdasm
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z24homomorphicEncryptKernelPKfPfif ; -- Begin function _Z24homomorphicEncryptKernelPKfPfif
.globl _Z24homomorphicEncryptKernelPKfPfif
.p2align 8
.type _Z24homomorphicEncryptKernelPKfPfif,@function
_Z24homomorphicEncryptKernelPKfPfif: ; @_Z24homomorphicEncryptKernelPKfPfif
; %bb.0:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x24
s_load_b64 s[2:3], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
v_cmp_gt_i32_e32 vcc_lo, s2, v1
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_2
; %bb.1:
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
global_load_b32 v2, v[2:3], off
s_waitcnt vmcnt(0)
v_add_f32_e32 v2, s3, v2
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z24homomorphicEncryptKernelPKfPfif
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z24homomorphicEncryptKernelPKfPfif, .Lfunc_end0-_Z24homomorphicEncryptKernelPKfPfif
; -- End function
.section .AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 148
; NumSgprs: 18
; NumVgprs: 4
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 4
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object ; @__hip_cuid_
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0 ; 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z24homomorphicEncryptKernelPKfPfif
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z24homomorphicEncryptKernelPKfPfif.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
```
| 356 | 2,526 |
113,655 |
Convert the following CUDA host assembly code to AMD host assembly:
```cudaasm
.file "tmpxft_000c0f27_00000000-6_cuda_code_025101.cudafe1.cpp"
.text
.globl _ZSt21ios_base_library_initv
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3638:
.cfi_startproc
endbr64
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
jmp __cudaUnregisterFatBinary@PLT
.cfi_endproc
.LFE3638:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.align 2
.type _ZNSolsEPFRSoS_E.isra.0, @function
_ZNSolsEPFRSoS_E.isra.0:
.LFB4292:
.cfi_startproc
jmp *%rsi
.cfi_endproc
.LFE4292:
.size _ZNSolsEPFRSoS_E.isra.0, .-_ZNSolsEPFRSoS_E.isra.0
.globl _Z49__device_stub__Z24homomorphicEncryptKernelPKfPfifPKfPfif
.type _Z49__device_stub__Z24homomorphicEncryptKernelPKfPfifPKfPfif, @function
_Z49__device_stub__Z24homomorphicEncryptKernelPKfPfifPKfPfif:
.LFB3660:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
leaq 48(%rsp), %rcx
leaq 56(%rsp), %rdi
movq %rsi, 16(%rsp)
leaq 68(%rsp), %rsi
movl %edx, 12(%rsp)
leaq 40(%rsp), %rdx
movss %xmm0, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movl $1, 64(%rsp)
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 12(%rsp), %rax
movq %rax, 120(%rsp)
leaq 8(%rsp), %rax
movq %rax, 128(%rsp)
movabsq $4294967297, %rax
movq %rax, 56(%rsp)
movq %rax, 68(%rsp)
movl $1, 76(%rsp)
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
jne .L3
pushq 48(%rsp)
.cfi_def_cfa_offset 168
leaq _Z24homomorphicEncryptKernelPKfPfif(%rip), %rdi
pushq 48(%rsp)
.cfi_def_cfa_offset 176
movq 84(%rsp), %rcx
movl 92(%rsp), %r8d
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
leaq 120(%rsp), %r9
call cudaLaunchKernel@PLT
popq %rax
.cfi_def_cfa_offset 168
popq %rdx
.cfi_def_cfa_offset 160
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
je .L5
call __stack_chk_fail@PLT
.L5:
addq $152, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3660:
.size _Z49__device_stub__Z24homomorphicEncryptKernelPKfPfifPKfPfif, .-_Z49__device_stub__Z24homomorphicEncryptKernelPKfPfifPKfPfif
.globl _Z24homomorphicEncryptKernelPKfPfif
.type _Z24homomorphicEncryptKernelPKfPfif, @function
_Z24homomorphicEncryptKernelPKfPfif:
.LFB3661:
.cfi_startproc
endbr64
jmp _Z49__device_stub__Z24homomorphicEncryptKernelPKfPfifPKfPfif
.cfi_endproc
.LFE3661:
.size _Z24homomorphicEncryptKernelPKfPfif, .-_Z24homomorphicEncryptKernelPKfPfif
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Failed to allocate device memory for input (error code "
.LC1:
.string ")"
.LC2:
.string "Failed to allocate device memory for output (error code "
.LC3:
.string "Failed to copy input data from host to device (error code "
.LC5:
.string "Failed to launch homomorphicEncryptKernel (error code "
.LC6:
.string "Failed to copy output data from device to host (error code "
.LC7:
.string "Homomorphic encryption test passed!"
.LC8:
.string "Homomorphic encryption test failed!"
.section .text.startup,"ax",@progbits
.globl main
.type main, @function
main:
.LFB3635:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
movl $4096, %edi
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $48, %rsp
.cfi_def_cfa_offset 80
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
call _Znam@PLT
movl $4096, %edi
movq %rax, %rbx
call _Znam@PLT
movq %rax, %rbp
xorl %eax, %eax
.L10:
cvtsi2ssl %eax, %xmm0
movss %xmm0, (%rbx,%rax,4)
incq %rax
cmpq $1024, %rax
jne .L10
movq %rsp, %rdi
movl $4096, %esi
call cudaMalloc@PLT
movl %eax, %r12d
testl %eax, %eax
je .L11
leaq .LC0(%rip), %rsi
leaq _ZSt4cerr(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movl %r12d, %esi
movq %rax, %rdi
call _ZNSolsEi@PLT
leaq .LC1(%rip), %rsi
movq %rax, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@GOTPCREL(%rip), %rsi
movq %rax, %rdi
call _ZNSolsEPFRSoS_E.isra.0
jmp .L12
.L11:
leaq 8(%rsp), %rdi
movl $4096, %esi
call cudaMalloc@PLT
movl %eax, %r12d
testl %eax, %eax
je .L13
leaq .LC2(%rip), %rsi
leaq _ZSt4cerr(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movl %r12d, %esi
movq %rax, %rdi
call _ZNSolsEi@PLT
leaq .LC1(%rip), %rsi
movq %rax, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@GOTPCREL(%rip), %rsi
movq %rax, %rdi
call _ZNSolsEPFRSoS_E.isra.0
movq (%rsp), %rdi
.L30:
call cudaFree@PLT
.L12:
orl $-1, %eax
jmp .L9
.L13:
movq (%rsp), %rdi
movq %rbx, %rsi
movl $1, %ecx
movl $4096, %edx
call cudaMemcpy@PLT
leaq .LC3(%rip), %rsi
movl %eax, %r12d
testl %eax, %eax
jne .L32
movl $16777217, %edx
movl $1073741825, %edi
xorl %r9d, %r9d
xorl %r8d, %r8d
salq $8, %rdx
salq $2, %rdi
movl $1, %ecx
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L16
movq 8(%rsp), %rsi
movq (%rsp), %rdi
movl $1024, %edx
movss .LC4(%rip), %xmm0
call _Z49__device_stub__Z24homomorphicEncryptKernelPKfPfifPKfPfif
.L16:
call cudaGetLastError@PLT
leaq .LC5(%rip), %rsi
movl %eax, %r12d
testl %eax, %eax
jne .L32
movq 8(%rsp), %rsi
movl $2, %ecx
movl $4096, %edx
movq %rbp, %rdi
call cudaMemcpy@PLT
movl %eax, %r12d
testl %eax, %eax
je .L18
leaq .LC6(%rip), %rsi
.L32:
leaq _ZSt4cerr(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movl %r12d, %esi
movq %rax, %rdi
call _ZNSolsEi@PLT
leaq .LC1(%rip), %rsi
movq %rax, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@GOTPCREL(%rip), %rsi
movq %rax, %rdi
call _ZNSolsEPFRSoS_E.isra.0
movq (%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
jmp .L30
.L18:
movq (%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movss .LC4(%rip), %xmm0
xorl %eax, %eax
.L21:
movss (%rbx,%rax), %xmm1
addss %xmm0, %xmm1
ucomiss 0(%rbp,%rax), %xmm1
jp .L19
jne .L19
addq $4, %rax
cmpq $4096, %rax
jne .L21
leaq .LC7(%rip), %rsi
jmp .L31
.L19:
leaq .LC8(%rip), %rsi
.L31:
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@GOTPCREL(%rip), %rsi
movq %rax, %rdi
call _ZNSolsEPFRSoS_E.isra.0
movq %rbx, %rdi
call _ZdaPv@PLT
movq %rbp, %rdi
call _ZdaPv@PLT
xorl %eax, %eax
.L9:
movq 40(%rsp), %rdx
subq %fs:40, %rdx
je .L24
call __stack_chk_fail@PLT
.L24:
addq $48, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3635:
.size main, .-main
.section .rodata.str1.1
.LC9:
.string "_Z24homomorphicEncryptKernelPKfPfif"
.section .text.startup
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3663:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
pushq $0
.cfi_def_cfa_offset 24
xorl %r9d, %r9d
orl $-1, %r8d
pushq $0
.cfi_def_cfa_offset 32
leaq .LC9(%rip), %rdx
movq %rax, %rdi
leaq _Z24homomorphicEncryptKernelPKfPfif(%rip), %rsi
pushq $0
.cfi_def_cfa_offset 40
movq %rdx, %rcx
pushq $0
.cfi_def_cfa_offset 48
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFunction@PLT
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
addq $32, %rsp
.cfi_def_cfa_offset 16
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
popq %rdx
.cfi_def_cfa_offset 8
jmp atexit@PLT
.cfi_endproc
.LFE3663:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC4:
.long 1078523331
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
```
|
```amdasm
.text
.file "cuda_code_025101.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z39__device_stub__homomorphicEncryptKernelPKfPfif # -- Begin function _Z39__device_stub__homomorphicEncryptKernelPKfPfif
.type _Z39__device_stub__homomorphicEncryptKernelPKfPfif,@function
_Z39__device_stub__homomorphicEncryptKernelPKfPfif: # @_Z39__device_stub__homomorphicEncryptKernelPKfPfif
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $112, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 40(%rsp), %rax
movq %rdi, (%rax)
leaq 32(%rsp), %rcx
movq %rsi, (%rcx)
leaq 12(%rsp), %rsi
movl %edx, (%rsi)
leaq 8(%rsp), %rdx
movss %xmm0, (%rdx)
leaq 80(%rsp), %rbx
movq %rax, (%rbx)
movq %rcx, 8(%rbx)
movq %rsi, 16(%rbx)
movq %rdx, 24(%rbx)
leaq 64(%rsp), %r14
leaq 48(%rsp), %r15
leaq 24(%rsp), %r12
leaq 16(%rsp), %r13
movq %r14, %rdi
movq %r15, %rsi
movq %r12, %rdx
movq %r13, %rcx
callq __hipPopCallConfiguration
movq (%r14), %rsi
movl 8(%r14), %edx
movq (%r15), %rcx
movl 8(%r15), %r8d
movl $_Z24homomorphicEncryptKernelPKfPfif, %edi
movq %rbx, %r9
pushq (%r13)
.cfi_adjust_cfa_offset 8
pushq (%r12)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $128, %rsp
.cfi_adjust_cfa_offset -128
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z39__device_stub__homomorphicEncryptKernelPKfPfif, .Lfunc_end0-_Z39__device_stub__homomorphicEncryptKernelPKfPfif
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI1_0:
.long 0x4048f5c3 # float 3.1400001
.text
.globl main
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $16, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %rbp, -16
movl $4096, %edi # imm = 0x1000
callq _Znam
movq %rax, %rbx
movl $4096, %edi # imm = 0x1000
callq _Znam
movq %rax, %r14
xorl %eax, %eax
.LBB1_1: # =>This Inner Loop Header: Depth=1
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movss %xmm0, (%rbx,%rax,4)
incq %rax
cmpq $1024, %rax # imm = 0x400
jne .LBB1_1
# %bb.2:
movq %rsp, %rdi
movl $4096, %esi # imm = 0x1000
callq hipMalloc
testl %eax, %eax
je .LBB1_4
# %bb.3:
movl %eax, %ebp
movl $_ZSt4cerr, %edi
movl $.L.str, %esi
movl $55, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cerr, %edi
movl %ebp, %esi
callq _ZNSolsEi
movq %rax, %rbx
movl $.L.str.1, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq (%rbx), %rax
movq -24(%rax), %rdi
addq %rbx, %rdi
movl $10, %esi
callq _ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
movsbl %al, %esi
movq %rbx, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
jmp .LBB1_15
.LBB1_4:
leaq 8(%rsp), %rdi
movl $4096, %esi # imm = 0x1000
callq hipMalloc
testl %eax, %eax
je .LBB1_6
# %bb.5:
movl %eax, %ebp
movl $_ZSt4cerr, %edi
movl $.L.str.2, %esi
movl $56, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cerr, %edi
movl %ebp, %esi
callq _ZNSolsEi
movq %rax, %rbx
movl $.L.str.1, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq (%rbx), %rax
movq -24(%rax), %rdi
addq %rbx, %rdi
movl $10, %esi
callq _ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
movsbl %al, %esi
movq %rbx, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq (%rsp), %rdi
jmp .LBB1_14
.LBB1_6:
movq (%rsp), %rdi
movl $4096, %edx # imm = 0x1000
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
je .LBB1_8
# %bb.7:
movl %eax, %ebp
movl $_ZSt4cerr, %edi
movl $.L.str.3, %esi
movl $58, %edx
jmp .LBB1_12
.LBB1_8:
movabsq $4294967300, %rdi # imm = 0x100000004
leaq 252(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_10
# %bb.9:
movq (%rsp), %rdi
movq 8(%rsp), %rsi
movss .LCPI1_0(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero
movl $1024, %edx # imm = 0x400
callq _Z39__device_stub__homomorphicEncryptKernelPKfPfif
.LBB1_10:
callq hipGetLastError
testl %eax, %eax
je .LBB1_17
# %bb.11:
movl %eax, %ebp
movl $_ZSt4cerr, %edi
movl $.L.str.4, %esi
movl $54, %edx
.LBB1_12:
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cerr, %edi
movl %ebp, %esi
callq _ZNSolsEi
movq %rax, %rbx
movl $.L.str.1, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq (%rbx), %rax
movq -24(%rax), %rdi
addq %rbx, %rdi
movl $10, %esi
callq _ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
movsbl %al, %esi
movq %rbx, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
.LBB1_13:
movq (%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
.LBB1_14:
callq hipFree
.LBB1_15:
movl $-1, %eax
.LBB1_16:
addq $16, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB1_17:
.cfi_def_cfa_offset 48
movq 8(%rsp), %rsi
movl $4096, %edx # imm = 0x1000
movq %r14, %rdi
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
je .LBB1_19
# %bb.18:
movl %eax, %ebp
movl $_ZSt4cerr, %edi
movl $.L.str.5, %esi
movl $59, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cerr, %edi
movl %ebp, %esi
callq _ZNSolsEi
movq %rax, %rbx
movl $.L.str.1, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq %rbx, %rdi
callq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_
jmp .LBB1_13
.LBB1_19:
movq (%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
xorl %eax, %eax
movss .LCPI1_0(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero
.LBB1_20: # =>This Inner Loop Header: Depth=1
movss (%r14,%rax,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
movss (%rbx,%rax,4), %xmm2 # xmm2 = mem[0],zero,zero,zero
addss %xmm0, %xmm2
ucomiss %xmm2, %xmm1
jne .LBB1_23
jp .LBB1_23
# %bb.21: # in Loop: Header=BB1_20 Depth=1
incq %rax
cmpq $1024, %rax # imm = 0x400
jne .LBB1_20
# %bb.22:
movl $.L.str.6, %esi
jmp .LBB1_24
.LBB1_23:
movl $.L.str.7, %esi
.LBB1_24: # %.critedge
movl $_ZSt4cout, %edi
movl $35, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
callq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_
movq %rbx, %rdi
callq _ZdaPv
movq %r14, %rdi
callq _ZdaPv
xorl %eax, %eax
jmp .LBB1_16
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, %rdi
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z24homomorphicEncryptKernelPKfPfif, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z24homomorphicEncryptKernelPKfPfif,@object # @_Z24homomorphicEncryptKernelPKfPfif
.section .rodata,"a",@progbits
.globl _Z24homomorphicEncryptKernelPKfPfif
.p2align 3, 0x0
_Z24homomorphicEncryptKernelPKfPfif:
.quad _Z39__device_stub__homomorphicEncryptKernelPKfPfif
.size _Z24homomorphicEncryptKernelPKfPfif, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Failed to allocate device memory for input (error code "
.size .L.str, 56
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz ")"
.size .L.str.1, 2
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Failed to allocate device memory for output (error code "
.size .L.str.2, 57
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Failed to copy input data from host to device (error code "
.size .L.str.3, 59
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Failed to launch homomorphicEncryptKernel (error code "
.size .L.str.4, 55
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "Failed to copy output data from device to host (error code "
.size .L.str.5, 60
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "Homomorphic encryption test passed!"
.size .L.str.6, 36
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "Homomorphic encryption test failed!"
.size .L.str.7, 36
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z24homomorphicEncryptKernelPKfPfif"
.size .L__unnamed_1, 36
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z39__device_stub__homomorphicEncryptKernelPKfPfif
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z24homomorphicEncryptKernelPKfPfif
.addrsig_sym _ZSt4cerr
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
```
| 4,265 | 5,472 |
113,656 |
Convert the following CUDA device assembly code to AMD device assembly:
```cudaasm
code for sm_80
Function : _Z15bitonicSortWarpPf
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ;
S2R R0, SR_TID.X ;
IMAD.MOV.U32 R3, RZ, RZ, 0x4 ;
ULDC.64 UR4, c[0x0][0x118] ;
IMAD.WIDE R2, R0, R3, c[0x0][0x160] ;
LDG.E R5, [R2.64] ;
LOP3.LUT R7, R0.reuse, 0x1, RZ, 0x3c, !PT ;
BSSY B0, 0x1b0 ;
ISETP.GT.U32.AND P0, PT, R7, R0, PT ;
IMAD.SHL.U32 R7, R0, 0x4, RZ ;
LOP3.LUT R4, R7, 0x4, RZ, 0x3c, !PT ;
STS [R0.X4], R5 ;
BAR.SYNC.DEFER_BLOCKING 0x0 ;
@!P0 BRA 0x1a0 ;
LDS R5, [R0.X4] ;
LOP3.LUT P1, RZ, R0, 0x2, RZ, 0xc0, !PT ;
LDS R6, [R4] ;
@!P1 BRA 0x170 ;
FSETP.GEU.AND P1, PT, R5, R6, PT ;
@P1 BRA 0x1a0 ;
STS [R0.X4], R6 ;
STS [R4], R5 ;
BRA 0x1a0 ;
FSETP.GT.AND P1, PT, R5, R6, PT ;
@P1 STS [R0.X4], R6 ;
@P1 STS [R4], R5 ;
BSYNC B0 ;
LOP3.LUT R5, R0.reuse, 0x2, RZ, 0x3c, !PT ;
BAR.SYNC.DEFER_BLOCKING 0x0 ;
LOP3.LUT R8, R0, 0x4, RZ, 0xc0, !PT ;
ISETP.GT.U32.AND P1, PT, R5, R0, PT ;
LOP3.LUT R5, R7, 0x8, RZ, 0x3c, !PT ;
BSSY B0, 0x2f0 ;
@!P1 BRA 0x2e0 ;
LDS R6, [R0.X4] ;
ISETP.NE.AND P2, PT, R8, RZ, PT ;
LDS R9, [R5] ;
@!P2 BRA 0x2b0 ;
FSETP.GEU.AND P2, PT, R6, R9, PT ;
@P2 BRA 0x2e0 ;
STS [R0.X4], R9 ;
STS [R5], R6 ;
BRA 0x2e0 ;
FSETP.GT.AND P2, PT, R6, R9, PT ;
@P2 STS [R0.X4], R9 ;
@P2 STS [R5], R6 ;
BSYNC B0 ;
BAR.SYNC.DEFER_BLOCKING 0x0 ;
BSSY B0, 0x3f0 ;
@!P0 BRA 0x3e0 ;
LDS R9, [R0.X4] ;
ISETP.NE.AND P2, PT, R8, RZ, PT ;
LDS R6, [R4] ;
@!P2 BRA 0x3b0 ;
FSETP.GEU.AND P2, PT, R9, R6, PT ;
@P2 BRA 0x3e0 ;
STS [R0.X4], R6 ;
STS [R4], R9 ;
BRA 0x3e0 ;
FSETP.GT.AND P2, PT, R9, R6, PT ;
@P2 STS [R0.X4], R6 ;
@P2 STS [R4], R9 ;
BSYNC B0 ;
LOP3.LUT R9, R0.reuse, 0x4, RZ, 0x3c, !PT ;
BAR.SYNC.DEFER_BLOCKING 0x0 ;
LOP3.LUT R10, R0, 0x8, RZ, 0xc0, !PT ;
ISETP.GT.U32.AND P2, PT, R9, R0, PT ;
LOP3.LUT R6, R7, 0x10, RZ, 0x3c, !PT ;
BSSY B0, 0x530 ;
@!P2 BRA 0x520 ;
LDS R9, [R0.X4] ;
ISETP.NE.AND P3, PT, R10, RZ, PT ;
LDS R8, [R6] ;
@!P3 BRA 0x4f0 ;
FSETP.GEU.AND P3, PT, R9, R8, PT ;
@P3 BRA 0x520 ;
STS [R0.X4], R8 ;
STS [R6], R9 ;
BRA 0x520 ;
FSETP.GT.AND P3, PT, R9, R8, PT ;
@P3 STS [R0.X4], R8 ;
@P3 STS [R6], R9 ;
BSYNC B0 ;
BAR.SYNC.DEFER_BLOCKING 0x0 ;
BSSY B0, 0x630 ;
@!P1 BRA 0x620 ;
LDS R8, [R0.X4] ;
ISETP.NE.AND P3, PT, R10, RZ, PT ;
LDS R9, [R5] ;
@!P3 BRA 0x5f0 ;
FSETP.GEU.AND P3, PT, R8, R9, PT ;
@P3 BRA 0x620 ;
STS [R0.X4], R9 ;
STS [R5], R8 ;
BRA 0x620 ;
FSETP.GT.AND P3, PT, R8, R9, PT ;
@P3 STS [R0.X4], R9 ;
@P3 STS [R5], R8 ;
BSYNC B0 ;
BAR.SYNC.DEFER_BLOCKING 0x0 ;
BSSY B0, 0x730 ;
@!P0 BRA 0x720 ;
LDS R9, [R0.X4] ;
ISETP.NE.AND P3, PT, R10, RZ, PT ;
LDS R8, [R4] ;
@!P3 BRA 0x6f0 ;
FSETP.GEU.AND P3, PT, R9, R8, PT ;
@P3 BRA 0x720 ;
STS [R0.X4], R8 ;
STS [R4], R9 ;
BRA 0x720 ;
FSETP.GT.AND P3, PT, R9, R8, PT ;
@P3 STS [R0.X4], R8 ;
@P3 STS [R4], R9 ;
BSYNC B0 ;
LOP3.LUT R9, R0.reuse, 0x8, RZ, 0x3c, !PT ;
BAR.SYNC.DEFER_BLOCKING 0x0 ;
LOP3.LUT R7, R7, 0x20, RZ, 0x3c, !PT ;
ISETP.GT.U32.AND P3, PT, R9, R0, PT ;
LOP3.LUT R10, R0, 0x10, RZ, 0xc0, !PT ;
BSSY B0, 0x870 ;
@!P3 BRA 0x860 ;
LDS R8, [R0.X4] ;
ISETP.NE.AND P4, PT, R10, RZ, PT ;
LDS R9, [R7] ;
@!P4 BRA 0x830 ;
FSETP.GEU.AND P4, PT, R8, R9, PT ;
@P4 BRA 0x860 ;
STS [R0.X4], R9 ;
STS [R7], R8 ;
BRA 0x860 ;
FSETP.GT.AND P4, PT, R8, R9, PT ;
@P4 STS [R0.X4], R9 ;
@P4 STS [R7], R8 ;
BSYNC B0 ;
BAR.SYNC.DEFER_BLOCKING 0x0 ;
BSSY B0, 0x970 ;
@!P2 BRA 0x960 ;
LDS R9, [R0.X4] ;
ISETP.NE.AND P4, PT, R10, RZ, PT ;
LDS R8, [R6] ;
@!P4 BRA 0x930 ;
FSETP.GEU.AND P4, PT, R9, R8, PT ;
@P4 BRA 0x960 ;
STS [R0.X4], R8 ;
STS [R6], R9 ;
BRA 0x960 ;
FSETP.GT.AND P4, PT, R9, R8, PT ;
@P4 STS [R0.X4], R8 ;
@P4 STS [R6], R9 ;
BSYNC B0 ;
BAR.SYNC.DEFER_BLOCKING 0x0 ;
BSSY B0, 0xa70 ;
@!P1 BRA 0xa60 ;
LDS R8, [R0.X4] ;
ISETP.NE.AND P4, PT, R10, RZ, PT ;
LDS R9, [R5] ;
@!P4 BRA 0xa30 ;
FSETP.GEU.AND P4, PT, R8, R9, PT ;
@P4 BRA 0xa60 ;
STS [R0.X4], R9 ;
STS [R5], R8 ;
BRA 0xa60 ;
FSETP.GT.AND P4, PT, R8, R9, PT ;
@P4 STS [R0.X4], R9 ;
@P4 STS [R5], R8 ;
BSYNC B0 ;
BAR.SYNC.DEFER_BLOCKING 0x0 ;
BSSY B0, 0xb70 ;
@!P0 BRA 0xb60 ;
LDS R9, [R0.X4] ;
ISETP.NE.AND P4, PT, R10, RZ, PT ;
LDS R8, [R4] ;
@!P4 BRA 0xb30 ;
FSETP.GEU.AND P4, PT, R9, R8, PT ;
@P4 BRA 0xb60 ;
STS [R0.X4], R8 ;
STS [R4], R9 ;
BRA 0xb60 ;
FSETP.GT.AND P4, PT, R9, R8, PT ;
@P4 STS [R0.X4], R8 ;
@P4 STS [R4], R9 ;
BSYNC B0 ;
LOP3.LUT R9, R0.reuse, 0x10, RZ, 0x3c, !PT ;
BAR.SYNC.DEFER_BLOCKING 0x0 ;
LOP3.LUT R10, R0, 0x20, RZ, 0xc0, !PT ;
ISETP.GT.U32.AND P4, PT, R9, R0, PT ;
BSSY B0, 0xca0 ;
@!P4 BRA 0xc90 ;
LDS R8, [R0.X4] ;
ISETP.NE.AND P4, PT, R10, RZ, PT ;
LDS R11, [R9.X4] ;
@!P4 BRA 0xc60 ;
FSETP.GEU.AND P4, PT, R8, R11, PT ;
@P4 BRA 0xc90 ;
STS [R0.X4], R11 ;
STS [R9.X4], R8 ;
BRA 0xc90 ;
FSETP.GT.AND P4, PT, R8, R11, PT ;
@P4 STS [R0.X4], R11 ;
@P4 STS [R9.X4], R8 ;
BSYNC B0 ;
BAR.SYNC.DEFER_BLOCKING 0x0 ;
BSSY B0, 0xda0 ;
@!P3 BRA 0xd90 ;
LDS R8, [R0.X4] ;
ISETP.NE.AND P3, PT, R10, RZ, PT ;
LDS R9, [R7] ;
@!P3 BRA 0xd60 ;
FSETP.GEU.AND P3, PT, R8, R9, PT ;
@P3 BRA 0xd90 ;
STS [R0.X4], R9 ;
STS [R7], R8 ;
BRA 0xd90 ;
FSETP.GT.AND P3, PT, R8, R9, PT ;
@P3 STS [R0.X4], R9 ;
@P3 STS [R7], R8 ;
BSYNC B0 ;
BAR.SYNC.DEFER_BLOCKING 0x0 ;
BSSY B0, 0xea0 ;
@!P2 BRA 0xe90 ;
LDS R7, [R0.X4] ;
ISETP.NE.AND P2, PT, R10, RZ, PT ;
LDS R8, [R6] ;
@!P2 BRA 0xe60 ;
FSETP.GEU.AND P2, PT, R7, R8, PT ;
@P2 BRA 0xe90 ;
STS [R0.X4], R8 ;
STS [R6], R7 ;
BRA 0xe90 ;
FSETP.GT.AND P2, PT, R7, R8, PT ;
@P2 STS [R0.X4], R8 ;
@P2 STS [R6], R7 ;
BSYNC B0 ;
BAR.SYNC.DEFER_BLOCKING 0x0 ;
BSSY B0, 0xfa0 ;
@!P1 BRA 0xf90 ;
LDS R6, [R0.X4] ;
ISETP.NE.AND P1, PT, R10, RZ, PT ;
LDS R7, [R5] ;
@!P1 BRA 0xf60 ;
FSETP.GEU.AND P1, PT, R6, R7, PT ;
@P1 BRA 0xf90 ;
STS [R0.X4], R7 ;
STS [R5], R6 ;
BRA 0xf90 ;
FSETP.GT.AND P1, PT, R6, R7, PT ;
@P1 STS [R0.X4], R7 ;
@P1 STS [R5], R6 ;
BSYNC B0 ;
BAR.SYNC.DEFER_BLOCKING 0x0 ;
BSSY B0, 0x10a0 ;
@!P0 BRA 0x1090 ;
LDS R5, [R0.X4] ;
ISETP.NE.AND P0, PT, R10, RZ, PT ;
LDS R6, [R4] ;
@!P0 BRA 0x1060 ;
FSETP.GEU.AND P0, PT, R5, R6, PT ;
@P0 BRA 0x1090 ;
STS [R0.X4], R6 ;
STS [R4], R5 ;
BRA 0x1090 ;
FSETP.GT.AND P0, PT, R5, R6, PT ;
@P0 STS [R0.X4], R6 ;
@P0 STS [R4], R5 ;
BSYNC B0 ;
BAR.SYNC.DEFER_BLOCKING 0x0 ;
LDS R5, [R0.X4] ;
STG.E [R2.64], R5 ;
EXIT ;
BRA 0x10e0;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
```
|
```amdasm
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z15bitonicSortWarpPf ; -- Begin function _Z15bitonicSortWarpPf
.globl _Z15bitonicSortWarpPf
.p2align 8
.type _Z15bitonicSortWarpPf,@function
_Z15bitonicSortWarpPf: ; @_Z15bitonicSortWarpPf
; %bb.0:
s_load_b64 s[2:3], s[0:1], 0x0
v_lshlrev_b32_e32 v1, 2, v0
s_mov_b32 s1, 2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v3, 0, v1
s_waitcnt lgkmcnt(0)
global_load_b32 v4, v1, s[2:3]
v_add_co_u32 v1, s0, s2, v1
v_add_co_ci_u32_e64 v2, null, s3, 0, s0
s_waitcnt vmcnt(0)
ds_store_b32 v3, v4
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
.LBB0_1: ; %.preheader
; =>This Loop Header: Depth=1
; Child Loop BB0_2 Depth 2
v_and_b32_e32 v4, s1, v0
s_mov_b32 s2, s1
s_delay_alu instid0(VALU_DEP_1)
v_cmp_ne_u32_e32 vcc_lo, 0, v4
.LBB0_2: ; Parent Loop BB0_1 Depth=1
; => This Inner Loop Header: Depth=2
s_mov_b32 s3, s2
s_lshr_b32 s2, s2, 1
s_mov_b32 s4, exec_lo
v_xor_b32_e32 v4, s2, v0
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_u32_e64 v4, v0
s_cbranch_execz .LBB0_9
; %bb.3: ; in Loop: Header=BB0_2 Depth=2
v_lshl_add_u32 v4, v4, 2, 0
s_mov_b32 s5, 0
ds_load_b32 v5, v3
ds_load_b32 v6, v4
s_and_saveexec_b32 s0, vcc_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s6, exec_lo, s0
s_cbranch_execz .LBB0_5
; %bb.4: ; in Loop: Header=BB0_2 Depth=2
s_waitcnt lgkmcnt(0)
v_cmp_lt_f32_e64 s0, v5, v6
s_delay_alu instid0(VALU_DEP_1)
s_and_b32 s5, s0, exec_lo
.LBB0_5: ; %Flow
; in Loop: Header=BB0_2 Depth=2
s_and_not1_saveexec_b32 s6, s6
s_cbranch_execz .LBB0_7
; %bb.6: ; in Loop: Header=BB0_2 Depth=2
s_waitcnt lgkmcnt(0)
v_cmp_gt_f32_e64 s0, v5, v6
s_and_not1_b32 s5, s5, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s0, s0, exec_lo
s_or_b32 s5, s5, s0
.LBB0_7: ; %Flow43
; in Loop: Header=BB0_2 Depth=2
s_or_b32 exec_lo, exec_lo, s6
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 exec_lo, exec_lo, s5
s_cbranch_execz .LBB0_9
; %bb.8: ; %.sink.split
; in Loop: Header=BB0_2 Depth=2
s_waitcnt lgkmcnt(0)
ds_store_b32 v3, v6
ds_store_b32 v4, v5
.LBB0_9: ; in Loop: Header=BB0_2 Depth=2
s_or_b32 exec_lo, exec_lo, s4
s_cmp_lt_u32 s3, 4
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc0 .LBB0_2
; %bb.10: ; %._crit_edge
; in Loop: Header=BB0_1 Depth=1
s_lshl_b32 s0, s1, 1
s_cmp_gt_u32 s1, 16
s_mov_b32 s1, s0
s_cbranch_scc0 .LBB0_1
; %bb.11:
ds_load_b32 v0, v3
s_waitcnt lgkmcnt(0)
global_store_b32 v[1:2], v0, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z15bitonicSortWarpPf
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 8
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 7
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z15bitonicSortWarpPf, .Lfunc_end0-_Z15bitonicSortWarpPf
; -- End function
.section .AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 340
; NumSgprs: 9
; NumVgprs: 7
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 1
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 9
; NumVGPRsForWavesPerEU: 7
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object ; @__hip_cuid_
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0 ; 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 8
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z15bitonicSortWarpPf
.private_segment_fixed_size: 0
.sgpr_count: 9
.sgpr_spill_count: 0
.symbol: _Z15bitonicSortWarpPf.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
```
| 3,769 | 2,739 |
113,657 |
Convert the following CUDA host assembly code to AMD host assembly:
```cudaasm
.file "tmpxft_000bc48f_00000000-6_cuda_code_065443.cudafe1.cpp"
.text
.globl _ZSt21ios_base_library_initv
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3638:
.cfi_startproc
endbr64
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
jmp __cudaUnregisterFatBinary@PLT
.cfi_endproc
.LFE3638:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.align 2
.type _ZNSolsEPFRSoS_E.isra.0, @function
_ZNSolsEPFRSoS_E.isra.0:
.LFB4293:
.cfi_startproc
jmp *%rsi
.cfi_endproc
.LFE4293:
.size _ZNSolsEPFRSoS_E.isra.0, .-_ZNSolsEPFRSoS_E.isra.0
.globl _Z35__device_stub__Z15bitonicSortWarpPfPf
.type _Z35__device_stub__Z15bitonicSortWarpPfPf, @function
_Z35__device_stub__Z15bitonicSortWarpPfPf:
.LFB3660:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movl $1, 40(%rsp)
movq %rax, 80(%rsp)
movabsq $4294967297, %rax
movq %rax, 32(%rsp)
movq %rax, 44(%rsp)
movl $1, 52(%rsp)
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
jne .L3
pushq 24(%rsp)
.cfi_def_cfa_offset 120
leaq _Z15bitonicSortWarpPf(%rip), %rdi
pushq 24(%rsp)
.cfi_def_cfa_offset 128
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq 96(%rsp), %r9
call cudaLaunchKernel@PLT
popq %rax
.cfi_def_cfa_offset 120
popq %rdx
.cfi_def_cfa_offset 112
.L3:
movq 88(%rsp), %rax
subq %fs:40, %rax
je .L5
call __stack_chk_fail@PLT
.L5:
addq $104, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3660:
.size _Z35__device_stub__Z15bitonicSortWarpPfPf, .-_Z35__device_stub__Z15bitonicSortWarpPfPf
.globl _Z15bitonicSortWarpPf
.type _Z15bitonicSortWarpPf, @function
_Z15bitonicSortWarpPf:
.LFB3661:
.cfi_startproc
endbr64
jmp _Z35__device_stub__Z15bitonicSortWarpPfPf
.cfi_endproc
.LFE3661:
.size _Z15bitonicSortWarpPf, .-_Z15bitonicSortWarpPf
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "Failed to allocate device memory: "
.LC2:
.string "Failed to copy data to device: "
.LC3:
.string "Kernel launch failed: "
.LC4:
.string "Failed to synchronize: "
.LC5:
.string "Failed to copy data from device: "
.LC6:
.string "Sorted array:"
.LC7:
.string " "
.section .text.startup,"ax",@progbits
.globl main
.type main, @function
main:
.LFB3635:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
xorl %ebx, %ebx
subq $1080, %rsp
.cfi_def_cfa_offset 1120
movq %fs:40, %rax
movq %rax, 1064(%rsp)
xorl %eax, %eax
.L10:
call rand@PLT
leaq 40(%rsp), %rbp
cvtsi2ssl %eax, %xmm0
mulss .LC0(%rip), %xmm0
movss %xmm0, 0(%rbp,%rbx,4)
incq %rbx
cmpq $256, %rbx
jne .L10
leaq 8(%rsp), %rdi
movl $1024, %esi
call cudaMalloc@PLT
movl %eax, %ebx
testl %eax, %eax
je .L11
leaq .LC1(%rip), %rsi
leaq _ZSt4cerr(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movl %ebx, %edi
movq %rax, %rbp
call cudaGetErrorString@PLT
movq %rbp, %rdi
movq %rax, %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@GOTPCREL(%rip), %rsi
movq %rax, %rdi
call _ZNSolsEPFRSoS_E.isra.0
jmp .L12
.L11:
movq 8(%rsp), %rdi
movl $1, %ecx
movl $1024, %edx
movq %rbp, %rsi
call cudaMemcpy@PLT
movl %eax, %ebx
testl %eax, %eax
je .L13
leaq .LC2(%rip), %rsi
.L24:
leaq _ZSt4cerr(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movl %ebx, %edi
movq %rax, %rbp
call cudaGetErrorString@PLT
movq %rbp, %rdi
movq %rax, %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@GOTPCREL(%rip), %rsi
movq %rax, %rdi
call _ZNSolsEPFRSoS_E.isra.0
movq 8(%rsp), %rdi
call cudaFree@PLT
.L12:
orl $-1, %eax
jmp .L9
.L13:
movl $134217729, %edx
xorl %r9d, %r9d
movl $1, %ecx
movabsq $4294967297, %rdi
salq $5, %rdx
movl $128, %r8d
movl $1, %esi
movl $1, 36(%rsp)
movq %rdx, 28(%rsp)
movq %rdi, 16(%rsp)
movl $1, 24(%rsp)
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L15
movq 8(%rsp), %rdi
call _Z35__device_stub__Z15bitonicSortWarpPfPf
.L15:
call cudaGetLastError@PLT
leaq .LC3(%rip), %rsi
movl %eax, %ebx
testl %eax, %eax
jne .L24
call cudaDeviceSynchronize@PLT
leaq .LC4(%rip), %rsi
movl %eax, %ebx
testl %eax, %eax
jne .L24
movq 8(%rsp), %rsi
movl $2, %ecx
movl $1024, %edx
movq %rbp, %rdi
call cudaMemcpy@PLT
leaq .LC5(%rip), %rsi
movl %eax, %ebx
testl %eax, %eax
jne .L24
movq 8(%rsp), %rdi
leaq _ZSt4cout(%rip), %r12
xorl %ebx, %ebx
leaq .LC7(%rip), %r13
call cudaFree@PLT
leaq .LC6(%rip), %rsi
movq %r12, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@GOTPCREL(%rip), %rsi
movq %rax, %rdi
call _ZNSolsEPFRSoS_E.isra.0
.L19:
movq %r12, %rdi
cvtss2sd 0(%rbp,%rbx,4), %xmm0
incq %rbx
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %r13, %rsi
movq %rax, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
cmpq $256, %rbx
jne .L19
movq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@GOTPCREL(%rip), %rsi
movq %r12, %rdi
call _ZNSolsEPFRSoS_E.isra.0
xorl %eax, %eax
.L9:
movq 1064(%rsp), %rdx
subq %fs:40, %rdx
je .L20
call __stack_chk_fail@PLT
.L20:
addq $1080, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3635:
.size main, .-main
.section .rodata.str1.1
.LC8:
.string "_Z15bitonicSortWarpPf"
.section .text.startup
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3663:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
pushq $0
.cfi_def_cfa_offset 24
xorl %r9d, %r9d
orl $-1, %r8d
pushq $0
.cfi_def_cfa_offset 32
leaq .LC8(%rip), %rdx
movq %rax, %rdi
leaq _Z15bitonicSortWarpPf(%rip), %rsi
pushq $0
.cfi_def_cfa_offset 40
movq %rdx, %rcx
pushq $0
.cfi_def_cfa_offset 48
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFunction@PLT
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
addq $32, %rsp
.cfi_def_cfa_offset 16
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
popq %rdx
.cfi_def_cfa_offset 8
jmp atexit@PLT
.cfi_endproc
.LFE3663:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC0:
.long 805306368
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
```
|
```amdasm
.text
.file "cuda_code_065443.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z30__device_stub__bitonicSortWarpPf # -- Begin function _Z30__device_stub__bitonicSortWarpPf
.type _Z30__device_stub__bitonicSortWarpPf,@function
_Z30__device_stub__bitonicSortWarpPf: # @_Z30__device_stub__bitonicSortWarpPf
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $64, %rsp
.cfi_def_cfa_offset 112
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 24(%rsp), %rax
movq %rdi, (%rax)
movq %rsp, %rbx
movq %rax, (%rbx)
leaq 48(%rsp), %r14
leaq 32(%rsp), %r15
leaq 16(%rsp), %r12
leaq 8(%rsp), %r13
movq %r14, %rdi
movq %r15, %rsi
movq %r12, %rdx
movq %r13, %rcx
callq __hipPopCallConfiguration
movq (%r14), %rsi
movl 8(%r14), %edx
movq (%r15), %rcx
movl 8(%r15), %r8d
movl $_Z15bitonicSortWarpPf, %edi
movq %rbx, %r9
pushq (%r13)
.cfi_adjust_cfa_offset 8
pushq (%r12)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $80, %rsp
.cfi_adjust_cfa_offset -80
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z30__device_stub__bitonicSortWarpPf, .Lfunc_end0-_Z30__device_stub__bitonicSortWarpPf
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI1_0:
.long 0x30000000 # float 4.65661287E-10
.text
.globl main
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $1040, %rsp # imm = 0x410
.cfi_def_cfa_offset 1056
.cfi_offset %rbx, -16
xorl %ebx, %ebx
.LBB1_1: # =>This Inner Loop Header: Depth=1
callq rand
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
mulss .LCPI1_0(%rip), %xmm0
movss %xmm0, 16(%rsp,%rbx,4)
incq %rbx
cmpq $256, %rbx # imm = 0x100
jne .LBB1_1
# %bb.2:
leaq 8(%rsp), %rdi
movl $1024, %esi # imm = 0x400
callq hipMalloc
testl %eax, %eax
je .LBB1_5
# %bb.3:
movl %eax, %ebx
movl $_ZSt4cerr, %edi
movl $.L.str, %esi
movl $34, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl %ebx, %edi
callq hipGetErrorString
testq %rax, %rax
je .LBB1_7
# %bb.4:
movq %rax, %rbx
movq %rax, %rdi
callq strlen
movl $_ZSt4cerr, %edi
movq %rbx, %rsi
movq %rax, %rdx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
jmp .LBB1_8
.LBB1_5:
movq 8(%rsp), %rdi
leaq 16(%rsp), %rsi
movl $1024, %edx # imm = 0x400
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
je .LBB1_9
# %bb.6:
movl %eax, %ebx
movl $_ZSt4cerr, %edi
movl $.L.str.1, %esi
movl $31, %edx
jmp .LBB1_15
.LBB1_7:
movq _ZSt4cerr(%rip), %rax
movq -24(%rax), %rax
leaq _ZSt4cerr(%rax), %rdi
movl 32(%rdi), %esi
orl $1, %esi
callq _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate
.LBB1_8: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit
movq _ZSt4cerr(%rip), %rax
movl $_ZSt4cerr, %ecx
movq -24(%rax), %rdi
addq %rcx, %rdi
movl $10, %esi
callq _ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
movsbl %al, %esi
movl $_ZSt4cerr, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
jmp .LBB1_20
.LBB1_9:
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 31(%rdi), %rdx
movl $128, %r8d
movl $1, %esi
movl $1, %ecx
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_11
# %bb.10:
movq 8(%rsp), %rdi
callq _Z30__device_stub__bitonicSortWarpPf
.LBB1_11:
callq hipGetLastError
testl %eax, %eax
je .LBB1_13
# %bb.12:
movl %eax, %ebx
movl $_ZSt4cerr, %edi
movl $.L.str.2, %esi
movl $22, %edx
jmp .LBB1_15
.LBB1_13:
callq hipDeviceSynchronize
testl %eax, %eax
je .LBB1_22
# %bb.14:
movl %eax, %ebx
movl $_ZSt4cerr, %edi
movl $.L.str.3, %esi
movl $23, %edx
.LBB1_15:
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl %ebx, %edi
callq hipGetErrorString
testq %rax, %rax
je .LBB1_17
# %bb.16:
movq %rax, %rbx
movq %rax, %rdi
callq strlen
movl $_ZSt4cerr, %edi
movq %rbx, %rsi
movq %rax, %rdx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
jmp .LBB1_18
.LBB1_17:
movq _ZSt4cerr(%rip), %rax
movq -24(%rax), %rax
leaq _ZSt4cerr(%rax), %rdi
movl 32(%rdi), %esi
orl $1, %esi
callq _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate
.LBB1_18: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit32
movq _ZSt4cerr(%rip), %rax
movl $_ZSt4cerr, %ecx
movq -24(%rax), %rdi
addq %rcx, %rdi
movl $10, %esi
callq _ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
movsbl %al, %esi
movl $_ZSt4cerr, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
.LBB1_19:
movq 8(%rsp), %rdi
callq hipFree
.LBB1_20:
movl $-1, %eax
.LBB1_21:
addq $1040, %rsp # imm = 0x410
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.LBB1_22:
.cfi_def_cfa_offset 1056
movq 8(%rsp), %rsi
leaq 16(%rsp), %rdi
movl $1024, %edx # imm = 0x400
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
je .LBB1_24
# %bb.23:
movl %eax, %ebx
movl $_ZSt4cerr, %edi
movl $.L.str.4, %esi
movl $33, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl %ebx, %edi
callq hipGetErrorString
movl $_ZSt4cerr, %edi
movq %rax, %rsi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movq %rax, %rdi
callq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_
jmp .LBB1_19
.LBB1_24:
movq 8(%rsp), %rdi
callq hipFree
movl $_ZSt4cout, %edi
movl $.L.str.5, %esi
movl $13, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
callq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_
xorl %ebx, %ebx
.LBB1_25: # =>This Inner Loop Header: Depth=1
xorps %xmm0, %xmm0
cvtss2sd 16(%rsp,%rbx,4), %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movl $.L.str.6, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
incq %rbx
cmpq $256, %rbx # imm = 0x100
jne .LBB1_25
# %bb.26:
movl $_ZSt4cout, %edi
callq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_
xorl %eax, %eax
jmp .LBB1_21
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, %rdi
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15bitonicSortWarpPf, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z15bitonicSortWarpPf,@object # @_Z15bitonicSortWarpPf
.section .rodata,"a",@progbits
.globl _Z15bitonicSortWarpPf
.p2align 3, 0x0
_Z15bitonicSortWarpPf:
.quad _Z30__device_stub__bitonicSortWarpPf
.size _Z15bitonicSortWarpPf, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Failed to allocate device memory: "
.size .L.str, 35
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Failed to copy data to device: "
.size .L.str.1, 32
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Kernel launch failed: "
.size .L.str.2, 23
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Failed to synchronize: "
.size .L.str.3, 24
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Failed to copy data from device: "
.size .L.str.4, 34
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "Sorted array:"
.size .L.str.5, 14
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz " "
.size .L.str.6, 2
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z15bitonicSortWarpPf"
.size .L__unnamed_1, 22
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z30__device_stub__bitonicSortWarpPf
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z15bitonicSortWarpPf
.addrsig_sym _ZSt4cerr
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
```
| 3,847 | 5,000 |
113,658 |
Convert the following CUDA device assembly code to AMD device assembly:
```cudaasm
code for sm_80
Function : _Z20btreeOperationKernelP9BTreeNode
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ;
S2R R2, SR_TID.X ;
IMAD.MOV.U32 R3, RZ, RZ, 0x28 ;
ULDC.64 UR4, c[0x0][0x118] ;
BSSY B0, 0x190 ;
ISETP.GT.AND P0, PT, R2.reuse, 0x3f, PT ;
IMAD R0, R2.reuse, 0x28, RZ ;
IMAD.WIDE R2, R2, R3, c[0x0][0x160] ;
@P0 BRA 0x180 ;
LDG.E R4, [R2.64] ;
LDG.E R5, [R2.64+0x4] ;
LDG.E R6, [R2.64+0x8] ;
LDG.E R7, [R2.64+0xc] ;
LDG.E R8, [R2.64+0x10] ;
LDG.E R9, [R2.64+0x14] ;
LDG.E R10, [R2.64+0x18] ;
LDG.E R11, [R2.64+0x1c] ;
LDG.E R12, [R2.64+0x20] ;
LDG.E R13, [R2.64+0x24] ;
STS.64 [R0], R4 ;
STS.64 [R0+0x8], R6 ;
STS.64 [R0+0x10], R8 ;
STS.64 [R0+0x18], R10 ;
STS.64 [R0+0x20], R12 ;
BSYNC B0 ;
BAR.SYNC.DEFER_BLOCKING 0x0 ;
BSSY B0, 0x2a0 ;
@P0 BRA 0x290 ;
LDS R4, [R0+0x10] ;
ISETP.GE.AND P1, PT, R4, 0x1, PT ;
@!P1 BRA 0x290 ;
IMAD.MOV.U32 R4, RZ, RZ, RZ ;
IMAD.MOV.U32 R5, RZ, RZ, R0 ;
LDS R6, [R5] ;
IADD3 R4, R4, 0x1, RZ ;
IADD3 R6, R6, 0x1, RZ ;
STS [R5], R6 ;
LDS R7, [R0+0x10] ;
IADD3 R5, R5, 0x4, RZ ;
ISETP.GE.AND P1, PT, R4, R7, PT ;
@!P1 BRA 0x210 ;
BSYNC B0 ;
BAR.SYNC.DEFER_BLOCKING 0x0 ;
@P0 EXIT ;
LDS.64 R4, [R0] ;
LDS.64 R6, [R0+0x8] ;
LDS.64 R8, [R0+0x10] ;
LDS.64 R10, [R0+0x18] ;
LDS.64 R12, [R0+0x20] ;
STG.E [R2.64], R4 ;
STG.E [R2.64+0x4], R5 ;
STG.E [R2.64+0x8], R6 ;
STG.E [R2.64+0xc], R7 ;
STG.E [R2.64+0x10], R8 ;
STG.E [R2.64+0x14], R9 ;
STG.E [R2.64+0x18], R10 ;
STG.E [R2.64+0x1c], R11 ;
STG.E [R2.64+0x20], R12 ;
STG.E [R2.64+0x24], R13 ;
EXIT ;
BRA 0x3c0;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
```
|
```amdasm
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z20btreeOperationKernelP9BTreeNode ; -- Begin function _Z20btreeOperationKernelP9BTreeNode
.globl _Z20btreeOperationKernelP9BTreeNode
.p2align 8
.type _Z20btreeOperationKernelP9BTreeNode,@function
_Z20btreeOperationKernelP9BTreeNode: ; @_Z20btreeOperationKernelP9BTreeNode
; %bb.0:
s_load_b64 s[2:3], s[0:1], 0x0
v_cmp_gt_u32_e32 vcc_lo, 64, v0
v_mul_u32_u24_e32 v1, 40, v0
s_and_saveexec_b32 s0, vcc_lo
s_cbranch_execz .LBB0_2
; %bb.1:
s_waitcnt lgkmcnt(0)
v_mad_u64_u32 v[10:11], null, v0, 40, s[2:3]
v_mul_u32_u24_e32 v14, 40, v0
s_clause 0x2
global_load_b128 v[2:5], v[10:11], off offset:24
global_load_b128 v[6:9], v[10:11], off offset:16
global_load_b128 v[10:13], v[10:11], off
s_waitcnt vmcnt(2)
ds_store_2addr_b32 v14, v2, v3 offset0:6 offset1:7
ds_store_2addr_b32 v14, v4, v5 offset0:8 offset1:9
s_waitcnt vmcnt(1)
ds_store_2addr_b32 v14, v8, v9 offset0:6 offset1:7
ds_store_2addr_b32 v14, v6, v7 offset0:4 offset1:5
s_waitcnt vmcnt(0)
ds_store_2addr_b32 v14, v12, v13 offset0:2 offset1:3
ds_store_2addr_b32 v14, v10, v11 offset1:1
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s0
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_and_saveexec_b32 s1, vcc_lo
s_cbranch_execz .LBB0_6
; %bb.3: ; %.preheader
ds_load_b32 v2, v1 offset:16
s_mov_b32 s4, 0
s_waitcnt lgkmcnt(0)
v_cmp_lt_i32_e64 s0, 0, v2
s_delay_alu instid0(VALU_DEP_1)
s_and_b32 exec_lo, exec_lo, s0
s_cbranch_execz .LBB0_6
; %bb.4: ; %.lr.ph
v_mad_u32_u24 v2, v0, 40, 16
v_mov_b32_e32 v3, v1
s_mov_b32 s5, 0
.LBB0_5: ; =>This Inner Loop Header: Depth=1
ds_load_b32 v4, v3
s_add_i32 s5, s5, 1
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v4, 1, v4
ds_store_b32 v3, v4
ds_load_b32 v4, v2
v_add_nc_u32_e32 v3, 4, v3
s_waitcnt lgkmcnt(0)
v_cmp_ge_i32_e64 s0, s5, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_or_b32 s4, s0, s4
s_and_not1_b32 exec_lo, exec_lo, s4
s_cbranch_execnz .LBB0_5
.LBB0_6: ; %.loopexit
s_or_b32 exec_lo, exec_lo, s1
s_barrier
buffer_gl0_inv
s_and_saveexec_b32 s0, vcc_lo
s_cbranch_execz .LBB0_8
; %bb.7:
ds_load_2addr_b32 v[2:3], v1 offset0:6 offset1:7
ds_load_2addr_b32 v[4:5], v1 offset0:8 offset1:9
ds_load_2addr_b32 v[6:7], v1 offset0:4 offset1:5
ds_load_2addr_b32 v[12:13], v1 offset0:2 offset1:3
ds_load_2addr_b32 v[10:11], v1 offset1:1
v_mad_u64_u32 v[14:15], null, v0, 40, s[2:3]
s_waitcnt lgkmcnt(4)
v_dual_mov_b32 v8, v2 :: v_dual_mov_b32 v9, v3
s_waitcnt lgkmcnt(3)
global_store_b128 v[14:15], v[2:5], off offset:24
s_waitcnt lgkmcnt(2)
global_store_b128 v[14:15], v[6:9], off offset:16
s_waitcnt lgkmcnt(0)
global_store_b128 v[14:15], v[10:13], off
.LBB0_8:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z20btreeOperationKernelP9BTreeNode
.amdhsa_group_segment_fixed_size 2560
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 8
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 16
.amdhsa_next_free_sgpr 6
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z20btreeOperationKernelP9BTreeNode, .Lfunc_end0-_Z20btreeOperationKernelP9BTreeNode
; -- End function
.section .AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 408
; NumSgprs: 8
; NumVgprs: 16
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 2560 bytes/workgroup (compile time only)
; SGPRBlocks: 0
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 8
; NumVGPRsForWavesPerEU: 16
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object ; @__hip_cuid_
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0 ; 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 2560
.kernarg_segment_align: 8
.kernarg_segment_size: 8
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z20btreeOperationKernelP9BTreeNode
.private_segment_fixed_size: 0
.sgpr_count: 8
.sgpr_spill_count: 0
.symbol: _Z20btreeOperationKernelP9BTreeNode.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 16
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
```
| 1,067 | 2,821 |
113,659 |
Convert the following CUDA host assembly code to AMD host assembly:
```cudaasm
.file "tmpxft_000e3945_00000000-6_cuda_code_038612.cudafe1.cpp"
.text
.globl _ZSt21ios_base_library_initv
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3638:
.cfi_startproc
endbr64
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
jmp __cudaUnregisterFatBinary@PLT
.cfi_endproc
.LFE3638:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.align 2
.type _ZNSolsEPFRSoS_E.isra.0, @function
_ZNSolsEPFRSoS_E.isra.0:
.LFB4292:
.cfi_startproc
jmp *%rsi
.cfi_endproc
.LFE4292:
.size _ZNSolsEPFRSoS_E.isra.0, .-_ZNSolsEPFRSoS_E.isra.0
.globl _Z49__device_stub__Z20btreeOperationKernelP9BTreeNodeP9BTreeNode
.type _Z49__device_stub__Z20btreeOperationKernelP9BTreeNodeP9BTreeNode, @function
_Z49__device_stub__Z20btreeOperationKernelP9BTreeNodeP9BTreeNode:
.LFB3660:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movl $1, 40(%rsp)
movq %rax, 80(%rsp)
movabsq $4294967297, %rax
movq %rax, 32(%rsp)
movq %rax, 44(%rsp)
movl $1, 52(%rsp)
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
jne .L3
pushq 24(%rsp)
.cfi_def_cfa_offset 120
leaq _Z20btreeOperationKernelP9BTreeNode(%rip), %rdi
pushq 24(%rsp)
.cfi_def_cfa_offset 128
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq 96(%rsp), %r9
call cudaLaunchKernel@PLT
popq %rax
.cfi_def_cfa_offset 120
popq %rdx
.cfi_def_cfa_offset 112
.L3:
movq 88(%rsp), %rax
subq %fs:40, %rax
je .L5
call __stack_chk_fail@PLT
.L5:
addq $104, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3660:
.size _Z49__device_stub__Z20btreeOperationKernelP9BTreeNodeP9BTreeNode, .-_Z49__device_stub__Z20btreeOperationKernelP9BTreeNodeP9BTreeNode
.globl _Z20btreeOperationKernelP9BTreeNode
.type _Z20btreeOperationKernelP9BTreeNode, @function
_Z20btreeOperationKernelP9BTreeNode:
.LFB3661:
.cfi_startproc
endbr64
jmp _Z49__device_stub__Z20btreeOperationKernelP9BTreeNodeP9BTreeNode
.cfi_endproc
.LFE3661:
.size _Z20btreeOperationKernelP9BTreeNode, .-_Z20btreeOperationKernelP9BTreeNode
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Failed to allocate device memory: "
.LC1:
.string "Failed to copy data to device: "
.LC2:
.string "Kernel launch failed: "
.LC3:
.string "Failed to copy data from device: "
.LC4:
.string "Node "
.LC5:
.string ": "
.LC6:
.string " "
.section .text.startup,"ax",@progbits
.globl main
.type main, @function
main:
.LFB3635:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
movl $2560, %edi
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $56, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
call _Znam@PLT
movl $1, %edx
movq %rax, %rbx
movq %rax, %r12
.L10:
leal -1(%rdx), %ecx
movl %edx, 4(%rax)
addq $40, %rax
movl %ecx, -40(%rax)
leal 1(%rdx), %ecx
movl %ecx, -32(%rax)
leal 2(%rdx), %ecx
addl $4, %edx
movl $4, -24(%rax)
movl %ecx, -28(%rax)
movl $-1, -20(%rax)
movl $-1, -16(%rax)
movl $-1, -12(%rax)
movl $-1, -8(%rax)
movl $-1, -4(%rax)
cmpl $257, %edx
jne .L10
leaq 8(%rsp), %rdi
movl $2560, %esi
call cudaMalloc@PLT
movl %eax, %ebp
testl %eax, %eax
je .L11
leaq .LC0(%rip), %rsi
leaq _ZSt4cerr(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movl %ebp, %edi
movq %rax, %r12
call cudaGetErrorString@PLT
movq %r12, %rdi
movq %rax, %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@GOTPCREL(%rip), %rsi
movq %rax, %rdi
call _ZNSolsEPFRSoS_E.isra.0
jmp .L26
.L11:
movq 8(%rsp), %rdi
movl $1, %ecx
movl $2560, %edx
movq %rbx, %rsi
call cudaMemcpy@PLT
movl %eax, %ebp
testl %eax, %eax
je .L13
leaq .LC1(%rip), %rsi
.L28:
leaq _ZSt4cerr(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movl %ebp, %edi
movq %rax, %r12
call cudaGetErrorString@PLT
movq %r12, %rdi
movq %rax, %rsi
.L27:
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@GOTPCREL(%rip), %rsi
movq %rax, %rdi
call _ZNSolsEPFRSoS_E.isra.0
movq 8(%rsp), %rdi
call cudaFree@PLT
.L26:
movq %rbx, %rdi
call _ZdaPv@PLT
orl $-1, %eax
jmp .L9
.L13:
movl $67108865, %edx
xorl %r9d, %r9d
xorl %r8d, %r8d
movl $1, %ecx
salq $6, %rdx
movl $1, %esi
movabsq $4294967297, %rdi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L15
movq 8(%rsp), %rdi
call _Z49__device_stub__Z20btreeOperationKernelP9BTreeNodeP9BTreeNode
.L15:
call cudaGetLastError@PLT
leaq .LC2(%rip), %rsi
movl %eax, %ebp
testl %eax, %eax
jne .L28
movq 8(%rsp), %rsi
movl $2, %ecx
movq %rbx, %rdi
xorl %ebp, %ebp
movl $2560, %edx
leaq .LC4(%rip), %r14
call cudaMemcpy@PLT
movl %eax, %r13d
testl %eax, %eax
je .L17
leaq .LC3(%rip), %rsi
leaq _ZSt4cerr(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movl %r13d, %edi
movq %rax, %rbp
call cudaGetErrorString@PLT
movq %rbp, %rdi
movq %rax, %rsi
jmp .L27
.L17:
movq %r14, %rsi
leaq _ZSt4cout(%rip), %rdi
xorl %r13d, %r13d
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movl %ebp, %esi
leaq .LC6(%rip), %r15
movq %rax, %rdi
call _ZNSolsEi@PLT
leaq .LC5(%rip), %rsi
movq %rax, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
.L18:
cmpl %r13d, 16(%r12)
jle .L29
movl (%r12,%r13,4), %esi
leaq _ZSt4cout(%rip), %rdi
incq %r13
call _ZNSolsEi@PLT
movq %r15, %rsi
movq %rax, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
jmp .L18
.L29:
movq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@GOTPCREL(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
incl %ebp
addq $40, %r12
call _ZNSolsEPFRSoS_E.isra.0
cmpl $64, %ebp
jne .L17
movq 8(%rsp), %rdi
call cudaFree@PLT
movq %rbx, %rdi
call _ZdaPv@PLT
xorl %eax, %eax
.L9:
movq 40(%rsp), %rdx
subq %fs:40, %rdx
je .L20
call __stack_chk_fail@PLT
.L20:
addq $56, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3635:
.size main, .-main
.section .rodata.str1.1
.LC7:
.string "_Z20btreeOperationKernelP9BTreeNode"
.section .text.startup
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3663:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
pushq $0
.cfi_def_cfa_offset 24
xorl %r9d, %r9d
orl $-1, %r8d
pushq $0
.cfi_def_cfa_offset 32
leaq .LC7(%rip), %rdx
movq %rax, %rdi
leaq _Z20btreeOperationKernelP9BTreeNode(%rip), %rsi
pushq $0
.cfi_def_cfa_offset 40
movq %rdx, %rcx
pushq $0
.cfi_def_cfa_offset 48
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFunction@PLT
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
addq $32, %rsp
.cfi_def_cfa_offset 16
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
popq %rdx
.cfi_def_cfa_offset 8
jmp atexit@PLT
.cfi_endproc
.LFE3663:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
```
|
```amdasm
.text
.file "cuda_code_038612.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z35__device_stub__btreeOperationKernelP9BTreeNode # -- Begin function _Z35__device_stub__btreeOperationKernelP9BTreeNode
.type _Z35__device_stub__btreeOperationKernelP9BTreeNode,@function
_Z35__device_stub__btreeOperationKernelP9BTreeNode: # @_Z35__device_stub__btreeOperationKernelP9BTreeNode
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $64, %rsp
.cfi_def_cfa_offset 112
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 24(%rsp), %rax
movq %rdi, (%rax)
movq %rsp, %rbx
movq %rax, (%rbx)
leaq 48(%rsp), %r14
leaq 32(%rsp), %r15
leaq 16(%rsp), %r12
leaq 8(%rsp), %r13
movq %r14, %rdi
movq %r15, %rsi
movq %r12, %rdx
movq %r13, %rcx
callq __hipPopCallConfiguration
movq (%r14), %rsi
movl 8(%r14), %edx
movq (%r15), %rcx
movl 8(%r15), %r8d
movl $_Z20btreeOperationKernelP9BTreeNode, %edi
movq %rbx, %r9
pushq (%r13)
.cfi_adjust_cfa_offset 8
pushq (%r12)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $80, %rsp
.cfi_adjust_cfa_offset -80
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z35__device_stub__btreeOperationKernelP9BTreeNode, .Lfunc_end0-_Z35__device_stub__btreeOperationKernelP9BTreeNode
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
pushq %rax
.cfi_def_cfa_offset 64
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $2560, %edi # imm = 0xA00
callq _Znam
movq %rax, %rbx
addq $20, %rax
xorl %ecx, %ecx
pcmpeqd %xmm0, %xmm0
movq %rbx, %rdx
xorl %esi, %esi
.LBB1_1: # =>This Loop Header: Depth=1
# Child Loop BB1_2 Depth 2
leaq (,%rsi,8), %rdi
leaq (%rdi,%rdi,4), %r8
leaq (%rax,%r8), %rdi
movl $4, 16(%rbx,%r8)
xorl %r8d, %r8d
.LBB1_2: # Parent Loop BB1_1 Depth=1
# => This Inner Loop Header: Depth=2
leal (%rcx,%r8), %r9d
movl %r9d, (%rdx,%r8,4)
incq %r8
cmpq $4, %r8
jne .LBB1_2
# %bb.3: # %.preheader65.preheader
# in Loop: Header=BB1_1 Depth=1
movdqu %xmm0, (%rdi)
movl $-1, 16(%rdi)
incq %rsi
addq $40, %rdx
addq $4, %rcx
cmpq $64, %rsi
jne .LBB1_1
# %bb.4:
movq %rsp, %rdi
movl $2560, %esi # imm = 0xA00
callq hipMalloc
testl %eax, %eax
je .LBB1_11
# %bb.5:
movl %eax, %ebp
movl $_ZSt4cerr, %edi
movl $.L.str, %esi
movl $34, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl %ebp, %edi
callq hipGetErrorString
testq %rax, %rax
je .LBB1_6
# %bb.7:
movq %rax, %r14
movq %rax, %rdi
callq strlen
movl $_ZSt4cerr, %edi
movq %r14, %rsi
movq %rax, %rdx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
jmp .LBB1_8
.LBB1_11:
movq (%rsp), %rdi
movl $2560, %edx # imm = 0xA00
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
je .LBB1_17
# %bb.12:
movl %eax, %ebp
movl $_ZSt4cerr, %edi
movl $.L.str.1, %esi
movl $31, %edx
jmp .LBB1_13
.LBB1_6:
movq _ZSt4cerr(%rip), %rax
movq -24(%rax), %rax
leaq _ZSt4cerr(%rax), %rdi
movl 32(%rdi), %esi
orl $1, %esi
callq _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate
.LBB1_8: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit
movq _ZSt4cerr(%rip), %rax
movl $_ZSt4cerr, %ecx
movq -24(%rax), %rdi
addq %rcx, %rdi
movl $10, %esi
callq _ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
movsbl %al, %esi
movl $_ZSt4cerr, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
jmp .LBB1_9
.LBB1_17:
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 63(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_19
# %bb.18:
movq (%rsp), %rdi
callq _Z35__device_stub__btreeOperationKernelP9BTreeNode
.LBB1_19:
callq hipGetLastError
testl %eax, %eax
je .LBB1_21
# %bb.20:
movl %eax, %ebp
movl $_ZSt4cerr, %edi
movl $.L.str.2, %esi
movl $22, %edx
jmp .LBB1_13
.LBB1_21:
movq (%rsp), %rsi
movl $2560, %edx # imm = 0xA00
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
je .LBB1_22
# %bb.28:
movl %eax, %ebp
movl $_ZSt4cerr, %edi
movl $.L.str.3, %esi
movl $33, %edx
.LBB1_13:
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl %ebp, %edi
callq hipGetErrorString
testq %rax, %rax
je .LBB1_14
# %bb.15:
movq %rax, %r14
movq %rax, %rdi
callq strlen
movl $_ZSt4cerr, %edi
movq %r14, %rsi
movq %rax, %rdx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
jmp .LBB1_16
.LBB1_14:
movq _ZSt4cerr(%rip), %rax
movq -24(%rax), %rax
leaq _ZSt4cerr(%rax), %rdi
movl 32(%rdi), %esi
orl $1, %esi
callq _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate
.LBB1_16: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit57
movq _ZSt4cerr(%rip), %rax
movl $_ZSt4cerr, %ecx
movq -24(%rax), %rdi
addq %rcx, %rdi
movl $10, %esi
callq _ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
movsbl %al, %esi
movl $_ZSt4cerr, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq (%rsp), %rdi
callq hipFree
.LBB1_9:
movl $-1, %ebp
.LBB1_10:
movq %rbx, %rdi
callq _ZdaPv
movl %ebp, %eax
addq $8, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB1_22: # %.preheader.preheader
.cfi_def_cfa_offset 64
xorl %r14d, %r14d
movl $_ZSt4cout, %r15d
movq %rbx, %r12
.LBB1_23: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB1_25 Depth 2
movl $_ZSt4cout, %edi
movl $.L.str.4, %esi
movl $5, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl %r14d, %esi
callq _ZNSolsEi
movl $.L.str.5, %esi
movl $2, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
leaq (%r14,%r14,4), %rax
cmpl $0, 16(%rbx,%rax,8)
jle .LBB1_26
# %bb.24: # %.lr.ph
# in Loop: Header=BB1_23 Depth=1
leaq (%rbx,%rax,8), %r13
addq $16, %r13
xorl %ebp, %ebp
.LBB1_25: # Parent Loop BB1_23 Depth=1
# => This Inner Loop Header: Depth=2
movl (%r12,%rbp,4), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movl $.L.str.6, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
incq %rbp
movslq (%r13), %rax
cmpq %rax, %rbp
jl .LBB1_25
.LBB1_26: # %._crit_edge
# in Loop: Header=BB1_23 Depth=1
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rdi
addq %r15, %rdi
movl $10, %esi
callq _ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
incq %r14
addq $40, %r12
cmpq $64, %r14
jne .LBB1_23
# %bb.27:
movq (%rsp), %rdi
callq hipFree
xorl %ebp, %ebp
jmp .LBB1_10
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, %rdi
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z20btreeOperationKernelP9BTreeNode, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z20btreeOperationKernelP9BTreeNode,@object # @_Z20btreeOperationKernelP9BTreeNode
.section .rodata,"a",@progbits
.globl _Z20btreeOperationKernelP9BTreeNode
.p2align 3, 0x0
_Z20btreeOperationKernelP9BTreeNode:
.quad _Z35__device_stub__btreeOperationKernelP9BTreeNode
.size _Z20btreeOperationKernelP9BTreeNode, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Failed to allocate device memory: "
.size .L.str, 35
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Failed to copy data to device: "
.size .L.str.1, 32
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Kernel launch failed: "
.size .L.str.2, 23
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Failed to copy data from device: "
.size .L.str.3, 34
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Node "
.size .L.str.4, 6
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz ": "
.size .L.str.5, 3
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz " "
.size .L.str.6, 2
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z20btreeOperationKernelP9BTreeNode"
.size .L__unnamed_1, 36
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z35__device_stub__btreeOperationKernelP9BTreeNode
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z20btreeOperationKernelP9BTreeNode
.addrsig_sym _ZSt4cerr
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
```
| 4,212 | 5,597 |
113,660 |
Convert the following CUDA device assembly code to AMD device assembly:
```cudaasm
code for sm_80
Function : _Z16extractMinFromPQPiS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ;
S2R R0, SR_TID.X ;
BSSY B0, 0xe0 ;
ISETP.NE.AND P0, PT, R0, RZ, PT ;
@P0 BRA 0xd0 ;
IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x164] ;
MOV R2, c[0x0][0x160] ;
IMAD.MOV.U32 R7, RZ, RZ, 0x7fffffff ;
ULDC.64 UR4, c[0x0][0x118] ;
ATOMG.E.MIN.S32.STRONG.GPU PT, R3, [R2.64], R7 ;
MOV R4, c[0x0][0x168] ;
MOV R5, c[0x0][0x16c] ;
STG.E [R4.64], R3 ;
BSYNC B0 ;
BAR.SYNC 0x0 ;
EXIT ;
BRA 0x100;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
Function : _Z12insertIntoPQPiS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ;
S2R R6, SR_TID.X ;
BSSY B0, 0xad0 ;
ISETP.GE.AND P0, PT, R6, c[0x0][0x170], PT ;
@P0 BRA 0xac0 ;
IMAD.MOV.U32 R7, RZ, RZ, 0x4 ;
ULDC.64 UR4, c[0x0][0x118] ;
IMAD.WIDE R6, R6, R7, c[0x0][0x168] ;
LDG.E R5, [R6.64] ;
IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x160] ;
IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x164] ;
IMAD.MOV.U32 R4, RZ, RZ, 0x7fffffff ;
ATOMG.E.CAS.STRONG.GPU PT, R9, [R2], R4, R5 ;
ISETP.NE.AND P0, PT, R9, 0x7fffffff, PT ;
@!P0 BRA 0xac0 ;
ULDC.64 UR4, c[0x0][0x118] ;
ATOMG.E.EXCH.STRONG.GPU PT, RZ, [R2.64], R9 ;
ATOMG.E.CAS.STRONG.GPU PT, R7, [R2+0x4], R4, R5 ;
ISETP.NE.AND P0, PT, R7, 0x7fffffff, PT ;
@!P0 BRA 0xac0 ;
ULDC.64 UR4, c[0x0][0x118] ;
ATOMG.E.EXCH.STRONG.GPU PT, RZ, [R2.64+0x4], R7 ;
ATOMG.E.CAS.STRONG.GPU PT, R9, [R2+0x8], R4, R5 ;
ISETP.NE.AND P0, PT, R9, 0x7fffffff, PT ;
@!P0 BRA 0xac0 ;
ULDC.64 UR4, c[0x0][0x118] ;
ATOMG.E.EXCH.STRONG.GPU PT, RZ, [R2.64+0x8], R9 ;
ATOMG.E.CAS.STRONG.GPU PT, R7, [R2+0xc], R4, R5 ;
ISETP.NE.AND P0, PT, R7, 0x7fffffff, PT ;
@!P0 BRA 0xac0 ;
ULDC.64 UR4, c[0x0][0x118] ;
ATOMG.E.EXCH.STRONG.GPU PT, RZ, [R2.64+0xc], R7 ;
ATOMG.E.CAS.STRONG.GPU PT, R9, [R2+0x10], R4, R5 ;
ISETP.NE.AND P0, PT, R9, 0x7fffffff, PT ;
@!P0 BRA 0xac0 ;
ULDC.64 UR4, c[0x0][0x118] ;
ATOMG.E.EXCH.STRONG.GPU PT, RZ, [R2.64+0x10], R9 ;
ATOMG.E.CAS.STRONG.GPU PT, R7, [R2+0x14], R4, R5 ;
ISETP.NE.AND P0, PT, R7, 0x7fffffff, PT ;
@!P0 BRA 0xac0 ;
ULDC.64 UR4, c[0x0][0x118] ;
ATOMG.E.EXCH.STRONG.GPU PT, RZ, [R2.64+0x14], R7 ;
ATOMG.E.CAS.STRONG.GPU PT, R9, [R2+0x18], R4, R5 ;
ISETP.NE.AND P0, PT, R9, 0x7fffffff, PT ;
@!P0 BRA 0xac0 ;
ULDC.64 UR4, c[0x0][0x118] ;
ATOMG.E.EXCH.STRONG.GPU PT, RZ, [R2.64+0x18], R9 ;
ATOMG.E.CAS.STRONG.GPU PT, R7, [R2+0x1c], R4, R5 ;
ISETP.NE.AND P0, PT, R7, 0x7fffffff, PT ;
@!P0 BRA 0xac0 ;
ULDC.64 UR4, c[0x0][0x118] ;
ATOMG.E.EXCH.STRONG.GPU PT, RZ, [R2.64+0x1c], R7 ;
ATOMG.E.CAS.STRONG.GPU PT, R9, [R2+0x20], R4, R5 ;
ISETP.NE.AND P0, PT, R9, 0x7fffffff, PT ;
@!P0 BRA 0xac0 ;
ULDC.64 UR4, c[0x0][0x118] ;
ATOMG.E.EXCH.STRONG.GPU PT, RZ, [R2.64+0x20], R9 ;
ATOMG.E.CAS.STRONG.GPU PT, R7, [R2+0x24], R4, R5 ;
ISETP.NE.AND P0, PT, R7, 0x7fffffff, PT ;
@!P0 BRA 0xac0 ;
ULDC.64 UR4, c[0x0][0x118] ;
ATOMG.E.EXCH.STRONG.GPU PT, RZ, [R2.64+0x24], R7 ;
ATOMG.E.CAS.STRONG.GPU PT, R9, [R2+0x28], R4, R5 ;
ISETP.NE.AND P0, PT, R9, 0x7fffffff, PT ;
@!P0 BRA 0xac0 ;
ULDC.64 UR4, c[0x0][0x118] ;
ATOMG.E.EXCH.STRONG.GPU PT, RZ, [R2.64+0x28], R9 ;
ATOMG.E.CAS.STRONG.GPU PT, R7, [R2+0x2c], R4, R5 ;
ISETP.NE.AND P0, PT, R7, 0x7fffffff, PT ;
@!P0 BRA 0xac0 ;
ULDC.64 UR4, c[0x0][0x118] ;
ATOMG.E.EXCH.STRONG.GPU PT, RZ, [R2.64+0x2c], R7 ;
ATOMG.E.CAS.STRONG.GPU PT, R9, [R2+0x30], R4, R5 ;
ISETP.NE.AND P0, PT, R9, 0x7fffffff, PT ;
@!P0 BRA 0xac0 ;
ULDC.64 UR4, c[0x0][0x118] ;
ATOMG.E.EXCH.STRONG.GPU PT, RZ, [R2.64+0x30], R9 ;
ATOMG.E.CAS.STRONG.GPU PT, R7, [R2+0x34], R4, R5 ;
ISETP.NE.AND P0, PT, R7, 0x7fffffff, PT ;
@!P0 BRA 0xac0 ;
ULDC.64 UR4, c[0x0][0x118] ;
ATOMG.E.EXCH.STRONG.GPU PT, RZ, [R2.64+0x34], R7 ;
ATOMG.E.CAS.STRONG.GPU PT, R9, [R2+0x38], R4, R5 ;
ISETP.NE.AND P0, PT, R9, 0x7fffffff, PT ;
@!P0 BRA 0xac0 ;
ULDC.64 UR4, c[0x0][0x118] ;
ATOMG.E.EXCH.STRONG.GPU PT, RZ, [R2.64+0x38], R9 ;
ATOMG.E.CAS.STRONG.GPU PT, R7, [R2+0x3c], R4, R5 ;
ISETP.NE.AND P0, PT, R7, 0x7fffffff, PT ;
@!P0 BRA 0xac0 ;
ULDC.64 UR4, c[0x0][0x118] ;
ATOMG.E.EXCH.STRONG.GPU PT, RZ, [R2.64+0x3c], R7 ;
ATOMG.E.CAS.STRONG.GPU PT, R9, [R2+0x40], R4, R5 ;
ISETP.NE.AND P0, PT, R9, 0x7fffffff, PT ;
@!P0 BRA 0xac0 ;
ULDC.64 UR4, c[0x0][0x118] ;
ATOMG.E.EXCH.STRONG.GPU PT, RZ, [R2.64+0x40], R9 ;
ATOMG.E.CAS.STRONG.GPU PT, R7, [R2+0x44], R4, R5 ;
ISETP.NE.AND P0, PT, R7, 0x7fffffff, PT ;
@!P0 BRA 0xac0 ;
ULDC.64 UR4, c[0x0][0x118] ;
ATOMG.E.EXCH.STRONG.GPU PT, RZ, [R2.64+0x44], R7 ;
ATOMG.E.CAS.STRONG.GPU PT, R9, [R2+0x48], R4, R5 ;
ISETP.NE.AND P0, PT, R9, 0x7fffffff, PT ;
@!P0 BRA 0xac0 ;
ULDC.64 UR4, c[0x0][0x118] ;
ATOMG.E.EXCH.STRONG.GPU PT, RZ, [R2.64+0x48], R9 ;
ATOMG.E.CAS.STRONG.GPU PT, R7, [R2+0x4c], R4, R5 ;
ISETP.NE.AND P0, PT, R7, 0x7fffffff, PT ;
@!P0 BRA 0xac0 ;
ULDC.64 UR4, c[0x0][0x118] ;
ATOMG.E.EXCH.STRONG.GPU PT, RZ, [R2.64+0x4c], R7 ;
ATOMG.E.CAS.STRONG.GPU PT, R9, [R2+0x50], R4, R5 ;
ISETP.NE.AND P0, PT, R9, 0x7fffffff, PT ;
@!P0 BRA 0xac0 ;
ULDC.64 UR4, c[0x0][0x118] ;
ATOMG.E.EXCH.STRONG.GPU PT, RZ, [R2.64+0x50], R9 ;
ATOMG.E.CAS.STRONG.GPU PT, R7, [R2+0x54], R4, R5 ;
ISETP.NE.AND P0, PT, R7, 0x7fffffff, PT ;
@!P0 BRA 0xac0 ;
ULDC.64 UR4, c[0x0][0x118] ;
ATOMG.E.EXCH.STRONG.GPU PT, RZ, [R2.64+0x54], R7 ;
ATOMG.E.CAS.STRONG.GPU PT, R9, [R2+0x58], R4, R5 ;
ISETP.NE.AND P0, PT, R9, 0x7fffffff, PT ;
@!P0 BRA 0xac0 ;
ULDC.64 UR4, c[0x0][0x118] ;
ATOMG.E.EXCH.STRONG.GPU PT, RZ, [R2.64+0x58], R9 ;
ATOMG.E.CAS.STRONG.GPU PT, R7, [R2+0x5c], R4, R5 ;
ISETP.NE.AND P0, PT, R7, 0x7fffffff, PT ;
@!P0 BRA 0xac0 ;
ULDC.64 UR4, c[0x0][0x118] ;
ATOMG.E.EXCH.STRONG.GPU PT, RZ, [R2.64+0x5c], R7 ;
ATOMG.E.CAS.STRONG.GPU PT, R9, [R2+0x60], R4, R5 ;
ISETP.NE.AND P0, PT, R9, 0x7fffffff, PT ;
@!P0 BRA 0xac0 ;
ULDC.64 UR4, c[0x0][0x118] ;
ATOMG.E.EXCH.STRONG.GPU PT, RZ, [R2.64+0x60], R9 ;
ATOMG.E.CAS.STRONG.GPU PT, R7, [R2+0x64], R4, R5 ;
ISETP.NE.AND P0, PT, R7, 0x7fffffff, PT ;
@!P0 BRA 0xac0 ;
ULDC.64 UR4, c[0x0][0x118] ;
ATOMG.E.EXCH.STRONG.GPU PT, RZ, [R2.64+0x64], R7 ;
ATOMG.E.CAS.STRONG.GPU PT, R9, [R2+0x68], R4, R5 ;
ISETP.NE.AND P0, PT, R9, 0x7fffffff, PT ;
@!P0 BRA 0xac0 ;
ULDC.64 UR4, c[0x0][0x118] ;
ATOMG.E.EXCH.STRONG.GPU PT, RZ, [R2.64+0x68], R9 ;
ATOMG.E.CAS.STRONG.GPU PT, R7, [R2+0x6c], R4, R5 ;
ISETP.NE.AND P0, PT, R7, 0x7fffffff, PT ;
@!P0 BRA 0xac0 ;
ULDC.64 UR4, c[0x0][0x118] ;
ATOMG.E.EXCH.STRONG.GPU PT, RZ, [R2.64+0x6c], R7 ;
ATOMG.E.CAS.STRONG.GPU PT, R9, [R2+0x70], R4, R5 ;
ISETP.NE.AND P0, PT, R9, 0x7fffffff, PT ;
@!P0 BRA 0xac0 ;
ULDC.64 UR4, c[0x0][0x118] ;
ATOMG.E.EXCH.STRONG.GPU PT, RZ, [R2.64+0x70], R9 ;
ATOMG.E.CAS.STRONG.GPU PT, R7, [R2+0x74], R4, R5 ;
ISETP.NE.AND P0, PT, R7, 0x7fffffff, PT ;
@!P0 BRA 0xac0 ;
ULDC.64 UR4, c[0x0][0x118] ;
ATOMG.E.EXCH.STRONG.GPU PT, RZ, [R2.64+0x74], R7 ;
ATOMG.E.CAS.STRONG.GPU PT, R9, [R2+0x78], R4, R5 ;
ISETP.NE.AND P0, PT, R9, 0x7fffffff, PT ;
@!P0 BRA 0xac0 ;
ULDC.64 UR4, c[0x0][0x118] ;
ATOMG.E.EXCH.STRONG.GPU PT, RZ, [R2.64+0x78], R9 ;
ATOMG.E.CAS.STRONG.GPU PT, R5, [R2+0x7c], R4, R5 ;
ISETP.NE.AND P0, PT, R5, 0x7fffffff, PT ;
@!P0 BRA 0xac0 ;
ULDC.64 UR4, c[0x0][0x118] ;
ATOMG.E.EXCH.STRONG.GPU PT, RZ, [R2.64+0x7c], R5 ;
BSYNC B0 ;
BAR.SYNC 0x0 ;
EXIT ;
BRA 0xaf0;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
```
|
```amdasm
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z12insertIntoPQPiS_i ; -- Begin function _Z12insertIntoPQPiS_i
.globl _Z12insertIntoPQPiS_i
.p2align 8
.type _Z12insertIntoPQPiS_i,@function
_Z12insertIntoPQPiS_i: ; @_Z12insertIntoPQPiS_i
; %bb.0:
s_load_b32 s2, s[0:1], 0x10
s_mov_b32 s6, exec_lo
s_waitcnt lgkmcnt(0)
v_cmpx_gt_i32_e64 s2, v0
s_cbranch_execz .LBB0_5
; %bb.1:
s_load_b128 s[0:3], s[0:1], 0x0
v_lshlrev_b32_e32 v0, 2, v0
v_mov_b32_e32 v2, 0
v_bfrev_b32_e32 v1, -2
s_mov_b32 s7, 0
; implicit-def: $sgpr8
s_waitcnt lgkmcnt(0)
global_load_b32 v0, v0, s[2:3]
s_mov_b64 s[2:3], 0
.LBB0_2: ; =>This Inner Loop Header: Depth=1
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s4, s0, s2
s_addc_u32 s5, s1, s3
s_or_b32 s8, s8, exec_lo
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b32 v3, v2, v[0:1], s[4:5] glc
s_mov_b32 s9, exec_lo
s_waitcnt vmcnt(0)
v_cmpx_ne_u32_e32 0x7fffffff, v3
s_cbranch_execz .LBB0_4
; %bb.3: ; in Loop: Header=BB0_2 Depth=1
global_atomic_swap_b32 v2, v3, s[4:5]
s_add_u32 s2, s2, 4
s_addc_u32 s3, s3, 0
s_cmpk_eq_i32 s2, 0x80
s_cselect_b32 s4, -1, 0
s_and_not1_b32 s5, s8, exec_lo
s_and_b32 s4, s4, exec_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 s8, s5, s4
.LBB0_4: ; %Flow
; in Loop: Header=BB0_2 Depth=1
s_or_b32 exec_lo, exec_lo, s9
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s4, exec_lo, s8
s_or_b32 s7, s4, s7
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s7
s_cbranch_execnz .LBB0_2
.LBB0_5: ; %Flow28
s_or_b32 exec_lo, exec_lo, s6
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z12insertIntoPQPiS_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 20
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 10
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z12insertIntoPQPiS_i, .Lfunc_end0-_Z12insertIntoPQPiS_i
; -- End function
.section .AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 208
; NumSgprs: 10
; NumVgprs: 4
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 1
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 10
; NumVGPRsForWavesPerEU: 4
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
.text
.protected _Z16extractMinFromPQPiS_ ; -- Begin function _Z16extractMinFromPQPiS_
.globl _Z16extractMinFromPQPiS_
.p2align 8
.type _Z16extractMinFromPQPiS_,@function
_Z16extractMinFromPQPiS_: ; @_Z16extractMinFromPQPiS_
; %bb.0:
s_mov_b32 s4, exec_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB1_4
; %bb.1:
s_load_b128 s[0:3], s[0:1], 0x0
v_mbcnt_lo_u32_b32 v0, exec_lo, 0
s_delay_alu instid0(VALU_DEP_1)
v_cmp_eq_u32_e32 vcc_lo, 0, v0
; implicit-def: $vgpr0
s_and_saveexec_b32 s5, vcc_lo
s_cbranch_execz .LBB1_3
; %bb.2:
v_mov_b32_e32 v0, 0
s_waitcnt lgkmcnt(0)
global_load_b32 v0, v0, s[0:1] glc
.LBB1_3:
s_or_b32 exec_lo, exec_lo, s5
s_waitcnt vmcnt(0) lgkmcnt(0)
v_readfirstlane_b32 s0, v0
s_delay_alu instid0(VALU_DEP_1)
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s0
global_store_b32 v0, v1, s[2:3]
.LBB1_4: ; %Flow
s_or_b32 exec_lo, exec_lo, s4
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z16extractMinFromPQPiS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 16
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 6
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z16extractMinFromPQPiS_, .Lfunc_end1-_Z16extractMinFromPQPiS_
; -- End function
.section .AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 116
; NumSgprs: 8
; NumVgprs: 2
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 0
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 8
; NumVGPRsForWavesPerEU: 2
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object ; @__hip_cuid_
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0 ; 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 20
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z12insertIntoPQPiS_i
.private_segment_fixed_size: 0
.sgpr_count: 10
.sgpr_spill_count: 0
.symbol: _Z12insertIntoPQPiS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 16
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z16extractMinFromPQPiS_
.private_segment_fixed_size: 0
.sgpr_count: 8
.sgpr_spill_count: 0
.symbol: _Z16extractMinFromPQPiS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
```
| 4,300 | 3,979 |
113,661 |
Convert the following CUDA host assembly code to AMD host assembly:
```cudaasm
.file "tmpxft_00111d79_00000000-6_cuda_code_085996.cudafe1.cpp"
.text
.globl _ZSt21ios_base_library_initv
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB6835:
.cfi_startproc
endbr64
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
jmp __cudaUnregisterFatBinary@PLT
.cfi_endproc
.LFE6835:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.align 2
.type _ZNSolsEPFRSoS_E.isra.0, @function
_ZNSolsEPFRSoS_E.isra.0:
.LFB7719:
.cfi_startproc
jmp *%rsi
.cfi_endproc
.LFE7719:
.size _ZNSolsEPFRSoS_E.isra.0, .-_ZNSolsEPFRSoS_E.isra.0
.globl _Z35__device_stub__Z12insertIntoPQPiS_iPiS_i
.type _Z35__device_stub__Z12insertIntoPQPiS_iPiS_i, @function
_Z35__device_stub__Z12insertIntoPQPiS_iPiS_i:
.LFB6857:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
leaq 40(%rsp), %rcx
leaq 48(%rsp), %rdi
movq %rsi, 16(%rsp)
leaq 60(%rsp), %rsi
movl %edx, 12(%rsp)
leaq 32(%rsp), %rdx
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movl $1, 56(%rsp)
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movabsq $4294967297, %rax
movq %rax, 48(%rsp)
movq %rax, 60(%rsp)
movl $1, 68(%rsp)
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
jne .L3
pushq 40(%rsp)
.cfi_def_cfa_offset 152
leaq _Z12insertIntoPQPiS_i(%rip), %rdi
pushq 40(%rsp)
.cfi_def_cfa_offset 160
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq 112(%rsp), %r9
call cudaLaunchKernel@PLT
popq %rax
.cfi_def_cfa_offset 152
popq %rdx
.cfi_def_cfa_offset 144
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
je .L5
call __stack_chk_fail@PLT
.L5:
addq $136, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE6857:
.size _Z35__device_stub__Z12insertIntoPQPiS_iPiS_i, .-_Z35__device_stub__Z12insertIntoPQPiS_iPiS_i
.globl _Z12insertIntoPQPiS_i
.type _Z12insertIntoPQPiS_i, @function
_Z12insertIntoPQPiS_i:
.LFB6858:
.cfi_startproc
endbr64
jmp _Z35__device_stub__Z12insertIntoPQPiS_iPiS_i
.cfi_endproc
.LFE6858:
.size _Z12insertIntoPQPiS_i, .-_Z12insertIntoPQPiS_i
.globl _Z38__device_stub__Z16extractMinFromPQPiS_PiS_
.type _Z38__device_stub__Z16extractMinFromPQPiS_PiS_, @function
_Z38__device_stub__Z16extractMinFromPQPiS_PiS_:
.LFB6859:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
leaq 32(%rsp), %rcx
leaq 24(%rsp), %rdx
movq %rsi, (%rsp)
leaq 40(%rsp), %rdi
leaq 52(%rsp), %rsi
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movl $1, 48(%rsp)
movq %rax, 88(%rsp)
movq %rsp, %rax
movq %rax, 96(%rsp)
movabsq $4294967297, %rax
movq %rax, 40(%rsp)
movq %rax, 52(%rsp)
movl $1, 60(%rsp)
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
jne .L9
pushq 32(%rsp)
.cfi_def_cfa_offset 136
leaq _Z16extractMinFromPQPiS_(%rip), %rdi
pushq 32(%rsp)
.cfi_def_cfa_offset 144
movq 68(%rsp), %rcx
movl 76(%rsp), %r8d
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
leaq 104(%rsp), %r9
call cudaLaunchKernel@PLT
popq %rax
.cfi_def_cfa_offset 136
popq %rdx
.cfi_def_cfa_offset 128
.L9:
movq 104(%rsp), %rax
subq %fs:40, %rax
je .L11
call __stack_chk_fail@PLT
.L11:
addq $120, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE6859:
.size _Z38__device_stub__Z16extractMinFromPQPiS_PiS_, .-_Z38__device_stub__Z16extractMinFromPQPiS_PiS_
.globl _Z16extractMinFromPQPiS_
.type _Z16extractMinFromPQPiS_, @function
_Z16extractMinFromPQPiS_:
.LFB6860:
.cfi_startproc
endbr64
jmp _Z38__device_stub__Z16extractMinFromPQPiS_PiS_
.cfi_endproc
.LFE6860:
.size _Z16extractMinFromPQPiS_, .-_Z16extractMinFromPQPiS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Failed to allocate memory for priority queue: "
.LC1:
.string "Failed to allocate memory for values: "
.LC2:
.string "Failed to allocate memory for result: "
.LC3:
.string "Failed to copy priority queue to device: "
.LC4:
.string "Failed to copy values to device: "
.LC5:
.string "Failed to launch insertIntoPQ kernel: "
.LC6:
.string "Failed to launch extractMinFromPQ kernel: "
.LC7:
.string "Failed to copy result from device: "
.LC8:
.string "Minimum value extracted from the priority queue: "
.section .text.startup,"ax",@progbits
.globl main
.type main, @function
main:
.LFB6832:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $320, %rsp
.cfi_def_cfa_offset 352
movq %fs:40, %rax
movq %rax, 312(%rsp)
xorl %eax, %eax
leaq 56(%rsp), %r12
.L15:
movl $2147483647, (%r12,%rax,4)
incq %rax
cmpq $32, %rax
jne .L15
xorl %eax, %eax
movl $32, %ecx
.L16:
movl %ecx, %edx
leaq 184(%rsp), %rbp
subl %eax, %edx
movl %edx, 0(%rbp,%rax,4)
incq %rax
cmpq $32, %rax
jne .L16
movl $128, %esi
leaq 8(%rsp), %rdi
call cudaMalloc@PLT
leaq .LC0(%rip), %rsi
movl %eax, %ebx
testl %eax, %eax
jne .L33
leaq 16(%rsp), %rdi
movl $128, %esi
call cudaMalloc@PLT
movl %eax, %ebx
testl %eax, %eax
je .L19
leaq .LC1(%rip), %rsi
.L33:
leaq _ZSt4cerr(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movl %ebx, %edi
movq %rax, %rbp
call cudaGetErrorString@PLT
movq %rbp, %rdi
movq %rax, %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@GOTPCREL(%rip), %rsi
movq %rax, %rdi
call _ZNSolsEPFRSoS_E.isra.0
orl $-1, %eax
jmp .L14
.L19:
movl $4, %esi
leaq 24(%rsp), %rdi
call cudaMalloc@PLT
leaq .LC2(%rip), %rsi
movl %eax, %ebx
testl %eax, %eax
jne .L33
movq 8(%rsp), %rdi
movq %r12, %rsi
movl $1, %ecx
movl $128, %edx
call cudaMemcpy@PLT
leaq .LC3(%rip), %rsi
movl %eax, %ebx
testl %eax, %eax
jne .L33
movq 16(%rsp), %rdi
movq %rbp, %rsi
movl $1, %ecx
movl $128, %edx
call cudaMemcpy@PLT
leaq .LC4(%rip), %rsi
movl %eax, %ebx
testl %eax, %eax
jne .L33
movl $134217729, %edx
xorl %r9d, %r9d
xorl %r8d, %r8d
movl $1, %ecx
salq $5, %rdx
movl $1, %esi
movabsq $4294967297, %rdi
movl $1, 52(%rsp)
movq %rdx, 44(%rsp)
movq %rdi, 32(%rsp)
movl $1, 40(%rsp)
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L24
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
movl $32, %edx
call _Z35__device_stub__Z12insertIntoPQPiS_iPiS_i
.L24:
call cudaGetLastError@PLT
leaq .LC5(%rip), %rsi
movl %eax, %ebx
testl %eax, %eax
jne .L33
movl $134217729, %edx
xorl %r9d, %r9d
xorl %r8d, %r8d
movl $1, %ecx
salq $5, %rdx
movl $1, %esi
movabsq $4294967297, %rdi
movl $1, 52(%rsp)
movq %rdx, 44(%rsp)
movq %rdi, 32(%rsp)
movl $1, 40(%rsp)
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L26
movq 24(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z38__device_stub__Z16extractMinFromPQPiS_PiS_
.L26:
call cudaGetLastError@PLT
leaq .LC6(%rip), %rsi
movl %eax, %ebx
testl %eax, %eax
jne .L33
movq 24(%rsp), %rsi
leaq 44(%rsp), %rdi
movl $2, %ecx
movl $4, %edx
call cudaMemcpy@PLT
leaq .LC7(%rip), %rsi
movl %eax, %ebx
testl %eax, %eax
jne .L33
leaq .LC8(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movl 44(%rsp), %esi
movq %rax, %rdi
call _ZNSolsEi@PLT
movq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@GOTPCREL(%rip), %rsi
movq %rax, %rdi
call _ZNSolsEPFRSoS_E.isra.0
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
xorl %eax, %eax
.L14:
movq 312(%rsp), %rdx
subq %fs:40, %rdx
je .L29
call __stack_chk_fail@PLT
.L29:
addq $320, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE6832:
.size main, .-main
.section .rodata.str1.1
.LC9:
.string "_Z16extractMinFromPQPiS_"
.LC10:
.string "_Z12insertIntoPQPiS_i"
.LC11:
.string "_ZN50_INTERNAL_62b287de_19_cuda_code_085996_cu_7623083c4cuda3std3__419piecewise_constructE"
.LC12:
.string "_ZN50_INTERNAL_62b287de_19_cuda_code_085996_cu_7623083c4cuda3std6ranges3__45__cpo4swapE"
.LC13:
.string "_ZN50_INTERNAL_62b287de_19_cuda_code_085996_cu_7623083c4cuda3std6ranges3__45__cpo9iter_moveE"
.section .text.startup
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB6862:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
pushq $0
.cfi_def_cfa_offset 24
xorl %r9d, %r9d
orl $-1, %r8d
pushq $0
.cfi_def_cfa_offset 32
leaq .LC9(%rip), %rdx
movq %rax, %rdi
movq %rax, %rbx
pushq $0
.cfi_def_cfa_offset 40
movq %rdx, %rcx
leaq _Z16extractMinFromPQPiS_(%rip), %rsi
pushq $0
.cfi_def_cfa_offset 48
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq %rbx, %rdi
xorl %r9d, %r9d
pushq $0
.cfi_def_cfa_offset 24
leaq .LC10(%rip), %rdx
orl $-1, %r8d
leaq _Z12insertIntoPQPiS_i(%rip), %rsi
pushq $0
.cfi_def_cfa_offset 32
movq %rdx, %rcx
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq %rbx, %rdi
xorl %r8d, %r8d
pushq $0
.cfi_def_cfa_offset 24
leaq .LC11(%rip), %rdx
movl $1, %r9d
leaq _ZN4cuda3std3__419piecewise_constructE(%rip), %rsi
pushq $0
.cfi_def_cfa_offset 32
movq %rdx, %rcx
call __cudaRegisterVar@PLT
popq %rax
.cfi_def_cfa_offset 24
popq %rdx
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
leaq .LC12(%rip), %rdx
movq %rbx, %rdi
xorl %r8d, %r8d
movq %rdx, %rcx
movl $1, %r9d
leaq _ZN4cuda3std6ranges3__45__cpo4swapE(%rip), %rsi
call __cudaRegisterVar@PLT
popq %rcx
.cfi_def_cfa_offset 24
popq %rsi
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
leaq .LC13(%rip), %rdx
movq %rbx, %rdi
xorl %r8d, %r8d
movl $1, %r9d
movq %rdx, %rcx
leaq _ZN4cuda3std6ranges3__45__cpo9iter_moveE(%rip), %rsi
call __cudaRegisterVar@PLT
popq %rdi
.cfi_def_cfa_offset 24
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
popq %r8
.cfi_def_cfa_offset 16
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit@PLT
.cfi_endproc
.LFE6862:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.weak _ZN4cuda3std3__419piecewise_constructE
.section .rodata._ZN4cuda3std3__419piecewise_constructE,"aG",@progbits,_ZN4cuda3std3__419piecewise_constructE,comdat
.type _ZN4cuda3std3__419piecewise_constructE, @gnu_unique_object
.size _ZN4cuda3std3__419piecewise_constructE, 1
_ZN4cuda3std3__419piecewise_constructE:
.zero 1
.weak _ZN4cuda3std6ranges3__45__cpo9iter_moveE
.section .rodata._ZN4cuda3std6ranges3__45__cpo9iter_moveE,"aG",@progbits,_ZN4cuda3std6ranges3__45__cpo9iter_moveE,comdat
.type _ZN4cuda3std6ranges3__45__cpo9iter_moveE, @gnu_unique_object
.size _ZN4cuda3std6ranges3__45__cpo9iter_moveE, 1
_ZN4cuda3std6ranges3__45__cpo9iter_moveE:
.zero 1
.weak _ZN4cuda3std6ranges3__45__cpo4swapE
.section .rodata._ZN4cuda3std6ranges3__45__cpo4swapE,"aG",@progbits,_ZN4cuda3std6ranges3__45__cpo4swapE,comdat
.type _ZN4cuda3std6ranges3__45__cpo4swapE, @gnu_unique_object
.size _ZN4cuda3std6ranges3__45__cpo4swapE, 1
_ZN4cuda3std6ranges3__45__cpo4swapE:
.zero 1
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
```
|
```amdasm
.text
.file "cuda_code_085996.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z27__device_stub__insertIntoPQPiS_i # -- Begin function _Z27__device_stub__insertIntoPQPiS_i
.type _Z27__device_stub__insertIntoPQPiS_i,@function
_Z27__device_stub__insertIntoPQPiS_i: # @_Z27__device_stub__insertIntoPQPiS_i
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $112, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 40(%rsp), %rax
movq %rdi, (%rax)
leaq 32(%rsp), %rcx
movq %rsi, (%rcx)
leaq 12(%rsp), %rsi
movl %edx, (%rsi)
leaq 80(%rsp), %rbx
movq %rax, (%rbx)
movq %rcx, 8(%rbx)
movq %rsi, 16(%rbx)
leaq 64(%rsp), %r14
leaq 48(%rsp), %r15
leaq 24(%rsp), %r12
leaq 16(%rsp), %r13
movq %r14, %rdi
movq %r15, %rsi
movq %r12, %rdx
movq %r13, %rcx
callq __hipPopCallConfiguration
movq (%r14), %rsi
movl 8(%r14), %edx
movq (%r15), %rcx
movl 8(%r15), %r8d
movl $_Z12insertIntoPQPiS_i, %edi
movq %rbx, %r9
pushq (%r13)
.cfi_adjust_cfa_offset 8
pushq (%r12)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $128, %rsp
.cfi_adjust_cfa_offset -128
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z27__device_stub__insertIntoPQPiS_i, .Lfunc_end0-_Z27__device_stub__insertIntoPQPiS_i
.cfi_endproc
# -- End function
.globl _Z31__device_stub__extractMinFromPQPiS_ # -- Begin function _Z31__device_stub__extractMinFromPQPiS_
.type _Z31__device_stub__extractMinFromPQPiS_,@function
_Z31__device_stub__extractMinFromPQPiS_: # @_Z31__device_stub__extractMinFromPQPiS_
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $80, %rsp
.cfi_def_cfa_offset 128
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 24(%rsp), %rax
movq %rdi, (%rax)
leaq 16(%rsp), %rcx
movq %rsi, (%rcx)
leaq 64(%rsp), %rbx
movq %rax, (%rbx)
movq %rcx, 8(%rbx)
leaq 48(%rsp), %r14
leaq 32(%rsp), %r15
leaq 8(%rsp), %r12
movq %rsp, %r13
movq %r14, %rdi
movq %r15, %rsi
movq %r12, %rdx
movq %r13, %rcx
callq __hipPopCallConfiguration
movq (%r14), %rsi
movl 8(%r14), %edx
movq (%r15), %rcx
movl 8(%r15), %r8d
movl $_Z16extractMinFromPQPiS_, %edi
movq %rbx, %r9
pushq (%r13)
.cfi_adjust_cfa_offset 8
pushq (%r12)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $96, %rsp
.cfi_adjust_cfa_offset -96
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z31__device_stub__extractMinFromPQPiS_, .Lfunc_end1-_Z31__device_stub__extractMinFromPQPiS_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $288, %rsp # imm = 0x120
.cfi_def_cfa_offset 320
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %rbp, -16
xorl %eax, %eax
.LBB2_1: # =>This Inner Loop Header: Depth=1
movl $2147483647, 160(%rsp,%rax,4) # imm = 0x7FFFFFFF
incq %rax
cmpq $32, %rax
jne .LBB2_1
# %bb.2: # %.preheader.preheader
movl $32, %eax
leaq 32(%rsp), %rcx
.LBB2_3: # %.preheader
# =>This Inner Loop Header: Depth=1
movl %eax, (%rcx)
addq $4, %rcx
decq %rax
jne .LBB2_3
# %bb.4:
movq %rsp, %rdi
movl $128, %esi
callq hipMalloc
testl %eax, %eax
je .LBB2_6
# %bb.5:
movl %eax, %ebx
movl $_ZSt4cerr, %edi
movl $.L.str, %esi
movl $46, %edx
jmp .LBB2_11
.LBB2_6:
leaq 16(%rsp), %rdi
movl $128, %esi
callq hipMalloc
testl %eax, %eax
je .LBB2_8
# %bb.7:
movl %eax, %ebx
movl $_ZSt4cerr, %edi
movl $.L.str.1, %esi
jmp .LBB2_10
.LBB2_8:
leaq 8(%rsp), %rdi
movl $4, %esi
callq hipMalloc
testl %eax, %eax
je .LBB2_17
# %bb.9:
movl %eax, %ebx
movl $_ZSt4cerr, %edi
movl $.L.str.2, %esi
.LBB2_10:
movl $38, %edx
.LBB2_11:
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl %ebx, %edi
callq hipGetErrorString
testq %rax, %rax
je .LBB2_13
# %bb.12:
movq %rax, %rbx
movq %rax, %rdi
callq strlen
movl $_ZSt4cerr, %edi
movq %rbx, %rsi
movq %rax, %rdx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
jmp .LBB2_14
.LBB2_13:
movq _ZSt4cerr(%rip), %rax
movq -24(%rax), %rax
leaq _ZSt4cerr(%rax), %rdi
movl 32(%rdi), %esi
orl $1, %esi
callq _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate
.LBB2_14: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit
movq _ZSt4cerr(%rip), %rax
movl $_ZSt4cerr, %ecx
movq -24(%rax), %rdi
addq %rcx, %rdi
movl $10, %esi
callq _ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
movsbl %al, %esi
movl $_ZSt4cerr, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
.LBB2_15:
movl $-1, %eax
.LBB2_16:
addq $288, %rsp # imm = 0x120
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB2_17:
.cfi_def_cfa_offset 320
movq (%rsp), %rdi
leaq 160(%rsp), %rsi
movl $128, %edx
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
je .LBB2_19
# %bb.18:
movl %eax, %ebx
movl $_ZSt4cerr, %edi
movl $.L.str.3, %esi
movl $41, %edx
jmp .LBB2_11
.LBB2_19:
movq 16(%rsp), %rdi
leaq 32(%rsp), %rsi
movl $128, %edx
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
je .LBB2_22
# %bb.20:
movl %eax, %ebx
movl $_ZSt4cerr, %edi
movl $.L.str.4, %esi
movl $33, %edx
.LBB2_21:
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl %ebx, %edi
jmp .LBB2_26
.LBB2_22:
movabsq $4294967297, %r14 # imm = 0x100000001
leaq 31(%r14), %rbx
movq %r14, %rdi
movl $1, %esi
movq %rbx, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_24
# %bb.23:
movq (%rsp), %rdi
movq 16(%rsp), %rsi
movl $32, %edx
callq _Z27__device_stub__insertIntoPQPiS_i
.LBB2_24:
callq hipGetLastError
testl %eax, %eax
je .LBB2_27
# %bb.25:
movl %eax, %ebp
movl $_ZSt4cerr, %edi
movl $.L.str.5, %esi
movl $38, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl %ebp, %edi
.LBB2_26:
callq hipGetErrorString
movl $_ZSt4cerr, %edi
movq %rax, %rsi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movq %rax, %rdi
callq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_
jmp .LBB2_15
.LBB2_27:
movq %r14, %rdi
movl $1, %esi
movq %rbx, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_29
# %bb.28:
movq (%rsp), %rdi
movq 8(%rsp), %rsi
callq _Z31__device_stub__extractMinFromPQPiS_
.LBB2_29:
callq hipGetLastError
testl %eax, %eax
je .LBB2_31
# %bb.30:
movl %eax, %ebx
movl $_ZSt4cerr, %edi
movl $.L.str.6, %esi
movl $42, %edx
jmp .LBB2_21
.LBB2_31:
movq 8(%rsp), %rsi
leaq 28(%rsp), %rdi
movl $4, %edx
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
je .LBB2_33
# %bb.32:
movl %eax, %ebx
movl $_ZSt4cerr, %edi
movl $.L.str.7, %esi
movl $35, %edx
jmp .LBB2_21
.LBB2_33:
movl $_ZSt4cout, %edi
movl $.L.str.8, %esi
movl $49, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl 28(%rsp), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movq %rax, %rdi
callq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_
movq (%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
xorl %eax, %eax
jmp .LBB2_16
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
movq __hip_gpubin_handle(%rip), %rbx
testq %rbx, %rbx
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, %rbx
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12insertIntoPQPiS_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z16extractMinFromPQPiS_, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z12insertIntoPQPiS_i,@object # @_Z12insertIntoPQPiS_i
.section .rodata,"a",@progbits
.globl _Z12insertIntoPQPiS_i
.p2align 3, 0x0
_Z12insertIntoPQPiS_i:
.quad _Z27__device_stub__insertIntoPQPiS_i
.size _Z12insertIntoPQPiS_i, 8
.type _Z16extractMinFromPQPiS_,@object # @_Z16extractMinFromPQPiS_
.globl _Z16extractMinFromPQPiS_
.p2align 3, 0x0
_Z16extractMinFromPQPiS_:
.quad _Z31__device_stub__extractMinFromPQPiS_
.size _Z16extractMinFromPQPiS_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Failed to allocate memory for priority queue: "
.size .L.str, 47
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Failed to allocate memory for values: "
.size .L.str.1, 39
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Failed to allocate memory for result: "
.size .L.str.2, 39
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Failed to copy priority queue to device: "
.size .L.str.3, 42
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Failed to copy values to device: "
.size .L.str.4, 34
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "Failed to launch insertIntoPQ kernel: "
.size .L.str.5, 39
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "Failed to launch extractMinFromPQ kernel: "
.size .L.str.6, 43
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "Failed to copy result from device: "
.size .L.str.7, 36
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "Minimum value extracted from the priority queue: "
.size .L.str.8, 50
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z12insertIntoPQPiS_i"
.size .L__unnamed_1, 22
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z16extractMinFromPQPiS_"
.size .L__unnamed_2, 25
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z27__device_stub__insertIntoPQPiS_i
.addrsig_sym _Z31__device_stub__extractMinFromPQPiS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z12insertIntoPQPiS_i
.addrsig_sym _Z16extractMinFromPQPiS_
.addrsig_sym _ZSt4cerr
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
```
| 6,171 | 6,352 |
113,662 |
Convert the following CUDA device assembly code to AMD device assembly:
```cudaasm
code for sm_80
Function : _Z18convBackpropKernelPfS_S_iiiiiiii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ;
S2R R0, SR_TID.Y ;
S2R R2, SR_TID.X ;
ISETP.GE.AND P0, PT, R0, c[0x0][0x188], PT ;
ISETP.GE.OR P0, PT, R2, c[0x0][0x184], P0 ;
@P0 EXIT ;
IABS R9, c[0x0][0x190] ;
IMAD.MOV.U32 R6, RZ, RZ, c[0x0][0x17c] ;
ULDC UR4, c[0x0][0x178] ;
IMAD.MOV.U32 R7, RZ, RZ, c[0x0][0x194] ;
I2F.RP R3, R9 ;
ULDC UR5, c[0x0][0x184] ;
IADD3 R6, R6, -c[0x0][0x188], RZ ;
UIADD3 UR4, UR4, -UR5, URZ ;
ULDC.64 UR8, c[0x0][0x118] ;
IMAD R6, R7, 0x2, R6 ;
IABS R10, R6 ;
LOP3.LUT R6, R6, c[0x0][0x190], RZ, 0x3c, !PT ;
MUFU.RCP R3, R3 ;
IADD3 R4, R3, 0xffffffe, RZ ;
LEA R3, R7, UR4, 0x1 ;
F2I.FTZ.U32.TRUNC.NTZ R5, R4 ;
IMAD.MOV.U32 R4, RZ, RZ, RZ ;
IMAD.MOV R8, RZ, RZ, -R5 ;
IMAD R7, R8, R9, RZ ;
IABS R8, R3 ;
LOP3.LUT R3, R3, c[0x0][0x190], RZ, 0x3c, !PT ;
IMAD.HI.U32 R4, R5, R7, R4 ;
ISETP.GE.AND P3, PT, R3, RZ, PT ;
S2R R3, SR_CTAID.Y ;
IMAD.HI.U32 R5, R4, R8, RZ ;
IMAD.HI.U32 R7, R4, R10, RZ ;
IMAD.MOV R4, RZ, RZ, -R5 ;
IMAD.MOV R11, RZ, RZ, -R7 ;
IMAD R4, R9.reuse, R4, R8 ;
IMAD R8, R9, R11, R10 ;
ISETP.GT.U32.AND P2, PT, R9.reuse, R4, PT ;
ISETP.GT.U32.AND P4, PT, R9, R8, PT ;
@!P2 IMAD.IADD R4, R4, 0x1, -R9.reuse ;
@!P2 IADD3 R5, R5, 0x1, RZ ;
@!P4 IMAD.IADD R8, R8, 0x1, -R9 ;
ISETP.GE.AND P2, PT, R6, RZ, PT ;
ISETP.GE.U32.AND P0, PT, R4, R9.reuse, PT ;
ISETP.GE.U32.AND P1, PT, R8, R9, PT ;
S2R R4, SR_CTAID.Z ;
@!P4 IADD3 R7, R7, 0x1, RZ ;
LOP3.LUT R6, RZ, c[0x0][0x190], RZ, 0x33, !PT ;
@P0 IADD3 R5, R5, 0x1, RZ ;
@P1 IADD3 R7, R7, 0x1, RZ ;
ISETP.NE.AND P0, PT, RZ, c[0x0][0x190], PT ;
@!P3 IMAD.MOV R5, RZ, RZ, -R5 ;
@!P2 IMAD.MOV R7, RZ, RZ, -R7 ;
SEL R5, R6.reuse, R5, !P0 ;
SEL R6, R6, R7, !P0 ;
IMAD.MOV.U32 R7, RZ, RZ, RZ ;
ISETP.GE.AND P0, PT, R5, RZ, PT ;
ISETP.LT.OR P0, PT, R6, RZ, !P0 ;
@P0 BRA 0xb70 ;
S2R R12, SR_CTAID.X ;
IADD3 R8, R5, 0x1, RZ ;
IMAD.MOV.U32 R7, RZ, RZ, RZ ;
IADD3 R11, R6, 0x1, RZ ;
UMOV UR4, URZ ;
LOP3.LUT R9, R8, 0x3, RZ, 0xc0, !PT ;
IMAD.IADD R18, R8, 0x1, -R9 ;
IMAD R10, R12, c[0x0][0x18c], R4 ;
IMAD R10, R10, R11, RZ ;
IMAD R11, R12, c[0x0][0x180], R3 ;
ISETP.GE.U32.AND P0, PT, R5, 0x3, PT ;
ULDC.64 UR6, c[0x0][0x190] ;
IADD3 R13, R10, UR4, RZ ;
UIMAD UR5, UR4, UR6, -UR7 ;
ISETP.NE.AND P5, PT, R9, RZ, PT ;
IMAD.MOV.U32 R23, RZ, RZ, RZ ;
UMOV UR6, UR4 ;
IMAD R26, R8, R13, RZ ;
UIADD3 UR4, UR4, 0x1, URZ ;
IADD3 R22, R0, UR5, RZ ;
ISETP.LE.AND P4, PT, R6, UR6, PT ;
IMAD R19, R11, c[0x0][0x17c], R22 ;
@!P0 BRA 0x850 ;
ISETP.GE.AND P6, PT, R22, c[0x0][0x17c], PT ;
IMAD.MOV.U32 R23, RZ, RZ, RZ ;
IMAD.MOV.U32 R24, RZ, RZ, R18 ;
IMAD.MOV.U32 R12, RZ, RZ, c[0x0][0x194] ;
IMAD.MOV.U32 R20, RZ, RZ, 0x4 ;
IMAD R13, R23, c[0x0][0x190], -R12 ;
IMAD.IADD R15, R13, 0x1, R2 ;
IMAD.IADD R13, R26, 0x1, R23 ;
LOP3.LUT R12, R15, R22, RZ, 0xfc, !PT ;
ISETP.LT.OR P0, PT, R12, RZ, P6 ;
IMAD.WIDE R12, R13, R20, c[0x0][0x170] ;
ISETP.GE.OR P0, PT, R15, c[0x0][0x178], P0 ;
@!P0 IMAD R15, R19, c[0x0][0x178], R15 ;
@!P0 LDG.E R16, [R12.64] ;
@!P0 IMAD.WIDE R14, R15, R20, c[0x0][0x160] ;
@!P0 LDG.E R14, [R14.64] ;
IMAD.MOV.U32 R28, RZ, RZ, c[0x0][0x190] ;
IMAD R25, R23, R28, c[0x0][0x190] ;
IADD3 R17, R2.reuse, -c[0x0][0x194], R25 ;
IADD3 R27, R25, c[0x0][0x190], RZ ;
LOP3.LUT R21, R17, R22.reuse, RZ, 0xfc, !PT ;
IADD3 R25, R2, -c[0x0][0x194], R27 ;
ISETP.LT.OR P1, PT, R21, RZ, P6 ;
LOP3.LUT R21, R25, R22, RZ, 0xfc, !PT ;
IADD3 R27, R27, c[0x0][0x190], RZ ;
ISETP.LT.OR P2, PT, R21, RZ, P6 ;
IADD3 R21, R2, -c[0x0][0x194], R27 ;
ISETP.GE.OR P1, PT, R17, c[0x0][0x178], P1 ;
LOP3.LUT R15, R21, R22, RZ, 0xfc, !PT ;
ISETP.GE.OR P2, PT, R25, c[0x0][0x178], P2 ;
ISETP.LT.OR P3, PT, R15, RZ, P6 ;
ISETP.GE.OR P3, PT, R21, c[0x0][0x178], P3 ;
@!P1 IMAD R15, R19, c[0x0][0x178], R17 ;
@!P2 IMAD R17, R19.reuse, c[0x0][0x178], R25 ;
@!P2 LDG.E R28, [R12.64+0x8] ;
@!P1 LDG.E R25, [R12.64+0x4] ;
@!P3 IMAD R21, R19, c[0x0][0x178], R21 ;
@!P3 LDG.E R27, [R12.64+0xc] ;
@!P0 FFMA R7, R16, R14, R7 ;
@!P1 IMAD.WIDE R14, R15, R20, c[0x0][0x160] ;
@!P2 IMAD.WIDE R16, R17, R20.reuse, c[0x0][0x160] ;
@!P1 LDG.E R14, [R14.64] ;
@!P3 IMAD.WIDE R20, R21, R20, c[0x0][0x160] ;
@!P2 LDG.E R16, [R16.64] ;
@!P3 LDG.E R20, [R20.64] ;
IADD3 R24, R24, -0x4, RZ ;
ISETP.NE.AND P0, PT, R24, RZ, PT ;
IADD3 R23, R23, 0x4, RZ ;
@!P1 FFMA R7, R25, R14, R7 ;
@!P2 FFMA R7, R28, R16, R7 ;
@!P3 FFMA R7, R27, R20, R7 ;
@P0 BRA 0x540 ;
@!P5 BRA 0xb60 ;
IMAD.MOV.U32 R24, RZ, RZ, c[0x0][0x190] ;
ISETP.GE.AND P0, PT, R22, c[0x0][0x17c], PT ;
IMAD.MOV.U32 R16, RZ, RZ, 0x4 ;
BSSY B0, 0x990 ;
IMAD R13, R23, R24, -c[0x0][0x194] ;
ISETP.NE.AND P2, PT, R9, 0x1, PT ;
IMAD.IADD R15, R13, 0x1, R2 ;
IMAD.IADD R13, R26, 0x1, R23 ;
LOP3.LUT R12, R15, R22, RZ, 0xfc, !PT ;
ISETP.LT.OR P1, PT, R12, RZ, P0 ;
IMAD.WIDE R12, R13, R16, c[0x0][0x170] ;
ISETP.GE.OR P1, PT, R15, c[0x0][0x178], P1 ;
@P1 BRA 0x980 ;
IMAD R15, R19, c[0x0][0x178], R15 ;
LDG.E R20, [R12.64] ;
IMAD.WIDE R14, R15, R16, c[0x0][0x160] ;
LDG.E R14, [R14.64] ;
FFMA R7, R20, R14, R7 ;
BSYNC B0 ;
@!P2 BRA 0xb60 ;
IMAD R23, R23, R24, c[0x0][0x190] ;
BSSY B0, 0xa80 ;
ISETP.NE.AND P2, PT, R9, 0x2, PT ;
IADD3 R15, R2, -c[0x0][0x194], R23 ;
LOP3.LUT R14, R15, R22, RZ, 0xfc, !PT ;
ISETP.LT.OR P1, PT, R14, RZ, P0 ;
ISETP.GE.OR P1, PT, R15, c[0x0][0x178], P1 ;
@P1 BRA 0xa70 ;
IMAD R15, R19, c[0x0][0x178], R15 ;
LDG.E R20, [R12.64+0x4] ;
IMAD.WIDE R14, R15, R16, c[0x0][0x160] ;
LDG.E R14, [R14.64] ;
FFMA R7, R20, R14, R7 ;
BSYNC B0 ;
@!P2 BRA 0xb60 ;
IADD3 R15, R23, c[0x0][0x190], RZ ;
BSSY B0, 0xb60 ;
IADD3 R15, R2, -c[0x0][0x194], R15 ;
LOP3.LUT R22, R15, R22, RZ, 0xfc, !PT ;
ISETP.LT.OR P0, PT, R22, RZ, P0 ;
ISETP.GE.OR P0, PT, R15, c[0x0][0x178], P0 ;
@P0 BRA 0xb50 ;
IMAD R17, R19, c[0x0][0x178], R15 ;
LDG.E R12, [R12.64+0x8] ;
IMAD.WIDE R16, R17, R16, c[0x0][0x160] ;
LDG.E R16, [R16.64] ;
FFMA R7, R12, R16, R7 ;
BSYNC B0 ;
@!P4 BRA 0x440 ;
IMAD R3, R4, c[0x0][0x180], R3 ;
IMAD R3, R3, c[0x0][0x188], R0 ;
IMAD.MOV.U32 R0, RZ, RZ, 0x4 ;
IMAD R3, R3, c[0x0][0x184], R2 ;
IMAD.WIDE R2, R3, R0, c[0x0][0x168] ;
RED.E.ADD.F32.FTZ.RN.STRONG.GPU [R2.64], R7 ;
EXIT ;
BRA 0xbe0;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
```
|
```amdasm
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z18convBackpropKernelPfS_S_iiiiiiii ; -- Begin function _Z18convBackpropKernelPfS_S_iiiiiiii
.globl _Z18convBackpropKernelPfS_S_iiiiiiii
.p2align 8
.type _Z18convBackpropKernelPfS_S_iiiiiiii,@function
_Z18convBackpropKernelPfS_S_iiiiiiii: ; @_Z18convBackpropKernelPfS_S_iiiiiiii
; %bb.0:
s_load_b256 s[4:11], s[0:1], 0x18
v_bfe_u32 v1, v0, 10, 10
v_and_b32_e32 v0, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_gt_i32_e32 vcc_lo, s8, v1
v_cmp_gt_i32_e64 s2, s7, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, s2, vcc_lo
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_14
; %bb.1:
s_ashr_i32 s12, s10, 31
s_lshl_b32 s23, s11, 1
s_add_i32 s2, s10, s12
s_sub_i32 s3, s5, s8
s_xor_b32 s2, s2, s12
s_add_i32 s3, s3, s23
v_cvt_f32_u32_e32 v2, s2
s_sub_i32 s16, 0, s2
s_ashr_i32 s22, s3, 31
v_mov_b32_e32 v4, 0
s_add_i32 s3, s3, s22
v_rcp_iflag_f32_e32 v2, v2
s_xor_b32 s3, s3, s22
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v2, 0x4f7ffffe, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_u32_f32_e32 v2, v2
v_readfirstlane_b32 s24, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s16, s16, s24
s_mul_hi_u32 s16, s24, s16
s_delay_alu instid0(SALU_CYCLE_1)
s_add_i32 s24, s24, s16
s_clause 0x1
s_load_b128 s[16:19], s[0:1], 0x0
s_load_b64 s[20:21], s[0:1], 0x10
s_mul_hi_u32 s25, s3, s24
s_xor_b32 s1, s22, s12
s_mul_i32 s0, s25, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_sub_i32 s0, s3, s0
s_add_i32 s3, s25, 1
s_sub_i32 s22, s0, s2
s_cmp_ge_u32 s0, s2
s_cselect_b32 s3, s3, s25
s_cselect_b32 s0, s22, s0
s_add_i32 s22, s3, 1
s_cmp_ge_u32 s0, s2
s_cselect_b32 s0, s22, s3
s_mov_b32 s22, 0
s_xor_b32 s0, s0, s1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_sub_i32 s3, s0, s1
s_cmp_lt_i32 s3, 0
s_cbranch_scc1 .LBB0_12
; %bb.2: ; %.preheader.lr.ph
s_sub_i32 s0, s4, s7
v_mov_b32_e32 v4, 0
s_add_i32 s0, s0, s23
s_mul_i32 s25, s10, s4
s_ashr_i32 s1, s0, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s0, s0, s1
s_xor_b32 s0, s0, s1
s_xor_b32 s1, s1, s12
s_mul_hi_u32 s23, s0, s24
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
s_mul_i32 s24, s23, s2
s_add_i32 s12, s23, 1
s_sub_i32 s0, s0, s24
s_sub_i32 s24, s0, s2
s_cmp_ge_u32 s0, s2
s_cselect_b32 s12, s12, s23
s_cselect_b32 s0, s24, s0
s_add_i32 s23, s12, 1
s_cmp_ge_u32 s0, s2
s_cselect_b32 s0, s23, s12
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_xor_b32 s0, s0, s1
s_sub_i32 s0, s0, s1
s_add_i32 s1, s3, 1
s_add_i32 s23, s0, 1
s_cmp_gt_i32 s0, -1
s_mul_i32 s0, s13, s6
s_cselect_b32 s24, -1, 0
s_add_i32 s0, s0, s14
s_mul_i32 s1, s1, s23
v_mad_u64_u32 v[2:3], null, s0, s5, v[1:2]
s_mul_i32 s0, s13, s9
v_subrev_nc_u32_e32 v3, s11, v0
s_add_i32 s0, s0, s15
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
s_mul_i32 s9, s1, s0
v_subrev_nc_u32_e32 v2, s11, v2
s_delay_alu instid0(VALU_DEP_1)
v_mul_lo_u32 v2, s4, v2
.LBB0_3: ; %.preheader
; =>This Loop Header: Depth=1
; Child Loop BB0_5 Depth 2
s_and_not1_b32 vcc_lo, exec_lo, s24
s_cbranch_vccnz .LBB0_10
; %bb.4: ; %.lr.ph
; in Loop: Header=BB0_3 Depth=1
s_mul_i32 s0, s22, s10
s_mov_b32 s12, s9
s_sub_i32 s0, s0, s11
s_mov_b32 s26, s23
v_add_nc_u32_e32 v5, s0, v1
s_delay_alu instid0(VALU_DEP_1)
v_cmp_lt_i32_e32 vcc_lo, -1, v5
v_cmp_gt_i32_e64 s0, s5, v5
v_mov_b32_e32 v5, v3
.LBB0_5: ; Parent Loop BB0_3 Depth=1
; => This Inner Loop Header: Depth=2
s_and_saveexec_b32 s27, vcc_lo
s_cbranch_execz .LBB0_9
; %bb.6: ; in Loop: Header=BB0_5 Depth=2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cmp_lt_i32_e64 s1, -1, v5
v_cmp_gt_i32_e64 s2, s4, v5
s_and_b32 s1, s0, s1
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
s_and_b32 s1, s1, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s2, s1
s_cbranch_execz .LBB0_8
; %bb.7: ; in Loop: Header=BB0_5 Depth=2
v_add_nc_u32_e32 v6, v2, v5
s_ashr_i32 s13, s12, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
s_lshl_b64 s[28:29], s[12:13], 2
s_waitcnt lgkmcnt(0)
s_add_u32 s28, s20, s28
v_ashrrev_i32_e32 v7, 31, v6
s_addc_u32 s29, s21, s29
v_lshlrev_b64 v[6:7], 2, v[6:7]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v6, s1, s16, v6
v_add_co_ci_u32_e64 v7, s1, s17, v7, s1
s_load_b32 s1, s[28:29], 0x0
global_load_b32 v6, v[6:7], off
s_waitcnt vmcnt(0) lgkmcnt(0)
v_fmac_f32_e32 v4, s1, v6
.LBB0_8: ; %Flow148
; in Loop: Header=BB0_5 Depth=2
s_or_b32 exec_lo, exec_lo, s2
.LBB0_9: ; in Loop: Header=BB0_5 Depth=2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_or_b32 exec_lo, exec_lo, s27
v_add_nc_u32_e32 v5, s10, v5
s_add_i32 s26, s26, -1
s_add_i32 s12, s12, 1
s_cmp_eq_u32 s26, 0
s_cbranch_scc0 .LBB0_5
.LBB0_10: ; %._crit_edge
; in Loop: Header=BB0_3 Depth=1
s_delay_alu instid0(VALU_DEP_1)
v_add_nc_u32_e32 v2, s25, v2
s_add_i32 s0, s22, 1
s_add_i32 s9, s9, s23
s_cmp_eq_u32 s22, s3
s_cbranch_scc1 .LBB0_12
; %bb.11: ; in Loop: Header=BB0_3 Depth=1
s_mov_b32 s22, s0
s_branch .LBB0_3
.LBB0_12: ; %._crit_edge105
s_mul_i32 s0, s15, s6
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s0, s0, s14
v_mad_u64_u32 v[2:3], null, s0, s8, v[1:2]
s_mov_b32 s0, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[5:6], null, v2, s7, v[0:1]
v_ashrrev_i32_e32 v6, 31, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[5:6]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s18, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s19, v1, vcc_lo
global_load_b32 v3, v[0:1], off
.LBB0_13: ; %atomicrmw.start
; =>This Inner Loop Header: Depth=1
s_waitcnt vmcnt(0)
v_add_f32_e32 v2, v3, v4
global_atomic_cmpswap_b32 v2, v[0:1], v[2:3], off glc
s_waitcnt vmcnt(0)
v_cmp_eq_u32_e32 vcc_lo, v2, v3
v_mov_b32_e32 v3, v2
s_or_b32 s0, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s0
s_cbranch_execnz .LBB0_13
.LBB0_14:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z18convBackpropKernelPfS_S_iiiiiiii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 56
.amdhsa_user_sgpr_count 13
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 1
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 30
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z18convBackpropKernelPfS_S_iiiiiiii, .Lfunc_end0-_Z18convBackpropKernelPfS_S_iiiiiiii
; -- End function
.section .AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 796
; NumSgprs: 32
; NumVgprs: 8
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 3
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 32
; NumVGPRsForWavesPerEU: 8
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 13
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 1
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object ; @__hip_cuid_
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0 ; 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 36
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: by_value
- .offset: 44
.size: 4
.value_kind: by_value
- .offset: 48
.size: 4
.value_kind: by_value
- .offset: 52
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 56
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z18convBackpropKernelPfS_S_iiiiiiii
.private_segment_fixed_size: 0
.sgpr_count: 32
.sgpr_spill_count: 0
.symbol: _Z18convBackpropKernelPfS_S_iiiiiiii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
```
| 4,082 | 5,303 |
113,663 |
Convert the following CUDA host assembly code to AMD host assembly:
```cudaasm
.file "tmpxft_0005ba5a_00000000-6_cuda_code_082627.cudafe1.cpp"
.text
.globl _ZSt21ios_base_library_initv
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3638:
.cfi_startproc
endbr64
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
jmp __cudaUnregisterFatBinary@PLT
.cfi_endproc
.LFE3638:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z50__device_stub__Z18convBackpropKernelPfS_S_iiiiiiiiPfS_S_iiiiiiii
.type _Z50__device_stub__Z18convBackpropKernelPfS_S_iiiiiiiiPfS_S_iiiiiiii, @function
_Z50__device_stub__Z18convBackpropKernelPfS_S_iiiiiiiiPfS_S_iiiiiiii:
.LFB3660:
.cfi_startproc
endbr64
subq $216, %rsp
.cfi_def_cfa_offset 224
movq %rdi, 40(%rsp)
leaq 64(%rsp), %rdi
movq %rsi, 32(%rsp)
leaq 76(%rsp), %rsi
movq %rdx, 24(%rsp)
leaq 48(%rsp), %rdx
movl %ecx, 20(%rsp)
leaq 56(%rsp), %rcx
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 200(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movl $1, 72(%rsp)
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
leaq 224(%rsp), %rax
movq %rax, 160(%rsp)
leaq 232(%rsp), %rax
movq %rax, 168(%rsp)
leaq 240(%rsp), %rax
movq %rax, 176(%rsp)
leaq 248(%rsp), %rax
movq %rax, 184(%rsp)
leaq 256(%rsp), %rax
movq %rax, 192(%rsp)
movabsq $4294967297, %rax
movq %rax, 64(%rsp)
movq %rax, 76(%rsp)
movl $1, 84(%rsp)
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
jne .L2
pushq 56(%rsp)
.cfi_def_cfa_offset 232
leaq _Z18convBackpropKernelPfS_S_iiiiiiii(%rip), %rdi
pushq 56(%rsp)
.cfi_def_cfa_offset 240
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq 128(%rsp), %r9
call cudaLaunchKernel@PLT
popq %rax
.cfi_def_cfa_offset 232
popq %rdx
.cfi_def_cfa_offset 224
.L2:
movq 200(%rsp), %rax
subq %fs:40, %rax
je .L4
call __stack_chk_fail@PLT
.L4:
addq $216, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3660:
.size _Z50__device_stub__Z18convBackpropKernelPfS_S_iiiiiiiiPfS_S_iiiiiiii, .-_Z50__device_stub__Z18convBackpropKernelPfS_S_iiiiiiiiPfS_S_iiiiiiii
.globl _Z18convBackpropKernelPfS_S_iiiiiiii
.type _Z18convBackpropKernelPfS_S_iiiiiiii, @function
_Z18convBackpropKernelPfS_S_iiiiiiii:
.LFB3661:
.cfi_startproc
endbr64
jmp _Z50__device_stub__Z18convBackpropKernelPfS_S_iiiiiiiiPfS_S_iiiiiiii
.cfi_endproc
.LFE3661:
.size _Z18convBackpropKernelPfS_S_iiiiiiii, .-_Z18convBackpropKernelPfS_S_iiiiiiii
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "convBackpropKernel launch failed: %s\n"
.LC2:
.string "cudaDeviceReset failed!\n"
.section .text.startup,"ax",@progbits
.globl main
.type main, @function
main:
.LFB3635:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
movl $12288, %edi
xorl %r13d, %r13d
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $72, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
call _Znam@PLT
movl $32768, %edi
movq %rax, %r12
call _Znam@PLT
movl $864, %edi
movq %rax, %rbp
call _Znam@PLT
movq %rax, %rbx
.L9:
call rand@PLT
cvtsi2ssl %eax, %xmm0
mulss .LC0(%rip), %xmm0
movss %xmm0, (%r12,%r13,4)
incq %r13
cmpq $3072, %r13
jne .L9
xorl %r13d, %r13d
.L10:
call rand@PLT
cvtsi2ssl %eax, %xmm0
mulss .LC0(%rip), %xmm0
movss %xmm0, 0(%rbp,%r13,4)
incq %r13
cmpq $8192, %r13
jne .L10
xorl %eax, %eax
movl $216, %ecx
movq %rbx, %rdi
movl $12288, %esi
rep stosl
leaq 8(%rsp), %rdi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $32768, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $864, %esi
call cudaMalloc@PLT
movq 8(%rsp), %rdi
movl $1, %ecx
movq %r12, %rsi
movl $12288, %edx
call cudaMemcpy@PLT
movq 16(%rsp), %rdi
movl $1, %ecx
movq %rbp, %rsi
movl $32768, %edx
call cudaMemcpy@PLT
movq 24(%rsp), %rdi
movl $1, %ecx
movq %rbx, %rsi
movl $864, %edx
call cudaMemcpy@PLT
movl $1610612737, %edi
xorl %r9d, %r9d
xorl %r8d, %r8d
salq $3, %rdi
movl $1, %ecx
movl $1, %esi
movabsq $12884901891, %rdx
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L11
pushq %rax
.cfi_def_cfa_offset 120
movl $3, %r9d
movl $32, %r8d
movl $32, %ecx
pushq $1
.cfi_def_cfa_offset 128
pushq $1
.cfi_def_cfa_offset 136
pushq $8
.cfi_def_cfa_offset 144
pushq $3
.cfi_def_cfa_offset 152
pushq $3
.cfi_def_cfa_offset 160
movq 64(%rsp), %rdx
movq 72(%rsp), %rsi
movq 56(%rsp), %rdi
call _Z50__device_stub__Z18convBackpropKernelPfS_S_iiiiiiiiPfS_S_iiiiiiii
addq $48, %rsp
.cfi_def_cfa_offset 112
.L11:
movq 24(%rsp), %rsi
movl $2, %ecx
movl $864, %edx
movq %rbx, %rdi
call cudaMemcpy@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq %r12, %rdi
call _ZdaPv@PLT
movq %rbp, %rdi
call _ZdaPv@PLT
movq %rbx, %rdi
call _ZdaPv@PLT
call cudaGetLastError@PLT
movl %eax, %edi
testl %eax, %eax
je .L12
call cudaGetErrorString@PLT
movq stderr(%rip), %rdi
movl $2, %esi
leaq .LC1(%rip), %rdx
movq %rax, %rcx
xorl %eax, %eax
call __fprintf_chk@PLT
jmp .L13
.L12:
call cudaDeviceReset@PLT
movl %eax, %edx
xorl %eax, %eax
testl %edx, %edx
je .L8
movq stderr(%rip), %rdi
leaq .LC2(%rip), %rdx
movl $2, %esi
call __fprintf_chk@PLT
.L13:
movl $1, %eax
.L8:
movq 56(%rsp), %rdx
subq %fs:40, %rdx
je .L15
call __stack_chk_fail@PLT
.L15:
addq $72, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3635:
.size main, .-main
.section .rodata.str1.1
.LC3:
.string "_Z18convBackpropKernelPfS_S_iiiiiiii"
.section .text.startup
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3663:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
pushq $0
.cfi_def_cfa_offset 24
xorl %r9d, %r9d
orl $-1, %r8d
pushq $0
.cfi_def_cfa_offset 32
leaq .LC3(%rip), %rdx
movq %rax, %rdi
leaq _Z18convBackpropKernelPfS_S_iiiiiiii(%rip), %rsi
pushq $0
.cfi_def_cfa_offset 40
movq %rdx, %rcx
pushq $0
.cfi_def_cfa_offset 48
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFunction@PLT
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
addq $32, %rsp
.cfi_def_cfa_offset 16
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
popq %rdx
.cfi_def_cfa_offset 8
jmp atexit@PLT
.cfi_endproc
.LFE3663:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC0:
.long 805306368
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
```
|
```amdasm
.text
.file "cuda_code_082627.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z33__device_stub__convBackpropKernelPfS_S_iiiiiiii # -- Begin function _Z33__device_stub__convBackpropKernelPfS_S_iiiiiiii
.type _Z33__device_stub__convBackpropKernelPfS_S_iiiiiiii,@function
_Z33__device_stub__convBackpropKernelPfS_S_iiiiiiii: # @_Z33__device_stub__convBackpropKernelPfS_S_iiiiiiii
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $192, %rsp
.cfi_def_cfa_offset 240
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 56(%rsp), %rax
movq %rdi, (%rax)
leaq 48(%rsp), %rdi
movq %rsi, (%rdi)
leaq 40(%rsp), %rsi
movq %rdx, (%rsi)
leaq 20(%rsp), %rdx
movl %ecx, (%rdx)
leaq 16(%rsp), %rcx
movl %r8d, (%rcx)
leaq 12(%rsp), %r8
movl %r9d, (%r8)
leaq 96(%rsp), %rbx
movq %rax, (%rbx)
movq %rdi, 8(%rbx)
movq %rsi, 16(%rbx)
movq %rdx, 24(%rbx)
movq %rcx, 32(%rbx)
movq %r8, 40(%rbx)
leaq 240(%rsp), %rax
movq %rax, 48(%rbx)
leaq 248(%rsp), %rax
movq %rax, 56(%rbx)
leaq 256(%rsp), %rax
movq %rax, 64(%rbx)
leaq 264(%rsp), %rax
movq %rax, 72(%rbx)
leaq 272(%rsp), %rax
movq %rax, 80(%rbx)
leaq 80(%rsp), %r14
leaq 64(%rsp), %r15
leaq 32(%rsp), %r12
leaq 24(%rsp), %r13
movq %r14, %rdi
movq %r15, %rsi
movq %r12, %rdx
movq %r13, %rcx
callq __hipPopCallConfiguration
movq (%r14), %rsi
movl 8(%r14), %edx
movq (%r15), %rcx
movl 8(%r15), %r8d
movl $_Z18convBackpropKernelPfS_S_iiiiiiii, %edi
movq %rbx, %r9
pushq (%r13)
.cfi_adjust_cfa_offset 8
pushq (%r12)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $208, %rsp
.cfi_adjust_cfa_offset -208
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z33__device_stub__convBackpropKernelPfS_S_iiiiiiii, .Lfunc_end0-_Z33__device_stub__convBackpropKernelPfS_S_iiiiiiii
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI1_0:
.long 0x30000000 # float 4.65661287E-10
.text
.globl main
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $24, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $12288, %edi # imm = 0x3000
callq _Znam
movq %rax, %rbx
movl $32768, %edi # imm = 0x8000
callq _Znam
movq %rax, %r14
movl $864, %edi # imm = 0x360
callq _Znam
movq %rax, %r15
xorl %r12d, %r12d
.LBB1_1: # =>This Inner Loop Header: Depth=1
callq rand
movss .LCPI1_0(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
mulss %xmm1, %xmm0
movss %xmm0, (%rbx,%r12,4)
incq %r12
cmpq $3072, %r12 # imm = 0xC00
jne .LBB1_1
# %bb.2: # %.preheader93.preheader
xorl %r12d, %r12d
.LBB1_3: # %.preheader93
# =>This Inner Loop Header: Depth=1
callq rand
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
mulss .LCPI1_0(%rip), %xmm0
movss %xmm0, (%r14,%r12,4)
incq %r12
cmpq $8192, %r12 # imm = 0x2000
jne .LBB1_3
# %bb.4: # %.preheader.preheader
movl $864, %edx # imm = 0x360
movq %r15, %rdi
xorl %esi, %esi
callq memset@PLT
leaq 16(%rsp), %r12
movl $12288, %esi # imm = 0x3000
movq %r12, %rdi
callq hipMalloc
leaq 8(%rsp), %r13
movl $32768, %esi # imm = 0x8000
movq %r13, %rdi
callq hipMalloc
movq %rsp, %rbp
movl $864, %esi # imm = 0x360
movq %rbp, %rdi
callq hipMalloc
movq (%r12), %rdi
movl $1, %r12d
movl $12288, %edx # imm = 0x3000
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq (%r13), %rdi
movl $32768, %edx # imm = 0x8000
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movq (%rbp), %rdi
movl $864, %edx # imm = 0x360
movq %r15, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $12884901891, %rdx # imm = 0x300000003
leaq 5(%rdx), %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_6
# %bb.5:
movq 16(%rsp), %rdi
movq (%rsp), %rsi
movq 8(%rsp), %rdx
subq $8, %rsp
.cfi_adjust_cfa_offset 8
movl $3, %eax
movl $32, %ecx
movl $32, %r8d
movl $3, %r9d
pushq %r12
.cfi_adjust_cfa_offset 8
pushq %r12
.cfi_adjust_cfa_offset 8
pushq $8
.cfi_adjust_cfa_offset 8
pushq %rax
.cfi_adjust_cfa_offset 8
pushq %rax
.cfi_adjust_cfa_offset 8
callq _Z33__device_stub__convBackpropKernelPfS_S_iiiiiiii
addq $48, %rsp
.cfi_adjust_cfa_offset -48
.LBB1_6:
movq (%rsp), %rsi
movl $864, %edx # imm = 0x360
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipFree
movq %rbx, %rdi
callq _ZdaPv
movq %r14, %rdi
callq _ZdaPv
movq %r15, %rdi
callq _ZdaPv
callq hipGetLastError
testl %eax, %eax
jne .LBB1_7
# %bb.8:
callq hipDeviceReset
movl %eax, %ecx
xorl %eax, %eax
testl %ecx, %ecx
jne .LBB1_9
.LBB1_11:
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB1_7:
.cfi_def_cfa_offset 80
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %esi
movq %rbx, %rdi
movq %rax, %rdx
xorl %eax, %eax
callq fprintf
jmp .LBB1_10
.LBB1_9:
movq stderr(%rip), %rcx
movl $.L.str.1, %edi
movl $23, %esi
movl $1, %edx
callq fwrite@PLT
.LBB1_10:
movl $1, %eax
jmp .LBB1_11
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, %rdi
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z18convBackpropKernelPfS_S_iiiiiiii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z18convBackpropKernelPfS_S_iiiiiiii,@object # @_Z18convBackpropKernelPfS_S_iiiiiiii
.section .rodata,"a",@progbits
.globl _Z18convBackpropKernelPfS_S_iiiiiiii
.p2align 3, 0x0
_Z18convBackpropKernelPfS_S_iiiiiiii:
.quad _Z33__device_stub__convBackpropKernelPfS_S_iiiiiiii
.size _Z18convBackpropKernelPfS_S_iiiiiiii, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "convBackpropKernel launch failed: %s\n"
.size .L.str, 38
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "hipDeviceReset failed!\n"
.size .L.str.1, 24
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z18convBackpropKernelPfS_S_iiiiiiii"
.size .L__unnamed_1, 37
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z33__device_stub__convBackpropKernelPfS_S_iiiiiiii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z18convBackpropKernelPfS_S_iiiiiiii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
```
| 3,956 | 4,666 |
113,664 |
Convert the following CUDA device assembly code to AMD device assembly:
```cudaasm
code for sm_80
Function : _Z15sparseFFTKernelP6float2i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
MOV R1, c[0x0][0x28] ;
S2R R2, SR_CTAID.X ;
S2R R3, SR_TID.X ;
IMAD R2, R2, c[0x0][0x0], R3 ;
ISETP.GE.AND P0, PT, R2, c[0x0][0x168], PT ;
@P0 EXIT ;
HFMA2.MMA R3, -RZ, RZ, 0, 4.76837158203125e-07 ;
ULDC.64 UR4, c[0x0][0x118] ;
IMAD.WIDE R2, R2, R3, c[0x0][0x160] ;
LDG.E.64 R4, [R2.64] ;
FADD R5, R5, R5 ;
FADD R4, R4, R4 ;
STG.E.64 [R2.64], R4 ;
EXIT ;
BRA 0xe0;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
```
|
```amdasm
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z15sparseFFTKernelP15HIP_vector_typeIfLj2EEi ; -- Begin function _Z15sparseFFTKernelP15HIP_vector_typeIfLj2EEi
.globl _Z15sparseFFTKernelP15HIP_vector_typeIfLj2EEi
.p2align 8
.type _Z15sparseFFTKernelP15HIP_vector_typeIfLj2EEi,@function
_Z15sparseFFTKernelP15HIP_vector_typeIfLj2EEi: ; @_Z15sparseFFTKernelP15HIP_vector_typeIfLj2EEi
; %bb.0:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x1c
s_load_b32 s3, s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
; %bb.1:
s_load_b64 s[0:1], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 3, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_load_b64 v[2:3], v[0:1], off
s_waitcnt vmcnt(0)
v_dual_add_f32 v2, v2, v2 :: v_dual_add_f32 v3, v3, v3
global_store_b64 v[0:1], v[2:3], off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z15sparseFFTKernelP15HIP_vector_typeIfLj2EEi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z15sparseFFTKernelP15HIP_vector_typeIfLj2EEi, .Lfunc_end0-_Z15sparseFFTKernelP15HIP_vector_typeIfLj2EEi
; -- End function
.section .AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 144
; NumSgprs: 18
; NumVgprs: 4
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 4
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object ; @__hip_cuid_
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0 ; 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z15sparseFFTKernelP15HIP_vector_typeIfLj2EEi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z15sparseFFTKernelP15HIP_vector_typeIfLj2EEi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
```
| 336 | 2,504 |
113,665 |
Convert the following CUDA host assembly code to AMD host assembly:
```cudaasm
.file "tmpxft_0014c8ab_00000000-6_cuda_code_046827.cudafe1.cpp"
.text
.globl _ZSt21ios_base_library_initv
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3662:
.cfi_startproc
endbr64
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
jmp __cudaUnregisterFatBinary@PLT
.cfi_endproc
.LFE3662:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.align 2
.type _ZNSolsEPFRSoS_E.isra.0, @function
_ZNSolsEPFRSoS_E.isra.0:
.LFB4317:
.cfi_startproc
jmp *%rsi
.cfi_endproc
.LFE4317:
.size _ZNSolsEPFRSoS_E.isra.0, .-_ZNSolsEPFRSoS_E.isra.0
.globl _Z42__device_stub__Z15sparseFFTKernelP6float2iP6float2i
.type _Z42__device_stub__Z15sparseFFTKernelP6float2iP6float2i, @function
_Z42__device_stub__Z15sparseFFTKernelP6float2iP6float2i:
.LFB3684:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
leaq 32(%rsp), %rcx
leaq 24(%rsp), %rdx
movl %esi, 4(%rsp)
leaq 40(%rsp), %rdi
leaq 52(%rsp), %rsi
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movl $1, 48(%rsp)
movq %rax, 88(%rsp)
leaq 4(%rsp), %rax
movq %rax, 96(%rsp)
movabsq $4294967297, %rax
movq %rax, 40(%rsp)
movq %rax, 52(%rsp)
movl $1, 60(%rsp)
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
jne .L3
pushq 32(%rsp)
.cfi_def_cfa_offset 136
leaq _Z15sparseFFTKernelP6float2i(%rip), %rdi
pushq 32(%rsp)
.cfi_def_cfa_offset 144
movq 68(%rsp), %rcx
movl 76(%rsp), %r8d
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
leaq 104(%rsp), %r9
call cudaLaunchKernel@PLT
popq %rax
.cfi_def_cfa_offset 136
popq %rdx
.cfi_def_cfa_offset 128
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
je .L5
call __stack_chk_fail@PLT
.L5:
addq $120, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3684:
.size _Z42__device_stub__Z15sparseFFTKernelP6float2iP6float2i, .-_Z42__device_stub__Z15sparseFFTKernelP6float2iP6float2i
.globl _Z15sparseFFTKernelP6float2i
.type _Z15sparseFFTKernelP6float2i, @function
_Z15sparseFFTKernelP6float2i:
.LFB3685:
.cfi_startproc
endbr64
jmp _Z42__device_stub__Z15sparseFFTKernelP6float2iP6float2i
.cfi_endproc
.LFE3685:
.size _Z15sparseFFTKernelP6float2i, .-_Z15sparseFFTKernelP6float2i
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "Failed to allocate device memory (error code "
.LC2:
.string ")"
.LC3:
.string "Failed to copy data from host to device (error code "
.LC4:
.string "Kernel launch failed (error code "
.LC5:
.string "Failed to copy data from device to host (error code "
.LC6:
.string "Transformed data:"
.LC7:
.string "h_data["
.LC8:
.string "] = ("
.LC9:
.string ", "
.section .text.startup,"ax",@progbits
.globl main
.type main, @function
main:
.LFB3659:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
movl $8192, %edi
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $48, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
call malloc@PLT
movq %rax, %rbx
xorl %eax, %eax
.L10:
cvtsi2ssl %eax, %xmm0
movl $0x00000000, 4(%rbx,%rax,8)
movss %xmm0, (%rbx,%rax,8)
incq %rax
cmpq $1024, %rax
jne .L10
movl $8192, %esi
leaq 8(%rsp), %rdi
leaq .LC2(%rip), %r12
call cudaMalloc@PLT
leaq .LC1(%rip), %rsi
testl %eax, %eax
movl %eax, %ebp
jne .L23
movq 8(%rsp), %rdi
movl $1, %ecx
movl $8192, %edx
movq %rbx, %rsi
call cudaMemcpy@PLT
movl %eax, %ebp
testl %eax, %eax
je .L13
leaq .LC3(%rip), %rsi
.L23:
leaq _ZSt4cerr(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movl %ebp, %esi
movq %rax, %rdi
call _ZNSolsEi@PLT
movq %r12, %rsi
movq %rax, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@GOTPCREL(%rip), %rsi
movq %rax, %rdi
call _ZNSolsEPFRSoS_E.isra.0
orl $-1, %eax
jmp .L9
.L13:
movl $16777217, %edx
movl $1073741825, %edi
xorl %r9d, %r9d
xorl %r8d, %r8d
salq $8, %rdx
salq $2, %rdi
movl $1, %ecx
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L15
movq 8(%rsp), %rdi
movl $1024, %esi
call _Z42__device_stub__Z15sparseFFTKernelP6float2iP6float2i
.L15:
call cudaGetLastError@PLT
leaq .LC4(%rip), %rsi
movl %eax, %ebp
testl %eax, %eax
jne .L23
movq 8(%rsp), %rsi
movl $2, %ecx
movl $8192, %edx
movq %rbx, %rdi
call cudaMemcpy@PLT
leaq .LC5(%rip), %rsi
movl %eax, %ebp
testl %eax, %eax
jne .L23
leaq _ZSt4cout(%rip), %r13
leaq .LC6(%rip), %rsi
xorl %ebp, %ebp
movq %r13, %rdi
leaq .LC7(%rip), %r14
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@GOTPCREL(%rip), %rsi
movq %rax, %rdi
call _ZNSolsEPFRSoS_E.isra.0
.L18:
movq %r14, %rsi
movq %r13, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movl %ebp, %esi
movq %rax, %rdi
call _ZNSolsEi@PLT
leaq .LC8(%rip), %rsi
movq %rax, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
cvtss2sd (%rbx,%rbp,8), %xmm0
movq %rax, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
leaq .LC9(%rip), %rsi
movq %rax, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
cvtss2sd 4(%rbx,%rbp,8), %xmm0
incq %rbp
movq %rax, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %r12, %rsi
movq %rax, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@GOTPCREL(%rip), %rsi
movq %rax, %rdi
call _ZNSolsEPFRSoS_E.isra.0
cmpq $10, %rbp
jne .L18
movq 8(%rsp), %rdi
call cudaFree@PLT
movq %rbx, %rdi
call free@PLT
xorl %eax, %eax
.L9:
movq 40(%rsp), %rdx
subq %fs:40, %rdx
je .L19
call __stack_chk_fail@PLT
.L19:
addq $48, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3659:
.size main, .-main
.section .rodata.str1.1
.LC10:
.string "_Z15sparseFFTKernelP6float2i"
.section .text.startup
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3687:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
pushq $0
.cfi_def_cfa_offset 24
xorl %r9d, %r9d
orl $-1, %r8d
pushq $0
.cfi_def_cfa_offset 32
leaq .LC10(%rip), %rdx
movq %rax, %rdi
leaq _Z15sparseFFTKernelP6float2i(%rip), %rsi
pushq $0
.cfi_def_cfa_offset 40
movq %rdx, %rcx
pushq $0
.cfi_def_cfa_offset 48
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFunction@PLT
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
addq $32, %rsp
.cfi_def_cfa_offset 16
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
popq %rdx
.cfi_def_cfa_offset 8
jmp atexit@PLT
.cfi_endproc
.LFE3687:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
```
|
```amdasm
.text
.file "cuda_code_046827.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z30__device_stub__sparseFFTKernelP15HIP_vector_typeIfLj2EEi # -- Begin function _Z30__device_stub__sparseFFTKernelP15HIP_vector_typeIfLj2EEi
.type _Z30__device_stub__sparseFFTKernelP15HIP_vector_typeIfLj2EEi,@function
_Z30__device_stub__sparseFFTKernelP15HIP_vector_typeIfLj2EEi: # @_Z30__device_stub__sparseFFTKernelP15HIP_vector_typeIfLj2EEi
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $80, %rsp
.cfi_def_cfa_offset 128
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 24(%rsp), %rax
movq %rdi, (%rax)
leaq 4(%rsp), %rcx
movl %esi, (%rcx)
leaq 64(%rsp), %rbx
movq %rax, (%rbx)
movq %rcx, 8(%rbx)
leaq 48(%rsp), %r14
leaq 32(%rsp), %r15
leaq 16(%rsp), %r12
leaq 8(%rsp), %r13
movq %r14, %rdi
movq %r15, %rsi
movq %r12, %rdx
movq %r13, %rcx
callq __hipPopCallConfiguration
movq (%r14), %rsi
movl 8(%r14), %edx
movq (%r15), %rcx
movl 8(%r15), %r8d
movl $_Z15sparseFFTKernelP15HIP_vector_typeIfLj2EEi, %edi
movq %rbx, %r9
pushq (%r13)
.cfi_adjust_cfa_offset 8
pushq (%r12)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $96, %rsp
.cfi_adjust_cfa_offset -96
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z30__device_stub__sparseFFTKernelP15HIP_vector_typeIfLj2EEi, .Lfunc_end0-_Z30__device_stub__sparseFFTKernelP15HIP_vector_typeIfLj2EEi
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
pushq %rax
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $8192, %edi # imm = 0x2000
callq malloc
movq %rax, %rbx
xorl %eax, %eax
.LBB1_1: # =>This Inner Loop Header: Depth=1
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movss %xmm0, (%rbx,%rax,8)
movl $0, 4(%rbx,%rax,8)
incq %rax
cmpq $1024, %rax # imm = 0x400
jne .LBB1_1
# %bb.2:
movq %rsp, %rdi
movl $8192, %esi # imm = 0x2000
callq hipMalloc
testl %eax, %eax
je .LBB1_4
# %bb.3:
movl %eax, %ebp
movl $_ZSt4cerr, %edi
movl $.L.str, %esi
movl $45, %edx
jmp .LBB1_7
.LBB1_4:
movq (%rsp), %rdi
movl $8192, %edx # imm = 0x2000
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
je .LBB1_8
# %bb.5:
movl %eax, %ebp
movl $_ZSt4cerr, %edi
movl $.L.str.2, %esi
.LBB1_6:
movl $52, %edx
jmp .LBB1_7
.LBB1_8:
movabsq $4294967300, %rdi # imm = 0x100000004
leaq 252(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_10
# %bb.9:
movq (%rsp), %rdi
movl $1024, %esi # imm = 0x400
callq _Z30__device_stub__sparseFFTKernelP15HIP_vector_typeIfLj2EEi
.LBB1_10:
callq hipGetLastError
testl %eax, %eax
je .LBB1_12
# %bb.11:
movl %eax, %ebp
movl $_ZSt4cerr, %edi
movl $.L.str.3, %esi
movl $33, %edx
.LBB1_7:
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cerr, %edi
movl %ebp, %esi
callq _ZNSolsEi
movq %rax, %rbx
movl $.L.str.1, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq (%rbx), %rax
movq -24(%rax), %rdi
addq %rbx, %rdi
movl $10, %esi
callq _ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
movsbl %al, %esi
movq %rbx, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $-1, %eax
.LBB1_17:
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB1_12:
.cfi_def_cfa_offset 48
movq (%rsp), %rsi
movl $8192, %edx # imm = 0x2000
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
je .LBB1_14
# %bb.13:
movl %eax, %ebp
movl $_ZSt4cerr, %edi
movl $.L.str.4, %esi
jmp .LBB1_6
.LBB1_14:
movl $_ZSt4cout, %edi
movl $.L.str.5, %esi
movl $17, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
callq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_
xorl %r14d, %r14d
.LBB1_15: # =>This Inner Loop Header: Depth=1
movl $_ZSt4cout, %edi
movl $.L.str.6, %esi
movl $7, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl %r14d, %esi
callq _ZNSolsEi
movq %rax, %r15
movl $.L.str.7, %esi
movl $5, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
xorps %xmm0, %xmm0
cvtss2sd (%rbx,%r14,8), %xmm0
movq %r15, %rdi
callq _ZNSo9_M_insertIdEERSoT_
movq %rax, %r15
movl $.L.str.8, %esi
movl $2, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
xorps %xmm0, %xmm0
cvtss2sd 4(%rbx,%r14,8), %xmm0
movq %r15, %rdi
callq _ZNSo9_M_insertIdEERSoT_
movq %rax, %r15
movl $.L.str.1, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq (%r15), %rax
movq -24(%rax), %rdi
addq %r15, %rdi
movl $10, %esi
callq _ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
movsbl %al, %esi
movq %r15, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
incq %r14
cmpq $10, %r14
jne .LBB1_15
# %bb.16:
movq (%rsp), %rdi
callq hipFree
movq %rbx, %rdi
callq free
xorl %eax, %eax
jmp .LBB1_17
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, %rdi
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15sparseFFTKernelP15HIP_vector_typeIfLj2EEi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z15sparseFFTKernelP15HIP_vector_typeIfLj2EEi,@object # @_Z15sparseFFTKernelP15HIP_vector_typeIfLj2EEi
.section .rodata,"a",@progbits
.globl _Z15sparseFFTKernelP15HIP_vector_typeIfLj2EEi
.p2align 3, 0x0
_Z15sparseFFTKernelP15HIP_vector_typeIfLj2EEi:
.quad _Z30__device_stub__sparseFFTKernelP15HIP_vector_typeIfLj2EEi
.size _Z15sparseFFTKernelP15HIP_vector_typeIfLj2EEi, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Failed to allocate device memory (error code "
.size .L.str, 46
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz ")"
.size .L.str.1, 2
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Failed to copy data from host to device (error code "
.size .L.str.2, 53
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Kernel launch failed (error code "
.size .L.str.3, 34
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Failed to copy data from device to host (error code "
.size .L.str.4, 53
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "Transformed data:"
.size .L.str.5, 18
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "h_data["
.size .L.str.6, 8
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "] = ("
.size .L.str.7, 6
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz ", "
.size .L.str.8, 3
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z15sparseFFTKernelP15HIP_vector_typeIfLj2EEi"
.size .L__unnamed_1, 46
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z30__device_stub__sparseFFTKernelP15HIP_vector_typeIfLj2EEi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z15sparseFFTKernelP15HIP_vector_typeIfLj2EEi
.addrsig_sym _ZSt4cerr
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
```
| 3,953 | 4,881 |
113,666 |
Convert the following CUDA device assembly code to AMD device assembly:
```cudaasm
code for sm_80
Function : _Z16waveletTransformPfi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ;
S2R R4, SR_CTAID.X ;
IMAD.MOV.U32 R3, RZ, RZ, 0x4 ;
ULDC.64 UR4, c[0x0][0x118] ;
BSSY B0, 0xd0 ;
S2R R7, SR_TID.X ;
IMAD R0, R4, c[0x0][0x0], R7 ;
IMAD.WIDE R2, R0.reuse, R3, c[0x0][0x160] ;
ISETP.GE.AND P1, PT, R0, c[0x0][0x168], PT ;
@P1 BRA 0xc0 ;
LDG.E R5, [R2.64] ;
STS [R0.X4], R5 ;
BSYNC B0 ;
IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x168] ;
BAR.SYNC.DEFER_BLOCKING 0x0 ;
ISETP.GE.AND P0, PT, R5, 0x2, PT ;
@!P0 BRA 0x6c0 ;
S2R R5, SR_CTAID.Y ;
MOV R9, c[0x0][0xc] ;
S2R R8, SR_CTAID.Z ;
IMAD.MOV R10, RZ, RZ, -R9 ;
MOV R9, c[0x0][0x14] ;
S2R R6, SR_TID.Y ;
S2R R14, SR_TID.Z ;
IMAD.IADD R4, R4, 0x1, R5 ;
IMAD.MOV R5, RZ, RZ, -R8 ;
IMAD R8, R10, c[0x0][0x10], RZ ;
ISETP.NE.AND P0, PT, R4, R5, PT ;
IMAD R5, R8, R9, -0x7fffffff ;
IMAD.IADD R4, R7, 0x1, R6 ;
HFMA2.MMA R7, -RZ, RZ, 0, 5.9604644775390625e-08 ;
SEL R5, R5, 0x1, !P0 ;
IMAD.SHL.U32 R6, R7, 0x2, RZ ;
IABS R16, R0 ;
ISETP.GE.AND P2, PT, R0, RZ, PT ;
IABS R12, R6 ;
IABS R13, R6 ;
I2F.RP R10, R12 ;
ISETP.NE.AND P3, PT, R6, RZ, PT ;
MUFU.RCP R10, R10 ;
IADD3 R8, R10, 0xffffffe, RZ ;
IMAD.MOV R10, RZ, RZ, -R13 ;
F2I.FTZ.U32.TRUNC.NTZ R9, R8 ;
MOV R8, RZ ;
IMAD.MOV R11, RZ, RZ, -R9 ;
IMAD R11, R11, R12, RZ ;
IMAD.HI.U32 R9, R9, R11, R8 ;
IMAD.HI.U32 R9, R9, R16, RZ ;
IMAD R9, R9, R10, R16 ;
ISETP.GT.U32.AND P0, PT, R12, R9, PT ;
@!P0 IMAD.IADD R9, R9, 0x1, -R12 ;
ISETP.GT.U32.AND P0, PT, R12, R9, PT ;
@!P0 IADD3 R9, R9, -R12, RZ ;
ISETP.NE.U32.AND P0, PT, RZ, c[0x0][0x90], PT ;
@!P2 IMAD.MOV R9, RZ, RZ, -R9 ;
ISETP.NE.AND.EX P0, PT, RZ, c[0x0][0x8c], PT, P0 ;
@!P3 LOP3.LUT R9, RZ, R6, RZ, 0x33, !PT ;
@!P0 BRA 0x700 ;
IMAD.MOV R11, RZ, RZ, -R14 ;
BAR.SYNC 0x0 ;
ISETP.NE.AND P0, PT, R4, R11, PT ;
BSSY B0, 0x570 ;
IADD3 R10, R0, -R9, RZ ;
@P0 BRA 0x560 ;
S2R R9, SR_LANEID ;
MEMBAR.ALL.GPU ;
VOTEU.ANY UR6, UPT, PT ;
IMAD.MOV.U32 R8, RZ, RZ, c[0x0][0x90] ;
FLO.U32 R12, UR6 ;
UPOPC UR7, UR6 ;
ERRBAR;
IMAD R13, R5, UR7, RZ ;
ISETP.EQ.U32.AND P0, PT, R12, R9, PT ;
IMAD.MOV.U32 R9, RZ, RZ, c[0x0][0x8c] ;
@P0 ATOM.E.ADD.STRONG.GPU PT, R13, [R8.64+0x4], R13 ;
S2R R11, SR_LTMASK ;
LOP3.LUT R15, R11, UR6, RZ, 0xc0, !PT ;
POPC R11, R15 ;
SHFL.IDX PT, R12, R13, R12, 0x1f ;
IMAD R11, R5, R11, R12 ;
LD.E.STRONG.GPU R12, [R8.64+0x4] ;
YIELD ;
LOP3.LUT R13, R12, R11, RZ, 0x3c, !PT ;
CCTL.IVALL ;
ISETP.GT.AND P0, PT, R13, -0x1, PT ;
@P0 BRA 0x500 ;
BSYNC B0 ;
BRA.CONV ~URZ, 0x5b0 ;
MOV R8, 0x5a0 ;
CALL.REL.NOINC 0x710 ;
BRA 0x5c0 ;
BAR.SYNC 0x0 ;
IADD3 R8, R10, R7, RZ ;
WARPSYNC 0xffffffff ;
ISETP.GE.AND P0, PT, R8, c[0x0][0x168], PT ;
ISETP.GE.OR P0, PT, R10, c[0x0][0x168], P0 ;
@!P0 IMAD.SHL.U32 R8, R10, 0x4, RZ ;
@!P0 LDS R12, [R10.X4] ;
@!P0 IMAD R8, R7, 0x4, R8 ;
@!P0 LDS R7, [R8] ;
@!P0 FADD R9, R7.reuse, R12.reuse ;
@!P0 FADD R7, -R7, R12 ;
@!P0 STS [R10.X4], R9 ;
@!P0 STS [R8], R7 ;
BAR.SYNC.DEFER_BLOCKING 0x0 ;
ISETP.GE.AND P0, PT, R6, c[0x0][0x168], PT ;
MOV R7, R6 ;
@!P0 BRA 0x200 ;
@P1 EXIT ;
LDS R5, [R0.X4] ;
STG.E [R2.64], R5 ;
EXIT ;
BPT.TRAP 0x1 ;
IMAD.MOV.U32 R9, RZ, RZ, 0x0 ;
WARPSYNC 0xffffffff ;
BAR.SYNC 0x0 ;
RET.REL.NODEC R8 0x0 ;
BRA 0x750;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
```
|
```amdasm
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z16waveletTransformPfi ; -- Begin function _Z16waveletTransformPfi
.globl _Z16waveletTransformPfi
.p2align 8
.type _Z16waveletTransformPfi,@function
_Z16waveletTransformPfi: ; @_Z16waveletTransformPfi
; %bb.0:
s_clause 0x2
s_load_b32 s6, s[0:1], 0x1c
s_load_b32 s8, s[0:1], 0x8
s_load_b64 s[2:3], s[0:1], 0x0
v_and_b32_e32 v3, 0x3ff, v0
s_add_u32 s4, s0, 16
s_addc_u32 s5, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s0, s6, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s0, v[3:4]
v_cmp_gt_i32_e32 vcc_lo, s8, v1
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b32_e32 v4, 2, v1
s_and_saveexec_b32 s1, vcc_lo
s_cbranch_execz .LBB0_2
; %bb.1:
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[5:6], 2, v[1:2]
v_add_co_u32 v5, s0, s2, v5
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v6, s0, s3, v6, s0
global_load_b32 v5, v[5:6], off
s_waitcnt vmcnt(0)
ds_store_b32 v4, v5
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s1
s_cmp_lt_i32 s8, 2
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB0_17
; %bb.3: ; %.lr.ph
v_bfe_u32 v5, v0, 20, 10
v_bfe_u32 v0, v0, 10, 10
v_add_nc_u32_e32 v6, v1, v2
s_mov_b32 s9, 1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_or3_b32 v3, v0, v5, v3
v_cmp_eq_u32_e64 s0, 0, v3
v_mov_b32_e32 v3, 0
v_xor_b32_e32 v0, v6, v2
.LBB0_4: ; =>This Loop Header: Depth=1
; Child Loop BB0_9 Depth 2
buffer_gl1_inv
buffer_gl0_inv
s_barrier
s_and_saveexec_b32 s10, s0
s_cbranch_execz .LBB0_14
; %bb.5: ; in Loop: Header=BB0_4 Depth=1
s_load_b64 s[6:7], s[4:5], 0x58
s_mov_b32 s11, exec_lo
s_mov_b32 s12, exec_lo
v_mbcnt_lo_u32_b32 v6, s11, 0
; implicit-def: $vgpr7
s_waitcnt lgkmcnt(0)
global_load_b32 v5, v3, s[6:7] offset:40
v_cmpx_eq_u32_e32 0, v6
s_cbranch_execz .LBB0_7
; %bb.6: ; in Loop: Header=BB0_4 Depth=1
s_bcnt1_i32_b32 s1, s11
s_delay_alu instid0(SALU_CYCLE_1)
v_mov_b32_e32 v7, s1
global_atomic_add_u32 v7, v3, v7, s[6:7] offset:32 glc
.LBB0_7: ; in Loop: Header=BB0_4 Depth=1
s_or_b32 exec_lo, exec_lo, s12
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s1, v7
v_add_nc_u32_e32 v8, -1, v5
s_mov_b32 s11, exec_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v6, s1, v6
v_and_b32_e32 v7, 0xffff, v6
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_ne_u32_e64 v7, v8
s_xor_b32 s11, exec_lo, s11
s_cbranch_execz .LBB0_11
; %bb.8: ; %.preheader.i.i.i.preheader
; in Loop: Header=BB0_4 Depth=1
s_mov_b32 s12, 0
.LBB0_9: ; %.preheader.i.i.i
; Parent Loop BB0_4 Depth=1
; => This Inner Loop Header: Depth=2
s_sleep 1
global_load_b32 v5, v3, s[6:7] offset:32 glc
s_waitcnt vmcnt(0)
v_xor_b32_e32 v5, v5, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_lt_u32_e64 s1, 0xffff, v5
s_or_b32 s12, s1, s12
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s12
s_cbranch_execnz .LBB0_9
; %bb.10: ; %Flow
; in Loop: Header=BB0_4 Depth=1
s_or_b32 exec_lo, exec_lo, s12
; implicit-def: $vgpr5
.LBB0_11: ; %Flow47
; in Loop: Header=BB0_4 Depth=1
s_and_not1_saveexec_b32 s1, s11
s_cbranch_execz .LBB0_14
; %bb.12: ; in Loop: Header=BB0_4 Depth=1
s_mov_b32 s11, exec_lo
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mbcnt_lo_u32_b32 v6, s11, 0
v_cmp_eq_u32_e64 s1, 0, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s1, exec_lo, s1
s_mov_b32 exec_lo, s1
s_cbranch_execz .LBB0_14
; %bb.13: ; in Loop: Header=BB0_4 Depth=1
v_sub_nc_u32_e32 v5, 0x10000, v5
s_bcnt1_i32_b32 s1, s11
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_mul_lo_u32 v5, v5, s1
global_atomic_add_u32 v3, v5, s[6:7] offset:32
.LBB0_14: ; %Flow49
; in Loop: Header=BB0_4 Depth=1
s_or_b32 exec_lo, exec_lo, s10
s_lshl_b32 s6, s9, 1
s_bfe_i32 s1, s9, 0x1001e
s_waitcnt_vscnt null, 0x0
s_barrier
s_add_i32 s7, s6, s1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_xor_b32 s7, s7, s1
v_cvt_f32_u32_e32 v5, s7
s_sub_i32 s1, 0, s7
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v5, v5
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v5, 0x4f7ffffe, v5
v_cvt_u32_f32_e32 v5, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v6, s1, v5
v_mul_hi_u32 v6, v5, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v5, v5, v6
v_mul_hi_u32 v5, v0, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v5, v5, s7
v_sub_nc_u32_e32 v5, v0, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_subrev_nc_u32_e32 v6, s7, v5
v_cmp_le_u32_e64 s1, s7, v5
v_cndmask_b32_e64 v5, v5, v6, s1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_subrev_nc_u32_e32 v6, s7, v5
v_cmp_le_u32_e64 s1, s7, v5
s_mov_b32 s7, exec_lo
v_cndmask_b32_e64 v5, v5, v6, s1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_xor_b32_e32 v5, v5, v2
v_sub_nc_u32_e32 v5, v2, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v5, v1, v5
v_add_nc_u32_e32 v6, s9, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_max_i32_e32 v6, v5, v6
v_cmpx_gt_i32_e64 s8, v6
s_cbranch_execz .LBB0_16
; %bb.15: ; in Loop: Header=BB0_4 Depth=1
v_lshlrev_b32_e32 v5, 2, v5
s_delay_alu instid0(VALU_DEP_1)
v_lshl_add_u32 v6, s9, 2, v5
ds_load_b32 v7, v5
ds_load_b32 v8, v6
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v9, v7, v8
v_sub_f32_e32 v7, v7, v8
ds_store_b32 v5, v9
ds_store_b32 v6, v7
.LBB0_16: ; in Loop: Header=BB0_4 Depth=1
s_or_b32 exec_lo, exec_lo, s7
s_cmp_lt_i32 s6, s8
s_mov_b32 s9, s6
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB0_4
.LBB0_17: ; %._crit_edge
s_and_saveexec_b32 s0, vcc_lo
s_cbranch_execz .LBB0_19
; %bb.18:
ds_load_b32 v3, v4
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
s_waitcnt lgkmcnt(0)
global_store_b32 v[0:1], v3, off
.LBB0_19:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z16waveletTransformPfi
.amdhsa_group_segment_fixed_size 8192
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 2
.amdhsa_next_free_vgpr 10
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z16waveletTransformPfi, .Lfunc_end0-_Z16waveletTransformPfi
; -- End function
.section .AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 880
; NumSgprs: 18
; NumVgprs: 10
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 8192 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 10
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 2
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object ; @__hip_cuid_
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0 ; 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
- .offset: 104
.size: 8
.value_kind: hidden_multigrid_sync_arg
.group_segment_fixed_size: 8192
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z16waveletTransformPfi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z16waveletTransformPfi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 10
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
```
| 2,019 | 5,247 |
113,667 |
Convert the following CUDA host assembly code to AMD host assembly:
```cudaasm
.file "tmpxft_00016639_00000000-6_cuda_code_058143.cudafe1.cpp"
.text
.globl _ZSt21ios_base_library_initv
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB6835:
.cfi_startproc
endbr64
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
jmp __cudaUnregisterFatBinary@PLT
.cfi_endproc
.LFE6835:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.align 2
.type _ZNSolsEPFRSoS_E.isra.0, @function
_ZNSolsEPFRSoS_E.isra.0:
.LFB7718:
.cfi_startproc
jmp *%rsi
.cfi_endproc
.LFE7718:
.size _ZNSolsEPFRSoS_E.isra.0, .-_ZNSolsEPFRSoS_E.isra.0
.globl _Z37__device_stub__Z16waveletTransformPfiPfi
.type _Z37__device_stub__Z16waveletTransformPfiPfi, @function
_Z37__device_stub__Z16waveletTransformPfiPfi:
.LFB6857:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
leaq 32(%rsp), %rcx
leaq 24(%rsp), %rdx
movl %esi, 4(%rsp)
leaq 40(%rsp), %rdi
leaq 52(%rsp), %rsi
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movl $1, 48(%rsp)
movq %rax, 88(%rsp)
leaq 4(%rsp), %rax
movq %rax, 96(%rsp)
movabsq $4294967297, %rax
movq %rax, 40(%rsp)
movq %rax, 52(%rsp)
movl $1, 60(%rsp)
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
jne .L3
pushq 32(%rsp)
.cfi_def_cfa_offset 136
leaq _Z16waveletTransformPfi(%rip), %rdi
pushq 32(%rsp)
.cfi_def_cfa_offset 144
movq 68(%rsp), %rcx
movl 76(%rsp), %r8d
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
leaq 104(%rsp), %r9
call cudaLaunchKernel@PLT
popq %rax
.cfi_def_cfa_offset 136
popq %rdx
.cfi_def_cfa_offset 128
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
je .L5
call __stack_chk_fail@PLT
.L5:
addq $120, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE6857:
.size _Z37__device_stub__Z16waveletTransformPfiPfi, .-_Z37__device_stub__Z16waveletTransformPfiPfi
.globl _Z16waveletTransformPfi
.type _Z16waveletTransformPfi, @function
_Z16waveletTransformPfi:
.LFB6858:
.cfi_startproc
endbr64
jmp _Z37__device_stub__Z16waveletTransformPfiPfi
.cfi_endproc
.LFE6858:
.size _Z16waveletTransformPfi, .-_Z16waveletTransformPfi
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Error allocating device memory: "
.LC1:
.string "Error copying memory to device: "
.LC2:
.string "Error launching kernel: "
.LC3:
.string "Error copying memory from device: "
.LC4:
.string "Transformed signal (first 10 elements):"
.LC5:
.string " "
.section .text.startup,"ax",@progbits
.globl main
.type main, @function
main:
.LFB6832:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
movl $8192, %edi
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $56, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
call malloc@PLT
movq %rax, %rbx
xorl %eax, %eax
.L10:
cvtsi2ssl %eax, %xmm0
movss %xmm0, (%rbx,%rax,4)
incq %rax
cmpq $2048, %rax
jne .L10
leaq 8(%rsp), %rdi
movl $8192, %esi
call cudaMalloc@PLT
movl %eax, %ebp
testl %eax, %eax
je .L11
leaq .LC0(%rip), %rsi
leaq _ZSt4cerr(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movl %ebp, %edi
movq %rax, %rbx
call cudaGetErrorString@PLT
movq %rbx, %rdi
movq %rax, %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@GOTPCREL(%rip), %rsi
movq %rax, %rdi
call _ZNSolsEPFRSoS_E.isra.0
jmp .L12
.L11:
movq 8(%rsp), %rdi
movl $1, %ecx
movl $8192, %edx
movq %rbx, %rsi
call cudaMemcpy@PLT
movl %eax, %ebp
testl %eax, %eax
je .L13
leaq .LC1(%rip), %rsi
.L23:
leaq _ZSt4cerr(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movl %ebp, %edi
movq %rax, %r12
call cudaGetErrorString@PLT
movq %r12, %rdi
movq %rax, %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@GOTPCREL(%rip), %rsi
movq %rax, %rdi
call _ZNSolsEPFRSoS_E.isra.0
movq 8(%rsp), %rdi
call cudaFree@PLT
movq %rbx, %rdi
call free@PLT
.L12:
orl $-1, %eax
jmp .L9
.L13:
movl $16777217, %edx
movl $536870913, %edi
xorl %r9d, %r9d
xorl %r8d, %r8d
salq $8, %rdx
salq $3, %rdi
movl $1, %ecx
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L15
movq 8(%rsp), %rdi
movl $2048, %esi
call _Z37__device_stub__Z16waveletTransformPfiPfi
.L15:
call cudaGetLastError@PLT
leaq .LC2(%rip), %rsi
movl %eax, %ebp
testl %eax, %eax
jne .L23
movq 8(%rsp), %rsi
movl $2, %ecx
movl $8192, %edx
movq %rbx, %rdi
call cudaMemcpy@PLT
leaq .LC3(%rip), %rsi
movl %eax, %ebp
testl %eax, %eax
jne .L23
leaq _ZSt4cout(%rip), %r12
leaq .LC4(%rip), %rsi
xorl %ebp, %ebp
movq %r12, %rdi
leaq .LC5(%rip), %r13
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@GOTPCREL(%rip), %rsi
movq %rax, %rdi
call _ZNSolsEPFRSoS_E.isra.0
.L18:
movq %r12, %rdi
cvtss2sd (%rbx,%rbp,4), %xmm0
incq %rbp
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %r13, %rsi
movq %rax, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
cmpq $10, %rbp
jne .L18
movq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@GOTPCREL(%rip), %rsi
movq %r12, %rdi
call _ZNSolsEPFRSoS_E.isra.0
movq 8(%rsp), %rdi
call cudaFree@PLT
movq %rbx, %rdi
call free@PLT
xorl %eax, %eax
.L9:
movq 40(%rsp), %rdx
subq %fs:40, %rdx
je .L19
call __stack_chk_fail@PLT
.L19:
addq $56, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE6832:
.size main, .-main
.section .rodata.str1.1
.LC6:
.string "_Z16waveletTransformPfi"
.LC7:
.string "_ZN50_INTERNAL_bb7d4521_19_cuda_code_058143_cu_27d318964cuda3std3__419piecewise_constructE"
.LC8:
.string "_ZN50_INTERNAL_bb7d4521_19_cuda_code_058143_cu_27d318964cuda3std6ranges3__45__cpo4swapE"
.LC9:
.string "_ZN50_INTERNAL_bb7d4521_19_cuda_code_058143_cu_27d318964cuda3std6ranges3__45__cpo9iter_moveE"
.section .text.startup
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB6860:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
pushq $0
.cfi_def_cfa_offset 24
xorl %r9d, %r9d
orl $-1, %r8d
pushq $0
.cfi_def_cfa_offset 32
leaq .LC6(%rip), %rdx
movq %rax, %rdi
movq %rax, %rbx
pushq $0
.cfi_def_cfa_offset 40
movq %rdx, %rcx
leaq _Z16waveletTransformPfi(%rip), %rsi
pushq $0
.cfi_def_cfa_offset 48
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq %rbx, %rdi
xorl %r8d, %r8d
pushq $0
.cfi_def_cfa_offset 24
leaq .LC7(%rip), %rdx
movl $1, %r9d
leaq _ZN4cuda3std3__419piecewise_constructE(%rip), %rsi
pushq $0
.cfi_def_cfa_offset 32
movq %rdx, %rcx
call __cudaRegisterVar@PLT
popq %rax
.cfi_def_cfa_offset 24
popq %rdx
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
leaq .LC8(%rip), %rdx
movq %rbx, %rdi
xorl %r8d, %r8d
movq %rdx, %rcx
movl $1, %r9d
leaq _ZN4cuda3std6ranges3__45__cpo4swapE(%rip), %rsi
call __cudaRegisterVar@PLT
popq %rcx
.cfi_def_cfa_offset 24
popq %rsi
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
leaq .LC9(%rip), %rdx
movq %rbx, %rdi
xorl %r8d, %r8d
movl $1, %r9d
movq %rdx, %rcx
leaq _ZN4cuda3std6ranges3__45__cpo9iter_moveE(%rip), %rsi
call __cudaRegisterVar@PLT
popq %rdi
.cfi_def_cfa_offset 24
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
popq %r8
.cfi_def_cfa_offset 16
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit@PLT
.cfi_endproc
.LFE6860:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.weak _ZN4cuda3std3__419piecewise_constructE
.section .rodata._ZN4cuda3std3__419piecewise_constructE,"aG",@progbits,_ZN4cuda3std3__419piecewise_constructE,comdat
.type _ZN4cuda3std3__419piecewise_constructE, @gnu_unique_object
.size _ZN4cuda3std3__419piecewise_constructE, 1
_ZN4cuda3std3__419piecewise_constructE:
.zero 1
.weak _ZN4cuda3std6ranges3__45__cpo9iter_moveE
.section .rodata._ZN4cuda3std6ranges3__45__cpo9iter_moveE,"aG",@progbits,_ZN4cuda3std6ranges3__45__cpo9iter_moveE,comdat
.type _ZN4cuda3std6ranges3__45__cpo9iter_moveE, @gnu_unique_object
.size _ZN4cuda3std6ranges3__45__cpo9iter_moveE, 1
_ZN4cuda3std6ranges3__45__cpo9iter_moveE:
.zero 1
.weak _ZN4cuda3std6ranges3__45__cpo4swapE
.section .rodata._ZN4cuda3std6ranges3__45__cpo4swapE,"aG",@progbits,_ZN4cuda3std6ranges3__45__cpo4swapE,comdat
.type _ZN4cuda3std6ranges3__45__cpo4swapE, @gnu_unique_object
.size _ZN4cuda3std6ranges3__45__cpo4swapE, 1
_ZN4cuda3std6ranges3__45__cpo4swapE:
.zero 1
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
```
|
```amdasm
.text
.file "cuda_code_058143.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z31__device_stub__waveletTransformPfi # -- Begin function _Z31__device_stub__waveletTransformPfi
.type _Z31__device_stub__waveletTransformPfi,@function
_Z31__device_stub__waveletTransformPfi: # @_Z31__device_stub__waveletTransformPfi
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $80, %rsp
.cfi_def_cfa_offset 128
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 24(%rsp), %rax
movq %rdi, (%rax)
leaq 4(%rsp), %rcx
movl %esi, (%rcx)
leaq 64(%rsp), %rbx
movq %rax, (%rbx)
movq %rcx, 8(%rbx)
leaq 48(%rsp), %r14
leaq 32(%rsp), %r15
leaq 16(%rsp), %r12
leaq 8(%rsp), %r13
movq %r14, %rdi
movq %r15, %rsi
movq %r12, %rdx
movq %r13, %rcx
callq __hipPopCallConfiguration
movq (%r14), %rsi
movl 8(%r14), %edx
movq (%r15), %rcx
movl 8(%r15), %r8d
movl $_Z16waveletTransformPfi, %edi
movq %rbx, %r9
pushq (%r13)
.cfi_adjust_cfa_offset 8
pushq (%r12)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $96, %rsp
.cfi_adjust_cfa_offset -96
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z31__device_stub__waveletTransformPfi, .Lfunc_end0-_Z31__device_stub__waveletTransformPfi
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $16, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %rbp, -16
movl $8192, %edi # imm = 0x2000
callq malloc
movq %rax, %rbx
xorl %eax, %eax
.LBB1_1: # =>This Inner Loop Header: Depth=1
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movss %xmm0, (%rbx,%rax,4)
incq %rax
cmpq $2048, %rax # imm = 0x800
jne .LBB1_1
# %bb.2:
leaq 8(%rsp), %rdi
movl $8192, %esi # imm = 0x2000
callq hipMalloc
testl %eax, %eax
je .LBB1_5
# %bb.3:
movl %eax, %ebp
movl $_ZSt4cerr, %edi
movl $.L.str, %esi
movl $32, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl %ebp, %edi
callq hipGetErrorString
testq %rax, %rax
je .LBB1_7
# %bb.4:
movq %rax, %rbx
movq %rax, %rdi
callq strlen
movl $_ZSt4cerr, %edi
movq %rbx, %rsi
movq %rax, %rdx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
jmp .LBB1_8
.LBB1_5:
movq 8(%rsp), %rdi
movl $8192, %edx # imm = 0x2000
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
je .LBB1_9
# %bb.6:
movl %eax, %ebp
movl $_ZSt4cerr, %edi
movl $.L.str.1, %esi
movl $32, %edx
jmp .LBB1_15
.LBB1_7:
movq _ZSt4cerr(%rip), %rax
movq -24(%rax), %rax
leaq _ZSt4cerr(%rax), %rdi
movl 32(%rdi), %esi
orl $1, %esi
callq _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate
.LBB1_8: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit
movq _ZSt4cerr(%rip), %rax
movl $_ZSt4cerr, %ecx
movq -24(%rax), %rdi
addq %rcx, %rdi
movl $10, %esi
callq _ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
movsbl %al, %esi
movl $_ZSt4cerr, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
jmp .LBB1_19
.LBB1_9:
movabsq $4294967304, %rdi # imm = 0x100000008
leaq 248(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_11
# %bb.10:
movq 8(%rsp), %rdi
movl $2048, %esi # imm = 0x800
callq _Z31__device_stub__waveletTransformPfi
.LBB1_11:
callq hipGetLastError
testl %eax, %eax
je .LBB1_13
# %bb.12:
movl %eax, %ebp
movl $_ZSt4cerr, %edi
movl $.L.str.2, %esi
movl $24, %edx
jmp .LBB1_15
.LBB1_13:
movq 8(%rsp), %rsi
movl $8192, %edx # imm = 0x2000
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
je .LBB1_21
# %bb.14:
movl %eax, %ebp
movl $_ZSt4cerr, %edi
movl $.L.str.3, %esi
movl $34, %edx
.LBB1_15:
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl %ebp, %edi
callq hipGetErrorString
testq %rax, %rax
je .LBB1_17
# %bb.16:
movq %rax, %r14
movq %rax, %rdi
callq strlen
movl $_ZSt4cerr, %edi
movq %r14, %rsi
movq %rax, %rdx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
jmp .LBB1_18
.LBB1_17:
movq _ZSt4cerr(%rip), %rax
movq -24(%rax), %rax
leaq _ZSt4cerr(%rax), %rdi
movl 32(%rdi), %esi
orl $1, %esi
callq _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate
.LBB1_18: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit47
movq _ZSt4cerr(%rip), %rax
movl $_ZSt4cerr, %ecx
movq -24(%rax), %rdi
addq %rcx, %rdi
movl $10, %esi
callq _ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
movsbl %al, %esi
movl $_ZSt4cerr, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq 8(%rsp), %rdi
callq hipFree
movq %rbx, %rdi
callq free
.LBB1_19:
movl $-1, %eax
.LBB1_20:
addq $16, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB1_21:
.cfi_def_cfa_offset 48
movl $_ZSt4cout, %edi
movl $.L.str.4, %esi
movl $39, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
callq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_
xorl %r14d, %r14d
.LBB1_22: # =>This Inner Loop Header: Depth=1
xorps %xmm0, %xmm0
cvtss2sd (%rbx,%r14,4), %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movl $.L.str.5, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
incq %r14
cmpq $10, %r14
jne .LBB1_22
# %bb.23:
movl $_ZSt4cout, %edi
callq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_
movq 8(%rsp), %rdi
callq hipFree
movq %rbx, %rdi
callq free
xorl %eax, %eax
jmp .LBB1_20
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, %rdi
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z16waveletTransformPfi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z16waveletTransformPfi,@object # @_Z16waveletTransformPfi
.section .rodata,"a",@progbits
.globl _Z16waveletTransformPfi
.p2align 3, 0x0
_Z16waveletTransformPfi:
.quad _Z31__device_stub__waveletTransformPfi
.size _Z16waveletTransformPfi, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Error allocating device memory: "
.size .L.str, 33
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Error copying memory to device: "
.size .L.str.1, 33
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Error launching kernel: "
.size .L.str.2, 25
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Error copying memory from device: "
.size .L.str.3, 35
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Transformed signal (first 10 elements):"
.size .L.str.4, 40
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz " "
.size .L.str.5, 2
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z16waveletTransformPfi"
.size .L__unnamed_1, 24
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z31__device_stub__waveletTransformPfi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z16waveletTransformPfi
.addrsig_sym _ZSt4cerr
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
```
| 4,888 | 4,774 |
113,668 |
Convert the following CUDA device assembly code to AMD device assembly:
```cudaasm
code for sm_80
Function : _Z16bubbleSortKernelPii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ;
S2R R2, SR_CTAID.X ;
IMAD.MOV.U32 R3, RZ, RZ, 0x4 ;
ULDC.64 UR8, c[0x0][0x118] ;
BSSY B0, 0xd0 ;
S2R R9, SR_TID.X ;
IMAD R2, R2, c[0x0][0x0], R9 ;
ISETP.GE.AND P0, PT, R2.reuse, c[0x0][0x168], PT ;
IMAD.WIDE R2, R2, R3, c[0x0][0x160] ;
@P0 BRA 0xc0 ;
LDG.E R0, [R2.64] ;
STS [R9.X4], R0 ;
BSYNC B0 ;
IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x168] ;
BAR.SYNC.DEFER_BLOCKING 0x0 ;
ISETP.GE.AND P1, PT, R0, 0x2, PT ;
@!P1 BRA 0x620 ;
IADD3 R4, R0.reuse, -0x2, RZ ;
UMOV UR4, URZ ;
IADD3 R0, R0, -0x1, RZ ;
ISETP.GE.U32.AND P1, PT, R4, 0x3, PT ;
LOP3.LUT R5, R0, 0x3, RZ, 0xc0, !PT ;
@!P1 BRA 0x510 ;
IMAD.IADD R6, R0, 0x1, -R5 ;
UMOV UR4, URZ ;
ULOP3.LUT UR5, URZ, UR4, URZ, 0x33, !UPT ;
BSSY B0, 0x250 ;
ULDC UR6, c[0x0][0x168] ;
UIADD3 UR5, UR5, UR6, URZ ;
ISETP.GE.AND P1, PT, R9, UR5, PT ;
@P1 BRA 0x240 ;
LDS R4, [R9.X4] ;
LDS R7, [R9.X4+0x4] ;
ISETP.GT.AND P1, PT, R4, R7, PT ;
@P1 STS [R9.X4], R7 ;
@P1 STS [R9.X4+0x4], R4 ;
BSYNC B0 ;
UIADD3 UR5, -UR4, -0x2, URZ ;
BAR.SYNC.DEFER_BLOCKING 0x0 ;
ULDC UR6, c[0x0][0x168] ;
BSSY B0, 0x320 ;
UIADD3 UR5, UR5, UR6, URZ ;
ISETP.GE.AND P1, PT, R9, UR5, PT ;
@P1 BRA 0x310 ;
LDS R4, [R9.X4] ;
LDS R7, [R9.X4+0x4] ;
ISETP.GT.AND P1, PT, R4, R7, PT ;
@P1 STS [R9.X4], R7 ;
@P1 STS [R9.X4+0x4], R4 ;
BSYNC B0 ;
UIADD3 UR5, -UR4, -0x3, URZ ;
BAR.SYNC.DEFER_BLOCKING 0x0 ;
ULDC UR6, c[0x0][0x168] ;
BSSY B0, 0x3f0 ;
UIADD3 UR5, UR5, UR6, URZ ;
ISETP.GE.AND P1, PT, R9, UR5, PT ;
@P1 BRA 0x3e0 ;
LDS R4, [R9.X4] ;
LDS R7, [R9.X4+0x4] ;
ISETP.GT.AND P1, PT, R4, R7, PT ;
@P1 STS [R9.X4], R7 ;
@P1 STS [R9.X4+0x4], R4 ;
BSYNC B0 ;
UIADD3 UR5, -UR4, -0x4, URZ ;
IADD3 R6, R6, -0x4, RZ ;
ULDC UR6, c[0x0][0x168] ;
BAR.SYNC.DEFER_BLOCKING 0x0 ;
UIADD3 UR5, UR5, UR6, URZ ;
ISETP.NE.AND P1, PT, R6, RZ, PT ;
BSSY B0, 0x4e0 ;
ISETP.GE.AND P2, PT, R9, UR5, PT ;
@P2 BRA 0x4d0 ;
LDS R4, [R9.X4] ;
LDS R7, [R9.X4+0x4] ;
ISETP.GT.AND P2, PT, R4, R7, PT ;
@P2 STS [R9.X4], R7 ;
@P2 STS [R9.X4+0x4], R4 ;
BSYNC B0 ;
BAR.SYNC.DEFER_BLOCKING 0x0 ;
UIADD3 UR4, UR4, 0x4, URZ ;
@P1 BRA 0x190 ;
ISETP.NE.AND P1, PT, R5, RZ, PT ;
@!P1 BRA 0x620 ;
IADD3 R0, R0, -UR4, RZ ;
ISETP.GE.AND P1, PT, R9, R0, PT ;
BSSY B0, 0x5d0 ;
@P1 BRA 0x5c0 ;
LDS R4, [R9.X4] ;
LDS R7, [R9.X4+0x4] ;
ISETP.GT.AND P1, PT, R4, R7, PT ;
@P1 STS [R9.X4], R7 ;
@P1 STS [R9.X4+0x4], R4 ;
BSYNC B0 ;
IADD3 R5, R5, -0x1, RZ ;
BAR.SYNC.DEFER_BLOCKING 0x0 ;
IADD3 R0, R0, -0x1, RZ ;
ISETP.NE.AND P1, PT, R5, RZ, PT ;
@P1 BRA 0x540 ;
@P0 EXIT ;
LDS R5, [R9.X4] ;
STG.E [R2.64], R5 ;
EXIT ;
BRA 0x660;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
```
|
```amdasm
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z16bubbleSortKernelPii ; -- Begin function _Z16bubbleSortKernelPii
.globl _Z16bubbleSortKernelPii
.p2align 8
.type _Z16bubbleSortKernelPii,@function
_Z16bubbleSortKernelPii: ; @_Z16bubbleSortKernelPii
; %bb.0:
s_clause 0x2
s_load_b32 s5, s[0:1], 0x1c
s_load_b32 s4, s[0:1], 0x8
s_load_b64 s[2:3], s[0:1], 0x0
v_lshl_add_u32 v5, v0, 2, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s0, s5, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s0, v[0:1]
v_cmp_gt_i32_e32 vcc_lo, s4, v1
v_ashrrev_i32_e32 v2, 31, v1
s_and_saveexec_b32 s1, vcc_lo
s_cbranch_execz .LBB0_2
; %bb.1:
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[1:2]
v_add_co_u32 v3, s0, s2, v3
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v4, s0, s3, v4, s0
global_load_b32 v3, v[3:4], off
s_waitcnt vmcnt(0)
ds_store_b32 v5, v3
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s1
s_cmp_lt_i32 s4, 2
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB0_8
; %bb.3: ; %.lr.ph
s_add_i32 s1, s4, -1
.LBB0_4: ; =>This Inner Loop Header: Depth=1
s_mov_b32 s4, exec_lo
v_cmpx_gt_i32_e64 s1, v0
s_cbranch_execz .LBB0_7
; %bb.5: ; in Loop: Header=BB0_4 Depth=1
ds_load_2addr_b32 v[3:4], v5 offset1:1
s_waitcnt lgkmcnt(0)
v_cmp_gt_i32_e64 s0, v3, v4
s_delay_alu instid0(VALU_DEP_1)
s_and_b32 exec_lo, exec_lo, s0
s_cbranch_execz .LBB0_7
; %bb.6: ; in Loop: Header=BB0_4 Depth=1
ds_store_2addr_b32 v5, v4, v3 offset1:1
.LBB0_7: ; in Loop: Header=BB0_4 Depth=1
s_or_b32 exec_lo, exec_lo, s4
s_add_i32 s1, s1, -1
s_waitcnt lgkmcnt(0)
s_cmp_eq_u32 s1, 0
s_barrier
buffer_gl0_inv
s_cbranch_scc0 .LBB0_4
.LBB0_8: ; %._crit_edge
s_and_saveexec_b32 s0, vcc_lo
s_cbranch_execz .LBB0_10
; %bb.9:
ds_load_b32 v3, v5
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
s_waitcnt lgkmcnt(0)
global_store_b32 v[0:1], v3, off
.LBB0_10:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z16bubbleSortKernelPii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z16bubbleSortKernelPii, .Lfunc_end0-_Z16bubbleSortKernelPii
; -- End function
.section .AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 312
; NumSgprs: 18
; NumVgprs: 6
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 6
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object ; @__hip_cuid_
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0 ; 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
- .offset: 136
.size: 4
.value_kind: hidden_dynamic_lds_size
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z16bubbleSortKernelPii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z16bubbleSortKernelPii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
```
| 1,639 | 2,963 |
113,669 |
Convert the following CUDA host assembly code to AMD host assembly:
```cudaasm
.file "tmpxft_00017bdd_00000000-6_cuda_code_027150.cudafe1.cpp"
.text
.globl _ZSt21ios_base_library_initv
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3639:
.cfi_startproc
endbr64
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
jmp __cudaUnregisterFatBinary@PLT
.cfi_endproc
.LFE3639:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "CUDA error: "
.LC2:
.string " - "
.text
.globl _Z14checkCudaError9cudaErrorPKc
.type _Z14checkCudaError9cudaErrorPKc, @function
_Z14checkCudaError9cudaErrorPKc:
.LFB3635:
.cfi_startproc
endbr64
testl %edi, %edi
je .L2
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
movq %rsi, %rbp
leaq .LC1(%rip), %rsi
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
movl %edi, %ebx
leaq _ZSt4cerr(%rip), %rdi
pushq %rax
.cfi_def_cfa_offset 32
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rbp, %rsi
movq %rax, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
leaq .LC2(%rip), %rsi
movq %rax, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movl %ebx, %edi
movq %rax, %rbp
call cudaGetErrorString@PLT
movq %rbp, %rdi
movq %rax, %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $1, %edi
call exit@PLT
.L2:
.cfi_def_cfa_offset 8
.cfi_restore 3
.cfi_restore 6
ret
.cfi_endproc
.LFE3635:
.size _Z14checkCudaError9cudaErrorPKc, .-_Z14checkCudaError9cudaErrorPKc
.globl _Z37__device_stub__Z16bubbleSortKernelPiiPii
.type _Z37__device_stub__Z16bubbleSortKernelPiiPii, @function
_Z37__device_stub__Z16bubbleSortKernelPiiPii:
.LFB3661:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
leaq 32(%rsp), %rcx
leaq 24(%rsp), %rdx
movl %esi, 4(%rsp)
leaq 40(%rsp), %rdi
leaq 52(%rsp), %rsi
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movl $1, 48(%rsp)
movq %rax, 88(%rsp)
leaq 4(%rsp), %rax
movq %rax, 96(%rsp)
movabsq $4294967297, %rax
movq %rax, 40(%rsp)
movq %rax, 52(%rsp)
movl $1, 60(%rsp)
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
jne .L8
pushq 32(%rsp)
.cfi_def_cfa_offset 136
leaq _Z16bubbleSortKernelPii(%rip), %rdi
pushq 32(%rsp)
.cfi_def_cfa_offset 144
movq 68(%rsp), %rcx
movl 76(%rsp), %r8d
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
leaq 104(%rsp), %r9
call cudaLaunchKernel@PLT
popq %rax
.cfi_def_cfa_offset 136
popq %rdx
.cfi_def_cfa_offset 128
.L8:
movq 104(%rsp), %rax
subq %fs:40, %rax
je .L10
call __stack_chk_fail@PLT
.L10:
addq $120, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3661:
.size _Z37__device_stub__Z16bubbleSortKernelPiiPii, .-_Z37__device_stub__Z16bubbleSortKernelPiiPii
.globl _Z16bubbleSortKernelPii
.type _Z16bubbleSortKernelPii, @function
_Z16bubbleSortKernelPii:
.LFB3662:
.cfi_startproc
endbr64
jmp _Z37__device_stub__Z16bubbleSortKernelPiiPii
.cfi_endproc
.LFE3662:
.size _Z16bubbleSortKernelPii, .-_Z16bubbleSortKernelPii
.section .rodata.str1.1
.LC3:
.string "Kernel launch failed"
.LC4:
.string "Device synchronization failed"
.LC5:
.string "Sorted data: "
.LC6:
.string " "
.section .rodata
.align 32
.LC0:
.long 32
.long 17
.long 24
.long 3
.long 13
.long 8
.long 29
.long 6
.long 31
.long 21
.long 15
.long 19
.long 5
.long 23
.long 11
.long 30
.long 7
.long 20
.long 12
.long 27
.long 9
.long 18
.long 26
.long 4
.long 28
.long 10
.long 16
.long 14
.long 22
.long 2
.long 25
.long 1
.section .text.startup,"ax",@progbits
.globl main
.type main, @function
main:
.LFB3636:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
leaq .LC0(%rip), %rsi
movl $32, %ecx
movabsq $4294967312, %r14
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
xorl %ebx, %ebx
subq $176, %rsp
.cfi_def_cfa_offset 224
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rdi
leaq 24(%rsp), %r13
rep movsl
xorl %edi, %edi
leaq 40(%rsp), %r12
leaq 104(%rsp), %rbp
call cudaSetDevice@PLT
movl $64, %esi
movq %r13, %rdi
call cudaMalloc@PLT
movq 24(%rsp), %rdi
movl $1, %ecx
movq %r12, %rsi
movl $64, %edx
call cudaMemcpy@PLT
movl $1, %edi
call cudaSetDevice@PLT
leaq 32(%rsp), %rdi
movl $64, %esi
call cudaMalloc@PLT
movq 32(%rsp), %rdi
movl $1, %ecx
movq %rbp, %rsi
movl $64, %edx
call cudaMemcpy@PLT
.L15:
movl %ebx, %edi
call cudaSetDevice@PLT
xorl %r9d, %r9d
movq %r14, %rdx
movl $1, %ecx
movl $64, %r8d
movl $1, %esi
movabsq $4294967297, %rdi
movq %r14, 12(%rsp)
movl $1, 20(%rsp)
movq %rdi, (%rsp)
movl $1, 8(%rsp)
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L14
movq 0(%r13,%rbx,8), %rdi
movl $16, %esi
call _Z37__device_stub__Z16bubbleSortKernelPiiPii
.L14:
call cudaGetLastError@PLT
leaq .LC3(%rip), %rsi
movl %eax, %edi
call _Z14checkCudaError9cudaErrorPKc
call cudaDeviceSynchronize@PLT
leaq .LC4(%rip), %rsi
movl %eax, %edi
call _Z14checkCudaError9cudaErrorPKc
testq %rbx, %rbx
jne .L21
movl $1, %ebx
jmp .L15
.L21:
xorl %edi, %edi
xorl %ebx, %ebx
leaq .LC6(%rip), %r13
call cudaSetDevice@PLT
movq 24(%rsp), %rsi
movl $2, %ecx
movq %r12, %rdi
movl $64, %edx
call cudaMemcpy@PLT
movl $1, %edi
call cudaSetDevice@PLT
movq 32(%rsp), %rsi
movq %rbp, %rdi
movl $2, %ecx
movl $64, %edx
leaq _ZSt4cout(%rip), %rbp
call cudaMemcpy@PLT
leaq .LC5(%rip), %rsi
movq %rbp, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
.L16:
movl (%r12,%rbx,4), %esi
movq %rbp, %rdi
incq %rbx
call _ZNSolsEi@PLT
movq %r13, %rsi
movq %rax, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
cmpq $32, %rbx
jne .L16
movq %rbp, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
xorl %edi, %edi
call cudaSetDevice@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movl $1, %edi
call cudaSetDevice@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 168(%rsp), %rax
subq %fs:40, %rax
je .L17
call __stack_chk_fail@PLT
.L17:
addq $176, %rsp
.cfi_def_cfa_offset 48
xorl %eax, %eax
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3636:
.size main, .-main
.section .rodata.str1.1
.LC7:
.string "_Z16bubbleSortKernelPii"
.section .text.startup
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3664:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
pushq $0
.cfi_def_cfa_offset 24
xorl %r9d, %r9d
orl $-1, %r8d
pushq $0
.cfi_def_cfa_offset 32
leaq .LC7(%rip), %rdx
movq %rax, %rdi
leaq _Z16bubbleSortKernelPii(%rip), %rsi
pushq $0
.cfi_def_cfa_offset 40
movq %rdx, %rcx
pushq $0
.cfi_def_cfa_offset 48
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFunction@PLT
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
addq $32, %rsp
.cfi_def_cfa_offset 16
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
popq %rdx
.cfi_def_cfa_offset 8
jmp atexit@PLT
.cfi_endproc
.LFE3664:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
```
|
```amdasm
.text
.file "cuda_code_027150.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z31__device_stub__bubbleSortKernelPii # -- Begin function _Z31__device_stub__bubbleSortKernelPii
.type _Z31__device_stub__bubbleSortKernelPii,@function
_Z31__device_stub__bubbleSortKernelPii: # @_Z31__device_stub__bubbleSortKernelPii
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $80, %rsp
.cfi_def_cfa_offset 128
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 24(%rsp), %rax
movq %rdi, (%rax)
leaq 4(%rsp), %rcx
movl %esi, (%rcx)
leaq 64(%rsp), %rbx
movq %rax, (%rbx)
movq %rcx, 8(%rbx)
leaq 48(%rsp), %r14
leaq 32(%rsp), %r15
leaq 16(%rsp), %r12
leaq 8(%rsp), %r13
movq %r14, %rdi
movq %r15, %rsi
movq %r12, %rdx
movq %r13, %rcx
callq __hipPopCallConfiguration
movq (%r14), %rsi
movl 8(%r14), %edx
movq (%r15), %rcx
movl 8(%r15), %r8d
movl $_Z16bubbleSortKernelPii, %edi
movq %rbx, %r9
pushq (%r13)
.cfi_adjust_cfa_offset 8
pushq (%r12)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $96, %rsp
.cfi_adjust_cfa_offset -96
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z31__device_stub__bubbleSortKernelPii, .Lfunc_end0-_Z31__device_stub__bubbleSortKernelPii
.cfi_endproc
# -- End function
.globl _Z14checkCudaError10hipError_tPKc # -- Begin function _Z14checkCudaError10hipError_tPKc
.type _Z14checkCudaError10hipError_tPKc,@function
_Z14checkCudaError10hipError_tPKc: # @_Z14checkCudaError10hipError_tPKc
.cfi_startproc
# %bb.0:
testl %edi, %edi
jne .LBB1_2
# %bb.1:
retq
.LBB1_2:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
pushq %rax
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movq %rsi, %r14
movl %edi, %ebx
movl $_ZSt4cerr, %edi
movl $.L.str, %esi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movq %rax, %rdi
movq %r14, %rsi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movl $.L.str.1, %esi
movq %rax, %rdi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movq %rax, %r14
movl %ebx, %edi
callq hipGetErrorString
movq %r14, %rdi
movq %rax, %rsi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movq %rax, %rdi
callq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_
movl $1, %edi
callq exit
.Lfunc_end1:
.size _Z14checkCudaError10hipError_tPKc, .Lfunc_end1-_Z14checkCudaError10hipError_tPKc
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.type main,@function
main: # @main
.cfi_startproc
# %bb.0: # %.preheader33.preheader.critedge
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $144, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movabsq $4294967297, %rbx # imm = 0x100000001
leaq 16(%rsp), %r14
movl $16, %ecx
movl $.L__const.main.data, %esi
movq %r14, %rdi
rep;movsq (%rsi), %es:(%rdi)
xorl %r15d, %r15d
xorl %edi, %edi
callq hipSetDevice
movq %rsp, %r12
movl $64, %esi
movq %r12, %rdi
callq hipMalloc
movq (%r12), %rdi
movl $64, %edx
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movl $1, %edi
callq hipSetDevice
leaq 80(%rsp), %r14
leaq 8(%rsp), %r12
movl $64, %esi
movq %r12, %rdi
callq hipMalloc
movq (%r12), %rdi
movl $64, %edx
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movb $1, %bpl
leaq 15(%rbx), %r12
.LBB2_1: # %.preheader33
# =>This Inner Loop Header: Depth=1
movl %r15d, %edi
callq hipSetDevice
movl $64, %r8d
movq %rbx, %rdi
movl $1, %esi
movq %r12, %rdx
movl $1, %ecx
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_3
# %bb.2: # in Loop: Header=BB2_1 Depth=1
movq (%rsp,%r15,8), %rdi
movl $16, %esi
callq _Z31__device_stub__bubbleSortKernelPii
.LBB2_3: # in Loop: Header=BB2_1 Depth=1
callq hipGetLastError
movl $.L.str.2, %esi
movl %eax, %edi
callq _Z14checkCudaError10hipError_tPKc
callq hipDeviceSynchronize
movl $.L.str.3, %esi
movl %eax, %edi
callq _Z14checkCudaError10hipError_tPKc
movl $1, %r15d
testb $1, %bpl
movl $0, %ebp
jne .LBB2_1
# %bb.4: # %.preheader
xorl %ebx, %ebx
xorl %edi, %edi
callq hipSetDevice
movq (%rsp), %rsi
leaq 16(%rsp), %rdi
movl $64, %edx
movl $2, %ecx
callq hipMemcpy
movl $1, %edi
callq hipSetDevice
movq 8(%rsp), %rsi
movl $64, %edx
movq %r14, %rdi
movl $2, %ecx
callq hipMemcpy
movl $_ZSt4cout, %edi
movl $.L.str.4, %esi
movl $13, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.LBB2_5: # =>This Inner Loop Header: Depth=1
movl 16(%rsp,%rbx,4), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movl $.L.str.5, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
incq %rbx
cmpq $32, %rbx
jne .LBB2_5
# %bb.6: # %.critedge53
movq _ZSt4cout(%rip), %rax
movl $_ZSt4cout, %ecx
movq -24(%rax), %rdi
addq %rcx, %rdi
movl $10, %esi
callq _ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
xorl %edi, %edi
callq hipSetDevice
movq (%rsp), %rdi
callq hipFree
movl $1, %edi
callq hipSetDevice
movq 8(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $144, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, %rdi
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z16bubbleSortKernelPii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z16bubbleSortKernelPii,@object # @_Z16bubbleSortKernelPii
.section .rodata,"a",@progbits
.globl _Z16bubbleSortKernelPii
.p2align 3, 0x0
_Z16bubbleSortKernelPii:
.quad _Z31__device_stub__bubbleSortKernelPii
.size _Z16bubbleSortKernelPii, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "CUDA error: "
.size .L.str, 13
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz " - "
.size .L.str.1, 4
.type .L__const.main.data,@object # @__const.main.data
.section .rodata,"a",@progbits
.p2align 4, 0x0
.L__const.main.data:
.long 32 # 0x20
.long 17 # 0x11
.long 24 # 0x18
.long 3 # 0x3
.long 13 # 0xd
.long 8 # 0x8
.long 29 # 0x1d
.long 6 # 0x6
.long 31 # 0x1f
.long 21 # 0x15
.long 15 # 0xf
.long 19 # 0x13
.long 5 # 0x5
.long 23 # 0x17
.long 11 # 0xb
.long 30 # 0x1e
.long 7 # 0x7
.long 20 # 0x14
.long 12 # 0xc
.long 27 # 0x1b
.long 9 # 0x9
.long 18 # 0x12
.long 26 # 0x1a
.long 4 # 0x4
.long 28 # 0x1c
.long 10 # 0xa
.long 16 # 0x10
.long 14 # 0xe
.long 22 # 0x16
.long 2 # 0x2
.long 25 # 0x19
.long 1 # 0x1
.size .L__const.main.data, 128
.type .L.str.2,@object # @.str.2
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.2:
.asciz "Kernel launch failed"
.size .L.str.2, 21
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Device synchronization failed"
.size .L.str.3, 30
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Sorted data: "
.size .L.str.4, 14
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz " "
.size .L.str.5, 2
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z16bubbleSortKernelPii"
.size .L__unnamed_1, 24
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z31__device_stub__bubbleSortKernelPii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z16bubbleSortKernelPii
.addrsig_sym _ZSt4cerr
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
```
| 4,138 | 5,016 |
113,670 |
Convert the following CUDA device assembly code to AMD device assembly:
```cudaasm
code for sm_80
Function : _Z23sparseConvolutionKernelPKfPKiS0_S2_Pfiiii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ;
S2R R2, SR_CTAID.Y ;
ULDC.64 UR4, c[0x0][0x118] ;
BSSY B0, 0x3b0 ;
S2R R5, SR_TID.Y ;
S2R R3, SR_CTAID.X ;
S2R R0, SR_TID.X ;
IMAD R2, R2, c[0x0][0x4], R5 ;
ISETP.GE.AND P0, PT, R2, c[0x0][0x18c], PT ;
IMAD R3, R3, c[0x0][0x0], R0 ;
IMAD.MOV.U32 R0, RZ, RZ, RZ ;
ISETP.GE.OR P0, PT, R3, c[0x0][0x188], P0 ;
@P0 BRA 0x3a0 ;
MOV R8, c[0x0][0x194] ;
IMAD R8, R8, c[0x0][0x190], RZ ;
ISETP.GE.AND P0, PT, R8, 0x1, PT ;
@!P0 BRA 0x3a0 ;
IMAD.MOV.U32 R9, RZ, RZ, c[0x0][0x18c] ;
IMAD R9, R9, c[0x0][0x188], RZ ;
ISETP.GE.AND P0, PT, R9, 0x1, PT ;
@!P0 BRA 0x3a0 ;
HFMA2.MMA R0, -RZ, RZ, 0, 0 ;
IMAD.MOV.U32 R11, RZ, RZ, RZ ;
SHF.L.U32 R4, R11, 0x1, RZ ;
IMAD.MOV.U32 R5, RZ, RZ, 0x4 ;
IMAD.WIDE R4, R4, R5, c[0x0][0x178] ;
LDG.E.CONSTANT R7, [R4.64+0x4] ;
LDG.E.CONSTANT R6, [R4.64] ;
BSSY B1, 0x370 ;
IMAD.IADD R13, R2, 0x1, -R7 ;
IADD3 R12, R3, -R6, RZ ;
LOP3.LUT R6, R13, R12, RZ, 0xfc, !PT ;
ISETP.GE.AND P0, PT, R6, RZ, PT ;
ISETP.GE.OR P0, PT, R12, c[0x0][0x188], !P0 ;
ISETP.GE.OR P0, PT, R13, c[0x0][0x18c], P0 ;
@P0 BRA 0x360 ;
MOV R6, RZ ;
HFMA2.MMA R15, -RZ, RZ, 0, 2.384185791015625e-07 ;
IMAD.SHL.U32 R4, R6, 0x2, RZ ;
IMAD.WIDE R4, R4, R15, c[0x0][0x168] ;
LDG.E.CONSTANT R7, [R4.64] ;
LDG.E.CONSTANT R10, [R4.64+0x4] ;
ISETP.EQ.AND P1, PT, R7, R12, PT ;
ISETP.NE.AND P0, PT, R10, R13, PT ;
@!P0 BRA P1, 0x310 ;
IADD3 R6, R6, 0x1, RZ ;
ISETP.GE.AND P0, PT, R6, R9, PT ;
@!P0 BRA 0x250 ;
BRA 0x360 ;
IMAD.WIDE R4, R6, R15, c[0x0][0x160] ;
IMAD.WIDE R6, R11, R15, c[0x0][0x170] ;
LDG.E.CONSTANT R4, [R4.64] ;
LDG.E.CONSTANT R7, [R6.64] ;
FFMA R0, R7, R4, R0 ;
BSYNC B1 ;
IADD3 R11, R11, 0x1, RZ ;
ISETP.GE.AND P0, PT, R11, R8, PT ;
@!P0 BRA 0x170 ;
BSYNC B0 ;
IMAD.MOV.U32 R5, RZ, RZ, 0x4 ;
IMAD R2, R2, c[0x0][0x188], R3 ;
IMAD.WIDE R2, R2, R5, c[0x0][0x180] ;
STG.E [R2.64], R0 ;
EXIT ;
BRA 0x400;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
```
|
```amdasm
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z23sparseConvolutionKernelPKfPKiS0_S2_Pfiiii ; -- Begin function _Z23sparseConvolutionKernelPKfPKiS0_S2_Pfiiii
.globl _Z23sparseConvolutionKernelPKfPKiS0_S2_Pfiiii
.p2align 8
.type _Z23sparseConvolutionKernelPKfPKiS0_S2_Pfiiii,@function
_Z23sparseConvolutionKernelPKfPKiS0_S2_Pfiiii: ; @_Z23sparseConvolutionKernelPKfPKiS0_S2_Pfiiii
; %bb.0:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x44
s_load_b128 s[16:19], s[0:1], 0x28
s_load_b64 s[12:13], s[0:1], 0x20
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_lshr_b32 s3, s2, 16
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[0:1], null, s14, s2, v[2:3]
v_mad_u64_u32 v[1:2], null, s15, s3, v[3:4]
v_mov_b32_e32 v2, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cmp_gt_i32_e32 vcc_lo, s16, v0
v_cmp_gt_i32_e64 s2, s17, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, s2, vcc_lo
s_and_saveexec_b32 s22, s2
s_cbranch_execz .LBB0_15
; %bb.1: ; %.preheader63
s_mul_i32 s23, s19, s18
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_lt_i32 s23, 1
s_cbranch_scc1 .LBB0_14
; %bb.2: ; %.lr.ph72
s_load_b256 s[4:11], s[0:1], 0x0
s_mul_i32 s24, s17, s16
v_mov_b32_e32 v2, 0
s_cmp_lt_i32 s24, 1
s_mov_b32 s3, 0
s_cselect_b32 s25, -1, 0
s_mov_b32 s14, s3
s_waitcnt lgkmcnt(0)
s_add_u32 s6, s6, 4
s_addc_u32 s7, s7, 0
.LBB0_3: ; =>This Loop Header: Depth=1
; Child Loop BB0_6 Depth 2
s_lshl_b32 s2, s14, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_lshl_b64 s[0:1], s[2:3], 2
s_mov_b32 s2, exec_lo
s_add_u32 s0, s10, s0
s_addc_u32 s1, s11, s1
s_load_b64 s[0:1], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
v_subrev_nc_u32_e32 v3, s0, v0
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_lt_i32_e32 -1, v3
s_cbranch_execz .LBB0_13
; %bb.4: ; in Loop: Header=BB0_3 Depth=1
v_subrev_nc_u32_e32 v4, s1, v1
v_cmp_le_i32_e32 vcc_lo, s16, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cmp_le_i32_e64 s0, s17, v4
v_cmp_gt_i32_e64 s1, 0, v4
s_or_b32 s0, vcc_lo, s0
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
s_or_b32 s0, s0, s1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_or_b32 s0, s0, s25
s_xor_b32 s0, s0, -1
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s26, s0
s_cbranch_execz .LBB0_12
; %bb.5: ; %.lr.ph
; in Loop: Header=BB0_3 Depth=1
s_mov_b32 s15, s3
s_mov_b32 s27, 1
s_lshl_b64 s[0:1], s[14:15], 2
s_mov_b32 s15, 0
s_add_u32 s0, s8, s0
s_addc_u32 s1, s9, s1
s_mov_b64 s[18:19], s[4:5]
s_mov_b64 s[20:21], s[6:7]
; implicit-def: $sgpr28
.LBB0_6: ; Parent Loop BB0_3 Depth=1
; => This Inner Loop Header: Depth=2
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s30, s20, -4
s_addc_u32 s31, s21, -1
s_or_b32 s28, s28, exec_lo
s_load_b32 s29, s[30:31], 0x0
s_waitcnt lgkmcnt(0)
v_cmp_eq_u32_e32 vcc_lo, s29, v3
s_and_saveexec_b32 s29, vcc_lo
s_cbranch_execz .LBB0_10
; %bb.7: ; in Loop: Header=BB0_6 Depth=2
s_load_b32 s30, s[20:21], 0x0
s_waitcnt lgkmcnt(0)
v_cmp_eq_u32_e32 vcc_lo, s30, v4
s_mov_b32 s30, -1
s_and_saveexec_b32 s31, vcc_lo
s_cbranch_execz .LBB0_9
; %bb.8: ; in Loop: Header=BB0_6 Depth=2
s_load_b32 s30, s[18:19], 0x0
s_load_b32 s33, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
v_fmac_f32_e64 v2, s30, s33
s_xor_b32 s30, exec_lo, -1
.LBB0_9: ; %Flow
; in Loop: Header=BB0_6 Depth=2
s_or_b32 exec_lo, exec_lo, s31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_and_not1_b32 s28, s28, exec_lo
s_and_b32 s30, s30, exec_lo
s_or_b32 s28, s28, s30
.LBB0_10: ; in Loop: Header=BB0_6 Depth=2
s_or_b32 exec_lo, exec_lo, s29
s_cmp_ge_i32 s27, s24
s_cselect_b32 s29, -1, 0
s_xor_b32 s30, s28, -1
s_add_i32 s27, s27, 1
s_or_b32 s29, s30, s29
s_add_u32 s20, s20, 8
s_addc_u32 s21, s21, 0
s_add_u32 s18, s18, 4
s_addc_u32 s19, s19, 0
s_and_b32 s29, exec_lo, s29
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_or_b32 s15, s29, s15
s_and_not1_b32 exec_lo, exec_lo, s15
s_cbranch_execnz .LBB0_6
; %bb.11: ; %Flow94
; in Loop: Header=BB0_3 Depth=1
s_or_b32 exec_lo, exec_lo, s15
.LBB0_12: ; %Flow95
; in Loop: Header=BB0_3 Depth=1
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s26
.LBB0_13: ; %.loopexit
; in Loop: Header=BB0_3 Depth=1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s2
s_add_i32 s14, s14, 1
s_cmp_lg_u32 s14, s23
s_cbranch_scc1 .LBB0_3
s_branch .LBB0_15
.LBB0_14:
v_mov_b32_e32 v2, 0
.LBB0_15: ; %.loopexit64
s_or_b32 exec_lo, exec_lo, s22
v_mad_u64_u32 v[3:4], null, v1, s16, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v4, 31, v3
v_lshlrev_b64 v[0:1], 2, v[3:4]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s12, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s13, v1, vcc_lo
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z23sparseConvolutionKernelPKfPKiS0_S2_Pfiiii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 312
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 34
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z23sparseConvolutionKernelPKfPKiS0_S2_Pfiiii, .Lfunc_end0-_Z23sparseConvolutionKernelPKfPKiS0_S2_Pfiiii
; -- End function
.section .AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 608
; NumSgprs: 36
; NumVgprs: 5
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 4
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 36
; NumVGPRsForWavesPerEU: 5
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object ; @__hip_cuid_
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0 ; 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .actual_access: read_only
.address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .actual_access: read_only
.address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .actual_access: read_only
.address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .actual_access: read_only
.address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .actual_access: write_only
.address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .offset: 40
.size: 4
.value_kind: by_value
- .offset: 44
.size: 4
.value_kind: by_value
- .offset: 48
.size: 4
.value_kind: by_value
- .offset: 52
.size: 4
.value_kind: by_value
- .offset: 56
.size: 4
.value_kind: hidden_block_count_x
- .offset: 60
.size: 4
.value_kind: hidden_block_count_y
- .offset: 64
.size: 4
.value_kind: hidden_block_count_z
- .offset: 68
.size: 2
.value_kind: hidden_group_size_x
- .offset: 70
.size: 2
.value_kind: hidden_group_size_y
- .offset: 72
.size: 2
.value_kind: hidden_group_size_z
- .offset: 74
.size: 2
.value_kind: hidden_remainder_x
- .offset: 76
.size: 2
.value_kind: hidden_remainder_y
- .offset: 78
.size: 2
.value_kind: hidden_remainder_z
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 112
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 120
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 312
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z23sparseConvolutionKernelPKfPKiS0_S2_Pfiiii
.private_segment_fixed_size: 0
.sgpr_count: 36
.sgpr_spill_count: 0
.symbol: _Z23sparseConvolutionKernelPKfPKiS0_S2_Pfiiii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
```
| 1,324 | 4,939 |
113,671 |
Convert the following CUDA host assembly code to AMD host assembly:
```cudaasm
.file "tmpxft_000d2472_00000000-6_cuda_code_018401.cudafe1.cpp"
.text
.globl _ZSt21ios_base_library_initv
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB6836:
.cfi_startproc
endbr64
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
jmp __cudaUnregisterFatBinary@PLT
.cfi_endproc
.LFE6836:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "CUDA error: "
.LC1:
.string " ("
.LC2:
.string ")"
.text
.globl _Z14checkCudaError9cudaErrorPKc
.type _Z14checkCudaError9cudaErrorPKc, @function
_Z14checkCudaError9cudaErrorPKc:
.LFB6832:
.cfi_startproc
endbr64
testl %edi, %edi
je .L2
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
movq %rsi, %rbp
leaq .LC0(%rip), %rsi
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
movl %edi, %ebx
leaq _ZSt4cerr(%rip), %rdi
pushq %rax
.cfi_def_cfa_offset 32
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rbp, %rsi
movq %rax, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
leaq .LC1(%rip), %rsi
movq %rax, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movl %ebx, %edi
movq %rax, %rbp
call cudaGetErrorString@PLT
movq %rbp, %rdi
movq %rax, %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
leaq .LC2(%rip), %rsi
movq %rax, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $1, %edi
call exit@PLT
.L2:
.cfi_def_cfa_offset 8
.cfi_restore 3
.cfi_restore 6
ret
.cfi_endproc
.LFE6832:
.size _Z14checkCudaError9cudaErrorPKc, .-_Z14checkCudaError9cudaErrorPKc
.globl _Z59__device_stub__Z23sparseConvolutionKernelPKfPKiS0_S2_PfiiiiPKfPKiS0_S2_Pfiiii
.type _Z59__device_stub__Z23sparseConvolutionKernelPKfPKiS0_S2_PfiiiiPKfPKiS0_S2_Pfiiii, @function
_Z59__device_stub__Z23sparseConvolutionKernelPKfPKiS0_S2_PfiiiiPKfPKiS0_S2_Pfiiii:
.LFB6858:
.cfi_startproc
endbr64
subq $216, %rsp
.cfi_def_cfa_offset 224
movl %r9d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 200(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rdi, 24(%rsp)
leaq 80(%rsp), %rdi
movq %rax, 128(%rsp)
leaq 32(%rsp), %rax
movq %rax, 136(%rsp)
leaq 40(%rsp), %rax
movq %rax, 144(%rsp)
leaq 48(%rsp), %rax
movq %rax, 152(%rsp)
leaq 56(%rsp), %rax
movq %rax, 160(%rsp)
leaq 12(%rsp), %rax
movq %rax, 168(%rsp)
leaq 224(%rsp), %rax
movq %rax, 176(%rsp)
leaq 232(%rsp), %rax
movq %rax, 184(%rsp)
leaq 240(%rsp), %rax
movq %rsi, 32(%rsp)
leaq 92(%rsp), %rsi
movq %rdx, 40(%rsp)
leaq 64(%rsp), %rdx
movq %rcx, 48(%rsp)
leaq 72(%rsp), %rcx
movq %rax, 192(%rsp)
movabsq $4294967297, %rax
movq %r8, 56(%rsp)
movq %rax, 80(%rsp)
movl $1, 88(%rsp)
movq %rax, 92(%rsp)
movl $1, 100(%rsp)
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
jne .L8
pushq 72(%rsp)
.cfi_def_cfa_offset 232
leaq _Z23sparseConvolutionKernelPKfPKiS0_S2_Pfiiii(%rip), %rdi
pushq 72(%rsp)
.cfi_def_cfa_offset 240
movq 108(%rsp), %rcx
movl 116(%rsp), %r8d
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
leaq 144(%rsp), %r9
call cudaLaunchKernel@PLT
popq %rax
.cfi_def_cfa_offset 232
popq %rdx
.cfi_def_cfa_offset 224
.L8:
movq 200(%rsp), %rax
subq %fs:40, %rax
je .L10
call __stack_chk_fail@PLT
.L10:
addq $216, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE6858:
.size _Z59__device_stub__Z23sparseConvolutionKernelPKfPKiS0_S2_PfiiiiPKfPKiS0_S2_Pfiiii, .-_Z59__device_stub__Z23sparseConvolutionKernelPKfPKiS0_S2_PfiiiiPKfPKiS0_S2_Pfiiii
.globl _Z23sparseConvolutionKernelPKfPKiS0_S2_Pfiiii
.type _Z23sparseConvolutionKernelPKfPKiS0_S2_Pfiiii, @function
_Z23sparseConvolutionKernelPKfPKiS0_S2_Pfiiii:
.LFB6859:
.cfi_startproc
endbr64
jmp _Z59__device_stub__Z23sparseConvolutionKernelPKfPKiS0_S2_PfiiiiPKfPKiS0_S2_Pfiiii
.cfi_endproc
.LFE6859:
.size _Z23sparseConvolutionKernelPKfPKiS0_S2_Pfiiii, .-_Z23sparseConvolutionKernelPKfPKiS0_S2_Pfiiii
.section .rodata.str1.1
.LC4:
.string "cudaMalloc d_input"
.LC5:
.string "cudaMalloc d_inputIndices"
.LC6:
.string "cudaMalloc d_filter"
.LC7:
.string "cudaMalloc d_filterIndices"
.LC8:
.string "cudaMalloc d_output"
.LC9:
.string "cudaMemcpy d_input"
.LC10:
.string "cudaMemcpy d_inputIndices"
.LC11:
.string "cudaMemcpy d_filter"
.LC12:
.string "cudaMemcpy d_filterIndices"
.LC13:
.string "Kernel launch failed"
.LC14:
.string "cudaMemcpy h_output"
.LC15:
.string "Sparse convolution completed successfully."
.section .text.startup,"ax",@progbits
.globl main
.type main, @function
main:
.LFB6833:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
movl $268435456, %edi
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $80, %rsp
.cfi_def_cfa_offset 128
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
call _Znam@PLT
movl $536870912, %edi
movq %rax, %r13
call _Znam@PLT
movl $36, %edi
movq %rax, %rbp
call _Znam@PLT
movl $72, %edi
movq %rax, %r12
call _Znam@PLT
movl $268435456, %edi
movq %rax, %rbx
call _Znam@PLT
movss .LC3(%rip), %xmm0
movq %rax, %r14
xorl %eax, %eax
.L14:
movl %eax, %edx
movss %xmm0, 0(%r13,%rax,4)
andl $8191, %edx
movl %edx, 0(%rbp,%rax,8)
movl %eax, %edx
sarl $13, %edx
movl %edx, 4(%rbp,%rax,8)
incq %rax
cmpq $67108864, %rax
jne .L14
xorl %ecx, %ecx
movl $3, %esi
.L15:
movl %ecx, %eax
movss %xmm0, (%r12,%rcx,4)
cltd
idivl %esi
movl %edx, (%rbx,%rcx,8)
movl %eax, 4(%rbx,%rcx,8)
incq %rcx
cmpq $9, %rcx
jne .L15
leaq 8(%rsp), %rdi
movl $268435456, %esi
call cudaMalloc@PLT
leaq .LC4(%rip), %rsi
movl %eax, %edi
call _Z14checkCudaError9cudaErrorPKc
leaq 16(%rsp), %rdi
movl $536870912, %esi
call cudaMalloc@PLT
leaq .LC5(%rip), %rsi
movl %eax, %edi
call _Z14checkCudaError9cudaErrorPKc
leaq 24(%rsp), %rdi
movl $36, %esi
call cudaMalloc@PLT
leaq .LC6(%rip), %rsi
movl %eax, %edi
call _Z14checkCudaError9cudaErrorPKc
leaq 32(%rsp), %rdi
movl $72, %esi
call cudaMalloc@PLT
leaq .LC7(%rip), %rsi
movl %eax, %edi
call _Z14checkCudaError9cudaErrorPKc
leaq 40(%rsp), %rdi
movl $268435456, %esi
call cudaMalloc@PLT
leaq .LC8(%rip), %rsi
movl %eax, %edi
call _Z14checkCudaError9cudaErrorPKc
movq 8(%rsp), %rdi
movl $1, %ecx
movq %r13, %rsi
movl $268435456, %edx
call cudaMemcpy@PLT
leaq .LC9(%rip), %rsi
movl %eax, %edi
call _Z14checkCudaError9cudaErrorPKc
movq 16(%rsp), %rdi
movl $1, %ecx
movq %rbp, %rsi
movl $536870912, %edx
call cudaMemcpy@PLT
leaq .LC10(%rip), %rsi
movl %eax, %edi
call _Z14checkCudaError9cudaErrorPKc
movq 24(%rsp), %rdi
movl $1, %ecx
movq %r12, %rsi
movl $36, %edx
call cudaMemcpy@PLT
leaq .LC11(%rip), %rsi
movl %eax, %edi
call _Z14checkCudaError9cudaErrorPKc
movq 32(%rsp), %rdi
movl $1, %ecx
movq %rbx, %rsi
movl $72, %edx
call cudaMemcpy@PLT
leaq .LC12(%rip), %rsi
movl %eax, %edi
call _Z14checkCudaError9cudaErrorPKc
xorl %r9d, %r9d
xorl %r8d, %r8d
movl $1, %ecx
movabsq $137438953504, %rdx
movl $1, %esi
movabsq $1099511628032, %rdi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L16
pushq %rax
.cfi_def_cfa_offset 136
movl $8192, %r9d
pushq $3
.cfi_def_cfa_offset 144
pushq $3
.cfi_def_cfa_offset 152
pushq $8192
.cfi_def_cfa_offset 160
movq 72(%rsp), %r8
movq 64(%rsp), %rcx
movq 56(%rsp), %rdx
movq 48(%rsp), %rsi
movq 40(%rsp), %rdi
call _Z59__device_stub__Z23sparseConvolutionKernelPKfPKiS0_S2_PfiiiiPKfPKiS0_S2_Pfiiii
addq $32, %rsp
.cfi_def_cfa_offset 128
.L16:
call cudaGetLastError@PLT
leaq .LC13(%rip), %rsi
movl %eax, %edi
call _Z14checkCudaError9cudaErrorPKc
movq 40(%rsp), %rsi
movl $2, %ecx
movq %r14, %rdi
movl $268435456, %edx
call cudaMemcpy@PLT
leaq .LC14(%rip), %rsi
movl %eax, %edi
call _Z14checkCudaError9cudaErrorPKc
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
movq %r13, %rdi
call _ZdaPv@PLT
movq %rbp, %rdi
call _ZdaPv@PLT
movq %r12, %rdi
call _ZdaPv@PLT
movq %rbx, %rdi
call _ZdaPv@PLT
movq %r14, %rdi
call _ZdaPv@PLT
leaq _ZSt4cout(%rip), %rdi
leaq .LC15(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq 72(%rsp), %rax
subq %fs:40, %rax
je .L17
call __stack_chk_fail@PLT
.L17:
addq $80, %rsp
.cfi_def_cfa_offset 48
xorl %eax, %eax
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE6833:
.size main, .-main
.section .rodata.str1.1
.LC16:
.string "_Z23sparseConvolutionKernelPKfPKiS0_S2_Pfiiii"
.LC17:
.string "_ZN50_INTERNAL_3073b423_19_cuda_code_018401_cu_b6c02bb44cuda3std3__419piecewise_constructE"
.LC18:
.string "_ZN50_INTERNAL_3073b423_19_cuda_code_018401_cu_b6c02bb44cuda3std6ranges3__45__cpo4swapE"
.LC19:
.string "_ZN50_INTERNAL_3073b423_19_cuda_code_018401_cu_b6c02bb44cuda3std6ranges3__45__cpo9iter_moveE"
.section .text.startup
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB6861:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
pushq $0
.cfi_def_cfa_offset 24
xorl %r9d, %r9d
orl $-1, %r8d
pushq $0
.cfi_def_cfa_offset 32
leaq .LC16(%rip), %rdx
movq %rax, %rdi
movq %rax, %rbx
pushq $0
.cfi_def_cfa_offset 40
movq %rdx, %rcx
leaq _Z23sparseConvolutionKernelPKfPKiS0_S2_Pfiiii(%rip), %rsi
pushq $0
.cfi_def_cfa_offset 48
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq %rbx, %rdi
xorl %r8d, %r8d
pushq $0
.cfi_def_cfa_offset 24
leaq .LC17(%rip), %rdx
movl $1, %r9d
leaq _ZN4cuda3std3__419piecewise_constructE(%rip), %rsi
pushq $0
.cfi_def_cfa_offset 32
movq %rdx, %rcx
call __cudaRegisterVar@PLT
popq %rax
.cfi_def_cfa_offset 24
popq %rdx
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
leaq .LC18(%rip), %rdx
movq %rbx, %rdi
xorl %r8d, %r8d
movq %rdx, %rcx
movl $1, %r9d
leaq _ZN4cuda3std6ranges3__45__cpo4swapE(%rip), %rsi
call __cudaRegisterVar@PLT
popq %rcx
.cfi_def_cfa_offset 24
popq %rsi
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
leaq .LC19(%rip), %rdx
movq %rbx, %rdi
xorl %r8d, %r8d
movl $1, %r9d
movq %rdx, %rcx
leaq _ZN4cuda3std6ranges3__45__cpo9iter_moveE(%rip), %rsi
call __cudaRegisterVar@PLT
popq %rdi
.cfi_def_cfa_offset 24
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
popq %r8
.cfi_def_cfa_offset 16
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit@PLT
.cfi_endproc
.LFE6861:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.weak _ZN4cuda3std3__419piecewise_constructE
.section .rodata._ZN4cuda3std3__419piecewise_constructE,"aG",@progbits,_ZN4cuda3std3__419piecewise_constructE,comdat
.type _ZN4cuda3std3__419piecewise_constructE, @gnu_unique_object
.size _ZN4cuda3std3__419piecewise_constructE, 1
_ZN4cuda3std3__419piecewise_constructE:
.zero 1
.weak _ZN4cuda3std6ranges3__45__cpo9iter_moveE
.section .rodata._ZN4cuda3std6ranges3__45__cpo9iter_moveE,"aG",@progbits,_ZN4cuda3std6ranges3__45__cpo9iter_moveE,comdat
.type _ZN4cuda3std6ranges3__45__cpo9iter_moveE, @gnu_unique_object
.size _ZN4cuda3std6ranges3__45__cpo9iter_moveE, 1
_ZN4cuda3std6ranges3__45__cpo9iter_moveE:
.zero 1
.weak _ZN4cuda3std6ranges3__45__cpo4swapE
.section .rodata._ZN4cuda3std6ranges3__45__cpo4swapE,"aG",@progbits,_ZN4cuda3std6ranges3__45__cpo4swapE,comdat
.type _ZN4cuda3std6ranges3__45__cpo4swapE, @gnu_unique_object
.size _ZN4cuda3std6ranges3__45__cpo4swapE, 1
_ZN4cuda3std6ranges3__45__cpo4swapE:
.zero 1
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC3:
.long 1065353216
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
```
|
```amdasm
.text
.file "cuda_code_018401.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z38__device_stub__sparseConvolutionKernelPKfPKiS0_S2_Pfiiii # -- Begin function _Z38__device_stub__sparseConvolutionKernelPKfPKiS0_S2_Pfiiii
.type _Z38__device_stub__sparseConvolutionKernelPKfPKiS0_S2_Pfiiii,@function
_Z38__device_stub__sparseConvolutionKernelPKfPKiS0_S2_Pfiiii: # @_Z38__device_stub__sparseConvolutionKernelPKfPKiS0_S2_Pfiiii
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $176, %rsp
.cfi_def_cfa_offset 224
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 56(%rsp), %rax
movq %rdi, (%rax)
leaq 48(%rsp), %rdi
movq %rsi, (%rdi)
leaq 40(%rsp), %rsi
movq %rdx, (%rsi)
leaq 32(%rsp), %rdx
movq %rcx, (%rdx)
leaq 24(%rsp), %rcx
movq %r8, (%rcx)
leaq 4(%rsp), %r8
movl %r9d, (%r8)
leaq 96(%rsp), %rbx
movq %rax, (%rbx)
movq %rdi, 8(%rbx)
movq %rsi, 16(%rbx)
movq %rdx, 24(%rbx)
movq %rcx, 32(%rbx)
movq %r8, 40(%rbx)
leaq 224(%rsp), %rax
movq %rax, 48(%rbx)
leaq 232(%rsp), %rax
movq %rax, 56(%rbx)
leaq 240(%rsp), %rax
movq %rax, 64(%rbx)
leaq 80(%rsp), %r14
leaq 64(%rsp), %r15
leaq 16(%rsp), %r12
leaq 8(%rsp), %r13
movq %r14, %rdi
movq %r15, %rsi
movq %r12, %rdx
movq %r13, %rcx
callq __hipPopCallConfiguration
movq (%r14), %rsi
movl 8(%r14), %edx
movq (%r15), %rcx
movl 8(%r15), %r8d
movl $_Z23sparseConvolutionKernelPKfPKiS0_S2_Pfiiii, %edi
movq %rbx, %r9
pushq (%r13)
.cfi_adjust_cfa_offset 8
pushq (%r12)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $192, %rsp
.cfi_adjust_cfa_offset -192
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z38__device_stub__sparseConvolutionKernelPKfPKiS0_S2_Pfiiii, .Lfunc_end0-_Z38__device_stub__sparseConvolutionKernelPKfPKiS0_S2_Pfiiii
.cfi_endproc
# -- End function
.globl _Z14checkCudaError10hipError_tPKc # -- Begin function _Z14checkCudaError10hipError_tPKc
.type _Z14checkCudaError10hipError_tPKc,@function
_Z14checkCudaError10hipError_tPKc: # @_Z14checkCudaError10hipError_tPKc
.cfi_startproc
# %bb.0:
testl %edi, %edi
jne .LBB1_2
# %bb.1:
retq
.LBB1_2:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
pushq %rax
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movq %rsi, %r14
movl %edi, %ebx
movl $_ZSt4cerr, %edi
movl $.L.str, %esi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movq %rax, %rdi
movq %r14, %rsi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movl $.L.str.1, %esi
movq %rax, %rdi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movq %rax, %r14
movl %ebx, %edi
callq hipGetErrorString
movq %r14, %rdi
movq %rax, %rsi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movl $.L.str.2, %esi
movq %rax, %rdi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movq %rax, %rdi
callq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_
movl $1, %edi
callq exit
.Lfunc_end1:
.size _Z14checkCudaError10hipError_tPKc, .Lfunc_end1-_Z14checkCudaError10hipError_tPKc
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $56, %rsp
.cfi_def_cfa_offset 112
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $268435456, %edi # imm = 0x10000000
callq _Znam
movq %rax, %rbx
movl $536870912, %edi # imm = 0x20000000
callq _Znam
movq %rax, %r14
movl $36, %edi
callq _Znam
movq %rax, %r15
movl $72, %edi
callq _Znam
movq %rax, %r12
movl $268435456, %edi # imm = 0x10000000
callq _Znam
movq %rax, 48(%rsp) # 8-byte Spill
xorl %eax, %eax
.LBB2_1: # =>This Inner Loop Header: Depth=1
movl $1065353216, (%rbx,%rax,4) # imm = 0x3F800000
movl %eax, %ecx
andl $8191, %ecx # imm = 0x1FFF
movl %ecx, (%r14,%rax,8)
movl %eax, %ecx
shrl $13, %ecx
movl %ecx, 4(%r14,%rax,8)
incq %rax
cmpq $67108864, %rax # imm = 0x4000000
jne .LBB2_1
# %bb.2: # %.preheader.preheader
xorl %eax, %eax
movl $2863311531, %ecx # imm = 0xAAAAAAAB
.LBB2_3: # %.preheader
# =>This Inner Loop Header: Depth=1
movl %eax, %edx
imulq %rcx, %rdx
shrq $33, %rdx
leal (%rdx,%rdx,2), %edx
movl %eax, %esi
subl %edx, %esi
movl $1065353216, (%r15,%rax,4) # imm = 0x3F800000
movl %esi, (%r12,%rax,8)
movzbl %al, %edx
imull $171, %edx, %edx
shrl $9, %edx
movl %edx, 4(%r12,%rax,8)
incq %rax
cmpq $9, %rax
jne .LBB2_3
# %bb.4:
leaq 40(%rsp), %r13
movl $268435456, %esi # imm = 0x10000000
movq %r13, %rdi
callq hipMalloc
movl $.L.str.3, %esi
movl %eax, %edi
callq _Z14checkCudaError10hipError_tPKc
leaq 32(%rsp), %rbp
movl $536870912, %esi # imm = 0x20000000
movq %rbp, %rdi
callq hipMalloc
movl $.L.str.4, %esi
movl %eax, %edi
callq _Z14checkCudaError10hipError_tPKc
leaq 24(%rsp), %rdi
movl $36, %esi
callq hipMalloc
movl $.L.str.5, %esi
movl %eax, %edi
callq _Z14checkCudaError10hipError_tPKc
leaq 16(%rsp), %rdi
movl $72, %esi
callq hipMalloc
movl $.L.str.6, %esi
movl %eax, %edi
callq _Z14checkCudaError10hipError_tPKc
leaq 8(%rsp), %rdi
movl $268435456, %esi # imm = 0x10000000
callq hipMalloc
movl $.L.str.7, %esi
movl %eax, %edi
callq _Z14checkCudaError10hipError_tPKc
movq (%r13), %rdi
movl $268435456, %edx # imm = 0x10000000
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movl $.L.str.8, %esi
movl %eax, %edi
callq _Z14checkCudaError10hipError_tPKc
movq (%rbp), %rdi
movl $536870912, %edx # imm = 0x20000000
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movl $.L.str.9, %esi
movl %eax, %edi
callq _Z14checkCudaError10hipError_tPKc
leaq 24(%rsp), %rax
movq (%rax), %rdi
movl $36, %edx
movq %r15, %rsi
movl $1, %ecx
callq hipMemcpy
movl $.L.str.10, %esi
movl %eax, %edi
callq _Z14checkCudaError10hipError_tPKc
leaq 16(%rsp), %rax
movq (%rax), %rdi
movl $72, %edx
movq %r12, %rsi
movl $1, %ecx
callq hipMemcpy
movl $.L.str.11, %esi
movl %eax, %edi
callq _Z14checkCudaError10hipError_tPKc
movabsq $1099511628032, %rdi # imm = 0x10000000100
movabsq $137438953504, %rdx # imm = 0x2000000020
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_6
# %bb.5:
movq 40(%rsp), %rdi
movq 32(%rsp), %rsi
movq 24(%rsp), %rdx
movq 16(%rsp), %rcx
movq 8(%rsp), %r8
subq $8, %rsp
.cfi_adjust_cfa_offset 8
movl $3, %eax
movl $8192, %r9d # imm = 0x2000
pushq %rax
.cfi_adjust_cfa_offset 8
pushq %rax
.cfi_adjust_cfa_offset 8
pushq $8192 # imm = 0x2000
.cfi_adjust_cfa_offset 8
callq _Z38__device_stub__sparseConvolutionKernelPKfPKiS0_S2_Pfiiii
addq $32, %rsp
.cfi_adjust_cfa_offset -32
.LBB2_6:
callq hipGetLastError
movl $.L.str.12, %esi
movl %eax, %edi
callq _Z14checkCudaError10hipError_tPKc
movq 8(%rsp), %rsi
movl $268435456, %edx # imm = 0x10000000
movq 48(%rsp), %r13 # 8-byte Reload
movq %r13, %rdi
movl $2, %ecx
callq hipMemcpy
movl $.L.str.13, %esi
movl %eax, %edi
callq _Z14checkCudaError10hipError_tPKc
movq 40(%rsp), %rdi
callq hipFree
movq 32(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq %rbx, %rdi
callq _ZdaPv
movq %r14, %rdi
callq _ZdaPv
movq %r15, %rdi
callq _ZdaPv
movq %r12, %rdi
callq _ZdaPv
movq %r13, %rdi
callq _ZdaPv
movl $_ZSt4cout, %ebx
movl $_ZSt4cout, %edi
movl $.L.str.14, %esi
movl $42, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rdi
addq %rbx, %rdi
movl $10, %esi
callq _ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
xorl %eax, %eax
addq $56, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, %rdi
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z23sparseConvolutionKernelPKfPKiS0_S2_Pfiiii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z23sparseConvolutionKernelPKfPKiS0_S2_Pfiiii,@object # @_Z23sparseConvolutionKernelPKfPKiS0_S2_Pfiiii
.section .rodata,"a",@progbits
.globl _Z23sparseConvolutionKernelPKfPKiS0_S2_Pfiiii
.p2align 3, 0x0
_Z23sparseConvolutionKernelPKfPKiS0_S2_Pfiiii:
.quad _Z38__device_stub__sparseConvolutionKernelPKfPKiS0_S2_Pfiiii
.size _Z23sparseConvolutionKernelPKfPKiS0_S2_Pfiiii, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "CUDA error: "
.size .L.str, 13
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz " ("
.size .L.str.1, 3
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz ")"
.size .L.str.2, 2
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "hipMalloc d_input"
.size .L.str.3, 18
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "hipMalloc d_inputIndices"
.size .L.str.4, 25
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "hipMalloc d_filter"
.size .L.str.5, 19
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "hipMalloc d_filterIndices"
.size .L.str.6, 26
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "hipMalloc d_output"
.size .L.str.7, 19
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "hipMemcpy d_input"
.size .L.str.8, 18
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "hipMemcpy d_inputIndices"
.size .L.str.9, 25
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "hipMemcpy d_filter"
.size .L.str.10, 19
.type .L.str.11,@object # @.str.11
.L.str.11:
.asciz "hipMemcpy d_filterIndices"
.size .L.str.11, 26
.type .L.str.12,@object # @.str.12
.L.str.12:
.asciz "Kernel launch failed"
.size .L.str.12, 21
.type .L.str.13,@object # @.str.13
.L.str.13:
.asciz "hipMemcpy h_output"
.size .L.str.13, 19
.type .L.str.14,@object # @.str.14
.L.str.14:
.asciz "Sparse convolution completed successfully."
.size .L.str.14, 43
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z23sparseConvolutionKernelPKfPKiS0_S2_Pfiiii"
.size .L__unnamed_1, 46
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z38__device_stub__sparseConvolutionKernelPKfPKiS0_S2_Pfiiii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z23sparseConvolutionKernelPKfPKiS0_S2_Pfiiii
.addrsig_sym _ZSt4cerr
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
```
| 6,580 | 6,663 |
113,672 |
Convert the following CUDA device assembly code to AMD device assembly:
```cudaasm
code for sm_80
Function : _Z19graphColoringKernelv
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ;
S2R R4, SR_CTAID.X ;
S2R R3, SR_TID.X ;
IMAD R4, R4, c[0x0][0x0], R3 ;
ISETP.GT.AND P0, PT, R4, 0x7ff, PT ;
@P0 EXIT ;
IMAD.MOV.U32 R5, RZ, RZ, 0x4 ;
ULDC.64 UR4, c[0x0][0x118] ;
HFMA2.MMA R11, -RZ, RZ, 0, 0 ;
IMAD.WIDE R2, R4, R5, c[0x4][0x10] ;
IMAD.WIDE R4, R4, R5, c[0x4][0x8] ;
STG.E [R2.64], RZ ;
BAR.SYNC 0x0 ;
LDG.E R0, [R4.64+0x4] ;
LDG.E R7, [R4.64] ;
ISETP.GE.AND P0, PT, R7, R0, PT ;
@P0 BRA 0x1d0 ;
BSSY B0, 0x200 ;
IMAD.MOV.U32 R13, RZ, RZ, R7 ;
MOV R8, 0x4 ;
IMAD.WIDE R6, R13, R8, c[0x4][0x0] ;
LDG.E R6, [R6.64] ;
IMAD.WIDE R8, R6, R8, c[0x4][0x10] ;
LDG.E R8, [R8.64] ;
ISETP.NE.AND P0, PT, R8, R11, PT ;
@!P0 BRA 0x1f0 ;
IADD3 R13, R13, 0x1, RZ ;
ISETP.GE.AND P0, PT, R13, R0, PT ;
@!P0 BRA 0x130 ;
STG.E [R2.64], R11 ;
EXIT ;
BSYNC B0 ;
BRA.CONV ~URZ, 0x240 ;
MOV R6, 0x230 ;
CALL.REL.NOINC 0x290 ;
BRA 0x250 ;
BAR.SYNC 0x0 ;
IADD3 R11, R11, 0x1, RZ ;
ISETP.GE.U32.AND P0, PT, R11, 0x800, PT ;
@!P0 BRA 0xd0 ;
EXIT ;
IMAD.MOV.U32 R7, RZ, RZ, 0x0 ;
WARPSYNC 0xffffffff ;
BAR.SYNC 0x0 ;
RET.REL.NODEC R6 0x0 ;
BRA 0x2d0;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
```
|
```amdasm
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z19graphColoringKernelv ; -- Begin function _Z19graphColoringKernelv
.globl _Z19graphColoringKernelv
.p2align 8
.type _Z19graphColoringKernelv,@function
_Z19graphColoringKernelv: ; @_Z19graphColoringKernelv
; %bb.0:
s_load_b32 s0, s[0:1], 0xc
s_waitcnt lgkmcnt(0)
s_and_b32 s0, s0, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s0, v[0:1]
s_mov_b32 s0, exec_lo
v_cmpx_gt_i32_e32 0x800, v1
s_cbranch_execz .LBB0_13
; %bb.1:
v_ashrrev_i32_e32 v2, 31, v1
s_getpc_b64 s[2:3]
s_add_u32 s2, s2, colors@rel32@lo+4
s_addc_u32 s3, s3, colors@rel32@hi+12
s_getpc_b64 s[4:5]
s_add_u32 s4, s4, adjListPtr@rel32@lo+4
s_addc_u32 s5, s5, adjListPtr@rel32@hi+12
v_mov_b32_e32 v4, 0
s_mov_b32 s1, 0
v_lshlrev_b64 v[2:3], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v2, s2
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v3, vcc_lo
v_add_co_u32 v2, vcc_lo, v2, s4
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
s_mov_b32 s2, 0
global_store_b32 v[0:1], v4, off
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
.LBB0_2: ; =>This Loop Header: Depth=1
; Child Loop BB0_4 Depth 2
global_load_b64 v[4:5], v[2:3], off
s_mov_b32 s4, -1
s_mov_b32 s0, 0
s_mov_b32 s3, exec_lo
s_waitcnt vmcnt(0)
v_cmpx_lt_i32_e64 v4, v5
s_cbranch_execz .LBB0_8
; %bb.3: ; %.lr.ph.preheader
; in Loop: Header=BB0_2 Depth=1
v_ashrrev_i32_e32 v7, 31, v4
v_mov_b32_e32 v6, v4
s_getpc_b64 s[4:5]
s_add_u32 s4, s4, adjList@rel32@lo+4
s_addc_u32 s5, s5, adjList@rel32@hi+12
; implicit-def: $sgpr7
; implicit-def: $sgpr6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[6:7], 2, v[6:7]
v_add_co_u32 v6, vcc_lo, v6, s4
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v7, vcc_lo, s5, v7, vcc_lo
s_mov_b32 s4, 0
; implicit-def: $sgpr5
.LBB0_4: ; %.lr.ph
; Parent Loop BB0_2 Depth=1
; => This Inner Loop Header: Depth=2
global_load_b32 v8, v[6:7], off
s_getpc_b64 s[8:9]
s_add_u32 s8, s8, colors@rel32@lo+4
s_addc_u32 s9, s9, colors@rel32@hi+12
s_or_b32 s6, s6, exec_lo
s_or_b32 s7, s7, exec_lo
s_waitcnt vmcnt(0)
v_ashrrev_i32_e32 v9, 31, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[8:9], 2, v[8:9]
v_add_co_u32 v8, vcc_lo, v8, s8
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v9, vcc_lo, s9, v9, vcc_lo
s_mov_b32 s8, exec_lo
global_load_b32 v8, v[8:9], off
s_waitcnt vmcnt(0)
v_cmpx_ne_u32_e64 s2, v8
; %bb.5: ; in Loop: Header=BB0_4 Depth=2
v_add_nc_u32_e32 v4, 1, v4
v_add_co_u32 v6, s0, v6, 4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e64 v7, s0, 0, v7, s0
v_cmp_ge_i32_e32 vcc_lo, v4, v5
s_and_not1_b32 s0, s7, exec_lo
s_and_not1_b32 s6, s6, exec_lo
s_and_b32 s7, vcc_lo, exec_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 s7, s0, s7
; %bb.6: ; %Flow
; in Loop: Header=BB0_4 Depth=2
s_or_b32 exec_lo, exec_lo, s8
s_xor_b32 s0, s6, -1
s_and_b32 s8, exec_lo, s7
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
s_or_b32 s4, s8, s4
s_and_not1_b32 s5, s5, exec_lo
s_and_b32 s0, s0, exec_lo
s_or_b32 s5, s5, s0
s_and_not1_b32 exec_lo, exec_lo, s4
s_cbranch_execnz .LBB0_4
; %bb.7: ; %loop.exit.guard
; in Loop: Header=BB0_2 Depth=1
s_or_b32 exec_lo, exec_lo, s4
s_delay_alu instid0(SALU_CYCLE_1)
s_mov_b32 s0, exec_lo
s_or_not1_b32 s4, s5, exec_lo
.LBB0_8: ; %Flow66
; in Loop: Header=BB0_2 Depth=1
s_or_b32 exec_lo, exec_lo, s3
; implicit-def: $sgpr3
s_and_saveexec_b32 s5, s4
s_cbranch_execz .LBB0_10
; %bb.9: ; %.critedge.loopexit
; in Loop: Header=BB0_2 Depth=1
v_mov_b32_e32 v4, s2
s_mov_b32 s3, -1
s_and_not1_b32 s0, s0, exec_lo
global_store_b32 v[0:1], v4, off
.LBB0_10: ; %Flow67
; in Loop: Header=BB0_2 Depth=1
s_or_b32 exec_lo, exec_lo, s5
s_and_saveexec_b32 s4, s0
s_cbranch_execz .LBB0_12
; %bb.11: ; in Loop: Header=BB0_2 Depth=1
s_waitcnt_vscnt null, 0x0
s_barrier
s_and_not1_b32 s3, s3, exec_lo
buffer_gl0_inv
.LBB0_12: ; in Loop: Header=BB0_2 Depth=1
s_or_b32 exec_lo, exec_lo, s4
s_add_i32 s2, s2, 1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_cmpk_eq_i32 s2, 0x800
s_cselect_b32 s0, -1, 0
s_or_b32 s0, s3, s0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s0, exec_lo, s0
s_or_b32 s1, s0, s1
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s1
s_cbranch_execnz .LBB0_2
.LBB0_13: ; %.loopexit
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z19graphColoringKernelv
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 256
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 10
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z19graphColoringKernelv, .Lfunc_end0-_Z19graphColoringKernelv
; -- End function
.section .AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 584
; NumSgprs: 18
; NumVgprs: 10
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 10
; Occupancy: 16
; WaveLimiterHint : 1
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.protected adjList ; @adjList
.type adjList,@object
.section .bss,"aw",@nobits
.globl adjList
.p2align 4, 0x0
adjList:
.zero 16384
.size adjList, 16384
.protected adjListPtr ; @adjListPtr
.type adjListPtr,@object
.globl adjListPtr
.p2align 4, 0x0
adjListPtr:
.zero 8196
.size adjListPtr, 8196
.protected colors ; @colors
.type colors,@object
.globl colors
.p2align 4, 0x0
colors:
.zero 8192
.size colors, 8192
.type __hip_cuid_,@object ; @__hip_cuid_
.globl __hip_cuid_
__hip_cuid_:
.byte 0 ; 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym adjList
.addrsig_sym adjListPtr
.addrsig_sym colors
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: hidden_block_count_x
- .offset: 4
.size: 4
.value_kind: hidden_block_count_y
- .offset: 8
.size: 4
.value_kind: hidden_block_count_z
- .offset: 12
.size: 2
.value_kind: hidden_group_size_x
- .offset: 14
.size: 2
.value_kind: hidden_group_size_y
- .offset: 16
.size: 2
.value_kind: hidden_group_size_z
- .offset: 18
.size: 2
.value_kind: hidden_remainder_x
- .offset: 20
.size: 2
.value_kind: hidden_remainder_y
- .offset: 22
.size: 2
.value_kind: hidden_remainder_z
- .offset: 40
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 48
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 64
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 256
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z19graphColoringKernelv
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z19graphColoringKernelv.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 10
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
```
| 779 | 4,374 |
113,673 |
Convert the following CUDA host assembly code to AMD host assembly:
```cudaasm
.file "tmpxft_00094a6b_00000000-6_cuda_code_039834.cudafe1.cpp"
.text
.globl _ZSt21ios_base_library_initv
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB6836:
.cfi_startproc
endbr64
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
jmp __cudaUnregisterFatBinary@PLT
.cfi_endproc
.LFE6836:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "CUDA error: "
.LC1:
.string " ("
.LC2:
.string ")"
.text
.globl _Z14checkCudaError9cudaErrorPKc
.type _Z14checkCudaError9cudaErrorPKc, @function
_Z14checkCudaError9cudaErrorPKc:
.LFB6832:
.cfi_startproc
endbr64
testl %edi, %edi
je .L2
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
movq %rsi, %rbp
leaq .LC0(%rip), %rsi
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
movl %edi, %ebx
leaq _ZSt4cerr(%rip), %rdi
pushq %rax
.cfi_def_cfa_offset 32
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rbp, %rsi
movq %rax, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
leaq .LC1(%rip), %rsi
movq %rax, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movl %ebx, %edi
movq %rax, %rbp
call cudaGetErrorString@PLT
movq %rbp, %rdi
movq %rax, %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
leaq .LC2(%rip), %rsi
movq %rax, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $1, %edi
call exit@PLT
.L2:
.cfi_def_cfa_offset 8
.cfi_restore 3
.cfi_restore 6
ret
.cfi_endproc
.LFE6832:
.size _Z14checkCudaError9cudaErrorPKc, .-_Z14checkCudaError9cudaErrorPKc
.globl _Z38__device_stub__Z19graphColoringKernelvv
.type _Z38__device_stub__Z19graphColoringKernelvv, @function
_Z38__device_stub__Z19graphColoringKernelvv:
.LFB6858:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
movabsq $4294967297, %rax
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
movl $1, 24(%rsp)
movl $1, 36(%rsp)
movq %rax, 16(%rsp)
movq %rax, 28(%rsp)
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
jne .L8
pushq 8(%rsp)
.cfi_def_cfa_offset 104
leaq _Z19graphColoringKernelv(%rip), %rdi
pushq 8(%rsp)
.cfi_def_cfa_offset 112
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq 80(%rsp), %r9
call cudaLaunchKernel@PLT
popq %rax
.cfi_def_cfa_offset 104
popq %rdx
.cfi_def_cfa_offset 96
.L8:
movq 72(%rsp), %rax
subq %fs:40, %rax
je .L10
call __stack_chk_fail@PLT
.L10:
addq $88, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE6858:
.size _Z38__device_stub__Z19graphColoringKernelvv, .-_Z38__device_stub__Z19graphColoringKernelvv
.globl _Z19graphColoringKernelv
.type _Z19graphColoringKernelv, @function
_Z19graphColoringKernelv:
.LFB6859:
.cfi_startproc
endbr64
jmp _Z38__device_stub__Z19graphColoringKernelvv
.cfi_endproc
.LFE6859:
.size _Z19graphColoringKernelv, .-_Z19graphColoringKernelv
.section .rodata.str1.1
.LC3:
.string "cudaMalloc d_adjList"
.LC4:
.string "cudaMalloc d_adjListPtr"
.LC5:
.string "cudaMalloc d_colors"
.LC6:
.string "cudaMemcpy d_adjList"
.LC7:
.string "cudaMemcpy d_adjListPtr"
.LC8:
.string "graphColoringKernel launch"
.LC9:
.string "cudaMemcpy d_colors"
.LC10:
.string "Node colors:"
.LC11:
.string "Node "
.LC12:
.string ": Color "
.section .text.startup,"ax",@progbits
.globl main
.type main, @function
main:
.LFB6833:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
leaq -32768(%rsp), %r11
.cfi_def_cfa 11, 32808
.LPSRL0:
subq $4096, %rsp
orq $0, (%rsp)
cmpq %r11, %rsp
jne .LPSRL0
.cfi_def_cfa_register 7
subq $72, %rsp
.cfi_def_cfa_offset 32880
xorl %edx, %edx
movq %fs:40, %rax
movq %rax, 32824(%rsp)
xorl %eax, %eax
leaq 8244(%rsp), %rbx
.L16:
movl %edx, (%rbx,%rax,4)
movl %eax, %edi
movl %eax, %r8d
leal 1(%rax), %ecx
movslq %edx, %rsi
.L14:
cmpl $2048, %ecx
je .L23
movl %ecx, 16440(%rsp,%rsi,4)
incl %ecx
movl %r8d, 16444(%rsp,%rsi,4)
addq $2, %rsi
jmp .L14
.L23:
imull $-2, %edi, %ecx
incq %rax
leal 4094(%rdx,%rcx), %edx
cmpq $2048, %rax
jne .L16
movq %rsp, %rdi
movl $16384, %esi
movl $4192256, 16436(%rsp)
call cudaMalloc@PLT
leaq .LC3(%rip), %rsi
movl %eax, %edi
call _Z14checkCudaError9cudaErrorPKc
leaq 8(%rsp), %rdi
movl $8196, %esi
call cudaMalloc@PLT
leaq .LC4(%rip), %rsi
movl %eax, %edi
call _Z14checkCudaError9cudaErrorPKc
leaq 16(%rsp), %rdi
movl $8192, %esi
call cudaMalloc@PLT
leaq .LC5(%rip), %rsi
movl %eax, %edi
call _Z14checkCudaError9cudaErrorPKc
movq (%rsp), %rdi
movl $1, %ecx
movl $16384, %edx
leaq 16440(%rsp), %rsi
call cudaMemcpy@PLT
leaq .LC6(%rip), %rsi
movl %eax, %edi
call _Z14checkCudaError9cudaErrorPKc
movq 8(%rsp), %rdi
movl $1, %ecx
movq %rbx, %rsi
movl $8196, %edx
call cudaMemcpy@PLT
leaq .LC7(%rip), %rsi
movl %eax, %edi
call _Z14checkCudaError9cudaErrorPKc
movl $16777217, %edx
xorl %r9d, %r9d
xorl %r8d, %r8d
movl $536870913, %edi
salq $8, %rdx
movl $1, %ecx
movl $1, %esi
salq $3, %rdi
movq %rdx, 40(%rsp)
movl $1, 48(%rsp)
movq %rdi, 28(%rsp)
movl $1, 36(%rsp)
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L17
call _Z38__device_stub__Z19graphColoringKernelvv
.L17:
call cudaGetLastError@PLT
leaq .LC8(%rip), %rsi
leaq 52(%rsp), %rbp
xorl %ebx, %ebx
movl %eax, %edi
leaq _ZSt4cout(%rip), %r12
leaq .LC11(%rip), %r13
call _Z14checkCudaError9cudaErrorPKc
movq 16(%rsp), %rsi
movl $2, %ecx
movq %rbp, %rdi
movl $8192, %edx
call cudaMemcpy@PLT
leaq .LC9(%rip), %rsi
movl %eax, %edi
call _Z14checkCudaError9cudaErrorPKc
leaq .LC10(%rip), %rsi
movq %r12, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
.L18:
movq %r13, %rsi
movq %r12, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movl %ebx, %esi
movq %rax, %rdi
call _ZNSolsEi@PLT
leaq .LC12(%rip), %rsi
movq %rax, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movl 0(%rbp,%rbx,4), %esi
incq %rbx
movq %rax, %rdi
call _ZNSolsEi@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
cmpq $2048, %rbx
jne .L18
movq (%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 32824(%rsp), %rax
subq %fs:40, %rax
je .L19
call __stack_chk_fail@PLT
.L19:
addq $32840, %rsp
.cfi_def_cfa_offset 40
xorl %eax, %eax
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE6833:
.size main, .-main
.section .rodata.str1.1
.LC13:
.string "_Z19graphColoringKernelv"
.LC14:
.string "adjList"
.LC15:
.string "adjListPtr"
.LC16:
.string "colors"
.LC17:
.string "_ZN50_INTERNAL_d39df273_19_cuda_code_039834_cu_366ae1884cuda3std3__419piecewise_constructE"
.LC18:
.string "_ZN50_INTERNAL_d39df273_19_cuda_code_039834_cu_366ae1884cuda3std6ranges3__45__cpo4swapE"
.LC19:
.string "_ZN50_INTERNAL_d39df273_19_cuda_code_039834_cu_366ae1884cuda3std6ranges3__45__cpo9iter_moveE"
.section .text.startup
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB6861:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
pushq $0
.cfi_def_cfa_offset 24
xorl %r9d, %r9d
orl $-1, %r8d
pushq $0
.cfi_def_cfa_offset 32
leaq .LC13(%rip), %rdx
movq %rax, %rdi
movq %rax, %rbx
pushq $0
.cfi_def_cfa_offset 40
movq %rdx, %rcx
leaq _Z19graphColoringKernelv(%rip), %rsi
pushq $0
.cfi_def_cfa_offset 48
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq %rbx, %rdi
xorl %r8d, %r8d
pushq $0
.cfi_def_cfa_offset 24
leaq .LC14(%rip), %rdx
movl $16384, %r9d
leaq _ZL7adjList(%rip), %rsi
pushq $0
.cfi_def_cfa_offset 32
movq %rdx, %rcx
call __cudaRegisterVar@PLT
popq %rax
.cfi_def_cfa_offset 24
popq %rdx
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
leaq .LC15(%rip), %rdx
movq %rbx, %rdi
xorl %r8d, %r8d
movq %rdx, %rcx
movl $8196, %r9d
leaq _ZL10adjListPtr(%rip), %rsi
call __cudaRegisterVar@PLT
popq %rcx
.cfi_def_cfa_offset 24
popq %rsi
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
leaq .LC16(%rip), %rdx
movq %rbx, %rdi
xorl %r8d, %r8d
movq %rdx, %rcx
movl $8192, %r9d
leaq _ZL6colors(%rip), %rsi
call __cudaRegisterVar@PLT
popq %rdi
.cfi_def_cfa_offset 24
popq %r8
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
leaq .LC17(%rip), %rdx
movq %rbx, %rdi
xorl %r8d, %r8d
movq %rdx, %rcx
movl $1, %r9d
leaq _ZN4cuda3std3__419piecewise_constructE(%rip), %rsi
call __cudaRegisterVar@PLT
popq %r9
.cfi_def_cfa_offset 24
popq %r10
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
leaq .LC18(%rip), %rdx
movq %rbx, %rdi
xorl %r8d, %r8d
movq %rdx, %rcx
movl $1, %r9d
leaq _ZN4cuda3std6ranges3__45__cpo4swapE(%rip), %rsi
call __cudaRegisterVar@PLT
popq %r11
.cfi_def_cfa_offset 24
popq %rax
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
leaq .LC19(%rip), %rdx
movq %rbx, %rdi
xorl %r8d, %r8d
movq %rdx, %rcx
movl $1, %r9d
leaq _ZN4cuda3std6ranges3__45__cpo9iter_moveE(%rip), %rsi
call __cudaRegisterVar@PLT
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
popq %rax
.cfi_def_cfa_offset 24
popq %rdx
.cfi_def_cfa_offset 16
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit@PLT
.cfi_endproc
.LFE6861:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZL6colors
.comm _ZL6colors,8192,32
.local _ZL10adjListPtr
.comm _ZL10adjListPtr,8196,32
.local _ZL7adjList
.comm _ZL7adjList,16384,32
.weak _ZN4cuda3std3__419piecewise_constructE
.section .rodata._ZN4cuda3std3__419piecewise_constructE,"aG",@progbits,_ZN4cuda3std3__419piecewise_constructE,comdat
.type _ZN4cuda3std3__419piecewise_constructE, @gnu_unique_object
.size _ZN4cuda3std3__419piecewise_constructE, 1
_ZN4cuda3std3__419piecewise_constructE:
.zero 1
.weak _ZN4cuda3std6ranges3__45__cpo9iter_moveE
.section .rodata._ZN4cuda3std6ranges3__45__cpo9iter_moveE,"aG",@progbits,_ZN4cuda3std6ranges3__45__cpo9iter_moveE,comdat
.type _ZN4cuda3std6ranges3__45__cpo9iter_moveE, @gnu_unique_object
.size _ZN4cuda3std6ranges3__45__cpo9iter_moveE, 1
_ZN4cuda3std6ranges3__45__cpo9iter_moveE:
.zero 1
.weak _ZN4cuda3std6ranges3__45__cpo4swapE
.section .rodata._ZN4cuda3std6ranges3__45__cpo4swapE,"aG",@progbits,_ZN4cuda3std6ranges3__45__cpo4swapE,comdat
.type _ZN4cuda3std6ranges3__45__cpo4swapE, @gnu_unique_object
.size _ZN4cuda3std6ranges3__45__cpo4swapE, 1
_ZN4cuda3std6ranges3__45__cpo4swapE:
.zero 1
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
```
|
```amdasm
.text
.file "cuda_code_039834.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z34__device_stub__graphColoringKernelv # -- Begin function _Z34__device_stub__graphColoringKernelv
.type _Z34__device_stub__graphColoringKernelv,@function
_Z34__device_stub__graphColoringKernelv: # @_Z34__device_stub__graphColoringKernelv
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $56, %rsp
.cfi_def_cfa_offset 96
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 40(%rsp), %rbx
leaq 24(%rsp), %r14
leaq 16(%rsp), %r15
leaq 8(%rsp), %r12
movq %rbx, %rdi
movq %r14, %rsi
movq %r15, %rdx
movq %r12, %rcx
callq __hipPopCallConfiguration
movq (%rbx), %rsi
movl 8(%rbx), %edx
movq (%r14), %rcx
movl 8(%r14), %r8d
movq %rsp, %r9
movl $_Z19graphColoringKernelv, %edi
pushq (%r12)
.cfi_adjust_cfa_offset 8
pushq (%r15)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z34__device_stub__graphColoringKernelv, .Lfunc_end0-_Z34__device_stub__graphColoringKernelv
.cfi_endproc
# -- End function
.globl _Z14checkCudaError10hipError_tPKc # -- Begin function _Z14checkCudaError10hipError_tPKc
.type _Z14checkCudaError10hipError_tPKc,@function
_Z14checkCudaError10hipError_tPKc: # @_Z14checkCudaError10hipError_tPKc
.cfi_startproc
# %bb.0:
testl %edi, %edi
jne .LBB1_2
# %bb.1:
retq
.LBB1_2:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
pushq %rax
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movq %rsi, %r14
movl %edi, %ebx
movl $_ZSt4cerr, %edi
movl $.L.str, %esi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movq %rax, %rdi
movq %r14, %rsi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movl $.L.str.1, %esi
movq %rax, %rdi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movq %rax, %r14
movl %ebx, %edi
callq hipGetErrorString
movq %r14, %rdi
movq %rax, %rsi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movl $.L.str.2, %esi
movq %rax, %rdi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movq %rax, %rdi
callq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_
movl $1, %edi
callq exit
.Lfunc_end1:
.size _Z14checkCudaError10hipError_tPKc, .Lfunc_end1-_Z14checkCudaError10hipError_tPKc
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $32816, %rsp # imm = 0x8030
.cfi_def_cfa_offset 32848
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
xorl %ecx, %ecx
leaq 16436(%rsp), %rax
xorl %edx, %edx
.LBB2_1: # =>This Loop Header: Depth=1
# Child Loop BB2_9 Depth 2
movq %rcx, %rsi
movl %edx, 8224(%rsp,%rcx,4)
incq %rcx
cmpq $2046, %rsi # imm = 0x7FE
ja .LBB2_2
# %bb.8: # %.lr.ph.preheader
# in Loop: Header=BB2_1 Depth=1
movl $4094, %r8d # imm = 0xFFE
subl %esi, %r8d
subl %esi, %r8d
movslq %edx, %rdi
leaq (%rax,%rdi,4), %rdi
addl %r8d, %edx
movl %ecx, %r8d
.LBB2_9: # %.lr.ph
# Parent Loop BB2_1 Depth=1
# => This Inner Loop Header: Depth=2
movl %r8d, -4(%rdi)
movl %esi, (%rdi)
incl %r8d
addq $8, %rdi
cmpl $2048, %r8d # imm = 0x800
jne .LBB2_9
.LBB2_2: # %.loopexit
# in Loop: Header=BB2_1 Depth=1
cmpq $2048, %rcx # imm = 0x800
jne .LBB2_1
# %bb.3:
leaq 8224(%rsp), %rbx
movl %edx, 8192(%rbx)
leaq 24(%rsp), %r15
movl $16384, %esi # imm = 0x4000
movq %r15, %rdi
callq hipMalloc
movl $.L.str.3, %esi
movl %eax, %edi
callq _Z14checkCudaError10hipError_tPKc
leaq 16(%rsp), %r14
movl $8196, %esi # imm = 0x2004
movq %r14, %rdi
callq hipMalloc
movl $.L.str.4, %esi
movl %eax, %edi
callq _Z14checkCudaError10hipError_tPKc
leaq 8(%rsp), %rdi
movl $8192, %esi # imm = 0x2000
callq hipMalloc
movl $.L.str.5, %esi
movl %eax, %edi
callq _Z14checkCudaError10hipError_tPKc
movq (%r15), %rdi
leaq 16432(%rsp), %rsi
movl $16384, %edx # imm = 0x4000
movl $1, %ecx
callq hipMemcpy
movl $.L.str.6, %esi
movl %eax, %edi
callq _Z14checkCudaError10hipError_tPKc
movq (%r14), %rdi
movl $8196, %edx # imm = 0x2004
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movl $.L.str.7, %esi
movl %eax, %edi
callq _Z14checkCudaError10hipError_tPKc
movabsq $4294967304, %rdi # imm = 0x100000008
leaq 248(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_5
# %bb.4:
callq _Z34__device_stub__graphColoringKernelv
.LBB2_5:
callq hipGetLastError
movl $.L.str.8, %esi
movl %eax, %edi
callq _Z14checkCudaError10hipError_tPKc
movq 8(%rsp), %rsi
leaq 32(%rsp), %rdi
movl $8192, %edx # imm = 0x2000
movl $2, %ecx
callq hipMemcpy
movl $.L.str.9, %esi
movl %eax, %edi
callq _Z14checkCudaError10hipError_tPKc
movl $_ZSt4cout, %ebx
movl $_ZSt4cout, %edi
movl $.L.str.10, %esi
movl $12, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rdi
addq %rbx, %rdi
movl $10, %esi
callq _ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
xorl %ebx, %ebx
.LBB2_6: # =>This Inner Loop Header: Depth=1
movl $_ZSt4cout, %edi
movl $.L.str.11, %esi
movl $5, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl %ebx, %esi
callq _ZNSolsEi
movq %rax, %r14
movl $.L.str.12, %esi
movl $8, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl 32(%rsp,%rbx,4), %esi
movq %r14, %rdi
callq _ZNSolsEi
movq %rax, %r14
movq (%rax), %rax
movq -24(%rax), %rdi
addq %r14, %rdi
movl $10, %esi
callq _ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
movsbl %al, %esi
movq %r14, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
incq %rbx
cmpq $2048, %rbx # imm = 0x800
jne .LBB2_6
# %bb.7:
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $32816, %rsp # imm = 0x8030
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
movq __hip_gpubin_handle(%rip), %rbx
testq %rbx, %rbx
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, %rbx
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
subq $32, %rsp
.cfi_adjust_cfa_offset 32
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z19graphColoringKernelv, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
addq $32, %rsp
.cfi_adjust_cfa_offset -32
movl $adjList, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movl $16384, %r9d # imm = 0x4000
movq %rbx, %rdi
xorl %r8d, %r8d
pushq $0
.cfi_adjust_cfa_offset 8
pushq $0
.cfi_adjust_cfa_offset 8
callq __hipRegisterVar
addq $16, %rsp
.cfi_adjust_cfa_offset -16
movl $adjListPtr, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movl $8196, %r9d # imm = 0x2004
movq %rbx, %rdi
xorl %r8d, %r8d
pushq $0
.cfi_adjust_cfa_offset 8
pushq $0
.cfi_adjust_cfa_offset 8
callq __hipRegisterVar
addq $16, %rsp
.cfi_adjust_cfa_offset -16
movl $colors, %esi
movl $.L__unnamed_4, %edx
movl $.L__unnamed_4, %ecx
movl $8192, %r9d # imm = 0x2000
movq %rbx, %rdi
xorl %r8d, %r8d
pushq $0
.cfi_adjust_cfa_offset 8
pushq $0
.cfi_adjust_cfa_offset 8
callq __hipRegisterVar
addq $16, %rsp
.cfi_adjust_cfa_offset -16
movl $__hip_module_dtor, %edi
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type adjList,@object # @adjList
.local adjList
.comm adjList,16384,16
.type adjListPtr,@object # @adjListPtr
.local adjListPtr
.comm adjListPtr,8196,16
.type colors,@object # @colors
.local colors
.comm colors,8192,16
.type _Z19graphColoringKernelv,@object # @_Z19graphColoringKernelv
.section .rodata,"a",@progbits
.globl _Z19graphColoringKernelv
.p2align 3, 0x0
_Z19graphColoringKernelv:
.quad _Z34__device_stub__graphColoringKernelv
.size _Z19graphColoringKernelv, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "CUDA error: "
.size .L.str, 13
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz " ("
.size .L.str.1, 3
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz ")"
.size .L.str.2, 2
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "hipMalloc d_adjList"
.size .L.str.3, 20
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "hipMalloc d_adjListPtr"
.size .L.str.4, 23
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "hipMalloc d_colors"
.size .L.str.5, 19
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "hipMemcpy d_adjList"
.size .L.str.6, 20
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "hipMemcpy d_adjListPtr"
.size .L.str.7, 23
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "graphColoringKernel launch"
.size .L.str.8, 27
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "hipMemcpy d_colors"
.size .L.str.9, 19
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "Node colors:"
.size .L.str.10, 13
.type .L.str.11,@object # @.str.11
.L.str.11:
.asciz "Node "
.size .L.str.11, 6
.type .L.str.12,@object # @.str.12
.L.str.12:
.asciz ": Color "
.size .L.str.12, 9
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z19graphColoringKernelv"
.size .L__unnamed_1, 25
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "adjList"
.size .L__unnamed_2, 8
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "adjListPtr"
.size .L__unnamed_3, 11
.type .L__unnamed_4,@object # @3
.L__unnamed_4:
.asciz "colors"
.size .L__unnamed_4, 7
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z34__device_stub__graphColoringKernelv
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym adjList
.addrsig_sym adjListPtr
.addrsig_sym colors
.addrsig_sym _Z19graphColoringKernelv
.addrsig_sym _ZSt4cerr
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
```
| 6,103 | 6,075 |
113,674 |
Convert the following CUDA device assembly code to AMD device assembly:
```cudaasm
code for sm_80
Function : _Z21bilateralFilterKernelPKfPfiiff
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
MOV R1, c[0x0][0x28] ;
S2R R9, SR_CTAID.X ;
ULDC.64 UR10, c[0x0][0x118] ;
S2R R2, SR_TID.X ;
S2R R3, SR_CTAID.Y ;
S2R R10, SR_TID.Y ;
IMAD R9, R9, c[0x0][0x0], R2 ;
ISETP.GE.AND P1, PT, R9, c[0x0][0x170], PT ;
IMAD R8, R3, c[0x0][0x4], R10 ;
LOP3.LUT R0, R9, R8, RZ, 0xfc, !PT ;
ISETP.GT.AND P0, PT, R0, -0x1, !P1 ;
ISETP.LT.AND P0, PT, R8, c[0x0][0x174], P0 ;
@P0 MOV R5, 0x4 ;
@P0 IMAD R4, R8, c[0x0][0x170], R9 ;
@P0 IMAD.WIDE R4, R4, R5, c[0x0][0x160] ;
@P0 LDG.E R0, [R4.64] ;
SHF.L.U32 R7, R2.reuse, 0x2, RZ ;
BSSY B0, 0x2e0 ;
ISETP.GT.U32.AND P2, PT, R2, 0x4, PT ;
ISETP.GT.U32.AND P3, PT, R10.reuse, 0x4, PT ;
IMAD R3, R10, 0x68, R7 ;
@!P0 STS [R3+0x21c], RZ ;
@P2 BRA 0x2d0 ;
ISETP.GE.AND P2, PT, R8, c[0x0][0x174], PT ;
ISETP.GT.AND P2, PT, R8, -0x1, !P2 ;
@!P2 STS [R3+0x208], RZ ;
@!P2 STS [R3+0x25c], RZ ;
@!P2 BRA 0x2d0 ;
IADD3 R4, R9.reuse, 0xb, RZ ;
IMAD R2, R8, c[0x0][0x170], RZ ;
HFMA2.MMA R13, -RZ, RZ, 0, 2.384185791015625e-07 ;
ISETP.GT.AND P2, PT, R9, 0x4, PT ;
ISETP.GE.AND P4, PT, R4, c[0x0][0x170], PT ;
IADD3 R4, R9, R2.reuse, RZ ;
IADD3 R6, R2, c[0x0][0x170], RZ ;
IADD3 R5, R4.reuse, -0x5, RZ ;
IADD3 R12, R4, 0xb, RZ ;
SEL R5, R5, R2, P2 ;
@P4 IADD3 R12, R6, -0x1, RZ ;
IMAD.WIDE R4, R5, R13, c[0x0][0x160] ;
IMAD.WIDE R12, R12, R13, c[0x0][0x160] ;
LDG.E R4, [R4.64] ;
LDG.E R12, [R12.64] ;
STS [R3+0x208], R4 ;
STS [R3+0x25c], R12 ;
BSYNC B0 ;
BSSY B0, 0x450 ;
@P3 BRA 0x440 ;
ISETP.GT.AND P1, PT, R9, -0x1, !P1 ;
@!P1 STS [R3+0x14], RZ ;
@!P1 STS [R3+0x89c], RZ ;
@!P1 BRA 0x440 ;
IADD3 R4, R8.reuse, 0xb, RZ ;
HFMA2.MMA R13, -RZ, RZ, 0, 2.384185791015625e-07 ;
IADD3 R2, R8, -0x5, RZ ;
ISETP.GE.AND P2, PT, R4, c[0x0][0x174], PT ;
MOV R5, c[0x0][0x174] ;
IMAD R2, R2, c[0x0][0x170], R9 ;
ISETP.GT.AND P1, PT, R8, 0x4, PT ;
SEL R2, R2, R9, P1 ;
@P2 IADD3 R4, R5, -0x1, RZ ;
IMAD R12, R4, c[0x0][0x170], R9 ;
IMAD.WIDE R4, R2, R13, c[0x0][0x160] ;
IMAD.WIDE R12, R12, R13, c[0x0][0x160] ;
LDG.E R4, [R4.64] ;
LDG.E R12, [R12.64] ;
STS [R3+0x14], R4 ;
STS [R3+0x89c], R12 ;
BSYNC B0 ;
@P0 STS [R3+0x21c], R0 ;
BAR.SYNC.DEFER_BLOCKING 0x0 ;
@!P0 EXIT ;
LDS R6, [R3+0x21c] ;
MOV R5, c[0x0][0x178] ;
HFMA2.MMA R20, -RZ, RZ, 0, 0 ;
MOV R4, c[0x0][0x17c] ;
UMOV UR5, 0xfffffffb ;
MOV R19, RZ ;
FADD R5, R5, c[0x0][0x178] ;
FADD R4, R4, c[0x0][0x17c] ;
FMUL R5, R5, c[0x0][0x178] ;
FMUL R4, R4, c[0x0][0x17c] ;
IADD3 R0, R10, UR5, RZ ;
UIMAD UR9, UR5, UR5, URZ ;
UIADD3 UR5, UR5, 0x1, URZ ;
IMAD R3, R0, 0x68, R7 ;
UMOV UR6, 0xfffffffe ;
UISETP.GE.AND UP1, UPT, UR5, 0x6, UPT ;
UMOV UR7, 0x208 ;
UMOV UR8, 0xfffffffc ;
UIADD3 UR4, UR6, -0x3, URZ ;
MUFU.RCP R0, R5 ;
IADD3 R2, R3, UR7, RZ ;
UIMAD UR4, UR4, UR4, UR9 ;
UIADD3 UR4, -UR4, URZ, URZ ;
I2F R14, UR4 ;
FFMA R11, -R5, R0, 1 ;
FFMA R11, R0, R11, R0 ;
FCHK P0, R14, R5 ;
FFMA R0, R14, R11, RZ ;
FFMA R12, -R5, R0, R14 ;
FFMA R0, R11, R12, R0 ;
@!P0 BRA 0x6a0 ;
MOV R13, R5 ;
MOV R12, 0x6a0 ;
CALL.REL.NOINC 0x1560 ;
LDS R21, [R2] ;
HFMA2.MMA R11, -RZ, RZ, 0.96630859375, -0.0022525787353515625 ;
MOV R12, 0x437c0000 ;
MUFU.RCP R15, R4 ;
BSSY B0, 0x850 ;
FFMA.SAT R11, R0, R11, 0.5 ;
FFMA.RM R11, R11, R12, 12582913 ;
FADD R13, R11.reuse, -12583039 ;
SHF.L.U32 R22, R11, 0x17, RZ ;
FFMA R12, -R4, R15, 1 ;
FFMA R13, R0.reuse, 1.4426950216293334961, -R13 ;
FFMA R12, R15, R12, R15 ;
FFMA R13, R0, 1.925963033500011079e-08, R13 ;
MUFU.EX2 R13, R13 ;
FADD R0, -R6, R21 ;
FMUL R17, R0, R0 ;
FCHK P0, -R17, R4 ;
FFMA R15, -R17, R12, RZ ;
FMUL R22, R22, R13 ;
FFMA R0, -R4, R15, -R17 ;
FFMA R0, R12, R0, R15 ;
@!P0 BRA 0x840 ;
FADD R14, -R17, -RZ ;
MOV R13, R4 ;
MOV R12, 0x840 ;
CALL.REL.NOINC 0x1560 ;
BSYNC B0 ;
HFMA2.MMA R11, -RZ, RZ, 0.96630859375, -0.0022525787353515625 ;
UIMAD UR4, UR8, UR8, UR9 ;
MOV R12, 0x437c0000 ;
MUFU.RCP R16, R5 ;
UIADD3 UR4, -UR4, URZ, URZ ;
FFMA.SAT R11, R0, R11, 0.5 ;
FFMA.RM R11, R11, R12, 12582913 ;
I2F R14, UR4 ;
FADD R13, R11.reuse, -12583039 ;
SHF.L.U32 R11, R11, 0x17, RZ ;
FFMA R15, -R5, R16, 1 ;
FFMA R13, R0, 1.4426950216293334961, -R13 ;
FFMA R17, R16, R15, R16 ;
FFMA R13, R0, 1.925963033500011079e-08, R13 ;
MUFU.EX2 R0, R13 ;
FFMA R12, R17, R14, RZ ;
FFMA R15, -R5, R12, R14 ;
FCHK P0, R14, R5 ;
FFMA R12, R17, R15, R12 ;
FMUL R11, R11, R0 ;
FMUL R22, R22, R11 ;
FFMA R19, R21, R22, R19 ;
FADD R20, R22, R20 ;
@!P0 BRA 0xa10 ;
MOV R13, R5 ;
MOV R12, 0xa00 ;
CALL.REL.NOINC 0x1560 ;
MOV R12, R0 ;
LDS R21, [R2+0x4] ;
MOV R11, 0x3bbb989d ;
BSSY B0, 0xbc0 ;
MOV R13, 0x437c0000 ;
FFMA.SAT R0, R12, R11, 0.5 ;
FFMA.RM R0, R0, R13, 12582913 ;
MUFU.RCP R13, R4 ;
FADD R11, R0.reuse, -12583039 ;
SHF.L.U32 R22, R0, 0x17, RZ ;
FFMA R11, R12, 1.4426950216293334961, -R11 ;
FFMA R11, R12, 1.925963033500011079e-08, R11 ;
MUFU.EX2 R11, R11 ;
FFMA R14, -R4, R13, 1 ;
FFMA R14, R13, R14, R13 ;
FADD R12, -R6, R21 ;
FMUL R15, R12, R12 ;
FMUL R22, R22, R11 ;
FCHK P0, -R15, R4 ;
FFMA R13, R14, -R15, RZ ;
FFMA R0, -R4, R13, -R15 ;
FFMA R0, R14, R0, R13 ;
@!P0 BRA 0xbb0 ;
FADD R14, -R15, -RZ ;
MOV R13, R4 ;
MOV R12, 0xbb0 ;
CALL.REL.NOINC 0x1560 ;
BSYNC B0 ;
HFMA2.MMA R11, -RZ, RZ, 0.96630859375, -0.0022525787353515625 ;
UIADD3 UR4, UR6, -0x1, URZ ;
MOV R12, 0x437c0000 ;
MUFU.RCP R16, R5 ;
UIMAD UR4, UR4, UR4, UR9 ;
UIADD3 UR4, -UR4, URZ, URZ ;
FFMA.SAT R11, R0, R11, 0.5 ;
FFMA.RM R11, R11, R12, 12582913 ;
FADD R13, R11, -12583039 ;
I2F R14, UR4 ;
FFMA R15, -R5, R16, 1 ;
SHF.L.U32 R11, R11, 0x17, RZ ;
FFMA R13, R0, 1.4426950216293334961, -R13 ;
FFMA R17, R16, R15, R16 ;
FFMA R13, R0, 1.925963033500011079e-08, R13 ;
MUFU.EX2 R0, R13 ;
FFMA R12, R17, R14, RZ ;
FCHK P0, R14, R5 ;
FFMA R15, -R5, R12, R14 ;
FFMA R12, R17, R15, R12 ;
FMUL R11, R11, R0 ;
FMUL R22, R22, R11 ;
FFMA R19, R21, R22, R19 ;
FADD R20, R20, R22 ;
@!P0 BRA 0xd90 ;
MOV R13, R5 ;
MOV R12, 0xd80 ;
CALL.REL.NOINC 0x1560 ;
MOV R12, R0 ;
LDS R21, [R2+0x8] ;
MOV R11, 0x3bbb989d ;
BSSY B0, 0xf40 ;
MOV R13, 0x437c0000 ;
FFMA.SAT R0, R12, R11, 0.5 ;
FFMA.RM R0, R0, R13, 12582913 ;
MUFU.RCP R13, R4 ;
FADD R11, R0.reuse, -12583039 ;
SHF.L.U32 R22, R0, 0x17, RZ ;
FFMA R11, R12, 1.4426950216293334961, -R11 ;
FFMA R11, R12, 1.925963033500011079e-08, R11 ;
MUFU.EX2 R11, R11 ;
FFMA R14, -R4, R13, 1 ;
FFMA R14, R13, R14, R13 ;
FADD R12, -R6, R21 ;
FMUL R15, R12, R12 ;
FMUL R22, R22, R11 ;
FCHK P0, -R15, R4 ;
FFMA R13, R14, -R15, RZ ;
FFMA R0, -R4, R13, -R15 ;
FFMA R0, R14, R0, R13 ;
@!P0 BRA 0xf30 ;
FADD R14, -R15, -RZ ;
MOV R13, R4 ;
MOV R12, 0xf30 ;
CALL.REL.NOINC 0x1560 ;
BSYNC B0 ;
HFMA2.MMA R11, -RZ, RZ, 0.96630859375, -0.0022525787353515625 ;
MOV R12, 0x437c0000 ;
UISETP.NE.AND UP0, UPT, UR7, 0x228, UPT ;
PLOP3.LUT P0, PT, PT, PT, UP0, 0x80, 0x0 ;
FFMA.SAT R11, R0, R11, 0.5 ;
FFMA.RM R11, R11, R12, 12582913 ;
FADD R13, R11.reuse, -12583039 ;
SHF.L.U32 R11, R11, 0x17, RZ ;
FFMA R13, R0, 1.4426950216293334961, -R13 ;
FFMA R13, R0, 1.925963033500011079e-08, R13 ;
MUFU.EX2 R0, R13 ;
FMUL R11, R11, R0 ;
FMUL R22, R22, R11 ;
FFMA R19, R21, R22, R19 ;
FADD R20, R20, R22 ;
@!P0 BRA 0x13f0 ;
UIMAD UR4, UR6, UR6, UR9 ;
MUFU.RCP R0, R5 ;
UIADD3 UR4, -UR4, URZ, URZ ;
I2F R14, UR4 ;
FFMA R11, -R5, R0, 1 ;
FFMA R13, R0, R11, R0 ;
FCHK P0, R14, R5 ;
FFMA R0, R14, R13, RZ ;
FFMA R11, -R5, R0, R14 ;
FFMA R0, R11, R13, R0 ;
@!P0 BRA 0x1120 ;
MOV R13, R5 ;
MOV R12, 0x1120 ;
CALL.REL.NOINC 0x1560 ;
LDS R2, [R2+0xc] ;
HFMA2.MMA R11, -RZ, RZ, 0.96630859375, -0.0022525787353515625 ;
MOV R12, 0x437c0000 ;
MUFU.RCP R15, R4 ;
BSSY B0, 0x12e0 ;
FFMA.SAT R11, R0, R11, 0.5 ;
FFMA.RM R11, R11, R12, 12582913 ;
FADD R13, R11.reuse, -12583039 ;
SHF.L.U32 R21, R11, 0x17, RZ ;
FFMA R14, -R4, R15, 1 ;
FFMA R13, R0.reuse, 1.4426950216293334961, -R13 ;
FFMA R14, R15, R14, R15 ;
FFMA R13, R0, 1.925963033500011079e-08, R13 ;
MUFU.EX2 R0, R13 ;
FADD R12, -R6, R2 ;
FMUL R17, R12, R12 ;
FMUL R21, R21, R0 ;
FCHK P0, -R17, R4 ;
FFMA R15, -R17, R14, RZ ;
FFMA R12, -R4, R15, -R17 ;
FFMA R12, R12, R14, R15 ;
@!P0 BRA 0x12d0 ;
FADD R14, -R17, -RZ ;
MOV R13, R4 ;
MOV R12, 0x12c0 ;
CALL.REL.NOINC 0x1560 ;
MOV R12, R0 ;
BSYNC B0 ;
HFMA2.MMA R11, -RZ, RZ, 0.96630859375, -0.0022525787353515625 ;
MOV R13, 0x437c0000 ;
UIADD3 UR6, UR6, 0x4, URZ ;
UIADD3 UR7, UR7, 0x10, URZ ;
UIADD3 UR8, UR8, 0x4, URZ ;
FFMA.SAT R0, R12, R11, 0.5 ;
FFMA.RM R0, R0, R13, 12582913 ;
FADD R11, R0.reuse, -12583039 ;
SHF.L.U32 R0, R0, 0x17, RZ ;
FFMA R11, R12, 1.4426950216293334961, -R11 ;
FFMA R11, R12, 1.925963033500011079e-08, R11 ;
MUFU.EX2 R11, R11 ;
FMUL R0, R0, R11 ;
FMUL R21, R21, R0 ;
FFMA R19, R2, R21, R19 ;
FADD R20, R20, R21 ;
BRA 0x5a0 ;
PLOP3.LUT P0, PT, PT, PT, UP1, 0x80, 0x0 ;
@P0 CALL.REL.NOINC 0x1420 ;
BRA 0x520 ;
MUFU.RCP R3, R20 ;
BSSY B0, 0x1510 ;
FCHK P0, R19, R20 ;
FFMA R0, -R20, R3, 1 ;
FFMA R0, R3, R0, R3 ;
FFMA R3, R19, R0, RZ ;
FFMA R2, -R20, R3, R19 ;
FFMA R5, R0, R2, R3 ;
@!P0 BRA 0x1500 ;
MOV R14, R19 ;
MOV R13, R20 ;
MOV R12, 0x14f0 ;
CALL.REL.NOINC 0x1560 ;
MOV R5, R0 ;
BSYNC B0 ;
HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ;
IMAD R2, R8, c[0x0][0x170], R9 ;
IMAD.WIDE R2, R2, R3, c[0x0][0x168] ;
STG.E [R2.64], R5 ;
EXIT ;
SHF.R.U32.HI R0, RZ, 0x17, R13 ;
BSSY B1, 0x1ba0 ;
SHF.R.U32.HI R15, RZ, 0x17, R14 ;
LOP3.LUT R0, R0, 0xff, RZ, 0xc0, !PT ;
LOP3.LUT R15, R15, 0xff, RZ, 0xc0, !PT ;
IADD3 R16, R0, -0x1, RZ ;
IADD3 R17, R15, -0x1, RZ ;
ISETP.GT.U32.AND P0, PT, R16, 0xfd, PT ;
ISETP.GT.U32.OR P0, PT, R17, 0xfd, P0 ;
@!P0 MOV R11, RZ ;
@!P0 BRA 0x1780 ;
FSETP.GTU.FTZ.AND P0, PT, |R14|, +INF , PT ;
FSETP.GTU.FTZ.AND P1, PT, |R13|, +INF , PT ;
PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ;
@P0 BRA 0x1b80 ;
LOP3.LUT P0, RZ, R13, 0x7fffffff, R14, 0xc8, !PT ;
@!P0 BRA 0x1b60 ;
FSETP.NEU.FTZ.AND P1, PT, |R14|.reuse, +INF , PT ;
FSETP.NEU.FTZ.AND P2, PT, |R13|, +INF , PT ;
FSETP.NEU.FTZ.AND P0, PT, |R14|, +INF , PT ;
@!P2 BRA !P1, 0x1b60 ;
LOP3.LUT P1, RZ, R14, 0x7fffffff, RZ, 0xc0, !PT ;
PLOP3.LUT P1, PT, P2, P1, PT, 0x2a, 0x0 ;
@P1 BRA 0x1b40 ;
LOP3.LUT P1, RZ, R13, 0x7fffffff, RZ, 0xc0, !PT ;
PLOP3.LUT P0, PT, P0, P1, PT, 0x2a, 0x0 ;
@P0 BRA 0x1b10 ;
ISETP.GE.AND P0, PT, R17, RZ, PT ;
ISETP.GE.AND P1, PT, R16, RZ, PT ;
@P0 MOV R11, RZ ;
@!P0 FFMA R14, R14, 1.84467440737095516160e+19, RZ ;
@!P0 MOV R11, 0xffffffc0 ;
@!P1 FFMA R13, R13, 1.84467440737095516160e+19, RZ ;
@!P1 IADD3 R11, R11, 0x40, RZ ;
LEA R16, R0, 0xc0800000, 0x17 ;
BSSY B2, 0x1b00 ;
IADD3 R15, R15, -0x7f, RZ ;
IADD3 R23, -R16, R13, RZ ;
IMAD R14, R15, -0x800000, R14 ;
MUFU.RCP R16, R23 ;
FADD.FTZ R13, -R23, -RZ ;
FFMA R17, R16, R13, 1 ;
FFMA R17, R16, R17, R16 ;
FFMA R16, R14, R17, RZ ;
FFMA R18, R13, R16, R14 ;
FFMA R18, R17, R18, R16 ;
IADD3 R16, R15, 0x7f, -R0 ;
FFMA R13, R13, R18, R14 ;
IADD3 R11, R16, R11, RZ ;
FFMA R14, R17, R13, R18 ;
SHF.R.U32.HI R0, RZ, 0x17, R14 ;
LOP3.LUT R0, R0, 0xff, RZ, 0xc0, !PT ;
IADD3 R0, R0, R11, RZ ;
IADD3 R15, R0, -0x1, RZ ;
ISETP.GE.U32.AND P0, PT, R15, 0xfe, PT ;
@!P0 BRA 0x1ae0 ;
ISETP.GT.AND P0, PT, R0, 0xfe, PT ;
@P0 BRA 0x1ab0 ;
ISETP.GE.AND P0, PT, R0, 0x1, PT ;
@P0 BRA 0x1af0 ;
ISETP.GE.AND P0, PT, R0, -0x18, PT ;
LOP3.LUT R14, R14, 0x80000000, RZ, 0xc0, !PT ;
@!P0 BRA 0x1af0 ;
FFMA.RZ R11, R17.reuse, R13.reuse, R18.reuse ;
ISETP.NE.AND P2, PT, R0.reuse, RZ, PT ;
FFMA.RP R15, R17.reuse, R13.reuse, R18.reuse ;
ISETP.NE.AND P1, PT, R0.reuse, RZ, PT ;
FFMA.RM R18, R17, R13, R18 ;
LOP3.LUT R11, R11, 0x7fffff, RZ, 0xc0, !PT ;
IADD3 R13, R0.reuse, 0x20, RZ ;
LOP3.LUT R16, R11, 0x800000, RZ, 0xfc, !PT ;
IADD3 R0, -R0, RZ, RZ ;
SHF.L.U32 R13, R16, R13, RZ ;
FSETP.NEU.FTZ.AND P0, PT, R15, R18, PT ;
SEL R11, R0, RZ, P2 ;
ISETP.NE.AND P1, PT, R13, RZ, P1 ;
SHF.R.U32.HI R11, RZ, R11, R16 ;
PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ;
SHF.R.U32.HI R0, RZ, 0x1, R11 ;
SEL R13, RZ, 0x1, !P0 ;
LOP3.LUT R16, R13, 0x1, R0, 0xf8, !PT ;
LOP3.LUT R11, R16, R11, RZ, 0xc0, !PT ;
IADD3 R11, R0, R11, RZ ;
LOP3.LUT R14, R11, R14, RZ, 0xfc, !PT ;
BRA 0x1af0 ;
LOP3.LUT R14, R14, 0x80000000, RZ, 0xc0, !PT ;
LOP3.LUT R14, R14, 0x7f800000, RZ, 0xfc, !PT ;
BRA 0x1af0 ;
LEA R14, R11, R14, 0x17 ;
BSYNC B2 ;
BRA 0x1b90 ;
LOP3.LUT R14, R13, 0x80000000, R14, 0x48, !PT ;
LOP3.LUT R14, R14, 0x7f800000, RZ, 0xfc, !PT ;
BRA 0x1b90 ;
LOP3.LUT R14, R13, 0x80000000, R14, 0x48, !PT ;
BRA 0x1b90 ;
MUFU.RSQ R14, -QNAN ;
BRA 0x1b90 ;
FADD.FTZ R14, R14, R13 ;
BSYNC B1 ;
HFMA2.MMA R13, -RZ, RZ, 0, 0 ;
MOV R0, R14 ;
RET.REL.NODEC R12 0x0 ;
BRA 0x1bd0;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
```
|
```amdasm
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z21bilateralFilterKernelPKfPfiiff ; -- Begin function _Z21bilateralFilterKernelPKfPfiiff
.globl _Z21bilateralFilterKernelPKfPfiiff
.p2align 8
.type _Z21bilateralFilterKernelPKfPfiiff,@function
_Z21bilateralFilterKernelPKfPfiiff: ; @_Z21bilateralFilterKernelPKfPfiiff
; %bb.0:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b256 s[4:11], s[0:1], 0x0
v_and_b32_e32 v5, 0x3ff, v0
v_bfe_u32 v0, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s0, s2, 0xffff
s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[1:2], null, s14, s0, v[5:6]
v_mov_b32_e32 v2, 0
s_lshr_b32 s0, s2, 16
s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[3:4], null, s15, s0, v[0:1]
v_cmp_lt_i32_e32 vcc_lo, -1, v1
s_and_saveexec_b32 s3, vcc_lo
s_cbranch_execz .LBB0_4
; %bb.1:
v_cmp_gt_i32_e64 s0, s8, v1
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_cmp_gt_i32_e64 s1, s9, v3
v_cmp_lt_i32_e64 s2, -1, v3
v_mov_b32_e32 v2, 0
s_and_b32 s0, s0, s1
s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
s_and_b32 s0, s0, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_3
; %bb.2:
v_mad_u64_u32 v[6:7], null, v3, s8, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v7, 31, v6
v_lshlrev_b64 v[6:7], 2, v[6:7]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v6, s0, s4, v6
v_add_co_ci_u32_e64 v7, s0, s5, v7, s0
global_load_b32 v2, v[6:7], off
.LBB0_3: ; %Flow193
s_or_b32 exec_lo, exec_lo, s1
.LBB0_4:
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
s_or_b32 exec_lo, exec_lo, s3
v_lshlrev_b32_e32 v4, 2, v5
s_mov_b32 s12, exec_lo
v_mad_u32_u24 v8, 0x68, v0, v4
s_waitcnt vmcnt(0)
ds_store_b32 v8, v2 offset:540
v_cmpx_gt_u32_e32 5, v5
s_cbranch_execz .LBB0_14
; %bb.5:
v_cmp_gt_i32_e64 s0, 0, v3
v_cmp_le_i32_e64 s1, s9, v3
s_mov_b32 s2, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_or_b32 s0, s0, s1
s_and_saveexec_b32 s1, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s0, exec_lo, s1
s_cbranch_execz .LBB0_7
; %bb.6:
v_mov_b32_e32 v2, 0
ds_store_b32 v8, v2 offset:520
.LBB0_7: ; %Flow190
s_or_saveexec_b32 s1, s0
v_mov_b32_e32 v2, s2
s_xor_b32 exec_lo, exec_lo, s1
s_cbranch_execz .LBB0_13
; %bb.8:
v_add_nc_u32_e32 v5, -5, v1
v_cmp_lt_i32_e64 s0, 4, v1
v_mul_lo_u32 v2, v3, s8
; implicit-def: $sgpr2_sgpr3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e64 v4, 0, v5, s0
v_add_nc_u32_e32 v6, v2, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v7, 31, v6
v_lshlrev_b64 v[6:7], 2, v[6:7]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v6, s0, s4, v6
v_add_co_ci_u32_e64 v7, s0, s5, v7, s0
global_load_b32 v4, v[6:7], off
v_add_nc_u32_e32 v6, 11, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
v_cmp_le_i32_e64 s0, s8, v6
s_waitcnt vmcnt(0)
ds_store_b32 v8, v4 offset:520
; implicit-def: $vgpr4
s_and_saveexec_b32 s13, s0
s_xor_b32 s0, exec_lo, s13
; %bb.9:
v_add_nc_u32_e32 v4, s8, v2
s_mov_b64 s[2:3], -1
; implicit-def: $vgpr2
; implicit-def: $vgpr5
; %bb.10: ; %Flow189
s_or_saveexec_b32 s0, s0
v_dual_mov_b32 v7, s3 :: v_dual_mov_b32 v6, s2
s_xor_b32 exec_lo, exec_lo, s0
; %bb.11:
v_mov_b32_e32 v6, 16
v_dual_mov_b32 v7, 0 :: v_dual_add_nc_u32 v4, v2, v5
; %bb.12:
s_or_b32 exec_lo, exec_lo, s0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v5, 31, v4
v_lshlrev_b64 v[6:7], 2, v[6:7]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[4:5], 2, v[4:5]
v_add_co_u32 v2, s0, s4, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_ci_u32_e64 v5, s0, s5, v5, s0
v_add_co_u32 v4, s0, v2, v6
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v5, s0, v5, v7, s0
global_load_b32 v2, v[4:5], off
.LBB0_13: ; %Flow191
s_or_b32 exec_lo, exec_lo, s1
s_waitcnt vmcnt(0)
ds_store_b32 v8, v2 offset:604
.LBB0_14: ; %Flow192
s_or_b32 exec_lo, exec_lo, s12
s_delay_alu instid0(SALU_CYCLE_1)
s_mov_b32 s1, exec_lo
v_cmpx_gt_u32_e32 5, v0
s_cbranch_execz .LBB0_24
; %bb.15:
v_cmp_le_i32_e64 s0, s8, v1
s_xor_b32 s2, vcc_lo, -1
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
s_or_b32 s2, s2, s0
; implicit-def: $sgpr0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_saveexec_b32 s3, s2
s_xor_b32 s2, exec_lo, s3
s_cbranch_execz .LBB0_17
; %bb.16:
v_mov_b32_e32 v0, 0
s_mov_b32 s0, 0
ds_store_b32 v8, v0 offset:20
.LBB0_17: ; %Flow186
s_or_saveexec_b32 s2, s2
v_mov_b32_e32 v0, s0
s_xor_b32 exec_lo, exec_lo, s2
s_cbranch_execz .LBB0_23
; %bb.18:
v_cmp_gt_i32_e64 s0, 5, v3
; implicit-def: $vgpr4_vgpr5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_saveexec_b32 s3, s0
s_xor_b32 s0, exec_lo, s3
; %bb.19:
v_mov_b32_e32 v2, 0
s_delay_alu instid0(VALU_DEP_1)
v_dual_mov_b32 v5, v2 :: v_dual_mov_b32 v4, v1
; %bb.20: ; %Flow185
s_and_not1_saveexec_b32 s0, s0
; %bb.21:
v_add_nc_u32_e32 v0, -5, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[4:5], null, v0, s8, v[1:2]
v_ashrrev_i32_e32 v5, 31, v4
; %bb.22:
s_or_b32 exec_lo, exec_lo, s0
v_add_nc_u32_e32 v0, 11, v3
s_add_i32 s3, s9, -1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[4:5], 2, v[4:5]
v_cmp_gt_i32_e64 s0, s9, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cndmask_b32_e64 v0, s3, v0, s0
v_add_co_u32 v4, s0, s4, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e64 v5, s0, s5, v5, s0
v_mad_u64_u32 v[6:7], null, v0, s8, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v7, 31, v6
v_lshlrev_b64 v[6:7], 2, v[6:7]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v6, s0, s4, v6
v_add_co_ci_u32_e64 v7, s0, s5, v7, s0
s_clause 0x1
global_load_b32 v2, v[4:5], off
global_load_b32 v0, v[6:7], off
s_waitcnt vmcnt(1)
ds_store_b32 v8, v2 offset:20
.LBB0_23: ; %Flow187
s_or_b32 exec_lo, exec_lo, s2
s_waitcnt vmcnt(0)
ds_store_b32 v8, v0 offset:2204
.LBB0_24: ; %Flow188
s_or_b32 exec_lo, exec_lo, s1
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_and_saveexec_b32 s0, vcc_lo
s_cbranch_execz .LBB0_31
; %bb.25:
v_cmp_gt_i32_e32 vcc_lo, s8, v1
v_cmp_gt_i32_e64 s0, s9, v3
v_cmp_lt_i32_e64 s1, -1, v3
s_delay_alu instid0(VALU_DEP_2)
s_and_b32 s0, vcc_lo, s0
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
s_and_b32 s0, s0, s1
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 exec_lo, exec_lo, s0
s_cbranch_execz .LBB0_31
; %bb.26:
ds_load_b32 v4, v8 offset:540
v_add_f32_e64 v0, s10, s10
v_add_f32_e64 v2, s11, s11
s_mov_b32 s1, -5
s_delay_alu instid0(VALU_DEP_1)
v_dual_mul_f32 v5, s10, v0 :: v_dual_mul_f32 v6, s11, v2
v_mov_b32_e32 v0, 0
v_mov_b32_e32 v2, 0
.LBB0_27: ; %.preheader
; =>This Loop Header: Depth=1
; Child Loop BB0_28 Depth 2
s_delay_alu instid0(VALU_DEP_1)
v_mov_b32_e32 v7, v8
s_mul_i32 s2, s1, s1
s_mov_b32 s3, -5
.LBB0_28: ; Parent Loop BB0_27 Depth=1
; => This Inner Loop Header: Depth=2
ds_load_b32 v9, v7
s_mul_i32 s0, s3, s3
s_add_i32 s3, s3, 1
s_add_i32 s0, s2, s0
v_add_nc_u32_e32 v7, 4, v7
s_sub_i32 s0, 0, s0
s_cmp_eq_u32 s3, 6
v_cvt_f32_i32_e32 v11, s0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_div_scale_f32 v12, null, v5, v5, v11
v_div_scale_f32 v16, vcc_lo, v11, v5, v11
v_rcp_f32_e32 v14, v12
s_waitcnt lgkmcnt(0)
v_sub_f32_e32 v10, v9, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_2)
v_mul_f32_e64 v10, v10, -v10
s_waitcnt_depctr 0xfff
v_fma_f32 v17, -v12, v14, 1.0
v_div_scale_f32 v13, null, v6, v6, v10
v_div_scale_f32 v18, s0, v10, v6, v10
v_rcp_f32_e32 v15, v13
s_waitcnt_depctr 0xfff
v_fma_f32 v19, -v13, v15, 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_fmac_f32 v15, v19, v15 :: v_dual_fmac_f32 v14, v17, v14
v_mul_f32_e32 v19, v18, v15
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_f32_e32 v17, v16, v14
v_fma_f32 v21, -v13, v19, v18
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v20, -v12, v17, v16
v_fmac_f32_e32 v19, v21, v15
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fmac_f32_e32 v17, v20, v14
v_fma_f32 v13, -v13, v19, v18
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v12, -v12, v17, v16
v_div_fmas_f32 v12, v12, v14, v17
s_mov_b32 vcc_lo, s0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_div_fmas_f32 v13, v13, v15, v19
v_div_fixup_f32 v11, v12, v5, v11
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_div_fixup_f32 v10, v13, v6, v10
v_mul_f32_e32 v12, 0x3fb8aa3b, v11
v_cmp_ngt_f32_e32 vcc_lo, 0xc2ce8ed0, v11
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_fma_f32 v14, 0x3fb8aa3b, v11, -v12
v_rndne_f32_e32 v15, v12
v_mul_f32_e32 v13, 0x3fb8aa3b, v10
v_fmac_f32_e32 v14, 0x32a5705f, v11
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_sub_f32_e32 v12, v12, v15
v_fma_f32 v16, 0x3fb8aa3b, v10, -v13
v_rndne_f32_e32 v17, v13
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f32_e32 v12, v12, v14
v_dual_fmac_f32 v16, 0x32a5705f, v10 :: v_dual_sub_f32 v13, v13, v17
v_cvt_i32_f32_e32 v14, v15
v_cvt_i32_f32_e32 v15, v17
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_exp_f32_e32 v12, v12
v_add_f32_e32 v13, v13, v16
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
v_exp_f32_e32 v13, v13
s_waitcnt_depctr 0xfff
v_ldexp_f32 v12, v12, v14
v_ldexp_f32 v13, v13, v15
v_cndmask_b32_e32 v12, 0, v12, vcc_lo
v_cmp_ngt_f32_e32 vcc_lo, 0xc2ce8ed0, v10
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_cndmask_b32_e32 v13, 0, v13, vcc_lo
v_cmp_nlt_f32_e32 vcc_lo, 0x42b17218, v11
v_cndmask_b32_e32 v11, 0x7f800000, v12, vcc_lo
v_cmp_nlt_f32_e32 vcc_lo, 0x42b17218, v10
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v10, 0x7f800000, v13, vcc_lo
v_mul_f32_e32 v12, v11, v10
v_fmac_f32_e32 v2, v11, v10
s_delay_alu instid0(VALU_DEP_2)
v_fmac_f32_e32 v0, v9, v12
s_cbranch_scc0 .LBB0_28
; %bb.29: ; in Loop: Header=BB0_27 Depth=1
v_add_nc_u32_e32 v8, 0x68, v8
s_add_i32 s1, s1, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s1, 6
s_cbranch_scc0 .LBB0_27
; %bb.30:
v_div_scale_f32 v6, null, v2, v2, v0
v_div_scale_f32 v8, vcc_lo, v0, v2, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f32_e32 v7, v6
s_waitcnt_depctr 0xfff
v_fma_f32 v4, -v6, v7, 1.0
v_fmac_f32_e32 v7, v4, v7
v_mad_u64_u32 v[4:5], null, v3, s8, v[1:2]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_f32_e32 v9, v8, v7
v_ashrrev_i32_e32 v5, 31, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v10, -v6, v9, v8
v_lshlrev_b64 v[3:4], 2, v[4:5]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v9, v10, v7
v_fma_f32 v1, -v6, v9, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fmas_f32 v1, v1, v7, v9
v_div_fixup_f32 v2, v1, v2, v0
v_add_co_u32 v0, vcc_lo, s6, v3
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v4, vcc_lo
global_store_b32 v[0:1], v2, off
.LBB0_31:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z21bilateralFilterKernelPKfPfiiff
.amdhsa_group_segment_fixed_size 2704
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 22
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z21bilateralFilterKernelPKfPfiiff, .Lfunc_end0-_Z21bilateralFilterKernelPKfPfiiff
; -- End function
.section .AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1652
; NumSgprs: 18
; NumVgprs: 22
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 2704 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 2
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 22
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object ; @__hip_cuid_
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0 ; 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 2704
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z21bilateralFilterKernelPKfPfiiff
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z21bilateralFilterKernelPKfPfiiff.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 22
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
```
| 8,396 | 8,551 |
113,675 |
Convert the following CUDA host assembly code to AMD host assembly:
```cudaasm
.file "tmpxft_0006ac1b_00000000-6_cuda_code_003285.cudafe1.cpp"
.text
.globl _ZSt21ios_base_library_initv
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3639:
.cfi_startproc
endbr64
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
jmp __cudaUnregisterFatBinary@PLT
.cfi_endproc
.LFE3639:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "CUDA error: "
.LC1:
.string " ("
.LC2:
.string ")"
.text
.globl _Z14checkCudaError9cudaErrorPKc
.type _Z14checkCudaError9cudaErrorPKc, @function
_Z14checkCudaError9cudaErrorPKc:
.LFB3635:
.cfi_startproc
endbr64
testl %edi, %edi
je .L2
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
movq %rsi, %rbp
leaq .LC0(%rip), %rsi
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
movl %edi, %ebx
leaq _ZSt4cerr(%rip), %rdi
pushq %rax
.cfi_def_cfa_offset 32
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rbp, %rsi
movq %rax, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
leaq .LC1(%rip), %rsi
movq %rax, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movl %ebx, %edi
movq %rax, %rbp
call cudaGetErrorString@PLT
movq %rbp, %rdi
movq %rax, %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
leaq .LC2(%rip), %rsi
movq %rax, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $1, %edi
call exit@PLT
.L2:
.cfi_def_cfa_offset 8
.cfi_restore 3
.cfi_restore 6
ret
.cfi_endproc
.LFE3635:
.size _Z14checkCudaError9cudaErrorPKc, .-_Z14checkCudaError9cudaErrorPKc
.globl _Z48__device_stub__Z21bilateralFilterKernelPKfPfiiffPKfPfiiff
.type _Z48__device_stub__Z21bilateralFilterKernelPKfPfiiffPKfPfiiff, @function
_Z48__device_stub__Z21bilateralFilterKernelPKfPfiiffPKfPfiiff:
.LFB3661:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 24(%rsp)
leaq 56(%rsp), %rdi
movq %rsi, 16(%rsp)
leaq 68(%rsp), %rsi
movl %edx, 12(%rsp)
leaq 40(%rsp), %rdx
movl %ecx, 8(%rsp)
leaq 48(%rsp), %rcx
movss %xmm0, 4(%rsp)
movss %xmm1, (%rsp)
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movl $1, 64(%rsp)
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 12(%rsp), %rax
movq %rax, 120(%rsp)
leaq 8(%rsp), %rax
movq %rax, 128(%rsp)
leaq 4(%rsp), %rax
movq %rax, 136(%rsp)
movq %rsp, %rax
movq %rax, 144(%rsp)
movabsq $4294967297, %rax
movq %rax, 56(%rsp)
movq %rax, 68(%rsp)
movl $1, 76(%rsp)
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
jne .L8
pushq 48(%rsp)
.cfi_def_cfa_offset 184
leaq _Z21bilateralFilterKernelPKfPfiiff(%rip), %rdi
pushq 48(%rsp)
.cfi_def_cfa_offset 192
movq 84(%rsp), %rcx
movl 92(%rsp), %r8d
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
leaq 120(%rsp), %r9
call cudaLaunchKernel@PLT
popq %rax
.cfi_def_cfa_offset 184
popq %rdx
.cfi_def_cfa_offset 176
.L8:
movq 152(%rsp), %rax
subq %fs:40, %rax
je .L10
call __stack_chk_fail@PLT
.L10:
addq $168, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3661:
.size _Z48__device_stub__Z21bilateralFilterKernelPKfPfiiffPKfPfiiff, .-_Z48__device_stub__Z21bilateralFilterKernelPKfPfiiffPKfPfiiff
.globl _Z21bilateralFilterKernelPKfPfiiff
.type _Z21bilateralFilterKernelPKfPfiiff, @function
_Z21bilateralFilterKernelPKfPfiiff:
.LFB3662:
.cfi_startproc
endbr64
jmp _Z48__device_stub__Z21bilateralFilterKernelPKfPfiiffPKfPfiiff
.cfi_endproc
.LFE3662:
.size _Z21bilateralFilterKernelPKfPfiiff, .-_Z21bilateralFilterKernelPKfPfiiff
.section .rodata.str1.1
.LC4:
.string "Failed to allocate device input"
.LC5:
.string "Failed to allocate device output"
.LC6:
.string "Failed to copy input data to device"
.LC9:
.string "Kernel launch failed"
.LC10:
.string "Device synchronize failed"
.LC11:
.string "Failed to copy output data to host"
.LC12:
.string " "
.section .text.startup,"ax",@progbits
.globl main
.type main, @function
main:
.LFB3636:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
movl $4194304, %edi
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
xorl %r12d, %r12d
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $56, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
call _Znam@PLT
movl $4194304, %edi
movq %rax, %rbp
call _Znam@PLT
movq %rax, %rbx
.L14:
call rand@PLT
cvtsi2ssl %eax, %xmm0
mulss .LC3(%rip), %xmm0
movss %xmm0, 0(%rbp,%r12,4)
incq %r12
cmpq $1048576, %r12
jne .L14
movq %rsp, %rdi
movl $4194304, %esi
call cudaMalloc@PLT
leaq .LC4(%rip), %rsi
movl %eax, %edi
call _Z14checkCudaError9cudaErrorPKc
leaq 8(%rsp), %rdi
movl $4194304, %esi
call cudaMalloc@PLT
leaq .LC5(%rip), %rsi
movl %eax, %edi
call _Z14checkCudaError9cudaErrorPKc
movq (%rsp), %rdi
movl $1, %ecx
movq %rbp, %rsi
movl $4194304, %edx
call cudaMemcpy@PLT
leaq .LC6(%rip), %rsi
movl %eax, %edi
call _Z14checkCudaError9cudaErrorPKc
xorl %r9d, %r9d
xorl %r8d, %r8d
movl $1, %ecx
movabsq $68719476752, %rdx
movl $1, %esi
movabsq $274877907008, %rdi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L15
movq 8(%rsp), %rsi
movq (%rsp), %rdi
movl $1024, %ecx
movl $1024, %edx
movss .LC7(%rip), %xmm1
movss .LC8(%rip), %xmm0
call _Z48__device_stub__Z21bilateralFilterKernelPKfPfiiffPKfPfiiff
.L15:
call cudaGetLastError@PLT
leaq .LC9(%rip), %rsi
xorl %r12d, %r12d
leaq _ZSt4cout(%rip), %r13
movl %eax, %edi
call _Z14checkCudaError9cudaErrorPKc
call cudaDeviceSynchronize@PLT
leaq .LC10(%rip), %rsi
movl %eax, %edi
call _Z14checkCudaError9cudaErrorPKc
movq 8(%rsp), %rsi
movl $2, %ecx
movq %rbx, %rdi
movl $4194304, %edx
call cudaMemcpy@PLT
leaq .LC11(%rip), %rsi
movl %eax, %edi
call _Z14checkCudaError9cudaErrorPKc
.L16:
movq %r13, %rdi
cvtss2sd (%rbx,%r12,4), %xmm0
incq %r12
call _ZNSo9_M_insertIdEERSoT_@PLT
leaq .LC12(%rip), %rsi
movq %rax, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
cmpq $10, %r12
jne .L16
movq %r13, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq %rbp, %rdi
call _ZdaPv@PLT
movq %rbx, %rdi
call _ZdaPv@PLT
movq (%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
je .L17
call __stack_chk_fail@PLT
.L17:
addq $56, %rsp
.cfi_def_cfa_offset 40
xorl %eax, %eax
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3636:
.size main, .-main
.section .rodata.str1.1
.LC13:
.string "_Z21bilateralFilterKernelPKfPfiiff"
.section .text.startup
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3664:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
pushq $0
.cfi_def_cfa_offset 24
xorl %r9d, %r9d
orl $-1, %r8d
pushq $0
.cfi_def_cfa_offset 32
leaq .LC13(%rip), %rdx
movq %rax, %rdi
leaq _Z21bilateralFilterKernelPKfPfiiff(%rip), %rsi
pushq $0
.cfi_def_cfa_offset 40
movq %rdx, %rcx
pushq $0
.cfi_def_cfa_offset 48
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFunction@PLT
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
addq $32, %rsp
.cfi_def_cfa_offset 16
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
popq %rdx
.cfi_def_cfa_offset 8
jmp atexit@PLT
.cfi_endproc
.LFE3664:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC3:
.long 805306368
.align 4
.LC7:
.long 1036831949
.align 4
.LC8:
.long 1065353216
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
```
|
```amdasm
.text
.file "cuda_code_003285.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z36__device_stub__bilateralFilterKernelPKfPfiiff # -- Begin function _Z36__device_stub__bilateralFilterKernelPKfPfiiff
.type _Z36__device_stub__bilateralFilterKernelPKfPfiiff,@function
_Z36__device_stub__bilateralFilterKernelPKfPfiiff: # @_Z36__device_stub__bilateralFilterKernelPKfPfiiff
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $128, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 40(%rsp), %rax
movq %rdi, (%rax)
leaq 32(%rsp), %rdi
movq %rsi, (%rdi)
leaq 12(%rsp), %rsi
movl %edx, (%rsi)
leaq 8(%rsp), %rdx
movl %ecx, (%rdx)
leaq 4(%rsp), %rcx
movss %xmm0, (%rcx)
movq %rsp, %r8
movss %xmm1, (%r8)
leaq 80(%rsp), %rbx
movq %rax, (%rbx)
movq %rdi, 8(%rbx)
movq %rsi, 16(%rbx)
movq %rdx, 24(%rbx)
movq %rcx, 32(%rbx)
movq %r8, 40(%rbx)
leaq 64(%rsp), %r14
leaq 48(%rsp), %r15
leaq 24(%rsp), %r12
leaq 16(%rsp), %r13
movq %r14, %rdi
movq %r15, %rsi
movq %r12, %rdx
movq %r13, %rcx
callq __hipPopCallConfiguration
movq (%r14), %rsi
movl 8(%r14), %edx
movq (%r15), %rcx
movl 8(%r15), %r8d
movl $_Z21bilateralFilterKernelPKfPfiiff, %edi
movq %rbx, %r9
pushq (%r13)
.cfi_adjust_cfa_offset 8
pushq (%r12)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $144, %rsp
.cfi_adjust_cfa_offset -144
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z36__device_stub__bilateralFilterKernelPKfPfiiff, .Lfunc_end0-_Z36__device_stub__bilateralFilterKernelPKfPfiiff
.cfi_endproc
# -- End function
.globl _Z14checkCudaError10hipError_tPKc # -- Begin function _Z14checkCudaError10hipError_tPKc
.type _Z14checkCudaError10hipError_tPKc,@function
_Z14checkCudaError10hipError_tPKc: # @_Z14checkCudaError10hipError_tPKc
.cfi_startproc
# %bb.0:
testl %edi, %edi
jne .LBB1_2
# %bb.1:
retq
.LBB1_2:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
pushq %rax
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movq %rsi, %r14
movl %edi, %ebx
movl $_ZSt4cerr, %edi
movl $.L.str, %esi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movq %rax, %rdi
movq %r14, %rsi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movl $.L.str.1, %esi
movq %rax, %rdi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movq %rax, %r14
movl %ebx, %edi
callq hipGetErrorString
movq %r14, %rdi
movq %rax, %rsi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movl $.L.str.2, %esi
movq %rax, %rdi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movq %rax, %rdi
callq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_
movl $1, %edi
callq exit
.Lfunc_end1:
.size _Z14checkCudaError10hipError_tPKc, .Lfunc_end1-_Z14checkCudaError10hipError_tPKc
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI2_0:
.long 0x30000000 # float 4.65661287E-10
.LCPI2_1:
.long 0x3f800000 # float 1
.LCPI2_2:
.long 0x3dcccccd # float 0.100000001
.text
.globl main
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $16, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $4194304, %edi # imm = 0x400000
callq _Znam
movq %rax, %rbx
movl $4194304, %edi # imm = 0x400000
callq _Znam
movq %rax, %r14
xorl %r15d, %r15d
.LBB2_1: # =>This Inner Loop Header: Depth=1
callq rand
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
mulss .LCPI2_0(%rip), %xmm0
movss %xmm0, (%rbx,%r15,4)
incq %r15
cmpq $1048576, %r15 # imm = 0x100000
jne .LBB2_1
# %bb.2:
leaq 8(%rsp), %r15
movl $4194304, %esi # imm = 0x400000
movq %r15, %rdi
callq hipMalloc
movl $.L.str.3, %esi
movl %eax, %edi
callq _Z14checkCudaError10hipError_tPKc
movq %rsp, %rdi
movl $4194304, %esi # imm = 0x400000
callq hipMalloc
movl $.L.str.4, %esi
movl %eax, %edi
callq _Z14checkCudaError10hipError_tPKc
movq (%r15), %rdi
movl $4194304, %edx # imm = 0x400000
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movl $.L.str.5, %esi
movl %eax, %edi
callq _Z14checkCudaError10hipError_tPKc
movabsq $274877907008, %rdi # imm = 0x4000000040
movabsq $68719476752, %rdx # imm = 0x1000000010
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_4
# %bb.3:
movq 8(%rsp), %rdi
movq (%rsp), %rsi
movss .LCPI2_1(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero
movss .LCPI2_2(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero
movl $1024, %edx # imm = 0x400
movl $1024, %ecx # imm = 0x400
callq _Z36__device_stub__bilateralFilterKernelPKfPfiiff
.LBB2_4:
callq hipGetLastError
movl $.L.str.6, %esi
movl %eax, %edi
callq _Z14checkCudaError10hipError_tPKc
callq hipDeviceSynchronize
movl $.L.str.7, %esi
movl %eax, %edi
callq _Z14checkCudaError10hipError_tPKc
movq (%rsp), %rsi
movl $4194304, %edx # imm = 0x400000
movq %r14, %rdi
movl $2, %ecx
callq hipMemcpy
movl $.L.str.8, %esi
movl %eax, %edi
callq _Z14checkCudaError10hipError_tPKc
xorl %r15d, %r15d
.LBB2_5: # =>This Inner Loop Header: Depth=1
xorps %xmm0, %xmm0
cvtss2sd (%r14,%r15,4), %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movl $.L.str.9, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
incq %r15
cmpq $10, %r15
jne .LBB2_5
# %bb.6:
movq _ZSt4cout(%rip), %rax
movl $_ZSt4cout, %ecx
movq -24(%rax), %rdi
addq %rcx, %rdi
movl $10, %esi
callq _ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq %rbx, %rdi
callq _ZdaPv
movq %r14, %rdi
callq _ZdaPv
movq 8(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $16, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, %rdi
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z21bilateralFilterKernelPKfPfiiff, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z21bilateralFilterKernelPKfPfiiff,@object # @_Z21bilateralFilterKernelPKfPfiiff
.section .rodata,"a",@progbits
.globl _Z21bilateralFilterKernelPKfPfiiff
.p2align 3, 0x0
_Z21bilateralFilterKernelPKfPfiiff:
.quad _Z36__device_stub__bilateralFilterKernelPKfPfiiff
.size _Z21bilateralFilterKernelPKfPfiiff, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "CUDA error: "
.size .L.str, 13
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz " ("
.size .L.str.1, 3
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz ")"
.size .L.str.2, 2
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Failed to allocate device input"
.size .L.str.3, 32
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Failed to allocate device output"
.size .L.str.4, 33
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "Failed to copy input data to device"
.size .L.str.5, 36
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "Kernel launch failed"
.size .L.str.6, 21
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "Device synchronize failed"
.size .L.str.7, 26
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "Failed to copy output data to host"
.size .L.str.8, 35
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz " "
.size .L.str.9, 2
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z21bilateralFilterKernelPKfPfiiff"
.size .L__unnamed_1, 35
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z36__device_stub__bilateralFilterKernelPKfPfiiff
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z21bilateralFilterKernelPKfPfiiff
.addrsig_sym _ZSt4cerr
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
```
| 4,282 | 5,143 |
113,676 |
Convert the following CUDA device assembly code to AMD device assembly:
```cudaasm
code for sm_80
Function : _Z18segmentImageKernelPhS_iih
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ;
S2R R3, SR_CTAID.Y ;
S2R R2, SR_TID.Y ;
S2R R0, SR_CTAID.X ;
S2R R5, SR_TID.X ;
IMAD R3, R3, c[0x0][0x4], R2 ;
ISETP.GE.AND P0, PT, R3, c[0x0][0x174], PT ;
IMAD R0, R0, c[0x0][0x0], R5 ;
ISETP.GE.OR P0, PT, R0, c[0x0][0x170], P0 ;
@P0 EXIT ;
IMAD R0, R3, c[0x0][0x170], R0 ;
ULDC.64 UR4, c[0x0][0x118] ;
SHF.R.S32.HI R5, RZ, 0x1f, R0 ;
IADD3 R2, P0, R0, c[0x0][0x160], RZ ;
IADD3.X R3, R5, c[0x0][0x164], RZ, P0, !PT ;
LDG.E.U8 R2, [R2.64] ;
ULDC.U8 UR6, c[0x0][0x178] ;
IADD3 R4, P1, R0, c[0x0][0x168], RZ ;
IADD3.X R5, R5, c[0x0][0x16c], RZ, P1, !PT ;
ISETP.GT.U32.AND P0, PT, R2, UR6, PT ;
SEL R7, RZ, 0xffff, !P0 ;
STG.E.U8 [R4.64], R7 ;
EXIT ;
BRA 0x170;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
```
|
```amdasm
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z18segmentImageKernelPhS_iih ; -- Begin function _Z18segmentImageKernelPhS_iih
.globl _Z18segmentImageKernelPhS_iih
.p2align 8
.type _Z18segmentImageKernelPhS_iih,@function
_Z18segmentImageKernelPhS_iih: ; @_Z18segmentImageKernelPhS_iih
; %bb.0:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b128 s[4:7], s[0:1], 0x10
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_lshr_b32 s3, s2, 16
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[0:1], null, s14, s2, v[2:3]
v_mad_u64_u32 v[1:2], null, s15, s3, v[3:4]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_gt_i32_e32 vcc_lo, s4, v0
v_cmp_gt_i32_e64 s2, s5, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, vcc_lo, s2
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_2
; %bb.1:
s_load_b128 s[0:3], s[0:1], 0x0
v_mad_u64_u32 v[2:3], null, v1, s4, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v3, 31, v2
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v2
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v3, vcc_lo
global_load_u8 v0, v[0:1], off
v_and_b32_e64 v1, 0xff, s6
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_cmp_gt_u16_e32 vcc_lo, v0, v1
v_cndmask_b32_e64 v4, 0, -1, vcc_lo
v_add_co_u32 v0, vcc_lo, s2, v2
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v3, vcc_lo
global_store_b8 v[0:1], v4, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z18segmentImageKernelPhS_iih
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z18segmentImageKernelPhS_iih, .Lfunc_end0-_Z18segmentImageKernelPhS_iih
; -- End function
.section .AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 216
; NumSgprs: 18
; NumVgprs: 5
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 5
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object ; @__hip_cuid_
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0 ; 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 1
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z18segmentImageKernelPhS_iih
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z18segmentImageKernelPhS_iih.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
```
| 548 | 2,767 |
113,677 |
Convert the following CUDA host assembly code to AMD host assembly:
```cudaasm
.file "tmpxft_000c40c5_00000000-6_cuda_code_004148.cudafe1.cpp"
.text
.globl _ZSt21ios_base_library_initv
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB4002:
.cfi_startproc
endbr64
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
jmp __cudaUnregisterFatBinary@PLT
.cfi_endproc
.LFE4002:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "CUDA error: "
.LC1:
.string " ("
.LC2:
.string ")"
.text
.globl _Z14checkCudaError9cudaErrorPKc
.type _Z14checkCudaError9cudaErrorPKc, @function
_Z14checkCudaError9cudaErrorPKc:
.LFB3998:
.cfi_startproc
endbr64
testl %edi, %edi
je .L2
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
movq %rsi, %rbp
leaq .LC0(%rip), %rsi
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
movl %edi, %ebx
leaq _ZSt4cerr(%rip), %rdi
pushq %rax
.cfi_def_cfa_offset 32
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rbp, %rsi
movq %rax, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
leaq .LC1(%rip), %rsi
movq %rax, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movl %ebx, %edi
movq %rax, %rbp
call cudaGetErrorString@PLT
movq %rbp, %rdi
movq %rax, %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
leaq .LC2(%rip), %rsi
movq %rax, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $1, %edi
call exit@PLT
.L2:
.cfi_def_cfa_offset 8
.cfi_restore 3
.cfi_restore 6
ret
.cfi_endproc
.LFE3998:
.size _Z14checkCudaError9cudaErrorPKc, .-_Z14checkCudaError9cudaErrorPKc
.globl _Z43__device_stub__Z18segmentImageKernelPhS_iihPhS_iih
.type _Z43__device_stub__Z18segmentImageKernelPhS_iihPhS_iih, @function
_Z43__device_stub__Z18segmentImageKernelPhS_iihPhS_iih:
.LFB4024:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
leaq 48(%rsp), %rdi
movq %rsi, 16(%rsp)
leaq 60(%rsp), %rsi
movl %edx, 12(%rsp)
leaq 32(%rsp), %rdx
movl %ecx, 8(%rsp)
leaq 40(%rsp), %rcx
movb %r8b, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movl $1, 56(%rsp)
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 4(%rsp), %rax
movq %rax, 128(%rsp)
movabsq $4294967297, %rax
movq %rax, 48(%rsp)
movq %rax, 60(%rsp)
movl $1, 68(%rsp)
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
jne .L8
pushq 40(%rsp)
.cfi_def_cfa_offset 168
leaq _Z18segmentImageKernelPhS_iih(%rip), %rdi
pushq 40(%rsp)
.cfi_def_cfa_offset 176
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq 112(%rsp), %r9
call cudaLaunchKernel@PLT
popq %rax
.cfi_def_cfa_offset 168
popq %rdx
.cfi_def_cfa_offset 160
.L8:
movq 136(%rsp), %rax
subq %fs:40, %rax
je .L10
call __stack_chk_fail@PLT
.L10:
addq $152, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4024:
.size _Z43__device_stub__Z18segmentImageKernelPhS_iihPhS_iih, .-_Z43__device_stub__Z18segmentImageKernelPhS_iihPhS_iih
.globl _Z18segmentImageKernelPhS_iih
.type _Z18segmentImageKernelPhS_iih, @function
_Z18segmentImageKernelPhS_iih:
.LFB4025:
.cfi_startproc
endbr64
movzbl %r8b, %r8d
jmp _Z43__device_stub__Z18segmentImageKernelPhS_iihPhS_iih
.cfi_endproc
.LFE4025:
.size _Z18segmentImageKernelPhS_iih, .-_Z18segmentImageKernelPhS_iih
.section .rodata.str1.1
.LC3:
.string "_Z18segmentImageKernelPhS_iih"
.section .text.startup,"ax",@progbits
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB4027:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
pushq $0
.cfi_def_cfa_offset 24
xorl %r9d, %r9d
orl $-1, %r8d
pushq $0
.cfi_def_cfa_offset 32
leaq .LC3(%rip), %rdx
movq %rax, %rdi
leaq _Z18segmentImageKernelPhS_iih(%rip), %rsi
pushq $0
.cfi_def_cfa_offset 40
movq %rdx, %rcx
pushq $0
.cfi_def_cfa_offset 48
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFunction@PLT
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
addq $32, %rsp
.cfi_def_cfa_offset 16
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
popq %rdx
.cfi_def_cfa_offset 8
jmp atexit@PLT
.cfi_endproc
.LFE4027:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .rodata._ZNSt6vectorIhSaIhEEC2EmRKS0_.str1.1,"aMS",@progbits,1
.LC4:
.string "cannot create std::vector larger than max_size()"
.section .text._ZNSt6vectorIhSaIhEEC2EmRKS0_,"axG",@progbits,_ZNSt6vectorIhSaIhEEC5EmRKS0_,comdat
.align 2
.weak _ZNSt6vectorIhSaIhEEC2EmRKS0_
.type _ZNSt6vectorIhSaIhEEC2EmRKS0_, @function
_ZNSt6vectorIhSaIhEEC2EmRKS0_:
.LFB4337:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
pushq %rdx
.cfi_def_cfa_offset 32
testq %rsi, %rsi
jns .L16
leaq .LC4(%rip), %rdi
call _ZSt20__throw_length_errorPKc@PLT
.L16:
movq $0, (%rdi)
movq %rdi, %rbp
movq %rsi, %rbx
movl $0, %edx
movq $0, 8(%rdi)
movq $0, 16(%rdi)
je .L17
movq %rsi, %rdi
call _Znwm@PLT
movq %rax, %rdx
.L17:
leaq (%rdx,%rbx), %rsi
movq %rdx, 0(%rbp)
movq %rdx, 8(%rbp)
movq %rsi, 16(%rbp)
testq %rbx, %rbx
je .L18
movb $0, (%rdx)
incq %rdx
cmpq $1, %rbx
je .L18
movq %rdx, %rdi
leaq -1(%rbx), %rcx
xorl %eax, %eax
movq %rsi, %rdx
rep stosb
.L18:
movq %rdx, 8(%rbp)
popq %rax
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4337:
.size _ZNSt6vectorIhSaIhEEC2EmRKS0_, .-_ZNSt6vectorIhSaIhEEC2EmRKS0_
.weak _ZNSt6vectorIhSaIhEEC1EmRKS0_
.set _ZNSt6vectorIhSaIhEEC1EmRKS0_,_ZNSt6vectorIhSaIhEEC2EmRKS0_
.section .text._ZNSt6vectorIhSaIhEED2Ev,"axG",@progbits,_ZNSt6vectorIhSaIhEED5Ev,comdat
.align 2
.weak _ZNSt6vectorIhSaIhEED2Ev
.type _ZNSt6vectorIhSaIhEED2Ev, @function
_ZNSt6vectorIhSaIhEED2Ev:
.LFB4340:
.cfi_startproc
endbr64
movq (%rdi), %rax
testq %rax, %rax
je .L28
movq 16(%rdi), %rsi
movq %rax, %rdi
subq %rax, %rsi
jmp _ZdlPvm@PLT
.L28:
ret
.cfi_endproc
.LFE4340:
.size _ZNSt6vectorIhSaIhEED2Ev, .-_ZNSt6vectorIhSaIhEED2Ev
.weak _ZNSt6vectorIhSaIhEED1Ev
.set _ZNSt6vectorIhSaIhEED1Ev,_ZNSt6vectorIhSaIhEED2Ev
.section .rodata.str1.1
.LC5:
.string "Failed to allocate d_input"
.LC6:
.string "Failed to allocate d_output"
.LC7:
.string "Failed to copy input data to device"
.LC8:
.string "Kernel launch failed"
.LC9:
.string "Failed to synchronize device"
.LC10:
.string "Failed to copy output data to host"
.LC11:
.string "Failed to free d_input"
.LC12:
.string "Failed to free d_output"
.section .text.startup
.globl main
.type main, @function
main:
.LFB3999:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA3999
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
movl $2073600, %esi
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $96, %rsp
.cfi_def_cfa_offset 144
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 64(%rsp), %rbp
leaq 40(%rsp), %r12
movq %rbp, %rdx
movq %r12, %rdi
.LEHB0:
call _ZNSt6vectorIhSaIhEEC1EmRKS0_
.LEHE0:
leaq 28(%rsp), %rdx
movl $2073600, %esi
movq %rbp, %rdi
.LEHB1:
call _ZNSt6vectorIhSaIhEEC1EmRKS0_
.LEHE1:
xorl %ebx, %ebx
movl $256, %r14d
.L31:
call rand@PLT
movq 40(%rsp), %r13
cltd
idivl %r14d
movb %dl, 0(%r13,%rbx)
incq %rbx
cmpq $2073600, %rbx
jne .L31
movq %rsp, %rdi
movl $2073600, %esi
.LEHB2:
call cudaMalloc@PLT
movl %eax, %edi
leaq .LC5(%rip), %rsi
call _Z14checkCudaError9cudaErrorPKc
leaq 8(%rsp), %rdi
movl $2073600, %esi
call cudaMalloc@PLT
movl %eax, %edi
leaq .LC6(%rip), %rsi
call _Z14checkCudaError9cudaErrorPKc
movq (%rsp), %rdi
movl $1, %ecx
movl $2073600, %edx
movq %r13, %rsi
call cudaMemcpy@PLT
movl %eax, %edi
leaq .LC7(%rip), %rsi
call _Z14checkCudaError9cudaErrorPKc
xorl %r9d, %r9d
xorl %r8d, %r8d
movl $1, %ecx
movl $1, %esi
movabsq $292057776248, %rdi
movl $1, 36(%rsp)
movabsq $68719476752, %rdx
movq %rdi, 28(%rsp)
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L32
.L34:
call cudaGetLastError@PLT
movl %eax, %edi
leaq .LC8(%rip), %rsi
call _Z14checkCudaError9cudaErrorPKc
jmp .L45
.L32:
movq 8(%rsp), %rsi
movq (%rsp), %rdi
movl $128, %r8d
movl $1080, %ecx
movl $1920, %edx
call _Z43__device_stub__Z18segmentImageKernelPhS_iihPhS_iih
jmp .L34
.L45:
call cudaDeviceSynchronize@PLT
movl %eax, %edi
leaq .LC9(%rip), %rsi
call _Z14checkCudaError9cudaErrorPKc
movq 8(%rsp), %rsi
movq 64(%rsp), %rdi
movl $2, %ecx
movl $2073600, %edx
call cudaMemcpy@PLT
movl %eax, %edi
leaq .LC10(%rip), %rsi
call _Z14checkCudaError9cudaErrorPKc
movq (%rsp), %rdi
call cudaFree@PLT
movl %eax, %edi
leaq .LC11(%rip), %rsi
call _Z14checkCudaError9cudaErrorPKc
movq 8(%rsp), %rdi
call cudaFree@PLT
movl %eax, %edi
leaq .LC12(%rip), %rsi
call _Z14checkCudaError9cudaErrorPKc
.LEHE2:
movq %rbp, %rdi
call _ZNSt6vectorIhSaIhEED1Ev
movq %r12, %rdi
call _ZNSt6vectorIhSaIhEED1Ev
movq 88(%rsp), %rax
subq %fs:40, %rax
je .L38
jmp .L43
.L40:
endbr64
movq %rax, %rbx
.L35:
movq %rbp, %rdi
call _ZNSt6vectorIhSaIhEED1Ev
jmp .L36
.L39:
endbr64
movq %rax, %rbx
.L36:
movq %r12, %rdi
call _ZNSt6vectorIhSaIhEED1Ev
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L43
movq %rbx, %rdi
.LEHB3:
call _Unwind_Resume@PLT
.LEHE3:
.L43:
call __stack_chk_fail@PLT
.L38:
addq $96, %rsp
.cfi_def_cfa_offset 48
xorl %eax, %eax
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3999:
.globl __gxx_personality_v0
.section .gcc_except_table,"a",@progbits
.LLSDA3999:
.byte 0xff
.byte 0xff
.byte 0x1
.uleb128 .LLSDACSE3999-.LLSDACSB3999
.LLSDACSB3999:
.uleb128 .LEHB0-.LFB3999
.uleb128 .LEHE0-.LEHB0
.uleb128 0
.uleb128 0
.uleb128 .LEHB1-.LFB3999
.uleb128 .LEHE1-.LEHB1
.uleb128 .L39-.LFB3999
.uleb128 0
.uleb128 .LEHB2-.LFB3999
.uleb128 .LEHE2-.LEHB2
.uleb128 .L40-.LFB3999
.uleb128 0
.uleb128 .LEHB3-.LFB3999
.uleb128 .LEHE3-.LEHB3
.uleb128 0
.uleb128 0
.LLSDACSE3999:
.section .text.startup
.size main, .-main
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.hidden DW.ref.__gxx_personality_v0
.weak DW.ref.__gxx_personality_v0
.section .data.rel.local.DW.ref.__gxx_personality_v0,"awG",@progbits,DW.ref.__gxx_personality_v0,comdat
.align 8
.type DW.ref.__gxx_personality_v0, @object
.size DW.ref.__gxx_personality_v0, 8
DW.ref.__gxx_personality_v0:
.quad __gxx_personality_v0
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
```
|
```amdasm
.text
.file "cuda_code_004148.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z33__device_stub__segmentImageKernelPhS_iih # -- Begin function _Z33__device_stub__segmentImageKernelPhS_iih
.type _Z33__device_stub__segmentImageKernelPhS_iih,@function
_Z33__device_stub__segmentImageKernelPhS_iih: # @_Z33__device_stub__segmentImageKernelPhS_iih
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $128, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 40(%rsp), %rax
movq %rdi, (%rax)
leaq 32(%rsp), %rdi
movq %rsi, (%rdi)
leaq 12(%rsp), %rsi
movl %edx, (%rsi)
leaq 8(%rsp), %rdx
movl %ecx, (%rdx)
leaq 7(%rsp), %rcx
movb %r8b, (%rcx)
leaq 80(%rsp), %rbx
movq %rax, (%rbx)
movq %rdi, 8(%rbx)
movq %rsi, 16(%rbx)
movq %rdx, 24(%rbx)
movq %rcx, 32(%rbx)
leaq 64(%rsp), %r14
leaq 48(%rsp), %r15
leaq 24(%rsp), %r12
leaq 16(%rsp), %r13
movq %r14, %rdi
movq %r15, %rsi
movq %r12, %rdx
movq %r13, %rcx
callq __hipPopCallConfiguration
movq (%r14), %rsi
movl 8(%r14), %edx
movq (%r15), %rcx
movl 8(%r15), %r8d
movl $_Z18segmentImageKernelPhS_iih, %edi
movq %rbx, %r9
pushq (%r13)
.cfi_adjust_cfa_offset 8
pushq (%r12)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $144, %rsp
.cfi_adjust_cfa_offset -144
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z33__device_stub__segmentImageKernelPhS_iih, .Lfunc_end0-_Z33__device_stub__segmentImageKernelPhS_iih
.cfi_endproc
# -- End function
.globl _Z14checkCudaError10hipError_tPKc # -- Begin function _Z14checkCudaError10hipError_tPKc
.type _Z14checkCudaError10hipError_tPKc,@function
_Z14checkCudaError10hipError_tPKc: # @_Z14checkCudaError10hipError_tPKc
.cfi_startproc
# %bb.0:
testl %edi, %edi
jne .LBB1_2
# %bb.1:
retq
.LBB1_2:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
pushq %rax
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movq %rsi, %r14
movl %edi, %ebx
movl $_ZSt4cerr, %edi
movl $.L.str, %esi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movq %rax, %rdi
movq %r14, %rsi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movl $.L.str.1, %esi
movq %rax, %rdi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movq %rax, %r14
movl %ebx, %edi
callq hipGetErrorString
movq %r14, %rdi
movq %rax, %rsi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movl $.L.str.2, %esi
movq %rax, %rdi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movq %rax, %rdi
callq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_
movl $1, %edi
callq exit
.Lfunc_end1:
.size _Z14checkCudaError10hipError_tPKc, .Lfunc_end1-_Z14checkCudaError10hipError_tPKc
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.type main,@function
main: # @main
.Lfunc_begin0:
.cfi_startproc
.cfi_personality 3, __gxx_personality_v0
.cfi_lsda 3, .Lexception0
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $16, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $2073600, %edi # imm = 0x1FA400
callq _Znwm
movq %rax, %rbx
movl $2073600, %edx # imm = 0x1FA400
movq %rax, %rdi
xorl %esi, %esi
callq memset@PLT
.Ltmp0:
movl $2073600, %edi # imm = 0x1FA400
callq _Znwm
.Ltmp1:
# %bb.1:
movq %rax, %r14
xorl %r15d, %r15d
movl $2073600, %edx # imm = 0x1FA400
movq %rax, %rdi
xorl %esi, %esi
callq memset@PLT
.LBB2_2: # =>This Inner Loop Header: Depth=1
callq rand
movb %al, (%rbx,%r15)
incq %r15
cmpq $2073600, %r15 # imm = 0x1FA400
jne .LBB2_2
# %bb.3:
.Ltmp3:
leaq 8(%rsp), %rdi
movl $2073600, %esi # imm = 0x1FA400
callq hipMalloc
.Ltmp4:
# %bb.4: # %_ZL9hipMallocIhE10hipError_tPPT_m.exit
.Ltmp5:
movl $.L.str.3, %esi
movl %eax, %edi
callq _Z14checkCudaError10hipError_tPKc
.Ltmp6:
# %bb.5:
.Ltmp7:
movq %rsp, %rdi
movl $2073600, %esi # imm = 0x1FA400
callq hipMalloc
.Ltmp8:
# %bb.6: # %_ZL9hipMallocIhE10hipError_tPPT_m.exit19
.Ltmp9:
movl $.L.str.4, %esi
movl %eax, %edi
callq _Z14checkCudaError10hipError_tPKc
.Ltmp10:
# %bb.7:
movq 8(%rsp), %rdi
.Ltmp11:
movl $2073600, %edx # imm = 0x1FA400
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
.Ltmp12:
# %bb.8:
.Ltmp13:
movl $.L.str.5, %esi
movl %eax, %edi
callq _Z14checkCudaError10hipError_tPKc
.Ltmp14:
# %bb.9:
.Ltmp16:
movabsq $292057776248, %rdi # imm = 0x4400000078
movabsq $68719476752, %rdx # imm = 0x1000000010
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
.Ltmp17:
# %bb.10:
testl %eax, %eax
jne .LBB2_12
# %bb.11:
movq 8(%rsp), %rdi
movq (%rsp), %rsi
.Ltmp18:
movl $1920, %edx # imm = 0x780
movl $1080, %ecx # imm = 0x438
movl $128, %r8d
callq _Z33__device_stub__segmentImageKernelPhS_iih
.Ltmp19:
.LBB2_12:
.Ltmp20:
callq hipGetLastError
.Ltmp21:
# %bb.13:
.Ltmp22:
movl $.L.str.6, %esi
movl %eax, %edi
callq _Z14checkCudaError10hipError_tPKc
.Ltmp23:
# %bb.14:
.Ltmp24:
callq hipDeviceSynchronize
.Ltmp25:
# %bb.15:
.Ltmp26:
movl $.L.str.7, %esi
movl %eax, %edi
callq _Z14checkCudaError10hipError_tPKc
.Ltmp27:
# %bb.16:
movq (%rsp), %rsi
.Ltmp28:
movl $2073600, %edx # imm = 0x1FA400
movq %r14, %rdi
movl $2, %ecx
callq hipMemcpy
.Ltmp29:
# %bb.17:
.Ltmp30:
movl $.L.str.8, %esi
movl %eax, %edi
callq _Z14checkCudaError10hipError_tPKc
.Ltmp31:
# %bb.18:
movq 8(%rsp), %rdi
.Ltmp32:
callq hipFree
.Ltmp33:
# %bb.19:
.Ltmp34:
movl $.L.str.9, %esi
movl %eax, %edi
callq _Z14checkCudaError10hipError_tPKc
.Ltmp35:
# %bb.20:
movq (%rsp), %rdi
.Ltmp36:
callq hipFree
.Ltmp37:
# %bb.21:
.Ltmp38:
movl $.L.str.10, %esi
movl %eax, %edi
callq _Z14checkCudaError10hipError_tPKc
.Ltmp39:
# %bb.22: # %_ZNSt6vectorIhSaIhEED2Ev.exit21
movq %r14, %rdi
callq _ZdlPv
movq %rbx, %rdi
callq _ZdlPv
xorl %eax, %eax
addq $16, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB2_26:
.cfi_def_cfa_offset 48
.Ltmp2:
movq %rax, %r15
jmp .LBB2_25
.LBB2_23:
.Ltmp15:
jmp .LBB2_24
.LBB2_27:
.Ltmp40:
.LBB2_24: # %_ZNSt6vectorIhSaIhEED2Ev.exit23
movq %rax, %r15
movq %r14, %rdi
callq _ZdlPv
.LBB2_25: # %_ZNSt6vectorIhSaIhEED2Ev.exit25
movq %rbx, %rdi
callq _ZdlPv
movq %r15, %rdi
callq _Unwind_Resume@PLT
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
.section .gcc_except_table,"a",@progbits
.p2align 2, 0x0
GCC_except_table2:
.Lexception0:
.byte 255 # @LPStart Encoding = omit
.byte 255 # @TType Encoding = omit
.byte 1 # Call site Encoding = uleb128
.uleb128 .Lcst_end0-.Lcst_begin0
.Lcst_begin0:
.uleb128 .Lfunc_begin0-.Lfunc_begin0 # >> Call Site 1 <<
.uleb128 .Ltmp0-.Lfunc_begin0 # Call between .Lfunc_begin0 and .Ltmp0
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp0-.Lfunc_begin0 # >> Call Site 2 <<
.uleb128 .Ltmp1-.Ltmp0 # Call between .Ltmp0 and .Ltmp1
.uleb128 .Ltmp2-.Lfunc_begin0 # jumps to .Ltmp2
.byte 0 # On action: cleanup
.uleb128 .Ltmp1-.Lfunc_begin0 # >> Call Site 3 <<
.uleb128 .Ltmp3-.Ltmp1 # Call between .Ltmp1 and .Ltmp3
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp3-.Lfunc_begin0 # >> Call Site 4 <<
.uleb128 .Ltmp14-.Ltmp3 # Call between .Ltmp3 and .Ltmp14
.uleb128 .Ltmp15-.Lfunc_begin0 # jumps to .Ltmp15
.byte 0 # On action: cleanup
.uleb128 .Ltmp16-.Lfunc_begin0 # >> Call Site 5 <<
.uleb128 .Ltmp39-.Ltmp16 # Call between .Ltmp16 and .Ltmp39
.uleb128 .Ltmp40-.Lfunc_begin0 # jumps to .Ltmp40
.byte 0 # On action: cleanup
.uleb128 .Ltmp39-.Lfunc_begin0 # >> Call Site 6 <<
.uleb128 .Lfunc_end2-.Ltmp39 # Call between .Ltmp39 and .Lfunc_end2
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.Lcst_end0:
.p2align 2, 0x0
# -- End function
.text
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, %rdi
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z18segmentImageKernelPhS_iih, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z18segmentImageKernelPhS_iih,@object # @_Z18segmentImageKernelPhS_iih
.section .rodata,"a",@progbits
.globl _Z18segmentImageKernelPhS_iih
.p2align 3, 0x0
_Z18segmentImageKernelPhS_iih:
.quad _Z33__device_stub__segmentImageKernelPhS_iih
.size _Z18segmentImageKernelPhS_iih, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "CUDA error: "
.size .L.str, 13
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz " ("
.size .L.str.1, 3
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz ")"
.size .L.str.2, 2
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Failed to allocate d_input"
.size .L.str.3, 27
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Failed to allocate d_output"
.size .L.str.4, 28
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "Failed to copy input data to device"
.size .L.str.5, 36
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "Kernel launch failed"
.size .L.str.6, 21
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "Failed to synchronize device"
.size .L.str.7, 29
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "Failed to copy output data to host"
.size .L.str.8, 35
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "Failed to free d_input"
.size .L.str.9, 23
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "Failed to free d_output"
.size .L.str.10, 24
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z18segmentImageKernelPhS_iih"
.size .L__unnamed_1, 30
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z33__device_stub__segmentImageKernelPhS_iih
.addrsig_sym __gxx_personality_v0
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Unwind_Resume
.addrsig_sym _Z18segmentImageKernelPhS_iih
.addrsig_sym _ZSt4cerr
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
```
| 6,007 | 6,039 |
113,680 |
Convert the following CUDA device assembly code to AMD device assembly:
```cudaasm
code for sm_80
Function : _Z25fluidStructureInteractionPfS_S_f
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ;
S2R R0, SR_CTAID.X ;
HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ;
ULDC.64 UR4, c[0x0][0x118] ;
BSSY B0, 0xe0 ;
S2R R11, SR_TID.X ;
IMAD R0, R0, c[0x0][0x0], R11 ;
IMAD.WIDE R2, R0.reuse, R3, c[0x0][0x170] ;
ISETP.GT.AND P0, PT, R0, 0x7ff, PT ;
SHF.R.S32.HI R5, RZ, 0x1f, R0 ;
@P0 BRA 0xd0 ;
LDG.E R4, [R2.64] ;
STS [R11.X4], R4 ;
BSYNC B0 ;
BAR.SYNC.DEFER_BLOCKING 0x0 ;
@P0 EXIT ;
IMAD.SHL.U32 R4, R0.reuse, 0x4, RZ ;
SHF.L.U64.HI R5, R0, 0x2, R5 ;
LDS R0, [R11.X4] ;
IADD3 R6, P0, R4.reuse, c[0x0][0x168], RZ ;
IADD3 R4, P1, R4, c[0x0][0x160], RZ ;
IADD3.X R7, R5.reuse, c[0x0][0x16c], RZ, P0, !PT ;
IADD3.X R5, R5, c[0x0][0x164], RZ, P1, !PT ;
LDG.E R6, [R6.64] ;
LDG.E R8, [R4.64] ;
FMUL R0, R0, c[0x0][0x178] ;
FMUL R9, R0, c[0x0][0x178] ;
FFMA R9, R6, c[0x0][0x178], R9 ;
FADD R9, R9, R8 ;
STG.E [R4.64], R9 ;
STG.E [R2.64], RZ ;
EXIT ;
BRA 0x200;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
```
|
```amdasm
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z25fluidStructureInteractionPfS_S_f ; -- Begin function _Z25fluidStructureInteractionPfS_S_f
.globl _Z25fluidStructureInteractionPfS_S_f
.p2align 8
.type _Z25fluidStructureInteractionPfS_S_f,@function
_Z25fluidStructureInteractionPfS_S_f: ; @_Z25fluidStructureInteractionPfS_S_f
; %bb.0:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b64 s[4:5], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
v_lshlrev_b32_e32 v0, 2, v0
v_cmp_gt_i32_e32 vcc_lo, 0x800, v1
v_ashrrev_i32_e32 v2, 31, v1
s_and_saveexec_b32 s3, vcc_lo
s_cbranch_execz .LBB0_2
; %bb.1:
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[1:2]
v_add_co_u32 v3, s2, s4, v3
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v4, s2, s5, v4, s2
global_load_b32 v3, v[3:4], off
s_waitcnt vmcnt(0)
ds_store_b32 v0, v3
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s3
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_4
; %bb.3:
s_load_b128 s[8:11], s[0:1], 0x0
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_load_b32 s0, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v3, vcc_lo, s10, v1
v_add_co_ci_u32_e32 v4, vcc_lo, s11, v2, vcc_lo
v_add_co_u32 v5, vcc_lo, s8, v1
v_add_co_ci_u32_e32 v6, vcc_lo, s9, v2, vcc_lo
global_load_b32 v3, v[3:4], off
global_load_b32 v4, v[5:6], off
ds_load_b32 v0, v0
s_waitcnt lgkmcnt(0)
v_mul_f32_e32 v0, s0, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mul_f32_e32 v0, s0, v0
s_waitcnt vmcnt(1)
v_dual_fmac_f32 v0, s0, v3 :: v_dual_mov_b32 v3, 0
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_add_f32_e32 v4, v4, v0
v_add_co_u32 v0, vcc_lo, s4, v1
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v2, vcc_lo
global_store_b32 v[5:6], v4, off
global_store_b32 v[0:1], v3, off
.LBB0_4:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z25fluidStructureInteractionPfS_S_f
.amdhsa_group_segment_fixed_size 512
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z25fluidStructureInteractionPfS_S_f, .Lfunc_end0-_Z25fluidStructureInteractionPfS_S_f
; -- End function
.section .AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 308
; NumSgprs: 18
; NumVgprs: 7
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 512 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 7
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object ; @__hip_cuid_
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0 ; 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 512
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z25fluidStructureInteractionPfS_S_f
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z25fluidStructureInteractionPfS_S_f.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
```
| 698 | 2,999 |
113,681 |
Convert the following CUDA host assembly code to AMD host assembly:
```cudaasm
.file "tmpxft_0008d375_00000000-6_cuda_code_066648.cudafe1.cpp"
.text
.globl _ZSt21ios_base_library_initv
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3638:
.cfi_startproc
endbr64
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
jmp __cudaUnregisterFatBinary@PLT
.cfi_endproc
.LFE3638:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.align 2
.type _ZNSolsEPFRSoS_E.isra.0, @function
_ZNSolsEPFRSoS_E.isra.0:
.LFB4292:
.cfi_startproc
jmp *%rsi
.cfi_endproc
.LFE4292:
.size _ZNSolsEPFRSoS_E.isra.0, .-_ZNSolsEPFRSoS_E.isra.0
.globl _Z50__device_stub__Z25fluidStructureInteractionPfS_S_fPfS_S_f
.type _Z50__device_stub__Z25fluidStructureInteractionPfS_S_fPfS_S_f, @function
_Z50__device_stub__Z25fluidStructureInteractionPfS_S_fPfS_S_f:
.LFB3660:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
leaq 48(%rsp), %rcx
leaq 56(%rsp), %rdi
movq %rsi, 16(%rsp)
leaq 68(%rsp), %rsi
movq %rdx, 8(%rsp)
leaq 40(%rsp), %rdx
movss %xmm0, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movl $1, 64(%rsp)
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 4(%rsp), %rax
movq %rax, 128(%rsp)
movabsq $4294967297, %rax
movq %rax, 56(%rsp)
movq %rax, 68(%rsp)
movl $1, 76(%rsp)
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
jne .L3
pushq 48(%rsp)
.cfi_def_cfa_offset 168
leaq _Z25fluidStructureInteractionPfS_S_f(%rip), %rdi
pushq 48(%rsp)
.cfi_def_cfa_offset 176
movq 84(%rsp), %rcx
movl 92(%rsp), %r8d
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
leaq 120(%rsp), %r9
call cudaLaunchKernel@PLT
popq %rax
.cfi_def_cfa_offset 168
popq %rdx
.cfi_def_cfa_offset 160
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
je .L5
call __stack_chk_fail@PLT
.L5:
addq $152, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3660:
.size _Z50__device_stub__Z25fluidStructureInteractionPfS_S_fPfS_S_f, .-_Z50__device_stub__Z25fluidStructureInteractionPfS_S_fPfS_S_f
.globl _Z25fluidStructureInteractionPfS_S_f
.type _Z25fluidStructureInteractionPfS_S_f, @function
_Z25fluidStructureInteractionPfS_S_f:
.LFB3661:
.cfi_startproc
endbr64
jmp _Z50__device_stub__Z25fluidStructureInteractionPfS_S_fPfS_S_f
.cfi_endproc
.LFE3661:
.size _Z25fluidStructureInteractionPfS_S_f, .-_Z25fluidStructureInteractionPfS_S_f
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "Error allocating device memory for positions: "
.LC2:
.string "Error allocating device memory for velocities: "
.LC3:
.string "Error allocating device memory for forces: "
.LC4:
.string "Error copying positions to device: "
.LC5:
.string "Error copying velocities to device: "
.LC6:
.string "Error copying forces to device: "
.LC8:
.string "Error launching kernel: "
.LC9:
.string "Error copying positions back to host: "
.LC10:
.string "Simulation completed successfully."
.section .text.startup,"ax",@progbits
.globl main
.type main, @function
main:
.LFB3635:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
movl $8192, %edi
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $72, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
call _Znam@PLT
movl $8192, %edi
movq %rax, %rbp
call _Znam@PLT
movl $8192, %edi
movq %rax, %r12
call _Znam@PLT
movss .LC0(%rip), %xmm0
xorl %ecx, %ecx
movq %rax, %rbx
.L10:
cvtsi2ssl %ecx, %xmm1
movss %xmm0, (%r12,%rcx,4)
movss %xmm1, 0(%rbp,%rcx,4)
incq %rcx
cmpq $2048, %rcx
jne .L10
xorl %eax, %eax
movq %rbx, %rdi
movl $8192, %esi
rep stosl
leaq 8(%rsp), %rdi
call cudaMalloc@PLT
leaq .LC1(%rip), %rsi
movl %eax, %r13d
testl %eax, %eax
jne .L25
leaq 16(%rsp), %rdi
movl $8192, %esi
call cudaMalloc@PLT
movl %eax, %r13d
testl %eax, %eax
je .L13
leaq .LC2(%rip), %rsi
.L25:
leaq _ZSt4cerr(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movl %r13d, %edi
movq %rax, %rbx
call cudaGetErrorString@PLT
movq %rbx, %rdi
movq %rax, %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@GOTPCREL(%rip), %rsi
movq %rax, %rdi
call _ZNSolsEPFRSoS_E.isra.0
orl $-1, %eax
jmp .L9
.L13:
movl $8192, %esi
leaq 24(%rsp), %rdi
call cudaMalloc@PLT
leaq .LC3(%rip), %rsi
movl %eax, %r13d
testl %eax, %eax
jne .L25
movq 8(%rsp), %rdi
movq %rbp, %rsi
movl $1, %ecx
movl $8192, %edx
call cudaMemcpy@PLT
leaq .LC4(%rip), %rsi
movl %eax, %r13d
testl %eax, %eax
jne .L25
movq 16(%rsp), %rdi
movq %r12, %rsi
movl $1, %ecx
movl $8192, %edx
call cudaMemcpy@PLT
leaq .LC5(%rip), %rsi
movl %eax, %r13d
testl %eax, %eax
jne .L25
movq 24(%rsp), %rdi
movq %rbx, %rsi
movl $1, %ecx
movl $8192, %edx
call cudaMemcpy@PLT
leaq .LC6(%rip), %rsi
movl %eax, %r13d
testl %eax, %eax
jne .L25
movl $33554433, %edx
movl $268435457, %edi
xorl %r9d, %r9d
xorl %r8d, %r8d
salq $7, %rdx
salq $4, %rdi
movl $1, %ecx
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L19
movss .LC7(%rip), %xmm0
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z50__device_stub__Z25fluidStructureInteractionPfS_S_fPfS_S_f
.L19:
call cudaGetLastError@PLT
leaq .LC8(%rip), %rsi
movl %eax, %r13d
testl %eax, %eax
jne .L25
movq 8(%rsp), %rsi
movl $2, %ecx
movl $8192, %edx
movq %rbp, %rdi
call cudaMemcpy@PLT
leaq .LC9(%rip), %rsi
movl %eax, %r13d
testl %eax, %eax
jne .L25
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq %rbp, %rdi
call _ZdaPv@PLT
movq %r12, %rdi
call _ZdaPv@PLT
movq %rbx, %rdi
call _ZdaPv@PLT
leaq .LC10(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@GOTPCREL(%rip), %rsi
movq %rax, %rdi
call _ZNSolsEPFRSoS_E.isra.0
xorl %eax, %eax
.L9:
movq 56(%rsp), %rdx
subq %fs:40, %rdx
je .L22
call __stack_chk_fail@PLT
.L22:
addq $72, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3635:
.size main, .-main
.section .rodata.str1.1
.LC11:
.string "_Z25fluidStructureInteractionPfS_S_f"
.section .text.startup
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3663:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
pushq $0
.cfi_def_cfa_offset 24
xorl %r9d, %r9d
orl $-1, %r8d
pushq $0
.cfi_def_cfa_offset 32
leaq .LC11(%rip), %rdx
movq %rax, %rdi
leaq _Z25fluidStructureInteractionPfS_S_f(%rip), %rsi
pushq $0
.cfi_def_cfa_offset 40
movq %rdx, %rcx
pushq $0
.cfi_def_cfa_offset 48
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFunction@PLT
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
addq $32, %rsp
.cfi_def_cfa_offset 16
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
popq %rdx
.cfi_def_cfa_offset 8
jmp atexit@PLT
.cfi_endproc
.LFE3663:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC0:
.long 1065353216
.align 4
.LC7:
.long 1008981770
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
```
|
```amdasm
.text
.file "cuda_code_066648.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z40__device_stub__fluidStructureInteractionPfS_S_f # -- Begin function _Z40__device_stub__fluidStructureInteractionPfS_S_f
.type _Z40__device_stub__fluidStructureInteractionPfS_S_f,@function
_Z40__device_stub__fluidStructureInteractionPfS_S_f: # @_Z40__device_stub__fluidStructureInteractionPfS_S_f
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $112, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 40(%rsp), %rax
movq %rdi, (%rax)
leaq 32(%rsp), %rcx
movq %rsi, (%rcx)
leaq 24(%rsp), %rsi
movq %rdx, (%rsi)
leaq 4(%rsp), %rdx
movss %xmm0, (%rdx)
leaq 80(%rsp), %rbx
movq %rax, (%rbx)
movq %rcx, 8(%rbx)
movq %rsi, 16(%rbx)
movq %rdx, 24(%rbx)
leaq 64(%rsp), %r14
leaq 48(%rsp), %r15
leaq 16(%rsp), %r12
leaq 8(%rsp), %r13
movq %r14, %rdi
movq %r15, %rsi
movq %r12, %rdx
movq %r13, %rcx
callq __hipPopCallConfiguration
movq (%r14), %rsi
movl 8(%r14), %edx
movq (%r15), %rcx
movl 8(%r15), %r8d
movl $_Z25fluidStructureInteractionPfS_S_f, %edi
movq %rbx, %r9
pushq (%r13)
.cfi_adjust_cfa_offset 8
pushq (%r12)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $128, %rsp
.cfi_adjust_cfa_offset -128
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z40__device_stub__fluidStructureInteractionPfS_S_f, .Lfunc_end0-_Z40__device_stub__fluidStructureInteractionPfS_S_f
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI1_0:
.long 0x3c23d70a # float 0.00999999977
.text
.globl main
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $32, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $8192, %edi # imm = 0x2000
callq _Znam
movq %rax, %rbx
movl $8192, %edi # imm = 0x2000
callq _Znam
movq %rax, %r14
movl $8192, %edi # imm = 0x2000
callq _Znam
movq %rax, %r15
xorl %r12d, %r12d
movl $8192, %edx # imm = 0x2000
movq %rax, %rdi
xorl %esi, %esi
callq memset@PLT
.LBB1_1: # =>This Inner Loop Header: Depth=1
xorps %xmm0, %xmm0
cvtsi2ss %r12d, %xmm0
movss %xmm0, (%rbx,%r12,4)
movl $1065353216, (%r14,%r12,4) # imm = 0x3F800000
incq %r12
cmpq $2048, %r12 # imm = 0x800
jne .LBB1_1
# %bb.2:
leaq 8(%rsp), %rdi
movl $8192, %esi # imm = 0x2000
callq hipMalloc
testl %eax, %eax
je .LBB1_4
# %bb.3:
movl %eax, %ebp
movl $_ZSt4cerr, %edi
movl $.L.str, %esi
movl $46, %edx
jmp .LBB1_10
.LBB1_4:
leaq 24(%rsp), %rdi
movl $8192, %esi # imm = 0x2000
callq hipMalloc
testl %eax, %eax
je .LBB1_6
# %bb.5:
movl %eax, %ebp
movl $_ZSt4cerr, %edi
movl $.L.str.1, %esi
movl $47, %edx
jmp .LBB1_10
.LBB1_6:
leaq 16(%rsp), %rdi
movl $8192, %esi # imm = 0x2000
callq hipMalloc
testl %eax, %eax
je .LBB1_8
# %bb.7:
movl %eax, %ebp
movl $_ZSt4cerr, %edi
movl $.L.str.2, %esi
movl $43, %edx
jmp .LBB1_10
.LBB1_8:
movq 8(%rsp), %rdi
movl $8192, %edx # imm = 0x2000
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
je .LBB1_16
# %bb.9:
movl %eax, %ebp
movl $_ZSt4cerr, %edi
movl $.L.str.3, %esi
movl $35, %edx
.LBB1_10:
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl %ebp, %edi
callq hipGetErrorString
testq %rax, %rax
je .LBB1_12
# %bb.11:
movq %rax, %rbx
movq %rax, %rdi
callq strlen
movl $_ZSt4cerr, %edi
movq %rbx, %rsi
movq %rax, %rdx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
jmp .LBB1_13
.LBB1_12:
movq _ZSt4cerr(%rip), %rax
movq -24(%rax), %rax
leaq _ZSt4cerr(%rax), %rdi
movl 32(%rdi), %esi
orl $1, %esi
callq _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate
.LBB1_13: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit
movq _ZSt4cerr(%rip), %rax
movl $_ZSt4cerr, %ecx
movq -24(%rax), %rdi
addq %rcx, %rdi
movl $10, %esi
callq _ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
movsbl %al, %esi
movl $_ZSt4cerr, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
.LBB1_14:
movl $-1, %eax
.LBB1_15:
addq $32, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB1_16:
.cfi_def_cfa_offset 80
movq 24(%rsp), %rdi
movl $8192, %edx # imm = 0x2000
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
je .LBB1_18
# %bb.17:
movl %eax, %ebp
movl $_ZSt4cerr, %edi
movl $.L.str.4, %esi
movl $36, %edx
jmp .LBB1_26
.LBB1_18:
movq 16(%rsp), %rdi
movl $8192, %edx # imm = 0x2000
movq %r15, %rsi
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
je .LBB1_20
# %bb.19:
movl %eax, %ebp
movl $_ZSt4cerr, %edi
movl $.L.str.5, %esi
movl $32, %edx
jmp .LBB1_26
.LBB1_20:
movabsq $4294967312, %rdi # imm = 0x100000010
leaq 112(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_22
# %bb.21:
movq 8(%rsp), %rdi
movq 24(%rsp), %rsi
movq 16(%rsp), %rdx
movss .LCPI1_0(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero
callq _Z40__device_stub__fluidStructureInteractionPfS_S_f
.LBB1_22:
callq hipGetLastError
testl %eax, %eax
je .LBB1_24
# %bb.23:
movl %eax, %ebp
movl $_ZSt4cerr, %edi
movl $.L.str.6, %esi
movl $24, %edx
jmp .LBB1_26
.LBB1_24:
movq 8(%rsp), %rsi
movl $8192, %edx # imm = 0x2000
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
je .LBB1_27
# %bb.25:
movl %eax, %ebp
movl $_ZSt4cerr, %edi
movl $.L.str.7, %esi
movl $38, %edx
.LBB1_26:
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl %ebp, %edi
callq hipGetErrorString
movl $_ZSt4cerr, %edi
movq %rax, %rsi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movq %rax, %rdi
callq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_
jmp .LBB1_14
.LBB1_27:
movq 8(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq %rbx, %rdi
callq _ZdaPv
movq %r14, %rdi
callq _ZdaPv
movq %r15, %rdi
callq _ZdaPv
movl $_ZSt4cout, %edi
movl $.L.str.8, %esi
movl $34, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
callq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_
xorl %eax, %eax
jmp .LBB1_15
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, %rdi
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z25fluidStructureInteractionPfS_S_f, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z25fluidStructureInteractionPfS_S_f,@object # @_Z25fluidStructureInteractionPfS_S_f
.section .rodata,"a",@progbits
.globl _Z25fluidStructureInteractionPfS_S_f
.p2align 3, 0x0
_Z25fluidStructureInteractionPfS_S_f:
.quad _Z40__device_stub__fluidStructureInteractionPfS_S_f
.size _Z25fluidStructureInteractionPfS_S_f, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Error allocating device memory for positions: "
.size .L.str, 47
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Error allocating device memory for velocities: "
.size .L.str.1, 48
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Error allocating device memory for forces: "
.size .L.str.2, 44
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Error copying positions to device: "
.size .L.str.3, 36
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Error copying velocities to device: "
.size .L.str.4, 37
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "Error copying forces to device: "
.size .L.str.5, 33
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "Error launching kernel: "
.size .L.str.6, 25
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "Error copying positions back to host: "
.size .L.str.7, 39
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "Simulation completed successfully."
.size .L.str.8, 35
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z25fluidStructureInteractionPfS_S_f"
.size .L__unnamed_1, 37
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z40__device_stub__fluidStructureInteractionPfS_S_f
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z25fluidStructureInteractionPfS_S_f
.addrsig_sym _ZSt4cerr
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
```
| 4,101 | 5,497 |
113,682 |
Convert the following CUDA device assembly code to AMD device assembly:
```cudaasm
code for sm_80
Function : _Z11btreeKernelP9BTreeNode
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
MOV R1, c[0x0][0x28] ;
S2R R2, SR_CTAID.X ;
S2R R3, SR_TID.X ;
IMAD R2, R2, c[0x0][0x0], R3 ;
ISETP.GT.AND P0, PT, R2, 0x3fff, PT ;
@P0 EXIT ;
HFMA2.MMA R5, -RZ, RZ, 0, 7.152557373046875e-07 ;
MOV R7, 0x1 ;
ULDC.64 UR4, c[0x0][0x118] ;
IMAD.WIDE R2, R2, R5, c[0x0][0x160] ;
RED.E.ADD.STRONG.GPU [R2.64], R7 ;
BAR.SYNC.DEFER_BLOCKING 0x0 ;
LDG.E R4, [R2.64+0x4] ;
BSSY B0, 0x140 ;
ISETP.NE.AND P0, PT, R4, -0x1, PT ;
@!P0 BRA 0x130 ;
IMAD.WIDE R4, R4, R5, c[0x0][0x160] ;
LDG.E R5, [R4.64] ;
RED.E.ADD.STRONG.GPU [R2.64], R5 ;
BSYNC B0 ;
BAR.SYNC.DEFER_BLOCKING 0x0 ;
EXIT ;
BRA 0x160;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
```
|
```amdasm
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z11btreeKernelP9BTreeNode ; -- Begin function _Z11btreeKernelP9BTreeNode
.globl _Z11btreeKernelP9BTreeNode
.p2align 8
.type _Z11btreeKernelP9BTreeNode,@function
_Z11btreeKernelP9BTreeNode: ; @_Z11btreeKernelP9BTreeNode
; %bb.0:
s_load_b32 s2, s[0:1], 0x14
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e32 0x4000, v2
s_cbranch_execz .LBB0_4
; %bb.1:
s_load_b64 s[0:1], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
v_mad_i64_i32 v[0:1], null, v2, 12, s[0:1]
v_mov_b32_e32 v2, 1
global_atomic_add_u32 v[0:1], v2, off
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
global_load_b32 v2, v[0:1], off offset:4
s_waitcnt vmcnt(0)
v_cmp_ne_u32_e32 vcc_lo, -1, v2
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_3
; %bb.2:
v_mad_i64_i32 v[3:4], null, v2, 12, s[0:1]
global_load_b32 v2, v[3:4], off
s_waitcnt vmcnt(0)
global_atomic_add_u32 v[0:1], v2, off
.LBB0_3:
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
.LBB0_4:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11btreeKernelP9BTreeNode
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 264
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z11btreeKernelP9BTreeNode, .Lfunc_end0-_Z11btreeKernelP9BTreeNode
; -- End function
.section .AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 168
; NumSgprs: 18
; NumVgprs: 5
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 5
; Occupancy: 16
; WaveLimiterHint : 1
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object ; @__hip_cuid_
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0 ; 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: hidden_block_count_x
- .offset: 12
.size: 4
.value_kind: hidden_block_count_y
- .offset: 16
.size: 4
.value_kind: hidden_block_count_z
- .offset: 20
.size: 2
.value_kind: hidden_group_size_x
- .offset: 22
.size: 2
.value_kind: hidden_group_size_y
- .offset: 24
.size: 2
.value_kind: hidden_group_size_z
- .offset: 26
.size: 2
.value_kind: hidden_remainder_x
- .offset: 28
.size: 2
.value_kind: hidden_remainder_y
- .offset: 30
.size: 2
.value_kind: hidden_remainder_z
- .offset: 48
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 72
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 264
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11btreeKernelP9BTreeNode
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z11btreeKernelP9BTreeNode.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
```
| 454 | 2,383 |
113,683 |
Convert the following CUDA host assembly code to AMD host assembly:
```cudaasm
.file "tmpxft_00069f61_00000000-6_cuda_code_078234.cudafe1.cpp"
.text
.globl _ZSt21ios_base_library_initv
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3638:
.cfi_startproc
endbr64
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
jmp __cudaUnregisterFatBinary@PLT
.cfi_endproc
.LFE3638:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z40__device_stub__Z11btreeKernelP9BTreeNodeP9BTreeNode
.type _Z40__device_stub__Z11btreeKernelP9BTreeNodeP9BTreeNode, @function
_Z40__device_stub__Z11btreeKernelP9BTreeNodeP9BTreeNode:
.LFB3660:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movl $1, 40(%rsp)
movq %rax, 80(%rsp)
movabsq $4294967297, %rax
movq %rax, 32(%rsp)
movq %rax, 44(%rsp)
movl $1, 52(%rsp)
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
jne .L2
pushq 24(%rsp)
.cfi_def_cfa_offset 120
leaq _Z11btreeKernelP9BTreeNode(%rip), %rdi
pushq 24(%rsp)
.cfi_def_cfa_offset 128
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq 96(%rsp), %r9
call cudaLaunchKernel@PLT
popq %rax
.cfi_def_cfa_offset 120
popq %rdx
.cfi_def_cfa_offset 112
.L2:
movq 88(%rsp), %rax
subq %fs:40, %rax
je .L4
call __stack_chk_fail@PLT
.L4:
addq $104, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3660:
.size _Z40__device_stub__Z11btreeKernelP9BTreeNodeP9BTreeNode, .-_Z40__device_stub__Z11btreeKernelP9BTreeNodeP9BTreeNode
.globl _Z11btreeKernelP9BTreeNode
.type _Z11btreeKernelP9BTreeNode, @function
_Z11btreeKernelP9BTreeNode:
.LFB3661:
.cfi_startproc
endbr64
jmp _Z40__device_stub__Z11btreeKernelP9BTreeNodeP9BTreeNode
.cfi_endproc
.LFE3661:
.size _Z11btreeKernelP9BTreeNode, .-_Z11btreeKernelP9BTreeNode
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Failed to allocate Unified Memory"
.LC1:
.string "Kernel launch failed"
.LC2:
.string "Node "
.LC3:
.string ": data = "
.LC4:
.string ", left = "
.LC5:
.string ", right = "
.section .text.startup,"ax",@progbits
.globl main
.type main, @function
main:
.LFB3635:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
movl $1, %edx
movl $196608, %esi
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $48, %rsp
.cfi_def_cfa_offset 80
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rdi
call cudaMallocManaged@PLT
testl %eax, %eax
je .L9
leaq .LC0(%rip), %rsi
leaq _ZSt4cerr(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
jmp .L10
.L9:
movq 8(%rsp), %rcx
movl $2, %edx
xorl %eax, %eax
orl $-1, %edi
.L13:
leal (%rax,%rax), %r8d
movl %eax, (%rcx)
orl $-1, %esi
cmpl $16382, %r8d
ja .L11
leal -1(%rdx), %esi
.L11:
movl %esi, 4(%rcx)
incl %eax
movl %edi, %esi
cmpl $16384, %edx
cmovb %edx, %esi
addq $12, %rcx
addl $2, %edx
movl %esi, -4(%rcx)
cmpl $16384, %eax
jne .L13
movl $16777217, %edx
movl $67108865, %edi
xorl %r9d, %r9d
xorl %r8d, %r8d
salq $8, %rdx
salq $6, %rdi
movl $1, %ecx
movl $1, %esi
movq %rdx, 28(%rsp)
movl $1, 36(%rsp)
movq %rdi, 16(%rsp)
movl $1, 24(%rsp)
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L14
movq 8(%rsp), %rdi
call _Z40__device_stub__Z11btreeKernelP9BTreeNodeP9BTreeNode
.L14:
call cudaDeviceSynchronize@PLT
xorl %ebx, %ebx
leaq .LC2(%rip), %rbp
testl %eax, %eax
je .L15
leaq .LC1(%rip), %rsi
leaq _ZSt4cerr(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
.L10:
orl $-1, %eax
jmp .L8
.L15:
movq %rbp, %rsi
imulq $12, %rbx, %r12
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movl %ebx, %esi
incq %rbx
movq %rax, %rdi
call _ZNSolsEi@PLT
leaq .LC3(%rip), %rsi
movq %rax, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movq 8(%rsp), %rax
movl (%rax,%r12), %esi
call _ZNSolsEi@PLT
leaq .LC4(%rip), %rsi
movq %rax, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movq 8(%rsp), %rax
movl 4(%rax,%r12), %esi
call _ZNSolsEi@PLT
leaq .LC5(%rip), %rsi
movq %rax, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movq 8(%rsp), %rax
movl 8(%rax,%r12), %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
cmpq $10, %rbx
jne .L15
movq 8(%rsp), %rdi
call cudaFree@PLT
xorl %eax, %eax
.L8:
movq 40(%rsp), %rdx
subq %fs:40, %rdx
je .L17
call __stack_chk_fail@PLT
.L17:
addq $48, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3635:
.size main, .-main
.section .rodata.str1.1
.LC6:
.string "_Z11btreeKernelP9BTreeNode"
.section .text.startup
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3663:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
pushq $0
.cfi_def_cfa_offset 24
xorl %r9d, %r9d
orl $-1, %r8d
pushq $0
.cfi_def_cfa_offset 32
leaq .LC6(%rip), %rdx
movq %rax, %rdi
leaq _Z11btreeKernelP9BTreeNode(%rip), %rsi
pushq $0
.cfi_def_cfa_offset 40
movq %rdx, %rcx
pushq $0
.cfi_def_cfa_offset 48
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFunction@PLT
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
addq $32, %rsp
.cfi_def_cfa_offset 16
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
popq %rdx
.cfi_def_cfa_offset 8
jmp atexit@PLT
.cfi_endproc
.LFE3663:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
```
|
```amdasm
.text
.file "cuda_code_078234.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z26__device_stub__btreeKernelP9BTreeNode # -- Begin function _Z26__device_stub__btreeKernelP9BTreeNode
.type _Z26__device_stub__btreeKernelP9BTreeNode,@function
_Z26__device_stub__btreeKernelP9BTreeNode: # @_Z26__device_stub__btreeKernelP9BTreeNode
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $64, %rsp
.cfi_def_cfa_offset 112
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 24(%rsp), %rax
movq %rdi, (%rax)
movq %rsp, %rbx
movq %rax, (%rbx)
leaq 48(%rsp), %r14
leaq 32(%rsp), %r15
leaq 16(%rsp), %r12
leaq 8(%rsp), %r13
movq %r14, %rdi
movq %r15, %rsi
movq %r12, %rdx
movq %r13, %rcx
callq __hipPopCallConfiguration
movq (%r14), %rsi
movl 8(%r14), %edx
movq (%r15), %rcx
movl 8(%r15), %r8d
movl $_Z11btreeKernelP9BTreeNode, %edi
movq %rbx, %r9
pushq (%r13)
.cfi_adjust_cfa_offset 8
pushq (%r12)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $80, %rsp
.cfi_adjust_cfa_offset -80
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z26__device_stub__btreeKernelP9BTreeNode, .Lfunc_end0-_Z26__device_stub__btreeKernelP9BTreeNode
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $16, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 8(%rsp), %rdi
movl $196608, %esi # imm = 0x30000
movl $1, %edx
callq hipMallocManaged
testl %eax, %eax
je .LBB1_1
# %bb.10:
movl $_ZSt4cerr, %ebx
movl $_ZSt4cerr, %edi
movl $.L.str, %esi
movl $33, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cerr(%rip), %rax
movq -24(%rax), %rdi
addq %rbx, %rdi
movl $10, %esi
callq _ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
movsbl %al, %esi
movl $_ZSt4cerr, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
jmp .LBB1_11
.LBB1_1: # %.preheader29
movq 8(%rsp), %rax
addq $8, %rax
movl $2, %ecx
movl $1, %edx
xorl %esi, %esi
movl $16384, %edi # imm = 0x4000
.LBB1_2: # =>This Inner Loop Header: Depth=1
cmpq %rdi, %rdx
movl $-1, %r8d
cmovbl %edx, %r8d
movl %esi, -8(%rax)
movl %r8d, -4(%rax)
cmpq $8191, %rsi # imm = 0x1FFF
movl $-1, %r8d
cmovbl %ecx, %r8d
movl %r8d, (%rax)
incq %rsi
addq $12, %rax
addl $2, %ecx
addq $2, %rdx
cmpq %rdi, %rsi
jne .LBB1_2
# %bb.3:
movabsq $4294967360, %rdi # imm = 0x100000040
leaq 192(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_5
# %bb.4:
movq 8(%rsp), %rdi
callq _Z26__device_stub__btreeKernelP9BTreeNode
.LBB1_5:
callq hipDeviceSynchronize
testl %eax, %eax
je .LBB1_6
# %bb.9:
movl $_ZSt4cerr, %ebx
movl $_ZSt4cerr, %edi
movl $.L.str.1, %esi
movl $20, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cerr(%rip), %rax
movq -24(%rax), %rdi
addq %rbx, %rdi
movl $10, %esi
callq _ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
movsbl %al, %esi
movl $_ZSt4cerr, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq 8(%rsp), %rdi
callq hipFree
.LBB1_11:
movl $-1, %eax
.LBB1_12:
addq $16, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB1_6: # %.preheader.preheader
.cfi_def_cfa_offset 48
xorl %r15d, %r15d
xorl %ebx, %ebx
.LBB1_7: # %.preheader
# =>This Inner Loop Header: Depth=1
movl $_ZSt4cout, %edi
movl $.L.str.2, %esi
movl $5, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl %ebx, %esi
callq _ZNSolsEi
movq %rax, %r14
movl $.L.str.3, %esi
movl $9, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq 8(%rsp), %rax
movl (%rax,%r15), %esi
movq %r14, %rdi
callq _ZNSolsEi
movq %rax, %r14
movl $.L.str.4, %esi
movl $9, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq 8(%rsp), %rax
movl 4(%rax,%r15), %esi
movq %r14, %rdi
callq _ZNSolsEi
movq %rax, %r14
movl $.L.str.5, %esi
movl $10, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq 8(%rsp), %rax
movl 8(%rax,%r15), %esi
movq %r14, %rdi
callq _ZNSolsEi
movq %rax, %r14
movq (%rax), %rax
movq -24(%rax), %rdi
addq %r14, %rdi
movl $10, %esi
callq _ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
movsbl %al, %esi
movq %r14, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
incq %rbx
addq $12, %r15
cmpq $10, %rbx
jne .LBB1_7
# %bb.8:
movq 8(%rsp), %rdi
callq hipFree
xorl %eax, %eax
jmp .LBB1_12
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, %rdi
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11btreeKernelP9BTreeNode, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z11btreeKernelP9BTreeNode,@object # @_Z11btreeKernelP9BTreeNode
.section .rodata,"a",@progbits
.globl _Z11btreeKernelP9BTreeNode
.p2align 3, 0x0
_Z11btreeKernelP9BTreeNode:
.quad _Z26__device_stub__btreeKernelP9BTreeNode
.size _Z11btreeKernelP9BTreeNode, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Failed to allocate Unified Memory"
.size .L.str, 34
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Kernel launch failed"
.size .L.str.1, 21
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Node "
.size .L.str.2, 6
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz ": data = "
.size .L.str.3, 10
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz ", left = "
.size .L.str.4, 10
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz ", right = "
.size .L.str.5, 11
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z11btreeKernelP9BTreeNode"
.size .L__unnamed_1, 27
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z26__device_stub__btreeKernelP9BTreeNode
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z11btreeKernelP9BTreeNode
.addrsig_sym _ZSt4cerr
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
```
| 3,437 | 4,313 |
113,684 |
Convert the following CUDA device assembly code to AMD device assembly:
```cudaasm
code for sm_80
Function : _Z13argon2_kernelPji
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ;
S2R R0, SR_TID.X ;
IMAD.MOV.U32 R21, RZ, RZ, 0x4 ;
ULDC.64 UR4, c[0x0][0x118] ;
IMAD.SHL.U32 R2, R0, 0x8, RZ ;
IMAD.WIDE R22, R2, R21, c[0x0][0x160] ;
LDG.E R8, [R22.64] ;
LDG.E R9, [R22.64+0x4] ;
LDG.E R10, [R22.64+0x8] ;
LDG.E R11, [R22.64+0xc] ;
LDG.E R4, [R22.64+0x10] ;
LDG.E R5, [R22.64+0x14] ;
LDG.E R6, [R22.64+0x18] ;
LDG.E R7, [R22.64+0x1c] ;
IMAD.SHL.U32 R0, R0, 0x20, RZ ;
LOP3.LUT R20, R2, 0x38, RZ, 0xc0, !PT ;
IMAD.MOV.U32 R2, RZ, RZ, RZ ;
S2R R3, SR_LANEID ;
IMAD.WIDE.U32 R20, R20, R21, c[0x0][0x160] ;
LOP3.LUT R3, R3, 0xfffffff8, RZ, 0xc0, !PT ;
STS.128 [R0], R8 ;
STS.128 [R0+0x10], R4 ;
LDG.E R4, [R20.64] ;
LDG.E R5, [R20.64+0x4] ;
LDG.E R6, [R20.64+0x8] ;
LDG.E R7, [R20.64+0xc] ;
LDG.E R8, [R20.64+0x10] ;
LDG.E R9, [R20.64+0x14] ;
LDG.E R10, [R20.64+0x18] ;
LDG.E R11, [R20.64+0x1c] ;
IADD3 R2, R2, 0x1, RZ ;
IMAD.MOV.U32 R12, RZ, RZ, 0x4 ;
ISETP.GE.U32.AND P0, PT, R2, 0x3, PT ;
LOP3.LUT R13, R4, c[0x3][0x0], RZ, 0x3c, !PT ;
LOP3.LUT R14, R5, c[0x3][0x4], RZ, 0x3c, !PT ;
LOP3.LUT R13, R13, c[0x3][0x1c], RZ, 0x3c, !PT ;
LOP3.LUT R15, R6, c[0x3][0x8], RZ, 0x3c, !PT ;
LOP3.LUT R14, R14, c[0x3][0x0], RZ, 0x3c, !PT ;
LOP3.LUT R16, R7, c[0x3][0xc], RZ, 0x3c, !PT ;
STS.128 [R0], R4 ;
LOP3.LUT R15, R15, c[0x3][0x4], RZ, 0x3c, !PT ;
LOP3.LUT R17, R8, c[0x3][0x10], RZ, 0x3c, !PT ;
LOP3.LUT R16, R16, c[0x3][0x8], RZ, 0x3c, !PT ;
LOP3.LUT R18, R9, c[0x3][0x14], RZ, 0x3c, !PT ;
LOP3.LUT R17, R17, c[0x3][0xc], RZ, 0x3c, !PT ;
LOP3.LUT R19, R10, c[0x3][0x18], RZ, 0x3c, !PT ;
LOP3.LUT R18, R18, c[0x3][0x10], RZ, 0x3c, !PT ;
LOP3.LUT R24, R11, c[0x3][0x1c], RZ, 0x3c, !PT ;
STS.128 [R0+0x10], R8 ;
LOP3.LUT R19, R19, c[0x3][0x14], RZ, 0x3c, !PT ;
LOP3.LUT R24, R24, c[0x3][0x18], RZ, 0x3c, !PT ;
LOP3.LUT R13, R13, c[0x3][0x18], RZ, 0x3c, !PT ;
LOP3.LUT R14, R14, c[0x3][0x1c], RZ, 0x3c, !PT ;
LOP3.LUT R15, R15, c[0x3][0x0], RZ, 0x3c, !PT ;
LOP3.LUT R16, R16, c[0x3][0x4], RZ, 0x3c, !PT ;
LOP3.LUT R17, R17, c[0x3][0x8], RZ, 0x3c, !PT ;
LOP3.LUT R18, R18, c[0x3][0xc], RZ, 0x3c, !PT ;
LOP3.LUT R19, R19, c[0x3][0x10], RZ, 0x3c, !PT ;
LOP3.LUT R24, R24, c[0x3][0x14], RZ, 0x3c, !PT ;
LOP3.LUT R8, R16, c[0x3][0x0], RZ, 0x3c, !PT ;
LOP3.LUT R5, R13, c[0x3][0x14], RZ, 0x3c, !PT ;
LOP3.LUT R6, R14, c[0x3][0x18], RZ, 0x3c, !PT ;
LOP3.LUT R7, R15, c[0x3][0x1c], RZ, 0x3c, !PT ;
LOP3.LUT R9, R17, c[0x3][0x4], RZ, 0x3c, !PT ;
LOP3.LUT R10, R18, c[0x3][0x8], RZ, 0x3c, !PT ;
LOP3.LUT R11, R19, c[0x3][0xc], RZ, 0x3c, !PT ;
LOP3.LUT R4, R24, c[0x3][0x10], RZ, 0x3c, !PT ;
LOP3.LUT R10, R10, c[0x3][0x4], RZ, 0x3c, !PT ;
LOP3.LUT R11, R11, c[0x3][0x8], RZ, 0x3c, !PT ;
LOP3.LUT R5, R5, c[0x3][0x10], RZ, 0x3c, !PT ;
LOP3.LUT R13, R4, c[0x3][0xc], RZ, 0x3c, !PT ;
LOP3.LUT R9, R9, c[0x3][0x0], RZ, 0x3c, !PT ;
LOP3.LUT R6, R6, c[0x3][0x14], RZ, 0x3c, !PT ;
LOP3.LUT R7, R7, c[0x3][0x18], RZ, 0x3c, !PT ;
LOP3.LUT R8, R8, c[0x3][0x1c], RZ, 0x3c, !PT ;
LOP3.LUT R4, R10, c[0x3][0x0], RZ, 0x3c, !PT ;
LOP3.LUT R11, R11, c[0x3][0x4], RZ, 0x3c, !PT ;
LOP3.LUT R10, R5, c[0x3][0xc], RZ, 0x3c, !PT ;
LOP3.LUT R13, R13, c[0x3][0x8], RZ, 0x3c, !PT ;
LOP3.LUT R6, R6, c[0x3][0x10], RZ, 0x3c, !PT ;
LOP3.LUT R7, R7, c[0x3][0x14], RZ, 0x3c, !PT ;
LOP3.LUT R8, R8, c[0x3][0x18], RZ, 0x3c, !PT ;
LOP3.LUT R9, R9, c[0x3][0x1c], RZ, 0x3c, !PT ;
LOP3.LUT R5, R11, c[0x3][0x0], RZ, 0x3c, !PT ;
LOP3.LUT R10, R10, c[0x3][0x8], RZ, 0x3c, !PT ;
LOP3.LUT R13, R13, c[0x3][0x4], RZ, 0x3c, !PT ;
LOP3.LUT R11, R4, c[0x3][0x1c], RZ, 0x3c, !PT ;
LOP3.LUT R6, R6, c[0x3][0xc], RZ, 0x3c, !PT ;
LOP3.LUT R7, R7, c[0x3][0x10], RZ, 0x3c, !PT ;
LOP3.LUT R8, R8, c[0x3][0x14], RZ, 0x3c, !PT ;
LOP3.LUT R9, R9, c[0x3][0x18], RZ, 0x3c, !PT ;
LOP3.LUT R10, R10, c[0x3][0x4], RZ, 0x3c, !PT ;
LOP3.LUT R4, R13, c[0x3][0x0], RZ, 0x3c, !PT ;
LOP3.LUT R11, R11, c[0x3][0x18], RZ, 0x3c, !PT ;
LOP3.LUT R6, R6, c[0x3][0x8], RZ, 0x3c, !PT ;
LOP3.LUT R7, R7, c[0x3][0xc], RZ, 0x3c, !PT ;
LOP3.LUT R8, R8, c[0x3][0x10], RZ, 0x3c, !PT ;
LOP3.LUT R9, R9, c[0x3][0x14], RZ, 0x3c, !PT ;
LOP3.LUT R13, R5, c[0x3][0x1c], RZ, 0x3c, !PT ;
LOP3.LUT R5, R10, c[0x3][0x0], RZ, 0x3c, !PT ;
LOP3.LUT R11, R11, c[0x3][0x14], RZ, 0x3c, !PT ;
LOP3.LUT R10, R4, c[0x3][0x1c], RZ, 0x3c, !PT ;
LOP3.LUT R6, R6, c[0x3][0x4], RZ, 0x3c, !PT ;
LOP3.LUT R7, R7, c[0x3][0x8], RZ, 0x3c, !PT ;
LOP3.LUT R8, R8, c[0x3][0xc], RZ, 0x3c, !PT ;
LOP3.LUT R9, R9, c[0x3][0x10], RZ, 0x3c, !PT ;
LOP3.LUT R13, R13, c[0x3][0x18], RZ, 0x3c, !PT ;
LOP3.LUT R11, R11, c[0x3][0x10], RZ, 0x3c, !PT ;
LOP3.LUT R10, R10, c[0x3][0x18], RZ, 0x3c, !PT ;
LOP3.LUT R4, R6, c[0x3][0x0], RZ, 0x3c, !PT ;
LOP3.LUT R7, R7, c[0x3][0x4], RZ, 0x3c, !PT ;
LOP3.LUT R8, R8, c[0x3][0x8], RZ, 0x3c, !PT ;
LOP3.LUT R9, R9, c[0x3][0xc], RZ, 0x3c, !PT ;
LOP3.LUT R13, R13, c[0x3][0x14], RZ, 0x3c, !PT ;
LOP3.LUT R6, R5, c[0x3][0x1c], RZ, 0x3c, !PT ;
LOP3.LUT R11, R11, c[0x3][0xc], RZ, 0x3c, !PT ;
LOP3.LUT R10, R10, c[0x3][0x14], RZ, 0x3c, !PT ;
LOP3.LUT R5, R7, c[0x3][0x0], RZ, 0x3c, !PT ;
LOP3.LUT R8, R8, c[0x3][0x4], RZ, 0x3c, !PT ;
LOP3.LUT R9, R9, c[0x3][0x8], RZ, 0x3c, !PT ;
LOP3.LUT R13, R13, c[0x3][0x10], RZ, 0x3c, !PT ;
LOP3.LUT R6, R6, c[0x3][0x18], RZ, 0x3c, !PT ;
LOP3.LUT R7, R4, c[0x3][0x1c], RZ, 0x3c, !PT ;
LOP3.LUT R11, R11, c[0x3][0x8], RZ, 0x3c, !PT ;
LOP3.LUT R10, R10, c[0x3][0x10], RZ, 0x3c, !PT ;
LOP3.LUT R4, R8, c[0x3][0x0], RZ, 0x3c, !PT ;
LOP3.LUT R9, R9, c[0x3][0x4], RZ, 0x3c, !PT ;
LOP3.LUT R13, R13, c[0x3][0xc], RZ, 0x3c, !PT ;
LOP3.LUT R6, R6, c[0x3][0x14], RZ, 0x3c, !PT ;
LOP3.LUT R7, R7, c[0x3][0x18], RZ, 0x3c, !PT ;
LOP3.LUT R8, R5, c[0x3][0x1c], RZ, 0x3c, !PT ;
LOP3.LUT R11, R11, c[0x3][0x4], RZ, 0x3c, !PT ;
LOP3.LUT R10, R10, c[0x3][0xc], RZ, 0x3c, !PT ;
LOP3.LUT R5, R9, c[0x3][0x0], RZ, 0x3c, !PT ;
LOP3.LUT R13, R13, c[0x3][0x8], RZ, 0x3c, !PT ;
LOP3.LUT R6, R6, c[0x3][0x10], RZ, 0x3c, !PT ;
LOP3.LUT R7, R7, c[0x3][0x14], RZ, 0x3c, !PT ;
LOP3.LUT R8, R8, c[0x3][0x18], RZ, 0x3c, !PT ;
LOP3.LUT R9, R4, c[0x3][0x1c], RZ, 0x3c, !PT ;
LOP3.LUT R4, R11, c[0x3][0x0], RZ, 0x3c, !PT ;
LOP3.LUT R10, R10, c[0x3][0x8], RZ, 0x3c, !PT ;
LOP3.LUT R13, R13, c[0x3][0x4], RZ, 0x3c, !PT ;
LOP3.LUT R11, R5, c[0x3][0x1c], RZ, 0x3c, !PT ;
LOP3.LUT R6, R6, c[0x3][0xc], RZ, 0x3c, !PT ;
LOP3.LUT R7, R7, c[0x3][0x10], RZ, 0x3c, !PT ;
LOP3.LUT R8, R8, c[0x3][0x14], RZ, 0x3c, !PT ;
LOP3.LUT R9, R9, c[0x3][0x18], RZ, 0x3c, !PT ;
LOP3.LUT R10, R10, c[0x3][0x4], RZ, 0x3c, !PT ;
LOP3.LUT R5, R13, c[0x3][0x0], RZ, 0x3c, !PT ;
LOP3.LUT R11, R11, c[0x3][0x18], RZ, 0x3c, !PT ;
LOP3.LUT R6, R6, c[0x3][0x8], RZ, 0x3c, !PT ;
LOP3.LUT R7, R7, c[0x3][0xc], RZ, 0x3c, !PT ;
LOP3.LUT R8, R8, c[0x3][0x10], RZ, 0x3c, !PT ;
LOP3.LUT R9, R9, c[0x3][0x14], RZ, 0x3c, !PT ;
LOP3.LUT R13, R4, c[0x3][0x1c], RZ, 0x3c, !PT ;
LOP3.LUT R4, R10, c[0x3][0x0], RZ, 0x3c, !PT ;
LOP3.LUT R11, R11, c[0x3][0x14], RZ, 0x3c, !PT ;
LOP3.LUT R10, R5, c[0x3][0x1c], RZ, 0x3c, !PT ;
LOP3.LUT R6, R6, c[0x3][0x4], RZ, 0x3c, !PT ;
LOP3.LUT R7, R7, c[0x3][0x8], RZ, 0x3c, !PT ;
LOP3.LUT R8, R8, c[0x3][0xc], RZ, 0x3c, !PT ;
LOP3.LUT R9, R9, c[0x3][0x10], RZ, 0x3c, !PT ;
LOP3.LUT R13, R13, c[0x3][0x18], RZ, 0x3c, !PT ;
LOP3.LUT R11, R11, c[0x3][0x10], RZ, 0x3c, !PT ;
LOP3.LUT R10, R10, c[0x3][0x18], RZ, 0x3c, !PT ;
LOP3.LUT R5, R6, c[0x3][0x0], RZ, 0x3c, !PT ;
LOP3.LUT R7, R7, c[0x3][0x4], RZ, 0x3c, !PT ;
LOP3.LUT R8, R8, c[0x3][0x8], RZ, 0x3c, !PT ;
LOP3.LUT R9, R9, c[0x3][0xc], RZ, 0x3c, !PT ;
LOP3.LUT R13, R13, c[0x3][0x14], RZ, 0x3c, !PT ;
LOP3.LUT R6, R4, c[0x3][0x1c], RZ, 0x3c, !PT ;
LOP3.LUT R11, R11, c[0x3][0xc], RZ, 0x3c, !PT ;
LOP3.LUT R10, R10, c[0x3][0x14], RZ, 0x3c, !PT ;
LOP3.LUT R4, R7, c[0x3][0x0], RZ, 0x3c, !PT ;
LOP3.LUT R8, R8, c[0x3][0x4], RZ, 0x3c, !PT ;
LOP3.LUT R9, R9, c[0x3][0x8], RZ, 0x3c, !PT ;
LOP3.LUT R13, R13, c[0x3][0x10], RZ, 0x3c, !PT ;
LOP3.LUT R6, R6, c[0x3][0x18], RZ, 0x3c, !PT ;
LOP3.LUT R7, R5, c[0x3][0x1c], RZ, 0x3c, !PT ;
LOP3.LUT R11, R11, c[0x3][0x8], RZ, 0x3c, !PT ;
LOP3.LUT R10, R10, c[0x3][0x10], RZ, 0x3c, !PT ;
LOP3.LUT R5, R8, c[0x3][0x0], RZ, 0x3c, !PT ;
LOP3.LUT R9, R9, c[0x3][0x4], RZ, 0x3c, !PT ;
LOP3.LUT R13, R13, c[0x3][0xc], RZ, 0x3c, !PT ;
LOP3.LUT R6, R6, c[0x3][0x14], RZ, 0x3c, !PT ;
LOP3.LUT R7, R7, c[0x3][0x18], RZ, 0x3c, !PT ;
LOP3.LUT R8, R4, c[0x3][0x1c], RZ, 0x3c, !PT ;
LOP3.LUT R11, R11, c[0x3][0x4], RZ, 0x3c, !PT ;
LOP3.LUT R10, R10, c[0x3][0xc], RZ, 0x3c, !PT ;
LOP3.LUT R4, R9, c[0x3][0x0], RZ, 0x3c, !PT ;
LOP3.LUT R13, R13, c[0x3][0x8], RZ, 0x3c, !PT ;
LOP3.LUT R6, R6, c[0x3][0x10], RZ, 0x3c, !PT ;
LOP3.LUT R7, R7, c[0x3][0x14], RZ, 0x3c, !PT ;
LOP3.LUT R8, R8, c[0x3][0x18], RZ, 0x3c, !PT ;
LOP3.LUT R9, R5, c[0x3][0x1c], RZ, 0x3c, !PT ;
LOP3.LUT R5, R11, c[0x3][0x0], RZ, 0x3c, !PT ;
LOP3.LUT R10, R10, c[0x3][0x8], RZ, 0x3c, !PT ;
LOP3.LUT R13, R13, c[0x3][0x4], RZ, 0x3c, !PT ;
LOP3.LUT R11, R4, c[0x3][0x1c], RZ, 0x3c, !PT ;
LOP3.LUT R6, R6, c[0x3][0xc], RZ, 0x3c, !PT ;
LOP3.LUT R7, R7, c[0x3][0x10], RZ, 0x3c, !PT ;
LOP3.LUT R8, R8, c[0x3][0x14], RZ, 0x3c, !PT ;
LOP3.LUT R9, R9, c[0x3][0x18], RZ, 0x3c, !PT ;
LOP3.LUT R10, R10, c[0x3][0x4], RZ, 0x3c, !PT ;
LOP3.LUT R4, R13, c[0x3][0x0], RZ, 0x3c, !PT ;
LOP3.LUT R11, R11, c[0x3][0x18], RZ, 0x3c, !PT ;
LOP3.LUT R6, R6, c[0x3][0x8], RZ, 0x3c, !PT ;
LOP3.LUT R7, R7, c[0x3][0xc], RZ, 0x3c, !PT ;
LOP3.LUT R8, R8, c[0x3][0x10], RZ, 0x3c, !PT ;
LOP3.LUT R9, R9, c[0x3][0x14], RZ, 0x3c, !PT ;
LOP3.LUT R13, R5, c[0x3][0x1c], RZ, 0x3c, !PT ;
LOP3.LUT R5, R10, c[0x3][0x0], RZ, 0x3c, !PT ;
LOP3.LUT R11, R11, c[0x3][0x14], RZ, 0x3c, !PT ;
LOP3.LUT R10, R4, c[0x3][0x1c], RZ, 0x3c, !PT ;
LOP3.LUT R6, R6, c[0x3][0x4], RZ, 0x3c, !PT ;
LOP3.LUT R7, R7, c[0x3][0x8], RZ, 0x3c, !PT ;
LOP3.LUT R8, R8, c[0x3][0xc], RZ, 0x3c, !PT ;
LOP3.LUT R9, R9, c[0x3][0x10], RZ, 0x3c, !PT ;
LOP3.LUT R13, R13, c[0x3][0x18], RZ, 0x3c, !PT ;
LOP3.LUT R11, R11, c[0x3][0x10], RZ, 0x3c, !PT ;
LOP3.LUT R10, R10, c[0x3][0x18], RZ, 0x3c, !PT ;
LOP3.LUT R4, R6, c[0x3][0x0], RZ, 0x3c, !PT ;
LOP3.LUT R7, R7, c[0x3][0x4], RZ, 0x3c, !PT ;
LOP3.LUT R8, R8, c[0x3][0x8], RZ, 0x3c, !PT ;
LOP3.LUT R9, R9, c[0x3][0xc], RZ, 0x3c, !PT ;
LOP3.LUT R13, R13, c[0x3][0x14], RZ, 0x3c, !PT ;
LOP3.LUT R6, R5, c[0x3][0x1c], RZ, 0x3c, !PT ;
LOP3.LUT R11, R11, c[0x3][0xc], RZ, 0x3c, !PT ;
LOP3.LUT R10, R10, c[0x3][0x14], RZ, 0x3c, !PT ;
LOP3.LUT R5, R7, c[0x3][0x0], RZ, 0x3c, !PT ;
LOP3.LUT R8, R8, c[0x3][0x4], RZ, 0x3c, !PT ;
LOP3.LUT R9, R9, c[0x3][0x8], RZ, 0x3c, !PT ;
LOP3.LUT R13, R13, c[0x3][0x10], RZ, 0x3c, !PT ;
LOP3.LUT R6, R6, c[0x3][0x18], RZ, 0x3c, !PT ;
LOP3.LUT R7, R4, c[0x3][0x1c], RZ, 0x3c, !PT ;
LOP3.LUT R11, R11, c[0x3][0x8], RZ, 0x3c, !PT ;
LOP3.LUT R10, R10, c[0x3][0x10], RZ, 0x3c, !PT ;
LOP3.LUT R4, R8, c[0x3][0x0], RZ, 0x3c, !PT ;
LOP3.LUT R9, R9, c[0x3][0x4], RZ, 0x3c, !PT ;
LOP3.LUT R13, R13, c[0x3][0xc], RZ, 0x3c, !PT ;
LOP3.LUT R6, R6, c[0x3][0x14], RZ, 0x3c, !PT ;
LOP3.LUT R7, R7, c[0x3][0x18], RZ, 0x3c, !PT ;
LOP3.LUT R8, R5, c[0x3][0x1c], RZ, 0x3c, !PT ;
LOP3.LUT R11, R11, c[0x3][0x4], RZ, 0x3c, !PT ;
LOP3.LUT R10, R10, c[0x3][0xc], RZ, 0x3c, !PT ;
LOP3.LUT R5, R9, c[0x3][0x0], RZ, 0x3c, !PT ;
LOP3.LUT R13, R13, c[0x3][0x8], RZ, 0x3c, !PT ;
LOP3.LUT R6, R6, c[0x3][0x10], RZ, 0x3c, !PT ;
LOP3.LUT R7, R7, c[0x3][0x14], RZ, 0x3c, !PT ;
LOP3.LUT R8, R8, c[0x3][0x18], RZ, 0x3c, !PT ;
LOP3.LUT R9, R4, c[0x3][0x1c], RZ, 0x3c, !PT ;
LOP3.LUT R4, R11, c[0x3][0x0], RZ, 0x3c, !PT ;
LOP3.LUT R10, R10, c[0x3][0x8], RZ, 0x3c, !PT ;
LOP3.LUT R13, R13, c[0x3][0x4], RZ, 0x3c, !PT ;
LOP3.LUT R11, R5, c[0x3][0x1c], RZ, 0x3c, !PT ;
LOP3.LUT R6, R6, c[0x3][0xc], RZ, 0x3c, !PT ;
LOP3.LUT R7, R7, c[0x3][0x10], RZ, 0x3c, !PT ;
LOP3.LUT R8, R8, c[0x3][0x14], RZ, 0x3c, !PT ;
LOP3.LUT R9, R9, c[0x3][0x18], RZ, 0x3c, !PT ;
LOP3.LUT R10, R10, c[0x3][0x4], RZ, 0x3c, !PT ;
LOP3.LUT R5, R13, c[0x3][0x0], RZ, 0x3c, !PT ;
LOP3.LUT R11, R11, c[0x3][0x18], RZ, 0x3c, !PT ;
LOP3.LUT R6, R6, c[0x3][0x8], RZ, 0x3c, !PT ;
LOP3.LUT R7, R7, c[0x3][0xc], RZ, 0x3c, !PT ;
LOP3.LUT R8, R8, c[0x3][0x10], RZ, 0x3c, !PT ;
LOP3.LUT R9, R9, c[0x3][0x14], RZ, 0x3c, !PT ;
LOP3.LUT R13, R4, c[0x3][0x1c], RZ, 0x3c, !PT ;
LOP3.LUT R4, R10, c[0x3][0x0], RZ, 0x3c, !PT ;
LOP3.LUT R11, R11, c[0x3][0x14], RZ, 0x3c, !PT ;
LOP3.LUT R10, R5, c[0x3][0x1c], RZ, 0x3c, !PT ;
LOP3.LUT R6, R6, c[0x3][0x4], RZ, 0x3c, !PT ;
LOP3.LUT R7, R7, c[0x3][0x8], RZ, 0x3c, !PT ;
LOP3.LUT R8, R8, c[0x3][0xc], RZ, 0x3c, !PT ;
LOP3.LUT R9, R9, c[0x3][0x10], RZ, 0x3c, !PT ;
LOP3.LUT R13, R13, c[0x3][0x18], RZ, 0x3c, !PT ;
LOP3.LUT R11, R11, c[0x3][0x10], RZ, 0x3c, !PT ;
LOP3.LUT R10, R10, c[0x3][0x18], RZ, 0x3c, !PT ;
LOP3.LUT R5, R6, c[0x3][0x0], RZ, 0x3c, !PT ;
LOP3.LUT R7, R7, c[0x3][0x4], RZ, 0x3c, !PT ;
LOP3.LUT R8, R8, c[0x3][0x8], RZ, 0x3c, !PT ;
LOP3.LUT R9, R9, c[0x3][0xc], RZ, 0x3c, !PT ;
LOP3.LUT R13, R13, c[0x3][0x14], RZ, 0x3c, !PT ;
LOP3.LUT R6, R4, c[0x3][0x1c], RZ, 0x3c, !PT ;
LOP3.LUT R11, R11, c[0x3][0xc], RZ, 0x3c, !PT ;
LOP3.LUT R10, R10, c[0x3][0x14], RZ, 0x3c, !PT ;
LOP3.LUT R4, R7, c[0x3][0x0], RZ, 0x3c, !PT ;
LOP3.LUT R8, R8, c[0x3][0x4], RZ, 0x3c, !PT ;
LOP3.LUT R9, R9, c[0x3][0x8], RZ, 0x3c, !PT ;
LOP3.LUT R13, R13, c[0x3][0x10], RZ, 0x3c, !PT ;
LOP3.LUT R6, R6, c[0x3][0x18], RZ, 0x3c, !PT ;
LOP3.LUT R7, R5, c[0x3][0x1c], RZ, 0x3c, !PT ;
LOP3.LUT R11, R11, c[0x3][0x8], RZ, 0x3c, !PT ;
LOP3.LUT R10, R10, c[0x3][0x10], RZ, 0x3c, !PT ;
LOP3.LUT R5, R8, c[0x3][0x0], RZ, 0x3c, !PT ;
LOP3.LUT R9, R9, c[0x3][0x4], RZ, 0x3c, !PT ;
LOP3.LUT R13, R13, c[0x3][0xc], RZ, 0x3c, !PT ;
LOP3.LUT R6, R6, c[0x3][0x14], RZ, 0x3c, !PT ;
LOP3.LUT R7, R7, c[0x3][0x18], RZ, 0x3c, !PT ;
LOP3.LUT R8, R4, c[0x3][0x1c], RZ, 0x3c, !PT ;
LOP3.LUT R11, R11, c[0x3][0x4], RZ, 0x3c, !PT ;
LOP3.LUT R10, R10, c[0x3][0xc], RZ, 0x3c, !PT ;
LOP3.LUT R4, R9, c[0x3][0x0], RZ, 0x3c, !PT ;
LOP3.LUT R13, R13, c[0x3][0x8], RZ, 0x3c, !PT ;
LOP3.LUT R6, R6, c[0x3][0x10], RZ, 0x3c, !PT ;
LOP3.LUT R7, R7, c[0x3][0x14], RZ, 0x3c, !PT ;
LOP3.LUT R8, R8, c[0x3][0x18], RZ, 0x3c, !PT ;
LOP3.LUT R9, R5, c[0x3][0x1c], RZ, 0x3c, !PT ;
LOP3.LUT R5, R11, c[0x3][0x0], RZ, 0x3c, !PT ;
LOP3.LUT R10, R10, c[0x3][0x8], RZ, 0x3c, !PT ;
LOP3.LUT R13, R13, c[0x3][0x4], RZ, 0x3c, !PT ;
LOP3.LUT R11, R4, c[0x3][0x1c], RZ, 0x3c, !PT ;
LOP3.LUT R6, R6, c[0x3][0xc], RZ, 0x3c, !PT ;
LOP3.LUT R7, R7, c[0x3][0x10], RZ, 0x3c, !PT ;
LOP3.LUT R8, R8, c[0x3][0x14], RZ, 0x3c, !PT ;
LOP3.LUT R9, R9, c[0x3][0x18], RZ, 0x3c, !PT ;
IADD3 R12, R12, 0x24, RZ ;
LOP3.LUT R10, R10, c[0x3][0x4], RZ, 0x3c, !PT ;
LOP3.LUT R4, R13, c[0x3][0x0], RZ, 0x3c, !PT ;
LOP3.LUT R11, R11, c[0x3][0x18], RZ, 0x3c, !PT ;
LOP3.LUT R6, R6, c[0x3][0x8], RZ, 0x3c, !PT ;
LOP3.LUT R7, R7, c[0x3][0xc], RZ, 0x3c, !PT ;
LOP3.LUT R8, R8, c[0x3][0x10], RZ, 0x3c, !PT ;
LOP3.LUT R9, R9, c[0x3][0x14], RZ, 0x3c, !PT ;
LOP3.LUT R13, R5, c[0x3][0x1c], RZ, 0x3c, !PT ;
ISETP.NE.AND P1, PT, R12, 0x100, PT ;
LOP3.LUT R5, R10, c[0x3][0x0], RZ, 0x3c, !PT ;
LOP3.LUT R11, R11, c[0x3][0x14], RZ, 0x3c, !PT ;
LOP3.LUT R10, R4, c[0x3][0x1c], RZ, 0x3c, !PT ;
LOP3.LUT R6, R6, c[0x3][0x4], RZ, 0x3c, !PT ;
LOP3.LUT R7, R7, c[0x3][0x8], RZ, 0x3c, !PT ;
LOP3.LUT R8, R8, c[0x3][0xc], RZ, 0x3c, !PT ;
LOP3.LUT R9, R9, c[0x3][0x10], RZ, 0x3c, !PT ;
LOP3.LUT R13, R13, c[0x3][0x18], RZ, 0x3c, !PT ;
LOP3.LUT R11, R11, c[0x3][0x10], RZ, 0x3c, !PT ;
LOP3.LUT R10, R10, c[0x3][0x18], RZ, 0x3c, !PT ;
LOP3.LUT R4, R6, c[0x3][0x0], RZ, 0x3c, !PT ;
LOP3.LUT R7, R7, c[0x3][0x4], RZ, 0x3c, !PT ;
LOP3.LUT R8, R8, c[0x3][0x8], RZ, 0x3c, !PT ;
LOP3.LUT R9, R9, c[0x3][0xc], RZ, 0x3c, !PT ;
LOP3.LUT R13, R13, c[0x3][0x14], RZ, 0x3c, !PT ;
LOP3.LUT R5, R5, c[0x3][0x1c], RZ, 0x3c, !PT ;
LOP3.LUT R11, R11, c[0x3][0xc], RZ, 0x3c, !PT ;
LOP3.LUT R6, R10, c[0x3][0x14], RZ, 0x3c, !PT ;
LOP3.LUT R7, R7, c[0x3][0x0], RZ, 0x3c, !PT ;
LOP3.LUT R8, R8, c[0x3][0x4], RZ, 0x3c, !PT ;
LOP3.LUT R9, R9, c[0x3][0x8], RZ, 0x3c, !PT ;
LOP3.LUT R13, R13, c[0x3][0x10], RZ, 0x3c, !PT ;
LOP3.LUT R5, R5, c[0x3][0x18], RZ, 0x3c, !PT ;
LOP3.LUT R14, R4, c[0x3][0x1c], RZ, 0x3c, !PT ;
LOP3.LUT R10, R11, c[0x3][0x8], RZ, 0x3c, !PT ;
LOP3.LUT R4, R6, c[0x3][0x10], RZ, 0x3c, !PT ;
LOP3.LUT R8, R8, c[0x3][0x0], RZ, 0x3c, !PT ;
LOP3.LUT R9, R9, c[0x3][0x4], RZ, 0x3c, !PT ;
LOP3.LUT R11, R13, c[0x3][0xc], RZ, 0x3c, !PT ;
LOP3.LUT R5, R5, c[0x3][0x14], RZ, 0x3c, !PT ;
LOP3.LUT R6, R14, c[0x3][0x18], RZ, 0x3c, !PT ;
LOP3.LUT R7, R7, c[0x3][0x1c], RZ, 0x3c, !PT ;
@!P1 CALL.REL.NOINC 0x1670 ;
BRA 0x430 ;
IMAD.MOV.U32 R24, RZ, RZ, 0xff ;
STS.128 [R0+0x20], R8 ;
IMAD.MOV.U32 R12, RZ, RZ, R9 ;
VOTEU.ANY UR7, UPT, PT ;
IMAD.MOV.U32 R13, RZ, RZ, R10 ;
SHF.L.U32 R24, R24, R3, RZ ;
IMAD.MOV.U32 R14, RZ, RZ, R11 ;
STS.128 [R0+0x30], R4 ;
IMAD.MOV.U32 R15, RZ, RZ, R4 ;
MATCH.ANY R25, R24 ;
REDUX.OR UR6, R24 ;
IMAD.MOV.U32 R16, RZ, RZ, R5 ;
STG.E [R20.64], R9 ;
IMAD.MOV.U32 R17, RZ, RZ, R6 ;
IMAD.MOV.U32 R18, RZ, RZ, R7 ;
STG.E [R20.64+0x4], R10 ;
IMAD.MOV.U32 R19, RZ, RZ, R8 ;
STG.E [R20.64+0x8], R11 ;
STG.E [R20.64+0xc], R4 ;
STG.E [R20.64+0x10], R5 ;
STG.E [R20.64+0x14], R6 ;
LOP3.LUT P1, RZ, R24, UR7, R25, 0x40, !PT ;
STG.E [R20.64+0x18], R7 ;
STG.E [R20.64+0x1c], R8 ;
STS.128 [R0], R12 ;
STS.128 [R0+0x10], R16 ;
@!P1 BRA.CONV UR6, 0x1840 ;
MOV R4, 0x1840 ;
CALL.REL.NOINC 0x1920 ;
NOP ;
@P0 CALL.REL.NOINC 0x1870 ;
BRA 0x160 ;
LDS.128 R4, [R0] ;
LDS.128 R8, [R0+0x10] ;
STG.E [R22.64], R4 ;
STG.E [R22.64+0x4], R5 ;
STG.E [R22.64+0x8], R6 ;
STG.E [R22.64+0xc], R7 ;
STG.E [R22.64+0x10], R8 ;
STG.E [R22.64+0x14], R9 ;
STG.E [R22.64+0x18], R10 ;
STG.E [R22.64+0x1c], R11 ;
EXIT ;
IMAD.MOV.U32 R5, RZ, RZ, 0x0 ;
WARPSYNC R24 ;
RET.REL.NODEC R4 0x0 ;
BRA 0x1950;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
```
|
```amdasm
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z13argon2_kernelPji ; -- Begin function _Z13argon2_kernelPji
.globl _Z13argon2_kernelPji
.p2align 8
.type _Z13argon2_kernelPji,@function
_Z13argon2_kernelPji: ; @_Z13argon2_kernelPji
; %bb.0:
s_load_b64 s[0:1], s[0:1], 0x0
v_lshlrev_b32_e32 v7, 5, v0
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v1, s2, s0, v7
v_add_co_ci_u32_e64 v2, null, s1, 0, s2
s_mov_b32 s2, 0
s_delay_alu instid0(VALU_DEP_1)
v_dual_mov_b32 v4, v2 :: v_dual_mov_b32 v3, v1
.LBB0_1: ; =>This Inner Loop Header: Depth=1
global_load_b32 v5, v[3:4], off
v_add_co_u32 v3, vcc_lo, v3, 4
v_add_nc_u32_e32 v6, s2, v7
v_add_co_ci_u32_e32 v4, vcc_lo, 0, v4, vcc_lo
s_add_i32 s2, s2, 4
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s2, 32
s_waitcnt vmcnt(0)
ds_store_b32 v6, v5
s_cbranch_scc0 .LBB0_1
; %bb.2: ; %.preheader60
v_and_b32_e32 v0, 7, v0
s_mov_b32 s2, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b32_e32 v3, 5, v0
v_add_nc_u32_e32 v0, 32, v7
v_add_co_u32 v3, s0, s0, v3
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v4, null, s1, 0, s0
.LBB0_3: ; =>This Loop Header: Depth=1
; Child Loop BB0_4 Depth 2
; Child Loop BB0_6 Depth 2
; Child Loop BB0_7 Depth 3
; Child Loop BB0_9 Depth 3
; Child Loop BB0_12 Depth 2
s_delay_alu instid0(VALU_DEP_1)
v_dual_mov_b32 v6, v4 :: v_dual_mov_b32 v5, v3
s_mov_b32 s0, 0
.LBB0_4: ; Parent Loop BB0_3 Depth=1
; => This Inner Loop Header: Depth=2
global_load_b32 v8, v[5:6], off
v_add_co_u32 v5, vcc_lo, v5, 4
v_add_nc_u32_e32 v9, s0, v7
v_add_co_ci_u32_e32 v6, vcc_lo, 0, v6, vcc_lo
s_add_i32 s0, s0, 4
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_lg_u32 s0, 32
s_waitcnt vmcnt(0)
ds_store_b32 v9, v8
s_cbranch_scc1 .LBB0_4
; %bb.5: ; %.preheader35.i.preheader
; in Loop: Header=BB0_3 Depth=1
s_mov_b32 s3, 0
.LBB0_6: ; %.preheader35.i
; Parent Loop BB0_3 Depth=1
; => This Loop Header: Depth=2
; Child Loop BB0_7 Depth 3
; Child Loop BB0_9 Depth 3
v_mov_b32_e32 v5, v7
s_mov_b64 s[0:1], 0
.LBB0_7: ; Parent Loop BB0_3 Depth=1
; Parent Loop BB0_6 Depth=2
; => This Inner Loop Header: Depth=3
s_getpc_b64 s[4:5]
s_add_u32 s4, s4, const_block@rel32@lo+4
s_addc_u32 s5, s5, const_block@rel32@hi+12
s_add_u32 s4, s0, s4
s_addc_u32 s5, s1, s5
ds_load_b32 v6, v5
s_load_b32 s4, s[4:5], 0x0
s_add_u32 s0, s0, 4
s_addc_u32 s1, s1, 0
s_cmp_lg_u32 s0, 32
s_waitcnt lgkmcnt(0)
v_xor_b32_e32 v6, s4, v6
ds_store_b32 v5, v6 offset:32
v_add_nc_u32_e32 v5, 4, v5
s_cbranch_scc1 .LBB0_7
; %bb.8: ; %.preheader34.i.preheader
; in Loop: Header=BB0_6 Depth=2
v_mov_b32_e32 v5, v7
s_mov_b32 s0, 1
.LBB0_9: ; %.preheader34.i
; Parent Loop BB0_3 Depth=1
; Parent Loop BB0_6 Depth=2
; => This Inner Loop Header: Depth=3
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 s1, s0, 7
s_add_i32 s0, s0, 1
v_lshl_add_u32 v6, s1, 2, v0
s_cmp_eq_u32 s0, 9
ds_load_b32 v6, v6
s_waitcnt lgkmcnt(0)
ds_store_b32 v5, v6
v_add_nc_u32_e32 v5, 4, v5
s_cbranch_scc0 .LBB0_9
; %bb.10: ; in Loop: Header=BB0_6 Depth=2
s_add_i32 s3, s3, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmpk_lg_i32 s3, 0x100
s_cbranch_scc1 .LBB0_6
; %bb.11: ; %.preheader.i.preheader
; in Loop: Header=BB0_3 Depth=1
v_dual_mov_b32 v6, v4 :: v_dual_mov_b32 v5, v3
s_mov_b32 s0, 0
.LBB0_12: ; %.preheader.i
; Parent Loop BB0_3 Depth=1
; => This Inner Loop Header: Depth=2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_add_nc_u32_e32 v8, s0, v7
s_add_i32 s0, s0, 4
s_cmp_lg_u32 s0, 32
ds_load_b32 v8, v8
s_waitcnt lgkmcnt(0)
global_store_b32 v[5:6], v8, off
v_add_co_u32 v5, vcc_lo, v5, 4
v_add_co_ci_u32_e32 v6, vcc_lo, 0, v6, vcc_lo
s_cbranch_scc1 .LBB0_12
; %bb.13: ; %_Z8blockmixPjS_i.exit
; in Loop: Header=BB0_3 Depth=1
s_add_i32 s2, s2, 1
s_waitcnt_vscnt null, 0x0
buffer_gl1_inv
buffer_gl0_inv
s_cmp_lg_u32 s2, 3
s_cbranch_scc1 .LBB0_3
; %bb.14: ; %.preheader.preheader
s_mov_b32 s0, 0
.LBB0_15: ; %.preheader
; =>This Inner Loop Header: Depth=1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_add_nc_u32_e32 v0, s0, v7
s_add_i32 s0, s0, 4
s_cmp_eq_u32 s0, 32
ds_load_b32 v0, v0
s_waitcnt lgkmcnt(0)
global_store_b32 v[1:2], v0, off
v_add_co_u32 v1, vcc_lo, v1, 4
v_add_co_ci_u32_e32 v2, vcc_lo, 0, v2, vcc_lo
s_cbranch_scc0 .LBB0_15
; %bb.16:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13argon2_kernelPji
.amdhsa_group_segment_fixed_size 1024
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 12
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 10
.amdhsa_next_free_sgpr 6
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z13argon2_kernelPji, .Lfunc_end0-_Z13argon2_kernelPji
; -- End function
.section .AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 544
; NumSgprs: 8
; NumVgprs: 10
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 1024 bytes/workgroup (compile time only)
; SGPRBlocks: 0
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 8
; NumVGPRsForWavesPerEU: 10
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.protected const_block ; @const_block
.type const_block,@object
.section .bss,"aw",@nobits
.globl const_block
.p2align 4, 0x0
const_block:
.zero 32
.size const_block, 32
.type __hip_cuid_,@object ; @__hip_cuid_
.globl __hip_cuid_
__hip_cuid_:
.byte 0 ; 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym const_block
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 1024
.kernarg_segment_align: 8
.kernarg_segment_size: 12
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13argon2_kernelPji
.private_segment_fixed_size: 0
.sgpr_count: 8
.sgpr_spill_count: 0
.symbol: _Z13argon2_kernelPji.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 10
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
```
| 12,582 | 3,847 |
113,685 |
Convert the following CUDA host assembly code to AMD host assembly:
```cudaasm
.file "tmpxft_0002c1ca_00000000-6_cuda_code_025065.cudafe1.cpp"
.text
.globl _ZSt21ios_base_library_initv
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB6836:
.cfi_startproc
endbr64
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
jmp __cudaUnregisterFatBinary@PLT
.cfi_endproc
.LFE6836:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.align 2
.type _ZNSolsEPFRSoS_E.isra.0, @function
_ZNSolsEPFRSoS_E.isra.0:
.LFB7720:
.cfi_startproc
jmp *%rsi
.cfi_endproc
.LFE7720:
.size _ZNSolsEPFRSoS_E.isra.0, .-_ZNSolsEPFRSoS_E.isra.0
.globl _Z8blockmixPjS_i
.type _Z8blockmixPjS_i, @function
_Z8blockmixPjS_i:
.LFB6832:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE6832:
.size _Z8blockmixPjS_i, .-_Z8blockmixPjS_i
.globl _Z34__device_stub__Z13argon2_kernelPjiPji
.type _Z34__device_stub__Z13argon2_kernelPjiPji, @function
_Z34__device_stub__Z13argon2_kernelPjiPji:
.LFB6858:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
leaq 32(%rsp), %rcx
leaq 24(%rsp), %rdx
movl %esi, 4(%rsp)
leaq 40(%rsp), %rdi
leaq 52(%rsp), %rsi
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movl $1, 48(%rsp)
movq %rax, 88(%rsp)
leaq 4(%rsp), %rax
movq %rax, 96(%rsp)
movabsq $4294967297, %rax
movq %rax, 40(%rsp)
movq %rax, 52(%rsp)
movl $1, 60(%rsp)
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
jne .L5
pushq 32(%rsp)
.cfi_def_cfa_offset 136
leaq _Z13argon2_kernelPji(%rip), %rdi
pushq 32(%rsp)
.cfi_def_cfa_offset 144
movq 68(%rsp), %rcx
movl 76(%rsp), %r8d
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
leaq 104(%rsp), %r9
call cudaLaunchKernel@PLT
popq %rax
.cfi_def_cfa_offset 136
popq %rdx
.cfi_def_cfa_offset 128
.L5:
movq 104(%rsp), %rax
subq %fs:40, %rax
je .L7
call __stack_chk_fail@PLT
.L7:
addq $120, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE6858:
.size _Z34__device_stub__Z13argon2_kernelPjiPji, .-_Z34__device_stub__Z13argon2_kernelPjiPji
.globl _Z13argon2_kernelPji
.type _Z13argon2_kernelPji, @function
_Z13argon2_kernelPji:
.LFB6859:
.cfi_startproc
endbr64
jmp _Z34__device_stub__Z13argon2_kernelPjiPji
.cfi_endproc
.LFE6859:
.size _Z13argon2_kernelPji, .-_Z13argon2_kernelPji
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "CUDA error: "
.section .text.startup,"ax",@progbits
.globl main
.type main, @function
main:
.LFB6833:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
movl $1024, %edi
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $88, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
call _Znam@PLT
movl $256, %ecx
movl $1024, %esi
movq %rax, %rbx
xorl %eax, %eax
movq %rbx, %rdi
rep stosl
leaq 8(%rsp), %rdi
call cudaMalloc@PLT
movl %eax, %ebp
testl %eax, %eax
jne .L22
movq 8(%rsp), %rdi
movl $1, %ecx
movl $1024, %edx
movq %rbx, %rsi
call cudaMemcpy@PLT
movl %eax, %ebp
testl %eax, %eax
je .L14
.L22:
leaq .LC0(%rip), %rsi
leaq _ZSt4cerr(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movl %ebp, %edi
movq %rax, %rbx
call cudaGetErrorString@PLT
movq %rbx, %rdi
movq %rax, %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@GOTPCREL(%rip), %rsi
movq %rax, %rdi
call _ZNSolsEPFRSoS_E.isra.0
orl $-1, %eax
jmp .L11
.L14:
leaq 40(%rsp), %rsi
movl $1, %r8d
xorl %ecx, %ecx
movl $32, %edx
movabsq $-3819410105021120785, %rax
leaq _ZL11const_block(%rip), %rdi
movq %rax, 40(%rsp)
movabsq $1384787474431998670, %rax
movq %rax, 48(%rsp)
movabsq $-8526495043095935641, %rax
movq %rax, 56(%rsp)
movabsq $8526495043095935640, %rax
movq %rax, 64(%rsp)
call cudaMemcpyToSymbol@PLT
movl %eax, %ebp
testl %eax, %eax
jne .L22
movl $16777217, %edx
xorl %r9d, %r9d
xorl %r8d, %r8d
movl $1, %ecx
salq $8, %rdx
movl $1, %esi
movabsq $4294967297, %rdi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L17
movq 8(%rsp), %rdi
movl $32, %esi
call _Z34__device_stub__Z13argon2_kernelPjiPji
.L17:
call cudaGetLastError@PLT
movl %eax, %ebp
testl %eax, %eax
jne .L22
movq 8(%rsp), %rsi
movl $2, %ecx
movl $1024, %edx
movq %rbx, %rdi
call cudaMemcpy@PLT
movl %eax, %ebp
testl %eax, %eax
jne .L22
movq 8(%rsp), %rdi
call cudaFree@PLT
movq %rbx, %rdi
call _ZdaPv@PLT
xorl %eax, %eax
.L11:
movq 72(%rsp), %rdx
subq %fs:40, %rdx
je .L20
call __stack_chk_fail@PLT
.L20:
addq $88, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE6833:
.size main, .-main
.section .rodata.str1.1
.LC1:
.string "_Z13argon2_kernelPji"
.LC2:
.string "const_block"
.LC3:
.string "_ZN50_INTERNAL_4498f2e1_19_cuda_code_025065_cu_06a248174cuda3std3__419piecewise_constructE"
.LC4:
.string "_ZN50_INTERNAL_4498f2e1_19_cuda_code_025065_cu_06a248174cuda3std6ranges3__45__cpo4swapE"
.LC5:
.string "_ZN50_INTERNAL_4498f2e1_19_cuda_code_025065_cu_06a248174cuda3std6ranges3__45__cpo9iter_moveE"
.section .text.startup
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB6861:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
pushq $0
.cfi_def_cfa_offset 24
xorl %r9d, %r9d
orl $-1, %r8d
pushq $0
.cfi_def_cfa_offset 32
leaq .LC1(%rip), %rdx
movq %rax, %rdi
movq %rax, %rbx
pushq $0
.cfi_def_cfa_offset 40
movq %rdx, %rcx
leaq _Z13argon2_kernelPji(%rip), %rsi
pushq $0
.cfi_def_cfa_offset 48
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq %rbx, %rdi
xorl %r8d, %r8d
pushq $0
.cfi_def_cfa_offset 24
leaq .LC2(%rip), %rdx
movl $32, %r9d
leaq _ZL11const_block(%rip), %rsi
pushq $1
.cfi_def_cfa_offset 32
movq %rdx, %rcx
call __cudaRegisterVar@PLT
popq %rax
.cfi_def_cfa_offset 24
popq %rdx
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
leaq .LC3(%rip), %rdx
movq %rbx, %rdi
xorl %r8d, %r8d
movq %rdx, %rcx
movl $1, %r9d
leaq _ZN4cuda3std3__419piecewise_constructE(%rip), %rsi
call __cudaRegisterVar@PLT
popq %rcx
.cfi_def_cfa_offset 24
popq %rsi
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
leaq .LC4(%rip), %rdx
movq %rbx, %rdi
xorl %r8d, %r8d
movq %rdx, %rcx
movl $1, %r9d
leaq _ZN4cuda3std6ranges3__45__cpo4swapE(%rip), %rsi
call __cudaRegisterVar@PLT
popq %rdi
.cfi_def_cfa_offset 24
popq %r8
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
leaq .LC5(%rip), %rdx
movq %rbx, %rdi
xorl %r8d, %r8d
movl $1, %r9d
movq %rdx, %rcx
leaq _ZN4cuda3std6ranges3__45__cpo9iter_moveE(%rip), %rsi
call __cudaRegisterVar@PLT
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
popq %r9
.cfi_def_cfa_offset 24
popq %r10
.cfi_def_cfa_offset 16
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit@PLT
.cfi_endproc
.LFE6861:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZL11const_block
.comm _ZL11const_block,32,32
.weak _ZN4cuda3std3__419piecewise_constructE
.section .rodata._ZN4cuda3std3__419piecewise_constructE,"aG",@progbits,_ZN4cuda3std3__419piecewise_constructE,comdat
.type _ZN4cuda3std3__419piecewise_constructE, @gnu_unique_object
.size _ZN4cuda3std3__419piecewise_constructE, 1
_ZN4cuda3std3__419piecewise_constructE:
.zero 1
.weak _ZN4cuda3std6ranges3__45__cpo9iter_moveE
.section .rodata._ZN4cuda3std6ranges3__45__cpo9iter_moveE,"aG",@progbits,_ZN4cuda3std6ranges3__45__cpo9iter_moveE,comdat
.type _ZN4cuda3std6ranges3__45__cpo9iter_moveE, @gnu_unique_object
.size _ZN4cuda3std6ranges3__45__cpo9iter_moveE, 1
_ZN4cuda3std6ranges3__45__cpo9iter_moveE:
.zero 1
.weak _ZN4cuda3std6ranges3__45__cpo4swapE
.section .rodata._ZN4cuda3std6ranges3__45__cpo4swapE,"aG",@progbits,_ZN4cuda3std6ranges3__45__cpo4swapE,comdat
.type _ZN4cuda3std6ranges3__45__cpo4swapE, @gnu_unique_object
.size _ZN4cuda3std6ranges3__45__cpo4swapE, 1
_ZN4cuda3std6ranges3__45__cpo4swapE:
.zero 1
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
```
|
```amdasm
.text
.file "cuda_code_025065.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z28__device_stub__argon2_kernelPji # -- Begin function _Z28__device_stub__argon2_kernelPji
.type _Z28__device_stub__argon2_kernelPji,@function
_Z28__device_stub__argon2_kernelPji: # @_Z28__device_stub__argon2_kernelPji
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $80, %rsp
.cfi_def_cfa_offset 128
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 24(%rsp), %rax
movq %rdi, (%rax)
leaq 4(%rsp), %rcx
movl %esi, (%rcx)
leaq 64(%rsp), %rbx
movq %rax, (%rbx)
movq %rcx, 8(%rbx)
leaq 48(%rsp), %r14
leaq 32(%rsp), %r15
leaq 16(%rsp), %r12
leaq 8(%rsp), %r13
movq %r14, %rdi
movq %r15, %rsi
movq %r12, %rdx
movq %r13, %rcx
callq __hipPopCallConfiguration
movq (%r14), %rsi
movl 8(%r14), %edx
movq (%r15), %rcx
movl 8(%r15), %r8d
movl $_Z13argon2_kernelPji, %edi
movq %rbx, %r9
pushq (%r13)
.cfi_adjust_cfa_offset 8
pushq (%r12)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $96, %rsp
.cfi_adjust_cfa_offset -96
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z28__device_stub__argon2_kernelPji, .Lfunc_end0-_Z28__device_stub__argon2_kernelPji
.cfi_endproc
# -- End function
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0 # -- Begin function main
.LCPI1_0:
.long 3735928559 # 0xdeadbeef
.long 3405691582 # 0xcafebabe
.long 4277009102 # 0xfeedface
.long 322420958 # 0x1337c0de
.LCPI1_1:
.long 19088743 # 0x1234567
.long 2309737967 # 0x89abcdef
.long 4275878552 # 0xfedcba98
.long 1985229328 # 0x76543210
.text
.globl main
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $56, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -24
.cfi_offset %rbp, -16
movl $1024, %edi # imm = 0x400
callq _Znam
movq %rax, %rbx
movl $1024, %edx # imm = 0x400
movq %rax, %rdi
xorl %esi, %esi
callq memset@PLT
leaq 8(%rsp), %rdi
movl $1024, %esi # imm = 0x400
callq hipMalloc
testl %eax, %eax
jne .LBB1_6
# %bb.1:
movq 8(%rsp), %rdi
movl $1024, %edx # imm = 0x400
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB1_6
# %bb.2:
movaps .LCPI1_0(%rip), %xmm0 # xmm0 = [3735928559,3405691582,4277009102,322420958]
leaq 16(%rsp), %rsi
movaps %xmm0, (%rsi)
movaps .LCPI1_1(%rip), %xmm0 # xmm0 = [19088743,2309737967,4275878552,1985229328]
movaps %xmm0, 16(%rsi)
movl $const_block, %edi
movl $32, %edx
xorl %ecx, %ecx
movl $1, %r8d
callq hipMemcpyToSymbol
testl %eax, %eax
jne .LBB1_6
# %bb.3:
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 255(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_5
# %bb.4:
movq 8(%rsp), %rdi
movl $32, %esi
callq _Z28__device_stub__argon2_kernelPji
.LBB1_5:
callq hipGetLastError
testl %eax, %eax
je .LBB1_12
.LBB1_6:
movl %eax, %ebp
movl $_ZSt4cerr, %edi
movl $.L.str, %esi
movl $12, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl %ebp, %edi
callq hipGetErrorString
testq %rax, %rax
je .LBB1_8
# %bb.7:
movq %rax, %rbx
movq %rax, %rdi
callq strlen
movl $_ZSt4cerr, %edi
movq %rbx, %rsi
movq %rax, %rdx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
jmp .LBB1_9
.LBB1_8:
movq _ZSt4cerr(%rip), %rax
movq -24(%rax), %rax
leaq _ZSt4cerr(%rax), %rdi
movl 32(%rdi), %esi
orl $1, %esi
callq _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate
.LBB1_9: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit
movq _ZSt4cerr(%rip), %rax
movl $_ZSt4cerr, %ecx
movq -24(%rax), %rdi
addq %rcx, %rdi
movl $10, %esi
callq _ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
movsbl %al, %esi
movl $_ZSt4cerr, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
.LBB1_10:
movl $-1, %eax
.LBB1_11:
addq $56, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB1_12:
.cfi_def_cfa_offset 80
movq 8(%rsp), %rsi
movl $1024, %edx # imm = 0x400
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
je .LBB1_14
# %bb.13:
movl %eax, %ebp
movl $_ZSt4cerr, %edi
movl $.L.str, %esi
movl $12, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl %ebp, %edi
callq hipGetErrorString
movl $_ZSt4cerr, %edi
movq %rax, %rsi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movq %rax, %rdi
callq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_
jmp .LBB1_10
.LBB1_14:
movq 8(%rsp), %rdi
callq hipFree
movq %rbx, %rdi
callq _ZdaPv
xorl %eax, %eax
jmp .LBB1_11
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
movq __hip_gpubin_handle(%rip), %rbx
testq %rbx, %rbx
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, %rbx
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13argon2_kernelPji, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $0, 8(%rsp)
movl $1, (%rsp)
movl $const_block, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movl $32, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
callq __hipRegisterVar
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type const_block,@object # @const_block
.local const_block
.comm const_block,32,16
.type _Z13argon2_kernelPji,@object # @_Z13argon2_kernelPji
.section .rodata,"a",@progbits
.globl _Z13argon2_kernelPji
.p2align 3, 0x0
_Z13argon2_kernelPji:
.quad _Z28__device_stub__argon2_kernelPji
.size _Z13argon2_kernelPji, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "CUDA error: "
.size .L.str, 13
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z13argon2_kernelPji"
.size .L__unnamed_1, 21
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "const_block"
.size .L__unnamed_2, 12
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z28__device_stub__argon2_kernelPji
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym const_block
.addrsig_sym _Z13argon2_kernelPji
.addrsig_sym _ZSt4cerr
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
```
| 4,655 | 4,293 |
113,688 |
Convert the following CUDA device assembly code to AMD device assembly:
```cudaasm
code for sm_80
Function : _Z17gaborFilterKernelPKfPfii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
MOV R1, c[0x0][0x28] ;
S2R R6, SR_TID.Y ;
ULDC.64 UR4, c[0x0][0x118] ;
BSSY B0, 0x2a0 ;
S2R R3, SR_CTAID.Y ;
S2R R0, SR_CTAID.X ;
S2R R9, SR_TID.X ;
ISETP.GT.AND P0, PT, R6, 0x17, PT ;
LEA R3, R3, R6, 0x4 ;
LEA R0, R0, R9, 0x4 ;
@P0 BRA 0x290 ;
MOV R2, R6 ;
ISETP.GT.AND P0, PT, R9, 0x17, PT ;
BSSY B1, 0x260 ;
@P0 BRA 0x250 ;
IADD3 R4, R3, R2, RZ ;
MOV R7, R9 ;
IADD3 R8, R4, -0x4, RZ ;
ISETP.GE.AND P0, PT, R8, c[0x0][0x174], PT ;
ISETP.GT.AND P0, PT, R4, 0x3, !P0 ;
IADD3 R4, R0, R7, RZ ;
BSSY B2, 0x210 ;
IMAD R11, R2, 0x18, R7 ;
ISETP.LT.OR P1, PT, R4.reuse, 0x4, !P0 ;
IADD3 R13, R4, -0x4, RZ ;
HFMA2.MMA R4, -RZ, RZ, 0, 0 ;
ISETP.GE.OR P1, PT, R13, c[0x0][0x170], P1 ;
@P1 BRA 0x200 ;
MOV R5, 0x4 ;
IMAD R4, R8, c[0x0][0x170], R13 ;
IMAD.WIDE R4, R4, R5, c[0x0][0x160] ;
LDG.E R4, [R4.64] ;
BSYNC B2 ;
STS [R11.X4], R4 ;
IADD3 R7, R7, c[0x0][0x0], RZ ;
ISETP.GE.AND P1, PT, R7, 0x18, PT ;
@!P1 BRA 0x140 ;
BSYNC B1 ;
IADD3 R2, R2, c[0x0][0x4], RZ ;
ISETP.GE.AND P0, PT, R2, 0x18, PT ;
@!P0 BRA 0xc0 ;
BSYNC B0 ;
BAR.SYNC.DEFER_BLOCKING 0x0 ;
ISETP.GE.AND P0, PT, R3, c[0x0][0x174], PT ;
ISETP.GE.OR P0, PT, R0, c[0x0][0x170], P0 ;
@P0 EXIT ;
IMAD R2, R6, 0x18, R9 ;
IMAD R3, R3, c[0x0][0x170], R0 ;
LDS R6, [R2.X4] ;
LDS R7, [R2.X4+0x4] ;
LDS R8, [R2.X4+0x8] ;
LDS R9, [R2.X4+0xc] ;
LDS R10, [R2.X4+0x10] ;
LDS R11, [R2.X4+0x14] ;
LDS R12, [R2.X4+0x18] ;
LDS R13, [R2.X4+0x1c] ;
LDS R14, [R2.X4+0x20] ;
LDS R5, [R2.X4+0x60] ;
FFMA R6, R6, c[0x3][0x0], RZ ;
LDS R4, [R2.X4+0x64] ;
FFMA R7, R7, c[0x3][0x4], R6 ;
LDS R16, [R2.X4+0x2a0] ;
FFMA R8, R8, c[0x3][0x8], R7 ;
LDS R6, [R2.X4+0x68] ;
FFMA R9, R9, c[0x3][0xc], R8 ;
LDS R7, [R2.X4+0x6c] ;
FFMA R10, R10, c[0x3][0x10], R9 ;
LDS R8, [R2.X4+0x70] ;
FFMA R11, R11, c[0x3][0x14], R10 ;
LDS R9, [R2.X4+0x74] ;
FFMA R12, R12, c[0x3][0x18], R11 ;
LDS R10, [R2.X4+0x78] ;
FFMA R13, R13, c[0x3][0x1c], R12 ;
LDS R11, [R2.X4+0x7c] ;
FFMA R14, R14, c[0x3][0x20], R13 ;
LDS R12, [R2.X4+0x80] ;
FFMA R15, R5, c[0x3][0x24], R14 ;
LDS R13, [R2.X4+0xc0] ;
LDS R5, [R2.X4+0xc4] ;
FFMA R15, R4, c[0x3][0x28], R15 ;
LDS R4, [R2.X4+0xc8] ;
FFMA R14, R6, c[0x3][0x2c], R15 ;
LDS R17, [R2.X4+0x318] ;
FFMA R15, R7, c[0x3][0x30], R14 ;
LDS R6, [R2.X4+0xcc] ;
FFMA R14, R8, c[0x3][0x34], R15 ;
LDS R7, [R2.X4+0xd0] ;
FFMA R15, R9, c[0x3][0x38], R14 ;
LDS R8, [R2.X4+0xd4] ;
FFMA R14, R10, c[0x3][0x3c], R15 ;
LDS R9, [R2.X4+0xd8] ;
FFMA R15, R11, c[0x3][0x40], R14 ;
LDS R10, [R2.X4+0xdc] ;
FFMA R14, R12, c[0x3][0x44], R15 ;
LDS R11, [R2.X4+0xe0] ;
FFMA R14, R13, c[0x3][0x48], R14 ;
LDS R12, [R2.X4+0x120] ;
FFMA R15, R5, c[0x3][0x4c], R14 ;
LDS R13, [R2.X4+0x124] ;
FFMA R15, R4, c[0x3][0x50], R15 ;
LDS R5, [R2.X4+0x128] ;
LDS R4, [R2.X4+0x12c] ;
FFMA R14, R6, c[0x3][0x54], R15 ;
LDS R19, [R2.X4+0x31c] ;
FFMA R15, R7, c[0x3][0x58], R14 ;
LDS R6, [R2.X4+0x130] ;
FFMA R14, R8, c[0x3][0x5c], R15 ;
LDS R7, [R2.X4+0x134] ;
FFMA R15, R9, c[0x3][0x60], R14 ;
LDS R8, [R2.X4+0x138] ;
FFMA R14, R10, c[0x3][0x64], R15 ;
LDS R9, [R2.X4+0x13c] ;
FFMA R15, R11, c[0x3][0x68], R14 ;
LDS R10, [R2.X4+0x140] ;
FFMA R14, R12, c[0x3][0x6c], R15 ;
LDS R11, [R2.X4+0x180] ;
FFMA R14, R13, c[0x3][0x70], R14 ;
LDS R12, [R2.X4+0x184] ;
FFMA R15, R5, c[0x3][0x74], R14 ;
LDS R13, [R2.X4+0x188] ;
FFMA R15, R4, c[0x3][0x78], R15 ;
LDS R5, [R2.X4+0x18c] ;
LDS R4, [R2.X4+0x190] ;
FFMA R14, R6, c[0x3][0x7c], R15 ;
LDS R21, [R2.X4+0x320] ;
FFMA R15, R7, c[0x3][0x80], R14 ;
LDS R6, [R2.X4+0x194] ;
FFMA R14, R8, c[0x3][0x84], R15 ;
LDS R7, [R2.X4+0x198] ;
FFMA R15, R9, c[0x3][0x88], R14 ;
LDS R8, [R2.X4+0x19c] ;
FFMA R14, R10, c[0x3][0x8c], R15 ;
LDS R9, [R2.X4+0x1a0] ;
FFMA R15, R11, c[0x3][0x90], R14 ;
LDS R10, [R2.X4+0x1e0] ;
FFMA R14, R12, c[0x3][0x94], R15 ;
LDS R11, [R2.X4+0x1e4] ;
FFMA R14, R13, c[0x3][0x98], R14 ;
LDS R12, [R2.X4+0x1e8] ;
FFMA R15, R5, c[0x3][0x9c], R14 ;
LDS R13, [R2.X4+0x1ec] ;
FFMA R15, R4, c[0x3][0xa0], R15 ;
LDS R5, [R2.X4+0x1f0] ;
LDS R4, [R2.X4+0x1f4] ;
FFMA R14, R6, c[0x3][0xa4], R15 ;
LDS R6, [R2.X4+0x1f8] ;
FFMA R15, R7, c[0x3][0xa8], R14 ;
LDS R7, [R2.X4+0x1fc] ;
FFMA R14, R8, c[0x3][0xac], R15 ;
LDS R8, [R2.X4+0x200] ;
FFMA R15, R9, c[0x3][0xb0], R14 ;
LDS R9, [R2.X4+0x240] ;
FFMA R14, R10, c[0x3][0xb4], R15 ;
LDS R10, [R2.X4+0x244] ;
FFMA R15, R11, c[0x3][0xb8], R14 ;
LDS R11, [R2.X4+0x248] ;
FFMA R14, R12, c[0x3][0xbc], R15 ;
LDS R12, [R2.X4+0x24c] ;
FFMA R14, R13, c[0x3][0xc0], R14 ;
LDS R13, [R2.X4+0x250] ;
FFMA R15, R5, c[0x3][0xc4], R14 ;
LDS R5, [R2.X4+0x254] ;
FFMA R15, R4, c[0x3][0xc8], R15 ;
LDS R4, [R2.X4+0x258] ;
FFMA R14, R6, c[0x3][0xcc], R15 ;
LDS R6, [R2.X4+0x25c] ;
FFMA R15, R7, c[0x3][0xd0], R14 ;
LDS R7, [R2.X4+0x260] ;
FFMA R8, R8, c[0x3][0xd4], R15 ;
LDS R15, [R2.X4+0x2a4] ;
FFMA R9, R9, c[0x3][0xd8], R8 ;
LDS R14, [R2.X4+0x2a8] ;
FFMA R10, R10, c[0x3][0xdc], R9 ;
LDS R8, [R2.X4+0x2b8] ;
FFMA R9, R11, c[0x3][0xe0], R10 ;
LDS R11, [R2.X4+0x2ac] ;
FFMA R12, R12, c[0x3][0xe4], R9 ;
LDS R10, [R2.X4+0x2b0] ;
FFMA R12, R13, c[0x3][0xe8], R12 ;
LDS R9, [R2.X4+0x2b4] ;
FFMA R5, R5, c[0x3][0xec], R12 ;
LDS R12, [R2.X4+0x2bc] ;
FFMA R5, R4, c[0x3][0xf0], R5 ;
LDS R13, [R2.X4+0x30c] ;
FFMA R4, R6, c[0x3][0xf4], R5 ;
LDS R6, [R2.X4+0x2c0] ;
FFMA R7, R7, c[0x3][0xf8], R4 ;
LDS R5, [R2.X4+0x300] ;
FFMA R16, R16, c[0x3][0xfc], R7 ;
LDS R4, [R2.X4+0x304] ;
FFMA R15, R15, c[0x3][0x100], R16 ;
LDS R7, [R2.X4+0x308] ;
FFMA R14, R14, c[0x3][0x104], R15 ;
LDS R15, [R2.X4+0x310] ;
FFMA R11, R11, c[0x3][0x108], R14 ;
FFMA R10, R10, c[0x3][0x10c], R11 ;
LDS R11, [R2.X4+0x314] ;
FFMA R9, R9, c[0x3][0x110], R10 ;
FFMA R9, R8, c[0x3][0x114], R9 ;
FFMA R9, R12, c[0x3][0x118], R9 ;
FFMA R6, R6, c[0x3][0x11c], R9 ;
FFMA R5, R5, c[0x3][0x120], R6 ;
MOV R6, 0x4 ;
FFMA R4, R4, c[0x3][0x124], R5 ;
IMAD.WIDE R2, R3, R6, c[0x0][0x168] ;
FFMA R4, R7, c[0x3][0x128], R4 ;
FFMA R4, R13, c[0x3][0x12c], R4 ;
FFMA R4, R15, c[0x3][0x130], R4 ;
FFMA R4, R11, c[0x3][0x134], R4 ;
FFMA R4, R17, c[0x3][0x138], R4 ;
FFMA R4, R19, c[0x3][0x13c], R4 ;
FFMA R21, R21, c[0x3][0x140], R4 ;
STG.E [R2.64], R21 ;
EXIT ;
BRA 0xd60;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
```
|
```amdasm
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z17gaborFilterKernelPKfPfii ; -- Begin function _Z17gaborFilterKernelPKfPfii
.globl _Z17gaborFilterKernelPKfPfii
.p2align 8
.type _Z17gaborFilterKernelPKfPfii,@function
_Z17gaborFilterKernelPKfPfii: ; @_Z17gaborFilterKernelPKfPfii
; %bb.0:
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[8:9], s[0:1], 0x10
v_bfe_u32 v2, v0, 10, 10
v_and_b32_e32 v0, 0x3ff, v0
s_lshl_b32 s12, s14, 4
s_mov_b32 s13, exec_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshl_add_u32 v1, s15, 4, v2
v_lshlrev_b32_e32 v3, 2, v0
v_cmpx_gt_u32_e32 24, v2
s_cbranch_execz .LBB0_10
; %bb.1: ; %.preheader62.lr.ph
s_load_b32 s2, s[0:1], 0x24
v_cmp_gt_u32_e32 vcc_lo, 24, v0
s_add_u32 s10, s0, 24
v_lshl_add_u32 v4, v0, 1, s12
v_mad_u32_u24 v5, 0x60, v2, v3
v_mov_b32_e32 v6, v2
s_addc_u32 s11, s1, 0
s_mov_b32 s16, 0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s14, s2, 16
s_add_u32 s4, s4, -16
s_addc_u32 s5, s5, -1
s_mul_i32 s15, s14, 0x60
.LBB0_2: ; %.preheader62
; =>This Loop Header: Depth=1
; Child Loop BB0_4 Depth 2
s_and_saveexec_b32 s17, vcc_lo
s_cbranch_execz .LBB0_9
; %bb.3: ; %.lr.ph
; in Loop: Header=BB0_2 Depth=1
s_load_b32 s2, s[10:11], 0xc
v_dual_mov_b32 v8, v5 :: v_dual_add_nc_u32 v9, v6, v1
s_mov_b32 s19, 0
s_mov_b32 s21, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v10, -4, v9
v_cmp_lt_i32_e64 s0, 3, v9
v_mul_lo_u32 v7, v10, s8
v_cmp_gt_i32_e64 s1, s9, v10
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_ashrrev_i32_e32 v9, 31, v7
s_waitcnt lgkmcnt(0)
s_and_b32 s18, s2, 0xffff
s_lshl_b32 s20, s18, 2
.LBB0_4: ; Parent Loop BB0_2 Depth=1
; => This Inner Loop Header: Depth=2
v_mov_b32_e32 v10, 0
s_and_saveexec_b32 s22, s0
s_cbranch_execz .LBB0_8
; %bb.5: ; in Loop: Header=BB0_4 Depth=2
v_add_nc_u32_e32 v11, s21, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v10, -4, v11
v_cmp_gt_i32_e64 s3, s8, v10
v_mov_b32_e32 v10, 0
v_cmp_lt_i32_e64 s2, 3, v11
s_delay_alu instid0(VALU_DEP_1)
s_and_b32 s2, s1, s2
s_delay_alu instid0(VALU_DEP_3) | instid1(SALU_CYCLE_1)
s_and_b32 s2, s2, s3
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_7
; %bb.6: ; in Loop: Header=BB0_4 Depth=2
v_ashrrev_i32_e32 v12, 31, v11
v_add_co_u32 v10, s2, v11, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e64 v11, s2, v12, v9, s2
v_lshlrev_b64 v[10:11], 2, v[10:11]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v10, s2, s4, v10
v_add_co_ci_u32_e64 v11, s2, s5, v11, s2
global_load_b32 v10, v[10:11], off
.LBB0_7: ; %Flow96
; in Loop: Header=BB0_4 Depth=2
s_or_b32 exec_lo, exec_lo, s3
.LBB0_8: ; in Loop: Header=BB0_4 Depth=2
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s22
s_add_i32 s21, s21, s18
s_waitcnt vmcnt(0)
ds_store_b32 v8, v10
v_add_nc_u32_e32 v11, s21, v0
v_add_nc_u32_e32 v8, s20, v8
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_lt_u32_e64 s2, 23, v11
s_or_b32 s19, s2, s19
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s19
s_cbranch_execnz .LBB0_4
.LBB0_9: ; %Flow98
; in Loop: Header=BB0_2 Depth=1
s_or_b32 exec_lo, exec_lo, s17
v_add_nc_u32_e32 v6, s14, v6
v_add_nc_u32_e32 v5, s15, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_lt_u32_e64 s0, 23, v6
s_or_b32 s16, s0, s16
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s16
s_cbranch_execnz .LBB0_2
.LBB0_10: ; %Flow100
s_or_b32 exec_lo, exec_lo, s13
v_add_nc_u32_e32 v0, s12, v0
s_waitcnt lgkmcnt(0)
v_cmp_gt_i32_e32 vcc_lo, s9, v1
s_barrier
buffer_gl0_inv
v_cmp_gt_i32_e64 s0, s8, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s0, s0, vcc_lo
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_16
; %bb.11: ; %.preheader.preheader
v_mad_u32_u24 v3, 0x60, v2, v3
v_mov_b32_e32 v2, 0
s_mov_b32 s4, 0
s_getpc_b64 s[0:1]
s_add_u32 s0, s0, d_gaborFilter@rel32@lo+4
s_addc_u32 s1, s1, d_gaborFilter@rel32@hi+12
.LBB0_12: ; %.preheader
; =>This Loop Header: Depth=1
; Child Loop BB0_13 Depth 2
s_delay_alu instid0(SALU_CYCLE_1)
s_mov_b64 s[2:3], s[0:1]
s_mov_b32 s5, 0
.LBB0_13: ; Parent Loop BB0_12 Depth=1
; => This Inner Loop Header: Depth=2
s_delay_alu instid0(SALU_CYCLE_1)
v_add_nc_u32_e32 v4, s5, v3
s_load_b32 s9, s[2:3], 0x0
s_add_i32 s5, s5, 4
s_add_u32 s2, s2, 4
s_addc_u32 s3, s3, 0
ds_load_b32 v4, v4
s_cmp_eq_u32 s5, 36
s_waitcnt lgkmcnt(0)
v_fmac_f32_e32 v2, s9, v4
s_cbranch_scc0 .LBB0_13
; %bb.14: ; in Loop: Header=BB0_12 Depth=1
s_add_i32 s4, s4, 1
v_add_nc_u32_e32 v3, 0x60, v3
s_add_u32 s0, s0, 36
s_addc_u32 s1, s1, 0
s_cmp_eq_u32 s4, 9
s_cbranch_scc0 .LBB0_12
; %bb.15:
v_mad_u64_u32 v[3:4], null, v1, s8, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v4, 31, v3
v_lshlrev_b64 v[0:1], 2, v[3:4]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
global_store_b32 v[0:1], v2, off
.LBB0_16:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z17gaborFilterKernelPKfPfii
.amdhsa_group_segment_fixed_size 2304
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 13
.amdhsa_next_free_sgpr 23
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z17gaborFilterKernelPKfPfii, .Lfunc_end0-_Z17gaborFilterKernelPKfPfii
; -- End function
.section .AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 708
; NumSgprs: 25
; NumVgprs: 13
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 2304 bytes/workgroup (compile time only)
; SGPRBlocks: 3
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 25
; NumVGPRsForWavesPerEU: 13
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.protected d_gaborFilter ; @d_gaborFilter
.type d_gaborFilter,@object
.section .bss,"aw",@nobits
.globl d_gaborFilter
.p2align 4, 0x0
d_gaborFilter:
.zero 324
.size d_gaborFilter, 324
.type __hip_cuid_,@object ; @__hip_cuid_
.globl __hip_cuid_
__hip_cuid_:
.byte 0 ; 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym d_gaborFilter
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 2304
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z17gaborFilterKernelPKfPfii
.private_segment_fixed_size: 0
.sgpr_count: 25
.sgpr_spill_count: 0
.symbol: _Z17gaborFilterKernelPKfPfii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 13
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
```
| 4,286 | 4,942 |
113,689 |
Convert the following CUDA host assembly code to AMD host assembly:
```cudaasm
.file "tmpxft_000e6775_00000000-6_cuda_code_045734.cudafe1.cpp"
.text
.globl _ZSt21ios_base_library_initv
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3639:
.cfi_startproc
endbr64
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
jmp __cudaUnregisterFatBinary@PLT
.cfi_endproc
.LFE3639:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string ": "
.text
.globl _Z14checkCudaError9cudaErrorPKc
.type _Z14checkCudaError9cudaErrorPKc, @function
_Z14checkCudaError9cudaErrorPKc:
.LFB3635:
.cfi_startproc
endbr64
testl %edi, %edi
je .L2
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
movl %edi, %ebx
leaq _ZSt4cerr(%rip), %rdi
pushq %rax
.cfi_def_cfa_offset 32
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
leaq .LC0(%rip), %rsi
movq %rax, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movl %ebx, %edi
movq %rax, %rbp
call cudaGetErrorString@PLT
movq %rbp, %rdi
movq %rax, %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $1, %edi
call exit@PLT
.L2:
.cfi_def_cfa_offset 8
.cfi_restore 3
.cfi_restore 6
ret
.cfi_endproc
.LFE3635:
.size _Z14checkCudaError9cudaErrorPKc, .-_Z14checkCudaError9cudaErrorPKc
.globl _Z42__device_stub__Z17gaborFilterKernelPKfPfiiPKfPfii
.type _Z42__device_stub__Z17gaborFilterKernelPKfPfiiPKfPfii, @function
_Z42__device_stub__Z17gaborFilterKernelPKfPfiiPKfPfii:
.LFB3661:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
leaq 56(%rsp), %rdi
movq %rsi, 16(%rsp)
leaq 68(%rsp), %rsi
movl %edx, 12(%rsp)
leaq 40(%rsp), %rdx
movl %ecx, 8(%rsp)
leaq 48(%rsp), %rcx
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movl $1, 64(%rsp)
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 12(%rsp), %rax
movq %rax, 120(%rsp)
leaq 8(%rsp), %rax
movq %rax, 128(%rsp)
movabsq $4294967297, %rax
movq %rax, 56(%rsp)
movq %rax, 68(%rsp)
movl $1, 76(%rsp)
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
jne .L8
pushq 48(%rsp)
.cfi_def_cfa_offset 168
leaq _Z17gaborFilterKernelPKfPfii(%rip), %rdi
pushq 48(%rsp)
.cfi_def_cfa_offset 176
movq 84(%rsp), %rcx
movl 92(%rsp), %r8d
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
leaq 120(%rsp), %r9
call cudaLaunchKernel@PLT
popq %rax
.cfi_def_cfa_offset 168
popq %rdx
.cfi_def_cfa_offset 160
.L8:
movq 136(%rsp), %rax
subq %fs:40, %rax
je .L10
call __stack_chk_fail@PLT
.L10:
addq $152, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3661:
.size _Z42__device_stub__Z17gaborFilterKernelPKfPfiiPKfPfii, .-_Z42__device_stub__Z17gaborFilterKernelPKfPfiiPKfPfii
.globl _Z17gaborFilterKernelPKfPfii
.type _Z17gaborFilterKernelPKfPfii, @function
_Z17gaborFilterKernelPKfPfii:
.LFB3662:
.cfi_startproc
endbr64
jmp _Z42__device_stub__Z17gaborFilterKernelPKfPfiiPKfPfii
.cfi_endproc
.LFE3662:
.size _Z17gaborFilterKernelPKfPfii, .-_Z17gaborFilterKernelPKfPfii
.section .rodata.str1.1
.LC2:
.string "Failed to allocate d_input"
.LC3:
.string "Failed to allocate d_output"
.LC4:
.string "Failed to copy input data"
.LC12:
.string "Failed to copy Gabor filter to constant memory"
.LC13:
.string "Kernel launch failed"
.LC14:
.string "Kernel execution failed"
.LC15:
.string "Failed to copy output data"
.LC16:
.string "Failed to free d_input"
.LC17:
.string "Failed to free d_output"
.LC18:
.string "Gabor filtering completed successfully."
.section .text.startup,"ax",@progbits
.globl main
.type main, @function
main:
.LFB3636:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
movl $16777216, %edi
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
xorl %r12d, %r12d
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $400, %rsp
.cfi_def_cfa_offset 448
movq %fs:40, %rax
movq %rax, 392(%rsp)
xorl %eax, %eax
call _Znam@PLT
movl $16777216, %edi
movq %rax, %rbx
call _Znam@PLT
movq %rax, %rbp
.L14:
call rand@PLT
cvtsi2ssl %eax, %xmm0
mulss .LC1(%rip), %xmm0
movss %xmm0, (%rbx,%r12,4)
incq %r12
cmpq $1048576, %r12
jne .L14
leaq 24(%rsp), %rdi
movl $4194304, %esi
leaq -76(%rsp), %r14
movl $-4, %r13d
call cudaMalloc@PLT
leaq .LC2(%rip), %rsi
movl %eax, %edi
call _Z14checkCudaError9cudaErrorPKc
leaq 32(%rsp), %rdi
movl $4194304, %esi
call cudaMalloc@PLT
leaq .LC3(%rip), %rsi
movl %eax, %edi
call _Z14checkCudaError9cudaErrorPKc
movq 24(%rsp), %rdi
movl $1, %ecx
movq %rbx, %rsi
movl $4194304, %edx
call cudaMemcpy@PLT
leaq .LC4(%rip), %rsi
movl %eax, %edi
call _Z14checkCudaError9cudaErrorPKc
.L15:
cvtsi2ssl %r13d, %xmm3
mulss .LC5(%rip), %xmm3
movq $-4, %r12
.L16:
movl %r12d, %eax
cvtsi2ssl %r12d, %xmm1
movss .LC6(%rip), %xmm0
movss %xmm3, 12(%rsp)
mulss .LC5(%rip), %xmm1
negl %eax
cvtsi2ssl %eax, %xmm2
mulss .LC5(%rip), %xmm2
addss %xmm3, %xmm1
addss %xmm3, %xmm2
movss %xmm1, 8(%rsp)
mulss %xmm2, %xmm0
mulss %xmm2, %xmm0
movaps %xmm1, %xmm2
mulss %xmm1, %xmm2
addss %xmm2, %xmm0
mulss .LC19(%rip), %xmm0
call expf@PLT
movss 8(%rsp), %xmm1
movss %xmm0, 4(%rsp)
cvtss2sd %xmm1, %xmm0
mulsd .LC9(%rip), %xmm0
xorps %xmm1, %xmm1
divsd .LC10(%rip), %xmm0
addsd %xmm1, %xmm0
call cos@PLT
movss 4(%rsp), %xmm2
movss 12(%rsp), %xmm3
movaps %xmm0, %xmm1
cvtss2sd %xmm2, %xmm0
mulsd %xmm1, %xmm0
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 160(%r14,%r12,4)
incq %r12
cmpq $5, %r12
jne .L16
incl %r13d
addq $36, %r14
cmpl $5, %r13d
jne .L15
xorl %ecx, %ecx
movl $1, %r8d
movl $324, %edx
leaq 68(%rsp), %rsi
leaq _ZL13d_gaborFilter(%rip), %rdi
call cudaMemcpyToSymbol@PLT
leaq .LC12(%rip), %rsi
movl %eax, %edi
call _Z14checkCudaError9cudaErrorPKc
xorl %r9d, %r9d
xorl %r8d, %r8d
movl $1, %ecx
movabsq $68719476752, %rdx
movl $1, %esi
movabsq $274877907008, %rdi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L18
movq 32(%rsp), %rsi
movq 24(%rsp), %rdi
movl $1024, %ecx
movl $1024, %edx
call _Z42__device_stub__Z17gaborFilterKernelPKfPfiiPKfPfii
.L18:
call cudaGetLastError@PLT
leaq .LC13(%rip), %rsi
movl %eax, %edi
call _Z14checkCudaError9cudaErrorPKc
call cudaDeviceSynchronize@PLT
leaq .LC14(%rip), %rsi
movl %eax, %edi
call _Z14checkCudaError9cudaErrorPKc
movq 32(%rsp), %rsi
movl $2, %ecx
movq %rbp, %rdi
movl $4194304, %edx
call cudaMemcpy@PLT
leaq .LC15(%rip), %rsi
movl %eax, %edi
call _Z14checkCudaError9cudaErrorPKc
movq 24(%rsp), %rdi
call cudaFree@PLT
leaq .LC16(%rip), %rsi
movl %eax, %edi
call _Z14checkCudaError9cudaErrorPKc
movq 32(%rsp), %rdi
call cudaFree@PLT
leaq .LC17(%rip), %rsi
movl %eax, %edi
call _Z14checkCudaError9cudaErrorPKc
movq %rbx, %rdi
call _ZdaPv@PLT
movq %rbp, %rdi
call _ZdaPv@PLT
leaq _ZSt4cout(%rip), %rdi
leaq .LC18(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq 392(%rsp), %rax
subq %fs:40, %rax
je .L19
call __stack_chk_fail@PLT
.L19:
addq $400, %rsp
.cfi_def_cfa_offset 48
xorl %eax, %eax
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3636:
.size main, .-main
.section .rodata.str1.1
.LC20:
.string "_Z17gaborFilterKernelPKfPfii"
.LC21:
.string "d_gaborFilter"
.section .text.startup
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3664:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
pushq $0
.cfi_def_cfa_offset 24
xorl %r9d, %r9d
orl $-1, %r8d
pushq $0
.cfi_def_cfa_offset 32
leaq .LC20(%rip), %rdx
movq %rax, %rdi
movq %rax, %rbx
pushq $0
.cfi_def_cfa_offset 40
movq %rdx, %rcx
leaq _Z17gaborFilterKernelPKfPfii(%rip), %rsi
pushq $0
.cfi_def_cfa_offset 48
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq %rbx, %rdi
xorl %r8d, %r8d
pushq $0
.cfi_def_cfa_offset 24
leaq .LC21(%rip), %rdx
movl $324, %r9d
leaq _ZL13d_gaborFilter(%rip), %rsi
pushq $1
.cfi_def_cfa_offset 32
movq %rdx, %rcx
call __cudaRegisterVar@PLT
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
popq %rax
.cfi_def_cfa_offset 24
popq %rdx
.cfi_def_cfa_offset 16
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit@PLT
.cfi_endproc
.LFE3664:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZL13d_gaborFilter
.comm _ZL13d_gaborFilter,324,32
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC1:
.long 805306368
.align 4
.LC5:
.long 1060439283
.align 4
.LC6:
.long 1048576000
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC9:
.long 1413754136
.long 1075388923
.align 8
.LC10:
.long 0
.long 1076101120
.section .rodata.cst4
.align 4
.LC19:
.long -1107296256
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
```
|
```amdasm
.text
.file "cuda_code_045734.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z32__device_stub__gaborFilterKernelPKfPfii # -- Begin function _Z32__device_stub__gaborFilterKernelPKfPfii
.type _Z32__device_stub__gaborFilterKernelPKfPfii,@function
_Z32__device_stub__gaborFilterKernelPKfPfii: # @_Z32__device_stub__gaborFilterKernelPKfPfii
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $112, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 40(%rsp), %rax
movq %rdi, (%rax)
leaq 32(%rsp), %rdi
movq %rsi, (%rdi)
leaq 12(%rsp), %rsi
movl %edx, (%rsi)
leaq 8(%rsp), %rdx
movl %ecx, (%rdx)
leaq 80(%rsp), %rbx
movq %rax, (%rbx)
movq %rdi, 8(%rbx)
movq %rsi, 16(%rbx)
movq %rdx, 24(%rbx)
leaq 64(%rsp), %r14
leaq 48(%rsp), %r15
leaq 24(%rsp), %r12
leaq 16(%rsp), %r13
movq %r14, %rdi
movq %r15, %rsi
movq %r12, %rdx
movq %r13, %rcx
callq __hipPopCallConfiguration
movq (%r14), %rsi
movl 8(%r14), %edx
movq (%r15), %rcx
movl 8(%r15), %r8d
movl $_Z17gaborFilterKernelPKfPfii, %edi
movq %rbx, %r9
pushq (%r13)
.cfi_adjust_cfa_offset 8
pushq (%r12)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $128, %rsp
.cfi_adjust_cfa_offset -128
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z32__device_stub__gaborFilterKernelPKfPfii, .Lfunc_end0-_Z32__device_stub__gaborFilterKernelPKfPfii
.cfi_endproc
# -- End function
.globl _Z14checkCudaError10hipError_tPKc # -- Begin function _Z14checkCudaError10hipError_tPKc
.type _Z14checkCudaError10hipError_tPKc,@function
_Z14checkCudaError10hipError_tPKc: # @_Z14checkCudaError10hipError_tPKc
.cfi_startproc
# %bb.0:
testl %edi, %edi
jne .LBB1_2
# %bb.1:
retq
.LBB1_2:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
pushq %rax
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movl %edi, %ebx
movl $_ZSt4cerr, %edi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movl $.L.str, %esi
movq %rax, %rdi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movq %rax, %r14
movl %ebx, %edi
callq hipGetErrorString
movq %r14, %rdi
movq %rax, %rsi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movq %rax, %rdi
callq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_
movl $1, %edi
callq exit
.Lfunc_end1:
.size _Z14checkCudaError10hipError_tPKc, .Lfunc_end1-_Z14checkCudaError10hipError_tPKc
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI2_0:
.long 0x30000000 # float 4.65661287E-10
.LCPI2_1:
.long 0x3f3504f3 # float 0.707106769
.LCPI2_2:
.long 0x3e800000 # float 0.25
.LCPI2_3:
.long 0xbe000000 # float -0.125
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0
.LCPI2_4:
.quad 0x401921fb54442d18 # double 6.2831853071795862
.LCPI2_5:
.quad 0x4024000000000000 # double 10
.LCPI2_6:
.quad 0x0000000000000000 # double 0
.text
.globl main
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $360, %rsp # imm = 0x168
.cfi_def_cfa_offset 416
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $16777216, %edi # imm = 0x1000000
callq _Znam
movq %rax, %rbx
movl $16777216, %edi # imm = 0x1000000
callq _Znam
movq %rax, %r14
xorl %r15d, %r15d
.LBB2_1: # =>This Inner Loop Header: Depth=1
callq rand
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
mulss .LCPI2_0(%rip), %xmm0
movss %xmm0, (%rbx,%r15,4)
incq %r15
cmpq $1048576, %r15 # imm = 0x100000
jne .LBB2_1
# %bb.2:
leaq 16(%rsp), %r15
movl $4194304, %esi # imm = 0x400000
movq %r15, %rdi
callq hipMalloc
movl $.L.str.1, %esi
movl %eax, %edi
callq _Z14checkCudaError10hipError_tPKc
movq %rsp, %rdi
movl $4194304, %esi # imm = 0x400000
callq hipMalloc
movl $.L.str.2, %esi
movl %eax, %edi
callq _Z14checkCudaError10hipError_tPKc
movq (%r15), %rdi
movl $4194304, %edx # imm = 0x400000
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movl $.L.str.3, %esi
movl %eax, %edi
callq _Z14checkCudaError10hipError_tPKc
movq $-4, %r15
leaq 32(%rsp), %r12
movss .LCPI2_1(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero
movss .LCPI2_2(%rip), %xmm3 # xmm3 = mem[0],zero,zero,zero
movss .LCPI2_3(%rip), %xmm4 # xmm4 = mem[0],zero,zero,zero
.LBB2_3: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB2_4 Depth 2
xorps %xmm1, %xmm1
cvtsi2ss %r15d, %xmm1
mulss %xmm0, %xmm1
movss %xmm1, 8(%rsp) # 4-byte Spill
movl $4, %ebp
xorl %r13d, %r13d
.LBB2_4: # Parent Loop BB2_3 Depth=1
# => This Inner Loop Header: Depth=2
leal -4(%r13), %eax
xorps %xmm5, %xmm5
cvtsi2ss %eax, %xmm5
mulss %xmm0, %xmm5
movss 8(%rsp), %xmm2 # 4-byte Reload
# xmm2 = mem[0],zero,zero,zero
addss %xmm2, %xmm5
movss %xmm5, 12(%rsp) # 4-byte Spill
xorps %xmm1, %xmm1
cvtsi2ss %ebp, %xmm1
mulss %xmm0, %xmm1
addss %xmm2, %xmm1
movaps %xmm5, %xmm2
mulss %xmm5, %xmm2
movaps %xmm1, %xmm0
mulss %xmm3, %xmm0
mulss %xmm1, %xmm0
addss %xmm2, %xmm0
mulss %xmm4, %xmm0
callq expf
cvtss2sd %xmm0, %xmm0
movsd %xmm0, 24(%rsp) # 8-byte Spill
xorps %xmm0, %xmm0
cvtss2sd 12(%rsp), %xmm0 # 4-byte Folded Reload
mulsd .LCPI2_4(%rip), %xmm0
divsd .LCPI2_5(%rip), %xmm0
addsd .LCPI2_6(%rip), %xmm0
callq cos
movss .LCPI2_3(%rip), %xmm4 # xmm4 = mem[0],zero,zero,zero
movss .LCPI2_2(%rip), %xmm3 # xmm3 = mem[0],zero,zero,zero
mulsd 24(%rsp), %xmm0 # 8-byte Folded Reload
cvtsd2ss %xmm0, %xmm0
movss %xmm0, (%r12,%r13,4)
movss .LCPI2_1(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero
decl %ebp
incq %r13
cmpq $9, %r13
jne .LBB2_4
# %bb.5: # in Loop: Header=BB2_3 Depth=1
incq %r15
addq $36, %r12
cmpq $5, %r15
jne .LBB2_3
# %bb.6:
leaq 32(%rsp), %rsi
movl $d_gaborFilter, %edi
movl $324, %edx # imm = 0x144
xorl %ecx, %ecx
movl $1, %r8d
callq hipMemcpyToSymbol
movl $.L.str.4, %esi
movl %eax, %edi
callq _Z14checkCudaError10hipError_tPKc
movabsq $274877907008, %rdi # imm = 0x4000000040
movabsq $68719476752, %rdx # imm = 0x1000000010
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_8
# %bb.7:
movq 16(%rsp), %rdi
movq (%rsp), %rsi
movl $1024, %edx # imm = 0x400
movl $1024, %ecx # imm = 0x400
callq _Z32__device_stub__gaborFilterKernelPKfPfii
.LBB2_8:
callq hipGetLastError
movl $.L.str.5, %esi
movl %eax, %edi
callq _Z14checkCudaError10hipError_tPKc
callq hipDeviceSynchronize
movl $.L.str.6, %esi
movl %eax, %edi
callq _Z14checkCudaError10hipError_tPKc
movq (%rsp), %rsi
movl $4194304, %edx # imm = 0x400000
movq %r14, %rdi
movl $2, %ecx
callq hipMemcpy
movl $.L.str.7, %esi
movl %eax, %edi
callq _Z14checkCudaError10hipError_tPKc
movq 16(%rsp), %rdi
callq hipFree
movl $.L.str.8, %esi
movl %eax, %edi
callq _Z14checkCudaError10hipError_tPKc
movq (%rsp), %rdi
callq hipFree
movl $.L.str.9, %esi
movl %eax, %edi
callq _Z14checkCudaError10hipError_tPKc
movq %rbx, %rdi
callq _ZdaPv
movq %r14, %rdi
callq _ZdaPv
movl $_ZSt4cout, %ebx
movl $_ZSt4cout, %edi
movl $.L.str.10, %esi
movl $39, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rdi
addq %rbx, %rdi
movl $10, %esi
callq _ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
xorl %eax, %eax
addq $360, %rsp # imm = 0x168
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
movq __hip_gpubin_handle(%rip), %rbx
testq %rbx, %rbx
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, %rbx
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z17gaborFilterKernelPKfPfii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $0, 8(%rsp)
movl $1, (%rsp)
movl $d_gaborFilter, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movl $324, %r9d # imm = 0x144
movq %rbx, %rdi
xorl %r8d, %r8d
callq __hipRegisterVar
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type d_gaborFilter,@object # @d_gaborFilter
.local d_gaborFilter
.comm d_gaborFilter,324,16
.type _Z17gaborFilterKernelPKfPfii,@object # @_Z17gaborFilterKernelPKfPfii
.section .rodata,"a",@progbits
.globl _Z17gaborFilterKernelPKfPfii
.p2align 3, 0x0
_Z17gaborFilterKernelPKfPfii:
.quad _Z32__device_stub__gaborFilterKernelPKfPfii
.size _Z17gaborFilterKernelPKfPfii, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz ": "
.size .L.str, 3
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Failed to allocate d_input"
.size .L.str.1, 27
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Failed to allocate d_output"
.size .L.str.2, 28
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Failed to copy input data"
.size .L.str.3, 26
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Failed to copy Gabor filter to constant memory"
.size .L.str.4, 47
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "Kernel launch failed"
.size .L.str.5, 21
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "Kernel execution failed"
.size .L.str.6, 24
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "Failed to copy output data"
.size .L.str.7, 27
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "Failed to free d_input"
.size .L.str.8, 23
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "Failed to free d_output"
.size .L.str.9, 24
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "Gabor filtering completed successfully."
.size .L.str.10, 40
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z17gaborFilterKernelPKfPfii"
.size .L__unnamed_1, 29
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "d_gaborFilter"
.size .L__unnamed_2, 14
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z32__device_stub__gaborFilterKernelPKfPfii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym d_gaborFilter
.addrsig_sym _Z17gaborFilterKernelPKfPfii
.addrsig_sym _ZSt4cerr
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
```
| 5,129 | 6,534 |
113,690 |
Convert the following CUDA device assembly code to AMD device assembly:
```cudaasm
code for sm_80
Function : _Z21fluidSimulationKernelPfS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ;
S2R R0, SR_CTAID.X ;
ULDC UR4, c[0x0][0x170] ;
IMAD.MOV.U32 R3, RZ, RZ, 0x4 ;
UIADD3 UR4, UR4, -0x1, URZ ;
S2R R8, SR_TID.X ;
IMAD R0, R0, c[0x0][0x0], R8 ;
IMAD.WIDE R2, R0.reuse, R3, c[0x0][0x160] ;
ISETP.GE.AND P0, PT, R0.reuse, 0x1, PT ;
ISETP.GE.AND P1, PT, R0, UR4, PT ;
ULDC.64 UR4, c[0x0][0x118] ;
ISETP.NE.OR P0, PT, R8.reuse, RZ, !P0 ;
LDG.E R5, [R2.64] ;
ISETP.NE.OR P2, PT, R8, 0xff, P1 ;
@!P0 LDG.E R6, [R2.64+-0x4] ;
@!P2 LDG.E R4, [R2.64+0x400] ;
ISETP.LT.OR P1, PT, R0, 0x1, P1 ;
@!P0 STS [RZ], R6 ;
@!P2 STS [0x404], R4 ;
STS [R8.X4+0x4], R5 ;
BAR.SYNC.DEFER_BLOCKING 0x0 ;
@P1 EXIT ;
LDS R5, [R8.X4] ;
SHF.R.S32.HI R7, RZ, 0x1f, R0 ;
LEA R4, P0, R0.reuse, c[0x0][0x168], 0x2 ;
LDS R6, [R8.X4+0x8] ;
FADD R6, -R5, R6 ;
LEA.HI.X R5, R0, c[0x0][0x16c], R7, 0x2, P0 ;
FMUL R7, R6, 0.5 ;
STG.E [R4.64], R7 ;
LDG.E R0, [R2.64] ;
FFMA R9, R7, -0.10000000149011611938, R0 ;
STG.E [R2.64], R9 ;
EXIT ;
BRA 0x220;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
```
|
```amdasm
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z21fluidSimulationKernelPfS_i ; -- Begin function _Z21fluidSimulationKernelPfS_i
.globl _Z21fluidSimulationKernelPfS_i
.p2align 8
.type _Z21fluidSimulationKernelPfS_i,@function
_Z21fluidSimulationKernelPfS_i: ; @_Z21fluidSimulationKernelPfS_i
; %bb.0:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b128 s[4:7], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
v_cmp_eq_u32_e64 s2, 0, v0
v_cmp_lt_i32_e32 vcc_lo, 0, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, s2, vcc_lo
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_2
; %bb.1:
v_mov_b32_e32 v2, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[1:2]
v_add_co_u32 v3, s2, s4, v3
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v4, s2, s5, v4, s2
global_load_b32 v3, v[3:4], off offset:-4
s_waitcnt vmcnt(0)
ds_store_b32 v2, v3
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s3
s_load_b32 s0, s[0:1], 0x10
v_ashrrev_i32_e32 v2, 31, v1
v_cmp_eq_u32_e64 s1, 0xff, v0
s_waitcnt lgkmcnt(0)
s_add_i32 s0, s0, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cmp_gt_i32_e64 s0, s0, v1
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_and_b32 s1, s1, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s2, s1
s_cbranch_execz .LBB0_4
; %bb.3:
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v3, s1, s4, v1
v_add_co_ci_u32_e64 v4, s1, s5, v2, s1
global_load_b32 v3, v[3:4], off offset:1024
v_mov_b32_e32 v4, 0
s_waitcnt vmcnt(0)
ds_store_b32 v4, v3 offset:1028
.LBB0_4: ; %._crit_edge
s_or_b32 exec_lo, exec_lo, s2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v3, s1, s4, v1
v_add_co_ci_u32_e64 v4, s1, s5, v2, s1
v_lshlrev_b32_e32 v0, 2, v0
s_and_b32 s0, vcc_lo, s0
global_load_b32 v5, v[3:4], off
s_waitcnt vmcnt(0)
ds_store_b32 v0, v5 offset:4
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_6
; %bb.5:
ds_load_2addr_b32 v[5:6], v0 offset1:2
s_waitcnt lgkmcnt(0)
v_sub_f32_e32 v0, v6, v5
s_delay_alu instid0(VALU_DEP_1)
v_mul_f32_e32 v5, 0.5, v0
v_add_co_u32 v0, vcc_lo, s6, v1
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v2, vcc_lo
global_store_b32 v[0:1], v5, off
global_load_b32 v0, v[3:4], off
s_waitcnt vmcnt(0)
v_fmamk_f32 v0, v5, 0xbdcccccd, v0
global_store_b32 v[3:4], v0, off
.LBB0_6:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z21fluidSimulationKernelPfS_i
.amdhsa_group_segment_fixed_size 1032
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z21fluidSimulationKernelPfS_i, .Lfunc_end0-_Z21fluidSimulationKernelPfS_i
; -- End function
.section .AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 404
; NumSgprs: 18
; NumVgprs: 7
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 1032 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 7
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object ; @__hip_cuid_
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0 ; 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 1032
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z21fluidSimulationKernelPfS_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z21fluidSimulationKernelPfS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
```
| 726 | 3,248 |
113,691 |
Convert the following CUDA host assembly code to AMD host assembly:
```cudaasm
.file "tmpxft_0000d0b0_00000000-6_cuda_code_081934.cudafe1.cpp"
.text
.globl _ZSt21ios_base_library_initv
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3638:
.cfi_startproc
endbr64
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
jmp __cudaUnregisterFatBinary@PLT
.cfi_endproc
.LFE3638:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.align 2
.type _ZNSolsEPFRSoS_E.isra.0, @function
_ZNSolsEPFRSoS_E.isra.0:
.LFB4293:
.cfi_startproc
jmp *%rsi
.cfi_endproc
.LFE4293:
.size _ZNSolsEPFRSoS_E.isra.0, .-_ZNSolsEPFRSoS_E.isra.0
.globl _Z44__device_stub__Z21fluidSimulationKernelPfS_iPfS_i
.type _Z44__device_stub__Z21fluidSimulationKernelPfS_iPfS_i, @function
_Z44__device_stub__Z21fluidSimulationKernelPfS_iPfS_i:
.LFB3660:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
leaq 40(%rsp), %rcx
leaq 48(%rsp), %rdi
movq %rsi, 16(%rsp)
leaq 60(%rsp), %rsi
movl %edx, 12(%rsp)
leaq 32(%rsp), %rdx
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movl $1, 56(%rsp)
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movabsq $4294967297, %rax
movq %rax, 48(%rsp)
movq %rax, 60(%rsp)
movl $1, 68(%rsp)
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
jne .L3
pushq 40(%rsp)
.cfi_def_cfa_offset 152
leaq _Z21fluidSimulationKernelPfS_i(%rip), %rdi
pushq 40(%rsp)
.cfi_def_cfa_offset 160
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq 112(%rsp), %r9
call cudaLaunchKernel@PLT
popq %rax
.cfi_def_cfa_offset 152
popq %rdx
.cfi_def_cfa_offset 144
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
je .L5
call __stack_chk_fail@PLT
.L5:
addq $136, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3660:
.size _Z44__device_stub__Z21fluidSimulationKernelPfS_iPfS_i, .-_Z44__device_stub__Z21fluidSimulationKernelPfS_iPfS_i
.globl _Z21fluidSimulationKernelPfS_i
.type _Z21fluidSimulationKernelPfS_i, @function
_Z21fluidSimulationKernelPfS_i:
.LFB3661:
.cfi_startproc
endbr64
jmp _Z44__device_stub__Z21fluidSimulationKernelPfS_iPfS_i
.cfi_endproc
.LFE3661:
.size _Z21fluidSimulationKernelPfS_i, .-_Z21fluidSimulationKernelPfS_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Error allocating device memory for fluid field"
.LC1:
.string "Error allocating device memory for flux"
.LC2:
.string "Error copying fluid field to device"
.LC3:
.string "Error launching kernel: "
.LC4:
.string "Error copying fluid field from device"
.LC5:
.string "Updated fluid field:"
.LC6:
.string " "
.section .text.startup,"ax",@progbits
.globl main
.type main, @function
main:
.LFB3635:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
movl $1024, %edi
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $48, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
call _Znam@PLT
movl $1024, %edi
movq %rax, %rbx
call _Znam@PLT
xorl %ecx, %ecx
movq %rax, %rbp
.L10:
cvtsi2ssl %ecx, %xmm0
movss %xmm0, (%rbx,%rcx,4)
incq %rcx
cmpq $256, %rcx
jne .L10
xorl %eax, %eax
movq %rbp, %rdi
movl $1024, %esi
rep stosl
movq %rsp, %rdi
call cudaMalloc@PLT
testl %eax, %eax
je .L11
leaq .LC0(%rip), %rsi
leaq _ZSt4cerr(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@GOTPCREL(%rip), %rsi
movq %rax, %rdi
call _ZNSolsEPFRSoS_E.isra.0
jmp .L12
.L11:
leaq 8(%rsp), %rdi
movl $1024, %esi
call cudaMalloc@PLT
testl %eax, %eax
je .L13
leaq .LC1(%rip), %rsi
leaq _ZSt4cerr(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@GOTPCREL(%rip), %rsi
movq %rax, %rdi
call _ZNSolsEPFRSoS_E.isra.0
movq (%rsp), %rdi
.L24:
call cudaFree@PLT
.L12:
orl $-1, %eax
jmp .L9
.L13:
movq (%rsp), %rdi
movq %rbx, %rsi
movl $1, %ecx
movl $1024, %edx
call cudaMemcpy@PLT
leaq .LC2(%rip), %rsi
testl %eax, %eax
jne .L26
movl $16777217, %edx
xorl %r9d, %r9d
xorl %r8d, %r8d
movl $1, %ecx
salq $8, %rdx
movl $1, %esi
movabsq $4294967297, %rdi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L16
movq 8(%rsp), %rsi
movq (%rsp), %rdi
movl $256, %edx
call _Z44__device_stub__Z21fluidSimulationKernelPfS_iPfS_i
.L16:
call cudaGetLastError@PLT
movl %eax, %r12d
testl %eax, %eax
je .L17
leaq .LC3(%rip), %rsi
leaq _ZSt4cerr(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movl %r12d, %edi
movq %rax, %rbx
call cudaGetErrorString@PLT
movq %rbx, %rdi
movq %rax, %rsi
jmp .L25
.L17:
movq (%rsp), %rsi
movl $2, %ecx
movl $1024, %edx
movq %rbx, %rdi
call cudaMemcpy@PLT
testl %eax, %eax
je .L18
leaq .LC4(%rip), %rsi
.L26:
leaq _ZSt4cerr(%rip), %rdi
.L25:
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@GOTPCREL(%rip), %rsi
movq %rax, %rdi
call _ZNSolsEPFRSoS_E.isra.0
movq (%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
jmp .L24
.L18:
leaq _ZSt4cout(%rip), %r13
leaq .LC5(%rip), %rsi
xorl %r12d, %r12d
movq %r13, %rdi
leaq .LC6(%rip), %r14
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@GOTPCREL(%rip), %rsi
movq %rax, %rdi
call _ZNSolsEPFRSoS_E.isra.0
.L19:
movq %r13, %rdi
cvtss2sd (%rbx,%r12,4), %xmm0
incq %r12
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %r14, %rsi
movq %rax, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
cmpq $10, %r12
jne .L19
movq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@GOTPCREL(%rip), %rsi
movq %r13, %rdi
call _ZNSolsEPFRSoS_E.isra.0
movq (%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq %rbx, %rdi
call _ZdaPv@PLT
movq %rbp, %rdi
call _ZdaPv@PLT
xorl %eax, %eax
.L9:
movq 40(%rsp), %rdx
subq %fs:40, %rdx
je .L20
call __stack_chk_fail@PLT
.L20:
addq $48, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3635:
.size main, .-main
.section .rodata.str1.1
.LC7:
.string "_Z21fluidSimulationKernelPfS_i"
.section .text.startup
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3663:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
pushq $0
.cfi_def_cfa_offset 24
xorl %r9d, %r9d
orl $-1, %r8d
pushq $0
.cfi_def_cfa_offset 32
leaq .LC7(%rip), %rdx
movq %rax, %rdi
leaq _Z21fluidSimulationKernelPfS_i(%rip), %rsi
pushq $0
.cfi_def_cfa_offset 40
movq %rdx, %rcx
pushq $0
.cfi_def_cfa_offset 48
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFunction@PLT
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
addq $32, %rsp
.cfi_def_cfa_offset 16
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
popq %rdx
.cfi_def_cfa_offset 8
jmp atexit@PLT
.cfi_endproc
.LFE3663:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
```
|
```amdasm
.text
.file "cuda_code_081934.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z36__device_stub__fluidSimulationKernelPfS_i # -- Begin function _Z36__device_stub__fluidSimulationKernelPfS_i
.type _Z36__device_stub__fluidSimulationKernelPfS_i,@function
_Z36__device_stub__fluidSimulationKernelPfS_i: # @_Z36__device_stub__fluidSimulationKernelPfS_i
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $112, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 40(%rsp), %rax
movq %rdi, (%rax)
leaq 32(%rsp), %rcx
movq %rsi, (%rcx)
leaq 12(%rsp), %rsi
movl %edx, (%rsi)
leaq 80(%rsp), %rbx
movq %rax, (%rbx)
movq %rcx, 8(%rbx)
movq %rsi, 16(%rbx)
leaq 64(%rsp), %r14
leaq 48(%rsp), %r15
leaq 24(%rsp), %r12
leaq 16(%rsp), %r13
movq %r14, %rdi
movq %r15, %rsi
movq %r12, %rdx
movq %r13, %rcx
callq __hipPopCallConfiguration
movq (%r14), %rsi
movl 8(%r14), %edx
movq (%r15), %rcx
movl 8(%r15), %r8d
movl $_Z21fluidSimulationKernelPfS_i, %edi
movq %rbx, %r9
pushq (%r13)
.cfi_adjust_cfa_offset 8
pushq (%r12)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $128, %rsp
.cfi_adjust_cfa_offset -128
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z36__device_stub__fluidSimulationKernelPfS_i, .Lfunc_end0-_Z36__device_stub__fluidSimulationKernelPfS_i
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $16, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %rbp, -16
movl $1024, %edi # imm = 0x400
callq _Znam
movq %rax, %rbx
xorl %eax, %eax
.LBB1_1: # =>This Inner Loop Header: Depth=1
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movss %xmm0, (%rbx,%rax,4)
incq %rax
cmpq $256, %rax # imm = 0x100
jne .LBB1_1
# %bb.2:
movq %rsp, %rdi
movl $1024, %esi # imm = 0x400
callq hipMalloc
testl %eax, %eax
je .LBB1_4
# %bb.3:
movl $_ZSt4cerr, %ebx
movl $_ZSt4cerr, %edi
movl $.L.str, %esi
movl $46, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cerr(%rip), %rax
movq -24(%rax), %rdi
addq %rbx, %rdi
movl $10, %esi
callq _ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
movsbl %al, %esi
movl $_ZSt4cerr, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
jmp .LBB1_20
.LBB1_4:
leaq 8(%rsp), %rdi
movl $1024, %esi # imm = 0x400
callq hipMalloc
testl %eax, %eax
je .LBB1_6
# %bb.5:
movl $_ZSt4cerr, %ebx
movl $_ZSt4cerr, %edi
movl $.L.str.1, %esi
movl $39, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cerr(%rip), %rax
movq -24(%rax), %rdi
addq %rbx, %rdi
movl $10, %esi
callq _ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
movsbl %al, %esi
movl $_ZSt4cerr, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq (%rsp), %rdi
jmp .LBB1_19
.LBB1_6:
movq (%rsp), %rdi
movl $1024, %edx # imm = 0x400
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
je .LBB1_8
# %bb.7:
movl $_ZSt4cerr, %ebx
movl $_ZSt4cerr, %edi
movl $.L.str.2, %esi
movl $35, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cerr(%rip), %rax
movq -24(%rax), %rdi
addq %rbx, %rdi
jmp .LBB1_17
.LBB1_8:
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 255(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_10
# %bb.9:
movq (%rsp), %rdi
movq 8(%rsp), %rsi
movl $256, %edx # imm = 0x100
callq _Z36__device_stub__fluidSimulationKernelPfS_i
.LBB1_10:
callq hipGetLastError
testl %eax, %eax
je .LBB1_13
# %bb.11:
movl %eax, %ebp
movl $_ZSt4cerr, %edi
movl $.L.str.3, %esi
movl $24, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl %ebp, %edi
callq hipGetErrorString
testq %rax, %rax
je .LBB1_15
# %bb.12:
movq %rax, %rbx
movq %rax, %rdi
callq strlen
movl $_ZSt4cerr, %edi
movq %rbx, %rsi
movq %rax, %rdx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
jmp .LBB1_16
.LBB1_13:
movq (%rsp), %rsi
movl $1024, %edx # imm = 0x400
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
je .LBB1_22
# %bb.14:
movl $_ZSt4cerr, %edi
movl $.L.str.4, %esi
movl $37, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cerr, %edi
callq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_
jmp .LBB1_18
.LBB1_15:
movq _ZSt4cerr(%rip), %rax
movq -24(%rax), %rax
leaq _ZSt4cerr(%rax), %rdi
movl 32(%rdi), %esi
orl $1, %esi
callq _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate
.LBB1_16: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit
movq _ZSt4cerr(%rip), %rax
movl $_ZSt4cerr, %ecx
movq -24(%rax), %rdi
addq %rcx, %rdi
.LBB1_17:
movl $10, %esi
callq _ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
movsbl %al, %esi
movl $_ZSt4cerr, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
.LBB1_18:
movq (%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
.LBB1_19:
callq hipFree
.LBB1_20:
movl $-1, %eax
.LBB1_21:
addq $16, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB1_22:
.cfi_def_cfa_offset 48
movl $_ZSt4cout, %edi
movl $.L.str.5, %esi
movl $20, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
callq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_
xorl %r14d, %r14d
.LBB1_23: # =>This Inner Loop Header: Depth=1
xorps %xmm0, %xmm0
cvtss2sd (%rbx,%r14,4), %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movl $.L.str.6, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
incq %r14
cmpq $10, %r14
jne .LBB1_23
# %bb.24:
movl $_ZSt4cout, %edi
callq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_
movq (%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq %rbx, %rdi
callq _ZdaPv
xorl %eax, %eax
jmp .LBB1_21
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, %rdi
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z21fluidSimulationKernelPfS_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z21fluidSimulationKernelPfS_i,@object # @_Z21fluidSimulationKernelPfS_i
.section .rodata,"a",@progbits
.globl _Z21fluidSimulationKernelPfS_i
.p2align 3, 0x0
_Z21fluidSimulationKernelPfS_i:
.quad _Z36__device_stub__fluidSimulationKernelPfS_i
.size _Z21fluidSimulationKernelPfS_i, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Error allocating device memory for fluid field"
.size .L.str, 47
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Error allocating device memory for flux"
.size .L.str.1, 40
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Error copying fluid field to device"
.size .L.str.2, 36
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Error launching kernel: "
.size .L.str.3, 25
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Error copying fluid field from device"
.size .L.str.4, 38
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "Updated fluid field:"
.size .L.str.5, 21
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz " "
.size .L.str.6, 2
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z21fluidSimulationKernelPfS_i"
.size .L__unnamed_1, 31
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z36__device_stub__fluidSimulationKernelPfS_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z21fluidSimulationKernelPfS_i
.addrsig_sym _ZSt4cerr
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
```
| 4,122 | 5,080 |
113,692 |
Convert the following CUDA device assembly code to AMD device assembly:
```cudaasm
code for sm_80
Function : _Z9bfsKernelPiS_S_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ;
IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x160] ;
MOV R3, c[0x0][0x164] ;
ULDC.64 UR4, c[0x0][0x118] ;
LDG.E R0, [R2.64] ;
BSSY B0, 0xe0 ;
S2R R11, SR_TID.X ;
ISETP.GE.AND P0, PT, R11, R0, PT ;
@P0 BRA 0xd0 ;
IMAD.MOV.U32 R4, RZ, RZ, 0x4 ;
IMAD.WIDE R4, R11, R4, c[0x0][0x160] ;
LDG.E R4, [R4.64+0x4] ;
STS [R11.X4], R4 ;
BSYNC B0 ;
BAR.SYNC.DEFER_BLOCKING 0x0 ;
@P0 BRA 0x280 ;
MOV R9, R11 ;
LDS R4, [R9.X4] ;
IMAD.MOV.U32 R5, RZ, RZ, 0x4 ;
IMAD.WIDE R4, R4, R5, c[0x0][0x178] ;
LDG.E R13, [R4.64+0x4] ;
LDG.E R6, [R4.64] ;
BSSY B0, 0x250 ;
ISETP.GE.AND P0, PT, R6, R13, PT ;
@P0 BRA 0x240 ;
MOV R8, R6 ;
IMAD.MOV.U32 R7, RZ, RZ, 0x4 ;
IMAD.WIDE R4, R8, R7, c[0x0][0x170] ;
LDG.E R4, [R4.64] ;
IMAD.WIDE R6, R4, R7, c[0x0][0x168] ;
LDG.E R10, [R6.64] ;
ISETP.NE.AND P0, PT, R10, RZ, PT ;
@!P0 BRA 0x2e0 ;
IADD3 R8, R8, 0x1, RZ ;
ISETP.GE.AND P0, PT, R8, R13, PT ;
@!P0 BRA 0x1a0 ;
BSYNC B0 ;
IADD3 R9, R9, c[0x0][0x0], RZ ;
ISETP.GE.AND P0, PT, R9, R0, PT ;
@!P0 BRA 0x110 ;
WARPSYNC 0xffffffff ;
BAR.SYNC.DEFER_BLOCKING 0x0 ;
ISETP.NE.AND P0, PT, R11, RZ, PT ;
@P0 EXIT ;
STG.E [R2.64], RZ ;
EXIT ;
HFMA2.MMA R1, -RZ, RZ, 0, 5.9604644775390625e-08 ;
STG.E [R6.64], R1 ;
BPT.TRAP 0x1 ;
BRA 0x310;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
```
|
```amdasm
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9bfsKernelPiS_S_S_i ; -- Begin function _Z9bfsKernelPiS_S_S_i
.globl _Z9bfsKernelPiS_S_S_i
.p2align 8
.type _Z9bfsKernelPiS_S_S_i,@function
_Z9bfsKernelPiS_S_S_i: ; @_Z9bfsKernelPiS_S_S_i
; %bb.0:
s_load_b256 s[4:11], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_load_b32 s2, s[4:5], 0x0
s_waitcnt lgkmcnt(0)
v_cmp_gt_i32_e32 vcc_lo, s2, v0
s_and_saveexec_b32 s3, vcc_lo
s_cbranch_execz .LBB0_2
; %bb.1:
v_lshlrev_b32_e32 v1, 2, v0
global_load_b32 v2, v1, s[4:5] offset:4
v_add_nc_u32_e32 v1, 0, v1
s_waitcnt vmcnt(0)
ds_store_b32 v1, v2
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s3
s_load_b32 s0, s[0:1], 0x34
v_mov_b32_e32 v1, 0
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
scratch_store_b32 off, v1, off offset:4
s_and_saveexec_b32 s1, vcc_lo
s_cbranch_execz .LBB0_12
; %bb.3: ; %.lr.ph40
v_dual_mov_b32 v10, 1 :: v_dual_mov_b32 v11, v0
s_and_b32 s3, 0xffff, s0
s_add_u32 s12, s4, 4
s_addc_u32 s14, s5, 0
s_mov_b32 s13, 0
.LBB0_4: ; =>This Loop Header: Depth=1
; Child Loop BB0_6 Depth 2
v_lshl_add_u32 v2, v11, 2, 0
s_mov_b32 s15, exec_lo
ds_load_b32 v2, v2
s_waitcnt lgkmcnt(0)
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[2:3]
v_add_co_u32 v2, vcc_lo, s10, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s11, v3, vcc_lo
global_load_b64 v[3:4], v[2:3], off
s_waitcnt vmcnt(0)
v_cmpx_lt_i32_e64 v3, v4
s_cbranch_execz .LBB0_10
; %bb.5: ; %.lr.ph.preheader
; in Loop: Header=BB0_4 Depth=1
v_ashrrev_i32_e32 v6, 31, v3
v_mov_b32_e32 v5, v3
s_mov_b32 s16, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[5:6], 2, v[5:6]
v_add_co_u32 v5, vcc_lo, s8, v5
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v6, vcc_lo, s9, v6, vcc_lo
.LBB0_6: ; %.lr.ph
; Parent Loop BB0_4 Depth=1
; => This Inner Loop Header: Depth=2
global_load_b32 v7, v[5:6], off
s_mov_b32 s0, exec_lo
s_waitcnt vmcnt(0)
v_ashrrev_i32_e32 v8, 31, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[8:9], 2, v[7:8]
v_add_co_u32 v8, vcc_lo, s6, v8
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v9, vcc_lo, s7, v9, vcc_lo
global_load_b32 v2, v[8:9], off
s_waitcnt vmcnt(0)
v_cmpx_eq_u32_e32 0, v2
s_cbranch_execz .LBB0_8
; %bb.7: ; in Loop: Header=BB0_6 Depth=2
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[12:13], 2, v[1:2]
v_add_nc_u32_e32 v1, 1, v1
v_add_co_u32 v12, vcc_lo, s12, v12
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v13, vcc_lo, s14, v13, vcc_lo
global_store_b32 v[8:9], v10, off
global_store_b32 v[12:13], v7, off
.LBB0_8: ; in Loop: Header=BB0_6 Depth=2
s_or_b32 exec_lo, exec_lo, s0
v_add_nc_u32_e32 v3, 1, v3
v_add_co_u32 v5, s0, v5, 4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e64 v6, s0, 0, v6, s0
v_cmp_ge_i32_e32 vcc_lo, v3, v4
s_or_b32 s16, vcc_lo, s16
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s16
s_cbranch_execnz .LBB0_6
; %bb.9: ; %Flow
; in Loop: Header=BB0_4 Depth=1
s_or_b32 exec_lo, exec_lo, s16
.LBB0_10: ; %Flow59
; in Loop: Header=BB0_4 Depth=1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
s_or_b32 exec_lo, exec_lo, s15
v_add_nc_u32_e32 v11, s3, v11
v_cmp_le_i32_e32 vcc_lo, s2, v11
s_or_b32 s13, vcc_lo, s13
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s13
s_cbranch_execnz .LBB0_4
; %bb.11: ; %._crit_edge41.loopexit
s_or_b32 exec_lo, exec_lo, s13
scratch_store_b32 off, v1, off offset:4
.LBB0_12: ; %Flow60
s_or_b32 exec_lo, exec_lo, s1
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
s_mov_b32 s0, exec_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB0_14
; %bb.13:
scratch_load_b32 v0, off, off offset:4
v_mov_b32_e32 v1, 0
s_waitcnt vmcnt(0)
global_store_b32 v1, v0, s[4:5]
.LBB0_14:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9bfsKernelPiS_S_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 8
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 1
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 14
.amdhsa_next_free_sgpr 17
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9bfsKernelPiS_S_S_i, .Lfunc_end0-_Z9bfsKernelPiS_S_S_i
; -- End function
.section .AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 544
; NumSgprs: 19
; NumVgprs: 14
; ScratchSize: 8
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 19
; NumVGPRsForWavesPerEU: 14
; Occupancy: 16
; WaveLimiterHint : 1
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 1
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object ; @__hip_cuid_
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0 ; 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
- .offset: 160
.size: 4
.value_kind: hidden_dynamic_lds_size
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9bfsKernelPiS_S_S_i
.private_segment_fixed_size: 8
.sgpr_count: 19
.sgpr_spill_count: 0
.symbol: _Z9bfsKernelPiS_S_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 14
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
```
| 890 | 4,116 |
113,693 |
Convert the following CUDA host assembly code to AMD host assembly:
```cudaasm
.file "tmpxft_001396d5_00000000-6_cuda_code_046943.cudafe1.cpp"
.text
.globl _ZSt21ios_base_library_initv
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB6836:
.cfi_startproc
endbr64
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
jmp __cudaUnregisterFatBinary@PLT
.cfi_endproc
.LFE6836:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z15initializeGraphR5GraphPiS1_
.type _Z15initializeGraphR5GraphPiS1_, @function
_Z15initializeGraphR5GraphPiS1_:
.LFB6832:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
movq %rsi, %r12
movl $32768, %esi
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
movq %rdx, %rbp
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
movq %rdi, %rbx
call cudaMalloc@PLT
leaq 8(%rbx), %rdi
movl $16388, %esi
call cudaMalloc@PLT
movq (%rbx), %rdi
movq %r12, %rsi
movl $1, %ecx
movl $32768, %edx
call cudaMemcpy@PLT
movq 8(%rbx), %rdi
movq %rbp, %rsi
popq %rbx
.cfi_def_cfa_offset 24
movl $1, %ecx
popq %rbp
.cfi_def_cfa_offset 16
movl $16388, %edx
popq %r12
.cfi_def_cfa_offset 8
jmp cudaMemcpy@PLT
.cfi_endproc
.LFE6832:
.size _Z15initializeGraphR5GraphPiS1_, .-_Z15initializeGraphR5GraphPiS1_
.globl _Z35__device_stub__Z9bfsKernelPiS_S_S_iPiS_S_S_i
.type _Z35__device_stub__Z9bfsKernelPiS_S_S_iPiS_S_S_i, @function
_Z35__device_stub__Z9bfsKernelPiS_S_S_iPiS_S_S_i:
.LFB6858:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 40(%rsp)
leaq 64(%rsp), %rdi
movq %rsi, 32(%rsp)
leaq 76(%rsp), %rsi
movq %rdx, 24(%rsp)
leaq 48(%rsp), %rdx
movq %rcx, 16(%rsp)
leaq 56(%rsp), %rcx
movl %r8d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movl $1, 72(%rsp)
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 12(%rsp), %rax
movq %rax, 144(%rsp)
movabsq $4294967297, %rax
movq %rax, 64(%rsp)
movq %rax, 76(%rsp)
movl $1, 84(%rsp)
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
jne .L4
pushq 56(%rsp)
.cfi_def_cfa_offset 184
leaq _Z9bfsKernelPiS_S_S_i(%rip), %rdi
pushq 56(%rsp)
.cfi_def_cfa_offset 192
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq 128(%rsp), %r9
call cudaLaunchKernel@PLT
popq %rax
.cfi_def_cfa_offset 184
popq %rdx
.cfi_def_cfa_offset 176
.L4:
movq 152(%rsp), %rax
subq %fs:40, %rax
je .L6
call __stack_chk_fail@PLT
.L6:
addq $168, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE6858:
.size _Z35__device_stub__Z9bfsKernelPiS_S_S_iPiS_S_S_i, .-_Z35__device_stub__Z9bfsKernelPiS_S_S_iPiS_S_S_i
.globl _Z9bfsKernelPiS_S_S_i
.type _Z9bfsKernelPiS_S_S_i, @function
_Z9bfsKernelPiS_S_S_i:
.LFB6859:
.cfi_startproc
endbr64
jmp _Z35__device_stub__Z9bfsKernelPiS_S_S_iPiS_S_S_i
.cfi_endproc
.LFE6859:
.size _Z9bfsKernelPiS_S_S_i, .-_Z9bfsKernelPiS_S_S_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "BFS completed successfully."
.section .text.startup,"ax",@progbits
.globl main
.type main, @function
main:
.LFB6833:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
leaq -32768(%rsp), %r11
.cfi_def_cfa 11, 32808
.LPSRL0:
subq $4096, %rsp
orq $0, (%rsp)
cmpq %r11, %rsp
jne .LPSRL0
.cfi_def_cfa_register 7
subq $88, %rsp
.cfi_def_cfa_offset 32896
movl $4097, %ecx
movq %fs:40, %rax
movq %rax, 32840(%rsp)
xorl %eax, %eax
leaq 16452(%rsp), %rdi
leaq 16452(%rsp), %r12
rep stosl
leaq 68(%rsp), %rdi
movl $4096, %ecx
rep stosl
movl $32768, %edi
call _Znam@PLT
movl $16388, %edi
movq %rax, %rbp
call _Znam@PLT
movq %rax, %rbx
xorl %eax, %eax
.L11:
leal (%rax,%rax), %edx
movl %edx, (%rbx,%rax,4)
leal 1(%rax), %edx
andl $4095, %edx
movl %edx, 0(%rbp,%rax,8)
leal 4095(%rax), %edx
andl $4095, %edx
movl %edx, 4(%rbp,%rax,8)
incq %rax
cmpq $4096, %rax
jne .L11
movl $8192, 16384(%rbx)
leaq 8(%rsp), %rdi
movl $16388, %esi
movabsq $4294967552, %r13
movq $1, 16452(%rsp)
movl $1, 68(%rsp)
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $16384, %esi
call cudaMalloc@PLT
movq 8(%rsp), %rdi
movl $1, %ecx
movq %r12, %rsi
movl $16388, %edx
call cudaMemcpy@PLT
movq 16(%rsp), %rdi
movl $1, %ecx
movl $16384, %edx
leaq 68(%rsp), %rsi
call cudaMemcpy@PLT
leaq 48(%rsp), %rdi
movq %rbx, %rdx
movq %rbp, %rsi
call _Z15initializeGraphR5GraphPiS1_
.L12:
cmpl $0, 16452(%rsp)
jle .L18
movl $268435457, %edi
xorl %r9d, %r9d
movq %r13, %rdx
movl $1, %ecx
salq $4, %rdi
movl $1024, %r8d
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L13
movq 56(%rsp), %rcx
movq 48(%rsp), %rdx
movl $4096, %r8d
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z35__device_stub__Z9bfsKernelPiS_S_S_iPiS_S_S_i
.L13:
call cudaDeviceSynchronize@PLT
movq 8(%rsp), %rsi
movl $2, %ecx
movq %r12, %rdi
movl $4, %edx
call cudaMemcpy@PLT
jmp .L12
.L18:
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 48(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rdi
call cudaFree@PLT
movq %rbp, %rdi
call _ZdaPv@PLT
movq %rbx, %rdi
call _ZdaPv@PLT
leaq _ZSt4cout(%rip), %rdi
leaq .LC0(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq 32840(%rsp), %rax
subq %fs:40, %rax
je .L15
call __stack_chk_fail@PLT
.L15:
addq $32856, %rsp
.cfi_def_cfa_offset 40
xorl %eax, %eax
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE6833:
.size main, .-main
.section .rodata.str1.1
.LC1:
.string "_Z9bfsKernelPiS_S_S_i"
.LC2:
.string "_ZN50_INTERNAL_cbbbbc8f_19_cuda_code_046943_cu_2f41af5d4cuda3std3__419piecewise_constructE"
.LC3:
.string "_ZN50_INTERNAL_cbbbbc8f_19_cuda_code_046943_cu_2f41af5d4cuda3std6ranges3__45__cpo4swapE"
.LC4:
.string "_ZN50_INTERNAL_cbbbbc8f_19_cuda_code_046943_cu_2f41af5d4cuda3std6ranges3__45__cpo9iter_moveE"
.section .text.startup
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB6861:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
pushq $0
.cfi_def_cfa_offset 24
xorl %r9d, %r9d
orl $-1, %r8d
pushq $0
.cfi_def_cfa_offset 32
leaq .LC1(%rip), %rdx
movq %rax, %rdi
movq %rax, %rbx
pushq $0
.cfi_def_cfa_offset 40
movq %rdx, %rcx
leaq _Z9bfsKernelPiS_S_S_i(%rip), %rsi
pushq $0
.cfi_def_cfa_offset 48
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq %rbx, %rdi
xorl %r8d, %r8d
pushq $0
.cfi_def_cfa_offset 24
leaq .LC2(%rip), %rdx
movl $1, %r9d
leaq _ZN4cuda3std3__419piecewise_constructE(%rip), %rsi
pushq $0
.cfi_def_cfa_offset 32
movq %rdx, %rcx
call __cudaRegisterVar@PLT
popq %rax
.cfi_def_cfa_offset 24
popq %rdx
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
leaq .LC3(%rip), %rdx
movq %rbx, %rdi
xorl %r8d, %r8d
movq %rdx, %rcx
movl $1, %r9d
leaq _ZN4cuda3std6ranges3__45__cpo4swapE(%rip), %rsi
call __cudaRegisterVar@PLT
popq %rcx
.cfi_def_cfa_offset 24
popq %rsi
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
leaq .LC4(%rip), %rdx
movq %rbx, %rdi
xorl %r8d, %r8d
movl $1, %r9d
movq %rdx, %rcx
leaq _ZN4cuda3std6ranges3__45__cpo9iter_moveE(%rip), %rsi
call __cudaRegisterVar@PLT
popq %rdi
.cfi_def_cfa_offset 24
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
popq %r8
.cfi_def_cfa_offset 16
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit@PLT
.cfi_endproc
.LFE6861:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.weak _ZN4cuda3std3__419piecewise_constructE
.section .rodata._ZN4cuda3std3__419piecewise_constructE,"aG",@progbits,_ZN4cuda3std3__419piecewise_constructE,comdat
.type _ZN4cuda3std3__419piecewise_constructE, @gnu_unique_object
.size _ZN4cuda3std3__419piecewise_constructE, 1
_ZN4cuda3std3__419piecewise_constructE:
.zero 1
.weak _ZN4cuda3std6ranges3__45__cpo9iter_moveE
.section .rodata._ZN4cuda3std6ranges3__45__cpo9iter_moveE,"aG",@progbits,_ZN4cuda3std6ranges3__45__cpo9iter_moveE,comdat
.type _ZN4cuda3std6ranges3__45__cpo9iter_moveE, @gnu_unique_object
.size _ZN4cuda3std6ranges3__45__cpo9iter_moveE, 1
_ZN4cuda3std6ranges3__45__cpo9iter_moveE:
.zero 1
.weak _ZN4cuda3std6ranges3__45__cpo4swapE
.section .rodata._ZN4cuda3std6ranges3__45__cpo4swapE,"aG",@progbits,_ZN4cuda3std6ranges3__45__cpo4swapE,comdat
.type _ZN4cuda3std6ranges3__45__cpo4swapE, @gnu_unique_object
.size _ZN4cuda3std6ranges3__45__cpo4swapE, 1
_ZN4cuda3std6ranges3__45__cpo4swapE:
.zero 1
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
```
|
```amdasm
.text
.file "cuda_code_046943.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z24__device_stub__bfsKernelPiS_S_S_i # -- Begin function _Z24__device_stub__bfsKernelPiS_S_S_i
.type _Z24__device_stub__bfsKernelPiS_S_S_i,@function
_Z24__device_stub__bfsKernelPiS_S_S_i: # @_Z24__device_stub__bfsKernelPiS_S_S_i
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $144, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 56(%rsp), %rax
movq %rdi, (%rax)
leaq 48(%rsp), %rdi
movq %rsi, (%rdi)
leaq 40(%rsp), %rsi
movq %rdx, (%rsi)
leaq 32(%rsp), %rdx
movq %rcx, (%rdx)
leaq 12(%rsp), %rcx
movl %r8d, (%rcx)
leaq 96(%rsp), %rbx
movq %rax, (%rbx)
movq %rdi, 8(%rbx)
movq %rsi, 16(%rbx)
movq %rdx, 24(%rbx)
movq %rcx, 32(%rbx)
leaq 80(%rsp), %r14
leaq 64(%rsp), %r15
leaq 24(%rsp), %r12
leaq 16(%rsp), %r13
movq %r14, %rdi
movq %r15, %rsi
movq %r12, %rdx
movq %r13, %rcx
callq __hipPopCallConfiguration
movq (%r14), %rsi
movl 8(%r14), %edx
movq (%r15), %rcx
movl 8(%r15), %r8d
movl $_Z9bfsKernelPiS_S_S_i, %edi
movq %rbx, %r9
pushq (%r13)
.cfi_adjust_cfa_offset 8
pushq (%r12)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $160, %rsp
.cfi_adjust_cfa_offset -160
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z24__device_stub__bfsKernelPiS_S_S_i, .Lfunc_end0-_Z24__device_stub__bfsKernelPiS_S_S_i
.cfi_endproc
# -- End function
.globl _Z15initializeGraphR5GraphPiS1_ # -- Begin function _Z15initializeGraphR5GraphPiS1_
.type _Z15initializeGraphR5GraphPiS1_,@function
_Z15initializeGraphR5GraphPiS1_: # @_Z15initializeGraphR5GraphPiS1_
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rdx, %rbx
movq %rsi, %r14
movq %rdi, %r15
movl $32768, %esi # imm = 0x8000
callq hipMalloc
leaq 8(%r15), %rdi
movl $16388, %esi # imm = 0x4004
callq hipMalloc
movq (%r15), %rdi
movl $32768, %edx # imm = 0x8000
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movq 8(%r15), %rdi
movl $16388, %edx # imm = 0x4004
movq %rbx, %rsi
movl $1, %ecx
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
jmp hipMemcpy # TAILCALL
.Lfunc_end1:
.size _Z15initializeGraphR5GraphPiS1_, .Lfunc_end1-_Z15initializeGraphR5GraphPiS1_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $32824, %rsp # imm = 0x8038
.cfi_def_cfa_offset 32880
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
leaq 32(%rsp), %rdi
xorl %r15d, %r15d
movl $16388, %edx # imm = 0x4004
xorl %esi, %esi
callq memset@PLT
leaq 16432(%rsp), %rdi
movl $16384, %edx # imm = 0x4000
xorl %esi, %esi
callq memset@PLT
movl $32768, %edi # imm = 0x8000
callq _Znam
movq %rax, %rbx
movl $16388, %edi # imm = 0x4004
callq _Znam
movq %rax, %r14
movl $4095, %eax # imm = 0xFFF
xorl %ecx, %ecx
.LBB2_1: # =>This Inner Loop Header: Depth=1
movl %r15d, (%r14,%rcx,4)
leaq 1(%rcx), %rdx
movl %edx, %esi
andl %eax, %esi
movl %esi, (%rbx,%rcx,8)
leal -1(%rcx), %esi
andl %eax, %esi
movl %esi, 4(%rbx,%rcx,8)
addl $2, %r15d
movq %rdx, %rcx
cmpq $4096, %rdx # imm = 0x1000
jne .LBB2_1
# %bb.2:
movl $8192, 16384(%r14) # imm = 0x2000
leaq 32(%rsp), %r15
movq $1, (%r15)
leaq 16432(%rsp), %r12
movl $1, (%r12)
movq %rsp, %r13
movl $16388, %esi # imm = 0x4004
movq %r13, %rdi
callq hipMalloc
leaq 8(%rsp), %rbp
movl $16384, %esi # imm = 0x4000
movq %rbp, %rdi
callq hipMalloc
movq (%r13), %rdi
movl $16388, %edx # imm = 0x4004
movq %r15, %rsi
movl $1, %ecx
callq hipMemcpy
movq (%rbp), %rdi
movl $16384, %edx # imm = 0x4000
movq %r12, %rsi
movl $1, %ecx
callq hipMemcpy
leaq 16(%rsp), %rdi
movq %rbx, %rsi
movq %r14, %rdx
callq _Z15initializeGraphR5GraphPiS1_
cmpl $0, (%r15)
jle .LBB2_7
# %bb.3: # %.lr.ph
movabsq $4294967312, %r15 # imm = 0x100000010
leaq 240(%r15), %r12
leaq 32(%rsp), %r13
.LBB2_4: # =>This Inner Loop Header: Depth=1
movl $1024, %r8d # imm = 0x400
movq %r15, %rdi
movl $1, %esi
movq %r12, %rdx
movl $1, %ecx
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_6
# %bb.5: # in Loop: Header=BB2_4 Depth=1
movq (%rsp), %rdi
movq 8(%rsp), %rsi
movq 16(%rsp), %rdx
movq 24(%rsp), %rcx
movl $4096, %r8d # imm = 0x1000
callq _Z24__device_stub__bfsKernelPiS_S_S_i
.LBB2_6: # in Loop: Header=BB2_4 Depth=1
callq hipDeviceSynchronize
movq (%rsp), %rsi
movl $4, %edx
movq %r13, %rdi
movl $2, %ecx
callq hipMemcpy
cmpl $0, 32(%rsp)
jg .LBB2_4
.LBB2_7: # %._crit_edge
movq (%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
movq %rbx, %rdi
callq _ZdaPv
movq %r14, %rdi
callq _ZdaPv
movl $_ZSt4cout, %ebx
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $27, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rdi
addq %rbx, %rdi
movl $10, %esi
callq _ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
xorl %eax, %eax
addq $32824, %rsp # imm = 0x8038
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, %rdi
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9bfsKernelPiS_S_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9bfsKernelPiS_S_S_i,@object # @_Z9bfsKernelPiS_S_S_i
.section .rodata,"a",@progbits
.globl _Z9bfsKernelPiS_S_S_i
.p2align 3, 0x0
_Z9bfsKernelPiS_S_S_i:
.quad _Z24__device_stub__bfsKernelPiS_S_S_i
.size _Z9bfsKernelPiS_S_S_i, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "BFS completed successfully."
.size .L.str, 28
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z9bfsKernelPiS_S_S_i"
.size .L__unnamed_1, 22
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__bfsKernelPiS_S_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9bfsKernelPiS_S_S_i
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
```
| 5,068 | 4,744 |
113,698 |
Convert the following CUDA device assembly code to AMD device assembly:
```cudaasm
code for sm_80
Function : _Z18convBackpropKernelPfS_S_S_S_iiiiii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ;
S2R R3, SR_CTAID.Y ;
ULDC.64 UR6, c[0x0][0x118] ;
S2R R0, SR_CTAID.X ;
S2R R9, SR_TID.X ;
S2R R6, SR_TID.Y ;
IMAD R7, R0, 0x10, R9 ;
IMAD R4, R3, 0x10, R6 ;
IADD3 R5, R7, -c[0x0][0x19c], RZ ;
ISETP.GE.AND P1, PT, R6, c[0x0][0x194], PT ;
IADD3 R0, R4, -c[0x0][0x19c], RZ ;
ISETP.LT.AND P1, PT, R9, c[0x0][0x190], !P1 ;
LOP3.LUT R2, R5, R0, RZ, 0xfc, !PT ;
ISETP.GT.AND P0, PT, R2, -0x1, PT ;
ISETP.LT.AND P0, PT, R5, c[0x0][0x188], P0 ;
@P1 IMAD.MOV.U32 R15, RZ, RZ, 0x4 ;
ISETP.LT.AND P0, PT, R0, c[0x0][0x18c], P0 ;
@P1 IMAD R14, R6, c[0x0][0x190], R9 ;
@P0 IMAD.MOV.U32 R13, RZ, RZ, 0x4 ;
@P0 IMAD R12, R0, c[0x0][0x188], R5 ;
@P0 IMAD.WIDE R12, R12, R13, c[0x0][0x160] ;
@P0 LDG.E R3, [R12.64] ;
@P1 IMAD.WIDE R14, R14, R15, c[0x0][0x168] ;
@P1 LDG.E R2, [R14.64] ;
IABS R8, c[0x0][0x198] ;
ULDC UR4, c[0x0][0x188] ;
BSSY B0, 0xcf0 ;
IMAD.MOV.U32 R12, RZ, RZ, c[0x0][0x18c] ;
I2F.RP R16, R8 ;
ULDC UR5, c[0x0][0x190] ;
UIADD3 UR4, UR4, -UR5, URZ ;
IADD3 R12, R12, -c[0x0][0x194], RZ ;
IMAD.MOV.U32 R15, RZ, RZ, c[0x0][0x19c] ;
IMAD R13, R15.reuse, 0x2, R12 ;
LEA R12, R15, UR4, 0x1 ;
IABS R15, R13 ;
MUFU.RCP R16, R16 ;
LOP3.LUT R13, R13, c[0x0][0x198], RZ, 0x3c, !PT ;
ISETP.GE.AND P2, PT, R13, RZ, PT ;
IADD3 R10, R16, 0xffffffe, RZ ;
F2I.FTZ.U32.TRUNC.NTZ R11, R10 ;
IMAD.MOV.U32 R10, RZ, RZ, RZ ;
IMAD.MOV R17, RZ, RZ, -R11 ;
IMAD R17, R17, R8, RZ ;
IMAD.HI.U32 R10, R11, R17, R10 ;
IABS R11, R12 ;
LOP3.LUT R12, R12, c[0x0][0x198], RZ, 0x3c, !PT ;
IMAD.HI.U32 R14, R10, R15, RZ ;
IMAD.HI.U32 R10, R10, R11, RZ ;
IMAD.MOV R17, RZ, RZ, -R14 ;
IMAD.MOV R16, RZ, RZ, -R10 ;
IMAD R15, R8.reuse, R17, R15 ;
IMAD R11, R8, R16, R11 ;
ISETP.GT.U32.AND P6, PT, R8.reuse, R15, PT ;
ISETP.GT.U32.AND P5, PT, R8, R11, PT ;
@!P6 IMAD.IADD R15, R15, 0x1, -R8.reuse ;
@!P6 IADD3 R14, R14, 0x1, RZ ;
@!P5 IMAD.IADD R11, R11, 0x1, -R8 ;
@!P5 IADD3 R10, R10, 0x1, RZ ;
ISETP.GE.U32.AND P3, PT, R15, R8.reuse, PT ;
ISETP.GE.U32.AND P4, PT, R11, R8, PT ;
IMAD.SHL.U32 R11, R9, 0x4, RZ ;
ISETP.GE.AND P5, PT, R12, RZ, PT ;
IMAD.MOV.U32 R8, RZ, RZ, RZ ;
IMAD R13, R6, 0x40, R11 ;
LOP3.LUT R11, RZ, c[0x0][0x198], RZ, 0x33, !PT ;
@!P0 STS [R13], RZ ;
@P3 IADD3 R14, R14, 0x1, RZ ;
@P4 IADD3 R10, R10, 0x1, RZ ;
@!P1 STS [R13+0x400], RZ ;
ISETP.NE.AND P3, PT, RZ, c[0x0][0x198], PT ;
@!P2 IMAD.MOV R14, RZ, RZ, -R14 ;
@!P5 IMAD.MOV R10, RZ, RZ, -R10 ;
SEL R15, R11.reuse, R14, !P3 ;
SEL R12, R11, R10, !P3 ;
IMAD.MOV.U32 R10, RZ, RZ, RZ ;
ISETP.GT.AND P2, PT, R4, R15, PT ;
ISETP.GT.OR P2, PT, R7, R12, P2 ;
@P0 STS [R13], R3 ;
@P1 STS [R13+0x400], R2 ;
IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x194] ;
BAR.SYNC 0x0 ;
ISETP.LT.OR P2, PT, R3, 0x1, P2 ;
@P2 BRA 0xce0 ;
IMAD.MOV.U32 R2, RZ, RZ, 0x1 ;
ISETP.LE.AND P2, PT, R2, c[0x0][0x190], PT ;
@!P2 BRA 0xce0 ;
IMAD.MOV.U32 R2, RZ, RZ, 0x1 ;
IADD3 R12, R12, 0x1, RZ ;
IMAD.MOV.U32 R11, RZ, RZ, c[0x0][0x190] ;
IMAD.MOV.U32 R8, RZ, RZ, RZ ;
IADD3 R2, -R2, c[0x0][0x190], RZ ;
IMAD.MOV.U32 R13, RZ, RZ, RZ ;
LOP3.LUT R11, R11, 0x3, RZ, 0xc0, !PT ;
IMAD.MOV.U32 R10, RZ, RZ, RZ ;
ISETP.GE.U32.AND P5, PT, R2, 0x3, PT ;
IMAD R12, R4, R12, R7 ;
IADD3 R14, -R11, c[0x0][0x190], RZ ;
ISETP.NE.AND P6, PT, R11, RZ, PT ;
IMAD R15, R4, c[0x0][0x198], R13 ;
IMAD R16, R12, c[0x0][0x194], R13 ;
IMAD.MOV.U32 R18, RZ, RZ, RZ ;
@!P5 BRA 0x9a0 ;
IMAD.MOV.U32 R18, RZ, RZ, RZ ;
IMAD.MOV.U32 R17, RZ, RZ, R14 ;
IMAD R20, R7, c[0x0][0x198], R18 ;
IMAD.MOV.U32 R3, RZ, RZ, 0x4 ;
LOP3.LUT R2, R20, R15, RZ, 0xfc, !PT ;
ISETP.GE.AND P3, PT, R2, RZ, PT ;
IMAD R2, R16, c[0x0][0x190], R18 ;
ISETP.GE.OR P3, PT, R20, c[0x0][0x188], !P3 ;
IMAD.WIDE R2, R2, R3, c[0x0][0x170] ;
ISETP.GE.OR P3, PT, R15, c[0x0][0x18c], P3 ;
@!P3 LDG.E R21, [R2.64] ;
IADD3 R26, R20, 0x1, RZ ;
IMAD R19, R13, 0x10, R18 ;
LOP3.LUT R22, R26, R15, RZ, 0xfc, !PT ;
IMAD.SHL.U32 R19, R19, 0x4, RZ ;
ISETP.GE.AND P2, PT, R22, RZ, PT ;
@!P3 LDS R22, [R19+0x400] ;
ISETP.GE.OR P2, PT, R26, c[0x0][0x188], !P2 ;
@!P3 LDS R24, [R19] ;
ISETP.GE.OR P2, PT, R15, c[0x0][0x18c], P2 ;
IADD3 R26, R20, 0x2, RZ ;
@!P2 LDG.E R23, [R2.64+0x4] ;
LOP3.LUT R25, R26, R15.reuse, RZ, 0xfc, !PT ;
IADD3 R20, R20, 0x3, RZ ;
ISETP.GE.AND P4, PT, R25, RZ, PT ;
LOP3.LUT R25, R20, R15, RZ, 0xfc, !PT ;
ISETP.GE.OR P4, PT, R26, c[0x0][0x188], !P4 ;
ISETP.GE.OR P4, PT, R15, c[0x0][0x18c], P4 ;
@!P3 FFMA R10, R21.reuse, R22, R10 ;
@!P3 FFMA R8, R21, R24, R8 ;
ISETP.GE.AND P3, PT, R25, RZ, PT ;
@!P4 LDG.E R21, [R2.64+0x8] ;
ISETP.GE.OR P3, PT, R20, c[0x0][0x188], !P3 ;
@!P2 LDS R22, [R19+0x4] ;
ISETP.GE.OR P3, PT, R15, c[0x0][0x18c], P3 ;
@!P2 LDS R20, [R19+0x404] ;
@!P4 LDS R24, [R19+0x408] ;
@!P3 LDG.E R25, [R2.64+0xc] ;
@!P3 LDS R26, [R19+0x40c] ;
@!P3 LDS R27, [R19+0xc] ;
@!P2 FFMA R10, R23, R20, R10 ;
@!P4 LDS R20, [R19+0x8] ;
IADD3 R17, R17, -0x4, RZ ;
@!P2 FFMA R8, R23, R22, R8 ;
ISETP.NE.AND P2, PT, R17, RZ, PT ;
IADD3 R18, R18, 0x4, RZ ;
@!P4 FFMA R10, R21.reuse, R24, R10 ;
@!P4 FFMA R8, R21, R20, R8 ;
@!P3 FFMA R10, R25.reuse, R26, R10 ;
@!P3 FFMA R8, R25, R27, R8 ;
@P2 BRA 0x690 ;
@!P6 BRA 0xcb0 ;
IMAD R20, R7, c[0x0][0x198], R18.reuse ;
BSSY B1, 0xae0 ;
IMAD R3, R13, 0x10, R18 ;
ISETP.NE.AND P3, PT, R11, 0x1, PT ;
IMAD.MOV.U32 R17, RZ, RZ, 0x4 ;
LOP3.LUT R2, R20, R15, RZ, 0xfc, !PT ;
ISETP.GE.AND P2, PT, R2, RZ, PT ;
IMAD R2, R16, c[0x0][0x190], R18 ;
IMAD.SHL.U32 R16, R3, 0x4, RZ ;
ISETP.GE.OR P2, PT, R20, c[0x0][0x188], !P2 ;
IMAD.WIDE R2, R2, R17, c[0x0][0x170] ;
ISETP.GE.OR P2, PT, R15, c[0x0][0x18c], P2 ;
@P2 BRA 0xad0 ;
LDG.E R17, [R2.64] ;
LDS R18, [R16+0x400] ;
LDS R19, [R16] ;
FFMA R10, R17.reuse, R18, R10 ;
FFMA R8, R17, R19, R8 ;
BSYNC B1 ;
BSSY B1, 0xcb0 ;
@!P3 BRA 0xca0 ;
IADD3 R18, R20, 0x1, RZ ;
BSSY B2, 0xbe0 ;
ISETP.NE.AND P3, PT, R11, 0x2, PT ;
LOP3.LUT R17, R18, R15, RZ, 0xfc, !PT ;
ISETP.GE.AND P2, PT, R17, RZ, PT ;
ISETP.GE.OR P2, PT, R18, c[0x0][0x188], !P2 ;
ISETP.GE.OR P2, PT, R15, c[0x0][0x18c], P2 ;
@P2 BRA 0xbd0 ;
LDG.E R17, [R2.64+0x4] ;
LDS R18, [R16+0x404] ;
LDS R19, [R16+0x4] ;
FFMA R10, R17.reuse, R18, R10 ;
FFMA R8, R17, R19, R8 ;
BSYNC B2 ;
@!P3 BRA 0xca0 ;
IADD3 R20, R20, 0x2, RZ ;
LOP3.LUT R17, R20, R15, RZ, 0xfc, !PT ;
ISETP.GE.AND P2, PT, R17, RZ, PT ;
ISETP.GE.OR P2, PT, R20, c[0x0][0x188], !P2 ;
ISETP.GE.OR P2, PT, R15, c[0x0][0x18c], P2 ;
@P2 BRA 0xca0 ;
LDG.E R3, [R2.64+0x8] ;
LDS R15, [R16+0x408] ;
LDS R17, [R16+0x8] ;
FFMA R10, R3.reuse, R15, R10 ;
FFMA R8, R3, R17, R8 ;
BSYNC B1 ;
IADD3 R13, R13, 0x1, RZ ;
ISETP.GE.AND P2, PT, R13, c[0x0][0x194], PT ;
@!P2 BRA 0x620 ;
BSYNC B0 ;
BAR.SYNC 0x0 ;
BSSY B0, 0xd70 ;
@!P0 BRA 0xd60 ;
IMAD.MOV.U32 R3, RZ, RZ, 0x4 ;
IMAD R2, R0, c[0x0][0x188], R5 ;
IMAD.WIDE R2, R2, R3, c[0x0][0x178] ;
RED.E.ADD.F32.FTZ.RN.STRONG.GPU [R2.64], R10 ;
BSYNC B0 ;
@!P1 EXIT ;
IMAD.MOV.U32 R3, RZ, RZ, 0x4 ;
IMAD R2, R6, c[0x0][0x190], R9 ;
IMAD.WIDE R2, R2, R3, c[0x0][0x180] ;
RED.E.ADD.F32.FTZ.RN.STRONG.GPU [R2.64], R8 ;
EXIT ;
BRA 0xdd0;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
```
|
```amdasm
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z18convBackpropKernelPfS_S_S_S_iiiiii ; -- Begin function _Z18convBackpropKernelPfS_S_S_S_iiiiii
.globl _Z18convBackpropKernelPfS_S_S_S_iiiiii
.p2align 8
.type _Z18convBackpropKernelPfS_S_S_S_iiiiii,@function
_Z18convBackpropKernelPfS_S_S_S_iiiiii: ; @_Z18convBackpropKernelPfS_S_S_S_iiiiii
; %bb.0:
s_clause 0x1
s_load_b64 s[20:21], s[0:1], 0x38
s_load_b256 s[4:11], s[0:1], 0x0
v_dual_mov_b32 v8, 0 :: v_dual_and_b32 v1, 0x3ff, v0
s_clause 0x1
s_load_b64 s[12:13], s[0:1], 0x20
s_load_b128 s[16:19], s[0:1], 0x28
v_bfe_u32 v6, v0, 10, 10
v_mov_b32_e32 v5, 0
v_lshl_add_u32 v2, s14, 4, v1
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshl_add_u32 v3, s15, 4, v6
s_waitcnt lgkmcnt(0)
v_subrev_nc_u32_e32 v0, s21, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v4, s21, v3
v_cmp_lt_i32_e64 s0, -1, v0
s_delay_alu instid0(VALU_DEP_1)
s_and_saveexec_b32 s3, s0
s_cbranch_execz .LBB0_4
; %bb.1:
v_cmp_gt_i32_e32 vcc_lo, s16, v0
v_cmp_gt_i32_e64 s1, s17, v4
v_cmp_lt_i32_e64 s2, -1, v4
v_mov_b32_e32 v8, 0
s_delay_alu instid0(VALU_DEP_3)
s_and_b32 s1, vcc_lo, s1
s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
s_and_b32 s2, s1, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s1, s2
s_cbranch_execz .LBB0_3
; %bb.2:
v_mad_u64_u32 v[7:8], null, v4, s16, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v8, 31, v7
v_lshlrev_b64 v[7:8], 2, v[7:8]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v7, vcc_lo, s4, v7
v_add_co_ci_u32_e32 v8, vcc_lo, s5, v8, vcc_lo
global_load_b32 v8, v[7:8], off
.LBB0_3: ; %Flow246
s_or_b32 exec_lo, exec_lo, s1
.LBB0_4:
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
s_or_b32 exec_lo, exec_lo, s3
v_lshlrev_b32_e32 v7, 2, v1
v_cmp_gt_i32_e32 vcc_lo, s19, v6
v_cmp_gt_i32_e64 s1, s18, v1
v_lshl_add_u32 v7, v6, 6, v7
s_delay_alu instid0(VALU_DEP_2)
s_and_b32 s3, s1, vcc_lo
s_waitcnt vmcnt(0)
ds_store_b32 v7, v8
s_and_saveexec_b32 s1, s3
s_cbranch_execz .LBB0_6
; %bb.5:
v_mad_u64_u32 v[8:9], null, v6, s18, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v9, 31, v8
v_lshlrev_b64 v[8:9], 2, v[8:9]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v8, vcc_lo, s6, v8
v_add_co_ci_u32_e32 v9, vcc_lo, s7, v9, vcc_lo
global_load_b32 v5, v[8:9], off
.LBB0_6:
s_or_b32 exec_lo, exec_lo, s1
s_ashr_i32 s1, s20, 31
s_waitcnt vmcnt(0)
ds_store_b32 v7, v5 offset:1024
s_add_i32 s2, s20, s1
s_lshl_b32 s5, s21, 1
s_xor_b32 s4, s2, s1
s_sub_i32 s2, s16, s18
v_cvt_f32_u32_e32 v8, s4
s_add_i32 s2, s2, s5
s_sub_i32 s7, 0, s4
s_ashr_i32 s14, s2, 31
s_waitcnt lgkmcnt(0)
v_rcp_iflag_f32_e32 v8, v8
s_add_i32 s2, s2, s14
s_barrier
s_xor_b32 s2, s2, s14
s_xor_b32 s14, s14, s1
buffer_gl0_inv
v_dual_mov_b32 v7, 0 :: v_dual_mul_f32 v8, 0x4f7ffffe, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_u32_f32_e32 v8, v8
v_readfirstlane_b32 s6, v8
v_mov_b32_e32 v8, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s7, s7, s6
s_mul_hi_u32 s7, s6, s7
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s6, s6, s7
s_mul_hi_u32 s7, s2, s6
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s15, s7, s4
s_sub_i32 s2, s2, s15
s_add_i32 s15, s7, 1
s_sub_i32 s21, s2, s4
s_cmp_ge_u32 s2, s4
s_cselect_b32 s7, s15, s7
s_cselect_b32 s2, s21, s2
s_add_i32 s15, s7, 1
s_cmp_ge_u32 s2, s4
s_cselect_b32 s2, s15, s7
s_sub_i32 s7, s17, s19
s_xor_b32 s2, s2, s14
s_add_i32 s5, s7, s5
s_sub_i32 s2, s2, s14
s_ashr_i32 s7, s5, 31
v_cmp_ge_i32_e32 vcc_lo, s2, v2
s_add_i32 s5, s5, s7
s_xor_b32 s1, s7, s1
s_xor_b32 s5, s5, s7
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_hi_u32 s6, s5, s6
s_mul_i32 s14, s6, s4
s_add_i32 s7, s6, 1
s_sub_i32 s5, s5, s14
s_delay_alu instid0(SALU_CYCLE_1)
s_sub_i32 s14, s5, s4
s_cmp_ge_u32 s5, s4
s_cselect_b32 s6, s7, s6
s_cselect_b32 s5, s14, s5
s_add_i32 s7, s6, 1
s_cmp_ge_u32 s5, s4
s_mov_b32 s5, 0
s_cselect_b32 s4, s7, s6
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_xor_b32 s4, s4, s1
s_sub_i32 s1, s4, s1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_ge_i32_e64 s1, s1, v3
s_and_b32 s1, vcc_lo, s1
s_cmp_gt_i32 s19, 0
s_cselect_b32 s4, -1, 0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s1, s1, s4
s_and_saveexec_b32 s4, s1
s_cbranch_execz .LBB0_16
; %bb.7: ; %.preheader.lr.ph
v_mul_lo_u32 v5, v3, s2
s_mul_i32 s1, s19, s18
v_mul_lo_u32 v9, v3, s20
v_mov_b32_e32 v8, 0
s_cmp_gt_i32 s18, 0
s_mov_b32 s7, 0
s_cselect_b32 s6, -1, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add3_u32 v7, v5, v3, v2
v_mul_lo_u32 v5, v2, s20
v_mul_lo_u32 v10, s1, v7
v_mov_b32_e32 v7, 0
.LBB0_8: ; %.preheader
; =>This Loop Header: Depth=1
; Child Loop BB0_10 Depth 2
s_and_not1_b32 vcc_lo, exec_lo, s6
s_cbranch_vccnz .LBB0_15
; %bb.9: ; %.lr.ph
; in Loop: Header=BB0_8 Depth=1
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_dual_mov_b32 v11, v5 :: v_dual_add_nc_u32 v2, s7, v9
s_mov_b32 s14, s5
s_mov_b32 s15, s18
v_cmp_lt_i32_e32 vcc_lo, -1, v2
v_cmp_gt_i32_e64 s1, s17, v2
v_mov_b32_e32 v2, v10
.LBB0_10: ; Parent Loop BB0_8 Depth=1
; => This Inner Loop Header: Depth=2
s_mov_b32 s20, exec_lo
v_cmpx_lt_i32_e32 -1, v11
s_cbranch_execz .LBB0_14
; %bb.11: ; in Loop: Header=BB0_10 Depth=2
v_cmp_gt_i32_e64 s2, s16, v11
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, s2, vcc_lo
s_and_b32 s2, s2, s1
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s21, s2
s_cbranch_execz .LBB0_13
; %bb.12: ; in Loop: Header=BB0_10 Depth=2
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[12:13], 2, v[2:3]
v_add_co_u32 v12, s2, s8, v12
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v13, s2, s9, v13, s2
global_load_b32 v3, v[12:13], off
v_mov_b32_e32 v12, s14
ds_load_2addr_stride64_b32 v[12:13], v12 offset1:4
s_waitcnt vmcnt(0) lgkmcnt(0)
v_fmac_f32_e32 v8, v3, v13
v_fmac_f32_e32 v7, v3, v12
.LBB0_13: ; %Flow241
; in Loop: Header=BB0_10 Depth=2
s_or_b32 exec_lo, exec_lo, s21
.LBB0_14: ; in Loop: Header=BB0_10 Depth=2
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s20
v_add_nc_u32_e32 v2, 1, v2
v_add_nc_u32_e32 v11, 1, v11
s_add_i32 s15, s15, -1
s_add_i32 s14, s14, 4
s_cmp_eq_u32 s15, 0
s_cbranch_scc0 .LBB0_10
.LBB0_15: ; %._crit_edge
; in Loop: Header=BB0_8 Depth=1
s_delay_alu instid0(VALU_DEP_2)
v_add_nc_u32_e32 v10, s18, v10
s_add_i32 s7, s7, 1
s_add_i32 s5, s5, 64
s_cmp_eq_u32 s7, s19
s_cbranch_scc0 .LBB0_8
.LBB0_16: ; %Flow245
s_or_b32 exec_lo, exec_lo, s4
s_barrier
buffer_gl0_inv
s_and_saveexec_b32 s2, s0
s_cbranch_execz .LBB0_20
; %bb.17:
v_cmp_gt_i32_e32 vcc_lo, s16, v0
v_cmp_gt_i32_e64 s0, s17, v4
v_cmp_lt_i32_e64 s1, -1, v4
s_delay_alu instid0(VALU_DEP_2)
s_and_b32 s0, vcc_lo, s0
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
s_and_b32 s0, s0, s1
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 exec_lo, exec_lo, s0
s_cbranch_execz .LBB0_20
; %bb.18:
v_mad_u64_u32 v[2:3], null, v4, s16, v[0:1]
s_mov_b32 s0, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s10, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s11, v3, vcc_lo
global_load_b32 v5, v[2:3], off
.LBB0_19: ; %atomicrmw.start
; =>This Inner Loop Header: Depth=1
s_waitcnt vmcnt(0)
v_add_f32_e32 v4, v5, v8
global_atomic_cmpswap_b32 v0, v[2:3], v[4:5], off glc
s_waitcnt vmcnt(0)
v_cmp_eq_u32_e32 vcc_lo, v0, v5
v_mov_b32_e32 v5, v0
s_or_b32 s0, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s0
s_cbranch_execnz .LBB0_19
.LBB0_20:
s_or_b32 exec_lo, exec_lo, s2
s_and_saveexec_b32 s0, s3
s_cbranch_execz .LBB0_23
; %bb.21:
v_mad_u64_u32 v[2:3], null, v6, s18, v[1:2]
s_mov_b32 s0, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[0:1], 2, v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s12, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s13, v1, vcc_lo
global_load_b32 v3, v[0:1], off
.LBB0_22: ; %atomicrmw.start191
; =>This Inner Loop Header: Depth=1
s_waitcnt vmcnt(0)
v_add_f32_e32 v2, v3, v7
global_atomic_cmpswap_b32 v2, v[0:1], v[2:3], off glc
s_waitcnt vmcnt(0)
v_cmp_eq_u32_e32 vcc_lo, v2, v3
v_mov_b32_e32 v3, v2
s_or_b32 s0, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s0
s_cbranch_execnz .LBB0_22
.LBB0_23:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z18convBackpropKernelPfS_S_S_S_iiiiii
.amdhsa_group_segment_fixed_size 2048
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 64
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 14
.amdhsa_next_free_sgpr 22
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z18convBackpropKernelPfS_S_S_S_iiiiii, .Lfunc_end0-_Z18convBackpropKernelPfS_S_S_S_iiiiii
; -- End function
.section .AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1220
; NumSgprs: 24
; NumVgprs: 14
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 2048 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 24
; NumVGPRsForWavesPerEU: 14
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object ; @__hip_cuid_
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0 ; 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .offset: 40
.size: 4
.value_kind: by_value
- .offset: 44
.size: 4
.value_kind: by_value
- .offset: 48
.size: 4
.value_kind: by_value
- .offset: 52
.size: 4
.value_kind: by_value
- .offset: 56
.size: 4
.value_kind: by_value
- .offset: 60
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 2048
.kernarg_segment_align: 8
.kernarg_segment_size: 64
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z18convBackpropKernelPfS_S_S_S_iiiiii
.private_segment_fixed_size: 0
.sgpr_count: 24
.sgpr_spill_count: 0
.symbol: _Z18convBackpropKernelPfS_S_S_S_iiiiii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 14
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
```
| 4,647 | 6,791 |
113,699 |
Convert the following CUDA host assembly code to AMD host assembly:
```cudaasm
.file "tmpxft_000992f5_00000000-6_cuda_code_067576.cudafe1.cpp"
.text
.globl _ZSt21ios_base_library_initv
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB6836:
.cfi_startproc
endbr64
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
jmp __cudaUnregisterFatBinary@PLT
.cfi_endproc
.LFE6836:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "/home/ubuntu/Datasets/cuda-codes-80k-from-llm-dedup-compiled/cuda_code_067576.cu"
.LC1:
.string "%s in %s at line %d\n"
.text
.type _ZL11HandleError9cudaErrorPKci.constprop.0, @function
_ZL11HandleError9cudaErrorPKci.constprop.0:
.LFB7720:
.cfi_startproc
testl %edi, %edi
je .L2
subq $24, %rsp
.cfi_def_cfa_offset 32
movl %esi, 12(%rsp)
call cudaGetErrorString@PLT
movl 12(%rsp), %r8d
movl $2, %edi
leaq .LC0(%rip), %rcx
movq %rax, %rdx
leaq .LC1(%rip), %rsi
xorl %eax, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L2:
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE7720:
.size _ZL11HandleError9cudaErrorPKci.constprop.0, .-_ZL11HandleError9cudaErrorPKci.constprop.0
.globl _Z52__device_stub__Z18convBackpropKernelPfS_S_S_S_iiiiiiPfS_S_S_S_iiiiii
.type _Z52__device_stub__Z18convBackpropKernelPfS_S_S_S_iiiiiiPfS_S_S_S_iiiiii, @function
_Z52__device_stub__Z18convBackpropKernelPfS_S_S_S_iiiiiiPfS_S_S_S_iiiiii:
.LFB6858:
.cfi_startproc
endbr64
subq $216, %rsp
.cfi_def_cfa_offset 224
movq %rdi, 40(%rsp)
leaq 64(%rsp), %rdi
movq %rsi, 32(%rsp)
leaq 76(%rsp), %rsi
movq %rdx, 24(%rsp)
leaq 48(%rsp), %rdx
movq %rcx, 16(%rsp)
leaq 56(%rsp), %rcx
movq %r8, 8(%rsp)
movl %r9d, 4(%rsp)
movq %fs:40, %rax
movq %rax, 200(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movl $1, 72(%rsp)
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
leaq 4(%rsp), %rax
movq %rax, 152(%rsp)
leaq 224(%rsp), %rax
movq %rax, 160(%rsp)
leaq 232(%rsp), %rax
movq %rax, 168(%rsp)
leaq 240(%rsp), %rax
movq %rax, 176(%rsp)
leaq 248(%rsp), %rax
movq %rax, 184(%rsp)
leaq 256(%rsp), %rax
movq %rax, 192(%rsp)
movabsq $4294967297, %rax
movq %rax, 64(%rsp)
movq %rax, 76(%rsp)
movl $1, 84(%rsp)
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
jne .L8
pushq 56(%rsp)
.cfi_def_cfa_offset 232
leaq _Z18convBackpropKernelPfS_S_S_S_iiiiii(%rip), %rdi
pushq 56(%rsp)
.cfi_def_cfa_offset 240
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq 128(%rsp), %r9
call cudaLaunchKernel@PLT
popq %rax
.cfi_def_cfa_offset 232
popq %rdx
.cfi_def_cfa_offset 224
.L8:
movq 200(%rsp), %rax
subq %fs:40, %rax
je .L10
call __stack_chk_fail@PLT
.L10:
addq $216, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE6858:
.size _Z52__device_stub__Z18convBackpropKernelPfS_S_S_S_iiiiiiPfS_S_S_S_iiiiii, .-_Z52__device_stub__Z18convBackpropKernelPfS_S_S_S_iiiiiiPfS_S_S_S_iiiiii
.globl _Z18convBackpropKernelPfS_S_S_S_iiiiii
.type _Z18convBackpropKernelPfS_S_S_S_iiiiii, @function
_Z18convBackpropKernelPfS_S_S_S_iiiiii:
.LFB6859:
.cfi_startproc
endbr64
jmp _Z52__device_stub__Z18convBackpropKernelPfS_S_S_S_iiiiiiPfS_S_S_S_iiiiii
.cfi_endproc
.LFE6859:
.size _Z18convBackpropKernelPfS_S_S_S_iiiiii, .-_Z18convBackpropKernelPfS_S_S_S_iiiiii
.section .rodata.str1.1
.LC3:
.string "Backpropagation completed successfully."
.section .text.startup,"ax",@progbits
.globl main
.type main, @function
main:
.LFB6833:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
movl $4096, %esi
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $80, %rsp
.cfi_def_cfa_offset 128
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rdi
call cudaMalloc@PLT
movl $93, %esi
movl %eax, %edi
call _ZL11HandleError9cudaErrorPKci.constprop.0
leaq 16(%rsp), %rdi
movl $36, %esi
call cudaMalloc@PLT
movl $94, %esi
movl %eax, %edi
call _ZL11HandleError9cudaErrorPKci.constprop.0
leaq 24(%rsp), %rdi
movl $36864, %esi
call cudaMalloc@PLT
movl $95, %esi
movl %eax, %edi
call _ZL11HandleError9cudaErrorPKci.constprop.0
leaq 32(%rsp), %rdi
movl $4096, %esi
call cudaMalloc@PLT
movl $96, %esi
movl %eax, %edi
call _ZL11HandleError9cudaErrorPKci.constprop.0
leaq 40(%rsp), %rdi
movl $36, %esi
call cudaMalloc@PLT
movl $97, %esi
movl %eax, %edi
call _ZL11HandleError9cudaErrorPKci.constprop.0
movl $4096, %edi
call _Znam@PLT
movl $36, %edi
movq %rax, %r12
call _Znam@PLT
movl $36864, %edi
movq %rax, %rbp
call _Znam@PLT
movss .LC2(%rip), %xmm0
movq %rax, %rbx
xorl %eax, %eax
.L14:
movss %xmm0, (%r12,%rax,4)
incq %rax
cmpq $1024, %rax
jne .L14
xorl %eax, %eax
.L15:
movss %xmm0, 0(%rbp,%rax,4)
incq %rax
cmpq $9, %rax
jne .L15
xorl %eax, %eax
.L16:
movss %xmm0, (%rbx,%rax,4)
incq %rax
cmpq $9216, %rax
jne .L16
movq 8(%rsp), %rdi
movl $1, %ecx
movl $4096, %edx
movq %r12, %rsi
call cudaMemcpy@PLT
movl $106, %esi
movl %eax, %edi
call _ZL11HandleError9cudaErrorPKci.constprop.0
movq 16(%rsp), %rdi
movl $1, %ecx
movq %rbp, %rsi
movl $36, %edx
call cudaMemcpy@PLT
movl $107, %esi
movl %eax, %edi
call _ZL11HandleError9cudaErrorPKci.constprop.0
movq 24(%rsp), %rdi
movl $1, %ecx
movq %rbx, %rsi
movl $36864, %edx
call cudaMemcpy@PLT
movl $108, %esi
movl %eax, %edi
call _ZL11HandleError9cudaErrorPKci.constprop.0
xorl %r9d, %r9d
xorl %r8d, %r8d
movl $1, %ecx
movabsq $68719476752, %rdx
movl $1, %esi
movabsq $8589934594, %rdi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L17
pushq %rax
.cfi_def_cfa_offset 136
movl $32, %r9d
pushq $1
.cfi_def_cfa_offset 144
pushq $1
.cfi_def_cfa_offset 152
pushq $3
.cfi_def_cfa_offset 160
pushq $3
.cfi_def_cfa_offset 168
pushq $32
.cfi_def_cfa_offset 176
movq 88(%rsp), %r8
movq 80(%rsp), %rcx
movq 72(%rsp), %rdx
movq 64(%rsp), %rsi
movq 56(%rsp), %rdi
call _Z52__device_stub__Z18convBackpropKernelPfS_S_S_S_iiiiiiPfS_S_S_S_iiiiii
addq $48, %rsp
.cfi_def_cfa_offset 128
.L17:
call cudaGetLastError@PLT
movl $117, %esi
movl %eax, %edi
call _ZL11HandleError9cudaErrorPKci.constprop.0
call cudaDeviceSynchronize@PLT
movl $118, %esi
movl %eax, %edi
call _ZL11HandleError9cudaErrorPKci.constprop.0
movl $4096, %edi
call _Znam@PLT
movl $36, %edi
movq %rax, %r14
call _Znam@PLT
movq 32(%rsp), %rsi
movl $2, %ecx
movq %r14, %rdi
movl $4096, %edx
movq %rax, %r13
call cudaMemcpy@PLT
movl $123, %esi
movl %eax, %edi
call _ZL11HandleError9cudaErrorPKci.constprop.0
movq 40(%rsp), %rsi
movl $2, %ecx
movq %r13, %rdi
movl $36, %edx
call cudaMemcpy@PLT
movl $124, %esi
movl %eax, %edi
call _ZL11HandleError9cudaErrorPKci.constprop.0
movq 8(%rsp), %rdi
call cudaFree@PLT
movl $127, %esi
movl %eax, %edi
call _ZL11HandleError9cudaErrorPKci.constprop.0
movq 16(%rsp), %rdi
call cudaFree@PLT
movl $128, %esi
movl %eax, %edi
call _ZL11HandleError9cudaErrorPKci.constprop.0
movq 24(%rsp), %rdi
call cudaFree@PLT
movl $129, %esi
movl %eax, %edi
call _ZL11HandleError9cudaErrorPKci.constprop.0
movq 32(%rsp), %rdi
call cudaFree@PLT
movl $130, %esi
movl %eax, %edi
call _ZL11HandleError9cudaErrorPKci.constprop.0
movq 40(%rsp), %rdi
call cudaFree@PLT
movl $131, %esi
movl %eax, %edi
call _ZL11HandleError9cudaErrorPKci.constprop.0
movq %r12, %rdi
call _ZdaPv@PLT
movq %rbp, %rdi
call _ZdaPv@PLT
movq %rbx, %rdi
call _ZdaPv@PLT
movq %r14, %rdi
call _ZdaPv@PLT
movq %r13, %rdi
call _ZdaPv@PLT
leaq _ZSt4cout(%rip), %rdi
leaq .LC3(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq 72(%rsp), %rax
subq %fs:40, %rax
je .L18
call __stack_chk_fail@PLT
.L18:
addq $80, %rsp
.cfi_def_cfa_offset 48
xorl %eax, %eax
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE6833:
.size main, .-main
.section .rodata.str1.1
.LC4:
.string "_Z18convBackpropKernelPfS_S_S_S_iiiiii"
.LC5:
.string "_ZN50_INTERNAL_2855fadf_19_cuda_code_067576_cu_30f8ee924cuda3std3__419piecewise_constructE"
.LC6:
.string "_ZN50_INTERNAL_2855fadf_19_cuda_code_067576_cu_30f8ee924cuda3std6ranges3__45__cpo4swapE"
.LC7:
.string "_ZN50_INTERNAL_2855fadf_19_cuda_code_067576_cu_30f8ee924cuda3std6ranges3__45__cpo9iter_moveE"
.section .text.startup
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB6861:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
pushq $0
.cfi_def_cfa_offset 24
xorl %r9d, %r9d
orl $-1, %r8d
pushq $0
.cfi_def_cfa_offset 32
leaq .LC4(%rip), %rdx
movq %rax, %rdi
movq %rax, %rbx
pushq $0
.cfi_def_cfa_offset 40
movq %rdx, %rcx
leaq _Z18convBackpropKernelPfS_S_S_S_iiiiii(%rip), %rsi
pushq $0
.cfi_def_cfa_offset 48
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq %rbx, %rdi
xorl %r8d, %r8d
pushq $0
.cfi_def_cfa_offset 24
leaq .LC5(%rip), %rdx
movl $1, %r9d
leaq _ZN4cuda3std3__419piecewise_constructE(%rip), %rsi
pushq $0
.cfi_def_cfa_offset 32
movq %rdx, %rcx
call __cudaRegisterVar@PLT
popq %rax
.cfi_def_cfa_offset 24
popq %rdx
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
leaq .LC6(%rip), %rdx
movq %rbx, %rdi
xorl %r8d, %r8d
movq %rdx, %rcx
movl $1, %r9d
leaq _ZN4cuda3std6ranges3__45__cpo4swapE(%rip), %rsi
call __cudaRegisterVar@PLT
popq %rcx
.cfi_def_cfa_offset 24
popq %rsi
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
leaq .LC7(%rip), %rdx
movq %rbx, %rdi
xorl %r8d, %r8d
movl $1, %r9d
movq %rdx, %rcx
leaq _ZN4cuda3std6ranges3__45__cpo9iter_moveE(%rip), %rsi
call __cudaRegisterVar@PLT
popq %rdi
.cfi_def_cfa_offset 24
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
popq %r8
.cfi_def_cfa_offset 16
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit@PLT
.cfi_endproc
.LFE6861:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.weak _ZN4cuda3std3__419piecewise_constructE
.section .rodata._ZN4cuda3std3__419piecewise_constructE,"aG",@progbits,_ZN4cuda3std3__419piecewise_constructE,comdat
.type _ZN4cuda3std3__419piecewise_constructE, @gnu_unique_object
.size _ZN4cuda3std3__419piecewise_constructE, 1
_ZN4cuda3std3__419piecewise_constructE:
.zero 1
.weak _ZN4cuda3std6ranges3__45__cpo9iter_moveE
.section .rodata._ZN4cuda3std6ranges3__45__cpo9iter_moveE,"aG",@progbits,_ZN4cuda3std6ranges3__45__cpo9iter_moveE,comdat
.type _ZN4cuda3std6ranges3__45__cpo9iter_moveE, @gnu_unique_object
.size _ZN4cuda3std6ranges3__45__cpo9iter_moveE, 1
_ZN4cuda3std6ranges3__45__cpo9iter_moveE:
.zero 1
.weak _ZN4cuda3std6ranges3__45__cpo4swapE
.section .rodata._ZN4cuda3std6ranges3__45__cpo4swapE,"aG",@progbits,_ZN4cuda3std6ranges3__45__cpo4swapE,comdat
.type _ZN4cuda3std6ranges3__45__cpo4swapE, @gnu_unique_object
.size _ZN4cuda3std6ranges3__45__cpo4swapE, 1
_ZN4cuda3std6ranges3__45__cpo4swapE:
.zero 1
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC2:
.long 1065353216
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
```
|
```amdasm
.text
.file "cuda_code_067576.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z33__device_stub__convBackpropKernelPfS_S_S_S_iiiiii # -- Begin function _Z33__device_stub__convBackpropKernelPfS_S_S_S_iiiiii
.type _Z33__device_stub__convBackpropKernelPfS_S_S_S_iiiiii,@function
_Z33__device_stub__convBackpropKernelPfS_S_S_S_iiiiii: # @_Z33__device_stub__convBackpropKernelPfS_S_S_S_iiiiii
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $192, %rsp
.cfi_def_cfa_offset 240
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 56(%rsp), %rax
movq %rdi, (%rax)
leaq 48(%rsp), %rdi
movq %rsi, (%rdi)
leaq 40(%rsp), %rsi
movq %rdx, (%rsi)
leaq 32(%rsp), %rdx
movq %rcx, (%rdx)
leaq 24(%rsp), %rcx
movq %r8, (%rcx)
leaq 4(%rsp), %r8
movl %r9d, (%r8)
leaq 96(%rsp), %rbx
movq %rax, (%rbx)
movq %rdi, 8(%rbx)
movq %rsi, 16(%rbx)
movq %rdx, 24(%rbx)
movq %rcx, 32(%rbx)
movq %r8, 40(%rbx)
leaq 240(%rsp), %rax
movq %rax, 48(%rbx)
leaq 248(%rsp), %rax
movq %rax, 56(%rbx)
leaq 256(%rsp), %rax
movq %rax, 64(%rbx)
leaq 264(%rsp), %rax
movq %rax, 72(%rbx)
leaq 272(%rsp), %rax
movq %rax, 80(%rbx)
leaq 80(%rsp), %r14
leaq 64(%rsp), %r15
leaq 16(%rsp), %r12
leaq 8(%rsp), %r13
movq %r14, %rdi
movq %r15, %rsi
movq %r12, %rdx
movq %r13, %rcx
callq __hipPopCallConfiguration
movq (%r14), %rsi
movl 8(%r14), %edx
movq (%r15), %rcx
movl 8(%r15), %r8d
movl $_Z18convBackpropKernelPfS_S_S_S_iiiiii, %edi
movq %rbx, %r9
pushq (%r13)
.cfi_adjust_cfa_offset 8
pushq (%r12)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $208, %rsp
.cfi_adjust_cfa_offset -208
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z33__device_stub__convBackpropKernelPfS_S_S_S_iiiiii, .Lfunc_end0-_Z33__device_stub__convBackpropKernelPfS_S_S_S_iiiiii
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $48, %rsp
.cfi_def_cfa_offset 96
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 40(%rsp), %rdi
movl $4096, %esi # imm = 0x1000
callq hipMalloc
movl %eax, %edi
movl $93, %esi
callq _ZL11HandleError10hipError_tPKci
leaq 32(%rsp), %rdi
movl $36, %esi
callq hipMalloc
movl %eax, %edi
movl $94, %esi
callq _ZL11HandleError10hipError_tPKci
leaq 24(%rsp), %rdi
movl $36864, %esi # imm = 0x9000
callq hipMalloc
movl %eax, %edi
movl $95, %esi
callq _ZL11HandleError10hipError_tPKci
leaq 16(%rsp), %rdi
movl $4096, %esi # imm = 0x1000
callq hipMalloc
movl %eax, %edi
movl $96, %esi
callq _ZL11HandleError10hipError_tPKci
leaq 8(%rsp), %rdi
movl $36, %esi
callq hipMalloc
movl %eax, %edi
movl $97, %esi
callq _ZL11HandleError10hipError_tPKci
movl $4096, %edi # imm = 0x1000
callq _Znam
movq %rax, %rbx
movl $36, %edi
callq _Znam
movq %rax, %r14
movl $36864, %edi # imm = 0x9000
callq _Znam
movq %rax, %r15
xorl %eax, %eax
.LBB1_1: # =>This Inner Loop Header: Depth=1
movl $1065353216, (%rbx,%rax,4) # imm = 0x3F800000
incq %rax
cmpq $1024, %rax # imm = 0x400
jne .LBB1_1
# %bb.2: # %.preheader82.preheader
xorl %eax, %eax
.LBB1_3: # %.preheader82
# =>This Inner Loop Header: Depth=1
movl $1065353216, (%r14,%rax,4) # imm = 0x3F800000
incq %rax
cmpq $9, %rax
jne .LBB1_3
# %bb.4: # %.preheader.preheader
xorl %eax, %eax
.LBB1_5: # %.preheader
# =>This Inner Loop Header: Depth=1
movl $1065353216, (%r15,%rax,4) # imm = 0x3F800000
incq %rax
cmpq $9216, %rax # imm = 0x2400
jne .LBB1_5
# %bb.6:
movq 40(%rsp), %rdi
movl $1, %r12d
movl $4096, %edx # imm = 0x1000
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movl %eax, %edi
movl $106, %esi
callq _ZL11HandleError10hipError_tPKci
movq 32(%rsp), %rdi
movl $36, %edx
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movl %eax, %edi
movl $107, %esi
callq _ZL11HandleError10hipError_tPKci
movq 24(%rsp), %rdi
movl $36864, %edx # imm = 0x9000
movq %r15, %rsi
movl $1, %ecx
callq hipMemcpy
movl %eax, %edi
movl $108, %esi
callq _ZL11HandleError10hipError_tPKci
movabsq $8589934594, %rdi # imm = 0x200000002
movabsq $68719476752, %rdx # imm = 0x1000000010
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_8
# %bb.7:
movq 40(%rsp), %rdi
movq 32(%rsp), %rsi
movq 24(%rsp), %rdx
movq 16(%rsp), %rcx
movq 8(%rsp), %r8
subq $8, %rsp
.cfi_adjust_cfa_offset 8
movl $3, %eax
movl $32, %r9d
pushq %r12
.cfi_adjust_cfa_offset 8
pushq %r12
.cfi_adjust_cfa_offset 8
pushq %rax
.cfi_adjust_cfa_offset 8
pushq %rax
.cfi_adjust_cfa_offset 8
pushq $32
.cfi_adjust_cfa_offset 8
callq _Z33__device_stub__convBackpropKernelPfS_S_S_S_iiiiii
addq $48, %rsp
.cfi_adjust_cfa_offset -48
.LBB1_8:
callq hipGetLastError
movl %eax, %edi
movl $117, %esi
callq _ZL11HandleError10hipError_tPKci
callq hipDeviceSynchronize
movl %eax, %edi
movl $118, %esi
callq _ZL11HandleError10hipError_tPKci
movl $4096, %edi # imm = 0x1000
callq _Znam
movq %rax, %r12
movl $36, %edi
callq _Znam
movq %rax, %r13
movq 16(%rsp), %rsi
movl $4096, %edx # imm = 0x1000
movq %r12, %rdi
movl $2, %ecx
callq hipMemcpy
movl %eax, %edi
movl $123, %esi
callq _ZL11HandleError10hipError_tPKci
movq 8(%rsp), %rsi
movl $36, %edx
movq %r13, %rdi
movl $2, %ecx
callq hipMemcpy
movl %eax, %edi
movl $124, %esi
callq _ZL11HandleError10hipError_tPKci
movq 40(%rsp), %rdi
callq hipFree
movl %eax, %edi
movl $127, %esi
callq _ZL11HandleError10hipError_tPKci
movq 32(%rsp), %rdi
callq hipFree
movl %eax, %edi
movl $128, %esi
callq _ZL11HandleError10hipError_tPKci
movq 24(%rsp), %rdi
callq hipFree
movl %eax, %edi
movl $129, %esi
callq _ZL11HandleError10hipError_tPKci
movq 16(%rsp), %rdi
callq hipFree
movl %eax, %edi
movl $130, %esi
callq _ZL11HandleError10hipError_tPKci
movq 8(%rsp), %rdi
callq hipFree
movl %eax, %edi
movl $131, %esi
callq _ZL11HandleError10hipError_tPKci
movq %rbx, %rdi
callq _ZdaPv
movq %r14, %rdi
callq _ZdaPv
movq %r15, %rdi
callq _ZdaPv
movq %r12, %rdi
callq _ZdaPv
movq %r13, %rdi
callq _ZdaPv
movl $_ZSt4cout, %ebx
movl $_ZSt4cout, %edi
movl $.L.str.1, %esi
movl $39, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rdi
addq %rbx, %rdi
movl $10, %esi
callq _ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
xorl %eax, %eax
addq $48, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.type _ZL11HandleError10hipError_tPKci,@function # -- Begin function _ZL11HandleError10hipError_tPKci
_ZL11HandleError10hipError_tPKci: # @_ZL11HandleError10hipError_tPKci
.cfi_startproc
# %bb.0:
testl %edi, %edi
jne .LBB2_2
# %bb.1:
retq
.LBB2_2:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
movl %esi, %ebx
callq hipGetErrorString
movl $.L.str.2, %edi
movl $.L.str, %edx
movq %rax, %rsi
movl %ebx, %ecx
xorl %eax, %eax
callq printf
movl $1, %edi
callq exit
.Lfunc_end2:
.size _ZL11HandleError10hipError_tPKci, .Lfunc_end2-_ZL11HandleError10hipError_tPKci
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, %rdi
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z18convBackpropKernelPfS_S_S_S_iiiiii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z18convBackpropKernelPfS_S_S_S_iiiiii,@object # @_Z18convBackpropKernelPfS_S_S_S_iiiiii
.section .rodata,"a",@progbits
.globl _Z18convBackpropKernelPfS_S_S_S_iiiiii
.p2align 3, 0x0
_Z18convBackpropKernelPfS_S_S_S_iiiiii:
.quad _Z33__device_stub__convBackpropKernelPfS_S_S_S_iiiiii
.size _Z18convBackpropKernelPfS_S_S_S_iiiiii, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "/home/ubuntu/Datasets/hip-codes-80k-from-llm-dedup-disassemble/cuda_code_067576.hip"
.size .L.str, 84
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Backpropagation completed successfully."
.size .L.str.1, 40
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "%s in %s at line %d\n"
.size .L.str.2, 21
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z18convBackpropKernelPfS_S_S_S_iiiiii"
.size .L__unnamed_1, 39
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z33__device_stub__convBackpropKernelPfS_S_S_S_iiiiii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z18convBackpropKernelPfS_S_S_S_iiiiii
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
```
| 6,228 | 5,709 |
113,700 |
Convert the following CUDA device assembly code to AMD device assembly:
```cudaasm
code for sm_80
Function : _Z11bTreeKernelP9BTreeNodei
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ;
S2R R4, SR_CTAID.X ;
S2R R3, SR_TID.X ;
IMAD R4, R4, c[0x0][0x0], R3 ;
ISETP.GE.AND P0, PT, R4, c[0x0][0x168], PT ;
@P0 EXIT ;
IMAD.MOV.U32 R5, RZ, RZ, 0x30 ;
ULDC.64 UR4, c[0x0][0x118] ;
IMAD.WIDE R2, R4, R5, c[0x0][0x160] ;
LDG.E R9, [R2.64+0x14] ;
BSSY B0, 0x220 ;
SHF.R.S32.HI R0, RZ, 0x1f, R4 ;
ISETP.GE.AND P0, PT, R9, 0x1, PT ;
@!P0 BRA 0x210 ;
IMAD R13, R0, 0x30, RZ ;
BSSY B1, 0x200 ;
IMAD.WIDE.U32 R6, R4, R5, c[0x0][0x160] ;
IMAD.MOV.U32 R8, RZ, RZ, RZ ;
IMAD.IADD R13, R7, 0x1, R13 ;
IMAD.MOV.U32 R10, RZ, RZ, R6 ;
IMAD.MOV.U32 R6, RZ, RZ, R10 ;
IMAD.MOV.U32 R7, RZ, RZ, R13 ;
LDG.E R9, [R6.64] ;
IADD3 R9, R9, 0x1, RZ ;
STG.E [R6.64], R9 ;
LDG.E R11, [R2.64+0x14] ;
IADD3 R8, R8, 0x1, RZ ;
IADD3 R10, P1, R6, 0x4, RZ ;
IMAD.X R13, RZ, RZ, R7, P1 ;
ISETP.GE.AND P0, PT, R8, R11, PT ;
@!P0 BRA 0x140 ;
BSYNC B1 ;
IMAD.MOV.U32 R9, RZ, RZ, R11 ;
BSYNC B0 ;
ISETP.GE.AND P0, PT, R9, RZ, PT ;
@!P0 EXIT ;
ISETP.GE.U32.AND P0, PT, R9.reuse, 0x3, PT ;
BSSY B1, 0xaf0 ;
IADD3 R6, R9, 0x1, RZ ;
IMAD.MOV.U32 R7, RZ, RZ, RZ ;
LOP3.LUT R6, R6, 0x3, RZ, 0xc0, !PT ;
@!P0 BRA 0xae0 ;
IMAD.IADD R8, R9, 0x1, -R6 ;
BSSY B0, 0x9a0 ;
IMAD.WIDE.U32 R2, R4, R5, c[0x0][0x160] ;
ISETP.GT.AND P0, PT, R8, -0x1, PT ;
IMAD R7, R0, 0x30, RZ ;
IADD3 R2, P1, R2, 0x24, RZ ;
IMAD.X R3, R3, 0x1, R7, P1 ;
IMAD.MOV.U32 R7, RZ, RZ, RZ ;
@!P0 BRA 0x990 ;
IADD3 R9, R8, 0x1, RZ ;
BSSY B2, 0x720 ;
PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ;
ISETP.GT.AND P1, PT, R9, 0xc, PT ;
@!P1 BRA 0x710 ;
PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ;
LDG.E R22, [R2.64+-0x4] ;
LDG.E R19, [R2.64+-0xc] ;
LDG.E R20, [R2.64+-0x8] ;
LDG.E R15, [R2.64+0x1c] ;
LDG.E R10, [R2.64+0x30] ;
LDG.E R24, [R2.64] ;
LDG.E R26, [R2.64+0x4] ;
LDG.E R28, [R2.64+0x8] ;
LDG.E R18, [R2.64+0xc] ;
LDG.E R14, [R2.64+0x10] ;
LDG.E R17, [R2.64+0x14] ;
LDG.E R16, [R2.64+0x18] ;
LDG.E R13, [R2.64+0x20] ;
LDG.E R9, [R2.64+0x24] ;
LDG.E R12, [R2.64+0x28] ;
LDG.E R11, [R2.64+0x2c] ;
IADD3 R8, R8, -0x10, RZ ;
ISETP.GT.AND P1, PT, R8, 0xb, PT ;
IADD3 R7, R7, 0x10, RZ ;
IADD3 R23, R22, 0x1, RZ ;
IADD3 R19, R19, 0x1, RZ ;
STG.E [R2.64+-0x4], R23 ;
IADD3 R21, R20, 0x1, RZ ;
STG.E [R2.64+-0xc], R19 ;
IADD3 R15, R15, 0x1, RZ ;
STG.E [R2.64+-0x8], R21 ;
IADD3 R23, R10, 0x1, RZ ;
IADD3 R10, P2, R2, 0x40, RZ ;
STG.E [R2.64+0x1c], R15 ;
IADD3 R25, R24, 0x1, RZ ;
IADD3 R27, R26, 0x1, RZ ;
IADD3 R29, R28, 0x1, RZ ;
IADD3 R19, R18, 0x1, RZ ;
IMAD.X R15, RZ, RZ, R3, P2 ;
IADD3 R14, R14, 0x1, RZ ;
IADD3 R17, R17, 0x1, RZ ;
IADD3 R16, R16, 0x1, RZ ;
IADD3 R13, R13, 0x1, RZ ;
IADD3 R9, R9, 0x1, RZ ;
IADD3 R21, R12, 0x1, RZ ;
IADD3 R11, R11, 0x1, RZ ;
STG.E [R2.64], R25 ;
STG.E [R2.64+0x4], R27 ;
STG.E [R2.64+0x8], R29 ;
STG.E [R2.64+0xc], R19 ;
STG.E [R2.64+0x10], R14 ;
STG.E [R2.64+0x14], R17 ;
STG.E [R2.64+0x18], R16 ;
STG.E [R2.64+0x20], R13 ;
STG.E [R2.64+0x24], R9 ;
STG.E [R2.64+0x28], R21 ;
STG.E [R2.64+0x2c], R11 ;
STG.E [R2.64+0x30], R23 ;
IMAD.MOV.U32 R2, RZ, RZ, R10 ;
IMAD.MOV.U32 R3, RZ, RZ, R15 ;
@P1 BRA 0x390 ;
BSYNC B2 ;
IADD3 R9, R8, 0x1, RZ ;
BSSY B2, 0x960 ;
ISETP.GT.AND P1, PT, R9, 0x4, PT ;
@!P1 BRA 0x950 ;
LDG.E R9, [R2.64+-0xc] ;
LDG.E R10, [R2.64+-0x8] ;
LDG.E R12, [R2.64+-0x4] ;
LDG.E R14, [R2.64] ;
LDG.E R16, [R2.64+0x4] ;
LDG.E R18, [R2.64+0x8] ;
LDG.E R20, [R2.64+0xc] ;
LDG.E R22, [R2.64+0x10] ;
PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ;
IADD3 R7, R7, 0x8, RZ ;
IADD3 R8, R8, -0x8, RZ ;
IADD3 R9, R9, 0x1, RZ ;
IADD3 R11, R10, 0x1, RZ ;
STG.E [R2.64+-0xc], R9 ;
IADD3 R13, R12, 0x1, RZ ;
STG.E [R2.64+-0x8], R11 ;
IADD3 R15, R14, 0x1, RZ ;
STG.E [R2.64+-0x4], R13 ;
IADD3 R17, R16, 0x1, RZ ;
STG.E [R2.64], R15 ;
IADD3 R9, P1, R2, 0x20, RZ ;
IADD3 R19, R18, 0x1, RZ ;
STG.E [R2.64+0x4], R17 ;
IMAD.X R10, RZ, RZ, R3, P1 ;
IADD3 R21, R20, 0x1, RZ ;
STG.E [R2.64+0x8], R19 ;
IADD3 R23, R22, 0x1, RZ ;
STG.E [R2.64+0xc], R21 ;
STG.E [R2.64+0x10], R23 ;
IMAD.MOV.U32 R2, RZ, RZ, R9 ;
IMAD.MOV.U32 R3, RZ, RZ, R10 ;
BSYNC B2 ;
ISETP.NE.OR P0, PT, R8, -0x1, P0 ;
@!P0 BREAK B0 ;
@!P0 BRA 0xae0 ;
BSYNC B0 ;
LDG.E R10, [R2.64+-0x8] ;
LDG.E R9, [R2.64+-0xc] ;
LDG.E R12, [R2.64+-0x4] ;
LDG.E R14, [R2.64] ;
IADD3 R8, R8, -0x4, RZ ;
ISETP.NE.AND P0, PT, R8, -0x1, PT ;
IADD3 R7, R7, 0x4, RZ ;
IADD3 R11, R10, 0x1, RZ ;
IADD3 R10, P1, R2, 0x10, RZ ;
IADD3 R9, R9, 0x1, RZ ;
IADD3 R13, R12, 0x1, RZ ;
IMAD.X R17, RZ, RZ, R3, P1 ;
IADD3 R15, R14, 0x1, RZ ;
STG.E [R2.64+-0xc], R9 ;
STG.E [R2.64+-0x8], R11 ;
STG.E [R2.64+-0x4], R13 ;
STG.E [R2.64], R15 ;
IMAD.MOV.U32 R2, RZ, RZ, R10 ;
IMAD.MOV.U32 R3, RZ, RZ, R17 ;
@P0 BRA 0x9a0 ;
BSYNC B1 ;
WARPSYNC 0xffffffff ;
ISETP.NE.AND P0, PT, R6, RZ, PT ;
@!P0 EXIT ;
IMAD.WIDE.U32 R2, R4, R5, c[0x0][0x160] ;
IMAD R5, R0, 0x30, RZ ;
IMAD.IADD R3, R3, 0x1, R5 ;
IMAD.WIDE R2, R7, 0x4, R2 ;
IADD3 R0, P0, R2, 0x18, RZ ;
IMAD.X R7, RZ, RZ, R3, P0 ;
IMAD.MOV.U32 R2, RZ, RZ, R0 ;
IMAD.MOV.U32 R3, RZ, RZ, R7 ;
LDG.E R0, [R2.64] ;
IADD3 R6, R6, -0x1, RZ ;
ISETP.NE.AND P0, PT, R6, RZ, PT ;
IADD3 R5, R0, 0x1, RZ ;
IADD3 R0, P1, R2, 0x4, RZ ;
STG.E [R2.64], R5 ;
IMAD.X R7, RZ, RZ, R3, P1 ;
@P0 BRA 0xb80 ;
EXIT ;
BRA 0xc30;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
```
|
```amdasm
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z11bTreeKernelP9BTreeNodei ; -- Begin function _Z11bTreeKernelP9BTreeNodei
.globl _Z11bTreeKernelP9BTreeNodei
.p2align 8
.type _Z11bTreeKernelP9BTreeNodei,@function
_Z11bTreeKernelP9BTreeNodei: ; @_Z11bTreeKernelP9BTreeNodei
; %bb.0:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x1c
s_load_b32 s3, s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_8
; %bb.1: ; %.preheader19
s_load_b64 s[2:3], s[0:1], 0x0
s_mov_b32 s4, 0
s_mov_b32 s1, exec_lo
s_waitcnt lgkmcnt(0)
v_mad_i64_i32 v[4:5], null, v1, 48, s[2:3]
global_load_b32 v6, v[4:5], off offset:20
s_waitcnt vmcnt(0)
v_cmpx_lt_i32_e32 0, v6
s_cbranch_execz .LBB0_5
; %bb.2: ; %.lr.ph
v_mad_i64_i32 v[2:3], null, v1, 48, s[2:3]
v_add_co_u32 v4, vcc_lo, v4, 20
v_add_co_ci_u32_e32 v5, vcc_lo, 0, v5, vcc_lo
s_mov_b32 s5, 0
.LBB0_3: ; =>This Inner Loop Header: Depth=1
global_load_b32 v0, v[2:3], off
s_add_i32 s5, s5, 1
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v0, 1, v0
global_store_b32 v[2:3], v0, off
global_load_b32 v6, v[4:5], off
v_add_co_u32 v2, s0, v2, 4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
v_add_co_ci_u32_e64 v3, s0, 0, v3, s0
s_waitcnt vmcnt(0)
v_cmp_ge_i32_e32 vcc_lo, s5, v6
s_or_b32 s4, vcc_lo, s4
s_and_not1_b32 exec_lo, exec_lo, s4
s_cbranch_execnz .LBB0_3
; %bb.4: ; %Flow34
s_or_b32 exec_lo, exec_lo, s4
.LBB0_5: ; %Flow35
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s1
v_cmp_lt_i32_e32 vcc_lo, -1, v6
s_mov_b32 s1, -1
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_8
; %bb.6: ; %.lr.ph25.preheader
v_mad_i64_i32 v[2:3], null, v1, 48, s[2:3]
s_mov_b32 s2, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v2, 24
v_add_co_ci_u32_e32 v1, vcc_lo, 0, v3, vcc_lo
.LBB0_7: ; %.lr.ph25
; =>This Inner Loop Header: Depth=1
global_load_b32 v2, v[0:1], off
s_add_i32 s1, s1, 1
s_delay_alu instid0(SALU_CYCLE_1)
v_cmp_ge_i32_e32 vcc_lo, s1, v6
s_or_b32 s2, vcc_lo, s2
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v2, 1, v2
global_store_b32 v[0:1], v2, off
v_add_co_u32 v0, s0, v0, 4
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v1, s0, 0, v1, s0
s_and_not1_b32 exec_lo, exec_lo, s2
s_cbranch_execnz .LBB0_7
.LBB0_8: ; %.loopexit
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11bTreeKernelP9BTreeNodei
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z11bTreeKernelP9BTreeNodei, .Lfunc_end0-_Z11bTreeKernelP9BTreeNodei
; -- End function
.section .AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 344
; NumSgprs: 18
; NumVgprs: 7
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 7
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object ; @__hip_cuid_
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0 ; 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11bTreeKernelP9BTreeNodei
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z11bTreeKernelP9BTreeNodei.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
```
| 3,552 | 3,170 |
113,701 |
Convert the following CUDA host assembly code to AMD host assembly:
```cudaasm
.file "tmpxft_0008e210_00000000-6_cuda_code_082743.cudafe1.cpp"
.text
.globl _ZSt21ios_base_library_initv
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3639:
.cfi_startproc
endbr64
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
jmp __cudaUnregisterFatBinary@PLT
.cfi_endproc
.LFE3639:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "CUDA Error: "
.LC1:
.string " ("
.LC2:
.string ")"
.text
.globl _Z14checkCudaError9cudaErrorPKc
.type _Z14checkCudaError9cudaErrorPKc, @function
_Z14checkCudaError9cudaErrorPKc:
.LFB3635:
.cfi_startproc
endbr64
testl %edi, %edi
je .L2
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
movq %rsi, %rbp
leaq .LC0(%rip), %rsi
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
movl %edi, %ebx
leaq _ZSt4cerr(%rip), %rdi
pushq %rax
.cfi_def_cfa_offset 32
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rbp, %rsi
movq %rax, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
leaq .LC1(%rip), %rsi
movq %rax, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movl %ebx, %edi
movq %rax, %rbp
call cudaGetErrorString@PLT
movq %rbp, %rdi
movq %rax, %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
leaq .LC2(%rip), %rsi
movq %rax, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $1, %edi
call exit@PLT
.L2:
.cfi_def_cfa_offset 8
.cfi_restore 3
.cfi_restore 6
ret
.cfi_endproc
.LFE3635:
.size _Z14checkCudaError9cudaErrorPKc, .-_Z14checkCudaError9cudaErrorPKc
.globl _Z41__device_stub__Z11bTreeKernelP9BTreeNodeiP9BTreeNodei
.type _Z41__device_stub__Z11bTreeKernelP9BTreeNodeiP9BTreeNodei, @function
_Z41__device_stub__Z11bTreeKernelP9BTreeNodeiP9BTreeNodei:
.LFB3661:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
leaq 32(%rsp), %rcx
leaq 24(%rsp), %rdx
movl %esi, 4(%rsp)
leaq 40(%rsp), %rdi
leaq 52(%rsp), %rsi
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movl $1, 48(%rsp)
movq %rax, 88(%rsp)
leaq 4(%rsp), %rax
movq %rax, 96(%rsp)
movabsq $4294967297, %rax
movq %rax, 40(%rsp)
movq %rax, 52(%rsp)
movl $1, 60(%rsp)
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
jne .L8
pushq 32(%rsp)
.cfi_def_cfa_offset 136
leaq _Z11bTreeKernelP9BTreeNodei(%rip), %rdi
pushq 32(%rsp)
.cfi_def_cfa_offset 144
movq 68(%rsp), %rcx
movl 76(%rsp), %r8d
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
leaq 104(%rsp), %r9
call cudaLaunchKernel@PLT
popq %rax
.cfi_def_cfa_offset 136
popq %rdx
.cfi_def_cfa_offset 128
.L8:
movq 104(%rsp), %rax
subq %fs:40, %rax
je .L10
call __stack_chk_fail@PLT
.L10:
addq $120, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3661:
.size _Z41__device_stub__Z11bTreeKernelP9BTreeNodeiP9BTreeNodei, .-_Z41__device_stub__Z11bTreeKernelP9BTreeNodeiP9BTreeNodei
.globl _Z11bTreeKernelP9BTreeNodei
.type _Z11bTreeKernelP9BTreeNodei, @function
_Z11bTreeKernelP9BTreeNodei:
.LFB3662:
.cfi_startproc
endbr64
jmp _Z41__device_stub__Z11bTreeKernelP9BTreeNodeiP9BTreeNodei
.cfi_endproc
.LFE3662:
.size _Z11bTreeKernelP9BTreeNodei, .-_Z11bTreeKernelP9BTreeNodei
.section .rodata.str1.1
.LC3:
.string "Failed to allocate device memory"
.LC4:
.string "Failed to copy data to device"
.LC5:
.string "Kernel launch failed"
.LC6:
.string "Failed to copy data from device"
.LC7:
.string "Modified B-tree nodes:"
.LC8:
.string "Node "
.LC9:
.string ": "
.LC10:
.string " "
.LC11:
.string "| Children: "
.LC12:
.string "Failed to free device memory"
.section .text.startup,"ax",@progbits
.globl main
.type main, @function
main:
.LFB3636:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
movl $1536, %edi
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $56, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
call _Znam@PLT
xorl %edx, %edx
xorl %ecx, %ecx
movq %rax, %rbx
movq %rax, %rbp
.L14:
leal 1(%rcx), %esi
movl %edx, 24(%rax)
addq $48, %rax
movl %esi, -44(%rax)
leal 2(%rcx), %esi
movl %esi, -40(%rax)
leal 1(%rdx), %esi
movl %esi, -20(%rax)
leal 2(%rdx), %esi
movl %esi, -16(%rax)
leal 3(%rdx), %esi
addl $6, %edx
movl %ecx, -48(%rax)
addl $5, %ecx
movl $3, -28(%rax)
movl %esi, -12(%rax)
cmpl $192, %edx
jne .L14
leaq 8(%rsp), %rdi
movl $1536, %esi
call cudaMalloc@PLT
leaq .LC3(%rip), %rsi
movl %eax, %edi
call _Z14checkCudaError9cudaErrorPKc
movq 8(%rsp), %rdi
movl $1, %ecx
movq %rbx, %rsi
movl $1536, %edx
call cudaMemcpy@PLT
leaq .LC4(%rip), %rsi
movl %eax, %edi
call _Z14checkCudaError9cudaErrorPKc
movl $134217729, %edx
xorl %r9d, %r9d
xorl %r8d, %r8d
salq $5, %rdx
movl $1, %ecx
movl $1, %esi
movabsq $4294967297, %rdi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L15
movq 8(%rsp), %rdi
movl $32, %esi
call _Z41__device_stub__Z11bTreeKernelP9BTreeNodeiP9BTreeNodei
.L15:
call cudaGetLastError@PLT
leaq .LC5(%rip), %rsi
leaq _ZSt4cout(%rip), %r12
xorl %r13d, %r13d
movl %eax, %edi
leaq .LC10(%rip), %r15
call _Z14checkCudaError9cudaErrorPKc
movq 8(%rsp), %rsi
movl $2, %ecx
movq %rbx, %rdi
movl $1536, %edx
call cudaMemcpy@PLT
leaq .LC6(%rip), %rsi
movl %eax, %edi
call _Z14checkCudaError9cudaErrorPKc
leaq .LC7(%rip), %rsi
movq %r12, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
.L20:
leaq .LC8(%rip), %rsi
movq %r12, %rdi
xorl %r14d, %r14d
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movl %r13d, %esi
movq %rax, %rdi
call _ZNSolsEi@PLT
leaq .LC9(%rip), %rsi
movq %rax, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
.L16:
cmpl %r14d, 20(%rbp)
jle .L25
movl 0(%rbp,%r14,4), %esi
movq %r12, %rdi
incq %r14
call _ZNSolsEi@PLT
movq %r15, %rsi
movq %rax, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
jmp .L16
.L25:
leaq .LC11(%rip), %rsi
movq %r12, %rdi
xorl %r14d, %r14d
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
.L18:
cmpl %r14d, 20(%rbp)
jl .L26
movl 24(%rbp,%r14,4), %esi
movq %r12, %rdi
incq %r14
call _ZNSolsEi@PLT
movq %r15, %rsi
movq %rax, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
jmp .L18
.L26:
movq %r12, %rdi
incl %r13d
addq $48, %rbp
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
cmpl $32, %r13d
jne .L20
movq 8(%rsp), %rdi
call cudaFree@PLT
leaq .LC12(%rip), %rsi
movl %eax, %edi
call _Z14checkCudaError9cudaErrorPKc
movq %rbx, %rdi
call _ZdaPv@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
je .L21
call __stack_chk_fail@PLT
.L21:
addq $56, %rsp
.cfi_def_cfa_offset 56
xorl %eax, %eax
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3636:
.size main, .-main
.section .rodata.str1.1
.LC13:
.string "_Z11bTreeKernelP9BTreeNodei"
.section .text.startup
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3664:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
pushq $0
.cfi_def_cfa_offset 24
xorl %r9d, %r9d
orl $-1, %r8d
pushq $0
.cfi_def_cfa_offset 32
leaq .LC13(%rip), %rdx
movq %rax, %rdi
leaq _Z11bTreeKernelP9BTreeNodei(%rip), %rsi
pushq $0
.cfi_def_cfa_offset 40
movq %rdx, %rcx
pushq $0
.cfi_def_cfa_offset 48
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFunction@PLT
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
addq $32, %rsp
.cfi_def_cfa_offset 16
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
popq %rdx
.cfi_def_cfa_offset 8
jmp atexit@PLT
.cfi_endproc
.LFE3664:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
```
|
```amdasm
.text
.file "cuda_code_082743.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z26__device_stub__bTreeKernelP9BTreeNodei # -- Begin function _Z26__device_stub__bTreeKernelP9BTreeNodei
.type _Z26__device_stub__bTreeKernelP9BTreeNodei,@function
_Z26__device_stub__bTreeKernelP9BTreeNodei: # @_Z26__device_stub__bTreeKernelP9BTreeNodei
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $80, %rsp
.cfi_def_cfa_offset 128
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 24(%rsp), %rax
movq %rdi, (%rax)
leaq 4(%rsp), %rcx
movl %esi, (%rcx)
leaq 64(%rsp), %rbx
movq %rax, (%rbx)
movq %rcx, 8(%rbx)
leaq 48(%rsp), %r14
leaq 32(%rsp), %r15
leaq 16(%rsp), %r12
leaq 8(%rsp), %r13
movq %r14, %rdi
movq %r15, %rsi
movq %r12, %rdx
movq %r13, %rcx
callq __hipPopCallConfiguration
movq (%r14), %rsi
movl 8(%r14), %edx
movq (%r15), %rcx
movl 8(%r15), %r8d
movl $_Z11bTreeKernelP9BTreeNodei, %edi
movq %rbx, %r9
pushq (%r13)
.cfi_adjust_cfa_offset 8
pushq (%r12)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $96, %rsp
.cfi_adjust_cfa_offset -96
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z26__device_stub__bTreeKernelP9BTreeNodei, .Lfunc_end0-_Z26__device_stub__bTreeKernelP9BTreeNodei
.cfi_endproc
# -- End function
.globl _Z14checkCudaError10hipError_tPKc # -- Begin function _Z14checkCudaError10hipError_tPKc
.type _Z14checkCudaError10hipError_tPKc,@function
_Z14checkCudaError10hipError_tPKc: # @_Z14checkCudaError10hipError_tPKc
.cfi_startproc
# %bb.0:
testl %edi, %edi
jne .LBB1_2
# %bb.1:
retq
.LBB1_2:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
pushq %rax
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movq %rsi, %r14
movl %edi, %ebx
movl $_ZSt4cerr, %edi
movl $.L.str, %esi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movq %rax, %rdi
movq %r14, %rsi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movl $.L.str.1, %esi
movq %rax, %rdi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movq %rax, %r14
movl %ebx, %edi
callq hipGetErrorString
movq %r14, %rdi
movq %rax, %rsi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movl $.L.str.2, %esi
movq %rax, %rdi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movq %rax, %rdi
callq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_
movl $1, %edi
callq exit
.Lfunc_end1:
.size _Z14checkCudaError10hipError_tPKc, .Lfunc_end1-_Z14checkCudaError10hipError_tPKc
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
pushq %rax
.cfi_def_cfa_offset 64
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $1536, %edi # imm = 0x600
callq _Znam
movq %rax, %rbx
xorl %eax, %eax
movq %rbx, %rcx
xorl %edx, %edx
xorl %esi, %esi
.LBB2_1: # %.lr.ph
# =>This Loop Header: Depth=1
# Child Loop BB2_2 Depth 2
# Child Loop BB2_5 Depth 2
leaq (%rsi,%rsi,2), %r8
shlq $4, %r8
leaq (%rbx,%r8), %rdi
addq $20, %rdi
movl $3, 20(%rbx,%r8)
xorl %r8d, %r8d
.LBB2_2: # Parent Loop BB2_1 Depth=1
# => This Inner Loop Header: Depth=2
leal (%rdx,%r8), %r9d
movl %r9d, (%rcx,%r8,4)
incq %r8
movslq (%rdi), %r9
cmpq %r9, %r8
jl .LBB2_2
# %bb.3: # %.preheader
# in Loop: Header=BB2_1 Depth=1
movl %r9d, %edi
testl %edi, %edi
js .LBB2_6
# %bb.4: # %.lr.ph64
# in Loop: Header=BB2_1 Depth=1
movq $-1, %r8
.LBB2_5: # Parent Loop BB2_1 Depth=1
# => This Inner Loop Header: Depth=2
leal (%rax,%r8), %r9d
incl %r9d
movl %r9d, 28(%rcx,%r8,4)
incq %r8
cmpq %rdi, %r8
jb .LBB2_5
.LBB2_6: # %._crit_edge
# in Loop: Header=BB2_1 Depth=1
incq %rsi
addq $5, %rdx
addq $48, %rcx
addq $6, %rax
cmpq $32, %rsi
jne .LBB2_1
# %bb.7:
movq %rsp, %r14
movl $1536, %esi # imm = 0x600
movq %r14, %rdi
callq hipMalloc
movl $.L.str.3, %esi
movl %eax, %edi
callq _Z14checkCudaError10hipError_tPKc
movq (%r14), %rdi
movl $1536, %edx # imm = 0x600
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movl $.L.str.4, %esi
movl %eax, %edi
callq _Z14checkCudaError10hipError_tPKc
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 31(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_9
# %bb.8:
movq (%rsp), %rdi
movl $32, %esi
callq _Z26__device_stub__bTreeKernelP9BTreeNodei
.LBB2_9:
callq hipGetLastError
movl $.L.str.5, %esi
movl %eax, %edi
callq _Z14checkCudaError10hipError_tPKc
movq (%rsp), %rsi
movl $1536, %edx # imm = 0x600
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
movl $.L.str.6, %esi
movl %eax, %edi
callq _Z14checkCudaError10hipError_tPKc
movl $_ZSt4cout, %r15d
movl $_ZSt4cout, %edi
movl $.L.str.7, %esi
movl $22, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rdi
addq %r15, %rdi
movl $10, %esi
callq _ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
xorl %r14d, %r14d
movq %rbx, %r12
.LBB2_10: # =>This Loop Header: Depth=1
# Child Loop BB2_12 Depth 2
# Child Loop BB2_15 Depth 2
movl $_ZSt4cout, %edi
movl $.L.str.8, %esi
movl $5, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl %r14d, %esi
callq _ZNSolsEi
movl $.L.str.9, %esi
movl $2, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
leaq (%r14,%r14,2), %rax
shlq $4, %rax
leaq (%rbx,%rax), %r13
addq $20, %r13
cmpl $0, 20(%rbx,%rax)
jle .LBB2_13
# %bb.11: # %.lr.ph68
# in Loop: Header=BB2_10 Depth=1
xorl %ebp, %ebp
.LBB2_12: # Parent Loop BB2_10 Depth=1
# => This Inner Loop Header: Depth=2
movl (%r12,%rbp,4), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movl $.L.str.10, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
incq %rbp
movslq (%r13), %rax
cmpq %rax, %rbp
jl .LBB2_12
.LBB2_13: # %._crit_edge69
# in Loop: Header=BB2_10 Depth=1
movl $_ZSt4cout, %edi
movl $.L.str.11, %esi
movl $12, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
cmpl $0, (%r13)
js .LBB2_16
# %bb.14: # %.lr.ph74.preheader
# in Loop: Header=BB2_10 Depth=1
movq $-1, %rbp
.LBB2_15: # %.lr.ph74
# Parent Loop BB2_10 Depth=1
# => This Inner Loop Header: Depth=2
movl 28(%r12,%rbp,4), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movl $.L.str.10, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movslq (%r13), %rax
incq %rbp
cmpq %rax, %rbp
jl .LBB2_15
.LBB2_16: # %._crit_edge75
# in Loop: Header=BB2_10 Depth=1
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rdi
addq %r15, %rdi
movl $10, %esi
callq _ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
incq %r14
addq $48, %r12
cmpq $32, %r14
jne .LBB2_10
# %bb.17:
movq (%rsp), %rdi
callq hipFree
movl $.L.str.12, %esi
movl %eax, %edi
callq _Z14checkCudaError10hipError_tPKc
movq %rbx, %rdi
callq _ZdaPv
xorl %eax, %eax
addq $8, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, %rdi
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11bTreeKernelP9BTreeNodei, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z11bTreeKernelP9BTreeNodei,@object # @_Z11bTreeKernelP9BTreeNodei
.section .rodata,"a",@progbits
.globl _Z11bTreeKernelP9BTreeNodei
.p2align 3, 0x0
_Z11bTreeKernelP9BTreeNodei:
.quad _Z26__device_stub__bTreeKernelP9BTreeNodei
.size _Z11bTreeKernelP9BTreeNodei, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "CUDA Error: "
.size .L.str, 13
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz " ("
.size .L.str.1, 3
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz ")"
.size .L.str.2, 2
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Failed to allocate device memory"
.size .L.str.3, 33
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Failed to copy data to device"
.size .L.str.4, 30
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "Kernel launch failed"
.size .L.str.5, 21
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "Failed to copy data from device"
.size .L.str.6, 32
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "Modified B-tree nodes:"
.size .L.str.7, 23
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "Node "
.size .L.str.8, 6
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz ": "
.size .L.str.9, 3
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz " "
.size .L.str.10, 2
.type .L.str.11,@object # @.str.11
.L.str.11:
.asciz "| Children: "
.size .L.str.11, 13
.type .L.str.12,@object # @.str.12
.L.str.12:
.asciz "Failed to free device memory"
.size .L.str.12, 29
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z11bTreeKernelP9BTreeNodei"
.size .L__unnamed_1, 28
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z26__device_stub__bTreeKernelP9BTreeNodei
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z11bTreeKernelP9BTreeNodei
.addrsig_sym _ZSt4cerr
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
```
| 4,628 | 6,203 |
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