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module lms_ctr_mm_interconnect_0_router
(
// -------------------
// Clock & Reset
// -------------------
input clk,
input reset,
// -------------------
// Command Sink (Input)
// -------------------
input sink_valid,
input [103-1 : 0] sink_data,
input sink_startofpacket,
input sink_endofpacket,
output sink_ready,
// -------------------
// Command Source (Output)
// -------------------
output src_valid,
output reg [103-1 : 0] src_data,
output reg [15-1 : 0] src_channel,
output src_startofpacket,
output src_endofpacket,
input src_ready
);
// -------------------------------------------------------
// Local parameters and variables
// -------------------------------------------------------
localparam PKT_ADDR_H = 57;
localparam PKT_ADDR_L = 36;
localparam PKT_DEST_ID_H = 89;
localparam PKT_DEST_ID_L = 86;
localparam PKT_PROTECTION_H = 93;
localparam PKT_PROTECTION_L = 91;
localparam ST_DATA_W = 103;
localparam ST_CHANNEL_W = 15;
localparam DECODER_TYPE = 0;
localparam PKT_TRANS_WRITE = 60;
localparam PKT_TRANS_READ = 61;
localparam PKT_ADDR_W = PKT_ADDR_H-PKT_ADDR_L + 1;
localparam PKT_DEST_ID_W = PKT_DEST_ID_H-PKT_DEST_ID_L + 1;
// -------------------------------------------------------
// Figure out the number of bits to mask off for each slave span
// during address decoding
// -------------------------------------------------------
localparam PAD0 = log2ceil(64'h200000 - 64'h100000);
localparam PAD1 = log2ceil(64'h201000 - 64'h200000);
localparam PAD2 = log2ceil(64'h202000 - 64'h201800);
localparam PAD3 = log2ceil(64'h202020 - 64'h202000);
localparam PAD4 = log2ceil(64'h202040 - 64'h202020);
localparam PAD5 = log2ceil(64'h202060 - 64'h202040);
localparam PAD6 = log2ceil(64'h202080 - 64'h202060);
localparam PAD7 = log2ceil(64'h2020a0 - 64'h202080);
localparam PAD8 = log2ceil(64'h2020c0 - 64'h2020a0);
localparam PAD9 = log2ceil(64'h2020e0 - 64'h2020c0);
localparam PAD10 = log2ceil(64'h2020f0 - 64'h2020e0);
localparam PAD11 = log2ceil(64'h202100 - 64'h2020f0);
localparam PAD12 = log2ceil(64'h202110 - 64'h202100);
localparam PAD13 = log2ceil(64'h202118 - 64'h202110);
localparam PAD14 = log2ceil(64'h202120 - 64'h202118);
// -------------------------------------------------------
// Work out which address bits are significant based on the
// address range of the slaves. If the required width is too
// large or too small, we use the address field width instead.
// -------------------------------------------------------
localparam ADDR_RANGE = 64'h202120;
localparam RANGE_ADDR_WIDTH = log2ceil(ADDR_RANGE);
localparam OPTIMIZED_ADDR_H = (RANGE_ADDR_WIDTH > PKT_ADDR_W) ||
(RANGE_ADDR_WIDTH == 0) ?
PKT_ADDR_H :
PKT_ADDR_L + RANGE_ADDR_WIDTH - 1;
localparam RG = RANGE_ADDR_WIDTH-1;
localparam REAL_ADDRESS_RANGE = OPTIMIZED_ADDR_H - PKT_ADDR_L;
reg [PKT_ADDR_W-1 : 0] address;
always @* begin
address = {PKT_ADDR_W{1'b0}};
address [REAL_ADDRESS_RANGE:0] = sink_data[OPTIMIZED_ADDR_H : PKT_ADDR_L];
end
// -------------------------------------------------------
// Pass almost everything through, untouched
// -------------------------------------------------------
assign sink_ready = src_ready;
assign src_valid = sink_valid;
assign src_startofpacket = sink_startofpacket;
assign src_endofpacket = sink_endofpacket;
wire [PKT_DEST_ID_W-1:0] default_destid;
wire [15-1 : 0] default_src_channel;
// -------------------------------------------------------
// Write and read transaction signals
// -------------------------------------------------------
wire read_transaction;
assign read_transaction = sink_data[PKT_TRANS_READ];
lms_ctr_mm_interconnect_0_router_default_decode the_default_decode(
.default_destination_id (default_destid),
.default_wr_channel (),
.default_rd_channel (),
.default_src_channel (default_src_channel)
);
always @* begin
src_data = sink_data;
src_channel = default_src_channel;
src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = default_destid;
// --------------------------------------------------
// Address Decoder
// Sets the channel and destination ID based on the address
// --------------------------------------------------
// ( 0x100000 .. 0x200000 )
if ( {address[RG:PAD0],{PAD0{1'b0}}} == 22'h100000 ) begin
src_channel = 15'b000000000100000;
src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 10;
end
// ( 0x200000 .. 0x201000 )
if ( {address[RG:PAD1],{PAD1{1'b0}}} == 22'h200000 ) begin
src_channel = 15'b000100000000000;
src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 11;
end
// ( 0x201800 .. 0x202000 )
if ( {address[RG:PAD2],{PAD2{1'b0}}} == 22'h201800 ) begin
src_channel = 15'b000000001000000;
src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 8;
end
// ( 0x202000 .. 0x202020 )
if ( {address[RG:PAD3],{PAD3{1'b0}}} == 22'h202000 ) begin
src_channel = 15'b100000000000000;
src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 3;
end
// ( 0x202020 .. 0x202040 )
if ( {address[RG:PAD4],{PAD4{1'b0}}} == 22'h202020 ) begin
src_channel = 15'b010000000000000;
src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 1;
end
// ( 0x202040 .. 0x202060 )
if ( {address[RG:PAD5],{PAD5{1'b0}}} == 22'h202040 ) begin
src_channel = 15'b001000000000000;
src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 4;
end
// ( 0x202060 .. 0x202080 )
if ( {address[RG:PAD6],{PAD6{1'b0}}} == 22'h202060 ) begin
src_channel = 15'b000010000000000;
src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 7;
end
// ( 0x202080 .. 0x2020a0 )
if ( {address[RG:PAD7],{PAD7{1'b0}}} == 22'h202080 ) begin
src_channel = 15'b000001000000000;
src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 14;
end
// ( 0x2020a0 .. 0x2020c0 )
if ( {address[RG:PAD8],{PAD8{1'b0}}} == 22'h2020a0 ) begin
src_channel = 15'b000000000000100;
src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 5;
end
// ( 0x2020c0 .. 0x2020e0 )
if ( {address[RG:PAD9],{PAD9{1'b0}}} == 22'h2020c0 ) begin
src_channel = 15'b000000000000001;
src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 2;
end
// ( 0x2020e0 .. 0x2020f0 )
if ( {address[RG:PAD10],{PAD10{1'b0}}} == 22'h2020e0 ) begin
src_channel = 15'b000000100000000;
src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 6;
end
// ( 0x2020f0 .. 0x202100 )
if ( {address[RG:PAD11],{PAD11{1'b0}}} == 22'h2020f0 && read_transaction ) begin
src_channel = 15'b000000010000000;
src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 12;
end
// ( 0x202100 .. 0x202110 )
if ( {address[RG:PAD12],{PAD12{1'b0}}} == 22'h202100 ) begin
src_channel = 15'b000000000000010;
src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 0;
end
// ( 0x202110 .. 0x202118 )
if ( {address[RG:PAD13],{PAD13{1'b0}}} == 22'h202110 ) begin
src_channel = 15'b000000000010000;
src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 9;
end
// ( 0x202118 .. 0x202120 )
if ( {address[RG:PAD14],{PAD14{1'b0}}} == 22'h202118 && read_transaction ) begin
src_channel = 15'b000000000001000;
src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 13;
end
end
// --------------------------------------------------
// Ceil(log2()) function
// --------------------------------------------------
function integer log2ceil;
input reg[65:0] val;
reg [65:0] i;
begin
i = 1;
log2ceil = 0;
while (i < val) begin
log2ceil = log2ceil + 1;
i = i << 1;
end
end
endfunction
endmodule |
module lms_ctr_mm_interconnect_0_rsp_demux
(
// -------------------
// Sink
// -------------------
input [1-1 : 0] sink_valid,
input [103-1 : 0] sink_data, // ST_DATA_W=103
input [15-1 : 0] sink_channel, // ST_CHANNEL_W=15
input sink_startofpacket,
input sink_endofpacket,
output sink_ready,
// -------------------
// Sources
// -------------------
output reg src0_valid,
output reg [103-1 : 0] src0_data, // ST_DATA_W=103
output reg [15-1 : 0] src0_channel, // ST_CHANNEL_W=15
output reg src0_startofpacket,
output reg src0_endofpacket,
input src0_ready,
// -------------------
// Clock & Reset
// -------------------
(*altera_attribute = "-name MESSAGE_DISABLE 15610" *) // setting message suppression on clk
input clk,
(*altera_attribute = "-name MESSAGE_DISABLE 15610" *) // setting message suppression on reset
input reset
);
localparam NUM_OUTPUTS = 1;
wire [NUM_OUTPUTS - 1 : 0] ready_vector;
// -------------------
// Demux
// -------------------
always @* begin
src0_data = sink_data;
src0_startofpacket = sink_startofpacket;
src0_endofpacket = sink_endofpacket;
src0_channel = sink_channel >> NUM_OUTPUTS;
src0_valid = sink_channel[0] && sink_valid;
end
// -------------------
// Backpressure
// -------------------
assign ready_vector[0] = src0_ready;
assign sink_ready = |(sink_channel & {{14{1'b0}},{ready_vector[NUM_OUTPUTS - 1 : 0]}});
endmodule |
module lms_ctr_irq_mapper
(
// -------------------
// Clock & Reset
// -------------------
input clk,
input reset,
// -------------------
// IRQ Receivers
// -------------------
input receiver0_irq,
input receiver1_irq,
input receiver2_irq,
input receiver3_irq,
input receiver4_irq,
// -------------------
// Command Source (Output)
// -------------------
output reg [31 : 0] sender_irq
);
always @* begin
sender_irq = 0;
sender_irq[0] = receiver0_irq;
sender_irq[1] = receiver1_irq;
sender_irq[2] = receiver2_irq;
sender_irq[3] = receiver3_irq;
sender_irq[4] = receiver4_irq;
end
endmodule |
module lms_ctr_mm_interconnect_0_cmd_demux_001
(
// -------------------
// Sink
// -------------------
input [1-1 : 0] sink_valid,
input [103-1 : 0] sink_data, // ST_DATA_W=103
input [15-1 : 0] sink_channel, // ST_CHANNEL_W=15
input sink_startofpacket,
input sink_endofpacket,
output sink_ready,
// -------------------
// Sources
// -------------------
output reg src0_valid,
output reg [103-1 : 0] src0_data, // ST_DATA_W=103
output reg [15-1 : 0] src0_channel, // ST_CHANNEL_W=15
output reg src0_startofpacket,
output reg src0_endofpacket,
input src0_ready,
output reg src1_valid,
output reg [103-1 : 0] src1_data, // ST_DATA_W=103
output reg [15-1 : 0] src1_channel, // ST_CHANNEL_W=15
output reg src1_startofpacket,
output reg src1_endofpacket,
input src1_ready,
// -------------------
// Clock & Reset
// -------------------
(*altera_attribute = "-name MESSAGE_DISABLE 15610" *) // setting message suppression on clk
input clk,
(*altera_attribute = "-name MESSAGE_DISABLE 15610" *) // setting message suppression on reset
input reset
);
localparam NUM_OUTPUTS = 2;
wire [NUM_OUTPUTS - 1 : 0] ready_vector;
// -------------------
// Demux
// -------------------
always @* begin
src0_data = sink_data;
src0_startofpacket = sink_startofpacket;
src0_endofpacket = sink_endofpacket;
src0_channel = sink_channel >> NUM_OUTPUTS;
src0_valid = sink_channel[0] && sink_valid;
src1_data = sink_data;
src1_startofpacket = sink_startofpacket;
src1_endofpacket = sink_endofpacket;
src1_channel = sink_channel >> NUM_OUTPUTS;
src1_valid = sink_channel[1] && sink_valid;
end
// -------------------
// Backpressure
// -------------------
assign ready_vector[0] = src0_ready;
assign ready_vector[1] = src1_ready;
assign sink_ready = |(sink_channel & {{13{1'b0}},{ready_vector[NUM_OUTPUTS - 1 : 0]}});
endmodule |
module lms_ctr_mm_interconnect_0_rsp_mux_001
(
// ----------------------
// Sinks
// ----------------------
input sink0_valid,
input [103-1 : 0] sink0_data,
input [15-1: 0] sink0_channel,
input sink0_startofpacket,
input sink0_endofpacket,
output sink0_ready,
input sink1_valid,
input [103-1 : 0] sink1_data,
input [15-1: 0] sink1_channel,
input sink1_startofpacket,
input sink1_endofpacket,
output sink1_ready,
// ----------------------
// Source
// ----------------------
output src_valid,
output [103-1 : 0] src_data,
output [15-1 : 0] src_channel,
output src_startofpacket,
output src_endofpacket,
input src_ready,
// ----------------------
// Clock & Reset
// ----------------------
input clk,
input reset
);
localparam PAYLOAD_W = 103 + 15 + 2;
localparam NUM_INPUTS = 2;
localparam SHARE_COUNTER_W = 1;
localparam PIPELINE_ARB = 0;
localparam ST_DATA_W = 103;
localparam ST_CHANNEL_W = 15;
localparam PKT_TRANS_LOCK = 62;
// ------------------------------------------
// Signals
// ------------------------------------------
wire [NUM_INPUTS - 1 : 0] request;
wire [NUM_INPUTS - 1 : 0] valid;
wire [NUM_INPUTS - 1 : 0] grant;
wire [NUM_INPUTS - 1 : 0] next_grant;
reg [NUM_INPUTS - 1 : 0] saved_grant;
reg [PAYLOAD_W - 1 : 0] src_payload;
wire last_cycle;
reg packet_in_progress;
reg update_grant;
wire [PAYLOAD_W - 1 : 0] sink0_payload;
wire [PAYLOAD_W - 1 : 0] sink1_payload;
assign valid[0] = sink0_valid;
assign valid[1] = sink1_valid;
// ------------------------------------------
// ------------------------------------------
// Grant Logic & Updates
// ------------------------------------------
// ------------------------------------------
reg [NUM_INPUTS - 1 : 0] lock;
always @* begin
lock[0] = sink0_data[62];
lock[1] = sink1_data[62];
end
assign last_cycle = src_valid & src_ready & src_endofpacket & ~(|(lock & grant));
// ------------------------------------------
// We're working on a packet at any time valid is high, except
// when this is the endofpacket.
// ------------------------------------------
always @(posedge clk or posedge reset) begin
if (reset) begin
packet_in_progress <= 1'b0;
end
else begin
if (last_cycle)
packet_in_progress <= 1'b0;
else if (src_valid)
packet_in_progress <= 1'b1;
end
end
// ------------------------------------------
// Shares
//
// Special case: all-equal shares _should_ be optimized into assigning a
// constant to next_grant_share.
// Special case: all-1's shares _should_ result in the share counter
// being optimized away.
// ------------------------------------------
// Input | arb shares | counter load value
// 0 | 1 | 0
// 1 | 1 | 0
wire [SHARE_COUNTER_W - 1 : 0] share_0 = 1'd0;
wire [SHARE_COUNTER_W - 1 : 0] share_1 = 1'd0;
// ------------------------------------------
// Choose the share value corresponding to the grant.
// ------------------------------------------
reg [SHARE_COUNTER_W - 1 : 0] next_grant_share;
always @* begin
next_grant_share =
share_0 & { SHARE_COUNTER_W {next_grant[0]} } |
share_1 & { SHARE_COUNTER_W {next_grant[1]} };
end
// ------------------------------------------
// Flag to indicate first packet of an arb sequence.
// ------------------------------------------
wire grant_changed = ~packet_in_progress && ~(|(saved_grant & valid));
reg first_packet_r;
wire first_packet = grant_changed | first_packet_r;
always @(posedge clk or posedge reset) begin
if (reset) begin
first_packet_r <= 1'b0;
end
else begin
if (update_grant)
first_packet_r <= 1'b1;
else if (last_cycle)
first_packet_r <= 1'b0;
else if (grant_changed)
first_packet_r <= 1'b1;
end
end
// ------------------------------------------
// Compute the next share-count value.
// ------------------------------------------
reg [SHARE_COUNTER_W - 1 : 0] p1_share_count;
reg [SHARE_COUNTER_W - 1 : 0] share_count;
reg share_count_zero_flag;
always @* begin
if (first_packet) begin
p1_share_count = next_grant_share;
end
else begin
// Update the counter, but don't decrement below 0.
p1_share_count = share_count_zero_flag ? '0 : share_count - 1'b1;
end
end
// ------------------------------------------
// Update the share counter and share-counter=zero flag.
// ------------------------------------------
always @(posedge clk or posedge reset) begin
if (reset) begin
share_count <= '0;
share_count_zero_flag <= 1'b1;
end
else begin
if (last_cycle) begin
share_count <= p1_share_count;
share_count_zero_flag <= (p1_share_count == '0);
end
end
end
// ------------------------------------------
// For each input, maintain a final_packet signal which goes active for the
// last packet of a full-share packet sequence. Example: if I have 4
// shares and I'm continuously requesting, final_packet is active in the
// 4th packet.
// ------------------------------------------
wire final_packet_0 = 1'b1;
wire final_packet_1 = 1'b1;
// ------------------------------------------
// Concatenate all final_packet signals (wire or reg) into a handy vector.
// ------------------------------------------
wire [NUM_INPUTS - 1 : 0] final_packet = {
final_packet_1,
final_packet_0
};
// ------------------------------------------
// ------------------------------------------
wire p1_done = |(final_packet & grant);
// ------------------------------------------
// Flag for the first cycle of packets within an
// arb sequence
// ------------------------------------------
reg first_cycle;
always @(posedge clk, posedge reset) begin
if (reset)
first_cycle <= 0;
else
first_cycle <= last_cycle && ~p1_done;
end
always @* begin
update_grant = 0;
// ------------------------------------------
// No arbitration pipeline, update grant whenever
// the current arb winner has consumed all shares,
// or all requests are low
// ------------------------------------------
update_grant = (last_cycle && p1_done) || (first_cycle && ~(|valid));
update_grant = last_cycle;
end
wire save_grant;
assign save_grant = 1;
assign grant = next_grant;
always @(posedge clk, posedge reset) begin
if (reset)
saved_grant <= '0;
else if (save_grant)
saved_grant <= next_grant;
end
// ------------------------------------------
// ------------------------------------------
// Arbitrator
// ------------------------------------------
// ------------------------------------------
// ------------------------------------------
// Create a request vector that stays high during
// the packet for unpipelined arbitration.
//
// The pipelined arbitration scheme does not require
// request to be held high during the packet.
// ------------------------------------------
assign request = valid;
wire [NUM_INPUTS - 1 : 0] next_grant_from_arb;
altera_merlin_arbitrator
#(
.NUM_REQUESTERS(NUM_INPUTS),
.SCHEME ("no-arb"),
.PIPELINE (0)
) arb (
.clk (clk),
.reset (reset),
.request (request),
.grant (next_grant_from_arb),
.save_top_priority (src_valid),
.increment_top_priority (update_grant)
);
assign next_grant = next_grant_from_arb;
// ------------------------------------------
// ------------------------------------------
// Mux
//
// Implemented as a sum of products.
// ------------------------------------------
// ------------------------------------------
assign sink0_ready = src_ready && grant[0];
assign sink1_ready = src_ready && grant[1];
assign src_valid = |(grant & valid);
always @* begin
src_payload =
sink0_payload & {PAYLOAD_W {grant[0]} } |
sink1_payload & {PAYLOAD_W {grant[1]} };
end
// ------------------------------------------
// Mux Payload Mapping
// ------------------------------------------
assign sink0_payload = {sink0_channel,sink0_data,
sink0_startofpacket,sink0_endofpacket};
assign sink1_payload = {sink1_channel,sink1_data,
sink1_startofpacket,sink1_endofpacket};
assign {src_channel,src_data,src_startofpacket,src_endofpacket} = src_payload;
endmodule |
module lms_ctr_nios2_cpu_custom_instruction_master_comb_xconnect
(
// -------------------
// Custom instruction masters
// -------------------
output [31 : 0] ci_master0_dataa,
output [31 : 0] ci_master0_datab,
input [31 : 0] ci_master0_result,
output [ 7 : 0] ci_master0_n,
output ci_master0_readra,
output ci_master0_readrb,
output ci_master0_writerc,
output [ 4 : 0] ci_master0_a,
output [ 4 : 0] ci_master0_b,
output [ 4 : 0] ci_master0_c,
output [31 : 0] ci_master0_ipending,
output ci_master0_estatus,
// -------------------
// Custom instruction slave
// -------------------
input [31 : 0] ci_slave_dataa,
input [31 : 0] ci_slave_datab,
output [31 : 0] ci_slave_result,
input [ 7 : 0] ci_slave_n,
input ci_slave_readra,
input ci_slave_readrb,
input ci_slave_writerc,
input [ 4 : 0] ci_slave_a,
input [ 4 : 0] ci_slave_b,
input [ 4 : 0] ci_slave_c,
input [31 : 0] ci_slave_ipending,
input ci_slave_estatus
);
wire select0;
// -------------------------------------------------------
// Wire non-control signals through to each master
// -------------------------------------------------------
assign ci_master0_dataa = ci_slave_dataa;
assign ci_master0_datab = ci_slave_datab;
assign ci_master0_n = ci_slave_n;
assign ci_master0_a = ci_slave_a;
assign ci_master0_b = ci_slave_b;
assign ci_master0_c = ci_slave_c;
assign ci_master0_ipending = ci_slave_ipending;
assign ci_master0_estatus = ci_slave_estatus;
// -------------------------------------------------------
// Figure out which output is selected, and use that to
// gate control signals
// -------------------------------------------------------
assign select0 = ci_slave_n >= 0 && ci_slave_n < 1;
assign ci_master0_readra = (select0 && ci_slave_readra);
assign ci_master0_readrb = (select0 && ci_slave_readrb);
assign ci_master0_writerc = (select0 && ci_slave_writerc);
// -------------------------------------------------------
// Use the select signal to figure out which result to mux
// back
// -------------------------------------------------------
assign ci_slave_result = {32{ select0 }} & ci_master0_result
;
endmodule |
module factory_mm_interconnect_0_cmd_mux
(
// ----------------------
// Sinks
// ----------------------
input sink0_valid,
input [98-1 : 0] sink0_data,
input [6-1: 0] sink0_channel,
input sink0_startofpacket,
input sink0_endofpacket,
output sink0_ready,
// ----------------------
// Source
// ----------------------
output src_valid,
output [98-1 : 0] src_data,
output [6-1 : 0] src_channel,
output src_startofpacket,
output src_endofpacket,
input src_ready,
// ----------------------
// Clock & Reset
// ----------------------
input clk,
input reset
);
localparam PAYLOAD_W = 98 + 6 + 2;
localparam NUM_INPUTS = 1;
localparam SHARE_COUNTER_W = 1;
localparam PIPELINE_ARB = 1;
localparam ST_DATA_W = 98;
localparam ST_CHANNEL_W = 6;
localparam PKT_TRANS_LOCK = 61;
assign src_valid = sink0_valid;
assign src_data = sink0_data;
assign src_channel = sink0_channel;
assign src_startofpacket = sink0_startofpacket;
assign src_endofpacket = sink0_endofpacket;
assign sink0_ready = src_ready;
endmodule |
module factory_mm_interconnect_0_cmd_demux
(
// -------------------
// Sink
// -------------------
input [1-1 : 0] sink_valid,
input [98-1 : 0] sink_data, // ST_DATA_W=98
input [6-1 : 0] sink_channel, // ST_CHANNEL_W=6
input sink_startofpacket,
input sink_endofpacket,
output sink_ready,
// -------------------
// Sources
// -------------------
output reg src0_valid,
output reg [98-1 : 0] src0_data, // ST_DATA_W=98
output reg [6-1 : 0] src0_channel, // ST_CHANNEL_W=6
output reg src0_startofpacket,
output reg src0_endofpacket,
input src0_ready,
output reg src1_valid,
output reg [98-1 : 0] src1_data, // ST_DATA_W=98
output reg [6-1 : 0] src1_channel, // ST_CHANNEL_W=6
output reg src1_startofpacket,
output reg src1_endofpacket,
input src1_ready,
output reg src2_valid,
output reg [98-1 : 0] src2_data, // ST_DATA_W=98
output reg [6-1 : 0] src2_channel, // ST_CHANNEL_W=6
output reg src2_startofpacket,
output reg src2_endofpacket,
input src2_ready,
output reg src3_valid,
output reg [98-1 : 0] src3_data, // ST_DATA_W=98
output reg [6-1 : 0] src3_channel, // ST_CHANNEL_W=6
output reg src3_startofpacket,
output reg src3_endofpacket,
input src3_ready,
output reg src4_valid,
output reg [98-1 : 0] src4_data, // ST_DATA_W=98
output reg [6-1 : 0] src4_channel, // ST_CHANNEL_W=6
output reg src4_startofpacket,
output reg src4_endofpacket,
input src4_ready,
output reg src5_valid,
output reg [98-1 : 0] src5_data, // ST_DATA_W=98
output reg [6-1 : 0] src5_channel, // ST_CHANNEL_W=6
output reg src5_startofpacket,
output reg src5_endofpacket,
input src5_ready,
// -------------------
// Clock & Reset
// -------------------
(*altera_attribute = "-name MESSAGE_DISABLE 15610" *) // setting message suppression on clk
input clk,
(*altera_attribute = "-name MESSAGE_DISABLE 15610" *) // setting message suppression on reset
input reset
);
localparam NUM_OUTPUTS = 6;
wire [NUM_OUTPUTS - 1 : 0] ready_vector;
// -------------------
// Demux
// -------------------
always @* begin
src0_data = sink_data;
src0_startofpacket = sink_startofpacket;
src0_endofpacket = sink_endofpacket;
src0_channel = sink_channel >> NUM_OUTPUTS;
src0_valid = sink_channel[0] && sink_valid;
src1_data = sink_data;
src1_startofpacket = sink_startofpacket;
src1_endofpacket = sink_endofpacket;
src1_channel = sink_channel >> NUM_OUTPUTS;
src1_valid = sink_channel[1] && sink_valid;
src2_data = sink_data;
src2_startofpacket = sink_startofpacket;
src2_endofpacket = sink_endofpacket;
src2_channel = sink_channel >> NUM_OUTPUTS;
src2_valid = sink_channel[2] && sink_valid;
src3_data = sink_data;
src3_startofpacket = sink_startofpacket;
src3_endofpacket = sink_endofpacket;
src3_channel = sink_channel >> NUM_OUTPUTS;
src3_valid = sink_channel[3] && sink_valid;
src4_data = sink_data;
src4_startofpacket = sink_startofpacket;
src4_endofpacket = sink_endofpacket;
src4_channel = sink_channel >> NUM_OUTPUTS;
src4_valid = sink_channel[4] && sink_valid;
src5_data = sink_data;
src5_startofpacket = sink_startofpacket;
src5_endofpacket = sink_endofpacket;
src5_channel = sink_channel >> NUM_OUTPUTS;
src5_valid = sink_channel[5] && sink_valid;
end
// -------------------
// Backpressure
// -------------------
assign ready_vector[0] = src0_ready;
assign ready_vector[1] = src1_ready;
assign ready_vector[2] = src2_ready;
assign ready_vector[3] = src3_ready;
assign ready_vector[4] = src4_ready;
assign ready_vector[5] = src5_ready;
assign sink_ready = |(sink_channel & ready_vector);
endmodule |
module factory_mm_interconnect_0_rsp_demux
(
// -------------------
// Sink
// -------------------
input [1-1 : 0] sink_valid,
input [98-1 : 0] sink_data, // ST_DATA_W=98
input [6-1 : 0] sink_channel, // ST_CHANNEL_W=6
input sink_startofpacket,
input sink_endofpacket,
output sink_ready,
// -------------------
// Sources
// -------------------
output reg src0_valid,
output reg [98-1 : 0] src0_data, // ST_DATA_W=98
output reg [6-1 : 0] src0_channel, // ST_CHANNEL_W=6
output reg src0_startofpacket,
output reg src0_endofpacket,
input src0_ready,
// -------------------
// Clock & Reset
// -------------------
(*altera_attribute = "-name MESSAGE_DISABLE 15610" *) // setting message suppression on clk
input clk,
(*altera_attribute = "-name MESSAGE_DISABLE 15610" *) // setting message suppression on reset
input reset
);
localparam NUM_OUTPUTS = 1;
wire [NUM_OUTPUTS - 1 : 0] ready_vector;
// -------------------
// Demux
// -------------------
always @* begin
src0_data = sink_data;
src0_startofpacket = sink_startofpacket;
src0_endofpacket = sink_endofpacket;
src0_channel = sink_channel >> NUM_OUTPUTS;
src0_valid = sink_channel[0] && sink_valid;
end
// -------------------
// Backpressure
// -------------------
assign ready_vector[0] = src0_ready;
assign sink_ready = |(sink_channel & {{5{1'b0}},{ready_vector[NUM_OUTPUTS - 1 : 0]}});
endmodule |
module factory_mm_interconnect_0_router_default_decode
#(
parameter DEFAULT_CHANNEL = 4,
DEFAULT_WR_CHANNEL = -1,
DEFAULT_RD_CHANNEL = -1,
DEFAULT_DESTID = 4
)
(output [84 - 82 : 0] default_destination_id,
output [6-1 : 0] default_wr_channel,
output [6-1 : 0] default_rd_channel,
output [6-1 : 0] default_src_channel
);
assign default_destination_id =
DEFAULT_DESTID[84 - 82 : 0];
generate
if (DEFAULT_CHANNEL == -1) begin : no_default_channel_assignment
assign default_src_channel = '0;
end
else begin : default_channel_assignment
assign default_src_channel = 6'b1 << DEFAULT_CHANNEL;
end
endgenerate
generate
if (DEFAULT_RD_CHANNEL == -1) begin : no_default_rw_channel_assignment
assign default_wr_channel = '0;
assign default_rd_channel = '0;
end
else begin : default_rw_channel_assignment
assign default_wr_channel = 6'b1 << DEFAULT_WR_CHANNEL;
assign default_rd_channel = 6'b1 << DEFAULT_RD_CHANNEL;
end
endgenerate
endmodule |
module factory_mm_interconnect_0_router
(
// -------------------
// Clock & Reset
// -------------------
input clk,
input reset,
// -------------------
// Command Sink (Input)
// -------------------
input sink_valid,
input [98-1 : 0] sink_data,
input sink_startofpacket,
input sink_endofpacket,
output sink_ready,
// -------------------
// Command Source (Output)
// -------------------
output src_valid,
output reg [98-1 : 0] src_data,
output reg [6-1 : 0] src_channel,
output src_startofpacket,
output src_endofpacket,
input src_ready
);
// -------------------------------------------------------
// Local parameters and variables
// -------------------------------------------------------
localparam PKT_ADDR_H = 56;
localparam PKT_ADDR_L = 36;
localparam PKT_DEST_ID_H = 84;
localparam PKT_DEST_ID_L = 82;
localparam PKT_PROTECTION_H = 88;
localparam PKT_PROTECTION_L = 86;
localparam ST_DATA_W = 98;
localparam ST_CHANNEL_W = 6;
localparam DECODER_TYPE = 0;
localparam PKT_TRANS_WRITE = 59;
localparam PKT_TRANS_READ = 60;
localparam PKT_ADDR_W = PKT_ADDR_H-PKT_ADDR_L + 1;
localparam PKT_DEST_ID_W = PKT_DEST_ID_H-PKT_DEST_ID_L + 1;
// -------------------------------------------------------
// Figure out the number of bits to mask off for each slave span
// during address decoding
// -------------------------------------------------------
localparam PAD0 = log2ceil(64'h20 - 64'h0);
localparam PAD1 = log2ceil(64'h40 - 64'h20);
localparam PAD2 = log2ceil(64'h48 - 64'h40);
localparam PAD3 = log2ceil(64'h80 - 64'h60);
localparam PAD4 = log2ceil(64'h800 - 64'h400);
localparam PAD5 = log2ceil(64'h200000 - 64'h100000);
// -------------------------------------------------------
// Work out which address bits are significant based on the
// address range of the slaves. If the required width is too
// large or too small, we use the address field width instead.
// -------------------------------------------------------
localparam ADDR_RANGE = 64'h200000;
localparam RANGE_ADDR_WIDTH = log2ceil(ADDR_RANGE);
localparam OPTIMIZED_ADDR_H = (RANGE_ADDR_WIDTH > PKT_ADDR_W) ||
(RANGE_ADDR_WIDTH == 0) ?
PKT_ADDR_H :
PKT_ADDR_L + RANGE_ADDR_WIDTH - 1;
localparam RG = RANGE_ADDR_WIDTH-1;
localparam REAL_ADDRESS_RANGE = OPTIMIZED_ADDR_H - PKT_ADDR_L;
reg [PKT_ADDR_W-1 : 0] address;
always @* begin
address = {PKT_ADDR_W{1'b0}};
address [REAL_ADDRESS_RANGE:0] = sink_data[OPTIMIZED_ADDR_H : PKT_ADDR_L];
end
// -------------------------------------------------------
// Pass almost everything through, untouched
// -------------------------------------------------------
assign sink_ready = src_ready;
assign src_valid = sink_valid;
assign src_startofpacket = sink_startofpacket;
assign src_endofpacket = sink_endofpacket;
wire [PKT_DEST_ID_W-1:0] default_destid;
wire [6-1 : 0] default_src_channel;
factory_mm_interconnect_0_router_default_decode the_default_decode(
.default_destination_id (default_destid),
.default_wr_channel (),
.default_rd_channel (),
.default_src_channel (default_src_channel)
);
always @* begin
src_data = sink_data;
src_channel = default_src_channel;
src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = default_destid;
// --------------------------------------------------
// Address Decoder
// Sets the channel and destination ID based on the address
// --------------------------------------------------
// ( 0x0 .. 0x20 )
if ( {address[RG:PAD0],{PAD0{1'b0}}} == 21'h0 ) begin
src_channel = 6'b100000;
src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 5;
end
// ( 0x20 .. 0x40 )
if ( {address[RG:PAD1],{PAD1{1'b0}}} == 21'h20 ) begin
src_channel = 6'b000001;
src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 1;
end
// ( 0x40 .. 0x48 )
if ( {address[RG:PAD2],{PAD2{1'b0}}} == 21'h40 ) begin
src_channel = 6'b001000;
src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 3;
end
// ( 0x60 .. 0x80 )
if ( {address[RG:PAD3],{PAD3{1'b0}}} == 21'h60 ) begin
src_channel = 6'b000010;
src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 2;
end
// ( 0x400 .. 0x800 )
if ( {address[RG:PAD4],{PAD4{1'b0}}} == 21'h400 ) begin
src_channel = 6'b000100;
src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 0;
end
// ( 0x100000 .. 0x200000 )
if ( {address[RG:PAD5],{PAD5{1'b0}}} == 21'h100000 ) begin
src_channel = 6'b010000;
src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 4;
end
end
// --------------------------------------------------
// Ceil(log2()) function
// --------------------------------------------------
function integer log2ceil;
input reg[65:0] val;
reg [65:0] i;
begin
i = 1;
log2ceil = 0;
while (i < val) begin
log2ceil = log2ceil + 1;
i = i << 1;
end
end
endfunction
endmodule |
module factory_mm_interconnect_0_rsp_mux
(
// ----------------------
// Sinks
// ----------------------
input sink0_valid,
input [98-1 : 0] sink0_data,
input [6-1: 0] sink0_channel,
input sink0_startofpacket,
input sink0_endofpacket,
output sink0_ready,
input sink1_valid,
input [98-1 : 0] sink1_data,
input [6-1: 0] sink1_channel,
input sink1_startofpacket,
input sink1_endofpacket,
output sink1_ready,
input sink2_valid,
input [98-1 : 0] sink2_data,
input [6-1: 0] sink2_channel,
input sink2_startofpacket,
input sink2_endofpacket,
output sink2_ready,
input sink3_valid,
input [98-1 : 0] sink3_data,
input [6-1: 0] sink3_channel,
input sink3_startofpacket,
input sink3_endofpacket,
output sink3_ready,
input sink4_valid,
input [98-1 : 0] sink4_data,
input [6-1: 0] sink4_channel,
input sink4_startofpacket,
input sink4_endofpacket,
output sink4_ready,
input sink5_valid,
input [98-1 : 0] sink5_data,
input [6-1: 0] sink5_channel,
input sink5_startofpacket,
input sink5_endofpacket,
output sink5_ready,
// ----------------------
// Source
// ----------------------
output src_valid,
output [98-1 : 0] src_data,
output [6-1 : 0] src_channel,
output src_startofpacket,
output src_endofpacket,
input src_ready,
// ----------------------
// Clock & Reset
// ----------------------
input clk,
input reset
);
localparam PAYLOAD_W = 98 + 6 + 2;
localparam NUM_INPUTS = 6;
localparam SHARE_COUNTER_W = 1;
localparam PIPELINE_ARB = 0;
localparam ST_DATA_W = 98;
localparam ST_CHANNEL_W = 6;
localparam PKT_TRANS_LOCK = 61;
// ------------------------------------------
// Signals
// ------------------------------------------
wire [NUM_INPUTS - 1 : 0] request;
wire [NUM_INPUTS - 1 : 0] valid;
wire [NUM_INPUTS - 1 : 0] grant;
wire [NUM_INPUTS - 1 : 0] next_grant;
reg [NUM_INPUTS - 1 : 0] saved_grant;
reg [PAYLOAD_W - 1 : 0] src_payload;
wire last_cycle;
reg packet_in_progress;
reg update_grant;
wire [PAYLOAD_W - 1 : 0] sink0_payload;
wire [PAYLOAD_W - 1 : 0] sink1_payload;
wire [PAYLOAD_W - 1 : 0] sink2_payload;
wire [PAYLOAD_W - 1 : 0] sink3_payload;
wire [PAYLOAD_W - 1 : 0] sink4_payload;
wire [PAYLOAD_W - 1 : 0] sink5_payload;
assign valid[0] = sink0_valid;
assign valid[1] = sink1_valid;
assign valid[2] = sink2_valid;
assign valid[3] = sink3_valid;
assign valid[4] = sink4_valid;
assign valid[5] = sink5_valid;
// ------------------------------------------
// ------------------------------------------
// Grant Logic & Updates
// ------------------------------------------
// ------------------------------------------
reg [NUM_INPUTS - 1 : 0] lock;
always @* begin
lock[0] = sink0_data[61];
lock[1] = sink1_data[61];
lock[2] = sink2_data[61];
lock[3] = sink3_data[61];
lock[4] = sink4_data[61];
lock[5] = sink5_data[61];
end
assign last_cycle = src_valid & src_ready & src_endofpacket & ~(|(lock & grant));
// ------------------------------------------
// We're working on a packet at any time valid is high, except
// when this is the endofpacket.
// ------------------------------------------
always @(posedge clk or posedge reset) begin
if (reset) begin
packet_in_progress <= 1'b0;
end
else begin
if (last_cycle)
packet_in_progress <= 1'b0;
else if (src_valid)
packet_in_progress <= 1'b1;
end
end
// ------------------------------------------
// Shares
//
// Special case: all-equal shares _should_ be optimized into assigning a
// constant to next_grant_share.
// Special case: all-1's shares _should_ result in the share counter
// being optimized away.
// ------------------------------------------
// Input | arb shares | counter load value
// 0 | 1 | 0
// 1 | 1 | 0
// 2 | 1 | 0
// 3 | 1 | 0
// 4 | 1 | 0
// 5 | 1 | 0
wire [SHARE_COUNTER_W - 1 : 0] share_0 = 1'd0;
wire [SHARE_COUNTER_W - 1 : 0] share_1 = 1'd0;
wire [SHARE_COUNTER_W - 1 : 0] share_2 = 1'd0;
wire [SHARE_COUNTER_W - 1 : 0] share_3 = 1'd0;
wire [SHARE_COUNTER_W - 1 : 0] share_4 = 1'd0;
wire [SHARE_COUNTER_W - 1 : 0] share_5 = 1'd0;
// ------------------------------------------
// Choose the share value corresponding to the grant.
// ------------------------------------------
reg [SHARE_COUNTER_W - 1 : 0] next_grant_share;
always @* begin
next_grant_share =
share_0 & { SHARE_COUNTER_W {next_grant[0]} } |
share_1 & { SHARE_COUNTER_W {next_grant[1]} } |
share_2 & { SHARE_COUNTER_W {next_grant[2]} } |
share_3 & { SHARE_COUNTER_W {next_grant[3]} } |
share_4 & { SHARE_COUNTER_W {next_grant[4]} } |
share_5 & { SHARE_COUNTER_W {next_grant[5]} };
end
// ------------------------------------------
// Flag to indicate first packet of an arb sequence.
// ------------------------------------------
wire grant_changed = ~packet_in_progress && ~(|(saved_grant & valid));
reg first_packet_r;
wire first_packet = grant_changed | first_packet_r;
always @(posedge clk or posedge reset) begin
if (reset) begin
first_packet_r <= 1'b0;
end
else begin
if (update_grant)
first_packet_r <= 1'b1;
else if (last_cycle)
first_packet_r <= 1'b0;
else if (grant_changed)
first_packet_r <= 1'b1;
end
end
// ------------------------------------------
// Compute the next share-count value.
// ------------------------------------------
reg [SHARE_COUNTER_W - 1 : 0] p1_share_count;
reg [SHARE_COUNTER_W - 1 : 0] share_count;
reg share_count_zero_flag;
always @* begin
if (first_packet) begin
p1_share_count = next_grant_share;
end
else begin
// Update the counter, but don't decrement below 0.
p1_share_count = share_count_zero_flag ? '0 : share_count - 1'b1;
end
end
// ------------------------------------------
// Update the share counter and share-counter=zero flag.
// ------------------------------------------
always @(posedge clk or posedge reset) begin
if (reset) begin
share_count <= '0;
share_count_zero_flag <= 1'b1;
end
else begin
if (last_cycle) begin
share_count <= p1_share_count;
share_count_zero_flag <= (p1_share_count == '0);
end
end
end
// ------------------------------------------
// For each input, maintain a final_packet signal which goes active for the
// last packet of a full-share packet sequence. Example: if I have 4
// shares and I'm continuously requesting, final_packet is active in the
// 4th packet.
// ------------------------------------------
wire final_packet_0 = 1'b1;
wire final_packet_1 = 1'b1;
wire final_packet_2 = 1'b1;
wire final_packet_3 = 1'b1;
wire final_packet_4 = 1'b1;
wire final_packet_5 = 1'b1;
// ------------------------------------------
// Concatenate all final_packet signals (wire or reg) into a handy vector.
// ------------------------------------------
wire [NUM_INPUTS - 1 : 0] final_packet = {
final_packet_5,
final_packet_4,
final_packet_3,
final_packet_2,
final_packet_1,
final_packet_0
};
// ------------------------------------------
// ------------------------------------------
wire p1_done = |(final_packet & grant);
// ------------------------------------------
// Flag for the first cycle of packets within an
// arb sequence
// ------------------------------------------
reg first_cycle;
always @(posedge clk, posedge reset) begin
if (reset)
first_cycle <= 0;
else
first_cycle <= last_cycle && ~p1_done;
end
always @* begin
update_grant = 0;
// ------------------------------------------
// No arbitration pipeline, update grant whenever
// the current arb winner has consumed all shares,
// or all requests are low
// ------------------------------------------
update_grant = (last_cycle && p1_done) || (first_cycle && ~(|valid));
update_grant = last_cycle;
end
wire save_grant;
assign save_grant = 1;
assign grant = next_grant;
always @(posedge clk, posedge reset) begin
if (reset)
saved_grant <= '0;
else if (save_grant)
saved_grant <= next_grant;
end
// ------------------------------------------
// ------------------------------------------
// Arbitrator
// ------------------------------------------
// ------------------------------------------
// ------------------------------------------
// Create a request vector that stays high during
// the packet for unpipelined arbitration.
//
// The pipelined arbitration scheme does not require
// request to be held high during the packet.
// ------------------------------------------
assign request = valid;
wire [NUM_INPUTS - 1 : 0] next_grant_from_arb;
altera_merlin_arbitrator
#(
.NUM_REQUESTERS(NUM_INPUTS),
.SCHEME ("no-arb"),
.PIPELINE (0)
) arb (
.clk (clk),
.reset (reset),
.request (request),
.grant (next_grant_from_arb),
.save_top_priority (src_valid),
.increment_top_priority (update_grant)
);
assign next_grant = next_grant_from_arb;
// ------------------------------------------
// ------------------------------------------
// Mux
//
// Implemented as a sum of products.
// ------------------------------------------
// ------------------------------------------
assign sink0_ready = src_ready && grant[0];
assign sink1_ready = src_ready && grant[1];
assign sink2_ready = src_ready && grant[2];
assign sink3_ready = src_ready && grant[3];
assign sink4_ready = src_ready && grant[4];
assign sink5_ready = src_ready && grant[5];
assign src_valid = |(grant & valid);
always @* begin
src_payload =
sink0_payload & {PAYLOAD_W {grant[0]} } |
sink1_payload & {PAYLOAD_W {grant[1]} } |
sink2_payload & {PAYLOAD_W {grant[2]} } |
sink3_payload & {PAYLOAD_W {grant[3]} } |
sink4_payload & {PAYLOAD_W {grant[4]} } |
sink5_payload & {PAYLOAD_W {grant[5]} };
end
// ------------------------------------------
// Mux Payload Mapping
// ------------------------------------------
assign sink0_payload = {sink0_channel,sink0_data,
sink0_startofpacket,sink0_endofpacket};
assign sink1_payload = {sink1_channel,sink1_data,
sink1_startofpacket,sink1_endofpacket};
assign sink2_payload = {sink2_channel,sink2_data,
sink2_startofpacket,sink2_endofpacket};
assign sink3_payload = {sink3_channel,sink3_data,
sink3_startofpacket,sink3_endofpacket};
assign sink4_payload = {sink4_channel,sink4_data,
sink4_startofpacket,sink4_endofpacket};
assign sink5_payload = {sink5_channel,sink5_data,
sink5_startofpacket,sink5_endofpacket};
assign {src_channel,src_data,src_startofpacket,src_endofpacket} = src_payload;
endmodule |
module factory_mm_interconnect_0_router_001_default_decode
#(
parameter DEFAULT_CHANNEL = 0,
DEFAULT_WR_CHANNEL = -1,
DEFAULT_RD_CHANNEL = -1,
DEFAULT_DESTID = 0
)
(output [84 - 82 : 0] default_destination_id,
output [6-1 : 0] default_wr_channel,
output [6-1 : 0] default_rd_channel,
output [6-1 : 0] default_src_channel
);
assign default_destination_id =
DEFAULT_DESTID[84 - 82 : 0];
generate
if (DEFAULT_CHANNEL == -1) begin : no_default_channel_assignment
assign default_src_channel = '0;
end
else begin : default_channel_assignment
assign default_src_channel = 6'b1 << DEFAULT_CHANNEL;
end
endgenerate
generate
if (DEFAULT_RD_CHANNEL == -1) begin : no_default_rw_channel_assignment
assign default_wr_channel = '0;
assign default_rd_channel = '0;
end
else begin : default_rw_channel_assignment
assign default_wr_channel = 6'b1 << DEFAULT_WR_CHANNEL;
assign default_rd_channel = 6'b1 << DEFAULT_RD_CHANNEL;
end
endgenerate
endmodule |
module factory_mm_interconnect_0_router_001
(
// -------------------
// Clock & Reset
// -------------------
input clk,
input reset,
// -------------------
// Command Sink (Input)
// -------------------
input sink_valid,
input [98-1 : 0] sink_data,
input sink_startofpacket,
input sink_endofpacket,
output sink_ready,
// -------------------
// Command Source (Output)
// -------------------
output src_valid,
output reg [98-1 : 0] src_data,
output reg [6-1 : 0] src_channel,
output src_startofpacket,
output src_endofpacket,
input src_ready
);
// -------------------------------------------------------
// Local parameters and variables
// -------------------------------------------------------
localparam PKT_ADDR_H = 56;
localparam PKT_ADDR_L = 36;
localparam PKT_DEST_ID_H = 84;
localparam PKT_DEST_ID_L = 82;
localparam PKT_PROTECTION_H = 88;
localparam PKT_PROTECTION_L = 86;
localparam ST_DATA_W = 98;
localparam ST_CHANNEL_W = 6;
localparam DECODER_TYPE = 1;
localparam PKT_TRANS_WRITE = 59;
localparam PKT_TRANS_READ = 60;
localparam PKT_ADDR_W = PKT_ADDR_H-PKT_ADDR_L + 1;
localparam PKT_DEST_ID_W = PKT_DEST_ID_H-PKT_DEST_ID_L + 1;
// -------------------------------------------------------
// Figure out the number of bits to mask off for each slave span
// during address decoding
// -------------------------------------------------------
// -------------------------------------------------------
// Work out which address bits are significant based on the
// address range of the slaves. If the required width is too
// large or too small, we use the address field width instead.
// -------------------------------------------------------
localparam ADDR_RANGE = 64'h0;
localparam RANGE_ADDR_WIDTH = log2ceil(ADDR_RANGE);
localparam OPTIMIZED_ADDR_H = (RANGE_ADDR_WIDTH > PKT_ADDR_W) ||
(RANGE_ADDR_WIDTH == 0) ?
PKT_ADDR_H :
PKT_ADDR_L + RANGE_ADDR_WIDTH - 1;
localparam RG = RANGE_ADDR_WIDTH;
localparam REAL_ADDRESS_RANGE = OPTIMIZED_ADDR_H - PKT_ADDR_L;
reg [PKT_DEST_ID_W-1 : 0] destid;
// -------------------------------------------------------
// Pass almost everything through, untouched
// -------------------------------------------------------
assign sink_ready = src_ready;
assign src_valid = sink_valid;
assign src_startofpacket = sink_startofpacket;
assign src_endofpacket = sink_endofpacket;
wire [6-1 : 0] default_src_channel;
factory_mm_interconnect_0_router_001_default_decode the_default_decode(
.default_destination_id (),
.default_wr_channel (),
.default_rd_channel (),
.default_src_channel (default_src_channel)
);
always @* begin
src_data = sink_data;
src_channel = default_src_channel;
// --------------------------------------------------
// DestinationID Decoder
// Sets the channel based on the destination ID.
// --------------------------------------------------
destid = sink_data[PKT_DEST_ID_H : PKT_DEST_ID_L];
if (destid == 0 ) begin
src_channel = 6'b1;
end
end
// --------------------------------------------------
// Ceil(log2()) function
// --------------------------------------------------
function integer log2ceil;
input reg[65:0] val;
reg [65:0] i;
begin
i = 1;
log2ceil = 0;
while (i < val) begin
log2ceil = log2ceil + 1;
i = i << 1;
end
end
endfunction
endmodule |
module AXILITE #
(
parameter C_S00_BASEADDR = 0,
// Parameters of Axi Slave Bus Interface S00_AXI
parameter C_S00_AXI_DATA_WIDTH = 32,
parameter C_S00_AXI_ADDR_WIDTH = 32
)
(
// Ports of Axi Slave Bus Interface S00_AXI
input wire s00_axi_aclk,
input wire s00_axi_aresetn,
input wire [C_S00_AXI_ADDR_WIDTH-1 : 0] s00_axi_awaddr,
input wire s00_axi_awvalid,
output wire s00_axi_awready,
input wire [C_S00_AXI_DATA_WIDTH-1 : 0] s00_axi_wdata,
input wire s00_axi_wvalid,
output wire s00_axi_wready,
output wire [1 : 0] s00_axi_bresp,
output wire s00_axi_bvalid,
input wire s00_axi_bready,
input wire [C_S00_AXI_ADDR_WIDTH-1 : 0] s00_axi_araddr,
input wire s00_axi_arvalid,
output wire s00_axi_arready,
output wire [C_S00_AXI_DATA_WIDTH-1 : 0] s00_axi_rdata,
output wire [1 : 0] s00_axi_rresp,
output wire s00_axi_rvalid,
input wire s00_axi_rready
);
// Instantiation of Axi Bus Interface S00_AXI
AXILITE_S00 # (
.C_S_AXI_DATA_WIDTH(C_S00_AXI_DATA_WIDTH),
.C_S_AXI_BASEADDR(C_S00_BASEADDR),
.C_S_AXI_ADDR_WIDTH(C_S00_AXI_ADDR_WIDTH)
) AXILITE_S00_inst (
.S_AXI_ACLK(s00_axi_aclk),
.S_AXI_ARESETN(s00_axi_aresetn),
.S_AXI_AWADDR(s00_axi_awaddr),
.S_AXI_AWVALID(s00_axi_awvalid),
.S_AXI_AWREADY(s00_axi_awready),
.S_AXI_WDATA(s00_axi_wdata),
.S_AXI_WVALID(s00_axi_wvalid),
.S_AXI_WREADY(s00_axi_wready),
.S_AXI_BRESP(s00_axi_bresp),
.S_AXI_BVALID(s00_axi_bvalid),
.S_AXI_BREADY(s00_axi_bready),
.S_AXI_ARADDR(s00_axi_araddr),
.S_AXI_ARVALID(s00_axi_arvalid),
.S_AXI_ARREADY(s00_axi_arready),
.S_AXI_RDATA(s00_axi_rdata),
.S_AXI_RRESP(s00_axi_rresp),
.S_AXI_RVALID(s00_axi_rvalid),
.S_AXI_RREADY(s00_axi_rready)
);
endmodule |
module button_debouncer
#(parameter CNT_WIDTH = 16)
( input clk,
input reset,
input key,
output reg key_state_o,
output reg key_down_o,
output reg key_up_o
);
// Синхронизируем вход с текущим тактовым доменом.
reg [1:0] key_reg;
always @ (posedge clk)
begin
if (reset)
key_reg <= 2'b00;
else
key_reg <= {key_reg[0], ~key};
end
reg [CNT_WIDTH - 1:0] key_count;
wire key_change_f = (key_state_o != key_reg[1]);
wire key_cnt_max = &key_count;
always @(posedge clk)
begin
if (reset)
begin
key_count <= 0;
key_state_o <= 0;
end
else if(key_change_f)
begin
key_count <= key_count + 'd1;
if(key_cnt_max)
key_state_o <= ~key_state_o;
end
else
key_count <= 0;
end
always @(posedge clk)
begin
key_down_o <= key_change_f & key_cnt_max & ~key_state_o;
key_up_o <= key_change_f & key_cnt_max & key_state_o;
end
endmodule |
module sys_array_cell
#(parameter DATA_WIDTH = 8)
( input clk,
input reset_n,
input param_load,
input signed [DATA_WIDTH - 1:0] input_data,
input signed [2 * DATA_WIDTH - 1:0] prop_data,
input signed [DATA_WIDTH - 1:0] param_data,
output reg signed [2 * DATA_WIDTH - 1:0] out_data,
output reg signed [DATA_WIDTH - 1:0] prop_param
);
reg signed [DATA_WIDTH - 1:0] par;
always @(posedge clk)
begin
if (~reset_n) begin // Сброс
out_data <= {2 * DATA_WIDTH{1'b0}};
par <= {DATA_WIDTH{1'b0}};
end
else if (param_load) begin // Загрузка параметра
par <= param_data;
end
else begin // Вычисление данных
// Задание 1. Реализуйте основные вычисления модуля.
end
end
endmodule |
module seven_segment_4_digits
(
input clock,
input reset,
input [15:0] number,
output reg [ 7:0] abcdefgh,
output reg [ 3:0] digit
);
function [7:0] bcd_to_seg (input [3:0] bcd);
case (bcd)
'h0: bcd_to_seg = 'b11000000;
'h1: bcd_to_seg = 'b11111001;
'h2: bcd_to_seg = 'b10100100;
'h3: bcd_to_seg = 'b10110000;
'h4: bcd_to_seg = 'b10011001;
'h5: bcd_to_seg = 'b10010010;
'h6: bcd_to_seg = 'b10000010;
'h7: bcd_to_seg = 'b11111000;
'h8: bcd_to_seg = 'b10000000;
'h9: bcd_to_seg = 'b10010000;
'ha: bcd_to_seg = 'b10001000;
'hb: bcd_to_seg = 'b10000011;
'hc: bcd_to_seg = 'b11000110;
'hd: bcd_to_seg = 'b10100001;
'he: bcd_to_seg = 'b10000110;
'hf: bcd_to_seg = 'b10001110;
endcase
endfunction
reg [15:0] cnt;
always @ (posedge clock)
if (reset)
cnt <= 16'd0;
else
cnt <= cnt + 16'd1;
reg [1:0] i;
always @ (posedge clock)
begin
if (reset)
begin
abcdefgh <= bcd_to_seg(0);
digit <= ~ 4'b1;
i <= 0;
end
else if (cnt == 16'b0)
begin
abcdefgh <= bcd_to_seg(number [i * 4 +: 4]);
digit <= ~ (4'b1 << i);
i <= i + 1;
end
end
endmodule |
module read_data
#(parameter DATA_WIDTH=8)(
input clk,
input reset_n,
input change,
output [2:0] code,
output [DATA_WIDTH-1:0] inp,
output [DATA_WIDTH-1:0] par,
output [2*DATA_WIDTH-1:0] prop,
output [2*DATA_WIDTH-1:0] result
);
reg [0:7] [DATA_WIDTH-1:0] data_inp;
reg [0:7] [DATA_WIDTH-1:0] data_param;
reg [0:7] [2*DATA_WIDTH-1:0] data_prop;
reg [0:7] [2*DATA_WIDTH-1:0] data_result;
reg [2:0] code_b;
always @(posedge clk)
begin
if (~reset_n)
begin
code_b = 'd0;
// Индексация 0 1 2 3 4 5 6 7
data_inp = {8'hf1, 8'hf7, 8'hc8, 8'h4c, 8'h50, 8'hd9, 8'h32, 8'h85};
data_param = {8'hc8, 8'h6d, 8'h83, 8'hd1, 8'hd7, 8'h4b, 8'h17, 8'h82};
// Индексация 0 1 2 3 4 5 6 7
data_prop = {16'h001b, 16'h0031, 16'h00de, 16'h0032, 16'h00b9, 16'h0057, 16'h00d7, 16'h00e6};
data_result = {16'hbc63, 16'h695c, 16'h6736, 16'h3e3e, 16'h43e9, 16'h3fea, 16'h0555, 16'h4470};
end
else
if (change)
code_b = code_b + 1;
end
assign inp = data_inp[code_b];
assign par = data_param[code_b];
assign prop = data_prop[code_b];
assign result = data_result[code_b];
// Для RZRD
assign code = ~{code_b[0], code_b[1], code_b[2]};
// Для omdazz
//assign code = ~code_b;
endmodule |
module shift_reg
#(parameter DATA_WIDTH=8,
parameter LENGTH=4)
(
input clk,
input reset_n,
input [1:0] ctrl_code,
input [0:LENGTH-1] [DATA_WIDTH-1:0] data_in,
input [DATA_WIDTH-1:0] data_write,
output reg [DATA_WIDTH-1:0] data_read,
output reg [0:LENGTH-1] [DATA_WIDTH-1:0] data_out
);
localparam REG_UPLOAD = 0,
REG_LOAD = 1,
REG_WRITE = 2,
REG_READ = 3;
reg en;
reg [0:LENGTH - 1] [DATA_WIDTH - 1:0] contents;
integer i;
always @(posedge clk)
begin
if (~reset_n)
begin
for(i = 0; i < LENGTH; i = i + 1) begin : for_reset_n
contents[i] <= {DATA_WIDTH{1'b0}};
end
en <= 1'b1;
end
else
begin
if (en)
begin
case (ctrl_code)
REG_UPLOAD: data_out <= contents;
REG_LOAD: contents <= data_in;
REG_READ:
begin
data_read <= contents[0];
for (i = 0; i < LENGTH - 1; i = i + 1) begin : for_REG_READ
contents[i] <= contents[i+1];
end
contents[LENGTH-1] <= contents[0];
end
REG_WRITE:
begin
for (i = 0; i < LENGTH - 1; i = i + 1) begin : for_REG_WRITE
contents[i] <= contents[i+1];
end
contents[LENGTH-1] <= data_write;
end
endcase
end
end
end
endmodule |
module sys_array_fetcher
#( parameter DATA_WIDTH = 8,
parameter ARRAY_W_W = 2, //Строк в массиве весов
parameter ARRAY_W_L = 5, //Столбцов в массиве весов
parameter ARRAY_A_W = 5, //Строк в массиве данных
parameter ARRAY_A_L = 2) //Столбцов в массиве данных
( input clk,
input reset_n,
input load_params,
input start_comp,
input [0:ARRAY_A_W - 1] [0:ARRAY_A_L - 1] [DATA_WIDTH - 1:0] input_data_b,
input [0:ARRAY_W_W - 1] [0:ARRAY_W_L - 1] [DATA_WIDTH - 1:0] input_data_w,
output reg ready,
output reg [0:ARRAY_W_W - 1] [0:ARRAY_A_L - 1] [2 * DATA_WIDTH - 1:0] out_data
);
// Необходимое количество циклов clk для выполнения выборки и возврата результатов
localparam FETCH_LENGTH = ARRAY_A_L + ARRAY_A_W + ARRAY_W_W + 1;
reg [15:0] cnt; // Счетчик
reg [ARRAY_A_W-1:0] [1:0] control_sr_read; // Контрольные сигналы регистра чтения
reg [ARRAY_W_W-1:0] [1:0] control_sr_write; // Контрольные сигналы регистра записи
wire [0:ARRAY_A_W-1] [DATA_WIDTH-1:0] input_sys_array;
wire [0:ARRAY_A_W-1] [DATA_WIDTH-1:0] empty_wire_reads;
wire [0:ARRAY_A_W-1] [0:ARRAY_A_L-1] [DATA_WIDTH-1:0] empty_wire2_reads;
wire [0:ARRAY_W_W-1] [0:ARRAY_A_L-1] [2*DATA_WIDTH-1:0] empty_wire_writes;
wire [0:ARRAY_W_W-1] [2*DATA_WIDTH-1:0] empty_wire2_writes;
wire [0:ARRAY_W_W-1] [2*DATA_WIDTH-1:0] output_sys_array;
wire [0:ARRAY_W_W - 1] [0:ARRAY_A_L - 1] [2 * DATA_WIDTH - 1:0] output_wire;
genvar i,j;
generate
for (i=0;i<ARRAY_A_W; i=i+1) begin: generate_reads_shift_reg
shift_reg #(.DATA_WIDTH(DATA_WIDTH), .LENGTH(ARRAY_A_L)) reads
( .clk(clk),
.reset_n(reset_n),
.ctrl_code(control_sr_read[i]),
.data_in(input_data_b[i]),
.data_write(empty_wire_reads[i]),
.data_read(input_sys_array[i]),
.data_out(empty_wire2_reads[i])
);
end
endgenerate
generate
for (i=0;i<ARRAY_W_W;i=i+1) begin: generate_writes_shift_reg
shift_reg #(.DATA_WIDTH(2*DATA_WIDTH), .LENGTH(ARRAY_A_L)) writes
( .clk(clk),
.reset_n(reset_n),
.ctrl_code(control_sr_write[i]),
.data_in(empty_wire_writes[i]),
.data_write(output_sys_array[i]),
.data_read(empty_wire2_writes[i]),
.data_out(output_wire[i])
);
end
endgenerate
sys_array_basic #(.DATA_WIDTH(DATA_WIDTH),
.ARRAY_W_W(ARRAY_W_W), .ARRAY_W_L(ARRAY_W_L),
.ARRAY_A_W(ARRAY_A_W), .ARRAY_A_L(ARRAY_A_L))
systolic_array
(
.clk(clk),
.reset_n(reset_n),
.weights_load(load_params),
.weight_data(input_data_w),
.input_data(input_sys_array),
.output_data(output_sys_array)
);
always @(posedge clk)
begin
if (~reset_n) begin // Сброс
cnt <= 15'd0;
control_sr_read <= {ARRAY_A_W * 2{1'b0}};
control_sr_write <= {ARRAY_W_W * 2{1'b0}};
out_data <= 'b0;
ready <= 1'b0;
end
else if(start_comp) begin // Начало вычислений
cnt <= 15'd1;
control_sr_read <= {ARRAY_A_W{2'b01}}; //initiate loading read registers
end
else
if (cnt > 0) begin // Основные вычисления
if (cnt == 1) begin // Задание сигналова на первом такте вычислений
control_sr_read[ARRAY_A_W - 1:1] <= {2 * (ARRAY_A_W - 1){1'b0}};
control_sr_read[0] <= 2'b11;
cnt <= cnt + 1'b1; end
else
begin // Задание логических сигналов
if (cnt < ARRAY_W_L + 1) // Включение регистров чтения
control_sr_read[cnt-1] <= 2'b11;
if ((cnt > ARRAY_A_L) && (cnt < ARRAY_A_L + ARRAY_W_L + 1)) // Старт отключения регистров чтения
control_sr_read[cnt - ARRAY_A_L - 1] <= 2'b00;
if ((cnt > ARRAY_W_L + 1) && (cnt < ARRAY_W_L + ARRAY_W_W + 2)) // Включение регистров записи
control_sr_write[cnt - ARRAY_W_L - 2] <= 2'b10;
if ((cnt > ARRAY_W_L + ARRAY_A_L + 1) && (cnt <= FETCH_LENGTH)) // Старт отключения регистров записи
control_sr_write[cnt - (ARRAY_W_L + ARRAY_A_L) - 2] <= 2'b00;
if (cnt <= FETCH_LENGTH+1)
cnt <= cnt + 1'b1;
else begin // Выдача итогового результата
cnt <= 15'd0;
out_data <= output_wire;
ready <= 1'b1;
end
end
end
end
endmodule |
module sys_array_basic
#(
parameter DATA_WIDTH = 8,
parameter ARRAY_W_W = 4, //Строк в массиве весов
parameter ARRAY_W_L = 4, //Столбцов в массиве весов
parameter ARRAY_A_W = 4, //Строк в массиве данных
parameter ARRAY_A_L = 4) //Столбцов в массиве данных
( input clk,
input reset_n,
input weights_load,
input [0:ARRAY_A_W-1] [DATA_WIDTH-1:0] input_data,
input [0:ARRAY_W_W-1] [0:ARRAY_W_L-1] [DATA_WIDTH-1:0] weight_data,
output [0:ARRAY_W_W-1] [2*DATA_WIDTH-1:0] output_data
);
wire [0:ARRAY_W_W-1] [0:ARRAY_W_L-1] [2*DATA_WIDTH-1:0] temp_output_data;
wire [0:ARRAY_W_W-1] [0:ARRAY_W_L-1] [DATA_WIDTH-1:0] propagate_module;
genvar i;
genvar j;
genvar t;
// Генерация массива вычислительных ячеек
// Задание 2. Допишите необходимые входные и выходные сигналы.
generate
for(i = 0; i < ARRAY_W_W; i = i + 1) begin : generate_array_proc
for (j = 0; j < ARRAY_W_L; j = j + 1) begin : generate_array_proc2
if ((i == 0) && (j == 0)) // i - строка, j - столбец
begin
sys_array_cell #(.DATA_WIDTH(DATA_WIDTH)) cell_inst (
.clk(clk),
.reset_n(reset_n),
.param_load(weights_load),
.input_data(input_data[0]),
.prop_data({2*DATA_WIDTH{1'b0}}),
.param_data(weight_data[0][0]),
.out_data(temp_output_data[0][0]),
.prop_param(propagate_module[0][0])
);
end
else if (i == 0) // Первая строка
begin
sys_array_cell #(.DATA_WIDTH(DATA_WIDTH)) cell_inst (
.clk(),
.reset_n(),
.param_load(),
.input_data(),
.prop_data(),
.param_data(),
.out_data(),
.prop_param()
);
end
else if (j == 0) // Первый столбец
begin
sys_array_cell #(.DATA_WIDTH(DATA_WIDTH)) cell_inst (
.clk(),
.reset_n(),
.param_load(),
.input_data(),
.prop_data(),
.param_data(),
.out_data(),
.prop_param()
);
end
else
begin // Остальные элементы
sys_array_cell #(.DATA_WIDTH(DATA_WIDTH)) cell_inst (
.clk(),
.reset_n(),
.param_load(),
.input_data(),
.prop_data(),
.param_data(),
.out_data(),
.prop_param()
);
end
end
end
endgenerate
// Генерация связей для выходных данных
generate
for (t=0;t<ARRAY_W_W;t=t+1) begin: output_prop
assign output_data[t] = temp_output_data[t][ARRAY_W_L-1];
end
endgenerate
endmodule |
module upsizing
# (
parameter n = 5, nb = n * 8
)
(
input wire aclk,
input wire aresetn,
input wire [nb - 1:0] in_tdata,
input wire in_tvalid,
output wire in_tready,
output wire [nb*2- 1:0] out_tdata,
output wire out_tvalid,
input wire out_tready
);
logic flag_hf;
logic [nb-1:0] reg_hf;
always @(posedge aclk)
if( ~aresetn )
flag_hf <= #1 '0;
else if( in_tvalid & in_tready )
flag_hf <= #1 ~flag_hf;
always @(posedge aclk)
if( in_tvalid & in_tready & ~flag_hf )
reg_hf <= #1 in_tdata;
assign out_tdata = { reg_hf, in_tdata };
assign in_tready = ~flag_hf | out_tready;
assign out_tvalid = flag_hf & in_tvalid;
endmodule |
module downsizing
# (
parameter n = 5, nb = n * 8
)
(
input wire aclk,
input wire aresetn,
input wire [nb*2 - 1:0] in_tdata,
input wire in_tvalid,
output wire in_tready,
output wire [nb - 1:0] out_tdata,
output wire out_tvalid,
input wire out_tready
);
logic flag_hf;
always @(posedge aclk)
if( ~aresetn )
flag_hf <= #1 '0;
else if( out_tvalid & out_tready )
flag_hf <= #1 ~flag_hf;
assign out_tdata = (flag_hf) ? in_tdata[0+:nb] : in_tdata[nb+:nb];
assign in_tready = flag_hf & out_tready;
assign out_tvalid = in_tvalid;
endmodule |
module top(
input wire aclk,
input wire aresetn,
input wire [255:0] in_tdata,
input wire in_tvalid,
output wire in_tready,
output wire [255:0] out_tdata,
output wire out_tvalid,
input wire out_tready
);
logic [255:0] c0_tdata;
logic c0_tvalid;
logic c0_tready;
logic [511:0] c1_tdata;
logic c1_tvalid;
logic c1_tready;
logic [255:0] c2_tdata;
logic c2_tvalid;
logic c2_tready;
logic [511:0] c3_tdata;
logic c3_tvalid;
logic c3_tready;
logic [255:0] c4_tdata;
logic c4_tvalid;
logic c4_tready;
logic [511:0] c1s_tdata;
logic c1s_tvalid;
logic c1s_tready;
logic [255:0] c2s_tdata;
logic c2s_tvalid;
logic c2s_tready;
logic [511:0] c3s_tdata;
logic c3s_tvalid;
logic c3s_tready;
axis_register_slice_32 reg_i (
.aclk ( aclk ),
.aresetn ( aresetn ),
.s_axis_tvalid ( in_tvalid ),
.s_axis_tready ( in_tready ),
.s_axis_tdata ( in_tdata ),
.m_axis_tvalid ( c0_tvalid ),
.m_axis_tready ( c0_tready ),
.m_axis_tdata ( c0_tdata )
);
upsizing
#(
.n ( 32 )
)
upsizing_0
(
.aclk ( aclk ),
.aresetn ( aresetn ),
.in_tdata ( c0_tdata ),
.in_tvalid ( c0_tvalid ),
.in_tready ( c0_tready ),
.out_tdata ( c1_tdata ),
.out_tvalid ( c1_tvalid ),
.out_tready ( c1_tready )
);
skid_crd
#(
.n ( 64 )
)
skid_0
(
.aclk ( aclk ),
.aresetn ( aresetn ),
.in_tdata ( c1_tdata ),
.in_tvalid ( c1_tvalid ),
.in_tready ( c1_tready ),
.out_tdata ( c1s_tdata ),
.out_tvalid ( c1s_tvalid ),
.out_tready ( c1s_tready )
);
downsizing
#(
.n ( 32 )
)
downsizing_0
(
.aclk ( aclk ),
.aresetn ( aresetn ),
.in_tdata ( c1s_tdata ),
.in_tvalid ( c1s_tvalid ),
.in_tready ( c1s_tready ),
.out_tdata ( c2_tdata ),
.out_tvalid ( c2_tvalid ),
.out_tready ( c2_tready )
);
skid_crd
#(
.n ( 32 )
)
skid_1
(
.aclk ( aclk ),
.aresetn ( aresetn ),
.in_tdata ( c2_tdata ),
.in_tvalid ( c2_tvalid ),
.in_tready ( c2_tready ),
.out_tdata ( c2s_tdata ),
.out_tvalid ( c2s_tvalid ),
.out_tready ( c2s_tready )
);
upsizing
#(
.n ( 32 )
)
upsizing_1
(
.aclk ( aclk ),
.aresetn ( aresetn ),
.in_tdata ( c2s_tdata ),
.in_tvalid ( c2s_tvalid ),
.in_tready ( c2s_tready ),
.out_tdata ( c3_tdata ),
.out_tvalid ( c3_tvalid ),
.out_tready ( c3_tready )
);
skid_crd
#(
.n ( 64 )
)
skid_2
(
.aclk ( aclk ),
.aresetn ( aresetn ),
.in_tdata ( c3_tdata ),
.in_tvalid ( c3_tvalid ),
.in_tready ( c3_tready ),
.out_tdata ( c3s_tdata ),
.out_tvalid ( c3s_tvalid ),
.out_tready ( c3s_tready )
);
downsizing
#(
.n ( 32 )
)
downsizing_1
(
.aclk ( aclk ),
.aresetn ( aresetn ),
.in_tdata ( c3s_tdata ),
.in_tvalid ( c3s_tvalid ),
.in_tready ( c3s_tready ),
.out_tdata ( c4_tdata ),
.out_tvalid ( c4_tvalid ),
.out_tready ( c4_tready )
);
axis_register_slice_32 reg_0 (
.aclk ( aclk ),
.aresetn ( aresetn ),
.s_axis_tvalid ( c4_tvalid ),
.s_axis_tready ( c4_tready ),
.s_axis_tdata ( c4_tdata ),
.m_axis_tvalid ( out_tvalid ),
.m_axis_tready ( out_tready ),
.m_axis_tdata ( out_tdata )
);
endmodule |
module top(
input wire aclk,
input wire aresetn,
input wire [255:0] in_tdata,
input wire in_tvalid,
output wire in_tready,
output wire [255:0] out_tdata,
output wire out_tvalid,
input wire out_tready
);
logic [255:0] c0_tdata;
logic c0_tvalid;
logic c0_tready;
logic [511:0] c1_tdata;
logic c1_tvalid;
logic c1_tready;
logic [255:0] c2_tdata;
logic c2_tvalid;
logic c2_tready;
logic [511:0] c3_tdata;
logic c3_tvalid;
logic c3_tready;
logic [255:0] c4_tdata;
logic c4_tvalid;
logic c4_tready;
logic [511:0] c1s_tdata;
logic c1s_tvalid;
logic c1s_tready;
logic [255:0] c2s_tdata;
logic c2s_tvalid;
logic c2s_tready;
logic [511:0] c3s_tdata;
logic c3s_tvalid;
logic c3s_tready;
axis_register_slice_32 reg_i (
.aclk ( aclk ),
.aresetn ( aresetn ),
.s_axis_tvalid ( in_tvalid ),
.s_axis_tready ( in_tready ),
.s_axis_tdata ( in_tdata ),
.m_axis_tvalid ( c0_tvalid ),
.m_axis_tready ( c0_tready ),
.m_axis_tdata ( c0_tdata )
);
upsizing
#(
.n ( 32 )
)
upsizing_0
(
.aclk ( aclk ),
.aresetn ( aresetn ),
.in_tdata ( c0_tdata ),
.in_tvalid ( c0_tvalid ),
.in_tready ( c0_tready ),
.out_tdata ( c1_tdata ),
.out_tvalid ( c1_tvalid ),
.out_tready ( c1_tready )
);
double_buffer_wrp
#(
.n ( 64 )
)
skid_0
(
.aclk ( aclk ),
.aresetn ( aresetn ),
.in_tdata ( c1_tdata ),
.in_tvalid ( c1_tvalid ),
.in_tready ( c1_tready ),
.out_tdata ( c1s_tdata ),
.out_tvalid ( c1s_tvalid ),
.out_tready ( c1s_tready )
);
downsizing
#(
.n ( 32 )
)
downsizing_0
(
.aclk ( aclk ),
.aresetn ( aresetn ),
.in_tdata ( c1s_tdata ),
.in_tvalid ( c1s_tvalid ),
.in_tready ( c1s_tready ),
.out_tdata ( c2_tdata ),
.out_tvalid ( c2_tvalid ),
.out_tready ( c2_tready )
);
double_buffer_wrp
#(
.n ( 32 )
)
skid_1
(
.aclk ( aclk ),
.aresetn ( aresetn ),
.in_tdata ( c2_tdata ),
.in_tvalid ( c2_tvalid ),
.in_tready ( c2_tready ),
.out_tdata ( c2s_tdata ),
.out_tvalid ( c2s_tvalid ),
.out_tready ( c2s_tready )
);
upsizing
#(
.n ( 32 )
)
upsizing_1
(
.aclk ( aclk ),
.aresetn ( aresetn ),
.in_tdata ( c2s_tdata ),
.in_tvalid ( c2s_tvalid ),
.in_tready ( c2s_tready ),
.out_tdata ( c3_tdata ),
.out_tvalid ( c3_tvalid ),
.out_tready ( c3_tready )
);
double_buffer_wrp
#(
.n ( 64 )
)
skid_2
(
.aclk ( aclk ),
.aresetn ( aresetn ),
.in_tdata ( c3_tdata ),
.in_tvalid ( c3_tvalid ),
.in_tready ( c3_tready ),
.out_tdata ( c3s_tdata ),
.out_tvalid ( c3s_tvalid ),
.out_tready ( c3s_tready )
);
downsizing
#(
.n ( 32 )
)
downsizing_1
(
.aclk ( aclk ),
.aresetn ( aresetn ),
.in_tdata ( c3s_tdata ),
.in_tvalid ( c3s_tvalid ),
.in_tready ( c3s_tready ),
.out_tdata ( c4_tdata ),
.out_tvalid ( c4_tvalid ),
.out_tready ( c4_tready )
);
axis_register_slice_32 reg_0 (
.aclk ( aclk ),
.aresetn ( aresetn ),
.s_axis_tvalid ( c4_tvalid ),
.s_axis_tready ( c4_tready ),
.s_axis_tdata ( c4_tdata ),
.m_axis_tvalid ( out_tvalid ),
.m_axis_tready ( out_tready ),
.m_axis_tdata ( out_tdata )
);
endmodule |
module user();
endmodule |
module fifo_w8
#(
parameter WIDTH = 16
)
(
input wire reset_p, //! 1 - reset
input wire clk, //! clock
input wire [WIDTH-1:0] data_i,
input wire data_we,
output wire [WIDTH-1:0] data_o,
input wire data_rd,
output wire full,
output wire empty
);
logic [WIDTH-1:0] mem[8];
logic [3:0] cnt_wr;
logic [3:0] cnt_rd;
logic rstp;
always @(posedge clk) begin
rstp <= #1 reset_p;
if( ~full & data_we ) begin
mem[cnt_wr[2:0]] <= #1 data_i;
cnt_wr <= #1 cnt_wr + 1;
end
if( ~empty & data_rd ) begin
cnt_rd <= #1 cnt_rd + 1;
end
if( rstp ) begin
cnt_wr <= # 2'b0000;
cnt_rd <= # 2'b0000;
end
end
//assign full = (cnt_wr_next==cnt_rd) ? 1 : 0;
assign full = (cnt_rd[2:0]==cnt_wr[2:0] && cnt_rd[3]!=cnt_wr[3]) ? 1 : 0;
assign empty = (cnt_wr==cnt_rd) ? 1 : 0;
assign data_o = mem[cnt_rd[2:0]];
endmodule |
module user_axis
# (
parameter n = 5, //! Number of bytes
parameter nb = n * 8 //! Number of bits
)
(
input wire clk, //! clok
input wire reset_n, //! 0 - reset
input wire [nb*2 - 1:0] in_tdata, //! input data
input wire in_tvalid, //! 1 - input data is valid
output wire in_tready, //! 1 - ready for get data
output wire [nb - 1:0] out_tdata, //! output data
output wire out_tvalid, //! 1 - output data is valid
input wire out_tready //! 1 - ready for get data
);
assign out_tdata = in_tdata;
assign out_tvalid = in_tvalid & reset_n;
assign in_tready = out_tready & reset_n;
endmodule |
module top(
input wire aclk,
input wire aresetn,
input wire [255:0] in_tdata,
input wire in_tvalid,
output wire in_tready,
output wire [255:0] out_tdata,
output wire out_tvalid,
input wire out_tready
);
logic [255:0] c0_tdata;
logic c0_tvalid;
logic c0_tready;
logic [511:0] c1_tdata;
logic c1_tvalid;
logic c1_tready;
logic [255:0] c2_tdata;
logic c2_tvalid;
logic c2_tready;
logic [511:0] c3_tdata;
logic c3_tvalid;
logic c3_tready;
logic [255:0] c4_tdata;
logic c4_tvalid;
logic c4_tready;
axis_register_slice_32 reg_i (
.aclk ( aclk ),
.aresetn ( aresetn ),
.s_axis_tvalid ( in_tvalid ),
.s_axis_tready ( in_tready ),
.s_axis_tdata ( in_tdata ),
.m_axis_tvalid ( c0_tvalid ),
.m_axis_tready ( c0_tready ),
.m_axis_tdata ( c0_tdata )
);
upsizing
#(
.n ( 32 )
)
upsizing_0
(
.aclk ( aclk ),
.aresetn ( aresetn ),
.in_tdata ( c0_tdata ),
.in_tvalid ( c0_tvalid ),
.in_tready ( c0_tready ),
.out_tdata ( c1_tdata ),
.out_tvalid ( c1_tvalid ),
.out_tready ( c1_tready )
);
downsizing
#(
.n ( 32 )
)
downsizing_0
(
.aclk ( aclk ),
.aresetn ( aresetn ),
.in_tdata ( c1_tdata ),
.in_tvalid ( c1_tvalid ),
.in_tready ( c1_tready ),
.out_tdata ( c2_tdata ),
.out_tvalid ( c2_tvalid ),
.out_tready ( c2_tready )
);
upsizing
#(
.n ( 32 )
)
upsizing_1
(
.aclk ( aclk ),
.aresetn ( aresetn ),
.in_tdata ( c2_tdata ),
.in_tvalid ( c2_tvalid ),
.in_tready ( c2_tready ),
.out_tdata ( c3_tdata ),
.out_tvalid ( c3_tvalid ),
.out_tready ( c3_tready )
);
downsizing
#(
.n ( 32 )
)
downsizing_1
(
.aclk ( aclk ),
.aresetn ( aresetn ),
.in_tdata ( c3_tdata ),
.in_tvalid ( c3_tvalid ),
.in_tready ( c3_tready ),
.out_tdata ( c4_tdata ),
.out_tvalid ( c4_tvalid ),
.out_tready ( c4_tready )
);
axis_register_slice_32 reg_0 (
.aclk ( aclk ),
.aresetn ( aresetn ),
.s_axis_tvalid ( c4_tvalid ),
.s_axis_tready ( c4_tready ),
.s_axis_tdata ( c4_tdata ),
.m_axis_tvalid ( out_tvalid ),
.m_axis_tready ( out_tready ),
.m_axis_tdata ( out_tdata )
);
endmodule |
module top(
input wire aclk,
input wire aresetn,
input wire [255:0] in_tdata,
input wire in_tvalid,
output wire in_tready,
output wire [255:0] out_tdata,
output wire out_tvalid,
input wire out_tready
);
logic [255:0] c0_tdata;
logic c0_tvalid;
logic c0_tready;
logic [511:0] c1_tdata;
logic c1_tvalid;
logic c1_tready;
logic [255:0] c2_tdata;
logic c2_tvalid;
logic c2_tready;
logic [511:0] c3_tdata;
logic c3_tvalid;
logic c3_tready;
logic [255:0] c4_tdata;
logic c4_tvalid;
logic c4_tready;
logic [511:0] c1s_tdata;
logic c1s_tvalid;
logic c1s_tready;
logic [255:0] c2s_tdata;
logic c2s_tvalid;
logic c2s_tready;
logic [511:0] c3s_tdata;
logic c3s_tvalid;
logic c3s_tready;
axis_register_slice_32 reg_i (
.aclk ( aclk ),
.aresetn ( aresetn ),
.s_axis_tvalid ( in_tvalid ),
.s_axis_tready ( in_tready ),
.s_axis_tdata ( in_tdata ),
.m_axis_tvalid ( c0_tvalid ),
.m_axis_tready ( c0_tready ),
.m_axis_tdata ( c0_tdata )
);
upsizing
#(
.n ( 32 )
)
upsizing_0
(
.aclk ( aclk ),
.aresetn ( aresetn ),
.in_tdata ( c0_tdata ),
.in_tvalid ( c0_tvalid ),
.in_tready ( c0_tready ),
.out_tdata ( c1_tdata ),
.out_tvalid ( c1_tvalid ),
.out_tready ( c1_tready )
);
skid_buffer
#(
.n ( 64 )
)
skid_0
(
.aclk ( aclk ),
.aresetn ( aresetn ),
.in_tdata ( c1_tdata ),
.in_tvalid ( c1_tvalid ),
.in_tready ( c1_tready ),
.out_tdata ( c1s_tdata ),
.out_tvalid ( c1s_tvalid ),
.out_tready ( c1s_tready )
);
downsizing
#(
.n ( 32 )
)
downsizing_0
(
.aclk ( aclk ),
.aresetn ( aresetn ),
.in_tdata ( c1s_tdata ),
.in_tvalid ( c1s_tvalid ),
.in_tready ( c1s_tready ),
.out_tdata ( c2_tdata ),
.out_tvalid ( c2_tvalid ),
.out_tready ( c2_tready )
);
skid_buffer
#(
.n ( 32 )
)
skid_1
(
.aclk ( aclk ),
.aresetn ( aresetn ),
.in_tdata ( c2_tdata ),
.in_tvalid ( c2_tvalid ),
.in_tready ( c2_tready ),
.out_tdata ( c2s_tdata ),
.out_tvalid ( c2s_tvalid ),
.out_tready ( c2s_tready )
);
upsizing
#(
.n ( 32 )
)
upsizing_1
(
.aclk ( aclk ),
.aresetn ( aresetn ),
.in_tdata ( c2s_tdata ),
.in_tvalid ( c2s_tvalid ),
.in_tready ( c2s_tready ),
.out_tdata ( c3_tdata ),
.out_tvalid ( c3_tvalid ),
.out_tready ( c3_tready )
);
skid_buffer
#(
.n ( 64 )
)
skid_2
(
.aclk ( aclk ),
.aresetn ( aresetn ),
.in_tdata ( c3_tdata ),
.in_tvalid ( c3_tvalid ),
.in_tready ( c3_tready ),
.out_tdata ( c3s_tdata ),
.out_tvalid ( c3s_tvalid ),
.out_tready ( c3s_tready )
);
downsizing
#(
.n ( 32 )
)
downsizing_1
(
.aclk ( aclk ),
.aresetn ( aresetn ),
.in_tdata ( c3s_tdata ),
.in_tvalid ( c3s_tvalid ),
.in_tready ( c3s_tready ),
.out_tdata ( c4_tdata ),
.out_tvalid ( c4_tvalid ),
.out_tready ( c4_tready )
);
axis_register_slice_32 reg_0 (
.aclk ( aclk ),
.aresetn ( aresetn ),
.s_axis_tvalid ( c4_tvalid ),
.s_axis_tready ( c4_tready ),
.s_axis_tdata ( c4_tdata ),
.m_axis_tvalid ( out_tvalid ),
.m_axis_tready ( out_tready ),
.m_axis_tdata ( out_tdata )
);
endmodule |
module other_single_port_ram21
#( parameter RAMLENGTH=800, //RAMLENGTH*DATAWIDTH = 4800 = 80x60 RAM RESOLUTION
RAM_INITIAL_VALUE=6'b111111, //default value for memreset
DATA_WIDTH=6,
ADDR_WIDTH=10
)
(
input [DATA_WIDTH-1:0]data, //RAM words' write input
input [ADDR_WIDTH-1:0] addr, //ln(RAMLENGTH)/ln(2)
input we, clk, memenable,
input [ADDR_WIDTH:0] resetcnt,
output [DATA_WIDTH-1:0]q //RAM words' read input
);
//memreset variable
//integer i;
// Declare the RAM variable
(* ramstyle = "M9K" *) reg [DATA_WIDTH-1:0]ramblock[3*RAMLENGTH-1:0] ;
//(* ramstyle = "M9K" *) - synthesis attribute for making ramblocks of Altera M9K memory blocks
// !!! Not sure in its usefullness
// Variable to hold the registered read address, write data, and we
reg [ADDR_WIDTH-1:0] addr_reg;
reg [DATA_WIDTH-1:0] data_reg;
reg we_reg;
wire [ADDR_WIDTH-1:0] addr_x;
wire [DATA_WIDTH-1:0] data_x;
wire we_x;
// always @ (posedge clk)begin
// //memory reset
// if(memreset) counter<='d800;
// else if(counter!=0)
// begin
// counter<=counter-1;
// ramblock[counter-1]<=RAM_INITIAL_VALUE;
// end
// //R/W operations
// else if(enable) begin
// addr_reg <= addr;
// data_reg <= data;
// we_reg<=we;
// // Write
// if (we_reg) begin
// ramblock[addr_reg]<=data_reg;
// end
// end
// end
assign addr_x = (memenable) ? addr : resetcnt;
assign data_x = (memenable) ? data : '0;
assign we_x = (memenable) ? we : 1;
always @ (posedge clk)begin
addr_reg <= addr_x;
we_reg<=we_x;
data_reg <= data_x;
if (we_reg) begin ramblock[addr_reg]<=data_reg;
end
end
// Continuous assignment implies read returns NEW data.
// This is the natural behavior of the TriMatrix memory
// blocks in Single Port mode.
assign q = ramblock[addr_reg];
endmodule |
module TestBench();
parameter RAMLENGTH = 800,
DATA_WIDTH=6,
ADDR_WIDTH=10,
V_BOTTOM = 1,
V_SYNC = 3,
V_TOP = 30,
H_FRONT = 80,
H_SYNC = 136,
H_BACK = 216,
RESOLUTION_H = 640,
RESOLUTION_V = 480,
X_WIRE_WIDTH = $clog2 (RESOLUTION_H+H_FRONT+H_SYNC+H_BACK),
Y_WIRE_WIDTH = $clog2 (RESOLUTION_V+V_BOTTOM+V_SYNC+V_TOP);
reg display_on, clk, memreset,reset_n,fifoempty;
reg [ADDR_WIDTH-1:0] resetcnt;
reg [X_WIRE_WIDTH-1:0] hpos;
reg [Y_WIRE_WIDTH-1:0] vpos;
reg [2:0] RGBin,RGB;
int hpos_check[10];
int vpos_check[10];
int RGB_check[10];
RGBMemory_top
#(
.RAMLENGTH(RAMLENGTH), //RAMLENGTH*DATAWIDTH = 4800 = 80x60 RAM RESOLUTION
.DATA_WIDTH(DATA_WIDTH),
.X_WIRE_WIDTH(X_WIRE_WIDTH),
.Y_WIRE_WIDTH(Y_WIRE_WIDTH),
.ADDR_WIDTH(ADDR_WIDTH),
.RESOLUTION_H(RESOLUTION_H),
.RESOLUTION_V(RESOLUTION_V)
)
FrameBuffer
(
.display_on(display_on),
.clk(clk),
.memreset(memreset),
.reset_n(~reset_n),
.resetcnt(resetcnt),
.RGBin(RGBin),
.hpos(hpos),
.vpos(vpos),
.RGB(RGB),
.fifoempty(fifoempty)
);
always #5 clk=~clk;
initial begin
fifoempty=0;
clk=0;
display_on=1;
RGBin=0;
resetcnt=0;
memreset=0;
hpos=0;
vpos=0;
RGB=0;
reset_n=0;
#20;
reset_n=1;
for(integer i=0; i<800; i++) begin
resetcnt<=i;
#10;
end
#15;
memreset=1;
#100
display_on=0;
vpos=0;
for(integer i=0; i<5; i++) begin
hpos=i;
if((i%2)==0) RGBin=3'b111;
else RGBin=3'b000;
#50;
end
#120;
display_on=1;
RGBin=0;
vpos=0;
for(integer i=0;i<31;i++) begin
hpos=i; #10;
end
#120
display_on=0;
vpos=1;
for(integer i=0; i<5; i++) begin
hpos=i;
if((i%2)==0) RGBin=3'b111;
else RGBin=3'b000;
#50;
end
#120
display_on=1;
RGBin=0;
vpos=0;
for(integer i=0;i<31;i++) begin
hpos=i; #10;
end
#120
display_on=0;
vpos=2;
for(integer i=0; i<5; i++) begin
hpos=i;
if((i%2)==0) RGBin=3'b111;
else RGBin=3'b000;
#50;
end
#120
display_on=1;
RGBin=0;
vpos=0;
for(integer i=0;i<31;i++) begin
hpos=i; #10;
end
#120
hpos=0;
vpos=0;
/*#100
display_on=0;
for(integer i=0; i<10; i++)begin
hpos=$urandom_range(0,79);
vpos=$urandom_range(0,59);
RGBin=$urandom_range(0,7);
hpos_check[i]=hpos;
vpos_check[i]=vpos;
RGB_check[i]=RGBin;
#50;
end
#10
display_on=1;
for(integer i=0; i<10; i++)begin
hpos=hpos_check[i]*8;
vpos=vpos_check[i]*8;
#10;
if(RGB!=RGB_check[i]) $display("Wrong data on the coordinates hpos=%d, vpos=%d. Supposed to be %d ",hpos,vpos, RGB_check[i]);
end
#10*/
$stop;
end
endmodule |
module Top_FB_TestBench();
reg clk, reset_n;
top DUT (
.clk(clk),
.reset_n(reset_n)
);
always #5 clk=~clk;
initial begin
clk=1;
reset_n=0;
#20;
reset_n=1;
end
endmodule |
module FIFOTestBench();
parameter RESOLUTION_H = 1280,
RESOLUTION_V = 960,
V_BOTTOM = 1,
V_SYNC = 3,
V_TOP = 30,
H_FRONT = 80,
H_SYNC = 136,
H_BACK = 216,
X_WIRE_WIDTH = $clog2 (RESOLUTION_H+H_FRONT+H_SYNC+H_BACK),
Y_WIRE_WIDTH = $clog2 (RESOLUTION_V+V_BOTTOM+V_SYNC+V_TOP),
FIFODEPTH=10;
reg clk,reset_n,push,pop,empty,full;
reg [X_WIRE_WIDTH-1:0] hpos,hpos_read;
reg [Y_WIRE_WIDTH-1:0] vpos,vpos_read;
reg [2:0] RGBin,RGB;
//int hpos_check[10];
//int vpos_check[10];
//int RGB_check[10];
FIFO_top
#(
.RESOLUTION_H(RESOLUTION_H),
.RESOLUTION_V(RESOLUTION_V),
.V_BOTTOM(V_BOTTOM),
.V_SYNC(V_SYNC),
.V_TOP(V_TOP),
.H_FRONT(H_FRONT),
.H_SYNC(H_SYNC),
.H_BACK(H_BACK),
.FIFODEPTH(FIFODEPTH)
)
DUT (
.clk(clk),
.rst(~reset_n),
.push(push),
.toppop(pop),
.hpos_write(hpos),
.vpos_write(vpos),
.RGB_write(RGBin),
.hpos_read(hpos_read),
.vpos_read(vpos_read),
.RGB_read(RGB),
.empty(empty),
.full(full)
);
always #5 clk=~clk;
initial begin
clk=0;
push=0;
pop=0;
hpos=0;
vpos=0;
hpos_read=0;
vpos_read=0;
RGBin=0;
reset_n=0;
#20;
reset_n=1;
#10
push=1;
for(integer i=0; i<10; i++) begin
hpos=$urandom_range(0,1279);
vpos=$urandom_range(0,959);
RGBin=$urandom_range(0,7);
#10;
end
push=0;
#10;
pop=1;
#550;
pop=0;
push=1;
for(integer i=0; i<7; i++) begin
hpos=$urandom_range(0,1279);
vpos=$urandom_range(0,959);
RGBin=$urandom_range(0,7);
#10;
end
push=0;
#10;
pop=1;
#120;
$stop;
end
endmodule |
module Top_FB_TestBench();
reg clk, reset_n;
reg [3:0] key_sw;
top DUT (
.clk(clk),
.reset_n(reset_n),
.key_sw(key_sw)
);
always #5 clk=~clk;
initial begin
clk=1;
reset_n=0;
key_sw=0;
#20;
reset_n=1;
end
endmodule |
module sm_rom_p1
#(
parameter SIZE = 64
)
(
input [31:0] a,
output [31:0] rd
);
reg [31:0] rom [SIZE - 1:0];
assign rd = rom [a];
initial begin
$readmemh ("p1_program.hex", rom);
end
endmodule |
module sm_rom_p0
#(
parameter SIZE = 64
)
(
input [31:0] a,
output [31:0] rd
);
reg [31:0] rom [SIZE - 1:0];
assign rd = rom [a];
initial begin
$readmemh ("p0_program.hex", rom);
end
endmodule |
module arbiter
#(
parameter N = 5 // Number of requesters
)(
input wire rst,
input wire clk,
input wire [N-1:0] req,
output wire [N-1:0] grant
);
reg [N-1:0] pointer_req;
//reg [N-1:0] next_grant;
wire [2*N-1:0] double_req = {req,req};
wire [2*N-1:0] double_grant = double_req & ~(double_req - pointer_req);
//Asynchronous grant update
// assign grant = (rst)? {N{1'b0}} : double_grant[N-1:0] | double_grant[2*N-1:N];
assign grant = double_grant[N-1:0] | double_grant[2*N-1:N];
//Update the rotate pointer
wire [N-1:0] new_req = req ^ grant;
wire [2*N-1:0] new_double_req = {new_req,new_req};
wire [2*N-1:0] new_double_grant = new_double_req & ~(new_double_req - pointer_req);
wire [N-1:0] async_pointer_req = new_double_grant[N-1:0] | new_double_grant[2*N-1:N];
always @ (posedge clk)
if (rst || async_pointer_req == 0)
pointer_req <= #1 1;
else
pointer_req <= #1 async_pointer_req;
endmodule |
module mfp_uart_receiver (
input clock,
input reset_n,
input rx,
output reg [7:0] byte_data,
output byte_ready
);
parameter clock_frequency = 50000000;
parameter baud_rate = 9600;
parameter clock_cycles_in_symbol = clock_frequency / baud_rate;
// Synchronize rx input to clock
reg rx_sync1, rx_sync;
always @(posedge clock or negedge reset_n) begin
if (!reset_n) begin
rx_sync1 <= 1'b1;
rx_sync <= 1'b1;
end else begin
rx_sync1 <= rx;
rx_sync <= rx_sync1;
end
end
// Finding edge for start bit
reg prev_rx_sync;
always @(posedge clock or negedge reset_n) begin
if (!reset_n) prev_rx_sync <= 1'b1;
else prev_rx_sync <= rx_sync;
end
wire start_bit_edge = prev_rx_sync & !rx_sync;
// Counter to measure distance between symbols
reg [31:0] counter;
reg load_counter;
reg [31:0] load_counter_value;
always @(posedge clock or negedge reset_n) begin
if (!reset_n) counter <= 32'b0;
else if (load_counter) counter <= load_counter_value;
else if (counter != 0) counter <= counter - 1;
end
wire counter_done = counter == 1;
// Shift register to accumulate data
reg shift;
reg [7:0] shifted_1;
assign byte_ready = shifted_1[0];
always @(posedge clock or negedge reset_n) begin
if (!reset_n) begin
shifted_1 <= 8'b0;
end else if (shift) begin
if (shifted_1 == 0) shifted_1 <= 8'b10000000;
else shifted_1 <= shifted_1 >> 1;
byte_data <= {rx, byte_data[7:1]};
end else if (byte_ready) begin
shifted_1 <= 8'b0;
end
end
reg idle, idle_r;
always @* begin
idle = idle_r;
shift = 1'b0;
load_counter = 32'b0;
load_counter_value = 32'b0;
if (idle) begin
if (start_bit_edge) begin
load_counter = 1;
load_counter_value = clock_cycles_in_symbol * 3 / 2;
idle = 1'b0;
end
end else if (counter_done) begin
shift = 1'b1;
load_counter = 1;
load_counter_value = clock_cycles_in_symbol;
end else if (byte_ready) begin
idle = 1'b1;
end
end
always @(posedge clock or negedge reset_n) begin
if (!reset_n) idle_r <= 1'b1;
else idle_r <= idle;
end
endmodule |
module data_aggregator (
input clock,
input reset,
input enter,
input add,
input multiply,
input separator,
input [3:0] data,
output reg [7:0] number,
output reg enter_occured
);
always @(posedge clock) begin
if (reset) begin
number <= 8'b0;
enter_occured <= 1'b0;
end else if (enter) begin
number <= {number[3:0], data};
enter_occured <= 1'b1;
end else if (add || multiply) begin
enter_occured <= 1'b0;
end else if (separator) begin
number <= 8'b0;
end
end
endmodule |
module two_bytes_uart_tx (
input clock,
input start,
input reset,
input [15:0] data,
output reg q,
output busy
);
reg [12:0] cnt;
reg [3:0] bit_num;
wire bit_start = (cnt == 5208);
wire idle = (bit_num == 4'hF);
assign busy = ~idle;
reg byte_state;
wire [7:0] word = byte_state ? data[7:0] : data[15:8];
always @(posedge clock) begin
if (reset) cnt <= 13'b0;
else if (start && idle) cnt <= 13'b0;
else if (bit_start) cnt <= 13'b0;
else cnt <= cnt + 13'b1;
end
always @(posedge clock) begin
if (reset) begin
bit_num <= 4'hf;
byte_state <= 1'b0;
q <= 1'b1;
end else if (start && idle) begin
bit_num <= 4'h0;
byte_state <= 1'b0;
q <= 1'b1;
end else if (bit_start) begin
case (bit_num)
4'h0: begin bit_num <= 4'h1; q <= 1'b0; end // start
4'h1: begin bit_num <= 4'h2; q <= word[0]; end
4'h2: begin bit_num <= 4'h3; q <= word[1]; end
4'h3: begin bit_num <= 4'h4; q <= word[2]; end
4'h4: begin bit_num <= 4'h5; q <= word[3]; end
4'h5: begin bit_num <= 4'h6; q <= word[4]; end
4'h6: begin bit_num <= 4'h7; q <= word[5]; end
4'h7: begin bit_num <= 4'h8; q <= word[6]; end
4'h8: begin bit_num <= 4'h9; q <= word[7]; end
4'h9: begin bit_num <= 4'ha; q <= 1'b1; // finish
if (!byte_state) begin
byte_state <= 1'b1;
bit_num <= 4'h0;
end
end
default: begin bit_num <= 4'hF; end // Stop
endcase
end
end
endmodule |
module uart_transmitter (
input clock,
input start,
input reset,
input [15:0] data,
output reg q,
output busy
);
parameter clock_frequency = 50000000;
parameter baud_rate = 9600;
parameter clock_cycles_in_bit = clock_frequency / baud_rate;
reg [12:0] cnt;
reg [3:0] bit_num;
wire bit_start = (cnt == clock_cycles_in_bit);
wire idle = (bit_num == 4'hF);
assign busy = ~idle;
reg byte_state;
wire [7:0] word = byte_state ? data[7:0] : data[15:8];
always @(posedge clock) begin
if (reset) cnt <= 13'b0;
else if (start && idle) cnt <= 13'b0;
else if (bit_start) cnt <= 13'b0;
else cnt <= cnt + 13'b1;
end
always @(posedge clock) begin
if (reset) begin
bit_num <= 4'hF;
byte_state <= 1'b0;
q <= 1'b1;
end else if (start && idle) begin
bit_num <= 4'h0;
byte_state <= 1'b0;
q <= 1'b1;
end else if (bit_start) begin
case (bit_num)
4'h0: begin bit_num <= 4'h1; q <= 1'b0; end // start
4'h1: begin bit_num <= 4'h2; q <= word[0]; end
4'h2: begin bit_num <= 4'h3; q <= word[1]; end
4'h3: begin bit_num <= 4'h4; q <= word[2]; end
4'h4: begin bit_num <= 4'h5; q <= word[3]; end
4'h5: begin bit_num <= 4'h6; q <= word[4]; end
4'h6: begin bit_num <= 4'h7; q <= word[5]; end
4'h7: begin bit_num <= 4'h8; q <= word[6]; end
4'h8: begin bit_num <= 4'h9; q <= word[7]; end
4'h9: begin bit_num <= 4'ha; q <= 1'b1; // finish
if (!byte_state) begin
byte_state <= 1'b1;
bit_num <= 4'h0;
end
end
default: begin bit_num <= 4'hF; end // Stop
endcase
end
end
endmodule |
module seven_segment_4_digits (
input clock,
input reset,
input [15:0] number,
output reg [7:0] abcdefgh,
output reg [3:0] digit
);
function [7:0] bcd_to_seg(input [3:0] bcd);
case (bcd)
'h0: bcd_to_seg = 'b00000011; // a b c d e f g h
'h1: bcd_to_seg = 'b10011111;
'h2: bcd_to_seg = 'b00100101; // --a--
'h3: bcd_to_seg = 'b00001101; // | |
'h4: bcd_to_seg = 'b10011001; // f b
'h5: bcd_to_seg = 'b01001001; // | |
'h6: bcd_to_seg = 'b01000001; // --g--
'h7: bcd_to_seg = 'b00011111; // | |
'h8: bcd_to_seg = 'b00000001; // e c
'h9: bcd_to_seg = 'b00011001; // | |
'ha: bcd_to_seg = 'b00010001; // --d-- h
'hb: bcd_to_seg = 'b11000001;
'hc: bcd_to_seg = 'b01100011;
'hd: bcd_to_seg = 'b10000101;
'he: bcd_to_seg = 'b01100001;
'hf: bcd_to_seg = 'b01110001;
endcase
endfunction
reg [15:0] cnt;
always @(posedge clock)
if (reset) cnt <= 16'd0;
else cnt <= cnt + 16'd1;
reg [1:0] i;
always @(posedge clock) begin
if (reset) begin
abcdefgh <= bcd_to_seg(0);
digit <= ~4'b1;
i <= 2'b0;
end else if (cnt == 16'b0) begin
abcdefgh <= bcd_to_seg(number[i * 4 +: 4]);
digit <= ~(4'b1 << i);
i <= i + 1;
end
end
endmodule |
module top (
input clock,
input reset_n,
input rx,
output reg tx,
output reg [7:0] abcdefgh,
output reg [3:0] nx_digit
);
wire byte_ready;
wire [7:0] ascii_data;
uart_receiver listener (
.clock (clock),
.reset_n(reset_n),
.rx (rx),
.byte_data (ascii_data),
.byte_ready(byte_ready)
);
wire separator, add, multiply, enter, clear, error_ascii;
wire [3:0] digit;
ascii_to_action translator (
.clock(clock),
.start(byte_ready),
.reset(~reset_n),
.data (ascii_data),
.separator(separator),
.add (add),
.multiply (multiply),
.digit (digit),
.enter (enter),
.clear (clear),
.error (error_ascii)
);
// Prepare and accumulate data
logic [7:0] number;
logic enter_occured;
data_aggregator aggregator (
.clock (clock),
.reset (~reset_n),
.enter (enter),
.add (add),
.multiply (multiply),
.separator(separator),
.data (digit),
.number (number),
.enter_occured(enter_occured)
);
// ~~~~~~~~~~~~~~~~~~~~~~~~~~~~
wire [15:0] result;
wire overflow, newresult;
wire [3:0] error_calculator;
wire is_tx_busy;
calculator calculator (
.clock (clock),
.reset (~reset_n || clear),
.enter (separator & enter_occured),
.add (add),
.multiply(multiply),
.data (number),
.newresult(newresult),
.result (result),
.overflow (overflow),
.error (error_calculator)
);
seven_segment_4_digits display (
.clock (clock),
.reset (~reset_n),
.number(result),
.digit (nx_digit),
.abcdefgh(abcdefgh)
);
uart_transmitter loader (
.clock(clock),
.reset(~reset_n),
.start(newresult),
.data (result),
.q (tx),
.busy(is_tx_busy)
);
endmodule |
module DE0_NANO_SOC_QSYS_mm_interconnect_0_rsp_demux
(
// -------------------
// Sink
// -------------------
input [1-1 : 0] sink_valid,
input [96-1 : 0] sink_data, // ST_DATA_W=96
input [6-1 : 0] sink_channel, // ST_CHANNEL_W=6
input sink_startofpacket,
input sink_endofpacket,
output sink_ready,
// -------------------
// Sources
// -------------------
output reg src0_valid,
output reg [96-1 : 0] src0_data, // ST_DATA_W=96
output reg [6-1 : 0] src0_channel, // ST_CHANNEL_W=6
output reg src0_startofpacket,
output reg src0_endofpacket,
input src0_ready,
output reg src1_valid,
output reg [96-1 : 0] src1_data, // ST_DATA_W=96
output reg [6-1 : 0] src1_channel, // ST_CHANNEL_W=6
output reg src1_startofpacket,
output reg src1_endofpacket,
input src1_ready,
// -------------------
// Clock & Reset
// -------------------
(*altera_attribute = "-name MESSAGE_DISABLE 15610" *) // setting message suppression on clk
input clk,
(*altera_attribute = "-name MESSAGE_DISABLE 15610" *) // setting message suppression on reset
input reset
);
localparam NUM_OUTPUTS = 2;
wire [NUM_OUTPUTS - 1 : 0] ready_vector;
// -------------------
// Demux
// -------------------
always @* begin
src0_data = sink_data;
src0_startofpacket = sink_startofpacket;
src0_endofpacket = sink_endofpacket;
src0_channel = sink_channel >> NUM_OUTPUTS;
src0_valid = sink_channel[0] && sink_valid;
src1_data = sink_data;
src1_startofpacket = sink_startofpacket;
src1_endofpacket = sink_endofpacket;
src1_channel = sink_channel >> NUM_OUTPUTS;
src1_valid = sink_channel[1] && sink_valid;
end
// -------------------
// Backpressure
// -------------------
assign ready_vector[0] = src0_ready;
assign ready_vector[1] = src1_ready;
assign sink_ready = |(sink_channel & {{4{1'b0}},{ready_vector[NUM_OUTPUTS - 1 : 0]}});
endmodule |
module DE0_NANO_SOC_QSYS_mm_interconnect_0_cmd_demux
(
// -------------------
// Sink
// -------------------
input [6-1 : 0] sink_valid,
input [96-1 : 0] sink_data, // ST_DATA_W=96
input [6-1 : 0] sink_channel, // ST_CHANNEL_W=6
input sink_startofpacket,
input sink_endofpacket,
output sink_ready,
// -------------------
// Sources
// -------------------
output reg src0_valid,
output reg [96-1 : 0] src0_data, // ST_DATA_W=96
output reg [6-1 : 0] src0_channel, // ST_CHANNEL_W=6
output reg src0_startofpacket,
output reg src0_endofpacket,
input src0_ready,
output reg src1_valid,
output reg [96-1 : 0] src1_data, // ST_DATA_W=96
output reg [6-1 : 0] src1_channel, // ST_CHANNEL_W=6
output reg src1_startofpacket,
output reg src1_endofpacket,
input src1_ready,
// -------------------
// Clock & Reset
// -------------------
(*altera_attribute = "-name MESSAGE_DISABLE 15610" *) // setting message suppression on clk
input clk,
(*altera_attribute = "-name MESSAGE_DISABLE 15610" *) // setting message suppression on reset
input reset
);
localparam NUM_OUTPUTS = 2;
wire [NUM_OUTPUTS - 1 : 0] ready_vector;
// -------------------
// Demux
// -------------------
always @* begin
src0_data = sink_data;
src0_startofpacket = sink_startofpacket;
src0_endofpacket = sink_endofpacket;
src0_channel = sink_channel >> NUM_OUTPUTS;
src0_valid = sink_channel[0] && sink_valid[0];
src1_data = sink_data;
src1_startofpacket = sink_startofpacket;
src1_endofpacket = sink_endofpacket;
src1_channel = sink_channel >> NUM_OUTPUTS;
src1_valid = sink_channel[1] && sink_valid[1];
end
// -------------------
// Backpressure
// -------------------
assign ready_vector[0] = src0_ready;
assign ready_vector[1] = src1_ready;
assign sink_ready = |(sink_channel & {{4{1'b0}},{ready_vector[NUM_OUTPUTS - 1 : 0]}});
endmodule |
module DE0_NANO_SOC_QSYS_irq_mapper
(
// -------------------
// Clock & Reset
// -------------------
input clk,
input reset,
// -------------------
// IRQ Receivers
// -------------------
input receiver0_irq,
input receiver1_irq,
// -------------------
// Command Source (Output)
// -------------------
output reg [31 : 0] sender_irq
);
always @* begin
sender_irq = 0;
sender_irq[0] = receiver0_irq;
sender_irq[1] = receiver1_irq;
end
endmodule |
module DE0_NANO_SOC_QSYS_mm_interconnect_0_cmd_mux_002
(
// ----------------------
// Sinks
// ----------------------
input sink0_valid,
input [96-1 : 0] sink0_data,
input [6-1: 0] sink0_channel,
input sink0_startofpacket,
input sink0_endofpacket,
output sink0_ready,
// ----------------------
// Source
// ----------------------
output src_valid,
output [96-1 : 0] src_data,
output [6-1 : 0] src_channel,
output src_startofpacket,
output src_endofpacket,
input src_ready,
// ----------------------
// Clock & Reset
// ----------------------
input clk,
input reset
);
localparam PAYLOAD_W = 96 + 6 + 2;
localparam NUM_INPUTS = 1;
localparam SHARE_COUNTER_W = 1;
localparam PIPELINE_ARB = 1;
localparam ST_DATA_W = 96;
localparam ST_CHANNEL_W = 6;
localparam PKT_TRANS_LOCK = 60;
assign src_valid = sink0_valid;
assign src_data = sink0_data;
assign src_channel = sink0_channel;
assign src_startofpacket = sink0_startofpacket;
assign src_endofpacket = sink0_endofpacket;
assign sink0_ready = src_ready;
endmodule |
module DE0_NANO_SOC_QSYS_mm_interconnect_0_rsp_demux_002
(
// -------------------
// Sink
// -------------------
input [1-1 : 0] sink_valid,
input [96-1 : 0] sink_data, // ST_DATA_W=96
input [6-1 : 0] sink_channel, // ST_CHANNEL_W=6
input sink_startofpacket,
input sink_endofpacket,
output sink_ready,
// -------------------
// Sources
// -------------------
output reg src0_valid,
output reg [96-1 : 0] src0_data, // ST_DATA_W=96
output reg [6-1 : 0] src0_channel, // ST_CHANNEL_W=6
output reg src0_startofpacket,
output reg src0_endofpacket,
input src0_ready,
// -------------------
// Clock & Reset
// -------------------
(*altera_attribute = "-name MESSAGE_DISABLE 15610" *) // setting message suppression on clk
input clk,
(*altera_attribute = "-name MESSAGE_DISABLE 15610" *) // setting message suppression on reset
input reset
);
localparam NUM_OUTPUTS = 1;
wire [NUM_OUTPUTS - 1 : 0] ready_vector;
// -------------------
// Demux
// -------------------
always @* begin
src0_data = sink_data;
src0_startofpacket = sink_startofpacket;
src0_endofpacket = sink_endofpacket;
src0_channel = sink_channel >> NUM_OUTPUTS;
src0_valid = sink_channel[0] && sink_valid;
end
// -------------------
// Backpressure
// -------------------
assign ready_vector[0] = src0_ready;
assign sink_ready = |(sink_channel & {{5{1'b0}},{ready_vector[NUM_OUTPUTS - 1 : 0]}});
endmodule |
module DE0_NANO_SOC_QSYS_mm_interconnect_0_rsp_mux_001
(
// ----------------------
// Sinks
// ----------------------
input sink0_valid,
input [96-1 : 0] sink0_data,
input [6-1: 0] sink0_channel,
input sink0_startofpacket,
input sink0_endofpacket,
output sink0_ready,
input sink1_valid,
input [96-1 : 0] sink1_data,
input [6-1: 0] sink1_channel,
input sink1_startofpacket,
input sink1_endofpacket,
output sink1_ready,
input sink2_valid,
input [96-1 : 0] sink2_data,
input [6-1: 0] sink2_channel,
input sink2_startofpacket,
input sink2_endofpacket,
output sink2_ready,
input sink3_valid,
input [96-1 : 0] sink3_data,
input [6-1: 0] sink3_channel,
input sink3_startofpacket,
input sink3_endofpacket,
output sink3_ready,
input sink4_valid,
input [96-1 : 0] sink4_data,
input [6-1: 0] sink4_channel,
input sink4_startofpacket,
input sink4_endofpacket,
output sink4_ready,
input sink5_valid,
input [96-1 : 0] sink5_data,
input [6-1: 0] sink5_channel,
input sink5_startofpacket,
input sink5_endofpacket,
output sink5_ready,
// ----------------------
// Source
// ----------------------
output src_valid,
output [96-1 : 0] src_data,
output [6-1 : 0] src_channel,
output src_startofpacket,
output src_endofpacket,
input src_ready,
// ----------------------
// Clock & Reset
// ----------------------
input clk,
input reset
);
localparam PAYLOAD_W = 96 + 6 + 2;
localparam NUM_INPUTS = 6;
localparam SHARE_COUNTER_W = 1;
localparam PIPELINE_ARB = 0;
localparam ST_DATA_W = 96;
localparam ST_CHANNEL_W = 6;
localparam PKT_TRANS_LOCK = 60;
// ------------------------------------------
// Signals
// ------------------------------------------
wire [NUM_INPUTS - 1 : 0] request;
wire [NUM_INPUTS - 1 : 0] valid;
wire [NUM_INPUTS - 1 : 0] grant;
wire [NUM_INPUTS - 1 : 0] next_grant;
reg [NUM_INPUTS - 1 : 0] saved_grant;
reg [PAYLOAD_W - 1 : 0] src_payload;
wire last_cycle;
reg packet_in_progress;
reg update_grant;
wire [PAYLOAD_W - 1 : 0] sink0_payload;
wire [PAYLOAD_W - 1 : 0] sink1_payload;
wire [PAYLOAD_W - 1 : 0] sink2_payload;
wire [PAYLOAD_W - 1 : 0] sink3_payload;
wire [PAYLOAD_W - 1 : 0] sink4_payload;
wire [PAYLOAD_W - 1 : 0] sink5_payload;
assign valid[0] = sink0_valid;
assign valid[1] = sink1_valid;
assign valid[2] = sink2_valid;
assign valid[3] = sink3_valid;
assign valid[4] = sink4_valid;
assign valid[5] = sink5_valid;
// ------------------------------------------
// ------------------------------------------
// Grant Logic & Updates
// ------------------------------------------
// ------------------------------------------
reg [NUM_INPUTS - 1 : 0] lock;
always @* begin
lock[0] = sink0_data[60];
lock[1] = sink1_data[60];
lock[2] = sink2_data[60];
lock[3] = sink3_data[60];
lock[4] = sink4_data[60];
lock[5] = sink5_data[60];
end
assign last_cycle = src_valid & src_ready & src_endofpacket & ~(|(lock & grant));
// ------------------------------------------
// We're working on a packet at any time valid is high, except
// when this is the endofpacket.
// ------------------------------------------
always @(posedge clk or posedge reset) begin
if (reset) begin
packet_in_progress <= 1'b0;
end
else begin
if (last_cycle)
packet_in_progress <= 1'b0;
else if (src_valid)
packet_in_progress <= 1'b1;
end
end
// ------------------------------------------
// Shares
//
// Special case: all-equal shares _should_ be optimized into assigning a
// constant to next_grant_share.
// Special case: all-1's shares _should_ result in the share counter
// being optimized away.
// ------------------------------------------
// Input | arb shares | counter load value
// 0 | 1 | 0
// 1 | 1 | 0
// 2 | 1 | 0
// 3 | 1 | 0
// 4 | 1 | 0
// 5 | 1 | 0
wire [SHARE_COUNTER_W - 1 : 0] share_0 = 1'd0;
wire [SHARE_COUNTER_W - 1 : 0] share_1 = 1'd0;
wire [SHARE_COUNTER_W - 1 : 0] share_2 = 1'd0;
wire [SHARE_COUNTER_W - 1 : 0] share_3 = 1'd0;
wire [SHARE_COUNTER_W - 1 : 0] share_4 = 1'd0;
wire [SHARE_COUNTER_W - 1 : 0] share_5 = 1'd0;
// ------------------------------------------
// Choose the share value corresponding to the grant.
// ------------------------------------------
reg [SHARE_COUNTER_W - 1 : 0] next_grant_share;
always @* begin
next_grant_share =
share_0 & { SHARE_COUNTER_W {next_grant[0]} } |
share_1 & { SHARE_COUNTER_W {next_grant[1]} } |
share_2 & { SHARE_COUNTER_W {next_grant[2]} } |
share_3 & { SHARE_COUNTER_W {next_grant[3]} } |
share_4 & { SHARE_COUNTER_W {next_grant[4]} } |
share_5 & { SHARE_COUNTER_W {next_grant[5]} };
end
// ------------------------------------------
// Flag to indicate first packet of an arb sequence.
// ------------------------------------------
wire grant_changed = ~packet_in_progress && ~(|(saved_grant & valid));
reg first_packet_r;
wire first_packet = grant_changed | first_packet_r;
always @(posedge clk or posedge reset) begin
if (reset) begin
first_packet_r <= 1'b0;
end
else begin
if (update_grant)
first_packet_r <= 1'b1;
else if (last_cycle)
first_packet_r <= 1'b0;
else if (grant_changed)
first_packet_r <= 1'b1;
end
end
// ------------------------------------------
// Compute the next share-count value.
// ------------------------------------------
reg [SHARE_COUNTER_W - 1 : 0] p1_share_count;
reg [SHARE_COUNTER_W - 1 : 0] share_count;
reg share_count_zero_flag;
always @* begin
if (first_packet) begin
p1_share_count = next_grant_share;
end
else begin
// Update the counter, but don't decrement below 0.
p1_share_count = share_count_zero_flag ? '0 : share_count - 1'b1;
end
end
// ------------------------------------------
// Update the share counter and share-counter=zero flag.
// ------------------------------------------
always @(posedge clk or posedge reset) begin
if (reset) begin
share_count <= '0;
share_count_zero_flag <= 1'b1;
end
else begin
if (last_cycle) begin
share_count <= p1_share_count;
share_count_zero_flag <= (p1_share_count == '0);
end
end
end
// ------------------------------------------
// For each input, maintain a final_packet signal which goes active for the
// last packet of a full-share packet sequence. Example: if I have 4
// shares and I'm continuously requesting, final_packet is active in the
// 4th packet.
// ------------------------------------------
wire final_packet_0 = 1'b1;
wire final_packet_1 = 1'b1;
wire final_packet_2 = 1'b1;
wire final_packet_3 = 1'b1;
wire final_packet_4 = 1'b1;
wire final_packet_5 = 1'b1;
// ------------------------------------------
// Concatenate all final_packet signals (wire or reg) into a handy vector.
// ------------------------------------------
wire [NUM_INPUTS - 1 : 0] final_packet = {
final_packet_5,
final_packet_4,
final_packet_3,
final_packet_2,
final_packet_1,
final_packet_0
};
// ------------------------------------------
// ------------------------------------------
wire p1_done = |(final_packet & grant);
// ------------------------------------------
// Flag for the first cycle of packets within an
// arb sequence
// ------------------------------------------
reg first_cycle;
always @(posedge clk, posedge reset) begin
if (reset)
first_cycle <= 0;
else
first_cycle <= last_cycle && ~p1_done;
end
always @* begin
update_grant = 0;
// ------------------------------------------
// No arbitration pipeline, update grant whenever
// the current arb winner has consumed all shares,
// or all requests are low
// ------------------------------------------
update_grant = (last_cycle && p1_done) || (first_cycle && ~(|valid));
update_grant = last_cycle;
end
wire save_grant;
assign save_grant = 1;
assign grant = next_grant;
always @(posedge clk, posedge reset) begin
if (reset)
saved_grant <= '0;
else if (save_grant)
saved_grant <= next_grant;
end
// ------------------------------------------
// ------------------------------------------
// Arbitrator
// ------------------------------------------
// ------------------------------------------
// ------------------------------------------
// Create a request vector that stays high during
// the packet for unpipelined arbitration.
//
// The pipelined arbitration scheme does not require
// request to be held high during the packet.
// ------------------------------------------
assign request = valid;
altera_merlin_arbitrator
#(
.NUM_REQUESTERS(NUM_INPUTS),
.SCHEME ("no-arb"),
.PIPELINE (0)
) arb (
.clk (clk),
.reset (reset),
.request (request),
.grant (next_grant),
.save_top_priority (src_valid),
.increment_top_priority (update_grant)
);
// ------------------------------------------
// ------------------------------------------
// Mux
//
// Implemented as a sum of products.
// ------------------------------------------
// ------------------------------------------
assign sink0_ready = src_ready && grant[0];
assign sink1_ready = src_ready && grant[1];
assign sink2_ready = src_ready && grant[2];
assign sink3_ready = src_ready && grant[3];
assign sink4_ready = src_ready && grant[4];
assign sink5_ready = src_ready && grant[5];
assign src_valid = |(grant & valid);
always @* begin
src_payload =
sink0_payload & {PAYLOAD_W {grant[0]} } |
sink1_payload & {PAYLOAD_W {grant[1]} } |
sink2_payload & {PAYLOAD_W {grant[2]} } |
sink3_payload & {PAYLOAD_W {grant[3]} } |
sink4_payload & {PAYLOAD_W {grant[4]} } |
sink5_payload & {PAYLOAD_W {grant[5]} };
end
// ------------------------------------------
// Mux Payload Mapping
// ------------------------------------------
assign sink0_payload = {sink0_channel,sink0_data,
sink0_startofpacket,sink0_endofpacket};
assign sink1_payload = {sink1_channel,sink1_data,
sink1_startofpacket,sink1_endofpacket};
assign sink2_payload = {sink2_channel,sink2_data,
sink2_startofpacket,sink2_endofpacket};
assign sink3_payload = {sink3_channel,sink3_data,
sink3_startofpacket,sink3_endofpacket};
assign sink4_payload = {sink4_channel,sink4_data,
sink4_startofpacket,sink4_endofpacket};
assign sink5_payload = {sink5_channel,sink5_data,
sink5_startofpacket,sink5_endofpacket};
assign {src_channel,src_data,src_startofpacket,src_endofpacket} = src_payload;
endmodule |
module DE0_NANO_SOC_QSYS_mm_interconnect_0_router_default_decode
#(
parameter DEFAULT_CHANNEL = 1,
DEFAULT_WR_CHANNEL = -1,
DEFAULT_RD_CHANNEL = -1,
DEFAULT_DESTID = 3
)
(output [82 - 80 : 0] default_destination_id,
output [6-1 : 0] default_wr_channel,
output [6-1 : 0] default_rd_channel,
output [6-1 : 0] default_src_channel
);
assign default_destination_id =
DEFAULT_DESTID[82 - 80 : 0];
generate begin : default_decode
if (DEFAULT_CHANNEL == -1) begin
assign default_src_channel = '0;
end
else begin
assign default_src_channel = 6'b1 << DEFAULT_CHANNEL;
end
end
endgenerate
generate begin : default_decode_rw
if (DEFAULT_RD_CHANNEL == -1) begin
assign default_wr_channel = '0;
assign default_rd_channel = '0;
end
else begin
assign default_wr_channel = 6'b1 << DEFAULT_WR_CHANNEL;
assign default_rd_channel = 6'b1 << DEFAULT_RD_CHANNEL;
end
end
endgenerate
endmodule |
module DE0_NANO_SOC_QSYS_mm_interconnect_0_router
(
// -------------------
// Clock & Reset
// -------------------
input clk,
input reset,
// -------------------
// Command Sink (Input)
// -------------------
input sink_valid,
input [96-1 : 0] sink_data,
input sink_startofpacket,
input sink_endofpacket,
output sink_ready,
// -------------------
// Command Source (Output)
// -------------------
output src_valid,
output reg [96-1 : 0] src_data,
output reg [6-1 : 0] src_channel,
output src_startofpacket,
output src_endofpacket,
input src_ready
);
// -------------------------------------------------------
// Local parameters and variables
// -------------------------------------------------------
localparam PKT_ADDR_H = 55;
localparam PKT_ADDR_L = 36;
localparam PKT_DEST_ID_H = 82;
localparam PKT_DEST_ID_L = 80;
localparam PKT_PROTECTION_H = 86;
localparam PKT_PROTECTION_L = 84;
localparam ST_DATA_W = 96;
localparam ST_CHANNEL_W = 6;
localparam DECODER_TYPE = 0;
localparam PKT_TRANS_WRITE = 58;
localparam PKT_TRANS_READ = 59;
localparam PKT_ADDR_W = PKT_ADDR_H-PKT_ADDR_L + 1;
localparam PKT_DEST_ID_W = PKT_DEST_ID_H-PKT_DEST_ID_L + 1;
// -------------------------------------------------------
// Figure out the number of bits to mask off for each slave span
// during address decoding
// -------------------------------------------------------
localparam PAD0 = log2ceil(64'h80000 - 64'h40000);
localparam PAD1 = log2ceil(64'h81000 - 64'h80800);
// -------------------------------------------------------
// Work out which address bits are significant based on the
// address range of the slaves. If the required width is too
// large or too small, we use the address field width instead.
// -------------------------------------------------------
localparam ADDR_RANGE = 64'h81000;
localparam RANGE_ADDR_WIDTH = log2ceil(ADDR_RANGE);
localparam OPTIMIZED_ADDR_H = (RANGE_ADDR_WIDTH > PKT_ADDR_W) ||
(RANGE_ADDR_WIDTH == 0) ?
PKT_ADDR_H :
PKT_ADDR_L + RANGE_ADDR_WIDTH - 1;
localparam RG = RANGE_ADDR_WIDTH-1;
localparam REAL_ADDRESS_RANGE = OPTIMIZED_ADDR_H - PKT_ADDR_L;
reg [PKT_ADDR_W-1 : 0] address;
always @* begin
address = {PKT_ADDR_W{1'b0}};
address [REAL_ADDRESS_RANGE:0] = sink_data[OPTIMIZED_ADDR_H : PKT_ADDR_L];
end
// -------------------------------------------------------
// Pass almost everything through, untouched
// -------------------------------------------------------
assign sink_ready = src_ready;
assign src_valid = sink_valid;
assign src_startofpacket = sink_startofpacket;
assign src_endofpacket = sink_endofpacket;
wire [PKT_DEST_ID_W-1:0] default_destid;
wire [6-1 : 0] default_src_channel;
DE0_NANO_SOC_QSYS_mm_interconnect_0_router_default_decode the_default_decode(
.default_destination_id (default_destid),
.default_wr_channel (),
.default_rd_channel (),
.default_src_channel (default_src_channel)
);
always @* begin
src_data = sink_data;
src_channel = default_src_channel;
src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = default_destid;
// --------------------------------------------------
// Address Decoder
// Sets the channel and destination ID based on the address
// --------------------------------------------------
// ( 0x40000 .. 0x80000 )
if ( {address[RG:PAD0],{PAD0{1'b0}}} == 20'h40000 ) begin
src_channel = 6'b10;
src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 3;
end
// ( 0x80800 .. 0x81000 )
if ( {address[RG:PAD1],{PAD1{1'b0}}} == 20'h80800 ) begin
src_channel = 6'b01;
src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 2;
end
end
// --------------------------------------------------
// Ceil(log2()) function
// --------------------------------------------------
function integer log2ceil;
input reg[65:0] val;
reg [65:0] i;
begin
i = 1;
log2ceil = 0;
while (i < val) begin
log2ceil = log2ceil + 1;
i = i << 1;
end
end
endfunction
endmodule |
module DE0_NANO_SOC_QSYS_mm_interconnect_0_cmd_mux
(
// ----------------------
// Sinks
// ----------------------
input sink0_valid,
input [96-1 : 0] sink0_data,
input [6-1: 0] sink0_channel,
input sink0_startofpacket,
input sink0_endofpacket,
output sink0_ready,
input sink1_valid,
input [96-1 : 0] sink1_data,
input [6-1: 0] sink1_channel,
input sink1_startofpacket,
input sink1_endofpacket,
output sink1_ready,
// ----------------------
// Source
// ----------------------
output src_valid,
output [96-1 : 0] src_data,
output [6-1 : 0] src_channel,
output src_startofpacket,
output src_endofpacket,
input src_ready,
// ----------------------
// Clock & Reset
// ----------------------
input clk,
input reset
);
localparam PAYLOAD_W = 96 + 6 + 2;
localparam NUM_INPUTS = 2;
localparam SHARE_COUNTER_W = 1;
localparam PIPELINE_ARB = 1;
localparam ST_DATA_W = 96;
localparam ST_CHANNEL_W = 6;
localparam PKT_TRANS_LOCK = 60;
// ------------------------------------------
// Signals
// ------------------------------------------
wire [NUM_INPUTS - 1 : 0] request;
wire [NUM_INPUTS - 1 : 0] valid;
wire [NUM_INPUTS - 1 : 0] grant;
wire [NUM_INPUTS - 1 : 0] next_grant;
reg [NUM_INPUTS - 1 : 0] saved_grant;
reg [PAYLOAD_W - 1 : 0] src_payload;
wire last_cycle;
reg packet_in_progress;
reg update_grant;
wire [PAYLOAD_W - 1 : 0] sink0_payload;
wire [PAYLOAD_W - 1 : 0] sink1_payload;
assign valid[0] = sink0_valid;
assign valid[1] = sink1_valid;
wire [NUM_INPUTS - 1 : 0] eop;
assign eop[0] = sink0_endofpacket;
assign eop[1] = sink1_endofpacket;
// ------------------------------------------
// ------------------------------------------
// Grant Logic & Updates
// ------------------------------------------
// ------------------------------------------
reg [NUM_INPUTS - 1 : 0] lock;
always @* begin
lock[0] = sink0_data[60];
lock[1] = sink1_data[60];
end
reg [NUM_INPUTS - 1 : 0] locked = '0;
always @(posedge clk or posedge reset) begin
if (reset) begin
locked <= '0;
end
else begin
locked <= next_grant & lock;
end
end
assign last_cycle = src_valid & src_ready & src_endofpacket & ~(|(lock & grant));
// ------------------------------------------
// We're working on a packet at any time valid is high, except
// when this is the endofpacket.
// ------------------------------------------
always @(posedge clk or posedge reset) begin
if (reset) begin
packet_in_progress <= 1'b0;
end
else begin
if (last_cycle)
packet_in_progress <= 1'b0;
else if (src_valid)
packet_in_progress <= 1'b1;
end
end
// ------------------------------------------
// Shares
//
// Special case: all-equal shares _should_ be optimized into assigning a
// constant to next_grant_share.
// Special case: all-1's shares _should_ result in the share counter
// being optimized away.
// ------------------------------------------
// Input | arb shares | counter load value
// 0 | 1 | 0
// 1 | 1 | 0
wire [SHARE_COUNTER_W - 1 : 0] share_0 = 1'd0;
wire [SHARE_COUNTER_W - 1 : 0] share_1 = 1'd0;
// ------------------------------------------
// Choose the share value corresponding to the grant.
// ------------------------------------------
reg [SHARE_COUNTER_W - 1 : 0] next_grant_share;
always @* begin
next_grant_share =
share_0 & { SHARE_COUNTER_W {next_grant[0]} } |
share_1 & { SHARE_COUNTER_W {next_grant[1]} };
end
// ------------------------------------------
// Flag to indicate first packet of an arb sequence.
// ------------------------------------------
// ------------------------------------------
// Compute the next share-count value.
// ------------------------------------------
reg [SHARE_COUNTER_W - 1 : 0] p1_share_count;
reg [SHARE_COUNTER_W - 1 : 0] share_count;
reg share_count_zero_flag;
always @* begin
// Update the counter, but don't decrement below 0.
p1_share_count = share_count_zero_flag ? '0 : share_count - 1'b1;
end
// ------------------------------------------
// Update the share counter and share-counter=zero flag.
// ------------------------------------------
always @(posedge clk or posedge reset) begin
if (reset) begin
share_count <= '0;
share_count_zero_flag <= 1'b1;
end
else begin
if (update_grant) begin
share_count <= next_grant_share;
share_count_zero_flag <= (next_grant_share == '0);
end
else if (last_cycle) begin
share_count <= p1_share_count;
share_count_zero_flag <= (p1_share_count == '0);
end
end
end
always @* begin
update_grant = 0;
// ------------------------------------------
// The pipeline delays grant by one cycle, so
// we have to calculate the update_grant signal
// one cycle ahead of time.
//
// Possible optimization: omit the first clause
// "if (!packet_in_progress & ~src_valid) ..."
// cost: one idle cycle at the the beginning of each
// grant cycle.
// benefit: save a small amount of logic.
// ------------------------------------------
if (!packet_in_progress & !src_valid)
update_grant = 1;
if (last_cycle && share_count_zero_flag)
update_grant = 1;
end
wire save_grant;
assign save_grant = update_grant;
assign grant = saved_grant;
always @(posedge clk, posedge reset) begin
if (reset)
saved_grant <= '0;
else if (save_grant)
saved_grant <= next_grant;
end
// ------------------------------------------
// ------------------------------------------
// Arbitrator
// ------------------------------------------
// ------------------------------------------
// ------------------------------------------
// Create a request vector that stays high during
// the packet for unpipelined arbitration.
//
// The pipelined arbitration scheme does not require
// request to be held high during the packet.
// ------------------------------------------
reg [NUM_INPUTS - 1 : 0] prev_request;
always @(posedge clk, posedge reset) begin
if (reset)
prev_request <= '0;
else
prev_request <= request & ~(valid & eop);
end
assign request = (PIPELINE_ARB == 1) ? valid | locked :
prev_request | valid | locked;
altera_merlin_arbitrator
#(
.NUM_REQUESTERS(NUM_INPUTS),
.SCHEME ("round-robin"),
.PIPELINE (1)
) arb (
.clk (clk),
.reset (reset),
.request (request),
.grant (next_grant),
.save_top_priority (src_valid),
.increment_top_priority (update_grant)
);
// ------------------------------------------
// ------------------------------------------
// Mux
//
// Implemented as a sum of products.
// ------------------------------------------
// ------------------------------------------
assign sink0_ready = src_ready && grant[0];
assign sink1_ready = src_ready && grant[1];
assign src_valid = |(grant & valid);
always @* begin
src_payload =
sink0_payload & {PAYLOAD_W {grant[0]} } |
sink1_payload & {PAYLOAD_W {grant[1]} };
end
// ------------------------------------------
// Mux Payload Mapping
// ------------------------------------------
assign sink0_payload = {sink0_channel,sink0_data,
sink0_startofpacket,sink0_endofpacket};
assign sink1_payload = {sink1_channel,sink1_data,
sink1_startofpacket,sink1_endofpacket};
assign {src_channel,src_data,src_startofpacket,src_endofpacket} = src_payload;
endmodule |
module DE0_NANO_SOC_QSYS_mm_interconnect_0_router_001_default_decode
#(
parameter DEFAULT_CHANNEL = 1,
DEFAULT_WR_CHANNEL = -1,
DEFAULT_RD_CHANNEL = -1,
DEFAULT_DESTID = 3
)
(output [82 - 80 : 0] default_destination_id,
output [6-1 : 0] default_wr_channel,
output [6-1 : 0] default_rd_channel,
output [6-1 : 0] default_src_channel
);
assign default_destination_id =
DEFAULT_DESTID[82 - 80 : 0];
generate begin : default_decode
if (DEFAULT_CHANNEL == -1) begin
assign default_src_channel = '0;
end
else begin
assign default_src_channel = 6'b1 << DEFAULT_CHANNEL;
end
end
endgenerate
generate begin : default_decode_rw
if (DEFAULT_RD_CHANNEL == -1) begin
assign default_wr_channel = '0;
assign default_rd_channel = '0;
end
else begin
assign default_wr_channel = 6'b1 << DEFAULT_WR_CHANNEL;
assign default_rd_channel = 6'b1 << DEFAULT_RD_CHANNEL;
end
end
endgenerate
endmodule |
module DE0_NANO_SOC_QSYS_mm_interconnect_0_router_001
(
// -------------------
// Clock & Reset
// -------------------
input clk,
input reset,
// -------------------
// Command Sink (Input)
// -------------------
input sink_valid,
input [96-1 : 0] sink_data,
input sink_startofpacket,
input sink_endofpacket,
output sink_ready,
// -------------------
// Command Source (Output)
// -------------------
output src_valid,
output reg [96-1 : 0] src_data,
output reg [6-1 : 0] src_channel,
output src_startofpacket,
output src_endofpacket,
input src_ready
);
// -------------------------------------------------------
// Local parameters and variables
// -------------------------------------------------------
localparam PKT_ADDR_H = 55;
localparam PKT_ADDR_L = 36;
localparam PKT_DEST_ID_H = 82;
localparam PKT_DEST_ID_L = 80;
localparam PKT_PROTECTION_H = 86;
localparam PKT_PROTECTION_L = 84;
localparam ST_DATA_W = 96;
localparam ST_CHANNEL_W = 6;
localparam DECODER_TYPE = 0;
localparam PKT_TRANS_WRITE = 58;
localparam PKT_TRANS_READ = 59;
localparam PKT_ADDR_W = PKT_ADDR_H-PKT_ADDR_L + 1;
localparam PKT_DEST_ID_W = PKT_DEST_ID_H-PKT_DEST_ID_L + 1;
// -------------------------------------------------------
// Figure out the number of bits to mask off for each slave span
// during address decoding
// -------------------------------------------------------
localparam PAD0 = log2ceil(64'h10 - 64'h0);
localparam PAD1 = log2ceil(64'h80000 - 64'h40000);
localparam PAD2 = log2ceil(64'h81000 - 64'h80800);
localparam PAD3 = log2ceil(64'h81008 - 64'h81000);
localparam PAD4 = log2ceil(64'h81010 - 64'h81008);
localparam PAD5 = log2ceil(64'h81018 - 64'h81010);
// -------------------------------------------------------
// Work out which address bits are significant based on the
// address range of the slaves. If the required width is too
// large or too small, we use the address field width instead.
// -------------------------------------------------------
localparam ADDR_RANGE = 64'h81018;
localparam RANGE_ADDR_WIDTH = log2ceil(ADDR_RANGE);
localparam OPTIMIZED_ADDR_H = (RANGE_ADDR_WIDTH > PKT_ADDR_W) ||
(RANGE_ADDR_WIDTH == 0) ?
PKT_ADDR_H :
PKT_ADDR_L + RANGE_ADDR_WIDTH - 1;
localparam RG = RANGE_ADDR_WIDTH-1;
localparam REAL_ADDRESS_RANGE = OPTIMIZED_ADDR_H - PKT_ADDR_L;
reg [PKT_ADDR_W-1 : 0] address;
always @* begin
address = {PKT_ADDR_W{1'b0}};
address [REAL_ADDRESS_RANGE:0] = sink_data[OPTIMIZED_ADDR_H : PKT_ADDR_L];
end
// -------------------------------------------------------
// Pass almost everything through, untouched
// -------------------------------------------------------
assign sink_ready = src_ready;
assign src_valid = sink_valid;
assign src_startofpacket = sink_startofpacket;
assign src_endofpacket = sink_endofpacket;
wire [PKT_DEST_ID_W-1:0] default_destid;
wire [6-1 : 0] default_src_channel;
// -------------------------------------------------------
// Write and read transaction signals
// -------------------------------------------------------
wire read_transaction;
assign read_transaction = sink_data[PKT_TRANS_READ];
DE0_NANO_SOC_QSYS_mm_interconnect_0_router_001_default_decode the_default_decode(
.default_destination_id (default_destid),
.default_wr_channel (),
.default_rd_channel (),
.default_src_channel (default_src_channel)
);
always @* begin
src_data = sink_data;
src_channel = default_src_channel;
src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = default_destid;
// --------------------------------------------------
// Address Decoder
// Sets the channel and destination ID based on the address
// --------------------------------------------------
// ( 0x0 .. 0x10 )
if ( {address[RG:PAD0],{PAD0{1'b0}}} == 20'h0 ) begin
src_channel = 6'b100000;
src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 4;
end
// ( 0x40000 .. 0x80000 )
if ( {address[RG:PAD1],{PAD1{1'b0}}} == 20'h40000 ) begin
src_channel = 6'b000010;
src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 3;
end
// ( 0x80800 .. 0x81000 )
if ( {address[RG:PAD2],{PAD2{1'b0}}} == 20'h80800 ) begin
src_channel = 6'b000001;
src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 2;
end
// ( 0x81000 .. 0x81008 )
if ( {address[RG:PAD3],{PAD3{1'b0}}} == 20'h81000 ) begin
src_channel = 6'b001000;
src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 1;
end
// ( 0x81008 .. 0x81010 )
if ( {address[RG:PAD4],{PAD4{1'b0}}} == 20'h81008 && read_transaction ) begin
src_channel = 6'b000100;
src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 5;
end
// ( 0x81010 .. 0x81018 )
if ( {address[RG:PAD5],{PAD5{1'b0}}} == 20'h81010 ) begin
src_channel = 6'b010000;
src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 0;
end
end
// --------------------------------------------------
// Ceil(log2()) function
// --------------------------------------------------
function integer log2ceil;
input reg[65:0] val;
reg [65:0] i;
begin
i = 1;
log2ceil = 0;
while (i < val) begin
log2ceil = log2ceil + 1;
i = i << 1;
end
end
endfunction
endmodule |
module DE0_NANO_SOC_QSYS_mm_interconnect_0_router_002_default_decode
#(
parameter DEFAULT_CHANNEL = 0,
DEFAULT_WR_CHANNEL = -1,
DEFAULT_RD_CHANNEL = -1,
DEFAULT_DESTID = 1
)
(output [82 - 80 : 0] default_destination_id,
output [6-1 : 0] default_wr_channel,
output [6-1 : 0] default_rd_channel,
output [6-1 : 0] default_src_channel
);
assign default_destination_id =
DEFAULT_DESTID[82 - 80 : 0];
generate begin : default_decode
if (DEFAULT_CHANNEL == -1) begin
assign default_src_channel = '0;
end
else begin
assign default_src_channel = 6'b1 << DEFAULT_CHANNEL;
end
end
endgenerate
generate begin : default_decode_rw
if (DEFAULT_RD_CHANNEL == -1) begin
assign default_wr_channel = '0;
assign default_rd_channel = '0;
end
else begin
assign default_wr_channel = 6'b1 << DEFAULT_WR_CHANNEL;
assign default_rd_channel = 6'b1 << DEFAULT_RD_CHANNEL;
end
end
endgenerate
endmodule |
module DE0_NANO_SOC_QSYS_mm_interconnect_0_router_002
(
// -------------------
// Clock & Reset
// -------------------
input clk,
input reset,
// -------------------
// Command Sink (Input)
// -------------------
input sink_valid,
input [96-1 : 0] sink_data,
input sink_startofpacket,
input sink_endofpacket,
output sink_ready,
// -------------------
// Command Source (Output)
// -------------------
output src_valid,
output reg [96-1 : 0] src_data,
output reg [6-1 : 0] src_channel,
output src_startofpacket,
output src_endofpacket,
input src_ready
);
// -------------------------------------------------------
// Local parameters and variables
// -------------------------------------------------------
localparam PKT_ADDR_H = 55;
localparam PKT_ADDR_L = 36;
localparam PKT_DEST_ID_H = 82;
localparam PKT_DEST_ID_L = 80;
localparam PKT_PROTECTION_H = 86;
localparam PKT_PROTECTION_L = 84;
localparam ST_DATA_W = 96;
localparam ST_CHANNEL_W = 6;
localparam DECODER_TYPE = 1;
localparam PKT_TRANS_WRITE = 58;
localparam PKT_TRANS_READ = 59;
localparam PKT_ADDR_W = PKT_ADDR_H-PKT_ADDR_L + 1;
localparam PKT_DEST_ID_W = PKT_DEST_ID_H-PKT_DEST_ID_L + 1;
// -------------------------------------------------------
// Figure out the number of bits to mask off for each slave span
// during address decoding
// -------------------------------------------------------
// -------------------------------------------------------
// Work out which address bits are significant based on the
// address range of the slaves. If the required width is too
// large or too small, we use the address field width instead.
// -------------------------------------------------------
localparam ADDR_RANGE = 64'h0;
localparam RANGE_ADDR_WIDTH = log2ceil(ADDR_RANGE);
localparam OPTIMIZED_ADDR_H = (RANGE_ADDR_WIDTH > PKT_ADDR_W) ||
(RANGE_ADDR_WIDTH == 0) ?
PKT_ADDR_H :
PKT_ADDR_L + RANGE_ADDR_WIDTH - 1;
localparam RG = RANGE_ADDR_WIDTH;
localparam REAL_ADDRESS_RANGE = OPTIMIZED_ADDR_H - PKT_ADDR_L;
reg [PKT_DEST_ID_W-1 : 0] destid;
// -------------------------------------------------------
// Pass almost everything through, untouched
// -------------------------------------------------------
assign sink_ready = src_ready;
assign src_valid = sink_valid;
assign src_startofpacket = sink_startofpacket;
assign src_endofpacket = sink_endofpacket;
wire [6-1 : 0] default_src_channel;
// -------------------------------------------------------
// Write and read transaction signals
// -------------------------------------------------------
wire read_transaction;
assign read_transaction = sink_data[PKT_TRANS_READ];
DE0_NANO_SOC_QSYS_mm_interconnect_0_router_002_default_decode the_default_decode(
.default_destination_id (),
.default_wr_channel (),
.default_rd_channel (),
.default_src_channel (default_src_channel)
);
always @* begin
src_data = sink_data;
src_channel = default_src_channel;
// --------------------------------------------------
// DestinationID Decoder
// Sets the channel based on the destination ID.
// --------------------------------------------------
destid = sink_data[PKT_DEST_ID_H : PKT_DEST_ID_L];
if (destid == 1 && read_transaction) begin
src_channel = 6'b01;
end
if (destid == 0 ) begin
src_channel = 6'b10;
end
end
// --------------------------------------------------
// Ceil(log2()) function
// --------------------------------------------------
function integer log2ceil;
input reg[65:0] val;
reg [65:0] i;
begin
i = 1;
log2ceil = 0;
while (i < val) begin
log2ceil = log2ceil + 1;
i = i << 1;
end
end
endfunction
endmodule |
module DE0_NANO_SOC_QSYS_mm_interconnect_0_router_004_default_decode
#(
parameter DEFAULT_CHANNEL = 0,
DEFAULT_WR_CHANNEL = -1,
DEFAULT_RD_CHANNEL = -1,
DEFAULT_DESTID = 0
)
(output [82 - 80 : 0] default_destination_id,
output [6-1 : 0] default_wr_channel,
output [6-1 : 0] default_rd_channel,
output [6-1 : 0] default_src_channel
);
assign default_destination_id =
DEFAULT_DESTID[82 - 80 : 0];
generate begin : default_decode
if (DEFAULT_CHANNEL == -1) begin
assign default_src_channel = '0;
end
else begin
assign default_src_channel = 6'b1 << DEFAULT_CHANNEL;
end
end
endgenerate
generate begin : default_decode_rw
if (DEFAULT_RD_CHANNEL == -1) begin
assign default_wr_channel = '0;
assign default_rd_channel = '0;
end
else begin
assign default_wr_channel = 6'b1 << DEFAULT_WR_CHANNEL;
assign default_rd_channel = 6'b1 << DEFAULT_RD_CHANNEL;
end
end
endgenerate
endmodule |
module DE0_NANO_SOC_QSYS_mm_interconnect_0_router_004
(
// -------------------
// Clock & Reset
// -------------------
input clk,
input reset,
// -------------------
// Command Sink (Input)
// -------------------
input sink_valid,
input [96-1 : 0] sink_data,
input sink_startofpacket,
input sink_endofpacket,
output sink_ready,
// -------------------
// Command Source (Output)
// -------------------
output src_valid,
output reg [96-1 : 0] src_data,
output reg [6-1 : 0] src_channel,
output src_startofpacket,
output src_endofpacket,
input src_ready
);
// -------------------------------------------------------
// Local parameters and variables
// -------------------------------------------------------
localparam PKT_ADDR_H = 55;
localparam PKT_ADDR_L = 36;
localparam PKT_DEST_ID_H = 82;
localparam PKT_DEST_ID_L = 80;
localparam PKT_PROTECTION_H = 86;
localparam PKT_PROTECTION_L = 84;
localparam ST_DATA_W = 96;
localparam ST_CHANNEL_W = 6;
localparam DECODER_TYPE = 1;
localparam PKT_TRANS_WRITE = 58;
localparam PKT_TRANS_READ = 59;
localparam PKT_ADDR_W = PKT_ADDR_H-PKT_ADDR_L + 1;
localparam PKT_DEST_ID_W = PKT_DEST_ID_H-PKT_DEST_ID_L + 1;
// -------------------------------------------------------
// Figure out the number of bits to mask off for each slave span
// during address decoding
// -------------------------------------------------------
// -------------------------------------------------------
// Work out which address bits are significant based on the
// address range of the slaves. If the required width is too
// large or too small, we use the address field width instead.
// -------------------------------------------------------
localparam ADDR_RANGE = 64'h0;
localparam RANGE_ADDR_WIDTH = log2ceil(ADDR_RANGE);
localparam OPTIMIZED_ADDR_H = (RANGE_ADDR_WIDTH > PKT_ADDR_W) ||
(RANGE_ADDR_WIDTH == 0) ?
PKT_ADDR_H :
PKT_ADDR_L + RANGE_ADDR_WIDTH - 1;
localparam RG = RANGE_ADDR_WIDTH;
localparam REAL_ADDRESS_RANGE = OPTIMIZED_ADDR_H - PKT_ADDR_L;
reg [PKT_DEST_ID_W-1 : 0] destid;
// -------------------------------------------------------
// Pass almost everything through, untouched
// -------------------------------------------------------
assign sink_ready = src_ready;
assign src_valid = sink_valid;
assign src_startofpacket = sink_startofpacket;
assign src_endofpacket = sink_endofpacket;
wire [6-1 : 0] default_src_channel;
DE0_NANO_SOC_QSYS_mm_interconnect_0_router_004_default_decode the_default_decode(
.default_destination_id (),
.default_wr_channel (),
.default_rd_channel (),
.default_src_channel (default_src_channel)
);
always @* begin
src_data = sink_data;
src_channel = default_src_channel;
// --------------------------------------------------
// DestinationID Decoder
// Sets the channel based on the destination ID.
// --------------------------------------------------
destid = sink_data[PKT_DEST_ID_H : PKT_DEST_ID_L];
if (destid == 0 ) begin
src_channel = 6'b1;
end
end
// --------------------------------------------------
// Ceil(log2()) function
// --------------------------------------------------
function integer log2ceil;
input reg[65:0] val;
reg [65:0] i;
begin
i = 1;
log2ceil = 0;
while (i < val) begin
log2ceil = log2ceil + 1;
i = i << 1;
end
end
endfunction
endmodule |
module DE0_NANO_SOC_QSYS_mm_interconnect_0_rsp_mux
(
// ----------------------
// Sinks
// ----------------------
input sink0_valid,
input [96-1 : 0] sink0_data,
input [6-1: 0] sink0_channel,
input sink0_startofpacket,
input sink0_endofpacket,
output sink0_ready,
input sink1_valid,
input [96-1 : 0] sink1_data,
input [6-1: 0] sink1_channel,
input sink1_startofpacket,
input sink1_endofpacket,
output sink1_ready,
// ----------------------
// Source
// ----------------------
output src_valid,
output [96-1 : 0] src_data,
output [6-1 : 0] src_channel,
output src_startofpacket,
output src_endofpacket,
input src_ready,
// ----------------------
// Clock & Reset
// ----------------------
input clk,
input reset
);
localparam PAYLOAD_W = 96 + 6 + 2;
localparam NUM_INPUTS = 2;
localparam SHARE_COUNTER_W = 1;
localparam PIPELINE_ARB = 0;
localparam ST_DATA_W = 96;
localparam ST_CHANNEL_W = 6;
localparam PKT_TRANS_LOCK = 60;
// ------------------------------------------
// Signals
// ------------------------------------------
wire [NUM_INPUTS - 1 : 0] request;
wire [NUM_INPUTS - 1 : 0] valid;
wire [NUM_INPUTS - 1 : 0] grant;
wire [NUM_INPUTS - 1 : 0] next_grant;
reg [NUM_INPUTS - 1 : 0] saved_grant;
reg [PAYLOAD_W - 1 : 0] src_payload;
wire last_cycle;
reg packet_in_progress;
reg update_grant;
wire [PAYLOAD_W - 1 : 0] sink0_payload;
wire [PAYLOAD_W - 1 : 0] sink1_payload;
assign valid[0] = sink0_valid;
assign valid[1] = sink1_valid;
// ------------------------------------------
// ------------------------------------------
// Grant Logic & Updates
// ------------------------------------------
// ------------------------------------------
reg [NUM_INPUTS - 1 : 0] lock;
always @* begin
lock[0] = sink0_data[60];
lock[1] = sink1_data[60];
end
assign last_cycle = src_valid & src_ready & src_endofpacket & ~(|(lock & grant));
// ------------------------------------------
// We're working on a packet at any time valid is high, except
// when this is the endofpacket.
// ------------------------------------------
always @(posedge clk or posedge reset) begin
if (reset) begin
packet_in_progress <= 1'b0;
end
else begin
if (last_cycle)
packet_in_progress <= 1'b0;
else if (src_valid)
packet_in_progress <= 1'b1;
end
end
// ------------------------------------------
// Shares
//
// Special case: all-equal shares _should_ be optimized into assigning a
// constant to next_grant_share.
// Special case: all-1's shares _should_ result in the share counter
// being optimized away.
// ------------------------------------------
// Input | arb shares | counter load value
// 0 | 1 | 0
// 1 | 1 | 0
wire [SHARE_COUNTER_W - 1 : 0] share_0 = 1'd0;
wire [SHARE_COUNTER_W - 1 : 0] share_1 = 1'd0;
// ------------------------------------------
// Choose the share value corresponding to the grant.
// ------------------------------------------
reg [SHARE_COUNTER_W - 1 : 0] next_grant_share;
always @* begin
next_grant_share =
share_0 & { SHARE_COUNTER_W {next_grant[0]} } |
share_1 & { SHARE_COUNTER_W {next_grant[1]} };
end
// ------------------------------------------
// Flag to indicate first packet of an arb sequence.
// ------------------------------------------
wire grant_changed = ~packet_in_progress && ~(|(saved_grant & valid));
reg first_packet_r;
wire first_packet = grant_changed | first_packet_r;
always @(posedge clk or posedge reset) begin
if (reset) begin
first_packet_r <= 1'b0;
end
else begin
if (update_grant)
first_packet_r <= 1'b1;
else if (last_cycle)
first_packet_r <= 1'b0;
else if (grant_changed)
first_packet_r <= 1'b1;
end
end
// ------------------------------------------
// Compute the next share-count value.
// ------------------------------------------
reg [SHARE_COUNTER_W - 1 : 0] p1_share_count;
reg [SHARE_COUNTER_W - 1 : 0] share_count;
reg share_count_zero_flag;
always @* begin
if (first_packet) begin
p1_share_count = next_grant_share;
end
else begin
// Update the counter, but don't decrement below 0.
p1_share_count = share_count_zero_flag ? '0 : share_count - 1'b1;
end
end
// ------------------------------------------
// Update the share counter and share-counter=zero flag.
// ------------------------------------------
always @(posedge clk or posedge reset) begin
if (reset) begin
share_count <= '0;
share_count_zero_flag <= 1'b1;
end
else begin
if (last_cycle) begin
share_count <= p1_share_count;
share_count_zero_flag <= (p1_share_count == '0);
end
end
end
// ------------------------------------------
// For each input, maintain a final_packet signal which goes active for the
// last packet of a full-share packet sequence. Example: if I have 4
// shares and I'm continuously requesting, final_packet is active in the
// 4th packet.
// ------------------------------------------
wire final_packet_0 = 1'b1;
wire final_packet_1 = 1'b1;
// ------------------------------------------
// Concatenate all final_packet signals (wire or reg) into a handy vector.
// ------------------------------------------
wire [NUM_INPUTS - 1 : 0] final_packet = {
final_packet_1,
final_packet_0
};
// ------------------------------------------
// ------------------------------------------
wire p1_done = |(final_packet & grant);
// ------------------------------------------
// Flag for the first cycle of packets within an
// arb sequence
// ------------------------------------------
reg first_cycle;
always @(posedge clk, posedge reset) begin
if (reset)
first_cycle <= 0;
else
first_cycle <= last_cycle && ~p1_done;
end
always @* begin
update_grant = 0;
// ------------------------------------------
// No arbitration pipeline, update grant whenever
// the current arb winner has consumed all shares,
// or all requests are low
// ------------------------------------------
update_grant = (last_cycle && p1_done) || (first_cycle && ~(|valid));
update_grant = last_cycle;
end
wire save_grant;
assign save_grant = 1;
assign grant = next_grant;
always @(posedge clk, posedge reset) begin
if (reset)
saved_grant <= '0;
else if (save_grant)
saved_grant <= next_grant;
end
// ------------------------------------------
// ------------------------------------------
// Arbitrator
// ------------------------------------------
// ------------------------------------------
// ------------------------------------------
// Create a request vector that stays high during
// the packet for unpipelined arbitration.
//
// The pipelined arbitration scheme does not require
// request to be held high during the packet.
// ------------------------------------------
assign request = valid;
altera_merlin_arbitrator
#(
.NUM_REQUESTERS(NUM_INPUTS),
.SCHEME ("no-arb"),
.PIPELINE (0)
) arb (
.clk (clk),
.reset (reset),
.request (request),
.grant (next_grant),
.save_top_priority (src_valid),
.increment_top_priority (update_grant)
);
// ------------------------------------------
// ------------------------------------------
// Mux
//
// Implemented as a sum of products.
// ------------------------------------------
// ------------------------------------------
assign sink0_ready = src_ready && grant[0];
assign sink1_ready = src_ready && grant[1];
assign src_valid = |(grant & valid);
always @* begin
src_payload =
sink0_payload & {PAYLOAD_W {grant[0]} } |
sink1_payload & {PAYLOAD_W {grant[1]} };
end
// ------------------------------------------
// Mux Payload Mapping
// ------------------------------------------
assign sink0_payload = {sink0_channel,sink0_data,
sink0_startofpacket,sink0_endofpacket};
assign sink1_payload = {sink1_channel,sink1_data,
sink1_startofpacket,sink1_endofpacket};
assign {src_channel,src_data,src_startofpacket,src_endofpacket} = src_payload;
endmodule |
module DE0_NANO_SOC_QSYS_mm_interconnect_0_cmd_demux_001
(
// -------------------
// Sink
// -------------------
input [6-1 : 0] sink_valid,
input [96-1 : 0] sink_data, // ST_DATA_W=96
input [6-1 : 0] sink_channel, // ST_CHANNEL_W=6
input sink_startofpacket,
input sink_endofpacket,
output sink_ready,
// -------------------
// Sources
// -------------------
output reg src0_valid,
output reg [96-1 : 0] src0_data, // ST_DATA_W=96
output reg [6-1 : 0] src0_channel, // ST_CHANNEL_W=6
output reg src0_startofpacket,
output reg src0_endofpacket,
input src0_ready,
output reg src1_valid,
output reg [96-1 : 0] src1_data, // ST_DATA_W=96
output reg [6-1 : 0] src1_channel, // ST_CHANNEL_W=6
output reg src1_startofpacket,
output reg src1_endofpacket,
input src1_ready,
output reg src2_valid,
output reg [96-1 : 0] src2_data, // ST_DATA_W=96
output reg [6-1 : 0] src2_channel, // ST_CHANNEL_W=6
output reg src2_startofpacket,
output reg src2_endofpacket,
input src2_ready,
output reg src3_valid,
output reg [96-1 : 0] src3_data, // ST_DATA_W=96
output reg [6-1 : 0] src3_channel, // ST_CHANNEL_W=6
output reg src3_startofpacket,
output reg src3_endofpacket,
input src3_ready,
output reg src4_valid,
output reg [96-1 : 0] src4_data, // ST_DATA_W=96
output reg [6-1 : 0] src4_channel, // ST_CHANNEL_W=6
output reg src4_startofpacket,
output reg src4_endofpacket,
input src4_ready,
output reg src5_valid,
output reg [96-1 : 0] src5_data, // ST_DATA_W=96
output reg [6-1 : 0] src5_channel, // ST_CHANNEL_W=6
output reg src5_startofpacket,
output reg src5_endofpacket,
input src5_ready,
// -------------------
// Clock & Reset
// -------------------
(*altera_attribute = "-name MESSAGE_DISABLE 15610" *) // setting message suppression on clk
input clk,
(*altera_attribute = "-name MESSAGE_DISABLE 15610" *) // setting message suppression on reset
input reset
);
localparam NUM_OUTPUTS = 6;
wire [NUM_OUTPUTS - 1 : 0] ready_vector;
// -------------------
// Demux
// -------------------
always @* begin
src0_data = sink_data;
src0_startofpacket = sink_startofpacket;
src0_endofpacket = sink_endofpacket;
src0_channel = sink_channel >> NUM_OUTPUTS;
src0_valid = sink_channel[0] && sink_valid[0];
src1_data = sink_data;
src1_startofpacket = sink_startofpacket;
src1_endofpacket = sink_endofpacket;
src1_channel = sink_channel >> NUM_OUTPUTS;
src1_valid = sink_channel[1] && sink_valid[1];
src2_data = sink_data;
src2_startofpacket = sink_startofpacket;
src2_endofpacket = sink_endofpacket;
src2_channel = sink_channel >> NUM_OUTPUTS;
src2_valid = sink_channel[2] && sink_valid[2];
src3_data = sink_data;
src3_startofpacket = sink_startofpacket;
src3_endofpacket = sink_endofpacket;
src3_channel = sink_channel >> NUM_OUTPUTS;
src3_valid = sink_channel[3] && sink_valid[3];
src4_data = sink_data;
src4_startofpacket = sink_startofpacket;
src4_endofpacket = sink_endofpacket;
src4_channel = sink_channel >> NUM_OUTPUTS;
src4_valid = sink_channel[4] && sink_valid[4];
src5_data = sink_data;
src5_startofpacket = sink_startofpacket;
src5_endofpacket = sink_endofpacket;
src5_channel = sink_channel >> NUM_OUTPUTS;
src5_valid = sink_channel[5] && sink_valid[5];
end
// -------------------
// Backpressure
// -------------------
assign ready_vector[0] = src0_ready;
assign ready_vector[1] = src1_ready;
assign ready_vector[2] = src2_ready;
assign ready_vector[3] = src3_ready;
assign ready_vector[4] = src4_ready;
assign ready_vector[5] = src5_ready;
assign sink_ready = |(sink_channel & ready_vector);
endmodule |
module aes_tb_top;
import uvm_pkg::*;
import aes_pkg::*;
//Interface declaration
aes_if vif();
/*
input [7:0] key_byte, state_byte,
input clk,rst,enable,
output reg [7:0] state_out_byte,
output reg load,ready
*/
//Connects the Interface to the DUT
AES_Encrypt aes(
.key_byte(vif.in_key_byte),
.state_byte(vif.in_state_byte),
.clk(vif.sig_clock),
.rst(vif.sig_rst),
.enable(vif.sig_enable),
.state_out_byte(vif.out_state_byte),
.load(vif.sig_load),
.ready(vif.sig_ready)
);
initial begin
//Registers the Interface in the configuration block so that other
//blocks can use it
uvm_resource_db#(virtual aes_if)::set
(.scope("ifs"), .name("aes_if"), .val(vif));
//Executes the test
run_test();
end
//Variable initialization
initial begin
vif.sig_clock <= 1'b1;
end
//Clock generation
always
#5 vif.sig_clock = ~vif.sig_clock;
endmodule |
module tone_mapping
#(
parameter W = 10
)
(
input wire clk,
input wire reset_n,
input wire sop,
input wire eop,
input wire valid,
input wire [W-1: 0] data,
input wire [7:0] reg_parallax_corr,
output wire [W-3: 0] data_o
);
wire [W-1: 0] min;
wire [W-1: 0] max;
wire [W-1: 0] max_min_diff;
reg [W-1: 0] data_min_diff;
reg [(W-1)*2:0] data_min_diff_mult;
//reg [W-3: 0] data_min_div;
min_max_detector
#(
.W ( W )
)
min_max_detector_inst
(
.clk ( clk ),
.reset_n ( reset_n ),
.sop ( sop ),
.eop ( eop ),
.valid ( valid ),
.data ( data ),
.min ( min ),
.max ( max ),
.max_min_diff ( max_min_diff ),
.reg_parallax_corr (reg_parallax_corr)
);
always @( posedge clk )
begin
data_min_diff <= data - min;
data_min_diff_mult <= data_min_diff*255;
end
tone_mapping_divider tone_mapping_divider_inst
(
.clock ( clk ),
.denom ( max_min_diff ),
.numer ( data_min_diff_mult ),
.quotient ( data_o ),
.remain ( )
);
endmodule |
module parallax_fix
(
input wire clk,
input wire reset_n,
input wire [7 : 0] parallax_corr,
input wire [ 7: 0] raw_data_0,
input wire [ 7: 0] raw_data_1,
input wire raw_data_valid,
input wire raw_data_sop,
input wire raw_data_eop,
output wire [ 7: 0] prlx_fxd_data_0,
output wire [ 7: 0] prlx_fxd_data_1,
output reg prlx_fxd_data_valid,
output reg prlx_fxd_data_sop,
output reg prlx_fxd_data_eop
);
reg [11: 0] cnt_wr;
reg [11: 0] cnt_rd;
wire wr_0;
wire rd_0;
wire wr_1;
wire rd_1;
wire [7 :0] q_0;
wire [7 :0] q_1;
wire w_prlx_fxd_data_valid;
wire w_prlx_fxd_data_sop;
wire w_prlx_fxd_data_eop;
always @( posedge clk or negedge reset_n )
if ( !reset_n )
cnt_wr <= 12'h0;
else
if ( raw_data_valid )
cnt_wr <= cnt_wr + 1'h1;
else
cnt_wr <= 12'h0;
always @( posedge clk or negedge reset_n )
if ( !reset_n )
cnt_rd <= 12'h0;
else
if ( cnt_rd == 12'd1280 )
cnt_rd <= 12'h0;
else if ( cnt_wr == parallax_corr )
cnt_rd <= 1'h1;
else if ( cnt_rd != 12'h0 )
cnt_rd <= cnt_rd + 1'h1;
assign wr_1 = raw_data_valid && ( cnt_wr < (1280-parallax_corr) );
assign wr_0 = raw_data_valid && ( cnt_wr >= parallax_corr );
assign rd_0 = ( cnt_rd > 0 ) ? 1'h1: 1'h0;
fifo_parallax_fix fifo_parallax_fix_0
(
.clock ( clk ),
.data ( raw_data_0 ),
.rdreq ( rd_0 ),
.wrreq ( wr_0 ),
.empty (),
.full (),
.q ( q_0 ),
.usedw ()
);
fifo_parallax_fix fifo_parallax_fix_1
(
.clock ( clk ),
.data ( raw_data_1 ),
.rdreq ( rd_0 ),
.wrreq ( wr_1 ),
.empty (),
.full (),
.q ( q_1 ),
.usedw ()
);
assign prlx_fxd_data_0 = ( cnt_rd < (1280-parallax_corr) ) ? q_0 : 7'h1;
assign prlx_fxd_data_1 = ( cnt_rd < (1280-parallax_corr) ) ? q_1 : 7'h1;
assign w_prlx_fxd_data_valid = ( cnt_rd > 12'h0 ) ? 1'h1 : 7'h0;
assign w_prlx_fxd_data_sop = ( cnt_rd == 12'h1 ) ? 1'h1 : 7'h0;
assign w_prlx_fxd_data_eop = ( cnt_rd == 12'd1280 ) ? 1'h1 : 7'h0;
always @( posedge clk )
begin
prlx_fxd_data_valid <= w_prlx_fxd_data_valid ;
prlx_fxd_data_sop <= w_prlx_fxd_data_sop ;
prlx_fxd_data_eop <= w_prlx_fxd_data_eop ;
end
/*
assign prlx_fxd_data_valid
assign prlx_fxd_data_sop
assign prlx_fxd_data_eop*/
endmodule |
module gamma_correction
(
input wire clk,
input wire reset_n,
input wire [ 7: 0] raw_data_0,
input wire [ 7: 0] raw_data_1,
input wire raw_data_valid,
input wire raw_data_sop,
input wire raw_data_eop,
output wire [ 7: 0] addr_0,
input wire [ 7: 0] data_0,
output wire [ 7: 0] addr_1,
input wire [ 7: 0] data_1,
output wire [ 7: 0] gamma_data_0,
output wire [ 7: 0] gamma_data_1,
output wire gamma_data_valid,
output wire gamma_data_sop,
output wire gamma_data_eop
);
assign addr_0 = raw_data_0;
assign addr_1 = raw_data_1;
assign gamma_data_0 = data_0;
assign gamma_data_1 = data_1;
delay_rg
#(
.W ( 3 ),
.D ( 1 )
)
delay_strobes
(
.clk ( clk ),
.data_in ( { raw_data_sop, raw_data_eop, raw_data_valid } ),
.data_out ( { gamma_data_sop, gamma_data_eop, gamma_data_valid } )
);
endmodule |
module wrp_HDR_algorithm
#(
parameter DATA_WIDTH = 32
)
(
//clocks & reset
input wire clk,
//
input wire asi_snk_0_valid_i,
input wire [DATA_WIDTH-1: 0] asi_snk_0_data_r_i,
input wire [DATA_WIDTH-1: 0] asi_snk_0_data_g_i,
input wire [DATA_WIDTH-1: 0] asi_snk_0_data_b_i,
input wire asi_snk_0_startofpacket_i,
input wire asi_snk_0_endofpacket_i,
input wire [DATA_WIDTH-1: 0] asi_snk_1_data_r_i,
input wire [DATA_WIDTH-1: 0] asi_snk_1_data_g_i,
input wire [DATA_WIDTH-1: 0] asi_snk_1_data_b_i,
output logic aso_src_valid_o,
output logic [DATA_WIDTH+1: 0] aso_src_data_r_o,
output logic [DATA_WIDTH+1: 0] aso_src_data_g_o,
output logic [DATA_WIDTH+1: 0] aso_src_data_b_o,
output logic aso_src_startofpacket_o,
output logic aso_src_endofpacket_o
);
//
HDR_algorithm
#(
.DATA_WIDTH ( DATA_WIDTH )
)
HDR_algorithm_r
(
.clk ( clk ),
.data_i0 ( asi_snk_0_data_r_i ),
.data_i1 ( asi_snk_1_data_r_i ),
.data_o ( aso_src_data_r_o )
);
HDR_algorithm
#(
.DATA_WIDTH ( DATA_WIDTH )
)
HDR_algorithm_g
(
.clk ( clk ),
.data_i0 ( asi_snk_0_data_g_i ),
.data_i1 ( asi_snk_1_data_g_i ),
.data_o ( aso_src_data_g_o )
);
HDR_algorithm
#(
.DATA_WIDTH ( DATA_WIDTH )
)
HDR_algorithm_b
(
.clk ( clk ),
.data_i0 ( asi_snk_0_data_b_i ),
.data_i1 ( asi_snk_1_data_b_i ),
.data_o ( aso_src_data_b_o )
);
delay_rg
#(
.W ( 3 ),
.D ( 21+2-8+5 )
)
delay_weight
(
.clk ( clk ),
.data_in ( {asi_snk_0_endofpacket_i, asi_snk_0_startofpacket_i, asi_snk_0_valid_i } ),
.data_out ( {aso_src_endofpacket_o, aso_src_startofpacket_o, aso_src_valid_o } )
);
endmodule |
module calc_weight_coef
#(
parameter DATA_WIDTH = 32
)
(
//clocks & reset
input wire clk,
// input wire reset_n,
//
input wire [DATA_WIDTH-1: 0] Z,
output wire [DATA_WIDTH-1: 0] weight_coef
);
localparam Zmin = 0;
localparam Zmax = 255;
localparam Zhalf_summ = (Zmax + Zmin)/2;
reg [DATA_WIDTH: 0] Zsumm;
reg [DATA_WIDTH-1: 0] weight_coef_tmp;
always @( posedge clk )
if ( Z <= Zhalf_summ )
weight_coef_tmp = Z - Zmin;
else
weight_coef_tmp = Zmax - Z;
assign weight_coef = ( weight_coef_tmp != 0 ) ? weight_coef_tmp : 1;
endmodule |
module wrp_tone_mapping
#(
parameter W = 10
)
(
input wire clk,
input wire reset_n,
input wire enable,
input wire sop_i,
input wire eop_i,
input wire valid_i,
input wire [W-1: 0] data_r_i,
input wire [W-1: 0] data_g_i,
input wire [W-1: 0] data_b_i,
input wire [7:0] reg_parallax_corr,
output reg [W-3: 0] data_r_o,
output reg [W-3: 0] data_g_o,
output reg [W-3: 0] data_b_o,
output reg sop_o,
output reg eop_o,
output reg valid_o
);
wire sop;
wire eop;
wire valid;
wire [W-3: 0] data_r;
wire [W-3: 0] data_g;
wire [W-3: 0] data_b;
tone_mapping
#(
.W ( W )
)
tone_mapping_r
(
.clk ( clk ),
.reset_n ( reset_n ),
.sop ( sop_i ),
.eop ( eop_i ),
.valid ( valid_i ),
.data ( data_r_i ),
.data_o ( data_r ),
.reg_parallax_corr ( reg_parallax_corr )
);
tone_mapping
#(
.W ( W )
)
tone_mapping_g
(
.clk ( clk ),
.reset_n ( reset_n ),
.sop ( sop_i ),
.eop ( eop_i ),
.valid ( valid_i ),
.data ( data_g_i ),
.data_o ( data_g ),
.reg_parallax_corr ( reg_parallax_corr )
);
tone_mapping
#(
.W ( W )
)
tone_mapping_b
(
.clk ( clk ),
.reset_n ( reset_n ),
.sop ( sop_i ),
.eop ( eop_i ),
.valid ( valid_i ),
.data ( data_b_i ),
.data_o ( data_b ),
.reg_parallax_corr ( reg_parallax_corr )
);
delay_rg
#(
.W ( 3 ),
.D ( 20 )
)
delay_strobes
(
.clk ( clk ),
.data_in ( { sop_i, eop_i, valid_i } ),
.data_out ( { sop, eop, valid } )
);
always @( posedge clk )
if ( enable )
begin
data_r_o <= data_r;
data_g_o <= data_g;
data_b_o <= data_b;
sop_o <= sop;
eop_o <= eop;
valid_o <= valid;
end
else
begin
data_r_o <= data_r_i[8:1];
data_g_o <= data_g_i[8:1];
data_b_o <= data_b_i[8:1];
sop_o <= sop_i;
eop_o <= eop_i;
valid_o <= valid_i ;
end
endmodule |
module HDR_algorithm
#(
parameter DATA_WIDTH = 32
)
(
//clocks & reset
input wire clk,
//
input wire [DATA_WIDTH-1: 0] data_i0,
input wire [DATA_WIDTH-1: 0] data_i1,
output reg [DATA_WIDTH+1: 0] data_o
);
//
wire [DATA_WIDTH-1: 0] weight_coef_0;
wire [DATA_WIDTH-1: 0] weight_coef_1;
reg [DATA_WIDTH: 0] weight_coef_sum;
wire [DATA_WIDTH: 0] weight_coef_sum_delay;
wire [DATA_WIDTH-1: 0] bright_delay_0;
wire [DATA_WIDTH-1: 0] bright_delay_1;
reg [(DATA_WIDTH*2): 0] mult_0;
reg [(DATA_WIDTH*2): 0] mult_1;
reg [(DATA_WIDTH*2)+1: 0] E;
wire [17: 0] quotient;
wire [ 8: 0] remain;
delay_rg
#(
.W ( DATA_WIDTH ),
.D ( 2 )
)
delay_rg_0
(
.clk ( clk ),
.data_in ( data_i0 ),
.data_out ( bright_delay_0)
);
delay_rg
#(
.W ( DATA_WIDTH ),
.D ( 2 )
)
delay_rg_1
(
.clk ( clk ),
.data_in ( data_i1 ),
.data_out ( bright_delay_1)
);
calc_weight_coef
#(
.DATA_WIDTH ( DATA_WIDTH )
)
calc_weight_coef_0
(
.clk ( clk ),
.Z ( data_i0 ),
.weight_coef ( weight_coef_0 )
);
calc_weight_coef
#(
.DATA_WIDTH ( DATA_WIDTH )
)
calc_weight_coef_1
(
.clk ( clk ),
.Z ( data_i1 ),
.weight_coef ( weight_coef_1 )
);
delay_rg
#(
.W ( DATA_WIDTH+1 ),
.D ( 2 )
)
delay_weight
(
.clk ( clk ),
.data_in ( weight_coef_sum ),
.data_out ( weight_coef_sum_delay )
);
always @( posedge clk )
weight_coef_sum <= weight_coef_0 + weight_coef_1;
always @( posedge clk )
begin
mult_0 <= weight_coef_sum*bright_delay_0;
mult_1 <= weight_coef_sum*bright_delay_1;
end
always @( posedge clk )
E = mult_0 + mult_1;
HDR_divider HDR_divider_inst
(
.clock ( clk ),
.denom ( weight_coef_sum_delay ),
.numer ( E ),
.quotient ( quotient ),
.remain ( remain )
);
always @( posedge clk )
if ( remain > 0 )
data_o <= quotient[9:0] + 1'h1;
else
data_o <= quotient[9:0];
endmodule |
module RGB2HSV
(
input wire clk,
input wire rst,
input wire [ 7: 0] r,
input wire [ 7: 0] g,
input wire [ 7: 0] b,
output reg [ 8: 0] H,
output wire [10: 0] S,
output wire [ 7: 0] V
);
localparam DIV_DELAY = 9;
//st0
reg [ 7: 0] max;
reg [ 7: 0] min;
reg [ 7: 0] st1_r;
reg [ 7: 0] st1_g;
reg [ 7: 0] st1_b;
reg [ 4: 0] chz;
wire[ 4: 0] chz_delay;
wire[ 7: 0] max_for_div;
//st1
reg [ 7: 0] max_min_sub_H;
reg signed [18: 0] sub_H;
wire signed [17: 0] div_min_max_S;
reg signed [18: 0] mult_2048_max_V;
wire [7 : 0] remain_S;
//st2
wire signed [17: 0] div_sub_maxmin_H;
wire [ 7: 0] remain_H;
reg [11: 0] sub_1_div_S;
//st3
reg [23: 0] mult60_H;
wire signed [8: 0] mult60_H_round_H;
//st4
// reg [8:0] H;
//st0
//поиск минимума и максимума
always @( posedge clk /*or posedge rst*/ )
if ( ( r >= g ) && ( r >= b ) )
max <= r;
else if ( ( g >= r ) && ( g >= b ) )
max <= g;
else if ( ( b >= r ) && ( b >= g ) )
max <= b;
always @( posedge clk /*or posedge rst*/ )
if ( ( r <= g ) && ( r <= b ) )
min <= r;
else if ( ( g <= r ) && ( g <= b ) )
min <= g;
else if ( ( b <= r ) && ( b <= g ) )
min <= b;
always @( posedge clk )
begin
st1_r <= r;
st1_g <= g;
st1_b <= b;
end
//st1
always @( posedge clk )
max_min_sub_H <= max - min;
always @( posedge clk )
if ( ( max == st1_r ) )
sub_H <= {st1_g,10'd0} - {st1_b,10'd0};
else if ( max == st1_g )
sub_H <= {st1_b,10'd0} - {st1_r,10'd0};
else if ( max == st1_b )
sub_H <= {st1_r,10'd0} - {st1_g,10'd0};
always @( posedge clk )
if ( min == max )
chz <= 5'b10000;
else if ( ( max == st1_r ) && ( st1_g >= st1_b ) )
chz <= 5'b01000;
else if( ( max == st1_r ) && ( st1_g < st1_b ) )
chz <= 5'b00100;
else if ( max == st1_g )
chz <= 5'b00010;
else if ( max == st1_b )
chz <= 5'b00001;
assign max_for_div = ( ( max == 0 ) ? 1 : max );
rgb2hsv_divider_S rgb2hsv_divider_S_inst
(
.clock ( clk ),
.denom ( max_for_div ),
.numer ( { min, 11'h0 } ),
.quotient ( div_min_max_S ),
.remain ( remain_S )
);
/*
always @( posedge clk )
mult_2048_max_V <= { max, 11'h0 };
*/
//st2
delay_rg
#(
.W ( 5 ),
.D ( 6+DIV_DELAY )
)
delay_rg_1
(
.clk ( clk ),
.data_in ( chz ),
.data_out ( chz_delay )
);
rgb2hsv_divider0 rgb2hsv_divider0_inst
(
.clock ( clk ),
.denom ( max_min_sub_H ),
.numer ( sub_H ),
.quotient ( div_sub_maxmin_H ),
.remain ( remain_H )
);
always @( posedge clk )
sub_1_div_S <= ( remain_S[7] == 1 ) ? ( 2047 - div_min_max_S[11:0] ) : ( 2048 - div_min_max_S[11:0] );
//st3
always @( posedge clk )
mult60_H <= ( remain_H[7] == 1 ) ? ( (div_sub_maxmin_H + 1) * 60 ) : ( div_sub_maxmin_H * 60);
rounder
#(
.BEFORE_ROUND ( 24 ),
.LOW_BIT ( 10 ),
.AFTER_ROUND ( 9 )
)
rounder_inst
(
.clk ( clk ),
.reset_b ( !rst ),
.data_in ( mult60_H ),
.data_out ( mult60_H_round_H )
);
//st4
always @( posedge clk )
case ( chz_delay )
5'b10000: H <= '0;
5'b01000: H <= mult60_H_round_H;
5'b00100: H <= mult60_H_round_H + 360;
5'b00010: H <= mult60_H_round_H + 120;
5'b00001: H <= mult60_H_round_H + 240;
default: H <= '0;
endcase
delay_rg
#(
.W ( 11 ),
.D ( 6 )
)
delay_rg_S
(
.clk ( clk ),
.data_in ( ( sub_1_div_S[11]?2047:sub_1_div_S[10:0] ) ),
.data_out ( S )
);
delay_rg
#(
.W ( 8 ),
.D ( 8 + DIV_DELAY )
)
delay_rg_V
(
.clk ( clk ),
.data_in ( max ),
.data_out ( V )
);
endmodule |
module jonpaolo02_async_fifo (
input [7:0] io_in,
output [7:0] io_out
);
async_fifo #(.WIDTH(3), .DEPTH(8)) top
(.rst(io_in[2]),
.wclk(io_in[0]), .we(io_in[3]),
.full(io_out[3]),
.wdata(io_in[7:5]),
.rclk(io_in[1]), .re(io_in[4]),
.empty(io_out[4]),
.rdata(io_out[7:5]));
endmodule |
module lms_ctr_mm_interconnect_0_cmd_mux
(
// ----------------------
// Sinks
// ----------------------
input sink0_valid,
input [95-1 : 0] sink0_data,
input [11-1: 0] sink0_channel,
input sink0_startofpacket,
input sink0_endofpacket,
output sink0_ready,
// ----------------------
// Source
// ----------------------
output src_valid,
output [95-1 : 0] src_data,
output [11-1 : 0] src_channel,
output src_startofpacket,
output src_endofpacket,
input src_ready,
// ----------------------
// Clock & Reset
// ----------------------
input clk,
input reset
);
localparam PAYLOAD_W = 95 + 11 + 2;
localparam NUM_INPUTS = 1;
localparam SHARE_COUNTER_W = 1;
localparam PIPELINE_ARB = 1;
localparam ST_DATA_W = 95;
localparam ST_CHANNEL_W = 11;
localparam PKT_TRANS_LOCK = 57;
assign src_valid = sink0_valid;
assign src_data = sink0_data;
assign src_channel = sink0_channel;
assign src_startofpacket = sink0_startofpacket;
assign src_endofpacket = sink0_endofpacket;
assign sink0_ready = src_ready;
endmodule |
module lms_ctr_mm_interconnect_0_cmd_demux
(
// -------------------
// Sink
// -------------------
input [1-1 : 0] sink_valid,
input [95-1 : 0] sink_data, // ST_DATA_W=95
input [11-1 : 0] sink_channel, // ST_CHANNEL_W=11
input sink_startofpacket,
input sink_endofpacket,
output sink_ready,
// -------------------
// Sources
// -------------------
output reg src0_valid,
output reg [95-1 : 0] src0_data, // ST_DATA_W=95
output reg [11-1 : 0] src0_channel, // ST_CHANNEL_W=11
output reg src0_startofpacket,
output reg src0_endofpacket,
input src0_ready,
output reg src1_valid,
output reg [95-1 : 0] src1_data, // ST_DATA_W=95
output reg [11-1 : 0] src1_channel, // ST_CHANNEL_W=11
output reg src1_startofpacket,
output reg src1_endofpacket,
input src1_ready,
output reg src2_valid,
output reg [95-1 : 0] src2_data, // ST_DATA_W=95
output reg [11-1 : 0] src2_channel, // ST_CHANNEL_W=11
output reg src2_startofpacket,
output reg src2_endofpacket,
input src2_ready,
output reg src3_valid,
output reg [95-1 : 0] src3_data, // ST_DATA_W=95
output reg [11-1 : 0] src3_channel, // ST_CHANNEL_W=11
output reg src3_startofpacket,
output reg src3_endofpacket,
input src3_ready,
output reg src4_valid,
output reg [95-1 : 0] src4_data, // ST_DATA_W=95
output reg [11-1 : 0] src4_channel, // ST_CHANNEL_W=11
output reg src4_startofpacket,
output reg src4_endofpacket,
input src4_ready,
output reg src5_valid,
output reg [95-1 : 0] src5_data, // ST_DATA_W=95
output reg [11-1 : 0] src5_channel, // ST_CHANNEL_W=11
output reg src5_startofpacket,
output reg src5_endofpacket,
input src5_ready,
output reg src6_valid,
output reg [95-1 : 0] src6_data, // ST_DATA_W=95
output reg [11-1 : 0] src6_channel, // ST_CHANNEL_W=11
output reg src6_startofpacket,
output reg src6_endofpacket,
input src6_ready,
output reg src7_valid,
output reg [95-1 : 0] src7_data, // ST_DATA_W=95
output reg [11-1 : 0] src7_channel, // ST_CHANNEL_W=11
output reg src7_startofpacket,
output reg src7_endofpacket,
input src7_ready,
output reg src8_valid,
output reg [95-1 : 0] src8_data, // ST_DATA_W=95
output reg [11-1 : 0] src8_channel, // ST_CHANNEL_W=11
output reg src8_startofpacket,
output reg src8_endofpacket,
input src8_ready,
output reg src9_valid,
output reg [95-1 : 0] src9_data, // ST_DATA_W=95
output reg [11-1 : 0] src9_channel, // ST_CHANNEL_W=11
output reg src9_startofpacket,
output reg src9_endofpacket,
input src9_ready,
output reg src10_valid,
output reg [95-1 : 0] src10_data, // ST_DATA_W=95
output reg [11-1 : 0] src10_channel, // ST_CHANNEL_W=11
output reg src10_startofpacket,
output reg src10_endofpacket,
input src10_ready,
// -------------------
// Clock & Reset
// -------------------
(*altera_attribute = "-name MESSAGE_DISABLE 15610" *) // setting message suppression on clk
input clk,
(*altera_attribute = "-name MESSAGE_DISABLE 15610" *) // setting message suppression on reset
input reset
);
localparam NUM_OUTPUTS = 11;
wire [NUM_OUTPUTS - 1 : 0] ready_vector;
// -------------------
// Demux
// -------------------
always @* begin
src0_data = sink_data;
src0_startofpacket = sink_startofpacket;
src0_endofpacket = sink_endofpacket;
src0_channel = sink_channel >> NUM_OUTPUTS;
src0_valid = sink_channel[0] && sink_valid;
src1_data = sink_data;
src1_startofpacket = sink_startofpacket;
src1_endofpacket = sink_endofpacket;
src1_channel = sink_channel >> NUM_OUTPUTS;
src1_valid = sink_channel[1] && sink_valid;
src2_data = sink_data;
src2_startofpacket = sink_startofpacket;
src2_endofpacket = sink_endofpacket;
src2_channel = sink_channel >> NUM_OUTPUTS;
src2_valid = sink_channel[2] && sink_valid;
src3_data = sink_data;
src3_startofpacket = sink_startofpacket;
src3_endofpacket = sink_endofpacket;
src3_channel = sink_channel >> NUM_OUTPUTS;
src3_valid = sink_channel[3] && sink_valid;
src4_data = sink_data;
src4_startofpacket = sink_startofpacket;
src4_endofpacket = sink_endofpacket;
src4_channel = sink_channel >> NUM_OUTPUTS;
src4_valid = sink_channel[4] && sink_valid;
src5_data = sink_data;
src5_startofpacket = sink_startofpacket;
src5_endofpacket = sink_endofpacket;
src5_channel = sink_channel >> NUM_OUTPUTS;
src5_valid = sink_channel[5] && sink_valid;
src6_data = sink_data;
src6_startofpacket = sink_startofpacket;
src6_endofpacket = sink_endofpacket;
src6_channel = sink_channel >> NUM_OUTPUTS;
src6_valid = sink_channel[6] && sink_valid;
src7_data = sink_data;
src7_startofpacket = sink_startofpacket;
src7_endofpacket = sink_endofpacket;
src7_channel = sink_channel >> NUM_OUTPUTS;
src7_valid = sink_channel[7] && sink_valid;
src8_data = sink_data;
src8_startofpacket = sink_startofpacket;
src8_endofpacket = sink_endofpacket;
src8_channel = sink_channel >> NUM_OUTPUTS;
src8_valid = sink_channel[8] && sink_valid;
src9_data = sink_data;
src9_startofpacket = sink_startofpacket;
src9_endofpacket = sink_endofpacket;
src9_channel = sink_channel >> NUM_OUTPUTS;
src9_valid = sink_channel[9] && sink_valid;
src10_data = sink_data;
src10_startofpacket = sink_startofpacket;
src10_endofpacket = sink_endofpacket;
src10_channel = sink_channel >> NUM_OUTPUTS;
src10_valid = sink_channel[10] && sink_valid;
end
// -------------------
// Backpressure
// -------------------
assign ready_vector[0] = src0_ready;
assign ready_vector[1] = src1_ready;
assign ready_vector[2] = src2_ready;
assign ready_vector[3] = src3_ready;
assign ready_vector[4] = src4_ready;
assign ready_vector[5] = src5_ready;
assign ready_vector[6] = src6_ready;
assign ready_vector[7] = src7_ready;
assign ready_vector[8] = src8_ready;
assign ready_vector[9] = src9_ready;
assign ready_vector[10] = src10_ready;
assign sink_ready = |(sink_channel & ready_vector);
endmodule |
module lms_ctr_mm_interconnect_0_router_001_default_decode
#(
parameter DEFAULT_CHANNEL = 1,
DEFAULT_WR_CHANNEL = -1,
DEFAULT_RD_CHANNEL = -1,
DEFAULT_DESTID = 5
)
(output [81 - 78 : 0] default_destination_id,
output [11-1 : 0] default_wr_channel,
output [11-1 : 0] default_rd_channel,
output [11-1 : 0] default_src_channel
);
assign default_destination_id =
DEFAULT_DESTID[81 - 78 : 0];
generate
if (DEFAULT_CHANNEL == -1) begin : no_default_channel_assignment
assign default_src_channel = '0;
end
else begin : default_channel_assignment
assign default_src_channel = 11'b1 << DEFAULT_CHANNEL;
end
endgenerate
generate
if (DEFAULT_RD_CHANNEL == -1) begin : no_default_rw_channel_assignment
assign default_wr_channel = '0;
assign default_rd_channel = '0;
end
else begin : default_rw_channel_assignment
assign default_wr_channel = 11'b1 << DEFAULT_WR_CHANNEL;
assign default_rd_channel = 11'b1 << DEFAULT_RD_CHANNEL;
end
endgenerate
endmodule |
module lms_ctr_mm_interconnect_0_router_001
(
// -------------------
// Clock & Reset
// -------------------
input clk,
input reset,
// -------------------
// Command Sink (Input)
// -------------------
input sink_valid,
input [95-1 : 0] sink_data,
input sink_startofpacket,
input sink_endofpacket,
output sink_ready,
// -------------------
// Command Source (Output)
// -------------------
output src_valid,
output reg [95-1 : 0] src_data,
output reg [11-1 : 0] src_channel,
output src_startofpacket,
output src_endofpacket,
input src_ready
);
// -------------------------------------------------------
// Local parameters and variables
// -------------------------------------------------------
localparam PKT_ADDR_H = 52;
localparam PKT_ADDR_L = 36;
localparam PKT_DEST_ID_H = 81;
localparam PKT_DEST_ID_L = 78;
localparam PKT_PROTECTION_H = 85;
localparam PKT_PROTECTION_L = 83;
localparam ST_DATA_W = 95;
localparam ST_CHANNEL_W = 11;
localparam DECODER_TYPE = 0;
localparam PKT_TRANS_WRITE = 55;
localparam PKT_TRANS_READ = 56;
localparam PKT_ADDR_W = PKT_ADDR_H-PKT_ADDR_L + 1;
localparam PKT_DEST_ID_W = PKT_DEST_ID_H-PKT_DEST_ID_L + 1;
// -------------------------------------------------------
// Figure out the number of bits to mask off for each slave span
// during address decoding
// -------------------------------------------------------
localparam PAD0 = log2ceil(64'h10000 - 64'h8000);
localparam PAD1 = log2ceil(64'h11000 - 64'h10800);
// -------------------------------------------------------
// Work out which address bits are significant based on the
// address range of the slaves. If the required width is too
// large or too small, we use the address field width instead.
// -------------------------------------------------------
localparam ADDR_RANGE = 64'h11000;
localparam RANGE_ADDR_WIDTH = log2ceil(ADDR_RANGE);
localparam OPTIMIZED_ADDR_H = (RANGE_ADDR_WIDTH > PKT_ADDR_W) ||
(RANGE_ADDR_WIDTH == 0) ?
PKT_ADDR_H :
PKT_ADDR_L + RANGE_ADDR_WIDTH - 1;
localparam RG = RANGE_ADDR_WIDTH-1;
localparam REAL_ADDRESS_RANGE = OPTIMIZED_ADDR_H - PKT_ADDR_L;
reg [PKT_ADDR_W-1 : 0] address;
always @* begin
address = {PKT_ADDR_W{1'b0}};
address [REAL_ADDRESS_RANGE:0] = sink_data[OPTIMIZED_ADDR_H : PKT_ADDR_L];
end
// -------------------------------------------------------
// Pass almost everything through, untouched
// -------------------------------------------------------
assign sink_ready = src_ready;
assign src_valid = sink_valid;
assign src_startofpacket = sink_startofpacket;
assign src_endofpacket = sink_endofpacket;
wire [PKT_DEST_ID_W-1:0] default_destid;
wire [11-1 : 0] default_src_channel;
lms_ctr_mm_interconnect_0_router_001_default_decode the_default_decode(
.default_destination_id (default_destid),
.default_wr_channel (),
.default_rd_channel (),
.default_src_channel (default_src_channel)
);
always @* begin
src_data = sink_data;
src_channel = default_src_channel;
src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = default_destid;
// --------------------------------------------------
// Address Decoder
// Sets the channel and destination ID based on the address
// --------------------------------------------------
// ( 0x8000 .. 0x10000 )
if ( {address[RG:PAD0],{PAD0{1'b0}}} == 17'h8000 ) begin
src_channel = 11'b10;
src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 5;
end
// ( 0x10800 .. 0x11000 )
if ( {address[RG:PAD1],{PAD1{1'b0}}} == 17'h10800 ) begin
src_channel = 11'b01;
src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 4;
end
end
// --------------------------------------------------
// Ceil(log2()) function
// --------------------------------------------------
function integer log2ceil;
input reg[65:0] val;
reg [65:0] i;
begin
i = 1;
log2ceil = 0;
while (i < val) begin
log2ceil = log2ceil + 1;
i = i << 1;
end
end
endfunction
endmodule |
module lms_ctr_mm_interconnect_0_router_002_default_decode
#(
parameter DEFAULT_CHANNEL = 0,
DEFAULT_WR_CHANNEL = -1,
DEFAULT_RD_CHANNEL = -1,
DEFAULT_DESTID = 0
)
(output [81 - 78 : 0] default_destination_id,
output [11-1 : 0] default_wr_channel,
output [11-1 : 0] default_rd_channel,
output [11-1 : 0] default_src_channel
);
assign default_destination_id =
DEFAULT_DESTID[81 - 78 : 0];
generate
if (DEFAULT_CHANNEL == -1) begin : no_default_channel_assignment
assign default_src_channel = '0;
end
else begin : default_channel_assignment
assign default_src_channel = 11'b1 << DEFAULT_CHANNEL;
end
endgenerate
generate
if (DEFAULT_RD_CHANNEL == -1) begin : no_default_rw_channel_assignment
assign default_wr_channel = '0;
assign default_rd_channel = '0;
end
else begin : default_rw_channel_assignment
assign default_wr_channel = 11'b1 << DEFAULT_WR_CHANNEL;
assign default_rd_channel = 11'b1 << DEFAULT_RD_CHANNEL;
end
endgenerate
endmodule |
module lms_ctr_mm_interconnect_0_router_002
(
// -------------------
// Clock & Reset
// -------------------
input clk,
input reset,
// -------------------
// Command Sink (Input)
// -------------------
input sink_valid,
input [95-1 : 0] sink_data,
input sink_startofpacket,
input sink_endofpacket,
output sink_ready,
// -------------------
// Command Source (Output)
// -------------------
output src_valid,
output reg [95-1 : 0] src_data,
output reg [11-1 : 0] src_channel,
output src_startofpacket,
output src_endofpacket,
input src_ready
);
// -------------------------------------------------------
// Local parameters and variables
// -------------------------------------------------------
localparam PKT_ADDR_H = 52;
localparam PKT_ADDR_L = 36;
localparam PKT_DEST_ID_H = 81;
localparam PKT_DEST_ID_L = 78;
localparam PKT_PROTECTION_H = 85;
localparam PKT_PROTECTION_L = 83;
localparam ST_DATA_W = 95;
localparam ST_CHANNEL_W = 11;
localparam DECODER_TYPE = 1;
localparam PKT_TRANS_WRITE = 55;
localparam PKT_TRANS_READ = 56;
localparam PKT_ADDR_W = PKT_ADDR_H-PKT_ADDR_L + 1;
localparam PKT_DEST_ID_W = PKT_DEST_ID_H-PKT_DEST_ID_L + 1;
// -------------------------------------------------------
// Figure out the number of bits to mask off for each slave span
// during address decoding
// -------------------------------------------------------
// -------------------------------------------------------
// Work out which address bits are significant based on the
// address range of the slaves. If the required width is too
// large or too small, we use the address field width instead.
// -------------------------------------------------------
localparam ADDR_RANGE = 64'h0;
localparam RANGE_ADDR_WIDTH = log2ceil(ADDR_RANGE);
localparam OPTIMIZED_ADDR_H = (RANGE_ADDR_WIDTH > PKT_ADDR_W) ||
(RANGE_ADDR_WIDTH == 0) ?
PKT_ADDR_H :
PKT_ADDR_L + RANGE_ADDR_WIDTH - 1;
localparam RG = RANGE_ADDR_WIDTH;
localparam REAL_ADDRESS_RANGE = OPTIMIZED_ADDR_H - PKT_ADDR_L;
reg [PKT_DEST_ID_W-1 : 0] destid;
// -------------------------------------------------------
// Pass almost everything through, untouched
// -------------------------------------------------------
assign sink_ready = src_ready;
assign src_valid = sink_valid;
assign src_startofpacket = sink_startofpacket;
assign src_endofpacket = sink_endofpacket;
wire [11-1 : 0] default_src_channel;
lms_ctr_mm_interconnect_0_router_002_default_decode the_default_decode(
.default_destination_id (),
.default_wr_channel (),
.default_rd_channel (),
.default_src_channel (default_src_channel)
);
always @* begin
src_data = sink_data;
src_channel = default_src_channel;
// --------------------------------------------------
// DestinationID Decoder
// Sets the channel based on the destination ID.
// --------------------------------------------------
destid = sink_data[PKT_DEST_ID_H : PKT_DEST_ID_L];
if (destid == 0 ) begin
src_channel = 11'b1;
end
end
// --------------------------------------------------
// Ceil(log2()) function
// --------------------------------------------------
function integer log2ceil;
input reg[65:0] val;
reg [65:0] i;
begin
i = 1;
log2ceil = 0;
while (i < val) begin
log2ceil = log2ceil + 1;
i = i << 1;
end
end
endfunction
endmodule |
module lms_ctr_mm_interconnect_0_rsp_mux
(
// ----------------------
// Sinks
// ----------------------
input sink0_valid,
input [95-1 : 0] sink0_data,
input [11-1: 0] sink0_channel,
input sink0_startofpacket,
input sink0_endofpacket,
output sink0_ready,
input sink1_valid,
input [95-1 : 0] sink1_data,
input [11-1: 0] sink1_channel,
input sink1_startofpacket,
input sink1_endofpacket,
output sink1_ready,
input sink2_valid,
input [95-1 : 0] sink2_data,
input [11-1: 0] sink2_channel,
input sink2_startofpacket,
input sink2_endofpacket,
output sink2_ready,
input sink3_valid,
input [95-1 : 0] sink3_data,
input [11-1: 0] sink3_channel,
input sink3_startofpacket,
input sink3_endofpacket,
output sink3_ready,
input sink4_valid,
input [95-1 : 0] sink4_data,
input [11-1: 0] sink4_channel,
input sink4_startofpacket,
input sink4_endofpacket,
output sink4_ready,
input sink5_valid,
input [95-1 : 0] sink5_data,
input [11-1: 0] sink5_channel,
input sink5_startofpacket,
input sink5_endofpacket,
output sink5_ready,
input sink6_valid,
input [95-1 : 0] sink6_data,
input [11-1: 0] sink6_channel,
input sink6_startofpacket,
input sink6_endofpacket,
output sink6_ready,
input sink7_valid,
input [95-1 : 0] sink7_data,
input [11-1: 0] sink7_channel,
input sink7_startofpacket,
input sink7_endofpacket,
output sink7_ready,
input sink8_valid,
input [95-1 : 0] sink8_data,
input [11-1: 0] sink8_channel,
input sink8_startofpacket,
input sink8_endofpacket,
output sink8_ready,
input sink9_valid,
input [95-1 : 0] sink9_data,
input [11-1: 0] sink9_channel,
input sink9_startofpacket,
input sink9_endofpacket,
output sink9_ready,
input sink10_valid,
input [95-1 : 0] sink10_data,
input [11-1: 0] sink10_channel,
input sink10_startofpacket,
input sink10_endofpacket,
output sink10_ready,
// ----------------------
// Source
// ----------------------
output src_valid,
output [95-1 : 0] src_data,
output [11-1 : 0] src_channel,
output src_startofpacket,
output src_endofpacket,
input src_ready,
// ----------------------
// Clock & Reset
// ----------------------
input clk,
input reset
);
localparam PAYLOAD_W = 95 + 11 + 2;
localparam NUM_INPUTS = 11;
localparam SHARE_COUNTER_W = 1;
localparam PIPELINE_ARB = 0;
localparam ST_DATA_W = 95;
localparam ST_CHANNEL_W = 11;
localparam PKT_TRANS_LOCK = 57;
// ------------------------------------------
// Signals
// ------------------------------------------
wire [NUM_INPUTS - 1 : 0] request;
wire [NUM_INPUTS - 1 : 0] valid;
wire [NUM_INPUTS - 1 : 0] grant;
wire [NUM_INPUTS - 1 : 0] next_grant;
reg [NUM_INPUTS - 1 : 0] saved_grant;
reg [PAYLOAD_W - 1 : 0] src_payload;
wire last_cycle;
reg packet_in_progress;
reg update_grant;
wire [PAYLOAD_W - 1 : 0] sink0_payload;
wire [PAYLOAD_W - 1 : 0] sink1_payload;
wire [PAYLOAD_W - 1 : 0] sink2_payload;
wire [PAYLOAD_W - 1 : 0] sink3_payload;
wire [PAYLOAD_W - 1 : 0] sink4_payload;
wire [PAYLOAD_W - 1 : 0] sink5_payload;
wire [PAYLOAD_W - 1 : 0] sink6_payload;
wire [PAYLOAD_W - 1 : 0] sink7_payload;
wire [PAYLOAD_W - 1 : 0] sink8_payload;
wire [PAYLOAD_W - 1 : 0] sink9_payload;
wire [PAYLOAD_W - 1 : 0] sink10_payload;
assign valid[0] = sink0_valid;
assign valid[1] = sink1_valid;
assign valid[2] = sink2_valid;
assign valid[3] = sink3_valid;
assign valid[4] = sink4_valid;
assign valid[5] = sink5_valid;
assign valid[6] = sink6_valid;
assign valid[7] = sink7_valid;
assign valid[8] = sink8_valid;
assign valid[9] = sink9_valid;
assign valid[10] = sink10_valid;
// ------------------------------------------
// ------------------------------------------
// Grant Logic & Updates
// ------------------------------------------
// ------------------------------------------
reg [NUM_INPUTS - 1 : 0] lock;
always @* begin
lock[0] = sink0_data[57];
lock[1] = sink1_data[57];
lock[2] = sink2_data[57];
lock[3] = sink3_data[57];
lock[4] = sink4_data[57];
lock[5] = sink5_data[57];
lock[6] = sink6_data[57];
lock[7] = sink7_data[57];
lock[8] = sink8_data[57];
lock[9] = sink9_data[57];
lock[10] = sink10_data[57];
end
assign last_cycle = src_valid & src_ready & src_endofpacket & ~(|(lock & grant));
// ------------------------------------------
// We're working on a packet at any time valid is high, except
// when this is the endofpacket.
// ------------------------------------------
always @(posedge clk or posedge reset) begin
if (reset) begin
packet_in_progress <= 1'b0;
end
else begin
if (last_cycle)
packet_in_progress <= 1'b0;
else if (src_valid)
packet_in_progress <= 1'b1;
end
end
// ------------------------------------------
// Shares
//
// Special case: all-equal shares _should_ be optimized into assigning a
// constant to next_grant_share.
// Special case: all-1's shares _should_ result in the share counter
// being optimized away.
// ------------------------------------------
// Input | arb shares | counter load value
// 0 | 1 | 0
// 1 | 1 | 0
// 2 | 1 | 0
// 3 | 1 | 0
// 4 | 1 | 0
// 5 | 1 | 0
// 6 | 1 | 0
// 7 | 1 | 0
// 8 | 1 | 0
// 9 | 1 | 0
// 10 | 1 | 0
wire [SHARE_COUNTER_W - 1 : 0] share_0 = 1'd0;
wire [SHARE_COUNTER_W - 1 : 0] share_1 = 1'd0;
wire [SHARE_COUNTER_W - 1 : 0] share_2 = 1'd0;
wire [SHARE_COUNTER_W - 1 : 0] share_3 = 1'd0;
wire [SHARE_COUNTER_W - 1 : 0] share_4 = 1'd0;
wire [SHARE_COUNTER_W - 1 : 0] share_5 = 1'd0;
wire [SHARE_COUNTER_W - 1 : 0] share_6 = 1'd0;
wire [SHARE_COUNTER_W - 1 : 0] share_7 = 1'd0;
wire [SHARE_COUNTER_W - 1 : 0] share_8 = 1'd0;
wire [SHARE_COUNTER_W - 1 : 0] share_9 = 1'd0;
wire [SHARE_COUNTER_W - 1 : 0] share_10 = 1'd0;
// ------------------------------------------
// Choose the share value corresponding to the grant.
// ------------------------------------------
reg [SHARE_COUNTER_W - 1 : 0] next_grant_share;
always @* begin
next_grant_share =
share_0 & { SHARE_COUNTER_W {next_grant[0]} } |
share_1 & { SHARE_COUNTER_W {next_grant[1]} } |
share_2 & { SHARE_COUNTER_W {next_grant[2]} } |
share_3 & { SHARE_COUNTER_W {next_grant[3]} } |
share_4 & { SHARE_COUNTER_W {next_grant[4]} } |
share_5 & { SHARE_COUNTER_W {next_grant[5]} } |
share_6 & { SHARE_COUNTER_W {next_grant[6]} } |
share_7 & { SHARE_COUNTER_W {next_grant[7]} } |
share_8 & { SHARE_COUNTER_W {next_grant[8]} } |
share_9 & { SHARE_COUNTER_W {next_grant[9]} } |
share_10 & { SHARE_COUNTER_W {next_grant[10]} };
end
// ------------------------------------------
// Flag to indicate first packet of an arb sequence.
// ------------------------------------------
wire grant_changed = ~packet_in_progress && ~(|(saved_grant & valid));
reg first_packet_r;
wire first_packet = grant_changed | first_packet_r;
always @(posedge clk or posedge reset) begin
if (reset) begin
first_packet_r <= 1'b0;
end
else begin
if (update_grant)
first_packet_r <= 1'b1;
else if (last_cycle)
first_packet_r <= 1'b0;
else if (grant_changed)
first_packet_r <= 1'b1;
end
end
// ------------------------------------------
// Compute the next share-count value.
// ------------------------------------------
reg [SHARE_COUNTER_W - 1 : 0] p1_share_count;
reg [SHARE_COUNTER_W - 1 : 0] share_count;
reg share_count_zero_flag;
always @* begin
if (first_packet) begin
p1_share_count = next_grant_share;
end
else begin
// Update the counter, but don't decrement below 0.
p1_share_count = share_count_zero_flag ? '0 : share_count - 1'b1;
end
end
// ------------------------------------------
// Update the share counter and share-counter=zero flag.
// ------------------------------------------
always @(posedge clk or posedge reset) begin
if (reset) begin
share_count <= '0;
share_count_zero_flag <= 1'b1;
end
else begin
if (last_cycle) begin
share_count <= p1_share_count;
share_count_zero_flag <= (p1_share_count == '0);
end
end
end
// ------------------------------------------
// For each input, maintain a final_packet signal which goes active for the
// last packet of a full-share packet sequence. Example: if I have 4
// shares and I'm continuously requesting, final_packet is active in the
// 4th packet.
// ------------------------------------------
wire final_packet_0 = 1'b1;
wire final_packet_1 = 1'b1;
wire final_packet_2 = 1'b1;
wire final_packet_3 = 1'b1;
wire final_packet_4 = 1'b1;
wire final_packet_5 = 1'b1;
wire final_packet_6 = 1'b1;
wire final_packet_7 = 1'b1;
wire final_packet_8 = 1'b1;
wire final_packet_9 = 1'b1;
wire final_packet_10 = 1'b1;
// ------------------------------------------
// Concatenate all final_packet signals (wire or reg) into a handy vector.
// ------------------------------------------
wire [NUM_INPUTS - 1 : 0] final_packet = {
final_packet_10,
final_packet_9,
final_packet_8,
final_packet_7,
final_packet_6,
final_packet_5,
final_packet_4,
final_packet_3,
final_packet_2,
final_packet_1,
final_packet_0
};
// ------------------------------------------
// ------------------------------------------
wire p1_done = |(final_packet & grant);
// ------------------------------------------
// Flag for the first cycle of packets within an
// arb sequence
// ------------------------------------------
reg first_cycle;
always @(posedge clk, posedge reset) begin
if (reset)
first_cycle <= 0;
else
first_cycle <= last_cycle && ~p1_done;
end
always @* begin
update_grant = 0;
// ------------------------------------------
// No arbitration pipeline, update grant whenever
// the current arb winner has consumed all shares,
// or all requests are low
// ------------------------------------------
update_grant = (last_cycle && p1_done) || (first_cycle && ~(|valid));
update_grant = last_cycle;
end
wire save_grant;
assign save_grant = 1;
assign grant = next_grant;
always @(posedge clk, posedge reset) begin
if (reset)
saved_grant <= '0;
else if (save_grant)
saved_grant <= next_grant;
end
// ------------------------------------------
// ------------------------------------------
// Arbitrator
// ------------------------------------------
// ------------------------------------------
// ------------------------------------------
// Create a request vector that stays high during
// the packet for unpipelined arbitration.
//
// The pipelined arbitration scheme does not require
// request to be held high during the packet.
// ------------------------------------------
assign request = valid;
wire [NUM_INPUTS - 1 : 0] next_grant_from_arb;
altera_merlin_arbitrator
#(
.NUM_REQUESTERS(NUM_INPUTS),
.SCHEME ("no-arb"),
.PIPELINE (0)
) arb (
.clk (clk),
.reset (reset),
.request (request),
.grant (next_grant_from_arb),
.save_top_priority (src_valid),
.increment_top_priority (update_grant)
);
assign next_grant = next_grant_from_arb;
// ------------------------------------------
// ------------------------------------------
// Mux
//
// Implemented as a sum of products.
// ------------------------------------------
// ------------------------------------------
assign sink0_ready = src_ready && grant[0];
assign sink1_ready = src_ready && grant[1];
assign sink2_ready = src_ready && grant[2];
assign sink3_ready = src_ready && grant[3];
assign sink4_ready = src_ready && grant[4];
assign sink5_ready = src_ready && grant[5];
assign sink6_ready = src_ready && grant[6];
assign sink7_ready = src_ready && grant[7];
assign sink8_ready = src_ready && grant[8];
assign sink9_ready = src_ready && grant[9];
assign sink10_ready = src_ready && grant[10];
assign src_valid = |(grant & valid);
always @* begin
src_payload =
sink0_payload & {PAYLOAD_W {grant[0]} } |
sink1_payload & {PAYLOAD_W {grant[1]} } |
sink2_payload & {PAYLOAD_W {grant[2]} } |
sink3_payload & {PAYLOAD_W {grant[3]} } |
sink4_payload & {PAYLOAD_W {grant[4]} } |
sink5_payload & {PAYLOAD_W {grant[5]} } |
sink6_payload & {PAYLOAD_W {grant[6]} } |
sink7_payload & {PAYLOAD_W {grant[7]} } |
sink8_payload & {PAYLOAD_W {grant[8]} } |
sink9_payload & {PAYLOAD_W {grant[9]} } |
sink10_payload & {PAYLOAD_W {grant[10]} };
end
// ------------------------------------------
// Mux Payload Mapping
// ------------------------------------------
assign sink0_payload = {sink0_channel,sink0_data,
sink0_startofpacket,sink0_endofpacket};
assign sink1_payload = {sink1_channel,sink1_data,
sink1_startofpacket,sink1_endofpacket};
assign sink2_payload = {sink2_channel,sink2_data,
sink2_startofpacket,sink2_endofpacket};
assign sink3_payload = {sink3_channel,sink3_data,
sink3_startofpacket,sink3_endofpacket};
assign sink4_payload = {sink4_channel,sink4_data,
sink4_startofpacket,sink4_endofpacket};
assign sink5_payload = {sink5_channel,sink5_data,
sink5_startofpacket,sink5_endofpacket};
assign sink6_payload = {sink6_channel,sink6_data,
sink6_startofpacket,sink6_endofpacket};
assign sink7_payload = {sink7_channel,sink7_data,
sink7_startofpacket,sink7_endofpacket};
assign sink8_payload = {sink8_channel,sink8_data,
sink8_startofpacket,sink8_endofpacket};
assign sink9_payload = {sink9_channel,sink9_data,
sink9_startofpacket,sink9_endofpacket};
assign sink10_payload = {sink10_channel,sink10_data,
sink10_startofpacket,sink10_endofpacket};
assign {src_channel,src_data,src_startofpacket,src_endofpacket} = src_payload;
endmodule |
module lms_ctr_mm_interconnect_0_cmd_mux_003
(
// ----------------------
// Sinks
// ----------------------
input sink0_valid,
input [95-1 : 0] sink0_data,
input [11-1: 0] sink0_channel,
input sink0_startofpacket,
input sink0_endofpacket,
output sink0_ready,
input sink1_valid,
input [95-1 : 0] sink1_data,
input [11-1: 0] sink1_channel,
input sink1_startofpacket,
input sink1_endofpacket,
output sink1_ready,
// ----------------------
// Source
// ----------------------
output src_valid,
output [95-1 : 0] src_data,
output [11-1 : 0] src_channel,
output src_startofpacket,
output src_endofpacket,
input src_ready,
// ----------------------
// Clock & Reset
// ----------------------
input clk,
input reset
);
localparam PAYLOAD_W = 95 + 11 + 2;
localparam NUM_INPUTS = 2;
localparam SHARE_COUNTER_W = 1;
localparam PIPELINE_ARB = 1;
localparam ST_DATA_W = 95;
localparam ST_CHANNEL_W = 11;
localparam PKT_TRANS_LOCK = 57;
// ------------------------------------------
// Signals
// ------------------------------------------
wire [NUM_INPUTS - 1 : 0] request;
wire [NUM_INPUTS - 1 : 0] valid;
wire [NUM_INPUTS - 1 : 0] grant;
wire [NUM_INPUTS - 1 : 0] next_grant;
reg [NUM_INPUTS - 1 : 0] saved_grant;
reg [PAYLOAD_W - 1 : 0] src_payload;
wire last_cycle;
reg packet_in_progress;
reg update_grant;
wire [PAYLOAD_W - 1 : 0] sink0_payload;
wire [PAYLOAD_W - 1 : 0] sink1_payload;
assign valid[0] = sink0_valid;
assign valid[1] = sink1_valid;
wire [NUM_INPUTS - 1 : 0] eop;
assign eop[0] = sink0_endofpacket;
assign eop[1] = sink1_endofpacket;
// ------------------------------------------
// ------------------------------------------
// Grant Logic & Updates
// ------------------------------------------
// ------------------------------------------
reg [NUM_INPUTS - 1 : 0] lock;
always @* begin
lock[0] = sink0_data[57];
lock[1] = sink1_data[57];
end
reg [NUM_INPUTS - 1 : 0] locked = '0;
always @(posedge clk or posedge reset) begin
if (reset) begin
locked <= '0;
end
else begin
locked <= next_grant & lock;
end
end
assign last_cycle = src_valid & src_ready & src_endofpacket & ~(|(lock & grant));
// ------------------------------------------
// We're working on a packet at any time valid is high, except
// when this is the endofpacket.
// ------------------------------------------
always @(posedge clk or posedge reset) begin
if (reset) begin
packet_in_progress <= 1'b0;
end
else begin
if (last_cycle)
packet_in_progress <= 1'b0;
else if (src_valid)
packet_in_progress <= 1'b1;
end
end
// ------------------------------------------
// Shares
//
// Special case: all-equal shares _should_ be optimized into assigning a
// constant to next_grant_share.
// Special case: all-1's shares _should_ result in the share counter
// being optimized away.
// ------------------------------------------
// Input | arb shares | counter load value
// 0 | 1 | 0
// 1 | 1 | 0
wire [SHARE_COUNTER_W - 1 : 0] share_0 = 1'd0;
wire [SHARE_COUNTER_W - 1 : 0] share_1 = 1'd0;
// ------------------------------------------
// Choose the share value corresponding to the grant.
// ------------------------------------------
reg [SHARE_COUNTER_W - 1 : 0] next_grant_share;
always @* begin
next_grant_share =
share_0 & { SHARE_COUNTER_W {next_grant[0]} } |
share_1 & { SHARE_COUNTER_W {next_grant[1]} };
end
// ------------------------------------------
// Flag to indicate first packet of an arb sequence.
// ------------------------------------------
// ------------------------------------------
// Compute the next share-count value.
// ------------------------------------------
reg [SHARE_COUNTER_W - 1 : 0] p1_share_count;
reg [SHARE_COUNTER_W - 1 : 0] share_count;
reg share_count_zero_flag;
always @* begin
// Update the counter, but don't decrement below 0.
p1_share_count = share_count_zero_flag ? '0 : share_count - 1'b1;
end
// ------------------------------------------
// Update the share counter and share-counter=zero flag.
// ------------------------------------------
always @(posedge clk or posedge reset) begin
if (reset) begin
share_count <= '0;
share_count_zero_flag <= 1'b1;
end
else begin
if (update_grant) begin
share_count <= next_grant_share;
share_count_zero_flag <= (next_grant_share == '0);
end
else if (last_cycle) begin
share_count <= p1_share_count;
share_count_zero_flag <= (p1_share_count == '0);
end
end
end
always @* begin
update_grant = 0;
// ------------------------------------------
// The pipeline delays grant by one cycle, so
// we have to calculate the update_grant signal
// one cycle ahead of time.
//
// Possible optimization: omit the first clause
// "if (!packet_in_progress & ~src_valid) ..."
// cost: one idle cycle at the the beginning of each
// grant cycle.
// benefit: save a small amount of logic.
// ------------------------------------------
if (!packet_in_progress & !src_valid)
update_grant = 1;
if (last_cycle && share_count_zero_flag)
update_grant = 1;
end
wire save_grant;
assign save_grant = update_grant;
assign grant = saved_grant;
always @(posedge clk, posedge reset) begin
if (reset)
saved_grant <= '0;
else if (save_grant)
saved_grant <= next_grant;
end
// ------------------------------------------
// ------------------------------------------
// Arbitrator
// ------------------------------------------
// ------------------------------------------
// ------------------------------------------
// Create a request vector that stays high during
// the packet for unpipelined arbitration.
//
// The pipelined arbitration scheme does not require
// request to be held high during the packet.
// ------------------------------------------
reg [NUM_INPUTS - 1 : 0] prev_request;
always @(posedge clk, posedge reset) begin
if (reset)
prev_request <= '0;
else
prev_request <= request & ~(valid & eop);
end
assign request = (PIPELINE_ARB == 1) ? valid | locked :
prev_request | valid | locked;
wire [NUM_INPUTS - 1 : 0] next_grant_from_arb;
altera_merlin_arbitrator
#(
.NUM_REQUESTERS(NUM_INPUTS),
.SCHEME ("round-robin"),
.PIPELINE (1)
) arb (
.clk (clk),
.reset (reset),
.request (request),
.grant (next_grant_from_arb),
.save_top_priority (src_valid),
.increment_top_priority (update_grant)
);
assign next_grant = next_grant_from_arb;
// ------------------------------------------
// ------------------------------------------
// Mux
//
// Implemented as a sum of products.
// ------------------------------------------
// ------------------------------------------
assign sink0_ready = src_ready && grant[0];
assign sink1_ready = src_ready && grant[1];
assign src_valid = |(grant & valid);
always @* begin
src_payload =
sink0_payload & {PAYLOAD_W {grant[0]} } |
sink1_payload & {PAYLOAD_W {grant[1]} };
end
// ------------------------------------------
// Mux Payload Mapping
// ------------------------------------------
assign sink0_payload = {sink0_channel,sink0_data,
sink0_startofpacket,sink0_endofpacket};
assign sink1_payload = {sink1_channel,sink1_data,
sink1_startofpacket,sink1_endofpacket};
assign {src_channel,src_data,src_startofpacket,src_endofpacket} = src_payload;
endmodule |
module lms_ctr_mm_interconnect_0_router_default_decode
#(
parameter DEFAULT_CHANNEL = 4,
DEFAULT_WR_CHANNEL = -1,
DEFAULT_RD_CHANNEL = -1,
DEFAULT_DESTID = 5
)
(output [81 - 78 : 0] default_destination_id,
output [11-1 : 0] default_wr_channel,
output [11-1 : 0] default_rd_channel,
output [11-1 : 0] default_src_channel
);
assign default_destination_id =
DEFAULT_DESTID[81 - 78 : 0];
generate
if (DEFAULT_CHANNEL == -1) begin : no_default_channel_assignment
assign default_src_channel = '0;
end
else begin : default_channel_assignment
assign default_src_channel = 11'b1 << DEFAULT_CHANNEL;
end
endgenerate
generate
if (DEFAULT_RD_CHANNEL == -1) begin : no_default_rw_channel_assignment
assign default_wr_channel = '0;
assign default_rd_channel = '0;
end
else begin : default_rw_channel_assignment
assign default_wr_channel = 11'b1 << DEFAULT_WR_CHANNEL;
assign default_rd_channel = 11'b1 << DEFAULT_RD_CHANNEL;
end
endgenerate
endmodule |
module lms_ctr_mm_interconnect_0_router
(
// -------------------
// Clock & Reset
// -------------------
input clk,
input reset,
// -------------------
// Command Sink (Input)
// -------------------
input sink_valid,
input [95-1 : 0] sink_data,
input sink_startofpacket,
input sink_endofpacket,
output sink_ready,
// -------------------
// Command Source (Output)
// -------------------
output src_valid,
output reg [95-1 : 0] src_data,
output reg [11-1 : 0] src_channel,
output src_startofpacket,
output src_endofpacket,
input src_ready
);
// -------------------------------------------------------
// Local parameters and variables
// -------------------------------------------------------
localparam PKT_ADDR_H = 52;
localparam PKT_ADDR_L = 36;
localparam PKT_DEST_ID_H = 81;
localparam PKT_DEST_ID_L = 78;
localparam PKT_PROTECTION_H = 85;
localparam PKT_PROTECTION_L = 83;
localparam ST_DATA_W = 95;
localparam ST_CHANNEL_W = 11;
localparam DECODER_TYPE = 0;
localparam PKT_TRANS_WRITE = 55;
localparam PKT_TRANS_READ = 56;
localparam PKT_ADDR_W = PKT_ADDR_H-PKT_ADDR_L + 1;
localparam PKT_DEST_ID_W = PKT_DEST_ID_H-PKT_DEST_ID_L + 1;
// -------------------------------------------------------
// Figure out the number of bits to mask off for each slave span
// during address decoding
// -------------------------------------------------------
localparam PAD0 = log2ceil(64'h10000 - 64'h8000);
localparam PAD1 = log2ceil(64'h11000 - 64'h10800);
localparam PAD2 = log2ceil(64'h11020 - 64'h11000);
localparam PAD3 = log2ceil(64'h11040 - 64'h11020);
localparam PAD4 = log2ceil(64'h11060 - 64'h11040);
localparam PAD5 = log2ceil(64'h11080 - 64'h11060);
localparam PAD6 = log2ceil(64'h110a0 - 64'h11080);
localparam PAD7 = log2ceil(64'h110b0 - 64'h110a0);
localparam PAD8 = log2ceil(64'h110c0 - 64'h110b0);
localparam PAD9 = log2ceil(64'h110d0 - 64'h110c0);
localparam PAD10 = log2ceil(64'h110d8 - 64'h110d0);
// -------------------------------------------------------
// Work out which address bits are significant based on the
// address range of the slaves. If the required width is too
// large or too small, we use the address field width instead.
// -------------------------------------------------------
localparam ADDR_RANGE = 64'h110d8;
localparam RANGE_ADDR_WIDTH = log2ceil(ADDR_RANGE);
localparam OPTIMIZED_ADDR_H = (RANGE_ADDR_WIDTH > PKT_ADDR_W) ||
(RANGE_ADDR_WIDTH == 0) ?
PKT_ADDR_H :
PKT_ADDR_L + RANGE_ADDR_WIDTH - 1;
localparam RG = RANGE_ADDR_WIDTH-1;
localparam REAL_ADDRESS_RANGE = OPTIMIZED_ADDR_H - PKT_ADDR_L;
reg [PKT_ADDR_W-1 : 0] address;
always @* begin
address = {PKT_ADDR_W{1'b0}};
address [REAL_ADDRESS_RANGE:0] = sink_data[OPTIMIZED_ADDR_H : PKT_ADDR_L];
end
// -------------------------------------------------------
// Pass almost everything through, untouched
// -------------------------------------------------------
assign sink_ready = src_ready;
assign src_valid = sink_valid;
assign src_startofpacket = sink_startofpacket;
assign src_endofpacket = sink_endofpacket;
wire [PKT_DEST_ID_W-1:0] default_destid;
wire [11-1 : 0] default_src_channel;
// -------------------------------------------------------
// Write and read transaction signals
// -------------------------------------------------------
wire read_transaction;
assign read_transaction = sink_data[PKT_TRANS_READ];
lms_ctr_mm_interconnect_0_router_default_decode the_default_decode(
.default_destination_id (default_destid),
.default_wr_channel (),
.default_rd_channel (),
.default_src_channel (default_src_channel)
);
always @* begin
src_data = sink_data;
src_channel = default_src_channel;
src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = default_destid;
// --------------------------------------------------
// Address Decoder
// Sets the channel and destination ID based on the address
// --------------------------------------------------
// ( 0x8000 .. 0x10000 )
if ( {address[RG:PAD0],{PAD0{1'b0}}} == 17'h8000 ) begin
src_channel = 11'b00000010000;
src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 5;
end
// ( 0x10800 .. 0x11000 )
if ( {address[RG:PAD1],{PAD1{1'b0}}} == 17'h10800 ) begin
src_channel = 11'b00000001000;
src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 4;
end
// ( 0x11000 .. 0x11020 )
if ( {address[RG:PAD2],{PAD2{1'b0}}} == 17'h11000 ) begin
src_channel = 11'b10000000000;
src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 6;
end
// ( 0x11020 .. 0x11040 )
if ( {address[RG:PAD3],{PAD3{1'b0}}} == 17'h11020 ) begin
src_channel = 11'b01000000000;
src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 7;
end
// ( 0x11040 .. 0x11060 )
if ( {address[RG:PAD4],{PAD4{1'b0}}} == 17'h11040 ) begin
src_channel = 11'b00100000000;
src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 8;
end
// ( 0x11060 .. 0x11080 )
if ( {address[RG:PAD5],{PAD5{1'b0}}} == 17'h11060 ) begin
src_channel = 11'b00010000000;
src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 3;
end
// ( 0x11080 .. 0x110a0 )
if ( {address[RG:PAD6],{PAD6{1'b0}}} == 17'h11080 ) begin
src_channel = 11'b00000000010;
src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 1;
end
// ( 0x110a0 .. 0x110b0 )
if ( {address[RG:PAD7],{PAD7{1'b0}}} == 17'h110a0 ) begin
src_channel = 11'b00001000000;
src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 2;
end
// ( 0x110b0 .. 0x110c0 )
if ( {address[RG:PAD8],{PAD8{1'b0}}} == 17'h110b0 && read_transaction ) begin
src_channel = 11'b00000100000;
src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 9;
end
// ( 0x110c0 .. 0x110d0 )
if ( {address[RG:PAD9],{PAD9{1'b0}}} == 17'h110c0 ) begin
src_channel = 11'b00000000001;
src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 0;
end
// ( 0x110d0 .. 0x110d8 )
if ( {address[RG:PAD10],{PAD10{1'b0}}} == 17'h110d0 && read_transaction ) begin
src_channel = 11'b00000000100;
src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 10;
end
end
// --------------------------------------------------
// Ceil(log2()) function
// --------------------------------------------------
function integer log2ceil;
input reg[65:0] val;
reg [65:0] i;
begin
i = 1;
log2ceil = 0;
while (i < val) begin
log2ceil = log2ceil + 1;
i = i << 1;
end
end
endfunction
endmodule |
module lms_ctr_mm_interconnect_0_cmd_mux_002
(
// ----------------------
// Sinks
// ----------------------
input sink0_valid,
input [93-1 : 0] sink0_data,
input [8-1: 0] sink0_channel,
input sink0_startofpacket,
input sink0_endofpacket,
output sink0_ready,
input sink1_valid,
input [93-1 : 0] sink1_data,
input [8-1: 0] sink1_channel,
input sink1_startofpacket,
input sink1_endofpacket,
output sink1_ready,
// ----------------------
// Source
// ----------------------
output src_valid,
output [93-1 : 0] src_data,
output [8-1 : 0] src_channel,
output src_startofpacket,
output src_endofpacket,
input src_ready,
// ----------------------
// Clock & Reset
// ----------------------
input clk,
input reset
);
localparam PAYLOAD_W = 93 + 8 + 2;
localparam NUM_INPUTS = 2;
localparam SHARE_COUNTER_W = 1;
localparam PIPELINE_ARB = 1;
localparam ST_DATA_W = 93;
localparam ST_CHANNEL_W = 8;
localparam PKT_TRANS_LOCK = 57;
// ------------------------------------------
// Signals
// ------------------------------------------
wire [NUM_INPUTS - 1 : 0] request;
wire [NUM_INPUTS - 1 : 0] valid;
wire [NUM_INPUTS - 1 : 0] grant;
wire [NUM_INPUTS - 1 : 0] next_grant;
reg [NUM_INPUTS - 1 : 0] saved_grant;
reg [PAYLOAD_W - 1 : 0] src_payload;
wire last_cycle;
reg packet_in_progress;
reg update_grant;
wire [PAYLOAD_W - 1 : 0] sink0_payload;
wire [PAYLOAD_W - 1 : 0] sink1_payload;
assign valid[0] = sink0_valid;
assign valid[1] = sink1_valid;
wire [NUM_INPUTS - 1 : 0] eop;
assign eop[0] = sink0_endofpacket;
assign eop[1] = sink1_endofpacket;
// ------------------------------------------
// ------------------------------------------
// Grant Logic & Updates
// ------------------------------------------
// ------------------------------------------
reg [NUM_INPUTS - 1 : 0] lock;
always @* begin
lock[0] = sink0_data[57];
lock[1] = sink1_data[57];
end
reg [NUM_INPUTS - 1 : 0] locked = '0;
always @(posedge clk or posedge reset) begin
if (reset) begin
locked <= '0;
end
else begin
locked <= next_grant & lock;
end
end
assign last_cycle = src_valid & src_ready & src_endofpacket & ~(|(lock & grant));
// ------------------------------------------
// We're working on a packet at any time valid is high, except
// when this is the endofpacket.
// ------------------------------------------
always @(posedge clk or posedge reset) begin
if (reset) begin
packet_in_progress <= 1'b0;
end
else begin
if (last_cycle)
packet_in_progress <= 1'b0;
else if (src_valid)
packet_in_progress <= 1'b1;
end
end
// ------------------------------------------
// Shares
//
// Special case: all-equal shares _should_ be optimized into assigning a
// constant to next_grant_share.
// Special case: all-1's shares _should_ result in the share counter
// being optimized away.
// ------------------------------------------
// Input | arb shares | counter load value
// 0 | 1 | 0
// 1 | 1 | 0
wire [SHARE_COUNTER_W - 1 : 0] share_0 = 1'd0;
wire [SHARE_COUNTER_W - 1 : 0] share_1 = 1'd0;
// ------------------------------------------
// Choose the share value corresponding to the grant.
// ------------------------------------------
reg [SHARE_COUNTER_W - 1 : 0] next_grant_share;
always @* begin
next_grant_share =
share_0 & { SHARE_COUNTER_W {next_grant[0]} } |
share_1 & { SHARE_COUNTER_W {next_grant[1]} };
end
// ------------------------------------------
// Flag to indicate first packet of an arb sequence.
// ------------------------------------------
// ------------------------------------------
// Compute the next share-count value.
// ------------------------------------------
reg [SHARE_COUNTER_W - 1 : 0] p1_share_count;
reg [SHARE_COUNTER_W - 1 : 0] share_count;
reg share_count_zero_flag;
always @* begin
// Update the counter, but don't decrement below 0.
p1_share_count = share_count_zero_flag ? '0 : share_count - 1'b1;
end
// ------------------------------------------
// Update the share counter and share-counter=zero flag.
// ------------------------------------------
always @(posedge clk or posedge reset) begin
if (reset) begin
share_count <= '0;
share_count_zero_flag <= 1'b1;
end
else begin
if (update_grant) begin
share_count <= next_grant_share;
share_count_zero_flag <= (next_grant_share == '0);
end
else if (last_cycle) begin
share_count <= p1_share_count;
share_count_zero_flag <= (p1_share_count == '0);
end
end
end
always @* begin
update_grant = 0;
// ------------------------------------------
// The pipeline delays grant by one cycle, so
// we have to calculate the update_grant signal
// one cycle ahead of time.
//
// Possible optimization: omit the first clause
// "if (!packet_in_progress & ~src_valid) ..."
// cost: one idle cycle at the the beginning of each
// grant cycle.
// benefit: save a small amount of logic.
// ------------------------------------------
if (!packet_in_progress & !src_valid)
update_grant = 1;
if (last_cycle && share_count_zero_flag)
update_grant = 1;
end
wire save_grant;
assign save_grant = update_grant;
assign grant = saved_grant;
always @(posedge clk, posedge reset) begin
if (reset)
saved_grant <= '0;
else if (save_grant)
saved_grant <= next_grant;
end
// ------------------------------------------
// ------------------------------------------
// Arbitrator
// ------------------------------------------
// ------------------------------------------
// ------------------------------------------
// Create a request vector that stays high during
// the packet for unpipelined arbitration.
//
// The pipelined arbitration scheme does not require
// request to be held high during the packet.
// ------------------------------------------
reg [NUM_INPUTS - 1 : 0] prev_request;
always @(posedge clk, posedge reset) begin
if (reset)
prev_request <= '0;
else
prev_request <= request & ~(valid & eop);
end
assign request = (PIPELINE_ARB == 1) ? valid | locked :
prev_request | valid | locked;
wire [NUM_INPUTS - 1 : 0] next_grant_from_arb;
altera_merlin_arbitrator
#(
.NUM_REQUESTERS(NUM_INPUTS),
.SCHEME ("round-robin"),
.PIPELINE (1)
) arb (
.clk (clk),
.reset (reset),
.request (request),
.grant (next_grant_from_arb),
.save_top_priority (src_valid),
.increment_top_priority (update_grant)
);
assign next_grant = next_grant_from_arb;
// ------------------------------------------
// ------------------------------------------
// Mux
//
// Implemented as a sum of products.
// ------------------------------------------
// ------------------------------------------
assign sink0_ready = src_ready && grant[0];
assign sink1_ready = src_ready && grant[1];
assign src_valid = |(grant & valid);
always @* begin
src_payload =
sink0_payload & {PAYLOAD_W {grant[0]} } |
sink1_payload & {PAYLOAD_W {grant[1]} };
end
// ------------------------------------------
// Mux Payload Mapping
// ------------------------------------------
assign sink0_payload = {sink0_channel,sink0_data,
sink0_startofpacket,sink0_endofpacket};
assign sink1_payload = {sink1_channel,sink1_data,
sink1_startofpacket,sink1_endofpacket};
assign {src_channel,src_data,src_startofpacket,src_endofpacket} = src_payload;
endmodule |
module lms_ctr_mm_interconnect_0_rsp_demux
(
// -------------------
// Sink
// -------------------
input [1-1 : 0] sink_valid,
input [95-1 : 0] sink_data, // ST_DATA_W=95
input [11-1 : 0] sink_channel, // ST_CHANNEL_W=11
input sink_startofpacket,
input sink_endofpacket,
output sink_ready,
// -------------------
// Sources
// -------------------
output reg src0_valid,
output reg [95-1 : 0] src0_data, // ST_DATA_W=95
output reg [11-1 : 0] src0_channel, // ST_CHANNEL_W=11
output reg src0_startofpacket,
output reg src0_endofpacket,
input src0_ready,
// -------------------
// Clock & Reset
// -------------------
(*altera_attribute = "-name MESSAGE_DISABLE 15610" *) // setting message suppression on clk
input clk,
(*altera_attribute = "-name MESSAGE_DISABLE 15610" *) // setting message suppression on reset
input reset
);
localparam NUM_OUTPUTS = 1;
wire [NUM_OUTPUTS - 1 : 0] ready_vector;
// -------------------
// Demux
// -------------------
always @* begin
src0_data = sink_data;
src0_startofpacket = sink_startofpacket;
src0_endofpacket = sink_endofpacket;
src0_channel = sink_channel >> NUM_OUTPUTS;
src0_valid = sink_channel[0] && sink_valid;
end
// -------------------
// Backpressure
// -------------------
assign ready_vector[0] = src0_ready;
assign sink_ready = |(sink_channel & {{10{1'b0}},{ready_vector[NUM_OUTPUTS - 1 : 0]}});
endmodule |
module lms_ctr_irq_mapper
(
// -------------------
// Clock & Reset
// -------------------
input clk,
input reset,
// -------------------
// IRQ Receivers
// -------------------
input receiver0_irq,
input receiver1_irq,
input receiver2_irq,
input receiver3_irq,
// -------------------
// Command Source (Output)
// -------------------
output reg [31 : 0] sender_irq
);
always @* begin
sender_irq = 0;
sender_irq[0] = receiver0_irq;
sender_irq[1] = receiver1_irq;
sender_irq[2] = receiver2_irq;
sender_irq[3] = receiver3_irq;
end
endmodule |
module lms_ctr_mm_interconnect_0_cmd_demux_001
(
// -------------------
// Sink
// -------------------
input [1-1 : 0] sink_valid,
input [95-1 : 0] sink_data, // ST_DATA_W=95
input [11-1 : 0] sink_channel, // ST_CHANNEL_W=11
input sink_startofpacket,
input sink_endofpacket,
output sink_ready,
// -------------------
// Sources
// -------------------
output reg src0_valid,
output reg [95-1 : 0] src0_data, // ST_DATA_W=95
output reg [11-1 : 0] src0_channel, // ST_CHANNEL_W=11
output reg src0_startofpacket,
output reg src0_endofpacket,
input src0_ready,
output reg src1_valid,
output reg [95-1 : 0] src1_data, // ST_DATA_W=95
output reg [11-1 : 0] src1_channel, // ST_CHANNEL_W=11
output reg src1_startofpacket,
output reg src1_endofpacket,
input src1_ready,
// -------------------
// Clock & Reset
// -------------------
(*altera_attribute = "-name MESSAGE_DISABLE 15610" *) // setting message suppression on clk
input clk,
(*altera_attribute = "-name MESSAGE_DISABLE 15610" *) // setting message suppression on reset
input reset
);
localparam NUM_OUTPUTS = 2;
wire [NUM_OUTPUTS - 1 : 0] ready_vector;
// -------------------
// Demux
// -------------------
always @* begin
src0_data = sink_data;
src0_startofpacket = sink_startofpacket;
src0_endofpacket = sink_endofpacket;
src0_channel = sink_channel >> NUM_OUTPUTS;
src0_valid = sink_channel[0] && sink_valid;
src1_data = sink_data;
src1_startofpacket = sink_startofpacket;
src1_endofpacket = sink_endofpacket;
src1_channel = sink_channel >> NUM_OUTPUTS;
src1_valid = sink_channel[1] && sink_valid;
end
// -------------------
// Backpressure
// -------------------
assign ready_vector[0] = src0_ready;
assign ready_vector[1] = src1_ready;
assign sink_ready = |(sink_channel & {{9{1'b0}},{ready_vector[NUM_OUTPUTS - 1 : 0]}});
endmodule |
module lms_ctr_mm_interconnect_0_router_005_default_decode
#(
parameter DEFAULT_CHANNEL = 0,
DEFAULT_WR_CHANNEL = -1,
DEFAULT_RD_CHANNEL = -1,
DEFAULT_DESTID = 0
)
(output [81 - 78 : 0] default_destination_id,
output [11-1 : 0] default_wr_channel,
output [11-1 : 0] default_rd_channel,
output [11-1 : 0] default_src_channel
);
assign default_destination_id =
DEFAULT_DESTID[81 - 78 : 0];
generate
if (DEFAULT_CHANNEL == -1) begin : no_default_channel_assignment
assign default_src_channel = '0;
end
else begin : default_channel_assignment
assign default_src_channel = 11'b1 << DEFAULT_CHANNEL;
end
endgenerate
generate
if (DEFAULT_RD_CHANNEL == -1) begin : no_default_rw_channel_assignment
assign default_wr_channel = '0;
assign default_rd_channel = '0;
end
else begin : default_rw_channel_assignment
assign default_wr_channel = 11'b1 << DEFAULT_WR_CHANNEL;
assign default_rd_channel = 11'b1 << DEFAULT_RD_CHANNEL;
end
endgenerate
endmodule |
module lms_ctr_mm_interconnect_0_router_005
(
// -------------------
// Clock & Reset
// -------------------
input clk,
input reset,
// -------------------
// Command Sink (Input)
// -------------------
input sink_valid,
input [95-1 : 0] sink_data,
input sink_startofpacket,
input sink_endofpacket,
output sink_ready,
// -------------------
// Command Source (Output)
// -------------------
output src_valid,
output reg [95-1 : 0] src_data,
output reg [11-1 : 0] src_channel,
output src_startofpacket,
output src_endofpacket,
input src_ready
);
// -------------------------------------------------------
// Local parameters and variables
// -------------------------------------------------------
localparam PKT_ADDR_H = 52;
localparam PKT_ADDR_L = 36;
localparam PKT_DEST_ID_H = 81;
localparam PKT_DEST_ID_L = 78;
localparam PKT_PROTECTION_H = 85;
localparam PKT_PROTECTION_L = 83;
localparam ST_DATA_W = 95;
localparam ST_CHANNEL_W = 11;
localparam DECODER_TYPE = 1;
localparam PKT_TRANS_WRITE = 55;
localparam PKT_TRANS_READ = 56;
localparam PKT_ADDR_W = PKT_ADDR_H-PKT_ADDR_L + 1;
localparam PKT_DEST_ID_W = PKT_DEST_ID_H-PKT_DEST_ID_L + 1;
// -------------------------------------------------------
// Figure out the number of bits to mask off for each slave span
// during address decoding
// -------------------------------------------------------
// -------------------------------------------------------
// Work out which address bits are significant based on the
// address range of the slaves. If the required width is too
// large or too small, we use the address field width instead.
// -------------------------------------------------------
localparam ADDR_RANGE = 64'h0;
localparam RANGE_ADDR_WIDTH = log2ceil(ADDR_RANGE);
localparam OPTIMIZED_ADDR_H = (RANGE_ADDR_WIDTH > PKT_ADDR_W) ||
(RANGE_ADDR_WIDTH == 0) ?
PKT_ADDR_H :
PKT_ADDR_L + RANGE_ADDR_WIDTH - 1;
localparam RG = RANGE_ADDR_WIDTH;
localparam REAL_ADDRESS_RANGE = OPTIMIZED_ADDR_H - PKT_ADDR_L;
reg [PKT_DEST_ID_W-1 : 0] destid;
// -------------------------------------------------------
// Pass almost everything through, untouched
// -------------------------------------------------------
assign sink_ready = src_ready;
assign src_valid = sink_valid;
assign src_startofpacket = sink_startofpacket;
assign src_endofpacket = sink_endofpacket;
wire [11-1 : 0] default_src_channel;
// -------------------------------------------------------
// Write and read transaction signals
// -------------------------------------------------------
wire read_transaction;
assign read_transaction = sink_data[PKT_TRANS_READ];
lms_ctr_mm_interconnect_0_router_005_default_decode the_default_decode(
.default_destination_id (),
.default_wr_channel (),
.default_rd_channel (),
.default_src_channel (default_src_channel)
);
always @* begin
src_data = sink_data;
src_channel = default_src_channel;
// --------------------------------------------------
// DestinationID Decoder
// Sets the channel based on the destination ID.
// --------------------------------------------------
destid = sink_data[PKT_DEST_ID_H : PKT_DEST_ID_L];
if (destid == 0 ) begin
src_channel = 11'b01;
end
if (destid == 1 && read_transaction) begin
src_channel = 11'b10;
end
end
// --------------------------------------------------
// Ceil(log2()) function
// --------------------------------------------------
function integer log2ceil;
input reg[65:0] val;
reg [65:0] i;
begin
i = 1;
log2ceil = 0;
while (i < val) begin
log2ceil = log2ceil + 1;
i = i << 1;
end
end
endfunction
endmodule |
module lms_ctr_mm_interconnect_0_router_004_default_decode
#(
parameter DEFAULT_CHANNEL = 0,
DEFAULT_WR_CHANNEL = -1,
DEFAULT_RD_CHANNEL = -1,
DEFAULT_DESTID = 0
)
(output [79 - 77 : 0] default_destination_id,
output [8-1 : 0] default_wr_channel,
output [8-1 : 0] default_rd_channel,
output [8-1 : 0] default_src_channel
);
assign default_destination_id =
DEFAULT_DESTID[79 - 77 : 0];
generate
if (DEFAULT_CHANNEL == -1) begin : no_default_channel_assignment
assign default_src_channel = '0;
end
else begin : default_channel_assignment
assign default_src_channel = 8'b1 << DEFAULT_CHANNEL;
end
endgenerate
generate
if (DEFAULT_RD_CHANNEL == -1) begin : no_default_rw_channel_assignment
assign default_wr_channel = '0;
assign default_rd_channel = '0;
end
else begin : default_rw_channel_assignment
assign default_wr_channel = 8'b1 << DEFAULT_WR_CHANNEL;
assign default_rd_channel = 8'b1 << DEFAULT_RD_CHANNEL;
end
endgenerate
endmodule |
module lms_ctr_mm_interconnect_0_router_004
(
// -------------------
// Clock & Reset
// -------------------
input clk,
input reset,
// -------------------
// Command Sink (Input)
// -------------------
input sink_valid,
input [93-1 : 0] sink_data,
input sink_startofpacket,
input sink_endofpacket,
output sink_ready,
// -------------------
// Command Source (Output)
// -------------------
output src_valid,
output reg [93-1 : 0] src_data,
output reg [8-1 : 0] src_channel,
output src_startofpacket,
output src_endofpacket,
input src_ready
);
// -------------------------------------------------------
// Local parameters and variables
// -------------------------------------------------------
localparam PKT_ADDR_H = 52;
localparam PKT_ADDR_L = 36;
localparam PKT_DEST_ID_H = 79;
localparam PKT_DEST_ID_L = 77;
localparam PKT_PROTECTION_H = 83;
localparam PKT_PROTECTION_L = 81;
localparam ST_DATA_W = 93;
localparam ST_CHANNEL_W = 8;
localparam DECODER_TYPE = 1;
localparam PKT_TRANS_WRITE = 55;
localparam PKT_TRANS_READ = 56;
localparam PKT_ADDR_W = PKT_ADDR_H-PKT_ADDR_L + 1;
localparam PKT_DEST_ID_W = PKT_DEST_ID_H-PKT_DEST_ID_L + 1;
// -------------------------------------------------------
// Figure out the number of bits to mask off for each slave span
// during address decoding
// -------------------------------------------------------
// -------------------------------------------------------
// Work out which address bits are significant based on the
// address range of the slaves. If the required width is too
// large or too small, we use the address field width instead.
// -------------------------------------------------------
localparam ADDR_RANGE = 64'h0;
localparam RANGE_ADDR_WIDTH = log2ceil(ADDR_RANGE);
localparam OPTIMIZED_ADDR_H = (RANGE_ADDR_WIDTH > PKT_ADDR_W) ||
(RANGE_ADDR_WIDTH == 0) ?
PKT_ADDR_H :
PKT_ADDR_L + RANGE_ADDR_WIDTH - 1;
localparam RG = RANGE_ADDR_WIDTH;
localparam REAL_ADDRESS_RANGE = OPTIMIZED_ADDR_H - PKT_ADDR_L;
reg [PKT_DEST_ID_W-1 : 0] destid;
// -------------------------------------------------------
// Pass almost everything through, untouched
// -------------------------------------------------------
assign sink_ready = src_ready;
assign src_valid = sink_valid;
assign src_startofpacket = sink_startofpacket;
assign src_endofpacket = sink_endofpacket;
wire [8-1 : 0] default_src_channel;
// -------------------------------------------------------
// Write and read transaction signals
// -------------------------------------------------------
wire read_transaction;
assign read_transaction = sink_data[PKT_TRANS_READ];
lms_ctr_mm_interconnect_0_router_004_default_decode the_default_decode(
.default_destination_id (),
.default_wr_channel (),
.default_rd_channel (),
.default_src_channel (default_src_channel)
);
always @* begin
src_data = sink_data;
src_channel = default_src_channel;
// --------------------------------------------------
// DestinationID Decoder
// Sets the channel based on the destination ID.
// --------------------------------------------------
destid = sink_data[PKT_DEST_ID_H : PKT_DEST_ID_L];
if (destid == 0 ) begin
src_channel = 8'b01;
end
if (destid == 1 && read_transaction) begin
src_channel = 8'b10;
end
end
// --------------------------------------------------
// Ceil(log2()) function
// --------------------------------------------------
function integer log2ceil;
input reg[65:0] val;
reg [65:0] i;
begin
i = 1;
log2ceil = 0;
while (i < val) begin
log2ceil = log2ceil + 1;
i = i << 1;
end
end
endfunction
endmodule |
module lms_ctr_mm_interconnect_0_rsp_mux_001
(
// ----------------------
// Sinks
// ----------------------
input sink0_valid,
input [95-1 : 0] sink0_data,
input [11-1: 0] sink0_channel,
input sink0_startofpacket,
input sink0_endofpacket,
output sink0_ready,
input sink1_valid,
input [95-1 : 0] sink1_data,
input [11-1: 0] sink1_channel,
input sink1_startofpacket,
input sink1_endofpacket,
output sink1_ready,
// ----------------------
// Source
// ----------------------
output src_valid,
output [95-1 : 0] src_data,
output [11-1 : 0] src_channel,
output src_startofpacket,
output src_endofpacket,
input src_ready,
// ----------------------
// Clock & Reset
// ----------------------
input clk,
input reset
);
localparam PAYLOAD_W = 95 + 11 + 2;
localparam NUM_INPUTS = 2;
localparam SHARE_COUNTER_W = 1;
localparam PIPELINE_ARB = 0;
localparam ST_DATA_W = 95;
localparam ST_CHANNEL_W = 11;
localparam PKT_TRANS_LOCK = 57;
// ------------------------------------------
// Signals
// ------------------------------------------
wire [NUM_INPUTS - 1 : 0] request;
wire [NUM_INPUTS - 1 : 0] valid;
wire [NUM_INPUTS - 1 : 0] grant;
wire [NUM_INPUTS - 1 : 0] next_grant;
reg [NUM_INPUTS - 1 : 0] saved_grant;
reg [PAYLOAD_W - 1 : 0] src_payload;
wire last_cycle;
reg packet_in_progress;
reg update_grant;
wire [PAYLOAD_W - 1 : 0] sink0_payload;
wire [PAYLOAD_W - 1 : 0] sink1_payload;
assign valid[0] = sink0_valid;
assign valid[1] = sink1_valid;
// ------------------------------------------
// ------------------------------------------
// Grant Logic & Updates
// ------------------------------------------
// ------------------------------------------
reg [NUM_INPUTS - 1 : 0] lock;
always @* begin
lock[0] = sink0_data[57];
lock[1] = sink1_data[57];
end
assign last_cycle = src_valid & src_ready & src_endofpacket & ~(|(lock & grant));
// ------------------------------------------
// We're working on a packet at any time valid is high, except
// when this is the endofpacket.
// ------------------------------------------
always @(posedge clk or posedge reset) begin
if (reset) begin
packet_in_progress <= 1'b0;
end
else begin
if (last_cycle)
packet_in_progress <= 1'b0;
else if (src_valid)
packet_in_progress <= 1'b1;
end
end
// ------------------------------------------
// Shares
//
// Special case: all-equal shares _should_ be optimized into assigning a
// constant to next_grant_share.
// Special case: all-1's shares _should_ result in the share counter
// being optimized away.
// ------------------------------------------
// Input | arb shares | counter load value
// 0 | 1 | 0
// 1 | 1 | 0
wire [SHARE_COUNTER_W - 1 : 0] share_0 = 1'd0;
wire [SHARE_COUNTER_W - 1 : 0] share_1 = 1'd0;
// ------------------------------------------
// Choose the share value corresponding to the grant.
// ------------------------------------------
reg [SHARE_COUNTER_W - 1 : 0] next_grant_share;
always @* begin
next_grant_share =
share_0 & { SHARE_COUNTER_W {next_grant[0]} } |
share_1 & { SHARE_COUNTER_W {next_grant[1]} };
end
// ------------------------------------------
// Flag to indicate first packet of an arb sequence.
// ------------------------------------------
wire grant_changed = ~packet_in_progress && ~(|(saved_grant & valid));
reg first_packet_r;
wire first_packet = grant_changed | first_packet_r;
always @(posedge clk or posedge reset) begin
if (reset) begin
first_packet_r <= 1'b0;
end
else begin
if (update_grant)
first_packet_r <= 1'b1;
else if (last_cycle)
first_packet_r <= 1'b0;
else if (grant_changed)
first_packet_r <= 1'b1;
end
end
// ------------------------------------------
// Compute the next share-count value.
// ------------------------------------------
reg [SHARE_COUNTER_W - 1 : 0] p1_share_count;
reg [SHARE_COUNTER_W - 1 : 0] share_count;
reg share_count_zero_flag;
always @* begin
if (first_packet) begin
p1_share_count = next_grant_share;
end
else begin
// Update the counter, but don't decrement below 0.
p1_share_count = share_count_zero_flag ? '0 : share_count - 1'b1;
end
end
// ------------------------------------------
// Update the share counter and share-counter=zero flag.
// ------------------------------------------
always @(posedge clk or posedge reset) begin
if (reset) begin
share_count <= '0;
share_count_zero_flag <= 1'b1;
end
else begin
if (last_cycle) begin
share_count <= p1_share_count;
share_count_zero_flag <= (p1_share_count == '0);
end
end
end
// ------------------------------------------
// For each input, maintain a final_packet signal which goes active for the
// last packet of a full-share packet sequence. Example: if I have 4
// shares and I'm continuously requesting, final_packet is active in the
// 4th packet.
// ------------------------------------------
wire final_packet_0 = 1'b1;
wire final_packet_1 = 1'b1;
// ------------------------------------------
// Concatenate all final_packet signals (wire or reg) into a handy vector.
// ------------------------------------------
wire [NUM_INPUTS - 1 : 0] final_packet = {
final_packet_1,
final_packet_0
};
// ------------------------------------------
// ------------------------------------------
wire p1_done = |(final_packet & grant);
// ------------------------------------------
// Flag for the first cycle of packets within an
// arb sequence
// ------------------------------------------
reg first_cycle;
always @(posedge clk, posedge reset) begin
if (reset)
first_cycle <= 0;
else
first_cycle <= last_cycle && ~p1_done;
end
always @* begin
update_grant = 0;
// ------------------------------------------
// No arbitration pipeline, update grant whenever
// the current arb winner has consumed all shares,
// or all requests are low
// ------------------------------------------
update_grant = (last_cycle && p1_done) || (first_cycle && ~(|valid));
update_grant = last_cycle;
end
wire save_grant;
assign save_grant = 1;
assign grant = next_grant;
always @(posedge clk, posedge reset) begin
if (reset)
saved_grant <= '0;
else if (save_grant)
saved_grant <= next_grant;
end
// ------------------------------------------
// ------------------------------------------
// Arbitrator
// ------------------------------------------
// ------------------------------------------
// ------------------------------------------
// Create a request vector that stays high during
// the packet for unpipelined arbitration.
//
// The pipelined arbitration scheme does not require
// request to be held high during the packet.
// ------------------------------------------
assign request = valid;
wire [NUM_INPUTS - 1 : 0] next_grant_from_arb;
altera_merlin_arbitrator
#(
.NUM_REQUESTERS(NUM_INPUTS),
.SCHEME ("no-arb"),
.PIPELINE (0)
) arb (
.clk (clk),
.reset (reset),
.request (request),
.grant (next_grant_from_arb),
.save_top_priority (src_valid),
.increment_top_priority (update_grant)
);
assign next_grant = next_grant_from_arb;
// ------------------------------------------
// ------------------------------------------
// Mux
//
// Implemented as a sum of products.
// ------------------------------------------
// ------------------------------------------
assign sink0_ready = src_ready && grant[0];
assign sink1_ready = src_ready && grant[1];
assign src_valid = |(grant & valid);
always @* begin
src_payload =
sink0_payload & {PAYLOAD_W {grant[0]} } |
sink1_payload & {PAYLOAD_W {grant[1]} };
end
// ------------------------------------------
// Mux Payload Mapping
// ------------------------------------------
assign sink0_payload = {sink0_channel,sink0_data,
sink0_startofpacket,sink0_endofpacket};
assign sink1_payload = {sink1_channel,sink1_data,
sink1_startofpacket,sink1_endofpacket};
assign {src_channel,src_data,src_startofpacket,src_endofpacket} = src_payload;
endmodule |
module sgen_nco_tb;
time CLK_PERIOD = 50.0;// 10kHz
reg i_rst_an;
reg i_ena;
reg i_clk;
reg s_clk;
reg [`P_PHASEACCU_WIDTH-1:0] i_fcw;
wire rdy;
wire signed [`P_ROM_WIDTH:0] o_sin_rtl,o_cos_rtl;
reg data_ready;
integer error_count=0;
reg [8*64:1] filename_vcd;
// READ-IN MATLAB STIMULI FILE
reg [8*64:1] filename_mat_inp;
integer fid_mat_inp;
integer status_mat_inp;
// READ-IN MATLAB RESPONSE FILE
reg [8*64:1] filename_mat_oup;
integer fid_mat_oup;
integer status_mat_oup;
reg signed [`P_ROM_WIDTH:0] o_sin_mat, o_cos_mat;
// WRITE-OUT RTL RESPONSE FILE
reg [8*64:1] filename_rtl_oup;
integer fid_rtl_oup;
integer status_rtl_oup;
// RTL MATLAB TOLERANCE
integer diff, abs_diff;
// -------------------------------------------------------------------
initial
begin
i_rst_an = 1'b1;
#1 i_rst_an = 1'b0;
#(2*2*CLK_PERIOD+CLK_PERIOD-3) i_rst_an = 1'b1;
end
initial
begin
i_ena = 1'b0;
#(2*2*CLK_PERIOD+CLK_PERIOD-1) i_ena = 1'b1;
end
initial s_clk = 1'b0;
always s_clk = #(CLK_PERIOD) ~s_clk;
//initial s_clk = #5 i_clk;
assign #1 i_clk = s_clk;
initial
begin: TEXTIO_READ_IN
$display("### INFO: RTL Simulation of NCO.");
$display("### Testcase %d", `TESTCASE);
$sformat(filename_mat_inp,"%s%0d%s","./sim/testcases/stimuli/stimuli_tc_",`TESTCASE,"_mat.dat");
$sformat(filename_mat_oup,"%s%0d%s","./sim/testcases/response/response_tc_",`TESTCASE,"_mat.dat");
$display("%s",filename_mat_inp);
fid_mat_inp = $fopen(filename_mat_inp, "r");
fid_mat_oup = $fopen(filename_mat_oup, "r");
if ((fid_mat_inp == `NULL)||(fid_mat_oup == `NULL)) begin
$display("data_file handle was NULL");
$finish;
end
@(posedge data_ready)
begin
$fclose(fid_mat_inp);
$fclose(fid_mat_oup);
if (error_count>0)
$display("### INFO: Testcase FAILED");
else
$display("### INFO: Testcase PASSED");
$finish;
end
end
always @(posedge s_clk)
begin: MATLAB_STIMULI
if (i_rst_an && i_ena)
status_mat_inp = $fscanf(fid_mat_inp,"%d\n", i_fcw);
else
i_fcw = 'd0;
if ($feof(fid_mat_inp)) begin
data_ready = 1'b1;
end
end
always @(posedge i_clk)
begin: MATLAB_RESPONSE
if (i_rst_an && i_ena)
status_mat_oup = $fscanf(fid_mat_oup,"%d %d\n", o_sin_mat, o_cos_mat);
end
always @(negedge i_clk)
begin: ASSERT_RTL_vs_MATLAB
if (i_rst_an && i_ena)
diff = o_sin_rtl - o_sin_mat;
abs_diff = `ABS(diff);
if ( abs_diff > 1)
begin
$error("### RTL = %d, MAT = %d", o_sin_rtl, o_sin_mat); error_count<= error_count + 1;
end
end
`ifdef RTL
initial
begin: TEXTIO_WRITE_OUT
$sformat(filename_rtl_oup,"%s%0d%s","./sim/testcases/response/response_tc_",`TESTCASE,"_rtl.dat");
fid_rtl_oup = $fopen(filename_rtl_oup, "w");
@(posedge data_ready) $fclose(fid_rtl_oup);
end
always @(posedge i_clk)
begin: RTL_RESPONSE
$fwrite(fid_rtl_oup,"%d\n",o_sin_rtl);
end
`endif
sgen_nco #(
.gp_rom_width (`P_ROM_WIDTH),
.gp_rom_depth (`P_ROM_DEPTH),
.gp_phase_accu_width (`P_PHASEACCU_WIDTH)
) dut (
.i_rst_an (i_rst_an),
.i_ena (i_ena),
.i_clk (i_clk),
.i_fcw (i_fcw),
.o_sin (o_sin_rtl),
.o_cos (o_cos_rtl)
);
`ifdef VCD
initial
begin
$sformat(filename_vcd,"%s%0d%s","sgen_nco_",`TESTCASE,".vcd");
$dumpfile(filename_vcd);
$dumpvars(0,sgen_nco_tb);
end
`endif
endmodule |
module filt_fir_tb;
time CLK_PERIOD = 50;
reg i_rst_an;
reg i_ena;
reg i_clk;
reg [`P_INP_DATA_W-1:0] i_data;
wire rdy;
wire signed [`P_OUP_DATA_W-1:0] oup_data;
reg data_ready;
integer error_count=0;
integer nr_of_samples=0;
reg [8*64:1] filename_vcd;
// READ-IN MATLAB STIMULI FILE
reg [8*64:1] filename_mat_inp;
integer fid_mat_inp;
integer status_mat_inp;
// READ-IN MATLAB RESPONSE FILE
reg [8*64:1] filename_mat_oup;
integer fid_mat_oup;
integer status_mat_oup;
reg signed [`P_OUP_DATA_W-1:0] o_data_mat;
// -------------------------------------------------------------------
initial
begin
i_rst_an = 1'b1;
#170 i_rst_an = 1'b0;
#205 i_rst_an = 1'b1;
end
initial
begin
i_ena = 1'b0;
#410 i_ena = 1'b1;
end
initial i_clk = 1'b0;
always i_clk = #(CLK_PERIOD) ~i_clk;
initial
begin: TEXTIO_READ_IN
$display("### INFO: RTL Simulation of FIR Filter.");
$display("### Testcase %d", `TESTCASE);
//$write("### ");$system($sformatf("date"));
$sformat(filename_mat_inp,"%s%0d%s","./sim/testcases/stimuli/stimuli_tc_",`TESTCASE,"_mat.dat");
$sformat(filename_mat_oup,"%s%0d%s","./sim/testcases/response/response_tc_",`TESTCASE,"_mat.dat");
$display("%s",filename_mat_inp);
fid_mat_inp = $fopen(filename_mat_inp, "r");
fid_mat_oup = $fopen(filename_mat_oup, "r");
if ((fid_mat_inp == `NULL)||(fid_mat_oup == `NULL)) begin
$display("data_file handle was NULL");
$finish;
end
@(posedge data_ready)
begin
$fclose(fid_mat_inp);
$fclose(fid_mat_oup);
if (error_count>0)
$display("### INFO: Testcase FAILED");
else
$display("### INFO: Testcase PASSED with %d samples", nr_of_samples);
$finish;
end
end
always @(posedge i_clk)
begin: MATLAB_STIMULI
if (i_rst_an && i_ena) begin
status_mat_inp = $fscanf(fid_mat_inp,"%d\n", i_data);
nr_of_samples <= nr_of_samples + 1;
end
else
i_data = 'd0;
if ($feof(fid_mat_inp)) begin
data_ready = 1'b1;
end
end
always @(posedge i_clk)
begin: MATLAB_RESPONSE
if (i_rst_an && i_ena)
status_mat_oup = $fscanf(fid_mat_oup,"%d\n", o_data_mat);
end
always @(negedge i_clk)
begin
if (i_rst_an && i_ena)
if (oup_data != o_data_mat)
begin
$error("### RTL = %d, MAT = %d", oup_data, o_data_mat); error_count<= error_count + 1;
end
end
filt_fir #(
.gp_inp_width (`P_INP_DATA_W),
.gp_coeff_length (`P_COEFF_L),
.gp_coeff_width (`P_COEFF_W),
.gp_tf_df (`P_TF_DF),
.gp_symm (`P_SYMM),
.gp_oup_width ()
) dut (
.i_rst_an (i_rst_an),
.i_ena (i_ena),
.i_clk (i_clk),
.i_data (i_data),
.o_data (oup_data)
);
`ifdef VCD
initial
begin
$sformat(filename_vcd,"%s%0d%s","filt_fir_",`TESTCASE,".vcd");
$dumpfile(filename_vcd);
$dumpvars(0,filt_fir_tb);
end
`endif
endmodule |
module filt_ppi_tb;
time CLK_PERIOD = 1000;
//time F_CLK_PERIOD = CLK_PERIOD/`P_INTERPOLATION;
reg i_rst_an;
reg i_ena=1'b0;
reg i_clk;
reg i_fclk;
reg f_clk=1'b0;
reg s_clk;
int r_cnt=`P_INTERPOLATION;
reg [1:0] r_start_chk='d0;
integer error_count=0;
reg data_ready=1'b0;
reg signed [`P_INP_DATA_W-1:0] i_data;
wire signed [`P_OUP_W-1:0] o_data_rtl;
reg [8*64:1] filename_vcd;
// READ-IN MATLAB STIMULI FILE
reg [8*64:1] filename_mat_inp;
integer fid_mat_inp;
integer status_mat_inp;
// READ-IN MATLAB RESPONSE FILE
reg [8*64:1] filename_mat_oup;
integer fid_mat_oup;
integer status_mat_oup;
reg signed [`P_OUP_W-1:0] r_data_mat;
reg signed [`P_OUP_W-1:0] sr_data_mat [0:`P_INTERPOLATION];
reg signed [`P_OUP_W-1:0] o_data_mat;
// -------------------------------------------------------------------
initial
begin: RST
i_rst_an = 1'b1;
#2 i_rst_an = 1'b0;
#(0.5*CLK_PERIOD) i_rst_an = 1'b1;
end
always @(posedge s_clk)
begin: EGU
if (i_rst_an)
i_ena = 1'b1;
end
always f_clk = #(CLK_PERIOD/(`P_INTERPOLATION*2)) ~f_clk;
always @(posedge f_clk)
begin: SCLK
if (r_cnt<`P_INTERPOLATION-1)
r_cnt <= r_cnt + 1;
else
r_cnt <= 'd0;
end
assign s_clk = (r_cnt<`P_INTERPOLATION/2) ? 1'b1 : 1'b0;
initial begin
fork
forever #2 i_fclk = f_clk;
forever #2 i_clk = s_clk;
join
end
always @(posedge i_clk)
begin: FLAG_START_CHK
if (r_start_chk < 3)
r_start_chk <= r_start_chk + 1;
end
integer error;
initial
begin: TEXTIO_READ_IN
$display("### INFO: RTL Simulation of Polyphase Interpolation FIR Filter.");
$display("### Testcase %d", `TESTCASE);
//$write("### ");$system($sformatf("date"));
$sformat(filename_mat_inp,"%s%0d%s","./sim/testcases/stimuli/stimuli_tc_",`TESTCASE,"_mat.dat");
$sformat(filename_mat_oup,"%s%0d%s","./sim/testcases/response/response_tc_",`TESTCASE,"_mat.dat");
$display("%s",filename_mat_inp);$display("%s",filename_mat_oup);
fid_mat_inp = $fopen(filename_mat_inp, "r");
fid_mat_oup = $fopen(filename_mat_oup, "r");
if ((fid_mat_inp == `NULL)||(fid_mat_oup == `NULL)) begin
$display("data_file handle was NULL");
$finish;
end
@(posedge data_ready)
begin
$fclose(fid_mat_inp);
$fclose(fid_mat_oup);
if (error_count>0)
$display("### INFO: Testcase FAILED");
else
$display("### INFO: Testcase PASSED");
$finish;
end
end
always @(posedge i_clk)
begin: MATLAB_STIMULI
if (i_rst_an && i_ena)
status_mat_inp = $fscanf(fid_mat_inp,"%d\n", i_data);
else
i_data = 'd0;
if ($feof(fid_mat_inp)) begin
data_ready = 1'b1;
end
end
always @(negedge i_fclk)
begin: MATLAB_RESPONSE
if (i_rst_an && i_ena)
status_mat_oup = $fscanf(fid_mat_oup,"%d\n", o_data_mat);
end
filt_ppi #(
.gp_idata_width (`P_INP_DATA_W ),
.gp_interpolation_factor (`P_INTERPOLATION),
.gp_coeff_length (`P_COEFF_L ),
.gp_coeff_width (`P_COEFF_W ),
.gp_tf_df (`P_TF_DF ),
.gp_comm_ccw (`P_COMM_CCW_CW ),
.gp_mul_ccw (`P_MUL_CCW_CW ),
.gp_comm_phase (`P_COMM_PHA ),
.gp_odata_width (`P_OUP_W )
) dut (
.i_rst_an (i_rst_an ),
.i_ena (i_ena ),
.i_clk (i_clk ),
.i_data (i_data ),
.i_fclk (i_fclk ),
.o_data (o_data_rtl),
.o_sclk ( )
);
always @(posedge i_fclk)
begin: ASSERT_OUP_CHK
if (i_rst_an && i_ena && (r_start_chk == 3))
begin
if (o_data_rtl !== o_data_mat)
begin
$error("### RTL = %d, MAT = %d", o_data_rtl, o_data_mat); error_count<= error_count + 1;
end
end
end
`ifdef VCD
initial
begin
$sformat(filename_vcd,"%s%0d%s","filt_ppi_",`TESTCASE,".vcd");
$dumpfile(filename_vcd);
$dumpvars(0,filt_ppi_tb);
end
`endif
endmodule |
module filt_ppd_tb;
time CLK_PERIOD = 50;
reg i_rst_an;
reg i_ena=1'b0;
reg i_clk;
reg f_clk=1'b0;
wire s_clk;// = 1'b0;
integer error_count=0;
reg data_ready;
reg signed [`P_INP_DATA_W-1:0] i_data,r_data;
wire signed [`P_OUP_W-1:0] o_data_rtl;
reg [8*64:1] filename_vcd;
// READ-IN MATLAB STIMULI FILE
reg [8*64:1] filename_mat_inp;
integer fid_mat_inp;
integer status_mat_inp;
// READ-IN MATLAB RESPONSE FILE
reg [8*64:1] filename_mat_oup;
integer fid_mat_oup;
integer status_mat_oup;
reg signed [`P_OUP_W-1:0] o_data_mat;
// -------------------------------------------------------------------
initial
begin: RGU
i_rst_an = 1'b1;
#130 i_rst_an = 1'b0;
#205 i_rst_an = 1'b1;
end
always @(posedge f_clk)
begin: EGU
if (i_rst_an&&!s_clk)
i_ena = 1'b1;
end
always
begin: GEN_CLK
f_clk = #(CLK_PERIOD/2) ~f_clk;
end
reg res_clk;
initial begin
fork
forever #2 i_clk = f_clk;
forever #1 res_clk = s_clk;
join
end
initial data_ready = 0;
initial
begin: TEXTIO_READ_IN
$display("### INFO: RTL Simulation of Polyphase Decimation FIR Filter.");
$display("### Testcase %d", `TESTCASE);
//$write("### ");$system($sformatf("date"));
$sformat(filename_mat_inp,"%s%0d%s","./sim/testcases/stimuli/stimuli_tc_",`TESTCASE,"_mat.dat");
$sformat(filename_mat_oup,"%s%0d%s","./sim/testcases/response/response_tc_",`TESTCASE,"_mat.dat");
$display("%s",filename_mat_inp);$display("%s",filename_mat_oup);
fid_mat_inp = $fopen(filename_mat_inp, "r");
fid_mat_oup = $fopen(filename_mat_oup, "r");
if ((fid_mat_inp == `NULL)||(fid_mat_oup == `NULL)) begin
$display("data_file handle was NULL");
$finish;
end
@(posedge data_ready)
begin
$fclose(fid_mat_inp);
$fclose(fid_mat_oup);
if (error_count>0)
$display("### INFO: Testcase FAILED");
else
$display("### INFO: Testcase PASSED");
$finish;
end
end
always @(posedge i_clk)
begin: MATLAB_STIMULI
if (i_rst_an && i_ena)
status_mat_inp = $fscanf(fid_mat_inp,"%d\n", r_data);
else
r_data = 'd0;
if ($feof(fid_mat_inp)) begin
data_ready = 1'b1;
end
end
always i_data = #5 r_data;
always @(posedge res_clk)
begin: MATLAB_RESPONSE
if (i_rst_an && i_ena)
status_mat_oup = $fscanf(fid_mat_oup, "%d\n", o_data_mat);
end
filt_ppd #(
.gp_idata_width (`P_INP_DATA_W ),
.gp_decimation_factor (`P_DECIMATION ),
.gp_coeff_length (`P_COEFF_L ),
.gp_coeff_width (`P_COEFF_W ),
.gp_tf_df (`P_TF_DF ),
.gp_comm_reg_oup (`P_COMM_R_OUP ),
.gp_comm_ccw (`P_COMM_CCW_CW),
.gp_mul_ccw (`P_MUL_CCW_CW ),
.gp_comm_phase (`P_COMM_PHA ),
.gp_odata_width ( )
) dut (
.i_rst_an (i_rst_an ),
.i_ena (i_ena ),
.i_clk (i_clk ),
.i_data (i_data ),
.o_data (o_data_rtl),
.o_sclk (s_clk )
);
always @(negedge s_clk)
begin
if (i_rst_an && i_ena)
if (o_data_rtl != o_data_mat)
//else
begin
$error("### RTL = %d, MAT = %d", o_data_rtl, o_data_mat); error_count<= error_count + 1;
end
end
`ifdef VCD
initial
begin
$sformat(filename_vcd,"%s%0d%s","filt_ppd_",`TESTCASE,".vcd");
$dumpfile(filename_vcd);
$dumpvars(0,filt_ppd_tb);
end
`endif
endmodule |
module filt_mac_tb;
localparam CLK_CYCLES = (`P_SYMM) ? `DIV2(`P_COEFF_L) : `P_COEFF_L;
time F_CLK_PERIOD = 50;
time S_CLK_PERIOD = 50*CLK_CYCLES;
reg i_rst_an;
reg i_ena;
reg i_clk;
reg s_clk;
reg f_clk = 1'b0;
reg [`P_INP_DATA_W-1:0] i_data;
wire rdy;
wire signed [`P_OUP_DATA_W-1:0] oup_data;
wire o_done;
reg data_ready;
reg load_response= 1'b0;
integer error_count=0;
integer count_clk_cycles=127;
reg [8*64:1] filename_vcd;
// READ-IN MATLAB STIMULI FILE
reg [8*64:1] filename_mat_inp;
integer fid_mat_inp;
integer status_mat_inp;
// READ-IN MATLAB RESPONSE FILE
reg [8*64:1] filename_mat_oup;
integer fid_mat_oup;
integer status_mat_oup;
reg signed [`P_OUP_DATA_W-1:0] o_data_mat;
// -------------------------------------------------------------------
initial
begin: RGU
i_rst_an = 1'b1;
#17 i_rst_an = 1'b0;
#205 i_rst_an = 1'b1;
end
initial
begin: EGU
i_ena = 1'b0;
#400 i_ena = 1'b1;
end
//initial f_clk = 1'b0;
always
begin: FCGU
f_clk = #(F_CLK_PERIOD) ~f_clk;
end
initial s_clk = 1'b0;
//initial count_clk_cycles = 127;
always @(posedge f_clk)
begin: CLK_DIV
if (i_ena)
begin
if (count_clk_cycles < CLK_CYCLES-1)
count_clk_cycles <= count_clk_cycles + 1'b1;
else
count_clk_cycles = 0;
end
end
always @(*)
begin: SCGU
s_clk = (count_clk_cycles==0) ? 1'b1 : 1'b0;
end
always
begin: CGU
i_clk = #1 f_clk;
end
//initial load_response = 1'b0;
always @(posedge o_done)
begin
if ( (i_rst_an && i_ena) && (load_response < 1) )
load_response <= load_response + 1'b1;
end
initial
begin: TEXTIO_READ_IN
$display("### INFO: RTL Simulation of FIR Filter.");
$display("### Testcase %d", `TESTCASE);
$write("### ");
//$system($sformatf("date"));
$sformat(filename_mat_inp,"%s%0d%s","./sim/testcases/stimuli/stimuli_tc_",`TESTCASE,"_mat.dat");
$sformat(filename_mat_oup,"%s%0d%s","./sim/testcases/response/response_tc_",`TESTCASE,"_mat.dat");
$display("%s",filename_mat_inp);
fid_mat_inp = $fopen(filename_mat_inp, "r");
fid_mat_oup = $fopen(filename_mat_oup, "r");
if ((fid_mat_inp == `NULL)||(fid_mat_oup == `NULL)) begin
$display("data_file handle was NULL");
$finish;
end
@(posedge data_ready)
begin
$fclose(fid_mat_inp);
$fclose(fid_mat_oup);
if (error_count>0)
$display("### INFO: Testcase FAILED");
else
$display("### INFO: Testcase PASSED");
$finish;
end
end
always @(posedge s_clk)
begin: MATLAB_STIMULI
if (i_rst_an && i_ena)
status_mat_inp = $fscanf(fid_mat_inp,"%d\n", i_data);
else
i_data = 'd0;
if ($feof(fid_mat_inp)) begin
data_ready = 1'b1;
end
end
always @(posedge s_clk)
begin: MATLAB_RESPONSE
if (i_rst_an && i_ena && load_response)
status_mat_oup = $fscanf(fid_mat_oup,"%d\n", o_data_mat);
else
o_data_mat = 'd0;
end
always @(negedge s_clk)
begin: CHK_OUP
if (i_rst_an && i_ena)
if (oup_data != o_data_mat)
begin
$error("### RTL = %d, MAT = %d", oup_data, o_data_mat); error_count<= error_count + 1;
end
end
/*initial
begin
i_data = 'd0;
#(549+300) i_data = 'd1;
#(4*100) i_data = 'd0;
i_data = 'd0;
#(549+300) i_data = 'd1;
i_data = 'd10;
#(549+300) i_data = 'd1;
#(4*100) i_data = 'd2;
#(4*100) i_data = 'd3;
#(4*100) i_data = 'd4;
#(4*100) i_data = 'd5;
#(4*100) i_data = 'd6;
#(4*100) i_data = 'd7;
#(4*100) i_data = 'd8;
#(4*100) i_data = 'd9;
i_data = 'd0;
#(549+1700) i_data = 'd1;
#(17*100) i_data = 'd2;
#(17*100) i_data = 'd3;
#(17*100) i_data = 'd4;
#(17*100) i_data = 'd5;
#(17*100) i_data = 'd6;
#(17*100) i_data = 'd7;
#(17*100) i_data = 'd8;
#(17*100) i_data = 'd9;
end*/
filt_mac #(
.gp_inp_width (`P_INP_DATA_W),
.gp_coeff_length (`P_COEFF_L),
.gp_coeff_width (`P_COEFF_W),
.gp_symm (`P_SYMM),
.gp_oup_width (`P_OUP_DATA_W)
) dut (
.i_rst_an (i_rst_an),
.i_ena (i_ena),
.i_clk (i_clk),
.i_data (i_data),
.o_data (oup_data),
.o_done (o_done)
);
`ifdef VCD
initial
begin
$sformat(filename_vcd,"%s%0d%s","filt_mac_",`TESTCASE,".vcd");
$dumpfile(filename_vcd);
$dumpvars(0,filt_mac_tb);
end
`endif
endmodule |
module filt_cici_tb;
time CLK_PERIOD = 400;
//time F_CLK_PERIOD = CLK_PERIOD/`P_INTERPOLATION;
reg i_rst_an;
reg i_ena=1'b0;
reg i_clk=1'b0;
reg i_fclk=1'b0;
reg f_clk=1'b0;
reg s_clk;
int r_cnt=`P_INTERPOLATION;
reg [`P_INP_DATA_W-1:0] i_data,r_data;
wire rdy;
wire signed [`P_OUP_DATA_W-1:0] oup_data;
reg data_ready=1'b0;
integer error_count=0;
reg [8*64:1] filename_vcd;
// READ-IN MATLAB STIMULI FILE
reg [8*64:1] filename_mat_inp;
integer fid_mat_inp;
integer status_mat_inp;
// READ-IN MATLAB RESPONSE FILE
reg [8*64:1] filename_mat_oup;
integer fid_mat_oup;
integer status_mat_oup;
reg signed [`P_OUP_DATA_W-1:0] o_data_mat;
// -------------------------------------------------------------------
initial
begin: RST
i_rst_an = 1'b1;
#2 i_rst_an = 1'b0;
#(0.5*CLK_PERIOD) i_rst_an = 1'b1;
end
always @(posedge s_clk)
begin: EGU
if (i_rst_an)
i_ena = 1'b1;
end
always f_clk = #(CLK_PERIOD/(`P_INTERPOLATION*2)) ~f_clk;
always @(posedge f_clk)
begin: SCLK
if (r_cnt<`P_INTERPOLATION-1)
r_cnt <= r_cnt + 1;
else
r_cnt <= 'd0;
end
assign s_clk = (r_cnt<`P_INTERPOLATION/2) ? 1'b1 : 1'b0;
initial begin
fork
forever #2 i_fclk = f_clk;
forever #2 i_clk = s_clk;
join
end
initial
begin: TEXTIO_READ_IN
$display("### INFO: RTL Simulation of CIC Interpolation Filter.");
$display("### Testcase %d", `TESTCASE);
$sformat(filename_mat_inp,"%s%0d%s","./sim/testcases/stimuli/stimuli_tc_",`TESTCASE,"_mat.dat");
$sformat(filename_mat_oup,"%s%0d%s","./sim/testcases/response/response_tc_",`TESTCASE,"_mat.dat");
$display("%s",filename_mat_inp);
fid_mat_inp = $fopen(filename_mat_inp, "r");
fid_mat_oup = $fopen(filename_mat_oup, "r");
if ((fid_mat_inp == `NULL)||(fid_mat_oup == `NULL)) begin
$display("data_file handle was NULL");
$finish;
end
@(posedge data_ready)
begin
$fclose(fid_mat_inp);
$fclose(fid_mat_oup);
if (error_count>0)
$display("### INFO: Testcase FAILED");
else
$display("### INFO: Testcase PASSED");
$finish;
end
end
always @(posedge i_clk)
begin: MATLAB_STIMULI
if (i_rst_an && i_ena)
status_mat_inp = $fscanf(fid_mat_inp,"%d\n", i_data);
else
i_data = 'd0;
if ($feof(fid_mat_inp)) begin
data_ready = 1'b1;
end
end
always @(posedge i_fclk)
begin: MATLAB_RESPONSE
if (i_rst_an && i_ena)
status_mat_oup = $fscanf(fid_mat_oup,"%d\n", o_data_mat);
end
always @(negedge f_clk)
begin
if (i_rst_an && i_ena)
if (oup_data != o_data_mat)
begin
$error("### RTL = %d, MAT = %d", oup_data, o_data_mat); error_count<= error_count + 1;
end
end
filt_cici #(
.gp_interpolation_factor (`P_INTERPOLATION),
.gp_order (`P_ORDER),
.gp_diff_delay (`P_DIFF_DELAY),
.gp_phase (`P_PHASE),
.gp_inp_width (`P_INP_DATA_W),
.gp_oup_width (`P_OUP_DATA_W)
) dut (
.i_rst_an (i_rst_an),
.i_ena (i_ena),
.i_clk (s_clk),
.i_fclk (i_fclk),
.i_data (i_data),
.o_data (oup_data)
);
`ifdef VCD
initial
begin
$sformat(filename_vcd,"%s%0d%s","filt_cici_",`TESTCASE,".vcd");
$dumpfile(filename_vcd);
$dumpvars(0,filt_cici_tb);
end
`endif
endmodule |
module sgen_cordic_tb;
time F_CLK_PERIOD = 50;
time S_CLK_PERIOD = 50*`P_ITER;
reg i_rst_an;
reg i_ena;
reg i_clk;
wire s_clk;
reg f_clk;
reg data_ready=1'b0;
integer counter;
integer error_count=0;
reg [8*64:1] filename_vcd;
// READ-IN MATLAB STIMULI FILE
reg [8*64:1] filename_mat_inp;
integer fid_mat_inp;
integer status_mat_inp;
// READ-IN MATLAB RESPONSE FILE
reg [8*64:1] filename_mat_oup;
integer fid_mat_oup;
integer status_mat_oup;
// READ-IN MATLAB RESPONSE FILE
reg [8*64:1] filename_mat_dbg;
integer fid_mat_dbg;
integer status_mat_dbg;
// MATLAB DEBUG OUTPUTS
reg signed [`P_XY_WIDTH+$clog2(`P_ITER)-1:0] o_x_mat;
reg signed [`P_XY_WIDTH+$clog2(`P_ITER)-1:0] o_y_mat;
reg signed [`P_Z_WIDTH +$clog2(`P_ITER)-1:0] o_z_mat;
reg signed [1 :0] o_d_mat;
reg signed [`P_XY_WIDTH-1:0] i_x;
reg signed [`P_XY_WIDTH-1:0] i_y;
reg signed [`P_Z_WIDTH-1 :0] i_z;
reg signed [`P_XY_WIDTH+$clog2(`P_ITER)-1:0] o_x_a_mat;
reg signed [`P_XY_WIDTH-1:0] o_y_r_mat;//???? change width based on mode of operation
// -------------------------------------------------------------------
initial
begin
i_rst_an = 1'b1;
#1 i_rst_an = 1'b0;
#(S_CLK_PERIOD-10) i_rst_an = 1'b1;
end
initial
begin
i_ena = 1'b0;
#(S_CLK_PERIOD-1) i_ena = 1'b1;
end
initial f_clk = 1'b1;
always f_clk = #(F_CLK_PERIOD) ~f_clk;
initial counter = 1024;
always @(posedge f_clk)
begin
if (counter < `P_ITER-1)
counter <= counter + 1;
else
counter <= 0;
end
assign s_clk = (counter < `P_ITER/2) ? 1'b0 : 1'b1;
assign #1 i_clk = (`P_IMPL_U_I) ? s_clk : f_clk;
initial
begin: TEXTIO_READ_IN
$display("### INFO: RTL Simulation of FIR Filter.");
$display("### Testcase %d", `TESTCASE);
$sformat(filename_mat_inp,"%s%0d%s","./sim/testcases/stimuli/stimuli_tc_",`TESTCASE,"_mat.dat");
$sformat(filename_mat_oup,"%s%0d%s","./sim/testcases/response/response_tc_",`TESTCASE,"_oup_mat.dat");
$sformat(filename_mat_dbg,"%s%0d%s","./sim/testcases/response/response_tc_",`TESTCASE,"_dbg_mat.dat");
fid_mat_inp = $fopen(filename_mat_inp, "r");
fid_mat_oup = $fopen(filename_mat_oup, "r");
fid_mat_dbg = $fopen(filename_mat_dbg, "r");
if ((fid_mat_inp == `NULL)||(fid_mat_oup == `NULL)) begin
$display("data_file handle was NULL");
$finish;
end
@(posedge data_ready)
begin
$fclose(fid_mat_inp);
$fclose(fid_mat_oup);
$fclose(fid_mat_dbg);
if (error_count>0)
$display("### INFO: Testcase FAILED");
else
$display("### INFO: Testcase PASSED");
$finish;
end
end
always @(posedge s_clk)
begin: MATLAB_STIMULI
if (i_rst_an && i_ena)
status_mat_inp = $fscanf(fid_mat_inp,"%d %d %d\n", i_x, i_y, i_z);
end
always @(negedge s_clk)
begin: MATLAB_RESPONSE
if (i_rst_an && i_ena)
status_mat_oup = $fscanf(fid_mat_oup,"%d %d\n", o_x_a_mat, o_y_r_mat);
end
always @(negedge f_clk)
begin: MATLAB_DEBUG
if (i_rst_an && i_ena)
status_mat_dbg = $fscanf(fid_mat_dbg,"%d %d %d %d\n", o_x_mat, o_y_mat, o_z_mat, o_d_mat);
if ($feof(fid_mat_dbg)) begin
data_ready = 1'b1;
end
end
wire signed [`P_XY_WIDTH-1:0] x_2_gain;
wire signed [`P_XY_WIDTH-1:0] y_2_gain;
sgen_cordic #(
.gp_mode_rot_vec (`P_MODE_ROT_VEC),
.gp_impl_unrolled_iterative (`P_IMPL_U_I),
.gp_nr_iter (`P_ITER),
.gp_angle_width (`P_ATAN_LUT_WIDTH),
.gp_angle_depth (`P_ATAN_LUT_DEPTH),
.gp_xy_width (`P_XY_WIDTH),
.gp_z_width (`P_Z_WIDTH)
) dut (
.i_rst_an(i_rst_an),
.i_ena(i_ena),
.i_clk(i_clk),
.i_x(i_x),
.i_y(i_y),
.i_z(i_z),
.o_x(x_2_gain),
.o_y(y_2_gain),
.o_z(),
.o_done()
);
cordic_gain #(
.gp_mode_rot_vec (`P_MODE_ROT_VEC),
.gp_gain_width (`P_ATAN_GAIN_WIDTH),
.gp_xy_width (`P_XY_WIDTH),
.gp_xy_owidth ()
) gain_compensation (
.i_cordic_x (x_2_gain),
.i_cordic_y (y_2_gain),
.o_cordic_x (),
.o_cordic_y ()
);
`ifdef VCD
initial
begin
$sformat(filename_vcd,"%s%0d%s","sgen_cordic_",`TESTCASE,".vcd");
$dumpfile(filename_vcd);
$dumpvars(0,sgen_cordic_tb);
end
`endif
endmodule |
module filt_cicd_tb;
time CLK_PERIOD = 50;
reg i_rst_an;
reg i_ena;
reg i_clk;
wire s_clk;
reg [`P_INP_DATA_W-1:0] i_data;
wire rdy;
wire signed [`P_OUP_DATA_W-1:0] oup_data;
reg data_ready;
integer error_count=0;
reg [8*64:1] filename_vcd;
// READ-IN MATLAB STIMULI FILE
reg [8*64:1] filename_mat_inp;
integer fid_mat_inp;
integer status_mat_inp;
// READ-IN MATLAB RESPONSE FILE
reg [8*64:1] filename_mat_oup;
integer fid_mat_oup;
integer status_mat_oup;
reg signed [`P_OUP_DATA_W-1:0] o_data_mat;
// -------------------------------------------------------------------
initial
begin
i_rst_an = 1'b1;
#170 i_rst_an = 1'b0;
#205 i_rst_an = 1'b1;
end
initial
begin
i_ena = 1'b0;
#400 i_ena = 1'b1;
end
initial i_clk = 1'b0;
always i_clk = #(CLK_PERIOD) ~i_clk;
assign #1 s_clk = dut.w_sclk;
initial
begin: TEXTIO_READ_IN
$display("### INFO: RTL Simulation of FIR Filter.");
$display("### Testcase %d", `TESTCASE);
$sformat(filename_mat_inp,"%s%0d%s","./sim/testcases/stimuli/stimuli_tc_",`TESTCASE,"_mat.dat");
$sformat(filename_mat_oup,"%s%0d%s","./sim/testcases/response/response_tc_",`TESTCASE,"_mat.dat");
$display("%s",filename_mat_inp);
fid_mat_inp = $fopen(filename_mat_inp, "r");
fid_mat_oup = $fopen(filename_mat_oup, "r");
if ((fid_mat_inp == `NULL)||(fid_mat_oup == `NULL)) begin
$display("data_file handle was NULL");
$finish;
end
@(posedge data_ready)
begin
$fclose(fid_mat_inp);
$fclose(fid_mat_oup);
if (error_count>0)
$display("### INFO: Testcase FAILED");
else
$display("### INFO: Testcase PASSED");
$finish;
end
end
always @(posedge i_clk)
begin: MATLAB_STIMULI
if (i_rst_an && i_ena)
status_mat_inp = $fscanf(fid_mat_inp,"%d\n", i_data);
else
i_data = 'd0;
if ($feof(fid_mat_inp)) begin
data_ready = 1'b1;
end
end
always @(negedge s_clk)
begin: MATLAB_RESPONSE
if (i_rst_an && i_ena)
status_mat_oup = $fscanf(fid_mat_oup,"%d\n", o_data_mat);
else
o_data_mat = 'd0;
end
always @(posedge s_clk)
begin
if (i_rst_an && i_ena)
if (oup_data != o_data_mat)
//else
begin
$error("### RTL = %d, MAT = %d", oup_data, o_data_mat); error_count<= error_count + 1;
end
end
filt_cicd #(
.gp_decimation_factor (`P_DECIMATION),
.gp_order (`P_ORDER),
.gp_diff_delay (`P_DIFF_DELAY),
.gp_phase (`P_PHASE),
.gp_inp_width (`P_INP_DATA_W),
.gp_oup_width ()
) dut (
.i_rst_an (i_rst_an),
.i_ena (i_ena),
.i_clk (i_clk),
.i_data (i_data),
.o_data (oup_data)
);
`ifdef VCD
initial
begin
$sformat(filename_vcd,"%s%0d%s","filt_cicd_",`TESTCASE,".vcd");
$dumpfile(filename_vcd);
$dumpvars(0,filt_cicd_tb);
end
`endif
endmodule |
module Top(
input wire logic reset,
input wire logic clk,
output wire logic tx,
input wire logic rx,
output wire logic led);
logic reset_n;
SyncChain #(.DEFAULT(1'b0)) reset_sync_chain(
.reset_n(~reset),
.clk(clk),
.x(1'b1),
.x_sync(reset_n));
logic rx_sync;
SyncChain #(.DEFAULT(1'b1)) rx_sync_chain(
.reset_n(reset_n),
.clk(clk),
.x(rx),
.x_sync(rx_sync));
Uart uart(
.reset_n(reset_n),
.clk(clk),
.tx(tx),
.rx(rx_sync),
.has_errored(led));
endmodule |
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