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module reqrsp_iso_intf #(
/// Address width of the interface.
parameter int unsigned AddrWidth = 0,
/// Data width of the interface.
parameter int unsigned DataWidth = 0,
/// Bypass.
parameter bit BypassReq = 0,
parameter bit BypassRsp = 0
) (
/// Clock of source clock domain.
input logic src_clk_i,
/// Active low async reset in source domain.
input logic src_rst_ni,
/// Source interface.
REQRSP_BUS src,
/// Clock of destination clock domain.
input logic dst_clk_i,
/// Active low async reset in destination domain.
input logic dst_rst_ni,
/// Destination interface.
REQRSP_BUS dst
);
typedef logic [AddrWidth-1:0] addr_t;
typedef logic [DataWidth-1:0] data_t;
typedef logic [DataWidth/8-1:0] strb_t;
`REQRSP_TYPEDEF_ALL(reqrsp, addr_t, data_t, strb_t)
reqrsp_req_t reqrsp_src_req, reqrsp_dst_req;
reqrsp_rsp_t reqrsp_src_rsp, reqrsp_dst_rsp;
reqrsp_iso #(
.AddrWidth (AddrWidth),
.DataWidth (DataWidth),
.req_t (reqrsp_req_t),
.rsp_t (reqrsp_rsp_t),
.BypassReq (BypassReq),
.BypassRsp (BypassRsp)
) i_reqrsp_iso (
.src_clk_i,
.src_rst_ni,
.src_req_i (reqrsp_src_req),
.src_rsp_o (reqrsp_src_rsp),
.dst_clk_i,
.dst_rst_ni,
.dst_req_o (reqrsp_dst_req),
.dst_rsp_i (reqrsp_dst_rsp)
);
`REQRSP_ASSIGN_TO_REQ(reqrsp_src_req, src)
`REQRSP_ASSIGN_FROM_RESP(src, reqrsp_src_rsp)
`REQRSP_ASSIGN_FROM_REQ(dst, reqrsp_dst_req)
`REQRSP_ASSIGN_TO_RESP(reqrsp_dst_rsp, dst)
endmodule
|
module reqrsp_demux #(
/// Number of input ports.
parameter int unsigned NrPorts = 2,
/// Request type.
parameter type req_t = logic,
/// Response type.
parameter type rsp_t = logic,
/// Amount of outstanding responses. Determines the FIFO size.
parameter int unsigned RespDepth = 8,
// Dependent parameters, DO NOT OVERRIDE!
parameter int unsigned SelectWidth = cf_math_pkg::idx_width(NrPorts),
parameter type select_t = logic [SelectWidth-1:0]
) (
input logic clk_i,
input logic rst_ni,
input select_t slv_select_i,
input req_t slv_req_i,
output rsp_t slv_rsp_o,
output req_t [NrPorts-1:0] mst_req_o,
input rsp_t [NrPorts-1:0] mst_rsp_i
);
logic [NrPorts-1:0] fwd;
logic req_ready, req_valid;
logic fifo_full, fifo_empty;
logic [NrPorts-1:0] fifo_data;
logic push_id_fifo, pop_id_fifo;
// we need space in the return id fifo, silence if no space is available
assign req_valid = ~fifo_full & slv_req_i.q_valid;
assign slv_rsp_o.q_ready = ~fifo_full & req_ready;
// Stream demux (unwrapped because of struct issues)
always_comb begin
for (int i = 0; i < NrPorts; i++) begin
mst_req_o[i].q_valid = '0;
mst_req_o[i].q = slv_req_i.q;
mst_req_o[i].p_ready = fwd[i] ? slv_req_i.p_ready : 1'b0;
end
mst_req_o[slv_select_i].q_valid = req_valid;
end
assign req_ready = mst_rsp_i[slv_select_i].q_ready;
assign push_id_fifo = req_valid & slv_rsp_o.q_ready;
assign pop_id_fifo = slv_rsp_o.p_valid & slv_req_i.p_ready;
for (genvar i = 0; i < NrPorts; i++) begin : gen_fifo_data
assign fifo_data[i] = mst_rsp_i[i].q_ready & mst_req_o[i].q_valid;
end
// Remember selected master for correct forwarding of read data/acknowledge.
fifo_v3 #(
.DATA_WIDTH ( NrPorts ),
.DEPTH ( RespDepth )
) i_id_fifo (
.clk_i,
.rst_ni,
.flush_i (1'b0),
.testmode_i (1'b0),
.full_o (fifo_full),
.empty_o (fifo_empty),
.usage_o ( ),
// Onehot mask.
.data_i (fifo_data),
.push_i (push_id_fifo),
.data_o (fwd),
.pop_i (pop_id_fifo)
);
// Response data routing.
always_comb begin
slv_rsp_o.p = '0;
slv_rsp_o.p_valid = '0;
for (int i = 0; i < NrPorts; i++) begin
if (fwd[i]) begin
slv_rsp_o.p = mst_rsp_i[i].p;
slv_rsp_o.p_valid = mst_rsp_i[i].p_valid;
end
end
end
`ASSERT(SelectStable, slv_req_i.q_valid && !slv_rsp_o.q_ready |=> $stable(slv_select_i))
`ASSERT(SelectInBounds, slv_req_i.q_valid |-> (slv_select_i <= NrPorts))
endmodule
|
module reqrsp_demux_intf #(
/// Number of input ports.
parameter int unsigned NrPorts = 2,
/// Address width of the interface.
parameter int unsigned AddrWidth = 0,
/// Data width of the interface.
parameter int unsigned DataWidth = 0,
/// Amount of outstanding responses. Determines the FIFO size.
parameter int unsigned RespDepth = 8,
// Dependent parameters, DO NOT OVERRIDE!
parameter int unsigned SelectWidth = cf_math_pkg::idx_width(NrPorts),
parameter type select_t = logic [SelectWidth-1:0]
) (
input logic clk_i,
input logic rst_ni,
input select_t slv_select_i,
REQRSP_BUS slv,
REQRSP_BUS mst [NrPorts]
);
typedef logic [AddrWidth-1:0] addr_t;
typedef logic [DataWidth-1:0] data_t;
typedef logic [DataWidth/8-1:0] strb_t;
`REQRSP_TYPEDEF_ALL(reqrsp, addr_t, data_t, strb_t)
reqrsp_req_t reqrsp_slv_req;
reqrsp_rsp_t reqrsp_slv_rsp;
reqrsp_req_t [NrPorts-1:0] reqrsp_mst_req;
reqrsp_rsp_t [NrPorts-1:0] reqrsp_mst_rsp;
reqrsp_demux #(
.NrPorts (NrPorts),
.req_t (reqrsp_req_t),
.rsp_t (reqrsp_rsp_t),
.RespDepth (RespDepth)
) i_reqrsp_demux (
.clk_i,
.rst_ni,
.slv_select_i (slv_select_i),
.slv_req_i (reqrsp_slv_req),
.slv_rsp_o (reqrsp_slv_rsp),
.mst_req_o (reqrsp_mst_req),
.mst_rsp_i (reqrsp_mst_rsp)
);
`REQRSP_ASSIGN_TO_REQ(reqrsp_slv_req, slv)
`REQRSP_ASSIGN_FROM_RESP(slv, reqrsp_slv_rsp)
for (genvar i = 0; i < NrPorts; i++) begin : gen_interface_assignment
`REQRSP_ASSIGN_FROM_REQ(mst[i], reqrsp_mst_req[i])
`REQRSP_ASSIGN_TO_RESP(reqrsp_mst_rsp[i], mst[i])
end
endmodule
|
module reqrsp_mux #(
/// Number of input ports.
parameter int unsigned NrPorts = 2,
/// Address width of the interface.
parameter int unsigned AddrWidth = 0,
/// Data width of the interface.
parameter int unsigned DataWidth = 0,
/// Request type.
parameter type req_t = logic,
/// Response type.
parameter type rsp_t = logic,
/// Amount of outstanding responses. Determines the FIFO size.
parameter int unsigned RespDepth = 8,
/// Cut timing paths on the request path. Incurs a cycle additional latency.
/// Registers are inserted at the slave side.
parameter bit [NrPorts-1:0] RegisterReq = '0
) (
input logic clk_i,
input logic rst_ni,
input req_t [NrPorts-1:0] slv_req_i,
output rsp_t [NrPorts-1:0] slv_rsp_o,
output req_t mst_req_o,
input rsp_t mst_rsp_i
);
typedef logic [AddrWidth-1:0] addr_t;
typedef logic [DataWidth-1:0] data_t;
typedef logic [DataWidth/8-1:0] strb_t;
`REQRSP_TYPEDEF_REQ_CHAN_T(req_chan_t, addr_t, data_t, strb_t)
localparam int unsigned LogNrPorts = cf_math_pkg::idx_width(NrPorts);
logic [NrPorts-1:0] req_valid_masked, req_ready_masked;
logic [LogNrPorts-1:0] idx, idx_rsp;
logic full;
req_chan_t [NrPorts-1:0] req_payload_q;
logic [NrPorts-1:0] req_valid_q, req_ready_q;
// Unforunately we need this signal otherwise the simulator complains about
// multiple driven signals, because some other signals are driven from an
// `always_comb` block.
logic [NrPorts-1:0] slv_rsp_q_ready;
// Optionially cut the incoming path
for (genvar i = 0; i < NrPorts; i++) begin : gen_cuts
spill_register #(
.T (req_chan_t),
.Bypass (!RegisterReq[i])
) i_spill_register_req (
.clk_i,
.rst_ni,
.valid_i (slv_req_i[i].q_valid),
.ready_o (slv_rsp_q_ready[i]),
.data_i (slv_req_i[i].q),
.valid_o (req_valid_q[i]),
.ready_i (req_ready_masked[i]),
.data_o (req_payload_q[i])
);
end
// We need to silence the handshake in case the fifo is full and we can't
// accept more transactions.
for (genvar i = 0; i < NrPorts; i++) begin : gen_req_valid_masked
assign req_valid_masked[i] = req_valid_q[i] & ~full;
assign req_ready_masked[i] = req_ready_q[i] & ~full;
end
/// Arbitrate on instruction request port
rr_arb_tree #(
.NumIn (NrPorts),
.DataType (req_chan_t),
.AxiVldRdy (1'b1),
.LockIn (1'b1)
) i_q_mux (
.clk_i,
.rst_ni,
.flush_i (1'b0),
.rr_i ('0),
.req_i (req_valid_masked),
.gnt_o (req_ready_q),
.data_i (req_payload_q),
.gnt_i (mst_rsp_i.q_ready),
.req_o (mst_req_o.q_valid),
.data_o (mst_req_o.q),
.idx_o ()
);
// De-generate version does not need a fifo. We always know where to route
// back the responses.
if (NrPorts == 1) begin : gen_single_port
assign idx_rsp = 0;
assign full = 1'b0;
end else begin : gen_multi_port
// For the "normal" case we need to safe the arbitration decision. We so by
// converting the handshake into a binary signal which we save for response
// routing.
onehot_to_bin #(
.ONEHOT_WIDTH (NrPorts)
) i_onehot_to_bin (
.onehot (req_valid_q & req_ready_q),
.bin (idx)
);
// Safe the arbitration decision.
fifo_v3 #(
.DATA_WIDTH (LogNrPorts),
.DEPTH (RespDepth)
) i_resp_fifo (
.clk_i,
.rst_ni,
.flush_i (1'b0),
.testmode_i (1'b0),
.full_o (full),
.empty_o (),
.usage_o (),
.data_i (idx),
.push_i (mst_req_o.q_valid & mst_rsp_i.q_ready),
.data_o (idx_rsp),
.pop_i (mst_req_o.p_ready & mst_rsp_i.p_valid)
);
end
// Output Mux
always_comb begin
for (int i = 0; i < NrPorts; i++) begin
slv_rsp_o[i].p_valid = '0;
slv_rsp_o[i].q_ready = slv_rsp_q_ready[i];
slv_rsp_o[i].p = mst_rsp_i.p;
end
slv_rsp_o[idx_rsp].p_valid = mst_rsp_i.p_valid;
end
assign mst_req_o.p_ready = slv_req_i[idx_rsp].p_ready;
endmodule
|
module reqrsp_mux_intf #(
/// Number of input ports.
parameter int unsigned NrPorts = 2,
/// Address width of the interface.
parameter int unsigned AddrWidth = 0,
/// Data width of the interface.
parameter int unsigned DataWidth = 0,
/// Amount of outstanding responses. Determines the FIFO size.
parameter int unsigned RespDepth = 8,
/// Cut timing paths on the request path. Incurs a cycle additional latency.
/// Registers are inserted at the slave side.
parameter bit [NrPorts-1:0] RegisterReq = '0
) (
input logic clk_i,
input logic rst_ni,
REQRSP_BUS slv [NrPorts],
REQRSP_BUS mst
);
typedef logic [AddrWidth-1:0] addr_t;
typedef logic [DataWidth-1:0] data_t;
typedef logic [DataWidth/8-1:0] strb_t;
`REQRSP_TYPEDEF_ALL(reqrsp, addr_t, data_t, strb_t)
reqrsp_req_t [NrPorts-1:0] reqrsp_slv_req;
reqrsp_rsp_t [NrPorts-1:0] reqrsp_slv_rsp;
reqrsp_req_t reqrsp_mst_req;
reqrsp_rsp_t reqrsp_mst_rsp;
reqrsp_mux #(
.NrPorts (NrPorts),
.AddrWidth (AddrWidth),
.DataWidth (DataWidth),
.req_t (reqrsp_req_t),
.rsp_t (reqrsp_rsp_t),
.RespDepth (RespDepth),
.RegisterReq (RegisterReq)
) i_reqrsp_mux (
.clk_i,
.rst_ni,
.slv_req_i (reqrsp_slv_req),
.slv_rsp_o (reqrsp_slv_rsp),
.mst_req_o (reqrsp_mst_req),
.mst_rsp_i (reqrsp_mst_rsp)
);
for (genvar i = 0; i < NrPorts; i++) begin : gen_interface_assignment
`REQRSP_ASSIGN_TO_REQ(reqrsp_slv_req[i], slv[i])
`REQRSP_ASSIGN_FROM_RESP(slv[i], reqrsp_slv_rsp[i])
end
`REQRSP_ASSIGN_FROM_REQ(mst, reqrsp_mst_req)
`REQRSP_ASSIGN_TO_RESP(reqrsp_mst_rsp, mst)
endmodule
|
module mempool_dma #(
parameter int unsigned AddrWidth = 32,
parameter int unsigned DataWidth = 32,
parameter int unsigned NumBackends = 1,
/// AXI4+ATOP request struct definition.
parameter type axi_lite_req_t = logic,
/// AXI4+ATOP response struct definition.
parameter type axi_lite_rsp_t = logic,
/// Arbitrary 1D burst request definition:
/// - `id`: the AXI id used - this id should be constant, as the DMA does not support reordering
/// - `src`, `dst`: source and destination address, same width as the AXI 4 channels
/// - `num_bytes`: the length of the contiguous 1D transfer requested, can be up to 32/64 bit long
/// num_bytes will be interpreted as an unsigned number
/// A value of 0 will cause the backend to discard the transfer prematurely
/// - `src_cache`, `dst_cache`: the configuration of the cache fields in the AX beats
/// - `src_burst`, `dst_burst`: currently only incremental bursts are supported (`2'b01`)
/// - `decouple_rw`: if set to true, there is no longer exactly one AXI write_request issued for
/// every read request. This mode can improve performance of unaligned transfers when crossing
/// the AXI page boundaries.
/// - `deburst`: if set, the DMA will split all bursts in single transfers
/// - `serialize`: if set, the DMA will only send AX belonging to a given Arbitrary 1D burst request
/// at a time. This is default behavior to prevent deadlocks. Setting `serialize` to
/// zero violates the AXI4+ATOP specification.
parameter type burst_req_t = logic,
/// Give each DMA backend a unique id
parameter int unsigned DmaIdWidth = -1
) (
input logic clk_i,
input logic rst_ni,
input axi_lite_req_t config_req_i,
output axi_lite_rsp_t config_res_o,
output burst_req_t burst_req_o,
output logic valid_o,
input logic ready_i,
input logic backend_idle_i,
input logic trans_complete_i,
output logic [DmaIdWidth-1:0] dma_id_o
);
// import mempool_dma_frontend_reg_pkg::BlockAw;
// import mempool_dma_frontend_reg_pkg::mempool_dma_frontend_reg2hw_t;
// import mempool_dma_frontend_reg_pkg::mempool_dma_frontend_hw2reg_t;
import mempool_dma_frontend_reg_pkg::*;
`REG_BUS_TYPEDEF_ALL(ctrl_reg, logic[BlockAw-1:0], logic[DataWidth-1:0], logic[DataWidth/8-1:0]);
ctrl_reg_req_t ctrl_reg_req;
ctrl_reg_rsp_t ctrl_reg_rsp;
mempool_dma_frontend_reg2hw_t ctrl_reg2hw;
mempool_dma_frontend_hw2reg_t ctrl_hw2reg;
logic trans_complete_d, trans_complete_q;
`FF(trans_complete_q, trans_complete_d, '0, clk_i, rst_ni)
always_comb begin
trans_complete_d = trans_complete_q;
if (trans_complete_i) begin
trans_complete_d = 1'b1;
end
if (valid_o) begin
trans_complete_d = 1'b0;
end
end
assign ctrl_hw2reg = '{
status : backend_idle_i,
next_id : 1'b0,
done : trans_complete_q
};
axi_lite_to_reg #(
.ADDR_WIDTH (AddrWidth ),
.DATA_WIDTH (DataWidth ),
.BUFFER_DEPTH (1 ),
.DECOUPLE_W (0 ),
.axi_lite_req_t(axi_lite_req_t),
.axi_lite_rsp_t(axi_lite_rsp_t),
.reg_req_t (ctrl_reg_req_t),
.reg_rsp_t (ctrl_reg_rsp_t)
) i_axi_lite_to_reg (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
.axi_lite_req_i(config_req_i),
.axi_lite_rsp_o(config_res_o),
.reg_req_o (ctrl_reg_req),
.reg_rsp_i (ctrl_reg_rsp)
);
mempool_dma_frontend_reg_top #(
.reg_req_t(ctrl_reg_req_t),
.reg_rsp_t(ctrl_reg_rsp_t)
) i_mempool_dma_frontend_reg_top (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
.reg_req_i(ctrl_reg_req),
.reg_rsp_o(ctrl_reg_rsp),
.reg2hw (ctrl_reg2hw ),
.hw2reg (ctrl_hw2reg ),
.devmode_i(1'b0 )
);
assign burst_req_o = '{
id : 0,
src : ctrl_reg2hw.src_addr,
dst : ctrl_reg2hw.dst_addr,
num_bytes : ctrl_reg2hw.num_bytes,
cache_src : axi_pkg::CACHE_MODIFIABLE,
cache_dst : axi_pkg::CACHE_MODIFIABLE,
burst_src : axi_pkg::BURST_INCR,
burst_dst : axi_pkg::BURST_INCR,
decouple_rw : 1'b1,
deburst : 1'b0,
serialize : 1'b0
};
always_comb begin
valid_o = '0;
if (ctrl_reg2hw.next_id.re) begin
valid_o = 1'b1;
if (!ready_i) begin
// Store the valid request and stall upstream
// TODO config_res_o.raedy = 0;
end
// TODO stall ctrl_reg_req, ctrl_reg_rsp interface with ready_i
end
end
assign dma_id_o = '0;
// pragma translate_off
integer cycle;
integer transfer;
integer size;
integer f;
string str;
/* verilator lint_off BLKSEQ */
always_ff @(posedge clk_i or negedge rst_ni) begin
if (!rst_ni) begin
cycle = 0;
size = 0;
transfer = 0;
end else begin
if (valid_o && ready_i) begin
cycle = 0;
transfer = 1;
size = burst_req_o.num_bytes;
str = $sformatf("[mempool_dma] Launch request of %08d bytes\n", size);
f = $fopen("dma.log", "a");
$fwrite(f, str);
$fclose(f);
end else begin
cycle = cycle + 1;
end
if (transfer == 1 && trans_complete_i == 1) begin
transfer = 0;
str = "[mempool_dma] Finished request\n";
str = $sformatf("%s[mempool_dma] Duration: %08d cycles, %08.8f bytes/cycle\n", str, cycle, size/cycle);
f = $fopen("dma.log", "a");
$fwrite(f, str);
$fclose(f);
end
end
end
// pragma translate_on
endmodule : mempool_dma
|
module soc_system_irq_mapper
(
// -------------------
// Clock & Reset
// -------------------
input clk,
input reset,
// -------------------
// IRQ Receivers
// -------------------
input receiver0_irq,
input receiver1_irq,
input receiver2_irq,
// -------------------
// Command Source (Output)
// -------------------
output reg [2 : 0] sender_irq
);
always @* begin
sender_irq = 0;
sender_irq[2] = receiver0_irq;
sender_irq[1] = receiver1_irq;
sender_irq[0] = receiver2_irq;
end
endmodule
|
module soc_system_hps_0_fpga_interfaces(
// h2f_reset
output wire [1 - 1 : 0 ] h2f_rst_n
// f2h_cold_reset_req
,input wire [1 - 1 : 0 ] f2h_cold_rst_req_n
// f2h_debug_reset_req
,input wire [1 - 1 : 0 ] f2h_dbg_rst_req_n
// f2h_warm_reset_req
,input wire [1 - 1 : 0 ] f2h_warm_rst_req_n
// f2h_stm_hw_events
,input wire [28 - 1 : 0 ] f2h_stm_hwevents
// f2h_axi_clock
,input wire [1 - 1 : 0 ] f2h_axi_clk
// f2h_axi_slave
,input wire [8 - 1 : 0 ] f2h_AWID
,input wire [32 - 1 : 0 ] f2h_AWADDR
,input wire [4 - 1 : 0 ] f2h_AWLEN
,input wire [3 - 1 : 0 ] f2h_AWSIZE
,input wire [2 - 1 : 0 ] f2h_AWBURST
,input wire [2 - 1 : 0 ] f2h_AWLOCK
,input wire [4 - 1 : 0 ] f2h_AWCACHE
,input wire [3 - 1 : 0 ] f2h_AWPROT
,input wire [1 - 1 : 0 ] f2h_AWVALID
,output wire [1 - 1 : 0 ] f2h_AWREADY
,input wire [5 - 1 : 0 ] f2h_AWUSER
,input wire [8 - 1 : 0 ] f2h_WID
,input wire [64 - 1 : 0 ] f2h_WDATA
,input wire [8 - 1 : 0 ] f2h_WSTRB
,input wire [1 - 1 : 0 ] f2h_WLAST
,input wire [1 - 1 : 0 ] f2h_WVALID
,output wire [1 - 1 : 0 ] f2h_WREADY
,output wire [8 - 1 : 0 ] f2h_BID
,output wire [2 - 1 : 0 ] f2h_BRESP
,output wire [1 - 1 : 0 ] f2h_BVALID
,input wire [1 - 1 : 0 ] f2h_BREADY
,input wire [8 - 1 : 0 ] f2h_ARID
,input wire [32 - 1 : 0 ] f2h_ARADDR
,input wire [4 - 1 : 0 ] f2h_ARLEN
,input wire [3 - 1 : 0 ] f2h_ARSIZE
,input wire [2 - 1 : 0 ] f2h_ARBURST
,input wire [2 - 1 : 0 ] f2h_ARLOCK
,input wire [4 - 1 : 0 ] f2h_ARCACHE
,input wire [3 - 1 : 0 ] f2h_ARPROT
,input wire [1 - 1 : 0 ] f2h_ARVALID
,output wire [1 - 1 : 0 ] f2h_ARREADY
,input wire [5 - 1 : 0 ] f2h_ARUSER
,output wire [8 - 1 : 0 ] f2h_RID
,output wire [64 - 1 : 0 ] f2h_RDATA
,output wire [2 - 1 : 0 ] f2h_RRESP
,output wire [1 - 1 : 0 ] f2h_RLAST
,output wire [1 - 1 : 0 ] f2h_RVALID
,input wire [1 - 1 : 0 ] f2h_RREADY
// h2f_lw_axi_clock
,input wire [1 - 1 : 0 ] h2f_lw_axi_clk
// h2f_lw_axi_master
,output wire [12 - 1 : 0 ] h2f_lw_AWID
,output wire [21 - 1 : 0 ] h2f_lw_AWADDR
,output wire [4 - 1 : 0 ] h2f_lw_AWLEN
,output wire [3 - 1 : 0 ] h2f_lw_AWSIZE
,output wire [2 - 1 : 0 ] h2f_lw_AWBURST
,output wire [2 - 1 : 0 ] h2f_lw_AWLOCK
,output wire [4 - 1 : 0 ] h2f_lw_AWCACHE
,output wire [3 - 1 : 0 ] h2f_lw_AWPROT
,output wire [1 - 1 : 0 ] h2f_lw_AWVALID
,input wire [1 - 1 : 0 ] h2f_lw_AWREADY
,output wire [12 - 1 : 0 ] h2f_lw_WID
,output wire [32 - 1 : 0 ] h2f_lw_WDATA
,output wire [4 - 1 : 0 ] h2f_lw_WSTRB
,output wire [1 - 1 : 0 ] h2f_lw_WLAST
,output wire [1 - 1 : 0 ] h2f_lw_WVALID
,input wire [1 - 1 : 0 ] h2f_lw_WREADY
,input wire [12 - 1 : 0 ] h2f_lw_BID
,input wire [2 - 1 : 0 ] h2f_lw_BRESP
,input wire [1 - 1 : 0 ] h2f_lw_BVALID
,output wire [1 - 1 : 0 ] h2f_lw_BREADY
,output wire [12 - 1 : 0 ] h2f_lw_ARID
,output wire [21 - 1 : 0 ] h2f_lw_ARADDR
,output wire [4 - 1 : 0 ] h2f_lw_ARLEN
,output wire [3 - 1 : 0 ] h2f_lw_ARSIZE
,output wire [2 - 1 : 0 ] h2f_lw_ARBURST
,output wire [2 - 1 : 0 ] h2f_lw_ARLOCK
,output wire [4 - 1 : 0 ] h2f_lw_ARCACHE
,output wire [3 - 1 : 0 ] h2f_lw_ARPROT
,output wire [1 - 1 : 0 ] h2f_lw_ARVALID
,input wire [1 - 1 : 0 ] h2f_lw_ARREADY
,input wire [12 - 1 : 0 ] h2f_lw_RID
,input wire [32 - 1 : 0 ] h2f_lw_RDATA
,input wire [2 - 1 : 0 ] h2f_lw_RRESP
,input wire [1 - 1 : 0 ] h2f_lw_RLAST
,input wire [1 - 1 : 0 ] h2f_lw_RVALID
,output wire [1 - 1 : 0 ] h2f_lw_RREADY
// h2f_axi_clock
,input wire [1 - 1 : 0 ] h2f_axi_clk
// h2f_axi_master
,output wire [12 - 1 : 0 ] h2f_AWID
,output wire [30 - 1 : 0 ] h2f_AWADDR
,output wire [4 - 1 : 0 ] h2f_AWLEN
,output wire [3 - 1 : 0 ] h2f_AWSIZE
,output wire [2 - 1 : 0 ] h2f_AWBURST
,output wire [2 - 1 : 0 ] h2f_AWLOCK
,output wire [4 - 1 : 0 ] h2f_AWCACHE
,output wire [3 - 1 : 0 ] h2f_AWPROT
,output wire [1 - 1 : 0 ] h2f_AWVALID
,input wire [1 - 1 : 0 ] h2f_AWREADY
,output wire [12 - 1 : 0 ] h2f_WID
,output wire [64 - 1 : 0 ] h2f_WDATA
,output wire [8 - 1 : 0 ] h2f_WSTRB
,output wire [1 - 1 : 0 ] h2f_WLAST
,output wire [1 - 1 : 0 ] h2f_WVALID
,input wire [1 - 1 : 0 ] h2f_WREADY
,input wire [12 - 1 : 0 ] h2f_BID
,input wire [2 - 1 : 0 ] h2f_BRESP
,input wire [1 - 1 : 0 ] h2f_BVALID
,output wire [1 - 1 : 0 ] h2f_BREADY
,output wire [12 - 1 : 0 ] h2f_ARID
,output wire [30 - 1 : 0 ] h2f_ARADDR
,output wire [4 - 1 : 0 ] h2f_ARLEN
,output wire [3 - 1 : 0 ] h2f_ARSIZE
,output wire [2 - 1 : 0 ] h2f_ARBURST
,output wire [2 - 1 : 0 ] h2f_ARLOCK
,output wire [4 - 1 : 0 ] h2f_ARCACHE
,output wire [3 - 1 : 0 ] h2f_ARPROT
,output wire [1 - 1 : 0 ] h2f_ARVALID
,input wire [1 - 1 : 0 ] h2f_ARREADY
,input wire [12 - 1 : 0 ] h2f_RID
,input wire [64 - 1 : 0 ] h2f_RDATA
,input wire [2 - 1 : 0 ] h2f_RRESP
,input wire [1 - 1 : 0 ] h2f_RLAST
,input wire [1 - 1 : 0 ] h2f_RVALID
,output wire [1 - 1 : 0 ] h2f_RREADY
// f2h_sdram0_data
,input wire [30 - 1 : 0 ] f2h_sdram0_ADDRESS
,input wire [8 - 1 : 0 ] f2h_sdram0_BURSTCOUNT
,output wire [1 - 1 : 0 ] f2h_sdram0_WAITREQUEST
,output wire [32 - 1 : 0 ] f2h_sdram0_READDATA
,output wire [1 - 1 : 0 ] f2h_sdram0_READDATAVALID
,input wire [1 - 1 : 0 ] f2h_sdram0_READ
,input wire [32 - 1 : 0 ] f2h_sdram0_WRITEDATA
,input wire [4 - 1 : 0 ] f2h_sdram0_BYTEENABLE
,input wire [1 - 1 : 0 ] f2h_sdram0_WRITE
// f2h_sdram0_clock
,input wire [1 - 1 : 0 ] f2h_sdram0_clk
// f2h_irq0
,input wire [32 - 1 : 0 ] f2h_irq_p0
// f2h_irq1
,input wire [32 - 1 : 0 ] f2h_irq_p1
);
wire [9 - 1 : 0] intermediate;
assign intermediate[0:0] = ~intermediate[1:1];
assign intermediate[6:6] = intermediate[3:3]|intermediate[5:5];
assign intermediate[2:2] = intermediate[7:7];
assign intermediate[4:4] = intermediate[7:7];
assign intermediate[8:8] = intermediate[7:7];
assign f2h_sdram0_WAITREQUEST[0:0] = intermediate[0:0];
assign intermediate[3:3] = f2h_sdram0_READ[0:0];
assign intermediate[5:5] = f2h_sdram0_WRITE[0:0];
assign intermediate[7:7] = f2h_sdram0_clk[0:0];
cyclonev_hps_interface_clocks_resets clocks_resets(
.f2h_pending_rst_ack({
1'b1 // 0:0
})
,.f2h_warm_rst_req_n({
f2h_warm_rst_req_n[0:0] // 0:0
})
,.f2h_dbg_rst_req_n({
f2h_dbg_rst_req_n[0:0] // 0:0
})
,.h2f_rst_n({
h2f_rst_n[0:0] // 0:0
})
,.f2h_cold_rst_req_n({
f2h_cold_rst_req_n[0:0] // 0:0
})
);
cyclonev_hps_interface_dbg_apb debug_apb(
.DBG_APB_DISABLE({
1'b0 // 0:0
})
,.P_CLK_EN({
1'b0 // 0:0
})
);
cyclonev_hps_interface_stm_event stm_event(
.stm_event({
f2h_stm_hwevents[27:0] // 27:0
})
);
cyclonev_hps_interface_tpiu_trace tpiu(
.traceclk_ctl({
1'b1 // 0:0
})
);
cyclonev_hps_interface_boot_from_fpga boot_from_fpga(
.boot_from_fpga_ready({
1'b0 // 0:0
})
,.boot_from_fpga_on_failure({
1'b0 // 0:0
})
,.bsel_en({
1'b0 // 0:0
})
,.csel_en({
1'b0 // 0:0
})
,.csel({
2'b01 // 1:0
})
,.bsel({
3'b001 // 2:0
})
);
cyclonev_hps_interface_fpga2hps fpga2hps(
.port_size_config({
2'b01 // 1:0
})
,.arsize({
f2h_ARSIZE[2:0] // 2:0
})
,.awuser({
f2h_AWUSER[4:0] // 4:0
})
,.wvalid({
f2h_WVALID[0:0] // 0:0
})
,.rlast({
f2h_RLAST[0:0] // 0:0
})
,.clk({
f2h_axi_clk[0:0] // 0:0
})
,.rresp({
f2h_RRESP[1:0] // 1:0
})
,.arready({
f2h_ARREADY[0:0] // 0:0
})
,.arprot({
f2h_ARPROT[2:0] // 2:0
})
,.araddr({
f2h_ARADDR[31:0] // 31:0
})
,.bvalid({
f2h_BVALID[0:0] // 0:0
})
,.arid({
f2h_ARID[7:0] // 7:0
})
,.bid({
f2h_BID[7:0] // 7:0
})
,.arburst({
f2h_ARBURST[1:0] // 1:0
})
,.arcache({
f2h_ARCACHE[3:0] // 3:0
})
,.awvalid({
f2h_AWVALID[0:0] // 0:0
})
,.wdata({
f2h_WDATA[63:0] // 63:0
})
,.aruser({
f2h_ARUSER[4:0] // 4:0
})
,.rid({
f2h_RID[7:0] // 7:0
})
,.rvalid({
f2h_RVALID[0:0] // 0:0
})
,.wready({
f2h_WREADY[0:0] // 0:0
})
,.awlock({
f2h_AWLOCK[1:0] // 1:0
})
,.bresp({
f2h_BRESP[1:0] // 1:0
})
,.arlen({
f2h_ARLEN[3:0] // 3:0
})
,.awsize({
f2h_AWSIZE[2:0] // 2:0
})
,.awlen({
f2h_AWLEN[3:0] // 3:0
})
,.bready({
f2h_BREADY[0:0] // 0:0
})
,.awid({
f2h_AWID[7:0] // 7:0
})
,.rdata({
f2h_RDATA[63:0] // 63:0
})
,.awready({
f2h_AWREADY[0:0] // 0:0
})
,.arvalid({
f2h_ARVALID[0:0] // 0:0
})
,.wlast({
f2h_WLAST[0:0] // 0:0
})
,.awprot({
f2h_AWPROT[2:0] // 2:0
})
,.awaddr({
f2h_AWADDR[31:0] // 31:0
})
,.wid({
f2h_WID[7:0] // 7:0
})
,.awburst({
f2h_AWBURST[1:0] // 1:0
})
,.awcache({
f2h_AWCACHE[3:0] // 3:0
})
,.arlock({
f2h_ARLOCK[1:0] // 1:0
})
,.rready({
f2h_RREADY[0:0] // 0:0
})
,.wstrb({
f2h_WSTRB[7:0] // 7:0
})
);
cyclonev_hps_interface_hps2fpga_light_weight hps2fpga_light_weight(
.arsize({
h2f_lw_ARSIZE[2:0] // 2:0
})
,.wvalid({
h2f_lw_WVALID[0:0] // 0:0
})
,.rlast({
h2f_lw_RLAST[0:0] // 0:0
})
,.clk({
h2f_lw_axi_clk[0:0] // 0:0
})
,.rresp({
h2f_lw_RRESP[1:0] // 1:0
})
,.arready({
h2f_lw_ARREADY[0:0] // 0:0
})
,.arprot({
h2f_lw_ARPROT[2:0] // 2:0
})
,.araddr({
h2f_lw_ARADDR[20:0] // 20:0
})
,.bvalid({
h2f_lw_BVALID[0:0] // 0:0
})
,.arid({
h2f_lw_ARID[11:0] // 11:0
})
,.bid({
h2f_lw_BID[11:0] // 11:0
})
,.arburst({
h2f_lw_ARBURST[1:0] // 1:0
})
,.arcache({
h2f_lw_ARCACHE[3:0] // 3:0
})
,.awvalid({
h2f_lw_AWVALID[0:0] // 0:0
})
,.wdata({
h2f_lw_WDATA[31:0] // 31:0
})
,.rid({
h2f_lw_RID[11:0] // 11:0
})
,.rvalid({
h2f_lw_RVALID[0:0] // 0:0
})
,.wready({
h2f_lw_WREADY[0:0] // 0:0
})
,.awlock({
h2f_lw_AWLOCK[1:0] // 1:0
})
,.bresp({
h2f_lw_BRESP[1:0] // 1:0
})
,.arlen({
h2f_lw_ARLEN[3:0] // 3:0
})
,.awsize({
h2f_lw_AWSIZE[2:0] // 2:0
})
,.awlen({
h2f_lw_AWLEN[3:0] // 3:0
})
,.bready({
h2f_lw_BREADY[0:0] // 0:0
})
,.awid({
h2f_lw_AWID[11:0] // 11:0
})
,.rdata({
h2f_lw_RDATA[31:0] // 31:0
})
,.awready({
h2f_lw_AWREADY[0:0] // 0:0
})
,.arvalid({
h2f_lw_ARVALID[0:0] // 0:0
})
,.wlast({
h2f_lw_WLAST[0:0] // 0:0
})
,.awprot({
h2f_lw_AWPROT[2:0] // 2:0
})
,.awaddr({
h2f_lw_AWADDR[20:0] // 20:0
})
,.wid({
h2f_lw_WID[11:0] // 11:0
})
,.awcache({
h2f_lw_AWCACHE[3:0] // 3:0
})
,.arlock({
h2f_lw_ARLOCK[1:0] // 1:0
})
,.awburst({
h2f_lw_AWBURST[1:0] // 1:0
})
,.rready({
h2f_lw_RREADY[0:0] // 0:0
})
,.wstrb({
h2f_lw_WSTRB[3:0] // 3:0
})
);
cyclonev_hps_interface_hps2fpga hps2fpga(
.port_size_config({
2'b01 // 1:0
})
,.arsize({
h2f_ARSIZE[2:0] // 2:0
})
,.wvalid({
h2f_WVALID[0:0] // 0:0
})
,.rlast({
h2f_RLAST[0:0] // 0:0
})
,.clk({
h2f_axi_clk[0:0] // 0:0
})
,.rresp({
h2f_RRESP[1:0] // 1:0
})
,.arready({
h2f_ARREADY[0:0] // 0:0
})
,.arprot({
h2f_ARPROT[2:0] // 2:0
})
,.araddr({
h2f_ARADDR[29:0] // 29:0
})
,.bvalid({
h2f_BVALID[0:0] // 0:0
})
,.arid({
h2f_ARID[11:0] // 11:0
})
,.bid({
h2f_BID[11:0] // 11:0
})
,.arburst({
h2f_ARBURST[1:0] // 1:0
})
,.arcache({
h2f_ARCACHE[3:0] // 3:0
})
,.awvalid({
h2f_AWVALID[0:0] // 0:0
})
,.wdata({
h2f_WDATA[63:0] // 63:0
})
,.rid({
h2f_RID[11:0] // 11:0
})
,.rvalid({
h2f_RVALID[0:0] // 0:0
})
,.wready({
h2f_WREADY[0:0] // 0:0
})
,.awlock({
h2f_AWLOCK[1:0] // 1:0
})
,.bresp({
h2f_BRESP[1:0] // 1:0
})
,.arlen({
h2f_ARLEN[3:0] // 3:0
})
,.awsize({
h2f_AWSIZE[2:0] // 2:0
})
,.awlen({
h2f_AWLEN[3:0] // 3:0
})
,.bready({
h2f_BREADY[0:0] // 0:0
})
,.awid({
h2f_AWID[11:0] // 11:0
})
,.rdata({
h2f_RDATA[63:0] // 63:0
})
,.awready({
h2f_AWREADY[0:0] // 0:0
})
,.arvalid({
h2f_ARVALID[0:0] // 0:0
})
,.wlast({
h2f_WLAST[0:0] // 0:0
})
,.awprot({
h2f_AWPROT[2:0] // 2:0
})
,.awaddr({
h2f_AWADDR[29:0] // 29:0
})
,.wid({
h2f_WID[11:0] // 11:0
})
,.awcache({
h2f_AWCACHE[3:0] // 3:0
})
,.arlock({
h2f_ARLOCK[1:0] // 1:0
})
,.awburst({
h2f_AWBURST[1:0] // 1:0
})
,.rready({
h2f_RREADY[0:0] // 0:0
})
,.wstrb({
h2f_WSTRB[7:0] // 7:0
})
);
cyclonev_hps_interface_fpga2sdram f2sdram(
.cmd_data_0({
18'b000000000000000000 // 59:42
,f2h_sdram0_BURSTCOUNT[7:0] // 41:34
,2'b00 // 33:32
,f2h_sdram0_ADDRESS[29:0] // 31:2
,intermediate[5:5] // 1:1
,intermediate[3:3] // 0:0
})
,.cfg_port_width({
12'b000000000000 // 11:0
})
,.rd_valid_0({
f2h_sdram0_READDATAVALID[0:0] // 0:0
})
,.wr_clk_0({
intermediate[4:4] // 0:0
})
,.cfg_cport_type({
12'b000000000011 // 11:0
})
,.wr_data_0({
6'b000000 // 89:84
,f2h_sdram0_BYTEENABLE[3:0] // 83:80
,48'b000000000000000000000000000000000000000000000000 // 79:32
,f2h_sdram0_WRITEDATA[31:0] // 31:0
})
,.cfg_rfifo_cport_map({
16'b0000000000000000 // 15:0
})
,.cfg_cport_wfifo_map({
18'b000000000000000000 // 17:0
})
,.cmd_port_clk_0({
intermediate[8:8] // 0:0
})
,.cfg_cport_rfifo_map({
18'b000000000000000000 // 17:0
})
,.rd_ready_0({
1'b1 // 0:0
})
,.cmd_ready_0({
intermediate[1:1] // 0:0
})
,.rd_clk_0({
intermediate[2:2] // 0:0
})
,.cfg_wfifo_cport_map({
16'b0000000000000000 // 15:0
})
,.wrack_ready_0({
1'b1 // 0:0
})
,.cmd_valid_0({
intermediate[6:6] // 0:0
})
,.rd_data_0({
f2h_sdram0_READDATA[31:0] // 31:0
})
,.cfg_axi_mm_select({
6'b000000 // 5:0
})
);
cyclonev_hps_interface_interrupts interrupts(
.irq({
f2h_irq_p1[31:0] // 63:32
,f2h_irq_p0[31:0] // 31:0
})
);
endmodule
|
module altera_avalon_st_pipeline_stage #(
parameter
SYMBOLS_PER_BEAT = 1,
BITS_PER_SYMBOL = 8,
USE_PACKETS = 0,
USE_EMPTY = 0,
PIPELINE_READY = 1,
// Optional ST signal widths. Value "0" means no such port.
CHANNEL_WIDTH = 0,
ERROR_WIDTH = 0,
// Derived parameters
DATA_WIDTH = SYMBOLS_PER_BEAT * BITS_PER_SYMBOL,
PACKET_WIDTH = 0,
EMPTY_WIDTH = 0
)
(
input clk,
input reset,
output in_ready,
input in_valid,
input [DATA_WIDTH - 1 : 0] in_data,
input [(CHANNEL_WIDTH ? (CHANNEL_WIDTH - 1) : 0) : 0] in_channel,
input [(ERROR_WIDTH ? (ERROR_WIDTH - 1) : 0) : 0] in_error,
input in_startofpacket,
input in_endofpacket,
input [(EMPTY_WIDTH ? (EMPTY_WIDTH - 1) : 0) : 0] in_empty,
input out_ready,
output out_valid,
output [DATA_WIDTH - 1 : 0] out_data,
output [(CHANNEL_WIDTH ? (CHANNEL_WIDTH - 1) : 0) : 0] out_channel,
output [(ERROR_WIDTH ? (ERROR_WIDTH - 1) : 0) : 0] out_error,
output out_startofpacket,
output out_endofpacket,
output [(EMPTY_WIDTH ? (EMPTY_WIDTH - 1) : 0) : 0] out_empty
);
localparam
PAYLOAD_WIDTH =
DATA_WIDTH +
PACKET_WIDTH +
CHANNEL_WIDTH +
EMPTY_WIDTH +
ERROR_WIDTH;
wire [PAYLOAD_WIDTH - 1: 0] in_payload;
wire [PAYLOAD_WIDTH - 1: 0] out_payload;
// Assign in_data and other optional in_* interface signals to in_payload.
assign in_payload[DATA_WIDTH - 1 : 0] = in_data;
generate
// optional packet inputs
if (PACKET_WIDTH) begin
assign in_payload[
DATA_WIDTH + PACKET_WIDTH - 1 :
DATA_WIDTH
] = {in_startofpacket, in_endofpacket};
end
// optional channel input
if (CHANNEL_WIDTH) begin
assign in_payload[
DATA_WIDTH + PACKET_WIDTH + CHANNEL_WIDTH - 1 :
DATA_WIDTH + PACKET_WIDTH
] = in_channel;
end
// optional empty input
if (EMPTY_WIDTH) begin
assign in_payload[
DATA_WIDTH + PACKET_WIDTH + CHANNEL_WIDTH + EMPTY_WIDTH - 1 :
DATA_WIDTH + PACKET_WIDTH + CHANNEL_WIDTH
] = in_empty;
end
// optional error input
if (ERROR_WIDTH) begin
assign in_payload[
DATA_WIDTH + PACKET_WIDTH + CHANNEL_WIDTH + EMPTY_WIDTH + ERROR_WIDTH - 1 :
DATA_WIDTH + PACKET_WIDTH + CHANNEL_WIDTH + EMPTY_WIDTH
] = in_error;
end
endgenerate
altera_avalon_st_pipeline_base #(
.SYMBOLS_PER_BEAT (PAYLOAD_WIDTH),
.BITS_PER_SYMBOL (1),
.PIPELINE_READY (PIPELINE_READY)
) core (
.clk (clk),
.reset (reset),
.in_ready (in_ready),
.in_valid (in_valid),
.in_data (in_payload),
.out_ready (out_ready),
.out_valid (out_valid),
.out_data (out_payload)
);
// Assign out_data and other optional out_* interface signals from out_payload.
assign out_data = out_payload[DATA_WIDTH - 1 : 0];
generate
// optional packet outputs
if (PACKET_WIDTH) begin
assign {out_startofpacket, out_endofpacket} =
out_payload[DATA_WIDTH + PACKET_WIDTH - 1 : DATA_WIDTH];
end else begin
// Avoid a "has no driver" warning.
assign {out_startofpacket, out_endofpacket} = 2'b0;
end
// optional channel output
if (CHANNEL_WIDTH) begin
assign out_channel = out_payload[
DATA_WIDTH + PACKET_WIDTH + CHANNEL_WIDTH - 1 :
DATA_WIDTH + PACKET_WIDTH
];
end else begin
// Avoid a "has no driver" warning.
assign out_channel = 1'b0;
end
// optional empty output
if (EMPTY_WIDTH) begin
assign out_empty = out_payload[
DATA_WIDTH + PACKET_WIDTH + CHANNEL_WIDTH + EMPTY_WIDTH - 1 :
DATA_WIDTH + PACKET_WIDTH + CHANNEL_WIDTH
];
end else begin
// Avoid a "has no driver" warning.
assign out_empty = 1'b0;
end
// optional error output
if (ERROR_WIDTH) begin
assign out_error = out_payload[
DATA_WIDTH + PACKET_WIDTH + CHANNEL_WIDTH + EMPTY_WIDTH + ERROR_WIDTH - 1 :
DATA_WIDTH + PACKET_WIDTH + CHANNEL_WIDTH + EMPTY_WIDTH
];
end else begin
// Avoid a "has no driver" warning.
assign out_error = 1'b0;
end
endgenerate
endmodule
|
module soc_system_mm_interconnect_0_router_default_decode
#(
parameter DEFAULT_CHANNEL = 0,
DEFAULT_WR_CHANNEL = -1,
DEFAULT_RD_CHANNEL = -1,
DEFAULT_DESTID = 0
)
(output [87 - 87 : 0] default_destination_id,
output [2-1 : 0] default_wr_channel,
output [2-1 : 0] default_rd_channel,
output [2-1 : 0] default_src_channel
);
assign default_destination_id =
DEFAULT_DESTID[87 - 87 : 0];
generate
if (DEFAULT_CHANNEL == -1) begin : no_default_channel_assignment
assign default_src_channel = '0;
end
else begin : default_channel_assignment
assign default_src_channel = 2'b1 << DEFAULT_CHANNEL;
end
endgenerate
generate
if (DEFAULT_RD_CHANNEL == -1) begin : no_default_rw_channel_assignment
assign default_wr_channel = '0;
assign default_rd_channel = '0;
end
else begin : default_rw_channel_assignment
assign default_wr_channel = 2'b1 << DEFAULT_WR_CHANNEL;
assign default_rd_channel = 2'b1 << DEFAULT_RD_CHANNEL;
end
endgenerate
endmodule
|
module soc_system_mm_interconnect_0_router
(
// -------------------
// Clock & Reset
// -------------------
input clk,
input reset,
// -------------------
// Command Sink (Input)
// -------------------
input sink_valid,
input [112-1 : 0] sink_data,
input sink_startofpacket,
input sink_endofpacket,
output sink_ready,
// -------------------
// Command Source (Output)
// -------------------
output src_valid,
output reg [112-1 : 0] src_data,
output reg [2-1 : 0] src_channel,
output src_startofpacket,
output src_endofpacket,
input src_ready
);
// -------------------------------------------------------
// Local parameters and variables
// -------------------------------------------------------
localparam PKT_ADDR_H = 56;
localparam PKT_ADDR_L = 36;
localparam PKT_DEST_ID_H = 87;
localparam PKT_DEST_ID_L = 87;
localparam PKT_PROTECTION_H = 102;
localparam PKT_PROTECTION_L = 100;
localparam ST_DATA_W = 112;
localparam ST_CHANNEL_W = 2;
localparam DECODER_TYPE = 0;
localparam PKT_TRANS_WRITE = 59;
localparam PKT_TRANS_READ = 60;
localparam PKT_ADDR_W = PKT_ADDR_H-PKT_ADDR_L + 1;
localparam PKT_DEST_ID_W = PKT_DEST_ID_H-PKT_DEST_ID_L + 1;
// -------------------------------------------------------
// Figure out the number of bits to mask off for each slave span
// during address decoding
// -------------------------------------------------------
localparam PAD0 = log2ceil(64'h40000 - 64'h0);
// -------------------------------------------------------
// Work out which address bits are significant based on the
// address range of the slaves. If the required width is too
// large or too small, we use the address field width instead.
// -------------------------------------------------------
localparam ADDR_RANGE = 64'h40000;
localparam RANGE_ADDR_WIDTH = log2ceil(ADDR_RANGE);
localparam OPTIMIZED_ADDR_H = (RANGE_ADDR_WIDTH > PKT_ADDR_W) ||
(RANGE_ADDR_WIDTH == 0) ?
PKT_ADDR_H :
PKT_ADDR_L + RANGE_ADDR_WIDTH - 1;
localparam RG = RANGE_ADDR_WIDTH;
localparam REAL_ADDRESS_RANGE = OPTIMIZED_ADDR_H - PKT_ADDR_L;
// -------------------------------------------------------
// Pass almost everything through, untouched
// -------------------------------------------------------
assign sink_ready = src_ready;
assign src_valid = sink_valid;
assign src_startofpacket = sink_startofpacket;
assign src_endofpacket = sink_endofpacket;
wire [PKT_DEST_ID_W-1:0] default_destid;
wire [2-1 : 0] default_src_channel;
soc_system_mm_interconnect_0_router_default_decode the_default_decode(
.default_destination_id (default_destid),
.default_wr_channel (),
.default_rd_channel (),
.default_src_channel (default_src_channel)
);
always @* begin
src_data = sink_data;
src_channel = default_src_channel;
src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = default_destid;
// --------------------------------------------------
// Address Decoder
// Sets the channel and destination ID based on the address
// --------------------------------------------------
// ( 0 .. 40000 )
src_channel = 2'b1;
src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 0;
end
// --------------------------------------------------
// Ceil(log2()) function
// --------------------------------------------------
function integer log2ceil;
input reg[65:0] val;
reg [65:0] i;
begin
i = 1;
log2ceil = 0;
while (i < val) begin
log2ceil = log2ceil + 1;
i = i << 1;
end
end
endfunction
endmodule
|
module soc_system_mm_interconnect_0_rsp_demux
(
// -------------------
// Sink
// -------------------
input [1-1 : 0] sink_valid,
input [112-1 : 0] sink_data, // ST_DATA_W=112
input [2-1 : 0] sink_channel, // ST_CHANNEL_W=2
input sink_startofpacket,
input sink_endofpacket,
output sink_ready,
// -------------------
// Sources
// -------------------
output reg src0_valid,
output reg [112-1 : 0] src0_data, // ST_DATA_W=112
output reg [2-1 : 0] src0_channel, // ST_CHANNEL_W=2
output reg src0_startofpacket,
output reg src0_endofpacket,
input src0_ready,
output reg src1_valid,
output reg [112-1 : 0] src1_data, // ST_DATA_W=112
output reg [2-1 : 0] src1_channel, // ST_CHANNEL_W=2
output reg src1_startofpacket,
output reg src1_endofpacket,
input src1_ready,
// -------------------
// Clock & Reset
// -------------------
(*altera_attribute = "-name MESSAGE_DISABLE 15610" *) // setting message suppression on clk
input clk,
(*altera_attribute = "-name MESSAGE_DISABLE 15610" *) // setting message suppression on reset
input reset
);
localparam NUM_OUTPUTS = 2;
wire [NUM_OUTPUTS - 1 : 0] ready_vector;
// -------------------
// Demux
// -------------------
always @* begin
src0_data = sink_data;
src0_startofpacket = sink_startofpacket;
src0_endofpacket = sink_endofpacket;
src0_channel = sink_channel >> NUM_OUTPUTS;
src0_valid = sink_channel[0] && sink_valid;
src1_data = sink_data;
src1_startofpacket = sink_startofpacket;
src1_endofpacket = sink_endofpacket;
src1_channel = sink_channel >> NUM_OUTPUTS;
src1_valid = sink_channel[1] && sink_valid;
end
// -------------------
// Backpressure
// -------------------
assign ready_vector[0] = src0_ready;
assign ready_vector[1] = src1_ready;
assign sink_ready = |(sink_channel & ready_vector);
endmodule
|
module hps_sdram_p0 (
global_reset_n,
soft_reset_n,
csr_soft_reset_req,
parallelterminationcontrol,
seriesterminationcontrol,
pll_mem_clk,
pll_write_clk,
pll_write_clk_pre_phy_clk,
pll_addr_cmd_clk,
pll_avl_clk,
pll_config_clk,
pll_mem_phy_clk,
afi_phy_clk,
pll_avl_phy_clk,
pll_locked,
dll_pll_locked,
dll_delayctrl,
dll_clk,
ctl_reset_n,
afi_reset_n,
afi_reset_export_n,
afi_clk,
afi_half_clk,
afi_addr,
afi_ba,
afi_cke,
afi_cs_n,
afi_ras_n,
afi_we_n,
afi_cas_n,
afi_rst_n,
afi_odt,
afi_mem_clk_disable,
afi_dqs_burst,
afi_wdata,
afi_wdata_valid,
afi_dm,
afi_rdata,
afi_rdata_en,
afi_rdata_en_full,
afi_rdata_valid,
afi_cal_success,
afi_cal_fail,
afi_wlat,
afi_rlat,
avl_read,
avl_write,
avl_address,
avl_writedata,
avl_waitrequest,
avl_readdata,
cfg_addlat,
cfg_bankaddrwidth,
cfg_caswrlat,
cfg_coladdrwidth,
cfg_csaddrwidth,
cfg_devicewidth,
cfg_dramconfig,
cfg_interfacewidth,
cfg_rowaddrwidth,
cfg_tcl,
cfg_tmrd,
cfg_trefi,
cfg_trfc,
cfg_twr,
io_intaddrdout,
io_intbadout,
io_intcasndout,
io_intckdout,
io_intckedout,
io_intckndout,
io_intcsndout,
io_intdmdout,
io_intdqdin,
io_intdqdout,
io_intdqoe,
io_intdqsbdout,
io_intdqsboe,
io_intdqsdout,
io_intdqslogicdqsena,
io_intdqslogicfiforeset,
io_intdqslogicincrdataen,
io_intdqslogicincwrptr,
io_intdqslogicoct,
io_intdqslogicrdatavalid,
io_intdqslogicreadlatency,
io_intdqsoe,
io_intodtdout,
io_intrasndout,
io_intresetndout,
io_intwendout,
io_intafirlat,
io_intafiwlat,
io_intaficalfail,
io_intaficalsuccess,
mem_a,
mem_ba,
mem_ck,
mem_ck_n,
mem_cke,
mem_cs_n,
mem_dm,
mem_ras_n,
mem_cas_n,
mem_we_n,
mem_dq,
mem_dqs,
mem_dqs_n,
mem_reset_n,
mem_odt,
avl_clk,
scc_clk,
avl_reset_n,
scc_reset_n,
scc_data,
scc_dqs_ena,
scc_dqs_io_ena,
scc_dq_ena,
scc_dm_ena,
scc_upd,
capture_strobe_tracking,
phy_clk,
ctl_clk,
phy_reset_n
);
// ********************************************************************************************************************************
// BEGIN PARAMETER SECTION
// All parameters default to "" will have their values passed in from higher level wrapper with the controller and driver.
parameter DEVICE_FAMILY = "Cyclone V";
parameter IS_HHP_HPS = "true";
// choose between abstract (fast) and regular model
`ifndef ALTERA_ALT_MEM_IF_PHY_FAST_SIM_MODEL
`define ALTERA_ALT_MEM_IF_PHY_FAST_SIM_MODEL 0
`endif
parameter ALTERA_ALT_MEM_IF_PHY_FAST_SIM_MODEL = `ALTERA_ALT_MEM_IF_PHY_FAST_SIM_MODEL;
localparam FAST_SIM_MODEL = ALTERA_ALT_MEM_IF_PHY_FAST_SIM_MODEL;
// On-chip termination
parameter OCT_TERM_CONTROL_WIDTH = 16;
// PHY-Memory Interface
// Memory device specific parameters, they are set according to the memory spec.
parameter MEM_IF_ADDR_WIDTH = 15;
parameter MEM_IF_BANKADDR_WIDTH = 3;
parameter MEM_IF_CK_WIDTH = 1;
parameter MEM_IF_CLK_EN_WIDTH = 1;
parameter MEM_IF_CS_WIDTH = 1;
parameter MEM_IF_DM_WIDTH = 4;
parameter MEM_IF_CONTROL_WIDTH = 1;
parameter MEM_IF_DQ_WIDTH = 32;
parameter MEM_IF_DQS_WIDTH = 4;
parameter MEM_IF_READ_DQS_WIDTH = 4;
parameter MEM_IF_WRITE_DQS_WIDTH = 4;
parameter MEM_IF_ODT_WIDTH = 1;
// DLL Interface
parameter DLL_DELAY_CTRL_WIDTH = 7;
parameter SCC_DATA_WIDTH = 1;
// Read Datapath parameters, the values should not be changed unless the intention is to change the architecture.
// Read valid prediction FIFO
parameter READ_VALID_FIFO_SIZE = 16;
// Data resynchronization FIFO
parameter READ_FIFO_SIZE = 8;
parameter MR1_ODS = 0;
parameter MR1_RTT = 3;
parameter MR2_RTT_WR = 0;
// The DLL offset control width
parameter DLL_OFFSET_CTRL_WIDTH = 6;
parameter CALIB_REG_WIDTH = 8;
parameter TB_PROTOCOL = "DDR3";
parameter TB_MEM_CLK_FREQ = "400.0";
parameter TB_RATE = "FULL";
parameter TB_MEM_DQ_WIDTH = "32";
parameter TB_MEM_DQS_WIDTH = "4";
parameter TB_PLL_DLL_MASTER = "true";
parameter FAST_SIM_CALIBRATION = "false";
parameter AC_ROM_INIT_FILE_NAME = "hps_AC_ROM.hex";
parameter INST_ROM_INIT_FILE_NAME = "hps_inst_ROM.hex";
localparam SIM_FILESET = ("false" == "true");
// END PARAMETER SECTION
// ********************************************************************************************************************************
// ********************************************************************************************************************************
// BEGIN PORT SECTION
// When the PHY is selected to be a PLL/DLL SLAVE, the PLL and DLL are instantied at the top level of the example design
input pll_mem_clk;
input pll_write_clk;
input pll_write_clk_pre_phy_clk;
input pll_addr_cmd_clk;
input pll_avl_clk;
input pll_config_clk;
input pll_locked;
input pll_mem_phy_clk;
input afi_phy_clk;
input pll_avl_phy_clk;
input [DLL_DELAY_CTRL_WIDTH-1:0] dll_delayctrl;
output dll_pll_locked;
output dll_clk;
// Reset Interface, AFI 2.0
input global_reset_n; // Resets (active-low) the whole system (all PHY logic + PLL)
input soft_reset_n; // Resets (active-low) PHY logic only, PLL is NOT reset
output afi_reset_n; // Asynchronously asserted and synchronously de-asserted on afi_clk domain
output afi_reset_export_n; // Asynchronously asserted and synchronously de-asserted on afi_clk domain
// should be used to reset system level afi_clk domain logic
output ctl_reset_n; // Asynchronously asserted and synchronously de-asserted on ctl_clk domain
// should be used by hard controller only
input csr_soft_reset_req; // Reset request (active_high) being driven by external debug master
// OCT termination control signals
input [OCT_TERM_CONTROL_WIDTH-1:0] parallelterminationcontrol;
input [OCT_TERM_CONTROL_WIDTH-1:0] seriesterminationcontrol;
// PHY-Controller Interface, AFI 2.0
// Control Interface
input [19:0] afi_addr; // address
input [2:0] afi_ba; // bank
input [1:0] afi_cke; // clock enable
input [1:0] afi_cs_n; // chip select
input [0:0] afi_ras_n;
input [0:0] afi_we_n;
input [0:0] afi_cas_n;
input [1:0] afi_odt;
input [0:0] afi_rst_n;
input [0:0] afi_mem_clk_disable;
// Write data interface
input [4:0] afi_dqs_burst;
input [79:0] afi_wdata; // write data
input [4:0] afi_wdata_valid; // write data valid, used to maintain write latency required by protocol spec
input [9:0] afi_dm; // write data mask
// Read data interface
output [79:0] afi_rdata; // read data
input [4:0] afi_rdata_en; // read enable, used to maintain the read latency calibrated by PHY
input [4:0] afi_rdata_en_full; // read enable full burst, used to create DQS enable
output [0:0] afi_rdata_valid; // read data valid
// Status interface
output afi_cal_success; // calibration success
output afi_cal_fail; // calibration failure
output [3:0] afi_wlat;
output [4:0] afi_rlat;
// Avalon interface to the sequencer
input [15:0] avl_address;
input avl_read;
output [31:0] avl_readdata;
output avl_waitrequest;
input avl_write;
input [31:0] avl_writedata;
// Configuration interface to the memory controller
input [7:0] cfg_addlat;
input [7:0] cfg_bankaddrwidth;
input [7:0] cfg_caswrlat;
input [7:0] cfg_coladdrwidth;
input [7:0] cfg_csaddrwidth;
input [7:0] cfg_devicewidth;
input [23:0] cfg_dramconfig;
input [7:0] cfg_interfacewidth;
input [7:0] cfg_rowaddrwidth;
input [7:0] cfg_tcl;
input [7:0] cfg_tmrd;
input [15:0] cfg_trefi;
input [7:0] cfg_trfc;
input [7:0] cfg_twr;
// IO/bypass interface to the core (or soft controller)
input [63:0] io_intaddrdout;
input [11:0] io_intbadout;
input [3:0] io_intcasndout;
input [3:0] io_intckdout;
input [7:0] io_intckedout;
input [3:0] io_intckndout;
input [7:0] io_intcsndout;
input [19:0] io_intdmdout;
output [179:0] io_intdqdin;
input [179:0] io_intdqdout;
input [89:0] io_intdqoe;
input [19:0] io_intdqsbdout;
input [9:0] io_intdqsboe;
input [19:0] io_intdqsdout;
input [9:0] io_intdqslogicdqsena;
input [4:0] io_intdqslogicfiforeset;
input [9:0] io_intdqslogicincrdataen;
input [9:0] io_intdqslogicincwrptr;
input [9:0] io_intdqslogicoct;
output [4:0] io_intdqslogicrdatavalid;
input [24:0] io_intdqslogicreadlatency;
input [9:0] io_intdqsoe;
input [7:0] io_intodtdout;
input [3:0] io_intrasndout;
input [3:0] io_intresetndout;
input [3:0] io_intwendout;
output [4:0] io_intafirlat;
output [3:0] io_intafiwlat;
output io_intaficalfail;
output io_intaficalsuccess;
// PHY-Memory Interface
output [MEM_IF_ADDR_WIDTH-1:0] mem_a; // address
output [MEM_IF_BANKADDR_WIDTH-1:0] mem_ba; // bank
output [MEM_IF_CK_WIDTH-1:0] mem_ck; // differential address and command clock
output [MEM_IF_CK_WIDTH-1:0] mem_ck_n;
output [MEM_IF_CLK_EN_WIDTH-1:0] mem_cke; // clock enable
output [MEM_IF_CS_WIDTH-1:0] mem_cs_n; // chip select
output [MEM_IF_DM_WIDTH-1:0] mem_dm; // data mask
output [MEM_IF_CONTROL_WIDTH-1:0] mem_ras_n;
output [MEM_IF_CONTROL_WIDTH-1:0] mem_cas_n;
output [MEM_IF_CONTROL_WIDTH-1:0] mem_we_n;
inout [MEM_IF_DQ_WIDTH-1:0] mem_dq; // bidirectional data bus
inout [MEM_IF_DQS_WIDTH-1:0] mem_dqs; // bidirectional data strobe
inout [MEM_IF_DQS_WIDTH-1:0] mem_dqs_n; // differential bidirectional data strobe
output [MEM_IF_ODT_WIDTH-1:0] mem_odt;
output mem_reset_n;
// PLL Interface
input afi_clk;
input afi_half_clk;
wire pll_dqs_ena_clk;
output avl_clk;
output scc_clk;
output avl_reset_n;
output scc_reset_n;
input [SCC_DATA_WIDTH-1:0] scc_data;
input [MEM_IF_READ_DQS_WIDTH-1:0] scc_dqs_ena;
input [MEM_IF_READ_DQS_WIDTH-1:0] scc_dqs_io_ena;
input [MEM_IF_DQ_WIDTH-1:0] scc_dq_ena;
input [MEM_IF_DM_WIDTH-1:0] scc_dm_ena;
input [0:0] scc_upd;
output [MEM_IF_READ_DQS_WIDTH-1:0] capture_strobe_tracking;
output phy_clk;
output ctl_clk;
output phy_reset_n;
// END PORT SECTION
initial $display("Using %0s core emif simulation models", FAST_SIM_MODEL ? "Fast" : "Regular");
assign avl_clk = pll_avl_clk;
assign scc_clk = pll_config_clk;
assign pll_dqs_ena_clk = pll_write_clk;
hps_sdram_p0_acv_hard_memphy #(
.DEVICE_FAMILY(DEVICE_FAMILY),
.IS_HHP_HPS(IS_HHP_HPS),
.OCT_SERIES_TERM_CONTROL_WIDTH(OCT_TERM_CONTROL_WIDTH),
.OCT_PARALLEL_TERM_CONTROL_WIDTH(OCT_TERM_CONTROL_WIDTH),
.MEM_ADDRESS_WIDTH(MEM_IF_ADDR_WIDTH),
.MEM_BANK_WIDTH(MEM_IF_BANKADDR_WIDTH),
.MEM_CLK_EN_WIDTH(MEM_IF_CLK_EN_WIDTH),
.MEM_CK_WIDTH(MEM_IF_CK_WIDTH),
.MEM_ODT_WIDTH(MEM_IF_ODT_WIDTH),
.MEM_DQS_WIDTH(MEM_IF_DQS_WIDTH),
.MEM_IF_CS_WIDTH(MEM_IF_CS_WIDTH),
.MEM_DM_WIDTH(MEM_IF_DM_WIDTH),
.MEM_CONTROL_WIDTH(MEM_IF_CONTROL_WIDTH),
.MEM_DQ_WIDTH(MEM_IF_DQ_WIDTH),
.MEM_READ_DQS_WIDTH(MEM_IF_READ_DQS_WIDTH),
.MEM_WRITE_DQS_WIDTH(MEM_IF_WRITE_DQS_WIDTH),
.DLL_DELAY_CTRL_WIDTH(DLL_DELAY_CTRL_WIDTH),
.MR1_ODS(MR1_ODS),
.MR1_RTT(MR1_RTT),
.MR2_RTT_WR(MR2_RTT_WR),
.CALIB_REG_WIDTH(CALIB_REG_WIDTH),
.TB_PROTOCOL(TB_PROTOCOL),
.TB_MEM_CLK_FREQ(TB_MEM_CLK_FREQ),
.TB_RATE(TB_RATE),
.TB_MEM_DQ_WIDTH(TB_MEM_DQ_WIDTH),
.TB_MEM_DQS_WIDTH(TB_MEM_DQS_WIDTH),
.TB_PLL_DLL_MASTER(TB_PLL_DLL_MASTER),
.FAST_SIM_MODEL(FAST_SIM_MODEL),
.FAST_SIM_CALIBRATION(FAST_SIM_CALIBRATION),
.AC_ROM_INIT_FILE_NAME(AC_ROM_INIT_FILE_NAME),
.INST_ROM_INIT_FILE_NAME(INST_ROM_INIT_FILE_NAME)
) umemphy (
.global_reset_n(global_reset_n),
.soft_reset_n(soft_reset_n & ~csr_soft_reset_req),
.ctl_reset_n(ctl_reset_n),
.ctl_reset_export_n(afi_reset_export_n),
.afi_reset_n(afi_reset_n),
.pll_locked(pll_locked),
.oct_ctl_rt_value(parallelterminationcontrol),
.oct_ctl_rs_value(seriesterminationcontrol),
.afi_addr(afi_addr),
.afi_ba(afi_ba),
.afi_cke(afi_cke),
.afi_cs_n(afi_cs_n),
.afi_ras_n(afi_ras_n),
.afi_we_n(afi_we_n),
.afi_cas_n(afi_cas_n),
.afi_rst_n(afi_rst_n),
.afi_odt(afi_odt),
.afi_mem_clk_disable(afi_mem_clk_disable),
.afi_dqs_burst(afi_dqs_burst),
.afi_wdata(afi_wdata),
.afi_wdata_valid(afi_wdata_valid),
.afi_dm(afi_dm),
.afi_rdata(afi_rdata),
.afi_rdata_en(afi_rdata_en),
.afi_rdata_en_full(afi_rdata_en_full),
.afi_rdata_valid(afi_rdata_valid),
.afi_wlat(afi_wlat),
.afi_rlat(afi_rlat),
.afi_cal_success(afi_cal_success),
.afi_cal_fail(afi_cal_fail),
.avl_read(avl_read),
.avl_write(avl_write),
.avl_address(avl_address),
.avl_writedata(avl_writedata),
.avl_waitrequest(avl_waitrequest),
.avl_readdata(avl_readdata),
.cfg_addlat(cfg_addlat),
.cfg_bankaddrwidth(cfg_bankaddrwidth),
.cfg_caswrlat(cfg_caswrlat),
.cfg_coladdrwidth(cfg_coladdrwidth),
.cfg_csaddrwidth(cfg_csaddrwidth),
.cfg_devicewidth(cfg_devicewidth),
.cfg_dramconfig(cfg_dramconfig),
.cfg_interfacewidth(cfg_interfacewidth),
.cfg_rowaddrwidth(cfg_rowaddrwidth),
.cfg_tcl(cfg_tcl),
.cfg_tmrd(cfg_tmrd),
.cfg_trefi(cfg_trefi),
.cfg_trfc(cfg_trfc),
.cfg_twr(cfg_twr),
.io_intaddrdout(io_intaddrdout),
.io_intbadout(io_intbadout),
.io_intcasndout(io_intcasndout),
.io_intckdout(io_intckdout),
.io_intckedout(io_intckedout),
.io_intckndout(io_intckndout),
.io_intcsndout(io_intcsndout),
.io_intdmdout(io_intdmdout),
.io_intdqdin(io_intdqdin),
.io_intdqdout(io_intdqdout),
.io_intdqoe(io_intdqoe),
.io_intdqsbdout(io_intdqsbdout),
.io_intdqsboe(io_intdqsboe),
.io_intdqsdout(io_intdqsdout),
.io_intdqslogicdqsena(io_intdqslogicdqsena),
.io_intdqslogicfiforeset(io_intdqslogicfiforeset),
.io_intdqslogicincrdataen(io_intdqslogicincrdataen),
.io_intdqslogicincwrptr(io_intdqslogicincwrptr),
.io_intdqslogicoct(io_intdqslogicoct),
.io_intdqslogicrdatavalid(io_intdqslogicrdatavalid),
.io_intdqslogicreadlatency(io_intdqslogicreadlatency),
.io_intdqsoe(io_intdqsoe),
.io_intodtdout(io_intodtdout),
.io_intrasndout(io_intrasndout),
.io_intresetndout(io_intresetndout),
.io_intwendout(io_intwendout),
.io_intafirlat(io_intafirlat),
.io_intafiwlat(io_intafiwlat),
.io_intaficalfail(io_intaficalfail),
.io_intaficalsuccess(io_intaficalsuccess),
.mem_a(mem_a),
.mem_ba(mem_ba),
.mem_ck(mem_ck),
.mem_ck_n(mem_ck_n),
.mem_cke(mem_cke),
.mem_cs_n(mem_cs_n),
.mem_dm(mem_dm),
.mem_ras_n(mem_ras_n),
.mem_cas_n(mem_cas_n),
.mem_we_n(mem_we_n),
.mem_reset_n(mem_reset_n),
.mem_dq(mem_dq),
.mem_dqs(mem_dqs),
.mem_dqs_n(mem_dqs_n),
.mem_odt(mem_odt),
.pll_afi_clk(afi_clk),
.pll_mem_clk(pll_mem_clk),
.pll_mem_phy_clk(pll_mem_phy_clk),
.pll_afi_phy_clk(afi_phy_clk),
.pll_avl_phy_clk(pll_avl_phy_clk),
.pll_write_clk(pll_write_clk),
.pll_write_clk_pre_phy_clk(pll_write_clk_pre_phy_clk),
.pll_addr_cmd_clk(pll_addr_cmd_clk),
.pll_afi_half_clk(afi_half_clk),
.pll_dqs_ena_clk(pll_dqs_ena_clk),
.seq_clk(afi_clk),
.reset_n_avl_clk(avl_reset_n),
.reset_n_scc_clk(scc_reset_n),
.scc_data(scc_data),
.scc_dqs_ena(scc_dqs_ena),
.scc_dqs_io_ena(scc_dqs_io_ena),
.scc_dq_ena(scc_dq_ena),
.scc_dm_ena(scc_dm_ena),
.scc_upd(scc_upd),
.capture_strobe_tracking(capture_strobe_tracking),
.phy_clk(phy_clk),
.ctl_clk(ctl_clk),
.phy_reset_n(phy_reset_n),
.pll_avl_clk(pll_avl_clk),
.pll_config_clk(pll_config_clk),
.dll_clk(dll_clk),
.dll_pll_locked(dll_pll_locked),
.dll_phy_delayctrl(dll_delayctrl)
);
endmodule
|
module soc_system_mm_interconnect_3_cmd_mux
(
// ----------------------
// Sinks
// ----------------------
input sink0_valid,
input [118-1 : 0] sink0_data,
input [2-1: 0] sink0_channel,
input sink0_startofpacket,
input sink0_endofpacket,
output sink0_ready,
// ----------------------
// Source
// ----------------------
output src_valid,
output [118-1 : 0] src_data,
output [2-1 : 0] src_channel,
output src_startofpacket,
output src_endofpacket,
input src_ready,
// ----------------------
// Clock & Reset
// ----------------------
input clk,
input reset
);
localparam PAYLOAD_W = 118 + 2 + 2;
localparam NUM_INPUTS = 1;
localparam SHARE_COUNTER_W = 1;
localparam PIPELINE_ARB = 1;
localparam ST_DATA_W = 118;
localparam ST_CHANNEL_W = 2;
localparam PKT_TRANS_LOCK = 72;
assign src_valid = sink0_valid;
assign src_data = sink0_data;
assign src_channel = sink0_channel;
assign src_startofpacket = sink0_startofpacket;
assign src_endofpacket = sink0_endofpacket;
assign sink0_ready = src_ready;
endmodule
|
module soc_system_mm_interconnect_1_rsp_mux
(
// ----------------------
// Sinks
// ----------------------
input sink0_valid,
input [108-1 : 0] sink0_data,
input [14-1: 0] sink0_channel,
input sink0_startofpacket,
input sink0_endofpacket,
output sink0_ready,
input sink1_valid,
input [108-1 : 0] sink1_data,
input [14-1: 0] sink1_channel,
input sink1_startofpacket,
input sink1_endofpacket,
output sink1_ready,
input sink2_valid,
input [108-1 : 0] sink2_data,
input [14-1: 0] sink2_channel,
input sink2_startofpacket,
input sink2_endofpacket,
output sink2_ready,
input sink3_valid,
input [108-1 : 0] sink3_data,
input [14-1: 0] sink3_channel,
input sink3_startofpacket,
input sink3_endofpacket,
output sink3_ready,
input sink4_valid,
input [108-1 : 0] sink4_data,
input [14-1: 0] sink4_channel,
input sink4_startofpacket,
input sink4_endofpacket,
output sink4_ready,
input sink5_valid,
input [108-1 : 0] sink5_data,
input [14-1: 0] sink5_channel,
input sink5_startofpacket,
input sink5_endofpacket,
output sink5_ready,
input sink6_valid,
input [108-1 : 0] sink6_data,
input [14-1: 0] sink6_channel,
input sink6_startofpacket,
input sink6_endofpacket,
output sink6_ready,
input sink7_valid,
input [108-1 : 0] sink7_data,
input [14-1: 0] sink7_channel,
input sink7_startofpacket,
input sink7_endofpacket,
output sink7_ready,
input sink8_valid,
input [108-1 : 0] sink8_data,
input [14-1: 0] sink8_channel,
input sink8_startofpacket,
input sink8_endofpacket,
output sink8_ready,
input sink9_valid,
input [108-1 : 0] sink9_data,
input [14-1: 0] sink9_channel,
input sink9_startofpacket,
input sink9_endofpacket,
output sink9_ready,
input sink10_valid,
input [108-1 : 0] sink10_data,
input [14-1: 0] sink10_channel,
input sink10_startofpacket,
input sink10_endofpacket,
output sink10_ready,
input sink11_valid,
input [108-1 : 0] sink11_data,
input [14-1: 0] sink11_channel,
input sink11_startofpacket,
input sink11_endofpacket,
output sink11_ready,
input sink12_valid,
input [108-1 : 0] sink12_data,
input [14-1: 0] sink12_channel,
input sink12_startofpacket,
input sink12_endofpacket,
output sink12_ready,
input sink13_valid,
input [108-1 : 0] sink13_data,
input [14-1: 0] sink13_channel,
input sink13_startofpacket,
input sink13_endofpacket,
output sink13_ready,
// ----------------------
// Source
// ----------------------
output src_valid,
output [108-1 : 0] src_data,
output [14-1 : 0] src_channel,
output src_startofpacket,
output src_endofpacket,
input src_ready,
// ----------------------
// Clock & Reset
// ----------------------
input clk,
input reset
);
localparam PAYLOAD_W = 108 + 14 + 2;
localparam NUM_INPUTS = 14;
localparam SHARE_COUNTER_W = 1;
localparam PIPELINE_ARB = 0;
localparam ST_DATA_W = 108;
localparam ST_CHANNEL_W = 14;
localparam PKT_TRANS_LOCK = 72;
// ------------------------------------------
// Signals
// ------------------------------------------
wire [NUM_INPUTS - 1 : 0] request;
wire [NUM_INPUTS - 1 : 0] valid;
wire [NUM_INPUTS - 1 : 0] grant;
wire [NUM_INPUTS - 1 : 0] next_grant;
reg [NUM_INPUTS - 1 : 0] saved_grant;
reg [PAYLOAD_W - 1 : 0] src_payload;
wire last_cycle;
reg packet_in_progress;
reg update_grant;
wire [PAYLOAD_W - 1 : 0] sink0_payload;
wire [PAYLOAD_W - 1 : 0] sink1_payload;
wire [PAYLOAD_W - 1 : 0] sink2_payload;
wire [PAYLOAD_W - 1 : 0] sink3_payload;
wire [PAYLOAD_W - 1 : 0] sink4_payload;
wire [PAYLOAD_W - 1 : 0] sink5_payload;
wire [PAYLOAD_W - 1 : 0] sink6_payload;
wire [PAYLOAD_W - 1 : 0] sink7_payload;
wire [PAYLOAD_W - 1 : 0] sink8_payload;
wire [PAYLOAD_W - 1 : 0] sink9_payload;
wire [PAYLOAD_W - 1 : 0] sink10_payload;
wire [PAYLOAD_W - 1 : 0] sink11_payload;
wire [PAYLOAD_W - 1 : 0] sink12_payload;
wire [PAYLOAD_W - 1 : 0] sink13_payload;
assign valid[0] = sink0_valid;
assign valid[1] = sink1_valid;
assign valid[2] = sink2_valid;
assign valid[3] = sink3_valid;
assign valid[4] = sink4_valid;
assign valid[5] = sink5_valid;
assign valid[6] = sink6_valid;
assign valid[7] = sink7_valid;
assign valid[8] = sink8_valid;
assign valid[9] = sink9_valid;
assign valid[10] = sink10_valid;
assign valid[11] = sink11_valid;
assign valid[12] = sink12_valid;
assign valid[13] = sink13_valid;
// ------------------------------------------
// ------------------------------------------
// Grant Logic & Updates
// ------------------------------------------
// ------------------------------------------
reg [NUM_INPUTS - 1 : 0] lock;
always @* begin
lock[0] = sink0_data[72];
lock[1] = sink1_data[72];
lock[2] = sink2_data[72];
lock[3] = sink3_data[72];
lock[4] = sink4_data[72];
lock[5] = sink5_data[72];
lock[6] = sink6_data[72];
lock[7] = sink7_data[72];
lock[8] = sink8_data[72];
lock[9] = sink9_data[72];
lock[10] = sink10_data[72];
lock[11] = sink11_data[72];
lock[12] = sink12_data[72];
lock[13] = sink13_data[72];
end
assign last_cycle = src_valid & src_ready & src_endofpacket & ~(|(lock & grant));
// ------------------------------------------
// We're working on a packet at any time valid is high, except
// when this is the endofpacket.
// ------------------------------------------
always @(posedge clk or posedge reset) begin
if (reset) begin
packet_in_progress <= 1'b0;
end
else begin
if (last_cycle)
packet_in_progress <= 1'b0;
else if (src_valid)
packet_in_progress <= 1'b1;
end
end
// ------------------------------------------
// Shares
//
// Special case: all-equal shares _should_ be optimized into assigning a
// constant to next_grant_share.
// Special case: all-1's shares _should_ result in the share counter
// being optimized away.
// ------------------------------------------
// Input | arb shares | counter load value
// 0 | 1 | 0
// 1 | 1 | 0
// 2 | 1 | 0
// 3 | 1 | 0
// 4 | 1 | 0
// 5 | 1 | 0
// 6 | 1 | 0
// 7 | 1 | 0
// 8 | 1 | 0
// 9 | 1 | 0
// 10 | 1 | 0
// 11 | 1 | 0
// 12 | 1 | 0
// 13 | 1 | 0
wire [SHARE_COUNTER_W - 1 : 0] share_0 = 1'd0;
wire [SHARE_COUNTER_W - 1 : 0] share_1 = 1'd0;
wire [SHARE_COUNTER_W - 1 : 0] share_2 = 1'd0;
wire [SHARE_COUNTER_W - 1 : 0] share_3 = 1'd0;
wire [SHARE_COUNTER_W - 1 : 0] share_4 = 1'd0;
wire [SHARE_COUNTER_W - 1 : 0] share_5 = 1'd0;
wire [SHARE_COUNTER_W - 1 : 0] share_6 = 1'd0;
wire [SHARE_COUNTER_W - 1 : 0] share_7 = 1'd0;
wire [SHARE_COUNTER_W - 1 : 0] share_8 = 1'd0;
wire [SHARE_COUNTER_W - 1 : 0] share_9 = 1'd0;
wire [SHARE_COUNTER_W - 1 : 0] share_10 = 1'd0;
wire [SHARE_COUNTER_W - 1 : 0] share_11 = 1'd0;
wire [SHARE_COUNTER_W - 1 : 0] share_12 = 1'd0;
wire [SHARE_COUNTER_W - 1 : 0] share_13 = 1'd0;
// ------------------------------------------
// Choose the share value corresponding to the grant.
// ------------------------------------------
reg [SHARE_COUNTER_W - 1 : 0] next_grant_share;
always @* begin
next_grant_share =
share_0 & { SHARE_COUNTER_W {next_grant[0]} } |
share_1 & { SHARE_COUNTER_W {next_grant[1]} } |
share_2 & { SHARE_COUNTER_W {next_grant[2]} } |
share_3 & { SHARE_COUNTER_W {next_grant[3]} } |
share_4 & { SHARE_COUNTER_W {next_grant[4]} } |
share_5 & { SHARE_COUNTER_W {next_grant[5]} } |
share_6 & { SHARE_COUNTER_W {next_grant[6]} } |
share_7 & { SHARE_COUNTER_W {next_grant[7]} } |
share_8 & { SHARE_COUNTER_W {next_grant[8]} } |
share_9 & { SHARE_COUNTER_W {next_grant[9]} } |
share_10 & { SHARE_COUNTER_W {next_grant[10]} } |
share_11 & { SHARE_COUNTER_W {next_grant[11]} } |
share_12 & { SHARE_COUNTER_W {next_grant[12]} } |
share_13 & { SHARE_COUNTER_W {next_grant[13]} };
end
// ------------------------------------------
// Flag to indicate first packet of an arb sequence.
// ------------------------------------------
wire grant_changed = ~packet_in_progress && ~(|(saved_grant & valid));
reg first_packet_r;
wire first_packet = grant_changed | first_packet_r;
always @(posedge clk or posedge reset) begin
if (reset) begin
first_packet_r <= 1'b0;
end
else begin
if (update_grant)
first_packet_r <= 1'b1;
else if (last_cycle)
first_packet_r <= 1'b0;
else if (grant_changed)
first_packet_r <= 1'b1;
end
end
// ------------------------------------------
// Compute the next share-count value.
// ------------------------------------------
reg [SHARE_COUNTER_W - 1 : 0] p1_share_count;
reg [SHARE_COUNTER_W - 1 : 0] share_count;
reg share_count_zero_flag;
always @* begin
if (first_packet) begin
p1_share_count = next_grant_share;
end
else begin
// Update the counter, but don't decrement below 0.
p1_share_count = share_count_zero_flag ? '0 : share_count - 1'b1;
end
end
// ------------------------------------------
// Update the share counter and share-counter=zero flag.
// ------------------------------------------
always @(posedge clk or posedge reset) begin
if (reset) begin
share_count <= '0;
share_count_zero_flag <= 1'b1;
end
else begin
if (last_cycle) begin
share_count <= p1_share_count;
share_count_zero_flag <= (p1_share_count == '0);
end
end
end
// ------------------------------------------
// For each input, maintain a final_packet signal which goes active for the
// last packet of a full-share packet sequence. Example: if I have 4
// shares and I'm continuously requesting, final_packet is active in the
// 4th packet.
// ------------------------------------------
wire final_packet_0 = 1'b1;
wire final_packet_1 = 1'b1;
wire final_packet_2 = 1'b1;
wire final_packet_3 = 1'b1;
wire final_packet_4 = 1'b1;
wire final_packet_5 = 1'b1;
wire final_packet_6 = 1'b1;
wire final_packet_7 = 1'b1;
wire final_packet_8 = 1'b1;
wire final_packet_9 = 1'b1;
wire final_packet_10 = 1'b1;
wire final_packet_11 = 1'b1;
wire final_packet_12 = 1'b1;
wire final_packet_13 = 1'b1;
// ------------------------------------------
// Concatenate all final_packet signals (wire or reg) into a handy vector.
// ------------------------------------------
wire [NUM_INPUTS - 1 : 0] final_packet = {
final_packet_13,
final_packet_12,
final_packet_11,
final_packet_10,
final_packet_9,
final_packet_8,
final_packet_7,
final_packet_6,
final_packet_5,
final_packet_4,
final_packet_3,
final_packet_2,
final_packet_1,
final_packet_0
};
// ------------------------------------------
// ------------------------------------------
wire p1_done = |(final_packet & grant);
// ------------------------------------------
// Flag for the first cycle of packets within an
// arb sequence
// ------------------------------------------
reg first_cycle;
always @(posedge clk, posedge reset) begin
if (reset)
first_cycle <= 0;
else
first_cycle <= last_cycle && ~p1_done;
end
always @* begin
update_grant = 0;
// ------------------------------------------
// No arbitration pipeline, update grant whenever
// the current arb winner has consumed all shares,
// or all requests are low
// ------------------------------------------
update_grant = (last_cycle && p1_done) || (first_cycle && ~(|valid));
update_grant = last_cycle;
end
wire save_grant;
assign save_grant = 1;
assign grant = next_grant;
always @(posedge clk, posedge reset) begin
if (reset)
saved_grant <= '0;
else if (save_grant)
saved_grant <= next_grant;
end
// ------------------------------------------
// ------------------------------------------
// Arbitrator
// ------------------------------------------
// ------------------------------------------
// ------------------------------------------
// Create a request vector that stays high during
// the packet for unpipelined arbitration.
//
// The pipelined arbitration scheme does not require
// request to be held high during the packet.
// ------------------------------------------
assign request = valid;
wire [NUM_INPUTS - 1 : 0] next_grant_from_arb;
altera_merlin_arbitrator
#(
.NUM_REQUESTERS(NUM_INPUTS),
.SCHEME ("no-arb"),
.PIPELINE (0)
) arb (
.clk (clk),
.reset (reset),
.request (request),
.grant (next_grant_from_arb),
.save_top_priority (src_valid),
.increment_top_priority (update_grant)
);
assign next_grant = next_grant_from_arb;
// ------------------------------------------
// ------------------------------------------
// Mux
//
// Implemented as a sum of products.
// ------------------------------------------
// ------------------------------------------
assign sink0_ready = src_ready && grant[0];
assign sink1_ready = src_ready && grant[1];
assign sink2_ready = src_ready && grant[2];
assign sink3_ready = src_ready && grant[3];
assign sink4_ready = src_ready && grant[4];
assign sink5_ready = src_ready && grant[5];
assign sink6_ready = src_ready && grant[6];
assign sink7_ready = src_ready && grant[7];
assign sink8_ready = src_ready && grant[8];
assign sink9_ready = src_ready && grant[9];
assign sink10_ready = src_ready && grant[10];
assign sink11_ready = src_ready && grant[11];
assign sink12_ready = src_ready && grant[12];
assign sink13_ready = src_ready && grant[13];
assign src_valid = |(grant & valid);
always @* begin
src_payload =
sink0_payload & {PAYLOAD_W {grant[0]} } |
sink1_payload & {PAYLOAD_W {grant[1]} } |
sink2_payload & {PAYLOAD_W {grant[2]} } |
sink3_payload & {PAYLOAD_W {grant[3]} } |
sink4_payload & {PAYLOAD_W {grant[4]} } |
sink5_payload & {PAYLOAD_W {grant[5]} } |
sink6_payload & {PAYLOAD_W {grant[6]} } |
sink7_payload & {PAYLOAD_W {grant[7]} } |
sink8_payload & {PAYLOAD_W {grant[8]} } |
sink9_payload & {PAYLOAD_W {grant[9]} } |
sink10_payload & {PAYLOAD_W {grant[10]} } |
sink11_payload & {PAYLOAD_W {grant[11]} } |
sink12_payload & {PAYLOAD_W {grant[12]} } |
sink13_payload & {PAYLOAD_W {grant[13]} };
end
// ------------------------------------------
// Mux Payload Mapping
// ------------------------------------------
assign sink0_payload = {sink0_channel,sink0_data,
sink0_startofpacket,sink0_endofpacket};
assign sink1_payload = {sink1_channel,sink1_data,
sink1_startofpacket,sink1_endofpacket};
assign sink2_payload = {sink2_channel,sink2_data,
sink2_startofpacket,sink2_endofpacket};
assign sink3_payload = {sink3_channel,sink3_data,
sink3_startofpacket,sink3_endofpacket};
assign sink4_payload = {sink4_channel,sink4_data,
sink4_startofpacket,sink4_endofpacket};
assign sink5_payload = {sink5_channel,sink5_data,
sink5_startofpacket,sink5_endofpacket};
assign sink6_payload = {sink6_channel,sink6_data,
sink6_startofpacket,sink6_endofpacket};
assign sink7_payload = {sink7_channel,sink7_data,
sink7_startofpacket,sink7_endofpacket};
assign sink8_payload = {sink8_channel,sink8_data,
sink8_startofpacket,sink8_endofpacket};
assign sink9_payload = {sink9_channel,sink9_data,
sink9_startofpacket,sink9_endofpacket};
assign sink10_payload = {sink10_channel,sink10_data,
sink10_startofpacket,sink10_endofpacket};
assign sink11_payload = {sink11_channel,sink11_data,
sink11_startofpacket,sink11_endofpacket};
assign sink12_payload = {sink12_channel,sink12_data,
sink12_startofpacket,sink12_endofpacket};
assign sink13_payload = {sink13_channel,sink13_data,
sink13_startofpacket,sink13_endofpacket};
assign {src_channel,src_data,src_startofpacket,src_endofpacket} = src_payload;
endmodule
|
module soc_system_mm_interconnect_0_rsp_mux
(
// ----------------------
// Sinks
// ----------------------
input sink0_valid,
input [112-1 : 0] sink0_data,
input [2-1: 0] sink0_channel,
input sink0_startofpacket,
input sink0_endofpacket,
output sink0_ready,
// ----------------------
// Source
// ----------------------
output src_valid,
output [112-1 : 0] src_data,
output [2-1 : 0] src_channel,
output src_startofpacket,
output src_endofpacket,
input src_ready,
// ----------------------
// Clock & Reset
// ----------------------
input clk,
input reset
);
localparam PAYLOAD_W = 112 + 2 + 2;
localparam NUM_INPUTS = 1;
localparam SHARE_COUNTER_W = 1;
localparam PIPELINE_ARB = 0;
localparam ST_DATA_W = 112;
localparam ST_CHANNEL_W = 2;
localparam PKT_TRANS_LOCK = 61;
assign src_valid = sink0_valid;
assign src_data = sink0_data;
assign src_channel = sink0_channel;
assign src_startofpacket = sink0_startofpacket;
assign src_endofpacket = sink0_endofpacket;
assign sink0_ready = src_ready;
endmodule
|
module soc_system_mm_interconnect_0_router_003_default_decode
#(
parameter DEFAULT_CHANNEL = 2,
DEFAULT_WR_CHANNEL = -1,
DEFAULT_RD_CHANNEL = -1,
DEFAULT_DESTID = 4
)
(output [104 - 102 : 0] default_destination_id,
output [7-1 : 0] default_wr_channel,
output [7-1 : 0] default_rd_channel,
output [7-1 : 0] default_src_channel
);
assign default_destination_id =
DEFAULT_DESTID[104 - 102 : 0];
generate
if (DEFAULT_CHANNEL == -1) begin : no_default_channel_assignment
assign default_src_channel = '0;
end
else begin : default_channel_assignment
assign default_src_channel = 7'b1 << DEFAULT_CHANNEL;
end
endgenerate
generate
if (DEFAULT_RD_CHANNEL == -1) begin : no_default_rw_channel_assignment
assign default_wr_channel = '0;
assign default_rd_channel = '0;
end
else begin : default_rw_channel_assignment
assign default_wr_channel = 7'b1 << DEFAULT_WR_CHANNEL;
assign default_rd_channel = 7'b1 << DEFAULT_RD_CHANNEL;
end
endgenerate
endmodule
|
module soc_system_mm_interconnect_0_router_003
(
// -------------------
// Clock & Reset
// -------------------
input clk,
input reset,
// -------------------
// Command Sink (Input)
// -------------------
input sink_valid,
input [129-1 : 0] sink_data,
input sink_startofpacket,
input sink_endofpacket,
output sink_ready,
// -------------------
// Command Source (Output)
// -------------------
output src_valid,
output reg [129-1 : 0] src_data,
output reg [7-1 : 0] src_channel,
output src_startofpacket,
output src_endofpacket,
input src_ready
);
// -------------------------------------------------------
// Local parameters and variables
// -------------------------------------------------------
localparam PKT_ADDR_H = 67;
localparam PKT_ADDR_L = 36;
localparam PKT_DEST_ID_H = 104;
localparam PKT_DEST_ID_L = 102;
localparam PKT_PROTECTION_H = 119;
localparam PKT_PROTECTION_L = 117;
localparam ST_DATA_W = 129;
localparam ST_CHANNEL_W = 7;
localparam DECODER_TYPE = 0;
localparam PKT_TRANS_WRITE = 70;
localparam PKT_TRANS_READ = 71;
localparam PKT_ADDR_W = PKT_ADDR_H-PKT_ADDR_L + 1;
localparam PKT_DEST_ID_W = PKT_DEST_ID_H-PKT_DEST_ID_L + 1;
// -------------------------------------------------------
// Figure out the number of bits to mask off for each slave span
// during address decoding
// -------------------------------------------------------
localparam PAD0 = log2ceil(64'h10008 - 64'h10000);
localparam PAD1 = log2ceil(64'h10050 - 64'h10040);
localparam PAD2 = log2ceil(64'h10090 - 64'h10080);
localparam PAD3 = log2ceil(64'h100d0 - 64'h100c0);
localparam PAD4 = log2ceil(64'h20008 - 64'h20000);
// -------------------------------------------------------
// Work out which address bits are significant based on the
// address range of the slaves. If the required width is too
// large or too small, we use the address field width instead.
// -------------------------------------------------------
localparam ADDR_RANGE = 64'h20008;
localparam RANGE_ADDR_WIDTH = log2ceil(ADDR_RANGE);
localparam OPTIMIZED_ADDR_H = (RANGE_ADDR_WIDTH > PKT_ADDR_W) ||
(RANGE_ADDR_WIDTH == 0) ?
PKT_ADDR_H :
PKT_ADDR_L + RANGE_ADDR_WIDTH - 1;
localparam RG = RANGE_ADDR_WIDTH-1;
localparam REAL_ADDRESS_RANGE = OPTIMIZED_ADDR_H - PKT_ADDR_L;
reg [PKT_ADDR_W-1 : 0] address;
always @* begin
address = {PKT_ADDR_W{1'b0}};
address [REAL_ADDRESS_RANGE:0] = sink_data[OPTIMIZED_ADDR_H : PKT_ADDR_L];
end
// -------------------------------------------------------
// Pass almost everything through, untouched
// -------------------------------------------------------
assign sink_ready = src_ready;
assign src_valid = sink_valid;
assign src_startofpacket = sink_startofpacket;
assign src_endofpacket = sink_endofpacket;
wire [PKT_DEST_ID_W-1:0] default_destid;
wire [7-1 : 0] default_src_channel;
// -------------------------------------------------------
// Write and read transaction signals
// -------------------------------------------------------
wire read_transaction;
assign read_transaction = sink_data[PKT_TRANS_READ];
soc_system_mm_interconnect_0_router_003_default_decode the_default_decode(
.default_destination_id (default_destid),
.default_wr_channel (),
.default_rd_channel (),
.default_src_channel (default_src_channel)
);
always @* begin
src_data = sink_data;
src_channel = default_src_channel;
src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = default_destid;
// --------------------------------------------------
// Address Decoder
// Sets the channel and destination ID based on the address
// --------------------------------------------------
// ( 0x10000 .. 0x10008 )
if ( {address[RG:PAD0],{PAD0{1'b0}}} == 18'h10000 && read_transaction ) begin
src_channel = 7'b00010;
src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 6;
end
// ( 0x10040 .. 0x10050 )
if ( {address[RG:PAD1],{PAD1{1'b0}}} == 18'h10040 ) begin
src_channel = 7'b00100;
src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 4;
end
// ( 0x10080 .. 0x10090 )
if ( {address[RG:PAD2],{PAD2{1'b0}}} == 18'h10080 ) begin
src_channel = 7'b01000;
src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 1;
end
// ( 0x100c0 .. 0x100d0 )
if ( {address[RG:PAD3],{PAD3{1'b0}}} == 18'h100c0 ) begin
src_channel = 7'b10000;
src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 0;
end
// ( 0x20000 .. 0x20008 )
if ( {address[RG:PAD4],{PAD4{1'b0}}} == 18'h20000 ) begin
src_channel = 7'b00001;
src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 3;
end
end
// --------------------------------------------------
// Ceil(log2()) function
// --------------------------------------------------
function integer log2ceil;
input reg[65:0] val;
reg [65:0] i;
begin
i = 1;
log2ceil = 0;
while (i < val) begin
log2ceil = log2ceil + 1;
i = i << 1;
end
end
endfunction
endmodule
|
module soc_system_hps_0_hps_io_border(
// memory
output wire [15 - 1 : 0 ] mem_a
,output wire [3 - 1 : 0 ] mem_ba
,output wire [1 - 1 : 0 ] mem_ck
,output wire [1 - 1 : 0 ] mem_ck_n
,output wire [1 - 1 : 0 ] mem_cke
,output wire [1 - 1 : 0 ] mem_cs_n
,output wire [1 - 1 : 0 ] mem_ras_n
,output wire [1 - 1 : 0 ] mem_cas_n
,output wire [1 - 1 : 0 ] mem_we_n
,output wire [1 - 1 : 0 ] mem_reset_n
,inout wire [32 - 1 : 0 ] mem_dq
,inout wire [4 - 1 : 0 ] mem_dqs
,inout wire [4 - 1 : 0 ] mem_dqs_n
,output wire [1 - 1 : 0 ] mem_odt
,output wire [4 - 1 : 0 ] mem_dm
,input wire [1 - 1 : 0 ] oct_rzqin
// hps_io
,output wire [1 - 1 : 0 ] hps_io_emac1_inst_TX_CLK
,output wire [1 - 1 : 0 ] hps_io_emac1_inst_TXD0
,output wire [1 - 1 : 0 ] hps_io_emac1_inst_TXD1
,output wire [1 - 1 : 0 ] hps_io_emac1_inst_TXD2
,output wire [1 - 1 : 0 ] hps_io_emac1_inst_TXD3
,input wire [1 - 1 : 0 ] hps_io_emac1_inst_RXD0
,inout wire [1 - 1 : 0 ] hps_io_emac1_inst_MDIO
,output wire [1 - 1 : 0 ] hps_io_emac1_inst_MDC
,input wire [1 - 1 : 0 ] hps_io_emac1_inst_RX_CTL
,output wire [1 - 1 : 0 ] hps_io_emac1_inst_TX_CTL
,input wire [1 - 1 : 0 ] hps_io_emac1_inst_RX_CLK
,input wire [1 - 1 : 0 ] hps_io_emac1_inst_RXD1
,input wire [1 - 1 : 0 ] hps_io_emac1_inst_RXD2
,input wire [1 - 1 : 0 ] hps_io_emac1_inst_RXD3
,inout wire [1 - 1 : 0 ] hps_io_sdio_inst_CMD
,inout wire [1 - 1 : 0 ] hps_io_sdio_inst_D0
,inout wire [1 - 1 : 0 ] hps_io_sdio_inst_D1
,output wire [1 - 1 : 0 ] hps_io_sdio_inst_CLK
,inout wire [1 - 1 : 0 ] hps_io_sdio_inst_D2
,inout wire [1 - 1 : 0 ] hps_io_sdio_inst_D3
,inout wire [1 - 1 : 0 ] hps_io_usb1_inst_D0
,inout wire [1 - 1 : 0 ] hps_io_usb1_inst_D1
,inout wire [1 - 1 : 0 ] hps_io_usb1_inst_D2
,inout wire [1 - 1 : 0 ] hps_io_usb1_inst_D3
,inout wire [1 - 1 : 0 ] hps_io_usb1_inst_D4
,inout wire [1 - 1 : 0 ] hps_io_usb1_inst_D5
,inout wire [1 - 1 : 0 ] hps_io_usb1_inst_D6
,inout wire [1 - 1 : 0 ] hps_io_usb1_inst_D7
,input wire [1 - 1 : 0 ] hps_io_usb1_inst_CLK
,output wire [1 - 1 : 0 ] hps_io_usb1_inst_STP
,input wire [1 - 1 : 0 ] hps_io_usb1_inst_DIR
,input wire [1 - 1 : 0 ] hps_io_usb1_inst_NXT
,output wire [1 - 1 : 0 ] hps_io_spim1_inst_CLK
,output wire [1 - 1 : 0 ] hps_io_spim1_inst_MOSI
,input wire [1 - 1 : 0 ] hps_io_spim1_inst_MISO
,output wire [1 - 1 : 0 ] hps_io_spim1_inst_SS0
,input wire [1 - 1 : 0 ] hps_io_uart0_inst_RX
,output wire [1 - 1 : 0 ] hps_io_uart0_inst_TX
,inout wire [1 - 1 : 0 ] hps_io_i2c0_inst_SDA
,inout wire [1 - 1 : 0 ] hps_io_i2c0_inst_SCL
,inout wire [1 - 1 : 0 ] hps_io_i2c1_inst_SDA
,inout wire [1 - 1 : 0 ] hps_io_i2c1_inst_SCL
,inout wire [1 - 1 : 0 ] hps_io_gpio_inst_GPIO09
,inout wire [1 - 1 : 0 ] hps_io_gpio_inst_GPIO35
,inout wire [1 - 1 : 0 ] hps_io_gpio_inst_GPIO40
,inout wire [1 - 1 : 0 ] hps_io_gpio_inst_GPIO53
,inout wire [1 - 1 : 0 ] hps_io_gpio_inst_GPIO54
,inout wire [1 - 1 : 0 ] hps_io_gpio_inst_GPIO61
);
assign hps_io_emac1_inst_MDIO = intermediate[1] ? intermediate[0] : 'z;
assign hps_io_sdio_inst_CMD = intermediate[3] ? intermediate[2] : 'z;
assign hps_io_sdio_inst_D0 = intermediate[5] ? intermediate[4] : 'z;
assign hps_io_sdio_inst_D1 = intermediate[7] ? intermediate[6] : 'z;
assign hps_io_sdio_inst_D2 = intermediate[9] ? intermediate[8] : 'z;
assign hps_io_sdio_inst_D3 = intermediate[11] ? intermediate[10] : 'z;
assign hps_io_usb1_inst_D0 = intermediate[13] ? intermediate[12] : 'z;
assign hps_io_usb1_inst_D1 = intermediate[15] ? intermediate[14] : 'z;
assign hps_io_usb1_inst_D2 = intermediate[17] ? intermediate[16] : 'z;
assign hps_io_usb1_inst_D3 = intermediate[19] ? intermediate[18] : 'z;
assign hps_io_usb1_inst_D4 = intermediate[21] ? intermediate[20] : 'z;
assign hps_io_usb1_inst_D5 = intermediate[23] ? intermediate[22] : 'z;
assign hps_io_usb1_inst_D6 = intermediate[25] ? intermediate[24] : 'z;
assign hps_io_usb1_inst_D7 = intermediate[27] ? intermediate[26] : 'z;
assign hps_io_spim1_inst_MOSI = intermediate[29] ? intermediate[28] : 'z;
assign hps_io_i2c0_inst_SDA = intermediate[30] ? '0 : 'z;
assign hps_io_i2c0_inst_SCL = intermediate[31] ? '0 : 'z;
assign hps_io_i2c1_inst_SDA = intermediate[32] ? '0 : 'z;
assign hps_io_i2c1_inst_SCL = intermediate[33] ? '0 : 'z;
assign hps_io_gpio_inst_GPIO09 = intermediate[35] ? intermediate[34] : 'z;
assign hps_io_gpio_inst_GPIO35 = intermediate[37] ? intermediate[36] : 'z;
assign hps_io_gpio_inst_GPIO40 = intermediate[39] ? intermediate[38] : 'z;
assign hps_io_gpio_inst_GPIO53 = intermediate[41] ? intermediate[40] : 'z;
assign hps_io_gpio_inst_GPIO54 = intermediate[43] ? intermediate[42] : 'z;
assign hps_io_gpio_inst_GPIO61 = intermediate[45] ? intermediate[44] : 'z;
wire [46 - 1 : 0] intermediate;
wire [102 - 1 : 0] floating;
cyclonev_hps_peripheral_emac emac1_inst(
.EMAC_GMII_MDO_I({
hps_io_emac1_inst_MDIO[0:0] // 0:0
})
,.EMAC_GMII_MDO_OE({
intermediate[1:1] // 0:0
})
,.EMAC_PHY_TXD({
hps_io_emac1_inst_TXD3[0:0] // 3:3
,hps_io_emac1_inst_TXD2[0:0] // 2:2
,hps_io_emac1_inst_TXD1[0:0] // 1:1
,hps_io_emac1_inst_TXD0[0:0] // 0:0
})
,.EMAC_CLK_TX({
hps_io_emac1_inst_TX_CLK[0:0] // 0:0
})
,.EMAC_PHY_RXDV({
hps_io_emac1_inst_RX_CTL[0:0] // 0:0
})
,.EMAC_PHY_RXD({
hps_io_emac1_inst_RXD3[0:0] // 3:3
,hps_io_emac1_inst_RXD2[0:0] // 2:2
,hps_io_emac1_inst_RXD1[0:0] // 1:1
,hps_io_emac1_inst_RXD0[0:0] // 0:0
})
,.EMAC_GMII_MDO_O({
intermediate[0:0] // 0:0
})
,.EMAC_GMII_MDC({
hps_io_emac1_inst_MDC[0:0] // 0:0
})
,.EMAC_PHY_TX_OE({
hps_io_emac1_inst_TX_CTL[0:0] // 0:0
})
,.EMAC_CLK_RX({
hps_io_emac1_inst_RX_CLK[0:0] // 0:0
})
);
cyclonev_hps_peripheral_sdmmc sdio_inst(
.SDMMC_DATA_I({
hps_io_sdio_inst_D3[0:0] // 3:3
,hps_io_sdio_inst_D2[0:0] // 2:2
,hps_io_sdio_inst_D1[0:0] // 1:1
,hps_io_sdio_inst_D0[0:0] // 0:0
})
,.SDMMC_CMD_O({
intermediate[2:2] // 0:0
})
,.SDMMC_CCLK({
hps_io_sdio_inst_CLK[0:0] // 0:0
})
,.SDMMC_DATA_O({
intermediate[10:10] // 3:3
,intermediate[8:8] // 2:2
,intermediate[6:6] // 1:1
,intermediate[4:4] // 0:0
})
,.SDMMC_CMD_OE({
intermediate[3:3] // 0:0
})
,.SDMMC_CMD_I({
hps_io_sdio_inst_CMD[0:0] // 0:0
})
,.SDMMC_DATA_OE({
intermediate[11:11] // 3:3
,intermediate[9:9] // 2:2
,intermediate[7:7] // 1:1
,intermediate[5:5] // 0:0
})
);
cyclonev_hps_peripheral_usb usb1_inst(
.USB_ULPI_STP({
hps_io_usb1_inst_STP[0:0] // 0:0
})
,.USB_ULPI_DATA_I({
hps_io_usb1_inst_D7[0:0] // 7:7
,hps_io_usb1_inst_D6[0:0] // 6:6
,hps_io_usb1_inst_D5[0:0] // 5:5
,hps_io_usb1_inst_D4[0:0] // 4:4
,hps_io_usb1_inst_D3[0:0] // 3:3
,hps_io_usb1_inst_D2[0:0] // 2:2
,hps_io_usb1_inst_D1[0:0] // 1:1
,hps_io_usb1_inst_D0[0:0] // 0:0
})
,.USB_ULPI_NXT({
hps_io_usb1_inst_NXT[0:0] // 0:0
})
,.USB_ULPI_DIR({
hps_io_usb1_inst_DIR[0:0] // 0:0
})
,.USB_ULPI_DATA_O({
intermediate[26:26] // 7:7
,intermediate[24:24] // 6:6
,intermediate[22:22] // 5:5
,intermediate[20:20] // 4:4
,intermediate[18:18] // 3:3
,intermediate[16:16] // 2:2
,intermediate[14:14] // 1:1
,intermediate[12:12] // 0:0
})
,.USB_ULPI_CLK({
hps_io_usb1_inst_CLK[0:0] // 0:0
})
,.USB_ULPI_DATA_OE({
intermediate[27:27] // 7:7
,intermediate[25:25] // 6:6
,intermediate[23:23] // 5:5
,intermediate[21:21] // 4:4
,intermediate[19:19] // 3:3
,intermediate[17:17] // 2:2
,intermediate[15:15] // 1:1
,intermediate[13:13] // 0:0
})
);
cyclonev_hps_peripheral_spi_master spim1_inst(
.SPI_MASTER_RXD({
hps_io_spim1_inst_MISO[0:0] // 0:0
})
,.SPI_MASTER_TXD({
intermediate[28:28] // 0:0
})
,.SPI_MASTER_SSI_OE_N({
intermediate[29:29] // 0:0
})
,.SPI_MASTER_SCLK({
hps_io_spim1_inst_CLK[0:0] // 0:0
})
,.SPI_MASTER_SS_0_N({
hps_io_spim1_inst_SS0[0:0] // 0:0
})
);
cyclonev_hps_peripheral_uart uart0_inst(
.UART_RXD({
hps_io_uart0_inst_RX[0:0] // 0:0
})
,.UART_TXD({
hps_io_uart0_inst_TX[0:0] // 0:0
})
);
cyclonev_hps_peripheral_i2c i2c0_inst(
.I2C_DATA({
hps_io_i2c0_inst_SDA[0:0] // 0:0
})
,.I2C_CLK({
hps_io_i2c0_inst_SCL[0:0] // 0:0
})
,.I2C_DATA_OE({
intermediate[30:30] // 0:0
})
,.I2C_CLK_OE({
intermediate[31:31] // 0:0
})
);
cyclonev_hps_peripheral_i2c i2c1_inst(
.I2C_DATA({
hps_io_i2c1_inst_SDA[0:0] // 0:0
})
,.I2C_CLK({
hps_io_i2c1_inst_SCL[0:0] // 0:0
})
,.I2C_DATA_OE({
intermediate[32:32] // 0:0
})
,.I2C_CLK_OE({
intermediate[33:33] // 0:0
})
);
cyclonev_hps_peripheral_gpio gpio_inst(
.GPIO1_PORTA_I({
hps_io_gpio_inst_GPIO54[0:0] // 25:25
,hps_io_gpio_inst_GPIO53[0:0] // 24:24
,floating[11:0] // 23:12
,hps_io_gpio_inst_GPIO40[0:0] // 11:11
,floating[15:12] // 10:7
,hps_io_gpio_inst_GPIO35[0:0] // 6:6
,floating[21:16] // 5:0
})
,.GPIO1_PORTA_OE({
intermediate[43:43] // 25:25
,intermediate[41:41] // 24:24
,floating[33:22] // 23:12
,intermediate[39:39] // 11:11
,floating[37:34] // 10:7
,intermediate[37:37] // 6:6
,floating[43:38] // 5:0
})
,.GPIO2_PORTA_O({
intermediate[44:44] // 3:3
,floating[46:44] // 2:0
})
,.GPIO0_PORTA_O({
intermediate[34:34] // 9:9
,floating[55:47] // 8:0
})
,.GPIO2_PORTA_I({
hps_io_gpio_inst_GPIO61[0:0] // 3:3
,floating[58:56] // 2:0
})
,.GPIO2_PORTA_OE({
intermediate[45:45] // 3:3
,floating[61:59] // 2:0
})
,.GPIO0_PORTA_I({
hps_io_gpio_inst_GPIO09[0:0] // 9:9
,floating[70:62] // 8:0
})
,.GPIO0_PORTA_OE({
intermediate[35:35] // 9:9
,floating[79:71] // 8:0
})
,.GPIO1_PORTA_O({
intermediate[42:42] // 25:25
,intermediate[40:40] // 24:24
,floating[91:80] // 23:12
,intermediate[38:38] // 11:11
,floating[95:92] // 10:7
,intermediate[36:36] // 6:6
,floating[101:96] // 5:0
})
);
hps_sdram hps_sdram_inst(
.mem_dq({
mem_dq[31:0] // 31:0
})
,.mem_odt({
mem_odt[0:0] // 0:0
})
,.mem_ras_n({
mem_ras_n[0:0] // 0:0
})
,.mem_dqs_n({
mem_dqs_n[3:0] // 3:0
})
,.mem_dqs({
mem_dqs[3:0] // 3:0
})
,.mem_dm({
mem_dm[3:0] // 3:0
})
,.mem_we_n({
mem_we_n[0:0] // 0:0
})
,.mem_cas_n({
mem_cas_n[0:0] // 0:0
})
,.mem_ba({
mem_ba[2:0] // 2:0
})
,.mem_a({
mem_a[14:0] // 14:0
})
,.mem_cs_n({
mem_cs_n[0:0] // 0:0
})
,.mem_ck({
mem_ck[0:0] // 0:0
})
,.mem_cke({
mem_cke[0:0] // 0:0
})
,.oct_rzqin({
oct_rzqin[0:0] // 0:0
})
,.mem_reset_n({
mem_reset_n[0:0] // 0:0
})
,.mem_ck_n({
mem_ck_n[0:0] // 0:0
})
);
endmodule
|
module soc_system_irq_mapper_002
(
// -------------------
// Clock & Reset
// -------------------
input clk,
input reset,
// -------------------
// IRQ Receivers
// -------------------
// -------------------
// Command Source (Output)
// -------------------
output reg [31 : 0] sender_irq
);
initial sender_irq = 0;
always @* begin
sender_irq = 0;
end
endmodule
|
module soc_system_mm_interconnect_0_cmd_demux
(
// -------------------
// Sink
// -------------------
input [1-1 : 0] sink_valid,
input [112-1 : 0] sink_data, // ST_DATA_W=112
input [2-1 : 0] sink_channel, // ST_CHANNEL_W=2
input sink_startofpacket,
input sink_endofpacket,
output sink_ready,
// -------------------
// Sources
// -------------------
output reg src0_valid,
output reg [112-1 : 0] src0_data, // ST_DATA_W=112
output reg [2-1 : 0] src0_channel, // ST_CHANNEL_W=2
output reg src0_startofpacket,
output reg src0_endofpacket,
input src0_ready,
// -------------------
// Clock & Reset
// -------------------
(*altera_attribute = "-name MESSAGE_DISABLE 15610" *) // setting message suppression on clk
input clk,
(*altera_attribute = "-name MESSAGE_DISABLE 15610" *) // setting message suppression on reset
input reset
);
localparam NUM_OUTPUTS = 1;
wire [NUM_OUTPUTS - 1 : 0] ready_vector;
// -------------------
// Demux
// -------------------
always @* begin
src0_data = sink_data;
src0_startofpacket = sink_startofpacket;
src0_endofpacket = sink_endofpacket;
src0_channel = sink_channel >> NUM_OUTPUTS;
src0_valid = sink_channel[0] && sink_valid;
end
// -------------------
// Backpressure
// -------------------
assign ready_vector[0] = src0_ready;
assign sink_ready = |(sink_channel & {{1{1'b0}},{ready_vector[NUM_OUTPUTS - 1 : 0]}});
endmodule
|
module soc_system_mm_interconnect_0_router_006_default_decode
#(
parameter DEFAULT_CHANNEL = 0,
DEFAULT_WR_CHANNEL = -1,
DEFAULT_RD_CHANNEL = -1,
DEFAULT_DESTID = 0
)
(output [104 - 102 : 0] default_destination_id,
output [7-1 : 0] default_wr_channel,
output [7-1 : 0] default_rd_channel,
output [7-1 : 0] default_src_channel
);
assign default_destination_id =
DEFAULT_DESTID[104 - 102 : 0];
generate
if (DEFAULT_CHANNEL == -1) begin : no_default_channel_assignment
assign default_src_channel = '0;
end
else begin : default_channel_assignment
assign default_src_channel = 7'b1 << DEFAULT_CHANNEL;
end
endgenerate
generate
if (DEFAULT_RD_CHANNEL == -1) begin : no_default_rw_channel_assignment
assign default_wr_channel = '0;
assign default_rd_channel = '0;
end
else begin : default_rw_channel_assignment
assign default_wr_channel = 7'b1 << DEFAULT_WR_CHANNEL;
assign default_rd_channel = 7'b1 << DEFAULT_RD_CHANNEL;
end
endgenerate
endmodule
|
module soc_system_mm_interconnect_0_router_006
(
// -------------------
// Clock & Reset
// -------------------
input clk,
input reset,
// -------------------
// Command Sink (Input)
// -------------------
input sink_valid,
input [129-1 : 0] sink_data,
input sink_startofpacket,
input sink_endofpacket,
output sink_ready,
// -------------------
// Command Source (Output)
// -------------------
output src_valid,
output reg [129-1 : 0] src_data,
output reg [7-1 : 0] src_channel,
output src_startofpacket,
output src_endofpacket,
input src_ready
);
// -------------------------------------------------------
// Local parameters and variables
// -------------------------------------------------------
localparam PKT_ADDR_H = 67;
localparam PKT_ADDR_L = 36;
localparam PKT_DEST_ID_H = 104;
localparam PKT_DEST_ID_L = 102;
localparam PKT_PROTECTION_H = 119;
localparam PKT_PROTECTION_L = 117;
localparam ST_DATA_W = 129;
localparam ST_CHANNEL_W = 7;
localparam DECODER_TYPE = 1;
localparam PKT_TRANS_WRITE = 70;
localparam PKT_TRANS_READ = 71;
localparam PKT_ADDR_W = PKT_ADDR_H-PKT_ADDR_L + 1;
localparam PKT_DEST_ID_W = PKT_DEST_ID_H-PKT_DEST_ID_L + 1;
// -------------------------------------------------------
// Figure out the number of bits to mask off for each slave span
// during address decoding
// -------------------------------------------------------
// -------------------------------------------------------
// Work out which address bits are significant based on the
// address range of the slaves. If the required width is too
// large or too small, we use the address field width instead.
// -------------------------------------------------------
localparam ADDR_RANGE = 64'h0;
localparam RANGE_ADDR_WIDTH = log2ceil(ADDR_RANGE);
localparam OPTIMIZED_ADDR_H = (RANGE_ADDR_WIDTH > PKT_ADDR_W) ||
(RANGE_ADDR_WIDTH == 0) ?
PKT_ADDR_H :
PKT_ADDR_L + RANGE_ADDR_WIDTH - 1;
localparam RG = RANGE_ADDR_WIDTH;
localparam REAL_ADDRESS_RANGE = OPTIMIZED_ADDR_H - PKT_ADDR_L;
reg [PKT_DEST_ID_W-1 : 0] destid;
// -------------------------------------------------------
// Pass almost everything through, untouched
// -------------------------------------------------------
assign sink_ready = src_ready;
assign src_valid = sink_valid;
assign src_startofpacket = sink_startofpacket;
assign src_endofpacket = sink_endofpacket;
wire [7-1 : 0] default_src_channel;
// -------------------------------------------------------
// Write and read transaction signals
// -------------------------------------------------------
wire write_transaction;
assign write_transaction = sink_data[PKT_TRANS_WRITE];
wire read_transaction;
assign read_transaction = sink_data[PKT_TRANS_READ];
soc_system_mm_interconnect_0_router_006_default_decode the_default_decode(
.default_destination_id (),
.default_wr_channel (),
.default_rd_channel (),
.default_src_channel (default_src_channel)
);
always @* begin
src_data = sink_data;
src_channel = default_src_channel;
// --------------------------------------------------
// DestinationID Decoder
// Sets the channel based on the destination ID.
// --------------------------------------------------
destid = sink_data[PKT_DEST_ID_H : PKT_DEST_ID_L];
if (destid == 0 ) begin
src_channel = 7'b001;
end
if (destid == 2 && write_transaction) begin
src_channel = 7'b010;
end
if (destid == 2 && read_transaction) begin
src_channel = 7'b100;
end
end
// --------------------------------------------------
// Ceil(log2()) function
// --------------------------------------------------
function integer log2ceil;
input reg[65:0] val;
reg [65:0] i;
begin
i = 1;
log2ceil = 0;
while (i < val) begin
log2ceil = log2ceil + 1;
i = i << 1;
end
end
endfunction
endmodule
|
module soc_system_mm_interconnect_1_router_001_default_decode
#(
parameter DEFAULT_CHANNEL = 1,
DEFAULT_WR_CHANNEL = -1,
DEFAULT_RD_CHANNEL = -1,
DEFAULT_DESTID = 0
)
(output [92 - 90 : 0] default_destination_id,
output [7-1 : 0] default_wr_channel,
output [7-1 : 0] default_rd_channel,
output [7-1 : 0] default_src_channel
);
assign default_destination_id =
DEFAULT_DESTID[92 - 90 : 0];
generate
if (DEFAULT_CHANNEL == -1) begin : no_default_channel_assignment
assign default_src_channel = '0;
end
else begin : default_channel_assignment
assign default_src_channel = 7'b1 << DEFAULT_CHANNEL;
end
endgenerate
generate
if (DEFAULT_RD_CHANNEL == -1) begin : no_default_rw_channel_assignment
assign default_wr_channel = '0;
assign default_rd_channel = '0;
end
else begin : default_rw_channel_assignment
assign default_wr_channel = 7'b1 << DEFAULT_WR_CHANNEL;
assign default_rd_channel = 7'b1 << DEFAULT_RD_CHANNEL;
end
endgenerate
endmodule
|
module soc_system_mm_interconnect_1_router_001
(
// -------------------
// Clock & Reset
// -------------------
input clk,
input reset,
// -------------------
// Command Sink (Input)
// -------------------
input sink_valid,
input [106-1 : 0] sink_data,
input sink_startofpacket,
input sink_endofpacket,
output sink_ready,
// -------------------
// Command Source (Output)
// -------------------
output src_valid,
output reg [106-1 : 0] src_data,
output reg [7-1 : 0] src_channel,
output src_startofpacket,
output src_endofpacket,
input src_ready
);
// -------------------------------------------------------
// Local parameters and variables
// -------------------------------------------------------
localparam PKT_ADDR_H = 67;
localparam PKT_ADDR_L = 36;
localparam PKT_DEST_ID_H = 92;
localparam PKT_DEST_ID_L = 90;
localparam PKT_PROTECTION_H = 96;
localparam PKT_PROTECTION_L = 94;
localparam ST_DATA_W = 106;
localparam ST_CHANNEL_W = 7;
localparam DECODER_TYPE = 0;
localparam PKT_TRANS_WRITE = 70;
localparam PKT_TRANS_READ = 71;
localparam PKT_ADDR_W = PKT_ADDR_H-PKT_ADDR_L + 1;
localparam PKT_DEST_ID_W = PKT_DEST_ID_H-PKT_DEST_ID_L + 1;
// -------------------------------------------------------
// Figure out the number of bits to mask off for each slave span
// during address decoding
// -------------------------------------------------------
localparam PAD0 = log2ceil(64'h1008 - 64'h1000);
localparam PAD1 = log2ceil(64'h2008 - 64'h2000);
localparam PAD2 = log2ceil(64'h3010 - 64'h3000);
localparam PAD3 = log2ceil(64'h4010 - 64'h4000);
localparam PAD4 = log2ceil(64'h5010 - 64'h5000);
localparam PAD5 = log2ceil(64'h30100 - 64'h30000);
// -------------------------------------------------------
// Work out which address bits are significant based on the
// address range of the slaves. If the required width is too
// large or too small, we use the address field width instead.
// -------------------------------------------------------
localparam ADDR_RANGE = 64'h30100;
localparam RANGE_ADDR_WIDTH = log2ceil(ADDR_RANGE);
localparam OPTIMIZED_ADDR_H = (RANGE_ADDR_WIDTH > PKT_ADDR_W) ||
(RANGE_ADDR_WIDTH == 0) ?
PKT_ADDR_H :
PKT_ADDR_L + RANGE_ADDR_WIDTH - 1;
localparam RG = RANGE_ADDR_WIDTH-1;
localparam REAL_ADDRESS_RANGE = OPTIMIZED_ADDR_H - PKT_ADDR_L;
reg [PKT_ADDR_W-1 : 0] address;
always @* begin
address = {PKT_ADDR_W{1'b0}};
address [REAL_ADDRESS_RANGE:0] = sink_data[OPTIMIZED_ADDR_H : PKT_ADDR_L];
end
// -------------------------------------------------------
// Pass almost everything through, untouched
// -------------------------------------------------------
assign sink_ready = src_ready;
assign src_valid = sink_valid;
assign src_startofpacket = sink_startofpacket;
assign src_endofpacket = sink_endofpacket;
wire [PKT_DEST_ID_W-1:0] default_destid;
wire [7-1 : 0] default_src_channel;
// -------------------------------------------------------
// Write and read transaction signals
// -------------------------------------------------------
wire read_transaction;
assign read_transaction = sink_data[PKT_TRANS_READ];
soc_system_mm_interconnect_1_router_001_default_decode the_default_decode(
.default_destination_id (default_destid),
.default_wr_channel (),
.default_rd_channel (),
.default_src_channel (default_src_channel)
);
always @* begin
src_data = sink_data;
src_channel = default_src_channel;
src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = default_destid;
// --------------------------------------------------
// Address Decoder
// Sets the channel and destination ID based on the address
// --------------------------------------------------
// ( 0x1000 .. 0x1008 )
if ( {address[RG:PAD0],{PAD0{1'b0}}} == 18'h1000 && read_transaction ) begin
src_channel = 7'b000100;
src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 6;
end
// ( 0x2000 .. 0x2008 )
if ( {address[RG:PAD1],{PAD1{1'b0}}} == 18'h2000 ) begin
src_channel = 7'b000001;
src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 3;
end
// ( 0x3000 .. 0x3010 )
if ( {address[RG:PAD2],{PAD2{1'b0}}} == 18'h3000 ) begin
src_channel = 7'b001000;
src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 4;
end
// ( 0x4000 .. 0x4010 )
if ( {address[RG:PAD3],{PAD3{1'b0}}} == 18'h4000 ) begin
src_channel = 7'b010000;
src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 2;
end
// ( 0x5000 .. 0x5010 )
if ( {address[RG:PAD4],{PAD4{1'b0}}} == 18'h5000 ) begin
src_channel = 7'b100000;
src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 1;
end
// ( 0x30000 .. 0x30100 )
if ( {address[RG:PAD5],{PAD5{1'b0}}} == 18'h30000 ) begin
src_channel = 7'b000010;
src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 0;
end
end
// --------------------------------------------------
// Ceil(log2()) function
// --------------------------------------------------
function integer log2ceil;
input reg[65:0] val;
reg [65:0] i;
begin
i = 1;
log2ceil = 0;
while (i < val) begin
log2ceil = log2ceil + 1;
i = i << 1;
end
end
endfunction
endmodule
|
module soc_system_mm_interconnect_0_rsp_mux_003
(
// ----------------------
// Sinks
// ----------------------
input sink0_valid,
input [129-1 : 0] sink0_data,
input [7-1: 0] sink0_channel,
input sink0_startofpacket,
input sink0_endofpacket,
output sink0_ready,
input sink1_valid,
input [129-1 : 0] sink1_data,
input [7-1: 0] sink1_channel,
input sink1_startofpacket,
input sink1_endofpacket,
output sink1_ready,
input sink2_valid,
input [129-1 : 0] sink2_data,
input [7-1: 0] sink2_channel,
input sink2_startofpacket,
input sink2_endofpacket,
output sink2_ready,
input sink3_valid,
input [129-1 : 0] sink3_data,
input [7-1: 0] sink3_channel,
input sink3_startofpacket,
input sink3_endofpacket,
output sink3_ready,
input sink4_valid,
input [129-1 : 0] sink4_data,
input [7-1: 0] sink4_channel,
input sink4_startofpacket,
input sink4_endofpacket,
output sink4_ready,
// ----------------------
// Source
// ----------------------
output src_valid,
output [129-1 : 0] src_data,
output [7-1 : 0] src_channel,
output src_startofpacket,
output src_endofpacket,
input src_ready,
// ----------------------
// Clock & Reset
// ----------------------
input clk,
input reset
);
localparam PAYLOAD_W = 129 + 7 + 2;
localparam NUM_INPUTS = 5;
localparam SHARE_COUNTER_W = 1;
localparam PIPELINE_ARB = 0;
localparam ST_DATA_W = 129;
localparam ST_CHANNEL_W = 7;
localparam PKT_TRANS_LOCK = 72;
// ------------------------------------------
// Signals
// ------------------------------------------
wire [NUM_INPUTS - 1 : 0] request;
wire [NUM_INPUTS - 1 : 0] valid;
wire [NUM_INPUTS - 1 : 0] grant;
wire [NUM_INPUTS - 1 : 0] next_grant;
reg [NUM_INPUTS - 1 : 0] saved_grant;
reg [PAYLOAD_W - 1 : 0] src_payload;
wire last_cycle;
reg packet_in_progress;
reg update_grant;
wire [PAYLOAD_W - 1 : 0] sink0_payload;
wire [PAYLOAD_W - 1 : 0] sink1_payload;
wire [PAYLOAD_W - 1 : 0] sink2_payload;
wire [PAYLOAD_W - 1 : 0] sink3_payload;
wire [PAYLOAD_W - 1 : 0] sink4_payload;
assign valid[0] = sink0_valid;
assign valid[1] = sink1_valid;
assign valid[2] = sink2_valid;
assign valid[3] = sink3_valid;
assign valid[4] = sink4_valid;
// ------------------------------------------
// ------------------------------------------
// Grant Logic & Updates
// ------------------------------------------
// ------------------------------------------
reg [NUM_INPUTS - 1 : 0] lock;
always @* begin
lock[0] = sink0_data[72];
lock[1] = sink1_data[72];
lock[2] = sink2_data[72];
lock[3] = sink3_data[72];
lock[4] = sink4_data[72];
end
assign last_cycle = src_valid & src_ready & src_endofpacket & ~(|(lock & grant));
// ------------------------------------------
// We're working on a packet at any time valid is high, except
// when this is the endofpacket.
// ------------------------------------------
always @(posedge clk or posedge reset) begin
if (reset) begin
packet_in_progress <= 1'b0;
end
else begin
if (last_cycle)
packet_in_progress <= 1'b0;
else if (src_valid)
packet_in_progress <= 1'b1;
end
end
// ------------------------------------------
// Shares
//
// Special case: all-equal shares _should_ be optimized into assigning a
// constant to next_grant_share.
// Special case: all-1's shares _should_ result in the share counter
// being optimized away.
// ------------------------------------------
// Input | arb shares | counter load value
// 0 | 1 | 0
// 1 | 1 | 0
// 2 | 1 | 0
// 3 | 1 | 0
// 4 | 1 | 0
wire [SHARE_COUNTER_W - 1 : 0] share_0 = 1'd0;
wire [SHARE_COUNTER_W - 1 : 0] share_1 = 1'd0;
wire [SHARE_COUNTER_W - 1 : 0] share_2 = 1'd0;
wire [SHARE_COUNTER_W - 1 : 0] share_3 = 1'd0;
wire [SHARE_COUNTER_W - 1 : 0] share_4 = 1'd0;
// ------------------------------------------
// Choose the share value corresponding to the grant.
// ------------------------------------------
reg [SHARE_COUNTER_W - 1 : 0] next_grant_share;
always @* begin
next_grant_share =
share_0 & { SHARE_COUNTER_W {next_grant[0]} } |
share_1 & { SHARE_COUNTER_W {next_grant[1]} } |
share_2 & { SHARE_COUNTER_W {next_grant[2]} } |
share_3 & { SHARE_COUNTER_W {next_grant[3]} } |
share_4 & { SHARE_COUNTER_W {next_grant[4]} };
end
// ------------------------------------------
// Flag to indicate first packet of an arb sequence.
// ------------------------------------------
wire grant_changed = ~packet_in_progress && ~(|(saved_grant & valid));
reg first_packet_r;
wire first_packet = grant_changed | first_packet_r;
always @(posedge clk or posedge reset) begin
if (reset) begin
first_packet_r <= 1'b0;
end
else begin
if (update_grant)
first_packet_r <= 1'b1;
else if (last_cycle)
first_packet_r <= 1'b0;
else if (grant_changed)
first_packet_r <= 1'b1;
end
end
// ------------------------------------------
// Compute the next share-count value.
// ------------------------------------------
reg [SHARE_COUNTER_W - 1 : 0] p1_share_count;
reg [SHARE_COUNTER_W - 1 : 0] share_count;
reg share_count_zero_flag;
always @* begin
if (first_packet) begin
p1_share_count = next_grant_share;
end
else begin
// Update the counter, but don't decrement below 0.
p1_share_count = share_count_zero_flag ? '0 : share_count - 1'b1;
end
end
// ------------------------------------------
// Update the share counter and share-counter=zero flag.
// ------------------------------------------
always @(posedge clk or posedge reset) begin
if (reset) begin
share_count <= '0;
share_count_zero_flag <= 1'b1;
end
else begin
if (last_cycle) begin
share_count <= p1_share_count;
share_count_zero_flag <= (p1_share_count == '0);
end
end
end
// ------------------------------------------
// For each input, maintain a final_packet signal which goes active for the
// last packet of a full-share packet sequence. Example: if I have 4
// shares and I'm continuously requesting, final_packet is active in the
// 4th packet.
// ------------------------------------------
wire final_packet_0 = 1'b1;
wire final_packet_1 = 1'b1;
wire final_packet_2 = 1'b1;
wire final_packet_3 = 1'b1;
wire final_packet_4 = 1'b1;
// ------------------------------------------
// Concatenate all final_packet signals (wire or reg) into a handy vector.
// ------------------------------------------
wire [NUM_INPUTS - 1 : 0] final_packet = {
final_packet_4,
final_packet_3,
final_packet_2,
final_packet_1,
final_packet_0
};
// ------------------------------------------
// ------------------------------------------
wire p1_done = |(final_packet & grant);
// ------------------------------------------
// Flag for the first cycle of packets within an
// arb sequence
// ------------------------------------------
reg first_cycle;
always @(posedge clk, posedge reset) begin
if (reset)
first_cycle <= 0;
else
first_cycle <= last_cycle && ~p1_done;
end
always @* begin
update_grant = 0;
// ------------------------------------------
// No arbitration pipeline, update grant whenever
// the current arb winner has consumed all shares,
// or all requests are low
// ------------------------------------------
update_grant = (last_cycle && p1_done) || (first_cycle && ~(|valid));
update_grant = last_cycle;
end
wire save_grant;
assign save_grant = 1;
assign grant = next_grant;
always @(posedge clk, posedge reset) begin
if (reset)
saved_grant <= '0;
else if (save_grant)
saved_grant <= next_grant;
end
// ------------------------------------------
// ------------------------------------------
// Arbitrator
// ------------------------------------------
// ------------------------------------------
// ------------------------------------------
// Create a request vector that stays high during
// the packet for unpipelined arbitration.
//
// The pipelined arbitration scheme does not require
// request to be held high during the packet.
// ------------------------------------------
assign request = valid;
wire [NUM_INPUTS - 1 : 0] next_grant_from_arb;
altera_merlin_arbitrator
#(
.NUM_REQUESTERS(NUM_INPUTS),
.SCHEME ("no-arb"),
.PIPELINE (0)
) arb (
.clk (clk),
.reset (reset),
.request (request),
.grant (next_grant_from_arb),
.save_top_priority (src_valid),
.increment_top_priority (update_grant)
);
assign next_grant = next_grant_from_arb;
// ------------------------------------------
// ------------------------------------------
// Mux
//
// Implemented as a sum of products.
// ------------------------------------------
// ------------------------------------------
assign sink0_ready = src_ready && grant[0];
assign sink1_ready = src_ready && grant[1];
assign sink2_ready = src_ready && grant[2];
assign sink3_ready = src_ready && grant[3];
assign sink4_ready = src_ready && grant[4];
assign src_valid = |(grant & valid);
always @* begin
src_payload =
sink0_payload & {PAYLOAD_W {grant[0]} } |
sink1_payload & {PAYLOAD_W {grant[1]} } |
sink2_payload & {PAYLOAD_W {grant[2]} } |
sink3_payload & {PAYLOAD_W {grant[3]} } |
sink4_payload & {PAYLOAD_W {grant[4]} };
end
// ------------------------------------------
// Mux Payload Mapping
// ------------------------------------------
assign sink0_payload = {sink0_channel,sink0_data,
sink0_startofpacket,sink0_endofpacket};
assign sink1_payload = {sink1_channel,sink1_data,
sink1_startofpacket,sink1_endofpacket};
assign sink2_payload = {sink2_channel,sink2_data,
sink2_startofpacket,sink2_endofpacket};
assign sink3_payload = {sink3_channel,sink3_data,
sink3_startofpacket,sink3_endofpacket};
assign sink4_payload = {sink4_channel,sink4_data,
sink4_startofpacket,sink4_endofpacket};
assign {src_channel,src_data,src_startofpacket,src_endofpacket} = src_payload;
endmodule
|
module hps_sdram_pll (
global_reset_n,
pll_ref_clk,
pll_mem_clk,
pll_write_clk,
pll_write_clk_pre_phy_clk,
pll_addr_cmd_clk,
pll_avl_clk,
pll_config_clk,
pll_locked,
afi_clk,
pll_mem_phy_clk,
afi_phy_clk,
pll_avl_phy_clk,
afi_half_clk
);
// ********************************************************************************************************************************
// BEGIN PARAMETER SECTION
// All parameters default to "" will have their values passed in from higher level wrapper with the controller and driver.
parameter DEVICE_FAMILY = "Cyclone V";
parameter IS_HHP_HPS = "true";
// Clock settings
parameter GENERIC_PLL = "true";
parameter REF_CLK_FREQ = "25.0 MHz";
parameter REF_CLK_PERIOD_PS = 40000;
parameter PLL_MEM_CLK_FREQ_STR = "400.0 MHz";
parameter PLL_WRITE_CLK_FREQ_STR = "400.0 MHz";
parameter PLL_DR_CLK_FREQ_STR = "";
parameter PLL_MEM_CLK_FREQ_SIM_STR = "2500 ps";
parameter PLL_WRITE_CLK_FREQ_SIM_STR = "2500 ps";
parameter PLL_DR_CLK_FREQ_SIM_STR = "0 ps";
parameter MEM_CLK_PHASE = "0 ps";
parameter WRITE_CLK_PHASE = "1875 ps";
parameter DR_CLK_PHASE = "";
localparam SIM_FILESET = ("false" == "true");
localparam MEM_CLK_FREQ = SIM_FILESET ? PLL_MEM_CLK_FREQ_SIM_STR : PLL_MEM_CLK_FREQ_STR;
localparam WRITE_CLK_FREQ = SIM_FILESET ? PLL_WRITE_CLK_FREQ_SIM_STR : PLL_WRITE_CLK_FREQ_STR;
localparam DR_CLK_FREQ = SIM_FILESET ? PLL_DR_CLK_FREQ_SIM_STR : PLL_DR_CLK_FREQ_STR;
// END PARAMETER SECTION
// ********************************************************************************************************************************
// ********************************************************************************************************************************
// BEGIN PORT SECTION
input global_reset_n; // Resets (active-low) the whole system (all PHY logic + PLL)
input pll_ref_clk; // PLL reference clock
output pll_mem_clk;
output pll_write_clk;
output pll_write_clk_pre_phy_clk;
output pll_addr_cmd_clk;
output pll_avl_clk;
output pll_config_clk;
output pll_locked;
output afi_clk;
output pll_mem_phy_clk;
output afi_phy_clk;
output pll_avl_phy_clk;
output afi_half_clk;
// END PORT SECTION
// ********************************************************************************************************************************
generate
if (SIM_FILESET) begin
wire fbout;
generic_pll pll1 (
.refclk({pll_ref_clk}),
.rst(~global_reset_n),
.fbclk(fbout),
.outclk(pll_mem_clk),
.fboutclk(fbout),
.locked(pll_locked)
);
defparam pll1.reference_clock_frequency = REF_CLK_FREQ,
pll1.output_clock_frequency = MEM_CLK_FREQ,
pll1.phase_shift = MEM_CLK_PHASE,
pll1.duty_cycle = 50;
generic_pll pll2 (
.refclk({pll_ref_clk}),
.rst(~global_reset_n),
.fbclk(fbout),
.outclk(pll_write_clk),
.fboutclk(),
.locked()
);
defparam pll2.reference_clock_frequency = REF_CLK_FREQ,
pll2.output_clock_frequency = WRITE_CLK_FREQ,
pll2.phase_shift = WRITE_CLK_PHASE,
pll2.duty_cycle = 50;
end else begin
wire [4-1:0] clk_out;
if (DEVICE_FAMILY == "Arria V") begin
arriav_hps_sdram_pll pll (
.clk_out(clk_out)
);
defparam pll.reference_clock_frequency = REF_CLK_FREQ,
pll.clk0_frequency = MEM_CLK_FREQ,
pll.clk0_phase_shift = MEM_CLK_PHASE,
pll.clk1_frequency = WRITE_CLK_FREQ,
pll.clk1_phase_shift = WRITE_CLK_PHASE,
pll.clk2_frequency = DR_CLK_FREQ,
pll.clk2_phase_shift = DR_CLK_PHASE;
end else if (DEVICE_FAMILY == "Cyclone V") begin
cyclonev_hps_sdram_pll pll (
.clk_out(clk_out)
);
defparam pll.reference_clock_frequency = REF_CLK_FREQ,
pll.clk0_frequency = MEM_CLK_FREQ,
pll.clk0_phase_shift = MEM_CLK_PHASE,
pll.clk1_frequency = WRITE_CLK_FREQ,
pll.clk1_phase_shift = WRITE_CLK_PHASE,
pll.clk2_frequency = DR_CLK_FREQ,
pll.clk2_phase_shift = DR_CLK_PHASE;
end else begin
unknown_family_hps_sdram_pll pll();
end
assign pll_mem_clk = clk_out[0];
assign pll_write_clk = clk_out[1];
assign pll_dr_clk = clk_out[2];
end
endgenerate
assign pll_addr_cmd_clk = pll_mem_clk;
assign pll_avl_clk = pll_mem_clk;
assign pll_config_clk = pll_mem_clk;
assign afi_clk = pll_mem_clk;
assign pll_mem_phy_clk = pll_mem_clk;
assign afi_phy_clk = pll_mem_clk;
assign pll_avl_phy_clk = pll_mem_clk;
assign afi_half_clk = pll_mem_clk;
assign pll_write_clk_pre_phy_clk = pll_write_clk;
endmodule
|
module soc_system_mm_interconnect_2_cmd_demux
(
// -------------------
// Sink
// -------------------
input [2-1 : 0] sink_valid,
input [118-1 : 0] sink_data, // ST_DATA_W=118
input [2-1 : 0] sink_channel, // ST_CHANNEL_W=2
input sink_startofpacket,
input sink_endofpacket,
output sink_ready,
// -------------------
// Sources
// -------------------
output reg src0_valid,
output reg [118-1 : 0] src0_data, // ST_DATA_W=118
output reg [2-1 : 0] src0_channel, // ST_CHANNEL_W=2
output reg src0_startofpacket,
output reg src0_endofpacket,
input src0_ready,
output reg src1_valid,
output reg [118-1 : 0] src1_data, // ST_DATA_W=118
output reg [2-1 : 0] src1_channel, // ST_CHANNEL_W=2
output reg src1_startofpacket,
output reg src1_endofpacket,
input src1_ready,
// -------------------
// Clock & Reset
// -------------------
(*altera_attribute = "-name MESSAGE_DISABLE 15610" *) // setting message suppression on clk
input clk,
(*altera_attribute = "-name MESSAGE_DISABLE 15610" *) // setting message suppression on reset
input reset
);
localparam NUM_OUTPUTS = 2;
wire [NUM_OUTPUTS - 1 : 0] ready_vector;
// -------------------
// Demux
// -------------------
always @* begin
src0_data = sink_data;
src0_startofpacket = sink_startofpacket;
src0_endofpacket = sink_endofpacket;
src0_channel = sink_channel >> NUM_OUTPUTS;
src0_valid = sink_channel[0] && sink_valid[0];
src1_data = sink_data;
src1_startofpacket = sink_startofpacket;
src1_endofpacket = sink_endofpacket;
src1_channel = sink_channel >> NUM_OUTPUTS;
src1_valid = sink_channel[1] && sink_valid[1];
end
// -------------------
// Backpressure
// -------------------
assign ready_vector[0] = src0_ready;
assign ready_vector[1] = src1_ready;
assign sink_ready = |(sink_channel & ready_vector);
endmodule
|
module soc_system_mm_interconnect_2_router_001_default_decode
#(
parameter DEFAULT_CHANNEL = 0,
DEFAULT_WR_CHANNEL = -1,
DEFAULT_RD_CHANNEL = -1,
DEFAULT_DESTID = 0
)
(output [140 - 140 : 0] default_destination_id,
output [2-1 : 0] default_wr_channel,
output [2-1 : 0] default_rd_channel,
output [2-1 : 0] default_src_channel
);
assign default_destination_id =
DEFAULT_DESTID[140 - 140 : 0];
generate
if (DEFAULT_CHANNEL == -1) begin : no_default_channel_assignment
assign default_src_channel = '0;
end
else begin : default_channel_assignment
assign default_src_channel = 2'b1 << DEFAULT_CHANNEL;
end
endgenerate
generate
if (DEFAULT_RD_CHANNEL == -1) begin : no_default_rw_channel_assignment
assign default_wr_channel = '0;
assign default_rd_channel = '0;
end
else begin : default_rw_channel_assignment
assign default_wr_channel = 2'b1 << DEFAULT_WR_CHANNEL;
assign default_rd_channel = 2'b1 << DEFAULT_RD_CHANNEL;
end
endgenerate
endmodule
|
module soc_system_mm_interconnect_2_router_001
(
// -------------------
// Clock & Reset
// -------------------
input clk,
input reset,
// -------------------
// Command Sink (Input)
// -------------------
input sink_valid,
input [154-1 : 0] sink_data,
input sink_startofpacket,
input sink_endofpacket,
output sink_ready,
// -------------------
// Command Source (Output)
// -------------------
output src_valid,
output reg [154-1 : 0] src_data,
output reg [2-1 : 0] src_channel,
output src_startofpacket,
output src_endofpacket,
input src_ready
);
// -------------------------------------------------------
// Local parameters and variables
// -------------------------------------------------------
localparam PKT_ADDR_H = 103;
localparam PKT_ADDR_L = 72;
localparam PKT_DEST_ID_H = 140;
localparam PKT_DEST_ID_L = 140;
localparam PKT_PROTECTION_H = 144;
localparam PKT_PROTECTION_L = 142;
localparam ST_DATA_W = 154;
localparam ST_CHANNEL_W = 2;
localparam DECODER_TYPE = 1;
localparam PKT_TRANS_WRITE = 106;
localparam PKT_TRANS_READ = 107;
localparam PKT_ADDR_W = PKT_ADDR_H-PKT_ADDR_L + 1;
localparam PKT_DEST_ID_W = PKT_DEST_ID_H-PKT_DEST_ID_L + 1;
// -------------------------------------------------------
// Figure out the number of bits to mask off for each slave span
// during address decoding
// -------------------------------------------------------
// -------------------------------------------------------
// Work out which address bits are significant based on the
// address range of the slaves. If the required width is too
// large or too small, we use the address field width instead.
// -------------------------------------------------------
localparam ADDR_RANGE = 64'h0;
localparam RANGE_ADDR_WIDTH = log2ceil(ADDR_RANGE);
localparam OPTIMIZED_ADDR_H = (RANGE_ADDR_WIDTH > PKT_ADDR_W) ||
(RANGE_ADDR_WIDTH == 0) ?
PKT_ADDR_H :
PKT_ADDR_L + RANGE_ADDR_WIDTH - 1;
localparam RG = RANGE_ADDR_WIDTH;
localparam REAL_ADDRESS_RANGE = OPTIMIZED_ADDR_H - PKT_ADDR_L;
reg [PKT_DEST_ID_W-1 : 0] destid;
// -------------------------------------------------------
// Pass almost everything through, untouched
// -------------------------------------------------------
assign sink_ready = src_ready;
assign src_valid = sink_valid;
assign src_startofpacket = sink_startofpacket;
assign src_endofpacket = sink_endofpacket;
wire [2-1 : 0] default_src_channel;
soc_system_mm_interconnect_2_router_001_default_decode the_default_decode(
.default_destination_id (),
.default_wr_channel (),
.default_rd_channel (),
.default_src_channel (default_src_channel)
);
always @* begin
src_data = sink_data;
src_channel = default_src_channel;
// --------------------------------------------------
// DestinationID Decoder
// Sets the channel based on the destination ID.
// --------------------------------------------------
destid = sink_data[PKT_DEST_ID_H : PKT_DEST_ID_L];
if (destid == 0 ) begin
src_channel = 2'b1;
end
end
// --------------------------------------------------
// Ceil(log2()) function
// --------------------------------------------------
function integer log2ceil;
input reg[65:0] val;
reg [65:0] i;
begin
i = 1;
log2ceil = 0;
while (i < val) begin
log2ceil = log2ceil + 1;
i = i << 1;
end
end
endfunction
endmodule
|
module soc_system_mm_interconnect_2_rsp_mux
(
// ----------------------
// Sinks
// ----------------------
input sink0_valid,
input [118-1 : 0] sink0_data,
input [2-1: 0] sink0_channel,
input sink0_startofpacket,
input sink0_endofpacket,
output sink0_ready,
input sink1_valid,
input [118-1 : 0] sink1_data,
input [2-1: 0] sink1_channel,
input sink1_startofpacket,
input sink1_endofpacket,
output sink1_ready,
// ----------------------
// Source
// ----------------------
output src_valid,
output [118-1 : 0] src_data,
output [2-1 : 0] src_channel,
output src_startofpacket,
output src_endofpacket,
input src_ready,
// ----------------------
// Clock & Reset
// ----------------------
input clk,
input reset
);
localparam PAYLOAD_W = 118 + 2 + 2;
localparam NUM_INPUTS = 2;
localparam SHARE_COUNTER_W = 1;
localparam PIPELINE_ARB = 0;
localparam ST_DATA_W = 118;
localparam ST_CHANNEL_W = 2;
localparam PKT_TRANS_LOCK = 72;
// ------------------------------------------
// Signals
// ------------------------------------------
wire [NUM_INPUTS - 1 : 0] request;
wire [NUM_INPUTS - 1 : 0] valid;
wire [NUM_INPUTS - 1 : 0] grant;
wire [NUM_INPUTS - 1 : 0] next_grant;
reg [NUM_INPUTS - 1 : 0] saved_grant;
reg [PAYLOAD_W - 1 : 0] src_payload;
wire last_cycle;
reg packet_in_progress;
reg update_grant;
wire [PAYLOAD_W - 1 : 0] sink0_payload;
wire [PAYLOAD_W - 1 : 0] sink1_payload;
assign valid[0] = sink0_valid;
assign valid[1] = sink1_valid;
// ------------------------------------------
// ------------------------------------------
// Grant Logic & Updates
// ------------------------------------------
// ------------------------------------------
reg [NUM_INPUTS - 1 : 0] lock;
always @* begin
lock[0] = sink0_data[72];
lock[1] = sink1_data[72];
end
assign last_cycle = src_valid & src_ready & src_endofpacket & ~(|(lock & grant));
// ------------------------------------------
// We're working on a packet at any time valid is high, except
// when this is the endofpacket.
// ------------------------------------------
always @(posedge clk or posedge reset) begin
if (reset) begin
packet_in_progress <= 1'b0;
end
else begin
if (last_cycle)
packet_in_progress <= 1'b0;
else if (src_valid)
packet_in_progress <= 1'b1;
end
end
// ------------------------------------------
// Shares
//
// Special case: all-equal shares _should_ be optimized into assigning a
// constant to next_grant_share.
// Special case: all-1's shares _should_ result in the share counter
// being optimized away.
// ------------------------------------------
// Input | arb shares | counter load value
// 0 | 1 | 0
// 1 | 1 | 0
wire [SHARE_COUNTER_W - 1 : 0] share_0 = 1'd0;
wire [SHARE_COUNTER_W - 1 : 0] share_1 = 1'd0;
// ------------------------------------------
// Choose the share value corresponding to the grant.
// ------------------------------------------
reg [SHARE_COUNTER_W - 1 : 0] next_grant_share;
always @* begin
next_grant_share =
share_0 & { SHARE_COUNTER_W {next_grant[0]} } |
share_1 & { SHARE_COUNTER_W {next_grant[1]} };
end
// ------------------------------------------
// Flag to indicate first packet of an arb sequence.
// ------------------------------------------
wire grant_changed = ~packet_in_progress && ~(|(saved_grant & valid));
reg first_packet_r;
wire first_packet = grant_changed | first_packet_r;
always @(posedge clk or posedge reset) begin
if (reset) begin
first_packet_r <= 1'b0;
end
else begin
if (update_grant)
first_packet_r <= 1'b1;
else if (last_cycle)
first_packet_r <= 1'b0;
else if (grant_changed)
first_packet_r <= 1'b1;
end
end
// ------------------------------------------
// Compute the next share-count value.
// ------------------------------------------
reg [SHARE_COUNTER_W - 1 : 0] p1_share_count;
reg [SHARE_COUNTER_W - 1 : 0] share_count;
reg share_count_zero_flag;
always @* begin
if (first_packet) begin
p1_share_count = next_grant_share;
end
else begin
// Update the counter, but don't decrement below 0.
p1_share_count = share_count_zero_flag ? '0 : share_count - 1'b1;
end
end
// ------------------------------------------
// Update the share counter and share-counter=zero flag.
// ------------------------------------------
always @(posedge clk or posedge reset) begin
if (reset) begin
share_count <= '0;
share_count_zero_flag <= 1'b1;
end
else begin
if (last_cycle) begin
share_count <= p1_share_count;
share_count_zero_flag <= (p1_share_count == '0);
end
end
end
// ------------------------------------------
// For each input, maintain a final_packet signal which goes active for the
// last packet of a full-share packet sequence. Example: if I have 4
// shares and I'm continuously requesting, final_packet is active in the
// 4th packet.
// ------------------------------------------
wire final_packet_0 = 1'b1;
wire final_packet_1 = 1'b1;
// ------------------------------------------
// Concatenate all final_packet signals (wire or reg) into a handy vector.
// ------------------------------------------
wire [NUM_INPUTS - 1 : 0] final_packet = {
final_packet_1,
final_packet_0
};
// ------------------------------------------
// ------------------------------------------
wire p1_done = |(final_packet & grant);
// ------------------------------------------
// Flag for the first cycle of packets within an
// arb sequence
// ------------------------------------------
reg first_cycle;
always @(posedge clk, posedge reset) begin
if (reset)
first_cycle <= 0;
else
first_cycle <= last_cycle && ~p1_done;
end
always @* begin
update_grant = 0;
// ------------------------------------------
// No arbitration pipeline, update grant whenever
// the current arb winner has consumed all shares,
// or all requests are low
// ------------------------------------------
update_grant = (last_cycle && p1_done) || (first_cycle && ~(|valid));
update_grant = last_cycle;
end
wire save_grant;
assign save_grant = 1;
assign grant = next_grant;
always @(posedge clk, posedge reset) begin
if (reset)
saved_grant <= '0;
else if (save_grant)
saved_grant <= next_grant;
end
// ------------------------------------------
// ------------------------------------------
// Arbitrator
// ------------------------------------------
// ------------------------------------------
// ------------------------------------------
// Create a request vector that stays high during
// the packet for unpipelined arbitration.
//
// The pipelined arbitration scheme does not require
// request to be held high during the packet.
// ------------------------------------------
assign request = valid;
wire [NUM_INPUTS - 1 : 0] next_grant_from_arb;
altera_merlin_arbitrator
#(
.NUM_REQUESTERS(NUM_INPUTS),
.SCHEME ("no-arb"),
.PIPELINE (0)
) arb (
.clk (clk),
.reset (reset),
.request (request),
.grant (next_grant_from_arb),
.save_top_priority (src_valid),
.increment_top_priority (update_grant)
);
assign next_grant = next_grant_from_arb;
// ------------------------------------------
// ------------------------------------------
// Mux
//
// Implemented as a sum of products.
// ------------------------------------------
// ------------------------------------------
assign sink0_ready = src_ready && grant[0];
assign sink1_ready = src_ready && grant[1];
assign src_valid = |(grant & valid);
always @* begin
src_payload =
sink0_payload & {PAYLOAD_W {grant[0]} } |
sink1_payload & {PAYLOAD_W {grant[1]} };
end
// ------------------------------------------
// Mux Payload Mapping
// ------------------------------------------
assign sink0_payload = {sink0_channel,sink0_data,
sink0_startofpacket,sink0_endofpacket};
assign sink1_payload = {sink1_channel,sink1_data,
sink1_startofpacket,sink1_endofpacket};
assign {src_channel,src_data,src_startofpacket,src_endofpacket} = src_payload;
endmodule
|
module soc_system_mm_interconnect_3_rsp_mux
(
// ----------------------
// Sinks
// ----------------------
input sink0_valid,
input [118-1 : 0] sink0_data,
input [2-1: 0] sink0_channel,
input sink0_startofpacket,
input sink0_endofpacket,
output sink0_ready,
input sink1_valid,
input [118-1 : 0] sink1_data,
input [2-1: 0] sink1_channel,
input sink1_startofpacket,
input sink1_endofpacket,
output sink1_ready,
// ----------------------
// Source
// ----------------------
output src_valid,
output [118-1 : 0] src_data,
output [2-1 : 0] src_channel,
output src_startofpacket,
output src_endofpacket,
input src_ready,
// ----------------------
// Clock & Reset
// ----------------------
input clk,
input reset
);
localparam PAYLOAD_W = 118 + 2 + 2;
localparam NUM_INPUTS = 2;
localparam SHARE_COUNTER_W = 1;
localparam PIPELINE_ARB = 0;
localparam ST_DATA_W = 118;
localparam ST_CHANNEL_W = 2;
localparam PKT_TRANS_LOCK = 72;
// ------------------------------------------
// Signals
// ------------------------------------------
wire [NUM_INPUTS - 1 : 0] request;
wire [NUM_INPUTS - 1 : 0] valid;
wire [NUM_INPUTS - 1 : 0] grant;
wire [NUM_INPUTS - 1 : 0] next_grant;
reg [NUM_INPUTS - 1 : 0] saved_grant;
reg [PAYLOAD_W - 1 : 0] src_payload;
wire last_cycle;
reg packet_in_progress;
reg update_grant;
wire [PAYLOAD_W - 1 : 0] sink0_payload;
wire [PAYLOAD_W - 1 : 0] sink1_payload;
assign valid[0] = sink0_valid;
assign valid[1] = sink1_valid;
// ------------------------------------------
// ------------------------------------------
// Grant Logic & Updates
// ------------------------------------------
// ------------------------------------------
reg [NUM_INPUTS - 1 : 0] lock;
always @* begin
lock[0] = sink0_data[72];
lock[1] = sink1_data[72];
end
assign last_cycle = src_valid & src_ready & src_endofpacket & ~(|(lock & grant));
// ------------------------------------------
// We're working on a packet at any time valid is high, except
// when this is the endofpacket.
// ------------------------------------------
always @(posedge clk or posedge reset) begin
if (reset) begin
packet_in_progress <= 1'b0;
end
else begin
if (last_cycle)
packet_in_progress <= 1'b0;
else if (src_valid)
packet_in_progress <= 1'b1;
end
end
// ------------------------------------------
// Shares
//
// Special case: all-equal shares _should_ be optimized into assigning a
// constant to next_grant_share.
// Special case: all-1's shares _should_ result in the share counter
// being optimized away.
// ------------------------------------------
// Input | arb shares | counter load value
// 0 | 1 | 0
// 1 | 1 | 0
wire [SHARE_COUNTER_W - 1 : 0] share_0 = 1'd0;
wire [SHARE_COUNTER_W - 1 : 0] share_1 = 1'd0;
// ------------------------------------------
// Choose the share value corresponding to the grant.
// ------------------------------------------
reg [SHARE_COUNTER_W - 1 : 0] next_grant_share;
always @* begin
next_grant_share =
share_0 & { SHARE_COUNTER_W {next_grant[0]} } |
share_1 & { SHARE_COUNTER_W {next_grant[1]} };
end
// ------------------------------------------
// Flag to indicate first packet of an arb sequence.
// ------------------------------------------
wire grant_changed = ~packet_in_progress && ~(|(saved_grant & valid));
reg first_packet_r;
wire first_packet = grant_changed | first_packet_r;
always @(posedge clk or posedge reset) begin
if (reset) begin
first_packet_r <= 1'b0;
end
else begin
if (update_grant)
first_packet_r <= 1'b1;
else if (last_cycle)
first_packet_r <= 1'b0;
else if (grant_changed)
first_packet_r <= 1'b1;
end
end
// ------------------------------------------
// Compute the next share-count value.
// ------------------------------------------
reg [SHARE_COUNTER_W - 1 : 0] p1_share_count;
reg [SHARE_COUNTER_W - 1 : 0] share_count;
reg share_count_zero_flag;
always @* begin
if (first_packet) begin
p1_share_count = next_grant_share;
end
else begin
// Update the counter, but don't decrement below 0.
p1_share_count = share_count_zero_flag ? '0 : share_count - 1'b1;
end
end
// ------------------------------------------
// Update the share counter and share-counter=zero flag.
// ------------------------------------------
always @(posedge clk or posedge reset) begin
if (reset) begin
share_count <= '0;
share_count_zero_flag <= 1'b1;
end
else begin
if (last_cycle) begin
share_count <= p1_share_count;
share_count_zero_flag <= (p1_share_count == '0);
end
end
end
// ------------------------------------------
// For each input, maintain a final_packet signal which goes active for the
// last packet of a full-share packet sequence. Example: if I have 4
// shares and I'm continuously requesting, final_packet is active in the
// 4th packet.
// ------------------------------------------
wire final_packet_0 = 1'b1;
wire final_packet_1 = 1'b1;
// ------------------------------------------
// Concatenate all final_packet signals (wire or reg) into a handy vector.
// ------------------------------------------
wire [NUM_INPUTS - 1 : 0] final_packet = {
final_packet_1,
final_packet_0
};
// ------------------------------------------
// ------------------------------------------
wire p1_done = |(final_packet & grant);
// ------------------------------------------
// Flag for the first cycle of packets within an
// arb sequence
// ------------------------------------------
reg first_cycle;
always @(posedge clk, posedge reset) begin
if (reset)
first_cycle <= 0;
else
first_cycle <= last_cycle && ~p1_done;
end
always @* begin
update_grant = 0;
// ------------------------------------------
// No arbitration pipeline, update grant whenever
// the current arb winner has consumed all shares,
// or all requests are low
// ------------------------------------------
update_grant = (last_cycle && p1_done) || (first_cycle && ~(|valid));
update_grant = last_cycle;
end
wire save_grant;
assign save_grant = 1;
assign grant = next_grant;
always @(posedge clk, posedge reset) begin
if (reset)
saved_grant <= '0;
else if (save_grant)
saved_grant <= next_grant;
end
// ------------------------------------------
// ------------------------------------------
// Arbitrator
// ------------------------------------------
// ------------------------------------------
// ------------------------------------------
// Create a request vector that stays high during
// the packet for unpipelined arbitration.
//
// The pipelined arbitration scheme does not require
// request to be held high during the packet.
// ------------------------------------------
assign request = valid;
wire [NUM_INPUTS - 1 : 0] next_grant_from_arb;
altera_merlin_arbitrator
#(
.NUM_REQUESTERS(NUM_INPUTS),
.SCHEME ("no-arb"),
.PIPELINE (0)
) arb (
.clk (clk),
.reset (reset),
.request (request),
.grant (next_grant_from_arb),
.save_top_priority (src_valid),
.increment_top_priority (update_grant)
);
assign next_grant = next_grant_from_arb;
// ------------------------------------------
// ------------------------------------------
// Mux
//
// Implemented as a sum of products.
// ------------------------------------------
// ------------------------------------------
assign sink0_ready = src_ready && grant[0];
assign sink1_ready = src_ready && grant[1];
assign src_valid = |(grant & valid);
always @* begin
src_payload =
sink0_payload & {PAYLOAD_W {grant[0]} } |
sink1_payload & {PAYLOAD_W {grant[1]} };
end
// ------------------------------------------
// Mux Payload Mapping
// ------------------------------------------
assign sink0_payload = {sink0_channel,sink0_data,
sink0_startofpacket,sink0_endofpacket};
assign sink1_payload = {sink1_channel,sink1_data,
sink1_startofpacket,sink1_endofpacket};
assign {src_channel,src_data,src_startofpacket,src_endofpacket} = src_payload;
endmodule
|
module soc_system_mm_interconnect_0_cmd_mux
(
// ----------------------
// Sinks
// ----------------------
input sink0_valid,
input [112-1 : 0] sink0_data,
input [2-1: 0] sink0_channel,
input sink0_startofpacket,
input sink0_endofpacket,
output sink0_ready,
input sink1_valid,
input [112-1 : 0] sink1_data,
input [2-1: 0] sink1_channel,
input sink1_startofpacket,
input sink1_endofpacket,
output sink1_ready,
// ----------------------
// Source
// ----------------------
output src_valid,
output [112-1 : 0] src_data,
output [2-1 : 0] src_channel,
output src_startofpacket,
output src_endofpacket,
input src_ready,
// ----------------------
// Clock & Reset
// ----------------------
input clk,
input reset
);
localparam PAYLOAD_W = 112 + 2 + 2;
localparam NUM_INPUTS = 2;
localparam SHARE_COUNTER_W = 1;
localparam PIPELINE_ARB = 1;
localparam ST_DATA_W = 112;
localparam ST_CHANNEL_W = 2;
localparam PKT_TRANS_LOCK = 61;
// ------------------------------------------
// Signals
// ------------------------------------------
wire [NUM_INPUTS - 1 : 0] request;
wire [NUM_INPUTS - 1 : 0] valid;
wire [NUM_INPUTS - 1 : 0] grant;
wire [NUM_INPUTS - 1 : 0] next_grant;
reg [NUM_INPUTS - 1 : 0] saved_grant;
reg [PAYLOAD_W - 1 : 0] src_payload;
wire last_cycle;
reg packet_in_progress;
reg update_grant;
wire [PAYLOAD_W - 1 : 0] sink0_payload;
wire [PAYLOAD_W - 1 : 0] sink1_payload;
assign valid[0] = sink0_valid;
assign valid[1] = sink1_valid;
wire [NUM_INPUTS - 1 : 0] eop;
assign eop[0] = sink0_endofpacket;
assign eop[1] = sink1_endofpacket;
// ------------------------------------------
// ------------------------------------------
// Grant Logic & Updates
// ------------------------------------------
// ------------------------------------------
reg [NUM_INPUTS - 1 : 0] lock;
always @* begin
lock[0] = sink0_data[61];
lock[1] = sink1_data[61];
end
reg [NUM_INPUTS - 1 : 0] locked = '0;
always @(posedge clk or posedge reset) begin
if (reset) begin
locked <= '0;
end
else begin
locked <= next_grant & lock;
end
end
assign last_cycle = src_valid & src_ready & src_endofpacket & ~(|(lock & grant));
// ------------------------------------------
// We're working on a packet at any time valid is high, except
// when this is the endofpacket.
// ------------------------------------------
always @(posedge clk or posedge reset) begin
if (reset) begin
packet_in_progress <= 1'b0;
end
else begin
if (last_cycle)
packet_in_progress <= 1'b0;
else if (src_valid)
packet_in_progress <= 1'b1;
end
end
// ------------------------------------------
// Shares
//
// Special case: all-equal shares _should_ be optimized into assigning a
// constant to next_grant_share.
// Special case: all-1's shares _should_ result in the share counter
// being optimized away.
// ------------------------------------------
// Input | arb shares | counter load value
// 0 | 1 | 0
// 1 | 1 | 0
wire [SHARE_COUNTER_W - 1 : 0] share_0 = 1'd0;
wire [SHARE_COUNTER_W - 1 : 0] share_1 = 1'd0;
// ------------------------------------------
// Choose the share value corresponding to the grant.
// ------------------------------------------
reg [SHARE_COUNTER_W - 1 : 0] next_grant_share;
always @* begin
next_grant_share =
share_0 & { SHARE_COUNTER_W {next_grant[0]} } |
share_1 & { SHARE_COUNTER_W {next_grant[1]} };
end
// ------------------------------------------
// Flag to indicate first packet of an arb sequence.
// ------------------------------------------
// ------------------------------------------
// Compute the next share-count value.
// ------------------------------------------
reg [SHARE_COUNTER_W - 1 : 0] p1_share_count;
reg [SHARE_COUNTER_W - 1 : 0] share_count;
reg share_count_zero_flag;
always @* begin
// Update the counter, but don't decrement below 0.
p1_share_count = share_count_zero_flag ? '0 : share_count - 1'b1;
end
// ------------------------------------------
// Update the share counter and share-counter=zero flag.
// ------------------------------------------
always @(posedge clk or posedge reset) begin
if (reset) begin
share_count <= '0;
share_count_zero_flag <= 1'b1;
end
else begin
if (update_grant) begin
share_count <= next_grant_share;
share_count_zero_flag <= (next_grant_share == '0);
end
else if (last_cycle) begin
share_count <= p1_share_count;
share_count_zero_flag <= (p1_share_count == '0);
end
end
end
always @* begin
update_grant = 0;
// ------------------------------------------
// The pipeline delays grant by one cycle, so
// we have to calculate the update_grant signal
// one cycle ahead of time.
//
// Possible optimization: omit the first clause
// "if (!packet_in_progress & ~src_valid) ..."
// cost: one idle cycle at the the beginning of each
// grant cycle.
// benefit: save a small amount of logic.
// ------------------------------------------
if (!packet_in_progress & !src_valid)
update_grant = 1;
if (last_cycle && share_count_zero_flag)
update_grant = 1;
end
wire save_grant;
assign save_grant = update_grant;
assign grant = saved_grant;
always @(posedge clk, posedge reset) begin
if (reset)
saved_grant <= '0;
else if (save_grant)
saved_grant <= next_grant;
end
// ------------------------------------------
// ------------------------------------------
// Arbitrator
// ------------------------------------------
// ------------------------------------------
// ------------------------------------------
// Create a request vector that stays high during
// the packet for unpipelined arbitration.
//
// The pipelined arbitration scheme does not require
// request to be held high during the packet.
// ------------------------------------------
reg [NUM_INPUTS - 1 : 0] prev_request;
always @(posedge clk, posedge reset) begin
if (reset)
prev_request <= '0;
else
prev_request <= request & ~(valid & eop);
end
assign request = (PIPELINE_ARB == 1) ? valid | locked :
prev_request | valid | locked;
wire [NUM_INPUTS - 1 : 0] next_grant_from_arb;
altera_merlin_arbitrator
#(
.NUM_REQUESTERS(NUM_INPUTS),
.SCHEME ("round-robin"),
.PIPELINE (1)
) arb (
.clk (clk),
.reset (reset),
.request (request),
.grant (next_grant_from_arb),
.save_top_priority (src_valid),
.increment_top_priority (update_grant)
);
assign next_grant = next_grant_from_arb;
// ------------------------------------------
// ------------------------------------------
// Mux
//
// Implemented as a sum of products.
// ------------------------------------------
// ------------------------------------------
assign sink0_ready = src_ready && grant[0];
assign sink1_ready = src_ready && grant[1];
assign src_valid = |(grant & valid);
always @* begin
src_payload =
sink0_payload & {PAYLOAD_W {grant[0]} } |
sink1_payload & {PAYLOAD_W {grant[1]} };
end
// ------------------------------------------
// Mux Payload Mapping
// ------------------------------------------
assign sink0_payload = {sink0_channel,sink0_data,
sink0_startofpacket,sink0_endofpacket};
assign sink1_payload = {sink1_channel,sink1_data,
sink1_startofpacket,sink1_endofpacket};
assign {src_channel,src_data,src_startofpacket,src_endofpacket} = src_payload;
endmodule
|
module soc_system_mm_interconnect_2_rsp_demux
(
// -------------------
// Sink
// -------------------
input [1-1 : 0] sink_valid,
input [118-1 : 0] sink_data, // ST_DATA_W=118
input [2-1 : 0] sink_channel, // ST_CHANNEL_W=2
input sink_startofpacket,
input sink_endofpacket,
output sink_ready,
// -------------------
// Sources
// -------------------
output reg src0_valid,
output reg [118-1 : 0] src0_data, // ST_DATA_W=118
output reg [2-1 : 0] src0_channel, // ST_CHANNEL_W=2
output reg src0_startofpacket,
output reg src0_endofpacket,
input src0_ready,
// -------------------
// Clock & Reset
// -------------------
(*altera_attribute = "-name MESSAGE_DISABLE 15610" *) // setting message suppression on clk
input clk,
(*altera_attribute = "-name MESSAGE_DISABLE 15610" *) // setting message suppression on reset
input reset
);
localparam NUM_OUTPUTS = 1;
wire [NUM_OUTPUTS - 1 : 0] ready_vector;
// -------------------
// Demux
// -------------------
always @* begin
src0_data = sink_data;
src0_startofpacket = sink_startofpacket;
src0_endofpacket = sink_endofpacket;
src0_channel = sink_channel >> NUM_OUTPUTS;
src0_valid = sink_channel[0] && sink_valid;
end
// -------------------
// Backpressure
// -------------------
assign ready_vector[0] = src0_ready;
assign sink_ready = |(sink_channel & {{1{1'b0}},{ready_vector[NUM_OUTPUTS - 1 : 0]}});
endmodule
|
module soc_system_mm_interconnect_0_router_005_default_decode
#(
parameter DEFAULT_CHANNEL = -1,
DEFAULT_WR_CHANNEL = 0,
DEFAULT_RD_CHANNEL = 1,
DEFAULT_DESTID = 1
)
(output [140 - 138 : 0] default_destination_id,
output [7-1 : 0] default_wr_channel,
output [7-1 : 0] default_rd_channel,
output [7-1 : 0] default_src_channel
);
assign default_destination_id =
DEFAULT_DESTID[140 - 138 : 0];
generate
if (DEFAULT_CHANNEL == -1) begin : no_default_channel_assignment
assign default_src_channel = '0;
end
else begin : default_channel_assignment
assign default_src_channel = 7'b1 << DEFAULT_CHANNEL;
end
endgenerate
generate
if (DEFAULT_RD_CHANNEL == -1) begin : no_default_rw_channel_assignment
assign default_wr_channel = '0;
assign default_rd_channel = '0;
end
else begin : default_rw_channel_assignment
assign default_wr_channel = 7'b1 << DEFAULT_WR_CHANNEL;
assign default_rd_channel = 7'b1 << DEFAULT_RD_CHANNEL;
end
endgenerate
endmodule
|
module soc_system_mm_interconnect_0_router_005
(
// -------------------
// Clock & Reset
// -------------------
input clk,
input reset,
// -------------------
// Command Sink (Input)
// -------------------
input sink_valid,
input [165-1 : 0] sink_data,
input sink_startofpacket,
input sink_endofpacket,
output sink_ready,
// -------------------
// Command Source (Output)
// -------------------
output src_valid,
output reg [165-1 : 0] src_data,
output reg [7-1 : 0] src_channel,
output src_startofpacket,
output src_endofpacket,
input src_ready
);
// -------------------------------------------------------
// Local parameters and variables
// -------------------------------------------------------
localparam PKT_ADDR_H = 103;
localparam PKT_ADDR_L = 72;
localparam PKT_DEST_ID_H = 140;
localparam PKT_DEST_ID_L = 138;
localparam PKT_PROTECTION_H = 155;
localparam PKT_PROTECTION_L = 153;
localparam ST_DATA_W = 165;
localparam ST_CHANNEL_W = 7;
localparam DECODER_TYPE = 1;
localparam PKT_TRANS_WRITE = 106;
localparam PKT_TRANS_READ = 107;
localparam PKT_ADDR_W = PKT_ADDR_H-PKT_ADDR_L + 1;
localparam PKT_DEST_ID_W = PKT_DEST_ID_H-PKT_DEST_ID_L + 1;
// -------------------------------------------------------
// Figure out the number of bits to mask off for each slave span
// during address decoding
// -------------------------------------------------------
// -------------------------------------------------------
// Work out which address bits are significant based on the
// address range of the slaves. If the required width is too
// large or too small, we use the address field width instead.
// -------------------------------------------------------
localparam ADDR_RANGE = 64'h0;
localparam RANGE_ADDR_WIDTH = log2ceil(ADDR_RANGE);
localparam OPTIMIZED_ADDR_H = (RANGE_ADDR_WIDTH > PKT_ADDR_W) ||
(RANGE_ADDR_WIDTH == 0) ?
PKT_ADDR_H :
PKT_ADDR_L + RANGE_ADDR_WIDTH - 1;
localparam RG = RANGE_ADDR_WIDTH;
localparam REAL_ADDRESS_RANGE = OPTIMIZED_ADDR_H - PKT_ADDR_L;
reg [PKT_DEST_ID_W-1 : 0] destid;
// -------------------------------------------------------
// Pass almost everything through, untouched
// -------------------------------------------------------
assign sink_ready = src_ready;
assign src_valid = sink_valid;
assign src_startofpacket = sink_startofpacket;
assign src_endofpacket = sink_endofpacket;
wire [7-1 : 0] default_rd_channel;
wire [7-1 : 0] default_wr_channel;
// -------------------------------------------------------
// Write and read transaction signals
// -------------------------------------------------------
wire write_transaction;
assign write_transaction = sink_data[PKT_TRANS_WRITE];
wire read_transaction;
assign read_transaction = sink_data[PKT_TRANS_READ];
soc_system_mm_interconnect_0_router_005_default_decode the_default_decode(
.default_destination_id (),
.default_wr_channel (default_wr_channel),
.default_rd_channel (default_rd_channel),
.default_src_channel ()
);
always @* begin
src_data = sink_data;
src_channel = write_transaction ? default_wr_channel : default_rd_channel;
// --------------------------------------------------
// DestinationID Decoder
// Sets the channel based on the destination ID.
// --------------------------------------------------
destid = sink_data[PKT_DEST_ID_H : PKT_DEST_ID_L];
if (destid == 1 && write_transaction) begin
src_channel = 7'b001;
end
if (destid == 1 && read_transaction) begin
src_channel = 7'b010;
end
if (destid == 0 ) begin
src_channel = 7'b100;
end
end
// --------------------------------------------------
// Ceil(log2()) function
// --------------------------------------------------
function integer log2ceil;
input reg[65:0] val;
reg [65:0] i;
begin
i = 1;
log2ceil = 0;
while (i < val) begin
log2ceil = log2ceil + 1;
i = i << 1;
end
end
endfunction
endmodule
|
module soc_system_mm_interconnect_1_router_default_decode
#(
parameter DEFAULT_CHANNEL = 1,
DEFAULT_WR_CHANNEL = -1,
DEFAULT_RD_CHANNEL = -1,
DEFAULT_DESTID = 0
)
(output [94 - 91 : 0] default_destination_id,
output [14-1 : 0] default_wr_channel,
output [14-1 : 0] default_rd_channel,
output [14-1 : 0] default_src_channel
);
assign default_destination_id =
DEFAULT_DESTID[94 - 91 : 0];
generate
if (DEFAULT_CHANNEL == -1) begin : no_default_channel_assignment
assign default_src_channel = '0;
end
else begin : default_channel_assignment
assign default_src_channel = 14'b1 << DEFAULT_CHANNEL;
end
endgenerate
generate
if (DEFAULT_RD_CHANNEL == -1) begin : no_default_rw_channel_assignment
assign default_wr_channel = '0;
assign default_rd_channel = '0;
end
else begin : default_rw_channel_assignment
assign default_wr_channel = 14'b1 << DEFAULT_WR_CHANNEL;
assign default_rd_channel = 14'b1 << DEFAULT_RD_CHANNEL;
end
endgenerate
endmodule
|
module soc_system_mm_interconnect_1_router
(
// -------------------
// Clock & Reset
// -------------------
input clk,
input reset,
// -------------------
// Command Sink (Input)
// -------------------
input sink_valid,
input [108-1 : 0] sink_data,
input sink_startofpacket,
input sink_endofpacket,
output sink_ready,
// -------------------
// Command Source (Output)
// -------------------
output src_valid,
output reg [108-1 : 0] src_data,
output reg [14-1 : 0] src_channel,
output src_startofpacket,
output src_endofpacket,
input src_ready
);
// -------------------------------------------------------
// Local parameters and variables
// -------------------------------------------------------
localparam PKT_ADDR_H = 67;
localparam PKT_ADDR_L = 36;
localparam PKT_DEST_ID_H = 94;
localparam PKT_DEST_ID_L = 91;
localparam PKT_PROTECTION_H = 98;
localparam PKT_PROTECTION_L = 96;
localparam ST_DATA_W = 108;
localparam ST_CHANNEL_W = 14;
localparam DECODER_TYPE = 0;
localparam PKT_TRANS_WRITE = 70;
localparam PKT_TRANS_READ = 71;
localparam PKT_ADDR_W = PKT_ADDR_H-PKT_ADDR_L + 1;
localparam PKT_DEST_ID_W = PKT_DEST_ID_H-PKT_DEST_ID_L + 1;
// -------------------------------------------------------
// Figure out the number of bits to mask off for each slave span
// during address decoding
// -------------------------------------------------------
localparam PAD0 = log2ceil(64'h1008 - 64'h1000);
localparam PAD1 = log2ceil(64'h2008 - 64'h2000);
localparam PAD2 = log2ceil(64'h3010 - 64'h3000);
localparam PAD3 = log2ceil(64'h4010 - 64'h4000);
localparam PAD4 = log2ceil(64'h5010 - 64'h5000);
localparam PAD5 = log2ceil(64'h8010 - 64'h8000);
localparam PAD6 = log2ceil(64'h9010 - 64'h9000);
localparam PAD7 = log2ceil(64'ha010 - 64'ha000);
localparam PAD8 = log2ceil(64'hb010 - 64'hb000);
localparam PAD9 = log2ceil(64'hc010 - 64'hc000);
localparam PAD10 = log2ceil(64'hd010 - 64'hd000);
localparam PAD11 = log2ceil(64'he010 - 64'he000);
localparam PAD12 = log2ceil(64'hf010 - 64'hf000);
localparam PAD13 = log2ceil(64'h30100 - 64'h30000);
// -------------------------------------------------------
// Work out which address bits are significant based on the
// address range of the slaves. If the required width is too
// large or too small, we use the address field width instead.
// -------------------------------------------------------
localparam ADDR_RANGE = 64'h30100;
localparam RANGE_ADDR_WIDTH = log2ceil(ADDR_RANGE);
localparam OPTIMIZED_ADDR_H = (RANGE_ADDR_WIDTH > PKT_ADDR_W) ||
(RANGE_ADDR_WIDTH == 0) ?
PKT_ADDR_H :
PKT_ADDR_L + RANGE_ADDR_WIDTH - 1;
localparam RG = RANGE_ADDR_WIDTH-1;
localparam REAL_ADDRESS_RANGE = OPTIMIZED_ADDR_H - PKT_ADDR_L;
reg [PKT_ADDR_W-1 : 0] address;
always @* begin
address = {PKT_ADDR_W{1'b0}};
address [REAL_ADDRESS_RANGE:0] = sink_data[OPTIMIZED_ADDR_H : PKT_ADDR_L];
end
// -------------------------------------------------------
// Pass almost everything through, untouched
// -------------------------------------------------------
assign sink_ready = src_ready;
assign src_valid = sink_valid;
assign src_startofpacket = sink_startofpacket;
assign src_endofpacket = sink_endofpacket;
wire [PKT_DEST_ID_W-1:0] default_destid;
wire [14-1 : 0] default_src_channel;
// -------------------------------------------------------
// Write and read transaction signals
// -------------------------------------------------------
wire read_transaction;
assign read_transaction = sink_data[PKT_TRANS_READ];
soc_system_mm_interconnect_1_router_default_decode the_default_decode(
.default_destination_id (default_destid),
.default_wr_channel (),
.default_rd_channel (),
.default_src_channel (default_src_channel)
);
always @* begin
src_data = sink_data;
src_channel = default_src_channel;
src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = default_destid;
// --------------------------------------------------
// Address Decoder
// Sets the channel and destination ID based on the address
// --------------------------------------------------
// ( 0x1000 .. 0x1008 )
if ( {address[RG:PAD0],{PAD0{1'b0}}} == 18'h1000 && read_transaction ) begin
src_channel = 14'b00000000000100;
src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 13;
end
// ( 0x2000 .. 0x2008 )
if ( {address[RG:PAD1],{PAD1{1'b0}}} == 18'h2000 ) begin
src_channel = 14'b00000000000001;
src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 3;
end
// ( 0x3000 .. 0x3010 )
if ( {address[RG:PAD2],{PAD2{1'b0}}} == 18'h3000 ) begin
src_channel = 14'b00000000001000;
src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 4;
end
// ( 0x4000 .. 0x4010 )
if ( {address[RG:PAD3],{PAD3{1'b0}}} == 18'h4000 ) begin
src_channel = 14'b00000000010000;
src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 2;
end
// ( 0x5000 .. 0x5010 )
if ( {address[RG:PAD4],{PAD4{1'b0}}} == 18'h5000 ) begin
src_channel = 14'b00000000100000;
src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 1;
end
// ( 0x8000 .. 0x8010 )
if ( {address[RG:PAD5],{PAD5{1'b0}}} == 18'h8000 ) begin
src_channel = 14'b00000001000000;
src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 5;
end
// ( 0x9000 .. 0x9010 )
if ( {address[RG:PAD6],{PAD6{1'b0}}} == 18'h9000 ) begin
src_channel = 14'b00000010000000;
src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 6;
end
// ( 0xa000 .. 0xa010 )
if ( {address[RG:PAD7],{PAD7{1'b0}}} == 18'ha000 ) begin
src_channel = 14'b00000100000000;
src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 7;
end
// ( 0xb000 .. 0xb010 )
if ( {address[RG:PAD8],{PAD8{1'b0}}} == 18'hb000 ) begin
src_channel = 14'b00001000000000;
src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 8;
end
// ( 0xc000 .. 0xc010 )
if ( {address[RG:PAD9],{PAD9{1'b0}}} == 18'hc000 ) begin
src_channel = 14'b00010000000000;
src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 9;
end
// ( 0xd000 .. 0xd010 )
if ( {address[RG:PAD10],{PAD10{1'b0}}} == 18'hd000 ) begin
src_channel = 14'b00100000000000;
src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 10;
end
// ( 0xe000 .. 0xe010 )
if ( {address[RG:PAD11],{PAD11{1'b0}}} == 18'he000 ) begin
src_channel = 14'b01000000000000;
src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 11;
end
// ( 0xf000 .. 0xf010 )
if ( {address[RG:PAD12],{PAD12{1'b0}}} == 18'hf000 ) begin
src_channel = 14'b10000000000000;
src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 12;
end
// ( 0x30000 .. 0x30100 )
if ( {address[RG:PAD13],{PAD13{1'b0}}} == 18'h30000 ) begin
src_channel = 14'b00000000000010;
src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 0;
end
end
// --------------------------------------------------
// Ceil(log2()) function
// --------------------------------------------------
function integer log2ceil;
input reg[65:0] val;
reg [65:0] i;
begin
i = 1;
log2ceil = 0;
while (i < val) begin
log2ceil = log2ceil + 1;
i = i << 1;
end
end
endfunction
endmodule
|
module soc_system_mm_interconnect_1_rsp_demux
(
// -------------------
// Sink
// -------------------
input [1-1 : 0] sink_valid,
input [108-1 : 0] sink_data, // ST_DATA_W=108
input [14-1 : 0] sink_channel, // ST_CHANNEL_W=14
input sink_startofpacket,
input sink_endofpacket,
output sink_ready,
// -------------------
// Sources
// -------------------
output reg src0_valid,
output reg [108-1 : 0] src0_data, // ST_DATA_W=108
output reg [14-1 : 0] src0_channel, // ST_CHANNEL_W=14
output reg src0_startofpacket,
output reg src0_endofpacket,
input src0_ready,
output reg src1_valid,
output reg [108-1 : 0] src1_data, // ST_DATA_W=108
output reg [14-1 : 0] src1_channel, // ST_CHANNEL_W=14
output reg src1_startofpacket,
output reg src1_endofpacket,
input src1_ready,
// -------------------
// Clock & Reset
// -------------------
(*altera_attribute = "-name MESSAGE_DISABLE 15610" *) // setting message suppression on clk
input clk,
(*altera_attribute = "-name MESSAGE_DISABLE 15610" *) // setting message suppression on reset
input reset
);
localparam NUM_OUTPUTS = 2;
wire [NUM_OUTPUTS - 1 : 0] ready_vector;
// -------------------
// Demux
// -------------------
always @* begin
src0_data = sink_data;
src0_startofpacket = sink_startofpacket;
src0_endofpacket = sink_endofpacket;
src0_channel = sink_channel >> NUM_OUTPUTS;
src0_valid = sink_channel[0] && sink_valid;
src1_data = sink_data;
src1_startofpacket = sink_startofpacket;
src1_endofpacket = sink_endofpacket;
src1_channel = sink_channel >> NUM_OUTPUTS;
src1_valid = sink_channel[1] && sink_valid;
end
// -------------------
// Backpressure
// -------------------
assign ready_vector[0] = src0_ready;
assign ready_vector[1] = src1_ready;
assign sink_ready = |(sink_channel & {{12{1'b0}},{ready_vector[NUM_OUTPUTS - 1 : 0]}});
endmodule
|
module soc_system_irq_mapper_001
(
// -------------------
// Clock & Reset
// -------------------
input clk,
input reset,
// -------------------
// IRQ Receivers
// -------------------
input receiver0_irq,
input receiver1_irq,
input receiver2_irq,
// -------------------
// Command Source (Output)
// -------------------
output reg [31 : 0] sender_irq
);
always @* begin
sender_irq = 0;
sender_irq[2] = receiver0_irq;
sender_irq[1] = receiver1_irq;
sender_irq[0] = receiver2_irq;
end
endmodule
|
module altera_mem_if_dll_cyclonev (
clk,
dll_pll_locked,
dll_delayctrl
);
parameter DLL_DELAY_CTRL_WIDTH = 0;
parameter DELAY_BUFFER_MODE = "";
parameter DELAY_CHAIN_LENGTH = 0;
parameter DLL_INPUT_FREQUENCY_PS_STR = "";
parameter DLL_OFFSET_CTRL_WIDTH = 0;
input clk; // DLL input clock
input dll_pll_locked;
output [DLL_DELAY_CTRL_WIDTH-1:0] dll_delayctrl;
wire wire_dll_wys_m_offsetdelayctrlclkout;
wire [DLL_DELAY_CTRL_WIDTH-1:0] wire_dll_wys_m_offsetdelayctrlout;
wire dll_aload;
assign dll_aload = ~dll_pll_locked;
cyclonev_dll dll_wys_m(
.clk(clk),
.aload(dll_aload),
.delayctrlout(dll_delayctrl),
.dqsupdate(),
.locked(),
.upndnout(),
.dftcore()
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.upndnin(1'b1),
.upndninclkena(1'b1)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
// synopsys translate_off
,
.dffin()
// synopsys translate_on
);
defparam dll_wys_m.input_frequency = DLL_INPUT_FREQUENCY_PS_STR;
defparam dll_wys_m.jitter_reduction = "true";
defparam dll_wys_m.static_delay_ctrl = DELAY_CHAIN_LENGTH;
defparam dll_wys_m.lpm_type = "cyclonev_dll";
endmodule
|
module soc_system_mm_interconnect_0_cmd_demux_003
(
// -------------------
// Sink
// -------------------
input [7-1 : 0] sink_valid,
input [129-1 : 0] sink_data, // ST_DATA_W=129
input [7-1 : 0] sink_channel, // ST_CHANNEL_W=7
input sink_startofpacket,
input sink_endofpacket,
output sink_ready,
// -------------------
// Sources
// -------------------
output reg src0_valid,
output reg [129-1 : 0] src0_data, // ST_DATA_W=129
output reg [7-1 : 0] src0_channel, // ST_CHANNEL_W=7
output reg src0_startofpacket,
output reg src0_endofpacket,
input src0_ready,
output reg src1_valid,
output reg [129-1 : 0] src1_data, // ST_DATA_W=129
output reg [7-1 : 0] src1_channel, // ST_CHANNEL_W=7
output reg src1_startofpacket,
output reg src1_endofpacket,
input src1_ready,
output reg src2_valid,
output reg [129-1 : 0] src2_data, // ST_DATA_W=129
output reg [7-1 : 0] src2_channel, // ST_CHANNEL_W=7
output reg src2_startofpacket,
output reg src2_endofpacket,
input src2_ready,
output reg src3_valid,
output reg [129-1 : 0] src3_data, // ST_DATA_W=129
output reg [7-1 : 0] src3_channel, // ST_CHANNEL_W=7
output reg src3_startofpacket,
output reg src3_endofpacket,
input src3_ready,
output reg src4_valid,
output reg [129-1 : 0] src4_data, // ST_DATA_W=129
output reg [7-1 : 0] src4_channel, // ST_CHANNEL_W=7
output reg src4_startofpacket,
output reg src4_endofpacket,
input src4_ready,
// -------------------
// Clock & Reset
// -------------------
(*altera_attribute = "-name MESSAGE_DISABLE 15610" *) // setting message suppression on clk
input clk,
(*altera_attribute = "-name MESSAGE_DISABLE 15610" *) // setting message suppression on reset
input reset
);
localparam NUM_OUTPUTS = 5;
wire [NUM_OUTPUTS - 1 : 0] ready_vector;
// -------------------
// Demux
// -------------------
always @* begin
src0_data = sink_data;
src0_startofpacket = sink_startofpacket;
src0_endofpacket = sink_endofpacket;
src0_channel = sink_channel >> NUM_OUTPUTS;
src0_valid = sink_channel[0] && sink_valid[0];
src1_data = sink_data;
src1_startofpacket = sink_startofpacket;
src1_endofpacket = sink_endofpacket;
src1_channel = sink_channel >> NUM_OUTPUTS;
src1_valid = sink_channel[1] && sink_valid[1];
src2_data = sink_data;
src2_startofpacket = sink_startofpacket;
src2_endofpacket = sink_endofpacket;
src2_channel = sink_channel >> NUM_OUTPUTS;
src2_valid = sink_channel[2] && sink_valid[2];
src3_data = sink_data;
src3_startofpacket = sink_startofpacket;
src3_endofpacket = sink_endofpacket;
src3_channel = sink_channel >> NUM_OUTPUTS;
src3_valid = sink_channel[3] && sink_valid[3];
src4_data = sink_data;
src4_startofpacket = sink_startofpacket;
src4_endofpacket = sink_endofpacket;
src4_channel = sink_channel >> NUM_OUTPUTS;
src4_valid = sink_channel[4] && sink_valid[4];
end
// -------------------
// Backpressure
// -------------------
assign ready_vector[0] = src0_ready;
assign ready_vector[1] = src1_ready;
assign ready_vector[2] = src2_ready;
assign ready_vector[3] = src3_ready;
assign ready_vector[4] = src4_ready;
assign sink_ready = |(sink_channel & {{2{1'b0}},{ready_vector[NUM_OUTPUTS - 1 : 0]}});
endmodule
|
module soc_system_mm_interconnect_0_cmd_mux_001
(
// ----------------------
// Sinks
// ----------------------
input sink0_valid,
input [129-1 : 0] sink0_data,
input [7-1: 0] sink0_channel,
input sink0_startofpacket,
input sink0_endofpacket,
output sink0_ready,
input sink1_valid,
input [129-1 : 0] sink1_data,
input [7-1: 0] sink1_channel,
input sink1_startofpacket,
input sink1_endofpacket,
output sink1_ready,
input sink2_valid,
input [129-1 : 0] sink2_data,
input [7-1: 0] sink2_channel,
input sink2_startofpacket,
input sink2_endofpacket,
output sink2_ready,
// ----------------------
// Source
// ----------------------
output src_valid,
output [129-1 : 0] src_data,
output [7-1 : 0] src_channel,
output src_startofpacket,
output src_endofpacket,
input src_ready,
// ----------------------
// Clock & Reset
// ----------------------
input clk,
input reset
);
localparam PAYLOAD_W = 129 + 7 + 2;
localparam NUM_INPUTS = 3;
localparam SHARE_COUNTER_W = 1;
localparam PIPELINE_ARB = 1;
localparam ST_DATA_W = 129;
localparam ST_CHANNEL_W = 7;
localparam PKT_TRANS_LOCK = 72;
// ------------------------------------------
// Signals
// ------------------------------------------
wire [NUM_INPUTS - 1 : 0] request;
wire [NUM_INPUTS - 1 : 0] valid;
wire [NUM_INPUTS - 1 : 0] grant;
wire [NUM_INPUTS - 1 : 0] next_grant;
reg [NUM_INPUTS - 1 : 0] saved_grant;
reg [PAYLOAD_W - 1 : 0] src_payload;
wire last_cycle;
reg packet_in_progress;
reg update_grant;
wire [PAYLOAD_W - 1 : 0] sink0_payload;
wire [PAYLOAD_W - 1 : 0] sink1_payload;
wire [PAYLOAD_W - 1 : 0] sink2_payload;
assign valid[0] = sink0_valid;
assign valid[1] = sink1_valid;
assign valid[2] = sink2_valid;
wire [NUM_INPUTS - 1 : 0] eop;
assign eop[0] = sink0_endofpacket;
assign eop[1] = sink1_endofpacket;
assign eop[2] = sink2_endofpacket;
// ------------------------------------------
// ------------------------------------------
// Grant Logic & Updates
// ------------------------------------------
// ------------------------------------------
reg [NUM_INPUTS - 1 : 0] lock;
always @* begin
lock[0] = sink0_data[72];
lock[1] = sink1_data[72];
lock[2] = sink2_data[72];
end
reg [NUM_INPUTS - 1 : 0] locked = '0;
always @(posedge clk or posedge reset) begin
if (reset) begin
locked <= '0;
end
else begin
locked <= next_grant & lock;
end
end
assign last_cycle = src_valid & src_ready & src_endofpacket & ~(|(lock & grant));
// ------------------------------------------
// We're working on a packet at any time valid is high, except
// when this is the endofpacket.
// ------------------------------------------
always @(posedge clk or posedge reset) begin
if (reset) begin
packet_in_progress <= 1'b0;
end
else begin
if (last_cycle)
packet_in_progress <= 1'b0;
else if (src_valid)
packet_in_progress <= 1'b1;
end
end
// ------------------------------------------
// Shares
//
// Special case: all-equal shares _should_ be optimized into assigning a
// constant to next_grant_share.
// Special case: all-1's shares _should_ result in the share counter
// being optimized away.
// ------------------------------------------
// Input | arb shares | counter load value
// 0 | 1 | 0
// 1 | 1 | 0
// 2 | 1 | 0
wire [SHARE_COUNTER_W - 1 : 0] share_0 = 1'd0;
wire [SHARE_COUNTER_W - 1 : 0] share_1 = 1'd0;
wire [SHARE_COUNTER_W - 1 : 0] share_2 = 1'd0;
// ------------------------------------------
// Choose the share value corresponding to the grant.
// ------------------------------------------
reg [SHARE_COUNTER_W - 1 : 0] next_grant_share;
always @* begin
next_grant_share =
share_0 & { SHARE_COUNTER_W {next_grant[0]} } |
share_1 & { SHARE_COUNTER_W {next_grant[1]} } |
share_2 & { SHARE_COUNTER_W {next_grant[2]} };
end
// ------------------------------------------
// Flag to indicate first packet of an arb sequence.
// ------------------------------------------
// ------------------------------------------
// Compute the next share-count value.
// ------------------------------------------
reg [SHARE_COUNTER_W - 1 : 0] p1_share_count;
reg [SHARE_COUNTER_W - 1 : 0] share_count;
reg share_count_zero_flag;
always @* begin
// Update the counter, but don't decrement below 0.
p1_share_count = share_count_zero_flag ? '0 : share_count - 1'b1;
end
// ------------------------------------------
// Update the share counter and share-counter=zero flag.
// ------------------------------------------
always @(posedge clk or posedge reset) begin
if (reset) begin
share_count <= '0;
share_count_zero_flag <= 1'b1;
end
else begin
if (update_grant) begin
share_count <= next_grant_share;
share_count_zero_flag <= (next_grant_share == '0);
end
else if (last_cycle) begin
share_count <= p1_share_count;
share_count_zero_flag <= (p1_share_count == '0);
end
end
end
always @* begin
update_grant = 0;
// ------------------------------------------
// The pipeline delays grant by one cycle, so
// we have to calculate the update_grant signal
// one cycle ahead of time.
//
// Possible optimization: omit the first clause
// "if (!packet_in_progress & ~src_valid) ..."
// cost: one idle cycle at the the beginning of each
// grant cycle.
// benefit: save a small amount of logic.
// ------------------------------------------
if (!packet_in_progress & !src_valid)
update_grant = 1;
if (last_cycle && share_count_zero_flag)
update_grant = 1;
end
wire save_grant;
assign save_grant = update_grant;
assign grant = saved_grant;
always @(posedge clk, posedge reset) begin
if (reset)
saved_grant <= '0;
else if (save_grant)
saved_grant <= next_grant;
end
// ------------------------------------------
// ------------------------------------------
// Arbitrator
// ------------------------------------------
// ------------------------------------------
// ------------------------------------------
// Create a request vector that stays high during
// the packet for unpipelined arbitration.
//
// The pipelined arbitration scheme does not require
// request to be held high during the packet.
// ------------------------------------------
reg [NUM_INPUTS - 1 : 0] prev_request;
always @(posedge clk, posedge reset) begin
if (reset)
prev_request <= '0;
else
prev_request <= request & ~(valid & eop);
end
assign request = (PIPELINE_ARB == 1) ? valid | locked :
prev_request | valid | locked;
wire [NUM_INPUTS - 1 : 0] next_grant_from_arb;
altera_merlin_arbitrator
#(
.NUM_REQUESTERS(NUM_INPUTS),
.SCHEME ("round-robin"),
.PIPELINE (1)
) arb (
.clk (clk),
.reset (reset),
.request (request),
.grant (next_grant_from_arb),
.save_top_priority (src_valid),
.increment_top_priority (update_grant)
);
assign next_grant = next_grant_from_arb;
// ------------------------------------------
// ------------------------------------------
// Mux
//
// Implemented as a sum of products.
// ------------------------------------------
// ------------------------------------------
assign sink0_ready = src_ready && grant[0];
assign sink1_ready = src_ready && grant[1];
assign sink2_ready = src_ready && grant[2];
assign src_valid = |(grant & valid);
always @* begin
src_payload =
sink0_payload & {PAYLOAD_W {grant[0]} } |
sink1_payload & {PAYLOAD_W {grant[1]} } |
sink2_payload & {PAYLOAD_W {grant[2]} };
end
// ------------------------------------------
// Mux Payload Mapping
// ------------------------------------------
assign sink0_payload = {sink0_channel,sink0_data,
sink0_startofpacket,sink0_endofpacket};
assign sink1_payload = {sink1_channel,sink1_data,
sink1_startofpacket,sink1_endofpacket};
assign sink2_payload = {sink2_channel,sink2_data,
sink2_startofpacket,sink2_endofpacket};
assign {src_channel,src_data,src_startofpacket,src_endofpacket} = src_payload;
endmodule
|
module soc_system_mm_interconnect_2_router_default_decode
#(
parameter DEFAULT_CHANNEL = -1,
DEFAULT_WR_CHANNEL = 0,
DEFAULT_RD_CHANNEL = 1,
DEFAULT_DESTID = 0
)
(output [104 - 104 : 0] default_destination_id,
output [2-1 : 0] default_wr_channel,
output [2-1 : 0] default_rd_channel,
output [2-1 : 0] default_src_channel
);
assign default_destination_id =
DEFAULT_DESTID[104 - 104 : 0];
generate
if (DEFAULT_CHANNEL == -1) begin : no_default_channel_assignment
assign default_src_channel = '0;
end
else begin : default_channel_assignment
assign default_src_channel = 2'b1 << DEFAULT_CHANNEL;
end
endgenerate
generate
if (DEFAULT_RD_CHANNEL == -1) begin : no_default_rw_channel_assignment
assign default_wr_channel = '0;
assign default_rd_channel = '0;
end
else begin : default_rw_channel_assignment
assign default_wr_channel = 2'b1 << DEFAULT_WR_CHANNEL;
assign default_rd_channel = 2'b1 << DEFAULT_RD_CHANNEL;
end
endgenerate
endmodule
|
module soc_system_mm_interconnect_2_router
(
// -------------------
// Clock & Reset
// -------------------
input clk,
input reset,
// -------------------
// Command Sink (Input)
// -------------------
input sink_valid,
input [118-1 : 0] sink_data,
input sink_startofpacket,
input sink_endofpacket,
output sink_ready,
// -------------------
// Command Source (Output)
// -------------------
output src_valid,
output reg [118-1 : 0] src_data,
output reg [2-1 : 0] src_channel,
output src_startofpacket,
output src_endofpacket,
input src_ready
);
// -------------------------------------------------------
// Local parameters and variables
// -------------------------------------------------------
localparam PKT_ADDR_H = 67;
localparam PKT_ADDR_L = 36;
localparam PKT_DEST_ID_H = 104;
localparam PKT_DEST_ID_L = 104;
localparam PKT_PROTECTION_H = 108;
localparam PKT_PROTECTION_L = 106;
localparam ST_DATA_W = 118;
localparam ST_CHANNEL_W = 2;
localparam DECODER_TYPE = 0;
localparam PKT_TRANS_WRITE = 70;
localparam PKT_TRANS_READ = 71;
localparam PKT_ADDR_W = PKT_ADDR_H-PKT_ADDR_L + 1;
localparam PKT_DEST_ID_W = PKT_DEST_ID_H-PKT_DEST_ID_L + 1;
// -------------------------------------------------------
// Figure out the number of bits to mask off for each slave span
// during address decoding
// -------------------------------------------------------
localparam PAD0 = log2ceil(64'h100000000 - 64'h0);
localparam PAD1 = log2ceil(64'h100000000 - 64'h0);
// -------------------------------------------------------
// Work out which address bits are significant based on the
// address range of the slaves. If the required width is too
// large or too small, we use the address field width instead.
// -------------------------------------------------------
localparam ADDR_RANGE = 64'h100000000;
localparam RANGE_ADDR_WIDTH = log2ceil(ADDR_RANGE);
localparam OPTIMIZED_ADDR_H = (RANGE_ADDR_WIDTH > PKT_ADDR_W) ||
(RANGE_ADDR_WIDTH == 0) ?
PKT_ADDR_H :
PKT_ADDR_L + RANGE_ADDR_WIDTH - 1;
localparam RG = RANGE_ADDR_WIDTH;
localparam REAL_ADDRESS_RANGE = OPTIMIZED_ADDR_H - PKT_ADDR_L;
reg [PKT_ADDR_W-1 : 0] address;
always @* begin
address = {PKT_ADDR_W{1'b0}};
address [REAL_ADDRESS_RANGE:0] = sink_data[OPTIMIZED_ADDR_H : PKT_ADDR_L];
end
// -------------------------------------------------------
// Pass almost everything through, untouched
// -------------------------------------------------------
assign sink_ready = src_ready;
assign src_valid = sink_valid;
assign src_startofpacket = sink_startofpacket;
assign src_endofpacket = sink_endofpacket;
wire [PKT_DEST_ID_W-1:0] default_destid;
wire [2-1 : 0] default_rd_channel;
wire [2-1 : 0] default_wr_channel;
// -------------------------------------------------------
// Write and read transaction signals
// -------------------------------------------------------
wire write_transaction;
assign write_transaction = sink_data[PKT_TRANS_WRITE];
wire read_transaction;
assign read_transaction = sink_data[PKT_TRANS_READ];
soc_system_mm_interconnect_2_router_default_decode the_default_decode(
.default_destination_id (default_destid),
.default_wr_channel (default_wr_channel),
.default_rd_channel (default_rd_channel),
.default_src_channel ()
);
always @* begin
src_data = sink_data;
src_channel = write_transaction ? default_wr_channel : default_rd_channel;
src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = default_destid;
// --------------------------------------------------
// Address Decoder
// Sets the channel and destination ID based on the address
// --------------------------------------------------
if (write_transaction) begin
// ( 0 .. 100000000 )
src_channel = 2'b01;
src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 0;
end
if (read_transaction) begin
// ( 0 .. 100000000 )
src_channel = 2'b10;
src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 0;
end
end
// --------------------------------------------------
// Ceil(log2()) function
// --------------------------------------------------
function integer log2ceil;
input reg[65:0] val;
reg [65:0] i;
begin
i = 1;
log2ceil = 0;
while (i < val) begin
log2ceil = log2ceil + 1;
i = i << 1;
end
end
endfunction
endmodule
|
module soc_system_mm_interconnect_0_rsp_demux_002
(
// -------------------
// Sink
// -------------------
input [1-1 : 0] sink_valid,
input [129-1 : 0] sink_data, // ST_DATA_W=129
input [7-1 : 0] sink_channel, // ST_CHANNEL_W=7
input sink_startofpacket,
input sink_endofpacket,
output sink_ready,
// -------------------
// Sources
// -------------------
output reg src0_valid,
output reg [129-1 : 0] src0_data, // ST_DATA_W=129
output reg [7-1 : 0] src0_channel, // ST_CHANNEL_W=7
output reg src0_startofpacket,
output reg src0_endofpacket,
input src0_ready,
// -------------------
// Clock & Reset
// -------------------
(*altera_attribute = "-name MESSAGE_DISABLE 15610" *) // setting message suppression on clk
input clk,
(*altera_attribute = "-name MESSAGE_DISABLE 15610" *) // setting message suppression on reset
input reset
);
localparam NUM_OUTPUTS = 1;
wire [NUM_OUTPUTS - 1 : 0] ready_vector;
// -------------------
// Demux
// -------------------
always @* begin
src0_data = sink_data;
src0_startofpacket = sink_startofpacket;
src0_endofpacket = sink_endofpacket;
src0_channel = sink_channel >> NUM_OUTPUTS;
src0_valid = sink_channel[0] && sink_valid;
end
// -------------------
// Backpressure
// -------------------
assign ready_vector[0] = src0_ready;
assign sink_ready = |(sink_channel & {{6{1'b0}},{ready_vector[NUM_OUTPUTS - 1 : 0]}});
endmodule
|
module soc_system_mm_interconnect_0_router_007_default_decode
#(
parameter DEFAULT_CHANNEL = 0,
DEFAULT_WR_CHANNEL = -1,
DEFAULT_RD_CHANNEL = -1,
DEFAULT_DESTID = 0
)
(output [104 - 102 : 0] default_destination_id,
output [7-1 : 0] default_wr_channel,
output [7-1 : 0] default_rd_channel,
output [7-1 : 0] default_src_channel
);
assign default_destination_id =
DEFAULT_DESTID[104 - 102 : 0];
generate
if (DEFAULT_CHANNEL == -1) begin : no_default_channel_assignment
assign default_src_channel = '0;
end
else begin : default_channel_assignment
assign default_src_channel = 7'b1 << DEFAULT_CHANNEL;
end
endgenerate
generate
if (DEFAULT_RD_CHANNEL == -1) begin : no_default_rw_channel_assignment
assign default_wr_channel = '0;
assign default_rd_channel = '0;
end
else begin : default_rw_channel_assignment
assign default_wr_channel = 7'b1 << DEFAULT_WR_CHANNEL;
assign default_rd_channel = 7'b1 << DEFAULT_RD_CHANNEL;
end
endgenerate
endmodule
|
module soc_system_mm_interconnect_0_router_007
(
// -------------------
// Clock & Reset
// -------------------
input clk,
input reset,
// -------------------
// Command Sink (Input)
// -------------------
input sink_valid,
input [129-1 : 0] sink_data,
input sink_startofpacket,
input sink_endofpacket,
output sink_ready,
// -------------------
// Command Source (Output)
// -------------------
output src_valid,
output reg [129-1 : 0] src_data,
output reg [7-1 : 0] src_channel,
output src_startofpacket,
output src_endofpacket,
input src_ready
);
// -------------------------------------------------------
// Local parameters and variables
// -------------------------------------------------------
localparam PKT_ADDR_H = 67;
localparam PKT_ADDR_L = 36;
localparam PKT_DEST_ID_H = 104;
localparam PKT_DEST_ID_L = 102;
localparam PKT_PROTECTION_H = 119;
localparam PKT_PROTECTION_L = 117;
localparam ST_DATA_W = 129;
localparam ST_CHANNEL_W = 7;
localparam DECODER_TYPE = 1;
localparam PKT_TRANS_WRITE = 70;
localparam PKT_TRANS_READ = 71;
localparam PKT_ADDR_W = PKT_ADDR_H-PKT_ADDR_L + 1;
localparam PKT_DEST_ID_W = PKT_DEST_ID_H-PKT_DEST_ID_L + 1;
// -------------------------------------------------------
// Figure out the number of bits to mask off for each slave span
// during address decoding
// -------------------------------------------------------
// -------------------------------------------------------
// Work out which address bits are significant based on the
// address range of the slaves. If the required width is too
// large or too small, we use the address field width instead.
// -------------------------------------------------------
localparam ADDR_RANGE = 64'h0;
localparam RANGE_ADDR_WIDTH = log2ceil(ADDR_RANGE);
localparam OPTIMIZED_ADDR_H = (RANGE_ADDR_WIDTH > PKT_ADDR_W) ||
(RANGE_ADDR_WIDTH == 0) ?
PKT_ADDR_H :
PKT_ADDR_L + RANGE_ADDR_WIDTH - 1;
localparam RG = RANGE_ADDR_WIDTH;
localparam REAL_ADDRESS_RANGE = OPTIMIZED_ADDR_H - PKT_ADDR_L;
reg [PKT_DEST_ID_W-1 : 0] destid;
// -------------------------------------------------------
// Pass almost everything through, untouched
// -------------------------------------------------------
assign sink_ready = src_ready;
assign src_valid = sink_valid;
assign src_startofpacket = sink_startofpacket;
assign src_endofpacket = sink_endofpacket;
wire [7-1 : 0] default_src_channel;
soc_system_mm_interconnect_0_router_007_default_decode the_default_decode(
.default_destination_id (),
.default_wr_channel (),
.default_rd_channel (),
.default_src_channel (default_src_channel)
);
always @* begin
src_data = sink_data;
src_channel = default_src_channel;
// --------------------------------------------------
// DestinationID Decoder
// Sets the channel based on the destination ID.
// --------------------------------------------------
destid = sink_data[PKT_DEST_ID_H : PKT_DEST_ID_L];
if (destid == 0 ) begin
src_channel = 7'b1;
end
end
// --------------------------------------------------
// Ceil(log2()) function
// --------------------------------------------------
function integer log2ceil;
input reg[65:0] val;
reg [65:0] i;
begin
i = 1;
log2ceil = 0;
while (i < val) begin
log2ceil = log2ceil + 1;
i = i << 1;
end
end
endfunction
endmodule
|
module soc_system_mm_interconnect_3_router_001_default_decode
#(
parameter DEFAULT_CHANNEL = 0,
DEFAULT_WR_CHANNEL = -1,
DEFAULT_RD_CHANNEL = -1,
DEFAULT_DESTID = 0
)
(output [140 - 140 : 0] default_destination_id,
output [2-1 : 0] default_wr_channel,
output [2-1 : 0] default_rd_channel,
output [2-1 : 0] default_src_channel
);
assign default_destination_id =
DEFAULT_DESTID[140 - 140 : 0];
generate
if (DEFAULT_CHANNEL == -1) begin : no_default_channel_assignment
assign default_src_channel = '0;
end
else begin : default_channel_assignment
assign default_src_channel = 2'b1 << DEFAULT_CHANNEL;
end
endgenerate
generate
if (DEFAULT_RD_CHANNEL == -1) begin : no_default_rw_channel_assignment
assign default_wr_channel = '0;
assign default_rd_channel = '0;
end
else begin : default_rw_channel_assignment
assign default_wr_channel = 2'b1 << DEFAULT_WR_CHANNEL;
assign default_rd_channel = 2'b1 << DEFAULT_RD_CHANNEL;
end
endgenerate
endmodule
|
module soc_system_mm_interconnect_3_router_001
(
// -------------------
// Clock & Reset
// -------------------
input clk,
input reset,
// -------------------
// Command Sink (Input)
// -------------------
input sink_valid,
input [154-1 : 0] sink_data,
input sink_startofpacket,
input sink_endofpacket,
output sink_ready,
// -------------------
// Command Source (Output)
// -------------------
output src_valid,
output reg [154-1 : 0] src_data,
output reg [2-1 : 0] src_channel,
output src_startofpacket,
output src_endofpacket,
input src_ready
);
// -------------------------------------------------------
// Local parameters and variables
// -------------------------------------------------------
localparam PKT_ADDR_H = 103;
localparam PKT_ADDR_L = 72;
localparam PKT_DEST_ID_H = 140;
localparam PKT_DEST_ID_L = 140;
localparam PKT_PROTECTION_H = 144;
localparam PKT_PROTECTION_L = 142;
localparam ST_DATA_W = 154;
localparam ST_CHANNEL_W = 2;
localparam DECODER_TYPE = 1;
localparam PKT_TRANS_WRITE = 106;
localparam PKT_TRANS_READ = 107;
localparam PKT_ADDR_W = PKT_ADDR_H-PKT_ADDR_L + 1;
localparam PKT_DEST_ID_W = PKT_DEST_ID_H-PKT_DEST_ID_L + 1;
// -------------------------------------------------------
// Figure out the number of bits to mask off for each slave span
// during address decoding
// -------------------------------------------------------
// -------------------------------------------------------
// Work out which address bits are significant based on the
// address range of the slaves. If the required width is too
// large or too small, we use the address field width instead.
// -------------------------------------------------------
localparam ADDR_RANGE = 64'h0;
localparam RANGE_ADDR_WIDTH = log2ceil(ADDR_RANGE);
localparam OPTIMIZED_ADDR_H = (RANGE_ADDR_WIDTH > PKT_ADDR_W) ||
(RANGE_ADDR_WIDTH == 0) ?
PKT_ADDR_H :
PKT_ADDR_L + RANGE_ADDR_WIDTH - 1;
localparam RG = RANGE_ADDR_WIDTH;
localparam REAL_ADDRESS_RANGE = OPTIMIZED_ADDR_H - PKT_ADDR_L;
reg [PKT_DEST_ID_W-1 : 0] destid;
// -------------------------------------------------------
// Pass almost everything through, untouched
// -------------------------------------------------------
assign sink_ready = src_ready;
assign src_valid = sink_valid;
assign src_startofpacket = sink_startofpacket;
assign src_endofpacket = sink_endofpacket;
wire [2-1 : 0] default_src_channel;
soc_system_mm_interconnect_3_router_001_default_decode the_default_decode(
.default_destination_id (),
.default_wr_channel (),
.default_rd_channel (),
.default_src_channel (default_src_channel)
);
always @* begin
src_data = sink_data;
src_channel = default_src_channel;
// --------------------------------------------------
// DestinationID Decoder
// Sets the channel based on the destination ID.
// --------------------------------------------------
destid = sink_data[PKT_DEST_ID_H : PKT_DEST_ID_L];
if (destid == 0 ) begin
src_channel = 2'b1;
end
end
// --------------------------------------------------
// Ceil(log2()) function
// --------------------------------------------------
function integer log2ceil;
input reg[65:0] val;
reg [65:0] i;
begin
i = 1;
log2ceil = 0;
while (i < val) begin
log2ceil = log2ceil + 1;
i = i << 1;
end
end
endfunction
endmodule
|
module soc_system_mm_interconnect_0_rsp_demux_001
(
// -------------------
// Sink
// -------------------
input [1-1 : 0] sink_valid,
input [129-1 : 0] sink_data, // ST_DATA_W=129
input [7-1 : 0] sink_channel, // ST_CHANNEL_W=7
input sink_startofpacket,
input sink_endofpacket,
output sink_ready,
// -------------------
// Sources
// -------------------
output reg src0_valid,
output reg [129-1 : 0] src0_data, // ST_DATA_W=129
output reg [7-1 : 0] src0_channel, // ST_CHANNEL_W=7
output reg src0_startofpacket,
output reg src0_endofpacket,
input src0_ready,
output reg src1_valid,
output reg [129-1 : 0] src1_data, // ST_DATA_W=129
output reg [7-1 : 0] src1_channel, // ST_CHANNEL_W=7
output reg src1_startofpacket,
output reg src1_endofpacket,
input src1_ready,
output reg src2_valid,
output reg [129-1 : 0] src2_data, // ST_DATA_W=129
output reg [7-1 : 0] src2_channel, // ST_CHANNEL_W=7
output reg src2_startofpacket,
output reg src2_endofpacket,
input src2_ready,
// -------------------
// Clock & Reset
// -------------------
(*altera_attribute = "-name MESSAGE_DISABLE 15610" *) // setting message suppression on clk
input clk,
(*altera_attribute = "-name MESSAGE_DISABLE 15610" *) // setting message suppression on reset
input reset
);
localparam NUM_OUTPUTS = 3;
wire [NUM_OUTPUTS - 1 : 0] ready_vector;
// -------------------
// Demux
// -------------------
always @* begin
src0_data = sink_data;
src0_startofpacket = sink_startofpacket;
src0_endofpacket = sink_endofpacket;
src0_channel = sink_channel >> NUM_OUTPUTS;
src0_valid = sink_channel[0] && sink_valid;
src1_data = sink_data;
src1_startofpacket = sink_startofpacket;
src1_endofpacket = sink_endofpacket;
src1_channel = sink_channel >> NUM_OUTPUTS;
src1_valid = sink_channel[1] && sink_valid;
src2_data = sink_data;
src2_startofpacket = sink_startofpacket;
src2_endofpacket = sink_endofpacket;
src2_channel = sink_channel >> NUM_OUTPUTS;
src2_valid = sink_channel[2] && sink_valid;
end
// -------------------
// Backpressure
// -------------------
assign ready_vector[0] = src0_ready;
assign ready_vector[1] = src1_ready;
assign ready_vector[2] = src2_ready;
assign sink_ready = |(sink_channel & {{4{1'b0}},{ready_vector[NUM_OUTPUTS - 1 : 0]}});
endmodule
|
module soc_system_mm_interconnect_1_router_002_default_decode
#(
parameter DEFAULT_CHANNEL = 0,
DEFAULT_WR_CHANNEL = -1,
DEFAULT_RD_CHANNEL = -1,
DEFAULT_DESTID = 1
)
(output [94 - 91 : 0] default_destination_id,
output [14-1 : 0] default_wr_channel,
output [14-1 : 0] default_rd_channel,
output [14-1 : 0] default_src_channel
);
assign default_destination_id =
DEFAULT_DESTID[94 - 91 : 0];
generate
if (DEFAULT_CHANNEL == -1) begin : no_default_channel_assignment
assign default_src_channel = '0;
end
else begin : default_channel_assignment
assign default_src_channel = 14'b1 << DEFAULT_CHANNEL;
end
endgenerate
generate
if (DEFAULT_RD_CHANNEL == -1) begin : no_default_rw_channel_assignment
assign default_wr_channel = '0;
assign default_rd_channel = '0;
end
else begin : default_rw_channel_assignment
assign default_wr_channel = 14'b1 << DEFAULT_WR_CHANNEL;
assign default_rd_channel = 14'b1 << DEFAULT_RD_CHANNEL;
end
endgenerate
endmodule
|
module soc_system_mm_interconnect_1_router_002
(
// -------------------
// Clock & Reset
// -------------------
input clk,
input reset,
// -------------------
// Command Sink (Input)
// -------------------
input sink_valid,
input [108-1 : 0] sink_data,
input sink_startofpacket,
input sink_endofpacket,
output sink_ready,
// -------------------
// Command Source (Output)
// -------------------
output src_valid,
output reg [108-1 : 0] src_data,
output reg [14-1 : 0] src_channel,
output src_startofpacket,
output src_endofpacket,
input src_ready
);
// -------------------------------------------------------
// Local parameters and variables
// -------------------------------------------------------
localparam PKT_ADDR_H = 67;
localparam PKT_ADDR_L = 36;
localparam PKT_DEST_ID_H = 94;
localparam PKT_DEST_ID_L = 91;
localparam PKT_PROTECTION_H = 98;
localparam PKT_PROTECTION_L = 96;
localparam ST_DATA_W = 108;
localparam ST_CHANNEL_W = 14;
localparam DECODER_TYPE = 1;
localparam PKT_TRANS_WRITE = 70;
localparam PKT_TRANS_READ = 71;
localparam PKT_ADDR_W = PKT_ADDR_H-PKT_ADDR_L + 1;
localparam PKT_DEST_ID_W = PKT_DEST_ID_H-PKT_DEST_ID_L + 1;
// -------------------------------------------------------
// Figure out the number of bits to mask off for each slave span
// during address decoding
// -------------------------------------------------------
// -------------------------------------------------------
// Work out which address bits are significant based on the
// address range of the slaves. If the required width is too
// large or too small, we use the address field width instead.
// -------------------------------------------------------
localparam ADDR_RANGE = 64'h0;
localparam RANGE_ADDR_WIDTH = log2ceil(ADDR_RANGE);
localparam OPTIMIZED_ADDR_H = (RANGE_ADDR_WIDTH > PKT_ADDR_W) ||
(RANGE_ADDR_WIDTH == 0) ?
PKT_ADDR_H :
PKT_ADDR_L + RANGE_ADDR_WIDTH - 1;
localparam RG = RANGE_ADDR_WIDTH;
localparam REAL_ADDRESS_RANGE = OPTIMIZED_ADDR_H - PKT_ADDR_L;
reg [PKT_DEST_ID_W-1 : 0] destid;
// -------------------------------------------------------
// Pass almost everything through, untouched
// -------------------------------------------------------
assign sink_ready = src_ready;
assign src_valid = sink_valid;
assign src_startofpacket = sink_startofpacket;
assign src_endofpacket = sink_endofpacket;
wire [14-1 : 0] default_src_channel;
soc_system_mm_interconnect_1_router_002_default_decode the_default_decode(
.default_destination_id (),
.default_wr_channel (),
.default_rd_channel (),
.default_src_channel (default_src_channel)
);
always @* begin
src_data = sink_data;
src_channel = default_src_channel;
// --------------------------------------------------
// DestinationID Decoder
// Sets the channel based on the destination ID.
// --------------------------------------------------
destid = sink_data[PKT_DEST_ID_H : PKT_DEST_ID_L];
if (destid == 1 ) begin
src_channel = 14'b01;
end
if (destid == 0 ) begin
src_channel = 14'b10;
end
end
// --------------------------------------------------
// Ceil(log2()) function
// --------------------------------------------------
function integer log2ceil;
input reg[65:0] val;
reg [65:0] i;
begin
i = 1;
log2ceil = 0;
while (i < val) begin
log2ceil = log2ceil + 1;
i = i << 1;
end
end
endfunction
endmodule
|
module soc_system_mm_interconnect_3_router_default_decode
#(
parameter DEFAULT_CHANNEL = -1,
DEFAULT_WR_CHANNEL = 0,
DEFAULT_RD_CHANNEL = 1,
DEFAULT_DESTID = 0
)
(output [104 - 104 : 0] default_destination_id,
output [2-1 : 0] default_wr_channel,
output [2-1 : 0] default_rd_channel,
output [2-1 : 0] default_src_channel
);
assign default_destination_id =
DEFAULT_DESTID[104 - 104 : 0];
generate
if (DEFAULT_CHANNEL == -1) begin : no_default_channel_assignment
assign default_src_channel = '0;
end
else begin : default_channel_assignment
assign default_src_channel = 2'b1 << DEFAULT_CHANNEL;
end
endgenerate
generate
if (DEFAULT_RD_CHANNEL == -1) begin : no_default_rw_channel_assignment
assign default_wr_channel = '0;
assign default_rd_channel = '0;
end
else begin : default_rw_channel_assignment
assign default_wr_channel = 2'b1 << DEFAULT_WR_CHANNEL;
assign default_rd_channel = 2'b1 << DEFAULT_RD_CHANNEL;
end
endgenerate
endmodule
|
module soc_system_mm_interconnect_3_router
(
// -------------------
// Clock & Reset
// -------------------
input clk,
input reset,
// -------------------
// Command Sink (Input)
// -------------------
input sink_valid,
input [118-1 : 0] sink_data,
input sink_startofpacket,
input sink_endofpacket,
output sink_ready,
// -------------------
// Command Source (Output)
// -------------------
output src_valid,
output reg [118-1 : 0] src_data,
output reg [2-1 : 0] src_channel,
output src_startofpacket,
output src_endofpacket,
input src_ready
);
// -------------------------------------------------------
// Local parameters and variables
// -------------------------------------------------------
localparam PKT_ADDR_H = 67;
localparam PKT_ADDR_L = 36;
localparam PKT_DEST_ID_H = 104;
localparam PKT_DEST_ID_L = 104;
localparam PKT_PROTECTION_H = 108;
localparam PKT_PROTECTION_L = 106;
localparam ST_DATA_W = 118;
localparam ST_CHANNEL_W = 2;
localparam DECODER_TYPE = 0;
localparam PKT_TRANS_WRITE = 70;
localparam PKT_TRANS_READ = 71;
localparam PKT_ADDR_W = PKT_ADDR_H-PKT_ADDR_L + 1;
localparam PKT_DEST_ID_W = PKT_DEST_ID_H-PKT_DEST_ID_L + 1;
// -------------------------------------------------------
// Figure out the number of bits to mask off for each slave span
// during address decoding
// -------------------------------------------------------
localparam PAD0 = log2ceil(64'h100000000 - 64'h0);
localparam PAD1 = log2ceil(64'h100000000 - 64'h0);
// -------------------------------------------------------
// Work out which address bits are significant based on the
// address range of the slaves. If the required width is too
// large or too small, we use the address field width instead.
// -------------------------------------------------------
localparam ADDR_RANGE = 64'h100000000;
localparam RANGE_ADDR_WIDTH = log2ceil(ADDR_RANGE);
localparam OPTIMIZED_ADDR_H = (RANGE_ADDR_WIDTH > PKT_ADDR_W) ||
(RANGE_ADDR_WIDTH == 0) ?
PKT_ADDR_H :
PKT_ADDR_L + RANGE_ADDR_WIDTH - 1;
localparam RG = RANGE_ADDR_WIDTH;
localparam REAL_ADDRESS_RANGE = OPTIMIZED_ADDR_H - PKT_ADDR_L;
reg [PKT_ADDR_W-1 : 0] address;
always @* begin
address = {PKT_ADDR_W{1'b0}};
address [REAL_ADDRESS_RANGE:0] = sink_data[OPTIMIZED_ADDR_H : PKT_ADDR_L];
end
// -------------------------------------------------------
// Pass almost everything through, untouched
// -------------------------------------------------------
assign sink_ready = src_ready;
assign src_valid = sink_valid;
assign src_startofpacket = sink_startofpacket;
assign src_endofpacket = sink_endofpacket;
wire [PKT_DEST_ID_W-1:0] default_destid;
wire [2-1 : 0] default_rd_channel;
wire [2-1 : 0] default_wr_channel;
// -------------------------------------------------------
// Write and read transaction signals
// -------------------------------------------------------
wire write_transaction;
assign write_transaction = sink_data[PKT_TRANS_WRITE];
wire read_transaction;
assign read_transaction = sink_data[PKT_TRANS_READ];
soc_system_mm_interconnect_3_router_default_decode the_default_decode(
.default_destination_id (default_destid),
.default_wr_channel (default_wr_channel),
.default_rd_channel (default_rd_channel),
.default_src_channel ()
);
always @* begin
src_data = sink_data;
src_channel = write_transaction ? default_wr_channel : default_rd_channel;
src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = default_destid;
// --------------------------------------------------
// Address Decoder
// Sets the channel and destination ID based on the address
// --------------------------------------------------
if (write_transaction) begin
// ( 0 .. 100000000 )
src_channel = 2'b01;
src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 0;
end
if (read_transaction) begin
// ( 0 .. 100000000 )
src_channel = 2'b10;
src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 0;
end
end
// --------------------------------------------------
// Ceil(log2()) function
// --------------------------------------------------
function integer log2ceil;
input reg[65:0] val;
reg [65:0] i;
begin
i = 1;
log2ceil = 0;
while (i < val) begin
log2ceil = log2ceil + 1;
i = i << 1;
end
end
endfunction
endmodule
|
module soc_system_mm_interconnect_3_cmd_demux
(
// -------------------
// Sink
// -------------------
input [2-1 : 0] sink_valid,
input [118-1 : 0] sink_data, // ST_DATA_W=118
input [2-1 : 0] sink_channel, // ST_CHANNEL_W=2
input sink_startofpacket,
input sink_endofpacket,
output sink_ready,
// -------------------
// Sources
// -------------------
output reg src0_valid,
output reg [118-1 : 0] src0_data, // ST_DATA_W=118
output reg [2-1 : 0] src0_channel, // ST_CHANNEL_W=2
output reg src0_startofpacket,
output reg src0_endofpacket,
input src0_ready,
output reg src1_valid,
output reg [118-1 : 0] src1_data, // ST_DATA_W=118
output reg [2-1 : 0] src1_channel, // ST_CHANNEL_W=2
output reg src1_startofpacket,
output reg src1_endofpacket,
input src1_ready,
// -------------------
// Clock & Reset
// -------------------
(*altera_attribute = "-name MESSAGE_DISABLE 15610" *) // setting message suppression on clk
input clk,
(*altera_attribute = "-name MESSAGE_DISABLE 15610" *) // setting message suppression on reset
input reset
);
localparam NUM_OUTPUTS = 2;
wire [NUM_OUTPUTS - 1 : 0] ready_vector;
// -------------------
// Demux
// -------------------
always @* begin
src0_data = sink_data;
src0_startofpacket = sink_startofpacket;
src0_endofpacket = sink_endofpacket;
src0_channel = sink_channel >> NUM_OUTPUTS;
src0_valid = sink_channel[0] && sink_valid[0];
src1_data = sink_data;
src1_startofpacket = sink_startofpacket;
src1_endofpacket = sink_endofpacket;
src1_channel = sink_channel >> NUM_OUTPUTS;
src1_valid = sink_channel[1] && sink_valid[1];
end
// -------------------
// Backpressure
// -------------------
assign ready_vector[0] = src0_ready;
assign ready_vector[1] = src1_ready;
assign sink_ready = |(sink_channel & ready_vector);
endmodule
|
module hps_sdram_p0_phy_csr(
clk,
reset_n,
csr_addr,
csr_be,
csr_write_req,
csr_wdata,
csr_read_req,
csr_rdata,
csr_rdata_valid,
csr_waitrequest,
pll_locked,
afi_cal_success,
afi_cal_fail,
seq_fom_in,
seq_fom_out,
cal_init_failing_stage,
cal_init_failing_substage,
cal_init_failing_group
);
localparam RESET_REQUEST_DELAY = 4;
localparam CSR_IP_VERSION_NUMBER = 181;
parameter CSR_ADDR_WIDTH = 8;
parameter CSR_DATA_WIDTH = 32;
parameter CSR_BE_WIDTH = 4;
parameter MEM_READ_DQS_WIDTH = 64;
parameter MR1_RTT = 0;
parameter MR1_ODS = 0;
parameter MR2_RTT_WR = 0;
input clk;
input reset_n;
input [CSR_ADDR_WIDTH - 1 : 0] csr_addr;
input [CSR_BE_WIDTH - 1 : 0] csr_be;
input csr_write_req;
input [CSR_DATA_WIDTH - 1 : 0] csr_wdata;
input csr_read_req;
output [CSR_DATA_WIDTH - 1 : 0] csr_rdata;
output csr_rdata_valid;
output csr_waitrequest;
input pll_locked;
input afi_cal_success;
input afi_cal_fail;
input [7:0] seq_fom_in;
input [7:0] seq_fom_out;
input [7:0] cal_init_failing_stage;
input [7:0] cal_init_failing_substage;
input [7:0] cal_init_failing_group;
reg int_write_req;
reg int_read_req;
reg [CSR_ADDR_WIDTH-1:0] int_addr;
reg [CSR_BE_WIDTH - 1 : 0] int_be;
reg [CSR_DATA_WIDTH - 1 : 0] int_rdata;
reg int_rdata_valid;
reg int_waitrequest;
reg [CSR_DATA_WIDTH - 1 : 0] int_wdata;
reg [31:0] csr_register_0001;
reg [31:0] csr_register_0002;
reg [31:0] csr_register_0004;
reg [31:0] csr_register_0005;
reg [31:0] csr_register_0006;
reg [31:0] csr_register_0007;
reg [31:0] csr_register_0008;
always @ (posedge clk) begin
csr_register_0001 <= 0;
csr_register_0001 <= 32'hdeadbeef;
csr_register_0002 <= 0;
csr_register_0002 <= {CSR_IP_VERSION_NUMBER[15:0],16'h4};
csr_register_0004 <= 0;
csr_register_0004[24] <= afi_cal_success;
csr_register_0004[25] <= afi_cal_fail;
csr_register_0004[26] <= pll_locked;
csr_register_0005 <= 0;
csr_register_0005[7:0] <= seq_fom_in;
csr_register_0005[23:16] <= seq_fom_out;
csr_register_0006 <= 0;
csr_register_0006[7:0] <= cal_init_failing_stage;
csr_register_0006[15:8] <= cal_init_failing_substage;
csr_register_0006[23:16] <= cal_init_failing_group;
csr_register_0007 <= 0;
csr_register_0008 <= 0;
csr_register_0008[2:0] <= MR1_RTT[2:0] & 3'b111;
csr_register_0008[6:5] <= MR1_ODS[1:0] & 2'b11;
csr_register_0008[10:9] <= MR2_RTT_WR[1:0] & 2'b11;
end
always @ (posedge clk or negedge reset_n) begin
if (!reset_n) begin
int_write_req <= 0;
int_read_req <= 0;
int_addr <= 0;
int_wdata <= 0;
int_be <= 0;
end
else begin
int_addr <= csr_addr;
int_wdata <= csr_wdata;
int_be <= csr_be;
if (csr_write_req)
int_write_req <= 1'b1;
else
int_write_req <= 1'b0;
if (csr_read_req)
int_read_req <= 1'b1;
else
int_read_req <= 1'b0;
end
end
always @ (posedge clk or negedge reset_n) begin
if (!reset_n) begin
int_rdata <= 0;
int_rdata_valid <= 0;
int_waitrequest <= 1;
end
else begin
int_waitrequest <= 1'b0;
if (int_read_req)
case (int_addr)
'h1 :
int_rdata <= csr_register_0001;
'h2 :
int_rdata <= csr_register_0002;
'h4 :
int_rdata <= csr_register_0004;
'h5 :
int_rdata <= csr_register_0005;
'h6 :
int_rdata <= csr_register_0006;
'h7 :
int_rdata <= csr_register_0007;
'h8 :
int_rdata <= csr_register_0008;
default :
int_rdata <= 0;
endcase
if (int_read_req)
int_rdata_valid <= 1'b1;
else
int_rdata_valid <= 1'b0;
end
end
always @ (posedge clk or negedge reset_n) begin
if (!reset_n) begin
end
else begin
if (int_write_req) begin
end
end
end
`ifndef SYNTH_FOR_SIM
hps_sdram_p0_iss_probe pll_probe (
.probe_input(pll_locked)
);
`endif
assign csr_waitrequest = int_waitrequest;
assign csr_rdata = int_rdata;
assign csr_rdata_valid = int_rdata_valid;
endmodule
|
module soc_system_mm_interconnect_0_router_002_default_decode
#(
parameter DEFAULT_CHANNEL = -1,
DEFAULT_WR_CHANNEL = 0,
DEFAULT_RD_CHANNEL = 1,
DEFAULT_DESTID = 0
)
(output [87 - 87 : 0] default_destination_id,
output [2-1 : 0] default_wr_channel,
output [2-1 : 0] default_rd_channel,
output [2-1 : 0] default_src_channel
);
assign default_destination_id =
DEFAULT_DESTID[87 - 87 : 0];
generate
if (DEFAULT_CHANNEL == -1) begin : no_default_channel_assignment
assign default_src_channel = '0;
end
else begin : default_channel_assignment
assign default_src_channel = 2'b1 << DEFAULT_CHANNEL;
end
endgenerate
generate
if (DEFAULT_RD_CHANNEL == -1) begin : no_default_rw_channel_assignment
assign default_wr_channel = '0;
assign default_rd_channel = '0;
end
else begin : default_rw_channel_assignment
assign default_wr_channel = 2'b1 << DEFAULT_WR_CHANNEL;
assign default_rd_channel = 2'b1 << DEFAULT_RD_CHANNEL;
end
endgenerate
endmodule
|
module soc_system_mm_interconnect_0_router_002
(
// -------------------
// Clock & Reset
// -------------------
input clk,
input reset,
// -------------------
// Command Sink (Input)
// -------------------
input sink_valid,
input [112-1 : 0] sink_data,
input sink_startofpacket,
input sink_endofpacket,
output sink_ready,
// -------------------
// Command Source (Output)
// -------------------
output src_valid,
output reg [112-1 : 0] src_data,
output reg [2-1 : 0] src_channel,
output src_startofpacket,
output src_endofpacket,
input src_ready
);
// -------------------------------------------------------
// Local parameters and variables
// -------------------------------------------------------
localparam PKT_ADDR_H = 56;
localparam PKT_ADDR_L = 36;
localparam PKT_DEST_ID_H = 87;
localparam PKT_DEST_ID_L = 87;
localparam PKT_PROTECTION_H = 102;
localparam PKT_PROTECTION_L = 100;
localparam ST_DATA_W = 112;
localparam ST_CHANNEL_W = 2;
localparam DECODER_TYPE = 1;
localparam PKT_TRANS_WRITE = 59;
localparam PKT_TRANS_READ = 60;
localparam PKT_ADDR_W = PKT_ADDR_H-PKT_ADDR_L + 1;
localparam PKT_DEST_ID_W = PKT_DEST_ID_H-PKT_DEST_ID_L + 1;
// -------------------------------------------------------
// Figure out the number of bits to mask off for each slave span
// during address decoding
// -------------------------------------------------------
// -------------------------------------------------------
// Work out which address bits are significant based on the
// address range of the slaves. If the required width is too
// large or too small, we use the address field width instead.
// -------------------------------------------------------
localparam ADDR_RANGE = 64'h0;
localparam RANGE_ADDR_WIDTH = log2ceil(ADDR_RANGE);
localparam OPTIMIZED_ADDR_H = (RANGE_ADDR_WIDTH > PKT_ADDR_W) ||
(RANGE_ADDR_WIDTH == 0) ?
PKT_ADDR_H :
PKT_ADDR_L + RANGE_ADDR_WIDTH - 1;
localparam RG = RANGE_ADDR_WIDTH;
localparam REAL_ADDRESS_RANGE = OPTIMIZED_ADDR_H - PKT_ADDR_L;
reg [PKT_DEST_ID_W-1 : 0] destid;
// -------------------------------------------------------
// Pass almost everything through, untouched
// -------------------------------------------------------
assign sink_ready = src_ready;
assign src_valid = sink_valid;
assign src_startofpacket = sink_startofpacket;
assign src_endofpacket = sink_endofpacket;
wire [2-1 : 0] default_rd_channel;
wire [2-1 : 0] default_wr_channel;
// -------------------------------------------------------
// Write and read transaction signals
// -------------------------------------------------------
wire write_transaction;
assign write_transaction = sink_data[PKT_TRANS_WRITE];
wire read_transaction;
assign read_transaction = sink_data[PKT_TRANS_READ];
soc_system_mm_interconnect_0_router_002_default_decode the_default_decode(
.default_destination_id (),
.default_wr_channel (default_wr_channel),
.default_rd_channel (default_rd_channel),
.default_src_channel ()
);
always @* begin
src_data = sink_data;
src_channel = write_transaction ? default_wr_channel : default_rd_channel;
// --------------------------------------------------
// DestinationID Decoder
// Sets the channel based on the destination ID.
// --------------------------------------------------
destid = sink_data[PKT_DEST_ID_H : PKT_DEST_ID_L];
if (destid == 0 && write_transaction) begin
src_channel = 2'b01;
end
if (destid == 0 && read_transaction) begin
src_channel = 2'b10;
end
end
// --------------------------------------------------
// Ceil(log2()) function
// --------------------------------------------------
function integer log2ceil;
input reg[65:0] val;
reg [65:0] i;
begin
i = 1;
log2ceil = 0;
while (i < val) begin
log2ceil = log2ceil + 1;
i = i << 1;
end
end
endfunction
endmodule
|
module soc_system_mm_interconnect_0_cmd_mux_002
(
// ----------------------
// Sinks
// ----------------------
input sink0_valid,
input [129-1 : 0] sink0_data,
input [7-1: 0] sink0_channel,
input sink0_startofpacket,
input sink0_endofpacket,
output sink0_ready,
// ----------------------
// Source
// ----------------------
output src_valid,
output [129-1 : 0] src_data,
output [7-1 : 0] src_channel,
output src_startofpacket,
output src_endofpacket,
input src_ready,
// ----------------------
// Clock & Reset
// ----------------------
input clk,
input reset
);
localparam PAYLOAD_W = 129 + 7 + 2;
localparam NUM_INPUTS = 1;
localparam SHARE_COUNTER_W = 1;
localparam PIPELINE_ARB = 1;
localparam ST_DATA_W = 129;
localparam ST_CHANNEL_W = 7;
localparam PKT_TRANS_LOCK = 72;
assign src_valid = sink0_valid;
assign src_data = sink0_data;
assign src_channel = sink0_channel;
assign src_startofpacket = sink0_startofpacket;
assign src_endofpacket = sink0_endofpacket;
assign sink0_ready = src_ready;
endmodule
|
module soc_system_fpga_only_master_b2p_adapter
(
// Interface: in
output reg in_ready,
input in_valid,
input [8-1: 0] in_data,
input [8-1: 0] in_channel,
input in_startofpacket,
input in_endofpacket,
// Interface: out
input out_ready,
output reg out_valid,
output reg [8-1: 0] out_data,
output reg out_startofpacket,
output reg out_endofpacket,
// Interface: clk
input clk,
// Interface: reset
input reset_n
);
reg out_channel;
// ---------------------------------------------------------------------
//| Payload Mapping
// ---------------------------------------------------------------------
always @* begin
in_ready = out_ready;
out_valid = in_valid;
out_data = in_data;
out_startofpacket = in_startofpacket;
out_endofpacket = in_endofpacket;
out_channel = in_channel; //TODO delete this to avoid Quartus warnings
// Suppress channels that are higher than the destination's max_channel.
if (in_channel > 0) begin
out_valid = 0;
// Simulation Message goes here.
end
end
endmodule
|
module soc_system_fpga_only_master_p2b_adapter
(
// Interface: in
output reg in_ready,
input in_valid,
input [8-1: 0] in_data,
input in_startofpacket,
input in_endofpacket,
// Interface: out
input out_ready,
output reg out_valid,
output reg [8-1: 0] out_data,
output reg [8-1: 0] out_channel,
output reg out_startofpacket,
output reg out_endofpacket,
// Interface: clk
input clk,
// Interface: reset
input reset_n
);
reg in_channel = 0;
// ---------------------------------------------------------------------
//| Payload Mapping
// ---------------------------------------------------------------------
always @* begin
in_ready = out_ready;
out_valid = in_valid;
out_data = in_data;
out_startofpacket = in_startofpacket;
out_endofpacket = in_endofpacket;
out_channel = 0;
out_channel = in_channel;
end
endmodule
|
module soc_system_mm_interconnect_2_cmd_mux
(
// ----------------------
// Sinks
// ----------------------
input sink0_valid,
input [118-1 : 0] sink0_data,
input [2-1: 0] sink0_channel,
input sink0_startofpacket,
input sink0_endofpacket,
output sink0_ready,
// ----------------------
// Source
// ----------------------
output src_valid,
output [118-1 : 0] src_data,
output [2-1 : 0] src_channel,
output src_startofpacket,
output src_endofpacket,
input src_ready,
// ----------------------
// Clock & Reset
// ----------------------
input clk,
input reset
);
localparam PAYLOAD_W = 118 + 2 + 2;
localparam NUM_INPUTS = 1;
localparam SHARE_COUNTER_W = 1;
localparam PIPELINE_ARB = 1;
localparam ST_DATA_W = 118;
localparam ST_CHANNEL_W = 2;
localparam PKT_TRANS_LOCK = 72;
assign src_valid = sink0_valid;
assign src_data = sink0_data;
assign src_channel = sink0_channel;
assign src_startofpacket = sink0_startofpacket;
assign src_endofpacket = sink0_endofpacket;
assign sink0_ready = src_ready;
endmodule
|
module soc_system_mm_interconnect_1_cmd_demux
(
// -------------------
// Sink
// -------------------
input [14-1 : 0] sink_valid,
input [108-1 : 0] sink_data, // ST_DATA_W=108
input [14-1 : 0] sink_channel, // ST_CHANNEL_W=14
input sink_startofpacket,
input sink_endofpacket,
output sink_ready,
// -------------------
// Sources
// -------------------
output reg src0_valid,
output reg [108-1 : 0] src0_data, // ST_DATA_W=108
output reg [14-1 : 0] src0_channel, // ST_CHANNEL_W=14
output reg src0_startofpacket,
output reg src0_endofpacket,
input src0_ready,
output reg src1_valid,
output reg [108-1 : 0] src1_data, // ST_DATA_W=108
output reg [14-1 : 0] src1_channel, // ST_CHANNEL_W=14
output reg src1_startofpacket,
output reg src1_endofpacket,
input src1_ready,
output reg src2_valid,
output reg [108-1 : 0] src2_data, // ST_DATA_W=108
output reg [14-1 : 0] src2_channel, // ST_CHANNEL_W=14
output reg src2_startofpacket,
output reg src2_endofpacket,
input src2_ready,
output reg src3_valid,
output reg [108-1 : 0] src3_data, // ST_DATA_W=108
output reg [14-1 : 0] src3_channel, // ST_CHANNEL_W=14
output reg src3_startofpacket,
output reg src3_endofpacket,
input src3_ready,
output reg src4_valid,
output reg [108-1 : 0] src4_data, // ST_DATA_W=108
output reg [14-1 : 0] src4_channel, // ST_CHANNEL_W=14
output reg src4_startofpacket,
output reg src4_endofpacket,
input src4_ready,
output reg src5_valid,
output reg [108-1 : 0] src5_data, // ST_DATA_W=108
output reg [14-1 : 0] src5_channel, // ST_CHANNEL_W=14
output reg src5_startofpacket,
output reg src5_endofpacket,
input src5_ready,
output reg src6_valid,
output reg [108-1 : 0] src6_data, // ST_DATA_W=108
output reg [14-1 : 0] src6_channel, // ST_CHANNEL_W=14
output reg src6_startofpacket,
output reg src6_endofpacket,
input src6_ready,
output reg src7_valid,
output reg [108-1 : 0] src7_data, // ST_DATA_W=108
output reg [14-1 : 0] src7_channel, // ST_CHANNEL_W=14
output reg src7_startofpacket,
output reg src7_endofpacket,
input src7_ready,
output reg src8_valid,
output reg [108-1 : 0] src8_data, // ST_DATA_W=108
output reg [14-1 : 0] src8_channel, // ST_CHANNEL_W=14
output reg src8_startofpacket,
output reg src8_endofpacket,
input src8_ready,
output reg src9_valid,
output reg [108-1 : 0] src9_data, // ST_DATA_W=108
output reg [14-1 : 0] src9_channel, // ST_CHANNEL_W=14
output reg src9_startofpacket,
output reg src9_endofpacket,
input src9_ready,
output reg src10_valid,
output reg [108-1 : 0] src10_data, // ST_DATA_W=108
output reg [14-1 : 0] src10_channel, // ST_CHANNEL_W=14
output reg src10_startofpacket,
output reg src10_endofpacket,
input src10_ready,
output reg src11_valid,
output reg [108-1 : 0] src11_data, // ST_DATA_W=108
output reg [14-1 : 0] src11_channel, // ST_CHANNEL_W=14
output reg src11_startofpacket,
output reg src11_endofpacket,
input src11_ready,
output reg src12_valid,
output reg [108-1 : 0] src12_data, // ST_DATA_W=108
output reg [14-1 : 0] src12_channel, // ST_CHANNEL_W=14
output reg src12_startofpacket,
output reg src12_endofpacket,
input src12_ready,
output reg src13_valid,
output reg [108-1 : 0] src13_data, // ST_DATA_W=108
output reg [14-1 : 0] src13_channel, // ST_CHANNEL_W=14
output reg src13_startofpacket,
output reg src13_endofpacket,
input src13_ready,
// -------------------
// Clock & Reset
// -------------------
(*altera_attribute = "-name MESSAGE_DISABLE 15610" *) // setting message suppression on clk
input clk,
(*altera_attribute = "-name MESSAGE_DISABLE 15610" *) // setting message suppression on reset
input reset
);
localparam NUM_OUTPUTS = 14;
wire [NUM_OUTPUTS - 1 : 0] ready_vector;
// -------------------
// Demux
// -------------------
always @* begin
src0_data = sink_data;
src0_startofpacket = sink_startofpacket;
src0_endofpacket = sink_endofpacket;
src0_channel = sink_channel >> NUM_OUTPUTS;
src0_valid = sink_channel[0] && sink_valid[0];
src1_data = sink_data;
src1_startofpacket = sink_startofpacket;
src1_endofpacket = sink_endofpacket;
src1_channel = sink_channel >> NUM_OUTPUTS;
src1_valid = sink_channel[1] && sink_valid[1];
src2_data = sink_data;
src2_startofpacket = sink_startofpacket;
src2_endofpacket = sink_endofpacket;
src2_channel = sink_channel >> NUM_OUTPUTS;
src2_valid = sink_channel[2] && sink_valid[2];
src3_data = sink_data;
src3_startofpacket = sink_startofpacket;
src3_endofpacket = sink_endofpacket;
src3_channel = sink_channel >> NUM_OUTPUTS;
src3_valid = sink_channel[3] && sink_valid[3];
src4_data = sink_data;
src4_startofpacket = sink_startofpacket;
src4_endofpacket = sink_endofpacket;
src4_channel = sink_channel >> NUM_OUTPUTS;
src4_valid = sink_channel[4] && sink_valid[4];
src5_data = sink_data;
src5_startofpacket = sink_startofpacket;
src5_endofpacket = sink_endofpacket;
src5_channel = sink_channel >> NUM_OUTPUTS;
src5_valid = sink_channel[5] && sink_valid[5];
src6_data = sink_data;
src6_startofpacket = sink_startofpacket;
src6_endofpacket = sink_endofpacket;
src6_channel = sink_channel >> NUM_OUTPUTS;
src6_valid = sink_channel[6] && sink_valid[6];
src7_data = sink_data;
src7_startofpacket = sink_startofpacket;
src7_endofpacket = sink_endofpacket;
src7_channel = sink_channel >> NUM_OUTPUTS;
src7_valid = sink_channel[7] && sink_valid[7];
src8_data = sink_data;
src8_startofpacket = sink_startofpacket;
src8_endofpacket = sink_endofpacket;
src8_channel = sink_channel >> NUM_OUTPUTS;
src8_valid = sink_channel[8] && sink_valid[8];
src9_data = sink_data;
src9_startofpacket = sink_startofpacket;
src9_endofpacket = sink_endofpacket;
src9_channel = sink_channel >> NUM_OUTPUTS;
src9_valid = sink_channel[9] && sink_valid[9];
src10_data = sink_data;
src10_startofpacket = sink_startofpacket;
src10_endofpacket = sink_endofpacket;
src10_channel = sink_channel >> NUM_OUTPUTS;
src10_valid = sink_channel[10] && sink_valid[10];
src11_data = sink_data;
src11_startofpacket = sink_startofpacket;
src11_endofpacket = sink_endofpacket;
src11_channel = sink_channel >> NUM_OUTPUTS;
src11_valid = sink_channel[11] && sink_valid[11];
src12_data = sink_data;
src12_startofpacket = sink_startofpacket;
src12_endofpacket = sink_endofpacket;
src12_channel = sink_channel >> NUM_OUTPUTS;
src12_valid = sink_channel[12] && sink_valid[12];
src13_data = sink_data;
src13_startofpacket = sink_startofpacket;
src13_endofpacket = sink_endofpacket;
src13_channel = sink_channel >> NUM_OUTPUTS;
src13_valid = sink_channel[13] && sink_valid[13];
end
// -------------------
// Backpressure
// -------------------
assign ready_vector[0] = src0_ready;
assign ready_vector[1] = src1_ready;
assign ready_vector[2] = src2_ready;
assign ready_vector[3] = src3_ready;
assign ready_vector[4] = src4_ready;
assign ready_vector[5] = src5_ready;
assign ready_vector[6] = src6_ready;
assign ready_vector[7] = src7_ready;
assign ready_vector[8] = src8_ready;
assign ready_vector[9] = src9_ready;
assign ready_vector[10] = src10_ready;
assign ready_vector[11] = src11_ready;
assign ready_vector[12] = src12_ready;
assign ready_vector[13] = src13_ready;
assign sink_ready = |(sink_channel & ready_vector);
endmodule
|
module soc_system_f2sdram_only_master_p2b_adapter
(
// Interface: in
output reg in_ready,
input in_valid,
input [8-1: 0] in_data,
input in_startofpacket,
input in_endofpacket,
// Interface: out
input out_ready,
output reg out_valid,
output reg [8-1: 0] out_data,
output reg [8-1: 0] out_channel,
output reg out_startofpacket,
output reg out_endofpacket,
// Interface: clk
input clk,
// Interface: reset
input reset_n
);
reg in_channel = 0;
// ---------------------------------------------------------------------
//| Payload Mapping
// ---------------------------------------------------------------------
always @* begin
in_ready = out_ready;
out_valid = in_valid;
out_data = in_data;
out_startofpacket = in_startofpacket;
out_endofpacket = in_endofpacket;
out_channel = 0;
out_channel = in_channel;
end
endmodule
|
module altera_mem_if_oct_cyclonev (
oct_rzqin,
parallelterminationcontrol,
seriesterminationcontrol
);
parameter OCT_TERM_CONTROL_WIDTH = 0;
// These should be connected to reference resistance pins on the board, via OCT control block if instantiated by user
input oct_rzqin;
// for OCT master, termination control signals will be available to top level
output [OCT_TERM_CONTROL_WIDTH-1:0] parallelterminationcontrol;
output [OCT_TERM_CONTROL_WIDTH-1:0] seriesterminationcontrol;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 oct_rzqin;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [0:0] wire_sd1a_serdataout;
cyclonev_termination sd1a_0
(
.clkusrdftout(),
.compoutrdn(),
.compoutrup(),
.enserout(),
.rzqin(oct_rzqin),
.scanout(),
.serdataout(wire_sd1a_serdataout[0:0]),
.serdatatocore()
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.clkenusr(1'b0),
.clkusr(1'b0),
.enserusr(1'b0),
.nclrusr(1'b0),
.otherenser({10{1'b0}}),
.scanclk(1'b0),
.scanen(1'b0),
.scanin(1'b0),
.serdatafromcore(1'b0),
.serdatain(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
cyclonev_termination_logic sd2a_0
(
.parallelterminationcontrol(parallelterminationcontrol),
.serdata(wire_sd1a_serdataout),
.seriesterminationcontrol(seriesterminationcontrol)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.enser(1'b0),
.s2pload(1'b0),
.scanclk(1'b0),
.scanenable(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
// synopsys translate_off
// synopsys translate_on
);
endmodule
|
module soc_system_mm_interconnect_0_rsp_mux_002
(
// ----------------------
// Sinks
// ----------------------
input sink0_valid,
input [129-1 : 0] sink0_data,
input [7-1: 0] sink0_channel,
input sink0_startofpacket,
input sink0_endofpacket,
output sink0_ready,
input sink1_valid,
input [129-1 : 0] sink1_data,
input [7-1: 0] sink1_channel,
input sink1_startofpacket,
input sink1_endofpacket,
output sink1_ready,
input sink2_valid,
input [129-1 : 0] sink2_data,
input [7-1: 0] sink2_channel,
input sink2_startofpacket,
input sink2_endofpacket,
output sink2_ready,
input sink3_valid,
input [129-1 : 0] sink3_data,
input [7-1: 0] sink3_channel,
input sink3_startofpacket,
input sink3_endofpacket,
output sink3_ready,
input sink4_valid,
input [129-1 : 0] sink4_data,
input [7-1: 0] sink4_channel,
input sink4_startofpacket,
input sink4_endofpacket,
output sink4_ready,
input sink5_valid,
input [129-1 : 0] sink5_data,
input [7-1: 0] sink5_channel,
input sink5_startofpacket,
input sink5_endofpacket,
output sink5_ready,
input sink6_valid,
input [129-1 : 0] sink6_data,
input [7-1: 0] sink6_channel,
input sink6_startofpacket,
input sink6_endofpacket,
output sink6_ready,
// ----------------------
// Source
// ----------------------
output src_valid,
output [129-1 : 0] src_data,
output [7-1 : 0] src_channel,
output src_startofpacket,
output src_endofpacket,
input src_ready,
// ----------------------
// Clock & Reset
// ----------------------
input clk,
input reset
);
localparam PAYLOAD_W = 129 + 7 + 2;
localparam NUM_INPUTS = 7;
localparam SHARE_COUNTER_W = 1;
localparam PIPELINE_ARB = 0;
localparam ST_DATA_W = 129;
localparam ST_CHANNEL_W = 7;
localparam PKT_TRANS_LOCK = 72;
// ------------------------------------------
// Signals
// ------------------------------------------
wire [NUM_INPUTS - 1 : 0] request;
wire [NUM_INPUTS - 1 : 0] valid;
wire [NUM_INPUTS - 1 : 0] grant;
wire [NUM_INPUTS - 1 : 0] next_grant;
reg [NUM_INPUTS - 1 : 0] saved_grant;
reg [PAYLOAD_W - 1 : 0] src_payload;
wire last_cycle;
reg packet_in_progress;
reg update_grant;
wire [PAYLOAD_W - 1 : 0] sink0_payload;
wire [PAYLOAD_W - 1 : 0] sink1_payload;
wire [PAYLOAD_W - 1 : 0] sink2_payload;
wire [PAYLOAD_W - 1 : 0] sink3_payload;
wire [PAYLOAD_W - 1 : 0] sink4_payload;
wire [PAYLOAD_W - 1 : 0] sink5_payload;
wire [PAYLOAD_W - 1 : 0] sink6_payload;
assign valid[0] = sink0_valid;
assign valid[1] = sink1_valid;
assign valid[2] = sink2_valid;
assign valid[3] = sink3_valid;
assign valid[4] = sink4_valid;
assign valid[5] = sink5_valid;
assign valid[6] = sink6_valid;
// ------------------------------------------
// ------------------------------------------
// Grant Logic & Updates
// ------------------------------------------
// ------------------------------------------
reg [NUM_INPUTS - 1 : 0] lock;
always @* begin
lock[0] = sink0_data[72];
lock[1] = sink1_data[72];
lock[2] = sink2_data[72];
lock[3] = sink3_data[72];
lock[4] = sink4_data[72];
lock[5] = sink5_data[72];
lock[6] = sink6_data[72];
end
assign last_cycle = src_valid & src_ready & src_endofpacket & ~(|(lock & grant));
// ------------------------------------------
// We're working on a packet at any time valid is high, except
// when this is the endofpacket.
// ------------------------------------------
always @(posedge clk or posedge reset) begin
if (reset) begin
packet_in_progress <= 1'b0;
end
else begin
if (last_cycle)
packet_in_progress <= 1'b0;
else if (src_valid)
packet_in_progress <= 1'b1;
end
end
// ------------------------------------------
// Shares
//
// Special case: all-equal shares _should_ be optimized into assigning a
// constant to next_grant_share.
// Special case: all-1's shares _should_ result in the share counter
// being optimized away.
// ------------------------------------------
// Input | arb shares | counter load value
// 0 | 1 | 0
// 1 | 1 | 0
// 2 | 1 | 0
// 3 | 1 | 0
// 4 | 1 | 0
// 5 | 1 | 0
// 6 | 1 | 0
wire [SHARE_COUNTER_W - 1 : 0] share_0 = 1'd0;
wire [SHARE_COUNTER_W - 1 : 0] share_1 = 1'd0;
wire [SHARE_COUNTER_W - 1 : 0] share_2 = 1'd0;
wire [SHARE_COUNTER_W - 1 : 0] share_3 = 1'd0;
wire [SHARE_COUNTER_W - 1 : 0] share_4 = 1'd0;
wire [SHARE_COUNTER_W - 1 : 0] share_5 = 1'd0;
wire [SHARE_COUNTER_W - 1 : 0] share_6 = 1'd0;
// ------------------------------------------
// Choose the share value corresponding to the grant.
// ------------------------------------------
reg [SHARE_COUNTER_W - 1 : 0] next_grant_share;
always @* begin
next_grant_share =
share_0 & { SHARE_COUNTER_W {next_grant[0]} } |
share_1 & { SHARE_COUNTER_W {next_grant[1]} } |
share_2 & { SHARE_COUNTER_W {next_grant[2]} } |
share_3 & { SHARE_COUNTER_W {next_grant[3]} } |
share_4 & { SHARE_COUNTER_W {next_grant[4]} } |
share_5 & { SHARE_COUNTER_W {next_grant[5]} } |
share_6 & { SHARE_COUNTER_W {next_grant[6]} };
end
// ------------------------------------------
// Flag to indicate first packet of an arb sequence.
// ------------------------------------------
wire grant_changed = ~packet_in_progress && ~(|(saved_grant & valid));
reg first_packet_r;
wire first_packet = grant_changed | first_packet_r;
always @(posedge clk or posedge reset) begin
if (reset) begin
first_packet_r <= 1'b0;
end
else begin
if (update_grant)
first_packet_r <= 1'b1;
else if (last_cycle)
first_packet_r <= 1'b0;
else if (grant_changed)
first_packet_r <= 1'b1;
end
end
// ------------------------------------------
// Compute the next share-count value.
// ------------------------------------------
reg [SHARE_COUNTER_W - 1 : 0] p1_share_count;
reg [SHARE_COUNTER_W - 1 : 0] share_count;
reg share_count_zero_flag;
always @* begin
if (first_packet) begin
p1_share_count = next_grant_share;
end
else begin
// Update the counter, but don't decrement below 0.
p1_share_count = share_count_zero_flag ? '0 : share_count - 1'b1;
end
end
// ------------------------------------------
// Update the share counter and share-counter=zero flag.
// ------------------------------------------
always @(posedge clk or posedge reset) begin
if (reset) begin
share_count <= '0;
share_count_zero_flag <= 1'b1;
end
else begin
if (last_cycle) begin
share_count <= p1_share_count;
share_count_zero_flag <= (p1_share_count == '0);
end
end
end
// ------------------------------------------
// For each input, maintain a final_packet signal which goes active for the
// last packet of a full-share packet sequence. Example: if I have 4
// shares and I'm continuously requesting, final_packet is active in the
// 4th packet.
// ------------------------------------------
wire final_packet_0 = 1'b1;
wire final_packet_1 = 1'b1;
wire final_packet_2 = 1'b1;
wire final_packet_3 = 1'b1;
wire final_packet_4 = 1'b1;
wire final_packet_5 = 1'b1;
wire final_packet_6 = 1'b1;
// ------------------------------------------
// Concatenate all final_packet signals (wire or reg) into a handy vector.
// ------------------------------------------
wire [NUM_INPUTS - 1 : 0] final_packet = {
final_packet_6,
final_packet_5,
final_packet_4,
final_packet_3,
final_packet_2,
final_packet_1,
final_packet_0
};
// ------------------------------------------
// ------------------------------------------
wire p1_done = |(final_packet & grant);
// ------------------------------------------
// Flag for the first cycle of packets within an
// arb sequence
// ------------------------------------------
reg first_cycle;
always @(posedge clk, posedge reset) begin
if (reset)
first_cycle <= 0;
else
first_cycle <= last_cycle && ~p1_done;
end
always @* begin
update_grant = 0;
// ------------------------------------------
// No arbitration pipeline, update grant whenever
// the current arb winner has consumed all shares,
// or all requests are low
// ------------------------------------------
update_grant = (last_cycle && p1_done) || (first_cycle && ~(|valid));
update_grant = last_cycle;
end
wire save_grant;
assign save_grant = 1;
assign grant = next_grant;
always @(posedge clk, posedge reset) begin
if (reset)
saved_grant <= '0;
else if (save_grant)
saved_grant <= next_grant;
end
// ------------------------------------------
// ------------------------------------------
// Arbitrator
// ------------------------------------------
// ------------------------------------------
// ------------------------------------------
// Create a request vector that stays high during
// the packet for unpipelined arbitration.
//
// The pipelined arbitration scheme does not require
// request to be held high during the packet.
// ------------------------------------------
assign request = valid;
wire [NUM_INPUTS - 1 : 0] next_grant_from_arb;
altera_merlin_arbitrator
#(
.NUM_REQUESTERS(NUM_INPUTS),
.SCHEME ("no-arb"),
.PIPELINE (0)
) arb (
.clk (clk),
.reset (reset),
.request (request),
.grant (next_grant_from_arb),
.save_top_priority (src_valid),
.increment_top_priority (update_grant)
);
assign next_grant = next_grant_from_arb;
// ------------------------------------------
// ------------------------------------------
// Mux
//
// Implemented as a sum of products.
// ------------------------------------------
// ------------------------------------------
assign sink0_ready = src_ready && grant[0];
assign sink1_ready = src_ready && grant[1];
assign sink2_ready = src_ready && grant[2];
assign sink3_ready = src_ready && grant[3];
assign sink4_ready = src_ready && grant[4];
assign sink5_ready = src_ready && grant[5];
assign sink6_ready = src_ready && grant[6];
assign src_valid = |(grant & valid);
always @* begin
src_payload =
sink0_payload & {PAYLOAD_W {grant[0]} } |
sink1_payload & {PAYLOAD_W {grant[1]} } |
sink2_payload & {PAYLOAD_W {grant[2]} } |
sink3_payload & {PAYLOAD_W {grant[3]} } |
sink4_payload & {PAYLOAD_W {grant[4]} } |
sink5_payload & {PAYLOAD_W {grant[5]} } |
sink6_payload & {PAYLOAD_W {grant[6]} };
end
// ------------------------------------------
// Mux Payload Mapping
// ------------------------------------------
assign sink0_payload = {sink0_channel,sink0_data,
sink0_startofpacket,sink0_endofpacket};
assign sink1_payload = {sink1_channel,sink1_data,
sink1_startofpacket,sink1_endofpacket};
assign sink2_payload = {sink2_channel,sink2_data,
sink2_startofpacket,sink2_endofpacket};
assign sink3_payload = {sink3_channel,sink3_data,
sink3_startofpacket,sink3_endofpacket};
assign sink4_payload = {sink4_channel,sink4_data,
sink4_startofpacket,sink4_endofpacket};
assign sink5_payload = {sink5_channel,sink5_data,
sink5_startofpacket,sink5_endofpacket};
assign sink6_payload = {sink6_channel,sink6_data,
sink6_startofpacket,sink6_endofpacket};
assign {src_channel,src_data,src_startofpacket,src_endofpacket} = src_payload;
endmodule
|
module soc_system_mm_interconnect_1_cmd_mux
(
// ----------------------
// Sinks
// ----------------------
input sink0_valid,
input [108-1 : 0] sink0_data,
input [14-1: 0] sink0_channel,
input sink0_startofpacket,
input sink0_endofpacket,
output sink0_ready,
input sink1_valid,
input [108-1 : 0] sink1_data,
input [14-1: 0] sink1_channel,
input sink1_startofpacket,
input sink1_endofpacket,
output sink1_ready,
// ----------------------
// Source
// ----------------------
output src_valid,
output [108-1 : 0] src_data,
output [14-1 : 0] src_channel,
output src_startofpacket,
output src_endofpacket,
input src_ready,
// ----------------------
// Clock & Reset
// ----------------------
input clk,
input reset
);
localparam PAYLOAD_W = 108 + 14 + 2;
localparam NUM_INPUTS = 2;
localparam SHARE_COUNTER_W = 1;
localparam PIPELINE_ARB = 1;
localparam ST_DATA_W = 108;
localparam ST_CHANNEL_W = 14;
localparam PKT_TRANS_LOCK = 72;
// ------------------------------------------
// Signals
// ------------------------------------------
wire [NUM_INPUTS - 1 : 0] request;
wire [NUM_INPUTS - 1 : 0] valid;
wire [NUM_INPUTS - 1 : 0] grant;
wire [NUM_INPUTS - 1 : 0] next_grant;
reg [NUM_INPUTS - 1 : 0] saved_grant;
reg [PAYLOAD_W - 1 : 0] src_payload;
wire last_cycle;
reg packet_in_progress;
reg update_grant;
wire [PAYLOAD_W - 1 : 0] sink0_payload;
wire [PAYLOAD_W - 1 : 0] sink1_payload;
assign valid[0] = sink0_valid;
assign valid[1] = sink1_valid;
wire [NUM_INPUTS - 1 : 0] eop;
assign eop[0] = sink0_endofpacket;
assign eop[1] = sink1_endofpacket;
// ------------------------------------------
// ------------------------------------------
// Grant Logic & Updates
// ------------------------------------------
// ------------------------------------------
reg [NUM_INPUTS - 1 : 0] lock;
always @* begin
lock[0] = sink0_data[72];
lock[1] = sink1_data[72];
end
reg [NUM_INPUTS - 1 : 0] locked = '0;
always @(posedge clk or posedge reset) begin
if (reset) begin
locked <= '0;
end
else begin
locked <= next_grant & lock;
end
end
assign last_cycle = src_valid & src_ready & src_endofpacket & ~(|(lock & grant));
// ------------------------------------------
// We're working on a packet at any time valid is high, except
// when this is the endofpacket.
// ------------------------------------------
always @(posedge clk or posedge reset) begin
if (reset) begin
packet_in_progress <= 1'b0;
end
else begin
if (last_cycle)
packet_in_progress <= 1'b0;
else if (src_valid)
packet_in_progress <= 1'b1;
end
end
// ------------------------------------------
// Shares
//
// Special case: all-equal shares _should_ be optimized into assigning a
// constant to next_grant_share.
// Special case: all-1's shares _should_ result in the share counter
// being optimized away.
// ------------------------------------------
// Input | arb shares | counter load value
// 0 | 1 | 0
// 1 | 1 | 0
wire [SHARE_COUNTER_W - 1 : 0] share_0 = 1'd0;
wire [SHARE_COUNTER_W - 1 : 0] share_1 = 1'd0;
// ------------------------------------------
// Choose the share value corresponding to the grant.
// ------------------------------------------
reg [SHARE_COUNTER_W - 1 : 0] next_grant_share;
always @* begin
next_grant_share =
share_0 & { SHARE_COUNTER_W {next_grant[0]} } |
share_1 & { SHARE_COUNTER_W {next_grant[1]} };
end
// ------------------------------------------
// Flag to indicate first packet of an arb sequence.
// ------------------------------------------
// ------------------------------------------
// Compute the next share-count value.
// ------------------------------------------
reg [SHARE_COUNTER_W - 1 : 0] p1_share_count;
reg [SHARE_COUNTER_W - 1 : 0] share_count;
reg share_count_zero_flag;
always @* begin
// Update the counter, but don't decrement below 0.
p1_share_count = share_count_zero_flag ? '0 : share_count - 1'b1;
end
// ------------------------------------------
// Update the share counter and share-counter=zero flag.
// ------------------------------------------
always @(posedge clk or posedge reset) begin
if (reset) begin
share_count <= '0;
share_count_zero_flag <= 1'b1;
end
else begin
if (update_grant) begin
share_count <= next_grant_share;
share_count_zero_flag <= (next_grant_share == '0);
end
else if (last_cycle) begin
share_count <= p1_share_count;
share_count_zero_flag <= (p1_share_count == '0);
end
end
end
always @* begin
update_grant = 0;
// ------------------------------------------
// The pipeline delays grant by one cycle, so
// we have to calculate the update_grant signal
// one cycle ahead of time.
//
// Possible optimization: omit the first clause
// "if (!packet_in_progress & ~src_valid) ..."
// cost: one idle cycle at the the beginning of each
// grant cycle.
// benefit: save a small amount of logic.
// ------------------------------------------
if (!packet_in_progress & !src_valid)
update_grant = 1;
if (last_cycle && share_count_zero_flag)
update_grant = 1;
end
wire save_grant;
assign save_grant = update_grant;
assign grant = saved_grant;
always @(posedge clk, posedge reset) begin
if (reset)
saved_grant <= '0;
else if (save_grant)
saved_grant <= next_grant;
end
// ------------------------------------------
// ------------------------------------------
// Arbitrator
// ------------------------------------------
// ------------------------------------------
// ------------------------------------------
// Create a request vector that stays high during
// the packet for unpipelined arbitration.
//
// The pipelined arbitration scheme does not require
// request to be held high during the packet.
// ------------------------------------------
reg [NUM_INPUTS - 1 : 0] prev_request;
always @(posedge clk, posedge reset) begin
if (reset)
prev_request <= '0;
else
prev_request <= request & ~(valid & eop);
end
assign request = (PIPELINE_ARB == 1) ? valid | locked :
prev_request | valid | locked;
wire [NUM_INPUTS - 1 : 0] next_grant_from_arb;
altera_merlin_arbitrator
#(
.NUM_REQUESTERS(NUM_INPUTS),
.SCHEME ("round-robin"),
.PIPELINE (1)
) arb (
.clk (clk),
.reset (reset),
.request (request),
.grant (next_grant_from_arb),
.save_top_priority (src_valid),
.increment_top_priority (update_grant)
);
assign next_grant = next_grant_from_arb;
// ------------------------------------------
// ------------------------------------------
// Mux
//
// Implemented as a sum of products.
// ------------------------------------------
// ------------------------------------------
assign sink0_ready = src_ready && grant[0];
assign sink1_ready = src_ready && grant[1];
assign src_valid = |(grant & valid);
always @* begin
src_payload =
sink0_payload & {PAYLOAD_W {grant[0]} } |
sink1_payload & {PAYLOAD_W {grant[1]} };
end
// ------------------------------------------
// Mux Payload Mapping
// ------------------------------------------
assign sink0_payload = {sink0_channel,sink0_data,
sink0_startofpacket,sink0_endofpacket};
assign sink1_payload = {sink1_channel,sink1_data,
sink1_startofpacket,sink1_endofpacket};
assign {src_channel,src_data,src_startofpacket,src_endofpacket} = src_payload;
endmodule
|
module soc_system_f2sdram_only_master_b2p_adapter
(
// Interface: in
output reg in_ready,
input in_valid,
input [8-1: 0] in_data,
input [8-1: 0] in_channel,
input in_startofpacket,
input in_endofpacket,
// Interface: out
input out_ready,
output reg out_valid,
output reg [8-1: 0] out_data,
output reg out_startofpacket,
output reg out_endofpacket,
// Interface: clk
input clk,
// Interface: reset
input reset_n
);
reg out_channel;
// ---------------------------------------------------------------------
//| Payload Mapping
// ---------------------------------------------------------------------
always @* begin
in_ready = out_ready;
out_valid = in_valid;
out_data = in_data;
out_startofpacket = in_startofpacket;
out_endofpacket = in_endofpacket;
out_channel = in_channel; //TODO delete this to avoid Quartus warnings
// Suppress channels that are higher than the destination's max_channel.
if (in_channel > 0) begin
out_valid = 0;
// Simulation Message goes here.
end
end
endmodule
|
module soc_system_mm_interconnect_0_cmd_demux_002
(
// -------------------
// Sink
// -------------------
input [7-1 : 0] sink_valid,
input [129-1 : 0] sink_data, // ST_DATA_W=129
input [7-1 : 0] sink_channel, // ST_CHANNEL_W=7
input sink_startofpacket,
input sink_endofpacket,
output sink_ready,
// -------------------
// Sources
// -------------------
output reg src0_valid,
output reg [129-1 : 0] src0_data, // ST_DATA_W=129
output reg [7-1 : 0] src0_channel, // ST_CHANNEL_W=7
output reg src0_startofpacket,
output reg src0_endofpacket,
input src0_ready,
output reg src1_valid,
output reg [129-1 : 0] src1_data, // ST_DATA_W=129
output reg [7-1 : 0] src1_channel, // ST_CHANNEL_W=7
output reg src1_startofpacket,
output reg src1_endofpacket,
input src1_ready,
output reg src2_valid,
output reg [129-1 : 0] src2_data, // ST_DATA_W=129
output reg [7-1 : 0] src2_channel, // ST_CHANNEL_W=7
output reg src2_startofpacket,
output reg src2_endofpacket,
input src2_ready,
output reg src3_valid,
output reg [129-1 : 0] src3_data, // ST_DATA_W=129
output reg [7-1 : 0] src3_channel, // ST_CHANNEL_W=7
output reg src3_startofpacket,
output reg src3_endofpacket,
input src3_ready,
output reg src4_valid,
output reg [129-1 : 0] src4_data, // ST_DATA_W=129
output reg [7-1 : 0] src4_channel, // ST_CHANNEL_W=7
output reg src4_startofpacket,
output reg src4_endofpacket,
input src4_ready,
output reg src5_valid,
output reg [129-1 : 0] src5_data, // ST_DATA_W=129
output reg [7-1 : 0] src5_channel, // ST_CHANNEL_W=7
output reg src5_startofpacket,
output reg src5_endofpacket,
input src5_ready,
output reg src6_valid,
output reg [129-1 : 0] src6_data, // ST_DATA_W=129
output reg [7-1 : 0] src6_channel, // ST_CHANNEL_W=7
output reg src6_startofpacket,
output reg src6_endofpacket,
input src6_ready,
// -------------------
// Clock & Reset
// -------------------
(*altera_attribute = "-name MESSAGE_DISABLE 15610" *) // setting message suppression on clk
input clk,
(*altera_attribute = "-name MESSAGE_DISABLE 15610" *) // setting message suppression on reset
input reset
);
localparam NUM_OUTPUTS = 7;
wire [NUM_OUTPUTS - 1 : 0] ready_vector;
// -------------------
// Demux
// -------------------
always @* begin
src0_data = sink_data;
src0_startofpacket = sink_startofpacket;
src0_endofpacket = sink_endofpacket;
src0_channel = sink_channel >> NUM_OUTPUTS;
src0_valid = sink_channel[0] && sink_valid[0];
src1_data = sink_data;
src1_startofpacket = sink_startofpacket;
src1_endofpacket = sink_endofpacket;
src1_channel = sink_channel >> NUM_OUTPUTS;
src1_valid = sink_channel[1] && sink_valid[1];
src2_data = sink_data;
src2_startofpacket = sink_startofpacket;
src2_endofpacket = sink_endofpacket;
src2_channel = sink_channel >> NUM_OUTPUTS;
src2_valid = sink_channel[2] && sink_valid[2];
src3_data = sink_data;
src3_startofpacket = sink_startofpacket;
src3_endofpacket = sink_endofpacket;
src3_channel = sink_channel >> NUM_OUTPUTS;
src3_valid = sink_channel[3] && sink_valid[3];
src4_data = sink_data;
src4_startofpacket = sink_startofpacket;
src4_endofpacket = sink_endofpacket;
src4_channel = sink_channel >> NUM_OUTPUTS;
src4_valid = sink_channel[4] && sink_valid[4];
src5_data = sink_data;
src5_startofpacket = sink_startofpacket;
src5_endofpacket = sink_endofpacket;
src5_channel = sink_channel >> NUM_OUTPUTS;
src5_valid = sink_channel[5] && sink_valid[5];
src6_data = sink_data;
src6_startofpacket = sink_startofpacket;
src6_endofpacket = sink_endofpacket;
src6_channel = sink_channel >> NUM_OUTPUTS;
src6_valid = sink_channel[6] && sink_valid[6];
end
// -------------------
// Backpressure
// -------------------
assign ready_vector[0] = src0_ready;
assign ready_vector[1] = src1_ready;
assign ready_vector[2] = src2_ready;
assign ready_vector[3] = src3_ready;
assign ready_vector[4] = src4_ready;
assign ready_vector[5] = src5_ready;
assign ready_vector[6] = src6_ready;
assign sink_ready = |(sink_channel & ready_vector);
endmodule
|
module mem #( //
parameter ADDR_LEN = 11 //
) (
input clk, rst,
input [ADDR_LEN-1:0] addr, // memory address
output reg [31:0] rd_data, // data read out
input wr_req,
input [31:0] wr_data // data write in
);
localparam MEM_SIZE = 1<<ADDR_LEN;
reg [31:0] ram_cell [MEM_SIZE];
always @ (posedge clk or posedge rst)
if(rst)
rd_data <= 0;
else
rd_data <= ram_cell[addr];
always @ (posedge clk)
if(wr_req)
ram_cell[addr] <= wr_data;
endmodule
|
module cache_tb();
`define DATA_COUNT (8)
`define RDWR_COUNT (6*`DATA_COUNT)
reg wr_cycle [`RDWR_COUNT];
reg rd_cycle [`RDWR_COUNT];
reg [31:0] addr_rom [`RDWR_COUNT];
reg [31:0] wr_data_rom [`RDWR_COUNT];
reg [31:0] validation_data [`DATA_COUNT];
initial begin
// 8 sequence write cycles
rd_cycle[ 0] = 1'b0; wr_cycle[ 0] = 1'b1; addr_rom[ 0]='h00000000; wr_data_rom[ 0]='h0000001b;
rd_cycle[ 1] = 1'b0; wr_cycle[ 1] = 1'b1; addr_rom[ 1]='h00000004; wr_data_rom[ 1]='h0000001c;
rd_cycle[ 2] = 1'b0; wr_cycle[ 2] = 1'b1; addr_rom[ 2]='h00000008; wr_data_rom[ 2]='h00000014;
rd_cycle[ 3] = 1'b0; wr_cycle[ 3] = 1'b1; addr_rom[ 3]='h0000000c; wr_data_rom[ 3]='h00000005;
rd_cycle[ 4] = 1'b0; wr_cycle[ 4] = 1'b1; addr_rom[ 4]='h00000010; wr_data_rom[ 4]='h00000016;
rd_cycle[ 5] = 1'b0; wr_cycle[ 5] = 1'b1; addr_rom[ 5]='h00000014; wr_data_rom[ 5]='h00000002;
rd_cycle[ 6] = 1'b0; wr_cycle[ 6] = 1'b1; addr_rom[ 6]='h00000018; wr_data_rom[ 6]='h00000008;
rd_cycle[ 7] = 1'b0; wr_cycle[ 7] = 1'b1; addr_rom[ 7]='h0000001c; wr_data_rom[ 7]='h00000003;
// 24 random read and write cycles
rd_cycle[ 8] = 1'b0; wr_cycle[ 8] = 1'b1; addr_rom[ 8]='h00000008; wr_data_rom[ 8]='h0000000f;
rd_cycle[ 9] = 1'b0; wr_cycle[ 9] = 1'b1; addr_rom[ 9]='h00000008; wr_data_rom[ 9]='h0000000c;
rd_cycle[ 10] = 1'b0; wr_cycle[ 10] = 1'b1; addr_rom[ 10]='h0000001c; wr_data_rom[ 10]='h00000013;
rd_cycle[ 11] = 1'b1; wr_cycle[ 11] = 1'b0; addr_rom[ 11]='h0000001c; wr_data_rom[ 11]='h00000000;
rd_cycle[ 12] = 1'b1; wr_cycle[ 12] = 1'b0; addr_rom[ 12]='h0000001c; wr_data_rom[ 12]='h00000000;
rd_cycle[ 13] = 1'b1; wr_cycle[ 13] = 1'b0; addr_rom[ 13]='h00000008; wr_data_rom[ 13]='h00000000;
rd_cycle[ 14] = 1'b1; wr_cycle[ 14] = 1'b0; addr_rom[ 14]='h00000008; wr_data_rom[ 14]='h00000000;
rd_cycle[ 15] = 1'b1; wr_cycle[ 15] = 1'b0; addr_rom[ 15]='h00000000; wr_data_rom[ 15]='h00000000;
rd_cycle[ 16] = 1'b0; wr_cycle[ 16] = 1'b1; addr_rom[ 16]='h00000018; wr_data_rom[ 16]='h00000008;
rd_cycle[ 17] = 1'b1; wr_cycle[ 17] = 1'b0; addr_rom[ 17]='h00000010; wr_data_rom[ 17]='h00000000;
rd_cycle[ 18] = 1'b0; wr_cycle[ 18] = 1'b1; addr_rom[ 18]='h00000000; wr_data_rom[ 18]='h0000001e;
rd_cycle[ 19] = 1'b1; wr_cycle[ 19] = 1'b0; addr_rom[ 19]='h00000014; wr_data_rom[ 19]='h00000000;
rd_cycle[ 20] = 1'b1; wr_cycle[ 20] = 1'b0; addr_rom[ 20]='h00000000; wr_data_rom[ 20]='h00000000;
rd_cycle[ 21] = 1'b1; wr_cycle[ 21] = 1'b0; addr_rom[ 21]='h00000000; wr_data_rom[ 21]='h00000000;
rd_cycle[ 22] = 1'b0; wr_cycle[ 22] = 1'b1; addr_rom[ 22]='h0000001c; wr_data_rom[ 22]='h00000005;
rd_cycle[ 23] = 1'b1; wr_cycle[ 23] = 1'b0; addr_rom[ 23]='h00000008; wr_data_rom[ 23]='h00000000;
rd_cycle[ 24] = 1'b0; wr_cycle[ 24] = 1'b1; addr_rom[ 24]='h00000014; wr_data_rom[ 24]='h00000000;
rd_cycle[ 25] = 1'b1; wr_cycle[ 25] = 1'b0; addr_rom[ 25]='h00000008; wr_data_rom[ 25]='h00000000;
rd_cycle[ 26] = 1'b0; wr_cycle[ 26] = 1'b1; addr_rom[ 26]='h00000000; wr_data_rom[ 26]='h0000000c;
rd_cycle[ 27] = 1'b1; wr_cycle[ 27] = 1'b0; addr_rom[ 27]='h00000010; wr_data_rom[ 27]='h00000000;
rd_cycle[ 28] = 1'b0; wr_cycle[ 28] = 1'b1; addr_rom[ 28]='h00000010; wr_data_rom[ 28]='h0000000b;
rd_cycle[ 29] = 1'b1; wr_cycle[ 29] = 1'b0; addr_rom[ 29]='h0000000c; wr_data_rom[ 29]='h00000000;
rd_cycle[ 30] = 1'b0; wr_cycle[ 30] = 1'b1; addr_rom[ 30]='h00000004; wr_data_rom[ 30]='h00000011;
rd_cycle[ 31] = 1'b1; wr_cycle[ 31] = 1'b0; addr_rom[ 31]='h0000001c; wr_data_rom[ 31]='h00000000;
// 8 silence cycles
rd_cycle[ 32] = 1'b0; wr_cycle[ 32] = 1'b0; addr_rom[ 32]='h00000000; wr_data_rom[ 32]='h00000000;
rd_cycle[ 33] = 1'b0; wr_cycle[ 33] = 1'b0; addr_rom[ 33]='h00000000; wr_data_rom[ 33]='h00000000;
rd_cycle[ 34] = 1'b0; wr_cycle[ 34] = 1'b0; addr_rom[ 34]='h00000000; wr_data_rom[ 34]='h00000000;
rd_cycle[ 35] = 1'b0; wr_cycle[ 35] = 1'b0; addr_rom[ 35]='h00000000; wr_data_rom[ 35]='h00000000;
rd_cycle[ 36] = 1'b0; wr_cycle[ 36] = 1'b0; addr_rom[ 36]='h00000000; wr_data_rom[ 36]='h00000000;
rd_cycle[ 37] = 1'b0; wr_cycle[ 37] = 1'b0; addr_rom[ 37]='h00000000; wr_data_rom[ 37]='h00000000;
rd_cycle[ 38] = 1'b0; wr_cycle[ 38] = 1'b0; addr_rom[ 38]='h00000000; wr_data_rom[ 38]='h00000000;
rd_cycle[ 39] = 1'b0; wr_cycle[ 39] = 1'b0; addr_rom[ 39]='h00000000; wr_data_rom[ 39]='h00000000;
// 8 sequence read cycles
rd_cycle[ 40] = 1'b1; wr_cycle[ 40] = 1'b0; addr_rom[ 40]='h00000000; wr_data_rom[ 40]='h00000000;
rd_cycle[ 41] = 1'b1; wr_cycle[ 41] = 1'b0; addr_rom[ 41]='h00000004; wr_data_rom[ 41]='h00000000;
rd_cycle[ 42] = 1'b1; wr_cycle[ 42] = 1'b0; addr_rom[ 42]='h00000008; wr_data_rom[ 42]='h00000000;
rd_cycle[ 43] = 1'b1; wr_cycle[ 43] = 1'b0; addr_rom[ 43]='h0000000c; wr_data_rom[ 43]='h00000000;
rd_cycle[ 44] = 1'b1; wr_cycle[ 44] = 1'b0; addr_rom[ 44]='h00000010; wr_data_rom[ 44]='h00000000;
rd_cycle[ 45] = 1'b1; wr_cycle[ 45] = 1'b0; addr_rom[ 45]='h00000014; wr_data_rom[ 45]='h00000000;
rd_cycle[ 46] = 1'b1; wr_cycle[ 46] = 1'b0; addr_rom[ 46]='h00000018; wr_data_rom[ 46]='h00000000;
rd_cycle[ 47] = 1'b1; wr_cycle[ 47] = 1'b0; addr_rom[ 47]='h0000001c; wr_data_rom[ 47]='h00000000;
end
initial begin
validation_data[ 0] = 'h0000000c;
validation_data[ 1] = 'h00000011;
validation_data[ 2] = 'h0000000c;
validation_data[ 3] = 'h00000005;
validation_data[ 4] = 'h0000000b;
validation_data[ 5] = 'h00000000;
validation_data[ 6] = 'h00000008;
validation_data[ 7] = 'h00000005;
end
reg clk = 1'b1, rst = 1'b1;
initial #4 rst = 1'b0;
always #1 clk = ~clk;
wire miss;
wire [31:0] rd_data;
reg [31:0] index = 0, wr_data = 0, addr = 0;
reg rd_req = 1'b0, wr_req = 1'b0;
reg rd_req_ff = 1'b0, miss_ff = 1'b0;
reg [31:0] validation_count = 0;
always @ (posedge clk or posedge rst)
if(rst) begin
rd_req_ff <= 1'b0;
miss_ff <= 1'b0;
end else begin
rd_req_ff <= rd_req;
miss_ff <= miss;
end
always @ (posedge clk or posedge rst)
if(rst) begin
validation_count <= 0;
end else begin
if(validation_count>=`DATA_COUNT) begin
validation_count <= 'hffffffff;
end else if(rd_req_ff && (index>(4*`DATA_COUNT))) begin
if(~miss_ff) begin
if(validation_data[validation_count]==rd_data)
validation_count <= validation_count+1;
else
validation_count <= 0;
end
end else begin
validation_count <= 0;
end
end
always @ (posedge clk or posedge rst)
if(rst) begin
index <= 0;
wr_data <= 0;
addr <= 0;
rd_req <= 1'b0;
wr_req <= 1'b0;
end else begin
if(~miss) begin
if(index<`RDWR_COUNT) begin
if(wr_cycle[index]) begin
rd_req <= 1'b0;
wr_req <= 1'b1;
end else if(rd_cycle[index]) begin
wr_data <= 0;
rd_req <= 1'b1;
wr_req <= 1'b0;
end else begin
wr_data <= 0;
rd_req <= 1'b0;
wr_req <= 1'b0;
end
wr_data <= wr_data_rom[index];
addr <= addr_rom[index];
index <= index + 1;
end else begin
wr_data <= 0;
addr <= 0;
rd_req <= 1'b0;
wr_req <= 1'b0;
end
end
end
cache #(
.LINE_ADDR_LEN ( 3 ),
.SET_ADDR_LEN ( 2 ),
.TAG_ADDR_LEN ( 12 ),
.WAY_CNT ( 3 )
) cache_test_instance (
.clk ( clk ),
.rst ( rst ),
.miss ( miss ),
.addr ( addr ),
.rd_req ( rd_req ),
.rd_data ( rd_data ),
.wr_req ( wr_req ),
.wr_data ( wr_data )
);
endmodule
|
module InstructionRam(
input clk, rst,
input [ 3:0] wea,
input [11:0] addra,
input [31:0] dina ,
output reg [31:0] douta
);
initial begin douta=0;end
reg [31:0] ram_cell [1024];
initial begin
ram_cell[ 0] = 32'h10004693;
ram_cell[ 1] = 32'h00001137;
ram_cell[ 2] = 32'h00004533;
ram_cell[ 3] = 32'h000045b3;
ram_cell[ 4] = 32'hfff68613;
ram_cell[ 5] = 32'h00261613;
ram_cell[ 6] = 32'h008000ef;
ram_cell[ 7] = 32'h0000006f;
ram_cell[ 8] = 32'h0cc5da63;
ram_cell[ 9] = 32'h0005e333;
ram_cell[ 10] = 32'h000663b3;
ram_cell[ 11] = 32'h006502b3;
ram_cell[ 12] = 32'h0002a283;
ram_cell[ 13] = 32'h04735263;
ram_cell[ 14] = 32'h00750e33;
ram_cell[ 15] = 32'h000e2e03;
ram_cell[ 16] = 32'h005e4663;
ram_cell[ 17] = 32'hffc38393;
ram_cell[ 18] = 32'hfedff06f;
ram_cell[ 19] = 32'h00650eb3;
ram_cell[ 20] = 32'h01cea023;
ram_cell[ 21] = 32'h02735263;
ram_cell[ 22] = 32'h00650e33;
ram_cell[ 23] = 32'h000e2e03;
ram_cell[ 24] = 32'h01c2c663;
ram_cell[ 25] = 32'h00430313;
ram_cell[ 26] = 32'hfedff06f;
ram_cell[ 27] = 32'h00750eb3;
ram_cell[ 28] = 32'h01cea023;
ram_cell[ 29] = 32'hfc7340e3;
ram_cell[ 30] = 32'h00650eb3;
ram_cell[ 31] = 32'h005ea023;
ram_cell[ 32] = 32'hffc10113;
ram_cell[ 33] = 32'h00112023;
ram_cell[ 34] = 32'hffc10113;
ram_cell[ 35] = 32'h00b12023;
ram_cell[ 36] = 32'hffc10113;
ram_cell[ 37] = 32'h00c12023;
ram_cell[ 38] = 32'hffc10113;
ram_cell[ 39] = 32'h00612023;
ram_cell[ 40] = 32'hffc30613;
ram_cell[ 41] = 32'hf7dff0ef;
ram_cell[ 42] = 32'h00012303;
ram_cell[ 43] = 32'h00410113;
ram_cell[ 44] = 32'h00012603;
ram_cell[ 45] = 32'h00410113;
ram_cell[ 46] = 32'h00012583;
ram_cell[ 47] = 32'hffc10113;
ram_cell[ 48] = 32'h00c12023;
ram_cell[ 49] = 32'hffc10113;
ram_cell[ 50] = 32'h00612023;
ram_cell[ 51] = 32'h00430593;
ram_cell[ 52] = 32'hf51ff0ef;
ram_cell[ 53] = 32'h00012303;
ram_cell[ 54] = 32'h00410113;
ram_cell[ 55] = 32'h00012603;
ram_cell[ 56] = 32'h00410113;
ram_cell[ 57] = 32'h00012583;
ram_cell[ 58] = 32'h00410113;
ram_cell[ 59] = 32'h00012083;
ram_cell[ 60] = 32'h00410113;
ram_cell[ 61] = 32'h00008067;
end
always @ (posedge clk or posedge rst)
if(rst)
douta <= 0;
else
douta <= ram_cell[addra];
always @ (posedge clk)
if(wea[0])
ram_cell[addra][ 7: 0] <= dina[ 7: 0];
always @ (posedge clk)
if(wea[1])
ram_cell[addra][15: 8] <= dina[15: 8];
always @ (posedge clk)
if(wea[2])
ram_cell[addra][23:16] <= dina[23:16];
always @ (posedge clk)
if(wea[3])
ram_cell[addra][31:24] <= dina[31:24];
endmodule
|
module syncpls (
input logic t_clk, //transmitting clock.
input logic t_rst_n, //reset in t_clk domain.
input logic t_pulse, //input pulse in t_clk domain.
input logic r_clk, //receiving clock.
input logic r_rst_n, //reset in r_clk_domain.
output logic r_pulse); //output pulse in r_clk domain.
logic t_tgl, r_tgl;
pls2tgl pls2tgl_inst (
.tgl(t_tgl),
.pulse(t_pulse),
.clk(t_clk),
.rst_n(t_rst_n));
sync3 sync3_inst (
.q(r_tgl),
.d(t_tgl),
.clk(r_clk),
.rst_n(r_rst_n));
tgl2pls tgl2pls_inst(
.pulse(r_pulse),
.q(),
.d(r_tgl),
.clk(r_clk),
.rst_n(r_rst_n));
endmodule
|
module usb_hid_host_top (
input wire wb_clk, // Wishbone clock - assumed to be faster than usb_clock, e.g. 50MHz.
input wire usb_clk, // 12MHz clock
input wire usb_rst_n, // USB clock domain active low reset
input wire wb_rst_n, // Wishbone clock domain active low reset
input wire usb_dm_i, usb_dp_i, // USB D- and D+ input
output wire usb_dm_o, usb_dp_o, // USB D- and D+ output
output wire usb_oe, // Output Enable.
output wire irq,
//32-bit pipelined Wishbone slave interface.
input wire [3:0] wbs_adr,
input wire [31:0] wbs_dat_w,
output reg [31:0] wbs_dat_r,
input wire [3:0] wbs_sel,
output wire wbs_stall,
input wire wbs_cyc,
input wire wbs_stb,
output wire wbs_ack,
input wire wbs_we,
output wire wbs_err
);
wire [1:0] usb_typ; //USB type
wire usb_conn_err; //USB connection error
// keyboard signals
wire [7:0] usb_key_modifiers;
wire [7:0] usb_key1, usb_key2, usb_key3, usb_key4;
// mouse signals
wire [7:0] usb_mouse_btn; // {5'bx, middle, right, left}
wire signed [7:0] usb_mouse_dx; // signed 8-bit, cleared after `report` pulse
wire signed [7:0] usb_mouse_dy; // signed 8-bit, cleared after `report` pulse
// gamepad signals
wire usb_game_l, usb_game_r, usb_game_u, usb_game_d; // left right up down
wire usb_game_a, usb_game_b, usb_game_x, usb_game_y, usb_game_sel, usb_game_sta; // buttons
wire [63:0] usb_dbg_hid_report; // last HID report
wire [3:0] leds; //Led bitmap
wire wb_update_leds_stb, usb_update_leds_stb;
wire wb_ack_update_leds_stb, usb_ack_update_leds_stb;
wire wb_report_stb, usb_report_stb;
wire wb_usb_rst_n;
//Synchronize usb clock domain reset signal to WB clock domain.
sync3 wb_usb_rst_n_sync (
.q(wb_usb_rst_n),
.d(usb_rst_n),
.clk(wb_clk),
.rst_n(wb_rst_n));
//Wishbone front-end for USB HID host.
wb_usb_hid_host wb_usb_hid_host_inst(
.wb_clk(wb_clk),
.wb_rst_n(wb_rst_n),
.irq(irq),
.wbs_adr(wbs_adr),
.wbs_dat_w(wbs_dat_w),
.wbs_dat_r(wbs_dat_r),
.wbs_sel(wbs_sel),
.wbs_stall(wbs_stall),
.wbs_cyc(wbs_cyc),
.wbs_stb(wbs_stb),
.wbs_ack(wbs_ack),
.wbs_we(wbs_we),
.wbs_err(wbs_err),
.wb_usb_rst_n(wb_usb_rst_n),
.usb_typ(usb_typ),
.usb_report_stb(wb_report_stb),
.usb_conn_err(usb_conn_err),
.usb_key_modifiers(usb_key_modifiers),
.usb_key1(usb_key1), .usb_key2(usb_key2), .usb_key3(usb_key3), .usb_key4(usb_key4),
.usb_mouse_btn(usb_mouse_btn),
.usb_mouse_dx(usb_mouse_dx),
.usb_mouse_dy(usb_mouse_dy),
.usb_game_l(usb_game_l), .usb_game_r(usb_game_r), .usb_game_u(usb_game_u), .usb_game_d(usb_game_d),
.usb_game_a(usb_game_a), .usb_game_b(usb_game_b), .usb_game_x(usb_game_x), .usb_game_y(usb_game_y),
.usb_game_sel(usb_game_sel), .usb_game_sta(usb_game_sta),
.usb_dbg_hid_report(usb_dbg_hid_report),
.update_leds_stb(wb_update_leds_stb),
.leds(leds),
.ack_update_leds_stb(wb_ack_update_leds_stb)
);
//Synchronize update_leds pulse to USB clock domain.
syncpls update_leds_syncpls (
.t_clk(wb_clk), //transmitting clock.
.t_rst_n(wb_rst_n), //reset in t_clk domain.
.t_pulse(wb_update_leds_stb), //input pulse in t_clk domain.
.r_clk(usb_clk), //receiving clock.
.r_rst_n(usb_rst_n), //reset in r_clk_domain.
.r_pulse(usb_update_leds_stb)); //output pulse in r_clk domain.
//Synchronize ack_update_leds pulse to WB clock domain.
syncpls ack_update_leds_syncpls (
.t_clk(usb_clk), //transmitting clock.
.t_rst_n(usb_rst_n), //reset in t_clk domain.
.t_pulse(usb_ack_update_leds_stb), //input pulse in t_clk domain.
.r_clk(wb_clk), //receiving clock.
.r_rst_n(wb_rst_n), //reset in r_clk_domain.
.r_pulse(wb_ack_update_leds_stb)); //output pulse in r_clk domain.
//Synchronize usb_report pulse to WB clock domain.
syncpls usb_report_syncpls (
.t_clk(usb_clk), //transmitting clock.
.t_rst_n(usb_rst_n), //reset in t_clk domain.
.t_pulse(usb_report_stb), //input pulse in t_clk domain.
.r_clk(wb_clk), //receiving clock.
.r_rst_n(wb_rst_n), //reset in r_clk_domain.
.r_pulse(wb_report_stb)); //output pulse in r_clk domain.
usb_hid_host usb_hid_host_inst (
.usbclk(usb_clk),
.usbrst_n(usb_rst_n),
.usb_dm_i(usb_dm_i),
.usb_dp_i(usb_dp_i),
.usb_dm_o(usb_dm_o),
.usb_dp_o(usb_dp_o),
.usb_oe(usb_oe),
.update_leds_stb(usb_update_leds_stb),
.ack_update_leds_stb(usb_ack_update_leds_stb),
.leds(leds),
.typ(usb_typ),
.report(usb_report_stb),
.conerr(usb_conn_err),
.key_modifiers(usb_key_modifiers),
.key1(usb_key1),
.key2(usb_key2),
.key3(usb_key3),
.key4(usb_key4),
.mouse_btn(usb_mouse_btn),
.mouse_dx(usb_mouse_dx),
.mouse_dy(usb_mouse_dy),
.game_l(usb_game_l),
.game_r(usb_game_r),
.game_u(usb_game_u),
.game_d(usb_game_d),
.game_a(usb_game_a),
.game_b(usb_game_b),
.game_x(usb_game_x),
.game_y(usb_game_y),
.game_sel(usb_game_sel),
.game_sta(usb_game_sta),
.dbg_hid_report(usb_dbg_hid_report));
endmodule
|
module wb_usb_hid_host (
input wire wb_clk, // Wishbone clock - assumed to be faster than usb_clock, e.g. 50MHz.
input wire wb_rst_n, // System clock domain active low reset
output wire irq,
//32-bit pipelined Wishbone slave interface.
input wire [3:0] wbs_adr,
input wire [31:0] wbs_dat_w,
output reg [31:0] wbs_dat_r,
input wire [3:0] wbs_sel,
output wire wbs_stall,
input wire wbs_cyc,
input wire wbs_stb,
output wire wbs_ack,
input wire wbs_we,
output wire wbs_err,
input wire wb_usb_rst_n, //WB synchronous indication that USB clock domain is in reset
input wire [1:0] usb_typ, //USB type
input wire usb_report_stb, //USB report strobe indication
input wire usb_conn_err, //USB connection error
// keyboard signals
input wire [7:0] usb_key_modifiers,
input wire [7:0] usb_key1,
usb_key2,
usb_key3,
usb_key4,
// mouse signals
input wire [7:0] usb_mouse_btn, // {5'bx, middle, right, left}
input wire signed [7:0] usb_mouse_dx, // signed 8-bit, cleared after `report` pulse
input wire signed [7:0] usb_mouse_dy, // signed 8-bit, cleared after `report` pulse
// gamepad signals
input wire usb_game_l,
usb_game_r,
usb_game_u,
usb_game_d, // left right up down
input wire usb_game_a,
usb_game_b,
usb_game_x,
usb_game_y,
usb_game_sel,
usb_game_sta, // buttons
input wire [63:0] usb_dbg_hid_report, // last HID report
// Pulse requesting to update keyboard LEDS.
output reg update_leds_stb,
output reg [3:0] leds, //Led bitmap
// Indication that leds have been updated
input wire ack_update_leds_stb
);
reg [1:0] wb_usb_ien; //IRQ enable register
reg [1:0] wb_usb_isr; //IRQ status register
reg [1:0] wb_usb_typ; //USB type register: 0: no device, 1: keyboard, 2: mouse, 3: gamepad
reg wb_usb_conn_err; //USB connection error register.
// keyboard registers.
reg [7:0] wb_usb_key_modifiers;
reg [7:0] wb_usb_key1, wb_usb_key2, wb_usb_key3, wb_usb_key4;
// mouse registers.
reg [7:0] wb_usb_mouse_btn; // {5'bx, middle, right, left}
reg signed [7:0] wb_usb_mouse_dx; // signed 8-bit, cleared after `report` pulse
reg signed [7:0] wb_usb_mouse_dy; // signed 8-bit, cleared after `report` pulse
// gamepad registers.
reg wb_usb_game_l, wb_usb_game_r, wb_usb_game_u, wb_usb_game_d; // left right up down
reg
wb_usb_game_a,
wb_usb_game_b,
wb_usb_game_x,
wb_usb_game_y,
wb_usb_game_sel,
wb_usb_game_sta; // buttons
reg [63:0] wb_usb_dbg_hid_report; // last HID report register.
// Wishbone
reg do_ack_wbs;
wire do_wbs_wr_reg;
wire unused = &{wbs_sel, wbs_dat_w[31:4]};
//IRQ signalling.
assign irq = |(wb_usb_isr & wb_usb_ien);
//WB slave handshake.
assign do_wbs_wr_reg = wbs_cyc && wbs_stb && wbs_we;
assign wbs_ack = do_ack_wbs & wbs_cyc;
assign wbs_stall = 1'b0;
assign wbs_err = 1'b0;
always @(posedge wb_clk) begin
if ((!wb_usb_rst_n) || (!wb_rst_n)) begin
if (!wb_rst_n) begin
wb_usb_ien <= 2'b0;
do_ack_wbs <= 1'b0;
update_leds_stb <= 1'b0;
leds <= 4'b0;
end
wb_usb_isr <= 2'b00;
wb_usb_typ <= 2'b00;
wb_usb_conn_err <= 1'b0;
end else begin
//WBS ack on next clock cycle.
do_ack_wbs <= 1'b0;
if (wbs_stb) begin
do_ack_wbs <= 1'b1;
end
update_leds_stb <= 1'b0;
//WBS register writes
//A write to WB register 9 triggers an update_led action to the usb_hid_host module.
//The usb_hid_host module will send the new led bitmap to the USB device using a SetReport transaction.
if (do_wbs_wr_reg) begin
case (wbs_adr)
4'd0: wb_usb_ien <= wbs_dat_w[1:0];
4'd1: wb_usb_isr <= wb_usb_isr & ~wbs_dat_w[1:0];
4'd9: begin
update_leds_stb <= 1'b1;
leds <= wbs_dat_w[3:0];
end
default: ;
endcase
end
//update_led acknowledge received. Signal ISR.
if (ack_update_leds_stb) wb_usb_isr[1] <= 1'b1;
//A USB report has been received.
if (usb_report_stb) begin
wb_usb_isr[0] <= 1'b1;
{wb_usb_typ, wb_usb_conn_err} <= {usb_typ, usb_conn_err};
{wb_usb_key_modifiers, wb_usb_key1, wb_usb_key2, wb_usb_key3, wb_usb_key4} <= {
usb_key_modifiers, usb_key1, usb_key2, usb_key3, usb_key4
};
{wb_usb_mouse_btn, wb_usb_mouse_dx, wb_usb_mouse_dy} <= {
usb_mouse_btn, usb_mouse_dx, usb_mouse_dy
};
{wb_usb_game_l, wb_usb_game_r, wb_usb_game_u, wb_usb_game_d, wb_usb_game_a, wb_usb_game_b, wb_usb_game_x, wb_usb_game_y, wb_usb_game_sel, wb_usb_game_sta}
<= {
usb_game_l,
usb_game_r,
usb_game_u,
usb_game_d,
usb_game_a,
usb_game_b,
usb_game_x,
usb_game_y,
usb_game_sel,
usb_game_sta
};
wb_usb_dbg_hid_report <= usb_dbg_hid_report;
end
end
end
//WBS register reads
always @* begin
case (wbs_adr) //wbs address is a word address.
4'd0: wbs_dat_r = {30'b0, wb_usb_ien};
4'd1: wbs_dat_r = {30'b0, wb_usb_isr};
4'd2: wbs_dat_r = {29'b0, wb_usb_conn_err, wb_usb_typ};
4'd3: wbs_dat_r = {24'b0, wb_usb_key_modifiers};
4'd4: wbs_dat_r = {wb_usb_key4, wb_usb_key3, wb_usb_key2, wb_usb_key1};
4'd5: wbs_dat_r = {8'b0, wb_usb_mouse_btn, wb_usb_mouse_dx, wb_usb_mouse_dy};
4'd6:
wbs_dat_r = {
22'b0,
wb_usb_game_l,
wb_usb_game_r,
wb_usb_game_u,
wb_usb_game_d,
wb_usb_game_a,
wb_usb_game_b,
wb_usb_game_x,
wb_usb_game_y,
wb_usb_game_sel,
wb_usb_game_sta
};
4'd7: wbs_dat_r = wb_usb_dbg_hid_report[31:0];
4'd8: wbs_dat_r = wb_usb_dbg_hid_report[63:32];
4'd9: wbs_dat_r = {28'b0, leds};
default: wbs_dat_r = 32'd0;
endcase
end
endmodule
|
module wbxbar_ooc #(
parameter NM = 6, NS=8,
parameter AW = 28, DW=32,
parameter [NS*AW-1:0] SLAVE_ADDR = {
{ 3'b111, {(AW-3){1'b0}} },
{ 3'b110, {(AW-3){1'b0}} },
{ 3'b101, {(AW-3){1'b0}} },
{ 3'b100, {(AW-3){1'b0}} },
{ 3'b011, {(AW-3){1'b0}} },
{ 3'b010, {(AW-3){1'b0}} },
{ 4'b0010, {(AW-4){1'b0}} },
{ 4'b0000, {(AW-4){1'b0}} } },
parameter [NS*AW-1:0] SLAVE_MASK = { {(NS-2){ 3'b111, {(AW-3){1'b0}} }},
{(2){ 4'b1111, {(AW-4){1'b0}} }} }
) (
input logic i_clk, i_reset,
input logic [NM-1:0] i_mcyc, i_mstb, i_mwe,
input logic [NM*AW-1:0] i_maddr,
input logic [NM*DW-1:0] i_mdata,
input logic [NM*DW/8-1:0] i_msel,
output logic [NM-1:0] o_mstall,
output logic [NM-1:0] o_mack,
output logic [NM*DW-1:0] o_mdata,
output logic [NM-1:0] o_merr,
output logic [NS-1:0] o_scyc, o_sstb, o_swe,
output logic [NS*AW-1:0] o_saddr,
output logic [NS*DW-1:0] o_sdata,
output logic [NS*DW/8-1:0] o_ssel,
input logic [NS-1:0] i_sstall, i_sack,
input logic [NS*DW-1:0] i_sdata,
input logic [NS-1:0] i_serr);
wbxbar #(
.NM(NM), .NS(NS),
.AW(AW), .DW(DW),
.SLAVE_ADDR(SLAVE_ADDR),
.SLAVE_MASK(SLAVE_MASK),
.OPT_DBLBUFFER(1'b0),
.OPT_LOWPOWER(1'b0) ) wbxbar_inst(.*);
endmodule
|
module wb_timer (
input wire clk_i,
input wire rst_i,
input wire wb_cyc_i,
input wire wb_stb_i,
input wire wb_we_i,
input wire [7:0] wb_addr_i,
input wire [31:0] wb_data_i,
input wire [3:0] wb_sel_i,
output wire wb_stall_o,
output wire wb_ack_o,
output wire wb_err_o,
output wire [31:0] wb_data_o,
output wire timer_irq_o
);
assign wb_stall_o = 1'b0;
timer #(
.DataWidth(32),
.AddressWidth(10)
) timer_inst (
.clk_i(clk_i),
.rst_ni(~rst_i),
.timer_req_i(wb_cyc_i & wb_stb_i),
.timer_addr_i({wb_addr_i, 2'b00}), //Word-to-Byte addressing
.timer_we_i(wb_we_i),
.timer_be_i(wb_sel_i),
.timer_wdata_i(wb_data_i),
.timer_rvalid_o(wb_ack_o),
.timer_rdata_o(wb_data_o),
.timer_err_o(wb_err_o),
.timer_intr_o(timer_irq_o)
);
endmodule
|
module cpu_sys_rsp_xbar_mux
(
// ----------------------
// Sinks
// ----------------------
input sink0_valid,
input [90-1 : 0] sink0_data,
input [5-1: 0] sink0_channel,
input sink0_startofpacket,
input sink0_endofpacket,
output sink0_ready,
input sink1_valid,
input [90-1 : 0] sink1_data,
input [5-1: 0] sink1_channel,
input sink1_startofpacket,
input sink1_endofpacket,
output sink1_ready,
input sink2_valid,
input [90-1 : 0] sink2_data,
input [5-1: 0] sink2_channel,
input sink2_startofpacket,
input sink2_endofpacket,
output sink2_ready,
input sink3_valid,
input [90-1 : 0] sink3_data,
input [5-1: 0] sink3_channel,
input sink3_startofpacket,
input sink3_endofpacket,
output sink3_ready,
input sink4_valid,
input [90-1 : 0] sink4_data,
input [5-1: 0] sink4_channel,
input sink4_startofpacket,
input sink4_endofpacket,
output sink4_ready,
// ----------------------
// Source
// ----------------------
output src_valid,
output [90-1 : 0] src_data,
output [5-1 : 0] src_channel,
output src_startofpacket,
output src_endofpacket,
input src_ready,
// ----------------------
// Clock & Reset
// ----------------------
input clk,
input reset
);
localparam PAYLOAD_W = 90 + 5 + 2;
localparam NUM_INPUTS = 5;
localparam SHARE_COUNTER_W = 1;
localparam PIPELINE_ARB = 0;
localparam ST_DATA_W = 90;
localparam ST_CHANNEL_W = 5;
localparam PKT_TRANS_LOCK = 57;
// ------------------------------------------
// Signals
// ------------------------------------------
wire [NUM_INPUTS - 1 : 0] request;
wire [NUM_INPUTS - 1 : 0] valid;
wire [NUM_INPUTS - 1 : 0] grant;
wire [NUM_INPUTS - 1 : 0] next_grant;
reg [NUM_INPUTS - 1 : 0] saved_grant;
reg [PAYLOAD_W - 1 : 0] src_payload;
wire last_cycle;
reg packet_in_progress;
reg update_grant;
wire [PAYLOAD_W - 1 : 0] sink0_payload;
wire [PAYLOAD_W - 1 : 0] sink1_payload;
wire [PAYLOAD_W - 1 : 0] sink2_payload;
wire [PAYLOAD_W - 1 : 0] sink3_payload;
wire [PAYLOAD_W - 1 : 0] sink4_payload;
assign valid[0] = sink0_valid;
assign valid[1] = sink1_valid;
assign valid[2] = sink2_valid;
assign valid[3] = sink3_valid;
assign valid[4] = sink4_valid;
// ------------------------------------------
// ------------------------------------------
// Grant Logic & Updates
// ------------------------------------------
// ------------------------------------------
reg [NUM_INPUTS - 1 : 0] lock;
always @* begin
lock[0] = sink0_data[57];
lock[1] = sink1_data[57];
lock[2] = sink2_data[57];
lock[3] = sink3_data[57];
lock[4] = sink4_data[57];
end
assign last_cycle = src_valid & src_ready & src_endofpacket & ~(|(lock & grant));
// ------------------------------------------
// We're working on a packet at any time valid is high, except
// when this is the endofpacket.
// ------------------------------------------
always @(posedge clk or posedge reset) begin
if (reset) begin
packet_in_progress <= 1'b0;
end
else begin
if (src_valid)
packet_in_progress <= 1'b1;
if (last_cycle)
packet_in_progress <= 1'b0;
end
end
// ------------------------------------------
// Shares
//
// Special case: all-equal shares _should_ be optimized into assigning a
// constant to next_grant_share.
// Special case: all-1's shares _should_ result in the share counter
// being optimized away.
// ------------------------------------------
// Input | arb shares | counter load value
// 0 | 1 | 0
// 1 | 1 | 0
// 2 | 1 | 0
// 3 | 1 | 0
// 4 | 1 | 0
wire [SHARE_COUNTER_W - 1 : 0] share_0 = 1'd0;
wire [SHARE_COUNTER_W - 1 : 0] share_1 = 1'd0;
wire [SHARE_COUNTER_W - 1 : 0] share_2 = 1'd0;
wire [SHARE_COUNTER_W - 1 : 0] share_3 = 1'd0;
wire [SHARE_COUNTER_W - 1 : 0] share_4 = 1'd0;
// ------------------------------------------
// Choose the share value corresponding to the grant.
// ------------------------------------------
reg [SHARE_COUNTER_W - 1 : 0] next_grant_share;
always @* begin
next_grant_share =
share_0 & { SHARE_COUNTER_W {next_grant[0]} } |
share_1 & { SHARE_COUNTER_W {next_grant[1]} } |
share_2 & { SHARE_COUNTER_W {next_grant[2]} } |
share_3 & { SHARE_COUNTER_W {next_grant[3]} } |
share_4 & { SHARE_COUNTER_W {next_grant[4]} };
end
// ------------------------------------------
// Flag to indicate first packet of an arb sequence.
// ------------------------------------------
wire grant_changed = ~packet_in_progress && !(saved_grant & valid);
reg first_packet_r;
wire first_packet = grant_changed | first_packet_r;
always @(posedge clk or posedge reset) begin
if (reset) begin
first_packet_r <= 1'b0;
end
else begin
if (update_grant)
first_packet_r <= 1'b1;
else if (last_cycle)
first_packet_r <= 1'b0;
else if (grant_changed)
first_packet_r <= 1'b1;
end
end
// ------------------------------------------
// Compute the next share-count value.
// ------------------------------------------
reg [SHARE_COUNTER_W - 1 : 0] p1_share_count;
reg [SHARE_COUNTER_W - 1 : 0] share_count;
reg share_count_zero_flag;
always @* begin
if (first_packet) begin
p1_share_count = next_grant_share;
end
else begin
// Update the counter, but don't decrement below 0.
p1_share_count = share_count_zero_flag ? '0 : share_count - 1'b1;
end
end
// ------------------------------------------
// Update the share counter and share-counter=zero flag.
// ------------------------------------------
always @(posedge clk or posedge reset) begin
if (reset) begin
share_count <= '0;
share_count_zero_flag <= 1'b1;
end
else begin
if (last_cycle) begin
share_count <= p1_share_count;
share_count_zero_flag <= (p1_share_count == '0);
end
end
end
// ------------------------------------------
// For each input, maintain a final_packet signal which goes active for the
// last packet of a full-share packet sequence. Example: if I have 4
// shares and I'm continuously requesting, final_packet is active in the
// 4th packet.
// ------------------------------------------
wire final_packet_0 = 1'b1;
wire final_packet_1 = 1'b1;
wire final_packet_2 = 1'b1;
wire final_packet_3 = 1'b1;
wire final_packet_4 = 1'b1;
// ------------------------------------------
// Concatenate all final_packet signals (wire or reg) into a handy vector.
// ------------------------------------------
wire [NUM_INPUTS - 1 : 0] final_packet = {
final_packet_4,
final_packet_3,
final_packet_2,
final_packet_1,
final_packet_0
};
// ------------------------------------------
// ------------------------------------------
wire p1_done = |(final_packet & grant);
// ------------------------------------------
// Flag for the first cycle of packets within an
// arb sequence
// ------------------------------------------
reg first_cycle;
always @(posedge clk, posedge reset) begin
if (reset)
first_cycle <= 0;
else
first_cycle <= last_cycle && ~p1_done;
end
always @* begin
update_grant = 0;
// ------------------------------------------
// No arbitration pipeline, update grant whenever
// the current arb winner has consumed all shares,
// or all requests are low
// ------------------------------------------
update_grant = (last_cycle && p1_done) || (first_cycle && !valid);
update_grant = last_cycle;
end
wire save_grant;
assign save_grant = 1;
assign grant = next_grant;
always @(posedge clk, posedge reset) begin
if (reset)
saved_grant <= '0;
else if (save_grant)
saved_grant <= next_grant;
end
// ------------------------------------------
// ------------------------------------------
// Arbitrator
// ------------------------------------------
// ------------------------------------------
// ------------------------------------------
// Create a request vector that stays high during
// the packet for unpipelined arbitration.
//
// The pipelined arbitration scheme does not require
// request to be held high during the packet.
// ------------------------------------------
assign request = valid;
altera_merlin_arbitrator
#(
.NUM_REQUESTERS(NUM_INPUTS),
.SCHEME ("no-arb"),
.PIPELINE (0)
) arb (
.clk (clk),
.reset (reset),
.request (request),
.grant (next_grant),
.save_top_priority (src_valid),
.increment_top_priority (update_grant)
);
// ------------------------------------------
// ------------------------------------------
// Mux
//
// Implemented as a sum of products.
// ------------------------------------------
// ------------------------------------------
assign sink0_ready = src_ready && grant[0];
assign sink1_ready = src_ready && grant[1];
assign sink2_ready = src_ready && grant[2];
assign sink3_ready = src_ready && grant[3];
assign sink4_ready = src_ready && grant[4];
assign src_valid = |(grant & valid);
always @* begin
src_payload =
sink0_payload & {PAYLOAD_W {grant[0]} } |
sink1_payload & {PAYLOAD_W {grant[1]} } |
sink2_payload & {PAYLOAD_W {grant[2]} } |
sink3_payload & {PAYLOAD_W {grant[3]} } |
sink4_payload & {PAYLOAD_W {grant[4]} };
end
// ------------------------------------------
// Mux Payload Mapping
// ------------------------------------------
assign sink0_payload = {sink0_channel,sink0_data,
sink0_startofpacket,sink0_endofpacket};
assign sink1_payload = {sink1_channel,sink1_data,
sink1_startofpacket,sink1_endofpacket};
assign sink2_payload = {sink2_channel,sink2_data,
sink2_startofpacket,sink2_endofpacket};
assign sink3_payload = {sink3_channel,sink3_data,
sink3_startofpacket,sink3_endofpacket};
assign sink4_payload = {sink4_channel,sink4_data,
sink4_startofpacket,sink4_endofpacket};
assign {src_channel,src_data,src_startofpacket,src_endofpacket} = src_payload;
endmodule
|
module altera_merlin_arbitrator
#(
parameter NUM_REQUESTERS = 8,
// --------------------------------------
// Implemented schemes
// "round-robin"
// "fixed-priority"
// "no-arb"
// --------------------------------------
parameter SCHEME = "round-robin",
parameter PIPELINE = 0
)
(
input clk,
input reset,
// --------------------------------------
// Requests
// --------------------------------------
input [NUM_REQUESTERS-1:0] request,
// --------------------------------------
// Grants
// --------------------------------------
output [NUM_REQUESTERS-1:0] grant,
// --------------------------------------
// Control Signals
// --------------------------------------
input increment_top_priority,
input save_top_priority
);
// --------------------------------------
// Signals
// --------------------------------------
wire [NUM_REQUESTERS-1:0] top_priority;
reg [NUM_REQUESTERS-1:0] top_priority_reg;
reg [NUM_REQUESTERS-1:0] last_grant;
wire [2*NUM_REQUESTERS-1:0] result;
// --------------------------------------
// Scheme Selection
// --------------------------------------
generate
if (SCHEME == "round-robin" && NUM_REQUESTERS > 1) begin
assign top_priority = top_priority_reg;
end
else begin
// Fixed arbitration (or single-requester corner case)
assign top_priority = 1'b1;
end
endgenerate
// --------------------------------------
// Decision Logic
// --------------------------------------
altera_merlin_arb_adder
#(
.WIDTH (2 * NUM_REQUESTERS)
)
adder
(
.a ({ ~request, ~request }),
.b ({{NUM_REQUESTERS{1'b0}}, top_priority}),
.sum (result)
);
generate if (SCHEME == "no-arb") begin
// --------------------------------------
// No arbitration: just wire request directly to grant
// --------------------------------------
assign grant = request;
end else begin
// Do the math in double-vector domain
wire [2*NUM_REQUESTERS-1:0] grant_double_vector;
assign grant_double_vector = {request, request} & result;
// --------------------------------------
// Extract grant from the top and bottom halves
// of the double vector.
// --------------------------------------
assign grant =
grant_double_vector[NUM_REQUESTERS - 1 : 0] |
grant_double_vector[2 * NUM_REQUESTERS - 1 : NUM_REQUESTERS];
end
endgenerate
// --------------------------------------
// Left-rotate the last grant vector to create top_priority.
// --------------------------------------
always @(posedge clk or posedge reset) begin
if (reset) begin
top_priority_reg <= 1'b1;
end
else begin
if (PIPELINE) begin
if (increment_top_priority) begin
top_priority_reg <= (|request) ? {grant[NUM_REQUESTERS-2:0],
grant[NUM_REQUESTERS-1]} : top_priority_reg;
end
end else begin
if (save_top_priority) begin
top_priority_reg <= grant;
end
if (increment_top_priority) begin
if (|request)
top_priority_reg <= { grant[NUM_REQUESTERS-2:0],
grant[NUM_REQUESTERS-1] };
else
top_priority_reg <= { top_priority_reg[NUM_REQUESTERS-2:0], top_priority_reg[NUM_REQUESTERS-1] };
end
end
end
end
endmodule
|
module altera_merlin_arb_adder
#(
parameter WIDTH = 8
)
(
input [WIDTH-1:0] a,
input [WIDTH-1:0] b,
output [WIDTH-1:0] sum
);
// ----------------------------------------------
// Benchmarks indicate that for small widths, the full
// adder has higher fmax because synthesis can merge
// it with the mux, allowing partial decisions to be
// made early.
//
// The magic number is 4 requesters, which means an
// 8 bit adder.
// ----------------------------------------------
genvar i;
generate if (WIDTH <= 8) begin : full_adder
wire cout[WIDTH-1:0];
assign sum[0] = (a[0] ^ b[0]);
assign cout[0] = (a[0] & b[0]);
for (i = 1; i < WIDTH; i = i+1) begin : arb
assign sum[i] = (a[i] ^ b[i]) ^ cout[i-1];
assign cout[i] = (a[i] & b[i]) | (cout[i-1] & (a[i] ^ b[i]));
end
end else begin : carry_chain
assign sum = a + b;
end
endgenerate
endmodule
|
module altera_merlin_burst_uncompressor
#(
parameter ADDR_W = 16,
parameter BURSTWRAP_W = 3,
parameter BYTE_CNT_W = 4,
parameter PKT_SYMBOLS = 4,
parameter BURST_SIZE_W = 3
)
(
input clk,
input reset,
// sink ST signals
input sink_startofpacket,
input sink_endofpacket,
input sink_valid,
output sink_ready,
// sink ST "data"
input [ADDR_W - 1: 0] sink_addr,
input [BURSTWRAP_W - 1 : 0] sink_burstwrap,
input [BYTE_CNT_W - 1 : 0] sink_byte_cnt,
input sink_is_compressed,
input [BURST_SIZE_W-1 : 0] sink_burstsize,
// source ST signals
output source_startofpacket,
output source_endofpacket,
output source_valid,
input source_ready,
// source ST "data"
output [ADDR_W - 1: 0] source_addr,
output [BURSTWRAP_W - 1 : 0] source_burstwrap,
output [BYTE_CNT_W - 1 : 0] source_byte_cnt,
// Note: in the slave agent, the output should always be uncompressed. In
// other applications, it may be required to leave-compressed or not. How to
// control? Seems like a simple mux - pass-through if no uncompression is
// required.
output source_is_compressed,
output [BURST_SIZE_W-1 : 0] source_burstsize
);
//----------------------------------------------------
// AXSIZE decoding
//
// Turns the axsize value into the actual number of bytes
// being transferred.
// ---------------------------------------------------
function reg[63:0] bytes_in_transfer;
input [2:0] axsize;
case (axsize)
3'b000: bytes_in_transfer = 64'b0000000000000000000000000000000000000000000000000000000000000001;
3'b001: bytes_in_transfer = 64'b0000000000000000000000000000000000000000000000000000000000000010;
3'b010: bytes_in_transfer = 64'b0000000000000000000000000000000000000000000000000000000000000100;
3'b011: bytes_in_transfer = 64'b0000000000000000000000000000000000000000000000000000000000001000;
3'b100: bytes_in_transfer = 64'b0000000000000000000000000000000000000000000000000000000000010000;
3'b101: bytes_in_transfer = 64'b0000000000000000000000000000000000000000000000000000000000100000;
3'b110: bytes_in_transfer = 64'b0000000000000000000000000000000000000000000000000000000001000000;
3'b111: bytes_in_transfer = 64'b0000000000000000000000000000000000000000000000000000000010000000;
default:bytes_in_transfer = 64'b0000000000000000000000000000000000000000000000000000000000000001;
endcase
endfunction
// num_symbols is PKT_SYMBOLS, appropriately sized.
wire [31:0] int_num_symbols = PKT_SYMBOLS;
wire [BYTE_CNT_W-1:0] num_symbols = int_num_symbols[BYTE_CNT_W-1:0];
// def: Burst Compression. In a merlin network, a compressed burst is one
// which is transmitted in a single beat. Example: read burst. In
// constrast, an uncompressed burst (example: write burst) is transmitted in
// one beat per writedata item.
//
// For compressed bursts which require response packets, burst
// uncompression is required. Concrete example: a read burst of size 8
// occupies one response-fifo position. When that fifo position reaches the
// front of the FIFO, the slave starts providing the required 8 readdatavalid
// pulses. The 8 return response beats must be provided in a single packet,
// with incrementing address and decrementing byte_cnt fields. Upon receipt
// of the final readdata item of the burst, the response FIFO item is
// retired.
// Burst uncompression logic provides:
// a) 2-state FSM (idle, busy)
// reset to idle state
// transition to busy state for 2nd and subsequent rdv pulses
// - a single-cycle burst (aka non-burst read) causes no transition to
// busy state.
// b) response startofpacket/endofpacket logic. The response FIFO item
// will have sop asserted, and may have eop asserted. (In the case of
// multiple read bursts transmit in the command fabric in a single packet,
// the eop assertion will come in a later FIFO item.) To support packet
// conservation, and emit a well-formed packet on the response fabric,
// i) response fabric startofpacket is asserted only for the first resp.
// beat;
// ii) response fabric endofpacket is asserted only for the last resp.
// beat.
// c) response address field. The response address field contains an
// incrementing sequence, such that each readdata item is associated with
// its slave-map location. N.b. a) computing the address correctly requires
// knowledge of burstwrap behavior b) there may be no clients of the address
// field, which makes this field a good target for optimization. See
// burst_uncompress_address_counter below.
// d) response byte_cnt field. The response byte_cnt field contains a
// decrementing sequence, such that each beat of the response contains the
// count of bytes to follow. In the case of sub-bursts in a single packet,
// the byte_cnt field may decrement down to num_symbols, then back up to
// some value, multiple times in the packet.
reg burst_uncompress_busy;
reg [BYTE_CNT_W-1:0] burst_uncompress_byte_counter;
wire first_packet_beat;
wire last_packet_beat;
assign first_packet_beat = sink_valid & ~burst_uncompress_busy;
// First cycle: burst_uncompress_byte_counter isn't ready yet, mux the input to
// the output.
assign source_byte_cnt =
first_packet_beat ? sink_byte_cnt : burst_uncompress_byte_counter;
assign source_valid = sink_valid;
// Last packet beat is set throughout receipt of an uncompressed read burst
// from the response FIFO - this forces all the burst uncompression machinery
// idle.
assign last_packet_beat = ~sink_is_compressed |
(
burst_uncompress_busy ?
(sink_valid & (burst_uncompress_byte_counter == num_symbols)) :
sink_valid & (sink_byte_cnt == num_symbols)
);
always @(posedge clk or posedge reset) begin
if (reset) begin
burst_uncompress_busy <= '0;
burst_uncompress_byte_counter <= '0;
end
else begin
if (source_valid & source_ready & sink_valid) begin
// No matter what the current state, last_packet_beat leads to
// idle.
if (last_packet_beat) begin
burst_uncompress_busy <= '0;
burst_uncompress_byte_counter <= '0;
end
else begin
if (burst_uncompress_busy) begin
burst_uncompress_byte_counter <= burst_uncompress_byte_counter ?
(burst_uncompress_byte_counter - num_symbols) :
(sink_byte_cnt - num_symbols);
end
else begin // not busy, at least one more beat to go
burst_uncompress_byte_counter <= sink_byte_cnt - num_symbols;
// To do: should busy go true for numsymbols-size compressed
// bursts?
burst_uncompress_busy <= '1;
end
end
end
end
end
wire [ADDR_W - 1 : 0 ] addr_width_burstwrap;
reg [ADDR_W - 1 : 0 ] burst_uncompress_address_base;
reg [ADDR_W - 1 : 0] burst_uncompress_address_offset;
wire [63:0] decoded_burstsize_wire;
wire [ADDR_W-1:0] decoded_burstsize;
// The input burstwrap value can be used as a mask against address values,
// but with one caveat: the address width may be (probably is) wider than
// the burstwrap width. The spec says: extend the msb of the burstwrap
// value out over the entire address width (but only if the address width
// actually is wider than the burstwrap width; otherwise it's a 0-width or
// negative range and concatenation multiplier).
assign addr_width_burstwrap[BURSTWRAP_W - 1 : 0] = sink_burstwrap;
generate
if (ADDR_W > BURSTWRAP_W) begin : addr_sign_extend
// Sign-extend, just wires:
assign addr_width_burstwrap[ADDR_W - 1 : BURSTWRAP_W] =
{(ADDR_W - BURSTWRAP_W) {sink_burstwrap[BURSTWRAP_W - 1]}};
end
endgenerate
always @(posedge clk or posedge reset) begin
if (reset) begin
burst_uncompress_address_base <= '0;
end
else if (first_packet_beat & source_ready) begin
burst_uncompress_address_base <= sink_addr & ~addr_width_burstwrap;
end
end
assign decoded_burstsize_wire = bytes_in_transfer(sink_burstsize); //expand it to 64 bits
assign decoded_burstsize = decoded_burstsize_wire[ADDR_W-1:0]; //then take the width that is needed
wire [ADDR_W - 1 : 0] p1_burst_uncompress_address_offset =
(
(first_packet_beat ?
sink_addr :
burst_uncompress_address_offset) + decoded_burstsize
) &
addr_width_burstwrap;
always @(posedge clk or posedge reset) begin
if (reset) begin
burst_uncompress_address_offset <= '0;
end
else begin
if (source_ready & source_valid) begin
burst_uncompress_address_offset <= p1_burst_uncompress_address_offset;
// if (first_packet_beat) begin
// burst_uncompress_address_offset <=
// (sink_addr + num_symbols) & addr_width_burstwrap;
// end
// else begin
// burst_uncompress_address_offset <=
// (burst_uncompress_address_offset + num_symbols) & addr_width_burstwrap;
// end
end
end
end
// On the first packet beat, send the input address out unchanged,
// while values are computed/registered for 2nd and subsequent beats.
assign source_addr = first_packet_beat ? sink_addr :
burst_uncompress_address_base | burst_uncompress_address_offset;
assign source_burstwrap = sink_burstwrap;
assign source_burstsize = sink_burstsize;
//-------------------------------------------------------------------
// A single (compressed) read burst will have sop/eop in the same beat.
// A sequence of read sub-bursts emitted by a burst adapter in response to a
// single read burst will have sop on the first sub-burst, eop on the last.
// Assert eop only upon (sink_endofpacket & last_packet_beat) to preserve
// packet conservation.
assign source_startofpacket = sink_startofpacket & ~burst_uncompress_busy;
assign source_endofpacket = sink_endofpacket & last_packet_beat;
assign sink_ready = source_valid & source_ready & last_packet_beat;
// This is correct for the slave agent usage, but won't always be true in the
// width adapter. To do: add an "please uncompress" input, and use it to
// pass-through or modify, and set source_is_compressed accordingly.
assign source_is_compressed = 1'b0;
endmodule
|
module cpu_sys_rsp_xbar_demux_001
(
// -------------------
// Sink
// -------------------
input [1-1 : 0] sink_valid,
input [90-1 : 0] sink_data, // ST_DATA_W=90
input [5-1 : 0] sink_channel, // ST_CHANNEL_W=5
input sink_startofpacket,
input sink_endofpacket,
output sink_ready,
// -------------------
// Sources
// -------------------
output reg src0_valid,
output reg [90-1 : 0] src0_data, // ST_DATA_W=90
output reg [5-1 : 0] src0_channel, // ST_CHANNEL_W=5
output reg src0_startofpacket,
output reg src0_endofpacket,
input src0_ready,
// -------------------
// Clock & Reset
// -------------------
(*altera_attribute = "-name MESSAGE_DISABLE 15610" *) // setting message suppression on clk
input clk,
(*altera_attribute = "-name MESSAGE_DISABLE 15610" *) // setting message suppression on reset
input reset
);
localparam NUM_OUTPUTS = 1;
wire [NUM_OUTPUTS - 1 : 0] ready_vector;
// -------------------
// Demux
// -------------------
always @* begin
src0_data = sink_data;
src0_startofpacket = sink_startofpacket;
src0_endofpacket = sink_endofpacket;
src0_channel = sink_channel >> NUM_OUTPUTS;
src0_valid = sink_channel[0] && sink_valid;
end
// -------------------
// Backpressure
// -------------------
assign ready_vector[0] = src0_ready;
assign sink_ready = |(sink_channel & {{4{1'b0}},{ready_vector[NUM_OUTPUTS - 1 : 0]}});
endmodule
|
module cpu_sys_id_router_default_decode
#(
parameter DEFAULT_CHANNEL = 0,
DEFAULT_WR_CHANNEL = -1,
DEFAULT_RD_CHANNEL = -1,
DEFAULT_DESTID = 0
)
(output [79 - 77 : 0] default_destination_id,
output [5-1 : 0] default_wr_channel,
output [5-1 : 0] default_rd_channel,
output [5-1 : 0] default_src_channel
);
assign default_destination_id =
DEFAULT_DESTID[79 - 77 : 0];
generate begin : default_decode
if (DEFAULT_CHANNEL == -1) begin
assign default_src_channel = '0;
end
else begin
assign default_src_channel = 5'b1 << DEFAULT_CHANNEL;
end
end
endgenerate
generate begin : default_decode_rw
if (DEFAULT_RD_CHANNEL == -1) begin
assign default_wr_channel = '0;
assign default_rd_channel = '0;
end
else begin
assign default_wr_channel = 5'b1 << DEFAULT_WR_CHANNEL;
assign default_rd_channel = 5'b1 << DEFAULT_RD_CHANNEL;
end
end
endgenerate
endmodule
|
module cpu_sys_id_router
(
// -------------------
// Clock & Reset
// -------------------
input clk,
input reset,
// -------------------
// Command Sink (Input)
// -------------------
input sink_valid,
input [90-1 : 0] sink_data,
input sink_startofpacket,
input sink_endofpacket,
output sink_ready,
// -------------------
// Command Source (Output)
// -------------------
output src_valid,
output reg [90-1 : 0] src_data,
output reg [5-1 : 0] src_channel,
output src_startofpacket,
output src_endofpacket,
input src_ready
);
// -------------------------------------------------------
// Local parameters and variables
// -------------------------------------------------------
localparam PKT_ADDR_H = 52;
localparam PKT_ADDR_L = 36;
localparam PKT_DEST_ID_H = 79;
localparam PKT_DEST_ID_L = 77;
localparam PKT_PROTECTION_H = 83;
localparam PKT_PROTECTION_L = 81;
localparam ST_DATA_W = 90;
localparam ST_CHANNEL_W = 5;
localparam DECODER_TYPE = 1;
localparam PKT_TRANS_WRITE = 55;
localparam PKT_TRANS_READ = 56;
localparam PKT_ADDR_W = PKT_ADDR_H-PKT_ADDR_L + 1;
localparam PKT_DEST_ID_W = PKT_DEST_ID_H-PKT_DEST_ID_L + 1;
// -------------------------------------------------------
// Figure out the number of bits to mask off for each slave span
// during address decoding
// -------------------------------------------------------
// -------------------------------------------------------
// Work out which address bits are significant based on the
// address range of the slaves. If the required width is too
// large or too small, we use the address field width instead.
// -------------------------------------------------------
localparam ADDR_RANGE = 64'h0;
localparam RANGE_ADDR_WIDTH = log2ceil(ADDR_RANGE);
localparam OPTIMIZED_ADDR_H = (RANGE_ADDR_WIDTH > PKT_ADDR_W) ||
(RANGE_ADDR_WIDTH == 0) ?
PKT_ADDR_H :
PKT_ADDR_L + RANGE_ADDR_WIDTH - 1;
localparam RG = RANGE_ADDR_WIDTH;
reg [PKT_DEST_ID_W-1 : 0] destid;
// -------------------------------------------------------
// Pass almost everything through, untouched
// -------------------------------------------------------
assign sink_ready = src_ready;
assign src_valid = sink_valid;
assign src_startofpacket = sink_startofpacket;
assign src_endofpacket = sink_endofpacket;
wire [PKT_DEST_ID_W-1:0] default_destid;
wire [5-1 : 0] default_src_channel;
cpu_sys_id_router_default_decode the_default_decode(
.default_destination_id (default_destid),
.default_wr_channel (),
.default_rd_channel (),
.default_src_channel (default_src_channel)
);
always @* begin
src_data = sink_data;
src_channel = default_src_channel;
// --------------------------------------------------
// DestinationID Decoder
// Sets the channel based on the destination ID.
// --------------------------------------------------
destid = sink_data[PKT_DEST_ID_H : PKT_DEST_ID_L];
if (destid == 0 ) begin
src_channel = 5'b01;
end
if (destid == 1 ) begin
src_channel = 5'b10;
end
end
// --------------------------------------------------
// Ceil(log2()) function
// --------------------------------------------------
function integer log2ceil;
input reg[65:0] val;
reg [65:0] i;
begin
i = 1;
log2ceil = 0;
while (i < val) begin
log2ceil = log2ceil + 1;
i = i << 1;
end
end
endfunction
endmodule
|
module cpu_sys_cmd_xbar_demux
(
// -------------------
// Sink
// -------------------
input [1-1 : 0] sink_valid,
input [90-1 : 0] sink_data, // ST_DATA_W=90
input [5-1 : 0] sink_channel, // ST_CHANNEL_W=5
input sink_startofpacket,
input sink_endofpacket,
output sink_ready,
// -------------------
// Sources
// -------------------
output reg src0_valid,
output reg [90-1 : 0] src0_data, // ST_DATA_W=90
output reg [5-1 : 0] src0_channel, // ST_CHANNEL_W=5
output reg src0_startofpacket,
output reg src0_endofpacket,
input src0_ready,
output reg src1_valid,
output reg [90-1 : 0] src1_data, // ST_DATA_W=90
output reg [5-1 : 0] src1_channel, // ST_CHANNEL_W=5
output reg src1_startofpacket,
output reg src1_endofpacket,
input src1_ready,
output reg src2_valid,
output reg [90-1 : 0] src2_data, // ST_DATA_W=90
output reg [5-1 : 0] src2_channel, // ST_CHANNEL_W=5
output reg src2_startofpacket,
output reg src2_endofpacket,
input src2_ready,
output reg src3_valid,
output reg [90-1 : 0] src3_data, // ST_DATA_W=90
output reg [5-1 : 0] src3_channel, // ST_CHANNEL_W=5
output reg src3_startofpacket,
output reg src3_endofpacket,
input src3_ready,
output reg src4_valid,
output reg [90-1 : 0] src4_data, // ST_DATA_W=90
output reg [5-1 : 0] src4_channel, // ST_CHANNEL_W=5
output reg src4_startofpacket,
output reg src4_endofpacket,
input src4_ready,
// -------------------
// Clock & Reset
// -------------------
(*altera_attribute = "-name MESSAGE_DISABLE 15610" *) // setting message suppression on clk
input clk,
(*altera_attribute = "-name MESSAGE_DISABLE 15610" *) // setting message suppression on reset
input reset
);
localparam NUM_OUTPUTS = 5;
wire [NUM_OUTPUTS - 1 : 0] ready_vector;
// -------------------
// Demux
// -------------------
always @* begin
src0_data = sink_data;
src0_startofpacket = sink_startofpacket;
src0_endofpacket = sink_endofpacket;
src0_channel = sink_channel >> NUM_OUTPUTS;
src0_valid = sink_channel[0] && sink_valid;
src1_data = sink_data;
src1_startofpacket = sink_startofpacket;
src1_endofpacket = sink_endofpacket;
src1_channel = sink_channel >> NUM_OUTPUTS;
src1_valid = sink_channel[1] && sink_valid;
src2_data = sink_data;
src2_startofpacket = sink_startofpacket;
src2_endofpacket = sink_endofpacket;
src2_channel = sink_channel >> NUM_OUTPUTS;
src2_valid = sink_channel[2] && sink_valid;
src3_data = sink_data;
src3_startofpacket = sink_startofpacket;
src3_endofpacket = sink_endofpacket;
src3_channel = sink_channel >> NUM_OUTPUTS;
src3_valid = sink_channel[3] && sink_valid;
src4_data = sink_data;
src4_startofpacket = sink_startofpacket;
src4_endofpacket = sink_endofpacket;
src4_channel = sink_channel >> NUM_OUTPUTS;
src4_valid = sink_channel[4] && sink_valid;
end
// -------------------
// Backpressure
// -------------------
assign ready_vector[0] = src0_ready;
assign ready_vector[1] = src1_ready;
assign ready_vector[2] = src2_ready;
assign ready_vector[3] = src3_ready;
assign ready_vector[4] = src4_ready;
assign sink_ready = |(sink_channel & ready_vector);
endmodule
|
module cpu_sys_cmd_xbar_demux_001
(
// -------------------
// Sink
// -------------------
input [1-1 : 0] sink_valid,
input [90-1 : 0] sink_data, // ST_DATA_W=90
input [5-1 : 0] sink_channel, // ST_CHANNEL_W=5
input sink_startofpacket,
input sink_endofpacket,
output sink_ready,
// -------------------
// Sources
// -------------------
output reg src0_valid,
output reg [90-1 : 0] src0_data, // ST_DATA_W=90
output reg [5-1 : 0] src0_channel, // ST_CHANNEL_W=5
output reg src0_startofpacket,
output reg src0_endofpacket,
input src0_ready,
output reg src1_valid,
output reg [90-1 : 0] src1_data, // ST_DATA_W=90
output reg [5-1 : 0] src1_channel, // ST_CHANNEL_W=5
output reg src1_startofpacket,
output reg src1_endofpacket,
input src1_ready,
// -------------------
// Clock & Reset
// -------------------
(*altera_attribute = "-name MESSAGE_DISABLE 15610" *) // setting message suppression on clk
input clk,
(*altera_attribute = "-name MESSAGE_DISABLE 15610" *) // setting message suppression on reset
input reset
);
localparam NUM_OUTPUTS = 2;
wire [NUM_OUTPUTS - 1 : 0] ready_vector;
// -------------------
// Demux
// -------------------
always @* begin
src0_data = sink_data;
src0_startofpacket = sink_startofpacket;
src0_endofpacket = sink_endofpacket;
src0_channel = sink_channel >> NUM_OUTPUTS;
src0_valid = sink_channel[0] && sink_valid;
src1_data = sink_data;
src1_startofpacket = sink_startofpacket;
src1_endofpacket = sink_endofpacket;
src1_channel = sink_channel >> NUM_OUTPUTS;
src1_valid = sink_channel[1] && sink_valid;
end
// -------------------
// Backpressure
// -------------------
assign ready_vector[0] = src0_ready;
assign ready_vector[1] = src1_ready;
assign sink_ready = |(sink_channel & {{3{1'b0}},{ready_vector[NUM_OUTPUTS - 1 : 0]}});
endmodule
|
module cpu_sys_cmd_xbar_mux
(
// ----------------------
// Sinks
// ----------------------
input sink0_valid,
input [90-1 : 0] sink0_data,
input [5-1: 0] sink0_channel,
input sink0_startofpacket,
input sink0_endofpacket,
output sink0_ready,
input sink1_valid,
input [90-1 : 0] sink1_data,
input [5-1: 0] sink1_channel,
input sink1_startofpacket,
input sink1_endofpacket,
output sink1_ready,
// ----------------------
// Source
// ----------------------
output src_valid,
output [90-1 : 0] src_data,
output [5-1 : 0] src_channel,
output src_startofpacket,
output src_endofpacket,
input src_ready,
// ----------------------
// Clock & Reset
// ----------------------
input clk,
input reset
);
localparam PAYLOAD_W = 90 + 5 + 2;
localparam NUM_INPUTS = 2;
localparam SHARE_COUNTER_W = 1;
localparam PIPELINE_ARB = 1;
localparam ST_DATA_W = 90;
localparam ST_CHANNEL_W = 5;
localparam PKT_TRANS_LOCK = 57;
// ------------------------------------------
// Signals
// ------------------------------------------
wire [NUM_INPUTS - 1 : 0] request;
wire [NUM_INPUTS - 1 : 0] valid;
wire [NUM_INPUTS - 1 : 0] grant;
wire [NUM_INPUTS - 1 : 0] next_grant;
reg [NUM_INPUTS - 1 : 0] saved_grant;
reg [PAYLOAD_W - 1 : 0] src_payload;
wire last_cycle;
reg packet_in_progress;
reg update_grant;
wire [PAYLOAD_W - 1 : 0] sink0_payload;
wire [PAYLOAD_W - 1 : 0] sink1_payload;
assign valid[0] = sink0_valid;
assign valid[1] = sink1_valid;
wire [NUM_INPUTS - 1 : 0] eop;
assign eop[0] = sink0_endofpacket;
assign eop[1] = sink1_endofpacket;
// ------------------------------------------
// ------------------------------------------
// Grant Logic & Updates
// ------------------------------------------
// ------------------------------------------
reg [NUM_INPUTS - 1 : 0] lock;
always @* begin
lock[0] = sink0_data[57];
lock[1] = sink1_data[57];
end
reg [NUM_INPUTS - 1 : 0] locked = '0;
always @(posedge clk or posedge reset) begin
if (reset) begin
locked <= '0;
end
else begin
locked <= next_grant & lock;
end
end
assign last_cycle = src_valid & src_ready & src_endofpacket & ~(|(lock & grant));
// ------------------------------------------
// We're working on a packet at any time valid is high, except
// when this is the endofpacket.
// ------------------------------------------
always @(posedge clk or posedge reset) begin
if (reset) begin
packet_in_progress <= 1'b0;
end
else begin
if (src_valid)
packet_in_progress <= 1'b1;
if (last_cycle)
packet_in_progress <= 1'b0;
end
end
// ------------------------------------------
// Shares
//
// Special case: all-equal shares _should_ be optimized into assigning a
// constant to next_grant_share.
// Special case: all-1's shares _should_ result in the share counter
// being optimized away.
// ------------------------------------------
// Input | arb shares | counter load value
// 0 | 1 | 0
// 1 | 1 | 0
wire [SHARE_COUNTER_W - 1 : 0] share_0 = 1'd0;
wire [SHARE_COUNTER_W - 1 : 0] share_1 = 1'd0;
// ------------------------------------------
// Choose the share value corresponding to the grant.
// ------------------------------------------
reg [SHARE_COUNTER_W - 1 : 0] next_grant_share;
always @* begin
next_grant_share =
share_0 & { SHARE_COUNTER_W {next_grant[0]} } |
share_1 & { SHARE_COUNTER_W {next_grant[1]} };
end
// ------------------------------------------
// Flag to indicate first packet of an arb sequence.
// ------------------------------------------
// ------------------------------------------
// Compute the next share-count value.
// ------------------------------------------
reg [SHARE_COUNTER_W - 1 : 0] p1_share_count;
reg [SHARE_COUNTER_W - 1 : 0] share_count;
reg share_count_zero_flag;
always @* begin
// Update the counter, but don't decrement below 0.
p1_share_count = share_count_zero_flag ? '0 : share_count - 1'b1;
end
// ------------------------------------------
// Update the share counter and share-counter=zero flag.
// ------------------------------------------
always @(posedge clk or posedge reset) begin
if (reset) begin
share_count <= '0;
share_count_zero_flag <= 1'b1;
end
else begin
if (update_grant) begin
share_count <= next_grant_share;
share_count_zero_flag <= (next_grant_share == '0);
end
else if (last_cycle) begin
share_count <= p1_share_count;
share_count_zero_flag <= (p1_share_count == '0);
end
end
end
always @* begin
update_grant = 0;
// ------------------------------------------
// The pipeline delays grant by one cycle, so
// we have to calculate the update_grant signal
// one cycle ahead of time.
//
// Possible optimization: omit the first clause
// "if (!packet_in_progress & ~src_valid) ..."
// cost: one idle cycle at the the beginning of each
// grant cycle.
// benefit: save a small amount of logic.
// ------------------------------------------
if (!packet_in_progress & !src_valid)
update_grant = 1;
if (last_cycle && share_count_zero_flag)
update_grant = 1;
end
wire save_grant;
assign save_grant = update_grant;
assign grant = saved_grant;
always @(posedge clk, posedge reset) begin
if (reset)
saved_grant <= '0;
else if (save_grant)
saved_grant <= next_grant;
end
// ------------------------------------------
// ------------------------------------------
// Arbitrator
// ------------------------------------------
// ------------------------------------------
// ------------------------------------------
// Create a request vector that stays high during
// the packet for unpipelined arbitration.
//
// The pipelined arbitration scheme does not require
// request to be held high during the packet.
// ------------------------------------------
reg [NUM_INPUTS - 1 : 0] prev_request;
always @(posedge clk, posedge reset) begin
if (reset)
prev_request <= '0;
else
prev_request <= request & ~(valid & eop);
end
assign request = (PIPELINE_ARB == 1) ? valid | locked :
prev_request | valid | locked;
altera_merlin_arbitrator
#(
.NUM_REQUESTERS(NUM_INPUTS),
.SCHEME ("round-robin"),
.PIPELINE (1)
) arb (
.clk (clk),
.reset (reset),
.request (request),
.grant (next_grant),
.save_top_priority (src_valid),
.increment_top_priority (update_grant)
);
// ------------------------------------------
// ------------------------------------------
// Mux
//
// Implemented as a sum of products.
// ------------------------------------------
// ------------------------------------------
assign sink0_ready = src_ready && grant[0];
assign sink1_ready = src_ready && grant[1];
assign src_valid = |(grant & valid);
always @* begin
src_payload =
sink0_payload & {PAYLOAD_W {grant[0]} } |
sink1_payload & {PAYLOAD_W {grant[1]} };
end
// ------------------------------------------
// Mux Payload Mapping
// ------------------------------------------
assign sink0_payload = {sink0_channel,sink0_data,
sink0_startofpacket,sink0_endofpacket};
assign sink1_payload = {sink1_channel,sink1_data,
sink1_startofpacket,sink1_endofpacket};
assign {src_channel,src_data,src_startofpacket,src_endofpacket} = src_payload;
endmodule
|
module cpu_sys_id_router_001_default_decode
#(
parameter DEFAULT_CHANNEL = 0,
DEFAULT_WR_CHANNEL = -1,
DEFAULT_RD_CHANNEL = -1,
DEFAULT_DESTID = 0
)
(output [79 - 77 : 0] default_destination_id,
output [5-1 : 0] default_wr_channel,
output [5-1 : 0] default_rd_channel,
output [5-1 : 0] default_src_channel
);
assign default_destination_id =
DEFAULT_DESTID[79 - 77 : 0];
generate begin : default_decode
if (DEFAULT_CHANNEL == -1) begin
assign default_src_channel = '0;
end
else begin
assign default_src_channel = 5'b1 << DEFAULT_CHANNEL;
end
end
endgenerate
generate begin : default_decode_rw
if (DEFAULT_RD_CHANNEL == -1) begin
assign default_wr_channel = '0;
assign default_rd_channel = '0;
end
else begin
assign default_wr_channel = 5'b1 << DEFAULT_WR_CHANNEL;
assign default_rd_channel = 5'b1 << DEFAULT_RD_CHANNEL;
end
end
endgenerate
endmodule
|
module cpu_sys_id_router_001
(
// -------------------
// Clock & Reset
// -------------------
input clk,
input reset,
// -------------------
// Command Sink (Input)
// -------------------
input sink_valid,
input [90-1 : 0] sink_data,
input sink_startofpacket,
input sink_endofpacket,
output sink_ready,
// -------------------
// Command Source (Output)
// -------------------
output src_valid,
output reg [90-1 : 0] src_data,
output reg [5-1 : 0] src_channel,
output src_startofpacket,
output src_endofpacket,
input src_ready
);
// -------------------------------------------------------
// Local parameters and variables
// -------------------------------------------------------
localparam PKT_ADDR_H = 52;
localparam PKT_ADDR_L = 36;
localparam PKT_DEST_ID_H = 79;
localparam PKT_DEST_ID_L = 77;
localparam PKT_PROTECTION_H = 83;
localparam PKT_PROTECTION_L = 81;
localparam ST_DATA_W = 90;
localparam ST_CHANNEL_W = 5;
localparam DECODER_TYPE = 1;
localparam PKT_TRANS_WRITE = 55;
localparam PKT_TRANS_READ = 56;
localparam PKT_ADDR_W = PKT_ADDR_H-PKT_ADDR_L + 1;
localparam PKT_DEST_ID_W = PKT_DEST_ID_H-PKT_DEST_ID_L + 1;
// -------------------------------------------------------
// Figure out the number of bits to mask off for each slave span
// during address decoding
// -------------------------------------------------------
// -------------------------------------------------------
// Work out which address bits are significant based on the
// address range of the slaves. If the required width is too
// large or too small, we use the address field width instead.
// -------------------------------------------------------
localparam ADDR_RANGE = 64'h0;
localparam RANGE_ADDR_WIDTH = log2ceil(ADDR_RANGE);
localparam OPTIMIZED_ADDR_H = (RANGE_ADDR_WIDTH > PKT_ADDR_W) ||
(RANGE_ADDR_WIDTH == 0) ?
PKT_ADDR_H :
PKT_ADDR_L + RANGE_ADDR_WIDTH - 1;
localparam RG = RANGE_ADDR_WIDTH;
reg [PKT_DEST_ID_W-1 : 0] destid;
// -------------------------------------------------------
// Pass almost everything through, untouched
// -------------------------------------------------------
assign sink_ready = src_ready;
assign src_valid = sink_valid;
assign src_startofpacket = sink_startofpacket;
assign src_endofpacket = sink_endofpacket;
wire [PKT_DEST_ID_W-1:0] default_destid;
wire [5-1 : 0] default_src_channel;
cpu_sys_id_router_001_default_decode the_default_decode(
.default_destination_id (default_destid),
.default_wr_channel (),
.default_rd_channel (),
.default_src_channel (default_src_channel)
);
always @* begin
src_data = sink_data;
src_channel = default_src_channel;
// --------------------------------------------------
// DestinationID Decoder
// Sets the channel based on the destination ID.
// --------------------------------------------------
destid = sink_data[PKT_DEST_ID_H : PKT_DEST_ID_L];
if (destid == 0 ) begin
src_channel = 5'b1;
end
end
// --------------------------------------------------
// Ceil(log2()) function
// --------------------------------------------------
function integer log2ceil;
input reg[65:0] val;
reg [65:0] i;
begin
i = 1;
log2ceil = 0;
while (i < val) begin
log2ceil = log2ceil + 1;
i = i << 1;
end
end
endfunction
endmodule
|
module cpu_sys_irq_mapper
(
// -------------------
// Clock & Reset
// -------------------
input clk,
input reset,
// -------------------
// IRQ Receivers
// -------------------
// -------------------
// Command Source (Output)
// -------------------
output reg [31 : 0] sender_irq
);
initial sender_irq = 0;
always @* begin
sender_irq = 0;
end
endmodule
|
module cpu_sys_addr_router_001_default_decode
#(
parameter DEFAULT_CHANNEL = 1,
DEFAULT_WR_CHANNEL = -1,
DEFAULT_RD_CHANNEL = -1,
DEFAULT_DESTID = 1
)
(output [79 - 77 : 0] default_destination_id,
output [5-1 : 0] default_wr_channel,
output [5-1 : 0] default_rd_channel,
output [5-1 : 0] default_src_channel
);
assign default_destination_id =
DEFAULT_DESTID[79 - 77 : 0];
generate begin : default_decode
if (DEFAULT_CHANNEL == -1) begin
assign default_src_channel = '0;
end
else begin
assign default_src_channel = 5'b1 << DEFAULT_CHANNEL;
end
end
endgenerate
generate begin : default_decode_rw
if (DEFAULT_RD_CHANNEL == -1) begin
assign default_wr_channel = '0;
assign default_rd_channel = '0;
end
else begin
assign default_wr_channel = 5'b1 << DEFAULT_WR_CHANNEL;
assign default_rd_channel = 5'b1 << DEFAULT_RD_CHANNEL;
end
end
endgenerate
endmodule
|
module cpu_sys_addr_router_001
(
// -------------------
// Clock & Reset
// -------------------
input clk,
input reset,
// -------------------
// Command Sink (Input)
// -------------------
input sink_valid,
input [90-1 : 0] sink_data,
input sink_startofpacket,
input sink_endofpacket,
output sink_ready,
// -------------------
// Command Source (Output)
// -------------------
output src_valid,
output reg [90-1 : 0] src_data,
output reg [5-1 : 0] src_channel,
output src_startofpacket,
output src_endofpacket,
input src_ready
);
// -------------------------------------------------------
// Local parameters and variables
// -------------------------------------------------------
localparam PKT_ADDR_H = 52;
localparam PKT_ADDR_L = 36;
localparam PKT_DEST_ID_H = 79;
localparam PKT_DEST_ID_L = 77;
localparam PKT_PROTECTION_H = 83;
localparam PKT_PROTECTION_L = 81;
localparam ST_DATA_W = 90;
localparam ST_CHANNEL_W = 5;
localparam DECODER_TYPE = 0;
localparam PKT_TRANS_WRITE = 55;
localparam PKT_TRANS_READ = 56;
localparam PKT_ADDR_W = PKT_ADDR_H-PKT_ADDR_L + 1;
localparam PKT_DEST_ID_W = PKT_DEST_ID_H-PKT_DEST_ID_L + 1;
// -------------------------------------------------------
// Figure out the number of bits to mask off for each slave span
// during address decoding
// -------------------------------------------------------
localparam PAD0 = log2ceil(64'h10000 - 64'h8000);
localparam PAD1 = log2ceil(64'h11000 - 64'h10800);
// -------------------------------------------------------
// Work out which address bits are significant based on the
// address range of the slaves. If the required width is too
// large or too small, we use the address field width instead.
// -------------------------------------------------------
localparam ADDR_RANGE = 64'h11000;
localparam RANGE_ADDR_WIDTH = log2ceil(ADDR_RANGE);
localparam OPTIMIZED_ADDR_H = (RANGE_ADDR_WIDTH > PKT_ADDR_W) ||
(RANGE_ADDR_WIDTH == 0) ?
PKT_ADDR_H :
PKT_ADDR_L + RANGE_ADDR_WIDTH - 1;
localparam RG = RANGE_ADDR_WIDTH-1;
wire [PKT_ADDR_W-1 : 0] address = sink_data[OPTIMIZED_ADDR_H : PKT_ADDR_L];
// -------------------------------------------------------
// Pass almost everything through, untouched
// -------------------------------------------------------
assign sink_ready = src_ready;
assign src_valid = sink_valid;
assign src_startofpacket = sink_startofpacket;
assign src_endofpacket = sink_endofpacket;
wire [PKT_DEST_ID_W-1:0] default_destid;
wire [5-1 : 0] default_src_channel;
cpu_sys_addr_router_001_default_decode the_default_decode(
.default_destination_id (default_destid),
.default_wr_channel (),
.default_rd_channel (),
.default_src_channel (default_src_channel)
);
always @* begin
src_data = sink_data;
src_channel = default_src_channel;
src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = default_destid;
// --------------------------------------------------
// Address Decoder
// Sets the channel and destination ID based on the address
// --------------------------------------------------
// ( 0x8000 .. 0x10000 )
if ( {address[RG:PAD0],{PAD0{1'b0}}} == 17'h8000 ) begin
src_channel = 5'b10;
src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 1;
end
// ( 0x10800 .. 0x11000 )
if ( {address[RG:PAD1],{PAD1{1'b0}}} == 17'h10800 ) begin
src_channel = 5'b01;
src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 3;
end
end
// --------------------------------------------------
// Ceil(log2()) function
// --------------------------------------------------
function integer log2ceil;
input reg[65:0] val;
reg [65:0] i;
begin
i = 1;
log2ceil = 0;
while (i < val) begin
log2ceil = log2ceil + 1;
i = i << 1;
end
end
endfunction
endmodule
|
module cpu_sys_rsp_xbar_mux_001
(
// ----------------------
// Sinks
// ----------------------
input sink0_valid,
input [90-1 : 0] sink0_data,
input [5-1: 0] sink0_channel,
input sink0_startofpacket,
input sink0_endofpacket,
output sink0_ready,
input sink1_valid,
input [90-1 : 0] sink1_data,
input [5-1: 0] sink1_channel,
input sink1_startofpacket,
input sink1_endofpacket,
output sink1_ready,
// ----------------------
// Source
// ----------------------
output src_valid,
output [90-1 : 0] src_data,
output [5-1 : 0] src_channel,
output src_startofpacket,
output src_endofpacket,
input src_ready,
// ----------------------
// Clock & Reset
// ----------------------
input clk,
input reset
);
localparam PAYLOAD_W = 90 + 5 + 2;
localparam NUM_INPUTS = 2;
localparam SHARE_COUNTER_W = 1;
localparam PIPELINE_ARB = 0;
localparam ST_DATA_W = 90;
localparam ST_CHANNEL_W = 5;
localparam PKT_TRANS_LOCK = 57;
// ------------------------------------------
// Signals
// ------------------------------------------
wire [NUM_INPUTS - 1 : 0] request;
wire [NUM_INPUTS - 1 : 0] valid;
wire [NUM_INPUTS - 1 : 0] grant;
wire [NUM_INPUTS - 1 : 0] next_grant;
reg [NUM_INPUTS - 1 : 0] saved_grant;
reg [PAYLOAD_W - 1 : 0] src_payload;
wire last_cycle;
reg packet_in_progress;
reg update_grant;
wire [PAYLOAD_W - 1 : 0] sink0_payload;
wire [PAYLOAD_W - 1 : 0] sink1_payload;
assign valid[0] = sink0_valid;
assign valid[1] = sink1_valid;
// ------------------------------------------
// ------------------------------------------
// Grant Logic & Updates
// ------------------------------------------
// ------------------------------------------
reg [NUM_INPUTS - 1 : 0] lock;
always @* begin
lock[0] = sink0_data[57];
lock[1] = sink1_data[57];
end
assign last_cycle = src_valid & src_ready & src_endofpacket & ~(|(lock & grant));
// ------------------------------------------
// We're working on a packet at any time valid is high, except
// when this is the endofpacket.
// ------------------------------------------
always @(posedge clk or posedge reset) begin
if (reset) begin
packet_in_progress <= 1'b0;
end
else begin
if (src_valid)
packet_in_progress <= 1'b1;
if (last_cycle)
packet_in_progress <= 1'b0;
end
end
// ------------------------------------------
// Shares
//
// Special case: all-equal shares _should_ be optimized into assigning a
// constant to next_grant_share.
// Special case: all-1's shares _should_ result in the share counter
// being optimized away.
// ------------------------------------------
// Input | arb shares | counter load value
// 0 | 1 | 0
// 1 | 1 | 0
wire [SHARE_COUNTER_W - 1 : 0] share_0 = 1'd0;
wire [SHARE_COUNTER_W - 1 : 0] share_1 = 1'd0;
// ------------------------------------------
// Choose the share value corresponding to the grant.
// ------------------------------------------
reg [SHARE_COUNTER_W - 1 : 0] next_grant_share;
always @* begin
next_grant_share =
share_0 & { SHARE_COUNTER_W {next_grant[0]} } |
share_1 & { SHARE_COUNTER_W {next_grant[1]} };
end
// ------------------------------------------
// Flag to indicate first packet of an arb sequence.
// ------------------------------------------
wire grant_changed = ~packet_in_progress && !(saved_grant & valid);
reg first_packet_r;
wire first_packet = grant_changed | first_packet_r;
always @(posedge clk or posedge reset) begin
if (reset) begin
first_packet_r <= 1'b0;
end
else begin
if (update_grant)
first_packet_r <= 1'b1;
else if (last_cycle)
first_packet_r <= 1'b0;
else if (grant_changed)
first_packet_r <= 1'b1;
end
end
// ------------------------------------------
// Compute the next share-count value.
// ------------------------------------------
reg [SHARE_COUNTER_W - 1 : 0] p1_share_count;
reg [SHARE_COUNTER_W - 1 : 0] share_count;
reg share_count_zero_flag;
always @* begin
if (first_packet) begin
p1_share_count = next_grant_share;
end
else begin
// Update the counter, but don't decrement below 0.
p1_share_count = share_count_zero_flag ? '0 : share_count - 1'b1;
end
end
// ------------------------------------------
// Update the share counter and share-counter=zero flag.
// ------------------------------------------
always @(posedge clk or posedge reset) begin
if (reset) begin
share_count <= '0;
share_count_zero_flag <= 1'b1;
end
else begin
if (last_cycle) begin
share_count <= p1_share_count;
share_count_zero_flag <= (p1_share_count == '0);
end
end
end
// ------------------------------------------
// For each input, maintain a final_packet signal which goes active for the
// last packet of a full-share packet sequence. Example: if I have 4
// shares and I'm continuously requesting, final_packet is active in the
// 4th packet.
// ------------------------------------------
wire final_packet_0 = 1'b1;
wire final_packet_1 = 1'b1;
// ------------------------------------------
// Concatenate all final_packet signals (wire or reg) into a handy vector.
// ------------------------------------------
wire [NUM_INPUTS - 1 : 0] final_packet = {
final_packet_1,
final_packet_0
};
// ------------------------------------------
// ------------------------------------------
wire p1_done = |(final_packet & grant);
// ------------------------------------------
// Flag for the first cycle of packets within an
// arb sequence
// ------------------------------------------
reg first_cycle;
always @(posedge clk, posedge reset) begin
if (reset)
first_cycle <= 0;
else
first_cycle <= last_cycle && ~p1_done;
end
always @* begin
update_grant = 0;
// ------------------------------------------
// No arbitration pipeline, update grant whenever
// the current arb winner has consumed all shares,
// or all requests are low
// ------------------------------------------
update_grant = (last_cycle && p1_done) || (first_cycle && !valid);
update_grant = last_cycle;
end
wire save_grant;
assign save_grant = 1;
assign grant = next_grant;
always @(posedge clk, posedge reset) begin
if (reset)
saved_grant <= '0;
else if (save_grant)
saved_grant <= next_grant;
end
// ------------------------------------------
// ------------------------------------------
// Arbitrator
// ------------------------------------------
// ------------------------------------------
// ------------------------------------------
// Create a request vector that stays high during
// the packet for unpipelined arbitration.
//
// The pipelined arbitration scheme does not require
// request to be held high during the packet.
// ------------------------------------------
assign request = valid;
altera_merlin_arbitrator
#(
.NUM_REQUESTERS(NUM_INPUTS),
.SCHEME ("no-arb"),
.PIPELINE (0)
) arb (
.clk (clk),
.reset (reset),
.request (request),
.grant (next_grant),
.save_top_priority (src_valid),
.increment_top_priority (update_grant)
);
// ------------------------------------------
// ------------------------------------------
// Mux
//
// Implemented as a sum of products.
// ------------------------------------------
// ------------------------------------------
assign sink0_ready = src_ready && grant[0];
assign sink1_ready = src_ready && grant[1];
assign src_valid = |(grant & valid);
always @* begin
src_payload =
sink0_payload & {PAYLOAD_W {grant[0]} } |
sink1_payload & {PAYLOAD_W {grant[1]} };
end
// ------------------------------------------
// Mux Payload Mapping
// ------------------------------------------
assign sink0_payload = {sink0_channel,sink0_data,
sink0_startofpacket,sink0_endofpacket};
assign sink1_payload = {sink1_channel,sink1_data,
sink1_startofpacket,sink1_endofpacket};
assign {src_channel,src_data,src_startofpacket,src_endofpacket} = src_payload;
endmodule
|
module cpu_sys_addr_router_default_decode
#(
parameter DEFAULT_CHANNEL = 2,
DEFAULT_WR_CHANNEL = -1,
DEFAULT_RD_CHANNEL = -1,
DEFAULT_DESTID = 1
)
(output [79 - 77 : 0] default_destination_id,
output [5-1 : 0] default_wr_channel,
output [5-1 : 0] default_rd_channel,
output [5-1 : 0] default_src_channel
);
assign default_destination_id =
DEFAULT_DESTID[79 - 77 : 0];
generate begin : default_decode
if (DEFAULT_CHANNEL == -1) begin
assign default_src_channel = '0;
end
else begin
assign default_src_channel = 5'b1 << DEFAULT_CHANNEL;
end
end
endgenerate
generate begin : default_decode_rw
if (DEFAULT_RD_CHANNEL == -1) begin
assign default_wr_channel = '0;
assign default_rd_channel = '0;
end
else begin
assign default_wr_channel = 5'b1 << DEFAULT_WR_CHANNEL;
assign default_rd_channel = 5'b1 << DEFAULT_RD_CHANNEL;
end
end
endgenerate
endmodule
|
module cpu_sys_addr_router
(
// -------------------
// Clock & Reset
// -------------------
input clk,
input reset,
// -------------------
// Command Sink (Input)
// -------------------
input sink_valid,
input [90-1 : 0] sink_data,
input sink_startofpacket,
input sink_endofpacket,
output sink_ready,
// -------------------
// Command Source (Output)
// -------------------
output src_valid,
output reg [90-1 : 0] src_data,
output reg [5-1 : 0] src_channel,
output src_startofpacket,
output src_endofpacket,
input src_ready
);
// -------------------------------------------------------
// Local parameters and variables
// -------------------------------------------------------
localparam PKT_ADDR_H = 52;
localparam PKT_ADDR_L = 36;
localparam PKT_DEST_ID_H = 79;
localparam PKT_DEST_ID_L = 77;
localparam PKT_PROTECTION_H = 83;
localparam PKT_PROTECTION_L = 81;
localparam ST_DATA_W = 90;
localparam ST_CHANNEL_W = 5;
localparam DECODER_TYPE = 0;
localparam PKT_TRANS_WRITE = 55;
localparam PKT_TRANS_READ = 56;
localparam PKT_ADDR_W = PKT_ADDR_H-PKT_ADDR_L + 1;
localparam PKT_DEST_ID_W = PKT_DEST_ID_H-PKT_DEST_ID_L + 1;
// -------------------------------------------------------
// Figure out the number of bits to mask off for each slave span
// during address decoding
// -------------------------------------------------------
localparam PAD0 = log2ceil(64'h10000 - 64'h8000);
localparam PAD1 = log2ceil(64'h11000 - 64'h10800);
localparam PAD2 = log2ceil(64'h11020 - 64'h11000);
localparam PAD3 = log2ceil(64'h11030 - 64'h11020);
localparam PAD4 = log2ceil(64'h11038 - 64'h11030);
// -------------------------------------------------------
// Work out which address bits are significant based on the
// address range of the slaves. If the required width is too
// large or too small, we use the address field width instead.
// -------------------------------------------------------
localparam ADDR_RANGE = 64'h11038;
localparam RANGE_ADDR_WIDTH = log2ceil(ADDR_RANGE);
localparam OPTIMIZED_ADDR_H = (RANGE_ADDR_WIDTH > PKT_ADDR_W) ||
(RANGE_ADDR_WIDTH == 0) ?
PKT_ADDR_H :
PKT_ADDR_L + RANGE_ADDR_WIDTH - 1;
localparam RG = RANGE_ADDR_WIDTH-1;
wire [PKT_ADDR_W-1 : 0] address = sink_data[OPTIMIZED_ADDR_H : PKT_ADDR_L];
// -------------------------------------------------------
// Pass almost everything through, untouched
// -------------------------------------------------------
assign sink_ready = src_ready;
assign src_valid = sink_valid;
assign src_startofpacket = sink_startofpacket;
assign src_endofpacket = sink_endofpacket;
wire [PKT_DEST_ID_W-1:0] default_destid;
wire [5-1 : 0] default_src_channel;
cpu_sys_addr_router_default_decode the_default_decode(
.default_destination_id (default_destid),
.default_wr_channel (),
.default_rd_channel (),
.default_src_channel (default_src_channel)
);
always @* begin
src_data = sink_data;
src_channel = default_src_channel;
src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = default_destid;
// --------------------------------------------------
// Address Decoder
// Sets the channel and destination ID based on the address
// --------------------------------------------------
// ( 0x8000 .. 0x10000 )
if ( {address[RG:PAD0],{PAD0{1'b0}}} == 17'h8000 ) begin
src_channel = 5'b00100;
src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 1;
end
// ( 0x10800 .. 0x11000 )
if ( {address[RG:PAD1],{PAD1{1'b0}}} == 17'h10800 ) begin
src_channel = 5'b00001;
src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 3;
end
// ( 0x11000 .. 0x11020 )
if ( {address[RG:PAD2],{PAD2{1'b0}}} == 17'h11000 ) begin
src_channel = 5'b01000;
src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 4;
end
// ( 0x11020 .. 0x11030 )
if ( {address[RG:PAD3],{PAD3{1'b0}}} == 17'h11020 ) begin
src_channel = 5'b00010;
src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 0;
end
// ( 0x11030 .. 0x11038 )
if ( {address[RG:PAD4],{PAD4{1'b0}}} == 17'h11030 ) begin
src_channel = 5'b10000;
src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 2;
end
end
// --------------------------------------------------
// Ceil(log2()) function
// --------------------------------------------------
function integer log2ceil;
input reg[65:0] val;
reg [65:0] i;
begin
i = 1;
log2ceil = 0;
while (i < val) begin
log2ceil = log2ceil + 1;
i = i << 1;
end
end
endfunction
endmodule
|
module SimpleDisplayMemory
#(
parameter DisplayBufferSize = 256
)(
input wire clk,
input wire [31:0] InstAdd, // Address to fetch instruction from
input wire [31:0] DataAdd, // Address to fetch data from
input wire [31:0] MemDataContent,
input wire DataReadEn, // Enables output from memory
input wire DataWriteEn, // Enables writing to memory at end of cur. cycle
input wire MEMTYPE, // Enables writing to memory at end of cur. cycle
output reg [31:0] MemDataOut, // Data from memory
output reg [31:0] MemInstOut, // Instruction from memory
output wire [ASCII_SIZE-1:0] DisplayBuffer [CHARS_VERT-1:0][CHARS_HORZ-1:0]
);
reg [31:0] mem [1023:0];
// Declare an internal flat representation of display memory
reg [ASCII_SIZE-1:0] dispMem [CHARS_VERT*CHARS_HORZ-1:0];
// *Un-flatten* the display memory
genvar x, y, z;
generate
for (x = 0; x < CHARS_VERT; x++) begin
for (y = 0; y < CHARS_HORZ; y++) begin
assign DisplayBuffer[x][y] = dispMem[x*y];
end
end
endgenerate
integer k = 0;
initial begin
mem [0] = 32'h77ff0030;
mem [1] = 32'h77ff0001;
mem [2] = 32'h77ff0001;
mem [3] = 32'h77ff002d;
mem [4] = 32'h77ff002c;
mem [5] = 32'h00000030;
mem [6] = 32'h00000031;
mem [7] = 32'h00000032;
mem [8] = 32'h00000033;
mem [9] = 32'h00000034;
mem [10] = 32'h00000035;
mem [11] = 32'h00000036;
mem [12] = 32'h00000037;
mem [13] = 32'h00000038;
mem [14] = 32'h00000039;
mem [15] = 32'h00000061;
mem [16] = 32'h00000062;
mem [17] = 32'h00000063;
mem [18] = 32'h00000064;
mem [19] = 32'h00000065;
mem [20] = 32'h00000066;
// Push
mem [21] = 32'hc3bd0004;
mem [22] = 32'h673dfffc;
//ANDC
mem [23] = 32'he339000f;
// SHLC
mem [24] = 32'hf3390002;
// LD
mem [25] = 32'h63390014;
// STV
mem [26] = 32'h03380000;
mem [27] = 32'h633dfffc;
mem [28] = 32'hc3bdfffc;
mem [29] = 32'h6ffc0000;
mem [30] = 32'hc3bd0004;
mem [31] = 32'h66fdfffc;
mem [32] = 32'hc3bd0004;
mem [33] = 32'h671dfffc;
mem [34] = 32'hc3bd0004;
mem [35] = 32'h679dfffc;
mem [36] = 32'hc31f001c;
mem [37] = 32'h779fffef;
mem [38] = 32'hf7390004;
mem [39] = 32'hc318fffc;
mem [40] = 32'hd6f80000;
mem [41] = 32'h77f7fffb;
mem [42] = 32'h639dfffc;
mem [43] = 32'hc3bdfffc;
mem [44] = 32'h631dfffc;
mem [45] = 32'hc3bdfffc;
mem [46] = 32'h62fdfffc;
mem [47] = 32'hc3bdfffc;
mem [48] = 32'h6ffc0000;
mem [49] = 32'hc3bf0c00;
mem [50] = 32'hc37f0c00;
mem [51] = 32'hc33f01ea;
mem [52] = 32'h779fffe9;
mem [53] = 32'hc3ff0000;
mem [54] = 32'h77fffffe;
for (k = 0; k < DisplayBufferSize; k = k + 1) begin
dispMem[k] = 8'h00;
end
end
always @(posedge clk) begin
//#1
if (DataWriteEn) begin
if (MEMTYPE) begin
dispMem[DataAdd/4] = MemDataContent;
end else begin
mem[DataAdd/4] = MemDataContent;
end
end
end
always @(mem, DataAdd, InstAdd, MEMTYPE) begin
//#2
MemInstOut = mem[InstAdd/4];
if (MEMTYPE) begin
MemDataOut = dispMem[DataAdd/4];
end else begin
MemDataOut = mem[DataAdd/4];
end
end
endmodule // BasicTestMemory
|
module Processor
#(
parameter RstAddr = 32'h80000000, // Address to jump upon RESET
parameter XAddr = 32'h80000008, // Address to jump upon exception
parameter IllOpAddr = 32'h80000004, // Address to jump upon execution of illegal Op-code
parameter XPReg = 5'b11110, // Register add for storing pc upon exception
parameter DisplayBufferSize = 256 // Bits
)(
input wire clk, // Global clock
input wire RESET, // External RESET input
input wire IRQ, // Interrupt
input wire [ASCII_SIZE-1:0] DisplayBuffer [CHARS_VERT-1:0][CHARS_HORZ-1:0] // Memory output for display
);
wire [31:0] InstAdd; //Address of next instruction to fetch
wire [31:0] InstData; // Instruction fetched from memory
wire [31:0] SextC; // Gets C from Inst and sign extends it
wire WERF; // Write enable for register file
reg [31:0] WD; // Write data for register file
wire [31:0] RD1; // Data from 1st register corresponding to Ra
wire [31:0] RD2; // Data from 2nd register corresponding to Rb
wire [2:0] PCSEL; // Control for mux selecting next PC
wire RA2SEL; // Controls mux selecting add. for 2nd reg in regile
wire ASEL; // Selects input 'A' for ALU
wire BSEL; // Selects input 'B' for ALU
wire [1:0] WDSEL; // Selects WD
wire [5:0] ALUFN; // alu function
wire [31:0] aluRes; // Result from ALU
wire WR; // Write enable for memory
wire WASEL; // Selects write add. for reg file
wire [31:0] MemDataOut; // Output from memory (data)
wire [31:0] a; // Input 'A' to ALU
wire [31:0] b; // Input 'B' to ALU
wire [31:0] Rc; // Add. of C reg
wire [31:0] JT;
wire [31:0] ShftSextC; // 4*SextC
wire [31:0] PcIncr;
wire [31:0] branchOffset;
wire MEMTYPE;
wire Z;
assign Rc = InstData[25:21];
assign SextC = {{16{InstData[15]}}, InstData[15:0]};
assign ShftSextC = SextC << 2;
assign JT = {{RD1[31:2]}, {2'b00}};
assign Z = RD1 == 32'h00000000;
ProgramCounter #(32) pc_inst
(
.RESET(RESET),
.clk(clk),
.PCSEL(PCSEL),
.XAddr(XAddr),
.RstAddr(RstAddr),
.IllOpAddr(IllOpAddr),
.IRQ(IRQ),
.JT(JT&32'hfffffffc),
.ShftSextC(ShftSextC),
.pc_o(InstAdd),
.PcIncr(PcIncr),
.branchOffset(branchOffset)
);
// Connection for ALU using BSEL from CtrlModule
assign a = ASEL ? {{1'b0}, {branchOffset[30:0]}} : RD1;
assign b = BSEL ? SextC : RD2;
Alu alu_inst
(
.alufn(ALUFN),
.a(a),
.b(b),
.alu(aluRes),
.z(),
.v(),
.n()
);
always @(aluRes, InstAdd, PcIncr, MemDataOut, WDSEL) begin
case (WDSEL)
2'b00:
WD = {{InstAdd[31]}, {PcIncr[30:0]}};
2'b01:
WD = aluRes;
2'b10:
WD = MemDataOut;
default:
WD = {32{1'b0}};
endcase // case (WDSEL)
end // always @ (alu, RD, WDSEL)
RegfileModule regFile_inst
(
.clk(clk),
.XPReg(XPReg),
.WASEL(WASEL),
.Ra(InstData[20:16]),
.Rb(InstData[15:11]),
.Rc(InstData[25:21]),
.WERF(WERF),
.RA2SEL(RA2SEL),
.WD(WD),
.RD1(RD1),
.RD2(RD2)
);
SimpleDisplayMemory
#(
256 // Display buffer width
) mem_inst (
.clk(clk),
.InstAdd({{1'b0}, {InstAdd[30:0]}}),
.DataAdd(aluRes),
.MemDataContent(RD2),
.DataReadEn(~WR),
.DataWriteEn(WR),
.MemDataOut(MemDataOut),
.MemInstOut(InstData),
.DisplayBuffer(DisplayBuffer),
.MEMTYPE(MEMTYPE)
);
CtrlLogicModule ctrl_inst
(
.OPCODE(InstData[31:26]),
.RESET(RESET),
.IRQ(IRQ),
.PCSEL(PCSEL),
.RA2SEL(RA2SEL),
.ASEL(ASEL),
.BSEL(BSEL),
.WDSEL(WDSEL),
.ALUFN(ALUFN),
.MEMTYPE(MEMTYPE),
.pc_31(InstAdd[31]),
.WR(WR),
.WERF(WERF),
.WASEL(WASEL),
.Z(Z)
);
endmodule
|
module draw(clk_25M, charBuffer, hSync, vSync, red, green, blue);
input clk_25M;
input [ASCII_SIZE-1:0] charBuffer [CHARS_VERT-1:0][CHARS_HORZ-1:0];
output wire hSync, vSync;
output reg [3-1:0] red, green, blue;
// Text mode parameters
// Opposite order of each array element to keep ROM human readable
reg [0:ASCII_SIZE-1] fontRom [ROM_SIZE-1:0];
wire draw;
wire [32-1:0] hPos, vPos;
hvSyncGen hvInst(clk_25M, hSync, vSync, draw, hPos, vPos);
initial begin
{{red}, {green}, {blue}} = 12'h000;
// Initialise font ROM
$readmemb("/home/suyash/vgaCharRom.bin", fontRom);
end
function getXYPixel;
input [32-1:0] hPos, vPos;
input [0:ASCII_SIZE-1] fontRom [ROM_SIZE-1:0];
input [8-1:0] charBuffer [CHARS_VERT-1:0][CHARS_HORZ-1:0];
getXYPixel = fontRom[(charBuffer[vPos>>4][hPos>>3])<<4 + (vPos&4'b111)][hPos&3'b111];
endfunction // getXYPixel
always @(hPos, vPos) begin
//$display("%d:%d", hPos, vPos);
//{{red}, {green}, {blue}} = {12{getXYPixel(hPos, vPos, fontRom, charBuffer)}};
{{red}, {green}, {blue}} = {12{fontRom[(charBuffer[vPos/16][hPos/8])*16 + (vPos&4'b1111)][hPos&3'b111]}};
//$display("For hPos: %d vPos: %d, got x: %d y: %d %d %d %d", hPos, vPos, charBuffer[vPos>>4][hPos>>3]<<4 + vPos&4'b1111, hPos&3'b111, vPos>>4, hPos>>4, vPos&4'b1111);
end
endmodule // draw
|
module hvSyncGen(clk_25M, hSync, vSync, draw, hPos, vPos);
input clk_25M;
output hSync, vSync, draw;
output [32-1:0] hPos, vPos;
`ifdef DEBUG
parameter FP_H = 48, H = 640, BP_H = 48, RT_H = 96;
parameter FP_V = 33, V = 480, BP_V = 33, RT_V = 2;
`else
parameter FP_H = 16, H = 640, BP_H = 48, RT_H = 96;
parameter FP_V = 10, V = 480, BP_V = 33, RT_V = 2;
`endif
integer hCounter, vCounter;
function genXSync;
input integer counter, fp, disp, bp, rt;
begin : genXSync_block
genXSync = (counter > disp + fp) && (counter < disp + fp + rt)
? 1'b1 : 1'b0;
end
endfunction // function
function genDrawPulse;
input integer hCounter, vCounter;
input integer fp_h, h;
input integer fp_v, v;
if ((hCounter - fp_h < h && hCounter > fp_h) && (vCounter - fp_v < v && vCounter > fp_v)) begin
genDrawPulse = 1'b1;
end else begin
genDrawPulse = 1'b0;
end
endfunction // genDrawPulse
assign hPos = (hCounter < H) ? hCounter : 0;
assign vPos = (vCounter < V) ? vCounter : 0;
assign hSync = genXSync(hCounter, FP_H, H, BP_H, RT_H);
assign vSync = genXSync(vCounter, FP_V, V, BP_V, RT_V);
assign draw = genDrawPulse(hCounter, vCounter, FP_H, H, FP_V, V);
initial begin
hCounter = 0;
vCounter = 0;
end
always @(posedge (hCounter == 0)) begin
vCounter = (vCounter == FP_V + V + BP_V + RT_V) ? 1'b0 : vCounter + 1;
end
always @(posedge clk_25M) begin
hCounter = (hCounter == FP_H + H + BP_H + RT_H) ? 1'b0 : hCounter + 1;
end
endmodule // hvSyncGen
|
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