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module rule_unit(
input logic clk,
input logic rst,
input logic [15:0] src_port,
input logic [15:0] dst_port,
input logic tcp,
input logic [RULE_AWIDTH-1:0] in_rule_data,
input logic in_rule_valid,
output logic [RULE_AWIDTH-1:0] out_rule_data,
output logic rule_pg_match,
output logic [RULE_AWIDTH-1:0] rule_pg_addr,
input rule_pg_t rule_pg_data
);
localparam NUM_PIPES = 16;
// Stats
`ifdef DEBUG
logic [15:0] port_match_cnt;
logic [15:0] no_port_cnt;
logic [15:0] error_cnt;
`endif
logic tcp_r1;
logic tcp_r2;
logic tcp_r3;
logic tcp_r4;
logic [15:0] src_port_r1;
logic [15:0] src_port_r2;
logic [15:0] src_port_r3;
logic [15:0] src_port_r4;
logic [15:0] dst_port_r1;
logic [15:0] dst_port_r2;
logic [15:0] dst_port_r3;
logic [15:0] dst_port_r4;
logic [RULE_AWIDTH-1:0] reg_rule_data;
logic rule_rd;
logic rule_pg_valid;
logic [PG_AWIDTH-1:0] in_pg_0_n;
logic [PG_AWIDTH-1:0] in_pg_1_n;
logic [PG_AWIDTH-1:0] in_pg_2_n;
logic [PG_AWIDTH-1:0] in_pg_3_n;
logic in_pg_valid_n;
logic [PG_AWIDTH-1:0] in_pg_0;
logic [PG_AWIDTH-1:0] in_pg_1;
logic [PG_AWIDTH-1:0] in_pg_2;
logic [PG_AWIDTH-1:0] in_pg_3;
logic in_pg_valid_0;
logic in_pg_valid_1;
logic in_pg_valid_2;
logic in_pg_valid_3;
logic port_match;
logic port_match_0;
logic port_match_1;
logic port_match_2;
logic port_match_3;
logic [PG_AWIDTH-1:0] pg_entry_addr_0;
pg_entry_t pg_entry_data_0;
logic [PG_AWIDTH-1:0] single_addr_0;
logic [15:0] single_data_0;
logic [4:0] range_addr_0;
pg_range_t range_data_0;
logic [4:0] list_addr_0;
pg_list_t list_data_0;
logic [10:0] http_src_addr_0;
logic [31:0] http_src_data_0;
logic [10:0] http_dst_addr_0;
logic [31:0] http_dst_data_0;
logic [PG_AWIDTH-1:0] pg_entry_addr_1;
pg_entry_t pg_entry_data_1;
logic [PG_AWIDTH-1:0] single_addr_1;
logic [15:0] single_data_1;
logic [4:0] range_addr_1;
pg_range_t range_data_1;
logic [4:0] list_addr_1;
pg_list_t list_data_1;
logic [10:0] http_src_addr_1;
logic [31:0] http_src_data_1;
logic [10:0] http_dst_addr_1;
logic [31:0] http_dst_data_1;
logic [PG_AWIDTH-1:0] pg_entry_addr_2;
pg_entry_t pg_entry_data_2;
logic [PG_AWIDTH-1:0] single_addr_2;
logic [15:0] single_data_2;
logic [4:0] range_addr_2;
pg_range_t range_data_2;
logic [4:0] list_addr_2;
pg_list_t list_data_2;
logic [10:0] http_src_addr_2;
logic [31:0] http_src_data_2;
logic [10:0] http_dst_addr_2;
logic [31:0] http_dst_data_2;
logic [PG_AWIDTH-1:0] pg_entry_addr_3;
pg_entry_t pg_entry_data_3;
logic [PG_AWIDTH-1:0] single_addr_3;
logic [15:0] single_data_3;
logic [4:0] range_addr_3;
pg_range_t range_data_3;
logic [4:0] list_addr_3;
pg_list_t list_data_3;
logic [10:0] http_src_addr_3;
logic [31:0] http_src_data_3;
logic [10:0] http_dst_addr_3;
logic [31:0] http_dst_data_3;
assign rule_pg_addr = in_rule_data - 1;
// First stage: index rule2pg table
always @(posedge clk) begin
if (rst) begin
rule_rd <= 0;
end
else begin
// CYCLE 1
// rule2pg table read delay 1
tcp_r1 <= tcp;
src_port_r1 <= src_port;
dst_port_r1 <= dst_port;
rule_rd <= (in_rule_data != 0) & in_rule_valid;
// CYCLE 2
// rule2pg table read delay 2
rule_pg_valid <= rule_rd;
tcp_r2 <= tcp_r1;
src_port_r2 <= src_port_r1;
dst_port_r2 <= dst_port_r1;
// CYCLE 3
// Register URAM outputs
tcp_r3 <= tcp_r2;
src_port_r3 <= src_port_r2;
dst_port_r3 <= dst_port_r2;
in_pg_0_n <= rule_pg_data.pg0;
in_pg_1_n <= rule_pg_data.pg1;
in_pg_2_n <= rule_pg_data.pg2;
in_pg_3_n <= rule_pg_data.pg3;
in_pg_valid_n <= rule_pg_valid;
// CYCLE 4
// Assign each port group
// pg = 0 is treated as invalid pg
tcp_r4 <= tcp_r3;
src_port_r4 <= src_port_r3;
dst_port_r4 <= dst_port_r3;
in_pg_0 <= in_pg_0_n - 1;
in_pg_1 <= in_pg_1_n - 1;
in_pg_2 <= in_pg_2_n - 1;
in_pg_3 <= in_pg_3_n - 1;
in_pg_valid_0 <= in_pg_valid_n & (in_pg_0_n != 0);
in_pg_valid_1 <= in_pg_valid_n & (in_pg_1_n != 0);
in_pg_valid_2 <= in_pg_valid_n & (in_pg_2_n != 0);
in_pg_valid_3 <= in_pg_valid_n & (in_pg_3_n != 0);
end
end
assign port_match = (port_match_0 | port_match_1 |
port_match_2 | port_match_3);
always @(posedge clk) begin
if (rst) begin
rule_pg_match <= 0;
end
else begin
rule_pg_match <= port_match;
end
out_rule_data <= 0;
if (port_match) begin
out_rule_data <= reg_rule_data;
end
end
`ifdef DEBUG
always @(posedge clk) begin
if (rst) begin
port_match_cnt <= 0;
no_port_cnt <= 0;
end
else begin
if (port_match) begin
port_match_cnt <= port_match_cnt + 1;
end
if (reg_rule_data != 0) begin
no_port_cnt <= no_port_cnt + 1;
end
end
end
`endif
hyper_pipe #(
.WIDTH (RULE_AWIDTH),
.NUM_PIPES(NUM_PIPES)
) hp_rule (
.clk(clk),
.din(in_rule_data),
.dout(reg_rule_data)
);
port_unit pg_0 (
.clk (clk),
.rst (rst),
.in_pg (in_pg_0),
.in_pg_valid (in_pg_valid_0),
.src_port (src_port_r4),
.dst_port (dst_port_r4),
.tcp (tcp_r4),
.pg_entry_addr (pg_entry_addr_0),
.pg_entry_data (pg_entry_data_0),
.single_addr (single_addr_0),
.single_data (single_data_0),
.range_addr (range_addr_0),
.range_data (range_data_0),
.list_addr (list_addr_0),
.list_data (list_data_0),
.http_src_addr (http_src_addr_0),
.http_src_data (http_src_data_0),
.http_dst_addr (http_dst_addr_0),
.http_dst_data (http_dst_data_0),
.port_match (port_match_0)
);
port_unit pg_1 (
.clk (clk),
.rst (rst),
.in_pg (in_pg_1),
.in_pg_valid (in_pg_valid_1),
.src_port (src_port_r4),
.dst_port (dst_port_r4),
.tcp (tcp_r4),
.pg_entry_addr (pg_entry_addr_1),
.pg_entry_data (pg_entry_data_1),
.single_addr (single_addr_1),
.single_data (single_data_1),
.range_addr (range_addr_1),
.range_data (range_data_1),
.list_addr (list_addr_1),
.list_data (list_data_1),
.http_src_addr (http_src_addr_1),
.http_src_data (http_src_data_1),
.http_dst_addr (http_dst_addr_1),
.http_dst_data (http_dst_data_1),
.port_match (port_match_1)
);
port_unit pg_2 (
.clk (clk),
.rst (rst),
.in_pg (in_pg_2),
.in_pg_valid (in_pg_valid_2),
.src_port (src_port_r4),
.dst_port (dst_port_r4),
.tcp (tcp_r4),
.pg_entry_addr (pg_entry_addr_2),
.pg_entry_data (pg_entry_data_2),
.single_addr (single_addr_2),
.single_data (single_data_2),
.range_addr (range_addr_2),
.range_data (range_data_2),
.list_addr (list_addr_2),
.list_data (list_data_2),
.http_src_addr (http_src_addr_2),
.http_src_data (http_src_data_2),
.http_dst_addr (http_dst_addr_2),
.http_dst_data (http_dst_data_2),
.port_match (port_match_2)
);
port_unit pg_3 (
.clk (clk),
.rst (rst),
.in_pg (in_pg_3),
.in_pg_valid (in_pg_valid_3),
.src_port (src_port_r4),
.dst_port (dst_port_r4),
.tcp (tcp_r4),
.pg_entry_addr (pg_entry_addr_3),
.pg_entry_data (pg_entry_data_3),
.single_addr (single_addr_3),
.single_data (single_data_3),
.range_addr (range_addr_3),
.range_data (range_data_3),
.list_addr (list_addr_3),
.list_data (list_data_3),
.http_src_addr (http_src_addr_3),
.http_src_data (http_src_data_3),
.http_dst_addr (http_dst_addr_3),
.http_dst_data (http_dst_data_3),
.port_match (port_match_3)
);
rom_2port #(
.DWIDTH(PG_ENTRY_WIDTH),
.AWIDTH(PG_AWIDTH),
.MEM_SIZE(PG_DEPTH),
.INIT_FILE("./memory_init/pg_meta.mif")
)
pg_entry_table_0_1 (
.q_a (pg_entry_data_0),
.q_b (pg_entry_data_1),
.address_a (pg_entry_addr_0),
.address_b (pg_entry_addr_1),
.clock (clk)
);
rom_2port #(
.DWIDTH(PG_ENTRY_WIDTH),
.AWIDTH(PG_AWIDTH),
.MEM_SIZE(PG_DEPTH),
.INIT_FILE("./memory_init/pg_meta.mif")
)
pg_entry_table_2_3 (
.q_a (pg_entry_data_2),
.q_b (pg_entry_data_3),
.address_a (pg_entry_addr_2),
.address_b (pg_entry_addr_3),
.clock (clk)
);
rom_2port #(
.DWIDTH(16),
.AWIDTH(PG_AWIDTH),
.MEM_SIZE(PG_DEPTH),
.INIT_FILE("./memory_init/pg_single_value.mif")
)
single_table_0_1 (
.q_a (single_data_0),
.q_b (single_data_1),
.address_a (single_addr_0),
.address_b (single_addr_1),
.clock (clk)
);
rom_2port #(
.DWIDTH(16),
.AWIDTH(PG_AWIDTH),
.MEM_SIZE(PG_DEPTH),
.INIT_FILE("./memory_init/pg_single_value.mif")
)
single_table_2_3 (
.q_a (single_data_2),
.q_b (single_data_3),
.address_a (single_addr_2),
.address_b (single_addr_3),
.clock (clk)
);
rom_1port_mlab #(
.DWIDTH(PG_RANGE_DWIDTH),
.AWIDTH(PG_RANGE_AWIDTH),
.MEM_SIZE(PG_RANGE_DEPTH),
.INIT_FILE("./memory_init/pg_range.mif")
)
range_table_0 (
.address (range_addr_0),
.clock (clk),
.q (range_data_0)
);
rom_1port_mlab #(
.DWIDTH(PG_RANGE_DWIDTH),
.AWIDTH(PG_RANGE_AWIDTH),
.MEM_SIZE(PG_RANGE_DEPTH),
.INIT_FILE("./memory_init/pg_range.mif")
)
range_table_1 (
.address (range_addr_1),
.clock (clk),
.q (range_data_1)
);
rom_1port_mlab #(
.DWIDTH(PG_RANGE_DWIDTH),
.AWIDTH(PG_RANGE_AWIDTH),
.MEM_SIZE(PG_RANGE_DEPTH),
.INIT_FILE("./memory_init/pg_range.mif")
)
range_table_2 (
.address (range_addr_2),
.clock (clk),
.q (range_data_2)
);
rom_1port_mlab #(
.DWIDTH(PG_RANGE_DWIDTH),
.AWIDTH(PG_RANGE_AWIDTH),
.MEM_SIZE(PG_RANGE_DEPTH),
.INIT_FILE("./memory_init/pg_range.mif")
)
range_table_3 (
.address (range_addr_3),
.clock (clk),
.q (range_data_3)
);
rom_1port_mlab #(
.DWIDTH (PG_LIST_DWIDTH),
.AWIDTH (PG_LIST_AWIDTH),
.MEM_SIZE(PG_LIST_DEPTH),
.INIT_FILE("./memory_init/pg_list.mif")
)
list_table_0 (
.address (list_addr_0),
.clock (clk),
.q (list_data_0)
);
rom_1port_mlab #(
.DWIDTH (PG_LIST_DWIDTH),
.AWIDTH (PG_LIST_AWIDTH),
.MEM_SIZE(PG_LIST_DEPTH),
.INIT_FILE("./memory_init/pg_list.mif")
)
list_table_1 (
.address (list_addr_1),
.clock (clk),
.q (list_data_1)
);
rom_1port_mlab #(
.DWIDTH (PG_LIST_DWIDTH),
.AWIDTH (PG_LIST_AWIDTH),
.MEM_SIZE(PG_LIST_DEPTH),
.INIT_FILE("./memory_init/pg_list.mif")
)
list_table_2 (
.address (list_addr_2),
.clock (clk),
.q (list_data_2)
);
rom_1port_mlab #(
.DWIDTH (PG_LIST_DWIDTH),
.AWIDTH (PG_LIST_AWIDTH),
.MEM_SIZE(PG_LIST_DEPTH),
.INIT_FILE("./memory_init/pg_list.mif")
)
list_table_3 (
.address (list_addr_3),
.clock (clk),
.q (list_data_3)
);
rom_2port #(
.DWIDTH (PG_HTTP_DWIDTH),
.AWIDTH (PG_HTTP_AWIDTH),
.MEM_SIZE(PG_HTTP_DEPTH),
.INIT_FILE("./memory_init/pg_http_src.mif")
)
http_src_table_0_1 (
.q_a (http_src_data_0),
.q_b (http_src_data_1),
.address_a (http_src_addr_0),
.address_b (http_src_addr_1),
.clock (clk)
);
rom_2port #(
.DWIDTH (PG_HTTP_DWIDTH),
.AWIDTH (PG_HTTP_AWIDTH),
.MEM_SIZE(PG_HTTP_DEPTH),
.INIT_FILE("./memory_init/pg_http_src.mif")
)
http_src_table_2_3 (
.q_a (http_src_data_2),
.q_b (http_src_data_3),
.address_a (http_src_addr_2),
.address_b (http_src_addr_3),
.clock (clk)
);
rom_2port #(
.DWIDTH (PG_HTTP_DWIDTH),
.AWIDTH (PG_HTTP_AWIDTH),
.MEM_SIZE(PG_HTTP_DEPTH),
.INIT_FILE("./memory_init/pg_http_dst.mif")
)
http_dst_table_0_1 (
.q_a (http_dst_data_0),
.q_b (http_dst_data_1),
.address_a (http_dst_addr_0),
.address_b (http_dst_addr_1),
.clock (clk)
);
rom_2port #(
.DWIDTH (PG_HTTP_DWIDTH),
.AWIDTH (PG_HTTP_AWIDTH),
.MEM_SIZE(PG_HTTP_DEPTH),
.INIT_FILE("./memory_init/pg_http_dst.mif")
)
http_dst_table_2_3 (
.q_a (http_dst_data_2),
.q_b (http_dst_data_3),
.address_a (http_dst_addr_2),
.address_b (http_dst_addr_3),
.clock (clk)
);
endmodule |
module mul_hash(clk, a, ab0, ab1, ab2, ab3);
input clk;
input[7:0] a;
// 4 terms of multiply
output reg [23:0] ab0;
output reg [23:0] ab1;
output reg [23:0] ab2;
output reg [23:0] ab3;
wire [63:0] b = 64'h0b4e0ef37bc32127;
reg [7:0] a_reg0;
reg [7:0] a_reg1;
reg [7:0] a_reg2;
wire [15:0] b0 = b[15: 0];
wire [15:0] b1 = b[31:16];
wire [15:0] b2 = b[47:32];
wire [15:0] b3 = b[63:48];
reg [23:0] ab0_reg0;
reg [23:0] ab1_reg0;
reg [23:0] ab2_reg0;
reg [23:0] ab3_reg0;
reg [23:0] ab0_reg1;
reg [23:0] ab1_reg1;
reg [23:0] ab2_reg1;
reg [23:0] ab3_reg1;
// Register inputs and outputs
always @ (posedge clk) begin
a_reg0 <= a;
a_reg1 <= a_reg0;
a_reg2 <= a_reg1;
ab0_reg0 <= a_reg2 * b0;
ab1_reg0 <= a_reg2 * b1;
ab2_reg0 <= a_reg2 * b2;
ab3_reg0 <= a_reg2 * b3;
ab0_reg1 <= ab0_reg0;
ab1_reg1 <= ab1_reg0;
ab2_reg1 <= ab2_reg0;
ab3_reg1 <= ab3_reg0;
ab0 <= ab0_reg1;
ab1 <= ab1_reg1;
ab2 <= ab2_reg1;
ab3 <= ab3_reg1;
end
endmodule |
module port_group (
input logic clk,
input logic rst,
// In Meta data
input logic in_meta_valid,
input logic [15:0] src_port,
input logic [15:0] dst_port,
input logic is_tcp,
output logic in_meta_ready,
// In User data
input logic in_usr_sop,
input logic in_usr_eop,
input logic [63:0] in_usr_data,
input logic [2:0] in_usr_empty,
input logic in_usr_valid,
output logic in_usr_ready,
// Memory write port
input logic [2*RULE_PG_WIDTH-1:0] wr_data,
input logic [RULE_AWIDTH-2:0] wr_addr,
input logic wr_en,
// Out User data
output logic [63:0] out_usr_data,
output logic out_usr_valid,
output logic out_usr_sop,
output logic out_usr_eop,
output logic [2:0] out_usr_empty,
input logic out_usr_ready,
//stats
output logic [31:0] no_pg_rule_cnt,
output logic [31:0] pg_rule_cnt
);
// This should be 1 bigger than the NUM_PIPE in rule_unit
localparam NUM_PIPES = 17;
typedef enum {
IDLE,
RULE
} state_t;
state_t state;
logic tcp;
logic [15:0] src_port_r;
logic [15:0] dst_port_r;
logic rule_valid;
logic reg_rule_valid;
logic rule_eop;
logic reg_rule_eop;
logic int_sop;
logic int_eop;
logic [63:0] int_data;
logic int_valid;
logic int_ready;
logic int_almost_full;
logic [1:0] int_cnt;
logic [RULE_AWIDTH-1:0] in_rule_data_0;
logic [RULE_AWIDTH-1:0] out_rule_data_0;
logic rule_pg_match_0;
logic [RULE_AWIDTH-1:0] rule_pg_addr_0;
rule_pg_t rule_pg_data_0;
logic [RULE_AWIDTH-1:0] in_rule_data_1;
logic [RULE_AWIDTH-1:0] out_rule_data_1;
logic rule_pg_match_1;
logic [RULE_AWIDTH-1:0] rule_pg_addr_1;
rule_pg_t rule_pg_data_1;
logic [RULE_AWIDTH-1:0] in_rule_data_2;
logic [RULE_AWIDTH-1:0] out_rule_data_2;
logic rule_pg_match_2;
logic [RULE_AWIDTH-1:0] rule_pg_addr_2;
rule_pg_t rule_pg_data_2;
logic [RULE_AWIDTH-1:0] in_rule_data_3;
logic [RULE_AWIDTH-1:0] out_rule_data_3;
logic rule_pg_match_3;
logic [RULE_AWIDTH-1:0] rule_pg_addr_3;
rule_pg_t rule_pg_data_3;
logic rule_packer_sop;
logic rule_packer_eop;
logic [511:0] rule_packer_data;
logic rule_packer_valid;
logic rule_packer_ready;
logic [5:0] rule_packer_empty;
logic rule_packer_fifo_sop;
logic rule_packer_fifo_eop;
logic [511:0] rule_packer_fifo_data;
logic rule_packer_fifo_valid;
logic rule_packer_fifo_ready;
logic [5:0] rule_packer_fifo_empty;
logic [2*RULE_PG_WIDTH-1:0] wr_data_r;
logic [RULE_AWIDTH-2:0] wr_addr_r;
logic wr_en_r;
//Forward pkt data
assign in_usr_ready = (state == RULE);
always @(posedge clk) begin
if (rst) begin
tcp <= 0;
state <= IDLE;
rule_valid <= 0;
rule_eop <= 0;
in_meta_ready <= 0;
end else begin
case(state)
IDLE: begin
rule_eop <= 0;
rule_valid <= 0;
in_meta_ready <= 0;
if (in_meta_valid & !in_meta_ready & !int_almost_full) begin
state <= RULE;
src_port_r <= src_port;
dst_port_r <= dst_port;
tcp <= is_tcp;
end
end
RULE: begin
if (in_usr_valid) begin
in_rule_data_0 <= in_usr_data[16*0+RULE_AWIDTH-1:16*0];
in_rule_data_1 <= in_usr_data[16*1+RULE_AWIDTH-1:16*1];
in_rule_data_2 <= in_usr_data[16*2+RULE_AWIDTH-1:16*2];
in_rule_data_3 <= in_usr_data[16*3+RULE_AWIDTH-1:16*3];
rule_valid <= 1;
if (in_usr_eop) begin
state <= IDLE;
rule_eop <= 1;
in_meta_ready <= 1;
end
end else begin
rule_valid <= 0;
end
end
endcase
end
end
//Need to re-calculate the sop, as some of rules will be discarded.
assign int_sop = (int_cnt == 0) ? int_valid : 1'b0;
always @(posedge clk) begin
if (rst) begin
int_eop <= 0;
int_valid <= 0;
int_cnt <= 0;
end else begin
int_valid <= 0;
int_eop <= 0;
if (reg_rule_valid) begin
int_eop <= reg_rule_eop;
int_valid <= rule_pg_match_0 | rule_pg_match_1 | rule_pg_match_2 | rule_pg_match_3 | reg_rule_eop;
end
if(int_valid)begin
if(int_eop)begin
int_cnt <= 0;
end else begin
int_cnt <= int_cnt + 1;
end
end
end
int_data[16*0+15:16*0] <= {3'b0,out_rule_data_0};
int_data[16*1+15:16*1] <= {3'b0,out_rule_data_1};
int_data[16*2+15:16*2] <= {3'b0,out_rule_data_2};
int_data[16*3+15:16*3] <= {3'b0,out_rule_data_3};
end
//Stats
always @(posedge clk) begin
if (rst) begin
no_pg_rule_cnt <= 0;
pg_rule_cnt <= 0;
end else begin
if (reg_rule_valid & !reg_rule_eop) begin
no_pg_rule_cnt <= no_pg_rule_cnt + 1;
end
if (int_valid & !int_eop) begin
pg_rule_cnt <= pg_rule_cnt + 1;
end
end
end
always @(posedge clk) begin
wr_data_r <= wr_data;
wr_addr_r <= wr_addr;
wr_en_r <= wr_en;
if (rst)
wr_en_r <= 1'b0;
end
hyper_pipe_rst #(
.WIDTH (1),
.NUM_PIPES(NUM_PIPES)
) hp_rule_valid (
.clk(clk),
.rst(rst),
.din(rule_valid),
.dout(reg_rule_valid)
);
hyper_pipe_rst #(
.WIDTH (1),
.NUM_PIPES(NUM_PIPES)
) hp_rule_eop (
.clk(clk),
.rst(rst),
.din(rule_eop),
.dout(reg_rule_eop)
);
rule_unit rule_unit_0 (
.clk (clk),
.rst (rst),
.src_port (src_port_r),
.dst_port (dst_port_r),
.tcp (tcp),
.in_rule_data (in_rule_data_0),
.in_rule_valid (rule_valid),
.out_rule_data (out_rule_data_0),
.rule_pg_match (rule_pg_match_0),
.rule_pg_addr (rule_pg_addr_0),
.rule_pg_data (rule_pg_data_0)
);
rule_unit rule_unit_1 (
.clk (clk),
.rst (rst),
.src_port (src_port_r),
.dst_port (dst_port_r),
.tcp (tcp),
.in_rule_data (in_rule_data_1),
.in_rule_valid (rule_valid),
.out_rule_data (out_rule_data_1),
.rule_pg_match (rule_pg_match_1),
.rule_pg_addr (rule_pg_addr_1),
.rule_pg_data (rule_pg_data_1)
);
rule_unit rule_unit_2 (
.clk (clk),
.rst (rst),
.src_port (src_port_r),
.dst_port (dst_port_r),
.tcp (tcp),
.in_rule_data (in_rule_data_2),
.in_rule_valid (rule_valid),
.out_rule_data (out_rule_data_2),
.rule_pg_match (rule_pg_match_2),
.rule_pg_addr (rule_pg_addr_2),
.rule_pg_data (rule_pg_data_2)
);
rule_unit rule_unit_3 (
.clk (clk),
.rst (rst),
.src_port (src_port_r),
.dst_port (dst_port_r),
.tcp (tcp),
.in_rule_data (in_rule_data_3),
.in_rule_valid (rule_valid),
.out_rule_data (out_rule_data_3),
.rule_pg_match (rule_pg_match_3),
.rule_pg_addr (rule_pg_addr_3),
.rule_pg_data (rule_pg_data_3)
);
uram_2rw_reg #(
.DWIDTH(RULE_PG_WIDTH),
.AWIDTH(RULE_AWIDTH),
.LWIDTH(2*RULE_PG_WIDTH),
.MEM_SIZE(RULE_DEPTH)
// .INIT_FILE("./memory_init/rule_2_pg.mif")
)
rule2pg_table_0_1 (
.clock (clk),
.en_a (1'b1),
.wr_en_a (wr_en_r),
.address_a (wr_en_r ? {wr_addr_r, 1'b0} : rule_pg_addr_0),
.wr_data_a (wr_data_r),
.q_a (rule_pg_data_0),
.en_b (1'b1),
.wr_en_b (1'b0),
.address_b (rule_pg_addr_1),
.wr_data_b ({2*RULE_PG_WIDTH{1'b0}}),
.q_b (rule_pg_data_1)
);
uram_2rw_reg #(
.DWIDTH(RULE_PG_WIDTH),
.AWIDTH(RULE_AWIDTH),
.LWIDTH(2*RULE_PG_WIDTH),
.MEM_SIZE(RULE_DEPTH)
// .INIT_FILE("./memory_init/rule_2_pg.mif")
)
rule2pg_table_2_3 (
.clock (clk),
.en_a (1'b1),
.wr_en_a (wr_en_r),
.address_a (wr_en_r ? {wr_addr_r, 1'b0} : rule_pg_addr_2),
.wr_data_a (wr_data_r),
.q_a (rule_pg_data_2),
.en_b (1'b1),
.wr_en_b (1'b0),
.address_b (rule_pg_addr_3),
.wr_data_b ({2*RULE_PG_WIDTH{1'b0}}),
.q_b (rule_pg_data_3)
);
//rule FIFO
unified_pkt_fifo #(
.FIFO_NAME ("[port_group] rule_FIFO"),
.MEM_TYPE ("M20K"),
.DUAL_CLOCK (0),
.USE_ALMOST_FULL (1),
.FULL_LEVEL (48),
.SYMBOLS_PER_BEAT (8),
.BITS_PER_SYMBOL (8),
.FIFO_DEPTH (64)
) rule_fifo (
.in_clk (clk),
.in_reset (rst),
.out_clk (),
.out_reset (),
.in_data (int_data),
.in_valid (int_valid),
.in_ready (int_ready),
.in_startofpacket (int_sop),
.in_endofpacket (int_eop),
.in_empty (3'd0),
.out_data (out_usr_data),
.out_valid (out_usr_valid),
.out_ready (out_usr_ready),
.out_startofpacket (out_usr_sop),
.out_endofpacket (out_usr_eop),
.out_empty (out_usr_empty),
.fill_level (),
.almost_full (int_almost_full),
.overflow ()
);
endmodule |
module hashtable(clk,
addr0,addr0_valid,addr1,addr1_valid,
dout0,dout0_valid,dout1,dout1_valid
);
parameter NBITS = 15;
parameter DWIDTH = 16;
parameter MEM_SIZE = 32768;
parameter INIT_FILE = "./hashtable1.mif";
parameter BM_AWIDTH = (NBITS-3);
input clk;
input [NBITS-1:0] addr0;
input addr0_valid;
input [NBITS-1:0] addr1;
input addr1_valid;
output reg [DWIDTH-1:0] dout0;
output reg dout0_valid;
output reg [DWIDTH-1:0] dout1;
output reg dout1_valid;
reg [NBITS-1:0] addr0_r1;
reg [NBITS-1:0] addr1_r1;
reg [NBITS-1:0] addr0_r2;
reg [NBITS-1:0] addr1_r2;
wire [BM_AWIDTH-1:0] bm_addr0;
wire [BM_AWIDTH-1:0] bm_addr1;
wire [2:0] bm_bit0;
wire [2:0] bm_bit1;
reg [2:0] bm_bit0_reg1;
reg [2:0] bm_bit1_reg1;
reg [2:0] bm_bit0_reg2;
reg [2:0] bm_bit1_reg2;
reg out0_valid_reg1;
reg out1_valid_reg1;
reg q0_valid;
reg q1_valid;
wire [7:0] q0;
wire [7:0] q1;
assign bm_addr0 = addr0[NBITS-1:3];
assign bm_addr1 = addr1[NBITS-1:3];
assign bm_bit0 = addr0[2:0];
assign bm_bit1 = addr1[2:0];
always @ (posedge clk) begin
out0_valid_reg1 <= addr0_valid;
out1_valid_reg1 <= addr1_valid;
q0_valid <= out0_valid_reg1;
q1_valid <= out1_valid_reg1;
bm_bit0_reg1 <= bm_bit0;
bm_bit0_reg2 <= bm_bit0_reg1;
bm_bit1_reg1 <= bm_bit1;
bm_bit1_reg2 <= bm_bit1_reg1;
//propogate addresses
addr0_r1 <= addr0;
addr1_r1 <= addr1;
addr0_r2 <= addr0_r1;
addr1_r2 <= addr1_r1;
dout0 <= addr0_r2;
dout1 <= addr1_r2;
//dout0_valid <= q0_valid & (q0[DWIDTH-1]==0);
//dout1_valid <= q1_valid & (q1[DWIDTH-1]==0);
//use bitmap to indicate whether it is a match or not
dout0_valid <= q0_valid & ((q0 >> bm_bit0_reg2) & 1);
dout1_valid <= q1_valid & ((q1 >> bm_bit1_reg2) & 1);
end
rom_2port #(
.DWIDTH(8),
.AWIDTH(BM_AWIDTH),
.MEM_SIZE(MEM_SIZE),
.INIT_FILE(INIT_FILE)
)
rom_2port_inst (
.q_a (q0),
.q_b (q1),
.address_a (bm_addr0),
.address_b (bm_addr1),
.clock (clk)
);
endmodule |
module rule_depacker_64_32 (
input logic clk,
input logic rst,
input logic in_rule_sop,
input logic in_rule_eop,
input logic [2:0] in_rule_empty,
input logic in_rule_valid,
input logic [63:0] in_rule_data,
output logic in_rule_ready,
output logic out_rule_sop,
output logic out_rule_eop,
output logic out_rule_valid,
output logic [31:0] out_rule_data,
output logic [1:0] out_rule_empty,
input logic out_rule_ready
);
typedef enum{
IDLE,
MIDDLE,
LAST
} state_t;
state_t state;
logic [63:0] latch;
logic int_rule_sop;
logic int_rule_eop;
logic int_rule_valid;
logic [31:0] int_rule_data;
logic [1:0] int_rule_empty;
logic int_rule_ready;
logic int_rule_almost_full;
logic int_cnt;
assign int_rule_empty = 0;
always @(posedge clk) begin
if (rst) begin
int_cnt <= 1'b0;
int_rule_valid <= 1'b0;
int_rule_eop <= 1'b0;
int_rule_sop <= 1'b0;
end else begin
in_rule_ready <= 1'b0;
int_rule_valid <= 1'b0;
int_rule_eop <= 1'b0;
int_rule_sop <= 1'b0;
case(state)
IDLE:begin
int_cnt <= 1'b0;
if(!int_rule_almost_full & in_rule_valid)begin
in_rule_ready <= 1'b1;
if(in_rule_eop)begin
state <= LAST;
end else begin
latch <= in_rule_data;
state <= MIDDLE;
end
end
end
MIDDLE:begin
case(int_cnt)
1'b0:begin
if(latch[31:0]!=0)begin
int_rule_valid <= 1'b1;
int_rule_data <= latch[31:0];
end
end
1'b1:begin
if(latch[63:32]!=0)begin
int_rule_valid <= 1'b1;
int_rule_data <= latch[63:32];
end
state <= IDLE;
end
endcase
int_cnt <= int_cnt + 1'b1;
end
LAST:begin
int_rule_valid <= 1'b1;
int_rule_eop <= 1'b1;
int_rule_data <= 0;
int_rule_sop <= in_rule_sop;
state <= IDLE;
end
endcase
end
end
unified_pkt_fifo #(
.FIFO_NAME ("[rule_depacker_32] rule_FIFO"),
.MEM_TYPE ("M20K"),
.DUAL_CLOCK (0),
.FULL_LEVEL (48),
.SYMBOLS_PER_BEAT (4),
.BITS_PER_SYMBOL (8),
.FIFO_DEPTH (64)
) rule_fifo (
.in_clk (clk),
.in_reset (rst),
.out_clk (),
.out_reset (),
.in_data (int_rule_data),
.in_valid (int_rule_valid),
.in_ready (int_rule_ready),
.in_startofpacket (int_rule_sop),
.in_endofpacket (int_rule_eop),
.in_empty (int_rule_empty),
.out_data (out_rule_data),
.out_valid (out_rule_valid),
.out_ready (out_rule_ready),
.out_startofpacket (out_rule_sop),
.out_endofpacket (out_rule_eop),
.out_empty (out_rule_empty),
.fill_level (),
.almost_full (int_rule_almost_full),
.overflow ()
);
endmodule |
module reduction_2t1(
input clk,
input rst,
input rule_s_t in_data_0,
input in_valid_0,
output logic in_ready_0,
input rule_s_t in_data_1,
input in_valid_1,
output logic in_ready_1,
output rule_s_t out_data,
output logic out_valid,
input out_ready
);
localparam FIFO_DEPTH = 32;
localparam FULL_LEVEL = 20;
logic [1:0] req;
logic [1:0] grant;
logic all_last;
logic same_data;
rule_s_t cache_0;
rule_s_t cache_1;
logic cache_valid_0;
logic cache_valid_1;
logic not_cached_0;
logic not_cached_1;
logic [31:0] int_csr_readdata;
logic int_almost_full;
rule_s_t int_data;
logic int_valid;
logic int_ready;
typedef enum{
SYNC,
MERGE,
MERGE_CACHE,
ARB
} state_t;
state_t state;
//When both inputs are the "last" empty rule
assign all_last = in_data_0.last & in_data_1.last & in_valid_0 & in_valid_1;
//When the inputs are same with each other, if one is last the other is not,
//it doesn't count
assign same_data = (in_data_0 == in_data_1) & in_valid_0 & in_valid_1;
//When the inputs are same as cached data
assign cached_0 = (in_data_0 == cache_0) & in_valid_0 & cache_valid_0;
assign cached_1 = (in_data_1 == cache_1) & in_valid_1 & cache_valid_1;
//state transition
always@(*)begin
state = ARB;
if(all_last)begin
state = SYNC;
end else if (same_data) begin
if(cached_0 | cached_1)begin
state = MERGE_CACHE;
end else begin
state = MERGE;
end
end else begin
state = ARB;
end
end
//Generate request and deq signals
always@(*)begin
req = 0;
in_ready_0 = 1'b0;
in_ready_1 = 1'b0;
case(state)
SYNC:begin
in_ready_0 = !int_almost_full;
in_ready_1 = !int_almost_full;
end
MERGE:begin
in_ready_0 = !int_almost_full;
in_ready_1 = !int_almost_full;
end
MERGE_CACHE:begin
in_ready_0 = 1'b1;
in_ready_1 = 1'b1;
end
ARB:begin
req[0] = in_valid_0 & !in_data_0.last & !cached_0 & !int_almost_full;
req[1] = in_valid_1 & !in_data_1.last & !cached_1 & !int_almost_full;
in_ready_0 = grant[0] | cached_0;
in_ready_1 = grant[1] | cached_1;
end
endcase
end
//Enqueue data, update cache
always@(posedge clk)begin
if(rst)begin
int_valid <= 1'b0;
int_data <= 0;
cache_valid_0 <= 1'b0;
cache_valid_1 <= 1'b0;
cache_0 <= 0;
cache_1 <= 0;
end else begin
int_valid <= 0;
case(state)
SYNC:begin
int_valid <= !int_almost_full;
int_data <= in_data_0;
//clean cache
cache_0 <= 0;
cache_1 <= 0;
cache_valid_0 <= 1'b0;
cache_valid_1 <= 1'b0;
end
MERGE:begin
int_valid <= !int_almost_full;
int_data <= in_data_0;
//update 0 cache
cache_0 <= in_data_0;
cache_valid_0 <= 1'b1;
end
MERGE_CACHE:begin
//does not generate any data for downstream
//does not affect cache
int_valid <= 1'b0;
end
ARB:begin
int_valid <= grant[0] | grant[1];
int_data <= grant[0] ? in_data_0 : in_data_1;
//update cache when either input is granted
if(grant[0])begin
cache_valid_0 <= 1'b1;
cache_0 <= in_data_0;
end
if(grant[1])begin
cache_valid_1 <= 1'b1;
cache_1 <= in_data_1;
end
end
endcase
end
end
unified_fifo #(
.FIFO_NAME ("[fast_pattern] reduction_2t1_FIFO"),
.MEM_TYPE ("MLAB"),
.DUAL_CLOCK (0),
.USE_ALMOST_FULL (1),
.FULL_LEVEL (FULL_LEVEL),
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (RULE_S_WIDTH),
.FIFO_DEPTH (FIFO_DEPTH)
) output_fifo (
.in_clk (clk),
.in_reset (rst),
.out_clk (),
.out_reset (),
.in_data (int_data),
.in_valid (int_valid),
.in_ready (int_ready),
.out_data (out_data),
.out_valid (out_valid),
.out_ready (out_ready),
.fill_level (int_csr_readdata),
.almost_full (int_almost_full),
.overflow ()
);
rr_arbiter #(
.DWIDTH(2)
)
arb_2_inst(
.clk (clk),
.rst (rst),
.req (req),
.grant (grant)
);
endmodule |
module acc_hash(clk, p,
a0b0, a0b1, a0b2, a0b3,
a1b0, a1b1, a1b2, a1b3,
a2b0, a2b1, a2b2,
a3b0, a3b1, a3b2,
a4b0, a4b1,
a5b0, a5b1,
a6b0,
a7b0);
parameter ANDMSK = 64'hffffffffffffffff;
parameter NBITS = 15;
input clk;
output reg [NBITS-1:0] p;
input [23:0] a0b0;
input [23:0] a0b1;
input [23:0] a0b2;
input [23:0] a0b3;
input [23:0] a1b0;
input [23:0] a1b1;
input [23:0] a1b2;
input [23:0] a1b3;
input [23:0] a2b0;
input [23:0] a2b1;
input [23:0] a2b2;
input [23:0] a3b0;
input [23:0] a3b1;
input [23:0] a3b2;
input [23:0] a4b0;
input [23:0] a4b1;
input [23:0] a5b0;
input [23:0] a5b1;
input [23:0] a6b0;
input [23:0] a7b0;
reg [23:0] msk_a0b0;
reg [23:0] msk_a0b1;
reg [23:0] msk_a0b2;
reg [23:0] msk_a0b3;
reg [23:0] msk_a1b0;
reg [23:0] msk_a1b1;
reg [23:0] msk_a1b2;
reg [23:0] msk_a1b3;
reg [23:0] msk_a2b0;
reg [23:0] msk_a2b1;
reg [23:0] msk_a2b2;
reg [23:0] msk_a3b0;
reg [23:0] msk_a3b1;
reg [23:0] msk_a3b2;
reg [23:0] msk_a4b0;
reg [23:0] msk_a4b1;
reg [23:0] msk_a5b0;
reg [23:0] msk_a5b1;
reg [23:0] msk_a6b0;
reg [23:0] msk_a7b0;
reg [32:0] a01_b0;
reg [32:0] a23_b0;
reg [32:0] a45_b0;
reg [32:0] a67_b0;
reg [32:0] a01_b1;
reg [32:0] a23_b1;
reg [32:0] a45_b1;
reg [32:0] a01_b2;
reg [32:0] a23_b2;
reg [32:0] a01_b3;
reg [33:0] add_a01_b1_a23_b0;
reg [33:0] add_a01_b2_a45_b0;
reg [16:0] add_a01_b3_a23_b2;
reg [16:0] add_a45_b1_a67_b0;
reg [32:0] a01_b0_reg;
reg [32:0] a23_b1_reg;
reg [50:0] sum0_reg;
reg [34:0] sum1_reg;
reg [16:0] sum2_reg;
reg [50:0] half_sum0_reg;
reg [35:0] half_sum1_reg;
reg [64:0] sum;
localparam LSB_BYTES_MASKED = (ANDMSK[63:56]==0) ? 8 :
(ANDMSK[55:48]==0) ? 7 :
(ANDMSK[47:40]==0) ? 6 :
(ANDMSK[39:32]==0) ? 5 :
(ANDMSK[31:24]==0) ? 4 :
(ANDMSK[23:16]==0) ? 3 :
(ANDMSK[15: 8]==0) ? 2 :
(ANDMSK[7 : 0]==0) ? 1 : 0;
// These parameter muxes are resolved in synthesie.
always @ (*) begin
msk_a0b0 = (LSB_BYTES_MASKED>=1) ? 24'd0 : a0b0;
msk_a0b1 = (LSB_BYTES_MASKED>=1) ? 24'd0 : a0b1;
msk_a0b2 = (LSB_BYTES_MASKED>=1) ? 24'd0 : a0b2;
msk_a0b3 = (LSB_BYTES_MASKED>=1) ? 24'd0 : a0b3;
msk_a1b0 = (LSB_BYTES_MASKED>=2) ? 24'd0 : a1b0;
msk_a1b1 = (LSB_BYTES_MASKED>=2) ? 24'd0 : a1b1;
msk_a1b2 = (LSB_BYTES_MASKED>=2) ? 24'd0 : a1b2;
msk_a1b3 = (LSB_BYTES_MASKED>=2) ? 24'd0 : a1b3;
msk_a2b0 = (LSB_BYTES_MASKED>=3) ? 24'd0 : a2b0;
msk_a2b1 = (LSB_BYTES_MASKED>=3) ? 24'd0 : a2b1;
msk_a2b2 = (LSB_BYTES_MASKED>=3) ? 24'd0 : a2b2;
msk_a3b0 = (LSB_BYTES_MASKED>=4) ? 24'd0 : a3b0;
msk_a3b1 = (LSB_BYTES_MASKED>=4) ? 24'd0 : a3b1;
msk_a3b2 = (LSB_BYTES_MASKED>=4) ? 24'd0 : a3b2;
msk_a4b0 = (LSB_BYTES_MASKED>=5) ? 24'd0 : a4b0;
msk_a4b1 = (LSB_BYTES_MASKED>=5) ? 24'd0 : a4b1;
msk_a5b0 = (LSB_BYTES_MASKED>=6) ? 24'd0 : a5b0;
msk_a5b1 = (LSB_BYTES_MASKED>=6) ? 24'd0 : a5b1;
msk_a6b0 = (LSB_BYTES_MASKED>=7) ? 24'd0 : a6b0; // Always non-zero
msk_a7b0 = (LSB_BYTES_MASKED==8) ? 24'd0 : a7b0; // Always non-zero
end
// Addition tree
always @ (posedge clk) begin
// level 1, mergin as into 16-bit values
a01_b0 <= msk_a0b0 + {msk_a1b0, 8'd0};
a23_b0 <= msk_a2b0 + {msk_a3b0, 8'd0};
a45_b0 <= msk_a4b0 + {msk_a5b0, 8'd0};
a67_b0 <= msk_a6b0 + {msk_a7b0, 8'd0};
a01_b1 <= msk_a0b1 + {msk_a1b1, 8'd0};
a23_b1 <= msk_a2b1 + {msk_a3b1, 8'd0};
a45_b1 <= msk_a4b1 + {msk_a5b1, 8'd0};
a01_b2 <= msk_a0b2 + {msk_a1b2, 8'd0};
a23_b2 <= msk_a2b2 + {msk_a3b2, 8'd0};
a01_b3 <= msk_a0b3 + {msk_a1b3, 8'd0};
// Level 2, a01_b3, a23_b2, a45_b1, a67_b0
// are cut short because of final truncation
add_a01_b1_a23_b0 <= a01_b1 + a23_b0;
add_a01_b2_a45_b0 <= a01_b2 + a45_b0;
add_a01_b3_a23_b2 <= a01_b3[15:0] + a23_b2[15:0];
add_a45_b1_a67_b0 <= a45_b1[15:0] + a67_b0[15:0];
a01_b0_reg <= a01_b0;
a23_b1_reg <= a23_b1;
// Level 3
sum0_reg <= (add_a01_b1_a23_b0<<16) + a01_b0_reg;
sum1_reg <= add_a01_b2_a45_b0 + a23_b1_reg;
sum2_reg <= add_a01_b3_a23_b2[15:0] + add_a45_b1_a67_b0[15:0];
// Level 4
half_sum0_reg <= sum0_reg;
half_sum1_reg <= {sum2_reg[15:0], 16'd0} + sum1_reg;
// Final Addition
sum <= half_sum0_reg + {half_sum1_reg[31:0], 32'd0};
// Output selection
p <= sum[63:64-NBITS];
end
endmodule |
module mul_hash(clk,a,p);
input clk;
input[63:0] a;
output reg [63:0] p;
localparam ANDMSK = 64'hdfdfdfdfdfdfdfdf;
wire [63:0] b = 64'h0b4e0ef37bc32127;
reg [63:0] a_reg0;
reg [63:0] a_reg1;
reg [63:0] a_reg2;
(* srl_style = "register" *) reg [63:0] a_reg3;
(* srl_style = "register" *) reg [63:0] a_reg4;
(* srl_style = "register" *) reg [63:0] a_reg5;
(* srl_style = "register" *) reg [63:0] sum_reg0;
(* srl_style = "register" *) reg [63:0] sum_reg1;
(* srl_style = "register" *) reg [63:0] sum_reg2;
always @ (posedge clk) begin
a_reg3 <= a_reg2;
a_reg4 <= a_reg3;
a_reg5 <= a_reg4;
sum_reg0 <= a_reg5 * b;
sum_reg1 <= sum_reg0;
sum_reg2 <= sum_reg1;
end
// Sign and mask handling
reg in_v_reg0;
reg in_v_reg1;
wire signed [63:0] temp;
wire [63:0] after_and;
reg sign;
reg sign_r1;
reg sign_r2;
reg sign_r3;
reg sign_r4;
reg sign_r5;
reg sign_r6;
reg sign_r7;
reg valid;
reg valid_r1;
reg valid_r2;
reg valid_r3;
reg valid_r4;
reg valid_r5;
reg valid_r6;
reg valid_r7;
reg valid_r8;
reg valid_r9;
reg valid_r10;
always @ (posedge clk) begin
a_reg0 <= a;
a_reg1 <= a_reg0 & ANDMSK;
if(a_reg0[63]) begin
sign <= 1;
end else begin
sign <= 0;
end
if(sign) begin
a_reg2 <= ~a_reg1 + 1;
end else begin
a_reg2 <= a_reg1;
end
sign_r1 <= sign;
sign_r2 <= sign_r1;
sign_r3 <= sign_r2;
sign_r4 <= sign_r3;
sign_r5 <= sign_r4;
sign_r6 <= sign_r5;
sign_r7 <= sign_r6;
if(sign_r7) begin
p <= ~sum_reg2 + 1;
end else begin
p <= sum_reg2;
end
end
endmodule |
module rom_2port #(
parameter DWIDTH = 8,
parameter AWIDTH = 8,
parameter MEM_SIZE = (2**AWIDTH),
parameter INIT_FILE = ""
) (
input wire clock,
input wire [AWIDTH-1:0] address_a,
input wire [AWIDTH-1:0] address_b,
output reg [DWIDTH-1:0] q_a,
output reg [DWIDTH-1:0] q_b
);
reg [DWIDTH-1:0] mem [0:(1<<AWIDTH)-1];
reg [AWIDTH-1:0] address_a_r;
reg [AWIDTH-1:0] address_b_r;
always @ (posedge clock) begin
address_a_r <= address_a;
address_b_r <= address_b;
q_a <= mem[address_a_r];
q_b <= mem[address_b_r];
end
initial begin
if (INIT_FILE!="")
$readmemh(INIT_FILE, mem);
end
endmodule |
module uram_2rw_reg #(
parameter DWIDTH = 8,
parameter AWIDTH = 8,
parameter LWIDTH = DWIDTH,
parameter MEM_SIZE = (2**AWIDTH)
) (
input wire clock,
input wire en_a,
input wire [AWIDTH-1:0] address_a,
input wire [LWIDTH-1:0] wr_data_a,
input wire wr_en_a,
output wire [DWIDTH-1:0] q_a,
input wire en_b,
input wire [AWIDTH-1:0] address_b,
input wire [LWIDTH-1:0] wr_data_b,
input wire wr_en_b,
output wire [DWIDTH-1:0] q_b
);
localparam DEPTH = (LWIDTH==DWIDTH) ? AWIDTH :
AWIDTH-$clog2(LWIDTH/DWIDTH);
localparam SEL_BITS = AWIDTH-DEPTH;
(* ram_style = "ultra" *)
reg [LWIDTH-1:0] mem [0:(1<<DEPTH)-1];
reg en_a_r;
reg wr_en_a_r;
reg [AWIDTH-1:0] address_a_r;
reg [LWIDTH-1:0] wr_data_a_r;
reg [LWIDTH-1:0] q_a_r;
reg en_b_r;
reg wr_en_b_r;
reg [AWIDTH-1:0] address_b_r;
reg [LWIDTH-1:0] wr_data_b_r;
reg [LWIDTH-1:0] q_b_r;
// Input register
always @ (posedge clock) begin
en_a_r <= en_a;
wr_en_a_r <= wr_en_a;
address_a_r <= address_a;
wr_data_a_r <= wr_data_a;
en_b_r <= en_b;
wr_en_b_r <= wr_en_b;
address_b_r <= address_b;
wr_data_b_r <= wr_data_b;
end
always @ (posedge clock)
if (en_a_r)
if (wr_en_a_r)
mem[address_a_r[AWIDTH-1:SEL_BITS]] <= wr_data_a_r;
always @ (posedge clock)
if (en_a_r)
if (!wr_en_a_r)
q_a_r <= mem[address_a_r[AWIDTH-1:SEL_BITS]];
always @ (posedge clock)
if (en_b_r)
if (wr_en_b_r)
mem[address_b_r[AWIDTH-1:SEL_BITS]] <= wr_data_b_r;
always @ (posedge clock)
if (en_b_r)
if (!wr_en_b_r)
q_b_r <= mem[address_b_r[AWIDTH-1:SEL_BITS]];
generate
if (DWIDTH==LWIDTH) begin
assign q_a = q_a_r;
assign q_b = q_b_r;
end else begin
reg [SEL_BITS-1:0] sel_a;
reg [SEL_BITS-1:0] sel_b;
always @ (posedge clock) begin
sel_a <= address_a_r[SEL_BITS-1:0];
sel_b <= address_b_r[SEL_BITS-1:0];
end
assign q_a = q_a_r[sel_a*DWIDTH +: DWIDTH];
assign q_b = q_b_r[sel_b*DWIDTH +: DWIDTH];
end
endgenerate
endmodule |
module rom_2port_noreg #(
parameter DWIDTH = 8,
parameter AWIDTH = 8,
parameter MEM_SIZE = (2**AWIDTH),
parameter INIT_FILE = ""
) (
input wire clock,
input wire [AWIDTH-1:0] address_a,
input wire [AWIDTH-1:0] address_b,
output reg [DWIDTH-1:0] q_a,
output reg [DWIDTH-1:0] q_b
);
reg [DWIDTH-1:0] mem [0:(1<<AWIDTH)-1];
always @ (posedge clock) begin
q_a <= mem[address_a];
q_b <= mem[address_b];
end
initial begin
if (INIT_FILE!="")
$readmemh(INIT_FILE, mem);
end
endmodule |
module rom_1port_mlab #(
parameter DWIDTH = 8,
parameter AWIDTH = 8,
parameter MEM_SIZE = (2**AWIDTH),
parameter INIT_FILE = ""
) (
input wire clock,
input wire [AWIDTH-1:0] address,
output reg [DWIDTH-1:0] q
);
reg [DWIDTH-1:0] mem [0:(1<<AWIDTH)-1];
reg [AWIDTH-1:0] address_r;
always @ (posedge clock) begin
address_r <= address;
q <= mem[address_r];
end
initial begin
if (INIT_FILE!="")
$readmemh(INIT_FILE, mem);
end
endmodule |
module singledsp (
input wire clk0,
input wire clk1,
input wire clk2,
input wire [2:0] ena,
input wire [17:0] ax,
input wire [17:0] ay,
output reg [36:0] resulta
);
reg [17:0] ax_r;
reg [17:0] ay_r;
reg [17:0] ax_rr;
reg [17:0] ay_rr;
reg [35:0] mul;
always @ (posedge clk0)
if (ena[0]) begin
ax_r <= ax;
ay_r <= ay;
ax_rr <= ax_r;
ay_rr <= ay_r;
mul <= ax_rr*ay_rr;
resulta <= {1'b0, mul};
end
endmodule |
module dsp (
input wire clk0,
input wire clk1,
input wire clk2,
input wire [2:0] ena,
input wire [17:0] ax,
input wire [17:0] ay,
input wire [17:0] bx,
input wire [17:0] by,
output reg [36:0] resulta
);
reg [17:0] ax_r;
reg [17:0] ay_r;
reg [17:0] bx_r;
reg [17:0] by_r;
reg [35:0] mul_a;
reg [35:0] mul_b;
reg [36:0] sum;
always @ (posedge clk0)
if (ena[0]) begin
ax_r <= ax;
ay_r <= ay;
bx_r <= bx;
by_r <= by;
mul_a <= ax_r*ay_r;
mul_b <= bx_r*by_r;
sum <= mul_a + mul_b;
resulta <= sum;
end
endmodule |
module pigasus_sme_wrapper # (
parameter BYTE_COUNT = 16,
parameter STRB_COUNT = $clog2(BYTE_COUNT)
) (
input wire clk,
input wire rst,
// AXI Stream input
input wire [BYTE_COUNT*8-1:0] s_axis_tdata,
input wire [STRB_COUNT-1:0] s_axis_tempty,
input wire s_axis_tvalid,
input wire s_axis_tfirst,
input wire s_axis_tlast,
output wire s_axis_tready,
input wire [71:0] wr_data,
input wire [16:0] wr_addr,
input wire wr_en,
// Metadata state in
input wire [63:0] preamble_state_in,
input wire [15:0] src_port,
input wire [15:0] dst_port,
input wire meta_valid,
output wire meta_ready,
// Match output
output wire [31:0] match_rules_ID,
output wire match_last,
output wire match_valid,
input wire match_release,
// Metadata state out
output wire [63:0] preamble_state_out,
output reg state_out_valid
);
//////////////////////////////////////////////////////////////////////////
////////////////////// Preprocessing input data //////////////////////
//////////////////////////////////////////////////////////////////////////
reg [BYTE_COUNT*8-1:0] s_axis_tdata_rev_r;
reg [STRB_COUNT-1:0] s_axis_tempty_r;
reg s_axis_tvalid_r;
reg s_axis_tfirst_r;
reg s_axis_tlast_r;
reg [STRB_COUNT-1:0] empty_minus_7;
reg empty_less_than_7;
integer i;
always @ (posedge clk) begin
s_axis_tvalid_r <= (s_axis_tvalid && s_axis_tready) ||
(s_axis_tvalid_r && !s_axis_tready);
// Ready is asserted based on the registerred input data,
// so when extra_r or pigasus ready do not accept the incoming
// data, proper SoP is already in the registerred data, just
// not used for 1 or 2 cycles based on extra_r state;
if (s_axis_tvalid && s_axis_tready) begin
s_axis_tempty_r <= s_axis_tempty;
s_axis_tfirst_r <= s_axis_tfirst;
s_axis_tlast_r <= s_axis_tlast;
empty_less_than_7 <= (s_axis_tempty < 7);
// If more than 7 overflows and becomes empty-7
// If less than 7, becomes the extra cycle tempty
empty_minus_7 <= (BYTE_COUNT-7) + s_axis_tempty;
// Byte swap the input data
for (i=1;i<=BYTE_COUNT;i=i+1)
s_axis_tdata_rev_r[(i-1)*8+:8] <= s_axis_tdata[(BYTE_COUNT-i)*8+:8];
end
if (rst)
s_axis_tvalid_r <= 1'b0;
end
// Metadata state, 56 bits preamble, 1 bit is_tcp,
// 3 bits zero, 1 bit has_preamble, 3 bits zero.
// For the first packet RISCV would set the tcp bit
// and output of this wrapper would fill the has_preamble
// for next packets
wire [55:0] preamble = preamble_state_in[55:0];
wire is_tcp = preamble_state_in[56];
wire has_preamble = preamble_state_in[60];
//////////////////////////////////////////////////////////////////////////
/////// Latching of LSB 7 bytes and check if extra cycle is needed ///////
//////////////////////////////////////////////////////////////////////////
reg [55:0] rest_7;
reg [STRB_COUNT-1:0] rem_empty;
reg extra_cycle;
wire in_pkt_ready;
always @ (posedge clk) begin
if (s_axis_tvalid_r && in_pkt_ready) begin
rest_7 <= s_axis_tdata_rev_r[55:0];
rem_empty <= empty_minus_7;
end
if (s_axis_tvalid_r && s_axis_tlast_r && in_pkt_ready &&
has_preamble && empty_less_than_7)
extra_cycle <= 1'b1;
else if (extra_cycle && in_pkt_ready)
extra_cycle <= 1'b0;
if (rst)
extra_cycle <= 1'b0;
end
//////////////////////////////////////////////////////////////////////////
/////////////////// Add the preamble if necessary ////////////////////
//////////////////////////////////////////////////////////////////////////
reg [BYTE_COUNT*8-1:0] in_pkt_data;
wire [STRB_COUNT-1:0] in_pkt_empty;
wire in_pkt_valid;
wire in_pkt_sop;
wire in_pkt_eop;
assign in_pkt_eop = extra_cycle || (s_axis_tlast_r &&
!(has_preamble && empty_less_than_7));
assign in_pkt_valid = s_axis_tvalid_r || extra_cycle;
assign in_pkt_sop = s_axis_tfirst_r && !extra_cycle;
assign in_pkt_empty = (!has_preamble) ? s_axis_tempty_r :
extra_cycle ? rem_empty :
empty_less_than_7 ? {STRB_COUNT{1'b0}} :
empty_minus_7;
assign s_axis_tready = in_pkt_ready && !extra_cycle;
// Note that if there are non_valid bytes at LSB, first_filter masks the empty
// bytes, so tempty takes care of them, even in case of EOP and empty>=7
always @ (*)
if (has_preamble) begin
if (extra_cycle)
in_pkt_data = {rest_7, {8*(BYTE_COUNT-7){1'b1}}};
else if (s_axis_tfirst_r)
in_pkt_data = {preamble, s_axis_tdata_rev_r[8*BYTE_COUNT-1:56]};
else
in_pkt_data = {rest_7, s_axis_tdata_rev_r[8*BYTE_COUNT-1:56]};
end else begin
in_pkt_data = s_axis_tdata_rev_r;
end
//////////////////////////////////////////////////////////////////////////
////////////////////// processing output state ///////////////////////
//////////////////////////////////////////////////////////////////////////
// Save last 7 bytes. Use 0xFF for fillers so preamble is padded
reg [55:0] last_7;
always @ (posedge clk)
if (s_axis_tlast_r && s_axis_tvalid_r)
if (s_axis_tfirst_r) begin
if (has_preamble)
last_7 <= {preamble, s_axis_tdata_rev_r} >> (8*s_axis_tempty_r);
else
last_7 <= {{56{1'b1}}, s_axis_tdata_rev_r} >> (8*s_axis_tempty_r);
end else begin
last_7 <= {rest_7, s_axis_tdata_rev_r} >> (8*s_axis_tempty_r);
end
// If it's not TCP, no need for preamble. But if it is TCP, output
// would have the has_preamble set
assign preamble_state_out = {preamble_state_in[63:61], is_tcp,
preamble_state_in[59:57], is_tcp, last_7};
always @ (posedge clk)
if (rst)
state_out_valid <= 1'b0;
else
state_out_valid <= s_axis_tlast_r && s_axis_tvalid_r && s_axis_tready;
//////////////////////////////////////////////////////////////////////////
//////////// Pigasus fast pattern matcher and port group /////////////
//////////////////////////////////////////////////////////////////////////
wire [127:0] pigasus_data;
wire pigasus_valid;
wire pigasus_ready;
wire pigasus_sop;
wire pigasus_eop;
wire [3:0] pigasus_empty;
string_matcher pigasus (
.clk(clk),
.rst(rst),
.in_pkt_data(in_pkt_data),
.in_pkt_empty(in_pkt_empty),
.in_pkt_valid(in_pkt_valid),
.in_pkt_sop(in_pkt_sop),
.in_pkt_eop(in_pkt_eop),
.in_pkt_ready(in_pkt_ready),
.wr_data(wr_data[63:0]),
.wr_addr(wr_addr),
.wr_en(wr_en),
.out_usr_data(pigasus_data),
.out_usr_valid(pigasus_valid),
.out_usr_ready(pigasus_ready),
.out_usr_sop(pigasus_sop),
.out_usr_eop(pigasus_eop),
.out_usr_empty(pigasus_empty)
);
wire [63:0] pigasus_data_r;
wire pigasus_valid_r;
wire pigasus_ready_r;
wire pigasus_sop_r;
wire pigasus_eop_r;
wire [2:0] pigasus_empty_r;
rule_depacker_128_64 rule_depacker1_inst (
.clk(clk),
.rst(rst),
.in_rule_sop(pigasus_sop),
.in_rule_eop(pigasus_eop),
.in_rule_data(pigasus_data),
.in_rule_empty(pigasus_empty),
.in_rule_valid(pigasus_valid),
.in_rule_ready(pigasus_ready),
.out_rule_data(pigasus_data_r),
.out_rule_valid(pigasus_valid_r),
.out_rule_ready(pigasus_ready_r),
.out_rule_sop(pigasus_sop_r),
.out_rule_eop(pigasus_eop_r),
.out_rule_empty(pigasus_empty_r)
);
wire [63:0] sme_output;
wire sme_output_valid;
wire sme_output_ready;
wire sme_output_eop;
port_group pg_inst (
.clk(clk),
.rst(rst),
.in_usr_sop(pigasus_sop_r),
.in_usr_eop(pigasus_eop_r),
.in_usr_data(pigasus_data_r),
.in_usr_empty(pigasus_empty_r),
.in_usr_valid(pigasus_valid_r),
.in_usr_ready(pigasus_ready_r),
.in_meta_valid(meta_valid),
.src_port({src_port[7:0], src_port[15:8]}),
.dst_port({dst_port[7:0], dst_port[15:8]}),
.is_tcp(is_tcp),
.in_meta_ready(meta_ready),
.wr_data(wr_data[71:0]),
.wr_addr(wr_addr[11:0]),
.wr_en(wr_en && (wr_addr[16:15]==2'b11)),
.out_usr_data(sme_output),
.out_usr_valid(sme_output_valid),
.out_usr_ready(sme_output_ready),
.out_usr_sop(),
.out_usr_eop(sme_output_eop),
.out_usr_empty(),
.no_pg_rule_cnt(),
.pg_rule_cnt()
);
rule_depacker_64_32 rule_depacker2_inst (
.clk(clk),
.rst(rst),
.in_rule_sop(1'b0),
.in_rule_eop(sme_output_eop),
.in_rule_empty(3'd0),
.in_rule_valid(sme_output_valid),
.in_rule_data(sme_output),
.in_rule_ready(sme_output_ready),
.out_rule_sop(),
.out_rule_eop(match_last),
.out_rule_valid(match_valid),
.out_rule_data(match_rules_ID),
.out_rule_empty(),
.out_rule_ready(match_release)
);
endmodule |
module first_filter(
input clk,
input rst,
input [FP_DWIDTH-1:0] in_data,
input in_valid,
input in_sop,
input in_eop,
input [FP_EWIDTH-1:0] in_empty,
input [63:0] wr_data,
input [12:0] wr_addr,
input wr_en,
output logic [FP_DWIDTH-1:0] out_data,
output logic out_valid
);
logic [12:0] addr0;
logic [63:0] q0;
logic [127:0] temp_st0;
logic [12:0] addr1;
logic [63:0] q1;
logic [127:0] temp_st1;
logic [12:0] addr2;
logic [63:0] q2;
logic [127:0] temp_st2;
logic [12:0] addr3;
logic [63:0] q3;
logic [127:0] temp_st3;
logic [12:0] addr4;
logic [63:0] q4;
logic [127:0] temp_st4;
logic [12:0] addr5;
logic [63:0] q5;
logic [127:0] temp_st5;
logic [12:0] addr6;
logic [63:0] q6;
logic [127:0] temp_st6;
logic [12:0] addr7;
logic [63:0] q7;
logic [127:0] temp_st7;
logic [12:0] addr8;
logic [63:0] q8;
logic [127:0] temp_st8;
logic [12:0] addr9;
logic [63:0] q9;
logic [127:0] temp_st9;
logic [12:0] addr10;
logic [63:0] q10;
logic [127:0] temp_st10;
logic [12:0] addr11;
logic [63:0] q11;
logic [127:0] temp_st11;
logic [12:0] addr12;
logic [63:0] q12;
logic [127:0] temp_st12;
logic [12:0] addr13;
logic [63:0] q13;
logic [127:0] temp_st13;
logic [12:0] addr14;
logic [63:0] q14;
logic [127:0] temp_st14;
logic [12:0] addr15;
logic [63:0] q15;
logic [127:0] temp_st15;
logic [FP_DWIDTH-1:0] in_reg;
logic [63:0] state;
logic [63:0] next_state;
logic in_valid_reg;
logic in_valid_reg_1;
logic [127:0] shiftor0;
logic [127:0] shiftor_state_0;
logic [127:0] shiftor1;
logic [127:0] shiftor_state_1;
logic new_pkt;
logic new_pkt_reg;
logic state_valid;
logic last;
logic last_r;
logic last_r1;
logic [FP_DWIDTH-1:0] mask;
logic [8:0] shift;
logic [63:0] wr_data_r;
logic [12:0] wr_addr_r;
logic wr_en_r;
assign addr0 = in_reg[0*8+12:0*8];
assign addr1 = in_reg[1*8+12:1*8];
assign addr2 = in_reg[2*8+12:2*8];
assign addr3 = in_reg[3*8+12:3*8];
assign addr4 = in_reg[4*8+12:4*8];
assign addr5 = in_reg[5*8+12:5*8];
assign addr6 = in_reg[6*8+12:6*8];
assign addr7 = in_reg[7*8+12:7*8];
assign addr8 = in_reg[8*8+12:8*8];
assign addr9 = in_reg[9*8+12:9*8];
assign addr10 = in_reg[10*8+12:10*8];
assign addr11 = in_reg[11*8+12:11*8];
assign addr12 = in_reg[12*8+12:12*8];
assign addr13 = in_reg[13*8+12:13*8];
assign addr14 = in_reg[14*8+12:14*8];
assign addr15 = last ? {5'b0,in_reg[(15+1)*8-1:15*8]} : {in_data[4:0],in_reg[(15+1)*8-1:15*8]};
assign temp_st0 = q0 << 0*8;
assign temp_st1 = q1 << 1*8;
assign temp_st2 = q2 << 2*8;
assign temp_st3 = q3 << 3*8;
assign temp_st4 = q4 << 4*8;
assign temp_st5 = q5 << 5*8;
assign temp_st6 = q6 << 6*8;
assign temp_st7 = q7 << 7*8;
assign temp_st8 = q8 << 0*8;
assign temp_st9 = q9 << 1*8;
assign temp_st10 = q10 << 2*8;
assign temp_st11 = q11 << 3*8;
assign temp_st12 = q12 << 4*8;
assign temp_st13 = q13 << 5*8;
assign temp_st14 = q14 << 6*8;
assign temp_st15 = q15 << 7*8;
assign shiftor0 = temp_st0 | temp_st1 | temp_st2 | temp_st3 | temp_st4 | temp_st5 | temp_st6 | temp_st7 | 0;
assign shiftor1 = temp_st8 | temp_st9 | temp_st10 | temp_st11 | temp_st12 | temp_st13 | temp_st14 | temp_st15 | 0;
assign shiftor_state_0 = shiftor0 | state;
assign shiftor_state_1 = shiftor1 | shiftor_state_0[127:64];
//assign out_data = {state_high2[63:0],state_high1[63:0],state_high[63:0],state_low[63:0]} | mask;
assign out_data[64*0+63:64*0] = shiftor_state_0[63:0] | mask[64*0+63:64*0];
//assign out_data = {state_high2[63:0],state_high1[63:0],state_high[63:0],state_low[63:0]} | mask;
assign out_data[64*1+63:64*1] = shiftor_state_1[63:0] | mask[64*1+63:64*1];
assign next_state = shiftor_state_1[127:64];
//assign next_state = shiftor_state_1[127:64];
always @ (posedge clk) begin
shift <= (16-in_empty)*8;
last <= in_valid & in_eop;
last_r <= last;
last_r1 <= last_r;
if(last_r)begin
mask <= {FP_DWIDTH-1{1'b1}} << shift;
end else begin
mask <= 0;
end
end
always @ (posedge clk) begin
in_valid_reg <= in_valid;
in_valid_reg_1 <= in_valid_reg;
out_valid <= in_valid_reg_1;
// state update
if (out_valid)begin
if (last_r1) begin
state <= 64'h0003070f1f3f7fff;
end else begin
state <= next_state;
end
end
if (in_valid) begin
in_reg <= in_data;
end
if (rst) begin
state <= 64'h0003070f1f3f7fff;
end
end
always @(posedge clk) begin
wr_data_r <= wr_data;
wr_addr_r <= wr_addr;
wr_en_r <= wr_en;
if (rst)
wr_en_r <= 1'b0;
end
uram_2rw_reg #(
.DWIDTH(64),
.AWIDTH(13),
.MEM_SIZE(8192)
// .INIT_FILE("./memory_init/match_table.mif")
)
match_table_0 (
.clock (clk),
.en_a (1'b1),
.wr_en_a (wr_en_r),
.address_a (wr_en_r ? wr_addr_r : addr0),
.wr_data_a (wr_data_r),
.q_a (q0),
.en_b (1'b1),
.wr_en_b (1'b0),
.address_b (addr1),
.wr_data_b (64'd0),
.q_b (q1)
);
uram_2rw_reg #(
.DWIDTH(64),
.AWIDTH(13),
.MEM_SIZE(8192)
// .INIT_FILE("./memory_init/match_table.mif")
)
match_table_1 (
.clock (clk),
.en_a (1'b1),
.wr_en_a (wr_en_r),
.address_a (wr_en_r ? wr_addr_r : addr2),
.wr_data_a (wr_data_r),
.q_a (q2),
.en_b (1'b1),
.wr_en_b (1'b0),
.address_b (addr3),
.wr_data_b (64'd0),
.q_b (q3)
);
uram_2rw_reg #(
.DWIDTH(64),
.AWIDTH(13),
.MEM_SIZE(8192)
// .INIT_FILE("./memory_init/match_table.mif")
)
match_table_2 (
.clock (clk),
.en_a (1'b1),
.wr_en_a (wr_en_r),
.address_a (wr_en_r ? wr_addr_r : addr4),
.wr_data_a (wr_data_r),
.q_a (q4),
.en_b (1'b1),
.wr_en_b (1'b0),
.address_b (addr5),
.wr_data_b (64'd0),
.q_b (q5)
);
uram_2rw_reg #(
.DWIDTH(64),
.AWIDTH(13),
.MEM_SIZE(8192)
// .INIT_FILE("./memory_init/match_table.mif")
)
match_table_3 (
.clock (clk),
.en_a (1'b1),
.wr_en_a (wr_en_r),
.address_a (wr_en_r ? wr_addr_r : addr6),
.wr_data_a (wr_data_r),
.q_a (q6),
.en_b (1'b1),
.wr_en_b (1'b0),
.address_b (addr7),
.wr_data_b (64'd0),
.q_b (q7)
);
uram_2rw_reg #(
.DWIDTH(64),
.AWIDTH(13),
.MEM_SIZE(8192)
// .INIT_FILE("./memory_init/match_table.mif")
)
match_table_4 (
.clock (clk),
.en_a (1'b1),
.wr_en_a (wr_en_r),
.address_a (wr_en_r ? wr_addr_r : addr8),
.wr_data_a (wr_data_r),
.q_a (q8),
.en_b (1'b1),
.wr_en_b (1'b0),
.address_b (addr9),
.wr_data_b (64'd0),
.q_b (q9)
);
uram_2rw_reg #(
.DWIDTH(64),
.AWIDTH(13),
.MEM_SIZE(8192)
// .INIT_FILE("./memory_init/match_table.mif")
)
match_table_5 (
.clock (clk),
.en_a (1'b1),
.wr_en_a (wr_en_r),
.address_a (wr_en_r ? wr_addr_r : addr10),
.wr_data_a (wr_data_r),
.q_a (q10),
.en_b (1'b1),
.wr_en_b (1'b0),
.address_b (addr11),
.wr_data_b (64'd0),
.q_b (q11)
);
uram_2rw_reg #(
.DWIDTH(64),
.AWIDTH(13),
.MEM_SIZE(8192)
// .INIT_FILE("./memory_init/match_table.mif")
)
match_table_6 (
.clock (clk),
.en_a (1'b1),
.wr_en_a (wr_en_r),
.address_a (wr_en_r ? wr_addr_r : addr12),
.wr_data_a (wr_data_r),
.q_a (q12),
.en_b (1'b1),
.wr_en_b (1'b0),
.address_b (addr13),
.wr_data_b (64'd0),
.q_b (q13)
);
uram_2rw_reg #(
.DWIDTH(64),
.AWIDTH(13),
.MEM_SIZE(8192)
// .INIT_FILE("./memory_init/match_table.mif")
)
match_table_7 (
.clock (clk),
.en_a (1'b1),
.wr_en_a (wr_en_r),
.address_a (wr_en_r ? wr_addr_r : addr14),
.wr_data_a (wr_data_r),
.q_a (q14),
.en_b (1'b1),
.wr_en_b (1'b0),
.address_b (addr15),
.wr_data_b (64'd0),
.q_b (q15)
);
endmodule |
module reduction_2t1(
input clk,
input rst,
input rule_s_t in_data_0,
input in_valid_0,
output logic in_ready_0,
input rule_s_t in_data_1,
input in_valid_1,
output logic in_ready_1,
output rule_s_t out_data,
output logic out_valid,
input out_ready
);
localparam FIFO_DEPTH = 16;
localparam FULL_LEVEL = 12;
logic [1:0] req;
logic [1:0] grant;
logic all_last;
logic same_data;
rule_s_t cache_0;
rule_s_t cache_1;
logic cache_valid_0;
logic cache_valid_1;
logic not_cached_0;
logic not_cached_1;
logic [31:0] int_csr_readdata;
logic int_almost_full;
rule_s_t int_data;
logic int_valid;
logic int_ready;
typedef enum{
SYNC,
MERGE,
MERGE_CACHE,
ARB
} state_t;
state_t state;
//When both inputs are the "last" empty rule
assign all_last = in_data_0.last & in_data_1.last & in_valid_0 & in_valid_1;
//When the inputs are same with each other, if one is last the other is not,
//it doesn't count
assign same_data = (in_data_0 == in_data_1) & in_valid_0 & in_valid_1;
//When the inputs are same as cached data
assign cached_0 = (in_data_0 == cache_0) & in_valid_0 & cache_valid_0;
assign cached_1 = (in_data_1 == cache_1) & in_valid_1 & cache_valid_1;
//state transition
always@(*)begin
state = ARB;
if(all_last)begin
state = SYNC;
end else if (same_data) begin
if(cached_0 | cached_1)begin
state = MERGE_CACHE;
end else begin
state = MERGE;
end
end else begin
state = ARB;
end
end
//Generate request and deq signals
always@(*)begin
req = 0;
in_ready_0 = 1'b0;
in_ready_1 = 1'b0;
case(state)
SYNC:begin
in_ready_0 = !int_almost_full;
in_ready_1 = !int_almost_full;
end
MERGE:begin
in_ready_0 = !int_almost_full;
in_ready_1 = !int_almost_full;
end
MERGE_CACHE:begin
in_ready_0 = 1'b1;
in_ready_1 = 1'b1;
end
ARB:begin
req[0] = in_valid_0 & !in_data_0.last & !cached_0 & !int_almost_full;
req[1] = in_valid_1 & !in_data_1.last & !cached_1 & !int_almost_full;
in_ready_0 = grant[0] | cached_0;
in_ready_1 = grant[1] | cached_1;
end
endcase
end
//Enqueue data, update cache
always@(posedge clk)begin
if(rst)begin
int_valid <= 1'b0;
int_data <= 0;
cache_valid_0 <= 1'b0;
cache_valid_1 <= 1'b0;
cache_0 <= 0;
cache_1 <= 0;
end else begin
int_valid <= 0;
case(state)
SYNC:begin
int_valid <= !int_almost_full;
int_data <= in_data_0;
//clean cache
cache_0 <= 0;
cache_1 <= 0;
cache_valid_0 <= 1'b0;
cache_valid_1 <= 1'b0;
end
MERGE:begin
int_valid <= !int_almost_full;
int_data <= in_data_0;
//update 0 cache
cache_0 <= in_data_0;
cache_valid_0 <= 1'b1;
end
MERGE_CACHE:begin
//does not generate any data for downstream
//does not affect cache
int_valid <= 1'b0;
end
ARB:begin
int_valid <= grant[0] | grant[1];
int_data <= grant[0] ? in_data_0 : in_data_1;
//update cache when either input is granted
if(grant[0])begin
cache_valid_0 <= 1'b1;
cache_0 <= in_data_0;
end
if(grant[1])begin
cache_valid_1 <= 1'b1;
cache_1 <= in_data_1;
end
end
endcase
end
end
unified_fifo #(
.FIFO_NAME ("[fast_pattern] reduction_2t1_FIFO"),
.MEM_TYPE ("MLAB"),
.DUAL_CLOCK (0),
.USE_ALMOST_FULL (1),
.FULL_LEVEL (FULL_LEVEL),
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (RULE_S_WIDTH),
.FIFO_DEPTH (FIFO_DEPTH)
) output_fifo (
.in_clk (clk),
.in_reset (rst),
.out_clk (),
.out_reset (),
.in_data (int_data),
.in_valid (int_valid),
.in_ready (int_ready),
.out_data (out_data),
.out_valid (out_valid),
.out_ready (out_ready),
.fill_level (int_csr_readdata),
.almost_full (int_almost_full),
.overflow ()
);
rr_arbiter #(
.DWIDTH(2)
)
arb_2_inst(
.clk (clk),
.rst (rst),
.req (req),
.grant (grant)
);
endmodule |
module port_unit(
input logic clk,
input logic rst,
input logic [PG_AWIDTH-1:0] in_pg,
input logic in_pg_valid,
input logic [15:0] src_port,
input logic [15:0] dst_port,
input logic tcp,
output logic [PG_AWIDTH-1:0] pg_entry_addr,
input pg_entry_t pg_entry_data,
output logic [PG_AWIDTH-1:0] single_addr,
input logic [15:0] single_data,
output logic [4:0] range_addr,
input pg_range_t range_data,
output logic [4:0] list_addr,
input pg_list_t list_data,
output logic [10:0] http_src_addr,
input logic [31:0] http_src_data,
output logic [10:0] http_dst_addr,
input logic [31:0] http_dst_data,
output logic port_match
);
logic rd_pg;
logic rd_pg_r;
logic rd_pg_valid;
logic rd_pg_valid_r;
logic reg_tcp;
logic [15:0] reg_src_port;
logic [15:0] reg_dst_port;
logic any;
logic any_r1;
logic any_r2;
logic any_r3;
logic any_r4;
logic any_r5;
logic any_r6;
logic [PG_AWIDTH-1:0] pg_r1;
logic [PG_AWIDTH-1:0] pg_r2;
logic [PG_AWIDTH-1:0] pg_r3;
logic [PG_AWIDTH-1:0] pg_r4;
logic [PG_AWIDTH-1:0] pg_r5;
pg_entry_t pg_entry_data_r1;
logic single_rd;
logic single_rd_r;
logic single_rd_valid;
logic [15:0] check_port;
logic [15:0] check_port_r1;
logic [15:0] check_port_r2;
logic [15:0] check_port_r3;
logic [15:0] check_port_r4;
logic [15:0] check_port_r5;
logic single_match;
logic single_match_r1;
logic single_match_r2;
logic single_match_r3;
logic range_rd;
logic range_rd_r;
logic range_rd_valid;
logic range_match;
logic range_match_r1;
logic range_match_r2;
logic range_match_r3;
logic list_rd;
logic list_rd_r1;
logic list_rd_r2;
logic list_rd_r3;
logic list_rd_r;
logic list_rd_valid;
logic [4:0] list_index;
logic [4:0] list_index_r1;
logic [4:0] list_index_r2;
logic [4:0] list_index_r3;
logic [6:0] list_bm;
logic list_bm_match;
logic list_match;
logic http_src_rd;
logic http_src_rd_r;
logic http_src_rd_valid;
logic http_src_match;
logic http_src_match_r1;
logic http_src_match_r2;
logic http_src_match_r3;
logic http_dst_rd;
logic http_dst_rd_r;
logic http_dst_rd_valid;
logic http_dst_match;
logic http_dst_match_r1;
logic http_dst_match_r2;
logic http_dst_match_r3;
assign pg_entry_addr = pg_r1;
assign single_addr = pg_r5;
assign list_addr = list_index_r3;
// First stage: index rule2pg table
always @(posedge clk) begin
// CYCLE 1
// Read pg entry table based on rule_rd_valid
rd_pg <= in_pg_valid;
pg_r1 <= in_pg;
// CYCLE 2
// pg entry table read delay 1
rd_pg_r <= rd_pg;
pg_r2 <= pg_r1;
// CYCLE 3
// pg entry table read delay 2
rd_pg_valid <= rd_pg_r;
pg_r3 <= pg_r2;
// CYCLE 4
// Pass the output pg_entry
pg_entry_data_r1 <= pg_entry_data;
rd_pg_valid_r <= rd_pg_valid;
pg_r4 <= pg_r3;
// CYCLE 5
// Parse the meta data bits
pg_r5 <= pg_r4;
any <= 0;
single_rd <= 0;
range_rd <= 0;
range_addr <= 0;
list_rd <= 0;
list_index <= 0;
check_port <= 0;
http_src_rd <= 0;
http_dst_rd <= 0;
http_src_addr <= 0;
http_dst_addr <= 0;
// Read single value table
if ((rd_pg_valid_r) & (reg_tcp == pg_entry_data_r1.tcp)) begin
if (pg_entry_data_r1.any) begin
any <= 1;
end
else begin
if (pg_entry_data_r1.single) begin
single_rd <= 1;
end
// Range has higher priority than list
else if (pg_entry_data_r1.range) begin
range_rd <= 1;
range_addr <= pg_entry_data_r1.table_index;
end
else if (pg_entry_data_r1.list) begin
list_rd <= 1;
list_index <= pg_entry_data_r1.table_index;
end
else begin
if (pg_entry_data_r1.src) begin
http_src_rd <= 1;
http_src_addr <= reg_src_port >> 5;
end
else begin
http_dst_rd <= 1;
http_dst_addr <= reg_dst_port >> 5;
end
end
end
if (pg_entry_data_r1.src) begin
check_port <= reg_src_port;
end
else begin
check_port <= reg_dst_port;
end
end
// CYCLE 6
// Table read delay 1, forward other signals
any_r1 <= any;
single_rd_r <= single_rd;
range_rd_r <= range_rd;
list_rd_r1 <= list_rd;
list_index_r1 <= list_index;
http_src_rd_r <= http_src_rd;
http_dst_rd_r <= http_dst_rd;
check_port_r1 <= check_port;
// CYCLE 7
// Table read delay 2, forward other signals, read the Range
// Table at the same cycle
any_r2 <= any_r1;
single_rd_valid <= single_rd_r;
range_rd_valid <= range_rd_r;
list_rd_r2 <= list_rd_r1;
list_index_r2 <= list_index_r1;
http_src_rd_valid <= http_src_rd_r;
http_dst_rd_valid <= http_dst_rd_r;
check_port_r2 <= check_port_r1;
// CYCLE 8
// Forward other signals
any_r3 <= any_r2;
list_rd_r3 <= list_rd_r2;
list_index_r3 <= list_index_r2;
check_port_r3 <= check_port_r2;
// Decide signals based on Table output
single_match <= 0;
if (single_rd_valid & (single_data == check_port_r2)) begin
single_match <= 1;
end
range_match <= 0;
if (range_rd_valid) begin
if (((check_port_r2 >= range_data.range_start0) & (check_port_r2 <= range_data.range_end0)) |
((check_port_r2 >= range_data.range_start1) & (check_port_r2 <= range_data.range_end1)) |
((check_port_r2 >= range_data.range_start2) & (check_port_r2 <= range_data.range_end2)) ) begin
range_match <= 1;
end
// Trigger the list check even if there is no range match. It is
// safe to do so as one port group can be either range or list.
if (range_data.list) begin
list_rd_r3 <= 1;
list_index_r3 <= range_data.list_index;
end
end
http_src_match <= 0;
if (http_src_rd_valid) begin
if ((http_src_data >> check_port_r2[4:0]) & 1) begin
http_src_match <= 1;
end
end
http_dst_match <= 0;
if (http_dst_rd_valid) begin
if ((http_dst_data >> check_port_r2[4:0]) & 1) begin
http_dst_match <= 1;
end
end
// CYCLE 9
// Read List Table delay 1
any_r4 <= any_r3;
single_match_r1 <= single_match;
range_match_r1 <= range_match;
http_src_match_r1 <= http_src_match;
http_dst_match_r1 <= http_dst_match;
check_port_r4 <= check_port_r3;
list_rd_r <= list_rd_r3;
// CYCLE 10
// Read List Table delay 2
any_r5 <= any_r4;
single_match_r2 <= single_match_r1;
range_match_r2 <= range_match_r1;
http_src_match_r2 <= http_src_match_r1;
http_dst_match_r2 <= http_dst_match_r1;
check_port_r5 <= check_port_r4;
list_rd_valid <= list_rd_r;
// CYCLE 11
// Compare the List Table output with check_port
any_r6 <= any_r5;
single_match_r3 <= single_match_r2;
range_match_r3 <= range_match_r2;
http_src_match_r3 <= http_src_match_r2;
http_dst_match_r3 <= http_dst_match_r2;
list_match <= 0;
if (list_rd_valid) begin
list_match <= list_bm_match;
end
// CYCLE 12
port_match <= (any_r6 | single_match_r3 | range_match_r3 |
http_src_match_r3 | http_dst_match_r3 | list_match);
end
assign list_bm[0] = (check_port_r5 == list_data.value0);
assign list_bm[1] = (check_port_r5 == list_data.value1);
assign list_bm[2] = (check_port_r5 == list_data.value2);
assign list_bm[3] = (check_port_r5 == list_data.value3);
assign list_bm[4] = (check_port_r5 == list_data.value4);
assign list_bm[5] = (check_port_r5 == list_data.value5);
assign list_bm[6] = (check_port_r5 == list_data.value6);
assign list_bm_match = (list_bm[0] | list_bm[1] | list_bm[2] | list_bm[3] |
list_bm[4] | list_bm[5] | list_bm[6]);
hyper_pipe #(
.WIDTH (1),
.NUM_PIPES(3)
) hp_tcp (
.clk(clk),
.din(tcp),
.dout(reg_tcp)
);
hyper_pipe #(
.WIDTH (16),
.NUM_PIPES(3)
) hp_src_port (
.clk(clk),
.din(src_port),
.dout(reg_src_port)
);
hyper_pipe #(
.WIDTH (16),
.NUM_PIPES(5)
) hp_dst_port (
.clk(clk),
.din(dst_port),
.dout(reg_dst_port)
);
endmodule |
module top(output logic a);
initial begin
a = 1;
a ^= 0;
end
endmodule |
module top;
initial begin
$display("Bin number 10 should be printed: %b", 2'd2);
end
endmodule |
module top(input [3:0] a, output [3:0] b);
assign b = !a;
endmodule |
module top;
initial begin
$display("Hex number ab should be printed: %h", 8'hAB);
end
endmodule |
module top(input [3:0] a, output [3:0] b);
assign b = +a;
endmodule |
module top(input a, output b);
assign b = a;
endmodule |
module top(input [3:0] a, output [3:0] b);
assign b = -a;
endmodule |
module top(output logic a, b, c, d, e, f, g, h, i, j, k, l);
initial begin
a = 1;
a -= 1;
b = 4;
b /= 2;
c = 5;
c %= 2;
d = 1;
d <<= 1;
e = 8;
e >>= 1;
f = 1;
f += 1;
g = 2;
g *= 3;
h = 3;
h &= 1;
i = 6;
i |= 4;
j = 1;
j ^= 0;
k = 5;
k <<<= 1;
l = 5;
l >>>= 1;
end
endmodule |
module top ();
wire a = 0;
wire b = 0;
wire c = 0;
wire d = 0;
reg out;
always @(*)
out = (a | b) & (c | d);
endmodule |
module top ();
wire a = 1;
reg b = 0;
always @* begin
if(a) b = 1;
else b = 0;
end
endmodule |
module top
(
input [0:3] in, // verilog_lint: waive packed-dimensions-range-ordering
output out_1, out_2, out_3, out_4, out_5, out_6, out_7, out_8, out_9, out_10,
out_11, out_12, out_13, out_14, out_15, out_16, out_17, out_18
);
assign out_1 = in[0] & in[1];
assign out_2 = in[0] | in[1];
assign out_3 = in[0] ~& in[1];
assign out_4 = in[0] ~| in[1];
assign out_5 = in[0] ^ in[1];
assign out_6 = in[0] ~^ in[1];
assign out_7 = in[0] ^~ in[1];
assign out_8 = ~in[0];
assign out_9 = in[0];
assign out_10 = &in[0];
assign out_11 = |in[0];
assign out_12 = ~&in[0];
assign out_13 = ~|in[0];
assign out_14 = ^in[0];
assign out_15 = ~^in[0];
assign out_16 = ^~in[0];
assign out_17 = in[0:1] && in [2:3];
assign out_18 = in[0:1] || in [2:3];
endmodule |
module top (i, index_o);
input [31:0] i;
output [1:2] index_o; // verilog_lint: waive packed-dimensions-range-ordering
wire [1:2] index_o; // verilog_lint: waive packed-dimensions-range-ordering
assign index_o[1] = i[1];
assign index_o[2] = i[0];
endmodule |
module top;
endmodule |
module prim_secded_top (
input logic [21:0] in_22,
output logic [21:0] d_o_28,
output logic [5:0] syndrome_o_28,
output logic [1:0] err_o_28,
input logic [31:0] in_32,
output logic [31:0] d_o_32,
output logic [6:0] syndrome_o_32,
output logic [1:0] err_o_32,
input logic [63:0] in_64,
output logic [63:0] d_o_72,
output logic [7:0] syndrome_o_64,
output logic [1:0] err_o_64
);
logic [27:0] enc_28;
prim_secded_28_22_enc enc1 (
.in ( in_22 ),
.out ( enc_28)
);
prim_secded_28_22_dec dec1 (
.in ( enc_28),
.d_o ( d_o_28),
.syndrome_o ( syndrome_o_28),
.err_o ( err_o_28)
);
logic [38:0] enc_39;
prim_secded_39_32_enc enc2 (
.in ( in_32),
.out ( enc_39)
);
prim_secded_39_32_dec dec2 (
.in ( enc_39),
.d_o ( d_o_32),
.syndrome_o ( syndrome_o_32),
.err_o ( err_o_32)
);
logic [71:0] enc_72;
prim_secded_72_64_enc enc3 (
.in ( in_64),
.out ( enc_72)
);
prim_secded_72_64_dec dec3 (
.in ( enc_72),
.d_o ( d_o_72),
.syndrome_o ( syndrome_o_64),
.err_o ( err_o_64)
);
endmodule |
module tft_ili9341_spi(
input spiClk, input[8:0] data, input dataAvailable,
output wire tft_sck, output reg tft_sdi, output reg tft_dc, output wire tft_cs,
output reg idle
);
// Registers
reg[0:2] counter = 3'b0;
reg[8:0] internalData;
reg internalSck;
reg cs;
initial internalSck <= 1'b1;
initial idle <= 1'b1;
initial cs <= 1'b0;
// Combinational Assignments
wire dataDc = internalData[8];
wire[0:7] dataShift = internalData[7:0]; // MSB first
assign tft_sck = internalSck & cs; // only drive sck with an active CS
assign tft_cs = !cs; // active low
// Update SPI CLK + Output data
always @ (posedge spiClk) begin
// Store new data in internal register
if (dataAvailable) begin
internalData <= data;
idle <= 1'b0;
end
// Change data if we're actively sending
if (!idle) begin
// Toggle Clock on every active tick
internalSck <= !internalSck;
// Check if SCK will be low next
if (internalSck) begin
// Update pins
tft_dc <= dataDc;
tft_sdi <= dataShift[counter];
cs <= 1'b1;
// Advance counter
counter <= counter + 1'b1;
idle <= &counter; // we're just sending the last bit
end
end
else begin
internalSck <= 1'b1; // idle mode (also: sent last bit)
if (internalSck) cs <= 1'b0; // idle for two bits in a row -> deactivate CS
end
end
endmodule |
module axis_dram_fifo_single
#(
parameter USE_SRAM_MEMORY = 0,
parameter USE_BD_INTERCON = 0,
parameter SR_BASE = 0
) (
input bus_clk,
input bus_rst,
input sys_clk,
input sys_rst,
input [63:0] i_tdata,
input i_tlast,
input i_tvalid,
output i_tready,
output [63:0] o_tdata,
output o_tlast,
output o_tvalid,
input o_tready,
input set_stb,
input [7:0] set_addr,
input [31:0] set_data,
output [31:0] rb_data,
input [63:0] forced_bit_err,
output init_calib_complete
);
// Misc declarations
axi4_rd_t #(.DWIDTH(64), .AWIDTH(32), .IDWIDTH(1)) dma_axi_rd(.clk(sys_clk));
axi4_wr_t #(.DWIDTH(64), .AWIDTH(32), .IDWIDTH(1)) dma_axi_wr(.clk(sys_clk));
axi4_rd_t #(.DWIDTH(256), .AWIDTH(32), .IDWIDTH(1)) mig_axi_rd(.clk(sys_clk));
axi4_wr_t #(.DWIDTH(256), .AWIDTH(32), .IDWIDTH(1)) mig_axi_wr(.clk(sys_clk));
wire [31:0] ddr3_dq; // Data pins. Input for Reads; Output for Writes.
wire [3:0] ddr3_dqs_n; // Data Strobes. Input for Reads; Output for Writes.
wire [3:0] ddr3_dqs_p;
wire [14:0] ddr3_addr; // Address
wire [2:0] ddr3_ba; // Bank Address
wire ddr3_ras_n; // Row Address Strobe.
wire ddr3_cas_n; // Column address select
wire ddr3_we_n; // Write Enable
wire ddr3_reset_n; // SDRAM reset pin.
wire [0:0] ddr3_ck_p; // Differential clock
wire [0:0] ddr3_ck_n;
wire [0:0] ddr3_cke; // Clock Enable
wire [0:0] ddr3_cs_n; // Chip Select
wire [3:0] ddr3_dm; // Data Mask [3] = UDM.U26; [2] = LDM.U26; ...
wire [0:0] ddr3_odt; // On-Die termination enable.
wire ddr3_axi_clk; // 1/4 DDR external clock rate (250MHz)
wire ddr3_axi_rst; // Synchronized to ddr_sys_clk
reg ddr3_axi_rst_reg_n; // Synchronized to ddr_sys_clk
wire ddr3_axi_clk_x2;
always @(posedge ddr3_axi_clk)
ddr3_axi_rst_reg_n <= ~ddr3_axi_rst;
axi_dma_fifo #(
.DEFAULT_BASE(30'h00010000),
.DEFAULT_MASK(30'hFFFF0000),
.DEFAULT_TIMEOUT(280),
.SR_BASE(SR_BASE),
.EXT_BIST(1),
.SIMULATION(1)
) axi_dma_fifo_i0 (
//
// Clocks and reset
.bus_clk (bus_clk),
.bus_reset (bus_rst),
.dram_clk (ddr3_axi_clk_x2),
.dram_reset (ddr3_axi_rst),
//
// AXI Write address channel
.m_axi_awid (dma_axi_wr.addr.id),
.m_axi_awaddr (dma_axi_wr.addr.addr),
.m_axi_awlen (dma_axi_wr.addr.len),
.m_axi_awsize (dma_axi_wr.addr.size),
.m_axi_awburst (dma_axi_wr.addr.burst),
.m_axi_awlock (dma_axi_wr.addr.lock),
.m_axi_awcache (dma_axi_wr.addr.cache),
.m_axi_awprot (dma_axi_wr.addr.prot),
.m_axi_awqos (dma_axi_wr.addr.qos),
.m_axi_awregion (dma_axi_wr.addr.region),
.m_axi_awuser (dma_axi_wr.addr.user),
.m_axi_awvalid (dma_axi_wr.addr.valid),
.m_axi_awready (dma_axi_wr.addr.ready),
//
// AXI Write data channel.
.m_axi_wdata (dma_axi_wr.data.data),
.m_axi_wstrb (dma_axi_wr.data.strb),
.m_axi_wlast (dma_axi_wr.data.last),
.m_axi_wuser (dma_axi_wr.data.user),
.m_axi_wvalid (dma_axi_wr.data.valid),
.m_axi_wready (dma_axi_wr.data.ready),
//
// AXI Write response channel signals
.m_axi_bid (dma_axi_wr.resp.id),
.m_axi_bresp (dma_axi_wr.resp.resp),
.m_axi_buser (dma_axi_wr.resp.user),
.m_axi_bvalid (dma_axi_wr.resp.valid),
.m_axi_bready (dma_axi_wr.resp.ready),
//
// AXI Read address channel
.m_axi_arid (dma_axi_rd.addr.id),
.m_axi_araddr (dma_axi_rd.addr.addr),
.m_axi_arlen (dma_axi_rd.addr.len),
.m_axi_arsize (dma_axi_rd.addr.size),
.m_axi_arburst (dma_axi_rd.addr.burst),
.m_axi_arlock (dma_axi_rd.addr.lock),
.m_axi_arcache (dma_axi_rd.addr.cache),
.m_axi_arprot (dma_axi_rd.addr.prot),
.m_axi_arqos (dma_axi_rd.addr.qos),
.m_axi_arregion (dma_axi_rd.addr.region),
.m_axi_aruser (dma_axi_rd.addr.user),
.m_axi_arvalid (dma_axi_rd.addr.valid),
.m_axi_arready (dma_axi_rd.addr.ready),
//
// AXI Read data channel
.m_axi_rid (dma_axi_rd.data.id),
.m_axi_rdata (dma_axi_rd.data.data),
.m_axi_rresp (dma_axi_rd.data.resp),
.m_axi_rlast (dma_axi_rd.data.last),
.m_axi_ruser (dma_axi_rd.data.user),
.m_axi_rvalid (dma_axi_rd.data.valid),
.m_axi_rready (dma_axi_rd.data.ready),
//
// CHDR friendly AXI stream input
.i_tdata (i_tdata),
.i_tlast (i_tlast),
.i_tvalid (i_tvalid),
.i_tready (i_tready),
//
// CHDR friendly AXI Stream output
.o_tdata (o_tdata),
.o_tlast (o_tlast),
.o_tvalid (o_tvalid),
.o_tready (o_tready),
//
// Settings
.set_stb (set_stb),
.set_addr (set_addr),
.set_data (set_data),
.rb_data (rb_data),
.debug()
);
generate if (USE_SRAM_MEMORY) begin
assign init_calib_complete = 1;
assign ddr3_axi_clk = bus_clk;
assign ddr3_axi_clk_x2 = bus_clk;
assign ddr3_axi_rst = bus_rst;
axi4_dualport_sram axi4_dualport_sram_i1 (
.s_aclk (ddr3_axi_clk_x2), // input s_aclk
.s_aresetn (~ddr3_axi_rst), // input s_aresetn
.s_axi_awid (dma_axi_wr.addr.id), // input [0 : 0] s_axi_awid
.s_axi_awaddr (dma_axi_wr.addr.addr), // input [31 : 0] s_axi_awaddr
.s_axi_awlen (dma_axi_wr.addr.len), // input [7 : 0] s_axi_awlen
.s_axi_awsize (dma_axi_wr.addr.size), // input [2 : 0] s_axi_awsize
.s_axi_awburst (dma_axi_wr.addr.burst), // input [1 : 0] s_axi_awburst
.s_axi_awvalid (dma_axi_wr.addr.valid), // input s_axi_awvalid
.s_axi_awready (dma_axi_wr.addr.ready), // output s_axi_awready
.s_axi_wdata (dma_axi_wr.data.data ^ forced_bit_err), // input [63 : 0] s_axi_wdata
.s_axi_wstrb (dma_axi_wr.data.strb), // input [7 : 0] s_axi_wstrb
.s_axi_wlast (dma_axi_wr.data.last), // input s_axi_wlast
.s_axi_wvalid (dma_axi_wr.data.valid), // input s_axi_wvalid
.s_axi_wready (dma_axi_wr.data.ready), // output s_axi_wready
.s_axi_bid (dma_axi_wr.resp.id), // output [0 : 0] s_axi_bid
.s_axi_bresp (dma_axi_wr.resp.resp), // output [1 : 0] s_axi_bresp
.s_axi_bvalid (dma_axi_wr.resp.valid), // output s_axi_bvalid
.s_axi_bready (dma_axi_wr.resp.ready), // input s_axi_bready
.s_axi_arid (dma_axi_rd.addr.id), // input [0 : 0] s_axi_arid
.s_axi_araddr (dma_axi_rd.addr.addr), // input [31 : 0] s_axi_araddr
.s_axi_arlen (dma_axi_rd.addr.len), // input [7 : 0] s_axi_arlen
.s_axi_arsize (dma_axi_rd.addr.size), // input [2 : 0] s_axi_arsize
.s_axi_arburst (dma_axi_rd.addr.burst), // input [1 : 0] s_axi_arburst
.s_axi_arvalid (dma_axi_rd.addr.valid), // input s_axi_arvalid
.s_axi_arready (dma_axi_rd.addr.ready), // output s_axi_arready
.s_axi_rid (dma_axi_rd.data.id), // output [0 : 0] s_axi_rid
.s_axi_rdata (dma_axi_rd.data.data), // output [63 : 0] s_axi_rdata
.s_axi_rresp (dma_axi_rd.data.resp), // output [1 : 0] s_axi_rresp
.s_axi_rlast (dma_axi_rd.data.last), // output s_axi_rlast
.s_axi_rvalid (dma_axi_rd.data.valid), // output s_axi_rvalid
.s_axi_rready (dma_axi_rd.data.ready) // input s_axi_rready
);
end else begin //generate if (USE_SRAM_MEMORY) begin
//---------------------------------------------------
// We use an interconnect to connect to FIFOs.
//---------------------------------------------------
if (USE_BD_INTERCON) begin
// Vivado Block Diagram interconnect.
axi_intercon_2x64_128_bd_wrapper axi_intercon_2x64_128_i (
.S00_AXI_ACLK (ddr3_axi_clk_x2), // input S00_AXI_ACLK
.S00_AXI_ARESETN (~ddr3_axi_rst), // input S00_AXI_ARESETN
.S00_AXI_AWID (dma_axi_wr.addr.id), // input [0 : 0] S00_AXI_AWID
.S00_AXI_AWADDR (dma_axi_wr.addr.addr), // input [31 : 0] S00_AXI_AWADDR
.S00_AXI_AWLEN (dma_axi_wr.addr.len), // input [7 : 0] S00_AXI_AWLEN
.S00_AXI_AWSIZE (dma_axi_wr.addr.size), // input [2 : 0] S00_AXI_AWSIZE
.S00_AXI_AWBURST (dma_axi_wr.addr.burst), // input [1 : 0] S00_AXI_AWBURST
.S00_AXI_AWLOCK (dma_axi_wr.addr.lock), // input S00_AXI_AWLOCK
.S00_AXI_AWCACHE (dma_axi_wr.addr.cache), // input [3 : 0] S00_AXI_AWCACHE
.S00_AXI_AWPROT (dma_axi_wr.addr.prot), // input [2 : 0] S00_AXI_AWPROT
.S00_AXI_AWQOS (dma_axi_wr.addr.qos), // input [3 : 0] S00_AXI_AWQOS
.S00_AXI_AWVALID (dma_axi_wr.addr.valid), // input S00_AXI_AWVALID
.S00_AXI_AWREADY (dma_axi_wr.addr.ready), // output S00_AXI_AWREADY
.S00_AXI_WDATA (dma_axi_wr.data.data ^ forced_bit_err), // input [63 : 0] S00_AXI_WDATA
.S00_AXI_WSTRB (dma_axi_wr.data.strb), // input [7 : 0] S00_AXI_WSTRB
.S00_AXI_WLAST (dma_axi_wr.data.last), // input S00_AXI_WLAST
.S00_AXI_WVALID (dma_axi_wr.data.valid), // input S00_AXI_WVALID
.S00_AXI_WREADY (dma_axi_wr.data.ready), // output S00_AXI_WREADY
.S00_AXI_BID (dma_axi_wr.resp.id), // output [0 : 0] S00_AXI_BID
.S00_AXI_BRESP (dma_axi_wr.resp.resp), // output [1 : 0] S00_AXI_BRESP
.S00_AXI_BVALID (dma_axi_wr.resp.valid), // output S00_AXI_BVALID
.S00_AXI_BREADY (dma_axi_wr.resp.ready), // input S00_AXI_BREADY
.S00_AXI_ARID (dma_axi_rd.addr.id), // input [0 : 0] S00_AXI_ARID
.S00_AXI_ARADDR (dma_axi_rd.addr.addr), // input [31 : 0] S00_AXI_ARADDR
.S00_AXI_ARLEN (dma_axi_rd.addr.len), // input [7 : 0] S00_AXI_ARLEN
.S00_AXI_ARSIZE (dma_axi_rd.addr.size), // input [2 : 0] S00_AXI_ARSIZE
.S00_AXI_ARBURST (dma_axi_rd.addr.burst), // input [1 : 0] S00_AXI_ARBURST
.S00_AXI_ARLOCK (dma_axi_rd.addr.lock), // input S00_AXI_ARLOCK
.S00_AXI_ARCACHE (dma_axi_rd.addr.cache), // input [3 : 0] S00_AXI_ARCACHE
.S00_AXI_ARPROT (dma_axi_rd.addr.prot), // input [2 : 0] S00_AXI_ARPROT
.S00_AXI_ARQOS (dma_axi_rd.addr.qos), // input [3 : 0] S00_AXI_ARQOS
.S00_AXI_ARVALID (dma_axi_rd.addr.valid), // input S00_AXI_ARVALID
.S00_AXI_ARREADY (dma_axi_rd.addr.ready), // output S00_AXI_ARREADY
.S00_AXI_RID (dma_axi_rd.data.id), // output [0 : 0] S00_AXI_RID
.S00_AXI_RDATA (dma_axi_rd.data.data), // output [63 : 0] S00_AXI_RDATA
.S00_AXI_RRESP (dma_axi_rd.data.resp), // output [1 : 0] S00_AXI_RRESP
.S00_AXI_RLAST (dma_axi_rd.data.last), // output S00_AXI_RLAST
.S00_AXI_RVALID (dma_axi_rd.data.valid), // output S00_AXI_RVALID
.S00_AXI_RREADY (dma_axi_rd.data.ready), // input S00_AXI_RREADY
//
//.S01_AXI_ARESET_OUT_N (), // output S01_AXI_ARESET_OUT_N
.S01_AXI_ACLK (ddr3_axi_clk_x2), // input S01_AXI_ACLK
.S01_AXI_ARESETN (~ddr3_axi_rst), // input S01_AXI_ARESETN
.S01_AXI_AWID (0), // input [0 : 0] S01_AXI_AWID
.S01_AXI_AWADDR (0), // input [31 : 0] S01_AXI_AWADDR
.S01_AXI_AWLEN (0), // input [7 : 0] S01_AXI_AWLEN
.S01_AXI_AWSIZE (0), // input [2 : 0] S01_AXI_AWSIZE
.S01_AXI_AWBURST (0), // input [1 : 0] S01_AXI_AWBURST
.S01_AXI_AWLOCK (0), // input S01_AXI_AWLOCK
.S01_AXI_AWCACHE (0), // input [3 : 0] S01_AXI_AWCACHE
.S01_AXI_AWPROT (0), // input [2 : 0] S01_AXI_AWPROT
.S01_AXI_AWQOS (0), // input [3 : 0] S01_AXI_AWQOS
.S01_AXI_AWVALID (0), // input S01_AXI_AWVALID
.S01_AXI_AWREADY (), // output S01_AXI_AWREADY
.S01_AXI_WDATA (0), // input [63 : 0] S01_AXI_WDATA
.S01_AXI_WSTRB (0), // input [7 : 0] S01_AXI_WSTRB
.S01_AXI_WLAST (0), // input S01_AXI_WLAST
.S01_AXI_WVALID (0), // input S01_AXI_WVALID
.S01_AXI_WREADY (), // output S01_AXI_WREADY
.S01_AXI_BID (), // output [0 : 0] S01_AXI_BID
.S01_AXI_BRESP (), // output [1 : 0] S01_AXI_BRESP
.S01_AXI_BVALID (), // output S01_AXI_BVALID
.S01_AXI_BREADY (0), // input S01_AXI_BREADY
.S01_AXI_ARID (0), // input [0 : 0] S01_AXI_ARID
.S01_AXI_ARADDR (0), // input [31 : 0] S01_AXI_ARADDR
.S01_AXI_ARLEN (0), // input [7 : 0] S01_AXI_ARLEN
.S01_AXI_ARSIZE (0), // input [2 : 0] S01_AXI_ARSIZE
.S01_AXI_ARBURST (0), // input [1 : 0] S01_AXI_ARBURST
.S01_AXI_ARLOCK (0), // input S01_AXI_ARLOCK
.S01_AXI_ARCACHE (0), // input [3 : 0] S01_AXI_ARCACHE
.S01_AXI_ARPROT (0), // input [2 : 0] S01_AXI_ARPROT
.S01_AXI_ARQOS (0), // input [3 : 0] S01_AXI_ARQOS
.S01_AXI_ARVALID (0), // input S01_AXI_ARVALID
.S01_AXI_ARREADY (), // output S01_AXI_ARREADY
.S01_AXI_RID (), // output [0 : 0] S01_AXI_RID
.S01_AXI_RDATA (), // output [63 : 0] S01_AXI_RDATA
.S01_AXI_RRESP (), // output [1 : 0] S01_AXI_RRESP
.S01_AXI_RLAST (), // output S01_AXI_RLAST
.S01_AXI_RVALID (), // output S01_AXI_RVALID
.S01_AXI_RREADY (0), // input S01_AXI_RREADY
//
//.M00_AXI_ARESET_OUT_N (), // output M00_AXI_ARESET_OUT_N
.M00_AXI_ACLK (ddr3_axi_clk), // input M00_AXI_ACLK
.M00_AXI_ARESETN (~ddr3_axi_rst), // input M00_AXI_ARESETN
.M00_AXI_AWID (mig_axi_wr.addr.id), // output [3 : 0] M00_AXI_AWID
.M00_AXI_AWADDR (mig_axi_wr.addr.addr), // output [31 : 0] M00_AXI_AWADDR
.M00_AXI_AWLEN (mig_axi_wr.addr.len), // output [7 : 0] M00_AXI_AWLEN
.M00_AXI_AWSIZE (mig_axi_wr.addr.size), // output [2 : 0] M00_AXI_AWSIZE
.M00_AXI_AWBURST (mig_axi_wr.addr.burst), // output [1 : 0] M00_AXI_AWBURST
.M00_AXI_AWLOCK (mig_axi_wr.addr.lock), // output M00_AXI_AWLOCK
.M00_AXI_AWCACHE (mig_axi_wr.addr.cache), // output [3 : 0] M00_AXI_AWCACHE
.M00_AXI_AWPROT (mig_axi_wr.addr.prot), // output [2 : 0] M00_AXI_AWPROT
.M00_AXI_AWQOS (mig_axi_wr.addr.qos), // output [3 : 0] M00_AXI_AWQOS
.M00_AXI_AWVALID (mig_axi_wr.addr.valid), // output M00_AXI_AWVALID
.M00_AXI_AWREADY (mig_axi_wr.addr.ready), // input M00_AXI_AWREADY
.M00_AXI_WDATA (mig_axi_wr.data.data), // output [127 : 0] M00_AXI_WDATA
.M00_AXI_WSTRB (mig_axi_wr.data.strb), // output [15 : 0] M00_AXI_WSTRB
.M00_AXI_WLAST (mig_axi_wr.data.last), // output M00_AXI_WLAST
.M00_AXI_WVALID (mig_axi_wr.data.valid), // output M00_AXI_WVALID
.M00_AXI_WREADY (mig_axi_wr.data.ready), // input M00_AXI_WREADY
.M00_AXI_BID (mig_axi_wr.resp.id), // input [3 : 0] M00_AXI_BID
.M00_AXI_BRESP (mig_axi_wr.resp.resp), // input [1 : 0] M00_AXI_BRESP
.M00_AXI_BVALID (mig_axi_wr.resp.valid), // input M00_AXI_BVALID
.M00_AXI_BREADY (mig_axi_wr.resp.ready), // output M00_AXI_BREADY
.M00_AXI_ARID (mig_axi_rd.addr.id), // output [3 : 0] M00_AXI_ARID
.M00_AXI_ARADDR (mig_axi_rd.addr.addr), // output [31 : 0] M00_AXI_ARADDR
.M00_AXI_ARLEN (mig_axi_rd.addr.len), // output [7 : 0] M00_AXI_ARLEN
.M00_AXI_ARSIZE (mig_axi_rd.addr.size), // output [2 : 0] M00_AXI_ARSIZE
.M00_AXI_ARBURST (mig_axi_rd.addr.burst), // output [1 : 0] M00_AXI_ARBURST
.M00_AXI_ARLOCK (mig_axi_rd.addr.lock), // output M00_AXI_ARLOCK
.M00_AXI_ARCACHE (mig_axi_rd.addr.cache), // output [3 : 0] M00_AXI_ARCACHE
.M00_AXI_ARPROT (mig_axi_rd.addr.prot), // output [2 : 0] M00_AXI_ARPROT
.M00_AXI_ARQOS (mig_axi_rd.addr.qos), // output [3 : 0] M00_AXI_ARQOS
.M00_AXI_ARVALID (mig_axi_rd.addr.valid), // output M00_AXI_ARVALID
.M00_AXI_ARREADY (mig_axi_rd.addr.ready), // input M00_AXI_ARREADY
.M00_AXI_RID (mig_axi_rd.data.id), // input [3 : 0] M00_AXI_RID
.M00_AXI_RDATA (mig_axi_rd.data.data), // input [127 : 0] M00_AXI_RDATA
.M00_AXI_RRESP (mig_axi_rd.data.resp), // input [1 : 0] M00_AXI_RRESP
.M00_AXI_RLAST (mig_axi_rd.data.last), // input M00_AXI_RLAST
.M00_AXI_RVALID (mig_axi_rd.data.valid), // input M00_AXI_RVALID
.M00_AXI_RREADY (mig_axi_rd.data.ready) // output M00_AXI_RREADY
);
end else begin
//Original IP interconnect
axi_intercon_2x64_128 axi_intercon_2x64_128_i (
.INTERCONNECT_ACLK(ddr3_axi_clk_x2), // input INTERCONNECT_ACLK
.INTERCONNECT_ARESETN(~ddr3_axi_rst), // input INTERCONNECT_ARESETN
//
.S00_AXI_ARESET_OUT_N (), // output S00_AXI_ARESET_OUT_N
.S00_AXI_ACLK (ddr3_axi_clk_x2), // input S00_AXI_ACLK
.S00_AXI_AWID (dma_axi_wr.addr.id), // input [0 : 0] S00_AXI_AWID
.S00_AXI_AWADDR (dma_axi_wr.addr.addr), // input [31 : 0] S00_AXI_AWADDR
.S00_AXI_AWLEN (dma_axi_wr.addr.len), // input [7 : 0] S00_AXI_AWLEN
.S00_AXI_AWSIZE (dma_axi_wr.addr.size), // input [2 : 0] S00_AXI_AWSIZE
.S00_AXI_AWBURST (dma_axi_wr.addr.burst), // input [1 : 0] S00_AXI_AWBURST
.S00_AXI_AWLOCK (dma_axi_wr.addr.lock), // input S00_AXI_AWLOCK
.S00_AXI_AWCACHE (dma_axi_wr.addr.cache), // input [3 : 0] S00_AXI_AWCACHE
.S00_AXI_AWPROT (dma_axi_wr.addr.prot), // input [2 : 0] S00_AXI_AWPROT
.S00_AXI_AWQOS (dma_axi_wr.addr.qos), // input [3 : 0] S00_AXI_AWQOS
.S00_AXI_AWVALID (dma_axi_wr.addr.valid), // input S00_AXI_AWVALID
.S00_AXI_AWREADY (dma_axi_wr.addr.ready), // output S00_AXI_AWREADY
.S00_AXI_WDATA (dma_axi_wr.data.data ^ forced_bit_err), // input [63 : 0] S00_AXI_WDATA
.S00_AXI_WSTRB (dma_axi_wr.data.strb), // input [7 : 0] S00_AXI_WSTRB
.S00_AXI_WLAST (dma_axi_wr.data.last), // input S00_AXI_WLAST
.S00_AXI_WVALID (dma_axi_wr.data.valid), // input S00_AXI_WVALID
.S00_AXI_WREADY (dma_axi_wr.data.ready), // output S00_AXI_WREADY
.S00_AXI_BID (dma_axi_wr.resp.id), // output [0 : 0] S00_AXI_BID
.S00_AXI_BRESP (dma_axi_wr.resp.resp), // output [1 : 0] S00_AXI_BRESP
.S00_AXI_BVALID (dma_axi_wr.resp.valid), // output S00_AXI_BVALID
.S00_AXI_BREADY (dma_axi_wr.resp.ready), // input S00_AXI_BREADY
.S00_AXI_ARID (dma_axi_rd.addr.id), // input [0 : 0] S00_AXI_ARID
.S00_AXI_ARADDR (dma_axi_rd.addr.addr), // input [31 : 0] S00_AXI_ARADDR
.S00_AXI_ARLEN (dma_axi_rd.addr.len), // input [7 : 0] S00_AXI_ARLEN
.S00_AXI_ARSIZE (dma_axi_rd.addr.size), // input [2 : 0] S00_AXI_ARSIZE
.S00_AXI_ARBURST (dma_axi_rd.addr.burst), // input [1 : 0] S00_AXI_ARBURST
.S00_AXI_ARLOCK (dma_axi_rd.addr.lock), // input S00_AXI_ARLOCK
.S00_AXI_ARCACHE (dma_axi_rd.addr.cache), // input [3 : 0] S00_AXI_ARCACHE
.S00_AXI_ARPROT (dma_axi_rd.addr.prot), // input [2 : 0] S00_AXI_ARPROT
.S00_AXI_ARQOS (dma_axi_rd.addr.qos), // input [3 : 0] S00_AXI_ARQOS
.S00_AXI_ARVALID (dma_axi_rd.addr.valid), // input S00_AXI_ARVALID
.S00_AXI_ARREADY (dma_axi_rd.addr.ready), // output S00_AXI_ARREADY
.S00_AXI_RID (dma_axi_rd.data.id), // output [0 : 0] S00_AXI_RID
.S00_AXI_RDATA (dma_axi_rd.data.data), // output [63 : 0] S00_AXI_RDATA
.S00_AXI_RRESP (dma_axi_rd.data.resp), // output [1 : 0] S00_AXI_RRESP
.S00_AXI_RLAST (dma_axi_rd.data.last), // output S00_AXI_RLAST
.S00_AXI_RVALID (dma_axi_rd.data.valid), // output S00_AXI_RVALID
.S00_AXI_RREADY (dma_axi_rd.data.ready), // input S00_AXI_RREADY
//
.S01_AXI_ARESET_OUT_N (), // output S01_AXI_ARESET_OUT_N
.S01_AXI_ACLK (ddr3_axi_clk_x2), // input S01_AXI_ACLK
.S01_AXI_AWID (0), // input [0 : 0] S01_AXI_AWID
.S01_AXI_AWADDR (0), // input [31 : 0] S01_AXI_AWADDR
.S01_AXI_AWLEN (0), // input [7 : 0] S01_AXI_AWLEN
.S01_AXI_AWSIZE (0), // input [2 : 0] S01_AXI_AWSIZE
.S01_AXI_AWBURST (0), // input [1 : 0] S01_AXI_AWBURST
.S01_AXI_AWLOCK (0), // input S01_AXI_AWLOCK
.S01_AXI_AWCACHE (0), // input [3 : 0] S01_AXI_AWCACHE
.S01_AXI_AWPROT (0), // input [2 : 0] S01_AXI_AWPROT
.S01_AXI_AWQOS (0), // input [3 : 0] S01_AXI_AWQOS
.S01_AXI_AWVALID (0), // input S01_AXI_AWVALID
.S01_AXI_AWREADY (), // output S01_AXI_AWREADY
.S01_AXI_WDATA (0), // input [63 : 0] S01_AXI_WDATA
.S01_AXI_WSTRB (0), // input [7 : 0] S01_AXI_WSTRB
.S01_AXI_WLAST (0), // input S01_AXI_WLAST
.S01_AXI_WVALID (0), // input S01_AXI_WVALID
.S01_AXI_WREADY (), // output S01_AXI_WREADY
.S01_AXI_BID (), // output [0 : 0] S01_AXI_BID
.S01_AXI_BRESP (), // output [1 : 0] S01_AXI_BRESP
.S01_AXI_BVALID (), // output S01_AXI_BVALID
.S01_AXI_BREADY (0), // input S01_AXI_BREADY
.S01_AXI_ARID (0), // input [0 : 0] S01_AXI_ARID
.S01_AXI_ARADDR (0), // input [31 : 0] S01_AXI_ARADDR
.S01_AXI_ARLEN (0), // input [7 : 0] S01_AXI_ARLEN
.S01_AXI_ARSIZE (0), // input [2 : 0] S01_AXI_ARSIZE
.S01_AXI_ARBURST (0), // input [1 : 0] S01_AXI_ARBURST
.S01_AXI_ARLOCK (0), // input S01_AXI_ARLOCK
.S01_AXI_ARCACHE (0), // input [3 : 0] S01_AXI_ARCACHE
.S01_AXI_ARPROT (0), // input [2 : 0] S01_AXI_ARPROT
.S01_AXI_ARQOS (0), // input [3 : 0] S01_AXI_ARQOS
.S01_AXI_ARVALID (0), // input S01_AXI_ARVALID
.S01_AXI_ARREADY (), // output S01_AXI_ARREADY
.S01_AXI_RID (), // output [0 : 0] S01_AXI_RID
.S01_AXI_RDATA (), // output [63 : 0] S01_AXI_RDATA
.S01_AXI_RRESP (), // output [1 : 0] S01_AXI_RRESP
.S01_AXI_RLAST (), // output S01_AXI_RLAST
.S01_AXI_RVALID (), // output S01_AXI_RVALID
.S01_AXI_RREADY (0), // input S01_AXI_RREADY
//
.M00_AXI_ARESET_OUT_N (), // output M00_AXI_ARESET_OUT_N
.M00_AXI_ACLK (ddr3_axi_clk), // input M00_AXI_ACLK
.M00_AXI_AWID (mig_axi_wr.addr.id), // output [3 : 0] M00_AXI_AWID
.M00_AXI_AWADDR (mig_axi_wr.addr.addr), // output [31 : 0] M00_AXI_AWADDR
.M00_AXI_AWLEN (mig_axi_wr.addr.len), // output [7 : 0] M00_AXI_AWLEN
.M00_AXI_AWSIZE (mig_axi_wr.addr.size), // output [2 : 0] M00_AXI_AWSIZE
.M00_AXI_AWBURST (mig_axi_wr.addr.burst), // output [1 : 0] M00_AXI_AWBURST
.M00_AXI_AWLOCK (mig_axi_wr.addr.lock), // output M00_AXI_AWLOCK
.M00_AXI_AWCACHE (mig_axi_wr.addr.cache), // output [3 : 0] M00_AXI_AWCACHE
.M00_AXI_AWPROT (mig_axi_wr.addr.prot), // output [2 : 0] M00_AXI_AWPROT
.M00_AXI_AWQOS (mig_axi_wr.addr.qos), // output [3 : 0] M00_AXI_AWQOS
.M00_AXI_AWVALID (mig_axi_wr.addr.valid), // output M00_AXI_AWVALID
.M00_AXI_AWREADY (mig_axi_wr.addr.ready), // input M00_AXI_AWREADY
.M00_AXI_WDATA (mig_axi_wr.data.data), // output [127 : 0] M00_AXI_WDATA
.M00_AXI_WSTRB (mig_axi_wr.data.strb), // output [15 : 0] M00_AXI_WSTRB
.M00_AXI_WLAST (mig_axi_wr.data.last), // output M00_AXI_WLAST
.M00_AXI_WVALID (mig_axi_wr.data.valid), // output M00_AXI_WVALID
.M00_AXI_WREADY (mig_axi_wr.data.ready), // input M00_AXI_WREADY
.M00_AXI_BID (mig_axi_wr.resp.id), // input [3 : 0] M00_AXI_BID
.M00_AXI_BRESP (mig_axi_wr.resp.resp), // input [1 : 0] M00_AXI_BRESP
.M00_AXI_BVALID (mig_axi_wr.resp.valid), // input M00_AXI_BVALID
.M00_AXI_BREADY (mig_axi_wr.resp.ready), // output M00_AXI_BREADY
.M00_AXI_ARID (mig_axi_rd.addr.id), // output [3 : 0] M00_AXI_ARID
.M00_AXI_ARADDR (mig_axi_rd.addr.addr), // output [31 : 0] M00_AXI_ARADDR
.M00_AXI_ARLEN (mig_axi_rd.addr.len), // output [7 : 0] M00_AXI_ARLEN
.M00_AXI_ARSIZE (mig_axi_rd.addr.size), // output [2 : 0] M00_AXI_ARSIZE
.M00_AXI_ARBURST (mig_axi_rd.addr.burst), // output [1 : 0] M00_AXI_ARBURST
.M00_AXI_ARLOCK (mig_axi_rd.addr.lock), // output M00_AXI_ARLOCK
.M00_AXI_ARCACHE (mig_axi_rd.addr.cache), // output [3 : 0] M00_AXI_ARCACHE
.M00_AXI_ARPROT (mig_axi_rd.addr.prot), // output [2 : 0] M00_AXI_ARPROT
.M00_AXI_ARQOS (mig_axi_rd.addr.qos), // output [3 : 0] M00_AXI_ARQOS
.M00_AXI_ARVALID (mig_axi_rd.addr.valid), // output M00_AXI_ARVALID
.M00_AXI_ARREADY (mig_axi_rd.addr.ready), // input M00_AXI_ARREADY
.M00_AXI_RID (mig_axi_rd.data.id), // input [3 : 0] M00_AXI_RID
.M00_AXI_RDATA (mig_axi_rd.data.data), // input [127 : 0] M00_AXI_RDATA
.M00_AXI_RRESP (mig_axi_rd.data.resp), // input [1 : 0] M00_AXI_RRESP
.M00_AXI_RLAST (mig_axi_rd.data.last), // input M00_AXI_RLAST
.M00_AXI_RVALID (mig_axi_rd.data.valid), // input M00_AXI_RVALID
.M00_AXI_RREADY (mig_axi_rd.data.ready) // output M00_AXI_RREADY
);
end
//---------------------------------------------------
// MIG
//---------------------------------------------------
wire ddr3_idelay_refclk;
ddr3_32bit ddr_mig_i (
// Memory interface ports
.ddr3_addr (ddr3_addr),
.ddr3_ba (ddr3_ba),
.ddr3_cas_n (ddr3_cas_n),
.ddr3_ck_n (ddr3_ck_n),
.ddr3_ck_p (ddr3_ck_p),
.ddr3_cke (ddr3_cke),
.ddr3_ras_n (ddr3_ras_n),
.ddr3_reset_n (ddr3_reset_n),
.ddr3_we_n (ddr3_we_n),
.ddr3_dq (ddr3_dq),
.ddr3_dqs_n (ddr3_dqs_n),
.ddr3_dqs_p (ddr3_dqs_p),
.init_calib_complete (init_calib_complete),
.ddr3_cs_n (ddr3_cs_n),
.ddr3_dm (ddr3_dm),
.ddr3_odt (ddr3_odt),
// Application interface ports
.ui_clk (ddr3_axi_clk), // 150MHz clock out
.ui_addn_clk_0 (ddr3_axi_clk_x2), // 300MHz clock out
.ui_addn_clk_1 (ddr3_idelay_refclk),
.ui_addn_clk_2 (),
.ui_addn_clk_3 (),
.ui_addn_clk_4 (),
.clk_ref_i (ddr3_idelay_refclk),
.ui_clk_sync_rst (ddr3_axi_rst), // Active high Reset signal synchronised to 150MHz
.aresetn (ddr3_axi_rst_reg_n),
.app_sr_req (1'b0),
.app_sr_active (),
.app_ref_req (1'b0),
.app_ref_ack (),
.app_zq_req (1'b0),
.app_zq_ack (),
.device_temp_i (12'd0),
// Slave Interface Write Address Ports
.s_axi_awid (mig_axi_wr.addr.id),
.s_axi_awaddr (mig_axi_wr.addr.addr),
.s_axi_awlen (mig_axi_wr.addr.len),
.s_axi_awsize (mig_axi_wr.addr.size),
.s_axi_awburst (mig_axi_wr.addr.burst),
.s_axi_awlock (mig_axi_wr.addr.lock),
.s_axi_awcache (mig_axi_wr.addr.cache),
.s_axi_awprot (mig_axi_wr.addr.prot),
.s_axi_awqos (mig_axi_wr.addr.qos),
.s_axi_awvalid (mig_axi_wr.addr.valid),
.s_axi_awready (mig_axi_wr.addr.ready),
// Slave Interface Write Data Ports
.s_axi_wdata (mig_axi_wr.data.data),
.s_axi_wstrb (mig_axi_wr.data.strb),
.s_axi_wlast (mig_axi_wr.data.last),
.s_axi_wvalid (mig_axi_wr.data.valid),
.s_axi_wready (mig_axi_wr.data.ready),
// Slave Interface Write Response Ports
.s_axi_bid (mig_axi_wr.resp.id),
.s_axi_bresp (mig_axi_wr.resp.resp),
.s_axi_bvalid (mig_axi_wr.resp.valid),
.s_axi_bready (mig_axi_wr.resp.ready),
// Slave Interface Read Address Ports
.s_axi_arid (mig_axi_rd.addr.id),
.s_axi_araddr (mig_axi_rd.addr.addr),
.s_axi_arlen (mig_axi_rd.addr.len),
.s_axi_arsize (mig_axi_rd.addr.size),
.s_axi_arburst (mig_axi_rd.addr.burst),
.s_axi_arlock (mig_axi_rd.addr.lock),
.s_axi_arcache (mig_axi_rd.addr.cache),
.s_axi_arprot (mig_axi_rd.addr.prot),
.s_axi_arqos (mig_axi_rd.addr.qos),
.s_axi_arvalid (mig_axi_rd.addr.valid),
.s_axi_arready (mig_axi_rd.addr.ready),
// Slave Interface Read Data Ports
.s_axi_rid (mig_axi_rd.data.id),
.s_axi_rdata (mig_axi_rd.data.data),
.s_axi_rresp (mig_axi_rd.data.resp),
.s_axi_rlast (mig_axi_rd.data.last),
.s_axi_rvalid (mig_axi_rd.data.valid),
.s_axi_rready (mig_axi_rd.data.ready),
// System Clock Ports
.sys_clk_i (sys_clk), // From external 100MHz source.
.sys_rst (sys_rst)
);
//---------------------------------------------------
// DDR3 SDRAM Models
//---------------------------------------------------
ddr3_model #(
.DEBUG(0) //Disable verbose prints
) sdram_i0 (
.rst_n (ddr3_reset_n),
.ck (ddr3_ck_p),
.ck_n (ddr3_ck_n),
.cke (ddr3_cke),
.cs_n (ddr3_cs_n),
.ras_n (ddr3_ras_n),
.cas_n (ddr3_cas_n),
.we_n (ddr3_we_n),
.dm_tdqs (ddr3_dm[1:0]),
.ba (ddr3_ba),
.addr (ddr3_addr),
.dq (ddr3_dq[15:0]),
.dqs (ddr3_dqs_p[1:0]),
.dqs_n (ddr3_dqs_n[1:0]),
.tdqs_n (), // Unused on x16
.odt (ddr3_odt)
);
ddr3_model #(
.DEBUG(0) //Disable verbose prints
) sdram_i1 (
.rst_n (ddr3_reset_n),
.ck (ddr3_ck_p),
.ck_n (ddr3_ck_n),
.cke (ddr3_cke),
.cs_n (ddr3_cs_n),
.ras_n (ddr3_ras_n),
.cas_n (ddr3_cas_n),
.we_n (ddr3_we_n),
.dm_tdqs (ddr3_dm[3:2]),
.ba (ddr3_ba),
.addr (ddr3_addr),
.dq (ddr3_dq[31:16]),
.dqs (ddr3_dqs_p[3:2]),
.dqs_n (ddr3_dqs_n[3:2]),
.tdqs_n (), // Unused on x16
.odt (ddr3_odt)
);
end endgenerate
endmodule |
module axis_dram_fifo_single
#(
parameter DIFF_CLK = 0,
parameter SR_BASE = 0
) (
input bus_clk,
input bus_rst,
input sys_clk_p,
input sys_clk_n,
input sys_rst_n,
input dma_engine_clk,
input [63:0] i_tdata,
input i_tlast,
input i_tvalid,
output i_tready,
output [63:0] o_tdata,
output o_tlast,
output o_tvalid,
input o_tready,
input set_stb,
input [7:0] set_addr,
input [31:0] set_data,
output [31:0] rb_data,
input [63:0] forced_bit_err,
output init_calib_complete
);
wire ddr3_axi_clk; // 1/4 DDR external clock rate (250MHz)
wire ddr3_axi_rst; // Synchronized to ddr_sys_clk
reg ddr3_axi_rst_reg_n; // Synchronized to ddr_sys_clk
// Misc declarations
axi4_rd_t #(.DWIDTH(64), .AWIDTH(32), .IDWIDTH(1)) dma_axi_rd(.clk(dma_engine_clk));
axi4_wr_t #(.DWIDTH(64), .AWIDTH(32), .IDWIDTH(1)) dma_axi_wr(.clk(dma_engine_clk));
axi4_rd_t #(.DWIDTH(256), .AWIDTH(32), .IDWIDTH(4)) mig_axi_rd(.clk(ddr3_axi_clk));
axi4_wr_t #(.DWIDTH(256), .AWIDTH(32), .IDWIDTH(4)) mig_axi_wr(.clk(ddr3_axi_clk));
wire [31:0] ddr3_dq; // Data pins. Input for Reads; Output for Writes.
wire [3:0] ddr3_dqs_n; // Data Strobes. Input for Reads; Output for Writes.
wire [3:0] ddr3_dqs_p;
wire [15:0] ddr3_addr; // Address
wire [2:0] ddr3_ba; // Bank Address
wire ddr3_ras_n; // Row Address Strobe.
wire ddr3_cas_n; // Column address select
wire ddr3_we_n; // Write Enable
wire ddr3_reset_n; // SDRAM reset pin.
wire [0:0] ddr3_ck_p; // Differential clock
wire [0:0] ddr3_ck_n;
wire [0:0] ddr3_cke; // Clock Enable
wire [0:0] ddr3_cs_n; // Chip Select
wire [3:0] ddr3_dm; // Data Mask [3] = UDM.U26; [2] = LDM.U26; ...
wire [0:0] ddr3_odt; // On-Die termination enable.
always @(posedge ddr3_axi_clk)
ddr3_axi_rst_reg_n <= ~ddr3_axi_rst;
axi_dma_fifo #(
.DEFAULT_BASE(30'h02000000),
.DEFAULT_MASK(30'hFF000000),
.DEFAULT_TIMEOUT(280),
.SR_BASE(SR_BASE),
.EXT_BIST(1),
.SIMULATION(1)
) axi_dma_fifo_i0 (
//
// Clocks and reset
.bus_clk (bus_clk),
.bus_reset (bus_rst),
.dram_clk (dma_engine_clk),
.dram_reset (ddr3_axi_rst),
//
// AXI Write address channel
.m_axi_awid (dma_axi_wr.addr.id),
.m_axi_awaddr (dma_axi_wr.addr.addr),
.m_axi_awlen (dma_axi_wr.addr.len),
.m_axi_awsize (dma_axi_wr.addr.size),
.m_axi_awburst (dma_axi_wr.addr.burst),
.m_axi_awlock (dma_axi_wr.addr.lock),
.m_axi_awcache (dma_axi_wr.addr.cache),
.m_axi_awprot (dma_axi_wr.addr.prot),
.m_axi_awqos (dma_axi_wr.addr.qos),
.m_axi_awregion (dma_axi_wr.addr.region),
.m_axi_awuser (dma_axi_wr.addr.user),
.m_axi_awvalid (dma_axi_wr.addr.valid),
.m_axi_awready (dma_axi_wr.addr.ready),
//
// AXI Write data channel.
.m_axi_wdata (dma_axi_wr.data.data),
.m_axi_wstrb (dma_axi_wr.data.strb),
.m_axi_wlast (dma_axi_wr.data.last),
.m_axi_wuser (dma_axi_wr.data.user),
.m_axi_wvalid (dma_axi_wr.data.valid),
.m_axi_wready (dma_axi_wr.data.ready),
//
// AXI Write response channel signals
.m_axi_bid (dma_axi_wr.resp.id),
.m_axi_bresp (dma_axi_wr.resp.resp),
.m_axi_buser (dma_axi_wr.resp.user),
.m_axi_bvalid (dma_axi_wr.resp.valid),
.m_axi_bready (dma_axi_wr.resp.ready),
//
// AXI Read address channel
.m_axi_arid (dma_axi_rd.addr.id),
.m_axi_araddr (dma_axi_rd.addr.addr),
.m_axi_arlen (dma_axi_rd.addr.len),
.m_axi_arsize (dma_axi_rd.addr.size),
.m_axi_arburst (dma_axi_rd.addr.burst),
.m_axi_arlock (dma_axi_rd.addr.lock),
.m_axi_arcache (dma_axi_rd.addr.cache),
.m_axi_arprot (dma_axi_rd.addr.prot),
.m_axi_arqos (dma_axi_rd.addr.qos),
.m_axi_arregion (dma_axi_rd.addr.region),
.m_axi_aruser (dma_axi_rd.addr.user),
.m_axi_arvalid (dma_axi_rd.addr.valid),
.m_axi_arready (dma_axi_rd.addr.ready),
//
// AXI Read data channel
.m_axi_rid (dma_axi_rd.data.id),
.m_axi_rdata (dma_axi_rd.data.data),
.m_axi_rresp (dma_axi_rd.data.resp),
.m_axi_rlast (dma_axi_rd.data.last),
.m_axi_ruser (dma_axi_rd.data.user),
.m_axi_rvalid (dma_axi_rd.data.valid),
.m_axi_rready (dma_axi_rd.data.ready),
//
// CHDR friendly AXI stream input
.i_tdata (i_tdata),
.i_tlast (i_tlast),
.i_tvalid (i_tvalid),
.i_tready (i_tready),
//
// CHDR friendly AXI Stream output
.o_tdata (o_tdata),
.o_tlast (o_tlast),
.o_tvalid (o_tvalid),
.o_tready (o_tready),
//
// Settings
.set_stb (set_stb),
.set_addr (set_addr),
.set_data (set_data),
.rb_data (rb_data),
.debug()
);
//---------------------------------------------------
// We use an interconnect to connect to FIFOs.
//---------------------------------------------------
// Attach to third slave just to validate proper ID handling in interconnect
axi_intercon_4x64_256_bd_wrapper axi_intercon_i (
//
.S00_AXI_ACLK (dma_engine_clk), // input S01_AXI_ACLK
.S00_AXI_ARESETN (~ddr3_axi_rst), // input S01_AXI_ARESETN
.S00_AXI_AWID (0), // input [0 : 0] S01_AXI_AWID
.S00_AXI_AWADDR (0), // input [31 : 0] S01_AXI_AWADDR
.S00_AXI_AWLEN (0), // input [7 : 0] S01_AXI_AWLEN
.S00_AXI_AWSIZE (0), // input [2 : 0] S01_AXI_AWSIZE
.S00_AXI_AWBURST (0), // input [1 : 0] S01_AXI_AWBURST
.S00_AXI_AWLOCK (0), // input S01_AXI_AWLOCK
.S00_AXI_AWCACHE (0), // input [3 : 0] S01_AXI_AWCACHE
.S00_AXI_AWPROT (0), // input [2 : 0] S01_AXI_AWPROT
.S00_AXI_AWQOS (0), // input [3 : 0] S01_AXI_AWQOS
.S00_AXI_AWVALID (0), // input S01_AXI_AWVALID
.S00_AXI_AWREADY (), // output S01_AXI_AWREADY
.S00_AXI_WDATA (0), // input [63 : 0] S01_AXI_WDATA
.S00_AXI_WSTRB (0), // input [7 : 0] S01_AXI_WSTRB
.S00_AXI_WLAST (0), // input S01_AXI_WLAST
.S00_AXI_WVALID (0), // input S01_AXI_WVALID
.S00_AXI_WREADY (), // output S01_AXI_WREADY
.S00_AXI_BID (), // output [0 : 0] S01_AXI_BID
.S00_AXI_BRESP (), // output [1 : 0] S01_AXI_BRESP
.S00_AXI_BVALID (), // output S01_AXI_BVALID
.S00_AXI_BREADY (1), // input S01_AXI_BREADY
.S00_AXI_ARID (0), // input [0 : 0] S01_AXI_ARID
.S00_AXI_ARADDR (0), // input [31 : 0] S01_AXI_ARADDR
.S00_AXI_ARLEN (0), // input [7 : 0] S01_AXI_ARLEN
.S00_AXI_ARSIZE (0), // input [2 : 0] S01_AXI_ARSIZE
.S00_AXI_ARBURST (0), // input [1 : 0] S01_AXI_ARBURST
.S00_AXI_ARLOCK (0), // input S01_AXI_ARLOCK
.S00_AXI_ARCACHE (0), // input [3 : 0] S01_AXI_ARCACHE
.S00_AXI_ARPROT (0), // input [2 : 0] S01_AXI_ARPROT
.S00_AXI_ARQOS (0), // input [3 : 0] S01_AXI_ARQOS
.S00_AXI_ARVALID (0), // input S01_AXI_ARVALID
.S00_AXI_ARREADY (), // output S01_AXI_ARREADY
.S00_AXI_RID (), // output [0 : 0] S01_AXI_RID
.S00_AXI_RDATA (), // output [63 : 0] S01_AXI_RDATA
.S00_AXI_RRESP (), // output [1 : 0] S01_AXI_RRESP
.S00_AXI_RLAST (), // output S01_AXI_RLAST
.S00_AXI_RVALID (), // output S01_AXI_RVALID
.S00_AXI_RREADY (1), // input S01_AXI_RREADY
//
.S01_AXI_ACLK (dma_engine_clk), // input S01_AXI_ACLK
.S01_AXI_ARESETN (~ddr3_axi_rst), // input S01_AXI_ARESETN
.S01_AXI_AWID (0), // input [0 : 0] S01_AXI_AWID
.S01_AXI_AWADDR (0), // input [31 : 0] S01_AXI_AWADDR
.S01_AXI_AWLEN (0), // input [7 : 0] S01_AXI_AWLEN
.S01_AXI_AWSIZE (0), // input [2 : 0] S01_AXI_AWSIZE
.S01_AXI_AWBURST (0), // input [1 : 0] S01_AXI_AWBURST
.S01_AXI_AWLOCK (0), // input S01_AXI_AWLOCK
.S01_AXI_AWCACHE (0), // input [3 : 0] S01_AXI_AWCACHE
.S01_AXI_AWPROT (0), // input [2 : 0] S01_AXI_AWPROT
.S01_AXI_AWQOS (0), // input [3 : 0] S01_AXI_AWQOS
.S01_AXI_AWVALID (0), // input S01_AXI_AWVALID
.S01_AXI_AWREADY (), // output S01_AXI_AWREADY
.S01_AXI_WDATA (0), // input [63 : 0] S01_AXI_WDATA
.S01_AXI_WSTRB (0), // input [7 : 0] S01_AXI_WSTRB
.S01_AXI_WLAST (0), // input S01_AXI_WLAST
.S01_AXI_WVALID (0), // input S01_AXI_WVALID
.S01_AXI_WREADY (), // output S01_AXI_WREADY
.S01_AXI_BID (), // output [0 : 0] S01_AXI_BID
.S01_AXI_BRESP (), // output [1 : 0] S01_AXI_BRESP
.S01_AXI_BVALID (), // output S01_AXI_BVALID
.S01_AXI_BREADY (1), // input S01_AXI_BREADY
.S01_AXI_ARID (0), // input [0 : 0] S01_AXI_ARID
.S01_AXI_ARADDR (0), // input [31 : 0] S01_AXI_ARADDR
.S01_AXI_ARLEN (0), // input [7 : 0] S01_AXI_ARLEN
.S01_AXI_ARSIZE (0), // input [2 : 0] S01_AXI_ARSIZE
.S01_AXI_ARBURST (0), // input [1 : 0] S01_AXI_ARBURST
.S01_AXI_ARLOCK (0), // input S01_AXI_ARLOCK
.S01_AXI_ARCACHE (0), // input [3 : 0] S01_AXI_ARCACHE
.S01_AXI_ARPROT (0), // input [2 : 0] S01_AXI_ARPROT
.S01_AXI_ARQOS (0), // input [3 : 0] S01_AXI_ARQOS
.S01_AXI_ARVALID (0), // input S01_AXI_ARVALID
.S01_AXI_ARREADY (), // output S01_AXI_ARREADY
.S01_AXI_RID (), // output [0 : 0] S01_AXI_RID
.S01_AXI_RDATA (), // output [63 : 0] S01_AXI_RDATA
.S01_AXI_RRESP (), // output [1 : 0] S01_AXI_RRESP
.S01_AXI_RLAST (), // output S01_AXI_RLAST
.S01_AXI_RVALID (), // output S01_AXI_RVALID
.S01_AXI_RREADY (1), // input S01_AXI_RREADY
//
.S02_AXI_ACLK (dma_engine_clk), // input S01_AXI_ACLK
.S02_AXI_ARESETN (~ddr3_axi_rst), // input S01_AXI_ARESETN
.S02_AXI_AWID (0), // input [0 : 0] S01_AXI_AWID
.S02_AXI_AWADDR (0), // input [31 : 0] S01_AXI_AWADDR
.S02_AXI_AWLEN (0), // input [7 : 0] S01_AXI_AWLEN
.S02_AXI_AWSIZE (0), // input [2 : 0] S01_AXI_AWSIZE
.S02_AXI_AWBURST (0), // input [1 : 0] S01_AXI_AWBURST
.S02_AXI_AWLOCK (0), // input S01_AXI_AWLOCK
.S02_AXI_AWCACHE (0), // input [3 : 0] S01_AXI_AWCACHE
.S02_AXI_AWPROT (0), // input [2 : 0] S01_AXI_AWPROT
.S02_AXI_AWQOS (0), // input [3 : 0] S01_AXI_AWQOS
.S02_AXI_AWVALID (0), // input S01_AXI_AWVALID
.S02_AXI_AWREADY (), // output S01_AXI_AWREADY
.S02_AXI_WDATA (0), // input [63 : 0] S01_AXI_WDATA
.S02_AXI_WSTRB (0), // input [7 : 0] S01_AXI_WSTRB
.S02_AXI_WLAST (0), // input S01_AXI_WLAST
.S02_AXI_WVALID (0), // input S01_AXI_WVALID
.S02_AXI_WREADY (), // output S01_AXI_WREADY
.S02_AXI_BID (), // output [0 : 0] S01_AXI_BID
.S02_AXI_BRESP (), // output [1 : 0] S01_AXI_BRESP
.S02_AXI_BVALID (), // output S01_AXI_BVALID
.S02_AXI_BREADY (1), // input S01_AXI_BREADY
.S02_AXI_ARID (0), // input [0 : 0] S01_AXI_ARID
.S02_AXI_ARADDR (0), // input [31 : 0] S01_AXI_ARADDR
.S02_AXI_ARLEN (0), // input [7 : 0] S01_AXI_ARLEN
.S02_AXI_ARSIZE (0), // input [2 : 0] S01_AXI_ARSIZE
.S02_AXI_ARBURST (0), // input [1 : 0] S01_AXI_ARBURST
.S02_AXI_ARLOCK (0), // input S01_AXI_ARLOCK
.S02_AXI_ARCACHE (0), // input [3 : 0] S01_AXI_ARCACHE
.S02_AXI_ARPROT (0), // input [2 : 0] S01_AXI_ARPROT
.S02_AXI_ARQOS (0), // input [3 : 0] S01_AXI_ARQOS
.S02_AXI_ARVALID (0), // input S01_AXI_ARVALID
.S02_AXI_ARREADY (), // output S01_AXI_ARREADY
.S02_AXI_RID (), // output [0 : 0] S01_AXI_RID
.S02_AXI_RDATA (), // output [63 : 0] S01_AXI_RDATA
.S02_AXI_RRESP (), // output [1 : 0] S01_AXI_RRESP
.S02_AXI_RLAST (), // output S01_AXI_RLAST
.S02_AXI_RVALID (), // output S01_AXI_RVALID
.S02_AXI_RREADY (1), // input S01_AXI_RREADY
//
.S03_AXI_ACLK (dma_engine_clk), // input S00_AXI_ACLK
.S03_AXI_ARESETN (~ddr3_axi_rst), // input S00_AXI_ARESETN
.S03_AXI_AWID (dma_axi_wr.addr.id), // input [0 : 0] S00_AXI_AWID
.S03_AXI_AWADDR (dma_axi_wr.addr.addr), // input [31 : 0] S00_AXI_AWADDR
.S03_AXI_AWLEN (dma_axi_wr.addr.len), // input [7 : 0] S00_AXI_AWLEN
.S03_AXI_AWSIZE (dma_axi_wr.addr.size), // input [2 : 0] S00_AXI_AWSIZE
.S03_AXI_AWBURST (dma_axi_wr.addr.burst), // input [1 : 0] S00_AXI_AWBURST
.S03_AXI_AWLOCK (dma_axi_wr.addr.lock), // input S00_AXI_AWLOCK
.S03_AXI_AWCACHE (dma_axi_wr.addr.cache), // input [3 : 0] S00_AXI_AWCACHE
.S03_AXI_AWPROT (dma_axi_wr.addr.prot), // input [2 : 0] S00_AXI_AWPROT
.S03_AXI_AWQOS (dma_axi_wr.addr.qos), // input [3 : 0] S00_AXI_AWQOS
.S03_AXI_AWVALID (dma_axi_wr.addr.valid), // input S00_AXI_AWVALID
.S03_AXI_AWREADY (dma_axi_wr.addr.ready), // output S00_AXI_AWREADY
.S03_AXI_WDATA (dma_axi_wr.data.data ^ forced_bit_err), // input [63 : 0] S00_AXI_WDATA
.S03_AXI_WSTRB (dma_axi_wr.data.strb), // input [7 : 0] S00_AXI_WSTRB
.S03_AXI_WLAST (dma_axi_wr.data.last), // input S00_AXI_WLAST
.S03_AXI_WVALID (dma_axi_wr.data.valid), // input S00_AXI_WVALID
.S03_AXI_WREADY (dma_axi_wr.data.ready), // output S00_AXI_WREADY
.S03_AXI_BID (dma_axi_wr.resp.id), // output [0 : 0] S00_AXI_BID
.S03_AXI_BRESP (dma_axi_wr.resp.resp), // output [1 : 0] S00_AXI_BRESP
.S03_AXI_BVALID (dma_axi_wr.resp.valid), // output S00_AXI_BVALID
.S03_AXI_BREADY (dma_axi_wr.resp.ready), // input S00_AXI_BREADY
.S03_AXI_ARID (dma_axi_rd.addr.id), // input [0 : 0] S00_AXI_ARID
.S03_AXI_ARADDR (dma_axi_rd.addr.addr), // input [31 : 0] S00_AXI_ARADDR
.S03_AXI_ARLEN (dma_axi_rd.addr.len), // input [7 : 0] S00_AXI_ARLEN
.S03_AXI_ARSIZE (dma_axi_rd.addr.size), // input [2 : 0] S00_AXI_ARSIZE
.S03_AXI_ARBURST (dma_axi_rd.addr.burst), // input [1 : 0] S00_AXI_ARBURST
.S03_AXI_ARLOCK (dma_axi_rd.addr.lock), // input S00_AXI_ARLOCK
.S03_AXI_ARCACHE (dma_axi_rd.addr.cache), // input [3 : 0] S00_AXI_ARCACHE
.S03_AXI_ARPROT (dma_axi_rd.addr.prot), // input [2 : 0] S00_AXI_ARPROT
.S03_AXI_ARQOS (dma_axi_rd.addr.qos), // input [3 : 0] S00_AXI_ARQOS
.S03_AXI_ARVALID (dma_axi_rd.addr.valid), // input S00_AXI_ARVALID
.S03_AXI_ARREADY (dma_axi_rd.addr.ready), // output S00_AXI_ARREADY
.S03_AXI_RID (dma_axi_rd.data.id), // output [0 : 0] S00_AXI_RID
.S03_AXI_RDATA (dma_axi_rd.data.data), // output [63 : 0] S00_AXI_RDATA
.S03_AXI_RRESP (dma_axi_rd.data.resp), // output [1 : 0] S00_AXI_RRESP
.S03_AXI_RLAST (dma_axi_rd.data.last), // output S00_AXI_RLAST
.S03_AXI_RVALID (dma_axi_rd.data.valid), // output S00_AXI_RVALID
.S03_AXI_RREADY (dma_axi_rd.data.ready), // input S00_AXI_RREADY
//
.M00_AXI_ACLK (ddr3_axi_clk), // input M00_AXI_ACLK
.M00_AXI_ARESETN (~ddr3_axi_rst), // input M00_AXI_ARESETN
.M00_AXI_AWID (mig_axi_wr.addr.id), // output [3 : 0] M00_AXI_AWID
.M00_AXI_AWADDR (mig_axi_wr.addr.addr), // output [31 : 0] M00_AXI_AWADDR
.M00_AXI_AWLEN (mig_axi_wr.addr.len), // output [7 : 0] M00_AXI_AWLEN
.M00_AXI_AWSIZE (mig_axi_wr.addr.size), // output [2 : 0] M00_AXI_AWSIZE
.M00_AXI_AWBURST (mig_axi_wr.addr.burst), // output [1 : 0] M00_AXI_AWBURST
.M00_AXI_AWLOCK (mig_axi_wr.addr.lock), // output M00_AXI_AWLOCK
.M00_AXI_AWCACHE (mig_axi_wr.addr.cache), // output [3 : 0] M00_AXI_AWCACHE
.M00_AXI_AWPROT (mig_axi_wr.addr.prot), // output [2 : 0] M00_AXI_AWPROT
.M00_AXI_AWQOS (mig_axi_wr.addr.qos), // output [3 : 0] M00_AXI_AWQOS
.M00_AXI_AWVALID (mig_axi_wr.addr.valid), // output M00_AXI_AWVALID
.M00_AXI_AWREADY (mig_axi_wr.addr.ready), // input M00_AXI_AWREADY
.M00_AXI_WDATA (mig_axi_wr.data.data), // output [127 : 0] M00_AXI_WDATA
.M00_AXI_WSTRB (mig_axi_wr.data.strb), // output [15 : 0] M00_AXI_WSTRB
.M00_AXI_WLAST (mig_axi_wr.data.last), // output M00_AXI_WLAST
.M00_AXI_WVALID (mig_axi_wr.data.valid), // output M00_AXI_WVALID
.M00_AXI_WREADY (mig_axi_wr.data.ready), // input M00_AXI_WREADY
.M00_AXI_BID (mig_axi_wr.resp.id), // input [3 : 0] M00_AXI_BID
.M00_AXI_BRESP (mig_axi_wr.resp.resp), // input [1 : 0] M00_AXI_BRESP
.M00_AXI_BVALID (mig_axi_wr.resp.valid), // input M00_AXI_BVALID
.M00_AXI_BREADY (mig_axi_wr.resp.ready), // output M00_AXI_BREADY
.M00_AXI_ARID (mig_axi_rd.addr.id), // output [3 : 0] M00_AXI_ARID
.M00_AXI_ARADDR (mig_axi_rd.addr.addr), // output [31 : 0] M00_AXI_ARADDR
.M00_AXI_ARLEN (mig_axi_rd.addr.len), // output [7 : 0] M00_AXI_ARLEN
.M00_AXI_ARSIZE (mig_axi_rd.addr.size), // output [2 : 0] M00_AXI_ARSIZE
.M00_AXI_ARBURST (mig_axi_rd.addr.burst), // output [1 : 0] M00_AXI_ARBURST
.M00_AXI_ARLOCK (mig_axi_rd.addr.lock), // output M00_AXI_ARLOCK
.M00_AXI_ARCACHE (mig_axi_rd.addr.cache), // output [3 : 0] M00_AXI_ARCACHE
.M00_AXI_ARPROT (mig_axi_rd.addr.prot), // output [2 : 0] M00_AXI_ARPROT
.M00_AXI_ARQOS (mig_axi_rd.addr.qos), // output [3 : 0] M00_AXI_ARQOS
.M00_AXI_ARVALID (mig_axi_rd.addr.valid), // output M00_AXI_ARVALID
.M00_AXI_ARREADY (mig_axi_rd.addr.ready), // input M00_AXI_ARREADY
.M00_AXI_RID (mig_axi_rd.data.id), // input [3 : 0] M00_AXI_RID
.M00_AXI_RDATA (mig_axi_rd.data.data), // input [127 : 0] M00_AXI_RDATA
.M00_AXI_RRESP (mig_axi_rd.data.resp), // input [1 : 0] M00_AXI_RRESP
.M00_AXI_RLAST (mig_axi_rd.data.last), // input M00_AXI_RLAST
.M00_AXI_RVALID (mig_axi_rd.data.valid), // input M00_AXI_RVALID
.M00_AXI_RREADY (mig_axi_rd.data.ready) // output M00_AXI_RREADY
);
//---------------------------------------------------
// MIG
//---------------------------------------------------
ddr3_32bit ddr_mig_i (
// Memory interface ports
.ddr3_addr (ddr3_addr),
.ddr3_ba (ddr3_ba),
.ddr3_cas_n (ddr3_cas_n),
.ddr3_ck_n (ddr3_ck_n),
.ddr3_ck_p (ddr3_ck_p),
.ddr3_cke (ddr3_cke),
.ddr3_ras_n (ddr3_ras_n),
.ddr3_reset_n (ddr3_reset_n),
.ddr3_we_n (ddr3_we_n),
.ddr3_dq (ddr3_dq),
.ddr3_dqs_n (ddr3_dqs_n),
.ddr3_dqs_p (ddr3_dqs_p),
.init_calib_complete (init_calib_complete),
.ddr3_cs_n (ddr3_cs_n),
.ddr3_dm (ddr3_dm),
.ddr3_odt (ddr3_odt),
// Application interface ports
.ui_clk (ddr3_axi_clk), // 150MHz clock out
.ui_clk_sync_rst (ddr3_axi_rst), // Active high Reset signal synchronised to 150MHz
.aresetn (ddr3_axi_rst_reg_n),
.app_sr_req (1'b0),
.app_sr_active (),
.app_ref_req (1'b0),
.app_ref_ack (),
.app_zq_req (1'b0),
.app_zq_ack (),
// Slave Interface Write Address Ports
.s_axi_awid (mig_axi_wr.addr.id),
.s_axi_awaddr (mig_axi_wr.addr.addr),
.s_axi_awlen (mig_axi_wr.addr.len),
.s_axi_awsize (mig_axi_wr.addr.size),
.s_axi_awburst (mig_axi_wr.addr.burst),
.s_axi_awlock (mig_axi_wr.addr.lock),
.s_axi_awcache (mig_axi_wr.addr.cache),
.s_axi_awprot (mig_axi_wr.addr.prot),
.s_axi_awqos (mig_axi_wr.addr.qos),
.s_axi_awvalid (mig_axi_wr.addr.valid),
.s_axi_awready (mig_axi_wr.addr.ready),
// Slave Interface Write Data Ports
.s_axi_wdata (mig_axi_wr.data.data),
.s_axi_wstrb (mig_axi_wr.data.strb),
.s_axi_wlast (mig_axi_wr.data.last),
.s_axi_wvalid (mig_axi_wr.data.valid),
.s_axi_wready (mig_axi_wr.data.ready),
// Slave Interface Write Response Ports
.s_axi_bid (mig_axi_wr.resp.id),
.s_axi_bresp (mig_axi_wr.resp.resp),
.s_axi_bvalid (mig_axi_wr.resp.valid),
.s_axi_bready (mig_axi_wr.resp.ready),
// Slave Interface Read Address Ports
.s_axi_arid (mig_axi_rd.addr.id),
.s_axi_araddr (mig_axi_rd.addr.addr),
.s_axi_arlen (mig_axi_rd.addr.len),
.s_axi_arsize (mig_axi_rd.addr.size),
.s_axi_arburst (mig_axi_rd.addr.burst),
.s_axi_arlock (mig_axi_rd.addr.lock),
.s_axi_arcache (mig_axi_rd.addr.cache),
.s_axi_arprot (mig_axi_rd.addr.prot),
.s_axi_arqos (mig_axi_rd.addr.qos),
.s_axi_arvalid (mig_axi_rd.addr.valid),
.s_axi_arready (mig_axi_rd.addr.ready),
// Slave Interface Read Data Ports
.s_axi_rid (mig_axi_rd.data.id),
.s_axi_rdata (mig_axi_rd.data.data),
.s_axi_rresp (mig_axi_rd.data.resp),
.s_axi_rlast (mig_axi_rd.data.last),
.s_axi_rvalid (mig_axi_rd.data.valid),
.s_axi_rready (mig_axi_rd.data.ready),
// System Clock Ports
.sys_clk_p (sys_clk_p), // From external 100MHz source.
.sys_clk_n (sys_clk_n), // From external 100MHz source.
.clk_ref_i (bus_clk),
.sys_rst (sys_rst_n) // IJB. Poorly named active low. Should change RST_ACT_LOW.
);
//---------------------------------------------------
// DDR3 SDRAM Models
//---------------------------------------------------
ddr3_model #(
.DEBUG(0) //Disable verbose prints
) sdram_i0 (
.rst_n (ddr3_reset_n),
.ck (ddr3_ck_p),
.ck_n (ddr3_ck_n),
.cke (ddr3_cke),
.cs_n (ddr3_cs_n),
.ras_n (ddr3_ras_n),
.cas_n (ddr3_cas_n),
.we_n (ddr3_we_n),
.dm_tdqs (ddr3_dm[1:0]),
.ba (ddr3_ba),
.addr (ddr3_addr),
.dq (ddr3_dq[15:0]),
.dqs (ddr3_dqs_p[1:0]),
.dqs_n (ddr3_dqs_n[1:0]),
.tdqs_n (), // Unused on x16
.odt (ddr3_odt)
);
ddr3_model #(
.DEBUG(0) //Disable verbose prints
) sdram_i1 (
.rst_n (ddr3_reset_n),
.ck (ddr3_ck_p),
.ck_n (ddr3_ck_n),
.cke (ddr3_cke),
.cs_n (ddr3_cs_n),
.ras_n (ddr3_ras_n),
.cas_n (ddr3_cas_n),
.we_n (ddr3_we_n),
.dm_tdqs (ddr3_dm[3:2]),
.ba (ddr3_ba),
.addr (ddr3_addr),
.dq (ddr3_dq[31:16]),
.dqs (ddr3_dqs_p[3:2]),
.dqs_n (ddr3_dqs_n[3:2]),
.tdqs_n (), // Unused on x16
.odt (ddr3_odt)
);
endmodule |
module noc_block_eq_tb;
`TEST_BENCH_INIT("noc_block_eq_tb", `NUM_TEST_CASES, `NS_PER_TICK);
`RFNOC_SIM_INIT(1, 166.67, 200);
`RFNOC_ADD_BLOCK(noc_block_eq, 0);
localparam PACKET_SIZE = 64;
//----------------------------------------------------------------------------
// Stimulus
//----------------------------------------------------------------------------
shortint long_preamble[PACKET_SIZE] = '{0, 0, 0, 0, 0, 0, 1, 1, -1, -1,
1, 1, -1, 1, -1, 1, 1, 1, 1, 1, 1, -1, -1, 1, 1, -1, 1, -1, 1, 1, 1, 1, 0,
1, -1, -1, 1, 1, -1, 1, -1, 1, -1, -1, -1, -1, -1, 1, 1, -1, -1, 1, -1, 1,
-1, 1, 1, 1, 1, 0, 0, 0, 0, 0};
initial begin
logic [63:0] header;
cvita_pkt_t packet;
reg [63:0] mem [0:65535];
int file;
int file_length;
// Prepare preamble: Scale to full range
foreach(long_preamble[i]) begin
if(long_preamble[i] == 1)
long_preamble[i] = 32767;
else if(long_preamble[i] == -1)
long_preamble[i] = -32768;
end
while(bus_rst) @(posedge bus_clk);
while(ce_rst) @(posedge ce_clk);
repeat(10) @(posedge bus_clk);
// Test bench -> Equalizer -> Test bench
`RFNOC_CONNECT_BLOCK_PORT(noc_block_tb, 1, noc_block_eq, 0, PACKET_SIZE*4);
`RFNOC_CONNECT_BLOCK_PORT(noc_block_eq, 0, noc_block_tb, 1, PACKET_SIZE*4);
// Setup equalizer
tb_next_dst = sid_noc_block_eq;
repeat(10) @(posedge bus_clk);
//-------------------------------------------------------------------------
// Setup header
header = flatten_chdr_no_ts('{pkt_type: DATA, has_time: 0, eob: 1,
seqno: 12'h0, length: 8, src_sid: sid_noc_block_tb,
dst_sid: sid_noc_block_eq, timestamp: 64'h0});
packet.push_back(header);
// Add preamble
for(int i = 0; i < PACKET_SIZE - 1; i = i + 2) begin
logic [63:0] preamble;
preamble = {shortint'(long_preamble[i]), shortint'(0),
shortint'(long_preamble[i + 1]), shortint'(0)};
packet.push_back(preamble);
end
// Send preamble
tb_cvita_data.push_pkt(packet);
packet = {};
//-------------------------------------------------------------------------
// Change header
header[60] = 0; // EOB
packet.push_back(header);
// Add data
for(int i = 0; i < PACKET_SIZE / 2; ++i) begin
logic [63:0] data;
shortint pos;
shortint neg;
pos = 32767;
neg = -32768;
data = {pos, neg, neg, pos};
packet.push_back(data);
end
// Send data
tb_cvita_data.push_pkt(packet);
packet = {};
//-------------------------------------------------------------------------
#100000;
// Read file
file = $fopen("../../../../test-int16.bin", "r");
file_length = $fread(mem, file);
$display("Read %d lines", file_length);
$fclose(file);
// Change header
header[60] = 1; // EOB
packet.push_back(header);
// Add preamble
for(int i = 0; i < PACKET_SIZE / 2; ++i) begin
packet.push_back(mem[i]);
end
// Send preamble
tb_cvita_data.push_pkt(packet);
packet = {};
//-------------------------------------------------------------------------
// Change header
header[60] = 0; // EOB
packet.push_back(header);
// Add data
for (int i = PACKET_SIZE / 2; i < PACKET_SIZE; ++i) begin
packet.push_back(mem[i]);
end
// Send data
tb_cvita_data.push_pkt(packet);
packet = {};
//-------------------------------------------------------------------------
#100000;
$finish;
end
//----------------------------------------------------------------------------
// Verification
//----------------------------------------------------------------------------
initial begin : tb_main
logic [63:0] data;
cvita_pkt_t packet;
reg [63:0] comp [0:65535];
int file;
int file_length;
// Read file
file = $fopen("../../../../comp-int16.bin", "r");
file_length = $fread(comp, file);
$display("Read %d lines", file_length);
$fclose(file);
`TEST_CASE_START("Wait for reset");
while (bus_rst) @(posedge bus_clk);
while (ce_rst) @(posedge ce_clk);
`TEST_CASE_DONE(~bus_rst & ~ce_rst);
#70000;
packet = {};
`TEST_CASE_START("Receive data");
tb_cvita_data.pull_pkt(packet);
$display("Header: %H", packet.pop_front());
foreach(packet[i]) begin
data = packet[i];
$display("Received[%d]: %d, %d | %d, %d (%h)", shortint'(i),
shortint'(data[63:48]), shortint'(data[47:32]), shortint'(data[31:16]),
shortint'(data[15:0]), data);
end
`TEST_CASE_DONE(1);
packet = {};
`TEST_CASE_START("Receive file data");
tb_cvita_data.pull_pkt(packet);
$display("Header: %H", packet.pop_front());
foreach(packet[i]) begin
data = packet[i];
$display("Received[%d]: %d, %d | %d, %d (%h)", shortint'(i),
shortint'(data[63:48]), shortint'(data[47:32]), shortint'(data[31:16]),
shortint'(data[15:0]), data);
end
`TEST_CASE_DONE(1);
// End simulation
#1000;
$finish;
end
endmodule |
module Hq2x_optimized
#(
parameter LENGTH = 858,
parameter HALF_DEPTH = 0
)
(
input clk,
input ce_x4,
input [DWIDTH:0] inputpixel,
input mono,
input disable_hq2x,
input reset_frame,
input reset_line,
input [1:0] read_y,
input hblank,
output [DWIDTH:0] outpixel /*verilator public*/
);
localparam AWIDTH = $clog2(LENGTH)-1;
localparam DWIDTH = HALF_DEPTH ? 11 : 23;
localparam DWIDTH1 = DWIDTH+1;
localparam EXACT_BUFFER = 1;
`HQ_TABLE_TYPE [5:0] hqTable[256] = '{
19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 47, 35, 23, 15, 55, 39,
19, 19, 26, 58, 19, 19, 26, 58, 23, 15, 35, 35, 23, 15, 7, 35,
19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 55, 39, 23, 15, 51, 43,
19, 19, 26, 58, 19, 19, 26, 58, 23, 15, 51, 35, 23, 15, 7, 43,
19, 19, 26, 11, 19, 19, 26, 11, 23, 61, 35, 35, 23, 61, 51, 35,
19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 35,
19, 19, 26, 11, 19, 19, 26, 11, 23, 61, 7, 35, 23, 61, 7, 43,
19, 19, 26, 11, 19, 19, 26, 58, 23, 15, 51, 35, 23, 61, 7, 43,
19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 47, 35, 23, 15, 55, 39,
19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 35,
19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 55, 39, 23, 15, 51, 43,
19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 39, 23, 15, 7, 43,
19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 39,
19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 7, 35,
19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 7, 43,
19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 7, 35, 23, 15, 7, 43
};
reg [23:0] Prev0, Prev1, Prev2, Curr0, Curr1, Curr2, Next0, Next1, Next2;
reg [23:0] A, B, D, F, G, H;
reg [7:0] pattern, nextpatt;
reg [1:0] cyc;
reg curbuf;
reg prevbuf = 0;
wire iobuf = !curbuf;
wire diff0, diff1;
DiffCheck diffcheck0(
clk,
Curr1,
(cyc == 0) ? Prev0 :
(cyc == 1) ? Curr0 :
(cyc == 2) ? Prev2 : Next1,
diff0
);
DiffCheck diffcheck1(
clk,
Curr1,
(cyc == 0) ? Prev1 :
(cyc == 1) ? Next0 :
(cyc == 2) ? Curr2 : Next2,
diff1
);
wire [7:0] new_pattern = {diff1, diff0, pattern[7:2]};
wire [23:0] X = (cyc == 0) ? A : (cyc == 1) ? Prev1 : (cyc == 2) ? Next1 : G;
wire [23:0] blend_result_pre;
Blend blender(clk, hqTable[nextpatt], disable_hq2x, Curr0_d, X_d, B_d, D_d, F_d, H_d, blend_result_pre);
reg [23:0] Curr0_d, X_d, B_d, D_d, F_d, H_d;
delayline #(
.WIDTH(6*24),
.CYCLES(4)
) blender_queue (
.clock(clk),
.in({ Curr0, X, B, D, F, H }),
.out({ Curr0_d, X_d, B_d, D_d, F_d, H_d })
);
wire [DWIDTH:0] Curr20tmp;
wire [23:0] Curr20 = HALF_DEPTH ? h2rgb(Curr20tmp) : Curr20tmp;
wire [DWIDTH:0] Curr21tmp;
wire [23:0] Curr21 = HALF_DEPTH ? h2rgb(Curr21tmp) : Curr21tmp;
reg [AWIDTH:0] wrin_addr2;
reg [DWIDTH:0] wrpix;
reg wrin_en;
function [23:0] h2rgb;
input [11:0] v;
begin
h2rgb = mono ? {v[7:0], v[7:0], v[7:0]} : {v[11:8],v[11:8],v[7:4],v[7:4],v[3:0],v[3:0]};
end
endfunction
function [11:0] rgb2h;
input [23:0] v;
begin
rgb2h = mono ? {4'b0000, v[23:20], v[19:16]} : {v[23:20], v[15:12], v[7:4]};
end
endfunction
hq2x_in #(.LENGTH(LENGTH), .DWIDTH(DWIDTH)) hq2x_in
(
.clk(clk),
.rdaddr(offs),
.rdbuf0(prevbuf),
.rdbuf1(curbuf),
.q0(Curr20tmp),
.q1(Curr21tmp),
.wraddr(wrin_addr2),
.wrbuf(iobuf),
.data(wrpix),
.wren(wrin_en)
);
reg [AWIDTH+1:0] read_x /*verilator public*/;
reg [AWIDTH+1:0] wrout_addr, wrout_addr_delayed;
reg wrout_en, wrout_en_delayed;
reg [DWIDTH1*4-1:0] wrdata, wrdata_pre;
wire [DWIDTH1*4-1:0] outpixel_x4;
reg [DWIDTH1*2-1:0] outpixel_x2;
delayline #(
.WIDTH(AWIDTH+1+1+1),
.CYCLES(22)
) wrdl (
.clock(clk),
.in({ wrout_en, wrout_addr }),
.out({ wrout_en_delayed, wrout_addr_delayed })
);
assign outpixel = read_x[0] ? outpixel_x2[DWIDTH1*2-1:DWIDTH1] : outpixel_x2[DWIDTH:0];
hq2x_buf #(.NUMWORDS(EXACT_BUFFER ? LENGTH : LENGTH*2), .AWIDTH(AWIDTH+1), .DWIDTH(DWIDTH1*4-1)) hq2x_out
(
.clock(clk),
.rdaddress(EXACT_BUFFER ? read_x[AWIDTH+1:1] : {read_x[AWIDTH+1:1],read_y[1]}),
.q(outpixel_x4),
.data(wrdata),
.wraddress(wrout_addr_delayed),
.wren(wrout_en_delayed)
);
wire [DWIDTH:0] blend_result = HALF_DEPTH ? rgb2h(blend_result_pre) : blend_result_pre[DWIDTH:0];
reg [AWIDTH:0] offs /*verilator public*/;
always @(posedge clk) begin
reg old_reset_line;
reg old_reset_frame;
wrout_en <= 0;
wrin_en <= 0;
if(ce_x4) begin
pattern <= new_pattern;
if(read_x[0]) outpixel_x2 <= read_y[0] ? outpixel_x4[DWIDTH1*4-1:DWIDTH1*2] : outpixel_x4[DWIDTH1*2-1:0];
if(~&offs) begin
if (cyc == 1) begin
Prev2 <= Curr20;
Curr2 <= Curr21;
Next2 <= HALF_DEPTH ? h2rgb(inputpixel) : inputpixel;
wrpix <= inputpixel;
wrin_addr2 <= offs;
wrin_en <= 1;
end
case({cyc[1],^cyc})
0: wrdata[DWIDTH1+DWIDTH:DWIDTH1] <= blend_result;
1: wrdata[DWIDTH1*3+DWIDTH:DWIDTH1*3] <= blend_result;
2: wrdata[DWIDTH:0] <= blend_result;
3: wrdata[DWIDTH1*2+DWIDTH:DWIDTH1*2] <= blend_result;
endcase
if(cyc==3) begin
offs <= offs + 1'd1;
wrout_addr <= EXACT_BUFFER ? offs : {offs, curbuf};
wrout_en <= 1;
end
end
if(cyc==0) begin
nextpatt <= {new_pattern[7:6], new_pattern[3], new_pattern[5], new_pattern[2], new_pattern[4], new_pattern[1:0]};
end else begin
nextpatt <= {nextpatt[5], nextpatt[3], nextpatt[0], nextpatt[6], nextpatt[1], nextpatt[7], nextpatt[4], nextpatt[2]};
end
if(cyc==3) begin
{A, G} <= {Prev0, Next0};
{B, F, H, D} <= {Prev1, Curr2, Next1, Curr0};
{Prev0, Prev1} <= {Prev1, Prev2};
{Curr0, Curr1} <= {Curr1, Curr2};
{Next0, Next1} <= {Next1, Next2};
end else begin
{B, F, H, D} <= {F, H, D, B};
end
cyc <= cyc + 1'b1;
if(old_reset_line && ~reset_line) begin
old_reset_frame <= reset_frame;
offs <= 0;
cyc <= 0;
curbuf <= ~curbuf;
prevbuf <= curbuf;
{Prev0, Prev1, Prev2, Curr0, Curr1, Curr2, Next0, Next1, Next2} <= '0;
if(old_reset_frame & ~reset_frame) begin
curbuf <= 0;
prevbuf <= 0;
end
end
if(~hblank & ~&read_x) read_x <= read_x + 1'd1;
if(hblank) read_x <= 0;
old_reset_line <= reset_line;
end
end
endmodule |
module hq2x_in #(parameter LENGTH, parameter DWIDTH)
(
input clk,
input [AWIDTH:0] rdaddr,
input rdbuf0, rdbuf1,
output[DWIDTH:0] q0,q1,
input [AWIDTH:0] wraddr,
input wrbuf,
input [DWIDTH:0] data,
input wren
);
localparam AWIDTH = $clog2(LENGTH)-1;
wire [DWIDTH:0] out[2];
assign q0 = out[rdbuf0];
assign q1 = out[rdbuf1];
hq2x_buf #(.NUMWORDS(LENGTH), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf0(clk,data,rdaddr,wraddr,wren && (wrbuf == 0),out[0]);
hq2x_buf #(.NUMWORDS(LENGTH), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf1(clk,data,rdaddr,wraddr,wren && (wrbuf == 1),out[1]);
endmodule |
module hq2x_buf #(parameter NUMWORDS, parameter AWIDTH, parameter DWIDTH)
(
input clock,
input [DWIDTH:0] data /*verilator public*/,
input [AWIDTH:0] rdaddress /*verilator public*/,
input [AWIDTH:0] wraddress /*verilator public*/,
input wren /*verilator public*/,
output logic [DWIDTH:0] q /*verilator public*/
);
(* max_depth = 1024 *) (* ramstyle = "no_rw_check" *) logic [DWIDTH:0] ram[0:NUMWORDS-1];
always_ff@(posedge clock) begin
if(wren) ram[wraddress] <= data;
q <= ram[rdaddress];
end
endmodule |
module DiffCheck
(
input clock,
input [23:0] rgb1,
input [23:0] rgb2,
output reg result
);
reg [7:0] r, g, b, r_q, g_q, b_q;
reg [8:0] t, gx, u, t_q, gx_q;
reg [9:0] y, v;
// if y is inside (-96..96)
reg y_inside, u_inside, v_inside;
always_ff @(posedge clock) begin
// stage 1
r <= rgb1[7:1] - rgb2[7:1];
g <= rgb1[15:9] - rgb2[15:9];
b <= rgb1[23:17] - rgb2[23:17];
// stage 2
t <= $signed(r) + $signed(b);
gx <= { g[7], g };
{ r_q, g_q, b_q } <= { r, g, b };
// stage 3
y <= $signed(t) + $signed(gx);
u <= $signed(r_q) - $signed(b_q);
v <= $signed({g_q, 1'b0}) - $signed(t);
// stage 4
// if y is inside (-96..96)
y_inside <= (y < 10'h60 || y >= 10'h3a0);
// if u is inside (-16, 16)
u_inside <= (u < 9'h10 || u >= 9'h1f0);
// if v is inside (-24, 24)
v_inside <= (v < 10'h18 || v >= 10'h3e8);
// stage 5
result <= !(y_inside && u_inside && v_inside);
end
endmodule |
module InnerBlend
(
input clock,
input [8:0] Op,
input [7:0] A,
input [7:0] B,
input [7:0] C,
output reg [7:0] O
);
function [10:0] mul8x3;
input [7:0] op1;
input [2:0] op2;
begin
mul8x3 = 11'd0;
if(op2[0]) mul8x3 = mul8x3 + op1;
if(op2[1]) mul8x3 = mul8x3 + {op1, 1'b0};
if(op2[2]) mul8x3 = mul8x3 + {op1, 2'b00};
end
endfunction
reg OpOnes;
reg [10:0] Amul, Bmul, Cmul;
reg [10:0] At, Bt, Ct;
reg [11:0] Res;
reg [8:0] Op_q, Op_q_q, Op_q_q_q, Op_q_q_q_q;
reg [7:0] A_q, A_q_q, A_q_q_q, A_q_q_q_q, B_q, B_q_q, C_q, C_q_q;
always_ff @(posedge clock) begin
// stage 1
{ Op_q, A_q, B_q, C_q } <= { Op, A, B, C };
// stage 2
OpOnes <= Op_q[4];
Amul <= mul8x3(A_q, Op_q[7:5]);
Bmul <= mul8x3(B_q, {Op_q[3:2], 1'b0});
Cmul <= mul8x3(C_q, {Op_q[1:0], 1'b0});
{ Op_q_q, A_q_q, B_q_q, C_q_q } <= { Op_q, A_q, B_q, C_q };
// stage 3
At <= Amul;
Bt <= (OpOnes == 0) ? Bmul : {3'b0, B_q_q};
Ct <= (OpOnes == 0) ? Cmul : {3'b0, C_q_q};
{ Op_q_q_q, A_q_q_q } <= { Op_q_q, A_q_q };
// stage 4
Res <= {At, 1'b0} + Bt + Ct;
{ Op_q_q_q_q, A_q_q_q_q } <= { Op_q_q_q, A_q_q_q };
// stage 5
O <= Op_q_q_q_q[8] ? A_q_q_q_q : Res[11:4];
end
endmodule |
module Blend
(
input clock,
input [5:0] rule,
input disable_hq2x,
input [23:0] E,
input [23:0] A,
input [23:0] B,
input [23:0] D,
input [23:0] F,
input [23:0] H,
output reg [23:0] Result
);
reg [23:0] E_reg, A_reg, B_reg, D_reg, F_reg, H_reg;
reg [23:0] E_reg_d, A_reg_d, B_reg_d, D_reg_d, F_reg_q, H_reg_d;
reg [23:0] Input1, Input2, Input3;
reg [23:0] res_out, res_out_q, res_out_q_q, res_out_q_q_q, res_out_q_q_q_q;
reg [1:0] input_ctrl;
reg [8:0] op, op_q;
reg [5:0] rule_reg, rule_1, rule_2, rule_3, rule_d;
localparam BLEND0 = 9'b1_xxx_x_xx_xx; // 0: A
localparam BLEND1 = 9'b0_110_0_10_00; // 1: (A * 12 + B * 4) >> 4
localparam BLEND2 = 9'b0_100_0_10_10; // 2: (A * 8 + B * 4 + C * 4) >> 4
localparam BLEND3 = 9'b0_101_0_10_01; // 3: (A * 10 + B * 4 + C * 2) >> 4
localparam BLEND4 = 9'b0_110_0_01_01; // 4: (A * 12 + B * 2 + C * 2) >> 4
localparam BLEND5 = 9'b0_010_0_11_11; // 5: (A * 4 + (B + C) * 6) >> 4
localparam BLEND6 = 9'b0_111_1_xx_xx; // 6: (A * 14 + B + C) >> 4
localparam AB = 2'b00;
localparam AD = 2'b01;
localparam DB = 2'b10;
localparam BD = 2'b11;
wire is_diff;
DiffCheck diff_checker(clock, rule_reg[1] ? B_reg : H_reg, rule_reg[0] ? D_reg : F_reg, is_diff);
delayline #(
.WIDTH(6*24),
.CYCLES(5)
) delay1 (
.clock(clock),
.in({ E_reg, A_reg, B_reg, D_reg, F_reg, H_reg }),
.out({ E_reg_d, A_reg_d, B_reg_d, D_reg_d, F_reg_q, H_reg_d })
);
delayline #(
.WIDTH(6),
.CYCLES(4)
) delay2 (
.clock(clock),
.in(rule_reg),
.out(rule_d)
);
always_ff @(posedge clock) begin
{ rule_reg, E_reg, A_reg, B_reg, D_reg, F_reg, H_reg } <= { rule, E, A, B, D, F, H };
case({!is_diff, rule_d[5:2]})
1,17: {op, input_ctrl} <= {BLEND1, AB};
2,18: {op, input_ctrl} <= {BLEND1, DB};
3,19: {op, input_ctrl} <= {BLEND1, BD};
4,20: {op, input_ctrl} <= {BLEND2, DB};
5,21: {op, input_ctrl} <= {BLEND2, AB};
6,22: {op, input_ctrl} <= {BLEND2, AD};
8: {op, input_ctrl} <= {BLEND0, 2'bxx};
9: {op, input_ctrl} <= {BLEND0, 2'bxx};
10: {op, input_ctrl} <= {BLEND0, 2'bxx};
11: {op, input_ctrl} <= {BLEND1, AB};
12: {op, input_ctrl} <= {BLEND1, AB};
13: {op, input_ctrl} <= {BLEND1, AB};
14: {op, input_ctrl} <= {BLEND1, DB};
15: {op, input_ctrl} <= {BLEND1, BD};
24: {op, input_ctrl} <= {BLEND2, DB};
25: {op, input_ctrl} <= {BLEND5, DB};
26: {op, input_ctrl} <= {BLEND6, DB};
27: {op, input_ctrl} <= {BLEND2, DB};
28: {op, input_ctrl} <= {BLEND4, DB};
29: {op, input_ctrl} <= {BLEND5, DB};
30: {op, input_ctrl} <= {BLEND3, BD};
31: {op, input_ctrl} <= {BLEND3, DB};
default: {op, input_ctrl} <= {11{1'bx}};
endcase
// Setting op[8] effectively disables HQ2X because blend will always return E.
if (disable_hq2x) op[8] <= 1;
end
// Generate inputs to the inner blender. Valid combinations.
// 00: E A B
// 01: E A D
// 10: E D B
// 11: E B D
InnerBlend inner_blend1(clock, op_q, Input1[7:0], Input2[7:0], Input3[7:0], res_out[7:0]);
InnerBlend inner_blend2(clock, op_q, Input1[15:8], Input2[15:8], Input3[15:8], res_out[15:8]);
InnerBlend inner_blend3(clock, op_q, Input1[23:16], Input2[23:16], Input3[23:16], res_out[23:16]);
always_ff @(posedge clock) begin
op_q <= op;
Input1 <= E_reg_d;
Input2 <= !input_ctrl[1] ? A_reg_d :
!input_ctrl[0] ? D_reg_d : B_reg_d;
Input3 <= !input_ctrl[0] ? B_reg_d : D_reg_d;
{ Result, res_out_q_q_q_q, res_out_q_q_q, res_out_q_q, res_out_q } <= { res_out_q_q_q_q, res_out_q_q_q, res_out_q_q, res_out_q, res_out };
end
endmodule |
module testbench();
supply0 vss;
supply1 vdd;
// Skeleton
initial
begin
$dumpfile("waveform.vcd");
$dumpvars(0, testbench);
#(1000)
$finish;
end
// Stimulus
reg a,b;
initial
begin
#100 a = 0; b = 0 ;
#100 a = 0; b = 1 ;
#100 a = 1; b = 0 ;
#100 a = 1; b = 1 ;
end
// DUT
defparam dut.NMODEL = "nmos";
defparam dut.PMODEL = "pmos";
defparam dut.W = {0,1,2,3};
defparam dut.L = {0,1,2,3};
defparam dut.M = {0,1,2,3};
defparam dut.NF = {0,1,2,3};
oh_nor2 dut (/*AUTOINST*/
// Outputs
.z (z),
// Inputs
.vdd (vdd),
.vss (vss),
.a (a),
.b (b));
endmodule // top |
module testbench();
supply0 vss;
supply1 vdd;
// Skeleton
initial
begin
$dumpfile("waveform.vcd");
$dumpvars(0, testbench);
#(1000)
$finish;
end
// Stimulus
reg a,b;
initial
begin
#100 a = 0; b = 0 ;
#100 a = 0; b = 1 ;
#100 a = 1; b = 0 ;
#100 a = 1; b = 1 ;
end
// DUT
oh_nand2 #(.SIM("switch"),
.NMODEL("nmos"),
.PMODEL("pmos"),
.W({0,1,2,3}),
.L({4,5,6,7}),
.M({8,9,10,11}),
.NF({12,13,14,15}))
dut (/*AUTOINST*/
// Outputs
.z (z),
// Inputs
.vdd (vdd),
.vss (vss),
.a (a),
.b (b));
endmodule // top |
module oh_pmos #(parameter MODEL = "pmos",
parameter W = "0",
parameter L = "0",
parameter M = "0",
parameter NF = "0"
)
(
input bulk,
input g,
input s,
inout d
);
//out,in,ctrlr
pmos p (d,s,g);
// Debug information
`ifdef OH_DEBUG
initial
begin
$display("inst=%m model=%s w=%0d l=%0d m=%0d nf=%0d",
MODEL,W,L,M,NF);
end
`endif
endmodule |
module oh_nmos #(parameter MODEL = "nmos",
parameter W = "0",
parameter L = "0",
parameter M = "0",
parameter NF = "0"
)
(
input bulk,
input g,
input s,
inout d
);
// Primitive Device
nmos n (d, s, g);
// Debug information
`ifdef OH_DEBUG
initial
begin
$display("inst=%m model=%s w=%0d l=%0d m=%0d nf=%0d",
MODEL,W,L,M,NF);
end
`endif
endmodule |
module vector_muladd(
clk,
rst,
op_din_en,
op_din_eop,
op_din,
op_weight,
op_bias,
op_dout
);
//========================================
//parameter define
//========================================
parameter CPF = 4;
parameter RELU = 0;
parameter Q = 8;
parameter DIN_Q = 6;
parameter DOUT_Q = 6;
parameter ACC_WIDTH = 40;
parameter BIAS_DW = 16;
parameter BN = 0;
parameter BN_SCALE_Q = 13;
parameter BN_BIAS_Q = 13;
parameter MID_Q = 13;
parameter DIN_DW = 16;
parameter DOUT_DW = 8; //bit-width of output
parameter WW = 16; //bit-width of weight
parameter MAT_DW = 32;
parameter DELTA_DELAY = 0;
parameter DATA_CHANNEL = 1; // when using 8bit, set to 2
//========================================
//input/output declare
//========================================
input clk;
input rst;
input op_din_en;
input op_din_eop;
input [DIN_DW*CPF-1:0] op_din;
input [WW*DATA_CHANNEL*CPF-1:0] op_weight;
input [BIAS_DW*DATA_CHANNEL-1:0] op_bias;
output [DOUT_DW*DATA_CHANNEL-1:0] op_dout;
wire [MAT_DW-1:0] mul[CPF-1:0];
//========================================
// Multiplier for 1bit/2bit/8bit/16bit
//========================================
genvar gv_i;
generate
for ( gv_i = 0; gv_i < CPF; gv_i = gv_i +1 ) begin: gen_multiplier
multiplier #(.C_WIDTH(DATA_CHANNEL),.D_WIDTH(DIN_DW),.W_WIDTH(WW*DATA_CHANNEL),.M_WIDTH(MAT_DW)) u_mult(
.clk(clk),
.d_i(op_din[DIN_DW*(gv_i+1)-1:DIN_DW*gv_i]),
.w_i(op_weight[WW*DATA_CHANNEL*(gv_i+1)-1:WW*DATA_CHANNEL*gv_i]),
.m_o(mul[gv_i])
);
end
endgenerate
//reg the bais in the end.
reg [BIAS_DW*DATA_CHANNEL-1:0] op_bias_d1;
always @ (posedge clk)
begin
if(rst)
op_bias_d1 <= {(BIAS_DW*DATA_CHANNEL){1'b0}};
else if (op_din_eop)
op_bias_d1 <= op_bias;
else
op_bias_d1 <= op_bias_d1;
end
//========================================
//delay op_din_en N clock
//========================================
wire op_din_en_d1;
delay #((CPF <2)?1:((CPF < 8)?2:((CPF < 32)?3:4)))u_delay_1(
.clk(clk),
.rst(rst),
.in(op_din_en),
.out(op_din_en_d1)
);
//========================================
//delay op_din_eop N+1 clock
//========================================
wire op_din_eop_d2;
delay #((CPF <2)?2:((CPF < 8)?3:((CPF < 32)?4:5)))u_delay_2(
.clk(clk),
.rst(rst),
.in(op_din_eop),
.out(op_din_eop_d2)
);
wire [ACC_WIDTH-1:0] a2_tmp;
wire [BIAS_DW-1:0] bias_tmp;
//========================================
// accumulator
//========================================
generate
if (DIN_DW == 8 && WW == 8) begin: gen_adder_8b
wire [MAT_DW/2-1:0] mul0[CPF-1:0];
wire [MAT_DW/2-1:0] mul1[CPF-1:0];
wire [ACC_WIDTH-1:0] a2_tmp_0;
wire [ACC_WIDTH-1:0] a2_tmp_1;
for ( gv_i = 0; gv_i < CPF; gv_i = gv_i +1 ) begin: gen_mul_8
assign mul0[gv_i] = mul[gv_i][MAT_DW/2-1:0];
assign mul1[gv_i] = mul[gv_i][MAT_DW-1:MAT_DW/2];
end
acc_addr #(.CPF(CPF),.M_DW(MAT_DW/2),.ACC_WIDTH(ACC_WIDTH)) u_acc_addr0(
.clk(clk),
.rst(rst),
.mul(mul0),
.op_din_eop_d2(op_din_eop_d2),
.op_din_en_d1(op_din_en_d1),
.a_o(a2_tmp_0));
acc_addr #(.CPF(CPF),.M_DW(MAT_DW/2),.ACC_WIDTH(ACC_WIDTH)) u_acc_addr1(
.clk(clk),
.rst(rst),
.mul(mul1),
.op_din_eop_d2(op_din_eop_d2),
.op_din_en_d1(op_din_en_d1),
.a_o(a2_tmp_1));
//reg the last accumulated data for multiplexing
reg[2*ACC_WIDTH-1:0] a2_tmp_reg;
always @ (posedge clk)
begin
if(rst)
a2_tmp_reg <= {(2*ACC_WIDTH){1'b0}};
else if (op_din_eop_d2 == 1'b1)
a2_tmp_reg <= {a2_tmp_1, a2_tmp_0};
end
reg a2_tmp_sel;
always @ (posedge clk)
begin
if(rst)
a2_tmp_sel <= 1'b0;
else if (op_din_eop_d2 == 1'b1)
a2_tmp_sel <= 1'b0;
else
a2_tmp_sel <= ~a2_tmp_sel;
end
assign a2_tmp = a2_tmp_sel ? a2_tmp_reg[2*ACC_WIDTH-1:ACC_WIDTH] : a2_tmp_reg[ACC_WIDTH-1:0];
assign bias_tmp = a2_tmp_sel ? op_bias_d1[2*BIAS_DW-1:BIAS_DW] : op_bias_d1[BIAS_DW-1:0];
end
else begin: gen_adder_16b // 16 bit
acc_addr #(.CPF(CPF),.M_DW(MAT_DW),.ACC_WIDTH(ACC_WIDTH)) u_acc_addr0(
.clk(clk),
.rst(rst),
.mul(mul),
.op_din_eop_d2(op_din_eop_d2),
.op_din_en_d1(op_din_en_d1),
.a_o(a2_tmp));
assign bias_tmp = op_bias_d1;
end
endgenerate
wire [DOUT_DW-1:0] op_dout_tmp;
bn_bias_relu #(
.RELU(RELU),
.Q(Q),
.DIN_Q(DIN_Q),
.DOUT_DW(DOUT_DW),
.DOUT_Q(DOUT_Q),
.ACC_WIDTH(ACC_WIDTH),
.BIAS_DW(BIAS_DW),
.BN(BN),
.BN_SCALE_Q(BN_SCALE_Q),
.BN_BIAS_Q(BN_BIAS_Q),
.MID_Q(MID_Q)
) u_bn_bias_relu (
.clk(clk),
.rst(rst),
.acc_in(a2_tmp),
.op_bias(bias_tmp),
.op_dout(op_dout_tmp)
);
generate
if (DIN_DW == 8 && WW == 8) begin: gen_out_8bits
reg [DOUT_DW-1:0] op_dout_reg;
always @ (posedge clk)
begin
if(rst)
op_dout_reg <= {(DOUT_DW){1'b0}};
else
op_dout_reg <= op_dout_tmp;
end
assign op_dout = {op_dout_tmp, op_dout_reg};
end
else begin:gen_out
assign op_dout = op_dout_tmp;
end
endgenerate
endmodule |
module SysPLL_inferred(
// Clock in ports
input CLK_IN,
// Clock out ports
output CLK_OUT1,
output CLK_OUT2,
// Status and control signals
input RESET,
output LOCKED
);
assign CLK_OUT1 = CLK_IN;
assign CLK_OUT2 = CLK_IN;
assign LOCKED = ~RESET;
endmodule |
module SysPLL_kc705
(
input i_clk_tcxo,
output o_clk_sys,
output o_clk_ddr,
input i_reset,
output o_locked
);
// Input buffering
//------------------------------------
wire i_clk_tcxo_clk_wiz_0;
wire clk_in2_clk_wiz_0;
assign i_clk_tcxo_clk_wiz_0 = i_clk_tcxo;
// Clocking PRIMITIVE
//------------------------------------
// Instantiation of the MMCM PRIMITIVE
// * Unused inputs are tied off
// * Unused outputs are labeled unused
wire o_clk_sys_clk_wiz_0;
wire o_clk_ddr_clk_wiz_0;
wire clk_out3_clk_wiz_0;
wire clk_out4_clk_wiz_0;
wire clk_out5_clk_wiz_0;
wire clk_out6_clk_wiz_0;
wire clk_out7_clk_wiz_0;
wire [15:0] do_unused;
wire drdy_unused;
wire psdone_unused;
wire locked_int;
wire clkfbout_clk_wiz_0;
wire clkfbout_buf_clk_wiz_0;
wire clkfboutb_unused;
wire clkout0b_unused;
wire clkout1b_unused;
wire clkout2_unused;
wire clkout2b_unused;
wire clkout3_unused;
wire clkout3b_unused;
wire clkout4_unused;
wire clkout5_unused;
wire clkout6_unused;
wire clkfbstopped_unused;
wire clkinstopped_unused;
wire reset_high;
MMCME2_ADV
#(.BANDWIDTH ("OPTIMIZED"),
.CLKOUT4_CASCADE ("FALSE"),
.COMPENSATION ("ZHOLD"),
.STARTUP_WAIT ("FALSE"),
.DIVCLK_DIVIDE (1),
.CLKFBOUT_MULT_F (5.000),
.CLKFBOUT_PHASE (0.000),
.CLKFBOUT_USE_FINE_PS ("FALSE"),
.CLKOUT0_DIVIDE_F (25.000),
.CLKOUT0_PHASE (0.000),
.CLKOUT0_DUTY_CYCLE (0.500),
.CLKOUT0_USE_FINE_PS ("FALSE"),
.CLKOUT1_DIVIDE (5),
.CLKOUT1_PHASE (0.000),
.CLKOUT1_DUTY_CYCLE (0.500),
.CLKOUT1_USE_FINE_PS ("FALSE"),
.CLKIN1_PERIOD (5.000))
mmcm_adv_inst
// Output clocks
(
.CLKFBOUT (clkfbout_clk_wiz_0),
.CLKFBOUTB (clkfboutb_unused),
.CLKOUT0 (o_clk_sys_clk_wiz_0),
.CLKOUT0B (clkout0b_unused),
.CLKOUT1 (o_clk_ddr_clk_wiz_0),
.CLKOUT1B (clkout1b_unused),
.CLKOUT2 (clkout2_unused),
.CLKOUT2B (clkout2b_unused),
.CLKOUT3 (clkout3_unused),
.CLKOUT3B (clkout3b_unused),
.CLKOUT4 (clkout4_unused),
.CLKOUT5 (clkout5_unused),
.CLKOUT6 (clkout6_unused),
// Input clock control
.CLKFBIN (clkfbout_buf_clk_wiz_0),
.CLKIN1 (i_clk_tcxo_clk_wiz_0),
.CLKIN2 (1'b0),
// Tied to always select the primary input clock
.CLKINSEL (1'b1),
// Ports for dynamic reconfiguration
.DADDR (7'h0),
.DCLK (1'b0),
.DEN (1'b0),
.DI (16'h0),
.DO (do_unused),
.DRDY (drdy_unused),
.DWE (1'b0),
// Ports for dynamic phase shift
.PSCLK (1'b0),
.PSEN (1'b0),
.PSINCDEC (1'b0),
.PSDONE (psdone_unused),
// Other control and status signals
.LOCKED (locked_int),
.CLKINSTOPPED (clkinstopped_unused),
.CLKFBSTOPPED (clkfbstopped_unused),
.PWRDWN (1'b0),
.RST (reset_high));
assign reset_high = i_reset;
assign o_locked = locked_int;
// Clock Monitor clock assigning
//--------------------------------------
// Output buffering
//-----------------------------------
BUFG clkf_buf
(.O (clkfbout_buf_clk_wiz_0),
.I (clkfbout_clk_wiz_0));
BUFG clkout1_buf
(.O (o_clk_sys),
.I (o_clk_sys_clk_wiz_0));
BUFG clkout2_buf
(.O (o_clk_ddr),
.I (o_clk_ddr_clk_wiz_0));
endmodule |
module tb_sim();
// -----------------------------
// simulation setting
// -----------------------------
initial begin
$dumpfile("tb_sim.vcd");
$dumpvars(0, tb_sim);
#20000
$finish();
end
localparam RATE = 1000.0/300.0;
// localparam RATE = 1000.0/250.0;
reg reset = 1'b1;
always #(RATE*100) reset = 1'b0;
reg clk = 1'b1;
always #(RATE/2.0) clk = ~clk;
tb_main
i_tb_main
(
.reset (reset),
.clk (clk)
);
endmodule |
module tb_sim();
// -----------------------------
// simulation setting
// -----------------------------
initial begin
$dumpfile("tb_sim.vcd");
$dumpvars(0, tb_sim);
#2000000;
$finish();
end
localparam RATE = 1000.0/300.0;
// localparam RATE = 1000.0/250.0;
reg reset = 1'b1;
always #(RATE*100) reset = 1'b0;
reg clk = 1'b1;
always #(RATE/2.0) clk = ~clk;
tb_main
i_tb_main
(
.reset (reset),
.clk (clk)
);
endmodule |
module tb_sim();
// -----------------------------
// simulation setting
// -----------------------------
initial begin
$dumpfile("tb_sim.vcd");
$dumpvars(0, tb_sim);
#2000000
$finish();
end
localparam RATE = 1000.0/300.0;
// localparam RATE = 1000.0/250.0;
reg reset = 1'b1;
always #(RATE*100) reset = 1'b0;
reg clk = 1'b1;
always #(RATE/2.0) clk = ~clk;
tb_main
i_tb_main
(
.reset (reset),
.clk (clk)
);
endmodule |
module tb_sim();
initial begin
$dumpfile("tb_sim.vcd");
$dumpvars(0, tb_sim);
#1000000
$finish;
end
// ---------------------------------
// clock & reset
// ---------------------------------
localparam RATE = 1000.0/100.00;
logic reset = 1;
initial #100 reset = 0;
logic clk = 1'b1;
always #(RATE/2.0) clk <= ~clk;
// ---------------------------------
// main
// ---------------------------------
tb_main
i_tb_main
(
.reset,
.clk
);
endmodule |
module tb_sim();
initial begin
$dumpfile("tb_sim.vcd");
$dumpvars(1, tb_sim);
#10000
$finish;
end
// ---------------------------------
// clock & reset
// ---------------------------------
localparam CLK_RATE = 1000.0/100.00;
reg reset = 1;
initial #100 reset = 0;
reg clk = 1'b1;
always #(CLK_RATE/2.0) clk <= ~clk;
// ---------------------------------
// main
// ---------------------------------
tb_main
i_tb_main
(
.reset,
.clk
);
endmodule |
module tb_top();
initial begin
$dumpfile("tb_top.vcd");
$dumpvars(0, tb_top);
#100000;
$finish;
end
localparam RATE = 1000.0/200.0;
logic clk = 1'b1;
always #(RATE/2.0) clk = ~clk;
logic reset = 1'b1;
initial #(RATE*100) reset = 1'b0;
tb_main
u_tb_main
(
.reset ,
.clk
);
endmodule |
module tb_sim();
localparam RATE = 10.0;
initial begin
$dumpfile("tb_sim.vcd");
$dumpvars(0, tb_sim);
#(RATE*100);
#(20000*100)
$finish();
end
reg reset = 1'b1;
always #(RATE*100) reset = 1'b0;
reg clk = 1'b1;
always #(RATE/2.0) clk = ~clk;
// -----------------------------
// main
// -----------------------------
tb_main
#(
.DEVICE ("ULTRASCALE")
)
i_main
(
.reset,
.clk
);
endmodule |
module tb_sim();
localparam RATE = 10.0;
initial begin
$dumpfile("tb_sim.vcd");
$dumpvars(0, tb_sim);
#1000000
$finish();
end
reg reset = 1'b1;
always #(RATE*100) reset = 1'b0;
reg clk = 1'b1;
always #(RATE/2.0) clk = ~clk;
// -----------------------------
// main
// -----------------------------
tb_main
i_main
(
.reset,
.clk
);
/*
logic [1:0] a;
logic [1:0] b;
logic [1:0] c;
logic [1:0] d0;
logic [1:0] d1;
logic msb_carry;
logic carry;
logic overflow;
logic zero;
logic negative;
logic my_eq ;
logic my_ne ;
logic my_lt ;
logic my_ge ;
logic my_ltu;
logic my_geu;
logic exp_eq ;
logic exp_ne ;
logic exp_lt ;
logic exp_ge ;
logic exp_ltu;
logic exp_geu;
initial begin
for (int i = 0; i < 4; ++i ) begin
for (int j = 0; j < 4; ++j ) begin
a = i[1:0];
b = j[1:0];
d0 = a;
d1 = ~b;
{msb_carry, c[0:0]} = {1'b0, d0[0:0]} + {1'b0, d1[0:0]} + 1'b1;
{carry, c[1]} = {1'b0, d0[1]} + {1'b0, d1[1]} + msb_carry;
overflow = (msb_carry != carry);
zero = (c == '0);
negative = c[1];
my_eq = zero;
my_ne = !zero;
my_lt = (overflow != negative);
my_ge = (overflow == negative);
my_ltu = !carry;
my_geu = carry;
exp_eq = ( $signed(a) == $signed(b));
exp_ne = ( $signed(a) != $signed(b));
exp_lt = ( $signed(a) < $signed(b));
exp_ge = ( $signed(a) >= $signed(b));
exp_ltu = ($unsigned(a) < $unsigned(b));
exp_geu = ($unsigned(a) >= $unsigned(b));
$display("%b-%b=%b carry=%b overflow=%b zero=%b, negative=%b", i[1:0], j[1:0], c, carry, overflow, zero, negative);
$display(" eq = %b %b", exp_eq , my_eq );
$display(" ne = %b %b", exp_ne , my_ne );
$display(" lt = %b %b", exp_lt , my_lt );
$display(" ge = %b %b", exp_ge , my_ge );
$display(" ltu = %b %b", exp_ltu, my_ltu );
$display(" geu = %b %b", exp_geu, my_geu );
end
end
$finish;
end
*/
endmodule |
module tb_sim();
localparam RATE = 10.0;
initial begin
$dumpfile("tb_sim.vcd");
$dumpvars(0, tb_sim);
#2000000
$finish();
end
reg reset = 1'b1;
always #(RATE*100) reset = 1'b0;
reg clk = 1'b1;
always #(RATE/2.0) clk = ~clk;
// -----------------------------
// main
// -----------------------------
tb_sim_main
i_sim_main
(
.reset,
.clk
);
endmodule |
module tb_sim();
localparam RATE = 10.0;
initial begin
$dumpfile("tb_sim.vcd");
$dumpvars(0, tb_sim);
#200000
$finish();
end
reg reset = 1'b1;
always #(RATE*100) reset = 1'b0;
reg clk = 1'b1;
always #(RATE/2.0) clk = ~clk;
// -----------------------------
// main
// -----------------------------
tb_main
i_tb_main
(
.reset (reset),
.clk (clk)
);
endmodule |
module tb_sim();
localparam RATE = 10.0;
initial begin
$dumpfile("tb_sim.vcd");
$dumpvars(0, tb_sim);
#200000
$finish();
end
reg reset = 1'b1;
always #(RATE*100) reset = 1'b0;
reg clk = 1'b1;
always #(RATE/2.0) clk = ~clk;
// -----------------------------
// main
// -----------------------------
tb_sim_main
i_sim_main
(
.reset (reset),
.clk (clk)
);
endmodule |
module tb_sim();
localparam RATE = 10.0;
initial begin
$dumpfile("tb_sim.vcd");
$dumpvars(0, tb_sim);
#10000
$finish();
end
reg reset = 1'b1;
always #(RATE*100) reset = 1'b0;
reg clk = 1'b1;
always #(RATE/2.0) clk = ~clk;
// -----------------------------
// main
// -----------------------------
tb_main
i_tb_main
(
.reset (reset),
.clk (clk)
);
endmodule |
module tb_sim();
localparam RATE = 1000.0 / 100.0;
initial begin
$dumpfile("tb_sim.vcd");
$dumpvars(0, tb_sim);
// $dumpvars(3, tb_sim);
#1000000;
$finish;
end
reg reset = 1'b1;
initial #(RATE*100) reset = 1'b0;
reg clk = 1'b1;
always #(RATE/2.0) clk = ~clk;
// -----------------------------------------
// main
// -----------------------------------------
tb_main
i_tb_main
(
.reset,
.clk
);
endmodule |
module tb_sim();
localparam RATE = 1000.0/250.0;
initial begin
$dumpfile("tb_sim.vcd");
$dumpvars(0, tb_sim);
#10000000;
$finish;
end
reg clk = 1'b1;
always #(RATE/2.0) clk = ~clk;
reg reset = 1'b1;
initial #(RATE*100.5) reset = 1'b0;
tb_main
i_tb_main
(
.reset (reset),
.clk (clk)
);
endmodule |
module tb_sim();
// -----------------------------
// simulation setting
// -----------------------------
initial begin
$dumpfile("tb_sim.vcd");
$dumpvars(0, tb_sim);
#100000
$finish();
end
localparam RATE = 1000.0/300.0;
// localparam RATE = 1000.0/250.0;
reg reset = 1'b1;
always #(RATE*100) reset = 1'b0;
reg clk = 1'b1;
always #(RATE/2.0) clk = ~clk;
tb_main
i_tb_main
(
.reset (reset),
.clk (clk)
);
endmodule |
module tb_sim();
// -----------------------------
// simulation setting
// -----------------------------
initial begin
$dumpfile("tb_sim.vcd");
$dumpvars(0, tb_sim);
#300000
$finish();
end
localparam RATE = 1000.0/300.0;
// localparam RATE = 1000.0/250.0;
reg reset = 1'b1;
always #(RATE*100) reset = 1'b0;
reg clk = 1'b1;
always #(RATE/2.0) clk = ~clk;
tb_main
i_tb_main
(
.reset (reset),
.clk (clk)
);
endmodule |
module tb_main
(
input wire reset,
input wire clk
);
parameter USER_WIDTH = 0;
parameter DATA_WIDTH = 8;
parameter USER_BITS = USER_WIDTH > 0 ? USER_WIDTH : 1;
logic cke = 1'b1;
logic s_img_row_first;
logic s_img_row_last;
logic s_img_col_first;
logic s_img_col_last;
logic s_img_de;
logic [USER_BITS-1:0] s_img_user;
logic [DATA_WIDTH-1:0] s_img_r;
logic [DATA_WIDTH-1:0] s_img_g;
logic [DATA_WIDTH-1:0] s_img_b;
logic s_img_valid;
logic m_img_row_first;
logic m_img_row_last;
logic m_img_col_first;
logic m_img_col_last;
logic m_img_de;
logic [USER_BITS-1:0] m_img_user;
logic [DATA_WIDTH-1:0] m_img_h;
logic [DATA_WIDTH-1:0] m_img_s;
logic [DATA_WIDTH-1:0] m_img_v;
logic m_img_valid;
jelly2_img_rgb2hsv
#(
.USER_WIDTH (USER_WIDTH),
.DATA_WIDTH (DATA_WIDTH)
)
i_img_rgb2hsv
(
.reset,
.clk,
.cke,
.s_img_row_first,
.s_img_row_last,
.s_img_col_first,
.s_img_col_last,
.s_img_de,
.s_img_user,
.s_img_r,
.s_img_g,
.s_img_b,
.s_img_valid,
.m_img_row_first,
.m_img_row_last,
.m_img_col_first,
.m_img_col_last,
.m_img_de,
.m_img_user,
.m_img_h,
.m_img_s,
.m_img_v,
.m_img_valid
);
jelly2_img_master_model
#(
.COMPONENTS (3),
.DATA_WIDTH (8),
.X_NUM (256),
.Y_NUM (256),
.X_BLANK (0), // 基本ゼロ
.Y_BLANK (0), // 末尾にde落ちラインを追加
.X_WIDTH (32),
.Y_WIDTH (32),
.F_WIDTH (32),
// .FILE_NAME ("../../../../data/color/Parrots.ppm"),
.FILE_NAME ("../../../../data/col_ptn.ppm"),
.FILE_EXT (""),
.SEQUENTIAL_FILE (0),
.ENDIAN (0)
)
i_img_master_model
(
.reset,
.clk,
.cke,
.enable (1'b1),
.busy (),
.m_img_row_first (s_img_row_first),
.m_img_row_last (s_img_row_last),
.m_img_col_first (s_img_col_first),
.m_img_col_last (s_img_col_last),
.m_img_de (s_img_de),
.m_img_data ({s_img_r, s_img_g, s_img_b}),
.m_img_x (),
.m_img_y (),
.m_img_f (),
.m_img_valid (s_img_valid)
);
jelly2_img_slave_model
#(
.COMPONENTS (3),
.DATA_WIDTH (8),
.INIT_FRAME_NUM (0),
.X_WIDTH (32),
.Y_WIDTH (32),
.F_WIDTH (32),
.FORMAT ("P3"),
.FILE_NAME ("img_"),
.FILE_EXT (".ppm"),
.SEQUENTIAL_FILE (1),
.ENDIAN (0)
)
i_img_slave_model
(
.reset,
.clk,
.cke,
.param_width (256),
.param_height (256),
.frame_num (),
.s_img_row_first (m_img_row_first),
.s_img_row_last (m_img_row_last),
.s_img_col_first (m_img_col_first),
.s_img_col_last (m_img_col_last),
.s_img_de (m_img_de),
.s_img_data ({m_img_h, m_img_s, m_img_v}),
.s_img_valid (m_img_valid)
);
endmodule |
module tb_sim();
localparam RATE = 10.0;
initial begin
$dumpfile("tb_sim.vcd");
$dumpvars(0, tb_sim);
#2000000
$finish();
end
logic reset = 1'b1;
always #(RATE*100) reset = 1'b0;
logic clk = 1'b1;
always #(RATE/2.0) clk = ~clk;
// -----------------------------
// main
// -----------------------------
tb_main
i_sim_main
(
.*
);
endmodule |
module tb_sim();
// -----------------------------
// simulation setting
// -----------------------------
initial begin
$dumpfile("tb_sim.vcd");
$dumpvars(0, tb_sim);
#2000000
$finish();
end
localparam RATE = 10.0;
reg reset = 1'b1;
always #(RATE*100) reset = 1'b0;
reg clk = 1'b1;
always #(RATE/2.0) clk = ~clk;
tb_main
i_tb_main
(
.aresetn (~reset),
.aclk (clk)
);
endmodule |
module tb_sim();
localparam RATE = 1000.0/200.0;
initial begin
$dumpfile("tb_sim.vcd");
$dumpvars(0, tb_sim);
#1000000
$finish;
end
logic reset = 1'b1;
initial #(RATE*10) reset <= 1'b0;
logic clk = 1'b1;
always #(RATE/2.0) clk = ~clk;
// ----------------------------------
// main
// ----------------------------------
tb_sim_main
i_sim_main
(
.*
);
/*
// ----------------------------------
// WISHBONE master
// ----------------------------------
localparam WB_DAT_SIZE = 3;
localparam WB_ADR_WIDTH = 40 - WB_DAT_SIZE;
localparam WB_DAT_WIDTH = (8 << WB_DAT_SIZE);
localparam WB_SEL_WIDTH = (1 << WB_DAT_SIZE);
// force connect to top-net
wire wb_rst_i = i_top.wb_peri_rst_i;
wire wb_clk_i = i_top.wb_peri_clk_i;
reg [WB_ADR_WIDTH-1:0] wb_adr_o;
wire [WB_DAT_WIDTH-1:0] wb_dat_i = i_top.wb_peri_dat_o;
reg [WB_DAT_WIDTH-1:0] wb_dat_o;
reg wb_we_o;
reg [WB_SEL_WIDTH-1:0] wb_sel_o;
reg wb_stb_o = 0;
wire wb_ack_i = i_top.wb_peri_ack_o;
initial begin
force i_top.wb_peri_adr_i = wb_adr_o;
force i_top.wb_peri_dat_i = wb_dat_o;
force i_top.wb_peri_we_i = wb_we_o;
force i_top.wb_peri_sel_i = wb_sel_o;
force i_top.wb_peri_stb_i = wb_stb_o;
end
reg [WB_DAT_WIDTH-1:0] reg_wb_dat;
reg reg_wb_ack;
always_ff @(posedge wb_clk_i) begin
if ( ~wb_we_o & wb_stb_o & wb_ack_i ) begin
reg_wb_dat <= wb_dat_i;
end
reg_wb_ack <= wb_ack_i;
end
task wb_write(
input [WB_ADR_WIDTH-1:0] adr,
input [WB_DAT_WIDTH-1:0] dat,
input [WB_SEL_WIDTH-1:0] sel
);
begin
$display("WISHBONE_WRITE(adr:%h dat:%h sel:%b)", adr, dat, sel);
@(negedge wb_clk_i);
wb_adr_o = adr;
wb_dat_o = dat;
wb_sel_o = sel;
wb_we_o = 1'b1;
wb_stb_o = 1'b1;
@(negedge wb_clk_i);
while ( reg_wb_ack == 1'b0 ) begin
@(negedge wb_clk_i);
end
wb_adr_o = {WB_ADR_WIDTH{1'bx}};
wb_dat_o = {WB_DAT_WIDTH{1'bx}};
wb_sel_o = {WB_SEL_WIDTH{1'bx}};
wb_we_o = 1'bx;
wb_stb_o = 1'b0;
end
endtask
task wb_read(
input [WB_ADR_WIDTH-1:0] adr
);
begin
@(negedge wb_clk_i);
wb_adr_o = adr;
wb_dat_o = {WB_DAT_WIDTH{1'bx}};
wb_sel_o = {WB_SEL_WIDTH{1'b1}};
wb_we_o = 1'b0;
wb_stb_o = 1'b1;
@(negedge wb_clk_i);
while ( reg_wb_ack == 1'b0 ) begin
@(negedge wb_clk_i);
end
wb_adr_o = {WB_ADR_WIDTH{1'bx}};
wb_dat_o = {WB_DAT_WIDTH{1'bx}};
wb_sel_o = {WB_SEL_WIDTH{1'bx}};
wb_we_o = 1'bx;
wb_stb_o = 1'b0;
$display("WISHBONE_READ(adr:%h dat:%h)", adr, reg_wb_dat);
end
endtask
// ----------------------------------
// Simulation
// ----------------------------------
localparam ADR_DMA0 = 32'h000000;
localparam ADR_DMA1 = 32'h000100;
localparam ADR_LED = 32'h001000;
localparam ADR_TIM = 32'h002000;
localparam REG_DMA_STATUS = 0;
localparam REG_DMA_WSTART = 1;
localparam REG_DMA_RSTART = 2;
localparam REG_DMA_ADDR = 3;
localparam REG_DMA_WDATA0 = 4;
localparam REG_DMA_WDATA1 = 5;
localparam REG_DMA_RDATA0 = 6;
localparam REG_DMA_RDATA1 = 7;
localparam REG_DMA_ID = 8;
localparam REG_TIM_CONTROL = 2'b00;
localparam REG_TIM_COMPARE = 2'b01;
localparam REG_TIM_COUNTER = 2'b11;
initial begin
@(negedge wb_rst_i);
#10000;
$display(" --- dma0 --- ");
wb_read (ADR_DMA0 + REG_DMA_ID); // CORE_ID
$display(" --- dma1 --- ");
wb_read (ADR_DMA1 + REG_DMA_ID); // CORE_ID
wb_read (ADR_DMA1 + REG_DMA_WDATA0);
wb_write(ADR_DMA1 + REG_DMA_WDATA0, 64'h0123456789abcdef, 8'h0f);
wb_read (ADR_DMA1 + REG_DMA_WDATA0);
wb_write(ADR_DMA1 + REG_DMA_WDATA0, 64'h01234567FFFFFFFF, 8'hf0);
wb_read (ADR_DMA1 + REG_DMA_WDATA0);
$display("write start");
wb_write(ADR_DMA1 + REG_DMA_WDATA0, 64'h0123456789abcdef, 8'hff);
wb_write(ADR_DMA1 + REG_DMA_WDATA1, 64'hfedcba9876543210, 8'hff);
wb_write(ADR_DMA1 + REG_DMA_ADDR, 64'h0000_0100, 8'hff);
wb_write(ADR_DMA1 + REG_DMA_WSTART, 64'h0000_0001, 8'hff);
#10000;
wb_write(ADR_DMA0 + REG_DMA_ADDR, 64'h0000_0100, 8'hff);
wb_write(ADR_DMA0 + REG_DMA_RSTART, 64'h0000_0001, 8'hff);
wb_read (ADR_DMA0 + REG_DMA_STATUS);
#10000;
wb_read (ADR_DMA0 + REG_DMA_STATUS);
wb_read (ADR_DMA0 + REG_DMA_RDATA0);
wb_read (ADR_DMA0 + REG_DMA_RDATA1);
#10000;
$display(" --- led --- ");
wb_read (ADR_LED);
wb_write(ADR_LED, 1, 8'hff);
#10000;
wb_write(ADR_LED, 0, 8'hff);
#10000;
$display(" --- timer --- ");
wb_write(ADR_TIM + REG_TIM_COMPARE, 1000-1, 8'hff);
wb_write(ADR_TIM + REG_TIM_CONTROL, 1000-1, 8'hff);
#11000;
wb_read (ADR_TIM + REG_TIM_CONTROL); // clear
#10000;
wb_read (ADR_TIM + REG_TIM_CONTROL); // clear
#10000;
$finish();
end
*/
endmodule |
module tb_sim();
initial begin
$dumpfile("tb_sim.vcd");
$dumpvars(0, tb_sim);
#1000000
$finish;
end
// ---------------------------------
// clock & reset
// ---------------------------------
localparam RATE27 = 27.0/100.00;
localparam RATE126 = 126.0/200.00;
localparam RATE25 = 5*126.0/250.00;
reg in_reset_n = 1'b0;
initial #100 in_reset_n = 1'b1;
reg in_clk = 1'b1;
always #(RATE27/2.0) in_clk <= ~in_clk;
reg clk = 1'b1;
always #(RATE25/2.0) clk <= ~clk;
reg clk_x5 = 1'b1;
always #(RATE126/2.0) clk_x5 <= ~clk_x5;
// ---------------------------------
// main
// ---------------------------------
tb_main
i_tb_main
(
.in_reset_n,
.in_clk,
.clk,
.clk_x5
);
endmodule |
module image_processing
#(
parameter WB_ADR_WIDTH = 17,
parameter WB_DAT_WIDTH = 32,
parameter WB_SEL_WIDTH = (WB_DAT_WIDTH / 8),
parameter AXI4_ID_WIDTH = 6,
parameter AXI4_ADDR_WIDTH = 32,
parameter AXI4_DATA_SIZE = 3, // 0:8bit, 1:16bit, 2:32bit ...
parameter AXI4_DATA_WIDTH = (8 << AXI4_DATA_SIZE),
parameter AXI4_STRB_WIDTH = AXI4_DATA_WIDTH / 8,
parameter AXI4_LEN_WIDTH = 8,
parameter AXI4_QOS_WIDTH = 4,
parameter S_DATA_WIDTH = 10,
parameter M_DATA_WIDTH = 8,
parameter MAX_X_NUM = 4096,
parameter IMG_Y_NUM = 480,
parameter IMG_Y_WIDTH = 14,
parameter TUSER_WIDTH = 1,
parameter S_TDATA_WIDTH = 1*S_DATA_WIDTH,
parameter M_TDATA_WIDTH = 4*M_DATA_WIDTH
)
(
input wire aresetn,
input wire aclk,
input wire in_update_req,
input wire s_wb_rst_i,
input wire s_wb_clk_i,
input wire [WB_ADR_WIDTH-1:0] s_wb_adr_i,
input wire [WB_DAT_WIDTH-1:0] s_wb_dat_i,
output wire [WB_DAT_WIDTH-1:0] s_wb_dat_o,
input wire s_wb_we_i,
input wire [WB_SEL_WIDTH-1:0] s_wb_sel_i,
input wire s_wb_stb_i,
output wire s_wb_ack_o,
input wire [TUSER_WIDTH-1:0] s_axi4s_tuser,
input wire s_axi4s_tlast,
input wire [S_TDATA_WIDTH-1:0] s_axi4s_tdata,
input wire s_axi4s_tvalid,
output wire s_axi4s_tready,
output wire [TUSER_WIDTH-1:0] m_axi4s_tuser,
output wire m_axi4s_tlast,
output wire [M_TDATA_WIDTH-1:0] m_axi4s_tdata,
output wire m_axi4s_tvalid,
input wire m_axi4s_tready,
input wire m_axi4_aresetn,
input wire m_axi4_aclk,
output wire [AXI4_ID_WIDTH-1:0] m_axi4_awid,
output wire [AXI4_ADDR_WIDTH-1:0] m_axi4_awaddr,
output wire [AXI4_LEN_WIDTH-1:0] m_axi4_awlen,
output wire [2:0] m_axi4_awsize,
output wire [1:0] m_axi4_awburst,
output wire [0:0] m_axi4_awlock,
output wire [3:0] m_axi4_awcache,
output wire [2:0] m_axi4_awprot,
output wire [AXI4_QOS_WIDTH-1:0] m_axi4_awqos,
output wire [3:0] m_axi4_awregion,
output wire m_axi4_awvalid,
input wire m_axi4_awready,
output wire [AXI4_DATA_WIDTH-1:0] m_axi4_wdata,
output wire [AXI4_STRB_WIDTH-1:0] m_axi4_wstrb,
output wire m_axi4_wlast,
output wire m_axi4_wvalid,
input wire m_axi4_wready,
input wire [AXI4_ID_WIDTH-1:0] m_axi4_bid,
input wire [1:0] m_axi4_bresp,
input wire m_axi4_bvalid,
output wire m_axi4_bready,
output wire [AXI4_ID_WIDTH-1:0] m_axi4_arid,
output wire [AXI4_ADDR_WIDTH-1:0] m_axi4_araddr,
output wire [AXI4_LEN_WIDTH-1:0] m_axi4_arlen,
output wire [2:0] m_axi4_arsize,
output wire [1:0] m_axi4_arburst,
output wire [0:0] m_axi4_arlock,
output wire [3:0] m_axi4_arcache,
output wire [2:0] m_axi4_arprot,
output wire [AXI4_QOS_WIDTH-1:0] m_axi4_arqos,
output wire [3:0] m_axi4_arregion,
output wire m_axi4_arvalid,
input wire m_axi4_arready,
input wire [AXI4_ID_WIDTH-1:0] m_axi4_rid,
input wire [AXI4_DATA_WIDTH-1:0] m_axi4_rdata,
input wire [1:0] m_axi4_rresp,
input wire m_axi4_rlast,
input wire m_axi4_rvalid,
output wire m_axi4_rready
);
localparam USE_VALID = 0;
localparam USER_WIDTH = (TUSER_WIDTH - 1) >= 0 ? (TUSER_WIDTH - 1) : 0;
localparam USER_BITS = USER_WIDTH > 0 ? USER_WIDTH : 1;
wire reset = ~aresetn;
wire clk = aclk;
wire cke;
wire img_src_line_first;
wire img_src_line_last;
wire img_src_pixel_first;
wire img_src_pixel_last;
wire img_src_de;
wire [USER_BITS-1:0] img_src_user;
wire [S_TDATA_WIDTH-1:0] img_src_data;
wire img_src_valid;
wire img_sink_line_first;
wire img_sink_line_last;
wire img_sink_pixel_first;
wire img_sink_pixel_last;
wire img_sink_de;
wire [USER_BITS-1:0] img_sink_user;
wire [M_TDATA_WIDTH-1:0] img_sink_data;
wire img_sink_valid;
// axi4s<->img
jelly_axi4s_img
#(
.TUSER_WIDTH (TUSER_WIDTH),
.S_TDATA_WIDTH (S_TDATA_WIDTH),
.M_TDATA_WIDTH (M_TDATA_WIDTH),
.IMG_Y_NUM (IMG_Y_NUM),
.IMG_Y_WIDTH (IMG_Y_WIDTH),
.BLANK_Y_WIDTH (8),
.IMG_CKE_BUFG (0)
)
jelly_axi4s_img
(
.reset (reset),
.clk (clk),
.param_blank_num (8'h0f),
.s_axi4s_tdata (s_axi4s_tdata),
.s_axi4s_tlast (s_axi4s_tlast),
.s_axi4s_tuser (s_axi4s_tuser),
.s_axi4s_tvalid (s_axi4s_tvalid),
.s_axi4s_tready (s_axi4s_tready),
.m_axi4s_tdata (m_axi4s_tdata),
.m_axi4s_tlast (m_axi4s_tlast),
.m_axi4s_tuser (m_axi4s_tuser),
.m_axi4s_tvalid (m_axi4s_tvalid),
.m_axi4s_tready (m_axi4s_tready),
.img_cke (cke),
.src_img_line_first (img_src_line_first),
.src_img_line_last (img_src_line_last),
.src_img_pixel_first (img_src_pixel_first),
.src_img_pixel_last (img_src_pixel_last),
.src_img_de (img_src_de),
.src_img_user (img_src_user),
.src_img_data (img_src_data),
.src_img_valid (img_src_valid),
.sink_img_line_first (img_sink_line_first),
.sink_img_line_last (img_sink_line_last),
.sink_img_pixel_first (img_sink_pixel_first),
.sink_img_pixel_last (img_sink_pixel_last),
.sink_img_user (img_sink_user),
.sink_img_de (img_sink_de),
.sink_img_data (img_sink_data),
.sink_img_valid (img_sink_valid)
);
// demosaic
wire img_demos_line_first;
wire img_demos_line_last;
wire img_demos_pixel_first;
wire img_demos_pixel_last;
wire img_demos_de;
wire [USER_BITS-1:0] img_demos_user;
wire [S_DATA_WIDTH-1:0] img_demos_raw;
wire [S_DATA_WIDTH-1:0] img_demos_r;
wire [S_DATA_WIDTH-1:0] img_demos_g;
wire [S_DATA_WIDTH-1:0] img_demos_b;
wire img_demos_valid;
wire [WB_DAT_WIDTH-1:0] wb_demos_dat_o;
wire wb_demos_stb_i;
wire wb_demos_ack_o;
jelly_img_demosaic_acpi
#(
.USER_WIDTH (USER_BITS),
.DATA_WIDTH (S_DATA_WIDTH),
.MAX_X_NUM (4096),
.RAM_TYPE ("block"),
.USE_VALID (USE_VALID),
.WB_ADR_WIDTH (6),
.WB_DAT_WIDTH (WB_DAT_WIDTH),
.INIT_PARAM_PHASE (2'b11)
)
i_img_demosaic_acpi
(
.reset (reset),
.clk (clk),
.cke (cke),
.in_update_req (in_update_req),
.s_wb_rst_i (s_wb_rst_i),
.s_wb_clk_i (s_wb_clk_i),
.s_wb_adr_i (s_wb_adr_i[5:0]),
.s_wb_dat_i (s_wb_dat_i),
.s_wb_dat_o (wb_demos_dat_o),
.s_wb_we_i (s_wb_we_i),
.s_wb_sel_i (s_wb_sel_i),
.s_wb_stb_i (wb_demos_stb_i),
.s_wb_ack_o (wb_demos_ack_o),
.s_img_line_first (img_src_line_first),
.s_img_line_last (img_src_line_last),
.s_img_pixel_first (img_src_pixel_first),
.s_img_pixel_last (img_src_pixel_last),
.s_img_de (img_src_de),
.s_img_user (img_src_user),
.s_img_raw (img_src_data),
.s_img_valid (img_src_valid),
.m_img_line_first (img_demos_line_first),
.m_img_line_last (img_demos_line_last),
.m_img_pixel_first (img_demos_pixel_first),
.m_img_pixel_last (img_demos_pixel_last),
.m_img_de (img_demos_de),
.m_img_user (img_demos_user),
.m_img_raw (img_demos_raw),
.m_img_r (img_demos_r),
.m_img_g (img_demos_g),
.m_img_b (img_demos_b),
.m_img_valid (img_demos_valid)
);
// color matrix
wire img_colmat_line_first;
wire img_colmat_line_last;
wire img_colmat_pixel_first;
wire img_colmat_pixel_last;
wire img_colmat_de;
wire [USER_BITS-1:0] img_colmat_user;
wire [S_DATA_WIDTH-1:0] img_colmat_raw;
wire [S_DATA_WIDTH-1:0] img_colmat_r;
wire [S_DATA_WIDTH-1:0] img_colmat_g;
wire [S_DATA_WIDTH-1:0] img_colmat_b;
wire img_colmat_valid;
wire [WB_DAT_WIDTH-1:0] wb_colmat_dat_o;
wire wb_colmat_stb_i;
wire wb_colmat_ack_o;
jelly_img_color_matrix
#(
.USER_WIDTH (USER_BITS + S_DATA_WIDTH),
.DATA_WIDTH (S_DATA_WIDTH),
.INTERNAL_WIDTH (S_DATA_WIDTH+2),
.COEFF_INT_WIDTH (9),
.COEFF_FRAC_WIDTH (16),
.COEFF3_INT_WIDTH (9),
.COEFF3_FRAC_WIDTH (16),
.STATIC_COEFF (1),
.DEVICE ("RTL"),
.WB_ADR_WIDTH (6),
.WB_DAT_WIDTH (WB_DAT_WIDTH),
.INIT_PARAM_MATRIX00 (1 << 16),
.INIT_PARAM_MATRIX01 (0),
.INIT_PARAM_MATRIX02 (0),
.INIT_PARAM_MATRIX03 (0),
.INIT_PARAM_MATRIX10 (0),
.INIT_PARAM_MATRIX11 (1 << 16),
.INIT_PARAM_MATRIX12 (0),
.INIT_PARAM_MATRIX13 (0),
.INIT_PARAM_MATRIX20 (0),
.INIT_PARAM_MATRIX21 (0),
.INIT_PARAM_MATRIX22 (1 << 16),
.INIT_PARAM_MATRIX23 (0),
.INIT_PARAM_CLIP_MIN0 ({S_DATA_WIDTH{1'b0}}),
.INIT_PARAM_CLIP_MAX0 ({S_DATA_WIDTH{1'b1}}),
.INIT_PARAM_CLIP_MIN1 ({S_DATA_WIDTH{1'b0}}),
.INIT_PARAM_CLIP_MAX1 ({S_DATA_WIDTH{1'b1}}),
.INIT_PARAM_CLIP_MIN2 ({S_DATA_WIDTH{1'b0}}),
.INIT_PARAM_CLIP_MAX2 ({S_DATA_WIDTH{1'b1}})
)
i_img_color_matrix
(
.reset (reset),
.clk (clk),
.cke (cke),
.in_update_req (in_update_req),
.s_wb_rst_i (s_wb_rst_i),
.s_wb_clk_i (s_wb_clk_i),
.s_wb_adr_i (s_wb_adr_i[5:0]),
.s_wb_dat_i (s_wb_dat_i),
.s_wb_dat_o (wb_colmat_dat_o),
.s_wb_we_i (s_wb_we_i),
.s_wb_sel_i (s_wb_sel_i),
.s_wb_stb_i (wb_colmat_stb_i),
.s_wb_ack_o (wb_colmat_ack_o),
.s_img_line_first (img_demos_line_first),
.s_img_line_last (img_demos_line_last),
.s_img_pixel_first (img_demos_pixel_first),
.s_img_pixel_last (img_demos_pixel_last),
.s_img_de (img_demos_de),
.s_img_user ({img_demos_user, img_demos_raw}),
.s_img_color0 (img_demos_r),
.s_img_color1 (img_demos_g),
.s_img_color2 (img_demos_b),
.s_img_valid (img_demos_valid),
.m_img_line_first (img_colmat_line_first),
.m_img_line_last (img_colmat_line_last),
.m_img_pixel_first (img_colmat_pixel_first),
.m_img_pixel_last (img_colmat_pixel_last),
.m_img_de (img_colmat_de),
.m_img_user ({img_colmat_user, img_colmat_raw}),
.m_img_color0 (img_colmat_r),
.m_img_color1 (img_colmat_g),
.m_img_color2 (img_colmat_b),
.m_img_valid (img_colmat_valid)
);
// gamma correction
wire img_gamma_line_first;
wire img_gamma_line_last;
wire img_gamma_pixel_first;
wire img_gamma_pixel_last;
wire img_gamma_de;
wire [USER_BITS-1:0] img_gamma_user;
wire [S_DATA_WIDTH-1:0] img_gamma_raw;
wire [3*M_DATA_WIDTH-1:0] img_gamma_data;
wire img_gamma_valid;
wire [WB_DAT_WIDTH-1:0] wb_gamma_dat_o;
wire wb_gamma_stb_i;
wire wb_gamma_ack_o;
jelly_img_gamma_correction
#(
.COMPONENTS (3),
.USER_WIDTH (USER_BITS+S_DATA_WIDTH),
.S_DATA_WIDTH (S_DATA_WIDTH),
.M_DATA_WIDTH (M_DATA_WIDTH),
.USE_VALID (USE_VALID),
.RAM_TYPE ("block"),
.WB_ADR_WIDTH (12),
.WB_DAT_WIDTH (WB_DAT_WIDTH),
.INIT_CTL_CONTROL (2'b00),
.INIT_PARAM_ENABLE (3'b000)
)
i_img_gamma_correction
(
.reset (reset),
.clk (clk),
.cke (cke),
.in_update_req (in_update_req),
.s_wb_rst_i (s_wb_rst_i),
.s_wb_clk_i (s_wb_clk_i),
.s_wb_adr_i (s_wb_adr_i[11:0]),
.s_wb_dat_i (s_wb_dat_i),
.s_wb_dat_o (wb_gamma_dat_o),
.s_wb_we_i (s_wb_we_i),
.s_wb_sel_i (s_wb_sel_i),
.s_wb_stb_i (wb_gamma_stb_i),
.s_wb_ack_o (wb_gamma_ack_o),
.s_img_line_first (img_colmat_line_first),
.s_img_line_last (img_colmat_line_last),
.s_img_pixel_first (img_colmat_pixel_first),
.s_img_pixel_last (img_colmat_pixel_last),
.s_img_de (img_colmat_de),
.s_img_user ({img_colmat_user, img_colmat_raw}),
.s_img_data ({img_colmat_r, img_colmat_g, img_colmat_b}),
.s_img_valid (img_colmat_valid),
.m_img_line_first (img_gamma_line_first),
.m_img_line_last (img_gamma_line_last),
.m_img_pixel_first (img_gamma_pixel_first),
.m_img_pixel_last (img_gamma_pixel_last),
.m_img_de (img_gamma_de),
.m_img_user ({img_gamma_user, img_gamma_raw}),
.m_img_data (img_gamma_data),
.m_img_valid (img_gamma_valid)
);
// gaussian
wire img_gauss_line_first;
wire img_gauss_line_last;
wire img_gauss_pixel_first;
wire img_gauss_pixel_last;
wire img_gauss_de;
wire [USER_BITS-1:0] img_gauss_user;
wire [S_DATA_WIDTH-1:0] img_gauss_raw;
wire [3*M_DATA_WIDTH-1:0] img_gauss_data;
wire img_gauss_valid;
wire [WB_DAT_WIDTH-1:0] wb_gauss_dat_o;
wire wb_gauss_stb_i;
wire wb_gauss_ack_o;
jelly_img_gaussian_3x3
#(
.NUM (3),
.USER_WIDTH (USER_BITS+S_DATA_WIDTH),
.COMPONENTS (3),
.DATA_WIDTH (M_DATA_WIDTH),
.MAX_X_NUM (MAX_X_NUM),
.RAM_TYPE ("block"),
.USE_VALID (USE_VALID),
.WB_ADR_WIDTH (8),
.WB_DAT_WIDTH (WB_DAT_WIDTH),
.INIT_CTL_CONTROL (3'b000),
.INIT_PARAM_ENABLE (3'b000)
)
i_img_gaussian_3x3
(
.reset (reset),
.clk (clk),
.cke (cke),
.in_update_req (in_update_req),
.s_wb_rst_i (s_wb_rst_i),
.s_wb_clk_i (s_wb_clk_i),
.s_wb_adr_i (s_wb_adr_i[7:0]),
.s_wb_dat_i (s_wb_dat_i),
.s_wb_dat_o (wb_gauss_dat_o),
.s_wb_we_i (s_wb_we_i),
.s_wb_sel_i (s_wb_sel_i),
.s_wb_stb_i (wb_gauss_stb_i),
.s_wb_ack_o (wb_gauss_ack_o),
.s_img_line_first (img_gamma_line_first),
.s_img_line_last (img_gamma_line_last),
.s_img_pixel_first (img_gamma_pixel_first),
.s_img_pixel_last (img_gamma_pixel_last),
.s_img_de (img_gamma_de),
.s_img_user ({img_gamma_user, img_gamma_raw}),
.s_img_data (img_gamma_data),
.s_img_valid (img_gamma_valid),
.m_img_line_first (img_gauss_line_first),
.m_img_line_last (img_gauss_line_last),
.m_img_pixel_first (img_gauss_pixel_first),
.m_img_pixel_last (img_gauss_pixel_last),
.m_img_de (img_gauss_de),
.m_img_user ({img_gauss_user, img_gauss_raw}),
.m_img_data (img_gauss_data),
.m_img_valid (img_gauss_valid)
);
// selector
localparam SEL_N = 2;
localparam SEL_U = USER_BITS;
localparam SEL_D = M_TDATA_WIDTH;
wire [SEL_N-1:0] img_sel_line_first;
wire [SEL_N-1:0] img_sel_line_last;
wire [SEL_N-1:0] img_sel_pixel_first;
wire [SEL_N-1:0] img_sel_pixel_last;
wire [SEL_N-1:0] img_sel_de;
wire [SEL_N*SEL_U-1:0] img_sel_user;
wire [SEL_N*SEL_D-1:0] img_sel_data;
wire [SEL_N-1:0] img_sel_valid;
assign img_sel_line_first [0] = img_gauss_line_first;
assign img_sel_line_last [0] = img_gauss_line_last;
assign img_sel_pixel_first[0] = img_gauss_pixel_first;
assign img_sel_pixel_last [0] = img_gauss_pixel_last;
assign img_sel_de [0] = img_gauss_de;
assign img_sel_user [0*SEL_U +: SEL_U] = img_gauss_user;
assign img_sel_data [0*SEL_D +: SEL_D] = {img_gauss_raw[S_DATA_WIDTH-1 -: M_DATA_WIDTH], img_gauss_data};
assign img_sel_valid [0] = img_gauss_valid;
assign img_sel_line_first [1] = img_src_line_first;
assign img_sel_line_last [1] = img_src_line_last;
assign img_sel_pixel_first[1] = img_src_pixel_first;
assign img_sel_pixel_last [1] = img_src_pixel_last;
assign img_sel_de [1] = img_src_de;
assign img_sel_user [1*SEL_U +: SEL_U] = img_src_user;
assign img_sel_data [1*SEL_D +: SEL_D] = {4{img_src_data[S_DATA_WIDTH-1 -: M_DATA_WIDTH]}};
assign img_sel_valid [1] = img_src_valid;
wire [WB_DAT_WIDTH-1:0] wb_sel_dat_o;
wire wb_sel_stb_i;
wire wb_sel_ack_o;
jelly_img_selector
#(
.NUM (SEL_N),
.USER_WIDTH (SEL_U),
.DATA_WIDTH (SEL_D),
.WB_ADR_WIDTH (8),
.WB_DAT_WIDTH (WB_DAT_WIDTH),
.INIT_CTL_SELECT (0)
)
i_img_selector
(
.reset (reset),
.clk (clk),
.cke (cke),
.s_wb_rst_i (s_wb_rst_i),
.s_wb_clk_i (s_wb_clk_i),
.s_wb_adr_i (s_wb_adr_i[7:0]),
.s_wb_dat_i (s_wb_dat_i),
.s_wb_dat_o (wb_sel_dat_o),
.s_wb_we_i (s_wb_we_i),
.s_wb_sel_i (s_wb_sel_i),
.s_wb_stb_i (wb_sel_stb_i),
.s_wb_ack_o (wb_sel_ack_o),
.s_img_line_first (img_sel_line_first),
.s_img_line_last (img_sel_line_last),
.s_img_pixel_first (img_sel_pixel_first),
.s_img_pixel_last (img_sel_pixel_last),
.s_img_de (img_sel_de),
.s_img_user (img_sel_user),
.s_img_data (img_sel_data),
.s_img_valid (img_sel_valid),
.m_img_line_first (img_sink_line_first),
.m_img_line_last (img_sink_line_last),
.m_img_pixel_first (img_sink_pixel_first),
.m_img_pixel_last (img_sink_pixel_last),
.m_img_de (img_sink_de),
.m_img_user (img_sink_user),
.m_img_data (img_sink_data),
.m_img_valid (img_sink_valid)
);
// 外部メモリは利用しない
assign m_axi4_awid = '0;
assign m_axi4_awaddr = '0;
assign m_axi4_awlen = '0;
assign m_axi4_awsize = '0;
assign m_axi4_awburst = '0;
assign m_axi4_awlock = '0;
assign m_axi4_awcache = '0;
assign m_axi4_awprot = '0;
assign m_axi4_awqos = '0;
assign m_axi4_awregion = '0;
assign m_axi4_awvalid = '0;
assign m_axi4_wdata = '0;
assign m_axi4_wstrb = '0;
assign m_axi4_wlast = '0;
assign m_axi4_wvalid = '0;
assign m_axi4_bready = '0;
assign m_axi4_arid = '0;
assign m_axi4_araddr = '0;
assign m_axi4_arlen = '0;
assign m_axi4_arsize = '0;
assign m_axi4_arburst = '0;
assign m_axi4_arlock = '0;
assign m_axi4_arcache = '0;
assign m_axi4_arprot = '0;
assign m_axi4_arqos = '0;
assign m_axi4_arregion = '0;
assign m_axi4_arvalid = '0;
assign m_axi4_rready = '0;
// WISHBONE
assign wb_demos_stb_i = s_wb_stb_i & (s_wb_adr_i[WB_ADR_WIDTH-1:13] == 4'h0);
assign wb_colmat_stb_i = s_wb_stb_i & (s_wb_adr_i[WB_ADR_WIDTH-1:13] == 4'h1);
assign wb_gamma_stb_i = s_wb_stb_i & (s_wb_adr_i[WB_ADR_WIDTH-1:13] == 4'h2);
assign wb_gauss_stb_i = s_wb_stb_i & (s_wb_adr_i[WB_ADR_WIDTH-1:13] == 4'h4);
assign wb_sel_stb_i = s_wb_stb_i & (s_wb_adr_i[WB_ADR_WIDTH-1:13] == 4'hf);
assign s_wb_dat_o = wb_demos_stb_i ? wb_demos_dat_o :
wb_colmat_stb_i ? wb_colmat_dat_o :
wb_gamma_stb_i ? wb_gamma_dat_o :
wb_gauss_stb_i ? wb_gauss_dat_o :
wb_sel_stb_i ? wb_sel_dat_o :
{WB_DAT_WIDTH{1'b0}};
assign s_wb_ack_o = wb_demos_stb_i ? wb_demos_ack_o :
wb_colmat_stb_i ? wb_colmat_ack_o :
wb_gamma_stb_i ? wb_gamma_ack_o :
wb_gauss_stb_i ? wb_gauss_ack_o :
wb_sel_stb_i ? wb_sel_ack_o :
s_wb_stb_i;
endmodule |
module tb_sim_main();
wire [1:0] led;
wire imu_sck;
wire imu_sda;
ultra96v2_mpu9250
i_top
(
.led (led),
.imu_sck (imu_sck),
.imu_sda (imu_sda)
);
endmodule |
module tb_sim_main();
logic [1:0] led;
ultra96v2_rtos
i_top
(
.*
);
endmodule |
module tb_sim_main();
wire [1:0] led;
ultra96v2_hls_test
i_top
(
.led (led)
);
endmodule |
module rmii_to_pmod
(
output wire [3:0] rmii_refclk,
input wire [3:0] rmii_txen,
input wire [3:0][1:0] rmii_tx,
output wire [3:0][1:0] rmii_rx,
output wire [3:0] rmii_crs,
output wire [3:0] rmii_mdc,
input wire [3:0] rmii_mdio_t,
input wire [3:0] rmii_mdio_o,
output wire [3:0] rmii_mdio_i,
inout wire [7:0] pmod_a,
inout wire [7:0] pmod_b,
inout wire [7:0] pmod_c,
inout wire [7:0] pmod_d,
inout wire [7:0] pmod_e
);
IOBUF i_iobuf_pmod_a0 (.IO(pmod_a[0]), .I(rmii_tx [0][0]), .O(), .T(1'b0));
IOBUF i_iobuf_pmod_a1 (.IO(pmod_a[1]), .I(1'b0), .O(rmii_rx [0][1]), .T(1'b1));
IOBUF i_iobuf_pmod_a2 (.IO(pmod_a[2]), .I(1'b0), .O(rmii_crs [0] ), .T(1'b1));
IOBUF i_iobuf_pmod_a3 (.IO(pmod_a[3]), .I(1'b1), .O(rmii_mdc [0] ), .T(1'b0));
IOBUF i_iobuf_pmod_a4 (.IO(pmod_a[4]), .I(rmii_txen [0]), .O(), .T(1'b0));
IOBUF i_iobuf_pmod_a5 (.IO(pmod_a[5]), .I(1'b0), .O(rmii_rx [0][0]), .T(1'b1));
IOBUF i_iobuf_pmod_a6 (.IO(pmod_a[6]), .I(1'b0), .O(rmii_refclk[0]), .T(1'b1));
IOBUF i_iobuf_pmod_a7 (.IO(pmod_a[7]), .I(rmii_mdio_o[0]), .O(rmii_mdio_i[0]), .T(rmii_mdio_t[0]));
IOBUF i_iobuf_pmod_c0 (.IO(pmod_c[0]), .I(rmii_tx [0][1]), .O(), .T(1'b0));
IOBUF i_iobuf_pmod_b0 (.IO(pmod_b[0]), .I(rmii_tx [1][0]), .O(), .T(1'b0));
IOBUF i_iobuf_pmod_b1 (.IO(pmod_b[1]), .I(1'b0), .O(rmii_rx [1][1]), .T(1'b1));
IOBUF i_iobuf_pmod_b2 (.IO(pmod_b[2]), .I(1'b0), .O(rmii_crs [1] ), .T(1'b1));
IOBUF i_iobuf_pmod_b3 (.IO(pmod_b[3]), .I(1'b1), .O(rmii_mdc [1] ), .T(1'b0));
IOBUF i_iobuf_pmod_b4 (.IO(pmod_b[4]), .I(rmii_txen [1]), .O(), .T(1'b0));
IOBUF i_iobuf_pmod_b5 (.IO(pmod_b[5]), .I(1'b0), .O(rmii_rx [1][0]), .T(1'b1));
IOBUF i_iobuf_pmod_b6 (.IO(pmod_b[6]), .I(1'b0), .O(rmii_refclk[1]), .T(1'b1));
IOBUF i_iobuf_pmod_b7 (.IO(pmod_b[7]), .I(rmii_mdio_o[1]), .O(rmii_mdio_i[1]), .T(rmii_mdio_t[1]));
IOBUF i_iobuf_pmod_c1 (.IO(pmod_c[1]), .I(rmii_tx [1][1]), .O(), .T(1'b0));
IOBUF i_iobuf_pmod_d0 (.IO(pmod_d[0]), .I(rmii_tx [2][0]), .O(), .T(1'b0));
IOBUF i_iobuf_pmod_d1 (.IO(pmod_d[1]), .I(1'b0), .O(rmii_rx [2][1]), .T(1'b1));
IOBUF i_iobuf_pmod_d2 (.IO(pmod_d[2]), .I(1'b0), .O(rmii_crs [2] ), .T(1'b1));
IOBUF i_iobuf_pmod_d3 (.IO(pmod_d[3]), .I(1'b1), .O(rmii_mdc [2] ), .T(1'b0));
IOBUF i_iobuf_pmod_d4 (.IO(pmod_d[4]), .I(rmii_txen [2]), .O(), .T(1'b0));
IOBUF i_iobuf_pmod_d5 (.IO(pmod_d[5]), .I(1'b0), .O(rmii_rx [2][0]), .T(1'b1));
IOBUF i_iobuf_pmod_d6 (.IO(pmod_d[6]), .I(1'b0), .O(rmii_refclk[2]), .T(1'b1));
IOBUF i_iobuf_pmod_d7 (.IO(pmod_d[7]), .I(rmii_mdio_o[2]), .O(rmii_mdio_i[2]), .T(rmii_mdio_t[2]));
IOBUF i_iobuf_pmod_c2 (.IO(pmod_c[2]), .I(rmii_tx [2][1]), .O(), .T(1'b0));
IOBUF i_iobuf_pmod_e0 (.IO(pmod_e[0]), .I(rmii_tx [3][0]), .O(), .T(1'b0));
IOBUF i_iobuf_pmod_e1 (.IO(pmod_e[1]), .I(1'b0), .O(rmii_rx [3][1]), .T(1'b1));
IOBUF i_iobuf_pmod_e2 (.IO(pmod_e[2]), .I(1'b0), .O(rmii_crs [3] ), .T(1'b1));
IOBUF i_iobuf_pmod_e3 (.IO(pmod_e[3]), .I(1'b1), .O(rmii_mdc [3] ), .T(1'b0));
IOBUF i_iobuf_pmod_e4 (.IO(pmod_e[4]), .I(rmii_txen [3]), .O(), .T(1'b0));
IOBUF i_iobuf_pmod_e5 (.IO(pmod_e[5]), .I(1'b0), .O(rmii_rx [3][0]), .T(1'b1));
IOBUF i_iobuf_pmod_e6 (.IO(pmod_e[6]), .I(1'b0), .O(rmii_refclk[3]), .T(1'b1));
IOBUF i_iobuf_pmod_e7 (.IO(pmod_e[7]), .I(rmii_mdio_o[3]), .O(rmii_mdio_i[3]), .T(rmii_mdio_t[3]));
IOBUF i_iobuf_pmod_c3 (.IO(pmod_c[3]), .I(rmii_tx [3][1]), .O(), .T(1'b0));
endmodule |
module jelly2_mipi_rx_lane
#(
parameter LANES = 2,
parameter TDATA_SIZE = 0,
parameter FIFO_PTR_WIDTH = 5,
parameter FIFO_RAM_TYPE = "distributed",
parameter ASYNC = 1,
parameter LANE_SYNC = 1,
parameter TDATA_WIDTH = (8 << TDATA_SIZE)
)
(
// input
input wire rxreseths,
input wire rxbyteclkhs,
input wire [LANES*8-1:0] rxdatahs,
input wire [LANES-1:0] rxvalidhs,
input wire [LANES-1:0] rxactivehs,
input wire [LANES-1:0] rxsynchs,
// output
input wire aresetn,
input wire aclk,
output wire [TDATA_WIDTH-1:0] m_axi4s_tdata,
output wire [0:0] m_axi4s_tuser,
output wire m_axi4s_tlast,
output wire m_axi4s_tvalid,
input wire m_axi4s_tready
);
wire reset = rxreseths;
wire clk = rxbyteclkhs;
// レーン間同期
wire [LANES*8-1:0] sync_rxdatahs;
wire [LANES-1:0] sync_rxvalidhs;
wire [LANES-1:0] sync_rxactivehs;
wire [LANES-1:0] sync_rxsynchs;
generate
if ( LANE_SYNC ) begin : blk_sync
jelly_mipi_rx_lane_sync
#(
.LANES (LANES)
)
i_mipi_rx_lane_sync
(
.reset (reset),
.clk (clk),
.in_rxdatahs (rxdatahs),
.in_rxvalidhs (rxvalidhs),
.in_rxactivehs (rxactivehs),
.in_rxsynchs (rxsynchs),
.out_rxdatahs (sync_rxdatahs),
.out_rxvalidhs (sync_rxvalidhs),
.out_rxactivehs (sync_rxactivehs),
.out_rxsynchs (sync_rxsynchs)
);
end
else begin : blk_bypass
assign sync_rxdatahs = rxdatahs;
assign sync_rxvalidhs = rxvalidhs;
assign sync_rxactivehs = rxactivehs;
assign sync_rxsynchs = rxsynchs;
end
endgenerate
// パケット切り出し
wire recv_first;
wire recv_last;
wire [LANES*8-1:0] recv_data;
wire recv_valid;
jelly_mipi_rx_lane_recv
#(
.LANES (LANES)
)
i_mipi_rx_lane_recv
(
.reset (reset),
.clk (clk),
.in_rxdatahs (sync_rxdatahs),
.in_rxvalidhs (sync_rxvalidhs),
.in_rxactivehs (sync_rxactivehs),
.in_rxsynchs (sync_rxsynchs),
.out_first (recv_first),
.out_last (recv_last),
.out_data (recv_data),
.out_valid (recv_valid)
);
// FIFO
wire fifo_first;
wire fifo_last;
wire [LANES*8-1:0] fifo_data;
wire fifo_valid;
wire fifo_ready;
jelly2_fifo_generic_fwtf
#(
.ASYNC (1),
.DATA_WIDTH (2+8*LANES),
.PTR_WIDTH (FIFO_PTR_WIDTH),
.DOUT_REGS (0),
.RAM_TYPE (FIFO_RAM_TYPE),
.LOW_DEALY (0),
.S_REGS (0),
.M_REGS (1)
)
i_fifo_generic_fwtf
(
.s_reset (reset),
.s_clk (clk),
.s_cke (1'b1),
.s_data ({recv_first, recv_last, recv_data}),
.s_valid (recv_valid),
.s_ready (),
.s_free_count (),
.m_reset (~aresetn),
.m_clk (aclk),
.m_cke (1'b1),
.m_data ({fifo_first, fifo_last, fifo_data}),
.m_valid (fifo_valid),
.m_ready (fifo_ready),
.m_data_count ()
);
// width convert
localparam LANE_SIZE = (LANES == 1) ? 0 :
(LANES == 2) ? 1 : 2;
jelly_data_width_converter
#(
.UNIT_WIDTH (8),
.S_DATA_SIZE (LANE_SIZE),
.M_DATA_SIZE (TDATA_SIZE)
)
i_data_width_converter
(
.reset (~aresetn),
.clk (aclk),
.cke (1'b1),
.endian (1'b0),
.s_data (fifo_data),
.s_first (fifo_first),
.s_last (fifo_last),
.s_valid (fifo_valid),
.s_ready (fifo_ready),
.m_data (m_axi4s_tdata),
.m_first (m_axi4s_tuser),
.m_last (m_axi4s_tlast),
.m_valid (m_axi4s_tvalid),
.m_ready (m_axi4s_tready)
);
endmodule |
module jelly2_mipi_csi2_rx_raw10
#(
parameter S_AXI4S_REGS = 0,
parameter M_AXI4S_REGS = 0
)
(
input wire aresetn,
input wire aclk,
input wire [0:0] s_axi4s_tuser,
input wire s_axi4s_tlast,
input wire [7:0] s_axi4s_tdata,
input wire s_axi4s_tvalid,
output wire s_axi4s_tready,
output wire [0:0] m_axi4s_tuser,
output wire m_axi4s_tlast,
output wire [9:0] m_axi4s_tdata,
output wire m_axi4s_tvalid,
input wire m_axi4s_tready
);
wire [0:0] conv_tuser;
wire conv_tlast;
wire [8*5-1:0] conv_tdata8;
wire [10*4-1:0] conv_tdata10;
wire conv_tvalid;
wire conv_tready;
jelly2_stream_width_convert
#(
.UNIT_WIDTH (8),
.S_NUM (1),
.M_NUM (5),
.HAS_FIRST (1),
.HAS_LAST (1),
.HAS_ALIGN_S (0),
.HAS_ALIGN_M (0),
.AUTO_FIRST (0),
.FIRST_OVERWRITE (1),
.FIRST_FORCE_LAST (0),
.ALIGN_S_WIDTH (1),
.ALIGN_M_WIDTH (1),
.S_REGS (1),
.M_REGS (1)
)
i_data_stream_convert_s
(
.reset (~aresetn),
.clk (aclk),
.cke (1'b1),
.endian (1'b0),
.padding ({8{1'bx}}),
.s_user_l ('0),
.s_user_f ('0),
.s_keep ('0),
.s_strb ('0),
.s_align_s (1'b0),
.s_align_m (1'b0),
.s_first (s_axi4s_tuser),
.s_last (s_axi4s_tlast),
.s_data (s_axi4s_tdata),
.s_valid (s_axi4s_tvalid),
.s_ready (s_axi4s_tready),
.m_user_l (),
.m_user_f (),
.m_keep (),
.m_strb (),
.m_first (conv_tuser),
.m_last (conv_tlast),
.m_data (conv_tdata8),
.m_valid (conv_tvalid),
.m_ready (conv_tready)
);
wire [7:0] lsb_data = conv_tdata8[4*8 +: 8];
assign conv_tdata10[0*10 +: 10] = {conv_tdata8[0*8 +: 8], lsb_data[0*2 +: 2]};
assign conv_tdata10[1*10 +: 10] = {conv_tdata8[1*8 +: 8], lsb_data[1*2 +: 2]};
assign conv_tdata10[2*10 +: 10] = {conv_tdata8[2*8 +: 8], lsb_data[2*2 +: 2]};
assign conv_tdata10[3*10 +: 10] = {conv_tdata8[3*8 +: 8], lsb_data[3*2 +: 2]};
jelly2_stream_width_convert
#(
.UNIT_WIDTH (10),
.S_NUM (4),
.M_NUM (1),
.HAS_FIRST (1),
.HAS_LAST (1),
.HAS_ALIGN_S (0),
.HAS_ALIGN_M (0),
.AUTO_FIRST (0),
.FIRST_OVERWRITE (1),
.FIRST_FORCE_LAST (0),
.ALIGN_S_WIDTH (1),
.ALIGN_M_WIDTH (1),
.S_REGS (1),
.M_REGS (1)
)
i_stream_width_convert_m
(
.reset (~aresetn),
.clk (aclk),
.cke (1'b1),
.endian (1'b0),
.padding ({10{1'bx}}),
.s_user_l ('0),
.s_user_f ('0),
.s_keep ('0),
.s_strb ('0),
.s_align_s (1'b0),
.s_align_m (1'b0),
.s_first (conv_tuser),
.s_last (conv_tlast),
.s_data (conv_tdata10),
.s_valid (conv_tvalid),
.s_ready (conv_tready),
.m_user_f (),
.m_user_l (),
.m_keep (),
.m_strb (),
.m_first (m_axi4s_tuser),
.m_last (m_axi4s_tlast),
.m_data (m_axi4s_tdata),
.m_valid (m_axi4s_tvalid),
.m_ready (m_axi4s_tready)
);
endmodule |
module jelly2_img_rgb2hsv
#(
parameter USER_WIDTH = 0,
parameter DATA_WIDTH = 8,
parameter USER_BITS = USER_WIDTH > 0 ? USER_WIDTH : 1
)
(
input wire reset,
input wire clk,
input wire cke,
input wire s_img_row_first,
input wire s_img_row_last,
input wire s_img_col_first,
input wire s_img_col_last,
input wire s_img_de,
input wire [USER_BITS-1:0] s_img_user,
input wire [DATA_WIDTH-1:0] s_img_r,
input wire [DATA_WIDTH-1:0] s_img_g,
input wire [DATA_WIDTH-1:0] s_img_b,
input wire s_img_valid,
output wire m_img_row_first,
output wire m_img_row_last,
output wire m_img_col_first,
output wire m_img_col_last,
output wire m_img_de,
output wire [USER_BITS-1:0] m_img_user,
output wire [DATA_WIDTH-1:0] m_img_h,
output wire [DATA_WIDTH-1:0] m_img_s,
output wire [DATA_WIDTH-1:0] m_img_v,
output wire m_img_valid
);
logic m_row_first;
logic m_row_last;
logic m_col_first;
logic m_col_last;
logic m_de;
logic [USER_BITS-1:0] m_user;
logic [DATA_WIDTH-1:0] m_h;
logic [DATA_WIDTH-1:0] m_s;
logic [DATA_WIDTH-1:0] m_v;
logic m_valid;
jelly2_rgb2hsv
#(
.USER_WIDTH (USER_BITS+5),
.DATA_WIDTH (DATA_WIDTH)
)
i_rgb2hsv
(
.reset,
.clk,
.cke,
.s_user ({
s_img_user,
s_img_row_first,
s_img_row_last,
s_img_col_first,
s_img_col_last,
s_img_de
}),
.s_r (s_img_r),
.s_g (s_img_g),
.s_b (s_img_b),
.s_valid (s_img_valid),
.m_user ({
m_user,
m_row_first,
m_row_last,
m_col_first,
m_col_last,
m_de
}),
.m_h (m_h),
.m_s (m_s),
.m_v (m_v),
.m_valid (m_valid)
);
assign m_img_row_first = m_row_first & m_valid;
assign m_img_row_last = m_row_last & m_valid;
assign m_img_col_first = m_col_first & m_valid;
assign m_img_col_last = m_col_last & m_valid;
assign m_img_de = m_de & m_valid;
assign m_img_user = m_user;
assign m_img_h = m_h;
assign m_img_s = m_s;
assign m_img_v = m_v;
assign m_img_valid = m_valid;
endmodule |
module jelly2_img_delay
#(
parameter USER_WIDTH = 0,
parameter USER_BITS = USER_WIDTH > 0 ? USER_WIDTH : 1,
parameter LATENCY = 1,
parameter USE_VALID = 0,
parameter INIT_USER = {USER_BITS{1'bx}}
)
(
input wire reset,
input wire clk,
input wire cke,
input wire s_img_col_first,
input wire s_img_col_last,
input wire s_img_row_first,
input wire s_img_row_last,
input wire s_img_de,
input wire [USER_BITS-1:0] s_img_user,
input wire s_img_valid,
output wire m_img_col_first,
output wire m_img_col_last,
output wire m_img_row_first,
output wire m_img_row_last,
output wire m_img_de,
output wire [USER_BITS-1:0] m_img_user,
output wire m_img_valid
);
wire [USER_BITS-1:0] delay_user;
wire delay_row_first;
wire delay_row_last;
wire delay_col_first;
wire delay_col_last;
wire delay_de;
wire delay_valid;
jelly_data_delay
#(
.LATENCY (LATENCY),
.DATA_WIDTH (USER_BITS + 6),
.DATA_INIT ({INIT_USER, 6'bxxxxx0})
)
i_data_delay
(
.reset (reset),
.clk (clk),
.cke (cke),
.in_data ({
s_img_user,
s_img_row_first,
s_img_row_last,
s_img_col_first,
s_img_col_last,
s_img_de,
s_img_valid
}),
.out_data ({
delay_user,
delay_row_first,
delay_row_last,
delay_col_first,
delay_col_last,
delay_de,
delay_valid
})
);
generate
if ( USE_VALID ) begin : blk_use_valid
assign m_img_row_first = delay_row_first;
assign m_img_row_last = delay_row_last;
assign m_img_col_first = delay_col_first;
assign m_img_col_last = delay_col_last;
assign m_img_de = delay_de;
assign m_img_user = delay_user;
assign m_img_valid = delay_valid;
end
else begin
assign m_img_row_first = delay_valid & delay_row_first;
assign m_img_row_last = delay_valid & delay_row_last;
assign m_img_col_first = delay_valid & delay_col_first;
assign m_img_col_last = delay_valid & delay_col_last;
assign m_img_de = delay_valid & delay_de;
assign m_img_user = delay_user;
assign m_img_valid = delay_valid;
end
endgenerate
endmodule |
module jelly2_axi4_read_width_convert
#(
parameter S_ARASYNC = 1, // s_ar <-> m_ar は非同期か
parameter S_RASYNC = 1, // s_r <-> m_ar は非同期か
parameter S_CASYNC = 1, // s_c <-> m_ar は非同期か
parameter M_RASYNC = 0, // m_r <-> m_ar は非同期か
parameter RASYNC = 1, // m_r <-> s_r は非同期か
parameter BYTE_WIDTH = 8,
parameter ALLOW_UNALIGNED = 0, // 非アライメント転送を許すか
parameter BYPASS_GATE = 0, // 強制的にGATEをバイパスさせる(上で責任をもって整形)
parameter HAS_S_RFIRST = 0, // s_rfirst は必要か
parameter HAS_S_RLAST = 1, // s_rlast は必要か
parameter HAS_M_RFIRST = 0, // コマンドと対応する m_rfirst がある(今のところ無意味)
parameter HAS_M_RLAST = 0, // コマンドと対応する m_rlast がある
parameter ARADDR_WIDTH = 32,
parameter ARUSER_WIDTH = 0,
parameter S_RDATA_WIDTH = 32, // BYTE_WIDTH の倍数であること
parameter S_RUSER_WIDTH = 0,
parameter S_ARLEN_WIDTH = 32,
parameter S_ARLEN_OFFSET = 1'b1,
parameter S_ARUSER_WIDTH = 0,
parameter M_RDATA_SIZE = 3, // log2 (0:8bit, 1:16bit, 2:32bit ...)
parameter M_RDATA_WIDTH = (BYTE_WIDTH << M_RDATA_SIZE),
parameter M_RUSER_WIDTH = S_RUSER_WIDTH * M_RDATA_WIDTH / S_RDATA_WIDTH,
parameter M_ARLEN_WIDTH = 32,
parameter M_ARLEN_OFFSET = 1'b1,
parameter M_ARUSER_WIDTH = 0,
parameter POST_CONVERT = (M_RDATA_WIDTH >= S_RDATA_WIDTH),
parameter CONVERT_S_REGS = 0,
parameter RFIFO_PTR_WIDTH = 9,
parameter RFIFO_RAM_TYPE = "block",
parameter RFIFO_LOW_DEALY = 0,
parameter RFIFO_DOUT_REGS = 1,
parameter RFIFO_S_REGS = 0,
parameter RFIFO_M_REGS = 1,
parameter ARFIFO_PTR_WIDTH = S_ARASYNC ? 4 : 0,
parameter ARFIFO_RAM_TYPE = "distributed",
parameter ARFIFO_LOW_DEALY = 1,
parameter ARFIFO_DOUT_REGS = 0,
parameter ARFIFO_S_REGS = 0,
parameter ARFIFO_M_REGS = 0,
parameter SRFIFO_PTR_WIDTH = 4,
parameter SRFIFO_RAM_TYPE = "distributed",
parameter SRFIFO_LOW_DEALY = 1,
parameter SRFIFO_DOUT_REGS = 0,
parameter SRFIFO_S_REGS = 0,
parameter SRFIFO_M_REGS = 0,
parameter MRFIFO_PTR_WIDTH = 4,
parameter MRFIFO_RAM_TYPE = "distributed",
parameter MRFIFO_LOW_DEALY = 1,
parameter MRFIFO_DOUT_REGS = 0,
parameter MRFIFO_S_REGS = 0,
parameter MRFIFO_M_REGS = 0,
// local
parameter ARUSER_BITS = ARUSER_WIDTH > 0 ? ARUSER_WIDTH : 1,
parameter S_RUSER_BITS = S_RUSER_WIDTH > 0 ? S_RUSER_WIDTH : 1,
parameter M_RUSER_BITS = M_RUSER_WIDTH > 0 ? M_RUSER_WIDTH : 1
)
(
input wire endian,
// address command
input wire s_arresetn,
input wire s_arclk,
input wire [ARADDR_WIDTH-1:0] s_araddr,
input wire [S_ARLEN_WIDTH-1:0] s_arlen,
input wire [ARUSER_BITS-1:0] s_aruser,
input wire s_arvalid,
output wire s_arready,
// read data (after FIFO convert)
input wire s_rresetn,
input wire s_rclk,
output wire s_rfirst,
output wire s_rlast,
output wire [S_RDATA_WIDTH-1:0] s_rdata,
output wire [S_RUSER_BITS-1:0] s_ruser,
output wire s_rvalid,
input wire s_rready,
output wire [RFIFO_PTR_WIDTH:0] rfifo_data_count,
output wire rfifo_rd_signal,
// acknowledge (before FIFO convert)
input wire s_cresetn,
input wire s_cclk,
output wire s_cvalid,
input wire s_cready,
// address command
input wire m_arresetn,
input wire m_arclk,
output wire [ARADDR_WIDTH-1:0] m_araddr,
output wire [M_ARLEN_WIDTH-1:0] m_arlen,
output wire [ARUSER_BITS-1:0] m_aruser,
output wire m_arvalid,
input wire m_arready,
// read data
input wire m_rresetn,
input wire m_rclk,
input wire [M_RDATA_WIDTH-1:0] m_rdata,
input wire m_rfirst,
input wire m_rlast,
input wire [M_RUSER_BITS-1:0] m_ruser,
input wire m_rvalid,
output wire m_rready,
output wire [RFIFO_PTR_WIDTH:0] rfifo_free_count,
output wire rfifo_wr_signal
);
// ---------------------------------
// localparam
// ---------------------------------
localparam ALIGN_WIDTH = M_RDATA_SIZE;
localparam ALIGN_BITS = ALIGN_WIDTH > 0 ? ALIGN_WIDTH : 1;
// ---------------------------------
// s_ar
// ---------------------------------
// m_ar 側にクロック載せ替え
wire [ARADDR_WIDTH-1:0] arfifo_araddr;
wire [S_ARLEN_WIDTH-1:0] arfifo_arlen;
wire [ARUSER_BITS-1:0] arfifo_aruser;
wire arfifo_arvalid;
wire arfifo_arready;
// verilator lint_off PINMISSING
jelly2_fifo_pack
#(
.ASYNC (S_ARASYNC),
.DATA0_WIDTH (ARADDR_WIDTH),
.DATA1_WIDTH (S_ARLEN_WIDTH),
.DATA2_WIDTH (ARUSER_WIDTH),
.PTR_WIDTH (ARFIFO_PTR_WIDTH),
.DOUT_REGS (ARFIFO_DOUT_REGS),
.RAM_TYPE (ARFIFO_RAM_TYPE),
.LOW_DEALY (ARFIFO_LOW_DEALY),
.S_REGS (ARFIFO_S_REGS),
.M_REGS (ARFIFO_M_REGS)
)
i_fifo_pack_cmd_ar
(
.s_reset (~s_arresetn),
.s_clk (s_arclk),
.s_cke (1'b1),
.s_data0 (s_araddr),
.s_data1 (s_arlen),
.s_data2 (s_aruser),
.s_valid (s_arvalid),
.s_ready (s_arready),
.m_reset (~m_arresetn),
.m_clk (m_arclk),
.m_cke (1'b1),
.m_data0 (arfifo_araddr),
.m_data1 (arfifo_arlen),
.m_data2 (arfifo_aruser),
.m_valid (arfifo_arvalid),
.m_ready (arfifo_arready)
);
// verilator lint_on PINMISSING
// address convert
wire [ARADDR_WIDTH-1:0] adrcnv_araddr;
wire [ALIGN_BITS-1:0] adrcnv_align;
wire [S_ARLEN_WIDTH-1:0] adrcnv_arlen_s;
wire [M_ARLEN_WIDTH-1:0] adrcnv_arlen_m;
wire [ARUSER_BITS-1:0] adrcnv_aruser;
wire adrcnv_arvalid;
wire adrcnv_arready;
jelly2_address_width_convert
#(
.ALLOW_UNALIGNED (ALLOW_UNALIGNED),
.ADDR_WIDTH (ARADDR_WIDTH),
.USER_WIDTH (ARUSER_BITS + S_ARLEN_WIDTH),
.S_UNIT (S_RDATA_WIDTH / BYTE_WIDTH),
.M_UNIT_SIZE (M_RDATA_SIZE),
.S_LEN_WIDTH (S_ARLEN_WIDTH),
.S_LEN_OFFSET (S_ARLEN_OFFSET),
.M_LEN_WIDTH (M_ARLEN_WIDTH),
.M_LEN_OFFSET (M_ARLEN_OFFSET)
)
i_address_width_conver
(
.reset (~m_arresetn),
.clk (m_arclk),
.cke (1'b1),
.s_addr (arfifo_araddr),
.s_len (arfifo_arlen),
.s_user ({arfifo_aruser, arfifo_arlen}),
.s_valid (arfifo_arvalid),
.s_ready (arfifo_arready),
.m_addr (adrcnv_araddr),
.m_align (adrcnv_align),
.m_len (adrcnv_arlen_m),
.m_user ({adrcnv_aruser, adrcnv_arlen_s}),
.m_valid (adrcnv_arvalid),
.m_ready (adrcnv_arready)
);
// アドレスコマンドと、データ制御用に分岐
wire [ARADDR_WIDTH-1:0] ar_araddr;
wire [M_ARLEN_WIDTH-1:0] ar_arlen;
wire [ARUSER_BITS-1:0] ar_aruser;
wire ar_arvalid;
wire ar_arready;
wire [M_ARLEN_WIDTH-1:0] mr_arlen;
wire [ALIGN_BITS-1:0] mr_align;
wire mr_arvalid;
wire mr_arready;
wire [S_ARLEN_WIDTH-1:0] sr_arlen;
wire sr_arvalid;
wire sr_arready;
// verilator lint_off PINMISSING
jelly2_data_split_pack2
#(
.NUM (3),
.DATA0_0_WIDTH (ARADDR_WIDTH),
.DATA0_1_WIDTH (M_ARLEN_WIDTH),
.DATA0_2_WIDTH (ARUSER_WIDTH),
.DATA1_0_WIDTH (M_ARLEN_WIDTH),
.DATA1_1_WIDTH (ALIGN_WIDTH),
.DATA2_0_WIDTH (S_ARLEN_WIDTH),
.S_REGS (0)
)
i_data_split_pack2_ar
(
.reset (~m_arresetn),
.clk (m_arclk),
.cke (1'b1),
.s_data0_0 (adrcnv_araddr),
.s_data0_1 (adrcnv_arlen_m),
.s_data0_2 (adrcnv_aruser),
.s_data1_0 (adrcnv_arlen_m),
.s_data1_1 (adrcnv_align),
.s_data2_0 (adrcnv_arlen_s),
.s_valid (adrcnv_arvalid),
.s_ready (adrcnv_arready),
.m0_data0 (ar_araddr),
.m0_data1 (ar_arlen),
.m0_data2 (ar_aruser),
.m0_valid (ar_arvalid),
.m0_ready (ar_arready),
.m1_data0 (mr_arlen),
.m1_data1 (mr_align),
.m1_valid (mr_arvalid),
.m1_ready (mr_arready),
.m2_data0 (sr_arlen),
.m2_valid (sr_arvalid),
.m2_ready (sr_arready)
);
// verilator lint_on PINMISSING
// command
assign m_araddr = ar_araddr;
assign m_arlen = ar_arlen;
assign m_aruser = ar_aruser;
assign m_arvalid = ar_arvalid;
assign ar_arready = m_arready;
// ---------------------------------
// rdata
// ---------------------------------
// gate (アライン補正の為、上位のアクセス単位で last をつけ直してalignをつける)
wire [ALIGN_BITS-1:0] gate_align;
wire [M_RDATA_WIDTH-1:0] gate_rdata;
wire [M_RUSER_BITS-1:0] gate_ruser;
wire gate_rlast;
wire gate_rvalid;
wire gate_rready;
jelly2_stream_gate
#(
.BYPASS (!(ALLOW_UNALIGNED && !HAS_M_RLAST)), // 基本アライメントしなければバイパスする
.BYPASS_COMBINE (ALLOW_UNALIGNED), // 下位からフラグが来る場合もalignはつける
.DETECTOR_ENABLE (0),
.DATA_WIDTH (M_RUSER_BITS + M_RDATA_WIDTH),
.LEN_WIDTH (M_ARLEN_WIDTH),
.LEN_OFFSET (M_ARLEN_OFFSET),
.USER_WIDTH (ALIGN_WIDTH),
.S_REGS (0),
.M_REGS (0),
.ASYNC (M_RASYNC),
.FIFO_PTR_WIDTH (MRFIFO_PTR_WIDTH),
.FIFO_DOUT_REGS (MRFIFO_DOUT_REGS),
.FIFO_RAM_TYPE (MRFIFO_RAM_TYPE),
.FIFO_LOW_DEALY (MRFIFO_LOW_DEALY),
.FIFO_S_REGS (MRFIFO_S_REGS),
.FIFO_M_REGS (MRFIFO_M_REGS)
)
i_stream_gate_m
(
.reset (~m_rresetn),
.clk (m_rclk),
.cke (1'b1),
.skip (1'b0),
.detect_first (1'b0),
.detect_last (1'b0),
.padding_en (1'b0),
.padding_data ({(M_RUSER_BITS + M_RDATA_WIDTH){1'b0}}),
.s_permit_reset (~m_arresetn),
.s_permit_clk (m_arclk),
.s_permit_first (1'b1),
.s_permit_last (1'b1),
.s_permit_len (mr_arlen),
.s_permit_user (mr_align),
.s_permit_valid (mr_arvalid),
.s_permit_ready (mr_arready),
.s_first (1'b0),
.s_last (m_rlast),
.s_data ({m_ruser, m_rdata}),
.s_valid (m_rvalid),
.s_ready (m_rready),
.m_first (),
.m_last (gate_rlast),
.m_data ({gate_ruser, gate_rdata}),
.m_user (gate_align),
.m_valid (gate_rvalid),
.m_ready (gate_rready)
);
// read response channel
jelly2_signal_transfer
#(
.ASYNC (S_CASYNC),
.CAPACITY_WIDTH (RFIFO_PTR_WIDTH)
)
i_signal_transfer
(
.s_reset (~m_arresetn),
.s_clk (m_arclk),
.s_valid (gate_rvalid & gate_rready & gate_rlast),
.m_reset (~s_cresetn),
.m_clk (s_cclk),
.m_valid (s_cvalid),
.m_ready (s_cready)
);
// fifo with width convert
wire [S_RDATA_WIDTH-1:0] conv_rdata;
wire conv_rfirst;
wire conv_rlast;
wire [S_RUSER_BITS-1:0] conv_ruser;
wire conv_rvalid;
wire conv_rready;
jelly2_axi4s_fifo_width_convert
#(
.ASYNC (RASYNC),
.FIFO_PTR_WIDTH (RFIFO_PTR_WIDTH),
.FIFO_RAM_TYPE (RFIFO_RAM_TYPE),
.FIFO_LOW_DEALY (RFIFO_LOW_DEALY),
.FIFO_DOUT_REGS (RFIFO_DOUT_REGS),
.FIFO_S_REGS (RFIFO_S_REGS),
.FIFO_M_REGS (RFIFO_M_REGS),
.HAS_STRB (0),
.HAS_KEEP (0),
.HAS_FIRST (0),
.HAS_LAST (ALLOW_UNALIGNED),
.HAS_ALIGN_S (ALLOW_UNALIGNED),
.HAS_ALIGN_M (0),
.S_TDATA_WIDTH (M_RDATA_WIDTH),
.M_TDATA_WIDTH (S_RDATA_WIDTH),
.S_TUSER_WIDTH (M_RUSER_WIDTH),
.FIRST_FORCE_LAST (0),
.FIRST_OVERWRITE (0),
.ALIGN_S_WIDTH (ALIGN_BITS),
.ALIGN_M_WIDTH (1),
.CONVERT_S_REGS (CONVERT_S_REGS),
.POST_CONVERT (POST_CONVERT)
)
i_axi4s_fifo_width_convert
(
.endian (endian),
.s_aresetn (m_rresetn),
.s_aclk (m_rclk),
.s_align_s (gate_align),
.s_align_m (1'b0),
.s_axi4s_tdata (gate_rdata),
.s_axi4s_tstrb ({(M_RDATA_WIDTH/8){1'b1}}),
.s_axi4s_tkeep ({(M_RDATA_WIDTH/8){1'b1}}),
.s_axi4s_tfirst (1'b0),
.s_axi4s_tlast (gate_rlast),
.s_axi4s_tuser (gate_ruser),
.s_axi4s_tvalid (gate_rvalid),
.s_axi4s_tready (gate_rready),
.fifo_free_count (rfifo_free_count),
.fifo_wr_signal (rfifo_wr_signal),
.m_aresetn (s_rresetn),
.m_aclk (s_rclk),
.m_axi4s_tdata (conv_rdata),
.m_axi4s_tstrb (),
.m_axi4s_tkeep (),
.m_axi4s_tfirst (conv_rfirst),
.m_axi4s_tlast (conv_rlast),
.m_axi4s_tuser (conv_ruser),
.m_axi4s_tvalid (conv_rvalid),
.m_axi4s_tready (conv_rready),
.fifo_data_count (rfifo_data_count),
.fifo_rd_signal (rfifo_rd_signal)
);
// gate (アライン補正の余分をカット。上位側で整形する場合はBYPASS_GATEで強制バイパス可)
jelly2_stream_gate
#(
.BYPASS (!ALLOW_UNALIGNED || BYPASS_GATE),
.DETECTOR_ENABLE (!BYPASS_GATE),
.DATA_WIDTH (S_RUSER_BITS + S_RDATA_WIDTH),
.LEN_WIDTH (S_ARLEN_WIDTH),
.LEN_OFFSET (S_ARLEN_OFFSET),
.USER_WIDTH (ALIGN_WIDTH),
.S_REGS (0),
.M_REGS (0),
.ASYNC (S_RASYNC),
.FIFO_PTR_WIDTH (SRFIFO_PTR_WIDTH),
.FIFO_DOUT_REGS (SRFIFO_DOUT_REGS),
.FIFO_RAM_TYPE (SRFIFO_RAM_TYPE),
.FIFO_LOW_DEALY (SRFIFO_LOW_DEALY),
.FIFO_S_REGS (SRFIFO_S_REGS),
.FIFO_M_REGS (SRFIFO_M_REGS)
)
i_stream_gate_s
(
.reset (~s_rresetn),
.clk (s_rclk),
.cke (1'b1),
.skip (1'b0),
.detect_first (1'b0),
.detect_last (ALLOW_UNALIGNED),
.padding_en (1'b0),
.padding_data ({(S_RUSER_BITS + S_RDATA_WIDTH){1'b0}}),
.s_first (conv_rfirst),
.s_last (conv_rlast),
.s_data ({conv_ruser, conv_rdata}),
.s_valid (conv_rvalid),
.s_ready (conv_rready),
.m_first (s_rfirst),
.m_last (s_rlast),
.m_data ({s_ruser, s_rdata}),
.m_user (),
.m_valid (s_rvalid),
.m_ready (s_rready),
.s_permit_reset (~m_arresetn),
.s_permit_clk (m_arclk),
.s_permit_first (1'b1),
.s_permit_last (1'b1),
.s_permit_len (sr_arlen),
.s_permit_user ({ALIGN_WIDTH{1'b0}}),
.s_permit_valid (sr_arvalid),
.s_permit_ready (sr_arready)
);
endmodule |
module jelly2_axi4_read
#(
parameter ARASYNC = 1,
parameter RASYNC = 1,
parameter CASYNC = 1,
parameter BYTE_WIDTH = 8,
parameter BYPASS_GATE = 0,
parameter BYPASS_ALIGN = 0,
parameter ALLOW_UNALIGNED = 0,
parameter HAS_RFIRST = 0,
parameter HAS_RLAST = 0,
parameter AXI4_ID_WIDTH = 6,
parameter AXI4_ADDR_WIDTH = 32,
parameter AXI4_DATA_SIZE = 2, // 0:8bit, 1:16bit, 2:32bit ...
parameter AXI4_DATA_WIDTH = (BYTE_WIDTH << AXI4_DATA_SIZE),
parameter AXI4_LEN_WIDTH = 8,
parameter AXI4_QOS_WIDTH = 4,
parameter AXI4_ARID = {AXI4_ID_WIDTH{1'b0}},
parameter AXI4_ARSIZE = AXI4_DATA_SIZE,
parameter AXI4_ARBURST = 2'b01,
parameter AXI4_ARLOCK = 1'b0,
parameter AXI4_ARCACHE = 4'b0001,
parameter AXI4_ARPROT = 3'b000,
parameter AXI4_ARQOS = 0,
parameter AXI4_ARREGION = 4'b0000,
parameter AXI4_ALIGN = 12, // 2^12 = 4k が境界
parameter S_RDATA_WIDTH = 32,
parameter S_ARLEN_WIDTH = 12,
parameter S_ARLEN_OFFSET = 1'b1,
parameter CAPACITY_WIDTH = S_ARLEN_WIDTH,
parameter CONVERT_S_REGS = 0,
parameter RFIFO_PTR_WIDTH = 9,
parameter RFIFO_RAM_TYPE = "block",
parameter RFIFO_LOW_DEALY = 0,
parameter RFIFO_DOUT_REGS = 1,
parameter RFIFO_S_REGS = 0,
parameter RFIFO_M_REGS = 0,
parameter ARFIFO_PTR_WIDTH = 4,
parameter ARFIFO_RAM_TYPE = "distributed",
parameter ARFIFO_LOW_DEALY = 1,
parameter ARFIFO_DOUT_REGS = 0,
parameter ARFIFO_S_REGS = 0,
parameter ARFIFO_M_REGS = 0,
parameter SRFIFO_PTR_WIDTH = 4,
parameter SRFIFO_RAM_TYPE = "distributed",
parameter SRFIFO_LOW_DEALY = 0,
parameter SRFIFO_DOUT_REGS = 0,
parameter SRFIFO_S_REGS = 0,
parameter SRFIFO_M_REGS = 0,
parameter MRFIFO_PTR_WIDTH = 4,
parameter MRFIFO_RAM_TYPE = "distributed",
parameter MRFIFO_LOW_DEALY = 1,
parameter MRFIFO_DOUT_REGS = 0,
parameter MRFIFO_S_REGS = 0,
parameter MRFIFO_M_REGS = 0
)
(
input wire endian,
input wire s_arresetn,
input wire s_arclk,
input wire [AXI4_ADDR_WIDTH-1:0] s_araddr,
input wire [S_ARLEN_WIDTH-1:0] s_arlen,
input wire [AXI4_LEN_WIDTH-1:0] s_arlen_max,
input wire s_arvalid,
output wire s_arready,
input wire s_rresetn,
input wire s_rclk,
output wire [S_RDATA_WIDTH-1:0] s_rdata,
output wire s_rfirst,
output wire s_rlast,
output wire s_rvalid,
input wire s_rready,
input wire s_cresetn,
input wire s_cclk,
output wire s_cvalid,
input wire s_cready,
input wire m_aresetn,
input wire m_aclk,
output wire [AXI4_ID_WIDTH-1:0] m_axi4_arid,
output wire [AXI4_ADDR_WIDTH-1:0] m_axi4_araddr,
output wire [AXI4_LEN_WIDTH-1:0] m_axi4_arlen,
output wire [2:0] m_axi4_arsize,
output wire [1:0] m_axi4_arburst,
output wire [0:0] m_axi4_arlock,
output wire [3:0] m_axi4_arcache,
output wire [2:0] m_axi4_arprot,
output wire [AXI4_QOS_WIDTH-1:0] m_axi4_arqos,
output wire [3:0] m_axi4_arregion,
output wire m_axi4_arvalid,
input wire m_axi4_arready,
input wire [AXI4_ID_WIDTH-1:0] m_axi4_rid,
input wire [AXI4_DATA_WIDTH-1:0] m_axi4_rdata,
input wire [1:0] m_axi4_rresp,
input wire m_axi4_rlast,
input wire m_axi4_rvalid,
output wire m_axi4_rready
);
// ---------------------------------
// local parameter
// ---------------------------------
localparam UNALIGNED = ((S_RDATA_WIDTH & (S_RDATA_WIDTH - 1)) != 0) || ALLOW_UNALIGNED;
wire [AXI4_ADDR_WIDTH-1:0] addr_mask = UNALIGNED ? 0 : (1 << AXI4_DATA_SIZE) - 1;
// ---------------------------------
// bus width convert
// ---------------------------------
wire [AXI4_ADDR_WIDTH-1:0] conv_araddr;
wire [CAPACITY_WIDTH-1:0] conv_arlen;
wire [AXI4_LEN_WIDTH-1:0] conv_arlen_max;
wire conv_arvalid;
wire conv_arready;
wire s_rfifo_rd_signal;
jelly2_axi4_read_width_convert
#(
.S_ARASYNC (ARASYNC),
.S_RASYNC (RASYNC),
.S_CASYNC (CASYNC),
.M_RASYNC (0),
.RASYNC (RASYNC),
.BYTE_WIDTH (BYTE_WIDTH),
.ALLOW_UNALIGNED (UNALIGNED),
.BYPASS_GATE (BYPASS_GATE),
.HAS_S_RFIRST (HAS_RFIRST),
.HAS_S_RLAST (HAS_RLAST),
.HAS_M_RFIRST (0),
.HAS_M_RLAST (0), // コマンド分割するので利用できない
.ARADDR_WIDTH (AXI4_ADDR_WIDTH),
.ARUSER_WIDTH (AXI4_LEN_WIDTH),
.S_RDATA_WIDTH (S_RDATA_WIDTH),
.S_RUSER_WIDTH (0),
.S_ARLEN_WIDTH (S_ARLEN_WIDTH),
.S_ARLEN_OFFSET (S_ARLEN_OFFSET),
.S_ARUSER_WIDTH (0),
.M_RDATA_SIZE (AXI4_DATA_SIZE),
.M_RUSER_WIDTH (0),
.M_ARLEN_WIDTH (CAPACITY_WIDTH),
.M_ARLEN_OFFSET (1'b1),
.M_ARUSER_WIDTH (0),
.RFIFO_PTR_WIDTH (RFIFO_PTR_WIDTH),
.RFIFO_RAM_TYPE (RFIFO_RAM_TYPE),
.RFIFO_LOW_DEALY (RFIFO_LOW_DEALY),
.RFIFO_DOUT_REGS (RFIFO_DOUT_REGS),
.RFIFO_S_REGS (RFIFO_S_REGS),
.RFIFO_M_REGS (RFIFO_M_REGS),
.ARFIFO_PTR_WIDTH (ARFIFO_PTR_WIDTH),
.ARFIFO_RAM_TYPE (ARFIFO_RAM_TYPE),
.ARFIFO_LOW_DEALY (ARFIFO_LOW_DEALY),
.ARFIFO_DOUT_REGS (ARFIFO_DOUT_REGS),
.ARFIFO_S_REGS (ARFIFO_S_REGS),
.ARFIFO_M_REGS (ARFIFO_M_REGS),
.SRFIFO_PTR_WIDTH (SRFIFO_PTR_WIDTH),
.SRFIFO_RAM_TYPE (SRFIFO_RAM_TYPE),
.SRFIFO_LOW_DEALY (SRFIFO_LOW_DEALY),
.SRFIFO_DOUT_REGS (SRFIFO_DOUT_REGS),
.SRFIFO_S_REGS (SRFIFO_S_REGS),
.SRFIFO_M_REGS (SRFIFO_M_REGS),
.MRFIFO_PTR_WIDTH (MRFIFO_PTR_WIDTH),
.MRFIFO_RAM_TYPE (MRFIFO_RAM_TYPE),
.MRFIFO_LOW_DEALY (MRFIFO_LOW_DEALY),
.MRFIFO_DOUT_REGS (MRFIFO_DOUT_REGS),
.MRFIFO_S_REGS (MRFIFO_S_REGS),
.MRFIFO_M_REGS (MRFIFO_M_REGS),
.CONVERT_S_REGS (CONVERT_S_REGS),
.POST_CONVERT (1)
)
i_axi4_read_width_convert
(
.endian (endian),
.s_arresetn (s_arresetn),
.s_arclk (s_arclk),
.s_araddr (s_araddr & ~addr_mask),
.s_arlen (s_arlen),
.s_aruser (s_arlen_max),
.s_arvalid (s_arvalid),
.s_arready (s_arready),
.s_rresetn (s_rresetn),
.s_rclk (s_rclk),
.s_rfirst (s_rfirst),
.s_rlast (s_rlast),
.s_rdata (s_rdata),
.s_ruser (),
.s_rvalid (s_rvalid),
.s_rready (s_rready),
.rfifo_data_count (),
.rfifo_rd_signal (s_rfifo_rd_signal),
.s_cresetn (s_cresetn),
.s_cclk (s_cclk),
.s_cvalid (s_cvalid),
.s_cready (s_cready),
.m_arresetn (m_aresetn),
.m_arclk (m_aclk),
.m_araddr (conv_araddr),
.m_arlen (conv_arlen),
.m_aruser (conv_arlen_max),
.m_arvalid (conv_arvalid),
.m_arready (conv_arready),
.m_rresetn (m_aresetn),
.m_rclk (m_aclk),
.m_rdata (m_axi4_rdata),
.m_rfirst (1'b0),
.m_rlast (m_axi4_rlast),
.m_ruser (1'b0),
.m_rvalid (m_axi4_rvalid),
.m_rready (m_axi4_rready),
.rfifo_free_count (),
.rfifo_wr_signal ()
);
// FIFO 書き込み済み量を CAPACIY として管理
wire [CAPACITY_WIDTH-1:0] conv_rd_size;
wire conv_rd_valid;
wire conv_rd_ready;
jelly2_capacity_async
#(
.ASYNC (RASYNC),
.CAPACITY_WIDTH (CAPACITY_WIDTH),
.REQUEST_WIDTH (1),
.ISSUE_WIDTH (CAPACITY_WIDTH),
.REQUEST_SIZE_OFFSET (1'b1),
.ISSUE_SIZE_OFFSET (1'b0)
)
i_capacity_async
(
.s_reset (~s_rresetn),
.s_clk (s_rclk),
.s_request_size (1'b0),
.s_request_valid (s_rfifo_rd_signal),
.s_queued_request (),
.m_reset (~m_aresetn),
.m_clk (m_aclk),
.m_issue_size (conv_rd_size),
.m_issue_valid (conv_rd_valid),
.m_issue_ready (conv_rd_ready),
.m_queued_request ()
);
// ---------------------------------
// Read command capacity control
// ---------------------------------
wire [AXI4_ADDR_WIDTH-1:0] adrgen_araddr;
wire [AXI4_LEN_WIDTH-1:0] adrgen_arlen;
wire adrgen_arlast;
wire adrgen_arvalid;
wire adrgen_arready;
jelly2_address_generator
#(
.ADDR_WIDTH (AXI4_ADDR_WIDTH),
.ADDR_UNIT (1 << AXI4_DATA_SIZE),
.SIZE_WIDTH (CAPACITY_WIDTH),
.SIZE_OFFSET (1'b1),
.LEN_WIDTH (AXI4_LEN_WIDTH),
.LEN_OFFSET (1'b1),
.S_REGS (0)
)
i_address_generator
(
.reset (~m_aresetn),
.clk (m_aclk),
.cke (1'b1),
.s_addr (conv_araddr),
.s_size (conv_arlen),
.s_max_len (conv_arlen_max),
.s_valid (conv_arvalid),
.s_ready (conv_arready),
.m_addr (adrgen_araddr),
.m_len (adrgen_arlen),
.m_last (),
.m_valid (adrgen_arvalid),
.m_ready (adrgen_arready)
);
// capacity (FIFOに書き込み終わった分だけ発行)
wire [AXI4_ADDR_WIDTH-1:0] capsize_araddr;
wire [AXI4_LEN_WIDTH-1:0] capsize_arlen;
wire capsize_arvalid;
wire capsize_arready;
wire [CAPACITY_WIDTH-1:0] initial_capacity = (1 << RFIFO_PTR_WIDTH);
jelly2_capacity_size
#(
.CAPACITY_WIDTH (CAPACITY_WIDTH),
.CMD_USER_WIDTH (AXI4_ADDR_WIDTH),
.CMD_SIZE_WIDTH (AXI4_LEN_WIDTH),
.CMD_SIZE_OFFSET (1'b1),
.CHARGE_WIDTH (CAPACITY_WIDTH),
.CHARGE_SIZE_OFFSET (1'b0),
.S_REGS (1),
.M_REGS (1)
)
i_capacity_size
(
.reset (~m_aresetn),
.clk (m_aclk),
.cke (1'b1),
.initial_capacity (initial_capacity),
.current_capacity (),
.s_charge_size (conv_rd_size),
.s_charge_valid (conv_rd_valid & conv_rd_ready),
.s_cmd_user (adrgen_araddr),
.s_cmd_size (adrgen_arlen),
.s_cmd_valid (adrgen_arvalid),
.s_cmd_ready (adrgen_arready),
.m_cmd_user (capsize_araddr),
.m_cmd_size (capsize_arlen),
.m_cmd_valid (capsize_arvalid),
.m_cmd_ready (capsize_arready)
);
assign conv_rd_ready = 1'b1;
// 4kアライメント処理
wire [AXI4_ADDR_WIDTH-1:0] align_araddr;
wire [AXI4_LEN_WIDTH-1:0] align_arlen;
wire align_arvalid;
wire align_arready;
jelly2_address_align_split
#(
.BYPASS (BYPASS_ALIGN),
.USER_WIDTH (0),
.ADDR_WIDTH (AXI4_ADDR_WIDTH),
.UNIT_SIZE (AXI4_DATA_SIZE),
.LEN_WIDTH (AXI4_LEN_WIDTH),
.ALIGN (AXI4_ALIGN),
.S_REGS (0)
)
i_address_align_split
(
.reset (~m_aresetn),
.clk (m_aclk),
.cke (1'b1),
.s_addr (capsize_araddr),
.s_len (capsize_arlen),
.s_first (1'b0),
.s_last (1'b0),
.s_user (1'b0),
.s_valid (capsize_arvalid),
.s_ready (capsize_arready),
.m_first (),
.m_last (),
.m_addr (align_araddr),
.m_len (align_arlen),
.m_user (),
.m_valid (align_arvalid),
.m_ready (align_arready)
);
// ar
assign m_axi4_arid = AXI4_ARID;
assign m_axi4_araddr = align_araddr;
assign m_axi4_arlen = align_arlen;
assign m_axi4_arsize = AXI4_ARSIZE;
assign m_axi4_arburst = AXI4_ARBURST;
assign m_axi4_arlock = AXI4_ARLOCK;
assign m_axi4_arcache = AXI4_ARCACHE;
assign m_axi4_arprot = AXI4_ARPROT;
assign m_axi4_arqos = AXI4_ARQOS;
assign m_axi4_arregion = AXI4_ARREGION;
assign m_axi4_arvalid = align_arvalid;
assign align_arready = m_axi4_arready;
endmodule |
module jelly2_axi4_write_width_convert
#(
parameter AWASYNC = 1,
parameter WASYNC = 1,
parameter AW_W_ASYNC = (AWASYNC || WASYNC),
parameter BYTE_WIDTH = 8,
parameter BYPASS_GATE = 1,
parameter ALLOW_UNALIGNED = 0,
parameter HAS_S_WSTRB = 0,
parameter HAS_S_WFIRST = 0,
parameter HAS_S_WLAST = 0,
parameter HAS_M_WSTRB = 0,
parameter HAS_M_WFIRST = 0,
parameter HAS_M_WLAST = 0,
parameter AWADDR_WIDTH = 32,
parameter AWUSER_WIDTH = 0,
parameter S_WDATA_WIDTH = 32, // 8の倍数であること
parameter S_WSTRB_WIDTH = S_WDATA_WIDTH / BYTE_WIDTH,
parameter S_WUSER_WIDTH = 0,
parameter S_AWLEN_WIDTH = 32,
parameter S_AWLEN_OFFSET = 1'b1,
parameter S_AWUSER_WIDTH = 0,
parameter M_WDATA_SIZE = 3, // log2 (0:8bit, 1:16bit, 2:32bit ...)
parameter M_WDATA_WIDTH = (BYTE_WIDTH << M_WDATA_SIZE),
parameter M_WSTRB_WIDTH = M_WDATA_WIDTH / BYTE_WIDTH,
parameter M_WUSER_WIDTH = S_WUSER_WIDTH * M_WDATA_WIDTH / S_WDATA_WIDTH,
parameter M_AWLEN_WIDTH = 32,
parameter M_AWLEN_OFFSET = 1'b1,
parameter M_AWUSER_WIDTH = 0,
parameter WFIFO_PTR_WIDTH = 9,
parameter WFIFO_RAM_TYPE = "block",
parameter WFIFO_LOW_DEALY = 0,
parameter WFIFO_DOUT_REGS = 1,
parameter WFIFO_S_REGS = 0,
parameter WFIFO_M_REGS = 1,
parameter AWFIFO_PTR_WIDTH = 4,
parameter AWFIFO_RAM_TYPE = "distributed",
parameter AWFIFO_LOW_DEALY = 1,
parameter AWFIFO_DOUT_REGS = 0,
parameter AWFIFO_S_REGS = 0,
parameter AWFIFO_M_REGS = 0,
parameter SWFIFOPTR_WIDTH = 4,
parameter SWFIFORAM_TYPE = "distributed",
parameter SWFIFOLOW_DEALY = 1,
parameter SWFIFODOUT_REGS = 0,
parameter SWFIFOS_REGS = 0,
parameter SWFIFOM_REGS = 0,
parameter CONVERT_S_REGS = 0,
parameter POST_CONVERT = (M_WDATA_WIDTH < S_WDATA_WIDTH),
// local
parameter AWUSER_BITS = AWUSER_WIDTH > 0 ? AWUSER_WIDTH : 1,
parameter S_WUSER_BITS = S_WUSER_WIDTH > 0 ? S_WUSER_WIDTH : 1,
parameter M_WUSER_BITS = M_WUSER_WIDTH > 0 ? M_WUSER_WIDTH : 1
)
(
input wire endian,
input wire s_awresetn,
input wire s_awclk,
input wire [AWADDR_WIDTH-1:0] s_awaddr,
input wire [S_AWLEN_WIDTH-1:0] s_awlen,
input wire [AWUSER_BITS-1:0] s_awuser,
input wire s_awvalid,
output wire s_awready,
input wire s_wresetn,
input wire s_wclk,
input wire s_wfirst,
input wire s_wlast,
input wire [S_WDATA_WIDTH-1:0] s_wdata,
input wire [S_WSTRB_WIDTH-1:0] s_wstrb,
input wire [S_WUSER_BITS-1:0] s_wuser,
input wire s_wvalid,
output wire s_wready,
output wire [WFIFO_PTR_WIDTH:0] wfifo_free_count,
output wire wfifo_wr_signal,
input wire m_awresetn,
input wire m_awclk,
output wire [AWADDR_WIDTH-1:0] m_awaddr,
output wire [M_AWLEN_WIDTH-1:0] m_awlen,
output wire [AWUSER_BITS-1:0] m_awuser,
output wire m_awvalid,
input wire m_awready,
input wire m_wresetn,
input wire m_wclk,
output wire [M_WDATA_WIDTH-1:0] m_wdata,
output wire [M_WSTRB_WIDTH-1:0] m_wstrb,
output wire m_wfirst,
output wire m_wlast,
output wire [M_WUSER_BITS-1:0] m_wuser,
output wire m_wvalid,
input wire m_wready,
output wire [WFIFO_PTR_WIDTH:0] wfifo_data_count,
output wire wfifo_rd_signal
);
// ---------------------------------
// localparam
// ---------------------------------
localparam ALIGN_WIDTH = M_WDATA_SIZE;
localparam ALIGN_BITS = ALIGN_WIDTH > 0 ? ALIGN_WIDTH : 1;
// ---------------------------------
// s_aw
// ---------------------------------
// master 側にクロック載せ替え
wire [AWADDR_WIDTH-1:0] awfifo_awaddr;
wire [S_AWLEN_WIDTH-1:0] awfifo_awlen;
wire [AWUSER_BITS-1:0] awfifo_awuser;
wire awfifo_awvalid;
wire awfifo_awready;
// verilator lint_off PINMISSING
jelly2_fifo_pack
#(
.ASYNC (AWASYNC),
.DATA0_WIDTH (AWADDR_WIDTH),
.DATA1_WIDTH (S_AWLEN_WIDTH),
.DATA2_WIDTH (AWUSER_WIDTH),
.PTR_WIDTH (AWFIFO_PTR_WIDTH),
.DOUT_REGS (AWFIFO_DOUT_REGS),
.RAM_TYPE (AWFIFO_RAM_TYPE),
.LOW_DEALY (AWFIFO_LOW_DEALY),
.S_REGS (AWFIFO_S_REGS),
.M_REGS (AWFIFO_M_REGS)
)
i_fifo_pack_cmd_aw
(
.s_reset (~s_awresetn),
.s_clk (s_awclk),
.s_cke (1'b1),
.s_data0 (s_awaddr),
.s_data1 (s_awlen),
.s_data2 (s_awuser),
.s_valid (s_awvalid),
.s_ready (s_awready),
.m_reset (~m_awresetn),
.m_clk (m_awclk),
.m_cke (1'b1),
.m_data0 (awfifo_awaddr),
.m_data1 (awfifo_awlen),
.m_data2 (awfifo_awuser),
.m_valid (awfifo_awvalid),
.m_ready (awfifo_awready)
);
// verilator lint_on PINMISSING
// address convert
wire [AWADDR_WIDTH-1:0] adrcnv_awaddr;
wire [ALIGN_BITS-1:0] adrcnv_align;
wire [S_AWLEN_WIDTH-1:0] adrcnv_awlen_s;
wire [M_AWLEN_WIDTH-1:0] adrcnv_awlen_m;
wire [AWUSER_BITS-1:0] adrcnv_awuser;
wire adrcnv_awvalid;
wire adrcnv_awready;
jelly2_address_width_convert
#(
.ALLOW_UNALIGNED (ALLOW_UNALIGNED),
.ADDR_WIDTH (AWADDR_WIDTH),
.USER_WIDTH (AWUSER_BITS + S_AWLEN_WIDTH),
.S_UNIT (S_WDATA_WIDTH / BYTE_WIDTH),
.M_UNIT_SIZE (M_WDATA_SIZE),
.S_LEN_WIDTH (S_AWLEN_WIDTH),
.S_LEN_OFFSET (S_AWLEN_OFFSET),
.M_LEN_WIDTH (M_AWLEN_WIDTH),
.M_LEN_OFFSET (M_AWLEN_OFFSET)
)
i_address_width_convert
(
.reset (~m_awresetn),
.clk (m_awclk),
.cke (1'b1),
.s_addr (awfifo_awaddr),
.s_len (awfifo_awlen),
.s_user ({awfifo_awuser, awfifo_awlen}),
.s_valid (awfifo_awvalid),
.s_ready (awfifo_awready),
.m_addr (adrcnv_awaddr),
.m_align (adrcnv_align),
.m_len (adrcnv_awlen_m),
.m_user ({adrcnv_awuser, adrcnv_awlen_s}),
.m_valid (adrcnv_awvalid),
.m_ready (adrcnv_awready)
);
// アドレスコマンドと、データ制御用に分岐
wire [AWADDR_WIDTH-1:0] cmd_awaddr;
wire [M_AWLEN_WIDTH-1:0] cmd_awlen;
wire [AWUSER_BITS-1:0] cmd_awuser;
wire cmd_awvalid;
wire cmd_awready;
wire [S_AWLEN_WIDTH-1:0] dat_awlen;
wire [ALIGN_BITS-1:0] dat_align;
wire dat_awvalid;
wire dat_awready;
// verilator lint_off PINMISSING
jelly2_data_split_pack2
#(
.NUM (2),
.DATA0_0_WIDTH (AWADDR_WIDTH),
.DATA0_1_WIDTH (M_AWLEN_WIDTH),
.DATA0_2_WIDTH (AWUSER_WIDTH),
.DATA1_0_WIDTH (S_AWLEN_WIDTH),
.DATA1_1_WIDTH (ALIGN_WIDTH),
.S_REGS (0)
)
i_data_split_pack2_aw
(
.reset (~m_awresetn),
.clk (m_awclk),
.cke (1'b1),
.s_data0_0 (adrcnv_awaddr),
.s_data0_1 (adrcnv_awlen_m),
.s_data0_2 (adrcnv_awuser),
.s_data1_0 (adrcnv_awlen_s),
.s_data1_1 (adrcnv_align),
.s_valid (adrcnv_awvalid),
.s_ready (adrcnv_awready),
.m0_data0 (cmd_awaddr),
.m0_data1 (cmd_awlen),
.m0_data2 (cmd_awuser),
.m0_valid (cmd_awvalid),
.m0_ready (cmd_awready),
.m1_data0 (dat_awlen),
.m1_data1 (dat_align),
.m1_valid (dat_awvalid),
.m1_ready (dat_awready)
);
// verilator lint_on PINMISSING
assign m_awaddr = cmd_awaddr;
assign m_awlen = cmd_awlen;
assign m_awuser = cmd_awuser;
assign m_awvalid = cmd_awvalid;
assign cmd_awready = m_awready;
// ---------------------------------
// wdata
// ---------------------------------
// s_w 側のクロックに載せ替え
wire [S_AWLEN_WIDTH-1:0] datfifo_awlen;
wire [ALIGN_BITS-1:0] datfifo_align;
wire datfifo_awvalid;
wire datfifo_awready;
// verilator lint_off PINMISSING
jelly2_fifo_pack
#(
.ASYNC (WASYNC),
.DATA0_WIDTH (S_AWLEN_WIDTH),
.DATA1_WIDTH (ALIGN_WIDTH),
.PTR_WIDTH (SWFIFOPTR_WIDTH),
.DOUT_REGS (SWFIFODOUT_REGS),
.RAM_TYPE (SWFIFORAM_TYPE),
.LOW_DEALY (SWFIFOLOW_DEALY),
.S_REGS (SWFIFOS_REGS),
.M_REGS (SWFIFOM_REGS)
)
i_fifo_pack_dat
(
.s_reset (~m_awresetn),
.s_clk (m_awclk),
.s_cke (1'b1),
.s_data0 (dat_awlen),
.s_data1 (dat_align),
.s_valid (dat_awvalid),
.s_ready (dat_awready),
.m_reset (~s_wresetn),
.m_clk (s_wclk),
.m_cke (1'b1),
.m_data0 (datfifo_awlen),
.m_data1 (datfifo_align),
.m_valid (datfifo_awvalid),
.m_ready (datfifo_awready)
);
// verilator lint_on PINMISSING
// gate
wire [ALIGN_BITS-1:0] gate_align;
wire [S_WDATA_WIDTH-1:0] gate_wdata;
wire [S_WSTRB_WIDTH-1:0] gate_wstrb;
wire [S_WUSER_BITS-1:0] gate_wuser;
wire gate_wfirst;
wire gate_wlast;
wire gate_wvalid;
wire gate_wready;
jelly2_stream_gate
#(
.BYPASS (BYPASS_GATE && !HAS_S_WLAST),
.DETECTOR_ENABLE (0),
.DATA_WIDTH (S_WUSER_BITS + S_WSTRB_WIDTH + S_WDATA_WIDTH),
.LEN_WIDTH (S_AWLEN_WIDTH),
.LEN_OFFSET (S_AWLEN_OFFSET),
.USER_WIDTH (ALIGN_WIDTH),
.S_REGS (0),
.M_REGS (1)
)
i_stream_gate
(
.reset (~s_wresetn),
.clk (s_wclk),
.cke (1'b1),
.skip (1'b0),
.detect_first (1'b0),
.detect_last (1'b0),
.padding_en (1'b0),
.padding_data ({{S_WUSER_BITS{1'bx}}, {S_WSTRB_WIDTH{1'b0}}, {S_WDATA_WIDTH{1'b0}}}),
.s_permit_reset (~s_wresetn),
.s_permit_clk (s_wclk),
.s_permit_first (1'b1),
.s_permit_last (1'b1),
.s_permit_len (datfifo_awlen),
.s_permit_user (datfifo_align),
.s_permit_valid (datfifo_awvalid),
.s_permit_ready (datfifo_awready),
.s_first (HAS_S_WFIRST ? s_wfirst : 1'b0),
.s_last (HAS_S_WLAST ? s_wlast : 1'b0),
.s_data ({s_wuser, s_wstrb, s_wdata}),
.s_valid (s_wvalid),
.s_ready (s_wready),
.m_first (gate_wfirst),
.m_last (gate_wlast),
.m_data ({gate_wuser, gate_wstrb, gate_wdata}),
.m_user (gate_align),
.m_valid (gate_wvalid),
.m_ready (gate_wready)
);
// fifo with width convert
wire [M_WDATA_WIDTH-1:0] conv_wdata;
wire [M_WSTRB_WIDTH-1:0] conv_wstrb;
wire conv_wfirst;
wire conv_wlast;
wire [M_WUSER_BITS-1:0] conv_wuser;
wire conv_wvalid;
wire conv_wready;
jelly2_axi4s_fifo_width_convert
#(
.ASYNC (WASYNC),
.FIFO_PTR_WIDTH (WFIFO_PTR_WIDTH),
.FIFO_RAM_TYPE (WFIFO_RAM_TYPE),
.FIFO_LOW_DEALY (WFIFO_LOW_DEALY),
.FIFO_DOUT_REGS (WFIFO_DOUT_REGS),
.FIFO_S_REGS (WFIFO_S_REGS),
.FIFO_M_REGS (WFIFO_M_REGS),
.HAS_STRB (ALLOW_UNALIGNED),
.HAS_KEEP (0),
.HAS_FIRST (0),
.HAS_LAST (ALLOW_UNALIGNED),
.HAS_ALIGN_S (0),
.HAS_ALIGN_M (ALLOW_UNALIGNED),
.S_TDATA_WIDTH (S_WDATA_WIDTH),
.M_TDATA_WIDTH (M_WDATA_WIDTH),
.S_TUSER_WIDTH (S_WUSER_WIDTH),
.FIRST_FORCE_LAST (0),
.FIRST_OVERWRITE (0),
.ALIGN_S_WIDTH (1),
.ALIGN_M_WIDTH (ALIGN_BITS),
.CONVERT_S_REGS (CONVERT_S_REGS),
.POST_CONVERT (POST_CONVERT)
)
i_axi4s_fifo_width_convert
(
.endian (endian),
.s_aresetn (s_wresetn),
.s_aclk (s_wclk),
.s_align_s (1'b0),
.s_align_m (gate_align),
.s_axi4s_tdata (gate_wdata),
.s_axi4s_tstrb (HAS_S_WSTRB ? gate_wstrb : {S_WSTRB_WIDTH{1'b1}}),
.s_axi4s_tkeep ({S_WSTRB_WIDTH{1'b1}}),
.s_axi4s_tfirst (gate_wfirst),
.s_axi4s_tlast (gate_wlast),
.s_axi4s_tuser (gate_wuser),
.s_axi4s_tvalid (gate_wvalid),
.s_axi4s_tready (gate_wready),
.fifo_free_count (wfifo_free_count),
.fifo_wr_signal (wfifo_wr_signal),
.m_aresetn (m_wresetn),
.m_aclk (m_wclk),
.m_axi4s_tdata (conv_wdata),
.m_axi4s_tstrb (conv_wstrb),
.m_axi4s_tkeep (),
.m_axi4s_tfirst (conv_wfirst),
.m_axi4s_tlast (conv_wlast),
.m_axi4s_tuser (conv_wuser),
.m_axi4s_tvalid (conv_wvalid),
.m_axi4s_tready (conv_wready),
.fifo_data_count (wfifo_data_count),
.fifo_rd_signal (wfifo_rd_signal)
);
assign m_wdata = conv_wdata;
assign m_wstrb = HAS_M_WSTRB ? conv_wstrb : {M_WSTRB_WIDTH{1'b1}};
assign m_wfirst = HAS_M_WFIRST ? conv_wfirst : 1'b0;
assign m_wlast = HAS_M_WLAST ? conv_wlast : 1'b0;
assign m_wuser = conv_wuser;
assign m_wvalid = conv_wvalid;
assign conv_wready = m_wready;
endmodule |
module jelly2_axi4_read_nd
#(
parameter N = 2,
parameter ARASYNC = 1,
parameter RASYNC = 1,
parameter CASYNC = 1,
parameter BYTE_WIDTH = 8,
parameter BYPASS_GATE = 1,
parameter BYPASS_ALIGN = 0,
parameter ALLOW_UNALIGNED = 0,
parameter HAS_RFIRST = 0,
parameter HAS_RLAST = 1,
parameter AXI4_ID_WIDTH = 6,
parameter AXI4_ADDR_WIDTH = 32,
parameter AXI4_DATA_SIZE = 2, // 0:8bit, 1:16bit, 2:32bit ...
parameter AXI4_DATA_WIDTH = (BYTE_WIDTH << AXI4_DATA_SIZE),
parameter AXI4_LEN_WIDTH = 8,
parameter AXI4_QOS_WIDTH = 4,
parameter AXI4_ARID = {AXI4_ID_WIDTH{1'b0}},
parameter AXI4_ARSIZE = AXI4_DATA_SIZE,
parameter AXI4_ARBURST = 2'b01,
parameter AXI4_ARLOCK = 1'b0,
parameter AXI4_ARCACHE = 4'b0001,
parameter AXI4_ARPROT = 3'b000,
parameter AXI4_ARQOS = 0,
parameter AXI4_ARREGION = 4'b0000,
parameter AXI4_ALIGN = 12, // 2^12 = 4k が境界
parameter S_RDATA_WIDTH = 32,
parameter S_ARSTEP_WIDTH = AXI4_ADDR_WIDTH,
parameter S_ARLEN_WIDTH = 12,
parameter S_ARLEN_OFFSET = 1'b1,
parameter CAPACITY_WIDTH = S_RDATA_WIDTH, // 内部キューイング用
parameter CONVERT_S_REGS = 0,
parameter RFIFO_PTR_WIDTH = 9,
parameter RFIFO_RAM_TYPE = "block",
parameter RFIFO_LOW_DEALY = 0,
parameter RFIFO_DOUT_REGS = 1,
parameter RFIFO_S_REGS = 0,
parameter RFIFO_M_REGS = 1,
parameter ARFIFO_PTR_WIDTH = 4,
parameter ARFIFO_RAM_TYPE = "distributed",
parameter ARFIFO_LOW_DEALY = 1,
parameter ARFIFO_DOUT_REGS = 0,
parameter ARFIFO_S_REGS = 0,
parameter ARFIFO_M_REGS = 0,
parameter SRFIFO_PTR_WIDTH = 4,
parameter SRFIFO_RAM_TYPE = "distributed",
parameter SRFIFO_LOW_DEALY = 0,
parameter SRFIFO_DOUT_REGS = 0,
parameter SRFIFO_S_REGS = 0,
parameter SRFIFO_M_REGS = 0,
parameter MRFIFO_PTR_WIDTH = 4,
parameter MRFIFO_RAM_TYPE = "distributed",
parameter MRFIFO_LOW_DEALY = 1,
parameter MRFIFO_DOUT_REGS = 0,
parameter MRFIFO_S_REGS = 0,
parameter MRFIFO_M_REGS = 0,
parameter RACKFIFO_PTR_WIDTH = 4,
parameter RACKFIFO_DOUT_REGS = 0,
parameter RACKFIFO_RAM_TYPE = "distributed",
parameter RACKFIFO_LOW_DEALY = 1,
parameter RACKFIFO_S_REGS = 0,
parameter RACKFIFO_M_REGS = 0,
parameter RACK_S_REGS = 0,
parameter RACK_M_REGS = 1,
parameter CACKFIFO_PTR_WIDTH = 4,
parameter CACKFIFO_DOUT_REGS = 0,
parameter CACKFIFO_RAM_TYPE = "distributed",
parameter CACKFIFO_LOW_DEALY = 1,
parameter CACKFIFO_S_REGS = 0,
parameter CACKFIFO_M_REGS = 0,
parameter CACK_S_REGS = 0,
parameter CACK_M_REGS = 0
)
(
input wire endian,
input wire s_arresetn,
input wire s_arclk,
input wire [AXI4_ADDR_WIDTH-1:0] s_araddr,
input wire [AXI4_LEN_WIDTH-1:0] s_arlen_max,
input wire [N*S_ARSTEP_WIDTH-1:0] s_arstep, // step0は無視(1固定、つまり連続アクセスのみ)
input wire [N*S_ARLEN_WIDTH-1:0] s_arlen,
input wire s_arvalid,
output wire s_arready,
input wire s_rresetn,
input wire s_rclk,
output wire [S_RDATA_WIDTH-1:0] s_rdata,
output wire [N-1:0] s_rfirst,
output wire [N-1:0] s_rlast,
output wire s_rvalid,
input wire s_rready,
input wire s_cresetn,
input wire s_cclk,
output wire [N-1:0] s_cfirst,
output wire [N-1:0] s_clast,
output wire s_cvalid,
input wire s_cready,
input wire m_aresetn,
input wire m_aclk,
output wire [AXI4_ID_WIDTH-1:0] m_axi4_arid,
output wire [AXI4_ADDR_WIDTH-1:0] m_axi4_araddr,
output wire [AXI4_LEN_WIDTH-1:0] m_axi4_arlen,
output wire [2:0] m_axi4_arsize,
output wire [1:0] m_axi4_arburst,
output wire [0:0] m_axi4_arlock,
output wire [3:0] m_axi4_arcache,
output wire [2:0] m_axi4_arprot,
output wire [AXI4_QOS_WIDTH-1:0] m_axi4_arqos,
output wire [3:0] m_axi4_arregion,
output wire m_axi4_arvalid,
input wire m_axi4_arready,
input wire [AXI4_ID_WIDTH-1:0] m_axi4_rid,
input wire [AXI4_DATA_WIDTH-1:0] m_axi4_rdata,
input wire [1:0] m_axi4_rresp,
input wire m_axi4_rlast,
input wire m_axi4_rvalid,
output wire m_axi4_rready
);
// ---------------------------------------------
// N-Dimension addressing
// ---------------------------------------------
// m_ar 側にクロック載せ替え
wire [AXI4_ADDR_WIDTH-1:0] arfifo_araddr;
wire [AXI4_LEN_WIDTH-1:0] arfifo_arlen_max;
wire [N*S_ARSTEP_WIDTH-1:0] arfifo_arstep;
wire [N*S_ARLEN_WIDTH-1:0] arfifo_arlen;
wire arfifo_arvalid;
wire arfifo_arready;
// verilator lint_off PINMISSING
jelly2_fifo_pack
#(
.ASYNC (ARASYNC),
.DATA0_WIDTH (AXI4_ADDR_WIDTH),
.DATA1_WIDTH (AXI4_LEN_WIDTH),
.DATA2_WIDTH (N*S_ARSTEP_WIDTH),
.DATA3_WIDTH (N*S_ARLEN_WIDTH),
.PTR_WIDTH (ARFIFO_PTR_WIDTH),
.DOUT_REGS (ARFIFO_DOUT_REGS),
.RAM_TYPE (ARFIFO_RAM_TYPE),
.LOW_DEALY (ARFIFO_LOW_DEALY),
.S_REGS (ARFIFO_S_REGS),
.M_REGS (ARFIFO_M_REGS)
)
i_fifo_pack_cmd_ar
(
.s_reset (~s_arresetn),
.s_clk (s_arclk),
.s_cke (1'b1),
.s_data0 (s_araddr),
.s_data1 (s_arlen_max),
.s_data2 (s_arstep),
.s_data3 (s_arlen),
.s_valid (s_arvalid),
.s_ready (s_arready),
.m_reset (~m_aresetn),
.m_clk (m_aclk),
.m_cke (1'b1),
.m_data0 (arfifo_araddr),
.m_data1 (arfifo_arlen_max),
.m_data2 (arfifo_arstep),
.m_data3 (arfifo_arlen),
.m_valid (arfifo_arvalid),
.m_ready (arfifo_arready)
);
// verilator lint_on PINMISSING
// address generate
wire [AXI4_ADDR_WIDTH-1:0] adrgen_araddr;
wire [S_ARLEN_WIDTH-1:0] adrgen_arlen;
wire [AXI4_LEN_WIDTH-1:0] adrgen_arlen_max;
wire [N-1:0] adrgen_arfirst;
wire [N-1:0] adrgen_arlast;
wire adrgen_arvalid;
wire adrgen_arready;
generate
if ( N >= 2 ) begin : blk_adrgen_nd
// 2D以上のアドレッシング
jelly2_address_generator_nd
#(
.N (N-1),
.ADDR_WIDTH (AXI4_ADDR_WIDTH),
.STEP_WIDTH (S_ARSTEP_WIDTH),
.LEN_WIDTH (S_ARLEN_WIDTH),
.LEN_OFFSET (S_ARLEN_OFFSET),
.USER_WIDTH (S_ARLEN_WIDTH + AXI4_LEN_WIDTH)
)
i_address_generator_nd
(
.reset (~m_aresetn),
.clk (m_aclk),
.cke (1'b1),
.s_addr (arfifo_araddr),
.s_step (arfifo_arstep[N*S_ARSTEP_WIDTH-1:S_ARSTEP_WIDTH]),
.s_len (arfifo_arlen [N*S_ARLEN_WIDTH-1:S_ARLEN_WIDTH]),
.s_user ({arfifo_arlen[S_ARLEN_WIDTH-1:0], arfifo_arlen_max}),
.s_valid (arfifo_arvalid),
.s_ready (arfifo_arready),
.m_addr (adrgen_araddr),
.m_first (adrgen_arfirst[N-1:1]),
.m_last (adrgen_arlast[N-1:1]),
.m_user ({adrgen_arlen, adrgen_arlen_max}),
.m_valid (adrgen_arvalid),
.m_ready (adrgen_arready)
);
assign adrgen_arfirst[0] = 1'b1;
assign adrgen_arlast[0] = 1'b1;
end
else begin : blk_1d
assign adrgen_araddr = arfifo_araddr;
assign adrgen_arlen = arfifo_arlen;
assign adrgen_arlen_max = arfifo_arlen_max;
assign adrgen_arfirst = 1'b1;
assign adrgen_arlast = 1'b1;
assign adrgen_arvalid = arfifo_arvalid;
assign arfifo_arready = adrgen_arready;
end
endgenerate
// コマンド分岐
wire [AXI4_ADDR_WIDTH-1:0] cmd_araddr;
wire [S_ARLEN_WIDTH-1:0] cmd_arlen;
wire [AXI4_LEN_WIDTH-1:0] cmd_arlen_max;
wire cmd_arvalid;
wire cmd_arready;
wire [N-1:0] dat_arfirst;
wire [N-1:0] dat_arlast;
wire [S_ARLEN_WIDTH-1:0] dat_arlen;
wire dat_arvalid;
wire dat_arready;
wire [N-1:0] ack_arfirst;
wire [N-1:0] ack_arlast;
wire ack_arvalid;
wire ack_arready;
// verilator lint_off PINMISSING
jelly2_data_split_pack2
#(
.NUM (3),
.DATA0_0_WIDTH (AXI4_ADDR_WIDTH),
.DATA0_1_WIDTH (S_ARLEN_WIDTH),
.DATA0_2_WIDTH (AXI4_LEN_WIDTH),
.DATA1_0_WIDTH (N),
.DATA1_1_WIDTH (N),
.DATA1_2_WIDTH (S_ARLEN_WIDTH),
.DATA2_0_WIDTH (N),
.DATA2_1_WIDTH (N),
.S_REGS (1)
)
i_data_split_pack2
(
.reset (~m_aresetn),
.clk (m_aclk),
.cke (1'b1),
.s_data0_0 (adrgen_araddr),
.s_data0_1 (adrgen_arlen),
.s_data0_2 (adrgen_arlen_max),
.s_data1_0 (adrgen_arfirst),
.s_data1_1 (adrgen_arlast),
.s_data1_2 (adrgen_arlen),
.s_data2_0 (adrgen_arfirst),
.s_data2_1 (adrgen_arlast),
.s_valid (adrgen_arvalid),
.s_ready (adrgen_arready),
.m0_data0 (cmd_araddr),
.m0_data1 (cmd_arlen),
.m0_data2 (cmd_arlen_max),
.m0_valid (cmd_arvalid),
.m0_ready (cmd_arready),
.m1_data0 (dat_arfirst),
.m1_data1 (dat_arlast),
.m1_data2 (dat_arlen),
.m1_valid (dat_arvalid),
.m1_ready (dat_arready),
.m2_data0 (ack_arfirst),
.m2_data1 (ack_arlast),
.m2_valid (ack_arvalid),
.m2_ready (ack_arready)
);
// verilator lint_on PINMISSING
// ---------------------------------------------
// 1D read core
// ---------------------------------------------
wire [S_RDATA_WIDTH-1:0] read_rdata;
wire read_rfirst;
wire read_rlast;
wire read_rvalid;
wire read_rready;
wire read_cvalid;
wire read_cready;
jelly2_axi4_read
#(
.ARASYNC (0),
.RASYNC (RASYNC),
.BYTE_WIDTH (BYTE_WIDTH),
.BYPASS_GATE (0),
.BYPASS_ALIGN (BYPASS_ALIGN),
.AXI4_ALIGN (AXI4_ALIGN),
.ALLOW_UNALIGNED (ALLOW_UNALIGNED),
.HAS_RFIRST (0),
.HAS_RLAST (ALLOW_UNALIGNED || HAS_RFIRST || HAS_RLAST),
.AXI4_ID_WIDTH (AXI4_ID_WIDTH),
.AXI4_ADDR_WIDTH (AXI4_ADDR_WIDTH),
.AXI4_DATA_SIZE (AXI4_DATA_SIZE),
.AXI4_DATA_WIDTH (AXI4_DATA_WIDTH),
.AXI4_LEN_WIDTH (AXI4_LEN_WIDTH),
.AXI4_QOS_WIDTH (AXI4_QOS_WIDTH),
.AXI4_ARID (AXI4_ARID),
.AXI4_ARSIZE (AXI4_ARSIZE),
.AXI4_ARBURST (AXI4_ARBURST),
.AXI4_ARLOCK (AXI4_ARLOCK),
.AXI4_ARCACHE (AXI4_ARCACHE),
.AXI4_ARPROT (AXI4_ARPROT),
.AXI4_ARQOS (AXI4_ARQOS),
.AXI4_ARREGION (AXI4_ARREGION),
.S_RDATA_WIDTH (S_RDATA_WIDTH),
.S_ARLEN_WIDTH (S_ARLEN_WIDTH),
.S_ARLEN_OFFSET (S_ARLEN_OFFSET),
.CAPACITY_WIDTH (CAPACITY_WIDTH),
.CONVERT_S_REGS (CONVERT_S_REGS),
.RFIFO_PTR_WIDTH (RFIFO_PTR_WIDTH),
.RFIFO_RAM_TYPE (RFIFO_RAM_TYPE),
.RFIFO_LOW_DEALY (RFIFO_LOW_DEALY),
.RFIFO_DOUT_REGS (RFIFO_DOUT_REGS),
.RFIFO_S_REGS (RFIFO_S_REGS),
.RFIFO_M_REGS (RFIFO_M_REGS),
.ARFIFO_PTR_WIDTH (0),
.ARFIFO_RAM_TYPE (ARFIFO_RAM_TYPE),
.ARFIFO_LOW_DEALY (ARFIFO_LOW_DEALY),
.ARFIFO_DOUT_REGS (ARFIFO_DOUT_REGS),
.ARFIFO_S_REGS (ARFIFO_S_REGS),
.ARFIFO_M_REGS (ARFIFO_M_REGS),
.SRFIFO_PTR_WIDTH (SRFIFO_PTR_WIDTH),
.SRFIFO_RAM_TYPE (SRFIFO_RAM_TYPE),
.SRFIFO_LOW_DEALY (SRFIFO_LOW_DEALY),
.SRFIFO_DOUT_REGS (SRFIFO_DOUT_REGS),
.SRFIFO_S_REGS (SRFIFO_S_REGS),
.SRFIFO_M_REGS (SRFIFO_M_REGS),
.MRFIFO_PTR_WIDTH (MRFIFO_PTR_WIDTH),
.MRFIFO_RAM_TYPE (MRFIFO_RAM_TYPE),
.MRFIFO_LOW_DEALY (MRFIFO_LOW_DEALY),
.MRFIFO_DOUT_REGS (MRFIFO_DOUT_REGS),
.MRFIFO_S_REGS (MRFIFO_S_REGS),
.MRFIFO_M_REGS (MRFIFO_M_REGS)
)
i_axi4_read
(
.endian (endian),
.s_arresetn (m_aresetn),
.s_arclk (m_aclk),
.s_araddr (cmd_araddr),
.s_arlen (cmd_arlen),
.s_arlen_max (cmd_arlen_max),
.s_arvalid (cmd_arvalid),
.s_arready (cmd_arready),
.s_rresetn (s_rresetn),
.s_rclk (s_rclk),
.s_rdata (read_rdata),
.s_rfirst (read_rfirst),
.s_rlast (read_rlast),
.s_rvalid (read_rvalid),
.s_rready (read_rready),
.s_cresetn (s_cresetn),
.s_cclk (s_cclk),
.s_cvalid (read_cvalid),
.s_cready (read_cready),
.m_aresetn (m_aresetn),
.m_aclk (m_aclk),
.m_axi4_arid (m_axi4_arid),
.m_axi4_araddr (m_axi4_araddr),
.m_axi4_arlen (m_axi4_arlen),
.m_axi4_arsize (m_axi4_arsize),
.m_axi4_arburst (m_axi4_arburst),
.m_axi4_arlock (m_axi4_arlock),
.m_axi4_arcache (m_axi4_arcache),
.m_axi4_arprot (m_axi4_arprot),
.m_axi4_arqos (m_axi4_arqos),
.m_axi4_arregion (m_axi4_arregion),
.m_axi4_arvalid (m_axi4_arvalid),
.m_axi4_arready (m_axi4_arready),
.m_axi4_rid (m_axi4_rid),
.m_axi4_rdata (m_axi4_rdata),
.m_axi4_rresp (m_axi4_rresp),
.m_axi4_rlast (m_axi4_rlast),
.m_axi4_rvalid (m_axi4_rvalid),
.m_axi4_rready (m_axi4_rready)
);
// ---------------------------------------------
// read data
// ---------------------------------------------
// r ポートの成形＆フラグ付与 (read_rlast のみ信用できる前提で残りを作る)
wire gate_flag_f;
wire gate_flag_l;
wire [S_RDATA_WIDTH-1:0] gate_rdata;
wire [N-1:0] gate_rfirst;
wire [N-1:0] gate_rlast;
wire gate_rvalid;
wire gate_rready;
jelly2_stream_gate
#(
.N (1),
.BYPASS ((!ALLOW_UNALIGNED && !HAS_RFIRST) || BYPASS_GATE),
.BYPASS_COMBINE (HAS_RFIRST || HAS_RLAST),
.DETECTOR_ENABLE (ALLOW_UNALIGNED),
.DATA_WIDTH (S_RDATA_WIDTH),
.LEN_WIDTH (S_ARLEN_WIDTH),
.LEN_OFFSET (S_ARLEN_OFFSET),
.USER_WIDTH (N + N),
.S_REGS (0),
.M_REGS (0),
.ASYNC (ARASYNC || RASYNC),
.FIFO_PTR_WIDTH (CACKFIFO_PTR_WIDTH),
.FIFO_DOUT_REGS (CACKFIFO_DOUT_REGS),
.FIFO_RAM_TYPE (CACKFIFO_RAM_TYPE),
.FIFO_LOW_DEALY (CACKFIFO_LOW_DEALY),
.FIFO_S_REGS (CACKFIFO_S_REGS),
.FIFO_M_REGS (CACKFIFO_M_REGS)
)
i_stream_gate
(
.reset (~s_rresetn),
.clk (s_rclk),
.cke (1'b1),
.skip (1'b0),
.detect_first (1'b0),
.detect_last (1'b1),
.padding_en (1'b0),
.padding_data ({S_RDATA_WIDTH{1'bx}}),
.s_first (1'b0),
.s_last (read_rlast),
.s_data (read_rdata),
.s_valid (read_rvalid),
.s_ready (read_rready),
.m_first (gate_flag_f),
.m_last (gate_flag_l),
.m_data (gate_rdata),
.m_user ({gate_rfirst, gate_rlast}),
.m_valid (gate_rvalid),
.m_ready (gate_rready),
.s_permit_reset (~m_aresetn),
.s_permit_clk (m_aclk),
.s_permit_first (1'b1),
.s_permit_last (1'b1),
.s_permit_len (dat_arlen),
.s_permit_user ({dat_arfirst, dat_arlast}),
.s_permit_valid (dat_arvalid),
.s_permit_ready (dat_arready)
);
assign s_rfirst = (HAS_RFIRST && gate_flag_f) ? gate_rfirst : {N{1'b0}};
assign s_rlast = (HAS_RLAST && gate_flag_l) ? gate_rlast : {N{1'b0}};
assign s_rdata = gate_rdata;
assign s_rvalid = gate_rvalid;
assign gate_rready = s_rready;
/*
jelly2_stream_add_syncflag
#(
.FIRST_WIDTH (N),
.LAST_WIDTH (N),
.USER_WIDTH (S_RDATA_WIDTH),
.HAS_FIRST (HAS_S_RFIRST),
.HAS_LAST (HAS_S_RLAST),
.ASYNC (ARASYNC || RASYNC),
.FIFO_PTR_WIDTH (RACKFIFO_PTR_WIDTH),
.FIFO_DOUT_REGS (RACKFIFO_DOUT_REGS),
.FIFO_RAM_TYPE (RACKFIFO_RAM_TYPE),
.FIFO_LOW_DEALY (RACKFIFO_LOW_DEALY),
.FIFO_S_REGS (RACKFIFO_S_REGS),
.FIFO_M_REGS (RACKFIFO_M_REGS),
.S_REGS (RACK_S_REGS),
.M_REGS (RACK_M_REGS)
)
i_stream_add_syncflag_r
(
.reset (~s_rresetn),
.clk (s_rclk),
.cke (1'b1),
.s_first (read_rfirst),
.s_last (read_rlast),
.s_user (read_rdata),
.s_valid (read_rvalid),
.s_ready (read_rready),
.m_first (),
.m_last (),
.m_added_first (s_rfirst),
.m_added_last (s_rlast),
.m_user (s_rdata),
.m_valid (s_rvalid),
.m_ready (s_rready),
.s_add_reset (~s_arresetn),
.s_add_clk (s_arclk),
.s_add_first (dat_arfirst),
.s_add_last (dat_arlast),
.s_add_valid (dat_arvalid),
.s_add_ready (dat_arready)
);
*/
// ---------------------------------------------
// read ack
// ---------------------------------------------
// c ポートにフラグ付与
jelly2_stream_add_syncflag
#(
.FIRST_WIDTH (N),
.LAST_WIDTH (N),
.USER_WIDTH (0),
.HAS_FIRST (1),
.HAS_LAST (1),
.ASYNC (ARASYNC || RASYNC),
.FIFO_PTR_WIDTH (CACKFIFO_PTR_WIDTH),
.FIFO_DOUT_REGS (CACKFIFO_DOUT_REGS),
.FIFO_RAM_TYPE (CACKFIFO_RAM_TYPE),
.FIFO_LOW_DEALY (CACKFIFO_LOW_DEALY),
.FIFO_S_REGS (CACKFIFO_S_REGS),
.FIFO_M_REGS (CACKFIFO_M_REGS),
.S_REGS (CACK_S_REGS),
.M_REGS (CACK_M_REGS)
)
i_stream_add_syncflag_rb
(
.reset (~s_cresetn),
.clk (s_cclk),
.cke (1'b1),
.s_first (1'b1),
.s_last (1'b1),
.s_user (1'b0),
.s_valid (read_cvalid),
.s_ready (read_cready),
.m_first (),
.m_last (),
.m_added_first (s_cfirst),
.m_added_last (s_clast),
.m_user (),
.m_valid (s_cvalid),
.m_ready (s_cready),
.s_add_reset (~m_aresetn),
.s_add_clk (m_aclk),
.s_add_first (ack_arfirst),
.s_add_last (ack_arlast),
.s_add_valid (ack_arvalid),
.s_add_ready (ack_arready)
);
endmodule |
module jelly2_data_ff_pack
#(
parameter DATA0_WIDTH = 32,
parameter DATA1_WIDTH = 0,
parameter DATA2_WIDTH = 0,
parameter DATA3_WIDTH = 0,
parameter DATA4_WIDTH = 0,
parameter DATA5_WIDTH = 0,
parameter DATA6_WIDTH = 0,
parameter DATA7_WIDTH = 0,
parameter DATA8_WIDTH = 0,
parameter DATA9_WIDTH = 0,
parameter S_REGS = 1,
parameter M_REGS = 1,
// local
parameter DATA0_BITS = DATA0_WIDTH > 0 ? DATA0_WIDTH : 1,
parameter DATA1_BITS = DATA1_WIDTH > 0 ? DATA1_WIDTH : 1,
parameter DATA2_BITS = DATA2_WIDTH > 0 ? DATA2_WIDTH : 1,
parameter DATA3_BITS = DATA3_WIDTH > 0 ? DATA3_WIDTH : 1,
parameter DATA4_BITS = DATA4_WIDTH > 0 ? DATA4_WIDTH : 1,
parameter DATA5_BITS = DATA5_WIDTH > 0 ? DATA5_WIDTH : 1,
parameter DATA6_BITS = DATA6_WIDTH > 0 ? DATA6_WIDTH : 1,
parameter DATA7_BITS = DATA7_WIDTH > 0 ? DATA7_WIDTH : 1,
parameter DATA8_BITS = DATA8_WIDTH > 0 ? DATA8_WIDTH : 1,
parameter DATA9_BITS = DATA9_WIDTH > 0 ? DATA9_WIDTH : 1
)
(
input wire reset,
input wire clk,
input wire cke,
input wire [DATA0_BITS-1:0] s_data0,
input wire [DATA1_BITS-1:0] s_data1,
input wire [DATA2_BITS-1:0] s_data2,
input wire [DATA3_BITS-1:0] s_data3,
input wire [DATA4_BITS-1:0] s_data4,
input wire [DATA5_BITS-1:0] s_data5,
input wire [DATA6_BITS-1:0] s_data6,
input wire [DATA7_BITS-1:0] s_data7,
input wire [DATA8_BITS-1:0] s_data8,
input wire [DATA9_BITS-1:0] s_data9,
input wire s_valid,
output wire s_ready,
output wire [DATA0_BITS-1:0] m_data0,
output wire [DATA1_BITS-1:0] m_data1,
output wire [DATA2_BITS-1:0] m_data2,
output wire [DATA3_BITS-1:0] m_data3,
output wire [DATA4_BITS-1:0] m_data4,
output wire [DATA5_BITS-1:0] m_data5,
output wire [DATA6_BITS-1:0] m_data6,
output wire [DATA7_BITS-1:0] m_data7,
output wire [DATA8_BITS-1:0] m_data8,
output wire [DATA9_BITS-1:0] m_data9,
output wire m_valid,
input wire m_ready
);
// pack/unpack
localparam PACK_WIDTH = DATA0_WIDTH
+ DATA1_WIDTH
+ DATA2_WIDTH
+ DATA3_WIDTH
+ DATA4_WIDTH
+ DATA5_WIDTH
+ DATA6_WIDTH
+ DATA7_WIDTH
+ DATA8_WIDTH
+ DATA9_WIDTH;
localparam PACK_BITS = PACK_WIDTH > 0 ? PACK_WIDTH : 1;
wire [PACK_BITS-1:0] m_pack;
wire [PACK_BITS-1:0] s_pack;
jelly2_func_pack
#(
.N (1),
.W0 (DATA0_WIDTH),
.W1 (DATA1_WIDTH),
.W2 (DATA2_WIDTH),
.W3 (DATA3_WIDTH),
.W4 (DATA4_WIDTH),
.W5 (DATA5_WIDTH),
.W6 (DATA6_WIDTH),
.W7 (DATA7_WIDTH),
.W8 (DATA8_WIDTH),
.W9 (DATA9_WIDTH)
)
i_func_pack
(
.in0 (s_data0),
.in1 (s_data1),
.in2 (s_data2),
.in3 (s_data3),
.in4 (s_data4),
.in5 (s_data5),
.in6 (s_data6),
.in7 (s_data7),
.in8 (s_data8),
.in9 (s_data9),
.out (s_pack)
);
jelly2_func_unpack
#(
.N (1),
.W0 (DATA0_WIDTH),
.W1 (DATA1_WIDTH),
.W2 (DATA2_WIDTH),
.W3 (DATA3_WIDTH),
.W4 (DATA4_WIDTH),
.W5 (DATA5_WIDTH),
.W6 (DATA6_WIDTH),
.W7 (DATA7_WIDTH),
.W8 (DATA8_WIDTH),
.W9 (DATA9_WIDTH)
)
i_func_unpack
(
.in (m_pack),
.out0 (m_data0),
.out1 (m_data1),
.out2 (m_data2),
.out3 (m_data3),
.out4 (m_data4),
.out5 (m_data5),
.out6 (m_data6),
.out7 (m_data7),
.out8 (m_data8),
.out9 (m_data9)
);
// insert ff
jelly_data_ff
#(
.DATA_WIDTH (PACK_BITS),
.INIT_DATA ({PACK_BITS{1'bx}}),
.S_REGS (S_REGS),
.M_REGS (M_REGS)
)
i_data_ff
(
.reset (reset),
.clk (clk),
.cke (cke),
.s_data (s_pack),
.s_valid (s_valid),
.s_ready (s_ready),
.m_data (m_pack),
.m_valid (m_valid),
.m_ready (m_ready)
);
endmodule |
module jelly2_stream_add_syncflag
#(
parameter FIRST_WIDTH = 0,
parameter LAST_WIDTH = 1,
parameter USER_WIDTH = 0,
parameter HAS_FIRST = 1,
parameter HAS_LAST = 1,
parameter S_REGS = 0,
parameter M_REGS = 0,
parameter ASYNC = 0,
parameter FIFO_PTR_WIDTH = 4,
parameter FIFO_DOUT_REGS = 0,
parameter FIFO_RAM_TYPE = "distributed",
parameter FIFO_LOW_DEALY = 1,
parameter FIFO_S_REGS = 0,
parameter FIFO_M_REGS = 0,
// loacal
parameter FIRST_BITS = FIRST_WIDTH > 0 ? FIRST_WIDTH : 1,
parameter LAST_BITS = LAST_WIDTH > 0 ? LAST_WIDTH : 1,
parameter USER_BITS = USER_WIDTH > 0 ? USER_WIDTH : 1,
parameter DEFAULT_FIRST = {FIRST_BITS{1'b0}},
parameter DEFAULT_LAST = {LAST_BITS{1'b0}}
)
(
input wire reset,
input wire clk,
input wire cke,
input wire s_first,
input wire s_last,
input wire [USER_BITS-1:0] s_user,
input wire s_valid,
output wire s_ready,
output wire m_first,
output wire m_last,
output wire [FIRST_BITS-1:0] m_added_first,
output wire [LAST_BITS-1:0] m_added_last,
output wire [USER_BITS-1:0] m_user,
output wire m_valid,
input wire m_ready,
input wire s_add_reset,
input wire s_add_clk,
input wire [FIRST_BITS-1:0] s_add_first,
input wire [LAST_BITS-1:0] s_add_last,
input wire s_add_valid,
output wire s_add_ready
);
// insert FF
wire ff_s_first;
wire ff_s_last;
wire [USER_BITS-1:0] ff_s_user;
wire ff_s_valid;
wire ff_s_ready;
// verilator lint_off PINMISSING
jelly2_data_ff_pack
#(
.DATA0_WIDTH (HAS_FIRST ? 1 : 0),
.DATA1_WIDTH (HAS_LAST ? 1 : 0),
.DATA2_WIDTH (USER_WIDTH),
.S_REGS (S_REGS),
.M_REGS (0)
)
jelly_data_ff_pack_s
(
.reset (reset),
.clk (clk),
.cke (cke),
.s_data0 (s_first),
.s_data1 (s_last),
.s_data2 (s_user),
.s_valid (s_valid),
.s_ready (s_ready),
.m_data0 (ff_s_first),
.m_data1 (ff_s_last),
.m_data2 (ff_s_user),
.m_valid (ff_s_valid),
.m_ready (ff_s_ready)
);
// verilator lint_on PINMISSING
// insert FF
wire ff_m_first;
wire ff_m_last;
wire [FIRST_BITS-1:0] ff_m_added_first;
wire [LAST_BITS-1:0] ff_m_added_last;
wire [USER_BITS-1:0] ff_m_user;
wire ff_m_valid;
wire ff_m_ready;
// verilator lint_off PINMISSING
jelly2_data_ff_pack
#(
.DATA0_WIDTH (HAS_FIRST ? 1 : 0),
.DATA1_WIDTH (HAS_LAST ? 1 : 0),
.DATA2_WIDTH (FIRST_WIDTH),
.DATA3_WIDTH (LAST_WIDTH),
.DATA4_WIDTH (USER_WIDTH),
.S_REGS (0),
.M_REGS (M_REGS)
)
i_data_ff_pack_m
(
.reset (reset),
.clk (clk),
.cke (cke),
.s_data0 (ff_m_first),
.s_data1 (ff_m_last),
.s_data2 (ff_m_added_first),
.s_data3 (ff_m_added_last),
.s_data4 (ff_m_user),
.s_valid (ff_m_valid),
.s_ready (ff_m_ready),
.m_data0 (m_first),
.m_data1 (m_last),
.m_data2 (m_added_first),
.m_data3 (m_added_last),
.m_data4 (m_user),
.m_valid (m_valid),
.m_ready (m_ready)
);
// verilator lint_on PINMISSING
// FIFO
wire [FIRST_BITS-1:0] fifo_first;
wire [LAST_BITS-1:0] fifo_last;
wire fifo_valid;
wire fifo_ready;
// verilator lint_off PINMISSING
jelly2_fifo_pack
#(
.ASYNC (ASYNC),
.DATA0_WIDTH (FIRST_WIDTH),
.DATA1_WIDTH (LAST_WIDTH),
.PTR_WIDTH (FIFO_PTR_WIDTH),
.DOUT_REGS (FIFO_DOUT_REGS),
.RAM_TYPE (FIFO_RAM_TYPE ),
.LOW_DEALY (FIFO_LOW_DEALY),
.S_REGS (FIFO_S_REGS),
.M_REGS (FIFO_M_REGS)
)
i_fifo_pack
(
.s_reset (s_add_reset),
.s_clk (s_add_clk),
.s_cke (1'b1),
.s_data0 (s_add_first),
.s_data1 (s_add_last),
.s_valid (s_add_valid),
.s_ready (s_add_ready),
.m_reset (reset),
.m_clk (clk),
.m_cke (1'b1),
.m_data0 (fifo_first),
.m_data1 (fifo_last),
.m_valid (fifo_valid),
.m_ready (fifo_ready & cke)
);
// verilator lint_on PINMISSING
// connection
assign fifo_ready = (ff_m_ready & ff_s_valid & ff_s_last);
assign ff_m_first = HAS_FIRST ? ff_s_first : 1'b0;
assign ff_m_last = HAS_LAST ? ff_s_last : 1'b0;
assign ff_m_added_first = ff_m_first ? fifo_first : DEFAULT_FIRST;
assign ff_m_added_last = ff_m_last ? fifo_last : DEFAULT_LAST;
assign ff_m_user = ff_s_user;
assign ff_m_valid = ff_s_valid && fifo_valid;
assign ff_s_ready = ff_m_ready && fifo_valid;
endmodule |
module jelly2_stream_width_convert_pack
#(
parameter S_NUM = 1,
parameter M_NUM = 1,
parameter UNIT0_WIDTH = 32,
parameter UNIT1_WIDTH = 0,
parameter UNIT2_WIDTH = 0,
parameter UNIT3_WIDTH = 0,
parameter UNIT4_WIDTH = 0,
parameter UNIT5_WIDTH = 0,
parameter UNIT6_WIDTH = 0,
parameter UNIT7_WIDTH = 0,
parameter UNIT8_WIDTH = 0,
parameter UNIT9_WIDTH = 0,
parameter S_DATA0_WIDTH = S_NUM * UNIT0_WIDTH,
parameter S_DATA1_WIDTH = S_NUM * UNIT1_WIDTH,
parameter S_DATA2_WIDTH = S_NUM * UNIT2_WIDTH,
parameter S_DATA3_WIDTH = S_NUM * UNIT3_WIDTH,
parameter S_DATA4_WIDTH = S_NUM * UNIT4_WIDTH,
parameter S_DATA5_WIDTH = S_NUM * UNIT5_WIDTH,
parameter S_DATA6_WIDTH = S_NUM * UNIT6_WIDTH,
parameter S_DATA7_WIDTH = S_NUM * UNIT7_WIDTH,
parameter S_DATA8_WIDTH = S_NUM * UNIT8_WIDTH,
parameter S_DATA9_WIDTH = S_NUM * UNIT9_WIDTH,
parameter M_DATA0_WIDTH = M_NUM * UNIT0_WIDTH,
parameter M_DATA1_WIDTH = M_NUM * UNIT1_WIDTH,
parameter M_DATA2_WIDTH = M_NUM * UNIT2_WIDTH,
parameter M_DATA3_WIDTH = M_NUM * UNIT3_WIDTH,
parameter M_DATA4_WIDTH = M_NUM * UNIT4_WIDTH,
parameter M_DATA5_WIDTH = M_NUM * UNIT5_WIDTH,
parameter M_DATA6_WIDTH = M_NUM * UNIT6_WIDTH,
parameter M_DATA7_WIDTH = M_NUM * UNIT7_WIDTH,
parameter M_DATA8_WIDTH = M_NUM * UNIT8_WIDTH,
parameter M_DATA9_WIDTH = M_NUM * UNIT9_WIDTH,
parameter HAS_FIRST = 0, // first を備える
parameter HAS_LAST = 0, // last を備える
parameter AUTO_FIRST = (HAS_LAST & !HAS_FIRST), // last の次を自動的に first とする
parameter HAS_ALIGN_S = 1, // slave 側のアライメントを指定する
parameter HAS_ALIGN_M = 1, // master 側のアライメントを指定する
parameter FIRST_OVERWRITE = 0, // first時前方に残変換があれば吐き出さずに上書き
parameter FIRST_FORCE_LAST = 0, // first時前方に残変換があれば強制的にlastを付与(残が無い場合はlastはつかない)
parameter ALIGN_S_WIDTH = S_NUM <= 2 ? 1 :
S_NUM <= 4 ? 2 :
S_NUM <= 8 ? 3 :
S_NUM <= 16 ? 4 :
S_NUM <= 32 ? 5 :
S_NUM <= 64 ? 6 :
S_NUM <= 128 ? 7 :
S_NUM <= 256 ? 8 :
S_NUM <= 512 ? 9 : 10,
parameter ALIGN_M_WIDTH = M_NUM <= 2 ? 1 :
M_NUM <= 4 ? 2 :
M_NUM <= 8 ? 3 :
M_NUM <= 16 ? 4 :
M_NUM <= 32 ? 5 :
M_NUM <= 64 ? 6 :
M_NUM <= 128 ? 7 :
M_NUM <= 256 ? 8 :
M_NUM <= 512 ? 9 : 10,
parameter USER_F_WIDTH = 0,
parameter USER_L_WIDTH = 0,
parameter S_REGS = (S_NUM != M_NUM),
// local
parameter UNIT0_BITS = UNIT0_WIDTH > 0 ? UNIT0_WIDTH : 1,
parameter UNIT1_BITS = UNIT1_WIDTH > 0 ? UNIT1_WIDTH : 1,
parameter UNIT2_BITS = UNIT2_WIDTH > 0 ? UNIT2_WIDTH : 1,
parameter UNIT3_BITS = UNIT3_WIDTH > 0 ? UNIT3_WIDTH : 1,
parameter UNIT4_BITS = UNIT4_WIDTH > 0 ? UNIT4_WIDTH : 1,
parameter UNIT5_BITS = UNIT5_WIDTH > 0 ? UNIT5_WIDTH : 1,
parameter UNIT6_BITS = UNIT6_WIDTH > 0 ? UNIT6_WIDTH : 1,
parameter UNIT7_BITS = UNIT7_WIDTH > 0 ? UNIT7_WIDTH : 1,
parameter UNIT8_BITS = UNIT8_WIDTH > 0 ? UNIT8_WIDTH : 1,
parameter UNIT9_BITS = UNIT9_WIDTH > 0 ? UNIT9_WIDTH : 1,
parameter S_DATA0_BITS = S_DATA0_WIDTH > 0 ? S_DATA0_WIDTH : 1,
parameter S_DATA1_BITS = S_DATA1_WIDTH > 0 ? S_DATA1_WIDTH : 1,
parameter S_DATA2_BITS = S_DATA2_WIDTH > 0 ? S_DATA2_WIDTH : 1,
parameter S_DATA3_BITS = S_DATA3_WIDTH > 0 ? S_DATA3_WIDTH : 1,
parameter S_DATA4_BITS = S_DATA4_WIDTH > 0 ? S_DATA4_WIDTH : 1,
parameter S_DATA5_BITS = S_DATA5_WIDTH > 0 ? S_DATA5_WIDTH : 1,
parameter S_DATA6_BITS = S_DATA6_WIDTH > 0 ? S_DATA6_WIDTH : 1,
parameter S_DATA7_BITS = S_DATA7_WIDTH > 0 ? S_DATA7_WIDTH : 1,
parameter S_DATA8_BITS = S_DATA8_WIDTH > 0 ? S_DATA8_WIDTH : 1,
parameter S_DATA9_BITS = S_DATA9_WIDTH > 0 ? S_DATA9_WIDTH : 1,
parameter M_DATA0_BITS = M_DATA0_WIDTH > 0 ? M_DATA0_WIDTH : 1,
parameter M_DATA1_BITS = M_DATA1_WIDTH > 0 ? M_DATA1_WIDTH : 1,
parameter M_DATA2_BITS = M_DATA2_WIDTH > 0 ? M_DATA2_WIDTH : 1,
parameter M_DATA3_BITS = M_DATA3_WIDTH > 0 ? M_DATA3_WIDTH : 1,
parameter M_DATA4_BITS = M_DATA4_WIDTH > 0 ? M_DATA4_WIDTH : 1,
parameter M_DATA5_BITS = M_DATA5_WIDTH > 0 ? M_DATA5_WIDTH : 1,
parameter M_DATA6_BITS = M_DATA6_WIDTH > 0 ? M_DATA6_WIDTH : 1,
parameter M_DATA7_BITS = M_DATA7_WIDTH > 0 ? M_DATA7_WIDTH : 1,
parameter M_DATA8_BITS = M_DATA8_WIDTH > 0 ? M_DATA8_WIDTH : 1,
parameter M_DATA9_BITS = M_DATA9_WIDTH > 0 ? M_DATA9_WIDTH : 1,
parameter USER_F_BITS = USER_F_WIDTH > 0 ? USER_F_WIDTH : 1,
parameter USER_L_BITS = USER_L_WIDTH > 0 ? USER_L_WIDTH : 1
)
(
input wire reset,
input wire clk,
input wire cke,
input wire endian,
input wire [UNIT0_BITS-1:0] padding0,
input wire [UNIT1_BITS-1:0] padding1,
input wire [UNIT2_BITS-1:0] padding2,
input wire [UNIT3_BITS-1:0] padding3,
input wire [UNIT4_BITS-1:0] padding4,
input wire [UNIT5_BITS-1:0] padding5,
input wire [UNIT6_BITS-1:0] padding6,
input wire [UNIT7_BITS-1:0] padding7,
input wire [UNIT8_BITS-1:0] padding8,
input wire [UNIT9_BITS-1:0] padding9,
input wire [ALIGN_S_WIDTH-1:0] s_align_s,
input wire [ALIGN_M_WIDTH-1:0] s_align_m,
input wire s_first,
input wire s_last,
input wire [S_DATA0_BITS-1:0] s_data0,
input wire [S_DATA1_BITS-1:0] s_data1,
input wire [S_DATA2_BITS-1:0] s_data2,
input wire [S_DATA3_BITS-1:0] s_data3,
input wire [S_DATA4_BITS-1:0] s_data4,
input wire [S_DATA5_BITS-1:0] s_data5,
input wire [S_DATA6_BITS-1:0] s_data6,
input wire [S_DATA7_BITS-1:0] s_data7,
input wire [S_DATA8_BITS-1:0] s_data8,
input wire [S_DATA9_BITS-1:0] s_data9,
input wire [USER_F_BITS-1:0] s_user_f, // アライメント先頭前提で伝搬するユーザーデータ
input wire [USER_L_BITS-1:0] s_user_l, // アライメント末尾前提で伝搬するユーザーデータ
input wire s_valid,
output wire s_ready,
output wire m_first,
output wire m_last,
output wire [M_DATA0_BITS-1:0] m_data0,
output wire [M_DATA1_BITS-1:0] m_data1,
output wire [M_DATA2_BITS-1:0] m_data2,
output wire [M_DATA3_BITS-1:0] m_data3,
output wire [M_DATA4_BITS-1:0] m_data4,
output wire [M_DATA5_BITS-1:0] m_data5,
output wire [M_DATA6_BITS-1:0] m_data6,
output wire [M_DATA7_BITS-1:0] m_data7,
output wire [M_DATA8_BITS-1:0] m_data8,
output wire [M_DATA9_BITS-1:0] m_data9,
output wire [USER_F_BITS-1:0] m_user_f,
output wire [USER_L_BITS-1:0] m_user_l,
output wire m_valid,
input wire m_ready
);
// pack/unpack
localparam PACK_UNIT = UNIT0_WIDTH
+ UNIT1_WIDTH
+ UNIT2_WIDTH
+ UNIT3_WIDTH
+ UNIT4_WIDTH
+ UNIT5_WIDTH
+ UNIT6_WIDTH
+ UNIT7_WIDTH
+ UNIT8_WIDTH
+ UNIT9_WIDTH;
localparam S_PACK_WIDTH = S_NUM * PACK_UNIT;
localparam M_PACK_WIDTH = M_NUM * PACK_UNIT;
localparam S_PACK_BITS = S_PACK_WIDTH > 0 ? S_PACK_WIDTH : 1;
localparam M_PACK_BITS = M_PACK_WIDTH > 0 ? M_PACK_WIDTH : 1;
wire [M_PACK_BITS-1:0] m_pack;
wire [S_PACK_BITS-1:0] s_pack;
jelly2_func_pack
#(
.N (S_NUM),
.W0 (UNIT0_WIDTH),
.W1 (UNIT1_WIDTH),
.W2 (UNIT2_WIDTH),
.W3 (UNIT3_WIDTH),
.W4 (UNIT4_WIDTH),
.W5 (UNIT5_WIDTH),
.W6 (UNIT6_WIDTH),
.W7 (UNIT7_WIDTH),
.W8 (UNIT8_WIDTH),
.W9 (UNIT9_WIDTH)
)
i_func_pack
(
.in0 (s_data0),
.in1 (s_data1),
.in2 (s_data2),
.in3 (s_data3),
.in4 (s_data4),
.in5 (s_data5),
.in6 (s_data6),
.in7 (s_data7),
.in8 (s_data8),
.in9 (s_data9),
.out (s_pack)
);
jelly2_func_unpack
#(
.N (M_NUM),
.W0 (UNIT0_WIDTH),
.W1 (UNIT1_WIDTH),
.W2 (UNIT2_WIDTH),
.W3 (UNIT3_WIDTH),
.W4 (UNIT4_WIDTH),
.W5 (UNIT5_WIDTH),
.W6 (UNIT6_WIDTH),
.W7 (UNIT7_WIDTH),
.W8 (UNIT8_WIDTH),
.W9 (UNIT9_WIDTH)
)
i_func_unpack
(
.in (m_pack),
.out0 (m_data0),
.out1 (m_data1),
.out2 (m_data2),
.out3 (m_data3),
.out4 (m_data4),
.out5 (m_data5),
.out6 (m_data6),
.out7 (m_data7),
.out8 (m_data8),
.out9 (m_data9)
);
localparam PADDING_WIDTH = PACK_UNIT;
localparam PADDING_BITS = PADDING_WIDTH > 0 ? PADDING_WIDTH : 1;
wire [PADDING_BITS-1:0] padding_pack;
jelly2_func_pack
#(
.N (1),
.W0 (UNIT0_WIDTH),
.W1 (UNIT1_WIDTH),
.W2 (UNIT2_WIDTH),
.W3 (UNIT3_WIDTH),
.W4 (UNIT4_WIDTH),
.W5 (UNIT5_WIDTH),
.W6 (UNIT6_WIDTH),
.W7 (UNIT7_WIDTH),
.W8 (UNIT8_WIDTH),
.W9 (UNIT9_WIDTH)
)
i_func_pack_padding
(
.in0 (padding0),
.in1 (padding1),
.in2 (padding2),
.in3 (padding3),
.in4 (padding4),
.in5 (padding5),
.in6 (padding6),
.in7 (padding7),
.in8 (padding8),
.in9 (padding9),
.out (padding_pack)
);
// packing
jelly2_stream_width_convert
#(
.UNIT_WIDTH (PACK_UNIT),
.S_NUM (S_NUM),
.M_NUM (M_NUM),
.HAS_FIRST (HAS_FIRST),
.HAS_LAST (HAS_LAST),
.AUTO_FIRST (AUTO_FIRST),
.HAS_ALIGN_S (HAS_ALIGN_S),
.HAS_ALIGN_M (HAS_ALIGN_M),
.FIRST_OVERWRITE (FIRST_OVERWRITE),
.FIRST_FORCE_LAST (FIRST_FORCE_LAST),
.ALIGN_S_WIDTH (ALIGN_S_WIDTH),
.ALIGN_M_WIDTH (ALIGN_M_WIDTH),
.USER_F_WIDTH (USER_F_WIDTH),
.USER_L_WIDTH (USER_L_WIDTH),
.S_REGS (S_REGS)
)
i_stream_width_convert
(
.reset (reset),
.clk (clk),
.cke (cke),
.endian (endian),
.padding (padding_pack),
.s_align_s (s_align_s),
.s_align_m (s_align_m),
.s_first (s_first),
.s_last (s_last),
.s_data (s_pack),
.s_strb ('1),
.s_keep ('1),
.s_user_f (s_user_f),
.s_user_l (s_user_l),
.s_valid (s_valid),
.s_ready (s_ready),
.m_first (m_first),
.m_last (m_last),
.m_data (m_pack),
.m_strb (),
.m_keep (),
.m_user_f (m_user_f),
.m_user_l (m_user_l),
.m_valid (m_valid),
.m_ready (m_ready)
);
endmodule |
module VerilatorWrapper(
input IP_CLK,
input IP_ARESET_N,
input [31:0] SAXI0_ARADDR,
input [2:0] SAXI0_ARPROT,
input [3:0] SAXI0_ARCACHE,
input [7:0] SAXI0_ARLEN,
input [3:0] SAXI0_ARQOS,
input [0:0] SAXI0_ARLOCK,
input [5:0] SAXI0_ARUSER,
input [3:0] SAXI0_ARREGION,
input [11:0] SAXI0_ARID,
input [2:0] SAXI0_ARSIZE,
input [1:0] SAXI0_ARBURST,
input SAXI0_ARVALID,
output SAXI0_ARREADY,
output [1:0] SAXI0_RRESP,
output [0:0] SAXI0_RLAST,
output [31:0] SAXI0_RDATA,
output [5:0] SAXI0_RUSER,
output [11:0] SAXI0_RID,
output SAXI0_RVALID,
input SAXI0_RREADY,
input [1:0] SAXI0_AWBURST,
input [0:0] SAXI0_AWLOCK,
input [3:0] SAXI0_AWCACHE,
input [2:0] SAXI0_AWSIZE,
input [3:0] SAXI0_AWQOS,
input [31:0] SAXI0_AWADDR,
input [7:0] SAXI0_AWLEN,
input [5:0] SAXI0_AWUSER,
input [11:0] SAXI0_AWID,
input [2:0] SAXI0_AWPROT,
input [3:0] SAXI0_AWREGION,
output SAXI0_AWREADY,
input SAXI0_AWVALID,
input [31:0] SAXI0_WDATA,
input [3:0] SAXI0_WSTRB,
input [0:0] SAXI0_WLAST,
input [5:0] SAXI0_WUSER,
output SAXI0_WREADY,
input SAXI0_WVALID,
output [11:0] SAXI0_BID,
output [5:0] SAXI0_BUSER,
output [1:0] SAXI0_BRESP,
input SAXI0_BREADY,
output SAXI0_BVALID,
output [31:0] MAXI0_ARADDR,
output [2:0] MAXI0_ARPROT,
output [3:0] MAXI0_ARCACHE,
output [7:0] MAXI0_ARLEN,
output [3:0] MAXI0_ARQOS,
output [0:0] MAXI0_ARLOCK,
output [5:0] MAXI0_ARUSER,
output [3:0] MAXI0_ARREGION,
output [11:0] MAXI0_ARID,
output [2:0] MAXI0_ARSIZE,
output [1:0] MAXI0_ARBURST,
output MAXI0_ARVALID,
input MAXI0_ARREADY,
input [1:0] MAXI0_RRESP,
input [0:0] MAXI0_RLAST,
input [63:0] MAXI0_RDATA,
input [5:0] MAXI0_RUSER,
input [11:0] MAXI0_RID,
input MAXI0_RVALID,
output MAXI0_RREADY,
output [1:0] MAXI0_AWBURST,
output [0:0] MAXI0_AWLOCK,
output [3:0] MAXI0_AWCACHE,
output [2:0] MAXI0_AWSIZE,
output [3:0] MAXI0_AWQOS,
output [31:0] MAXI0_AWADDR,
output [7:0] MAXI0_AWLEN,
output [5:0] MAXI0_AWUSER,
output [11:0] MAXI0_AWID,
output [2:0] MAXI0_AWPROT,
output [3:0] MAXI0_AWREGION,
input MAXI0_AWREADY,
output MAXI0_AWVALID,
output [63:0] MAXI0_WDATA,
output [7:0] MAXI0_WSTRB,
output [0:0] MAXI0_WLAST,
output [5:0] MAXI0_WUSER,
input MAXI0_WREADY,
output MAXI0_WVALID,
input [11:0] MAXI0_BID,
input [5:0] MAXI0_BUSER,
input [1:0] MAXI0_BRESP,
output MAXI0_BREADY,
input MAXI0_BVALID,
output [31:0] MAXI1_ARADDR,
output [2:0] MAXI1_ARPROT,
output [3:0] MAXI1_ARCACHE,
output [7:0] MAXI1_ARLEN,
output [3:0] MAXI1_ARQOS,
output [0:0] MAXI1_ARLOCK,
output [5:0] MAXI1_ARUSER,
output [3:0] MAXI1_ARREGION,
output [11:0] MAXI1_ARID,
output [2:0] MAXI1_ARSIZE,
output [1:0] MAXI1_ARBURST,
output MAXI1_ARVALID,
input MAXI1_ARREADY,
input [1:0] MAXI1_RRESP,
input [0:0] MAXI1_RLAST,
input [63:0] MAXI1_RDATA,
input [5:0] MAXI1_RUSER,
input [11:0] MAXI1_RID,
input MAXI1_RVALID,
output MAXI1_RREADY,
output [1:0] MAXI1_AWBURST,
output [0:0] MAXI1_AWLOCK,
output [3:0] MAXI1_AWCACHE,
output [2:0] MAXI1_AWSIZE,
output [3:0] MAXI1_AWQOS,
output [31:0] MAXI1_AWADDR,
output [7:0] MAXI1_AWLEN,
output [5:0] MAXI1_AWUSER,
output [11:0] MAXI1_AWID,
output [2:0] MAXI1_AWPROT,
output [3:0] MAXI1_AWREGION,
input MAXI1_AWREADY,
output MAXI1_AWVALID,
output [63:0] MAXI1_WDATA,
output [7:0] MAXI1_WSTRB,
output [0:0] MAXI1_WLAST,
output [5:0] MAXI1_WUSER,
input MAXI1_WREADY,
output MAXI1_WVALID,
input [11:0] MAXI1_BID,
input [5:0] MAXI1_BUSER,
input [1:0] MAXI1_BRESP,
output MAXI1_BREADY,
input MAXI1_BVALID);
wire [159:0] ZynqNOC_write_input; // write issue
assign MAXI0_WUSER = ZynqNOC_write_input[158:153];
assign MAXI0_AWQOS = ZynqNOC_write_input[77:74];
assign MAXI0_WLAST = ZynqNOC_write_input[152:152];
assign MAXI0_AWCACHE = ZynqNOC_write_input[60:57];
assign MAXI0_AWLOCK = ZynqNOC_write_input[78:78];
assign MAXI0_AWUSER = ZynqNOC_write_input[73:68];
assign MAXI0_WDATA = ZynqNOC_write_input[143:80];
assign MAXI0_WSTRB = ZynqNOC_write_input[151:144];
assign MAXI0_AWID = ZynqNOC_write_input[56:45];
assign MAXI0_AWREGION = ZynqNOC_write_input[67:64];
assign MAXI0_AWSIZE = ZynqNOC_write_input[44:42];
assign MAXI0_AWADDR = ZynqNOC_write_input[31:0];
assign MAXI0_AWVALID = ZynqNOC_write_input[79];
assign MAXI0_AWLEN = ZynqNOC_write_input[39:32];
assign MAXI0_AWBURST = ZynqNOC_write_input[41:40];
assign MAXI0_WVALID = ZynqNOC_write_input[159];
assign MAXI0_AWPROT = ZynqNOC_write_input[63:61];
wire [20:0] ZynqNOC_write_output; // write response
assign ZynqNOC_write_output = {MAXI0_BVALID,MAXI0_BUSER,MAXI0_BID,MAXI0_BRESP};
wire ZynqNOC_write_ready_downstream;
assign MAXI0_BREADY = ZynqNOC_write_ready_downstream;
wire [1:0] ZynqNOC_write_ready;
assign ZynqNOC_write_ready = {MAXI0_WREADY,MAXI0_AWREADY};
////////////////
wire regs_read_ready_downstream;
assign regs_read_ready_downstream = SAXI0_RREADY;
wire regs_read_ready;
assign SAXI0_ARREADY = regs_read_ready;
wire [79:0] regs_read_input; // issue read to slave
assign regs_read_input = {SAXI0_ARVALID,SAXI0_ARQOS,SAXI0_ARUSER,SAXI0_ARREGION,SAXI0_ARLOCK,SAXI0_ARCACHE,SAXI0_ARPROT,SAXI0_ARID,SAXI0_ARBURST,SAXI0_ARSIZE,SAXI0_ARLEN,SAXI0_ARADDR};
wire [53:0] regs_read_output; // slave read response
assign SAXI0_RVALID = regs_read_output[53];
assign SAXI0_RLAST = regs_read_output[32:32];
assign SAXI0_RID = regs_read_output[46:35];
assign SAXI0_RDATA = regs_read_output[31:0];
assign SAXI0_RUSER = regs_read_output[52:47];
assign SAXI0_RRESP = regs_read_output[34:33];
wire regs_write_ready_downstream;
assign regs_write_ready_downstream = SAXI0_BREADY;
wire [1:0] regs_write_ready;
assign SAXI0_AWREADY = regs_write_ready[0];
assign SAXI0_WREADY = regs_write_ready[1];
wire [123:0] regs_write_input; // issue write to slave
assign regs_write_input[79:0] = {SAXI0_AWVALID,SAXI0_AWLOCK,SAXI0_AWQOS,SAXI0_AWUSER,SAXI0_AWREGION,SAXI0_AWPROT,SAXI0_AWCACHE,SAXI0_AWID,SAXI0_AWSIZE,SAXI0_AWBURST,SAXI0_AWLEN,SAXI0_AWADDR};
assign regs_write_input[123:80] = {SAXI0_WVALID,SAXI0_WUSER,SAXI0_WLAST,SAXI0_WSTRB,SAXI0_WDATA};
wire [20:0] regs_write_output; // return write result from slave
assign SAXI0_BVALID = regs_write_output[20];
assign SAXI0_BID = regs_write_output[13:2];
assign SAXI0_BUSER = regs_write_output[19:14];
assign SAXI0_BRESP = regs_write_output[1:0];
/////////////////////
wire ZynqNOC_read_ready_downstream;
assign MAXI0_RREADY = ZynqNOC_read_ready_downstream;
wire ZynqNOC_read_ready;
assign ZynqNOC_read_ready = MAXI0_ARREADY;
wire [79:0] ZynqNOC_read_input; // read request
assign MAXI0_ARADDR = ZynqNOC_read_input[31:0];
assign MAXI0_ARPROT = ZynqNOC_read_input[59:57];
assign MAXI0_ARCACHE = ZynqNOC_read_input[63:60];
assign MAXI0_ARBURST = ZynqNOC_read_input[44:43];
assign MAXI0_ARLEN = ZynqNOC_read_input[39:32];
assign MAXI0_ARSIZE = ZynqNOC_read_input[42:40];
assign MAXI0_ARLOCK = ZynqNOC_read_input[64:64];
assign MAXI0_ARVALID = ZynqNOC_read_input[79];
assign MAXI0_ARREGION = ZynqNOC_read_input[68:65];
assign MAXI0_ARID = ZynqNOC_read_input[56:45];
assign MAXI0_ARQOS = ZynqNOC_read_input[78:75];
assign MAXI0_ARUSER = ZynqNOC_read_input[74:69];
wire [85:0] ZynqNOC_read_output; // read response
assign ZynqNOC_read_output = {MAXI0_RVALID,MAXI0_RUSER,MAXI0_RID,MAXI0_RRESP,MAXI0_RLAST,MAXI0_RDATA};
wire ZynqNOC_read1_ready_downstream;
assign MAXI1_RREADY = ZynqNOC_read1_ready_downstream;
wire ZynqNOC_read1_ready;
assign ZynqNOC_read1_ready = MAXI1_ARREADY;
wire [79:0] ZynqNOC_read1_input; // read request
assign MAXI1_ARADDR = ZynqNOC_read1_input[31:0];
assign MAXI1_ARPROT = ZynqNOC_read1_input[59:57];
assign MAXI1_ARCACHE = ZynqNOC_read1_input[63:60];
assign MAXI1_ARBURST = ZynqNOC_read1_input[44:43];
assign MAXI1_ARLEN = ZynqNOC_read1_input[39:32];
assign MAXI1_ARSIZE = ZynqNOC_read1_input[42:40];
assign MAXI1_ARLOCK = ZynqNOC_read1_input[64:64];
assign MAXI1_ARVALID = ZynqNOC_read1_input[79];
assign MAXI1_ARREGION = ZynqNOC_read1_input[68:65];
assign MAXI1_ARID = ZynqNOC_read1_input[56:45];
assign MAXI1_ARQOS = ZynqNOC_read1_input[78:75];
assign MAXI1_ARUSER = ZynqNOC_read1_input[74:69];
wire [85:0] ZynqNOC_read1_output; // read response
assign ZynqNOC_read1_output = {MAXI1_RVALID,MAXI1_RUSER,MAXI1_RID,MAXI1_RRESP,MAXI1_RLAST,MAXI1_RDATA};
Top top(.CLK(IP_CLK), .reset(~IP_ARESET_N), .*);
endmodule |
module HPS(
output wire [1 - 1 : 0 ] h2f_rst_n
,output wire [1 - 1 : 0 ] h2f_user0_clk
);
cyclonev_hps_interface_clocks_resets clocks_resets(
.f2h_pending_rst_ack({
1'b1 // 0:0
})
,.f2h_warm_rst_req_n({
1'b1 // 0:0
})
,.f2h_dbg_rst_req_n({
1'b1 // 0:0
})
,.h2f_rst_n({
h2f_rst_n[0:0] // 0:0
})
,.f2h_cold_rst_req_n({
1'b1 // 0:0
})
,.h2f_user0_clk({
h2f_user0_clk[0:0] // 0:0
})
);
cyclonev_hps_interface_dbg_apb debug_apb(
.DBG_APB_DISABLE({
1'b0 // 0:0
})
,.P_CLK_EN({
1'b0 // 0:0
})
);
cyclonev_hps_interface_tpiu_trace tpiu(
.traceclk_ctl({
1'b1 // 0:0
})
);
cyclonev_hps_interface_boot_from_fpga boot_from_fpga(
.boot_from_fpga_ready({
1'b0 // 0:0
})
,.boot_from_fpga_on_failure({
1'b0 // 0:0
})
,.bsel_en({
1'b0 // 0:0
})
,.csel_en({
1'b0 // 0:0
})
,.csel({
2'b01 // 1:0
})
,.bsel({
3'b001 // 2:0
})
);
cyclonev_hps_interface_fpga2hps fpga2hps(
.port_size_config({
2'b11 // 1:0
})
);
cyclonev_hps_interface_hps2fpga hps2fpga(
.port_size_config({
2'b11 // 1:0
})
);
cyclonev_hps_interface_fpga2sdram f2sdram(
.cfg_cport_rfifo_map({
18'b000000000000000000 // 17:0
})
,.cfg_axi_mm_select({
6'b000000 // 5:0
})
,.cfg_wfifo_cport_map({
16'b0000000000000000 // 15:0
})
,.cfg_cport_type({
12'b000000000000 // 11:0
})
,.cfg_rfifo_cport_map({
16'b0000000000000000 // 15:0
})
,.cfg_port_width({
12'b000000000000 // 11:0
})
,.cfg_cport_wfifo_map({
18'b000000000000000000 // 17:0
})
);
endmodule |
module lms_ctr_mm_interconnect_0_router_007_default_decode
#(
parameter DEFAULT_CHANNEL = 0,
DEFAULT_WR_CHANNEL = -1,
DEFAULT_RD_CHANNEL = -1,
DEFAULT_DESTID = 0
)
(output [89 - 86 : 0] default_destination_id,
output [15-1 : 0] default_wr_channel,
output [15-1 : 0] default_rd_channel,
output [15-1 : 0] default_src_channel
);
assign default_destination_id =
DEFAULT_DESTID[89 - 86 : 0];
generate
if (DEFAULT_CHANNEL == -1) begin : no_default_channel_assignment
assign default_src_channel = '0;
end
else begin : default_channel_assignment
assign default_src_channel = 15'b1 << DEFAULT_CHANNEL;
end
endgenerate
generate
if (DEFAULT_RD_CHANNEL == -1) begin : no_default_rw_channel_assignment
assign default_wr_channel = '0;
assign default_rd_channel = '0;
end
else begin : default_rw_channel_assignment
assign default_wr_channel = 15'b1 << DEFAULT_WR_CHANNEL;
assign default_rd_channel = 15'b1 << DEFAULT_RD_CHANNEL;
end
endgenerate
endmodule |
module lms_ctr_mm_interconnect_0_router_007
(
// -------------------
// Clock & Reset
// -------------------
input clk,
input reset,
// -------------------
// Command Sink (Input)
// -------------------
input sink_valid,
input [103-1 : 0] sink_data,
input sink_startofpacket,
input sink_endofpacket,
output sink_ready,
// -------------------
// Command Source (Output)
// -------------------
output src_valid,
output reg [103-1 : 0] src_data,
output reg [15-1 : 0] src_channel,
output src_startofpacket,
output src_endofpacket,
input src_ready
);
// -------------------------------------------------------
// Local parameters and variables
// -------------------------------------------------------
localparam PKT_ADDR_H = 57;
localparam PKT_ADDR_L = 36;
localparam PKT_DEST_ID_H = 89;
localparam PKT_DEST_ID_L = 86;
localparam PKT_PROTECTION_H = 93;
localparam PKT_PROTECTION_L = 91;
localparam ST_DATA_W = 103;
localparam ST_CHANNEL_W = 15;
localparam DECODER_TYPE = 1;
localparam PKT_TRANS_WRITE = 60;
localparam PKT_TRANS_READ = 61;
localparam PKT_ADDR_W = PKT_ADDR_H-PKT_ADDR_L + 1;
localparam PKT_DEST_ID_W = PKT_DEST_ID_H-PKT_DEST_ID_L + 1;
// -------------------------------------------------------
// Figure out the number of bits to mask off for each slave span
// during address decoding
// -------------------------------------------------------
// -------------------------------------------------------
// Work out which address bits are significant based on the
// address range of the slaves. If the required width is too
// large or too small, we use the address field width instead.
// -------------------------------------------------------
localparam ADDR_RANGE = 64'h0;
localparam RANGE_ADDR_WIDTH = log2ceil(ADDR_RANGE);
localparam OPTIMIZED_ADDR_H = (RANGE_ADDR_WIDTH > PKT_ADDR_W) ||
(RANGE_ADDR_WIDTH == 0) ?
PKT_ADDR_H :
PKT_ADDR_L + RANGE_ADDR_WIDTH - 1;
localparam RG = RANGE_ADDR_WIDTH;
localparam REAL_ADDRESS_RANGE = OPTIMIZED_ADDR_H - PKT_ADDR_L;
reg [PKT_DEST_ID_W-1 : 0] destid;
// -------------------------------------------------------
// Pass almost everything through, untouched
// -------------------------------------------------------
assign sink_ready = src_ready;
assign src_valid = sink_valid;
assign src_startofpacket = sink_startofpacket;
assign src_endofpacket = sink_endofpacket;
wire [15-1 : 0] default_src_channel;
// -------------------------------------------------------
// Write and read transaction signals
// -------------------------------------------------------
wire read_transaction;
assign read_transaction = sink_data[PKT_TRANS_READ];
lms_ctr_mm_interconnect_0_router_007_default_decode the_default_decode(
.default_destination_id (),
.default_wr_channel (),
.default_rd_channel (),
.default_src_channel (default_src_channel)
);
always @* begin
src_data = sink_data;
src_channel = default_src_channel;
// --------------------------------------------------
// DestinationID Decoder
// Sets the channel based on the destination ID.
// --------------------------------------------------
destid = sink_data[PKT_DEST_ID_H : PKT_DEST_ID_L];
if (destid == 0 ) begin
src_channel = 15'b01;
end
if (destid == 1 && read_transaction) begin
src_channel = 15'b10;
end
end
// --------------------------------------------------
// Ceil(log2()) function
// --------------------------------------------------
function integer log2ceil;
input reg[65:0] val;
reg [65:0] i;
begin
i = 1;
log2ceil = 0;
while (i < val) begin
log2ceil = log2ceil + 1;
i = i << 1;
end
end
endfunction
endmodule |
module altera_customins_slave_translator
#(
parameter N_WIDTH = 8,
USE_DONE = 1,
NUM_FIXED_CYCLES = 2
)
(
// --------------------------------------
// Slave
// --------------------------------------
input wire [31:0] ci_slave_dataa,
input wire [31:0] ci_slave_datab,
output wire [31:0] ci_slave_result,
input wire [7:0] ci_slave_n,
input wire ci_slave_readra,
input wire ci_slave_readrb,
input wire ci_slave_writerc,
input wire [4:0] ci_slave_a,
input wire [4:0] ci_slave_b,
input wire [4:0] ci_slave_c,
input wire [31:0] ci_slave_ipending,
input wire ci_slave_estatus,
input wire ci_slave_clk,
input wire ci_slave_clken,
input wire ci_slave_reset,
input wire ci_slave_reset_req,
input wire ci_slave_start,
output wire ci_slave_done,
// --------------------------------------
// Master
// --------------------------------------
output wire [31:0] ci_master_dataa,
output wire [31:0] ci_master_datab,
input wire [31:0] ci_master_result,
output wire [N_WIDTH-1:0] ci_master_n,
output wire ci_master_readra,
output wire ci_master_readrb,
output wire ci_master_writerc,
output wire [4:0] ci_master_a,
output wire [4:0] ci_master_b,
output wire [4:0] ci_master_c,
output wire [31:0] ci_master_ipending,
output wire ci_master_estatus,
output wire ci_master_clk,
output wire ci_master_clken,
output wire ci_master_reset,
output wire ci_master_reset_req,
output wire ci_master_start,
input wire ci_master_done
);
localparam COUNTER_WIDTH = $clog2(NUM_FIXED_CYCLES);
wire gen_done;
reg [COUNTER_WIDTH-1:0] count;
reg running;
reg reg_start;
assign ci_slave_result = ci_master_result;
assign ci_master_writerc = ci_slave_writerc;
assign ci_master_dataa = ci_slave_dataa;
assign ci_master_readra = ci_slave_readra;
assign ci_master_datab = ci_slave_datab;
assign ci_master_readrb = ci_slave_readrb;
assign ci_master_b = ci_slave_b;
assign ci_master_c = ci_slave_c;
assign ci_master_a = ci_slave_a;
assign ci_master_ipending = ci_slave_ipending;
assign ci_master_estatus = ci_slave_estatus;
assign ci_master_clk = ci_slave_clk;
assign ci_master_clken = ci_slave_clken;
assign ci_master_reset = ci_slave_reset;
assign ci_master_reset_req = ci_slave_reset_req;
// --------------------------------------
// Is there something we need to do if the master does not
// have start?
// --------------------------------------
assign ci_master_start = ci_slave_start;
// --------------------------------------
// Create the done signal if the slave does not drive it.
//
// For num_cycles = 2, this is just the registered start.
// Anything larger and we use a down-counter.
// --------------------------------------
assign ci_slave_done = (USE_DONE == 1) ? ci_master_done : gen_done;
assign gen_done = (NUM_FIXED_CYCLES == 2) ? reg_start : (count == 0);
always @(posedge ci_slave_clk, posedge ci_slave_reset) begin
if (ci_slave_reset)
reg_start <= 0;
else if (ci_slave_clken)
reg_start <= ci_slave_start;
end
always @(posedge ci_slave_clk, posedge ci_slave_reset) begin
if (ci_slave_reset) begin
running <= 0;
count <= NUM_FIXED_CYCLES - 2;
end
else if (ci_slave_clken) begin
if (ci_slave_start)
running <= 1;
if (running)
count <= count - 1;
if (ci_slave_done) begin
running <= 0;
count <= NUM_FIXED_CYCLES - 2;
end
end
end
// --------------------------------------
// Opcode base addresses must be a multiple of their span,
// just like base addresses. This simplifies the following
// assignment (just drop the high order bits)
// --------------------------------------
assign ci_master_n = ci_slave_n[N_WIDTH-1:0];
endmodule |
module lms_ctr_mm_interconnect_0_cmd_mux
(
// ----------------------
// Sinks
// ----------------------
input sink0_valid,
input [103-1 : 0] sink0_data,
input [15-1: 0] sink0_channel,
input sink0_startofpacket,
input sink0_endofpacket,
output sink0_ready,
// ----------------------
// Source
// ----------------------
output src_valid,
output [103-1 : 0] src_data,
output [15-1 : 0] src_channel,
output src_startofpacket,
output src_endofpacket,
input src_ready,
// ----------------------
// Clock & Reset
// ----------------------
input clk,
input reset
);
localparam PAYLOAD_W = 103 + 15 + 2;
localparam NUM_INPUTS = 1;
localparam SHARE_COUNTER_W = 1;
localparam PIPELINE_ARB = 1;
localparam ST_DATA_W = 103;
localparam ST_CHANNEL_W = 15;
localparam PKT_TRANS_LOCK = 62;
assign src_valid = sink0_valid;
assign src_data = sink0_data;
assign src_channel = sink0_channel;
assign src_startofpacket = sink0_startofpacket;
assign src_endofpacket = sink0_endofpacket;
assign sink0_ready = src_ready;
endmodule |
module lms_ctr_mm_interconnect_0_cmd_demux
(
// -------------------
// Sink
// -------------------
input [1-1 : 0] sink_valid,
input [103-1 : 0] sink_data, // ST_DATA_W=103
input [15-1 : 0] sink_channel, // ST_CHANNEL_W=15
input sink_startofpacket,
input sink_endofpacket,
output sink_ready,
// -------------------
// Sources
// -------------------
output reg src0_valid,
output reg [103-1 : 0] src0_data, // ST_DATA_W=103
output reg [15-1 : 0] src0_channel, // ST_CHANNEL_W=15
output reg src0_startofpacket,
output reg src0_endofpacket,
input src0_ready,
output reg src1_valid,
output reg [103-1 : 0] src1_data, // ST_DATA_W=103
output reg [15-1 : 0] src1_channel, // ST_CHANNEL_W=15
output reg src1_startofpacket,
output reg src1_endofpacket,
input src1_ready,
output reg src2_valid,
output reg [103-1 : 0] src2_data, // ST_DATA_W=103
output reg [15-1 : 0] src2_channel, // ST_CHANNEL_W=15
output reg src2_startofpacket,
output reg src2_endofpacket,
input src2_ready,
output reg src3_valid,
output reg [103-1 : 0] src3_data, // ST_DATA_W=103
output reg [15-1 : 0] src3_channel, // ST_CHANNEL_W=15
output reg src3_startofpacket,
output reg src3_endofpacket,
input src3_ready,
output reg src4_valid,
output reg [103-1 : 0] src4_data, // ST_DATA_W=103
output reg [15-1 : 0] src4_channel, // ST_CHANNEL_W=15
output reg src4_startofpacket,
output reg src4_endofpacket,
input src4_ready,
output reg src5_valid,
output reg [103-1 : 0] src5_data, // ST_DATA_W=103
output reg [15-1 : 0] src5_channel, // ST_CHANNEL_W=15
output reg src5_startofpacket,
output reg src5_endofpacket,
input src5_ready,
output reg src6_valid,
output reg [103-1 : 0] src6_data, // ST_DATA_W=103
output reg [15-1 : 0] src6_channel, // ST_CHANNEL_W=15
output reg src6_startofpacket,
output reg src6_endofpacket,
input src6_ready,
output reg src7_valid,
output reg [103-1 : 0] src7_data, // ST_DATA_W=103
output reg [15-1 : 0] src7_channel, // ST_CHANNEL_W=15
output reg src7_startofpacket,
output reg src7_endofpacket,
input src7_ready,
output reg src8_valid,
output reg [103-1 : 0] src8_data, // ST_DATA_W=103
output reg [15-1 : 0] src8_channel, // ST_CHANNEL_W=15
output reg src8_startofpacket,
output reg src8_endofpacket,
input src8_ready,
output reg src9_valid,
output reg [103-1 : 0] src9_data, // ST_DATA_W=103
output reg [15-1 : 0] src9_channel, // ST_CHANNEL_W=15
output reg src9_startofpacket,
output reg src9_endofpacket,
input src9_ready,
output reg src10_valid,
output reg [103-1 : 0] src10_data, // ST_DATA_W=103
output reg [15-1 : 0] src10_channel, // ST_CHANNEL_W=15
output reg src10_startofpacket,
output reg src10_endofpacket,
input src10_ready,
output reg src11_valid,
output reg [103-1 : 0] src11_data, // ST_DATA_W=103
output reg [15-1 : 0] src11_channel, // ST_CHANNEL_W=15
output reg src11_startofpacket,
output reg src11_endofpacket,
input src11_ready,
output reg src12_valid,
output reg [103-1 : 0] src12_data, // ST_DATA_W=103
output reg [15-1 : 0] src12_channel, // ST_CHANNEL_W=15
output reg src12_startofpacket,
output reg src12_endofpacket,
input src12_ready,
output reg src13_valid,
output reg [103-1 : 0] src13_data, // ST_DATA_W=103
output reg [15-1 : 0] src13_channel, // ST_CHANNEL_W=15
output reg src13_startofpacket,
output reg src13_endofpacket,
input src13_ready,
output reg src14_valid,
output reg [103-1 : 0] src14_data, // ST_DATA_W=103
output reg [15-1 : 0] src14_channel, // ST_CHANNEL_W=15
output reg src14_startofpacket,
output reg src14_endofpacket,
input src14_ready,
// -------------------
// Clock & Reset
// -------------------
(*altera_attribute = "-name MESSAGE_DISABLE 15610" *) // setting message suppression on clk
input clk,
(*altera_attribute = "-name MESSAGE_DISABLE 15610" *) // setting message suppression on reset
input reset
);
localparam NUM_OUTPUTS = 15;
wire [NUM_OUTPUTS - 1 : 0] ready_vector;
// -------------------
// Demux
// -------------------
always @* begin
src0_data = sink_data;
src0_startofpacket = sink_startofpacket;
src0_endofpacket = sink_endofpacket;
src0_channel = sink_channel >> NUM_OUTPUTS;
src0_valid = sink_channel[0] && sink_valid;
src1_data = sink_data;
src1_startofpacket = sink_startofpacket;
src1_endofpacket = sink_endofpacket;
src1_channel = sink_channel >> NUM_OUTPUTS;
src1_valid = sink_channel[1] && sink_valid;
src2_data = sink_data;
src2_startofpacket = sink_startofpacket;
src2_endofpacket = sink_endofpacket;
src2_channel = sink_channel >> NUM_OUTPUTS;
src2_valid = sink_channel[2] && sink_valid;
src3_data = sink_data;
src3_startofpacket = sink_startofpacket;
src3_endofpacket = sink_endofpacket;
src3_channel = sink_channel >> NUM_OUTPUTS;
src3_valid = sink_channel[3] && sink_valid;
src4_data = sink_data;
src4_startofpacket = sink_startofpacket;
src4_endofpacket = sink_endofpacket;
src4_channel = sink_channel >> NUM_OUTPUTS;
src4_valid = sink_channel[4] && sink_valid;
src5_data = sink_data;
src5_startofpacket = sink_startofpacket;
src5_endofpacket = sink_endofpacket;
src5_channel = sink_channel >> NUM_OUTPUTS;
src5_valid = sink_channel[5] && sink_valid;
src6_data = sink_data;
src6_startofpacket = sink_startofpacket;
src6_endofpacket = sink_endofpacket;
src6_channel = sink_channel >> NUM_OUTPUTS;
src6_valid = sink_channel[6] && sink_valid;
src7_data = sink_data;
src7_startofpacket = sink_startofpacket;
src7_endofpacket = sink_endofpacket;
src7_channel = sink_channel >> NUM_OUTPUTS;
src7_valid = sink_channel[7] && sink_valid;
src8_data = sink_data;
src8_startofpacket = sink_startofpacket;
src8_endofpacket = sink_endofpacket;
src8_channel = sink_channel >> NUM_OUTPUTS;
src8_valid = sink_channel[8] && sink_valid;
src9_data = sink_data;
src9_startofpacket = sink_startofpacket;
src9_endofpacket = sink_endofpacket;
src9_channel = sink_channel >> NUM_OUTPUTS;
src9_valid = sink_channel[9] && sink_valid;
src10_data = sink_data;
src10_startofpacket = sink_startofpacket;
src10_endofpacket = sink_endofpacket;
src10_channel = sink_channel >> NUM_OUTPUTS;
src10_valid = sink_channel[10] && sink_valid;
src11_data = sink_data;
src11_startofpacket = sink_startofpacket;
src11_endofpacket = sink_endofpacket;
src11_channel = sink_channel >> NUM_OUTPUTS;
src11_valid = sink_channel[11] && sink_valid;
src12_data = sink_data;
src12_startofpacket = sink_startofpacket;
src12_endofpacket = sink_endofpacket;
src12_channel = sink_channel >> NUM_OUTPUTS;
src12_valid = sink_channel[12] && sink_valid;
src13_data = sink_data;
src13_startofpacket = sink_startofpacket;
src13_endofpacket = sink_endofpacket;
src13_channel = sink_channel >> NUM_OUTPUTS;
src13_valid = sink_channel[13] && sink_valid;
src14_data = sink_data;
src14_startofpacket = sink_startofpacket;
src14_endofpacket = sink_endofpacket;
src14_channel = sink_channel >> NUM_OUTPUTS;
src14_valid = sink_channel[14] && sink_valid;
end
// -------------------
// Backpressure
// -------------------
assign ready_vector[0] = src0_ready;
assign ready_vector[1] = src1_ready;
assign ready_vector[2] = src2_ready;
assign ready_vector[3] = src3_ready;
assign ready_vector[4] = src4_ready;
assign ready_vector[5] = src5_ready;
assign ready_vector[6] = src6_ready;
assign ready_vector[7] = src7_ready;
assign ready_vector[8] = src8_ready;
assign ready_vector[9] = src9_ready;
assign ready_vector[10] = src10_ready;
assign ready_vector[11] = src11_ready;
assign ready_vector[12] = src12_ready;
assign ready_vector[13] = src13_ready;
assign ready_vector[14] = src14_ready;
assign sink_ready = |(sink_channel & ready_vector);
endmodule |
module lms_ctr_mm_interconnect_0_router_001_default_decode
#(
parameter DEFAULT_CHANNEL = 0,
DEFAULT_WR_CHANNEL = -1,
DEFAULT_RD_CHANNEL = -1,
DEFAULT_DESTID = 10
)
(output [89 - 86 : 0] default_destination_id,
output [15-1 : 0] default_wr_channel,
output [15-1 : 0] default_rd_channel,
output [15-1 : 0] default_src_channel
);
assign default_destination_id =
DEFAULT_DESTID[89 - 86 : 0];
generate
if (DEFAULT_CHANNEL == -1) begin : no_default_channel_assignment
assign default_src_channel = '0;
end
else begin : default_channel_assignment
assign default_src_channel = 15'b1 << DEFAULT_CHANNEL;
end
endgenerate
generate
if (DEFAULT_RD_CHANNEL == -1) begin : no_default_rw_channel_assignment
assign default_wr_channel = '0;
assign default_rd_channel = '0;
end
else begin : default_rw_channel_assignment
assign default_wr_channel = 15'b1 << DEFAULT_WR_CHANNEL;
assign default_rd_channel = 15'b1 << DEFAULT_RD_CHANNEL;
end
endgenerate
endmodule |
module lms_ctr_mm_interconnect_0_router_001
(
// -------------------
// Clock & Reset
// -------------------
input clk,
input reset,
// -------------------
// Command Sink (Input)
// -------------------
input sink_valid,
input [103-1 : 0] sink_data,
input sink_startofpacket,
input sink_endofpacket,
output sink_ready,
// -------------------
// Command Source (Output)
// -------------------
output src_valid,
output reg [103-1 : 0] src_data,
output reg [15-1 : 0] src_channel,
output src_startofpacket,
output src_endofpacket,
input src_ready
);
// -------------------------------------------------------
// Local parameters and variables
// -------------------------------------------------------
localparam PKT_ADDR_H = 57;
localparam PKT_ADDR_L = 36;
localparam PKT_DEST_ID_H = 89;
localparam PKT_DEST_ID_L = 86;
localparam PKT_PROTECTION_H = 93;
localparam PKT_PROTECTION_L = 91;
localparam ST_DATA_W = 103;
localparam ST_CHANNEL_W = 15;
localparam DECODER_TYPE = 0;
localparam PKT_TRANS_WRITE = 60;
localparam PKT_TRANS_READ = 61;
localparam PKT_ADDR_W = PKT_ADDR_H-PKT_ADDR_L + 1;
localparam PKT_DEST_ID_W = PKT_DEST_ID_H-PKT_DEST_ID_L + 1;
// -------------------------------------------------------
// Figure out the number of bits to mask off for each slave span
// during address decoding
// -------------------------------------------------------
localparam PAD0 = log2ceil(64'h200000 - 64'h100000);
localparam PAD1 = log2ceil(64'h202000 - 64'h201800);
// -------------------------------------------------------
// Work out which address bits are significant based on the
// address range of the slaves. If the required width is too
// large or too small, we use the address field width instead.
// -------------------------------------------------------
localparam ADDR_RANGE = 64'h202000;
localparam RANGE_ADDR_WIDTH = log2ceil(ADDR_RANGE);
localparam OPTIMIZED_ADDR_H = (RANGE_ADDR_WIDTH > PKT_ADDR_W) ||
(RANGE_ADDR_WIDTH == 0) ?
PKT_ADDR_H :
PKT_ADDR_L + RANGE_ADDR_WIDTH - 1;
localparam RG = RANGE_ADDR_WIDTH-1;
localparam REAL_ADDRESS_RANGE = OPTIMIZED_ADDR_H - PKT_ADDR_L;
reg [PKT_ADDR_W-1 : 0] address;
always @* begin
address = {PKT_ADDR_W{1'b0}};
address [REAL_ADDRESS_RANGE:0] = sink_data[OPTIMIZED_ADDR_H : PKT_ADDR_L];
end
// -------------------------------------------------------
// Pass almost everything through, untouched
// -------------------------------------------------------
assign sink_ready = src_ready;
assign src_valid = sink_valid;
assign src_startofpacket = sink_startofpacket;
assign src_endofpacket = sink_endofpacket;
wire [PKT_DEST_ID_W-1:0] default_destid;
wire [15-1 : 0] default_src_channel;
lms_ctr_mm_interconnect_0_router_001_default_decode the_default_decode(
.default_destination_id (default_destid),
.default_wr_channel (),
.default_rd_channel (),
.default_src_channel (default_src_channel)
);
always @* begin
src_data = sink_data;
src_channel = default_src_channel;
src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = default_destid;
// --------------------------------------------------
// Address Decoder
// Sets the channel and destination ID based on the address
// --------------------------------------------------
// ( 0x100000 .. 0x200000 )
if ( {address[RG:PAD0],{PAD0{1'b0}}} == 22'h100000 ) begin
src_channel = 15'b01;
src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 10;
end
// ( 0x201800 .. 0x202000 )
if ( {address[RG:PAD1],{PAD1{1'b0}}} == 22'h201800 ) begin
src_channel = 15'b10;
src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 8;
end
end
// --------------------------------------------------
// Ceil(log2()) function
// --------------------------------------------------
function integer log2ceil;
input reg[65:0] val;
reg [65:0] i;
begin
i = 1;
log2ceil = 0;
while (i < val) begin
log2ceil = log2ceil + 1;
i = i << 1;
end
end
endfunction
endmodule |
module lms_ctr_mm_interconnect_0_router_002_default_decode
#(
parameter DEFAULT_CHANNEL = 0,
DEFAULT_WR_CHANNEL = -1,
DEFAULT_RD_CHANNEL = -1,
DEFAULT_DESTID = 0
)
(output [89 - 86 : 0] default_destination_id,
output [15-1 : 0] default_wr_channel,
output [15-1 : 0] default_rd_channel,
output [15-1 : 0] default_src_channel
);
assign default_destination_id =
DEFAULT_DESTID[89 - 86 : 0];
generate
if (DEFAULT_CHANNEL == -1) begin : no_default_channel_assignment
assign default_src_channel = '0;
end
else begin : default_channel_assignment
assign default_src_channel = 15'b1 << DEFAULT_CHANNEL;
end
endgenerate
generate
if (DEFAULT_RD_CHANNEL == -1) begin : no_default_rw_channel_assignment
assign default_wr_channel = '0;
assign default_rd_channel = '0;
end
else begin : default_rw_channel_assignment
assign default_wr_channel = 15'b1 << DEFAULT_WR_CHANNEL;
assign default_rd_channel = 15'b1 << DEFAULT_RD_CHANNEL;
end
endgenerate
endmodule |
module lms_ctr_mm_interconnect_0_router_002
(
// -------------------
// Clock & Reset
// -------------------
input clk,
input reset,
// -------------------
// Command Sink (Input)
// -------------------
input sink_valid,
input [103-1 : 0] sink_data,
input sink_startofpacket,
input sink_endofpacket,
output sink_ready,
// -------------------
// Command Source (Output)
// -------------------
output src_valid,
output reg [103-1 : 0] src_data,
output reg [15-1 : 0] src_channel,
output src_startofpacket,
output src_endofpacket,
input src_ready
);
// -------------------------------------------------------
// Local parameters and variables
// -------------------------------------------------------
localparam PKT_ADDR_H = 57;
localparam PKT_ADDR_L = 36;
localparam PKT_DEST_ID_H = 89;
localparam PKT_DEST_ID_L = 86;
localparam PKT_PROTECTION_H = 93;
localparam PKT_PROTECTION_L = 91;
localparam ST_DATA_W = 103;
localparam ST_CHANNEL_W = 15;
localparam DECODER_TYPE = 1;
localparam PKT_TRANS_WRITE = 60;
localparam PKT_TRANS_READ = 61;
localparam PKT_ADDR_W = PKT_ADDR_H-PKT_ADDR_L + 1;
localparam PKT_DEST_ID_W = PKT_DEST_ID_H-PKT_DEST_ID_L + 1;
// -------------------------------------------------------
// Figure out the number of bits to mask off for each slave span
// during address decoding
// -------------------------------------------------------
// -------------------------------------------------------
// Work out which address bits are significant based on the
// address range of the slaves. If the required width is too
// large or too small, we use the address field width instead.
// -------------------------------------------------------
localparam ADDR_RANGE = 64'h0;
localparam RANGE_ADDR_WIDTH = log2ceil(ADDR_RANGE);
localparam OPTIMIZED_ADDR_H = (RANGE_ADDR_WIDTH > PKT_ADDR_W) ||
(RANGE_ADDR_WIDTH == 0) ?
PKT_ADDR_H :
PKT_ADDR_L + RANGE_ADDR_WIDTH - 1;
localparam RG = RANGE_ADDR_WIDTH;
localparam REAL_ADDRESS_RANGE = OPTIMIZED_ADDR_H - PKT_ADDR_L;
reg [PKT_DEST_ID_W-1 : 0] destid;
// -------------------------------------------------------
// Pass almost everything through, untouched
// -------------------------------------------------------
assign sink_ready = src_ready;
assign src_valid = sink_valid;
assign src_startofpacket = sink_startofpacket;
assign src_endofpacket = sink_endofpacket;
wire [15-1 : 0] default_src_channel;
lms_ctr_mm_interconnect_0_router_002_default_decode the_default_decode(
.default_destination_id (),
.default_wr_channel (),
.default_rd_channel (),
.default_src_channel (default_src_channel)
);
always @* begin
src_data = sink_data;
src_channel = default_src_channel;
// --------------------------------------------------
// DestinationID Decoder
// Sets the channel based on the destination ID.
// --------------------------------------------------
destid = sink_data[PKT_DEST_ID_H : PKT_DEST_ID_L];
if (destid == 0 ) begin
src_channel = 15'b1;
end
end
// --------------------------------------------------
// Ceil(log2()) function
// --------------------------------------------------
function integer log2ceil;
input reg[65:0] val;
reg [65:0] i;
begin
i = 1;
log2ceil = 0;
while (i < val) begin
log2ceil = log2ceil + 1;
i = i << 1;
end
end
endfunction
endmodule |
module lms_ctr_mm_interconnect_0_cmd_mux_005
(
// ----------------------
// Sinks
// ----------------------
input sink0_valid,
input [103-1 : 0] sink0_data,
input [15-1: 0] sink0_channel,
input sink0_startofpacket,
input sink0_endofpacket,
output sink0_ready,
input sink1_valid,
input [103-1 : 0] sink1_data,
input [15-1: 0] sink1_channel,
input sink1_startofpacket,
input sink1_endofpacket,
output sink1_ready,
// ----------------------
// Source
// ----------------------
output src_valid,
output [103-1 : 0] src_data,
output [15-1 : 0] src_channel,
output src_startofpacket,
output src_endofpacket,
input src_ready,
// ----------------------
// Clock & Reset
// ----------------------
input clk,
input reset
);
localparam PAYLOAD_W = 103 + 15 + 2;
localparam NUM_INPUTS = 2;
localparam SHARE_COUNTER_W = 1;
localparam PIPELINE_ARB = 1;
localparam ST_DATA_W = 103;
localparam ST_CHANNEL_W = 15;
localparam PKT_TRANS_LOCK = 62;
// ------------------------------------------
// Signals
// ------------------------------------------
wire [NUM_INPUTS - 1 : 0] request;
wire [NUM_INPUTS - 1 : 0] valid;
wire [NUM_INPUTS - 1 : 0] grant;
wire [NUM_INPUTS - 1 : 0] next_grant;
reg [NUM_INPUTS - 1 : 0] saved_grant;
reg [PAYLOAD_W - 1 : 0] src_payload;
wire last_cycle;
reg packet_in_progress;
reg update_grant;
wire [PAYLOAD_W - 1 : 0] sink0_payload;
wire [PAYLOAD_W - 1 : 0] sink1_payload;
assign valid[0] = sink0_valid;
assign valid[1] = sink1_valid;
wire [NUM_INPUTS - 1 : 0] eop;
assign eop[0] = sink0_endofpacket;
assign eop[1] = sink1_endofpacket;
// ------------------------------------------
// ------------------------------------------
// Grant Logic & Updates
// ------------------------------------------
// ------------------------------------------
reg [NUM_INPUTS - 1 : 0] lock;
always @* begin
lock[0] = sink0_data[62];
lock[1] = sink1_data[62];
end
reg [NUM_INPUTS - 1 : 0] locked = '0;
always @(posedge clk or posedge reset) begin
if (reset) begin
locked <= '0;
end
else begin
locked <= next_grant & lock;
end
end
assign last_cycle = src_valid & src_ready & src_endofpacket & ~(|(lock & grant));
// ------------------------------------------
// We're working on a packet at any time valid is high, except
// when this is the endofpacket.
// ------------------------------------------
always @(posedge clk or posedge reset) begin
if (reset) begin
packet_in_progress <= 1'b0;
end
else begin
if (last_cycle)
packet_in_progress <= 1'b0;
else if (src_valid)
packet_in_progress <= 1'b1;
end
end
// ------------------------------------------
// Shares
//
// Special case: all-equal shares _should_ be optimized into assigning a
// constant to next_grant_share.
// Special case: all-1's shares _should_ result in the share counter
// being optimized away.
// ------------------------------------------
// Input | arb shares | counter load value
// 0 | 1 | 0
// 1 | 1 | 0
wire [SHARE_COUNTER_W - 1 : 0] share_0 = 1'd0;
wire [SHARE_COUNTER_W - 1 : 0] share_1 = 1'd0;
// ------------------------------------------
// Choose the share value corresponding to the grant.
// ------------------------------------------
reg [SHARE_COUNTER_W - 1 : 0] next_grant_share;
always @* begin
next_grant_share =
share_0 & { SHARE_COUNTER_W {next_grant[0]} } |
share_1 & { SHARE_COUNTER_W {next_grant[1]} };
end
// ------------------------------------------
// Flag to indicate first packet of an arb sequence.
// ------------------------------------------
// ------------------------------------------
// Compute the next share-count value.
// ------------------------------------------
reg [SHARE_COUNTER_W - 1 : 0] p1_share_count;
reg [SHARE_COUNTER_W - 1 : 0] share_count;
reg share_count_zero_flag;
always @* begin
// Update the counter, but don't decrement below 0.
p1_share_count = share_count_zero_flag ? '0 : share_count - 1'b1;
end
// ------------------------------------------
// Update the share counter and share-counter=zero flag.
// ------------------------------------------
always @(posedge clk or posedge reset) begin
if (reset) begin
share_count <= '0;
share_count_zero_flag <= 1'b1;
end
else begin
if (update_grant) begin
share_count <= next_grant_share;
share_count_zero_flag <= (next_grant_share == '0);
end
else if (last_cycle) begin
share_count <= p1_share_count;
share_count_zero_flag <= (p1_share_count == '0);
end
end
end
always @* begin
update_grant = 0;
// ------------------------------------------
// The pipeline delays grant by one cycle, so
// we have to calculate the update_grant signal
// one cycle ahead of time.
//
// Possible optimization: omit the first clause
// "if (!packet_in_progress & ~src_valid) ..."
// cost: one idle cycle at the the beginning of each
// grant cycle.
// benefit: save a small amount of logic.
// ------------------------------------------
if (!packet_in_progress & !src_valid)
update_grant = 1;
if (last_cycle && share_count_zero_flag)
update_grant = 1;
end
wire save_grant;
assign save_grant = update_grant;
assign grant = saved_grant;
always @(posedge clk, posedge reset) begin
if (reset)
saved_grant <= '0;
else if (save_grant)
saved_grant <= next_grant;
end
// ------------------------------------------
// ------------------------------------------
// Arbitrator
// ------------------------------------------
// ------------------------------------------
// ------------------------------------------
// Create a request vector that stays high during
// the packet for unpipelined arbitration.
//
// The pipelined arbitration scheme does not require
// request to be held high during the packet.
// ------------------------------------------
reg [NUM_INPUTS - 1 : 0] prev_request;
always @(posedge clk, posedge reset) begin
if (reset)
prev_request <= '0;
else
prev_request <= request & ~(valid & eop);
end
assign request = (PIPELINE_ARB == 1) ? valid | locked :
prev_request | valid | locked;
wire [NUM_INPUTS - 1 : 0] next_grant_from_arb;
altera_merlin_arbitrator
#(
.NUM_REQUESTERS(NUM_INPUTS),
.SCHEME ("round-robin"),
.PIPELINE (1)
) arb (
.clk (clk),
.reset (reset),
.request (request),
.grant (next_grant_from_arb),
.save_top_priority (src_valid),
.increment_top_priority (update_grant)
);
assign next_grant = next_grant_from_arb;
// ------------------------------------------
// ------------------------------------------
// Mux
//
// Implemented as a sum of products.
// ------------------------------------------
// ------------------------------------------
assign sink0_ready = src_ready && grant[0];
assign sink1_ready = src_ready && grant[1];
assign src_valid = |(grant & valid);
always @* begin
src_payload =
sink0_payload & {PAYLOAD_W {grant[0]} } |
sink1_payload & {PAYLOAD_W {grant[1]} };
end
// ------------------------------------------
// Mux Payload Mapping
// ------------------------------------------
assign sink0_payload = {sink0_channel,sink0_data,
sink0_startofpacket,sink0_endofpacket};
assign sink1_payload = {sink1_channel,sink1_data,
sink1_startofpacket,sink1_endofpacket};
assign {src_channel,src_data,src_startofpacket,src_endofpacket} = src_payload;
endmodule |
module lms_ctr_mm_interconnect_0_rsp_mux
(
// ----------------------
// Sinks
// ----------------------
input sink0_valid,
input [103-1 : 0] sink0_data,
input [15-1: 0] sink0_channel,
input sink0_startofpacket,
input sink0_endofpacket,
output sink0_ready,
input sink1_valid,
input [103-1 : 0] sink1_data,
input [15-1: 0] sink1_channel,
input sink1_startofpacket,
input sink1_endofpacket,
output sink1_ready,
input sink2_valid,
input [103-1 : 0] sink2_data,
input [15-1: 0] sink2_channel,
input sink2_startofpacket,
input sink2_endofpacket,
output sink2_ready,
input sink3_valid,
input [103-1 : 0] sink3_data,
input [15-1: 0] sink3_channel,
input sink3_startofpacket,
input sink3_endofpacket,
output sink3_ready,
input sink4_valid,
input [103-1 : 0] sink4_data,
input [15-1: 0] sink4_channel,
input sink4_startofpacket,
input sink4_endofpacket,
output sink4_ready,
input sink5_valid,
input [103-1 : 0] sink5_data,
input [15-1: 0] sink5_channel,
input sink5_startofpacket,
input sink5_endofpacket,
output sink5_ready,
input sink6_valid,
input [103-1 : 0] sink6_data,
input [15-1: 0] sink6_channel,
input sink6_startofpacket,
input sink6_endofpacket,
output sink6_ready,
input sink7_valid,
input [103-1 : 0] sink7_data,
input [15-1: 0] sink7_channel,
input sink7_startofpacket,
input sink7_endofpacket,
output sink7_ready,
input sink8_valid,
input [103-1 : 0] sink8_data,
input [15-1: 0] sink8_channel,
input sink8_startofpacket,
input sink8_endofpacket,
output sink8_ready,
input sink9_valid,
input [103-1 : 0] sink9_data,
input [15-1: 0] sink9_channel,
input sink9_startofpacket,
input sink9_endofpacket,
output sink9_ready,
input sink10_valid,
input [103-1 : 0] sink10_data,
input [15-1: 0] sink10_channel,
input sink10_startofpacket,
input sink10_endofpacket,
output sink10_ready,
input sink11_valid,
input [103-1 : 0] sink11_data,
input [15-1: 0] sink11_channel,
input sink11_startofpacket,
input sink11_endofpacket,
output sink11_ready,
input sink12_valid,
input [103-1 : 0] sink12_data,
input [15-1: 0] sink12_channel,
input sink12_startofpacket,
input sink12_endofpacket,
output sink12_ready,
input sink13_valid,
input [103-1 : 0] sink13_data,
input [15-1: 0] sink13_channel,
input sink13_startofpacket,
input sink13_endofpacket,
output sink13_ready,
input sink14_valid,
input [103-1 : 0] sink14_data,
input [15-1: 0] sink14_channel,
input sink14_startofpacket,
input sink14_endofpacket,
output sink14_ready,
// ----------------------
// Source
// ----------------------
output src_valid,
output [103-1 : 0] src_data,
output [15-1 : 0] src_channel,
output src_startofpacket,
output src_endofpacket,
input src_ready,
// ----------------------
// Clock & Reset
// ----------------------
input clk,
input reset
);
localparam PAYLOAD_W = 103 + 15 + 2;
localparam NUM_INPUTS = 15;
localparam SHARE_COUNTER_W = 1;
localparam PIPELINE_ARB = 0;
localparam ST_DATA_W = 103;
localparam ST_CHANNEL_W = 15;
localparam PKT_TRANS_LOCK = 62;
// ------------------------------------------
// Signals
// ------------------------------------------
wire [NUM_INPUTS - 1 : 0] request;
wire [NUM_INPUTS - 1 : 0] valid;
wire [NUM_INPUTS - 1 : 0] grant;
wire [NUM_INPUTS - 1 : 0] next_grant;
reg [NUM_INPUTS - 1 : 0] saved_grant;
reg [PAYLOAD_W - 1 : 0] src_payload;
wire last_cycle;
reg packet_in_progress;
reg update_grant;
wire [PAYLOAD_W - 1 : 0] sink0_payload;
wire [PAYLOAD_W - 1 : 0] sink1_payload;
wire [PAYLOAD_W - 1 : 0] sink2_payload;
wire [PAYLOAD_W - 1 : 0] sink3_payload;
wire [PAYLOAD_W - 1 : 0] sink4_payload;
wire [PAYLOAD_W - 1 : 0] sink5_payload;
wire [PAYLOAD_W - 1 : 0] sink6_payload;
wire [PAYLOAD_W - 1 : 0] sink7_payload;
wire [PAYLOAD_W - 1 : 0] sink8_payload;
wire [PAYLOAD_W - 1 : 0] sink9_payload;
wire [PAYLOAD_W - 1 : 0] sink10_payload;
wire [PAYLOAD_W - 1 : 0] sink11_payload;
wire [PAYLOAD_W - 1 : 0] sink12_payload;
wire [PAYLOAD_W - 1 : 0] sink13_payload;
wire [PAYLOAD_W - 1 : 0] sink14_payload;
assign valid[0] = sink0_valid;
assign valid[1] = sink1_valid;
assign valid[2] = sink2_valid;
assign valid[3] = sink3_valid;
assign valid[4] = sink4_valid;
assign valid[5] = sink5_valid;
assign valid[6] = sink6_valid;
assign valid[7] = sink7_valid;
assign valid[8] = sink8_valid;
assign valid[9] = sink9_valid;
assign valid[10] = sink10_valid;
assign valid[11] = sink11_valid;
assign valid[12] = sink12_valid;
assign valid[13] = sink13_valid;
assign valid[14] = sink14_valid;
// ------------------------------------------
// ------------------------------------------
// Grant Logic & Updates
// ------------------------------------------
// ------------------------------------------
reg [NUM_INPUTS - 1 : 0] lock;
always @* begin
lock[0] = sink0_data[62];
lock[1] = sink1_data[62];
lock[2] = sink2_data[62];
lock[3] = sink3_data[62];
lock[4] = sink4_data[62];
lock[5] = sink5_data[62];
lock[6] = sink6_data[62];
lock[7] = sink7_data[62];
lock[8] = sink8_data[62];
lock[9] = sink9_data[62];
lock[10] = sink10_data[62];
lock[11] = sink11_data[62];
lock[12] = sink12_data[62];
lock[13] = sink13_data[62];
lock[14] = sink14_data[62];
end
assign last_cycle = src_valid & src_ready & src_endofpacket & ~(|(lock & grant));
// ------------------------------------------
// We're working on a packet at any time valid is high, except
// when this is the endofpacket.
// ------------------------------------------
always @(posedge clk or posedge reset) begin
if (reset) begin
packet_in_progress <= 1'b0;
end
else begin
if (last_cycle)
packet_in_progress <= 1'b0;
else if (src_valid)
packet_in_progress <= 1'b1;
end
end
// ------------------------------------------
// Shares
//
// Special case: all-equal shares _should_ be optimized into assigning a
// constant to next_grant_share.
// Special case: all-1's shares _should_ result in the share counter
// being optimized away.
// ------------------------------------------
// Input | arb shares | counter load value
// 0 | 1 | 0
// 1 | 1 | 0
// 2 | 1 | 0
// 3 | 1 | 0
// 4 | 1 | 0
// 5 | 1 | 0
// 6 | 1 | 0
// 7 | 1 | 0
// 8 | 1 | 0
// 9 | 1 | 0
// 10 | 1 | 0
// 11 | 1 | 0
// 12 | 1 | 0
// 13 | 1 | 0
// 14 | 1 | 0
wire [SHARE_COUNTER_W - 1 : 0] share_0 = 1'd0;
wire [SHARE_COUNTER_W - 1 : 0] share_1 = 1'd0;
wire [SHARE_COUNTER_W - 1 : 0] share_2 = 1'd0;
wire [SHARE_COUNTER_W - 1 : 0] share_3 = 1'd0;
wire [SHARE_COUNTER_W - 1 : 0] share_4 = 1'd0;
wire [SHARE_COUNTER_W - 1 : 0] share_5 = 1'd0;
wire [SHARE_COUNTER_W - 1 : 0] share_6 = 1'd0;
wire [SHARE_COUNTER_W - 1 : 0] share_7 = 1'd0;
wire [SHARE_COUNTER_W - 1 : 0] share_8 = 1'd0;
wire [SHARE_COUNTER_W - 1 : 0] share_9 = 1'd0;
wire [SHARE_COUNTER_W - 1 : 0] share_10 = 1'd0;
wire [SHARE_COUNTER_W - 1 : 0] share_11 = 1'd0;
wire [SHARE_COUNTER_W - 1 : 0] share_12 = 1'd0;
wire [SHARE_COUNTER_W - 1 : 0] share_13 = 1'd0;
wire [SHARE_COUNTER_W - 1 : 0] share_14 = 1'd0;
// ------------------------------------------
// Choose the share value corresponding to the grant.
// ------------------------------------------
reg [SHARE_COUNTER_W - 1 : 0] next_grant_share;
always @* begin
next_grant_share =
share_0 & { SHARE_COUNTER_W {next_grant[0]} } |
share_1 & { SHARE_COUNTER_W {next_grant[1]} } |
share_2 & { SHARE_COUNTER_W {next_grant[2]} } |
share_3 & { SHARE_COUNTER_W {next_grant[3]} } |
share_4 & { SHARE_COUNTER_W {next_grant[4]} } |
share_5 & { SHARE_COUNTER_W {next_grant[5]} } |
share_6 & { SHARE_COUNTER_W {next_grant[6]} } |
share_7 & { SHARE_COUNTER_W {next_grant[7]} } |
share_8 & { SHARE_COUNTER_W {next_grant[8]} } |
share_9 & { SHARE_COUNTER_W {next_grant[9]} } |
share_10 & { SHARE_COUNTER_W {next_grant[10]} } |
share_11 & { SHARE_COUNTER_W {next_grant[11]} } |
share_12 & { SHARE_COUNTER_W {next_grant[12]} } |
share_13 & { SHARE_COUNTER_W {next_grant[13]} } |
share_14 & { SHARE_COUNTER_W {next_grant[14]} };
end
// ------------------------------------------
// Flag to indicate first packet of an arb sequence.
// ------------------------------------------
wire grant_changed = ~packet_in_progress && ~(|(saved_grant & valid));
reg first_packet_r;
wire first_packet = grant_changed | first_packet_r;
always @(posedge clk or posedge reset) begin
if (reset) begin
first_packet_r <= 1'b0;
end
else begin
if (update_grant)
first_packet_r <= 1'b1;
else if (last_cycle)
first_packet_r <= 1'b0;
else if (grant_changed)
first_packet_r <= 1'b1;
end
end
// ------------------------------------------
// Compute the next share-count value.
// ------------------------------------------
reg [SHARE_COUNTER_W - 1 : 0] p1_share_count;
reg [SHARE_COUNTER_W - 1 : 0] share_count;
reg share_count_zero_flag;
always @* begin
if (first_packet) begin
p1_share_count = next_grant_share;
end
else begin
// Update the counter, but don't decrement below 0.
p1_share_count = share_count_zero_flag ? '0 : share_count - 1'b1;
end
end
// ------------------------------------------
// Update the share counter and share-counter=zero flag.
// ------------------------------------------
always @(posedge clk or posedge reset) begin
if (reset) begin
share_count <= '0;
share_count_zero_flag <= 1'b1;
end
else begin
if (last_cycle) begin
share_count <= p1_share_count;
share_count_zero_flag <= (p1_share_count == '0);
end
end
end
// ------------------------------------------
// For each input, maintain a final_packet signal which goes active for the
// last packet of a full-share packet sequence. Example: if I have 4
// shares and I'm continuously requesting, final_packet is active in the
// 4th packet.
// ------------------------------------------
wire final_packet_0 = 1'b1;
wire final_packet_1 = 1'b1;
wire final_packet_2 = 1'b1;
wire final_packet_3 = 1'b1;
wire final_packet_4 = 1'b1;
wire final_packet_5 = 1'b1;
wire final_packet_6 = 1'b1;
wire final_packet_7 = 1'b1;
wire final_packet_8 = 1'b1;
wire final_packet_9 = 1'b1;
wire final_packet_10 = 1'b1;
wire final_packet_11 = 1'b1;
wire final_packet_12 = 1'b1;
wire final_packet_13 = 1'b1;
wire final_packet_14 = 1'b1;
// ------------------------------------------
// Concatenate all final_packet signals (wire or reg) into a handy vector.
// ------------------------------------------
wire [NUM_INPUTS - 1 : 0] final_packet = {
final_packet_14,
final_packet_13,
final_packet_12,
final_packet_11,
final_packet_10,
final_packet_9,
final_packet_8,
final_packet_7,
final_packet_6,
final_packet_5,
final_packet_4,
final_packet_3,
final_packet_2,
final_packet_1,
final_packet_0
};
// ------------------------------------------
// ------------------------------------------
wire p1_done = |(final_packet & grant);
// ------------------------------------------
// Flag for the first cycle of packets within an
// arb sequence
// ------------------------------------------
reg first_cycle;
always @(posedge clk, posedge reset) begin
if (reset)
first_cycle <= 0;
else
first_cycle <= last_cycle && ~p1_done;
end
always @* begin
update_grant = 0;
// ------------------------------------------
// No arbitration pipeline, update grant whenever
// the current arb winner has consumed all shares,
// or all requests are low
// ------------------------------------------
update_grant = (last_cycle && p1_done) || (first_cycle && ~(|valid));
update_grant = last_cycle;
end
wire save_grant;
assign save_grant = 1;
assign grant = next_grant;
always @(posedge clk, posedge reset) begin
if (reset)
saved_grant <= '0;
else if (save_grant)
saved_grant <= next_grant;
end
// ------------------------------------------
// ------------------------------------------
// Arbitrator
// ------------------------------------------
// ------------------------------------------
// ------------------------------------------
// Create a request vector that stays high during
// the packet for unpipelined arbitration.
//
// The pipelined arbitration scheme does not require
// request to be held high during the packet.
// ------------------------------------------
assign request = valid;
wire [NUM_INPUTS - 1 : 0] next_grant_from_arb;
altera_merlin_arbitrator
#(
.NUM_REQUESTERS(NUM_INPUTS),
.SCHEME ("no-arb"),
.PIPELINE (0)
) arb (
.clk (clk),
.reset (reset),
.request (request),
.grant (next_grant_from_arb),
.save_top_priority (src_valid),
.increment_top_priority (update_grant)
);
assign next_grant = next_grant_from_arb;
// ------------------------------------------
// ------------------------------------------
// Mux
//
// Implemented as a sum of products.
// ------------------------------------------
// ------------------------------------------
assign sink0_ready = src_ready && grant[0];
assign sink1_ready = src_ready && grant[1];
assign sink2_ready = src_ready && grant[2];
assign sink3_ready = src_ready && grant[3];
assign sink4_ready = src_ready && grant[4];
assign sink5_ready = src_ready && grant[5];
assign sink6_ready = src_ready && grant[6];
assign sink7_ready = src_ready && grant[7];
assign sink8_ready = src_ready && grant[8];
assign sink9_ready = src_ready && grant[9];
assign sink10_ready = src_ready && grant[10];
assign sink11_ready = src_ready && grant[11];
assign sink12_ready = src_ready && grant[12];
assign sink13_ready = src_ready && grant[13];
assign sink14_ready = src_ready && grant[14];
assign src_valid = |(grant & valid);
always @* begin
src_payload =
sink0_payload & {PAYLOAD_W {grant[0]} } |
sink1_payload & {PAYLOAD_W {grant[1]} } |
sink2_payload & {PAYLOAD_W {grant[2]} } |
sink3_payload & {PAYLOAD_W {grant[3]} } |
sink4_payload & {PAYLOAD_W {grant[4]} } |
sink5_payload & {PAYLOAD_W {grant[5]} } |
sink6_payload & {PAYLOAD_W {grant[6]} } |
sink7_payload & {PAYLOAD_W {grant[7]} } |
sink8_payload & {PAYLOAD_W {grant[8]} } |
sink9_payload & {PAYLOAD_W {grant[9]} } |
sink10_payload & {PAYLOAD_W {grant[10]} } |
sink11_payload & {PAYLOAD_W {grant[11]} } |
sink12_payload & {PAYLOAD_W {grant[12]} } |
sink13_payload & {PAYLOAD_W {grant[13]} } |
sink14_payload & {PAYLOAD_W {grant[14]} };
end
// ------------------------------------------
// Mux Payload Mapping
// ------------------------------------------
assign sink0_payload = {sink0_channel,sink0_data,
sink0_startofpacket,sink0_endofpacket};
assign sink1_payload = {sink1_channel,sink1_data,
sink1_startofpacket,sink1_endofpacket};
assign sink2_payload = {sink2_channel,sink2_data,
sink2_startofpacket,sink2_endofpacket};
assign sink3_payload = {sink3_channel,sink3_data,
sink3_startofpacket,sink3_endofpacket};
assign sink4_payload = {sink4_channel,sink4_data,
sink4_startofpacket,sink4_endofpacket};
assign sink5_payload = {sink5_channel,sink5_data,
sink5_startofpacket,sink5_endofpacket};
assign sink6_payload = {sink6_channel,sink6_data,
sink6_startofpacket,sink6_endofpacket};
assign sink7_payload = {sink7_channel,sink7_data,
sink7_startofpacket,sink7_endofpacket};
assign sink8_payload = {sink8_channel,sink8_data,
sink8_startofpacket,sink8_endofpacket};
assign sink9_payload = {sink9_channel,sink9_data,
sink9_startofpacket,sink9_endofpacket};
assign sink10_payload = {sink10_channel,sink10_data,
sink10_startofpacket,sink10_endofpacket};
assign sink11_payload = {sink11_channel,sink11_data,
sink11_startofpacket,sink11_endofpacket};
assign sink12_payload = {sink12_channel,sink12_data,
sink12_startofpacket,sink12_endofpacket};
assign sink13_payload = {sink13_channel,sink13_data,
sink13_startofpacket,sink13_endofpacket};
assign sink14_payload = {sink14_channel,sink14_data,
sink14_startofpacket,sink14_endofpacket};
assign {src_channel,src_data,src_startofpacket,src_endofpacket} = src_payload;
endmodule |
module lms_ctr_mm_interconnect_0_router_default_decode
#(
parameter DEFAULT_CHANNEL = 5,
DEFAULT_WR_CHANNEL = -1,
DEFAULT_RD_CHANNEL = -1,
DEFAULT_DESTID = 10
)
(output [89 - 86 : 0] default_destination_id,
output [15-1 : 0] default_wr_channel,
output [15-1 : 0] default_rd_channel,
output [15-1 : 0] default_src_channel
);
assign default_destination_id =
DEFAULT_DESTID[89 - 86 : 0];
generate
if (DEFAULT_CHANNEL == -1) begin : no_default_channel_assignment
assign default_src_channel = '0;
end
else begin : default_channel_assignment
assign default_src_channel = 15'b1 << DEFAULT_CHANNEL;
end
endgenerate
generate
if (DEFAULT_RD_CHANNEL == -1) begin : no_default_rw_channel_assignment
assign default_wr_channel = '0;
assign default_rd_channel = '0;
end
else begin : default_rw_channel_assignment
assign default_wr_channel = 15'b1 << DEFAULT_WR_CHANNEL;
assign default_rd_channel = 15'b1 << DEFAULT_RD_CHANNEL;
end
endgenerate
endmodule |
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