uid
int64 2
114k
| input
stringlengths 101
58.4k
| output
stringlengths 422
72.4k
| input_tokens
int64 24
31.2k
| output_tokens
int64 182
31.2k
|
|---|---|---|---|---|
2 |
Convert the following CUDA device assembly code to AMD device assembly:
```cudaasm
code for sm_80
Function : _Z8MyKernelPii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
MOV R1, c[0x0][0x28] ;
S2R R2, SR_TID.X ;
S2R R3, SR_CTAID.X ;
IMAD R2, R3, c[0x0][0x0], R2 ;
ISETP.GE.AND P0, PT, R2, c[0x0][0x168], PT ;
@P0 EXIT ;
HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ;
ULDC.64 UR4, c[0x0][0x118] ;
IMAD.WIDE R2, R2, R3, c[0x0][0x160] ;
LDG.E R0, [R2.64] ;
IMAD R5, R0, R0, RZ ;
STG.E [R2.64], R5 ;
EXIT ;
BRA 0xd0;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
```
|
```amdasm
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z8MyKernelPii ; -- Begin function _Z8MyKernelPii
.globl _Z8MyKernelPii
.p2align 8
.type _Z8MyKernelPii,@function
_Z8MyKernelPii: ; @_Z8MyKernelPii
; %bb.0:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x1c
s_load_b32 s3, s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
; %bb.1:
s_load_b64 s[0:1], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_load_b32 v2, v[0:1], off
s_waitcnt vmcnt(0)
v_mul_lo_u32 v2, v2, v2
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z8MyKernelPii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z8MyKernelPii, .Lfunc_end0-_Z8MyKernelPii
; -- End function
.section .AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 144
; NumSgprs: 18
; NumVgprs: 3
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 3
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object ; @__hip_cuid_
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0 ; 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z8MyKernelPii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z8MyKernelPii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
```
| 319 | 2,342 |
3 |
Convert the following CUDA host assembly code to AMD host assembly:
```cudaasm
.file "tmpxft_00122270_00000000-6_occupancy.cudafe1.cpp"
.text
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "Launched blocks of size %d with gridSize %d. Theoretical occupancy: %f\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $1096, %rsp
.cfi_def_cfa_offset 1152
movq %fs:40, %rax
movq %rax, 1080(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rdi
call cudaGetDevice@PLT
testl %eax, %eax
je .L11
.L4:
leal 1048575(%rbx), %eax
cltd
idivl %ebx
movl %eax, %ebp
call cudaDeviceSynchronize@PLT
leaq 40(%rsp), %rdi
movl $0, %r8d
movl $0, %ecx
movl %ebx, %edx
leaq _Z8MyKernelPii(%rip), %rsi
call cudaOccupancyMaxActiveBlocksPerMultiprocessorWithFlags@PLT
leaq 44(%rsp), %rdi
call cudaGetDevice@PLT
leaq 48(%rsp), %rdi
movl 44(%rsp), %esi
call cudaGetDeviceProperties_v2@PLT
movl 356(%rsp), %ecx
movl %ebx, %eax
imull 40(%rsp), %eax
cltd
idivl %ecx
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movl 672(%rsp), %eax
cltd
idivl %ecx
pxor %xmm1, %xmm1
cvtsi2ssl %eax, %xmm1
divss %xmm1, %xmm0
cvtss2sd %xmm0, %xmm0
movl %ebp, %ecx
movl %ebx, %edx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 1080(%rsp), %rax
subq %fs:40, %rax
jne .L12
movl $0, %eax
addq $1096, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore_state
leaq 28(%rsp), %rdi
movl 24(%rsp), %edx
movl $39, %esi
call cudaDeviceGetAttribute@PLT
testl %eax, %eax
jne .L4
leaq 32(%rsp), %rdi
movl 24(%rsp), %edx
movl $10, %esi
call cudaDeviceGetAttribute@PLT
testl %eax, %eax
jne .L4
leaq 36(%rsp), %rdi
movl 24(%rsp), %edx
movl $1, %esi
call cudaDeviceGetAttribute@PLT
testl %eax, %eax
jne .L4
leaq 40(%rsp), %rdi
movl 24(%rsp), %edx
movl $16, %esi
call cudaDeviceGetAttribute@PLT
testl %eax, %eax
jne .L4
leaq 48(%rsp), %rdi
leaq _Z8MyKernelPii(%rip), %rsi
call cudaFuncGetAttributes@PLT
testl %eax, %eax
jne .L4
movl 28(%rsp), %eax
movl %eax, 12(%rsp)
movl 32(%rsp), %r15d
movl 72(%rsp), %r13d
movl 36(%rsp), %eax
cmpl %eax, %r13d
cmovg %eax, %r13d
leal -1(%r15,%r13), %eax
cltd
idivl %r15d
imull %r15d, %eax
movl %eax, %ebp
movl $0, %r14d
movl $0, %ebx
jmp .L5
.L6:
cmpl %r14d, 12(%rsp)
je .L4
subl %r15d, %ebp
.L5:
testl %ebp, %ebp
jle .L4
cmpl %ebp, %r13d
movl %ebp, %r12d
cmovle %r13d, %r12d
leaq 44(%rsp), %rdi
movl $0, %r8d
movl $0, %ecx
movl %r12d, %edx
leaq _Z8MyKernelPii(%rip), %rsi
call cudaOccupancyMaxActiveBlocksPerMultiprocessorWithFlags@PLT
testl %eax, %eax
jne .L4
movl %r12d, %eax
imull 44(%rsp), %eax
cmpl %r14d, %eax
jle .L6
movl %eax, %r14d
movl %r12d, %ebx
jmp .L6
.L12:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.globl _Z28__device_stub__Z8MyKernelPiiPii
.type _Z28__device_stub__Z8MyKernelPiiPii, @function
_Z28__device_stub__Z8MyKernelPiiPii:
.LFB2082:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L17
.L13:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L18
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L17:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z8MyKernelPii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L13
.L18:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z28__device_stub__Z8MyKernelPiiPii, .-_Z28__device_stub__Z8MyKernelPiiPii
.globl _Z8MyKernelPii
.type _Z8MyKernelPii, @function
_Z8MyKernelPii:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z28__device_stub__Z8MyKernelPiiPii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z8MyKernelPii, .-_Z8MyKernelPii
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "_Z8MyKernelPii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z8MyKernelPii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
```
|
```amdasm
.text
.file "occupancy.hip"
.globl _Z23__device_stub__MyKernelPii # -- Begin function _Z23__device_stub__MyKernelPii
.type _Z23__device_stub__MyKernelPii,@function
_Z23__device_stub__MyKernelPii: # @_Z23__device_stub__MyKernelPii
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $80, %rsp
.cfi_def_cfa_offset 128
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 24(%rsp), %rax
movq %rdi, (%rax)
leaq 4(%rsp), %rcx
movl %esi, (%rcx)
leaq 64(%rsp), %rbx
movq %rax, (%rbx)
movq %rcx, 8(%rbx)
leaq 48(%rsp), %r14
leaq 32(%rsp), %r15
leaq 16(%rsp), %r12
leaq 8(%rsp), %r13
movq %r14, %rdi
movq %r15, %rsi
movq %r12, %rdx
movq %r13, %rcx
callq __hipPopCallConfiguration
movq (%r14), %rsi
movl 8(%r14), %edx
movq (%r15), %rcx
movl 8(%r15), %r8d
movl $_Z8MyKernelPii, %edi
movq %rbx, %r9
pushq (%r13)
.cfi_adjust_cfa_offset 8
pushq (%r12)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $96, %rsp
.cfi_adjust_cfa_offset -96
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z23__device_stub__MyKernelPii, .Lfunc_end0-_Z23__device_stub__MyKernelPii
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $1496, %rsp # imm = 0x5D8
.cfi_def_cfa_offset 1536
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 16(%rsp), %rdi
leaq 20(%rsp), %r14
movl $_Z8MyKernelPii, %edx
movq %r14, %rsi
xorl %ecx, %ecx
xorl %r8d, %r8d
callq hipOccupancyMaxPotentialBlockSize
movl (%r14), %ecx
leal 1048575(%rcx), %eax
cltd
idivl %ecx
movl %eax, %ebx
callq hipDeviceSynchronize
movl (%r14), %edx
leaq 12(%rsp), %r15
movl $_Z8MyKernelPii, %esi
movq %r15, %rdi
xorl %ecx, %ecx
callq hipOccupancyMaxActiveBlocksPerMultiprocessor
leaq 8(%rsp), %r12
movq %r12, %rdi
callq hipGetDevice
movl (%r12), %esi
leaq 24(%rsp), %r12
movq %r12, %rdi
callq hipGetDevicePropertiesR0600
movl (%r14), %esi
movl (%r15), %eax
imull %esi, %eax
movl 308(%r12), %edi
movl 624(%r12), %ecx
cltd
idivl %edi
cvtsi2ss %eax, %xmm0
movl %ecx, %eax
cltd
idivl %edi
cvtsi2ss %eax, %xmm1
divss %xmm1, %xmm0
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movl %ebx, %edx
movb $1, %al
callq printf
xorl %eax, %eax
addq $1496, %rsp # imm = 0x5D8
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, %rdi
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8MyKernelPii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z8MyKernelPii,@object # @_Z8MyKernelPii
.section .rodata,"a",@progbits
.globl _Z8MyKernelPii
.p2align 3, 0x0
_Z8MyKernelPii:
.quad _Z23__device_stub__MyKernelPii
.size _Z8MyKernelPii, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Launched blocks of size %d with gridSize %d. Theoretical occupancy: %f\n"
.size .L.str, 72
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z8MyKernelPii"
.size .L__unnamed_1, 15
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z23__device_stub__MyKernelPii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z8MyKernelPii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
```
| 3,445 | 2,809 |
4 |
Convert the following CUDA device assembly code to AMD device assembly:
```cudaasm
code for sm_80
Function : _Z10matrix_addPKfS0_Pf
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
MOV R1, c[0x0][0x28] ;
S2R R0, SR_TID.X ;
HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ;
ULDC.64 UR4, c[0x0][0x118] ;
S2R R3, SR_CTAID.X ;
S2R R2, SR_TID.Y ;
S2R R5, SR_CTAID.Y ;
IMAD R0, R3, c[0x0][0x0], R0 ;
IMAD R3, R5, c[0x0][0x4], R2 ;
LEA R0, R3, R0, 0x5 ;
IMAD.WIDE R2, R0, R7, c[0x0][0x160] ;
IMAD.WIDE R4, R0.reuse, R7.reuse, c[0x0][0x168] ;
LDG.E R2, [R2.64] ;
LDG.E R5, [R4.64] ;
IMAD.WIDE R6, R0, R7, c[0x0][0x170] ;
FADD R9, R2, R5 ;
STG.E [R6.64], R9 ;
EXIT ;
BRA 0x120;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
```
|
```amdasm
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10matrix_addPKfS0_Pf ; -- Begin function _Z10matrix_addPKfS0_Pf
.globl _Z10matrix_addPKfS0_Pf
.p2align 8
.type _Z10matrix_addPKfS0_Pf,@function
_Z10matrix_addPKfS0_Pf: ; @_Z10matrix_addPKfS0_Pf
; %bb.0:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b128 s[4:7], s[0:1], 0x0
v_bfe_u32 v1, v0, 10, 10
v_and_b32_e32 v0, 0x3ff, v0
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_lshr_b32 s3, s2, 16
s_and_b32 s2, s2, 0xffff
s_mul_i32 s15, s15, s3
s_mul_i32 s14, s14, s2
v_add_lshl_u32 v1, s15, v1, 5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add3_u32 v0, s14, v0, v1
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[0:1]
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_f32_e32 v2, v2, v3
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10matrix_addPKfS0_Pf
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10matrix_addPKfS0_Pf, .Lfunc_end0-_Z10matrix_addPKfS0_Pf
; -- End function
.section .AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 188
; NumSgprs: 18
; NumVgprs: 6
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 6
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object ; @__hip_cuid_
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0 ; 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10matrix_addPKfS0_Pf
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z10matrix_addPKfS0_Pf.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
```
| 426 | 2,589 |
5 |
Convert the following CUDA host assembly code to AMD host assembly:
```cudaasm
.file "tmpxft_00124e24_00000000-6_adder.cudafe1.cpp"
.text
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2063:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2063:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%02.0f "
.LC1:
.string "\n"
.text
.globl _Z12print_matrixPKfii
.type _Z12print_matrixPKfii, @function
_Z12print_matrixPKfii:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $40, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 16(%rsp)
testl %edx, %edx
je .L3
movl %esi, %r15d
movslq %edx, %rax
movq %rax, 8(%rsp)
movl $0, %r14d
movl $0, %r13d
movslq %esi, %rax
movq %rax, 24(%rsp)
leaq .LC0(%rip), %r12
jmp .L5
.L7:
movslq %r14d, %rax
movq 16(%rsp), %rcx
leaq (%rcx,%rax,4), %rbx
movq 24(%rsp), %rdx
addq %rdx, %rax
leaq (%rcx,%rax,4), %rbp
.L6:
pxor %xmm0, %xmm0
cvtss2sd (%rbx), %xmm0
movq %r12, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %rbp, %rbx
jne .L6
.L8:
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $1, %r13
addl %r15d, %r14d
movq 8(%rsp), %rax
cmpq %rax, %r13
je .L3
.L5:
testl %r15d, %r15d
jne .L7
jmp .L8
.L3:
addq $40, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size _Z12print_matrixPKfii, .-_Z12print_matrixPKfii
.globl _Z15create_matrix_dPPfii
.type _Z15create_matrix_dPPfii, @function
_Z15create_matrix_dPPfii:
.LFB2058:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
movq %rdi, %rbp
imull %edx, %esi
movslq %esi, %rbx
salq $2, %rbx
movq %rbx, %rsi
call cudaMalloc@PLT
movq 0(%rbp), %rdi
movq %rbx, %rdx
movl $0, %esi
call cudaMemset@PLT
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size _Z15create_matrix_dPPfii, .-_Z15create_matrix_dPPfii
.globl _Z15create_matrix_hPPfii
.type _Z15create_matrix_hPPfii, @function
_Z15create_matrix_hPPfii:
.LFB2059:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
movq %rdi, %rbp
imull %edx, %esi
movslq %esi, %rbx
salq $2, %rbx
movq %rbx, %rdi
call malloc@PLT
movq %rax, %rdi
movq %rax, 0(%rbp)
movq %rbx, %rcx
movq %rbx, %rdx
movl $0, %esi
call __memset_chk@PLT
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2059:
.size _Z15create_matrix_hPPfii, .-_Z15create_matrix_hPPfii
.globl _Z36__device_stub__Z10matrix_addPKfS0_PfPKfS0_Pf
.type _Z36__device_stub__Z10matrix_addPKfS0_PfPKfS0_Pf, @function
_Z36__device_stub__Z10matrix_addPKfS0_PfPKfS0_Pf:
.LFB2085:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L19
.L15:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L20
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z10matrix_addPKfS0_Pf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L15
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2085:
.size _Z36__device_stub__Z10matrix_addPKfS0_PfPKfS0_Pf, .-_Z36__device_stub__Z10matrix_addPKfS0_PfPKfS0_Pf
.globl _Z10matrix_addPKfS0_Pf
.type _Z10matrix_addPKfS0_Pf, @function
_Z10matrix_addPKfS0_Pf:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z36__device_stub__Z10matrix_addPKfS0_PfPKfS0_Pf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _Z10matrix_addPKfS0_Pf, .-_Z10matrix_addPKfS0_Pf
.section .rodata.str1.1
.LC3:
.string "first matrix\n"
.LC4:
.string "second matrix\n"
.LC5:
.string "resultant matrix\n"
.text
.globl main
.type main, @function
main:
.LFB2060:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $80, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movq %rsp, %rdi
movl $32, %edx
movl $32, %esi
call _Z15create_matrix_hPPfii
leaq 8(%rsp), %rdi
movl $32, %edx
movl $32, %esi
call _Z15create_matrix_hPPfii
leaq 16(%rsp), %rdi
movl $32, %edx
movl $32, %esi
call _Z15create_matrix_hPPfii
leaq 24(%rsp), %rdi
movl $32, %edx
movl $32, %esi
call _Z15create_matrix_dPPfii
leaq 32(%rsp), %rdi
movl $32, %edx
movl $32, %esi
call _Z15create_matrix_dPPfii
leaq 40(%rsp), %rdi
movl $32, %edx
movl $32, %esi
call _Z15create_matrix_dPPfii
movq (%rsp), %rbp
movq 8(%rsp), %rbx
movq %rbp, %rdi
movq %rbx, %rsi
movl $0, %ecx
movss .LC2(%rip), %xmm1
.L24:
movl $0, %eax
.L25:
leal (%rcx,%rax), %edx
pxor %xmm0, %xmm0
cvtsi2ssl %edx, %xmm0
movss %xmm0, (%rdi,%rax,4)
movss %xmm1, (%rsi,%rax,4)
addq $1, %rax
cmpq $32, %rax
jne .L25
addl $32, %ecx
subq $-128, %rdi
subq $-128, %rsi
cmpl $1024, %ecx
jne .L24
movl $1, %ecx
movl $4096, %edx
movq %rbp, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $4096, %edx
movq %rbx, %rsi
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
movl $8, 48(%rsp)
movl $8, 52(%rsp)
movl $4, 60(%rsp)
movl $4, 64(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 48(%rsp), %rdx
movl $1, %ecx
movq 60(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L31
.L27:
movq 16(%rsp), %r12
movl $2, %ecx
movl $4096, %edx
movq 40(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $32, %edx
movl $32, %esi
movq %rbp, %rdi
call _Z12print_matrixPKfii
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $32, %edx
movl $32, %esi
movq %rbx, %rdi
call _Z12print_matrixPKfii
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $32, %edx
movl $32, %esi
movq %r12, %rdi
call _Z12print_matrixPKfii
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L32
movl $0, %eax
addq $80, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L31:
.cfi_restore_state
movq 40(%rsp), %rdx
movq 32(%rsp), %rsi
movq 24(%rsp), %rdi
call _Z36__device_stub__Z10matrix_addPKfS0_PfPKfS0_Pf
jmp .L27
.L32:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2060:
.size main, .-main
.section .rodata.str1.1
.LC6:
.string "_Z10matrix_addPKfS0_Pf"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2088:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _Z10matrix_addPKfS0_Pf(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2088:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC2:
.long 1065353216
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
```
|
```amdasm
.text
.file "adder.hip"
.globl _Z25__device_stub__matrix_addPKfS0_Pf # -- Begin function _Z25__device_stub__matrix_addPKfS0_Pf
.type _Z25__device_stub__matrix_addPKfS0_Pf,@function
_Z25__device_stub__matrix_addPKfS0_Pf: # @_Z25__device_stub__matrix_addPKfS0_Pf
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $112, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 40(%rsp), %rax
movq %rdi, (%rax)
leaq 32(%rsp), %rcx
movq %rsi, (%rcx)
leaq 24(%rsp), %rsi
movq %rdx, (%rsi)
leaq 80(%rsp), %rbx
movq %rax, (%rbx)
movq %rcx, 8(%rbx)
movq %rsi, 16(%rbx)
leaq 64(%rsp), %r14
leaq 48(%rsp), %r15
leaq 16(%rsp), %r12
leaq 8(%rsp), %r13
movq %r14, %rdi
movq %r15, %rsi
movq %r12, %rdx
movq %r13, %rcx
callq __hipPopCallConfiguration
movq (%r14), %rsi
movl 8(%r14), %edx
movq (%r15), %rcx
movl 8(%r15), %r8d
movl $_Z10matrix_addPKfS0_Pf, %edi
movq %rbx, %r9
pushq (%r13)
.cfi_adjust_cfa_offset 8
pushq (%r12)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $128, %rsp
.cfi_adjust_cfa_offset -128
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z25__device_stub__matrix_addPKfS0_Pf, .Lfunc_end0-_Z25__device_stub__matrix_addPKfS0_Pf
.cfi_endproc
# -- End function
.globl _Z12print_matrixPKfii # -- Begin function _Z12print_matrixPKfii
.type _Z12print_matrixPKfii,@function
_Z12print_matrixPKfii: # @_Z12print_matrixPKfii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
pushq %rax
.cfi_def_cfa_offset 64
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %esi, 4(%rsp) # 4-byte Spill
testl %edx, %edx
je .LBB1_6
# %bb.1: # %.preheader.lr.ph
movq %rdi, %r14
movslq 4(%rsp), %r15 # 4-byte Folded Reload
movl %edx, %r12d
movl %r15d, %r13d
shlq $2, %r15
xorl %ebp, %ebp
.LBB1_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB1_4 Depth 2
cmpl $0, 4(%rsp) # 4-byte Folded Reload
je .LBB1_5
# %bb.3: # %.lr.ph
# in Loop: Header=BB1_2 Depth=1
xorl %ebx, %ebx
.LBB1_4: # Parent Loop BB1_2 Depth=1
# => This Inner Loop Header: Depth=2
xorps %xmm0, %xmm0
cvtss2sd (%r14,%rbx,4), %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
incq %rbx
cmpq %rbx, %r13
jne .LBB1_4
.LBB1_5: # %._crit_edge
# in Loop: Header=BB1_2 Depth=1
movl $10, %edi
callq putchar@PLT
incq %rbp
addq %r15, %r14
cmpq %r12, %rbp
jne .LBB1_2
.LBB1_6: # %._crit_edge16
addq $8, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z12print_matrixPKfii, .Lfunc_end1-_Z12print_matrixPKfii
.cfi_endproc
# -- End function
.globl _Z15create_matrix_dPPfii # -- Begin function _Z15create_matrix_dPPfii
.type _Z15create_matrix_dPPfii,@function
_Z15create_matrix_dPPfii: # @_Z15create_matrix_dPPfii
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
pushq %rax
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movq %rdi, %rbx
imull %edx, %esi
movslq %esi, %r14
shlq $2, %r14
movq %r14, %rsi
callq hipMalloc
movq (%rbx), %rdi
xorl %esi, %esi
movq %r14, %rdx
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
jmp hipMemset # TAILCALL
.Lfunc_end2:
.size _Z15create_matrix_dPPfii, .Lfunc_end2-_Z15create_matrix_dPPfii
.cfi_endproc
# -- End function
.globl _Z15create_matrix_hPPfii # -- Begin function _Z15create_matrix_hPPfii
.type _Z15create_matrix_hPPfii,@function
_Z15create_matrix_hPPfii: # @_Z15create_matrix_hPPfii
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
movq %rdi, %rbx
imull %edx, %esi
movslq %esi, %rsi
shlq $2, %rsi
movl $1, %edi
callq calloc@PLT
movq %rax, (%rbx)
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size _Z15create_matrix_hPPfii, .Lfunc_end3-_Z15create_matrix_hPPfii
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $32, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $1, %edi
movl $4096, %esi # imm = 0x1000
callq calloc@PLT
movq %rax, %r15
movl $1, %edi
movl $4096, %esi # imm = 0x1000
callq calloc@PLT
movq %rax, %r14
movl $1, %edi
movl $4096, %esi # imm = 0x1000
callq calloc@PLT
movq %rax, %rbx
leaq 24(%rsp), %r12
movl $4096, %esi # imm = 0x1000
movq %r12, %rdi
callq hipMalloc
movq (%r12), %rdi
xorl %r13d, %r13d
movl $4096, %edx # imm = 0x1000
xorl %esi, %esi
callq hipMemset
leaq 16(%rsp), %r12
movl $4096, %esi # imm = 0x1000
movq %r12, %rdi
callq hipMalloc
movq (%r12), %rdi
movl $4096, %edx # imm = 0x1000
xorl %esi, %esi
callq hipMemset
leaq 8(%rsp), %r12
movl $4096, %esi # imm = 0x1000
movq %r12, %rdi
callq hipMalloc
movq (%r12), %rdi
movl $4096, %edx # imm = 0x1000
xorl %esi, %esi
callq hipMemset
xorl %eax, %eax
.LBB4_1: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB4_2 Depth 2
movl $32, %ecx
movq %r13, %rdx
.LBB4_2: # Parent Loop BB4_1 Depth=1
# => This Inner Loop Header: Depth=2
xorps %xmm0, %xmm0
cvtsi2ss %edx, %xmm0
movss %xmm0, (%r15,%rdx,4)
movl $1065353216, (%r14,%rdx,4) # imm = 0x3F800000
incq %rdx
decq %rcx
jne .LBB4_2
# %bb.3: # in Loop: Header=BB4_1 Depth=1
incq %rax
addq $32, %r13
cmpq $32, %rax
jne .LBB4_1
# %bb.4:
movq 24(%rsp), %rdi
movl $4096, %edx # imm = 0x1000
movq %r15, %rsi
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
movl $4096, %edx # imm = 0x1000
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $17179869188, %rdi # imm = 0x400000004
movabsq $34359738376, %rdx # imm = 0x800000008
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_6
# %bb.5:
movq 24(%rsp), %rdi
movq 16(%rsp), %rsi
movq 8(%rsp), %rdx
callq _Z25__device_stub__matrix_addPKfS0_Pf
.LBB4_6:
movq 8(%rsp), %rsi
movl $4096, %edx # imm = 0x1000
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movl $.Lstr, %edi
callq puts@PLT
movq %r15, %rdi
movl $32, %esi
movl $32, %edx
callq _Z12print_matrixPKfii
movl $.Lstr.1, %edi
callq puts@PLT
movq %r14, %rdi
movl $32, %esi
movl $32, %edx
callq _Z12print_matrixPKfii
movl $.Lstr.2, %edi
callq puts@PLT
movq %rbx, %rdi
movl $32, %esi
movl $32, %edx
callq _Z12print_matrixPKfii
xorl %eax, %eax
addq $32, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end4:
.size main, .Lfunc_end4-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
jne .LBB5_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, %rdi
movq %rax, __hip_gpubin_handle(%rip)
.LBB5_2:
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10matrix_addPKfS0_Pf, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end5:
.size __hip_module_ctor, .Lfunc_end5-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB6_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB6_2:
retq
.Lfunc_end6:
.size __hip_module_dtor, .Lfunc_end6-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10matrix_addPKfS0_Pf,@object # @_Z10matrix_addPKfS0_Pf
.section .rodata,"a",@progbits
.globl _Z10matrix_addPKfS0_Pf
.p2align 3, 0x0
_Z10matrix_addPKfS0_Pf:
.quad _Z25__device_stub__matrix_addPKfS0_Pf
.size _Z10matrix_addPKfS0_Pf, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%02.0f "
.size .L.str, 8
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z10matrix_addPKfS0_Pf"
.size .L__unnamed_1, 23
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "first matrix"
.size .Lstr, 13
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "second matrix"
.size .Lstr.1, 14
.type .Lstr.2,@object # @str.2
.Lstr.2:
.asciz "resultant matrix"
.size .Lstr.2, 17
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__matrix_addPKfS0_Pf
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10matrix_addPKfS0_Pf
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
```
| 5,103 | 5,531 |
8 |
Convert the following CUDA device assembly code to AMD device assembly:
```cudaasm
code for sm_80
Function : kernel
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ;
IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x16c] ;
ULDC.64 UR4, c[0x0][0x118] ;
IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x168] ;
LDG.E R3, [R2.64] ;
BSSY B0, 0x1c0 ;
S2R R5, SR_CTAID.X ;
S2R R4, SR_TID.X ;
S2R R6, SR_CTAID.Y ;
S2R R11, SR_TID.Y ;
IMAD R5, R5, c[0x0][0x0], R4 ;
I2F.U32 R4, R5 ;
IMAD R2, R6, c[0x0][0x4], R11 ;
I2F R7, R3 ;
MUFU.RCP R0, R7 ;
FCHK P0, R4, R7 ;
FFMA R9, -R7, R0, 1 ;
FFMA R9, R0, R9, R0 ;
IMAD R0, R2, R3, R5 ;
FFMA R6, R4, R9, RZ ;
IMAD R0, R0, 0x3, RZ ;
FFMA R3, -R7, R6, R4 ;
FFMA R3, R9, R3, R6 ;
@!P0 BRA 0x1b0 ;
IMAD.MOV.U32 R8, RZ, RZ, R4 ;
MOV R4, 0x1b0 ;
CALL.REL.NOINC 0x570 ;
BSYNC B0 ;
IMAD.MOV.U32 R6, RZ, RZ, c[0x0][0x170] ;
IMAD.MOV.U32 R7, RZ, RZ, c[0x0][0x174] ;
IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x17c] ;
LDG.E R6, [R6.64] ;
IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x178] ;
LDG.E R5, [R4.64] ;
BSSY B0, 0x350 ;
I2F R9, R6 ;
IMAD.IADD R8, R2, 0x1, R5 ;
HFMA2.MMA R2, -RZ, RZ, 2.15625, 0 ;
I2F.U32 R8, R8 ;
FFMA R2, R3, R2, -2 ;
MUFU.RCP R10, R9 ;
FCHK P0, R8, R9 ;
FFMA R11, -R9, R10, 1 ;
FFMA R11, R10, R11, R10 ;
FFMA R10, R8, R11, RZ ;
FFMA R7, -R9, R10, R8 ;
FFMA R7, R11, R7, R10 ;
@!P0 BRA 0x340 ;
IMAD.MOV.U32 R7, RZ, RZ, R9 ;
MOV R4, 0x330 ;
CALL.REL.NOINC 0x570 ;
IMAD.MOV.U32 R7, RZ, RZ, R3 ;
BSYNC B0 ;
IMAD.MOV.U32 R6, RZ, RZ, 0x40200000 ;
BSSY B0, 0x470 ;
IMAD.MOV.U32 R3, RZ, RZ, RZ ;
CS2R R4, SRZ ;
FFMA R8, R7, R6, -1.25 ;
CS2R R6, SRZ ;
FADD R3, -R6, R3 ;
IADD3 R4, R4, 0x1, RZ ;
FADD R6, R7, R7 ;
FADD R7, R2, R3 ;
ISETP.GE.U32.AND P0, PT, R4, 0x100, PT ;
FFMA R5, R6, R5, R8 ;
FMUL R3, R7, R7 ;
FMUL R6, R5, R5 ;
FADD R9, R6, R3 ;
FSETP.LE.AND P1, PT, R9, 4, PT ;
@!P0 BRA P1, 0x3b0 ;
BSYNC B0 ;
IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x184] ;
IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x180] ;
LDG.E R3, [R2.64] ;
ISETP.GE.AND P0, PT, R0, R3, PT ;
@P0 EXIT ;
ISETP.NE.AND P0, PT, R4, 0x100, PT ;
IADD3 R2, P1, R0, c[0x0][0x160], RZ ;
LEA.HI.X.SX32 R3, R0, c[0x0][0x164], 0x1, P1 ;
STG.E.U8 [R2.64], RZ ;
@P0 STG.E.U8 [R2.64+0x1], R4 ;
@P0 STG.E.U8 [R2.64+0x2], RZ ;
@P0 EXIT ;
MOV R0, 0x1 ;
STG.E.U8 [R2.64+0x2], RZ ;
STG.E.U8 [R2.64+0x1], R0 ;
EXIT ;
SHF.R.U32.HI R5, RZ, 0x17, R7.reuse ;
BSSY B1, 0xbd0 ;
SHF.R.U32.HI R3, RZ, 0x17, R8 ;
IMAD.MOV.U32 R6, RZ, RZ, R7 ;
LOP3.LUT R11, R5, 0xff, RZ, 0xc0, !PT ;
LOP3.LUT R9, R3, 0xff, RZ, 0xc0, !PT ;
IMAD.MOV.U32 R3, RZ, RZ, R8 ;
IADD3 R12, R11, -0x1, RZ ;
IADD3 R10, R9, -0x1, RZ ;
ISETP.GT.U32.AND P0, PT, R12, 0xfd, PT ;
ISETP.GT.U32.OR P0, PT, R10, 0xfd, P0 ;
@!P0 IMAD.MOV.U32 R5, RZ, RZ, RZ ;
@!P0 BRA 0x7b0 ;
FSETP.GTU.FTZ.AND P0, PT, |R8|, +INF , PT ;
FSETP.GTU.FTZ.AND P1, PT, |R7|, +INF , PT ;
PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ;
@P0 BRA 0xbb0 ;
LOP3.LUT P0, RZ, R6, 0x7fffffff, R3, 0xc8, !PT ;
@!P0 BRA 0xb90 ;
FSETP.NEU.FTZ.AND P2, PT, |R8|.reuse, +INF , PT ;
FSETP.NEU.FTZ.AND P1, PT, |R7|, +INF , PT ;
FSETP.NEU.FTZ.AND P0, PT, |R8|, +INF , PT ;
@!P1 BRA !P2, 0xb90 ;
LOP3.LUT P2, RZ, R3, 0x7fffffff, RZ, 0xc0, !PT ;
PLOP3.LUT P1, PT, P1, P2, PT, 0x2a, 0x0 ;
@P1 BRA 0xb70 ;
LOP3.LUT P1, RZ, R6, 0x7fffffff, RZ, 0xc0, !PT ;
PLOP3.LUT P0, PT, P0, P1, PT, 0x2a, 0x0 ;
@P0 BRA 0xb40 ;
ISETP.GE.AND P0, PT, R10, RZ, PT ;
ISETP.GE.AND P1, PT, R12, RZ, PT ;
@P0 IMAD.MOV.U32 R5, RZ, RZ, RZ ;
@!P0 IMAD.MOV.U32 R5, RZ, RZ, -0x40 ;
@!P0 FFMA R3, R8, 1.84467440737095516160e+19, RZ ;
@!P1 FFMA R6, R7, 1.84467440737095516160e+19, RZ ;
@!P1 IADD3 R5, R5, 0x40, RZ ;
LEA R7, R11, 0xc0800000, 0x17 ;
BSSY B2, 0xb30 ;
IMAD.IADD R7, R6, 0x1, -R7 ;
IADD3 R6, R9, -0x7f, RZ ;
MUFU.RCP R8, R7 ;
FADD.FTZ R10, -R7, -RZ ;
IMAD R3, R6, -0x800000, R3 ;
FFMA R9, R8, R10, 1 ;
FFMA R12, R8, R9, R8 ;
FFMA R8, R3, R12, RZ ;
FFMA R9, R10, R8, R3 ;
FFMA R9, R12, R9, R8 ;
IADD3 R8, R6, 0x7f, -R11 ;
FFMA R10, R10, R9, R3 ;
IADD3 R8, R8, R5, RZ ;
FFMA R3, R12, R10, R9 ;
SHF.R.U32.HI R6, RZ, 0x17, R3 ;
LOP3.LUT R6, R6, 0xff, RZ, 0xc0, !PT ;
IMAD.IADD R11, R6, 0x1, R8 ;
IADD3 R5, R11, -0x1, RZ ;
ISETP.GE.U32.AND P0, PT, R5, 0xfe, PT ;
@!P0 BRA 0xb10 ;
ISETP.GT.AND P0, PT, R11, 0xfe, PT ;
@P0 BRA 0xae0 ;
ISETP.GE.AND P0, PT, R11, 0x1, PT ;
@P0 BRA 0xb20 ;
ISETP.GE.AND P0, PT, R11, -0x18, PT ;
LOP3.LUT R3, R3, 0x80000000, RZ, 0xc0, !PT ;
@!P0 BRA 0xb20 ;
FFMA.RZ R5, R12.reuse, R10.reuse, R9.reuse ;
IADD3 R8, R11.reuse, 0x20, RZ ;
FFMA.RM R6, R12.reuse, R10.reuse, R9.reuse ;
ISETP.NE.AND P2, PT, R11, RZ, PT ;
LOP3.LUT R7, R5, 0x7fffff, RZ, 0xc0, !PT ;
FFMA.RP R5, R12, R10, R9 ;
ISETP.NE.AND P1, PT, R11, RZ, PT ;
IMAD.MOV R9, RZ, RZ, -R11 ;
LOP3.LUT R7, R7, 0x800000, RZ, 0xfc, !PT ;
FSETP.NEU.FTZ.AND P0, PT, R5, R6, PT ;
SHF.L.U32 R8, R7, R8, RZ ;
SEL R6, R9, RZ, P2 ;
ISETP.NE.AND P1, PT, R8, RZ, P1 ;
SHF.R.U32.HI R6, RZ, R6, R7 ;
PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ;
SHF.R.U32.HI R8, RZ, 0x1, R6 ;
SEL R5, RZ, 0x1, !P0 ;
LOP3.LUT R5, R5, 0x1, R8, 0xf8, !PT ;
LOP3.LUT R5, R5, R6, RZ, 0xc0, !PT ;
IMAD.IADD R8, R8, 0x1, R5 ;
LOP3.LUT R3, R8, R3, RZ, 0xfc, !PT ;
BRA 0xb20 ;
LOP3.LUT R3, R3, 0x80000000, RZ, 0xc0, !PT ;
LOP3.LUT R3, R3, 0x7f800000, RZ, 0xfc, !PT ;
BRA 0xb20 ;
IMAD R3, R8, 0x800000, R3 ;
BSYNC B2 ;
BRA 0xbc0 ;
LOP3.LUT R3, R6, 0x80000000, R3, 0x48, !PT ;
LOP3.LUT R3, R3, 0x7f800000, RZ, 0xfc, !PT ;
BRA 0xbc0 ;
LOP3.LUT R3, R6, 0x80000000, R3, 0x48, !PT ;
BRA 0xbc0 ;
MUFU.RSQ R3, -QNAN ;
BRA 0xbc0 ;
FADD.FTZ R3, R8, R7 ;
BSYNC B1 ;
IMAD.MOV.U32 R5, RZ, RZ, 0x0 ;
RET.REL.NODEC R4 0x0 ;
BRA 0xbf0;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
```
|
```amdasm
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected kernel ; -- Begin function kernel
.globl kernel
.p2align 8
.type kernel,@function
kernel: ; @kernel
; %bb.0:
s_clause 0x1
s_load_b256 s[4:11], s[0:1], 0x0
s_load_b32 s2, s[0:1], 0x34
v_bfe_u32 v2, v0, 10, 10
v_and_b32_e32 v3, 0x3ff, v0
s_load_b64 s[0:1], s[0:1], 0x20
s_waitcnt lgkmcnt(0)
s_load_b32 s10, s[10:11], 0x0
s_load_b32 s3, s[6:7], 0x0
s_load_b32 s6, s[8:9], 0x0
s_lshr_b32 s7, s2, 16
s_and_b32 s2, s2, 0xffff
v_mad_u64_u32 v[0:1], null, s15, s7, v[2:3]
v_mad_u64_u32 v[1:2], null, s14, s2, v[3:4]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_cvt_f32_u32_e32 v3, v1
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v2, s10, v0
v_cvt_f32_i32_e32 v4, s3
v_cvt_f32_i32_e32 v5, s6
s_mov_b32 s6, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cvt_f32_u32_e32 v2, v2
v_div_scale_f32 v6, null, v4, v4, v3
v_div_scale_f32 v12, vcc_lo, v3, v4, v3
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_div_scale_f32 v7, null, v5, v5, v2
v_rcp_f32_e32 v8, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_rcp_f32_e32 v9, v7
s_waitcnt_depctr 0xfff
v_fma_f32 v10, -v6, v8, 1.0
v_fma_f32 v11, -v7, v9, 1.0
v_dual_fmac_f32 v9, v11, v9 :: v_dual_fmac_f32 v8, v10, v8
v_div_scale_f32 v10, s2, v2, v5, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v13, v10, v9
v_fma_f32 v15, -v7, v13, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_fmac_f32_e32 v13, v15, v9
v_mul_f32_e32 v11, v12, v8
v_fma_f32 v7, -v7, v13, v10
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v14, -v6, v11, v12
v_fmac_f32_e32 v11, v14, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v6, -v6, v11, v12
v_div_fmas_f32 v6, v6, v8, v11
s_mov_b32 vcc_lo, s2
s_mov_b32 s2, 0x40200000
v_div_fmas_f32 v7, v7, v9, v13
v_mov_b32_e32 v9, -2.0
v_div_fixup_f32 v3, v6, v4, v3
v_mov_b32_e32 v6, 0
v_mov_b32_e32 v8, 0
v_div_fixup_f32 v4, v7, v5, v2
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
v_dual_mov_b32 v7, 0 :: v_dual_fmamk_f32 v2, v3, 0x40500000, v9
v_dual_fmaak_f32 v3, s2, v4, 0xbfa00000 :: v_dual_mov_b32 v4, 0
s_mov_b32 s2, 0
.LBB0_1: ; =>This Inner Loop Header: Depth=1
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_dual_sub_f32 v5, v6, v7 :: v_dual_add_f32 v6, v8, v8
s_add_i32 s7, s6, 1
s_cmpk_gt_u32 s6, 0xfe
s_cselect_b32 s6, -1, 0
v_add_f32_e32 v8, v2, v5
v_fma_f32 v4, v4, v6, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_f32_e32 v6, v8, v8
v_mul_f32_e32 v7, v4, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v5, v4, v4, v6
v_cmp_nge_f32_e32 vcc_lo, 4.0, v5
v_mov_b32_e32 v5, s7
s_or_b32 s6, vcc_lo, s6
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s6, exec_lo, s6
s_or_b32 s2, s6, s2
s_mov_b32 s6, s7
s_and_not1_b32 exec_lo, exec_lo, s2
s_cbranch_execnz .LBB0_1
; %bb.2:
s_or_b32 exec_lo, exec_lo, s2
s_load_b32 s0, s[0:1], 0x0
v_mad_u64_u32 v[2:3], null, v0, s3, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshl_add_u32 v0, v2, 1, v2
s_waitcnt lgkmcnt(0)
v_cmp_gt_i32_e32 vcc_lo, s0, v0
s_and_saveexec_b32 s0, vcc_lo
; %bb.3: ; %.sink.split
v_cmp_ne_u32_e32 vcc_lo, 0x100, v5
v_ashrrev_i32_e32 v1, 31, v0
v_dual_mov_b32 v3, 0 :: v_dual_cndmask_b32 v2, 1, v5
v_add_co_u32 v0, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
v_lshlrev_b16 v2, 8, v2
s_clause 0x1
global_store_b8 v[0:1], v3, off offset:2
global_store_b16 v[0:1], v2, off
; %bb.4:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel kernel
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 16
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size kernel, .Lfunc_end0-kernel
; -- End function
.section .AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 580
; NumSgprs: 18
; NumVgprs: 16
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 16
; Occupancy: 16
; WaveLimiterHint : 1
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object ; @__hip_cuid_
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0 ; 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: kernel
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: kernel.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 16
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
```
| 3,587 | 4,111 |
9 |
Convert the following CUDA host assembly code to AMD host assembly:
```cudaasm
.file "tmpxft_001780a1_00000000-6_mandel_brot_kernel.cudafe1.cpp"
.text
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z36__device_stub__Z6kernelPcPiS0_S0_S0_PcPiS0_S0_S0_
.type _Z36__device_stub__Z6kernelPcPiS0_S0_S0_PcPiS0_S0_S0_, @function
_Z36__device_stub__Z6kernelPcPiS0_S0_S0_PcPiS0_S0_S0_:
.LFB2051:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movq %r8, 8(%rsp)
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 184
pushq 56(%rsp)
.cfi_def_cfa_offset 192
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq kernel(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z36__device_stub__Z6kernelPcPiS0_S0_S0_PcPiS0_S0_S0_, .-_Z36__device_stub__Z6kernelPcPiS0_S0_S0_PcPiS0_S0_S0_
.globl kernel
.type kernel, @function
kernel:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z36__device_stub__Z6kernelPcPiS0_S0_S0_PcPiS0_S0_S0_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size kernel, .-kernel
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "kernel"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq kernel(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
```
|
```amdasm
.text
.file "mandel_brot_kernel.hip"
.globl __device_stub__kernel # -- Begin function __device_stub__kernel
.type __device_stub__kernel,@function
__device_stub__kernel: # @__device_stub__kernel
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $144, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 56(%rsp), %rax
movq %rdi, (%rax)
leaq 48(%rsp), %rdi
movq %rsi, (%rdi)
leaq 40(%rsp), %rsi
movq %rdx, (%rsi)
leaq 32(%rsp), %rdx
movq %rcx, (%rdx)
leaq 24(%rsp), %rcx
movq %r8, (%rcx)
leaq 96(%rsp), %rbx
movq %rax, (%rbx)
movq %rdi, 8(%rbx)
movq %rsi, 16(%rbx)
movq %rdx, 24(%rbx)
movq %rcx, 32(%rbx)
leaq 80(%rsp), %r14
leaq 64(%rsp), %r15
leaq 16(%rsp), %r12
leaq 8(%rsp), %r13
movq %r14, %rdi
movq %r15, %rsi
movq %r12, %rdx
movq %r13, %rcx
callq __hipPopCallConfiguration
movq (%r14), %rsi
movl 8(%r14), %edx
movq (%r15), %rcx
movl 8(%r15), %r8d
movl $kernel, %edi
movq %rbx, %r9
pushq (%r13)
.cfi_adjust_cfa_offset 8
pushq (%r12)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $160, %rsp
.cfi_adjust_cfa_offset -160
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size __device_stub__kernel, .Lfunc_end0-__device_stub__kernel
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, %rdi
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $kernel, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type kernel,@object # @kernel
.section .rodata,"a",@progbits
.globl kernel
.p2align 3, 0x0
kernel:
.quad __device_stub__kernel
.size kernel, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "kernel"
.size .L__unnamed_1, 7
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __device_stub__kernel
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym kernel
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
```
| 1,915 | 1,961 |
10 |
Convert the following CUDA device assembly code to AMD device assembly:
```cudaasm
code for sm_80
Function : _Z10kernel_addPKfS0_iPf
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
MOV R1, c[0x0][0x28] ;
S2R R0, SR_CTAID.X ;
S2R R3, SR_TID.X ;
IMAD R0, R0, c[0x0][0x0], R3 ;
ISETP.GE.AND P0, PT, R0, c[0x0][0x170], PT ;
@P0 EXIT ;
ULDC.64 UR4, c[0x0][0x118] ;
HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ;
IMAD.WIDE R2, R0, R7, c[0x0][0x160] ;
IMAD.WIDE R4, R0.reuse, R7.reuse, c[0x0][0x168] ;
LDG.E R3, [R2.64] ;
LDG.E R4, [R4.64] ;
IMAD.WIDE R6, R0, R7, c[0x0][0x178] ;
MOV R11, c[0x0][0x0] ;
IMAD R0, R11, c[0x0][0xc], R0 ;
ISETP.GE.AND P0, PT, R0, c[0x0][0x170], PT ;
FADD R9, R4, R3 ;
STG.E [R6.64], R9 ;
@!P0 BRA 0x70 ;
EXIT ;
BRA 0x140;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
```
|
```amdasm
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10kernel_addPKfS0_iPf ; -- Begin function _Z10kernel_addPKfS0_iPf
.globl _Z10kernel_addPKfS0_iPf
.p2align 8
.type _Z10kernel_addPKfS0_iPf,@function
_Z10kernel_addPKfS0_iPf: ; @_Z10kernel_addPKfS0_iPf
; %bb.0:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x2c
s_load_b32 s8, s[0:1], 0x10
s_add_u32 s2, s0, 32
s_addc_u32 s3, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s9, s4, 0xffff
s_mov_b32 s4, exec_lo
v_mad_u64_u32 v[1:2], null, s15, s9, v[0:1]
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s8, v1
s_cbranch_execz .LBB0_3
; %bb.1: ; %.lr.ph
s_load_b32 s10, s[2:3], 0x0
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[2:3], s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_mul_i32 s1, s10, s9
s_mov_b32 s9, 0
.LBB0_2: ; =>This Inner Loop Header: Depth=1
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[1:2]
v_add_co_u32 v4, vcc_lo, s4, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v3, vcc_lo
v_add_co_u32 v6, vcc_lo, s6, v2
v_add_co_ci_u32_e32 v7, vcc_lo, s7, v3, vcc_lo
v_add_co_u32 v2, s0, s2, v2
global_load_b32 v0, v[4:5], off
global_load_b32 v4, v[6:7], off
v_add_nc_u32_e32 v1, s1, v1
v_add_co_ci_u32_e64 v3, s0, s3, v3, s0
s_waitcnt vmcnt(0)
v_add_f32_e32 v0, v0, v4
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_cmp_le_i32_e32 vcc_lo, s8, v1
global_store_b32 v[2:3], v0, off
s_or_b32 s9, vcc_lo, s9
s_and_not1_b32 exec_lo, exec_lo, s9
s_cbranch_execnz .LBB0_2
.LBB0_3: ; %Flow21
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10kernel_addPKfS0_iPf
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10kernel_addPKfS0_iPf, .Lfunc_end0-_Z10kernel_addPKfS0_iPf
; -- End function
.section .AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 236
; NumSgprs: 18
; NumVgprs: 8
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 8
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object ; @__hip_cuid_
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0 ; 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10kernel_addPKfS0_iPf
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z10kernel_addPKfS0_iPf.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
```
| 472 | 2,816 |
11 |
Convert the following CUDA host assembly code to AMD host assembly:
```cudaasm
.file "tmpxft_0005fcf2_00000000-6_kernel_add.cudafe1.cpp"
.text
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2032:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2032:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z37__device_stub__Z10kernel_addPKfS0_iPfPKfS0_iPf
.type _Z37__device_stub__Z10kernel_addPKfS0_iPfPKfS0_iPf, @function
_Z37__device_stub__Z10kernel_addPKfS0_iPfPKfS0_iPf:
.LFB2054:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %rcx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z10kernel_addPKfS0_iPf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2054:
.size _Z37__device_stub__Z10kernel_addPKfS0_iPfPKfS0_iPf, .-_Z37__device_stub__Z10kernel_addPKfS0_iPfPKfS0_iPf
.globl _Z10kernel_addPKfS0_iPf
.type _Z10kernel_addPKfS0_iPf, @function
_Z10kernel_addPKfS0_iPf:
.LFB2055:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z37__device_stub__Z10kernel_addPKfS0_iPfPKfS0_iPf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2055:
.size _Z10kernel_addPKfS0_iPf, .-_Z10kernel_addPKfS0_iPf
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z10kernel_addPKfS0_iPf"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2057:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z10kernel_addPKfS0_iPf(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.text
.type _GLOBAL__sub_I__Z37__device_stub__Z10kernel_addPKfS0_iPfPKfS0_iPf, @function
_GLOBAL__sub_I__Z37__device_stub__Z10kernel_addPKfS0_iPfPKfS0_iPf:
.LFB2174:
.cfi_startproc
ret
.cfi_endproc
.LFE2174:
.size _GLOBAL__sub_I__Z37__device_stub__Z10kernel_addPKfS0_iPfPKfS0_iPf, .-_GLOBAL__sub_I__Z37__device_stub__Z10kernel_addPKfS0_iPfPKfS0_iPf
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
```
|
```amdasm
.text
.file "kernel_add.hip"
.globl _Z25__device_stub__kernel_addPKfS0_iPf # -- Begin function _Z25__device_stub__kernel_addPKfS0_iPf
.type _Z25__device_stub__kernel_addPKfS0_iPf,@function
_Z25__device_stub__kernel_addPKfS0_iPf: # @_Z25__device_stub__kernel_addPKfS0_iPf
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $112, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 40(%rsp), %rax
movq %rdi, (%rax)
leaq 32(%rsp), %rdi
movq %rsi, (%rdi)
leaq 4(%rsp), %rsi
movl %edx, (%rsi)
leaq 24(%rsp), %rdx
movq %rcx, (%rdx)
leaq 80(%rsp), %rbx
movq %rax, (%rbx)
movq %rdi, 8(%rbx)
movq %rsi, 16(%rbx)
movq %rdx, 24(%rbx)
leaq 64(%rsp), %r14
leaq 48(%rsp), %r15
leaq 16(%rsp), %r12
leaq 8(%rsp), %r13
movq %r14, %rdi
movq %r15, %rsi
movq %r12, %rdx
movq %r13, %rcx
callq __hipPopCallConfiguration
movq (%r14), %rsi
movl 8(%r14), %edx
movq (%r15), %rcx
movl 8(%r15), %r8d
movl $_Z10kernel_addPKfS0_iPf, %edi
movq %rbx, %r9
pushq (%r13)
.cfi_adjust_cfa_offset 8
pushq (%r12)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $128, %rsp
.cfi_adjust_cfa_offset -128
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z25__device_stub__kernel_addPKfS0_iPf, .Lfunc_end0-_Z25__device_stub__kernel_addPKfS0_iPf
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, %rdi
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10kernel_addPKfS0_iPf, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10kernel_addPKfS0_iPf,@object # @_Z10kernel_addPKfS0_iPf
.section .rodata,"a",@progbits
.globl _Z10kernel_addPKfS0_iPf
.p2align 3, 0x0
_Z10kernel_addPKfS0_iPf:
.quad _Z25__device_stub__kernel_addPKfS0_iPf
.size _Z10kernel_addPKfS0_iPf, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z10kernel_addPKfS0_iPf"
.size .L__unnamed_1, 24
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__kernel_addPKfS0_iPf
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10kernel_addPKfS0_iPf
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
```
| 2,111 | 2,117 |
12 |
Convert the following CUDA device assembly code to AMD device assembly:
```cudaasm
code for sm_80
Function : _Z20sum_Matrices_columnaPiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ;
S2R R2, SR_CTAID.Y ;
S2R R3, SR_TID.Y ;
IMAD R2, R2, c[0x0][0x4], R3 ;
ISETP.GT.AND P0, PT, R2, 0x4, PT ;
@P0 EXIT ;
S2R R3, SR_CTAID.X ;
IADD3 R4, -R2.reuse, 0x1, RZ ;
ULDC.64 UR4, c[0x0][0x118] ;
IADD3 R5, -R2, 0x4, RZ ;
S2R R0, SR_TID.X ;
LOP3.LUT P1, R10, R4, 0x3, RZ, 0xc0, !PT ;
BSSY B0, 0x2f0 ;
ISETP.GE.U32.AND P0, PT, R5, 0x3, PT ;
@!P1 BRA 0x2e0 ;
IMAD R5, R3, c[0x0][0x0], R0 ;
IMAD.MOV.U32 R9, RZ, RZ, 0x4 ;
IMAD R8, R2, 0x5, R5 ;
IMAD.WIDE R4, R8, R9, c[0x0][0x170] ;
IMAD.WIDE R6, R8, R9, c[0x0][0x168] ;
MOV R14, R4 ;
IMAD.WIDE R8, R8, R9, c[0x0][0x160] ;
MOV R13, R7 ;
IMAD.MOV.U32 R15, RZ, RZ, R5 ;
IMAD.MOV.U32 R12, RZ, RZ, R6 ;
IMAD.MOV.U32 R11, RZ, RZ, R9 ;
MOV R4, R12 ;
IMAD.MOV.U32 R7, RZ, RZ, R11 ;
MOV R6, R8 ;
IMAD.MOV.U32 R5, RZ, RZ, R13 ;
LDG.E R7, [R6.64] ;
LDG.E R4, [R4.64] ;
IADD3 R10, R10, -0x1, RZ ;
MOV R5, R15 ;
ISETP.NE.AND P1, PT, R10, RZ, PT ;
IADD3 R8, P4, R8, 0x14, RZ ;
IADD3 R12, P3, R12, 0x14, RZ ;
IADD3 R2, R2, 0x1, RZ ;
IMAD.X R11, RZ, RZ, R11, P4 ;
IADD3.X R13, RZ, R13, RZ, P3, !PT ;
IADD3 R9, R4, R7, RZ ;
IMAD.MOV.U32 R4, RZ, RZ, R14 ;
STG.E [R4.64], R9 ;
IADD3 R14, P2, R14, 0x14, RZ ;
IMAD.X R15, RZ, RZ, R15, P2 ;
@P1 BRA 0x1a0 ;
BSYNC B0 ;
@!P0 EXIT ;
IMAD R3, R3, c[0x0][0x0], R0 ;
IADD3 R0, R2, -0x4, RZ ;
IMAD R8, R2, 0x5, R3 ;
HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ;
IMAD.WIDE R6, R8, R3, c[0x0][0x168] ;
IMAD.WIDE R4, R8.reuse, R3.reuse, c[0x0][0x160] ;
LDG.E R9, [R6.64] ;
LDG.E R10, [R4.64] ;
IMAD.WIDE R2, R8, R3, c[0x0][0x170] ;
IMAD.IADD R9, R9, 0x1, R10 ;
STG.E [R2.64], R9 ;
LDG.E R10, [R6.64+0x14] ;
LDG.E R11, [R4.64+0x14] ;
IADD3 R11, R10, R11, RZ ;
STG.E [R2.64+0x14], R11 ;
LDG.E R10, [R6.64+0x28] ;
LDG.E R13, [R4.64+0x28] ;
IMAD.IADD R13, R10, 0x1, R13 ;
STG.E [R2.64+0x28], R13 ;
LDG.E R10, [R6.64+0x3c] ;
LDG.E R15, [R4.64+0x3c] ;
IADD3 R0, R0, 0x4, RZ ;
IADD3 R8, R8, 0x14, RZ ;
ISETP.GE.AND P0, PT, R0, 0x1, PT ;
IADD3 R15, R10, R15, RZ ;
STG.E [R2.64+0x3c], R15 ;
@!P0 BRA 0x330 ;
EXIT ;
BRA 0x4c0;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
Function : _Z17sum_Matrices_filaPiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ;
S2R R8, SR_CTAID.X ;
S2R R3, SR_TID.X ;
S2R R9, SR_CTAID.Y ;
S2R R2, SR_TID.Y ;
IMAD R8, R8, c[0x0][0x0], R3 ;
ISETP.GT.AND P0, PT, R8, 0x4, PT ;
@P0 EXIT ;
IADD3 R0, -R8.reuse, 0x1, RZ ;
ULDC.64 UR4, c[0x0][0x118] ;
IADD3 R3, -R8, 0x4, RZ ;
BSSY B0, 0x300 ;
LOP3.LUT P1, R10, R0, 0x3, RZ, 0xc0, !PT ;
IMAD R9, R9, c[0x0][0x4], R2 ;
ISETP.GE.U32.AND P0, PT, R3, 0x3, PT ;
IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x170] ;
@!P1 BRA 0x2f0 ;
HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ;
IMAD R6, R9, 0x5, R8 ;
IMAD.WIDE R2, R6, R7, c[0x0][0x170] ;
IMAD.WIDE R4, R6, R7, c[0x0][0x168] ;
IMAD.WIDE R6, R6, R7, c[0x0][0x160] ;
MOV R12, R4 ;
IMAD.MOV.U32 R14, RZ, RZ, R2 ;
MOV R11, R7 ;
IMAD.MOV.U32 R15, RZ, RZ, R3 ;
IMAD.MOV.U32 R13, RZ, RZ, R5 ;
IMAD.MOV.U32 R2, RZ, RZ, R12 ;
MOV R5, R11 ;
IMAD.MOV.U32 R4, RZ, RZ, R6 ;
MOV R3, R13 ;
LDG.E R5, [R4.64] ;
LDG.E R2, [R2.64] ;
IADD3 R10, R10, -0x1, RZ ;
IMAD.MOV.U32 R3, RZ, RZ, R15 ;
ISETP.NE.AND P1, PT, R10, RZ, PT ;
IADD3 R12, P3, R12, 0x4, RZ ;
IADD3 R6, P4, R6, 0x4, RZ ;
IADD3 R8, R8, 0x1, RZ ;
IMAD.X R13, RZ, RZ, R13, P3 ;
IADD3.X R11, RZ, R11, RZ, P4, !PT ;
IMAD.IADD R7, R2, 0x1, R5 ;
MOV R2, R14 ;
STG.E [R2.64], R7 ;
IADD3 R14, P2, R14, 0x4, RZ ;
IADD3.X R15, RZ, R15, RZ, P2, !PT ;
@P1 BRA 0x1b0 ;
BSYNC B0 ;
IMAD.MOV.U32 R23, RZ, RZ, c[0x0][0x174] ;
MOV R2, c[0x0][0x168] ;
@!P0 EXIT ;
IMAD R9, R9, 0x5, R8 ;
MOV R4, c[0x0][0x160] ;
IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x16c] ;
IADD3 R8, R8, -0x4, RZ ;
IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x164] ;
IADD3 R15, R9, 0x1, RZ ;
IMAD.WIDE R18, R9, 0x4, R2 ;
IMAD.WIDE R6, R9, 0x4, R4 ;
LDG.E R18, [R18.64] ;
LDG.E R11, [R6.64] ;
IMAD.WIDE R12, R15, 0x4, R2 ;
MOV R6, R0 ;
IMAD.MOV.U32 R7, RZ, RZ, R23 ;
IMAD.WIDE R20, R9, 0x4, R6 ;
IADD3 R23, R18, R11, RZ ;
IMAD.WIDE R10, R15.reuse, 0x4, R4 ;
STG.E [R20.64], R23 ;
LDG.E R0, [R12.64] ;
LDG.E R25, [R10.64] ;
IMAD.WIDE R16, R15, 0x4, R6 ;
IMAD.IADD R25, R0, 0x1, R25 ;
STG.E [R16.64], R25 ;
LDG.E R0, [R12.64+0x4] ;
LDG.E R19, [R10.64+0x4] ;
IADD3 R19, R0, R19, RZ ;
STG.E [R16.64+0x4], R19 ;
LDG.E R0, [R12.64+0x8] ;
LDG.E R21, [R10.64+0x8] ;
IADD3 R8, R8, 0x4, RZ ;
IADD3 R2, P2, R2, 0x10, RZ ;
ISETP.GE.AND P0, PT, R8, 0x1, PT ;
IADD3 R4, P3, R4, 0x10, RZ ;
IMAD.X R3, RZ, RZ, R3, P2 ;
IADD3.X R5, RZ, R5, RZ, P3, !PT ;
IMAD.IADD R21, R0, 0x1, R21 ;
IADD3 R0, P1, R6, 0x10, RZ ;
STG.E [R16.64+0x8], R21 ;
IADD3.X R23, RZ, R7, RZ, P1, !PT ;
@!P0 BRA 0x390 ;
EXIT ;
BRA 0x5b0;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
Function : _Z19sum_Matrices_NormalPiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
MOV R1, c[0x0][0x28] ;
S2R R3, SR_CTAID.Y ;
S2R R2, SR_TID.Y ;
S2R R0, SR_CTAID.X ;
S2R R5, SR_TID.X ;
IMAD R3, R3, c[0x0][0x4], R2 ;
ISETP.GT.AND P0, PT, R3, 0x4, PT ;
IMAD R0, R0, c[0x0][0x0], R5 ;
ISETP.GT.OR P0, PT, R0, 0x4, P0 ;
@P0 EXIT ;
HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ;
IMAD R0, R3, 0x5, R0 ;
ULDC.64 UR4, c[0x0][0x118] ;
IMAD.WIDE R4, R0, R7, c[0x0][0x168] ;
IMAD.WIDE R2, R0.reuse, R7.reuse, c[0x0][0x160] ;
LDG.E R4, [R4.64] ;
LDG.E R3, [R2.64] ;
IMAD.WIDE R6, R0, R7, c[0x0][0x170] ;
IADD3 R9, R4, R3, RZ ;
STG.E [R6.64], R9 ;
EXIT ;
BRA 0x150;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
```
|
```amdasm
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z19sum_Matrices_NormalPiS_S_ ; -- Begin function _Z19sum_Matrices_NormalPiS_S_
.globl _Z19sum_Matrices_NormalPiS_S_
.p2align 8
.type _Z19sum_Matrices_NormalPiS_S_,@function
_Z19sum_Matrices_NormalPiS_S_: ; @_Z19sum_Matrices_NormalPiS_S_
; %bb.0:
s_load_b32 s2, s[0:1], 0x24
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_lshr_b32 s3, s2, 16
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[0:1], null, s14, s2, v[2:3]
v_mad_u64_u32 v[1:2], null, s15, s3, v[3:4]
s_mov_b32 s2, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_max_i32_e32 v2, v0, v1
v_cmpx_gt_i32_e32 5, v2
s_cbranch_execz .LBB0_2
; %bb.1:
s_load_b128 s[4:7], s[0:1], 0x0
v_mad_u64_u32 v[2:3], null, v1, 5, v[0:1]
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[0:1], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v2, v3, v2
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z19sum_Matrices_NormalPiS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z19sum_Matrices_NormalPiS_S_, .Lfunc_end0-_Z19sum_Matrices_NormalPiS_S_
; -- End function
.section .AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 208
; NumSgprs: 18
; NumVgprs: 6
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 6
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
.text
.protected _Z17sum_Matrices_filaPiS_S_ ; -- Begin function _Z17sum_Matrices_filaPiS_S_
.globl _Z17sum_Matrices_filaPiS_S_
.p2align 8
.type _Z17sum_Matrices_filaPiS_S_,@function
_Z17sum_Matrices_filaPiS_S_: ; @_Z17sum_Matrices_filaPiS_S_
; %bb.0:
s_load_b32 s4, s[0:1], 0x24
v_and_b32_e32 v3, 0x3ff, v0
s_add_u32 s2, s0, 24
s_addc_u32 s3, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s14, s4, v[3:4]
s_mov_b32 s4, exec_lo
v_cmpx_gt_i32_e32 5, v1
s_cbranch_execz .LBB1_3
; %bb.1: ; %.lr.ph
s_load_b32 s2, s[2:3], 0xc
v_bfe_u32 v0, v0, 10, 10
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
v_add_nc_u32_e32 v6, -1, v1
s_waitcnt lgkmcnt(0)
s_lshr_b32 s2, s2, 16
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, s15, s2, v[0:1]
v_mad_u64_u32 v[3:4], null, v2, 5, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v4, 31, v3
v_lshlrev_b64 v[4:5], 2, v[3:4]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s4, v4
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v5, vcc_lo
v_add_co_u32 v2, vcc_lo, s6, v4
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v5, vcc_lo
v_add_co_u32 v4, vcc_lo, s0, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s1, v5, vcc_lo
s_mov_b32 s1, 0
.LBB1_2: ; =>This Inner Loop Header: Depth=1
global_load_b32 v7, v[0:1], off
global_load_b32 v8, v[2:3], off
v_add_co_u32 v0, vcc_lo, v0, 4
v_add_nc_u32_e32 v6, 1, v6
v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
v_add_co_u32 v2, vcc_lo, v2, 4
v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_4)
v_cmp_lt_i32_e32 vcc_lo, 3, v6
s_or_b32 s1, vcc_lo, s1
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v7, v8, v7
global_store_b32 v[4:5], v7, off
v_add_co_u32 v4, s0, v4, 4
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v5, s0, 0, v5, s0
s_and_not1_b32 exec_lo, exec_lo, s1
s_cbranch_execnz .LBB1_2
.LBB1_3: ; %Flow31
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z17sum_Matrices_filaPiS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z17sum_Matrices_filaPiS_S_, .Lfunc_end1-_Z17sum_Matrices_filaPiS_S_
; -- End function
.section .AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 300
; NumSgprs: 18
; NumVgprs: 9
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 9
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
.text
.protected _Z20sum_Matrices_columnaPiS_S_ ; -- Begin function _Z20sum_Matrices_columnaPiS_S_
.globl _Z20sum_Matrices_columnaPiS_S_
.p2align 8
.type _Z20sum_Matrices_columnaPiS_S_,@function
_Z20sum_Matrices_columnaPiS_S_: ; @_Z20sum_Matrices_columnaPiS_S_
; %bb.0:
s_load_b32 s8, s[0:1], 0x24
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_lshr_b32 s2, s8, 16
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[3:4]
s_mov_b32 s2, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e32 5, v1
s_cbranch_execz .LBB2_3
; %bb.1: ; %.lr.ph.preheader
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[2:3], s[0:1], 0x10
v_lshl_add_u32 v3, v1, 2, v1
v_and_b32_e32 v0, 0x3ff, v0
s_and_b32 s0, s8, 0xffff
v_add_nc_u32_e32 v2, -1, v1
s_mul_i32 s14, s14, s0
s_mov_b32 s1, 0
v_add3_u32 v0, v0, s14, v3
.LBB2_2: ; %.lr.ph
; =>This Inner Loop Header: Depth=1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v1, 31, v0
v_add_nc_u32_e32 v2, 1, v2
v_lshlrev_b64 v[3:4], 2, v[0:1]
v_add_nc_u32_e32 v0, 5, v0
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v5, vcc_lo, s4, v3
v_add_co_ci_u32_e32 v6, vcc_lo, s5, v4, vcc_lo
v_add_co_u32 v7, vcc_lo, s6, v3
v_add_co_ci_u32_e32 v8, vcc_lo, s7, v4, vcc_lo
v_cmp_lt_i32_e32 vcc_lo, 3, v2
global_load_b32 v1, v[5:6], off
global_load_b32 v5, v[7:8], off
v_add_co_u32 v3, s0, s2, v3
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v4, s0, s3, v4, s0
s_or_b32 s1, vcc_lo, s1
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v1, v5, v1
global_store_b32 v[3:4], v1, off
s_and_not1_b32 exec_lo, exec_lo, s1
s_cbranch_execnz .LBB2_2
.LBB2_3: ; %Flow27
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z20sum_Matrices_columnaPiS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end2:
.size _Z20sum_Matrices_columnaPiS_S_, .Lfunc_end2-_Z20sum_Matrices_columnaPiS_S_
; -- End function
.section .AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 252
; NumSgprs: 18
; NumVgprs: 9
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 9
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object ; @__hip_cuid_
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0 ; 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z19sum_Matrices_NormalPiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z19sum_Matrices_NormalPiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z17sum_Matrices_filaPiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z17sum_Matrices_filaPiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z20sum_Matrices_columnaPiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z20sum_Matrices_columnaPiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
```
| 3,649 | 8,081 |
13 |
Convert the following CUDA host assembly code to AMD host assembly:
```cudaasm
.file "tmpxft_0002ae34_00000000-6_sum.cudafe1.cpp"
.text
.globl _ZSt21ios_base_library_initv
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3674:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3674:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z15imprimir_MatrizPA5_i
.type _Z15imprimir_MatrizPA5_i, @function
_Z15imprimir_MatrizPA5_i:
.LFB3669:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $24, %rsp
.cfi_def_cfa_offset 64
movq %fs:40, %rax
movq %rax, 8(%rsp)
xorl %eax, %eax
leaq 20(%rdi), %rbp
leaq 120(%rdi), %r13
leaq _ZSt4cout(%rip), %r12
jmp .L4
.L5:
movl $32, %esi
call _ZNSo3putEc@PLT
.L6:
addq $4, %rbx
cmpq %rbp, %rbx
je .L16
.L7:
movl (%rbx), %esi
movq %r12, %rdi
call _ZNSolsEi@PLT
movq %rax, %rdi
movb $32, 7(%rsp)
movq (%rax), %rax
movq -24(%rax), %rax
cmpq $0, 16(%rdi,%rax)
je .L5
leaq 7(%rsp), %rsi
movl $1, %edx
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
jmp .L6
.L16:
movq (%r12), %rax
movq -24(%rax), %rax
movq 240(%r12,%rax), %rbx
testq %rbx, %rbx
je .L17
cmpb $0, 56(%rbx)
je .L10
movzbl 67(%rbx), %esi
.L11:
movsbl %sil, %esi
movq %r12, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
addq $20, %rbp
cmpq %r13, %rbp
je .L3
.L4:
leaq -20(%rbp), %rbx
jmp .L7
.L17:
movq 8(%rsp), %rax
subq %fs:40, %rax
jne .L18
call _ZSt16__throw_bad_castv@PLT
.L18:
call __stack_chk_fail@PLT
.L10:
movq %rbx, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%rbx), %rax
movl $10, %esi
movq %rbx, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L11
.L3:
movq 8(%rsp), %rax
subq %fs:40, %rax
jne .L19
addq $24, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size _Z15imprimir_MatrizPA5_i, .-_Z15imprimir_MatrizPA5_i
.globl _Z15imprimir_vectorPi
.type _Z15imprimir_vectorPi, @function
_Z15imprimir_vectorPi:
.LFB3670:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $16, %rsp
.cfi_def_cfa_offset 48
movq %fs:40, %rax
movq %rax, 8(%rsp)
xorl %eax, %eax
movq %rdi, %rbx
leaq 20(%rdi), %rbp
leaq _ZSt4cout(%rip), %r12
jmp .L23
.L21:
movl $32, %esi
call _ZNSo3putEc@PLT
.L22:
addq $4, %rbx
cmpq %rbp, %rbx
je .L27
.L23:
movl (%rbx), %esi
movq %r12, %rdi
call _ZNSolsEi@PLT
movq %rax, %rdi
movb $32, 7(%rsp)
movq (%rax), %rax
movq -24(%rax), %rax
cmpq $0, 16(%rdi,%rax)
je .L21
leaq 7(%rsp), %rsi
movl $1, %edx
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
jmp .L22
.L27:
movq 8(%rsp), %rax
subq %fs:40, %rax
jne .L28
addq $16, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L28:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3670:
.size _Z15imprimir_vectorPi, .-_Z15imprimir_vectorPi
.globl _Z43__device_stub__Z19sum_Matrices_NormalPiS_S_PiS_S_
.type _Z43__device_stub__Z19sum_Matrices_NormalPiS_S_PiS_S_, @function
_Z43__device_stub__Z19sum_Matrices_NormalPiS_S_PiS_S_:
.LFB3696:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L33
.L29:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L34
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L33:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z19sum_Matrices_NormalPiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L29
.L34:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3696:
.size _Z43__device_stub__Z19sum_Matrices_NormalPiS_S_PiS_S_, .-_Z43__device_stub__Z19sum_Matrices_NormalPiS_S_PiS_S_
.globl _Z19sum_Matrices_NormalPiS_S_
.type _Z19sum_Matrices_NormalPiS_S_, @function
_Z19sum_Matrices_NormalPiS_S_:
.LFB3697:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z43__device_stub__Z19sum_Matrices_NormalPiS_S_PiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _Z19sum_Matrices_NormalPiS_S_, .-_Z19sum_Matrices_NormalPiS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%d "
.LC1:
.string "\n"
.text
.globl main
.type main, @function
main:
.LFB3671:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $384, %rsp
.cfi_def_cfa_offset 432
movq %fs:40, %rax
movq %rax, 376(%rsp)
xorl %eax, %eax
movl $0, %edi
call time@PLT
movl %eax, %edi
call srand@PLT
leaq 48(%rsp), %rax
leaq 160(%rsp), %rdx
leaq 148(%rsp), %rcx
.L38:
movl $1, (%rax)
movl $1, (%rdx)
movl $1, 4(%rax)
movl $1, 4(%rdx)
movl $1, 8(%rax)
movl $1, 8(%rdx)
movl $1, 12(%rax)
movl $1, 12(%rdx)
movl $1, 16(%rax)
movl $1, 16(%rdx)
addq $20, %rax
addq $20, %rdx
cmpq %rcx, %rax
jne .L38
leaq 48(%rsp), %rbp
movq %rbp, %rdi
call _Z15imprimir_MatrizPA5_i
leaq _ZSt4cout(%rip), %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq 160(%rsp), %rbx
movq %rbx, %rdi
call _Z15imprimir_MatrizPA5_i
movq %rsp, %rdi
movl $100, %esi
call cudaMalloc@PLT
leaq 8(%rsp), %rdi
movl $100, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $100, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $100, %edx
movq %rbp, %rsi
movq (%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $100, %edx
movq %rbx, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $5, 24(%rsp)
movl $5, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 24(%rsp), %rdx
movl $1, %ecx
movq 36(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L47
.L39:
call cudaDeviceSynchronize@PLT
leaq 272(%rsp), %rbp
movl $2, %ecx
movl $100, %edx
movq 16(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
leaq _ZSt4cout(%rip), %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq 372(%rsp), %r14
leaq .LC0(%rip), %r12
leaq .LC1(%rip), %r13
.L40:
movl $0, %ebx
.L41:
movl 0(%rbp,%rbx,4), %edx
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq $5, %rbx
jne .L41
movq %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $20, %rbp
cmpq %r14, %rbp
jne .L40
movq (%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 376(%rsp), %rax
subq %fs:40, %rax
jne .L48
movl $0, %eax
addq $384, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L47:
.cfi_restore_state
movq 16(%rsp), %rdx
movq 8(%rsp), %rsi
movq (%rsp), %rdi
call _Z43__device_stub__Z19sum_Matrices_NormalPiS_S_PiS_S_
jmp .L39
.L48:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3671:
.size main, .-main
.globl _Z41__device_stub__Z17sum_Matrices_filaPiS_S_PiS_S_
.type _Z41__device_stub__Z17sum_Matrices_filaPiS_S_PiS_S_, @function
_Z41__device_stub__Z17sum_Matrices_filaPiS_S_PiS_S_:
.LFB3698:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L53
.L49:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L54
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L53:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z17sum_Matrices_filaPiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L49
.L54:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3698:
.size _Z41__device_stub__Z17sum_Matrices_filaPiS_S_PiS_S_, .-_Z41__device_stub__Z17sum_Matrices_filaPiS_S_PiS_S_
.globl _Z17sum_Matrices_filaPiS_S_
.type _Z17sum_Matrices_filaPiS_S_, @function
_Z17sum_Matrices_filaPiS_S_:
.LFB3699:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z41__device_stub__Z17sum_Matrices_filaPiS_S_PiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3699:
.size _Z17sum_Matrices_filaPiS_S_, .-_Z17sum_Matrices_filaPiS_S_
.globl _Z44__device_stub__Z20sum_Matrices_columnaPiS_S_PiS_S_
.type _Z44__device_stub__Z20sum_Matrices_columnaPiS_S_PiS_S_, @function
_Z44__device_stub__Z20sum_Matrices_columnaPiS_S_PiS_S_:
.LFB3700:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L61
.L57:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L62
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L61:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z20sum_Matrices_columnaPiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L57
.L62:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3700:
.size _Z44__device_stub__Z20sum_Matrices_columnaPiS_S_PiS_S_, .-_Z44__device_stub__Z20sum_Matrices_columnaPiS_S_PiS_S_
.globl _Z20sum_Matrices_columnaPiS_S_
.type _Z20sum_Matrices_columnaPiS_S_, @function
_Z20sum_Matrices_columnaPiS_S_:
.LFB3701:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z44__device_stub__Z20sum_Matrices_columnaPiS_S_PiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3701:
.size _Z20sum_Matrices_columnaPiS_S_, .-_Z20sum_Matrices_columnaPiS_S_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC2:
.string "_Z20sum_Matrices_columnaPiS_S_"
.section .rodata.str1.1
.LC3:
.string "_Z17sum_Matrices_filaPiS_S_"
.LC4:
.string "_Z19sum_Matrices_NormalPiS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3703:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z20sum_Matrices_columnaPiS_S_(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z17sum_Matrices_filaPiS_S_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z19sum_Matrices_NormalPiS_S_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3703:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
```
|
```amdasm
.text
.file "sum.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z34__device_stub__sum_Matrices_NormalPiS_S_ # -- Begin function _Z34__device_stub__sum_Matrices_NormalPiS_S_
.type _Z34__device_stub__sum_Matrices_NormalPiS_S_,@function
_Z34__device_stub__sum_Matrices_NormalPiS_S_: # @_Z34__device_stub__sum_Matrices_NormalPiS_S_
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $112, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 40(%rsp), %rax
movq %rdi, (%rax)
leaq 32(%rsp), %rcx
movq %rsi, (%rcx)
leaq 24(%rsp), %rsi
movq %rdx, (%rsi)
leaq 80(%rsp), %rbx
movq %rax, (%rbx)
movq %rcx, 8(%rbx)
movq %rsi, 16(%rbx)
leaq 64(%rsp), %r14
leaq 48(%rsp), %r15
leaq 16(%rsp), %r12
leaq 8(%rsp), %r13
movq %r14, %rdi
movq %r15, %rsi
movq %r12, %rdx
movq %r13, %rcx
callq __hipPopCallConfiguration
movq (%r14), %rsi
movl 8(%r14), %edx
movq (%r15), %rcx
movl 8(%r15), %r8d
movl $_Z19sum_Matrices_NormalPiS_S_, %edi
movq %rbx, %r9
pushq (%r13)
.cfi_adjust_cfa_offset 8
pushq (%r12)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $128, %rsp
.cfi_adjust_cfa_offset -128
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z34__device_stub__sum_Matrices_NormalPiS_S_, .Lfunc_end0-_Z34__device_stub__sum_Matrices_NormalPiS_S_
.cfi_endproc
# -- End function
.globl _Z32__device_stub__sum_Matrices_filaPiS_S_ # -- Begin function _Z32__device_stub__sum_Matrices_filaPiS_S_
.type _Z32__device_stub__sum_Matrices_filaPiS_S_,@function
_Z32__device_stub__sum_Matrices_filaPiS_S_: # @_Z32__device_stub__sum_Matrices_filaPiS_S_
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $112, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 40(%rsp), %rax
movq %rdi, (%rax)
leaq 32(%rsp), %rcx
movq %rsi, (%rcx)
leaq 24(%rsp), %rsi
movq %rdx, (%rsi)
leaq 80(%rsp), %rbx
movq %rax, (%rbx)
movq %rcx, 8(%rbx)
movq %rsi, 16(%rbx)
leaq 64(%rsp), %r14
leaq 48(%rsp), %r15
leaq 16(%rsp), %r12
leaq 8(%rsp), %r13
movq %r14, %rdi
movq %r15, %rsi
movq %r12, %rdx
movq %r13, %rcx
callq __hipPopCallConfiguration
movq (%r14), %rsi
movl 8(%r14), %edx
movq (%r15), %rcx
movl 8(%r15), %r8d
movl $_Z17sum_Matrices_filaPiS_S_, %edi
movq %rbx, %r9
pushq (%r13)
.cfi_adjust_cfa_offset 8
pushq (%r12)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $128, %rsp
.cfi_adjust_cfa_offset -128
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z32__device_stub__sum_Matrices_filaPiS_S_, .Lfunc_end1-_Z32__device_stub__sum_Matrices_filaPiS_S_
.cfi_endproc
# -- End function
.globl _Z35__device_stub__sum_Matrices_columnaPiS_S_ # -- Begin function _Z35__device_stub__sum_Matrices_columnaPiS_S_
.type _Z35__device_stub__sum_Matrices_columnaPiS_S_,@function
_Z35__device_stub__sum_Matrices_columnaPiS_S_: # @_Z35__device_stub__sum_Matrices_columnaPiS_S_
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $112, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 40(%rsp), %rax
movq %rdi, (%rax)
leaq 32(%rsp), %rcx
movq %rsi, (%rcx)
leaq 24(%rsp), %rsi
movq %rdx, (%rsi)
leaq 80(%rsp), %rbx
movq %rax, (%rbx)
movq %rcx, 8(%rbx)
movq %rsi, 16(%rbx)
leaq 64(%rsp), %r14
leaq 48(%rsp), %r15
leaq 16(%rsp), %r12
leaq 8(%rsp), %r13
movq %r14, %rdi
movq %r15, %rsi
movq %r12, %rdx
movq %r13, %rcx
callq __hipPopCallConfiguration
movq (%r14), %rsi
movl 8(%r14), %edx
movq (%r15), %rcx
movl 8(%r15), %r8d
movl $_Z20sum_Matrices_columnaPiS_S_, %edi
movq %rbx, %r9
pushq (%r13)
.cfi_adjust_cfa_offset 8
pushq (%r12)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $128, %rsp
.cfi_adjust_cfa_offset -128
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size _Z35__device_stub__sum_Matrices_columnaPiS_S_, .Lfunc_end2-_Z35__device_stub__sum_Matrices_columnaPiS_S_
.cfi_endproc
# -- End function
.globl _Z15imprimir_MatrizPA5_i # -- Begin function _Z15imprimir_MatrizPA5_i
.type _Z15imprimir_MatrizPA5_i,@function
_Z15imprimir_MatrizPA5_i: # @_Z15imprimir_MatrizPA5_i
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $16, %rsp
.cfi_def_cfa_offset 64
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rdi, %rbx
xorl %r15d, %r15d
movl $_ZSt4cout, %r12d
leaq 15(%rsp), %r14
.LBB3_1: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB3_2 Depth 2
xorl %r13d, %r13d
.LBB3_2: # Parent Loop BB3_1 Depth=1
# => This Inner Loop Header: Depth=2
movl (%rbx,%r13,4), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movb $32, 15(%rsp)
movq (%rax), %rcx
movq -24(%rcx), %rcx
cmpq $0, 16(%rax,%rcx)
je .LBB3_6
# %bb.3: # in Loop: Header=BB3_2 Depth=2
movl $1, %edx
movq %rax, %rdi
movq %r14, %rsi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
jmp .LBB3_7
.LBB3_6: # in Loop: Header=BB3_2 Depth=2
movq %rax, %rdi
movl $32, %esi
callq _ZNSo3putEc
.LBB3_7: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_c.exit
# in Loop: Header=BB3_2 Depth=2
incq %r13
cmpq $5, %r13
jne .LBB3_2
# %bb.4: # in Loop: Header=BB3_1 Depth=1
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rdi
addq %r12, %rdi
movl $10, %esi
callq _ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
incq %r15
addq $20, %rbx
cmpq $5, %r15
jne .LBB3_1
# %bb.5:
addq $16, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size _Z15imprimir_MatrizPA5_i, .Lfunc_end3-_Z15imprimir_MatrizPA5_i
.cfi_endproc
# -- End function
.globl _Z15imprimir_vectorPi # -- Begin function _Z15imprimir_vectorPi
.type _Z15imprimir_vectorPi,@function
_Z15imprimir_vectorPi: # @_Z15imprimir_vectorPi
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $16, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rdi, %rbx
xorl %r15d, %r15d
leaq 15(%rsp), %r14
.LBB4_1: # =>This Inner Loop Header: Depth=1
movl (%rbx,%r15,4), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movb $32, 15(%rsp)
movq (%rax), %rcx
movq -24(%rcx), %rcx
cmpq $0, 16(%rax,%rcx)
je .LBB4_3
# %bb.2: # in Loop: Header=BB4_1 Depth=1
movl $1, %edx
movq %rax, %rdi
movq %r14, %rsi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
jmp .LBB4_4
.LBB4_3: # in Loop: Header=BB4_1 Depth=1
movq %rax, %rdi
movl $32, %esi
callq _ZNSo3putEc
.LBB4_4: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_c.exit
# in Loop: Header=BB4_1 Depth=1
incq %r15
cmpq $5, %r15
jne .LBB4_1
# %bb.5:
addq $16, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end4:
.size _Z15imprimir_vectorPi, .Lfunc_end4-_Z15imprimir_vectorPi
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $368, %rsp # imm = 0x170
.cfi_def_cfa_offset 416
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
xorl %ebx, %ebx
xorl %edi, %edi
callq time
movl %eax, %edi
callq srand
leaq 144(%rsp), %rax
leaq 32(%rsp), %rcx
movl $1, %edx
.LBB5_1: # %.preheader32
# =>This Loop Header: Depth=1
# Child Loop BB5_2 Depth 2
xorl %esi, %esi
.LBB5_2: # Parent Loop BB5_1 Depth=1
# => This Inner Loop Header: Depth=2
movl %edx, (%rax,%rsi,4)
movl %edx, (%rcx,%rsi,4)
incq %rsi
cmpq $5, %rsi
jne .LBB5_2
# %bb.3: # in Loop: Header=BB5_1 Depth=1
incq %rbx
addq $20, %rax
addq $20, %rcx
cmpq $5, %rbx
jne .LBB5_1
# %bb.4:
leaq 144(%rsp), %rbx
movq %rbx, %rdi
callq _Z15imprimir_MatrizPA5_i
movl $_ZSt4cout, %r13d
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rdi
addq %r13, %rdi
movl $10, %esi
callq _ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
leaq 32(%rsp), %r14
movq %r14, %rdi
callq _Z15imprimir_MatrizPA5_i
leaq 24(%rsp), %r15
movl $100, %esi
movq %r15, %rdi
callq hipMalloc
leaq 16(%rsp), %r12
movl $100, %esi
movq %r12, %rdi
callq hipMalloc
leaq 8(%rsp), %rdi
movl $100, %esi
callq hipMalloc
movq (%r15), %rdi
movl $100, %edx
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq (%r12), %rdi
movl $100, %edx
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $4294967297, %rdi # imm = 0x100000001
movabsq $21474836485, %rdx # imm = 0x500000005
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB5_6
# %bb.5:
movq 24(%rsp), %rdi
movq 16(%rsp), %rsi
movq 8(%rsp), %rdx
callq _Z34__device_stub__sum_Matrices_NormalPiS_S_
.LBB5_6:
callq hipDeviceSynchronize
movq 8(%rsp), %rsi
leaq 256(%rsp), %rbx
movl $100, %edx
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rdi
addq %r13, %rdi
movl $10, %esi
callq _ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
xorl %r14d, %r14d
.LBB5_7: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB5_8 Depth 2
xorl %r15d, %r15d
.LBB5_8: # Parent Loop BB5_7 Depth=1
# => This Inner Loop Header: Depth=2
movl (%rbx,%r15,4), %esi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
incq %r15
cmpq $5, %r15
jne .LBB5_8
# %bb.9: # in Loop: Header=BB5_7 Depth=1
movl $10, %edi
callq putchar@PLT
incq %r14
addq $20, %rbx
cmpq $5, %r14
jne .LBB5_7
# %bb.10:
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $368, %rsp # imm = 0x170
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end5:
.size main, .Lfunc_end5-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
movq __hip_gpubin_handle(%rip), %rbx
testq %rbx, %rbx
jne .LBB6_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, %rbx
movq %rax, __hip_gpubin_handle(%rip)
.LBB6_2:
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z19sum_Matrices_NormalPiS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z17sum_Matrices_filaPiS_S_, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z20sum_Matrices_columnaPiS_S_, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end6:
.size __hip_module_ctor, .Lfunc_end6-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB7_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB7_2:
retq
.Lfunc_end7:
.size __hip_module_dtor, .Lfunc_end7-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z19sum_Matrices_NormalPiS_S_,@object # @_Z19sum_Matrices_NormalPiS_S_
.section .rodata,"a",@progbits
.globl _Z19sum_Matrices_NormalPiS_S_
.p2align 3, 0x0
_Z19sum_Matrices_NormalPiS_S_:
.quad _Z34__device_stub__sum_Matrices_NormalPiS_S_
.size _Z19sum_Matrices_NormalPiS_S_, 8
.type _Z17sum_Matrices_filaPiS_S_,@object # @_Z17sum_Matrices_filaPiS_S_
.globl _Z17sum_Matrices_filaPiS_S_
.p2align 3, 0x0
_Z17sum_Matrices_filaPiS_S_:
.quad _Z32__device_stub__sum_Matrices_filaPiS_S_
.size _Z17sum_Matrices_filaPiS_S_, 8
.type _Z20sum_Matrices_columnaPiS_S_,@object # @_Z20sum_Matrices_columnaPiS_S_
.globl _Z20sum_Matrices_columnaPiS_S_
.p2align 3, 0x0
_Z20sum_Matrices_columnaPiS_S_:
.quad _Z35__device_stub__sum_Matrices_columnaPiS_S_
.size _Z20sum_Matrices_columnaPiS_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%d "
.size .L.str, 4
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z19sum_Matrices_NormalPiS_S_"
.size .L__unnamed_1, 30
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z17sum_Matrices_filaPiS_S_"
.size .L__unnamed_2, 28
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z20sum_Matrices_columnaPiS_S_"
.size .L__unnamed_3, 31
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z34__device_stub__sum_Matrices_NormalPiS_S_
.addrsig_sym _Z32__device_stub__sum_Matrices_filaPiS_S_
.addrsig_sym _Z35__device_stub__sum_Matrices_columnaPiS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z19sum_Matrices_NormalPiS_S_
.addrsig_sym _Z17sum_Matrices_filaPiS_S_
.addrsig_sym _Z20sum_Matrices_columnaPiS_S_
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
```
| 7,547 | 8,180 |
16 |
Convert the following CUDA device assembly code to AMD device assembly:
```cudaasm
code for sm_80
```
|
```amdasm
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object ; @__hip_cuid_
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0 ; 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
```
| 24 | 306 |
17 |
Convert the following CUDA host assembly code to AMD host assembly:
```cudaasm
.file "tmpxft_000d7a49_00000000-6_cuda_syn_block.cudafe1.cpp"
.text
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2030:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z12__syncblocksPVj
.type _Z12__syncblocksPVj, @function
_Z12__syncblocksPVj:
.LFB2027:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2027:
.size _Z12__syncblocksPVj, .-_Z12__syncblocksPVj
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2053:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2053:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
```
|
```amdasm
.text
.file "cuda_syn_block.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
```
| 922 | 185 |
18 |
Convert the following CUDA device assembly code to AMD device assembly:
```cudaasm
code for sm_80
Function : _Z15calculateMatrixPKcPiS1_S1_S1_S1_S1_S1_S1_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ;
S2R R34, SR_TID.X ;
ULDC UR5, c[0x3][0x20] ;
IMAD.MOV.U32 R3, RZ, RZ, c[0x3][0x0] ;
ULEA UR6, UR5, 0x4, 0x2 ;
S2UR UR4, SR_CTAID.X ;
IADD3 R32, R3.reuse, c[0x3][0x20], RZ ;
IADD3 R29, R3, -c[0x3][0x8], RZ ;
IADD3 R0, R32, -0x1, RZ ;
IADD3 R3, R3, 0x1, RZ ;
ISETP.GE.AND P0, PT, R0, 0x1, PT ;
IMAD.SHL.U32 R31, R34, 0x4, RZ ;
STS [R34.X4], RZ ;
IMAD R29, R29, UR4, RZ ;
IADD3 R30, R31, UR6, RZ ;
STS [R31+UR6], RZ ;
IMAD R28, R3, UR4, -R34 ;
STS [R30+UR6], RZ ;
BAR.SYNC.DEFER_BLOCKING 0x0 ;
@!P0 EXIT ;
ISETP.NE.AND P0, PT, R32, 0x2, PT ;
UMOV UR4, URZ ;
IADD3 R27, R34, c[0x0][0x1a8], RZ ;
UIADD3 UR5, UR5, -0x1, URZ ;
IMAD.IADD R26, R29.reuse, 0x1, -R34 ;
ULDC.64 UR8, c[0x0][0x118] ;
IADD3 R25, R29, c[0x3][0x0], RZ ;
IMAD.MOV.U32 R24, RZ, RZ, RZ ;
CS2R R22, SRZ ;
CS2R R16, SRZ ;
CS2R R20, SRZ ;
IMAD.MOV.U32 R37, RZ, RZ, RZ ;
IMAD.MOV.U32 R19, RZ, RZ, RZ ;
@!P0 BRA 0xc70 ;
LOP3.LUT R3, R0.reuse, 0x1, RZ, 0xc0, !PT ;
IMAD.MOV.U32 R24, RZ, RZ, RZ ;
ISETP.GE.AND P1, PT, R27, c[0x3][0x10], PT ;
CS2R R22, SRZ ;
CS2R R16, SRZ ;
IMAD.IADD R0, R0, 0x1, -R3 ;
CS2R R20, SRZ ;
IMAD.MOV.U32 R37, RZ, RZ, RZ ;
UMOV UR4, URZ ;
IMAD.MOV.U32 R19, RZ, RZ, RZ ;
ISETP.GE.AND P0, PT, R26, c[0x3][0xc], PT ;
IMAD.SHL.U32 R8, R28, 0x4, RZ ;
ISETP.LT.AND P1, PT, R26.reuse, R25, !P1 ;
IMAD.MOV.U32 R33, RZ, RZ, 0x4 ;
ISETP.GE.AND P0, PT, R26, R29, !P0 ;
BSSY B0, 0x550 ;
SHF.R.S32.HI R35, RZ, 0x1f, R28 ;
IMAD.WIDE R10, R28, R33, c[0x0][0x170] ;
PLOP3.LUT P1, PT, P0, P1, PT, 0x80, 0x0 ;
IADD3 R2, P2, R8, c[0x0][0x180], RZ ;
IMAD.WIDE R12, R28, R33.reuse, c[0x0][0x188] ;
IADD3 R4, P3, R8.reuse, c[0x0][0x1a0], RZ ;
IADD3 R6, P4, R8, c[0x0][0x178], RZ ;
IMAD.WIDE R14, R28, R33, c[0x0][0x190] ;
IADD3 R8, P5, R8, c[0x0][0x198], RZ ;
PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ;
SHF.L.U64.HI R35, R28, 0x2, R35 ;
@!P1 BRA 0x540 ;
IADD3 R16, P0, R26.reuse, c[0x0][0x160], RZ ;
LDS R37, [R31+UR6] ;
LEA.HI.X.SX32 R17, R26, c[0x0][0x164], 0x1, P0 ;
LDG.E.S8 R16, [R16.64] ;
LDS R17, [R30+UR6] ;
IMAD R18, R16, c[0x3][0x10], R27 ;
LDS R16, [R34.X4] ;
IMAD.WIDE R18, R18, R33, c[0x0][0x168] ;
LDG.E R19, [R18.64] ;
ISETP.NE.AND P1, PT, R34, RZ, PT ;
PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ;
@P1 BRA 0x540 ;
ISETP.GE.AND P0, PT, R28, 0x1, PT ;
LDG.E R16, [R10.64] ;
LDG.E R37, [R12.64] ;
LDG.E R17, [R14.64] ;
@P0 LDG.E R24, [R14.64+-0x4] ;
ISETP.NE.AND P1, PT, RZ, UR4, PT ;
@P0 LDG.E R22, [R10.64+-0x4] ;
ISETP.EQ.OR P1, PT, RZ, c[0x0][0x1a8], !P1 ;
PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ;
SEL R24, R26, R24, P1 ;
BSYNC B0 ;
BAR.SYNC.DEFER_BLOCKING 0x0 ;
IADD3.X R3, R35.reuse, c[0x0][0x184], RZ, P2, !PT ;
IADD3.X R5, R35.reuse, c[0x0][0x1a4], RZ, P3, !PT ;
IADD3.X R7, R35.reuse, c[0x0][0x17c], RZ, P4, !PT ;
BSSY B0, 0x7c0 ;
IADD3.X R9, R35, c[0x0][0x19c], RZ, P5, !PT ;
@!P0 BRA 0x7b0 ;
IADD3 R21, R21, -c[0x3][0x14], RZ ;
IMAD.IADD R22, R22, 0x1, R19 ;
IADD3 R20, R20, -c[0x3][0x18], RZ ;
IADD3 R18, R37, -c[0x3][0x18], RZ ;
IMNMX R20, R21, R20, !PT ;
IADD3 R21, R16, -c[0x3][0x14], RZ ;
IMNMX R18, R18, R21, !PT ;
IMNMX R21, RZ, R18, !PT ;
IMNMX R21, R20, R21, !PT ;
IMNMX R21, R21, R22, !PT ;
ISETP.NE.AND P0, PT, R21, R20, PT ;
SEL R22, R23, R24, !P0 ;
LDG.E R24, [R2.64] ;
ISETP.NE.AND P0, PT, R21.reuse, RZ, PT ;
ISETP.NE.AND P3, PT, R34, UR5, PT ;
STS [R31+UR6+0x4], R18 ;
ISETP.NE.AND P1, PT, R21, R18, PT ;
STS [R34.X4+0x4], R21 ;
SEL R23, R17, R22, !P1 ;
IMAD.MOV.U32 R22, RZ, RZ, R16 ;
@!P0 IADD3 R23, R26, 0x1, RZ ;
@!P3 IMAD.MOV.U32 R22, RZ, RZ, R16 ;
STS [R30+UR6+0x4], R23 ;
ISETP.GE.AND P2, PT, R21, R24, PT ;
IMAD.MOV.U32 R24, RZ, RZ, R17.reuse ;
@!P3 IMAD.MOV.U32 R24, RZ, RZ, R17 ;
@P2 STG.E [R2.64], R21 ;
@P2 STG.E [R4.64], R23 ;
@!P3 STG.E [R6.64], R21 ;
@!P3 STG.E [R12.64], R18 ;
@!P3 STG.E [R8.64], R23 ;
BSYNC B0 ;
IADD3 R36, R26, 0x1, RZ ;
BAR.SYNC.DEFER_BLOCKING 0x0 ;
ISETP.GE.AND P1, PT, R27, c[0x3][0x10], PT ;
ISETP.GE.AND P0, PT, R36.reuse, c[0x3][0xc], PT ;
ISETP.LT.AND P2, PT, R36.reuse, R25, !P1 ;
BSSY B0, 0x9c0 ;
ISETP.GE.AND P0, PT, R36, R29, !P0 ;
PLOP3.LUT P2, PT, P0, P2, PT, 0x80, 0x0 ;
PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ;
@!P2 BRA 0x9b0 ;
IADD3 R16, P0, R26.reuse, c[0x0][0x160], RZ ;
LDS R37, [R31+UR6] ;
LEA.HI.X.SX32 R17, R26, c[0x0][0x164], 0x1, P0 ;
LDG.E.S8 R16, [R16.64+0x1] ;
LDS R17, [R30+UR6] ;
IMAD R18, R16, c[0x3][0x10], R27 ;
LDS R16, [R34.X4] ;
IMAD.WIDE R18, R18, R33, c[0x0][0x168] ;
LDG.E R19, [R18.64] ;
ISETP.NE.AND P2, PT, R34, RZ, PT ;
PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ;
@P2 BRA 0x9b0 ;
ISETP.GE.AND P0, PT, R28, RZ, PT ;
LDG.E R17, [R14.64+0x4] ;
LDG.E R16, [R10.64+0x4] ;
LDG.E R37, [R12.64+0x4] ;
@P0 LDG.E R24, [R14.64] ;
ISETP.NE.AND P2, PT, RZ, c[0x0][0x1a8], PT ;
@P0 LDG.E R22, [R10.64] ;
PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ;
SEL R24, R36, R24, !P2 ;
BSYNC B0 ;
BAR.SYNC.DEFER_BLOCKING 0x0 ;
BSSY B0, 0xbf0 ;
@!P0 BRA 0xbe0 ;
LDG.E R10, [R2.64+0x4] ;
IADD3 R11, R37, -c[0x3][0x18], RZ ;
IMAD.IADD R18, R22, 0x1, R19 ;
IADD3 R14, R16, -c[0x3][0x14], RZ ;
IMAD.MOV.U32 R22, RZ, RZ, R16 ;
IADD3 R21, R21, -c[0x3][0x14], RZ ;
IADD3 R20, R20, -c[0x3][0x18], RZ ;
IMNMX R14, R11, R14, !PT ;
IMNMX R20, R21, R20, !PT ;
IMNMX R11, RZ, R14, !PT ;
STS [R31+UR6+0x4], R14 ;
ISETP.NE.AND P4, PT, R34, UR5, PT ;
IMNMX R11, R20, R11, !PT ;
IMNMX R21, R11, R18, !PT ;
ISETP.NE.AND P2, PT, R21.reuse, RZ, PT ;
STS [R34.X4+0x4], R21 ;
ISETP.NE.AND P3, PT, R21.reuse, R20, PT ;
@!P4 IMAD.MOV.U32 R22, RZ, RZ, R16 ;
ISETP.GE.AND P0, PT, R21, R10, PT ;
SEL R10, R23, R24, !P3 ;
IMAD.MOV.U32 R24, RZ, RZ, R17.reuse ;
ISETP.NE.AND P3, PT, R21, R14, PT ;
@!P4 IMAD.MOV.U32 R24, RZ, RZ, R17 ;
SEL R23, R17, R10, !P3 ;
@!P2 IADD3 R23, R26, 0x2, RZ ;
@P0 STG.E [R2.64+0x4], R21 ;
@P0 STG.E [R4.64+0x4], R23 ;
@!P4 STG.E [R6.64+0x4], R21 ;
@!P4 STG.E [R12.64+0x4], R14 ;
STS [R30+UR6+0x4], R23 ;
@!P4 STG.E [R8.64+0x4], R23 ;
BSYNC B0 ;
IADD3 R0, R0, -0x2, RZ ;
BAR.SYNC.DEFER_BLOCKING 0x0 ;
UIADD3 UR4, UR4, 0x2, URZ ;
IADD3 R26, R26, 0x2, RZ ;
ISETP.NE.AND P0, PT, R0, RZ, PT ;
IADD3 R28, R28, 0x2, RZ ;
@P0 BRA 0x2c0 ;
UMOV UR4, 0x1 ;
IADD3 R32, R32, -0x1, RZ ;
LOP3.LUT P0, RZ, R32, 0x1, RZ, 0xc0, !PT ;
@!P0 EXIT ;
ISETP.GE.AND P0, PT, R26.reuse, c[0x3][0xc], PT ;
IMAD.MOV.U32 R11, RZ, RZ, 0x4 ;
ISETP.GE.AND P1, PT, R27, c[0x3][0x10], PT ;
BSSY B0, 0xed0 ;
ISETP.GE.AND P0, PT, R26, R29, !P0 ;
IMAD.WIDE R2, R28, R11, c[0x0][0x188] ;
ISETP.LT.AND P1, PT, R26, R25, !P1 ;
SHF.R.S32.HI R9, RZ, 0x1f, R28 ;
PLOP3.LUT P1, PT, P0, P1, PT, 0x80, 0x0 ;
PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ;
@!P1 BRA 0xec0 ;
IADD3 R6, P0, R26.reuse, c[0x0][0x160], RZ ;
LDS R16, [R34.X4] ;
LEA.HI.X.SX32 R7, R26, c[0x0][0x164], 0x1, P0 ;
LDS R37, [R31+UR6] ;
LDG.E.S8 R6, [R6.64] ;
LDS R17, [R30+UR6] ;
ISETP.NE.AND P1, PT, R34, RZ, PT ;
IMAD R4, R6, c[0x3][0x10], R27 ;
IMAD.WIDE R4, R4, R11, c[0x0][0x168] ;
LDG.E R19, [R4.64] ;
PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ;
@P1 BRA 0xec0 ;
ISETP.GE.AND P1, PT, R28.reuse, 0x1, PT ;
IMAD.WIDE R6, R28.reuse, R11.reuse, c[0x0][0x190] ;
LDG.E R37, [R2.64] ;
IMAD.WIDE R4, R28, R11, c[0x0][0x170] ;
LDG.E R17, [R6.64] ;
LDG.E R16, [R4.64] ;
@P1 LDG.E R24, [R6.64+-0x4] ;
@P1 LDG.E R22, [R4.64+-0x4] ;
ISETP.NE.AND P1, PT, RZ, UR4, PT ;
ISETP.EQ.OR P1, PT, RZ, c[0x0][0x1a8], !P1 ;
SEL R24, R26, R24, P1 ;
BSYNC B0 ;
BAR.SYNC.DEFER_BLOCKING 0x0 ;
BSSY B0, 0x1160 ;
@!P0 BRA 0x1150 ;
IMAD.SHL.U32 R8, R28.reuse, 0x4, RZ ;
SHF.L.U64.HI R28, R28, 0x2, R9 ;
IADD3 R4, P0, R8, c[0x0][0x180], RZ ;
IADD3.X R5, R28, c[0x0][0x184], RZ, P0, !PT ;
LDG.E R6, [R4.64] ;
IADD3 R0, R37, -c[0x3][0x18], RZ ;
IMAD.IADD R22, R19, 0x1, R22 ;
IADD3 R7, R16, -c[0x3][0x14], RZ ;
IADD3 R21, R21, -c[0x3][0x14], RZ ;
IADD3 R20, R20, -c[0x3][0x18], RZ ;
IMNMX R0, R0, R7, !PT ;
IMNMX R20, R21, R20, !PT ;
IMNMX R7, RZ, R0, !PT ;
STS [R31+UR6+0x4], R0 ;
IMNMX R7, R20, R7, !PT ;
IMNMX R9, R7, R22, !PT ;
ISETP.NE.AND P1, PT, R9.reuse, R0, PT ;
STS [R34.X4+0x4], R9 ;
ISETP.NE.AND P0, PT, R9.reuse, RZ, PT ;
ISETP.NE.AND P2, PT, R9, R20, PT ;
@P1 SEL R17, R23, R24, !P2 ;
@!P0 IADD3 R17, R26, 0x1, RZ ;
ISETP.NE.AND P0, PT, R34, UR5, PT ;
STS [R30+UR6+0x4], R17 ;
ISETP.GE.AND P3, PT, R9, R6, PT ;
@P3 IADD3 R6, P1, R8, c[0x0][0x1a0], RZ ;
@P3 STG.E [R4.64], R9 ;
@P3 IADD3.X R7, R28, c[0x0][0x1a4], RZ, P1, !PT ;
@P3 STG.E [R6.64], R17 ;
@P0 BRA 0x1150 ;
IADD3 R4, P0, R8.reuse, c[0x0][0x178], RZ ;
IADD3 R6, P1, R8, c[0x0][0x198], RZ ;
IADD3.X R5, R28.reuse, c[0x0][0x17c], RZ, P0, !PT ;
IADD3.X R7, R28, c[0x0][0x19c], RZ, P1, !PT ;
STG.E [R4.64], R9 ;
STG.E [R2.64], R0 ;
STG.E [R6.64], R17 ;
BSYNC B0 ;
BAR.SYNC.DEFER_BLOCKING 0x0 ;
EXIT ;
BRA 0x1180;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
```
|
```amdasm
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z15calculateMatrixPKcPiS1_S1_S1_S1_S1_S1_S1_i ; -- Begin function _Z15calculateMatrixPKcPiS1_S1_S1_S1_S1_S1_S1_i
.globl _Z15calculateMatrixPKcPiS1_S1_S1_S1_S1_S1_S1_i
.p2align 8
.type _Z15calculateMatrixPKcPiS1_S1_S1_S1_S1_S1_S1_i,@function
_Z15calculateMatrixPKcPiS1_S1_S1_S1_S1_S1_S1_i: ; @_Z15calculateMatrixPKcPiS1_S1_S1_S1_S1_S1_S1_i
; %bb.0:
s_getpc_b64 s[2:3]
s_add_u32 s2, s2, queryPartLength@rel32@lo+4
s_addc_u32 s3, s3, queryPartLength@rel32@hi+12
v_dual_mov_b32 v1, 0 :: v_dual_lshlrev_b32 v4, 2, v0
s_load_b32 s4, s[2:3], 0x0
s_getpc_b64 s[2:3]
s_add_u32 s2, s2, partSeqSize@rel32@lo+4
s_addc_u32 s3, s3, partSeqSize@rel32@hi+12
s_load_b32 s2, s[2:3], 0x0
v_add_nc_u32_e32 v18, 0, v4
ds_store_b32 v18, v1
s_waitcnt lgkmcnt(0)
s_lshl_b32 s5, s4, 2
s_add_i32 s4, s4, -1
s_add_i32 s6, s5, 0
s_delay_alu instid0(SALU_CYCLE_1)
s_add_i32 s3, s6, 4
v_add_nc_u32_e32 v19, s6, v4
s_add_i32 s5, s3, s5
s_add_i32 s6, s4, s2
v_add_nc_u32_e32 v20, s5, v4
s_cmp_lt_i32 s6, 1
ds_store_b32 v19, v1 offset:4
ds_store_b32 v20, v1 offset:4
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB0_19
; %bb.1: ; %.lr.ph
s_getpc_b64 s[8:9]
s_add_u32 s8, s8, overlapLength@rel32@lo+4
s_addc_u32 s9, s9, overlapLength@rel32@hi+12
s_load_b512 s[16:31], s[0:1], 0x0
s_load_b32 s14, s[8:9], 0x0
s_clause 0x1
s_load_b32 s33, s[0:1], 0x48
s_load_b64 s[12:13], s[0:1], 0x40
s_add_i32 s7, s2, 1
s_getpc_b64 s[8:9]
s_add_u32 s8, s8, queryLength@rel32@lo+4
s_addc_u32 s9, s9, queryLength@rel32@hi+12
s_mul_i32 s7, s7, s15
s_getpc_b64 s[10:11]
s_add_u32 s10, s10, seqLibLength@rel32@lo+4
s_addc_u32 s11, s11, seqLibLength@rel32@hi+12
v_sub_nc_u32_e32 v2, s7, v0
s_load_b32 s7, s[8:9], 0x0
v_cmp_eq_u32_e32 vcc_lo, 0, v0
v_add_nc_u32_e32 v21, s3, v4
v_cmp_eq_u32_e64 s0, s4, v0
v_ashrrev_i32_e32 v3, 31, v2
v_add3_u32 v22, s5, 4, v4
s_load_b32 s34, s[10:11], 0x0
v_dual_mov_b32 v29, 0 :: v_dual_mov_b32 v30, 0
s_delay_alu instid0(VALU_DEP_3)
v_lshlrev_b64 v[16:17], 2, v[2:3]
v_dual_mov_b32 v31, 0 :: v_dual_mov_b32 v32, 0
s_waitcnt lgkmcnt(0)
s_sub_i32 s8, s2, s14
v_dual_mov_b32 v26, 0 :: v_dual_add_nc_u32 v3, s33, v0
s_mul_i32 s8, s8, s15
v_add_co_u32 v4, s1, s24, v16
v_sub_nc_u32_e32 v23, s8, v0
s_add_i32 s14, s8, s2
s_cmp_eq_u32 s33, 0
v_add_co_ci_u32_e64 v5, s1, s25, v17, s1
s_cselect_b32 s9, -1, 0
s_getpc_b64 s[2:3]
s_add_u32 s2, s2, gapExtension@rel32@lo+4
s_addc_u32 s3, s3, gapExtension@rel32@hi+12
v_ashrrev_i32_e32 v0, 31, v23
s_getpc_b64 s[4:5]
s_add_u32 s4, s4, gapOpen@rel32@lo+4
s_addc_u32 s5, s5, gapOpen@rel32@hi+12
s_load_b32 s10, s[2:3], 0x0
s_load_b32 s11, s[4:5], 0x0
v_add_co_u32 v24, s2, s16, v23
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e64 v25, s2, s17, v0, s2
v_add_co_u32 v6, s2, s12, v16
v_add_co_ci_u32_e64 v7, s2, s13, v17, s2
v_add_co_u32 v8, s2, s22, v16
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e64 v9, s2, s23, v17, s2
v_add_co_u32 v10, s2, s26, v16
v_add_co_ci_u32_e64 v11, s2, s27, v17, s2
v_add_co_u32 v12, s2, s30, v16
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e64 v13, s2, s31, v17, s2
v_add_co_u32 v14, s2, s20, v16
v_add_co_ci_u32_e64 v15, s2, s21, v17, s2
v_add_co_u32 v16, s2, s28, v16
v_cmp_gt_i32_e64 s1, s7, v3
v_add_co_ci_u32_e64 v17, s2, s29, v17, s2
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v33, 0
v_dual_mov_b32 v28, 0 :: v_dual_mov_b32 v27, 0
s_mov_b64 s[4:5], 0
s_min_i32 s12, s34, s14
.LBB0_2: ; =>This Inner Loop Header: Depth=1
v_add_co_u32 v34, null, v23, s4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_le_i32_e64 s2, s8, v34
v_cmp_gt_i32_e64 s3, s12, v34
s_and_b32 s2, s3, s2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s3, s2, s1
s_and_saveexec_b32 s13, s3
s_cbranch_execz .LBB0_8
; %bb.3: ; in Loop: Header=BB0_2 Depth=1
v_add_co_u32 v29, s2, v24, s4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e64 v30, s2, s5, v25, s2
global_load_i8 v31, v[29:30], off
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[29:30], null, s7, v31, v[3:4]
v_ashrrev_i32_e32 v30, 31, v29
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[29:30], 2, v[29:30]
v_add_co_u32 v29, s2, s18, v29
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v30, s2, s19, v30, s2
global_load_b32 v29, v[29:30], off
ds_load_b32 v32, v18
ds_load_b32 v30, v19 offset:4
ds_load_b32 v31, v20 offset:4
s_and_saveexec_b32 s14, vcc_lo
s_cbranch_execz .LBB0_7
; %bb.4: ; in Loop: Header=BB0_2 Depth=1
s_waitcnt lgkmcnt(0)
global_load_b32 v32, v[14:15], off
global_load_b32 v30, v[10:11], off
global_load_b32 v31, v[16:17], off
v_add_co_u32 v35, null, v2, s4
s_mov_b32 s15, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_lt_i32_e32 0, v35
s_cbranch_execz .LBB0_6
; %bb.5: ; in Loop: Header=BB0_2 Depth=1
v_add_nc_u32_e32 v0, -1, v35
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[35:36], 2, v[0:1]
v_add_co_u32 v37, s2, s20, v35
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e64 v38, s2, s21, v36, s2
v_add_co_u32 v35, s2, s28, v35
v_add_co_ci_u32_e64 v36, s2, s29, v36, s2
global_load_b32 v33, v[37:38], off
global_load_b32 v0, v[35:36], off
.LBB0_6: ; in Loop: Header=BB0_2 Depth=1
s_or_b32 exec_lo, exec_lo, s15
s_cmp_eq_u32 s4, 0
s_cselect_b32 s2, -1, 0
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 s2, s9, s2
s_waitcnt vmcnt(0)
v_cndmask_b32_e64 v0, v0, v34, s2
.LBB0_7: ; %Flow221
; in Loop: Header=BB0_2 Depth=1
s_or_b32 exec_lo, exec_lo, s14
.LBB0_8: ; in Loop: Header=BB0_2 Depth=1
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s13
s_waitcnt vmcnt(0) lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_and_saveexec_b32 s13, s3
s_cbranch_execz .LBB0_18
; %bb.9: ; in Loop: Header=BB0_2 Depth=1
v_subrev_nc_u32_e32 v35, s10, v30
v_subrev_nc_u32_e32 v36, s11, v32
v_subrev_nc_u32_e32 v28, s10, v28
v_subrev_nc_u32_e32 v27, s11, v27
v_add_nc_u32_e32 v37, v29, v33
s_mov_b32 s3, exec_lo
v_max_i32_e32 v33, v35, v36
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_max_i32_e32 v28, v28, v27
v_max3_i32 v35, v33, v28, v37
s_delay_alu instid0(VALU_DEP_1)
v_max_i32_e32 v27, 0, v35
v_cmpx_lt_i32_e32 0, v35
s_xor_b32 s3, exec_lo, s3
; %bb.10: ; in Loop: Header=BB0_2 Depth=1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_eq_u32_e64 s2, v27, v28
; implicit-def: $vgpr34
v_cndmask_b32_e64 v0, v0, v26, s2
v_cmp_eq_u32_e64 s2, v27, v33
s_delay_alu instid0(VALU_DEP_1)
v_cndmask_b32_e64 v26, v0, v31, s2
; %bb.11: ; %Flow219
; in Loop: Header=BB0_2 Depth=1
s_and_not1_saveexec_b32 s2, s3
; %bb.12: ; in Loop: Header=BB0_2 Depth=1
v_add_nc_u32_e32 v26, 1, v34
; %bb.13: ; in Loop: Header=BB0_2 Depth=1
s_or_b32 exec_lo, exec_lo, s2
global_load_b32 v0, v[4:5], off
s_mov_b32 s3, exec_lo
ds_store_b32 v21, v33 offset:4
ds_store_b32 v18, v27 offset:4
ds_store_b32 v22, v26 offset:4
s_waitcnt vmcnt(0)
v_cmpx_ge_i32_e64 v27, v0
s_cbranch_execz .LBB0_15
; %bb.14: ; in Loop: Header=BB0_2 Depth=1
global_store_b32 v[4:5], v27, off
global_store_b32 v[6:7], v26, off
.LBB0_15: ; in Loop: Header=BB0_2 Depth=1
s_or_b32 exec_lo, exec_lo, s3
s_and_saveexec_b32 s2, s0
s_cbranch_execz .LBB0_17
; %bb.16: ; in Loop: Header=BB0_2 Depth=1
global_store_b32 v[8:9], v27, off
global_store_b32 v[10:11], v33, off
global_store_b32 v[12:13], v26, off
.LBB0_17: ; %Flow
; in Loop: Header=BB0_2 Depth=1
s_or_b32 exec_lo, exec_lo, s2
v_dual_mov_b32 v0, v31 :: v_dual_mov_b32 v33, v32
.LBB0_18: ; %Flow220
; in Loop: Header=BB0_2 Depth=1
s_or_b32 exec_lo, exec_lo, s13
v_add_co_u32 v4, s2, v4, 4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e64 v5, s2, 0, v5, s2
v_add_co_u32 v6, s2, v6, 4
v_add_co_ci_u32_e64 v7, s2, 0, v7, s2
v_add_co_u32 v8, s2, v8, 4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e64 v9, s2, 0, v9, s2
v_add_co_u32 v10, s2, v10, 4
v_add_co_ci_u32_e64 v11, s2, 0, v11, s2
v_add_co_u32 v12, s2, v12, 4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e64 v13, s2, 0, v13, s2
v_add_co_u32 v14, s2, v14, 4
v_add_co_ci_u32_e64 v15, s2, 0, v15, s2
v_add_co_u32 v16, s2, v16, 4
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v17, s2, 0, v17, s2
s_add_u32 s4, s4, 1
s_addc_u32 s5, s5, 0
s_cmp_eq_u32 s6, s4
s_waitcnt lgkmcnt(0)
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
s_cbranch_scc0 .LBB0_2
.LBB0_19: ; %._crit_edge
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z15calculateMatrixPKcPiS1_S1_S1_S1_S1_S1_S1_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 76
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 39
.amdhsa_next_free_sgpr 35
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z15calculateMatrixPKcPiS1_S1_S1_S1_S1_S1_S1_i, .Lfunc_end0-_Z15calculateMatrixPKcPiS1_S1_S1_S1_S1_S1_S1_i
; -- End function
.section .AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1356
; NumSgprs: 37
; NumVgprs: 39
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 4
; VGPRBlocks: 4
; NumSGPRsForWavesPerEU: 37
; NumVGPRsForWavesPerEU: 39
; Occupancy: 16
; WaveLimiterHint : 1
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.protected partSeqSize ; @partSeqSize
.type partSeqSize,@object
.section .bss,"aw",@nobits
.globl partSeqSize
.p2align 2, 0x0
partSeqSize:
.long 0 ; 0x0
.size partSeqSize, 4
.protected partsNumber ; @partsNumber
.type partsNumber,@object
.globl partsNumber
.p2align 2, 0x0
partsNumber:
.long 0 ; 0x0
.size partsNumber, 4
.protected overlapLength ; @overlapLength
.type overlapLength,@object
.globl overlapLength
.p2align 2, 0x0
overlapLength:
.long 0 ; 0x0
.size overlapLength, 4
.protected seqLibLength ; @seqLibLength
.type seqLibLength,@object
.globl seqLibLength
.p2align 2, 0x0
seqLibLength:
.long 0 ; 0x0
.size seqLibLength, 4
.protected queryLength ; @queryLength
.type queryLength,@object
.globl queryLength
.p2align 2, 0x0
queryLength:
.long 0 ; 0x0
.size queryLength, 4
.protected gapOpen ; @gapOpen
.type gapOpen,@object
.globl gapOpen
.p2align 2, 0x0
gapOpen:
.long 0 ; 0x0
.size gapOpen, 4
.protected gapExtension ; @gapExtension
.type gapExtension,@object
.globl gapExtension
.p2align 2, 0x0
gapExtension:
.long 0 ; 0x0
.size gapExtension, 4
.protected maxScore ; @maxScore
.type maxScore,@object
.globl maxScore
.p2align 2, 0x0
maxScore:
.long 0 ; 0x0
.size maxScore, 4
.protected queryPartLength ; @queryPartLength
.type queryPartLength,@object
.globl queryPartLength
.p2align 2, 0x0
queryPartLength:
.long 0 ; 0x0
.size queryPartLength, 4
.type __hip_cuid_,@object ; @__hip_cuid_
.globl __hip_cuid_
__hip_cuid_:
.byte 0 ; 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym partSeqSize
.addrsig_sym overlapLength
.addrsig_sym seqLibLength
.addrsig_sym queryLength
.addrsig_sym gapOpen
.addrsig_sym gapExtension
.addrsig_sym queryPartLength
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 40
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 48
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 56
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 64
.size: 8
.value_kind: global_buffer
- .offset: 72
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 76
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z15calculateMatrixPKcPiS1_S1_S1_S1_S1_S1_S1_i
.private_segment_fixed_size: 0
.sgpr_count: 37
.sgpr_spill_count: 0
.symbol: _Z15calculateMatrixPKcPiS1_S1_S1_S1_S1_S1_S1_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 39
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
```
| 5,743 | 7,383 |
19 |
Convert the following CUDA host assembly code to AMD host assembly:
```cudaasm
.file "tmpxft_000a6892_00000000-6_sw_cuda.cudafe1.cpp"
.text
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2031:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2031:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "partSeqSize"
.LC1:
.string "partsNumber"
.LC2:
.string "overlapLength"
.LC3:
.string "seqLibLength"
.LC4:
.string "queryLength"
.LC5:
.string "gapOpen"
.LC6:
.string "gapExtension"
.LC7:
.string "maxScore"
.LC8:
.string "queryPartLength"
.text
.globl _Z12setConstantsiiiiiiiii
.type _Z12setConstantsiiiiiiiii, @function
_Z12setConstantsiiiiiiiii:
.LFB2028:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
movl %edi, 28(%rsp)
movl %esi, 24(%rsp)
movl %edx, 20(%rsp)
movl %ecx, 16(%rsp)
movl %r8d, 12(%rsp)
movl %r9d, 8(%rsp)
leaq 28(%rsp), %rsi
movl $1, %r8d
movl $0, %ecx
movl $4, %edx
leaq .LC0(%rip), %rdi
call cudaMemcpyToSymbol@PLT
leaq 24(%rsp), %rsi
movl $1, %r8d
movl $0, %ecx
movl $4, %edx
leaq .LC1(%rip), %rdi
call cudaMemcpyToSymbol@PLT
leaq 20(%rsp), %rsi
movl $1, %r8d
movl $0, %ecx
movl $4, %edx
leaq .LC2(%rip), %rdi
call cudaMemcpyToSymbol@PLT
leaq 16(%rsp), %rsi
movl $1, %r8d
movl $0, %ecx
movl $4, %edx
leaq .LC3(%rip), %rdi
call cudaMemcpyToSymbol@PLT
leaq 12(%rsp), %rsi
movl $1, %r8d
movl $0, %ecx
movl $4, %edx
leaq .LC4(%rip), %rdi
call cudaMemcpyToSymbol@PLT
leaq 8(%rsp), %rsi
movl $1, %r8d
movl $0, %ecx
movl $4, %edx
leaq .LC5(%rip), %rdi
call cudaMemcpyToSymbol@PLT
movl $1, %r8d
movl $0, %ecx
movl $4, %edx
leaq 48(%rsp), %rsi
leaq .LC6(%rip), %rdi
call cudaMemcpyToSymbol@PLT
leaq 56(%rsp), %rsi
movl $1, %r8d
movl $0, %ecx
movl $4, %edx
leaq .LC7(%rip), %rdi
call cudaMemcpyToSymbol@PLT
leaq 64(%rsp), %rsi
movl $1, %r8d
movl $0, %ecx
movl $4, %edx
leaq .LC8(%rip), %rdi
call cudaMemcpyToSymbol@PLT
addq $40, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2028:
.size _Z12setConstantsiiiiiiiii, .-_Z12setConstantsiiiiiiiii
.globl _Z60__device_stub__Z15calculateMatrixPKcPiS1_S1_S1_S1_S1_S1_S1_iPKcPiS1_S1_S1_S1_S1_S1_S1_i
.type _Z60__device_stub__Z15calculateMatrixPKcPiS1_S1_S1_S1_S1_S1_S1_iPKcPiS1_S1_S1_S1_S1_S1_S1_i, @function
_Z60__device_stub__Z15calculateMatrixPKcPiS1_S1_S1_S1_S1_S1_S1_iPKcPiS1_S1_S1_S1_S1_S1_S1_i:
.LFB2053:
.cfi_startproc
endbr64
subq $248, %rsp
.cfi_def_cfa_offset 256
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movq %rcx, 48(%rsp)
movq %r8, 40(%rsp)
movq %r9, 32(%rsp)
movq 256(%rsp), %rax
movq %rax, 24(%rsp)
movq 264(%rsp), %rax
movq %rax, 16(%rsp)
movq 272(%rsp), %rax
movq %rax, 8(%rsp)
movq %fs:40, %rax
movq %rax, 232(%rsp)
xorl %eax, %eax
leaq 72(%rsp), %rax
movq %rax, 144(%rsp)
leaq 64(%rsp), %rax
movq %rax, 152(%rsp)
leaq 56(%rsp), %rax
movq %rax, 160(%rsp)
leaq 48(%rsp), %rax
movq %rax, 168(%rsp)
leaq 40(%rsp), %rax
movq %rax, 176(%rsp)
leaq 32(%rsp), %rax
movq %rax, 184(%rsp)
leaq 24(%rsp), %rax
movq %rax, 192(%rsp)
leaq 16(%rsp), %rax
movq %rax, 200(%rsp)
leaq 8(%rsp), %rax
movq %rax, 208(%rsp)
leaq 280(%rsp), %rax
movq %rax, 216(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
movl $1, 104(%rsp)
movl $1, 108(%rsp)
movl $1, 112(%rsp)
movl $1, 116(%rsp)
leaq 88(%rsp), %rcx
leaq 80(%rsp), %rdx
leaq 108(%rsp), %rsi
leaq 96(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L9
.L5:
movq 232(%rsp), %rax
subq %fs:40, %rax
jne .L10
addq $248, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L9:
.cfi_restore_state
pushq 88(%rsp)
.cfi_def_cfa_offset 264
pushq 88(%rsp)
.cfi_def_cfa_offset 272
leaq 160(%rsp), %r9
movq 124(%rsp), %rcx
movl 132(%rsp), %r8d
movq 112(%rsp), %rsi
movl 120(%rsp), %edx
leaq _Z15calculateMatrixPKcPiS1_S1_S1_S1_S1_S1_S1_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 256
jmp .L5
.L10:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2053:
.size _Z60__device_stub__Z15calculateMatrixPKcPiS1_S1_S1_S1_S1_S1_S1_iPKcPiS1_S1_S1_S1_S1_S1_S1_i, .-_Z60__device_stub__Z15calculateMatrixPKcPiS1_S1_S1_S1_S1_S1_S1_iPKcPiS1_S1_S1_S1_S1_S1_S1_i
.globl _Z15calculateMatrixPKcPiS1_S1_S1_S1_S1_S1_S1_i
.type _Z15calculateMatrixPKcPiS1_S1_S1_S1_S1_S1_S1_i, @function
_Z15calculateMatrixPKcPiS1_S1_S1_S1_S1_S1_S1_i:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 24
pushq 40(%rsp)
.cfi_def_cfa_offset 32
pushq 40(%rsp)
.cfi_def_cfa_offset 40
pushq 40(%rsp)
.cfi_def_cfa_offset 48
call _Z60__device_stub__Z15calculateMatrixPKcPiS1_S1_S1_S1_S1_S1_S1_iPKcPiS1_S1_S1_S1_S1_S1_S1_i
addq $40, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _Z15calculateMatrixPKcPiS1_S1_S1_S1_S1_S1_S1_i, .-_Z15calculateMatrixPKcPiS1_S1_S1_S1_S1_S1_S1_i
.globl _Z20calculateMatrix_wrapiiPKcPiS1_S1_S1_S1_S1_S1_S1_i
.type _Z20calculateMatrix_wrapiiPKcPiS1_S1_S1_S1_S1_S1_S1_i, @function
_Z20calculateMatrix_wrapiiPKcPiS1_S1_S1_S1_S1_S1_S1_i:
.LFB2027:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $40, %rsp
.cfi_def_cfa_offset 80
movq %rdx, %rbx
movq %rcx, %rbp
movq %r8, %r12
movq %r9, %r13
movl %esi, 20(%rsp)
movl $1, 24(%rsp)
movl %edi, 8(%rsp)
movl $1, 12(%rsp)
addl $1, %esi
movslq %esi, %rsi
leaq (%rsi,%rsi,2), %rax
movl $0, %r9d
leaq 0(,%rax,4), %r8
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L16
.L13:
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L16:
.cfi_restore_state
movl 120(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 88
pushq 120(%rsp)
.cfi_def_cfa_offset 96
pushq 120(%rsp)
.cfi_def_cfa_offset 104
pushq 120(%rsp)
.cfi_def_cfa_offset 112
movq 120(%rsp), %r9
movq 112(%rsp), %r8
movq %r13, %rcx
movq %r12, %rdx
movq %rbp, %rsi
movq %rbx, %rdi
call _Z60__device_stub__Z15calculateMatrixPKcPiS1_S1_S1_S1_S1_S1_S1_iPKcPiS1_S1_S1_S1_S1_S1_S1_i
addq $32, %rsp
.cfi_def_cfa_offset 80
jmp .L13
.cfi_endproc
.LFE2027:
.size _Z20calculateMatrix_wrapiiPKcPiS1_S1_S1_S1_S1_S1_S1_i, .-_Z20calculateMatrix_wrapiiPKcPiS1_S1_S1_S1_S1_S1_S1_i
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC9:
.string "_Z15calculateMatrixPKcPiS1_S1_S1_S1_S1_S1_S1_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2056:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC9(%rip), %rdx
movq %rdx, %rcx
leaq _Z15calculateMatrixPKcPiS1_S1_S1_S1_S1_S1_S1_i(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $4, %r9d
movl $0, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _ZL11partSeqSize(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $4, %r9d
movl $0, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _ZL11partsNumber(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $4, %r9d
movl $0, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _ZL13overlapLength(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $4, %r9d
movl $0, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _ZL12seqLibLength(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $4, %r9d
movl $0, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _ZL11queryLength(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $4, %r9d
movl $0, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _ZL7gapOpen(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $4, %r9d
movl $0, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _ZL12gapExtension(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $4, %r9d
movl $0, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _ZL8maxScore(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $4, %r9d
movl $0, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _ZL15queryPartLength(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2056:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZL15queryPartLength
.comm _ZL15queryPartLength,4,4
.local _ZL8maxScore
.comm _ZL8maxScore,4,4
.local _ZL12gapExtension
.comm _ZL12gapExtension,4,4
.local _ZL7gapOpen
.comm _ZL7gapOpen,4,4
.local _ZL11queryLength
.comm _ZL11queryLength,4,4
.local _ZL12seqLibLength
.comm _ZL12seqLibLength,4,4
.local _ZL13overlapLength
.comm _ZL13overlapLength,4,4
.local _ZL11partsNumber
.comm _ZL11partsNumber,4,4
.local _ZL11partSeqSize
.comm _ZL11partSeqSize,4,4
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
```
|
```amdasm
.text
.file "sw_cuda.hip"
.globl _Z30__device_stub__calculateMatrixPKcPiS1_S1_S1_S1_S1_S1_S1_i # -- Begin function _Z30__device_stub__calculateMatrixPKcPiS1_S1_S1_S1_S1_S1_S1_i
.type _Z30__device_stub__calculateMatrixPKcPiS1_S1_S1_S1_S1_S1_S1_i,@function
_Z30__device_stub__calculateMatrixPKcPiS1_S1_S1_S1_S1_S1_S1_i: # @_Z30__device_stub__calculateMatrixPKcPiS1_S1_S1_S1_S1_S1_S1_i
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $176, %rsp
.cfi_def_cfa_offset 224
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 56(%rsp), %rax
movq %rdi, (%rax)
leaq 48(%rsp), %rdi
movq %rsi, (%rdi)
leaq 40(%rsp), %rsi
movq %rdx, (%rsi)
leaq 32(%rsp), %rdx
movq %rcx, (%rdx)
leaq 24(%rsp), %rcx
movq %r8, (%rcx)
leaq 16(%rsp), %r8
movq %r9, (%r8)
leaq 96(%rsp), %rbx
movq %rax, (%rbx)
movq %rdi, 8(%rbx)
movq %rsi, 16(%rbx)
movq %rdx, 24(%rbx)
movq %rcx, 32(%rbx)
movq %r8, 40(%rbx)
leaq 224(%rsp), %rax
movq %rax, 48(%rbx)
leaq 232(%rsp), %rax
movq %rax, 56(%rbx)
leaq 240(%rsp), %rax
movq %rax, 64(%rbx)
leaq 248(%rsp), %rax
movq %rax, 72(%rbx)
leaq 80(%rsp), %r14
leaq 64(%rsp), %r15
leaq 8(%rsp), %r12
movq %rsp, %r13
movq %r14, %rdi
movq %r15, %rsi
movq %r12, %rdx
movq %r13, %rcx
callq __hipPopCallConfiguration
movq (%r14), %rsi
movl 8(%r14), %edx
movq (%r15), %rcx
movl 8(%r15), %r8d
movl $_Z15calculateMatrixPKcPiS1_S1_S1_S1_S1_S1_S1_i, %edi
movq %rbx, %r9
pushq (%r13)
.cfi_adjust_cfa_offset 8
pushq (%r12)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $192, %rsp
.cfi_adjust_cfa_offset -192
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z30__device_stub__calculateMatrixPKcPiS1_S1_S1_S1_S1_S1_S1_i, .Lfunc_end0-_Z30__device_stub__calculateMatrixPKcPiS1_S1_S1_S1_S1_S1_S1_i
.cfi_endproc
# -- End function
.globl _Z20calculateMatrix_wrapiiPKcPiS1_S1_S1_S1_S1_S1_S1_i # -- Begin function _Z20calculateMatrix_wrapiiPKcPiS1_S1_S1_S1_S1_S1_S1_i
.type _Z20calculateMatrix_wrapiiPKcPiS1_S1_S1_S1_S1_S1_S1_i,@function
_Z20calculateMatrix_wrapiiPKcPiS1_S1_S1_S1_S1_S1_S1_i: # @_Z20calculateMatrix_wrapiiPKcPiS1_S1_S1_S1_S1_S1_S1_i
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
pushq %rax
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %r9, %rbx
movq %r8, %r14
movq %rcx, %r15
movq %rdx, %r12
movslq %esi, %rax
leaq (,%rax,4), %rcx
leaq (%rcx,%rcx,2), %r8
addq $12, %r8
movl %edi, %edi
btsq $32, %rdi
movl %eax, %edx
btsq $32, %rdx
movl $1, %esi
movl $1, %ecx
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
je .LBB1_1
# %bb.2:
addq $8, %rsp
.cfi_def_cfa_offset 40
jmp .LBB1_3
.LBB1_1:
.cfi_def_cfa_offset 48
movl 88(%rsp), %eax
movq 56(%rsp), %r9
movq 48(%rsp), %r8
movq %r12, %rdi
movq %r15, %rsi
movq %r14, %rdx
movq %rbx, %rcx
pushq %rax
.cfi_adjust_cfa_offset 8
pushq 88(%rsp)
.cfi_adjust_cfa_offset 8
pushq 88(%rsp)
.cfi_adjust_cfa_offset 8
pushq 88(%rsp)
.cfi_adjust_cfa_offset 8
callq _Z30__device_stub__calculateMatrixPKcPiS1_S1_S1_S1_S1_S1_S1_i
addq $40, %rsp
.cfi_adjust_cfa_offset -40
.LBB1_3:
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z20calculateMatrix_wrapiiPKcPiS1_S1_S1_S1_S1_S1_S1_i, .Lfunc_end1-_Z20calculateMatrix_wrapiiPKcPiS1_S1_S1_S1_S1_S1_S1_i
.cfi_endproc
# -- End function
.globl _Z12setConstantsiiiiiiiii # -- Begin function _Z12setConstantsiiiiiiiii
.type _Z12setConstantsiiiiiiiii,@function
_Z12setConstantsiiiiiiiii: # @_Z12setConstantsiiiiiiiii
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $32, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 28(%rsp), %rax
movl %edi, (%rax)
leaq 24(%rsp), %r13
movl %esi, (%r13)
leaq 20(%rsp), %r12
movl %edx, (%r12)
leaq 16(%rsp), %r15
movl %ecx, (%r15)
leaq 12(%rsp), %r14
movl %r8d, (%r14)
leaq 8(%rsp), %rbx
movl %r9d, (%rbx)
movl $.L.str, %edi
movl $4, %edx
movq %rax, %rsi
xorl %ecx, %ecx
movl $1, %r8d
callq hipMemcpyToSymbol
movl $.L.str.1, %edi
movl $4, %edx
movq %r13, %rsi
xorl %ecx, %ecx
movl $1, %r8d
callq hipMemcpyToSymbol
movl $.L.str.2, %edi
movl $4, %edx
movq %r12, %rsi
xorl %ecx, %ecx
movl $1, %r8d
callq hipMemcpyToSymbol
movl $.L.str.3, %edi
movl $4, %edx
movq %r15, %rsi
xorl %ecx, %ecx
movl $1, %r8d
callq hipMemcpyToSymbol
movl $.L.str.4, %edi
movl $4, %edx
movq %r14, %rsi
xorl %ecx, %ecx
movl $1, %r8d
callq hipMemcpyToSymbol
movl $.L.str.5, %edi
movl $4, %edx
movq %rbx, %rsi
xorl %ecx, %ecx
movl $1, %r8d
callq hipMemcpyToSymbol
leaq 80(%rsp), %rsi
movl $.L.str.6, %edi
movl $4, %edx
xorl %ecx, %ecx
movl $1, %r8d
callq hipMemcpyToSymbol
leaq 88(%rsp), %rsi
movl $.L.str.7, %edi
movl $4, %edx
xorl %ecx, %ecx
movl $1, %r8d
callq hipMemcpyToSymbol
leaq 96(%rsp), %rsi
movl $.L.str.8, %edi
movl $4, %edx
xorl %ecx, %ecx
movl $1, %r8d
callq hipMemcpyToSymbol
addq $32, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size _Z12setConstantsiiiiiiiii, .Lfunc_end2-_Z12setConstantsiiiiiiiii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
movq __hip_gpubin_handle(%rip), %rbx
testq %rbx, %rbx
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, %rbx
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
subq $32, %rsp
.cfi_adjust_cfa_offset 32
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15calculateMatrixPKcPiS1_S1_S1_S1_S1_S1_S1_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
addq $32, %rsp
.cfi_adjust_cfa_offset -32
movl $partSeqSize, %esi
movl $.L.str, %edx
movl $.L.str, %ecx
movl $4, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
pushq $0
.cfi_adjust_cfa_offset 8
pushq $1
.cfi_adjust_cfa_offset 8
callq __hipRegisterVar
addq $16, %rsp
.cfi_adjust_cfa_offset -16
movl $partsNumber, %esi
movl $.L.str.1, %edx
movl $.L.str.1, %ecx
movl $4, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
pushq $0
.cfi_adjust_cfa_offset 8
pushq $1
.cfi_adjust_cfa_offset 8
callq __hipRegisterVar
addq $16, %rsp
.cfi_adjust_cfa_offset -16
movl $overlapLength, %esi
movl $.L.str.2, %edx
movl $.L.str.2, %ecx
movl $4, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
pushq $0
.cfi_adjust_cfa_offset 8
pushq $1
.cfi_adjust_cfa_offset 8
callq __hipRegisterVar
addq $16, %rsp
.cfi_adjust_cfa_offset -16
movl $seqLibLength, %esi
movl $.L.str.3, %edx
movl $.L.str.3, %ecx
movl $4, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
pushq $0
.cfi_adjust_cfa_offset 8
pushq $1
.cfi_adjust_cfa_offset 8
callq __hipRegisterVar
addq $16, %rsp
.cfi_adjust_cfa_offset -16
movl $queryLength, %esi
movl $.L.str.4, %edx
movl $.L.str.4, %ecx
movl $4, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
pushq $0
.cfi_adjust_cfa_offset 8
pushq $1
.cfi_adjust_cfa_offset 8
callq __hipRegisterVar
addq $16, %rsp
.cfi_adjust_cfa_offset -16
movl $gapOpen, %esi
movl $.L.str.5, %edx
movl $.L.str.5, %ecx
movl $4, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
pushq $0
.cfi_adjust_cfa_offset 8
pushq $1
.cfi_adjust_cfa_offset 8
callq __hipRegisterVar
addq $16, %rsp
.cfi_adjust_cfa_offset -16
movl $gapExtension, %esi
movl $.L.str.6, %edx
movl $.L.str.6, %ecx
movl $4, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
pushq $0
.cfi_adjust_cfa_offset 8
pushq $1
.cfi_adjust_cfa_offset 8
callq __hipRegisterVar
addq $16, %rsp
.cfi_adjust_cfa_offset -16
movl $maxScore, %esi
movl $.L.str.7, %edx
movl $.L.str.7, %ecx
movl $4, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
pushq $0
.cfi_adjust_cfa_offset 8
pushq $1
.cfi_adjust_cfa_offset 8
callq __hipRegisterVar
addq $16, %rsp
.cfi_adjust_cfa_offset -16
movl $queryPartLength, %esi
movl $.L.str.8, %edx
movl $.L.str.8, %ecx
movl $4, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
pushq $0
.cfi_adjust_cfa_offset 8
pushq $1
.cfi_adjust_cfa_offset 8
callq __hipRegisterVar
addq $16, %rsp
.cfi_adjust_cfa_offset -16
movl $__hip_module_dtor, %edi
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type partSeqSize,@object # @partSeqSize
.local partSeqSize
.comm partSeqSize,4,4
.type partsNumber,@object # @partsNumber
.local partsNumber
.comm partsNumber,4,4
.type overlapLength,@object # @overlapLength
.local overlapLength
.comm overlapLength,4,4
.type seqLibLength,@object # @seqLibLength
.local seqLibLength
.comm seqLibLength,4,4
.type queryLength,@object # @queryLength
.local queryLength
.comm queryLength,4,4
.type gapOpen,@object # @gapOpen
.local gapOpen
.comm gapOpen,4,4
.type gapExtension,@object # @gapExtension
.local gapExtension
.comm gapExtension,4,4
.type maxScore,@object # @maxScore
.local maxScore
.comm maxScore,4,4
.type queryPartLength,@object # @queryPartLength
.local queryPartLength
.comm queryPartLength,4,4
.type _Z15calculateMatrixPKcPiS1_S1_S1_S1_S1_S1_S1_i,@object # @_Z15calculateMatrixPKcPiS1_S1_S1_S1_S1_S1_S1_i
.section .rodata,"a",@progbits
.globl _Z15calculateMatrixPKcPiS1_S1_S1_S1_S1_S1_S1_i
.p2align 3, 0x0
_Z15calculateMatrixPKcPiS1_S1_S1_S1_S1_S1_S1_i:
.quad _Z30__device_stub__calculateMatrixPKcPiS1_S1_S1_S1_S1_S1_S1_i
.size _Z15calculateMatrixPKcPiS1_S1_S1_S1_S1_S1_S1_i, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "partSeqSize"
.size .L.str, 12
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "partsNumber"
.size .L.str.1, 12
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "overlapLength"
.size .L.str.2, 14
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "seqLibLength"
.size .L.str.3, 13
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "queryLength"
.size .L.str.4, 12
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "gapOpen"
.size .L.str.5, 8
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "gapExtension"
.size .L.str.6, 13
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "maxScore"
.size .L.str.7, 9
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "queryPartLength"
.size .L.str.8, 16
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z15calculateMatrixPKcPiS1_S1_S1_S1_S1_S1_S1_i"
.size .L__unnamed_1, 47
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z30__device_stub__calculateMatrixPKcPiS1_S1_S1_S1_S1_S1_S1_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym partSeqSize
.addrsig_sym partsNumber
.addrsig_sym overlapLength
.addrsig_sym seqLibLength
.addrsig_sym queryLength
.addrsig_sym gapOpen
.addrsig_sym gapExtension
.addrsig_sym maxScore
.addrsig_sym queryPartLength
.addrsig_sym _Z15calculateMatrixPKcPiS1_S1_S1_S1_S1_S1_S1_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
```
| 5,843 | 6,480 |
20 |
Convert the following CUDA device assembly code to AMD device assembly:
```cudaasm
code for sm_80
Function : _Z24ForwardEliminationColumnPdPiS0_S0_S0_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ;
IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x168] ;
ULDC.64 UR4, c[0x0][0x118] ;
IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x16c] ;
IMAD.MOV.U32 R6, RZ, RZ, c[0x0][0x180] ;
IMAD.MOV.U32 R7, RZ, RZ, c[0x0][0x184] ;
LDG.E R0, [R4.64] ;
LDG.E R6, [R6.64] ;
IMAD.MOV.U32 R10, RZ, RZ, c[0x0][0x170] ;
IMAD.MOV.U32 R11, RZ, RZ, c[0x0][0x174] ;
LDG.E R10, [R10.64] ;
IMAD.MOV.U32 R13, RZ, RZ, 0x8 ;
IMAD.MOV.U32 R16, RZ, RZ, c[0x0][0x178] ;
IMAD.MOV.U32 R17, RZ, RZ, c[0x0][0x17c] ;
LDG.E R16, [R16.64] ;
IADD3 R3, R0, 0x1, RZ ;
IMAD R2, R3, R6, RZ ;
IMAD.IADD R8, R6, 0x1, R2 ;
IMAD.WIDE R8, R8, R13, c[0x0][0x160] ;
LDG.E.64 R8, [R8.64] ;
IMAD R3, R3, R10, RZ ;
IMAD.IADD R12, R6, 0x1, R3 ;
IMAD.WIDE R12, R12, R13, c[0x0][0x160] ;
LDG.E.64 R12, [R12.64] ;
IMAD.MOV.U32 R4, RZ, RZ, 0x1 ;
S2R R14, SR_CTAID.X ;
S2R R15, SR_TID.X ;
MUFU.RCP64H R5, R9 ;
DFMA R6, -R8, R4, 1 ;
DFMA R6, R6, R6, R6 ;
DFMA R6, R4, R6, R4 ;
DFMA R4, -R8, R6, 1 ;
DFMA R4, R6, R4, R6 ;
DMUL R10, R12, R4 ;
DFMA R6, -R8, R10, R12 ;
DFMA R10, R4, R6, R10 ;
FSETP.GEU.AND P1, PT, |R13|, 6.5827683646048100446e-37, PT ;
FFMA R4, RZ, R9, R11 ;
FSETP.GT.AND P0, PT, |R4|, 1.469367938527859385e-39, PT ;
IMAD R5, R14, c[0x0][0x0], R15 ;
IMAD R4, R5, R16, RZ ;
@P0 BRA P1, 0x2c0 ;
MOV R22, 0x2c0 ;
CALL.REL.NOINC 0x840 ;
ISETP.GE.AND P0, PT, R16, 0x1, PT ;
@!P0 EXIT ;
IADD3 R6, R16.reuse, -0x1, RZ ;
IMAD.MOV.U32 R9, RZ, RZ, RZ ;
LOP3.LUT R5, R16, 0x3, RZ, 0xc0, !PT ;
ISETP.GE.U32.AND P1, PT, R6, 0x3, PT ;
ISETP.NE.AND P0, PT, R5, RZ, PT ;
@!P1 BRA 0x660 ;
BSSY B0, 0x660 ;
IMAD.IADD R8, R5, 0x1, -R16 ;
IADD3 R7, R4.reuse, 0x3, RZ ;
IMAD.IADD R6, R4.reuse, 0x1, R3 ;
IMAD.IADD R23, R4, 0x1, R2 ;
IMAD.MOV.U32 R9, RZ, RZ, RZ ;
IMAD.MOV.U32 R12, RZ, RZ, c[0x0][0x160] ;
IMAD.MOV.U32 R21, RZ, RZ, c[0x0][0x164] ;
IADD3 R13, R7, -0x3, RZ ;
ISETP.GT.AND P2, PT, R13, R0, PT ;
IMAD.MOV.U32 R13, RZ, RZ, R21 ;
IMAD.WIDE R16, R23, 0x8, R12 ;
IMAD.WIDE R14, R6, 0x8, R12 ;
@!P2 LDG.E.64 R20, [R16.64] ;
@!P2 LDG.E.64 R18, [R14.64] ;
IADD3 R25, R7, -0x2, RZ ;
@!P2 WARPSYNC 0xffffffff ;
ISETP.GT.AND P1, PT, R25, R0, PT ;
@!P2 DFMA R24, R20, -R10, R18 ;
@!P2 STG.E.64 [R14.64], R24 ;
@!P2 BAR.SYNC.DEFER_BLOCKING 0x0 ;
@!P1 LDG.E.64 R18, [R16.64+0x8] ;
@!P1 LDG.E.64 R20, [R14.64+0x8] ;
IADD3 R27, R7, -0x1, RZ ;
@!P1 WARPSYNC 0xffffffff ;
ISETP.GT.AND P2, PT, R27, R0, PT ;
@!P1 DFMA R26, R18, -R10, R20 ;
@!P1 STG.E.64 [R14.64+0x8], R26 ;
@!P1 BAR.SYNC.DEFER_BLOCKING 0x0 ;
@!P2 LDG.E.64 R18, [R16.64+0x10] ;
@!P2 LDG.E.64 R20, [R14.64+0x10] ;
@!P2 WARPSYNC 0xffffffff ;
ISETP.GT.AND P1, PT, R7, R0, PT ;
@!P2 DFMA R24, R18, -R10, R20 ;
@!P2 STG.E.64 [R14.64+0x10], R24 ;
@!P2 BAR.SYNC.DEFER_BLOCKING 0x0 ;
@!P1 LDG.E.64 R20, [R16.64+0x18] ;
@!P1 LDG.E.64 R18, [R14.64+0x18] ;
IADD3 R8, R8, 0x4, RZ ;
@!P1 WARPSYNC 0xffffffff ;
IADD3 R9, R9, 0x4, RZ ;
ISETP.NE.AND P2, PT, R8, RZ, PT ;
IADD3 R7, R7, 0x4, RZ ;
@!P1 DFMA R18, R20, -R10, R18 ;
@!P1 STG.E.64 [R14.64+0x18], R18 ;
@!P1 BAR.SYNC.DEFER_BLOCKING 0x0 ;
IADD3 R12, P1, R12, 0x20, RZ ;
IMAD.X R21, RZ, RZ, R13, P1 ;
@P2 BRA 0x3c0 ;
BSYNC B0 ;
@!P0 EXIT ;
IMAD.IADD R15, R4, 0x1, R9 ;
IMAD.MOV.U32 R7, RZ, RZ, 0x8 ;
IMAD.IADD R3, R3, 0x1, R15.reuse ;
IMAD.IADD R6, R2, 0x1, R15 ;
IMAD.WIDE R2, R3, R7, c[0x0][0x160] ;
IMAD.WIDE R6, R6, R7, c[0x0][0x160] ;
IMAD.MOV.U32 R14, RZ, RZ, R2 ;
IMAD.MOV.U32 R17, RZ, RZ, R3 ;
IMAD.MOV.U32 R4, RZ, RZ, R6 ;
IMAD.MOV.U32 R13, RZ, RZ, R7 ;
ISETP.GT.AND P0, PT, R15, R0, PT ;
IMAD.MOV.U32 R8, RZ, RZ, R14 ;
IMAD.MOV.U32 R9, RZ, RZ, R17 ;
@!P0 IMAD.MOV.U32 R12, RZ, RZ, R4 ;
@!P0 LDG.E.64 R6, [R8.64] ;
@!P0 LDG.E.64 R2, [R12.64] ;
IADD3 R5, R5, -0x1, RZ ;
@!P0 WARPSYNC 0xffffffff ;
IADD3 R14, P1, R8, 0x8, RZ ;
IADD3 R4, P2, R4, 0x8, RZ ;
IADD3 R15, R15, 0x1, RZ ;
IMAD.X R17, RZ, RZ, R9, P1 ;
IMAD.X R13, RZ, RZ, R13, P2 ;
@!P0 DFMA R2, R2, -R10, R6 ;
@!P0 STG.E.64 [R8.64], R2 ;
@!P0 BAR.SYNC.DEFER_BLOCKING 0x0 ;
ISETP.NE.AND P0, PT, R5, RZ, PT ;
@P0 BRA 0x710 ;
EXIT ;
FSETP.GEU.AND P0, PT, |R9|.reuse, 1.469367938527859385e-39, PT ;
IMAD.MOV.U32 R14, RZ, RZ, 0x1 ;
LOP3.LUT R6, R9.reuse, 0x800fffff, RZ, 0xc0, !PT ;
IMAD.MOV.U32 R17, RZ, RZ, 0x1ca00000 ;
LOP3.LUT R23, R9, 0x7ff00000, RZ, 0xc0, !PT ;
LOP3.LUT R7, R6, 0x3ff00000, RZ, 0xfc, !PT ;
IMAD.MOV.U32 R6, RZ, RZ, R8 ;
@!P0 DMUL R6, R8, 8.98846567431157953865e+307 ;
MUFU.RCP64H R15, R7 ;
DFMA R10, R14, -R6, 1 ;
DFMA R18, R10, R10, R10 ;
IMAD.MOV.U32 R11, RZ, RZ, R13 ;
IMAD.MOV.U32 R10, RZ, RZ, R12 ;
DFMA R14, R14, R18, R14 ;
LOP3.LUT R5, R11, 0x7ff00000, RZ, 0xc0, !PT ;
ISETP.GE.U32.AND P1, PT, R5, R23, PT ;
DFMA R12, R14.reuse, -R6, 1 ;
IMAD.MOV.U32 R24, RZ, RZ, R5 ;
@!P0 LOP3.LUT R23, R7, 0x7ff00000, RZ, 0xc0, !PT ;
SEL R19, R17, 0x63400000, !P1 ;
FSETP.GEU.AND P1, PT, |R11|, 1.469367938527859385e-39, PT ;
DFMA R14, R14, R12, R14 ;
LOP3.LUT R13, R19, 0x800fffff, R11, 0xf8, !PT ;
IMAD.MOV.U32 R12, RZ, RZ, R10 ;
@P1 BRA 0xa50 ;
LOP3.LUT R18, R9, 0x7ff00000, RZ, 0xc0, !PT ;
ISETP.GE.U32.AND P0, PT, R5, R18, PT ;
IMAD.MOV.U32 R18, RZ, RZ, RZ ;
SEL R19, R17, 0x63400000, !P0 ;
LOP3.LUT R19, R19, 0x80000000, R11, 0xf8, !PT ;
LOP3.LUT R19, R19, 0x100000, RZ, 0xfc, !PT ;
DFMA R12, R12, 2, -R18 ;
LOP3.LUT R24, R13, 0x7ff00000, RZ, 0xc0, !PT ;
IADD3 R20, R24, -0x1, RZ ;
DMUL R18, R14, R12 ;
IADD3 R25, R23, -0x1, RZ ;
ISETP.GT.U32.AND P0, PT, R20, 0x7feffffe, PT ;
DFMA R20, R18, -R6, R12 ;
ISETP.GT.U32.OR P0, PT, R25, 0x7feffffe, P0 ;
DFMA R20, R14, R20, R18 ;
@P0 BRA 0xc90 ;
LOP3.LUT R14, R9, 0x7ff00000, RZ, 0xc0, !PT ;
ISETP.GE.U32.AND P0, PT, R5.reuse, R14, PT ;
IMAD.IADD R10, R5, 0x1, -R14 ;
SEL R14, R17, 0x63400000, !P0 ;
IMNMX R10, R10, -0x46a00000, !PT ;
IMNMX R5, R10, 0x46a00000, PT ;
IMAD.MOV.U32 R10, RZ, RZ, RZ ;
IMAD.IADD R5, R5, 0x1, -R14 ;
IADD3 R11, R5, 0x7fe00000, RZ ;
DMUL R14, R20, R10 ;
FSETP.GTU.AND P0, PT, |R15|, 1.469367938527859385e-39, PT ;
@P0 BRA 0xde0 ;
DFMA R6, R20, -R6, R12 ;
IMAD.MOV.U32 R10, RZ, RZ, RZ ;
FSETP.NEU.AND P0, PT, R7.reuse, RZ, PT ;
LOP3.LUT R9, R7, 0x80000000, R9, 0x48, !PT ;
LOP3.LUT R11, R9, R11, RZ, 0xfc, !PT ;
@!P0 BRA 0xde0 ;
IMAD.MOV R7, RZ, RZ, -R5 ;
DMUL.RP R10, R20, R10 ;
IMAD.MOV.U32 R6, RZ, RZ, RZ ;
IADD3 R5, -R5, -0x43300000, RZ ;
DFMA R6, R14, -R6, R20 ;
LOP3.LUT R9, R11, R9, RZ, 0x3c, !PT ;
FSETP.NEU.AND P0, PT, |R7|, R5, PT ;
FSEL R14, R10, R14, !P0 ;
FSEL R15, R9, R15, !P0 ;
BRA 0xde0 ;
DSETP.NAN.AND P0, PT, R10, R10, PT ;
@P0 BRA 0xdc0 ;
DSETP.NAN.AND P0, PT, R8, R8, PT ;
@P0 BRA 0xd90 ;
ISETP.NE.AND P0, PT, R24, R23, PT ;
IMAD.MOV.U32 R14, RZ, RZ, 0x0 ;
IMAD.MOV.U32 R15, RZ, RZ, -0x80000 ;
@!P0 BRA 0xde0 ;
ISETP.NE.AND P0, PT, R24, 0x7ff00000, PT ;
LOP3.LUT R15, R11, 0x80000000, R9, 0x48, !PT ;
ISETP.EQ.OR P0, PT, R23, RZ, !P0 ;
@P0 LOP3.LUT R5, R15, 0x7ff00000, RZ, 0xfc, !PT ;
@!P0 IMAD.MOV.U32 R14, RZ, RZ, RZ ;
@P0 IMAD.MOV.U32 R14, RZ, RZ, RZ ;
@P0 IMAD.MOV.U32 R15, RZ, RZ, R5 ;
BRA 0xde0 ;
LOP3.LUT R15, R9, 0x80000, RZ, 0xfc, !PT ;
IMAD.MOV.U32 R14, RZ, RZ, R8 ;
BRA 0xde0 ;
LOP3.LUT R15, R11, 0x80000, RZ, 0xfc, !PT ;
IMAD.MOV.U32 R14, RZ, RZ, R10 ;
IMAD.MOV.U32 R23, RZ, RZ, 0x0 ;
IMAD.MOV.U32 R10, RZ, RZ, R14 ;
IMAD.MOV.U32 R11, RZ, RZ, R15 ;
RET.REL.NODEC R22 0x0 ;
BRA 0xe20;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
```
|
```amdasm
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z24ForwardEliminationColumnPdPiS0_S0_S0_ ; -- Begin function _Z24ForwardEliminationColumnPdPiS0_S0_S0_
.globl _Z24ForwardEliminationColumnPdPiS0_S0_S0_
.p2align 8
.type _Z24ForwardEliminationColumnPdPiS0_S0_S0_,@function
_Z24ForwardEliminationColumnPdPiS0_S0_S0_: ; @_Z24ForwardEliminationColumnPdPiS0_S0_S0_
; %bb.0:
s_load_b256 s[4:11], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_load_b32 s2, s[10:11], 0x0
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s2, 1
s_cbranch_scc1 .LBB0_5
; %bb.1: ; %.lr.ph
s_load_b64 s[10:11], s[0:1], 0x20
s_load_b32 s3, s[6:7], 0x0
s_load_b32 s1, s[0:1], 0x34
s_waitcnt lgkmcnt(0)
s_load_b32 s10, s[10:11], 0x0
s_load_b32 s8, s[8:9], 0x0
s_add_i32 s9, s3, 1
s_and_b32 s11, s1, 0xffff
s_waitcnt lgkmcnt(0)
s_mul_i32 s0, s10, s9
s_mul_i32 s1, s8, s9
s_add_i32 s6, s0, s10
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_ashr_i32 s7, s6, 31
s_lshl_b64 s[6:7], s[6:7], 3
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
s_add_u32 s6, s4, s6
s_addc_u32 s7, s5, s7
s_add_i32 s8, s10, s1
s_ashr_i32 s9, s8, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_lshl_b64 s[8:9], s[8:9], 3
s_add_u32 s8, s4, s8
s_addc_u32 s9, s5, s9
s_clause 0x1
s_load_b64 s[6:7], s[6:7], 0x0
s_load_b64 s[8:9], s[8:9], 0x0
s_waitcnt lgkmcnt(0)
v_div_scale_f64 v[1:2], null, s[6:7], s[6:7], s[8:9]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f64_e32 v[3:4], v[1:2]
s_waitcnt_depctr 0xfff
v_fma_f64 v[5:6], -v[1:2], v[3:4], 1.0
v_fma_f64 v[3:4], v[3:4], v[5:6], v[3:4]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[5:6], -v[1:2], v[3:4], 1.0
v_fma_f64 v[3:4], v[3:4], v[5:6], v[3:4]
v_div_scale_f64 v[5:6], vcc_lo, s[8:9], s[6:7], s[8:9]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f64 v[7:8], v[5:6], v[3:4]
v_fma_f64 v[1:2], -v[1:2], v[7:8], v[5:6]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fmas_f64 v[1:2], v[1:2], v[3:4], v[7:8]
v_div_fixup_f64 v[1:2], v[1:2], s[6:7], s[8:9]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[3:4], null, s15, s11, v[0:1]
v_mul_lo_u32 v0, v3, s2
.LBB0_2: ; =>This Inner Loop Header: Depth=1
s_mov_b32 s6, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_ge_i32_e64 s3, v0
s_cbranch_execz .LBB0_4
; %bb.3: ; in Loop: Header=BB0_2 Depth=1
v_add_nc_u32_e32 v3, s0, v0
v_add_nc_u32_e32 v5, s1, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v4, 31, v3
v_ashrrev_i32_e32 v6, 31, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[3:4], 3, v[3:4]
v_lshlrev_b64 v[5:6], 3, v[5:6]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v3, vcc_lo, s4, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v5, vcc_lo, s4, v5
v_add_co_ci_u32_e32 v6, vcc_lo, s5, v6, vcc_lo
s_clause 0x1
global_load_b64 v[3:4], v[3:4], off
global_load_b64 v[7:8], v[5:6], off
s_waitcnt vmcnt(0)
v_fma_f64 v[3:4], -v[1:2], v[3:4], v[7:8]
global_store_b64 v[5:6], v[3:4], off
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
.LBB0_4: ; in Loop: Header=BB0_2 Depth=1
s_or_b32 exec_lo, exec_lo, s6
v_add_nc_u32_e32 v0, 1, v0
s_add_i32 s2, s2, -1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s2, 0
s_cbranch_scc0 .LBB0_2
.LBB0_5: ; %._crit_edge
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z24ForwardEliminationColumnPdPiS0_S0_S0_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z24ForwardEliminationColumnPdPiS0_S0_S0_, .Lfunc_end0-_Z24ForwardEliminationColumnPdPiS0_S0_S0_
; -- End function
.section .AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 476
; NumSgprs: 18
; NumVgprs: 9
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 9
; Occupancy: 16
; WaveLimiterHint : 1
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object ; @__hip_cuid_
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0 ; 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z24ForwardEliminationColumnPdPiS0_S0_S0_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z24ForwardEliminationColumnPdPiS0_S0_S0_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
```
| 4,894 | 3,974 |
21 |
Convert the following CUDA host assembly code to AMD host assembly:
```cudaasm
.file "tmpxft_00046ab2_00000000-6_ForwardEliminationColumn.cudafe1.cpp"
.text
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z55__device_stub__Z24ForwardEliminationColumnPdPiS0_S0_S0_PdPiS0_S0_S0_
.type _Z55__device_stub__Z24ForwardEliminationColumnPdPiS0_S0_S0_PdPiS0_S0_S0_, @function
_Z55__device_stub__Z24ForwardEliminationColumnPdPiS0_S0_S0_PdPiS0_S0_S0_:
.LFB2051:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movq %r8, 8(%rsp)
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 184
pushq 56(%rsp)
.cfi_def_cfa_offset 192
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z24ForwardEliminationColumnPdPiS0_S0_S0_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z55__device_stub__Z24ForwardEliminationColumnPdPiS0_S0_S0_PdPiS0_S0_S0_, .-_Z55__device_stub__Z24ForwardEliminationColumnPdPiS0_S0_S0_PdPiS0_S0_S0_
.globl _Z24ForwardEliminationColumnPdPiS0_S0_S0_
.type _Z24ForwardEliminationColumnPdPiS0_S0_S0_, @function
_Z24ForwardEliminationColumnPdPiS0_S0_S0_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z55__device_stub__Z24ForwardEliminationColumnPdPiS0_S0_S0_PdPiS0_S0_S0_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z24ForwardEliminationColumnPdPiS0_S0_S0_, .-_Z24ForwardEliminationColumnPdPiS0_S0_S0_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z24ForwardEliminationColumnPdPiS0_S0_S0_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z24ForwardEliminationColumnPdPiS0_S0_S0_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
```
|
```amdasm
.text
.file "ForwardEliminationColumn.hip"
.globl _Z39__device_stub__ForwardEliminationColumnPdPiS0_S0_S0_ # -- Begin function _Z39__device_stub__ForwardEliminationColumnPdPiS0_S0_S0_
.type _Z39__device_stub__ForwardEliminationColumnPdPiS0_S0_S0_,@function
_Z39__device_stub__ForwardEliminationColumnPdPiS0_S0_S0_: # @_Z39__device_stub__ForwardEliminationColumnPdPiS0_S0_S0_
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $144, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 56(%rsp), %rax
movq %rdi, (%rax)
leaq 48(%rsp), %rdi
movq %rsi, (%rdi)
leaq 40(%rsp), %rsi
movq %rdx, (%rsi)
leaq 32(%rsp), %rdx
movq %rcx, (%rdx)
leaq 24(%rsp), %rcx
movq %r8, (%rcx)
leaq 96(%rsp), %rbx
movq %rax, (%rbx)
movq %rdi, 8(%rbx)
movq %rsi, 16(%rbx)
movq %rdx, 24(%rbx)
movq %rcx, 32(%rbx)
leaq 80(%rsp), %r14
leaq 64(%rsp), %r15
leaq 16(%rsp), %r12
leaq 8(%rsp), %r13
movq %r14, %rdi
movq %r15, %rsi
movq %r12, %rdx
movq %r13, %rcx
callq __hipPopCallConfiguration
movq (%r14), %rsi
movl 8(%r14), %edx
movq (%r15), %rcx
movl 8(%r15), %r8d
movl $_Z24ForwardEliminationColumnPdPiS0_S0_S0_, %edi
movq %rbx, %r9
pushq (%r13)
.cfi_adjust_cfa_offset 8
pushq (%r12)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $160, %rsp
.cfi_adjust_cfa_offset -160
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z39__device_stub__ForwardEliminationColumnPdPiS0_S0_S0_, .Lfunc_end0-_Z39__device_stub__ForwardEliminationColumnPdPiS0_S0_S0_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, %rdi
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z24ForwardEliminationColumnPdPiS0_S0_S0_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z24ForwardEliminationColumnPdPiS0_S0_S0_,@object # @_Z24ForwardEliminationColumnPdPiS0_S0_S0_
.section .rodata,"a",@progbits
.globl _Z24ForwardEliminationColumnPdPiS0_S0_S0_
.p2align 3, 0x0
_Z24ForwardEliminationColumnPdPiS0_S0_S0_:
.quad _Z39__device_stub__ForwardEliminationColumnPdPiS0_S0_S0_
.size _Z24ForwardEliminationColumnPdPiS0_S0_S0_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z24ForwardEliminationColumnPdPiS0_S0_S0_"
.size .L__unnamed_1, 42
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z39__device_stub__ForwardEliminationColumnPdPiS0_S0_S0_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z24ForwardEliminationColumnPdPiS0_S0_S0_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
```
| 2,067 | 2,236 |
22 |
Convert the following CUDA device assembly code to AMD device assembly:
```cudaasm
code for sm_80
Function : _Z26convolution_forward_kernelPfS_S_S_iiiiiif
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ;
ULDC UR6, c[0x0][0x180] ;
S2R R10, SR_CTAID.X ;
USHF.R.S32.HI UR4, URZ, 0x1f, UR6 ;
ULDC.64 UR10, c[0x0][0x118] ;
S2R R4, SR_CTAID.Y ;
ULEA.HI UR4, UR4, UR6, URZ, 0x5 ;
S2R R8, SR_TID.Y ;
USHF.R.S32.HI UR4, URZ, 0x5, UR4 ;
IMAD R5, RZ, RZ, -UR4 ;
I2F.U32.RP R0, UR4 ;
MUFU.RCP R0, R0 ;
IADD3 R2, R0, 0xffffffe, RZ ;
F2I.FTZ.U32.TRUNC.NTZ R3, R2 ;
IMAD.MOV.U32 R2, RZ, RZ, RZ ;
IMAD R5, R5, R3, RZ ;
IMAD.HI.U32 R3, R3, R5, R2 ;
IMAD.HI.U32 R5, R3, R10, RZ ;
IMAD.HI.U32 R3, R3, R4, RZ ;
IMAD.MOV R9, RZ, RZ, -R5 ;
IMAD.MOV R7, RZ, RZ, -R3 ;
IMAD R2, R9, UR4, R10 ;
IMAD R0, R7, UR4, R4 ;
S2R R7, SR_TID.X ;
ISETP.GE.U32.AND P2, PT, R2, UR4, PT ;
ISETP.GE.U32.AND P0, PT, R0, UR4, PT ;
@P2 IADD3 R2, R2, -UR4, RZ ;
@P0 IADD3 R0, R0, -UR4, RZ ;
ISETP.GE.U32.AND P3, PT, R2, UR4, PT ;
ISETP.GE.U32.AND P1, PT, R0, UR4, PT ;
@P2 IADD3 R5, R5, 0x1, RZ ;
@P0 IADD3 R3, R3, 0x1, RZ ;
ISETP.NE.U32.AND P0, PT, RZ, UR4, PT ;
LOP3.LUT R0, RZ, UR4, RZ, 0x33, !PT ;
@P3 IADD3 R5, R5, 0x1, RZ ;
@P1 IADD3 R3, R3, 0x1, RZ ;
SEL R6, R0.reuse, R5, !P0 ;
SEL R9, R0, R3, !P0 ;
IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x184] ;
IMAD.MOV R3, RZ, RZ, -R6 ;
IMAD.MOV R11, RZ, RZ, -R9 ;
ISETP.GE.AND P0, PT, R0, 0x1, PT ;
IMAD R10, R3, UR4, R10 ;
IMAD R11, R11, UR4, R4 ;
IMAD.MOV.U32 R0, RZ, RZ, RZ ;
IMAD R10, R10, 0x20, R7 ;
IMAD R11, R11, 0x20, R8 ;
@!P0 BRA 0x11c0 ;
ULDC UR5, c[0x0][0x194] ;
IADD3 R0, R11.reuse, 0x20, RZ ;
UIADD3 UR5, UR6, UR5, URZ ;
IADD3 R2, R10, 0x20, RZ ;
ULDC.64 UR8, c[0x0][0x180] ;
IMAD.MOV.U32 R14, RZ, RZ, c[0x0][0x18c] ;
UIMAD UR4, UR6, UR8, URZ ;
ISETP.GE.AND P0, PT, R11, c[0x0][0x194], PT ;
IMAD.SHL.U32 R17, R7, 0x4, RZ ;
ISETP.GE.AND P5, PT, R0, UR5, PT ;
IMAD.MOV.U32 R15, RZ, RZ, RZ ;
IADD3 R12, R11, -c[0x0][0x194], RZ ;
IADD3 R13, R10, -c[0x0][0x194], RZ ;
ISETP.GE.AND P4, PT, R2.reuse, UR5, PT ;
ISETP.GE.OR P2, PT, R2, UR5, P5 ;
UIMAD UR5, UR4, UR9, URZ ;
IADD3 R0, R0, -c[0x0][0x194], RZ ;
IMAD R12, R12, c[0x0][0x180], R13.reuse ;
LEA R16, R8, 0x17c4, 0x5 ;
IADD3 R3, R14, -0x1, RZ ;
IMAD R13, R0, c[0x0][0x180], R13 ;
ISETP.GE.U32.AND P3, PT, R8, c[0x0][0x18c], PT ;
IMAD.IADD R16, R16, 0x1, R17.reuse ;
ISETP.LT.OR P0, PT, R10, c[0x0][0x194], !P0 ;
IMAD.MOV.U32 R0, RZ, RZ, RZ ;
LOP3.LUT R14, R14, 0x3, RZ, 0xc0, !PT ;
IMAD R17, R8, 0x9c, R17 ;
ISETP.GE.U32.AND P1, PT, R3, 0x3, PT ;
IMAD R19, R9, UR5, RZ ;
ISETP.LT.U32.AND P3, PT, R7, c[0x0][0x18c], !P3 ;
ISETP.LT.OR P4, PT, R11, c[0x0][0x194], P4 ;
ISETP.LT.OR P5, PT, R10, c[0x0][0x194], P5 ;
P2R R21, PR, RZ, 0x1 ;
IADD3 R18, -R14, c[0x0][0x18c], RZ ;
@P3 IMAD R3, R6, c[0x0][0x184], R15 ;
ISETP.NE.AND P6, PT, R21, RZ, PT ;
@P3 IMAD.MOV.U32 R5, RZ, RZ, 0x4 ;
@P3 IMAD R2, R3, c[0x0][0x18c], R8 ;
@P3 IMAD R2, R2, c[0x0][0x18c], R7 ;
@P3 IMAD.WIDE.U32 R4, R2, R5, c[0x0][0x168] ;
@P3 LDG.E R5, [R4.64] ;
IMAD R2, R15, UR4, RZ ;
BSSY B0, 0x680 ;
SHF.R.S32.HI R20, RZ, 0x1f, R2 ;
IADD3 R22, P0, R19, R2, RZ ;
LEA.HI.X.SX32 R23, R19, R20, 0x1, P0 ;
IADD3 R3, P0, R12, R22, RZ ;
LEA.HI.X.SX32 R20, R12, R23, 0x1, P0 ;
LEA R2, P0, R3, c[0x0][0x160], 0x2 ;
LEA.HI.X R3, R3, c[0x0][0x164], R20, 0x2, P0 ;
IMAD.MOV.U32 R20, RZ, RZ, RZ ;
@P3 STS [R16], R5 ;
BAR.SYNC.DEFER_BLOCKING 0x0 ;
@P6 BRA 0x670 ;
LDG.E R20, [R2.64] ;
BSYNC B0 ;
STS [R17], R20 ;
ISETP.GT.U32.AND P0, PT, R7, 0x6, PT ;
BSSY B0, 0x720 ;
@P0 BRA 0x710 ;
@P4 BRA 0x700 ;
LDG.E R2, [R2.64+0x80] ;
STS [R17+0x80], R2 ;
BRA 0x710 ;
STS [R17+0x80], RZ ;
BSYNC B0 ;
ISETP.GT.U32.AND P6, PT, R8, 0x6, PT ;
BSSY B0, 0x860 ;
@P6 BRA 0x850 ;
IADD3 R3, P6, R13.reuse, R22, RZ ;
BSSY B1, 0x7e0 ;
LEA.HI.X.SX32 R4, R13, R23, 0x1, P6 ;
LEA R2, P6, R3, c[0x0][0x160], 0x2 ;
LEA.HI.X R3, R3, c[0x0][0x164], R4, 0x2, P6 ;
IMAD.MOV.U32 R4, RZ, RZ, RZ ;
@P5 BRA 0x7d0 ;
LDG.E R4, [R2.64] ;
BSYNC B1 ;
STS [R17+0x1380], R4 ;
@P0 BRA 0x850 ;
@P2 BRA 0x840 ;
LDG.E R2, [R2.64+0x80] ;
STS [R17+0x1400], R2 ;
BRA 0x850 ;
STS [R17+0x1400], RZ ;
BSYNC B0 ;
IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x18c] ;
BAR.SYNC.DEFER_BLOCKING 0x0 ;
ISETP.GE.AND P0, PT, R2, 0x1, PT ;
@!P0 BRA 0x1170 ;
IMAD.MOV.U32 R26, RZ, RZ, RZ ;
IMAD.MOV.U32 R3, RZ, RZ, R17 ;
IMAD.MOV.U32 R4, RZ, RZ, RZ ;
@!P1 BRA 0x1020 ;
ISETP.GT.AND P0, PT, R18, RZ, PT ;
IMAD.MOV.U32 R4, RZ, RZ, RZ ;
LEA R20, R26, 0x17c4, 0x5 ;
IMAD.MOV.U32 R5, RZ, RZ, R3 ;
IMAD.MOV.U32 R2, RZ, RZ, R18 ;
IADD3 R20, R20, 0x8, RZ ;
@!P0 BRA 0xf00 ;
ISETP.GT.AND P6, PT, R2, 0xc, PT ;
PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ;
@!P6 BRA 0xcf0 ;
PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ;
LDS R23, [R20+-0x8] ;
IADD3 R2, R2, -0x10, RZ ;
IADD3 R4, R4, 0x10, RZ ;
LDS R22, [R5] ;
ISETP.GT.AND P6, PT, R2, 0xc, PT ;
LDS R25, [R20+-0x4] ;
LDS R24, [R5+0x4] ;
FFMA R22, R23, R22, R0 ;
LDS R23, [R20] ;
LDS R0, [R5+0x8] ;
FFMA R22, R25, R24, R22 ;
LDS R25, [R20+0x4] ;
LDS R24, [R5+0xc] ;
FFMA R0, R23, R0, R22 ;
LDS R23, [R20+0x8] ;
LDS R22, [R5+0x10] ;
FFMA R0, R25, R24, R0 ;
LDS R25, [R20+0xc] ;
LDS R24, [R5+0x14] ;
FFMA R0, R23, R22, R0 ;
LDS R23, [R20+0x10] ;
LDS R22, [R5+0x18] ;
FFMA R0, R25, R24, R0 ;
LDS R25, [R20+0x14] ;
LDS R24, [R5+0x1c] ;
FFMA R0, R23, R22, R0 ;
LDS R23, [R20+0x18] ;
LDS R22, [R5+0x20] ;
FFMA R0, R25, R24, R0 ;
LDS R25, [R20+0x1c] ;
LDS R24, [R5+0x24] ;
FFMA R0, R23, R22, R0 ;
LDS R23, [R20+0x20] ;
LDS R22, [R5+0x28] ;
FFMA R0, R25, R24, R0 ;
LDS R25, [R20+0x24] ;
LDS R24, [R5+0x2c] ;
FFMA R0, R23, R22, R0 ;
LDS R23, [R20+0x28] ;
LDS R22, [R5+0x30] ;
FFMA R0, R25, R24, R0 ;
LDS R25, [R20+0x2c] ;
LDS R24, [R5+0x34] ;
FFMA R0, R23, R22, R0 ;
LDS R23, [R20+0x30] ;
LDS R22, [R5+0x38] ;
FFMA R0, R25, R24, R0 ;
LDS R25, [R20+0x34] ;
LDS R24, [R5+0x3c] ;
IADD3 R20, R20, 0x40, RZ ;
IADD3 R5, R5, 0x40, RZ ;
FFMA R0, R23, R22, R0 ;
FFMA R0, R25, R24, R0 ;
@P6 BRA 0x990 ;
ISETP.GT.AND P6, PT, R2, 0x4, PT ;
@!P6 BRA 0xee0 ;
LDS R23, [R20+-0x8] ;
PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ;
IADD3 R4, R4, 0x8, RZ ;
LDS R22, [R5] ;
IADD3 R2, R2, -0x8, RZ ;
LDS R25, [R20+-0x4] ;
LDS R24, [R5+0x4] ;
FFMA R22, R23, R22, R0 ;
LDS R23, [R20] ;
LDS R0, [R5+0x8] ;
FFMA R22, R25, R24, R22 ;
LDS R25, [R20+0x4] ;
LDS R24, [R5+0xc] ;
FFMA R0, R23, R0, R22 ;
LDS R23, [R20+0x8] ;
LDS R22, [R5+0x10] ;
FFMA R0, R25, R24, R0 ;
LDS R25, [R20+0xc] ;
LDS R24, [R5+0x14] ;
FFMA R0, R23, R22, R0 ;
LDS R23, [R20+0x10] ;
LDS R22, [R5+0x18] ;
FFMA R0, R25, R24, R0 ;
LDS R25, [R20+0x14] ;
LDS R24, [R5+0x1c] ;
IADD3 R20, R20, 0x20, RZ ;
IADD3 R5, R5, 0x20, RZ ;
FFMA R0, R23, R22, R0 ;
FFMA R0, R25, R24, R0 ;
ISETP.NE.OR P0, PT, R2, RZ, P0 ;
@!P0 BRA 0x1020 ;
LDS R23, [R20+-0x8] ;
IADD3 R2, R2, -0x4, RZ ;
IADD3 R4, R4, 0x4, RZ ;
LDS R22, [R5] ;
ISETP.NE.AND P0, PT, R2, RZ, PT ;
LDS R25, [R20+-0x4] ;
LDS R24, [R5+0x4] ;
FFMA R22, R23, R22, R0 ;
LDS R23, [R20] ;
LDS R0, [R5+0x8] ;
FFMA R22, R25, R24, R22 ;
LDS R25, [R20+0x4] ;
LDS R24, [R5+0xc] ;
IADD3 R20, R20, 0x10, RZ ;
IADD3 R5, R5, 0x10, RZ ;
FFMA R0, R23, R0, R22 ;
FFMA R0, R25, R24, R0 ;
@P0 BRA 0xf00 ;
ISETP.NE.AND P0, PT, R14, RZ, PT ;
@!P0 BRA 0x1130 ;
LEA R5, R26, 0x17c4, 0x5 ;
IMAD R22, R4, 0x4, R3 ;
ISETP.NE.AND P0, PT, R14, 0x1, PT ;
IMAD R20, R4, 0x4, R5 ;
LDS R2, [R22] ;
LDS R5, [R20] ;
FFMA R0, R5, R2, R0 ;
@!P0 BRA 0x1130 ;
ISETP.NE.AND P0, PT, R14, 0x2, PT ;
LDS R5, [R20+0x4] ;
LDS R2, [R22+0x4] ;
@P0 LDS R23, [R20+0x8] ;
@P0 LDS R4, [R22+0x8] ;
FFMA R0, R5, R2, R0 ;
@P0 FFMA R0, R23, R4, R0 ;
IADD3 R26, R26, 0x1, RZ ;
IADD3 R3, R3, 0x9c, RZ ;
ISETP.GE.AND P0, PT, R26, c[0x0][0x18c], PT ;
@!P0 BRA 0x8c0 ;
IADD3 R15, R15, 0x1, RZ ;
BAR.SYNC.DEFER_BLOCKING 0x0 ;
ISETP.GE.AND P0, PT, R15, c[0x0][0x184], PT ;
@P0 CALL.REL.NOINC 0x11c0 ;
BRA 0x520 ;
IMAD.MOV.U32 R3, RZ, RZ, 0x4 ;
IMAD.WIDE R2, R6, R3, c[0x0][0x178] ;
LDG.E R3, [R2.64] ;
IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x198] ;
ULDC UR5, c[0x0][0x188] ;
IMAD.MOV.U32 R8, RZ, RZ, 0x4b800000 ;
UIMAD UR5, UR5, UR5, URZ ;
FMUL R4, R4, c[0x0][0x198] ;
ULDC UR6, c[0x0][0x190] ;
IMAD R11, R11, c[0x0][0x188], RZ ;
UIMAD UR6, UR5, UR6, URZ ;
FSETP.GEU.AND P0, PT, R4, 1.175494350822287508e-38, PT ;
IMAD R5, R6, UR5, RZ ;
SHF.R.S32.HI R2, RZ, 0x1f, R10 ;
IMAD R9, R9, UR6, RZ ;
SHF.R.S32.HI R7, RZ, 0x1f, R5 ;
IADD3 R6, P1, P2, R10, R9, R5 ;
SHF.R.S32.HI R9, RZ, 0x1f, R9 ;
@!P0 FMUL R4, R4, 16777216 ;
FSEL R5, R8, 1, !P0 ;
IADD3.X R2, R2, R9, R7, P1, P2 ;
IADD3 R6, P0, R11.reuse, R6, RZ ;
MUFU.RCP R4, R4 ;
LEA.HI.X.SX32 R11, R11, R2, 0x1, P0 ;
LEA R2, P0, R6, c[0x0][0x170], 0x2 ;
FMUL R5, R4, R5 ;
FADD R0, R3, R0 ;
LEA.HI.X R3, R6, c[0x0][0x174], R11, 0x2, P0 ;
FMUL R5, R0, R5 ;
STG.E [R2.64], R5 ;
EXIT ;
BRA 0x13b0;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
```
|
```amdasm
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z26convolution_forward_kernelPfS_S_S_iiiiiif ; -- Begin function _Z26convolution_forward_kernelPfS_S_S_iiiiiif
.globl _Z26convolution_forward_kernelPfS_S_S_iiiiiif
.p2align 8
.type _Z26convolution_forward_kernelPfS_S_S_iiiiiif,@function
_Z26convolution_forward_kernelPfS_S_S_iiiiiif: ; @_Z26convolution_forward_kernelPfS_S_S_iiiiiif
; %bb.0:
s_load_b256 s[16:23], s[0:1], 0x20
v_bfe_u32 v2, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_ashr_i32 s2, s16, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_lshr_b32 s2, s2, 27
s_add_i32 s2, s16, s2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_ashr_i32 s2, s2, 5
v_cvt_f32_u32_e32 v1, s2
s_sub_i32 s4, 0, s2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v1, v1
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v1, 0x4f7ffffe, v1
v_cvt_u32_f32_e32 v1, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_readfirstlane_b32 s3, v1
v_and_b32_e32 v1, 0x3ff, v0
s_mul_i32 s4, s4, s3
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_hi_u32 s4, s3, s4
s_add_i32 s3, s3, s4
s_load_b256 s[4:11], s[0:1], 0x0
s_mul_hi_u32 s12, s15, s3
s_mul_hi_u32 s3, s14, s3
s_mul_i32 s13, s12, s2
s_add_i32 s1, s12, 1
s_sub_i32 s0, s15, s13
s_delay_alu instid0(SALU_CYCLE_1)
s_sub_i32 s13, s0, s2
s_cmp_ge_u32 s0, s2
s_cselect_b32 s1, s1, s12
s_cselect_b32 s0, s13, s0
s_add_i32 s12, s1, 1
s_cmp_ge_u32 s0, s2
s_mul_i32 s0, s3, s2
s_cselect_b32 s13, s12, s1
s_sub_i32 s0, s14, s0
s_add_i32 s1, s3, 1
s_sub_i32 s12, s0, s2
s_cmp_ge_u32 s0, s2
s_cselect_b32 s1, s1, s3
s_cselect_b32 s0, s12, s0
s_add_i32 s3, s1, 1
s_cmp_ge_u32 s0, s2
s_cselect_b32 s12, s3, s1
s_mul_i32 s1, s13, s2
s_mul_i32 s0, s12, s2
s_sub_i32 s1, s15, s1
s_sub_i32 s0, s14, s0
v_lshl_add_u32 v11, s1, 5, v2
v_lshl_add_u32 v0, s0, 5, v1
s_cmp_lt_i32 s17, 1
s_mov_b32 s14, 0
s_cbranch_scc1 .LBB0_23
; %bb.1: ; %.lr.ph146
v_subrev_nc_u32_e32 v4, s21, v11
v_add_nc_u32_e32 v9, 32, v11
s_mul_i32 s15, s16, s16
v_max_u32_e32 v3, v1, v2
s_mul_i32 s0, s15, s17
v_mul_lo_u32 v5, v4, s16
v_subrev_nc_u32_e32 v4, s21, v9
v_lshlrev_b32_e32 v8, 2, v1
v_add_nc_u32_e32 v7, 32, v0
s_mul_i32 s2, s0, s13
v_cmp_gt_u32_e64 s0, s19, v3
v_mul_lo_u32 v17, v4, s16
s_ashr_i32 s3, s2, 31
v_lshlrev_b32_e32 v3, 5, v2
s_lshl_b64 s[24:25], s[2:3], 2
v_subrev_nc_u32_e32 v6, s21, v0
v_or_b32_e32 v10, 0x80, v8
v_subrev_nc_u32_e32 v12, s21, v7
v_or_b32_e32 v18, 32, v2
s_waitcnt lgkmcnt(0)
s_add_u32 s24, s4, s24
s_addc_u32 s25, s5, s25
s_add_i32 s5, s21, s16
v_cmp_gt_i32_e32 vcc_lo, s21, v0
v_cmp_le_i32_e64 s4, s5, v7
v_add_nc_u32_e32 v7, v6, v17
v_mad_u32_u24 v16, 0x9c, v18, v8
v_cmp_le_i32_e64 s5, s5, v9
v_add_nc_u32_e32 v9, v12, v17
v_mad_u32_u24 v17, 0x9c, v18, v10
v_mov_b32_e32 v18, 0
v_add3_u32 v13, v3, v8, 0x17d0
v_add_nc_u32_e32 v3, v6, v5
v_add_nc_u32_e32 v5, v12, v5
v_cmp_gt_i32_e64 s3, s21, v11
v_mad_u32_u24 v14, 0x9c, v2, v8
v_mad_u32_u24 v15, 0x9c, v2, v10
v_ashrrev_i32_e32 v4, 31, v3
v_ashrrev_i32_e32 v6, 31, v5
v_ashrrev_i32_e32 v8, 31, v7
v_ashrrev_i32_e32 v10, 31, v9
s_or_b32 s1, vcc_lo, s3
v_lshlrev_b64 v[3:4], 2, v[3:4]
s_xor_b32 s26, s1, -1
s_cmp_gt_i32 s19, 0
v_lshlrev_b64 v[5:6], 2, v[5:6]
v_lshlrev_b64 v[7:8], 2, v[7:8]
v_lshlrev_b64 v[9:10], 2, v[9:10]
v_cmp_gt_u32_e64 s1, 7, v1
v_cmp_gt_u32_e64 s2, 7, v2
v_mov_b32_e32 v12, 0
s_cselect_b32 s16, -1, 0
s_or_b32 s3, s3, s4
s_or_b32 s21, vcc_lo, s5
s_or_b32 s5, s5, s4
s_mul_i32 s23, s12, s17
s_xor_b32 s3, s3, -1
s_xor_b32 s4, s21, -1
s_xor_b32 s5, s5, -1
.LBB0_2: ; =>This Loop Header: Depth=1
; Child Loop BB0_19 Depth 2
; Child Loop BB0_20 Depth 3
s_and_saveexec_b32 s21, s0
s_cbranch_execz .LBB0_4
; %bb.3: ; in Loop: Header=BB0_2 Depth=1
s_add_i32 s27, s14, s23
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[19:20], null, s27, s19, v[2:3]
v_mad_u64_u32 v[20:21], null, v19, s19, v[1:2]
v_mov_b32_e32 v21, v18
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[19:20], 2, v[20:21]
v_add_co_u32 v19, vcc_lo, s6, v19
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v20, vcc_lo, s7, v20, vcc_lo
global_load_b32 v19, v[19:20], off
s_waitcnt vmcnt(0)
ds_store_b32 v13, v19
.LBB0_4: ; in Loop: Header=BB0_2 Depth=1
s_or_b32 exec_lo, exec_lo, s21
s_mul_i32 s28, s15, s14
v_mov_b32_e32 v19, 0
s_ashr_i32 s29, s28, 31
s_waitcnt lgkmcnt(0)
s_lshl_b64 s[28:29], s[28:29], 2
s_barrier
s_add_u32 s21, s24, s28
s_addc_u32 s27, s25, s29
buffer_gl0_inv
s_and_saveexec_b32 s28, s26
s_cbranch_execz .LBB0_6
; %bb.5: ; in Loop: Header=BB0_2 Depth=1
v_add_co_u32 v19, vcc_lo, s21, v3
v_add_co_ci_u32_e32 v20, vcc_lo, s27, v4, vcc_lo
global_load_b32 v19, v[19:20], off
.LBB0_6: ; in Loop: Header=BB0_2 Depth=1
s_or_b32 exec_lo, exec_lo, s28
s_waitcnt vmcnt(0)
ds_store_b32 v14, v19
s_and_saveexec_b32 s28, s1
s_cbranch_execz .LBB0_10
; %bb.7: ; in Loop: Header=BB0_2 Depth=1
v_mov_b32_e32 v19, 0
s_and_saveexec_b32 s29, s3
s_cbranch_execz .LBB0_9
; %bb.8: ; in Loop: Header=BB0_2 Depth=1
v_add_co_u32 v19, vcc_lo, s21, v5
v_add_co_ci_u32_e32 v20, vcc_lo, s27, v6, vcc_lo
global_load_b32 v19, v[19:20], off
.LBB0_9: ; %.sink.split
; in Loop: Header=BB0_2 Depth=1
s_or_b32 exec_lo, exec_lo, s29
s_waitcnt vmcnt(0)
ds_store_b32 v15, v19
.LBB0_10: ; %Flow196
; in Loop: Header=BB0_2 Depth=1
s_or_b32 exec_lo, exec_lo, s28
s_and_saveexec_b32 s28, s2
s_cbranch_execz .LBB0_17
; %bb.11: ; in Loop: Header=BB0_2 Depth=1
v_mov_b32_e32 v19, 0
s_and_saveexec_b32 s29, s4
s_cbranch_execz .LBB0_13
; %bb.12: ; in Loop: Header=BB0_2 Depth=1
v_add_co_u32 v19, vcc_lo, s21, v7
v_add_co_ci_u32_e32 v20, vcc_lo, s27, v8, vcc_lo
global_load_b32 v19, v[19:20], off
.LBB0_13: ; in Loop: Header=BB0_2 Depth=1
s_or_b32 exec_lo, exec_lo, s29
s_waitcnt vmcnt(0)
ds_store_b32 v16, v19
s_and_b32 exec_lo, exec_lo, s1
s_cbranch_execz .LBB0_17
; %bb.14: ; in Loop: Header=BB0_2 Depth=1
v_mov_b32_e32 v19, 0
s_and_saveexec_b32 s29, s5
s_cbranch_execz .LBB0_16
; %bb.15: ; in Loop: Header=BB0_2 Depth=1
v_add_co_u32 v19, vcc_lo, s21, v9
v_add_co_ci_u32_e32 v20, vcc_lo, s27, v10, vcc_lo
global_load_b32 v19, v[19:20], off
.LBB0_16: ; %.sink.split153
; in Loop: Header=BB0_2 Depth=1
s_or_b32 exec_lo, exec_lo, s29
s_waitcnt vmcnt(0)
ds_store_b32 v17, v19
.LBB0_17: ; %Flow195
; in Loop: Header=BB0_2 Depth=1
s_or_b32 exec_lo, exec_lo, s28
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 vcc_lo, exec_lo, s16
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_vccnz .LBB0_22
; %bb.18: ; %.preheader.preheader
; in Loop: Header=BB0_2 Depth=1
v_mov_b32_e32 v19, v14
s_mov_b32 s21, 0
s_movk_i32 s27, 0x17d0
.LBB0_19: ; %.preheader
; Parent Loop BB0_2 Depth=1
; => This Loop Header: Depth=2
; Child Loop BB0_20 Depth 3
s_mov_b32 s28, 0
s_mov_b32 s29, s19
.LBB0_20: ; Parent Loop BB0_2 Depth=1
; Parent Loop BB0_19 Depth=2
; => This Inner Loop Header: Depth=3
s_add_i32 s30, s27, s28
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v21, s30 :: v_dual_add_nc_u32 v20, s28, v19
s_add_i32 s29, s29, -1
s_add_i32 s28, s28, 4
s_cmp_eq_u32 s29, 0
ds_load_b32 v20, v20
ds_load_b32 v21, v21
s_waitcnt lgkmcnt(0)
v_fmac_f32_e32 v12, v20, v21
s_cbranch_scc0 .LBB0_20
; %bb.21: ; %._crit_edge
; in Loop: Header=BB0_19 Depth=2
v_add_nc_u32_e32 v19, 0x9c, v19
s_add_i32 s21, s21, 1
s_add_i32 s27, s27, 32
s_cmp_eq_u32 s21, s19
s_cbranch_scc0 .LBB0_19
.LBB0_22: ; %._crit_edge141
; in Loop: Header=BB0_2 Depth=1
s_add_i32 s14, s14, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s14, s17
s_barrier
buffer_gl0_inv
s_cbranch_scc0 .LBB0_2
s_branch .LBB0_24
.LBB0_23:
v_mov_b32_e32 v12, 0
.LBB0_24: ; %Flow198
v_mul_f32_e64 v4, s22, s22
s_mul_i32 s2, s18, s18
v_mul_lo_u32 v2, v11, s18
s_mul_i32 s0, s2, s20
s_mul_i32 s2, s2, s12
v_div_scale_f32 v5, null, v4, v4, 1.0
s_mul_i32 s0, s0, s13
v_div_scale_f32 v7, vcc_lo, 1.0, v4, 1.0
s_delay_alu instid0(VALU_DEP_2)
v_rcp_f32_e32 v6, v5
s_ashr_i32 s1, s0, 31
v_ashrrev_i32_e32 v3, 31, v2
s_lshl_b64 s[0:1], s[0:1], 2
s_waitcnt lgkmcnt(0)
s_add_u32 s4, s8, s0
s_addc_u32 s5, s9, s1
s_ashr_i32 s3, s2, 31
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_lshl_b64 s[0:1], s[2:3], 2
s_waitcnt_depctr 0xfff
v_fma_f32 v1, -v5, v6, 1.0
s_add_u32 s2, s4, s0
s_addc_u32 s3, s5, s1
s_ashr_i32 s13, s12, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
s_lshl_b64 s[0:1], s[12:13], 2
v_fmac_f32_e32 v6, v1, v6
s_add_u32 s0, s10, s0
s_addc_u32 s1, s11, s1
s_load_b32 s0, s[0:1], 0x0
v_mul_f32_e32 v8, v7, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v1, -v5, v8, v7
v_fmac_f32_e32 v8, v1, v6
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v5, -v5, v8, v7
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_delay_alu instid0(VALU_DEP_2)
v_div_fmas_f32 v5, v5, v6, v8
v_add_co_u32 v2, vcc_lo, s2, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v6, s0, v12
v_div_fixup_f32 v4, v5, v4, 1.0
v_add_co_u32 v0, vcc_lo, v2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, v3, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_3)
v_mul_f32_e32 v2, v4, v6
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z26convolution_forward_kernelPfS_S_S_iiiiiif
.amdhsa_group_segment_fixed_size 6352
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 60
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 22
.amdhsa_next_free_sgpr 31
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z26convolution_forward_kernelPfS_S_S_iiiiiif, .Lfunc_end0-_Z26convolution_forward_kernelPfS_S_S_iiiiiif
; -- End function
.section .AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1364
; NumSgprs: 33
; NumVgprs: 22
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 6352 bytes/workgroup (compile time only)
; SGPRBlocks: 4
; VGPRBlocks: 2
; NumSGPRsForWavesPerEU: 33
; NumVGPRsForWavesPerEU: 22
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object ; @__hip_cuid_
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0 ; 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 36
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: by_value
- .offset: 44
.size: 4
.value_kind: by_value
- .offset: 48
.size: 4
.value_kind: by_value
- .offset: 52
.size: 4
.value_kind: by_value
- .offset: 56
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 6352
.kernarg_segment_align: 8
.kernarg_segment_size: 60
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z26convolution_forward_kernelPfS_S_S_iiiiiif
.private_segment_fixed_size: 0
.sgpr_count: 33
.sgpr_spill_count: 0
.symbol: _Z26convolution_forward_kernelPfS_S_S_iiiiiif.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 22
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
```
| 5,807 | 7,240 |
23 |
Convert the following CUDA host assembly code to AMD host assembly:
```cudaasm
.file "tmpxft_0002129f_00000000-6_convolution_forward_kernel.cudafe1.cpp"
.text
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z59__device_stub__Z26convolution_forward_kernelPfS_S_S_iiiiiifPfS_S_S_iiiiiif
.type _Z59__device_stub__Z26convolution_forward_kernelPfS_S_S_iiiiiifPfS_S_S_iiiiiif, @function
_Z59__device_stub__Z26convolution_forward_kernelPfS_S_S_iiiiiifPfS_S_S_iiiiiif:
.LFB2051:
.cfi_startproc
endbr64
subq $216, %rsp
.cfi_def_cfa_offset 224
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movl %r8d, 12(%rsp)
movl %r9d, 8(%rsp)
movss %xmm0, 4(%rsp)
movq %fs:40, %rax
movq %rax, 200(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 12(%rsp), %rax
movq %rax, 144(%rsp)
leaq 8(%rsp), %rax
movq %rax, 152(%rsp)
leaq 224(%rsp), %rax
movq %rax, 160(%rsp)
leaq 232(%rsp), %rax
movq %rax, 168(%rsp)
leaq 240(%rsp), %rax
movq %rax, 176(%rsp)
leaq 248(%rsp), %rax
movq %rax, 184(%rsp)
leaq 4(%rsp), %rax
movq %rax, 192(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 200(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $216, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 232
pushq 56(%rsp)
.cfi_def_cfa_offset 240
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z26convolution_forward_kernelPfS_S_S_iiiiiif(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 224
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z59__device_stub__Z26convolution_forward_kernelPfS_S_S_iiiiiifPfS_S_S_iiiiiif, .-_Z59__device_stub__Z26convolution_forward_kernelPfS_S_S_iiiiiifPfS_S_S_iiiiiif
.globl _Z26convolution_forward_kernelPfS_S_S_iiiiiif
.type _Z26convolution_forward_kernelPfS_S_S_iiiiiif, @function
_Z26convolution_forward_kernelPfS_S_S_iiiiiif:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 24
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 40
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 48
call _Z59__device_stub__Z26convolution_forward_kernelPfS_S_S_iiiiiifPfS_S_S_iiiiiif
addq $40, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z26convolution_forward_kernelPfS_S_S_iiiiiif, .-_Z26convolution_forward_kernelPfS_S_S_iiiiiif
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z26convolution_forward_kernelPfS_S_S_iiiiiif"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z26convolution_forward_kernelPfS_S_S_iiiiiif(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
```
|
```amdasm
.text
.file "convolution_forward_kernel.hip"
.globl _Z41__device_stub__convolution_forward_kernelPfS_S_S_iiiiiif # -- Begin function _Z41__device_stub__convolution_forward_kernelPfS_S_S_iiiiiif
.type _Z41__device_stub__convolution_forward_kernelPfS_S_S_iiiiiif,@function
_Z41__device_stub__convolution_forward_kernelPfS_S_S_iiiiiif: # @_Z41__device_stub__convolution_forward_kernelPfS_S_S_iiiiiif
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $192, %rsp
.cfi_def_cfa_offset 240
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 56(%rsp), %rax
movq %rdi, (%rax)
leaq 48(%rsp), %rdi
movq %rsi, (%rdi)
leaq 40(%rsp), %rsi
movq %rdx, (%rsi)
leaq 32(%rsp), %rdx
movq %rcx, (%rdx)
leaq 12(%rsp), %rcx
movl %r8d, (%rcx)
leaq 8(%rsp), %r8
movl %r9d, (%r8)
leaq 4(%rsp), %r9
movss %xmm0, (%r9)
leaq 96(%rsp), %rbx
movq %rax, (%rbx)
movq %rdi, 8(%rbx)
movq %rsi, 16(%rbx)
movq %rdx, 24(%rbx)
movq %rcx, 32(%rbx)
movq %r8, 40(%rbx)
leaq 240(%rsp), %rax
movq %rax, 48(%rbx)
leaq 248(%rsp), %rax
movq %rax, 56(%rbx)
leaq 256(%rsp), %rax
movq %rax, 64(%rbx)
leaq 264(%rsp), %rax
movq %rax, 72(%rbx)
movq %r9, 80(%rbx)
leaq 80(%rsp), %r14
leaq 64(%rsp), %r15
leaq 24(%rsp), %r12
leaq 16(%rsp), %r13
movq %r14, %rdi
movq %r15, %rsi
movq %r12, %rdx
movq %r13, %rcx
callq __hipPopCallConfiguration
movq (%r14), %rsi
movl 8(%r14), %edx
movq (%r15), %rcx
movl 8(%r15), %r8d
movl $_Z26convolution_forward_kernelPfS_S_S_iiiiiif, %edi
movq %rbx, %r9
pushq (%r13)
.cfi_adjust_cfa_offset 8
pushq (%r12)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $208, %rsp
.cfi_adjust_cfa_offset -208
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z41__device_stub__convolution_forward_kernelPfS_S_S_iiiiiif, .Lfunc_end0-_Z41__device_stub__convolution_forward_kernelPfS_S_S_iiiiiif
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, %rdi
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z26convolution_forward_kernelPfS_S_S_iiiiiif, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z26convolution_forward_kernelPfS_S_S_iiiiiif,@object # @_Z26convolution_forward_kernelPfS_S_S_iiiiiif
.section .rodata,"a",@progbits
.globl _Z26convolution_forward_kernelPfS_S_S_iiiiiif
.p2align 3, 0x0
_Z26convolution_forward_kernelPfS_S_S_iiiiiif:
.quad _Z41__device_stub__convolution_forward_kernelPfS_S_S_iiiiiif
.size _Z26convolution_forward_kernelPfS_S_S_iiiiiif, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z26convolution_forward_kernelPfS_S_S_iiiiiif"
.size .L__unnamed_1, 46
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z41__device_stub__convolution_forward_kernelPfS_S_S_iiiiiif
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z26convolution_forward_kernelPfS_S_S_iiiiiif
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
```
| 2,355 | 2,412 |
24 |
Convert the following CUDA device assembly code to AMD device assembly:
```cudaasm
code for sm_80
```
|
```amdasm
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object ; @__hip_cuid_
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0 ; 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
```
| 24 | 306 |
25 |
Convert the following CUDA host assembly code to AMD host assembly:
```cudaasm
.file "tmpxft_00073149_00000000-6_cudasift.cudafe1.cpp"
.text
.globl _ZSt21ios_base_library_initv
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "There is no device"
.LC1:
.string "pause"
.LC2:
.string "no cida 1.x"
.text
.globl main
.type main, @function
main:
.LFB3669:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $1064, %rsp
.cfi_def_cfa_offset 1088
movq %fs:40, %rax
movq %rax, 1048(%rsp)
xorl %eax, %eax
movl $0, 12(%rsp)
leaq 12(%rsp), %rdi
call cudaGetDeviceCount@PLT
movl 12(%rsp), %eax
testl %eax, %eax
je .L16
movl $0, %ebx
leaq 16(%rsp), %rbp
jg .L8
jmp .L9
.L16:
leaq .LC0(%rip), %rsi
leaq _ZSt4cerr(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq .LC1(%rip), %rdi
call system@PLT
jmp .L5
.L6:
addl $1, %ebx
cmpl %ebx, 12(%rsp)
jle .L9
.L8:
movl %ebx, %esi
movq %rbp, %rdi
call cudaGetDeviceProperties_v2@PLT
testl %eax, %eax
jne .L6
cmpl $0, 376(%rsp)
jle .L6
.L9:
cmpl $0, 12(%rsp)
je .L17
.L10:
movl $0, %edi
call cudaSetDevice@PLT
leaq .LC1(%rip), %rdi
call system@PLT
.L5:
movq 1048(%rsp), %rax
subq %fs:40, %rax
jne .L18
movl $0, %eax
addq $1064, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L17:
.cfi_restore_state
leaq .LC2(%rip), %rsi
leaq _ZSt4cerr(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
jmp .L10
.L18:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
```
|
```amdasm
.text
.file "cudasift.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl main # -- Begin function main
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $1480, %rsp # imm = 0x5C8
.cfi_def_cfa_offset 1504
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
leaq 4(%rsp), %rbx
movl $0, (%rbx)
movq %rbx, %rdi
callq hipGetDeviceCount
cmpl $0, (%rbx)
je .LBB0_3
# %bb.1: # %.preheader
xorl %ebx, %ebx
leaq 8(%rsp), %r14
.LBB0_2: # =>This Inner Loop Header: Depth=1
movq %r14, %rdi
movl %ebx, %esi
callq hipGetDevicePropertiesR0600
incl %ebx
jmp .LBB0_2
.LBB0_3:
movl $_ZSt4cerr, %ebx
movl $_ZSt4cerr, %edi
movl $.L.str, %esi
movl $18, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cerr(%rip), %rax
movq -24(%rax), %rdi
addq %rbx, %rdi
movl $10, %esi
callq _ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
movsbl %al, %esi
movl $_ZSt4cerr, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $.L.str.1, %edi
callq system
xorl %eax, %eax
addq $1480, %rsp # imm = 0x5C8
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "There is no device"
.size .L.str, 19
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "pause"
.size .L.str.1, 6
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _ZSt4cerr
.addrsig_sym __hip_cuid_
```
| 1,630 | 953 |
26 |
Convert the following CUDA device assembly code to AMD device assembly:
```cudaasm
code for sm_80
Function : _Z12jacobikernelPfS_S_iifffi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ;
S2R R0, SR_TID.X ;
IMAD.MOV.U32 R8, RZ, RZ, c[0x0][0x17c] ;
ULDC.64 UR6, c[0x0][0x118] ;
IMAD.MOV.U32 R6, RZ, RZ, 0x4 ;
S2R R5, SR_TID.Y ;
S2R R3, SR_CTAID.X ;
S2R R2, SR_CTAID.Y ;
ISETP.GT.AND P0, PT, R0, 0x1, PT ;
ISETP.GT.AND P2, PT, R5.reuse, 0x1, PT ;
ISETP.GT.OR P1, PT, R5, 0x1, P0 ;
IMAD R4, R3, c[0x0][0x0], R0 ;
IMAD R7, R2, c[0x0][0x4], R5 ;
IMAD R9, R7, c[0x0][0x17c], R4 ;
IMAD R11, R8, 0x10, R9 ;
IMAD.WIDE R8, R9, R6, c[0x0][0x160] ;
IMAD.WIDE R10, R11, R6, c[0x0][0x160] ;
LDG.E R12, [R8.64] ;
@!P0 LDG.E R14, [R8.64+0x40] ;
@!P2 LDG.E R16, [R10.64] ;
@!P1 LDG.E R18, [R10.64+0x40] ;
IMAD R13, R5, 0x12, R0 ;
STS [R13.X4], R12 ;
@!P0 STS [R13.X4+0x40], R14 ;
@!P2 STS [R13.X4+0x480], R16 ;
@!P1 STS [R13.X4+0x4c0], R18 ;
BAR.SYNC.DEFER_BLOCKING 0x0 ;
LDS R15, [R13.X4+0x4] ;
LDS R20, [R13.X4+0x48] ;
LDS R22, [R13.X4+0x50] ;
LDS R9, [R13.X4+0x90] ;
LDS R24, [R13.X4] ;
LDS R10, [R13.X4+0x94] ;
LDS R12, [R13.X4+0x8] ;
LDS R11, [R13.X4+0x98] ;
LDS R8, [R13.X4+0x4c] ;
FADD R15, R15, R20 ;
FADD R15, R15, R22 ;
FADD R9, R9, R24 ;
FADD R10, R15, R10 ;
FADD R12, R9, R12 ;
FMUL R9, R10, c[0x0][0x184] ;
FADD R12, R12, R11 ;
IADD3 R11, R7, 0x1, RZ ;
IMAD.MOV.U32 R10, RZ, RZ, c[0x0][0x0] ;
FFMA R9, R8, c[0x0][0x180], R9 ;
IMAD R13, R10, c[0x0][0x4], RZ ;
FFMA R7, R12, c[0x0][0x188], R9 ;
IMAD R9, R11, c[0x0][0x17c], R4 ;
ISETP.GE.AND P0, PT, R13, 0x2, PT ;
FADD R10, -R8, R7 ;
IMAD.WIDE R8, R9, R6, c[0x0][0x168] ;
IMAD R4, R5, c[0x0][0x0], R0 ;
STG.E [R8.64+0x4], R7 ;
FADD R11, |R10|, -RZ ;
IMAD.SHL.U32 R6, R4.reuse, 0x4, RZ ;
BAR.SYNC.DEFER_BLOCKING 0x0 ;
ISETP.NE.AND P1, PT, R4, RZ, PT ;
STS [R4.X4], R11 ;
BAR.SYNC.DEFER_BLOCKING 0x0 ;
@!P0 BRA 0x480 ;
SHF.R.S32.HI R11, RZ, 0x1, R13 ;
ISETP.GE.AND P0, PT, R4, R11, PT ;
@!P0 IMAD R7, R11, 0x4, R6 ;
@!P0 LDS R8, [R4.X4] ;
@!P0 LDS R7, [R7] ;
@!P0 FMNMX R9, R7, R8, !PT ;
@!P0 STS [R4.X4], R9 ;
BAR.SYNC.DEFER_BLOCKING 0x0 ;
ISETP.GT.AND P0, PT, R13, 0x3, PT ;
IMAD.MOV.U32 R13, RZ, RZ, R11 ;
@P0 BRA 0x3d0 ;
@!P1 LDS R7, [RZ] ;
ISETP.GE.AND P0, PT, R4, c[0x0][0x18c], PT ;
@!P1 IMAD.MOV.U32 R9, RZ, RZ, 0x4 ;
BSSY B0, 0x580 ;
@!P1 IMAD R2, R2, c[0x0][0xc], R3 ;
IMAD.MOV.U32 R8, RZ, RZ, c[0x0][0x18c] ;
@!P1 IMAD.WIDE.U32 R2, R2, R9, c[0x0][0x170] ;
ISETP.GE.AND P2, PT, R8, 0x100, PT ;
IMAD.MOV.U32 R9, RZ, RZ, RZ ;
@!P1 STG.E [R2.64], R7 ;
BAR.SYNC.DEFER_BLOCKING 0x0 ;
@P0 BRA 0x570 ;
IMAD.MOV.U32 R3, RZ, RZ, 0x4 ;
IMAD.WIDE R2, R4, R3, c[0x0][0x170] ;
LDG.E R9, [R2.64] ;
BSYNC B0 ;
@!P2 BRA 0xc90 ;
IADD3 R8, R8, -0x100, RZ ;
UMOV UR4, 0x100 ;
ISETP.GE.U32.AND P0, PT, R8.reuse, 0x300, PT ;
LEA.HI R7, R8, 0x1, RZ, 0x18 ;
LOP3.LUT R7, R7, 0x3, RZ, 0xc0, !PT ;
@!P0 BRA 0xbc0 ;
LEA.HI R8, R8, -R7, RZ, 0x18 ;
IMAD.MOV.U32 R3, RZ, RZ, 0x4 ;
IADD3 R2, R4, 0x100, RZ ;
UMOV UR4, 0x100 ;
ISETP.GT.AND P0, PT, R8, -0x1, PT ;
IMAD.WIDE R2, R2, R3, c[0x0][0x170] ;
@!P0 BRA 0xac0 ;
IADD3 R10, R8, 0x1, RZ ;
PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ;
ISETP.GT.AND P2, PT, R10, 0xc, PT ;
@!P2 BRA 0x910 ;
PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ;
LDG.E R22, [R2.64] ;
LDG.E R21, [R2.64+0x400] ;
LDG.E R24, [R2.64+0x800] ;
LDG.E R26, [R2.64+0xc00] ;
LDG.E R28, [R2.64+0x1000] ;
LDG.E R20, [R2.64+0x1400] ;
LDG.E R19, [R2.64+0x1800] ;
LDG.E R18, [R2.64+0x1c00] ;
LDG.E R17, [R2.64+0x2000] ;
LDG.E R16, [R2.64+0x2400] ;
LDG.E R15, [R2.64+0x2800] ;
LDG.E R14, [R2.64+0x2c00] ;
LDG.E R13, [R2.64+0x3000] ;
LDG.E R11, [R2.64+0x3400] ;
LDG.E R12, [R2.64+0x3800] ;
LDG.E R10, [R2.64+0x3c00] ;
IADD3 R8, R8, -0x10, RZ ;
UIADD3 UR4, UR4, 0x1000, URZ ;
ISETP.GT.AND P2, PT, R8, 0xb, PT ;
IADD3 R2, P3, R2, 0x4000, RZ ;
IMAD.X R3, RZ, RZ, R3, P3 ;
FMNMX R22, R22, R9, !PT ;
FMNMX R21, R22, R21, !PT ;
FMNMX R21, R21, R24, !PT ;
FMNMX R21, R21, R26, !PT ;
FMNMX R21, R21, R28, !PT ;
FMNMX R20, R21, R20, !PT ;
FMNMX R19, R20, R19, !PT ;
FMNMX R18, R19, R18, !PT ;
FMNMX R17, R18, R17, !PT ;
FMNMX R16, R17, R16, !PT ;
FMNMX R15, R16, R15, !PT ;
FMNMX R14, R15, R14, !PT ;
FMNMX R14, R14, R13, !PT ;
FMNMX R11, R14, R11, !PT ;
FMNMX R11, R11, R12, !PT ;
FMNMX R9, R11, R10, !PT ;
@P2 BRA 0x6b0 ;
IADD3 R10, R8, 0x1, RZ ;
ISETP.GT.AND P2, PT, R10, 0x4, PT ;
@!P2 BRA 0xaa0 ;
LDG.E R10, [R2.64] ;
LDG.E R11, [R2.64+0x400] ;
LDG.E R13, [R2.64+0x800] ;
LDG.E R15, [R2.64+0xc00] ;
LDG.E R17, [R2.64+0x1000] ;
LDG.E R19, [R2.64+0x1400] ;
LDG.E R21, [R2.64+0x1800] ;
LDG.E R23, [R2.64+0x1c00] ;
PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ;
UIADD3 UR4, UR4, 0x800, URZ ;
IADD3 R8, R8, -0x8, RZ ;
FMNMX R10, R9, R10, !PT ;
FMNMX R10, R10, R11, !PT ;
IADD3 R11, P2, R2, 0x2000, RZ ;
FMNMX R10, R10, R13, !PT ;
IMAD.X R3, RZ, RZ, R3, P2 ;
FMNMX R10, R10, R15, !PT ;
IMAD.MOV.U32 R2, RZ, RZ, R11 ;
FMNMX R10, R10, R17, !PT ;
FMNMX R10, R10, R19, !PT ;
FMNMX R10, R10, R21, !PT ;
FMNMX R9, R10, R23, !PT ;
ISETP.NE.OR P0, PT, R8, -0x1, P0 ;
@!P0 BRA 0xbc0 ;
LDG.E R10, [R2.64] ;
LDG.E R11, [R2.64+0x400] ;
LDG.E R13, [R2.64+0x800] ;
LDG.E R15, [R2.64+0xc00] ;
IADD3 R8, R8, -0x4, RZ ;
UIADD3 UR4, UR4, 0x400, URZ ;
ISETP.NE.AND P0, PT, R8, -0x1, PT ;
FMNMX R10, R10, R9, !PT ;
FMNMX R10, R10, R11, !PT ;
IADD3 R11, P2, R2, 0x1000, RZ ;
FMNMX R10, R10, R13, !PT ;
IMAD.X R12, RZ, RZ, R3, P2 ;
FMNMX R9, R10, R15, !PT ;
IMAD.MOV.U32 R2, RZ, RZ, R11 ;
IMAD.MOV.U32 R3, RZ, RZ, R12 ;
@P0 BRA 0xac0 ;
ISETP.NE.AND P0, PT, R7, RZ, PT ;
@!P0 BRA 0xc90 ;
IADD3 R0, R0, UR4, RZ ;
IMAD.MOV.U32 R3, RZ, RZ, 0x4 ;
IMAD R0, R5, c[0x0][0x0], R0 ;
IMAD.WIDE R2, R0, R3, c[0x0][0x170] ;
LDG.E R0, [R2.64] ;
IADD3 R7, R7, -0x1, RZ ;
ISETP.NE.AND P0, PT, R7, RZ, PT ;
IADD3 R2, P2, R2, 0x400, RZ ;
IMAD.X R3, RZ, RZ, R3, P2 ;
FMNMX R9, R0, R9, !PT ;
@P0 BRA 0xc20 ;
IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x0] ;
STS [R4.X4], R9 ;
IMAD R0, R0, c[0x0][0x0], RZ ;
BAR.SYNC.DEFER_BLOCKING 0x0 ;
ISETP.GE.AND P0, PT, R0, 0x2, PT ;
@!P0 BRA 0xda0 ;
SHF.R.S32.HI R5, RZ, 0x1, R0 ;
ISETP.GE.AND P0, PT, R4, R5, PT ;
@!P0 IMAD R2, R5, 0x4, R6 ;
@!P0 LDS R3, [R4.X4] ;
@!P0 LDS R2, [R2] ;
@!P0 FMNMX R3, R2, R3, !PT ;
@!P0 STS [R4.X4], R3 ;
BAR.SYNC.DEFER_BLOCKING 0x0 ;
ISETP.GT.AND P0, PT, R0, 0x3, PT ;
IMAD.MOV.U32 R0, RZ, RZ, R5 ;
@P0 BRA 0xcf0 ;
@P1 EXIT ;
LDS R5, [RZ] ;
IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x170] ;
IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x174] ;
STG.E [R2.64], R5 ;
EXIT ;
BRA 0xe00;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
```
|
```amdasm
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z12jacobikernelPfS_S_iifffi ; -- Begin function _Z12jacobikernelPfS_S_iifffi
.globl _Z12jacobikernelPfS_S_iifffi
.p2align 8
.type _Z12jacobikernelPfS_S_iifffi,@function
_Z12jacobikernelPfS_S_iifffi: ; @_Z12jacobikernelPfS_S_iifffi
; %bb.0:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x3c
s_load_b128 s[8:11], s[0:1], 0x1c
v_bfe_u32 v1, v0, 10, 10
v_and_b32_e32 v0, 0x3ff, v0
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b32 s16, s[0:1], 0x30
s_mov_b32 s13, exec_lo
s_waitcnt lgkmcnt(0)
s_lshr_b32 s17, s2, 16
s_and_b32 s12, s2, 0xffff
s_load_b64 s[2:3], s[0:1], 0x10
v_mad_u64_u32 v[2:3], null, s15, s17, v[1:2]
v_mad_u64_u32 v[5:6], null, s14, s12, v[0:1]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v4, v2, s8
v_add_nc_u32_e32 v2, v4, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[6:7], 2, v[2:3]
v_add_nc_u32_e32 v3, 1, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v6, vcc_lo, s4, v6
v_add_co_ci_u32_e32 v7, vcc_lo, s5, v7, vcc_lo
global_load_b32 v6, v[6:7], off
v_mul_u32_u24_e32 v7, 18, v1
s_delay_alu instid0(VALU_DEP_1)
v_add_lshl_u32 v5, v7, v0, 2
s_waitcnt vmcnt(0)
ds_store_b32 v5, v6
v_cmpx_gt_u32_e32 2, v0
s_cbranch_execz .LBB0_2
; %bb.1:
v_add_nc_u32_e32 v6, v4, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v7, 31, v6
v_lshlrev_b64 v[6:7], 2, v[6:7]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v6, vcc_lo, s4, v6
v_add_co_ci_u32_e32 v7, vcc_lo, s5, v7, vcc_lo
global_load_b32 v6, v[6:7], off offset:60
s_waitcnt vmcnt(0)
ds_store_b32 v5, v6 offset:64
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s13
s_load_b32 s13, s[0:1], 0x2c
s_mov_b32 s0, exec_lo
v_cmpx_gt_u32_e32 2, v1
s_cbranch_execz .LBB0_4
; %bb.3:
v_lshl_add_u32 v6, s8, 4, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v7, 31, v6
v_lshlrev_b64 v[6:7], 2, v[6:7]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v6, vcc_lo, s4, v6
v_add_co_ci_u32_e32 v7, vcc_lo, s5, v7, vcc_lo
global_load_b32 v2, v[6:7], off
s_waitcnt vmcnt(0)
ds_store_b32 v5, v2 offset:1152
.LBB0_4:
s_or_b32 exec_lo, exec_lo, s0
v_or_b32_e32 v2, v1, v0
s_mov_b32 s0, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_u32_e32 2, v2
s_cbranch_execz .LBB0_6
; %bb.5:
s_lshl_b32 s1, s8, 4
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add3_u32 v6, v4, s1, v3
v_ashrrev_i32_e32 v7, 31, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[6:7], 2, v[6:7]
v_add_co_u32 v6, vcc_lo, s4, v6
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v7, vcc_lo, s5, v7, vcc_lo
global_load_b32 v2, v[6:7], off offset:60
s_waitcnt vmcnt(0)
ds_store_b32 v5, v2 offset:1216
.LBB0_6:
s_or_b32 exec_lo, exec_lo, s0
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
ds_load_2addr_b32 v[6:7], v5 offset0:36 offset1:37
ds_load_b32 v14, v5 offset:152
ds_load_2addr_b32 v[8:9], v5 offset0:18 offset1:19
ds_load_2addr_b32 v[10:11], v5 offset1:1
ds_load_2addr_b32 v[12:13], v5 offset0:2 offset1:20
s_mul_i32 s17, s17, s12
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_ashr_i32 s0, s17, 1
s_cmp_lt_i32 s0, 1
s_waitcnt lgkmcnt(1)
v_dual_add_f32 v2, v8, v11 :: v_dual_add_f32 v5, v10, v6
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_add_f32 v2, v2, v13 :: v_dual_add_f32 v5, v5, v12
v_add_f32_e32 v2, v2, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_mul_f32_e32 v6, s10, v2
v_add3_u32 v2, v4, s8, v3
v_add_f32_e32 v4, v5, v14
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_fmac_f32_e32 v6, s9, v9
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fmac_f32_e32 v6, s11, v4
v_lshlrev_b64 v[3:4], 2, v[2:3]
v_mad_u32_u24 v2, v1, s12, v0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_sub_f32_e32 v5, v6, v9
v_add_co_u32 v0, vcc_lo, s6, v3
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_lshlrev_b32_e32 v3, 2, v2
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v4, vcc_lo
v_and_b32_e32 v4, 0x7fffffff, v5
global_store_b32 v[0:1], v6, off
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
ds_store_b32 v3, v4
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB0_10
.LBB0_7: ; %.lr.ph
; =>This Inner Loop Header: Depth=1
s_mov_b32 s1, exec_lo
v_cmpx_gt_u32_e64 s0, v2
s_cbranch_execz .LBB0_9
; %bb.8: ; in Loop: Header=BB0_7 Depth=1
v_lshl_add_u32 v0, s0, 2, v3
ds_load_b32 v0, v0
ds_load_b32 v1, v3
s_waitcnt lgkmcnt(0)
v_dual_max_f32 v0, v0, v0 :: v_dual_max_f32 v1, v1, v1
s_delay_alu instid0(VALU_DEP_1)
v_max_f32_e32 v0, v1, v0
ds_store_b32 v3, v0
.LBB0_9: ; in Loop: Header=BB0_7 Depth=1
s_or_b32 exec_lo, exec_lo, s1
s_lshr_b32 s1, s0, 1
s_cmp_gt_u32 s0, 1
s_mov_b32 s0, s1
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB0_7
.LBB0_10: ; %._crit_edge
v_cmp_eq_u32_e32 vcc_lo, 0, v2
s_mov_b32 s1, 0
s_and_saveexec_b32 s4, vcc_lo
s_cbranch_execz .LBB0_12
; %bb.11:
v_mov_b32_e32 v0, 0
s_mul_i32 s0, s16, s15
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s0, s0, s14
s_lshl_b64 s[0:1], s[0:1], 2
ds_load_b32 v1, v0
s_add_u32 s0, s2, s0
s_addc_u32 s1, s3, s1
s_waitcnt lgkmcnt(0)
global_store_b32 v0, v1, s[0:1]
.LBB0_12:
s_or_b32 exec_lo, exec_lo, s4
v_mov_b32_e32 v4, 0
s_mov_b32 s1, exec_lo
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
v_cmpx_gt_i32_e64 s13, v2
s_cbranch_execz .LBB0_14
; %bb.13:
global_load_b32 v4, v3, s[2:3]
.LBB0_14:
s_or_b32 exec_lo, exec_lo, s1
s_cmpk_lt_i32 s13, 0x100
s_movk_i32 s1, 0x100
s_cbranch_scc1 .LBB0_17
; %bb.15: ; %.lr.ph120.preheader
v_lshl_add_u32 v0, v2, 2, 0x400
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v0, s0, s2, v0
v_add_co_ci_u32_e64 v1, null, s3, 0, s0
.LBB0_16: ; %.lr.ph120
; =>This Inner Loop Header: Depth=1
global_load_b32 v5, v[0:1], off
s_waitcnt vmcnt(1)
v_max_f32_e32 v4, v4, v4
v_add_co_u32 v0, s0, 0x400, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_add_co_ci_u32_e64 v1, s0, 0, v1, s0
s_addk_i32 s1, 0x100
s_cmp_le_i32 s1, s13
s_waitcnt vmcnt(0)
v_max_f32_e32 v5, v5, v5
s_delay_alu instid0(VALU_DEP_1)
v_max_f32_e32 v4, v4, v5
s_cbranch_scc1 .LBB0_16
.LBB0_17: ; %._crit_edge121
s_mul_i32 s12, s12, s12
s_waitcnt vmcnt(0)
ds_store_b32 v3, v4
s_ashr_i32 s1, s12, 1
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s1, 1
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB0_21
.LBB0_18: ; %.lr.ph123
; =>This Inner Loop Header: Depth=1
s_mov_b32 s4, exec_lo
v_cmpx_gt_u32_e64 s1, v2
s_cbranch_execz .LBB0_20
; %bb.19: ; in Loop: Header=BB0_18 Depth=1
v_lshl_add_u32 v0, s1, 2, v3
ds_load_b32 v0, v0
ds_load_b32 v1, v3
s_waitcnt lgkmcnt(0)
v_dual_max_f32 v0, v0, v0 :: v_dual_max_f32 v1, v1, v1
s_delay_alu instid0(VALU_DEP_1)
v_max_f32_e32 v0, v1, v0
ds_store_b32 v3, v0
.LBB0_20: ; in Loop: Header=BB0_18 Depth=1
s_or_b32 exec_lo, exec_lo, s4
s_lshr_b32 s0, s1, 1
s_cmp_gt_u32 s1, 1
s_mov_b32 s1, s0
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB0_18
.LBB0_21: ; %._crit_edge124
s_and_saveexec_b32 s0, vcc_lo
s_cbranch_execz .LBB0_23
; %bb.22:
v_mov_b32_e32 v0, 0
ds_load_b32 v1, v0
s_waitcnt lgkmcnt(0)
global_store_b32 v0, v1, s[2:3]
.LBB0_23:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z12jacobikernelPfS_S_iifffi
.amdhsa_group_segment_fixed_size 1296
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 304
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 15
.amdhsa_next_free_sgpr 18
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z12jacobikernelPfS_S_iifffi, .Lfunc_end0-_Z12jacobikernelPfS_S_iifffi
; -- End function
.section .AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1204
; NumSgprs: 20
; NumVgprs: 15
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 1296 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 20
; NumVGPRsForWavesPerEU: 15
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object ; @__hip_cuid_
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0 ; 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 36
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: by_value
- .offset: 44
.size: 4
.value_kind: by_value
- .offset: 48
.size: 4
.value_kind: hidden_block_count_x
- .offset: 52
.size: 4
.value_kind: hidden_block_count_y
- .offset: 56
.size: 4
.value_kind: hidden_block_count_z
- .offset: 60
.size: 2
.value_kind: hidden_group_size_x
- .offset: 62
.size: 2
.value_kind: hidden_group_size_y
- .offset: 64
.size: 2
.value_kind: hidden_group_size_z
- .offset: 66
.size: 2
.value_kind: hidden_remainder_x
- .offset: 68
.size: 2
.value_kind: hidden_remainder_y
- .offset: 70
.size: 2
.value_kind: hidden_remainder_z
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 112
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 1296
.kernarg_segment_align: 8
.kernarg_segment_size: 304
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z12jacobikernelPfS_S_iifffi
.private_segment_fixed_size: 0
.sgpr_count: 20
.sgpr_spill_count: 0
.symbol: _Z12jacobikernelPfS_S_iifffi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 15
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
```
| 4,286 | 6,296 |
27 |
Convert the following CUDA host assembly code to AMD host assembly:
```cudaasm
.file "tmpxft_000ca89e_00000000-6_Neeraja_1k_GFLOPS.cudafe1.cpp"
.text
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2063:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2063:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z42__device_stub__Z12jacobikernelPfS_S_iifffiPfS_S_iifffi
.type _Z42__device_stub__Z12jacobikernelPfS_S_iifffiPfS_S_iifffi, @function
_Z42__device_stub__Z12jacobikernelPfS_S_iifffiPfS_S_iifffi:
.LFB2085:
.cfi_startproc
endbr64
subq $200, %rsp
.cfi_def_cfa_offset 208
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movss %xmm0, 12(%rsp)
movss %xmm1, 8(%rsp)
movss %xmm2, 4(%rsp)
movl %r9d, (%rsp)
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
leaq 8(%rsp), %rax
movq %rax, 160(%rsp)
leaq 4(%rsp), %rax
movq %rax, 168(%rsp)
movq %rsp, %rax
movq %rax, 176(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 216
pushq 56(%rsp)
.cfi_def_cfa_offset 224
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z12jacobikernelPfS_S_iifffi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 208
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2085:
.size _Z42__device_stub__Z12jacobikernelPfS_S_iifffiPfS_S_iifffi, .-_Z42__device_stub__Z12jacobikernelPfS_S_iifffiPfS_S_iifffi
.globl _Z12jacobikernelPfS_S_iifffi
.type _Z12jacobikernelPfS_S_iifffi, @function
_Z12jacobikernelPfS_S_iifffi:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z42__device_stub__Z12jacobikernelPfS_S_iifffiPfS_S_iifffi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _Z12jacobikernelPfS_S_iifffi, .-_Z12jacobikernelPfS_S_iifffi
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC3:
.string "JacobiGPU converged in %d iterations to residual %f\n"
.align 8
.LC4:
.string "JacobiGPU used %.5f seconds total\n"
.align 8
.LC5:
.string "Size(Number of Operations) = %.0f Ops/sec \n"
.align 8
.LC6:
.string "Throughtput = %.4f GFlops/sec \n"
.text
.globl _Z9JacobiGPUPfiiffff
.type _Z9JacobiGPUPfiiffff, @function
_Z9JacobiGPUPfiiffff:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $120, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 24(%rsp)
movl %esi, %ebp
movl %edx, %r14d
movss %xmm0, 12(%rsp)
movss %xmm1, 16(%rsp)
movss %xmm2, 20(%rsp)
movss %xmm3, 8(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
movl $0x00000000, 32(%rsp)
leal -2(%rsi), %edx
testb $15, %dl
setne %r12b
movzbl %r12b, %r12d
leal 13(%rsi), %eax
testl %edx, %edx
cmovns %edx, %eax
sarl $4, %eax
addl %eax, %r12d
leal -2(%r14), %edx
testb $15, %dl
setne %bl
movzbl %bl, %ebx
leal 13(%r14), %eax
testl %edx, %edx
cmovns %edx, %eax
sarl $4, %eax
addl %eax, %ebx
movl $0x00000000, _ZL7sumtime(%rip)
movslq %esi, %r13
movslq %r14d, %rax
imulq %rax, %r13
salq $2, %r13
leaq 40(%rsp), %rdi
movq %r13, %rsi
call cudaMalloc@PLT
leaq 48(%rsp), %rdi
movq %r13, %rsi
call cudaMalloc@PLT
movl %r12d, %r15d
imull %ebx, %r15d
movslq %r15d, %rsi
salq $2, %rsi
leaq 56(%rsp), %rdi
call cudaMalloc@PLT
leaq 64(%rsp), %rdi
call cudaEventCreate@PLT
leaq 72(%rsp), %rdi
call cudaEventCreate@PLT
movl $16, 80(%rsp)
movl $16, 84(%rsp)
movl $1, 88(%rsp)
movl %r12d, 92(%rsp)
movl %ebx, 96(%rsp)
movl $1, 100(%rsp)
movl $1, %ecx
movq %r13, %rdx
movq 24(%rsp), %rbx
movq %rbx, %rsi
movq 40(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %r13, %rdx
movq %rbx, %rsi
movq 48(%rsp), %rdi
call cudaMemcpy@PLT
movl $0, %ebx
leaq 32(%rsp), %r12
jmp .L13
.L12:
movl $0, %esi
movq 72(%rsp), %rdi
call cudaEventRecord@PLT
movl $2, %ecx
movl $4, %edx
movq 56(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
leaq 36(%rsp), %rdi
movq 72(%rsp), %rdx
movq 64(%rsp), %rsi
call cudaEventElapsedTime@PLT
movss _ZL7sumtime(%rip), %xmm1
addss 36(%rsp), %xmm1
movss %xmm1, _ZL7sumtime(%rip)
movq 40(%rsp), %rax
movq 48(%rsp), %rdx
movq %rdx, 40(%rsp)
movq %rax, 48(%rsp)
movss 32(%rsp), %xmm0
comiss 8(%rsp), %xmm0
jbe .L17
.L13:
addl $1, %ebx
movl $0, %esi
movq 64(%rsp), %rdi
call cudaEventRecord@PLT
movl 88(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 80(%rsp), %rdx
movq 92(%rsp), %rdi
movl 100(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L12
movl %r15d, %r9d
movss 20(%rsp), %xmm2
movss 16(%rsp), %xmm1
movss 12(%rsp), %xmm0
movl %r14d, %r8d
movl %ebp, %ecx
movq 56(%rsp), %rdx
movq 48(%rsp), %rsi
movq 40(%rsp), %rdi
call _Z42__device_stub__Z12jacobikernelPfS_S_iifffiPfS_S_iifffi
jmp .L12
.L17:
imull %ebx, %ebp
imull %r14d, %ebp
movl %ebp, %eax
sall $4, %eax
subl %ebp, %eax
pxor %xmm5, %xmm5
cvtsi2sdl %eax, %xmm5
movq %xmm5, %rbp
divss .LC1(%rip), %xmm1
cvtss2sd %xmm1, %xmm1
movapd %xmm5, %xmm2
divsd %xmm1, %xmm2
divsd .LC2(%rip), %xmm2
movq %xmm2, %r12
cvtss2sd %xmm0, %xmm0
movl %ebx, %edx
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movss _ZL7sumtime(%rip), %xmm0
divss .LC1(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq %rbp, %xmm0
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq %r12, %xmm0
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl $2, %ecx
movq %r13, %rdx
movq 48(%rsp), %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
movq 48(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rdi
call cudaFree@PLT
movq 64(%rsp), %rdi
call cudaEventDestroy@PLT
movq 72(%rsp), %rdi
call cudaEventDestroy@PLT
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L18
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L18:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size _Z9JacobiGPUPfiiffff, .-_Z9JacobiGPUPfiiffff
.section .rodata.str1.1,"aMS",@progbits,1
.LC7:
.string "%s sizen [sizem]\n"
.LC8:
.string "Jacobi %d x %d\n"
.LC12:
.string "time(gpu ) = %f seconds\n"
.text
.globl main
.type main, @function
main:
.LFB2060:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $56, %rsp
.cfi_def_cfa_offset 112
movq %rsi, %rbp
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
cmpl $1, %edi
jle .L33
movl %edi, %ebx
movq 8(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
testl %eax, %eax
movl $100, %edx
cmovg %eax, %edx
movl %edx, %r14d
movl %edx, %r12d
cmpl $2, %ebx
jg .L34
.L23:
movl %r12d, %ecx
movl %r14d, %edx
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movslq %r12d, %rbp
movslq %r14d, %rax
leaq 0(,%rax,4), %rbx
movq %rbp, %r15
imulq %rbx, %r15
movq %r15, %rdi
call malloc@PLT
movq %rax, %r13
movq %r15, %rcx
movq %r15, %rdx
movl $0, %esi
movq %rax, %rdi
call __memset_chk@PLT
leaq 0(,%rbp,4), %rcx
leaq 0(%r13,%rbx), %rax
movl $0, %ebx
.L24:
pxor %xmm0, %xmm0
cvtsi2ssl %ebx, %xmm0
movss %xmm0, -4(%rax)
movl %ebx, %edx
addl $1, %ebx
addq %rcx, %rax
cmpl %ebx, %r14d
jne .L24
imull %r12d, %edx
movslq %edx, %rax
leaq 0(%r13,%rax,4), %rcx
movl $0, %eax
.L25:
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movss %xmm0, (%rcx,%rax,4)
addq $1, %rax
cmpq %rax, %rbp
jne .L25
addl %r12d, %edx
movslq %edx, %rdx
leal (%r12,%rbx), %eax
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movss %xmm0, -4(%r13,%rdx,4)
movq %rsp, %rdi
movl $0, %esi
call gettimeofday@PLT
movss .LC9(%rip), %xmm3
movaps %xmm3, %xmm2
movaps %xmm3, %xmm1
movss .LC10(%rip), %xmm0
movl %r12d, %edx
movl %ebx, %esi
movq %r13, %rdi
call _Z9JacobiGPUPfiiffff
leaq 16(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
movq 16(%rsp), %rax
subl (%rsp), %eax
imull $1000000, %eax, %eax
subl 8(%rsp), %eax
addl 24(%rsp), %eax
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
divss .LC11(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
leaq .LC12(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl $0, %eax
.L19:
movq 40(%rsp), %rdx
subq %fs:40, %rdx
jne .L35
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L33:
.cfi_restore_state
movq (%rsi), %rcx
leaq .LC7(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
call __fprintf_chk@PLT
movl $1, %eax
jmp .L19
.L34:
movq 16(%rbp), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
testl %eax, %eax
movl $100, %edx
cmovg %eax, %edx
movl %edx, %r12d
jmp .L23
.L35:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2060:
.size main, .-main
.section .rodata.str1.1
.LC13:
.string "_Z12jacobikernelPfS_S_iifffi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2088:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC13(%rip), %rdx
movq %rdx, %rcx
leaq _Z12jacobikernelPfS_S_iifffi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2088:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZL7sumtime
.comm _ZL7sumtime,4,4
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC1:
.long 1148846080
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC2:
.long 0
.long 1104006501
.section .rodata.cst4
.align 4
.LC9:
.long 1036831949
.align 4
.LC10:
.long 1045220557
.align 4
.LC11:
.long 1232348160
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
```
|
```amdasm
.text
.file "Neeraja_1k_GFLOPS.hip"
.globl _Z27__device_stub__jacobikernelPfS_S_iifffi # -- Begin function _Z27__device_stub__jacobikernelPfS_S_iifffi
.type _Z27__device_stub__jacobikernelPfS_S_iifffi,@function
_Z27__device_stub__jacobikernelPfS_S_iifffi: # @_Z27__device_stub__jacobikernelPfS_S_iifffi
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $176, %rsp
.cfi_def_cfa_offset 224
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 56(%rsp), %rax
movq %rdi, (%rax)
leaq 48(%rsp), %rdi
movq %rsi, (%rdi)
leaq 40(%rsp), %rsi
movq %rdx, (%rsi)
leaq 20(%rsp), %rdx
movl %ecx, (%rdx)
leaq 16(%rsp), %rcx
movl %r8d, (%rcx)
leaq 12(%rsp), %r8
movss %xmm0, (%r8)
leaq 8(%rsp), %r10
movss %xmm1, (%r10)
leaq 4(%rsp), %r11
movss %xmm2, (%r11)
movq %rsp, %r14
movl %r9d, (%r14)
leaq 96(%rsp), %rbx
movq %rax, (%rbx)
movq %rdi, 8(%rbx)
movq %rsi, 16(%rbx)
movq %rdx, 24(%rbx)
movq %rcx, 32(%rbx)
movq %r8, 40(%rbx)
movq %r10, 48(%rbx)
movq %r11, 56(%rbx)
movq %r14, 64(%rbx)
leaq 80(%rsp), %r14
leaq 64(%rsp), %r15
leaq 32(%rsp), %r12
leaq 24(%rsp), %r13
movq %r14, %rdi
movq %r15, %rsi
movq %r12, %rdx
movq %r13, %rcx
callq __hipPopCallConfiguration
movq (%r14), %rsi
movl 8(%r14), %edx
movq (%r15), %rcx
movl 8(%r15), %r8d
movl $_Z12jacobikernelPfS_S_iifffi, %edi
movq %rbx, %r9
pushq (%r13)
.cfi_adjust_cfa_offset 8
pushq (%r12)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $192, %rsp
.cfi_adjust_cfa_offset -192
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z27__device_stub__jacobikernelPfS_S_iifffi, .Lfunc_end0-_Z27__device_stub__jacobikernelPfS_S_iifffi
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function _Z9JacobiGPUPfiiffff
.LCPI1_0:
.long 0x447a0000 # float 1000
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0
.LCPI1_1:
.quad 0x41cdcd6500000000 # double 1.0E+9
.text
.globl _Z9JacobiGPUPfiiffff
.type _Z9JacobiGPUPfiiffff,@function
_Z9JacobiGPUPfiiffff: # @_Z9JacobiGPUPfiiffff
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $120, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movss %xmm3, 40(%rsp) # 4-byte Spill
movss %xmm2, 32(%rsp) # 4-byte Spill
movss %xmm1, 80(%rsp) # 4-byte Spill
movss %xmm0, 76(%rsp) # 4-byte Spill
movl %edx, %r15d
movl %esi, %r12d
movq %rdi, 88(%rsp) # 8-byte Spill
xorl %r13d, %r13d
leaq 28(%rsp), %rcx
leal -2(%r12), %eax
leal 13(%r12), %ebx
testl %eax, %eax
cmovnsl %eax, %ebx
sarl $4, %ebx
andl $15, %eax
cmpl $1, %eax
sbbl $-1, %ebx
movl %r13d, (%rcx)
leal -2(%r15), %eax
leal 13(%r15), %ebp
testl %eax, %eax
cmovnsl %eax, %ebp
sarl $4, %ebp
andl $15, %eax
cmpl $1, %eax
sbbl $-1, %ebp
movl %r13d, _ZL7sumtime(%rip)
movslq %esi, %rax
movslq %edx, %r14
imulq %rax, %r14
shlq $2, %r14
leaq 16(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
leaq 8(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
movl %ebp, %eax
imull %ebx, %eax
movl %eax, 72(%rsp) # 4-byte Spill
movslq %eax, %rsi
shlq $2, %rsi
leaq 64(%rsp), %rdi
callq hipMalloc
leaq 56(%rsp), %rdi
callq hipEventCreate
leaq 48(%rsp), %rdi
callq hipEventCreate
shlq $32, %rbp
orq %rbx, %rbp
leaq 16(%rsp), %rax
movq (%rax), %rdi
movq 88(%rsp), %rbx # 8-byte Reload
movq %rbx, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
leaq 8(%rsp), %rax
movq (%rax), %rdi
movq %rbx, %rsi
movq %r14, 96(%rsp) # 8-byte Spill
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
movq %r15, 112(%rsp) # 8-byte Spill
movl %r15d, %eax
movq %r12, 104(%rsp) # 8-byte Spill
imull %r12d, %eax
leal (%rax,%rax,4), %eax
leal (%rax,%rax,2), %ebx
movabsq $68719476752, %r15 # imm = 0x1000000010
leaq 84(%rsp), %r12
xorl %r14d, %r14d
.LBB1_1: # =>This Inner Loop Header: Depth=1
movq 56(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq %rbp, %rdi
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_3
# %bb.2: # in Loop: Header=BB1_1 Depth=1
movq 16(%rsp), %rdi
movq 8(%rsp), %rsi
movq 64(%rsp), %rdx
movq 104(%rsp), %rcx # 8-byte Reload
# kill: def $ecx killed $ecx killed $rcx
movq 112(%rsp), %r8 # 8-byte Reload
# kill: def $r8d killed $r8d killed $r8
movss 76(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
movss 80(%rsp), %xmm1 # 4-byte Reload
# xmm1 = mem[0],zero,zero,zero
movss 32(%rsp), %xmm2 # 4-byte Reload
# xmm2 = mem[0],zero,zero,zero
movl 72(%rsp), %r9d # 4-byte Reload
callq _Z27__device_stub__jacobikernelPfS_S_iifffi
.LBB1_3: # in Loop: Header=BB1_1 Depth=1
movq 48(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 64(%rsp), %rsi
movl $4, %edx
leaq 28(%rsp), %rdi
movl $2, %ecx
callq hipMemcpy
movq 56(%rsp), %rsi
movq 48(%rsp), %rdx
movq %r12, %rdi
callq hipEventElapsedTime
movss 84(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
addss _ZL7sumtime(%rip), %xmm0
movss %xmm0, _ZL7sumtime(%rip)
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq %rcx, 16(%rsp)
movq %rax, 8(%rsp)
movss 28(%rsp), %xmm1 # xmm1 = mem[0],zero,zero,zero
addl %ebx, %r13d
incl %r14d
ucomiss 40(%rsp), %xmm1 # 4-byte Folded Reload
ja .LBB1_1
# %bb.4:
divss .LCPI1_0(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
xorps %xmm2, %xmm2
cvtsi2sd %r13d, %xmm2
movsd %xmm2, 32(%rsp) # 8-byte Spill
divsd %xmm0, %xmm2
divsd .LCPI1_1(%rip), %xmm2
movsd %xmm2, 40(%rsp) # 8-byte Spill
xorps %xmm0, %xmm0
cvtss2sd %xmm1, %xmm0
movl $.L.str, %edi
movl %r14d, %esi
movb $1, %al
callq printf
movss _ZL7sumtime(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero
divss .LCPI1_0(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movl $.L.str.1, %edi
movb $1, %al
callq printf
movl $.L.str.2, %edi
movsd 32(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
movb $1, %al
callq printf
movl $.L.str.3, %edi
movsd 40(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
movb $1, %al
callq printf
movq 8(%rsp), %rsi
movq 88(%rsp), %rdi # 8-byte Reload
movq 96(%rsp), %rdx # 8-byte Reload
movl $2, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq 64(%rsp), %rdi
callq hipFree
movq 56(%rsp), %rdi
callq hipEventDestroy
movq 48(%rsp), %rdi
callq hipEventDestroy
addq $120, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z9JacobiGPUPfiiffff, .Lfunc_end1-_Z9JacobiGPUPfiiffff
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI2_0:
.long 0x3e4ccccd # float 0.200000003
.LCPI2_1:
.long 0x3dcccccd # float 0.100000001
.LCPI2_2:
.long 0x49742400 # float 1.0E+6
.text
.globl main
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $40, %rsp
.cfi_def_cfa_offset 96
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsi, %r15
cmpl $1, %edi
jle .LBB2_1
# %bb.2:
movl %edi, %ebp
movq 8(%r15), %rdi
callq atoi
movl %eax, %ebx
testl %eax, %eax
movl $100, %r12d
cmovlel %r12d, %ebx
movl %ebx, %r14d
cmpl $2, %ebp
je .LBB2_4
# %bb.3:
movq 16(%r15), %rdi
callq atoi
testl %eax, %eax
cmovgl %eax, %r12d
movl %r12d, %r14d
.LBB2_4: # %.lr.ph.preheader.i
xorl %r12d, %r12d
movl $.L.str.5, %edi
movl %ebx, %esi
movl %r14d, %edx
xorl %eax, %eax
callq printf
movslq %ebx, %rbp
movslq %r14d, %r13
movq %rbp, %rsi
imulq %r13, %rsi
shlq $2, %rsi
movl $1, %edi
callq calloc@PLT
movq %rax, %r15
movl %ebp, %eax
leaq (%r15,%rbp,4), %rcx
addq $-4, %rcx
shlq $2, %r13
.LBB2_5: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
xorps %xmm0, %xmm0
cvtsi2ss %r12d, %xmm0
movss %xmm0, (%rcx)
incq %r12
addq %r13, %rcx
cmpq %r12, %rax
jne .LBB2_5
# %bb.6: # %.preheader.i
testl %r14d, %r14d
jle .LBB2_9
# %bb.7: # %.lr.ph30.i
leal -1(%rbx), %eax
imull %r14d, %eax
movslq %eax, %rcx
movl %r14d, %eax
leaq (%r15,%rcx,4), %rcx
xorl %edx, %edx
.LBB2_8: # =>This Inner Loop Header: Depth=1
xorps %xmm0, %xmm0
cvtsi2ss %edx, %xmm0
movss %xmm0, (%rcx,%rdx,4)
incq %rdx
cmpq %rdx, %rax
jne .LBB2_8
.LBB2_9: # %_ZL4initPfii.exit
leal (%r14,%rbx), %eax
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movl %ebx, %eax
imull %r14d, %eax
cltq
movss %xmm0, -4(%r15,%rax,4)
xorl %r12d, %r12d
leaq 24(%rsp), %r13
movq %r13, %rdi
xorl %esi, %esi
callq gettimeofday
movss .LCPI2_0(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero
movss .LCPI2_1(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero
movq %r15, %rdi
movl %ebx, %esi
movl %r14d, %edx
movaps %xmm1, %xmm2
movaps %xmm1, %xmm3
callq _Z9JacobiGPUPfiiffff
leaq 8(%rsp), %rbx
movq %rbx, %rdi
xorl %esi, %esi
callq gettimeofday
movq (%rbx), %rax
subq (%r13), %rax
movabsq $4294967296000000, %rcx # imm = 0xF424000000000
imulq %rax, %rcx
shrq $32, %rcx
movl 8(%rbx), %eax
subl 8(%r13), %eax
addl %eax, %ecx
xorps %xmm0, %xmm0
cvtsi2ss %ecx, %xmm0
divss .LCPI2_2(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movl $.L.str.6, %edi
movb $1, %al
callq printf
.LBB2_10:
movl %r12d, %eax
addq $40, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB2_1:
.cfi_def_cfa_offset 96
movq stderr(%rip), %rdi
movq (%r15), %rdx
movl $.L.str.4, %esi
xorl %eax, %eax
callq fprintf
movl $1, %r12d
jmp .LBB2_10
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, %rdi
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12jacobikernelPfS_S_iifffi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z12jacobikernelPfS_S_iifffi,@object # @_Z12jacobikernelPfS_S_iifffi
.section .rodata,"a",@progbits
.globl _Z12jacobikernelPfS_S_iifffi
.p2align 3, 0x0
_Z12jacobikernelPfS_S_iifffi:
.quad _Z27__device_stub__jacobikernelPfS_S_iifffi
.size _Z12jacobikernelPfS_S_iifffi, 8
.type _ZL7sumtime,@object # @_ZL7sumtime
.local _ZL7sumtime
.comm _ZL7sumtime,4,4
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "JacobiGPU converged in %d iterations to residual %f\n"
.size .L.str, 54
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "JacobiGPU used %.5f seconds total\n"
.size .L.str.1, 36
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Size(Number of Operations) = %.0f Ops/sec \n"
.size .L.str.2, 44
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Throughtput = %.4f GFlops/sec \n"
.size .L.str.3, 32
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "%s sizen [sizem]\n"
.size .L.str.4, 18
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "Jacobi %d x %d\n"
.size .L.str.5, 16
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "time(gpu ) = %f seconds\n"
.size .L.str.6, 25
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z12jacobikernelPfS_S_iifffi"
.size .L__unnamed_1, 29
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z27__device_stub__jacobikernelPfS_S_iifffi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z12jacobikernelPfS_S_iifffi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
```
| 6,623 | 7,469 |
28 |
Convert the following CUDA device assembly code to AMD device assembly:
```cudaasm
code for sm_80
Function : _Z11myMatrixAddiPjS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
MOV R1, c[0x0][0x28] ;
S2R R4, SR_CTAID.X ;
HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ;
ULDC.64 UR4, c[0x0][0x118] ;
S2R R3, SR_TID.X ;
IMAD R4, R4, c[0x0][0x0], R3 ;
IMAD.WIDE R2, R4, R5, c[0x0][0x170] ;
IMAD.WIDE R4, R4, R5, c[0x0][0x168] ;
LDG.E R2, [R2.64] ;
LDG.E R7, [R4.64] ;
IADD3 R7, R2, R7, RZ ;
STG.E [R4.64], R7 ;
EXIT ;
BRA 0xd0;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
Function : _Z11myMatrixMuliPjS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ;
S2R R0, SR_CTAID.X ;
IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x160] ;
S2R R3, SR_TID.X ;
IMAD R0, R0, c[0x0][0x0], R3 ;
IMAD R3, R2, c[0x0][0x160], RZ ;
ISETP.GE.AND P0, PT, R0, R3, PT ;
@P0 EXIT ;
ISETP.GE.AND P0, PT, R2, 0x1, PT ;
ULDC.64 UR4, c[0x0][0x118] ;
HFMA2.MMA R12, -RZ, RZ, 0, 0 ;
@!P0 BRA 0xb70 ;
IABS R6, c[0x0][0x160] ;
IABS R7, R0 ;
I2F.RP R4, R6 ;
ISETP.GE.AND P1, PT, R0, RZ, PT ;
MOV R12, RZ ;
MUFU.RCP R4, R4 ;
IADD3 R2, R4, 0xffffffe, RZ ;
F2I.FTZ.U32.TRUNC.NTZ R3, R2 ;
MOV R2, RZ ;
IMAD.MOV R5, RZ, RZ, -R3 ;
IMAD R5, R5, R6, RZ ;
IMAD.HI.U32 R3, R3, R5, R2 ;
LOP3.LUT R2, RZ, c[0x0][0x160], RZ, 0x33, !PT ;
IMAD.MOV.U32 R5, RZ, RZ, R7 ;
IMNMX R4, R2, -0x2, !PT ;
IMAD.HI.U32 R3, R3, R5, RZ ;
IADD3 R3, -R3, RZ, RZ ;
IMAD R3, R6, R3, R5 ;
MOV R5, 0x4 ;
ISETP.GT.U32.AND P0, PT, R6, R3, PT ;
@!P0 IMAD.IADD R3, R3, 0x1, -R6 ;
ISETP.GT.U32.AND P0, PT, R6, R3, PT ;
@!P0 IADD3 R3, R3, -R6, RZ ;
IADD3 R6, R4, c[0x0][0x160], RZ ;
ISETP.NE.AND P0, PT, RZ, c[0x0][0x160], PT ;
@!P1 IMAD.MOV R3, RZ, RZ, -R3 ;
IADD3 R4, R6.reuse, 0x1, RZ ;
IADD3 R7, R6, 0x2, RZ ;
SEL R3, R2, R3, !P0 ;
ISETP.GE.U32.AND P0, PT, R4, 0x3, PT ;
LOP3.LUT R7, R7, 0x3, RZ, 0xc0, !PT ;
IMAD.IADD R2, R0, 0x1, -R3 ;
IMAD R4, R3, c[0x0][0x160], RZ ;
IMAD.WIDE R2, R2, R5, c[0x0][0x170] ;
IMAD.WIDE R4, R4, R5, c[0x0][0x178] ;
@!P0 BRA 0xab0 ;
IMAD.IADD R9, R6, 0x1, -R7 ;
HFMA2.MMA R12, -RZ, RZ, 0, 0 ;
ISETP.GT.AND P0, PT, R9, -0x2, PT ;
@!P0 BRA 0x940 ;
IADD3 R6, R9, 0x2, RZ ;
PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ;
ISETP.GT.AND P1, PT, R6, 0xc, PT ;
@!P1 BRA 0x700 ;
PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ;
LDG.E R17, [R4.64] ;
LDG.E R14, [R2.64] ;
LDG.E R19, [R4.64+0x4] ;
LDG.E R22, [R2.64+0x4] ;
LDG.E R21, [R4.64+0x8] ;
LDG.E R16, [R2.64+0x8] ;
LDG.E R18, [R4.64+0xc] ;
LDG.E R23, [R2.64+0xc] ;
LDG.E R20, [R4.64+0x10] ;
LDG.E R25, [R2.64+0x10] ;
LDG.E R10, [R4.64+0x14] ;
LDG.E R15, [R2.64+0x14] ;
LDG.E R8, [R4.64+0x18] ;
LDG.E R13, [R2.64+0x18] ;
LDG.E R6, [R4.64+0x1c] ;
LDG.E R11, [R2.64+0x1c] ;
LDG.E R27, [R4.64+0x38] ;
IMAD R14, R17, R14, R12 ;
LDG.E R12, [R4.64+0x20] ;
LDG.E R17, [R2.64+0x20] ;
IMAD R22, R19, R22, R14 ;
LDG.E R14, [R4.64+0x24] ;
LDG.E R19, [R2.64+0x24] ;
IMAD R22, R21, R16, R22 ;
LDG.E R16, [R4.64+0x28] ;
LDG.E R21, [R2.64+0x28] ;
IMAD R22, R18, R23, R22 ;
LDG.E R18, [R4.64+0x2c] ;
LDG.E R23, [R2.64+0x2c] ;
IMAD R22, R20, R25, R22 ;
LDG.E R20, [R4.64+0x30] ;
LDG.E R25, [R2.64+0x30] ;
IMAD R22, R10, R15, R22 ;
LDG.E R15, [R4.64+0x34] ;
LDG.E R10, [R2.64+0x34] ;
IMAD R24, R8, R13, R22 ;
LDG.E R8, [R2.64+0x38] ;
LDG.E R13, [R4.64+0x3c] ;
LDG.E R22, [R2.64+0x3c] ;
IMAD R6, R6, R11, R24 ;
IADD3 R9, R9, -0x10, RZ ;
ISETP.GT.AND P1, PT, R9, 0xa, PT ;
IADD3 R4, P3, R4, 0x40, RZ ;
IADD3 R2, P2, R2, 0x40, RZ ;
IMAD.X R5, RZ, RZ, R5, P3 ;
IADD3.X R3, RZ, R3, RZ, P2, !PT ;
IMAD R6, R12, R17, R6 ;
IMAD R6, R14, R19, R6 ;
IMAD R6, R16, R21, R6 ;
IMAD R6, R18, R23, R6 ;
IMAD R6, R20, R25, R6 ;
IMAD R6, R15, R10, R6 ;
IMAD R6, R27, R8, R6 ;
IMAD R12, R13, R22, R6 ;
@P1 BRA 0x390 ;
IADD3 R6, R9, 0x2, RZ ;
ISETP.GT.AND P1, PT, R6, 0x4, PT ;
@!P1 BRA 0x920 ;
LDG.E R15, [R4.64] ;
LDG.E R10, [R2.64] ;
LDG.E R17, [R4.64+0x4] ;
LDG.E R14, [R2.64+0x4] ;
LDG.E R19, [R4.64+0x8] ;
LDG.E R16, [R2.64+0x8] ;
LDG.E R21, [R4.64+0xc] ;
LDG.E R18, [R2.64+0xc] ;
LDG.E R23, [R4.64+0x10] ;
LDG.E R20, [R2.64+0x10] ;
LDG.E R25, [R4.64+0x14] ;
LDG.E R22, [R2.64+0x14] ;
LDG.E R13, [R4.64+0x18] ;
LDG.E R6, [R2.64+0x18] ;
LDG.E R8, [R4.64+0x1c] ;
LDG.E R11, [R2.64+0x1c] ;
PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ;
IADD3 R9, R9, -0x8, RZ ;
IADD3 R4, P2, R4, 0x20, RZ ;
IADD3.X R5, RZ, R5, RZ, P2, !PT ;
IMAD R10, R15, R10, R12 ;
IMAD R10, R17, R14, R10 ;
IADD3 R14, P1, R2, 0x20, RZ ;
IMAD.X R3, RZ, RZ, R3, P1 ;
IMAD R10, R19, R16, R10 ;
IMAD.MOV.U32 R2, RZ, RZ, R14 ;
IMAD R10, R21, R18, R10 ;
IMAD R10, R23, R20, R10 ;
IMAD R10, R25, R22, R10 ;
IMAD R6, R13, R6, R10 ;
IMAD R12, R8, R11, R6 ;
ISETP.NE.OR P0, PT, R9, -0x2, P0 ;
@!P0 BRA 0xab0 ;
LDG.E R11, [R4.64] ;
LDG.E R6, [R2.64] ;
LDG.E R13, [R4.64+0x4] ;
LDG.E R8, [R2.64+0x4] ;
LDG.E R15, [R4.64+0x8] ;
LDG.E R10, [R2.64+0x8] ;
LDG.E R17, [R4.64+0xc] ;
LDG.E R14, [R2.64+0xc] ;
IADD3 R9, R9, -0x4, RZ ;
ISETP.NE.AND P0, PT, R9, -0x2, PT ;
IMAD R6, R11, R6, R12 ;
IADD3 R11, P2, R4, 0x10, RZ ;
MOV R4, R11 ;
IMAD R6, R13, R8, R6 ;
IADD3 R13, P1, R2, 0x10, RZ ;
IADD3.X R8, RZ, R5, RZ, P2, !PT ;
MOV R2, R13 ;
IMAD R6, R15, R10, R6 ;
IMAD.X R10, RZ, RZ, R3, P1 ;
IMAD.MOV.U32 R5, RZ, RZ, R8 ;
IMAD.MOV.U32 R3, RZ, RZ, R10 ;
IMAD R12, R17, R14, R6 ;
@P0 BRA 0x940 ;
ISETP.NE.AND P0, PT, R7, RZ, PT ;
@!P0 BRA 0xb70 ;
LDG.E R9, [R4.64] ;
LDG.E R6, [R2.64] ;
IADD3 R7, R7, -0x1, RZ ;
ISETP.NE.AND P0, PT, R7, RZ, PT ;
IADD3 R4, P2, R4, 0x4, RZ ;
IADD3 R2, P1, R2, 0x4, RZ ;
IMAD.X R5, RZ, RZ, R5, P2 ;
IADD3.X R3, RZ, R3, RZ, P1, !PT ;
IMAD R12, R9, R6, R12 ;
@P0 BRA 0xad0 ;
MOV R3, 0x4 ;
IMAD.WIDE R2, R0, R3, c[0x0][0x168] ;
STG.E [R2.64], R12 ;
EXIT ;
BRA 0xbb0;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
```
|
```amdasm
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z11myMatrixMuliPjS_S_ ; -- Begin function _Z11myMatrixMuliPjS_S_
.globl _Z11myMatrixMuliPjS_S_
.p2align 8
.type _Z11myMatrixMuliPjS_S_,@function
_Z11myMatrixMuliPjS_S_: ; @_Z11myMatrixMuliPjS_S_
; %bb.0:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x2c
s_load_b32 s2, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(SALU_CYCLE_1)
v_mad_u64_u32 v[1:2], null, s15, s3, v[0:1]
s_mul_i32 s3, s2, s2
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_cmp_gt_i32_e32 vcc_lo, s3, v1
s_and_saveexec_b32 s3, vcc_lo
s_cbranch_execz .LBB0_6
; %bb.1:
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x8
s_load_b64 s[0:1], s[0:1], 0x18
v_ashrrev_i32_e32 v2, 31, v1
s_cmp_lt_i32 s2, 1
s_cbranch_scc1 .LBB0_4
; %bb.2: ; %.lr.ph.preheader
s_ashr_i32 s3, s2, 31
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_add_nc_u32_e32 v4, v1, v2
s_add_i32 s8, s2, s3
s_xor_b32 s3, s8, s3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_xor_b32_e32 v4, v4, v2
v_cvt_f32_u32_e32 v0, s3
s_sub_i32 s8, 0, s3
v_rcp_iflag_f32_e32 v0, v0
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v0, 0x4f7ffffe, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_u32_f32_e32 v0, v0
v_mul_lo_u32 v3, s8, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v3, v0, v3
v_add_nc_u32_e32 v0, v0, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v0, v4, v0
v_mul_lo_u32 v0, v0, s3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v0, v4, v0
v_subrev_nc_u32_e32 v3, s3, v0
v_cmp_le_u32_e32 vcc_lo, s3, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v0, v0, v3, vcc_lo
v_subrev_nc_u32_e32 v3, s3, v0
v_cmp_le_u32_e32 vcc_lo, s3, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v0, v0, v3, vcc_lo
v_xor_b32_e32 v0, v0, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v0, v0, v2
v_sub_nc_u32_e32 v3, v1, v0
v_mul_lo_u32 v5, v0, s2
v_mov_b32_e32 v0, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_ashrrev_i32_e32 v4, 31, v3
v_ashrrev_i32_e32 v6, 31, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[3:4], 2, v[3:4]
v_lshlrev_b64 v[5:6], 2, v[5:6]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v3, vcc_lo, s6, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s7, v4, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v5, vcc_lo, s0, v5
v_add_co_ci_u32_e32 v6, vcc_lo, s1, v6, vcc_lo
s_add_i32 s0, s2, 1
.LBB0_3: ; %.lr.ph
; =>This Inner Loop Header: Depth=1
global_load_b32 v9, v[3:4], off
global_load_b32 v10, v[5:6], off
v_add_co_u32 v3, vcc_lo, v3, 4
v_add_co_ci_u32_e32 v4, vcc_lo, 0, v4, vcc_lo
v_add_co_u32 v5, vcc_lo, v5, 4
v_add_co_ci_u32_e32 v6, vcc_lo, 0, v6, vcc_lo
s_add_i32 s0, s0, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
s_cmp_lt_u32 s0, 2
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[7:8], null, v10, v9, v[0:1]
v_mov_b32_e32 v0, v7
s_cbranch_scc0 .LBB0_3
s_branch .LBB0_5
.LBB0_4:
v_mov_b32_e32 v0, 0
.LBB0_5: ; %Flow44
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v1, vcc_lo, s4, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, s5, v2, vcc_lo
global_store_b32 v[1:2], v0, off
.LBB0_6:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11myMatrixMuliPjS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 11
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z11myMatrixMuliPjS_S_, .Lfunc_end0-_Z11myMatrixMuliPjS_S_
; -- End function
.section .AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 472
; NumSgprs: 18
; NumVgprs: 11
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 11
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
.text
.protected _Z11myMatrixAddiPjS_ ; -- Begin function _Z11myMatrixAddiPjS_
.globl _Z11myMatrixAddiPjS_
.p2align 8
.type _Z11myMatrixAddiPjS_,@function
_Z11myMatrixAddiPjS_: ; @_Z11myMatrixAddiPjS_
; %bb.0:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x24
s_load_b128 s[0:3], s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
v_add_co_u32 v2, vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[0:1], off
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v2, v3, v2
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11myMatrixAddiPjS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z11myMatrixAddiPjS_, .Lfunc_end1-_Z11myMatrixAddiPjS_
; -- End function
.section .AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 132
; NumSgprs: 18
; NumVgprs: 4
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 4
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object ; @__hip_cuid_
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0 ; 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11myMatrixMuliPjS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z11myMatrixMuliPjS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 11
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11myMatrixAddiPjS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z11myMatrixAddiPjS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
```
| 3,803 | 6,062 |
29 |
Convert the following CUDA host assembly code to AMD host assembly:
```cudaasm
.file "tmpxft_000e96c3_00000000-6_main.cudafe1.cpp"
.text
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2064:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2064:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z7CeilDivii
.type _Z7CeilDivii, @function
_Z7CeilDivii:
.LFB2057:
.cfi_startproc
endbr64
leal -1(%rdi), %eax
cltd
idivl %esi
addl $1, %eax
ret
.cfi_endproc
.LFE2057:
.size _Z7CeilDivii, .-_Z7CeilDivii
.globl _Z8rand_genjiPj
.type _Z8rand_genjiPj, @function
_Z8rand_genjiPj:
.LFB2058:
.cfi_startproc
endbr64
movl %edi, %r8d
movq %rdx, %r9
movl %esi, %edi
imull %esi, %edi
testl %esi, %esi
jle .L4
movslq %esi, %r10
leaq 0(,%r10,4), %r11
addl %r8d, %esi
movl $2, %eax
.L6:
movl $0, %ecx
.L7:
imull %eax, %eax
addl %r8d, %eax
addl %ecx, %eax
movl $0, %edx
divl %edi
movl %edx, %eax
movl %edx, (%r9,%rcx,4)
addq $1, %rcx
cmpq %rcx, %r10
jne .L7
addq %r11, %r9
addl $1, %r8d
cmpl %r8d, %esi
jne .L6
.L4:
ret
.cfi_endproc
.LFE2058:
.size _Z8rand_genjiPj, .-_Z8rand_genjiPj
.globl _Z10rand_gen_tjiPj
.type _Z10rand_gen_tjiPj, @function
_Z10rand_gen_tjiPj:
.LFB2059:
.cfi_startproc
endbr64
movl %edi, %r8d
movl %esi, %edi
imull %esi, %edi
testl %esi, %esi
jle .L15
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movl %esi, %r9d
movq %rdx, %r11
movslq %esi, %r10
salq $2, %r10
movl $0, %ebx
movl $2, %eax
.L11:
movq %r11, %rsi
movl $0, %ecx
.L12:
imull %eax, %eax
addl %r8d, %eax
addl %ecx, %eax
movl $0, %edx
divl %edi
movl %edx, %eax
movl %edx, (%rsi)
movl %ecx, %edx
addl $1, %ecx
addq %r10, %rsi
cmpl %ecx, %r9d
jne .L12
leal 1(%rbx), %ecx
addq $4, %r11
addl $1, %r8d
cmpl %edx, %ebx
je .L9
movl %ecx, %ebx
jmp .L11
.L9:
popq %rbx
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore 3
ret
.cfi_endproc
.LFE2059:
.size _Z10rand_gen_tjiPj, .-_Z10rand_gen_tjiPj
.globl _Z9signatureiPj
.type _Z9signatureiPj, @function
_Z9signatureiPj:
.LFB2060:
.cfi_startproc
endbr64
imull %edi, %edi
testl %edi, %edi
jle .L21
movl %edi, %edi
leaq (%rsi,%rdi,4), %rdx
movl $0, %eax
.L20:
addl (%rsi), %eax
imull $-1640531535, %eax, %eax
addq $4, %rsi
cmpq %rdx, %rsi
jne .L20
ret
.L21:
movl $0, %eax
ret
.cfi_endproc
.LFE2060:
.size _Z9signatureiPj, .-_Z9signatureiPj
.globl _Z36__device_stub__Z11myMatrixMuliPjS_S_iPjS_S_
.type _Z36__device_stub__Z11myMatrixMuliPjS_S_iPjS_S_, @function
_Z36__device_stub__Z11myMatrixMuliPjS_S_iPjS_S_:
.LFB2086:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 28(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %rcx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L27
.L23:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L28
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L27:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z11myMatrixMuliPjS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L23
.L28:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2086:
.size _Z36__device_stub__Z11myMatrixMuliPjS_S_iPjS_S_, .-_Z36__device_stub__Z11myMatrixMuliPjS_S_iPjS_S_
.globl _Z11myMatrixMuliPjS_S_
.type _Z11myMatrixMuliPjS_S_, @function
_Z11myMatrixMuliPjS_S_:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z36__device_stub__Z11myMatrixMuliPjS_S_iPjS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _Z11myMatrixMuliPjS_S_, .-_Z11myMatrixMuliPjS_S_
.globl _Z34__device_stub__Z11myMatrixAddiPjS_iPjS_
.type _Z34__device_stub__Z11myMatrixAddiPjS_iPjS_, @function
_Z34__device_stub__Z11myMatrixAddiPjS_iPjS_:
.LFB2088:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movl %edi, 28(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L35
.L31:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L36
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L35:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z11myMatrixAddiPjS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L31
.L36:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2088:
.size _Z34__device_stub__Z11myMatrixAddiPjS_iPjS_, .-_Z34__device_stub__Z11myMatrixAddiPjS_iPjS_
.globl _Z11myMatrixAddiPjS_
.type _Z11myMatrixAddiPjS_, @function
_Z11myMatrixAddiPjS_:
.LFB2089:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z34__device_stub__Z11myMatrixAddiPjS_iPjS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2089:
.size _Z11myMatrixAddiPjS_, .-_Z11myMatrixAddiPjS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%d"
.LC1:
.string "%u\n"
.text
.globl main
.type main, @function
main:
.LFB2061:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $160, %rsp
.cfi_def_cfa_offset 208
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 4(%rsp), %rsi
leaq .LC0(%rip), %rdi
call __isoc23_scanf@PLT
leaq 32(%rsp), %rbx
leaq 56(%rsp), %r12
leaq .LC0(%rip), %rbp
.L40:
movq %rbx, %rsi
movq %rbp, %rdi
movl $0, %eax
call __isoc23_scanf@PLT
addq $4, %rbx
cmpq %r12, %rbx
jne .L40
leaq IN(%rip), %rbp
movq %rbp, %r12
movl $0, %ebx
jmp .L44
.L41:
movl 32(%rsp,%rbx,4), %edi
movq %r12, %rdx
movl 4(%rsp), %esi
call _Z10rand_gen_tjiPj
addq $1, %rbx
cmpq $6, %rbx
je .L43
addq $4194304, %r12
.L44:
testl $-3, %ebx
jne .L41
movl 32(%rsp,%rbx,4), %edi
movq %r12, %rdx
movl 4(%rsp), %esi
call _Z8rand_genjiPj
addq $1, %rbx
addq $4194304, %r12
jmp .L44
.L43:
leaq 96(%rsp), %rbx
leaq 25165824(%rbp), %r13
movq %rbx, %r12
.L45:
movslq 4(%rsp), %rsi
imulq %rsi, %rsi
salq $2, %rsi
movq %r12, %rdi
call cudaMalloc@PLT
movslq 4(%rsp), %rdx
imulq %rdx, %rdx
salq $2, %rdx
movq (%r12), %rdi
movl $1, %ecx
movq %rbp, %rsi
call cudaMemcpy@PLT
addq $8, %r12
addq $4194304, %rbp
cmpq %r13, %rbp
jne .L45
leaq 64(%rsp), %rbp
leaq 96(%rsp), %r13
movq %rbp, %r12
.L46:
movslq 4(%rsp), %rsi
imulq %rsi, %rsi
salq $2, %rsi
movq %r12, %rdi
call cudaMalloc@PLT
addq $8, %r12
cmpq %r13, %r12
jne .L46
movl 4(%rsp), %eax
imull %eax, %eax
leal 30(%rax), %edx
subl $1, %eax
cmovs %edx, %eax
sarl $5, %eax
addl $1, %eax
movl %eax, 8(%rsp)
movl $1, 12(%rsp)
movl $1, 16(%rsp)
movl $32, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L62
.L47:
movl 28(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movq 8(%rsp), %rdi
movl 16(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L63
.L48:
movl 28(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movq 8(%rsp), %rdi
movl 16(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L64
.L49:
movl 28(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movq 8(%rsp), %rdi
movl 16(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L65
.L50:
movl 28(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movq 8(%rsp), %rdi
movl 16(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L66
.L51:
movl 28(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movq 8(%rsp), %rdi
movl 16(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L67
.L52:
movslq 4(%rsp), %rdx
imulq %rdx, %rdx
salq $2, %rdx
movl $2, %ecx
movq 64(%rsp), %rsi
leaq IN(%rip), %r12
movq %r12, %rdi
call cudaMemcpy@PLT
movslq 4(%rsp), %rdx
imulq %rdx, %rdx
salq $2, %rdx
movl $2, %ecx
movq 88(%rsp), %rsi
leaq 4194304(%r12), %r14
movq %r14, %rdi
call cudaMemcpy@PLT
movq %r12, %rsi
movl 4(%rsp), %edi
call _Z9signatureiPj
movl %eax, %edx
leaq .LC1(%rip), %r12
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %r14, %rsi
movl 4(%rsp), %edi
call _Z9signatureiPj
movl %eax, %edx
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 48(%rbx), %r12
.L53:
movq (%rbx), %rdi
call cudaFree@PLT
addq $8, %rbx
cmpq %r12, %rbx
jne .L53
.L54:
movq 0(%rbp), %rdi
call cudaFree@PLT
addq $8, %rbp
cmpq %r13, %rbp
jne .L54
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L68
movl $0, %eax
addq $160, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L62:
.cfi_restore_state
movq 104(%rsp), %rcx
movq 96(%rsp), %rdx
movq 64(%rsp), %rsi
movl 4(%rsp), %edi
call _Z36__device_stub__Z11myMatrixMuliPjS_S_iPjS_S_
jmp .L47
.L63:
movq 120(%rsp), %rcx
movq 112(%rsp), %rdx
movq 72(%rsp), %rsi
movl 4(%rsp), %edi
call _Z36__device_stub__Z11myMatrixMuliPjS_S_iPjS_S_
jmp .L48
.L64:
movq 128(%rsp), %rcx
movq 64(%rsp), %rdx
movq 88(%rsp), %rsi
movl 4(%rsp), %edi
call _Z36__device_stub__Z11myMatrixMuliPjS_S_iPjS_S_
jmp .L49
.L65:
movq 136(%rsp), %rcx
movq 72(%rsp), %rdx
movq 96(%rsp), %rsi
movl 4(%rsp), %edi
call _Z36__device_stub__Z11myMatrixMuliPjS_S_iPjS_S_
jmp .L50
.L66:
movq 72(%rsp), %rdx
movq 64(%rsp), %rsi
movl 4(%rsp), %edi
call _Z34__device_stub__Z11myMatrixAddiPjS_iPjS_
jmp .L51
.L67:
movq 96(%rsp), %rdx
movq 88(%rsp), %rsi
movl 4(%rsp), %edi
call _Z34__device_stub__Z11myMatrixAddiPjS_iPjS_
jmp .L52
.L68:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2061:
.size main, .-main
.section .rodata.str1.1
.LC2:
.string "_Z11myMatrixAddiPjS_"
.LC3:
.string "_Z11myMatrixMuliPjS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2091:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z11myMatrixAddiPjS_(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z11myMatrixMuliPjS_S_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2091:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl IN
.bss
.align 32
.type IN, @object
.size IN, 25165824
IN:
.zero 25165824
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
```
|
```amdasm
.text
.file "main.hip"
.globl _Z7CeilDivii # -- Begin function _Z7CeilDivii
.type _Z7CeilDivii,@function
_Z7CeilDivii: # @_Z7CeilDivii
.cfi_startproc
# %bb.0:
# kill: def $edi killed $edi def $rdi
leal -1(%rdi), %eax
cltd
idivl %esi
incl %eax
retq
.Lfunc_end0:
.size _Z7CeilDivii, .Lfunc_end0-_Z7CeilDivii
.cfi_endproc
# -- End function
.globl _Z26__device_stub__myMatrixMuliPjS_S_ # -- Begin function _Z26__device_stub__myMatrixMuliPjS_S_
.type _Z26__device_stub__myMatrixMuliPjS_S_,@function
_Z26__device_stub__myMatrixMuliPjS_S_: # @_Z26__device_stub__myMatrixMuliPjS_S_
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $112, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 4(%rsp), %rax
movl %edi, (%rax)
leaq 40(%rsp), %rdi
movq %rsi, (%rdi)
leaq 32(%rsp), %rsi
movq %rdx, (%rsi)
leaq 24(%rsp), %rdx
movq %rcx, (%rdx)
leaq 80(%rsp), %rbx
movq %rax, (%rbx)
movq %rdi, 8(%rbx)
movq %rsi, 16(%rbx)
movq %rdx, 24(%rbx)
leaq 64(%rsp), %r14
leaq 48(%rsp), %r15
leaq 16(%rsp), %r12
leaq 8(%rsp), %r13
movq %r14, %rdi
movq %r15, %rsi
movq %r12, %rdx
movq %r13, %rcx
callq __hipPopCallConfiguration
movq (%r14), %rsi
movl 8(%r14), %edx
movq (%r15), %rcx
movl 8(%r15), %r8d
movl $_Z11myMatrixMuliPjS_S_, %edi
movq %rbx, %r9
pushq (%r13)
.cfi_adjust_cfa_offset 8
pushq (%r12)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $128, %rsp
.cfi_adjust_cfa_offset -128
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z26__device_stub__myMatrixMuliPjS_S_, .Lfunc_end1-_Z26__device_stub__myMatrixMuliPjS_S_
.cfi_endproc
# -- End function
.globl _Z26__device_stub__myMatrixAddiPjS_ # -- Begin function _Z26__device_stub__myMatrixAddiPjS_
.type _Z26__device_stub__myMatrixAddiPjS_,@function
_Z26__device_stub__myMatrixAddiPjS_: # @_Z26__device_stub__myMatrixAddiPjS_
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $112, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 12(%rsp), %rax
movl %edi, (%rax)
leaq 40(%rsp), %rcx
movq %rsi, (%rcx)
leaq 32(%rsp), %rsi
movq %rdx, (%rsi)
leaq 80(%rsp), %rbx
movq %rax, (%rbx)
movq %rcx, 8(%rbx)
movq %rsi, 16(%rbx)
leaq 64(%rsp), %r14
leaq 48(%rsp), %r15
leaq 24(%rsp), %r12
leaq 16(%rsp), %r13
movq %r14, %rdi
movq %r15, %rsi
movq %r12, %rdx
movq %r13, %rcx
callq __hipPopCallConfiguration
movq (%r14), %rsi
movl 8(%r14), %edx
movq (%r15), %rcx
movl 8(%r15), %r8d
movl $_Z11myMatrixAddiPjS_, %edi
movq %rbx, %r9
pushq (%r13)
.cfi_adjust_cfa_offset 8
pushq (%r12)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $128, %rsp
.cfi_adjust_cfa_offset -128
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size _Z26__device_stub__myMatrixAddiPjS_, .Lfunc_end2-_Z26__device_stub__myMatrixAddiPjS_
.cfi_endproc
# -- End function
.globl _Z8rand_genjiPj # -- Begin function _Z8rand_genjiPj
.type _Z8rand_genjiPj,@function
_Z8rand_genjiPj: # @_Z8rand_genjiPj
.cfi_startproc
# %bb.0:
testl %esi, %esi
jle .LBB3_5
# %bb.1: # %.preheader.lr.ph
movq %rdx, %rcx
movl %esi, %r8d
imull %esi, %esi
movl %edi, %edi
leaq (,%r8,4), %r9
movl $2, %edx
xorl %r10d, %r10d
.LBB3_2: # %.lr.ph
# =>This Loop Header: Depth=1
# Child Loop BB3_3 Depth 2
xorl %r11d, %r11d
.LBB3_3: # Parent Loop BB3_2 Depth=1
# => This Inner Loop Header: Depth=2
imull %edx, %edx
addl %edi, %edx
addl %r11d, %edx
movl %edx, %eax
xorl %edx, %edx
divl %esi
movl %edx, (%rcx,%r11,4)
incq %r11
cmpq %r11, %r8
jne .LBB3_3
# %bb.4: # %._crit_edge
# in Loop: Header=BB3_2 Depth=1
incl %r10d
incq %rdi
addq %r9, %rcx
cmpl %r8d, %r10d
jne .LBB3_2
.LBB3_5: # %._crit_edge27
retq
.Lfunc_end3:
.size _Z8rand_genjiPj, .Lfunc_end3-_Z8rand_genjiPj
.cfi_endproc
# -- End function
.globl _Z10rand_gen_tjiPj # -- Begin function _Z10rand_gen_tjiPj
.type _Z10rand_gen_tjiPj,@function
_Z10rand_gen_tjiPj: # @_Z10rand_gen_tjiPj
.cfi_startproc
# %bb.0:
testl %esi, %esi
jle .LBB4_6
# %bb.1: # %.preheader.lr.ph
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movq %rdx, %rcx
movl %esi, %r8d
imull %esi, %esi
leaq (,%r8,4), %r9
movl $2, %edx
xorl %r10d, %r10d
.LBB4_2: # %.lr.ph
# =>This Loop Header: Depth=1
# Child Loop BB4_3 Depth 2
movq %r8, %r11
movl %edi, %ebx
movq %rcx, %r14
.LBB4_3: # Parent Loop BB4_2 Depth=1
# => This Inner Loop Header: Depth=2
imull %edx, %edx
addl %ebx, %edx
movl %edx, %eax
xorl %edx, %edx
divl %esi
movl %edx, (%r14)
addq %r9, %r14
incl %ebx
decq %r11
jne .LBB4_3
# %bb.4: # %._crit_edge
# in Loop: Header=BB4_2 Depth=1
incq %r10
addq $4, %rcx
incl %edi
cmpq %r8, %r10
jne .LBB4_2
# %bb.5:
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r14
.LBB4_6: # %._crit_edge24
retq
.Lfunc_end4:
.size _Z10rand_gen_tjiPj, .Lfunc_end4-_Z10rand_gen_tjiPj
.cfi_endproc
# -- End function
.globl _Z9signatureiPj # -- Begin function _Z9signatureiPj
.type _Z9signatureiPj,@function
_Z9signatureiPj: # @_Z9signatureiPj
.cfi_startproc
# %bb.0:
testl %edi, %edi
je .LBB5_1
# %bb.3: # %.lr.ph.preheader
imull %edi, %edi
incl %edi
xorl %eax, %eax
.LBB5_4: # %.lr.ph
# =>This Inner Loop Header: Depth=1
addl (%rsi), %eax
imull $-1640531535, %eax, %eax # imm = 0x9E3779B1
addq $4, %rsi
decl %edi
cmpl $1, %edi
jg .LBB5_4
# %bb.2: # %._crit_edge
retq
.LBB5_1:
xorl %eax, %eax
retq
.Lfunc_end5:
.size _Z9signatureiPj, .Lfunc_end5-_Z9signatureiPj
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $120, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
leaq 12(%rsp), %rsi
movl $.L.str, %edi
xorl %eax, %eax
callq __isoc23_scanf
xorl %ebx, %ebx
.LBB6_1: # =>This Inner Loop Header: Depth=1
leaq (%rsp,%rbx), %rsi
addq $96, %rsi
movl $.L.str, %edi
xorl %eax, %eax
callq __isoc23_scanf
addq $4, %rbx
cmpq $24, %rbx
jne .LBB6_1
# %bb.2: # %.preheader123
movl 12(%rsp), %ecx
movl %ecx, %esi
imull %ecx, %esi
leaq (,%rcx,4), %rdi
movl $IN, %r8d
xorl %r9d, %r9d
.LBB6_3: # =>This Loop Header: Depth=1
# Child Loop BB6_11 Depth 2
# Child Loop BB6_12 Depth 3
# Child Loop BB6_6 Depth 2
# Child Loop BB6_7 Depth 3
movl 96(%rsp,%r9,4), %r10d
testb $5, %r9b
je .LBB6_4
# %bb.9: # in Loop: Header=BB6_3 Depth=1
testl %ecx, %ecx
jle .LBB6_14
# %bb.10: # %.lr.ph.i83.preheader
# in Loop: Header=BB6_3 Depth=1
movl $2, %edx
movq %r8, %r11
xorl %ebx, %ebx
.LBB6_11: # %.lr.ph.i83
# Parent Loop BB6_3 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB6_12 Depth 3
movl %r10d, %ebp
movq %r11, %r14
movq %rcx, %r15
.LBB6_12: # Parent Loop BB6_3 Depth=1
# Parent Loop BB6_11 Depth=2
# => This Inner Loop Header: Depth=3
imull %edx, %edx
addl %ebp, %edx
movl %edx, %eax
xorl %edx, %edx
divl %esi
movl %edx, (%r14)
addq %rdi, %r14
incl %ebp
decq %r15
jne .LBB6_12
# %bb.13: # %._crit_edge.i87
# in Loop: Header=BB6_11 Depth=2
incq %rbx
addq $4, %r11
incl %r10d
cmpq %rcx, %rbx
jne .LBB6_11
jmp .LBB6_14
.LBB6_4: # in Loop: Header=BB6_3 Depth=1
testl %ecx, %ecx
jle .LBB6_14
# %bb.5: # %.preheader.lr.ph.i
# in Loop: Header=BB6_3 Depth=1
movl $2, %edx
xorl %r11d, %r11d
movq %r8, %rbx
.LBB6_6: # %.lr.ph.i
# Parent Loop BB6_3 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB6_7 Depth 3
xorl %r14d, %r14d
.LBB6_7: # Parent Loop BB6_3 Depth=1
# Parent Loop BB6_6 Depth=2
# => This Inner Loop Header: Depth=3
imull %edx, %edx
addl %r10d, %edx
addl %r14d, %edx
movl %edx, %eax
xorl %edx, %edx
divl %esi
movl %edx, (%rbx,%r14,4)
incq %r14
cmpq %r14, %rcx
jne .LBB6_7
# %bb.8: # %._crit_edge.i
# in Loop: Header=BB6_6 Depth=2
incl %r11d
addq %rdi, %rbx
incq %r10
cmpl %ecx, %r11d
jne .LBB6_6
.LBB6_14: # %_Z8rand_genjiPj.exit
# in Loop: Header=BB6_3 Depth=1
incq %r9
addq $4194304, %r8 # imm = 0x400000
cmpq $6, %r9
jne .LBB6_3
# %bb.15:
movl $IN, %ebx
xorl %r15d, %r15d
.LBB6_16: # =>This Inner Loop Header: Depth=1
leaq (%rsp,%r15), %r14
addq $48, %r14
movslq 12(%rsp), %rsi
imulq %rsi, %rsi
shlq $2, %rsi
movq %r14, %rdi
callq hipMalloc
movq (%r14), %rdi
movslq 12(%rsp), %rdx
imulq %rdx, %rdx
shlq $2, %rdx
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
addq $4194304, %rbx # imm = 0x400000
addq $8, %r15
cmpq $48, %r15
jne .LBB6_16
# %bb.17: # %.preheader121.preheader
xorl %ebx, %ebx
.LBB6_18: # %.preheader121
# =>This Inner Loop Header: Depth=1
leaq (%rsp,%rbx), %rdi
addq $16, %rdi
movslq 12(%rsp), %rsi
imulq %rsi, %rsi
shlq $2, %rsi
callq hipMalloc
addq $8, %rbx
cmpq $32, %rbx
jne .LBB6_18
# %bb.19:
movl 12(%rsp), %eax
imull %eax, %eax
leal -1(%rax), %ecx
addl $30, %eax
testl %ecx, %ecx
cmovnsl %ecx, %eax
movabsq $4294967328, %rbx # imm = 0x100000020
sarl $5, %eax
incl %eax
leaq (%rax,%rbx), %r14
addq $-32, %r14
movq %r14, %rdi
movl $1, %esi
movq %rbx, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB6_21
# %bb.20:
movl 12(%rsp), %edi
movq 16(%rsp), %rsi
movq 48(%rsp), %rdx
movq 56(%rsp), %rcx
callq _Z26__device_stub__myMatrixMuliPjS_S_
.LBB6_21:
movq %r14, %rdi
movl $1, %esi
movq %rbx, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB6_23
# %bb.22:
movl 12(%rsp), %edi
movq 24(%rsp), %rsi
movq 64(%rsp), %rdx
movq 72(%rsp), %rcx
callq _Z26__device_stub__myMatrixMuliPjS_S_
.LBB6_23:
movq %r14, %rdi
movl $1, %esi
movq %rbx, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB6_25
# %bb.24:
movl 12(%rsp), %edi
movq 16(%rsp), %rdx
movq 40(%rsp), %rsi
movq 80(%rsp), %rcx
callq _Z26__device_stub__myMatrixMuliPjS_S_
.LBB6_25:
movq %r14, %rdi
movl $1, %esi
movq %rbx, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB6_27
# %bb.26:
movl 12(%rsp), %edi
movq 24(%rsp), %rdx
movq 48(%rsp), %rsi
movq 88(%rsp), %rcx
callq _Z26__device_stub__myMatrixMuliPjS_S_
.LBB6_27:
movq %r14, %rdi
movl $1, %esi
movq %rbx, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB6_29
# %bb.28:
movl 12(%rsp), %edi
movq 16(%rsp), %rsi
movq 24(%rsp), %rdx
callq _Z26__device_stub__myMatrixAddiPjS_
.LBB6_29:
xorl %r15d, %r15d
movq %r14, %rdi
movl $1, %esi
movq %rbx, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB6_31
# %bb.30:
movl 12(%rsp), %edi
movq 40(%rsp), %rsi
movq 48(%rsp), %rdx
callq _Z26__device_stub__myMatrixAddiPjS_
.LBB6_31:
movq 16(%rsp), %rsi
movslq 12(%rsp), %rdx
imulq %rdx, %rdx
shlq $2, %rdx
movl $IN, %ebx
movl $IN, %edi
movl $2, %ecx
callq hipMemcpy
movq 40(%rsp), %rsi
movslq 12(%rsp), %rdx
imulq %rdx, %rdx
shlq $2, %rdx
movl $IN+4194304, %edi
movl $2, %ecx
callq hipMemcpy
movl 12(%rsp), %eax
testl %eax, %eax
je .LBB6_34
# %bb.32: # %.lr.ph.preheader.i
imull %eax, %eax
incl %eax
xorl %r15d, %r15d
.LBB6_33: # %.lr.ph.i88
# =>This Inner Loop Header: Depth=1
addl (%rbx), %r15d
imull $-1640531535, %r15d, %r15d # imm = 0x9E3779B1
addq $4, %rbx
decl %eax
cmpl $1, %eax
jg .LBB6_33
.LBB6_34: # %_Z9signatureiPj.exit
xorl %ebx, %ebx
movl $.L.str.1, %edi
movl %r15d, %esi
xorl %eax, %eax
callq printf
movl 12(%rsp), %eax
testl %eax, %eax
je .LBB6_37
# %bb.35: # %.lr.ph.preheader.i91
imull %eax, %eax
incl %eax
xorl %ebx, %ebx
movl $IN+4194304, %ecx
.LBB6_36: # %.lr.ph.i92
# =>This Inner Loop Header: Depth=1
addl (%rcx), %ebx
imull $-1640531535, %ebx, %ebx # imm = 0x9E3779B1
addq $4, %rcx
decl %eax
cmpl $1, %eax
jg .LBB6_36
.LBB6_37: # %_Z9signatureiPj.exit98
xorl %r14d, %r14d
movl $.L.str.1, %edi
movl %ebx, %esi
xorl %eax, %eax
callq printf
.LBB6_38: # =>This Inner Loop Header: Depth=1
movq 48(%rsp,%r14,8), %rdi
callq hipFree
incq %r14
cmpq $6, %r14
jne .LBB6_38
# %bb.39: # %.preheader.preheader
xorl %ebx, %ebx
.LBB6_40: # %.preheader
# =>This Inner Loop Header: Depth=1
movq 16(%rsp,%rbx,8), %rdi
callq hipFree
incq %rbx
cmpq $4, %rbx
jne .LBB6_40
# %bb.41:
xorl %eax, %eax
addq $120, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end6:
.size main, .Lfunc_end6-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
movq __hip_gpubin_handle(%rip), %rbx
testq %rbx, %rbx
jne .LBB7_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, %rbx
movq %rax, __hip_gpubin_handle(%rip)
.LBB7_2:
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11myMatrixMuliPjS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11myMatrixAddiPjS_, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end7:
.size __hip_module_ctor, .Lfunc_end7-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB8_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB8_2:
retq
.Lfunc_end8:
.size __hip_module_dtor, .Lfunc_end8-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z11myMatrixMuliPjS_S_,@object # @_Z11myMatrixMuliPjS_S_
.section .rodata,"a",@progbits
.globl _Z11myMatrixMuliPjS_S_
.p2align 3, 0x0
_Z11myMatrixMuliPjS_S_:
.quad _Z26__device_stub__myMatrixMuliPjS_S_
.size _Z11myMatrixMuliPjS_S_, 8
.type _Z11myMatrixAddiPjS_,@object # @_Z11myMatrixAddiPjS_
.globl _Z11myMatrixAddiPjS_
.p2align 3, 0x0
_Z11myMatrixAddiPjS_:
.quad _Z26__device_stub__myMatrixAddiPjS_
.size _Z11myMatrixAddiPjS_, 8
.type IN,@object # @IN
.bss
.globl IN
.p2align 4, 0x0
IN:
.zero 25165824
.size IN, 25165824
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%d"
.size .L.str, 3
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "%u\n"
.size .L.str.1, 4
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z11myMatrixMuliPjS_S_"
.size .L__unnamed_1, 23
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z11myMatrixAddiPjS_"
.size .L__unnamed_2, 21
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z26__device_stub__myMatrixMuliPjS_S_
.addrsig_sym _Z26__device_stub__myMatrixAddiPjS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z11myMatrixMuliPjS_S_
.addrsig_sym _Z11myMatrixAddiPjS_
.addrsig_sym IN
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
```
| 7,156 | 9,138 |
30 |
Convert the following CUDA device assembly code to AMD device assembly:
```cudaasm
code for sm_80
Function : _Z3sumPfS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
MOV R1, c[0x0][0x28] ;
S2R R8, SR_CTAID.X ;
HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ;
ULDC.64 UR6, c[0x0][0x118] ;
S2R R10, SR_TID.X ;
IMAD R6, R8, c[0x0][0x0], R10 ;
IMAD.WIDE R4, R6, R7, c[0x0][0x168] ;
IMAD.WIDE R2, R6.reuse, R7.reuse, c[0x0][0x160] ;
LDG.E R4, [R4.64] ;
LDG.E R3, [R2.64] ;
IMAD.WIDE R6, R6, R7, c[0x0][0x170] ;
ULDC UR4, c[0x0][0x0] ;
ISETP.NE.AND P0, PT, R10, RZ, PT ;
USHF.R.U32.HI UR4, URZ, 0x1, UR4 ;
ISETP.NE.AND P1, PT, RZ, UR4, PT ;
FMUL R9, R4, R3 ;
STG.E [R6.64], R9 ;
STS [R10.X4], R9 ;
@!P1 BRA 0x220 ;
BSSY B0, 0x220 ;
SHF.L.U32 R0, R10, 0x2, RZ ;
IMAD.U32 R3, RZ, RZ, UR4 ;
ISETP.GE.U32.AND P1, PT, R10, R3, PT ;
@!P1 LEA R2, R3, R0, 0x2 ;
@!P1 LDS R4, [R10.X4] ;
SHF.R.U32.HI R3, RZ, 0x1, R3 ;
@!P1 WARPSYNC 0xffffffff ;
@!P1 LDS R5, [R2] ;
@!P1 FADD R4, R4, R5 ;
@!P1 STS [R10.X4], R4 ;
@!P1 BAR.SYNC.DEFER_BLOCKING 0x0 ;
ISETP.NE.AND P1, PT, R3, RZ, PT ;
@P1 BRA 0x160 ;
BSYNC B0 ;
@P0 EXIT ;
LDS R5, [RZ] ;
IMAD.MOV.U32 R3, RZ, RZ, 0x4 ;
IMAD.WIDE.U32 R2, R8, R3, c[0x0][0x170] ;
STG.E [R2.64], R5 ;
EXIT ;
BRA 0x280;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
```
|
```amdasm
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3sumPfS_S_ ; -- Begin function _Z3sumPfS_S_
.globl _Z3sumPfS_S_
.p2align 8
.type _Z3sumPfS_S_,@function
_Z3sumPfS_S_: ; @_Z3sumPfS_S_
; %bb.0:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x24
s_load_b128 s[4:7], s[0:1], 0x0
s_mov_b32 s2, s15
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s2, s3, v[0:1]
s_cmp_lt_u32 s3, 2
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[1:2], 2, v[1:2]
v_add_co_u32 v3, vcc_lo, s4, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v2, vcc_lo
v_add_co_u32 v5, vcc_lo, s6, v1
v_add_co_ci_u32_e32 v6, vcc_lo, s7, v2, vcc_lo
global_load_b32 v7, v[3:4], off
global_load_b32 v5, v[5:6], off
v_add_co_u32 v3, vcc_lo, s0, v1
v_add_co_ci_u32_e32 v4, vcc_lo, s1, v2, vcc_lo
s_waitcnt vmcnt(0)
v_dual_mul_f32 v2, v7, v5 :: v_dual_lshlrev_b32 v1, 2, v0
global_store_b32 v[3:4], v2, off
ds_store_b32 v1, v2
s_cbranch_scc1 .LBB0_4
.LBB0_1: ; %.lr.ph
; =>This Inner Loop Header: Depth=1
s_lshr_b32 s4, s3, 1
s_mov_b32 s5, exec_lo
v_cmpx_gt_u32_e64 s4, v0
s_cbranch_execz .LBB0_3
; %bb.2: ; in Loop: Header=BB0_1 Depth=1
v_lshl_add_u32 v2, s4, 2, v1
ds_load_b32 v2, v2
ds_load_b32 v3, v1
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v2, v2, v3
ds_store_b32 v1, v2
s_waitcnt lgkmcnt(0)
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
.LBB0_3: ; in Loop: Header=BB0_1 Depth=1
s_or_b32 exec_lo, exec_lo, s5
s_cmp_lt_u32 s3, 4
s_mov_b32 s3, s4
s_cbranch_scc0 .LBB0_1
.LBB0_4: ; %._crit_edge
s_mov_b32 s3, 0
s_mov_b32 s4, exec_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB0_6
; %bb.5:
ds_load_b32 v0, v1
s_lshl_b64 s[2:3], s[2:3], 2
v_mov_b32_e32 v1, 0
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
s_waitcnt lgkmcnt(0)
global_store_b32 v1, v0, s[0:1]
.LBB0_6:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3sumPfS_S_
.amdhsa_group_segment_fixed_size 64
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3sumPfS_S_, .Lfunc_end0-_Z3sumPfS_S_
; -- End function
.section .AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 324
; NumSgprs: 18
; NumVgprs: 8
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 64 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 8
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object ; @__hip_cuid_
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0 ; 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 64
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3sumPfS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z3sumPfS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
```
| 784 | 2,977 |
31 |
Convert the following CUDA host assembly code to AMD host assembly:
```cudaasm
.file "tmpxft_0016bda3_00000000-6_CUDA_homework2.cudafe1.cpp"
.text
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z26__device_stub__Z3sumPfS_S_PfS_S_
.type _Z26__device_stub__Z3sumPfS_S_PfS_S_, @function
_Z26__device_stub__Z3sumPfS_S_PfS_S_:
.LFB2082:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z3sumPfS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z26__device_stub__Z3sumPfS_S_PfS_S_, .-_Z26__device_stub__Z3sumPfS_S_PfS_S_
.globl _Z3sumPfS_S_
.type _Z3sumPfS_S_, @function
_Z3sumPfS_S_:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z3sumPfS_S_PfS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z3sumPfS_S_, .-_Z3sumPfS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "GPU dotprod : %f\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $1344, %rsp
.cfi_def_cfa_offset 1360
movq %fs:40, %rax
movq %rax, 1336(%rsp)
xorl %eax, %eax
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $160, %ecx
.L12:
leal (%rax,%rax), %edx
pxor %xmm0, %xmm0
cvtsi2ssl %edx, %xmm0
movss %xmm0, 48(%rsp,%rax,4)
movl %ecx, %edx
subl %eax, %edx
pxor %xmm0, %xmm0
cvtsi2ssl %edx, %xmm0
movss %xmm0, 688(%rsp,%rax,4)
addq $1, %rax
cmpq $160, %rax
jne .L12
movq %rsp, %rdi
movl $640, %esi
call cudaMalloc@PLT
leaq 8(%rsp), %rdi
movl $640, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $40, %esi
call cudaMalloc@PLT
leaq 48(%rsp), %rsi
movl $1, %ecx
movl $640, %edx
movq (%rsp), %rdi
call cudaMemcpy@PLT
leaq 688(%rsp), %rsi
movl $1, %ecx
movl $640, %edx
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $10, 36(%rsp)
movl $16, 24(%rsp)
movl 32(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 24(%rsp), %rdx
movq 36(%rsp), %rdi
movl 44(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L19
.L13:
movl $40, %edi
call malloc@PLT
movq %rax, %rbx
movl $2, %ecx
movl $40, %edx
movq 16(%rsp), %rsi
movq %rax, %rdi
call cudaMemcpy@PLT
movq %rbx, %rax
leaq 40(%rbx), %rdx
pxor %xmm0, %xmm0
.L14:
addss (%rax), %xmm0
addq $4, %rax
cmpq %rdx, %rax
jne .L14
cvtss2sd %xmm0, %xmm0
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq (%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq %rbx, %rdi
call free@PLT
movq 1336(%rsp), %rax
subq %fs:40, %rax
jne .L20
movl $0, %eax
addq $1344, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
movq 16(%rsp), %rdx
movq 8(%rsp), %rsi
movq (%rsp), %rdi
call _Z26__device_stub__Z3sumPfS_S_PfS_S_
jmp .L13
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC2:
.string "_Z3sumPfS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z3sumPfS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
```
|
```amdasm
.text
.file "CUDA_homework2.hip"
.globl _Z18__device_stub__sumPfS_S_ # -- Begin function _Z18__device_stub__sumPfS_S_
.type _Z18__device_stub__sumPfS_S_,@function
_Z18__device_stub__sumPfS_S_: # @_Z18__device_stub__sumPfS_S_
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $112, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 40(%rsp), %rax
movq %rdi, (%rax)
leaq 32(%rsp), %rcx
movq %rsi, (%rcx)
leaq 24(%rsp), %rsi
movq %rdx, (%rsi)
leaq 80(%rsp), %rbx
movq %rax, (%rbx)
movq %rcx, 8(%rbx)
movq %rsi, 16(%rbx)
leaq 64(%rsp), %r14
leaq 48(%rsp), %r15
leaq 16(%rsp), %r12
leaq 8(%rsp), %r13
movq %r14, %rdi
movq %r15, %rsi
movq %r12, %rdx
movq %r13, %rcx
callq __hipPopCallConfiguration
movq (%r14), %rsi
movl 8(%r14), %edx
movq (%r15), %rcx
movl 8(%r15), %r8d
movl $_Z3sumPfS_S_, %edi
movq %rbx, %r9
pushq (%r13)
.cfi_adjust_cfa_offset 8
pushq (%r12)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $128, %rsp
.cfi_adjust_cfa_offset -128
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z18__device_stub__sumPfS_S_, .Lfunc_end0-_Z18__device_stub__sumPfS_S_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $1320, %rsp # imm = 0x528
.cfi_def_cfa_offset 1344
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movl $160, %eax
xorl %ecx, %ecx
.LBB1_1: # =>This Inner Loop Header: Depth=1
xorps %xmm0, %xmm0
cvtsi2ss %ecx, %xmm0
xorps %xmm1, %xmm1
cvtsi2ss %eax, %xmm1
movss %xmm0, 672(%rsp,%rcx,2)
movss %xmm1, 32(%rsp,%rcx,2)
addq $2, %rcx
decq %rax
jne .LBB1_1
# %bb.2:
leaq 24(%rsp), %rbx
movl $640, %esi # imm = 0x280
movq %rbx, %rdi
callq hipMalloc
leaq 16(%rsp), %r14
movl $640, %esi # imm = 0x280
movq %r14, %rdi
callq hipMalloc
leaq 8(%rsp), %rdi
movl $40, %esi
callq hipMalloc
movq (%rbx), %rdi
leaq 672(%rsp), %rsi
movl $640, %edx # imm = 0x280
movl $1, %ecx
callq hipMemcpy
movq (%r14), %rdi
leaq 32(%rsp), %rsi
movl $640, %edx # imm = 0x280
movl $1, %ecx
callq hipMemcpy
movabsq $4294967306, %rdi # imm = 0x10000000A
leaq 6(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq 24(%rsp), %rdi
movq 16(%rsp), %rsi
movq 8(%rsp), %rdx
callq _Z18__device_stub__sumPfS_S_
.LBB1_4:
movl $40, %edi
callq malloc
movq %rax, %rbx
movq 8(%rsp), %rsi
movl $40, %edx
movq %rax, %rdi
movl $2, %ecx
callq hipMemcpy
xorps %xmm0, %xmm0
xorl %eax, %eax
.LBB1_5: # =>This Inner Loop Header: Depth=1
addss (%rbx,%rax,4), %xmm0
incq %rax
cmpq $10, %rax
jne .LBB1_5
# %bb.6:
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq %rbx, %rdi
callq free
xorl %eax, %eax
addq $1320, %rsp # imm = 0x528
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, %rdi
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3sumPfS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3sumPfS_S_,@object # @_Z3sumPfS_S_
.section .rodata,"a",@progbits
.globl _Z3sumPfS_S_
.p2align 3, 0x0
_Z3sumPfS_S_:
.quad _Z18__device_stub__sumPfS_S_
.size _Z3sumPfS_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "GPU dotprod : %f\n"
.size .L.str, 18
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z3sumPfS_S_"
.size .L__unnamed_1, 13
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__sumPfS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3sumPfS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
```
| 2,973 | 3,153 |
32 |
Convert the following CUDA device assembly code to AMD device assembly:
```cudaasm
code for sm_80
```
|
```amdasm
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object ; @__hip_cuid_
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0 ; 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
```
| 24 | 306 |
33 |
Convert the following CUDA host assembly code to AMD host assembly:
```cudaasm
.file "tmpxft_0011d53c_00000000-6_pipelined_merge_sort.cudafe1.cpp"
.text
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
```
|
```amdasm
.text
.file "pipelined_merge_sort.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
```
| 750 | 187 |
36 |
Convert the following CUDA device assembly code to AMD device assembly:
```cudaasm
code for sm_80
Function : _Z6VecAddPfS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
MOV R1, c[0x0][0x28] ;
S2R R6, SR_TID.X ;
HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ;
ULDC.64 UR4, c[0x0][0x118] ;
IMAD.WIDE R2, R6, R7, c[0x0][0x160] ;
IMAD.WIDE R4, R6.reuse, R7.reuse, c[0x0][0x168] ;
LDG.E R2, [R2.64] ;
LDG.E R5, [R4.64] ;
IMAD.WIDE R6, R6, R7, c[0x0][0x170] ;
FADD R9, R2, R5 ;
STG.E [R6.64], R9 ;
EXIT ;
BRA 0xc0;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
```
|
```amdasm
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6VecAddPfS_S_ ; -- Begin function _Z6VecAddPfS_S_
.globl _Z6VecAddPfS_S_
.p2align 8
.type _Z6VecAddPfS_S_,@function
_Z6VecAddPfS_S_: ; @_Z6VecAddPfS_S_
; %bb.0:
s_load_b128 s[4:7], s[0:1], 0x0
v_lshlrev_b32_e32 v0, 2, v0
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_clause 0x1
global_load_b32 v1, v0, s[4:5]
global_load_b32 v2, v0, s[6:7]
s_waitcnt vmcnt(0)
v_add_f32_e32 v1, v1, v2
global_store_b32 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6VecAddPfS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 8
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6VecAddPfS_S_, .Lfunc_end0-_Z6VecAddPfS_S_
; -- End function
.section .AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 72
; NumSgprs: 8
; NumVgprs: 3
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 0
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 8
; NumVGPRsForWavesPerEU: 3
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object ; @__hip_cuid_
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0 ; 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6VecAddPfS_S_
.private_segment_fixed_size: 0
.sgpr_count: 8
.sgpr_spill_count: 0
.symbol: _Z6VecAddPfS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
```
| 324 | 1,784 |
37 |
Convert the following CUDA host assembly code to AMD host assembly:
```cudaasm
.file "tmpxft_000a6ee2_00000000-6_vec_add.cudafe1.cpp"
.text
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z29__device_stub__Z6VecAddPfS_S_PfS_S_
.type _Z29__device_stub__Z6VecAddPfS_S_PfS_S_, @function
_Z29__device_stub__Z6VecAddPfS_S_PfS_S_:
.LFB2082:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z6VecAddPfS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z29__device_stub__Z6VecAddPfS_S_PfS_S_, .-_Z29__device_stub__Z6VecAddPfS_S_PfS_S_
.globl _Z6VecAddPfS_S_
.type _Z6VecAddPfS_S_, @function
_Z6VecAddPfS_S_:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z6VecAddPfS_S_PfS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z6VecAddPfS_S_, .-_Z6VecAddPfS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%0.f "
.LC1:
.string "\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $64, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl $40, %edi
call malloc@PLT
movq %rax, %r12
movl $40, %edi
call malloc@PLT
movq %rax, %rbp
movl $0, %eax
.L12:
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movss %xmm0, (%r12,%rax,4)
movss %xmm0, 0(%rbp,%rax,4)
addq $1, %rax
cmpq $10, %rax
jne .L12
leaq 8(%rsp), %rdi
movl $40, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $40, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $40, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $40, %edx
movq %r12, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $40, %edx
movq %rbp, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $10, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L23
.L13:
movl $40, %edi
call malloc@PLT
movq %rax, %r13
movl $2, %ecx
movl $40, %edx
movq 24(%rsp), %rsi
movq %rax, %rdi
call cudaMemcpy@PLT
movq %r12, %rbx
addq $40, %r12
leaq .LC0(%rip), %r14
.L14:
pxor %xmm0, %xmm0
cvtss2sd (%rbx), %xmm0
movq %r14, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %r12, %rbx
jne .L14
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %rbp, %rbx
addq $40, %rbp
leaq .LC0(%rip), %r12
.L15:
pxor %xmm0, %xmm0
cvtss2sd (%rbx), %xmm0
movq %r12, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %rbp, %rbx
jne .L15
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %r13, %rbx
addq $40, %r13
leaq .LC0(%rip), %rbp
.L16:
pxor %xmm0, %xmm0
cvtss2sd (%rbx), %xmm0
movq %rbp, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %r13, %rbx
jne .L16
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L24
movl $0, %eax
addq $64, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z29__device_stub__Z6VecAddPfS_S_PfS_S_
jmp .L13
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC2:
.string "_Z6VecAddPfS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z6VecAddPfS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
```
|
```amdasm
.text
.file "vec_add.hip"
.globl _Z21__device_stub__VecAddPfS_S_ # -- Begin function _Z21__device_stub__VecAddPfS_S_
.type _Z21__device_stub__VecAddPfS_S_,@function
_Z21__device_stub__VecAddPfS_S_: # @_Z21__device_stub__VecAddPfS_S_
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $112, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 40(%rsp), %rax
movq %rdi, (%rax)
leaq 32(%rsp), %rcx
movq %rsi, (%rcx)
leaq 24(%rsp), %rsi
movq %rdx, (%rsi)
leaq 80(%rsp), %rbx
movq %rax, (%rbx)
movq %rcx, 8(%rbx)
movq %rsi, 16(%rbx)
leaq 64(%rsp), %r14
leaq 48(%rsp), %r15
leaq 16(%rsp), %r12
leaq 8(%rsp), %r13
movq %r14, %rdi
movq %r15, %rsi
movq %r12, %rdx
movq %r13, %rcx
callq __hipPopCallConfiguration
movq (%r14), %rsi
movl 8(%r14), %edx
movq (%r15), %rcx
movl 8(%r15), %r8d
movl $_Z6VecAddPfS_S_, %edi
movq %rbx, %r9
pushq (%r13)
.cfi_adjust_cfa_offset 8
pushq (%r12)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $128, %rsp
.cfi_adjust_cfa_offset -128
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z21__device_stub__VecAddPfS_S_, .Lfunc_end0-_Z21__device_stub__VecAddPfS_S_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $24, %rsp
.cfi_def_cfa_offset 64
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $40, %edi
callq malloc
movq %rax, %r14
movl $40, %edi
callq malloc
movq %rax, %rbx
xorl %eax, %eax
.LBB1_1: # =>This Inner Loop Header: Depth=1
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movss %xmm0, (%r14,%rax,4)
movss %xmm0, (%rbx,%rax,4)
incq %rax
cmpq $10, %rax
jne .LBB1_1
# %bb.2:
leaq 16(%rsp), %r15
movl $40, %esi
movq %r15, %rdi
callq hipMalloc
leaq 8(%rsp), %r12
movl $40, %esi
movq %r12, %rdi
callq hipMalloc
movq %rsp, %rdi
movl $40, %esi
callq hipMalloc
movq (%r15), %rdi
movl $40, %edx
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movq (%r12), %rdi
movl $40, %edx
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 9(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq 16(%rsp), %rdi
movq 8(%rsp), %rsi
movq (%rsp), %rdx
callq _Z21__device_stub__VecAddPfS_S_
.LBB1_4:
movl $40, %edi
callq malloc
movq %rax, %r15
movq (%rsp), %rsi
movl $40, %edx
movq %rax, %rdi
movl $2, %ecx
callq hipMemcpy
xorl %r12d, %r12d
.LBB1_5: # =>This Inner Loop Header: Depth=1
xorps %xmm0, %xmm0
cvtss2sd (%r14,%r12,4), %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
incq %r12
cmpq $10, %r12
jne .LBB1_5
# %bb.6:
movl $10, %edi
callq putchar@PLT
xorl %r14d, %r14d
.LBB1_7: # =>This Inner Loop Header: Depth=1
xorps %xmm0, %xmm0
cvtss2sd (%rbx,%r14,4), %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
incq %r14
cmpq $10, %r14
jne .LBB1_7
# %bb.8:
movl $10, %edi
callq putchar@PLT
xorl %ebx, %ebx
.LBB1_9: # =>This Inner Loop Header: Depth=1
xorps %xmm0, %xmm0
cvtss2sd (%r15,%rbx,4), %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
incq %rbx
cmpq $10, %rbx
jne .LBB1_9
# %bb.10:
movl $10, %edi
callq putchar@PLT
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $24, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, %rdi
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6VecAddPfS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6VecAddPfS_S_,@object # @_Z6VecAddPfS_S_
.section .rodata,"a",@progbits
.globl _Z6VecAddPfS_S_
.p2align 3, 0x0
_Z6VecAddPfS_S_:
.quad _Z21__device_stub__VecAddPfS_S_
.size _Z6VecAddPfS_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%0.f "
.size .L.str, 6
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z6VecAddPfS_S_"
.size .L__unnamed_1, 16
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__VecAddPfS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6VecAddPfS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
```
| 3,530 | 3,483 |
38 |
Convert the following CUDA device assembly code to AMD device assembly:
```cudaasm
code for sm_80
Function : _ZN8mmdeploy9operation4cuda9transposeIfEEvPKT_iiiiPS3_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
MOV R1, c[0x0][0x28] ;
S2R R19, SR_CTAID.Y ;
S2R R0, SR_TID.Y ;
S2R R3, SR_CTAID.X ;
S2R R2, SR_TID.X ;
IMAD R19, R19, c[0x0][0x4], R0 ;
IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x170] ;
ISETP.GE.U32.AND P0, PT, R19, c[0x0][0x168], PT ;
IMAD R18, R3, c[0x0][0x0], R2 ;
ISETP.GE.U32.OR P0, PT, R18, c[0x0][0x16c], P0 ;
ISETP.LT.OR P0, PT, R0, 0x1, P0 ;
@P0 EXIT ;
IADD3 R4, R0.reuse, -0x1, RZ ;
ULDC.64 UR4, c[0x0][0x118] ;
LOP3.LUT R0, R0, 0x3, RZ, 0xc0, !PT ;
HFMA2.MMA R14, -RZ, RZ, 0, 0 ;
ISETP.GE.U32.AND P1, PT, R4, 0x3, PT ;
IMAD R20, R18, c[0x0][0x170], RZ ;
ISETP.NE.AND P0, PT, R0, RZ, PT ;
@!P1 BRA 0x3c0 ;
IADD3 R2, R2, c[0x0][0x180], RZ ;
IMAD R22, R19.reuse, c[0x0][0x174], R20 ;
IADD3 R15, R0, -c[0x0][0x170], RZ ;
IMAD R17, R19, c[0x0][0x16c], R18 ;
MOV R14, RZ ;
IMAD R2, R3, c[0x0][0x0], R2 ;
IADD3 R22, R22, 0x3, RZ ;
IMAD.MOV.U32 R16, RZ, RZ, c[0x0][0x180] ;
IMAD R25, R19, c[0x0][0x16c], R2 ;
IMAD R23, R16, 0x2, R17 ;
IMAD R21, R16, 0x3, R17 ;
IADD3 R11, R22, -0x3, RZ ;
MOV R24, 0x4 ;
IMAD.WIDE.U32 R10, R11, R24, c[0x0][0x160] ;
LDG.E R27, [R10.64] ;
IADD3 R5, R22, -0x2, RZ ;
IMAD.WIDE.U32 R2, R17, R24, c[0x0][0x178] ;
IMAD.WIDE.U32 R4, R5, R24.reuse, c[0x0][0x160] ;
IADD3 R9, R22, -0x1, RZ ;
STG.E [R2.64], R27 ;
LDG.E R5, [R4.64] ;
IMAD.WIDE.U32 R6, R25, R24, c[0x0][0x178] ;
IMAD.WIDE.U32 R8, R9, R24.reuse, c[0x0][0x160] ;
STG.E [R6.64], R5 ;
LDG.E R9, [R8.64] ;
IMAD.WIDE.U32 R10, R23, R24, c[0x0][0x178] ;
IMAD.WIDE.U32 R12, R22, R24, c[0x0][0x160] ;
IADD3 R14, R14, 0x4, RZ ;
IMAD.IADD R4, R15, 0x1, R14 ;
STG.E [R10.64], R9 ;
LDG.E R13, [R12.64] ;
ISETP.NE.AND P1, PT, R4, RZ, PT ;
IMAD.WIDE.U32 R2, R21, R24, c[0x0][0x178] ;
LEA R25, R16.reuse, R25, 0x2 ;
LEA R17, R16.reuse, R17, 0x2 ;
IMAD R23, R16, 0x4, R23 ;
IADD3 R22, R22, 0x4, RZ ;
IMAD R21, R16, 0x4, R21 ;
STG.E [R2.64], R13 ;
@P1 BRA 0x1f0 ;
@!P0 EXIT ;
IMAD R3, R19, c[0x0][0x174], R14 ;
IMAD R18, R14, c[0x0][0x180], R18 ;
IADD3 R20, R20, R3, RZ ;
IMAD R18, R19, c[0x0][0x16c], R18 ;
HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ;
IMAD.WIDE.U32 R2, R20, R5, c[0x0][0x160] ;
LDG.E R3, [R2.64] ;
IADD3 R0, R0, -0x1, RZ ;
IMAD.WIDE.U32 R4, R18, R5, c[0x0][0x178] ;
IADD3 R20, R20, 0x1, RZ ;
ISETP.NE.AND P0, PT, R0, RZ, PT ;
IADD3 R18, R18, c[0x0][0x180], RZ ;
STG.E [R4.64], R3 ;
@P0 BRA 0x410 ;
EXIT ;
BRA 0x4c0;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
Function : _ZN8mmdeploy9operation4cuda9transposeIhEEvPKT_iiiiPS3_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ;
S2R R3, SR_CTAID.Y ;
S2R R0, SR_TID.Y ;
S2R R14, SR_CTAID.X ;
S2R R7, SR_TID.X ;
IMAD R3, R3, c[0x0][0x4], R0 ;
IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x170] ;
ISETP.GE.U32.AND P0, PT, R3, c[0x0][0x168], PT ;
IMAD R4, R14, c[0x0][0x0], R7 ;
ISETP.GE.U32.OR P0, PT, R4, c[0x0][0x16c], P0 ;
ISETP.LT.OR P0, PT, R0, 0x1, P0 ;
@P0 EXIT ;
IADD3 R2, R0.reuse, -0x1, RZ ;
ULDC.64 UR4, c[0x0][0x118] ;
LOP3.LUT R0, R0, 0x3, RZ, 0xc0, !PT ;
IMAD R6, R4, c[0x0][0x170], RZ ;
ISETP.GE.U32.AND P1, PT, R2, 0x3, PT ;
IMAD.MOV.U32 R5, RZ, RZ, RZ ;
ISETP.NE.AND P0, PT, R0, RZ, PT ;
@!P1 BRA 0x430 ;
IADD3 R5, R7, c[0x0][0x180], RZ ;
IMAD R9, R3.reuse, c[0x0][0x174], R6 ;
IADD3 R8, R0, -c[0x0][0x170], RZ ;
IMAD R2, R3, c[0x0][0x16c], R4 ;
IMAD R14, R14, c[0x0][0x0], R5 ;
IADD3 R9, R9, 0x3, RZ ;
IMAD.MOV.U32 R7, RZ, RZ, c[0x0][0x180] ;
IMAD.MOV.U32 R5, RZ, RZ, RZ ;
IMAD R10, R7, 0x2, R2 ;
IMAD R12, R7, 0x3, R2 ;
IMAD R14, R3, c[0x0][0x16c], R14 ;
IADD3 R24, R9, -0x3, RZ ;
IADD3 R24, P1, R24, c[0x0][0x160], RZ ;
IMAD.X R25, RZ, RZ, c[0x0][0x164], P1 ;
LDG.E.U8 R11, [R24.64] ;
IADD3 R18, R9, -0x2, RZ ;
IADD3 R16, P1, R2, c[0x0][0x178], RZ ;
IADD3 R18, P2, R18, c[0x0][0x160], RZ ;
IADD3.X R17, RZ, c[0x0][0x17c], RZ, P1, !PT ;
IMAD.X R19, RZ, RZ, c[0x0][0x164], P2 ;
IADD3 R22, R9, -0x1, RZ ;
STG.E.U8 [R16.64], R11 ;
LDG.E.U8 R19, [R18.64] ;
IADD3 R20, P1, R14, c[0x0][0x178], RZ ;
IADD3 R22, P2, R22, c[0x0][0x160], RZ ;
IMAD.X R21, RZ, RZ, c[0x0][0x17c], P1 ;
IMAD.X R23, RZ, RZ, c[0x0][0x164], P2 ;
IADD3 R24, P1, R10, c[0x0][0x178], RZ ;
STG.E.U8 [R20.64], R19 ;
LDG.E.U8 R23, [R22.64] ;
IADD3 R26, P2, R9, c[0x0][0x160], RZ ;
IMAD.X R25, RZ, RZ, c[0x0][0x17c], P1 ;
IMAD.X R27, RZ, RZ, c[0x0][0x164], P2 ;
IADD3 R5, R5, 0x4, RZ ;
IADD3 R16, P1, R12, c[0x0][0x178], RZ ;
IMAD.IADD R11, R8, 0x1, R5 ;
STG.E.U8 [R24.64], R23 ;
LDG.E.U8 R27, [R26.64] ;
IADD3.X R17, RZ, c[0x0][0x17c], RZ, P1, !PT ;
IMAD R14, R7, 0x4, R14 ;
ISETP.NE.AND P1, PT, R11, RZ, PT ;
IMAD R10, R7, 0x4, R10 ;
IADD3 R9, R9, 0x4, RZ ;
IMAD R12, R7.reuse, 0x4, R12 ;
LEA R2, R7, R2, 0x2 ;
STG.E.U8 [R16.64], R27 ;
@P1 BRA 0x1f0 ;
@!P0 EXIT ;
IMAD R4, R5, c[0x0][0x180], R4 ;
IMAD R5, R3, c[0x0][0x174], R5 ;
IMAD R7, R3, c[0x0][0x16c], R4 ;
IMAD.IADD R6, R6, 0x1, R5 ;
IADD3 R2, P0, R6, c[0x0][0x160], RZ ;
IMAD.X R3, RZ, RZ, c[0x0][0x164], P0 ;
LDG.E.U8 R3, [R2.64] ;
IADD3 R4, P0, R7.reuse, c[0x0][0x178], RZ ;
IADD3 R0, R0, -0x1, RZ ;
IADD3 R7, R7, c[0x0][0x180], RZ ;
IMAD.X R5, RZ, RZ, c[0x0][0x17c], P0 ;
ISETP.NE.AND P0, PT, R0, RZ, PT ;
IADD3 R6, R6, 0x1, RZ ;
STG.E.U8 [R4.64], R3 ;
@P0 BRA 0x480 ;
EXIT ;
BRA 0x540;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
```
|
```amdasm
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.section .text._ZN8mmdeploy9operation4cuda9transposeIhEEvPKT_iiiiPS3_i,"axG",@progbits,_ZN8mmdeploy9operation4cuda9transposeIhEEvPKT_iiiiPS3_i,comdat
.protected _ZN8mmdeploy9operation4cuda9transposeIhEEvPKT_iiiiPS3_i ; -- Begin function _ZN8mmdeploy9operation4cuda9transposeIhEEvPKT_iiiiPS3_i
.globl _ZN8mmdeploy9operation4cuda9transposeIhEEvPKT_iiiiPS3_i
.p2align 8
.type _ZN8mmdeploy9operation4cuda9transposeIhEEvPKT_iiiiPS3_i,@function
_ZN8mmdeploy9operation4cuda9transposeIhEEvPKT_iiiiPS3_i: ; @_ZN8mmdeploy9operation4cuda9transposeIhEEvPKT_iiiiPS3_i
; %bb.0:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x34
s_load_b128 s[4:7], s[0:1], 0x8
v_and_b32_e32 v4, 0x3ff, v0
v_bfe_u32 v0, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s2, 0xffff
s_lshr_b32 s2, s2, 16
s_mul_i32 s14, s14, s3
v_mad_u64_u32 v[2:3], null, s15, s2, v[0:1]
v_add_nc_u32_e32 v0, s14, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cmp_gt_u32_e32 vcc_lo, s5, v0
v_cmp_gt_u32_e64 s2, s4, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
s_and_b32 s2, vcc_lo, s2
s_cmp_gt_i32 s6, 0
s_cselect_b32 s3, -1, 0
s_and_b32 s2, s2, s3
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_3
; %bb.1: ; %.lr.ph
s_clause 0x2
s_load_b64 s[2:3], s[0:1], 0x0
s_load_b64 s[8:9], s[0:1], 0x18
s_load_b32 s0, s[0:1], 0x20
v_mul_lo_u32 v3, v0, s6
v_mul_lo_u32 v5, v2, s5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[0:1], null, v2, s7, v[3:4]
v_add3_u32 v1, v4, v5, s14
.LBB0_2: ; =>This Inner Loop Header: Depth=1
s_waitcnt lgkmcnt(0)
global_load_u8 v2, v0, s[2:3]
v_add_nc_u32_e32 v0, 1, v0
s_add_i32 s6, s6, -1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_lg_u32 s6, 0
s_waitcnt vmcnt(0)
global_store_b8 v1, v2, s[8:9]
v_add_nc_u32_e32 v1, s0, v1
s_cbranch_scc1 .LBB0_2
.LBB0_3: ; %.loopexit
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _ZN8mmdeploy9operation4cuda9transposeIhEEvPKT_iiiiPS3_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.section .text._ZN8mmdeploy9operation4cuda9transposeIhEEvPKT_iiiiPS3_i,"axG",@progbits,_ZN8mmdeploy9operation4cuda9transposeIhEEvPKT_iiiiPS3_i,comdat
.Lfunc_end0:
.size _ZN8mmdeploy9operation4cuda9transposeIhEEvPKT_iiiiPS3_i, .Lfunc_end0-_ZN8mmdeploy9operation4cuda9transposeIhEEvPKT_iiiiPS3_i
; -- End function
.section .AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 240
; NumSgprs: 18
; NumVgprs: 6
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 6
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
.section .text._ZN8mmdeploy9operation4cuda9transposeIfEEvPKT_iiiiPS3_i,"axG",@progbits,_ZN8mmdeploy9operation4cuda9transposeIfEEvPKT_iiiiPS3_i,comdat
.protected _ZN8mmdeploy9operation4cuda9transposeIfEEvPKT_iiiiPS3_i ; -- Begin function _ZN8mmdeploy9operation4cuda9transposeIfEEvPKT_iiiiPS3_i
.globl _ZN8mmdeploy9operation4cuda9transposeIfEEvPKT_iiiiPS3_i
.p2align 8
.type _ZN8mmdeploy9operation4cuda9transposeIfEEvPKT_iiiiPS3_i,@function
_ZN8mmdeploy9operation4cuda9transposeIfEEvPKT_iiiiPS3_i: ; @_ZN8mmdeploy9operation4cuda9transposeIfEEvPKT_iiiiPS3_i
; %bb.0:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x34
s_load_b128 s[4:7], s[0:1], 0x8
v_and_b32_e32 v4, 0x3ff, v0
v_bfe_u32 v0, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s2, 0xffff
s_lshr_b32 s2, s2, 16
s_mul_i32 s14, s14, s3
v_mad_u64_u32 v[2:3], null, s15, s2, v[0:1]
v_add_nc_u32_e32 v0, s14, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cmp_gt_u32_e32 vcc_lo, s5, v0
v_cmp_gt_u32_e64 s2, s4, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
s_and_b32 s2, vcc_lo, s2
s_cmp_gt_i32 s6, 0
s_cselect_b32 s3, -1, 0
s_and_b32 s2, s2, s3
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB1_3
; %bb.1: ; %.lr.ph
s_clause 0x2
s_load_b64 s[2:3], s[0:1], 0x0
s_load_b64 s[8:9], s[0:1], 0x18
s_load_b32 s0, s[0:1], 0x20
v_mul_lo_u32 v3, v0, s6
v_mul_lo_u32 v5, v2, s5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[0:1], null, v2, s7, v[3:4]
v_add3_u32 v2, v4, v5, s14
v_mov_b32_e32 v1, 0
.LBB1_2: ; =>This Inner Loop Header: Depth=1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[3:4], 2, v[0:1]
s_add_i32 s6, s6, -1
v_add_nc_u32_e32 v0, 1, v0
s_cmp_lg_u32 s6, 0
s_waitcnt lgkmcnt(0)
v_add_co_u32 v3, vcc_lo, s2, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s3, v4, vcc_lo
global_load_b32 v5, v[3:4], off
v_mov_b32_e32 v3, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[3:4], 2, v[2:3]
v_add_nc_u32_e32 v2, s0, v2
v_add_co_u32 v3, vcc_lo, s8, v3
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v4, vcc_lo, s9, v4, vcc_lo
s_waitcnt vmcnt(0)
global_store_b32 v[3:4], v5, off
s_cbranch_scc1 .LBB1_2
.LBB1_3: ; %.loopexit
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _ZN8mmdeploy9operation4cuda9transposeIfEEvPKT_iiiiPS3_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.section .text._ZN8mmdeploy9operation4cuda9transposeIfEEvPKT_iiiiPS3_i,"axG",@progbits,_ZN8mmdeploy9operation4cuda9transposeIfEEvPKT_iiiiPS3_i,comdat
.Lfunc_end1:
.size _ZN8mmdeploy9operation4cuda9transposeIfEEvPKT_iiiiPS3_i, .Lfunc_end1-_ZN8mmdeploy9operation4cuda9transposeIfEEvPKT_iiiiPS3_i
; -- End function
.section .AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 296
; NumSgprs: 18
; NumVgprs: 6
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 6
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object ; @__hip_cuid_
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0 ; 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _ZN8mmdeploy9operation4cuda9transposeIhEEvPKT_iiiiPS3_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _ZN8mmdeploy9operation4cuda9transposeIhEEvPKT_iiiiPS3_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _ZN8mmdeploy9operation4cuda9transposeIfEEvPKT_iiiiPS3_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _ZN8mmdeploy9operation4cuda9transposeIfEEvPKT_iiiiPS3_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
```
| 3,548 | 6,181 |
39 |
Convert the following CUDA host assembly code to AMD host assembly:
```cudaasm
.file "tmpxft_000c4f4e_00000000-6_transpose.cudafe1.cpp"
.text
.type _ZL69__device_stub__ZN8mmdeploy9operation4cuda9transposeIhEEvPKT_iiiiPS3_iPKhiiiiPhi, @function
_ZL69__device_stub__ZN8mmdeploy9operation4cuda9transposeIhEEvPKT_iiiiPS3_iPKhiiiiPhi:
.LFB2054:
.cfi_startproc
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 24(%rsp)
movl %esi, 20(%rsp)
movl %edx, 16(%rsp)
movl %ecx, 12(%rsp)
movl %r8d, 8(%rsp)
movq %r9, (%rsp)
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 12(%rsp), %rax
movq %rax, 120(%rsp)
leaq 8(%rsp), %rax
movq %rax, 128(%rsp)
movq %rsp, %rax
movq %rax, 136(%rsp)
leaq 176(%rsp), %rax
movq %rax, 144(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L5
.L1:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L6
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L5:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 184
pushq 40(%rsp)
.cfi_def_cfa_offset 192
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _ZN8mmdeploy9operation4cuda9transposeIhEEvPKT_iiiiPS3_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L1
.L6:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2054:
.size _ZL69__device_stub__ZN8mmdeploy9operation4cuda9transposeIhEEvPKT_iiiiPS3_iPKhiiiiPhi, .-_ZL69__device_stub__ZN8mmdeploy9operation4cuda9transposeIhEEvPKT_iiiiPS3_iPKhiiiiPhi
.section .text._ZN8mmdeploy9operation4cuda9transposeIhEEvPKT_iiiiPS3_i,"axG",@progbits,_ZN8mmdeploy9operation4cuda9transposeIhEEvPKT_iiiiPS3_i,comdat
.weak _ZN8mmdeploy9operation4cuda9transposeIhEEvPKT_iiiiPS3_i
.type _ZN8mmdeploy9operation4cuda9transposeIhEEvPKT_iiiiPS3_i, @function
_ZN8mmdeploy9operation4cuda9transposeIhEEvPKT_iiiiPS3_i:
.LFB2107:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
call _ZL69__device_stub__ZN8mmdeploy9operation4cuda9transposeIhEEvPKT_iiiiPS3_iPKhiiiiPhi
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2107:
.size _ZN8mmdeploy9operation4cuda9transposeIhEEvPKT_iiiiPS3_i, .-_ZN8mmdeploy9operation4cuda9transposeIhEEvPKT_iiiiPS3_i
.text
.type _ZL69__device_stub__ZN8mmdeploy9operation4cuda9transposeIfEEvPKT_iiiiPS3_iPKfiiiiPfi, @function
_ZL69__device_stub__ZN8mmdeploy9operation4cuda9transposeIfEEvPKT_iiiiPS3_iPKfiiiiPfi:
.LFB2056:
.cfi_startproc
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 24(%rsp)
movl %esi, 20(%rsp)
movl %edx, 16(%rsp)
movl %ecx, 12(%rsp)
movl %r8d, 8(%rsp)
movq %r9, (%rsp)
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 12(%rsp), %rax
movq %rax, 120(%rsp)
leaq 8(%rsp), %rax
movq %rax, 128(%rsp)
movq %rsp, %rax
movq %rax, 136(%rsp)
leaq 176(%rsp), %rax
movq %rax, 144(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L13
.L9:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L14
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L13:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 184
pushq 40(%rsp)
.cfi_def_cfa_offset 192
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _ZN8mmdeploy9operation4cuda9transposeIfEEvPKT_iiiiPS3_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L9
.L14:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2056:
.size _ZL69__device_stub__ZN8mmdeploy9operation4cuda9transposeIfEEvPKT_iiiiPS3_iPKfiiiiPfi, .-_ZL69__device_stub__ZN8mmdeploy9operation4cuda9transposeIfEEvPKT_iiiiPS3_iPKfiiiiPfi
.section .text._ZN8mmdeploy9operation4cuda9transposeIfEEvPKT_iiiiPS3_i,"axG",@progbits,_ZN8mmdeploy9operation4cuda9transposeIfEEvPKT_iiiiPS3_i,comdat
.weak _ZN8mmdeploy9operation4cuda9transposeIfEEvPKT_iiiiPS3_i
.type _ZN8mmdeploy9operation4cuda9transposeIfEEvPKT_iiiiPS3_i, @function
_ZN8mmdeploy9operation4cuda9transposeIfEEvPKT_iiiiPS3_i:
.LFB2109:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
call _ZL69__device_stub__ZN8mmdeploy9operation4cuda9transposeIfEEvPKT_iiiiPS3_iPKfiiiiPfi
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2109:
.size _ZN8mmdeploy9operation4cuda9transposeIfEEvPKT_iiiiPS3_i, .-_ZN8mmdeploy9operation4cuda9transposeIfEEvPKT_iiiiPS3_i
.text
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2032:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2032:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .text._ZN8mmdeploy9operation4cuda9TransposeIhEEvPKT_iiiPS3_P11CUstream_st,"axG",@progbits,_ZN8mmdeploy9operation4cuda9TransposeIhEEvPKT_iiiPS3_P11CUstream_st,comdat
.weak _ZN8mmdeploy9operation4cuda9TransposeIhEEvPKT_iiiPS3_P11CUstream_st
.type _ZN8mmdeploy9operation4cuda9TransposeIhEEvPKT_iiiPS3_P11CUstream_st, @function
_ZN8mmdeploy9operation4cuda9TransposeIhEEvPKT_iiiPS3_P11CUstream_st:
.LFB2105:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $32, %rsp
.cfi_def_cfa_offset 80
movq %rdi, %r13
movl %esi, %ebp
movl %edx, %ebx
movl %ecx, %r12d
movq %r8, %r14
leal 31(%rdx), %eax
shrl $5, %eax
movl %eax, 20(%rsp)
leal 7(%rsi), %eax
shrl $3, %eax
movl %eax, 24(%rsp)
movl $32, 8(%rsp)
movl $8, 12(%rsp)
movl $0, %r8d
movq 8(%rsp), %rdx
movl $1, %ecx
movq 20(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L22
.L19:
addq $32, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L22:
.cfi_restore_state
subq $8, %rsp
.cfi_def_cfa_offset 88
movl %ebp, %eax
imull %ebx, %eax
pushq %rax
.cfi_def_cfa_offset 96
movq %r14, %r9
movl %ebx, %r8d
imull %r12d, %r8d
movl %r12d, %ecx
movl %ebx, %edx
movl %ebp, %esi
movq %r13, %rdi
call _ZL69__device_stub__ZN8mmdeploy9operation4cuda9transposeIhEEvPKT_iiiiPS3_iPKhiiiiPhi
addq $16, %rsp
.cfi_def_cfa_offset 80
jmp .L19
.cfi_endproc
.LFE2105:
.size _ZN8mmdeploy9operation4cuda9TransposeIhEEvPKT_iiiPS3_P11CUstream_st, .-_ZN8mmdeploy9operation4cuda9TransposeIhEEvPKT_iiiPS3_P11CUstream_st
.section .text._ZN8mmdeploy9operation4cuda9TransposeIfEEvPKT_iiiPS3_P11CUstream_st,"axG",@progbits,_ZN8mmdeploy9operation4cuda9TransposeIfEEvPKT_iiiPS3_P11CUstream_st,comdat
.weak _ZN8mmdeploy9operation4cuda9TransposeIfEEvPKT_iiiPS3_P11CUstream_st
.type _ZN8mmdeploy9operation4cuda9TransposeIfEEvPKT_iiiPS3_P11CUstream_st, @function
_ZN8mmdeploy9operation4cuda9TransposeIfEEvPKT_iiiPS3_P11CUstream_st:
.LFB2106:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $32, %rsp
.cfi_def_cfa_offset 80
movq %rdi, %r13
movl %esi, %ebp
movl %edx, %ebx
movl %ecx, %r12d
movq %r8, %r14
leal 31(%rdx), %eax
shrl $5, %eax
movl %eax, 20(%rsp)
leal 7(%rsi), %eax
shrl $3, %eax
movl %eax, 24(%rsp)
movl $32, 8(%rsp)
movl $8, 12(%rsp)
movl $0, %r8d
movq 8(%rsp), %rdx
movl $1, %ecx
movq 20(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L26
.L23:
addq $32, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L26:
.cfi_restore_state
subq $8, %rsp
.cfi_def_cfa_offset 88
movl %ebp, %eax
imull %ebx, %eax
pushq %rax
.cfi_def_cfa_offset 96
movq %r14, %r9
movl %ebx, %r8d
imull %r12d, %r8d
movl %r12d, %ecx
movl %ebx, %edx
movl %ebp, %esi
movq %r13, %rdi
call _ZL69__device_stub__ZN8mmdeploy9operation4cuda9transposeIfEEvPKT_iiiiPS3_iPKfiiiiPfi
addq $16, %rsp
.cfi_def_cfa_offset 80
jmp .L23
.cfi_endproc
.LFE2106:
.size _ZN8mmdeploy9operation4cuda9TransposeIfEEvPKT_iiiPS3_P11CUstream_st, .-_ZN8mmdeploy9operation4cuda9TransposeIfEEvPKT_iiiPS3_P11CUstream_st
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_ZN8mmdeploy9operation4cuda9transposeIfEEvPKT_iiiiPS3_i"
.align 8
.LC1:
.string "_ZN8mmdeploy9operation4cuda9transposeIhEEvPKT_iiiiPS3_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2059:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _ZN8mmdeploy9operation4cuda9transposeIfEEvPKT_iiiiPS3_i(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _ZN8mmdeploy9operation4cuda9transposeIhEEvPKT_iiiiPS3_i(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2059:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
```
|
```amdasm
.text
.file "transpose.hip"
.section .text._ZN8mmdeploy9operation4cuda9TransposeIhEEvPKT_iiiPS3_P12ihipStream_t,"axG",@progbits,_ZN8mmdeploy9operation4cuda9TransposeIhEEvPKT_iiiPS3_P12ihipStream_t,comdat
.weak _ZN8mmdeploy9operation4cuda9TransposeIhEEvPKT_iiiPS3_P12ihipStream_t # -- Begin function _ZN8mmdeploy9operation4cuda9TransposeIhEEvPKT_iiiPS3_P12ihipStream_t
.type _ZN8mmdeploy9operation4cuda9TransposeIhEEvPKT_iiiPS3_P12ihipStream_t,@function
_ZN8mmdeploy9operation4cuda9TransposeIhEEvPKT_iiiPS3_P12ihipStream_t: # @_ZN8mmdeploy9operation4cuda9TransposeIhEEvPKT_iiiPS3_P12ihipStream_t
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $16, %rsp
.cfi_def_cfa_offset 64
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %r8, %rbx
movl %ecx, %ebp
movl %edx, %r14d
movl %esi, %r15d
movq %rdi, %r12
leal 31(%r14), %eax
shrl $5, %eax
leal 7(%r15), %edi
shrl $3, %edi
shlq $32, %rdi
orq %rax, %rdi
movabsq $34359738400, %rdx # imm = 0x800000020
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB0_2
# %bb.1:
movl %r14d, %eax
imull %r15d, %eax
movl %ebp, %r8d
imull %r14d, %r8d
movl %eax, (%rsp)
movq %r12, %rdi
movl %r15d, %esi
movl %r14d, %edx
movl %ebp, %ecx
movq %rbx, %r9
callq _ZN8mmdeploy9operation4cuda24__device_stub__transposeIhEEvPKT_iiiiPS3_i
.LBB0_2:
addq $16, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _ZN8mmdeploy9operation4cuda9TransposeIhEEvPKT_iiiPS3_P12ihipStream_t, .Lfunc_end0-_ZN8mmdeploy9operation4cuda9TransposeIhEEvPKT_iiiPS3_P12ihipStream_t
.cfi_endproc
# -- End function
.section .text._ZN8mmdeploy9operation4cuda24__device_stub__transposeIhEEvPKT_iiiiPS3_i,"axG",@progbits,_ZN8mmdeploy9operation4cuda24__device_stub__transposeIhEEvPKT_iiiiPS3_i,comdat
.weak _ZN8mmdeploy9operation4cuda24__device_stub__transposeIhEEvPKT_iiiiPS3_i # -- Begin function _ZN8mmdeploy9operation4cuda24__device_stub__transposeIhEEvPKT_iiiiPS3_i
.type _ZN8mmdeploy9operation4cuda24__device_stub__transposeIhEEvPKT_iiiiPS3_i,@function
_ZN8mmdeploy9operation4cuda24__device_stub__transposeIhEEvPKT_iiiiPS3_i: # @_ZN8mmdeploy9operation4cuda24__device_stub__transposeIhEEvPKT_iiiiPS3_i
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $144, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 40(%rsp), %rax
movq %rdi, (%rax)
leaq 12(%rsp), %rdi
movl %esi, (%rdi)
leaq 8(%rsp), %rsi
movl %edx, (%rsi)
leaq 4(%rsp), %rdx
movl %ecx, (%rdx)
movq %rsp, %rcx
movl %r8d, (%rcx)
leaq 32(%rsp), %r8
movq %r9, (%r8)
leaq 80(%rsp), %rbx
movq %rax, (%rbx)
movq %rdi, 8(%rbx)
movq %rsi, 16(%rbx)
movq %rdx, 24(%rbx)
movq %rcx, 32(%rbx)
movq %r8, 40(%rbx)
leaq 192(%rsp), %rax
movq %rax, 48(%rbx)
leaq 64(%rsp), %r14
leaq 48(%rsp), %r15
leaq 24(%rsp), %r12
leaq 16(%rsp), %r13
movq %r14, %rdi
movq %r15, %rsi
movq %r12, %rdx
movq %r13, %rcx
callq __hipPopCallConfiguration
movq (%r14), %rsi
movl 8(%r14), %edx
movq (%r15), %rcx
movl 8(%r15), %r8d
movl $_ZN8mmdeploy9operation4cuda9transposeIhEEvPKT_iiiiPS3_i, %edi
movq %rbx, %r9
pushq (%r13)
.cfi_adjust_cfa_offset 8
pushq (%r12)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $160, %rsp
.cfi_adjust_cfa_offset -160
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _ZN8mmdeploy9operation4cuda24__device_stub__transposeIhEEvPKT_iiiiPS3_i, .Lfunc_end1-_ZN8mmdeploy9operation4cuda24__device_stub__transposeIhEEvPKT_iiiiPS3_i
.cfi_endproc
# -- End function
.section .text._ZN8mmdeploy9operation4cuda9TransposeIfEEvPKT_iiiPS3_P12ihipStream_t,"axG",@progbits,_ZN8mmdeploy9operation4cuda9TransposeIfEEvPKT_iiiPS3_P12ihipStream_t,comdat
.weak _ZN8mmdeploy9operation4cuda9TransposeIfEEvPKT_iiiPS3_P12ihipStream_t # -- Begin function _ZN8mmdeploy9operation4cuda9TransposeIfEEvPKT_iiiPS3_P12ihipStream_t
.type _ZN8mmdeploy9operation4cuda9TransposeIfEEvPKT_iiiPS3_P12ihipStream_t,@function
_ZN8mmdeploy9operation4cuda9TransposeIfEEvPKT_iiiPS3_P12ihipStream_t: # @_ZN8mmdeploy9operation4cuda9TransposeIfEEvPKT_iiiPS3_P12ihipStream_t
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $16, %rsp
.cfi_def_cfa_offset 64
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %r8, %rbx
movl %ecx, %ebp
movl %edx, %r14d
movl %esi, %r15d
movq %rdi, %r12
leal 31(%r14), %eax
shrl $5, %eax
leal 7(%r15), %edi
shrl $3, %edi
shlq $32, %rdi
orq %rax, %rdi
movabsq $34359738400, %rdx # imm = 0x800000020
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_2
# %bb.1:
movl %r14d, %eax
imull %r15d, %eax
movl %ebp, %r8d
imull %r14d, %r8d
movl %eax, (%rsp)
movq %r12, %rdi
movl %r15d, %esi
movl %r14d, %edx
movl %ebp, %ecx
movq %rbx, %r9
callq _ZN8mmdeploy9operation4cuda24__device_stub__transposeIfEEvPKT_iiiiPS3_i
.LBB2_2:
addq $16, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size _ZN8mmdeploy9operation4cuda9TransposeIfEEvPKT_iiiPS3_P12ihipStream_t, .Lfunc_end2-_ZN8mmdeploy9operation4cuda9TransposeIfEEvPKT_iiiPS3_P12ihipStream_t
.cfi_endproc
# -- End function
.section .text._ZN8mmdeploy9operation4cuda24__device_stub__transposeIfEEvPKT_iiiiPS3_i,"axG",@progbits,_ZN8mmdeploy9operation4cuda24__device_stub__transposeIfEEvPKT_iiiiPS3_i,comdat
.weak _ZN8mmdeploy9operation4cuda24__device_stub__transposeIfEEvPKT_iiiiPS3_i # -- Begin function _ZN8mmdeploy9operation4cuda24__device_stub__transposeIfEEvPKT_iiiiPS3_i
.type _ZN8mmdeploy9operation4cuda24__device_stub__transposeIfEEvPKT_iiiiPS3_i,@function
_ZN8mmdeploy9operation4cuda24__device_stub__transposeIfEEvPKT_iiiiPS3_i: # @_ZN8mmdeploy9operation4cuda24__device_stub__transposeIfEEvPKT_iiiiPS3_i
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $144, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 40(%rsp), %rax
movq %rdi, (%rax)
leaq 12(%rsp), %rdi
movl %esi, (%rdi)
leaq 8(%rsp), %rsi
movl %edx, (%rsi)
leaq 4(%rsp), %rdx
movl %ecx, (%rdx)
movq %rsp, %rcx
movl %r8d, (%rcx)
leaq 32(%rsp), %r8
movq %r9, (%r8)
leaq 80(%rsp), %rbx
movq %rax, (%rbx)
movq %rdi, 8(%rbx)
movq %rsi, 16(%rbx)
movq %rdx, 24(%rbx)
movq %rcx, 32(%rbx)
movq %r8, 40(%rbx)
leaq 192(%rsp), %rax
movq %rax, 48(%rbx)
leaq 64(%rsp), %r14
leaq 48(%rsp), %r15
leaq 24(%rsp), %r12
leaq 16(%rsp), %r13
movq %r14, %rdi
movq %r15, %rsi
movq %r12, %rdx
movq %r13, %rcx
callq __hipPopCallConfiguration
movq (%r14), %rsi
movl 8(%r14), %edx
movq (%r15), %rcx
movl 8(%r15), %r8d
movl $_ZN8mmdeploy9operation4cuda9transposeIfEEvPKT_iiiiPS3_i, %edi
movq %rbx, %r9
pushq (%r13)
.cfi_adjust_cfa_offset 8
pushq (%r12)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $160, %rsp
.cfi_adjust_cfa_offset -160
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size _ZN8mmdeploy9operation4cuda24__device_stub__transposeIfEEvPKT_iiiiPS3_i, .Lfunc_end3-_ZN8mmdeploy9operation4cuda24__device_stub__transposeIfEEvPKT_iiiiPS3_i
.cfi_endproc
# -- End function
.text
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
movq __hip_gpubin_handle(%rip), %rbx
testq %rbx, %rbx
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, %rbx
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_ZN8mmdeploy9operation4cuda9transposeIhEEvPKT_iiiiPS3_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_ZN8mmdeploy9operation4cuda9transposeIfEEvPKT_iiiiPS3_i, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type _ZN8mmdeploy9operation4cuda9transposeIhEEvPKT_iiiiPS3_i,@object # @_ZN8mmdeploy9operation4cuda9transposeIhEEvPKT_iiiiPS3_i
.section .rodata._ZN8mmdeploy9operation4cuda9transposeIhEEvPKT_iiiiPS3_i,"aG",@progbits,_ZN8mmdeploy9operation4cuda9transposeIhEEvPKT_iiiiPS3_i,comdat
.weak _ZN8mmdeploy9operation4cuda9transposeIhEEvPKT_iiiiPS3_i
.p2align 3, 0x0
_ZN8mmdeploy9operation4cuda9transposeIhEEvPKT_iiiiPS3_i:
.quad _ZN8mmdeploy9operation4cuda24__device_stub__transposeIhEEvPKT_iiiiPS3_i
.size _ZN8mmdeploy9operation4cuda9transposeIhEEvPKT_iiiiPS3_i, 8
.type _ZN8mmdeploy9operation4cuda9transposeIfEEvPKT_iiiiPS3_i,@object # @_ZN8mmdeploy9operation4cuda9transposeIfEEvPKT_iiiiPS3_i
.section .rodata._ZN8mmdeploy9operation4cuda9transposeIfEEvPKT_iiiiPS3_i,"aG",@progbits,_ZN8mmdeploy9operation4cuda9transposeIfEEvPKT_iiiiPS3_i,comdat
.weak _ZN8mmdeploy9operation4cuda9transposeIfEEvPKT_iiiiPS3_i
.p2align 3, 0x0
_ZN8mmdeploy9operation4cuda9transposeIfEEvPKT_iiiiPS3_i:
.quad _ZN8mmdeploy9operation4cuda24__device_stub__transposeIfEEvPKT_iiiiPS3_i
.size _ZN8mmdeploy9operation4cuda9transposeIfEEvPKT_iiiiPS3_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_ZN8mmdeploy9operation4cuda9transposeIhEEvPKT_iiiiPS3_i"
.size .L__unnamed_1, 56
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_ZN8mmdeploy9operation4cuda9transposeIfEEvPKT_iiiiPS3_i"
.size .L__unnamed_2, 56
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _ZN8mmdeploy9operation4cuda24__device_stub__transposeIhEEvPKT_iiiiPS3_i
.addrsig_sym _ZN8mmdeploy9operation4cuda24__device_stub__transposeIfEEvPKT_iiiiPS3_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _ZN8mmdeploy9operation4cuda9transposeIhEEvPKT_iiiiPS3_i
.addrsig_sym _ZN8mmdeploy9operation4cuda9transposeIfEEvPKT_iiiiPS3_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
```
| 5,670 | 6,188 |
40 |
Convert the following CUDA device assembly code to AMD device assembly:
```cudaasm
code for sm_80
Function : _Z14mandelbrot_setddddiiiPi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ;
S2R R2, SR_CTAID.Y ;
S2R R3, SR_TID.Y ;
IMAD R2, R2, c[0x0][0x4], R3 ;
ISETP.GE.AND P0, PT, R2, c[0x0][0x184], PT ;
@P0 EXIT ;
S2R R3, SR_CTAID.X ;
ISETP.LT.AND P0, PT, RZ, c[0x0][0x188], PT ;
ULDC.64 UR4, c[0x0][0x118] ;
S2R R0, SR_TID.X ;
IMAD R3, R3, c[0x0][0x0], R0 ;
@P0 BRA 0x1e0 ;
ISETP.GE.AND P0, PT, R3, c[0x0][0x180], PT ;
BSSY B0, 0x1a0 ;
IMAD.MOV.U32 R11, RZ, RZ, c[0x0][0x4] ;
@P0 BRA 0x190 ;
IMAD.MOV.U32 R7, RZ, RZ, R3 ;
IMAD.MOV.U32 R9, RZ, RZ, 0x4 ;
IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x0] ;
IMAD R4, R2, c[0x0][0x180], R7.reuse ;
IMAD R7, R0, c[0x0][0xc], R7 ;
IMAD.WIDE R4, R4, R9, c[0x0][0x190] ;
ISETP.GE.AND P0, PT, R7, c[0x0][0x180], PT ;
STG.E [R4.64], RZ ;
@!P0 BRA 0x130 ;
BSYNC B0 ;
IMAD R2, R11, c[0x0][0x10], R2 ;
ISETP.GE.AND P0, PT, R2, c[0x0][0x184], PT ;
@!P0 BRA 0xc0 ;
EXIT ;
I2F.F64 R30, c[0x0][0x184] ;
IMAD.MOV.U32 R26, RZ, RZ, c[0x0][0x178] ;
IMAD.MOV.U32 R27, RZ, RZ, c[0x0][0x17c] ;
IMAD.MOV.U32 R24, RZ, RZ, c[0x0][0x168] ;
IMAD.MOV.U32 R25, RZ, RZ, c[0x0][0x16c] ;
I2F.F64 R28, c[0x0][0x180] ;
DADD R26, R26, -c[0x0][0x170] ;
DADD R24, R24, -c[0x0][0x160] ;
ISETP.GE.AND P0, PT, R3, c[0x0][0x180], PT ;
BSSY B0, 0xb50 ;
@P0 BRA 0xb40 ;
MUFU.RCP64H R7, R31 ;
IMAD.MOV.U32 R6, RZ, RZ, 0x1 ;
BSSY B1, 0x430 ;
DFMA R4, -R30, R6, 1 ;
DFMA R8, R4, R4, R4 ;
I2F.F64 R4, R2 ;
DFMA R8, R6, R8, R6 ;
DFMA R6, -R30, R8, 1 ;
DFMA R6, R8, R6, R8 ;
DMUL R10, R26, R4 ;
DMUL R4, R10, R6 ;
FSETP.GEU.AND P1, PT, |R11|, 6.5827683646048100446e-37, PT ;
DFMA R8, -R30, R4, R10 ;
DFMA R4, R6, R8, R4 ;
FFMA R0, RZ, R31, R5 ;
FSETP.GT.AND P0, PT, |R0|, 1.469367938527859385e-39, PT ;
@P0 BRA P1, 0x420 ;
IMAD.MOV.U32 R6, RZ, RZ, R10 ;
MOV R0, 0x400 ;
IMAD.MOV.U32 R7, RZ, RZ, R11 ;
IMAD.MOV.U32 R8, RZ, RZ, R30 ;
IMAD.MOV.U32 R9, RZ, RZ, R31 ;
CALL.REL.NOINC 0xba0 ;
MOV R4, R34 ;
IMAD.MOV.U32 R5, RZ, RZ, R35 ;
BSYNC B1 ;
DADD R22, R4, c[0x0][0x170] ;
IMAD.MOV.U32 R5, RZ, RZ, R3 ;
MUFU.RCP64H R9, R29 ;
IMAD.MOV.U32 R8, RZ, RZ, 0x1 ;
BSSY B1, 0x5f0 ;
DFMA R6, -R28, R8, 1 ;
DFMA R10, R6, R6, R6 ;
I2F.F64 R6, R5 ;
DFMA R10, R8, R10, R8 ;
DFMA R8, -R28, R10, 1 ;
DFMA R8, R10, R8, R10 ;
DMUL R12, R24, R6 ;
DMUL R6, R12, R8 ;
FSETP.GEU.AND P1, PT, |R13|, 6.5827683646048100446e-37, PT ;
DFMA R10, -R28, R6, R12 ;
DFMA R6, R8, R10, R6 ;
FFMA R0, RZ, R29, R7 ;
FSETP.GT.AND P0, PT, |R0|, 1.469367938527859385e-39, PT ;
@P0 BRA P1, 0x5e0 ;
IMAD.MOV.U32 R6, RZ, RZ, R12 ;
MOV R0, 0x5c0 ;
IMAD.MOV.U32 R7, RZ, RZ, R13 ;
IMAD.MOV.U32 R8, RZ, RZ, R28 ;
IMAD.MOV.U32 R9, RZ, RZ, R29 ;
CALL.REL.NOINC 0xba0 ;
IMAD.MOV.U32 R6, RZ, RZ, R34 ;
IMAD.MOV.U32 R7, RZ, RZ, R35 ;
BSYNC B1 ;
DADD R20, R6, c[0x0][0x160] ;
BSSY B1, 0xac0 ;
IMAD.MOV.U32 R4, RZ, RZ, RZ ;
CS2R R18, SRZ ;
CS2R R16, SRZ ;
DMUL R6, R16.reuse, R16 ;
BSSY B2, 0x890 ;
DMUL R8, R16, R18 ;
DFMA R6, R18, R18, -R6 ;
DFMA R8, R16, R18, R8 ;
DADD R18, R20, R6 ;
IMAD.MOV.U32 R6, RZ, RZ, 0x1 ;
DADD R16, R22, R8 ;
DADD R10, -RZ, |R18| ;
DADD R12, -RZ, |R16| ;
DSETP.GT.AND P0, PT, |R18|, |R16|, PT ;
FSEL R15, R11, R13, P0 ;
FSEL R14, R10, R12, P0 ;
MUFU.RCP64H R7, R15 ;
FSEL R12, R12, R10, P0 ;
FSEL R13, R13, R11, P0 ;
FSETP.GEU.AND P1, PT, |R13|, 6.5827683646048100446e-37, PT ;
DFMA R8, -R14, R6, 1 ;
DFMA R8, R8, R8, R8 ;
DFMA R8, R6, R8, R6 ;
DFMA R6, -R14, R8, 1 ;
DFMA R6, R8, R6, R8 ;
DMUL R8, R12, R6 ;
DFMA R10, -R14, R8, R12 ;
DFMA R6, R6, R10, R8 ;
FFMA R0, RZ, R15, R7 ;
FSETP.GT.AND P0, PT, |R0|, 1.469367938527859385e-39, PT ;
@P0 BRA P1, 0x880 ;
MOV R6, R12 ;
IMAD.MOV.U32 R7, RZ, RZ, R13 ;
MOV R0, 0x860 ;
IMAD.MOV.U32 R8, RZ, RZ, R14 ;
IMAD.MOV.U32 R9, RZ, RZ, R15 ;
CALL.REL.NOINC 0xba0 ;
IMAD.MOV.U32 R6, RZ, RZ, R34 ;
IMAD.MOV.U32 R7, RZ, RZ, R35 ;
BSYNC B2 ;
DFMA R6, R6, R6, 1 ;
IMAD.MOV.U32 R32, RZ, RZ, 0x0 ;
BSSY B2, 0x9e0 ;
IMAD.MOV.U32 R33, RZ, RZ, 0x3fd80000 ;
MUFU.RSQ64H R9, R7 ;
IADD3 R8, R7, -0x3500000, RZ ;
ISETP.GE.U32.AND P0, PT, R8, 0x7ca00000, PT ;
DMUL R10, R8, R8 ;
DFMA R10, R6, -R10, 1 ;
DFMA R32, R10, R32, 0.5 ;
DMUL R10, R8, R10 ;
DFMA R38, R32, R10, R8 ;
DMUL R10, R6, R38 ;
IADD3 R37, R39, -0x100000, RZ ;
IMAD.MOV.U32 R36, RZ, RZ, R38 ;
DFMA R32, R10, -R10, R6 ;
DFMA R34, R32, R36, R10 ;
@!P0 BRA 0x9d0 ;
MOV R0, 0x9d0 ;
CALL.REL.NOINC 0x1160 ;
BSYNC B2 ;
DSETP.GT.AND P0, PT, R14, c[0x2][0x0], PT ;
DMUL R34, R14, R34 ;
DSETP.EQ.OR P0, PT, R14, RZ, P0 ;
DADD R14, R14, R12 ;
DSETP.GT.OR P0, PT, R12, c[0x2][0x0], P0 ;
FSEL R6, R14, R34, P0 ;
FSEL R7, R15, R35, P0 ;
DSETP.GT.AND P0, PT, R6, 2, PT ;
@P0 BRA 0xab0 ;
IADD3 R4, R4, 0x1, RZ ;
ISETP.GE.AND P0, PT, R4, c[0x0][0x188], PT ;
@!P0 BRA 0x640 ;
IMAD.MOV.U32 R4, RZ, RZ, RZ ;
BSYNC B1 ;
IMAD.MOV.U32 R7, RZ, RZ, 0x4 ;
IMAD R6, R2, c[0x0][0x180], R5 ;
IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x0] ;
IMAD.WIDE R6, R6, R7, c[0x0][0x190] ;
IMAD R5, R0, c[0x0][0xc], R5 ;
STG.E [R6.64], R4 ;
ISETP.GE.AND P0, PT, R5, c[0x0][0x180], PT ;
@!P0 BRA 0x450 ;
BSYNC B0 ;
MOV R5, c[0x0][0x4] ;
IMAD R2, R5, c[0x0][0x10], R2 ;
ISETP.GE.AND P0, PT, R2, c[0x0][0x184], PT ;
@!P0 BRA 0x260 ;
EXIT ;
FSETP.GEU.AND P0, PT, |R9|.reuse, 1.469367938527859385e-39, PT ;
IMAD.MOV.U32 R36, RZ, RZ, 0x1 ;
LOP3.LUT R10, R9, 0x800fffff, RZ, 0xc0, !PT ;
IMAD.MOV.U32 R41, RZ, RZ, 0x1ca00000 ;
FSETP.GEU.AND P2, PT, |R7|.reuse, 1.469367938527859385e-39, PT ;
IMAD.MOV.U32 R32, RZ, RZ, R6 ;
LOP3.LUT R11, R10, 0x3ff00000, RZ, 0xfc, !PT ;
IMAD.MOV.U32 R10, RZ, RZ, R8 ;
LOP3.LUT R40, R7, 0x7ff00000, RZ, 0xc0, !PT ;
BSSY B3, 0x1130 ;
LOP3.LUT R43, R9, 0x7ff00000, RZ, 0xc0, !PT ;
@!P0 DMUL R10, R8, 8.98846567431157953865e+307 ;
ISETP.GE.U32.AND P1, PT, R40, R43, PT ;
@!P2 LOP3.LUT R33, R9, 0x7ff00000, RZ, 0xc0, !PT ;
@!P2 IMAD.MOV.U32 R38, RZ, RZ, RZ ;
MUFU.RCP64H R37, R11 ;
@!P2 ISETP.GE.U32.AND P3, PT, R40, R33, PT ;
SEL R33, R41.reuse, 0x63400000, !P1 ;
@!P2 SEL R39, R41, 0x63400000, !P3 ;
LOP3.LUT R33, R33, 0x800fffff, R7, 0xf8, !PT ;
@!P2 LOP3.LUT R39, R39, 0x80000000, R7, 0xf8, !PT ;
@!P0 LOP3.LUT R43, R11, 0x7ff00000, RZ, 0xc0, !PT ;
@!P2 LOP3.LUT R39, R39, 0x100000, RZ, 0xfc, !PT ;
DFMA R34, R36, -R10, 1 ;
@!P2 DFMA R32, R32, 2, -R38 ;
DFMA R34, R34, R34, R34 ;
DFMA R34, R36, R34, R36 ;
DFMA R36, R34, -R10, 1 ;
DFMA R34, R34, R36, R34 ;
DMUL R36, R34, R32 ;
DFMA R38, R36, -R10, R32 ;
DFMA R38, R34, R38, R36 ;
IMAD.MOV.U32 R36, RZ, RZ, R40 ;
@!P2 LOP3.LUT R36, R33, 0x7ff00000, RZ, 0xc0, !PT ;
IADD3 R34, R36, -0x1, RZ ;
ISETP.GT.U32.AND P0, PT, R34, 0x7feffffe, PT ;
IADD3 R34, R43, -0x1, RZ ;
ISETP.GT.U32.OR P0, PT, R34, 0x7feffffe, P0 ;
@P0 BRA 0xfd0 ;
LOP3.LUT R7, R9, 0x7ff00000, RZ, 0xc0, !PT ;
ISETP.GE.U32.AND P0, PT, R40.reuse, R7, PT ;
IMAD.IADD R6, R40, 0x1, -R7 ;
SEL R41, R41, 0x63400000, !P0 ;
IMNMX R6, R6, -0x46a00000, !PT ;
IMNMX R6, R6, 0x46a00000, PT ;
IMAD.IADD R36, R6, 0x1, -R41 ;
IMAD.MOV.U32 R6, RZ, RZ, RZ ;
IADD3 R7, R36, 0x7fe00000, RZ ;
DMUL R34, R38, R6 ;
FSETP.GTU.AND P0, PT, |R35|, 1.469367938527859385e-39, PT ;
@P0 BRA 0x1120 ;
DFMA R10, R38, -R10, R32 ;
IMAD.MOV.U32 R8, RZ, RZ, RZ ;
FSETP.NEU.AND P0, PT, R11.reuse, RZ, PT ;
LOP3.LUT R33, R11, 0x80000000, R9, 0x48, !PT ;
LOP3.LUT R9, R33, R7, RZ, 0xfc, !PT ;
@!P0 BRA 0x1120 ;
IMAD.MOV R7, RZ, RZ, -R36 ;
MOV R6, RZ ;
DMUL.RP R8, R38, R8 ;
DFMA R6, R34, -R6, R38 ;
LOP3.LUT R33, R9, R33, RZ, 0x3c, !PT ;
IADD3 R6, -R36, -0x43300000, RZ ;
FSETP.NEU.AND P0, PT, |R7|, R6, PT ;
FSEL R34, R8, R34, !P0 ;
FSEL R35, R33, R35, !P0 ;
BRA 0x1120 ;
DSETP.NAN.AND P0, PT, R6, R6, PT ;
@P0 BRA 0x1100 ;
DSETP.NAN.AND P0, PT, R8, R8, PT ;
@P0 BRA 0x10d0 ;
ISETP.NE.AND P0, PT, R36, R43, PT ;
IMAD.MOV.U32 R34, RZ, RZ, 0x0 ;
IMAD.MOV.U32 R35, RZ, RZ, -0x80000 ;
@!P0 BRA 0x1120 ;
ISETP.NE.AND P0, PT, R36, 0x7ff00000, PT ;
LOP3.LUT R35, R7, 0x80000000, R9, 0x48, !PT ;
ISETP.EQ.OR P0, PT, R43, RZ, !P0 ;
@P0 LOP3.LUT R6, R35, 0x7ff00000, RZ, 0xfc, !PT ;
@!P0 IMAD.MOV.U32 R34, RZ, RZ, RZ ;
@P0 IMAD.MOV.U32 R34, RZ, RZ, RZ ;
@P0 IMAD.MOV.U32 R35, RZ, RZ, R6 ;
BRA 0x1120 ;
LOP3.LUT R35, R9, 0x80000, RZ, 0xfc, !PT ;
IMAD.MOV.U32 R34, RZ, RZ, R8 ;
BRA 0x1120 ;
LOP3.LUT R35, R7, 0x80000, RZ, 0xfc, !PT ;
IMAD.MOV.U32 R34, RZ, RZ, R6 ;
BSYNC B3 ;
IMAD.MOV.U32 R6, RZ, RZ, R0 ;
IMAD.MOV.U32 R7, RZ, RZ, 0x0 ;
RET.REL.NODEC R6 0x0 ;
ISETP.GE.U32.AND P0, PT, R8, -0x3400000, PT ;
BSSY B3, 0x13e0 ;
IMAD.MOV.U32 R36, RZ, RZ, R38 ;
MOV R9, R33 ;
IMAD.MOV.U32 R8, RZ, RZ, R32 ;
@!P0 BRA 0x1240 ;
DFMA.RM R8, R8, R36, R10 ;
IADD3 R10, P0, R8, 0x1, RZ ;
IMAD.X R11, RZ, RZ, R9, P0 ;
DFMA.RP R6, -R8, R10, R6 ;
DSETP.GT.AND P0, PT, R6, RZ, PT ;
FSEL R8, R10, R8, P0 ;
FSEL R9, R11, R9, P0 ;
BRA 0x13d0 ;
DSETP.NE.AND P0, PT, R6, RZ, PT ;
@!P0 BRA 0x13c0 ;
ISETP.GE.AND P0, PT, R7, RZ, PT ;
@!P0 IMAD.MOV.U32 R8, RZ, RZ, 0x0 ;
@!P0 IMAD.MOV.U32 R9, RZ, RZ, -0x80000 ;
@!P0 BRA 0x13d0 ;
ISETP.GT.AND P0, PT, R7, 0x7fefffff, PT ;
@P0 BRA 0x13c0 ;
DMUL R6, R6, 8.11296384146066816958e+31 ;
IMAD.MOV.U32 R8, RZ, RZ, RZ ;
IMAD.MOV.U32 R32, RZ, RZ, 0x0 ;
IMAD.MOV.U32 R33, RZ, RZ, 0x3fd80000 ;
MUFU.RSQ64H R9, R7 ;
DMUL R10, R8, R8 ;
DFMA R10, R6, -R10, 1 ;
DFMA R32, R10, R32, 0.5 ;
DMUL R10, R8, R10 ;
DFMA R10, R32, R10, R8 ;
DMUL R8, R6, R10 ;
IADD3 R11, R11, -0x100000, RZ ;
DFMA R32, R8, -R8, R6 ;
DFMA R8, R10, R32, R8 ;
IADD3 R9, R9, -0x3500000, RZ ;
BRA 0x13d0 ;
DADD R8, R6, R6 ;
BSYNC B3 ;
IMAD.MOV.U32 R6, RZ, RZ, R0 ;
IMAD.MOV.U32 R7, RZ, RZ, 0x0 ;
IMAD.MOV.U32 R34, RZ, RZ, R8 ;
IMAD.MOV.U32 R35, RZ, RZ, R9 ;
RET.REL.NODEC R6 0x0 ;
BRA 0x1430;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
```
|
```amdasm
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z14mandelbrot_setddddiiiPi ; -- Begin function _Z14mandelbrot_setddddiiiPi
.globl _Z14mandelbrot_setddddiiiPi
.p2align 8
.type _Z14mandelbrot_setddddiiiPi,@function
_Z14mandelbrot_setddddiiiPi: ; @_Z14mandelbrot_setddddiiiPi
; %bb.0:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x44
s_load_b128 s[16:19], s[0:1], 0x20
v_bfe_u32 v1, v0, 10, 10
s_add_u32 s2, s0, 56
s_addc_u32 s3, s1, 0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s12, s4, 16
s_mov_b32 s4, exec_lo
v_mad_u64_u32 v[4:5], null, s15, s12, v[1:2]
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s17, v4
s_cbranch_execz .LBB0_14
; %bb.1: ; %.lr.ph35
s_load_b256 s[4:11], s[0:1], 0x0
v_cvt_f64_i32_e32 v[5:6], s16
v_cvt_f64_i32_e32 v[11:12], s17
v_and_b32_e32 v0, 0x3ff, v0
s_waitcnt lgkmcnt(0)
v_add_f64 v[7:8], s[6:7], -s[4:5]
v_add_f64 v[9:10], s[10:11], -s[8:9]
s_clause 0x1
s_load_b32 s6, s[2:3], 0xc
s_load_b64 s[10:11], s[2:3], 0x0
s_load_b64 s[2:3], s[0:1], 0x30
s_mov_b32 s7, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s1, s6, 0xffff
s_cmp_gt_i32 s18, 0
v_mad_u64_u32 v[13:14], null, s14, s1, v[0:1]
s_cselect_b32 s6, -1, 0
s_mul_i32 s10, s10, s1
s_mul_i32 s11, s11, s12
s_delay_alu instid0(VALU_DEP_1)
v_cmp_gt_i32_e64 s0, s16, v13
.LBB0_2: ; =>This Loop Header: Depth=1
; Child Loop BB0_4 Depth 2
; Child Loop BB0_6 Depth 3
s_delay_alu instid0(VALU_DEP_1)
s_and_saveexec_b32 s19, s0
s_cbranch_execz .LBB0_12
; %bb.3: ; %.lr.ph
; in Loop: Header=BB0_2 Depth=1
v_cvt_f64_i32_e32 v[0:1], v4
s_mov_b32 s20, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f64 v[0:1], v[9:10], v[0:1]
v_div_scale_f64 v[2:3], null, v[11:12], v[11:12], v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f64_e32 v[14:15], v[2:3]
s_waitcnt_depctr 0xfff
v_fma_f64 v[16:17], -v[2:3], v[14:15], 1.0
v_fma_f64 v[14:15], v[14:15], v[16:17], v[14:15]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[16:17], -v[2:3], v[14:15], 1.0
v_fma_f64 v[14:15], v[14:15], v[16:17], v[14:15]
v_div_scale_f64 v[16:17], vcc_lo, v[0:1], v[11:12], v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f64 v[18:19], v[16:17], v[14:15]
v_fma_f64 v[2:3], -v[2:3], v[18:19], v[16:17]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_div_fmas_f64 v[2:3], v[2:3], v[14:15], v[18:19]
v_mul_lo_u32 v18, v4, s16
v_mov_b32_e32 v19, v13
v_div_fixup_f64 v[0:1], v[2:3], v[11:12], v[0:1]
s_delay_alu instid0(VALU_DEP_1)
v_add_f64 v[14:15], v[0:1], s[8:9]
.LBB0_4: ; Parent Loop BB0_2 Depth=1
; => This Loop Header: Depth=2
; Child Loop BB0_6 Depth 3
s_and_not1_b32 vcc_lo, exec_lo, s6
s_cbranch_vccnz .LBB0_10
; %bb.5: ; %.lr.ph.i
; in Loop: Header=BB0_4 Depth=2
v_cvt_f64_i32_e32 v[0:1], v19
s_mov_b32 s12, 0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
s_mov_b32 s13, s12
s_mov_b32 s14, s12
s_mov_b32 s15, s12
s_mov_b32 s1, s12
v_mul_f64 v[0:1], v[7:8], v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_scale_f64 v[2:3], null, v[5:6], v[5:6], v[0:1]
v_rcp_f64_e32 v[16:17], v[2:3]
s_waitcnt_depctr 0xfff
v_fma_f64 v[20:21], -v[2:3], v[16:17], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[16:17], v[16:17], v[20:21], v[16:17]
v_fma_f64 v[20:21], -v[2:3], v[16:17], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_fma_f64 v[16:17], v[16:17], v[20:21], v[16:17]
v_div_scale_f64 v[20:21], vcc_lo, v[0:1], v[5:6], v[0:1]
v_mul_f64 v[22:23], v[20:21], v[16:17]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[2:3], -v[2:3], v[22:23], v[20:21]
v_div_fmas_f64 v[2:3], v[2:3], v[16:17], v[22:23]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fixup_f64 v[0:1], v[2:3], v[5:6], v[0:1]
v_add_f64 v[16:17], v[0:1], s[4:5]
v_dual_mov_b32 v0, s12 :: v_dual_mov_b32 v1, s13
v_dual_mov_b32 v2, s14 :: v_dual_mov_b32 v3, s15
; implicit-def: $sgpr13
.LBB0_6: ; Parent Loop BB0_2 Depth=1
; Parent Loop BB0_4 Depth=2
; => This Inner Loop Header: Depth=3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_mul_f64 v[20:21], v[2:3], v[2:3]
v_mul_f64 v[2:3], v[2:3], v[0:1]
s_or_b32 s13, s13, exec_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f64 v[0:1], v[0:1], v[0:1], -v[20:21]
v_fma_f64 v[2:3], v[2:3], 2.0, v[14:15]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f64 v[0:1], v[16:17], v[0:1]
v_mul_f64 v[20:21], v[2:3], v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[20:21], v[0:1], v[0:1], v[20:21]
v_cmp_gt_f64_e32 vcc_lo, 0x10000000, v[20:21]
v_cndmask_b32_e64 v22, 0, 1, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b32_e32 v22, 8, v22
v_ldexp_f64 v[20:21], v[20:21], v22
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_rsq_f64_e32 v[22:23], v[20:21]
s_waitcnt_depctr 0xfff
v_mul_f64 v[24:25], v[20:21], v[22:23]
v_mul_f64 v[22:23], v[22:23], 0.5
v_fma_f64 v[26:27], -v[22:23], v[24:25], 0.5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_fma_f64 v[24:25], v[24:25], v[26:27], v[24:25]
v_fma_f64 v[22:23], v[22:23], v[26:27], v[22:23]
v_fma_f64 v[26:27], -v[24:25], v[24:25], v[20:21]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[24:25], v[26:27], v[22:23], v[24:25]
v_fma_f64 v[26:27], -v[24:25], v[24:25], v[20:21]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_fma_f64 v[22:23], v[26:27], v[22:23], v[24:25]
v_cndmask_b32_e64 v24, 0, 0xffffff80, vcc_lo
v_cmp_class_f64_e64 vcc_lo, v[20:21], 0x260
v_ldexp_f64 v[22:23], v[22:23], v24
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_cndmask_b32 v21, v23, v21 :: v_dual_cndmask_b32 v20, v22, v20
v_cmp_nlt_f64_e32 vcc_lo, 2.0, v[20:21]
v_mov_b32_e32 v20, s1
s_and_saveexec_b32 s14, vcc_lo
; %bb.7: ; in Loop: Header=BB0_6 Depth=3
s_add_i32 s1, s1, 1
v_mov_b32_e32 v20, 0
s_cmp_eq_u32 s18, s1
s_cselect_b32 s15, -1, 0
s_and_not1_b32 s13, s13, exec_lo
s_and_b32 s15, s15, exec_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 s13, s13, s15
; %bb.8: ; %Flow
; in Loop: Header=BB0_6 Depth=3
s_or_b32 exec_lo, exec_lo, s14
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s14, exec_lo, s13
s_or_b32 s12, s14, s12
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s12
s_cbranch_execnz .LBB0_6
; %bb.9: ; %Flow60
; in Loop: Header=BB0_4 Depth=2
s_or_b32 exec_lo, exec_lo, s12
s_branch .LBB0_11
.LBB0_10: ; in Loop: Header=BB0_4 Depth=2
v_mov_b32_e32 v20, 0
.LBB0_11: ; %_Z10mandelbrot15HIP_vector_typeIdLj2EEi.exit
; in Loop: Header=BB0_4 Depth=2
v_add_nc_u32_e32 v0, v19, v18
v_add_nc_u32_e32 v19, s10, v19
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v1, 31, v0
v_cmp_le_i32_e32 vcc_lo, s16, v19
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_or_b32 s20, vcc_lo, s20
v_add_co_u32 v0, s1, s2, v0
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v1, s1, s3, v1, s1
global_store_b32 v[0:1], v20, off
s_and_not1_b32 exec_lo, exec_lo, s20
s_cbranch_execnz .LBB0_4
.LBB0_12: ; %Flow63
; in Loop: Header=BB0_2 Depth=1
s_or_b32 exec_lo, exec_lo, s19
; %bb.13: ; %._crit_edge
; in Loop: Header=BB0_2 Depth=1
v_add_nc_u32_e32 v4, s11, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_le_i32_e32 vcc_lo, s17, v4
s_or_b32 s7, vcc_lo, s7
s_and_not1_b32 exec_lo, exec_lo, s7
s_cbranch_execnz .LBB0_2
.LBB0_14: ; %Flow65
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z14mandelbrot_setddddiiiPi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 312
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 28
.amdhsa_next_free_sgpr 21
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z14mandelbrot_setddddiiiPi, .Lfunc_end0-_Z14mandelbrot_setddddiiiPi
; -- End function
.section .AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 976
; NumSgprs: 23
; NumVgprs: 28
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 3
; NumSGPRsForWavesPerEU: 23
; NumVGPRsForWavesPerEU: 28
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object ; @__hip_cuid_
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0 ; 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 8
.value_kind: by_value
- .offset: 8
.size: 8
.value_kind: by_value
- .offset: 16
.size: 8
.value_kind: by_value
- .offset: 24
.size: 8
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 36
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 48
.size: 8
.value_kind: global_buffer
- .offset: 56
.size: 4
.value_kind: hidden_block_count_x
- .offset: 60
.size: 4
.value_kind: hidden_block_count_y
- .offset: 64
.size: 4
.value_kind: hidden_block_count_z
- .offset: 68
.size: 2
.value_kind: hidden_group_size_x
- .offset: 70
.size: 2
.value_kind: hidden_group_size_y
- .offset: 72
.size: 2
.value_kind: hidden_group_size_z
- .offset: 74
.size: 2
.value_kind: hidden_remainder_x
- .offset: 76
.size: 2
.value_kind: hidden_remainder_y
- .offset: 78
.size: 2
.value_kind: hidden_remainder_z
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 112
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 120
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 312
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z14mandelbrot_setddddiiiPi
.private_segment_fixed_size: 0
.sgpr_count: 23
.sgpr_spill_count: 0
.symbol: _Z14mandelbrot_setddddiiiPi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 28
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
```
| 6,389 | 6,603 |
41 |
Convert the following CUDA host assembly code to AMD host assembly:
```cudaasm
.file "tmpxft_000b1f83_00000000-6_mandelbrot.cudafe1.cpp"
.text
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z10mandelbrot7double2i
.type _Z10mandelbrot7double2i, @function
_Z10mandelbrot7double2i:
.LFB2080:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2080:
.size _Z10mandelbrot7double2i, .-_Z10mandelbrot7double2i
.globl _Z41__device_stub__Z14mandelbrot_setddddiiiPiddddiiiPi
.type _Z41__device_stub__Z14mandelbrot_setddddiiiPiddddiiiPi, @function
_Z41__device_stub__Z14mandelbrot_setddddiiiPiddddiiiPi:
.LFB2106:
.cfi_startproc
endbr64
subq $216, %rsp
.cfi_def_cfa_offset 224
movsd %xmm0, 56(%rsp)
movsd %xmm1, 48(%rsp)
movsd %xmm2, 40(%rsp)
movsd %xmm3, 32(%rsp)
movl %edi, 28(%rsp)
movl %esi, 24(%rsp)
movl %edx, 20(%rsp)
movq %rcx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 200(%rsp)
xorl %eax, %eax
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 40(%rsp), %rax
movq %rax, 144(%rsp)
leaq 32(%rsp), %rax
movq %rax, 152(%rsp)
leaq 28(%rsp), %rax
movq %rax, 160(%rsp)
leaq 24(%rsp), %rax
movq %rax, 168(%rsp)
leaq 20(%rsp), %rax
movq %rax, 176(%rsp)
leaq 8(%rsp), %rax
movq %rax, 184(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
leaq 72(%rsp), %rcx
leaq 64(%rsp), %rdx
leaq 92(%rsp), %rsi
leaq 80(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L9
.L5:
movq 200(%rsp), %rax
subq %fs:40, %rax
jne .L10
addq $216, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L9:
.cfi_restore_state
pushq 72(%rsp)
.cfi_def_cfa_offset 232
pushq 72(%rsp)
.cfi_def_cfa_offset 240
leaq 144(%rsp), %r9
movq 108(%rsp), %rcx
movl 116(%rsp), %r8d
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
leaq _Z14mandelbrot_setddddiiiPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 224
jmp .L5
.L10:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2106:
.size _Z41__device_stub__Z14mandelbrot_setddddiiiPiddddiiiPi, .-_Z41__device_stub__Z14mandelbrot_setddddiiiPiddddiiiPi
.globl _Z14mandelbrot_setddddiiiPi
.type _Z14mandelbrot_setddddiiiPi, @function
_Z14mandelbrot_setddddiiiPi:
.LFB2107:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z41__device_stub__Z14mandelbrot_setddddiiiPiddddiiiPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2107:
.size _Z14mandelbrot_setddddiiiPi, .-_Z14mandelbrot_setddddiiiPi
.section .rodata.str1.1,"aMS",@progbits,1
.LC4:
.string "wb"
.LC5:
.string "MathPic.ppm"
.LC6:
.string "P6\n%d %d\n255\n"
.text
.globl main
.type main, @function
main:
.LFB2081:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $48, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movq $0, 16(%rsp)
movl $8294400, %edi
call malloc@PLT
movq %rax, %rbx
leaq 16(%rsp), %rdi
movl $8294400, %esi
call cudaMalloc@PLT
movl $16, 28(%rsp)
movl $16, 32(%rsp)
movq 28(%rsp), %rdi
movl $0, %r9d
movl $0, %r8d
movq %rdi, %rdx
movl $1, %ecx
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L21
.L14:
movl $2, %ecx
movl $8294400, %edx
movq 16(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
leaq .LC4(%rip), %rsi
leaq .LC5(%rip), %rdi
call fopen@PLT
movq %rax, %r12
movl $1080, %r8d
movl $1920, %ecx
leaq .LC6(%rip), %rdx
movl $2, %esi
movq %rax, %rdi
movl $0, %eax
call __fprintf_chk@PLT
movq %rbx, %rbp
leaq 8294400(%rbx), %r14
movq %rbx, %rax
movl $0, %ebx
.L15:
movl (%rax), %edx
cmpl %edx, %ebx
cmovl %edx, %ebx
addq $4, %rax
cmpq %r14, %rax
jne .L15
leaq 15(%rsp), %r13
.L16:
movl 0(%rbp), %edx
movl %edx, %eax
sall $8, %eax
subl %edx, %eax
cltd
idivl %ebx
movb %al, 15(%rsp)
movq %r12, %rcx
movl $1, %edx
movl $1, %esi
movq %r13, %rdi
call fwrite@PLT
movq %r12, %rcx
movl $1, %edx
movl $1, %esi
movq %r13, %rdi
call fwrite@PLT
movq %r12, %rcx
movl $1, %edx
movl $1, %esi
movq %r13, %rdi
call fwrite@PLT
addq $4, %rbp
cmpq %r14, %rbp
jne .L16
movq %r12, %rdi
call fclose@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L22
movl $0, %eax
addq $48, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L21:
.cfi_restore_state
movq 16(%rsp), %rcx
movl $2048, %edx
movl $1080, %esi
movl $1920, %edi
movsd .LC0(%rip), %xmm3
movsd .LC1(%rip), %xmm2
movsd .LC2(%rip), %xmm1
movsd .LC3(%rip), %xmm0
call _Z41__device_stub__Z14mandelbrot_setddddiiiPiddddiiiPi
jmp .L14
.L22:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2081:
.size main, .-main
.section .rodata.str1.1
.LC7:
.string "_Z14mandelbrot_setddddiiiPi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2109:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _Z14mandelbrot_setddddiiiPi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2109:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC0:
.long 163277477
.long 1068542398
.align 8
.LC1:
.long 768008872
.long 1068541926
.align 8
.LC2:
.long 1937614366
.long -1075317377
.align 8
.LC3:
.long 1326011023
.long -1075317272
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
```
|
```amdasm
.text
.file "mandelbrot.hip"
.globl _Z29__device_stub__mandelbrot_setddddiiiPi # -- Begin function _Z29__device_stub__mandelbrot_setddddiiiPi
.type _Z29__device_stub__mandelbrot_setddddiiiPi,@function
_Z29__device_stub__mandelbrot_setddddiiiPi: # @_Z29__device_stub__mandelbrot_setddddiiiPi
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $176, %rsp
.cfi_def_cfa_offset 224
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 72(%rsp), %rax
movsd %xmm0, (%rax)
leaq 64(%rsp), %r8
movsd %xmm1, (%r8)
leaq 56(%rsp), %r9
movsd %xmm2, (%r9)
leaq 48(%rsp), %r10
movsd %xmm3, (%r10)
leaq 20(%rsp), %r11
movl %edi, (%r11)
leaq 16(%rsp), %rdi
movl %esi, (%rdi)
leaq 12(%rsp), %rsi
movl %edx, (%rsi)
leaq 40(%rsp), %rdx
movq %rcx, (%rdx)
leaq 112(%rsp), %rbx
movq %rax, (%rbx)
movq %r8, 8(%rbx)
movq %r9, 16(%rbx)
movq %r10, 24(%rbx)
movq %r11, 32(%rbx)
movq %rdi, 40(%rbx)
movq %rsi, 48(%rbx)
movq %rdx, 56(%rbx)
leaq 96(%rsp), %r14
leaq 80(%rsp), %r15
leaq 32(%rsp), %r12
leaq 24(%rsp), %r13
movq %r14, %rdi
movq %r15, %rsi
movq %r12, %rdx
movq %r13, %rcx
callq __hipPopCallConfiguration
movq (%r14), %rsi
movl 8(%r14), %edx
movq (%r15), %rcx
movl 8(%r15), %r8d
movl $_Z14mandelbrot_setddddiiiPi, %edi
movq %rbx, %r9
pushq (%r13)
.cfi_adjust_cfa_offset 8
pushq (%r12)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $192, %rsp
.cfi_adjust_cfa_offset -192
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z29__device_stub__mandelbrot_setddddiiiPi, .Lfunc_end0-_Z29__device_stub__mandelbrot_setddddiiiPi
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI1_0:
.quad 0xbfe7f5e84f09528f # double -0.74876799999999999
.LCPI1_1:
.quad 0xbfe7f57f737da61e # double -0.74871799999999999
.LCPI1_2:
.quad 0x3fb0a7e62dc6e2a8 # double 0.0650619375
.LCPI1_3:
.quad 0x3fb0a9be09bb6aa5 # double 0.065090062500000004
.text
.globl main
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $16, %rsp
.cfi_def_cfa_offset 64
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
leaq 8(%rsp), %r14
movq $0, (%r14)
movl $8294400, %edi # imm = 0x7E9000
callq malloc
movq %rax, %rbx
movl $8294400, %esi # imm = 0x7E9000
movq %r14, %rdi
callq hipMalloc
xorl %r15d, %r15d
movabsq $68719476752, %rdi # imm = 0x1000000010
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq 8(%rsp), %rcx
movsd .LCPI1_0(%rip), %xmm0 # xmm0 = mem[0],zero
movsd .LCPI1_1(%rip), %xmm1 # xmm1 = mem[0],zero
movsd .LCPI1_2(%rip), %xmm2 # xmm2 = mem[0],zero
movsd .LCPI1_3(%rip), %xmm3 # xmm3 = mem[0],zero
movl $1920, %edi # imm = 0x780
movl $1080, %esi # imm = 0x438
movl $2048, %edx # imm = 0x800
callq _Z29__device_stub__mandelbrot_setddddiiiPi
.LBB1_2:
movq 8(%rsp), %rsi
movl $8294400, %edx # imm = 0x7E9000
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
movl $.L.str, %edi
movl $.L.str.1, %esi
callq fopen
movq %rax, %r14
movl $.L.str.2, %esi
movq %rax, %rdi
movl $1920, %edx # imm = 0x780
movl $1080, %ecx # imm = 0x438
xorl %eax, %eax
callq fprintf
xorl %eax, %eax
.LBB1_3: # =>This Inner Loop Header: Depth=1
movl (%rbx,%rax,4), %ecx
cmpl %r15d, %ecx
cmovgl %ecx, %r15d
incq %rax
cmpq $2073600, %rax # imm = 0x1FA400
jne .LBB1_3
# %bb.4: # %.preheader.preheader
xorl %r12d, %r12d
.LBB1_5: # %.preheader
# =>This Inner Loop Header: Depth=1
movl (%rbx,%r12,4), %ecx
movl %ecx, %eax
shll $8, %eax
subl %ecx, %eax
cltd
idivl %r15d
movsbl %al, %ebp
movl %ebp, %edi
movq %r14, %rsi
callq fputc@PLT
movl %ebp, %edi
movq %r14, %rsi
callq fputc@PLT
movl %ebp, %edi
movq %r14, %rsi
callq fputc@PLT
incq %r12
cmpq $2073600, %r12 # imm = 0x1FA400
jne .LBB1_5
# %bb.6:
movq %r14, %rdi
callq fclose
xorl %eax, %eax
addq $16, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, %rdi
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z14mandelbrot_setddddiiiPi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z14mandelbrot_setddddiiiPi,@object # @_Z14mandelbrot_setddddiiiPi
.section .rodata,"a",@progbits
.globl _Z14mandelbrot_setddddiiiPi
.p2align 3, 0x0
_Z14mandelbrot_setddddiiiPi:
.quad _Z29__device_stub__mandelbrot_setddddiiiPi
.size _Z14mandelbrot_setddddiiiPi, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "MathPic.ppm"
.size .L.str, 12
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "wb"
.size .L.str.1, 3
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "P6\n%d %d\n255\n"
.size .L.str.2, 14
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z14mandelbrot_setddddiiiPi"
.size .L__unnamed_1, 28
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z29__device_stub__mandelbrot_setddddiiiPi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z14mandelbrot_setddddiiiPi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
```
| 3,809 | 4,016 |
50 |
Convert the following CUDA device assembly code to AMD device assembly:
```cudaasm
code for sm_80
Function : _Z12testKernel4rPfS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ;
S2R R2, SR_CTAID.X ;
IMAD.MOV.U32 R3, RZ, RZ, 0x4 ;
ULDC.64 UR4, c[0x0][0x118] ;
S2R R7, SR_TID.X ;
ISETP.NE.AND P0, PT, R2.reuse, RZ, PT ;
ISETP.GE.U32.AND P3, PT, R2, 0x15, PT ;
ISETP.NE.AND P2, PT, R7.reuse, RZ, PT ;
ISETP.GE.U32.AND P1, PT, R7, 0x15, PT ;
@P0 IMAD R0, R2.reuse, 0x16, R7.reuse ;
@!P3 IMAD R16, R2, 0x16, R7 ;
@P0 IMAD.WIDE.U32 R4, R0.reuse, R3, c[0x0][0x168] ;
@P0 IADD3 R8, R0, -0x16, RZ ;
@P2 IMAD R0, R2, 0x16, R7 ;
@!P3 IADD3 R10, R16, 0x16, RZ ;
@P0 IMAD.WIDE.U32 R8, R8, R3.reuse, c[0x0][0x168] ;
@P0 LDG.E R4, [R4.64] ;
@P2 IADD3 R12, R0.reuse, -0x1, RZ ;
@P2 IMAD.WIDE.U32 R6, R0, R3, c[0x0][0x168] ;
@P0 LDG.E R9, [R8.64] ;
@!P2 IMAD R0, R2, 0x16, RZ ;
@!P3 IMAD.WIDE.U32 R16, R16, R3.reuse, c[0x0][0x168] ;
@P2 LDG.E R7, [R6.64] ;
@!P3 IMAD.WIDE.U32 R10, R10, R3.reuse, c[0x0][0x168] ;
@!P1 IADD3 R14, R0, 0x1, RZ ;
@!P3 LDG.E R17, [R16.64] ;
@P2 IMAD.WIDE.U32 R12, R12, R3.reuse, c[0x0][0x168] ;
@!P3 LDG.E R10, [R10.64] ;
@!P1 IMAD.WIDE.U32 R14, R14, R3, c[0x0][0x168] ;
@P2 LDG.E R12, [R12.64] ;
IMAD.WIDE.U32 R2, R0, R3, c[0x0][0x168] ;
@!P1 LDG.E R15, [R14.64] ;
@!P1 LDG.E R18, [R2.64] ;
@P0 FADD R4, -R4, R9 ;
CS2R R8, SRZ ;
@P0 FADD R8, RZ, R4 ;
@P0 IMAD.MOV.U32 R9, RZ, RZ, 0x3f800000 ;
@!P3 FADD R5, -R17, R10 ;
@!P3 FADD R9, R9, 1 ;
@!P3 FADD R8, R8, R5 ;
@P2 FADD R5, -R7, R12 ;
LEA R4, P3, R0, c[0x0][0x160], 0x2 ;
@P2 FADD R9, R9, 1 ;
@P2 FADD R8, R8, R5 ;
@!P1 FADD R15, -R18, R15 ;
LEA.HI.X R5, R0, c[0x0][0x164], RZ, 0x2, P3 ;
@!P1 FADD R9, R9, 1 ;
@!P1 FADD R8, R8, R15 ;
@!P0 BRA 0x420 ;
LDG.E R2, [R2.64] ;
MUFU.RCP R0, R9 ;
BSSY B0, 0x3f0 ;
FCHK P0, R8, R9 ;
FFMA R7, R0, -R9, 1 ;
FFMA R7, R0, R7, R0 ;
FFMA R0, R7, R8, RZ ;
FFMA R6, R0, -R9, R8 ;
FFMA R7, R7, R6, R0 ;
@!P0 BRA 0x3e0 ;
MOV R0, 0x3d0 ;
CALL.REL.NOINC 0x450 ;
IMAD.MOV.U32 R7, RZ, RZ, R3 ;
BSYNC B0 ;
FFMA R7, R7, 0.5, R2 ;
STG.E [R4.64], R7 ;
EXIT ;
IMAD.MOV.U32 R3, RZ, RZ, 0x3f800000 ;
STG.E [R4.64], R3 ;
EXIT ;
SHF.R.U32.HI R6, RZ, 0x17, R9.reuse ;
BSSY B1, 0xab0 ;
SHF.R.U32.HI R3, RZ, 0x17, R8.reuse ;
LOP3.LUT R13, R6, 0xff, RZ, 0xc0, !PT ;
IMAD.MOV.U32 R6, RZ, RZ, R9 ;
LOP3.LUT R11, R3, 0xff, RZ, 0xc0, !PT ;
IMAD.MOV.U32 R3, RZ, RZ, R8 ;
IADD3 R12, R13, -0x1, RZ ;
IADD3 R10, R11, -0x1, RZ ;
ISETP.GT.U32.AND P0, PT, R12, 0xfd, PT ;
ISETP.GT.U32.OR P0, PT, R10, 0xfd, P0 ;
@!P0 IMAD.MOV.U32 R7, RZ, RZ, RZ ;
@!P0 BRA 0x690 ;
FSETP.GTU.FTZ.AND P0, PT, |R8|, +INF , PT ;
FSETP.GTU.FTZ.AND P1, PT, |R9|, +INF , PT ;
PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ;
@P0 BRA 0xa90 ;
LOP3.LUT P0, RZ, R6, 0x7fffffff, R3, 0xc8, !PT ;
@!P0 BRA 0xa70 ;
FSETP.NEU.FTZ.AND P1, PT, |R8|.reuse, +INF , PT ;
FSETP.NEU.FTZ.AND P2, PT, |R9|, +INF , PT ;
FSETP.NEU.FTZ.AND P0, PT, |R8|, +INF , PT ;
@!P2 BRA !P1, 0xa70 ;
LOP3.LUT P1, RZ, R3, 0x7fffffff, RZ, 0xc0, !PT ;
PLOP3.LUT P1, PT, P2, P1, PT, 0x2a, 0x0 ;
@P1 BRA 0xa50 ;
LOP3.LUT P1, RZ, R6, 0x7fffffff, RZ, 0xc0, !PT ;
PLOP3.LUT P0, PT, P0, P1, PT, 0x2a, 0x0 ;
@P0 BRA 0xa20 ;
ISETP.GE.AND P0, PT, R10, RZ, PT ;
ISETP.GE.AND P1, PT, R12, RZ, PT ;
@P0 IMAD.MOV.U32 R7, RZ, RZ, RZ ;
@!P0 IMAD.MOV.U32 R7, RZ, RZ, -0x40 ;
@!P0 FFMA R3, R8, 1.84467440737095516160e+19, RZ ;
@!P1 FFMA R6, R9, 1.84467440737095516160e+19, RZ ;
@!P1 IADD3 R7, R7, 0x40, RZ ;
LEA R9, R13, 0xc0800000, 0x17 ;
BSSY B2, 0xa10 ;
IMAD.IADD R9, R6, 0x1, -R9 ;
IADD3 R6, R11, -0x7f, RZ ;
MUFU.RCP R8, R9 ;
FADD.FTZ R10, -R9, -RZ ;
IMAD R3, R6, -0x800000, R3 ;
FFMA R11, R8, R10, 1 ;
FFMA R12, R8, R11, R8 ;
FFMA R8, R3, R12, RZ ;
FFMA R11, R10, R8, R3 ;
FFMA R11, R12, R11, R8 ;
IADD3 R8, R6, 0x7f, -R13 ;
FFMA R10, R10, R11, R3 ;
IMAD.IADD R8, R8, 0x1, R7 ;
FFMA R3, R12, R10, R11 ;
SHF.R.U32.HI R6, RZ, 0x17, R3 ;
LOP3.LUT R6, R6, 0xff, RZ, 0xc0, !PT ;
IMAD.IADD R13, R6, 0x1, R8 ;
IADD3 R6, R13, -0x1, RZ ;
ISETP.GE.U32.AND P0, PT, R6, 0xfe, PT ;
@!P0 BRA 0x9f0 ;
ISETP.GT.AND P0, PT, R13, 0xfe, PT ;
@P0 BRA 0x9c0 ;
ISETP.GE.AND P0, PT, R13, 0x1, PT ;
@P0 BRA 0xa00 ;
ISETP.GE.AND P0, PT, R13, -0x18, PT ;
LOP3.LUT R3, R3, 0x80000000, RZ, 0xc0, !PT ;
@!P0 BRA 0xa00 ;
FFMA.RZ R6, R12.reuse, R10.reuse, R11.reuse ;
IADD3 R9, R13.reuse, 0x20, RZ ;
FFMA.RM R7, R12, R10.reuse, R11.reuse ;
ISETP.NE.AND P2, PT, R13.reuse, RZ, PT ;
LOP3.LUT R8, R6, 0x7fffff, RZ, 0xc0, !PT ;
FFMA.RP R6, R12, R10, R11 ;
ISETP.NE.AND P1, PT, R13, RZ, PT ;
IMAD.MOV R10, RZ, RZ, -R13 ;
LOP3.LUT R8, R8, 0x800000, RZ, 0xfc, !PT ;
FSETP.NEU.FTZ.AND P0, PT, R6, R7, PT ;
SHF.L.U32 R9, R8, R9, RZ ;
SEL R7, R10, RZ, P2 ;
ISETP.NE.AND P1, PT, R9, RZ, P1 ;
SHF.R.U32.HI R7, RZ, R7, R8 ;
PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ;
SHF.R.U32.HI R9, RZ, 0x1, R7 ;
SEL R6, RZ, 0x1, !P0 ;
LOP3.LUT R6, R6, 0x1, R9, 0xf8, !PT ;
LOP3.LUT R6, R6, R7, RZ, 0xc0, !PT ;
IMAD.IADD R6, R9, 0x1, R6 ;
LOP3.LUT R3, R6, R3, RZ, 0xfc, !PT ;
BRA 0xa00 ;
LOP3.LUT R3, R3, 0x80000000, RZ, 0xc0, !PT ;
LOP3.LUT R3, R3, 0x7f800000, RZ, 0xfc, !PT ;
BRA 0xa00 ;
IMAD R3, R8, 0x800000, R3 ;
BSYNC B2 ;
BRA 0xaa0 ;
LOP3.LUT R3, R6, 0x80000000, R3, 0x48, !PT ;
LOP3.LUT R3, R3, 0x7f800000, RZ, 0xfc, !PT ;
BRA 0xaa0 ;
LOP3.LUT R3, R6, 0x80000000, R3, 0x48, !PT ;
BRA 0xaa0 ;
MUFU.RSQ R3, -QNAN ;
BRA 0xaa0 ;
FADD.FTZ R3, R8, R9 ;
BSYNC B1 ;
IMAD.MOV.U32 R6, RZ, RZ, R0 ;
IMAD.MOV.U32 R7, RZ, RZ, 0x0 ;
RET.REL.NODEC R6 0x0 ;
BRA 0xae0;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
```
|
```amdasm
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z12testKernel4rPfS_ ; -- Begin function _Z12testKernel4rPfS_
.globl _Z12testKernel4rPfS_
.p2align 8
.type _Z12testKernel4rPfS_,@function
_Z12testKernel4rPfS_: ; @_Z12testKernel4rPfS_
; %bb.0:
s_load_b128 s[0:3], s[0:1], 0x0
v_mov_b32_e32 v3, 0
s_cmp_lg_u32 s15, 0
s_mov_b32 s5, 0
s_cselect_b32 s4, -1, 0
s_cmp_eq_u32 s15, 0
s_cbranch_scc1 .LBB0_2
; %bb.1:
v_mad_u64_u32 v[1:2], null, s15, 22, v[0:1]
v_mov_b32_e32 v4, 0
s_mov_b32 s5, 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_mov_b32_e32 v2, v4
v_subrev_nc_u32_e32 v3, 22, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[1:2], 2, v[1:2]
v_lshlrev_b64 v[3:4], 2, v[3:4]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v3, vcc_lo, s2, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s3, v4, vcc_lo
s_delay_alu instid0(VALU_DEP_4)
v_add_co_u32 v1, vcc_lo, s2, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s3, v2, vcc_lo
s_clause 0x1
global_load_b32 v3, v[3:4], off
global_load_b32 v1, v[1:2], off
s_waitcnt vmcnt(0)
v_sub_f32_e32 v1, v3, v1
s_delay_alu instid0(VALU_DEP_1)
v_add_f32_e32 v3, 0, v1
.LBB0_2:
s_cmp_lt_u32 s15, 21
s_cbranch_scc1 .LBB0_4
; %bb.3: ; %._crit_edge
s_mov_b32 s6, 0
s_branch .LBB0_5
.LBB0_4:
s_mov_b32 s6, -1
.LBB0_5: ; %Flow35
v_mov_b32_e32 v4, s5
s_and_not1_b32 vcc_lo, exec_lo, s6
s_cbranch_vccnz .LBB0_7
; %bb.6:
v_mad_u64_u32 v[1:2], null, s15, 22, v[0:1]
v_mov_b32_e32 v2, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v1, vcc_lo, s2, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, s3, v2, vcc_lo
s_clause 0x1
global_load_b32 v4, v[1:2], off offset:88
global_load_b32 v1, v[1:2], off
s_waitcnt vmcnt(0)
v_sub_f32_e32 v1, v4, v1
v_add_f32_e64 v4, s5, 1.0
s_delay_alu instid0(VALU_DEP_2)
v_add_f32_e32 v3, v3, v1
.LBB0_7:
s_mov_b32 s5, exec_lo
v_cmpx_ne_u32_e32 0, v0
s_cbranch_execz .LBB0_9
; %bb.8:
v_mad_u64_u32 v[1:2], null, s15, 22, v[0:1]
v_mov_b32_e32 v6, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_dual_add_f32 v4, 1.0, v4 :: v_dual_add_nc_u32 v5, -1, v1
v_mov_b32_e32 v2, v6
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[5:6], 2, v[5:6]
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v5, vcc_lo, s2, v5
v_add_co_ci_u32_e32 v6, vcc_lo, s3, v6, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v1, vcc_lo, s2, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s3, v2, vcc_lo
s_clause 0x1
global_load_b32 v5, v[5:6], off
global_load_b32 v1, v[1:2], off
s_waitcnt vmcnt(0)
v_sub_f32_e32 v1, v5, v1
s_delay_alu instid0(VALU_DEP_1)
v_add_f32_e32 v3, v3, v1
.LBB0_9:
s_or_b32 exec_lo, exec_lo, s5
s_delay_alu instid0(SALU_CYCLE_1)
s_mov_b32 s5, exec_lo
v_cmpx_gt_u32_e32 21, v0
s_cbranch_execz .LBB0_11
; %bb.10:
v_mad_u64_u32 v[1:2], null, s15, 22, v[0:1]
v_mov_b32_e32 v6, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_dual_add_f32 v4, 1.0, v4 :: v_dual_add_nc_u32 v5, 1, v1
v_mov_b32_e32 v2, v6
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[5:6], 2, v[5:6]
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v5, vcc_lo, s2, v5
v_add_co_ci_u32_e32 v6, vcc_lo, s3, v6, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v1, vcc_lo, s2, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s3, v2, vcc_lo
s_clause 0x1
global_load_b32 v5, v[5:6], off
global_load_b32 v1, v[1:2], off
s_waitcnt vmcnt(0)
v_sub_f32_e32 v1, v5, v1
s_delay_alu instid0(VALU_DEP_1)
v_add_f32_e32 v3, v3, v1
.LBB0_11:
s_or_b32 exec_lo, exec_lo, s5
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 vcc_lo, exec_lo, s4
s_cbranch_vccz .LBB0_13
; %bb.12:
v_mad_u64_u32 v[1:2], null, s15, 22, v[0:1]
v_mov_b32_e32 v2, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[5:6], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v5, vcc_lo, s2, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v6, vcc_lo, s3, v6, vcc_lo
s_mov_b32 s2, 0
global_load_b32 v5, v[5:6], off
v_div_scale_f32 v6, null, v4, v4, v3
v_rcp_f32_e32 v7, v6
s_waitcnt_depctr 0xfff
v_fma_f32 v8, -v6, v7, 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v7, v8, v7
v_div_scale_f32 v8, vcc_lo, v3, v4, v3
v_mul_f32_e32 v9, v8, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v10, -v6, v9, v8
v_fmac_f32_e32 v9, v10, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v6, -v6, v9, v8
v_div_fmas_f32 v6, v6, v7, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_div_fixup_f32 v3, v6, v4, v3
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v5, 0.5, v3
s_branch .LBB0_14
.LBB0_13:
s_waitcnt lgkmcnt(0)
s_mov_b32 s2, -1
; implicit-def: $vgpr5
; implicit-def: $vgpr1_vgpr2
.LBB0_14: ; %Flow
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 vcc_lo, exec_lo, s2
s_cbranch_vccnz .LBB0_16
; %bb.15:
v_mov_b32_e32 v1, 0
s_delay_alu instid0(VALU_DEP_1)
v_dual_mov_b32 v5, 1.0 :: v_dual_mov_b32 v2, v1
v_mov_b32_e32 v1, v0
.LBB0_16:
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v5, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z12testKernel4rPfS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 16
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 11
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z12testKernel4rPfS_, .Lfunc_end0-_Z12testKernel4rPfS_
; -- End function
.section .AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 808
; NumSgprs: 18
; NumVgprs: 11
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 11
; Occupancy: 16
; WaveLimiterHint : 1
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object ; @__hip_cuid_
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0 ; 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 16
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z12testKernel4rPfS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z12testKernel4rPfS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 11
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
```
| 3,565 | 4,685 |
51 |
Convert the following CUDA host assembly code to AMD host assembly:
```cudaasm
.file "tmpxft_0009a3e2_00000000-6_testKernel4r.cudafe1.cpp"
.text
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z34__device_stub__Z12testKernel4rPfS_PfS_
.type _Z34__device_stub__Z12testKernel4rPfS_PfS_, @function
_Z34__device_stub__Z12testKernel4rPfS_PfS_:
.LFB2051:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z12testKernel4rPfS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z34__device_stub__Z12testKernel4rPfS_PfS_, .-_Z34__device_stub__Z12testKernel4rPfS_PfS_
.globl _Z12testKernel4rPfS_
.type _Z12testKernel4rPfS_, @function
_Z12testKernel4rPfS_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z34__device_stub__Z12testKernel4rPfS_PfS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z12testKernel4rPfS_, .-_Z12testKernel4rPfS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z12testKernel4rPfS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z12testKernel4rPfS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
```
|
```amdasm
.text
.file "testKernel4r.hip"
.globl _Z27__device_stub__testKernel4rPfS_ # -- Begin function _Z27__device_stub__testKernel4rPfS_
.type _Z27__device_stub__testKernel4rPfS_,@function
_Z27__device_stub__testKernel4rPfS_: # @_Z27__device_stub__testKernel4rPfS_
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $80, %rsp
.cfi_def_cfa_offset 128
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 24(%rsp), %rax
movq %rdi, (%rax)
leaq 16(%rsp), %rcx
movq %rsi, (%rcx)
leaq 64(%rsp), %rbx
movq %rax, (%rbx)
movq %rcx, 8(%rbx)
leaq 48(%rsp), %r14
leaq 32(%rsp), %r15
leaq 8(%rsp), %r12
movq %rsp, %r13
movq %r14, %rdi
movq %r15, %rsi
movq %r12, %rdx
movq %r13, %rcx
callq __hipPopCallConfiguration
movq (%r14), %rsi
movl 8(%r14), %edx
movq (%r15), %rcx
movl 8(%r15), %r8d
movl $_Z12testKernel4rPfS_, %edi
movq %rbx, %r9
pushq (%r13)
.cfi_adjust_cfa_offset 8
pushq (%r12)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $96, %rsp
.cfi_adjust_cfa_offset -96
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z27__device_stub__testKernel4rPfS_, .Lfunc_end0-_Z27__device_stub__testKernel4rPfS_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, %rdi
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12testKernel4rPfS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z12testKernel4rPfS_,@object # @_Z12testKernel4rPfS_
.section .rodata,"a",@progbits
.globl _Z12testKernel4rPfS_
.p2align 3, 0x0
_Z12testKernel4rPfS_:
.quad _Z27__device_stub__testKernel4rPfS_
.size _Z12testKernel4rPfS_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z12testKernel4rPfS_"
.size .L__unnamed_1, 21
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z27__device_stub__testKernel4rPfS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z12testKernel4rPfS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
```
| 1,818 | 2,010 |
56 |
Convert the following CUDA device assembly code to AMD device assembly:
```cudaasm
code for sm_80
Function : _Z7FW_CudaiPiS_j
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ;
S2R R5, SR_CTAID.X ;
S2R R2, SR_TID.X ;
S2R R0, SR_CTAID.Y ;
S2R R3, SR_TID.Y ;
IMAD R5, R5, c[0x0][0x0], R2 ;
ISETP.GE.U32.AND P0, PT, R5, c[0x0][0x178], PT ;
IMAD R0, R0, c[0x0][0x4], R3 ;
ISETP.GE.U32.OR P0, PT, R0, c[0x0][0x178], P0 ;
@P0 EXIT ;
HFMA2.MMA R9, -RZ, RZ, 0, 2.384185791015625e-07 ;
IMAD.MOV.U32 R6, RZ, RZ, c[0x0][0x178] ;
ULDC.64 UR4, c[0x0][0x118] ;
IMAD R2, R0, R6, c[0x0][0x160] ;
IMAD.WIDE.U32 R2, R2, R9, c[0x0][0x168] ;
LDG.E R4, [R2.64] ;
ISETP.NE.AND P0, PT, R4, 0x7fffffff, PT ;
@!P0 EXIT ;
IMAD R6, R6, c[0x0][0x160], R5 ;
IMAD.WIDE.U32 R2, R6, R9, c[0x0][0x168] ;
LDG.E R7, [R2.64] ;
ISETP.NE.AND P0, PT, R7, 0x7fffffff, PT ;
@!P0 EXIT ;
IMAD R0, R0, c[0x0][0x178], R5 ;
IMAD.WIDE.U32 R2, R0, R9, c[0x0][0x168] ;
LDG.E R8, [R2.64] ;
IADD3 R9, R4, R7, RZ ;
ISETP.GT.AND P0, PT, R8, R9, PT ;
@!P0 EXIT ;
LEA R4, P0, R6.reuse, c[0x0][0x170], 0x2 ;
STG.E [R2.64], R9 ;
LEA.HI.X R5, R6, c[0x0][0x174], RZ, 0x2, P0 ;
LDG.E R5, [R4.64] ;
LEA R6, P0, R0, c[0x0][0x170], 0x2 ;
LEA.HI.X R7, R0, c[0x0][0x174], RZ, 0x2, P0 ;
STG.E [R6.64], R5 ;
EXIT ;
BRA 0x250;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
```
|
```amdasm
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z7FW_CudaiPiS_j ; -- Begin function _Z7FW_CudaiPiS_j
.globl _Z7FW_CudaiPiS_j
.p2align 8
.type _Z7FW_CudaiPiS_j,@function
_Z7FW_CudaiPiS_j: ; @_Z7FW_CudaiPiS_j
; %bb.0:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s4, s[0:1], 0x18
v_bfe_u32 v1, v0, 10, 10
v_and_b32_e32 v4, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s3, s2, 16
s_and_b32 s2, s2, 0xffff
v_mad_u64_u32 v[2:3], null, s15, s3, v[1:2]
v_mad_u64_u32 v[0:1], null, s14, s2, v[4:5]
s_mov_b32 s2, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_max_u32_e32 v1, v2, v0
v_cmpx_gt_u32_e64 s4, v1
s_cbranch_execz .LBB0_5
; %bb.1:
s_clause 0x1
s_load_b32 s5, s[0:1], 0x0
s_load_b128 s[0:3], s[0:1], 0x8
v_mul_lo_u32 v3, v2, s4
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_mov_b32 v2, 0 :: v_dual_add_nc_u32 v1, s5, v3
v_lshlrev_b64 v[4:5], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v4, vcc_lo, s0, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s1, v5, vcc_lo
global_load_b32 v7, v[4:5], off
s_waitcnt vmcnt(0)
v_cmp_ne_u32_e32 vcc_lo, 0x7fffffff, v7
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_5
; %bb.2:
v_mad_u64_u32 v[4:5], null, s4, s5, v[0:1]
v_mov_b32_e32 v5, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[1:2], 2, v[4:5]
v_add_co_u32 v4, vcc_lo, s0, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v5, vcc_lo, s1, v2, vcc_lo
global_load_b32 v8, v[4:5], off
s_waitcnt vmcnt(0)
v_cmp_ne_u32_e32 vcc_lo, 0x7fffffff, v8
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_5
; %bb.3:
v_dual_mov_b32 v4, 0 :: v_dual_add_nc_u32 v3, v3, v0
v_add_nc_u32_e32 v0, v8, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[3:4]
v_add_co_u32 v5, vcc_lo, s0, v3
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v6, vcc_lo, s1, v4, vcc_lo
global_load_b32 v9, v[5:6], off
s_waitcnt vmcnt(0)
v_cmp_gt_i32_e32 vcc_lo, v9, v0
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_5
; %bb.4:
v_add_co_u32 v1, vcc_lo, s2, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s3, v2, vcc_lo
global_store_b32 v[5:6], v0, off
v_add_co_u32 v0, vcc_lo, s2, v3
global_load_b32 v2, v[1:2], off
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v4, vcc_lo
s_waitcnt vmcnt(0)
global_store_b32 v[0:1], v2, off
.LBB0_5:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z7FW_CudaiPiS_j
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 10
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z7FW_CudaiPiS_j, .Lfunc_end0-_Z7FW_CudaiPiS_j
; -- End function
.section .AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 384
; NumSgprs: 18
; NumVgprs: 10
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 10
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object ; @__hip_cuid_
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0 ; 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z7FW_CudaiPiS_j
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z7FW_CudaiPiS_j.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 10
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
```
| 837 | 3,259 |
57 |
Convert the following CUDA host assembly code to AMD host assembly:
```cudaasm
.file "tmpxft_00017643_00000000-6_fw_cuda.cudafe1.cpp"
.text
.globl _ZSt21ios_base_library_initv
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3807:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3807:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "\r\n"
.LC1:
.string "\t"
.LC2:
.string "\342\210\236"
.text
.globl _Z11printMatrixPij
.type _Z11printMatrixPij, @function
_Z11printMatrixPij:
.LFB3800:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $8, %rsp
.cfi_def_cfa_offset 64
movq %rdi, %r14
movl %esi, %ebp
movl $2, %edx
leaq .LC0(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl %ebp, %r13d
imull %ebp, %r13d
testl %r13d, %r13d
je .L3
movl %r13d, %r13d
movl $1, %ebx
leaq _ZSt4cout(%rip), %r12
leaq .LC1(%rip), %r15
jmp .L8
.L5:
movl $3, %edx
leaq .LC2(%rip), %rsi
movq %r12, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl $1, %edx
movq %r15, %rsi
movq %r12, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
.L6:
movl %ebx, %eax
movl $0, %edx
divl %ebp
testl %edx, %edx
je .L11
.L7:
leaq 1(%rbx), %rax
cmpq %r13, %rbx
je .L3
movq %rax, %rbx
.L8:
movl -4(%r14,%rbx,4), %esi
cmpl $2147483647, %esi
je .L5
movq %r12, %rdi
call _ZNSolsEi@PLT
movq %rax, %rdi
movl $1, %edx
movq %r15, %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
jmp .L6
.L11:
movl $2, %edx
leaq .LC0(%rip), %rsi
movq %r12, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
jmp .L7
.L3:
addq $8, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3800:
.size _Z11printMatrixPij, .-_Z11printMatrixPij
.globl _Z7getPathPiS_iij
.type _Z7getPathPiS_iij, @function
_Z7getPathPiS_iij:
.LFB3802:
.cfi_startproc
endbr64
movl $0, %eax
cmpl %ecx, %edx
je .L17
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $8, %rsp
.cfi_def_cfa_offset 48
movq %rdi, %r12
movl %ecx, %ebx
movl %r8d, %ebp
movl %edx, %eax
imull %r8d, %eax
leal (%rax,%rcx), %eax
movl (%rsi,%rax,4), %r13d
movl $2147483647, %eax
cmpl $-1, %r13d
je .L12
movl %r13d, %ecx
call _Z7getPathPiS_iij
cmpl $2147483647, %eax
je .L12
imull %ebp, %r13d
leal 0(%r13,%rbx), %edx
addl (%r12,%rdx,4), %eax
.L12:
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L17:
.cfi_restore 3
.cfi_restore 6
.cfi_restore 12
.cfi_restore 13
ret
.cfi_endproc
.LFE3802:
.size _Z7getPathPiS_iij, .-_Z7getPathPiS_iij
.globl _Z24checkSolutionCorrectnessPiS_S_j
.type _Z24checkSolutionCorrectnessPiS_S_j, @function
_Z24checkSolutionCorrectnessPiS_S_j:
.LFB3803:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $24, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 8(%rsp)
testl %ecx, %ecx
je .L24
movq %rsi, %r13
movq %rdx, %r14
movl %ecx, %ebp
movl $0, %r15d
movl $0, %r12d
.L22:
movl $0, %ebx
jmp .L23
.L26:
movl %eax, %ebx
.L23:
movl %ebp, %r8d
movl %ebx, %ecx
movl %r12d, %edx
movq %r14, %rsi
movq 8(%rsp), %rdi
call _Z7getPathPiS_iij
leal (%rbx,%r15), %edx
cmpl %eax, 0(%r13,%rdx,4)
jne .L25
leal 1(%rbx), %eax
cmpl %eax, %ebp
jne .L26
leal 1(%r12), %eax
addl %ebp, %r15d
cmpl %ebx, %r12d
je .L27
movl %eax, %r12d
jmp .L22
.L24:
movl $1, %eax
jmp .L20
.L25:
movl $0, %eax
.L20:
addq $24, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L27:
.cfi_restore_state
movl $1, %eax
jmp .L20
.cfi_endproc
.LFE3803:
.size _Z24checkSolutionCorrectnessPiS_S_j, .-_Z24checkSolutionCorrectnessPiS_S_j
.globl _Z30__device_stub__Z7FW_CudaiPiS_jiPiS_j
.type _Z30__device_stub__Z7FW_CudaiPiS_jiPiS_j, @function
_Z30__device_stub__Z7FW_CudaiPiS_jiPiS_j:
.LFB3829:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 28(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 24(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 24(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L33
.L29:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L34
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L33:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z7FW_CudaiPiS_j(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L29
.L34:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3829:
.size _Z30__device_stub__Z7FW_CudaiPiS_jiPiS_j, .-_Z30__device_stub__Z7FW_CudaiPiS_jiPiS_j
.globl _Z7FW_CudaiPiS_j
.type _Z7FW_CudaiPiS_j, @function
_Z7FW_CudaiPiS_j:
.LFB3830:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z7FW_CudaiPiS_jiPiS_j
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3830:
.size _Z7FW_CudaiPiS_j, .-_Z7FW_CudaiPiS_j
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC3:
.string "Neuspje\305\241no alociranje matrice D (error code %s)!\n"
.align 8
.LC4:
.string "Neuspje\305\241no alociranje matrice PI (error code %s)!\n"
.align 8
.LC5:
.string "Neuspje\305\241no kopiranje matrice D iz hosta u device (error code %s)!\n"
.align 8
.LC6:
.string "Neuspje\305\241no kopiranje matrice PI iz hosta u device (error code %s)!\n"
.section .rodata.str1.1
.LC11:
.string "CUDA kernel se pokre\304\207e sa "
.LC12:
.string " blokova i "
.LC13:
.string " threadova po bloku.\r\n"
.section .rodata.str1.8
.align 8
.LC14:
.string "Neuspje\305\241no pokrenuta kernel metoda (error code %s)!\n"
.align 8
.LC15:
.string "Neuspje\305\241no kopiranje matrice D iz devicea u host (error code %s)!\n"
.align 8
.LC16:
.string "Neuspje\305\241no kopiranje matrice PI iz devicea u host (error code %s)!\n"
.align 8
.LC17:
.string "Neuspje\305\241no dealociranje matrice D (error code %s)!\n"
.align 8
.LC18:
.string "Neuspje\305\241no dealociranje matrice PI (error code %s)!\n"
.align 8
.LC19:
.string "Neuspje\305\241no resetiranje devicea (zavr\305\241avanje sa CUDA FW, priprema za sljede\304\207e pokretanje)! error=%s\n"
.text
.globl _Z19Floyd_Warshall_CudaPiS_S_j
.type _Z19Floyd_Warshall_CudaPiS_S_j, @function
_Z19Floyd_Warshall_CudaPiS_S_j:
.LFB3801:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $56, %rsp
.cfi_def_cfa_offset 112
movq %rsi, %r15
movq %rdx, %r14
movl %ecx, %r12d
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movq $0, (%rsp)
movl %ecx, %r13d
imull %ecx, %r13d
salq $2, %r13
movq %rsp, %rdi
movq %r13, %rsi
call cudaMalloc@PLT
testl %eax, %eax
jne .L57
movq $0, 8(%rsp)
leaq 8(%rsp), %rdi
movq %r13, %rsi
call cudaMalloc@PLT
testl %eax, %eax
jne .L58
movl $1, %ecx
movq %r13, %rdx
movq %r15, %rsi
movq (%rsp), %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L59
movl $1, %ecx
movq %r13, %rdx
movq %r14, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L60
movl %r12d, %eax
pxor %xmm0, %xmm0
cvtsi2ssq %rax, %xmm0
mulss .LC7(%rip), %xmm0
movaps %xmm0, %xmm3
movss .LC20(%rip), %xmm2
movaps %xmm0, %xmm1
andps %xmm2, %xmm1
movss .LC8(%rip), %xmm4
ucomiss %xmm1, %xmm4
jbe .L44
cvttss2sil %xmm0, %eax
pxor %xmm1, %xmm1
cvtsi2ssl %eax, %xmm1
cmpnless %xmm1, %xmm3
movss .LC10(%rip), %xmm4
andps %xmm4, %xmm3
addss %xmm1, %xmm3
andnps %xmm0, %xmm2
orps %xmm2, %xmm3
.L44:
cvttss2sil %xmm3, %ebp
movl $27, %edx
leaq .LC11(%rip), %rsi
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl %ebp, %esi
imull %ebp, %esi
movq %rbx, %rdi
call _ZNSolsEi@PLT
movq %rax, %rbx
movl $11, %edx
leaq .LC12(%rip), %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl $1024, %esi
movq %rbx, %rdi
call _ZNSolsEi@PLT
movq %rax, %rdi
movl $22, %edx
leaq .LC13(%rip), %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
testl %r12d, %r12d
je .L45
movl $0, %ebx
jmp .L48
.L57:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC3(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L58:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC4(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L59:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC5(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L60:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC6(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L46:
call cudaGetLastError@PLT
testl %eax, %eax
jne .L61
call cudaThreadSynchronize@PLT
addl $1, %ebx
cmpl %r12d, %ebx
je .L45
.L48:
movl $32, 28(%rsp)
movl $32, 32(%rsp)
movl %ebp, 16(%rsp)
movl %ebp, 20(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L46
movl %r12d, %ecx
movq 8(%rsp), %rdx
movq (%rsp), %rsi
movl %ebx, %edi
call _Z30__device_stub__Z7FW_CudaiPiS_jiPiS_j
jmp .L46
.L61:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC14(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L45:
movl $2, %ecx
movq %r13, %rdx
movq (%rsp), %rsi
movq %r15, %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L62
movl $2, %ecx
movq %r13, %rdx
movq 8(%rsp), %rsi
movq %r14, %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L63
movq (%rsp), %rdi
call cudaFree@PLT
testl %eax, %eax
jne .L64
movq 8(%rsp), %rdi
call cudaFree@PLT
testl %eax, %eax
jne .L65
call cudaDeviceReset@PLT
testl %eax, %eax
jne .L66
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L67
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L62:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC15(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L63:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC16(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L64:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC17(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L65:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC18(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L66:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC19(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L67:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3801:
.size _Z19Floyd_Warshall_CudaPiS_S_j, .-_Z19Floyd_Warshall_CudaPiS_S_j
.section .rodata.str1.1
.LC21:
.string "_Z7FW_CudaiPiS_j"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3832:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC21(%rip), %rdx
movq %rdx, %rcx
leaq _Z7FW_CudaiPiS_j(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3832:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .rodata.str1.1
.LC22:
.string "graphFile.txt"
.LC23:
.string "output_cuda.txt"
.LC24:
.string "V = "
.LC25:
.string ", E = "
.LC27:
.string "|V| = "
.LC28:
.string ", |E| = "
.LC29:
.string "\r\n\r\n"
.section .rodata.str1.8
.align 8
.LC30:
.string "Vrijeme izvr\305\241avanja Floyd-Warshall algoritma: "
.section .rodata.str1.1
.LC31:
.string "s.\r\n"
.section .rodata.str1.8
.align 8
.LC32:
.string "Svi najkra\304\207i putevi su to\304\215no izra\304\215unati!\r\n"
.align 8
.LC33:
.string "Najkra\304\207i putevi nisu to\304\215no izra\304\215unati.\r\n"
.text
.globl main
.type main, @function
main:
.LFB3804:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA3804
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $1096, %rsp
.cfi_def_cfa_offset 1152
movq %fs:40, %rax
movq %rax, 1080(%rsp)
xorl %eax, %eax
leaq 560(%rsp), %rbx
movq %rbx, %rdi
.LEHB0:
call _ZNSt14basic_ifstreamIcSt11char_traitsIcEEC1Ev@PLT
.LEHE0:
movl $8, %edx
leaq .LC22(%rip), %rsi
movq %rbx, %rdi
.LEHB1:
call _ZNSt14basic_ifstreamIcSt11char_traitsIcEE4openEPKcSt13_Ios_Openmode@PLT
leaq 48(%rsp), %rdi
call _ZNSt14basic_ofstreamIcSt11char_traitsIcEEC1Ev@PLT
.LEHE1:
leaq 48(%rsp), %rdi
movl $16, %edx
leaq .LC23(%rip), %rsi
.LEHB2:
call _ZNSt14basic_ofstreamIcSt11char_traitsIcEE4openEPKcSt13_Ios_Openmode@PLT
leaq 28(%rsp), %rsi
movq %rbx, %rdi
call _ZNSi10_M_extractIjEERSiRT_@PLT
movq %rax, %rdi
leaq 32(%rsp), %rsi
call _ZNSi10_M_extractIjEERSiRT_@PLT
leaq .LC24(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl 28(%rsp), %esi
call _ZNSo9_M_insertImEERSoT_@PLT
movq %rax, %rdi
leaq .LC25(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl 32(%rsp), %esi
call _ZNSo9_M_insertImEERSoT_@PLT
movq %rax, %rdi
leaq .LC0(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movl 28(%rsp), %eax
imull %eax, %eax
movl %eax, %r15d
movl %eax, 4(%rsp)
movl %eax, %r13d
leaq 0(,%r13,4), %rbx
movq %rbx, 8(%rsp)
movq %rbx, %rdi
call malloc@PLT
movq %rax, %rbp
movq %rbx, %rdi
call malloc@PLT
movq %rax, %r14
movq %rbx, %rdi
call malloc@PLT
movq %rax, %r12
testl %r15d, %r15d
je .L71
leaq 0(%rbp,%rbx), %rdx
cmpq %rdx, %rbp
je .L72
movq %rbp, %rax
.L73:
movl $2147483647, (%rax)
addq $4, %rax
cmpq %rax, %rdx
jne .L73
.L72:
movq 8(%rsp), %rax
leaq (%r12,%rax), %rdx
cmpq %rdx, %r12
je .L71
movq %r12, %rax
.L74:
movl $-1, (%rax)
addq $4, %rax
cmpq %rax, %rdx
jne .L74
.L71:
cmpl $0, 32(%rsp)
je .L75
movl $0, %ebx
leaq 36(%rsp), %r15
jmp .L77
.L104:
movq %rax, %rdi
leaq 40(%rsp), %rsi
call _ZNSirsERi@PLT
movq %rax, %rdi
leaq 44(%rsp), %rsi
call _ZNSirsERi@PLT
movl 36(%rsp), %eax
movl 40(%rsp), %edx
movl %eax, %ecx
imull 28(%rsp), %ecx
leal (%rcx,%rdx), %ecx
movl 44(%rsp), %esi
movl %esi, 0(%rbp,%rcx,4)
cmpl %edx, %eax
je .L76
movl %eax, (%r12,%rcx,4)
.L76:
addl $1, %ebx
cmpl 32(%rsp), %ebx
jnb .L75
.L77:
leaq 560(%rsp), %rdi
movq %r15, %rsi
call _ZNSirsERi@PLT
jmp .L104
.L75:
movl 28(%rsp), %esi
testl %esi, %esi
je .L78
leal 1(%rsi), %edi
movl $0, %edx
movl $0, %eax
.L79:
movl %edx, %ecx
movl $0, 0(%rbp,%rcx,4)
addl $1, %eax
addl %edi, %edx
cmpl %esi, %eax
jne .L79
.L78:
movq 8(%rsp), %rcx
movq %rcx, %rdx
movq %rbp, %rsi
movq %r14, %rdi
call __memcpy_chk@PLT
call clock@PLT
movq %rax, %rbx
movl 28(%rsp), %ecx
movq %r12, %rdx
movq %r14, %rsi
movq %rbp, %rdi
call _Z19Floyd_Warshall_CudaPiS_S_j
call clock@PLT
subq %rbx, %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
divsd .LC26(%rip), %xmm0
movsd %xmm0, 8(%rsp)
leaq 48(%rsp), %rdi
leaq .LC27(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl 28(%rsp), %esi
call _ZNSo9_M_insertImEERSoT_@PLT
movq %rax, %rdi
leaq .LC28(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl 32(%rsp), %esi
call _ZNSo9_M_insertImEERSoT_@PLT
movq %rax, %rdi
leaq .LC29(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
cmpl $0, 4(%rsp)
je .L80
movl $0, %ebx
leaq 48(%rsp), %r15
jmp .L84
.L105:
movl $2, %edx
leaq .LC0(%rip), %rsi
movq %r15, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
jmp .L81
.L106:
movq %rax, %rdi
movl $1, %edx
leaq .LC1(%rip), %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
jmp .L83
.L82:
movl $3, %edx
leaq .LC2(%rip), %rsi
movq %r15, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl $1, %edx
leaq .LC1(%rip), %rsi
movq %r15, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
.L83:
addq $1, %rbx
cmpq %rbx, %r13
je .L80
.L84:
movl %ebx, %eax
movl $0, %edx
divl 28(%rsp)
testl %edx, %edx
je .L105
.L81:
movl (%r14,%rbx,4), %esi
cmpl $2147483647, %esi
je .L82
movq %r15, %rdi
call _ZNSolsEi@PLT
jmp .L106
.L80:
leaq 48(%rsp), %rdi
leaq .LC29(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
cmpl $0, 4(%rsp)
je .L85
movl $0, %ebx
leaq 48(%rsp), %r15
jmp .L87
.L86:
movl (%r12,%rbx,4), %esi
movq %r15, %rdi
call _ZNSolsEi@PLT
movq %rax, %rdi
movl $1, %edx
leaq .LC1(%rip), %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
addq $1, %rbx
cmpq %rbx, %r13
je .L85
.L87:
movl %ebx, %eax
movl $0, %edx
divl 28(%rsp)
testl %edx, %edx
jne .L86
movl $2, %edx
leaq .LC0(%rip), %rsi
movq %r15, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
jmp .L86
.L85:
leaq .LC30(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movsd 8(%rsp), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
leaq .LC31(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movl 28(%rsp), %ecx
movq %r12, %rdx
movq %r14, %rsi
movq %rbp, %rdi
call _Z24checkSolutionCorrectnessPiS_S_j
testb %al, %al
je .L88
leaq .LC32(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
jmp .L89
.L88:
leaq .LC33(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
.L89:
leaq 560(%rsp), %rdi
call _ZNSt14basic_ifstreamIcSt11char_traitsIcEE5closeEv@PLT
leaq 48(%rsp), %rdi
call _ZNSt14basic_ofstreamIcSt11char_traitsIcEE5closeEv@PLT
.LEHE2:
movq %rbp, %rdi
call free@PLT
movq %r14, %rdi
call free@PLT
movq %r12, %rdi
call free@PLT
leaq 48(%rsp), %rdi
call _ZNSt14basic_ofstreamIcSt11char_traitsIcEED1Ev@PLT
leaq 560(%rsp), %rdi
call _ZNSt14basic_ifstreamIcSt11char_traitsIcEED1Ev@PLT
movq 1080(%rsp), %rax
subq %fs:40, %rax
jne .L107
movl $0, %eax
addq $1096, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L95:
.cfi_restore_state
endbr64
movq %rax, %rbx
leaq 48(%rsp), %rdi
call _ZNSt14basic_ofstreamIcSt11char_traitsIcEED1Ev@PLT
.L91:
leaq 560(%rsp), %rdi
call _ZNSt14basic_ifstreamIcSt11char_traitsIcEED1Ev@PLT
movq 1080(%rsp), %rax
subq %fs:40, %rax
je .L92
call __stack_chk_fail@PLT
.L94:
endbr64
movq %rax, %rbx
jmp .L91
.L92:
movq %rbx, %rdi
.LEHB3:
call _Unwind_Resume@PLT
.LEHE3:
.L107:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3804:
.globl __gxx_personality_v0
.section .gcc_except_table,"a",@progbits
.LLSDA3804:
.byte 0xff
.byte 0xff
.byte 0x1
.uleb128 .LLSDACSE3804-.LLSDACSB3804
.LLSDACSB3804:
.uleb128 .LEHB0-.LFB3804
.uleb128 .LEHE0-.LEHB0
.uleb128 0
.uleb128 0
.uleb128 .LEHB1-.LFB3804
.uleb128 .LEHE1-.LEHB1
.uleb128 .L94-.LFB3804
.uleb128 0
.uleb128 .LEHB2-.LFB3804
.uleb128 .LEHE2-.LEHB2
.uleb128 .L95-.LFB3804
.uleb128 0
.uleb128 .LEHB3-.LFB3804
.uleb128 .LEHE3-.LEHB3
.uleb128 0
.uleb128 0
.LLSDACSE3804:
.text
.size main, .-main
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC7:
.long 1023410176
.align 4
.LC8:
.long 1258291200
.align 4
.LC10:
.long 1065353216
.align 4
.LC20:
.long 2147483647
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC26:
.long 0
.long 1093567616
.hidden DW.ref.__gxx_personality_v0
.weak DW.ref.__gxx_personality_v0
.section .data.rel.local.DW.ref.__gxx_personality_v0,"awG",@progbits,DW.ref.__gxx_personality_v0,comdat
.align 8
.type DW.ref.__gxx_personality_v0, @object
.size DW.ref.__gxx_personality_v0, 8
DW.ref.__gxx_personality_v0:
.quad __gxx_personality_v0
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
```
|
```amdasm
.text
.file "fw_cuda.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z11printMatrixPij # -- Begin function _Z11printMatrixPij
.type _Z11printMatrixPij,@function
_Z11printMatrixPij: # @_Z11printMatrixPij
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl %esi, %ebx
movq %rdi, %r14
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $2, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl %ebx, %eax
imull %ebx, %eax
testl %eax, %eax
je .LBB0_8
# %bb.1: # %.lr.ph.preheader
movl %eax, %r13d
xorl %r15d, %r15d
.LBB0_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl (%r14,%r15,4), %esi
cmpl $2147483647, %esi # imm = 0x7FFFFFFF
jne .LBB0_3
# %bb.4: # in Loop: Header=BB0_2 Depth=1
movl $_ZSt4cout, %r12d
movl $_ZSt4cout, %edi
movl $.L.str.2, %esi
movl $3, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
jmp .LBB0_5
.LBB0_3: # in Loop: Header=BB0_2 Depth=1
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movq %rax, %r12
.LBB0_5: # in Loop: Header=BB0_2 Depth=1
movl $.L.str.1, %esi
movl $1, %edx
movq %r12, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
incq %r15
movl %r15d, %eax
xorl %edx, %edx
divl %ebx
testl %edx, %edx
jne .LBB0_7
# %bb.6: # in Loop: Header=BB0_2 Depth=1
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $2, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.LBB0_7: # in Loop: Header=BB0_2 Depth=1
cmpq %r15, %r13
jne .LBB0_2
.LBB0_8: # %._crit_edge
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z11printMatrixPij, .Lfunc_end0-_Z11printMatrixPij
.cfi_endproc
# -- End function
.globl _Z22__device_stub__FW_CudaiPiS_j # -- Begin function _Z22__device_stub__FW_CudaiPiS_j
.type _Z22__device_stub__FW_CudaiPiS_j,@function
_Z22__device_stub__FW_CudaiPiS_j: # @_Z22__device_stub__FW_CudaiPiS_j
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $112, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 12(%rsp), %rax
movl %edi, (%rax)
leaq 40(%rsp), %rdi
movq %rsi, (%rdi)
leaq 32(%rsp), %rsi
movq %rdx, (%rsi)
leaq 8(%rsp), %rdx
movl %ecx, (%rdx)
leaq 80(%rsp), %rbx
movq %rax, (%rbx)
movq %rdi, 8(%rbx)
movq %rsi, 16(%rbx)
movq %rdx, 24(%rbx)
leaq 64(%rsp), %r14
leaq 48(%rsp), %r15
leaq 24(%rsp), %r12
leaq 16(%rsp), %r13
movq %r14, %rdi
movq %r15, %rsi
movq %r12, %rdx
movq %r13, %rcx
callq __hipPopCallConfiguration
movq (%r14), %rsi
movl 8(%r14), %edx
movq (%r15), %rcx
movl 8(%r15), %r8d
movl $_Z7FW_CudaiPiS_j, %edi
movq %rbx, %r9
pushq (%r13)
.cfi_adjust_cfa_offset 8
pushq (%r12)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $128, %rsp
.cfi_adjust_cfa_offset -128
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z22__device_stub__FW_CudaiPiS_j, .Lfunc_end1-_Z22__device_stub__FW_CudaiPiS_j
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function _Z19Floyd_Warshall_CudaPiS_S_j
.LCPI2_0:
.long 0x3d000000 # float 0.03125
.text
.globl _Z19Floyd_Warshall_CudaPiS_S_j
.type _Z19Floyd_Warshall_CudaPiS_S_j,@function
_Z19Floyd_Warshall_CudaPiS_S_j: # @_Z19Floyd_Warshall_CudaPiS_S_j
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $24, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %ecx, %ebp
movq %rdx, %r14
movq %rsi, %r15
movl %ecx, %ebx
imull %ebx, %ebx
leaq 8(%rsp), %rdi
movq $0, (%rdi)
shlq $2, %rbx
movq %rbx, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB2_1
# %bb.3:
movq %rsp, %rdi
movq $0, (%rdi)
movq %rbx, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB2_4
# %bb.5:
movq 8(%rsp), %rdi
movq %r15, %rsi
movq %rbx, %rdx
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB2_6
# %bb.7:
movq (%rsp), %rdi
movq %r14, 16(%rsp) # 8-byte Spill
movq %r14, %rsi
movq %rbx, %rdx
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB2_8
# %bb.9:
movl %ebp, %eax
cvtsi2ss %rax, %xmm0
mulss .LCPI2_0(%rip), %xmm0
callq ceilf@PLT
cvttss2si %xmm0, %r12d
movl $_ZSt4cout, %edi
movl $.L.str.7, %esi
movl $27, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl %r12d, %esi
imull %r12d, %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movq %rax, %r14
movl $.L.str.8, %esi
movl $11, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq %r14, %rdi
movl $1024, %esi # imm = 0x400
callq _ZNSolsEi
movl $.L.str.9, %esi
movl $22, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
testl %ebp, %ebp
je .LBB2_16
# %bb.10: # %.lr.ph
movl %r12d, %eax
movq %rax, %r12
shlq $32, %r12
orq %rax, %r12
xorl %r13d, %r13d
movabsq $137438953504, %r14 # imm = 0x2000000020
.LBB2_11: # =>This Inner Loop Header: Depth=1
movq %r12, %rdi
movl $1, %esi
movq %r14, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_13
# %bb.12: # in Loop: Header=BB2_11 Depth=1
movq 8(%rsp), %rsi
movq (%rsp), %rdx
movl %r13d, %edi
movl %ebp, %ecx
callq _Z22__device_stub__FW_CudaiPiS_j
.LBB2_13: # in Loop: Header=BB2_11 Depth=1
callq hipGetLastError
testl %eax, %eax
jne .LBB2_14
# %bb.15: # in Loop: Header=BB2_11 Depth=1
callq hipDeviceSynchronize
incl %r13d
cmpl %r13d, %ebp
jne .LBB2_11
.LBB2_16: # %._crit_edge
movq 8(%rsp), %rsi
movq %r15, %rdi
movq %rbx, %rdx
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB2_17
# %bb.18:
movq (%rsp), %rsi
movq 16(%rsp), %rdi # 8-byte Reload
movq %rbx, %rdx
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB2_19
# %bb.20:
movq 8(%rsp), %rdi
callq hipFree
testl %eax, %eax
jne .LBB2_21
# %bb.22:
movq (%rsp), %rdi
callq hipFree
testl %eax, %eax
jne .LBB2_23
# %bb.24:
callq hipDeviceReset
testl %eax, %eax
jne .LBB2_25
# %bb.26:
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB2_14:
.cfi_def_cfa_offset 80
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.10, %esi
.LBB2_2:
movq %rbx, %rdi
movq %rax, %rdx
xorl %eax, %eax
callq fprintf
movl $1, %edi
callq exit
.LBB2_1:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.3, %esi
jmp .LBB2_2
.LBB2_4:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.4, %esi
jmp .LBB2_2
.LBB2_6:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.5, %esi
jmp .LBB2_2
.LBB2_8:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.6, %esi
jmp .LBB2_2
.LBB2_17:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.11, %esi
jmp .LBB2_2
.LBB2_19:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.12, %esi
jmp .LBB2_2
.LBB2_21:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.13, %esi
jmp .LBB2_2
.LBB2_23:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.14, %esi
jmp .LBB2_2
.LBB2_25:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.15, %esi
jmp .LBB2_2
.Lfunc_end2:
.size _Z19Floyd_Warshall_CudaPiS_S_j, .Lfunc_end2-_Z19Floyd_Warshall_CudaPiS_S_j
.cfi_endproc
# -- End function
.globl _Z7getPathPiS_iij # -- Begin function _Z7getPathPiS_iij
.type _Z7getPathPiS_iij,@function
_Z7getPathPiS_iij: # @_Z7getPathPiS_iij
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
xorl %r15d, %r15d
cmpl %ecx, %edx
je .LBB3_4
# %bb.1:
movl %r8d, %r14d
movl %ecx, %ebp
movl %r8d, %eax
imull %edx, %eax
addl %ecx, %eax
movl (%rsi,%rax,4), %r12d
movl $2147483647, %r15d # imm = 0x7FFFFFFF
cmpl $-1, %r12d
je .LBB3_4
# %bb.2:
movq %rdi, %rbx
movl %r12d, %ecx
movl %r14d, %r8d
callq _Z7getPathPiS_iij
cmpl $2147483647, %eax # imm = 0x7FFFFFFF
je .LBB3_4
# %bb.3:
imull %r14d, %r12d
addl %ebp, %r12d
addl (%rbx,%r12,4), %eax
movl %eax, %r15d
.LBB3_4:
movl %r15d, %eax
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size _Z7getPathPiS_iij, .Lfunc_end3-_Z7getPathPiS_iij
.cfi_endproc
# -- End function
.globl _Z24checkSolutionCorrectnessPiS_S_j # -- Begin function _Z24checkSolutionCorrectnessPiS_S_j
.type _Z24checkSolutionCorrectnessPiS_S_j,@function
_Z24checkSolutionCorrectnessPiS_S_j: # @_Z24checkSolutionCorrectnessPiS_S_j
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $24, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rdx, 16(%rsp) # 8-byte Spill
movq %rsi, 8(%rsp) # 8-byte Spill
testl %ecx, %ecx
je .LBB4_1
# %bb.2: # %.preheader.preheader
movl %ecx, %ebx
movq %rdi, %r12
movl %ecx, %r14d
xorl %r15d, %r15d
xorl %eax, %eax
xorl %ebp, %ebp
.LBB4_3: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB4_5 Depth 2
movq %rax, (%rsp) # 8-byte Spill
xorl %r13d, %r13d
.LBB4_5: # Parent Loop BB4_3 Depth=1
# => This Inner Loop Header: Depth=2
movq %r12, %rdi
movq 16(%rsp), %rsi # 8-byte Reload
movl %ebp, %edx
movl %r13d, %ecx
movl %ebx, %r8d
callq _Z7getPathPiS_iij
leal (%r15,%r13), %ecx
movq 8(%rsp), %rdx # 8-byte Reload
cmpl (%rdx,%rcx,4), %eax
jne .LBB4_6
# %bb.4: # in Loop: Header=BB4_5 Depth=2
incq %r13
cmpq %r13, %r14
jne .LBB4_5
# %bb.7: # in Loop: Header=BB4_3 Depth=1
incl %ebp
cmpl %ebx, %ebp
setae %al
addq %r14, %r15
cmpl %r14d, %ebp
jne .LBB4_3
jmp .LBB4_8
.LBB4_6:
movq (%rsp), %rax # 8-byte Reload
jmp .LBB4_8
.LBB4_1:
movb $1, %al
.LBB4_8: # %.thread
andb $1, %al
# kill: def $al killed $al killed $rax
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end4:
.size _Z24checkSolutionCorrectnessPiS_S_j, .Lfunc_end4-_Z24checkSolutionCorrectnessPiS_S_j
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI5_0:
.quad 0x412e848000000000 # double 1.0E+6
.text
.globl main
.type main,@function
main: # @main
.Lfunc_begin0:
.cfi_startproc
.cfi_personality 3, __gxx_personality_v0
.cfi_lsda 3, .Lexception0
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $1080, %rsp # imm = 0x438
.cfi_def_cfa_offset 1136
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
leaq 560(%rsp), %rbx
movq %rbx, %rdi
callq _ZNSt14basic_ifstreamIcSt11char_traitsIcEEC1Ev
.Ltmp0:
movl $.L.str.16, %esi
movq %rbx, %rdi
movl $8, %edx
callq _ZNSt14basic_ifstreamIcSt11char_traitsIcEE4openEPKcSt13_Ios_Openmode
.Ltmp1:
# %bb.1:
.Ltmp3:
leaq 48(%rsp), %rdi
callq _ZNSt14basic_ofstreamIcSt11char_traitsIcEEC1Ev
.Ltmp4:
# %bb.2:
.Ltmp6:
leaq 48(%rsp), %rdi
movl $.L.str.17, %esi
movl $16, %edx
callq _ZNSt14basic_ofstreamIcSt11char_traitsIcEE4openEPKcSt13_Ios_Openmode
.Ltmp7:
# %bb.3:
.Ltmp8:
leaq 560(%rsp), %rdi
movq %rsp, %rsi
callq _ZNSi10_M_extractIjEERSiRT_
.Ltmp9:
# %bb.4: # %_ZNSirsERj.exit
.Ltmp10:
leaq 4(%rsp), %rsi
movq %rax, %rdi
callq _ZNSi10_M_extractIjEERSiRT_
.Ltmp11:
# %bb.5: # %_ZNSirsERj.exit69
.Ltmp12:
movl $_ZSt4cout, %edi
movl $.L.str.18, %esi
movl $4, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp13:
# %bb.6: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit
movl (%rsp), %esi
.Ltmp14:
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertImEERSoT_
.Ltmp15:
# %bb.7: # %_ZNSolsEj.exit
.Ltmp16:
movq %rax, %rbx
movl $.L.str.19, %esi
movl $6, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp17:
# %bb.8: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit70
movl 4(%rsp), %esi
.Ltmp18:
movq %rbx, %rdi
callq _ZNSo9_M_insertImEERSoT_
.Ltmp19:
# %bb.9: # %_ZNSolsEj.exit71
.Ltmp20:
movl $.L.str, %esi
movl $2, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp21:
# %bb.10: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit72
movl (%rsp), %r13d
movl %r13d, %r14d
imull %r14d, %r14d
leaq (,%r14,4), %r12
movq %r12, %rdi
callq malloc
movq %rax, %rbx
movq %r12, %rdi
callq malloc
movq %rax, 16(%rsp) # 8-byte Spill
movq %r12, %rdi
callq malloc
movq %rax, 8(%rsp) # 8-byte Spill
movq %r14, 24(%rsp) # 8-byte Spill
testl %r14d, %r14d
je .LBB5_14
# %bb.11:
xorl %eax, %eax
.LBB5_12: # %.lr.ph.i.i.i.i
# =>This Inner Loop Header: Depth=1
movl $2147483647, (%rbx,%rax) # imm = 0x7FFFFFFF
addq $4, %rax
cmpq %rax, %r12
jne .LBB5_12
# %bb.13: # %_ZSt6fill_nIPijiET_S1_T0_RKT1_.exit
movq 8(%rsp), %rdi # 8-byte Reload
movl $255, %esi
movq %r12, %rdx
callq memset@PLT
.LBB5_14: # %_ZSt6fill_nIPijiET_S1_T0_RKT1_.exit77
cmpl $0, 4(%rsp)
je .LBB5_22
# %bb.15: # %.lr.ph.preheader
xorl %ebp, %ebp
leaq 40(%rsp), %r14
leaq 36(%rsp), %r15
.LBB5_16: # %.lr.ph
# =>This Inner Loop Header: Depth=1
.Ltmp23:
leaq 560(%rsp), %rdi
leaq 44(%rsp), %rsi
callq _ZNSirsERi
.Ltmp24:
# %bb.17: # in Loop: Header=BB5_16 Depth=1
.Ltmp25:
movq %rax, %rdi
movq %r14, %rsi
callq _ZNSirsERi
.Ltmp26:
# %bb.18: # in Loop: Header=BB5_16 Depth=1
.Ltmp27:
movq %rax, %rdi
movq %r15, %rsi
callq _ZNSirsERi
.Ltmp28:
# %bb.19: # in Loop: Header=BB5_16 Depth=1
movl 36(%rsp), %edx
movl 44(%rsp), %eax
movl (%rsp), %r13d
movl %r13d, %ecx
imull %eax, %ecx
movl 40(%rsp), %esi
addl %esi, %ecx
movl %edx, (%rbx,%rcx,4)
cmpl %esi, %eax
je .LBB5_21
# %bb.20: # in Loop: Header=BB5_16 Depth=1
movq 8(%rsp), %rdx # 8-byte Reload
movl %eax, (%rdx,%rcx,4)
.LBB5_21: # in Loop: Header=BB5_16 Depth=1
incl %ebp
cmpl 4(%rsp), %ebp
jb .LBB5_16
.LBB5_22: # %.preheader
testl %r13d, %r13d
je .LBB5_25
# %bb.23: # %.lr.ph98
movl %r13d, %eax
incl %r13d
xorl %ecx, %ecx
.LBB5_24: # =>This Inner Loop Header: Depth=1
movl %ecx, %edx
movl $0, (%rbx,%rdx,4)
addl %r13d, %ecx
decq %rax
jne .LBB5_24
.LBB5_25: # %._crit_edge
movq 16(%rsp), %r14 # 8-byte Reload
movq %r14, %rdi
movq %rbx, %rsi
movq %r12, %rdx
callq memcpy@PLT
callq clock
movq %rax, %r15
movl (%rsp), %ecx
.Ltmp30:
movq %r14, %rsi
movq 8(%rsp), %rdx # 8-byte Reload
callq _Z19Floyd_Warshall_CudaPiS_S_j
.Ltmp31:
# %bb.26:
callq clock
movq %rax, %r13
.Ltmp33:
leaq 48(%rsp), %rdi
movl $.L.str.20, %esi
movl $6, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp34:
# %bb.27: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit78
movl (%rsp), %esi
.Ltmp35:
leaq 48(%rsp), %rbp
movq %rbp, %rdi
callq _ZNSo9_M_insertImEERSoT_
.Ltmp36:
# %bb.28: # %_ZNSolsEj.exit79
.Ltmp37:
movq %rax, %r14
movl $.L.str.21, %esi
movl $8, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp38:
# %bb.29: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit80
movl 4(%rsp), %esi
.Ltmp39:
movq %r14, %rdi
callq _ZNSo9_M_insertImEERSoT_
.Ltmp40:
# %bb.30: # %_ZNSolsEj.exit81
.Ltmp41:
movl $.L.str.22, %esi
movl $4, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp42:
# %bb.31: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit82.preheader
cmpq $0, 24(%rsp) # 8-byte Folded Reload
je .LBB5_40
# %bb.32: # %.lr.ph100.preheader
xorl %r12d, %r12d
.LBB5_33: # %.lr.ph100
# =>This Inner Loop Header: Depth=1
movl %r12d, %eax
xorl %edx, %edx
divl (%rsp)
testl %edx, %edx
jne .LBB5_35
# %bb.34: # in Loop: Header=BB5_33 Depth=1
.Ltmp43:
movl $.L.str, %esi
movl $2, %edx
movq %rbp, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp44:
.LBB5_35: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit84
# in Loop: Header=BB5_33 Depth=1
movq 16(%rsp), %rax # 8-byte Reload
movl (%rax,%r12,4), %esi
cmpl $2147483647, %esi # imm = 0x7FFFFFFF
jne .LBB5_37
# %bb.36: # in Loop: Header=BB5_33 Depth=1
.Ltmp47:
movl $.L.str.2, %esi
movl $3, %edx
movq %rbp, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp48:
movq %rbp, %rax
jmp .LBB5_38
.LBB5_37: # in Loop: Header=BB5_33 Depth=1
.Ltmp45:
movq %rbp, %rdi
callq _ZNSolsEi
.Ltmp46:
.LBB5_38: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit86.invoke
# in Loop: Header=BB5_33 Depth=1
.Ltmp49:
movl $.L.str.1, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp50:
# %bb.39: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit85
# in Loop: Header=BB5_33 Depth=1
incq %r12
cmpq %r12, 24(%rsp) # 8-byte Folded Reload
jne .LBB5_33
.LBB5_40: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit82._crit_edge
.Ltmp52:
leaq 48(%rsp), %rdi
movl $.L.str.22, %esi
movl $4, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp53:
movq 8(%rsp), %r12 # 8-byte Reload
# %bb.41: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit83.preheader
movq %r15, %rbp
cmpq $0, 24(%rsp) # 8-byte Folded Reload
je .LBB5_48
# %bb.42: # %.lr.ph102.preheader
xorl %r14d, %r14d
leaq 48(%rsp), %r15
.LBB5_43: # %.lr.ph102
# =>This Inner Loop Header: Depth=1
movl %r14d, %eax
xorl %edx, %edx
divl (%rsp)
testl %edx, %edx
jne .LBB5_45
# %bb.44: # in Loop: Header=BB5_43 Depth=1
.Ltmp54:
movl $.L.str, %esi
movl $2, %edx
movq %r15, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp55:
.LBB5_45: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit89
# in Loop: Header=BB5_43 Depth=1
movl (%r12,%r14,4), %esi
.Ltmp56:
movq %r15, %rdi
callq _ZNSolsEi
.Ltmp57:
# %bb.46: # in Loop: Header=BB5_43 Depth=1
.Ltmp58:
movl $.L.str.1, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp59:
# %bb.47: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit90
# in Loop: Header=BB5_43 Depth=1
incq %r14
cmpq %r14, 24(%rsp) # 8-byte Folded Reload
jne .LBB5_43
.LBB5_48: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit83._crit_edge
.Ltmp61:
movl $_ZSt4cout, %edi
movl $.L.str.23, %esi
movl $47, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp62:
# %bb.49: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit88
.Ltmp63:
subq %rbp, %r13
cvtsi2sd %r13, %xmm0
divsd .LCPI5_0(%rip), %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
.Ltmp64:
# %bb.50: # %_ZNSolsEd.exit
.Ltmp65:
movl $.L.str.24, %esi
movl $4, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp66:
# %bb.51: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit91
movl (%rsp), %ecx
movq %rbx, %rdi
movq 16(%rsp), %rsi # 8-byte Reload
movq %r12, %rdx
callq _Z24checkSolutionCorrectnessPiS_S_j
movl $.L.str.25, %ecx
movl $.L.str.26, %esi
testb %al, %al
cmovneq %rcx, %rsi
movzbl %al, %eax
leaq 43(,%rax,2), %rdx
.Ltmp67:
movl $_ZSt4cout, %edi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp68:
# %bb.52: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit92
.Ltmp69:
leaq 560(%rsp), %rdi
callq _ZNSt14basic_ifstreamIcSt11char_traitsIcEE5closeEv
.Ltmp70:
# %bb.53:
.Ltmp71:
leaq 48(%rsp), %rdi
callq _ZNSt14basic_ofstreamIcSt11char_traitsIcEE5closeEv
.Ltmp72:
# %bb.54:
movq %rbx, %rdi
callq free
movq 16(%rsp), %rdi # 8-byte Reload
callq free
movq %r12, %rdi
callq free
movq _ZTTSt14basic_ofstreamIcSt11char_traitsIcEE(%rip), %rax
leaq 56(%rsp), %rdi
movq %rax, -8(%rdi)
movq _ZTTSt14basic_ofstreamIcSt11char_traitsIcEE+24(%rip), %rcx
movq -24(%rax), %rax
movq %rcx, 48(%rsp,%rax)
callq _ZNSt13basic_filebufIcSt11char_traitsIcEED2Ev
leaq 296(%rsp), %rdi
callq _ZNSt8ios_baseD2Ev
leaq 560(%rsp), %rdi
callq _ZNSt14basic_ifstreamIcSt11char_traitsIcEED1Ev
xorl %eax, %eax
addq $1080, %rsp # imm = 0x438
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB5_55:
.cfi_def_cfa_offset 1136
.Ltmp32:
jmp .LBB5_64
.LBB5_56:
.Ltmp5:
jmp .LBB5_58
.LBB5_57:
.Ltmp2:
.LBB5_58:
movq %rax, %rbx
jmp .LBB5_65
.LBB5_59:
.Ltmp22:
jmp .LBB5_64
.LBB5_60:
.Ltmp73:
jmp .LBB5_64
.LBB5_61:
.Ltmp60:
jmp .LBB5_64
.LBB5_62:
.Ltmp51:
jmp .LBB5_64
.LBB5_63:
.Ltmp29:
.LBB5_64:
movq %rax, %rbx
leaq 48(%rsp), %rdi
callq _ZNSt14basic_ofstreamIcSt11char_traitsIcEED1Ev
.LBB5_65:
leaq 560(%rsp), %rdi
callq _ZNSt14basic_ifstreamIcSt11char_traitsIcEED1Ev
movq %rbx, %rdi
callq _Unwind_Resume@PLT
.Lfunc_end5:
.size main, .Lfunc_end5-main
.cfi_endproc
.section .gcc_except_table,"a",@progbits
.p2align 2, 0x0
GCC_except_table5:
.Lexception0:
.byte 255 # @LPStart Encoding = omit
.byte 255 # @TType Encoding = omit
.byte 1 # Call site Encoding = uleb128
.uleb128 .Lcst_end0-.Lcst_begin0
.Lcst_begin0:
.uleb128 .Lfunc_begin0-.Lfunc_begin0 # >> Call Site 1 <<
.uleb128 .Ltmp0-.Lfunc_begin0 # Call between .Lfunc_begin0 and .Ltmp0
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp0-.Lfunc_begin0 # >> Call Site 2 <<
.uleb128 .Ltmp1-.Ltmp0 # Call between .Ltmp0 and .Ltmp1
.uleb128 .Ltmp2-.Lfunc_begin0 # jumps to .Ltmp2
.byte 0 # On action: cleanup
.uleb128 .Ltmp3-.Lfunc_begin0 # >> Call Site 3 <<
.uleb128 .Ltmp4-.Ltmp3 # Call between .Ltmp3 and .Ltmp4
.uleb128 .Ltmp5-.Lfunc_begin0 # jumps to .Ltmp5
.byte 0 # On action: cleanup
.uleb128 .Ltmp6-.Lfunc_begin0 # >> Call Site 4 <<
.uleb128 .Ltmp21-.Ltmp6 # Call between .Ltmp6 and .Ltmp21
.uleb128 .Ltmp22-.Lfunc_begin0 # jumps to .Ltmp22
.byte 0 # On action: cleanup
.uleb128 .Ltmp21-.Lfunc_begin0 # >> Call Site 5 <<
.uleb128 .Ltmp23-.Ltmp21 # Call between .Ltmp21 and .Ltmp23
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp23-.Lfunc_begin0 # >> Call Site 6 <<
.uleb128 .Ltmp28-.Ltmp23 # Call between .Ltmp23 and .Ltmp28
.uleb128 .Ltmp29-.Lfunc_begin0 # jumps to .Ltmp29
.byte 0 # On action: cleanup
.uleb128 .Ltmp28-.Lfunc_begin0 # >> Call Site 7 <<
.uleb128 .Ltmp30-.Ltmp28 # Call between .Ltmp28 and .Ltmp30
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp30-.Lfunc_begin0 # >> Call Site 8 <<
.uleb128 .Ltmp31-.Ltmp30 # Call between .Ltmp30 and .Ltmp31
.uleb128 .Ltmp32-.Lfunc_begin0 # jumps to .Ltmp32
.byte 0 # On action: cleanup
.uleb128 .Ltmp33-.Lfunc_begin0 # >> Call Site 9 <<
.uleb128 .Ltmp42-.Ltmp33 # Call between .Ltmp33 and .Ltmp42
.uleb128 .Ltmp73-.Lfunc_begin0 # jumps to .Ltmp73
.byte 0 # On action: cleanup
.uleb128 .Ltmp43-.Lfunc_begin0 # >> Call Site 10 <<
.uleb128 .Ltmp50-.Ltmp43 # Call between .Ltmp43 and .Ltmp50
.uleb128 .Ltmp51-.Lfunc_begin0 # jumps to .Ltmp51
.byte 0 # On action: cleanup
.uleb128 .Ltmp52-.Lfunc_begin0 # >> Call Site 11 <<
.uleb128 .Ltmp53-.Ltmp52 # Call between .Ltmp52 and .Ltmp53
.uleb128 .Ltmp73-.Lfunc_begin0 # jumps to .Ltmp73
.byte 0 # On action: cleanup
.uleb128 .Ltmp54-.Lfunc_begin0 # >> Call Site 12 <<
.uleb128 .Ltmp59-.Ltmp54 # Call between .Ltmp54 and .Ltmp59
.uleb128 .Ltmp60-.Lfunc_begin0 # jumps to .Ltmp60
.byte 0 # On action: cleanup
.uleb128 .Ltmp61-.Lfunc_begin0 # >> Call Site 13 <<
.uleb128 .Ltmp72-.Ltmp61 # Call between .Ltmp61 and .Ltmp72
.uleb128 .Ltmp73-.Lfunc_begin0 # jumps to .Ltmp73
.byte 0 # On action: cleanup
.uleb128 .Ltmp72-.Lfunc_begin0 # >> Call Site 14 <<
.uleb128 .Lfunc_end5-.Ltmp72 # Call between .Ltmp72 and .Lfunc_end5
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.Lcst_end0:
.p2align 2, 0x0
# -- End function
.text
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
jne .LBB6_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, %rdi
movq %rax, __hip_gpubin_handle(%rip)
.LBB6_2:
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7FW_CudaiPiS_j, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end6:
.size __hip_module_ctor, .Lfunc_end6-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB7_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB7_2:
retq
.Lfunc_end7:
.size __hip_module_dtor, .Lfunc_end7-__hip_module_dtor
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "\r\n"
.size .L.str, 3
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "\t"
.size .L.str.1, 2
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "\342\210\236"
.size .L.str.2, 4
.type _Z7FW_CudaiPiS_j,@object # @_Z7FW_CudaiPiS_j
.section .rodata,"a",@progbits
.globl _Z7FW_CudaiPiS_j
.p2align 3, 0x0
_Z7FW_CudaiPiS_j:
.quad _Z22__device_stub__FW_CudaiPiS_j
.size _Z7FW_CudaiPiS_j, 8
.type .L.str.3,@object # @.str.3
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.3:
.asciz "Neuspje\305\241no alociranje matrice D (error code %s)!\n"
.size .L.str.3, 51
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Neuspje\305\241no alociranje matrice PI (error code %s)!\n"
.size .L.str.4, 52
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "Neuspje\305\241no kopiranje matrice D iz hosta u device (error code %s)!\n"
.size .L.str.5, 68
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "Neuspje\305\241no kopiranje matrice PI iz hosta u device (error code %s)!\n"
.size .L.str.6, 69
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "CUDA kernel se pokre\304\207e sa "
.size .L.str.7, 28
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz " blokova i "
.size .L.str.8, 12
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz " threadova po bloku.\r\n"
.size .L.str.9, 23
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "Neuspje\305\241no pokrenuta kernel metoda (error code %s)!\n"
.size .L.str.10, 54
.type .L.str.11,@object # @.str.11
.L.str.11:
.asciz "Neuspje\305\241no kopiranje matrice D iz devicea u host (error code %s)!\n"
.size .L.str.11, 68
.type .L.str.12,@object # @.str.12
.L.str.12:
.asciz "Neuspje\305\241no kopiranje matrice PI iz devicea u host (error code %s)!\n"
.size .L.str.12, 69
.type .L.str.13,@object # @.str.13
.L.str.13:
.asciz "Neuspje\305\241no dealociranje matrice D (error code %s)!\n"
.size .L.str.13, 53
.type .L.str.14,@object # @.str.14
.L.str.14:
.asciz "Neuspje\305\241no dealociranje matrice PI (error code %s)!\n"
.size .L.str.14, 54
.type .L.str.15,@object # @.str.15
.L.str.15:
.asciz "Neuspje\305\241no resetiranje devicea (zavr\305\241avanje sa CUDA FW, priprema za sljede\304\207e pokretanje)! error=%s\n"
.size .L.str.15, 103
.type .L.str.16,@object # @.str.16
.L.str.16:
.asciz "graphFile.txt"
.size .L.str.16, 14
.type .L.str.17,@object # @.str.17
.L.str.17:
.asciz "output_cuda.txt"
.size .L.str.17, 16
.type .L.str.18,@object # @.str.18
.L.str.18:
.asciz "V = "
.size .L.str.18, 5
.type .L.str.19,@object # @.str.19
.L.str.19:
.asciz ", E = "
.size .L.str.19, 7
.type .L.str.20,@object # @.str.20
.L.str.20:
.asciz "|V| = "
.size .L.str.20, 7
.type .L.str.21,@object # @.str.21
.L.str.21:
.asciz ", |E| = "
.size .L.str.21, 9
.type .L.str.22,@object # @.str.22
.L.str.22:
.asciz "\r\n\r\n"
.size .L.str.22, 5
.type .L.str.23,@object # @.str.23
.L.str.23:
.asciz "Vrijeme izvr\305\241avanja Floyd-Warshall algoritma: "
.size .L.str.23, 48
.type .L.str.24,@object # @.str.24
.L.str.24:
.asciz "s.\r\n"
.size .L.str.24, 5
.type .L.str.25,@object # @.str.25
.L.str.25:
.asciz "Svi najkra\304\207i putevi su to\304\215no izra\304\215unati!\r\n"
.size .L.str.25, 46
.type .L.str.26,@object # @.str.26
.L.str.26:
.asciz "Najkra\304\207i putevi nisu to\304\215no izra\304\215unati.\r\n"
.size .L.str.26, 44
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z7FW_CudaiPiS_j"
.size .L__unnamed_1, 17
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__FW_CudaiPiS_j
.addrsig_sym __gxx_personality_v0
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Unwind_Resume
.addrsig_sym _ZSt4cout
.addrsig_sym _Z7FW_CudaiPiS_j
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
```
| 13,100 | 16,801 |
60 |
Convert the following CUDA device assembly code to AMD device assembly:
```cudaasm
code for sm_80
Function : _Z11get_averagePfS_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ;
S2R R4, SR_TID.X ;
ISETP.GE.AND P0, PT, R4, c[0x0][0x170], PT ;
@P0 EXIT ;
ISETP.LT.AND P0, PT, RZ, c[0x0][0x174], PT ;
I2F R0, c[0x0][0x174] ;
ULDC.64 UR4, c[0x0][0x118] ;
@P0 BRA 0x1d0 ;
IMAD.MOV.U32 R3, RZ, RZ, 0x4 ;
IMAD.WIDE R2, R4, R3, c[0x0][0x168] ;
LDG.E R13, [R2.64] ;
MUFU.RCP R5, R0 ;
IADD3 R4, R4, c[0x0][0x0], RZ ;
BSSY B0, 0x1a0 ;
ISETP.GE.AND P2, PT, R4, c[0x0][0x170], PT ;
FFMA R6, -R0, R5, 1 ;
FFMA R6, R5, R6, R5 ;
FCHK P0, R13, R0 ;
FFMA R5, R13, R6, RZ ;
FFMA R7, -R0, R5, R13 ;
FFMA R5, R6, R7, R5 ;
@!P0 BRA 0x190 ;
MOV R8, 0x180 ;
CALL.REL.NOINC 0x1750 ;
MOV R5, R11 ;
BSYNC B0 ;
STG.E [R2.64], R5 ;
@!P2 BRA 0x80 ;
EXIT ;
IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x174] ;
LOP3.LUT R16, R5.reuse, 0x3, RZ, 0xc0, !PT ;
IADD3 R5, R5, -0x1, RZ ;
IADD3 R6, -R16, c[0x0][0x174], RZ ;
ISETP.GE.U32.AND P3, PT, R5, 0x3, PT ;
IMAD.MOV.U32 R10, RZ, RZ, 0x4 ;
HFMA2.MMA R12, -RZ, RZ, 0, 0 ;
IMAD R7, R4.reuse, c[0x0][0x174], RZ ;
IMAD.WIDE R2, R4.reuse, R10, c[0x0][0x168] ;
IADD3 R4, R4, c[0x0][0x0], RZ ;
ISETP.GE.AND P2, PT, R4, c[0x0][0x170], PT ;
@!P3 BRA 0xa20 ;
LDG.E R13, [R2.64] ;
ISETP.GT.AND P0, PT, R6, RZ, PT ;
IMAD.MOV.U32 R12, RZ, RZ, RZ ;
IMAD.MOV.U32 R11, RZ, RZ, R6 ;
IMAD.WIDE R8, R7, R10, c[0x0][0x160] ;
@!P0 BRA 0x8e0 ;
ISETP.GT.AND P1, PT, R11, 0xc, PT ;
PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ;
@!P1 BRA 0x6b0 ;
PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ;
LDG.E R14, [R8.64] ;
FADD R13, R14, R13 ;
STG.E [R2.64], R13 ;
LDG.E R14, [R8.64+0x4] ;
FADD R15, R13, R14 ;
STG.E [R2.64], R15 ;
LDG.E R14, [R8.64+0x8] ;
FADD R17, R15, R14 ;
STG.E [R2.64], R17 ;
LDG.E R14, [R8.64+0xc] ;
FADD R19, R17, R14 ;
STG.E [R2.64], R19 ;
LDG.E R14, [R8.64+0x10] ;
FADD R13, R19, R14 ;
STG.E [R2.64], R13 ;
LDG.E R14, [R8.64+0x14] ;
FADD R15, R13, R14 ;
STG.E [R2.64], R15 ;
LDG.E R14, [R8.64+0x18] ;
FADD R17, R15, R14 ;
STG.E [R2.64], R17 ;
LDG.E R14, [R8.64+0x1c] ;
FADD R19, R17, R14 ;
STG.E [R2.64], R19 ;
LDG.E R14, [R8.64+0x20] ;
FADD R13, R19, R14 ;
STG.E [R2.64], R13 ;
LDG.E R14, [R8.64+0x24] ;
FADD R15, R13, R14 ;
STG.E [R2.64], R15 ;
LDG.E R14, [R8.64+0x28] ;
FADD R17, R15, R14 ;
STG.E [R2.64], R17 ;
LDG.E R14, [R8.64+0x2c] ;
FADD R19, R17, R14 ;
STG.E [R2.64], R19 ;
LDG.E R14, [R8.64+0x30] ;
FADD R21, R19, R14 ;
STG.E [R2.64], R21 ;
LDG.E R14, [R8.64+0x34] ;
FADD R15, R21, R14 ;
STG.E [R2.64], R15 ;
LDG.E R14, [R8.64+0x38] ;
FADD R17, R15, R14 ;
STG.E [R2.64], R17 ;
LDG.E R14, [R8.64+0x3c] ;
IADD3 R11, R11, -0x10, RZ ;
IADD3 R12, R12, 0x10, RZ ;
ISETP.GT.AND P1, PT, R11, 0xc, PT ;
FADD R13, R17, R14 ;
IADD3 R14, P4, R8, 0x40, RZ ;
STG.E [R2.64], R13 ;
IADD3.X R19, RZ, R9, RZ, P4, !PT ;
IMAD.MOV.U32 R8, RZ, RZ, R14 ;
IMAD.MOV.U32 R9, RZ, RZ, R19 ;
@P1 BRA 0x330 ;
ISETP.GT.AND P1, PT, R11, 0x4, PT ;
@!P1 BRA 0x8c0 ;
LDG.E R14, [R8.64] ;
FADD R13, R13, R14 ;
STG.E [R2.64], R13 ;
LDG.E R14, [R8.64+0x4] ;
FADD R15, R13, R14 ;
STG.E [R2.64], R15 ;
LDG.E R14, [R8.64+0x8] ;
FADD R17, R15, R14 ;
STG.E [R2.64], R17 ;
LDG.E R14, [R8.64+0xc] ;
FADD R19, R17, R14 ;
STG.E [R2.64], R19 ;
LDG.E R14, [R8.64+0x10] ;
FADD R21, R19, R14 ;
STG.E [R2.64], R21 ;
LDG.E R14, [R8.64+0x14] ;
FADD R15, R21, R14 ;
STG.E [R2.64], R15 ;
LDG.E R14, [R8.64+0x18] ;
FADD R17, R15, R14 ;
STG.E [R2.64], R17 ;
LDG.E R14, [R8.64+0x1c] ;
PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ;
IADD3 R12, R12, 0x8, RZ ;
IADD3 R11, R11, -0x8, RZ ;
FADD R13, R17, R14 ;
IADD3 R14, P1, R8, 0x20, RZ ;
STG.E [R2.64], R13 ;
IADD3.X R19, RZ, R9, RZ, P1, !PT ;
IMAD.MOV.U32 R8, RZ, RZ, R14 ;
IMAD.MOV.U32 R9, RZ, RZ, R19 ;
ISETP.NE.OR P0, PT, R11, RZ, P0 ;
@!P0 BRA 0xa20 ;
LDG.E R14, [R8.64] ;
FADD R15, R14, R13 ;
STG.E [R2.64], R15 ;
LDG.E R14, [R8.64+0x4] ;
FADD R17, R15, R14 ;
STG.E [R2.64], R17 ;
LDG.E R14, [R8.64+0x8] ;
FADD R19, R17, R14 ;
STG.E [R2.64], R19 ;
LDG.E R14, [R8.64+0xc] ;
IADD3 R11, R11, -0x4, RZ ;
IADD3 R12, R12, 0x4, RZ ;
ISETP.NE.AND P0, PT, R11, RZ, PT ;
FADD R13, R19, R14 ;
IADD3 R14, P1, R8, 0x10, RZ ;
STG.E [R2.64], R13 ;
IADD3.X R15, RZ, R9, RZ, P1, !PT ;
IMAD.MOV.U32 R8, RZ, RZ, R14 ;
MOV R9, R15 ;
@P0 BRA 0x8e0 ;
ISETP.NE.AND P4, PT, R16, RZ, PT ;
@!P4 BRA 0xb50 ;
IMAD.IADD R11, R7, 0x1, R12 ;
LDG.E R9, [R2.64] ;
IMAD.WIDE R10, R11, R10, c[0x0][0x160] ;
LDG.E R8, [R10.64] ;
ISETP.NE.AND P0, PT, R16, 0x1, PT ;
FADD R9, R8, R9 ;
STG.E [R2.64], R9 ;
@!P0 BRA 0xb60 ;
LDG.E R8, [R10.64+0x4] ;
ISETP.NE.AND P0, PT, R16, 0x2, PT ;
FADD R9, R9, R8 ;
STG.E [R2.64], R9 ;
@!P0 BRA 0xb60 ;
LDG.E R10, [R10.64+0x8] ;
FADD R9, R9, R10 ;
STG.E [R2.64], R9 ;
BRA 0xb60 ;
LDG.E R9, [R2.64] ;
MUFU.RCP R11, R0 ;
BSSY B0, 0xc30 ;
FCHK P0, R9, R0 ;
FFMA R8, -R0, R11, 1 ;
FFMA R10, R11, R8, R11 ;
FFMA R8, R10, R9, RZ ;
FFMA R11, -R0, R8, R9 ;
FFMA R11, R11, R10, R8 ;
@!P0 BRA 0xc20 ;
MOV R13, R9 ;
MOV R8, 0xc20 ;
CALL.REL.NOINC 0x1750 ;
BSYNC B0 ;
STG.E [R2.64], R11 ;
IMAD.MOV.U32 R8, RZ, RZ, RZ ;
@!P3 BRA 0x15e0 ;
ISETP.GT.AND P0, PT, R6, RZ, PT ;
HFMA2.MMA R8, -RZ, RZ, 0, 0 ;
IMAD.MOV.U32 R9, RZ, RZ, R6 ;
@!P0 BRA 0x1470 ;
ISETP.GT.AND P1, PT, R9, 0xc, PT ;
PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ;
@!P1 BRA 0x11b0 ;
PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ;
IADD3 R11, R7, R8, RZ ;
IMAD.MOV.U32 R12, RZ, RZ, 0x4 ;
LDG.E R14, [R2.64] ;
IMAD.WIDE R10, R11, R12, c[0x0][0x160] ;
LDG.E R13, [R10.64] ;
FADD R13, R13, -R14 ;
LDG.E R14, [R10.64+0x4] ;
STG.E [R10.64], R13 ;
LDG.E R15, [R2.64] ;
FADD R17, R14, -R15 ;
LDG.E R14, [R10.64+0x8] ;
STG.E [R10.64+0x4], R17 ;
LDG.E R15, [R2.64] ;
FADD R19, R14, -R15 ;
LDG.E R14, [R10.64+0xc] ;
STG.E [R10.64+0x8], R19 ;
LDG.E R15, [R2.64] ;
IADD3 R21, R7, 0x4, R8 ;
FADD R13, R14, -R15 ;
IMAD.WIDE R14, R21, R12, c[0x0][0x160] ;
STG.E [R10.64+0xc], R13 ;
LDG.E R18, [R2.64] ;
LDG.E R17, [R14.64] ;
LDG.E R10, [R14.64+0xc] ;
FADD R17, R17, -R18 ;
LDG.E R18, [R14.64+0x4] ;
STG.E [R14.64], R17 ;
LDG.E R19, [R2.64] ;
FADD R19, R18, -R19 ;
LDG.E R18, [R14.64+0x8] ;
STG.E [R14.64+0x4], R19 ;
LDG.E R21, [R2.64] ;
FADD R21, R18, -R21 ;
STG.E [R14.64+0x8], R21 ;
LDG.E R11, [R2.64] ;
IADD3 R23, R7, 0x8, R8 ;
FADD R13, R10, -R11 ;
IMAD.WIDE R10, R23, R12, c[0x0][0x160] ;
STG.E [R14.64+0xc], R13 ;
LDG.E R18, [R2.64] ;
LDG.E R17, [R10.64] ;
LDG.E R13, [R10.64+0xc] ;
FADD R17, R17, -R18 ;
LDG.E R18, [R10.64+0x4] ;
STG.E [R10.64], R17 ;
LDG.E R19, [R2.64] ;
FADD R19, R18, -R19 ;
LDG.E R18, [R10.64+0x8] ;
STG.E [R10.64+0x4], R19 ;
LDG.E R21, [R2.64] ;
FADD R21, R18, -R21 ;
STG.E [R10.64+0x8], R21 ;
LDG.E R14, [R2.64] ;
IADD3 R23, R7, 0xc, R8 ;
FADD R15, R13, -R14 ;
IMAD.WIDE R12, R23, R12, c[0x0][0x160] ;
STG.E [R10.64+0xc], R15 ;
LDG.E R17, [R2.64] ;
LDG.E R14, [R12.64] ;
LDG.E R10, [R12.64+0xc] ;
FADD R17, R14, -R17 ;
LDG.E R14, [R12.64+0x4] ;
STG.E [R12.64], R17 ;
LDG.E R19, [R2.64] ;
FADD R19, R14, -R19 ;
LDG.E R14, [R12.64+0x8] ;
STG.E [R12.64+0x4], R19 ;
LDG.E R21, [R2.64] ;
FADD R21, R14, -R21 ;
STG.E [R12.64+0x8], R21 ;
LDG.E R11, [R2.64] ;
IADD3 R9, R9, -0x10, RZ ;
ISETP.GT.AND P1, PT, R9, 0xc, PT ;
IADD3 R8, R8, 0x10, RZ ;
FADD R11, R10, -R11 ;
STG.E [R12.64+0xc], R11 ;
@P1 BRA 0xce0 ;
ISETP.GT.AND P1, PT, R9, 0x4, PT ;
@!P1 BRA 0x1450 ;
IADD3 R10, R7, R8, RZ ;
IMAD.MOV.U32 R21, RZ, RZ, 0x4 ;
LDG.E R13, [R2.64] ;
IMAD.WIDE R10, R10, R21, c[0x0][0x160] ;
LDG.E R12, [R10.64] ;
FADD R13, R12, -R13 ;
LDG.E R12, [R10.64+0x4] ;
STG.E [R10.64], R13 ;
LDG.E R15, [R2.64] ;
FADD R15, R12, -R15 ;
LDG.E R12, [R10.64+0x8] ;
STG.E [R10.64+0x4], R15 ;
LDG.E R17, [R2.64] ;
FADD R17, R12, -R17 ;
LDG.E R12, [R10.64+0xc] ;
STG.E [R10.64+0x8], R17 ;
LDG.E R19, [R2.64] ;
IADD3 R14, R7, 0x4, R8 ;
FADD R19, R12, -R19 ;
IMAD.WIDE R12, R14, R21, c[0x0][0x160] ;
STG.E [R10.64+0xc], R19 ;
LDG.E R21, [R2.64] ;
LDG.E R14, [R12.64] ;
LDG.E R10, [R12.64+0xc] ;
FADD R21, R14, -R21 ;
LDG.E R14, [R12.64+0x4] ;
STG.E [R12.64], R21 ;
LDG.E R15, [R2.64] ;
FADD R15, R14, -R15 ;
LDG.E R14, [R12.64+0x8] ;
STG.E [R12.64+0x4], R15 ;
LDG.E R17, [R2.64] ;
FADD R17, R14, -R17 ;
STG.E [R12.64+0x8], R17 ;
LDG.E R11, [R2.64] ;
PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ;
IADD3 R9, R9, -0x8, RZ ;
IADD3 R8, R8, 0x8, RZ ;
FADD R11, R10, -R11 ;
STG.E [R12.64+0xc], R11 ;
ISETP.NE.OR P0, PT, R9, RZ, P0 ;
@!P0 BRA 0x15e0 ;
IADD3 R10, R7, R8, RZ ;
IMAD.MOV.U32 R11, RZ, RZ, 0x4 ;
LDG.E R13, [R2.64] ;
IMAD.WIDE R10, R10, R11, c[0x0][0x160] ;
LDG.E R12, [R10.64] ;
FADD R13, R12, -R13 ;
LDG.E R12, [R10.64+0x4] ;
STG.E [R10.64], R13 ;
LDG.E R15, [R2.64] ;
FADD R15, R12, -R15 ;
LDG.E R12, [R10.64+0x8] ;
STG.E [R10.64+0x4], R15 ;
LDG.E R17, [R2.64] ;
FADD R17, R12, -R17 ;
LDG.E R12, [R10.64+0xc] ;
STG.E [R10.64+0x8], R17 ;
LDG.E R19, [R2.64] ;
IADD3 R9, R9, -0x4, RZ ;
ISETP.NE.AND P0, PT, R9, RZ, PT ;
IADD3 R8, R8, 0x4, RZ ;
FADD R19, R12, -R19 ;
STG.E [R10.64+0xc], R19 ;
@P0 BRA 0x1470 ;
@!P4 BRA 0x1720 ;
IADD3 R8, R7, R8, RZ ;
IMAD.MOV.U32 R9, RZ, RZ, 0x4 ;
LDG.E R10, [R2.64] ;
IMAD.WIDE R8, R8, R9, c[0x0][0x160] ;
LDG.E R7, [R8.64] ;
ISETP.NE.AND P0, PT, R16, 0x1, PT ;
FADD R7, R7, -R10 ;
STG.E [R8.64], R7 ;
@!P0 BRA 0x1720 ;
LDG.E R7, [R8.64+0x4] ;
LDG.E R10, [R2.64] ;
ISETP.NE.AND P0, PT, R16, 0x2, PT ;
FADD R7, R7, -R10 ;
STG.E [R8.64+0x4], R7 ;
@!P0 BRA 0x1720 ;
LDG.E R2, [R2.64] ;
LDG.E R7, [R8.64+0x8] ;
FADD R7, -R2, R7 ;
STG.E [R8.64+0x8], R7 ;
@P2 CALL.REL.NOINC 0x1740 ;
BRA 0x210 ;
EXIT ;
SHF.R.U32.HI R11, RZ, 0x17, R0.reuse ;
BSSY B1, 0x1db0 ;
SHF.R.U32.HI R9, RZ, 0x17, R13 ;
IMAD.MOV.U32 R12, RZ, RZ, R0 ;
LOP3.LUT R11, R11, 0xff, RZ, 0xc0, !PT ;
LOP3.LUT R14, R9, 0xff, RZ, 0xc0, !PT ;
IADD3 R17, R11, -0x1, RZ ;
IADD3 R15, R14, -0x1, RZ ;
ISETP.GT.U32.AND P0, PT, R17, 0xfd, PT ;
MOV R9, R13 ;
ISETP.GT.U32.OR P0, PT, R15, 0xfd, P0 ;
@!P0 MOV R10, RZ ;
@!P0 BRA 0x1990 ;
FSETP.GTU.FTZ.AND P0, PT, |R13|, +INF , PT ;
FSETP.GTU.FTZ.AND P1, PT, |R0|, +INF , PT ;
PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ;
@P0 BRA 0x1d90 ;
LOP3.LUT P0, RZ, R12, 0x7fffffff, R9, 0xc8, !PT ;
@!P0 BRA 0x1d70 ;
FSETP.NEU.FTZ.AND P5, PT, |R13|.reuse, +INF , PT ;
FSETP.NEU.FTZ.AND P1, PT, |R0|, +INF , PT ;
FSETP.NEU.FTZ.AND P0, PT, |R13|, +INF , PT ;
@!P1 BRA !P5, 0x1d70 ;
LOP3.LUT P5, RZ, R9, 0x7fffffff, RZ, 0xc0, !PT ;
PLOP3.LUT P1, PT, P1, P5, PT, 0x2a, 0x0 ;
@P1 BRA 0x1d50 ;
LOP3.LUT P1, RZ, R12, 0x7fffffff, RZ, 0xc0, !PT ;
PLOP3.LUT P0, PT, P0, P1, PT, 0x2a, 0x0 ;
@P0 BRA 0x1d20 ;
ISETP.GE.AND P0, PT, R15, RZ, PT ;
ISETP.GE.AND P1, PT, R17, RZ, PT ;
@P0 IMAD.MOV.U32 R10, RZ, RZ, RZ ;
@!P0 MOV R10, 0xffffffc0 ;
@!P0 FFMA R9, R13, 1.84467440737095516160e+19, RZ ;
@!P1 FFMA R12, R0, 1.84467440737095516160e+19, RZ ;
@!P1 IADD3 R10, R10, 0x40, RZ ;
LEA R13, R11, 0xc0800000, 0x17 ;
BSSY B2, 0x1d10 ;
IADD3 R14, R14, -0x7f, RZ ;
IMAD.IADD R13, R12, 0x1, -R13 ;
IMAD R9, R14.reuse, -0x800000, R9 ;
MUFU.RCP R12, R13 ;
FADD.FTZ R18, -R13, -RZ ;
IADD3 R13, R14, 0x7f, -R11 ;
IADD3 R10, R13, R10, RZ ;
FFMA R15, R12, R18, 1 ;
FFMA R12, R12, R15, R12 ;
FFMA R15, R9, R12, RZ ;
FFMA R17, R18, R15, R9 ;
FFMA R17, R12, R17, R15 ;
FFMA R18, R18, R17, R9 ;
FFMA R9, R12, R18, R17 ;
SHF.R.U32.HI R11, RZ, 0x17, R9 ;
LOP3.LUT R11, R11, 0xff, RZ, 0xc0, !PT ;
IMAD.IADD R14, R11, 0x1, R10 ;
IADD3 R11, R14, -0x1, RZ ;
ISETP.GE.U32.AND P0, PT, R11, 0xfe, PT ;
@!P0 BRA 0x1cf0 ;
ISETP.GT.AND P0, PT, R14, 0xfe, PT ;
@P0 BRA 0x1cc0 ;
ISETP.GE.AND P0, PT, R14, 0x1, PT ;
@P0 BRA 0x1d00 ;
ISETP.GE.AND P0, PT, R14, -0x18, PT ;
LOP3.LUT R9, R9, 0x80000000, RZ, 0xc0, !PT ;
@!P0 BRA 0x1d00 ;
FFMA.RZ R10, R12, R18.reuse, R17.reuse ;
ISETP.NE.AND P5, PT, R14, RZ, PT ;
FFMA.RM R11, R12, R18.reuse, R17.reuse ;
ISETP.NE.AND P1, PT, R14, RZ, PT ;
LOP3.LUT R13, R10, 0x7fffff, RZ, 0xc0, !PT ;
FFMA.RP R10, R12, R18, R17 ;
IADD3 R12, R14.reuse, 0x20, RZ ;
LOP3.LUT R13, R13, 0x800000, RZ, 0xfc, !PT ;
IADD3 R14, -R14, RZ, RZ ;
SHF.L.U32 R12, R13, R12, RZ ;
FSETP.NEU.FTZ.AND P0, PT, R10, R11, PT ;
SEL R10, R14, RZ, P5 ;
ISETP.NE.AND P1, PT, R12, RZ, P1 ;
SHF.R.U32.HI R10, RZ, R10, R13 ;
PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ;
SHF.R.U32.HI R12, RZ, 0x1, R10 ;
SEL R11, RZ, 0x1, !P0 ;
LOP3.LUT R11, R11, 0x1, R12, 0xf8, !PT ;
LOP3.LUT R11, R11, R10, RZ, 0xc0, !PT ;
IMAD.IADD R12, R12, 0x1, R11 ;
LOP3.LUT R9, R12, R9, RZ, 0xfc, !PT ;
BRA 0x1d00 ;
LOP3.LUT R9, R9, 0x80000000, RZ, 0xc0, !PT ;
LOP3.LUT R9, R9, 0x7f800000, RZ, 0xfc, !PT ;
BRA 0x1d00 ;
LEA R9, R10, R9, 0x17 ;
BSYNC B2 ;
BRA 0x1da0 ;
LOP3.LUT R9, R12, 0x80000000, R9, 0x48, !PT ;
LOP3.LUT R9, R9, 0x7f800000, RZ, 0xfc, !PT ;
BRA 0x1da0 ;
LOP3.LUT R9, R12, 0x80000000, R9, 0x48, !PT ;
BRA 0x1da0 ;
MUFU.RSQ R9, -QNAN ;
BRA 0x1da0 ;
FADD.FTZ R9, R13, R0 ;
BSYNC B1 ;
IMAD.MOV.U32 R11, RZ, RZ, R9 ;
HFMA2.MMA R9, -RZ, RZ, 0, 0 ;
RET.REL.NODEC R8 0x0 ;
BRA 0x1de0;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
```
|
```amdasm
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z11get_averagePfS_ii ; -- Begin function _Z11get_averagePfS_ii
.globl _Z11get_averagePfS_ii
.p2align 8
.type _Z11get_averagePfS_ii,@function
_Z11get_averagePfS_ii: ; @_Z11get_averagePfS_ii
; %bb.0:
s_load_b64 s[4:5], s[0:1], 0x10
s_mov_b32 s2, exec_lo
s_waitcnt lgkmcnt(0)
v_cmpx_gt_i32_e64 s4, v0
s_cbranch_execz .LBB0_11
; %bb.1: ; %.preheader.lr.ph
s_clause 0x1
s_load_b32 s8, s[0:1], 0x24
s_load_b128 s[0:3], s[0:1], 0x0
s_cmp_gt_i32 s5, 0
v_mul_lo_u32 v2, v0, s5
s_cselect_b32 s6, -1, 0
s_cmp_lt_i32 s5, 1
v_cvt_f32_i32_e32 v9, s5
s_cselect_b32 s7, -1, 0
s_mov_b32 s9, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s8, s8, 0xffff
s_delay_alu instid0(SALU_CYCLE_1)
s_mul_i32 s10, s5, s8
.LBB0_2: ; %.preheader
; =>This Loop Header: Depth=1
; Child Loop BB0_7 Depth 2
; Child Loop BB0_9 Depth 2
s_and_not1_b32 vcc_lo, exec_lo, s7
s_cbranch_vccnz .LBB0_4
; %bb.3: ; %.preheader.._crit_edge_crit_edge
; in Loop: Header=BB0_2 Depth=1
v_ashrrev_i32_e32 v1, 31, v0
s_mov_b32 s11, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[0:1]
v_add_co_u32 v3, vcc_lo, s2, v3
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v4, vcc_lo, s3, v4, vcc_lo
global_load_b32 v10, v[3:4], off
s_branch .LBB0_5
.LBB0_4: ; in Loop: Header=BB0_2 Depth=1
s_mov_b32 s11, -1
; implicit-def: $vgpr10
.LBB0_5: ; %Flow60
; in Loop: Header=BB0_2 Depth=1
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[2:3]
v_add_co_u32 v3, vcc_lo, s0, v3
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo
s_and_not1_b32 vcc_lo, exec_lo, s11
s_cbranch_vccnz .LBB0_8
; %bb.6: ; %.lr.ph
; in Loop: Header=BB0_2 Depth=1
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_dual_mov_b32 v8, v4 :: v_dual_mov_b32 v7, v3
s_mov_b32 s11, s5
v_lshlrev_b64 v[5:6], 2, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v5, vcc_lo, s2, v5
v_add_co_ci_u32_e32 v6, vcc_lo, s3, v6, vcc_lo
global_load_b32 v10, v[5:6], off
.LBB0_7: ; Parent Loop BB0_2 Depth=1
; => This Inner Loop Header: Depth=2
global_load_b32 v11, v[7:8], off
v_add_co_u32 v7, vcc_lo, v7, 4
v_add_co_ci_u32_e32 v8, vcc_lo, 0, v8, vcc_lo
s_add_i32 s11, s11, -1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s11, 0
s_waitcnt vmcnt(0)
v_add_f32_e32 v10, v11, v10
global_store_b32 v[5:6], v10, off
s_cbranch_scc0 .LBB0_7
.LBB0_8: ; %Flow61
; in Loop: Header=BB0_2 Depth=1
s_waitcnt vmcnt(0)
v_div_scale_f32 v5, null, v9, v9, v10
v_div_scale_f32 v8, vcc_lo, v10, v9, v10
s_mov_b32 s11, s5
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f32_e32 v7, v5
s_waitcnt_depctr 0xfff
v_fma_f32 v6, -v5, v7, 1.0
v_fmac_f32_e32 v7, v6, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v11, v8, v7
v_fma_f32 v6, -v5, v11, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v11, v6, v7
v_fma_f32 v8, -v5, v11, v8
v_lshlrev_b64 v[5:6], 2, v[0:1]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_div_fmas_f32 v1, v8, v7, v11
v_add_co_u32 v5, vcc_lo, s2, v5
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e32 v6, vcc_lo, s3, v6, vcc_lo
v_div_fixup_f32 v1, v1, v9, v10
s_and_not1_b32 vcc_lo, exec_lo, s6
global_store_b32 v[5:6], v1, off
s_cbranch_vccnz .LBB0_10
.LBB0_9: ; Parent Loop BB0_2 Depth=1
; => This Inner Loop Header: Depth=2
global_load_b32 v1, v[5:6], off
global_load_b32 v7, v[3:4], off
s_add_i32 s11, s11, -1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s11, 0
s_waitcnt vmcnt(0)
v_sub_f32_e32 v1, v7, v1
global_store_b32 v[3:4], v1, off
v_add_co_u32 v3, vcc_lo, v3, 4
v_add_co_ci_u32_e32 v4, vcc_lo, 0, v4, vcc_lo
s_cbranch_scc0 .LBB0_9
.LBB0_10: ; %._crit_edge32
; in Loop: Header=BB0_2 Depth=1
v_add_nc_u32_e32 v0, s8, v0
v_add_nc_u32_e32 v2, s10, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_le_i32_e32 vcc_lo, s4, v0
s_or_b32 s9, vcc_lo, s9
s_and_not1_b32 exec_lo, exec_lo, s9
s_cbranch_execnz .LBB0_2
.LBB0_11: ; %._crit_edge34
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11get_averagePfS_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 12
.amdhsa_next_free_sgpr 12
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z11get_averagePfS_ii, .Lfunc_end0-_Z11get_averagePfS_ii
; -- End function
.section .AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 544
; NumSgprs: 14
; NumVgprs: 12
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 1
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 14
; NumVGPRsForWavesPerEU: 12
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object ; @__hip_cuid_
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0 ; 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11get_averagePfS_ii
.private_segment_fixed_size: 0
.sgpr_count: 14
.sgpr_spill_count: 0
.symbol: _Z11get_averagePfS_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 12
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
```
| 8,607 | 4,240 |
61 |
Convert the following CUDA host assembly code to AMD host assembly:
```cudaasm
.file "tmpxft_0015a20a_00000000-6_cudaversion.cudafe1.cpp"
.text
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z35__device_stub__Z11get_averagePfS_iiPfS_ii
.type _Z35__device_stub__Z11get_averagePfS_iiPfS_ii, @function
_Z35__device_stub__Z11get_averagePfS_iiPfS_ii:
.LFB2082:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z11get_averagePfS_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z35__device_stub__Z11get_averagePfS_iiPfS_ii, .-_Z35__device_stub__Z11get_averagePfS_iiPfS_ii
.globl _Z11get_averagePfS_ii
.type _Z11get_averagePfS_ii, @function
_Z11get_averagePfS_ii:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z11get_averagePfS_iiPfS_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z11get_averagePfS_ii, .-_Z11get_averagePfS_ii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "r"
.LC1:
.string "matrix.csv"
.LC2:
.string "\n file opening failed "
.LC3:
.string "Start load csv\n"
.LC4:
.string ","
.LC5:
.string "Load Finish%lf\n"
.LC6:
.string "err is %d\n"
.LC7:
.string "Start calaute\n"
.LC8:
.string "Now write\n"
.LC9:
.string "w+"
.LC10:
.string "B1.csv"
.LC11:
.string "\n%d"
.LC12:
.string ",%lf "
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
leaq -397312(%rsp), %r11
.cfi_def_cfa 11, 397368
.LPSRL0:
subq $4096, %rsp
orq $0, (%rsp)
cmpq %r11, %rsp
jne .LPSRL0
.cfi_def_cfa_register 7
subq $2744, %rsp
.cfi_def_cfa_offset 400112
movq %fs:40, %rax
movq %rax, 400040(%rsp)
xorl %eax, %eax
movl row(%rip), %ebx
movl %ebx, %edi
imull col(%rip), %edi
movslq %edi, %rdi
salq $2, %rdi
call malloc@PLT
movq %rax, %rbp
movslq %ebx, %rdi
salq $2, %rdi
call malloc@PLT
movq %rax, %r14
leaq .LC0(%rip), %rsi
leaq .LC1(%rip), %rdi
call fopen@PLT
testq %rax, %rax
je .L28
movq %rax, %r13
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %ebx
leaq .LC4(%rip), %r12
.L14:
leaq 32(%rsp), %rdi
movq %r13, %rcx
movl $400000, %edx
movl $400000, %esi
call __fgets_chk@PLT
movq %rax, %rdi
testq %rax, %rax
je .L29
movq %r12, %rsi
call strtok@PLT
movq %rax, %rdi
testq %rax, %rax
je .L14
addl $1, %ebx
movslq %ebx, %rbx
.L16:
movl $0, %esi
call strtod@PLT
cvtsd2ss %xmm0, %xmm0
movss %xmm0, -4(%rbp,%rbx,4)
movq %r12, %rsi
movl $0, %edi
call strtok@PLT
movq %rax, %rdi
movq %rbx, %rax
addq $1, %rbx
testq %rdi, %rdi
jne .L16
movl %eax, %ebx
jmp .L14
.L28:
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $-1, %eax
jmp .L11
.L29:
pxor %xmm0, %xmm0
cvtss2sd 20(%rbp), %xmm0
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl row(%rip), %esi
imull col(%rip), %esi
movslq %esi, %rsi
salq $2, %rsi
leaq gmat(%rip), %rdi
call cudaMalloc@PLT
movl %eax, %edx
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movslq row(%rip), %rsi
salq $2, %rsi
leaq gsum(%rip), %rdi
call cudaMalloc@PLT
movl row(%rip), %edx
imull col(%rip), %edx
movslq %edx, %rdx
salq $2, %rdx
movl $1, %ecx
movq %rbp, %rsi
movq gmat(%rip), %rdi
call cudaMemcpy@PLT
movslq row(%rip), %rdx
salq $2, %rdx
movl $1, %ecx
movq %r14, %rsi
movq gsum(%rip), %rdi
call cudaMemcpy@PLT
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $512, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 8(%rsp)
movl $1, 12(%rsp)
movl $1, 16(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L30
.L18:
movl row(%rip), %edx
imull col(%rip), %edx
movslq %edx, %rdx
salq $2, %rdx
movl $2, %ecx
movq gmat(%rip), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
movslq row(%rip), %rdx
salq $2, %rdx
movl $2, %ecx
movq gsum(%rip), %rsi
movq %r14, %rdi
call cudaMemcpy@PLT
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC9(%rip), %rsi
leaq .LC10(%rip), %rdi
call fopen@PLT
movq %rax, %r12
cmpl $0, row(%rip)
jle .L23
movl $0, %r15d
leaq .LC12(%rip), %r14
.L21:
movl %r15d, %r13d
addl $1, %r15d
movl %r15d, %ecx
leaq .LC11(%rip), %rdx
movl $2, %esi
movq %r12, %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl col(%rip), %eax
testl %eax, %eax
jle .L19
movl $0, %ebx
.L20:
imull %r13d, %eax
addl %ebx, %eax
cltq
pxor %xmm0, %xmm0
cvtss2sd 0(%rbp,%rax,4), %xmm0
movq %r14, %rdx
movl $2, %esi
movq %r12, %rdi
movl $1, %eax
call __fprintf_chk@PLT
addl $1, %ebx
movl col(%rip), %eax
cmpl %ebx, %eax
jg .L20
.L19:
cmpl row(%rip), %r15d
jl .L21
movl $0, %eax
.L11:
movq 400040(%rsp), %rdx
subq %fs:40, %rdx
jne .L31
addq $400056, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L30:
.cfi_restore_state
movl col(%rip), %ecx
movl row(%rip), %edx
movq gsum(%rip), %rsi
movq gmat(%rip), %rdi
call _Z35__device_stub__Z11get_averagePfS_iiPfS_ii
jmp .L18
.L23:
movl $0, %eax
jmp .L11
.L31:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC13:
.string "_Z11get_averagePfS_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC13(%rip), %rdx
movq %rdx, %rcx
leaq _Z11get_averagePfS_ii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl gsum
.bss
.align 8
.type gsum, @object
.size gsum, 8
gsum:
.zero 8
.globl gmat
.align 8
.type gmat, @object
.size gmat, 8
gmat:
.zero 8
.globl col
.data
.align 4
.type col, @object
.size col, 4
col:
.long 464
.globl row
.align 4
.type row, @object
.size row, 4
row:
.long 480000
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
```
|
```amdasm
.text
.file "cudaversion.hip"
.globl _Z26__device_stub__get_averagePfS_ii # -- Begin function _Z26__device_stub__get_averagePfS_ii
.type _Z26__device_stub__get_averagePfS_ii,@function
_Z26__device_stub__get_averagePfS_ii: # @_Z26__device_stub__get_averagePfS_ii
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $112, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 40(%rsp), %rax
movq %rdi, (%rax)
leaq 32(%rsp), %rdi
movq %rsi, (%rdi)
leaq 12(%rsp), %rsi
movl %edx, (%rsi)
leaq 8(%rsp), %rdx
movl %ecx, (%rdx)
leaq 80(%rsp), %rbx
movq %rax, (%rbx)
movq %rdi, 8(%rbx)
movq %rsi, 16(%rbx)
movq %rdx, 24(%rbx)
leaq 64(%rsp), %r14
leaq 48(%rsp), %r15
leaq 24(%rsp), %r12
leaq 16(%rsp), %r13
movq %r14, %rdi
movq %r15, %rsi
movq %r12, %rdx
movq %r13, %rcx
callq __hipPopCallConfiguration
movq (%r14), %rsi
movl 8(%r14), %edx
movq (%r15), %rcx
movl 8(%r15), %r8d
movl $_Z11get_averagePfS_ii, %edi
movq %rbx, %r9
pushq (%r13)
.cfi_adjust_cfa_offset 8
pushq (%r12)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $128, %rsp
.cfi_adjust_cfa_offset -128
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z26__device_stub__get_averagePfS_ii, .Lfunc_end0-_Z26__device_stub__get_averagePfS_ii
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $400008, %rsp # imm = 0x61A88
.cfi_def_cfa_offset 400064
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movslq row(%rip), %r14
movslq col(%rip), %rdi
imulq %r14, %rdi
shlq $2, %rdi
callq malloc
movq %rax, %rbx
shlq $2, %r14
movq %r14, %rdi
callq malloc
movq %rax, %r14
movl $.L.str, %edi
movl $.L.str.1, %esi
callq fopen
testq %rax, %rax
je .LBB1_1
# %bb.3:
movq %rax, %r15
movl $.Lstr, %edi
callq puts@PLT
movq %rsp, %r12
movq %r12, %rdi
movl $400000, %esi # imm = 0x61A80
movq %r15, %rdx
callq fgets
xorl %r13d, %r13d
.LBB1_5: # %.lr.ph49
# =>This Loop Header: Depth=1
# Child Loop BB1_7 Depth 2
movl $.L.str.4, %esi
movq %rax, %rdi
callq strtok
testq %rax, %rax
je .LBB1_4
# %bb.6: # %.lr.ph.preheader
# in Loop: Header=BB1_5 Depth=1
movslq %r13d, %rcx
leaq (%rbx,%rcx,4), %rbp
.LBB1_7: # %.lr.ph
# Parent Loop BB1_5 Depth=1
# => This Inner Loop Header: Depth=2
movq %rax, %rdi
callq atof
cvtsd2ss %xmm0, %xmm0
movss %xmm0, (%rbp)
movl $.L.str.4, %esi
xorl %edi, %edi
callq strtok
addq $4, %rbp
incl %r13d
testq %rax, %rax
jne .LBB1_7
.LBB1_4: # %.loopexit43
# in Loop: Header=BB1_5 Depth=1
movq %r12, %rdi
movl $400000, %esi # imm = 0x61A80
movq %r15, %rdx
callq fgets
testq %rax, %rax
jne .LBB1_5
# %bb.8: # %._crit_edge.loopexit
xorps %xmm0, %xmm0
cvtss2sd 20(%rbx), %xmm0
movl $.L.str.5, %edi
movb $1, %al
callq printf
movslq row(%rip), %rax
movslq col(%rip), %rsi
imulq %rax, %rsi
shlq $2, %rsi
movl $gmat, %edi
callq hipMalloc
xorl %r15d, %r15d
movl $.L.str.6, %edi
movl %eax, %esi
xorl %eax, %eax
callq printf
movslq row(%rip), %rsi
shlq $2, %rsi
movl $gsum, %edi
callq hipMalloc
movq gmat(%rip), %rdi
movslq row(%rip), %rax
movslq col(%rip), %rdx
imulq %rax, %rdx
shlq $2, %rdx
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq gsum(%rip), %rdi
movslq row(%rip), %rdx
shlq $2, %rdx
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movl $.Lstr.1, %edi
callq puts@PLT
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 511(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_10
# %bb.9:
movq gmat(%rip), %rdi
movq gsum(%rip), %rsi
movl row(%rip), %edx
movl col(%rip), %ecx
callq _Z26__device_stub__get_averagePfS_ii
.LBB1_10:
movq gmat(%rip), %rsi
movslq row(%rip), %rax
movslq col(%rip), %rdx
imulq %rax, %rdx
shlq $2, %rdx
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
movq gsum(%rip), %rsi
movslq row(%rip), %rdx
shlq $2, %rdx
movq %r14, %rdi
movl $2, %ecx
callq hipMemcpy
movl $.Lstr.2, %edi
callq puts@PLT
movl $.L.str.9, %edi
movl $.L.str.10, %esi
callq fopen
cmpl $0, row(%rip)
jle .LBB1_2
# %bb.11: # %.lr.ph55.preheader
movq %rax, %r14
xorl %ebp, %ebp
.LBB1_12: # %.lr.ph55
# =>This Loop Header: Depth=1
# Child Loop BB1_16 Depth 2
movl %ebp, %r15d
leal 1(%r15), %ebp
movl $.L.str.11, %esi
movq %r14, %rdi
movl %ebp, %edx
xorl %eax, %eax
callq fprintf
movl col(%rip), %eax
testl %eax, %eax
jle .LBB1_13
# %bb.15: # %.lr.ph52.preheader
# in Loop: Header=BB1_12 Depth=1
xorl %r12d, %r12d
.LBB1_16: # %.lr.ph52
# Parent Loop BB1_12 Depth=1
# => This Inner Loop Header: Depth=2
imull %r15d, %eax
cltq
addq %r12, %rax
xorps %xmm0, %xmm0
cvtss2sd (%rbx,%rax,4), %xmm0
movl $.L.str.12, %esi
movq %r14, %rdi
movb $1, %al
callq fprintf
movl col(%rip), %eax
incq %r12
cmpl %eax, %r12d
jl .LBB1_16
.LBB1_13: # %.loopexit
# in Loop: Header=BB1_12 Depth=1
cmpl row(%rip), %ebp
jl .LBB1_12
# %bb.14:
xorl %r15d, %r15d
jmp .LBB1_2
.LBB1_1:
movl $.L.str.2, %edi
xorl %eax, %eax
callq printf
movl $-1, %r15d
.LBB1_2: # %.loopexit42
movl %r15d, %eax
addq $400008, %rsp # imm = 0x61A88
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, %rdi
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11get_averagePfS_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type row,@object # @row
.data
.globl row
.p2align 2, 0x0
row:
.long 480000 # 0x75300
.size row, 4
.type col,@object # @col
.globl col
.p2align 2, 0x0
col:
.long 464 # 0x1d0
.size col, 4
.type gmat,@object # @gmat
.bss
.globl gmat
.p2align 3, 0x0
gmat:
.quad 0
.size gmat, 8
.type gsum,@object # @gsum
.globl gsum
.p2align 3, 0x0
gsum:
.quad 0
.size gsum, 8
.type _Z11get_averagePfS_ii,@object # @_Z11get_averagePfS_ii
.section .rodata,"a",@progbits
.globl _Z11get_averagePfS_ii
.p2align 3, 0x0
_Z11get_averagePfS_ii:
.quad _Z26__device_stub__get_averagePfS_ii
.size _Z11get_averagePfS_ii, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "matrix.csv"
.size .L.str, 11
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "r"
.size .L.str.1, 2
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "\n file opening failed "
.size .L.str.2, 23
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz ","
.size .L.str.4, 2
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "Load Finish%lf\n"
.size .L.str.5, 16
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "err is %d\n"
.size .L.str.6, 11
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "B1.csv"
.size .L.str.9, 7
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "w+"
.size .L.str.10, 3
.type .L.str.11,@object # @.str.11
.L.str.11:
.asciz "\n%d"
.size .L.str.11, 4
.type .L.str.12,@object # @.str.12
.L.str.12:
.asciz ",%lf "
.size .L.str.12, 6
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z11get_averagePfS_ii"
.size .L__unnamed_1, 22
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Start load csv"
.size .Lstr, 15
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "Start calaute"
.size .Lstr.1, 14
.type .Lstr.2,@object # @str.2
.Lstr.2:
.asciz "Now write"
.size .Lstr.2, 10
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z26__device_stub__get_averagePfS_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym gmat
.addrsig_sym gsum
.addrsig_sym _Z11get_averagePfS_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
```
| 4,663 | 5,300 |
64 |
Convert the following CUDA device assembly code to AMD device assembly:
```cudaasm
code for sm_80
Function : _Z31access_from_max_into_min_kernelPiS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
MOV R1, c[0x0][0x28] ;
EXIT ;
BRA 0x20;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
Function : _Z31access_from_min_into_max_kernelPiS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
MOV R1, c[0x0][0x28] ;
EXIT ;
BRA 0x20;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
```
|
```amdasm
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z31access_from_min_into_max_kernelPiS_ ; -- Begin function _Z31access_from_min_into_max_kernelPiS_
.globl _Z31access_from_min_into_max_kernelPiS_
.p2align 8
.type _Z31access_from_min_into_max_kernelPiS_,@function
_Z31access_from_min_into_max_kernelPiS_: ; @_Z31access_from_min_into_max_kernelPiS_
; %bb.0:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z31access_from_min_into_max_kernelPiS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 16
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 1
.amdhsa_next_free_sgpr 1
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z31access_from_min_into_max_kernelPiS_, .Lfunc_end0-_Z31access_from_min_into_max_kernelPiS_
; -- End function
.section .AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 4
; NumSgprs: 0
; NumVgprs: 0
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 0
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 1
; NumVGPRsForWavesPerEU: 1
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
.text
.protected _Z31access_from_max_into_min_kernelPiS_ ; -- Begin function _Z31access_from_max_into_min_kernelPiS_
.globl _Z31access_from_max_into_min_kernelPiS_
.p2align 8
.type _Z31access_from_max_into_min_kernelPiS_,@function
_Z31access_from_max_into_min_kernelPiS_: ; @_Z31access_from_max_into_min_kernelPiS_
; %bb.0:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z31access_from_max_into_min_kernelPiS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 16
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 1
.amdhsa_next_free_sgpr 1
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z31access_from_max_into_min_kernelPiS_, .Lfunc_end1-_Z31access_from_max_into_min_kernelPiS_
; -- End function
.section .AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 4
; NumSgprs: 0
; NumVgprs: 0
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 0
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 1
; NumVGPRsForWavesPerEU: 1
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object ; @__hip_cuid_
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0 ; 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 16
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z31access_from_min_into_max_kernelPiS_
.private_segment_fixed_size: 0
.sgpr_count: 0
.sgpr_spill_count: 0
.symbol: _Z31access_from_min_into_max_kernelPiS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 0
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 16
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z31access_from_max_into_min_kernelPiS_
.private_segment_fixed_size: 0
.sgpr_count: 0
.sgpr_spill_count: 0
.symbol: _Z31access_from_max_into_min_kernelPiS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 0
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
```
| 226 | 2,900 |
65 |
Convert the following CUDA host assembly code to AMD host assembly:
```cudaasm
.file "tmpxft_000d411a_00000000-6_two_array_global.cudafe1.cpp"
.text
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z53__device_stub__Z31access_from_min_into_max_kernelPiS_PiS_
.type _Z53__device_stub__Z31access_from_min_into_max_kernelPiS_PiS_, @function
_Z53__device_stub__Z31access_from_min_into_max_kernelPiS_PiS_:
.LFB2082:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z31access_from_min_into_max_kernelPiS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z53__device_stub__Z31access_from_min_into_max_kernelPiS_PiS_, .-_Z53__device_stub__Z31access_from_min_into_max_kernelPiS_PiS_
.globl _Z31access_from_min_into_max_kernelPiS_
.type _Z31access_from_min_into_max_kernelPiS_, @function
_Z31access_from_min_into_max_kernelPiS_:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z53__device_stub__Z31access_from_min_into_max_kernelPiS_PiS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z31access_from_min_into_max_kernelPiS_, .-_Z31access_from_min_into_max_kernelPiS_
.globl _Z53__device_stub__Z31access_from_max_into_min_kernelPiS_PiS_
.type _Z53__device_stub__Z31access_from_max_into_min_kernelPiS_PiS_, @function
_Z53__device_stub__Z31access_from_max_into_min_kernelPiS_PiS_:
.LFB2084:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z31access_from_max_into_min_kernelPiS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z53__device_stub__Z31access_from_max_into_min_kernelPiS_PiS_, .-_Z53__device_stub__Z31access_from_max_into_min_kernelPiS_PiS_
.globl _Z31access_from_max_into_min_kernelPiS_
.type _Z31access_from_max_into_min_kernelPiS_, @function
_Z31access_from_max_into_min_kernelPiS_:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z53__device_stub__Z31access_from_max_into_min_kernelPiS_PiS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z31access_from_max_into_min_kernelPiS_, .-_Z31access_from_max_into_min_kernelPiS_
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $56, %rsp
.cfi_def_cfa_offset 80
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movq %rsp, %rdi
movl $4096, %esi
call cudaMalloc@PLT
leaq 8(%rsp), %rdi
movl $4096, %esi
call cudaMalloc@PLT
movq (%rsp), %rbx
movq 8(%rsp), %rbp
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L23
.L20:
movq (%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
call cudaDeviceReset@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L24
movl $0, %eax
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
cmpq %rbp, %rbx
movq %rbp, %rsi
cmovnb %rbx, %rsi
movq %rbp, %rdi
cmovbe %rbx, %rdi
call _Z53__device_stub__Z31access_from_max_into_min_kernelPiS_PiS_
jmp .L20
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z31access_from_max_into_min_kernelPiS_"
.align 8
.LC1:
.string "_Z31access_from_min_into_max_kernelPiS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z31access_from_max_into_min_kernelPiS_(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z31access_from_min_into_max_kernelPiS_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
```
|
```amdasm
.text
.file "two_array_global.hip"
.globl _Z46__device_stub__access_from_min_into_max_kernelPiS_ # -- Begin function _Z46__device_stub__access_from_min_into_max_kernelPiS_
.type _Z46__device_stub__access_from_min_into_max_kernelPiS_,@function
_Z46__device_stub__access_from_min_into_max_kernelPiS_: # @_Z46__device_stub__access_from_min_into_max_kernelPiS_
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $80, %rsp
.cfi_def_cfa_offset 128
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 24(%rsp), %rax
movq %rdi, (%rax)
leaq 16(%rsp), %rcx
movq %rsi, (%rcx)
leaq 64(%rsp), %rbx
movq %rax, (%rbx)
movq %rcx, 8(%rbx)
leaq 48(%rsp), %r14
leaq 32(%rsp), %r15
leaq 8(%rsp), %r12
movq %rsp, %r13
movq %r14, %rdi
movq %r15, %rsi
movq %r12, %rdx
movq %r13, %rcx
callq __hipPopCallConfiguration
movq (%r14), %rsi
movl 8(%r14), %edx
movq (%r15), %rcx
movl 8(%r15), %r8d
movl $_Z31access_from_min_into_max_kernelPiS_, %edi
movq %rbx, %r9
pushq (%r13)
.cfi_adjust_cfa_offset 8
pushq (%r12)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $96, %rsp
.cfi_adjust_cfa_offset -96
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z46__device_stub__access_from_min_into_max_kernelPiS_, .Lfunc_end0-_Z46__device_stub__access_from_min_into_max_kernelPiS_
.cfi_endproc
# -- End function
.globl _Z46__device_stub__access_from_max_into_min_kernelPiS_ # -- Begin function _Z46__device_stub__access_from_max_into_min_kernelPiS_
.type _Z46__device_stub__access_from_max_into_min_kernelPiS_,@function
_Z46__device_stub__access_from_max_into_min_kernelPiS_: # @_Z46__device_stub__access_from_max_into_min_kernelPiS_
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $80, %rsp
.cfi_def_cfa_offset 128
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 24(%rsp), %rax
movq %rdi, (%rax)
leaq 16(%rsp), %rcx
movq %rsi, (%rcx)
leaq 64(%rsp), %rbx
movq %rax, (%rbx)
movq %rcx, 8(%rbx)
leaq 48(%rsp), %r14
leaq 32(%rsp), %r15
leaq 8(%rsp), %r12
movq %rsp, %r13
movq %r14, %rdi
movq %r15, %rsi
movq %r12, %rdx
movq %r13, %rcx
callq __hipPopCallConfiguration
movq (%r14), %rsi
movl 8(%r14), %edx
movq (%r15), %rcx
movl 8(%r15), %r8d
movl $_Z31access_from_max_into_min_kernelPiS_, %edi
movq %rbx, %r9
pushq (%r13)
.cfi_adjust_cfa_offset 8
pushq (%r12)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $96, %rsp
.cfi_adjust_cfa_offset -96
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z46__device_stub__access_from_max_into_min_kernelPiS_, .Lfunc_end1-_Z46__device_stub__access_from_max_into_min_kernelPiS_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $16, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 8(%rsp), %rbx
movl $4096, %esi # imm = 0x1000
movq %rbx, %rdi
callq hipMalloc
movq %rsp, %r14
movl $4096, %esi # imm = 0x1000
movq %r14, %rdi
callq hipMalloc
movq (%rbx), %r15
movq (%r14), %rbx
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_2
# %bb.1:
cmpq %rbx, %r15
movq %r15, %rsi
cmovbq %rbx, %rsi
cmovbq %r15, %rbx
movq %rbx, %rdi
callq _Z46__device_stub__access_from_max_into_min_kernelPiS_
.LBB2_2:
movq 8(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipFree
callq hipDeviceReset
xorl %eax, %eax
addq $16, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
movq __hip_gpubin_handle(%rip), %rbx
testq %rbx, %rbx
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, %rbx
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z31access_from_min_into_max_kernelPiS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z31access_from_max_into_min_kernelPiS_, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z31access_from_min_into_max_kernelPiS_,@object # @_Z31access_from_min_into_max_kernelPiS_
.section .rodata,"a",@progbits
.globl _Z31access_from_min_into_max_kernelPiS_
.p2align 3, 0x0
_Z31access_from_min_into_max_kernelPiS_:
.quad _Z46__device_stub__access_from_min_into_max_kernelPiS_
.size _Z31access_from_min_into_max_kernelPiS_, 8
.type _Z31access_from_max_into_min_kernelPiS_,@object # @_Z31access_from_max_into_min_kernelPiS_
.globl _Z31access_from_max_into_min_kernelPiS_
.p2align 3, 0x0
_Z31access_from_max_into_min_kernelPiS_:
.quad _Z46__device_stub__access_from_max_into_min_kernelPiS_
.size _Z31access_from_max_into_min_kernelPiS_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z31access_from_min_into_max_kernelPiS_"
.size .L__unnamed_1, 40
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z31access_from_max_into_min_kernelPiS_"
.size .L__unnamed_2, 40
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z46__device_stub__access_from_min_into_max_kernelPiS_
.addrsig_sym _Z46__device_stub__access_from_max_into_min_kernelPiS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z31access_from_min_into_max_kernelPiS_
.addrsig_sym _Z31access_from_max_into_min_kernelPiS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
```
| 3,564 | 3,844 |
68 |
Convert the following CUDA device assembly code to AMD device assembly:
```cudaasm
code for sm_80
Function : _Z14actiune_threadPfS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
MOV R1, c[0x0][0x28] ;
S2R R9, SR_CTAID.X ;
ISETP.LT.AND P0, PT, RZ, c[0x0][0x178], PT ;
HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ;
ULDC.64 UR4, c[0x0][0x118] ;
S2R R0, SR_TID.X ;
S2R R5, SR_CTAID.Y ;
@!P0 MOV R15, RZ ;
LEA R9, R9, R0, 0x5 ;
IMAD R6, R5, c[0x0][0x178], R9 ;
IMAD.WIDE R6, R6, R7, c[0x0][0x170] ;
@!P0 BRA 0x810 ;
MOV R2, 0x4 ;
IMAD R5, R5, c[0x0][0x178], R0 ;
MOV R15, RZ ;
MOV R3, RZ ;
IMAD.WIDE R4, R5, R2, c[0x0][0x160] ;
IMAD.WIDE R8, R9, R2, c[0x0][0x168] ;
LDG.E R17, [R4.64] ;
IMAD.WIDE R10, R2, c[0x0][0x178], R8 ;
LDG.E R14, [R8.64] ;
IMAD.WIDE R20, R2.reuse, c[0x0][0x178], R10 ;
LDG.E R12, [R10.64] ;
LDG.E R13, [R20.64] ;
IMAD.WIDE R24, R2, c[0x0][0x178], R20 ;
LDG.E R16, [R24.64] ;
IMAD.WIDE R36, R2, c[0x0][0x178], R24 ;
LDG.E R19, [R36.64] ;
IMAD.WIDE R28, R2, c[0x0][0x178], R36 ;
IMAD.WIDE R30, R2.reuse, c[0x0][0x178], R28 ;
LDG.E R28, [R28.64] ;
LDG.E R27, [R30.64] ;
IMAD.WIDE R22, R2, c[0x0][0x178], R30 ;
LDG.E R26, [R22.64] ;
IMAD.WIDE R34, R2, c[0x0][0x178], R22 ;
LDG.E R25, [R34.64] ;
IMAD.WIDE R32, R2, c[0x0][0x178], R34 ;
LDG.E R24, [R32.64] ;
IMAD.WIDE R20, R2, c[0x0][0x178], R32 ;
IMAD.WIDE R36, R2.reuse, c[0x0][0x178], R20 ;
LDG.E R21, [R20.64] ;
IMAD.WIDE R30, R2, c[0x0][0x178], R36 ;
LDG.E R22, [R36.64] ;
LDG.E R23, [R30.64] ;
STS [R0.X4], R17 ;
LDS.128 R8, [RZ] ;
FFMA R8, R8, R14, R15 ;
FFMA R8, R12, R9, R8 ;
FFMA R10, R13, R10, R8 ;
LDS.128 R12, [0x10] ;
IMAD.WIDE R8, R2, c[0x0][0x178], R30 ;
LDG.E R18, [R8.64] ;
IMAD.WIDE R34, R2, c[0x0][0x178], R8 ;
LDG.E R17, [R34.64] ;
IMAD.WIDE R32, R2, c[0x0][0x178], R34 ;
FFMA R11, R16, R11, R10 ;
LDG.E R16, [R32.64] ;
IMAD.WIDE R36, R2, c[0x0][0x178], R32 ;
FFMA R11, R12, R19, R11 ;
LDG.E R19, [R36.64] ;
IMAD.WIDE R30, R2, c[0x0][0x178], R36 ;
LDG.E R20, [R30.64] ;
FFMA R11, R28, R13, R11 ;
FFMA R14, R27, R14, R11 ;
LDS.128 R8, [0x20] ;
FFMA R14, R26, R15, R14 ;
IMAD.WIDE R34, R2, c[0x0][0x178], R30 ;
LDG.E R29, [R34.64] ;
IMAD.WIDE R32, R2, c[0x0][0x178], R34 ;
LDG.E R28, [R32.64] ;
FFMA R8, R8, R25, R14 ;
LDS.128 R12, [0x30] ;
FFMA R8, R24, R9, R8 ;
IMAD.WIDE R26, R2, c[0x0][0x178], R32 ;
FFMA R8, R21, R10, R8 ;
IMAD.WIDE R36, R2, c[0x0][0x178], R26 ;
LDG.E R27, [R26.64] ;
FFMA R8, R22, R11, R8 ;
IMAD.WIDE R32, R2, c[0x0][0x178], R36 ;
LDG.E R25, [R32.64] ;
LDG.E R26, [R36.64] ;
IMAD.WIDE R34, R2, c[0x0][0x178], R32 ;
LDG.E R24, [R34.64] ;
FFMA R12, R12, R23, R8 ;
LDS.128 R8, [0x40] ;
IMAD.WIDE R30, R2, c[0x0][0x178], R34 ;
IMAD.WIDE R22, R2, c[0x0][0x178], R30 ;
FFMA R13, R18, R13, R12 ;
FFMA R13, R17, R14, R13 ;
LDG.E R17, [R30.64] ;
FFMA R13, R16, R15, R13 ;
IMAD.WIDE R14, R2, c[0x0][0x178], R22 ;
LDG.E R16, [R22.64] ;
FFMA R8, R8, R19, R13 ;
IMAD.WIDE R12, R2.reuse, c[0x0][0x178], R14 ;
LDG.E R19, [R14.64] ;
LDG.E R18, [R12.64] ;
IMAD.WIDE R36, R2, c[0x0][0x178], R12 ;
LDG.E R21, [R36.64] ;
IMAD.WIDE R34, R2, c[0x0][0x178], R36 ;
LDS.128 R12, [0x50] ;
FFMA R9, R20, R9, R8 ;
IMAD.WIDE R32, R2.reuse, c[0x0][0x178], R34 ;
LDG.E R20, [R34.64] ;
LDG.E R23, [R32.64] ;
IMAD.WIDE R30, R2, c[0x0][0x178], R32 ;
LDG.E R22, [R30.64] ;
FFMA R9, R29, R10, R9 ;
FFMA R9, R28, R11, R9 ;
FFMA R9, R12, R27, R9 ;
FFMA R13, R26, R13, R9 ;
LDS.128 R8, [0x60] ;
FFMA R13, R25, R14, R13 ;
FFMA R24, R24, R15, R13 ;
LDS.128 R12, [0x70] ;
IADD3 R3, R3, 0x20, RZ ;
ISETP.GE.AND P0, PT, R3, c[0x0][0x178], PT ;
IADD3 R4, P1, R4, 0x80, RZ ;
IADD3.X R5, RZ, R5, RZ, P1, !PT ;
FFMA R8, R8, R17, R24 ;
FFMA R8, R16, R9, R8 ;
FFMA R8, R19, R10, R8 ;
FFMA R8, R18, R11, R8 ;
FFMA R8, R12, R21, R8 ;
FFMA R8, R20, R13, R8 ;
FFMA R8, R23, R14, R8 ;
FFMA R15, R22, R15, R8 ;
IMAD.WIDE R8, R2, c[0x0][0x178], R30 ;
@!P0 BRA 0x120 ;
STG.E [R6.64], R15 ;
EXIT ;
BRA 0x830;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
```
|
```amdasm
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z14actiune_threadPfS_S_i ; -- Begin function _Z14actiune_threadPfS_S_i
.globl _Z14actiune_threadPfS_S_i
.p2align 8
.type _Z14actiune_threadPfS_S_i,@function
_Z14actiune_threadPfS_S_i: ; @_Z14actiune_threadPfS_S_i
; %bb.0:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x18
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
v_lshl_add_u32 v2, s14, 5, v0
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s2, 1
s_mul_i32 s15, s15, s2
s_cbranch_scc1 .LBB0_5
; %bb.1: ; %.lr.ph
v_dual_mov_b32 v3, 0 :: v_dual_add_nc_u32 v4, s15, v0
v_dual_mov_b32 v6, v2 :: v_dual_lshlrev_b32 v5, 2, v0
s_lshl_b32 s3, s2, 5
s_mov_b32 s8, 0
.LBB0_2: ; =>This Loop Header: Depth=1
; Child Loop BB0_3 Depth 2
s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
v_add_nc_u32_e32 v0, s8, v4
s_mov_b32 s9, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v1, 31, v0
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
global_load_b32 v1, v[0:1], off
v_mov_b32_e32 v0, v6
s_waitcnt vmcnt(0)
ds_store_b32 v5, v1
.LBB0_3: ; Parent Loop BB0_2 Depth=1
; => This Inner Loop Header: Depth=2
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[7:8], 2, v[0:1]
v_add_nc_u32_e32 v0, s2, v0
v_add_co_u32 v7, vcc_lo, s6, v7
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
v_add_co_ci_u32_e32 v8, vcc_lo, s7, v8, vcc_lo
global_load_b32 v1, v[7:8], off
v_mov_b32_e32 v7, s9
s_add_i32 s9, s9, 4
s_cmpk_eq_i32 s9, 0x80
ds_load_b32 v7, v7
s_waitcnt vmcnt(0) lgkmcnt(0)
v_fmac_f32_e32 v3, v1, v7
s_cbranch_scc0 .LBB0_3
; %bb.4: ; %.loopexit
; in Loop: Header=BB0_2 Depth=1
v_add_nc_u32_e32 v6, s3, v6
s_add_i32 s8, s8, 32
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_lt_i32 s8, s2
s_cbranch_scc1 .LBB0_2
s_branch .LBB0_6
.LBB0_5:
v_mov_b32_e32 v3, 0
.LBB0_6: ; %Flow51
v_add_nc_u32_e32 v0, s15, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v1, 31, v0
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v3, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z14actiune_threadPfS_S_i
.amdhsa_group_segment_fixed_size 128
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 28
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z14actiune_threadPfS_S_i, .Lfunc_end0-_Z14actiune_threadPfS_S_i
; -- End function
.section .AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 304
; NumSgprs: 18
; NumVgprs: 9
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 128 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 9
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object ; @__hip_cuid_
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0 ; 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 128
.kernarg_segment_align: 8
.kernarg_segment_size: 28
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z14actiune_threadPfS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z14actiune_threadPfS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
```
| 2,621 | 2,884 |
69 |
Convert the following CUDA host assembly code to AMD host assembly:
```cudaasm
.file "tmpxft_000aa7e6_00000000-6_cudaCode.cudafe1.cpp"
.text
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2030:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z39__device_stub__Z14actiune_threadPfS_S_iPfS_S_i
.type _Z39__device_stub__Z14actiune_threadPfS_S_iPfS_S_i, @function
_Z39__device_stub__Z14actiune_threadPfS_S_iPfS_S_i:
.LFB2052:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z14actiune_threadPfS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2052:
.size _Z39__device_stub__Z14actiune_threadPfS_S_iPfS_S_i, .-_Z39__device_stub__Z14actiune_threadPfS_S_iPfS_S_i
.globl _Z14actiune_threadPfS_S_i
.type _Z14actiune_threadPfS_S_i, @function
_Z14actiune_threadPfS_S_i:
.LFB2053:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z39__device_stub__Z14actiune_threadPfS_S_iPfS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2053:
.size _Z14actiune_threadPfS_S_i, .-_Z14actiune_threadPfS_S_i
.globl launch_actiune_thread
.type launch_actiune_thread, @function
launch_actiune_thread:
.LFB2027:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $24, %rsp
.cfi_def_cfa_offset 64
movq %rdi, %rbx
movq %rsi, %rbp
movq %rdx, %r12
movl %ecx, %r13d
movq %r8, %rdi
movl %r9d, %esi
movl 72(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 64(%rsp), %rdx
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L14
.L12:
call cudaGetLastError@PLT
addq $24, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
movl %r13d, %ecx
movq %r12, %rdx
movq %rbp, %rsi
movq %rbx, %rdi
call _Z39__device_stub__Z14actiune_threadPfS_S_iPfS_S_i
jmp .L12
.cfi_endproc
.LFE2027:
.size launch_actiune_thread, .-launch_actiune_thread
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z14actiune_threadPfS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2055:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z14actiune_threadPfS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2055:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
```
|
```amdasm
.text
.file "cudaCode.hip"
.globl _Z29__device_stub__actiune_threadPfS_S_i # -- Begin function _Z29__device_stub__actiune_threadPfS_S_i
.type _Z29__device_stub__actiune_threadPfS_S_i,@function
_Z29__device_stub__actiune_threadPfS_S_i: # @_Z29__device_stub__actiune_threadPfS_S_i
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $112, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 40(%rsp), %rax
movq %rdi, (%rax)
leaq 32(%rsp), %rdi
movq %rsi, (%rdi)
leaq 24(%rsp), %rsi
movq %rdx, (%rsi)
leaq 4(%rsp), %rdx
movl %ecx, (%rdx)
leaq 80(%rsp), %rbx
movq %rax, (%rbx)
movq %rdi, 8(%rbx)
movq %rsi, 16(%rbx)
movq %rdx, 24(%rbx)
leaq 64(%rsp), %r14
leaq 48(%rsp), %r15
leaq 16(%rsp), %r12
leaq 8(%rsp), %r13
movq %r14, %rdi
movq %r15, %rsi
movq %r12, %rdx
movq %r13, %rcx
callq __hipPopCallConfiguration
movq (%r14), %rsi
movl 8(%r14), %edx
movq (%r15), %rcx
movl 8(%r15), %r8d
movl $_Z14actiune_threadPfS_S_i, %edi
movq %rbx, %r9
pushq (%r13)
.cfi_adjust_cfa_offset 8
pushq (%r12)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $128, %rsp
.cfi_adjust_cfa_offset -128
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z29__device_stub__actiune_threadPfS_S_i, .Lfunc_end0-_Z29__device_stub__actiune_threadPfS_S_i
.cfi_endproc
# -- End function
.globl launch_actiune_thread # -- Begin function launch_actiune_thread
.type launch_actiune_thread,@function
launch_actiune_thread: # @launch_actiune_thread
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
pushq %rax
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl %ecx, %ebx
movq %rdx, %r14
movq %rsi, %r15
movq %rdi, %r12
movq 48(%rsp), %rdx
movl 56(%rsp), %ecx
movq %r8, %rdi
movl %r9d, %esi
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq %r12, %rdi
movq %r15, %rsi
movq %r14, %rdx
movl %ebx, %ecx
callq _Z29__device_stub__actiune_threadPfS_S_i
.LBB1_2:
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
jmp hipGetLastError # TAILCALL
.Lfunc_end1:
.size launch_actiune_thread, .Lfunc_end1-launch_actiune_thread
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, %rdi
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z14actiune_threadPfS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z14actiune_threadPfS_S_i,@object # @_Z14actiune_threadPfS_S_i
.section .rodata,"a",@progbits
.globl _Z14actiune_threadPfS_S_i
.p2align 3, 0x0
_Z14actiune_threadPfS_S_i:
.quad _Z29__device_stub__actiune_threadPfS_S_i
.size _Z14actiune_threadPfS_S_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z14actiune_threadPfS_S_i"
.size .L__unnamed_1, 26
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z29__device_stub__actiune_threadPfS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z14actiune_threadPfS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
```
| 2,493 | 2,683 |
70 |
Convert the following CUDA device assembly code to AMD device assembly:
```cudaasm
code for sm_80
Function : _Z14matrixMultiplyPfS_S_iiiiii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
MOV R1, c[0x0][0x28] ;
S2R R5, SR_CTAID.X ;
MOV R2, c[0x0][0x180] ;
ULDC.64 UR6, c[0x0][0x118] ;
HFMA2.MMA R23, -RZ, RZ, 0, 0 ;
S2R R12, SR_TID.X ;
ISETP.GE.AND P1, PT, R2, -0xc, PT ;
S2R R11, SR_CTAID.Y ;
S2R R10, SR_TID.Y ;
IMAD R0, R5, 0xe, R12 ;
ISETP.GE.AND P0, PT, R0, c[0x0][0x184], PT ;
IMAD R11, R11, 0xe, R10 ;
ISETP.GE.OR P0, PT, R11, c[0x0][0x178], P0 ;
@!P1 BRA 0x5b0 ;
IADD3 R3, R2, -0x1, RZ ;
IMAD.MOV.U32 R2, RZ, RZ, RZ ;
MOV R7, 0x4 ;
IMAD R4, R11, c[0x0][0x17c], R12 ;
MOV R23, RZ ;
IMAD.HI R18, R3, -0x6db6db6d, R2 ;
LEA R19, R12, 0x310, 0x2 ;
UMOV UR4, 0xffffffff ;
IMAD R16, R10, c[0x0][0x184], R12 ;
IMAD.WIDE R2, R4, R7, c[0x0][0x160] ;
IMAD R16, R5, 0xe, R16 ;
SHF.R.U32.HI R5, RZ, 0x1f, R18 ;
IMAD R15, R10, 0x38, RZ ;
MOV R14, R2 ;
MOV R13, R3 ;
IMAD R17, R12, 0x4, R15 ;
LEA.HI.SX32 R18, R18, R5, 0x1d ;
ISETP.GE.AND P1, PT, R10, c[0x0][0x180], PT ;
HFMA2.MMA R20, -RZ, RZ, 0, 0 ;
ISETP.GE.AND P2, PT, R12, c[0x0][0x180], PT ;
ISETP.GE.OR P1, PT, R0, c[0x0][0x184], P1 ;
ISETP.GE.OR P2, PT, R11, c[0x0][0x178], P2 ;
MOV R22, RZ ;
@!P1 MOV R3, 0x4 ;
@!P2 IMAD.MOV.U32 R4, RZ, RZ, R14 ;
@!P2 MOV R5, R13 ;
@!P1 IMAD.WIDE R2, R16, R3, c[0x0][0x168] ;
@!P2 LDG.E R20, [R4.64] ;
@!P1 LDG.E R22, [R2.64] ;
UIADD3 UR4, UR4, 0x1, URZ ;
IADD3 R14, P2, R14, 0x38, RZ ;
IADD3 R10, R10, 0xe, RZ ;
IADD3 R12, R12, 0xe, RZ ;
ISETP.LE.AND P1, PT, R18, UR4, PT ;
IADD3.X R13, RZ, R13, RZ, P2, !PT ;
STS [R17], R20 ;
STS [R17+0x310], R22 ;
BAR.SYNC.DEFER_BLOCKING 0x0 ;
LDS R26, [R19] ;
LDS.64 R6, [R15] ;
LDS R27, [R19+0x38] ;
LDS R25, [R19+0x70] ;
LDS.64 R8, [R15+0x8] ;
LDS R24, [R19+0xa8] ;
LDS R21, [R19+0xe0] ;
LDS.64 R4, [R15+0x10] ;
LDS R20, [R19+0x118] ;
LDS.64 R2, [R15+0x18] ;
LDS R22, [R19+0x188] ;
FFMA R6, R26, R6, R23 ;
LDS R23, [R19+0x150] ;
FFMA R6, R27, R7, R6 ;
FFMA R8, R25, R8, R6 ;
LDS R25, [R19+0x1c0] ;
FFMA R8, R24, R9, R8 ;
LDS.64 R6, [R15+0x20] ;
LDS R24, [R19+0x1f8] ;
FFMA R4, R21, R4, R8 ;
LDS R21, [R19+0x230] ;
FFMA R4, R20, R5, R4 ;
LDS.64 R8, [R15+0x28] ;
LDS R20, [R19+0x268] ;
FFMA R26, R23, R2, R4 ;
LDS R23, [R19+0x2a0] ;
FFMA R3, R22, R3, R26 ;
LDS.64 R4, [R15+0x30] ;
LDS R2, [R19+0x2d8] ;
FFMA R3, R25, R6, R3 ;
FFMA R3, R24, R7, R3 ;
HFMA2.MMA R7, -RZ, RZ, 0, 8.3446502685546875e-07 ;
FFMA R3, R21, R8, R3 ;
IMAD R16, R7, c[0x0][0x184], R16 ;
FFMA R3, R20, R9, R3 ;
FFMA R23, R23, R4, R3 ;
FFMA R23, R2, R5, R23 ;
BAR.SYNC.DEFER_BLOCKING 0x0 ;
@!P1 BRA 0x1f0 ;
@P0 EXIT ;
MOV R3, 0x4 ;
IMAD R2, R11, c[0x0][0x184], R0 ;
IMAD.WIDE R2, R2, R3, c[0x0][0x170] ;
STG.E [R2.64], R23 ;
EXIT ;
BRA 0x610;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
```
|
```amdasm
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z14matrixMultiplyPfS_S_iiiiii ; -- Begin function _Z14matrixMultiplyPfS_S_iiiiii
.globl _Z14matrixMultiplyPfS_S_iiiiii
.p2align 8
.type _Z14matrixMultiplyPfS_S_iiiiii,@function
_Z14matrixMultiplyPfS_S_iiiiii: ; @_Z14matrixMultiplyPfS_S_iiiiii
; %bb.0:
s_clause 0x2
s_load_b128 s[4:7], s[0:1], 0x18
s_load_b128 s[8:11], s[0:1], 0x0
s_load_b64 s[2:3], s[0:1], 0x10
v_bfe_u32 v3, v0, 10, 10
v_and_b32_e32 v4, 0x3ff, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
v_mad_u64_u32 v[0:1], null, s15, 14, v[3:4]
v_mad_u64_u32 v[1:2], null, s14, 14, v[4:5]
v_mov_b32_e32 v2, 0
s_waitcnt lgkmcnt(0)
v_cmp_gt_i32_e32 vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_3)
v_cmp_gt_i32_e64 s0, s7, v1
s_cmp_lt_i32 s6, -12
s_cbranch_scc1 .LBB0_10
; %bb.1: ; %.lr.ph
v_lshlrev_b32_e32 v2, 2, v4
s_add_i32 s1, s6, -1
v_mul_lo_u32 v6, v0, s5
s_mul_hi_i32 s5, s1, 0x92492493
v_mul_u32_u24_e32 v5, 56, v3
v_add_nc_u32_e32 v7, 0x310, v2
s_add_i32 s5, s5, s1
v_mad_u32_u24 v8, v3, 56, v2
v_mov_b32_e32 v2, 0
s_lshr_b32 s1, s5, 31
v_mad_u32_u24 v9, v3, 56, v7
s_ashr_i32 s5, s5, 3
s_mov_b32 s12, 0
s_add_i32 s5, s5, s1
.LBB0_2: ; =>This Loop Header: Depth=1
; Child Loop BB0_7 Depth 2
s_mul_i32 s13, s12, 14
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_mov_b32 v10, 0 :: v_dual_add_nc_u32 v11, s13, v4
v_cmp_gt_i32_e64 s1, s6, v11
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s1, vcc_lo, s1
s_and_saveexec_b32 s14, s1
s_cbranch_execz .LBB0_4
; %bb.3: ; in Loop: Header=BB0_2 Depth=1
v_add_nc_u32_e32 v10, v11, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v11, 31, v10
v_lshlrev_b64 v[10:11], 2, v[10:11]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v10, s1, s8, v10
v_add_co_ci_u32_e64 v11, s1, s9, v11, s1
global_load_b32 v10, v[10:11], off
.LBB0_4: ; %._crit_edge70
; in Loop: Header=BB0_2 Depth=1
s_or_b32 exec_lo, exec_lo, s14
v_dual_mov_b32 v12, 0 :: v_dual_add_nc_u32 v11, s13, v3
s_waitcnt vmcnt(0)
ds_store_b32 v8, v10
v_cmp_gt_i32_e64 s1, s6, v11
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s1, s1, s0
s_and_saveexec_b32 s13, s1
s_cbranch_execz .LBB0_6
; %bb.5: ; in Loop: Header=BB0_2 Depth=1
v_mad_u64_u32 v[12:13], null, v11, s7, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v13, 31, v12
v_lshlrev_b64 v[10:11], 2, v[12:13]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v10, s1, s10, v10
v_add_co_ci_u32_e64 v11, s1, s11, v11, s1
global_load_b32 v12, v[10:11], off
.LBB0_6: ; in Loop: Header=BB0_2 Depth=1
s_or_b32 exec_lo, exec_lo, s13
v_mov_b32_e32 v10, v7
s_mov_b32 s1, 0
s_waitcnt vmcnt(0)
ds_store_b32 v9, v12
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
.LBB0_7: ; Parent Loop BB0_2 Depth=1
; => This Inner Loop Header: Depth=2
v_add_nc_u32_e32 v11, s1, v5
s_add_i32 s1, s1, 4
ds_load_b32 v12, v10
ds_load_b32 v11, v11
v_add_nc_u32_e32 v10, 56, v10
s_cmp_eq_u32 s1, 56
s_waitcnt lgkmcnt(0)
v_fmac_f32_e32 v2, v11, v12
s_cbranch_scc0 .LBB0_7
; %bb.8: ; in Loop: Header=BB0_2 Depth=1
s_add_i32 s1, s12, 1
s_cmp_eq_u32 s12, s5
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB0_10
; %bb.9: ; in Loop: Header=BB0_2 Depth=1
s_mov_b32 s12, s1
s_branch .LBB0_2
.LBB0_10: ; %Flow99
v_cmp_gt_i32_e32 vcc_lo, s4, v0
v_cmp_gt_i32_e64 s0, s7, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s0, vcc_lo, s0
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_12
; %bb.11:
v_mad_u64_u32 v[3:4], null, v0, s7, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v4, 31, v3
v_lshlrev_b64 v[0:1], 2, v[3:4]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_store_b32 v[0:1], v2, off
.LBB0_12:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z14matrixMultiplyPfS_S_iiiiii
.amdhsa_group_segment_fixed_size 1568
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 48
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 14
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z14matrixMultiplyPfS_S_iiiiii, .Lfunc_end0-_Z14matrixMultiplyPfS_S_iiiiii
; -- End function
.section .AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 564
; NumSgprs: 18
; NumVgprs: 14
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 1568 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 14
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object ; @__hip_cuid_
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0 ; 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 36
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: by_value
- .offset: 44
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 1568
.kernarg_segment_align: 8
.kernarg_segment_size: 48
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z14matrixMultiplyPfS_S_iiiiii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z14matrixMultiplyPfS_S_iiiiii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 14
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
```
| 1,837 | 3,996 |
71 |
Convert the following CUDA host assembly code to AMD host assembly:
```cudaasm
.file "tmpxft_0002d5d2_00000000-6_matrixMultiply.cudafe1.cpp"
.text
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z44__device_stub__Z14matrixMultiplyPfS_S_iiiiiiPfS_S_iiiiii
.type _Z44__device_stub__Z14matrixMultiplyPfS_S_iiiiiiPfS_S_iiiiii, @function
_Z44__device_stub__Z14matrixMultiplyPfS_S_iiiiiiPfS_S_iiiiii:
.LFB2051:
.cfi_startproc
endbr64
subq $200, %rsp
.cfi_def_cfa_offset 208
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
leaq 208(%rsp), %rax
movq %rax, 160(%rsp)
leaq 216(%rsp), %rax
movq %rax, 168(%rsp)
leaq 224(%rsp), %rax
movq %rax, 176(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 216
pushq 56(%rsp)
.cfi_def_cfa_offset 224
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z14matrixMultiplyPfS_S_iiiiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 208
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z44__device_stub__Z14matrixMultiplyPfS_S_iiiiiiPfS_S_iiiiii, .-_Z44__device_stub__Z14matrixMultiplyPfS_S_iiiiiiPfS_S_iiiiii
.globl _Z14matrixMultiplyPfS_S_iiiiii
.type _Z14matrixMultiplyPfS_S_iiiiii, @function
_Z14matrixMultiplyPfS_S_iiiiii:
.LFB2052:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 40
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 48
call _Z44__device_stub__Z14matrixMultiplyPfS_S_iiiiiiPfS_S_iiiiii
addq $40, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z14matrixMultiplyPfS_S_iiiiii, .-_Z14matrixMultiplyPfS_S_iiiiii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z14matrixMultiplyPfS_S_iiiiii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z14matrixMultiplyPfS_S_iiiiii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
```
|
```amdasm
.text
.file "matrixMultiply.hip"
.globl _Z29__device_stub__matrixMultiplyPfS_S_iiiiii # -- Begin function _Z29__device_stub__matrixMultiplyPfS_S_iiiiii
.type _Z29__device_stub__matrixMultiplyPfS_S_iiiiii,@function
_Z29__device_stub__matrixMultiplyPfS_S_iiiiii: # @_Z29__device_stub__matrixMultiplyPfS_S_iiiiii
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $176, %rsp
.cfi_def_cfa_offset 224
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 56(%rsp), %rax
movq %rdi, (%rax)
leaq 48(%rsp), %rdi
movq %rsi, (%rdi)
leaq 40(%rsp), %rsi
movq %rdx, (%rsi)
leaq 20(%rsp), %rdx
movl %ecx, (%rdx)
leaq 16(%rsp), %rcx
movl %r8d, (%rcx)
leaq 12(%rsp), %r8
movl %r9d, (%r8)
leaq 96(%rsp), %rbx
movq %rax, (%rbx)
movq %rdi, 8(%rbx)
movq %rsi, 16(%rbx)
movq %rdx, 24(%rbx)
movq %rcx, 32(%rbx)
movq %r8, 40(%rbx)
leaq 224(%rsp), %rax
movq %rax, 48(%rbx)
leaq 232(%rsp), %rax
movq %rax, 56(%rbx)
leaq 240(%rsp), %rax
movq %rax, 64(%rbx)
leaq 80(%rsp), %r14
leaq 64(%rsp), %r15
leaq 32(%rsp), %r12
leaq 24(%rsp), %r13
movq %r14, %rdi
movq %r15, %rsi
movq %r12, %rdx
movq %r13, %rcx
callq __hipPopCallConfiguration
movq (%r14), %rsi
movl 8(%r14), %edx
movq (%r15), %rcx
movl 8(%r15), %r8d
movl $_Z14matrixMultiplyPfS_S_iiiiii, %edi
movq %rbx, %r9
pushq (%r13)
.cfi_adjust_cfa_offset 8
pushq (%r12)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $192, %rsp
.cfi_adjust_cfa_offset -192
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z29__device_stub__matrixMultiplyPfS_S_iiiiii, .Lfunc_end0-_Z29__device_stub__matrixMultiplyPfS_S_iiiiii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, %rdi
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z14matrixMultiplyPfS_S_iiiiii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z14matrixMultiplyPfS_S_iiiiii,@object # @_Z14matrixMultiplyPfS_S_iiiiii
.section .rodata,"a",@progbits
.globl _Z14matrixMultiplyPfS_S_iiiiii
.p2align 3, 0x0
_Z14matrixMultiplyPfS_S_iiiiii:
.quad _Z29__device_stub__matrixMultiplyPfS_S_iiiiii
.size _Z14matrixMultiplyPfS_S_iiiiii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z14matrixMultiplyPfS_S_iiiiii"
.size .L__unnamed_1, 31
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z29__device_stub__matrixMultiplyPfS_S_iiiiii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z14matrixMultiplyPfS_S_iiiiii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
```
| 2,217 | 2,293 |
72 |
Convert the following CUDA device assembly code to AMD device assembly:
```cudaasm
code for sm_80
Function : _Z18channelFirstKernelPhPfiiii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ;
IABS R7, c[0x0][0x178] ;
S2R R0, SR_TID.X ;
ULDC.64 UR4, c[0x0][0x118] ;
I2F.RP R4, R7 ;
S2R R5, SR_CTAID.X ;
MUFU.RCP R4, R4 ;
IMAD R0, R5, c[0x0][0x0], R0 ;
IABS R8, R0 ;
IADD3 R2, R4, 0xffffffe, RZ ;
F2I.FTZ.U32.TRUNC.NTZ R3, R2 ;
IMAD.MOV.U32 R2, RZ, RZ, RZ ;
IMAD.MOV R6, RZ, RZ, -R3 ;
IMAD R5, R6, R7, RZ ;
IMAD.HI.U32 R3, R3, R5, R2 ;
IMAD.HI.U32 R3, R3, R8, RZ ;
IADD3 R4, -R3, RZ, RZ ;
IMAD R2, R7, R4, R8 ;
ISETP.GT.U32.AND P2, PT, R7, R2, PT ;
@!P2 IMAD.IADD R2, R2, 0x1, -R7 ;
@!P2 IADD3 R3, R3, 0x1, RZ ;
ISETP.NE.AND P2, PT, RZ, c[0x0][0x178], PT ;
ISETP.GE.U32.AND P0, PT, R2, R7, PT ;
LOP3.LUT R2, R0, c[0x0][0x178], RZ, 0x3c, !PT ;
ISETP.GE.AND P1, PT, R2, RZ, PT ;
@P0 IADD3 R3, R3, 0x1, RZ ;
@!P1 IMAD.MOV R3, RZ, RZ, -R3 ;
@!P2 LOP3.LUT R3, RZ, c[0x0][0x178], RZ, 0x33, !PT ;
IADD3 R5, -R3, RZ, RZ ;
IMAD R2, R5, c[0x0][0x178], R0 ;
IMAD R3, R3, c[0x0][0x17c], R2 ;
IADD3 R2, P0, R3, c[0x0][0x160], RZ ;
LEA.HI.X.SX32 R3, R3, c[0x0][0x164], 0x1, P0 ;
LDG.E.U8 R7, [R2.64] ;
IABS R9, c[0x0][0x174] ;
I2F.RP R6, R9 ;
MUFU.RCP R6, R6 ;
IADD3 R4, R6, 0xffffffe, RZ ;
F2I.FTZ.U32.TRUNC.NTZ R5, R4 ;
IMAD.MOV.U32 R4, RZ, RZ, RZ ;
IMAD.MOV R10, RZ, RZ, -R5 ;
IMAD R11, R10, R9, RZ ;
IMAD.HI.U32 R5, R5, R11, R4 ;
HFMA2.MMA R4, -RZ, RZ, 0.00049591064453125, 0.00049591064453125 ;
IMAD.HI.U32 R5, R5, R8, RZ ;
IADD3 R2, -R5, RZ, RZ ;
IMAD R2, R9, R2, R8 ;
ISETP.GT.U32.AND P2, PT, R9, R2, PT ;
@!P2 IMAD.IADD R2, R2, 0x1, -R9 ;
@!P2 IADD3 R5, R5, 0x1, RZ ;
ISETP.NE.AND P2, PT, RZ, c[0x0][0x174], PT ;
ISETP.GE.U32.AND P0, PT, R2, R9, PT ;
LOP3.LUT R2, R0, c[0x0][0x174], RZ, 0x3c, !PT ;
ISETP.GE.AND P1, PT, R2, RZ, PT ;
@P0 IADD3 R5, R5, 0x1, RZ ;
IMAD.MOV.U32 R6, RZ, RZ, R5 ;
IMAD.MOV.U32 R5, RZ, RZ, 0x3f801010 ;
@!P1 IMAD.MOV R6, RZ, RZ, -R6 ;
@!P2 LOP3.LUT R6, RZ, c[0x0][0x174], RZ, 0x33, !PT ;
I2F.U16 R7, R7 ;
F2F.F64.F32 R2, R7 ;
DFMA R2, R2, R4, -1 ;
IADD3 R5, -R6, RZ, RZ ;
IMAD R9, R5, c[0x0][0x174], R0 ;
IMAD.MOV.U32 R5, RZ, RZ, 0x4 ;
F2F.F32.F64 R3, R2 ;
IMAD R4, R9, c[0x0][0x170], R6 ;
IMAD.WIDE R4, R4, R5, c[0x0][0x168] ;
STG.E [R4.64], R3 ;
EXIT ;
BRA 0x460;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
```
|
```amdasm
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z18channelFirstKernelPhPfiiii ; -- Begin function _Z18channelFirstKernelPhPfiiii
.globl _Z18channelFirstKernelPhPfiiii
.p2align 8
.type _Z18channelFirstKernelPhPfiiii,@function
_Z18channelFirstKernelPhPfiiii: ; @_Z18channelFirstKernelPhPfiiii
; %bb.0:
s_clause 0x1
s_load_b256 s[4:11], s[0:1], 0x0
s_load_b32 s0, s[0:1], 0x2c
s_waitcnt lgkmcnt(0)
s_ashr_i32 s2, s10, 31
s_and_b32 s0, s0, 0xffff
s_add_i32 s3, s10, s2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_xor_b32 s3, s3, s2
v_cvt_f32_u32_e32 v1, s3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v1, v1
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v1, 0x4f7ffffe, v1
v_cvt_u32_f32_e32 v3, v1
v_mad_u64_u32 v[1:2], null, s15, s0, v[0:1]
s_sub_i32 s0, 0, s3
s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
v_mul_lo_u32 v0, s0, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v4, 31, v1
v_mul_hi_u32 v0, v3, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v2, v1, v4
v_xor_b32_e32 v5, v2, v4
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v0, v3, v0
v_mul_hi_u32 v0, v5, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v2, v0, s3
v_sub_nc_u32_e32 v2, v5, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v6, s3, v2
v_cmp_le_u32_e32 vcc_lo, s3, v2
v_dual_cndmask_b32 v2, v2, v6 :: v_dual_add_nc_u32 v3, 1, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_cndmask_b32_e32 v0, v0, v3, vcc_lo
v_xor_b32_e32 v6, s2, v4
s_ashr_i32 s2, s9, 31
v_cmp_le_u32_e32 vcc_lo, s3, v2
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v3, 1, v0
s_add_i32 s0, s9, s2
v_xor_b32_e32 v4, s2, v4
s_xor_b32 s3, s0, s2
v_cndmask_b32_e32 v0, v0, v3, vcc_lo
s_sub_i32 s0, 0, s3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_xor_b32_e32 v0, v0, v6
v_sub_nc_u32_e32 v6, v0, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v0, v6, s10
v_sub_nc_u32_e32 v0, v1, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, v6, s11, v[0:1]
v_ashrrev_i32_e32 v0, 31, v2
v_add_co_u32 v2, vcc_lo, s4, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v0, vcc_lo
global_load_u8 v0, v[2:3], off
v_cvt_f32_u32_e32 v2, s3
v_rcp_iflag_f32_e32 v2, v2
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v2, 0x4f7ffffe, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_cvt_u32_f32_e32 v6, v2
s_waitcnt vmcnt(0)
v_cvt_f64_u32_e32 v[2:3], v0
v_mul_lo_u32 v0, s0, v6
s_mov_b32 s0, 0x10101010
s_mov_b32 s1, 0x3f801010
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v0, v6, v0
v_add_nc_u32_e32 v0, v6, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v0, v5, v0
v_mul_lo_u32 v6, v0, s3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_sub_nc_u32_e32 v5, v5, v6
v_fma_f64 v[2:3], v[2:3], s[0:1], -1.0
v_add_nc_u32_e32 v6, 1, v0
v_subrev_nc_u32_e32 v7, s3, v5
v_cmp_le_u32_e32 vcc_lo, s3, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_cndmask_b32 v5, v5, v7 :: v_dual_cndmask_b32 v0, v0, v6
v_cmp_le_u32_e32 vcc_lo, s3, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v6, 1, v0
v_cndmask_b32_e32 v0, v0, v6, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_xor_b32_e32 v0, v0, v4
v_sub_nc_u32_e32 v0, v0, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_lo_u32 v4, v0, s9
v_cvt_f32_f64_e32 v3, v[2:3]
v_sub_nc_u32_e32 v4, v1, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, v4, s8, v[0:1]
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
v_add_co_u32 v0, vcc_lo, s6, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
global_store_b32 v[0:1], v3, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z18channelFirstKernelPhPfiiii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z18channelFirstKernelPhPfiiii, .Lfunc_end0-_Z18channelFirstKernelPhPfiiii
; -- End function
.section .AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 544
; NumSgprs: 18
; NumVgprs: 8
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 8
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object ; @__hip_cuid_
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0 ; 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z18channelFirstKernelPhPfiiii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z18channelFirstKernelPhPfiiii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
```
| 1,515 | 4,398 |
73 |
Convert the following CUDA host assembly code to AMD host assembly:
```cudaasm
.file "tmpxft_00121c33_00000000-6_channel_first.cudafe1.cpp"
.text
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2030:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z44__device_stub__Z18channelFirstKernelPhPfiiiiPhPfiiii
.type _Z44__device_stub__Z18channelFirstKernelPhPfiiiiPhPfiiii, @function
_Z44__device_stub__Z18channelFirstKernelPhPfiiiiPhPfiiii:
.LFB2052:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
movl %r9d, (%rsp)
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 4(%rsp), %rax
movq %rax, 128(%rsp)
movq %rsp, %rax
movq %rax, 136(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 184
pushq 40(%rsp)
.cfi_def_cfa_offset 192
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z18channelFirstKernelPhPfiiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2052:
.size _Z44__device_stub__Z18channelFirstKernelPhPfiiiiPhPfiiii, .-_Z44__device_stub__Z18channelFirstKernelPhPfiiiiPhPfiiii
.globl _Z18channelFirstKernelPhPfiiii
.type _Z18channelFirstKernelPhPfiiii, @function
_Z18channelFirstKernelPhPfiiii:
.LFB2053:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z44__device_stub__Z18channelFirstKernelPhPfiiiiPhPfiiii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2053:
.size _Z18channelFirstKernelPhPfiiii, .-_Z18channelFirstKernelPhPfiiii
.globl _Z12channelFirstPhPfiiii
.type _Z12channelFirstPhPfiiii, @function
_Z12channelFirstPhPfiiii:
.LFB2027:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $40, %rsp
.cfi_def_cfa_offset 96
movq %rdi, %r12
movq %rsi, %r13
movl %edx, %ebx
movl %ecx, %ebp
movl %r8d, %r14d
movl %r9d, %r15d
movl $1024, 20(%rsp)
movl $1, 24(%rsp)
imull %ecx, %edx
leal 2046(%rdx), %eax
addl $1023, %edx
cmovns %edx, %eax
sarl $10, %eax
movl %eax, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L14
.L12:
call cudaDeviceSynchronize@PLT
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
movl %r15d, %r9d
movl %r14d, %r8d
movl %ebp, %ecx
movl %ebx, %edx
movq %r13, %rsi
movq %r12, %rdi
call _Z44__device_stub__Z18channelFirstKernelPhPfiiiiPhPfiiii
jmp .L12
.cfi_endproc
.LFE2027:
.size _Z12channelFirstPhPfiiii, .-_Z12channelFirstPhPfiiii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z18channelFirstKernelPhPfiiii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2055:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z18channelFirstKernelPhPfiiii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2055:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
```
|
```amdasm
.text
.file "channel_first.hip"
.globl _Z33__device_stub__channelFirstKernelPhPfiiii # -- Begin function _Z33__device_stub__channelFirstKernelPhPfiiii
.type _Z33__device_stub__channelFirstKernelPhPfiiii,@function
_Z33__device_stub__channelFirstKernelPhPfiiii: # @_Z33__device_stub__channelFirstKernelPhPfiiii
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $128, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 40(%rsp), %rax
movq %rdi, (%rax)
leaq 32(%rsp), %rdi
movq %rsi, (%rdi)
leaq 12(%rsp), %rsi
movl %edx, (%rsi)
leaq 8(%rsp), %rdx
movl %ecx, (%rdx)
leaq 4(%rsp), %rcx
movl %r8d, (%rcx)
movq %rsp, %r8
movl %r9d, (%r8)
leaq 80(%rsp), %rbx
movq %rax, (%rbx)
movq %rdi, 8(%rbx)
movq %rsi, 16(%rbx)
movq %rdx, 24(%rbx)
movq %rcx, 32(%rbx)
movq %r8, 40(%rbx)
leaq 64(%rsp), %r14
leaq 48(%rsp), %r15
leaq 24(%rsp), %r12
leaq 16(%rsp), %r13
movq %r14, %rdi
movq %r15, %rsi
movq %r12, %rdx
movq %r13, %rcx
callq __hipPopCallConfiguration
movq (%r14), %rsi
movl 8(%r14), %edx
movq (%r15), %rcx
movl 8(%r15), %r8d
movl $_Z18channelFirstKernelPhPfiiii, %edi
movq %rbx, %r9
pushq (%r13)
.cfi_adjust_cfa_offset 8
pushq (%r12)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $144, %rsp
.cfi_adjust_cfa_offset -144
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z33__device_stub__channelFirstKernelPhPfiiii, .Lfunc_end0-_Z33__device_stub__channelFirstKernelPhPfiiii
.cfi_endproc
# -- End function
.globl _Z12channelFirstPhPfiiii # -- Begin function _Z12channelFirstPhPfiiii
.type _Z12channelFirstPhPfiiii,@function
_Z12channelFirstPhPfiiii: # @_Z12channelFirstPhPfiiii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
pushq %rax
.cfi_def_cfa_offset 64
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %r9d, %ebx
movl %r8d, %ebp
movl %ecx, %r14d
movl %edx, %r15d
movq %rsi, %r12
movq %rdi, %r13
movl %ecx, %edi
imull %edx, %edi
leal 1023(%rdi), %eax
addl $2046, %edi # imm = 0x7FE
testl %eax, %eax
cmovnsl %eax, %edi
sarl $10, %edi
btsq $32, %rdi
movabsq $4294967296, %rdx # imm = 0x100000000
orq $1024, %rdx # imm = 0x400
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq %r13, %rdi
movq %r12, %rsi
movl %r15d, %edx
movl %r14d, %ecx
movl %ebp, %r8d
movl %ebx, %r9d
callq _Z33__device_stub__channelFirstKernelPhPfiiii
.LBB1_2:
addq $8, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
jmp hipDeviceSynchronize # TAILCALL
.Lfunc_end1:
.size _Z12channelFirstPhPfiiii, .Lfunc_end1-_Z12channelFirstPhPfiiii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, %rdi
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z18channelFirstKernelPhPfiiii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z18channelFirstKernelPhPfiiii,@object # @_Z18channelFirstKernelPhPfiiii
.section .rodata,"a",@progbits
.globl _Z18channelFirstKernelPhPfiiii
.p2align 3, 0x0
_Z18channelFirstKernelPhPfiiii:
.quad _Z33__device_stub__channelFirstKernelPhPfiiii
.size _Z18channelFirstKernelPhPfiiii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z18channelFirstKernelPhPfiiii"
.size .L__unnamed_1, 31
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z33__device_stub__channelFirstKernelPhPfiiii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z18channelFirstKernelPhPfiiii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
```
| 2,831 | 3,053 |
74 |
Convert the following CUDA device assembly code to AMD device assembly:
```cudaasm
code for sm_80
```
|
```amdasm
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object ; @__hip_cuid_
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0 ; 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
```
| 24 | 306 |
75 |
Convert the following CUDA host assembly code to AMD host assembly:
```cudaasm
.file "tmpxft_000f6830_00000000-6_hello.cudafe1.cpp"
.text
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "%d devices found supporting CUDA\n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "No GPU\n"
.section .rodata.str1.8
.align 8
.LC2:
.string "----------------------------------\n"
.section .rodata.str1.1
.LC3:
.string "Device %s\n"
.LC4:
.string " Device memory: \t%zu\n"
.LC5:
.string " Memory per-block: \t%zu\n"
.LC6:
.string " Register per-block: \t%d\n"
.LC7:
.string " Warp size: \t\t%d\n"
.LC8:
.string " Memory pitch: \t\t%zu\n"
.LC9:
.string " Constant Memory: \t%zu\n"
.LC10:
.string " Max thread per-block: \t%d\n"
.section .rodata.str1.8
.align 8
.LC11:
.string " Max thread dim: \t%d / %d / %d\n"
.align 8
.LC12:
.string " Max grid size: \t%d / %d / %d\n"
.section .rodata.str1.1
.LC13:
.string " Ver: \t\t\t%d.%d\n"
.LC14:
.string " Clock: \t\t%d\n"
.LC15:
.string " Texture Alignment: \t%zu\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $1064, %rsp
.cfi_def_cfa_offset 1120
movq %fs:40, %rax
movq %rax, 1048(%rsp)
xorl %eax, %eax
movl $0, 12(%rsp)
leaq 12(%rsp), %rdi
call cudaGetDeviceCount@PLT
movl 12(%rsp), %edx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 12(%rsp), %eax
testl %eax, %eax
je .L4
movl $0, %ebx
leaq .LC2(%rip), %r12
leaq .LC3(%rip), %r15
leaq .LC4(%rip), %r14
leaq .LC5(%rip), %r13
jle .L6
.L5:
leaq 16(%rsp), %rbp
movl %ebx, %esi
movq %rbp, %rdi
call cudaGetDeviceProperties_v2@PLT
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %rbp, %rdx
movq %r15, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 304(%rsp), %rdx
movq %r14, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 312(%rsp), %rdx
movq %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 320(%rsp), %edx
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 324(%rsp), %edx
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 328(%rsp), %rdx
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 368(%rsp), %rdx
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 336(%rsp), %edx
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 348(%rsp), %r8d
movl 344(%rsp), %ecx
movl 340(%rsp), %edx
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 360(%rsp), %r8d
movl 356(%rsp), %ecx
movl 352(%rsp), %edx
leaq .LC12(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 380(%rsp), %ecx
movl 376(%rsp), %edx
leaq .LC13(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 364(%rsp), %edx
leaq .LC14(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 384(%rsp), %rdx
leaq .LC15(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $1, %ebx
cmpl %ebx, 12(%rsp)
jg .L5
.L6:
movq 1048(%rsp), %rax
subq %fs:40, %rax
jne .L12
movl $0, %eax
addq $1064, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L4:
.cfi_restore_state
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L6
.L12:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
```
|
```amdasm
.text
.file "hello.hip"
.globl main # -- Begin function main
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $1480, %rsp # imm = 0x5C8
.cfi_def_cfa_offset 1504
.cfi_offset %rbx, -24
.cfi_offset %rbp, -16
leaq 4(%rsp), %rbx
movl $0, (%rbx)
movq %rbx, %rdi
callq hipGetDeviceCount
movl (%rbx), %esi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
cmpl $0, (%rbx)
je .LBB0_5
# %bb.1: # %.preheader
jle .LBB0_4
# %bb.2: # %.lr.ph
leaq 8(%rsp), %rbx
xorl %ebp, %ebp
.LBB0_3: # =>This Inner Loop Header: Depth=1
movq %rbx, %rdi
movl %ebp, %esi
callq hipGetDevicePropertiesR0600
movl $.Lstr.1, %edi
callq puts@PLT
movl $.L.str.3, %edi
movq %rbx, %rsi
xorl %eax, %eax
callq printf
movl $.Lstr.1, %edi
callq puts@PLT
movq 296(%rsp), %rsi
movl $.L.str.4, %edi
xorl %eax, %eax
callq printf
movq 304(%rsp), %rsi
movl $.L.str.5, %edi
xorl %eax, %eax
callq printf
movl 312(%rsp), %esi
movl $.L.str.6, %edi
xorl %eax, %eax
callq printf
movl 316(%rsp), %esi
movl $.L.str.7, %edi
xorl %eax, %eax
callq printf
movq 320(%rsp), %rsi
movl $.L.str.8, %edi
xorl %eax, %eax
callq printf
movq 360(%rsp), %rsi
movl $.L.str.9, %edi
xorl %eax, %eax
callq printf
movl 328(%rsp), %esi
movl $.L.str.10, %edi
xorl %eax, %eax
callq printf
movl 332(%rsp), %esi
movl 336(%rsp), %edx
movl 340(%rsp), %ecx
movl $.L.str.11, %edi
xorl %eax, %eax
callq printf
movl 344(%rsp), %esi
movl 348(%rsp), %edx
movl 352(%rsp), %ecx
movl $.L.str.12, %edi
xorl %eax, %eax
callq printf
movl 368(%rsp), %esi
movl 372(%rsp), %edx
movl $.L.str.13, %edi
xorl %eax, %eax
callq printf
movl 356(%rsp), %esi
movl $.L.str.14, %edi
xorl %eax, %eax
callq printf
movq 376(%rsp), %rsi
movl $.L.str.15, %edi
xorl %eax, %eax
callq printf
incl %ebp
cmpl 4(%rsp), %ebp
jl .LBB0_3
jmp .LBB0_4
.LBB0_5:
movl $.Lstr.2, %edi
callq puts@PLT
.LBB0_4: # %.loopexit
xorl %eax, %eax
addq $1480, %rsp # imm = 0x5C8
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%d devices found supporting CUDA\n"
.size .L.str, 34
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Device %s\n"
.size .L.str.3, 11
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz " Device memory: \t%zu\n"
.size .L.str.4, 22
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz " Memory per-block: \t%zu\n"
.size .L.str.5, 25
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz " Register per-block: \t%d\n"
.size .L.str.6, 26
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz " Warp size: \t\t%d\n"
.size .L.str.7, 18
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz " Memory pitch: \t\t%zu\n"
.size .L.str.8, 22
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz " Constant Memory: \t%zu\n"
.size .L.str.9, 24
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz " Max thread per-block: \t%d\n"
.size .L.str.10, 28
.type .L.str.11,@object # @.str.11
.L.str.11:
.asciz " Max thread dim: \t%d / %d / %d\n"
.size .L.str.11, 32
.type .L.str.12,@object # @.str.12
.L.str.12:
.asciz " Max grid size: \t%d / %d / %d\n"
.size .L.str.12, 31
.type .L.str.13,@object # @.str.13
.L.str.13:
.asciz " Ver: \t\t\t%d.%d\n"
.size .L.str.13, 16
.type .L.str.14,@object # @.str.14
.L.str.14:
.asciz " Clock: \t\t%d\n"
.size .L.str.14, 14
.type .L.str.15,@object # @.str.15
.L.str.15:
.asciz " Texture Alignment: \t%zu\n"
.size .L.str.15, 26
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr.1,@object # @str.1
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr.1:
.asciz "----------------------------------"
.size .Lstr.1, 35
.type .Lstr.2,@object # @str.2
.Lstr.2:
.asciz "No GPU"
.size .Lstr.2, 7
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
```
| 2,776 | 2,114 |
78 |
Convert the following CUDA device assembly code to AMD device assembly:
```cudaasm
code for sm_80
Function : _Z6kernelPi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
MOV R1, c[0x0][0x28] ;
S2R R5, SR_CTAID.X ;
HFMA2.MMA R2, -RZ, RZ, 0, 2.384185791015625e-07 ;
ULDC.64 UR4, c[0x0][0x118] ;
S2R R0, SR_TID.X ;
IMAD R5, R5, c[0x0][0x0], R0 ;
IMAD.WIDE R2, R5, R2, c[0x0][0x160] ;
STG.E [R2.64], R5 ;
EXIT ;
BRA 0x90;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
```
|
```amdasm
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6kernelPi ; -- Begin function _Z6kernelPi
.globl _Z6kernelPi
.p2align 8
.type _Z6kernelPi,@function
_Z6kernelPi: ; @_Z6kernelPi
; %bb.0:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x14
s_load_b64 s[0:1], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[1:2]
v_add_co_u32 v2, vcc_lo, s0, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
global_store_b32 v[2:3], v1, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6kernelPi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 264
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6kernelPi, .Lfunc_end0-_Z6kernelPi
; -- End function
.section .AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 96
; NumSgprs: 18
; NumVgprs: 4
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 4
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object ; @__hip_cuid_
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0 ; 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: hidden_block_count_x
- .offset: 12
.size: 4
.value_kind: hidden_block_count_y
- .offset: 16
.size: 4
.value_kind: hidden_block_count_z
- .offset: 20
.size: 2
.value_kind: hidden_group_size_x
- .offset: 22
.size: 2
.value_kind: hidden_group_size_y
- .offset: 24
.size: 2
.value_kind: hidden_group_size_z
- .offset: 26
.size: 2
.value_kind: hidden_remainder_x
- .offset: 28
.size: 2
.value_kind: hidden_remainder_y
- .offset: 30
.size: 2
.value_kind: hidden_remainder_z
- .offset: 48
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 72
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 264
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6kernelPi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z6kernelPi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
```
| 265 | 2,169 |
79 |
Convert the following CUDA host assembly code to AMD host assembly:
```cudaasm
.file "tmpxft_0000f095_00000000-6_cuda_1.cudafe1.cpp"
.text
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "couldn't allocate memory\n"
.LC1:
.string "%d "
.LC2:
.string "\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $24, %rsp
.cfi_def_cfa_offset 64
movq %fs:40, %rax
movq %rax, 8(%rsp)
xorl %eax, %eax
movq $0, (%rsp)
movl $64, %edi
call malloc@PLT
movq %rax, %rbp
movl $64, %edi
call malloc@PLT
movq %rax, %rbx
movq %rsp, %rdi
movl $64, %esi
call cudaMalloc@PLT
testq %rbp, %rbp
je .L4
movq (%rsp), %rdi
movl $0, %eax
testq %rdi, %rdi
je .L4
.L5:
movl %eax, (%rbx,%rax,4)
movl %eax, 0(%rbp,%rax,4)
addq $1, %rax
cmpq $16, %rax
jne .L5
movl $64, %edx
movl $0, %esi
call cudaMemset@PLT
movl $1, %ecx
movl $64, %edx
movq %rbx, %rsi
movq (%rsp), %rdi
call cudaMemcpy@PLT
movl $2, %ecx
movl $64, %edx
movq (%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
movq %rbp, %rbx
leaq 64(%rbp), %r13
leaq .LC1(%rip), %r12
.L7:
movl (%rbx), %edx
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %r13, %rbx
jne .L7
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %rbp, %rdi
call free@PLT
movq (%rsp), %rdi
call cudaFree@PLT
movl $0, %eax
.L3:
movq 8(%rsp), %rdx
subq %fs:40, %rdx
jne .L14
addq $24, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L4:
.cfi_restore_state
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %eax
jmp .L3
.L14:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.globl _Z25__device_stub__Z6kernelPiPi
.type _Z25__device_stub__Z6kernelPiPi, @function
_Z25__device_stub__Z6kernelPiPi:
.LFB2082:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L19
.L15:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L20
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z6kernelPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L15
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z25__device_stub__Z6kernelPiPi, .-_Z25__device_stub__Z6kernelPiPi
.globl _Z6kernelPi
.type _Z6kernelPi, @function
_Z6kernelPi:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z25__device_stub__Z6kernelPiPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z6kernelPi, .-_Z6kernelPi
.section .rodata.str1.1
.LC3:
.string "_Z6kernelPi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z6kernelPi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
```
|
```amdasm
.text
.file "cuda_1.hip"
.globl _Z21__device_stub__kernelPi # -- Begin function _Z21__device_stub__kernelPi
.type _Z21__device_stub__kernelPi,@function
_Z21__device_stub__kernelPi: # @_Z21__device_stub__kernelPi
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $64, %rsp
.cfi_def_cfa_offset 112
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 24(%rsp), %rax
movq %rdi, (%rax)
movq %rsp, %rbx
movq %rax, (%rbx)
leaq 48(%rsp), %r14
leaq 32(%rsp), %r15
leaq 16(%rsp), %r12
leaq 8(%rsp), %r13
movq %r14, %rdi
movq %r15, %rsi
movq %r12, %rdx
movq %r13, %rcx
callq __hipPopCallConfiguration
movq (%r14), %rsi
movl 8(%r14), %edx
movq (%r15), %rcx
movl 8(%r15), %r8d
movl $_Z6kernelPi, %edi
movq %rbx, %r9
pushq (%r13)
.cfi_adjust_cfa_offset 8
pushq (%r12)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $80, %rsp
.cfi_adjust_cfa_offset -80
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z21__device_stub__kernelPi, .Lfunc_end0-_Z21__device_stub__kernelPi
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $16, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 8(%rsp), %r15
movq $0, (%r15)
movl $64, %edi
callq malloc
movq %rax, %rbx
movl $64, %edi
callq malloc
movq %rax, %r14
movl $64, %esi
movq %r15, %rdi
callq hipMalloc
testq %rbx, %rbx
je .LBB1_7
# %bb.1:
movq 8(%rsp), %rdi
testq %rdi, %rdi
je .LBB1_7
# %bb.2: # %.preheader.preheader
xorl %eax, %eax
.LBB1_3: # %.preheader
# =>This Inner Loop Header: Depth=1
movl %eax, (%r14,%rax,4)
movl %eax, (%rbx,%rax,4)
incq %rax
cmpq $16, %rax
jne .LBB1_3
# %bb.4:
movl $64, %edx
xorl %esi, %esi
callq hipMemset
movq 8(%rsp), %rdi
movl $64, %edx
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rsi
movl $64, %edx
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
xorl %r14d, %r14d
.LBB1_5: # =>This Inner Loop Header: Depth=1
movl (%rbx,%r14,4), %esi
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
incq %r14
cmpq $16, %r14
jne .LBB1_5
# %bb.6:
movl $10, %edi
callq putchar@PLT
movq %rbx, %rdi
callq free
movq 8(%rsp), %rdi
callq hipFree
xorl %eax, %eax
jmp .LBB1_8
.LBB1_7:
movl $.Lstr, %edi
callq puts@PLT
movl $1, %eax
.LBB1_8:
addq $16, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, %rdi
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6kernelPi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6kernelPi,@object # @_Z6kernelPi
.section .rodata,"a",@progbits
.globl _Z6kernelPi
.p2align 3, 0x0
_Z6kernelPi:
.quad _Z21__device_stub__kernelPi
.size _Z6kernelPi, 8
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "%d "
.size .L.str.1, 4
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z6kernelPi"
.size .L__unnamed_1, 12
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "couldn't allocate memory"
.size .Lstr, 25
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__kernelPi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6kernelPi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
```
| 2,708 | 2,834 |
80 |
Convert the following CUDA device assembly code to AMD device assembly:
```cudaasm
code for sm_80
Function : _Z24bpnn_adjust_weights_cudaPfiS_iS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
MOV R1, c[0x0][0x28] ;
S2R R11, SR_TID.X ;
ULDC UR4, c[0x0][0x168] ;
HFMA2.MMA R0, -RZ, RZ, 0, 2.384185791015625e-07 ;
UIADD3 UR5, UR4, 0x1, URZ ;
S2R R13, SR_TID.Y ;
ULEA UR4, UR4, 0x10, 0x4 ;
S2R R10, SR_CTAID.Y ;
IADD3 R2, R11, c[0x0][0x168], RZ ;
IMAD R5, R13, UR5, R2 ;
IMAD.WIDE R2, R11, R0, c[0x0][0x160] ;
IMAD R9, R10.reuse, UR4, R5 ;
LEA R7, R10, R13, 0x4 ;
ULDC.64 UR4, c[0x0][0x118] ;
IMAD.WIDE R4, R9, R0.reuse, c[0x0][0x188] ;
LDG.E R12, [R2.64+0x4] ;
IMAD.WIDE R6, R7, R0.reuse, c[0x0][0x170] ;
LDG.E R22, [R4.64+0x8] ;
IMAD.WIDE R8, R9, R0, c[0x0][0x180] ;
LDG.E R16, [R6.64+0x4] ;
LDG.E R23, [R8.64+0x8] ;
F2F.F64.F32 R18, R12 ;
F2F.F64.F32 R14, R22 ;
F2F.F64.F32 R16, R16 ;
DMUL R18, R18, c[0x2][0x0] ;
F2F.F64.F32 R20, R23 ;
DMUL R14, R14, c[0x2][0x0] ;
DFMA R14, R18, R16, R14 ;
DADD R14, R14, R20 ;
F2F.F32.F64 R15, R14 ;
STG.E [R8.64+0x8], R15 ;
LDG.E R24, [R2.64+0x4] ;
LDG.E R12, [R4.64+0x8] ;
LDG.E R18, [R6.64+0x4] ;
LOP3.LUT P0, RZ, R13, R10, RZ, 0xfc, !PT ;
F2F.F64.F32 R16, R24 ;
F2F.F64.F32 R20, R12 ;
F2F.F64.F32 R18, R18 ;
DMUL R16, R16, c[0x2][0x0] ;
DMUL R20, R20, c[0x2][0x0] ;
DFMA R16, R16, R18, R20 ;
F2F.F32.F64 R17, R16 ;
STG.E [R4.64+0x8], R17 ;
BAR.SYNC.DEFER_BLOCKING 0x0 ;
@P0 EXIT ;
IADD3 R11, R11, 0x1, RZ ;
LDG.E R14, [R2.64+0x4] ;
IMAD.WIDE R4, R11, R0, c[0x0][0x188] ;
LDG.E R15, [R4.64] ;
IMAD.WIDE R10, R11, R0, c[0x0][0x180] ;
LDG.E R0, [R10.64] ;
F2F.F64.F32 R6, R14 ;
F2F.F64.F32 R8, R15 ;
F2F.F64.F32 R12, R0 ;
DMUL R8, R8, c[0x2][0x0] ;
DFMA R6, R6, c[0x2][0x0], R8 ;
DADD R6, R6, R12 ;
F2F.F32.F64 R7, R6 ;
STG.E [R10.64], R7 ;
LDG.E R16, [R4.64] ;
LDG.E R2, [R2.64+0x4] ;
F2F.F64.F32 R12, R16 ;
F2F.F64.F32 R8, R2 ;
DMUL R12, R12, c[0x2][0x0] ;
DFMA R8, R8, c[0x2][0x0], R12 ;
F2F.F32.F64 R9, R8 ;
STG.E [R4.64], R9 ;
EXIT ;
BRA 0x440;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
```
|
```amdasm
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z24bpnn_adjust_weights_cudaPfiS_iS_S_ ; -- Begin function _Z24bpnn_adjust_weights_cudaPfiS_iS_S_
.globl _Z24bpnn_adjust_weights_cudaPfiS_iS_S_
.p2align 8
.type _Z24bpnn_adjust_weights_cudaPfiS_iS_S_,@function
_Z24bpnn_adjust_weights_cudaPfiS_iS_S_: ; @_Z24bpnn_adjust_weights_cudaPfiS_iS_S_
; %bb.0:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x8
s_load_b64 s[2:3], s[0:1], 0x10
v_bfe_u32 v15, v0, 10, 10
v_and_b32_e32 v0, 0x3ff, v0
s_mov_b32 s8, exec_lo
s_delay_alu instid0(VALU_DEP_2)
v_lshl_add_u32 v1, s15, 4, v15
s_waitcnt lgkmcnt(0)
s_add_i32 s4, s4, 1
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_mul_lo_u32 v2, v1, s4
v_add_nc_u32_e32 v3, s4, v0
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x20
s_load_b64 s[0:1], s[0:1], 0x0
v_lshlrev_b32_e32 v0, 2, v0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add3_u32 v2, v3, v2, 1
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[2:3]
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v5, vcc_lo, s6, v3
v_add_co_ci_u32_e32 v6, vcc_lo, s7, v4, vcc_lo
global_load_b32 v7, v0, s[0:1] offset:4
global_load_b32 v9, v[5:6], off
v_add_co_u32 v1, vcc_lo, s2, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s3, v2, vcc_lo
v_add_co_u32 v3, vcc_lo, s4, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
global_load_b32 v11, v[1:2], off offset:4
s_mov_b32 s2, 0x33333333
s_mov_b32 s3, 0x3fd33333
global_load_b32 v13, v[3:4], off
s_waitcnt vmcnt(3)
v_cvt_f64_f32_e32 v[7:8], v7
s_waitcnt vmcnt(2)
v_cvt_f64_f32_e32 v[9:10], v9
s_waitcnt vmcnt(1)
v_cvt_f64_f32_e32 v[11:12], v11
s_waitcnt vmcnt(0)
v_cvt_f64_f32_e32 v[13:14], v13
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_mul_f64 v[7:8], v[7:8], s[2:3]
v_mul_f64 v[9:10], v[9:10], s[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[7:8], v[7:8], v[11:12], v[9:10]
v_add_f64 v[7:8], v[7:8], v[13:14]
s_delay_alu instid0(VALU_DEP_1)
v_cvt_f32_f64_e32 v7, v[7:8]
global_store_b32 v[3:4], v7, off
global_load_b32 v3, v0, s[0:1] offset:4
global_load_b32 v4, v[5:6], off
global_load_b32 v7, v[1:2], off offset:4
s_waitcnt vmcnt(2)
v_cvt_f64_f32_e32 v[1:2], v3
s_waitcnt vmcnt(1)
v_cvt_f64_f32_e32 v[3:4], v4
s_waitcnt vmcnt(0)
v_cvt_f64_f32_e32 v[7:8], v7
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_mul_f64 v[1:2], v[1:2], s[2:3]
v_mul_f64 v[3:4], v[3:4], s[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[1:2], v[1:2], v[7:8], v[3:4]
v_cvt_f32_f64_e32 v1, v[1:2]
v_or_b32_e32 v2, s15, v15
global_store_b32 v[5:6], v1, off
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
v_cmpx_eq_u32_e32 0, v2
s_cbranch_execz .LBB0_2
; %bb.1:
global_load_b32 v3, v0, s[6:7] offset:4
v_add_co_u32 v1, s0, s0, v0
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v2, null, s1, 0, s0
global_load_b32 v5, v[1:2], off offset:4
global_load_b32 v7, v0, s[4:5] offset:4
s_waitcnt vmcnt(2)
v_cvt_f64_f32_e32 v[3:4], v3
s_waitcnt vmcnt(1)
v_cvt_f64_f32_e32 v[5:6], v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f64 v[3:4], v[3:4], s[2:3]
v_fma_f64 v[3:4], v[5:6], s[2:3], v[3:4]
s_waitcnt vmcnt(0)
v_cvt_f64_f32_e32 v[5:6], v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[3:4], v[3:4], v[5:6]
v_cvt_f32_f64_e32 v3, v[3:4]
global_store_b32 v0, v3, s[4:5] offset:4
global_load_b32 v3, v0, s[6:7] offset:4
global_load_b32 v4, v[1:2], off offset:4
s_waitcnt vmcnt(1)
v_cvt_f64_f32_e32 v[1:2], v3
s_waitcnt vmcnt(0)
v_cvt_f64_f32_e32 v[3:4], v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f64 v[1:2], v[1:2], s[2:3]
v_fma_f64 v[1:2], v[3:4], s[2:3], v[1:2]
s_delay_alu instid0(VALU_DEP_1)
v_cvt_f32_f64_e32 v1, v[1:2]
global_store_b32 v0, v1, s[6:7] offset:4
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z24bpnn_adjust_weights_cudaPfiS_iS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 48
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 16
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z24bpnn_adjust_weights_cudaPfiS_iS_S_, .Lfunc_end0-_Z24bpnn_adjust_weights_cudaPfiS_iS_S_
; -- End function
.section .AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 632
; NumSgprs: 18
; NumVgprs: 16
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 16
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object ; @__hip_cuid_
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0 ; 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 40
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 48
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z24bpnn_adjust_weights_cudaPfiS_iS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z24bpnn_adjust_weights_cudaPfiS_iS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 16
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
```
| 1,352 | 3,916 |
81 |
Convert the following CUDA host assembly code to AMD host assembly:
```cudaasm
.file "tmpxft_0011f10c_00000000-6_bpnn_adjust_weights_cuda.cudafe1.cpp"
.text
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z52__device_stub__Z24bpnn_adjust_weights_cudaPfiS_iS_S_PfiS_iS_S_
.type _Z52__device_stub__Z24bpnn_adjust_weights_cudaPfiS_iS_S_PfiS_iS_S_, @function
_Z52__device_stub__Z24bpnn_adjust_weights_cudaPfiS_iS_S_PfiS_iS_S_:
.LFB2051:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movl %esi, 36(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 32(%rsp)
movq %r8, 16(%rsp)
movq %r9, 8(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 36(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 32(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 8(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z24bpnn_adjust_weights_cudaPfiS_iS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z52__device_stub__Z24bpnn_adjust_weights_cudaPfiS_iS_S_PfiS_iS_S_, .-_Z52__device_stub__Z24bpnn_adjust_weights_cudaPfiS_iS_S_PfiS_iS_S_
.globl _Z24bpnn_adjust_weights_cudaPfiS_iS_S_
.type _Z24bpnn_adjust_weights_cudaPfiS_iS_S_, @function
_Z24bpnn_adjust_weights_cudaPfiS_iS_S_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z52__device_stub__Z24bpnn_adjust_weights_cudaPfiS_iS_S_PfiS_iS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z24bpnn_adjust_weights_cudaPfiS_iS_S_, .-_Z24bpnn_adjust_weights_cudaPfiS_iS_S_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z24bpnn_adjust_weights_cudaPfiS_iS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z24bpnn_adjust_weights_cudaPfiS_iS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
```
|
```amdasm
.text
.file "bpnn_adjust_weights_cuda.hip"
.globl _Z39__device_stub__bpnn_adjust_weights_cudaPfiS_iS_S_ # -- Begin function _Z39__device_stub__bpnn_adjust_weights_cudaPfiS_iS_S_
.type _Z39__device_stub__bpnn_adjust_weights_cudaPfiS_iS_S_,@function
_Z39__device_stub__bpnn_adjust_weights_cudaPfiS_iS_S_: # @_Z39__device_stub__bpnn_adjust_weights_cudaPfiS_iS_S_
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $144, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 56(%rsp), %rax
movq %rdi, (%rax)
leaq 12(%rsp), %rdi
movl %esi, (%rdi)
leaq 48(%rsp), %rsi
movq %rdx, (%rsi)
leaq 8(%rsp), %rdx
movl %ecx, (%rdx)
leaq 40(%rsp), %rcx
movq %r8, (%rcx)
leaq 32(%rsp), %r8
movq %r9, (%r8)
leaq 96(%rsp), %rbx
movq %rax, (%rbx)
movq %rdi, 8(%rbx)
movq %rsi, 16(%rbx)
movq %rdx, 24(%rbx)
movq %rcx, 32(%rbx)
movq %r8, 40(%rbx)
leaq 80(%rsp), %r14
leaq 64(%rsp), %r15
leaq 24(%rsp), %r12
leaq 16(%rsp), %r13
movq %r14, %rdi
movq %r15, %rsi
movq %r12, %rdx
movq %r13, %rcx
callq __hipPopCallConfiguration
movq (%r14), %rsi
movl 8(%r14), %edx
movq (%r15), %rcx
movl 8(%r15), %r8d
movl $_Z24bpnn_adjust_weights_cudaPfiS_iS_S_, %edi
movq %rbx, %r9
pushq (%r13)
.cfi_adjust_cfa_offset 8
pushq (%r12)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $160, %rsp
.cfi_adjust_cfa_offset -160
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z39__device_stub__bpnn_adjust_weights_cudaPfiS_iS_S_, .Lfunc_end0-_Z39__device_stub__bpnn_adjust_weights_cudaPfiS_iS_S_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, %rdi
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z24bpnn_adjust_weights_cudaPfiS_iS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z24bpnn_adjust_weights_cudaPfiS_iS_S_,@object # @_Z24bpnn_adjust_weights_cudaPfiS_iS_S_
.section .rodata,"a",@progbits
.globl _Z24bpnn_adjust_weights_cudaPfiS_iS_S_
.p2align 3, 0x0
_Z24bpnn_adjust_weights_cudaPfiS_iS_S_:
.quad _Z39__device_stub__bpnn_adjust_weights_cudaPfiS_iS_S_
.size _Z24bpnn_adjust_weights_cudaPfiS_iS_S_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z24bpnn_adjust_weights_cudaPfiS_iS_S_"
.size .L__unnamed_1, 39
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z39__device_stub__bpnn_adjust_weights_cudaPfiS_iS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z24bpnn_adjust_weights_cudaPfiS_iS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
```
| 2,058 | 2,237 |
84 |
Convert the following CUDA device assembly code to AMD device assembly:
```cudaasm
code for sm_80
Function : _Z3addiiPi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ;
IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x164] ;
MOV R2, c[0x0][0x168] ;
ULDC.64 UR4, c[0x0][0x118] ;
MOV R3, c[0x0][0x16c] ;
IADD3 R5, R5, c[0x0][0x160], RZ ;
STG.E [R2.64], R5 ;
EXIT ;
BRA 0x80;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
```
|
```amdasm
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3addiiPi ; -- Begin function _Z3addiiPi
.globl _Z3addiiPi
.p2align 8
.type _Z3addiiPi,@function
_Z3addiiPi: ; @_Z3addiiPi
; %bb.0:
s_load_b128 s[0:3], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_add_i32 s0, s1, s0
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s0
global_store_b32 v0, v1, s[2:3]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3addiiPi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 16
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 4
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3addiiPi, .Lfunc_end0-_Z3addiiPi
; -- End function
.section .AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 48
; NumSgprs: 4
; NumVgprs: 2
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 0
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 4
; NumVGPRsForWavesPerEU: 2
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object ; @__hip_cuid_
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0 ; 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 16
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3addiiPi
.private_segment_fixed_size: 0
.sgpr_count: 4
.sgpr_spill_count: 0
.symbol: _Z3addiiPi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
```
| 256 | 1,675 |
85 |
Convert the following CUDA host assembly code to AMD host assembly:
```cudaasm
.file "tmpxft_0010c552_00000000-6_add.cudafe1.cpp"
.text
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z24__device_stub__Z3addiiPiiiPi
.type _Z24__device_stub__Z3addiiPiiiPi, @function
_Z24__device_stub__Z3addiiPiiiPi:
.LFB2082:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 12(%rsp)
movl %esi, 8(%rsp)
movq %rdx, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 8(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rax
movq %rax, 96(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z3addiiPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z24__device_stub__Z3addiiPiiiPi, .-_Z24__device_stub__Z3addiiPiiiPi
.globl _Z3addiiPi
.type _Z3addiiPi, @function
_Z3addiiPi:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z24__device_stub__Z3addiiPiiiPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z3addiiPi, .-_Z3addiiPi
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "Memory could not be allocated on device\n"
.align 8
.LC1:
.string "Could not copy from device to host\n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "%d = 2 + 7\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
subq $56, %rsp
.cfi_def_cfa_offset 64
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
testl %eax, %eax
jne .L17
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L18
.L13:
leaq 28(%rsp), %rdi
movl $2, %ecx
movl $4, %edx
movq 8(%rsp), %rsi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L19
movl 28(%rsp), %edx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L20
movl $0, %eax
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L17:
.cfi_restore_state
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L18:
movq 8(%rsp), %rdx
movl $7, %esi
movl $2, %edi
call _Z24__device_stub__Z3addiiPiiiPi
jmp .L13
.L19:
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC3:
.string "_Z3addiiPi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z3addiiPi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
```
|
```amdasm
.text
.file "add.hip"
.globl _Z18__device_stub__addiiPi # -- Begin function _Z18__device_stub__addiiPi
.type _Z18__device_stub__addiiPi,@function
_Z18__device_stub__addiiPi: # @_Z18__device_stub__addiiPi
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $96, %rsp
.cfi_def_cfa_offset 144
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 4(%rsp), %rax
movl %edi, (%rax)
movq %rsp, %rcx
movl %esi, (%rcx)
leaq 24(%rsp), %rsi
movq %rdx, (%rsi)
leaq 64(%rsp), %rbx
movq %rax, (%rbx)
movq %rcx, 8(%rbx)
movq %rsi, 16(%rbx)
leaq 48(%rsp), %r14
leaq 32(%rsp), %r15
leaq 16(%rsp), %r12
leaq 8(%rsp), %r13
movq %r14, %rdi
movq %r15, %rsi
movq %r12, %rdx
movq %r13, %rcx
callq __hipPopCallConfiguration
movq (%r14), %rsi
movl 8(%r14), %edx
movq (%r15), %rcx
movl 8(%r15), %r8d
movl $_Z3addiiPi, %edi
movq %rbx, %r9
pushq (%r13)
.cfi_adjust_cfa_offset 8
pushq (%r12)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $112, %rsp
.cfi_adjust_cfa_offset -112
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z18__device_stub__addiiPi, .Lfunc_end0-_Z18__device_stub__addiiPi
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $24, %rsp
.cfi_def_cfa_offset 32
leaq 8(%rsp), %rdi
movl $4, %esi
callq hipMalloc
testl %eax, %eax
jne .LBB1_1
# %bb.3:
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_5
# %bb.4:
movq 8(%rsp), %rdx
movl $2, %edi
movl $7, %esi
callq _Z18__device_stub__addiiPi
.LBB1_5:
movq 8(%rsp), %rsi
leaq 20(%rsp), %rdi
movl $4, %edx
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB1_6
# %bb.7:
movl 20(%rsp), %esi
movl $.L.str.2, %edi
xorl %eax, %eax
callq printf
movq 8(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $24, %rsp
.cfi_def_cfa_offset 8
retq
.LBB1_1:
.cfi_def_cfa_offset 32
movl $.Lstr.1, %edi
jmp .LBB1_2
.LBB1_6:
movl $.Lstr, %edi
.LBB1_2:
callq puts@PLT
movl $1, %edi
callq exit
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, %rdi
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3addiiPi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3addiiPi,@object # @_Z3addiiPi
.section .rodata,"a",@progbits
.globl _Z3addiiPi
.p2align 3, 0x0
_Z3addiiPi:
.quad _Z18__device_stub__addiiPi
.size _Z3addiiPi, 8
.type .L.str.2,@object # @.str.2
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.2:
.asciz "%d = 2 + 7\n"
.size .L.str.2, 12
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z3addiiPi"
.size .L__unnamed_1, 11
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Could not copy from device to host"
.size .Lstr, 35
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "Memory could not be allocated on device"
.size .Lstr.1, 40
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__addiiPi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3addiiPi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
```
| 2,570 | 2,661 |
86 |
Convert the following CUDA device assembly code to AMD device assembly:
```cudaasm
code for sm_80
Function : _Z19calcDenseForwardGPUPfS_S_S_iiiiiii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ;
S2R R0, SR_CTAID.Y ;
ULDC UR6, c[0x0][0x180] ;
ULDC.64 UR4, c[0x0][0x190] ;
S2R R3, SR_CTAID.X ;
UIMAD UR4, UR4, UR6, URZ ;
S2R R5, SR_TID.X ;
UIMAD UR4, UR4, UR5, URZ ;
ULDC UR5, c[0x0][0x198] ;
UIMAD UR4, UR4, UR5, URZ ;
IMAD R0, R0, c[0x0][0xc], R3 ;
IMAD R0, R0, c[0x0][0x0], R5 ;
ISETP.GE.AND P0, PT, R0, UR4, PT ;
@P0 EXIT ;
IABS R9, c[0x0][0x190] ;
ULDC.64 UR8, c[0x0][0x118] ;
ISETP.GE.AND P2, PT, R0, RZ, PT ;
IMAD.MOV.U32 R20, RZ, RZ, RZ ;
I2F.RP R4, R9 ;
LOP3.LUT R7, RZ, c[0x0][0x190], RZ, 0x33, !PT ;
MUFU.RCP R4, R4 ;
IADD3 R2, R4, 0xffffffe, RZ ;
F2I.FTZ.U32.TRUNC.NTZ R3, R2 ;
HFMA2.MMA R2, -RZ, RZ, 0, 0 ;
IMAD.MOV R6, RZ, RZ, -R3 ;
IMAD R5, R6, R9, RZ ;
IABS R6, R0 ;
IMAD.HI.U32 R3, R3, R5, R2 ;
IMAD.HI.U32 R3, R3, R6, RZ ;
IMAD.MOV R4, RZ, RZ, -R3 ;
IMAD R4, R9, R4, R6 ;
MOV R6, 0x1 ;
ISETP.GT.U32.AND P1, PT, R9, R4, PT ;
ISETP.LE.AND P0, PT, R6, c[0x0][0x188], PT ;
ISETP.GT.OR P0, PT, R6, c[0x0][0x18c], !P0 ;
@!P1 IMAD.IADD R4, R4, 0x1, -R9 ;
IMAD.IADD R5, R4, 0x1, -R9 ;
ISETP.GT.U32.AND P3, PT, R9, R4, PT ;
SEL R2, R5, R4, !P3 ;
ISETP.NE.AND P3, PT, RZ, c[0x0][0x190], PT ;
@!P2 IADD3 R2, -R2, RZ, RZ ;
SEL R2, R7, R2, !P3 ;
@P0 BRA 0x1230 ;
IABS R10, c[0x0][0x194] ;
ULDC UR5, c[0x0][0x184] ;
ISETP.GE.U32.AND P0, PT, R4, R9, PT ;
ULDC.64 UR6, c[0x0][0x188] ;
I2F.RP R6, R10 ;
LOP3.LUT R4, R0, c[0x0][0x190], RZ, 0x3c, !PT ;
UIMAD UR5, UR6, UR5, URZ ;
@!P1 IADD3 R3, R3, 0x1, RZ ;
ISETP.GE.AND P2, PT, R4, RZ, PT ;
UIMAD UR4, UR5, UR7, URZ ;
MOV R4, RZ ;
MOV R20, RZ ;
@P0 IADD3 R3, R3, 0x1, RZ ;
MUFU.RCP R6, R6 ;
@!P2 IMAD.MOV R3, RZ, RZ, -R3 ;
SEL R7, R7, R3, !P3 ;
IABS R3, c[0x0][0x198] ;
IADD3 R5, R6, 0xffffffe, RZ ;
IABS R6, R7 ;
LOP3.LUT R7, R7, c[0x0][0x194], RZ, 0x3c, !PT ;
F2I.FTZ.U32.TRUNC.NTZ R5, R5 ;
ISETP.GE.AND P2, PT, R7, RZ, PT ;
IADD3 R9, RZ, -R5, RZ ;
IMAD R9, R9, R10, RZ ;
IMAD.HI.U32 R4, R5, R9, R4 ;
IMAD.MOV.U32 R5, RZ, RZ, R6 ;
I2F.RP R6, R3 ;
IMAD.HI.U32 R4, R4, R5, RZ ;
IADD3 R8, -R4, RZ, RZ ;
IMAD R5, R10.reuse, R8, R5 ;
MUFU.RCP R6, R6 ;
ISETP.GT.U32.AND P1, PT, R10, R5, PT ;
@!P1 IMAD.IADD R5, R5, 0x1, -R10 ;
@!P1 IADD3 R4, R4, 0x1, RZ ;
IADD3 R8, R6, 0xffffffe, RZ ;
ISETP.GE.U32.AND P0, PT, R5, R10, PT ;
F2I.FTZ.U32.TRUNC.NTZ R5, R8 ;
ISETP.NE.AND P1, PT, RZ, c[0x0][0x194], PT ;
@P0 IADD3 R4, R4, 0x1, RZ ;
MOV R6, R4 ;
IMAD.MOV R4, RZ, RZ, -R5 ;
@!P2 IADD3 R6, -R6, RZ, RZ ;
IMAD R7, R4, R3, RZ ;
@!P1 LOP3.LUT R6, RZ, c[0x0][0x194], RZ, 0x33, !PT ;
IMAD.MOV.U32 R4, RZ, RZ, RZ ;
ISETP.NE.AND P2, PT, RZ, c[0x0][0x198], PT ;
IABS R8, R6 ;
IMAD.HI.U32 R4, R5, R7, R4 ;
LOP3.LUT R6, R6, c[0x0][0x198], RZ, 0x3c, !PT ;
ISETP.GE.AND P3, PT, R6, RZ, PT ;
IMAD.HI.U32 R4, R4, R8, RZ ;
IADD3 R5, -R4, RZ, RZ ;
IMAD R8, R3, R5, R8 ;
MOV R5, 0x1 ;
ISETP.GT.U32.AND P1, PT, R3, R8, PT ;
@!P1 IMAD.IADD R8, R8, 0x1, -R3 ;
@!P1 IADD3 R4, R4, 0x1, RZ ;
ISETP.GE.U32.AND P0, PT, R8, R3, PT ;
IMAD R8, R2, UR4, RZ ;
@P0 IADD3 R4, R4, 0x1, RZ ;
IMAD.MOV.U32 R3, RZ, RZ, R4 ;
IADD3 R4, -R5, c[0x0][0x184], RZ ;
MOV R5, c[0x0][0x184] ;
@!P3 IMAD.MOV R3, RZ, RZ, -R3 ;
ISETP.GE.U32.AND P1, PT, R4, 0x3, PT ;
@!P2 LOP3.LUT R3, RZ, c[0x0][0x198], RZ, 0x33, !PT ;
LOP3.LUT R4, R5, 0x3, RZ, 0xc0, !PT ;
IMAD.MOV.U32 R5, RZ, RZ, RZ ;
IMAD R10, R3, UR4, RZ ;
IADD3 R6, -R4, c[0x0][0x184], RZ ;
MOV R7, c[0x0][0x184] ;
ISETP.GE.AND P0, PT, R7, 0x1, PT ;
@!P0 BRA 0x1200 ;
IMAD R7, R3, c[0x0][0x18c], R5.reuse ;
IMAD R9, R2, c[0x0][0x18c], R5 ;
IMAD R11, R5.reuse, UR5, R10 ;
IMAD R12, R5, UR5, R8 ;
IMAD.MOV.U32 R18, RZ, RZ, RZ ;
UMOV UR4, URZ ;
@!P1 BRA 0x1080 ;
ISETP.GT.AND P0, PT, R6, RZ, PT ;
HFMA2.MMA R15, -RZ, RZ, 0, 2.384185791015625e-07 ;
IMAD R13, R9, c[0x0][0x188], R18.reuse ;
UMOV UR4, URZ ;
IMAD R19, R7, c[0x0][0x188], R18 ;
ULDC.64 UR6, c[0x0][0x160] ;
IMAD R14, R13, c[0x0][0x184], RZ ;
IMAD.MOV.U32 R13, RZ, RZ, R6 ;
IMAD R19, R19, c[0x0][0x184], RZ ;
IMAD.WIDE R14, R14, R15, c[0x0][0x170] ;
@!P0 BRA 0xef0 ;
ISETP.GT.AND P2, PT, R13, 0xc, PT ;
PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ;
@!P2 BRA 0xc70 ;
PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ;
MOV R16, UR6 ;
IMAD.U32 R17, RZ, RZ, UR7 ;
LDG.E R23, [R14.64] ;
IMAD.WIDE R16, R19, 0x4, R16 ;
LDG.E R26, [R14.64+0x4] ;
LDG.E R24, [R16.64] ;
LDG.E R25, [R16.64+0x4] ;
LDG.E R21, [R14.64+0x8] ;
LDG.E R22, [R16.64+0x8] ;
LDG.E R27, [R16.64+0x3c] ;
FFMA R23, R23, R24, R20 ;
LDG.E R24, [R14.64+0xc] ;
FFMA R25, R26, R25, R23 ;
LDG.E R26, [R16.64+0xc] ;
LDG.E R20, [R14.64+0x10] ;
LDG.E R23, [R16.64+0x10] ;
FFMA R25, R21, R22, R25 ;
LDG.E R21, [R14.64+0x14] ;
LDG.E R22, [R16.64+0x14] ;
FFMA R24, R24, R26, R25 ;
LDG.E R25, [R14.64+0x18] ;
LDG.E R26, [R16.64+0x18] ;
FFMA R24, R20, R23, R24 ;
LDG.E R20, [R14.64+0x1c] ;
LDG.E R23, [R16.64+0x1c] ;
FFMA R24, R21, R22, R24 ;
LDG.E R21, [R14.64+0x20] ;
LDG.E R22, [R16.64+0x20] ;
FFMA R24, R25, R26, R24 ;
LDG.E R25, [R14.64+0x24] ;
LDG.E R26, [R16.64+0x24] ;
FFMA R20, R20, R23, R24 ;
LDG.E R23, [R14.64+0x28] ;
LDG.E R24, [R16.64+0x28] ;
FFMA R22, R21, R22, R20 ;
LDG.E R20, [R14.64+0x2c] ;
LDG.E R21, [R16.64+0x2c] ;
FFMA R22, R25, R26, R22 ;
LDG.E R25, [R16.64+0x34] ;
FFMA R26, R23, R24, R22 ;
LDG.E R22, [R14.64+0x30] ;
LDG.E R23, [R16.64+0x30] ;
LDG.E R24, [R14.64+0x34] ;
FFMA R28, R20, R21, R26 ;
LDG.E R20, [R14.64+0x38] ;
LDG.E R21, [R16.64+0x38] ;
LDG.E R26, [R14.64+0x3c] ;
IADD3 R13, R13, -0x10, RZ ;
ISETP.GT.AND P2, PT, R13, 0xc, PT ;
UIADD3 UR6, UP0, UR6, 0x40, URZ ;
UIADD3 UR4, UR4, 0x10, URZ ;
UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ;
FFMA R22, R22, R23, R28 ;
IADD3 R23, P3, R14, 0x40, RZ ;
FFMA R22, R24, R25, R22 ;
IADD3.X R16, RZ, R15, RZ, P3, !PT ;
IMAD.MOV.U32 R14, RZ, RZ, R23 ;
FFMA R20, R20, R21, R22 ;
MOV R15, R16 ;
FFMA R20, R26, R27, R20 ;
@P2 BRA 0x8a0 ;
ISETP.GT.AND P2, PT, R13, 0x4, PT ;
@!P2 BRA 0xed0 ;
MOV R17, UR7 ;
IMAD.U32 R16, RZ, RZ, UR6 ;
LDG.E R21, [R14.64] ;
IMAD.WIDE R16, R19, 0x4, R16 ;
LDG.E R23, [R14.64+0x4] ;
LDG.E R22, [R16.64] ;
LDG.E R24, [R16.64+0x4] ;
LDG.E R25, [R14.64+0x8] ;
LDG.E R26, [R16.64+0x8] ;
LDG.E R27, [R14.64+0x14] ;
LDG.E R28, [R16.64+0x14] ;
FFMA R22, R21, R22, R20 ;
LDG.E R21, [R14.64+0xc] ;
LDG.E R20, [R16.64+0xc] ;
FFMA R22, R23, R24, R22 ;
LDG.E R23, [R14.64+0x10] ;
FFMA R25, R25, R26, R22 ;
LDG.E R22, [R16.64+0x10] ;
LDG.E R24, [R14.64+0x1c] ;
FFMA R26, R21, R20, R25 ;
LDG.E R20, [R14.64+0x18] ;
LDG.E R21, [R16.64+0x18] ;
LDG.E R25, [R16.64+0x1c] ;
FFMA R22, R23, R22, R26 ;
FFMA R22, R27, R28, R22 ;
UIADD3 UR6, UP0, UR6, 0x20, URZ ;
PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ;
IADD3 R13, R13, -0x8, RZ ;
UIADD3 UR4, UR4, 0x8, URZ ;
UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ;
FFMA R20, R20, R21, R22 ;
IADD3 R21, P2, R14, 0x20, RZ ;
IMAD.X R22, RZ, RZ, R15, P2 ;
MOV R14, R21 ;
FFMA R20, R24, R25, R20 ;
IMAD.MOV.U32 R15, RZ, RZ, R22 ;
ISETP.NE.OR P0, PT, R13, RZ, P0 ;
@!P0 BRA 0x1080 ;
MOV R16, UR6 ;
IMAD.U32 R17, RZ, RZ, UR7 ;
LDG.E R25, [R14.64] ;
IMAD.WIDE R16, R19, 0x4, R16 ;
LDG.E R27, [R14.64+0x4] ;
LDG.E R24, [R16.64] ;
LDG.E R26, [R16.64+0x4] ;
LDG.E R21, [R16.64+0x8] ;
LDG.E R28, [R14.64+0x8] ;
LDG.E R23, [R16.64+0xc] ;
LDG.E R22, [R14.64+0xc] ;
IADD3 R13, R13, -0x4, RZ ;
ISETP.NE.AND P0, PT, R13, RZ, PT ;
UIADD3 UR6, UP0, UR6, 0x10, URZ ;
UIADD3 UR4, UR4, 0x4, URZ ;
UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ;
FFMA R24, R25, R24, R20 ;
IADD3 R25, P2, R14, 0x10, RZ ;
FFMA R24, R27, R26, R24 ;
IADD3.X R16, RZ, R15, RZ, P2, !PT ;
IMAD.MOV.U32 R14, RZ, RZ, R25 ;
FFMA R21, R28, R21, R24 ;
MOV R15, R16 ;
FFMA R20, R22, R23, R21 ;
@P0 BRA 0xef0 ;
ISETP.NE.AND P0, PT, R4, RZ, PT ;
@!P0 BRA 0x11d0 ;
IMAD R13, R18.reuse, c[0x0][0x184], R11 ;
IMAD R14, R18, c[0x0][0x184], R12 ;
IMAD.MOV.U32 R15, RZ, RZ, 0x4 ;
IADD3 R13, R13, UR4, RZ ;
IADD3 R14, R14, UR4, RZ ;
IMAD.WIDE R16, R13, R15, c[0x0][0x160] ;
IMAD.WIDE R14, R14, R15, c[0x0][0x170] ;
LDG.E R19, [R16.64] ;
LDG.E R13, [R14.64] ;
ISETP.NE.AND P0, PT, R4, 0x1, PT ;
FFMA R20, R13, R19, R20 ;
@!P0 BRA 0x11d0 ;
ISETP.NE.AND P0, PT, R4, 0x2, PT ;
LDG.E R13, [R14.64+0x4] ;
LDG.E R19, [R16.64+0x4] ;
@P0 LDG.E R21, [R14.64+0x8] ;
@P0 LDG.E R22, [R16.64+0x8] ;
FFMA R20, R13, R19, R20 ;
@P0 FFMA R20, R21, R22, R20 ;
IADD3 R18, R18, 0x1, RZ ;
ISETP.GE.AND P0, PT, R18, c[0x0][0x188], PT ;
@!P0 BRA 0x790 ;
IADD3 R5, R5, 0x1, RZ ;
ISETP.GE.AND P0, PT, R5, c[0x0][0x18c], PT ;
@!P0 BRA 0x710 ;
MOV R5, 0x4 ;
IMAD.WIDE R2, R2, R5, c[0x0][0x178] ;
LDG.E R3, [R2.64] ;
IMAD.WIDE R4, R0, R5, c[0x0][0x168] ;
FADD R7, R3, R20 ;
STG.E [R4.64], R7 ;
EXIT ;
BRA 0x12a0;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
```
|
```amdasm
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z19calcDenseForwardGPUPfS_S_S_iiiiiii ; -- Begin function _Z19calcDenseForwardGPUPfS_S_S_iiiiiii
.globl _Z19calcDenseForwardGPUPfS_S_S_iiiiiii
.p2align 8
.type _Z19calcDenseForwardGPUPfS_S_S_iiiiiii,@function
_Z19calcDenseForwardGPUPfS_S_S_iiiiiii: ; @_Z19calcDenseForwardGPUPfS_S_S_iiiiiii
; %bb.0:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x40
s_load_b32 s3, s[0:1], 0x4c
s_load_b256 s[4:11], s[0:1], 0x20
s_waitcnt lgkmcnt(0)
s_mul_i32 s2, s2, s15
s_and_b32 s3, s3, 0xffff
s_add_i32 s2, s2, s14
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[1:2], null, s2, s3, v[0:1]
s_mul_i32 s2, s8, s4
s_mul_i32 s2, s2, s9
s_delay_alu instid0(SALU_CYCLE_1)
s_mul_i32 s2, s2, s10
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_cmp_gt_i32_e32 vcc_lo, s2, v1
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_12
; %bb.1:
s_ashr_i32 s2, s8, 31
v_ashrrev_i32_e32 v2, 31, v1
s_add_i32 s3, s8, s2
s_load_b256 s[12:19], s[0:1], 0x0
s_xor_b32 s3, s3, s2
s_mov_b32 s0, 0
v_cvt_f32_u32_e32 v0, s3
s_sub_i32 s4, 0, s3
v_add_nc_u32_e32 v4, v1, v2
s_cmp_lt_i32 s7, 1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v0, v0
v_xor_b32_e32 v4, v4, v2
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v0, 0x4f7ffffe, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_u32_f32_e32 v0, v0
v_mul_lo_u32 v3, s4, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v3, v0, v3
v_add_nc_u32_e32 v0, v0, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v0, v4, v0
v_mul_lo_u32 v3, v0, s3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v3, v4, v3
v_add_nc_u32_e32 v4, 1, v0
v_subrev_nc_u32_e32 v5, s3, v3
v_cmp_le_u32_e32 vcc_lo, s3, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_dual_cndmask_b32 v3, v3, v5 :: v_dual_cndmask_b32 v0, v0, v4
v_xor_b32_e32 v5, s2, v2
v_cmp_le_u32_e32 vcc_lo, s3, v3
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v4, 1, v0
v_cndmask_b32_e32 v0, v0, v4, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_xor_b32_e32 v0, v0, v5
v_sub_nc_u32_e32 v0, v0, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v3, v0, s8
v_sub_nc_u32_e32 v3, v1, v3
s_cbranch_scc1 .LBB0_10
; %bb.2: ; %.preheader65.lr.ph
s_ashr_i32 s1, s9, 31
v_ashrrev_i32_e32 v6, 31, v0
s_add_i32 s2, s9, s1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_xor_b32 s2, s2, s1
v_add_nc_u32_e32 v0, v0, v6
v_cvt_f32_u32_e32 v4, s2
s_sub_i32 s3, 0, s2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_xor_b32_e32 v0, v0, v6
v_rcp_iflag_f32_e32 v4, v4
v_xor_b32_e32 v6, s1, v6
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v4, 0x4f7ffffe, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_u32_f32_e32 v4, v4
v_mul_lo_u32 v5, s3, v4
s_ashr_i32 s3, s10, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s4, s10, s3
s_xor_b32 s4, s4, s3
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cvt_f32_u32_e32 v7, s4
v_mul_hi_u32 v5, v4, v5
s_sub_i32 s1, 0, s4
s_cmp_gt_i32 s6, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v7, v7
v_add_nc_u32_e32 v4, v4, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_mul_hi_u32 v4, v0, v4
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v7, 0x4f7ffffe, v7
v_mul_lo_u32 v5, v4, s2
v_sub_nc_u32_e32 v0, v0, v5
v_add_nc_u32_e32 v5, 1, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_subrev_nc_u32_e32 v8, s2, v0
v_cmp_le_u32_e32 vcc_lo, s2, v0
v_cndmask_b32_e32 v4, v4, v5, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v0, v0, v8, vcc_lo
v_add_nc_u32_e32 v5, 1, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_cmp_le_u32_e32 vcc_lo, s2, v0
s_cselect_b32 s2, -1, 0
s_cmp_gt_i32 s5, 0
v_cndmask_b32_e32 v0, v4, v5, vcc_lo
v_cvt_u32_f32_e32 v4, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_xor_b32_e32 v0, v0, v6
v_mul_lo_u32 v5, s1, v4
s_mul_i32 s1, s6, s5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v0, v0, v6
v_mul_hi_u32 v5, v4, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v6, 31, v0
v_add_nc_u32_e32 v0, v0, v6
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v4, v4, v5
v_xor_b32_e32 v0, v0, v6
v_xor_b32_e32 v6, s3, v6
s_mul_i32 s3, s1, s7
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_mul_lo_u32 v9, v3, s3
v_mul_hi_u32 v4, v0, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v5, v4, s4
v_sub_nc_u32_e32 v0, v0, v5
v_add_nc_u32_e32 v5, 1, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_subrev_nc_u32_e32 v7, s4, v0
v_cmp_le_u32_e32 vcc_lo, s4, v0
v_cndmask_b32_e32 v4, v4, v5, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_cndmask_b32 v0, v0, v7 :: v_dual_add_nc_u32 v5, 1, v4
v_cmp_le_u32_e32 vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v0, v4, v5, vcc_lo
v_xor_b32_e32 v0, v0, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v0, v0, v6
v_mul_lo_u32 v10, v0, s3
v_mov_b32_e32 v0, 0
s_cselect_b32 s3, -1, 0
.LBB0_3: ; %.preheader65
; =>This Loop Header: Depth=1
; Child Loop BB0_5 Depth 2
; Child Loop BB0_7 Depth 3
s_and_not1_b32 vcc_lo, exec_lo, s2
s_cbranch_vccnz .LBB0_9
; %bb.4: ; %.preheader.lr.ph
; in Loop: Header=BB0_3 Depth=1
s_delay_alu instid0(VALU_DEP_2)
v_dual_mov_b32 v11, v9 :: v_dual_mov_b32 v4, v10
s_mov_b32 s4, 0
.LBB0_5: ; %.preheader
; Parent Loop BB0_3 Depth=1
; => This Loop Header: Depth=2
; Child Loop BB0_7 Depth 3
s_and_not1_b32 vcc_lo, exec_lo, s3
s_cbranch_vccnz .LBB0_8
; %bb.6: ; %.lr.ph
; in Loop: Header=BB0_5 Depth=2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v5, 31, v4
v_mov_b32_e32 v7, v11
s_mov_b32 s8, s5
v_lshlrev_b64 v[5:6], 2, v[4:5]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v5, vcc_lo, s12, v5
v_add_co_ci_u32_e32 v6, vcc_lo, s13, v6, vcc_lo
.LBB0_7: ; Parent Loop BB0_3 Depth=1
; Parent Loop BB0_5 Depth=2
; => This Inner Loop Header: Depth=3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_ashrrev_i32_e32 v8, 31, v7
s_add_i32 s8, s8, -1
s_cmp_eq_u32 s8, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[12:13], 2, v[7:8]
v_add_co_u32 v12, vcc_lo, s16, v12
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v13, vcc_lo, s17, v13, vcc_lo
global_load_b32 v8, v[5:6], off
global_load_b32 v12, v[12:13], off
v_add_co_u32 v5, vcc_lo, v5, 4
v_add_co_ci_u32_e32 v6, vcc_lo, 0, v6, vcc_lo
s_waitcnt vmcnt(0)
v_dual_fmac_f32 v0, v8, v12 :: v_dual_add_nc_u32 v7, 1, v7
s_cbranch_scc0 .LBB0_7
.LBB0_8: ; %._crit_edge
; in Loop: Header=BB0_5 Depth=2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_add_nc_u32_e32 v4, s5, v4
v_add_nc_u32_e32 v11, s5, v11
s_add_i32 s4, s4, 1
s_cmp_eq_u32 s4, s6
s_cbranch_scc0 .LBB0_5
.LBB0_9: ; %._crit_edge70
; in Loop: Header=BB0_3 Depth=1
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_add_nc_u32_e32 v10, s1, v10
v_add_nc_u32_e32 v9, s1, v9
s_add_i32 s0, s0, 1
s_cmp_eq_u32 s0, s7
s_cbranch_scc0 .LBB0_3
s_branch .LBB0_11
.LBB0_10:
v_mov_b32_e32 v0, 0
.LBB0_11: ; %._crit_edge74
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v4, 31, v3
v_lshlrev_b64 v[1:2], 2, v[1:2]
v_lshlrev_b64 v[3:4], 2, v[3:4]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v3, vcc_lo, s18, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s19, v4, vcc_lo
global_load_b32 v3, v[3:4], off
s_waitcnt vmcnt(0)
v_add_f32_e32 v3, v0, v3
v_add_co_u32 v0, vcc_lo, s14, v1
v_add_co_ci_u32_e32 v1, vcc_lo, s15, v2, vcc_lo
global_store_b32 v[0:1], v3, off
.LBB0_12:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z19calcDenseForwardGPUPfS_S_S_iiiiiii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 320
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 14
.amdhsa_next_free_sgpr 20
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z19calcDenseForwardGPUPfS_S_S_iiiiiii, .Lfunc_end0-_Z19calcDenseForwardGPUPfS_S_S_iiiiiii
; -- End function
.section .AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1004
; NumSgprs: 22
; NumVgprs: 14
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 22
; NumVGPRsForWavesPerEU: 14
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object ; @__hip_cuid_
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0 ; 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 36
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: by_value
- .offset: 44
.size: 4
.value_kind: by_value
- .offset: 48
.size: 4
.value_kind: by_value
- .offset: 52
.size: 4
.value_kind: by_value
- .offset: 56
.size: 4
.value_kind: by_value
- .offset: 64
.size: 4
.value_kind: hidden_block_count_x
- .offset: 68
.size: 4
.value_kind: hidden_block_count_y
- .offset: 72
.size: 4
.value_kind: hidden_block_count_z
- .offset: 76
.size: 2
.value_kind: hidden_group_size_x
- .offset: 78
.size: 2
.value_kind: hidden_group_size_y
- .offset: 80
.size: 2
.value_kind: hidden_group_size_z
- .offset: 82
.size: 2
.value_kind: hidden_remainder_x
- .offset: 84
.size: 2
.value_kind: hidden_remainder_y
- .offset: 86
.size: 2
.value_kind: hidden_remainder_z
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 112
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 120
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 128
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 320
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z19calcDenseForwardGPUPfS_S_S_iiiiiii
.private_segment_fixed_size: 0
.sgpr_count: 22
.sgpr_spill_count: 0
.symbol: _Z19calcDenseForwardGPUPfS_S_S_iiiiiii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 14
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
```
| 5,778 | 6,849 |
87 |
Convert the following CUDA host assembly code to AMD host assembly:
```cudaasm
.file "tmpxft_00008dc1_00000000-6_calcDenseForwardGPU.cudafe1.cpp"
.text
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z52__device_stub__Z19calcDenseForwardGPUPfS_S_S_iiiiiiiPfS_S_S_iiiiiii
.type _Z52__device_stub__Z19calcDenseForwardGPUPfS_S_S_iiiiiiiPfS_S_S_iiiiiii, @function
_Z52__device_stub__Z19calcDenseForwardGPUPfS_S_S_iiiiiiiPfS_S_S_iiiiiii:
.LFB2051:
.cfi_startproc
endbr64
subq $216, %rsp
.cfi_def_cfa_offset 224
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movl %r8d, 12(%rsp)
movl %r9d, 8(%rsp)
movq %fs:40, %rax
movq %rax, 200(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 12(%rsp), %rax
movq %rax, 144(%rsp)
leaq 8(%rsp), %rax
movq %rax, 152(%rsp)
leaq 224(%rsp), %rax
movq %rax, 160(%rsp)
leaq 232(%rsp), %rax
movq %rax, 168(%rsp)
leaq 240(%rsp), %rax
movq %rax, 176(%rsp)
leaq 248(%rsp), %rax
movq %rax, 184(%rsp)
leaq 256(%rsp), %rax
movq %rax, 192(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 200(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $216, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 232
pushq 56(%rsp)
.cfi_def_cfa_offset 240
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z19calcDenseForwardGPUPfS_S_S_iiiiiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 224
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z52__device_stub__Z19calcDenseForwardGPUPfS_S_S_iiiiiiiPfS_S_S_iiiiiii, .-_Z52__device_stub__Z19calcDenseForwardGPUPfS_S_S_iiiiiiiPfS_S_S_iiiiiii
.globl _Z19calcDenseForwardGPUPfS_S_S_iiiiiii
.type _Z19calcDenseForwardGPUPfS_S_S_iiiiiii, @function
_Z19calcDenseForwardGPUPfS_S_S_iiiiiii:
.LFB2052:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
movl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
movl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 40
movl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 48
movl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 56
movl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 64
call _Z52__device_stub__Z19calcDenseForwardGPUPfS_S_S_iiiiiiiPfS_S_S_iiiiiii
addq $56, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z19calcDenseForwardGPUPfS_S_S_iiiiiii, .-_Z19calcDenseForwardGPUPfS_S_S_iiiiiii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z19calcDenseForwardGPUPfS_S_S_iiiiiii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z19calcDenseForwardGPUPfS_S_S_iiiiiii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
```
|
```amdasm
.text
.file "calcDenseForwardGPU.hip"
.globl _Z34__device_stub__calcDenseForwardGPUPfS_S_S_iiiiiii # -- Begin function _Z34__device_stub__calcDenseForwardGPUPfS_S_S_iiiiiii
.type _Z34__device_stub__calcDenseForwardGPUPfS_S_S_iiiiiii,@function
_Z34__device_stub__calcDenseForwardGPUPfS_S_S_iiiiiii: # @_Z34__device_stub__calcDenseForwardGPUPfS_S_S_iiiiiii
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $192, %rsp
.cfi_def_cfa_offset 240
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 56(%rsp), %rax
movq %rdi, (%rax)
leaq 48(%rsp), %rdi
movq %rsi, (%rdi)
leaq 40(%rsp), %rsi
movq %rdx, (%rsi)
leaq 32(%rsp), %rdx
movq %rcx, (%rdx)
leaq 12(%rsp), %rcx
movl %r8d, (%rcx)
leaq 8(%rsp), %r8
movl %r9d, (%r8)
leaq 96(%rsp), %rbx
movq %rax, (%rbx)
movq %rdi, 8(%rbx)
movq %rsi, 16(%rbx)
movq %rdx, 24(%rbx)
movq %rcx, 32(%rbx)
movq %r8, 40(%rbx)
leaq 240(%rsp), %rax
movq %rax, 48(%rbx)
leaq 248(%rsp), %rax
movq %rax, 56(%rbx)
leaq 256(%rsp), %rax
movq %rax, 64(%rbx)
leaq 264(%rsp), %rax
movq %rax, 72(%rbx)
leaq 272(%rsp), %rax
movq %rax, 80(%rbx)
leaq 80(%rsp), %r14
leaq 64(%rsp), %r15
leaq 24(%rsp), %r12
leaq 16(%rsp), %r13
movq %r14, %rdi
movq %r15, %rsi
movq %r12, %rdx
movq %r13, %rcx
callq __hipPopCallConfiguration
movq (%r14), %rsi
movl 8(%r14), %edx
movq (%r15), %rcx
movl 8(%r15), %r8d
movl $_Z19calcDenseForwardGPUPfS_S_S_iiiiiii, %edi
movq %rbx, %r9
pushq (%r13)
.cfi_adjust_cfa_offset 8
pushq (%r12)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $208, %rsp
.cfi_adjust_cfa_offset -208
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z34__device_stub__calcDenseForwardGPUPfS_S_S_iiiiiii, .Lfunc_end0-_Z34__device_stub__calcDenseForwardGPUPfS_S_S_iiiiiii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, %rdi
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z19calcDenseForwardGPUPfS_S_S_iiiiiii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z19calcDenseForwardGPUPfS_S_S_iiiiiii,@object # @_Z19calcDenseForwardGPUPfS_S_S_iiiiiii
.section .rodata,"a",@progbits
.globl _Z19calcDenseForwardGPUPfS_S_S_iiiiiii
.p2align 3, 0x0
_Z19calcDenseForwardGPUPfS_S_S_iiiiiii:
.quad _Z34__device_stub__calcDenseForwardGPUPfS_S_S_iiiiiii
.size _Z19calcDenseForwardGPUPfS_S_S_iiiiiii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z19calcDenseForwardGPUPfS_S_S_iiiiiii"
.size .L__unnamed_1, 39
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z34__device_stub__calcDenseForwardGPUPfS_S_S_iiiiiii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z19calcDenseForwardGPUPfS_S_S_iiiiiii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
```
| 2,388 | 2,420 |
88 |
Convert the following CUDA device assembly code to AMD device assembly:
```cudaasm
code for sm_80
```
|
```amdasm
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object ; @__hip_cuid_
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0 ; 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
```
| 24 | 306 |
89 |
Convert the following CUDA host assembly code to AMD host assembly:
```cudaasm
.file "tmpxft_001a6fc1_00000000-6_test_sort_mat.cudafe1.cpp"
.text
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "%d "
.LC3:
.string "\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $352, %rsp
.cfi_def_cfa_offset 384
movq %fs:40, %rax
movq %rax, 344(%rsp)
xorl %eax, %eax
movl $0x00000000, 80(%rsp)
movss .LC1(%rip), %xmm0
movss %xmm0, 84(%rsp)
movss %xmm0, 88(%rsp)
movss %xmm0, 92(%rsp)
movss %xmm0, 96(%rsp)
movl $0x00000000, 100(%rsp)
movss %xmm0, 104(%rsp)
movl $0x00000000, 108(%rsp)
movss %xmm0, 112(%rsp)
movss %xmm0, 116(%rsp)
movss %xmm0, 120(%rsp)
movss %xmm0, 124(%rsp)
movss %xmm0, 128(%rsp)
movl $0x00000000, 132(%rsp)
movss %xmm0, 136(%rsp)
movl $0x00000000, 140(%rsp)
movl $0x00000000, 144(%rsp)
movss %xmm0, 148(%rsp)
movss %xmm0, 152(%rsp)
movss %xmm0, 156(%rsp)
movl $0x00000000, 160(%rsp)
movl $0x00000000, 164(%rsp)
movss %xmm0, 168(%rsp)
movl $0x00000000, 172(%rsp)
movl $0x00000000, 176(%rsp)
movss %xmm0, 180(%rsp)
movl $0x00000000, 184(%rsp)
movl $0x00000000, 188(%rsp)
movss %xmm0, 192(%rsp)
movl $0x00000000, 196(%rsp)
movss %xmm0, 200(%rsp)
movl $0x00000000, 204(%rsp)
movl $0x00000000, 208(%rsp)
movss %xmm0, 212(%rsp)
movss %xmm0, 216(%rsp)
movss %xmm0, 220(%rsp)
movss %xmm0, 224(%rsp)
movss %xmm0, 228(%rsp)
movss %xmm0, 232(%rsp)
movss %xmm0, 236(%rsp)
movl $0x00000000, 240(%rsp)
movl $0x00000000, 244(%rsp)
movl $0x00000000, 248(%rsp)
movl $0x00000000, 252(%rsp)
movl $0x00000000, 256(%rsp)
movl $0x00000000, 260(%rsp)
movl $0x00000000, 264(%rsp)
movl $0x00000000, 268(%rsp)
movl $0x00000000, 272(%rsp)
movss %xmm0, 276(%rsp)
movl $0x00000000, 280(%rsp)
movl $0x00000000, 284(%rsp)
movl $0x00000000, 288(%rsp)
movl $0x00000000, 292(%rsp)
movss %xmm0, 296(%rsp)
movl $0x00000000, 300(%rsp)
movl $0x00000000, 304(%rsp)
movl $0x00000000, 308(%rsp)
movl $0x00000000, 312(%rsp)
movl $0x00000000, 316(%rsp)
movl $0x00000000, 320(%rsp)
movl $0x00000000, 324(%rsp)
movss %xmm0, 328(%rsp)
movl $0x00000000, 332(%rsp)
movl $0, 48(%rsp)
movl $1, 52(%rsp)
movl $2, 56(%rsp)
movl $3, 60(%rsp)
movl $4, 64(%rsp)
movl $5, 68(%rsp)
movl $6, 72(%rsp)
movl $7, 76(%rsp)
leaq 8(%rsp), %rdi
movl $256, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $32, %esi
call cudaMalloc@PLT
leaq 80(%rsp), %rsi
movl $1, %ecx
movl $256, %edx
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
leaq 48(%rsp), %rsi
movl $1, %ecx
movl $32, %edx
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $8, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 36(%rsp), %rdx
movl $1, %ecx
movq 24(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L9
.L4:
call cudaDeviceSynchronize@PLT
leaq 48(%rsp), %rbx
movl $2, %ecx
movl $32, %edx
movq 16(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
leaq 80(%rsp), %r12
leaq .LC2(%rip), %rbp
.L5:
movl (%rbx), %edx
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %r12, %rbx
jne .L5
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 344(%rsp), %rax
subq %fs:40, %rax
jne .L10
movl $0, %eax
addq $352, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L9:
.cfi_restore_state
movq 16(%rsp), %rdx
movl $8, %esi
movq 8(%rsp), %rdi
call _Z12bitonic_sortPfiPi@PLT
jmp .L4
.L10:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC1:
.long 1065353216
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
```
|
```amdasm
.text
.file "test_sort_mat.hip"
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0 # -- Begin function main
.LCPI0_0:
.long 0 # 0x0
.long 1 # 0x1
.long 2 # 0x2
.long 3 # 0x3
.LCPI0_1:
.long 4 # 0x4
.long 5 # 0x5
.long 6 # 0x6
.long 7 # 0x7
.text
.globl main
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $312, %rsp # imm = 0x138
.cfi_def_cfa_offset 352
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 48(%rsp), %r14
movl $.L__const.main.arr, %esi
movl $256, %edx # imm = 0x100
movq %r14, %rdi
callq memcpy@PLT
movaps .LCPI0_0(%rip), %xmm0 # xmm0 = [0,1,2,3]
leaq 16(%rsp), %rbx
movaps %xmm0, (%rbx)
movaps .LCPI0_1(%rip), %xmm0 # xmm0 = [4,5,6,7]
movaps %xmm0, 16(%rbx)
leaq 8(%rsp), %r15
movl $256, %esi # imm = 0x100
movq %r15, %rdi
callq hipMalloc
movq %rsp, %r12
movl $32, %esi
movq %r12, %rdi
callq hipMalloc
movq (%r15), %rdi
movl $256, %edx # imm = 0x100
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movq (%r12), %rdi
movl $32, %edx
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 7(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB0_2
# %bb.1:
movq 8(%rsp), %rdi
movq (%rsp), %rdx
movl $8, %esi
callq _Z27__device_stub__bitonic_sortPfiPi
.LBB0_2:
callq hipDeviceSynchronize
movq (%rsp), %rsi
leaq 16(%rsp), %rdi
movl $32, %edx
movl $2, %ecx
callq hipMemcpy
xorl %ebx, %ebx
.LBB0_3: # =>This Inner Loop Header: Depth=1
movl 16(%rsp,%rbx,4), %esi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
incq %rbx
cmpq $8, %rbx
jne .LBB0_3
# %bb.4:
movl $10, %edi
callq putchar@PLT
xorl %eax, %eax
addq $312, %rsp # imm = 0x138
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.type .L__const.main.arr,@object # @__const.main.arr
.section .rodata,"a",@progbits
.p2align 4, 0x0
.L__const.main.arr:
.long 0x00000000 # float 0
.long 0x3f800000 # float 1
.long 0x3f800000 # float 1
.long 0x3f800000 # float 1
.long 0x3f800000 # float 1
.long 0x00000000 # float 0
.long 0x3f800000 # float 1
.long 0x00000000 # float 0
.long 0x3f800000 # float 1
.long 0x3f800000 # float 1
.long 0x3f800000 # float 1
.long 0x3f800000 # float 1
.long 0x3f800000 # float 1
.long 0x00000000 # float 0
.long 0x3f800000 # float 1
.long 0x00000000 # float 0
.long 0x00000000 # float 0
.long 0x3f800000 # float 1
.long 0x3f800000 # float 1
.long 0x3f800000 # float 1
.long 0x00000000 # float 0
.long 0x00000000 # float 0
.long 0x3f800000 # float 1
.long 0x00000000 # float 0
.long 0x00000000 # float 0
.long 0x3f800000 # float 1
.long 0x00000000 # float 0
.long 0x00000000 # float 0
.long 0x3f800000 # float 1
.long 0x00000000 # float 0
.long 0x3f800000 # float 1
.long 0x00000000 # float 0
.long 0x00000000 # float 0
.long 0x3f800000 # float 1
.long 0x3f800000 # float 1
.long 0x3f800000 # float 1
.long 0x3f800000 # float 1
.long 0x3f800000 # float 1
.long 0x3f800000 # float 1
.long 0x3f800000 # float 1
.long 0x00000000 # float 0
.long 0x00000000 # float 0
.long 0x00000000 # float 0
.long 0x00000000 # float 0
.long 0x00000000 # float 0
.long 0x00000000 # float 0
.long 0x00000000 # float 0
.long 0x00000000 # float 0
.long 0x00000000 # float 0
.long 0x3f800000 # float 1
.long 0x00000000 # float 0
.long 0x00000000 # float 0
.long 0x00000000 # float 0
.long 0x00000000 # float 0
.long 0x3f800000 # float 1
.long 0x00000000 # float 0
.long 0x00000000 # float 0
.long 0x00000000 # float 0
.long 0x00000000 # float 0
.long 0x00000000 # float 0
.long 0x00000000 # float 0
.long 0x00000000 # float 0
.long 0x3f800000 # float 1
.long 0x00000000 # float 0
.size .L__const.main.arr, 256
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%d "
.size .L.str, 4
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
```
| 3,068 | 2,715 |
90 |
Convert the following CUDA device assembly code to AMD device assembly:
```cudaasm
code for sm_80
```
|
```amdasm
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object ; @__hip_cuid_
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0 ; 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
```
| 24 | 306 |
91 |
Convert the following CUDA host assembly code to AMD host assembly:
```cudaasm
.file "tmpxft_001bdc9d_00000000-6_utilities.cudafe1.cpp"
.text
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2162:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2162:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z16get_current_timev
.type _Z16get_current_timev, @function
_Z16get_current_timev:
.LFB2156:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _ZNSt6chrono3_V212system_clock3nowEv@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2156:
.size _Z16get_current_timev, .-_Z16get_current_timev
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "r"
.LC1:
.string "datread: cannot open <%s>\n"
.LC2:
.string "%d %d"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC3:
.string "datread: size mismatch, (nx,ny) = (%d,%d) expected (%d,%d)\n"
.section .rodata.str1.1
.LC4:
.string "%d"
.text
.globl _Z7datreadPcPvii
.type _Z7datreadPcPvii, @function
_Z7datreadPcPvii:
.LFB2157:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $56, %rsp
.cfi_def_cfa_offset 112
movq %rdi, %rbx
movq %rsi, 8(%rsp)
movl %edx, %r14d
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
leaq .LC0(%rip), %rsi
call fopen@PLT
testq %rax, %rax
je .L16
movq %rax, %r12
leaq 32(%rsp), %rcx
leaq 28(%rsp), %rdx
leaq .LC2(%rip), %rsi
movq %rax, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
movl 28(%rsp), %ecx
cmpl %r14d, %ecx
jne .L7
movl 4(%rsp), %eax
cmpl %eax, 32(%rsp)
jne .L7
testl %eax, %eax
jle .L8
subl $1, %eax
imull %r14d, %eax
movl %eax, (%rsp)
movl $0, %r15d
leaq .LC4(%rip), %r13
jmp .L9
.L16:
movq %rbx, %rcx
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.L7:
subq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 120
movl 12(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 128
movl %r14d, %r9d
movl 48(%rsp), %r8d
leaq .LC3(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.L11:
.cfi_restore_state
movslq (%rsp), %rdx
movq 8(%rsp), %rcx
leaq (%rcx,%rdx,4), %rbx
movslq %r14d, %rax
addq %rdx, %rax
leaq (%rcx,%rax,4), %rbp
.L10:
leaq 36(%rsp), %rdx
movq %r13, %rsi
movq %r12, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
pxor %xmm0, %xmm0
cvtsi2ssl 36(%rsp), %xmm0
movss %xmm0, (%rbx)
addq $4, %rbx
cmpq %rbp, %rbx
jne .L10
.L12:
addl $1, %r15d
subl %r14d, (%rsp)
cmpl %r15d, 4(%rsp)
je .L8
.L9:
testl %r14d, %r14d
jg .L11
jmp .L12
.L8:
movq %r12, %rdi
call fclose@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L17
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L17:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2157:
.size _Z7datreadPcPvii, .-_Z7datreadPcPvii
.section .rodata.str1.1
.LC5:
.string "w"
.LC6:
.string "pgmwrite: cannot create <%s>\n"
.LC8:
.string "P2\n"
.LC9:
.string "
.LC10:
.string "%d %d\n"
.LC11:
.string "%d\n"
.LC15:
.string "%3d "
.LC16:
.string "\n"
.text
.globl _Z8pgmwritePcPvii
.type _Z8pgmwritePcPvii, @function
_Z8pgmwritePcPvii:
.LFB2158:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $40, %rsp
.cfi_def_cfa_offset 96
movq %rdi, %rbx
movq %rsi, 24(%rsp)
movl %edx, %r15d
movl %ecx, %r14d
leaq .LC5(%rip), %rsi
call fopen@PLT
testq %rax, %rax
je .L47
movq %rax, %r12
movq 24(%rsp), %rsi
movq %rsi, %rax
movss (%rsi), %xmm0
movaps %xmm0, %xmm7
andps .LC7(%rip), %xmm7
movss %xmm7, 12(%rsp)
movl %r15d, %edx
imull %r14d, %edx
testl %edx, %edx
jle .L38
movslq %edx, %rdx
leaq (%rsi,%rdx,4), %rdx
movss %xmm7, 16(%rsp)
movss .LC7(%rip), %xmm1
.L23:
movss (%rax), %xmm0
andps %xmm1, %xmm0
movaps %xmm0, %xmm7
minss 12(%rsp), %xmm7
movss %xmm7, 12(%rsp)
maxss 16(%rsp), %xmm0
movss %xmm0, 16(%rsp)
addq $4, %rax
cmpq %rdx, %rax
jne .L23
.L20:
leaq .LC8(%rip), %rdx
movl $2, %esi
movq %r12, %rdi
movl $0, %eax
call __fprintf_chk@PLT
leaq .LC9(%rip), %rdx
movl $2, %esi
movq %r12, %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %r14d, %r8d
movl %r15d, %ecx
leaq .LC10(%rip), %rdx
movl $2, %esi
movq %r12, %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $255, %ecx
leaq .LC11(%rip), %rdx
movl $2, %esi
movq %r12, %rdi
movl $0, %eax
call __fprintf_chk@PLT
subl $1, %r14d
js .L24
movl %r14d, %eax
imull %r15d, %eax
movl %eax, 20(%rsp)
movl $0, %ebx
jmp .L25
.L47:
movq %rbx, %rcx
leaq .LC6(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.L38:
movss 12(%rsp), %xmm7
movss %xmm7, 16(%rsp)
jmp .L20
.L26:
movss 12(%rsp), %xmm2
subss %xmm2, %xmm0
andps .LC7(%rip), %xmm0
movss 16(%rsp), %xmm1
subss %xmm2, %xmm1
divss %xmm1, %xmm0
mulss .LC13(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
addsd .LC14(%rip), %xmm0
cvttsd2sil %xmm0, %eax
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
.L29:
divss .LC13(%rip), %xmm0
pxor %xmm5, %xmm5
ucomiss %xmm0, %xmm5
ja .L45
sqrtss %xmm0, %xmm0
.L32:
mulss .LC13(%rip), %xmm0
cvttss2sil %xmm0, %ecx
leaq .LC15(%rip), %rdx
movl $2, %esi
movq %r12, %rdi
movl $0, %eax
call __fprintf_chk@PLT
addl $1, %ebx
testb $15, %bl
je .L48
.L33:
addq $4, %rbp
cmpl %r13d, %ebx
je .L37
.L34:
movss 0(%rbp), %xmm0
pxor %xmm3, %xmm3
comiss 12(%rsp), %xmm3
ja .L26
movss 16(%rsp), %xmm6
comiss .LC13(%rip), %xmm6
ja .L26
andps .LC7(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
addsd .LC14(%rip), %xmm0
cvttsd2sil %xmm0, %eax
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
jmp .L29
.L45:
call sqrtf@PLT
jmp .L32
.L48:
leaq .LC16(%rip), %rdx
movl $2, %esi
movq %r12, %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L33
.L37:
subl $1, %r14d
subl %r15d, 20(%rsp)
cmpl $-1, %r14d
je .L35
.L25:
testl %r15d, %r15d
jle .L37
movslq 20(%rsp), %rax
movq 24(%rsp), %rdi
leaq (%rdi,%rax,4), %rbp
leal (%rbx,%r15), %r13d
jmp .L34
.L35:
testb $15, %bl
jne .L49
.L24:
movq %r12, %rdi
call fclose@PLT
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L49:
.cfi_restore_state
leaq .LC16(%rip), %rdx
movl $2, %esi
movq %r12, %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L24
.cfi_endproc
.LFE2158:
.size _Z8pgmwritePcPvii, .-_Z8pgmwritePcPvii
.section .rodata.str1.1
.LC17:
.string "Cuda error: %s: %s.\n"
.text
.globl _Z14checkCUDAErrorPKc
.type _Z14checkCUDAErrorPKc, @function
_Z14checkCUDAErrorPKc:
.LFB2159:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movq %rdi, %rbx
call cudaGetLastError@PLT
testl %eax, %eax
jne .L53
popq %rbx
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L53:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
movq %rbx, %rcx
leaq .LC17(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.cfi_endproc
.LFE2159:
.size _Z14checkCUDAErrorPKc, .-_Z14checkCUDAErrorPKc
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2185:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2185:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst16,"aM",@progbits,16
.align 16
.LC7:
.long 2147483647
.long 0
.long 0
.long 0
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC13:
.long 1132396544
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC14:
.long 0
.long 1071644672
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
```
|
```amdasm
.text
.file "utilities.hip"
.globl _Z16get_current_timev # -- Begin function _Z16get_current_timev
.type _Z16get_current_timev,@function
_Z16get_current_timev: # @_Z16get_current_timev
.cfi_startproc
# %bb.0:
jmp _ZNSt6chrono3_V212system_clock3nowEv # TAILCALL
.Lfunc_end0:
.size _Z16get_current_timev, .Lfunc_end0-_Z16get_current_timev
.cfi_endproc
# -- End function
.globl _Z7datreadPcPvii # -- Begin function _Z7datreadPcPvii
.type _Z7datreadPcPvii,@function
_Z7datreadPcPvii: # @_Z7datreadPcPvii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $40, %rsp
.cfi_def_cfa_offset 96
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %ecx, %ebp
movl %edx, %ebx
movq %rsi, %r15
movq %rdi, %r12
movl $.L.str, %esi
callq fopen
testq %rax, %rax
je .LBB1_10
# %bb.1:
movq %rax, %r14
leaq 36(%rsp), %r12
leaq 32(%rsp), %r13
movl $.L.str.2, %esi
movq %rax, %rdi
movq %r12, %rdx
movq %r13, %rcx
xorl %eax, %eax
callq __isoc23_fscanf
movl (%r12), %edx
movl (%r13), %ecx
cmpl %ebx, %edx
movl %ebx, %r8d
jne .LBB1_12
# %bb.2:
cmpl %ebp, %ecx
jne .LBB1_12
# %bb.3: # %.preheader25
testl %ebp, %ebp
jle .LBB1_9
# %bb.4: # %.preheader.lr.ph
movslq %r8d, %rcx
movl %ebp, %eax
movl %r8d, %ebp
movq %rax, 16(%rsp) # 8-byte Spill
decq %rax
imulq %rcx, %rax
leaq (%r15,%rax,4), %rbx
shlq $2, %rcx
negq %rcx
movq %rcx, 24(%rsp) # 8-byte Spill
leaq 12(%rsp), %r15
xorl %r13d, %r13d
movl %r8d, 8(%rsp) # 4-byte Spill
.LBB1_5: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB1_7 Depth 2
testl %r8d, %r8d
jle .LBB1_8
# %bb.6: # %.lr.ph
# in Loop: Header=BB1_5 Depth=1
xorl %r12d, %r12d
.LBB1_7: # Parent Loop BB1_5 Depth=1
# => This Inner Loop Header: Depth=2
movl $.L.str.4, %esi
movq %r14, %rdi
movq %r15, %rdx
xorl %eax, %eax
callq __isoc23_fscanf
xorps %xmm0, %xmm0
cvtsi2ssl 12(%rsp), %xmm0
movss %xmm0, (%rbx,%r12,4)
incq %r12
cmpq %r12, %rbp
jne .LBB1_7
.LBB1_8: # %._crit_edge
# in Loop: Header=BB1_5 Depth=1
incq %r13
addq 24(%rsp), %rbx # 8-byte Folded Reload
cmpq 16(%rsp), %r13 # 8-byte Folded Reload
movl 8(%rsp), %r8d # 4-byte Reload
jne .LBB1_5
.LBB1_9: # %._crit_edge28
movq %r14, %rdi
callq fclose
addq $40, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB1_10:
.cfi_def_cfa_offset 96
movq stderr(%rip), %rdi
movl $.L.str.1, %esi
movq %r12, %rdx
xorl %eax, %eax
callq fprintf
jmp .LBB1_11
.LBB1_12:
movq stderr(%rip), %rdi
movl $.L.str.3, %esi
movl %ebp, %r9d
xorl %eax, %eax
callq fprintf
.LBB1_11:
movl $-1, %edi
callq exit
.Lfunc_end1:
.size _Z7datreadPcPvii, .Lfunc_end1-_Z7datreadPcPvii
.cfi_endproc
# -- End function
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0 # -- Begin function _Z8pgmwritePcPvii
.LCPI2_0:
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0
.LCPI2_1:
.long 0x437f0000 # float 255
.LCPI2_3:
.long 0x00000000 # float 0
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0
.LCPI2_2:
.quad 0x3fe0000000000000 # double 0.5
.text
.globl _Z8pgmwritePcPvii
.type _Z8pgmwritePcPvii,@function
_Z8pgmwritePcPvii: # @_Z8pgmwritePcPvii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $88, %rsp
.cfi_def_cfa_offset 144
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %ecx, %r14d
movl %edx, %ebp
movq %rsi, %r15
movq %rdi, %r12
movl $.L.str.5, %esi
callq fopen
testq %rax, %rax
je .LBB2_23
# %bb.1:
movq %rax, %rbx
movss (%r15), %xmm0 # xmm0 = mem[0],zero,zero,zero
andps .LCPI2_0(%rip), %xmm0
movl %r14d, %eax
movl %ebp, 4(%rsp) # 4-byte Spill
imull %ebp, %eax
testl %eax, %eax
jle .LBB2_2
# %bb.3: # %.lr.ph.preheader
movl %eax, %eax
xorl %ecx, %ecx
movaps .LCPI2_0(%rip), %xmm1 # xmm1 = [NaN,NaN,NaN,NaN]
movaps %xmm0, %xmm2
.LBB2_4: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movss (%r15,%rcx,4), %xmm3 # xmm3 = mem[0],zero,zero,zero
andps %xmm1, %xmm3
movaps %xmm3, %xmm4
minss %xmm2, %xmm4
maxss %xmm0, %xmm3
incq %rcx
movaps %xmm3, %xmm0
movaps %xmm4, %xmm2
cmpq %rcx, %rax
jne .LBB2_4
jmp .LBB2_5
.LBB2_2:
movaps %xmm0, %xmm4
movaps %xmm0, %xmm3
.LBB2_5: # %._crit_edge
movaps %xmm4, 64(%rsp) # 16-byte Spill
movaps %xmm3, 32(%rsp) # 16-byte Spill
movl $1, %r12d
movl $.L.str.7, %edi
movl $3, %esi
movl $1, %edx
movq %rbx, %rcx
callq fwrite@PLT
movl $.L.str.8, %edi
movl $22, %esi
movl $1, %edx
movq %rbx, %rcx
callq fwrite@PLT
movl $.L.str.9, %esi
movq %rbx, %rdi
movl 4(%rsp), %ebp # 4-byte Reload
movl %ebp, %edx
movl %r14d, %ecx
xorl %eax, %eax
callq fprintf
movl $.L.str.10, %esi
movq %rbx, %rdi
movl $255, %edx
xorl %eax, %eax
callq fprintf
testl %r14d, %r14d
jle .LBB2_22
# %bb.6: # %.preheader.lr.ph
movss .LCPI2_1(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero
movaps 32(%rsp), %xmm2 # 16-byte Reload
cmpltps %xmm2, %xmm0
xorps %xmm4, %xmm4
movaps 64(%rsp), %xmm3 # 16-byte Reload
movaps %xmm3, %xmm1
cmpltps %xmm4, %xmm1
orps %xmm0, %xmm1
movaps %xmm2, %xmm0
movd %xmm1, %r13d
subss %xmm3, %xmm0
movl %r14d, 8(%rsp) # 4-byte Spill
movl %r14d, %edx
movslq %ebp, %rcx
testl %ebp, %ebp
movl $0, %eax
cmovgl %ebp, %eax
movq %rax, 16(%rsp) # 8-byte Spill
movl %ebp, %r14d
movq %rdx, 24(%rsp) # 8-byte Spill
leaq -1(%rdx), %rax
imulq %rcx, %rax
leaq (%r15,%rax,4), %r15
shlq $2, %rcx
negq %rcx
movq %rcx, 56(%rsp) # 8-byte Spill
movss .LCPI2_1(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero
movl $0, 12(%rsp) # 4-byte Folded Spill
movaps %xmm0, 32(%rsp) # 16-byte Spill
.LBB2_9: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB2_11 Depth 2
testl %ebp, %ebp
jle .LBB2_8
# %bb.10: # %.lr.ph72
# in Loop: Header=BB2_9 Depth=1
xorl %ebp, %ebp
.LBB2_11: # Parent Loop BB2_9 Depth=1
# => This Inner Loop Header: Depth=2
movss (%r15,%rbp,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
testb $1, %r13b
je .LBB2_13
# %bb.12: # in Loop: Header=BB2_11 Depth=2
subss %xmm3, %xmm0
andps .LCPI2_0(%rip), %xmm0
divss 32(%rsp), %xmm0 # 16-byte Folded Reload
mulss %xmm1, %xmm0
jmp .LBB2_14
.LBB2_13: # in Loop: Header=BB2_11 Depth=2
andps .LCPI2_0(%rip), %xmm0
.LBB2_14: # in Loop: Header=BB2_11 Depth=2
cvtss2sd %xmm0, %xmm0
addsd .LCPI2_2(%rip), %xmm0
cvttpd2dq %xmm0, %xmm0
cvtdq2ps %xmm0, %xmm0
divss %xmm1, %xmm0
ucomiss .LCPI2_3(%rip), %xmm0
jb .LBB2_16
# %bb.15: # in Loop: Header=BB2_11 Depth=2
sqrtss %xmm0, %xmm0
jmp .LBB2_17
.LBB2_16: # %call.sqrt
# in Loop: Header=BB2_11 Depth=2
callq sqrtf
movss .LCPI2_1(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero
.LBB2_17: # %.split
# in Loop: Header=BB2_11 Depth=2
mulss %xmm1, %xmm0
cvttss2si %xmm0, %edx
movl $.L.str.11, %esi
movq %rbx, %rdi
xorl %eax, %eax
callq fprintf
leal (%r12,%rbp), %eax
testb $15, %al
jne .LBB2_19
# %bb.18: # in Loop: Header=BB2_11 Depth=2
movl $10, %edi
movq %rbx, %rsi
callq fputc@PLT
.LBB2_19: # in Loop: Header=BB2_11 Depth=2
incq %rbp
cmpq %rbp, %r14
movaps 64(%rsp), %xmm3 # 16-byte Reload
movss .LCPI2_1(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero
jne .LBB2_11
# %bb.7: # %.loopexit.loopexit
# in Loop: Header=BB2_9 Depth=1
movl 4(%rsp), %ebp # 4-byte Reload
addl %ebp, 12(%rsp) # 4-byte Folded Spill
.LBB2_8: # %.loopexit
# in Loop: Header=BB2_9 Depth=1
movq 24(%rsp), %rcx # 8-byte Reload
leaq -1(%rcx), %rax
addq 56(%rsp), %r15 # 8-byte Folded Reload
addq 16(%rsp), %r12 # 8-byte Folded Reload
cmpq $2, %rcx
movq %rax, 24(%rsp) # 8-byte Spill
jge .LBB2_9
# %bb.20: # %._crit_edge77
movq 16(%rsp), %rax # 8-byte Reload
imull 8(%rsp), %eax # 4-byte Folded Reload
testb $15, %al
je .LBB2_22
# %bb.21:
movl $10, %edi
movq %rbx, %rsi
callq fputc@PLT
.LBB2_22: # %._crit_edge77.thread
movq %rbx, %rdi
addq $88, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
jmp fclose # TAILCALL
.LBB2_23:
.cfi_def_cfa_offset 144
movq stderr(%rip), %rdi
movl $.L.str.6, %esi
movq %r12, %rdx
xorl %eax, %eax
callq fprintf
movl $-1, %edi
callq exit
.Lfunc_end2:
.size _Z8pgmwritePcPvii, .Lfunc_end2-_Z8pgmwritePcPvii
.cfi_endproc
# -- End function
.globl _Z14checkCUDAErrorPKc # -- Begin function _Z14checkCUDAErrorPKc
.type _Z14checkCUDAErrorPKc,@function
_Z14checkCUDAErrorPKc: # @_Z14checkCUDAErrorPKc
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
pushq %rax
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movq %rdi, %rbx
callq hipGetLastError
testl %eax, %eax
jne .LBB3_2
# %bb.1:
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.LBB3_2:
.cfi_def_cfa_offset 32
movq stderr(%rip), %r14
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.13, %esi
movq %r14, %rdi
movq %rbx, %rdx
movq %rax, %rcx
xorl %eax, %eax
callq fprintf
movl $1, %edi
callq exit
.Lfunc_end3:
.size _Z14checkCUDAErrorPKc, .Lfunc_end3-_Z14checkCUDAErrorPKc
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "r"
.size .L.str, 2
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "datread: cannot open <%s>\n"
.size .L.str.1, 27
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "%d %d"
.size .L.str.2, 6
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "datread: size mismatch, (nx,ny) = (%d,%d) expected (%d,%d)\n"
.size .L.str.3, 60
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "%d"
.size .L.str.4, 3
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "w"
.size .L.str.5, 2
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "pgmwrite: cannot create <%s>\n"
.size .L.str.6, 30
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "P2\n"
.size .L.str.7, 4
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "# Written by pgmwrite\n"
.size .L.str.8, 23
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "%d %d\n"
.size .L.str.9, 7
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "%d\n"
.size .L.str.10, 4
.type .L.str.11,@object # @.str.11
.L.str.11:
.asciz "%3d "
.size .L.str.11, 5
.type .L.str.13,@object # @.str.13
.L.str.13:
.asciz "Cuda error: %s: %s.\n"
.size .L.str.13, 21
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
```
| 5,139 | 6,071 |
98 |
Convert the following CUDA device assembly code to AMD device assembly:
```cudaasm
code for sm_80
```
|
```amdasm
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object ; @__hip_cuid_
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0 ; 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
```
| 24 | 306 |
99 |
Convert the following CUDA host assembly code to AMD host assembly:
```cudaasm
.file "tmpxft_000adc47_00000000-6_DeviceProperties.cudafe1.cpp"
.text
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Enabled"
.LC1:
.string "Disabled"
.LC2:
.string "\nNumber of Devices: %d\n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC3:
.string "\n ---Device %d Information---\n"
.section .rodata.str1.1
.LC4:
.string "Name: %s\n"
.LC5:
.string "Shared Mem Per Block: %lu\n"
.LC6:
.string "Registers Per Block: %d\n"
.section .rodata.str1.8
.align 8
.LC7:
.string "Registers Per MultiProcessor: %d\n"
.section .rodata.str1.1
.LC8:
.string "Max Threads per Block: %d\n"
.section .rodata.str1.8
.align 8
.LC9:
.string "Max Threads per MultiProcessor: %d\n\n"
.section .rodata.str1.1
.LC10:
.string "Warp Size: %d\n"
.section .rodata.str1.8
.align 8
.LC11:
.string "Max thread dimensions:(%d, %d, %d)\n"
.align 8
.LC12:
.string "Max grid dimensions:(%d, %d, %d)\n\n"
.section .rodata.str1.1
.LC13:
.string "Total Global Mem: %lu\n"
.LC14:
.string "Total Constant Memory: %lu\n"
.LC15:
.string "Total Managed Memory: %d\n"
.LC16:
.string "Shared Memory Per Block: %lu\n"
.section .rodata.str1.8
.align 8
.LC17:
.string "Shared Memory Per MultiProcessor: %lu\n"
.align 8
.LC18:
.string "Device can Map Host Memory: %s\n"
.align 8
.LC19:
.string "Error Correcting code Mem: %s\n"
.section .rodata.str1.1
.LC20:
.string "Memory Bus Width: %d\n"
.LC21:
.string "Memory Pitch: %lu\n\n"
.LC22:
.string "Major Compute Capability: %d\n"
.LC23:
.string "Minor Compute Capability: %d\n"
.LC24:
.string "ClockRate: %d\n"
.LC25:
.string "MultiProcessor Count: %d\n"
.LC26:
.string "Device Overlap: %d\n"
.LC27:
.string "Kernel Execution Timeout: %s\n"
.LC28:
.string "Concurrent Kernels: %d\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $1064, %rsp
.cfi_def_cfa_offset 1120
movq %fs:40, %rax
movq %rax, 1048(%rsp)
xorl %eax, %eax
leaq 12(%rsp), %rdi
call cudaGetDeviceCount@PLT
movl 12(%rsp), %edx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
cmpl $0, 12(%rsp)
jle .L4
movl $0, %ebx
leaq .LC3(%rip), %r15
leaq .LC4(%rip), %r14
leaq .LC1(%rip), %r12
leaq .LC0(%rip), %rbp
.L8:
leaq 16(%rsp), %r13
movl %ebx, %esi
movq %r13, %rdi
call cudaGetDeviceProperties_v2@PLT
movl %ebx, %edx
movq %r15, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %r13, %rdx
movq %r14, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 312(%rsp), %rdx
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 320(%rsp), %edx
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 664(%rsp), %edx
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 336(%rsp), %edx
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 640(%rsp), %edx
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 324(%rsp), %edx
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 348(%rsp), %r8d
movl 344(%rsp), %ecx
movl 340(%rsp), %edx
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 360(%rsp), %r8d
movl 356(%rsp), %ecx
movl 352(%rsp), %edx
leaq .LC12(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 304(%rsp), %rdx
leaq .LC13(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 368(%rsp), %rdx
leaq .LC14(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 668(%rsp), %edx
leaq .LC15(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 312(%rsp), %rdx
leaq .LC16(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 656(%rsp), %rdx
leaq .LC17(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
cmpl $0, 416(%rsp)
movq %rbp, %rdx
cmove %r12, %rdx
leaq .LC18(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
cmpl $0, 596(%rsp)
movq %rbp, %rdx
cmove %r12, %rdx
leaq .LC19(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 628(%rsp), %edx
leaq .LC20(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 328(%rsp), %rdx
leaq .LC21(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 376(%rsp), %edx
leaq .LC22(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 380(%rsp), %edx
leaq .LC23(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 364(%rsp), %edx
leaq .LC24(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 404(%rsp), %edx
leaq .LC25(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 400(%rsp), %edx
leaq .LC26(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
cmpl $0, 408(%rsp)
movq %rbp, %rdx
cmove %r12, %rdx
leaq .LC27(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 592(%rsp), %edx
leaq .LC28(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $1, %ebx
cmpl %ebx, 12(%rsp)
jg .L8
.L4:
movq 1048(%rsp), %rax
subq %fs:40, %rax
jne .L15
movl $0, %eax
addq $1064, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
```
|
```amdasm
.text
.file "DeviceProperties.hip"
.globl main # -- Begin function main
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $1488, %rsp # imm = 0x5D0
.cfi_def_cfa_offset 1520
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %rbp, -16
leaq 12(%rsp), %rbx
movq %rbx, %rdi
callq hipGetDeviceCount
movl (%rbx), %esi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
cmpl $0, (%rbx)
jle .LBB0_3
# %bb.1: # %.lr.ph
leaq 16(%rsp), %rbx
movl $.L.str.18, %r14d
xorl %ebp, %ebp
.LBB0_2: # =>This Inner Loop Header: Depth=1
movq %rbx, %rdi
movl %ebp, %esi
callq hipGetDevicePropertiesR0600
movl $.L.str.1, %edi
movl %ebp, %esi
xorl %eax, %eax
callq printf
movl $.L.str.2, %edi
movq %rbx, %rsi
xorl %eax, %eax
callq printf
movq 312(%rsp), %rsi
movl $.L.str.3, %edi
xorl %eax, %eax
callq printf
movl 320(%rsp), %esi
movl $.L.str.4, %edi
xorl %eax, %eax
callq printf
movl 664(%rsp), %esi
movl $.L.str.5, %edi
xorl %eax, %eax
callq printf
movl 336(%rsp), %esi
movl $.L.str.6, %edi
xorl %eax, %eax
callq printf
movl 640(%rsp), %esi
movl $.L.str.7, %edi
xorl %eax, %eax
callq printf
movl 324(%rsp), %esi
movl $.L.str.8, %edi
xorl %eax, %eax
callq printf
movl 340(%rsp), %esi
movl 344(%rsp), %edx
movl 348(%rsp), %ecx
movl $.L.str.9, %edi
xorl %eax, %eax
callq printf
movl 352(%rsp), %esi
movl 356(%rsp), %edx
movl 360(%rsp), %ecx
movl $.L.str.10, %edi
xorl %eax, %eax
callq printf
movq 304(%rsp), %rsi
movl $.L.str.11, %edi
xorl %eax, %eax
callq printf
movq 368(%rsp), %rsi
movl $.L.str.12, %edi
xorl %eax, %eax
callq printf
movl 668(%rsp), %esi
movl $.L.str.13, %edi
xorl %eax, %eax
callq printf
movq 312(%rsp), %rsi
movl $.L.str.14, %edi
xorl %eax, %eax
callq printf
movq 656(%rsp), %rsi
movl $.L.str.15, %edi
xorl %eax, %eax
callq printf
cmpl $0, 416(%rsp)
movl $.L.str.17, %esi
cmoveq %r14, %rsi
movl $.L.str.16, %edi
xorl %eax, %eax
callq printf
cmpl $0, 596(%rsp)
movl $.L.str.17, %esi
cmoveq %r14, %rsi
movl $.L.str.19, %edi
xorl %eax, %eax
callq printf
movl 628(%rsp), %esi
movl $.L.str.20, %edi
xorl %eax, %eax
callq printf
movq 328(%rsp), %rsi
movl $.L.str.21, %edi
xorl %eax, %eax
callq printf
movl 376(%rsp), %esi
movl $.L.str.22, %edi
xorl %eax, %eax
callq printf
movl 380(%rsp), %esi
movl $.L.str.23, %edi
xorl %eax, %eax
callq printf
movl 364(%rsp), %esi
movl $.L.str.24, %edi
xorl %eax, %eax
callq printf
movl 404(%rsp), %esi
movl $.L.str.25, %edi
xorl %eax, %eax
callq printf
movl 400(%rsp), %esi
movl $.L.str.26, %edi
xorl %eax, %eax
callq printf
cmpl $0, 408(%rsp)
movl $.L.str.17, %esi
cmoveq %r14, %rsi
movl $.L.str.27, %edi
xorl %eax, %eax
callq printf
movl 592(%rsp), %esi
movl $.L.str.28, %edi
xorl %eax, %eax
callq printf
incl %ebp
cmpl 12(%rsp), %ebp
jl .LBB0_2
.LBB0_3: # %._crit_edge
xorl %eax, %eax
addq $1488, %rsp # imm = 0x5D0
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "\nNumber of Devices: %d\n"
.size .L.str, 24
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "\n ---Device %d Information---\n"
.size .L.str.1, 31
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Name: %s\n"
.size .L.str.2, 10
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Shared Mem Per Block: %lu\n"
.size .L.str.3, 27
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Registers Per Block: %d\n"
.size .L.str.4, 25
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "Registers Per MultiProcessor: %d\n"
.size .L.str.5, 34
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "Max Threads per Block: %d\n"
.size .L.str.6, 27
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "Max Threads per MultiProcessor: %d\n\n"
.size .L.str.7, 37
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "Warp Size: %d\n"
.size .L.str.8, 15
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "Max thread dimensions:(%d, %d, %d)\n"
.size .L.str.9, 36
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "Max grid dimensions:(%d, %d, %d)\n\n"
.size .L.str.10, 35
.type .L.str.11,@object # @.str.11
.L.str.11:
.asciz "Total Global Mem: %lu\n"
.size .L.str.11, 23
.type .L.str.12,@object # @.str.12
.L.str.12:
.asciz "Total Constant Memory: %lu\n"
.size .L.str.12, 28
.type .L.str.13,@object # @.str.13
.L.str.13:
.asciz "Total Managed Memory: %d\n"
.size .L.str.13, 26
.type .L.str.14,@object # @.str.14
.L.str.14:
.asciz "Shared Memory Per Block: %lu\n"
.size .L.str.14, 30
.type .L.str.15,@object # @.str.15
.L.str.15:
.asciz "Shared Memory Per MultiProcessor: %lu\n"
.size .L.str.15, 39
.type .L.str.16,@object # @.str.16
.L.str.16:
.asciz "Device can Map Host Memory: %s\n"
.size .L.str.16, 32
.type .L.str.17,@object # @.str.17
.L.str.17:
.asciz "Enabled"
.size .L.str.17, 8
.type .L.str.18,@object # @.str.18
.L.str.18:
.asciz "Disabled"
.size .L.str.18, 9
.type .L.str.19,@object # @.str.19
.L.str.19:
.asciz "Error Correcting code Mem: %s\n"
.size .L.str.19, 31
.type .L.str.20,@object # @.str.20
.L.str.20:
.asciz "Memory Bus Width: %d\n"
.size .L.str.20, 22
.type .L.str.21,@object # @.str.21
.L.str.21:
.asciz "Memory Pitch: %lu\n\n"
.size .L.str.21, 20
.type .L.str.22,@object # @.str.22
.L.str.22:
.asciz "Major Compute Capability: %d\n"
.size .L.str.22, 30
.type .L.str.23,@object # @.str.23
.L.str.23:
.asciz "Minor Compute Capability: %d\n"
.size .L.str.23, 30
.type .L.str.24,@object # @.str.24
.L.str.24:
.asciz "ClockRate: %d\n"
.size .L.str.24, 15
.type .L.str.25,@object # @.str.25
.L.str.25:
.asciz "MultiProcessor Count: %d\n"
.size .L.str.25, 26
.type .L.str.26,@object # @.str.26
.L.str.26:
.asciz "Device Overlap: %d\n"
.size .L.str.26, 20
.type .L.str.27,@object # @.str.27
.L.str.27:
.asciz "Kernel Execution Timeout: %s\n"
.size .L.str.27, 30
.type .L.str.28,@object # @.str.28
.L.str.28:
.asciz "Concurrent Kernels: %d\n"
.size .L.str.28, 24
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
```
| 3,676 | 3,302 |
100 |
Convert the following CUDA device assembly code to AMD device assembly:
```cudaasm
code for sm_80
```
|
```amdasm
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object ; @__hip_cuid_
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0 ; 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
```
| 24 | 306 |
101 |
Convert the following CUDA host assembly code to AMD host assembly:
```cudaasm
.file "tmpxft_000cc553_00000000-6_rcp_fused_nchw_8.cudafe1.cpp"
.text
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
```
|
```amdasm
.text
.file "rcp_fused_nchw_8.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
```
| 752 | 190 |
104 |
Convert the following CUDA device assembly code to AMD device assembly:
```cudaasm
code for sm_80
Function : _Z9skalarProPfS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ;
S2R R7, SR_CTAID.X ;
ULDC.64 UR6, c[0x0][0x118] ;
BSSY B0, 0x150 ;
HFMA2.MMA R6, -RZ, RZ, 0, 0 ;
S2R R8, SR_TID.X ;
IMAD R0, R7, c[0x0][0x0], R8 ;
ISETP.GT.AND P0, PT, R0, 0x7ffff, PT ;
@P0 BRA 0x140 ;
IMAD.MOV.U32 R6, RZ, RZ, RZ ;
MOV R5, 0x4 ;
IMAD.WIDE R2, R0, R5, c[0x0][0x160] ;
IMAD.WIDE R4, R0, R5, c[0x0][0x168] ;
LDG.E R2, [R2.64] ;
LDG.E R5, [R4.64] ;
IMAD.MOV.U32 R9, RZ, RZ, c[0x0][0x0] ;
IMAD R0, R9, c[0x0][0xc], R0 ;
ISETP.GE.AND P0, PT, R0, 0x80000, PT ;
FFMA R6, R5, R2, R6 ;
@!P0 BRA 0xa0 ;
BSYNC B0 ;
ULDC UR4, c[0x0][0x0] ;
STS [R8.X4], R6 ;
USHF.R.U32.HI UR4, URZ, 0x1, UR4 ;
BAR.SYNC.DEFER_BLOCKING 0x0 ;
ISETP.NE.AND P0, PT, R8, RZ, PT ;
ISETP.NE.AND P1, PT, RZ, UR4, PT ;
@!P1 BRA 0x2a0 ;
SHF.L.U32 R0, R8, 0x2, RZ ;
IMAD.U32 R3, RZ, RZ, UR4 ;
ISETP.GE.AND P1, PT, R8, R3, PT ;
@!P1 LEA R2, R3.reuse, R0, 0x2 ;
@!P1 LDS R4, [R8.X4] ;
@!P1 LDS R5, [R2] ;
@!P1 FADD R4, R4, R5 ;
IADD3 R5, R3.reuse, 0x1, RZ ;
LEA.HI R3, R3, R3, RZ, 0x1 ;
@!P1 STS [R8.X4], R4 ;
BAR.SYNC.DEFER_BLOCKING 0x0 ;
ISETP.GT.U32.AND P1, PT, R5, 0x2, PT ;
SHF.R.S32.HI R3, RZ, 0x1, R3 ;
@P1 BRA 0x1e0 ;
@P0 EXIT ;
LDS R5, [RZ] ;
IMAD.MOV.U32 R2, RZ, RZ, 0x4 ;
IMAD.WIDE.U32 R2, R7, R2, c[0x0][0x170] ;
STG.E [R2.64], R5 ;
EXIT ;
BRA 0x300;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
```
|
```amdasm
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9skalarProPfS_S_ ; -- Begin function _Z9skalarProPfS_S_
.globl _Z9skalarProPfS_S_
.p2align 8
.type _Z9skalarProPfS_S_,@function
_Z9skalarProPfS_S_: ; @_Z9skalarProPfS_S_
; %bb.0:
s_clause 0x2
s_load_b32 s3, s[0:1], 0x24
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[8:9], s[0:1], 0x10
s_add_u32 s0, s0, 24
s_mov_b32 s2, s15
s_addc_u32 s1, s1, 0
v_mov_b32_e32 v3, 0
s_mov_b32 s10, exec_lo
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s2, s3, v[0:1]
v_cmpx_gt_i32_e32 0x80000, v1
s_cbranch_execz .LBB0_4
; %bb.1: ; %.lr.ph
s_load_b32 s1, s[0:1], 0x0
v_mov_b32_e32 v3, 0
s_mov_b32 s0, 0
s_waitcnt lgkmcnt(0)
s_mul_i32 s1, s1, s3
.LBB0_2: ; =>This Inner Loop Header: Depth=1
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[4:5], 2, v[1:2]
v_add_nc_u32_e32 v1, s1, v1
v_add_co_u32 v6, vcc_lo, s4, v4
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v7, vcc_lo, s5, v5, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v5, vcc_lo
v_cmp_lt_i32_e32 vcc_lo, 0x7ffff, v1
global_load_b32 v2, v[6:7], off
global_load_b32 v4, v[4:5], off
s_or_b32 s0, vcc_lo, s0
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v3, v2, v4
s_and_not1_b32 exec_lo, exec_lo, s0
s_cbranch_execnz .LBB0_2
; %bb.3: ; %Flow40
s_or_b32 exec_lo, exec_lo, s0
.LBB0_4: ; %Flow41
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s10
v_lshlrev_b32_e32 v1, 2, v0
s_cmp_lt_u32 s3, 2
ds_store_b32 v1, v3
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB0_8
.LBB0_5: ; %.lr.ph29
; =>This Inner Loop Header: Depth=1
s_lshr_b32 s0, s3, 1
s_mov_b32 s1, exec_lo
v_cmpx_gt_u32_e64 s0, v0
s_cbranch_execz .LBB0_7
; %bb.6: ; in Loop: Header=BB0_5 Depth=1
v_lshl_add_u32 v2, s0, 2, v1
ds_load_b32 v2, v2
ds_load_b32 v3, v1
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v2, v2, v3
ds_store_b32 v1, v2
.LBB0_7: ; in Loop: Header=BB0_5 Depth=1
s_or_b32 exec_lo, exec_lo, s1
s_cmp_gt_u32 s3, 3
s_mov_b32 s3, s0
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB0_5
.LBB0_8: ; %._crit_edge30
s_mov_b32 s3, 0
s_mov_b32 s0, exec_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB0_10
; %bb.9:
v_mov_b32_e32 v0, 0
s_lshl_b64 s[0:1], s[2:3], 2
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s0, s8, s0
s_addc_u32 s1, s9, s1
ds_load_b32 v1, v0
s_waitcnt lgkmcnt(0)
global_store_b32 v0, v1, s[0:1]
.LBB0_10:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9skalarProPfS_S_
.amdhsa_group_segment_fixed_size 4096
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9skalarProPfS_S_, .Lfunc_end0-_Z9skalarProPfS_S_
; -- End function
.section .AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 408
; NumSgprs: 18
; NumVgprs: 8
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 4096 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 8
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object ; @__hip_cuid_
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0 ; 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 4096
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9skalarProPfS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z9skalarProPfS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
```
| 914 | 3,313 |
105 |
Convert the following CUDA host assembly code to AMD host assembly:
```cudaasm
.file "tmpxft_00040088_00000000-6_skalarPro.cudafe1.cpp"
.text
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z32__device_stub__Z9skalarProPfS_S_PfS_S_
.type _Z32__device_stub__Z9skalarProPfS_S_PfS_S_, @function
_Z32__device_stub__Z9skalarProPfS_S_PfS_S_:
.LFB2082:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9skalarProPfS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z32__device_stub__Z9skalarProPfS_S_PfS_S_, .-_Z32__device_stub__Z9skalarProPfS_S_PfS_S_
.globl _Z9skalarProPfS_S_
.type _Z9skalarProPfS_S_, @function
_Z9skalarProPfS_S_:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z9skalarProPfS_S_PfS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z9skalarProPfS_S_, .-_Z9skalarProPfS_S_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "Das Ergebnis vom Skalarprodukt: %f\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $72, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movslq blocksPerGrid(%rip), %r13
salq $2, %r13
movl $2097152, %edi
call malloc@PLT
movq %rax, %r12
movl $2097152, %edi
call malloc@PLT
movq %rax, %rbp
movq %r13, %rdi
call malloc@PLT
movq %rax, %rbx
movl $1, %eax
movl $524289, %ecx
.L12:
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movss %xmm0, -4(%r12,%rax,4)
movl %ecx, %edx
subl %eax, %edx
pxor %xmm0, %xmm0
cvtsi2ssl %edx, %xmm0
movss %xmm0, -4(%rbp,%rax,4)
addq $1, %rax
cmpq $524289, %rax
jne .L12
leaq 8(%rsp), %rdi
movl $2097152, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $2097152, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movq %r13, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movl $2097152, %edx
movq %r12, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $2097152, %edx
movq %rbp, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $1024, 44(%rsp)
movl $1, 48(%rsp)
movl blocksPerGrid(%rip), %eax
movl %eax, 32(%rsp)
movl $1, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L26
.L13:
movl $2, %ecx
movq %r13, %rdx
movq 24(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
movl blocksPerGrid(%rip), %edi
movl %edi, %eax
shrl $31, %eax
addl %edi, %eax
sarl %eax
movl %eax, %ecx
movslq %edi, %rsi
jne .L14
.L15:
pxor %xmm0, %xmm0
cvtss2sd (%rbx), %xmm0
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq %r12, %rdi
call free@PLT
movq %rbp, %rdi
call free@PLT
movq %rbx, %rdi
call free@PLT
call cudaThreadExit@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L27
movl $0, %eax
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L26:
.cfi_restore_state
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z32__device_stub__Z9skalarProPfS_S_PfS_S_
jmp .L13
.L16:
addq $1, %rax
cmpq %rax, %rsi
je .L19
.L17:
cmpl %eax, %ecx
jle .L16
leal (%rcx,%rax), %edx
movslq %edx, %rdx
movss (%rbx,%rax,4), %xmm0
addss (%rbx,%rdx,4), %xmm0
movss %xmm0, (%rbx,%rax,4)
jmp .L16
.L19:
movl %ecx, %eax
shrl $31, %eax
addl %ecx, %eax
sarl %eax
movl %eax, %ecx
je .L15
.L14:
movl $0, %eax
testl %edi, %edi
jg .L17
jmp .L19
.L27:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "_Z9skalarProPfS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z9skalarProPfS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl blocksPerGrid
.data
.align 4
.type blocksPerGrid, @object
.size blocksPerGrid, 4
blocksPerGrid:
.long 512
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
```
|
```amdasm
.text
.file "skalarPro.hip"
.globl _Z24__device_stub__skalarProPfS_S_ # -- Begin function _Z24__device_stub__skalarProPfS_S_
.type _Z24__device_stub__skalarProPfS_S_,@function
_Z24__device_stub__skalarProPfS_S_: # @_Z24__device_stub__skalarProPfS_S_
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $112, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 40(%rsp), %rax
movq %rdi, (%rax)
leaq 32(%rsp), %rcx
movq %rsi, (%rcx)
leaq 24(%rsp), %rsi
movq %rdx, (%rsi)
leaq 80(%rsp), %rbx
movq %rax, (%rbx)
movq %rcx, 8(%rbx)
movq %rsi, 16(%rbx)
leaq 64(%rsp), %r14
leaq 48(%rsp), %r15
leaq 16(%rsp), %r12
leaq 8(%rsp), %r13
movq %r14, %rdi
movq %r15, %rsi
movq %r12, %rdx
movq %r13, %rcx
callq __hipPopCallConfiguration
movq (%r14), %rsi
movl 8(%r14), %edx
movq (%r15), %rcx
movl 8(%r15), %r8d
movl $_Z9skalarProPfS_S_, %edi
movq %rbx, %r9
pushq (%r13)
.cfi_adjust_cfa_offset 8
pushq (%r12)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $128, %rsp
.cfi_adjust_cfa_offset -128
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z24__device_stub__skalarProPfS_S_, .Lfunc_end0-_Z24__device_stub__skalarProPfS_S_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $24, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movslq blocksPerGrid(%rip), %r12
shlq $2, %r12
movl $2097152, %edi # imm = 0x200000
callq malloc
movq %rax, %rbx
movl $2097152, %edi # imm = 0x200000
callq malloc
movq %rax, %r14
movq %r12, %rdi
callq malloc
movq %rax, %r15
movl $524288, %eax # imm = 0x80000
xorl %ecx, %ecx
.LBB1_1: # =>This Inner Loop Header: Depth=1
leaq 1(%rcx), %rdx
xorps %xmm0, %xmm0
cvtsi2ss %edx, %xmm0
xorps %xmm1, %xmm1
cvtsi2ss %eax, %xmm1
movss %xmm0, (%rbx,%rcx,4)
movss %xmm1, (%r14,%rcx,4)
movq %rdx, %rcx
decq %rax
jne .LBB1_1
# %bb.2:
leaq 16(%rsp), %r13
movl $2097152, %esi # imm = 0x200000
movq %r13, %rdi
callq hipMalloc
leaq 8(%rsp), %rbp
movl $2097152, %esi # imm = 0x200000
movq %rbp, %rdi
callq hipMalloc
movq %rsp, %rdi
movq %r12, %rsi
callq hipMalloc
movq (%r13), %rdi
movl $2097152, %edx # imm = 0x200000
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq (%rbp), %rdi
movl $2097152, %edx # imm = 0x200000
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movl blocksPerGrid(%rip), %edi
btsq $32, %rdi
movabsq $4294967296, %rdx # imm = 0x100000000
orq $1024, %rdx # imm = 0x400
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq 16(%rsp), %rdi
movq 8(%rsp), %rsi
movq (%rsp), %rdx
callq _Z24__device_stub__skalarProPfS_S_
.LBB1_4:
movq (%rsp), %rsi
movq %r15, %rdi
movq %r12, %rdx
movl $2, %ecx
callq hipMemcpy
movl blocksPerGrid(%rip), %eax
leal 1(%rax), %ecx
cmpl $3, %ecx
jb .LBB1_12
# %bb.5:
movl %eax, %ecx
.LBB1_7: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB1_9 Depth 2
movl %ecx, %edx
shrl $31, %edx
addl %ecx, %edx
movl %edx, %ecx
sarl %ecx
testl %eax, %eax
jle .LBB1_6
# %bb.8: # %.lr.ph.preheader
# in Loop: Header=BB1_7 Depth=1
movslq %ecx, %rdx
leaq (%r15,%rdx,4), %rsi
xorl %edi, %edi
.LBB1_9: # %.lr.ph
# Parent Loop BB1_7 Depth=1
# => This Inner Loop Header: Depth=2
cmpq %rdx, %rdi
jge .LBB1_11
# %bb.10: # in Loop: Header=BB1_9 Depth=2
movss (%rsi,%rdi,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
addss (%r15,%rdi,4), %xmm0
movss %xmm0, (%r15,%rdi,4)
.LBB1_11: # in Loop: Header=BB1_9 Depth=2
incq %rdi
cmpq %rdi, %rax
jne .LBB1_9
.LBB1_6: # %.loopexit
# in Loop: Header=BB1_7 Depth=1
leal 1(%rcx), %edx
cmpl $3, %edx
jae .LBB1_7
.LBB1_12: # %._crit_edge
xorps %xmm0, %xmm0
cvtss2sd (%r15), %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipFree
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
callq hipDeviceReset
xorl %eax, %eax
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, %rdi
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9skalarProPfS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type blocksPerGrid,@object # @blocksPerGrid
.data
.globl blocksPerGrid
.p2align 2, 0x0
blocksPerGrid:
.long 512 # 0x200
.size blocksPerGrid, 4
.type _Z9skalarProPfS_S_,@object # @_Z9skalarProPfS_S_
.section .rodata,"a",@progbits
.globl _Z9skalarProPfS_S_
.p2align 3, 0x0
_Z9skalarProPfS_S_:
.quad _Z24__device_stub__skalarProPfS_S_
.size _Z9skalarProPfS_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Das Ergebnis vom Skalarprodukt: %f\n"
.size .L.str, 36
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z9skalarProPfS_S_"
.size .L__unnamed_1, 19
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__skalarProPfS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9skalarProPfS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
```
| 3,589 | 4,092 |
106 |
Convert the following CUDA device assembly code to AMD device assembly:
```cudaasm
code for sm_80
```
|
```amdasm
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object ; @__hip_cuid_
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0 ; 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
```
| 24 | 306 |
107 |
Convert the following CUDA host assembly code to AMD host assembly:
```cudaasm
.file "tmpxft_001aa8a5_00000000-6_getInfo.cudafe1.cpp"
.text
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2684:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2684:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "problem getting device count = %s\n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "number of GPU devices: %d\n\n"
.section .rodata.str1.8
.align 8
.LC2:
.string "*********Num CPU cores on this machine: %d\n*********"
.align 8
.LC3:
.string "************ GPU Device: %d ************\n\n"
.align 8
.LC4:
.string "problem getting device properties = %s\n"
.section .rodata.str1.1
.LC5:
.string "\tName: %s\n"
.LC6:
.string "\tTotal global mem: %ld\n"
.LC7:
.string "\tTotal constant Mem: %ld\n"
.LC8:
.string "\tMultiprocessor count: %d\n"
.section .rodata.str1.8
.align 8
.LC9:
.string "\tShared mem per processor: %ld\n"
.section .rodata.str1.1
.LC10:
.string "\tMax threads per block: %d\n"
.section .rodata.str1.8
.align 8
.LC11:
.string "\tMax block dimensions: (%d, %d, %d)\n"
.align 8
.LC12:
.string "\tMax grid dimensions: (%d, %d, %d)\n"
.section .rodata.str1.1
.LC13:
.string "\n"
.text
.globl main
.type main, @function
main:
.LFB2681:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $1056, %rsp
.cfi_def_cfa_offset 1104
movq %fs:40, %rax
movq %rax, 1048(%rsp)
xorl %eax, %eax
call _ZNSt6thread20hardware_concurrencyEv@PLT
movl %eax, %ebx
call cudaDeviceReset@PLT
leaq 12(%rsp), %rdi
call cudaGetDeviceCount@PLT
testl %eax, %eax
jne .L12
movl 12(%rsp), %edx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %ebx, %edx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
cmpl $0, 12(%rsp)
jle .L9
movl $0, %ebx
leaq .LC3(%rip), %rbp
leaq .LC5(%rip), %r14
leaq .LC6(%rip), %r13
leaq .LC7(%rip), %r12
.L7:
movl %ebx, %edx
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 16(%rsp), %rdi
movl %ebx, %esi
call cudaGetDeviceProperties_v2@PLT
testl %eax, %eax
jne .L13
leaq 16(%rsp), %rdx
movq %r14, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 304(%rsp), %rdx
movq %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 368(%rsp), %rdx
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 404(%rsp), %edx
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 312(%rsp), %rdx
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 336(%rsp), %edx
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 348(%rsp), %r8d
movl 344(%rsp), %ecx
movl 340(%rsp), %edx
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 360(%rsp), %r8d
movl 356(%rsp), %ecx
movl 352(%rsp), %edx
leaq .LC12(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC13(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $1, %ebx
cmpl %ebx, 12(%rsp)
jg .L7
movl $0, %eax
jmp .L3
.L12:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %eax
.L3:
movq 1048(%rsp), %rdx
subq %fs:40, %rdx
jne .L14
addq $1056, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L13:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %eax
jmp .L3
.L9:
movl $0, %eax
jmp .L3
.L14:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2681:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2707:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2707:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
```
|
```amdasm
.text
.file "getInfo.hip"
.globl main # -- Begin function main
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $1488, %rsp # imm = 0x5D0
.cfi_def_cfa_offset 1520
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %rbp, -16
callq _ZNSt6thread20hardware_concurrencyEv
movl %eax, %ebx
callq hipDeviceReset
leaq 12(%rsp), %rdi
callq hipGetDeviceCount
testl %eax, %eax
je .LBB0_2
# %bb.1:
movl $.L.str, %ebx
.LBB0_6: # %.loopexit.sink.split
movl %eax, %edi
callq hipGetErrorString
movq %rbx, %rdi
movq %rax, %rsi
xorl %eax, %eax
callq printf
movl $1, %ebp
.LBB0_7: # %.loopexit
movl %ebp, %eax
addq $1488, %rsp # imm = 0x5D0
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB0_2:
.cfi_def_cfa_offset 1520
movl 12(%rsp), %esi
xorl %ebp, %ebp
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
movl $.L.str.2, %edi
movl %ebx, %esi
xorl %eax, %eax
callq printf
cmpl $0, 12(%rsp)
jle .LBB0_7
# %bb.3: # %.lr.ph
leaq 16(%rsp), %rbx
xorl %r14d, %r14d
xorl %ebp, %ebp
.LBB0_4: # =>This Inner Loop Header: Depth=1
movl $.L.str.3, %edi
movl %r14d, %esi
xorl %eax, %eax
callq printf
movq %rbx, %rdi
movl %r14d, %esi
callq hipGetDevicePropertiesR0600
testl %eax, %eax
jne .LBB0_5
# %bb.8: # in Loop: Header=BB0_4 Depth=1
movl $.L.str.5, %edi
movq %rbx, %rsi
xorl %eax, %eax
callq printf
movq 304(%rsp), %rsi
movl $.L.str.6, %edi
xorl %eax, %eax
callq printf
movq 368(%rsp), %rsi
movl $.L.str.7, %edi
xorl %eax, %eax
callq printf
movl 404(%rsp), %esi
movl $.L.str.8, %edi
xorl %eax, %eax
callq printf
movq 312(%rsp), %rsi
movl $.L.str.9, %edi
xorl %eax, %eax
callq printf
movl 336(%rsp), %esi
movl $.L.str.10, %edi
xorl %eax, %eax
callq printf
movl 340(%rsp), %esi
movl 344(%rsp), %edx
movl 348(%rsp), %ecx
movl $.L.str.11, %edi
xorl %eax, %eax
callq printf
movl 352(%rsp), %esi
movl 356(%rsp), %edx
movl 360(%rsp), %ecx
movl $.L.str.12, %edi
xorl %eax, %eax
callq printf
movl $10, %edi
callq putchar@PLT
incl %r14d
cmpl 12(%rsp), %r14d
jl .LBB0_4
jmp .LBB0_7
.LBB0_5:
movl $.L.str.4, %ebx
jmp .LBB0_6
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "problem getting device count = %s\n"
.size .L.str, 35
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "number of GPU devices: %d\n\n"
.size .L.str.1, 28
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "*********Num CPU cores on this machine: %d\n*********"
.size .L.str.2, 53
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "************ GPU Device: %d ************\n\n"
.size .L.str.3, 43
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "problem getting device properties = %s\n"
.size .L.str.4, 40
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "\tName: %s\n"
.size .L.str.5, 11
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "\tTotal global mem: %ld\n"
.size .L.str.6, 24
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "\tTotal constant Mem: %ld\n"
.size .L.str.7, 26
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "\tMultiprocessor count: %d\n"
.size .L.str.8, 27
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "\tShared mem per processor: %ld\n"
.size .L.str.9, 32
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "\tMax threads per block: %d\n"
.size .L.str.10, 28
.type .L.str.11,@object # @.str.11
.L.str.11:
.asciz "\tMax block dimensions: (%d, %d, %d)\n"
.size .L.str.11, 37
.type .L.str.12,@object # @.str.12
.L.str.12:
.asciz "\tMax grid dimensions: (%d, %d, %d)\n"
.size .L.str.12, 36
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
```
| 2,699 | 2,070 |
108 |
Convert the following CUDA device assembly code to AMD device assembly:
```cudaasm
code for sm_80
Function : _Z9dev_add_nPiS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
MOV R1, c[0x0][0x28] ;
S2R R6, SR_CTAID.X ;
ISETP.GE.AND P0, PT, R6, c[0x0][0x178], PT ;
@P0 EXIT ;
HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ;
ULDC.64 UR4, c[0x0][0x118] ;
IMAD.WIDE R4, R6, R7, c[0x0][0x168] ;
IMAD.WIDE R2, R6.reuse, R7.reuse, c[0x0][0x160] ;
LDG.E R4, [R4.64] ;
LDG.E R3, [R2.64] ;
IMAD.WIDE R6, R6, R7, c[0x0][0x170] ;
IADD3 R9, R4, R3, RZ ;
STG.E [R6.64], R9 ;
EXIT ;
BRA 0xe0;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
Function : _Z7dev_addPiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
MOV R1, c[0x0][0x28] ;
MOV R2, c[0x4][0x0] ;
ULDC.64 UR4, c[0x0][0x118] ;
MOV R3, c[0x4][0x4] ;
LDG.E R2, [R2.64] ;
S2R R7, SR_CTAID.X ;
ISETP.GE.AND P0, PT, R7, R2, PT ;
@P0 EXIT ;
HFMA2.MMA R6, -RZ, RZ, 0, 2.384185791015625e-07 ;
IMAD.WIDE R4, R7, R6, c[0x0][0x168] ;
IMAD.WIDE R2, R7.reuse, R6.reuse, c[0x0][0x160] ;
LDG.E R4, [R4.64] ;
LDG.E R3, [R2.64] ;
IMAD.WIDE R6, R7, R6, c[0x0][0x170] ;
IADD3 R9, R4, R3, RZ ;
STG.E [R6.64], R9 ;
EXIT ;
BRA 0x110;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
Function : _Z5set_Ni
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ;
IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x160] ;
MOV R2, c[0x4][0x0] ;
ULDC.64 UR4, c[0x0][0x118] ;
MOV R3, c[0x4][0x4] ;
STG.E [R2.64], R5 ;
EXIT ;
BRA 0x70;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
```
|
```amdasm
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z5set_Ni ; -- Begin function _Z5set_Ni
.globl _Z5set_Ni
.p2align 8
.type _Z5set_Ni,@function
_Z5set_Ni: ; @_Z5set_Ni
; %bb.0:
s_load_b32 s2, s[0:1], 0x0
v_mov_b32_e32 v0, 0
s_getpc_b64 s[0:1]
s_add_u32 s0, s0, N@rel32@lo+4
s_addc_u32 s1, s1, N@rel32@hi+12
s_waitcnt lgkmcnt(0)
v_mov_b32_e32 v1, s2
global_store_b32 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z5set_Ni
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 4
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 3
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z5set_Ni, .Lfunc_end0-_Z5set_Ni
; -- End function
.section .AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 60
; NumSgprs: 3
; NumVgprs: 2
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 0
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 3
; NumVGPRsForWavesPerEU: 2
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
.text
.protected _Z7dev_addPiS_S_ ; -- Begin function _Z7dev_addPiS_S_
.globl _Z7dev_addPiS_S_
.p2align 8
.type _Z7dev_addPiS_S_,@function
_Z7dev_addPiS_S_: ; @_Z7dev_addPiS_S_
; %bb.0:
s_getpc_b64 s[4:5]
s_add_u32 s4, s4, N@rel32@lo+4
s_addc_u32 s5, s5, N@rel32@hi+12
s_load_b32 s3, s[4:5], 0x0
s_waitcnt lgkmcnt(0)
s_cmp_ge_i32 s15, s3
s_cbranch_scc1 .LBB1_2
; %bb.1:
s_clause 0x1
s_load_b64 s[8:9], s[0:1], 0x10
s_load_b128 s[4:7], s[0:1], 0x0
s_mov_b32 s2, s15
s_ashr_i32 s3, s15, 31
s_delay_alu instid0(SALU_CYCLE_1)
s_lshl_b64 s[0:1], s[2:3], 2
s_waitcnt lgkmcnt(0)
s_add_u32 s2, s8, s0
s_addc_u32 s3, s9, s1
s_add_u32 s6, s6, s0
s_addc_u32 s7, s7, s1
s_add_u32 s0, s4, s0
s_addc_u32 s1, s5, s1
s_load_b32 s0, s[0:1], 0x0
s_load_b32 s1, s[6:7], 0x0
s_waitcnt lgkmcnt(0)
s_add_i32 s0, s1, s0
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s0
global_store_b32 v0, v1, s[2:3]
.LBB1_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z7dev_addPiS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 16
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z7dev_addPiS_S_, .Lfunc_end1-_Z7dev_addPiS_S_
; -- End function
.section .AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 160
; NumSgprs: 16
; NumVgprs: 2
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 1
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 16
; NumVGPRsForWavesPerEU: 2
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
.text
.protected _Z9dev_add_nPiS_S_i ; -- Begin function _Z9dev_add_nPiS_S_i
.globl _Z9dev_add_nPiS_S_i
.p2align 8
.type _Z9dev_add_nPiS_S_i,@function
_Z9dev_add_nPiS_S_i: ; @_Z9dev_add_nPiS_S_i
; %bb.0:
s_load_b32 s3, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_cmp_ge_i32 s15, s3
s_cbranch_scc1 .LBB2_2
; %bb.1:
s_clause 0x1
s_load_b64 s[8:9], s[0:1], 0x10
s_load_b128 s[4:7], s[0:1], 0x0
s_mov_b32 s2, s15
s_ashr_i32 s3, s15, 31
s_delay_alu instid0(SALU_CYCLE_1)
s_lshl_b64 s[0:1], s[2:3], 2
s_waitcnt lgkmcnt(0)
s_add_u32 s2, s8, s0
s_addc_u32 s3, s9, s1
s_add_u32 s6, s6, s0
s_addc_u32 s7, s7, s1
s_add_u32 s0, s4, s0
s_addc_u32 s1, s5, s1
s_load_b32 s0, s[0:1], 0x0
s_load_b32 s1, s[6:7], 0x0
s_waitcnt lgkmcnt(0)
s_add_i32 s0, s1, s0
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s0
global_store_b32 v0, v1, s[2:3]
.LBB2_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9dev_add_nPiS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 28
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 16
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end2:
.size _Z9dev_add_nPiS_S_i, .Lfunc_end2-_Z9dev_add_nPiS_S_i
; -- End function
.section .AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 140
; NumSgprs: 16
; NumVgprs: 2
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 1
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 16
; NumVGPRsForWavesPerEU: 2
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.protected N ; @N
.type N,@object
.section .bss,"aw",@nobits
.globl N
.p2align 2, 0x0
N:
.long 0 ; 0x0
.size N, 4
.type __hip_cuid_,@object ; @__hip_cuid_
.globl __hip_cuid_
__hip_cuid_:
.byte 0 ; 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym N
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 4
.kernarg_segment_size: 4
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z5set_Ni
.private_segment_fixed_size: 0
.sgpr_count: 3
.sgpr_spill_count: 0
.symbol: _Z5set_Ni.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z7dev_addPiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 16
.sgpr_spill_count: 0
.symbol: _Z7dev_addPiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 28
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9dev_add_nPiS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 16
.sgpr_spill_count: 0
.symbol: _Z9dev_add_nPiS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
```
| 929 | 5,234 |
109 |
Convert the following CUDA host assembly code to AMD host assembly:
```cudaasm
.file "tmpxft_00197093_00000000-6_add.cudafe1.cpp"
.text
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2031:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2031:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z23__device_stub__Z5set_Nii
.type _Z23__device_stub__Z5set_Nii, @function
_Z23__device_stub__Z5set_Nii:
.LFB2053:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movl %edi, 12(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z5set_Ni(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2053:
.size _Z23__device_stub__Z5set_Nii, .-_Z23__device_stub__Z5set_Nii
.globl _Z5set_Ni
.type _Z5set_Ni, @function
_Z5set_Ni:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z23__device_stub__Z5set_Nii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _Z5set_Ni, .-_Z5set_Ni
.globl _Z30__device_stub__Z7dev_addPiS_S_PiS_S_
.type _Z30__device_stub__Z7dev_addPiS_S_PiS_S_, @function
_Z30__device_stub__Z7dev_addPiS_S_PiS_S_:
.LFB2055:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z7dev_addPiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2055:
.size _Z30__device_stub__Z7dev_addPiS_S_PiS_S_, .-_Z30__device_stub__Z7dev_addPiS_S_PiS_S_
.globl _Z7dev_addPiS_S_
.type _Z7dev_addPiS_S_, @function
_Z7dev_addPiS_S_:
.LFB2056:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z7dev_addPiS_S_PiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2056:
.size _Z7dev_addPiS_S_, .-_Z7dev_addPiS_S_
.globl _Z3addPiS_S_i
.type _Z3addPiS_S_i, @function
_Z3addPiS_S_i:
.LFB2027:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $64, %rsp
.cfi_def_cfa_offset 112
movq %rdi, %r14
movq %rsi, %r13
movq %rdx, %r12
movl %ecx, %ebp
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L24
.L20:
movslq %ebp, %rbx
salq $2, %rbx
leaq 8(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %rbx, %rdx
movq %r14, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %rbx, %rdx
movq %r13, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl %ebp, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L25
.L21:
movl $2, %ecx
movq %rbx, %rdx
movq 24(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L26
addq $64, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L24:
.cfi_restore_state
movl %ebp, %edi
call _Z23__device_stub__Z5set_Nii
jmp .L20
.L25:
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z30__device_stub__Z7dev_addPiS_S_PiS_S_
jmp .L21
.L26:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2027:
.size _Z3addPiS_S_i, .-_Z3addPiS_S_i
.globl _Z33__device_stub__Z9dev_add_nPiS_S_iPiS_S_i
.type _Z33__device_stub__Z9dev_add_nPiS_S_iPiS_S_i, @function
_Z33__device_stub__Z9dev_add_nPiS_S_iPiS_S_i:
.LFB2057:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L31
.L27:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L32
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L31:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9dev_add_nPiS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L27
.L32:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size _Z33__device_stub__Z9dev_add_nPiS_S_iPiS_S_i, .-_Z33__device_stub__Z9dev_add_nPiS_S_iPiS_S_i
.globl _Z9dev_add_nPiS_S_i
.type _Z9dev_add_nPiS_S_i, @function
_Z9dev_add_nPiS_S_i:
.LFB2058:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z9dev_add_nPiS_S_iPiS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size _Z9dev_add_nPiS_S_i, .-_Z9dev_add_nPiS_S_i
.globl _Z5add_nPiS_S_i
.type _Z5add_nPiS_S_i, @function
_Z5add_nPiS_S_i:
.LFB2028:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $64, %rsp
.cfi_def_cfa_offset 112
movq %rdi, %r14
movq %rsi, %r13
movq %rdx, %r12
movl %ecx, %ebp
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movslq %ecx, %rbx
salq $2, %rbx
leaq 8(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %rbx, %rdx
movq %r14, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %rbx, %rdx
movq %r13, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl %ebp, 32(%rsp)
movl $1, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L39
.L36:
movl $2, %ecx
movq %rbx, %rdx
movq 24(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L40
addq $64, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L39:
.cfi_restore_state
movl %ebp, %ecx
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z33__device_stub__Z9dev_add_nPiS_S_iPiS_S_i
jmp .L36
.L40:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2028:
.size _Z5add_nPiS_S_i, .-_Z5add_nPiS_S_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z9dev_add_nPiS_S_i"
.LC1:
.string "_Z7dev_addPiS_S_"
.LC2:
.string "_Z5set_Ni"
.LC3:
.string "N"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2060:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z9dev_add_nPiS_S_i(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z7dev_addPiS_S_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z5set_Ni(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $4, %r9d
movl $0, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _ZL1N(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZL1N
.comm _ZL1N,4,4
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
```
|
```amdasm
.text
.file "add.hip"
.globl _Z20__device_stub__set_Ni # -- Begin function _Z20__device_stub__set_Ni
.type _Z20__device_stub__set_Ni,@function
_Z20__device_stub__set_Ni: # @_Z20__device_stub__set_Ni
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $80, %rsp
.cfi_def_cfa_offset 128
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 12(%rsp), %rax
movl %edi, (%rax)
leaq 16(%rsp), %rbx
movq %rax, (%rbx)
leaq 64(%rsp), %r14
leaq 48(%rsp), %r15
leaq 40(%rsp), %r12
leaq 32(%rsp), %r13
movq %r14, %rdi
movq %r15, %rsi
movq %r12, %rdx
movq %r13, %rcx
callq __hipPopCallConfiguration
movq (%r14), %rsi
movl 8(%r14), %edx
movq (%r15), %rcx
movl 8(%r15), %r8d
movl $_Z5set_Ni, %edi
movq %rbx, %r9
pushq (%r13)
.cfi_adjust_cfa_offset 8
pushq (%r12)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $96, %rsp
.cfi_adjust_cfa_offset -96
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z20__device_stub__set_Ni, .Lfunc_end0-_Z20__device_stub__set_Ni
.cfi_endproc
# -- End function
.globl _Z22__device_stub__dev_addPiS_S_ # -- Begin function _Z22__device_stub__dev_addPiS_S_
.type _Z22__device_stub__dev_addPiS_S_,@function
_Z22__device_stub__dev_addPiS_S_: # @_Z22__device_stub__dev_addPiS_S_
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $112, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 40(%rsp), %rax
movq %rdi, (%rax)
leaq 32(%rsp), %rcx
movq %rsi, (%rcx)
leaq 24(%rsp), %rsi
movq %rdx, (%rsi)
leaq 80(%rsp), %rbx
movq %rax, (%rbx)
movq %rcx, 8(%rbx)
movq %rsi, 16(%rbx)
leaq 64(%rsp), %r14
leaq 48(%rsp), %r15
leaq 16(%rsp), %r12
leaq 8(%rsp), %r13
movq %r14, %rdi
movq %r15, %rsi
movq %r12, %rdx
movq %r13, %rcx
callq __hipPopCallConfiguration
movq (%r14), %rsi
movl 8(%r14), %edx
movq (%r15), %rcx
movl 8(%r15), %r8d
movl $_Z7dev_addPiS_S_, %edi
movq %rbx, %r9
pushq (%r13)
.cfi_adjust_cfa_offset 8
pushq (%r12)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $128, %rsp
.cfi_adjust_cfa_offset -128
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z22__device_stub__dev_addPiS_S_, .Lfunc_end1-_Z22__device_stub__dev_addPiS_S_
.cfi_endproc
# -- End function
.globl _Z3addPiS_S_i # -- Begin function _Z3addPiS_S_i
.type _Z3addPiS_S_i,@function
_Z3addPiS_S_i: # @_Z3addPiS_S_i
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $40, %rsp
.cfi_def_cfa_offset 96
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %ecx, %ebp
movq %rdx, 32(%rsp) # 8-byte Spill
movq %rsi, 24(%rsp) # 8-byte Spill
movq %rdi, %r13
movabsq $4294967297, %r15 # imm = 0x100000001
movq %r15, %rdi
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_2
# %bb.1:
movl %ebp, %edi
callq _Z20__device_stub__set_Ni
.LBB2_2:
movslq %ebp, %r14
shlq $2, %r14
leaq 16(%rsp), %rbx
movq %rbx, %rdi
movq %r14, %rsi
callq hipMalloc
leaq 8(%rsp), %r12
movq %r12, %rdi
movq %r14, %rsi
callq hipMalloc
movq %rsp, %rdi
movq %r14, %rsi
callq hipMalloc
movq (%rbx), %rdi
movq %r13, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
movq (%r12), %rdi
movq 24(%rsp), %rsi # 8-byte Reload
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
movl %ebp, %eax
leaq (%r15,%rax), %rdi
decq %rdi
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_4
# %bb.3:
movq 16(%rsp), %rdi
movq 8(%rsp), %rsi
movq (%rsp), %rdx
callq _Z22__device_stub__dev_addPiS_S_
.LBB2_4:
movq (%rsp), %rsi
movq 32(%rsp), %rdi # 8-byte Reload
movq %r14, %rdx
movl $2, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipFree
addq $40, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size _Z3addPiS_S_i, .Lfunc_end2-_Z3addPiS_S_i
.cfi_endproc
# -- End function
.globl _Z24__device_stub__dev_add_nPiS_S_i # -- Begin function _Z24__device_stub__dev_add_nPiS_S_i
.type _Z24__device_stub__dev_add_nPiS_S_i,@function
_Z24__device_stub__dev_add_nPiS_S_i: # @_Z24__device_stub__dev_add_nPiS_S_i
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $112, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 40(%rsp), %rax
movq %rdi, (%rax)
leaq 32(%rsp), %rdi
movq %rsi, (%rdi)
leaq 24(%rsp), %rsi
movq %rdx, (%rsi)
leaq 4(%rsp), %rdx
movl %ecx, (%rdx)
leaq 80(%rsp), %rbx
movq %rax, (%rbx)
movq %rdi, 8(%rbx)
movq %rsi, 16(%rbx)
movq %rdx, 24(%rbx)
leaq 64(%rsp), %r14
leaq 48(%rsp), %r15
leaq 16(%rsp), %r12
leaq 8(%rsp), %r13
movq %r14, %rdi
movq %r15, %rsi
movq %r12, %rdx
movq %r13, %rcx
callq __hipPopCallConfiguration
movq (%r14), %rsi
movl 8(%r14), %edx
movq (%r15), %rcx
movl 8(%r15), %r8d
movl $_Z9dev_add_nPiS_S_i, %edi
movq %rbx, %r9
pushq (%r13)
.cfi_adjust_cfa_offset 8
pushq (%r12)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $128, %rsp
.cfi_adjust_cfa_offset -128
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size _Z24__device_stub__dev_add_nPiS_S_i, .Lfunc_end3-_Z24__device_stub__dev_add_nPiS_S_i
.cfi_endproc
# -- End function
.globl _Z5add_nPiS_S_i # -- Begin function _Z5add_nPiS_S_i
.type _Z5add_nPiS_S_i,@function
_Z5add_nPiS_S_i: # @_Z5add_nPiS_S_i
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $40, %rsp
.cfi_def_cfa_offset 96
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rdx, 32(%rsp) # 8-byte Spill
movq %rsi, %r15
movq %rdi, %r12
movl %ecx, 12(%rsp) # 4-byte Spill
movslq %ecx, %rbp
leaq (,%rbp,4), %r14
leaq 24(%rsp), %r13
movq %r13, %rdi
movq %r14, %rsi
callq hipMalloc
leaq 16(%rsp), %rbx
movq %rbx, %rdi
movq %r14, %rsi
callq hipMalloc
movq %rsp, %rdi
movq %r14, %rsi
callq hipMalloc
movq (%r13), %rdi
movq %r12, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
movq (%rbx), %rdi
movq %r15, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
movl %ebp, %edi
btsq $32, %rdi
movabsq $4294967296, %rdx # imm = 0x100000000
orq $1, %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_2
# %bb.1:
movq 24(%rsp), %rdi
movq 16(%rsp), %rsi
movq (%rsp), %rdx
movl 12(%rsp), %ecx # 4-byte Reload
callq _Z24__device_stub__dev_add_nPiS_S_i
.LBB4_2:
movq (%rsp), %rsi
movq 32(%rsp), %rdi # 8-byte Reload
movq %r14, %rdx
movl $2, %ecx
callq hipMemcpy
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipFree
addq $40, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end4:
.size _Z5add_nPiS_S_i, .Lfunc_end4-_Z5add_nPiS_S_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
movq __hip_gpubin_handle(%rip), %rbx
testq %rbx, %rbx
jne .LBB5_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, %rbx
movq %rax, __hip_gpubin_handle(%rip)
.LBB5_2:
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z5set_Ni, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7dev_addPiS_S_, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9dev_add_nPiS_S_i, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $0, 8(%rsp)
movl $0, (%rsp)
movl $N, %esi
movl $.L__unnamed_4, %edx
movl $.L__unnamed_4, %ecx
movl $4, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
callq __hipRegisterVar
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end5:
.size __hip_module_ctor, .Lfunc_end5-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB6_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB6_2:
retq
.Lfunc_end6:
.size __hip_module_dtor, .Lfunc_end6-__hip_module_dtor
.cfi_endproc
# -- End function
.type N,@object # @N
.local N
.comm N,4,4
.type _Z5set_Ni,@object # @_Z5set_Ni
.section .rodata,"a",@progbits
.globl _Z5set_Ni
.p2align 3, 0x0
_Z5set_Ni:
.quad _Z20__device_stub__set_Ni
.size _Z5set_Ni, 8
.type _Z7dev_addPiS_S_,@object # @_Z7dev_addPiS_S_
.globl _Z7dev_addPiS_S_
.p2align 3, 0x0
_Z7dev_addPiS_S_:
.quad _Z22__device_stub__dev_addPiS_S_
.size _Z7dev_addPiS_S_, 8
.type _Z9dev_add_nPiS_S_i,@object # @_Z9dev_add_nPiS_S_i
.globl _Z9dev_add_nPiS_S_i
.p2align 3, 0x0
_Z9dev_add_nPiS_S_i:
.quad _Z24__device_stub__dev_add_nPiS_S_i
.size _Z9dev_add_nPiS_S_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z5set_Ni"
.size .L__unnamed_1, 10
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z7dev_addPiS_S_"
.size .L__unnamed_2, 17
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z9dev_add_nPiS_S_i"
.size .L__unnamed_3, 20
.type .L__unnamed_4,@object # @3
.L__unnamed_4:
.asciz "N"
.size .L__unnamed_4, 2
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z20__device_stub__set_Ni
.addrsig_sym _Z22__device_stub__dev_addPiS_S_
.addrsig_sym _Z24__device_stub__dev_add_nPiS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym N
.addrsig_sym _Z5set_Ni
.addrsig_sym _Z7dev_addPiS_S_
.addrsig_sym _Z9dev_add_nPiS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
```
| 6,362 | 6,684 |
110 |
Convert the following CUDA device assembly code to AMD device assembly:
```cudaasm
code for sm_80
Function : _Z13cuComputeNormPfiiiS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
MOV R1, c[0x0][0x28] ;
S2R R12, SR_CTAID.X ;
S2R R5, SR_TID.X ;
IMAD R0, R12, c[0x0][0x0], R5 ;
ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x168], PT ;
@P0 EXIT ;
IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x170] ;
ULDC.64 UR4, c[0x0][0x118] ;
HFMA2.MMA R3, -RZ, RZ, 0, 0 ;
ISETP.GE.AND P0, PT, R2, 0x1, PT ;
@!P0 BRA 0x3a0 ;
IADD3 R3, R2.reuse, -0x1, RZ ;
LOP3.LUT R2, R2, 0x3, RZ, 0xc0, !PT ;
ISETP.GE.U32.AND P1, PT, R3, 0x3, PT ;
IMAD.MOV.U32 R3, RZ, RZ, RZ ;
ISETP.NE.AND P0, PT, R2, RZ, PT ;
MOV R13, RZ ;
@!P1 BRA 0x300 ;
IADD3 R3, R5, c[0x0][0x16c], RZ ;
IMAD.MOV.U32 R19, RZ, RZ, c[0x0][0x16c] ;
IADD3 R18, R2, -c[0x0][0x170], RZ ;
IMAD.MOV.U32 R13, RZ, RZ, RZ ;
MOV R16, R0 ;
IMAD R12, R12, c[0x0][0x0], R3 ;
HFMA2.MMA R3, -RZ, RZ, 0, 0 ;
IMAD R14, R19.reuse, 0x2, R0.reuse ;
IMAD R15, R19, 0x3, R0 ;
MOV R9, 0x4 ;
IMAD.WIDE.U32 R10, R16, R9, c[0x0][0x160] ;
IMAD.WIDE.U32 R6, R12, R9.reuse, c[0x0][0x160] ;
LDG.E R10, [R10.64] ;
IMAD.WIDE.U32 R4, R14, R9.reuse, c[0x0][0x160] ;
LDG.E R6, [R6.64] ;
IMAD.WIDE.U32 R8, R15, R9, c[0x0][0x160] ;
LDG.E R4, [R4.64] ;
LDG.E R8, [R8.64] ;
IADD3 R13, R13, 0x4, RZ ;
IMAD R12, R19.reuse, 0x4, R12 ;
LEA R16, R19.reuse, R16, 0x2 ;
IMAD R15, R19.reuse, 0x4, R15 ;
LEA R14, R19, R14, 0x2 ;
IMAD.IADD R17, R18, 0x1, R13 ;
ISETP.NE.AND P1, PT, R17, RZ, PT ;
FFMA R3, R10, R10, R3 ;
FFMA R3, R6, R6, R3 ;
FFMA R3, R4, R4, R3 ;
FFMA R3, R8, R8, R3 ;
@P1 BRA 0x1b0 ;
@!P0 BRA 0x3a0 ;
IMAD R13, R13, c[0x0][0x16c], R0 ;
HFMA2.MMA R4, -RZ, RZ, 0, 2.384185791015625e-07 ;
IMAD.WIDE.U32 R4, R13, R4, c[0x0][0x160] ;
LDG.E R4, [R4.64] ;
IADD3 R2, R2, -0x1, RZ ;
IADD3 R13, R13, c[0x0][0x16c], RZ ;
ISETP.NE.AND P0, PT, R2, RZ, PT ;
FFMA R3, R4, R4, R3 ;
@P0 BRA 0x320 ;
MOV R5, 0x4 ;
IMAD.WIDE.U32 R4, R0, R5, c[0x0][0x178] ;
STG.E [R4.64], R3 ;
EXIT ;
BRA 0x3e0;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
```
|
```amdasm
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z13cuComputeNormPfiiiS_ ; -- Begin function _Z13cuComputeNormPfiiiS_
.globl _Z13cuComputeNormPfiiiS_
.p2align 8
.type _Z13cuComputeNormPfiiiS_,@function
_Z13cuComputeNormPfiiiS_: ; @_Z13cuComputeNormPfiiiS_
; %bb.0:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b128 s[4:7], s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_u32_e64 s4, v1
s_cbranch_execz .LBB0_6
; %bb.1: ; %.preheader
s_cmp_lt_i32 s6, 1
s_cbranch_scc1 .LBB0_4
; %bb.2: ; %.lr.ph.preheader
s_load_b64 s[2:3], s[0:1], 0x0
v_dual_mov_b32 v3, 0 :: v_dual_mov_b32 v2, v1
s_delay_alu instid0(VALU_DEP_1)
v_mov_b32_e32 v0, v3
.LBB0_3: ; %.lr.ph
; =>This Inner Loop Header: Depth=1
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_lshlrev_b64 v[4:5], 2, v[2:3]
v_add_nc_u32_e32 v2, s5, v2
s_add_i32 s6, s6, -1
s_cmp_lg_u32 s6, 0
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2)
v_add_co_u32 v4, vcc_lo, s2, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s3, v5, vcc_lo
global_load_b32 v4, v[4:5], off
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v0, v4, v4
s_cbranch_scc1 .LBB0_3
s_branch .LBB0_5
.LBB0_4:
v_mov_b32_e32 v0, 0
.LBB0_5: ; %._crit_edge
s_load_b64 s[0:1], s[0:1], 0x18
v_mov_b32_e32 v2, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v1, vcc_lo, s0, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
global_store_b32 v[1:2], v0, off
.LBB0_6:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13cuComputeNormPfiiiS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z13cuComputeNormPfiiiS_, .Lfunc_end0-_Z13cuComputeNormPfiiiS_
; -- End function
.section .AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 228
; NumSgprs: 18
; NumVgprs: 6
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 6
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object ; @__hip_cuid_
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0 ; 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13cuComputeNormPfiiiS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z13cuComputeNormPfiiiS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
```
| 1,286 | 2,849 |
111 |
Convert the following CUDA host assembly code to AMD host assembly:
```cudaasm
.file "tmpxft_000cc80f_00000000-6_cuComputeNorm.cudafe1.cpp"
.text
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z38__device_stub__Z13cuComputeNormPfiiiS_PfiiiS_
.type _Z38__device_stub__Z13cuComputeNormPfiiiS_PfiiiS_, @function
_Z38__device_stub__Z13cuComputeNormPfiiiS_PfiiiS_:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movl %esi, 20(%rsp)
movl %edx, 16(%rsp)
movl %ecx, 12(%rsp)
movq %r8, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 12(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z13cuComputeNormPfiiiS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z38__device_stub__Z13cuComputeNormPfiiiS_PfiiiS_, .-_Z38__device_stub__Z13cuComputeNormPfiiiS_PfiiiS_
.globl _Z13cuComputeNormPfiiiS_
.type _Z13cuComputeNormPfiiiS_, @function
_Z13cuComputeNormPfiiiS_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z38__device_stub__Z13cuComputeNormPfiiiS_PfiiiS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z13cuComputeNormPfiiiS_, .-_Z13cuComputeNormPfiiiS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z13cuComputeNormPfiiiS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z13cuComputeNormPfiiiS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
```
|
```amdasm
.text
.file "cuComputeNorm.hip"
.globl _Z28__device_stub__cuComputeNormPfiiiS_ # -- Begin function _Z28__device_stub__cuComputeNormPfiiiS_
.type _Z28__device_stub__cuComputeNormPfiiiS_,@function
_Z28__device_stub__cuComputeNormPfiiiS_: # @_Z28__device_stub__cuComputeNormPfiiiS_
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $128, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 40(%rsp), %rax
movq %rdi, (%rax)
leaq 12(%rsp), %rdi
movl %esi, (%rdi)
leaq 8(%rsp), %rsi
movl %edx, (%rsi)
leaq 4(%rsp), %rdx
movl %ecx, (%rdx)
leaq 32(%rsp), %rcx
movq %r8, (%rcx)
leaq 80(%rsp), %rbx
movq %rax, (%rbx)
movq %rdi, 8(%rbx)
movq %rsi, 16(%rbx)
movq %rdx, 24(%rbx)
movq %rcx, 32(%rbx)
leaq 64(%rsp), %r14
leaq 48(%rsp), %r15
leaq 24(%rsp), %r12
leaq 16(%rsp), %r13
movq %r14, %rdi
movq %r15, %rsi
movq %r12, %rdx
movq %r13, %rcx
callq __hipPopCallConfiguration
movq (%r14), %rsi
movl 8(%r14), %edx
movq (%r15), %rcx
movl 8(%r15), %r8d
movl $_Z13cuComputeNormPfiiiS_, %edi
movq %rbx, %r9
pushq (%r13)
.cfi_adjust_cfa_offset 8
pushq (%r12)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $144, %rsp
.cfi_adjust_cfa_offset -144
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z28__device_stub__cuComputeNormPfiiiS_, .Lfunc_end0-_Z28__device_stub__cuComputeNormPfiiiS_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, %rdi
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13cuComputeNormPfiiiS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z13cuComputeNormPfiiiS_,@object # @_Z13cuComputeNormPfiiiS_
.section .rodata,"a",@progbits
.globl _Z13cuComputeNormPfiiiS_
.p2align 3, 0x0
_Z13cuComputeNormPfiiiS_:
.quad _Z28__device_stub__cuComputeNormPfiiiS_
.size _Z13cuComputeNormPfiiiS_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z13cuComputeNormPfiiiS_"
.size .L__unnamed_1, 25
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z28__device_stub__cuComputeNormPfiiiS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z13cuComputeNormPfiiiS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
```
| 1,937 | 2,123 |
112 |
Convert the following CUDA device assembly code to AMD device assembly:
```cudaasm
code for sm_80
Function : _Z12file1_kerneliRi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ;
IMAD.MOV R5, RZ, RZ, -c[0x0][0x160] ;
MOV R2, c[0x0][0x168] ;
ULDC.64 UR4, c[0x0][0x118] ;
MOV R3, c[0x0][0x16c] ;
STG.E [R2.64], R5 ;
EXIT ;
BRA 0x70;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
```
|
```amdasm
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z12file1_kerneliRi ; -- Begin function _Z12file1_kerneliRi
.globl _Z12file1_kerneliRi
.p2align 8
.type _Z12file1_kerneliRi,@function
_Z12file1_kerneliRi: ; @_Z12file1_kerneliRi
; %bb.0:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_sub_i32 s2, 0, s2
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
global_store_b32 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z12file1_kerneliRi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 16
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 3
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z12file1_kerneliRi, .Lfunc_end0-_Z12file1_kerneliRi
; -- End function
.section .AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 60
; NumSgprs: 3
; NumVgprs: 2
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 0
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 3
; NumVGPRsForWavesPerEU: 2
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object ; @__hip_cuid_
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0 ; 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 16
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z12file1_kerneliRi
.private_segment_fixed_size: 0
.sgpr_count: 3
.sgpr_spill_count: 0
.symbol: _Z12file1_kerneliRi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
```
| 220 | 1,718 |
113 |
Convert the following CUDA host assembly code to AMD host assembly:
```cudaasm
.file "tmpxft_000fbb7a_00000000-6_file1.cudafe1.cpp"
.text
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2030:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z33__device_stub__Z12file1_kerneliRiiPi
.type _Z33__device_stub__Z12file1_kerneliRiiPi, @function
_Z33__device_stub__Z12file1_kerneliRiiPi:
.LFB2052:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 12(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z12file1_kerneliRi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2052:
.size _Z33__device_stub__Z12file1_kerneliRiiPi, .-_Z33__device_stub__Z12file1_kerneliRiiPi
.globl _Z12file1_kerneliRi
.type _Z12file1_kerneliRi, @function
_Z12file1_kerneliRi:
.LFB2053:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z12file1_kerneliRiiPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2053:
.size _Z12file1_kerneliRi, .-_Z12file1_kerneliRi
.globl _Z19file1_launch_kerneli
.type _Z19file1_launch_kerneli, @function
_Z19file1_launch_kerneli:
.LFB2027:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $48, %rsp
.cfi_def_cfa_offset 64
movl %edi, %ebx
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movl $0, 12(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L15
.L12:
movl 12(%rsp), %eax
movq 40(%rsp), %rdx
subq %fs:40, %rdx
jne .L16
addq $48, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
leaq 12(%rsp), %rsi
movl %ebx, %edi
call _Z33__device_stub__Z12file1_kerneliRiiPi
jmp .L12
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2027:
.size _Z19file1_launch_kerneli, .-_Z19file1_launch_kerneli
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z12file1_kerneliRi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2055:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z12file1_kerneliRi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2055:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
```
|
```amdasm
.text
.file "file1.hip"
.globl _Z27__device_stub__file1_kerneliRi # -- Begin function _Z27__device_stub__file1_kerneliRi
.type _Z27__device_stub__file1_kerneliRi,@function
_Z27__device_stub__file1_kerneliRi: # @_Z27__device_stub__file1_kerneliRi
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $80, %rsp
.cfi_def_cfa_offset 128
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 4(%rsp), %rax
movl %edi, (%rax)
leaq 24(%rsp), %rcx
movq %rsi, (%rcx)
leaq 64(%rsp), %rbx
movq %rax, (%rbx)
movq %rcx, 8(%rbx)
leaq 48(%rsp), %r14
leaq 32(%rsp), %r15
leaq 16(%rsp), %r12
leaq 8(%rsp), %r13
movq %r14, %rdi
movq %r15, %rsi
movq %r12, %rdx
movq %r13, %rcx
callq __hipPopCallConfiguration
movq (%r14), %rsi
movl 8(%r14), %edx
movq (%r15), %rcx
movl 8(%r15), %r8d
movl $_Z12file1_kerneliRi, %edi
movq %rbx, %r9
pushq (%r13)
.cfi_adjust_cfa_offset 8
pushq (%r12)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $96, %rsp
.cfi_adjust_cfa_offset -96
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z27__device_stub__file1_kerneliRi, .Lfunc_end0-_Z27__device_stub__file1_kerneliRi
.cfi_endproc
# -- End function
.globl _Z19file1_launch_kerneli # -- Begin function _Z19file1_launch_kerneli
.type _Z19file1_launch_kerneli,@function
_Z19file1_launch_kerneli: # @_Z19file1_launch_kerneli
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
pushq %rax
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movl %edi, %ebx
movl $0, 4(%rsp)
xorl %r14d, %r14d
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
leaq 4(%rsp), %r14
movl %ebx, %edi
movq %r14, %rsi
callq _Z27__device_stub__file1_kerneliRi
movl (%r14), %r14d
.LBB1_2:
movl %r14d, %eax
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z19file1_launch_kerneli, .Lfunc_end1-_Z19file1_launch_kerneli
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, %rdi
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12file1_kerneliRi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z12file1_kerneliRi,@object # @_Z12file1_kerneliRi
.section .rodata,"a",@progbits
.globl _Z12file1_kerneliRi
.p2align 3, 0x0
_Z12file1_kerneliRi:
.quad _Z27__device_stub__file1_kerneliRi
.size _Z12file1_kerneliRi, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z12file1_kerneliRi"
.size .L__unnamed_1, 20
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z27__device_stub__file1_kerneliRi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z12file1_kerneliRi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
```
| 2,287 | 2,487 |
114 |
Convert the following CUDA device assembly code to AMD device assembly:
```cudaasm
code for sm_80
Function : _Z5printv
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ;
S2R R8, SR_TID.X ;
IADD3 R1, R1, -0x8, RZ ;
IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x8] ;
MOV R0, 0x0 ;
IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0xc] ;
IADD3 R6, P0, R1, c[0x0][0x20], RZ ;
LDC.64 R2, c[0x4][R0] ;
IMAD.X R7, RZ, RZ, c[0x0][0x24], P0 ;
STL [R1], R8 ;
LEPC R8 ;
MOV R11, 0x120 ;
MOV R20, 0xa0 ;
MOV R21, 0x0 ;
MOV R0, 0x0 ;
IADD3 R20, P0, P1, -R20, R11, R8 ;
IADD3.X R21, ~R0, R21, R9, P0, P1 ;
CALL.ABS.NOINC R2 ;
EXIT ;
BRA 0x130;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
```
|
```amdasm
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z5printv ; -- Begin function _Z5printv
.globl _Z5printv
.p2align 8
.type _Z5printv,@function
_Z5printv: ; @_Z5printv
; %bb.0:
s_load_b64 s[2:3], s[0:1], 0x50
v_mbcnt_lo_u32_b32 v31, -1, 0
v_mov_b32_e32 v7, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_dual_mov_b32 v8, 0 :: v_dual_mov_b32 v5, v31
;;#ASMSTART
;;#ASMEND
v_readfirstlane_b32 s0, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_eq_u32_e64 s0, s0, v5
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_6
; %bb.1:
v_mov_b32_e32 v1, 0
s_mov_b32 s4, exec_lo
s_waitcnt lgkmcnt(0)
global_load_b64 v[9:10], v1, s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
s_clause 0x1
global_load_b64 v[2:3], v1, s[2:3] offset:40
global_load_b64 v[6:7], v1, s[2:3]
s_waitcnt vmcnt(1)
v_and_b32_e32 v2, v2, v9
v_and_b32_e32 v3, v3, v10
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_hi_u32 v4, v2, 24
v_mul_lo_u32 v3, v3, 24
v_mul_lo_u32 v2, v2, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v3, v4, v3
s_waitcnt vmcnt(0)
v_add_co_u32 v2, vcc_lo, v6, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, v7, v3, vcc_lo
global_load_b64 v[7:8], v[2:3], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[7:8], v1, v[7:10], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmpx_ne_u64_e64 v[7:8], v[9:10]
s_cbranch_execz .LBB0_5
; %bb.2: ; %.preheader3.i.i.i.preheader
s_mov_b32 s5, 0
.LBB0_3: ; %.preheader3.i.i.i
; =>This Inner Loop Header: Depth=1
s_sleep 1
s_clause 0x1
global_load_b64 v[2:3], v1, s[2:3] offset:40
global_load_b64 v[11:12], v1, s[2:3]
v_dual_mov_b32 v10, v8 :: v_dual_mov_b32 v9, v7
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_and_b32_e32 v2, v2, v9
v_and_b32_e32 v8, v3, v10
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[6:7], null, v2, 24, v[11:12]
v_mov_b32_e32 v2, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[3:4], null, v8, 24, v[2:3]
v_mov_b32_e32 v7, v3
global_load_b64 v[7:8], v[6:7], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[7:8], v1, v[7:10], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmp_eq_u64_e32 vcc_lo, v[7:8], v[9:10]
s_or_b32 s5, vcc_lo, s5
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s5
s_cbranch_execnz .LBB0_3
; %bb.4: ; %Flow315
s_or_b32 exec_lo, exec_lo, s5
.LBB0_5: ; %Flow317
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s4
.LBB0_6: ; %.loopexit4.i.i.i
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s1
v_mov_b32_e32 v6, 0
v_readfirstlane_b32 s4, v7
v_readfirstlane_b32 s5, v8
s_mov_b32 s10, exec_lo
s_waitcnt lgkmcnt(0)
s_clause 0x1
global_load_b64 v[9:10], v6, s[2:3] offset:40
global_load_b128 v[1:4], v6, s[2:3]
s_waitcnt vmcnt(1)
v_readfirstlane_b32 s6, v9
v_readfirstlane_b32 s7, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b64 s[6:7], s[4:5], s[6:7]
s_mul_i32 s1, s7, 24
s_mul_hi_u32 s8, s6, 24
s_mul_i32 s9, s6, 24
s_and_saveexec_b32 s11, s0
s_cbranch_execz .LBB0_8
; %bb.7:
v_dual_mov_b32 v7, s10 :: v_dual_mov_b32 v8, v6
s_add_i32 s10, s8, s1
s_waitcnt vmcnt(0)
v_add_co_u32 v11, vcc_lo, v1, s9
v_add_co_ci_u32_e32 v12, vcc_lo, s10, v2, vcc_lo
v_dual_mov_b32 v9, 2 :: v_dual_mov_b32 v10, 1
global_store_b128 v[11:12], v[7:10], off offset:8
.LBB0_8:
s_or_b32 exec_lo, exec_lo, s11
s_lshl_b64 s[6:7], s[6:7], 12
v_lshlrev_b64 v[7:8], 6, v[5:6]
s_waitcnt vmcnt(0)
v_add_co_u32 v3, vcc_lo, v3, s6
v_add_co_ci_u32_e32 v4, vcc_lo, s7, v4, vcc_lo
s_mov_b32 s12, 0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_u32 v9, vcc_lo, v3, v7
s_mov_b32 s13, s12
s_mov_b32 s14, s12
s_mov_b32 s15, s12
v_add_co_ci_u32_e32 v10, vcc_lo, v4, v8, vcc_lo
v_dual_mov_b32 v5, 33 :: v_dual_mov_b32 v8, v6
v_mov_b32_e32 v7, v6
v_dual_mov_b32 v11, s12 :: v_dual_mov_b32 v14, s15
v_dual_mov_b32 v12, s13 :: v_dual_mov_b32 v13, s14
s_clause 0x3
global_store_b128 v[9:10], v[5:8], off
global_store_b128 v[9:10], v[11:14], off offset:16
global_store_b128 v[9:10], v[11:14], off offset:32
global_store_b128 v[9:10], v[11:14], off offset:48
s_and_saveexec_b32 s6, s0
s_cbranch_execz .LBB0_16
; %bb.9:
v_mov_b32_e32 v11, 0
s_mov_b32 s7, exec_lo
s_clause 0x1
global_load_b64 v[14:15], v11, s[2:3] offset:32 glc
global_load_b64 v[3:4], v11, s[2:3] offset:40
v_dual_mov_b32 v12, s4 :: v_dual_mov_b32 v13, s5
s_waitcnt vmcnt(0)
v_and_b32_e32 v4, s5, v4
v_and_b32_e32 v3, s4, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_lo_u32 v4, v4, 24
v_mul_hi_u32 v5, v3, 24
v_mul_lo_u32 v3, v3, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v4, v5, v4
v_add_co_u32 v7, vcc_lo, v1, v3
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v8, vcc_lo, v2, v4, vcc_lo
global_store_b64 v[7:8], v[14:15], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[5:6], v11, v[12:15], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmpx_ne_u64_e64 v[5:6], v[14:15]
s_cbranch_execz .LBB0_12
; %bb.10: ; %.preheader1.i.i.i.preheader
s_mov_b32 s10, 0
.LBB0_11: ; %.preheader1.i.i.i
; =>This Inner Loop Header: Depth=1
v_dual_mov_b32 v3, s4 :: v_dual_mov_b32 v4, s5
s_sleep 1
global_store_b64 v[7:8], v[5:6], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[3:4], v11, v[3:6], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[3:4], v[5:6]
v_dual_mov_b32 v6, v4 :: v_dual_mov_b32 v5, v3
s_or_b32 s10, vcc_lo, s10
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s10
s_cbranch_execnz .LBB0_11
.LBB0_12: ; %Flow313
s_or_b32 exec_lo, exec_lo, s7
v_mov_b32_e32 v6, 0
s_mov_b32 s10, exec_lo
s_mov_b32 s7, exec_lo
v_mbcnt_lo_u32_b32 v5, s10, 0
global_load_b64 v[3:4], v6, s[2:3] offset:16
v_cmpx_eq_u32_e32 0, v5
s_cbranch_execz .LBB0_14
; %bb.13:
s_bcnt1_i32_b32 s10, s10
s_delay_alu instid0(SALU_CYCLE_1)
v_mov_b32_e32 v5, s10
s_waitcnt vmcnt(0)
global_atomic_add_u64 v[3:4], v[5:6], off offset:8
.LBB0_14:
s_or_b32 exec_lo, exec_lo, s7
s_waitcnt vmcnt(0)
global_load_b64 v[5:6], v[3:4], off offset:16
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, 0, v[5:6]
s_cbranch_vccnz .LBB0_16
; %bb.15:
global_load_b32 v3, v[3:4], off offset:24
v_mov_b32_e32 v4, 0
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s7, v3
s_waitcnt_vscnt null, 0x0
global_store_b64 v[5:6], v[3:4], off
s_and_b32 m0, s7, 0xff
s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_16: ; %Flow314
s_or_b32 exec_lo, exec_lo, s6
s_add_i32 s8, s8, s1
v_add_co_u32 v1, vcc_lo, v1, s9
v_add_co_ci_u32_e32 v2, vcc_lo, s8, v2, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v1, vcc_lo, v1, 20
v_add_co_ci_u32_e32 v2, vcc_lo, 0, v2, vcc_lo
.LBB0_17: ; =>This Inner Loop Header: Depth=1
v_mov_b32_e32 v3, 1
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_19
; %bb.18: ; in Loop: Header=BB0_17 Depth=1
global_load_b32 v3, v[1:2], off glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_and_b32_e32 v3, 1, v3
.LBB0_19: ; in Loop: Header=BB0_17 Depth=1
s_or_b32 exec_lo, exec_lo, s1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s1, v3
s_cmp_eq_u32 s1, 0
s_cbranch_scc1 .LBB0_21
; %bb.20: ; in Loop: Header=BB0_17 Depth=1
s_mov_b32 s1, 0
s_sleep 1
s_branch .LBB0_22
.LBB0_21: ; in Loop: Header=BB0_17 Depth=1
s_mov_b32 s1, -1
.LBB0_22: ; %Flow308
; in Loop: Header=BB0_17 Depth=1
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 vcc_lo, exec_lo, s1
s_cbranch_vccnz .LBB0_17
; %bb.23:
global_load_b64 v[1:2], v[9:10], off
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_27
; %bb.24:
v_mov_b32_e32 v9, 0
s_clause 0x2
global_load_b64 v[5:6], v9, s[2:3] offset:40
global_load_b64 v[10:11], v9, s[2:3] offset:24 glc
global_load_b64 v[7:8], v9, s[2:3]
s_waitcnt vmcnt(2)
v_add_co_u32 v12, vcc_lo, v5, 1
v_add_co_ci_u32_e32 v13, vcc_lo, 0, v6, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v3, vcc_lo, v12, s4
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v13, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_eq_u64_e32 vcc_lo, 0, v[3:4]
v_dual_cndmask_b32 v4, v4, v13 :: v_dual_cndmask_b32 v3, v3, v12
v_and_b32_e32 v6, v4, v6
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_and_b32_e32 v5, v3, v5
v_mul_lo_u32 v6, v6, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_hi_u32 v12, v5, 24
v_mul_lo_u32 v5, v5, 24
v_add_nc_u32_e32 v6, v12, v6
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_co_u32 v7, vcc_lo, v7, v5
v_mov_b32_e32 v5, v10
v_add_co_ci_u32_e32 v8, vcc_lo, v8, v6, vcc_lo
v_mov_b32_e32 v6, v11
global_store_b64 v[7:8], v[10:11], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[5:6], v9, v[3:6], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_ne_u64_e32 vcc_lo, v[5:6], v[10:11]
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_27
; %bb.25: ; %.preheader.i.i.i.preheader
s_mov_b32 s0, 0
.LBB0_26: ; %.preheader.i.i.i
; =>This Inner Loop Header: Depth=1
s_sleep 1
global_store_b64 v[7:8], v[5:6], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[10:11], v9, v[3:6], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[10:11], v[5:6]
v_dual_mov_b32 v5, v10 :: v_dual_mov_b32 v6, v11
s_or_b32 s0, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s0
s_cbranch_execnz .LBB0_26
.LBB0_27: ; %__ockl_printf_begin.exit
s_or_b32 exec_lo, exec_lo, s1
s_getpc_b64 s[4:5]
s_add_u32 s4, s4, .str@rel32@lo+4
s_addc_u32 s5, s5, .str@rel32@hi+12
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_lg_u64 s[4:5], 0
s_cbranch_scc0 .LBB0_113
; %bb.28:
s_waitcnt vmcnt(0)
v_dual_mov_b32 v7, 2 :: v_dual_and_b32 v32, 2, v1
v_dual_mov_b32 v30, 0 :: v_dual_and_b32 v3, -3, v1
v_mov_b32_e32 v4, v2
v_mov_b32_e32 v8, 1
s_mov_b64 s[6:7], 4
.LBB0_29: ; =>This Loop Header: Depth=1
; Child Loop BB0_32 Depth 2
; Child Loop BB0_39 Depth 2
; Child Loop BB0_47 Depth 2
; Child Loop BB0_55 Depth 2
; Child Loop BB0_63 Depth 2
; Child Loop BB0_71 Depth 2
; Child Loop BB0_79 Depth 2
; Child Loop BB0_87 Depth 2
; Child Loop BB0_95 Depth 2
; Child Loop BB0_101 Depth 2
; Child Loop BB0_110 Depth 2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_lt_u64_e64 s0, s[6:7], 56
; implicit-def: $vgpr11_vgpr12
; implicit-def: $sgpr15
s_and_b32 s0, s0, exec_lo
s_cselect_b32 s8, s6, 56
s_cselect_b32 s9, s7, 0
s_cmp_gt_u32 s8, 7
s_mov_b32 s0, -1
s_cbranch_scc1 .LBB0_34
; %bb.30: ; in Loop: Header=BB0_29 Depth=1
v_mov_b32_e32 v11, 0
v_mov_b32_e32 v12, 0
s_cmp_eq_u32 s8, 0
s_cbranch_scc1 .LBB0_33
; %bb.31: ; %.preheader31.i.preheader
; in Loop: Header=BB0_29 Depth=1
s_lshl_b64 s[0:1], s[8:9], 3
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], s[4:5]
.LBB0_32: ; %.preheader31.i
; Parent Loop BB0_29 Depth=1
; => This Inner Loop Header: Depth=2
global_load_u8 v5, v30, s[12:13]
s_waitcnt vmcnt(0)
v_and_b32_e32 v29, 0xffff, v5
s_delay_alu instid0(VALU_DEP_1)
v_lshlrev_b64 v[5:6], s10, v[29:30]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_add_u32 s12, s12, 1
s_addc_u32 s13, s13, 0
s_cmp_lg_u32 s0, s10
v_or_b32_e32 v11, v5, v11
v_or_b32_e32 v12, v6, v12
s_cbranch_scc1 .LBB0_32
.LBB0_33: ; %Flow284
; in Loop: Header=BB0_29 Depth=1
s_mov_b32 s0, 0
s_mov_b32 s15, 0
.LBB0_34: ; %Flow286
; in Loop: Header=BB0_29 Depth=1
s_and_not1_b32 vcc_lo, exec_lo, s0
s_mov_b64 s[0:1], s[4:5]
s_cbranch_vccnz .LBB0_36
; %bb.35: ; in Loop: Header=BB0_29 Depth=1
global_load_b64 v[11:12], v30, s[4:5]
s_add_i32 s15, s8, -8
s_add_u32 s0, s4, 8
s_addc_u32 s1, s5, 0
.LBB0_36: ; %.loopexit32.i
; in Loop: Header=BB0_29 Depth=1
s_cmp_gt_u32 s15, 7
s_cbranch_scc1 .LBB0_41
; %bb.37: ; in Loop: Header=BB0_29 Depth=1
v_mov_b32_e32 v13, 0
v_mov_b32_e32 v14, 0
s_cmp_eq_u32 s15, 0
s_cbranch_scc1 .LBB0_40
; %bb.38: ; %.preheader29.i.preheader
; in Loop: Header=BB0_29 Depth=1
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_39: ; %.preheader29.i
; Parent Loop BB0_29 Depth=1
; => This Inner Loop Header: Depth=2
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v5, v30, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v29, 0xffff, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[5:6], s10, v[29:30]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s15, s12
v_or_b32_e32 v13, v5, v13
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v14, v6, v14
s_cbranch_scc1 .LBB0_39
.LBB0_40: ; %Flow279
; in Loop: Header=BB0_29 Depth=1
s_mov_b32 s10, 0
s_mov_b32 s14, 0
s_branch .LBB0_42
.LBB0_41: ; in Loop: Header=BB0_29 Depth=1
s_mov_b32 s10, -1
; implicit-def: $vgpr13_vgpr14
; implicit-def: $sgpr14
.LBB0_42: ; %Flow281
; in Loop: Header=BB0_29 Depth=1
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 vcc_lo, exec_lo, s10
s_cbranch_vccnz .LBB0_44
; %bb.43: ; in Loop: Header=BB0_29 Depth=1
global_load_b64 v[13:14], v30, s[0:1]
s_add_i32 s14, s15, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_44: ; %.loopexit30.i
; in Loop: Header=BB0_29 Depth=1
s_cmp_gt_u32 s14, 7
s_cbranch_scc1 .LBB0_49
; %bb.45: ; in Loop: Header=BB0_29 Depth=1
v_mov_b32_e32 v15, 0
v_mov_b32_e32 v16, 0
s_cmp_eq_u32 s14, 0
s_cbranch_scc1 .LBB0_48
; %bb.46: ; %.preheader27.i.preheader
; in Loop: Header=BB0_29 Depth=1
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_47: ; %.preheader27.i
; Parent Loop BB0_29 Depth=1
; => This Inner Loop Header: Depth=2
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v5, v30, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v29, 0xffff, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[5:6], s10, v[29:30]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s14, s12
v_or_b32_e32 v15, v5, v15
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v16, v6, v16
s_cbranch_scc1 .LBB0_47
.LBB0_48: ; %Flow274
; in Loop: Header=BB0_29 Depth=1
s_mov_b32 s10, 0
s_mov_b32 s15, 0
s_branch .LBB0_50
.LBB0_49: ; in Loop: Header=BB0_29 Depth=1
s_mov_b32 s10, -1
; implicit-def: $sgpr15
.LBB0_50: ; %Flow276
; in Loop: Header=BB0_29 Depth=1
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 vcc_lo, exec_lo, s10
s_cbranch_vccnz .LBB0_52
; %bb.51: ; in Loop: Header=BB0_29 Depth=1
global_load_b64 v[15:16], v30, s[0:1]
s_add_i32 s15, s14, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_52: ; %.loopexit28.i
; in Loop: Header=BB0_29 Depth=1
s_cmp_gt_u32 s15, 7
s_cbranch_scc1 .LBB0_57
; %bb.53: ; in Loop: Header=BB0_29 Depth=1
v_mov_b32_e32 v17, 0
v_mov_b32_e32 v18, 0
s_cmp_eq_u32 s15, 0
s_cbranch_scc1 .LBB0_56
; %bb.54: ; %.preheader25.i.preheader
; in Loop: Header=BB0_29 Depth=1
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_55: ; %.preheader25.i
; Parent Loop BB0_29 Depth=1
; => This Inner Loop Header: Depth=2
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v5, v30, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v29, 0xffff, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[5:6], s10, v[29:30]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s15, s12
v_or_b32_e32 v17, v5, v17
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v18, v6, v18
s_cbranch_scc1 .LBB0_55
.LBB0_56: ; %Flow269
; in Loop: Header=BB0_29 Depth=1
s_mov_b32 s10, 0
s_mov_b32 s14, 0
s_branch .LBB0_58
.LBB0_57: ; in Loop: Header=BB0_29 Depth=1
s_mov_b32 s10, -1
; implicit-def: $vgpr17_vgpr18
; implicit-def: $sgpr14
.LBB0_58: ; %Flow271
; in Loop: Header=BB0_29 Depth=1
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 vcc_lo, exec_lo, s10
s_cbranch_vccnz .LBB0_60
; %bb.59: ; in Loop: Header=BB0_29 Depth=1
global_load_b64 v[17:18], v30, s[0:1]
s_add_i32 s14, s15, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_60: ; %.loopexit26.i
; in Loop: Header=BB0_29 Depth=1
s_cmp_gt_u32 s14, 7
s_cbranch_scc1 .LBB0_65
; %bb.61: ; in Loop: Header=BB0_29 Depth=1
v_mov_b32_e32 v19, 0
v_mov_b32_e32 v20, 0
s_cmp_eq_u32 s14, 0
s_cbranch_scc1 .LBB0_64
; %bb.62: ; %.preheader23.i.preheader
; in Loop: Header=BB0_29 Depth=1
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_63: ; %.preheader23.i
; Parent Loop BB0_29 Depth=1
; => This Inner Loop Header: Depth=2
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v5, v30, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v29, 0xffff, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[5:6], s10, v[29:30]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s14, s12
v_or_b32_e32 v19, v5, v19
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v20, v6, v20
s_cbranch_scc1 .LBB0_63
.LBB0_64: ; %Flow264
; in Loop: Header=BB0_29 Depth=1
s_mov_b32 s10, 0
s_mov_b32 s15, 0
s_branch .LBB0_66
.LBB0_65: ; in Loop: Header=BB0_29 Depth=1
s_mov_b32 s10, -1
; implicit-def: $sgpr15
.LBB0_66: ; %Flow266
; in Loop: Header=BB0_29 Depth=1
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 vcc_lo, exec_lo, s10
s_cbranch_vccnz .LBB0_68
; %bb.67: ; in Loop: Header=BB0_29 Depth=1
global_load_b64 v[19:20], v30, s[0:1]
s_add_i32 s15, s14, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_68: ; %.loopexit24.i
; in Loop: Header=BB0_29 Depth=1
s_cmp_gt_u32 s15, 7
s_cbranch_scc1 .LBB0_73
; %bb.69: ; in Loop: Header=BB0_29 Depth=1
v_mov_b32_e32 v21, 0
v_mov_b32_e32 v22, 0
s_cmp_eq_u32 s15, 0
s_cbranch_scc1 .LBB0_72
; %bb.70: ; %.preheader21.i.preheader
; in Loop: Header=BB0_29 Depth=1
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_71: ; %.preheader21.i
; Parent Loop BB0_29 Depth=1
; => This Inner Loop Header: Depth=2
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v5, v30, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v29, 0xffff, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[5:6], s10, v[29:30]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s15, s12
v_or_b32_e32 v21, v5, v21
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v22, v6, v22
s_cbranch_scc1 .LBB0_71
.LBB0_72: ; %Flow259
; in Loop: Header=BB0_29 Depth=1
s_mov_b32 s10, 0
s_mov_b32 s14, 0
s_branch .LBB0_74
.LBB0_73: ; in Loop: Header=BB0_29 Depth=1
s_mov_b32 s10, -1
; implicit-def: $vgpr21_vgpr22
; implicit-def: $sgpr14
.LBB0_74: ; %Flow261
; in Loop: Header=BB0_29 Depth=1
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 vcc_lo, exec_lo, s10
s_cbranch_vccnz .LBB0_76
; %bb.75: ; in Loop: Header=BB0_29 Depth=1
global_load_b64 v[21:22], v30, s[0:1]
s_add_i32 s14, s15, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_76: ; %.loopexit22.i
; in Loop: Header=BB0_29 Depth=1
s_cmp_gt_u32 s14, 7
s_cbranch_scc1 .LBB0_81
; %bb.77: ; in Loop: Header=BB0_29 Depth=1
v_mov_b32_e32 v23, 0
v_mov_b32_e32 v24, 0
s_cmp_eq_u32 s14, 0
s_cbranch_scc1 .LBB0_80
; %bb.78: ; %.preheader.i.preheader
; in Loop: Header=BB0_29 Depth=1
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], s[0:1]
.LBB0_79: ; %.preheader.i
; Parent Loop BB0_29 Depth=1
; => This Inner Loop Header: Depth=2
global_load_u8 v5, v30, s[12:13]
s_add_i32 s14, s14, -1
s_waitcnt vmcnt(0)
v_and_b32_e32 v29, 0xffff, v5
s_delay_alu instid0(VALU_DEP_1)
v_lshlrev_b64 v[5:6], s10, v[29:30]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_add_u32 s12, s12, 1
s_addc_u32 s13, s13, 0
s_cmp_lg_u32 s14, 0
v_or_b32_e32 v23, v5, v23
v_or_b32_e32 v24, v6, v24
s_cbranch_scc1 .LBB0_79
.LBB0_80: ; %Flow254
; in Loop: Header=BB0_29 Depth=1
s_mov_b32 s10, 0
s_branch .LBB0_82
.LBB0_81: ; in Loop: Header=BB0_29 Depth=1
s_mov_b32 s10, -1
.LBB0_82: ; %Flow256
; in Loop: Header=BB0_29 Depth=1
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 vcc_lo, exec_lo, s10
s_cbranch_vccnz .LBB0_84
; %bb.83: ; in Loop: Header=BB0_29 Depth=1
global_load_b64 v[23:24], v30, s[0:1]
.LBB0_84: ; %.loopexit.i
; in Loop: Header=BB0_29 Depth=1
v_mov_b32_e32 v29, v31
s_waitcnt vmcnt(0)
v_mov_b32_e32 v5, 0
v_mov_b32_e32 v6, 0
;;#ASMSTART
;;#ASMEND
v_readfirstlane_b32 s0, v29
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_eq_u32_e64 s0, s0, v29
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_90
; %bb.85: ; in Loop: Header=BB0_29 Depth=1
global_load_b64 v[27:28], v30, s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
s_clause 0x1
global_load_b64 v[5:6], v30, s[2:3] offset:40
global_load_b64 v[9:10], v30, s[2:3]
s_mov_b32 s10, exec_lo
s_waitcnt vmcnt(1)
v_and_b32_e32 v6, v6, v28
v_and_b32_e32 v5, v5, v27
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_lo_u32 v6, v6, 24
v_mul_hi_u32 v25, v5, 24
v_mul_lo_u32 v5, v5, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v6, v25, v6
s_waitcnt vmcnt(0)
v_add_co_u32 v5, vcc_lo, v9, v5
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v6, vcc_lo, v10, v6, vcc_lo
global_load_b64 v[25:26], v[5:6], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[5:6], v30, v[25:28], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmpx_ne_u64_e64 v[5:6], v[27:28]
s_cbranch_execz .LBB0_89
; %bb.86: ; %.preheader3.i.i19.i.preheader
; in Loop: Header=BB0_29 Depth=1
s_mov_b32 s11, 0
.LBB0_87: ; %.preheader3.i.i19.i
; Parent Loop BB0_29 Depth=1
; => This Inner Loop Header: Depth=2
s_sleep 1
s_clause 0x1
global_load_b64 v[9:10], v30, s[2:3] offset:40
global_load_b64 v[25:26], v30, s[2:3]
v_dual_mov_b32 v28, v6 :: v_dual_mov_b32 v27, v5
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_and_b32_e32 v9, v9, v27
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[5:6], null, v9, 24, v[25:26]
v_and_b32_e32 v25, v10, v28
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[9:10], null, v25, 24, v[6:7]
v_mov_b32_e32 v6, v9
global_load_b64 v[25:26], v[5:6], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[5:6], v30, v[25:28], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmp_eq_u64_e32 vcc_lo, v[5:6], v[27:28]
s_or_b32 s11, vcc_lo, s11
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s11
s_cbranch_execnz .LBB0_87
; %bb.88: ; %Flow249
; in Loop: Header=BB0_29 Depth=1
s_or_b32 exec_lo, exec_lo, s11
.LBB0_89: ; %Flow251
; in Loop: Header=BB0_29 Depth=1
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s10
.LBB0_90: ; %.loopexit4.i.i14.i
; in Loop: Header=BB0_29 Depth=1
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s1
s_clause 0x1
global_load_b64 v[9:10], v30, s[2:3] offset:40
global_load_b128 v[25:28], v30, s[2:3]
v_readfirstlane_b32 s10, v5
v_readfirstlane_b32 s11, v6
s_mov_b32 s16, exec_lo
s_waitcnt vmcnt(1)
v_readfirstlane_b32 s12, v9
v_readfirstlane_b32 s13, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b64 s[12:13], s[10:11], s[12:13]
s_mul_i32 s1, s13, 24
s_mul_hi_u32 s14, s12, 24
s_mul_i32 s15, s12, 24
s_and_saveexec_b32 s17, s0
s_cbranch_execz .LBB0_92
; %bb.91: ; in Loop: Header=BB0_29 Depth=1
v_dual_mov_b32 v5, s16 :: v_dual_mov_b32 v6, v30
s_add_i32 s16, s14, s1
s_waitcnt vmcnt(0)
v_add_co_u32 v9, vcc_lo, v25, s15
v_add_co_ci_u32_e32 v10, vcc_lo, s16, v26, vcc_lo
global_store_b128 v[9:10], v[5:8], off offset:8
.LBB0_92: ; in Loop: Header=BB0_29 Depth=1
s_or_b32 exec_lo, exec_lo, s17
v_cmp_gt_u64_e64 vcc_lo, s[6:7], 56
v_or_b32_e32 v5, 0, v4
v_or_b32_e32 v6, v3, v32
s_lshl_b64 s[12:13], s[12:13], 12
s_lshl_b32 s16, s8, 2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_add_i32 s16, s16, 28
v_dual_cndmask_b32 v10, v5, v4 :: v_dual_cndmask_b32 v5, v6, v3
v_lshlrev_b64 v[3:4], 6, v[29:30]
s_waitcnt vmcnt(0)
v_add_co_u32 v6, vcc_lo, v27, s12
v_add_co_ci_u32_e32 v28, vcc_lo, s13, v28, vcc_lo
s_and_b32 s16, s16, 0x1e0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_co_u32 v27, vcc_lo, v6, v3
v_and_or_b32 v9, 0xffffff1f, v5, s16
v_add_co_ci_u32_e32 v28, vcc_lo, v28, v4, vcc_lo
s_clause 0x3
global_store_b128 v[27:28], v[9:12], off
global_store_b128 v[27:28], v[13:16], off offset:16
global_store_b128 v[27:28], v[17:20], off offset:32
global_store_b128 v[27:28], v[21:24], off offset:48
s_and_saveexec_b32 s12, s0
s_cbranch_execz .LBB0_100
; %bb.93: ; in Loop: Header=BB0_29 Depth=1
s_clause 0x1
global_load_b64 v[13:14], v30, s[2:3] offset:32 glc
global_load_b64 v[3:4], v30, s[2:3] offset:40
v_dual_mov_b32 v11, s10 :: v_dual_mov_b32 v12, s11
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s16, v3
v_readfirstlane_b32 s17, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b64 s[16:17], s[16:17], s[10:11]
s_mul_i32 s13, s17, 24
s_mul_hi_u32 s17, s16, 24
s_mul_i32 s16, s16, 24
s_add_i32 s17, s17, s13
v_add_co_u32 v9, vcc_lo, v25, s16
v_add_co_ci_u32_e32 v10, vcc_lo, s17, v26, vcc_lo
s_mov_b32 s13, exec_lo
global_store_b64 v[9:10], v[13:14], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[5:6], v30, v[11:14], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmpx_ne_u64_e64 v[5:6], v[13:14]
s_cbranch_execz .LBB0_96
; %bb.94: ; %.preheader1.i.i17.i.preheader
; in Loop: Header=BB0_29 Depth=1
s_mov_b32 s16, 0
.LBB0_95: ; %.preheader1.i.i17.i
; Parent Loop BB0_29 Depth=1
; => This Inner Loop Header: Depth=2
v_dual_mov_b32 v3, s10 :: v_dual_mov_b32 v4, s11
s_sleep 1
global_store_b64 v[9:10], v[5:6], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[3:4], v30, v[3:6], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[3:4], v[5:6]
v_dual_mov_b32 v6, v4 :: v_dual_mov_b32 v5, v3
s_or_b32 s16, vcc_lo, s16
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s16
s_cbranch_execnz .LBB0_95
.LBB0_96: ; %Flow247
; in Loop: Header=BB0_29 Depth=1
s_or_b32 exec_lo, exec_lo, s13
global_load_b64 v[3:4], v30, s[2:3] offset:16
s_mov_b32 s16, exec_lo
s_mov_b32 s13, exec_lo
v_mbcnt_lo_u32_b32 v5, s16, 0
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_eq_u32_e32 0, v5
s_cbranch_execz .LBB0_98
; %bb.97: ; in Loop: Header=BB0_29 Depth=1
s_bcnt1_i32_b32 s16, s16
s_delay_alu instid0(SALU_CYCLE_1)
v_mov_b32_e32 v29, s16
s_waitcnt vmcnt(0)
global_atomic_add_u64 v[3:4], v[29:30], off offset:8
.LBB0_98: ; in Loop: Header=BB0_29 Depth=1
s_or_b32 exec_lo, exec_lo, s13
s_waitcnt vmcnt(0)
global_load_b64 v[5:6], v[3:4], off offset:16
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, 0, v[5:6]
s_cbranch_vccnz .LBB0_100
; %bb.99: ; in Loop: Header=BB0_29 Depth=1
global_load_b32 v29, v[3:4], off offset:24
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s13, v29
s_waitcnt_vscnt null, 0x0
global_store_b64 v[5:6], v[29:30], off
s_and_b32 m0, s13, 0xff
s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_100: ; %Flow248
; in Loop: Header=BB0_29 Depth=1
s_or_b32 exec_lo, exec_lo, s12
s_add_i32 s14, s14, s1
v_add_co_u32 v3, vcc_lo, v25, s15
v_add_co_ci_u32_e32 v4, vcc_lo, s14, v26, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v3, vcc_lo, v3, 20
v_add_co_ci_u32_e32 v4, vcc_lo, 0, v4, vcc_lo
.LBB0_101: ; Parent Loop BB0_29 Depth=1
; => This Inner Loop Header: Depth=2
v_mov_b32_e32 v5, 1
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_103
; %bb.102: ; in Loop: Header=BB0_101 Depth=2
global_load_b32 v5, v[3:4], off glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_and_b32_e32 v5, 1, v5
.LBB0_103: ; in Loop: Header=BB0_101 Depth=2
s_or_b32 exec_lo, exec_lo, s1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s1, v5
s_cmp_eq_u32 s1, 0
s_cbranch_scc1 .LBB0_105
; %bb.104: ; in Loop: Header=BB0_101 Depth=2
s_mov_b32 s1, 0
s_sleep 1
s_branch .LBB0_106
.LBB0_105: ; in Loop: Header=BB0_101 Depth=2
s_mov_b32 s1, -1
.LBB0_106: ; %Flow242
; in Loop: Header=BB0_101 Depth=2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 vcc_lo, exec_lo, s1
s_cbranch_vccnz .LBB0_101
; %bb.107: ; in Loop: Header=BB0_29 Depth=1
global_load_b128 v[3:6], v[27:28], off
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_111
; %bb.108: ; in Loop: Header=BB0_29 Depth=1
s_clause 0x2
global_load_b64 v[5:6], v30, s[2:3] offset:40
global_load_b64 v[13:14], v30, s[2:3] offset:24 glc
global_load_b64 v[11:12], v30, s[2:3]
s_waitcnt vmcnt(2)
v_add_co_u32 v15, vcc_lo, v5, 1
v_add_co_ci_u32_e32 v16, vcc_lo, 0, v6, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v9, vcc_lo, v15, s10
v_add_co_ci_u32_e32 v10, vcc_lo, s11, v16, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_eq_u64_e32 vcc_lo, 0, v[9:10]
v_dual_cndmask_b32 v10, v10, v16 :: v_dual_cndmask_b32 v9, v9, v15
v_and_b32_e32 v6, v10, v6
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_and_b32_e32 v5, v9, v5
v_mul_hi_u32 v15, v5, 24
v_mul_lo_u32 v5, v5, 24
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_add_co_u32 v5, vcc_lo, v11, v5
v_mov_b32_e32 v11, v13
v_mul_lo_u32 v6, v6, 24
v_add_nc_u32_e32 v6, v15, v6
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e32 v6, vcc_lo, v12, v6, vcc_lo
v_mov_b32_e32 v12, v14
global_store_b64 v[5:6], v[13:14], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[11:12], v30, v[9:12], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_ne_u64_e32 vcc_lo, v[11:12], v[13:14]
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_111
; %bb.109: ; %.preheader.i.i16.i.preheader
; in Loop: Header=BB0_29 Depth=1
s_mov_b32 s0, 0
.LBB0_110: ; %.preheader.i.i16.i
; Parent Loop BB0_29 Depth=1
; => This Inner Loop Header: Depth=2
s_sleep 1
global_store_b64 v[5:6], v[11:12], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[13:14], v30, v[9:12], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[13:14], v[11:12]
v_dual_mov_b32 v11, v13 :: v_dual_mov_b32 v12, v14
s_or_b32 s0, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s0
s_cbranch_execnz .LBB0_110
.LBB0_111: ; %__ockl_hostcall_preview.exit20.i
; in Loop: Header=BB0_29 Depth=1
s_or_b32 exec_lo, exec_lo, s1
s_sub_u32 s6, s6, s8
s_subb_u32 s7, s7, s9
s_add_u32 s4, s4, s8
s_addc_u32 s5, s5, s9
s_cmp_lg_u64 s[6:7], 0
s_cbranch_scc1 .LBB0_29
; %bb.112: ; %Flow287
s_mov_b32 s0, 0
s_branch .LBB0_114
.LBB0_113:
s_mov_b32 s0, -1
; implicit-def: $vgpr3_vgpr4
.LBB0_114: ; %Flow302
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 vcc_lo, exec_lo, s0
s_cbranch_vccz .LBB0_143
; %bb.115:
s_waitcnt vmcnt(0)
v_mov_b32_e32 v3, v31
v_mov_b32_e32 v9, 0
v_mov_b32_e32 v10, 0
;;#ASMSTART
;;#ASMEND
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s0, v3
v_cmp_eq_u32_e64 s0, s0, v3
s_delay_alu instid0(VALU_DEP_1)
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_121
; %bb.116:
v_mov_b32_e32 v4, 0
s_mov_b32 s4, exec_lo
global_load_b64 v[7:8], v4, s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
s_clause 0x1
global_load_b64 v[5:6], v4, s[2:3] offset:40
global_load_b64 v[9:10], v4, s[2:3]
s_waitcnt vmcnt(1)
v_and_b32_e32 v5, v5, v7
v_and_b32_e32 v6, v6, v8
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_hi_u32 v11, v5, 24
v_mul_lo_u32 v6, v6, 24
v_mul_lo_u32 v5, v5, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v6, v11, v6
s_waitcnt vmcnt(0)
v_add_co_u32 v5, vcc_lo, v9, v5
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v6, vcc_lo, v10, v6, vcc_lo
global_load_b64 v[5:6], v[5:6], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[9:10], v4, v[5:8], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmpx_ne_u64_e64 v[9:10], v[7:8]
s_cbranch_execz .LBB0_120
; %bb.117: ; %.preheader3.i.i.i6.preheader
s_mov_b32 s5, 0
.LBB0_118: ; %.preheader3.i.i.i6
; =>This Inner Loop Header: Depth=1
s_sleep 1
s_clause 0x1
global_load_b64 v[5:6], v4, s[2:3] offset:40
global_load_b64 v[11:12], v4, s[2:3]
v_dual_mov_b32 v7, v9 :: v_dual_mov_b32 v8, v10
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_and_b32_e32 v5, v5, v7
v_and_b32_e32 v6, v6, v8
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[9:10], null, v5, 24, v[11:12]
v_mov_b32_e32 v5, v10
s_delay_alu instid0(VALU_DEP_1)
v_mad_u64_u32 v[10:11], null, v6, 24, v[5:6]
global_load_b64 v[5:6], v[9:10], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[9:10], v4, v[5:8], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmp_eq_u64_e32 vcc_lo, v[9:10], v[7:8]
s_or_b32 s5, vcc_lo, s5
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s5
s_cbranch_execnz .LBB0_118
; %bb.119: ; %Flow299
s_or_b32 exec_lo, exec_lo, s5
.LBB0_120: ; %Flow301
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s4
.LBB0_121: ; %.loopexit4.i.i.i1
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s1
v_mov_b32_e32 v4, 0
v_readfirstlane_b32 s4, v9
v_readfirstlane_b32 s5, v10
s_mov_b32 s10, exec_lo
s_clause 0x1
global_load_b64 v[11:12], v4, s[2:3] offset:40
global_load_b128 v[5:8], v4, s[2:3]
s_waitcnt vmcnt(1)
v_readfirstlane_b32 s6, v11
v_readfirstlane_b32 s7, v12
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b64 s[6:7], s[4:5], s[6:7]
s_mul_i32 s1, s7, 24
s_mul_hi_u32 s8, s6, 24
s_mul_i32 s9, s6, 24
s_and_saveexec_b32 s11, s0
s_cbranch_execz .LBB0_123
; %bb.122:
v_dual_mov_b32 v9, s10 :: v_dual_mov_b32 v10, v4
s_add_i32 s10, s8, s1
s_waitcnt vmcnt(0)
v_add_co_u32 v13, vcc_lo, v5, s9
v_add_co_ci_u32_e32 v14, vcc_lo, s10, v6, vcc_lo
v_dual_mov_b32 v11, 2 :: v_dual_mov_b32 v12, 1
global_store_b128 v[13:14], v[9:12], off offset:8
.LBB0_123:
s_or_b32 exec_lo, exec_lo, s11
s_lshl_b64 s[6:7], s[6:7], 12
v_lshlrev_b64 v[9:10], 6, v[3:4]
s_waitcnt vmcnt(0)
v_add_co_u32 v3, vcc_lo, v7, s6
v_add_co_ci_u32_e32 v8, vcc_lo, s7, v8, vcc_lo
s_mov_b32 s12, 0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_u32 v7, vcc_lo, v3, v9
s_mov_b32 s13, s12
s_mov_b32 s14, s12
s_mov_b32 s15, s12
v_and_or_b32 v1, 0xffffff1f, v1, 32
v_add_co_ci_u32_e32 v8, vcc_lo, v8, v10, vcc_lo
v_mov_b32_e32 v3, v4
v_dual_mov_b32 v9, s12 :: v_dual_mov_b32 v12, s15
v_dual_mov_b32 v10, s13 :: v_dual_mov_b32 v11, s14
s_clause 0x3
global_store_b128 v[7:8], v[1:4], off
global_store_b128 v[7:8], v[9:12], off offset:16
global_store_b128 v[7:8], v[9:12], off offset:32
global_store_b128 v[7:8], v[9:12], off offset:48
s_and_saveexec_b32 s6, s0
s_cbranch_execz .LBB0_131
; %bb.124:
v_dual_mov_b32 v11, 0 :: v_dual_mov_b32 v12, s4
v_mov_b32_e32 v13, s5
s_clause 0x1
global_load_b64 v[14:15], v11, s[2:3] offset:32 glc
global_load_b64 v[1:2], v11, s[2:3] offset:40
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s10, v1
v_readfirstlane_b32 s11, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b64 s[10:11], s[10:11], s[4:5]
s_mul_i32 s7, s11, 24
s_mul_hi_u32 s11, s10, 24
s_mul_i32 s10, s10, 24
s_add_i32 s11, s11, s7
v_add_co_u32 v9, vcc_lo, v5, s10
v_add_co_ci_u32_e32 v10, vcc_lo, s11, v6, vcc_lo
s_mov_b32 s7, exec_lo
global_store_b64 v[9:10], v[14:15], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[3:4], v11, v[12:15], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmpx_ne_u64_e64 v[3:4], v[14:15]
s_cbranch_execz .LBB0_127
; %bb.125: ; %.preheader1.i.i.i4.preheader
s_mov_b32 s10, 0
.LBB0_126: ; %.preheader1.i.i.i4
; =>This Inner Loop Header: Depth=1
v_dual_mov_b32 v1, s4 :: v_dual_mov_b32 v2, s5
s_sleep 1
global_store_b64 v[9:10], v[3:4], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[1:2], v11, v[1:4], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[1:2], v[3:4]
v_dual_mov_b32 v4, v2 :: v_dual_mov_b32 v3, v1
s_or_b32 s10, vcc_lo, s10
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s10
s_cbranch_execnz .LBB0_126
.LBB0_127: ; %Flow297
s_or_b32 exec_lo, exec_lo, s7
v_mov_b32_e32 v4, 0
s_mov_b32 s10, exec_lo
s_mov_b32 s7, exec_lo
v_mbcnt_lo_u32_b32 v3, s10, 0
global_load_b64 v[1:2], v4, s[2:3] offset:16
v_cmpx_eq_u32_e32 0, v3
s_cbranch_execz .LBB0_129
; %bb.128:
s_bcnt1_i32_b32 s10, s10
s_delay_alu instid0(SALU_CYCLE_1)
v_mov_b32_e32 v3, s10
s_waitcnt vmcnt(0)
global_atomic_add_u64 v[1:2], v[3:4], off offset:8
.LBB0_129:
s_or_b32 exec_lo, exec_lo, s7
s_waitcnt vmcnt(0)
global_load_b64 v[3:4], v[1:2], off offset:16
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, 0, v[3:4]
s_cbranch_vccnz .LBB0_131
; %bb.130:
global_load_b32 v1, v[1:2], off offset:24
v_mov_b32_e32 v2, 0
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s7, v1
s_waitcnt_vscnt null, 0x0
global_store_b64 v[3:4], v[1:2], off
s_and_b32 m0, s7, 0xff
s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_131: ; %Flow298
s_or_b32 exec_lo, exec_lo, s6
s_add_i32 s8, s8, s1
v_add_co_u32 v1, vcc_lo, v5, s9
v_add_co_ci_u32_e32 v2, vcc_lo, s8, v6, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v1, vcc_lo, v1, 20
v_add_co_ci_u32_e32 v2, vcc_lo, 0, v2, vcc_lo
.LBB0_132: ; =>This Inner Loop Header: Depth=1
v_mov_b32_e32 v3, 1
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_134
; %bb.133: ; in Loop: Header=BB0_132 Depth=1
global_load_b32 v3, v[1:2], off glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_and_b32_e32 v3, 1, v3
.LBB0_134: ; in Loop: Header=BB0_132 Depth=1
s_or_b32 exec_lo, exec_lo, s1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s1, v3
s_cmp_eq_u32 s1, 0
s_cbranch_scc1 .LBB0_136
; %bb.135: ; in Loop: Header=BB0_132 Depth=1
s_mov_b32 s1, 0
s_sleep 1
s_branch .LBB0_137
.LBB0_136: ; in Loop: Header=BB0_132 Depth=1
s_mov_b32 s1, -1
.LBB0_137: ; %Flow292
; in Loop: Header=BB0_132 Depth=1
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 vcc_lo, exec_lo, s1
s_cbranch_vccnz .LBB0_132
; %bb.138:
global_load_b128 v[3:6], v[7:8], off
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_142
; %bb.139:
v_mov_b32_e32 v9, 0
s_clause 0x2
global_load_b64 v[1:2], v9, s[2:3] offset:40
global_load_b64 v[10:11], v9, s[2:3] offset:24 glc
global_load_b64 v[7:8], v9, s[2:3]
s_waitcnt vmcnt(2)
v_add_co_u32 v12, vcc_lo, v1, 1
v_add_co_ci_u32_e32 v13, vcc_lo, 0, v2, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v5, vcc_lo, v12, s4
v_add_co_ci_u32_e32 v6, vcc_lo, s5, v13, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_eq_u64_e32 vcc_lo, 0, v[5:6]
v_dual_cndmask_b32 v6, v6, v13 :: v_dual_cndmask_b32 v5, v5, v12
v_and_b32_e32 v2, v6, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_and_b32_e32 v1, v5, v1
v_mul_lo_u32 v2, v2, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_hi_u32 v12, v1, 24
v_mul_lo_u32 v1, v1, 24
v_add_nc_u32_e32 v2, v12, v2
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_co_u32 v1, vcc_lo, v7, v1
v_mov_b32_e32 v7, v10
v_add_co_ci_u32_e32 v2, vcc_lo, v8, v2, vcc_lo
v_mov_b32_e32 v8, v11
global_store_b64 v[1:2], v[10:11], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[7:8], v9, v[5:8], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_ne_u64_e32 vcc_lo, v[7:8], v[10:11]
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_142
; %bb.140: ; %.preheader.i.i.i3.preheader
s_mov_b32 s0, 0
.LBB0_141: ; %.preheader.i.i.i3
; =>This Inner Loop Header: Depth=1
s_sleep 1
global_store_b64 v[1:2], v[7:8], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[10:11], v9, v[5:8], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[10:11], v[7:8]
v_dual_mov_b32 v7, v10 :: v_dual_mov_b32 v8, v11
s_or_b32 s0, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s0
s_cbranch_execnz .LBB0_141
.LBB0_142: ; %__ockl_hostcall_preview.exit.i
s_or_b32 exec_lo, exec_lo, s1
.LBB0_143: ; %__ockl_printf_append_string_n.exit
s_waitcnt vmcnt(0)
v_mov_b32_e32 v5, v31
v_mov_b32_e32 v1, 0
v_mov_b32_e32 v2, 0
;;#ASMSTART
;;#ASMEND
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s0, v5
v_cmp_eq_u32_e64 s0, s0, v5
s_delay_alu instid0(VALU_DEP_1)
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_149
; %bb.144:
v_mov_b32_e32 v6, 0
s_mov_b32 s4, exec_lo
global_load_b64 v[9:10], v6, s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
s_clause 0x1
global_load_b64 v[1:2], v6, s[2:3] offset:40
global_load_b64 v[7:8], v6, s[2:3]
s_waitcnt vmcnt(1)
v_and_b32_e32 v1, v1, v9
v_and_b32_e32 v2, v2, v10
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_hi_u32 v11, v1, 24
v_mul_lo_u32 v2, v2, 24
v_mul_lo_u32 v1, v1, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v2, v11, v2
s_waitcnt vmcnt(0)
v_add_co_u32 v1, vcc_lo, v7, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, v8, v2, vcc_lo
global_load_b64 v[7:8], v[1:2], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[1:2], v6, v[7:10], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmpx_ne_u64_e64 v[1:2], v[9:10]
s_cbranch_execz .LBB0_148
; %bb.145: ; %.preheader3.i.i.i13.preheader
s_mov_b32 s5, 0
.LBB0_146: ; %.preheader3.i.i.i13
; =>This Inner Loop Header: Depth=1
s_sleep 1
s_clause 0x1
global_load_b64 v[7:8], v6, s[2:3] offset:40
global_load_b64 v[11:12], v6, s[2:3]
v_dual_mov_b32 v10, v2 :: v_dual_mov_b32 v9, v1
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_and_b32_e32 v7, v7, v9
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[1:2], null, v7, 24, v[11:12]
v_and_b32_e32 v11, v8, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[7:8], null, v11, 24, v[2:3]
v_mov_b32_e32 v2, v7
global_load_b64 v[7:8], v[1:2], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[1:2], v6, v[7:10], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmp_eq_u64_e32 vcc_lo, v[1:2], v[9:10]
s_or_b32 s5, vcc_lo, s5
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s5
s_cbranch_execnz .LBB0_146
; %bb.147: ; %Flow235
s_or_b32 exec_lo, exec_lo, s5
.LBB0_148: ; %Flow237
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s4
.LBB0_149: ; %.loopexit4.i.i.i7
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s1
v_mov_b32_e32 v6, 0
v_readfirstlane_b32 s4, v1
v_readfirstlane_b32 s5, v2
s_mov_b32 s10, exec_lo
s_clause 0x1
global_load_b64 v[11:12], v6, s[2:3] offset:40
global_load_b128 v[7:10], v6, s[2:3]
s_waitcnt vmcnt(1)
v_readfirstlane_b32 s6, v11
v_readfirstlane_b32 s7, v12
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b64 s[6:7], s[4:5], s[6:7]
s_mul_i32 s1, s7, 24
s_mul_hi_u32 s8, s6, 24
s_mul_i32 s9, s6, 24
s_and_saveexec_b32 s11, s0
s_cbranch_execz .LBB0_151
; %bb.150:
v_dual_mov_b32 v11, s10 :: v_dual_mov_b32 v12, v6
s_add_i32 s10, s8, s1
s_waitcnt vmcnt(0)
v_add_co_u32 v1, vcc_lo, v7, s9
v_add_co_ci_u32_e32 v2, vcc_lo, s10, v8, vcc_lo
v_dual_mov_b32 v13, 2 :: v_dual_mov_b32 v14, 1
global_store_b128 v[1:2], v[11:14], off offset:8
.LBB0_151:
s_or_b32 exec_lo, exec_lo, s11
s_lshl_b64 s[6:7], s[6:7], 12
v_lshlrev_b64 v[1:2], 6, v[5:6]
s_waitcnt vmcnt(0)
v_add_co_u32 v5, vcc_lo, v9, s6
v_add_co_ci_u32_e32 v9, vcc_lo, s7, v10, vcc_lo
s_mov_b32 s12, 0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_u32 v1, vcc_lo, v5, v1
s_mov_b32 s13, s12
s_mov_b32 s14, s12
s_mov_b32 s15, s12
v_and_or_b32 v3, 0xffffff1d, v3, 34
v_add_co_ci_u32_e32 v2, vcc_lo, v9, v2, vcc_lo
v_mov_b32_e32 v5, v0
v_dual_mov_b32 v9, s12 :: v_dual_mov_b32 v12, s15
v_dual_mov_b32 v10, s13 :: v_dual_mov_b32 v11, s14
s_clause 0x3
global_store_b128 v[1:2], v[3:6], off
global_store_b128 v[1:2], v[9:12], off offset:16
global_store_b128 v[1:2], v[9:12], off offset:32
global_store_b128 v[1:2], v[9:12], off offset:48
s_and_saveexec_b32 s6, s0
s_cbranch_execz .LBB0_159
; %bb.152:
v_dual_mov_b32 v6, 0 :: v_dual_mov_b32 v9, s4
v_mov_b32_e32 v10, s5
s_clause 0x1
global_load_b64 v[11:12], v6, s[2:3] offset:32 glc
global_load_b64 v[0:1], v6, s[2:3] offset:40
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s10, v0
v_readfirstlane_b32 s11, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b64 s[10:11], s[10:11], s[4:5]
s_mul_i32 s7, s11, 24
s_mul_hi_u32 s11, s10, 24
s_mul_i32 s10, s10, 24
s_add_i32 s11, s11, s7
v_add_co_u32 v4, vcc_lo, v7, s10
v_add_co_ci_u32_e32 v5, vcc_lo, s11, v8, vcc_lo
s_mov_b32 s7, exec_lo
global_store_b64 v[4:5], v[11:12], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v6, v[9:12], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmpx_ne_u64_e64 v[2:3], v[11:12]
s_cbranch_execz .LBB0_155
; %bb.153: ; %.preheader1.i.i.i11.preheader
s_mov_b32 s10, 0
.LBB0_154: ; %.preheader1.i.i.i11
; =>This Inner Loop Header: Depth=1
v_dual_mov_b32 v0, s4 :: v_dual_mov_b32 v1, s5
s_sleep 1
global_store_b64 v[4:5], v[2:3], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[0:1], v6, v[0:3], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[0:1], v[2:3]
v_dual_mov_b32 v3, v1 :: v_dual_mov_b32 v2, v0
s_or_b32 s10, vcc_lo, s10
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s10
s_cbranch_execnz .LBB0_154
.LBB0_155: ; %Flow233
s_or_b32 exec_lo, exec_lo, s7
v_mov_b32_e32 v3, 0
s_mov_b32 s10, exec_lo
s_mov_b32 s7, exec_lo
v_mbcnt_lo_u32_b32 v2, s10, 0
global_load_b64 v[0:1], v3, s[2:3] offset:16
v_cmpx_eq_u32_e32 0, v2
s_cbranch_execz .LBB0_157
; %bb.156:
s_bcnt1_i32_b32 s10, s10
s_delay_alu instid0(SALU_CYCLE_1)
v_mov_b32_e32 v2, s10
s_waitcnt vmcnt(0)
global_atomic_add_u64 v[0:1], v[2:3], off offset:8
.LBB0_157:
s_or_b32 exec_lo, exec_lo, s7
s_waitcnt vmcnt(0)
global_load_b64 v[2:3], v[0:1], off offset:16
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, 0, v[2:3]
s_cbranch_vccnz .LBB0_159
; %bb.158:
global_load_b32 v0, v[0:1], off offset:24
v_mov_b32_e32 v1, 0
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s7, v0
s_waitcnt_vscnt null, 0x0
global_store_b64 v[2:3], v[0:1], off
s_and_b32 m0, s7, 0xff
s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_159: ; %Flow234
s_or_b32 exec_lo, exec_lo, s6
s_add_i32 s8, s8, s1
v_add_co_u32 v0, vcc_lo, v7, s9
v_add_co_ci_u32_e32 v1, vcc_lo, s8, v8, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v0, 20
v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
.LBB0_160: ; =>This Inner Loop Header: Depth=1
v_mov_b32_e32 v2, 1
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_162
; %bb.161: ; in Loop: Header=BB0_160 Depth=1
global_load_b32 v2, v[0:1], off glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_and_b32_e32 v2, 1, v2
.LBB0_162: ; in Loop: Header=BB0_160 Depth=1
s_or_b32 exec_lo, exec_lo, s1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s1, v2
s_cmp_eq_u32 s1, 0
s_cbranch_scc1 .LBB0_164
; %bb.163: ; in Loop: Header=BB0_160 Depth=1
s_mov_b32 s1, 0
s_sleep 1
s_branch .LBB0_165
.LBB0_164: ; in Loop: Header=BB0_160 Depth=1
s_mov_b32 s1, -1
.LBB0_165: ; %Flow228
; in Loop: Header=BB0_160 Depth=1
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 vcc_lo, exec_lo, s1
s_cbranch_vccnz .LBB0_160
; %bb.166:
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_170
; %bb.167:
v_mov_b32_e32 v6, 0
s_clause 0x2
global_load_b64 v[2:3], v6, s[2:3] offset:40
global_load_b64 v[7:8], v6, s[2:3] offset:24 glc
global_load_b64 v[4:5], v6, s[2:3]
s_waitcnt vmcnt(2)
v_add_co_u32 v9, vcc_lo, v2, 1
v_add_co_ci_u32_e32 v10, vcc_lo, 0, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v9, s4
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v10, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_eq_u64_e32 vcc_lo, 0, v[0:1]
v_dual_cndmask_b32 v1, v1, v10 :: v_dual_cndmask_b32 v0, v0, v9
v_and_b32_e32 v3, v1, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_and_b32_e32 v2, v0, v2
v_mul_lo_u32 v3, v3, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_hi_u32 v9, v2, 24
v_mul_lo_u32 v2, v2, 24
v_add_nc_u32_e32 v3, v9, v3
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_co_u32 v4, vcc_lo, v4, v2
v_mov_b32_e32 v2, v7
v_add_co_ci_u32_e32 v5, vcc_lo, v5, v3, vcc_lo
v_mov_b32_e32 v3, v8
global_store_b64 v[4:5], v[7:8], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v6, v[0:3], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_ne_u64_e32 vcc_lo, v[2:3], v[7:8]
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_170
; %bb.168: ; %.preheader.i.i.i10.preheader
s_mov_b32 s0, 0
.LBB0_169: ; %.preheader.i.i.i10
; =>This Inner Loop Header: Depth=1
s_sleep 1
global_store_b64 v[4:5], v[2:3], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[7:8], v6, v[0:3], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[7:8], v[2:3]
v_dual_mov_b32 v2, v7 :: v_dual_mov_b32 v3, v8
s_or_b32 s0, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s0
s_cbranch_execnz .LBB0_169
.LBB0_170: ; %__ockl_printf_append_args.exit
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z5printv
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 256
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 33
.amdhsa_next_free_sgpr 18
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z5printv, .Lfunc_end0-_Z5printv
; -- End function
.section .AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 6672
; NumSgprs: 20
; NumVgprs: 33
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 4
; NumSGPRsForWavesPerEU: 20
; NumVGPRsForWavesPerEU: 33
; Occupancy: 16
; WaveLimiterHint : 1
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type .str,@object ; @.str
.section .rodata.str1.1,"aMS",@progbits,1
.str:
.asciz "%d\n"
.size .str, 4
.type __hip_cuid_,@object ; @__hip_cuid_
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0 ; 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: hidden_block_count_x
- .offset: 4
.size: 4
.value_kind: hidden_block_count_y
- .offset: 8
.size: 4
.value_kind: hidden_block_count_z
- .offset: 12
.size: 2
.value_kind: hidden_group_size_x
- .offset: 14
.size: 2
.value_kind: hidden_group_size_y
- .offset: 16
.size: 2
.value_kind: hidden_group_size_z
- .offset: 18
.size: 2
.value_kind: hidden_remainder_x
- .offset: 20
.size: 2
.value_kind: hidden_remainder_y
- .offset: 22
.size: 2
.value_kind: hidden_remainder_z
- .offset: 40
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 48
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 64
.size: 2
.value_kind: hidden_grid_dims
- .offset: 80
.size: 8
.value_kind: hidden_hostcall_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 256
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z5printv
.private_segment_fixed_size: 0
.sgpr_count: 20
.sgpr_spill_count: 0
.symbol: _Z5printv.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 33
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
```
| 402 | 29,052 |
115 |
Convert the following CUDA host assembly code to AMD host assembly:
```cudaasm
.file "tmpxft_00190aa8_00000000-6_first_cuda.cudafe1.cpp"
.text
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z23__device_stub__Z5printvv
.type _Z23__device_stub__Z5printvv, @function
_Z23__device_stub__Z5printvv:
.LFB2082:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z5printv(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z23__device_stub__Z5printvv, .-_Z23__device_stub__Z5printvv
.globl _Z5printv
.type _Z5printv, @function
_Z5printv:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z23__device_stub__Z5printvv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z5printv, .-_Z5printv
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
movl $4, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L14
.L12:
call cudaDeviceSynchronize@PLT
call cudaDeviceReset@PLT
movl $0, %eax
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
call _Z23__device_stub__Z5printvv
jmp .L12
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z5printv"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z5printv(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
```
|
```amdasm
.text
.file "first_cuda.hip"
.globl _Z20__device_stub__printv # -- Begin function _Z20__device_stub__printv
.type _Z20__device_stub__printv,@function
_Z20__device_stub__printv: # @_Z20__device_stub__printv
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $56, %rsp
.cfi_def_cfa_offset 96
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 40(%rsp), %rbx
leaq 24(%rsp), %r14
leaq 16(%rsp), %r15
leaq 8(%rsp), %r12
movq %rbx, %rdi
movq %r14, %rsi
movq %r15, %rdx
movq %r12, %rcx
callq __hipPopCallConfiguration
movq (%rbx), %rsi
movl 8(%rbx), %edx
movq (%r14), %rcx
movl 8(%r14), %r8d
movq %rsp, %r9
movl $_Z5printv, %edi
pushq (%r12)
.cfi_adjust_cfa_offset 8
pushq (%r15)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z20__device_stub__printv, .Lfunc_end0-_Z20__device_stub__printv
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 3(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
callq _Z20__device_stub__printv
.LBB1_2:
callq hipDeviceSynchronize
callq hipDeviceReset
xorl %eax, %eax
popq %rcx
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, %rdi
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z5printv, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z5printv,@object # @_Z5printv
.section .rodata,"a",@progbits
.globl _Z5printv
.p2align 3, 0x0
_Z5printv:
.quad _Z20__device_stub__printv
.size _Z5printv, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z5printv"
.size .L__unnamed_1, 10
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z20__device_stub__printv
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z5printv
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
```
| 1,931 | 2,042 |
118 |
Convert the following CUDA device assembly code to AMD device assembly:
```cudaasm
code for sm_80
Function : _Z14matrix_productPiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
MOV R1, c[0x0][0x28] ;
S2R R7, SR_CTAID.Y ;
HFMA2.MMA R6, -RZ, RZ, 0, 0 ;
MOV R15, RZ ;
ULDC.64 UR4, c[0x0][0x118] ;
S2R R2, SR_TID.Y ;
ULDC.64 UR8, c[0x0][0x168] ;
ULDC.64 UR6, c[0x0][0x160] ;
S2R R0, SR_CTAID.X ;
S2R R3, SR_TID.X ;
LEA R7, R7, R2, 0x5 ;
SHF.L.U32 R8, R7, 0xa, RZ ;
LEA R0, R0, R3, 0x5 ;
MOV R4, UR6 ;
MOV R5, UR7 ;
MOV R2, UR8 ;
MOV R3, UR9 ;
IMAD.WIDE R4, R8, 0x4, R4 ;
IMAD.WIDE R2, R0, 0x4, R2 ;
LDG.E R17, [R4.64] ;
LDG.E R16, [R2.64] ;
LDG.E R18, [R2.64+0x1000] ;
LDG.E R25, [R4.64+0x4] ;
LDG.E R19, [R2.64+0x2000] ;
LDG.E R20, [R4.64+0x8] ;
LDG.E R22, [R2.64+0x3000] ;
LDG.E R21, [R4.64+0xc] ;
LDG.E R23, [R2.64+0x4000] ;
LDG.E R24, [R4.64+0x10] ;
LDG.E R9, [R2.64+0x5000] ;
LDG.E R10, [R4.64+0x14] ;
LDG.E R11, [R2.64+0x6000] ;
LDG.E R12, [R4.64+0x18] ;
LDG.E R13, [R2.64+0x7000] ;
LDG.E R14, [R4.64+0x1c] ;
LDG.E R28, [R4.64+0x38] ;
LDG.E R26, [R2.64+0xf000] ;
LDG.E R27, [R4.64+0x3c] ;
IMAD R17, R16, R17, R15 ;
LDG.E R15, [R2.64+0x8000] ;
LDG.E R16, [R4.64+0x20] ;
IMAD R25, R18, R25, R17 ;
LDG.E R17, [R2.64+0x9000] ;
LDG.E R18, [R4.64+0x24] ;
IMAD R25, R19, R20, R25 ;
LDG.E R19, [R2.64+0xa000] ;
LDG.E R20, [R4.64+0x28] ;
IMAD R25, R22, R21, R25 ;
LDG.E R21, [R2.64+0xb000] ;
LDG.E R22, [R4.64+0x2c] ;
IMAD R25, R23, R24, R25 ;
LDG.E R23, [R2.64+0xc000] ;
LDG.E R24, [R4.64+0x30] ;
IMAD R29, R9, R10, R25 ;
LDG.E R10, [R2.64+0xd000] ;
LDG.E R25, [R4.64+0x34] ;
LDG.E R9, [R2.64+0xe000] ;
IMAD R11, R11, R12, R29 ;
IMAD R11, R13, R14, R11 ;
IADD3 R6, R6, 0x10, RZ ;
ISETP.NE.AND P0, PT, R6, 0x400, PT ;
UIADD3 UR8, UP0, UR8, 0x10000, URZ ;
UIADD3 UR6, UP1, UR6, 0x40, URZ ;
UIADD3.X UR9, URZ, UR9, URZ, UP0, !UPT ;
UIADD3.X UR7, URZ, UR7, URZ, UP1, !UPT ;
IMAD R11, R15, R16, R11 ;
IMAD R11, R17, R18, R11 ;
IMAD R11, R19, R20, R11 ;
IMAD R11, R21, R22, R11 ;
IMAD R11, R23, R24, R11 ;
IMAD R10, R10, R25, R11 ;
IMAD R9, R9, R28, R10 ;
IMAD R15, R26, R27, R9 ;
@P0 BRA 0xd0 ;
HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ;
LEA R2, R7, R0, 0xa ;
IMAD.WIDE R2, R2, R3, c[0x0][0x170] ;
STG.E [R2.64], R15 ;
EXIT ;
BRA 0x4f0;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
```
|
```amdasm
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z14matrix_productPiS_S_ ; -- Begin function _Z14matrix_productPiS_S_
.globl _Z14matrix_productPiS_S_
.p2align 8
.type _Z14matrix_productPiS_S_,@function
_Z14matrix_productPiS_S_: ; @_Z14matrix_productPiS_S_
; %bb.0:
v_and_b32_e32 v1, 0xffc00, v0
s_load_b128 s[4:7], s[0:1], 0x0
v_and_b32_e32 v4, 0x3ff, v0
v_mov_b32_e32 v0, 0
s_load_b64 s[0:1], s[0:1], 0x10
v_lshl_add_u32 v1, s15, 15, v1
s_mov_b64 s[2:3], 0
v_lshl_add_u32 v5, s14, 5, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b64 v[2:3], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v6, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v7, vcc_lo, s5, v3, vcc_lo
v_mov_b32_e32 v2, v5
.LBB0_1: ; =>This Inner Loop Header: Depth=1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
v_ashrrev_i32_e32 v3, 31, v2
v_add_co_u32 v8, vcc_lo, v6, s2
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e32 v9, vcc_lo, s3, v7, vcc_lo
v_lshlrev_b64 v[3:4], 2, v[2:3]
v_add_nc_u32_e32 v2, 0x400, v2
s_add_u32 s2, s2, 4
s_addc_u32 s3, s3, 0
s_cmpk_lg_i32 s2, 0x1000
s_delay_alu instid0(VALU_DEP_2)
v_add_co_u32 v3, vcc_lo, s6, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s7, v4, vcc_lo
global_load_b32 v8, v[8:9], off
global_load_b32 v9, v[3:4], off
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[3:4], null, v9, v8, v[0:1]
s_delay_alu instid0(VALU_DEP_1)
v_mov_b32_e32 v0, v3
s_cbranch_scc1 .LBB0_1
; %bb.2:
v_add_nc_u32_e32 v0, v1, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v1, 31, v0
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v3, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z14matrix_productPiS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 10
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z14matrix_productPiS_S_, .Lfunc_end0-_Z14matrix_productPiS_S_
; -- End function
.section .AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 260
; NumSgprs: 18
; NumVgprs: 10
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 10
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object ; @__hip_cuid_
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0 ; 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z14matrix_productPiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z14matrix_productPiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 10
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
```
| 1,535 | 2,571 |
119 |
Convert the following CUDA host assembly code to AMD host assembly:
```cudaasm
.file "tmpxft_00143726_00000000-6_matrix_product.cudafe1.cpp"
.text
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z38__device_stub__Z14matrix_productPiS_S_PiS_S_
.type _Z38__device_stub__Z14matrix_productPiS_S_PiS_S_, @function
_Z38__device_stub__Z14matrix_productPiS_S_PiS_S_:
.LFB2082:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z14matrix_productPiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z38__device_stub__Z14matrix_productPiS_S_PiS_S_, .-_Z38__device_stub__Z14matrix_productPiS_S_PiS_S_
.globl _Z14matrix_productPiS_S_
.type _Z14matrix_productPiS_S_, @function
_Z14matrix_productPiS_S_:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z38__device_stub__Z14matrix_productPiS_S_PiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z14matrix_productPiS_S_, .-_Z14matrix_productPiS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "OK\n"
.LC1:
.string "NG\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $64, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl $4194304, %edi
call malloc@PLT
movq %rax, %rbp
movl $4194304, %edi
call malloc@PLT
movq %rax, %rbx
movl $4194304, %edi
call malloc@PLT
movq %rax, %r12
leaq 8(%rsp), %rdi
movl $4194304, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $4194304, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $4194304, %esi
call cudaMalloc@PLT
movl $0, %eax
.L12:
movl $1, (%rbx,%rax)
movl $1, 0(%rbp,%rax)
addq $4, %rax
cmpq $4194304, %rax
jne .L12
movl $1, %ecx
movl $4194304, %edx
movq %rbp, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $4194304, %edx
movq %rbx, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $4194304, %edx
movl $0, %esi
movq 24(%rsp), %rdi
call cudaMemset@PLT
movl $32, 32(%rsp)
movl $32, 36(%rsp)
movl $32, 44(%rsp)
movl $32, 48(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L27
.L13:
movl $2, %ecx
movl $4194304, %edx
movq 24(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
movl $0, %r14d
movl $0, %r9d
movl $1, %r11d
.L14:
leaq 4194304(%rbx), %rdi
movq %r14, %r10
salq $12, %r10
leaq 0(%rbp,%r10), %r13
addq %r12, %r10
movl $0, %r8d
.L19:
leaq -4194304(%rdi), %rax
movq %r13, %rcx
movl $0, %esi
.L15:
movl (%rcx), %edx
imull (%rax), %edx
addl %edx, %esi
addq $4, %rcx
addq $4096, %rax
cmpq %rdi, %rax
jne .L15
cmpl %esi, (%r10,%r8,4)
cmovne %r11d, %r9d
addq $1, %r8
addq $4, %rdi
cmpq $1024, %r8
jne .L19
addq $1, %r14
cmpq $1024, %r14
jne .L14
testl %r9d, %r9d
jne .L20
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
.L21:
movq %rbp, %rdi
call free@PLT
movq %rbx, %rdi
call free@PLT
movq %r12, %rdi
call free@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L28
movl $0, %eax
addq $64, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L27:
.cfi_restore_state
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z38__device_stub__Z14matrix_productPiS_S_PiS_S_
jmp .L13
.L20:
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L21
.L28:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC2:
.string "_Z14matrix_productPiS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z14matrix_productPiS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
```
|
```amdasm
.text
.file "matrix_product.hip"
.globl _Z29__device_stub__matrix_productPiS_S_ # -- Begin function _Z29__device_stub__matrix_productPiS_S_
.type _Z29__device_stub__matrix_productPiS_S_,@function
_Z29__device_stub__matrix_productPiS_S_: # @_Z29__device_stub__matrix_productPiS_S_
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $112, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 40(%rsp), %rax
movq %rdi, (%rax)
leaq 32(%rsp), %rcx
movq %rsi, (%rcx)
leaq 24(%rsp), %rsi
movq %rdx, (%rsi)
leaq 80(%rsp), %rbx
movq %rax, (%rbx)
movq %rcx, 8(%rbx)
movq %rsi, 16(%rbx)
leaq 64(%rsp), %r14
leaq 48(%rsp), %r15
leaq 16(%rsp), %r12
leaq 8(%rsp), %r13
movq %r14, %rdi
movq %r15, %rsi
movq %r12, %rdx
movq %r13, %rcx
callq __hipPopCallConfiguration
movq (%r14), %rsi
movl 8(%r14), %edx
movq (%r15), %rcx
movl 8(%r15), %r8d
movl $_Z14matrix_productPiS_S_, %edi
movq %rbx, %r9
pushq (%r13)
.cfi_adjust_cfa_offset 8
pushq (%r12)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $128, %rsp
.cfi_adjust_cfa_offset -128
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z29__device_stub__matrix_productPiS_S_, .Lfunc_end0-_Z29__device_stub__matrix_productPiS_S_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $32, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $4194304, %edi # imm = 0x400000
callq malloc
movq %rax, %rbx
movl $4194304, %edi # imm = 0x400000
callq malloc
movq %rax, %r14
movl $4194304, %edi # imm = 0x400000
callq malloc
movq %rax, %r15
leaq 24(%rsp), %rdi
movl $4194304, %esi # imm = 0x400000
callq hipMalloc
leaq 16(%rsp), %rdi
movl $4194304, %esi # imm = 0x400000
callq hipMalloc
leaq 8(%rsp), %rdi
movl $4194304, %esi # imm = 0x400000
callq hipMalloc
xorl %eax, %eax
movl $1, %ecx
.LBB1_1: # =>This Inner Loop Header: Depth=1
movl %ecx, (%r14,%rax,4)
movl %ecx, (%rbx,%rax,4)
incq %rax
cmpq $1048576, %rax # imm = 0x100000
jne .LBB1_1
# %bb.2:
movq 24(%rsp), %rdi
movl $1, %ebp
movl $4194304, %edx # imm = 0x400000
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
movl $4194304, %edx # imm = 0x400000
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
xorl %r12d, %r12d
movl $4194304, %edx # imm = 0x400000
xorl %esi, %esi
callq hipMemset
movabsq $137438953504, %rdi # imm = 0x2000000020
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq 24(%rsp), %rdi
movq 16(%rsp), %rsi
movq 8(%rsp), %rdx
callq _Z29__device_stub__matrix_productPiS_S_
.LBB1_4:
movq 8(%rsp), %rsi
movl $4194304, %edx # imm = 0x400000
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
movq %rbx, %rax
xorl %ecx, %ecx
.LBB1_5: # %.preheader45
# =>This Loop Header: Depth=1
# Child Loop BB1_6 Depth 2
# Child Loop BB1_7 Depth 3
movq %rcx, %rdx
shlq $12, %rdx
addq %r15, %rdx
movq %r14, %rsi
xorl %edi, %edi
.LBB1_6: # %.preheader
# Parent Loop BB1_5 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB1_7 Depth 3
xorl %r8d, %r8d
movq %rsi, %r9
xorl %r10d, %r10d
.LBB1_7: # Parent Loop BB1_5 Depth=1
# Parent Loop BB1_6 Depth=2
# => This Inner Loop Header: Depth=3
movl (%r9), %r11d
imull (%rax,%r8,4), %r11d
addl %r11d, %r10d
incq %r8
addq $4096, %r9 # imm = 0x1000
cmpq $1024, %r8 # imm = 0x400
jne .LBB1_7
# %bb.8: # in Loop: Header=BB1_6 Depth=2
cmpl %r10d, (%rdx,%rdi,4)
cmovnel %ebp, %r12d
incq %rdi
addq $4, %rsi
cmpq $1024, %rdi # imm = 0x400
jne .LBB1_6
# %bb.9: # in Loop: Header=BB1_5 Depth=1
incq %rcx
addq $4096, %rax # imm = 0x1000
cmpq $1024, %rcx # imm = 0x400
jne .LBB1_5
# %bb.10:
testl %r12d, %r12d
movl $.Lstr.1, %eax
movl $.Lstr, %edi
cmoveq %rax, %rdi
callq puts@PLT
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $32, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, %rdi
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z14matrix_productPiS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z14matrix_productPiS_S_,@object # @_Z14matrix_productPiS_S_
.section .rodata,"a",@progbits
.globl _Z14matrix_productPiS_S_
.p2align 3, 0x0
_Z14matrix_productPiS_S_:
.quad _Z29__device_stub__matrix_productPiS_S_
.size _Z14matrix_productPiS_S_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z14matrix_productPiS_S_"
.size .L__unnamed_1, 25
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "NG"
.size .Lstr, 3
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "OK"
.size .Lstr.1, 3
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z29__device_stub__matrix_productPiS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z14matrix_productPiS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
```
| 3,581 | 4,051 |
120 |
Convert the following CUDA device assembly code to AMD device assembly:
```cudaasm
code for sm_80
```
|
```amdasm
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object ; @__hip_cuid_
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0 ; 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
```
| 24 | 306 |
121 |
Convert the following CUDA host assembly code to AMD host assembly:
```cudaasm
.file "tmpxft_001524fd_00000000-6_brick_sort.cudafe1.cpp"
.text
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2030:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2053:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2053:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
```
|
```amdasm
.text
.file "brick_sort.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
```
| 747 | 184 |
122 |
Convert the following CUDA device assembly code to AMD device assembly:
```cudaasm
code for sm_80
Function : kernel
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
MOV R1, c[0x0][0x28] ;
S2R R2, SR_TID.X ;
S2R R3, SR_CTAID.X ;
IMAD R2, R3, c[0x0][0x0], R2 ;
ISETP.GE.AND P0, PT, R2, c[0x0][0x168], PT ;
@P0 EXIT ;
HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ;
ULDC.64 UR4, c[0x0][0x118] ;
IMAD.WIDE R2, R2, R3, c[0x0][0x160] ;
LDG.E R0, [R2.64] ;
MOV R4, 0xc0 ;
CALL.REL.NOINC 0xe0 ;
STG.E [R2.64], R7 ;
EXIT ;
HFMA2.MMA R5, -RZ, RZ, 0, 0 ;
FMUL R7, R0, R0 ;
RET.REL.NODEC R4 0x0 ;
BRA 0x110;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
```
|
```amdasm
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.p2align 2 ; -- Begin function square
.type square,@function
square: ; @square
; %bb.0:
s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
v_mul_f32_e32 v0, v0, v0
s_setpc_b64 s[30:31]
.Lfunc_end0:
.size square, .Lfunc_end0-square
; -- End function
.section .AMDGPU.csdata,"",@progbits
; Function info:
; codeLenInByte = 12
; NumSgprs: 32
; NumVgprs: 1
; ScratchSize: 0
; MemoryBound: 0
.text
.protected kernel ; -- Begin function kernel
.globl kernel
.p2align 8
.type kernel,@function
kernel: ; @kernel
; %bb.0:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x1c
s_load_b32 s3, s[0:1], 0x8
s_mov_b32 s32, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB1_2
; %bb.1:
s_load_b64 s[0:1], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v1, vcc_lo
s_getpc_b64 s[0:1]
s_add_u32 s0, s0, square@rel32@lo+4
s_addc_u32 s1, s1, square@rel32@hi+12
global_load_b32 v0, v[2:3], off
s_swappc_b64 s[30:31], s[0:1]
global_store_b32 v[2:3], v0, off
.LBB1_2:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel kernel
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 33
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size kernel, .Lfunc_end1-kernel
; -- End function
.section .AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 152
; NumSgprs: 35
; NumVgprs: 4
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 4
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 35
; NumVGPRsForWavesPerEU: 4
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object ; @__hip_cuid_
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0 ; 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: kernel
.private_segment_fixed_size: 0
.sgpr_count: 35
.sgpr_spill_count: 0
.symbol: kernel.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
```
| 372 | 2,503 |
123 |
Convert the following CUDA host assembly code to AMD host assembly:
```cudaasm
.file "tmpxft_0000f90b_00000000-6_simpleFunc.cudafe1.cpp"
.text
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl square
.type square, @function
square:
.LFB2057:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2057:
.size square, .-square
.globl _Z26__device_stub__Z6kernelPfiPfi
.type _Z26__device_stub__Z6kernelPfiPfi, @function
_Z26__device_stub__Z6kernelPfiPfi:
.LFB2083:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L9
.L5:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L10
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L9:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq kernel(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L5
.L10:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z26__device_stub__Z6kernelPfiPfi, .-_Z26__device_stub__Z6kernelPfiPfi
.globl kernel
.type kernel, @function
kernel:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z6kernelPfiPfi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size kernel, .-kernel
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Fail"
.LC1:
.string "Pass"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC4:
.string "Error[ %d ] - expected %f, got %f\n"
.section .rodata.str1.1
.LC5:
.string "Pass/Fail : %s\n"
.text
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $56, %rsp
.cfi_def_cfa_offset 80
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movl $128, %edi
call malloc@PLT
movq %rax, %rbx
leaq 8(%rsp), %rdi
movl $128, %esi
call cudaMalloc@PLT
movl $32, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $0, %eax
.L14:
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movss %xmm0, (%rbx,%rax,4)
addq $1, %rax
cmpq $32, %rax
jne .L14
movl $1, %ecx
movl $128, %edx
movq %rbx, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl 24(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 16(%rsp), %rdx
movq 28(%rsp), %rdi
movl 36(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L26
.L15:
call cudaThreadSynchronize@PLT
movl $2, %ecx
movl $128, %edx
movq 8(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
movl $0, %eax
movl $0, %ebp
movss .LC2(%rip), %xmm4
movsd .LC3(%rip), %xmm3
jmp .L19
.L26:
movl $32, %esi
movq 8(%rsp), %rdi
call _Z26__device_stub__Z6kernelPfiPfi
jmp .L15
.L16:
addq $1, %rax
cmpq $32, %rax
je .L27
.L19:
movl %eax, %edx
movss (%rbx,%rax,4), %xmm1
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movaps %xmm0, %xmm2
mulss %xmm0, %xmm2
movaps %xmm1, %xmm0
subss %xmm2, %xmm0
andps %xmm4, %xmm0
cvtss2sd %xmm0, %xmm0
comisd %xmm3, %xmm0
jbe .L16
addl $1, %ebp
cmpl $4, %ebp
jle .L16
pxor %xmm0, %xmm0
cvtss2sd %xmm2, %xmm0
cvtss2sd %xmm1, %xmm1
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $2, %eax
call __printf_chk@PLT
movq %rbx, %rdi
call free@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
leaq .LC0(%rip), %rdx
jmp .L18
.L27:
movq %rbx, %rdi
call free@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
testl %ebp, %ebp
leaq .LC1(%rip), %rdx
leaq .LC0(%rip), %rax
cmovne %rax, %rdx
.L18:
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L28
movl $0, %eax
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L28:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.1
.LC6:
.string "kernel"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq kernel(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst16,"aM",@progbits,16
.align 16
.LC2:
.long 2147483647
.long 0
.long 0
.long 0
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC3:
.long -755914244
.long 1062232653
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
```
|
```amdasm
.text
.file "simpleFunc.hip"
.globl __device_stub__kernel # -- Begin function __device_stub__kernel
.type __device_stub__kernel,@function
__device_stub__kernel: # @__device_stub__kernel
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $80, %rsp
.cfi_def_cfa_offset 128
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 24(%rsp), %rax
movq %rdi, (%rax)
leaq 4(%rsp), %rcx
movl %esi, (%rcx)
leaq 64(%rsp), %rbx
movq %rax, (%rbx)
movq %rcx, 8(%rbx)
leaq 48(%rsp), %r14
leaq 32(%rsp), %r15
leaq 16(%rsp), %r12
leaq 8(%rsp), %r13
movq %r14, %rdi
movq %r15, %rsi
movq %r12, %rdx
movq %r13, %rcx
callq __hipPopCallConfiguration
movq (%r14), %rsi
movl 8(%r14), %edx
movq (%r15), %rcx
movl 8(%r15), %r8d
movl $kernel, %edi
movq %rbx, %r9
pushq (%r13)
.cfi_adjust_cfa_offset 8
pushq (%r12)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $96, %rsp
.cfi_adjust_cfa_offset -96
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size __device_stub__kernel, .Lfunc_end0-__device_stub__kernel
.cfi_endproc
# -- End function
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0 # -- Begin function main
.LCPI1_0:
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0
.LCPI1_1:
.quad 0x3f50624dd2f1a9fc # double 0.001
.text
.globl main
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $16, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %rbp, -16
movl $128, %edi
callq malloc
movq %rax, %rbx
leaq 8(%rsp), %rdi
movl $128, %esi
callq hipMalloc
xorl %eax, %eax
.LBB1_1: # =>This Inner Loop Header: Depth=1
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movss %xmm0, (%rbx,%rax,4)
incq %rax
cmpq $32, %rax
jne .LBB1_1
# %bb.2:
movq 8(%rsp), %rdi
movl $128, %edx
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 31(%rdi), %rdx
xorl %r14d, %r14d
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq 8(%rsp), %rdi
movl $32, %esi
callq __device_stub__kernel
.LBB1_4:
callq hipDeviceSynchronize
movq 8(%rsp), %rsi
movl $128, %edx
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
movaps .LCPI1_0(%rip), %xmm0 # xmm0 = [NaN,NaN,NaN,NaN]
movsd .LCPI1_1(%rip), %xmm1 # xmm1 = mem[0],zero
xorl %esi, %esi
.LBB1_5: # =>This Inner Loop Header: Depth=1
xorps %xmm3, %xmm3
cvtsi2ss %esi, %xmm3
movss (%rbx,%rsi,4), %xmm2 # xmm2 = mem[0],zero,zero,zero
mulss %xmm3, %xmm3
movaps %xmm2, %xmm4
subss %xmm3, %xmm4
andps %xmm0, %xmm4
cvtss2sd %xmm4, %xmm4
ucomisd %xmm1, %xmm4
jbe .LBB1_8
# %bb.6: # in Loop: Header=BB1_5 Depth=1
leal 1(%r14), %ebp
cmpl $4, %r14d
jge .LBB1_10
# %bb.7: # in Loop: Header=BB1_5 Depth=1
movl %ebp, %r14d
.LBB1_8: # in Loop: Header=BB1_5 Depth=1
incq %rsi
cmpq $32, %rsi
jne .LBB1_5
jmp .LBB1_9
.LBB1_10:
xorps %xmm0, %xmm0
cvtss2sd %xmm3, %xmm0
xorps %xmm1, %xmm1
cvtss2sd %xmm2, %xmm1
movl $.L.str, %edi
# kill: def $esi killed $esi killed $rsi
movb $2, %al
callq printf
movl %ebp, %r14d
.LBB1_9: # %.loopexit
movq %rbx, %rdi
callq free
movq 8(%rsp), %rdi
callq hipFree
testl %r14d, %r14d
movl $.L.str.3, %eax
movl $.L.str.2, %esi
cmoveq %rax, %rsi
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
xorl %eax, %eax
addq $16, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, %rdi
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $kernel, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type kernel,@object # @kernel
.section .rodata,"a",@progbits
.globl kernel
.p2align 3, 0x0
kernel:
.quad __device_stub__kernel
.size kernel, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Error[ %d ] - expected %f, got %f\n"
.size .L.str, 35
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Pass/Fail : %s\n"
.size .L.str.1, 16
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Fail"
.size .L.str.2, 5
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Pass"
.size .L.str.3, 5
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "kernel"
.size .L__unnamed_1, 7
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __device_stub__kernel
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym kernel
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
```
| 3,342 | 3,475 |
128 |
Convert the following CUDA device assembly code to AMD device assembly:
```cudaasm
code for sm_80
Function : _Z13voronoiKernelPiiiiS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ;
S2R R2, SR_CTAID.Y ;
ULDC.64 UR8, c[0x0][0x180] ;
ULDC.64 UR6, c[0x0][0x178] ;
S2R R5, SR_TID.Y ;
S2R R3, SR_CTAID.X ;
S2R R0, SR_TID.X ;
IMAD R2, R2, c[0x0][0x4], R5 ;
BAR.SYNC.DEFER_BLOCKING 0x0 ;
ISETP.GE.AND P0, PT, R2, c[0x0][0x16c], PT ;
IMAD R3, R3, c[0x0][0x0], R0 ;
ISETP.GE.OR P0, PT, R3, c[0x0][0x168], P0 ;
@P0 EXIT ;
IMAD.U32 R8, RZ, RZ, UR6 ;
ULDC.64 UR4, c[0x0][0x118] ;
IMAD.U32 R9, RZ, RZ, UR7 ;
LDG.E R4, [R8.64] ;
IMAD.U32 R11, RZ, RZ, UR9 ;
IMAD.U32 R10, RZ, RZ, UR8 ;
LDG.E R11, [R10.64] ;
BSSY B0, 0x1b0 ;
MOV R0, 0x1a0 ;
IMAD.IADD R4, R3, 0x1, -R4 ;
I2F.F64 R6, R4 ;
DADD R14, -RZ, |R6| ;
CALL.REL.NOINC 0x1030 ;
BSYNC B0 ;
DADD R8, R6, 2 ;
ISETP.NE.AND P0, PT, R4, RZ, PT ;
BSSY B0, 0x2f0 ;
LOP3.LUT R8, R9, 0x7ff00000, RZ, 0xc0, !PT ;
IMAD.MOV.U32 R9, RZ, RZ, R19 ;
ISETP.NE.AND P1, PT, R8, 0x7ff00000, PT ;
IMAD.MOV.U32 R8, RZ, RZ, R18 ;
@!P0 CS2R R8, SRZ ;
@P1 BRA 0x2e0 ;
DSETP.GTU.AND P0, PT, |R6|, +INF , PT ;
@P0 BRA 0x2d0 ;
ISETP.NE.AND P0, PT, R6, RZ, PT ;
LOP3.LUT R6, R7, 0x7fffffff, RZ, 0xc0, !PT ;
ISETP.NE.OR P0, PT, R6, 0x7ff00000, P0 ;
@P0 BRA 0x2e0 ;
IMAD.MOV.U32 R8, RZ, RZ, 0x0 ;
IMAD.MOV.U32 R9, RZ, RZ, 0x7ff00000 ;
BRA 0x2e0 ;
DADD R8, R6, 2 ;
BSYNC B0 ;
IMAD.IADD R10, R2, 0x1, -R11 ;
BSSY B0, 0x360 ;
MOV R0, 0x350 ;
I2F.F64 R6, R10 ;
DADD R14, -RZ, |R6| ;
CALL.REL.NOINC 0x1030 ;
BSYNC B0 ;
DADD R12, R6, 2 ;
ISETP.NE.AND P1, PT, R10, RZ, PT ;
BSSY B0, 0x4b0 ;
ISETP.NE.AND P0, PT, R4, 0x1, PT ;
FSEL R4, R8, RZ, P0 ;
FSEL R5, R9, 1.875, P0 ;
LOP3.LUT R12, R13, 0x7ff00000, RZ, 0xc0, !PT ;
@!P1 CS2R R18, SRZ ;
ISETP.NE.AND P2, PT, R12, 0x7ff00000, PT ;
@P2 BRA 0x4a0 ;
DSETP.GTU.AND P0, PT, |R6|, +INF , PT ;
@P0 BRA 0x490 ;
ISETP.NE.AND P0, PT, R6, RZ, PT ;
LOP3.LUT R6, R7, 0x7fffffff, RZ, 0xc0, !PT ;
ISETP.NE.OR P0, PT, R6, 0x7ff00000, P0 ;
@P0 BRA 0x4a0 ;
IMAD.MOV.U32 R18, RZ, RZ, 0x0 ;
IMAD.MOV.U32 R19, RZ, RZ, 0x7ff00000 ;
BRA 0x4a0 ;
DADD R18, R6, 2 ;
BSYNC B0 ;
BAR.SYNC.DEFER_BLOCKING 0x0 ;
IMAD R0, R2, c[0x0][0x170], RZ ;
ISETP.NE.AND P0, PT, R10, 0x1, PT ;
IMAD.MOV.U32 R8, RZ, RZ, c[0x0][0x188] ;
IADD3 R12, P1, R0, c[0x0][0x160], RZ ;
FSEL R6, R18, RZ, P0 ;
FSEL R7, R19, 1.875, P0 ;
ISETP.GE.AND P0, PT, R8, 0x1, PT ;
LEA.HI.X.SX32 R13, R0, c[0x0][0x164], 0x1, P1 ;
DADD R14, R4, R6 ;
IMAD.WIDE R12, R3, 0x4, R12 ;
STG.E [R12.64], RZ ;
@!P0 EXIT ;
MUFU.RSQ64H R7, R15 ;
IADD3 R6, R15, -0x3500000, RZ ;
IMAD.MOV.U32 R8, RZ, RZ, 0x0 ;
BSSY B0, 0x700 ;
IMAD.MOV.U32 R9, RZ, RZ, 0x3fd80000 ;
ISETP.GE.U32.AND P0, PT, R6, 0x7ca00000, PT ;
DMUL R4, R6, R6 ;
DFMA R4, R14, -R4, 1 ;
DFMA R8, R4, R8, 0.5 ;
DMUL R4, R6, R4 ;
DFMA R16, R8, R4, R6 ;
IMAD.MOV.U32 R4, RZ, RZ, RZ ;
DMUL R18, R14, R16 ;
IADD3 R9, R17, -0x100000, RZ ;
IMAD.MOV.U32 R8, RZ, RZ, R16 ;
DFMA R20, R18, -R18, R14 ;
DFMA R10, R20, R8, R18 ;
@!P0 BRA 0x6f0 ;
IMAD.MOV.U32 R8, RZ, RZ, R16 ;
MOV R0, 0x6d0 ;
CALL.REL.NOINC 0xd30 ;
IMAD.MOV.U32 R10, RZ, RZ, R14 ;
IMAD.MOV.U32 R11, RZ, RZ, R15 ;
BSYNC B0 ;
IMAD.U32 R18, RZ, RZ, UR6 ;
IMAD.U32 R19, RZ, RZ, UR7 ;
LDG.E R6, [R18.64] ;
IMAD.U32 R16, RZ, RZ, UR8 ;
IMAD.U32 R17, RZ, RZ, UR9 ;
LDG.E R7, [R16.64] ;
BSSY B0, 0x7d0 ;
MOV R0, 0x7c0 ;
IMAD.IADD R6, R3, 0x1, -R6 ;
I2F.F64 R8, R6 ;
DADD R14, -RZ, |R8| ;
CALL.REL.NOINC 0x1030 ;
BSYNC B0 ;
DADD R14, R8, 2 ;
ISETP.NE.AND P0, PT, R6, RZ, PT ;
BSSY B0, 0x8f0 ;
LOP3.LUT R14, R15, 0x7ff00000, RZ, 0xc0, !PT ;
ISETP.NE.AND P1, PT, R14, 0x7ff00000, PT ;
@!P0 CS2R R18, SRZ ;
@P1 BRA 0x8e0 ;
DSETP.GTU.AND P0, PT, |R8|, +INF , PT ;
@P0 BRA 0x8d0 ;
ISETP.NE.AND P0, PT, R8, RZ, PT ;
LOP3.LUT R8, R9, 0x7fffffff, RZ, 0xc0, !PT ;
ISETP.NE.OR P0, PT, R8, 0x7ff00000, P0 ;
@P0 BRA 0x8e0 ;
IMAD.MOV.U32 R18, RZ, RZ, 0x0 ;
IMAD.MOV.U32 R19, RZ, RZ, 0x7ff00000 ;
BRA 0x8e0 ;
DADD R18, R8, 2 ;
BSYNC B0 ;
IMAD.IADD R7, R2, 0x1, -R7 ;
ISETP.NE.AND P0, PT, R6, 0x1, PT ;
BSSY B0, 0x990 ;
MOV R0, 0x980 ;
I2F.F64 R8, R7 ;
FSEL R30, R18, RZ, P0 ;
FSEL R31, R19, 1.875, P0 ;
DADD R14, -RZ, |R8| ;
CALL.REL.NOINC 0x1030 ;
BSYNC B0 ;
DADD R14, R8, 2 ;
ISETP.NE.AND P0, PT, R7, RZ, PT ;
BSSY B0, 0xab0 ;
LOP3.LUT R14, R15, 0x7ff00000, RZ, 0xc0, !PT ;
ISETP.NE.AND P1, PT, R14, 0x7ff00000, PT ;
@!P0 CS2R R18, SRZ ;
@P1 BRA 0xaa0 ;
DSETP.GTU.AND P0, PT, |R8|, +INF , PT ;
@P0 BRA 0xa90 ;
ISETP.NE.AND P0, PT, R8, RZ, PT ;
LOP3.LUT R8, R9, 0x7fffffff, RZ, 0xc0, !PT ;
ISETP.NE.OR P0, PT, R8, 0x7ff00000, P0 ;
@P0 BRA 0xaa0 ;
IMAD.MOV.U32 R18, RZ, RZ, 0x0 ;
IMAD.MOV.U32 R19, RZ, RZ, 0x7ff00000 ;
BRA 0xaa0 ;
DADD R18, R8, 2 ;
BSYNC B0 ;
ISETP.NE.AND P0, PT, R7, 0x1, PT ;
IMAD.MOV.U32 R14, RZ, RZ, 0x0 ;
BSSY B0, 0xc60 ;
IMAD.MOV.U32 R15, RZ, RZ, 0x3fd80000 ;
FSEL R6, R18, RZ, P0 ;
FSEL R7, R19, 1.875, P0 ;
DADD R30, R30, R6 ;
MUFU.RSQ64H R7, R31 ;
IADD3 R6, R31, -0x3500000, RZ ;
ISETP.GE.U32.AND P0, PT, R6, 0x7ca00000, PT ;
DMUL R8, R6, R6 ;
DFMA R8, R30, -R8, 1 ;
DFMA R14, R8, R14, 0.5 ;
DMUL R8, R6, R8 ;
DFMA R16, R14, R8, R6 ;
DMUL R18, R30, R16 ;
IADD3 R9, R17, -0x100000, RZ ;
IMAD.MOV.U32 R8, RZ, RZ, R16 ;
DFMA R20, R18, -R18, R30 ;
DFMA R14, R20, R8, R18 ;
@!P0 BRA 0xc50 ;
IMAD.MOV.U32 R8, RZ, RZ, R16 ;
MOV R0, 0xc50 ;
IMAD.MOV.U32 R14, RZ, RZ, R30 ;
IMAD.MOV.U32 R15, RZ, RZ, R31 ;
CALL.REL.NOINC 0xd30 ;
BSYNC B0 ;
BAR.SYNC.DEFER_BLOCKING 0x0 ;
UIADD3 UR8, UP0, UR8, 0x4, URZ ;
UIADD3 UR6, UP1, UR6, 0x4, URZ ;
UIADD3.X UR9, URZ, UR9, URZ, UP0, !UPT ;
DSETP.GEU.AND P0, PT, R14, R10, PT ;
UIADD3.X UR7, URZ, UR7, URZ, UP1, !UPT ;
@!P0 IMAD.MOV.U32 R10, RZ, RZ, R14 ;
@!P0 IMAD.MOV.U32 R11, RZ, RZ, R15 ;
@!P0 STG.E [R12.64], R4 ;
IADD3 R4, R4, 0x1, RZ ;
ISETP.GE.AND P1, PT, R4, c[0x0][0x188], PT ;
@!P1 BRA 0x700 ;
EXIT ;
ISETP.GE.U32.AND P0, PT, R6, -0x3400000, PT ;
BSSY B1, 0xfe0 ;
IMAD.MOV.U32 R6, RZ, RZ, R14 ;
IMAD.MOV.U32 R7, RZ, RZ, R15 ;
IMAD.MOV.U32 R14, RZ, RZ, R20 ;
IMAD.MOV.U32 R15, RZ, RZ, R21 ;
IMAD.MOV.U32 R16, RZ, RZ, R18 ;
IMAD.MOV.U32 R17, RZ, RZ, R19 ;
@!P0 BRA 0xe40 ;
DFMA.RM R8, R14, R8, R16 ;
IADD3 R14, P0, R8, 0x1, RZ ;
IMAD.X R15, RZ, RZ, R9, P0 ;
DFMA.RP R6, -R8, R14, R6 ;
DSETP.GT.AND P0, PT, R6, RZ, PT ;
FSEL R8, R14, R8, P0 ;
FSEL R9, R15, R9, P0 ;
BRA 0xfd0 ;
DSETP.NE.AND P0, PT, R6, RZ, PT ;
@!P0 BRA 0xfc0 ;
ISETP.GE.AND P0, PT, R7, RZ, PT ;
@!P0 IMAD.MOV.U32 R8, RZ, RZ, 0x0 ;
@!P0 IMAD.MOV.U32 R9, RZ, RZ, -0x80000 ;
@!P0 BRA 0xfd0 ;
ISETP.GT.AND P0, PT, R7, 0x7fefffff, PT ;
@P0 BRA 0xfc0 ;
DMUL R6, R6, 8.11296384146066816958e+31 ;
IMAD.MOV.U32 R8, RZ, RZ, RZ ;
IMAD.MOV.U32 R16, RZ, RZ, 0x0 ;
IMAD.MOV.U32 R17, RZ, RZ, 0x3fd80000 ;
MUFU.RSQ64H R9, R7 ;
DMUL R14, R8, R8 ;
DFMA R14, R6, -R14, 1 ;
DFMA R16, R14, R16, 0.5 ;
DMUL R14, R8, R14 ;
DFMA R14, R16, R14, R8 ;
DMUL R8, R6, R14 ;
IADD3 R15, R15, -0x100000, RZ ;
DFMA R16, R8, -R8, R6 ;
DFMA R8, R14, R16, R8 ;
IADD3 R9, R9, -0x3500000, RZ ;
BRA 0xfd0 ;
DADD R8, R6, R6 ;
BSYNC B1 ;
IMAD.MOV.U32 R6, RZ, RZ, R0 ;
IMAD.MOV.U32 R7, RZ, RZ, 0x0 ;
IMAD.MOV.U32 R14, RZ, RZ, R8 ;
IMAD.MOV.U32 R15, RZ, RZ, R9 ;
RET.REL.NODEC R6 0x0 ;
SHF.R.U32.HI R5, RZ, 0x14, R15 ;
ISETP.NE.AND P0, PT, R5, RZ, PT ;
@!P0 DMUL R24, R14, 1.80143985094819840000e+16 ;
@!P0 IMAD.MOV.U32 R15, RZ, RZ, R25 ;
@!P0 LEA.HI R5, R25, 0xffffffca, RZ, 0xc ;
@!P0 IMAD.MOV.U32 R14, RZ, RZ, R24 ;
LOP3.LUT R15, R15, 0x800fffff, RZ, 0xc0, !PT ;
IMAD.MOV.U32 R20, RZ, RZ, R14 ;
IMAD.MOV.U32 R14, RZ, RZ, RZ ;
LOP3.LUT R21, R15, 0x3ff00000, RZ, 0xfc, !PT ;
ISETP.GE.U32.AND P1, PT, R21, 0x3ff6a09f, PT ;
@P1 IADD3 R15, R21, -0x100000, RZ ;
@P1 IMAD.MOV.U32 R21, RZ, RZ, R15 ;
DADD R22, R20, 1 ;
DADD R20, R20, -1 ;
MUFU.RCP64H R15, R23 ;
DFMA R18, -R22, R14, 1 ;
DFMA R18, R18, R18, R18 ;
DFMA R18, R14, R18, R14 ;
DMUL R14, R18, R20 ;
DFMA R14, R18, R20, R14 ;
DADD R16, R20, -R14 ;
DMUL R22, R14, R14 ;
DADD R16, R16, R16 ;
DFMA R16, R20, -R14, R16 ;
IMAD.MOV.U32 R20, RZ, RZ, 0x7d2cafe2 ;
IMAD.MOV.U32 R21, RZ, RZ, 0x3eb0f5ff ;
DMUL R16, R18, R16 ;
DFMA R20, R22, R20, c[0x2][0x0] ;
DFMA R20, R22, R20, c[0x2][0x8] ;
DFMA R20, R22, R20, c[0x2][0x10] ;
DFMA R20, R22, R20, c[0x2][0x18] ;
DFMA R20, R22, R20, c[0x2][0x20] ;
DFMA R20, R22, R20, c[0x2][0x28] ;
DFMA R18, R22, R20, c[0x2][0x30] ;
DADD R24, -R18, c[0x2][0x30] ;
DFMA R20, R22, R20, R24 ;
IADD3 R25, R17, 0x100000, RZ ;
IMAD.MOV.U32 R24, RZ, RZ, R16 ;
DMUL R22, R14, R14 ;
DADD R20, RZ, R20 ;
DFMA R26, R14, R14, -R22 ;
DFMA R24, R14, R24, R26 ;
DMUL R26, R14, R22 ;
DFMA R28, R14, R22, -R26 ;
DFMA R28, R16, R22, R28 ;
DFMA R24, R14, R24, R28 ;
DADD R28, R20, c[0x2][0x38] ;
DADD R20, R18, R28 ;
DADD R18, R18, -R20 ;
DMUL R22, R20, R26 ;
DADD R28, R28, R18 ;
DFMA R18, R20, R26, -R22 ;
DFMA R18, R20, R24, R18 ;
DFMA R28, R28, R26, R18 ;
DADD R20, R22, R28 ;
DADD R18, R14, R20 ;
DADD R22, R22, -R20 ;
DADD R14, R14, -R18 ;
DADD R22, R28, R22 ;
DADD R14, R20, R14 ;
IADD3 R20, R5.reuse, -0x3ff, RZ ;
IMAD.MOV.U32 R21, RZ, RZ, 0x43300000 ;
@P1 IADD3 R20, R5, -0x3fe, RZ ;
DADD R22, R22, R14 ;
LOP3.LUT R20, R20, 0x80000000, RZ, 0x3c, !PT ;
DADD R22, R16, R22 ;
DADD R16, R20, c[0x2][0x40] ;
DADD R20, R18, R22 ;
DFMA R14, R16, c[0x2][0x48], R20 ;
DADD R24, R18, -R20 ;
DFMA R18, -R16, c[0x2][0x48], R14 ;
DADD R24, R22, R24 ;
DADD R18, -R20, R18 ;
IMAD.MOV.U32 R20, RZ, RZ, 0x652b82fe ;
IMAD.MOV.U32 R21, RZ, RZ, 0x3ff71547 ;
DADD R18, R24, -R18 ;
DFMA R18, R16, c[0x2][0x50], R18 ;
DADD R16, R14, R18 ;
DADD R14, R14, -R16 ;
DMUL R24, R16, 2 ;
DADD R14, R18, R14 ;
DFMA R22, R16, 2, -R24 ;
DFMA R22, R14, 2, R22 ;
DADD R16, R24, R22 ;
DFMA R20, R16, R20, 6.75539944105574400000e+15 ;
FSETP.GEU.AND P0, PT, |R17|, 4.1917929649353027344, PT ;
DADD R14, R20, -6.75539944105574400000e+15 ;
DFMA R18, R14, c[0x2][0x58], R16 ;
DFMA R18, R14, c[0x2][0x60], R18 ;
IMAD.MOV.U32 R14, RZ, RZ, 0x69ce2bdf ;
IMAD.MOV.U32 R15, RZ, RZ, 0x3e5ade15 ;
DFMA R14, R18, R14, c[0x2][0x68] ;
DFMA R14, R18, R14, c[0x2][0x70] ;
DFMA R14, R18, R14, c[0x2][0x78] ;
DFMA R14, R18, R14, c[0x2][0x80] ;
DFMA R14, R18, R14, c[0x2][0x88] ;
DFMA R14, R18, R14, c[0x2][0x90] ;
DFMA R14, R18, R14, c[0x2][0x98] ;
DFMA R14, R18, R14, c[0x2][0xa0] ;
DFMA R14, R18, R14, c[0x2][0xa8] ;
DFMA R14, R18, R14, 1 ;
DFMA R14, R18, R14, 1 ;
IMAD R19, R20, 0x100000, R15 ;
IMAD.MOV.U32 R18, RZ, RZ, R14 ;
@!P0 BRA 0x1790 ;
FSETP.GEU.AND P1, PT, |R17|, 4.2275390625, PT ;
DADD R18, R16, +INF ;
DSETP.GEU.AND P0, PT, R16, RZ, PT ;
FSEL R18, R18, RZ, P0 ;
@!P1 LEA.HI R5, R20, R20, RZ, 0x1 ;
FSEL R19, R19, RZ, P0 ;
@!P1 SHF.R.S32.HI R5, RZ, 0x1, R5 ;
@!P1 IMAD R15, R5, 0x100000, R15 ;
@!P1 IMAD.IADD R5, R20, 0x1, -R5 ;
@!P1 IMAD.MOV.U32 R20, RZ, RZ, RZ ;
@!P1 LEA R21, R5, 0x3ff00000, 0x14 ;
@!P1 DMUL R18, R14, R20 ;
LOP3.LUT R5, R19, 0x7fffffff, RZ, 0xc0, !PT ;
DADD R16, R24, -R16 ;
IMAD.MOV.U32 R14, RZ, RZ, R0 ;
ISETP.NE.AND P0, PT, R5, 0x7ff00000, PT ;
IMAD.MOV.U32 R15, RZ, RZ, 0x0 ;
DADD R16, R22, R16 ;
ISETP.EQ.AND P0, PT, R18, RZ, !P0 ;
@!P0 DFMA R18, R16, R18, R18 ;
RET.REL.NODEC R14 0x0 ;
BRA 0x1820;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
```
|
```amdasm
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.p2align 2 ; -- Begin function _Z13eucludianDistiiii
.type _Z13eucludianDistiiii,@function
_Z13eucludianDistiiii: ; @_Z13eucludianDistiiii
; %bb.0:
s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
v_sub_nc_u32_e32 v8, v0, v2
s_mov_b32 s2, 0x55555555
s_mov_b32 s3, 0x3fe55555
s_mov_b32 s4, 0x968915a9
s_mov_b32 s6, 0x4222de17
v_cvt_f64_i32_e32 v[4:5], v8
s_mov_b32 s5, 0x3fba6564
s_mov_b32 s7, 0x3fbdee67
s_mov_b32 s12, 0x3abe935a
s_mov_b32 s13, 0x3fbe25e4
s_mov_b32 s14, 0x47e6c9c2
s_mov_b32 s15, 0x3fc110ef
s_mov_b32 s16, 0xcfa74449
s_mov_b32 s17, 0x3fc3b13b
s_mov_b32 s18, 0x71bf3c30
s_mov_b32 s19, 0x3fc745d1
s_mov_b32 s20, 0x1c7792ce
s_mov_b32 s21, 0x3fcc71c7
s_mov_b32 s22, 0x924920da
s_mov_b32 s23, 0x3fd24924
s_mov_b32 s24, 0x9999999c
s_mov_b32 s25, 0x3fd99999
s_mov_b32 s9, 0xbfe55555
s_mov_b32 s8, s2
s_mov_b32 s10, 0xd5df274d
s_mov_b32 s11, 0x3c8543b0
s_mov_b32 s26, 11
s_mov_b32 s27, 0x3fe00000
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_frexp_mant_f64_e64 v[6:7], |v[4:5]|
v_frexp_exp_i32_f64_e32 v4, v[4:5]
v_cmp_gt_f64_e32 vcc_lo, s[2:3], v[6:7]
v_cndmask_b32_e64 v9, 0, 1, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_subrev_co_ci_u32_e32 v4, vcc_lo, 0, v4, vcc_lo
v_cmp_eq_u32_e32 vcc_lo, 1, v8
v_ldexp_f64 v[6:7], v[6:7], v9
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_f64 v[9:10], v[6:7], 1.0
v_add_f64 v[15:16], v[6:7], -1.0
v_rcp_f64_e32 v[11:12], v[9:10]
v_add_f64 v[17:18], v[9:10], -1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_add_f64 v[6:7], v[6:7], -v[17:18]
s_waitcnt_depctr 0xfff
v_fma_f64 v[13:14], -v[9:10], v[11:12], 1.0
v_fma_f64 v[11:12], v[13:14], v[11:12], v[11:12]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[13:14], -v[9:10], v[11:12], 1.0
v_fma_f64 v[11:12], v[13:14], v[11:12], v[11:12]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f64 v[13:14], v[15:16], v[11:12]
v_mul_f64 v[19:20], v[9:10], v[13:14]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[9:10], v[13:14], v[9:10], -v[19:20]
v_fma_f64 v[6:7], v[13:14], v[6:7], v[9:10]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[9:10], v[19:20], v[6:7]
v_add_f64 v[17:18], v[15:16], -v[9:10]
v_add_f64 v[19:20], v[9:10], -v[19:20]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f64 v[15:16], v[15:16], -v[17:18]
v_add_f64 v[6:7], v[19:20], -v[6:7]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[9:10], v[15:16], -v[9:10]
v_add_f64 v[6:7], v[6:7], v[9:10]
v_sub_nc_u32_e32 v9, v1, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[6:7], v[17:18], v[6:7]
v_mul_f64 v[6:7], v[11:12], v[6:7]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[10:11], v[13:14], v[6:7]
v_add_f64 v[12:13], v[10:11], -v[13:14]
v_mul_f64 v[14:15], v[10:11], v[10:11]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_f64 v[12:13], v[6:7], -v[12:13]
v_cvt_f64_i32_e32 v[6:7], v9
v_fma_f64 v[16:17], v[10:11], v[10:11], -v[14:15]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f64 v[18:19], v[12:13], v[12:13]
v_frexp_mant_f64_e64 v[20:21], |v[6:7]|
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f64 v[16:17], v[10:11], v[18:19], v[16:17]
v_cmp_gt_f64_e64 s0, s[2:3], v[20:21]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e64 v18, 0, 1, s0
v_ldexp_f64 v[18:19], v[20:21], v18
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f64 v[20:21], v[14:15], v[16:17]
v_add_f64 v[22:23], v[18:19], 1.0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_4)
v_fma_f64 v[24:25], v[20:21], s[6:7], s[4:5]
v_add_f64 v[30:31], v[18:19], -1.0
v_add_f64 v[14:15], v[20:21], -v[14:15]
v_mul_f64 v[48:49], v[10:11], v[20:21]
v_rcp_f64_e32 v[26:27], v[22:23]
v_fma_f64 v[24:25], v[20:21], v[24:25], s[12:13]
v_add_f64 v[32:33], v[22:23], -1.0
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f64 v[14:15], v[16:17], -v[14:15]
v_fma_f64 v[24:25], v[20:21], v[24:25], s[14:15]
s_waitcnt_depctr 0xfff
v_fma_f64 v[28:29], -v[22:23], v[26:27], 1.0
v_add_f64 v[18:19], v[18:19], -v[32:33]
v_fma_f64 v[24:25], v[20:21], v[24:25], s[16:17]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f64 v[26:27], v[28:29], v[26:27], v[26:27]
v_fma_f64 v[24:25], v[20:21], v[24:25], s[18:19]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f64 v[28:29], -v[22:23], v[26:27], 1.0
v_fma_f64 v[24:25], v[20:21], v[24:25], s[20:21]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f64 v[26:27], v[28:29], v[26:27], v[26:27]
v_fma_f64 v[24:25], v[20:21], v[24:25], s[22:23]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_f64 v[28:29], v[30:31], v[26:27]
v_fma_f64 v[24:25], v[20:21], v[24:25], s[24:25]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_f64 v[34:35], v[22:23], v[28:29]
v_mul_f64 v[32:33], v[20:21], v[24:25]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f64 v[22:23], v[28:29], v[22:23], -v[34:35]
v_fma_f64 v[16:17], v[20:21], v[24:25], -v[32:33]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f64 v[18:19], v[28:29], v[18:19], v[22:23]
v_fma_f64 v[16:17], v[14:15], v[24:25], v[16:17]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f64 v[22:23], v[34:35], v[18:19]
v_add_f64 v[36:37], v[32:33], v[16:17]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_f64 v[24:25], v[30:31], -v[22:23]
v_add_f64 v[34:35], v[22:23], -v[34:35]
v_add_f64 v[38:39], v[36:37], s[2:3]
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_add_f64 v[30:31], v[30:31], -v[24:25]
v_add_f64 v[32:33], v[36:37], -v[32:33]
v_add_f64 v[18:19], v[34:35], -v[18:19]
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_add_f64 v[22:23], v[30:31], -v[22:23]
v_add_f64 v[30:31], v[38:39], s[8:9]
v_add_f64 v[16:17], v[16:17], -v[32:33]
v_fma_f64 v[32:33], v[20:21], v[10:11], -v[48:49]
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_f64 v[18:19], v[18:19], v[22:23]
v_add_f64 v[22:23], v[36:37], -v[30:31]
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_f64 v[16:17], v[16:17], s[10:11]
v_fma_f64 v[20:21], v[20:21], v[12:13], v[32:33]
v_ldexp_f64 v[12:13], v[12:13], 1
v_add_f64 v[18:19], v[24:25], v[18:19]
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_f64 v[16:17], v[16:17], v[22:23]
v_fma_f64 v[14:15], v[14:15], v[10:11], v[20:21]
v_ldexp_f64 v[10:11], v[10:11], 1
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_mul_f64 v[18:19], v[26:27], v[18:19]
v_add_f64 v[20:21], v[38:39], v[16:17]
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f64 v[22:23], v[48:49], v[14:15]
v_add_f64 v[24:25], v[28:29], v[18:19]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f64 v[26:27], v[38:39], -v[20:21]
v_mul_f64 v[30:31], v[22:23], v[20:21]
v_add_f64 v[32:33], v[22:23], -v[48:49]
s_delay_alu instid0(VALU_DEP_4)
v_add_f64 v[28:29], v[24:25], -v[28:29]
v_mul_f64 v[34:35], v[24:25], v[24:25]
v_add_f64 v[16:17], v[16:17], v[26:27]
v_fma_f64 v[26:27], v[22:23], v[20:21], -v[30:31]
v_add_f64 v[14:15], v[14:15], -v[32:33]
v_add_f64 v[18:19], v[18:19], -v[28:29]
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_fma_f64 v[16:17], v[22:23], v[16:17], v[26:27]
v_fma_f64 v[22:23], v[24:25], v[24:25], -v[34:35]
v_add_f64 v[26:27], v[18:19], v[18:19]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f64 v[14:15], v[14:15], v[20:21], v[16:17]
v_fma_f64 v[16:17], v[24:25], v[26:27], v[22:23]
v_cvt_f64_i32_e32 v[26:27], v4
v_frexp_exp_i32_f64_e32 v4, v[6:7]
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_f64 v[20:21], v[30:31], v[14:15]
v_add_f64 v[22:23], v[34:35], v[16:17]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_f64 v[28:29], v[10:11], v[20:21]
v_add_f64 v[30:31], v[20:21], -v[30:31]
v_fma_f64 v[32:33], v[22:23], s[6:7], s[4:5]
s_mov_b32 s4, 0xfefa39ef
s_mov_b32 s5, 0x3fe62e42
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_add_f64 v[10:11], v[28:29], -v[10:11]
v_mul_f64 v[36:37], v[26:27], s[4:5]
v_add_f64 v[14:15], v[14:15], -v[30:31]
s_mov_b32 s6, 0x3b39803f
s_mov_b32 s7, 0x3c7abc9e
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
v_fma_f64 v[30:31], v[22:23], v[32:33], s[12:13]
s_mov_b32 s12, 0xfca7ab0c
s_mov_b32 s13, 0x3e928af3
v_add_f64 v[10:11], v[20:21], -v[10:11]
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_fma_f64 v[32:33], v[26:27], s[4:5], -v[36:37]
v_add_f64 v[12:13], v[12:13], v[14:15]
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_fma_f64 v[14:15], v[22:23], v[30:31], s[14:15]
s_mov_b32 s14, 0x6a5dcb37
s_mov_b32 s15, 0x3e5ade15
v_fma_f64 v[20:21], v[26:27], s[6:7], v[32:33]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f64 v[10:11], v[12:13], v[10:11]
v_fma_f64 v[12:13], v[22:23], v[14:15], s[16:17]
s_mov_b32 s16, 0x14761f6e
s_mov_b32 s17, 0x3f2a01a0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f64 v[14:15], v[36:37], v[20:21]
v_add_f64 v[26:27], v[28:29], v[10:11]
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_fma_f64 v[12:13], v[22:23], v[12:13], s[18:19]
s_mov_b32 s18, 0x1852b7b0
s_mov_b32 s19, 0x3f56c16c
v_add_f64 v[36:37], v[14:15], -v[36:37]
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_add_f64 v[30:31], v[14:15], v[26:27]
v_add_f64 v[28:29], v[26:27], -v[28:29]
v_fma_f64 v[12:13], v[22:23], v[12:13], s[20:21]
s_mov_b32 s20, 0x11122322
s_mov_b32 s21, 0x3f811111
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_f64 v[20:21], v[20:21], -v[36:37]
v_add_f64 v[32:33], v[30:31], -v[14:15]
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_4)
v_add_f64 v[10:11], v[10:11], -v[28:29]
v_add_f64 v[28:29], v[22:23], -v[34:35]
v_fma_f64 v[12:13], v[22:23], v[12:13], s[22:23]
s_mov_b32 s22, 0x555502a1
s_mov_b32 s23, 0x3fa55555
v_add_f64 v[38:39], v[30:31], -v[32:33]
v_add_f64 v[26:27], v[26:27], -v[32:33]
v_add_f64 v[34:35], v[20:21], v[10:11]
v_add_f64 v[16:17], v[16:17], -v[28:29]
v_fma_f64 v[12:13], v[22:23], v[12:13], s[24:25]
s_mov_b32 s24, 0x55555511
s_mov_b32 s25, 0x3fc55555
v_add_f64 v[14:15], v[14:15], -v[38:39]
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f64 v[28:29], v[34:35], -v[20:21]
v_mul_f64 v[32:33], v[22:23], v[12:13]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f64 v[14:15], v[26:27], v[14:15]
v_add_f64 v[10:11], v[10:11], -v[28:29]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_fma_f64 v[26:27], v[22:23], v[12:13], -v[32:33]
v_add_f64 v[14:15], v[34:35], v[14:15]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_fma_f64 v[12:13], v[16:17], v[12:13], v[26:27]
v_add_f64 v[26:27], v[34:35], -v[28:29]
v_add_f64 v[34:35], v[30:31], v[14:15]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f64 v[36:37], v[32:33], v[12:13]
v_add_f64 v[20:21], v[20:21], -v[26:27]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f64 v[26:27], v[34:35], -v[30:31]
v_add_f64 v[28:29], v[36:37], s[2:3]
v_add_f64 v[30:31], v[36:37], -v[32:33]
v_mul_f64 v[32:33], v[24:25], v[22:23]
v_add_f64 v[10:11], v[10:11], v[20:21]
s_mov_b32 s2, 0x652b82fe
v_add_f64 v[14:15], v[14:15], -v[26:27]
s_mov_b32 s3, 0x3ff71547
v_add_f64 v[20:21], v[28:29], s[8:9]
v_add_f64 v[12:13], v[12:13], -v[30:31]
v_fma_f64 v[26:27], v[22:23], v[24:25], -v[32:33]
s_mov_b32 s9, 0xbfe62e42
s_mov_b32 s8, s4
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_f64 v[10:11], v[10:11], v[14:15]
v_add_f64 v[14:15], v[36:37], -v[20:21]
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_f64 v[12:13], v[12:13], s[10:11]
v_fma_f64 v[20:21], v[22:23], v[18:19], v[26:27]
s_mov_b32 s11, 0xbc7abc9e
s_mov_b32 s10, s6
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_add_f64 v[22:23], v[34:35], v[10:11]
v_ldexp_f64 v[18:19], v[18:19], 1
v_add_f64 v[12:13], v[12:13], v[14:15]
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_2)
v_fma_f64 v[14:15], v[16:17], v[24:25], v[20:21]
v_mov_b32_e32 v16, 0
v_cndmask_b32_e64 v17, 2.0, 0x3ff00000, vcc_lo
v_add_f64 v[20:21], v[22:23], -v[34:35]
v_mul_f64 v[26:27], v[16:17], v[22:23]
v_add_f64 v[30:31], v[28:29], v[12:13]
v_add_f64 v[34:35], v[32:33], v[14:15]
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_f64 v[10:11], v[10:11], -v[20:21]
v_fma_f64 v[20:21], v[16:17], v[22:23], -v[26:27]
v_cmp_class_f64_e64 vcc_lo, v[26:27], 0x204
v_add_f64 v[22:23], v[28:29], -v[30:31]
v_mul_f64 v[28:29], v[34:35], v[30:31]
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_fma_f64 v[10:11], v[16:17], v[10:11], v[20:21]
v_add_f64 v[20:21], v[34:35], -v[32:33]
v_add_f64 v[12:13], v[12:13], v[22:23]
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_fma_f64 v[22:23], v[34:35], v[30:31], -v[28:29]
v_add_f64 v[32:33], v[26:27], v[10:11]
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f64 v[14:15], v[14:15], -v[20:21]
v_fma_f64 v[12:13], v[34:35], v[12:13], v[22:23]
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_dual_cndmask_b32 v21, v33, v27 :: v_dual_cndmask_b32 v20, v32, v26
v_add_f64 v[26:27], v[32:33], -v[26:27]
v_subrev_co_ci_u32_e64 v4, vcc_lo, 0, v4, s0
v_cmp_neq_f64_e64 vcc_lo, 0x7ff00000, |v[20:21]|
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_cvt_f64_i32_e32 v[34:35], v4
v_fma_f64 v[12:13], v[14:15], v[30:31], v[12:13]
v_add_f64 v[10:11], v[10:11], -v[26:27]
v_mul_f64 v[38:39], v[34:35], s[4:5]
s_delay_alu instid0(VALU_DEP_2)
v_cndmask_b32_e32 v11, 0, v11, vcc_lo
v_mul_f64 v[22:23], v[20:21], s[2:3]
v_cmp_nlt_f64_e64 s0, 0x40900000, v[20:21]
v_cmp_ngt_f64_e64 s1, 0xc090cc00, v[20:21]
v_cndmask_b32_e32 v10, 0, v10, vcc_lo
v_fma_f64 v[48:49], v[34:35], s[4:5], -v[38:39]
s_mov_b32 s4, 0x623fde64
s_mov_b32 s5, 0x3ec71dee
v_rndne_f64_e32 v[14:15], v[22:23]
v_ldexp_f64 v[22:23], v[24:25], 1
v_add_f64 v[24:25], v[28:29], v[12:13]
s_and_b32 vcc_lo, s1, s0
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_fma_f64 v[30:31], v[14:15], s[8:9], v[20:21]
v_cvt_i32_f64_e32 v4, v[14:15]
v_add_f64 v[36:37], v[22:23], v[24:25]
v_add_f64 v[28:29], v[24:25], -v[28:29]
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_fma_f64 v[30:31], v[14:15], s[10:11], v[30:31]
v_add_f64 v[22:23], v[36:37], -v[22:23]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f64 v[12:13], v[12:13], -v[28:29]
v_fma_f64 v[28:29], v[30:31], s[14:15], s[12:13]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f64 v[22:23], v[24:25], -v[22:23]
v_add_f64 v[12:13], v[18:19], v[12:13]
v_fma_f64 v[24:25], v[34:35], s[6:7], v[48:49]
s_mov_b32 s6, 0x7c89e6b0
s_mov_b32 s7, 0x3efa0199
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_fma_f64 v[18:19], v[30:31], v[28:29], s[4:5]
v_add_f64 v[12:13], v[12:13], v[22:23]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f64 v[22:23], v[38:39], v[24:25]
v_fma_f64 v[18:19], v[30:31], v[18:19], s[6:7]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f64 v[28:29], v[36:37], v[12:13]
v_add_f64 v[38:39], v[22:23], -v[38:39]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_fma_f64 v[18:19], v[30:31], v[18:19], s[16:17]
v_add_f64 v[34:35], v[22:23], v[28:29]
v_add_f64 v[36:37], v[28:29], -v[36:37]
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_f64 v[24:25], v[24:25], -v[38:39]
v_fma_f64 v[18:19], v[30:31], v[18:19], s[18:19]
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_f64 v[48:49], v[34:35], -v[22:23]
v_add_f64 v[12:13], v[12:13], -v[36:37]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_fma_f64 v[18:19], v[30:31], v[18:19], s[20:21]
v_add_f64 v[50:51], v[34:35], -v[48:49]
v_add_f64 v[28:29], v[28:29], -v[48:49]
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_f64 v[36:37], v[24:25], v[12:13]
v_fma_f64 v[18:19], v[30:31], v[18:19], s[22:23]
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f64 v[22:23], v[22:23], -v[50:51]
v_fma_f64 v[18:19], v[30:31], v[18:19], s[24:25]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_f64 v[22:23], v[28:29], v[22:23]
v_add_f64 v[28:29], v[36:37], -v[24:25]
v_fma_f64 v[18:19], v[30:31], v[18:19], s[26:27]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f64 v[22:23], v[36:37], v[22:23]
v_add_f64 v[36:37], v[36:37], -v[28:29]
v_add_f64 v[12:13], v[12:13], -v[28:29]
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_fma_f64 v[18:19], v[30:31], v[18:19], 1.0
v_add_f64 v[38:39], v[34:35], v[22:23]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_fma_f64 v[14:15], v[30:31], v[18:19], 1.0
v_add_f64 v[18:19], v[24:25], -v[36:37]
v_add_f64 v[24:25], v[38:39], -v[34:35]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_ldexp_f64 v[14:15], v[14:15], v4
v_add_f64 v[12:13], v[12:13], v[18:19]
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_add_f64 v[18:19], v[22:23], -v[24:25]
v_mul_f64 v[22:23], v[16:17], 0.5
v_cndmask_b32_e64 v4, 0x7ff00000, v15, s0
v_cndmask_b32_e32 v14, 0, v14, vcc_lo
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_add_f64 v[12:13], v[12:13], v[18:19]
v_trunc_f64_e32 v[18:19], v[16:17]
v_cndmask_b32_e64 v15, 0, v4, s1
v_cmp_eq_u32_e64 s1, 1, v9
s_delay_alu instid0(VALU_DEP_2)
v_fma_f64 v[10:11], v[14:15], v[10:11], v[14:15]
v_cmp_class_f64_e64 vcc_lo, v[14:15], 0x204
v_add_f64 v[20:21], v[38:39], v[12:13]
v_cmp_eq_f64_e64 s0, v[18:19], v[16:17]
v_cndmask_b32_e64 v17, 2.0, 0x3ff00000, s1
v_cndmask_b32_e32 v4, v10, v14, vcc_lo
v_cndmask_b32_e32 v10, v11, v15, vcc_lo
v_add_f64 v[18:19], v[20:21], -v[38:39]
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_mul_f64 v[24:25], v[16:17], v[20:21]
v_cndmask_b32_e64 v11, 0, v4, s0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f64 v[12:13], v[12:13], -v[18:19]
v_fma_f64 v[18:19], v[16:17], v[20:21], -v[24:25]
v_cmp_class_f64_e64 s1, v[24:25], 0x204
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[12:13], v[16:17], v[12:13], v[18:19]
v_add_f64 v[18:19], v[24:25], v[12:13]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cndmask_b32_e64 v21, v19, v25, s1
v_cndmask_b32_e64 v20, v18, v24, s1
v_add_f64 v[18:19], v[18:19], -v[24:25]
s_delay_alu instid0(VALU_DEP_2)
v_mul_f64 v[26:27], v[20:21], s[2:3]
v_cmp_neq_f64_e64 s1, 0x7ff00000, |v[20:21]|
v_cmp_nlt_f64_e64 s2, 0x40900000, v[20:21]
v_cmp_ngt_f64_e64 s3, 0xc090cc00, v[20:21]
v_add_f64 v[12:13], v[12:13], -v[18:19]
v_mul_f64 v[18:19], v[16:17], 0.5
v_rndne_f64_e32 v[26:27], v[26:27]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_cndmask_b32_e64 v13, 0, v13, s1
v_cndmask_b32_e64 v12, 0, v12, s1
s_and_b32 s1, s3, s2
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_fma_f64 v[28:29], v[26:27], s[8:9], v[20:21]
v_cvt_i32_f64_e32 v6, v[26:27]
v_fma_f64 v[28:29], v[26:27], s[10:11], v[28:29]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[30:31], v[28:29], s[14:15], s[12:13]
v_fma_f64 v[30:31], v[28:29], v[30:31], s[4:5]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[30:31], v[28:29], v[30:31], s[6:7]
v_fma_f64 v[30:31], v[28:29], v[30:31], s[16:17]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[30:31], v[28:29], v[30:31], s[18:19]
v_fma_f64 v[30:31], v[28:29], v[30:31], s[20:21]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[30:31], v[28:29], v[30:31], s[22:23]
v_fma_f64 v[30:31], v[28:29], v[30:31], s[24:25]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[30:31], v[28:29], v[30:31], s[26:27]
v_fma_f64 v[30:31], v[28:29], v[30:31], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_fma_f64 v[26:27], v[28:29], v[30:31], 1.0
v_trunc_f64_e32 v[28:29], v[16:17]
v_ldexp_f64 v[24:25], v[26:27], v6
v_trunc_f64_e32 v[26:27], v[18:19]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cmp_eq_f64_e64 s4, v[28:29], v[16:17]
v_cndmask_b32_e64 v6, 0x7ff00000, v25, s2
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
v_cndmask_b32_e64 v20, 0, v24, s1
v_trunc_f64_e32 v[24:25], v[22:23]
v_cmp_neq_f64_e64 s2, v[26:27], v[18:19]
v_cndmask_b32_e64 v21, 0, v6, s3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_fma_f64 v[12:13], v[20:21], v[12:13], v[20:21]
v_cmp_class_f64_e64 s3, v[20:21], 0x204
v_cmp_neq_f64_e64 s1, v[24:25], v[22:23]
v_cndmask_b32_e64 v6, v12, v20, s3
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cndmask_b32_e64 v12, v13, v21, s3
v_cndmask_b32_e64 v13, 0, v6, s4
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_3)
s_and_b32 vcc_lo, s0, s1
v_cndmask_b32_e32 v5, 0x3ff00000, v5, vcc_lo
s_and_b32 vcc_lo, s4, s2
v_cndmask_b32_e32 v7, 0x3ff00000, v7, vcc_lo
v_cmp_gt_i32_e32 vcc_lo, 0, v8
v_bfi_b32 v5, 0x7fffffff, v10, v5
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_bfi_b32 v7, 0x7fffffff, v12, v7
v_cndmask_b32_e32 v4, v4, v11, vcc_lo
v_cndmask_b32_e64 v10, 0x7ff80000, v5, s0
v_cmp_gt_i32_e64 s0, 0, v9
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cndmask_b32_e64 v8, 0x7ff80000, v7, s4
v_cndmask_b32_e32 v5, v5, v10, vcc_lo
v_cmp_ne_u32_e32 vcc_lo, v0, v2
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_cndmask_b32_e64 v2, v6, v13, s0
v_cndmask_b32_e64 v7, v7, v8, s0
v_cmp_ne_u32_e64 s0, v1, v3
v_dual_cndmask_b32 v0, 0, v4 :: v_dual_cndmask_b32 v1, 0, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
v_cndmask_b32_e64 v2, 0, v2, s0
v_cndmask_b32_e64 v3, 0, v7, s0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[0:1], v[0:1], v[2:3]
v_cmp_gt_f64_e32 vcc_lo, 0x10000000, v[0:1]
v_cndmask_b32_e64 v2, 0, 1, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b32_e32 v2, 8, v2
v_ldexp_f64 v[0:1], v[0:1], v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_rsq_f64_e32 v[2:3], v[0:1]
s_waitcnt_depctr 0xfff
v_mul_f64 v[4:5], v[0:1], v[2:3]
v_mul_f64 v[2:3], v[2:3], 0.5
v_fma_f64 v[6:7], -v[2:3], v[4:5], 0.5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_fma_f64 v[4:5], v[4:5], v[6:7], v[4:5]
v_fma_f64 v[2:3], v[2:3], v[6:7], v[2:3]
v_fma_f64 v[6:7], -v[4:5], v[4:5], v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[4:5], v[6:7], v[2:3], v[4:5]
v_fma_f64 v[6:7], -v[4:5], v[4:5], v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_fma_f64 v[2:3], v[6:7], v[2:3], v[4:5]
v_cndmask_b32_e64 v4, 0, 0xffffff80, vcc_lo
v_cmp_class_f64_e64 vcc_lo, v[0:1], 0x260
v_ldexp_f64 v[2:3], v[2:3], v4
s_delay_alu instid0(VALU_DEP_1)
v_dual_cndmask_b32 v0, v2, v0 :: v_dual_cndmask_b32 v1, v3, v1
s_setpc_b64 s[30:31]
.Lfunc_end0:
.size _Z13eucludianDistiiii, .Lfunc_end0-_Z13eucludianDistiiii
; -- End function
.section .AMDGPU.csdata,"",@progbits
; Function info:
; codeLenInByte = 3704
; NumSgprs: 34
; NumVgprs: 52
; ScratchSize: 0
; MemoryBound: 0
.text
.protected _Z13voronoiKernelPiiiiS_S_i ; -- Begin function _Z13voronoiKernelPiiiiS_S_i
.globl _Z13voronoiKernelPiiiiS_S_i
.p2align 8
.type _Z13voronoiKernelPiiiiS_S_i,@function
_Z13voronoiKernelPiiiiS_S_i: ; @_Z13voronoiKernelPiiiiS_S_i
; %bb.0:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x3c
s_load_b128 s[4:7], s[0:1], 0x8
v_and_b32_e32 v1, 0x3ff, v0
v_bfe_u32 v0, v0, 10, 10
s_mov_b32 s32, 0
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_lshr_b32 s3, s2, 16
s_and_b32 s2, s2, 0xffff
v_mad_u64_u32 v[42:43], null, s15, s3, v[0:1]
v_mad_u64_u32 v[40:41], null, s14, s2, v[1:2]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_gt_i32_e64 s2, s5, v42
v_cmp_gt_i32_e32 vcc_lo, s4, v40
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, vcc_lo, s2
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB1_6
; %bb.1:
s_clause 0x1
s_load_b128 s[36:39], s[0:1], 0x18
s_load_b64 s[2:3], s[0:1], 0x0
v_mul_lo_u32 v2, v42, s6
s_load_b32 s33, s[0:1], 0x28
v_ashrrev_i32_e32 v41, 31, v40
s_waitcnt lgkmcnt(0)
s_load_b32 s0, s[36:37], 0x0
s_load_b32 s1, s[38:39], 0x0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_4)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[0:1], 2, v[40:41]
v_add_co_u32 v2, vcc_lo, s2, v2
v_mov_b32_e32 v41, 0
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_co_u32 v45, vcc_lo, v2, v0
s_cmp_lt_i32 s33, 1
v_add_co_ci_u32_e32 v46, vcc_lo, v3, v1, vcc_lo
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
global_store_b32 v[45:46], v41, off
s_cbranch_scc1 .LBB1_6
; %bb.2: ; %.lr.ph.preheader
v_dual_mov_b32 v0, v40 :: v_dual_mov_b32 v1, v42
v_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v3, s1
s_getpc_b64 s[28:29]
s_add_u32 s28, s28, _Z13eucludianDistiiii@rel32@lo+4
s_addc_u32 s29, s29, _Z13eucludianDistiiii@rel32@hi+12
s_delay_alu instid0(SALU_CYCLE_1)
s_swappc_b64 s[30:31], s[28:29]
v_dual_mov_b32 v43, v0 :: v_dual_mov_b32 v44, v1
s_mov_b32 s34, 0
.LBB1_3: ; %.lr.ph
; =>This Inner Loop Header: Depth=1
s_clause 0x1
global_load_b32 v2, v41, s[36:37]
global_load_b32 v3, v41, s[38:39]
v_dual_mov_b32 v0, v40 :: v_dual_mov_b32 v1, v42
s_swappc_b64 s[30:31], s[28:29]
s_mov_b32 s0, exec_lo
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
v_cmpx_lt_f64_e32 v[0:1], v[43:44]
s_cbranch_execz .LBB1_5
; %bb.4: ; in Loop: Header=BB1_3 Depth=1
v_mov_b32_e32 v44, v1
v_dual_mov_b32 v2, s34 :: v_dual_mov_b32 v43, v0
global_store_b32 v[45:46], v2, off
.LBB1_5: ; in Loop: Header=BB1_3 Depth=1
s_or_b32 exec_lo, exec_lo, s0
s_add_i32 s34, s34, 1
s_add_u32 s36, s36, 4
s_addc_u32 s37, s37, 0
s_add_u32 s38, s38, 4
s_addc_u32 s39, s39, 0
s_cmp_lg_u32 s33, s34
s_cbranch_scc1 .LBB1_3
.LBB1_6: ; %.loopexit
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13voronoiKernelPiiiiS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 304
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 52
.amdhsa_next_free_sgpr 40
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z13voronoiKernelPiiiiS_S_i, .Lfunc_end1-_Z13voronoiKernelPiiiiS_S_i
; -- End function
.section .AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 436
; NumSgprs: 42
; NumVgprs: 52
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 5
; VGPRBlocks: 6
; NumSGPRsForWavesPerEU: 42
; NumVGPRsForWavesPerEU: 52
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object ; @__hip_cuid_
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0 ; 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .offset: 40
.size: 4
.value_kind: by_value
- .offset: 48
.size: 4
.value_kind: hidden_block_count_x
- .offset: 52
.size: 4
.value_kind: hidden_block_count_y
- .offset: 56
.size: 4
.value_kind: hidden_block_count_z
- .offset: 60
.size: 2
.value_kind: hidden_group_size_x
- .offset: 62
.size: 2
.value_kind: hidden_group_size_y
- .offset: 64
.size: 2
.value_kind: hidden_group_size_z
- .offset: 66
.size: 2
.value_kind: hidden_remainder_x
- .offset: 68
.size: 2
.value_kind: hidden_remainder_y
- .offset: 70
.size: 2
.value_kind: hidden_remainder_z
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 112
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 304
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13voronoiKernelPiiiiS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 42
.sgpr_spill_count: 0
.symbol: _Z13voronoiKernelPiiiiS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 52
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
```
| 7,304 | 19,427 |
129 |
Convert the following CUDA host assembly code to AMD host assembly:
```cudaasm
.file "tmpxft_00092caf_00000000-6_kernel.cudafe1.cpp"
.text
.globl _ZSt21ios_base_library_initv
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB4037:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4037:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z13eucludianDistiiii
.type _Z13eucludianDistiiii, @function
_Z13eucludianDistiiii:
.LFB4032:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE4032:
.size _Z13eucludianDistiiii, .-_Z13eucludianDistiiii
.globl _Z41__device_stub__Z13voronoiKernelPiiiiS_S_iPiiiiS_S_i
.type _Z41__device_stub__Z13voronoiKernelPiiiiS_S_iPiiiiS_S_i, @function
_Z41__device_stub__Z13voronoiKernelPiiiiS_S_iPiiiiS_S_i:
.LFB4059:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movl %esi, 36(%rsp)
movl %edx, 32(%rsp)
movl %ecx, 28(%rsp)
movq %r8, 16(%rsp)
movq %r9, 8(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 36(%rsp), %rax
movq %rax, 120(%rsp)
leaq 32(%rsp), %rax
movq %rax, 128(%rsp)
leaq 28(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 8(%rsp), %rax
movq %rax, 152(%rsp)
leaq 192(%rsp), %rax
movq %rax, 160(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L9
.L5:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L10
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L9:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z13voronoiKernelPiiiiS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L5
.L10:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4059:
.size _Z41__device_stub__Z13voronoiKernelPiiiiS_S_iPiiiiS_S_i, .-_Z41__device_stub__Z13voronoiKernelPiiiiS_S_iPiiiiS_S_i
.globl _Z13voronoiKernelPiiiiS_S_i
.type _Z13voronoiKernelPiiiiS_S_i, @function
_Z13voronoiKernelPiiiiS_S_i:
.LFB4060:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
call _Z41__device_stub__Z13voronoiKernelPiiiiS_S_iPiiiiS_S_i
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4060:
.size _Z13voronoiKernelPiiiiS_S_i, .-_Z13voronoiKernelPiiiiS_S_i
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "computing veronoi->Parallel..."
.section .rodata.str1.1,"aMS",@progbits,1
.LC5:
.string "done..."
.LC7:
.string "computation time(ms): "
.text
.globl _Z12voronoi_cudaPiRSt6vectorISt4pairIjjESaIS2_EEii
.type _Z12voronoi_cudaPiRSt6vectorISt4pairIjjESaIS2_EEii, @function
_Z12voronoi_cudaPiRSt6vectorISt4pairIjjESaIS2_EEii:
.LFB4033:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $120, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 8(%rsp)
movq %rsi, %rbx
movl %edx, (%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 32(%rsp), %rdi
call cudaEventCreate@PLT
leaq 40(%rsp), %rdi
call cudaEventCreate@PLT
movq 8(%rbx), %r13
movq (%rbx), %rbx
movq %r13, %r15
subq %rbx, %r15
sarq $3, %r15
leal 0(,%r15,4), %r14d
movslq %r14d, %r14
movq %r14, %rdi
call malloc@PLT
movq %rax, %r12
movq %r14, %rdi
call malloc@PLT
movq %rax, %rbp
cmpq %rbx, %r13
je .L14
subq $8, %r13
subq %rbx, %r13
shrq $3, %r13
leaq 4(,%r13,4), %rcx
movl $0, %eax
.L15:
movl (%rbx,%rax,2), %edx
movl %edx, (%r12,%rax)
movl 4(%rbx,%rax,2), %edx
movl %edx, 0(%rbp,%rax)
addq $4, %rax
cmpq %rcx, %rax
jne .L15
.L14:
movl $30, %edx
leaq .LC0(%rip), %rsi
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %rbx
testq %rbx, %rbx
je .L34
cmpb $0, 56(%rbx)
je .L18
movzbl 67(%rbx), %esi
.L19:
movsbl %sil, %esi
leaq _ZSt4cout(%rip), %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movslq 4(%rsp), %r13
movslq (%rsp), %rbx
salq $2, %rbx
leaq 72(%rsp), %rsi
leaq 48(%rsp), %rdi
movq %r13, %rcx
movq %rbx, %rdx
call cudaMallocPitch@PLT
movl $0, %esi
movq 32(%rsp), %rdi
call cudaEventRecord@PLT
leaq 56(%rsp), %rdi
movq %r14, %rsi
call cudaMalloc@PLT
leaq 64(%rsp), %rdi
movq %r14, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %r14, %rdx
movq %r12, %rsi
movq 56(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %r14, %rdx
movq %rbp, %rsi
movq 64(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, 88(%rsp)
pxor %xmm0, %xmm0
cvtsi2ssl 4(%rsp), %xmm0
mulss .LC1(%rip), %xmm0
movaps %xmm0, %xmm1
movss .LC8(%rip), %xmm3
movaps %xmm0, %xmm2
andps %xmm3, %xmm2
movss .LC2(%rip), %xmm4
ucomiss %xmm2, %xmm4
jbe .L20
cvttss2sil %xmm0, %eax
pxor %xmm2, %xmm2
cvtsi2ssl %eax, %xmm2
cmpnless %xmm2, %xmm1
movss .LC4(%rip), %xmm4
andps %xmm4, %xmm1
addss %xmm2, %xmm1
andnps %xmm0, %xmm3
orps %xmm3, %xmm1
.L20:
pxor %xmm0, %xmm0
cvtsi2ssl (%rsp), %xmm0
mulss .LC1(%rip), %xmm0
movaps %xmm0, %xmm4
movss .LC8(%rip), %xmm3
movaps %xmm0, %xmm2
andps %xmm3, %xmm2
movss .LC2(%rip), %xmm5
ucomiss %xmm2, %xmm5
jbe .L21
cvttss2sil %xmm0, %eax
pxor %xmm2, %xmm2
cvtsi2ssl %eax, %xmm2
cmpnless %xmm2, %xmm4
movss .LC4(%rip), %xmm5
andps %xmm5, %xmm4
addss %xmm2, %xmm4
andnps %xmm0, %xmm3
orps %xmm3, %xmm4
.L21:
cvttss2siq %xmm4, %rax
movl %eax, 92(%rsp)
cvttss2siq %xmm1, %rax
movl %eax, 96(%rsp)
movl $1, 100(%rsp)
movl $32, 80(%rsp)
movl $32, 84(%rsp)
movl 88(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 80(%rsp), %rdx
movq 92(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L35
.L22:
subq $8, %rsp
.cfi_def_cfa_offset 184
pushq $2
.cfi_def_cfa_offset 192
movq %r13, %r9
movq %rbx, %r8
movq 88(%rsp), %rcx
movq 64(%rsp), %rdx
movq %rbx, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy2D@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
call cudaDeviceSynchronize@PLT
movl $0, %esi
movq 40(%rsp), %rdi
call cudaEventRecord@PLT
movq 40(%rsp), %rdi
call cudaEventSynchronize@PLT
movl $7, %edx
leaq .LC5(%rip), %rsi
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %rbx
testq %rbx, %rbx
je .L36
cmpb $0, 56(%rbx)
je .L25
movzbl 67(%rbx), %esi
.L26:
movsbl %sil, %esi
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movl $0x00000000, 28(%rsp)
leaq 28(%rsp), %rdi
movq 40(%rsp), %rdx
movq 32(%rsp), %rsi
call cudaEventElapsedTime@PLT
movl $22, %edx
leaq .LC7(%rip), %rsi
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
pxor %xmm0, %xmm0
cvtss2sd 28(%rsp), %xmm0
movq %rbx, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rbx
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %r13
testq %r13, %r13
je .L37
cmpb $0, 56(%r13)
je .L29
movzbl 67(%r13), %esi
.L30:
movsbl %sil, %esi
movq %rbx, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movq 48(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rdi
call cudaFree@PLT
movq 64(%rsp), %rdi
call cudaFree@PLT
movq %r12, %rdi
call free@PLT
movq %rbp, %rdi
call free@PLT
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L38
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L34:
.cfi_restore_state
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L39
call _ZSt16__throw_bad_castv@PLT
.L39:
call __stack_chk_fail@PLT
.L18:
movq %rbx, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%rbx), %rax
movl $10, %esi
movq %rbx, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L19
.L35:
subq $8, %rsp
.cfi_def_cfa_offset 184
pushq %r15
.cfi_def_cfa_offset 192
movq 80(%rsp), %r9
movq 72(%rsp), %r8
movl 88(%rsp), %ecx
movl 20(%rsp), %edx
movl 16(%rsp), %esi
movq 64(%rsp), %rdi
call _Z41__device_stub__Z13voronoiKernelPiiiiS_S_iPiiiiS_S_i
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L22
.L36:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L40
call _ZSt16__throw_bad_castv@PLT
.L40:
call __stack_chk_fail@PLT
.L25:
movq %rbx, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%rbx), %rax
movl $10, %esi
movq %rbx, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L26
.L37:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L41
call _ZSt16__throw_bad_castv@PLT
.L41:
call __stack_chk_fail@PLT
.L29:
movq %r13, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq 0(%r13), %rax
movl $10, %esi
movq %r13, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L30
.L38:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4033:
.size _Z12voronoi_cudaPiRSt6vectorISt4pairIjjESaIS2_EEii, .-_Z12voronoi_cudaPiRSt6vectorISt4pairIjjESaIS2_EEii
.section .rodata.str1.1
.LC9:
.string "_Z13voronoiKernelPiiiiS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB4062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC9(%rip), %rdx
movq %rdx, %rcx
leaq _Z13voronoiKernelPiiiiS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4062:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC1:
.long 1023410176
.align 4
.LC2:
.long 1258291200
.align 4
.LC4:
.long 1065353216
.align 4
.LC8:
.long 2147483647
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
```
|
```amdasm
.text
.file "kernel.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z28__device_stub__voronoiKernelPiiiiS_S_i # -- Begin function _Z28__device_stub__voronoiKernelPiiiiS_S_i
.type _Z28__device_stub__voronoiKernelPiiiiS_S_i,@function
_Z28__device_stub__voronoiKernelPiiiiS_S_i: # @_Z28__device_stub__voronoiKernelPiiiiS_S_i
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $160, %rsp
.cfi_def_cfa_offset 208
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 56(%rsp), %rax
movq %rdi, (%rax)
leaq 20(%rsp), %rdi
movl %esi, (%rdi)
leaq 16(%rsp), %rsi
movl %edx, (%rsi)
leaq 12(%rsp), %rdx
movl %ecx, (%rdx)
leaq 48(%rsp), %rcx
movq %r8, (%rcx)
leaq 40(%rsp), %r8
movq %r9, (%r8)
leaq 96(%rsp), %rbx
movq %rax, (%rbx)
movq %rdi, 8(%rbx)
movq %rsi, 16(%rbx)
movq %rdx, 24(%rbx)
movq %rcx, 32(%rbx)
movq %r8, 40(%rbx)
leaq 208(%rsp), %rax
movq %rax, 48(%rbx)
leaq 80(%rsp), %r14
leaq 64(%rsp), %r15
leaq 32(%rsp), %r12
leaq 24(%rsp), %r13
movq %r14, %rdi
movq %r15, %rsi
movq %r12, %rdx
movq %r13, %rcx
callq __hipPopCallConfiguration
movq (%r14), %rsi
movl 8(%r14), %edx
movq (%r15), %rcx
movl 8(%r15), %r8d
movl $_Z13voronoiKernelPiiiiS_S_i, %edi
movq %rbx, %r9
pushq (%r13)
.cfi_adjust_cfa_offset 8
pushq (%r12)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $176, %rsp
.cfi_adjust_cfa_offset -176
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z28__device_stub__voronoiKernelPiiiiS_S_i, .Lfunc_end0-_Z28__device_stub__voronoiKernelPiiiiS_S_i
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function _Z12voronoi_cudaPiRSt6vectorISt4pairIjjESaIS2_EEii
.LCPI1_0:
.long 0x3d000000 # float 0.03125
.text
.globl _Z12voronoi_cudaPiRSt6vectorISt4pairIjjESaIS2_EEii
.type _Z12voronoi_cudaPiRSt6vectorISt4pairIjjESaIS2_EEii,@function
_Z12voronoi_cudaPiRSt6vectorISt4pairIjjESaIS2_EEii: # @_Z12voronoi_cudaPiRSt6vectorISt4pairIjjESaIS2_EEii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $104, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %ecx, 12(%rsp) # 4-byte Spill
movl %edx, %r13d
movq %rsi, %rbx
movq %rdi, 88(%rsp) # 8-byte Spill
leaq 64(%rsp), %rdi
callq hipEventCreate
leaq 32(%rsp), %rdi
callq hipEventCreate
movq (%rbx), %r15
movq 8(%rbx), %r12
movq %r12, %rax
subq %r15, %rax
shrq $3, %rax
movq %rax, 72(%rsp) # 8-byte Spill
leal (,%rax,4), %eax
movslq %eax, %rbp
movq %rbp, %rdi
callq malloc
movq %rax, %rbx
movq %rbp, %rdi
callq malloc
movq %rax, %r14
cmpq %r15, %r12
je .LBB1_3
# %bb.1: # %.lr.ph.preheader
xorl %eax, %eax
.LBB1_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
leaq (%r15,%rax,2), %rcx
addq $8, %rcx
movl -8(%rcx), %edx
movl %edx, (%rbx,%rax)
movl -4(%rcx), %edx
movl %edx, (%r14,%rax)
addq $4, %rax
cmpq %r12, %rcx
jne .LBB1_2
.LBB1_3: # %._crit_edge
movl $_ZSt4cout, %r15d
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $30, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rdi
addq %r15, %rdi
movl $10, %esi
callq _ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl %r13d, 44(%rsp) # 4-byte Spill
movslq %r13d, %r13
leaq (,%r13,4), %rdx
movslq 12(%rsp), %r12 # 4-byte Folded Reload
leaq 24(%rsp), %rdi
leaq 48(%rsp), %rsi
movq %rdx, 80(%rsp) # 8-byte Spill
movq %r12, %rcx
callq hipMallocPitch
movq 64(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
leaq 56(%rsp), %r15
movq %r15, %rdi
movq %rbp, %rsi
callq hipMalloc
leaq 16(%rsp), %rdi
movq %rbp, %rsi
callq hipMalloc
movq (%r15), %rdi
movq %rbx, %rsi
movq %rbp, %rdx
movl $1, %ecx
callq hipMemcpy
leaq 16(%rsp), %rax
movq (%rax), %rdi
movq %r14, %rsi
movq %rbp, %rdx
movl $1, %ecx
callq hipMemcpy
cvtsi2ss %r13d, %xmm0
mulss .LCPI1_0(%rip), %xmm0
callq ceilf@PLT
cvttss2si %xmm0, %r15
xorps %xmm0, %xmm0
cvtsi2ss %r12d, %xmm0
mulss .LCPI1_0(%rip), %xmm0
callq ceilf@PLT
cvttss2si %xmm0, %rdi
movl %r15d, %eax
shlq $32, %rdi
orq %rax, %rdi
movabsq $137438953504, %rdx # imm = 0x2000000020
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_5
# %bb.4:
movq 24(%rsp), %rdi
movl 48(%rsp), %ecx
movq 56(%rsp), %r8
movq 16(%rsp), %r9
movq 72(%rsp), %rax # 8-byte Reload
movl %eax, (%rsp)
movl 44(%rsp), %esi # 4-byte Reload
movl 12(%rsp), %edx # 4-byte Reload
callq _Z28__device_stub__voronoiKernelPiiiiS_S_i
.LBB1_5:
movq 24(%rsp), %rdx
movq 48(%rsp), %rcx
movl $2, (%rsp)
movq 88(%rsp), %rdi # 8-byte Reload
movq 80(%rsp), %rsi # 8-byte Reload
movq %rsi, %r8
movq %r12, %r9
callq hipMemcpy2D
callq hipDeviceSynchronize
movq 32(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 32(%rsp), %rdi
callq hipEventSynchronize
movl $_ZSt4cout, %edi
movl $.L.str.1, %esi
movl $7, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rdi
movl $_ZSt4cout, %eax
addq %rax, %rdi
movl $10, %esi
callq _ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
leaq 100(%rsp), %r15
movl $0, (%r15)
movq 64(%rsp), %rsi
movq 32(%rsp), %rdx
movq %r15, %rdi
callq hipEventElapsedTime
movl $_ZSt4cout, %edi
movl $.L.str.2, %esi
movl $22, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
xorps %xmm0, %xmm0
cvtss2sd (%r15), %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq %rax, %r15
movq (%rax), %rax
movq -24(%rax), %rdi
addq %r15, %rdi
movl $10, %esi
callq _ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
movsbl %al, %esi
movq %r15, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq 24(%rsp), %rdi
callq hipFree
movq 56(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
addq $104, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z12voronoi_cudaPiRSt6vectorISt4pairIjjESaIS2_EEii, .Lfunc_end1-_Z12voronoi_cudaPiRSt6vectorISt4pairIjjESaIS2_EEii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, %rdi
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13voronoiKernelPiiiiS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z13voronoiKernelPiiiiS_S_i,@object # @_Z13voronoiKernelPiiiiS_S_i
.section .rodata,"a",@progbits
.globl _Z13voronoiKernelPiiiiS_S_i
.p2align 3, 0x0
_Z13voronoiKernelPiiiiS_S_i:
.quad _Z28__device_stub__voronoiKernelPiiiiS_S_i
.size _Z13voronoiKernelPiiiiS_S_i, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "computing veronoi->Parallel..."
.size .L.str, 31
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "done..."
.size .L.str.1, 8
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "computation time(ms): "
.size .L.str.2, 23
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z13voronoiKernelPiiiiS_S_i"
.size .L__unnamed_1, 28
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z28__device_stub__voronoiKernelPiiiiS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z13voronoiKernelPiiiiS_S_i
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
```
| 6,226 | 5,243 |
130 |
Convert the following CUDA device assembly code to AMD device assembly:
```cudaasm
code for sm_80
Function : _Z4loopv
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ;
S2R R0, SR_TID.X ;
MOV R2, 0x0 ;
IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x8] ;
IADD3 R1, R1, -0x8, RZ ;
S2R R3, SR_CTAID.X ;
IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0xc] ;
IADD3 R6, P0, R1, c[0x0][0x20], RZ ;
IMAD.X R7, RZ, RZ, c[0x0][0x24], P0 ;
IMAD R0, R3, c[0x0][0x0], R0 ;
LDC.64 R2, c[0x4][R2] ;
STL [R1], R0 ;
LEPC R8 ;
MOV R11, 0x140 ;
MOV R20, 0xc0 ;
MOV R21, 0x0 ;
MOV R0, 0x0 ;
IADD3 R20, P0, P1, -R20, R11, R8 ;
IADD3.X R21, ~R0, R21, R9, P0, P1 ;
CALL.ABS.NOINC R2 ;
EXIT ;
BRA 0x150;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
```
|
```amdasm
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z4loopv ; -- Begin function _Z4loopv
.globl _Z4loopv
.p2align 8
.type _Z4loopv,@function
_Z4loopv: ; @_Z4loopv
; %bb.0:
s_clause 0x1
s_load_b32 s14, s[0:1], 0xc
s_load_b64 s[2:3], s[0:1], 0x50
v_mbcnt_lo_u32_b32 v29, -1, 0
v_mov_b32_e32 v7, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_dual_mov_b32 v8, 0 :: v_dual_mov_b32 v5, v29
;;#ASMSTART
;;#ASMEND
v_readfirstlane_b32 s0, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_eq_u32_e64 s0, s0, v5
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_6
; %bb.1:
v_mov_b32_e32 v1, 0
s_mov_b32 s4, exec_lo
s_waitcnt lgkmcnt(0)
global_load_b64 v[9:10], v1, s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
s_clause 0x1
global_load_b64 v[2:3], v1, s[2:3] offset:40
global_load_b64 v[6:7], v1, s[2:3]
s_waitcnt vmcnt(1)
v_and_b32_e32 v2, v2, v9
v_and_b32_e32 v3, v3, v10
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_hi_u32 v4, v2, 24
v_mul_lo_u32 v3, v3, 24
v_mul_lo_u32 v2, v2, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v3, v4, v3
s_waitcnt vmcnt(0)
v_add_co_u32 v2, vcc_lo, v6, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, v7, v3, vcc_lo
global_load_b64 v[7:8], v[2:3], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[7:8], v1, v[7:10], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmpx_ne_u64_e64 v[7:8], v[9:10]
s_cbranch_execz .LBB0_5
; %bb.2: ; %.preheader3.i.i.i.preheader
s_mov_b32 s5, 0
.LBB0_3: ; %.preheader3.i.i.i
; =>This Inner Loop Header: Depth=1
s_sleep 1
s_clause 0x1
global_load_b64 v[2:3], v1, s[2:3] offset:40
global_load_b64 v[11:12], v1, s[2:3]
v_dual_mov_b32 v10, v8 :: v_dual_mov_b32 v9, v7
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_and_b32_e32 v2, v2, v9
v_and_b32_e32 v8, v3, v10
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[6:7], null, v2, 24, v[11:12]
v_mov_b32_e32 v2, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[3:4], null, v8, 24, v[2:3]
v_mov_b32_e32 v7, v3
global_load_b64 v[7:8], v[6:7], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[7:8], v1, v[7:10], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmp_eq_u64_e32 vcc_lo, v[7:8], v[9:10]
s_or_b32 s5, vcc_lo, s5
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s5
s_cbranch_execnz .LBB0_3
; %bb.4: ; %Flow315
s_or_b32 exec_lo, exec_lo, s5
.LBB0_5: ; %Flow317
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s4
.LBB0_6: ; %.loopexit4.i.i.i
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s1
v_mov_b32_e32 v6, 0
v_readfirstlane_b32 s4, v7
v_readfirstlane_b32 s5, v8
s_mov_b32 s10, exec_lo
s_waitcnt lgkmcnt(0)
s_clause 0x1
global_load_b64 v[9:10], v6, s[2:3] offset:40
global_load_b128 v[1:4], v6, s[2:3]
s_waitcnt vmcnt(1)
v_readfirstlane_b32 s6, v9
v_readfirstlane_b32 s7, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b64 s[6:7], s[4:5], s[6:7]
s_mul_i32 s1, s7, 24
s_mul_hi_u32 s8, s6, 24
s_mul_i32 s9, s6, 24
s_and_saveexec_b32 s11, s0
s_cbranch_execz .LBB0_8
; %bb.7:
v_dual_mov_b32 v7, s10 :: v_dual_mov_b32 v8, v6
s_add_i32 s10, s8, s1
s_waitcnt vmcnt(0)
v_add_co_u32 v11, vcc_lo, v1, s9
v_add_co_ci_u32_e32 v12, vcc_lo, s10, v2, vcc_lo
v_dual_mov_b32 v9, 2 :: v_dual_mov_b32 v10, 1
global_store_b128 v[11:12], v[7:10], off offset:8
.LBB0_8:
s_or_b32 exec_lo, exec_lo, s11
s_lshl_b64 s[6:7], s[6:7], 12
v_lshlrev_b64 v[7:8], 6, v[5:6]
s_waitcnt vmcnt(0)
v_add_co_u32 v3, vcc_lo, v3, s6
v_add_co_ci_u32_e32 v4, vcc_lo, s7, v4, vcc_lo
s_mov_b32 s16, 0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_u32 v9, vcc_lo, v3, v7
s_mov_b32 s17, s16
s_mov_b32 s18, s16
s_mov_b32 s19, s16
v_add_co_ci_u32_e32 v10, vcc_lo, v4, v8, vcc_lo
v_dual_mov_b32 v5, 33 :: v_dual_mov_b32 v8, v6
v_mov_b32_e32 v7, v6
v_dual_mov_b32 v11, s16 :: v_dual_mov_b32 v14, s19
v_dual_mov_b32 v12, s17 :: v_dual_mov_b32 v13, s18
s_clause 0x3
global_store_b128 v[9:10], v[5:8], off
global_store_b128 v[9:10], v[11:14], off offset:16
global_store_b128 v[9:10], v[11:14], off offset:32
global_store_b128 v[9:10], v[11:14], off offset:48
s_and_saveexec_b32 s6, s0
s_cbranch_execz .LBB0_16
; %bb.9:
v_mov_b32_e32 v11, 0
s_mov_b32 s7, exec_lo
s_clause 0x1
global_load_b64 v[14:15], v11, s[2:3] offset:32 glc
global_load_b64 v[3:4], v11, s[2:3] offset:40
v_dual_mov_b32 v12, s4 :: v_dual_mov_b32 v13, s5
s_waitcnt vmcnt(0)
v_and_b32_e32 v4, s5, v4
v_and_b32_e32 v3, s4, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_lo_u32 v4, v4, 24
v_mul_hi_u32 v5, v3, 24
v_mul_lo_u32 v3, v3, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v4, v5, v4
v_add_co_u32 v7, vcc_lo, v1, v3
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v8, vcc_lo, v2, v4, vcc_lo
global_store_b64 v[7:8], v[14:15], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[5:6], v11, v[12:15], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmpx_ne_u64_e64 v[5:6], v[14:15]
s_cbranch_execz .LBB0_12
; %bb.10: ; %.preheader1.i.i.i.preheader
s_mov_b32 s10, 0
.LBB0_11: ; %.preheader1.i.i.i
; =>This Inner Loop Header: Depth=1
v_dual_mov_b32 v3, s4 :: v_dual_mov_b32 v4, s5
s_sleep 1
global_store_b64 v[7:8], v[5:6], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[3:4], v11, v[3:6], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[3:4], v[5:6]
v_dual_mov_b32 v6, v4 :: v_dual_mov_b32 v5, v3
s_or_b32 s10, vcc_lo, s10
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s10
s_cbranch_execnz .LBB0_11
.LBB0_12: ; %Flow313
s_or_b32 exec_lo, exec_lo, s7
v_mov_b32_e32 v6, 0
s_mov_b32 s10, exec_lo
s_mov_b32 s7, exec_lo
v_mbcnt_lo_u32_b32 v5, s10, 0
global_load_b64 v[3:4], v6, s[2:3] offset:16
v_cmpx_eq_u32_e32 0, v5
s_cbranch_execz .LBB0_14
; %bb.13:
s_bcnt1_i32_b32 s10, s10
s_delay_alu instid0(SALU_CYCLE_1)
v_mov_b32_e32 v5, s10
s_waitcnt vmcnt(0)
global_atomic_add_u64 v[3:4], v[5:6], off offset:8
.LBB0_14:
s_or_b32 exec_lo, exec_lo, s7
s_waitcnt vmcnt(0)
global_load_b64 v[5:6], v[3:4], off offset:16
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, 0, v[5:6]
s_cbranch_vccnz .LBB0_16
; %bb.15:
global_load_b32 v3, v[3:4], off offset:24
v_mov_b32_e32 v4, 0
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s7, v3
s_waitcnt_vscnt null, 0x0
global_store_b64 v[5:6], v[3:4], off
s_and_b32 m0, s7, 0xff
s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_16: ; %Flow314
s_or_b32 exec_lo, exec_lo, s6
s_add_i32 s8, s8, s1
v_add_co_u32 v1, vcc_lo, v1, s9
v_add_co_ci_u32_e32 v2, vcc_lo, s8, v2, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v1, vcc_lo, v1, 20
v_add_co_ci_u32_e32 v2, vcc_lo, 0, v2, vcc_lo
.LBB0_17: ; =>This Inner Loop Header: Depth=1
v_mov_b32_e32 v3, 1
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_19
; %bb.18: ; in Loop: Header=BB0_17 Depth=1
global_load_b32 v3, v[1:2], off glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_and_b32_e32 v3, 1, v3
.LBB0_19: ; in Loop: Header=BB0_17 Depth=1
s_or_b32 exec_lo, exec_lo, s1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s1, v3
s_cmp_eq_u32 s1, 0
s_cbranch_scc1 .LBB0_21
; %bb.20: ; in Loop: Header=BB0_17 Depth=1
s_mov_b32 s1, 0
s_sleep 1
s_branch .LBB0_22
.LBB0_21: ; in Loop: Header=BB0_17 Depth=1
s_mov_b32 s1, -1
.LBB0_22: ; %Flow308
; in Loop: Header=BB0_17 Depth=1
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 vcc_lo, exec_lo, s1
s_cbranch_vccnz .LBB0_17
; %bb.23:
global_load_b64 v[1:2], v[9:10], off
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_27
; %bb.24:
v_mov_b32_e32 v9, 0
s_clause 0x2
global_load_b64 v[5:6], v9, s[2:3] offset:40
global_load_b64 v[10:11], v9, s[2:3] offset:24 glc
global_load_b64 v[7:8], v9, s[2:3]
s_waitcnt vmcnt(2)
v_add_co_u32 v12, vcc_lo, v5, 1
v_add_co_ci_u32_e32 v13, vcc_lo, 0, v6, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v3, vcc_lo, v12, s4
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v13, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_eq_u64_e32 vcc_lo, 0, v[3:4]
v_dual_cndmask_b32 v4, v4, v13 :: v_dual_cndmask_b32 v3, v3, v12
v_and_b32_e32 v6, v4, v6
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_and_b32_e32 v5, v3, v5
v_mul_lo_u32 v6, v6, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_hi_u32 v12, v5, 24
v_mul_lo_u32 v5, v5, 24
v_add_nc_u32_e32 v6, v12, v6
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_co_u32 v7, vcc_lo, v7, v5
v_mov_b32_e32 v5, v10
v_add_co_ci_u32_e32 v8, vcc_lo, v8, v6, vcc_lo
v_mov_b32_e32 v6, v11
global_store_b64 v[7:8], v[10:11], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[5:6], v9, v[3:6], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_ne_u64_e32 vcc_lo, v[5:6], v[10:11]
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_27
; %bb.25: ; %.preheader.i.i.i.preheader
s_mov_b32 s0, 0
.LBB0_26: ; %.preheader.i.i.i
; =>This Inner Loop Header: Depth=1
s_sleep 1
global_store_b64 v[7:8], v[5:6], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[10:11], v9, v[3:6], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[10:11], v[5:6]
v_dual_mov_b32 v5, v10 :: v_dual_mov_b32 v6, v11
s_or_b32 s0, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s0
s_cbranch_execnz .LBB0_26
.LBB0_27: ; %__ockl_printf_begin.exit
s_or_b32 exec_lo, exec_lo, s1
s_getpc_b64 s[4:5]
s_add_u32 s4, s4, .str@rel32@lo+4
s_addc_u32 s5, s5, .str@rel32@hi+12
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_lg_u64 s[4:5], 0
s_cbranch_scc0 .LBB0_113
; %bb.28:
s_waitcnt vmcnt(0)
v_dual_mov_b32 v31, 0 :: v_dual_and_b32 v32, 2, v1
v_dual_mov_b32 v4, v2 :: v_dual_and_b32 v3, -3, v1
v_dual_mov_b32 v7, 2 :: v_dual_mov_b32 v8, 1
s_mov_b64 s[6:7], 29
.LBB0_29: ; =>This Loop Header: Depth=1
; Child Loop BB0_32 Depth 2
; Child Loop BB0_39 Depth 2
; Child Loop BB0_47 Depth 2
; Child Loop BB0_55 Depth 2
; Child Loop BB0_63 Depth 2
; Child Loop BB0_71 Depth 2
; Child Loop BB0_79 Depth 2
; Child Loop BB0_87 Depth 2
; Child Loop BB0_95 Depth 2
; Child Loop BB0_101 Depth 2
; Child Loop BB0_110 Depth 2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_lt_u64_e64 s0, s[6:7], 56
; implicit-def: $vgpr11_vgpr12
; implicit-def: $sgpr17
s_and_b32 s0, s0, exec_lo
s_cselect_b32 s8, s6, 56
s_cselect_b32 s9, s7, 0
s_cmp_gt_u32 s8, 7
s_mov_b32 s0, -1
s_cbranch_scc1 .LBB0_34
; %bb.30: ; in Loop: Header=BB0_29 Depth=1
v_mov_b32_e32 v11, 0
v_mov_b32_e32 v12, 0
s_cmp_eq_u32 s8, 0
s_cbranch_scc1 .LBB0_33
; %bb.31: ; %.preheader31.i.preheader
; in Loop: Header=BB0_29 Depth=1
s_lshl_b64 s[0:1], s[8:9], 3
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], s[4:5]
.LBB0_32: ; %.preheader31.i
; Parent Loop BB0_29 Depth=1
; => This Inner Loop Header: Depth=2
global_load_u8 v5, v31, s[12:13]
s_waitcnt vmcnt(0)
v_and_b32_e32 v30, 0xffff, v5
s_delay_alu instid0(VALU_DEP_1)
v_lshlrev_b64 v[5:6], s10, v[30:31]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_add_u32 s12, s12, 1
s_addc_u32 s13, s13, 0
s_cmp_lg_u32 s0, s10
v_or_b32_e32 v11, v5, v11
v_or_b32_e32 v12, v6, v12
s_cbranch_scc1 .LBB0_32
.LBB0_33: ; %Flow284
; in Loop: Header=BB0_29 Depth=1
s_mov_b32 s0, 0
s_mov_b32 s17, 0
.LBB0_34: ; %Flow286
; in Loop: Header=BB0_29 Depth=1
s_and_not1_b32 vcc_lo, exec_lo, s0
s_mov_b64 s[0:1], s[4:5]
s_cbranch_vccnz .LBB0_36
; %bb.35: ; in Loop: Header=BB0_29 Depth=1
global_load_b64 v[11:12], v31, s[4:5]
s_add_i32 s17, s8, -8
s_add_u32 s0, s4, 8
s_addc_u32 s1, s5, 0
.LBB0_36: ; %.loopexit32.i
; in Loop: Header=BB0_29 Depth=1
s_cmp_gt_u32 s17, 7
s_cbranch_scc1 .LBB0_41
; %bb.37: ; in Loop: Header=BB0_29 Depth=1
v_mov_b32_e32 v13, 0
v_mov_b32_e32 v14, 0
s_cmp_eq_u32 s17, 0
s_cbranch_scc1 .LBB0_40
; %bb.38: ; %.preheader29.i.preheader
; in Loop: Header=BB0_29 Depth=1
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_39: ; %.preheader29.i
; Parent Loop BB0_29 Depth=1
; => This Inner Loop Header: Depth=2
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s18, s0, s12
s_addc_u32 s19, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v5, v31, s[18:19]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v30, 0xffff, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[5:6], s10, v[30:31]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s17, s12
v_or_b32_e32 v13, v5, v13
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v14, v6, v14
s_cbranch_scc1 .LBB0_39
.LBB0_40: ; %Flow279
; in Loop: Header=BB0_29 Depth=1
s_mov_b32 s10, 0
s_mov_b32 s16, 0
s_branch .LBB0_42
.LBB0_41: ; in Loop: Header=BB0_29 Depth=1
s_mov_b32 s10, -1
; implicit-def: $vgpr13_vgpr14
; implicit-def: $sgpr16
.LBB0_42: ; %Flow281
; in Loop: Header=BB0_29 Depth=1
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 vcc_lo, exec_lo, s10
s_cbranch_vccnz .LBB0_44
; %bb.43: ; in Loop: Header=BB0_29 Depth=1
global_load_b64 v[13:14], v31, s[0:1]
s_add_i32 s16, s17, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_44: ; %.loopexit30.i
; in Loop: Header=BB0_29 Depth=1
s_cmp_gt_u32 s16, 7
s_cbranch_scc1 .LBB0_49
; %bb.45: ; in Loop: Header=BB0_29 Depth=1
v_mov_b32_e32 v15, 0
v_mov_b32_e32 v16, 0
s_cmp_eq_u32 s16, 0
s_cbranch_scc1 .LBB0_48
; %bb.46: ; %.preheader27.i.preheader
; in Loop: Header=BB0_29 Depth=1
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_47: ; %.preheader27.i
; Parent Loop BB0_29 Depth=1
; => This Inner Loop Header: Depth=2
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s18, s0, s12
s_addc_u32 s19, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v5, v31, s[18:19]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v30, 0xffff, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[5:6], s10, v[30:31]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s16, s12
v_or_b32_e32 v15, v5, v15
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v16, v6, v16
s_cbranch_scc1 .LBB0_47
.LBB0_48: ; %Flow274
; in Loop: Header=BB0_29 Depth=1
s_mov_b32 s10, 0
s_mov_b32 s17, 0
s_branch .LBB0_50
.LBB0_49: ; in Loop: Header=BB0_29 Depth=1
s_mov_b32 s10, -1
; implicit-def: $sgpr17
.LBB0_50: ; %Flow276
; in Loop: Header=BB0_29 Depth=1
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 vcc_lo, exec_lo, s10
s_cbranch_vccnz .LBB0_52
; %bb.51: ; in Loop: Header=BB0_29 Depth=1
global_load_b64 v[15:16], v31, s[0:1]
s_add_i32 s17, s16, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_52: ; %.loopexit28.i
; in Loop: Header=BB0_29 Depth=1
s_cmp_gt_u32 s17, 7
s_cbranch_scc1 .LBB0_57
; %bb.53: ; in Loop: Header=BB0_29 Depth=1
v_mov_b32_e32 v17, 0
v_mov_b32_e32 v18, 0
s_cmp_eq_u32 s17, 0
s_cbranch_scc1 .LBB0_56
; %bb.54: ; %.preheader25.i.preheader
; in Loop: Header=BB0_29 Depth=1
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_55: ; %.preheader25.i
; Parent Loop BB0_29 Depth=1
; => This Inner Loop Header: Depth=2
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s18, s0, s12
s_addc_u32 s19, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v5, v31, s[18:19]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v30, 0xffff, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[5:6], s10, v[30:31]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s17, s12
v_or_b32_e32 v17, v5, v17
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v18, v6, v18
s_cbranch_scc1 .LBB0_55
.LBB0_56: ; %Flow269
; in Loop: Header=BB0_29 Depth=1
s_mov_b32 s10, 0
s_mov_b32 s16, 0
s_branch .LBB0_58
.LBB0_57: ; in Loop: Header=BB0_29 Depth=1
s_mov_b32 s10, -1
; implicit-def: $vgpr17_vgpr18
; implicit-def: $sgpr16
.LBB0_58: ; %Flow271
; in Loop: Header=BB0_29 Depth=1
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 vcc_lo, exec_lo, s10
s_cbranch_vccnz .LBB0_60
; %bb.59: ; in Loop: Header=BB0_29 Depth=1
global_load_b64 v[17:18], v31, s[0:1]
s_add_i32 s16, s17, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_60: ; %.loopexit26.i
; in Loop: Header=BB0_29 Depth=1
s_cmp_gt_u32 s16, 7
s_cbranch_scc1 .LBB0_65
; %bb.61: ; in Loop: Header=BB0_29 Depth=1
v_mov_b32_e32 v19, 0
v_mov_b32_e32 v20, 0
s_cmp_eq_u32 s16, 0
s_cbranch_scc1 .LBB0_64
; %bb.62: ; %.preheader23.i.preheader
; in Loop: Header=BB0_29 Depth=1
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_63: ; %.preheader23.i
; Parent Loop BB0_29 Depth=1
; => This Inner Loop Header: Depth=2
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s18, s0, s12
s_addc_u32 s19, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v5, v31, s[18:19]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v30, 0xffff, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[5:6], s10, v[30:31]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s16, s12
v_or_b32_e32 v19, v5, v19
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v20, v6, v20
s_cbranch_scc1 .LBB0_63
.LBB0_64: ; %Flow264
; in Loop: Header=BB0_29 Depth=1
s_mov_b32 s10, 0
s_mov_b32 s17, 0
s_branch .LBB0_66
.LBB0_65: ; in Loop: Header=BB0_29 Depth=1
s_mov_b32 s10, -1
; implicit-def: $sgpr17
.LBB0_66: ; %Flow266
; in Loop: Header=BB0_29 Depth=1
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 vcc_lo, exec_lo, s10
s_cbranch_vccnz .LBB0_68
; %bb.67: ; in Loop: Header=BB0_29 Depth=1
global_load_b64 v[19:20], v31, s[0:1]
s_add_i32 s17, s16, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_68: ; %.loopexit24.i
; in Loop: Header=BB0_29 Depth=1
s_cmp_gt_u32 s17, 7
s_cbranch_scc1 .LBB0_73
; %bb.69: ; in Loop: Header=BB0_29 Depth=1
v_mov_b32_e32 v21, 0
v_mov_b32_e32 v22, 0
s_cmp_eq_u32 s17, 0
s_cbranch_scc1 .LBB0_72
; %bb.70: ; %.preheader21.i.preheader
; in Loop: Header=BB0_29 Depth=1
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_71: ; %.preheader21.i
; Parent Loop BB0_29 Depth=1
; => This Inner Loop Header: Depth=2
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s18, s0, s12
s_addc_u32 s19, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v5, v31, s[18:19]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v30, 0xffff, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[5:6], s10, v[30:31]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s17, s12
v_or_b32_e32 v21, v5, v21
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v22, v6, v22
s_cbranch_scc1 .LBB0_71
.LBB0_72: ; %Flow259
; in Loop: Header=BB0_29 Depth=1
s_mov_b32 s10, 0
s_mov_b32 s16, 0
s_branch .LBB0_74
.LBB0_73: ; in Loop: Header=BB0_29 Depth=1
s_mov_b32 s10, -1
; implicit-def: $vgpr21_vgpr22
; implicit-def: $sgpr16
.LBB0_74: ; %Flow261
; in Loop: Header=BB0_29 Depth=1
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 vcc_lo, exec_lo, s10
s_cbranch_vccnz .LBB0_76
; %bb.75: ; in Loop: Header=BB0_29 Depth=1
global_load_b64 v[21:22], v31, s[0:1]
s_add_i32 s16, s17, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_76: ; %.loopexit22.i
; in Loop: Header=BB0_29 Depth=1
s_cmp_gt_u32 s16, 7
s_cbranch_scc1 .LBB0_81
; %bb.77: ; in Loop: Header=BB0_29 Depth=1
v_mov_b32_e32 v23, 0
v_mov_b32_e32 v24, 0
s_cmp_eq_u32 s16, 0
s_cbranch_scc1 .LBB0_80
; %bb.78: ; %.preheader.i.preheader
; in Loop: Header=BB0_29 Depth=1
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], s[0:1]
.LBB0_79: ; %.preheader.i
; Parent Loop BB0_29 Depth=1
; => This Inner Loop Header: Depth=2
global_load_u8 v5, v31, s[12:13]
s_add_i32 s16, s16, -1
s_waitcnt vmcnt(0)
v_and_b32_e32 v30, 0xffff, v5
s_delay_alu instid0(VALU_DEP_1)
v_lshlrev_b64 v[5:6], s10, v[30:31]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_add_u32 s12, s12, 1
s_addc_u32 s13, s13, 0
s_cmp_lg_u32 s16, 0
v_or_b32_e32 v23, v5, v23
v_or_b32_e32 v24, v6, v24
s_cbranch_scc1 .LBB0_79
.LBB0_80: ; %Flow254
; in Loop: Header=BB0_29 Depth=1
s_mov_b32 s10, 0
s_branch .LBB0_82
.LBB0_81: ; in Loop: Header=BB0_29 Depth=1
s_mov_b32 s10, -1
.LBB0_82: ; %Flow256
; in Loop: Header=BB0_29 Depth=1
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 vcc_lo, exec_lo, s10
s_cbranch_vccnz .LBB0_84
; %bb.83: ; in Loop: Header=BB0_29 Depth=1
global_load_b64 v[23:24], v31, s[0:1]
.LBB0_84: ; %.loopexit.i
; in Loop: Header=BB0_29 Depth=1
s_waitcnt vmcnt(0)
v_dual_mov_b32 v30, v29 :: v_dual_mov_b32 v5, 0
;;#ASMSTART
;;#ASMEND
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_readfirstlane_b32 s0, v30
v_mov_b32_e32 v6, 0
v_cmp_eq_u32_e64 s0, s0, v30
s_delay_alu instid0(VALU_DEP_1)
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_90
; %bb.85: ; in Loop: Header=BB0_29 Depth=1
global_load_b64 v[27:28], v31, s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
s_clause 0x1
global_load_b64 v[5:6], v31, s[2:3] offset:40
global_load_b64 v[9:10], v31, s[2:3]
s_mov_b32 s10, exec_lo
s_waitcnt vmcnt(1)
v_and_b32_e32 v6, v6, v28
v_and_b32_e32 v5, v5, v27
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_lo_u32 v6, v6, 24
v_mul_hi_u32 v25, v5, 24
v_mul_lo_u32 v5, v5, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v6, v25, v6
s_waitcnt vmcnt(0)
v_add_co_u32 v5, vcc_lo, v9, v5
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v6, vcc_lo, v10, v6, vcc_lo
global_load_b64 v[25:26], v[5:6], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[5:6], v31, v[25:28], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmpx_ne_u64_e64 v[5:6], v[27:28]
s_cbranch_execz .LBB0_89
; %bb.86: ; %.preheader3.i.i19.i.preheader
; in Loop: Header=BB0_29 Depth=1
s_mov_b32 s11, 0
.LBB0_87: ; %.preheader3.i.i19.i
; Parent Loop BB0_29 Depth=1
; => This Inner Loop Header: Depth=2
s_sleep 1
s_clause 0x1
global_load_b64 v[9:10], v31, s[2:3] offset:40
global_load_b64 v[25:26], v31, s[2:3]
v_dual_mov_b32 v28, v6 :: v_dual_mov_b32 v27, v5
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_and_b32_e32 v9, v9, v27
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[5:6], null, v9, 24, v[25:26]
v_and_b32_e32 v25, v10, v28
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[9:10], null, v25, 24, v[6:7]
v_mov_b32_e32 v6, v9
global_load_b64 v[25:26], v[5:6], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[5:6], v31, v[25:28], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmp_eq_u64_e32 vcc_lo, v[5:6], v[27:28]
s_or_b32 s11, vcc_lo, s11
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s11
s_cbranch_execnz .LBB0_87
; %bb.88: ; %Flow249
; in Loop: Header=BB0_29 Depth=1
s_or_b32 exec_lo, exec_lo, s11
.LBB0_89: ; %Flow251
; in Loop: Header=BB0_29 Depth=1
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s10
.LBB0_90: ; %.loopexit4.i.i14.i
; in Loop: Header=BB0_29 Depth=1
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s1
s_clause 0x1
global_load_b64 v[9:10], v31, s[2:3] offset:40
global_load_b128 v[25:28], v31, s[2:3]
v_readfirstlane_b32 s10, v5
v_readfirstlane_b32 s11, v6
s_mov_b32 s18, exec_lo
s_waitcnt vmcnt(1)
v_readfirstlane_b32 s12, v9
v_readfirstlane_b32 s13, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b64 s[12:13], s[10:11], s[12:13]
s_mul_i32 s1, s13, 24
s_mul_hi_u32 s16, s12, 24
s_mul_i32 s17, s12, 24
s_and_saveexec_b32 s19, s0
s_cbranch_execz .LBB0_92
; %bb.91: ; in Loop: Header=BB0_29 Depth=1
v_dual_mov_b32 v5, s18 :: v_dual_mov_b32 v6, v31
s_add_i32 s18, s16, s1
s_waitcnt vmcnt(0)
v_add_co_u32 v9, vcc_lo, v25, s17
v_add_co_ci_u32_e32 v10, vcc_lo, s18, v26, vcc_lo
global_store_b128 v[9:10], v[5:8], off offset:8
.LBB0_92: ; in Loop: Header=BB0_29 Depth=1
s_or_b32 exec_lo, exec_lo, s19
v_cmp_gt_u64_e64 vcc_lo, s[6:7], 56
v_or_b32_e32 v5, 0, v4
v_or_b32_e32 v6, v3, v32
s_lshl_b64 s[12:13], s[12:13], 12
s_lshl_b32 s18, s8, 2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_add_i32 s18, s18, 28
v_dual_cndmask_b32 v10, v5, v4 :: v_dual_cndmask_b32 v5, v6, v3
v_lshlrev_b64 v[3:4], 6, v[30:31]
s_waitcnt vmcnt(0)
v_add_co_u32 v6, vcc_lo, v27, s12
v_add_co_ci_u32_e32 v28, vcc_lo, s13, v28, vcc_lo
s_and_b32 s18, s18, 0x1e0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_co_u32 v27, vcc_lo, v6, v3
v_and_or_b32 v9, 0xffffff1f, v5, s18
v_add_co_ci_u32_e32 v28, vcc_lo, v28, v4, vcc_lo
s_clause 0x3
global_store_b128 v[27:28], v[9:12], off
global_store_b128 v[27:28], v[13:16], off offset:16
global_store_b128 v[27:28], v[17:20], off offset:32
global_store_b128 v[27:28], v[21:24], off offset:48
s_and_saveexec_b32 s12, s0
s_cbranch_execz .LBB0_100
; %bb.93: ; in Loop: Header=BB0_29 Depth=1
s_clause 0x1
global_load_b64 v[13:14], v31, s[2:3] offset:32 glc
global_load_b64 v[3:4], v31, s[2:3] offset:40
v_dual_mov_b32 v11, s10 :: v_dual_mov_b32 v12, s11
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s18, v3
v_readfirstlane_b32 s19, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b64 s[18:19], s[18:19], s[10:11]
s_mul_i32 s13, s19, 24
s_mul_hi_u32 s19, s18, 24
s_mul_i32 s18, s18, 24
s_add_i32 s19, s19, s13
v_add_co_u32 v9, vcc_lo, v25, s18
v_add_co_ci_u32_e32 v10, vcc_lo, s19, v26, vcc_lo
s_mov_b32 s13, exec_lo
global_store_b64 v[9:10], v[13:14], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[5:6], v31, v[11:14], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmpx_ne_u64_e64 v[5:6], v[13:14]
s_cbranch_execz .LBB0_96
; %bb.94: ; %.preheader1.i.i17.i.preheader
; in Loop: Header=BB0_29 Depth=1
s_mov_b32 s18, 0
.LBB0_95: ; %.preheader1.i.i17.i
; Parent Loop BB0_29 Depth=1
; => This Inner Loop Header: Depth=2
v_dual_mov_b32 v3, s10 :: v_dual_mov_b32 v4, s11
s_sleep 1
global_store_b64 v[9:10], v[5:6], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[3:4], v31, v[3:6], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[3:4], v[5:6]
v_dual_mov_b32 v6, v4 :: v_dual_mov_b32 v5, v3
s_or_b32 s18, vcc_lo, s18
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s18
s_cbranch_execnz .LBB0_95
.LBB0_96: ; %Flow247
; in Loop: Header=BB0_29 Depth=1
s_or_b32 exec_lo, exec_lo, s13
global_load_b64 v[3:4], v31, s[2:3] offset:16
s_mov_b32 s18, exec_lo
s_mov_b32 s13, exec_lo
v_mbcnt_lo_u32_b32 v5, s18, 0
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_eq_u32_e32 0, v5
s_cbranch_execz .LBB0_98
; %bb.97: ; in Loop: Header=BB0_29 Depth=1
s_bcnt1_i32_b32 s18, s18
s_delay_alu instid0(SALU_CYCLE_1)
v_mov_b32_e32 v30, s18
s_waitcnt vmcnt(0)
global_atomic_add_u64 v[3:4], v[30:31], off offset:8
.LBB0_98: ; in Loop: Header=BB0_29 Depth=1
s_or_b32 exec_lo, exec_lo, s13
s_waitcnt vmcnt(0)
global_load_b64 v[5:6], v[3:4], off offset:16
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, 0, v[5:6]
s_cbranch_vccnz .LBB0_100
; %bb.99: ; in Loop: Header=BB0_29 Depth=1
global_load_b32 v30, v[3:4], off offset:24
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s13, v30
s_waitcnt_vscnt null, 0x0
global_store_b64 v[5:6], v[30:31], off
s_and_b32 m0, s13, 0xff
s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_100: ; %Flow248
; in Loop: Header=BB0_29 Depth=1
s_or_b32 exec_lo, exec_lo, s12
s_add_i32 s16, s16, s1
v_add_co_u32 v3, vcc_lo, v25, s17
v_add_co_ci_u32_e32 v4, vcc_lo, s16, v26, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v3, vcc_lo, v3, 20
v_add_co_ci_u32_e32 v4, vcc_lo, 0, v4, vcc_lo
.LBB0_101: ; Parent Loop BB0_29 Depth=1
; => This Inner Loop Header: Depth=2
v_mov_b32_e32 v5, 1
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_103
; %bb.102: ; in Loop: Header=BB0_101 Depth=2
global_load_b32 v5, v[3:4], off glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_and_b32_e32 v5, 1, v5
.LBB0_103: ; in Loop: Header=BB0_101 Depth=2
s_or_b32 exec_lo, exec_lo, s1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s1, v5
s_cmp_eq_u32 s1, 0
s_cbranch_scc1 .LBB0_105
; %bb.104: ; in Loop: Header=BB0_101 Depth=2
s_mov_b32 s1, 0
s_sleep 1
s_branch .LBB0_106
.LBB0_105: ; in Loop: Header=BB0_101 Depth=2
s_mov_b32 s1, -1
.LBB0_106: ; %Flow242
; in Loop: Header=BB0_101 Depth=2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 vcc_lo, exec_lo, s1
s_cbranch_vccnz .LBB0_101
; %bb.107: ; in Loop: Header=BB0_29 Depth=1
global_load_b128 v[3:6], v[27:28], off
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_111
; %bb.108: ; in Loop: Header=BB0_29 Depth=1
s_clause 0x2
global_load_b64 v[5:6], v31, s[2:3] offset:40
global_load_b64 v[13:14], v31, s[2:3] offset:24 glc
global_load_b64 v[11:12], v31, s[2:3]
s_waitcnt vmcnt(2)
v_add_co_u32 v15, vcc_lo, v5, 1
v_add_co_ci_u32_e32 v16, vcc_lo, 0, v6, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v9, vcc_lo, v15, s10
v_add_co_ci_u32_e32 v10, vcc_lo, s11, v16, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_eq_u64_e32 vcc_lo, 0, v[9:10]
v_dual_cndmask_b32 v10, v10, v16 :: v_dual_cndmask_b32 v9, v9, v15
v_and_b32_e32 v6, v10, v6
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_and_b32_e32 v5, v9, v5
v_mul_hi_u32 v15, v5, 24
v_mul_lo_u32 v5, v5, 24
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_add_co_u32 v5, vcc_lo, v11, v5
v_mov_b32_e32 v11, v13
v_mul_lo_u32 v6, v6, 24
v_add_nc_u32_e32 v6, v15, v6
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e32 v6, vcc_lo, v12, v6, vcc_lo
v_mov_b32_e32 v12, v14
global_store_b64 v[5:6], v[13:14], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[11:12], v31, v[9:12], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_ne_u64_e32 vcc_lo, v[11:12], v[13:14]
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_111
; %bb.109: ; %.preheader.i.i16.i.preheader
; in Loop: Header=BB0_29 Depth=1
s_mov_b32 s0, 0
.LBB0_110: ; %.preheader.i.i16.i
; Parent Loop BB0_29 Depth=1
; => This Inner Loop Header: Depth=2
s_sleep 1
global_store_b64 v[5:6], v[11:12], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[13:14], v31, v[9:12], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[13:14], v[11:12]
v_dual_mov_b32 v11, v13 :: v_dual_mov_b32 v12, v14
s_or_b32 s0, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s0
s_cbranch_execnz .LBB0_110
.LBB0_111: ; %__ockl_hostcall_preview.exit20.i
; in Loop: Header=BB0_29 Depth=1
s_or_b32 exec_lo, exec_lo, s1
s_sub_u32 s6, s6, s8
s_subb_u32 s7, s7, s9
s_add_u32 s4, s4, s8
s_addc_u32 s5, s5, s9
s_cmp_lg_u64 s[6:7], 0
s_cbranch_scc1 .LBB0_29
; %bb.112: ; %Flow287
s_mov_b32 s0, 0
s_branch .LBB0_114
.LBB0_113:
s_mov_b32 s0, -1
; implicit-def: $vgpr3_vgpr4
.LBB0_114: ; %Flow302
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 vcc_lo, exec_lo, s0
s_cbranch_vccz .LBB0_143
; %bb.115:
s_waitcnt vmcnt(0)
v_mov_b32_e32 v3, v29
v_mov_b32_e32 v9, 0
v_mov_b32_e32 v10, 0
;;#ASMSTART
;;#ASMEND
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s0, v3
v_cmp_eq_u32_e64 s0, s0, v3
s_delay_alu instid0(VALU_DEP_1)
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_121
; %bb.116:
v_mov_b32_e32 v4, 0
s_mov_b32 s4, exec_lo
global_load_b64 v[7:8], v4, s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
s_clause 0x1
global_load_b64 v[5:6], v4, s[2:3] offset:40
global_load_b64 v[9:10], v4, s[2:3]
s_waitcnt vmcnt(1)
v_and_b32_e32 v5, v5, v7
v_and_b32_e32 v6, v6, v8
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_hi_u32 v11, v5, 24
v_mul_lo_u32 v6, v6, 24
v_mul_lo_u32 v5, v5, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v6, v11, v6
s_waitcnt vmcnt(0)
v_add_co_u32 v5, vcc_lo, v9, v5
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v6, vcc_lo, v10, v6, vcc_lo
global_load_b64 v[5:6], v[5:6], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[9:10], v4, v[5:8], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmpx_ne_u64_e64 v[9:10], v[7:8]
s_cbranch_execz .LBB0_120
; %bb.117: ; %.preheader3.i.i.i6.preheader
s_mov_b32 s5, 0
.LBB0_118: ; %.preheader3.i.i.i6
; =>This Inner Loop Header: Depth=1
s_sleep 1
s_clause 0x1
global_load_b64 v[5:6], v4, s[2:3] offset:40
global_load_b64 v[11:12], v4, s[2:3]
v_dual_mov_b32 v7, v9 :: v_dual_mov_b32 v8, v10
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_and_b32_e32 v5, v5, v7
v_and_b32_e32 v6, v6, v8
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[9:10], null, v5, 24, v[11:12]
v_mov_b32_e32 v5, v10
s_delay_alu instid0(VALU_DEP_1)
v_mad_u64_u32 v[10:11], null, v6, 24, v[5:6]
global_load_b64 v[5:6], v[9:10], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[9:10], v4, v[5:8], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmp_eq_u64_e32 vcc_lo, v[9:10], v[7:8]
s_or_b32 s5, vcc_lo, s5
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s5
s_cbranch_execnz .LBB0_118
; %bb.119: ; %Flow299
s_or_b32 exec_lo, exec_lo, s5
.LBB0_120: ; %Flow301
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s4
.LBB0_121: ; %.loopexit4.i.i.i1
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s1
v_mov_b32_e32 v4, 0
v_readfirstlane_b32 s4, v9
v_readfirstlane_b32 s5, v10
s_mov_b32 s10, exec_lo
s_clause 0x1
global_load_b64 v[11:12], v4, s[2:3] offset:40
global_load_b128 v[5:8], v4, s[2:3]
s_waitcnt vmcnt(1)
v_readfirstlane_b32 s6, v11
v_readfirstlane_b32 s7, v12
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b64 s[6:7], s[4:5], s[6:7]
s_mul_i32 s1, s7, 24
s_mul_hi_u32 s8, s6, 24
s_mul_i32 s9, s6, 24
s_and_saveexec_b32 s11, s0
s_cbranch_execz .LBB0_123
; %bb.122:
v_dual_mov_b32 v9, s10 :: v_dual_mov_b32 v10, v4
s_add_i32 s10, s8, s1
s_waitcnt vmcnt(0)
v_add_co_u32 v13, vcc_lo, v5, s9
v_add_co_ci_u32_e32 v14, vcc_lo, s10, v6, vcc_lo
v_dual_mov_b32 v11, 2 :: v_dual_mov_b32 v12, 1
global_store_b128 v[13:14], v[9:12], off offset:8
.LBB0_123:
s_or_b32 exec_lo, exec_lo, s11
s_lshl_b64 s[6:7], s[6:7], 12
v_lshlrev_b64 v[9:10], 6, v[3:4]
s_waitcnt vmcnt(0)
v_add_co_u32 v3, vcc_lo, v7, s6
v_add_co_ci_u32_e32 v8, vcc_lo, s7, v8, vcc_lo
s_mov_b32 s16, 0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_u32 v7, vcc_lo, v3, v9
s_mov_b32 s17, s16
s_mov_b32 s18, s16
s_mov_b32 s19, s16
v_and_or_b32 v1, 0xffffff1f, v1, 32
v_add_co_ci_u32_e32 v8, vcc_lo, v8, v10, vcc_lo
v_mov_b32_e32 v3, v4
v_dual_mov_b32 v9, s16 :: v_dual_mov_b32 v12, s19
v_dual_mov_b32 v10, s17 :: v_dual_mov_b32 v11, s18
s_clause 0x3
global_store_b128 v[7:8], v[1:4], off
global_store_b128 v[7:8], v[9:12], off offset:16
global_store_b128 v[7:8], v[9:12], off offset:32
global_store_b128 v[7:8], v[9:12], off offset:48
s_and_saveexec_b32 s6, s0
s_cbranch_execz .LBB0_131
; %bb.124:
v_dual_mov_b32 v11, 0 :: v_dual_mov_b32 v12, s4
v_mov_b32_e32 v13, s5
s_clause 0x1
global_load_b64 v[14:15], v11, s[2:3] offset:32 glc
global_load_b64 v[1:2], v11, s[2:3] offset:40
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s10, v1
v_readfirstlane_b32 s11, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b64 s[10:11], s[10:11], s[4:5]
s_mul_i32 s7, s11, 24
s_mul_hi_u32 s11, s10, 24
s_mul_i32 s10, s10, 24
s_add_i32 s11, s11, s7
v_add_co_u32 v9, vcc_lo, v5, s10
v_add_co_ci_u32_e32 v10, vcc_lo, s11, v6, vcc_lo
s_mov_b32 s7, exec_lo
global_store_b64 v[9:10], v[14:15], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[3:4], v11, v[12:15], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmpx_ne_u64_e64 v[3:4], v[14:15]
s_cbranch_execz .LBB0_127
; %bb.125: ; %.preheader1.i.i.i4.preheader
s_mov_b32 s10, 0
.LBB0_126: ; %.preheader1.i.i.i4
; =>This Inner Loop Header: Depth=1
v_dual_mov_b32 v1, s4 :: v_dual_mov_b32 v2, s5
s_sleep 1
global_store_b64 v[9:10], v[3:4], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[1:2], v11, v[1:4], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[1:2], v[3:4]
v_dual_mov_b32 v4, v2 :: v_dual_mov_b32 v3, v1
s_or_b32 s10, vcc_lo, s10
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s10
s_cbranch_execnz .LBB0_126
.LBB0_127: ; %Flow297
s_or_b32 exec_lo, exec_lo, s7
v_mov_b32_e32 v4, 0
s_mov_b32 s10, exec_lo
s_mov_b32 s7, exec_lo
v_mbcnt_lo_u32_b32 v3, s10, 0
global_load_b64 v[1:2], v4, s[2:3] offset:16
v_cmpx_eq_u32_e32 0, v3
s_cbranch_execz .LBB0_129
; %bb.128:
s_bcnt1_i32_b32 s10, s10
s_delay_alu instid0(SALU_CYCLE_1)
v_mov_b32_e32 v3, s10
s_waitcnt vmcnt(0)
global_atomic_add_u64 v[1:2], v[3:4], off offset:8
.LBB0_129:
s_or_b32 exec_lo, exec_lo, s7
s_waitcnt vmcnt(0)
global_load_b64 v[3:4], v[1:2], off offset:16
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, 0, v[3:4]
s_cbranch_vccnz .LBB0_131
; %bb.130:
global_load_b32 v1, v[1:2], off offset:24
v_mov_b32_e32 v2, 0
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s7, v1
s_waitcnt_vscnt null, 0x0
global_store_b64 v[3:4], v[1:2], off
s_and_b32 m0, s7, 0xff
s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_131: ; %Flow298
s_or_b32 exec_lo, exec_lo, s6
s_add_i32 s8, s8, s1
v_add_co_u32 v1, vcc_lo, v5, s9
v_add_co_ci_u32_e32 v2, vcc_lo, s8, v6, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v1, vcc_lo, v1, 20
v_add_co_ci_u32_e32 v2, vcc_lo, 0, v2, vcc_lo
.LBB0_132: ; =>This Inner Loop Header: Depth=1
v_mov_b32_e32 v3, 1
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_134
; %bb.133: ; in Loop: Header=BB0_132 Depth=1
global_load_b32 v3, v[1:2], off glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_and_b32_e32 v3, 1, v3
.LBB0_134: ; in Loop: Header=BB0_132 Depth=1
s_or_b32 exec_lo, exec_lo, s1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s1, v3
s_cmp_eq_u32 s1, 0
s_cbranch_scc1 .LBB0_136
; %bb.135: ; in Loop: Header=BB0_132 Depth=1
s_mov_b32 s1, 0
s_sleep 1
s_branch .LBB0_137
.LBB0_136: ; in Loop: Header=BB0_132 Depth=1
s_mov_b32 s1, -1
.LBB0_137: ; %Flow292
; in Loop: Header=BB0_132 Depth=1
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 vcc_lo, exec_lo, s1
s_cbranch_vccnz .LBB0_132
; %bb.138:
global_load_b128 v[3:6], v[7:8], off
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_142
; %bb.139:
v_mov_b32_e32 v9, 0
s_clause 0x2
global_load_b64 v[1:2], v9, s[2:3] offset:40
global_load_b64 v[10:11], v9, s[2:3] offset:24 glc
global_load_b64 v[7:8], v9, s[2:3]
s_waitcnt vmcnt(2)
v_add_co_u32 v12, vcc_lo, v1, 1
v_add_co_ci_u32_e32 v13, vcc_lo, 0, v2, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v5, vcc_lo, v12, s4
v_add_co_ci_u32_e32 v6, vcc_lo, s5, v13, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_eq_u64_e32 vcc_lo, 0, v[5:6]
v_dual_cndmask_b32 v6, v6, v13 :: v_dual_cndmask_b32 v5, v5, v12
v_and_b32_e32 v2, v6, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_and_b32_e32 v1, v5, v1
v_mul_lo_u32 v2, v2, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_hi_u32 v12, v1, 24
v_mul_lo_u32 v1, v1, 24
v_add_nc_u32_e32 v2, v12, v2
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_co_u32 v1, vcc_lo, v7, v1
v_mov_b32_e32 v7, v10
v_add_co_ci_u32_e32 v2, vcc_lo, v8, v2, vcc_lo
v_mov_b32_e32 v8, v11
global_store_b64 v[1:2], v[10:11], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[7:8], v9, v[5:8], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_ne_u64_e32 vcc_lo, v[7:8], v[10:11]
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_142
; %bb.140: ; %.preheader.i.i.i3.preheader
s_mov_b32 s0, 0
.LBB0_141: ; %.preheader.i.i.i3
; =>This Inner Loop Header: Depth=1
s_sleep 1
global_store_b64 v[1:2], v[7:8], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[10:11], v9, v[5:8], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[10:11], v[7:8]
v_dual_mov_b32 v7, v10 :: v_dual_mov_b32 v8, v11
s_or_b32 s0, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s0
s_cbranch_execnz .LBB0_141
.LBB0_142: ; %__ockl_hostcall_preview.exit.i
s_or_b32 exec_lo, exec_lo, s1
.LBB0_143: ; %__ockl_printf_append_string_n.exit
;;#ASMSTART
;;#ASMEND
v_readfirstlane_b32 s0, v29
s_waitcnt vmcnt(0)
v_mov_b32_e32 v1, 0
v_mov_b32_e32 v2, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_eq_u32_e64 s0, s0, v29
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_149
; %bb.144:
v_mov_b32_e32 v5, 0
s_mov_b32 s4, exec_lo
global_load_b64 v[8:9], v5, s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
s_clause 0x1
global_load_b64 v[1:2], v5, s[2:3] offset:40
global_load_b64 v[6:7], v5, s[2:3]
s_waitcnt vmcnt(1)
v_and_b32_e32 v2, v2, v9
v_and_b32_e32 v1, v1, v8
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_lo_u32 v2, v2, 24
v_mul_hi_u32 v10, v1, 24
v_mul_lo_u32 v1, v1, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v2, v10, v2
s_waitcnt vmcnt(0)
v_add_co_u32 v1, vcc_lo, v6, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, v7, v2, vcc_lo
global_load_b64 v[6:7], v[1:2], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[1:2], v5, v[6:9], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmpx_ne_u64_e64 v[1:2], v[8:9]
s_cbranch_execz .LBB0_148
; %bb.145: ; %.preheader3.i.i.i13.preheader
s_mov_b32 s5, 0
.LBB0_146: ; %.preheader3.i.i.i13
; =>This Inner Loop Header: Depth=1
s_sleep 1
s_clause 0x1
global_load_b64 v[6:7], v5, s[2:3] offset:40
global_load_b64 v[10:11], v5, s[2:3]
v_dual_mov_b32 v9, v2 :: v_dual_mov_b32 v8, v1
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_and_b32_e32 v6, v6, v8
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[1:2], null, v6, 24, v[10:11]
v_and_b32_e32 v10, v7, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[6:7], null, v10, 24, v[2:3]
v_mov_b32_e32 v2, v6
global_load_b64 v[6:7], v[1:2], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[1:2], v5, v[6:9], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmp_eq_u64_e32 vcc_lo, v[1:2], v[8:9]
s_or_b32 s5, vcc_lo, s5
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s5
s_cbranch_execnz .LBB0_146
; %bb.147: ; %Flow235
s_or_b32 exec_lo, exec_lo, s5
.LBB0_148: ; %Flow237
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s4
.LBB0_149: ; %.loopexit4.i.i.i7
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s1
v_mov_b32_e32 v30, 0
v_readfirstlane_b32 s4, v1
v_readfirstlane_b32 s5, v2
s_mov_b32 s10, exec_lo
s_clause 0x1
global_load_b64 v[5:6], v30, s[2:3] offset:40
global_load_b128 v[7:10], v30, s[2:3]
s_waitcnt vmcnt(1)
v_readfirstlane_b32 s6, v5
v_readfirstlane_b32 s7, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b64 s[6:7], s[4:5], s[6:7]
s_mul_i32 s1, s7, 24
s_mul_hi_u32 s8, s6, 24
s_mul_i32 s9, s6, 24
s_and_saveexec_b32 s11, s0
s_cbranch_execz .LBB0_151
; %bb.150:
v_dual_mov_b32 v11, s10 :: v_dual_mov_b32 v12, v30
s_add_i32 s10, s8, s1
s_waitcnt vmcnt(0)
v_add_co_u32 v1, vcc_lo, v7, s9
v_add_co_ci_u32_e32 v2, vcc_lo, s10, v8, vcc_lo
v_dual_mov_b32 v13, 2 :: v_dual_mov_b32 v14, 1
global_store_b128 v[1:2], v[11:14], off offset:8
.LBB0_151:
s_or_b32 exec_lo, exec_lo, s11
s_lshl_b64 s[6:7], s[6:7], 12
v_lshlrev_b64 v[1:2], 6, v[29:30]
s_waitcnt vmcnt(0)
v_add_co_u32 v9, vcc_lo, v9, s6
v_add_co_ci_u32_e32 v10, vcc_lo, s7, v10, vcc_lo
s_and_b32 s6, 0xffff, s14
s_mov_b32 s12, 0
v_mad_u64_u32 v[5:6], null, s15, s6, v[0:1]
v_add_co_u32 v0, vcc_lo, v9, v1
s_mov_b32 s13, s12
s_mov_b32 s14, s12
s_mov_b32 s15, s12
v_and_or_b32 v3, 0xffffff1d, v3, 34
v_add_co_ci_u32_e32 v1, vcc_lo, v10, v2, vcc_lo
v_dual_mov_b32 v6, v30 :: v_dual_mov_b32 v9, s12
v_dual_mov_b32 v10, s13 :: v_dual_mov_b32 v11, s14
v_mov_b32_e32 v12, s15
s_clause 0x3
global_store_b128 v[0:1], v[3:6], off
global_store_b128 v[0:1], v[9:12], off offset:16
global_store_b128 v[0:1], v[9:12], off offset:32
global_store_b128 v[0:1], v[9:12], off offset:48
s_and_saveexec_b32 s6, s0
s_cbranch_execz .LBB0_159
; %bb.152:
v_dual_mov_b32 v6, 0 :: v_dual_mov_b32 v9, s4
v_mov_b32_e32 v10, s5
s_clause 0x1
global_load_b64 v[11:12], v6, s[2:3] offset:32 glc
global_load_b64 v[0:1], v6, s[2:3] offset:40
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s10, v0
v_readfirstlane_b32 s11, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b64 s[10:11], s[10:11], s[4:5]
s_mul_i32 s7, s11, 24
s_mul_hi_u32 s11, s10, 24
s_mul_i32 s10, s10, 24
s_add_i32 s11, s11, s7
v_add_co_u32 v4, vcc_lo, v7, s10
v_add_co_ci_u32_e32 v5, vcc_lo, s11, v8, vcc_lo
s_mov_b32 s7, exec_lo
global_store_b64 v[4:5], v[11:12], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v6, v[9:12], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmpx_ne_u64_e64 v[2:3], v[11:12]
s_cbranch_execz .LBB0_155
; %bb.153: ; %.preheader1.i.i.i11.preheader
s_mov_b32 s10, 0
.LBB0_154: ; %.preheader1.i.i.i11
; =>This Inner Loop Header: Depth=1
v_dual_mov_b32 v0, s4 :: v_dual_mov_b32 v1, s5
s_sleep 1
global_store_b64 v[4:5], v[2:3], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[0:1], v6, v[0:3], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[0:1], v[2:3]
v_dual_mov_b32 v3, v1 :: v_dual_mov_b32 v2, v0
s_or_b32 s10, vcc_lo, s10
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s10
s_cbranch_execnz .LBB0_154
.LBB0_155: ; %Flow233
s_or_b32 exec_lo, exec_lo, s7
v_mov_b32_e32 v3, 0
s_mov_b32 s10, exec_lo
s_mov_b32 s7, exec_lo
v_mbcnt_lo_u32_b32 v2, s10, 0
global_load_b64 v[0:1], v3, s[2:3] offset:16
v_cmpx_eq_u32_e32 0, v2
s_cbranch_execz .LBB0_157
; %bb.156:
s_bcnt1_i32_b32 s10, s10
s_delay_alu instid0(SALU_CYCLE_1)
v_mov_b32_e32 v2, s10
s_waitcnt vmcnt(0)
global_atomic_add_u64 v[0:1], v[2:3], off offset:8
.LBB0_157:
s_or_b32 exec_lo, exec_lo, s7
s_waitcnt vmcnt(0)
global_load_b64 v[2:3], v[0:1], off offset:16
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, 0, v[2:3]
s_cbranch_vccnz .LBB0_159
; %bb.158:
global_load_b32 v0, v[0:1], off offset:24
v_mov_b32_e32 v1, 0
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s7, v0
s_waitcnt_vscnt null, 0x0
global_store_b64 v[2:3], v[0:1], off
s_and_b32 m0, s7, 0xff
s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_159: ; %Flow234
s_or_b32 exec_lo, exec_lo, s6
s_add_i32 s8, s8, s1
v_add_co_u32 v0, vcc_lo, v7, s9
v_add_co_ci_u32_e32 v1, vcc_lo, s8, v8, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v0, 20
v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
.LBB0_160: ; =>This Inner Loop Header: Depth=1
v_mov_b32_e32 v2, 1
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_162
; %bb.161: ; in Loop: Header=BB0_160 Depth=1
global_load_b32 v2, v[0:1], off glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_and_b32_e32 v2, 1, v2
.LBB0_162: ; in Loop: Header=BB0_160 Depth=1
s_or_b32 exec_lo, exec_lo, s1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s1, v2
s_cmp_eq_u32 s1, 0
s_cbranch_scc1 .LBB0_164
; %bb.163: ; in Loop: Header=BB0_160 Depth=1
s_mov_b32 s1, 0
s_sleep 1
s_branch .LBB0_165
.LBB0_164: ; in Loop: Header=BB0_160 Depth=1
s_mov_b32 s1, -1
.LBB0_165: ; %Flow228
; in Loop: Header=BB0_160 Depth=1
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 vcc_lo, exec_lo, s1
s_cbranch_vccnz .LBB0_160
; %bb.166:
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_170
; %bb.167:
v_mov_b32_e32 v6, 0
s_clause 0x2
global_load_b64 v[2:3], v6, s[2:3] offset:40
global_load_b64 v[7:8], v6, s[2:3] offset:24 glc
global_load_b64 v[4:5], v6, s[2:3]
s_waitcnt vmcnt(2)
v_add_co_u32 v9, vcc_lo, v2, 1
v_add_co_ci_u32_e32 v10, vcc_lo, 0, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v9, s4
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v10, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_eq_u64_e32 vcc_lo, 0, v[0:1]
v_dual_cndmask_b32 v1, v1, v10 :: v_dual_cndmask_b32 v0, v0, v9
v_and_b32_e32 v3, v1, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_and_b32_e32 v2, v0, v2
v_mul_lo_u32 v3, v3, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_hi_u32 v9, v2, 24
v_mul_lo_u32 v2, v2, 24
v_add_nc_u32_e32 v3, v9, v3
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_co_u32 v4, vcc_lo, v4, v2
v_mov_b32_e32 v2, v7
v_add_co_ci_u32_e32 v5, vcc_lo, v5, v3, vcc_lo
v_mov_b32_e32 v3, v8
global_store_b64 v[4:5], v[7:8], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v6, v[0:3], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_ne_u64_e32 vcc_lo, v[2:3], v[7:8]
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_170
; %bb.168: ; %.preheader.i.i.i10.preheader
s_mov_b32 s0, 0
.LBB0_169: ; %.preheader.i.i.i10
; =>This Inner Loop Header: Depth=1
s_sleep 1
global_store_b64 v[4:5], v[2:3], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[7:8], v6, v[0:3], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[7:8], v[2:3]
v_dual_mov_b32 v2, v7 :: v_dual_mov_b32 v3, v8
s_or_b32 s0, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s0
s_cbranch_execnz .LBB0_169
.LBB0_170: ; %__ockl_printf_append_args.exit
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z4loopv
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 256
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 33
.amdhsa_next_free_sgpr 20
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z4loopv, .Lfunc_end0-_Z4loopv
; -- End function
.section .AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 6692
; NumSgprs: 22
; NumVgprs: 33
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 4
; NumSGPRsForWavesPerEU: 22
; NumVGPRsForWavesPerEU: 33
; Occupancy: 16
; WaveLimiterHint : 1
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type .str,@object ; @.str
.section .rodata.str1.1,"aMS",@progbits,1
.str:
.asciz "This is iteration number %d\n"
.size .str, 29
.type __hip_cuid_,@object ; @__hip_cuid_
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0 ; 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: hidden_block_count_x
- .offset: 4
.size: 4
.value_kind: hidden_block_count_y
- .offset: 8
.size: 4
.value_kind: hidden_block_count_z
- .offset: 12
.size: 2
.value_kind: hidden_group_size_x
- .offset: 14
.size: 2
.value_kind: hidden_group_size_y
- .offset: 16
.size: 2
.value_kind: hidden_group_size_z
- .offset: 18
.size: 2
.value_kind: hidden_remainder_x
- .offset: 20
.size: 2
.value_kind: hidden_remainder_y
- .offset: 22
.size: 2
.value_kind: hidden_remainder_z
- .offset: 40
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 48
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 64
.size: 2
.value_kind: hidden_grid_dims
- .offset: 80
.size: 8
.value_kind: hidden_hostcall_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 256
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z4loopv
.private_segment_fixed_size: 0
.sgpr_count: 22
.sgpr_spill_count: 0
.symbol: _Z4loopv.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 33
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
```
| 431 | 29,093 |
131 |
Convert the following CUDA host assembly code to AMD host assembly:
```cudaasm
.file "tmpxft_000257a8_00000000-6_02-multi-block-loop.cudafe1.cpp"
.text
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z22__device_stub__Z4loopvv
.type _Z22__device_stub__Z4loopvv, @function
_Z22__device_stub__Z4loopvv:
.LFB2082:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z4loopv(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z22__device_stub__Z4loopvv, .-_Z22__device_stub__Z4loopvv
.globl _Z4loopv
.type _Z4loopv, @function
_Z4loopv:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z22__device_stub__Z4loopvv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z4loopv, .-_Z4loopv
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
movl $5, 20(%rsp)
movl $1, 24(%rsp)
movl $2, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L14
.L12:
call cudaDeviceSynchronize@PLT
movl $0, %eax
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
call _Z22__device_stub__Z4loopvv
jmp .L12
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z4loopv"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z4loopv(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
```
|
```amdasm
.text
.file "02-multi-block-loop.hip"
.globl _Z19__device_stub__loopv # -- Begin function _Z19__device_stub__loopv
.type _Z19__device_stub__loopv,@function
_Z19__device_stub__loopv: # @_Z19__device_stub__loopv
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $56, %rsp
.cfi_def_cfa_offset 96
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 40(%rsp), %rbx
leaq 24(%rsp), %r14
leaq 16(%rsp), %r15
leaq 8(%rsp), %r12
movq %rbx, %rdi
movq %r14, %rsi
movq %r15, %rdx
movq %r12, %rcx
callq __hipPopCallConfiguration
movq (%rbx), %rsi
movl 8(%rbx), %edx
movq (%r14), %rcx
movl 8(%r14), %r8d
movq %rsp, %r9
movl $_Z4loopv, %edi
pushq (%r12)
.cfi_adjust_cfa_offset 8
pushq (%r15)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z19__device_stub__loopv, .Lfunc_end0-_Z19__device_stub__loopv
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
movabsq $4294967298, %rdi # imm = 0x100000002
leaq 3(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
callq _Z19__device_stub__loopv
.LBB1_2:
callq hipDeviceSynchronize
xorl %eax, %eax
popq %rcx
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, %rdi
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z4loopv, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z4loopv,@object # @_Z4loopv
.section .rodata,"a",@progbits
.globl _Z4loopv
.p2align 3, 0x0
_Z4loopv:
.quad _Z19__device_stub__loopv
.size _Z4loopv, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z4loopv"
.size .L__unnamed_1, 9
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z19__device_stub__loopv
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z4loopv
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
```
| 1,928 | 2,037 |
132 |
Convert the following CUDA device assembly code to AMD device assembly:
```cudaasm
code for sm_80
```
|
```amdasm
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object ; @__hip_cuid_
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0 ; 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
```
| 24 | 306 |
133 |
Convert the following CUDA host assembly code to AMD host assembly:
```cudaasm
.file "tmpxft_00113739_00000000-6_properties.cudafe1.cpp"
.text
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "name:%s\n"
.LC1:
.string "memory:%ld\n"
.LC2:
.string "warpsize:%d\n"
.LC3:
.string "max threads per block:%d\n"
.LC4:
.string "clock rate:%d\n"
.LC5:
.string "multiProcessorCount %d\n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC6:
.string "maxThreadsPerMultiProcessor %d\n"
.text
.globl _Z19list_env_propertiesv
.type _Z19list_env_propertiesv, @function
_Z19list_env_propertiesv:
.LFB2058:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $1056, %rsp
.cfi_def_cfa_offset 1104
movq %fs:40, %rax
movq %rax, 1048(%rsp)
xorl %eax, %eax
leaq 12(%rsp), %rdi
call cudaGetDeviceCount@PLT
testl %eax, %eax
jne .L3
cmpl $0, 12(%rsp)
jle .L3
movl $0, %ebx
leaq .LC0(%rip), %r14
leaq .LC1(%rip), %r13
leaq .LC2(%rip), %r12
leaq .LC3(%rip), %rbp
jmp .L6
.L5:
addl $1, %ebx
cmpl %ebx, 12(%rsp)
jle .L3
.L6:
leaq 16(%rsp), %rdi
movl %ebx, %esi
call cudaGetDeviceProperties_v2@PLT
cmpl $9999, 376(%rsp)
je .L5
testl %ebx, %ebx
jne .L5
leaq 16(%rsp), %rdx
movq %r14, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 304(%rsp), %rdx
movq %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 324(%rsp), %edx
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 336(%rsp), %edx
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 364(%rsp), %edx
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 404(%rsp), %edx
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 640(%rsp), %edx
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L5
.L3:
movq 1048(%rsp), %rax
subq %fs:40, %rax
jne .L10
addq $1056, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L10:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size _Z19list_env_propertiesv, .-_Z19list_env_propertiesv
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z19list_env_propertiesv
movl $0, %eax
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
```
|
```amdasm
.text
.file "properties.hip"
.globl main # -- Begin function main
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
callq _Z19list_env_propertiesv
xorl %eax, %eax
popq %rcx
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.globl _Z19list_env_propertiesv # -- Begin function _Z19list_env_propertiesv
.type _Z19list_env_propertiesv,@function
_Z19list_env_propertiesv: # @_Z19list_env_propertiesv
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $1480, %rsp # imm = 0x5C8
.cfi_def_cfa_offset 1504
.cfi_offset %rbx, -24
.cfi_offset %rbp, -16
leaq 4(%rsp), %rdi
callq hipGetDeviceCount
testl %eax, %eax
jne .LBB1_7
# %bb.1:
cmpl $0, 4(%rsp)
jle .LBB1_7
# %bb.2: # %.lr.ph
leaq 8(%rsp), %rbx
xorl %ebp, %ebp
.LBB1_3: # =>This Inner Loop Header: Depth=1
movq %rbx, %rdi
movl %ebp, %esi
callq hipGetDevicePropertiesR0600
testl %ebp, %ebp
jne .LBB1_6
# %bb.4: # in Loop: Header=BB1_3 Depth=1
cmpl $9999, 368(%rsp) # imm = 0x270F
je .LBB1_6
# %bb.5: # in Loop: Header=BB1_3 Depth=1
movl $.L.str, %edi
movq %rbx, %rsi
xorl %eax, %eax
callq printf
movq 296(%rsp), %rsi
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
movl 316(%rsp), %esi
movl $.L.str.2, %edi
xorl %eax, %eax
callq printf
movl 328(%rsp), %esi
movl $.L.str.3, %edi
xorl %eax, %eax
callq printf
movl 356(%rsp), %esi
movl $.L.str.4, %edi
xorl %eax, %eax
callq printf
movl 396(%rsp), %esi
movl $.L.str.5, %edi
xorl %eax, %eax
callq printf
movl 632(%rsp), %esi
movl $.L.str.6, %edi
xorl %eax, %eax
callq printf
.LBB1_6: # in Loop: Header=BB1_3 Depth=1
incl %ebp
cmpl 4(%rsp), %ebp
jl .LBB1_3
.LBB1_7: # %._crit_edge
addq $1480, %rsp # imm = 0x5C8
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z19list_env_propertiesv, .Lfunc_end1-_Z19list_env_propertiesv
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "name:%s\n"
.size .L.str, 9
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "memory:%ld\n"
.size .L.str.1, 12
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "warpsize:%d\n"
.size .L.str.2, 13
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "max threads per block:%d\n"
.size .L.str.3, 26
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "clock rate:%d\n"
.size .L.str.4, 15
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "multiProcessorCount %d\n"
.size .L.str.5, 24
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "maxThreadsPerMultiProcessor %d\n"
.size .L.str.6, 32
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
```
| 2,088 | 1,484 |
136 |
Convert the following CUDA device assembly code to AMD device assembly:
```cudaasm
code for sm_80
```
|
```amdasm
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object ; @__hip_cuid_
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0 ; 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
```
| 24 | 306 |
137 |
Convert the following CUDA host assembly code to AMD host assembly:
```cudaasm
.file "tmpxft_0004906c_00000000-6_mycudamath.cudafe1.cpp"
.text
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2036:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2036:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z7choldcUPfPiS_
.type _Z7choldcUPfPiS_, @function
_Z7choldcUPfPiS_:
.LFB2027:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2027:
.size _Z7choldcUPfPiS_, .-_Z7choldcUPfPiS_
.globl _Z8elsolveUPfPiS_S0_
.type _Z8elsolveUPfPiS_S0_, @function
_Z8elsolveUPfPiS_S0_:
.LFB2028:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2028:
.size _Z8elsolveUPfPiS_S0_, .-_Z8elsolveUPfPiS_S0_
.globl _Z12mdgbacksolvePfPiS_
.type _Z12mdgbacksolvePfPiS_, @function
_Z12mdgbacksolvePfPiS_:
.LFB2029:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2029:
.size _Z12mdgbacksolvePfPiS_, .-_Z12mdgbacksolvePfPiS_
.globl _Z8mtcrosspPfS_S_Pi
.type _Z8mtcrosspPfS_S_Pi, @function
_Z8mtcrosspPfS_S_Pi:
.LFB2030:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2030:
.size _Z8mtcrosspPfS_S_Pi, .-_Z8mtcrosspPfS_S_Pi
.globl _Z6mvprodPfS_S_PiS0_
.type _Z6mvprodPfS_S_PiS0_, @function
_Z6mvprodPfS_S_PiS0_:
.LFB2031:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2031:
.size _Z6mvprodPfS_S_PiS0_, .-_Z6mvprodPfS_S_PiS0_
.globl _Z5vprodPfS_S_Pi
.type _Z5vprodPfS_S_Pi, @function
_Z5vprodPfS_S_Pi:
.LFB2032:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2032:
.size _Z5vprodPfS_S_Pi, .-_Z5vprodPfS_S_Pi
.globl _Z9mvtcrosspPfS_S_PiS0_
.type _Z9mvtcrosspPfS_S_PiS0_, @function
_Z9mvtcrosspPfS_S_PiS0_:
.LFB2033:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2033:
.size _Z9mvtcrosspPfS_S_PiS0_, .-_Z9mvtcrosspPfS_S_PiS0_
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2059:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2059:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
```
|
```amdasm
.text
.file "mycudamath.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
```
| 2,078 | 187 |
140 |
Convert the following CUDA device assembly code to AMD device assembly:
```cudaasm
code for sm_80
Function : _Z6matmulPiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
MOV R1, c[0x0][0x28] ;
S2R R6, SR_CTAID.X ;
ISETP.NE.AND P0, PT, RZ, c[0x0][0xc], PT ;
ULDC.64 UR6, c[0x0][0x118] ;
S2R R7, SR_TID.X ;
S2R R8, SR_CTAID.Y ;
S2R R10, SR_TID.Y ;
@!P0 BRA 0x1d70 ;
ISETP.LT.U32.AND P1, PT, RZ, c[0x0][0xc], PT ;
HFMA2.MMA R9, -RZ, RZ, 0, 2.384185791015625e-07 ;
IMAD R3, R8, 0x1194, R7 ;
HFMA2.MMA R0, -RZ, RZ, 0, 0 ;
IMAD R12, R10.reuse, 0x3c, RZ ;
PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ;
IMAD R2, R10.reuse, 0x12c, R3 ;
MOV R4, RZ ;
IMAD R5, R10, 0x12c, R7 ;
LEA R11, R7, R12, 0x2 ;
IMAD.WIDE R2, R2, R9, c[0x0][0x160] ;
IMAD R14, R6, 0xf, R5 ;
@P1 BRA 0x4e0 ;
IMAD.WIDE R16, R14.reuse, R9, c[0x0][0x168] ;
LDG.E R0, [R2.64] ;
LDG.E R16, [R16.64] ;
PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ;
IADD3 R14, R14, 0x1194, RZ ;
IADD3 R2, P1, R2, 0x3c, RZ ;
IADD3.X R3, RZ, R3, RZ, P1, !PT ;
STS [R11], R0 ;
STS [R11+0x384], R16 ;
BAR.SYNC.DEFER_BLOCKING 0x0 ;
LDS R15, [R7.X4+0x384] ;
LDS R18, [R12] ;
LDS R25, [R7.X4+0x3c0] ;
LDS R26, [R12+0x4] ;
LDS R19, [R7.X4+0x3fc] ;
LDS R20, [R12+0x8] ;
LDS R22, [R7.X4+0x438] ;
LDS R21, [R12+0xc] ;
LDS R23, [R7.X4+0x474] ;
LDS R24, [R12+0x10] ;
LDS R0, [R7.X4+0x4b0] ;
LDS R5, [R12+0x14] ;
IMAD R18, R15, R18, R4 ;
LDS R13, [R7.X4+0x4ec] ;
LDS R16, [R12+0x18] ;
IMAD R25, R25, R26, R18 ;
LDS R4, [R7.X4+0x528] ;
LDS R15, [R12+0x1c] ;
IMAD R25, R19, R20, R25 ;
LDS R17, [R7.X4+0x564] ;
LDS R18, [R12+0x20] ;
IMAD R25, R22, R21, R25 ;
LDS R19, [R7.X4+0x5a0] ;
LDS R20, [R12+0x24] ;
IMAD R25, R23, R24, R25 ;
LDS R21, [R7.X4+0x5dc] ;
LDS R22, [R12+0x28] ;
IMAD R25, R0, R5, R25 ;
LDS R23, [R7.X4+0x618] ;
LDS R24, [R12+0x2c] ;
IMAD R25, R13, R16, R25 ;
LDS R0, [R7.X4+0x654] ;
LDS R5, [R12+0x30] ;
IMAD R25, R4, R15, R25 ;
LDS R13, [R7.X4+0x690] ;
LDS R16, [R12+0x34] ;
IMAD R17, R17, R18, R25 ;
LDS R4, [R7.X4+0x6cc] ;
LDS R15, [R12+0x38] ;
IMAD R17, R19, R20, R17 ;
IMAD R17, R21, R22, R17 ;
IMAD R17, R23, R24, R17 ;
IMAD R0, R0, R5, R17 ;
IMAD R0, R13, R16, R0 ;
IMAD R4, R4, R15, R0 ;
MOV R0, 0x1 ;
BAR.SYNC.DEFER_BLOCKING 0x0 ;
ISETP.GE.U32.AND P1, PT, R0.reuse, c[0x0][0xc], PT ;
IADD3 R5, -R0, c[0x0][0xc], RZ ;
ISETP.LE.U32.OR P1, PT, R5, 0x3, P1 ;
@P1 BRA 0x12e0 ;
PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ;
ULDC UR4, c[0x0][0xc] ;
UIADD3 UR4, UR4, -0x3, URZ ;
IMAD.WIDE R18, R14, R9, c[0x0][0x168] ;
LDG.E R20, [R2.64] ;
LDG.E R22, [R18.64] ;
STS [R11], R20 ;
STS [R11+0x384], R22 ;
BAR.SYNC.DEFER_BLOCKING 0x0 ;
LDS R21, [R7.X4+0x384] ;
LDS R23, [R12] ;
LDS R24, [R7.X4+0x3c0] ;
LDS R25, [R12+0x4] ;
LDS R5, [R7.X4+0x3fc] ;
LDS R16, [R12+0x8] ;
LDS R13, [R7.X4+0x438] ;
LDS R18, [R12+0xc] ;
LDS R15, [R7.X4+0x474] ;
LDS R20, [R12+0x10] ;
LDS R17, [R7.X4+0x4b0] ;
LDS R22, [R12+0x14] ;
IMAD R23, R21, R23, R4 ;
LDS R4, [R7.X4+0x4ec] ;
LDS R21, [R12+0x18] ;
IMAD R25, R24, R25, R23 ;
LDS R26, [R7.X4+0x528] ;
LDS R23, [R12+0x1c] ;
LDS R24, [R7.X4+0x564] ;
LDS R19, [R12+0x20] ;
IMAD R5, R5, R16, R25 ;
IADD3 R16, R14, 0x1194, RZ ;
LDS R25, [R7.X4+0x618] ;
IMAD R5, R13, R18, R5 ;
LDS R28, [R12+0x2c] ;
IMAD R5, R15, R20, R5 ;
LDS R15, [R7.X4+0x690] ;
IMAD R5, R17, R22, R5 ;
LDS R18, [R12+0x34] ;
LDS R17, [R7.X4+0x5a0] ;
IMAD R4, R4, R21, R5 ;
LDS R13, [R7.X4+0x6cc] ;
LDS R21, [R7.X4+0x654] ;
IMAD R23, R26, R23, R4 ;
IMAD.WIDE R4, R16, R9, c[0x0][0x168] ;
LDS R26, [R12+0x28] ;
LDS R16, [R12+0x38] ;
IMAD R20, R24, R19, R23 ;
LDS R19, [R12+0x24] ;
LDS R23, [R7.X4+0x5dc] ;
LDS R24, [R12+0x30] ;
BAR.SYNC.DEFER_BLOCKING 0x0 ;
LDG.E R5, [R4.64] ;
LDG.E R29, [R2.64+0x3c] ;
IMAD R27, R17, R19, R20 ;
IMAD R23, R23, R26, R27 ;
IMAD R23, R25, R28, R23 ;
IMAD R23, R21, R24, R23 ;
IMAD R23, R15, R18, R23 ;
IMAD R23, R13, R16, R23 ;
STS [R11+0x384], R5 ;
STS [R11], R29 ;
BAR.SYNC.DEFER_BLOCKING 0x0 ;
LDS R17, [R7.X4+0x384] ;
LDS R20, [R12] ;
LDS R19, [R7.X4+0x3c0] ;
LDS R22, [R12+0x4] ;
LDS R4, [R7.X4+0x3fc] ;
LDS R5, [R12+0x8] ;
LDS R21, [R7.X4+0x438] ;
LDS R24, [R12+0xc] ;
LDS R15, [R7.X4+0x474] ;
LDS R18, [R12+0x10] ;
LDS R13, [R7.X4+0x4b0] ;
LDS R16, [R12+0x14] ;
IMAD R17, R17, R20, R23 ;
LDS R23, [R7.X4+0x4ec] ;
LDS R26, [R12+0x18] ;
IMAD R25, R19, R22, R17 ;
LDS R22, [R7.X4+0x528] ;
LDS R19, [R12+0x1c] ;
LDS R20, [R7.X4+0x564] ;
LDS R17, [R12+0x20] ;
IMAD R4, R4, R5, R25 ;
LDS R25, [R7.X4+0x618] ;
IMAD R4, R21, R24, R4 ;
LDS R28, [R12+0x2c] ;
IMAD R4, R15, R18, R4 ;
LDS R21, [R7.X4+0x654] ;
IMAD R4, R13, R16, R4 ;
IADD3 R16, R14, 0x2328, RZ ;
LDS R24, [R12+0x30] ;
LDS R15, [R7.X4+0x690] ;
IMAD R4, R23, R26, R4 ;
LDS R23, [R7.X4+0x5dc] ;
LDS R26, [R12+0x28] ;
IMAD R22, R22, R19, R4 ;
IMAD.WIDE R4, R16, R9, c[0x0][0x168] ;
LDS R19, [R7.X4+0x5a0] ;
LDS R18, [R12+0x34] ;
IMAD R20, R20, R17, R22 ;
LDS R17, [R12+0x24] ;
LDS R13, [R7.X4+0x6cc] ;
LDS R16, [R12+0x38] ;
BAR.SYNC.DEFER_BLOCKING 0x0 ;
LDG.E R5, [R4.64] ;
LDG.E R29, [R2.64+0x78] ;
IMAD R27, R19, R17, R20 ;
IMAD R23, R23, R26, R27 ;
IMAD R23, R25, R28, R23 ;
IMAD R23, R21, R24, R23 ;
IMAD R23, R15, R18, R23 ;
IMAD R23, R13, R16, R23 ;
STS [R11+0x384], R5 ;
STS [R11], R29 ;
BAR.SYNC.DEFER_BLOCKING 0x0 ;
LDS R17, [R7.X4+0x384] ;
LDS R20, [R12] ;
LDS R19, [R7.X4+0x3c0] ;
LDS R22, [R12+0x4] ;
LDS R4, [R7.X4+0x3fc] ;
LDS R5, [R12+0x8] ;
LDS R21, [R7.X4+0x438] ;
LDS R24, [R12+0xc] ;
LDS R15, [R7.X4+0x474] ;
LDS R18, [R12+0x10] ;
LDS R13, [R7.X4+0x4b0] ;
LDS R16, [R12+0x14] ;
IMAD R17, R17, R20, R23 ;
LDS R23, [R7.X4+0x4ec] ;
LDS R26, [R12+0x18] ;
IMAD R25, R19, R22, R17 ;
LDS R22, [R7.X4+0x528] ;
LDS R19, [R12+0x1c] ;
LDS R20, [R7.X4+0x564] ;
LDS R17, [R12+0x20] ;
IMAD R4, R4, R5, R25 ;
LDS R28, [R12+0x24] ;
IMAD R4, R21, R24, R4 ;
LDS R25, [R12+0x28] ;
IMAD R4, R15, R18, R4 ;
LDS R18, [R7.X4+0x5dc] ;
IMAD R4, R13, R16, R4 ;
IADD3 R16, R14, 0x34bc, RZ ;
LDS R13, [R7.X4+0x5a0] ;
LDS R15, [R7.X4+0x618] ;
IMAD R4, R23, R26, R4 ;
LDS R23, [R7.X4+0x654] ;
LDS R26, [R12+0x30] ;
IMAD R19, R22, R19, R4 ;
IMAD.WIDE R4, R16, R9, c[0x0][0x168] ;
LDS R21, [R7.X4+0x690] ;
LDS R16, [R12+0x2c] ;
IMAD R27, R20, R17, R19 ;
LDS R24, [R12+0x34] ;
LDS R17, [R7.X4+0x6cc] ;
LDS R20, [R12+0x38] ;
BAR.SYNC.DEFER_BLOCKING 0x0 ;
LDG.E R4, [R4.64] ;
LDG.E R29, [R2.64+0xb4] ;
IMAD R13, R13, R28, R27 ;
IMAD R25, R18, R25, R13 ;
IMAD R25, R15, R16, R25 ;
IMAD R23, R23, R26, R25 ;
IMAD R23, R21, R24, R23 ;
IMAD R23, R17, R20, R23 ;
IADD3 R0, R0, 0x4, RZ ;
ISETP.GE.U32.AND P1, PT, R0, UR4, PT ;
IADD3 R2, P2, R2, 0xf0, RZ ;
IADD3 R14, R14, 0x4650, RZ ;
IADD3.X R3, RZ, R3, RZ, P2, !PT ;
STS [R11+0x384], R4 ;
STS [R11], R29 ;
BAR.SYNC.DEFER_BLOCKING 0x0 ;
LDS R19, [R7.X4+0x384] ;
LDS R22, [R12] ;
LDS R18, [R7.X4+0x3c0] ;
LDS R13, [R12+0x4] ;
LDS R15, [R7.X4+0x3fc] ;
LDS R16, [R12+0x8] ;
LDS R5, [R7.X4+0x438] ;
LDS R4, [R12+0xc] ;
LDS R24, [R7.X4+0x474] ;
LDS R21, [R12+0x10] ;
LDS R20, [R7.X4+0x4b0] ;
LDS R17, [R12+0x14] ;
IMAD R25, R19, R22, R23 ;
LDS R26, [R7.X4+0x4ec] ;
LDS R23, [R12+0x18] ;
LDS R22, [R7.X4+0x528] ;
LDS R19, [R12+0x1c] ;
IMAD R13, R18, R13, R25 ;
LDS R18, [R12+0x28] ;
IMAD R15, R15, R16, R13 ;
LDS R13, [R7.X4+0x564] ;
IMAD R15, R5, R4, R15 ;
LDS R16, [R12+0x20] ;
LDS R4, [R7.X4+0x5a0] ;
IMAD R21, R24, R21, R15 ;
LDS R5, [R12+0x24] ;
LDS R15, [R7.X4+0x5dc] ;
IMAD R21, R20, R17, R21 ;
LDS R17, [R7.X4+0x618] ;
LDS R20, [R12+0x2c] ;
IMAD R23, R26, R23, R21 ;
LDS R21, [R7.X4+0x654] ;
LDS R24, [R12+0x30] ;
IMAD R25, R22, R19, R23 ;
LDS R26, [R7.X4+0x690] ;
LDS R23, [R12+0x34] ;
LDS R19, [R7.X4+0x6cc] ;
LDS R22, [R12+0x38] ;
IMAD R13, R13, R16, R25 ;
IMAD R4, R4, R5, R13 ;
IMAD R4, R15, R18, R4 ;
IMAD R4, R17, R20, R4 ;
IMAD R4, R21, R24, R4 ;
IMAD R4, R26, R23, R4 ;
IMAD R4, R19, R22, R4 ;
BAR.SYNC.DEFER_BLOCKING 0x0 ;
@!P1 BRA 0x550 ;
ISETP.GE.U32.AND P1, PT, R0.reuse, c[0x0][0xc], PT ;
IADD3 R5, -R0, c[0x0][0xc], RZ ;
ISETP.LE.U32.OR P1, PT, R5, 0x1, P1 ;
@P1 BRA 0x1a00 ;
IMAD.WIDE R18, R14, R9, c[0x0][0x168] ;
LDG.E R22, [R2.64] ;
LDG.E R18, [R18.64] ;
STS [R11], R22 ;
STS [R11+0x384], R18 ;
BAR.SYNC.DEFER_BLOCKING 0x0 ;
LDS R15, [R7.X4+0x384] ;
LDS R21, [R12] ;
LDS R24, [R7.X4+0x3c0] ;
LDS R23, [R12+0x4] ;
LDS R20, [R7.X4+0x3fc] ;
LDS R17, [R12+0x8] ;
LDS R5, [R7.X4+0x438] ;
LDS R16, [R12+0xc] ;
LDS R13, [R7.X4+0x474] ;
LDS R18, [R12+0x10] ;
LDS R19, [R7.X4+0x4ec] ;
IMAD R21, R15, R21, R4 ;
LDS R22, [R12+0x18] ;
LDS R4, [R7.X4+0x4b0] ;
LDS R15, [R12+0x14] ;
IMAD R21, R24, R23, R21 ;
LDS R24, [R12+0x1c] ;
IMAD R21, R20, R17, R21 ;
LDS R25, [R7.X4+0x564] ;
LDS R17, [R7.X4+0x528] ;
LDS R20, [R12+0x20] ;
IMAD R5, R5, R16, R21 ;
LDS R23, [R7.X4+0x5a0] ;
IMAD R5, R13, R18, R5 ;
LDS R26, [R12+0x24] ;
LDS R21, [R7.X4+0x5dc] ;
LDS R18, [R7.X4+0x690] ;
LDS R13, [R12+0x34] ;
IMAD R4, R4, R15, R5 ;
LDS R16, [R12+0x38] ;
IMAD R4, R19, R22, R4 ;
LDS R15, [R7.X4+0x6cc] ;
LDS R19, [R7.X4+0x618] ;
IMAD R4, R17, R24, R4 ;
LDS R22, [R7.X4+0x654] ;
IMAD R25, R25, R20, R4 ;
LDS R24, [R12+0x28] ;
LDS R20, [R12+0x2c] ;
LDS R17, [R12+0x30] ;
BAR.SYNC.DEFER_BLOCKING 0x0 ;
IADD3 R4, R14, 0x1194, RZ ;
IMAD.WIDE R4, R4, R9, c[0x0][0x168] ;
LDG.E R29, [R2.64+0x3c] ;
LDG.E R5, [R4.64] ;
IMAD R23, R23, R26, R25 ;
IMAD R23, R21, R24, R23 ;
IMAD R20, R19, R20, R23 ;
IMAD R17, R22, R17, R20 ;
IMAD R17, R18, R13, R17 ;
IMAD R17, R15, R16, R17 ;
IADD3 R2, P1, R2, 0x78, RZ ;
PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ;
IADD3 R0, R0, 0x2, RZ ;
IADD3 R14, R14, 0x2328, RZ ;
IADD3.X R3, RZ, R3, RZ, P1, !PT ;
STS [R11], R29 ;
STS [R11+0x384], R5 ;
BAR.SYNC.DEFER_BLOCKING 0x0 ;
LDS R27, [R7.X4+0x384] ;
LDS R28, [R12] ;
LDS R24, [R7.X4+0x3c0] ;
LDS R21, [R12+0x4] ;
LDS R19, [R7.X4+0x3fc] ;
LDS R4, [R12+0x8] ;
LDS R5, [R7.X4+0x438] ;
LDS R20, [R12+0xc] ;
LDS R18, [R7.X4+0x474] ;
LDS R13, [R12+0x10] ;
LDS R16, [R7.X4+0x4b0] ;
LDS R15, [R12+0x14] ;
LDS R26, [R7.X4+0x4ec] ;
LDS R23, [R12+0x18] ;
IMAD R27, R27, R28, R17 ;
LDS R22, [R7.X4+0x528] ;
LDS R17, [R12+0x1c] ;
IMAD R21, R24, R21, R27 ;
LDS R24, [R12+0x30] ;
IMAD R21, R19, R4, R21 ;
LDS R19, [R7.X4+0x564] ;
IMAD R21, R5, R20, R21 ;
LDS R4, [R12+0x20] ;
LDS R5, [R7.X4+0x5a0] ;
IMAD R21, R18, R13, R21 ;
LDS R20, [R12+0x24] ;
LDS R13, [R7.X4+0x5dc] ;
IMAD R21, R16, R15, R21 ;
LDS R18, [R12+0x28] ;
LDS R15, [R7.X4+0x618] ;
IMAD R23, R26, R23, R21 ;
LDS R16, [R12+0x2c] ;
LDS R21, [R7.X4+0x654] ;
IMAD R25, R22, R17, R23 ;
LDS R23, [R7.X4+0x690] ;
LDS R26, [R12+0x34] ;
LDS R17, [R7.X4+0x6cc] ;
LDS R22, [R12+0x38] ;
IMAD R4, R19, R4, R25 ;
IMAD R4, R5, R20, R4 ;
IMAD R4, R13, R18, R4 ;
IMAD R4, R15, R16, R4 ;
IMAD R4, R21, R24, R4 ;
IMAD R4, R23, R26, R4 ;
IMAD R4, R17, R22, R4 ;
BAR.SYNC.DEFER_BLOCKING 0x0 ;
ISETP.LT.U32.OR P0, PT, R0, c[0x0][0xc], P0 ;
@!P0 BRA 0x1d80 ;
IMAD.WIDE R14, R14, R9, c[0x0][0x168] ;
LDG.E R2, [R2.64] ;
LDG.E R14, [R14.64] ;
STS [R11], R2 ;
STS [R11+0x384], R14 ;
BAR.SYNC.DEFER_BLOCKING 0x0 ;
LDS R13, [R7.X4+0x384] ;
LDS R18, [R12] ;
LDS R26, [R7.X4+0x3c0] ;
LDS R23, [R12+0x4] ;
LDS R24, [R7.X4+0x3fc] ;
LDS R21, [R12+0x8] ;
LDS R19, [R7.X4+0x438] ;
LDS R22, [R12+0xc] ;
LDS R17, [R7.X4+0x474] ;
LDS R20, [R12+0x10] ;
LDS R11, [R7.X4+0x4b0] ;
LDS R0, [R12+0x14] ;
IMAD R13, R13, R18, R4 ;
LDS R9, [R7.X4+0x4ec] ;
LDS R16, [R12+0x18] ;
IMAD R23, R26, R23, R13 ;
LDS R5, [R7.X4+0x528] ;
LDS R14, [R12+0x1c] ;
IMAD R23, R24, R21, R23 ;
LDS R2, [R7.X4+0x564] ;
LDS R3, [R12+0x20] ;
IMAD R23, R19, R22, R23 ;
LDS R15, [R7.X4+0x5a0] ;
LDS R18, [R12+0x24] ;
IMAD R25, R17, R20, R23 ;
LDS R4, [R7.X4+0x5dc] ;
LDS R13, [R12+0x28] ;
IMAD R0, R11, R0, R25 ;
LDS R21, [R7.X4+0x618] ;
LDS R24, [R12+0x2c] ;
IMAD R0, R9, R16, R0 ;
LDS R19, [R7.X4+0x654] ;
LDS R22, [R12+0x30] ;
IMAD R0, R5, R14, R0 ;
LDS R17, [R7.X4+0x690] ;
LDS R20, [R12+0x34] ;
IMAD R0, R2, R3, R0 ;
LDS R26, [R12+0x38] ;
LDS R23, [R7.X4+0x6cc] ;
IMAD R0, R15, R18, R0 ;
IMAD R0, R4, R13, R0 ;
IMAD R0, R21, R24, R0 ;
IMAD R0, R19, R22, R0 ;
IMAD R0, R17, R20, R0 ;
IMAD R4, R23, R26, R0 ;
BAR.SYNC.DEFER_BLOCKING 0x0 ;
BRA 0x1d80 ;
HFMA2.MMA R4, -RZ, RZ, 0, 0 ;
IMAD R3, R8, 0x1194, R7 ;
MOV R2, 0x4 ;
IMAD R3, R6, 0xf, R3 ;
IMAD R3, R10, 0x12c, R3 ;
IMAD.WIDE R2, R3, R2, c[0x0][0x170] ;
STG.E [R2.64], R4 ;
EXIT ;
BRA 0x1df0;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
```
|
```amdasm
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6matmulPiS_S_ ; -- Begin function _Z6matmulPiS_S_
.globl _Z6matmulPiS_S_
.p2align 8
.type _Z6matmulPiS_S_,@function
_Z6matmulPiS_S_: ; @_Z6matmulPiS_S_
; %bb.0:
s_clause 0x2
s_load_b32 s3, s[0:1], 0x18
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
v_bfe_u32 v8, v0, 10, 10
v_and_b32_e32 v3, 0x3ff, v0
s_mov_b32 s8, 0
s_mulk_i32 s15, 0x1194
s_mul_i32 s2, s14, 15
v_mul_u32_u24_e32 v4, 0x12c, v8
s_waitcnt lgkmcnt(0)
s_cmp_lg_u32 s3, 0
s_cbranch_scc0 .LBB0_6
; %bb.1: ; %.lr.ph
v_lshlrev_b32_e32 v0, 2, v3
v_add_nc_u32_e32 v2, v4, v3
s_mul_i32 s9, s14, 15
v_mul_u32_u24_e32 v5, 60, v8
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_nc_u32_e32 v6, 0x390, v0
v_add_nc_u32_e32 v1, s15, v2
v_mad_u32_u24 v7, v8, 60, v0
v_mov_b32_e32 v0, 0
v_add_nc_u32_e32 v2, s9, v2
v_mad_u32_u24 v8, v8, 60, v6
.LBB0_2: ; =>This Loop Header: Depth=1
; Child Loop BB0_3 Depth 2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[9:10], null, s8, 15, v[1:2]
v_mad_u64_u32 v[11:12], null, 0x1194, s8, v[2:3]
s_mov_b32 s10, 0
v_ashrrev_i32_e32 v10, 31, v9
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v12, 31, v11
v_lshlrev_b64 v[9:10], 2, v[9:10]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[11:12], 2, v[11:12]
v_add_co_u32 v9, vcc_lo, s4, v9
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e32 v10, vcc_lo, s5, v10, vcc_lo
v_add_co_u32 v11, vcc_lo, s6, v11
s_delay_alu instid0(VALU_DEP_4)
v_add_co_ci_u32_e32 v12, vcc_lo, s7, v12, vcc_lo
global_load_b32 v10, v[9:10], off
global_load_b32 v11, v[11:12], off
v_mov_b32_e32 v9, v6
s_waitcnt vmcnt(1)
ds_store_b32 v7, v10
s_waitcnt vmcnt(0)
ds_store_b32 v8, v11
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
.LBB0_3: ; Parent Loop BB0_2 Depth=1
; => This Inner Loop Header: Depth=2
v_add_nc_u32_e32 v10, s10, v5
s_add_i32 s10, s10, 4
ds_load_b32 v12, v9
ds_load_b32 v13, v10
s_cmp_eq_u32 s10, 60
s_waitcnt lgkmcnt(0)
v_mad_u64_u32 v[10:11], null, v12, v13, v[0:1]
s_delay_alu instid0(VALU_DEP_1)
v_dual_mov_b32 v0, v10 :: v_dual_add_nc_u32 v9, 60, v9
s_cbranch_scc0 .LBB0_3
; %bb.4: ; in Loop: Header=BB0_2 Depth=1
s_add_i32 s8, s8, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s8, s3
s_barrier
buffer_gl0_inv
s_cbranch_scc0 .LBB0_2
; %bb.5: ; %Flow
s_mov_b32 s3, 0
s_branch .LBB0_7
.LBB0_6:
s_mov_b32 s3, -1
; implicit-def: $vgpr0
; implicit-def: $sgpr9
.LBB0_7: ; %Flow54
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 vcc_lo, exec_lo, s3
s_cbranch_vccz .LBB0_9
; %bb.8: ; %.._crit_edge_crit_edge
v_mov_b32_e32 v0, 0
s_mov_b32 s9, s2
.LBB0_9: ; %._crit_edge
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s2, s9, s15
v_add3_u32 v1, s2, v3, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v1, vcc_lo, s0, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
global_store_b32 v[1:2], v0, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6matmulPiS_S_
.amdhsa_group_segment_fixed_size 1812
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 14
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6matmulPiS_S_, .Lfunc_end0-_Z6matmulPiS_S_
; -- End function
.section .AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 468
; NumSgprs: 18
; NumVgprs: 14
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 1812 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 14
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object ; @__hip_cuid_
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0 ; 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 1812
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6matmulPiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z6matmulPiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 14
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
```
| 8,411 | 3,719 |
141 |
Convert the following CUDA host assembly code to AMD host assembly:
```cudaasm
.file "tmpxft_00118bac_00000000-6_cuda_matmul_fast.cudafe1.cpp"
.text
.globl _ZSt21ios_base_library_initv
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3673:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3673:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z13global_offsetiiii
.type _Z13global_offsetiiii, @function
_Z13global_offsetiiii:
.LFB3669:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE3669:
.size _Z13global_offsetiiii, .-_Z13global_offsetiiii
.globl _Z29__device_stub__Z6matmulPiS_S_PiS_S_
.type _Z29__device_stub__Z6matmulPiS_S_PiS_S_, @function
_Z29__device_stub__Z6matmulPiS_S_PiS_S_:
.LFB3695:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L9
.L5:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L10
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L9:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z6matmulPiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L5
.L10:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3695:
.size _Z29__device_stub__Z6matmulPiS_S_PiS_S_, .-_Z29__device_stub__Z6matmulPiS_S_PiS_S_
.globl _Z6matmulPiS_S_
.type _Z6matmulPiS_S_, @function
_Z6matmulPiS_S_:
.LFB3696:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z6matmulPiS_S_PiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3696:
.size _Z6matmulPiS_S_, .-_Z6matmulPiS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "sum is "
.LC2:
.string "Seconds elapsed: %f\n"
.text
.globl main
.type main, @function
main:
.LFB3670:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
leaq -1077248(%rsp), %r11
.cfi_def_cfa 11, 1077272
.LPSRL0:
subq $4096, %rsp
orq $0, (%rsp)
cmpq %r11, %rsp
jne .LPSRL0
.cfi_def_cfa_register 7
subq $2824, %rsp
.cfi_def_cfa_offset 1080096
movq %fs:40, %rax
movq %rax, 1080056(%rsp)
xorl %eax, %eax
movq %rsp, %rdi
movl $360000, %esi
call cudaMalloc@PLT
leaq 8(%rsp), %rdi
movl $360000, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $360000, %esi
call cudaMalloc@PLT
movl $5, %edi
call srand@PLT
movl $1200, %ebp
.L14:
leaq -1200(%rbp), %rbx
.L15:
call rand@PLT
movl %eax, 48(%rsp,%rbx)
call rand@PLT
movl %eax, 360048(%rsp,%rbx)
movl $0, 720048(%rsp,%rbx)
addq $4, %rbx
cmpq %rbp, %rbx
jne .L15
addq $1200, %rbp
cmpq $361200, %rbp
jne .L14
leaq 48(%rsp), %rsi
movl $1, %ecx
movl $360000, %edx
movq (%rsp), %rdi
call cudaMemcpy@PLT
leaq 360048(%rsp), %rsi
movl $1, %ecx
movl $360000, %edx
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $15, 24(%rsp)
movl $15, 28(%rsp)
movl $1, 32(%rsp)
movl $20, 36(%rsp)
movl $20, 40(%rsp)
movl $1, 44(%rsp)
movl $0, %esi
leaq start(%rip), %rdi
call gettimeofday@PLT
movl 32(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 24(%rsp), %rdx
movq 36(%rsp), %rdi
movl 44(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L25
.L17:
call cudaThreadSynchronize@PLT
movl $0, %esi
leaq end(%rip), %rdi
call gettimeofday@PLT
leaq 720048(%rsp), %rdi
movl $2, %ecx
movl $360000, %edx
movq 16(%rsp), %rsi
call cudaMemcpy@PLT
leaq 721248(%rsp), %rcx
leaq 1081248(%rsp), %rsi
movl $0, %edx
.L18:
leaq -1200(%rcx), %rax
.L19:
addl (%rax), %edx
movl %edx, %ebx
addq $4, %rax
cmpq %rcx, %rax
jne .L19
addq $1200, %rcx
cmpq %rsi, %rcx
jne .L18
leaq .LC0(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl %ebx, %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
pxor %xmm0, %xmm0
cvtsi2sdq end(%rip), %xmm0
movsd .LC1(%rip), %xmm1
mulsd %xmm1, %xmm0
pxor %xmm2, %xmm2
cvtsi2sdq 8+end(%rip), %xmm2
addsd %xmm2, %xmm0
pxor %xmm2, %xmm2
cvtsi2sdq start(%rip), %xmm2
mulsd %xmm1, %xmm2
subsd %xmm2, %xmm0
pxor %xmm2, %xmm2
cvtsi2sdq 8+start(%rip), %xmm2
subsd %xmm2, %xmm0
divsd %xmm1, %xmm0
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq (%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 1080056(%rsp), %rax
subq %fs:40, %rax
jne .L26
movl $0, %eax
addq $1080072, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L25:
.cfi_restore_state
movq 16(%rsp), %rdx
movq 8(%rsp), %rsi
movq (%rsp), %rdi
call _Z29__device_stub__Z6matmulPiS_S_PiS_S_
jmp .L17
.L26:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3670:
.size main, .-main
.section .rodata.str1.1
.LC3:
.string "_Z6matmulPiS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3698:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z6matmulPiS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3698:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl end
.bss
.align 16
.type end, @object
.size end, 16
end:
.zero 16
.globl start
.align 16
.type start, @object
.size start, 16
start:
.zero 16
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC1:
.long 0
.long 1093567616
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
```
|
```amdasm
.text
.file "cuda_matmul_fast.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z21__device_stub__matmulPiS_S_ # -- Begin function _Z21__device_stub__matmulPiS_S_
.type _Z21__device_stub__matmulPiS_S_,@function
_Z21__device_stub__matmulPiS_S_: # @_Z21__device_stub__matmulPiS_S_
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $112, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 40(%rsp), %rax
movq %rdi, (%rax)
leaq 32(%rsp), %rcx
movq %rsi, (%rcx)
leaq 24(%rsp), %rsi
movq %rdx, (%rsi)
leaq 80(%rsp), %rbx
movq %rax, (%rbx)
movq %rcx, 8(%rbx)
movq %rsi, 16(%rbx)
leaq 64(%rsp), %r14
leaq 48(%rsp), %r15
leaq 16(%rsp), %r12
leaq 8(%rsp), %r13
movq %r14, %rdi
movq %r15, %rsi
movq %r12, %rdx
movq %r13, %rcx
callq __hipPopCallConfiguration
movq (%r14), %rsi
movl 8(%r14), %edx
movq (%r15), %rcx
movl 8(%r15), %r8d
movl $_Z6matmulPiS_S_, %edi
movq %rbx, %r9
pushq (%r13)
.cfi_adjust_cfa_offset 8
pushq (%r12)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $128, %rsp
.cfi_adjust_cfa_offset -128
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z21__device_stub__matmulPiS_S_, .Lfunc_end0-_Z21__device_stub__matmulPiS_S_
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI1_0:
.quad 0x412e848000000000 # double 1.0E+6
.text
.globl main
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $1080040, %rsp # imm = 0x107AE8
.cfi_def_cfa_offset 1080096
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
leaq 24(%rsp), %rdi
movl $360000, %esi # imm = 0x57E40
callq hipMalloc
leaq 16(%rsp), %rdi
movl $360000, %esi # imm = 0x57E40
callq hipMalloc
leaq 8(%rsp), %rdi
movl $360000, %esi # imm = 0x57E40
callq hipMalloc
movl $5, %edi
callq srand
leaq 32(%rsp), %rbx
leaq 360032(%rsp), %r14
leaq 720032(%rsp), %r15
xorl %r12d, %r12d
movl $1200, %r13d # imm = 0x4B0
.LBB1_1: # %.preheader31
# =>This Loop Header: Depth=1
# Child Loop BB1_2 Depth 2
xorl %ebp, %ebp
.LBB1_2: # Parent Loop BB1_1 Depth=1
# => This Inner Loop Header: Depth=2
callq rand
movl %eax, (%r15,%rbp,4)
callq rand
movl %eax, (%r14,%rbp,4)
movl $0, (%rbx,%rbp,4)
incq %rbp
cmpq $300, %rbp # imm = 0x12C
jne .LBB1_2
# %bb.3: # in Loop: Header=BB1_1 Depth=1
incq %r12
addq %r13, %rbx
addq %r13, %r14
addq %r13, %r15
cmpq $300, %r12 # imm = 0x12C
jne .LBB1_1
# %bb.4:
movq 24(%rsp), %rdi
leaq 720032(%rsp), %rsi
movl $360000, %edx # imm = 0x57E40
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
leaq 360032(%rsp), %rsi
movl $360000, %edx # imm = 0x57E40
movl $1, %ecx
callq hipMemcpy
xorl %ebx, %ebx
movl $start, %edi
xorl %esi, %esi
callq gettimeofday
movabsq $85899345940, %rdi # imm = 0x1400000014
movabsq $64424509455, %rdx # imm = 0xF0000000F
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_6
# %bb.5:
movq 24(%rsp), %rdi
movq 16(%rsp), %rsi
movq 8(%rsp), %rdx
callq _Z21__device_stub__matmulPiS_S_
.LBB1_6:
callq hipDeviceSynchronize
movl $end, %edi
xorl %esi, %esi
callq gettimeofday
movq 8(%rsp), %rsi
leaq 32(%rsp), %r14
movl $360000, %edx # imm = 0x57E40
movq %r14, %rdi
movl $2, %ecx
callq hipMemcpy
xorl %eax, %eax
.LBB1_7: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB1_8 Depth 2
xorl %ecx, %ecx
.LBB1_8: # Parent Loop BB1_7 Depth=1
# => This Inner Loop Header: Depth=2
addl (%r14,%rcx,4), %ebx
incq %rcx
cmpq $300, %rcx # imm = 0x12C
jne .LBB1_8
# %bb.9: # in Loop: Header=BB1_7 Depth=1
incq %rax
addq $1200, %r14 # imm = 0x4B0
cmpq $300, %rax # imm = 0x12C
jne .LBB1_7
# %bb.10:
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $7, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl %ebx, %esi
callq _ZNSolsEi
movq %rax, %rbx
movq (%rax), %rax
movq -24(%rax), %rdi
addq %rbx, %rdi
movl $10, %esi
callq _ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
movsbl %al, %esi
movq %rbx, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
cvtsi2sdq end(%rip), %xmm1
movsd .LCPI1_0(%rip), %xmm2 # xmm2 = mem[0],zero
mulsd %xmm2, %xmm1
cvtsi2sdq end+8(%rip), %xmm0
addsd %xmm1, %xmm0
xorps %xmm1, %xmm1
cvtsi2sdq start(%rip), %xmm1
mulsd %xmm2, %xmm1
subsd %xmm1, %xmm0
xorps %xmm1, %xmm1
cvtsi2sdq start+8(%rip), %xmm1
subsd %xmm1, %xmm0
divsd %xmm2, %xmm0
movl $.L.str.1, %edi
movb $1, %al
callq printf
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $1080040, %rsp # imm = 0x107AE8
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, %rdi
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6matmulPiS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type start,@object # @start
.bss
.globl start
.p2align 3, 0x0
start:
.zero 16
.size start, 16
.type end,@object # @end
.globl end
.p2align 3, 0x0
end:
.zero 16
.size end, 16
.type _Z6matmulPiS_S_,@object # @_Z6matmulPiS_S_
.section .rodata,"a",@progbits
.globl _Z6matmulPiS_S_
.p2align 3, 0x0
_Z6matmulPiS_S_:
.quad _Z21__device_stub__matmulPiS_S_
.size _Z6matmulPiS_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "sum is "
.size .L.str, 8
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Seconds elapsed: %f\n"
.size .L.str.1, 21
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z6matmulPiS_S_"
.size .L__unnamed_1, 16
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__matmulPiS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym start
.addrsig_sym end
.addrsig_sym _Z6matmulPiS_S_
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
```
| 3,897 | 4,499 |
142 |
Convert the following CUDA device assembly code to AMD device assembly:
```cudaasm
code for sm_80
Function : _Z3addPiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
MOV R1, c[0x0][0x28] ;
EXIT ;
BRA 0x20;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
```
|
```amdasm
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3addPiS_S_ ; -- Begin function _Z3addPiS_S_
.globl _Z3addPiS_S_
.p2align 8
.type _Z3addPiS_S_,@function
_Z3addPiS_S_: ; @_Z3addPiS_S_
; %bb.0:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3addPiS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 1
.amdhsa_next_free_sgpr 1
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3addPiS_S_, .Lfunc_end0-_Z3addPiS_S_
; -- End function
.section .AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 4
; NumSgprs: 0
; NumVgprs: 0
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 0
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 1
; NumVGPRsForWavesPerEU: 1
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object ; @__hip_cuid_
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0 ; 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3addPiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 0
.sgpr_spill_count: 0
.symbol: _Z3addPiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 0
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
```
| 120 | 1,584 |
143 |
Convert the following CUDA host assembly code to AMD host assembly:
```cudaasm
.file "tmpxft_0002a485_00000000-6_vectoradd.cudafe1.cpp"
.text
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2063:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2063:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z8get_timev
.type _Z8get_timev, @function
_Z8get_timev:
.LFB2058:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
movq %fs:40, %rax
movq %rax, 24(%rsp)
xorl %eax, %eax
movq %rsp, %rdi
movl $0, %esi
call gettimeofday@PLT
pxor %xmm0, %xmm0
cvtsi2sdq 8(%rsp), %xmm0
mulsd .LC0(%rip), %xmm0
pxor %xmm1, %xmm1
cvtsi2sdq (%rsp), %xmm1
addsd %xmm1, %xmm0
movq 24(%rsp), %rax
subq %fs:40, %rax
jne .L6
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L6:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size _Z8get_timev, .-_Z8get_timev
.globl _Z7add_cpuPiS_S_
.type _Z7add_cpuPiS_S_, @function
_Z7add_cpuPiS_S_:
.LFB2059:
.cfi_startproc
endbr64
ret
.cfi_endproc
.LFE2059:
.size _Z7add_cpuPiS_S_, .-_Z7add_cpuPiS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "[GPU]: %f sec Elpased\n"
.LC2:
.string "%d + %d != %d\n"
.LC3:
.string "GPU TEST SUCCESSFUL!\n"
.LC4:
.string "[CPU]: %f sec Elpased\n"
.LC5:
.string "CPU TEST SUCCESSFUL!\n"
.text
.globl main
.type main, @function
main:
.LFB2060:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
leaq -786432(%rsp), %r11
.cfi_def_cfa 11, 786464
.LPSRL0:
subq $4096, %rsp
orq $0, (%rsp)
cmpq %r11, %rsp
jne .LPSRL0
.cfi_def_cfa_register 7
subq $32, %rsp
.cfi_def_cfa_offset 786496
movq %fs:40, %rax
movq %rax, 786456(%rsp)
xorl %eax, %eax
.L9:
movl %eax, 16(%rsp,%rax,4)
movl %eax, %edx
imull %eax, %edx
movl %edx, 262160(%rsp,%rax,4)
addq $1, %rax
cmpq $65535, %rax
jne .L9
call _Z8get_timev
movsd %xmm0, 8(%rsp)
call _Z8get_timev
subsd 8(%rsp), %xmm0
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl $0, %ebx
movl $1, %ebp
leaq .LC2(%rip), %r12
jmp .L11
.L10:
addq $4, %rbx
cmpq $262140, %rbx
je .L21
.L11:
movl 16(%rsp,%rbx), %edx
movl 262160(%rsp,%rbx), %ecx
movl 524304(%rsp,%rbx), %r8d
leal (%rdx,%rcx), %eax
cmpl %r8d, %eax
je .L10
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %ebp
jmp .L10
.L21:
testb %bpl, %bpl
jne .L22
.L12:
call _Z8get_timev
movsd %xmm0, 8(%rsp)
call _Z8get_timev
subsd 8(%rsp), %xmm0
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl $0, %ebx
leaq .LC2(%rip), %r12
jmp .L14
.L22:
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L12
.L13:
addq $4, %rbx
cmpq $262140, %rbx
je .L23
.L14:
movl 16(%rsp,%rbx), %edx
movl 262160(%rsp,%rbx), %ecx
movl 524304(%rsp,%rbx), %r8d
leal (%rdx,%rcx), %eax
cmpl %r8d, %eax
je .L13
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %ebp
jmp .L13
.L23:
testb %bpl, %bpl
jne .L24
.L15:
movq 786456(%rsp), %rax
subq %fs:40, %rax
jne .L25
movl $0, %eax
addq $786464, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L24:
.cfi_restore_state
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L15
.L25:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2060:
.size main, .-main
.globl _Z26__device_stub__Z3addPiS_S_PiS_S_
.type _Z26__device_stub__Z3addPiS_S_PiS_S_, @function
_Z26__device_stub__Z3addPiS_S_PiS_S_:
.LFB2085:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L30
.L26:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L31
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L30:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z3addPiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L26
.L31:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2085:
.size _Z26__device_stub__Z3addPiS_S_PiS_S_, .-_Z26__device_stub__Z3addPiS_S_PiS_S_
.globl _Z3addPiS_S_
.type _Z3addPiS_S_, @function
_Z3addPiS_S_:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z3addPiS_S_PiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _Z3addPiS_S_, .-_Z3addPiS_S_
.section .rodata.str1.1
.LC6:
.string "_Z3addPiS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2088:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _Z3addPiS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2088:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC0:
.long -1598689907
.long 1051772663
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
```
|
```amdasm
.text
.file "vectoradd.hip"
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z8get_timev
.LCPI0_0:
.quad 0x3eb0c6f7a0b5ed8d # double 9.9999999999999995E-7
.text
.globl _Z8get_timev
.type _Z8get_timev,@function
_Z8get_timev: # @_Z8get_timev
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $16, %rsp
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -16
movq %rsp, %rbx
movq %rbx, %rdi
xorl %esi, %esi
callq gettimeofday
cvtsi2sdq (%rbx), %xmm1
cvtsi2sdq 8(%rbx), %xmm0
mulsd .LCPI0_0(%rip), %xmm0
addsd %xmm1, %xmm0
addq $16, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z8get_timev, .Lfunc_end0-_Z8get_timev
.cfi_endproc
# -- End function
.globl _Z18__device_stub__addPiS_S_ # -- Begin function _Z18__device_stub__addPiS_S_
.type _Z18__device_stub__addPiS_S_,@function
_Z18__device_stub__addPiS_S_: # @_Z18__device_stub__addPiS_S_
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $112, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 40(%rsp), %rax
movq %rdi, (%rax)
leaq 32(%rsp), %rcx
movq %rsi, (%rcx)
leaq 24(%rsp), %rsi
movq %rdx, (%rsi)
leaq 80(%rsp), %rbx
movq %rax, (%rbx)
movq %rcx, 8(%rbx)
movq %rsi, 16(%rbx)
leaq 64(%rsp), %r14
leaq 48(%rsp), %r15
leaq 16(%rsp), %r12
leaq 8(%rsp), %r13
movq %r14, %rdi
movq %r15, %rsi
movq %r12, %rdx
movq %r13, %rcx
callq __hipPopCallConfiguration
movq (%r14), %rsi
movl 8(%r14), %edx
movq (%r15), %rcx
movl 8(%r15), %r8d
movl $_Z3addPiS_S_, %edi
movq %rbx, %r9
pushq (%r13)
.cfi_adjust_cfa_offset 8
pushq (%r12)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $128, %rsp
.cfi_adjust_cfa_offset -128
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z18__device_stub__addPiS_S_, .Lfunc_end1-_Z18__device_stub__addPiS_S_
.cfi_endproc
# -- End function
.globl _Z7add_cpuPiS_S_ # -- Begin function _Z7add_cpuPiS_S_
.type _Z7add_cpuPiS_S_,@function
_Z7add_cpuPiS_S_: # @_Z7add_cpuPiS_S_
.cfi_startproc
# %bb.0:
retq
.Lfunc_end2:
.size _Z7add_cpuPiS_S_, .Lfunc_end2-_Z7add_cpuPiS_S_
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI3_0:
.quad 0x3eb0c6f7a0b5ed8d # double 9.9999999999999995E-7
.text
.globl main
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $786464, %rsp # imm = 0xC0020
.cfi_def_cfa_offset 786496
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %rbp, -16
xorl %eax, %eax
.LBB3_1: # =>This Inner Loop Header: Depth=1
movl %eax, 524320(%rsp,%rax,4)
movl %eax, %ecx
imull %eax, %ecx
movl %ecx, 262176(%rsp,%rax,4)
incq %rax
cmpq $65535, %rax # imm = 0xFFFF
jne .LBB3_1
# %bb.2:
xorl %r14d, %r14d
leaq 32(%rsp), %rbx
movq %rbx, %rdi
xorl %esi, %esi
callq gettimeofday
cvtsi2sdq (%rbx), %xmm0
cvtsi2sdq 8(%rbx), %xmm1
mulsd .LCPI3_0(%rip), %xmm1
addsd %xmm0, %xmm1
movsd %xmm1, 8(%rsp) # 8-byte Spill
leaq 32(%rsp), %rbx
movq %rbx, %rdi
xorl %esi, %esi
callq gettimeofday
xorps %xmm1, %xmm1
cvtsi2sdq (%rbx), %xmm1
xorps %xmm0, %xmm0
cvtsi2sdq 8(%rbx), %xmm0
mulsd .LCPI3_0(%rip), %xmm0
addsd %xmm1, %xmm0
subsd 8(%rsp), %xmm0 # 8-byte Folded Reload
movb $1, %bpl
movl $.L.str, %edi
movb $1, %al
callq printf
.LBB3_3: # =>This Inner Loop Header: Depth=1
movl 524320(%rsp,%r14,4), %esi
movl 262176(%rsp,%r14,4), %edx
leal (%rdx,%rsi), %eax
movl 32(%rsp,%r14,4), %ecx
cmpl %ecx, %eax
je .LBB3_5
# %bb.4: # in Loop: Header=BB3_3 Depth=1
xorl %ebp, %ebp
movl $.L.str.1, %edi
# kill: def $esi killed $esi killed $rsi
# kill: def $edx killed $edx killed $rdx
xorl %eax, %eax
callq printf
.LBB3_5: # in Loop: Header=BB3_3 Depth=1
incq %r14
cmpq $65535, %r14 # imm = 0xFFFF
jne .LBB3_3
# %bb.6:
testb $1, %bpl
je .LBB3_8
# %bb.7:
movl $.Lstr, %edi
callq puts@PLT
.LBB3_8:
xorl %r14d, %r14d
leaq 16(%rsp), %rbx
movq %rbx, %rdi
xorl %esi, %esi
callq gettimeofday
xorps %xmm0, %xmm0
cvtsi2sdq (%rbx), %xmm0
cvtsi2sdq 8(%rbx), %xmm2
movsd .LCPI3_0(%rip), %xmm1 # xmm1 = mem[0],zero
mulsd %xmm1, %xmm2
addsd %xmm0, %xmm2
movsd %xmm2, 8(%rsp) # 8-byte Spill
leaq 16(%rsp), %rbx
movq %rbx, %rdi
xorl %esi, %esi
callq gettimeofday
xorps %xmm1, %xmm1
cvtsi2sdq (%rbx), %xmm1
xorps %xmm0, %xmm0
cvtsi2sdq 8(%rbx), %xmm0
mulsd .LCPI3_0(%rip), %xmm0
addsd %xmm1, %xmm0
subsd 8(%rsp), %xmm0 # 8-byte Folded Reload
movl $.L.str.3, %edi
movb $1, %al
callq printf
.LBB3_9: # =>This Inner Loop Header: Depth=1
movl 524320(%rsp,%r14,4), %esi
movl 262176(%rsp,%r14,4), %edx
leal (%rdx,%rsi), %eax
movl 32(%rsp,%r14,4), %ecx
cmpl %ecx, %eax
je .LBB3_11
# %bb.10: # in Loop: Header=BB3_9 Depth=1
xorl %ebp, %ebp
movl $.L.str.1, %edi
# kill: def $esi killed $esi killed $rsi
# kill: def $edx killed $edx killed $rdx
xorl %eax, %eax
callq printf
.LBB3_11: # in Loop: Header=BB3_9 Depth=1
incq %r14
cmpq $65535, %r14 # imm = 0xFFFF
jne .LBB3_9
# %bb.12:
testb $1, %bpl
je .LBB3_14
# %bb.13:
movl $.Lstr.1, %edi
callq puts@PLT
.LBB3_14:
xorl %eax, %eax
addq $786464, %rsp # imm = 0xC0020
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, %rdi
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3addPiS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3addPiS_S_,@object # @_Z3addPiS_S_
.section .rodata,"a",@progbits
.globl _Z3addPiS_S_
.p2align 3, 0x0
_Z3addPiS_S_:
.quad _Z18__device_stub__addPiS_S_
.size _Z3addPiS_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "[GPU]: %f sec Elpased\n"
.size .L.str, 23
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "%d + %d != %d\n"
.size .L.str.1, 15
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "[CPU]: %f sec Elpased\n"
.size .L.str.3, 23
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z3addPiS_S_"
.size .L__unnamed_1, 13
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "GPU TEST SUCCESSFUL!"
.size .Lstr, 21
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "CPU TEST SUCCESSFUL!"
.size .Lstr.1, 21
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__addPiS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3addPiS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
```
| 3,654 | 4,506 |
144 |
Convert the following CUDA device assembly code to AMD device assembly:
```cudaasm
code for sm_80
Function : _Z15MatrixMulKernelPfS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
MOV R1, c[0x0][0x28] ;
S2R R4, SR_TID.Y ;
MOV R2, c[0x0][0x178] ;
ULDC.64 UR4, c[0x0][0x118] ;
HFMA2.MMA R28, -RZ, RZ, 0, 0 ;
S2R R0, SR_TID.X ;
ISETP.GE.AND P0, PT, R2, 0x1, PT ;
IMAD R4, R4, c[0x0][0x178], RZ ;
@!P0 BRA 0xbb0 ;
IADD3 R3, R2.reuse, -0x1, RZ ;
LOP3.LUT R5, R2, 0x3, RZ, 0xc0, !PT ;
ISETP.GE.U32.AND P0, PT, R3, 0x3, PT ;
MOV R28, RZ ;
MOV R3, RZ ;
@!P0 BRA 0xa90 ;
IADD3 R6, -R5, c[0x0][0x178], RZ ;
HFMA2.MMA R25, -RZ, RZ, 0, 2.384185791015625e-07 ;
ULDC.64 UR6, c[0x0][0x160] ;
HFMA2.MMA R3, -RZ, RZ, 0, 0 ;
ISETP.GT.AND P0, PT, R6, RZ, PT ;
MOV R28, RZ ;
IMAD.WIDE R24, R0, R25, c[0x0][0x168] ;
@!P0 BRA 0x900 ;
ISETP.GT.AND P1, PT, R6, 0xc, PT ;
PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ;
@!P1 BRA 0x640 ;
PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ;
MOV R12, UR6 ;
LDG.E R29, [R24.64] ;
MOV R13, UR7 ;
IMAD.WIDE R12, R4, 0x4, R12 ;
LDG.E R27, [R12.64] ;
IMAD.WIDE R10, R2, 0x4, R24 ;
LDG.E R17, [R12.64+0x4] ;
IMAD.WIDE R18, R2.reuse, 0x4, R10 ;
LDG.E R16, [R10.64] ;
LDG.E R7, [R12.64+0xc] ;
IMAD.WIDE R14, R2, 0x4, R18 ;
LDG.E R18, [R18.64] ;
IMAD.WIDE R20, R2.reuse, 0x4, R14 ;
LDG.E R26, [R14.64] ;
LDG.E R9, [R12.64+0x10] ;
LDG.E R19, [R12.64+0x8] ;
IMAD.WIDE R14, R2, 0x4, R20 ;
LDG.E R20, [R20.64] ;
IMAD.WIDE R22, R2.reuse, 0x4, R14 ;
LDG.E R8, [R14.64] ;
LDG.E R11, [R12.64+0x14] ;
IMAD.WIDE R24, R2, 0x4, R22 ;
LDG.E R10, [R22.64] ;
LDG.E R21, [R12.64+0x18] ;
FFMA R29, R29, R27, R28 ;
LDG.E R27, [R12.64+0x1c] ;
LDG.E R28, [R24.64] ;
IMAD.WIDE R14, R2, 0x4, R24 ;
FFMA R29, R16, R17, R29 ;
IMAD.WIDE R16, R2, 0x4, R14 ;
LDG.E R14, [R14.64] ;
FFMA R29, R18, R19, R29 ;
IMAD.WIDE R18, R2, 0x4, R16 ;
LDG.E R16, [R16.64] ;
FFMA R26, R26, R7, R29 ;
IMAD.WIDE R22, R2.reuse, 0x4, R18 ;
LDG.E R7, [R12.64+0x20] ;
LDG.E R29, [R12.64+0x24] ;
IMAD.WIDE R24, R2, 0x4, R22 ;
LDG.E R18, [R18.64] ;
FFMA R9, R20, R9, R26 ;
LDG.E R26, [R12.64+0x28] ;
FFMA R11, R8, R11, R9 ;
IMAD.WIDE R8, R2, 0x4, R24 ;
LDG.E R22, [R22.64] ;
LDG.E R17, [R12.64+0x2c] ;
FFMA R21, R10, R21, R11 ;
LDG.E R15, [R24.64] ;
IMAD.WIDE R10, R2, 0x4, R8 ;
LDG.E R19, [R8.64] ;
LDG.E R23, [R10.64] ;
LDG.E R24, [R12.64+0x30] ;
LDG.E R25, [R12.64+0x38] ;
LDG.E R8, [R12.64+0x3c] ;
FFMA R9, R28, R27, R21 ;
LDG.E R28, [R12.64+0x34] ;
IMAD.WIDE R20, R2, 0x4, R10 ;
LDG.E R27, [R20.64] ;
IADD3 R6, R6, -0x10, RZ ;
ISETP.GT.AND P1, PT, R6, 0xc, PT ;
FFMA R7, R14, R7, R9 ;
FFMA R7, R16, R29, R7 ;
FFMA R7, R18, R26, R7 ;
FFMA R7, R22, R17, R7 ;
UIADD3 UR6, UP0, UR6, 0x40, URZ ;
IADD3 R3, R3, 0x10, RZ ;
UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ;
FFMA R7, R15, R24, R7 ;
FFMA R28, R19, R28, R7 ;
FFMA R28, R23, R25, R28 ;
IMAD.WIDE R24, R2, 0x4, R20 ;
FFMA R28, R27, R8, R28 ;
@P1 BRA 0x1b0 ;
ISETP.GT.AND P1, PT, R6, 0x4, PT ;
@!P1 BRA 0x8e0 ;
IMAD.WIDE R16, R2, 0x4, R24 ;
MOV R8, UR6 ;
LDG.E R7, [R24.64] ;
MOV R9, UR7 ;
IMAD.WIDE R12, R2, 0x4, R16 ;
LDG.E R21, [R16.64] ;
IMAD.WIDE R8, R4, 0x4, R8 ;
LDG.E R23, [R12.64] ;
IMAD.WIDE R14, R2.reuse, 0x4, R12 ;
LDG.E R20, [R8.64] ;
LDG.E R22, [R8.64+0x4] ;
IMAD.WIDE R10, R2, 0x4, R14 ;
LDG.E R26, [R8.64+0x8] ;
IMAD.WIDE R16, R2.reuse, 0x4, R10 ;
LDG.E R14, [R14.64] ;
LDG.E R27, [R8.64+0xc] ;
IMAD.WIDE R18, R2, 0x4, R16 ;
LDG.E R10, [R10.64] ;
LDG.E R25, [R8.64+0x10] ;
IMAD.WIDE R12, R2, 0x4, R18 ;
LDG.E R16, [R16.64] ;
LDG.E R29, [R8.64+0x14] ;
LDG.E R24, [R18.64] ;
LDG.E R11, [R8.64+0x18] ;
LDG.E R15, [R12.64] ;
LDG.E R18, [R8.64+0x1c] ;
UIADD3 UR6, UP0, UR6, 0x20, URZ ;
PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ;
IADD3 R3, R3, 0x8, RZ ;
IADD3 R6, R6, -0x8, RZ ;
UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ;
FFMA R7, R7, R20, R28 ;
FFMA R7, R21, R22, R7 ;
FFMA R7, R23, R26, R7 ;
FFMA R7, R14, R27, R7 ;
FFMA R7, R10, R25, R7 ;
FFMA R7, R16, R29, R7 ;
FFMA R7, R24, R11, R7 ;
IMAD.WIDE R24, R2, 0x4, R12 ;
FFMA R28, R15, R18, R7 ;
ISETP.NE.OR P0, PT, R6, RZ, P0 ;
@!P0 BRA 0xa90 ;
MOV R8, UR6 ;
IMAD.WIDE R14, R2, 0x4, R24 ;
MOV R9, UR7 ;
LDG.E R25, [R24.64] ;
IMAD.WIDE R8, R4, 0x4, R8 ;
IMAD.WIDE R12, R2.reuse, 0x4, R14 ;
LDG.E R7, [R8.64] ;
LDG.E R14, [R14.64] ;
IMAD.WIDE R10, R2, 0x4, R12 ;
LDG.E R16, [R8.64+0x4] ;
LDG.E R18, [R12.64] ;
LDG.E R17, [R8.64+0x8] ;
LDG.E R19, [R8.64+0xc] ;
LDG.E R20, [R10.64] ;
IADD3 R6, R6, -0x4, RZ ;
ISETP.NE.AND P0, PT, R6, RZ, PT ;
UIADD3 UR6, UP0, UR6, 0x10, URZ ;
IADD3 R3, R3, 0x4, RZ ;
UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ;
FFMA R7, R25, R7, R28 ;
FFMA R7, R14, R16, R7 ;
IMAD.WIDE R24, R2, 0x4, R10 ;
FFMA R7, R18, R17, R7 ;
FFMA R28, R20, R19, R7 ;
@P0 BRA 0x900 ;
ISETP.NE.AND P0, PT, R5, RZ, PT ;
@!P0 BRA 0xbb0 ;
HFMA2.MMA R8, -RZ, RZ, 0, 2.384185791015625e-07 ;
IADD3 R6, R4, R3, RZ ;
IMAD R3, R3, c[0x0][0x178], R0 ;
IMAD.WIDE R6, R6, R8, c[0x0][0x160] ;
IMAD.WIDE R8, R3, R8, c[0x0][0x168] ;
MOV R10, R6 ;
MOV R6, R10 ;
LDG.E R3, [R8.64] ;
LDG.E R6, [R6.64] ;
IADD3 R5, R5, -0x1, RZ ;
IADD3 R10, P1, R10, 0x4, RZ ;
ISETP.NE.AND P0, PT, R5, RZ, PT ;
IMAD.WIDE R8, R2, 0x4, R8 ;
IADD3.X R7, RZ, R7, RZ, P1, !PT ;
FFMA R28, R3, R6, R28 ;
@P0 BRA 0xb10 ;
IADD3 R2, R4, R0, RZ ;
MOV R3, 0x4 ;
IMAD.WIDE R2, R2, R3, c[0x0][0x170] ;
STG.E [R2.64], R28 ;
EXIT ;
BRA 0xc00;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
```
|
```amdasm
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z15MatrixMulKernelPfS_S_i ; -- Begin function _Z15MatrixMulKernelPfS_S_i
.globl _Z15MatrixMulKernelPfS_S_i
.p2align 8
.type _Z15MatrixMulKernelPfS_S_i,@function
_Z15MatrixMulKernelPfS_S_i: ; @_Z15MatrixMulKernelPfS_S_i
; %bb.0:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x18
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
v_bfe_u32 v1, v0, 10, 10
v_and_b32_e32 v0, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2)
v_mul_lo_u32 v1, v1, s2
s_cmp_lt_i32 s2, 1
s_cbranch_scc1 .LBB0_3
; %bb.1: ; %.lr.ph.preheader
v_mov_b32_e32 v3, 0
s_mov_b32 s3, s2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mov_b32_e32 v2, v3
v_lshlrev_b64 v[4:5], 2, v[1:2]
v_mov_b32_e32 v2, v0
v_mov_b32_e32 v6, v3
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v4, vcc_lo, s4, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v5, vcc_lo
.LBB0_2: ; %.lr.ph
; =>This Inner Loop Header: Depth=1
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_lshlrev_b64 v[7:8], 2, v[2:3]
v_add_nc_u32_e32 v2, s2, v2
s_add_i32 s3, s3, -1
s_cmp_lg_u32 s3, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v7, vcc_lo, s6, v7
v_add_co_ci_u32_e32 v8, vcc_lo, s7, v8, vcc_lo
global_load_b32 v9, v[4:5], off
global_load_b32 v7, v[7:8], off
v_add_co_u32 v4, vcc_lo, v4, 4
v_add_co_ci_u32_e32 v5, vcc_lo, 0, v5, vcc_lo
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v6, v9, v7
s_cbranch_scc1 .LBB0_2
s_branch .LBB0_4
.LBB0_3:
v_mov_b32_e32 v6, 0
.LBB0_4: ; %._crit_edge
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v0, v1, v0
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[0:1]
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v6, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z15MatrixMulKernelPfS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 28
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 10
.amdhsa_next_free_sgpr 8
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z15MatrixMulKernelPfS_S_i, .Lfunc_end0-_Z15MatrixMulKernelPfS_S_i
; -- End function
.section .AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 264
; NumSgprs: 10
; NumVgprs: 10
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 1
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 10
; NumVGPRsForWavesPerEU: 10
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object ; @__hip_cuid_
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0 ; 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 28
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z15MatrixMulKernelPfS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 10
.sgpr_spill_count: 0
.symbol: _Z15MatrixMulKernelPfS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 10
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
```
| 3,527 | 2,641 |
145 |
Convert the following CUDA host assembly code to AMD host assembly:
```cudaasm
.file "tmpxft_000ce093_00000000-6_mat_multiply.cudafe1.cpp"
.text
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z40__device_stub__Z15MatrixMulKernelPfS_S_iPfS_S_i
.type _Z40__device_stub__Z15MatrixMulKernelPfS_S_iPfS_S_i, @function
_Z40__device_stub__Z15MatrixMulKernelPfS_S_iPfS_S_i:
.LFB2082:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z15MatrixMulKernelPfS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z40__device_stub__Z15MatrixMulKernelPfS_S_iPfS_S_i, .-_Z40__device_stub__Z15MatrixMulKernelPfS_S_iPfS_S_i
.globl _Z15MatrixMulKernelPfS_S_i
.type _Z15MatrixMulKernelPfS_S_i, @function
_Z15MatrixMulKernelPfS_S_i:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z40__device_stub__Z15MatrixMulKernelPfS_S_iPfS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z15MatrixMulKernelPfS_S_i, .-_Z15MatrixMulKernelPfS_S_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC3:
.string "kernel time (ms) : %7.5f\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
subq $4096, %rsp
.cfi_def_cfa_offset 4104
orq $0, (%rsp)
subq $4096, %rsp
.cfi_def_cfa_offset 8200
orq $0, (%rsp)
subq $4096, %rsp
.cfi_def_cfa_offset 12296
orq $0, (%rsp)
subq $104, %rsp
.cfi_def_cfa_offset 12400
movq %fs:40, %rax
movq %rax, 12376(%rsp)
xorl %eax, %eax
leaq 16(%rsp), %rdi
call cudaEventCreate@PLT
leaq 24(%rsp), %rdi
call cudaEventCreate@PLT
movl $0, %eax
movss .LC0(%rip), %xmm3
movss .LC1(%rip), %xmm2
.L12:
pxor %xmm1, %xmm1
cvtsi2ssl %eax, %xmm1
movss %xmm1, 80(%rsp,%rax,4)
movaps %xmm3, %xmm0
subss %xmm1, %xmm0
subss %xmm2, %xmm0
movss %xmm0, 4176(%rsp,%rax,4)
movl $0x00000000, 8272(%rsp,%rax,4)
addq $1, %rax
cmpq $1024, %rax
jne .L12
leaq 32(%rsp), %rdi
movl $4096, %esi
call cudaMalloc@PLT
leaq 40(%rsp), %rdi
movl $4096, %esi
call cudaMalloc@PLT
leaq 48(%rsp), %rdi
movl $4096, %esi
call cudaMalloc@PLT
leaq 80(%rsp), %rsi
movl $1, %ecx
movl $4096, %edx
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
leaq 4176(%rsp), %rsi
movl $1, %ecx
movl $4096, %edx
movq 40(%rsp), %rdi
call cudaMemcpy@PLT
leaq 8272(%rsp), %rsi
movl $1, %ecx
movl $4096, %edx
movq 48(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $32, 68(%rsp)
movl $32, 72(%rsp)
movl $1, 76(%rsp)
movl $0, %esi
movq 16(%rsp), %rdi
call cudaEventRecord@PLT
movl 76(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 68(%rsp), %rdx
movq 56(%rsp), %rdi
movl 64(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L17
.L13:
movl $0, %esi
movq 24(%rsp), %rdi
call cudaEventRecord@PLT
movq 24(%rsp), %rdi
call cudaEventSynchronize@PLT
movl $0x00000000, 12(%rsp)
leaq 12(%rsp), %rdi
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
call cudaEventElapsedTime@PLT
pxor %xmm0, %xmm0
cvtss2sd 12(%rsp), %xmm0
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
leaq 8272(%rsp), %rdi
movl $2, %ecx
movl $4096, %edx
movq 48(%rsp), %rsi
call cudaMemcpy@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
movq 48(%rsp), %rdi
call cudaFree@PLT
movq 12376(%rsp), %rax
subq %fs:40, %rax
jne .L18
movl $0, %eax
addq $12392, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L17:
.cfi_restore_state
movl $32, %ecx
movq 48(%rsp), %rdx
movq 40(%rsp), %rsi
movq 32(%rsp), %rdi
call _Z40__device_stub__Z15MatrixMulKernelPfS_S_iPfS_S_i
jmp .L13
.L18:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC4:
.string "_Z15MatrixMulKernelPfS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z15MatrixMulKernelPfS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC0:
.long 1149239296
.align 4
.LC1:
.long 1065353216
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
```
|
```amdasm
.text
.file "mat_multiply.hip"
.globl _Z30__device_stub__MatrixMulKernelPfS_S_i # -- Begin function _Z30__device_stub__MatrixMulKernelPfS_S_i
.type _Z30__device_stub__MatrixMulKernelPfS_S_i,@function
_Z30__device_stub__MatrixMulKernelPfS_S_i: # @_Z30__device_stub__MatrixMulKernelPfS_S_i
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $112, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 40(%rsp), %rax
movq %rdi, (%rax)
leaq 32(%rsp), %rdi
movq %rsi, (%rdi)
leaq 24(%rsp), %rsi
movq %rdx, (%rsi)
leaq 4(%rsp), %rdx
movl %ecx, (%rdx)
leaq 80(%rsp), %rbx
movq %rax, (%rbx)
movq %rdi, 8(%rbx)
movq %rsi, 16(%rbx)
movq %rdx, 24(%rbx)
leaq 64(%rsp), %r14
leaq 48(%rsp), %r15
leaq 16(%rsp), %r12
leaq 8(%rsp), %r13
movq %r14, %rdi
movq %r15, %rsi
movq %r12, %rdx
movq %r13, %rcx
callq __hipPopCallConfiguration
movq (%r14), %rsi
movl 8(%r14), %edx
movq (%r15), %rcx
movl 8(%r15), %r8d
movl $_Z15MatrixMulKernelPfS_S_i, %edi
movq %rbx, %r9
pushq (%r13)
.cfi_adjust_cfa_offset 8
pushq (%r12)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $128, %rsp
.cfi_adjust_cfa_offset -128
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z30__device_stub__MatrixMulKernelPfS_S_i, .Lfunc_end0-_Z30__device_stub__MatrixMulKernelPfS_S_i
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI1_0:
.long 0x44800000 # float 1024
.LCPI1_1:
.long 0xbf800000 # float -1
.text
.globl main
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $12336, %rsp # imm = 0x3030
.cfi_def_cfa_offset 12368
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 32(%rsp), %rdi
callq hipEventCreate
leaq 8(%rsp), %rdi
callq hipEventCreate
leaq 48(%rsp), %rdi
xorl %ebx, %ebx
movl $4096, %edx # imm = 0x1000
xorl %esi, %esi
callq memset@PLT
movss .LCPI1_0(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero
movss .LCPI1_1(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero
.LBB1_1: # =>This Inner Loop Header: Depth=1
xorps %xmm2, %xmm2
cvtsi2ss %ebx, %xmm2
movss %xmm2, 8240(%rsp,%rbx,4)
movaps %xmm0, %xmm3
subss %xmm2, %xmm3
addss %xmm1, %xmm3
movss %xmm3, 4144(%rsp,%rbx,4)
incq %rbx
cmpq $1024, %rbx # imm = 0x400
jne .LBB1_1
# %bb.2:
leaq 24(%rsp), %rbx
movl $4096, %esi # imm = 0x1000
movq %rbx, %rdi
callq hipMalloc
leaq 16(%rsp), %r14
movl $4096, %esi # imm = 0x1000
movq %r14, %rdi
callq hipMalloc
movq %rsp, %r15
movl $4096, %esi # imm = 0x1000
movq %r15, %rdi
callq hipMalloc
movq (%rbx), %rdi
leaq 8240(%rsp), %rsi
movl $4096, %edx # imm = 0x1000
movl $1, %ecx
callq hipMemcpy
movq (%r14), %rdi
leaq 4144(%rsp), %rsi
movl $4096, %edx # imm = 0x1000
movl $1, %ecx
callq hipMemcpy
movq (%r15), %rdi
leaq 48(%rsp), %rsi
movl $4096, %edx # imm = 0x1000
movl $1, %ecx
callq hipMemcpy
movq 32(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movabsq $4294967297, %rdi # imm = 0x100000001
movabsq $137438953504, %rdx # imm = 0x2000000020
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq 24(%rsp), %rdi
movq 16(%rsp), %rsi
movq (%rsp), %rdx
movl $32, %ecx
callq _Z30__device_stub__MatrixMulKernelPfS_S_i
.LBB1_4:
movq 8(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 8(%rsp), %rdi
callq hipEventSynchronize
leaq 44(%rsp), %rbx
movl $0, (%rbx)
movq 32(%rsp), %rsi
movq 8(%rsp), %rdx
movq %rbx, %rdi
callq hipEventElapsedTime
xorps %xmm0, %xmm0
cvtss2sd (%rbx), %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
movq (%rsp), %rsi
leaq 48(%rsp), %rdi
movl $4096, %edx # imm = 0x1000
movl $2, %ecx
callq hipMemcpy
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $12336, %rsp # imm = 0x3030
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, %rdi
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15MatrixMulKernelPfS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z15MatrixMulKernelPfS_S_i,@object # @_Z15MatrixMulKernelPfS_S_i
.section .rodata,"a",@progbits
.globl _Z15MatrixMulKernelPfS_S_i
.p2align 3, 0x0
_Z15MatrixMulKernelPfS_S_i:
.quad _Z30__device_stub__MatrixMulKernelPfS_S_i
.size _Z15MatrixMulKernelPfS_S_i, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "kernel time (ms) : %7.5f\n"
.size .L.str, 26
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z15MatrixMulKernelPfS_S_i"
.size .L__unnamed_1, 27
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z30__device_stub__MatrixMulKernelPfS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z15MatrixMulKernelPfS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
```
| 3,399 | 3,731 |
148 |
Convert the following CUDA device assembly code to AMD device assembly:
```cudaasm
code for sm_80
Function : _Z18backtestStrategiesP8Strategy
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
MOV R1, c[0x0][0x28] ;
S2R R0, SR_CTAID.X ;
S2R R3, SR_TID.X ;
IMAD R0, R0, c[0x0][0x0], R3 ;
ISETP.GT.AND P0, PT, R0, 0x30d3f, PT ;
@P0 EXIT ;
ULDC.64 UR4, c[0x0][0x118] ;
HFMA2.MMA R3, -RZ, RZ, 0, 4.76837158203125e-07 ;
IMAD.WIDE R2, R0, R3, c[0x0][0x160] ;
LDG.E.64 R4, [R2.64] ;
MOV R7, c[0x0][0x0] ;
IMAD R0, R7, c[0x0][0xc], R0 ;
ISETP.GE.AND P0, PT, R0, 0x30d40, PT ;
DADD R4, R4, 1 ;
STG.E.64 [R2.64], R4 ;
@!P0 BRA 0x70 ;
EXIT ;
BRA 0x110;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
```
|
```amdasm
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z18backtestStrategiesP8Strategy ; -- Begin function _Z18backtestStrategiesP8Strategy
.globl _Z18backtestStrategiesP8Strategy
.p2align 8
.type _Z18backtestStrategiesP8Strategy,@function
_Z18backtestStrategiesP8Strategy: ; @_Z18backtestStrategiesP8Strategy
; %bb.0:
s_load_b32 s4, s[0:1], 0x14
s_add_u32 s2, s0, 8
s_addc_u32 s3, s1, 0
s_mov_b32 s5, exec_lo
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
v_cmpx_gt_i32_e32 0x30d40, v1
s_cbranch_execz .LBB0_3
; %bb.1: ; %.lr.ph
s_load_b32 s2, s[2:3], 0x0
s_load_b64 s[0:1], s[0:1], 0x0
s_mov_b32 s3, 0
s_waitcnt lgkmcnt(0)
s_mul_i32 s2, s2, s4
.LBB0_2: ; =>This Inner Loop Header: Depth=1
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[2:3], 3, v[1:2]
v_add_nc_u32_e32 v1, s2, v1
v_add_co_u32 v2, vcc_lo, s0, v2
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
v_cmp_lt_i32_e32 vcc_lo, 0x30d3f, v1
global_load_b64 v[4:5], v[2:3], off
s_or_b32 s3, vcc_lo, s3
s_waitcnt vmcnt(0)
v_add_f64 v[4:5], v[4:5], 1.0
global_store_b64 v[2:3], v[4:5], off
s_and_not1_b32 exec_lo, exec_lo, s3
s_cbranch_execnz .LBB0_2
.LBB0_3: ; %Flow6
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z18backtestStrategiesP8Strategy
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 264
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z18backtestStrategiesP8Strategy, .Lfunc_end0-_Z18backtestStrategiesP8Strategy
; -- End function
.section .AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 180
; NumSgprs: 18
; NumVgprs: 6
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 6
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object ; @__hip_cuid_
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0 ; 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: hidden_block_count_x
- .offset: 12
.size: 4
.value_kind: hidden_block_count_y
- .offset: 16
.size: 4
.value_kind: hidden_block_count_z
- .offset: 20
.size: 2
.value_kind: hidden_group_size_x
- .offset: 22
.size: 2
.value_kind: hidden_group_size_y
- .offset: 24
.size: 2
.value_kind: hidden_group_size_z
- .offset: 26
.size: 2
.value_kind: hidden_remainder_x
- .offset: 28
.size: 2
.value_kind: hidden_remainder_y
- .offset: 30
.size: 2
.value_kind: hidden_remainder_z
- .offset: 48
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 72
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 264
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z18backtestStrategiesP8Strategy
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z18backtestStrategiesP8Strategy.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
```
| 403 | 2,556 |
149 |
Convert the following CUDA host assembly code to AMD host assembly:
```cudaasm
.file "tmpxft_001b7f5d_00000000-6_class.cudafe1.cpp"
.text
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2070:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2070:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z46__device_stub__Z18backtestStrategiesP8StrategyP8Strategy
.type _Z46__device_stub__Z18backtestStrategiesP8StrategyP8Strategy, @function
_Z46__device_stub__Z18backtestStrategiesP8StrategyP8Strategy:
.LFB2092:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z18backtestStrategiesP8Strategy(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2092:
.size _Z46__device_stub__Z18backtestStrategiesP8StrategyP8Strategy, .-_Z46__device_stub__Z18backtestStrategiesP8StrategyP8Strategy
.globl _Z18backtestStrategiesP8Strategy
.type _Z18backtestStrategiesP8Strategy, @function
_Z18backtestStrategiesP8Strategy:
.LFB2093:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z46__device_stub__Z18backtestStrategiesP8StrategyP8Strategy
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2093:
.size _Z18backtestStrategiesP8Strategy, .-_Z18backtestStrategiesP8Strategy
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "%f\n"
.text
.globl main
.type main, @function
main:
.LFB2067:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $56, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movl $1600000, %edi
call malloc@PLT
movq %rax, %r13
leaq 8(%rsp), %rdi
movl $1600000, %esi
call cudaMalloc@PLT
movq %r13, %rbx
leaq 1600000(%r13), %r12
movq %r13, %rax
.L12:
movq $0x000000000, (%rax)
addq $8, %rax
cmpq %r12, %rax
jne .L12
movl $1, %ecx
movl $1600000, %edx
movq %r13, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $363598, %ebp
jmp .L14
.L13:
subl $1, %ebp
je .L21
.L14:
movl $1024, 28(%rsp)
movl $1, 32(%rsp)
movl $32, 16(%rsp)
movl $1, 20(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L13
movq 8(%rsp), %rdi
call _Z46__device_stub__Z18backtestStrategiesP8StrategyP8Strategy
jmp .L13
.L21:
movl $2, %ecx
movl $1600000, %edx
movq 8(%rsp), %rsi
movq %r13, %rdi
call cudaMemcpy@PLT
leaq .LC1(%rip), %rbp
.L15:
movsd (%rbx), %xmm0
movq %rbp, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $8, %rbx
cmpq %r12, %rbx
jne .L15
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L22
movl $0, %eax
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L22:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2067:
.size main, .-main
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC2:
.string "_Z18backtestStrategiesP8Strategy"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2095:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z18backtestStrategiesP8Strategy(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2095:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
```
|
```amdasm
.text
.file "class.hip"
.globl _Z33__device_stub__backtestStrategiesP8Strategy # -- Begin function _Z33__device_stub__backtestStrategiesP8Strategy
.type _Z33__device_stub__backtestStrategiesP8Strategy,@function
_Z33__device_stub__backtestStrategiesP8Strategy: # @_Z33__device_stub__backtestStrategiesP8Strategy
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $64, %rsp
.cfi_def_cfa_offset 112
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 24(%rsp), %rax
movq %rdi, (%rax)
movq %rsp, %rbx
movq %rax, (%rbx)
leaq 48(%rsp), %r14
leaq 32(%rsp), %r15
leaq 16(%rsp), %r12
leaq 8(%rsp), %r13
movq %r14, %rdi
movq %r15, %rsi
movq %r12, %rdx
movq %r13, %rcx
callq __hipPopCallConfiguration
movq (%r14), %rsi
movl 8(%r14), %edx
movq (%r15), %rcx
movl 8(%r15), %r8d
movl $_Z18backtestStrategiesP8Strategy, %edi
movq %rbx, %r9
pushq (%r13)
.cfi_adjust_cfa_offset 8
pushq (%r12)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $80, %rsp
.cfi_adjust_cfa_offset -80
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z33__device_stub__backtestStrategiesP8Strategy, .Lfunc_end0-_Z33__device_stub__backtestStrategiesP8Strategy
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
pushq %rax
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movabsq $4294967328, %r14 # imm = 0x100000020
movl $1, %edi
movl $1600000, %esi # imm = 0x186A00
callq calloc@PLT
movq %rax, %rbx
movq %rsp, %r15
movl $1600000, %esi # imm = 0x186A00
movq %r15, %rdi
callq hipMalloc
movq (%r15), %rdi
movl $1600000, %edx # imm = 0x186A00
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movl $363598, %ebp # imm = 0x58C4E
leaq 992(%r14), %r15
.LBB1_1: # =>This Inner Loop Header: Depth=1
movq %r14, %rdi
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_3
# %bb.2: # in Loop: Header=BB1_1 Depth=1
movq (%rsp), %rdi
callq _Z33__device_stub__backtestStrategiesP8Strategy
.LBB1_3: # in Loop: Header=BB1_1 Depth=1
decl %ebp
jne .LBB1_1
# %bb.4:
movq (%rsp), %rsi
movl $1600000, %edx # imm = 0x186A00
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
xorl %r14d, %r14d
.LBB1_5: # =>This Inner Loop Header: Depth=1
movsd (%rbx,%r14,8), %xmm0 # xmm0 = mem[0],zero
movl $.L.str, %edi
movb $1, %al
callq printf
incq %r14
cmpq $200000, %r14 # imm = 0x30D40
jne .LBB1_5
# %bb.6:
movq (%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, %rdi
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z18backtestStrategiesP8Strategy, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z18backtestStrategiesP8Strategy,@object # @_Z18backtestStrategiesP8Strategy
.section .rodata,"a",@progbits
.globl _Z18backtestStrategiesP8Strategy
.p2align 3, 0x0
_Z18backtestStrategiesP8Strategy:
.quad _Z33__device_stub__backtestStrategiesP8Strategy
.size _Z18backtestStrategiesP8Strategy, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%f\n"
.size .L.str, 4
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z18backtestStrategiesP8Strategy"
.size .L__unnamed_1, 33
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z33__device_stub__backtestStrategiesP8Strategy
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z18backtestStrategiesP8Strategy
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
```
| 2,824 | 2,989 |
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