module
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|
|---|
module Subtractor_0x422b1f52edd46a85
(
input wire [ 0:0] clk,
input wire [ 15:0] in0,
input wire [ 15:0] in1,
output reg [ 15:0] out,
input wire [ 0:0] reset
);
// PYMTL SOURCE:
//
// @s.combinational
// def comb_logic():
// s.out.value = s.in0 - s.in1
// logic for comb_logic()
always @ (*) begin
out = (in0-in1);
end
endmodule
|
module Mux_0xdd6473406d1a99a
(
input wire [ 0:0] clk,
input wire [ 15:0] in_$000,
input wire [ 15:0] in_$001,
output reg [ 15:0] out,
input wire [ 0:0] reset,
input wire [ 0:0] sel
);
// localparam declarations
localparam nports = 2;
// array declarations
wire [ 15:0] in_[0:1];
assign in_[ 0] = in_$000;
assign in_[ 1] = in_$001;
// PYMTL SOURCE:
//
// @s.combinational
// def comb_logic():
// assert s.sel < nports
// s.out.v = s.in_[ s.sel ]
// logic for comb_logic()
always @ (*) begin
out = in_[sel];
end
endmodule
|
module RegEn_0x68db79c4ec1d6e5b
(
input wire [ 0:0] clk,
input wire [ 0:0] en,
input wire [ 15:0] in_,
output reg [ 15:0] out,
input wire [ 0:0] reset
);
// PYMTL SOURCE:
//
// @s.posedge_clk
// def seq_logic():
// if s.en:
// s.out.next = s.in_
// logic for seq_logic()
always @ (posedge clk) begin
if (en) begin
out <= in_;
end
else begin
end
end
endmodule
|
module RegRst_0x9f365fdf6c8998a
(
input wire [ 0:0] clk,
input wire [ 1:0] in_,
output reg [ 1:0] out,
input wire [ 0:0] reset
);
// localparam declarations
localparam reset_value = 0;
// PYMTL SOURCE:
//
// @s.posedge_clk
// def seq_logic():
// if s.reset:
// s.out.next = reset_value
// else:
// s.out.next = s.in_
// logic for seq_logic()
always @ (posedge clk) begin
if (reset) begin
out <= reset_value;
end
else begin
out <= in_;
end
end
endmodule
|
module ZeroComparator_0x422b1f52edd46a85
(
input wire [ 0:0] clk,
input wire [ 15:0] in_,
output reg [ 0:0] out,
input wire [ 0:0] reset
);
// PYMTL SOURCE:
//
// @s.combinational
// def comb_logic():
// s.out.value = s.in_ == 0
// logic for comb_logic()
always @ (*) begin
out = (in_ == 0);
end
endmodule
|
module LtComparator_0x422b1f52edd46a85
(
input wire [ 0:0] clk,
input wire [ 15:0] in0,
input wire [ 15:0] in1,
output reg [ 0:0] out,
input wire [ 0:0] reset
);
// PYMTL SOURCE:
//
// @s.combinational
// def comb_logic():
// s.out.value = s.in0 < s.in1
// logic for comb_logic()
always @ (*) begin
out = (in0 < in1);
end
endmodule
|
module Mux_0x683fa1a418b072c9
(
input wire [ 0:0] clk,
input wire [ 15:0] in_$000,
input wire [ 15:0] in_$001,
input wire [ 15:0] in_$002,
output reg [ 15:0] out,
input wire [ 0:0] reset,
input wire [ 1:0] sel
);
// localparam declarations
localparam nports = 3;
// array declarations
wire [ 15:0] in_[0:2];
assign in_[ 0] = in_$000;
assign in_[ 1] = in_$001;
assign in_[ 2] = in_$002;
// PYMTL SOURCE:
//
// @s.combinational
// def comb_logic():
// assert s.sel < nports
// s.out.v = s.in_[ s.sel ]
// logic for comb_logic()
always @ (*) begin
out = in_[sel];
end
endmodule
|
module PMPChecker( // @[:[email protected]]
input io_pmp_0_cfg_l, // @[:[email protected]]
input [1:0] io_pmp_0_cfg_a, // @[:[email protected]]
input io_pmp_0_cfg_x, // @[:[email protected]]
input io_pmp_0_cfg_w, // @[:[email protected]]
input io_pmp_0_cfg_r, // @[:[email protected]]
input [29:0] io_pmp_0_addr, // @[:[email protected]]
input [31:0] io_pmp_0_mask, // @[:[email protected]]
input io_pmp_1_cfg_l, // @[:[email protected]]
input [1:0] io_pmp_1_cfg_a, // @[:[email protected]]
input io_pmp_1_cfg_x, // @[:[email protected]]
input io_pmp_1_cfg_w, // @[:[email protected]]
input io_pmp_1_cfg_r, // @[:[email protected]]
input [29:0] io_pmp_1_addr, // @[:[email protected]]
input [31:0] io_pmp_1_mask, // @[:[email protected]]
input io_pmp_2_cfg_l, // @[:[email protected]]
input [1:0] io_pmp_2_cfg_a, // @[:[email protected]]
input io_pmp_2_cfg_x, // @[:[email protected]]
input io_pmp_2_cfg_w, // @[:[email protected]]
input io_pmp_2_cfg_r, // @[:[email protected]]
input [29:0] io_pmp_2_addr, // @[:[email protected]]
input [31:0] io_pmp_2_mask, // @[:[email protected]]
input io_pmp_3_cfg_l, // @[:[email protected]]
input [1:0] io_pmp_3_cfg_a, // @[:[email protected]]
input io_pmp_3_cfg_x, // @[:[email protected]]
input io_pmp_3_cfg_w, // @[:[email protected]]
input io_pmp_3_cfg_r, // @[:[email protected]]
input [29:0] io_pmp_3_addr, // @[:[email protected]]
input [31:0] io_pmp_3_mask, // @[:[email protected]]
input io_pmp_4_cfg_l, // @[:[email protected]]
input [1:0] io_pmp_4_cfg_a, // @[:[email protected]]
input io_pmp_4_cfg_x, // @[:[email protected]]
input io_pmp_4_cfg_w, // @[:[email protected]]
input io_pmp_4_cfg_r, // @[:[email protected]]
input [29:0] io_pmp_4_addr, // @[:[email protected]]
input [31:0] io_pmp_4_mask, // @[:[email protected]]
input io_pmp_5_cfg_l, // @[:[email protected]]
input [1:0] io_pmp_5_cfg_a, // @[:[email protected]]
input io_pmp_5_cfg_x, // @[:[email protected]]
input io_pmp_5_cfg_w, // @[:[email protected]]
input io_pmp_5_cfg_r, // @[:[email protected]]
input [29:0] io_pmp_5_addr, // @[:[email protected]]
input [31:0] io_pmp_5_mask, // @[:[email protected]]
input io_pmp_6_cfg_l, // @[:[email protected]]
input [1:0] io_pmp_6_cfg_a, // @[:[email protected]]
input io_pmp_6_cfg_x, // @[:[email protected]]
input io_pmp_6_cfg_w, // @[:[email protected]]
input io_pmp_6_cfg_r, // @[:[email protected]]
input [29:0] io_pmp_6_addr, // @[:[email protected]]
input [31:0] io_pmp_6_mask, // @[:[email protected]]
input io_pmp_7_cfg_l, // @[:[email protected]]
input [1:0] io_pmp_7_cfg_a, // @[:[email protected]]
input io_pmp_7_cfg_x, // @[:[email protected]]
input io_pmp_7_cfg_w, // @[:[email protected]]
input io_pmp_7_cfg_r, // @[:[email protected]]
input [29:0] io_pmp_7_addr, // @[:[email protected]]
input [31:0] io_pmp_7_mask, // @[:[email protected]]
input [31:0] io_addr, // @[:[email protected]]
output io_r, // @[:[email protected]]
output io_w, // @[:[email protected]]
output io_x // @[:[email protected]]
);
wire _T_10; // @[PMP.scala 45:20:[email protected]]
wire [31:0] _T_11; // @[PMP.scala 60:36:[email protected]]
wire [31:0] _T_12; // @[PMP.scala 60:29:[email protected]]
wire [31:0] _T_13; // @[PMP.scala 60:48:[email protected]]
wire [31:0] _T_14; // @[PMP.scala 60:27:[email protected]]
wire [31:0] _T_15; // @[PMP.scala 63:47:[email protected]]
wire [31:0] _T_16; // @[PMP.scala 63:54:[email protected]]
wire [31:0] _T_17; // @[PMP.scala 63:52:[email protected]]
wire _T_18; // @[PMP.scala 63:58:[email protected]]
wire _T_19; // @[PMP.scala 46:26:[email protected]]
wire [31:0] _T_24; // @[PMP.scala 60:36:[email protected]]
wire [31:0] _T_25; // @[PMP.scala 60:29:[email protected]]
wire [31:0] _T_26; // @[PMP.scala 60:48:[email protected]]
wire [31:0] _T_27; // @[PMP.scala 60:27:[email protected]]
wire _T_28; // @[PMP.scala 77:9:[email protected]]
wire _T_29; // @[PMP.scala 88:5:[email protected]]
wire _T_34; // @[PMP.scala 77:9:[email protected]]
wire _T_35; // @[PMP.scala 94:48:[email protected]]
wire _T_36; // @[PMP.scala 132:61:[email protected]]
wire _T_37; // @[PMP.scala 132:8:[email protected]]
wire _T_38; // @[PMP.scala 163:29:[email protected]]
wire _T_91; // @[PMP.scala 181:40:[email protected]]
wire _T_93; // @[PMP.scala 182:40:[email protected]]
wire _T_95; // @[PMP.scala 183:40:[email protected]]
wire _T_97_cfg_x; // @[PMP.scala 184:8:[email protected]]
wire _T_97_cfg_w; // @[PMP.scala 184:8:[email protected]]
wire _T_97_cfg_r; // @[PMP.scala 184:8:[email protected]]
wire _T_98; // @[PMP.scala 45:20:[email protected]]
wire [31:0] _T_103; // @[PMP.scala 63:47:[email protected]]
wire [31:0] _T_104; // @[PMP.scala 63:54:[email protected]]
wire [31:0] _T_105; // @[PMP.scala 63:52:[email protected]]
wire _T_106; // @[PMP.scala 63:58:[email protected]]
wire _T_107; // @[PMP.scala 46:26:[email protected]]
wire [31:0] _T_112; // @[PMP.scala 60:36:[email protected]]
wire [31:0] _T_113; // @[PMP.scala 60:29:[email protected]]
wire [31:0] _T_114; // @[PMP.scala 60:48:[email protected]]
wire [31:0] _T_115; // @[PMP.scala 60:27:[email protected]]
wire _T_116; // @[PMP.scala 77:9:[email protected]]
wire _T_117; // @[PMP.scala 88:5:[email protected]]
wire _T_123; // @[PMP.scala 94:48:[email protected]]
wire _T_124; // @[PMP.scala 132:61:[email protected]]
wire _T_125; // @[PMP.scala 132:8:[email protected]]
wire _T_126; // @[PMP.scala 163:29:[email protected]]
wire _T_179; // @[PMP.scala 181:40:[email protected]]
wire _T_181; // @[PMP.scala 182:40:[email protected]]
wire _T_183; // @[PMP.scala 183:40:[email protected]]
wire _T_185_cfg_x; // @[PMP.scala 184:8:[email protected]]
wire _T_185_cfg_w; // @[PMP.scala 184:8:[email protected]]
wire _T_185_cfg_r; // @[PMP.scala 184:8:[email protected]]
wire _T_186; // @[PMP.scala 45:20:[email protected]]
wire [31:0] _T_191; // @[PMP.scala 63:47:[email protected]]
wire [31:0] _T_192; // @[PMP.scala 63:54:[email protected]]
wire [31:0] _T_193; // @[PMP.scala 63:52:[email protected]]
wire _T_194; // @[PMP.scala 63:58:[email protected]]
wire _T_195; // @[PMP.scala 46:26:[email protected]]
wire [31:0] _T_200; // @[PMP.scala 60:36:[email protected]]
wire [31:0] _T_201; // @[PMP.scala 60:29:[email protected]]
wire [31:0] _T_202; // @[PMP.scala 60:48:[email protected]]
wire [31:0] _T_203; // @[PMP.scala 60:27:[email protected]]
wire _T_204; // @[PMP.scala 77:9:[email protected]]
wire _T_205; // @[PMP.scala 88:5:[email protected]]
wire _T_211; // @[PMP.scala 94:48:[email protected]]
wire _T_212; // @[PMP.scala 132:61:[email protected]]
wire _T_213; // @[PMP.scala 132:8:[email protected]]
wire _T_214; // @[PMP.scala 163:29:[email protected]]
wire _T_267; // @[PMP.scala 181:40:[email protected]]
wire _T_269; // @[PMP.scala 182:40:[email protected]]
wire _T_271; // @[PMP.scala 183:40:[email protected]]
wire _T_273_cfg_x; // @[PMP.scala 184:8:[email protected]]
wire _T_273_cfg_w; // @[PMP.scala 184:8:[email protected]]
wire _T_273_cfg_r; // @[PMP.scala 184:8:[email protected]]
wire _T_274; // @[PMP.scala 45:20:[email protected]]
wire [31:0] _T_279; // @[PMP.scala 63:47:[email protected]]
wire [31:0] _T_280; // @[PMP.scala 63:54:[email protected]]
wire [31:0] _T_281; // @[PMP.scala 63:52:[email protected]]
wire _T_282; // @[PMP.scala 63:58:[email protected]]
wire _T_283; // @[PMP.scala 46:26:[email protected]]
wire [31:0] _T_288; // @[PMP.scala 60:36:[email protected]]
wire [31:0] _T_289; // @[PMP.scala 60:29:[email protected]]
wire [31:0] _T_290; // @[PMP.scala 60:48:[email protected]]
wire [31:0] _T_291; // @[PMP.scala 60:27:[email protected]]
wire _T_292; // @[PMP.scala 77:9:[email protected]]
wire _T_293; // @[PMP.scala 88:5:[email protected]]
wire _T_299; // @[PMP.scala 94:48:[email protected]]
wire _T_300; // @[PMP.scala 132:61:[email protected]]
wire _T_301; // @[PMP.scala 132:8:[email protected]]
wire _T_302; // @[PMP.scala 163:29:[email protected]]
wire _T_355; // @[PMP.scala 181:40:[email protected]]
wire _T_357; // @[PMP.scala 182:40:[email protected]]
wire _T_359; // @[PMP.scala 183:40:[email protected]]
wire _T_361_cfg_x; // @[PMP.scala 184:8:[email protected]]
wire _T_361_cfg_w; // @[PMP.scala 184:8:[email protected]]
wire _T_361_cfg_r; // @[PMP.scala 184:8:[email protected]]
wire _T_362; // @[PMP.scala 45:20:[email protected]]
wire [31:0] _T_367; // @[PMP.scala 63:47:[email protected]]
wire [31:0] _T_368; // @[PMP.scala 63:54:[email protected]]
wire [31:0] _T_369; // @[PMP.scala 63:52:[email protected]]
wire _T_370; // @[PMP.scala 63:58:[email protected]]
wire _T_371; // @[PMP.scala 46:26:[email protected]]
wire [31:0] _T_376; // @[PMP.scala 60:36:[email protected]]
wire [31:0] _T_377; // @[PMP.scala 60:29:[email protected]]
wire [31:0] _T_378; // @[PMP.scala 60:48:[email protected]]
wire [31:0] _T_379; // @[PMP.scala 60:27:[email protected]]
wire _T_380; // @[PMP.scala 77:9:[email protected]]
wire _T_381; // @[PMP.scala 88:5:[email protected]]
wire _T_387; // @[PMP.scala 94:48:[email protected]]
wire _T_388; // @[PMP.scala 132:61:[email protected]]
wire _T_389; // @[PMP.scala 132:8:[email protected]]
wire _T_390; // @[PMP.scala 163:29:[email protected]]
wire _T_443; // @[PMP.scala 181:40:[email protected]]
wire _T_445; // @[PMP.scala 182:40:[email protected]]
wire _T_447; // @[PMP.scala 183:40:[email protected]]
wire _T_449_cfg_x; // @[PMP.scala 184:8:[email protected]]
wire _T_449_cfg_w; // @[PMP.scala 184:8:[email protected]]
wire _T_449_cfg_r; // @[PMP.scala 184:8:[email protected]]
wire _T_450; // @[PMP.scala 45:20:[email protected]]
wire [31:0] _T_455; // @[PMP.scala 63:47:[email protected]]
wire [31:0] _T_456; // @[PMP.scala 63:54:[email protected]]
wire [31:0] _T_457; // @[PMP.scala 63:52:[email protected]]
wire _T_458; // @[PMP.scala 63:58:[email protected]]
wire _T_459; // @[PMP.scala 46:26:[email protected]]
wire [31:0] _T_464; // @[PMP.scala 60:36:[email protected]]
wire [31:0] _T_465; // @[PMP.scala 60:29:[email protected]]
wire [31:0] _T_466; // @[PMP.scala 60:48:[email protected]]
wire [31:0] _T_467; // @[PMP.scala 60:27:[email protected]]
wire _T_468; // @[PMP.scala 77:9:[email protected]]
wire _T_469; // @[PMP.scala 88:5:[email protected]]
wire _T_475; // @[PMP.scala 94:48:[email protected]]
wire _T_476; // @[PMP.scala 132:61:[email protected]]
wire _T_477; // @[PMP.scala 132:8:[email protected]]
wire _T_478; // @[PMP.scala 163:29:[email protected]]
wire _T_531; // @[PMP.scala 181:40:[email protected]]
wire _T_533; // @[PMP.scala 182:40:[email protected]]
wire _T_535; // @[PMP.scala 183:40:[email protected]]
wire _T_537_cfg_x; // @[PMP.scala 184:8:[email protected]]
wire _T_537_cfg_w; // @[PMP.scala 184:8:[email protected]]
wire _T_537_cfg_r; // @[PMP.scala 184:8:[email protected]]
wire _T_538; // @[PMP.scala 45:20:[email protected]]
wire [31:0] _T_543; // @[PMP.scala 63:47:[email protected]]
wire [31:0] _T_544; // @[PMP.scala 63:54:[email protected]]
wire [31:0] _T_545; // @[PMP.scala 63:52:[email protected]]
wire _T_546; // @[PMP.scala 63:58:[email protected]]
wire _T_547; // @[PMP.scala 46:26:[email protected]]
wire [31:0] _T_552; // @[PMP.scala 60:36:[email protected]]
wire [31:0] _T_553; // @[PMP.scala 60:29:[email protected]]
wire [31:0] _T_554; // @[PMP.scala 60:48:[email protected]]
wire [31:0] _T_555; // @[PMP.scala 60:27:[email protected]]
wire _T_556; // @[PMP.scala 77:9:[email protected]]
wire _T_557; // @[PMP.scala 88:5:[email protected]]
wire _T_563; // @[PMP.scala 94:48:[email protected]]
wire _T_564; // @[PMP.scala 132:61:[email protected]]
wire _T_565; // @[PMP.scala 132:8:[email protected]]
wire _T_566; // @[PMP.scala 163:29:[email protected]]
wire _T_619; // @[PMP.scala 181:40:[email protected]]
wire _T_621; // @[PMP.scala 182:40:[email protected]]
wire _T_623; // @[PMP.scala 183:40:[email protected]]
wire _T_625_cfg_x; // @[PMP.scala 184:8:[email protected]]
wire _T_625_cfg_w; // @[PMP.scala 184:8:[email protected]]
wire _T_625_cfg_r; // @[PMP.scala 184:8:[email protected]]
wire _T_626; // @[PMP.scala 45:20:[email protected]]
wire [31:0] _T_631; // @[PMP.scala 63:47:[email protected]]
wire [31:0] _T_632; // @[PMP.scala 63:54:[email protected]]
wire [31:0] _T_633; // @[PMP.scala 63:52:[email protected]]
wire _T_634; // @[PMP.scala 63:58:[email protected]]
wire _T_635; // @[PMP.scala 46:26:[email protected]]
wire _T_652; // @[PMP.scala 132:61:[email protected]]
wire _T_653; // @[PMP.scala 132:8:[email protected]]
wire _T_654; // @[PMP.scala 163:29:[email protected]]
wire _T_707; // @[PMP.scala 181:40:[email protected]]
wire _T_709; // @[PMP.scala 182:40:[email protected]]
wire _T_711; // @[PMP.scala 183:40:[email protected]]
assign _T_10 = io_pmp_7_cfg_a[1]; // @[PMP.scala 45:20:[email protected]]
assign _T_11 = {io_pmp_7_addr, 2'h0}; // @[PMP.scala 60:36:[email protected]]
assign _T_12 = ~ _T_11; // @[PMP.scala 60:29:[email protected]]
assign _T_13 = _T_12 | 32'h3; // @[PMP.scala 60:48:[email protected]]
assign _T_14 = ~ _T_13; // @[PMP.scala 60:27:[email protected]]
assign _T_15 = io_addr ^ _T_14; // @[PMP.scala 63:47:[email protected]]
assign _T_16 = ~ io_pmp_7_mask; // @[PMP.scala 63:54:[email protected]]
assign _T_17 = _T_15 & _T_16; // @[PMP.scala 63:52:[email protected]]
assign _T_18 = _T_17 == 32'h0; // @[PMP.scala 63:58:[email protected]]
assign _T_19 = io_pmp_7_cfg_a[0]; // @[PMP.scala 46:26:[email protected]]
assign _T_24 = {io_pmp_6_addr, 2'h0}; // @[PMP.scala 60:36:[email protected]]
assign _T_25 = ~ _T_24; // @[PMP.scala 60:29:[email protected]]
assign _T_26 = _T_25 | 32'h3; // @[PMP.scala 60:48:[email protected]]
assign _T_27 = ~ _T_26; // @[PMP.scala 60:27:[email protected]]
assign _T_28 = io_addr < _T_27; // @[PMP.scala 77:9:[email protected]]
assign _T_29 = _T_28 == 1'h0; // @[PMP.scala 88:5:[email protected]]
assign _T_34 = io_addr < _T_14; // @[PMP.scala 77:9:[email protected]]
assign _T_35 = _T_29 & _T_34; // @[PMP.scala 94:48:[email protected]]
assign _T_36 = _T_19 & _T_35; // @[PMP.scala 132:61:[email protected]]
assign _T_37 = _T_10 ? _T_18 : _T_36; // @[PMP.scala 132:8:[email protected]]
assign _T_38 = io_pmp_7_cfg_l == 1'h0; // @[PMP.scala 163:29:[email protected]]
assign _T_91 = io_pmp_7_cfg_r | _T_38; // @[PMP.scala 181:40:[email protected]]
assign _T_93 = io_pmp_7_cfg_w | _T_38; // @[PMP.scala 182:40:[email protected]]
assign _T_95 = io_pmp_7_cfg_x | _T_38; // @[PMP.scala 183:40:[email protected]]
assign _T_97_cfg_x = _T_37 ? _T_95 : 1'h1; // @[PMP.scala 184:8:[email protected]]
assign _T_97_cfg_w = _T_37 ? _T_93 : 1'h1; // @[PMP.scala 184:8:[email protected]]
assign _T_97_cfg_r = _T_37 ? _T_91 : 1'h1; // @[PMP.scala 184:8:[email protected]]
assign _T_98 = io_pmp_6_cfg_a[1]; // @[PMP.scala 45:20:[email protected]]
assign _T_103 = io_addr ^ _T_27; // @[PMP.scala 63:47:[email protected]]
assign _T_104 = ~ io_pmp_6_mask; // @[PMP.scala 63:54:[email protected]]
assign _T_105 = _T_103 & _T_104; // @[PMP.scala 63:52:[email protected]]
assign _T_106 = _T_105 == 32'h0; // @[PMP.scala 63:58:[email protected]]
assign _T_107 = io_pmp_6_cfg_a[0]; // @[PMP.scala 46:26:[email protected]]
assign _T_112 = {io_pmp_5_addr, 2'h0}; // @[PMP.scala 60:36:[email protected]]
assign _T_113 = ~ _T_112; // @[PMP.scala 60:29:[email protected]]
assign _T_114 = _T_113 | 32'h3; // @[PMP.scala 60:48:[email protected]]
assign _T_115 = ~ _T_114; // @[PMP.scala 60:27:[email protected]]
assign _T_116 = io_addr < _T_115; // @[PMP.scala 77:9:[email protected]]
assign _T_117 = _T_116 == 1'h0; // @[PMP.scala 88:5:[email protected]]
assign _T_123 = _T_117 & _T_28; // @[PMP.scala 94:48:[email protected]]
assign _T_124 = _T_107 & _T_123; // @[PMP.scala 132:61:[email protected]]
assign _T_125 = _T_98 ? _T_106 : _T_124; // @[PMP.scala 132:8:[email protected]]
assign _T_126 = io_pmp_6_cfg_l == 1'h0; // @[PMP.scala 163:29:[email protected]]
assign _T_179 = io_pmp_6_cfg_r | _T_126; // @[PMP.scala 181:40:[email protected]]
assign _T_181 = io_pmp_6_cfg_w | _T_126; // @[PMP.scala 182:40:[email protected]]
assign _T_183 = io_pmp_6_cfg_x | _T_126; // @[PMP.scala 183:40:[email protected]]
assign _T_185_cfg_x = _T_125 ? _T_183 : _T_97_cfg_x; // @[PMP.scala 184:8:[email protected]]
assign _T_185_cfg_w = _T_125 ? _T_181 : _T_97_cfg_w; // @[PMP.scala 184:8:[email protected]]
assign _T_185_cfg_r = _T_125 ? _T_179 : _T_97_cfg_r; // @[PMP.scala 184:8:[email protected]]
assign _T_186 = io_pmp_5_cfg_a[1]; // @[PMP.scala 45:20:[email protected]]
assign _T_191 = io_addr ^ _T_115; // @[PMP.scala 63:47:[email protected]]
assign _T_192 = ~ io_pmp_5_mask; // @[PMP.scala 63:54:[email protected]]
assign _T_193 = _T_191 & _T_192; // @[PMP.scala 63:52:[email protected]]
assign _T_194 = _T_193 == 32'h0; // @[PMP.scala 63:58:[email protected]]
assign _T_195 = io_pmp_5_cfg_a[0]; // @[PMP.scala 46:26:[email protected]]
assign _T_200 = {io_pmp_4_addr, 2'h0}; // @[PMP.scala 60:36:[email protected]]
assign _T_201 = ~ _T_200; // @[PMP.scala 60:29:[email protected]]
assign _T_202 = _T_201 | 32'h3; // @[PMP.scala 60:48:[email protected]]
assign _T_203 = ~ _T_202; // @[PMP.scala 60:27:[email protected]]
assign _T_204 = io_addr < _T_203; // @[PMP.scala 77:9:[email protected]]
assign _T_205 = _T_204 == 1'h0; // @[PMP.scala 88:5:[email protected]]
assign _T_211 = _T_205 & _T_116; // @[PMP.scala 94:48:[email protected]]
assign _T_212 = _T_195 & _T_211; // @[PMP.scala 132:61:[email protected]]
assign _T_213 = _T_186 ? _T_194 : _T_212; // @[PMP.scala 132:8:[email protected]]
assign _T_214 = io_pmp_5_cfg_l == 1'h0; // @[PMP.scala 163:29:[email protected]]
assign _T_267 = io_pmp_5_cfg_r | _T_214; // @[PMP.scala 181:40:[email protected]]
assign _T_269 = io_pmp_5_cfg_w | _T_214; // @[PMP.scala 182:40:[email protected]]
assign _T_271 = io_pmp_5_cfg_x | _T_214; // @[PMP.scala 183:40:[email protected]]
assign _T_273_cfg_x = _T_213 ? _T_271 : _T_185_cfg_x; // @[PMP.scala 184:8:[email protected]]
assign _T_273_cfg_w = _T_213 ? _T_269 : _T_185_cfg_w; // @[PMP.scala 184:8:[email protected]]
assign _T_273_cfg_r = _T_213 ? _T_267 : _T_185_cfg_r; // @[PMP.scala 184:8:[email protected]]
assign _T_274 = io_pmp_4_cfg_a[1]; // @[PMP.scala 45:20:[email protected]]
assign _T_279 = io_addr ^ _T_203; // @[PMP.scala 63:47:[email protected]]
assign _T_280 = ~ io_pmp_4_mask; // @[PMP.scala 63:54:[email protected]]
assign _T_281 = _T_279 & _T_280; // @[PMP.scala 63:52:[email protected]]
assign _T_282 = _T_281 == 32'h0; // @[PMP.scala 63:58:[email protected]]
assign _T_283 = io_pmp_4_cfg_a[0]; // @[PMP.scala 46:26:[email protected]]
assign _T_288 = {io_pmp_3_addr, 2'h0}; // @[PMP.scala 60:36:[email protected]]
assign _T_289 = ~ _T_288; // @[PMP.scala 60:29:[email protected]]
assign _T_290 = _T_289 | 32'h3; // @[PMP.scala 60:48:[email protected]]
assign _T_291 = ~ _T_290; // @[PMP.scala 60:27:[email protected]]
assign _T_292 = io_addr < _T_291; // @[PMP.scala 77:9:[email protected]]
assign _T_293 = _T_292 == 1'h0; // @[PMP.scala 88:5:[email protected]]
assign _T_299 = _T_293 & _T_204; // @[PMP.scala 94:48:[email protected]]
assign _T_300 = _T_283 & _T_299; // @[PMP.scala 132:61:[email protected]]
assign _T_301 = _T_274 ? _T_282 : _T_300; // @[PMP.scala 132:8:[email protected]]
assign _T_302 = io_pmp_4_cfg_l == 1'h0; // @[PMP.scala 163:29:[email protected]]
assign _T_355 = io_pmp_4_cfg_r | _T_302; // @[PMP.scala 181:40:[email protected]]
assign _T_357 = io_pmp_4_cfg_w | _T_302; // @[PMP.scala 182:40:[email protected]]
assign _T_359 = io_pmp_4_cfg_x | _T_302; // @[PMP.scala 183:40:[email protected]]
assign _T_361_cfg_x = _T_301 ? _T_359 : _T_273_cfg_x; // @[PMP.scala 184:8:[email protected]]
assign _T_361_cfg_w = _T_301 ? _T_357 : _T_273_cfg_w; // @[PMP.scala 184:8:[email protected]]
assign _T_361_cfg_r = _T_301 ? _T_355 : _T_273_cfg_r; // @[PMP.scala 184:8:[email protected]]
assign _T_362 = io_pmp_3_cfg_a[1]; // @[PMP.scala 45:20:[email protected]]
assign _T_367 = io_addr ^ _T_291; // @[PMP.scala 63:47:[email protected]]
assign _T_368 = ~ io_pmp_3_mask; // @[PMP.scala 63:54:[email protected]]
assign _T_369 = _T_367 & _T_368; // @[PMP.scala 63:52:[email protected]]
assign _T_370 = _T_369 == 32'h0; // @[PMP.scala 63:58:[email protected]]
assign _T_371 = io_pmp_3_cfg_a[0]; // @[PMP.scala 46:26:[email protected]]
assign _T_376 = {io_pmp_2_addr, 2'h0}; // @[PMP.scala 60:36:[email protected]]
assign _T_377 = ~ _T_376; // @[PMP.scala 60:29:[email protected]]
assign _T_378 = _T_377 | 32'h3; // @[PMP.scala 60:48:[email protected]]
assign _T_379 = ~ _T_378; // @[PMP.scala 60:27:[email protected]]
assign _T_380 = io_addr < _T_379; // @[PMP.scala 77:9:[email protected]]
assign _T_381 = _T_380 == 1'h0; // @[PMP.scala 88:5:[email protected]]
assign _T_387 = _T_381 & _T_292; // @[PMP.scala 94:48:[email protected]]
assign _T_388 = _T_371 & _T_387; // @[PMP.scala 132:61:[email protected]]
assign _T_389 = _T_362 ? _T_370 : _T_388; // @[PMP.scala 132:8:[email protected]]
assign _T_390 = io_pmp_3_cfg_l == 1'h0; // @[PMP.scala 163:29:[email protected]]
assign _T_443 = io_pmp_3_cfg_r | _T_390; // @[PMP.scala 181:40:[email protected]]
assign _T_445 = io_pmp_3_cfg_w | _T_390; // @[PMP.scala 182:40:[email protected]]
assign _T_447 = io_pmp_3_cfg_x | _T_390; // @[PMP.scala 183:40:[email protected]]
assign _T_449_cfg_x = _T_389 ? _T_447 : _T_361_cfg_x; // @[PMP.scala 184:8:[email protected]]
assign _T_449_cfg_w = _T_389 ? _T_445 : _T_361_cfg_w; // @[PMP.scala 184:8:[email protected]]
assign _T_449_cfg_r = _T_389 ? _T_443 : _T_361_cfg_r; // @[PMP.scala 184:8:[email protected]]
assign _T_450 = io_pmp_2_cfg_a[1]; // @[PMP.scala 45:20:[email protected]]
assign _T_455 = io_addr ^ _T_379; // @[PMP.scala 63:47:[email protected]]
assign _T_456 = ~ io_pmp_2_mask; // @[PMP.scala 63:54:[email protected]]
assign _T_457 = _T_455 & _T_456; // @[PMP.scala 63:52:[email protected]]
assign _T_458 = _T_457 == 32'h0; // @[PMP.scala 63:58:[email protected]]
assign _T_459 = io_pmp_2_cfg_a[0]; // @[PMP.scala 46:26:[email protected]]
assign _T_464 = {io_pmp_1_addr, 2'h0}; // @[PMP.scala 60:36:[email protected]]
assign _T_465 = ~ _T_464; // @[PMP.scala 60:29:[email protected]]
assign _T_466 = _T_465 | 32'h3; // @[PMP.scala 60:48:[email protected]]
assign _T_467 = ~ _T_466; // @[PMP.scala 60:27:[email protected]]
assign _T_468 = io_addr < _T_467; // @[PMP.scala 77:9:[email protected]]
assign _T_469 = _T_468 == 1'h0; // @[PMP.scala 88:5:[email protected]]
assign _T_475 = _T_469 & _T_380; // @[PMP.scala 94:48:[email protected]]
assign _T_476 = _T_459 & _T_475; // @[PMP.scala 132:61:[email protected]]
assign _T_477 = _T_450 ? _T_458 : _T_476; // @[PMP.scala 132:8:[email protected]]
assign _T_478 = io_pmp_2_cfg_l == 1'h0; // @[PMP.scala 163:29:[email protected]]
assign _T_531 = io_pmp_2_cfg_r | _T_478; // @[PMP.scala 181:40:[email protected]]
assign _T_533 = io_pmp_2_cfg_w | _T_478; // @[PMP.scala 182:40:[email protected]]
assign _T_535 = io_pmp_2_cfg_x | _T_478; // @[PMP.scala 183:40:[email protected]]
assign _T_537_cfg_x = _T_477 ? _T_535 : _T_449_cfg_x; // @[PMP.scala 184:8:[email protected]]
assign _T_537_cfg_w = _T_477 ? _T_533 : _T_449_cfg_w; // @[PMP.scala 184:8:[email protected]]
assign _T_537_cfg_r = _T_477 ? _T_531 : _T_449_cfg_r; // @[PMP.scala 184:8:[email protected]]
assign _T_538 = io_pmp_1_cfg_a[1]; // @[PMP.scala 45:20:[email protected]]
assign _T_543 = io_addr ^ _T_467; // @[PMP.scala 63:47:[email protected]]
assign _T_544 = ~ io_pmp_1_mask; // @[PMP.scala 63:54:[email protected]]
assign _T_545 = _T_543 & _T_544; // @[PMP.scala 63:52:[email protected]]
assign _T_546 = _T_545 == 32'h0; // @[PMP.scala 63:58:[email protected]]
assign _T_547 = io_pmp_1_cfg_a[0]; // @[PMP.scala 46:26:[email protected]]
assign _T_552 = {io_pmp_0_addr, 2'h0}; // @[PMP.scala 60:36:[email protected]]
assign _T_553 = ~ _T_552; // @[PMP.scala 60:29:[email protected]]
assign _T_554 = _T_553 | 32'h3; // @[PMP.scala 60:48:[email protected]]
assign _T_555 = ~ _T_554; // @[PMP.scala 60:27:[email protected]]
assign _T_556 = io_addr < _T_555; // @[PMP.scala 77:9:[email protected]]
assign _T_557 = _T_556 == 1'h0; // @[PMP.scala 88:5:[email protected]]
assign _T_563 = _T_557 & _T_468; // @[PMP.scala 94:48:[email protected]]
assign _T_564 = _T_547 & _T_563; // @[PMP.scala 132:61:[email protected]]
assign _T_565 = _T_538 ? _T_546 : _T_564; // @[PMP.scala 132:8:[email protected]]
assign _T_566 = io_pmp_1_cfg_l == 1'h0; // @[PMP.scala 163:29:[email protected]]
assign _T_619 = io_pmp_1_cfg_r | _T_566; // @[PMP.scala 181:40:[email protected]]
assign _T_621 = io_pmp_1_cfg_w | _T_566; // @[PMP.scala 182:40:[email protected]]
assign _T_623 = io_pmp_1_cfg_x | _T_566; // @[PMP.scala 183:40:[email protected]]
assign _T_625_cfg_x = _T_565 ? _T_623 : _T_537_cfg_x; // @[PMP.scala 184:8:[email protected]]
assign _T_625_cfg_w = _T_565 ? _T_621 : _T_537_cfg_w; // @[PMP.scala 184:8:[email protected]]
assign _T_625_cfg_r = _T_565 ? _T_619 : _T_537_cfg_r; // @[PMP.scala 184:8:[email protected]]
assign _T_626 = io_pmp_0_cfg_a[1]; // @[PMP.scala 45:20:[email protected]]
assign _T_631 = io_addr ^ _T_555; // @[PMP.scala 63:47:[email protected]]
assign _T_632 = ~ io_pmp_0_mask; // @[PMP.scala 63:54:[email protected]]
assign _T_633 = _T_631 & _T_632; // @[PMP.scala 63:52:[email protected]]
assign _T_634 = _T_633 == 32'h0; // @[PMP.scala 63:58:[email protected]]
assign _T_635 = io_pmp_0_cfg_a[0]; // @[PMP.scala 46:26:[email protected]]
assign _T_652 = _T_635 & _T_556; // @[PMP.scala 132:61:[email protected]]
assign _T_653 = _T_626 ? _T_634 : _T_652; // @[PMP.scala 132:8:[email protected]]
assign _T_654 = io_pmp_0_cfg_l == 1'h0; // @[PMP.scala 163:29:[email protected]]
assign _T_707 = io_pmp_0_cfg_r | _T_654; // @[PMP.scala 181:40:[email protected]]
assign _T_709 = io_pmp_0_cfg_w | _T_654; // @[PMP.scala 182:40:[email protected]]
assign _T_711 = io_pmp_0_cfg_x | _T_654; // @[PMP.scala 183:40:[email protected]]
assign io_r = _T_653 ? _T_707 : _T_625_cfg_r; // @[PMP.scala 187:8:[email protected]]
assign io_w = _T_653 ? _T_709 : _T_625_cfg_w; // @[PMP.scala 188:8:[email protected]]
assign io_x = _T_653 ? _T_711 : _T_625_cfg_x; // @[PMP.scala 189:8:[email protected]]
endmodule
|
module Queue_40( // @[:[email protected]]
input clock, // @[:[email protected]]
input reset, // @[:[email protected]]
output io_enq_ready, // @[:[email protected]]
input io_enq_valid, // @[:[email protected]]
input [2:0] io_enq_bits_opcode, // @[:[email protected]]
input [2:0] io_enq_bits_param, // @[:[email protected]]
input [2:0] io_enq_bits_size, // @[:[email protected]]
input [4:0] io_enq_bits_source, // @[:[email protected]]
input [31:0] io_enq_bits_address, // @[:[email protected]]
input [3:0] io_enq_bits_mask, // @[:[email protected]]
input [31:0] io_enq_bits_data, // @[:[email protected]]
input io_deq_ready, // @[:[email protected]]
output io_deq_valid, // @[:[email protected]]
output [2:0] io_deq_bits_opcode, // @[:[email protected]]
output [2:0] io_deq_bits_param, // @[:[email protected]]
output [2:0] io_deq_bits_size, // @[:[email protected]]
output [4:0] io_deq_bits_source, // @[:[email protected]]
output [31:0] io_deq_bits_address, // @[:[email protected]]
output [3:0] io_deq_bits_mask, // @[:[email protected]]
output [31:0] io_deq_bits_data // @[:[email protected]]
);
reg [2:0] _T_opcode [0:1]; // @[Decoupled.scala 215:24:[email protected]]
reg [31:0] _RAND_0;
wire [2:0] _T_opcode__T_18_data; // @[Decoupled.scala 215:24:[email protected]]
wire _T_opcode__T_18_addr; // @[Decoupled.scala 215:24:[email protected]]
wire [2:0] _T_opcode__T_10_data; // @[Decoupled.scala 215:24:[email protected]]
wire _T_opcode__T_10_addr; // @[Decoupled.scala 215:24:[email protected]]
wire _T_opcode__T_10_mask; // @[Decoupled.scala 215:24:[email protected]]
wire _T_opcode__T_10_en; // @[Decoupled.scala 215:24:[email protected]]
reg [2:0] _T_param [0:1]; // @[Decoupled.scala 215:24:[email protected]]
reg [31:0] _RAND_1;
wire [2:0] _T_param__T_18_data; // @[Decoupled.scala 215:24:[email protected]]
wire _T_param__T_18_addr; // @[Decoupled.scala 215:24:[email protected]]
wire [2:0] _T_param__T_10_data; // @[Decoupled.scala 215:24:[email protected]]
wire _T_param__T_10_addr; // @[Decoupled.scala 215:24:[email protected]]
wire _T_param__T_10_mask; // @[Decoupled.scala 215:24:[email protected]]
wire _T_param__T_10_en; // @[Decoupled.scala 215:24:[email protected]]
reg [2:0] _T_size [0:1]; // @[Decoupled.scala 215:24:[email protected]]
reg [31:0] _RAND_2;
wire [2:0] _T_size__T_18_data; // @[Decoupled.scala 215:24:[email protected]]
wire _T_size__T_18_addr; // @[Decoupled.scala 215:24:[email protected]]
wire [2:0] _T_size__T_10_data; // @[Decoupled.scala 215:24:[email protected]]
wire _T_size__T_10_addr; // @[Decoupled.scala 215:24:[email protected]]
wire _T_size__T_10_mask; // @[Decoupled.scala 215:24:[email protected]]
wire _T_size__T_10_en; // @[Decoupled.scala 215:24:[email protected]]
reg [4:0] _T_source [0:1]; // @[Decoupled.scala 215:24:[email protected]]
reg [31:0] _RAND_3;
wire [4:0] _T_source__T_18_data; // @[Decoupled.scala 215:24:[email protected]]
wire _T_source__T_18_addr; // @[Decoupled.scala 215:24:[email protected]]
wire [4:0] _T_source__T_10_data; // @[Decoupled.scala 215:24:[email protected]]
wire _T_source__T_10_addr; // @[Decoupled.scala 215:24:[email protected]]
wire _T_source__T_10_mask; // @[Decoupled.scala 215:24:[email protected]]
wire _T_source__T_10_en; // @[Decoupled.scala 215:24:[email protected]]
reg [31:0] _T_address [0:1]; // @[Decoupled.scala 215:24:[email protected]]
reg [31:0] _RAND_4;
wire [31:0] _T_address__T_18_data; // @[Decoupled.scala 215:24:[email protected]]
wire _T_address__T_18_addr; // @[Decoupled.scala 215:24:[email protected]]
wire [31:0] _T_address__T_10_data; // @[Decoupled.scala 215:24:[email protected]]
wire _T_address__T_10_addr; // @[Decoupled.scala 215:24:[email protected]]
wire _T_address__T_10_mask; // @[Decoupled.scala 215:24:[email protected]]
wire _T_address__T_10_en; // @[Decoupled.scala 215:24:[email protected]]
reg [3:0] _T_mask [0:1]; // @[Decoupled.scala 215:24:[email protected]]
reg [31:0] _RAND_5;
wire [3:0] _T_mask__T_18_data; // @[Decoupled.scala 215:24:[email protected]]
wire _T_mask__T_18_addr; // @[Decoupled.scala 215:24:[email protected]]
wire [3:0] _T_mask__T_10_data; // @[Decoupled.scala 215:24:[email protected]]
wire _T_mask__T_10_addr; // @[Decoupled.scala 215:24:[email protected]]
wire _T_mask__T_10_mask; // @[Decoupled.scala 215:24:[email protected]]
wire _T_mask__T_10_en; // @[Decoupled.scala 215:24:[email protected]]
reg [31:0] _T_data [0:1]; // @[Decoupled.scala 215:24:[email protected]]
reg [31:0] _RAND_6;
wire [31:0] _T_data__T_18_data; // @[Decoupled.scala 215:24:[email protected]]
wire _T_data__T_18_addr; // @[Decoupled.scala 215:24:[email protected]]
wire [31:0] _T_data__T_10_data; // @[Decoupled.scala 215:24:[email protected]]
wire _T_data__T_10_addr; // @[Decoupled.scala 215:24:[email protected]]
wire _T_data__T_10_mask; // @[Decoupled.scala 215:24:[email protected]]
wire _T_data__T_10_en; // @[Decoupled.scala 215:24:[email protected]]
reg value; // @[Counter.scala 26:33:[email protected]]
reg [31:0] _RAND_7;
reg value_1; // @[Counter.scala 26:33:[email protected]]
reg [31:0] _RAND_8;
reg _T_1; // @[Decoupled.scala 218:35:[email protected]]
reg [31:0] _RAND_9;
wire _T_2; // @[Decoupled.scala 220:41:[email protected]]
wire _T_3; // @[Decoupled.scala 221:36:[email protected]]
wire _T_4; // @[Decoupled.scala 221:33:[email protected]]
wire _T_5; // @[Decoupled.scala 222:32:[email protected]]
wire _T_6; // @[Decoupled.scala 37:37:[email protected]]
wire _T_8; // @[Decoupled.scala 37:37:[email protected]]
wire _T_12; // @[Counter.scala 35:22:[email protected]]
wire _T_14; // @[Counter.scala 35:22:[email protected]]
wire _T_15; // @[Decoupled.scala 233:16:[email protected]]
assign _T_opcode__T_18_addr = value_1;
assign _T_opcode__T_18_data = _T_opcode[_T_opcode__T_18_addr]; // @[Decoupled.scala 215:24:[email protected]]
assign _T_opcode__T_10_data = io_enq_bits_opcode;
assign _T_opcode__T_10_addr = value;
assign _T_opcode__T_10_mask = 1'h1;
assign _T_opcode__T_10_en = io_enq_ready & io_enq_valid;
assign _T_param__T_18_addr = value_1;
assign _T_param__T_18_data = _T_param[_T_param__T_18_addr]; // @[Decoupled.scala 215:24:[email protected]]
assign _T_param__T_10_data = io_enq_bits_param;
assign _T_param__T_10_addr = value;
assign _T_param__T_10_mask = 1'h1;
assign _T_param__T_10_en = io_enq_ready & io_enq_valid;
assign _T_size__T_18_addr = value_1;
assign _T_size__T_18_data = _T_size[_T_size__T_18_addr]; // @[Decoupled.scala 215:24:[email protected]]
assign _T_size__T_10_data = io_enq_bits_size;
assign _T_size__T_10_addr = value;
assign _T_size__T_10_mask = 1'h1;
assign _T_size__T_10_en = io_enq_ready & io_enq_valid;
assign _T_source__T_18_addr = value_1;
assign _T_source__T_18_data = _T_source[_T_source__T_18_addr]; // @[Decoupled.scala 215:24:[email protected]]
assign _T_source__T_10_data = io_enq_bits_source;
assign _T_source__T_10_addr = value;
assign _T_source__T_10_mask = 1'h1;
assign _T_source__T_10_en = io_enq_ready & io_enq_valid;
assign _T_address__T_18_addr = value_1;
assign _T_address__T_18_data = _T_address[_T_address__T_18_addr]; // @[Decoupled.scala 215:24:[email protected]]
assign _T_address__T_10_data = io_enq_bits_address;
assign _T_address__T_10_addr = value;
assign _T_address__T_10_mask = 1'h1;
assign _T_address__T_10_en = io_enq_ready & io_enq_valid;
assign _T_mask__T_18_addr = value_1;
assign _T_mask__T_18_data = _T_mask[_T_mask__T_18_addr]; // @[Decoupled.scala 215:24:[email protected]]
assign _T_mask__T_10_data = io_enq_bits_mask;
assign _T_mask__T_10_addr = value;
assign _T_mask__T_10_mask = 1'h1;
assign _T_mask__T_10_en = io_enq_ready & io_enq_valid;
assign _T_data__T_18_addr = value_1;
assign _T_data__T_18_data = _T_data[_T_data__T_18_addr]; // @[Decoupled.scala 215:24:[email protected]]
assign _T_data__T_10_data = io_enq_bits_data;
assign _T_data__T_10_addr = value;
assign _T_data__T_10_mask = 1'h1;
assign _T_data__T_10_en = io_enq_ready & io_enq_valid;
assign _T_2 = value == value_1; // @[Decoupled.scala 220:41:[email protected]]
assign _T_3 = _T_1 == 1'h0; // @[Decoupled.scala 221:36:[email protected]]
assign _T_4 = _T_2 & _T_3; // @[Decoupled.scala 221:33:[email protected]]
assign _T_5 = _T_2 & _T_1; // @[Decoupled.scala 222:32:[email protected]]
assign _T_6 = io_enq_ready & io_enq_valid; // @[Decoupled.scala 37:37:[email protected]]
assign _T_8 = io_deq_ready & io_deq_valid; // @[Decoupled.scala 37:37:[email protected]]
assign _T_12 = value + 1'h1; // @[Counter.scala 35:22:[email protected]]
assign _T_14 = value_1 + 1'h1; // @[Counter.scala 35:22:[email protected]]
assign _T_15 = _T_6 != _T_8; // @[Decoupled.scala 233:16:[email protected]]
assign io_enq_ready = _T_5 == 1'h0; // @[Decoupled.scala 238:16:[email protected]]
assign io_deq_valid = _T_4 == 1'h0; // @[Decoupled.scala 237:16:[email protected]]
assign io_deq_bits_opcode = _T_opcode__T_18_data; // @[Decoupled.scala 239:15:[email protected]]
assign io_deq_bits_param = _T_param__T_18_data; // @[Decoupled.scala 239:15:[email protected]]
assign io_deq_bits_size = _T_size__T_18_data; // @[Decoupled.scala 239:15:[email protected]]
assign io_deq_bits_source = _T_source__T_18_data; // @[Decoupled.scala 239:15:[email protected]]
assign io_deq_bits_address = _T_address__T_18_data; // @[Decoupled.scala 239:15:[email protected]]
assign io_deq_bits_mask = _T_mask__T_18_data; // @[Decoupled.scala 239:15:[email protected]]
assign io_deq_bits_data = _T_data__T_18_data; // @[Decoupled.scala 239:15:[email protected]]
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
integer initvar;
`endif
initial begin
`ifdef RANDOMIZE
`ifdef INIT_RANDOM
`INIT_RANDOM
`endif
`ifndef VERILATOR
`ifdef RANDOMIZE_DELAY
#`RANDOMIZE_DELAY begin end
`else
#0.002 begin end
`endif
`endif
_RAND_0 = {1{`RANDOM}};
`ifdef RANDOMIZE_MEM_INIT
for (initvar = 0; initvar < 2; initvar = initvar+1)
_T_opcode[initvar] = _RAND_0[2:0];
`endif // RANDOMIZE_MEM_INIT
_RAND_1 = {1{`RANDOM}};
`ifdef RANDOMIZE_MEM_INIT
for (initvar = 0; initvar < 2; initvar = initvar+1)
_T_param[initvar] = _RAND_1[2:0];
`endif // RANDOMIZE_MEM_INIT
_RAND_2 = {1{`RANDOM}};
`ifdef RANDOMIZE_MEM_INIT
for (initvar = 0; initvar < 2; initvar = initvar+1)
_T_size[initvar] = _RAND_2[2:0];
`endif // RANDOMIZE_MEM_INIT
_RAND_3 = {1{`RANDOM}};
`ifdef RANDOMIZE_MEM_INIT
for (initvar = 0; initvar < 2; initvar = initvar+1)
_T_source[initvar] = _RAND_3[4:0];
`endif // RANDOMIZE_MEM_INIT
_RAND_4 = {1{`RANDOM}};
`ifdef RANDOMIZE_MEM_INIT
for (initvar = 0; initvar < 2; initvar = initvar+1)
_T_address[initvar] = _RAND_4[31:0];
`endif // RANDOMIZE_MEM_INIT
_RAND_5 = {1{`RANDOM}};
`ifdef RANDOMIZE_MEM_INIT
for (initvar = 0; initvar < 2; initvar = initvar+1)
_T_mask[initvar] = _RAND_5[3:0];
`endif // RANDOMIZE_MEM_INIT
_RAND_6 = {1{`RANDOM}};
`ifdef RANDOMIZE_MEM_INIT
for (initvar = 0; initvar < 2; initvar = initvar+1)
_T_data[initvar] = _RAND_6[31:0];
`endif // RANDOMIZE_MEM_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_7 = {1{`RANDOM}};
value = _RAND_7[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_8 = {1{`RANDOM}};
value_1 = _RAND_8[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_9 = {1{`RANDOM}};
_T_1 = _RAND_9[0:0];
`endif // RANDOMIZE_REG_INIT
`endif // RANDOMIZE
end
always @(posedge clock) begin
if(_T_opcode__T_10_en & _T_opcode__T_10_mask) begin
_T_opcode[_T_opcode__T_10_addr] <= _T_opcode__T_10_data; // @[Decoupled.scala 215:24:[email protected]]
end
if(_T_param__T_10_en & _T_param__T_10_mask) begin
_T_param[_T_param__T_10_addr] <= _T_param__T_10_data; // @[Decoupled.scala 215:24:[email protected]]
end
if(_T_size__T_10_en & _T_size__T_10_mask) begin
_T_size[_T_size__T_10_addr] <= _T_size__T_10_data; // @[Decoupled.scala 215:24:[email protected]]
end
if(_T_source__T_10_en & _T_source__T_10_mask) begin
_T_source[_T_source__T_10_addr] <= _T_source__T_10_data; // @[Decoupled.scala 215:24:[email protected]]
end
if(_T_address__T_10_en & _T_address__T_10_mask) begin
_T_address[_T_address__T_10_addr] <= _T_address__T_10_data; // @[Decoupled.scala 215:24:[email protected]]
end
if(_T_mask__T_10_en & _T_mask__T_10_mask) begin
_T_mask[_T_mask__T_10_addr] <= _T_mask__T_10_data; // @[Decoupled.scala 215:24:[email protected]]
end
if(_T_data__T_10_en & _T_data__T_10_mask) begin
_T_data[_T_data__T_10_addr] <= _T_data__T_10_data; // @[Decoupled.scala 215:24:[email protected]]
end
if (reset) begin
value <= 1'h0;
end else begin
if (_T_6) begin
value <= _T_12;
end
end
if (reset) begin
value_1 <= 1'h0;
end else begin
if (_T_8) begin
value_1 <= _T_14;
end
end
if (reset) begin
_T_1 <= 1'h0;
end else begin
if (_T_15) begin
_T_1 <= _T_6;
end
end
end
endmodule
|
module Queue_39( // @[:[email protected]]
input clock, // @[:[email protected]]
input reset, // @[:[email protected]]
output io_enq_ready, // @[:[email protected]]
input io_enq_valid, // @[:[email protected]]
input [2:0] io_enq_bits_opcode, // @[:[email protected]]
input [1:0] io_enq_bits_param, // @[:[email protected]]
input [3:0] io_enq_bits_size, // @[:[email protected]]
input io_enq_bits_source, // @[:[email protected]]
input io_enq_bits_sink, // @[:[email protected]]
input io_enq_bits_denied, // @[:[email protected]]
input [31:0] io_enq_bits_data, // @[:[email protected]]
input io_enq_bits_corrupt, // @[:[email protected]]
input io_deq_ready, // @[:[email protected]]
output io_deq_valid, // @[:[email protected]]
output [2:0] io_deq_bits_opcode, // @[:[email protected]]
output [1:0] io_deq_bits_param, // @[:[email protected]]
output [3:0] io_deq_bits_size, // @[:[email protected]]
output io_deq_bits_source, // @[:[email protected]]
output io_deq_bits_sink, // @[:[email protected]]
output io_deq_bits_denied, // @[:[email protected]]
output [31:0] io_deq_bits_data, // @[:[email protected]]
output io_deq_bits_corrupt // @[:[email protected]]
);
reg [2:0] _T_opcode [0:1]; // @[Decoupled.scala 215:24:[email protected]]
reg [31:0] _RAND_0;
wire [2:0] _T_opcode__T_18_data; // @[Decoupled.scala 215:24:[email protected]]
wire _T_opcode__T_18_addr; // @[Decoupled.scala 215:24:[email protected]]
wire [2:0] _T_opcode__T_10_data; // @[Decoupled.scala 215:24:[email protected]]
wire _T_opcode__T_10_addr; // @[Decoupled.scala 215:24:[email protected]]
wire _T_opcode__T_10_mask; // @[Decoupled.scala 215:24:[email protected]]
wire _T_opcode__T_10_en; // @[Decoupled.scala 215:24:[email protected]]
reg [1:0] _T_param [0:1]; // @[Decoupled.scala 215:24:[email protected]]
reg [31:0] _RAND_1;
wire [1:0] _T_param__T_18_data; // @[Decoupled.scala 215:24:[email protected]]
wire _T_param__T_18_addr; // @[Decoupled.scala 215:24:[email protected]]
wire [1:0] _T_param__T_10_data; // @[Decoupled.scala 215:24:[email protected]]
wire _T_param__T_10_addr; // @[Decoupled.scala 215:24:[email protected]]
wire _T_param__T_10_mask; // @[Decoupled.scala 215:24:[email protected]]
wire _T_param__T_10_en; // @[Decoupled.scala 215:24:[email protected]]
reg [3:0] _T_size [0:1]; // @[Decoupled.scala 215:24:[email protected]]
reg [31:0] _RAND_2;
wire [3:0] _T_size__T_18_data; // @[Decoupled.scala 215:24:[email protected]]
wire _T_size__T_18_addr; // @[Decoupled.scala 215:24:[email protected]]
wire [3:0] _T_size__T_10_data; // @[Decoupled.scala 215:24:[email protected]]
wire _T_size__T_10_addr; // @[Decoupled.scala 215:24:[email protected]]
wire _T_size__T_10_mask; // @[Decoupled.scala 215:24:[email protected]]
wire _T_size__T_10_en; // @[Decoupled.scala 215:24:[email protected]]
reg _T_source [0:1]; // @[Decoupled.scala 215:24:[email protected]]
reg [31:0] _RAND_3;
wire _T_source__T_18_data; // @[Decoupled.scala 215:24:[email protected]]
wire _T_source__T_18_addr; // @[Decoupled.scala 215:24:[email protected]]
wire _T_source__T_10_data; // @[Decoupled.scala 215:24:[email protected]]
wire _T_source__T_10_addr; // @[Decoupled.scala 215:24:[email protected]]
wire _T_source__T_10_mask; // @[Decoupled.scala 215:24:[email protected]]
wire _T_source__T_10_en; // @[Decoupled.scala 215:24:[email protected]]
reg _T_sink [0:1]; // @[Decoupled.scala 215:24:[email protected]]
reg [31:0] _RAND_4;
wire _T_sink__T_18_data; // @[Decoupled.scala 215:24:[email protected]]
wire _T_sink__T_18_addr; // @[Decoupled.scala 215:24:[email protected]]
wire _T_sink__T_10_data; // @[Decoupled.scala 215:24:[email protected]]
wire _T_sink__T_10_addr; // @[Decoupled.scala 215:24:[email protected]]
wire _T_sink__T_10_mask; // @[Decoupled.scala 215:24:[email protected]]
wire _T_sink__T_10_en; // @[Decoupled.scala 215:24:[email protected]]
reg _T_denied [0:1]; // @[Decoupled.scala 215:24:[email protected]]
reg [31:0] _RAND_5;
wire _T_denied__T_18_data; // @[Decoupled.scala 215:24:[email protected]]
wire _T_denied__T_18_addr; // @[Decoupled.scala 215:24:[email protected]]
wire _T_denied__T_10_data; // @[Decoupled.scala 215:24:[email protected]]
wire _T_denied__T_10_addr; // @[Decoupled.scala 215:24:[email protected]]
wire _T_denied__T_10_mask; // @[Decoupled.scala 215:24:[email protected]]
wire _T_denied__T_10_en; // @[Decoupled.scala 215:24:[email protected]]
reg [31:0] _T_data [0:1]; // @[Decoupled.scala 215:24:[email protected]]
reg [31:0] _RAND_6;
wire [31:0] _T_data__T_18_data; // @[Decoupled.scala 215:24:[email protected]]
wire _T_data__T_18_addr; // @[Decoupled.scala 215:24:[email protected]]
wire [31:0] _T_data__T_10_data; // @[Decoupled.scala 215:24:[email protected]]
wire _T_data__T_10_addr; // @[Decoupled.scala 215:24:[email protected]]
wire _T_data__T_10_mask; // @[Decoupled.scala 215:24:[email protected]]
wire _T_data__T_10_en; // @[Decoupled.scala 215:24:[email protected]]
reg _T_corrupt [0:1]; // @[Decoupled.scala 215:24:[email protected]]
reg [31:0] _RAND_7;
wire _T_corrupt__T_18_data; // @[Decoupled.scala 215:24:[email protected]]
wire _T_corrupt__T_18_addr; // @[Decoupled.scala 215:24:[email protected]]
wire _T_corrupt__T_10_data; // @[Decoupled.scala 215:24:[email protected]]
wire _T_corrupt__T_10_addr; // @[Decoupled.scala 215:24:[email protected]]
wire _T_corrupt__T_10_mask; // @[Decoupled.scala 215:24:[email protected]]
wire _T_corrupt__T_10_en; // @[Decoupled.scala 215:24:[email protected]]
reg value; // @[Counter.scala 26:33:[email protected]]
reg [31:0] _RAND_8;
reg value_1; // @[Counter.scala 26:33:[email protected]]
reg [31:0] _RAND_9;
reg _T_1; // @[Decoupled.scala 218:35:[email protected]]
reg [31:0] _RAND_10;
wire _T_2; // @[Decoupled.scala 220:41:[email protected]]
wire _T_3; // @[Decoupled.scala 221:36:[email protected]]
wire _T_4; // @[Decoupled.scala 221:33:[email protected]]
wire _T_5; // @[Decoupled.scala 222:32:[email protected]]
wire _T_6; // @[Decoupled.scala 37:37:[email protected]]
wire _T_8; // @[Decoupled.scala 37:37:[email protected]]
wire _T_12; // @[Counter.scala 35:22:[email protected]]
wire _T_14; // @[Counter.scala 35:22:[email protected]]
wire _T_15; // @[Decoupled.scala 233:16:[email protected]]
assign _T_opcode__T_18_addr = value_1;
assign _T_opcode__T_18_data = _T_opcode[_T_opcode__T_18_addr]; // @[Decoupled.scala 215:24:[email protected]]
assign _T_opcode__T_10_data = io_enq_bits_opcode;
assign _T_opcode__T_10_addr = value;
assign _T_opcode__T_10_mask = 1'h1;
assign _T_opcode__T_10_en = io_enq_ready & io_enq_valid;
assign _T_param__T_18_addr = value_1;
assign _T_param__T_18_data = _T_param[_T_param__T_18_addr]; // @[Decoupled.scala 215:24:[email protected]]
assign _T_param__T_10_data = io_enq_bits_param;
assign _T_param__T_10_addr = value;
assign _T_param__T_10_mask = 1'h1;
assign _T_param__T_10_en = io_enq_ready & io_enq_valid;
assign _T_size__T_18_addr = value_1;
assign _T_size__T_18_data = _T_size[_T_size__T_18_addr]; // @[Decoupled.scala 215:24:[email protected]]
assign _T_size__T_10_data = io_enq_bits_size;
assign _T_size__T_10_addr = value;
assign _T_size__T_10_mask = 1'h1;
assign _T_size__T_10_en = io_enq_ready & io_enq_valid;
assign _T_source__T_18_addr = value_1;
assign _T_source__T_18_data = _T_source[_T_source__T_18_addr]; // @[Decoupled.scala 215:24:[email protected]]
assign _T_source__T_10_data = io_enq_bits_source;
assign _T_source__T_10_addr = value;
assign _T_source__T_10_mask = 1'h1;
assign _T_source__T_10_en = io_enq_ready & io_enq_valid;
assign _T_sink__T_18_addr = value_1;
assign _T_sink__T_18_data = _T_sink[_T_sink__T_18_addr]; // @[Decoupled.scala 215:24:[email protected]]
assign _T_sink__T_10_data = io_enq_bits_sink;
assign _T_sink__T_10_addr = value;
assign _T_sink__T_10_mask = 1'h1;
assign _T_sink__T_10_en = io_enq_ready & io_enq_valid;
assign _T_denied__T_18_addr = value_1;
assign _T_denied__T_18_data = _T_denied[_T_denied__T_18_addr]; // @[Decoupled.scala 215:24:[email protected]]
assign _T_denied__T_10_data = io_enq_bits_denied;
assign _T_denied__T_10_addr = value;
assign _T_denied__T_10_mask = 1'h1;
assign _T_denied__T_10_en = io_enq_ready & io_enq_valid;
assign _T_data__T_18_addr = value_1;
assign _T_data__T_18_data = _T_data[_T_data__T_18_addr]; // @[Decoupled.scala 215:24:[email protected]]
assign _T_data__T_10_data = io_enq_bits_data;
assign _T_data__T_10_addr = value;
assign _T_data__T_10_mask = 1'h1;
assign _T_data__T_10_en = io_enq_ready & io_enq_valid;
assign _T_corrupt__T_18_addr = value_1;
assign _T_corrupt__T_18_data = _T_corrupt[_T_corrupt__T_18_addr]; // @[Decoupled.scala 215:24:[email protected]]
assign _T_corrupt__T_10_data = io_enq_bits_corrupt;
assign _T_corrupt__T_10_addr = value;
assign _T_corrupt__T_10_mask = 1'h1;
assign _T_corrupt__T_10_en = io_enq_ready & io_enq_valid;
assign _T_2 = value == value_1; // @[Decoupled.scala 220:41:[email protected]]
assign _T_3 = _T_1 == 1'h0; // @[Decoupled.scala 221:36:[email protected]]
assign _T_4 = _T_2 & _T_3; // @[Decoupled.scala 221:33:[email protected]]
assign _T_5 = _T_2 & _T_1; // @[Decoupled.scala 222:32:[email protected]]
assign _T_6 = io_enq_ready & io_enq_valid; // @[Decoupled.scala 37:37:[email protected]]
assign _T_8 = io_deq_ready & io_deq_valid; // @[Decoupled.scala 37:37:[email protected]]
assign _T_12 = value + 1'h1; // @[Counter.scala 35:22:[email protected]]
assign _T_14 = value_1 + 1'h1; // @[Counter.scala 35:22:[email protected]]
assign _T_15 = _T_6 != _T_8; // @[Decoupled.scala 233:16:[email protected]]
assign io_enq_ready = _T_5 == 1'h0; // @[Decoupled.scala 238:16:[email protected]]
assign io_deq_valid = _T_4 == 1'h0; // @[Decoupled.scala 237:16:[email protected]]
assign io_deq_bits_opcode = _T_opcode__T_18_data; // @[Decoupled.scala 239:15:[email protected]]
assign io_deq_bits_param = _T_param__T_18_data; // @[Decoupled.scala 239:15:[email protected]]
assign io_deq_bits_size = _T_size__T_18_data; // @[Decoupled.scala 239:15:[email protected]]
assign io_deq_bits_source = _T_source__T_18_data; // @[Decoupled.scala 239:15:[email protected]]
assign io_deq_bits_sink = _T_sink__T_18_data; // @[Decoupled.scala 239:15:[email protected]]
assign io_deq_bits_denied = _T_denied__T_18_data; // @[Decoupled.scala 239:15:[email protected]]
assign io_deq_bits_data = _T_data__T_18_data; // @[Decoupled.scala 239:15:[email protected]]
assign io_deq_bits_corrupt = _T_corrupt__T_18_data; // @[Decoupled.scala 239:15:[email protected]]
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
integer initvar;
`endif
initial begin
`ifdef RANDOMIZE
`ifdef INIT_RANDOM
`INIT_RANDOM
`endif
`ifndef VERILATOR
`ifdef RANDOMIZE_DELAY
#`RANDOMIZE_DELAY begin end
`else
#0.002 begin end
`endif
`endif
_RAND_0 = {1{`RANDOM}};
`ifdef RANDOMIZE_MEM_INIT
for (initvar = 0; initvar < 2; initvar = initvar+1)
_T_opcode[initvar] = _RAND_0[2:0];
`endif // RANDOMIZE_MEM_INIT
_RAND_1 = {1{`RANDOM}};
`ifdef RANDOMIZE_MEM_INIT
for (initvar = 0; initvar < 2; initvar = initvar+1)
_T_param[initvar] = _RAND_1[1:0];
`endif // RANDOMIZE_MEM_INIT
_RAND_2 = {1{`RANDOM}};
`ifdef RANDOMIZE_MEM_INIT
for (initvar = 0; initvar < 2; initvar = initvar+1)
_T_size[initvar] = _RAND_2[3:0];
`endif // RANDOMIZE_MEM_INIT
_RAND_3 = {1{`RANDOM}};
`ifdef RANDOMIZE_MEM_INIT
for (initvar = 0; initvar < 2; initvar = initvar+1)
_T_source[initvar] = _RAND_3[0:0];
`endif // RANDOMIZE_MEM_INIT
_RAND_4 = {1{`RANDOM}};
`ifdef RANDOMIZE_MEM_INIT
for (initvar = 0; initvar < 2; initvar = initvar+1)
_T_sink[initvar] = _RAND_4[0:0];
`endif // RANDOMIZE_MEM_INIT
_RAND_5 = {1{`RANDOM}};
`ifdef RANDOMIZE_MEM_INIT
for (initvar = 0; initvar < 2; initvar = initvar+1)
_T_denied[initvar] = _RAND_5[0:0];
`endif // RANDOMIZE_MEM_INIT
_RAND_6 = {1{`RANDOM}};
`ifdef RANDOMIZE_MEM_INIT
for (initvar = 0; initvar < 2; initvar = initvar+1)
_T_data[initvar] = _RAND_6[31:0];
`endif // RANDOMIZE_MEM_INIT
_RAND_7 = {1{`RANDOM}};
`ifdef RANDOMIZE_MEM_INIT
for (initvar = 0; initvar < 2; initvar = initvar+1)
_T_corrupt[initvar] = _RAND_7[0:0];
`endif // RANDOMIZE_MEM_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_8 = {1{`RANDOM}};
value = _RAND_8[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_9 = {1{`RANDOM}};
value_1 = _RAND_9[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_10 = {1{`RANDOM}};
_T_1 = _RAND_10[0:0];
`endif // RANDOMIZE_REG_INIT
`endif // RANDOMIZE
end
always @(posedge clock) begin
if(_T_opcode__T_10_en & _T_opcode__T_10_mask) begin
_T_opcode[_T_opcode__T_10_addr] <= _T_opcode__T_10_data; // @[Decoupled.scala 215:24:[email protected]]
end
if(_T_param__T_10_en & _T_param__T_10_mask) begin
_T_param[_T_param__T_10_addr] <= _T_param__T_10_data; // @[Decoupled.scala 215:24:[email protected]]
end
if(_T_size__T_10_en & _T_size__T_10_mask) begin
_T_size[_T_size__T_10_addr] <= _T_size__T_10_data; // @[Decoupled.scala 215:24:[email protected]]
end
if(_T_source__T_10_en & _T_source__T_10_mask) begin
_T_source[_T_source__T_10_addr] <= _T_source__T_10_data; // @[Decoupled.scala 215:24:[email protected]]
end
if(_T_sink__T_10_en & _T_sink__T_10_mask) begin
_T_sink[_T_sink__T_10_addr] <= _T_sink__T_10_data; // @[Decoupled.scala 215:24:[email protected]]
end
if(_T_denied__T_10_en & _T_denied__T_10_mask) begin
_T_denied[_T_denied__T_10_addr] <= _T_denied__T_10_data; // @[Decoupled.scala 215:24:[email protected]]
end
if(_T_data__T_10_en & _T_data__T_10_mask) begin
_T_data[_T_data__T_10_addr] <= _T_data__T_10_data; // @[Decoupled.scala 215:24:[email protected]]
end
if(_T_corrupt__T_10_en & _T_corrupt__T_10_mask) begin
_T_corrupt[_T_corrupt__T_10_addr] <= _T_corrupt__T_10_data; // @[Decoupled.scala 215:24:[email protected]]
end
if (reset) begin
value <= 1'h0;
end else begin
if (_T_6) begin
value <= _T_12;
end
end
if (reset) begin
value_1 <= 1'h0;
end else begin
if (_T_8) begin
value_1 <= _T_14;
end
end
if (reset) begin
_T_1 <= 1'h0;
end else begin
if (_T_15) begin
_T_1 <= _T_6;
end
end
end
endmodule
|
module AMOALU( // @[:[email protected]]
input [4:0] io_cmd, // @[:[email protected]]
input [31:0] io_lhs, // @[:[email protected]]
input [31:0] io_rhs, // @[:[email protected]]
output [31:0] io_out_unmasked // @[:[email protected]]
);
wire _T; // @[AMOALU.scala 64:20:[email protected]]
wire _T_1; // @[AMOALU.scala 64:43:[email protected]]
wire max; // @[AMOALU.scala 64:33:[email protected]]
wire _T_2; // @[AMOALU.scala 65:20:[email protected]]
wire _T_3; // @[AMOALU.scala 65:43:[email protected]]
wire min; // @[AMOALU.scala 65:33:[email protected]]
wire add; // @[AMOALU.scala 66:20:[email protected]]
wire _T_4; // @[AMOALU.scala 67:26:[email protected]]
wire _T_5; // @[AMOALU.scala 67:48:[email protected]]
wire logic_and; // @[AMOALU.scala 67:38:[email protected]]
wire _T_6; // @[AMOALU.scala 68:26:[email protected]]
wire logic_xor; // @[AMOALU.scala 68:39:[email protected]]
wire [31:0] adder_out; // @[AMOALU.scala 73:21:[email protected]]
wire [4:0] _T_14; // @[AMOALU.scala 86:17:[email protected]]
wire _T_16; // @[AMOALU.scala 86:25:[email protected]]
wire _T_17; // @[AMOALU.scala 88:12:[email protected]]
wire _T_18; // @[AMOALU.scala 88:23:[email protected]]
wire _T_19; // @[AMOALU.scala 88:18:[email protected]]
wire _T_22; // @[AMOALU.scala 79:35:[email protected]]
wire _T_25; // @[AMOALU.scala 88:58:[email protected]]
wire less; // @[AMOALU.scala 88:10:[email protected]]
wire _T_26; // @[AMOALU.scala 94:23:[email protected]]
wire [31:0] minmax; // @[AMOALU.scala 94:19:[email protected]]
wire [31:0] _T_27; // @[AMOALU.scala 96:27:[email protected]]
wire [31:0] _T_28; // @[AMOALU.scala 96:8:[email protected]]
wire [31:0] _T_29; // @[AMOALU.scala 97:27:[email protected]]
wire [31:0] _T_30; // @[AMOALU.scala 97:8:[email protected]]
wire [31:0] logic_; // @[AMOALU.scala 96:42:[email protected]]
wire _T_31; // @[AMOALU.scala 100:19:[email protected]]
wire [31:0] _T_32; // @[AMOALU.scala 100:8:[email protected]]
assign _T = io_cmd == 5'hd; // @[AMOALU.scala 64:20:[email protected]]
assign _T_1 = io_cmd == 5'hf; // @[AMOALU.scala 64:43:[email protected]]
assign max = _T | _T_1; // @[AMOALU.scala 64:33:[email protected]]
assign _T_2 = io_cmd == 5'hc; // @[AMOALU.scala 65:20:[email protected]]
assign _T_3 = io_cmd == 5'he; // @[AMOALU.scala 65:43:[email protected]]
assign min = _T_2 | _T_3; // @[AMOALU.scala 65:33:[email protected]]
assign add = io_cmd == 5'h8; // @[AMOALU.scala 66:20:[email protected]]
assign _T_4 = io_cmd == 5'ha; // @[AMOALU.scala 67:26:[email protected]]
assign _T_5 = io_cmd == 5'hb; // @[AMOALU.scala 67:48:[email protected]]
assign logic_and = _T_4 | _T_5; // @[AMOALU.scala 67:38:[email protected]]
assign _T_6 = io_cmd == 5'h9; // @[AMOALU.scala 68:26:[email protected]]
assign logic_xor = _T_6 | _T_4; // @[AMOALU.scala 68:39:[email protected]]
assign adder_out = io_lhs + io_rhs; // @[AMOALU.scala 73:21:[email protected]]
assign _T_14 = io_cmd & 5'h2; // @[AMOALU.scala 86:17:[email protected]]
assign _T_16 = _T_14 == 5'h0; // @[AMOALU.scala 86:25:[email protected]]
assign _T_17 = io_lhs[31]; // @[AMOALU.scala 88:12:[email protected]]
assign _T_18 = io_rhs[31]; // @[AMOALU.scala 88:23:[email protected]]
assign _T_19 = _T_17 == _T_18; // @[AMOALU.scala 88:18:[email protected]]
assign _T_22 = io_lhs < io_rhs; // @[AMOALU.scala 79:35:[email protected]]
assign _T_25 = _T_16 ? _T_17 : _T_18; // @[AMOALU.scala 88:58:[email protected]]
assign less = _T_19 ? _T_22 : _T_25; // @[AMOALU.scala 88:10:[email protected]]
assign _T_26 = less ? min : max; // @[AMOALU.scala 94:23:[email protected]]
assign minmax = _T_26 ? io_lhs : io_rhs; // @[AMOALU.scala 94:19:[email protected]]
assign _T_27 = io_lhs & io_rhs; // @[AMOALU.scala 96:27:[email protected]]
assign _T_28 = logic_and ? _T_27 : 32'h0; // @[AMOALU.scala 96:8:[email protected]]
assign _T_29 = io_lhs ^ io_rhs; // @[AMOALU.scala 97:27:[email protected]]
assign _T_30 = logic_xor ? _T_29 : 32'h0; // @[AMOALU.scala 97:8:[email protected]]
assign logic_ = _T_28 | _T_30; // @[AMOALU.scala 96:42:[email protected]]
assign _T_31 = logic_and | logic_xor; // @[AMOALU.scala 100:19:[email protected]]
assign _T_32 = _T_31 ? logic_ : minmax; // @[AMOALU.scala 100:8:[email protected]]
assign io_out_unmasked = add ? adder_out : _T_32; // @[AMOALU.scala 105:19:[email protected]]
endmodule
|
module MulDiv( // @[:[email protected]]
input clock, // @[:[email protected]]
input reset, // @[:[email protected]]
output io_req_ready, // @[:[email protected]]
input io_req_valid, // @[:[email protected]]
input [3:0] io_req_bits_fn, // @[:[email protected]]
input [31:0] io_req_bits_in1, // @[:[email protected]]
input [31:0] io_req_bits_in2, // @[:[email protected]]
input [4:0] io_req_bits_tag, // @[:[email protected]]
input io_kill, // @[:[email protected]]
input io_resp_ready, // @[:[email protected]]
output io_resp_valid, // @[:[email protected]]
output [31:0] io_resp_bits_data, // @[:[email protected]]
output [4:0] io_resp_bits_tag // @[:[email protected]]
);
reg [2:0] state; // @[Multiplier.scala 51:18:[email protected]]
reg [31:0] _RAND_0;
reg [4:0] req_tag; // @[Multiplier.scala 53:16:[email protected]]
reg [31:0] _RAND_1;
reg [5:0] count; // @[Multiplier.scala 54:18:[email protected]]
reg [31:0] _RAND_2;
reg neg_out; // @[Multiplier.scala 57:20:[email protected]]
reg [31:0] _RAND_3;
reg isHi; // @[Multiplier.scala 58:17:[email protected]]
reg [31:0] _RAND_4;
reg resHi; // @[Multiplier.scala 59:18:[email protected]]
reg [31:0] _RAND_5;
reg [32:0] divisor; // @[Multiplier.scala 60:20:[email protected]]
reg [63:0] _RAND_6;
reg [65:0] remainder; // @[Multiplier.scala 61:22:[email protected]]
reg [95:0] _RAND_7;
wire [3:0] _T; // @[Decode.scala 14:65:[email protected]]
wire cmdMul; // @[Decode.scala 14:121:[email protected]]
wire [3:0] _T_3; // @[Decode.scala 14:65:[email protected]]
wire _T_4; // @[Decode.scala 14:121:[email protected]]
wire [3:0] _T_5; // @[Decode.scala 14:65:[email protected]]
wire _T_6; // @[Decode.scala 14:121:[email protected]]
wire cmdHi; // @[Decode.scala 15:30:[email protected]]
wire [3:0] _T_9; // @[Decode.scala 14:65:[email protected]]
wire _T_10; // @[Decode.scala 14:121:[email protected]]
wire [3:0] _T_11; // @[Decode.scala 14:65:[email protected]]
wire _T_12; // @[Decode.scala 14:121:[email protected]]
wire lhsSigned; // @[Decode.scala 15:30:[email protected]]
wire _T_16; // @[Decode.scala 14:121:[email protected]]
wire rhsSigned; // @[Decode.scala 15:30:[email protected]]
wire _T_22; // @[Multiplier.scala 81:48:[email protected]]
wire lhs_sign; // @[Multiplier.scala 81:23:[email protected]]
wire [15:0] _T_26; // @[Multiplier.scala 82:43:[email protected]]
wire [15:0] _T_28; // @[Multiplier.scala 83:15:[email protected]]
wire [31:0] lhs_in; // @[Cat.scala 30:58:[email protected]]
wire _T_32; // @[Multiplier.scala 81:48:[email protected]]
wire rhs_sign; // @[Multiplier.scala 81:23:[email protected]]
wire [15:0] _T_36; // @[Multiplier.scala 82:43:[email protected]]
wire [15:0] _T_38; // @[Multiplier.scala 83:15:[email protected]]
wire [32:0] _T_39; // @[Multiplier.scala 88:29:[email protected]]
wire [32:0] subtractor; // @[Multiplier.scala 88:37:[email protected]]
wire [31:0] _T_41; // @[Multiplier.scala 89:36:[email protected]]
wire [31:0] _T_42; // @[Multiplier.scala 89:57:[email protected]]
wire [31:0] result; // @[Multiplier.scala 89:19:[email protected]]
wire [31:0] negated_remainder; // @[Multiplier.scala 90:27:[email protected]]
wire _T_44; // @[Multiplier.scala 92:39:[email protected]]
wire _T_45; // @[Multiplier.scala 93:20:[email protected]]
wire _T_46; // @[Multiplier.scala 96:18:[email protected]]
wire _T_47; // @[Multiplier.scala 101:39:[email protected]]
wire _T_48; // @[Multiplier.scala 106:39:[email protected]]
wire [32:0] _T_49; // @[Multiplier.scala 107:31:[email protected]]
wire [64:0] _T_51; // @[Cat.scala 30:58:[email protected]]
wire _T_52; // @[Multiplier.scala 108:31:[email protected]]
wire [31:0] _T_53; // @[Multiplier.scala 109:24:[email protected]]
wire [32:0] _T_54; // @[Multiplier.scala 110:23:[email protected]]
wire [32:0] _T_55; // @[Multiplier.scala 110:37:[email protected]]
wire [32:0] _T_56; // @[Multiplier.scala 111:26:[email protected]]
wire [7:0] _T_57; // @[Multiplier.scala 112:38:[email protected]]
wire [8:0] _T_58; // @[Cat.scala 30:58:[email protected]]
wire [8:0] _T_59; // @[Multiplier.scala 112:60:[email protected]]
wire [32:0] _GEN_35; // @[Multiplier.scala 112:67:[email protected]]
wire [41:0] _T_60; // @[Multiplier.scala 112:67:[email protected]]
wire [41:0] _GEN_36; // @[Multiplier.scala 112:76:[email protected]]
wire [41:0] _T_62; // @[Multiplier.scala 112:76:[email protected]]
wire [41:0] _T_63; // @[Multiplier.scala 112:76:[email protected]]
wire [23:0] _T_64; // @[Multiplier.scala 113:38:[email protected]]
wire [41:0] _T_65; // @[Cat.scala 30:58:[email protected]]
wire [65:0] _T_66; // @[Cat.scala 30:58:[email protected]]
wire _T_67; // @[Multiplier.scala 114:32:[email protected]]
wire _T_68; // @[Multiplier.scala 114:57:[email protected]]
wire _T_77; // @[Multiplier.scala 118:7:[email protected]]
wire [32:0] _T_88; // @[Multiplier.scala 120:37:[email protected]]
wire [31:0] _T_90; // @[Multiplier.scala 120:82:[email protected]]
wire [64:0] _T_91; // @[Cat.scala 30:58:[email protected]]
wire [32:0] _T_92; // @[Multiplier.scala 121:34:[email protected]]
wire [31:0] _T_93; // @[Multiplier.scala 121:67:[email protected]]
wire [65:0] _T_95; // @[Cat.scala 30:58:[email protected]]
wire [5:0] _T_97; // @[Multiplier.scala 123:20:[email protected]]
wire _T_98; // @[Multiplier.scala 124:25:[email protected]]
wire _T_100; // @[Multiplier.scala 129:39:[email protected]]
wire _T_101; // @[Multiplier.scala 133:28:[email protected]]
wire [31:0] _T_102; // @[Multiplier.scala 134:24:[email protected]]
wire [31:0] _T_103; // @[Multiplier.scala 134:45:[email protected]]
wire [31:0] _T_104; // @[Multiplier.scala 134:14:[email protected]]
wire _T_106; // @[Multiplier.scala 134:67:[email protected]]
wire [64:0] _T_108; // @[Cat.scala 30:58:[email protected]]
wire _T_109; // @[Multiplier.scala 138:17:[email protected]]
wire _T_113; // @[Multiplier.scala 146:24:[email protected]]
wire _T_116; // @[Multiplier.scala 146:30:[email protected]]
wire _T_118; // @[Multiplier.scala 159:18:[email protected]]
wire _T_119; // @[Decoupled.scala 37:37:[email protected]]
wire _T_120; // @[Multiplier.scala 161:24:[email protected]]
wire _T_121; // @[Decoupled.scala 37:37:[email protected]]
wire _T_122; // @[Multiplier.scala 165:46:[email protected]]
wire _T_129; // @[Multiplier.scala 169:46:[email protected]]
wire [32:0] _T_131; // @[Cat.scala 30:58:[email protected]]
wire [15:0] _T_140; // @[Multiplier.scala 176:69:[email protected]]
wire [15:0] loOut; // @[Multiplier.scala 176:86:[email protected]]
wire _T_149; // @[Multiplier.scala 180:27:[email protected]]
wire _T_150; // @[Multiplier.scala 180:51:[email protected]]
assign _T = io_req_bits_fn & 4'h4; // @[Decode.scala 14:65:[email protected]]
assign cmdMul = _T == 4'h0; // @[Decode.scala 14:121:[email protected]]
assign _T_3 = io_req_bits_fn & 4'h5; // @[Decode.scala 14:65:[email protected]]
assign _T_4 = _T_3 == 4'h1; // @[Decode.scala 14:121:[email protected]]
assign _T_5 = io_req_bits_fn & 4'h2; // @[Decode.scala 14:65:[email protected]]
assign _T_6 = _T_5 == 4'h2; // @[Decode.scala 14:121:[email protected]]
assign cmdHi = _T_4 | _T_6; // @[Decode.scala 15:30:[email protected]]
assign _T_9 = io_req_bits_fn & 4'h6; // @[Decode.scala 14:65:[email protected]]
assign _T_10 = _T_9 == 4'h0; // @[Decode.scala 14:121:[email protected]]
assign _T_11 = io_req_bits_fn & 4'h1; // @[Decode.scala 14:65:[email protected]]
assign _T_12 = _T_11 == 4'h0; // @[Decode.scala 14:121:[email protected]]
assign lhsSigned = _T_10 | _T_12; // @[Decode.scala 15:30:[email protected]]
assign _T_16 = _T_3 == 4'h4; // @[Decode.scala 14:121:[email protected]]
assign rhsSigned = _T_10 | _T_16; // @[Decode.scala 15:30:[email protected]]
assign _T_22 = io_req_bits_in1[31]; // @[Multiplier.scala 81:48:[email protected]]
assign lhs_sign = lhsSigned & _T_22; // @[Multiplier.scala 81:23:[email protected]]
assign _T_26 = io_req_bits_in1[31:16]; // @[Multiplier.scala 82:43:[email protected]]
assign _T_28 = io_req_bits_in1[15:0]; // @[Multiplier.scala 83:15:[email protected]]
assign lhs_in = {_T_26,_T_28}; // @[Cat.scala 30:58:[email protected]]
assign _T_32 = io_req_bits_in2[31]; // @[Multiplier.scala 81:48:[email protected]]
assign rhs_sign = rhsSigned & _T_32; // @[Multiplier.scala 81:23:[email protected]]
assign _T_36 = io_req_bits_in2[31:16]; // @[Multiplier.scala 82:43:[email protected]]
assign _T_38 = io_req_bits_in2[15:0]; // @[Multiplier.scala 83:15:[email protected]]
assign _T_39 = remainder[64:32]; // @[Multiplier.scala 88:29:[email protected]]
assign subtractor = _T_39 - divisor; // @[Multiplier.scala 88:37:[email protected]]
assign _T_41 = remainder[64:33]; // @[Multiplier.scala 89:36:[email protected]]
assign _T_42 = remainder[31:0]; // @[Multiplier.scala 89:57:[email protected]]
assign result = resHi ? _T_41 : _T_42; // @[Multiplier.scala 89:19:[email protected]]
assign negated_remainder = 32'h0 - result; // @[Multiplier.scala 90:27:[email protected]]
assign _T_44 = state == 3'h1; // @[Multiplier.scala 92:39:[email protected]]
assign _T_45 = remainder[31]; // @[Multiplier.scala 93:20:[email protected]]
assign _T_46 = divisor[31]; // @[Multiplier.scala 96:18:[email protected]]
assign _T_47 = state == 3'h5; // @[Multiplier.scala 101:39:[email protected]]
assign _T_48 = state == 3'h2; // @[Multiplier.scala 106:39:[email protected]]
assign _T_49 = remainder[65:33]; // @[Multiplier.scala 107:31:[email protected]]
assign _T_51 = {_T_49,_T_42}; // @[Cat.scala 30:58:[email protected]]
assign _T_52 = remainder[32]; // @[Multiplier.scala 108:31:[email protected]]
assign _T_53 = _T_51[31:0]; // @[Multiplier.scala 109:24:[email protected]]
assign _T_54 = _T_51[64:32]; // @[Multiplier.scala 110:23:[email protected]]
assign _T_55 = $signed(_T_54); // @[Multiplier.scala 110:37:[email protected]]
assign _T_56 = $signed(divisor); // @[Multiplier.scala 111:26:[email protected]]
assign _T_57 = _T_53[7:0]; // @[Multiplier.scala 112:38:[email protected]]
assign _T_58 = {_T_52,_T_57}; // @[Cat.scala 30:58:[email protected]]
assign _T_59 = $signed(_T_58); // @[Multiplier.scala 112:60:[email protected]]
assign _GEN_35 = {{24{_T_59[8]}},_T_59}; // @[Multiplier.scala 112:67:[email protected]]
assign _T_60 = $signed(_GEN_35) * $signed(_T_56); // @[Multiplier.scala 112:67:[email protected]]
assign _GEN_36 = {{9{_T_55[32]}},_T_55}; // @[Multiplier.scala 112:76:[email protected]]
assign _T_62 = $signed(_T_60) + $signed(_GEN_36); // @[Multiplier.scala 112:76:[email protected]]
assign _T_63 = $signed(_T_62); // @[Multiplier.scala 112:76:[email protected]]
assign _T_64 = _T_53[31:8]; // @[Multiplier.scala 113:38:[email protected]]
assign _T_65 = $unsigned(_T_63); // @[Cat.scala 30:58:[email protected]]
assign _T_66 = {_T_65,_T_64}; // @[Cat.scala 30:58:[email protected]]
assign _T_67 = count == 6'h2; // @[Multiplier.scala 114:32:[email protected]]
assign _T_68 = _T_67 & neg_out; // @[Multiplier.scala 114:57:[email protected]]
assign _T_77 = isHi == 1'h0; // @[Multiplier.scala 118:7:[email protected]]
assign _T_88 = _T_66[64:32]; // @[Multiplier.scala 120:37:[email protected]]
assign _T_90 = _T_66[31:0]; // @[Multiplier.scala 120:82:[email protected]]
assign _T_91 = {_T_88,_T_90}; // @[Cat.scala 30:58:[email protected]]
assign _T_92 = _T_91[64:32]; // @[Multiplier.scala 121:34:[email protected]]
assign _T_93 = _T_91[31:0]; // @[Multiplier.scala 121:67:[email protected]]
assign _T_95 = {_T_92,_T_68,_T_93}; // @[Cat.scala 30:58:[email protected]]
assign _T_97 = count + 6'h1; // @[Multiplier.scala 123:20:[email protected]]
assign _T_98 = count == 6'h3; // @[Multiplier.scala 124:25:[email protected]]
assign _T_100 = state == 3'h3; // @[Multiplier.scala 129:39:[email protected]]
assign _T_101 = subtractor[32]; // @[Multiplier.scala 133:28:[email protected]]
assign _T_102 = remainder[63:32]; // @[Multiplier.scala 134:24:[email protected]]
assign _T_103 = subtractor[31:0]; // @[Multiplier.scala 134:45:[email protected]]
assign _T_104 = _T_101 ? _T_102 : _T_103; // @[Multiplier.scala 134:14:[email protected]]
assign _T_106 = _T_101 == 1'h0; // @[Multiplier.scala 134:67:[email protected]]
assign _T_108 = {_T_104,_T_42,_T_106}; // @[Cat.scala 30:58:[email protected]]
assign _T_109 = count == 6'h20; // @[Multiplier.scala 138:17:[email protected]]
assign _T_113 = count == 6'h0; // @[Multiplier.scala 146:24:[email protected]]
assign _T_116 = _T_113 & _T_106; // @[Multiplier.scala 146:30:[email protected]]
assign _T_118 = _T_116 & _T_77; // @[Multiplier.scala 159:18:[email protected]]
assign _T_119 = io_resp_ready & io_resp_valid; // @[Decoupled.scala 37:37:[email protected]]
assign _T_120 = _T_119 | io_kill; // @[Multiplier.scala 161:24:[email protected]]
assign _T_121 = io_req_ready & io_req_valid; // @[Decoupled.scala 37:37:[email protected]]
assign _T_122 = lhs_sign | rhs_sign; // @[Multiplier.scala 165:46:[email protected]]
assign _T_129 = lhs_sign != rhs_sign; // @[Multiplier.scala 169:46:[email protected]]
assign _T_131 = {rhs_sign,_T_36,_T_38}; // @[Cat.scala 30:58:[email protected]]
assign _T_140 = result[31:16]; // @[Multiplier.scala 176:69:[email protected]]
assign loOut = result[15:0]; // @[Multiplier.scala 176:86:[email protected]]
assign _T_149 = state == 3'h6; // @[Multiplier.scala 180:27:[email protected]]
assign _T_150 = state == 3'h7; // @[Multiplier.scala 180:51:[email protected]]
assign io_req_ready = state == 3'h0; // @[Multiplier.scala 181:16:[email protected]]
assign io_resp_valid = _T_149 | _T_150; // @[Multiplier.scala 180:17:[email protected]]
assign io_resp_bits_data = {_T_140,loOut}; // @[Multiplier.scala 179:21:[email protected]]
assign io_resp_bits_tag = req_tag; // @[Multiplier.scala 178:16:[email protected]]
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
integer initvar;
`endif
initial begin
`ifdef RANDOMIZE
`ifdef INIT_RANDOM
`INIT_RANDOM
`endif
`ifndef VERILATOR
`ifdef RANDOMIZE_DELAY
#`RANDOMIZE_DELAY begin end
`else
#0.002 begin end
`endif
`endif
`ifdef RANDOMIZE_REG_INIT
_RAND_0 = {1{`RANDOM}};
state = _RAND_0[2:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_1 = {1{`RANDOM}};
req_tag = _RAND_1[4:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_2 = {1{`RANDOM}};
count = _RAND_2[5:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_3 = {1{`RANDOM}};
neg_out = _RAND_3[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_4 = {1{`RANDOM}};
isHi = _RAND_4[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_5 = {1{`RANDOM}};
resHi = _RAND_5[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_6 = {2{`RANDOM}};
divisor = _RAND_6[32:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_7 = {3{`RANDOM}};
remainder = _RAND_7[65:0];
`endif // RANDOMIZE_REG_INIT
`endif // RANDOMIZE
end
always @(posedge clock) begin
if (reset) begin
state <= 3'h0;
end else begin
if (_T_121) begin
if (cmdMul) begin
state <= 3'h2;
end else begin
if (_T_122) begin
state <= 3'h1;
end else begin
state <= 3'h3;
end
end
end else begin
if (_T_120) begin
state <= 3'h0;
end else begin
if (_T_100) begin
if (_T_109) begin
if (neg_out) begin
state <= 3'h5;
end else begin
state <= 3'h7;
end
end else begin
if (_T_48) begin
if (_T_98) begin
state <= 3'h6;
end else begin
if (_T_47) begin
state <= 3'h7;
end else begin
if (_T_44) begin
state <= 3'h3;
end
end
end
end else begin
if (_T_47) begin
state <= 3'h7;
end else begin
if (_T_44) begin
state <= 3'h3;
end
end
end
end
end else begin
if (_T_48) begin
if (_T_98) begin
state <= 3'h6;
end else begin
if (_T_47) begin
state <= 3'h7;
end else begin
if (_T_44) begin
state <= 3'h3;
end
end
end
end else begin
if (_T_47) begin
state <= 3'h7;
end else begin
if (_T_44) begin
state <= 3'h3;
end
end
end
end
end
end
end
if (_T_121) begin
req_tag <= io_req_bits_tag;
end
if (_T_121) begin
count <= 6'h0;
end else begin
if (_T_100) begin
count <= _T_97;
end else begin
if (_T_48) begin
count <= _T_97;
end
end
end
if (_T_121) begin
if (cmdHi) begin
neg_out <= lhs_sign;
end else begin
neg_out <= _T_129;
end
end else begin
if (_T_100) begin
if (_T_118) begin
neg_out <= 1'h0;
end
end
end
if (_T_121) begin
isHi <= cmdHi;
end
if (_T_121) begin
resHi <= 1'h0;
end else begin
if (_T_100) begin
if (_T_109) begin
resHi <= isHi;
end else begin
if (_T_48) begin
if (_T_98) begin
resHi <= isHi;
end else begin
if (_T_47) begin
resHi <= 1'h0;
end
end
end else begin
if (_T_47) begin
resHi <= 1'h0;
end
end
end
end else begin
if (_T_48) begin
if (_T_98) begin
resHi <= isHi;
end else begin
if (_T_47) begin
resHi <= 1'h0;
end
end
end else begin
if (_T_47) begin
resHi <= 1'h0;
end
end
end
end
if (_T_121) begin
divisor <= _T_131;
end else begin
if (_T_44) begin
if (_T_46) begin
divisor <= subtractor;
end
end
end
if (_T_121) begin
remainder <= {{34'd0}, lhs_in};
end else begin
if (_T_100) begin
remainder <= {{1'd0}, _T_108};
end else begin
if (_T_48) begin
remainder <= _T_95;
end else begin
if (_T_47) begin
remainder <= {{34'd0}, negated_remainder};
end else begin
if (_T_44) begin
if (_T_45) begin
remainder <= {{34'd0}, negated_remainder};
end
end
end
end
end
end
end
endmodule
|
module Queue_41( // @[:[email protected]]
input clock, // @[:[email protected]]
input reset, // @[:[email protected]]
output io_enq_ready, // @[:[email protected]]
input io_enq_valid, // @[:[email protected]]
input [2:0] io_enq_bits_opcode, // @[:[email protected]]
input [2:0] io_enq_bits_size, // @[:[email protected]]
input [4:0] io_enq_bits_source, // @[:[email protected]]
input [31:0] io_enq_bits_data, // @[:[email protected]]
input io_deq_ready, // @[:[email protected]]
output io_deq_valid, // @[:[email protected]]
output [2:0] io_deq_bits_opcode, // @[:[email protected]]
output [1:0] io_deq_bits_param, // @[:[email protected]]
output [2:0] io_deq_bits_size, // @[:[email protected]]
output [4:0] io_deq_bits_source, // @[:[email protected]]
output io_deq_bits_sink, // @[:[email protected]]
output io_deq_bits_denied, // @[:[email protected]]
output [31:0] io_deq_bits_data, // @[:[email protected]]
output io_deq_bits_corrupt // @[:[email protected]]
);
reg [2:0] _T_opcode [0:1]; // @[Decoupled.scala 215:24:[email protected]]
reg [31:0] _RAND_0;
wire [2:0] _T_opcode__T_18_data; // @[Decoupled.scala 215:24:[email protected]]
wire _T_opcode__T_18_addr; // @[Decoupled.scala 215:24:[email protected]]
wire [2:0] _T_opcode__T_10_data; // @[Decoupled.scala 215:24:[email protected]]
wire _T_opcode__T_10_addr; // @[Decoupled.scala 215:24:[email protected]]
wire _T_opcode__T_10_mask; // @[Decoupled.scala 215:24:[email protected]]
wire _T_opcode__T_10_en; // @[Decoupled.scala 215:24:[email protected]]
reg [1:0] _T_param [0:1]; // @[Decoupled.scala 215:24:[email protected]]
reg [31:0] _RAND_1;
wire [1:0] _T_param__T_18_data; // @[Decoupled.scala 215:24:[email protected]]
wire _T_param__T_18_addr; // @[Decoupled.scala 215:24:[email protected]]
wire [1:0] _T_param__T_10_data; // @[Decoupled.scala 215:24:[email protected]]
wire _T_param__T_10_addr; // @[Decoupled.scala 215:24:[email protected]]
wire _T_param__T_10_mask; // @[Decoupled.scala 215:24:[email protected]]
wire _T_param__T_10_en; // @[Decoupled.scala 215:24:[email protected]]
reg [2:0] _T_size [0:1]; // @[Decoupled.scala 215:24:[email protected]]
reg [31:0] _RAND_2;
wire [2:0] _T_size__T_18_data; // @[Decoupled.scala 215:24:[email protected]]
wire _T_size__T_18_addr; // @[Decoupled.scala 215:24:[email protected]]
wire [2:0] _T_size__T_10_data; // @[Decoupled.scala 215:24:[email protected]]
wire _T_size__T_10_addr; // @[Decoupled.scala 215:24:[email protected]]
wire _T_size__T_10_mask; // @[Decoupled.scala 215:24:[email protected]]
wire _T_size__T_10_en; // @[Decoupled.scala 215:24:[email protected]]
reg [4:0] _T_source [0:1]; // @[Decoupled.scala 215:24:[email protected]]
reg [31:0] _RAND_3;
wire [4:0] _T_source__T_18_data; // @[Decoupled.scala 215:24:[email protected]]
wire _T_source__T_18_addr; // @[Decoupled.scala 215:24:[email protected]]
wire [4:0] _T_source__T_10_data; // @[Decoupled.scala 215:24:[email protected]]
wire _T_source__T_10_addr; // @[Decoupled.scala 215:24:[email protected]]
wire _T_source__T_10_mask; // @[Decoupled.scala 215:24:[email protected]]
wire _T_source__T_10_en; // @[Decoupled.scala 215:24:[email protected]]
reg _T_sink [0:1]; // @[Decoupled.scala 215:24:[email protected]]
reg [31:0] _RAND_4;
wire _T_sink__T_18_data; // @[Decoupled.scala 215:24:[email protected]]
wire _T_sink__T_18_addr; // @[Decoupled.scala 215:24:[email protected]]
wire _T_sink__T_10_data; // @[Decoupled.scala 215:24:[email protected]]
wire _T_sink__T_10_addr; // @[Decoupled.scala 215:24:[email protected]]
wire _T_sink__T_10_mask; // @[Decoupled.scala 215:24:[email protected]]
wire _T_sink__T_10_en; // @[Decoupled.scala 215:24:[email protected]]
reg _T_denied [0:1]; // @[Decoupled.scala 215:24:[email protected]]
reg [31:0] _RAND_5;
wire _T_denied__T_18_data; // @[Decoupled.scala 215:24:[email protected]]
wire _T_denied__T_18_addr; // @[Decoupled.scala 215:24:[email protected]]
wire _T_denied__T_10_data; // @[Decoupled.scala 215:24:[email protected]]
wire _T_denied__T_10_addr; // @[Decoupled.scala 215:24:[email protected]]
wire _T_denied__T_10_mask; // @[Decoupled.scala 215:24:[email protected]]
wire _T_denied__T_10_en; // @[Decoupled.scala 215:24:[email protected]]
reg [31:0] _T_data [0:1]; // @[Decoupled.scala 215:24:[email protected]]
reg [31:0] _RAND_6;
wire [31:0] _T_data__T_18_data; // @[Decoupled.scala 215:24:[email protected]]
wire _T_data__T_18_addr; // @[Decoupled.scala 215:24:[email protected]]
wire [31:0] _T_data__T_10_data; // @[Decoupled.scala 215:24:[email protected]]
wire _T_data__T_10_addr; // @[Decoupled.scala 215:24:[email protected]]
wire _T_data__T_10_mask; // @[Decoupled.scala 215:24:[email protected]]
wire _T_data__T_10_en; // @[Decoupled.scala 215:24:[email protected]]
reg _T_corrupt [0:1]; // @[Decoupled.scala 215:24:[email protected]]
reg [31:0] _RAND_7;
wire _T_corrupt__T_18_data; // @[Decoupled.scala 215:24:[email protected]]
wire _T_corrupt__T_18_addr; // @[Decoupled.scala 215:24:[email protected]]
wire _T_corrupt__T_10_data; // @[Decoupled.scala 215:24:[email protected]]
wire _T_corrupt__T_10_addr; // @[Decoupled.scala 215:24:[email protected]]
wire _T_corrupt__T_10_mask; // @[Decoupled.scala 215:24:[email protected]]
wire _T_corrupt__T_10_en; // @[Decoupled.scala 215:24:[email protected]]
reg value; // @[Counter.scala 26:33:[email protected]]
reg [31:0] _RAND_8;
reg value_1; // @[Counter.scala 26:33:[email protected]]
reg [31:0] _RAND_9;
reg _T_1; // @[Decoupled.scala 218:35:[email protected]]
reg [31:0] _RAND_10;
wire _T_2; // @[Decoupled.scala 220:41:[email protected]]
wire _T_3; // @[Decoupled.scala 221:36:[email protected]]
wire _T_4; // @[Decoupled.scala 221:33:[email protected]]
wire _T_5; // @[Decoupled.scala 222:32:[email protected]]
wire _T_6; // @[Decoupled.scala 37:37:[email protected]]
wire _T_8; // @[Decoupled.scala 37:37:[email protected]]
wire _T_12; // @[Counter.scala 35:22:[email protected]]
wire _T_14; // @[Counter.scala 35:22:[email protected]]
wire _T_15; // @[Decoupled.scala 233:16:[email protected]]
assign _T_opcode__T_18_addr = value_1;
assign _T_opcode__T_18_data = _T_opcode[_T_opcode__T_18_addr]; // @[Decoupled.scala 215:24:[email protected]]
assign _T_opcode__T_10_data = io_enq_bits_opcode;
assign _T_opcode__T_10_addr = value;
assign _T_opcode__T_10_mask = 1'h1;
assign _T_opcode__T_10_en = io_enq_ready & io_enq_valid;
assign _T_param__T_18_addr = value_1;
assign _T_param__T_18_data = _T_param[_T_param__T_18_addr]; // @[Decoupled.scala 215:24:[email protected]]
assign _T_param__T_10_data = 2'h0;
assign _T_param__T_10_addr = value;
assign _T_param__T_10_mask = 1'h1;
assign _T_param__T_10_en = io_enq_ready & io_enq_valid;
assign _T_size__T_18_addr = value_1;
assign _T_size__T_18_data = _T_size[_T_size__T_18_addr]; // @[Decoupled.scala 215:24:[email protected]]
assign _T_size__T_10_data = io_enq_bits_size;
assign _T_size__T_10_addr = value;
assign _T_size__T_10_mask = 1'h1;
assign _T_size__T_10_en = io_enq_ready & io_enq_valid;
assign _T_source__T_18_addr = value_1;
assign _T_source__T_18_data = _T_source[_T_source__T_18_addr]; // @[Decoupled.scala 215:24:[email protected]]
assign _T_source__T_10_data = io_enq_bits_source;
assign _T_source__T_10_addr = value;
assign _T_source__T_10_mask = 1'h1;
assign _T_source__T_10_en = io_enq_ready & io_enq_valid;
assign _T_sink__T_18_addr = value_1;
assign _T_sink__T_18_data = _T_sink[_T_sink__T_18_addr]; // @[Decoupled.scala 215:24:[email protected]]
assign _T_sink__T_10_data = 1'h0;
assign _T_sink__T_10_addr = value;
assign _T_sink__T_10_mask = 1'h1;
assign _T_sink__T_10_en = io_enq_ready & io_enq_valid;
assign _T_denied__T_18_addr = value_1;
assign _T_denied__T_18_data = _T_denied[_T_denied__T_18_addr]; // @[Decoupled.scala 215:24:[email protected]]
assign _T_denied__T_10_data = 1'h0;
assign _T_denied__T_10_addr = value;
assign _T_denied__T_10_mask = 1'h1;
assign _T_denied__T_10_en = io_enq_ready & io_enq_valid;
assign _T_data__T_18_addr = value_1;
assign _T_data__T_18_data = _T_data[_T_data__T_18_addr]; // @[Decoupled.scala 215:24:[email protected]]
assign _T_data__T_10_data = io_enq_bits_data;
assign _T_data__T_10_addr = value;
assign _T_data__T_10_mask = 1'h1;
assign _T_data__T_10_en = io_enq_ready & io_enq_valid;
assign _T_corrupt__T_18_addr = value_1;
assign _T_corrupt__T_18_data = _T_corrupt[_T_corrupt__T_18_addr]; // @[Decoupled.scala 215:24:[email protected]]
assign _T_corrupt__T_10_data = 1'h0;
assign _T_corrupt__T_10_addr = value;
assign _T_corrupt__T_10_mask = 1'h1;
assign _T_corrupt__T_10_en = io_enq_ready & io_enq_valid;
assign _T_2 = value == value_1; // @[Decoupled.scala 220:41:[email protected]]
assign _T_3 = _T_1 == 1'h0; // @[Decoupled.scala 221:36:[email protected]]
assign _T_4 = _T_2 & _T_3; // @[Decoupled.scala 221:33:[email protected]]
assign _T_5 = _T_2 & _T_1; // @[Decoupled.scala 222:32:[email protected]]
assign _T_6 = io_enq_ready & io_enq_valid; // @[Decoupled.scala 37:37:[email protected]]
assign _T_8 = io_deq_ready & io_deq_valid; // @[Decoupled.scala 37:37:[email protected]]
assign _T_12 = value + 1'h1; // @[Counter.scala 35:22:[email protected]]
assign _T_14 = value_1 + 1'h1; // @[Counter.scala 35:22:[email protected]]
assign _T_15 = _T_6 != _T_8; // @[Decoupled.scala 233:16:[email protected]]
assign io_enq_ready = _T_5 == 1'h0; // @[Decoupled.scala 238:16:[email protected]]
assign io_deq_valid = _T_4 == 1'h0; // @[Decoupled.scala 237:16:[email protected]]
assign io_deq_bits_opcode = _T_opcode__T_18_data; // @[Decoupled.scala 239:15:[email protected]]
assign io_deq_bits_param = _T_param__T_18_data; // @[Decoupled.scala 239:15:[email protected]]
assign io_deq_bits_size = _T_size__T_18_data; // @[Decoupled.scala 239:15:[email protected]]
assign io_deq_bits_source = _T_source__T_18_data; // @[Decoupled.scala 239:15:[email protected]]
assign io_deq_bits_sink = _T_sink__T_18_data; // @[Decoupled.scala 239:15:[email protected]]
assign io_deq_bits_denied = _T_denied__T_18_data; // @[Decoupled.scala 239:15:[email protected]]
assign io_deq_bits_data = _T_data__T_18_data; // @[Decoupled.scala 239:15:[email protected]]
assign io_deq_bits_corrupt = _T_corrupt__T_18_data; // @[Decoupled.scala 239:15:[email protected]]
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
integer initvar;
`endif
initial begin
`ifdef RANDOMIZE
`ifdef INIT_RANDOM
`INIT_RANDOM
`endif
`ifndef VERILATOR
`ifdef RANDOMIZE_DELAY
#`RANDOMIZE_DELAY begin end
`else
#0.002 begin end
`endif
`endif
_RAND_0 = {1{`RANDOM}};
`ifdef RANDOMIZE_MEM_INIT
for (initvar = 0; initvar < 2; initvar = initvar+1)
_T_opcode[initvar] = _RAND_0[2:0];
`endif // RANDOMIZE_MEM_INIT
_RAND_1 = {1{`RANDOM}};
`ifdef RANDOMIZE_MEM_INIT
for (initvar = 0; initvar < 2; initvar = initvar+1)
_T_param[initvar] = _RAND_1[1:0];
`endif // RANDOMIZE_MEM_INIT
_RAND_2 = {1{`RANDOM}};
`ifdef RANDOMIZE_MEM_INIT
for (initvar = 0; initvar < 2; initvar = initvar+1)
_T_size[initvar] = _RAND_2[2:0];
`endif // RANDOMIZE_MEM_INIT
_RAND_3 = {1{`RANDOM}};
`ifdef RANDOMIZE_MEM_INIT
for (initvar = 0; initvar < 2; initvar = initvar+1)
_T_source[initvar] = _RAND_3[4:0];
`endif // RANDOMIZE_MEM_INIT
_RAND_4 = {1{`RANDOM}};
`ifdef RANDOMIZE_MEM_INIT
for (initvar = 0; initvar < 2; initvar = initvar+1)
_T_sink[initvar] = _RAND_4[0:0];
`endif // RANDOMIZE_MEM_INIT
_RAND_5 = {1{`RANDOM}};
`ifdef RANDOMIZE_MEM_INIT
for (initvar = 0; initvar < 2; initvar = initvar+1)
_T_denied[initvar] = _RAND_5[0:0];
`endif // RANDOMIZE_MEM_INIT
_RAND_6 = {1{`RANDOM}};
`ifdef RANDOMIZE_MEM_INIT
for (initvar = 0; initvar < 2; initvar = initvar+1)
_T_data[initvar] = _RAND_6[31:0];
`endif // RANDOMIZE_MEM_INIT
_RAND_7 = {1{`RANDOM}};
`ifdef RANDOMIZE_MEM_INIT
for (initvar = 0; initvar < 2; initvar = initvar+1)
_T_corrupt[initvar] = _RAND_7[0:0];
`endif // RANDOMIZE_MEM_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_8 = {1{`RANDOM}};
value = _RAND_8[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_9 = {1{`RANDOM}};
value_1 = _RAND_9[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_10 = {1{`RANDOM}};
_T_1 = _RAND_10[0:0];
`endif // RANDOMIZE_REG_INIT
`endif // RANDOMIZE
end
always @(posedge clock) begin
if(_T_opcode__T_10_en & _T_opcode__T_10_mask) begin
_T_opcode[_T_opcode__T_10_addr] <= _T_opcode__T_10_data; // @[Decoupled.scala 215:24:[email protected]]
end
if(_T_param__T_10_en & _T_param__T_10_mask) begin
_T_param[_T_param__T_10_addr] <= _T_param__T_10_data; // @[Decoupled.scala 215:24:[email protected]]
end
if(_T_size__T_10_en & _T_size__T_10_mask) begin
_T_size[_T_size__T_10_addr] <= _T_size__T_10_data; // @[Decoupled.scala 215:24:[email protected]]
end
if(_T_source__T_10_en & _T_source__T_10_mask) begin
_T_source[_T_source__T_10_addr] <= _T_source__T_10_data; // @[Decoupled.scala 215:24:[email protected]]
end
if(_T_sink__T_10_en & _T_sink__T_10_mask) begin
_T_sink[_T_sink__T_10_addr] <= _T_sink__T_10_data; // @[Decoupled.scala 215:24:[email protected]]
end
if(_T_denied__T_10_en & _T_denied__T_10_mask) begin
_T_denied[_T_denied__T_10_addr] <= _T_denied__T_10_data; // @[Decoupled.scala 215:24:[email protected]]
end
if(_T_data__T_10_en & _T_data__T_10_mask) begin
_T_data[_T_data__T_10_addr] <= _T_data__T_10_data; // @[Decoupled.scala 215:24:[email protected]]
end
if(_T_corrupt__T_10_en & _T_corrupt__T_10_mask) begin
_T_corrupt[_T_corrupt__T_10_addr] <= _T_corrupt__T_10_data; // @[Decoupled.scala 215:24:[email protected]]
end
if (reset) begin
value <= 1'h0;
end else begin
if (_T_6) begin
value <= _T_12;
end
end
if (reset) begin
value_1 <= 1'h0;
end else begin
if (_T_8) begin
value_1 <= _T_14;
end
end
if (reset) begin
_T_1 <= 1'h0;
end else begin
if (_T_15) begin
_T_1 <= _T_6;
end
end
end
endmodule
|
module ScratchpadSlavePort( // @[:[email protected]]
input clock, // @[:[email protected]]
input reset, // @[:[email protected]]
output auto_in_a_ready, // @[:[email protected]]
input auto_in_a_valid, // @[:[email protected]]
input [2:0] auto_in_a_bits_opcode, // @[:[email protected]]
input [2:0] auto_in_a_bits_param, // @[:[email protected]]
input [1:0] auto_in_a_bits_size, // @[:[email protected]]
input [10:0] auto_in_a_bits_source, // @[:[email protected]]
input [31:0] auto_in_a_bits_address, // @[:[email protected]]
input [3:0] auto_in_a_bits_mask, // @[:[email protected]]
input [31:0] auto_in_a_bits_data, // @[:[email protected]]
input auto_in_d_ready, // @[:[email protected]]
output auto_in_d_valid, // @[:[email protected]]
output [2:0] auto_in_d_bits_opcode, // @[:[email protected]]
output [1:0] auto_in_d_bits_size, // @[:[email protected]]
output [10:0] auto_in_d_bits_source, // @[:[email protected]]
output [31:0] auto_in_d_bits_data, // @[:[email protected]]
input io_dmem_req_ready, // @[:[email protected]]
output io_dmem_req_valid, // @[:[email protected]]
output [31:0] io_dmem_req_bits_addr, // @[:[email protected]]
output [4:0] io_dmem_req_bits_cmd, // @[:[email protected]]
output [1:0] io_dmem_req_bits_size, // @[:[email protected]]
output io_dmem_s1_kill, // @[:[email protected]]
output [31:0] io_dmem_s1_data_data, // @[:[email protected]]
output [3:0] io_dmem_s1_data_mask, // @[:[email protected]]
input io_dmem_s2_nack, // @[:[email protected]]
input io_dmem_resp_valid, // @[:[email protected]]
input [31:0] io_dmem_resp_bits_data_raw // @[:[email protected]]
);
reg [2:0] state; // @[ScratchpadSlavePort.scala 46:20:[email protected]]
reg [31:0] _RAND_0;
wire _T; // @[ScratchpadSlavePort.scala 48:17:[email protected]]
wire _T_51; // @[ScratchpadSlavePort.scala 98:50:[email protected]]
wire tl_in_d_valid; // @[ScratchpadSlavePort.scala 98:41:[email protected]]
wire _T_1; // @[Decoupled.scala 37:37:[email protected]]
wire _T_6; // @[ScratchpadSlavePort.scala 86:23:[email protected]]
wire _T_7; // @[ScratchpadSlavePort.scala 86:44:[email protected]]
wire _T_8; // @[ScratchpadSlavePort.scala 86:56:[email protected]]
wire _T_9; // @[ScratchpadSlavePort.scala 86:78:[email protected]]
wire ready; // @[ScratchpadSlavePort.scala 86:35:[email protected]]
wire _T_10; // @[ScratchpadSlavePort.scala 87:38:[email protected]]
wire _T_11; // @[ScratchpadSlavePort.scala 87:57:[email protected]]
wire dmem_req_valid; // @[ScratchpadSlavePort.scala 87:48:[email protected]]
wire _T_2; // @[ScratchpadSlavePort.scala 52:26:[email protected]]
reg [2:0] acq_opcode; // @[ScratchpadSlavePort.scala 54:18:[email protected]]
reg [31:0] _RAND_1;
reg [2:0] acq_param; // @[ScratchpadSlavePort.scala 54:18:[email protected]]
reg [31:0] _RAND_2;
reg [1:0] acq_size; // @[ScratchpadSlavePort.scala 54:18:[email protected]]
reg [31:0] _RAND_3;
reg [10:0] acq_source; // @[ScratchpadSlavePort.scala 54:18:[email protected]]
reg [31:0] _RAND_4;
reg [31:0] acq_address; // @[ScratchpadSlavePort.scala 54:18:[email protected]]
reg [31:0] _RAND_5;
reg [3:0] acq_mask; // @[ScratchpadSlavePort.scala 54:18:[email protected]]
reg [31:0] _RAND_6;
reg [31:0] acq_data; // @[ScratchpadSlavePort.scala 54:18:[email protected]]
reg [31:0] _RAND_7;
wire tl_in_a_ready; // @[ScratchpadSlavePort.scala 91:40:[email protected]]
wire _T_3; // @[Decoupled.scala 37:37:[email protected]]
wire ready_likely; // @[ScratchpadSlavePort.scala 85:42:[email protected]]
wire _T_13; // @[ScratchpadSlavePort.scala 88:48:[email protected]]
wire [2:0] _T_17_opcode; // @[ScratchpadSlavePort.scala 92:41:[email protected]]
wire [2:0] _T_17_param; // @[ScratchpadSlavePort.scala 92:41:[email protected]]
wire _T_21; // @[Mux.scala 69:19:[email protected]]
wire [3:0] _T_22; // @[Mux.scala 69:16:[email protected]]
wire _T_23; // @[Mux.scala 69:19:[email protected]]
wire [3:0] _T_24; // @[Mux.scala 69:16:[email protected]]
wire _T_25; // @[Mux.scala 69:19:[email protected]]
wire [3:0] _T_26; // @[Mux.scala 69:16:[email protected]]
wire _T_27; // @[Mux.scala 69:19:[email protected]]
wire [3:0] _T_28; // @[Mux.scala 69:16:[email protected]]
wire _T_29; // @[Mux.scala 69:19:[email protected]]
wire [3:0] _T_30; // @[Mux.scala 69:16:[email protected]]
wire [2:0] _T_33; // @[Mux.scala 69:16:[email protected]]
wire [3:0] _T_35; // @[Mux.scala 69:16:[email protected]]
wire [3:0] _T_37; // @[Mux.scala 69:16:[email protected]]
wire [3:0] _T_39; // @[Mux.scala 69:16:[email protected]]
wire _T_42; // @[Mux.scala 69:19:[email protected]]
wire [3:0] _T_43; // @[Mux.scala 69:16:[email protected]]
wire _T_44; // @[Mux.scala 69:19:[email protected]]
wire [3:0] _T_45; // @[Mux.scala 69:16:[email protected]]
wire _T_46; // @[Mux.scala 69:19:[email protected]]
wire [4:0] _T_47; // @[Mux.scala 69:16:[email protected]]
wire _T_48; // @[Mux.scala 69:19:[email protected]]
wire _T_53; // @[package.scala 15:47:[email protected]]
wire _T_54; // @[package.scala 15:47:[email protected]]
wire _T_55; // @[package.scala 15:62:[email protected]]
reg [31:0] _T_60; // @[Reg.scala 15:16:[email protected]]
reg [31:0] _RAND_8;
assign _T = state == 3'h1; // @[ScratchpadSlavePort.scala 48:17:[email protected]]
assign _T_51 = state == 3'h4; // @[ScratchpadSlavePort.scala 98:50:[email protected]]
assign tl_in_d_valid = io_dmem_resp_valid | _T_51; // @[ScratchpadSlavePort.scala 98:41:[email protected]]
assign _T_1 = auto_in_d_ready & tl_in_d_valid; // @[Decoupled.scala 37:37:[email protected]]
assign _T_6 = state == 3'h0; // @[ScratchpadSlavePort.scala 86:23:[email protected]]
assign _T_7 = state == 3'h2; // @[ScratchpadSlavePort.scala 86:44:[email protected]]
assign _T_8 = _T_7 & io_dmem_resp_valid; // @[ScratchpadSlavePort.scala 86:56:[email protected]]
assign _T_9 = _T_8 & auto_in_d_ready; // @[ScratchpadSlavePort.scala 86:78:[email protected]]
assign ready = _T_6 | _T_9; // @[ScratchpadSlavePort.scala 86:35:[email protected]]
assign _T_10 = auto_in_a_valid & ready; // @[ScratchpadSlavePort.scala 87:38:[email protected]]
assign _T_11 = state == 3'h3; // @[ScratchpadSlavePort.scala 87:57:[email protected]]
assign dmem_req_valid = _T_10 | _T_11; // @[ScratchpadSlavePort.scala 87:48:[email protected]]
assign _T_2 = dmem_req_valid & io_dmem_req_ready; // @[ScratchpadSlavePort.scala 52:26:[email protected]]
assign tl_in_a_ready = io_dmem_req_ready & ready; // @[ScratchpadSlavePort.scala 91:40:[email protected]]
assign _T_3 = tl_in_a_ready & auto_in_a_valid; // @[Decoupled.scala 37:37:[email protected]]
assign ready_likely = _T_6 | _T_7; // @[ScratchpadSlavePort.scala 85:42:[email protected]]
assign _T_13 = auto_in_a_valid & ready_likely; // @[ScratchpadSlavePort.scala 88:48:[email protected]]
assign _T_17_opcode = _T_11 ? acq_opcode : auto_in_a_bits_opcode; // @[ScratchpadSlavePort.scala 92:41:[email protected]]
assign _T_17_param = _T_11 ? acq_param : auto_in_a_bits_param; // @[ScratchpadSlavePort.scala 92:41:[email protected]]
assign _T_21 = 3'h4 == _T_17_param; // @[Mux.scala 69:19:[email protected]]
assign _T_22 = _T_21 ? 4'h8 : 4'h0; // @[Mux.scala 69:16:[email protected]]
assign _T_23 = 3'h3 == _T_17_param; // @[Mux.scala 69:19:[email protected]]
assign _T_24 = _T_23 ? 4'hf : _T_22; // @[Mux.scala 69:16:[email protected]]
assign _T_25 = 3'h2 == _T_17_param; // @[Mux.scala 69:19:[email protected]]
assign _T_26 = _T_25 ? 4'he : _T_24; // @[Mux.scala 69:16:[email protected]]
assign _T_27 = 3'h1 == _T_17_param; // @[Mux.scala 69:19:[email protected]]
assign _T_28 = _T_27 ? 4'hd : _T_26; // @[Mux.scala 69:16:[email protected]]
assign _T_29 = 3'h0 == _T_17_param; // @[Mux.scala 69:19:[email protected]]
assign _T_30 = _T_29 ? 4'hc : _T_28; // @[Mux.scala 69:16:[email protected]]
assign _T_33 = _T_23 ? 3'h4 : 3'h0; // @[Mux.scala 69:16:[email protected]]
assign _T_35 = _T_25 ? 4'hb : {{1'd0}, _T_33}; // @[Mux.scala 69:16:[email protected]]
assign _T_37 = _T_27 ? 4'ha : _T_35; // @[Mux.scala 69:16:[email protected]]
assign _T_39 = _T_29 ? 4'h9 : _T_37; // @[Mux.scala 69:16:[email protected]]
assign _T_42 = 3'h3 == _T_17_opcode; // @[Mux.scala 69:19:[email protected]]
assign _T_43 = _T_42 ? _T_39 : 4'h0; // @[Mux.scala 69:16:[email protected]]
assign _T_44 = 3'h2 == _T_17_opcode; // @[Mux.scala 69:19:[email protected]]
assign _T_45 = _T_44 ? _T_30 : _T_43; // @[Mux.scala 69:16:[email protected]]
assign _T_46 = 3'h1 == _T_17_opcode; // @[Mux.scala 69:19:[email protected]]
assign _T_47 = _T_46 ? 5'h11 : {{1'd0}, _T_45}; // @[Mux.scala 69:16:[email protected]]
assign _T_48 = 3'h0 == _T_17_opcode; // @[Mux.scala 69:19:[email protected]]
assign _T_53 = acq_opcode == 3'h0; // @[package.scala 15:47:[email protected]]
assign _T_54 = acq_opcode == 3'h1; // @[package.scala 15:47:[email protected]]
assign _T_55 = _T_53 | _T_54; // @[package.scala 15:62:[email protected]]
assign auto_in_a_ready = io_dmem_req_ready & ready; // @[LazyModule.scala 173:31:[email protected]]
assign auto_in_d_valid = io_dmem_resp_valid | _T_51; // @[LazyModule.scala 173:31:[email protected]]
assign auto_in_d_bits_opcode = _T_55 ? 3'h0 : 3'h1; // @[LazyModule.scala 173:31:[email protected]]
assign auto_in_d_bits_size = acq_size; // @[LazyModule.scala 173:31:[email protected]]
assign auto_in_d_bits_source = acq_source; // @[LazyModule.scala 173:31:[email protected]]
assign auto_in_d_bits_data = _T_7 ? io_dmem_resp_bits_data_raw : _T_60; // @[LazyModule.scala 173:31:[email protected]]
assign io_dmem_req_valid = _T_13 | _T_11; // @[ScratchpadSlavePort.scala 90:23:[email protected]]
assign io_dmem_req_bits_addr = _T_11 ? acq_address : auto_in_a_bits_address; // @[ScratchpadSlavePort.scala 92:22:[email protected]]
assign io_dmem_req_bits_cmd = _T_48 ? 5'h1 : _T_47; // @[ScratchpadSlavePort.scala 92:22:[email protected]]
assign io_dmem_req_bits_size = _T_11 ? acq_size : auto_in_a_bits_size; // @[ScratchpadSlavePort.scala 92:22:[email protected]]
assign io_dmem_s1_kill = state != 3'h1; // @[ScratchpadSlavePort.scala 95:21:[email protected]]
assign io_dmem_s1_data_data = acq_data; // @[ScratchpadSlavePort.scala 93:26:[email protected]]
assign io_dmem_s1_data_mask = acq_mask; // @[ScratchpadSlavePort.scala 94:26:[email protected]]
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
integer initvar;
`endif
initial begin
`ifdef RANDOMIZE
`ifdef INIT_RANDOM
`INIT_RANDOM
`endif
`ifndef VERILATOR
`ifdef RANDOMIZE_DELAY
#`RANDOMIZE_DELAY begin end
`else
#0.002 begin end
`endif
`endif
`ifdef RANDOMIZE_REG_INIT
_RAND_0 = {1{`RANDOM}};
state = _RAND_0[2:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_1 = {1{`RANDOM}};
acq_opcode = _RAND_1[2:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_2 = {1{`RANDOM}};
acq_param = _RAND_2[2:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_3 = {1{`RANDOM}};
acq_size = _RAND_3[1:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_4 = {1{`RANDOM}};
acq_source = _RAND_4[10:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_5 = {1{`RANDOM}};
acq_address = _RAND_5[31:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_6 = {1{`RANDOM}};
acq_mask = _RAND_6[3:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_7 = {1{`RANDOM}};
acq_data = _RAND_7[31:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_8 = {1{`RANDOM}};
_T_60 = _RAND_8[31:0];
`endif // RANDOMIZE_REG_INIT
`endif // RANDOMIZE
end
always @(posedge clock) begin
if (reset) begin
state <= 3'h0;
end else begin
if (_T_2) begin
state <= 3'h1;
end else begin
if (io_dmem_s2_nack) begin
state <= 3'h3;
end else begin
if (_T_1) begin
state <= 3'h0;
end else begin
if (io_dmem_resp_valid) begin
state <= 3'h4;
end else begin
if (_T) begin
state <= 3'h2;
end
end
end
end
end
end
if (_T_3) begin
acq_opcode <= auto_in_a_bits_opcode;
end
if (_T_3) begin
acq_param <= auto_in_a_bits_param;
end
if (_T_3) begin
acq_size <= auto_in_a_bits_size;
end
if (_T_3) begin
acq_source <= auto_in_a_bits_source;
end
if (_T_3) begin
acq_address <= auto_in_a_bits_address;
end
if (_T_3) begin
acq_mask <= auto_in_a_bits_mask;
end
if (_T_3) begin
acq_data <= auto_in_a_bits_data;
end
if (_T_7) begin
_T_60 <= io_dmem_resp_bits_data_raw;
end
end
endmodule
|
module IntXbar_4( // @[:[email protected]]
input auto_int_in_2_0, // @[:[email protected]]
input auto_int_in_1_0, // @[:[email protected]]
input auto_int_in_1_1, // @[:[email protected]]
input auto_int_in_0_0, // @[:[email protected]]
output auto_int_out_0, // @[:[email protected]]
output auto_int_out_1, // @[:[email protected]]
output auto_int_out_2, // @[:[email protected]]
output auto_int_out_3 // @[:[email protected]]
);
assign auto_int_out_0 = auto_int_in_0_0; // @[LazyModule.scala 173:49:[email protected]]
assign auto_int_out_1 = auto_int_in_1_0; // @[LazyModule.scala 173:49:[email protected]]
assign auto_int_out_2 = auto_int_in_1_1; // @[LazyModule.scala 173:49:[email protected]]
assign auto_int_out_3 = auto_int_in_2_0; // @[LazyModule.scala 173:49:[email protected]]
endmodule
|
module IntSyncCrossingSink_2( // @[:[email protected]]
input auto_in_sync_0, // @[:[email protected]]
output auto_out_0 // @[:[email protected]]
);
assign auto_out_0 = auto_in_sync_0; // @[LazyModule.scala 173:49:[email protected]]
endmodule
|
module SynchronizerShiftReg_w1_d3( // @[:[email protected]]
input clock, // @[:[email protected]]
input io_d, // @[:[email protected]]
output io_q // @[:[email protected]]
);
reg sync_0; // @[ShiftReg.scala 114:16:[email protected]]
reg [31:0] _RAND_0;
reg sync_1; // @[ShiftReg.scala 114:16:[email protected]]
reg [31:0] _RAND_1;
reg sync_2; // @[ShiftReg.scala 114:16:[email protected]]
reg [31:0] _RAND_2;
assign io_q = sync_0; // @[ShiftReg.scala 123:8:[email protected]]
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
integer initvar;
`endif
initial begin
`ifdef RANDOMIZE
`ifdef INIT_RANDOM
`INIT_RANDOM
`endif
`ifndef VERILATOR
`ifdef RANDOMIZE_DELAY
#`RANDOMIZE_DELAY begin end
`else
#0.002 begin end
`endif
`endif
`ifdef RANDOMIZE_REG_INIT
_RAND_0 = {1{`RANDOM}};
sync_0 = _RAND_0[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_1 = {1{`RANDOM}};
sync_1 = _RAND_1[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_2 = {1{`RANDOM}};
sync_2 = _RAND_2[0:0];
`endif // RANDOMIZE_REG_INIT
`endif // RANDOMIZE
end
always @(posedge clock) begin
sync_0 <= sync_1;
sync_1 <= sync_2;
sync_2 <= io_d;
end
endmodule
|
module HellaCacheArbiter( // @[:[email protected]]
input clock, // @[:[email protected]]
output io_requestor_0_req_ready, // @[:[email protected]]
input io_requestor_0_req_valid, // @[:[email protected]]
input [31:0] io_requestor_0_req_bits_addr, // @[:[email protected]]
input [6:0] io_requestor_0_req_bits_tag, // @[:[email protected]]
input [4:0] io_requestor_0_req_bits_cmd, // @[:[email protected]]
input [1:0] io_requestor_0_req_bits_size, // @[:[email protected]]
input io_requestor_0_req_bits_signed, // @[:[email protected]]
input io_requestor_0_s1_kill, // @[:[email protected]]
input [31:0] io_requestor_0_s1_data_data, // @[:[email protected]]
output io_requestor_0_s2_nack, // @[:[email protected]]
output io_requestor_0_resp_valid, // @[:[email protected]]
output [6:0] io_requestor_0_resp_bits_tag, // @[:[email protected]]
output [31:0] io_requestor_0_resp_bits_data, // @[:[email protected]]
output io_requestor_0_resp_bits_replay, // @[:[email protected]]
output io_requestor_0_resp_bits_has_data, // @[:[email protected]]
output [31:0] io_requestor_0_resp_bits_data_word_bypass, // @[:[email protected]]
output io_requestor_0_replay_next, // @[:[email protected]]
output io_requestor_0_s2_xcpt_ma_ld, // @[:[email protected]]
output io_requestor_0_s2_xcpt_ma_st, // @[:[email protected]]
output io_requestor_0_s2_xcpt_pf_ld, // @[:[email protected]]
output io_requestor_0_s2_xcpt_pf_st, // @[:[email protected]]
output io_requestor_0_s2_xcpt_ae_ld, // @[:[email protected]]
output io_requestor_0_s2_xcpt_ae_st, // @[:[email protected]]
output io_requestor_0_ordered, // @[:[email protected]]
output io_requestor_0_perf_grant, // @[:[email protected]]
output io_requestor_1_req_ready, // @[:[email protected]]
input io_requestor_1_req_valid, // @[:[email protected]]
input [31:0] io_requestor_1_req_bits_addr, // @[:[email protected]]
input [4:0] io_requestor_1_req_bits_cmd, // @[:[email protected]]
input [1:0] io_requestor_1_req_bits_size, // @[:[email protected]]
input io_requestor_1_s1_kill, // @[:[email protected]]
input [31:0] io_requestor_1_s1_data_data, // @[:[email protected]]
input [3:0] io_requestor_1_s1_data_mask, // @[:[email protected]]
output io_requestor_1_s2_nack, // @[:[email protected]]
output io_requestor_1_resp_valid, // @[:[email protected]]
output [31:0] io_requestor_1_resp_bits_data_raw, // @[:[email protected]]
input io_mem_req_ready, // @[:[email protected]]
output io_mem_req_valid, // @[:[email protected]]
output [31:0] io_mem_req_bits_addr, // @[:[email protected]]
output [6:0] io_mem_req_bits_tag, // @[:[email protected]]
output [4:0] io_mem_req_bits_cmd, // @[:[email protected]]
output [1:0] io_mem_req_bits_size, // @[:[email protected]]
output io_mem_req_bits_signed, // @[:[email protected]]
output io_mem_req_bits_phys, // @[:[email protected]]
output io_mem_s1_kill, // @[:[email protected]]
output [31:0] io_mem_s1_data_data, // @[:[email protected]]
output [3:0] io_mem_s1_data_mask, // @[:[email protected]]
input io_mem_s2_nack, // @[:[email protected]]
input io_mem_resp_valid, // @[:[email protected]]
input [6:0] io_mem_resp_bits_tag, // @[:[email protected]]
input [31:0] io_mem_resp_bits_data, // @[:[email protected]]
input io_mem_resp_bits_replay, // @[:[email protected]]
input io_mem_resp_bits_has_data, // @[:[email protected]]
input [31:0] io_mem_resp_bits_data_word_bypass, // @[:[email protected]]
input [31:0] io_mem_resp_bits_data_raw, // @[:[email protected]]
input io_mem_replay_next, // @[:[email protected]]
input io_mem_s2_xcpt_ma_ld, // @[:[email protected]]
input io_mem_s2_xcpt_ma_st, // @[:[email protected]]
input io_mem_s2_xcpt_pf_ld, // @[:[email protected]]
input io_mem_s2_xcpt_pf_st, // @[:[email protected]]
input io_mem_s2_xcpt_ae_ld, // @[:[email protected]]
input io_mem_s2_xcpt_ae_st, // @[:[email protected]]
input io_mem_ordered, // @[:[email protected]]
input io_mem_perf_grant // @[:[email protected]]
);
reg _T; // @[HellaCacheArbiter.scala 19:20:[email protected]]
reg [31:0] _RAND_0;
reg _T_1; // @[HellaCacheArbiter.scala 20:20:[email protected]]
reg [31:0] _RAND_1;
wire _T_4; // @[HellaCacheArbiter.scala 27:67:[email protected]]
wire [7:0] _T_7; // @[Cat.scala 30:58:[email protected]]
wire [7:0] _GEN_1; // @[HellaCacheArbiter.scala 49:26:[email protected]]
wire _T_8; // @[HellaCacheArbiter.scala 50:21:[email protected]]
wire _T_9; // @[HellaCacheArbiter.scala 51:21:[email protected]]
wire _T_10; // @[HellaCacheArbiter.scala 59:41:[email protected]]
wire _T_11; // @[HellaCacheArbiter.scala 59:57:[email protected]]
wire [5:0] _T_15; // @[HellaCacheArbiter.scala 70:45:[email protected]]
assign _T_4 = io_requestor_0_req_valid == 1'h0; // @[HellaCacheArbiter.scala 27:67:[email protected]]
assign _T_7 = {io_requestor_0_req_bits_tag,1'h0}; // @[Cat.scala 30:58:[email protected]]
assign _GEN_1 = io_requestor_0_req_valid ? _T_7 : 8'h1; // @[HellaCacheArbiter.scala 49:26:[email protected]]
assign _T_8 = _T == 1'h0; // @[HellaCacheArbiter.scala 50:21:[email protected]]
assign _T_9 = _T_1 == 1'h0; // @[HellaCacheArbiter.scala 51:21:[email protected]]
assign _T_10 = io_mem_resp_bits_tag[0]; // @[HellaCacheArbiter.scala 59:41:[email protected]]
assign _T_11 = _T_10 == 1'h0; // @[HellaCacheArbiter.scala 59:57:[email protected]]
assign _T_15 = io_mem_resp_bits_tag[6:1]; // @[HellaCacheArbiter.scala 70:45:[email protected]]
assign io_requestor_0_req_ready = io_mem_req_ready; // @[HellaCacheArbiter.scala 25:31:[email protected]]
assign io_requestor_0_s2_nack = io_mem_s2_nack & _T_9; // @[HellaCacheArbiter.scala 64:31:[email protected]]
assign io_requestor_0_resp_valid = io_mem_resp_valid & _T_11; // @[HellaCacheArbiter.scala 60:18:[email protected]]
assign io_requestor_0_resp_bits_tag = {{1'd0}, _T_15}; // @[HellaCacheArbiter.scala 69:17:[email protected] HellaCacheArbiter.scala 70:21:[email protected]]
assign io_requestor_0_resp_bits_data = io_mem_resp_bits_data; // @[HellaCacheArbiter.scala 69:17:[email protected]]
assign io_requestor_0_resp_bits_replay = io_mem_resp_bits_replay; // @[HellaCacheArbiter.scala 69:17:[email protected]]
assign io_requestor_0_resp_bits_has_data = io_mem_resp_bits_has_data; // @[HellaCacheArbiter.scala 69:17:[email protected]]
assign io_requestor_0_resp_bits_data_word_bypass = io_mem_resp_bits_data_word_bypass; // @[HellaCacheArbiter.scala 69:17:[email protected]]
assign io_requestor_0_replay_next = io_mem_replay_next; // @[HellaCacheArbiter.scala 72:35:[email protected]]
assign io_requestor_0_s2_xcpt_ma_ld = io_mem_s2_xcpt_ma_ld; // @[HellaCacheArbiter.scala 61:31:[email protected]]
assign io_requestor_0_s2_xcpt_ma_st = io_mem_s2_xcpt_ma_st; // @[HellaCacheArbiter.scala 61:31:[email protected]]
assign io_requestor_0_s2_xcpt_pf_ld = io_mem_s2_xcpt_pf_ld; // @[HellaCacheArbiter.scala 61:31:[email protected]]
assign io_requestor_0_s2_xcpt_pf_st = io_mem_s2_xcpt_pf_st; // @[HellaCacheArbiter.scala 61:31:[email protected]]
assign io_requestor_0_s2_xcpt_ae_ld = io_mem_s2_xcpt_ae_ld; // @[HellaCacheArbiter.scala 61:31:[email protected]]
assign io_requestor_0_s2_xcpt_ae_st = io_mem_s2_xcpt_ae_st; // @[HellaCacheArbiter.scala 61:31:[email protected]]
assign io_requestor_0_ordered = io_mem_ordered; // @[HellaCacheArbiter.scala 62:31:[email protected]]
assign io_requestor_0_perf_grant = io_mem_perf_grant; // @[HellaCacheArbiter.scala 63:28:[email protected]]
assign io_requestor_1_req_ready = io_requestor_0_req_ready & _T_4; // @[HellaCacheArbiter.scala 27:33:[email protected]]
assign io_requestor_1_s2_nack = io_mem_s2_nack & _T_1; // @[HellaCacheArbiter.scala 64:31:[email protected]]
assign io_requestor_1_resp_valid = io_mem_resp_valid & _T_10; // @[HellaCacheArbiter.scala 60:18:[email protected]]
assign io_requestor_1_resp_bits_data_raw = io_mem_resp_bits_data_raw; // @[HellaCacheArbiter.scala 69:17:[email protected]]
assign io_mem_req_valid = io_requestor_0_req_valid | io_requestor_1_req_valid; // @[HellaCacheArbiter.scala 24:22:[email protected]]
assign io_mem_req_bits_addr = io_requestor_0_req_valid ? io_requestor_0_req_bits_addr : io_requestor_1_req_bits_addr; // @[HellaCacheArbiter.scala 32:25:[email protected] HellaCacheArbiter.scala 32:25:[email protected]]
assign io_mem_req_bits_tag = _GEN_1[6:0]; // @[HellaCacheArbiter.scala 32:25:[email protected] HellaCacheArbiter.scala 33:29:[email protected] HellaCacheArbiter.scala 32:25:[email protected] HellaCacheArbiter.scala 33:29:[email protected]]
assign io_mem_req_bits_cmd = io_requestor_0_req_valid ? io_requestor_0_req_bits_cmd : io_requestor_1_req_bits_cmd; // @[HellaCacheArbiter.scala 32:25:[email protected] HellaCacheArbiter.scala 32:25:[email protected]]
assign io_mem_req_bits_size = io_requestor_0_req_valid ? io_requestor_0_req_bits_size : io_requestor_1_req_bits_size; // @[HellaCacheArbiter.scala 32:25:[email protected] HellaCacheArbiter.scala 32:25:[email protected]]
assign io_mem_req_bits_signed = io_requestor_0_req_valid ? io_requestor_0_req_bits_signed : 1'h0; // @[HellaCacheArbiter.scala 32:25:[email protected] HellaCacheArbiter.scala 32:25:[email protected]]
assign io_mem_req_bits_phys = io_requestor_0_req_valid ? 1'h0 : 1'h1; // @[HellaCacheArbiter.scala 32:25:[email protected] HellaCacheArbiter.scala 32:25:[email protected]]
assign io_mem_s1_kill = _T_8 ? io_requestor_0_s1_kill : io_requestor_1_s1_kill; // @[HellaCacheArbiter.scala 37:24:[email protected] HellaCacheArbiter.scala 37:24:[email protected]]
assign io_mem_s1_data_data = _T_8 ? io_requestor_0_s1_data_data : io_requestor_1_s1_data_data; // @[HellaCacheArbiter.scala 38:24:[email protected] HellaCacheArbiter.scala 38:24:[email protected]]
assign io_mem_s1_data_mask = _T_8 ? 4'h0 : io_requestor_1_s1_data_mask; // @[HellaCacheArbiter.scala 38:24:[email protected] HellaCacheArbiter.scala 38:24:[email protected]]
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
integer initvar;
`endif
initial begin
`ifdef RANDOMIZE
`ifdef INIT_RANDOM
`INIT_RANDOM
`endif
`ifndef VERILATOR
`ifdef RANDOMIZE_DELAY
#`RANDOMIZE_DELAY begin end
`else
#0.002 begin end
`endif
`endif
`ifdef RANDOMIZE_REG_INIT
_RAND_0 = {1{`RANDOM}};
_T = _RAND_0[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_1 = {1{`RANDOM}};
_T_1 = _RAND_1[0:0];
`endif // RANDOMIZE_REG_INIT
`endif // RANDOMIZE
end
always @(posedge clock) begin
if (io_requestor_0_req_valid) begin
_T <= 1'h0;
end else begin
_T <= 1'h1;
end
_T_1 <= _T;
end
endmodule
|
module Queue_38( // @[:[email protected]]
input clock, // @[:[email protected]]
input reset, // @[:[email protected]]
output io_enq_ready, // @[:[email protected]]
input io_enq_valid, // @[:[email protected]]
input [2:0] io_enq_bits_opcode, // @[:[email protected]]
input [2:0] io_enq_bits_param, // @[:[email protected]]
input [3:0] io_enq_bits_size, // @[:[email protected]]
input io_enq_bits_source, // @[:[email protected]]
input [31:0] io_enq_bits_address, // @[:[email protected]]
input [3:0] io_enq_bits_mask, // @[:[email protected]]
input [31:0] io_enq_bits_data, // @[:[email protected]]
input io_enq_bits_corrupt, // @[:[email protected]]
input io_deq_ready, // @[:[email protected]]
output io_deq_valid, // @[:[email protected]]
output [2:0] io_deq_bits_opcode, // @[:[email protected]]
output [2:0] io_deq_bits_param, // @[:[email protected]]
output [3:0] io_deq_bits_size, // @[:[email protected]]
output io_deq_bits_source, // @[:[email protected]]
output [31:0] io_deq_bits_address, // @[:[email protected]]
output [3:0] io_deq_bits_mask, // @[:[email protected]]
output [31:0] io_deq_bits_data, // @[:[email protected]]
output io_deq_bits_corrupt // @[:[email protected]]
);
reg [2:0] _T_opcode [0:1]; // @[Decoupled.scala 215:24:[email protected]]
reg [31:0] _RAND_0;
wire [2:0] _T_opcode__T_18_data; // @[Decoupled.scala 215:24:[email protected]]
wire _T_opcode__T_18_addr; // @[Decoupled.scala 215:24:[email protected]]
wire [2:0] _T_opcode__T_10_data; // @[Decoupled.scala 215:24:[email protected]]
wire _T_opcode__T_10_addr; // @[Decoupled.scala 215:24:[email protected]]
wire _T_opcode__T_10_mask; // @[Decoupled.scala 215:24:[email protected]]
wire _T_opcode__T_10_en; // @[Decoupled.scala 215:24:[email protected]]
reg [2:0] _T_param [0:1]; // @[Decoupled.scala 215:24:[email protected]]
reg [31:0] _RAND_1;
wire [2:0] _T_param__T_18_data; // @[Decoupled.scala 215:24:[email protected]]
wire _T_param__T_18_addr; // @[Decoupled.scala 215:24:[email protected]]
wire [2:0] _T_param__T_10_data; // @[Decoupled.scala 215:24:[email protected]]
wire _T_param__T_10_addr; // @[Decoupled.scala 215:24:[email protected]]
wire _T_param__T_10_mask; // @[Decoupled.scala 215:24:[email protected]]
wire _T_param__T_10_en; // @[Decoupled.scala 215:24:[email protected]]
reg [3:0] _T_size [0:1]; // @[Decoupled.scala 215:24:[email protected]]
reg [31:0] _RAND_2;
wire [3:0] _T_size__T_18_data; // @[Decoupled.scala 215:24:[email protected]]
wire _T_size__T_18_addr; // @[Decoupled.scala 215:24:[email protected]]
wire [3:0] _T_size__T_10_data; // @[Decoupled.scala 215:24:[email protected]]
wire _T_size__T_10_addr; // @[Decoupled.scala 215:24:[email protected]]
wire _T_size__T_10_mask; // @[Decoupled.scala 215:24:[email protected]]
wire _T_size__T_10_en; // @[Decoupled.scala 215:24:[email protected]]
reg _T_source [0:1]; // @[Decoupled.scala 215:24:[email protected]]
reg [31:0] _RAND_3;
wire _T_source__T_18_data; // @[Decoupled.scala 215:24:[email protected]]
wire _T_source__T_18_addr; // @[Decoupled.scala 215:24:[email protected]]
wire _T_source__T_10_data; // @[Decoupled.scala 215:24:[email protected]]
wire _T_source__T_10_addr; // @[Decoupled.scala 215:24:[email protected]]
wire _T_source__T_10_mask; // @[Decoupled.scala 215:24:[email protected]]
wire _T_source__T_10_en; // @[Decoupled.scala 215:24:[email protected]]
reg [31:0] _T_address [0:1]; // @[Decoupled.scala 215:24:[email protected]]
reg [31:0] _RAND_4;
wire [31:0] _T_address__T_18_data; // @[Decoupled.scala 215:24:[email protected]]
wire _T_address__T_18_addr; // @[Decoupled.scala 215:24:[email protected]]
wire [31:0] _T_address__T_10_data; // @[Decoupled.scala 215:24:[email protected]]
wire _T_address__T_10_addr; // @[Decoupled.scala 215:24:[email protected]]
wire _T_address__T_10_mask; // @[Decoupled.scala 215:24:[email protected]]
wire _T_address__T_10_en; // @[Decoupled.scala 215:24:[email protected]]
reg [3:0] _T_mask [0:1]; // @[Decoupled.scala 215:24:[email protected]]
reg [31:0] _RAND_5;
wire [3:0] _T_mask__T_18_data; // @[Decoupled.scala 215:24:[email protected]]
wire _T_mask__T_18_addr; // @[Decoupled.scala 215:24:[email protected]]
wire [3:0] _T_mask__T_10_data; // @[Decoupled.scala 215:24:[email protected]]
wire _T_mask__T_10_addr; // @[Decoupled.scala 215:24:[email protected]]
wire _T_mask__T_10_mask; // @[Decoupled.scala 215:24:[email protected]]
wire _T_mask__T_10_en; // @[Decoupled.scala 215:24:[email protected]]
reg [31:0] _T_data [0:1]; // @[Decoupled.scala 215:24:[email protected]]
reg [31:0] _RAND_6;
wire [31:0] _T_data__T_18_data; // @[Decoupled.scala 215:24:[email protected]]
wire _T_data__T_18_addr; // @[Decoupled.scala 215:24:[email protected]]
wire [31:0] _T_data__T_10_data; // @[Decoupled.scala 215:24:[email protected]]
wire _T_data__T_10_addr; // @[Decoupled.scala 215:24:[email protected]]
wire _T_data__T_10_mask; // @[Decoupled.scala 215:24:[email protected]]
wire _T_data__T_10_en; // @[Decoupled.scala 215:24:[email protected]]
reg _T_corrupt [0:1]; // @[Decoupled.scala 215:24:[email protected]]
reg [31:0] _RAND_7;
wire _T_corrupt__T_18_data; // @[Decoupled.scala 215:24:[email protected]]
wire _T_corrupt__T_18_addr; // @[Decoupled.scala 215:24:[email protected]]
wire _T_corrupt__T_10_data; // @[Decoupled.scala 215:24:[email protected]]
wire _T_corrupt__T_10_addr; // @[Decoupled.scala 215:24:[email protected]]
wire _T_corrupt__T_10_mask; // @[Decoupled.scala 215:24:[email protected]]
wire _T_corrupt__T_10_en; // @[Decoupled.scala 215:24:[email protected]]
reg value; // @[Counter.scala 26:33:[email protected]]
reg [31:0] _RAND_8;
reg value_1; // @[Counter.scala 26:33:[email protected]]
reg [31:0] _RAND_9;
reg _T_1; // @[Decoupled.scala 218:35:[email protected]]
reg [31:0] _RAND_10;
wire _T_2; // @[Decoupled.scala 220:41:[email protected]]
wire _T_3; // @[Decoupled.scala 221:36:[email protected]]
wire _T_4; // @[Decoupled.scala 221:33:[email protected]]
wire _T_5; // @[Decoupled.scala 222:32:[email protected]]
wire _T_6; // @[Decoupled.scala 37:37:[email protected]]
wire _T_8; // @[Decoupled.scala 37:37:[email protected]]
wire _T_12; // @[Counter.scala 35:22:[email protected]]
wire _T_14; // @[Counter.scala 35:22:[email protected]]
wire _T_15; // @[Decoupled.scala 233:16:[email protected]]
assign _T_opcode__T_18_addr = value_1;
assign _T_opcode__T_18_data = _T_opcode[_T_opcode__T_18_addr]; // @[Decoupled.scala 215:24:[email protected]]
assign _T_opcode__T_10_data = io_enq_bits_opcode;
assign _T_opcode__T_10_addr = value;
assign _T_opcode__T_10_mask = 1'h1;
assign _T_opcode__T_10_en = io_enq_ready & io_enq_valid;
assign _T_param__T_18_addr = value_1;
assign _T_param__T_18_data = _T_param[_T_param__T_18_addr]; // @[Decoupled.scala 215:24:[email protected]]
assign _T_param__T_10_data = io_enq_bits_param;
assign _T_param__T_10_addr = value;
assign _T_param__T_10_mask = 1'h1;
assign _T_param__T_10_en = io_enq_ready & io_enq_valid;
assign _T_size__T_18_addr = value_1;
assign _T_size__T_18_data = _T_size[_T_size__T_18_addr]; // @[Decoupled.scala 215:24:[email protected]]
assign _T_size__T_10_data = io_enq_bits_size;
assign _T_size__T_10_addr = value;
assign _T_size__T_10_mask = 1'h1;
assign _T_size__T_10_en = io_enq_ready & io_enq_valid;
assign _T_source__T_18_addr = value_1;
assign _T_source__T_18_data = _T_source[_T_source__T_18_addr]; // @[Decoupled.scala 215:24:[email protected]]
assign _T_source__T_10_data = io_enq_bits_source;
assign _T_source__T_10_addr = value;
assign _T_source__T_10_mask = 1'h1;
assign _T_source__T_10_en = io_enq_ready & io_enq_valid;
assign _T_address__T_18_addr = value_1;
assign _T_address__T_18_data = _T_address[_T_address__T_18_addr]; // @[Decoupled.scala 215:24:[email protected]]
assign _T_address__T_10_data = io_enq_bits_address;
assign _T_address__T_10_addr = value;
assign _T_address__T_10_mask = 1'h1;
assign _T_address__T_10_en = io_enq_ready & io_enq_valid;
assign _T_mask__T_18_addr = value_1;
assign _T_mask__T_18_data = _T_mask[_T_mask__T_18_addr]; // @[Decoupled.scala 215:24:[email protected]]
assign _T_mask__T_10_data = io_enq_bits_mask;
assign _T_mask__T_10_addr = value;
assign _T_mask__T_10_mask = 1'h1;
assign _T_mask__T_10_en = io_enq_ready & io_enq_valid;
assign _T_data__T_18_addr = value_1;
assign _T_data__T_18_data = _T_data[_T_data__T_18_addr]; // @[Decoupled.scala 215:24:[email protected]]
assign _T_data__T_10_data = io_enq_bits_data;
assign _T_data__T_10_addr = value;
assign _T_data__T_10_mask = 1'h1;
assign _T_data__T_10_en = io_enq_ready & io_enq_valid;
assign _T_corrupt__T_18_addr = value_1;
assign _T_corrupt__T_18_data = _T_corrupt[_T_corrupt__T_18_addr]; // @[Decoupled.scala 215:24:[email protected]]
assign _T_corrupt__T_10_data = io_enq_bits_corrupt;
assign _T_corrupt__T_10_addr = value;
assign _T_corrupt__T_10_mask = 1'h1;
assign _T_corrupt__T_10_en = io_enq_ready & io_enq_valid;
assign _T_2 = value == value_1; // @[Decoupled.scala 220:41:[email protected]]
assign _T_3 = _T_1 == 1'h0; // @[Decoupled.scala 221:36:[email protected]]
assign _T_4 = _T_2 & _T_3; // @[Decoupled.scala 221:33:[email protected]]
assign _T_5 = _T_2 & _T_1; // @[Decoupled.scala 222:32:[email protected]]
assign _T_6 = io_enq_ready & io_enq_valid; // @[Decoupled.scala 37:37:[email protected]]
assign _T_8 = io_deq_ready & io_deq_valid; // @[Decoupled.scala 37:37:[email protected]]
assign _T_12 = value + 1'h1; // @[Counter.scala 35:22:[email protected]]
assign _T_14 = value_1 + 1'h1; // @[Counter.scala 35:22:[email protected]]
assign _T_15 = _T_6 != _T_8; // @[Decoupled.scala 233:16:[email protected]]
assign io_enq_ready = _T_5 == 1'h0; // @[Decoupled.scala 238:16:[email protected]]
assign io_deq_valid = _T_4 == 1'h0; // @[Decoupled.scala 237:16:[email protected]]
assign io_deq_bits_opcode = _T_opcode__T_18_data; // @[Decoupled.scala 239:15:[email protected]]
assign io_deq_bits_param = _T_param__T_18_data; // @[Decoupled.scala 239:15:[email protected]]
assign io_deq_bits_size = _T_size__T_18_data; // @[Decoupled.scala 239:15:[email protected]]
assign io_deq_bits_source = _T_source__T_18_data; // @[Decoupled.scala 239:15:[email protected]]
assign io_deq_bits_address = _T_address__T_18_data; // @[Decoupled.scala 239:15:[email protected]]
assign io_deq_bits_mask = _T_mask__T_18_data; // @[Decoupled.scala 239:15:[email protected]]
assign io_deq_bits_data = _T_data__T_18_data; // @[Decoupled.scala 239:15:[email protected]]
assign io_deq_bits_corrupt = _T_corrupt__T_18_data; // @[Decoupled.scala 239:15:[email protected]]
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
integer initvar;
`endif
initial begin
`ifdef RANDOMIZE
`ifdef INIT_RANDOM
`INIT_RANDOM
`endif
`ifndef VERILATOR
`ifdef RANDOMIZE_DELAY
#`RANDOMIZE_DELAY begin end
`else
#0.002 begin end
`endif
`endif
_RAND_0 = {1{`RANDOM}};
`ifdef RANDOMIZE_MEM_INIT
for (initvar = 0; initvar < 2; initvar = initvar+1)
_T_opcode[initvar] = _RAND_0[2:0];
`endif // RANDOMIZE_MEM_INIT
_RAND_1 = {1{`RANDOM}};
`ifdef RANDOMIZE_MEM_INIT
for (initvar = 0; initvar < 2; initvar = initvar+1)
_T_param[initvar] = _RAND_1[2:0];
`endif // RANDOMIZE_MEM_INIT
_RAND_2 = {1{`RANDOM}};
`ifdef RANDOMIZE_MEM_INIT
for (initvar = 0; initvar < 2; initvar = initvar+1)
_T_size[initvar] = _RAND_2[3:0];
`endif // RANDOMIZE_MEM_INIT
_RAND_3 = {1{`RANDOM}};
`ifdef RANDOMIZE_MEM_INIT
for (initvar = 0; initvar < 2; initvar = initvar+1)
_T_source[initvar] = _RAND_3[0:0];
`endif // RANDOMIZE_MEM_INIT
_RAND_4 = {1{`RANDOM}};
`ifdef RANDOMIZE_MEM_INIT
for (initvar = 0; initvar < 2; initvar = initvar+1)
_T_address[initvar] = _RAND_4[31:0];
`endif // RANDOMIZE_MEM_INIT
_RAND_5 = {1{`RANDOM}};
`ifdef RANDOMIZE_MEM_INIT
for (initvar = 0; initvar < 2; initvar = initvar+1)
_T_mask[initvar] = _RAND_5[3:0];
`endif // RANDOMIZE_MEM_INIT
_RAND_6 = {1{`RANDOM}};
`ifdef RANDOMIZE_MEM_INIT
for (initvar = 0; initvar < 2; initvar = initvar+1)
_T_data[initvar] = _RAND_6[31:0];
`endif // RANDOMIZE_MEM_INIT
_RAND_7 = {1{`RANDOM}};
`ifdef RANDOMIZE_MEM_INIT
for (initvar = 0; initvar < 2; initvar = initvar+1)
_T_corrupt[initvar] = _RAND_7[0:0];
`endif // RANDOMIZE_MEM_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_8 = {1{`RANDOM}};
value = _RAND_8[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_9 = {1{`RANDOM}};
value_1 = _RAND_9[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_10 = {1{`RANDOM}};
_T_1 = _RAND_10[0:0];
`endif // RANDOMIZE_REG_INIT
`endif // RANDOMIZE
end
always @(posedge clock) begin
if(_T_opcode__T_10_en & _T_opcode__T_10_mask) begin
_T_opcode[_T_opcode__T_10_addr] <= _T_opcode__T_10_data; // @[Decoupled.scala 215:24:[email protected]]
end
if(_T_param__T_10_en & _T_param__T_10_mask) begin
_T_param[_T_param__T_10_addr] <= _T_param__T_10_data; // @[Decoupled.scala 215:24:[email protected]]
end
if(_T_size__T_10_en & _T_size__T_10_mask) begin
_T_size[_T_size__T_10_addr] <= _T_size__T_10_data; // @[Decoupled.scala 215:24:[email protected]]
end
if(_T_source__T_10_en & _T_source__T_10_mask) begin
_T_source[_T_source__T_10_addr] <= _T_source__T_10_data; // @[Decoupled.scala 215:24:[email protected]]
end
if(_T_address__T_10_en & _T_address__T_10_mask) begin
_T_address[_T_address__T_10_addr] <= _T_address__T_10_data; // @[Decoupled.scala 215:24:[email protected]]
end
if(_T_mask__T_10_en & _T_mask__T_10_mask) begin
_T_mask[_T_mask__T_10_addr] <= _T_mask__T_10_data; // @[Decoupled.scala 215:24:[email protected]]
end
if(_T_data__T_10_en & _T_data__T_10_mask) begin
_T_data[_T_data__T_10_addr] <= _T_data__T_10_data; // @[Decoupled.scala 215:24:[email protected]]
end
if(_T_corrupt__T_10_en & _T_corrupt__T_10_mask) begin
_T_corrupt[_T_corrupt__T_10_addr] <= _T_corrupt__T_10_data; // @[Decoupled.scala 215:24:[email protected]]
end
if (reset) begin
value <= 1'h0;
end else begin
if (_T_6) begin
value <= _T_12;
end
end
if (reset) begin
value_1 <= 1'h0;
end else begin
if (_T_8) begin
value_1 <= _T_14;
end
end
if (reset) begin
_T_1 <= 1'h0;
end else begin
if (_T_15) begin
_T_1 <= _T_6;
end
end
end
endmodule
|
module Repeater_5( // @[:[email protected]]
input clock, // @[:[email protected]]
input reset, // @[:[email protected]]
input io_repeat, // @[:[email protected]]
output io_full, // @[:[email protected]]
output io_enq_ready, // @[:[email protected]]
input io_enq_valid, // @[:[email protected]]
input [2:0] io_enq_bits_opcode, // @[:[email protected]]
input [2:0] io_enq_bits_param, // @[:[email protected]]
input [2:0] io_enq_bits_size, // @[:[email protected]]
input [4:0] io_enq_bits_source, // @[:[email protected]]
input [31:0] io_enq_bits_address, // @[:[email protected]]
input [3:0] io_enq_bits_mask, // @[:[email protected]]
input io_deq_ready, // @[:[email protected]]
output io_deq_valid, // @[:[email protected]]
output [2:0] io_deq_bits_opcode, // @[:[email protected]]
output [2:0] io_deq_bits_param, // @[:[email protected]]
output [2:0] io_deq_bits_size, // @[:[email protected]]
output [4:0] io_deq_bits_source, // @[:[email protected]]
output [31:0] io_deq_bits_address, // @[:[email protected]]
output [3:0] io_deq_bits_mask // @[:[email protected]]
);
reg full; // @[Repeater.scala 18:21:[email protected]]
reg [31:0] _RAND_0;
reg [2:0] saved_opcode; // @[Repeater.scala 19:18:[email protected]]
reg [31:0] _RAND_1;
reg [2:0] saved_param; // @[Repeater.scala 19:18:[email protected]]
reg [31:0] _RAND_2;
reg [2:0] saved_size; // @[Repeater.scala 19:18:[email protected]]
reg [31:0] _RAND_3;
reg [4:0] saved_source; // @[Repeater.scala 19:18:[email protected]]
reg [31:0] _RAND_4;
reg [31:0] saved_address; // @[Repeater.scala 19:18:[email protected]]
reg [31:0] _RAND_5;
reg [3:0] saved_mask; // @[Repeater.scala 19:18:[email protected]]
reg [31:0] _RAND_6;
wire _T_1; // @[Repeater.scala 23:35:[email protected]]
wire _T_4; // @[Decoupled.scala 37:37:[email protected]]
wire _T_5; // @[Repeater.scala 27:23:[email protected]]
wire _T_6; // @[Decoupled.scala 37:37:[email protected]]
wire _T_7; // @[Repeater.scala 28:26:[email protected]]
wire _T_8; // @[Repeater.scala 28:23:[email protected]]
assign _T_1 = full == 1'h0; // @[Repeater.scala 23:35:[email protected]]
assign _T_4 = io_enq_ready & io_enq_valid; // @[Decoupled.scala 37:37:[email protected]]
assign _T_5 = _T_4 & io_repeat; // @[Repeater.scala 27:23:[email protected]]
assign _T_6 = io_deq_ready & io_deq_valid; // @[Decoupled.scala 37:37:[email protected]]
assign _T_7 = io_repeat == 1'h0; // @[Repeater.scala 28:26:[email protected]]
assign _T_8 = _T_6 & _T_7; // @[Repeater.scala 28:23:[email protected]]
assign io_full = full; // @[Repeater.scala 25:11:[email protected]]
assign io_enq_ready = io_deq_ready & _T_1; // @[Repeater.scala 23:16:[email protected]]
assign io_deq_valid = io_enq_valid | full; // @[Repeater.scala 22:16:[email protected]]
assign io_deq_bits_opcode = full ? saved_opcode : io_enq_bits_opcode; // @[Repeater.scala 24:15:[email protected]]
assign io_deq_bits_param = full ? saved_param : io_enq_bits_param; // @[Repeater.scala 24:15:[email protected]]
assign io_deq_bits_size = full ? saved_size : io_enq_bits_size; // @[Repeater.scala 24:15:[email protected]]
assign io_deq_bits_source = full ? saved_source : io_enq_bits_source; // @[Repeater.scala 24:15:[email protected]]
assign io_deq_bits_address = full ? saved_address : io_enq_bits_address; // @[Repeater.scala 24:15:[email protected]]
assign io_deq_bits_mask = full ? saved_mask : io_enq_bits_mask; // @[Repeater.scala 24:15:[email protected]]
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
integer initvar;
`endif
initial begin
`ifdef RANDOMIZE
`ifdef INIT_RANDOM
`INIT_RANDOM
`endif
`ifndef VERILATOR
`ifdef RANDOMIZE_DELAY
#`RANDOMIZE_DELAY begin end
`else
#0.002 begin end
`endif
`endif
`ifdef RANDOMIZE_REG_INIT
_RAND_0 = {1{`RANDOM}};
full = _RAND_0[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_1 = {1{`RANDOM}};
saved_opcode = _RAND_1[2:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_2 = {1{`RANDOM}};
saved_param = _RAND_2[2:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_3 = {1{`RANDOM}};
saved_size = _RAND_3[2:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_4 = {1{`RANDOM}};
saved_source = _RAND_4[4:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_5 = {1{`RANDOM}};
saved_address = _RAND_5[31:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_6 = {1{`RANDOM}};
saved_mask = _RAND_6[3:0];
`endif // RANDOMIZE_REG_INIT
`endif // RANDOMIZE
end
always @(posedge clock) begin
if (reset) begin
full <= 1'h0;
end else begin
if (_T_8) begin
full <= 1'h0;
end else begin
if (_T_5) begin
full <= 1'h1;
end
end
end
if (_T_5) begin
saved_opcode <= io_enq_bits_opcode;
end
if (_T_5) begin
saved_param <= io_enq_bits_param;
end
if (_T_5) begin
saved_size <= io_enq_bits_size;
end
if (_T_5) begin
saved_source <= io_enq_bits_source;
end
if (_T_5) begin
saved_address <= io_enq_bits_address;
end
if (_T_5) begin
saved_mask <= io_enq_bits_mask;
end
end
endmodule
|
module ShiftQueue( // @[:[email protected]]
input clock, // @[:[email protected]]
input reset, // @[:[email protected]]
output io_enq_ready, // @[:[email protected]]
input io_enq_valid, // @[:[email protected]]
input [31:0] io_enq_bits_pc, // @[:[email protected]]
input [31:0] io_enq_bits_data, // @[:[email protected]]
input io_enq_bits_xcpt_ae_inst, // @[:[email protected]]
input io_enq_bits_replay, // @[:[email protected]]
input io_deq_ready, // @[:[email protected]]
output io_deq_valid, // @[:[email protected]]
output [31:0] io_deq_bits_pc, // @[:[email protected]]
output [31:0] io_deq_bits_data, // @[:[email protected]]
output io_deq_bits_xcpt_ae_inst, // @[:[email protected]]
output io_deq_bits_replay, // @[:[email protected]]
output [4:0] io_mask // @[:[email protected]]
);
reg _T_1_0; // @[ShiftQueue.scala 20:30:[email protected]]
reg [31:0] _RAND_0;
reg _T_1_1; // @[ShiftQueue.scala 20:30:[email protected]]
reg [31:0] _RAND_1;
reg _T_1_2; // @[ShiftQueue.scala 20:30:[email protected]]
reg [31:0] _RAND_2;
reg _T_1_3; // @[ShiftQueue.scala 20:30:[email protected]]
reg [31:0] _RAND_3;
reg _T_1_4; // @[ShiftQueue.scala 20:30:[email protected]]
reg [31:0] _RAND_4;
reg [31:0] _T_2_0_pc; // @[ShiftQueue.scala 21:25:[email protected]]
reg [31:0] _RAND_5;
reg [31:0] _T_2_0_data; // @[ShiftQueue.scala 21:25:[email protected]]
reg [31:0] _RAND_6;
reg _T_2_0_xcpt_ae_inst; // @[ShiftQueue.scala 21:25:[email protected]]
reg [31:0] _RAND_7;
reg _T_2_0_replay; // @[ShiftQueue.scala 21:25:[email protected]]
reg [31:0] _RAND_8;
reg [31:0] _T_2_1_pc; // @[ShiftQueue.scala 21:25:[email protected]]
reg [31:0] _RAND_9;
reg [31:0] _T_2_1_data; // @[ShiftQueue.scala 21:25:[email protected]]
reg [31:0] _RAND_10;
reg _T_2_1_xcpt_ae_inst; // @[ShiftQueue.scala 21:25:[email protected]]
reg [31:0] _RAND_11;
reg _T_2_1_replay; // @[ShiftQueue.scala 21:25:[email protected]]
reg [31:0] _RAND_12;
reg [31:0] _T_2_2_pc; // @[ShiftQueue.scala 21:25:[email protected]]
reg [31:0] _RAND_13;
reg [31:0] _T_2_2_data; // @[ShiftQueue.scala 21:25:[email protected]]
reg [31:0] _RAND_14;
reg _T_2_2_xcpt_ae_inst; // @[ShiftQueue.scala 21:25:[email protected]]
reg [31:0] _RAND_15;
reg _T_2_2_replay; // @[ShiftQueue.scala 21:25:[email protected]]
reg [31:0] _RAND_16;
reg [31:0] _T_2_3_pc; // @[ShiftQueue.scala 21:25:[email protected]]
reg [31:0] _RAND_17;
reg [31:0] _T_2_3_data; // @[ShiftQueue.scala 21:25:[email protected]]
reg [31:0] _RAND_18;
reg _T_2_3_xcpt_ae_inst; // @[ShiftQueue.scala 21:25:[email protected]]
reg [31:0] _RAND_19;
reg _T_2_3_replay; // @[ShiftQueue.scala 21:25:[email protected]]
reg [31:0] _RAND_20;
reg [31:0] _T_2_4_pc; // @[ShiftQueue.scala 21:25:[email protected]]
reg [31:0] _RAND_21;
reg [31:0] _T_2_4_data; // @[ShiftQueue.scala 21:25:[email protected]]
reg [31:0] _RAND_22;
reg _T_2_4_xcpt_ae_inst; // @[ShiftQueue.scala 21:25:[email protected]]
reg [31:0] _RAND_23;
reg _T_2_4_replay; // @[ShiftQueue.scala 21:25:[email protected]]
reg [31:0] _RAND_24;
wire _T_4; // @[Decoupled.scala 37:37:[email protected]]
wire _T_6; // @[ShiftQueue.scala 29:45:[email protected]]
wire _T_7; // @[ShiftQueue.scala 29:28:[email protected]]
wire _T_10; // @[ShiftQueue.scala 30:48:[email protected]]
wire _T_11; // @[ShiftQueue.scala 30:45:[email protected]]
wire _T_12; // @[ShiftQueue.scala 28:10:[email protected]]
wire _T_19; // @[ShiftQueue.scala 36:45:[email protected]]
wire _T_24; // @[ShiftQueue.scala 29:45:[email protected]]
wire _T_25; // @[ShiftQueue.scala 29:28:[email protected]]
wire _T_28; // @[ShiftQueue.scala 30:48:[email protected]]
wire _T_29; // @[ShiftQueue.scala 30:45:[email protected]]
wire _T_30; // @[ShiftQueue.scala 28:10:[email protected]]
wire _T_37; // @[ShiftQueue.scala 36:45:[email protected]]
wire _T_42; // @[ShiftQueue.scala 29:45:[email protected]]
wire _T_43; // @[ShiftQueue.scala 29:28:[email protected]]
wire _T_46; // @[ShiftQueue.scala 30:48:[email protected]]
wire _T_47; // @[ShiftQueue.scala 30:45:[email protected]]
wire _T_48; // @[ShiftQueue.scala 28:10:[email protected]]
wire _T_55; // @[ShiftQueue.scala 36:45:[email protected]]
wire _T_60; // @[ShiftQueue.scala 29:45:[email protected]]
wire _T_61; // @[ShiftQueue.scala 29:28:[email protected]]
wire _T_64; // @[ShiftQueue.scala 30:48:[email protected]]
wire _T_65; // @[ShiftQueue.scala 30:45:[email protected]]
wire _T_66; // @[ShiftQueue.scala 28:10:[email protected]]
wire _T_73; // @[ShiftQueue.scala 36:45:[email protected]]
wire _T_77; // @[ShiftQueue.scala 29:45:[email protected]]
wire _T_81; // @[ShiftQueue.scala 30:48:[email protected]]
wire _T_82; // @[ShiftQueue.scala 30:45:[email protected]]
wire _T_83; // @[ShiftQueue.scala 28:10:[email protected]]
wire _T_90; // @[ShiftQueue.scala 36:45:[email protected]]
wire [1:0] _T_94; // @[ShiftQueue.scala 52:20:[email protected]]
wire [2:0] _T_96; // @[ShiftQueue.scala 52:20:[email protected]]
assign _T_4 = io_enq_ready & io_enq_valid; // @[Decoupled.scala 37:37:[email protected]]
assign _T_6 = _T_4 & _T_1_0; // @[ShiftQueue.scala 29:45:[email protected]]
assign _T_7 = _T_1_1 | _T_6; // @[ShiftQueue.scala 29:28:[email protected]]
assign _T_10 = _T_1_0 == 1'h0; // @[ShiftQueue.scala 30:48:[email protected]]
assign _T_11 = _T_4 & _T_10; // @[ShiftQueue.scala 30:45:[email protected]]
assign _T_12 = io_deq_ready ? _T_7 : _T_11; // @[ShiftQueue.scala 28:10:[email protected]]
assign _T_19 = _T_4 | _T_1_0; // @[ShiftQueue.scala 36:45:[email protected]]
assign _T_24 = _T_4 & _T_1_1; // @[ShiftQueue.scala 29:45:[email protected]]
assign _T_25 = _T_1_2 | _T_24; // @[ShiftQueue.scala 29:28:[email protected]]
assign _T_28 = _T_1_1 == 1'h0; // @[ShiftQueue.scala 30:48:[email protected]]
assign _T_29 = _T_6 & _T_28; // @[ShiftQueue.scala 30:45:[email protected]]
assign _T_30 = io_deq_ready ? _T_25 : _T_29; // @[ShiftQueue.scala 28:10:[email protected]]
assign _T_37 = _T_6 | _T_1_1; // @[ShiftQueue.scala 36:45:[email protected]]
assign _T_42 = _T_4 & _T_1_2; // @[ShiftQueue.scala 29:45:[email protected]]
assign _T_43 = _T_1_3 | _T_42; // @[ShiftQueue.scala 29:28:[email protected]]
assign _T_46 = _T_1_2 == 1'h0; // @[ShiftQueue.scala 30:48:[email protected]]
assign _T_47 = _T_24 & _T_46; // @[ShiftQueue.scala 30:45:[email protected]]
assign _T_48 = io_deq_ready ? _T_43 : _T_47; // @[ShiftQueue.scala 28:10:[email protected]]
assign _T_55 = _T_24 | _T_1_2; // @[ShiftQueue.scala 36:45:[email protected]]
assign _T_60 = _T_4 & _T_1_3; // @[ShiftQueue.scala 29:45:[email protected]]
assign _T_61 = _T_1_4 | _T_60; // @[ShiftQueue.scala 29:28:[email protected]]
assign _T_64 = _T_1_3 == 1'h0; // @[ShiftQueue.scala 30:48:[email protected]]
assign _T_65 = _T_42 & _T_64; // @[ShiftQueue.scala 30:45:[email protected]]
assign _T_66 = io_deq_ready ? _T_61 : _T_65; // @[ShiftQueue.scala 28:10:[email protected]]
assign _T_73 = _T_42 | _T_1_3; // @[ShiftQueue.scala 36:45:[email protected]]
assign _T_77 = _T_4 & _T_1_4; // @[ShiftQueue.scala 29:45:[email protected]]
assign _T_81 = _T_1_4 == 1'h0; // @[ShiftQueue.scala 30:48:[email protected]]
assign _T_82 = _T_60 & _T_81; // @[ShiftQueue.scala 30:45:[email protected]]
assign _T_83 = io_deq_ready ? _T_77 : _T_82; // @[ShiftQueue.scala 28:10:[email protected]]
assign _T_90 = _T_60 | _T_1_4; // @[ShiftQueue.scala 36:45:[email protected]]
assign _T_94 = {_T_1_1,_T_1_0}; // @[ShiftQueue.scala 52:20:[email protected]]
assign _T_96 = {_T_1_4,_T_1_3,_T_1_2}; // @[ShiftQueue.scala 52:20:[email protected]]
assign io_enq_ready = _T_1_4 == 1'h0; // @[ShiftQueue.scala 39:16:[email protected]]
assign io_deq_valid = io_enq_valid ? 1'h1 : _T_1_0; // @[ShiftQueue.scala 40:16:[email protected] ShiftQueue.scala 44:40:[email protected]]
assign io_deq_bits_pc = _T_10 ? io_enq_bits_pc : _T_2_0_pc; // @[ShiftQueue.scala 41:15:[email protected] ShiftQueue.scala 45:36:[email protected]]
assign io_deq_bits_data = _T_10 ? io_enq_bits_data : _T_2_0_data; // @[ShiftQueue.scala 41:15:[email protected] ShiftQueue.scala 45:36:[email protected]]
assign io_deq_bits_xcpt_ae_inst = _T_10 ? io_enq_bits_xcpt_ae_inst : _T_2_0_xcpt_ae_inst; // @[ShiftQueue.scala 41:15:[email protected] ShiftQueue.scala 45:36:[email protected]]
assign io_deq_bits_replay = _T_10 ? io_enq_bits_replay : _T_2_0_replay; // @[ShiftQueue.scala 41:15:[email protected] ShiftQueue.scala 45:36:[email protected]]
assign io_mask = {_T_96,_T_94}; // @[ShiftQueue.scala 52:11:[email protected]]
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
integer initvar;
`endif
initial begin
`ifdef RANDOMIZE
`ifdef INIT_RANDOM
`INIT_RANDOM
`endif
`ifndef VERILATOR
`ifdef RANDOMIZE_DELAY
#`RANDOMIZE_DELAY begin end
`else
#0.002 begin end
`endif
`endif
`ifdef RANDOMIZE_REG_INIT
_RAND_0 = {1{`RANDOM}};
_T_1_0 = _RAND_0[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_1 = {1{`RANDOM}};
_T_1_1 = _RAND_1[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_2 = {1{`RANDOM}};
_T_1_2 = _RAND_2[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_3 = {1{`RANDOM}};
_T_1_3 = _RAND_3[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_4 = {1{`RANDOM}};
_T_1_4 = _RAND_4[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_5 = {1{`RANDOM}};
_T_2_0_pc = _RAND_5[31:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_6 = {1{`RANDOM}};
_T_2_0_data = _RAND_6[31:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_7 = {1{`RANDOM}};
_T_2_0_xcpt_ae_inst = _RAND_7[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_8 = {1{`RANDOM}};
_T_2_0_replay = _RAND_8[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_9 = {1{`RANDOM}};
_T_2_1_pc = _RAND_9[31:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_10 = {1{`RANDOM}};
_T_2_1_data = _RAND_10[31:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_11 = {1{`RANDOM}};
_T_2_1_xcpt_ae_inst = _RAND_11[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_12 = {1{`RANDOM}};
_T_2_1_replay = _RAND_12[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_13 = {1{`RANDOM}};
_T_2_2_pc = _RAND_13[31:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_14 = {1{`RANDOM}};
_T_2_2_data = _RAND_14[31:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_15 = {1{`RANDOM}};
_T_2_2_xcpt_ae_inst = _RAND_15[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_16 = {1{`RANDOM}};
_T_2_2_replay = _RAND_16[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_17 = {1{`RANDOM}};
_T_2_3_pc = _RAND_17[31:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_18 = {1{`RANDOM}};
_T_2_3_data = _RAND_18[31:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_19 = {1{`RANDOM}};
_T_2_3_xcpt_ae_inst = _RAND_19[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_20 = {1{`RANDOM}};
_T_2_3_replay = _RAND_20[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_21 = {1{`RANDOM}};
_T_2_4_pc = _RAND_21[31:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_22 = {1{`RANDOM}};
_T_2_4_data = _RAND_22[31:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_23 = {1{`RANDOM}};
_T_2_4_xcpt_ae_inst = _RAND_23[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_24 = {1{`RANDOM}};
_T_2_4_replay = _RAND_24[0:0];
`endif // RANDOMIZE_REG_INIT
`endif // RANDOMIZE
end
always @(posedge clock) begin
if (reset) begin
_T_1_0 <= 1'h0;
end else begin
if (io_deq_ready) begin
_T_1_0 <= _T_7;
end else begin
_T_1_0 <= _T_19;
end
end
if (reset) begin
_T_1_1 <= 1'h0;
end else begin
if (io_deq_ready) begin
_T_1_1 <= _T_25;
end else begin
_T_1_1 <= _T_37;
end
end
if (reset) begin
_T_1_2 <= 1'h0;
end else begin
if (io_deq_ready) begin
_T_1_2 <= _T_43;
end else begin
_T_1_2 <= _T_55;
end
end
if (reset) begin
_T_1_3 <= 1'h0;
end else begin
if (io_deq_ready) begin
_T_1_3 <= _T_61;
end else begin
_T_1_3 <= _T_73;
end
end
if (reset) begin
_T_1_4 <= 1'h0;
end else begin
if (io_deq_ready) begin
_T_1_4 <= _T_77;
end else begin
_T_1_4 <= _T_90;
end
end
if (_T_12) begin
if (_T_1_1) begin
_T_2_0_pc <= _T_2_1_pc;
end else begin
_T_2_0_pc <= io_enq_bits_pc;
end
end
if (_T_12) begin
if (_T_1_1) begin
_T_2_0_data <= _T_2_1_data;
end else begin
_T_2_0_data <= io_enq_bits_data;
end
end
if (_T_12) begin
if (_T_1_1) begin
_T_2_0_xcpt_ae_inst <= _T_2_1_xcpt_ae_inst;
end else begin
_T_2_0_xcpt_ae_inst <= io_enq_bits_xcpt_ae_inst;
end
end
if (_T_12) begin
if (_T_1_1) begin
_T_2_0_replay <= _T_2_1_replay;
end else begin
_T_2_0_replay <= io_enq_bits_replay;
end
end
if (_T_30) begin
if (_T_1_2) begin
_T_2_1_pc <= _T_2_2_pc;
end else begin
_T_2_1_pc <= io_enq_bits_pc;
end
end
if (_T_30) begin
if (_T_1_2) begin
_T_2_1_data <= _T_2_2_data;
end else begin
_T_2_1_data <= io_enq_bits_data;
end
end
if (_T_30) begin
if (_T_1_2) begin
_T_2_1_xcpt_ae_inst <= _T_2_2_xcpt_ae_inst;
end else begin
_T_2_1_xcpt_ae_inst <= io_enq_bits_xcpt_ae_inst;
end
end
if (_T_30) begin
if (_T_1_2) begin
_T_2_1_replay <= _T_2_2_replay;
end else begin
_T_2_1_replay <= io_enq_bits_replay;
end
end
if (_T_48) begin
if (_T_1_3) begin
_T_2_2_pc <= _T_2_3_pc;
end else begin
_T_2_2_pc <= io_enq_bits_pc;
end
end
if (_T_48) begin
if (_T_1_3) begin
_T_2_2_data <= _T_2_3_data;
end else begin
_T_2_2_data <= io_enq_bits_data;
end
end
if (_T_48) begin
if (_T_1_3) begin
_T_2_2_xcpt_ae_inst <= _T_2_3_xcpt_ae_inst;
end else begin
_T_2_2_xcpt_ae_inst <= io_enq_bits_xcpt_ae_inst;
end
end
if (_T_48) begin
if (_T_1_3) begin
_T_2_2_replay <= _T_2_3_replay;
end else begin
_T_2_2_replay <= io_enq_bits_replay;
end
end
if (_T_66) begin
if (_T_1_4) begin
_T_2_3_pc <= _T_2_4_pc;
end else begin
_T_2_3_pc <= io_enq_bits_pc;
end
end
if (_T_66) begin
if (_T_1_4) begin
_T_2_3_data <= _T_2_4_data;
end else begin
_T_2_3_data <= io_enq_bits_data;
end
end
if (_T_66) begin
if (_T_1_4) begin
_T_2_3_xcpt_ae_inst <= _T_2_4_xcpt_ae_inst;
end else begin
_T_2_3_xcpt_ae_inst <= io_enq_bits_xcpt_ae_inst;
end
end
if (_T_66) begin
if (_T_1_4) begin
_T_2_3_replay <= _T_2_4_replay;
end else begin
_T_2_3_replay <= io_enq_bits_replay;
end
end
if (_T_83) begin
_T_2_4_pc <= io_enq_bits_pc;
end
if (_T_83) begin
_T_2_4_data <= io_enq_bits_data;
end
if (_T_83) begin
_T_2_4_xcpt_ae_inst <= io_enq_bits_xcpt_ae_inst;
end
if (_T_83) begin
_T_2_4_replay <= io_enq_bits_replay;
end
end
endmodule
|
module IntSyncCrossingSink_1( // @[:[email protected]]
input auto_in_sync_0, // @[:[email protected]]
input auto_in_sync_1, // @[:[email protected]]
output auto_out_0, // @[:[email protected]]
output auto_out_1 // @[:[email protected]]
);
assign auto_out_0 = auto_in_sync_0; // @[LazyModule.scala 173:49:[email protected]]
assign auto_out_1 = auto_in_sync_1; // @[LazyModule.scala 173:49:[email protected]]
endmodule
|
module bp_fe_lce_tr_resp_in_data_width_p64_lce_data_width_p512_lce_addr_width_p22_lce_sets_p64_ways_p8_num_cce_p1_num_lce_p2_block_size_in_bytes_p8
(
tr_received_o,
lce_tr_resp_i,
lce_tr_resp_v_i,
lce_tr_resp_yumi_o,
data_mem_pkt_v_o,
data_mem_pkt_o,
data_mem_pkt_yumi_i
);
input [538:0] lce_tr_resp_i;
output [521:0] data_mem_pkt_o;
input lce_tr_resp_v_i;
input data_mem_pkt_yumi_i;
output tr_received_o;
output lce_tr_resp_yumi_o;
output data_mem_pkt_v_o;
wire [521:0] data_mem_pkt_o;
wire tr_received_o,lce_tr_resp_yumi_o,data_mem_pkt_v_o,lce_tr_resp_v_i;
assign data_mem_pkt_o[512] = 1'b1;
assign data_mem_pkt_v_o = lce_tr_resp_v_i;
assign data_mem_pkt_o[521] = lce_tr_resp_i[523];
assign data_mem_pkt_o[520] = lce_tr_resp_i[522];
assign data_mem_pkt_o[519] = lce_tr_resp_i[521];
assign data_mem_pkt_o[518] = lce_tr_resp_i[520];
assign data_mem_pkt_o[517] = lce_tr_resp_i[519];
assign data_mem_pkt_o[516] = lce_tr_resp_i[518];
assign data_mem_pkt_o[515] = lce_tr_resp_i[536];
assign data_mem_pkt_o[514] = lce_tr_resp_i[535];
assign data_mem_pkt_o[513] = lce_tr_resp_i[534];
assign data_mem_pkt_o[511] = lce_tr_resp_i[511];
assign data_mem_pkt_o[510] = lce_tr_resp_i[510];
assign data_mem_pkt_o[509] = lce_tr_resp_i[509];
assign data_mem_pkt_o[508] = lce_tr_resp_i[508];
assign data_mem_pkt_o[507] = lce_tr_resp_i[507];
assign data_mem_pkt_o[506] = lce_tr_resp_i[506];
assign data_mem_pkt_o[505] = lce_tr_resp_i[505];
assign data_mem_pkt_o[504] = lce_tr_resp_i[504];
assign data_mem_pkt_o[503] = lce_tr_resp_i[503];
assign data_mem_pkt_o[502] = lce_tr_resp_i[502];
assign data_mem_pkt_o[501] = lce_tr_resp_i[501];
assign data_mem_pkt_o[500] = lce_tr_resp_i[500];
assign data_mem_pkt_o[499] = lce_tr_resp_i[499];
assign data_mem_pkt_o[498] = lce_tr_resp_i[498];
assign data_mem_pkt_o[497] = lce_tr_resp_i[497];
assign data_mem_pkt_o[496] = lce_tr_resp_i[496];
assign data_mem_pkt_o[495] = lce_tr_resp_i[495];
assign data_mem_pkt_o[494] = lce_tr_resp_i[494];
assign data_mem_pkt_o[493] = lce_tr_resp_i[493];
assign data_mem_pkt_o[492] = lce_tr_resp_i[492];
assign data_mem_pkt_o[491] = lce_tr_resp_i[491];
assign data_mem_pkt_o[490] = lce_tr_resp_i[490];
assign data_mem_pkt_o[489] = lce_tr_resp_i[489];
assign data_mem_pkt_o[488] = lce_tr_resp_i[488];
assign data_mem_pkt_o[487] = lce_tr_resp_i[487];
assign data_mem_pkt_o[486] = lce_tr_resp_i[486];
assign data_mem_pkt_o[485] = lce_tr_resp_i[485];
assign data_mem_pkt_o[484] = lce_tr_resp_i[484];
assign data_mem_pkt_o[483] = lce_tr_resp_i[483];
assign data_mem_pkt_o[482] = lce_tr_resp_i[482];
assign data_mem_pkt_o[481] = lce_tr_resp_i[481];
assign data_mem_pkt_o[480] = lce_tr_resp_i[480];
assign data_mem_pkt_o[479] = lce_tr_resp_i[479];
assign data_mem_pkt_o[478] = lce_tr_resp_i[478];
assign data_mem_pkt_o[477] = lce_tr_resp_i[477];
assign data_mem_pkt_o[476] = lce_tr_resp_i[476];
assign data_mem_pkt_o[475] = lce_tr_resp_i[475];
assign data_mem_pkt_o[474] = lce_tr_resp_i[474];
assign data_mem_pkt_o[473] = lce_tr_resp_i[473];
assign data_mem_pkt_o[472] = lce_tr_resp_i[472];
assign data_mem_pkt_o[471] = lce_tr_resp_i[471];
assign data_mem_pkt_o[470] = lce_tr_resp_i[470];
assign data_mem_pkt_o[469] = lce_tr_resp_i[469];
assign data_mem_pkt_o[468] = lce_tr_resp_i[468];
assign data_mem_pkt_o[467] = lce_tr_resp_i[467];
assign data_mem_pkt_o[466] = lce_tr_resp_i[466];
assign data_mem_pkt_o[465] = lce_tr_resp_i[465];
assign data_mem_pkt_o[464] = lce_tr_resp_i[464];
assign data_mem_pkt_o[463] = lce_tr_resp_i[463];
assign data_mem_pkt_o[462] = lce_tr_resp_i[462];
assign data_mem_pkt_o[461] = lce_tr_resp_i[461];
assign data_mem_pkt_o[460] = lce_tr_resp_i[460];
assign data_mem_pkt_o[459] = lce_tr_resp_i[459];
assign data_mem_pkt_o[458] = lce_tr_resp_i[458];
assign data_mem_pkt_o[457] = lce_tr_resp_i[457];
assign data_mem_pkt_o[456] = lce_tr_resp_i[456];
assign data_mem_pkt_o[455] = lce_tr_resp_i[455];
assign data_mem_pkt_o[454] = lce_tr_resp_i[454];
assign data_mem_pkt_o[453] = lce_tr_resp_i[453];
assign data_mem_pkt_o[452] = lce_tr_resp_i[452];
assign data_mem_pkt_o[451] = lce_tr_resp_i[451];
assign data_mem_pkt_o[450] = lce_tr_resp_i[450];
assign data_mem_pkt_o[449] = lce_tr_resp_i[449];
assign data_mem_pkt_o[448] = lce_tr_resp_i[448];
assign data_mem_pkt_o[447] = lce_tr_resp_i[447];
assign data_mem_pkt_o[446] = lce_tr_resp_i[446];
assign data_mem_pkt_o[445] = lce_tr_resp_i[445];
assign data_mem_pkt_o[444] = lce_tr_resp_i[444];
assign data_mem_pkt_o[443] = lce_tr_resp_i[443];
assign data_mem_pkt_o[442] = lce_tr_resp_i[442];
assign data_mem_pkt_o[441] = lce_tr_resp_i[441];
assign data_mem_pkt_o[440] = lce_tr_resp_i[440];
assign data_mem_pkt_o[439] = lce_tr_resp_i[439];
assign data_mem_pkt_o[438] = lce_tr_resp_i[438];
assign data_mem_pkt_o[437] = lce_tr_resp_i[437];
assign data_mem_pkt_o[436] = lce_tr_resp_i[436];
assign data_mem_pkt_o[435] = lce_tr_resp_i[435];
assign data_mem_pkt_o[434] = lce_tr_resp_i[434];
assign data_mem_pkt_o[433] = lce_tr_resp_i[433];
assign data_mem_pkt_o[432] = lce_tr_resp_i[432];
assign data_mem_pkt_o[431] = lce_tr_resp_i[431];
assign data_mem_pkt_o[430] = lce_tr_resp_i[430];
assign data_mem_pkt_o[429] = lce_tr_resp_i[429];
assign data_mem_pkt_o[428] = lce_tr_resp_i[428];
assign data_mem_pkt_o[427] = lce_tr_resp_i[427];
assign data_mem_pkt_o[426] = lce_tr_resp_i[426];
assign data_mem_pkt_o[425] = lce_tr_resp_i[425];
assign data_mem_pkt_o[424] = lce_tr_resp_i[424];
assign data_mem_pkt_o[423] = lce_tr_resp_i[423];
assign data_mem_pkt_o[422] = lce_tr_resp_i[422];
assign data_mem_pkt_o[421] = lce_tr_resp_i[421];
assign data_mem_pkt_o[420] = lce_tr_resp_i[420];
assign data_mem_pkt_o[419] = lce_tr_resp_i[419];
assign data_mem_pkt_o[418] = lce_tr_resp_i[418];
assign data_mem_pkt_o[417] = lce_tr_resp_i[417];
assign data_mem_pkt_o[416] = lce_tr_resp_i[416];
assign data_mem_pkt_o[415] = lce_tr_resp_i[415];
assign data_mem_pkt_o[414] = lce_tr_resp_i[414];
assign data_mem_pkt_o[413] = lce_tr_resp_i[413];
assign data_mem_pkt_o[412] = lce_tr_resp_i[412];
assign data_mem_pkt_o[411] = lce_tr_resp_i[411];
assign data_mem_pkt_o[410] = lce_tr_resp_i[410];
assign data_mem_pkt_o[409] = lce_tr_resp_i[409];
assign data_mem_pkt_o[408] = lce_tr_resp_i[408];
assign data_mem_pkt_o[407] = lce_tr_resp_i[407];
assign data_mem_pkt_o[406] = lce_tr_resp_i[406];
assign data_mem_pkt_o[405] = lce_tr_resp_i[405];
assign data_mem_pkt_o[404] = lce_tr_resp_i[404];
assign data_mem_pkt_o[403] = lce_tr_resp_i[403];
assign data_mem_pkt_o[402] = lce_tr_resp_i[402];
assign data_mem_pkt_o[401] = lce_tr_resp_i[401];
assign data_mem_pkt_o[400] = lce_tr_resp_i[400];
assign data_mem_pkt_o[399] = lce_tr_resp_i[399];
assign data_mem_pkt_o[398] = lce_tr_resp_i[398];
assign data_mem_pkt_o[397] = lce_tr_resp_i[397];
assign data_mem_pkt_o[396] = lce_tr_resp_i[396];
assign data_mem_pkt_o[395] = lce_tr_resp_i[395];
assign data_mem_pkt_o[394] = lce_tr_resp_i[394];
assign data_mem_pkt_o[393] = lce_tr_resp_i[393];
assign data_mem_pkt_o[392] = lce_tr_resp_i[392];
assign data_mem_pkt_o[391] = lce_tr_resp_i[391];
assign data_mem_pkt_o[390] = lce_tr_resp_i[390];
assign data_mem_pkt_o[389] = lce_tr_resp_i[389];
assign data_mem_pkt_o[388] = lce_tr_resp_i[388];
assign data_mem_pkt_o[387] = lce_tr_resp_i[387];
assign data_mem_pkt_o[386] = lce_tr_resp_i[386];
assign data_mem_pkt_o[385] = lce_tr_resp_i[385];
assign data_mem_pkt_o[384] = lce_tr_resp_i[384];
assign data_mem_pkt_o[383] = lce_tr_resp_i[383];
assign data_mem_pkt_o[382] = lce_tr_resp_i[382];
assign data_mem_pkt_o[381] = lce_tr_resp_i[381];
assign data_mem_pkt_o[380] = lce_tr_resp_i[380];
assign data_mem_pkt_o[379] = lce_tr_resp_i[379];
assign data_mem_pkt_o[378] = lce_tr_resp_i[378];
assign data_mem_pkt_o[377] = lce_tr_resp_i[377];
assign data_mem_pkt_o[376] = lce_tr_resp_i[376];
assign data_mem_pkt_o[375] = lce_tr_resp_i[375];
assign data_mem_pkt_o[374] = lce_tr_resp_i[374];
assign data_mem_pkt_o[373] = lce_tr_resp_i[373];
assign data_mem_pkt_o[372] = lce_tr_resp_i[372];
assign data_mem_pkt_o[371] = lce_tr_resp_i[371];
assign data_mem_pkt_o[370] = lce_tr_resp_i[370];
assign data_mem_pkt_o[369] = lce_tr_resp_i[369];
assign data_mem_pkt_o[368] = lce_tr_resp_i[368];
assign data_mem_pkt_o[367] = lce_tr_resp_i[367];
assign data_mem_pkt_o[366] = lce_tr_resp_i[366];
assign data_mem_pkt_o[365] = lce_tr_resp_i[365];
assign data_mem_pkt_o[364] = lce_tr_resp_i[364];
assign data_mem_pkt_o[363] = lce_tr_resp_i[363];
assign data_mem_pkt_o[362] = lce_tr_resp_i[362];
assign data_mem_pkt_o[361] = lce_tr_resp_i[361];
assign data_mem_pkt_o[360] = lce_tr_resp_i[360];
assign data_mem_pkt_o[359] = lce_tr_resp_i[359];
assign data_mem_pkt_o[358] = lce_tr_resp_i[358];
assign data_mem_pkt_o[357] = lce_tr_resp_i[357];
assign data_mem_pkt_o[356] = lce_tr_resp_i[356];
assign data_mem_pkt_o[355] = lce_tr_resp_i[355];
assign data_mem_pkt_o[354] = lce_tr_resp_i[354];
assign data_mem_pkt_o[353] = lce_tr_resp_i[353];
assign data_mem_pkt_o[352] = lce_tr_resp_i[352];
assign data_mem_pkt_o[351] = lce_tr_resp_i[351];
assign data_mem_pkt_o[350] = lce_tr_resp_i[350];
assign data_mem_pkt_o[349] = lce_tr_resp_i[349];
assign data_mem_pkt_o[348] = lce_tr_resp_i[348];
assign data_mem_pkt_o[347] = lce_tr_resp_i[347];
assign data_mem_pkt_o[346] = lce_tr_resp_i[346];
assign data_mem_pkt_o[345] = lce_tr_resp_i[345];
assign data_mem_pkt_o[344] = lce_tr_resp_i[344];
assign data_mem_pkt_o[343] = lce_tr_resp_i[343];
assign data_mem_pkt_o[342] = lce_tr_resp_i[342];
assign data_mem_pkt_o[341] = lce_tr_resp_i[341];
assign data_mem_pkt_o[340] = lce_tr_resp_i[340];
assign data_mem_pkt_o[339] = lce_tr_resp_i[339];
assign data_mem_pkt_o[338] = lce_tr_resp_i[338];
assign data_mem_pkt_o[337] = lce_tr_resp_i[337];
assign data_mem_pkt_o[336] = lce_tr_resp_i[336];
assign data_mem_pkt_o[335] = lce_tr_resp_i[335];
assign data_mem_pkt_o[334] = lce_tr_resp_i[334];
assign data_mem_pkt_o[333] = lce_tr_resp_i[333];
assign data_mem_pkt_o[332] = lce_tr_resp_i[332];
assign data_mem_pkt_o[331] = lce_tr_resp_i[331];
assign data_mem_pkt_o[330] = lce_tr_resp_i[330];
assign data_mem_pkt_o[329] = lce_tr_resp_i[329];
assign data_mem_pkt_o[328] = lce_tr_resp_i[328];
assign data_mem_pkt_o[327] = lce_tr_resp_i[327];
assign data_mem_pkt_o[326] = lce_tr_resp_i[326];
assign data_mem_pkt_o[325] = lce_tr_resp_i[325];
assign data_mem_pkt_o[324] = lce_tr_resp_i[324];
assign data_mem_pkt_o[323] = lce_tr_resp_i[323];
assign data_mem_pkt_o[322] = lce_tr_resp_i[322];
assign data_mem_pkt_o[321] = lce_tr_resp_i[321];
assign data_mem_pkt_o[320] = lce_tr_resp_i[320];
assign data_mem_pkt_o[319] = lce_tr_resp_i[319];
assign data_mem_pkt_o[318] = lce_tr_resp_i[318];
assign data_mem_pkt_o[317] = lce_tr_resp_i[317];
assign data_mem_pkt_o[316] = lce_tr_resp_i[316];
assign data_mem_pkt_o[315] = lce_tr_resp_i[315];
assign data_mem_pkt_o[314] = lce_tr_resp_i[314];
assign data_mem_pkt_o[313] = lce_tr_resp_i[313];
assign data_mem_pkt_o[312] = lce_tr_resp_i[312];
assign data_mem_pkt_o[311] = lce_tr_resp_i[311];
assign data_mem_pkt_o[310] = lce_tr_resp_i[310];
assign data_mem_pkt_o[309] = lce_tr_resp_i[309];
assign data_mem_pkt_o[308] = lce_tr_resp_i[308];
assign data_mem_pkt_o[307] = lce_tr_resp_i[307];
assign data_mem_pkt_o[306] = lce_tr_resp_i[306];
assign data_mem_pkt_o[305] = lce_tr_resp_i[305];
assign data_mem_pkt_o[304] = lce_tr_resp_i[304];
assign data_mem_pkt_o[303] = lce_tr_resp_i[303];
assign data_mem_pkt_o[302] = lce_tr_resp_i[302];
assign data_mem_pkt_o[301] = lce_tr_resp_i[301];
assign data_mem_pkt_o[300] = lce_tr_resp_i[300];
assign data_mem_pkt_o[299] = lce_tr_resp_i[299];
assign data_mem_pkt_o[298] = lce_tr_resp_i[298];
assign data_mem_pkt_o[297] = lce_tr_resp_i[297];
assign data_mem_pkt_o[296] = lce_tr_resp_i[296];
assign data_mem_pkt_o[295] = lce_tr_resp_i[295];
assign data_mem_pkt_o[294] = lce_tr_resp_i[294];
assign data_mem_pkt_o[293] = lce_tr_resp_i[293];
assign data_mem_pkt_o[292] = lce_tr_resp_i[292];
assign data_mem_pkt_o[291] = lce_tr_resp_i[291];
assign data_mem_pkt_o[290] = lce_tr_resp_i[290];
assign data_mem_pkt_o[289] = lce_tr_resp_i[289];
assign data_mem_pkt_o[288] = lce_tr_resp_i[288];
assign data_mem_pkt_o[287] = lce_tr_resp_i[287];
assign data_mem_pkt_o[286] = lce_tr_resp_i[286];
assign data_mem_pkt_o[285] = lce_tr_resp_i[285];
assign data_mem_pkt_o[284] = lce_tr_resp_i[284];
assign data_mem_pkt_o[283] = lce_tr_resp_i[283];
assign data_mem_pkt_o[282] = lce_tr_resp_i[282];
assign data_mem_pkt_o[281] = lce_tr_resp_i[281];
assign data_mem_pkt_o[280] = lce_tr_resp_i[280];
assign data_mem_pkt_o[279] = lce_tr_resp_i[279];
assign data_mem_pkt_o[278] = lce_tr_resp_i[278];
assign data_mem_pkt_o[277] = lce_tr_resp_i[277];
assign data_mem_pkt_o[276] = lce_tr_resp_i[276];
assign data_mem_pkt_o[275] = lce_tr_resp_i[275];
assign data_mem_pkt_o[274] = lce_tr_resp_i[274];
assign data_mem_pkt_o[273] = lce_tr_resp_i[273];
assign data_mem_pkt_o[272] = lce_tr_resp_i[272];
assign data_mem_pkt_o[271] = lce_tr_resp_i[271];
assign data_mem_pkt_o[270] = lce_tr_resp_i[270];
assign data_mem_pkt_o[269] = lce_tr_resp_i[269];
assign data_mem_pkt_o[268] = lce_tr_resp_i[268];
assign data_mem_pkt_o[267] = lce_tr_resp_i[267];
assign data_mem_pkt_o[266] = lce_tr_resp_i[266];
assign data_mem_pkt_o[265] = lce_tr_resp_i[265];
assign data_mem_pkt_o[264] = lce_tr_resp_i[264];
assign data_mem_pkt_o[263] = lce_tr_resp_i[263];
assign data_mem_pkt_o[262] = lce_tr_resp_i[262];
assign data_mem_pkt_o[261] = lce_tr_resp_i[261];
assign data_mem_pkt_o[260] = lce_tr_resp_i[260];
assign data_mem_pkt_o[259] = lce_tr_resp_i[259];
assign data_mem_pkt_o[258] = lce_tr_resp_i[258];
assign data_mem_pkt_o[257] = lce_tr_resp_i[257];
assign data_mem_pkt_o[256] = lce_tr_resp_i[256];
assign data_mem_pkt_o[255] = lce_tr_resp_i[255];
assign data_mem_pkt_o[254] = lce_tr_resp_i[254];
assign data_mem_pkt_o[253] = lce_tr_resp_i[253];
assign data_mem_pkt_o[252] = lce_tr_resp_i[252];
assign data_mem_pkt_o[251] = lce_tr_resp_i[251];
assign data_mem_pkt_o[250] = lce_tr_resp_i[250];
assign data_mem_pkt_o[249] = lce_tr_resp_i[249];
assign data_mem_pkt_o[248] = lce_tr_resp_i[248];
assign data_mem_pkt_o[247] = lce_tr_resp_i[247];
assign data_mem_pkt_o[246] = lce_tr_resp_i[246];
assign data_mem_pkt_o[245] = lce_tr_resp_i[245];
assign data_mem_pkt_o[244] = lce_tr_resp_i[244];
assign data_mem_pkt_o[243] = lce_tr_resp_i[243];
assign data_mem_pkt_o[242] = lce_tr_resp_i[242];
assign data_mem_pkt_o[241] = lce_tr_resp_i[241];
assign data_mem_pkt_o[240] = lce_tr_resp_i[240];
assign data_mem_pkt_o[239] = lce_tr_resp_i[239];
assign data_mem_pkt_o[238] = lce_tr_resp_i[238];
assign data_mem_pkt_o[237] = lce_tr_resp_i[237];
assign data_mem_pkt_o[236] = lce_tr_resp_i[236];
assign data_mem_pkt_o[235] = lce_tr_resp_i[235];
assign data_mem_pkt_o[234] = lce_tr_resp_i[234];
assign data_mem_pkt_o[233] = lce_tr_resp_i[233];
assign data_mem_pkt_o[232] = lce_tr_resp_i[232];
assign data_mem_pkt_o[231] = lce_tr_resp_i[231];
assign data_mem_pkt_o[230] = lce_tr_resp_i[230];
assign data_mem_pkt_o[229] = lce_tr_resp_i[229];
assign data_mem_pkt_o[228] = lce_tr_resp_i[228];
assign data_mem_pkt_o[227] = lce_tr_resp_i[227];
assign data_mem_pkt_o[226] = lce_tr_resp_i[226];
assign data_mem_pkt_o[225] = lce_tr_resp_i[225];
assign data_mem_pkt_o[224] = lce_tr_resp_i[224];
assign data_mem_pkt_o[223] = lce_tr_resp_i[223];
assign data_mem_pkt_o[222] = lce_tr_resp_i[222];
assign data_mem_pkt_o[221] = lce_tr_resp_i[221];
assign data_mem_pkt_o[220] = lce_tr_resp_i[220];
assign data_mem_pkt_o[219] = lce_tr_resp_i[219];
assign data_mem_pkt_o[218] = lce_tr_resp_i[218];
assign data_mem_pkt_o[217] = lce_tr_resp_i[217];
assign data_mem_pkt_o[216] = lce_tr_resp_i[216];
assign data_mem_pkt_o[215] = lce_tr_resp_i[215];
assign data_mem_pkt_o[214] = lce_tr_resp_i[214];
assign data_mem_pkt_o[213] = lce_tr_resp_i[213];
assign data_mem_pkt_o[212] = lce_tr_resp_i[212];
assign data_mem_pkt_o[211] = lce_tr_resp_i[211];
assign data_mem_pkt_o[210] = lce_tr_resp_i[210];
assign data_mem_pkt_o[209] = lce_tr_resp_i[209];
assign data_mem_pkt_o[208] = lce_tr_resp_i[208];
assign data_mem_pkt_o[207] = lce_tr_resp_i[207];
assign data_mem_pkt_o[206] = lce_tr_resp_i[206];
assign data_mem_pkt_o[205] = lce_tr_resp_i[205];
assign data_mem_pkt_o[204] = lce_tr_resp_i[204];
assign data_mem_pkt_o[203] = lce_tr_resp_i[203];
assign data_mem_pkt_o[202] = lce_tr_resp_i[202];
assign data_mem_pkt_o[201] = lce_tr_resp_i[201];
assign data_mem_pkt_o[200] = lce_tr_resp_i[200];
assign data_mem_pkt_o[199] = lce_tr_resp_i[199];
assign data_mem_pkt_o[198] = lce_tr_resp_i[198];
assign data_mem_pkt_o[197] = lce_tr_resp_i[197];
assign data_mem_pkt_o[196] = lce_tr_resp_i[196];
assign data_mem_pkt_o[195] = lce_tr_resp_i[195];
assign data_mem_pkt_o[194] = lce_tr_resp_i[194];
assign data_mem_pkt_o[193] = lce_tr_resp_i[193];
assign data_mem_pkt_o[192] = lce_tr_resp_i[192];
assign data_mem_pkt_o[191] = lce_tr_resp_i[191];
assign data_mem_pkt_o[190] = lce_tr_resp_i[190];
assign data_mem_pkt_o[189] = lce_tr_resp_i[189];
assign data_mem_pkt_o[188] = lce_tr_resp_i[188];
assign data_mem_pkt_o[187] = lce_tr_resp_i[187];
assign data_mem_pkt_o[186] = lce_tr_resp_i[186];
assign data_mem_pkt_o[185] = lce_tr_resp_i[185];
assign data_mem_pkt_o[184] = lce_tr_resp_i[184];
assign data_mem_pkt_o[183] = lce_tr_resp_i[183];
assign data_mem_pkt_o[182] = lce_tr_resp_i[182];
assign data_mem_pkt_o[181] = lce_tr_resp_i[181];
assign data_mem_pkt_o[180] = lce_tr_resp_i[180];
assign data_mem_pkt_o[179] = lce_tr_resp_i[179];
assign data_mem_pkt_o[178] = lce_tr_resp_i[178];
assign data_mem_pkt_o[177] = lce_tr_resp_i[177];
assign data_mem_pkt_o[176] = lce_tr_resp_i[176];
assign data_mem_pkt_o[175] = lce_tr_resp_i[175];
assign data_mem_pkt_o[174] = lce_tr_resp_i[174];
assign data_mem_pkt_o[173] = lce_tr_resp_i[173];
assign data_mem_pkt_o[172] = lce_tr_resp_i[172];
assign data_mem_pkt_o[171] = lce_tr_resp_i[171];
assign data_mem_pkt_o[170] = lce_tr_resp_i[170];
assign data_mem_pkt_o[169] = lce_tr_resp_i[169];
assign data_mem_pkt_o[168] = lce_tr_resp_i[168];
assign data_mem_pkt_o[167] = lce_tr_resp_i[167];
assign data_mem_pkt_o[166] = lce_tr_resp_i[166];
assign data_mem_pkt_o[165] = lce_tr_resp_i[165];
assign data_mem_pkt_o[164] = lce_tr_resp_i[164];
assign data_mem_pkt_o[163] = lce_tr_resp_i[163];
assign data_mem_pkt_o[162] = lce_tr_resp_i[162];
assign data_mem_pkt_o[161] = lce_tr_resp_i[161];
assign data_mem_pkt_o[160] = lce_tr_resp_i[160];
assign data_mem_pkt_o[159] = lce_tr_resp_i[159];
assign data_mem_pkt_o[158] = lce_tr_resp_i[158];
assign data_mem_pkt_o[157] = lce_tr_resp_i[157];
assign data_mem_pkt_o[156] = lce_tr_resp_i[156];
assign data_mem_pkt_o[155] = lce_tr_resp_i[155];
assign data_mem_pkt_o[154] = lce_tr_resp_i[154];
assign data_mem_pkt_o[153] = lce_tr_resp_i[153];
assign data_mem_pkt_o[152] = lce_tr_resp_i[152];
assign data_mem_pkt_o[151] = lce_tr_resp_i[151];
assign data_mem_pkt_o[150] = lce_tr_resp_i[150];
assign data_mem_pkt_o[149] = lce_tr_resp_i[149];
assign data_mem_pkt_o[148] = lce_tr_resp_i[148];
assign data_mem_pkt_o[147] = lce_tr_resp_i[147];
assign data_mem_pkt_o[146] = lce_tr_resp_i[146];
assign data_mem_pkt_o[145] = lce_tr_resp_i[145];
assign data_mem_pkt_o[144] = lce_tr_resp_i[144];
assign data_mem_pkt_o[143] = lce_tr_resp_i[143];
assign data_mem_pkt_o[142] = lce_tr_resp_i[142];
assign data_mem_pkt_o[141] = lce_tr_resp_i[141];
assign data_mem_pkt_o[140] = lce_tr_resp_i[140];
assign data_mem_pkt_o[139] = lce_tr_resp_i[139];
assign data_mem_pkt_o[138] = lce_tr_resp_i[138];
assign data_mem_pkt_o[137] = lce_tr_resp_i[137];
assign data_mem_pkt_o[136] = lce_tr_resp_i[136];
assign data_mem_pkt_o[135] = lce_tr_resp_i[135];
assign data_mem_pkt_o[134] = lce_tr_resp_i[134];
assign data_mem_pkt_o[133] = lce_tr_resp_i[133];
assign data_mem_pkt_o[132] = lce_tr_resp_i[132];
assign data_mem_pkt_o[131] = lce_tr_resp_i[131];
assign data_mem_pkt_o[130] = lce_tr_resp_i[130];
assign data_mem_pkt_o[129] = lce_tr_resp_i[129];
assign data_mem_pkt_o[128] = lce_tr_resp_i[128];
assign data_mem_pkt_o[127] = lce_tr_resp_i[127];
assign data_mem_pkt_o[126] = lce_tr_resp_i[126];
assign data_mem_pkt_o[125] = lce_tr_resp_i[125];
assign data_mem_pkt_o[124] = lce_tr_resp_i[124];
assign data_mem_pkt_o[123] = lce_tr_resp_i[123];
assign data_mem_pkt_o[122] = lce_tr_resp_i[122];
assign data_mem_pkt_o[121] = lce_tr_resp_i[121];
assign data_mem_pkt_o[120] = lce_tr_resp_i[120];
assign data_mem_pkt_o[119] = lce_tr_resp_i[119];
assign data_mem_pkt_o[118] = lce_tr_resp_i[118];
assign data_mem_pkt_o[117] = lce_tr_resp_i[117];
assign data_mem_pkt_o[116] = lce_tr_resp_i[116];
assign data_mem_pkt_o[115] = lce_tr_resp_i[115];
assign data_mem_pkt_o[114] = lce_tr_resp_i[114];
assign data_mem_pkt_o[113] = lce_tr_resp_i[113];
assign data_mem_pkt_o[112] = lce_tr_resp_i[112];
assign data_mem_pkt_o[111] = lce_tr_resp_i[111];
assign data_mem_pkt_o[110] = lce_tr_resp_i[110];
assign data_mem_pkt_o[109] = lce_tr_resp_i[109];
assign data_mem_pkt_o[108] = lce_tr_resp_i[108];
assign data_mem_pkt_o[107] = lce_tr_resp_i[107];
assign data_mem_pkt_o[106] = lce_tr_resp_i[106];
assign data_mem_pkt_o[105] = lce_tr_resp_i[105];
assign data_mem_pkt_o[104] = lce_tr_resp_i[104];
assign data_mem_pkt_o[103] = lce_tr_resp_i[103];
assign data_mem_pkt_o[102] = lce_tr_resp_i[102];
assign data_mem_pkt_o[101] = lce_tr_resp_i[101];
assign data_mem_pkt_o[100] = lce_tr_resp_i[100];
assign data_mem_pkt_o[99] = lce_tr_resp_i[99];
assign data_mem_pkt_o[98] = lce_tr_resp_i[98];
assign data_mem_pkt_o[97] = lce_tr_resp_i[97];
assign data_mem_pkt_o[96] = lce_tr_resp_i[96];
assign data_mem_pkt_o[95] = lce_tr_resp_i[95];
assign data_mem_pkt_o[94] = lce_tr_resp_i[94];
assign data_mem_pkt_o[93] = lce_tr_resp_i[93];
assign data_mem_pkt_o[92] = lce_tr_resp_i[92];
assign data_mem_pkt_o[91] = lce_tr_resp_i[91];
assign data_mem_pkt_o[90] = lce_tr_resp_i[90];
assign data_mem_pkt_o[89] = lce_tr_resp_i[89];
assign data_mem_pkt_o[88] = lce_tr_resp_i[88];
assign data_mem_pkt_o[87] = lce_tr_resp_i[87];
assign data_mem_pkt_o[86] = lce_tr_resp_i[86];
assign data_mem_pkt_o[85] = lce_tr_resp_i[85];
assign data_mem_pkt_o[84] = lce_tr_resp_i[84];
assign data_mem_pkt_o[83] = lce_tr_resp_i[83];
assign data_mem_pkt_o[82] = lce_tr_resp_i[82];
assign data_mem_pkt_o[81] = lce_tr_resp_i[81];
assign data_mem_pkt_o[80] = lce_tr_resp_i[80];
assign data_mem_pkt_o[79] = lce_tr_resp_i[79];
assign data_mem_pkt_o[78] = lce_tr_resp_i[78];
assign data_mem_pkt_o[77] = lce_tr_resp_i[77];
assign data_mem_pkt_o[76] = lce_tr_resp_i[76];
assign data_mem_pkt_o[75] = lce_tr_resp_i[75];
assign data_mem_pkt_o[74] = lce_tr_resp_i[74];
assign data_mem_pkt_o[73] = lce_tr_resp_i[73];
assign data_mem_pkt_o[72] = lce_tr_resp_i[72];
assign data_mem_pkt_o[71] = lce_tr_resp_i[71];
assign data_mem_pkt_o[70] = lce_tr_resp_i[70];
assign data_mem_pkt_o[69] = lce_tr_resp_i[69];
assign data_mem_pkt_o[68] = lce_tr_resp_i[68];
assign data_mem_pkt_o[67] = lce_tr_resp_i[67];
assign data_mem_pkt_o[66] = lce_tr_resp_i[66];
assign data_mem_pkt_o[65] = lce_tr_resp_i[65];
assign data_mem_pkt_o[64] = lce_tr_resp_i[64];
assign data_mem_pkt_o[63] = lce_tr_resp_i[63];
assign data_mem_pkt_o[62] = lce_tr_resp_i[62];
assign data_mem_pkt_o[61] = lce_tr_resp_i[61];
assign data_mem_pkt_o[60] = lce_tr_resp_i[60];
assign data_mem_pkt_o[59] = lce_tr_resp_i[59];
assign data_mem_pkt_o[58] = lce_tr_resp_i[58];
assign data_mem_pkt_o[57] = lce_tr_resp_i[57];
assign data_mem_pkt_o[56] = lce_tr_resp_i[56];
assign data_mem_pkt_o[55] = lce_tr_resp_i[55];
assign data_mem_pkt_o[54] = lce_tr_resp_i[54];
assign data_mem_pkt_o[53] = lce_tr_resp_i[53];
assign data_mem_pkt_o[52] = lce_tr_resp_i[52];
assign data_mem_pkt_o[51] = lce_tr_resp_i[51];
assign data_mem_pkt_o[50] = lce_tr_resp_i[50];
assign data_mem_pkt_o[49] = lce_tr_resp_i[49];
assign data_mem_pkt_o[48] = lce_tr_resp_i[48];
assign data_mem_pkt_o[47] = lce_tr_resp_i[47];
assign data_mem_pkt_o[46] = lce_tr_resp_i[46];
assign data_mem_pkt_o[45] = lce_tr_resp_i[45];
assign data_mem_pkt_o[44] = lce_tr_resp_i[44];
assign data_mem_pkt_o[43] = lce_tr_resp_i[43];
assign data_mem_pkt_o[42] = lce_tr_resp_i[42];
assign data_mem_pkt_o[41] = lce_tr_resp_i[41];
assign data_mem_pkt_o[40] = lce_tr_resp_i[40];
assign data_mem_pkt_o[39] = lce_tr_resp_i[39];
assign data_mem_pkt_o[38] = lce_tr_resp_i[38];
assign data_mem_pkt_o[37] = lce_tr_resp_i[37];
assign data_mem_pkt_o[36] = lce_tr_resp_i[36];
assign data_mem_pkt_o[35] = lce_tr_resp_i[35];
assign data_mem_pkt_o[34] = lce_tr_resp_i[34];
assign data_mem_pkt_o[33] = lce_tr_resp_i[33];
assign data_mem_pkt_o[32] = lce_tr_resp_i[32];
assign data_mem_pkt_o[31] = lce_tr_resp_i[31];
assign data_mem_pkt_o[30] = lce_tr_resp_i[30];
assign data_mem_pkt_o[29] = lce_tr_resp_i[29];
assign data_mem_pkt_o[28] = lce_tr_resp_i[28];
assign data_mem_pkt_o[27] = lce_tr_resp_i[27];
assign data_mem_pkt_o[26] = lce_tr_resp_i[26];
assign data_mem_pkt_o[25] = lce_tr_resp_i[25];
assign data_mem_pkt_o[24] = lce_tr_resp_i[24];
assign data_mem_pkt_o[23] = lce_tr_resp_i[23];
assign data_mem_pkt_o[22] = lce_tr_resp_i[22];
assign data_mem_pkt_o[21] = lce_tr_resp_i[21];
assign data_mem_pkt_o[20] = lce_tr_resp_i[20];
assign data_mem_pkt_o[19] = lce_tr_resp_i[19];
assign data_mem_pkt_o[18] = lce_tr_resp_i[18];
assign data_mem_pkt_o[17] = lce_tr_resp_i[17];
assign data_mem_pkt_o[16] = lce_tr_resp_i[16];
assign data_mem_pkt_o[15] = lce_tr_resp_i[15];
assign data_mem_pkt_o[14] = lce_tr_resp_i[14];
assign data_mem_pkt_o[13] = lce_tr_resp_i[13];
assign data_mem_pkt_o[12] = lce_tr_resp_i[12];
assign data_mem_pkt_o[11] = lce_tr_resp_i[11];
assign data_mem_pkt_o[10] = lce_tr_resp_i[10];
assign data_mem_pkt_o[9] = lce_tr_resp_i[9];
assign data_mem_pkt_o[8] = lce_tr_resp_i[8];
assign data_mem_pkt_o[7] = lce_tr_resp_i[7];
assign data_mem_pkt_o[6] = lce_tr_resp_i[6];
assign data_mem_pkt_o[5] = lce_tr_resp_i[5];
assign data_mem_pkt_o[4] = lce_tr_resp_i[4];
assign data_mem_pkt_o[3] = lce_tr_resp_i[3];
assign data_mem_pkt_o[2] = lce_tr_resp_i[2];
assign data_mem_pkt_o[1] = lce_tr_resp_i[1];
assign data_mem_pkt_o[0] = lce_tr_resp_i[0];
assign lce_tr_resp_yumi_o = data_mem_pkt_yumi_i & lce_tr_resp_v_i;
assign tr_received_o = data_mem_pkt_yumi_i & lce_tr_resp_v_i;
endmodule
|
module bsg_mux_width_p64_els_p8
(
data_i,
sel_i,
data_o
);
input [511:0] data_i;
input [2:0] sel_i;
output [63:0] data_o;
wire [63:0] data_o;
wire N0,N1,N2,N3,N4,N5,N6,N7,N8,N9,N10,N11,N12,N13,N14;
assign data_o[63] = (N7)? data_i[63] :
(N9)? data_i[127] :
(N11)? data_i[191] :
(N13)? data_i[255] :
(N8)? data_i[319] :
(N10)? data_i[383] :
(N12)? data_i[447] :
(N14)? data_i[511] : 1'b0;
assign data_o[62] = (N7)? data_i[62] :
(N9)? data_i[126] :
(N11)? data_i[190] :
(N13)? data_i[254] :
(N8)? data_i[318] :
(N10)? data_i[382] :
(N12)? data_i[446] :
(N14)? data_i[510] : 1'b0;
assign data_o[61] = (N7)? data_i[61] :
(N9)? data_i[125] :
(N11)? data_i[189] :
(N13)? data_i[253] :
(N8)? data_i[317] :
(N10)? data_i[381] :
(N12)? data_i[445] :
(N14)? data_i[509] : 1'b0;
assign data_o[60] = (N7)? data_i[60] :
(N9)? data_i[124] :
(N11)? data_i[188] :
(N13)? data_i[252] :
(N8)? data_i[316] :
(N10)? data_i[380] :
(N12)? data_i[444] :
(N14)? data_i[508] : 1'b0;
assign data_o[59] = (N7)? data_i[59] :
(N9)? data_i[123] :
(N11)? data_i[187] :
(N13)? data_i[251] :
(N8)? data_i[315] :
(N10)? data_i[379] :
(N12)? data_i[443] :
(N14)? data_i[507] : 1'b0;
assign data_o[58] = (N7)? data_i[58] :
(N9)? data_i[122] :
(N11)? data_i[186] :
(N13)? data_i[250] :
(N8)? data_i[314] :
(N10)? data_i[378] :
(N12)? data_i[442] :
(N14)? data_i[506] : 1'b0;
assign data_o[57] = (N7)? data_i[57] :
(N9)? data_i[121] :
(N11)? data_i[185] :
(N13)? data_i[249] :
(N8)? data_i[313] :
(N10)? data_i[377] :
(N12)? data_i[441] :
(N14)? data_i[505] : 1'b0;
assign data_o[56] = (N7)? data_i[56] :
(N9)? data_i[120] :
(N11)? data_i[184] :
(N13)? data_i[248] :
(N8)? data_i[312] :
(N10)? data_i[376] :
(N12)? data_i[440] :
(N14)? data_i[504] : 1'b0;
assign data_o[55] = (N7)? data_i[55] :
(N9)? data_i[119] :
(N11)? data_i[183] :
(N13)? data_i[247] :
(N8)? data_i[311] :
(N10)? data_i[375] :
(N12)? data_i[439] :
(N14)? data_i[503] : 1'b0;
assign data_o[54] = (N7)? data_i[54] :
(N9)? data_i[118] :
(N11)? data_i[182] :
(N13)? data_i[246] :
(N8)? data_i[310] :
(N10)? data_i[374] :
(N12)? data_i[438] :
(N14)? data_i[502] : 1'b0;
assign data_o[53] = (N7)? data_i[53] :
(N9)? data_i[117] :
(N11)? data_i[181] :
(N13)? data_i[245] :
(N8)? data_i[309] :
(N10)? data_i[373] :
(N12)? data_i[437] :
(N14)? data_i[501] : 1'b0;
assign data_o[52] = (N7)? data_i[52] :
(N9)? data_i[116] :
(N11)? data_i[180] :
(N13)? data_i[244] :
(N8)? data_i[308] :
(N10)? data_i[372] :
(N12)? data_i[436] :
(N14)? data_i[500] : 1'b0;
assign data_o[51] = (N7)? data_i[51] :
(N9)? data_i[115] :
(N11)? data_i[179] :
(N13)? data_i[243] :
(N8)? data_i[307] :
(N10)? data_i[371] :
(N12)? data_i[435] :
(N14)? data_i[499] : 1'b0;
assign data_o[50] = (N7)? data_i[50] :
(N9)? data_i[114] :
(N11)? data_i[178] :
(N13)? data_i[242] :
(N8)? data_i[306] :
(N10)? data_i[370] :
(N12)? data_i[434] :
(N14)? data_i[498] : 1'b0;
assign data_o[49] = (N7)? data_i[49] :
(N9)? data_i[113] :
(N11)? data_i[177] :
(N13)? data_i[241] :
(N8)? data_i[305] :
(N10)? data_i[369] :
(N12)? data_i[433] :
(N14)? data_i[497] : 1'b0;
assign data_o[48] = (N7)? data_i[48] :
(N9)? data_i[112] :
(N11)? data_i[176] :
(N13)? data_i[240] :
(N8)? data_i[304] :
(N10)? data_i[368] :
(N12)? data_i[432] :
(N14)? data_i[496] : 1'b0;
assign data_o[47] = (N7)? data_i[47] :
(N9)? data_i[111] :
(N11)? data_i[175] :
(N13)? data_i[239] :
(N8)? data_i[303] :
(N10)? data_i[367] :
(N12)? data_i[431] :
(N14)? data_i[495] : 1'b0;
assign data_o[46] = (N7)? data_i[46] :
(N9)? data_i[110] :
(N11)? data_i[174] :
(N13)? data_i[238] :
(N8)? data_i[302] :
(N10)? data_i[366] :
(N12)? data_i[430] :
(N14)? data_i[494] : 1'b0;
assign data_o[45] = (N7)? data_i[45] :
(N9)? data_i[109] :
(N11)? data_i[173] :
(N13)? data_i[237] :
(N8)? data_i[301] :
(N10)? data_i[365] :
(N12)? data_i[429] :
(N14)? data_i[493] : 1'b0;
assign data_o[44] = (N7)? data_i[44] :
(N9)? data_i[108] :
(N11)? data_i[172] :
(N13)? data_i[236] :
(N8)? data_i[300] :
(N10)? data_i[364] :
(N12)? data_i[428] :
(N14)? data_i[492] : 1'b0;
assign data_o[43] = (N7)? data_i[43] :
(N9)? data_i[107] :
(N11)? data_i[171] :
(N13)? data_i[235] :
(N8)? data_i[299] :
(N10)? data_i[363] :
(N12)? data_i[427] :
(N14)? data_i[491] : 1'b0;
assign data_o[42] = (N7)? data_i[42] :
(N9)? data_i[106] :
(N11)? data_i[170] :
(N13)? data_i[234] :
(N8)? data_i[298] :
(N10)? data_i[362] :
(N12)? data_i[426] :
(N14)? data_i[490] : 1'b0;
assign data_o[41] = (N7)? data_i[41] :
(N9)? data_i[105] :
(N11)? data_i[169] :
(N13)? data_i[233] :
(N8)? data_i[297] :
(N10)? data_i[361] :
(N12)? data_i[425] :
(N14)? data_i[489] : 1'b0;
assign data_o[40] = (N7)? data_i[40] :
(N9)? data_i[104] :
(N11)? data_i[168] :
(N13)? data_i[232] :
(N8)? data_i[296] :
(N10)? data_i[360] :
(N12)? data_i[424] :
(N14)? data_i[488] : 1'b0;
assign data_o[39] = (N7)? data_i[39] :
(N9)? data_i[103] :
(N11)? data_i[167] :
(N13)? data_i[231] :
(N8)? data_i[295] :
(N10)? data_i[359] :
(N12)? data_i[423] :
(N14)? data_i[487] : 1'b0;
assign data_o[38] = (N7)? data_i[38] :
(N9)? data_i[102] :
(N11)? data_i[166] :
(N13)? data_i[230] :
(N8)? data_i[294] :
(N10)? data_i[358] :
(N12)? data_i[422] :
(N14)? data_i[486] : 1'b0;
assign data_o[37] = (N7)? data_i[37] :
(N9)? data_i[101] :
(N11)? data_i[165] :
(N13)? data_i[229] :
(N8)? data_i[293] :
(N10)? data_i[357] :
(N12)? data_i[421] :
(N14)? data_i[485] : 1'b0;
assign data_o[36] = (N7)? data_i[36] :
(N9)? data_i[100] :
(N11)? data_i[164] :
(N13)? data_i[228] :
(N8)? data_i[292] :
(N10)? data_i[356] :
(N12)? data_i[420] :
(N14)? data_i[484] : 1'b0;
assign data_o[35] = (N7)? data_i[35] :
(N9)? data_i[99] :
(N11)? data_i[163] :
(N13)? data_i[227] :
(N8)? data_i[291] :
(N10)? data_i[355] :
(N12)? data_i[419] :
(N14)? data_i[483] : 1'b0;
assign data_o[34] = (N7)? data_i[34] :
(N9)? data_i[98] :
(N11)? data_i[162] :
(N13)? data_i[226] :
(N8)? data_i[290] :
(N10)? data_i[354] :
(N12)? data_i[418] :
(N14)? data_i[482] : 1'b0;
assign data_o[33] = (N7)? data_i[33] :
(N9)? data_i[97] :
(N11)? data_i[161] :
(N13)? data_i[225] :
(N8)? data_i[289] :
(N10)? data_i[353] :
(N12)? data_i[417] :
(N14)? data_i[481] : 1'b0;
assign data_o[32] = (N7)? data_i[32] :
(N9)? data_i[96] :
(N11)? data_i[160] :
(N13)? data_i[224] :
(N8)? data_i[288] :
(N10)? data_i[352] :
(N12)? data_i[416] :
(N14)? data_i[480] : 1'b0;
assign data_o[31] = (N7)? data_i[31] :
(N9)? data_i[95] :
(N11)? data_i[159] :
(N13)? data_i[223] :
(N8)? data_i[287] :
(N10)? data_i[351] :
(N12)? data_i[415] :
(N14)? data_i[479] : 1'b0;
assign data_o[30] = (N7)? data_i[30] :
(N9)? data_i[94] :
(N11)? data_i[158] :
(N13)? data_i[222] :
(N8)? data_i[286] :
(N10)? data_i[350] :
(N12)? data_i[414] :
(N14)? data_i[478] : 1'b0;
assign data_o[29] = (N7)? data_i[29] :
(N9)? data_i[93] :
(N11)? data_i[157] :
(N13)? data_i[221] :
(N8)? data_i[285] :
(N10)? data_i[349] :
(N12)? data_i[413] :
(N14)? data_i[477] : 1'b0;
assign data_o[28] = (N7)? data_i[28] :
(N9)? data_i[92] :
(N11)? data_i[156] :
(N13)? data_i[220] :
(N8)? data_i[284] :
(N10)? data_i[348] :
(N12)? data_i[412] :
(N14)? data_i[476] : 1'b0;
assign data_o[27] = (N7)? data_i[27] :
(N9)? data_i[91] :
(N11)? data_i[155] :
(N13)? data_i[219] :
(N8)? data_i[283] :
(N10)? data_i[347] :
(N12)? data_i[411] :
(N14)? data_i[475] : 1'b0;
assign data_o[26] = (N7)? data_i[26] :
(N9)? data_i[90] :
(N11)? data_i[154] :
(N13)? data_i[218] :
(N8)? data_i[282] :
(N10)? data_i[346] :
(N12)? data_i[410] :
(N14)? data_i[474] : 1'b0;
assign data_o[25] = (N7)? data_i[25] :
(N9)? data_i[89] :
(N11)? data_i[153] :
(N13)? data_i[217] :
(N8)? data_i[281] :
(N10)? data_i[345] :
(N12)? data_i[409] :
(N14)? data_i[473] : 1'b0;
assign data_o[24] = (N7)? data_i[24] :
(N9)? data_i[88] :
(N11)? data_i[152] :
(N13)? data_i[216] :
(N8)? data_i[280] :
(N10)? data_i[344] :
(N12)? data_i[408] :
(N14)? data_i[472] : 1'b0;
assign data_o[23] = (N7)? data_i[23] :
(N9)? data_i[87] :
(N11)? data_i[151] :
(N13)? data_i[215] :
(N8)? data_i[279] :
(N10)? data_i[343] :
(N12)? data_i[407] :
(N14)? data_i[471] : 1'b0;
assign data_o[22] = (N7)? data_i[22] :
(N9)? data_i[86] :
(N11)? data_i[150] :
(N13)? data_i[214] :
(N8)? data_i[278] :
(N10)? data_i[342] :
(N12)? data_i[406] :
(N14)? data_i[470] : 1'b0;
assign data_o[21] = (N7)? data_i[21] :
(N9)? data_i[85] :
(N11)? data_i[149] :
(N13)? data_i[213] :
(N8)? data_i[277] :
(N10)? data_i[341] :
(N12)? data_i[405] :
(N14)? data_i[469] : 1'b0;
assign data_o[20] = (N7)? data_i[20] :
(N9)? data_i[84] :
(N11)? data_i[148] :
(N13)? data_i[212] :
(N8)? data_i[276] :
(N10)? data_i[340] :
(N12)? data_i[404] :
(N14)? data_i[468] : 1'b0;
assign data_o[19] = (N7)? data_i[19] :
(N9)? data_i[83] :
(N11)? data_i[147] :
(N13)? data_i[211] :
(N8)? data_i[275] :
(N10)? data_i[339] :
(N12)? data_i[403] :
(N14)? data_i[467] : 1'b0;
assign data_o[18] = (N7)? data_i[18] :
(N9)? data_i[82] :
(N11)? data_i[146] :
(N13)? data_i[210] :
(N8)? data_i[274] :
(N10)? data_i[338] :
(N12)? data_i[402] :
(N14)? data_i[466] : 1'b0;
assign data_o[17] = (N7)? data_i[17] :
(N9)? data_i[81] :
(N11)? data_i[145] :
(N13)? data_i[209] :
(N8)? data_i[273] :
(N10)? data_i[337] :
(N12)? data_i[401] :
(N14)? data_i[465] : 1'b0;
assign data_o[16] = (N7)? data_i[16] :
(N9)? data_i[80] :
(N11)? data_i[144] :
(N13)? data_i[208] :
(N8)? data_i[272] :
(N10)? data_i[336] :
(N12)? data_i[400] :
(N14)? data_i[464] : 1'b0;
assign data_o[15] = (N7)? data_i[15] :
(N9)? data_i[79] :
(N11)? data_i[143] :
(N13)? data_i[207] :
(N8)? data_i[271] :
(N10)? data_i[335] :
(N12)? data_i[399] :
(N14)? data_i[463] : 1'b0;
assign data_o[14] = (N7)? data_i[14] :
(N9)? data_i[78] :
(N11)? data_i[142] :
(N13)? data_i[206] :
(N8)? data_i[270] :
(N10)? data_i[334] :
(N12)? data_i[398] :
(N14)? data_i[462] : 1'b0;
assign data_o[13] = (N7)? data_i[13] :
(N9)? data_i[77] :
(N11)? data_i[141] :
(N13)? data_i[205] :
(N8)? data_i[269] :
(N10)? data_i[333] :
(N12)? data_i[397] :
(N14)? data_i[461] : 1'b0;
assign data_o[12] = (N7)? data_i[12] :
(N9)? data_i[76] :
(N11)? data_i[140] :
(N13)? data_i[204] :
(N8)? data_i[268] :
(N10)? data_i[332] :
(N12)? data_i[396] :
(N14)? data_i[460] : 1'b0;
assign data_o[11] = (N7)? data_i[11] :
(N9)? data_i[75] :
(N11)? data_i[139] :
(N13)? data_i[203] :
(N8)? data_i[267] :
(N10)? data_i[331] :
(N12)? data_i[395] :
(N14)? data_i[459] : 1'b0;
assign data_o[10] = (N7)? data_i[10] :
(N9)? data_i[74] :
(N11)? data_i[138] :
(N13)? data_i[202] :
(N8)? data_i[266] :
(N10)? data_i[330] :
(N12)? data_i[394] :
(N14)? data_i[458] : 1'b0;
assign data_o[9] = (N7)? data_i[9] :
(N9)? data_i[73] :
(N11)? data_i[137] :
(N13)? data_i[201] :
(N8)? data_i[265] :
(N10)? data_i[329] :
(N12)? data_i[393] :
(N14)? data_i[457] : 1'b0;
assign data_o[8] = (N7)? data_i[8] :
(N9)? data_i[72] :
(N11)? data_i[136] :
(N13)? data_i[200] :
(N8)? data_i[264] :
(N10)? data_i[328] :
(N12)? data_i[392] :
(N14)? data_i[456] : 1'b0;
assign data_o[7] = (N7)? data_i[7] :
(N9)? data_i[71] :
(N11)? data_i[135] :
(N13)? data_i[199] :
(N8)? data_i[263] :
(N10)? data_i[327] :
(N12)? data_i[391] :
(N14)? data_i[455] : 1'b0;
assign data_o[6] = (N7)? data_i[6] :
(N9)? data_i[70] :
(N11)? data_i[134] :
(N13)? data_i[198] :
(N8)? data_i[262] :
(N10)? data_i[326] :
(N12)? data_i[390] :
(N14)? data_i[454] : 1'b0;
assign data_o[5] = (N7)? data_i[5] :
(N9)? data_i[69] :
(N11)? data_i[133] :
(N13)? data_i[197] :
(N8)? data_i[261] :
(N10)? data_i[325] :
(N12)? data_i[389] :
(N14)? data_i[453] : 1'b0;
assign data_o[4] = (N7)? data_i[4] :
(N9)? data_i[68] :
(N11)? data_i[132] :
(N13)? data_i[196] :
(N8)? data_i[260] :
(N10)? data_i[324] :
(N12)? data_i[388] :
(N14)? data_i[452] : 1'b0;
assign data_o[3] = (N7)? data_i[3] :
(N9)? data_i[67] :
(N11)? data_i[131] :
(N13)? data_i[195] :
(N8)? data_i[259] :
(N10)? data_i[323] :
(N12)? data_i[387] :
(N14)? data_i[451] : 1'b0;
assign data_o[2] = (N7)? data_i[2] :
(N9)? data_i[66] :
(N11)? data_i[130] :
(N13)? data_i[194] :
(N8)? data_i[258] :
(N10)? data_i[322] :
(N12)? data_i[386] :
(N14)? data_i[450] : 1'b0;
assign data_o[1] = (N7)? data_i[1] :
(N9)? data_i[65] :
(N11)? data_i[129] :
(N13)? data_i[193] :
(N8)? data_i[257] :
(N10)? data_i[321] :
(N12)? data_i[385] :
(N14)? data_i[449] : 1'b0;
assign data_o[0] = (N7)? data_i[0] :
(N9)? data_i[64] :
(N11)? data_i[128] :
(N13)? data_i[192] :
(N8)? data_i[256] :
(N10)? data_i[320] :
(N12)? data_i[384] :
(N14)? data_i[448] : 1'b0;
assign N0 = ~sel_i[0];
assign N1 = ~sel_i[1];
assign N2 = N0 & N1;
assign N3 = N0 & sel_i[1];
assign N4 = sel_i[0] & N1;
assign N5 = sel_i[0] & sel_i[1];
assign N6 = ~sel_i[2];
assign N7 = N2 & N6;
assign N8 = N2 & sel_i[2];
assign N9 = N4 & N6;
assign N10 = N4 & sel_i[2];
assign N11 = N3 & N6;
assign N12 = N3 & sel_i[2];
assign N13 = N5 & N6;
assign N14 = N5 & sel_i[2];
endmodule
|
module bsg_scan_width_p8_or_p1_lo_to_hi_p1
(
i,
o
);
input [7:0] i;
output [7:0] o;
wire [7:0] o;
wire t_2__7_,t_2__6_,t_2__5_,t_2__4_,t_2__3_,t_2__2_,t_2__1_,t_2__0_,t_1__7_,t_1__6_,
t_1__5_,t_1__4_,t_1__3_,t_1__2_,t_1__1_,t_1__0_;
assign t_1__7_ = i[0] | 1'b0;
assign t_1__6_ = i[1] | i[0];
assign t_1__5_ = i[2] | i[1];
assign t_1__4_ = i[3] | i[2];
assign t_1__3_ = i[4] | i[3];
assign t_1__2_ = i[5] | i[4];
assign t_1__1_ = i[6] | i[5];
assign t_1__0_ = i[7] | i[6];
assign t_2__7_ = t_1__7_ | 1'b0;
assign t_2__6_ = t_1__6_ | 1'b0;
assign t_2__5_ = t_1__5_ | t_1__7_;
assign t_2__4_ = t_1__4_ | t_1__6_;
assign t_2__3_ = t_1__3_ | t_1__5_;
assign t_2__2_ = t_1__2_ | t_1__4_;
assign t_2__1_ = t_1__1_ | t_1__3_;
assign t_2__0_ = t_1__0_ | t_1__2_;
assign o[0] = t_2__7_ | 1'b0;
assign o[1] = t_2__6_ | 1'b0;
assign o[2] = t_2__5_ | 1'b0;
assign o[3] = t_2__4_ | 1'b0;
assign o[4] = t_2__3_ | t_2__7_;
assign o[5] = t_2__2_ | t_2__6_;
assign o[6] = t_2__1_ | t_2__5_;
assign o[7] = t_2__0_ | t_2__4_;
endmodule
|
module itlb_vaddr_width_p56_paddr_width_p22_eaddr_width_p64_btb_indx_width_p9_bht_indx_width_p5_ras_addr_width_p22_asid_width_p10_ppn_start_bit_p12_tag_width_p10
(
clk_i,
reset_i,
fe_itlb_i,
fe_itlb_v_i,
fe_itlb_ready_o,
pc_gen_itlb_i,
pc_gen_itlb_v_i,
pc_gen_itlb_ready_o,
itlb_icache_o,
itlb_icache_data_resp_v_o,
itlb_icache_data_resp_ready_i,
itlb_fe_o,
itlb_fe_v_o,
itlb_fe_ready_i
);
input [108:0] fe_itlb_i;
input [63:0] pc_gen_itlb_i;
output [9:0] itlb_icache_o;
output [133:0] itlb_fe_o;
input clk_i;
input reset_i;
input fe_itlb_v_i;
input pc_gen_itlb_v_i;
input itlb_icache_data_resp_ready_i;
input itlb_fe_ready_i;
output fe_itlb_ready_o;
output pc_gen_itlb_ready_o;
output itlb_icache_data_resp_v_o;
output itlb_fe_v_o;
wire [133:0] itlb_fe_o;
wire fe_itlb_ready_o,pc_gen_itlb_ready_o,itlb_icache_data_resp_v_o,itlb_fe_v_o;
reg [9:0] itlb_icache_o;
assign pc_gen_itlb_ready_o = 1'b1;
assign itlb_icache_data_resp_v_o = 1'b1;
assign fe_itlb_ready_o = 1'b0;
assign itlb_fe_v_o = 1'b0;
always @(posedge clk_i) begin
if(1'b1) begin
{ itlb_icache_o[9:0] } <= { pc_gen_itlb_i[21:12] };
end
end
endmodule
|
module bsg_mem_1r1w_synth_width_p36_els_p2_read_write_same_addr_p0_harden_p0
(
w_clk_i,
w_reset_i,
w_v_i,
w_addr_i,
w_data_i,
r_v_i,
r_addr_i,
r_data_o
);
input [0:0] w_addr_i;
input [35:0] w_data_i;
input [0:0] r_addr_i;
output [35:0] r_data_o;
input w_clk_i;
input w_reset_i;
input w_v_i;
input r_v_i;
wire [35:0] r_data_o;
wire N0,N1,N2,N3,N4,N5,N7,N8;
reg [71:0] mem;
assign r_data_o[35] = (N3)? mem[35] :
(N0)? mem[71] : 1'b0;
assign N0 = r_addr_i[0];
assign r_data_o[34] = (N3)? mem[34] :
(N0)? mem[70] : 1'b0;
assign r_data_o[33] = (N3)? mem[33] :
(N0)? mem[69] : 1'b0;
assign r_data_o[32] = (N3)? mem[32] :
(N0)? mem[68] : 1'b0;
assign r_data_o[31] = (N3)? mem[31] :
(N0)? mem[67] : 1'b0;
assign r_data_o[30] = (N3)? mem[30] :
(N0)? mem[66] : 1'b0;
assign r_data_o[29] = (N3)? mem[29] :
(N0)? mem[65] : 1'b0;
assign r_data_o[28] = (N3)? mem[28] :
(N0)? mem[64] : 1'b0;
assign r_data_o[27] = (N3)? mem[27] :
(N0)? mem[63] : 1'b0;
assign r_data_o[26] = (N3)? mem[26] :
(N0)? mem[62] : 1'b0;
assign r_data_o[25] = (N3)? mem[25] :
(N0)? mem[61] : 1'b0;
assign r_data_o[24] = (N3)? mem[24] :
(N0)? mem[60] : 1'b0;
assign r_data_o[23] = (N3)? mem[23] :
(N0)? mem[59] : 1'b0;
assign r_data_o[22] = (N3)? mem[22] :
(N0)? mem[58] : 1'b0;
assign r_data_o[21] = (N3)? mem[21] :
(N0)? mem[57] : 1'b0;
assign r_data_o[20] = (N3)? mem[20] :
(N0)? mem[56] : 1'b0;
assign r_data_o[19] = (N3)? mem[19] :
(N0)? mem[55] : 1'b0;
assign r_data_o[18] = (N3)? mem[18] :
(N0)? mem[54] : 1'b0;
assign r_data_o[17] = (N3)? mem[17] :
(N0)? mem[53] : 1'b0;
assign r_data_o[16] = (N3)? mem[16] :
(N0)? mem[52] : 1'b0;
assign r_data_o[15] = (N3)? mem[15] :
(N0)? mem[51] : 1'b0;
assign r_data_o[14] = (N3)? mem[14] :
(N0)? mem[50] : 1'b0;
assign r_data_o[13] = (N3)? mem[13] :
(N0)? mem[49] : 1'b0;
assign r_data_o[12] = (N3)? mem[12] :
(N0)? mem[48] : 1'b0;
assign r_data_o[11] = (N3)? mem[11] :
(N0)? mem[47] : 1'b0;
assign r_data_o[10] = (N3)? mem[10] :
(N0)? mem[46] : 1'b0;
assign r_data_o[9] = (N3)? mem[9] :
(N0)? mem[45] : 1'b0;
assign r_data_o[8] = (N3)? mem[8] :
(N0)? mem[44] : 1'b0;
assign r_data_o[7] = (N3)? mem[7] :
(N0)? mem[43] : 1'b0;
assign r_data_o[6] = (N3)? mem[6] :
(N0)? mem[42] : 1'b0;
assign r_data_o[5] = (N3)? mem[5] :
(N0)? mem[41] : 1'b0;
assign r_data_o[4] = (N3)? mem[4] :
(N0)? mem[40] : 1'b0;
assign r_data_o[3] = (N3)? mem[3] :
(N0)? mem[39] : 1'b0;
assign r_data_o[2] = (N3)? mem[2] :
(N0)? mem[38] : 1'b0;
assign r_data_o[1] = (N3)? mem[1] :
(N0)? mem[37] : 1'b0;
assign r_data_o[0] = (N3)? mem[0] :
(N0)? mem[36] : 1'b0;
assign N5 = ~w_addr_i[0];
assign { N8, N7 } = (N1)? { w_addr_i[0:0], N5 } :
(N2)? { 1'b0, 1'b0 } : 1'b0;
assign N1 = w_v_i;
assign N2 = N4;
assign N3 = ~r_addr_i[0];
assign N4 = ~w_v_i;
always @(posedge w_clk_i) begin
if(N8) begin
{ mem[71:36] } <= { w_data_i[35:0] };
end
if(N7) begin
{ mem[35:0] } <= { w_data_i[35:0] };
end
end
endmodule
|
module instr_scan_eaddr_width_p64_instr_width_p32
(
instr_i,
scan_o
);
input [31:0] instr_i;
output [68:0] scan_o;
wire [68:0] scan_o;
wire N0,N1,N2,N3,N4,N5,N6,N7,N9,N10,N11,N12,N13,N14,N15,N16,N17,N18,N19,N20,N21,N22,
N23,N24,N25,N26,N27,N28,N29,N30;
assign scan_o[66] = 1'b0;
assign scan_o[67] = 1'b0;
assign N7 = instr_i[0] & instr_i[1];
assign scan_o[68] = ~N7;
assign N9 = ~instr_i[6];
assign N10 = ~instr_i[5];
assign N11 = ~instr_i[3];
assign N12 = ~instr_i[2];
assign N13 = ~instr_i[1];
assign N14 = ~instr_i[0];
assign N15 = N10 | N9;
assign N16 = instr_i[4] | N15;
assign N17 = N11 | N16;
assign N18 = N12 | N17;
assign N19 = N13 | N18;
assign N20 = N14 | N19;
assign N21 = ~N20;
assign N22 = instr_i[3] | N16;
assign N23 = N12 | N22;
assign N24 = N13 | N23;
assign N25 = N14 | N24;
assign N26 = ~N25;
assign N27 = instr_i[2] | N22;
assign N28 = N13 | N27;
assign N29 = N14 | N28;
assign N30 = ~N29;
assign scan_o[65:64] = (N0)? { 1'b0, 1'b0 } :
(N1)? { 1'b0, 1'b1 } :
(N4)? { 1'b1, N20 } : 1'b0;
assign N0 = N30;
assign N1 = N26;
assign scan_o[63:0] = (N0)? { instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[7:7], instr_i[30:25], instr_i[11:8], 1'b0 } :
(N1)? { instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:20] } :
(N2)? { instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[19:12], instr_i[20:20], instr_i[30:21], 1'b0 } :
(N6)? { 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0 } : 1'b0;
assign N2 = N21;
assign N3 = N26 | N30;
assign N4 = ~N3;
assign N5 = N21 | N3;
assign N6 = ~N5;
endmodule
|
module bp_be_dcache_lru_encode_ways_p8
(
lru_i,
way_id_o
);
input [6:0] lru_i;
output [2:0] way_id_o;
wire [2:0] way_id_o;
wire N0,N1,N2,N3,N4,N5,N6,N7,N8,N9,N10,N11,N12,N13,N14,N15,N16,N17,N18,N19,N20,N21,
N22,N23,N24,N25,N26,N27,N28,N29,N30;
assign N11 = N8 & N9;
assign N12 = N11 & N10;
assign N13 = lru_i[3] & N9;
assign N14 = N13 & N10;
assign N16 = N15 & lru_i[1];
assign N17 = N16 & N10;
assign N18 = lru_i[4] & lru_i[1];
assign N19 = N18 & N10;
assign N22 = N20 & N21;
assign N23 = N22 & lru_i[0];
assign N24 = lru_i[5] & N21;
assign N25 = N24 & lru_i[0];
assign N27 = N26 & lru_i[2];
assign N28 = N27 & lru_i[0];
assign N29 = lru_i[6] & lru_i[2];
assign N30 = N29 & lru_i[0];
assign way_id_o = (N0)? { 1'b0, 1'b0, 1'b0 } :
(N1)? { 1'b0, 1'b0, 1'b1 } :
(N2)? { 1'b0, 1'b1, 1'b0 } :
(N3)? { 1'b0, 1'b1, 1'b1 } :
(N4)? { 1'b1, 1'b0, 1'b0 } :
(N5)? { 1'b1, 1'b0, 1'b1 } :
(N6)? { 1'b1, 1'b1, 1'b0 } :
(N7)? { 1'b1, 1'b1, 1'b1 } : 1'b0;
assign N0 = N12;
assign N1 = N14;
assign N2 = N17;
assign N3 = N19;
assign N4 = N23;
assign N5 = N25;
assign N6 = N28;
assign N7 = N30;
assign N8 = ~lru_i[3];
assign N9 = ~lru_i[1];
assign N10 = ~lru_i[0];
assign N15 = ~lru_i[4];
assign N20 = ~lru_i[5];
assign N21 = ~lru_i[2];
assign N26 = ~lru_i[6];
endmodule
|
module bp_fe_lce_data_cmd_data_width_p64_lce_addr_width_p22_lce_data_width_p512_num_cce_p1_num_lce_p2_lce_sets_p64_ways_p8_block_size_in_bytes_p8
(
cce_data_received_o,
lce_data_cmd_i,
lce_data_cmd_v_i,
lce_data_cmd_yumi_o,
data_mem_pkt_v_o,
data_mem_pkt_o,
data_mem_pkt_yumi_i
);
input [539:0] lce_data_cmd_i;
output [521:0] data_mem_pkt_o;
input lce_data_cmd_v_i;
input data_mem_pkt_yumi_i;
output cce_data_received_o;
output lce_data_cmd_yumi_o;
output data_mem_pkt_v_o;
wire [521:0] data_mem_pkt_o;
wire cce_data_received_o,lce_data_cmd_yumi_o,data_mem_pkt_v_o,data_mem_pkt_yumi_i,
lce_data_cmd_v_i;
assign data_mem_pkt_o[512] = 1'b1;
assign lce_data_cmd_yumi_o = data_mem_pkt_yumi_i;
assign data_mem_pkt_v_o = lce_data_cmd_v_i;
assign data_mem_pkt_o[521] = lce_data_cmd_i[523];
assign data_mem_pkt_o[520] = lce_data_cmd_i[522];
assign data_mem_pkt_o[519] = lce_data_cmd_i[521];
assign data_mem_pkt_o[518] = lce_data_cmd_i[520];
assign data_mem_pkt_o[517] = lce_data_cmd_i[519];
assign data_mem_pkt_o[516] = lce_data_cmd_i[518];
assign data_mem_pkt_o[515] = lce_data_cmd_i[536];
assign data_mem_pkt_o[514] = lce_data_cmd_i[535];
assign data_mem_pkt_o[513] = lce_data_cmd_i[534];
assign data_mem_pkt_o[511] = lce_data_cmd_i[511];
assign data_mem_pkt_o[510] = lce_data_cmd_i[510];
assign data_mem_pkt_o[509] = lce_data_cmd_i[509];
assign data_mem_pkt_o[508] = lce_data_cmd_i[508];
assign data_mem_pkt_o[507] = lce_data_cmd_i[507];
assign data_mem_pkt_o[506] = lce_data_cmd_i[506];
assign data_mem_pkt_o[505] = lce_data_cmd_i[505];
assign data_mem_pkt_o[504] = lce_data_cmd_i[504];
assign data_mem_pkt_o[503] = lce_data_cmd_i[503];
assign data_mem_pkt_o[502] = lce_data_cmd_i[502];
assign data_mem_pkt_o[501] = lce_data_cmd_i[501];
assign data_mem_pkt_o[500] = lce_data_cmd_i[500];
assign data_mem_pkt_o[499] = lce_data_cmd_i[499];
assign data_mem_pkt_o[498] = lce_data_cmd_i[498];
assign data_mem_pkt_o[497] = lce_data_cmd_i[497];
assign data_mem_pkt_o[496] = lce_data_cmd_i[496];
assign data_mem_pkt_o[495] = lce_data_cmd_i[495];
assign data_mem_pkt_o[494] = lce_data_cmd_i[494];
assign data_mem_pkt_o[493] = lce_data_cmd_i[493];
assign data_mem_pkt_o[492] = lce_data_cmd_i[492];
assign data_mem_pkt_o[491] = lce_data_cmd_i[491];
assign data_mem_pkt_o[490] = lce_data_cmd_i[490];
assign data_mem_pkt_o[489] = lce_data_cmd_i[489];
assign data_mem_pkt_o[488] = lce_data_cmd_i[488];
assign data_mem_pkt_o[487] = lce_data_cmd_i[487];
assign data_mem_pkt_o[486] = lce_data_cmd_i[486];
assign data_mem_pkt_o[485] = lce_data_cmd_i[485];
assign data_mem_pkt_o[484] = lce_data_cmd_i[484];
assign data_mem_pkt_o[483] = lce_data_cmd_i[483];
assign data_mem_pkt_o[482] = lce_data_cmd_i[482];
assign data_mem_pkt_o[481] = lce_data_cmd_i[481];
assign data_mem_pkt_o[480] = lce_data_cmd_i[480];
assign data_mem_pkt_o[479] = lce_data_cmd_i[479];
assign data_mem_pkt_o[478] = lce_data_cmd_i[478];
assign data_mem_pkt_o[477] = lce_data_cmd_i[477];
assign data_mem_pkt_o[476] = lce_data_cmd_i[476];
assign data_mem_pkt_o[475] = lce_data_cmd_i[475];
assign data_mem_pkt_o[474] = lce_data_cmd_i[474];
assign data_mem_pkt_o[473] = lce_data_cmd_i[473];
assign data_mem_pkt_o[472] = lce_data_cmd_i[472];
assign data_mem_pkt_o[471] = lce_data_cmd_i[471];
assign data_mem_pkt_o[470] = lce_data_cmd_i[470];
assign data_mem_pkt_o[469] = lce_data_cmd_i[469];
assign data_mem_pkt_o[468] = lce_data_cmd_i[468];
assign data_mem_pkt_o[467] = lce_data_cmd_i[467];
assign data_mem_pkt_o[466] = lce_data_cmd_i[466];
assign data_mem_pkt_o[465] = lce_data_cmd_i[465];
assign data_mem_pkt_o[464] = lce_data_cmd_i[464];
assign data_mem_pkt_o[463] = lce_data_cmd_i[463];
assign data_mem_pkt_o[462] = lce_data_cmd_i[462];
assign data_mem_pkt_o[461] = lce_data_cmd_i[461];
assign data_mem_pkt_o[460] = lce_data_cmd_i[460];
assign data_mem_pkt_o[459] = lce_data_cmd_i[459];
assign data_mem_pkt_o[458] = lce_data_cmd_i[458];
assign data_mem_pkt_o[457] = lce_data_cmd_i[457];
assign data_mem_pkt_o[456] = lce_data_cmd_i[456];
assign data_mem_pkt_o[455] = lce_data_cmd_i[455];
assign data_mem_pkt_o[454] = lce_data_cmd_i[454];
assign data_mem_pkt_o[453] = lce_data_cmd_i[453];
assign data_mem_pkt_o[452] = lce_data_cmd_i[452];
assign data_mem_pkt_o[451] = lce_data_cmd_i[451];
assign data_mem_pkt_o[450] = lce_data_cmd_i[450];
assign data_mem_pkt_o[449] = lce_data_cmd_i[449];
assign data_mem_pkt_o[448] = lce_data_cmd_i[448];
assign data_mem_pkt_o[447] = lce_data_cmd_i[447];
assign data_mem_pkt_o[446] = lce_data_cmd_i[446];
assign data_mem_pkt_o[445] = lce_data_cmd_i[445];
assign data_mem_pkt_o[444] = lce_data_cmd_i[444];
assign data_mem_pkt_o[443] = lce_data_cmd_i[443];
assign data_mem_pkt_o[442] = lce_data_cmd_i[442];
assign data_mem_pkt_o[441] = lce_data_cmd_i[441];
assign data_mem_pkt_o[440] = lce_data_cmd_i[440];
assign data_mem_pkt_o[439] = lce_data_cmd_i[439];
assign data_mem_pkt_o[438] = lce_data_cmd_i[438];
assign data_mem_pkt_o[437] = lce_data_cmd_i[437];
assign data_mem_pkt_o[436] = lce_data_cmd_i[436];
assign data_mem_pkt_o[435] = lce_data_cmd_i[435];
assign data_mem_pkt_o[434] = lce_data_cmd_i[434];
assign data_mem_pkt_o[433] = lce_data_cmd_i[433];
assign data_mem_pkt_o[432] = lce_data_cmd_i[432];
assign data_mem_pkt_o[431] = lce_data_cmd_i[431];
assign data_mem_pkt_o[430] = lce_data_cmd_i[430];
assign data_mem_pkt_o[429] = lce_data_cmd_i[429];
assign data_mem_pkt_o[428] = lce_data_cmd_i[428];
assign data_mem_pkt_o[427] = lce_data_cmd_i[427];
assign data_mem_pkt_o[426] = lce_data_cmd_i[426];
assign data_mem_pkt_o[425] = lce_data_cmd_i[425];
assign data_mem_pkt_o[424] = lce_data_cmd_i[424];
assign data_mem_pkt_o[423] = lce_data_cmd_i[423];
assign data_mem_pkt_o[422] = lce_data_cmd_i[422];
assign data_mem_pkt_o[421] = lce_data_cmd_i[421];
assign data_mem_pkt_o[420] = lce_data_cmd_i[420];
assign data_mem_pkt_o[419] = lce_data_cmd_i[419];
assign data_mem_pkt_o[418] = lce_data_cmd_i[418];
assign data_mem_pkt_o[417] = lce_data_cmd_i[417];
assign data_mem_pkt_o[416] = lce_data_cmd_i[416];
assign data_mem_pkt_o[415] = lce_data_cmd_i[415];
assign data_mem_pkt_o[414] = lce_data_cmd_i[414];
assign data_mem_pkt_o[413] = lce_data_cmd_i[413];
assign data_mem_pkt_o[412] = lce_data_cmd_i[412];
assign data_mem_pkt_o[411] = lce_data_cmd_i[411];
assign data_mem_pkt_o[410] = lce_data_cmd_i[410];
assign data_mem_pkt_o[409] = lce_data_cmd_i[409];
assign data_mem_pkt_o[408] = lce_data_cmd_i[408];
assign data_mem_pkt_o[407] = lce_data_cmd_i[407];
assign data_mem_pkt_o[406] = lce_data_cmd_i[406];
assign data_mem_pkt_o[405] = lce_data_cmd_i[405];
assign data_mem_pkt_o[404] = lce_data_cmd_i[404];
assign data_mem_pkt_o[403] = lce_data_cmd_i[403];
assign data_mem_pkt_o[402] = lce_data_cmd_i[402];
assign data_mem_pkt_o[401] = lce_data_cmd_i[401];
assign data_mem_pkt_o[400] = lce_data_cmd_i[400];
assign data_mem_pkt_o[399] = lce_data_cmd_i[399];
assign data_mem_pkt_o[398] = lce_data_cmd_i[398];
assign data_mem_pkt_o[397] = lce_data_cmd_i[397];
assign data_mem_pkt_o[396] = lce_data_cmd_i[396];
assign data_mem_pkt_o[395] = lce_data_cmd_i[395];
assign data_mem_pkt_o[394] = lce_data_cmd_i[394];
assign data_mem_pkt_o[393] = lce_data_cmd_i[393];
assign data_mem_pkt_o[392] = lce_data_cmd_i[392];
assign data_mem_pkt_o[391] = lce_data_cmd_i[391];
assign data_mem_pkt_o[390] = lce_data_cmd_i[390];
assign data_mem_pkt_o[389] = lce_data_cmd_i[389];
assign data_mem_pkt_o[388] = lce_data_cmd_i[388];
assign data_mem_pkt_o[387] = lce_data_cmd_i[387];
assign data_mem_pkt_o[386] = lce_data_cmd_i[386];
assign data_mem_pkt_o[385] = lce_data_cmd_i[385];
assign data_mem_pkt_o[384] = lce_data_cmd_i[384];
assign data_mem_pkt_o[383] = lce_data_cmd_i[383];
assign data_mem_pkt_o[382] = lce_data_cmd_i[382];
assign data_mem_pkt_o[381] = lce_data_cmd_i[381];
assign data_mem_pkt_o[380] = lce_data_cmd_i[380];
assign data_mem_pkt_o[379] = lce_data_cmd_i[379];
assign data_mem_pkt_o[378] = lce_data_cmd_i[378];
assign data_mem_pkt_o[377] = lce_data_cmd_i[377];
assign data_mem_pkt_o[376] = lce_data_cmd_i[376];
assign data_mem_pkt_o[375] = lce_data_cmd_i[375];
assign data_mem_pkt_o[374] = lce_data_cmd_i[374];
assign data_mem_pkt_o[373] = lce_data_cmd_i[373];
assign data_mem_pkt_o[372] = lce_data_cmd_i[372];
assign data_mem_pkt_o[371] = lce_data_cmd_i[371];
assign data_mem_pkt_o[370] = lce_data_cmd_i[370];
assign data_mem_pkt_o[369] = lce_data_cmd_i[369];
assign data_mem_pkt_o[368] = lce_data_cmd_i[368];
assign data_mem_pkt_o[367] = lce_data_cmd_i[367];
assign data_mem_pkt_o[366] = lce_data_cmd_i[366];
assign data_mem_pkt_o[365] = lce_data_cmd_i[365];
assign data_mem_pkt_o[364] = lce_data_cmd_i[364];
assign data_mem_pkt_o[363] = lce_data_cmd_i[363];
assign data_mem_pkt_o[362] = lce_data_cmd_i[362];
assign data_mem_pkt_o[361] = lce_data_cmd_i[361];
assign data_mem_pkt_o[360] = lce_data_cmd_i[360];
assign data_mem_pkt_o[359] = lce_data_cmd_i[359];
assign data_mem_pkt_o[358] = lce_data_cmd_i[358];
assign data_mem_pkt_o[357] = lce_data_cmd_i[357];
assign data_mem_pkt_o[356] = lce_data_cmd_i[356];
assign data_mem_pkt_o[355] = lce_data_cmd_i[355];
assign data_mem_pkt_o[354] = lce_data_cmd_i[354];
assign data_mem_pkt_o[353] = lce_data_cmd_i[353];
assign data_mem_pkt_o[352] = lce_data_cmd_i[352];
assign data_mem_pkt_o[351] = lce_data_cmd_i[351];
assign data_mem_pkt_o[350] = lce_data_cmd_i[350];
assign data_mem_pkt_o[349] = lce_data_cmd_i[349];
assign data_mem_pkt_o[348] = lce_data_cmd_i[348];
assign data_mem_pkt_o[347] = lce_data_cmd_i[347];
assign data_mem_pkt_o[346] = lce_data_cmd_i[346];
assign data_mem_pkt_o[345] = lce_data_cmd_i[345];
assign data_mem_pkt_o[344] = lce_data_cmd_i[344];
assign data_mem_pkt_o[343] = lce_data_cmd_i[343];
assign data_mem_pkt_o[342] = lce_data_cmd_i[342];
assign data_mem_pkt_o[341] = lce_data_cmd_i[341];
assign data_mem_pkt_o[340] = lce_data_cmd_i[340];
assign data_mem_pkt_o[339] = lce_data_cmd_i[339];
assign data_mem_pkt_o[338] = lce_data_cmd_i[338];
assign data_mem_pkt_o[337] = lce_data_cmd_i[337];
assign data_mem_pkt_o[336] = lce_data_cmd_i[336];
assign data_mem_pkt_o[335] = lce_data_cmd_i[335];
assign data_mem_pkt_o[334] = lce_data_cmd_i[334];
assign data_mem_pkt_o[333] = lce_data_cmd_i[333];
assign data_mem_pkt_o[332] = lce_data_cmd_i[332];
assign data_mem_pkt_o[331] = lce_data_cmd_i[331];
assign data_mem_pkt_o[330] = lce_data_cmd_i[330];
assign data_mem_pkt_o[329] = lce_data_cmd_i[329];
assign data_mem_pkt_o[328] = lce_data_cmd_i[328];
assign data_mem_pkt_o[327] = lce_data_cmd_i[327];
assign data_mem_pkt_o[326] = lce_data_cmd_i[326];
assign data_mem_pkt_o[325] = lce_data_cmd_i[325];
assign data_mem_pkt_o[324] = lce_data_cmd_i[324];
assign data_mem_pkt_o[323] = lce_data_cmd_i[323];
assign data_mem_pkt_o[322] = lce_data_cmd_i[322];
assign data_mem_pkt_o[321] = lce_data_cmd_i[321];
assign data_mem_pkt_o[320] = lce_data_cmd_i[320];
assign data_mem_pkt_o[319] = lce_data_cmd_i[319];
assign data_mem_pkt_o[318] = lce_data_cmd_i[318];
assign data_mem_pkt_o[317] = lce_data_cmd_i[317];
assign data_mem_pkt_o[316] = lce_data_cmd_i[316];
assign data_mem_pkt_o[315] = lce_data_cmd_i[315];
assign data_mem_pkt_o[314] = lce_data_cmd_i[314];
assign data_mem_pkt_o[313] = lce_data_cmd_i[313];
assign data_mem_pkt_o[312] = lce_data_cmd_i[312];
assign data_mem_pkt_o[311] = lce_data_cmd_i[311];
assign data_mem_pkt_o[310] = lce_data_cmd_i[310];
assign data_mem_pkt_o[309] = lce_data_cmd_i[309];
assign data_mem_pkt_o[308] = lce_data_cmd_i[308];
assign data_mem_pkt_o[307] = lce_data_cmd_i[307];
assign data_mem_pkt_o[306] = lce_data_cmd_i[306];
assign data_mem_pkt_o[305] = lce_data_cmd_i[305];
assign data_mem_pkt_o[304] = lce_data_cmd_i[304];
assign data_mem_pkt_o[303] = lce_data_cmd_i[303];
assign data_mem_pkt_o[302] = lce_data_cmd_i[302];
assign data_mem_pkt_o[301] = lce_data_cmd_i[301];
assign data_mem_pkt_o[300] = lce_data_cmd_i[300];
assign data_mem_pkt_o[299] = lce_data_cmd_i[299];
assign data_mem_pkt_o[298] = lce_data_cmd_i[298];
assign data_mem_pkt_o[297] = lce_data_cmd_i[297];
assign data_mem_pkt_o[296] = lce_data_cmd_i[296];
assign data_mem_pkt_o[295] = lce_data_cmd_i[295];
assign data_mem_pkt_o[294] = lce_data_cmd_i[294];
assign data_mem_pkt_o[293] = lce_data_cmd_i[293];
assign data_mem_pkt_o[292] = lce_data_cmd_i[292];
assign data_mem_pkt_o[291] = lce_data_cmd_i[291];
assign data_mem_pkt_o[290] = lce_data_cmd_i[290];
assign data_mem_pkt_o[289] = lce_data_cmd_i[289];
assign data_mem_pkt_o[288] = lce_data_cmd_i[288];
assign data_mem_pkt_o[287] = lce_data_cmd_i[287];
assign data_mem_pkt_o[286] = lce_data_cmd_i[286];
assign data_mem_pkt_o[285] = lce_data_cmd_i[285];
assign data_mem_pkt_o[284] = lce_data_cmd_i[284];
assign data_mem_pkt_o[283] = lce_data_cmd_i[283];
assign data_mem_pkt_o[282] = lce_data_cmd_i[282];
assign data_mem_pkt_o[281] = lce_data_cmd_i[281];
assign data_mem_pkt_o[280] = lce_data_cmd_i[280];
assign data_mem_pkt_o[279] = lce_data_cmd_i[279];
assign data_mem_pkt_o[278] = lce_data_cmd_i[278];
assign data_mem_pkt_o[277] = lce_data_cmd_i[277];
assign data_mem_pkt_o[276] = lce_data_cmd_i[276];
assign data_mem_pkt_o[275] = lce_data_cmd_i[275];
assign data_mem_pkt_o[274] = lce_data_cmd_i[274];
assign data_mem_pkt_o[273] = lce_data_cmd_i[273];
assign data_mem_pkt_o[272] = lce_data_cmd_i[272];
assign data_mem_pkt_o[271] = lce_data_cmd_i[271];
assign data_mem_pkt_o[270] = lce_data_cmd_i[270];
assign data_mem_pkt_o[269] = lce_data_cmd_i[269];
assign data_mem_pkt_o[268] = lce_data_cmd_i[268];
assign data_mem_pkt_o[267] = lce_data_cmd_i[267];
assign data_mem_pkt_o[266] = lce_data_cmd_i[266];
assign data_mem_pkt_o[265] = lce_data_cmd_i[265];
assign data_mem_pkt_o[264] = lce_data_cmd_i[264];
assign data_mem_pkt_o[263] = lce_data_cmd_i[263];
assign data_mem_pkt_o[262] = lce_data_cmd_i[262];
assign data_mem_pkt_o[261] = lce_data_cmd_i[261];
assign data_mem_pkt_o[260] = lce_data_cmd_i[260];
assign data_mem_pkt_o[259] = lce_data_cmd_i[259];
assign data_mem_pkt_o[258] = lce_data_cmd_i[258];
assign data_mem_pkt_o[257] = lce_data_cmd_i[257];
assign data_mem_pkt_o[256] = lce_data_cmd_i[256];
assign data_mem_pkt_o[255] = lce_data_cmd_i[255];
assign data_mem_pkt_o[254] = lce_data_cmd_i[254];
assign data_mem_pkt_o[253] = lce_data_cmd_i[253];
assign data_mem_pkt_o[252] = lce_data_cmd_i[252];
assign data_mem_pkt_o[251] = lce_data_cmd_i[251];
assign data_mem_pkt_o[250] = lce_data_cmd_i[250];
assign data_mem_pkt_o[249] = lce_data_cmd_i[249];
assign data_mem_pkt_o[248] = lce_data_cmd_i[248];
assign data_mem_pkt_o[247] = lce_data_cmd_i[247];
assign data_mem_pkt_o[246] = lce_data_cmd_i[246];
assign data_mem_pkt_o[245] = lce_data_cmd_i[245];
assign data_mem_pkt_o[244] = lce_data_cmd_i[244];
assign data_mem_pkt_o[243] = lce_data_cmd_i[243];
assign data_mem_pkt_o[242] = lce_data_cmd_i[242];
assign data_mem_pkt_o[241] = lce_data_cmd_i[241];
assign data_mem_pkt_o[240] = lce_data_cmd_i[240];
assign data_mem_pkt_o[239] = lce_data_cmd_i[239];
assign data_mem_pkt_o[238] = lce_data_cmd_i[238];
assign data_mem_pkt_o[237] = lce_data_cmd_i[237];
assign data_mem_pkt_o[236] = lce_data_cmd_i[236];
assign data_mem_pkt_o[235] = lce_data_cmd_i[235];
assign data_mem_pkt_o[234] = lce_data_cmd_i[234];
assign data_mem_pkt_o[233] = lce_data_cmd_i[233];
assign data_mem_pkt_o[232] = lce_data_cmd_i[232];
assign data_mem_pkt_o[231] = lce_data_cmd_i[231];
assign data_mem_pkt_o[230] = lce_data_cmd_i[230];
assign data_mem_pkt_o[229] = lce_data_cmd_i[229];
assign data_mem_pkt_o[228] = lce_data_cmd_i[228];
assign data_mem_pkt_o[227] = lce_data_cmd_i[227];
assign data_mem_pkt_o[226] = lce_data_cmd_i[226];
assign data_mem_pkt_o[225] = lce_data_cmd_i[225];
assign data_mem_pkt_o[224] = lce_data_cmd_i[224];
assign data_mem_pkt_o[223] = lce_data_cmd_i[223];
assign data_mem_pkt_o[222] = lce_data_cmd_i[222];
assign data_mem_pkt_o[221] = lce_data_cmd_i[221];
assign data_mem_pkt_o[220] = lce_data_cmd_i[220];
assign data_mem_pkt_o[219] = lce_data_cmd_i[219];
assign data_mem_pkt_o[218] = lce_data_cmd_i[218];
assign data_mem_pkt_o[217] = lce_data_cmd_i[217];
assign data_mem_pkt_o[216] = lce_data_cmd_i[216];
assign data_mem_pkt_o[215] = lce_data_cmd_i[215];
assign data_mem_pkt_o[214] = lce_data_cmd_i[214];
assign data_mem_pkt_o[213] = lce_data_cmd_i[213];
assign data_mem_pkt_o[212] = lce_data_cmd_i[212];
assign data_mem_pkt_o[211] = lce_data_cmd_i[211];
assign data_mem_pkt_o[210] = lce_data_cmd_i[210];
assign data_mem_pkt_o[209] = lce_data_cmd_i[209];
assign data_mem_pkt_o[208] = lce_data_cmd_i[208];
assign data_mem_pkt_o[207] = lce_data_cmd_i[207];
assign data_mem_pkt_o[206] = lce_data_cmd_i[206];
assign data_mem_pkt_o[205] = lce_data_cmd_i[205];
assign data_mem_pkt_o[204] = lce_data_cmd_i[204];
assign data_mem_pkt_o[203] = lce_data_cmd_i[203];
assign data_mem_pkt_o[202] = lce_data_cmd_i[202];
assign data_mem_pkt_o[201] = lce_data_cmd_i[201];
assign data_mem_pkt_o[200] = lce_data_cmd_i[200];
assign data_mem_pkt_o[199] = lce_data_cmd_i[199];
assign data_mem_pkt_o[198] = lce_data_cmd_i[198];
assign data_mem_pkt_o[197] = lce_data_cmd_i[197];
assign data_mem_pkt_o[196] = lce_data_cmd_i[196];
assign data_mem_pkt_o[195] = lce_data_cmd_i[195];
assign data_mem_pkt_o[194] = lce_data_cmd_i[194];
assign data_mem_pkt_o[193] = lce_data_cmd_i[193];
assign data_mem_pkt_o[192] = lce_data_cmd_i[192];
assign data_mem_pkt_o[191] = lce_data_cmd_i[191];
assign data_mem_pkt_o[190] = lce_data_cmd_i[190];
assign data_mem_pkt_o[189] = lce_data_cmd_i[189];
assign data_mem_pkt_o[188] = lce_data_cmd_i[188];
assign data_mem_pkt_o[187] = lce_data_cmd_i[187];
assign data_mem_pkt_o[186] = lce_data_cmd_i[186];
assign data_mem_pkt_o[185] = lce_data_cmd_i[185];
assign data_mem_pkt_o[184] = lce_data_cmd_i[184];
assign data_mem_pkt_o[183] = lce_data_cmd_i[183];
assign data_mem_pkt_o[182] = lce_data_cmd_i[182];
assign data_mem_pkt_o[181] = lce_data_cmd_i[181];
assign data_mem_pkt_o[180] = lce_data_cmd_i[180];
assign data_mem_pkt_o[179] = lce_data_cmd_i[179];
assign data_mem_pkt_o[178] = lce_data_cmd_i[178];
assign data_mem_pkt_o[177] = lce_data_cmd_i[177];
assign data_mem_pkt_o[176] = lce_data_cmd_i[176];
assign data_mem_pkt_o[175] = lce_data_cmd_i[175];
assign data_mem_pkt_o[174] = lce_data_cmd_i[174];
assign data_mem_pkt_o[173] = lce_data_cmd_i[173];
assign data_mem_pkt_o[172] = lce_data_cmd_i[172];
assign data_mem_pkt_o[171] = lce_data_cmd_i[171];
assign data_mem_pkt_o[170] = lce_data_cmd_i[170];
assign data_mem_pkt_o[169] = lce_data_cmd_i[169];
assign data_mem_pkt_o[168] = lce_data_cmd_i[168];
assign data_mem_pkt_o[167] = lce_data_cmd_i[167];
assign data_mem_pkt_o[166] = lce_data_cmd_i[166];
assign data_mem_pkt_o[165] = lce_data_cmd_i[165];
assign data_mem_pkt_o[164] = lce_data_cmd_i[164];
assign data_mem_pkt_o[163] = lce_data_cmd_i[163];
assign data_mem_pkt_o[162] = lce_data_cmd_i[162];
assign data_mem_pkt_o[161] = lce_data_cmd_i[161];
assign data_mem_pkt_o[160] = lce_data_cmd_i[160];
assign data_mem_pkt_o[159] = lce_data_cmd_i[159];
assign data_mem_pkt_o[158] = lce_data_cmd_i[158];
assign data_mem_pkt_o[157] = lce_data_cmd_i[157];
assign data_mem_pkt_o[156] = lce_data_cmd_i[156];
assign data_mem_pkt_o[155] = lce_data_cmd_i[155];
assign data_mem_pkt_o[154] = lce_data_cmd_i[154];
assign data_mem_pkt_o[153] = lce_data_cmd_i[153];
assign data_mem_pkt_o[152] = lce_data_cmd_i[152];
assign data_mem_pkt_o[151] = lce_data_cmd_i[151];
assign data_mem_pkt_o[150] = lce_data_cmd_i[150];
assign data_mem_pkt_o[149] = lce_data_cmd_i[149];
assign data_mem_pkt_o[148] = lce_data_cmd_i[148];
assign data_mem_pkt_o[147] = lce_data_cmd_i[147];
assign data_mem_pkt_o[146] = lce_data_cmd_i[146];
assign data_mem_pkt_o[145] = lce_data_cmd_i[145];
assign data_mem_pkt_o[144] = lce_data_cmd_i[144];
assign data_mem_pkt_o[143] = lce_data_cmd_i[143];
assign data_mem_pkt_o[142] = lce_data_cmd_i[142];
assign data_mem_pkt_o[141] = lce_data_cmd_i[141];
assign data_mem_pkt_o[140] = lce_data_cmd_i[140];
assign data_mem_pkt_o[139] = lce_data_cmd_i[139];
assign data_mem_pkt_o[138] = lce_data_cmd_i[138];
assign data_mem_pkt_o[137] = lce_data_cmd_i[137];
assign data_mem_pkt_o[136] = lce_data_cmd_i[136];
assign data_mem_pkt_o[135] = lce_data_cmd_i[135];
assign data_mem_pkt_o[134] = lce_data_cmd_i[134];
assign data_mem_pkt_o[133] = lce_data_cmd_i[133];
assign data_mem_pkt_o[132] = lce_data_cmd_i[132];
assign data_mem_pkt_o[131] = lce_data_cmd_i[131];
assign data_mem_pkt_o[130] = lce_data_cmd_i[130];
assign data_mem_pkt_o[129] = lce_data_cmd_i[129];
assign data_mem_pkt_o[128] = lce_data_cmd_i[128];
assign data_mem_pkt_o[127] = lce_data_cmd_i[127];
assign data_mem_pkt_o[126] = lce_data_cmd_i[126];
assign data_mem_pkt_o[125] = lce_data_cmd_i[125];
assign data_mem_pkt_o[124] = lce_data_cmd_i[124];
assign data_mem_pkt_o[123] = lce_data_cmd_i[123];
assign data_mem_pkt_o[122] = lce_data_cmd_i[122];
assign data_mem_pkt_o[121] = lce_data_cmd_i[121];
assign data_mem_pkt_o[120] = lce_data_cmd_i[120];
assign data_mem_pkt_o[119] = lce_data_cmd_i[119];
assign data_mem_pkt_o[118] = lce_data_cmd_i[118];
assign data_mem_pkt_o[117] = lce_data_cmd_i[117];
assign data_mem_pkt_o[116] = lce_data_cmd_i[116];
assign data_mem_pkt_o[115] = lce_data_cmd_i[115];
assign data_mem_pkt_o[114] = lce_data_cmd_i[114];
assign data_mem_pkt_o[113] = lce_data_cmd_i[113];
assign data_mem_pkt_o[112] = lce_data_cmd_i[112];
assign data_mem_pkt_o[111] = lce_data_cmd_i[111];
assign data_mem_pkt_o[110] = lce_data_cmd_i[110];
assign data_mem_pkt_o[109] = lce_data_cmd_i[109];
assign data_mem_pkt_o[108] = lce_data_cmd_i[108];
assign data_mem_pkt_o[107] = lce_data_cmd_i[107];
assign data_mem_pkt_o[106] = lce_data_cmd_i[106];
assign data_mem_pkt_o[105] = lce_data_cmd_i[105];
assign data_mem_pkt_o[104] = lce_data_cmd_i[104];
assign data_mem_pkt_o[103] = lce_data_cmd_i[103];
assign data_mem_pkt_o[102] = lce_data_cmd_i[102];
assign data_mem_pkt_o[101] = lce_data_cmd_i[101];
assign data_mem_pkt_o[100] = lce_data_cmd_i[100];
assign data_mem_pkt_o[99] = lce_data_cmd_i[99];
assign data_mem_pkt_o[98] = lce_data_cmd_i[98];
assign data_mem_pkt_o[97] = lce_data_cmd_i[97];
assign data_mem_pkt_o[96] = lce_data_cmd_i[96];
assign data_mem_pkt_o[95] = lce_data_cmd_i[95];
assign data_mem_pkt_o[94] = lce_data_cmd_i[94];
assign data_mem_pkt_o[93] = lce_data_cmd_i[93];
assign data_mem_pkt_o[92] = lce_data_cmd_i[92];
assign data_mem_pkt_o[91] = lce_data_cmd_i[91];
assign data_mem_pkt_o[90] = lce_data_cmd_i[90];
assign data_mem_pkt_o[89] = lce_data_cmd_i[89];
assign data_mem_pkt_o[88] = lce_data_cmd_i[88];
assign data_mem_pkt_o[87] = lce_data_cmd_i[87];
assign data_mem_pkt_o[86] = lce_data_cmd_i[86];
assign data_mem_pkt_o[85] = lce_data_cmd_i[85];
assign data_mem_pkt_o[84] = lce_data_cmd_i[84];
assign data_mem_pkt_o[83] = lce_data_cmd_i[83];
assign data_mem_pkt_o[82] = lce_data_cmd_i[82];
assign data_mem_pkt_o[81] = lce_data_cmd_i[81];
assign data_mem_pkt_o[80] = lce_data_cmd_i[80];
assign data_mem_pkt_o[79] = lce_data_cmd_i[79];
assign data_mem_pkt_o[78] = lce_data_cmd_i[78];
assign data_mem_pkt_o[77] = lce_data_cmd_i[77];
assign data_mem_pkt_o[76] = lce_data_cmd_i[76];
assign data_mem_pkt_o[75] = lce_data_cmd_i[75];
assign data_mem_pkt_o[74] = lce_data_cmd_i[74];
assign data_mem_pkt_o[73] = lce_data_cmd_i[73];
assign data_mem_pkt_o[72] = lce_data_cmd_i[72];
assign data_mem_pkt_o[71] = lce_data_cmd_i[71];
assign data_mem_pkt_o[70] = lce_data_cmd_i[70];
assign data_mem_pkt_o[69] = lce_data_cmd_i[69];
assign data_mem_pkt_o[68] = lce_data_cmd_i[68];
assign data_mem_pkt_o[67] = lce_data_cmd_i[67];
assign data_mem_pkt_o[66] = lce_data_cmd_i[66];
assign data_mem_pkt_o[65] = lce_data_cmd_i[65];
assign data_mem_pkt_o[64] = lce_data_cmd_i[64];
assign data_mem_pkt_o[63] = lce_data_cmd_i[63];
assign data_mem_pkt_o[62] = lce_data_cmd_i[62];
assign data_mem_pkt_o[61] = lce_data_cmd_i[61];
assign data_mem_pkt_o[60] = lce_data_cmd_i[60];
assign data_mem_pkt_o[59] = lce_data_cmd_i[59];
assign data_mem_pkt_o[58] = lce_data_cmd_i[58];
assign data_mem_pkt_o[57] = lce_data_cmd_i[57];
assign data_mem_pkt_o[56] = lce_data_cmd_i[56];
assign data_mem_pkt_o[55] = lce_data_cmd_i[55];
assign data_mem_pkt_o[54] = lce_data_cmd_i[54];
assign data_mem_pkt_o[53] = lce_data_cmd_i[53];
assign data_mem_pkt_o[52] = lce_data_cmd_i[52];
assign data_mem_pkt_o[51] = lce_data_cmd_i[51];
assign data_mem_pkt_o[50] = lce_data_cmd_i[50];
assign data_mem_pkt_o[49] = lce_data_cmd_i[49];
assign data_mem_pkt_o[48] = lce_data_cmd_i[48];
assign data_mem_pkt_o[47] = lce_data_cmd_i[47];
assign data_mem_pkt_o[46] = lce_data_cmd_i[46];
assign data_mem_pkt_o[45] = lce_data_cmd_i[45];
assign data_mem_pkt_o[44] = lce_data_cmd_i[44];
assign data_mem_pkt_o[43] = lce_data_cmd_i[43];
assign data_mem_pkt_o[42] = lce_data_cmd_i[42];
assign data_mem_pkt_o[41] = lce_data_cmd_i[41];
assign data_mem_pkt_o[40] = lce_data_cmd_i[40];
assign data_mem_pkt_o[39] = lce_data_cmd_i[39];
assign data_mem_pkt_o[38] = lce_data_cmd_i[38];
assign data_mem_pkt_o[37] = lce_data_cmd_i[37];
assign data_mem_pkt_o[36] = lce_data_cmd_i[36];
assign data_mem_pkt_o[35] = lce_data_cmd_i[35];
assign data_mem_pkt_o[34] = lce_data_cmd_i[34];
assign data_mem_pkt_o[33] = lce_data_cmd_i[33];
assign data_mem_pkt_o[32] = lce_data_cmd_i[32];
assign data_mem_pkt_o[31] = lce_data_cmd_i[31];
assign data_mem_pkt_o[30] = lce_data_cmd_i[30];
assign data_mem_pkt_o[29] = lce_data_cmd_i[29];
assign data_mem_pkt_o[28] = lce_data_cmd_i[28];
assign data_mem_pkt_o[27] = lce_data_cmd_i[27];
assign data_mem_pkt_o[26] = lce_data_cmd_i[26];
assign data_mem_pkt_o[25] = lce_data_cmd_i[25];
assign data_mem_pkt_o[24] = lce_data_cmd_i[24];
assign data_mem_pkt_o[23] = lce_data_cmd_i[23];
assign data_mem_pkt_o[22] = lce_data_cmd_i[22];
assign data_mem_pkt_o[21] = lce_data_cmd_i[21];
assign data_mem_pkt_o[20] = lce_data_cmd_i[20];
assign data_mem_pkt_o[19] = lce_data_cmd_i[19];
assign data_mem_pkt_o[18] = lce_data_cmd_i[18];
assign data_mem_pkt_o[17] = lce_data_cmd_i[17];
assign data_mem_pkt_o[16] = lce_data_cmd_i[16];
assign data_mem_pkt_o[15] = lce_data_cmd_i[15];
assign data_mem_pkt_o[14] = lce_data_cmd_i[14];
assign data_mem_pkt_o[13] = lce_data_cmd_i[13];
assign data_mem_pkt_o[12] = lce_data_cmd_i[12];
assign data_mem_pkt_o[11] = lce_data_cmd_i[11];
assign data_mem_pkt_o[10] = lce_data_cmd_i[10];
assign data_mem_pkt_o[9] = lce_data_cmd_i[9];
assign data_mem_pkt_o[8] = lce_data_cmd_i[8];
assign data_mem_pkt_o[7] = lce_data_cmd_i[7];
assign data_mem_pkt_o[6] = lce_data_cmd_i[6];
assign data_mem_pkt_o[5] = lce_data_cmd_i[5];
assign data_mem_pkt_o[4] = lce_data_cmd_i[4];
assign data_mem_pkt_o[3] = lce_data_cmd_i[3];
assign data_mem_pkt_o[2] = lce_data_cmd_i[2];
assign data_mem_pkt_o[1] = lce_data_cmd_i[1];
assign data_mem_pkt_o[0] = lce_data_cmd_i[0];
assign cce_data_received_o = lce_data_cmd_v_i & data_mem_pkt_yumi_i;
endmodule
|
module bp_be_dcache_lru_decode_ways_p8
(
way_id_i,
data_o,
mask_o
);
input [2:0] way_id_i;
output [6:0] data_o;
output [6:0] mask_o;
wire [6:0] data_o,mask_o;
wire N0,N1,N2,N3,N4,N5,N6,N7,N8,N9,N10,N11,N12,N13,N14,N15,N16,N17,N18,N19,N20,N21,
N22,N23,N24,N25,N26,N27,N28,N29,N30;
assign mask_o[0] = 1'b1;
assign N11 = N8 & N9;
assign N12 = N11 & N10;
assign N13 = way_id_i[2] | way_id_i[1];
assign N14 = N13 | N10;
assign N16 = way_id_i[2] | N9;
assign N17 = N16 | way_id_i[0];
assign N19 = N16 | N10;
assign N21 = N8 | way_id_i[1];
assign N22 = N21 | way_id_i[0];
assign N24 = N21 | N10;
assign N26 = N8 | N9;
assign N27 = N26 | way_id_i[0];
assign N29 = way_id_i[2] & way_id_i[1];
assign N30 = N29 & way_id_i[0];
assign data_o = (N0)? { 1'b0, 1'b0, 1'b0, 1'b1, 1'b0, 1'b1, 1'b1 } :
(N1)? { 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b1, 1'b1 } :
(N2)? { 1'b0, 1'b0, 1'b1, 1'b0, 1'b0, 1'b0, 1'b1 } :
(N3)? { 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b1 } :
(N4)? { 1'b0, 1'b1, 1'b0, 1'b0, 1'b1, 1'b0, 1'b0 } :
(N5)? { 1'b0, 1'b0, 1'b0, 1'b0, 1'b1, 1'b0, 1'b0 } :
(N6)? { 1'b1, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0 } :
(N7)? { 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0 } : 1'b0;
assign N0 = N12;
assign N1 = N15;
assign N2 = N18;
assign N3 = N20;
assign N4 = N23;
assign N5 = N25;
assign N6 = N28;
assign N7 = N30;
assign mask_o[6:1] = (N0)? { 1'b0, 1'b0, 1'b0, 1'b1, 1'b0, 1'b1 } :
(N1)? { 1'b0, 1'b0, 1'b0, 1'b1, 1'b0, 1'b1 } :
(N2)? { 1'b0, 1'b0, 1'b1, 1'b0, 1'b0, 1'b1 } :
(N3)? { 1'b0, 1'b0, 1'b1, 1'b0, 1'b0, 1'b1 } :
(N4)? { 1'b0, 1'b1, 1'b0, 1'b0, 1'b1, 1'b0 } :
(N5)? { 1'b0, 1'b1, 1'b0, 1'b0, 1'b1, 1'b0 } :
(N6)? { 1'b1, 1'b0, 1'b0, 1'b0, 1'b1, 1'b0 } :
(N7)? { 1'b1, 1'b0, 1'b0, 1'b0, 1'b1, 1'b0 } : 1'b0;
assign N8 = ~way_id_i[2];
assign N9 = ~way_id_i[1];
assign N10 = ~way_id_i[0];
assign N15 = ~N14;
assign N18 = ~N17;
assign N20 = ~N19;
assign N23 = ~N22;
assign N25 = ~N24;
assign N28 = ~N27;
endmodule
|
module bsg_encode_one_hot_width_p1
(
i,
addr_o,
v_o
);
input [0:0] i;
output [0:0] addr_o;
output v_o;
wire [0:0] addr_o;
wire v_o;
assign v_o = i[0];
assign addr_o[0] = 1'b0;
endmodule
|
module bp_be_dcache_lce_data_cmd_num_cce_p1_num_lce_p2_data_width_p64_paddr_width_p22_lce_data_width_p512_ways_p8_sets_p64
(
cce_data_received_o,
lce_data_cmd_i,
lce_data_cmd_v_i,
lce_data_cmd_yumi_o,
data_mem_pkt_v_o,
data_mem_pkt_o,
data_mem_pkt_yumi_i
);
input [539:0] lce_data_cmd_i;
output [521:0] data_mem_pkt_o;
input lce_data_cmd_v_i;
input data_mem_pkt_yumi_i;
output cce_data_received_o;
output lce_data_cmd_yumi_o;
output data_mem_pkt_v_o;
wire [521:0] data_mem_pkt_o;
wire cce_data_received_o,lce_data_cmd_yumi_o,data_mem_pkt_v_o,data_mem_pkt_yumi_i,
lce_data_cmd_v_i;
assign data_mem_pkt_o[0] = 1'b1;
assign cce_data_received_o = data_mem_pkt_yumi_i;
assign lce_data_cmd_yumi_o = data_mem_pkt_yumi_i;
assign data_mem_pkt_v_o = lce_data_cmd_v_i;
assign data_mem_pkt_o[521] = lce_data_cmd_i[523];
assign data_mem_pkt_o[520] = lce_data_cmd_i[522];
assign data_mem_pkt_o[519] = lce_data_cmd_i[521];
assign data_mem_pkt_o[518] = lce_data_cmd_i[520];
assign data_mem_pkt_o[517] = lce_data_cmd_i[519];
assign data_mem_pkt_o[516] = lce_data_cmd_i[518];
assign data_mem_pkt_o[515] = lce_data_cmd_i[536];
assign data_mem_pkt_o[514] = lce_data_cmd_i[535];
assign data_mem_pkt_o[513] = lce_data_cmd_i[534];
assign data_mem_pkt_o[512] = lce_data_cmd_i[511];
assign data_mem_pkt_o[511] = lce_data_cmd_i[510];
assign data_mem_pkt_o[510] = lce_data_cmd_i[509];
assign data_mem_pkt_o[509] = lce_data_cmd_i[508];
assign data_mem_pkt_o[508] = lce_data_cmd_i[507];
assign data_mem_pkt_o[507] = lce_data_cmd_i[506];
assign data_mem_pkt_o[506] = lce_data_cmd_i[505];
assign data_mem_pkt_o[505] = lce_data_cmd_i[504];
assign data_mem_pkt_o[504] = lce_data_cmd_i[503];
assign data_mem_pkt_o[503] = lce_data_cmd_i[502];
assign data_mem_pkt_o[502] = lce_data_cmd_i[501];
assign data_mem_pkt_o[501] = lce_data_cmd_i[500];
assign data_mem_pkt_o[500] = lce_data_cmd_i[499];
assign data_mem_pkt_o[499] = lce_data_cmd_i[498];
assign data_mem_pkt_o[498] = lce_data_cmd_i[497];
assign data_mem_pkt_o[497] = lce_data_cmd_i[496];
assign data_mem_pkt_o[496] = lce_data_cmd_i[495];
assign data_mem_pkt_o[495] = lce_data_cmd_i[494];
assign data_mem_pkt_o[494] = lce_data_cmd_i[493];
assign data_mem_pkt_o[493] = lce_data_cmd_i[492];
assign data_mem_pkt_o[492] = lce_data_cmd_i[491];
assign data_mem_pkt_o[491] = lce_data_cmd_i[490];
assign data_mem_pkt_o[490] = lce_data_cmd_i[489];
assign data_mem_pkt_o[489] = lce_data_cmd_i[488];
assign data_mem_pkt_o[488] = lce_data_cmd_i[487];
assign data_mem_pkt_o[487] = lce_data_cmd_i[486];
assign data_mem_pkt_o[486] = lce_data_cmd_i[485];
assign data_mem_pkt_o[485] = lce_data_cmd_i[484];
assign data_mem_pkt_o[484] = lce_data_cmd_i[483];
assign data_mem_pkt_o[483] = lce_data_cmd_i[482];
assign data_mem_pkt_o[482] = lce_data_cmd_i[481];
assign data_mem_pkt_o[481] = lce_data_cmd_i[480];
assign data_mem_pkt_o[480] = lce_data_cmd_i[479];
assign data_mem_pkt_o[479] = lce_data_cmd_i[478];
assign data_mem_pkt_o[478] = lce_data_cmd_i[477];
assign data_mem_pkt_o[477] = lce_data_cmd_i[476];
assign data_mem_pkt_o[476] = lce_data_cmd_i[475];
assign data_mem_pkt_o[475] = lce_data_cmd_i[474];
assign data_mem_pkt_o[474] = lce_data_cmd_i[473];
assign data_mem_pkt_o[473] = lce_data_cmd_i[472];
assign data_mem_pkt_o[472] = lce_data_cmd_i[471];
assign data_mem_pkt_o[471] = lce_data_cmd_i[470];
assign data_mem_pkt_o[470] = lce_data_cmd_i[469];
assign data_mem_pkt_o[469] = lce_data_cmd_i[468];
assign data_mem_pkt_o[468] = lce_data_cmd_i[467];
assign data_mem_pkt_o[467] = lce_data_cmd_i[466];
assign data_mem_pkt_o[466] = lce_data_cmd_i[465];
assign data_mem_pkt_o[465] = lce_data_cmd_i[464];
assign data_mem_pkt_o[464] = lce_data_cmd_i[463];
assign data_mem_pkt_o[463] = lce_data_cmd_i[462];
assign data_mem_pkt_o[462] = lce_data_cmd_i[461];
assign data_mem_pkt_o[461] = lce_data_cmd_i[460];
assign data_mem_pkt_o[460] = lce_data_cmd_i[459];
assign data_mem_pkt_o[459] = lce_data_cmd_i[458];
assign data_mem_pkt_o[458] = lce_data_cmd_i[457];
assign data_mem_pkt_o[457] = lce_data_cmd_i[456];
assign data_mem_pkt_o[456] = lce_data_cmd_i[455];
assign data_mem_pkt_o[455] = lce_data_cmd_i[454];
assign data_mem_pkt_o[454] = lce_data_cmd_i[453];
assign data_mem_pkt_o[453] = lce_data_cmd_i[452];
assign data_mem_pkt_o[452] = lce_data_cmd_i[451];
assign data_mem_pkt_o[451] = lce_data_cmd_i[450];
assign data_mem_pkt_o[450] = lce_data_cmd_i[449];
assign data_mem_pkt_o[449] = lce_data_cmd_i[448];
assign data_mem_pkt_o[448] = lce_data_cmd_i[447];
assign data_mem_pkt_o[447] = lce_data_cmd_i[446];
assign data_mem_pkt_o[446] = lce_data_cmd_i[445];
assign data_mem_pkt_o[445] = lce_data_cmd_i[444];
assign data_mem_pkt_o[444] = lce_data_cmd_i[443];
assign data_mem_pkt_o[443] = lce_data_cmd_i[442];
assign data_mem_pkt_o[442] = lce_data_cmd_i[441];
assign data_mem_pkt_o[441] = lce_data_cmd_i[440];
assign data_mem_pkt_o[440] = lce_data_cmd_i[439];
assign data_mem_pkt_o[439] = lce_data_cmd_i[438];
assign data_mem_pkt_o[438] = lce_data_cmd_i[437];
assign data_mem_pkt_o[437] = lce_data_cmd_i[436];
assign data_mem_pkt_o[436] = lce_data_cmd_i[435];
assign data_mem_pkt_o[435] = lce_data_cmd_i[434];
assign data_mem_pkt_o[434] = lce_data_cmd_i[433];
assign data_mem_pkt_o[433] = lce_data_cmd_i[432];
assign data_mem_pkt_o[432] = lce_data_cmd_i[431];
assign data_mem_pkt_o[431] = lce_data_cmd_i[430];
assign data_mem_pkt_o[430] = lce_data_cmd_i[429];
assign data_mem_pkt_o[429] = lce_data_cmd_i[428];
assign data_mem_pkt_o[428] = lce_data_cmd_i[427];
assign data_mem_pkt_o[427] = lce_data_cmd_i[426];
assign data_mem_pkt_o[426] = lce_data_cmd_i[425];
assign data_mem_pkt_o[425] = lce_data_cmd_i[424];
assign data_mem_pkt_o[424] = lce_data_cmd_i[423];
assign data_mem_pkt_o[423] = lce_data_cmd_i[422];
assign data_mem_pkt_o[422] = lce_data_cmd_i[421];
assign data_mem_pkt_o[421] = lce_data_cmd_i[420];
assign data_mem_pkt_o[420] = lce_data_cmd_i[419];
assign data_mem_pkt_o[419] = lce_data_cmd_i[418];
assign data_mem_pkt_o[418] = lce_data_cmd_i[417];
assign data_mem_pkt_o[417] = lce_data_cmd_i[416];
assign data_mem_pkt_o[416] = lce_data_cmd_i[415];
assign data_mem_pkt_o[415] = lce_data_cmd_i[414];
assign data_mem_pkt_o[414] = lce_data_cmd_i[413];
assign data_mem_pkt_o[413] = lce_data_cmd_i[412];
assign data_mem_pkt_o[412] = lce_data_cmd_i[411];
assign data_mem_pkt_o[411] = lce_data_cmd_i[410];
assign data_mem_pkt_o[410] = lce_data_cmd_i[409];
assign data_mem_pkt_o[409] = lce_data_cmd_i[408];
assign data_mem_pkt_o[408] = lce_data_cmd_i[407];
assign data_mem_pkt_o[407] = lce_data_cmd_i[406];
assign data_mem_pkt_o[406] = lce_data_cmd_i[405];
assign data_mem_pkt_o[405] = lce_data_cmd_i[404];
assign data_mem_pkt_o[404] = lce_data_cmd_i[403];
assign data_mem_pkt_o[403] = lce_data_cmd_i[402];
assign data_mem_pkt_o[402] = lce_data_cmd_i[401];
assign data_mem_pkt_o[401] = lce_data_cmd_i[400];
assign data_mem_pkt_o[400] = lce_data_cmd_i[399];
assign data_mem_pkt_o[399] = lce_data_cmd_i[398];
assign data_mem_pkt_o[398] = lce_data_cmd_i[397];
assign data_mem_pkt_o[397] = lce_data_cmd_i[396];
assign data_mem_pkt_o[396] = lce_data_cmd_i[395];
assign data_mem_pkt_o[395] = lce_data_cmd_i[394];
assign data_mem_pkt_o[394] = lce_data_cmd_i[393];
assign data_mem_pkt_o[393] = lce_data_cmd_i[392];
assign data_mem_pkt_o[392] = lce_data_cmd_i[391];
assign data_mem_pkt_o[391] = lce_data_cmd_i[390];
assign data_mem_pkt_o[390] = lce_data_cmd_i[389];
assign data_mem_pkt_o[389] = lce_data_cmd_i[388];
assign data_mem_pkt_o[388] = lce_data_cmd_i[387];
assign data_mem_pkt_o[387] = lce_data_cmd_i[386];
assign data_mem_pkt_o[386] = lce_data_cmd_i[385];
assign data_mem_pkt_o[385] = lce_data_cmd_i[384];
assign data_mem_pkt_o[384] = lce_data_cmd_i[383];
assign data_mem_pkt_o[383] = lce_data_cmd_i[382];
assign data_mem_pkt_o[382] = lce_data_cmd_i[381];
assign data_mem_pkt_o[381] = lce_data_cmd_i[380];
assign data_mem_pkt_o[380] = lce_data_cmd_i[379];
assign data_mem_pkt_o[379] = lce_data_cmd_i[378];
assign data_mem_pkt_o[378] = lce_data_cmd_i[377];
assign data_mem_pkt_o[377] = lce_data_cmd_i[376];
assign data_mem_pkt_o[376] = lce_data_cmd_i[375];
assign data_mem_pkt_o[375] = lce_data_cmd_i[374];
assign data_mem_pkt_o[374] = lce_data_cmd_i[373];
assign data_mem_pkt_o[373] = lce_data_cmd_i[372];
assign data_mem_pkt_o[372] = lce_data_cmd_i[371];
assign data_mem_pkt_o[371] = lce_data_cmd_i[370];
assign data_mem_pkt_o[370] = lce_data_cmd_i[369];
assign data_mem_pkt_o[369] = lce_data_cmd_i[368];
assign data_mem_pkt_o[368] = lce_data_cmd_i[367];
assign data_mem_pkt_o[367] = lce_data_cmd_i[366];
assign data_mem_pkt_o[366] = lce_data_cmd_i[365];
assign data_mem_pkt_o[365] = lce_data_cmd_i[364];
assign data_mem_pkt_o[364] = lce_data_cmd_i[363];
assign data_mem_pkt_o[363] = lce_data_cmd_i[362];
assign data_mem_pkt_o[362] = lce_data_cmd_i[361];
assign data_mem_pkt_o[361] = lce_data_cmd_i[360];
assign data_mem_pkt_o[360] = lce_data_cmd_i[359];
assign data_mem_pkt_o[359] = lce_data_cmd_i[358];
assign data_mem_pkt_o[358] = lce_data_cmd_i[357];
assign data_mem_pkt_o[357] = lce_data_cmd_i[356];
assign data_mem_pkt_o[356] = lce_data_cmd_i[355];
assign data_mem_pkt_o[355] = lce_data_cmd_i[354];
assign data_mem_pkt_o[354] = lce_data_cmd_i[353];
assign data_mem_pkt_o[353] = lce_data_cmd_i[352];
assign data_mem_pkt_o[352] = lce_data_cmd_i[351];
assign data_mem_pkt_o[351] = lce_data_cmd_i[350];
assign data_mem_pkt_o[350] = lce_data_cmd_i[349];
assign data_mem_pkt_o[349] = lce_data_cmd_i[348];
assign data_mem_pkt_o[348] = lce_data_cmd_i[347];
assign data_mem_pkt_o[347] = lce_data_cmd_i[346];
assign data_mem_pkt_o[346] = lce_data_cmd_i[345];
assign data_mem_pkt_o[345] = lce_data_cmd_i[344];
assign data_mem_pkt_o[344] = lce_data_cmd_i[343];
assign data_mem_pkt_o[343] = lce_data_cmd_i[342];
assign data_mem_pkt_o[342] = lce_data_cmd_i[341];
assign data_mem_pkt_o[341] = lce_data_cmd_i[340];
assign data_mem_pkt_o[340] = lce_data_cmd_i[339];
assign data_mem_pkt_o[339] = lce_data_cmd_i[338];
assign data_mem_pkt_o[338] = lce_data_cmd_i[337];
assign data_mem_pkt_o[337] = lce_data_cmd_i[336];
assign data_mem_pkt_o[336] = lce_data_cmd_i[335];
assign data_mem_pkt_o[335] = lce_data_cmd_i[334];
assign data_mem_pkt_o[334] = lce_data_cmd_i[333];
assign data_mem_pkt_o[333] = lce_data_cmd_i[332];
assign data_mem_pkt_o[332] = lce_data_cmd_i[331];
assign data_mem_pkt_o[331] = lce_data_cmd_i[330];
assign data_mem_pkt_o[330] = lce_data_cmd_i[329];
assign data_mem_pkt_o[329] = lce_data_cmd_i[328];
assign data_mem_pkt_o[328] = lce_data_cmd_i[327];
assign data_mem_pkt_o[327] = lce_data_cmd_i[326];
assign data_mem_pkt_o[326] = lce_data_cmd_i[325];
assign data_mem_pkt_o[325] = lce_data_cmd_i[324];
assign data_mem_pkt_o[324] = lce_data_cmd_i[323];
assign data_mem_pkt_o[323] = lce_data_cmd_i[322];
assign data_mem_pkt_o[322] = lce_data_cmd_i[321];
assign data_mem_pkt_o[321] = lce_data_cmd_i[320];
assign data_mem_pkt_o[320] = lce_data_cmd_i[319];
assign data_mem_pkt_o[319] = lce_data_cmd_i[318];
assign data_mem_pkt_o[318] = lce_data_cmd_i[317];
assign data_mem_pkt_o[317] = lce_data_cmd_i[316];
assign data_mem_pkt_o[316] = lce_data_cmd_i[315];
assign data_mem_pkt_o[315] = lce_data_cmd_i[314];
assign data_mem_pkt_o[314] = lce_data_cmd_i[313];
assign data_mem_pkt_o[313] = lce_data_cmd_i[312];
assign data_mem_pkt_o[312] = lce_data_cmd_i[311];
assign data_mem_pkt_o[311] = lce_data_cmd_i[310];
assign data_mem_pkt_o[310] = lce_data_cmd_i[309];
assign data_mem_pkt_o[309] = lce_data_cmd_i[308];
assign data_mem_pkt_o[308] = lce_data_cmd_i[307];
assign data_mem_pkt_o[307] = lce_data_cmd_i[306];
assign data_mem_pkt_o[306] = lce_data_cmd_i[305];
assign data_mem_pkt_o[305] = lce_data_cmd_i[304];
assign data_mem_pkt_o[304] = lce_data_cmd_i[303];
assign data_mem_pkt_o[303] = lce_data_cmd_i[302];
assign data_mem_pkt_o[302] = lce_data_cmd_i[301];
assign data_mem_pkt_o[301] = lce_data_cmd_i[300];
assign data_mem_pkt_o[300] = lce_data_cmd_i[299];
assign data_mem_pkt_o[299] = lce_data_cmd_i[298];
assign data_mem_pkt_o[298] = lce_data_cmd_i[297];
assign data_mem_pkt_o[297] = lce_data_cmd_i[296];
assign data_mem_pkt_o[296] = lce_data_cmd_i[295];
assign data_mem_pkt_o[295] = lce_data_cmd_i[294];
assign data_mem_pkt_o[294] = lce_data_cmd_i[293];
assign data_mem_pkt_o[293] = lce_data_cmd_i[292];
assign data_mem_pkt_o[292] = lce_data_cmd_i[291];
assign data_mem_pkt_o[291] = lce_data_cmd_i[290];
assign data_mem_pkt_o[290] = lce_data_cmd_i[289];
assign data_mem_pkt_o[289] = lce_data_cmd_i[288];
assign data_mem_pkt_o[288] = lce_data_cmd_i[287];
assign data_mem_pkt_o[287] = lce_data_cmd_i[286];
assign data_mem_pkt_o[286] = lce_data_cmd_i[285];
assign data_mem_pkt_o[285] = lce_data_cmd_i[284];
assign data_mem_pkt_o[284] = lce_data_cmd_i[283];
assign data_mem_pkt_o[283] = lce_data_cmd_i[282];
assign data_mem_pkt_o[282] = lce_data_cmd_i[281];
assign data_mem_pkt_o[281] = lce_data_cmd_i[280];
assign data_mem_pkt_o[280] = lce_data_cmd_i[279];
assign data_mem_pkt_o[279] = lce_data_cmd_i[278];
assign data_mem_pkt_o[278] = lce_data_cmd_i[277];
assign data_mem_pkt_o[277] = lce_data_cmd_i[276];
assign data_mem_pkt_o[276] = lce_data_cmd_i[275];
assign data_mem_pkt_o[275] = lce_data_cmd_i[274];
assign data_mem_pkt_o[274] = lce_data_cmd_i[273];
assign data_mem_pkt_o[273] = lce_data_cmd_i[272];
assign data_mem_pkt_o[272] = lce_data_cmd_i[271];
assign data_mem_pkt_o[271] = lce_data_cmd_i[270];
assign data_mem_pkt_o[270] = lce_data_cmd_i[269];
assign data_mem_pkt_o[269] = lce_data_cmd_i[268];
assign data_mem_pkt_o[268] = lce_data_cmd_i[267];
assign data_mem_pkt_o[267] = lce_data_cmd_i[266];
assign data_mem_pkt_o[266] = lce_data_cmd_i[265];
assign data_mem_pkt_o[265] = lce_data_cmd_i[264];
assign data_mem_pkt_o[264] = lce_data_cmd_i[263];
assign data_mem_pkt_o[263] = lce_data_cmd_i[262];
assign data_mem_pkt_o[262] = lce_data_cmd_i[261];
assign data_mem_pkt_o[261] = lce_data_cmd_i[260];
assign data_mem_pkt_o[260] = lce_data_cmd_i[259];
assign data_mem_pkt_o[259] = lce_data_cmd_i[258];
assign data_mem_pkt_o[258] = lce_data_cmd_i[257];
assign data_mem_pkt_o[257] = lce_data_cmd_i[256];
assign data_mem_pkt_o[256] = lce_data_cmd_i[255];
assign data_mem_pkt_o[255] = lce_data_cmd_i[254];
assign data_mem_pkt_o[254] = lce_data_cmd_i[253];
assign data_mem_pkt_o[253] = lce_data_cmd_i[252];
assign data_mem_pkt_o[252] = lce_data_cmd_i[251];
assign data_mem_pkt_o[251] = lce_data_cmd_i[250];
assign data_mem_pkt_o[250] = lce_data_cmd_i[249];
assign data_mem_pkt_o[249] = lce_data_cmd_i[248];
assign data_mem_pkt_o[248] = lce_data_cmd_i[247];
assign data_mem_pkt_o[247] = lce_data_cmd_i[246];
assign data_mem_pkt_o[246] = lce_data_cmd_i[245];
assign data_mem_pkt_o[245] = lce_data_cmd_i[244];
assign data_mem_pkt_o[244] = lce_data_cmd_i[243];
assign data_mem_pkt_o[243] = lce_data_cmd_i[242];
assign data_mem_pkt_o[242] = lce_data_cmd_i[241];
assign data_mem_pkt_o[241] = lce_data_cmd_i[240];
assign data_mem_pkt_o[240] = lce_data_cmd_i[239];
assign data_mem_pkt_o[239] = lce_data_cmd_i[238];
assign data_mem_pkt_o[238] = lce_data_cmd_i[237];
assign data_mem_pkt_o[237] = lce_data_cmd_i[236];
assign data_mem_pkt_o[236] = lce_data_cmd_i[235];
assign data_mem_pkt_o[235] = lce_data_cmd_i[234];
assign data_mem_pkt_o[234] = lce_data_cmd_i[233];
assign data_mem_pkt_o[233] = lce_data_cmd_i[232];
assign data_mem_pkt_o[232] = lce_data_cmd_i[231];
assign data_mem_pkt_o[231] = lce_data_cmd_i[230];
assign data_mem_pkt_o[230] = lce_data_cmd_i[229];
assign data_mem_pkt_o[229] = lce_data_cmd_i[228];
assign data_mem_pkt_o[228] = lce_data_cmd_i[227];
assign data_mem_pkt_o[227] = lce_data_cmd_i[226];
assign data_mem_pkt_o[226] = lce_data_cmd_i[225];
assign data_mem_pkt_o[225] = lce_data_cmd_i[224];
assign data_mem_pkt_o[224] = lce_data_cmd_i[223];
assign data_mem_pkt_o[223] = lce_data_cmd_i[222];
assign data_mem_pkt_o[222] = lce_data_cmd_i[221];
assign data_mem_pkt_o[221] = lce_data_cmd_i[220];
assign data_mem_pkt_o[220] = lce_data_cmd_i[219];
assign data_mem_pkt_o[219] = lce_data_cmd_i[218];
assign data_mem_pkt_o[218] = lce_data_cmd_i[217];
assign data_mem_pkt_o[217] = lce_data_cmd_i[216];
assign data_mem_pkt_o[216] = lce_data_cmd_i[215];
assign data_mem_pkt_o[215] = lce_data_cmd_i[214];
assign data_mem_pkt_o[214] = lce_data_cmd_i[213];
assign data_mem_pkt_o[213] = lce_data_cmd_i[212];
assign data_mem_pkt_o[212] = lce_data_cmd_i[211];
assign data_mem_pkt_o[211] = lce_data_cmd_i[210];
assign data_mem_pkt_o[210] = lce_data_cmd_i[209];
assign data_mem_pkt_o[209] = lce_data_cmd_i[208];
assign data_mem_pkt_o[208] = lce_data_cmd_i[207];
assign data_mem_pkt_o[207] = lce_data_cmd_i[206];
assign data_mem_pkt_o[206] = lce_data_cmd_i[205];
assign data_mem_pkt_o[205] = lce_data_cmd_i[204];
assign data_mem_pkt_o[204] = lce_data_cmd_i[203];
assign data_mem_pkt_o[203] = lce_data_cmd_i[202];
assign data_mem_pkt_o[202] = lce_data_cmd_i[201];
assign data_mem_pkt_o[201] = lce_data_cmd_i[200];
assign data_mem_pkt_o[200] = lce_data_cmd_i[199];
assign data_mem_pkt_o[199] = lce_data_cmd_i[198];
assign data_mem_pkt_o[198] = lce_data_cmd_i[197];
assign data_mem_pkt_o[197] = lce_data_cmd_i[196];
assign data_mem_pkt_o[196] = lce_data_cmd_i[195];
assign data_mem_pkt_o[195] = lce_data_cmd_i[194];
assign data_mem_pkt_o[194] = lce_data_cmd_i[193];
assign data_mem_pkt_o[193] = lce_data_cmd_i[192];
assign data_mem_pkt_o[192] = lce_data_cmd_i[191];
assign data_mem_pkt_o[191] = lce_data_cmd_i[190];
assign data_mem_pkt_o[190] = lce_data_cmd_i[189];
assign data_mem_pkt_o[189] = lce_data_cmd_i[188];
assign data_mem_pkt_o[188] = lce_data_cmd_i[187];
assign data_mem_pkt_o[187] = lce_data_cmd_i[186];
assign data_mem_pkt_o[186] = lce_data_cmd_i[185];
assign data_mem_pkt_o[185] = lce_data_cmd_i[184];
assign data_mem_pkt_o[184] = lce_data_cmd_i[183];
assign data_mem_pkt_o[183] = lce_data_cmd_i[182];
assign data_mem_pkt_o[182] = lce_data_cmd_i[181];
assign data_mem_pkt_o[181] = lce_data_cmd_i[180];
assign data_mem_pkt_o[180] = lce_data_cmd_i[179];
assign data_mem_pkt_o[179] = lce_data_cmd_i[178];
assign data_mem_pkt_o[178] = lce_data_cmd_i[177];
assign data_mem_pkt_o[177] = lce_data_cmd_i[176];
assign data_mem_pkt_o[176] = lce_data_cmd_i[175];
assign data_mem_pkt_o[175] = lce_data_cmd_i[174];
assign data_mem_pkt_o[174] = lce_data_cmd_i[173];
assign data_mem_pkt_o[173] = lce_data_cmd_i[172];
assign data_mem_pkt_o[172] = lce_data_cmd_i[171];
assign data_mem_pkt_o[171] = lce_data_cmd_i[170];
assign data_mem_pkt_o[170] = lce_data_cmd_i[169];
assign data_mem_pkt_o[169] = lce_data_cmd_i[168];
assign data_mem_pkt_o[168] = lce_data_cmd_i[167];
assign data_mem_pkt_o[167] = lce_data_cmd_i[166];
assign data_mem_pkt_o[166] = lce_data_cmd_i[165];
assign data_mem_pkt_o[165] = lce_data_cmd_i[164];
assign data_mem_pkt_o[164] = lce_data_cmd_i[163];
assign data_mem_pkt_o[163] = lce_data_cmd_i[162];
assign data_mem_pkt_o[162] = lce_data_cmd_i[161];
assign data_mem_pkt_o[161] = lce_data_cmd_i[160];
assign data_mem_pkt_o[160] = lce_data_cmd_i[159];
assign data_mem_pkt_o[159] = lce_data_cmd_i[158];
assign data_mem_pkt_o[158] = lce_data_cmd_i[157];
assign data_mem_pkt_o[157] = lce_data_cmd_i[156];
assign data_mem_pkt_o[156] = lce_data_cmd_i[155];
assign data_mem_pkt_o[155] = lce_data_cmd_i[154];
assign data_mem_pkt_o[154] = lce_data_cmd_i[153];
assign data_mem_pkt_o[153] = lce_data_cmd_i[152];
assign data_mem_pkt_o[152] = lce_data_cmd_i[151];
assign data_mem_pkt_o[151] = lce_data_cmd_i[150];
assign data_mem_pkt_o[150] = lce_data_cmd_i[149];
assign data_mem_pkt_o[149] = lce_data_cmd_i[148];
assign data_mem_pkt_o[148] = lce_data_cmd_i[147];
assign data_mem_pkt_o[147] = lce_data_cmd_i[146];
assign data_mem_pkt_o[146] = lce_data_cmd_i[145];
assign data_mem_pkt_o[145] = lce_data_cmd_i[144];
assign data_mem_pkt_o[144] = lce_data_cmd_i[143];
assign data_mem_pkt_o[143] = lce_data_cmd_i[142];
assign data_mem_pkt_o[142] = lce_data_cmd_i[141];
assign data_mem_pkt_o[141] = lce_data_cmd_i[140];
assign data_mem_pkt_o[140] = lce_data_cmd_i[139];
assign data_mem_pkt_o[139] = lce_data_cmd_i[138];
assign data_mem_pkt_o[138] = lce_data_cmd_i[137];
assign data_mem_pkt_o[137] = lce_data_cmd_i[136];
assign data_mem_pkt_o[136] = lce_data_cmd_i[135];
assign data_mem_pkt_o[135] = lce_data_cmd_i[134];
assign data_mem_pkt_o[134] = lce_data_cmd_i[133];
assign data_mem_pkt_o[133] = lce_data_cmd_i[132];
assign data_mem_pkt_o[132] = lce_data_cmd_i[131];
assign data_mem_pkt_o[131] = lce_data_cmd_i[130];
assign data_mem_pkt_o[130] = lce_data_cmd_i[129];
assign data_mem_pkt_o[129] = lce_data_cmd_i[128];
assign data_mem_pkt_o[128] = lce_data_cmd_i[127];
assign data_mem_pkt_o[127] = lce_data_cmd_i[126];
assign data_mem_pkt_o[126] = lce_data_cmd_i[125];
assign data_mem_pkt_o[125] = lce_data_cmd_i[124];
assign data_mem_pkt_o[124] = lce_data_cmd_i[123];
assign data_mem_pkt_o[123] = lce_data_cmd_i[122];
assign data_mem_pkt_o[122] = lce_data_cmd_i[121];
assign data_mem_pkt_o[121] = lce_data_cmd_i[120];
assign data_mem_pkt_o[120] = lce_data_cmd_i[119];
assign data_mem_pkt_o[119] = lce_data_cmd_i[118];
assign data_mem_pkt_o[118] = lce_data_cmd_i[117];
assign data_mem_pkt_o[117] = lce_data_cmd_i[116];
assign data_mem_pkt_o[116] = lce_data_cmd_i[115];
assign data_mem_pkt_o[115] = lce_data_cmd_i[114];
assign data_mem_pkt_o[114] = lce_data_cmd_i[113];
assign data_mem_pkt_o[113] = lce_data_cmd_i[112];
assign data_mem_pkt_o[112] = lce_data_cmd_i[111];
assign data_mem_pkt_o[111] = lce_data_cmd_i[110];
assign data_mem_pkt_o[110] = lce_data_cmd_i[109];
assign data_mem_pkt_o[109] = lce_data_cmd_i[108];
assign data_mem_pkt_o[108] = lce_data_cmd_i[107];
assign data_mem_pkt_o[107] = lce_data_cmd_i[106];
assign data_mem_pkt_o[106] = lce_data_cmd_i[105];
assign data_mem_pkt_o[105] = lce_data_cmd_i[104];
assign data_mem_pkt_o[104] = lce_data_cmd_i[103];
assign data_mem_pkt_o[103] = lce_data_cmd_i[102];
assign data_mem_pkt_o[102] = lce_data_cmd_i[101];
assign data_mem_pkt_o[101] = lce_data_cmd_i[100];
assign data_mem_pkt_o[100] = lce_data_cmd_i[99];
assign data_mem_pkt_o[99] = lce_data_cmd_i[98];
assign data_mem_pkt_o[98] = lce_data_cmd_i[97];
assign data_mem_pkt_o[97] = lce_data_cmd_i[96];
assign data_mem_pkt_o[96] = lce_data_cmd_i[95];
assign data_mem_pkt_o[95] = lce_data_cmd_i[94];
assign data_mem_pkt_o[94] = lce_data_cmd_i[93];
assign data_mem_pkt_o[93] = lce_data_cmd_i[92];
assign data_mem_pkt_o[92] = lce_data_cmd_i[91];
assign data_mem_pkt_o[91] = lce_data_cmd_i[90];
assign data_mem_pkt_o[90] = lce_data_cmd_i[89];
assign data_mem_pkt_o[89] = lce_data_cmd_i[88];
assign data_mem_pkt_o[88] = lce_data_cmd_i[87];
assign data_mem_pkt_o[87] = lce_data_cmd_i[86];
assign data_mem_pkt_o[86] = lce_data_cmd_i[85];
assign data_mem_pkt_o[85] = lce_data_cmd_i[84];
assign data_mem_pkt_o[84] = lce_data_cmd_i[83];
assign data_mem_pkt_o[83] = lce_data_cmd_i[82];
assign data_mem_pkt_o[82] = lce_data_cmd_i[81];
assign data_mem_pkt_o[81] = lce_data_cmd_i[80];
assign data_mem_pkt_o[80] = lce_data_cmd_i[79];
assign data_mem_pkt_o[79] = lce_data_cmd_i[78];
assign data_mem_pkt_o[78] = lce_data_cmd_i[77];
assign data_mem_pkt_o[77] = lce_data_cmd_i[76];
assign data_mem_pkt_o[76] = lce_data_cmd_i[75];
assign data_mem_pkt_o[75] = lce_data_cmd_i[74];
assign data_mem_pkt_o[74] = lce_data_cmd_i[73];
assign data_mem_pkt_o[73] = lce_data_cmd_i[72];
assign data_mem_pkt_o[72] = lce_data_cmd_i[71];
assign data_mem_pkt_o[71] = lce_data_cmd_i[70];
assign data_mem_pkt_o[70] = lce_data_cmd_i[69];
assign data_mem_pkt_o[69] = lce_data_cmd_i[68];
assign data_mem_pkt_o[68] = lce_data_cmd_i[67];
assign data_mem_pkt_o[67] = lce_data_cmd_i[66];
assign data_mem_pkt_o[66] = lce_data_cmd_i[65];
assign data_mem_pkt_o[65] = lce_data_cmd_i[64];
assign data_mem_pkt_o[64] = lce_data_cmd_i[63];
assign data_mem_pkt_o[63] = lce_data_cmd_i[62];
assign data_mem_pkt_o[62] = lce_data_cmd_i[61];
assign data_mem_pkt_o[61] = lce_data_cmd_i[60];
assign data_mem_pkt_o[60] = lce_data_cmd_i[59];
assign data_mem_pkt_o[59] = lce_data_cmd_i[58];
assign data_mem_pkt_o[58] = lce_data_cmd_i[57];
assign data_mem_pkt_o[57] = lce_data_cmd_i[56];
assign data_mem_pkt_o[56] = lce_data_cmd_i[55];
assign data_mem_pkt_o[55] = lce_data_cmd_i[54];
assign data_mem_pkt_o[54] = lce_data_cmd_i[53];
assign data_mem_pkt_o[53] = lce_data_cmd_i[52];
assign data_mem_pkt_o[52] = lce_data_cmd_i[51];
assign data_mem_pkt_o[51] = lce_data_cmd_i[50];
assign data_mem_pkt_o[50] = lce_data_cmd_i[49];
assign data_mem_pkt_o[49] = lce_data_cmd_i[48];
assign data_mem_pkt_o[48] = lce_data_cmd_i[47];
assign data_mem_pkt_o[47] = lce_data_cmd_i[46];
assign data_mem_pkt_o[46] = lce_data_cmd_i[45];
assign data_mem_pkt_o[45] = lce_data_cmd_i[44];
assign data_mem_pkt_o[44] = lce_data_cmd_i[43];
assign data_mem_pkt_o[43] = lce_data_cmd_i[42];
assign data_mem_pkt_o[42] = lce_data_cmd_i[41];
assign data_mem_pkt_o[41] = lce_data_cmd_i[40];
assign data_mem_pkt_o[40] = lce_data_cmd_i[39];
assign data_mem_pkt_o[39] = lce_data_cmd_i[38];
assign data_mem_pkt_o[38] = lce_data_cmd_i[37];
assign data_mem_pkt_o[37] = lce_data_cmd_i[36];
assign data_mem_pkt_o[36] = lce_data_cmd_i[35];
assign data_mem_pkt_o[35] = lce_data_cmd_i[34];
assign data_mem_pkt_o[34] = lce_data_cmd_i[33];
assign data_mem_pkt_o[33] = lce_data_cmd_i[32];
assign data_mem_pkt_o[32] = lce_data_cmd_i[31];
assign data_mem_pkt_o[31] = lce_data_cmd_i[30];
assign data_mem_pkt_o[30] = lce_data_cmd_i[29];
assign data_mem_pkt_o[29] = lce_data_cmd_i[28];
assign data_mem_pkt_o[28] = lce_data_cmd_i[27];
assign data_mem_pkt_o[27] = lce_data_cmd_i[26];
assign data_mem_pkt_o[26] = lce_data_cmd_i[25];
assign data_mem_pkt_o[25] = lce_data_cmd_i[24];
assign data_mem_pkt_o[24] = lce_data_cmd_i[23];
assign data_mem_pkt_o[23] = lce_data_cmd_i[22];
assign data_mem_pkt_o[22] = lce_data_cmd_i[21];
assign data_mem_pkt_o[21] = lce_data_cmd_i[20];
assign data_mem_pkt_o[20] = lce_data_cmd_i[19];
assign data_mem_pkt_o[19] = lce_data_cmd_i[18];
assign data_mem_pkt_o[18] = lce_data_cmd_i[17];
assign data_mem_pkt_o[17] = lce_data_cmd_i[16];
assign data_mem_pkt_o[16] = lce_data_cmd_i[15];
assign data_mem_pkt_o[15] = lce_data_cmd_i[14];
assign data_mem_pkt_o[14] = lce_data_cmd_i[13];
assign data_mem_pkt_o[13] = lce_data_cmd_i[12];
assign data_mem_pkt_o[12] = lce_data_cmd_i[11];
assign data_mem_pkt_o[11] = lce_data_cmd_i[10];
assign data_mem_pkt_o[10] = lce_data_cmd_i[9];
assign data_mem_pkt_o[9] = lce_data_cmd_i[8];
assign data_mem_pkt_o[8] = lce_data_cmd_i[7];
assign data_mem_pkt_o[7] = lce_data_cmd_i[6];
assign data_mem_pkt_o[6] = lce_data_cmd_i[5];
assign data_mem_pkt_o[5] = lce_data_cmd_i[4];
assign data_mem_pkt_o[4] = lce_data_cmd_i[3];
assign data_mem_pkt_o[3] = lce_data_cmd_i[2];
assign data_mem_pkt_o[2] = lce_data_cmd_i[1];
assign data_mem_pkt_o[1] = lce_data_cmd_i[0];
endmodule
|
module bsg_decode_num_out_p8
(
i,
o
);
input [2:0] i;
output [7:0] o;
wire [7:0] o;
assign o = { 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b1 } << i;
endmodule
|
module bsg_round_robin_arb_inputs_p4
(
clk_i,
reset_i,
grants_en_i,
reqs_i,
grants_o,
sel_one_hot_o,
v_o,
tag_o,
yumi_i
);
input [3:0] reqs_i;
output [3:0] grants_o;
output [3:0] sel_one_hot_o;
output [1:0] tag_o;
input clk_i;
input reset_i;
input grants_en_i;
input yumi_i;
output v_o;
wire [3:0] grants_o,sel_one_hot_o;
wire [1:0] tag_o;
wire v_o,N0,N1,N2,N3,N4,N5,N6,N7,N8,N9,N10,N11,N12,N13,N14,N15,N16,N17,N18,N19,N20,
N21,N22,N23,N24,N25,N26,N27,N28,N29,N30,N31,N32,N33,N34,N35,N36,N37,N38,N39,N40,
N41,N42,N43,N44,N45,N46,N47,N48,N49,N50,N51,N52,N53,N54,N55,N56,N57,N58,N59,N60,
N61,N62,N63,N64,N65,N66,N67,N68,N69,N70,N71,N72,N73,N74,N75,N76,N77,N78,N79,N80,
N81,N82,N83,N84,N85,N86,N87,N88,N89,N90,N91,N92,N93,N94,N95,N96,N97,N98,N99,N100,
N101,N102,N103;
reg [1:0] last_r;
assign N79 = N0 & N1 & (N2 & N3);
assign N0 = ~reqs_i[1];
assign N1 = ~reqs_i[2];
assign N2 = ~reqs_i[0];
assign N3 = ~reqs_i[3];
assign N80 = reqs_i[1] & N4 & N5;
assign N4 = ~last_r[0];
assign N5 = ~last_r[1];
assign N81 = N6 & reqs_i[2] & (N7 & N8);
assign N6 = ~reqs_i[1];
assign N7 = ~last_r[0];
assign N8 = ~last_r[1];
assign N82 = N9 & N10 & (reqs_i[3] & N11) & N12;
assign N9 = ~reqs_i[1];
assign N10 = ~reqs_i[2];
assign N11 = ~last_r[0];
assign N12 = ~last_r[1];
assign N13 = N17 & N18;
assign N14 = N13 & reqs_i[0];
assign N15 = N14 & N19;
assign N16 = N15 & N20;
assign N83 = N16 & N21;
assign N17 = ~reqs_i[1];
assign N18 = ~reqs_i[2];
assign N19 = ~reqs_i[3];
assign N20 = ~last_r[0];
assign N21 = ~last_r[1];
assign N84 = reqs_i[2] & last_r[0] & N22;
assign N22 = ~last_r[1];
assign N85 = N23 & reqs_i[3] & (last_r[0] & N24);
assign N23 = ~reqs_i[2];
assign N24 = ~last_r[1];
assign N86 = N25 & reqs_i[0] & (N26 & last_r[0]) & N27;
assign N25 = ~reqs_i[2];
assign N26 = ~reqs_i[3];
assign N27 = ~last_r[1];
assign N28 = reqs_i[1] & N32;
assign N29 = N28 & N33;
assign N30 = N29 & N34;
assign N31 = N30 & last_r[0];
assign N87 = N31 & N35;
assign N32 = ~reqs_i[2];
assign N33 = ~reqs_i[0];
assign N34 = ~reqs_i[3];
assign N35 = ~last_r[1];
assign N88 = reqs_i[3] & N36 & last_r[1];
assign N36 = ~last_r[0];
assign N89 = reqs_i[0] & N37 & (N38 & last_r[1]);
assign N37 = ~reqs_i[3];
assign N38 = ~last_r[0];
assign N90 = reqs_i[1] & N39 & (N40 & N41) & last_r[1];
assign N39 = ~reqs_i[0];
assign N40 = ~reqs_i[3];
assign N41 = ~last_r[0];
assign N42 = N46 & reqs_i[2];
assign N43 = N42 & N47;
assign N44 = N43 & N48;
assign N45 = N44 & N49;
assign N91 = N45 & last_r[1];
assign N46 = ~reqs_i[1];
assign N47 = ~reqs_i[0];
assign N48 = ~reqs_i[3];
assign N49 = ~last_r[0];
assign N92 = reqs_i[0] & last_r[0] & last_r[1];
assign N93 = reqs_i[1] & N50 & (last_r[0] & last_r[1]);
assign N50 = ~reqs_i[0];
assign N94 = N51 & reqs_i[2] & (N52 & last_r[0]) & last_r[1];
assign N51 = ~reqs_i[1];
assign N52 = ~reqs_i[0];
assign N53 = N57 & N58;
assign N54 = N53 & N59;
assign N55 = N54 & reqs_i[3];
assign N56 = N55 & last_r[0];
assign N95 = N56 & last_r[1];
assign N57 = ~reqs_i[1];
assign N58 = ~reqs_i[2];
assign N59 = ~reqs_i[0];
assign sel_one_hot_o = (N60)? { 1'b0, 1'b0, 1'b0, 1'b0 } :
(N61)? { 1'b0, 1'b0, 1'b1, 1'b0 } :
(N62)? { 1'b0, 1'b1, 1'b0, 1'b0 } :
(N63)? { 1'b1, 1'b0, 1'b0, 1'b0 } :
(N64)? { 1'b0, 1'b0, 1'b0, 1'b1 } :
(N65)? { 1'b0, 1'b1, 1'b0, 1'b0 } :
(N66)? { 1'b1, 1'b0, 1'b0, 1'b0 } :
(N67)? { 1'b0, 1'b0, 1'b0, 1'b1 } :
(N68)? { 1'b0, 1'b0, 1'b1, 1'b0 } :
(N69)? { 1'b1, 1'b0, 1'b0, 1'b0 } :
(N70)? { 1'b0, 1'b0, 1'b0, 1'b1 } :
(N71)? { 1'b0, 1'b0, 1'b1, 1'b0 } :
(N72)? { 1'b0, 1'b1, 1'b0, 1'b0 } :
(N73)? { 1'b0, 1'b0, 1'b0, 1'b1 } :
(N74)? { 1'b0, 1'b0, 1'b1, 1'b0 } :
(N75)? { 1'b0, 1'b1, 1'b0, 1'b0 } :
(N76)? { 1'b1, 1'b0, 1'b0, 1'b0 } : 1'b0;
assign N60 = N79;
assign N61 = N80;
assign N62 = N81;
assign N63 = N82;
assign N64 = N83;
assign N65 = N84;
assign N66 = N85;
assign N67 = N86;
assign N68 = N87;
assign N69 = N88;
assign N70 = N89;
assign N71 = N90;
assign N72 = N91;
assign N73 = N92;
assign N74 = N93;
assign N75 = N94;
assign N76 = N95;
assign tag_o = (N60)? { 1'b0, 1'b0 } :
(N61)? { 1'b0, 1'b1 } :
(N62)? { 1'b1, 1'b0 } :
(N63)? { 1'b1, 1'b1 } :
(N64)? { 1'b0, 1'b0 } :
(N65)? { 1'b1, 1'b0 } :
(N66)? { 1'b1, 1'b1 } :
(N67)? { 1'b0, 1'b0 } :
(N68)? { 1'b0, 1'b1 } :
(N69)? { 1'b1, 1'b1 } :
(N70)? { 1'b0, 1'b0 } :
(N71)? { 1'b0, 1'b1 } :
(N72)? { 1'b1, 1'b0 } :
(N73)? { 1'b0, 1'b0 } :
(N74)? { 1'b0, 1'b1 } :
(N75)? { 1'b1, 1'b0 } :
(N76)? { 1'b1, 1'b1 } : 1'b0;
assign { N99, N98 } = (N77)? { 1'b0, 1'b0 } :
(N78)? tag_o : 1'b0;
assign N77 = reset_i;
assign N78 = N97;
assign grants_o[3] = sel_one_hot_o[3] & grants_en_i;
assign grants_o[2] = sel_one_hot_o[2] & grants_en_i;
assign grants_o[1] = sel_one_hot_o[1] & grants_en_i;
assign grants_o[0] = sel_one_hot_o[0] & grants_en_i;
assign v_o = N103 | reqs_i[0];
assign N103 = N102 | reqs_i[1];
assign N102 = reqs_i[3] | reqs_i[2];
assign N96 = ~yumi_i;
assign N97 = ~reset_i;
assign N100 = N96 & N97;
assign N101 = ~N100;
always @(posedge clk_i) begin
if(N101) begin
{ last_r[1:0] } <= { N99, N98 };
end
end
endmodule
|
module bsg_mem_1r1w_synth_width_p109_els_p8_read_write_same_addr_p0_harden_p0
(
w_clk_i,
w_reset_i,
w_v_i,
w_addr_i,
w_data_i,
r_v_i,
r_addr_i,
r_data_o
);
input [2:0] w_addr_i;
input [108:0] w_data_i;
input [2:0] r_addr_i;
output [108:0] r_data_o;
input w_clk_i;
input w_reset_i;
input w_v_i;
input r_v_i;
wire [108:0] r_data_o;
wire N0,N1,N2,N3,N4,N5,N6,N7,N8,N9,N10,N11,N12,N13,N14,N15,N16,N17,N18,N19,N20,N21,
N22,N23,N24,N25,N26,N27,N28,N29,N30,N31,N32,N33,N34,N35,N36,N37,N38,N39,N40,N41,
N42,N43,N44,N45,N46,N47,N48,N49,N50,N51,N52,N53;
reg [871:0] mem;
assign r_data_o[108] = (N17)? mem[108] :
(N19)? mem[217] :
(N21)? mem[326] :
(N23)? mem[435] :
(N18)? mem[544] :
(N20)? mem[653] :
(N22)? mem[762] :
(N24)? mem[871] : 1'b0;
assign r_data_o[107] = (N17)? mem[107] :
(N19)? mem[216] :
(N21)? mem[325] :
(N23)? mem[434] :
(N18)? mem[543] :
(N20)? mem[652] :
(N22)? mem[761] :
(N24)? mem[870] : 1'b0;
assign r_data_o[106] = (N17)? mem[106] :
(N19)? mem[215] :
(N21)? mem[324] :
(N23)? mem[433] :
(N18)? mem[542] :
(N20)? mem[651] :
(N22)? mem[760] :
(N24)? mem[869] : 1'b0;
assign r_data_o[105] = (N17)? mem[105] :
(N19)? mem[214] :
(N21)? mem[323] :
(N23)? mem[432] :
(N18)? mem[541] :
(N20)? mem[650] :
(N22)? mem[759] :
(N24)? mem[868] : 1'b0;
assign r_data_o[104] = (N17)? mem[104] :
(N19)? mem[213] :
(N21)? mem[322] :
(N23)? mem[431] :
(N18)? mem[540] :
(N20)? mem[649] :
(N22)? mem[758] :
(N24)? mem[867] : 1'b0;
assign r_data_o[103] = (N17)? mem[103] :
(N19)? mem[212] :
(N21)? mem[321] :
(N23)? mem[430] :
(N18)? mem[539] :
(N20)? mem[648] :
(N22)? mem[757] :
(N24)? mem[866] : 1'b0;
assign r_data_o[102] = (N17)? mem[102] :
(N19)? mem[211] :
(N21)? mem[320] :
(N23)? mem[429] :
(N18)? mem[538] :
(N20)? mem[647] :
(N22)? mem[756] :
(N24)? mem[865] : 1'b0;
assign r_data_o[101] = (N17)? mem[101] :
(N19)? mem[210] :
(N21)? mem[319] :
(N23)? mem[428] :
(N18)? mem[537] :
(N20)? mem[646] :
(N22)? mem[755] :
(N24)? mem[864] : 1'b0;
assign r_data_o[100] = (N17)? mem[100] :
(N19)? mem[209] :
(N21)? mem[318] :
(N23)? mem[427] :
(N18)? mem[536] :
(N20)? mem[645] :
(N22)? mem[754] :
(N24)? mem[863] : 1'b0;
assign r_data_o[99] = (N17)? mem[99] :
(N19)? mem[208] :
(N21)? mem[317] :
(N23)? mem[426] :
(N18)? mem[535] :
(N20)? mem[644] :
(N22)? mem[753] :
(N24)? mem[862] : 1'b0;
assign r_data_o[98] = (N17)? mem[98] :
(N19)? mem[207] :
(N21)? mem[316] :
(N23)? mem[425] :
(N18)? mem[534] :
(N20)? mem[643] :
(N22)? mem[752] :
(N24)? mem[861] : 1'b0;
assign r_data_o[97] = (N17)? mem[97] :
(N19)? mem[206] :
(N21)? mem[315] :
(N23)? mem[424] :
(N18)? mem[533] :
(N20)? mem[642] :
(N22)? mem[751] :
(N24)? mem[860] : 1'b0;
assign r_data_o[96] = (N17)? mem[96] :
(N19)? mem[205] :
(N21)? mem[314] :
(N23)? mem[423] :
(N18)? mem[532] :
(N20)? mem[641] :
(N22)? mem[750] :
(N24)? mem[859] : 1'b0;
assign r_data_o[95] = (N17)? mem[95] :
(N19)? mem[204] :
(N21)? mem[313] :
(N23)? mem[422] :
(N18)? mem[531] :
(N20)? mem[640] :
(N22)? mem[749] :
(N24)? mem[858] : 1'b0;
assign r_data_o[94] = (N17)? mem[94] :
(N19)? mem[203] :
(N21)? mem[312] :
(N23)? mem[421] :
(N18)? mem[530] :
(N20)? mem[639] :
(N22)? mem[748] :
(N24)? mem[857] : 1'b0;
assign r_data_o[93] = (N17)? mem[93] :
(N19)? mem[202] :
(N21)? mem[311] :
(N23)? mem[420] :
(N18)? mem[529] :
(N20)? mem[638] :
(N22)? mem[747] :
(N24)? mem[856] : 1'b0;
assign r_data_o[92] = (N17)? mem[92] :
(N19)? mem[201] :
(N21)? mem[310] :
(N23)? mem[419] :
(N18)? mem[528] :
(N20)? mem[637] :
(N22)? mem[746] :
(N24)? mem[855] : 1'b0;
assign r_data_o[91] = (N17)? mem[91] :
(N19)? mem[200] :
(N21)? mem[309] :
(N23)? mem[418] :
(N18)? mem[527] :
(N20)? mem[636] :
(N22)? mem[745] :
(N24)? mem[854] : 1'b0;
assign r_data_o[90] = (N17)? mem[90] :
(N19)? mem[199] :
(N21)? mem[308] :
(N23)? mem[417] :
(N18)? mem[526] :
(N20)? mem[635] :
(N22)? mem[744] :
(N24)? mem[853] : 1'b0;
assign r_data_o[89] = (N17)? mem[89] :
(N19)? mem[198] :
(N21)? mem[307] :
(N23)? mem[416] :
(N18)? mem[525] :
(N20)? mem[634] :
(N22)? mem[743] :
(N24)? mem[852] : 1'b0;
assign r_data_o[88] = (N17)? mem[88] :
(N19)? mem[197] :
(N21)? mem[306] :
(N23)? mem[415] :
(N18)? mem[524] :
(N20)? mem[633] :
(N22)? mem[742] :
(N24)? mem[851] : 1'b0;
assign r_data_o[87] = (N17)? mem[87] :
(N19)? mem[196] :
(N21)? mem[305] :
(N23)? mem[414] :
(N18)? mem[523] :
(N20)? mem[632] :
(N22)? mem[741] :
(N24)? mem[850] : 1'b0;
assign r_data_o[86] = (N17)? mem[86] :
(N19)? mem[195] :
(N21)? mem[304] :
(N23)? mem[413] :
(N18)? mem[522] :
(N20)? mem[631] :
(N22)? mem[740] :
(N24)? mem[849] : 1'b0;
assign r_data_o[85] = (N17)? mem[85] :
(N19)? mem[194] :
(N21)? mem[303] :
(N23)? mem[412] :
(N18)? mem[521] :
(N20)? mem[630] :
(N22)? mem[739] :
(N24)? mem[848] : 1'b0;
assign r_data_o[84] = (N17)? mem[84] :
(N19)? mem[193] :
(N21)? mem[302] :
(N23)? mem[411] :
(N18)? mem[520] :
(N20)? mem[629] :
(N22)? mem[738] :
(N24)? mem[847] : 1'b0;
assign r_data_o[83] = (N17)? mem[83] :
(N19)? mem[192] :
(N21)? mem[301] :
(N23)? mem[410] :
(N18)? mem[519] :
(N20)? mem[628] :
(N22)? mem[737] :
(N24)? mem[846] : 1'b0;
assign r_data_o[82] = (N17)? mem[82] :
(N19)? mem[191] :
(N21)? mem[300] :
(N23)? mem[409] :
(N18)? mem[518] :
(N20)? mem[627] :
(N22)? mem[736] :
(N24)? mem[845] : 1'b0;
assign r_data_o[81] = (N17)? mem[81] :
(N19)? mem[190] :
(N21)? mem[299] :
(N23)? mem[408] :
(N18)? mem[517] :
(N20)? mem[626] :
(N22)? mem[735] :
(N24)? mem[844] : 1'b0;
assign r_data_o[80] = (N17)? mem[80] :
(N19)? mem[189] :
(N21)? mem[298] :
(N23)? mem[407] :
(N18)? mem[516] :
(N20)? mem[625] :
(N22)? mem[734] :
(N24)? mem[843] : 1'b0;
assign r_data_o[79] = (N17)? mem[79] :
(N19)? mem[188] :
(N21)? mem[297] :
(N23)? mem[406] :
(N18)? mem[515] :
(N20)? mem[624] :
(N22)? mem[733] :
(N24)? mem[842] : 1'b0;
assign r_data_o[78] = (N17)? mem[78] :
(N19)? mem[187] :
(N21)? mem[296] :
(N23)? mem[405] :
(N18)? mem[514] :
(N20)? mem[623] :
(N22)? mem[732] :
(N24)? mem[841] : 1'b0;
assign r_data_o[77] = (N17)? mem[77] :
(N19)? mem[186] :
(N21)? mem[295] :
(N23)? mem[404] :
(N18)? mem[513] :
(N20)? mem[622] :
(N22)? mem[731] :
(N24)? mem[840] : 1'b0;
assign r_data_o[76] = (N17)? mem[76] :
(N19)? mem[185] :
(N21)? mem[294] :
(N23)? mem[403] :
(N18)? mem[512] :
(N20)? mem[621] :
(N22)? mem[730] :
(N24)? mem[839] : 1'b0;
assign r_data_o[75] = (N17)? mem[75] :
(N19)? mem[184] :
(N21)? mem[293] :
(N23)? mem[402] :
(N18)? mem[511] :
(N20)? mem[620] :
(N22)? mem[729] :
(N24)? mem[838] : 1'b0;
assign r_data_o[74] = (N17)? mem[74] :
(N19)? mem[183] :
(N21)? mem[292] :
(N23)? mem[401] :
(N18)? mem[510] :
(N20)? mem[619] :
(N22)? mem[728] :
(N24)? mem[837] : 1'b0;
assign r_data_o[73] = (N17)? mem[73] :
(N19)? mem[182] :
(N21)? mem[291] :
(N23)? mem[400] :
(N18)? mem[509] :
(N20)? mem[618] :
(N22)? mem[727] :
(N24)? mem[836] : 1'b0;
assign r_data_o[72] = (N17)? mem[72] :
(N19)? mem[181] :
(N21)? mem[290] :
(N23)? mem[399] :
(N18)? mem[508] :
(N20)? mem[617] :
(N22)? mem[726] :
(N24)? mem[835] : 1'b0;
assign r_data_o[71] = (N17)? mem[71] :
(N19)? mem[180] :
(N21)? mem[289] :
(N23)? mem[398] :
(N18)? mem[507] :
(N20)? mem[616] :
(N22)? mem[725] :
(N24)? mem[834] : 1'b0;
assign r_data_o[70] = (N17)? mem[70] :
(N19)? mem[179] :
(N21)? mem[288] :
(N23)? mem[397] :
(N18)? mem[506] :
(N20)? mem[615] :
(N22)? mem[724] :
(N24)? mem[833] : 1'b0;
assign r_data_o[69] = (N17)? mem[69] :
(N19)? mem[178] :
(N21)? mem[287] :
(N23)? mem[396] :
(N18)? mem[505] :
(N20)? mem[614] :
(N22)? mem[723] :
(N24)? mem[832] : 1'b0;
assign r_data_o[68] = (N17)? mem[68] :
(N19)? mem[177] :
(N21)? mem[286] :
(N23)? mem[395] :
(N18)? mem[504] :
(N20)? mem[613] :
(N22)? mem[722] :
(N24)? mem[831] : 1'b0;
assign r_data_o[67] = (N17)? mem[67] :
(N19)? mem[176] :
(N21)? mem[285] :
(N23)? mem[394] :
(N18)? mem[503] :
(N20)? mem[612] :
(N22)? mem[721] :
(N24)? mem[830] : 1'b0;
assign r_data_o[66] = (N17)? mem[66] :
(N19)? mem[175] :
(N21)? mem[284] :
(N23)? mem[393] :
(N18)? mem[502] :
(N20)? mem[611] :
(N22)? mem[720] :
(N24)? mem[829] : 1'b0;
assign r_data_o[65] = (N17)? mem[65] :
(N19)? mem[174] :
(N21)? mem[283] :
(N23)? mem[392] :
(N18)? mem[501] :
(N20)? mem[610] :
(N22)? mem[719] :
(N24)? mem[828] : 1'b0;
assign r_data_o[64] = (N17)? mem[64] :
(N19)? mem[173] :
(N21)? mem[282] :
(N23)? mem[391] :
(N18)? mem[500] :
(N20)? mem[609] :
(N22)? mem[718] :
(N24)? mem[827] : 1'b0;
assign r_data_o[63] = (N17)? mem[63] :
(N19)? mem[172] :
(N21)? mem[281] :
(N23)? mem[390] :
(N18)? mem[499] :
(N20)? mem[608] :
(N22)? mem[717] :
(N24)? mem[826] : 1'b0;
assign r_data_o[62] = (N17)? mem[62] :
(N19)? mem[171] :
(N21)? mem[280] :
(N23)? mem[389] :
(N18)? mem[498] :
(N20)? mem[607] :
(N22)? mem[716] :
(N24)? mem[825] : 1'b0;
assign r_data_o[61] = (N17)? mem[61] :
(N19)? mem[170] :
(N21)? mem[279] :
(N23)? mem[388] :
(N18)? mem[497] :
(N20)? mem[606] :
(N22)? mem[715] :
(N24)? mem[824] : 1'b0;
assign r_data_o[60] = (N17)? mem[60] :
(N19)? mem[169] :
(N21)? mem[278] :
(N23)? mem[387] :
(N18)? mem[496] :
(N20)? mem[605] :
(N22)? mem[714] :
(N24)? mem[823] : 1'b0;
assign r_data_o[59] = (N17)? mem[59] :
(N19)? mem[168] :
(N21)? mem[277] :
(N23)? mem[386] :
(N18)? mem[495] :
(N20)? mem[604] :
(N22)? mem[713] :
(N24)? mem[822] : 1'b0;
assign r_data_o[58] = (N17)? mem[58] :
(N19)? mem[167] :
(N21)? mem[276] :
(N23)? mem[385] :
(N18)? mem[494] :
(N20)? mem[603] :
(N22)? mem[712] :
(N24)? mem[821] : 1'b0;
assign r_data_o[57] = (N17)? mem[57] :
(N19)? mem[166] :
(N21)? mem[275] :
(N23)? mem[384] :
(N18)? mem[493] :
(N20)? mem[602] :
(N22)? mem[711] :
(N24)? mem[820] : 1'b0;
assign r_data_o[56] = (N17)? mem[56] :
(N19)? mem[165] :
(N21)? mem[274] :
(N23)? mem[383] :
(N18)? mem[492] :
(N20)? mem[601] :
(N22)? mem[710] :
(N24)? mem[819] : 1'b0;
assign r_data_o[55] = (N17)? mem[55] :
(N19)? mem[164] :
(N21)? mem[273] :
(N23)? mem[382] :
(N18)? mem[491] :
(N20)? mem[600] :
(N22)? mem[709] :
(N24)? mem[818] : 1'b0;
assign r_data_o[54] = (N17)? mem[54] :
(N19)? mem[163] :
(N21)? mem[272] :
(N23)? mem[381] :
(N18)? mem[490] :
(N20)? mem[599] :
(N22)? mem[708] :
(N24)? mem[817] : 1'b0;
assign r_data_o[53] = (N17)? mem[53] :
(N19)? mem[162] :
(N21)? mem[271] :
(N23)? mem[380] :
(N18)? mem[489] :
(N20)? mem[598] :
(N22)? mem[707] :
(N24)? mem[816] : 1'b0;
assign r_data_o[52] = (N17)? mem[52] :
(N19)? mem[161] :
(N21)? mem[270] :
(N23)? mem[379] :
(N18)? mem[488] :
(N20)? mem[597] :
(N22)? mem[706] :
(N24)? mem[815] : 1'b0;
assign r_data_o[51] = (N17)? mem[51] :
(N19)? mem[160] :
(N21)? mem[269] :
(N23)? mem[378] :
(N18)? mem[487] :
(N20)? mem[596] :
(N22)? mem[705] :
(N24)? mem[814] : 1'b0;
assign r_data_o[50] = (N17)? mem[50] :
(N19)? mem[159] :
(N21)? mem[268] :
(N23)? mem[377] :
(N18)? mem[486] :
(N20)? mem[595] :
(N22)? mem[704] :
(N24)? mem[813] : 1'b0;
assign r_data_o[49] = (N17)? mem[49] :
(N19)? mem[158] :
(N21)? mem[267] :
(N23)? mem[376] :
(N18)? mem[485] :
(N20)? mem[594] :
(N22)? mem[703] :
(N24)? mem[812] : 1'b0;
assign r_data_o[48] = (N17)? mem[48] :
(N19)? mem[157] :
(N21)? mem[266] :
(N23)? mem[375] :
(N18)? mem[484] :
(N20)? mem[593] :
(N22)? mem[702] :
(N24)? mem[811] : 1'b0;
assign r_data_o[47] = (N17)? mem[47] :
(N19)? mem[156] :
(N21)? mem[265] :
(N23)? mem[374] :
(N18)? mem[483] :
(N20)? mem[592] :
(N22)? mem[701] :
(N24)? mem[810] : 1'b0;
assign r_data_o[46] = (N17)? mem[46] :
(N19)? mem[155] :
(N21)? mem[264] :
(N23)? mem[373] :
(N18)? mem[482] :
(N20)? mem[591] :
(N22)? mem[700] :
(N24)? mem[809] : 1'b0;
assign r_data_o[45] = (N17)? mem[45] :
(N19)? mem[154] :
(N21)? mem[263] :
(N23)? mem[372] :
(N18)? mem[481] :
(N20)? mem[590] :
(N22)? mem[699] :
(N24)? mem[808] : 1'b0;
assign r_data_o[44] = (N17)? mem[44] :
(N19)? mem[153] :
(N21)? mem[262] :
(N23)? mem[371] :
(N18)? mem[480] :
(N20)? mem[589] :
(N22)? mem[698] :
(N24)? mem[807] : 1'b0;
assign r_data_o[43] = (N17)? mem[43] :
(N19)? mem[152] :
(N21)? mem[261] :
(N23)? mem[370] :
(N18)? mem[479] :
(N20)? mem[588] :
(N22)? mem[697] :
(N24)? mem[806] : 1'b0;
assign r_data_o[42] = (N17)? mem[42] :
(N19)? mem[151] :
(N21)? mem[260] :
(N23)? mem[369] :
(N18)? mem[478] :
(N20)? mem[587] :
(N22)? mem[696] :
(N24)? mem[805] : 1'b0;
assign r_data_o[41] = (N17)? mem[41] :
(N19)? mem[150] :
(N21)? mem[259] :
(N23)? mem[368] :
(N18)? mem[477] :
(N20)? mem[586] :
(N22)? mem[695] :
(N24)? mem[804] : 1'b0;
assign r_data_o[40] = (N17)? mem[40] :
(N19)? mem[149] :
(N21)? mem[258] :
(N23)? mem[367] :
(N18)? mem[476] :
(N20)? mem[585] :
(N22)? mem[694] :
(N24)? mem[803] : 1'b0;
assign r_data_o[39] = (N17)? mem[39] :
(N19)? mem[148] :
(N21)? mem[257] :
(N23)? mem[366] :
(N18)? mem[475] :
(N20)? mem[584] :
(N22)? mem[693] :
(N24)? mem[802] : 1'b0;
assign r_data_o[38] = (N17)? mem[38] :
(N19)? mem[147] :
(N21)? mem[256] :
(N23)? mem[365] :
(N18)? mem[474] :
(N20)? mem[583] :
(N22)? mem[692] :
(N24)? mem[801] : 1'b0;
assign r_data_o[37] = (N17)? mem[37] :
(N19)? mem[146] :
(N21)? mem[255] :
(N23)? mem[364] :
(N18)? mem[473] :
(N20)? mem[582] :
(N22)? mem[691] :
(N24)? mem[800] : 1'b0;
assign r_data_o[36] = (N17)? mem[36] :
(N19)? mem[145] :
(N21)? mem[254] :
(N23)? mem[363] :
(N18)? mem[472] :
(N20)? mem[581] :
(N22)? mem[690] :
(N24)? mem[799] : 1'b0;
assign r_data_o[35] = (N17)? mem[35] :
(N19)? mem[144] :
(N21)? mem[253] :
(N23)? mem[362] :
(N18)? mem[471] :
(N20)? mem[580] :
(N22)? mem[689] :
(N24)? mem[798] : 1'b0;
assign r_data_o[34] = (N17)? mem[34] :
(N19)? mem[143] :
(N21)? mem[252] :
(N23)? mem[361] :
(N18)? mem[470] :
(N20)? mem[579] :
(N22)? mem[688] :
(N24)? mem[797] : 1'b0;
assign r_data_o[33] = (N17)? mem[33] :
(N19)? mem[142] :
(N21)? mem[251] :
(N23)? mem[360] :
(N18)? mem[469] :
(N20)? mem[578] :
(N22)? mem[687] :
(N24)? mem[796] : 1'b0;
assign r_data_o[32] = (N17)? mem[32] :
(N19)? mem[141] :
(N21)? mem[250] :
(N23)? mem[359] :
(N18)? mem[468] :
(N20)? mem[577] :
(N22)? mem[686] :
(N24)? mem[795] : 1'b0;
assign r_data_o[31] = (N17)? mem[31] :
(N19)? mem[140] :
(N21)? mem[249] :
(N23)? mem[358] :
(N18)? mem[467] :
(N20)? mem[576] :
(N22)? mem[685] :
(N24)? mem[794] : 1'b0;
assign r_data_o[30] = (N17)? mem[30] :
(N19)? mem[139] :
(N21)? mem[248] :
(N23)? mem[357] :
(N18)? mem[466] :
(N20)? mem[575] :
(N22)? mem[684] :
(N24)? mem[793] : 1'b0;
assign r_data_o[29] = (N17)? mem[29] :
(N19)? mem[138] :
(N21)? mem[247] :
(N23)? mem[356] :
(N18)? mem[465] :
(N20)? mem[574] :
(N22)? mem[683] :
(N24)? mem[792] : 1'b0;
assign r_data_o[28] = (N17)? mem[28] :
(N19)? mem[137] :
(N21)? mem[246] :
(N23)? mem[355] :
(N18)? mem[464] :
(N20)? mem[573] :
(N22)? mem[682] :
(N24)? mem[791] : 1'b0;
assign r_data_o[27] = (N17)? mem[27] :
(N19)? mem[136] :
(N21)? mem[245] :
(N23)? mem[354] :
(N18)? mem[463] :
(N20)? mem[572] :
(N22)? mem[681] :
(N24)? mem[790] : 1'b0;
assign r_data_o[26] = (N17)? mem[26] :
(N19)? mem[135] :
(N21)? mem[244] :
(N23)? mem[353] :
(N18)? mem[462] :
(N20)? mem[571] :
(N22)? mem[680] :
(N24)? mem[789] : 1'b0;
assign r_data_o[25] = (N17)? mem[25] :
(N19)? mem[134] :
(N21)? mem[243] :
(N23)? mem[352] :
(N18)? mem[461] :
(N20)? mem[570] :
(N22)? mem[679] :
(N24)? mem[788] : 1'b0;
assign r_data_o[24] = (N17)? mem[24] :
(N19)? mem[133] :
(N21)? mem[242] :
(N23)? mem[351] :
(N18)? mem[460] :
(N20)? mem[569] :
(N22)? mem[678] :
(N24)? mem[787] : 1'b0;
assign r_data_o[23] = (N17)? mem[23] :
(N19)? mem[132] :
(N21)? mem[241] :
(N23)? mem[350] :
(N18)? mem[459] :
(N20)? mem[568] :
(N22)? mem[677] :
(N24)? mem[786] : 1'b0;
assign r_data_o[22] = (N17)? mem[22] :
(N19)? mem[131] :
(N21)? mem[240] :
(N23)? mem[349] :
(N18)? mem[458] :
(N20)? mem[567] :
(N22)? mem[676] :
(N24)? mem[785] : 1'b0;
assign r_data_o[21] = (N17)? mem[21] :
(N19)? mem[130] :
(N21)? mem[239] :
(N23)? mem[348] :
(N18)? mem[457] :
(N20)? mem[566] :
(N22)? mem[675] :
(N24)? mem[784] : 1'b0;
assign r_data_o[20] = (N17)? mem[20] :
(N19)? mem[129] :
(N21)? mem[238] :
(N23)? mem[347] :
(N18)? mem[456] :
(N20)? mem[565] :
(N22)? mem[674] :
(N24)? mem[783] : 1'b0;
assign r_data_o[19] = (N17)? mem[19] :
(N19)? mem[128] :
(N21)? mem[237] :
(N23)? mem[346] :
(N18)? mem[455] :
(N20)? mem[564] :
(N22)? mem[673] :
(N24)? mem[782] : 1'b0;
assign r_data_o[18] = (N17)? mem[18] :
(N19)? mem[127] :
(N21)? mem[236] :
(N23)? mem[345] :
(N18)? mem[454] :
(N20)? mem[563] :
(N22)? mem[672] :
(N24)? mem[781] : 1'b0;
assign r_data_o[17] = (N17)? mem[17] :
(N19)? mem[126] :
(N21)? mem[235] :
(N23)? mem[344] :
(N18)? mem[453] :
(N20)? mem[562] :
(N22)? mem[671] :
(N24)? mem[780] : 1'b0;
assign r_data_o[16] = (N17)? mem[16] :
(N19)? mem[125] :
(N21)? mem[234] :
(N23)? mem[343] :
(N18)? mem[452] :
(N20)? mem[561] :
(N22)? mem[670] :
(N24)? mem[779] : 1'b0;
assign r_data_o[15] = (N17)? mem[15] :
(N19)? mem[124] :
(N21)? mem[233] :
(N23)? mem[342] :
(N18)? mem[451] :
(N20)? mem[560] :
(N22)? mem[669] :
(N24)? mem[778] : 1'b0;
assign r_data_o[14] = (N17)? mem[14] :
(N19)? mem[123] :
(N21)? mem[232] :
(N23)? mem[341] :
(N18)? mem[450] :
(N20)? mem[559] :
(N22)? mem[668] :
(N24)? mem[777] : 1'b0;
assign r_data_o[13] = (N17)? mem[13] :
(N19)? mem[122] :
(N21)? mem[231] :
(N23)? mem[340] :
(N18)? mem[449] :
(N20)? mem[558] :
(N22)? mem[667] :
(N24)? mem[776] : 1'b0;
assign r_data_o[12] = (N17)? mem[12] :
(N19)? mem[121] :
(N21)? mem[230] :
(N23)? mem[339] :
(N18)? mem[448] :
(N20)? mem[557] :
(N22)? mem[666] :
(N24)? mem[775] : 1'b0;
assign r_data_o[11] = (N17)? mem[11] :
(N19)? mem[120] :
(N21)? mem[229] :
(N23)? mem[338] :
(N18)? mem[447] :
(N20)? mem[556] :
(N22)? mem[665] :
(N24)? mem[774] : 1'b0;
assign r_data_o[10] = (N17)? mem[10] :
(N19)? mem[119] :
(N21)? mem[228] :
(N23)? mem[337] :
(N18)? mem[446] :
(N20)? mem[555] :
(N22)? mem[664] :
(N24)? mem[773] : 1'b0;
assign r_data_o[9] = (N17)? mem[9] :
(N19)? mem[118] :
(N21)? mem[227] :
(N23)? mem[336] :
(N18)? mem[445] :
(N20)? mem[554] :
(N22)? mem[663] :
(N24)? mem[772] : 1'b0;
assign r_data_o[8] = (N17)? mem[8] :
(N19)? mem[117] :
(N21)? mem[226] :
(N23)? mem[335] :
(N18)? mem[444] :
(N20)? mem[553] :
(N22)? mem[662] :
(N24)? mem[771] : 1'b0;
assign r_data_o[7] = (N17)? mem[7] :
(N19)? mem[116] :
(N21)? mem[225] :
(N23)? mem[334] :
(N18)? mem[443] :
(N20)? mem[552] :
(N22)? mem[661] :
(N24)? mem[770] : 1'b0;
assign r_data_o[6] = (N17)? mem[6] :
(N19)? mem[115] :
(N21)? mem[224] :
(N23)? mem[333] :
(N18)? mem[442] :
(N20)? mem[551] :
(N22)? mem[660] :
(N24)? mem[769] : 1'b0;
assign r_data_o[5] = (N17)? mem[5] :
(N19)? mem[114] :
(N21)? mem[223] :
(N23)? mem[332] :
(N18)? mem[441] :
(N20)? mem[550] :
(N22)? mem[659] :
(N24)? mem[768] : 1'b0;
assign r_data_o[4] = (N17)? mem[4] :
(N19)? mem[113] :
(N21)? mem[222] :
(N23)? mem[331] :
(N18)? mem[440] :
(N20)? mem[549] :
(N22)? mem[658] :
(N24)? mem[767] : 1'b0;
assign r_data_o[3] = (N17)? mem[3] :
(N19)? mem[112] :
(N21)? mem[221] :
(N23)? mem[330] :
(N18)? mem[439] :
(N20)? mem[548] :
(N22)? mem[657] :
(N24)? mem[766] : 1'b0;
assign r_data_o[2] = (N17)? mem[2] :
(N19)? mem[111] :
(N21)? mem[220] :
(N23)? mem[329] :
(N18)? mem[438] :
(N20)? mem[547] :
(N22)? mem[656] :
(N24)? mem[765] : 1'b0;
assign r_data_o[1] = (N17)? mem[1] :
(N19)? mem[110] :
(N21)? mem[219] :
(N23)? mem[328] :
(N18)? mem[437] :
(N20)? mem[546] :
(N22)? mem[655] :
(N24)? mem[764] : 1'b0;
assign r_data_o[0] = (N17)? mem[0] :
(N19)? mem[109] :
(N21)? mem[218] :
(N23)? mem[327] :
(N18)? mem[436] :
(N20)? mem[545] :
(N22)? mem[654] :
(N24)? mem[763] : 1'b0;
assign N50 = w_addr_i[0] & w_addr_i[1];
assign N33 = N50 & w_addr_i[2];
assign N51 = N0 & w_addr_i[1];
assign N0 = ~w_addr_i[0];
assign N32 = N51 & w_addr_i[2];
assign N52 = w_addr_i[0] & N1;
assign N1 = ~w_addr_i[1];
assign N31 = N52 & w_addr_i[2];
assign N53 = N2 & N3;
assign N2 = ~w_addr_i[0];
assign N3 = ~w_addr_i[1];
assign N30 = N53 & w_addr_i[2];
assign N29 = N50 & N4;
assign N4 = ~w_addr_i[2];
assign N28 = N51 & N5;
assign N5 = ~w_addr_i[2];
assign N27 = N52 & N6;
assign N6 = ~w_addr_i[2];
assign N26 = N53 & N7;
assign N7 = ~w_addr_i[2];
assign { N49, N48, N47, N46, N45, N44, N43, N42, N41, N40, N39, N38, N37, N36, N35, N34 } = (N8)? { N33, N33, N32, N32, N31, N31, N30, N30, N29, N29, N28, N28, N27, N27, N26, N26 } :
(N9)? { 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0 } : 1'b0;
assign N8 = w_v_i;
assign N9 = N25;
assign N10 = ~r_addr_i[0];
assign N11 = ~r_addr_i[1];
assign N12 = N10 & N11;
assign N13 = N10 & r_addr_i[1];
assign N14 = r_addr_i[0] & N11;
assign N15 = r_addr_i[0] & r_addr_i[1];
assign N16 = ~r_addr_i[2];
assign N17 = N12 & N16;
assign N18 = N12 & r_addr_i[2];
assign N19 = N14 & N16;
assign N20 = N14 & r_addr_i[2];
assign N21 = N13 & N16;
assign N22 = N13 & r_addr_i[2];
assign N23 = N15 & N16;
assign N24 = N15 & r_addr_i[2];
assign N25 = ~w_v_i;
always @(posedge w_clk_i) begin
if(N48) begin
{ mem[871:773], mem[763:763] } <= { w_data_i[108:10], w_data_i[0:0] };
end
if(N49) begin
{ mem[772:764] } <= { w_data_i[9:1] };
end
if(N46) begin
{ mem[762:664], mem[654:654] } <= { w_data_i[108:10], w_data_i[0:0] };
end
if(N47) begin
{ mem[663:655] } <= { w_data_i[9:1] };
end
if(N44) begin
{ mem[653:555], mem[545:545] } <= { w_data_i[108:10], w_data_i[0:0] };
end
if(N45) begin
{ mem[554:546] } <= { w_data_i[9:1] };
end
if(N42) begin
{ mem[544:446], mem[436:436] } <= { w_data_i[108:10], w_data_i[0:0] };
end
if(N43) begin
{ mem[445:437] } <= { w_data_i[9:1] };
end
if(N40) begin
{ mem[435:337], mem[327:327] } <= { w_data_i[108:10], w_data_i[0:0] };
end
if(N41) begin
{ mem[336:328] } <= { w_data_i[9:1] };
end
if(N38) begin
{ mem[326:228], mem[218:218] } <= { w_data_i[108:10], w_data_i[0:0] };
end
if(N39) begin
{ mem[227:219] } <= { w_data_i[9:1] };
end
if(N36) begin
{ mem[217:119], mem[109:109] } <= { w_data_i[108:10], w_data_i[0:0] };
end
if(N37) begin
{ mem[118:110] } <= { w_data_i[9:1] };
end
if(N34) begin
{ mem[108:10], mem[0:0] } <= { w_data_i[108:10], w_data_i[0:0] };
end
if(N35) begin
{ mem[9:1] } <= { w_data_i[9:1] };
end
end
endmodule
|
module bsg_mux_one_hot_width_p64_els_p5
(
data_i,
sel_one_hot_i,
data_o
);
input [319:0] data_i;
input [4:0] sel_one_hot_i;
output [63:0] data_o;
wire [63:0] data_o;
wire N0,N1,N2,N3,N4,N5,N6,N7,N8,N9,N10,N11,N12,N13,N14,N15,N16,N17,N18,N19,N20,N21,
N22,N23,N24,N25,N26,N27,N28,N29,N30,N31,N32,N33,N34,N35,N36,N37,N38,N39,N40,N41,
N42,N43,N44,N45,N46,N47,N48,N49,N50,N51,N52,N53,N54,N55,N56,N57,N58,N59,N60,N61,
N62,N63,N64,N65,N66,N67,N68,N69,N70,N71,N72,N73,N74,N75,N76,N77,N78,N79,N80,N81,
N82,N83,N84,N85,N86,N87,N88,N89,N90,N91,N92,N93,N94,N95,N96,N97,N98,N99,N100,N101,
N102,N103,N104,N105,N106,N107,N108,N109,N110,N111,N112,N113,N114,N115,N116,N117,
N118,N119,N120,N121,N122,N123,N124,N125,N126,N127,N128,N129,N130,N131,N132,N133,
N134,N135,N136,N137,N138,N139,N140,N141,N142,N143,N144,N145,N146,N147,N148,N149,
N150,N151,N152,N153,N154,N155,N156,N157,N158,N159,N160,N161,N162,N163,N164,N165,
N166,N167,N168,N169,N170,N171,N172,N173,N174,N175,N176,N177,N178,N179,N180,N181,
N182,N183,N184,N185,N186,N187,N188,N189,N190,N191;
wire [319:0] data_masked;
assign data_masked[63] = data_i[63] & sel_one_hot_i[0];
assign data_masked[62] = data_i[62] & sel_one_hot_i[0];
assign data_masked[61] = data_i[61] & sel_one_hot_i[0];
assign data_masked[60] = data_i[60] & sel_one_hot_i[0];
assign data_masked[59] = data_i[59] & sel_one_hot_i[0];
assign data_masked[58] = data_i[58] & sel_one_hot_i[0];
assign data_masked[57] = data_i[57] & sel_one_hot_i[0];
assign data_masked[56] = data_i[56] & sel_one_hot_i[0];
assign data_masked[55] = data_i[55] & sel_one_hot_i[0];
assign data_masked[54] = data_i[54] & sel_one_hot_i[0];
assign data_masked[53] = data_i[53] & sel_one_hot_i[0];
assign data_masked[52] = data_i[52] & sel_one_hot_i[0];
assign data_masked[51] = data_i[51] & sel_one_hot_i[0];
assign data_masked[50] = data_i[50] & sel_one_hot_i[0];
assign data_masked[49] = data_i[49] & sel_one_hot_i[0];
assign data_masked[48] = data_i[48] & sel_one_hot_i[0];
assign data_masked[47] = data_i[47] & sel_one_hot_i[0];
assign data_masked[46] = data_i[46] & sel_one_hot_i[0];
assign data_masked[45] = data_i[45] & sel_one_hot_i[0];
assign data_masked[44] = data_i[44] & sel_one_hot_i[0];
assign data_masked[43] = data_i[43] & sel_one_hot_i[0];
assign data_masked[42] = data_i[42] & sel_one_hot_i[0];
assign data_masked[41] = data_i[41] & sel_one_hot_i[0];
assign data_masked[40] = data_i[40] & sel_one_hot_i[0];
assign data_masked[39] = data_i[39] & sel_one_hot_i[0];
assign data_masked[38] = data_i[38] & sel_one_hot_i[0];
assign data_masked[37] = data_i[37] & sel_one_hot_i[0];
assign data_masked[36] = data_i[36] & sel_one_hot_i[0];
assign data_masked[35] = data_i[35] & sel_one_hot_i[0];
assign data_masked[34] = data_i[34] & sel_one_hot_i[0];
assign data_masked[33] = data_i[33] & sel_one_hot_i[0];
assign data_masked[32] = data_i[32] & sel_one_hot_i[0];
assign data_masked[31] = data_i[31] & sel_one_hot_i[0];
assign data_masked[30] = data_i[30] & sel_one_hot_i[0];
assign data_masked[29] = data_i[29] & sel_one_hot_i[0];
assign data_masked[28] = data_i[28] & sel_one_hot_i[0];
assign data_masked[27] = data_i[27] & sel_one_hot_i[0];
assign data_masked[26] = data_i[26] & sel_one_hot_i[0];
assign data_masked[25] = data_i[25] & sel_one_hot_i[0];
assign data_masked[24] = data_i[24] & sel_one_hot_i[0];
assign data_masked[23] = data_i[23] & sel_one_hot_i[0];
assign data_masked[22] = data_i[22] & sel_one_hot_i[0];
assign data_masked[21] = data_i[21] & sel_one_hot_i[0];
assign data_masked[20] = data_i[20] & sel_one_hot_i[0];
assign data_masked[19] = data_i[19] & sel_one_hot_i[0];
assign data_masked[18] = data_i[18] & sel_one_hot_i[0];
assign data_masked[17] = data_i[17] & sel_one_hot_i[0];
assign data_masked[16] = data_i[16] & sel_one_hot_i[0];
assign data_masked[15] = data_i[15] & sel_one_hot_i[0];
assign data_masked[14] = data_i[14] & sel_one_hot_i[0];
assign data_masked[13] = data_i[13] & sel_one_hot_i[0];
assign data_masked[12] = data_i[12] & sel_one_hot_i[0];
assign data_masked[11] = data_i[11] & sel_one_hot_i[0];
assign data_masked[10] = data_i[10] & sel_one_hot_i[0];
assign data_masked[9] = data_i[9] & sel_one_hot_i[0];
assign data_masked[8] = data_i[8] & sel_one_hot_i[0];
assign data_masked[7] = data_i[7] & sel_one_hot_i[0];
assign data_masked[6] = data_i[6] & sel_one_hot_i[0];
assign data_masked[5] = data_i[5] & sel_one_hot_i[0];
assign data_masked[4] = data_i[4] & sel_one_hot_i[0];
assign data_masked[3] = data_i[3] & sel_one_hot_i[0];
assign data_masked[2] = data_i[2] & sel_one_hot_i[0];
assign data_masked[1] = data_i[1] & sel_one_hot_i[0];
assign data_masked[0] = data_i[0] & sel_one_hot_i[0];
assign data_masked[127] = data_i[127] & sel_one_hot_i[1];
assign data_masked[126] = data_i[126] & sel_one_hot_i[1];
assign data_masked[125] = data_i[125] & sel_one_hot_i[1];
assign data_masked[124] = data_i[124] & sel_one_hot_i[1];
assign data_masked[123] = data_i[123] & sel_one_hot_i[1];
assign data_masked[122] = data_i[122] & sel_one_hot_i[1];
assign data_masked[121] = data_i[121] & sel_one_hot_i[1];
assign data_masked[120] = data_i[120] & sel_one_hot_i[1];
assign data_masked[119] = data_i[119] & sel_one_hot_i[1];
assign data_masked[118] = data_i[118] & sel_one_hot_i[1];
assign data_masked[117] = data_i[117] & sel_one_hot_i[1];
assign data_masked[116] = data_i[116] & sel_one_hot_i[1];
assign data_masked[115] = data_i[115] & sel_one_hot_i[1];
assign data_masked[114] = data_i[114] & sel_one_hot_i[1];
assign data_masked[113] = data_i[113] & sel_one_hot_i[1];
assign data_masked[112] = data_i[112] & sel_one_hot_i[1];
assign data_masked[111] = data_i[111] & sel_one_hot_i[1];
assign data_masked[110] = data_i[110] & sel_one_hot_i[1];
assign data_masked[109] = data_i[109] & sel_one_hot_i[1];
assign data_masked[108] = data_i[108] & sel_one_hot_i[1];
assign data_masked[107] = data_i[107] & sel_one_hot_i[1];
assign data_masked[106] = data_i[106] & sel_one_hot_i[1];
assign data_masked[105] = data_i[105] & sel_one_hot_i[1];
assign data_masked[104] = data_i[104] & sel_one_hot_i[1];
assign data_masked[103] = data_i[103] & sel_one_hot_i[1];
assign data_masked[102] = data_i[102] & sel_one_hot_i[1];
assign data_masked[101] = data_i[101] & sel_one_hot_i[1];
assign data_masked[100] = data_i[100] & sel_one_hot_i[1];
assign data_masked[99] = data_i[99] & sel_one_hot_i[1];
assign data_masked[98] = data_i[98] & sel_one_hot_i[1];
assign data_masked[97] = data_i[97] & sel_one_hot_i[1];
assign data_masked[96] = data_i[96] & sel_one_hot_i[1];
assign data_masked[95] = data_i[95] & sel_one_hot_i[1];
assign data_masked[94] = data_i[94] & sel_one_hot_i[1];
assign data_masked[93] = data_i[93] & sel_one_hot_i[1];
assign data_masked[92] = data_i[92] & sel_one_hot_i[1];
assign data_masked[91] = data_i[91] & sel_one_hot_i[1];
assign data_masked[90] = data_i[90] & sel_one_hot_i[1];
assign data_masked[89] = data_i[89] & sel_one_hot_i[1];
assign data_masked[88] = data_i[88] & sel_one_hot_i[1];
assign data_masked[87] = data_i[87] & sel_one_hot_i[1];
assign data_masked[86] = data_i[86] & sel_one_hot_i[1];
assign data_masked[85] = data_i[85] & sel_one_hot_i[1];
assign data_masked[84] = data_i[84] & sel_one_hot_i[1];
assign data_masked[83] = data_i[83] & sel_one_hot_i[1];
assign data_masked[82] = data_i[82] & sel_one_hot_i[1];
assign data_masked[81] = data_i[81] & sel_one_hot_i[1];
assign data_masked[80] = data_i[80] & sel_one_hot_i[1];
assign data_masked[79] = data_i[79] & sel_one_hot_i[1];
assign data_masked[78] = data_i[78] & sel_one_hot_i[1];
assign data_masked[77] = data_i[77] & sel_one_hot_i[1];
assign data_masked[76] = data_i[76] & sel_one_hot_i[1];
assign data_masked[75] = data_i[75] & sel_one_hot_i[1];
assign data_masked[74] = data_i[74] & sel_one_hot_i[1];
assign data_masked[73] = data_i[73] & sel_one_hot_i[1];
assign data_masked[72] = data_i[72] & sel_one_hot_i[1];
assign data_masked[71] = data_i[71] & sel_one_hot_i[1];
assign data_masked[70] = data_i[70] & sel_one_hot_i[1];
assign data_masked[69] = data_i[69] & sel_one_hot_i[1];
assign data_masked[68] = data_i[68] & sel_one_hot_i[1];
assign data_masked[67] = data_i[67] & sel_one_hot_i[1];
assign data_masked[66] = data_i[66] & sel_one_hot_i[1];
assign data_masked[65] = data_i[65] & sel_one_hot_i[1];
assign data_masked[64] = data_i[64] & sel_one_hot_i[1];
assign data_masked[191] = data_i[191] & sel_one_hot_i[2];
assign data_masked[190] = data_i[190] & sel_one_hot_i[2];
assign data_masked[189] = data_i[189] & sel_one_hot_i[2];
assign data_masked[188] = data_i[188] & sel_one_hot_i[2];
assign data_masked[187] = data_i[187] & sel_one_hot_i[2];
assign data_masked[186] = data_i[186] & sel_one_hot_i[2];
assign data_masked[185] = data_i[185] & sel_one_hot_i[2];
assign data_masked[184] = data_i[184] & sel_one_hot_i[2];
assign data_masked[183] = data_i[183] & sel_one_hot_i[2];
assign data_masked[182] = data_i[182] & sel_one_hot_i[2];
assign data_masked[181] = data_i[181] & sel_one_hot_i[2];
assign data_masked[180] = data_i[180] & sel_one_hot_i[2];
assign data_masked[179] = data_i[179] & sel_one_hot_i[2];
assign data_masked[178] = data_i[178] & sel_one_hot_i[2];
assign data_masked[177] = data_i[177] & sel_one_hot_i[2];
assign data_masked[176] = data_i[176] & sel_one_hot_i[2];
assign data_masked[175] = data_i[175] & sel_one_hot_i[2];
assign data_masked[174] = data_i[174] & sel_one_hot_i[2];
assign data_masked[173] = data_i[173] & sel_one_hot_i[2];
assign data_masked[172] = data_i[172] & sel_one_hot_i[2];
assign data_masked[171] = data_i[171] & sel_one_hot_i[2];
assign data_masked[170] = data_i[170] & sel_one_hot_i[2];
assign data_masked[169] = data_i[169] & sel_one_hot_i[2];
assign data_masked[168] = data_i[168] & sel_one_hot_i[2];
assign data_masked[167] = data_i[167] & sel_one_hot_i[2];
assign data_masked[166] = data_i[166] & sel_one_hot_i[2];
assign data_masked[165] = data_i[165] & sel_one_hot_i[2];
assign data_masked[164] = data_i[164] & sel_one_hot_i[2];
assign data_masked[163] = data_i[163] & sel_one_hot_i[2];
assign data_masked[162] = data_i[162] & sel_one_hot_i[2];
assign data_masked[161] = data_i[161] & sel_one_hot_i[2];
assign data_masked[160] = data_i[160] & sel_one_hot_i[2];
assign data_masked[159] = data_i[159] & sel_one_hot_i[2];
assign data_masked[158] = data_i[158] & sel_one_hot_i[2];
assign data_masked[157] = data_i[157] & sel_one_hot_i[2];
assign data_masked[156] = data_i[156] & sel_one_hot_i[2];
assign data_masked[155] = data_i[155] & sel_one_hot_i[2];
assign data_masked[154] = data_i[154] & sel_one_hot_i[2];
assign data_masked[153] = data_i[153] & sel_one_hot_i[2];
assign data_masked[152] = data_i[152] & sel_one_hot_i[2];
assign data_masked[151] = data_i[151] & sel_one_hot_i[2];
assign data_masked[150] = data_i[150] & sel_one_hot_i[2];
assign data_masked[149] = data_i[149] & sel_one_hot_i[2];
assign data_masked[148] = data_i[148] & sel_one_hot_i[2];
assign data_masked[147] = data_i[147] & sel_one_hot_i[2];
assign data_masked[146] = data_i[146] & sel_one_hot_i[2];
assign data_masked[145] = data_i[145] & sel_one_hot_i[2];
assign data_masked[144] = data_i[144] & sel_one_hot_i[2];
assign data_masked[143] = data_i[143] & sel_one_hot_i[2];
assign data_masked[142] = data_i[142] & sel_one_hot_i[2];
assign data_masked[141] = data_i[141] & sel_one_hot_i[2];
assign data_masked[140] = data_i[140] & sel_one_hot_i[2];
assign data_masked[139] = data_i[139] & sel_one_hot_i[2];
assign data_masked[138] = data_i[138] & sel_one_hot_i[2];
assign data_masked[137] = data_i[137] & sel_one_hot_i[2];
assign data_masked[136] = data_i[136] & sel_one_hot_i[2];
assign data_masked[135] = data_i[135] & sel_one_hot_i[2];
assign data_masked[134] = data_i[134] & sel_one_hot_i[2];
assign data_masked[133] = data_i[133] & sel_one_hot_i[2];
assign data_masked[132] = data_i[132] & sel_one_hot_i[2];
assign data_masked[131] = data_i[131] & sel_one_hot_i[2];
assign data_masked[130] = data_i[130] & sel_one_hot_i[2];
assign data_masked[129] = data_i[129] & sel_one_hot_i[2];
assign data_masked[128] = data_i[128] & sel_one_hot_i[2];
assign data_masked[255] = data_i[255] & sel_one_hot_i[3];
assign data_masked[254] = data_i[254] & sel_one_hot_i[3];
assign data_masked[253] = data_i[253] & sel_one_hot_i[3];
assign data_masked[252] = data_i[252] & sel_one_hot_i[3];
assign data_masked[251] = data_i[251] & sel_one_hot_i[3];
assign data_masked[250] = data_i[250] & sel_one_hot_i[3];
assign data_masked[249] = data_i[249] & sel_one_hot_i[3];
assign data_masked[248] = data_i[248] & sel_one_hot_i[3];
assign data_masked[247] = data_i[247] & sel_one_hot_i[3];
assign data_masked[246] = data_i[246] & sel_one_hot_i[3];
assign data_masked[245] = data_i[245] & sel_one_hot_i[3];
assign data_masked[244] = data_i[244] & sel_one_hot_i[3];
assign data_masked[243] = data_i[243] & sel_one_hot_i[3];
assign data_masked[242] = data_i[242] & sel_one_hot_i[3];
assign data_masked[241] = data_i[241] & sel_one_hot_i[3];
assign data_masked[240] = data_i[240] & sel_one_hot_i[3];
assign data_masked[239] = data_i[239] & sel_one_hot_i[3];
assign data_masked[238] = data_i[238] & sel_one_hot_i[3];
assign data_masked[237] = data_i[237] & sel_one_hot_i[3];
assign data_masked[236] = data_i[236] & sel_one_hot_i[3];
assign data_masked[235] = data_i[235] & sel_one_hot_i[3];
assign data_masked[234] = data_i[234] & sel_one_hot_i[3];
assign data_masked[233] = data_i[233] & sel_one_hot_i[3];
assign data_masked[232] = data_i[232] & sel_one_hot_i[3];
assign data_masked[231] = data_i[231] & sel_one_hot_i[3];
assign data_masked[230] = data_i[230] & sel_one_hot_i[3];
assign data_masked[229] = data_i[229] & sel_one_hot_i[3];
assign data_masked[228] = data_i[228] & sel_one_hot_i[3];
assign data_masked[227] = data_i[227] & sel_one_hot_i[3];
assign data_masked[226] = data_i[226] & sel_one_hot_i[3];
assign data_masked[225] = data_i[225] & sel_one_hot_i[3];
assign data_masked[224] = data_i[224] & sel_one_hot_i[3];
assign data_masked[223] = data_i[223] & sel_one_hot_i[3];
assign data_masked[222] = data_i[222] & sel_one_hot_i[3];
assign data_masked[221] = data_i[221] & sel_one_hot_i[3];
assign data_masked[220] = data_i[220] & sel_one_hot_i[3];
assign data_masked[219] = data_i[219] & sel_one_hot_i[3];
assign data_masked[218] = data_i[218] & sel_one_hot_i[3];
assign data_masked[217] = data_i[217] & sel_one_hot_i[3];
assign data_masked[216] = data_i[216] & sel_one_hot_i[3];
assign data_masked[215] = data_i[215] & sel_one_hot_i[3];
assign data_masked[214] = data_i[214] & sel_one_hot_i[3];
assign data_masked[213] = data_i[213] & sel_one_hot_i[3];
assign data_masked[212] = data_i[212] & sel_one_hot_i[3];
assign data_masked[211] = data_i[211] & sel_one_hot_i[3];
assign data_masked[210] = data_i[210] & sel_one_hot_i[3];
assign data_masked[209] = data_i[209] & sel_one_hot_i[3];
assign data_masked[208] = data_i[208] & sel_one_hot_i[3];
assign data_masked[207] = data_i[207] & sel_one_hot_i[3];
assign data_masked[206] = data_i[206] & sel_one_hot_i[3];
assign data_masked[205] = data_i[205] & sel_one_hot_i[3];
assign data_masked[204] = data_i[204] & sel_one_hot_i[3];
assign data_masked[203] = data_i[203] & sel_one_hot_i[3];
assign data_masked[202] = data_i[202] & sel_one_hot_i[3];
assign data_masked[201] = data_i[201] & sel_one_hot_i[3];
assign data_masked[200] = data_i[200] & sel_one_hot_i[3];
assign data_masked[199] = data_i[199] & sel_one_hot_i[3];
assign data_masked[198] = data_i[198] & sel_one_hot_i[3];
assign data_masked[197] = data_i[197] & sel_one_hot_i[3];
assign data_masked[196] = data_i[196] & sel_one_hot_i[3];
assign data_masked[195] = data_i[195] & sel_one_hot_i[3];
assign data_masked[194] = data_i[194] & sel_one_hot_i[3];
assign data_masked[193] = data_i[193] & sel_one_hot_i[3];
assign data_masked[192] = data_i[192] & sel_one_hot_i[3];
assign data_masked[319] = data_i[319] & sel_one_hot_i[4];
assign data_masked[318] = data_i[318] & sel_one_hot_i[4];
assign data_masked[317] = data_i[317] & sel_one_hot_i[4];
assign data_masked[316] = data_i[316] & sel_one_hot_i[4];
assign data_masked[315] = data_i[315] & sel_one_hot_i[4];
assign data_masked[314] = data_i[314] & sel_one_hot_i[4];
assign data_masked[313] = data_i[313] & sel_one_hot_i[4];
assign data_masked[312] = data_i[312] & sel_one_hot_i[4];
assign data_masked[311] = data_i[311] & sel_one_hot_i[4];
assign data_masked[310] = data_i[310] & sel_one_hot_i[4];
assign data_masked[309] = data_i[309] & sel_one_hot_i[4];
assign data_masked[308] = data_i[308] & sel_one_hot_i[4];
assign data_masked[307] = data_i[307] & sel_one_hot_i[4];
assign data_masked[306] = data_i[306] & sel_one_hot_i[4];
assign data_masked[305] = data_i[305] & sel_one_hot_i[4];
assign data_masked[304] = data_i[304] & sel_one_hot_i[4];
assign data_masked[303] = data_i[303] & sel_one_hot_i[4];
assign data_masked[302] = data_i[302] & sel_one_hot_i[4];
assign data_masked[301] = data_i[301] & sel_one_hot_i[4];
assign data_masked[300] = data_i[300] & sel_one_hot_i[4];
assign data_masked[299] = data_i[299] & sel_one_hot_i[4];
assign data_masked[298] = data_i[298] & sel_one_hot_i[4];
assign data_masked[297] = data_i[297] & sel_one_hot_i[4];
assign data_masked[296] = data_i[296] & sel_one_hot_i[4];
assign data_masked[295] = data_i[295] & sel_one_hot_i[4];
assign data_masked[294] = data_i[294] & sel_one_hot_i[4];
assign data_masked[293] = data_i[293] & sel_one_hot_i[4];
assign data_masked[292] = data_i[292] & sel_one_hot_i[4];
assign data_masked[291] = data_i[291] & sel_one_hot_i[4];
assign data_masked[290] = data_i[290] & sel_one_hot_i[4];
assign data_masked[289] = data_i[289] & sel_one_hot_i[4];
assign data_masked[288] = data_i[288] & sel_one_hot_i[4];
assign data_masked[287] = data_i[287] & sel_one_hot_i[4];
assign data_masked[286] = data_i[286] & sel_one_hot_i[4];
assign data_masked[285] = data_i[285] & sel_one_hot_i[4];
assign data_masked[284] = data_i[284] & sel_one_hot_i[4];
assign data_masked[283] = data_i[283] & sel_one_hot_i[4];
assign data_masked[282] = data_i[282] & sel_one_hot_i[4];
assign data_masked[281] = data_i[281] & sel_one_hot_i[4];
assign data_masked[280] = data_i[280] & sel_one_hot_i[4];
assign data_masked[279] = data_i[279] & sel_one_hot_i[4];
assign data_masked[278] = data_i[278] & sel_one_hot_i[4];
assign data_masked[277] = data_i[277] & sel_one_hot_i[4];
assign data_masked[276] = data_i[276] & sel_one_hot_i[4];
assign data_masked[275] = data_i[275] & sel_one_hot_i[4];
assign data_masked[274] = data_i[274] & sel_one_hot_i[4];
assign data_masked[273] = data_i[273] & sel_one_hot_i[4];
assign data_masked[272] = data_i[272] & sel_one_hot_i[4];
assign data_masked[271] = data_i[271] & sel_one_hot_i[4];
assign data_masked[270] = data_i[270] & sel_one_hot_i[4];
assign data_masked[269] = data_i[269] & sel_one_hot_i[4];
assign data_masked[268] = data_i[268] & sel_one_hot_i[4];
assign data_masked[267] = data_i[267] & sel_one_hot_i[4];
assign data_masked[266] = data_i[266] & sel_one_hot_i[4];
assign data_masked[265] = data_i[265] & sel_one_hot_i[4];
assign data_masked[264] = data_i[264] & sel_one_hot_i[4];
assign data_masked[263] = data_i[263] & sel_one_hot_i[4];
assign data_masked[262] = data_i[262] & sel_one_hot_i[4];
assign data_masked[261] = data_i[261] & sel_one_hot_i[4];
assign data_masked[260] = data_i[260] & sel_one_hot_i[4];
assign data_masked[259] = data_i[259] & sel_one_hot_i[4];
assign data_masked[258] = data_i[258] & sel_one_hot_i[4];
assign data_masked[257] = data_i[257] & sel_one_hot_i[4];
assign data_masked[256] = data_i[256] & sel_one_hot_i[4];
assign data_o[0] = N2 | data_masked[0];
assign N2 = N1 | data_masked[64];
assign N1 = N0 | data_masked[128];
assign N0 = data_masked[256] | data_masked[192];
assign data_o[1] = N5 | data_masked[1];
assign N5 = N4 | data_masked[65];
assign N4 = N3 | data_masked[129];
assign N3 = data_masked[257] | data_masked[193];
assign data_o[2] = N8 | data_masked[2];
assign N8 = N7 | data_masked[66];
assign N7 = N6 | data_masked[130];
assign N6 = data_masked[258] | data_masked[194];
assign data_o[3] = N11 | data_masked[3];
assign N11 = N10 | data_masked[67];
assign N10 = N9 | data_masked[131];
assign N9 = data_masked[259] | data_masked[195];
assign data_o[4] = N14 | data_masked[4];
assign N14 = N13 | data_masked[68];
assign N13 = N12 | data_masked[132];
assign N12 = data_masked[260] | data_masked[196];
assign data_o[5] = N17 | data_masked[5];
assign N17 = N16 | data_masked[69];
assign N16 = N15 | data_masked[133];
assign N15 = data_masked[261] | data_masked[197];
assign data_o[6] = N20 | data_masked[6];
assign N20 = N19 | data_masked[70];
assign N19 = N18 | data_masked[134];
assign N18 = data_masked[262] | data_masked[198];
assign data_o[7] = N23 | data_masked[7];
assign N23 = N22 | data_masked[71];
assign N22 = N21 | data_masked[135];
assign N21 = data_masked[263] | data_masked[199];
assign data_o[8] = N26 | data_masked[8];
assign N26 = N25 | data_masked[72];
assign N25 = N24 | data_masked[136];
assign N24 = data_masked[264] | data_masked[200];
assign data_o[9] = N29 | data_masked[9];
assign N29 = N28 | data_masked[73];
assign N28 = N27 | data_masked[137];
assign N27 = data_masked[265] | data_masked[201];
assign data_o[10] = N32 | data_masked[10];
assign N32 = N31 | data_masked[74];
assign N31 = N30 | data_masked[138];
assign N30 = data_masked[266] | data_masked[202];
assign data_o[11] = N35 | data_masked[11];
assign N35 = N34 | data_masked[75];
assign N34 = N33 | data_masked[139];
assign N33 = data_masked[267] | data_masked[203];
assign data_o[12] = N38 | data_masked[12];
assign N38 = N37 | data_masked[76];
assign N37 = N36 | data_masked[140];
assign N36 = data_masked[268] | data_masked[204];
assign data_o[13] = N41 | data_masked[13];
assign N41 = N40 | data_masked[77];
assign N40 = N39 | data_masked[141];
assign N39 = data_masked[269] | data_masked[205];
assign data_o[14] = N44 | data_masked[14];
assign N44 = N43 | data_masked[78];
assign N43 = N42 | data_masked[142];
assign N42 = data_masked[270] | data_masked[206];
assign data_o[15] = N47 | data_masked[15];
assign N47 = N46 | data_masked[79];
assign N46 = N45 | data_masked[143];
assign N45 = data_masked[271] | data_masked[207];
assign data_o[16] = N50 | data_masked[16];
assign N50 = N49 | data_masked[80];
assign N49 = N48 | data_masked[144];
assign N48 = data_masked[272] | data_masked[208];
assign data_o[17] = N53 | data_masked[17];
assign N53 = N52 | data_masked[81];
assign N52 = N51 | data_masked[145];
assign N51 = data_masked[273] | data_masked[209];
assign data_o[18] = N56 | data_masked[18];
assign N56 = N55 | data_masked[82];
assign N55 = N54 | data_masked[146];
assign N54 = data_masked[274] | data_masked[210];
assign data_o[19] = N59 | data_masked[19];
assign N59 = N58 | data_masked[83];
assign N58 = N57 | data_masked[147];
assign N57 = data_masked[275] | data_masked[211];
assign data_o[20] = N62 | data_masked[20];
assign N62 = N61 | data_masked[84];
assign N61 = N60 | data_masked[148];
assign N60 = data_masked[276] | data_masked[212];
assign data_o[21] = N65 | data_masked[21];
assign N65 = N64 | data_masked[85];
assign N64 = N63 | data_masked[149];
assign N63 = data_masked[277] | data_masked[213];
assign data_o[22] = N68 | data_masked[22];
assign N68 = N67 | data_masked[86];
assign N67 = N66 | data_masked[150];
assign N66 = data_masked[278] | data_masked[214];
assign data_o[23] = N71 | data_masked[23];
assign N71 = N70 | data_masked[87];
assign N70 = N69 | data_masked[151];
assign N69 = data_masked[279] | data_masked[215];
assign data_o[24] = N74 | data_masked[24];
assign N74 = N73 | data_masked[88];
assign N73 = N72 | data_masked[152];
assign N72 = data_masked[280] | data_masked[216];
assign data_o[25] = N77 | data_masked[25];
assign N77 = N76 | data_masked[89];
assign N76 = N75 | data_masked[153];
assign N75 = data_masked[281] | data_masked[217];
assign data_o[26] = N80 | data_masked[26];
assign N80 = N79 | data_masked[90];
assign N79 = N78 | data_masked[154];
assign N78 = data_masked[282] | data_masked[218];
assign data_o[27] = N83 | data_masked[27];
assign N83 = N82 | data_masked[91];
assign N82 = N81 | data_masked[155];
assign N81 = data_masked[283] | data_masked[219];
assign data_o[28] = N86 | data_masked[28];
assign N86 = N85 | data_masked[92];
assign N85 = N84 | data_masked[156];
assign N84 = data_masked[284] | data_masked[220];
assign data_o[29] = N89 | data_masked[29];
assign N89 = N88 | data_masked[93];
assign N88 = N87 | data_masked[157];
assign N87 = data_masked[285] | data_masked[221];
assign data_o[30] = N92 | data_masked[30];
assign N92 = N91 | data_masked[94];
assign N91 = N90 | data_masked[158];
assign N90 = data_masked[286] | data_masked[222];
assign data_o[31] = N95 | data_masked[31];
assign N95 = N94 | data_masked[95];
assign N94 = N93 | data_masked[159];
assign N93 = data_masked[287] | data_masked[223];
assign data_o[32] = N98 | data_masked[32];
assign N98 = N97 | data_masked[96];
assign N97 = N96 | data_masked[160];
assign N96 = data_masked[288] | data_masked[224];
assign data_o[33] = N101 | data_masked[33];
assign N101 = N100 | data_masked[97];
assign N100 = N99 | data_masked[161];
assign N99 = data_masked[289] | data_masked[225];
assign data_o[34] = N104 | data_masked[34];
assign N104 = N103 | data_masked[98];
assign N103 = N102 | data_masked[162];
assign N102 = data_masked[290] | data_masked[226];
assign data_o[35] = N107 | data_masked[35];
assign N107 = N106 | data_masked[99];
assign N106 = N105 | data_masked[163];
assign N105 = data_masked[291] | data_masked[227];
assign data_o[36] = N110 | data_masked[36];
assign N110 = N109 | data_masked[100];
assign N109 = N108 | data_masked[164];
assign N108 = data_masked[292] | data_masked[228];
assign data_o[37] = N113 | data_masked[37];
assign N113 = N112 | data_masked[101];
assign N112 = N111 | data_masked[165];
assign N111 = data_masked[293] | data_masked[229];
assign data_o[38] = N116 | data_masked[38];
assign N116 = N115 | data_masked[102];
assign N115 = N114 | data_masked[166];
assign N114 = data_masked[294] | data_masked[230];
assign data_o[39] = N119 | data_masked[39];
assign N119 = N118 | data_masked[103];
assign N118 = N117 | data_masked[167];
assign N117 = data_masked[295] | data_masked[231];
assign data_o[40] = N122 | data_masked[40];
assign N122 = N121 | data_masked[104];
assign N121 = N120 | data_masked[168];
assign N120 = data_masked[296] | data_masked[232];
assign data_o[41] = N125 | data_masked[41];
assign N125 = N124 | data_masked[105];
assign N124 = N123 | data_masked[169];
assign N123 = data_masked[297] | data_masked[233];
assign data_o[42] = N128 | data_masked[42];
assign N128 = N127 | data_masked[106];
assign N127 = N126 | data_masked[170];
assign N126 = data_masked[298] | data_masked[234];
assign data_o[43] = N131 | data_masked[43];
assign N131 = N130 | data_masked[107];
assign N130 = N129 | data_masked[171];
assign N129 = data_masked[299] | data_masked[235];
assign data_o[44] = N134 | data_masked[44];
assign N134 = N133 | data_masked[108];
assign N133 = N132 | data_masked[172];
assign N132 = data_masked[300] | data_masked[236];
assign data_o[45] = N137 | data_masked[45];
assign N137 = N136 | data_masked[109];
assign N136 = N135 | data_masked[173];
assign N135 = data_masked[301] | data_masked[237];
assign data_o[46] = N140 | data_masked[46];
assign N140 = N139 | data_masked[110];
assign N139 = N138 | data_masked[174];
assign N138 = data_masked[302] | data_masked[238];
assign data_o[47] = N143 | data_masked[47];
assign N143 = N142 | data_masked[111];
assign N142 = N141 | data_masked[175];
assign N141 = data_masked[303] | data_masked[239];
assign data_o[48] = N146 | data_masked[48];
assign N146 = N145 | data_masked[112];
assign N145 = N144 | data_masked[176];
assign N144 = data_masked[304] | data_masked[240];
assign data_o[49] = N149 | data_masked[49];
assign N149 = N148 | data_masked[113];
assign N148 = N147 | data_masked[177];
assign N147 = data_masked[305] | data_masked[241];
assign data_o[50] = N152 | data_masked[50];
assign N152 = N151 | data_masked[114];
assign N151 = N150 | data_masked[178];
assign N150 = data_masked[306] | data_masked[242];
assign data_o[51] = N155 | data_masked[51];
assign N155 = N154 | data_masked[115];
assign N154 = N153 | data_masked[179];
assign N153 = data_masked[307] | data_masked[243];
assign data_o[52] = N158 | data_masked[52];
assign N158 = N157 | data_masked[116];
assign N157 = N156 | data_masked[180];
assign N156 = data_masked[308] | data_masked[244];
assign data_o[53] = N161 | data_masked[53];
assign N161 = N160 | data_masked[117];
assign N160 = N159 | data_masked[181];
assign N159 = data_masked[309] | data_masked[245];
assign data_o[54] = N164 | data_masked[54];
assign N164 = N163 | data_masked[118];
assign N163 = N162 | data_masked[182];
assign N162 = data_masked[310] | data_masked[246];
assign data_o[55] = N167 | data_masked[55];
assign N167 = N166 | data_masked[119];
assign N166 = N165 | data_masked[183];
assign N165 = data_masked[311] | data_masked[247];
assign data_o[56] = N170 | data_masked[56];
assign N170 = N169 | data_masked[120];
assign N169 = N168 | data_masked[184];
assign N168 = data_masked[312] | data_masked[248];
assign data_o[57] = N173 | data_masked[57];
assign N173 = N172 | data_masked[121];
assign N172 = N171 | data_masked[185];
assign N171 = data_masked[313] | data_masked[249];
assign data_o[58] = N176 | data_masked[58];
assign N176 = N175 | data_masked[122];
assign N175 = N174 | data_masked[186];
assign N174 = data_masked[314] | data_masked[250];
assign data_o[59] = N179 | data_masked[59];
assign N179 = N178 | data_masked[123];
assign N178 = N177 | data_masked[187];
assign N177 = data_masked[315] | data_masked[251];
assign data_o[60] = N182 | data_masked[60];
assign N182 = N181 | data_masked[124];
assign N181 = N180 | data_masked[188];
assign N180 = data_masked[316] | data_masked[252];
assign data_o[61] = N185 | data_masked[61];
assign N185 = N184 | data_masked[125];
assign N184 = N183 | data_masked[189];
assign N183 = data_masked[317] | data_masked[253];
assign data_o[62] = N188 | data_masked[62];
assign N188 = N187 | data_masked[126];
assign N187 = N186 | data_masked[190];
assign N186 = data_masked[318] | data_masked[254];
assign data_o[63] = N191 | data_masked[63];
assign N191 = N190 | data_masked[127];
assign N190 = N189 | data_masked[191];
assign N189 = data_masked[319] | data_masked[255];
endmodule
|
module bsg_circular_ptr_slots_p32_max_add_p31
(
clk,
reset_i,
add_i,
o
);
input [4:0] add_i;
output [4:0] o;
input clk;
input reset_i;
wire N0,N1,N2,N3,N4,N5,N6,N7;
wire [4:0] ptr_n;
reg [4:0] o;
assign ptr_n = o + add_i;
assign { N7, N6, N5, N4, N3 } = (N0)? { 1'b0, 1'b0, 1'b0, 1'b0, 1'b0 } :
(N1)? ptr_n : 1'b0;
assign N0 = reset_i;
assign N1 = N2;
assign N2 = ~reset_i;
always @(posedge clk) begin
if(1'b1) begin
{ o[4:0] } <= { N7, N6, N5, N4, N3 };
end
end
endmodule
|
module bsg_mem_1r1w_synth_width_p38_els_p2_read_write_same_addr_p0_harden_p0
(
w_clk_i,
w_reset_i,
w_v_i,
w_addr_i,
w_data_i,
r_v_i,
r_addr_i,
r_data_o
);
input [0:0] w_addr_i;
input [37:0] w_data_i;
input [0:0] r_addr_i;
output [37:0] r_data_o;
input w_clk_i;
input w_reset_i;
input w_v_i;
input r_v_i;
wire [37:0] r_data_o;
wire N0,N1,N2,N3,N4,N5,N7,N8;
reg [75:0] mem;
assign r_data_o[37] = (N3)? mem[37] :
(N0)? mem[75] : 1'b0;
assign N0 = r_addr_i[0];
assign r_data_o[36] = (N3)? mem[36] :
(N0)? mem[74] : 1'b0;
assign r_data_o[35] = (N3)? mem[35] :
(N0)? mem[73] : 1'b0;
assign r_data_o[34] = (N3)? mem[34] :
(N0)? mem[72] : 1'b0;
assign r_data_o[33] = (N3)? mem[33] :
(N0)? mem[71] : 1'b0;
assign r_data_o[32] = (N3)? mem[32] :
(N0)? mem[70] : 1'b0;
assign r_data_o[31] = (N3)? mem[31] :
(N0)? mem[69] : 1'b0;
assign r_data_o[30] = (N3)? mem[30] :
(N0)? mem[68] : 1'b0;
assign r_data_o[29] = (N3)? mem[29] :
(N0)? mem[67] : 1'b0;
assign r_data_o[28] = (N3)? mem[28] :
(N0)? mem[66] : 1'b0;
assign r_data_o[27] = (N3)? mem[27] :
(N0)? mem[65] : 1'b0;
assign r_data_o[26] = (N3)? mem[26] :
(N0)? mem[64] : 1'b0;
assign r_data_o[25] = (N3)? mem[25] :
(N0)? mem[63] : 1'b0;
assign r_data_o[24] = (N3)? mem[24] :
(N0)? mem[62] : 1'b0;
assign r_data_o[23] = (N3)? mem[23] :
(N0)? mem[61] : 1'b0;
assign r_data_o[22] = (N3)? mem[22] :
(N0)? mem[60] : 1'b0;
assign r_data_o[21] = (N3)? mem[21] :
(N0)? mem[59] : 1'b0;
assign r_data_o[20] = (N3)? mem[20] :
(N0)? mem[58] : 1'b0;
assign r_data_o[19] = (N3)? mem[19] :
(N0)? mem[57] : 1'b0;
assign r_data_o[18] = (N3)? mem[18] :
(N0)? mem[56] : 1'b0;
assign r_data_o[17] = (N3)? mem[17] :
(N0)? mem[55] : 1'b0;
assign r_data_o[16] = (N3)? mem[16] :
(N0)? mem[54] : 1'b0;
assign r_data_o[15] = (N3)? mem[15] :
(N0)? mem[53] : 1'b0;
assign r_data_o[14] = (N3)? mem[14] :
(N0)? mem[52] : 1'b0;
assign r_data_o[13] = (N3)? mem[13] :
(N0)? mem[51] : 1'b0;
assign r_data_o[12] = (N3)? mem[12] :
(N0)? mem[50] : 1'b0;
assign r_data_o[11] = (N3)? mem[11] :
(N0)? mem[49] : 1'b0;
assign r_data_o[10] = (N3)? mem[10] :
(N0)? mem[48] : 1'b0;
assign r_data_o[9] = (N3)? mem[9] :
(N0)? mem[47] : 1'b0;
assign r_data_o[8] = (N3)? mem[8] :
(N0)? mem[46] : 1'b0;
assign r_data_o[7] = (N3)? mem[7] :
(N0)? mem[45] : 1'b0;
assign r_data_o[6] = (N3)? mem[6] :
(N0)? mem[44] : 1'b0;
assign r_data_o[5] = (N3)? mem[5] :
(N0)? mem[43] : 1'b0;
assign r_data_o[4] = (N3)? mem[4] :
(N0)? mem[42] : 1'b0;
assign r_data_o[3] = (N3)? mem[3] :
(N0)? mem[41] : 1'b0;
assign r_data_o[2] = (N3)? mem[2] :
(N0)? mem[40] : 1'b0;
assign r_data_o[1] = (N3)? mem[1] :
(N0)? mem[39] : 1'b0;
assign r_data_o[0] = (N3)? mem[0] :
(N0)? mem[38] : 1'b0;
assign N5 = ~w_addr_i[0];
assign { N8, N7 } = (N1)? { w_addr_i[0:0], N5 } :
(N2)? { 1'b0, 1'b0 } : 1'b0;
assign N1 = w_v_i;
assign N2 = N4;
assign N3 = ~r_addr_i[0];
assign N4 = ~w_v_i;
always @(posedge w_clk_i) begin
if(N8) begin
{ mem[75:38] } <= { w_data_i[37:0] };
end
if(N7) begin
{ mem[37:0] } <= { w_data_i[37:0] };
end
end
endmodule
|
module bsg_dff_en_width_p5
(
clk_i,
data_i,
en_i,
data_o
);
input [4:0] data_i;
output [4:0] data_o;
input clk_i;
input en_i;
reg [4:0] data_o;
always @(posedge clk_i) begin
if(en_i) begin
{ data_o[4:0] } <= { data_i[4:0] };
end
end
endmodule
|
module bsg_dff_en_width_p36
(
clk_i,
data_i,
en_i,
data_o
);
input [35:0] data_i;
output [35:0] data_o;
input clk_i;
input en_i;
reg [35:0] data_o;
always @(posedge clk_i) begin
if(en_i) begin
{ data_o[35:0] } <= { data_i[35:0] };
end
end
endmodule
|
module bsg_mux_one_hot_width_p28_els_p5
(
data_i,
sel_one_hot_i,
data_o
);
input [139:0] data_i;
input [4:0] sel_one_hot_i;
output [27:0] data_o;
wire [27:0] data_o;
wire N0,N1,N2,N3,N4,N5,N6,N7,N8,N9,N10,N11,N12,N13,N14,N15,N16,N17,N18,N19,N20,N21,
N22,N23,N24,N25,N26,N27,N28,N29,N30,N31,N32,N33,N34,N35,N36,N37,N38,N39,N40,N41,
N42,N43,N44,N45,N46,N47,N48,N49,N50,N51,N52,N53,N54,N55,N56,N57,N58,N59,N60,N61,
N62,N63,N64,N65,N66,N67,N68,N69,N70,N71,N72,N73,N74,N75,N76,N77,N78,N79,N80,N81,
N82,N83;
wire [139:0] data_masked;
assign data_masked[27] = data_i[27] & sel_one_hot_i[0];
assign data_masked[26] = data_i[26] & sel_one_hot_i[0];
assign data_masked[25] = data_i[25] & sel_one_hot_i[0];
assign data_masked[24] = data_i[24] & sel_one_hot_i[0];
assign data_masked[23] = data_i[23] & sel_one_hot_i[0];
assign data_masked[22] = data_i[22] & sel_one_hot_i[0];
assign data_masked[21] = data_i[21] & sel_one_hot_i[0];
assign data_masked[20] = data_i[20] & sel_one_hot_i[0];
assign data_masked[19] = data_i[19] & sel_one_hot_i[0];
assign data_masked[18] = data_i[18] & sel_one_hot_i[0];
assign data_masked[17] = data_i[17] & sel_one_hot_i[0];
assign data_masked[16] = data_i[16] & sel_one_hot_i[0];
assign data_masked[15] = data_i[15] & sel_one_hot_i[0];
assign data_masked[14] = data_i[14] & sel_one_hot_i[0];
assign data_masked[13] = data_i[13] & sel_one_hot_i[0];
assign data_masked[12] = data_i[12] & sel_one_hot_i[0];
assign data_masked[11] = data_i[11] & sel_one_hot_i[0];
assign data_masked[10] = data_i[10] & sel_one_hot_i[0];
assign data_masked[9] = data_i[9] & sel_one_hot_i[0];
assign data_masked[8] = data_i[8] & sel_one_hot_i[0];
assign data_masked[7] = data_i[7] & sel_one_hot_i[0];
assign data_masked[6] = data_i[6] & sel_one_hot_i[0];
assign data_masked[5] = data_i[5] & sel_one_hot_i[0];
assign data_masked[4] = data_i[4] & sel_one_hot_i[0];
assign data_masked[3] = data_i[3] & sel_one_hot_i[0];
assign data_masked[2] = data_i[2] & sel_one_hot_i[0];
assign data_masked[1] = data_i[1] & sel_one_hot_i[0];
assign data_masked[0] = data_i[0] & sel_one_hot_i[0];
assign data_masked[55] = data_i[55] & sel_one_hot_i[1];
assign data_masked[54] = data_i[54] & sel_one_hot_i[1];
assign data_masked[53] = data_i[53] & sel_one_hot_i[1];
assign data_masked[52] = data_i[52] & sel_one_hot_i[1];
assign data_masked[51] = data_i[51] & sel_one_hot_i[1];
assign data_masked[50] = data_i[50] & sel_one_hot_i[1];
assign data_masked[49] = data_i[49] & sel_one_hot_i[1];
assign data_masked[48] = data_i[48] & sel_one_hot_i[1];
assign data_masked[47] = data_i[47] & sel_one_hot_i[1];
assign data_masked[46] = data_i[46] & sel_one_hot_i[1];
assign data_masked[45] = data_i[45] & sel_one_hot_i[1];
assign data_masked[44] = data_i[44] & sel_one_hot_i[1];
assign data_masked[43] = data_i[43] & sel_one_hot_i[1];
assign data_masked[42] = data_i[42] & sel_one_hot_i[1];
assign data_masked[41] = data_i[41] & sel_one_hot_i[1];
assign data_masked[40] = data_i[40] & sel_one_hot_i[1];
assign data_masked[39] = data_i[39] & sel_one_hot_i[1];
assign data_masked[38] = data_i[38] & sel_one_hot_i[1];
assign data_masked[37] = data_i[37] & sel_one_hot_i[1];
assign data_masked[36] = data_i[36] & sel_one_hot_i[1];
assign data_masked[35] = data_i[35] & sel_one_hot_i[1];
assign data_masked[34] = data_i[34] & sel_one_hot_i[1];
assign data_masked[33] = data_i[33] & sel_one_hot_i[1];
assign data_masked[32] = data_i[32] & sel_one_hot_i[1];
assign data_masked[31] = data_i[31] & sel_one_hot_i[1];
assign data_masked[30] = data_i[30] & sel_one_hot_i[1];
assign data_masked[29] = data_i[29] & sel_one_hot_i[1];
assign data_masked[28] = data_i[28] & sel_one_hot_i[1];
assign data_masked[83] = data_i[83] & sel_one_hot_i[2];
assign data_masked[82] = data_i[82] & sel_one_hot_i[2];
assign data_masked[81] = data_i[81] & sel_one_hot_i[2];
assign data_masked[80] = data_i[80] & sel_one_hot_i[2];
assign data_masked[79] = data_i[79] & sel_one_hot_i[2];
assign data_masked[78] = data_i[78] & sel_one_hot_i[2];
assign data_masked[77] = data_i[77] & sel_one_hot_i[2];
assign data_masked[76] = data_i[76] & sel_one_hot_i[2];
assign data_masked[75] = data_i[75] & sel_one_hot_i[2];
assign data_masked[74] = data_i[74] & sel_one_hot_i[2];
assign data_masked[73] = data_i[73] & sel_one_hot_i[2];
assign data_masked[72] = data_i[72] & sel_one_hot_i[2];
assign data_masked[71] = data_i[71] & sel_one_hot_i[2];
assign data_masked[70] = data_i[70] & sel_one_hot_i[2];
assign data_masked[69] = data_i[69] & sel_one_hot_i[2];
assign data_masked[68] = data_i[68] & sel_one_hot_i[2];
assign data_masked[67] = data_i[67] & sel_one_hot_i[2];
assign data_masked[66] = data_i[66] & sel_one_hot_i[2];
assign data_masked[65] = data_i[65] & sel_one_hot_i[2];
assign data_masked[64] = data_i[64] & sel_one_hot_i[2];
assign data_masked[63] = data_i[63] & sel_one_hot_i[2];
assign data_masked[62] = data_i[62] & sel_one_hot_i[2];
assign data_masked[61] = data_i[61] & sel_one_hot_i[2];
assign data_masked[60] = data_i[60] & sel_one_hot_i[2];
assign data_masked[59] = data_i[59] & sel_one_hot_i[2];
assign data_masked[58] = data_i[58] & sel_one_hot_i[2];
assign data_masked[57] = data_i[57] & sel_one_hot_i[2];
assign data_masked[56] = data_i[56] & sel_one_hot_i[2];
assign data_masked[111] = data_i[111] & sel_one_hot_i[3];
assign data_masked[110] = data_i[110] & sel_one_hot_i[3];
assign data_masked[109] = data_i[109] & sel_one_hot_i[3];
assign data_masked[108] = data_i[108] & sel_one_hot_i[3];
assign data_masked[107] = data_i[107] & sel_one_hot_i[3];
assign data_masked[106] = data_i[106] & sel_one_hot_i[3];
assign data_masked[105] = data_i[105] & sel_one_hot_i[3];
assign data_masked[104] = data_i[104] & sel_one_hot_i[3];
assign data_masked[103] = data_i[103] & sel_one_hot_i[3];
assign data_masked[102] = data_i[102] & sel_one_hot_i[3];
assign data_masked[101] = data_i[101] & sel_one_hot_i[3];
assign data_masked[100] = data_i[100] & sel_one_hot_i[3];
assign data_masked[99] = data_i[99] & sel_one_hot_i[3];
assign data_masked[98] = data_i[98] & sel_one_hot_i[3];
assign data_masked[97] = data_i[97] & sel_one_hot_i[3];
assign data_masked[96] = data_i[96] & sel_one_hot_i[3];
assign data_masked[95] = data_i[95] & sel_one_hot_i[3];
assign data_masked[94] = data_i[94] & sel_one_hot_i[3];
assign data_masked[93] = data_i[93] & sel_one_hot_i[3];
assign data_masked[92] = data_i[92] & sel_one_hot_i[3];
assign data_masked[91] = data_i[91] & sel_one_hot_i[3];
assign data_masked[90] = data_i[90] & sel_one_hot_i[3];
assign data_masked[89] = data_i[89] & sel_one_hot_i[3];
assign data_masked[88] = data_i[88] & sel_one_hot_i[3];
assign data_masked[87] = data_i[87] & sel_one_hot_i[3];
assign data_masked[86] = data_i[86] & sel_one_hot_i[3];
assign data_masked[85] = data_i[85] & sel_one_hot_i[3];
assign data_masked[84] = data_i[84] & sel_one_hot_i[3];
assign data_masked[139] = data_i[139] & sel_one_hot_i[4];
assign data_masked[138] = data_i[138] & sel_one_hot_i[4];
assign data_masked[137] = data_i[137] & sel_one_hot_i[4];
assign data_masked[136] = data_i[136] & sel_one_hot_i[4];
assign data_masked[135] = data_i[135] & sel_one_hot_i[4];
assign data_masked[134] = data_i[134] & sel_one_hot_i[4];
assign data_masked[133] = data_i[133] & sel_one_hot_i[4];
assign data_masked[132] = data_i[132] & sel_one_hot_i[4];
assign data_masked[131] = data_i[131] & sel_one_hot_i[4];
assign data_masked[130] = data_i[130] & sel_one_hot_i[4];
assign data_masked[129] = data_i[129] & sel_one_hot_i[4];
assign data_masked[128] = data_i[128] & sel_one_hot_i[4];
assign data_masked[127] = data_i[127] & sel_one_hot_i[4];
assign data_masked[126] = data_i[126] & sel_one_hot_i[4];
assign data_masked[125] = data_i[125] & sel_one_hot_i[4];
assign data_masked[124] = data_i[124] & sel_one_hot_i[4];
assign data_masked[123] = data_i[123] & sel_one_hot_i[4];
assign data_masked[122] = data_i[122] & sel_one_hot_i[4];
assign data_masked[121] = data_i[121] & sel_one_hot_i[4];
assign data_masked[120] = data_i[120] & sel_one_hot_i[4];
assign data_masked[119] = data_i[119] & sel_one_hot_i[4];
assign data_masked[118] = data_i[118] & sel_one_hot_i[4];
assign data_masked[117] = data_i[117] & sel_one_hot_i[4];
assign data_masked[116] = data_i[116] & sel_one_hot_i[4];
assign data_masked[115] = data_i[115] & sel_one_hot_i[4];
assign data_masked[114] = data_i[114] & sel_one_hot_i[4];
assign data_masked[113] = data_i[113] & sel_one_hot_i[4];
assign data_masked[112] = data_i[112] & sel_one_hot_i[4];
assign data_o[0] = N2 | data_masked[0];
assign N2 = N1 | data_masked[28];
assign N1 = N0 | data_masked[56];
assign N0 = data_masked[112] | data_masked[84];
assign data_o[1] = N5 | data_masked[1];
assign N5 = N4 | data_masked[29];
assign N4 = N3 | data_masked[57];
assign N3 = data_masked[113] | data_masked[85];
assign data_o[2] = N8 | data_masked[2];
assign N8 = N7 | data_masked[30];
assign N7 = N6 | data_masked[58];
assign N6 = data_masked[114] | data_masked[86];
assign data_o[3] = N11 | data_masked[3];
assign N11 = N10 | data_masked[31];
assign N10 = N9 | data_masked[59];
assign N9 = data_masked[115] | data_masked[87];
assign data_o[4] = N14 | data_masked[4];
assign N14 = N13 | data_masked[32];
assign N13 = N12 | data_masked[60];
assign N12 = data_masked[116] | data_masked[88];
assign data_o[5] = N17 | data_masked[5];
assign N17 = N16 | data_masked[33];
assign N16 = N15 | data_masked[61];
assign N15 = data_masked[117] | data_masked[89];
assign data_o[6] = N20 | data_masked[6];
assign N20 = N19 | data_masked[34];
assign N19 = N18 | data_masked[62];
assign N18 = data_masked[118] | data_masked[90];
assign data_o[7] = N23 | data_masked[7];
assign N23 = N22 | data_masked[35];
assign N22 = N21 | data_masked[63];
assign N21 = data_masked[119] | data_masked[91];
assign data_o[8] = N26 | data_masked[8];
assign N26 = N25 | data_masked[36];
assign N25 = N24 | data_masked[64];
assign N24 = data_masked[120] | data_masked[92];
assign data_o[9] = N29 | data_masked[9];
assign N29 = N28 | data_masked[37];
assign N28 = N27 | data_masked[65];
assign N27 = data_masked[121] | data_masked[93];
assign data_o[10] = N32 | data_masked[10];
assign N32 = N31 | data_masked[38];
assign N31 = N30 | data_masked[66];
assign N30 = data_masked[122] | data_masked[94];
assign data_o[11] = N35 | data_masked[11];
assign N35 = N34 | data_masked[39];
assign N34 = N33 | data_masked[67];
assign N33 = data_masked[123] | data_masked[95];
assign data_o[12] = N38 | data_masked[12];
assign N38 = N37 | data_masked[40];
assign N37 = N36 | data_masked[68];
assign N36 = data_masked[124] | data_masked[96];
assign data_o[13] = N41 | data_masked[13];
assign N41 = N40 | data_masked[41];
assign N40 = N39 | data_masked[69];
assign N39 = data_masked[125] | data_masked[97];
assign data_o[14] = N44 | data_masked[14];
assign N44 = N43 | data_masked[42];
assign N43 = N42 | data_masked[70];
assign N42 = data_masked[126] | data_masked[98];
assign data_o[15] = N47 | data_masked[15];
assign N47 = N46 | data_masked[43];
assign N46 = N45 | data_masked[71];
assign N45 = data_masked[127] | data_masked[99];
assign data_o[16] = N50 | data_masked[16];
assign N50 = N49 | data_masked[44];
assign N49 = N48 | data_masked[72];
assign N48 = data_masked[128] | data_masked[100];
assign data_o[17] = N53 | data_masked[17];
assign N53 = N52 | data_masked[45];
assign N52 = N51 | data_masked[73];
assign N51 = data_masked[129] | data_masked[101];
assign data_o[18] = N56 | data_masked[18];
assign N56 = N55 | data_masked[46];
assign N55 = N54 | data_masked[74];
assign N54 = data_masked[130] | data_masked[102];
assign data_o[19] = N59 | data_masked[19];
assign N59 = N58 | data_masked[47];
assign N58 = N57 | data_masked[75];
assign N57 = data_masked[131] | data_masked[103];
assign data_o[20] = N62 | data_masked[20];
assign N62 = N61 | data_masked[48];
assign N61 = N60 | data_masked[76];
assign N60 = data_masked[132] | data_masked[104];
assign data_o[21] = N65 | data_masked[21];
assign N65 = N64 | data_masked[49];
assign N64 = N63 | data_masked[77];
assign N63 = data_masked[133] | data_masked[105];
assign data_o[22] = N68 | data_masked[22];
assign N68 = N67 | data_masked[50];
assign N67 = N66 | data_masked[78];
assign N66 = data_masked[134] | data_masked[106];
assign data_o[23] = N71 | data_masked[23];
assign N71 = N70 | data_masked[51];
assign N70 = N69 | data_masked[79];
assign N69 = data_masked[135] | data_masked[107];
assign data_o[24] = N74 | data_masked[24];
assign N74 = N73 | data_masked[52];
assign N73 = N72 | data_masked[80];
assign N72 = data_masked[136] | data_masked[108];
assign data_o[25] = N77 | data_masked[25];
assign N77 = N76 | data_masked[53];
assign N76 = N75 | data_masked[81];
assign N75 = data_masked[137] | data_masked[109];
assign data_o[26] = N80 | data_masked[26];
assign N80 = N79 | data_masked[54];
assign N79 = N78 | data_masked[82];
assign N78 = data_masked[138] | data_masked[110];
assign data_o[27] = N83 | data_masked[27];
assign N83 = N82 | data_masked[55];
assign N82 = N81 | data_masked[83];
assign N81 = data_masked[139] | data_masked[111];
endmodule
|
module bsg_circular_ptr_slots_p8_max_add_p1
(
clk,
reset_i,
add_i,
o
);
input [0:0] add_i;
output [2:0] o;
input clk;
input reset_i;
wire N0,N1,N2,N3,N4,N5,N6,N7,N8;
wire [2:0] genblk1_genblk1_ptr_r_p1;
reg [2:0] o;
assign genblk1_genblk1_ptr_r_p1 = o + 1'b1;
assign { N5, N4, N3 } = (N0)? { 1'b0, 1'b0, 1'b0 } :
(N1)? genblk1_genblk1_ptr_r_p1 : 1'b0;
assign N0 = reset_i;
assign N1 = N2;
assign N2 = ~reset_i;
assign N6 = ~add_i[0];
assign N7 = N6 & N2;
assign N8 = ~N7;
always @(posedge clk) begin
if(N8) begin
{ o[2:0] } <= { N5, N4, N3 };
end
end
endmodule
|
module bsg_mux_width_p8_els_p8
(
data_i,
sel_i,
data_o
);
input [63:0] data_i;
input [2:0] sel_i;
output [7:0] data_o;
wire [7:0] data_o;
wire N0,N1,N2,N3,N4,N5,N6,N7,N8,N9,N10,N11,N12,N13,N14;
assign data_o[7] = (N7)? data_i[7] :
(N9)? data_i[15] :
(N11)? data_i[23] :
(N13)? data_i[31] :
(N8)? data_i[39] :
(N10)? data_i[47] :
(N12)? data_i[55] :
(N14)? data_i[63] : 1'b0;
assign data_o[6] = (N7)? data_i[6] :
(N9)? data_i[14] :
(N11)? data_i[22] :
(N13)? data_i[30] :
(N8)? data_i[38] :
(N10)? data_i[46] :
(N12)? data_i[54] :
(N14)? data_i[62] : 1'b0;
assign data_o[5] = (N7)? data_i[5] :
(N9)? data_i[13] :
(N11)? data_i[21] :
(N13)? data_i[29] :
(N8)? data_i[37] :
(N10)? data_i[45] :
(N12)? data_i[53] :
(N14)? data_i[61] : 1'b0;
assign data_o[4] = (N7)? data_i[4] :
(N9)? data_i[12] :
(N11)? data_i[20] :
(N13)? data_i[28] :
(N8)? data_i[36] :
(N10)? data_i[44] :
(N12)? data_i[52] :
(N14)? data_i[60] : 1'b0;
assign data_o[3] = (N7)? data_i[3] :
(N9)? data_i[11] :
(N11)? data_i[19] :
(N13)? data_i[27] :
(N8)? data_i[35] :
(N10)? data_i[43] :
(N12)? data_i[51] :
(N14)? data_i[59] : 1'b0;
assign data_o[2] = (N7)? data_i[2] :
(N9)? data_i[10] :
(N11)? data_i[18] :
(N13)? data_i[26] :
(N8)? data_i[34] :
(N10)? data_i[42] :
(N12)? data_i[50] :
(N14)? data_i[58] : 1'b0;
assign data_o[1] = (N7)? data_i[1] :
(N9)? data_i[9] :
(N11)? data_i[17] :
(N13)? data_i[25] :
(N8)? data_i[33] :
(N10)? data_i[41] :
(N12)? data_i[49] :
(N14)? data_i[57] : 1'b0;
assign data_o[0] = (N7)? data_i[0] :
(N9)? data_i[8] :
(N11)? data_i[16] :
(N13)? data_i[24] :
(N8)? data_i[32] :
(N10)? data_i[40] :
(N12)? data_i[48] :
(N14)? data_i[56] : 1'b0;
assign N0 = ~sel_i[0];
assign N1 = ~sel_i[1];
assign N2 = N0 & N1;
assign N3 = N0 & sel_i[1];
assign N4 = sel_i[0] & N1;
assign N5 = sel_i[0] & sel_i[1];
assign N6 = ~sel_i[2];
assign N7 = N2 & N6;
assign N8 = N2 & sel_i[2];
assign N9 = N4 & N6;
assign N10 = N4 & sel_i[2];
assign N11 = N3 & N6;
assign N12 = N3 & sel_i[2];
assign N13 = N5 & N6;
assign N14 = N5 & sel_i[2];
endmodule
|
module bsg_mux_one_hot_width_p38_els_p4
(
data_i,
sel_one_hot_i,
data_o
);
input [151:0] data_i;
input [3:0] sel_one_hot_i;
output [37:0] data_o;
wire [37:0] data_o;
wire N0,N1,N2,N3,N4,N5,N6,N7,N8,N9,N10,N11,N12,N13,N14,N15,N16,N17,N18,N19,N20,N21,
N22,N23,N24,N25,N26,N27,N28,N29,N30,N31,N32,N33,N34,N35,N36,N37,N38,N39,N40,N41,
N42,N43,N44,N45,N46,N47,N48,N49,N50,N51,N52,N53,N54,N55,N56,N57,N58,N59,N60,N61,
N62,N63,N64,N65,N66,N67,N68,N69,N70,N71,N72,N73,N74,N75;
wire [151:0] data_masked;
assign data_masked[37] = data_i[37] & sel_one_hot_i[0];
assign data_masked[36] = data_i[36] & sel_one_hot_i[0];
assign data_masked[35] = data_i[35] & sel_one_hot_i[0];
assign data_masked[34] = data_i[34] & sel_one_hot_i[0];
assign data_masked[33] = data_i[33] & sel_one_hot_i[0];
assign data_masked[32] = data_i[32] & sel_one_hot_i[0];
assign data_masked[31] = data_i[31] & sel_one_hot_i[0];
assign data_masked[30] = data_i[30] & sel_one_hot_i[0];
assign data_masked[29] = data_i[29] & sel_one_hot_i[0];
assign data_masked[28] = data_i[28] & sel_one_hot_i[0];
assign data_masked[27] = data_i[27] & sel_one_hot_i[0];
assign data_masked[26] = data_i[26] & sel_one_hot_i[0];
assign data_masked[25] = data_i[25] & sel_one_hot_i[0];
assign data_masked[24] = data_i[24] & sel_one_hot_i[0];
assign data_masked[23] = data_i[23] & sel_one_hot_i[0];
assign data_masked[22] = data_i[22] & sel_one_hot_i[0];
assign data_masked[21] = data_i[21] & sel_one_hot_i[0];
assign data_masked[20] = data_i[20] & sel_one_hot_i[0];
assign data_masked[19] = data_i[19] & sel_one_hot_i[0];
assign data_masked[18] = data_i[18] & sel_one_hot_i[0];
assign data_masked[17] = data_i[17] & sel_one_hot_i[0];
assign data_masked[16] = data_i[16] & sel_one_hot_i[0];
assign data_masked[15] = data_i[15] & sel_one_hot_i[0];
assign data_masked[14] = data_i[14] & sel_one_hot_i[0];
assign data_masked[13] = data_i[13] & sel_one_hot_i[0];
assign data_masked[12] = data_i[12] & sel_one_hot_i[0];
assign data_masked[11] = data_i[11] & sel_one_hot_i[0];
assign data_masked[10] = data_i[10] & sel_one_hot_i[0];
assign data_masked[9] = data_i[9] & sel_one_hot_i[0];
assign data_masked[8] = data_i[8] & sel_one_hot_i[0];
assign data_masked[7] = data_i[7] & sel_one_hot_i[0];
assign data_masked[6] = data_i[6] & sel_one_hot_i[0];
assign data_masked[5] = data_i[5] & sel_one_hot_i[0];
assign data_masked[4] = data_i[4] & sel_one_hot_i[0];
assign data_masked[3] = data_i[3] & sel_one_hot_i[0];
assign data_masked[2] = data_i[2] & sel_one_hot_i[0];
assign data_masked[1] = data_i[1] & sel_one_hot_i[0];
assign data_masked[0] = data_i[0] & sel_one_hot_i[0];
assign data_masked[75] = data_i[75] & sel_one_hot_i[1];
assign data_masked[74] = data_i[74] & sel_one_hot_i[1];
assign data_masked[73] = data_i[73] & sel_one_hot_i[1];
assign data_masked[72] = data_i[72] & sel_one_hot_i[1];
assign data_masked[71] = data_i[71] & sel_one_hot_i[1];
assign data_masked[70] = data_i[70] & sel_one_hot_i[1];
assign data_masked[69] = data_i[69] & sel_one_hot_i[1];
assign data_masked[68] = data_i[68] & sel_one_hot_i[1];
assign data_masked[67] = data_i[67] & sel_one_hot_i[1];
assign data_masked[66] = data_i[66] & sel_one_hot_i[1];
assign data_masked[65] = data_i[65] & sel_one_hot_i[1];
assign data_masked[64] = data_i[64] & sel_one_hot_i[1];
assign data_masked[63] = data_i[63] & sel_one_hot_i[1];
assign data_masked[62] = data_i[62] & sel_one_hot_i[1];
assign data_masked[61] = data_i[61] & sel_one_hot_i[1];
assign data_masked[60] = data_i[60] & sel_one_hot_i[1];
assign data_masked[59] = data_i[59] & sel_one_hot_i[1];
assign data_masked[58] = data_i[58] & sel_one_hot_i[1];
assign data_masked[57] = data_i[57] & sel_one_hot_i[1];
assign data_masked[56] = data_i[56] & sel_one_hot_i[1];
assign data_masked[55] = data_i[55] & sel_one_hot_i[1];
assign data_masked[54] = data_i[54] & sel_one_hot_i[1];
assign data_masked[53] = data_i[53] & sel_one_hot_i[1];
assign data_masked[52] = data_i[52] & sel_one_hot_i[1];
assign data_masked[51] = data_i[51] & sel_one_hot_i[1];
assign data_masked[50] = data_i[50] & sel_one_hot_i[1];
assign data_masked[49] = data_i[49] & sel_one_hot_i[1];
assign data_masked[48] = data_i[48] & sel_one_hot_i[1];
assign data_masked[47] = data_i[47] & sel_one_hot_i[1];
assign data_masked[46] = data_i[46] & sel_one_hot_i[1];
assign data_masked[45] = data_i[45] & sel_one_hot_i[1];
assign data_masked[44] = data_i[44] & sel_one_hot_i[1];
assign data_masked[43] = data_i[43] & sel_one_hot_i[1];
assign data_masked[42] = data_i[42] & sel_one_hot_i[1];
assign data_masked[41] = data_i[41] & sel_one_hot_i[1];
assign data_masked[40] = data_i[40] & sel_one_hot_i[1];
assign data_masked[39] = data_i[39] & sel_one_hot_i[1];
assign data_masked[38] = data_i[38] & sel_one_hot_i[1];
assign data_masked[113] = data_i[113] & sel_one_hot_i[2];
assign data_masked[112] = data_i[112] & sel_one_hot_i[2];
assign data_masked[111] = data_i[111] & sel_one_hot_i[2];
assign data_masked[110] = data_i[110] & sel_one_hot_i[2];
assign data_masked[109] = data_i[109] & sel_one_hot_i[2];
assign data_masked[108] = data_i[108] & sel_one_hot_i[2];
assign data_masked[107] = data_i[107] & sel_one_hot_i[2];
assign data_masked[106] = data_i[106] & sel_one_hot_i[2];
assign data_masked[105] = data_i[105] & sel_one_hot_i[2];
assign data_masked[104] = data_i[104] & sel_one_hot_i[2];
assign data_masked[103] = data_i[103] & sel_one_hot_i[2];
assign data_masked[102] = data_i[102] & sel_one_hot_i[2];
assign data_masked[101] = data_i[101] & sel_one_hot_i[2];
assign data_masked[100] = data_i[100] & sel_one_hot_i[2];
assign data_masked[99] = data_i[99] & sel_one_hot_i[2];
assign data_masked[98] = data_i[98] & sel_one_hot_i[2];
assign data_masked[97] = data_i[97] & sel_one_hot_i[2];
assign data_masked[96] = data_i[96] & sel_one_hot_i[2];
assign data_masked[95] = data_i[95] & sel_one_hot_i[2];
assign data_masked[94] = data_i[94] & sel_one_hot_i[2];
assign data_masked[93] = data_i[93] & sel_one_hot_i[2];
assign data_masked[92] = data_i[92] & sel_one_hot_i[2];
assign data_masked[91] = data_i[91] & sel_one_hot_i[2];
assign data_masked[90] = data_i[90] & sel_one_hot_i[2];
assign data_masked[89] = data_i[89] & sel_one_hot_i[2];
assign data_masked[88] = data_i[88] & sel_one_hot_i[2];
assign data_masked[87] = data_i[87] & sel_one_hot_i[2];
assign data_masked[86] = data_i[86] & sel_one_hot_i[2];
assign data_masked[85] = data_i[85] & sel_one_hot_i[2];
assign data_masked[84] = data_i[84] & sel_one_hot_i[2];
assign data_masked[83] = data_i[83] & sel_one_hot_i[2];
assign data_masked[82] = data_i[82] & sel_one_hot_i[2];
assign data_masked[81] = data_i[81] & sel_one_hot_i[2];
assign data_masked[80] = data_i[80] & sel_one_hot_i[2];
assign data_masked[79] = data_i[79] & sel_one_hot_i[2];
assign data_masked[78] = data_i[78] & sel_one_hot_i[2];
assign data_masked[77] = data_i[77] & sel_one_hot_i[2];
assign data_masked[76] = data_i[76] & sel_one_hot_i[2];
assign data_masked[151] = data_i[151] & sel_one_hot_i[3];
assign data_masked[150] = data_i[150] & sel_one_hot_i[3];
assign data_masked[149] = data_i[149] & sel_one_hot_i[3];
assign data_masked[148] = data_i[148] & sel_one_hot_i[3];
assign data_masked[147] = data_i[147] & sel_one_hot_i[3];
assign data_masked[146] = data_i[146] & sel_one_hot_i[3];
assign data_masked[145] = data_i[145] & sel_one_hot_i[3];
assign data_masked[144] = data_i[144] & sel_one_hot_i[3];
assign data_masked[143] = data_i[143] & sel_one_hot_i[3];
assign data_masked[142] = data_i[142] & sel_one_hot_i[3];
assign data_masked[141] = data_i[141] & sel_one_hot_i[3];
assign data_masked[140] = data_i[140] & sel_one_hot_i[3];
assign data_masked[139] = data_i[139] & sel_one_hot_i[3];
assign data_masked[138] = data_i[138] & sel_one_hot_i[3];
assign data_masked[137] = data_i[137] & sel_one_hot_i[3];
assign data_masked[136] = data_i[136] & sel_one_hot_i[3];
assign data_masked[135] = data_i[135] & sel_one_hot_i[3];
assign data_masked[134] = data_i[134] & sel_one_hot_i[3];
assign data_masked[133] = data_i[133] & sel_one_hot_i[3];
assign data_masked[132] = data_i[132] & sel_one_hot_i[3];
assign data_masked[131] = data_i[131] & sel_one_hot_i[3];
assign data_masked[130] = data_i[130] & sel_one_hot_i[3];
assign data_masked[129] = data_i[129] & sel_one_hot_i[3];
assign data_masked[128] = data_i[128] & sel_one_hot_i[3];
assign data_masked[127] = data_i[127] & sel_one_hot_i[3];
assign data_masked[126] = data_i[126] & sel_one_hot_i[3];
assign data_masked[125] = data_i[125] & sel_one_hot_i[3];
assign data_masked[124] = data_i[124] & sel_one_hot_i[3];
assign data_masked[123] = data_i[123] & sel_one_hot_i[3];
assign data_masked[122] = data_i[122] & sel_one_hot_i[3];
assign data_masked[121] = data_i[121] & sel_one_hot_i[3];
assign data_masked[120] = data_i[120] & sel_one_hot_i[3];
assign data_masked[119] = data_i[119] & sel_one_hot_i[3];
assign data_masked[118] = data_i[118] & sel_one_hot_i[3];
assign data_masked[117] = data_i[117] & sel_one_hot_i[3];
assign data_masked[116] = data_i[116] & sel_one_hot_i[3];
assign data_masked[115] = data_i[115] & sel_one_hot_i[3];
assign data_masked[114] = data_i[114] & sel_one_hot_i[3];
assign data_o[0] = N1 | data_masked[0];
assign N1 = N0 | data_masked[38];
assign N0 = data_masked[114] | data_masked[76];
assign data_o[1] = N3 | data_masked[1];
assign N3 = N2 | data_masked[39];
assign N2 = data_masked[115] | data_masked[77];
assign data_o[2] = N5 | data_masked[2];
assign N5 = N4 | data_masked[40];
assign N4 = data_masked[116] | data_masked[78];
assign data_o[3] = N7 | data_masked[3];
assign N7 = N6 | data_masked[41];
assign N6 = data_masked[117] | data_masked[79];
assign data_o[4] = N9 | data_masked[4];
assign N9 = N8 | data_masked[42];
assign N8 = data_masked[118] | data_masked[80];
assign data_o[5] = N11 | data_masked[5];
assign N11 = N10 | data_masked[43];
assign N10 = data_masked[119] | data_masked[81];
assign data_o[6] = N13 | data_masked[6];
assign N13 = N12 | data_masked[44];
assign N12 = data_masked[120] | data_masked[82];
assign data_o[7] = N15 | data_masked[7];
assign N15 = N14 | data_masked[45];
assign N14 = data_masked[121] | data_masked[83];
assign data_o[8] = N17 | data_masked[8];
assign N17 = N16 | data_masked[46];
assign N16 = data_masked[122] | data_masked[84];
assign data_o[9] = N19 | data_masked[9];
assign N19 = N18 | data_masked[47];
assign N18 = data_masked[123] | data_masked[85];
assign data_o[10] = N21 | data_masked[10];
assign N21 = N20 | data_masked[48];
assign N20 = data_masked[124] | data_masked[86];
assign data_o[11] = N23 | data_masked[11];
assign N23 = N22 | data_masked[49];
assign N22 = data_masked[125] | data_masked[87];
assign data_o[12] = N25 | data_masked[12];
assign N25 = N24 | data_masked[50];
assign N24 = data_masked[126] | data_masked[88];
assign data_o[13] = N27 | data_masked[13];
assign N27 = N26 | data_masked[51];
assign N26 = data_masked[127] | data_masked[89];
assign data_o[14] = N29 | data_masked[14];
assign N29 = N28 | data_masked[52];
assign N28 = data_masked[128] | data_masked[90];
assign data_o[15] = N31 | data_masked[15];
assign N31 = N30 | data_masked[53];
assign N30 = data_masked[129] | data_masked[91];
assign data_o[16] = N33 | data_masked[16];
assign N33 = N32 | data_masked[54];
assign N32 = data_masked[130] | data_masked[92];
assign data_o[17] = N35 | data_masked[17];
assign N35 = N34 | data_masked[55];
assign N34 = data_masked[131] | data_masked[93];
assign data_o[18] = N37 | data_masked[18];
assign N37 = N36 | data_masked[56];
assign N36 = data_masked[132] | data_masked[94];
assign data_o[19] = N39 | data_masked[19];
assign N39 = N38 | data_masked[57];
assign N38 = data_masked[133] | data_masked[95];
assign data_o[20] = N41 | data_masked[20];
assign N41 = N40 | data_masked[58];
assign N40 = data_masked[134] | data_masked[96];
assign data_o[21] = N43 | data_masked[21];
assign N43 = N42 | data_masked[59];
assign N42 = data_masked[135] | data_masked[97];
assign data_o[22] = N45 | data_masked[22];
assign N45 = N44 | data_masked[60];
assign N44 = data_masked[136] | data_masked[98];
assign data_o[23] = N47 | data_masked[23];
assign N47 = N46 | data_masked[61];
assign N46 = data_masked[137] | data_masked[99];
assign data_o[24] = N49 | data_masked[24];
assign N49 = N48 | data_masked[62];
assign N48 = data_masked[138] | data_masked[100];
assign data_o[25] = N51 | data_masked[25];
assign N51 = N50 | data_masked[63];
assign N50 = data_masked[139] | data_masked[101];
assign data_o[26] = N53 | data_masked[26];
assign N53 = N52 | data_masked[64];
assign N52 = data_masked[140] | data_masked[102];
assign data_o[27] = N55 | data_masked[27];
assign N55 = N54 | data_masked[65];
assign N54 = data_masked[141] | data_masked[103];
assign data_o[28] = N57 | data_masked[28];
assign N57 = N56 | data_masked[66];
assign N56 = data_masked[142] | data_masked[104];
assign data_o[29] = N59 | data_masked[29];
assign N59 = N58 | data_masked[67];
assign N58 = data_masked[143] | data_masked[105];
assign data_o[30] = N61 | data_masked[30];
assign N61 = N60 | data_masked[68];
assign N60 = data_masked[144] | data_masked[106];
assign data_o[31] = N63 | data_masked[31];
assign N63 = N62 | data_masked[69];
assign N62 = data_masked[145] | data_masked[107];
assign data_o[32] = N65 | data_masked[32];
assign N65 = N64 | data_masked[70];
assign N64 = data_masked[146] | data_masked[108];
assign data_o[33] = N67 | data_masked[33];
assign N67 = N66 | data_masked[71];
assign N66 = data_masked[147] | data_masked[109];
assign data_o[34] = N69 | data_masked[34];
assign N69 = N68 | data_masked[72];
assign N68 = data_masked[148] | data_masked[110];
assign data_o[35] = N71 | data_masked[35];
assign N71 = N70 | data_masked[73];
assign N70 = data_masked[149] | data_masked[111];
assign data_o[36] = N73 | data_masked[36];
assign N73 = N72 | data_masked[74];
assign N72 = data_masked[150] | data_masked[112];
assign data_o[37] = N75 | data_masked[37];
assign N75 = N74 | data_masked[75];
assign N74 = data_masked[151] | data_masked[113];
endmodule
|
module bsg_mem_1r1w_synth_width_p26_els_p2_read_write_same_addr_p0_harden_p0
(
w_clk_i,
w_reset_i,
w_v_i,
w_addr_i,
w_data_i,
r_v_i,
r_addr_i,
r_data_o
);
input [0:0] w_addr_i;
input [25:0] w_data_i;
input [0:0] r_addr_i;
output [25:0] r_data_o;
input w_clk_i;
input w_reset_i;
input w_v_i;
input r_v_i;
wire [25:0] r_data_o;
wire N0,N1,N2,N3,N4,N5,N7,N8;
reg [51:0] mem;
assign r_data_o[25] = (N3)? mem[25] :
(N0)? mem[51] : 1'b0;
assign N0 = r_addr_i[0];
assign r_data_o[24] = (N3)? mem[24] :
(N0)? mem[50] : 1'b0;
assign r_data_o[23] = (N3)? mem[23] :
(N0)? mem[49] : 1'b0;
assign r_data_o[22] = (N3)? mem[22] :
(N0)? mem[48] : 1'b0;
assign r_data_o[21] = (N3)? mem[21] :
(N0)? mem[47] : 1'b0;
assign r_data_o[20] = (N3)? mem[20] :
(N0)? mem[46] : 1'b0;
assign r_data_o[19] = (N3)? mem[19] :
(N0)? mem[45] : 1'b0;
assign r_data_o[18] = (N3)? mem[18] :
(N0)? mem[44] : 1'b0;
assign r_data_o[17] = (N3)? mem[17] :
(N0)? mem[43] : 1'b0;
assign r_data_o[16] = (N3)? mem[16] :
(N0)? mem[42] : 1'b0;
assign r_data_o[15] = (N3)? mem[15] :
(N0)? mem[41] : 1'b0;
assign r_data_o[14] = (N3)? mem[14] :
(N0)? mem[40] : 1'b0;
assign r_data_o[13] = (N3)? mem[13] :
(N0)? mem[39] : 1'b0;
assign r_data_o[12] = (N3)? mem[12] :
(N0)? mem[38] : 1'b0;
assign r_data_o[11] = (N3)? mem[11] :
(N0)? mem[37] : 1'b0;
assign r_data_o[10] = (N3)? mem[10] :
(N0)? mem[36] : 1'b0;
assign r_data_o[9] = (N3)? mem[9] :
(N0)? mem[35] : 1'b0;
assign r_data_o[8] = (N3)? mem[8] :
(N0)? mem[34] : 1'b0;
assign r_data_o[7] = (N3)? mem[7] :
(N0)? mem[33] : 1'b0;
assign r_data_o[6] = (N3)? mem[6] :
(N0)? mem[32] : 1'b0;
assign r_data_o[5] = (N3)? mem[5] :
(N0)? mem[31] : 1'b0;
assign r_data_o[4] = (N3)? mem[4] :
(N0)? mem[30] : 1'b0;
assign r_data_o[3] = (N3)? mem[3] :
(N0)? mem[29] : 1'b0;
assign r_data_o[2] = (N3)? mem[2] :
(N0)? mem[28] : 1'b0;
assign r_data_o[1] = (N3)? mem[1] :
(N0)? mem[27] : 1'b0;
assign r_data_o[0] = (N3)? mem[0] :
(N0)? mem[26] : 1'b0;
assign N5 = ~w_addr_i[0];
assign { N8, N7 } = (N1)? { w_addr_i[0:0], N5 } :
(N2)? { 1'b0, 1'b0 } : 1'b0;
assign N1 = w_v_i;
assign N2 = N4;
assign N3 = ~r_addr_i[0];
assign N4 = ~w_v_i;
always @(posedge w_clk_i) begin
if(N8) begin
{ mem[51:26] } <= { w_data_i[25:0] };
end
if(N7) begin
{ mem[25:0] } <= { w_data_i[25:0] };
end
end
endmodule
|
module bsg_mem_1r1w_synth_width_p55_els_p2_read_write_same_addr_p0_harden_p0
(
w_clk_i,
w_reset_i,
w_v_i,
w_addr_i,
w_data_i,
r_v_i,
r_addr_i,
r_data_o
);
input [0:0] w_addr_i;
input [54:0] w_data_i;
input [0:0] r_addr_i;
output [54:0] r_data_o;
input w_clk_i;
input w_reset_i;
input w_v_i;
input r_v_i;
wire [54:0] r_data_o;
wire N0,N1,N2,N3,N4,N5,N7,N8;
reg [109:0] mem;
assign r_data_o[54] = (N3)? mem[54] :
(N0)? mem[109] : 1'b0;
assign N0 = r_addr_i[0];
assign r_data_o[53] = (N3)? mem[53] :
(N0)? mem[108] : 1'b0;
assign r_data_o[52] = (N3)? mem[52] :
(N0)? mem[107] : 1'b0;
assign r_data_o[51] = (N3)? mem[51] :
(N0)? mem[106] : 1'b0;
assign r_data_o[50] = (N3)? mem[50] :
(N0)? mem[105] : 1'b0;
assign r_data_o[49] = (N3)? mem[49] :
(N0)? mem[104] : 1'b0;
assign r_data_o[48] = (N3)? mem[48] :
(N0)? mem[103] : 1'b0;
assign r_data_o[47] = (N3)? mem[47] :
(N0)? mem[102] : 1'b0;
assign r_data_o[46] = (N3)? mem[46] :
(N0)? mem[101] : 1'b0;
assign r_data_o[45] = (N3)? mem[45] :
(N0)? mem[100] : 1'b0;
assign r_data_o[44] = (N3)? mem[44] :
(N0)? mem[99] : 1'b0;
assign r_data_o[43] = (N3)? mem[43] :
(N0)? mem[98] : 1'b0;
assign r_data_o[42] = (N3)? mem[42] :
(N0)? mem[97] : 1'b0;
assign r_data_o[41] = (N3)? mem[41] :
(N0)? mem[96] : 1'b0;
assign r_data_o[40] = (N3)? mem[40] :
(N0)? mem[95] : 1'b0;
assign r_data_o[39] = (N3)? mem[39] :
(N0)? mem[94] : 1'b0;
assign r_data_o[38] = (N3)? mem[38] :
(N0)? mem[93] : 1'b0;
assign r_data_o[37] = (N3)? mem[37] :
(N0)? mem[92] : 1'b0;
assign r_data_o[36] = (N3)? mem[36] :
(N0)? mem[91] : 1'b0;
assign r_data_o[35] = (N3)? mem[35] :
(N0)? mem[90] : 1'b0;
assign r_data_o[34] = (N3)? mem[34] :
(N0)? mem[89] : 1'b0;
assign r_data_o[33] = (N3)? mem[33] :
(N0)? mem[88] : 1'b0;
assign r_data_o[32] = (N3)? mem[32] :
(N0)? mem[87] : 1'b0;
assign r_data_o[31] = (N3)? mem[31] :
(N0)? mem[86] : 1'b0;
assign r_data_o[30] = (N3)? mem[30] :
(N0)? mem[85] : 1'b0;
assign r_data_o[29] = (N3)? mem[29] :
(N0)? mem[84] : 1'b0;
assign r_data_o[28] = (N3)? mem[28] :
(N0)? mem[83] : 1'b0;
assign r_data_o[27] = (N3)? mem[27] :
(N0)? mem[82] : 1'b0;
assign r_data_o[26] = (N3)? mem[26] :
(N0)? mem[81] : 1'b0;
assign r_data_o[25] = (N3)? mem[25] :
(N0)? mem[80] : 1'b0;
assign r_data_o[24] = (N3)? mem[24] :
(N0)? mem[79] : 1'b0;
assign r_data_o[23] = (N3)? mem[23] :
(N0)? mem[78] : 1'b0;
assign r_data_o[22] = (N3)? mem[22] :
(N0)? mem[77] : 1'b0;
assign r_data_o[21] = (N3)? mem[21] :
(N0)? mem[76] : 1'b0;
assign r_data_o[20] = (N3)? mem[20] :
(N0)? mem[75] : 1'b0;
assign r_data_o[19] = (N3)? mem[19] :
(N0)? mem[74] : 1'b0;
assign r_data_o[18] = (N3)? mem[18] :
(N0)? mem[73] : 1'b0;
assign r_data_o[17] = (N3)? mem[17] :
(N0)? mem[72] : 1'b0;
assign r_data_o[16] = (N3)? mem[16] :
(N0)? mem[71] : 1'b0;
assign r_data_o[15] = (N3)? mem[15] :
(N0)? mem[70] : 1'b0;
assign r_data_o[14] = (N3)? mem[14] :
(N0)? mem[69] : 1'b0;
assign r_data_o[13] = (N3)? mem[13] :
(N0)? mem[68] : 1'b0;
assign r_data_o[12] = (N3)? mem[12] :
(N0)? mem[67] : 1'b0;
assign r_data_o[11] = (N3)? mem[11] :
(N0)? mem[66] : 1'b0;
assign r_data_o[10] = (N3)? mem[10] :
(N0)? mem[65] : 1'b0;
assign r_data_o[9] = (N3)? mem[9] :
(N0)? mem[64] : 1'b0;
assign r_data_o[8] = (N3)? mem[8] :
(N0)? mem[63] : 1'b0;
assign r_data_o[7] = (N3)? mem[7] :
(N0)? mem[62] : 1'b0;
assign r_data_o[6] = (N3)? mem[6] :
(N0)? mem[61] : 1'b0;
assign r_data_o[5] = (N3)? mem[5] :
(N0)? mem[60] : 1'b0;
assign r_data_o[4] = (N3)? mem[4] :
(N0)? mem[59] : 1'b0;
assign r_data_o[3] = (N3)? mem[3] :
(N0)? mem[58] : 1'b0;
assign r_data_o[2] = (N3)? mem[2] :
(N0)? mem[57] : 1'b0;
assign r_data_o[1] = (N3)? mem[1] :
(N0)? mem[56] : 1'b0;
assign r_data_o[0] = (N3)? mem[0] :
(N0)? mem[55] : 1'b0;
assign N5 = ~w_addr_i[0];
assign { N8, N7 } = (N1)? { w_addr_i[0:0], N5 } :
(N2)? { 1'b0, 1'b0 } : 1'b0;
assign N1 = w_v_i;
assign N2 = N4;
assign N3 = ~r_addr_i[0];
assign N4 = ~w_v_i;
always @(posedge w_clk_i) begin
if(N8) begin
{ mem[109:55] } <= { w_data_i[54:0] };
end
if(N7) begin
{ mem[54:0] } <= { w_data_i[54:0] };
end
end
endmodule
|
module bsg_mux_width_p32_els_p2
(
data_i,
sel_i,
data_o
);
input [63:0] data_i;
input [0:0] sel_i;
output [31:0] data_o;
wire [31:0] data_o;
wire N0,N1;
assign data_o[31] = (N1)? data_i[31] :
(N0)? data_i[63] : 1'b0;
assign N0 = sel_i[0];
assign data_o[30] = (N1)? data_i[30] :
(N0)? data_i[62] : 1'b0;
assign data_o[29] = (N1)? data_i[29] :
(N0)? data_i[61] : 1'b0;
assign data_o[28] = (N1)? data_i[28] :
(N0)? data_i[60] : 1'b0;
assign data_o[27] = (N1)? data_i[27] :
(N0)? data_i[59] : 1'b0;
assign data_o[26] = (N1)? data_i[26] :
(N0)? data_i[58] : 1'b0;
assign data_o[25] = (N1)? data_i[25] :
(N0)? data_i[57] : 1'b0;
assign data_o[24] = (N1)? data_i[24] :
(N0)? data_i[56] : 1'b0;
assign data_o[23] = (N1)? data_i[23] :
(N0)? data_i[55] : 1'b0;
assign data_o[22] = (N1)? data_i[22] :
(N0)? data_i[54] : 1'b0;
assign data_o[21] = (N1)? data_i[21] :
(N0)? data_i[53] : 1'b0;
assign data_o[20] = (N1)? data_i[20] :
(N0)? data_i[52] : 1'b0;
assign data_o[19] = (N1)? data_i[19] :
(N0)? data_i[51] : 1'b0;
assign data_o[18] = (N1)? data_i[18] :
(N0)? data_i[50] : 1'b0;
assign data_o[17] = (N1)? data_i[17] :
(N0)? data_i[49] : 1'b0;
assign data_o[16] = (N1)? data_i[16] :
(N0)? data_i[48] : 1'b0;
assign data_o[15] = (N1)? data_i[15] :
(N0)? data_i[47] : 1'b0;
assign data_o[14] = (N1)? data_i[14] :
(N0)? data_i[46] : 1'b0;
assign data_o[13] = (N1)? data_i[13] :
(N0)? data_i[45] : 1'b0;
assign data_o[12] = (N1)? data_i[12] :
(N0)? data_i[44] : 1'b0;
assign data_o[11] = (N1)? data_i[11] :
(N0)? data_i[43] : 1'b0;
assign data_o[10] = (N1)? data_i[10] :
(N0)? data_i[42] : 1'b0;
assign data_o[9] = (N1)? data_i[9] :
(N0)? data_i[41] : 1'b0;
assign data_o[8] = (N1)? data_i[8] :
(N0)? data_i[40] : 1'b0;
assign data_o[7] = (N1)? data_i[7] :
(N0)? data_i[39] : 1'b0;
assign data_o[6] = (N1)? data_i[6] :
(N0)? data_i[38] : 1'b0;
assign data_o[5] = (N1)? data_i[5] :
(N0)? data_i[37] : 1'b0;
assign data_o[4] = (N1)? data_i[4] :
(N0)? data_i[36] : 1'b0;
assign data_o[3] = (N1)? data_i[3] :
(N0)? data_i[35] : 1'b0;
assign data_o[2] = (N1)? data_i[2] :
(N0)? data_i[34] : 1'b0;
assign data_o[1] = (N1)? data_i[1] :
(N0)? data_i[33] : 1'b0;
assign data_o[0] = (N1)? data_i[0] :
(N0)? data_i[32] : 1'b0;
assign N1 = ~sel_i[0];
endmodule
|
module bsg_mux_width_p64_els_p8
(
data_i,
sel_i,
data_o
);
input [511:0] data_i;
input [2:0] sel_i;
output [63:0] data_o;
wire [63:0] data_o;
wire N0,N1,N2,N3,N4,N5,N6,N7,N8,N9,N10,N11,N12,N13,N14;
assign data_o[63] = (N7)? data_i[63] :
(N9)? data_i[127] :
(N11)? data_i[191] :
(N13)? data_i[255] :
(N8)? data_i[319] :
(N10)? data_i[383] :
(N12)? data_i[447] :
(N14)? data_i[511] : 1'b0;
assign data_o[62] = (N7)? data_i[62] :
(N9)? data_i[126] :
(N11)? data_i[190] :
(N13)? data_i[254] :
(N8)? data_i[318] :
(N10)? data_i[382] :
(N12)? data_i[446] :
(N14)? data_i[510] : 1'b0;
assign data_o[61] = (N7)? data_i[61] :
(N9)? data_i[125] :
(N11)? data_i[189] :
(N13)? data_i[253] :
(N8)? data_i[317] :
(N10)? data_i[381] :
(N12)? data_i[445] :
(N14)? data_i[509] : 1'b0;
assign data_o[60] = (N7)? data_i[60] :
(N9)? data_i[124] :
(N11)? data_i[188] :
(N13)? data_i[252] :
(N8)? data_i[316] :
(N10)? data_i[380] :
(N12)? data_i[444] :
(N14)? data_i[508] : 1'b0;
assign data_o[59] = (N7)? data_i[59] :
(N9)? data_i[123] :
(N11)? data_i[187] :
(N13)? data_i[251] :
(N8)? data_i[315] :
(N10)? data_i[379] :
(N12)? data_i[443] :
(N14)? data_i[507] : 1'b0;
assign data_o[58] = (N7)? data_i[58] :
(N9)? data_i[122] :
(N11)? data_i[186] :
(N13)? data_i[250] :
(N8)? data_i[314] :
(N10)? data_i[378] :
(N12)? data_i[442] :
(N14)? data_i[506] : 1'b0;
assign data_o[57] = (N7)? data_i[57] :
(N9)? data_i[121] :
(N11)? data_i[185] :
(N13)? data_i[249] :
(N8)? data_i[313] :
(N10)? data_i[377] :
(N12)? data_i[441] :
(N14)? data_i[505] : 1'b0;
assign data_o[56] = (N7)? data_i[56] :
(N9)? data_i[120] :
(N11)? data_i[184] :
(N13)? data_i[248] :
(N8)? data_i[312] :
(N10)? data_i[376] :
(N12)? data_i[440] :
(N14)? data_i[504] : 1'b0;
assign data_o[55] = (N7)? data_i[55] :
(N9)? data_i[119] :
(N11)? data_i[183] :
(N13)? data_i[247] :
(N8)? data_i[311] :
(N10)? data_i[375] :
(N12)? data_i[439] :
(N14)? data_i[503] : 1'b0;
assign data_o[54] = (N7)? data_i[54] :
(N9)? data_i[118] :
(N11)? data_i[182] :
(N13)? data_i[246] :
(N8)? data_i[310] :
(N10)? data_i[374] :
(N12)? data_i[438] :
(N14)? data_i[502] : 1'b0;
assign data_o[53] = (N7)? data_i[53] :
(N9)? data_i[117] :
(N11)? data_i[181] :
(N13)? data_i[245] :
(N8)? data_i[309] :
(N10)? data_i[373] :
(N12)? data_i[437] :
(N14)? data_i[501] : 1'b0;
assign data_o[52] = (N7)? data_i[52] :
(N9)? data_i[116] :
(N11)? data_i[180] :
(N13)? data_i[244] :
(N8)? data_i[308] :
(N10)? data_i[372] :
(N12)? data_i[436] :
(N14)? data_i[500] : 1'b0;
assign data_o[51] = (N7)? data_i[51] :
(N9)? data_i[115] :
(N11)? data_i[179] :
(N13)? data_i[243] :
(N8)? data_i[307] :
(N10)? data_i[371] :
(N12)? data_i[435] :
(N14)? data_i[499] : 1'b0;
assign data_o[50] = (N7)? data_i[50] :
(N9)? data_i[114] :
(N11)? data_i[178] :
(N13)? data_i[242] :
(N8)? data_i[306] :
(N10)? data_i[370] :
(N12)? data_i[434] :
(N14)? data_i[498] : 1'b0;
assign data_o[49] = (N7)? data_i[49] :
(N9)? data_i[113] :
(N11)? data_i[177] :
(N13)? data_i[241] :
(N8)? data_i[305] :
(N10)? data_i[369] :
(N12)? data_i[433] :
(N14)? data_i[497] : 1'b0;
assign data_o[48] = (N7)? data_i[48] :
(N9)? data_i[112] :
(N11)? data_i[176] :
(N13)? data_i[240] :
(N8)? data_i[304] :
(N10)? data_i[368] :
(N12)? data_i[432] :
(N14)? data_i[496] : 1'b0;
assign data_o[47] = (N7)? data_i[47] :
(N9)? data_i[111] :
(N11)? data_i[175] :
(N13)? data_i[239] :
(N8)? data_i[303] :
(N10)? data_i[367] :
(N12)? data_i[431] :
(N14)? data_i[495] : 1'b0;
assign data_o[46] = (N7)? data_i[46] :
(N9)? data_i[110] :
(N11)? data_i[174] :
(N13)? data_i[238] :
(N8)? data_i[302] :
(N10)? data_i[366] :
(N12)? data_i[430] :
(N14)? data_i[494] : 1'b0;
assign data_o[45] = (N7)? data_i[45] :
(N9)? data_i[109] :
(N11)? data_i[173] :
(N13)? data_i[237] :
(N8)? data_i[301] :
(N10)? data_i[365] :
(N12)? data_i[429] :
(N14)? data_i[493] : 1'b0;
assign data_o[44] = (N7)? data_i[44] :
(N9)? data_i[108] :
(N11)? data_i[172] :
(N13)? data_i[236] :
(N8)? data_i[300] :
(N10)? data_i[364] :
(N12)? data_i[428] :
(N14)? data_i[492] : 1'b0;
assign data_o[43] = (N7)? data_i[43] :
(N9)? data_i[107] :
(N11)? data_i[171] :
(N13)? data_i[235] :
(N8)? data_i[299] :
(N10)? data_i[363] :
(N12)? data_i[427] :
(N14)? data_i[491] : 1'b0;
assign data_o[42] = (N7)? data_i[42] :
(N9)? data_i[106] :
(N11)? data_i[170] :
(N13)? data_i[234] :
(N8)? data_i[298] :
(N10)? data_i[362] :
(N12)? data_i[426] :
(N14)? data_i[490] : 1'b0;
assign data_o[41] = (N7)? data_i[41] :
(N9)? data_i[105] :
(N11)? data_i[169] :
(N13)? data_i[233] :
(N8)? data_i[297] :
(N10)? data_i[361] :
(N12)? data_i[425] :
(N14)? data_i[489] : 1'b0;
assign data_o[40] = (N7)? data_i[40] :
(N9)? data_i[104] :
(N11)? data_i[168] :
(N13)? data_i[232] :
(N8)? data_i[296] :
(N10)? data_i[360] :
(N12)? data_i[424] :
(N14)? data_i[488] : 1'b0;
assign data_o[39] = (N7)? data_i[39] :
(N9)? data_i[103] :
(N11)? data_i[167] :
(N13)? data_i[231] :
(N8)? data_i[295] :
(N10)? data_i[359] :
(N12)? data_i[423] :
(N14)? data_i[487] : 1'b0;
assign data_o[38] = (N7)? data_i[38] :
(N9)? data_i[102] :
(N11)? data_i[166] :
(N13)? data_i[230] :
(N8)? data_i[294] :
(N10)? data_i[358] :
(N12)? data_i[422] :
(N14)? data_i[486] : 1'b0;
assign data_o[37] = (N7)? data_i[37] :
(N9)? data_i[101] :
(N11)? data_i[165] :
(N13)? data_i[229] :
(N8)? data_i[293] :
(N10)? data_i[357] :
(N12)? data_i[421] :
(N14)? data_i[485] : 1'b0;
assign data_o[36] = (N7)? data_i[36] :
(N9)? data_i[100] :
(N11)? data_i[164] :
(N13)? data_i[228] :
(N8)? data_i[292] :
(N10)? data_i[356] :
(N12)? data_i[420] :
(N14)? data_i[484] : 1'b0;
assign data_o[35] = (N7)? data_i[35] :
(N9)? data_i[99] :
(N11)? data_i[163] :
(N13)? data_i[227] :
(N8)? data_i[291] :
(N10)? data_i[355] :
(N12)? data_i[419] :
(N14)? data_i[483] : 1'b0;
assign data_o[34] = (N7)? data_i[34] :
(N9)? data_i[98] :
(N11)? data_i[162] :
(N13)? data_i[226] :
(N8)? data_i[290] :
(N10)? data_i[354] :
(N12)? data_i[418] :
(N14)? data_i[482] : 1'b0;
assign data_o[33] = (N7)? data_i[33] :
(N9)? data_i[97] :
(N11)? data_i[161] :
(N13)? data_i[225] :
(N8)? data_i[289] :
(N10)? data_i[353] :
(N12)? data_i[417] :
(N14)? data_i[481] : 1'b0;
assign data_o[32] = (N7)? data_i[32] :
(N9)? data_i[96] :
(N11)? data_i[160] :
(N13)? data_i[224] :
(N8)? data_i[288] :
(N10)? data_i[352] :
(N12)? data_i[416] :
(N14)? data_i[480] : 1'b0;
assign data_o[31] = (N7)? data_i[31] :
(N9)? data_i[95] :
(N11)? data_i[159] :
(N13)? data_i[223] :
(N8)? data_i[287] :
(N10)? data_i[351] :
(N12)? data_i[415] :
(N14)? data_i[479] : 1'b0;
assign data_o[30] = (N7)? data_i[30] :
(N9)? data_i[94] :
(N11)? data_i[158] :
(N13)? data_i[222] :
(N8)? data_i[286] :
(N10)? data_i[350] :
(N12)? data_i[414] :
(N14)? data_i[478] : 1'b0;
assign data_o[29] = (N7)? data_i[29] :
(N9)? data_i[93] :
(N11)? data_i[157] :
(N13)? data_i[221] :
(N8)? data_i[285] :
(N10)? data_i[349] :
(N12)? data_i[413] :
(N14)? data_i[477] : 1'b0;
assign data_o[28] = (N7)? data_i[28] :
(N9)? data_i[92] :
(N11)? data_i[156] :
(N13)? data_i[220] :
(N8)? data_i[284] :
(N10)? data_i[348] :
(N12)? data_i[412] :
(N14)? data_i[476] : 1'b0;
assign data_o[27] = (N7)? data_i[27] :
(N9)? data_i[91] :
(N11)? data_i[155] :
(N13)? data_i[219] :
(N8)? data_i[283] :
(N10)? data_i[347] :
(N12)? data_i[411] :
(N14)? data_i[475] : 1'b0;
assign data_o[26] = (N7)? data_i[26] :
(N9)? data_i[90] :
(N11)? data_i[154] :
(N13)? data_i[218] :
(N8)? data_i[282] :
(N10)? data_i[346] :
(N12)? data_i[410] :
(N14)? data_i[474] : 1'b0;
assign data_o[25] = (N7)? data_i[25] :
(N9)? data_i[89] :
(N11)? data_i[153] :
(N13)? data_i[217] :
(N8)? data_i[281] :
(N10)? data_i[345] :
(N12)? data_i[409] :
(N14)? data_i[473] : 1'b0;
assign data_o[24] = (N7)? data_i[24] :
(N9)? data_i[88] :
(N11)? data_i[152] :
(N13)? data_i[216] :
(N8)? data_i[280] :
(N10)? data_i[344] :
(N12)? data_i[408] :
(N14)? data_i[472] : 1'b0;
assign data_o[23] = (N7)? data_i[23] :
(N9)? data_i[87] :
(N11)? data_i[151] :
(N13)? data_i[215] :
(N8)? data_i[279] :
(N10)? data_i[343] :
(N12)? data_i[407] :
(N14)? data_i[471] : 1'b0;
assign data_o[22] = (N7)? data_i[22] :
(N9)? data_i[86] :
(N11)? data_i[150] :
(N13)? data_i[214] :
(N8)? data_i[278] :
(N10)? data_i[342] :
(N12)? data_i[406] :
(N14)? data_i[470] : 1'b0;
assign data_o[21] = (N7)? data_i[21] :
(N9)? data_i[85] :
(N11)? data_i[149] :
(N13)? data_i[213] :
(N8)? data_i[277] :
(N10)? data_i[341] :
(N12)? data_i[405] :
(N14)? data_i[469] : 1'b0;
assign data_o[20] = (N7)? data_i[20] :
(N9)? data_i[84] :
(N11)? data_i[148] :
(N13)? data_i[212] :
(N8)? data_i[276] :
(N10)? data_i[340] :
(N12)? data_i[404] :
(N14)? data_i[468] : 1'b0;
assign data_o[19] = (N7)? data_i[19] :
(N9)? data_i[83] :
(N11)? data_i[147] :
(N13)? data_i[211] :
(N8)? data_i[275] :
(N10)? data_i[339] :
(N12)? data_i[403] :
(N14)? data_i[467] : 1'b0;
assign data_o[18] = (N7)? data_i[18] :
(N9)? data_i[82] :
(N11)? data_i[146] :
(N13)? data_i[210] :
(N8)? data_i[274] :
(N10)? data_i[338] :
(N12)? data_i[402] :
(N14)? data_i[466] : 1'b0;
assign data_o[17] = (N7)? data_i[17] :
(N9)? data_i[81] :
(N11)? data_i[145] :
(N13)? data_i[209] :
(N8)? data_i[273] :
(N10)? data_i[337] :
(N12)? data_i[401] :
(N14)? data_i[465] : 1'b0;
assign data_o[16] = (N7)? data_i[16] :
(N9)? data_i[80] :
(N11)? data_i[144] :
(N13)? data_i[208] :
(N8)? data_i[272] :
(N10)? data_i[336] :
(N12)? data_i[400] :
(N14)? data_i[464] : 1'b0;
assign data_o[15] = (N7)? data_i[15] :
(N9)? data_i[79] :
(N11)? data_i[143] :
(N13)? data_i[207] :
(N8)? data_i[271] :
(N10)? data_i[335] :
(N12)? data_i[399] :
(N14)? data_i[463] : 1'b0;
assign data_o[14] = (N7)? data_i[14] :
(N9)? data_i[78] :
(N11)? data_i[142] :
(N13)? data_i[206] :
(N8)? data_i[270] :
(N10)? data_i[334] :
(N12)? data_i[398] :
(N14)? data_i[462] : 1'b0;
assign data_o[13] = (N7)? data_i[13] :
(N9)? data_i[77] :
(N11)? data_i[141] :
(N13)? data_i[205] :
(N8)? data_i[269] :
(N10)? data_i[333] :
(N12)? data_i[397] :
(N14)? data_i[461] : 1'b0;
assign data_o[12] = (N7)? data_i[12] :
(N9)? data_i[76] :
(N11)? data_i[140] :
(N13)? data_i[204] :
(N8)? data_i[268] :
(N10)? data_i[332] :
(N12)? data_i[396] :
(N14)? data_i[460] : 1'b0;
assign data_o[11] = (N7)? data_i[11] :
(N9)? data_i[75] :
(N11)? data_i[139] :
(N13)? data_i[203] :
(N8)? data_i[267] :
(N10)? data_i[331] :
(N12)? data_i[395] :
(N14)? data_i[459] : 1'b0;
assign data_o[10] = (N7)? data_i[10] :
(N9)? data_i[74] :
(N11)? data_i[138] :
(N13)? data_i[202] :
(N8)? data_i[266] :
(N10)? data_i[330] :
(N12)? data_i[394] :
(N14)? data_i[458] : 1'b0;
assign data_o[9] = (N7)? data_i[9] :
(N9)? data_i[73] :
(N11)? data_i[137] :
(N13)? data_i[201] :
(N8)? data_i[265] :
(N10)? data_i[329] :
(N12)? data_i[393] :
(N14)? data_i[457] : 1'b0;
assign data_o[8] = (N7)? data_i[8] :
(N9)? data_i[72] :
(N11)? data_i[136] :
(N13)? data_i[200] :
(N8)? data_i[264] :
(N10)? data_i[328] :
(N12)? data_i[392] :
(N14)? data_i[456] : 1'b0;
assign data_o[7] = (N7)? data_i[7] :
(N9)? data_i[71] :
(N11)? data_i[135] :
(N13)? data_i[199] :
(N8)? data_i[263] :
(N10)? data_i[327] :
(N12)? data_i[391] :
(N14)? data_i[455] : 1'b0;
assign data_o[6] = (N7)? data_i[6] :
(N9)? data_i[70] :
(N11)? data_i[134] :
(N13)? data_i[198] :
(N8)? data_i[262] :
(N10)? data_i[326] :
(N12)? data_i[390] :
(N14)? data_i[454] : 1'b0;
assign data_o[5] = (N7)? data_i[5] :
(N9)? data_i[69] :
(N11)? data_i[133] :
(N13)? data_i[197] :
(N8)? data_i[261] :
(N10)? data_i[325] :
(N12)? data_i[389] :
(N14)? data_i[453] : 1'b0;
assign data_o[4] = (N7)? data_i[4] :
(N9)? data_i[68] :
(N11)? data_i[132] :
(N13)? data_i[196] :
(N8)? data_i[260] :
(N10)? data_i[324] :
(N12)? data_i[388] :
(N14)? data_i[452] : 1'b0;
assign data_o[3] = (N7)? data_i[3] :
(N9)? data_i[67] :
(N11)? data_i[131] :
(N13)? data_i[195] :
(N8)? data_i[259] :
(N10)? data_i[323] :
(N12)? data_i[387] :
(N14)? data_i[451] : 1'b0;
assign data_o[2] = (N7)? data_i[2] :
(N9)? data_i[66] :
(N11)? data_i[130] :
(N13)? data_i[194] :
(N8)? data_i[258] :
(N10)? data_i[322] :
(N12)? data_i[386] :
(N14)? data_i[450] : 1'b0;
assign data_o[1] = (N7)? data_i[1] :
(N9)? data_i[65] :
(N11)? data_i[129] :
(N13)? data_i[193] :
(N8)? data_i[257] :
(N10)? data_i[321] :
(N12)? data_i[385] :
(N14)? data_i[449] : 1'b0;
assign data_o[0] = (N7)? data_i[0] :
(N9)? data_i[64] :
(N11)? data_i[128] :
(N13)? data_i[192] :
(N8)? data_i[256] :
(N10)? data_i[320] :
(N12)? data_i[384] :
(N14)? data_i[448] : 1'b0;
assign N0 = ~sel_i[0];
assign N1 = ~sel_i[1];
assign N2 = N0 & N1;
assign N3 = N0 & sel_i[1];
assign N4 = sel_i[0] & N1;
assign N5 = sel_i[0] & sel_i[1];
assign N6 = ~sel_i[2];
assign N7 = N2 & N6;
assign N8 = N2 & sel_i[2];
assign N9 = N4 & N6;
assign N10 = N4 & sel_i[2];
assign N11 = N3 & N6;
assign N12 = N3 & sel_i[2];
assign N13 = N5 & N6;
assign N14 = N5 & sel_i[2];
endmodule
|
module bsg_mux_one_hot_width_p28_els_p2
(
data_i,
sel_one_hot_i,
data_o
);
input [55:0] data_i;
input [1:0] sel_one_hot_i;
output [27:0] data_o;
wire [27:0] data_o;
wire [55:0] data_masked;
assign data_masked[27] = data_i[27] & sel_one_hot_i[0];
assign data_masked[26] = data_i[26] & sel_one_hot_i[0];
assign data_masked[25] = data_i[25] & sel_one_hot_i[0];
assign data_masked[24] = data_i[24] & sel_one_hot_i[0];
assign data_masked[23] = data_i[23] & sel_one_hot_i[0];
assign data_masked[22] = data_i[22] & sel_one_hot_i[0];
assign data_masked[21] = data_i[21] & sel_one_hot_i[0];
assign data_masked[20] = data_i[20] & sel_one_hot_i[0];
assign data_masked[19] = data_i[19] & sel_one_hot_i[0];
assign data_masked[18] = data_i[18] & sel_one_hot_i[0];
assign data_masked[17] = data_i[17] & sel_one_hot_i[0];
assign data_masked[16] = data_i[16] & sel_one_hot_i[0];
assign data_masked[15] = data_i[15] & sel_one_hot_i[0];
assign data_masked[14] = data_i[14] & sel_one_hot_i[0];
assign data_masked[13] = data_i[13] & sel_one_hot_i[0];
assign data_masked[12] = data_i[12] & sel_one_hot_i[0];
assign data_masked[11] = data_i[11] & sel_one_hot_i[0];
assign data_masked[10] = data_i[10] & sel_one_hot_i[0];
assign data_masked[9] = data_i[9] & sel_one_hot_i[0];
assign data_masked[8] = data_i[8] & sel_one_hot_i[0];
assign data_masked[7] = data_i[7] & sel_one_hot_i[0];
assign data_masked[6] = data_i[6] & sel_one_hot_i[0];
assign data_masked[5] = data_i[5] & sel_one_hot_i[0];
assign data_masked[4] = data_i[4] & sel_one_hot_i[0];
assign data_masked[3] = data_i[3] & sel_one_hot_i[0];
assign data_masked[2] = data_i[2] & sel_one_hot_i[0];
assign data_masked[1] = data_i[1] & sel_one_hot_i[0];
assign data_masked[0] = data_i[0] & sel_one_hot_i[0];
assign data_masked[55] = data_i[55] & sel_one_hot_i[1];
assign data_masked[54] = data_i[54] & sel_one_hot_i[1];
assign data_masked[53] = data_i[53] & sel_one_hot_i[1];
assign data_masked[52] = data_i[52] & sel_one_hot_i[1];
assign data_masked[51] = data_i[51] & sel_one_hot_i[1];
assign data_masked[50] = data_i[50] & sel_one_hot_i[1];
assign data_masked[49] = data_i[49] & sel_one_hot_i[1];
assign data_masked[48] = data_i[48] & sel_one_hot_i[1];
assign data_masked[47] = data_i[47] & sel_one_hot_i[1];
assign data_masked[46] = data_i[46] & sel_one_hot_i[1];
assign data_masked[45] = data_i[45] & sel_one_hot_i[1];
assign data_masked[44] = data_i[44] & sel_one_hot_i[1];
assign data_masked[43] = data_i[43] & sel_one_hot_i[1];
assign data_masked[42] = data_i[42] & sel_one_hot_i[1];
assign data_masked[41] = data_i[41] & sel_one_hot_i[1];
assign data_masked[40] = data_i[40] & sel_one_hot_i[1];
assign data_masked[39] = data_i[39] & sel_one_hot_i[1];
assign data_masked[38] = data_i[38] & sel_one_hot_i[1];
assign data_masked[37] = data_i[37] & sel_one_hot_i[1];
assign data_masked[36] = data_i[36] & sel_one_hot_i[1];
assign data_masked[35] = data_i[35] & sel_one_hot_i[1];
assign data_masked[34] = data_i[34] & sel_one_hot_i[1];
assign data_masked[33] = data_i[33] & sel_one_hot_i[1];
assign data_masked[32] = data_i[32] & sel_one_hot_i[1];
assign data_masked[31] = data_i[31] & sel_one_hot_i[1];
assign data_masked[30] = data_i[30] & sel_one_hot_i[1];
assign data_masked[29] = data_i[29] & sel_one_hot_i[1];
assign data_masked[28] = data_i[28] & sel_one_hot_i[1];
assign data_o[0] = data_masked[28] | data_masked[0];
assign data_o[1] = data_masked[29] | data_masked[1];
assign data_o[2] = data_masked[30] | data_masked[2];
assign data_o[3] = data_masked[31] | data_masked[3];
assign data_o[4] = data_masked[32] | data_masked[4];
assign data_o[5] = data_masked[33] | data_masked[5];
assign data_o[6] = data_masked[34] | data_masked[6];
assign data_o[7] = data_masked[35] | data_masked[7];
assign data_o[8] = data_masked[36] | data_masked[8];
assign data_o[9] = data_masked[37] | data_masked[9];
assign data_o[10] = data_masked[38] | data_masked[10];
assign data_o[11] = data_masked[39] | data_masked[11];
assign data_o[12] = data_masked[40] | data_masked[12];
assign data_o[13] = data_masked[41] | data_masked[13];
assign data_o[14] = data_masked[42] | data_masked[14];
assign data_o[15] = data_masked[43] | data_masked[15];
assign data_o[16] = data_masked[44] | data_masked[16];
assign data_o[17] = data_masked[45] | data_masked[17];
assign data_o[18] = data_masked[46] | data_masked[18];
assign data_o[19] = data_masked[47] | data_masked[19];
assign data_o[20] = data_masked[48] | data_masked[20];
assign data_o[21] = data_masked[49] | data_masked[21];
assign data_o[22] = data_masked[50] | data_masked[22];
assign data_o[23] = data_masked[51] | data_masked[23];
assign data_o[24] = data_masked[52] | data_masked[24];
assign data_o[25] = data_masked[53] | data_masked[25];
assign data_o[26] = data_masked[54] | data_masked[26];
assign data_o[27] = data_masked[55] | data_masked[27];
endmodule
|
module bsg_mux_segmented_segments_p5_segment_width_p128
(
data0_i,
data1_i,
sel_i,
data_o
);
input [639:0] data0_i;
input [639:0] data1_i;
input [4:0] sel_i;
output [639:0] data_o;
wire [639:0] data_o;
wire N0,N1,N2,N3,N4,N5,N6,N7,N8,N9;
assign data_o[127:0] = (N0)? data1_i[127:0] :
(N5)? data0_i[127:0] : 1'b0;
assign N0 = sel_i[0];
assign data_o[255:128] = (N1)? data1_i[255:128] :
(N6)? data0_i[255:128] : 1'b0;
assign N1 = sel_i[1];
assign data_o[383:256] = (N2)? data1_i[383:256] :
(N7)? data0_i[383:256] : 1'b0;
assign N2 = sel_i[2];
assign data_o[511:384] = (N3)? data1_i[511:384] :
(N8)? data0_i[511:384] : 1'b0;
assign N3 = sel_i[3];
assign data_o[639:512] = (N4)? data1_i[639:512] :
(N9)? data0_i[639:512] : 1'b0;
assign N4 = sel_i[4];
assign N5 = ~sel_i[0];
assign N6 = ~sel_i[1];
assign N7 = ~sel_i[2];
assign N8 = ~sel_i[3];
assign N9 = ~sel_i[4];
endmodule
|
module bsg_mux_one_hot_width_p32_els_p2
(
data_i,
sel_one_hot_i,
data_o
);
input [63:0] data_i;
input [1:0] sel_one_hot_i;
output [31:0] data_o;
wire [31:0] data_o;
wire [63:0] data_masked;
assign data_masked[31] = data_i[31] & sel_one_hot_i[0];
assign data_masked[30] = data_i[30] & sel_one_hot_i[0];
assign data_masked[29] = data_i[29] & sel_one_hot_i[0];
assign data_masked[28] = data_i[28] & sel_one_hot_i[0];
assign data_masked[27] = data_i[27] & sel_one_hot_i[0];
assign data_masked[26] = data_i[26] & sel_one_hot_i[0];
assign data_masked[25] = data_i[25] & sel_one_hot_i[0];
assign data_masked[24] = data_i[24] & sel_one_hot_i[0];
assign data_masked[23] = data_i[23] & sel_one_hot_i[0];
assign data_masked[22] = data_i[22] & sel_one_hot_i[0];
assign data_masked[21] = data_i[21] & sel_one_hot_i[0];
assign data_masked[20] = data_i[20] & sel_one_hot_i[0];
assign data_masked[19] = data_i[19] & sel_one_hot_i[0];
assign data_masked[18] = data_i[18] & sel_one_hot_i[0];
assign data_masked[17] = data_i[17] & sel_one_hot_i[0];
assign data_masked[16] = data_i[16] & sel_one_hot_i[0];
assign data_masked[15] = data_i[15] & sel_one_hot_i[0];
assign data_masked[14] = data_i[14] & sel_one_hot_i[0];
assign data_masked[13] = data_i[13] & sel_one_hot_i[0];
assign data_masked[12] = data_i[12] & sel_one_hot_i[0];
assign data_masked[11] = data_i[11] & sel_one_hot_i[0];
assign data_masked[10] = data_i[10] & sel_one_hot_i[0];
assign data_masked[9] = data_i[9] & sel_one_hot_i[0];
assign data_masked[8] = data_i[8] & sel_one_hot_i[0];
assign data_masked[7] = data_i[7] & sel_one_hot_i[0];
assign data_masked[6] = data_i[6] & sel_one_hot_i[0];
assign data_masked[5] = data_i[5] & sel_one_hot_i[0];
assign data_masked[4] = data_i[4] & sel_one_hot_i[0];
assign data_masked[3] = data_i[3] & sel_one_hot_i[0];
assign data_masked[2] = data_i[2] & sel_one_hot_i[0];
assign data_masked[1] = data_i[1] & sel_one_hot_i[0];
assign data_masked[0] = data_i[0] & sel_one_hot_i[0];
assign data_masked[63] = data_i[63] & sel_one_hot_i[1];
assign data_masked[62] = data_i[62] & sel_one_hot_i[1];
assign data_masked[61] = data_i[61] & sel_one_hot_i[1];
assign data_masked[60] = data_i[60] & sel_one_hot_i[1];
assign data_masked[59] = data_i[59] & sel_one_hot_i[1];
assign data_masked[58] = data_i[58] & sel_one_hot_i[1];
assign data_masked[57] = data_i[57] & sel_one_hot_i[1];
assign data_masked[56] = data_i[56] & sel_one_hot_i[1];
assign data_masked[55] = data_i[55] & sel_one_hot_i[1];
assign data_masked[54] = data_i[54] & sel_one_hot_i[1];
assign data_masked[53] = data_i[53] & sel_one_hot_i[1];
assign data_masked[52] = data_i[52] & sel_one_hot_i[1];
assign data_masked[51] = data_i[51] & sel_one_hot_i[1];
assign data_masked[50] = data_i[50] & sel_one_hot_i[1];
assign data_masked[49] = data_i[49] & sel_one_hot_i[1];
assign data_masked[48] = data_i[48] & sel_one_hot_i[1];
assign data_masked[47] = data_i[47] & sel_one_hot_i[1];
assign data_masked[46] = data_i[46] & sel_one_hot_i[1];
assign data_masked[45] = data_i[45] & sel_one_hot_i[1];
assign data_masked[44] = data_i[44] & sel_one_hot_i[1];
assign data_masked[43] = data_i[43] & sel_one_hot_i[1];
assign data_masked[42] = data_i[42] & sel_one_hot_i[1];
assign data_masked[41] = data_i[41] & sel_one_hot_i[1];
assign data_masked[40] = data_i[40] & sel_one_hot_i[1];
assign data_masked[39] = data_i[39] & sel_one_hot_i[1];
assign data_masked[38] = data_i[38] & sel_one_hot_i[1];
assign data_masked[37] = data_i[37] & sel_one_hot_i[1];
assign data_masked[36] = data_i[36] & sel_one_hot_i[1];
assign data_masked[35] = data_i[35] & sel_one_hot_i[1];
assign data_masked[34] = data_i[34] & sel_one_hot_i[1];
assign data_masked[33] = data_i[33] & sel_one_hot_i[1];
assign data_masked[32] = data_i[32] & sel_one_hot_i[1];
assign data_o[0] = data_masked[32] | data_masked[0];
assign data_o[1] = data_masked[33] | data_masked[1];
assign data_o[2] = data_masked[34] | data_masked[2];
assign data_o[3] = data_masked[35] | data_masked[3];
assign data_o[4] = data_masked[36] | data_masked[4];
assign data_o[5] = data_masked[37] | data_masked[5];
assign data_o[6] = data_masked[38] | data_masked[6];
assign data_o[7] = data_masked[39] | data_masked[7];
assign data_o[8] = data_masked[40] | data_masked[8];
assign data_o[9] = data_masked[41] | data_masked[9];
assign data_o[10] = data_masked[42] | data_masked[10];
assign data_o[11] = data_masked[43] | data_masked[11];
assign data_o[12] = data_masked[44] | data_masked[12];
assign data_o[13] = data_masked[45] | data_masked[13];
assign data_o[14] = data_masked[46] | data_masked[14];
assign data_o[15] = data_masked[47] | data_masked[15];
assign data_o[16] = data_masked[48] | data_masked[16];
assign data_o[17] = data_masked[49] | data_masked[17];
assign data_o[18] = data_masked[50] | data_masked[18];
assign data_o[19] = data_masked[51] | data_masked[19];
assign data_o[20] = data_masked[52] | data_masked[20];
assign data_o[21] = data_masked[53] | data_masked[21];
assign data_o[22] = data_masked[54] | data_masked[22];
assign data_o[23] = data_masked[55] | data_masked[23];
assign data_o[24] = data_masked[56] | data_masked[24];
assign data_o[25] = data_masked[57] | data_masked[25];
assign data_o[26] = data_masked[58] | data_masked[26];
assign data_o[27] = data_masked[59] | data_masked[27];
assign data_o[28] = data_masked[60] | data_masked[28];
assign data_o[29] = data_masked[61] | data_masked[29];
assign data_o[30] = data_masked[62] | data_masked[30];
assign data_o[31] = data_masked[63] | data_masked[31];
endmodule
|
module bp_be_pipe_mem_vaddr_width_p56_lce_sets_p64_cce_block_size_in_bytes_p64
(
clk_i,
reset_i,
decode_i,
rs1_i,
rs2_i,
imm_i,
exc_i,
mmu_cmd_o,
mmu_cmd_v_o,
mmu_cmd_ready_i,
mmu_resp_i,
mmu_resp_v_i,
mmu_resp_ready_o,
result_o,
cache_miss_o
);
input [42:0] decode_i;
input [63:0] rs1_i;
input [63:0] rs2_i;
input [63:0] imm_i;
input [6:0] exc_i;
output [123:0] mmu_cmd_o;
input [70:0] mmu_resp_i;
output [63:0] result_o;
input clk_i;
input reset_i;
input mmu_cmd_ready_i;
input mmu_resp_v_i;
output mmu_cmd_v_o;
output mmu_resp_ready_o;
output cache_miss_o;
wire [123:0] mmu_cmd_o;
wire [63:0] result_o;
wire mmu_cmd_v_o,mmu_resp_ready_o,cache_miss_o,N0,N1,N2,N3,N4,N5,N6,N7;
assign mmu_resp_ready_o = 1'b1;
assign mmu_cmd_o[123] = decode_i[22];
assign mmu_cmd_o[122] = decode_i[21];
assign mmu_cmd_o[121] = decode_i[20];
assign mmu_cmd_o[120] = decode_i[19];
assign mmu_cmd_o[63] = rs2_i[63];
assign mmu_cmd_o[62] = rs2_i[62];
assign mmu_cmd_o[61] = rs2_i[61];
assign mmu_cmd_o[60] = rs2_i[60];
assign mmu_cmd_o[59] = rs2_i[59];
assign mmu_cmd_o[58] = rs2_i[58];
assign mmu_cmd_o[57] = rs2_i[57];
assign mmu_cmd_o[56] = rs2_i[56];
assign mmu_cmd_o[55] = rs2_i[55];
assign mmu_cmd_o[54] = rs2_i[54];
assign mmu_cmd_o[53] = rs2_i[53];
assign mmu_cmd_o[52] = rs2_i[52];
assign mmu_cmd_o[51] = rs2_i[51];
assign mmu_cmd_o[50] = rs2_i[50];
assign mmu_cmd_o[49] = rs2_i[49];
assign mmu_cmd_o[48] = rs2_i[48];
assign mmu_cmd_o[47] = rs2_i[47];
assign mmu_cmd_o[46] = rs2_i[46];
assign mmu_cmd_o[45] = rs2_i[45];
assign mmu_cmd_o[44] = rs2_i[44];
assign mmu_cmd_o[43] = rs2_i[43];
assign mmu_cmd_o[42] = rs2_i[42];
assign mmu_cmd_o[41] = rs2_i[41];
assign mmu_cmd_o[40] = rs2_i[40];
assign mmu_cmd_o[39] = rs2_i[39];
assign mmu_cmd_o[38] = rs2_i[38];
assign mmu_cmd_o[37] = rs2_i[37];
assign mmu_cmd_o[36] = rs2_i[36];
assign mmu_cmd_o[35] = rs2_i[35];
assign mmu_cmd_o[34] = rs2_i[34];
assign mmu_cmd_o[33] = rs2_i[33];
assign mmu_cmd_o[32] = rs2_i[32];
assign mmu_cmd_o[31] = rs2_i[31];
assign mmu_cmd_o[30] = rs2_i[30];
assign mmu_cmd_o[29] = rs2_i[29];
assign mmu_cmd_o[28] = rs2_i[28];
assign mmu_cmd_o[27] = rs2_i[27];
assign mmu_cmd_o[26] = rs2_i[26];
assign mmu_cmd_o[25] = rs2_i[25];
assign mmu_cmd_o[24] = rs2_i[24];
assign mmu_cmd_o[23] = rs2_i[23];
assign mmu_cmd_o[22] = rs2_i[22];
assign mmu_cmd_o[21] = rs2_i[21];
assign mmu_cmd_o[20] = rs2_i[20];
assign mmu_cmd_o[19] = rs2_i[19];
assign mmu_cmd_o[18] = rs2_i[18];
assign mmu_cmd_o[17] = rs2_i[17];
assign mmu_cmd_o[16] = rs2_i[16];
assign mmu_cmd_o[15] = rs2_i[15];
assign mmu_cmd_o[14] = rs2_i[14];
assign mmu_cmd_o[13] = rs2_i[13];
assign mmu_cmd_o[12] = rs2_i[12];
assign mmu_cmd_o[11] = rs2_i[11];
assign mmu_cmd_o[10] = rs2_i[10];
assign mmu_cmd_o[9] = rs2_i[9];
assign mmu_cmd_o[8] = rs2_i[8];
assign mmu_cmd_o[7] = rs2_i[7];
assign mmu_cmd_o[6] = rs2_i[6];
assign mmu_cmd_o[5] = rs2_i[5];
assign mmu_cmd_o[4] = rs2_i[4];
assign mmu_cmd_o[3] = rs2_i[3];
assign mmu_cmd_o[2] = rs2_i[2];
assign mmu_cmd_o[1] = rs2_i[1];
assign mmu_cmd_o[0] = rs2_i[0];
assign result_o[63] = mmu_resp_i[70];
assign result_o[62] = mmu_resp_i[69];
assign result_o[61] = mmu_resp_i[68];
assign result_o[60] = mmu_resp_i[67];
assign result_o[59] = mmu_resp_i[66];
assign result_o[58] = mmu_resp_i[65];
assign result_o[57] = mmu_resp_i[64];
assign result_o[56] = mmu_resp_i[63];
assign result_o[55] = mmu_resp_i[62];
assign result_o[54] = mmu_resp_i[61];
assign result_o[53] = mmu_resp_i[60];
assign result_o[52] = mmu_resp_i[59];
assign result_o[51] = mmu_resp_i[58];
assign result_o[50] = mmu_resp_i[57];
assign result_o[49] = mmu_resp_i[56];
assign result_o[48] = mmu_resp_i[55];
assign result_o[47] = mmu_resp_i[54];
assign result_o[46] = mmu_resp_i[53];
assign result_o[45] = mmu_resp_i[52];
assign result_o[44] = mmu_resp_i[51];
assign result_o[43] = mmu_resp_i[50];
assign result_o[42] = mmu_resp_i[49];
assign result_o[41] = mmu_resp_i[48];
assign result_o[40] = mmu_resp_i[47];
assign result_o[39] = mmu_resp_i[46];
assign result_o[38] = mmu_resp_i[45];
assign result_o[37] = mmu_resp_i[44];
assign result_o[36] = mmu_resp_i[43];
assign result_o[35] = mmu_resp_i[42];
assign result_o[34] = mmu_resp_i[41];
assign result_o[33] = mmu_resp_i[40];
assign result_o[32] = mmu_resp_i[39];
assign result_o[31] = mmu_resp_i[38];
assign result_o[30] = mmu_resp_i[37];
assign result_o[29] = mmu_resp_i[36];
assign result_o[28] = mmu_resp_i[35];
assign result_o[27] = mmu_resp_i[34];
assign result_o[26] = mmu_resp_i[33];
assign result_o[25] = mmu_resp_i[32];
assign result_o[24] = mmu_resp_i[31];
assign result_o[23] = mmu_resp_i[30];
assign result_o[22] = mmu_resp_i[29];
assign result_o[21] = mmu_resp_i[28];
assign result_o[20] = mmu_resp_i[27];
assign result_o[19] = mmu_resp_i[26];
assign result_o[18] = mmu_resp_i[25];
assign result_o[17] = mmu_resp_i[24];
assign result_o[16] = mmu_resp_i[23];
assign result_o[15] = mmu_resp_i[22];
assign result_o[14] = mmu_resp_i[21];
assign result_o[13] = mmu_resp_i[20];
assign result_o[12] = mmu_resp_i[19];
assign result_o[11] = mmu_resp_i[18];
assign result_o[10] = mmu_resp_i[17];
assign result_o[9] = mmu_resp_i[16];
assign result_o[8] = mmu_resp_i[15];
assign result_o[7] = mmu_resp_i[14];
assign result_o[6] = mmu_resp_i[13];
assign result_o[5] = mmu_resp_i[12];
assign result_o[4] = mmu_resp_i[11];
assign result_o[3] = mmu_resp_i[10];
assign result_o[2] = mmu_resp_i[9];
assign result_o[1] = mmu_resp_i[8];
assign result_o[0] = mmu_resp_i[7];
assign cache_miss_o = mmu_resp_i[0];
assign mmu_cmd_o[119:64] = rs1_i[55:0] + imm_i[55:0];
assign mmu_cmd_v_o = N0 & N7;
assign N0 = decode_i[29] | decode_i[30];
assign N7 = ~N6;
assign N6 = N5 | exc_i[0];
assign N5 = N4 | exc_i[1];
assign N4 = N3 | exc_i[2];
assign N3 = N2 | exc_i[3];
assign N2 = N1 | exc_i[4];
assign N1 = exc_i[6] | exc_i[5];
endmodule
|
module bsg_round_robin_arb_inputs_p2
(
clk_i,
reset_i,
grants_en_i,
reqs_i,
grants_o,
sel_one_hot_o,
v_o,
tag_o,
yumi_i
);
input [1:0] reqs_i;
output [1:0] grants_o;
output [1:0] sel_one_hot_o;
output [0:0] tag_o;
input clk_i;
input reset_i;
input grants_en_i;
input yumi_i;
output v_o;
wire [1:0] grants_o,sel_one_hot_o;
wire [0:0] tag_o;
wire v_o,N0,N1,N2,N3,N4,N5,N6,N7,N8,N9,N10,N11,N12,N13,N14,N15,N16,N17,N18,N19,N20,
N21,N22;
reg [0:0] last_r;
assign N13 = N0 & N1;
assign N0 = ~reqs_i[1];
assign N1 = ~reqs_i[0];
assign N14 = reqs_i[1] & N2;
assign N2 = ~last_r[0];
assign N15 = N3 & reqs_i[0] & N4;
assign N3 = ~reqs_i[1];
assign N4 = ~last_r[0];
assign N16 = reqs_i[0] & last_r[0];
assign N17 = reqs_i[1] & N5 & last_r[0];
assign N5 = ~reqs_i[0];
assign sel_one_hot_o = (N6)? { 1'b0, 1'b0 } :
(N7)? { 1'b1, 1'b0 } :
(N8)? { 1'b0, 1'b1 } :
(N9)? { 1'b0, 1'b1 } :
(N10)? { 1'b1, 1'b0 } : 1'b0;
assign N6 = N13;
assign N7 = N14;
assign N8 = N15;
assign N9 = N16;
assign N10 = N17;
assign tag_o[0] = (N6)? 1'b0 :
(N7)? 1'b1 :
(N8)? 1'b0 :
(N9)? 1'b0 :
(N10)? 1'b1 : 1'b0;
assign N20 = (N11)? 1'b0 :
(N12)? tag_o[0] : 1'b0;
assign N11 = reset_i;
assign N12 = N19;
assign grants_o[1] = sel_one_hot_o[1] & grants_en_i;
assign grants_o[0] = sel_one_hot_o[0] & grants_en_i;
assign v_o = reqs_i[1] | reqs_i[0];
assign N18 = ~yumi_i;
assign N19 = ~reset_i;
assign N21 = N18 & N19;
assign N22 = ~N21;
always @(posedge clk_i) begin
if(N22) begin
{ last_r[0:0] } <= { N20 };
end
end
endmodule
|
module bsg_mux_segmented_segments_p8_segment_width_p8
(
data0_i,
data1_i,
sel_i,
data_o
);
input [63:0] data0_i;
input [63:0] data1_i;
input [7:0] sel_i;
output [63:0] data_o;
wire [63:0] data_o;
wire N0,N1,N2,N3,N4,N5,N6,N7,N8,N9,N10,N11,N12,N13,N14,N15;
assign data_o[7:0] = (N0)? data1_i[7:0] :
(N8)? data0_i[7:0] : 1'b0;
assign N0 = sel_i[0];
assign data_o[15:8] = (N1)? data1_i[15:8] :
(N9)? data0_i[15:8] : 1'b0;
assign N1 = sel_i[1];
assign data_o[23:16] = (N2)? data1_i[23:16] :
(N10)? data0_i[23:16] : 1'b0;
assign N2 = sel_i[2];
assign data_o[31:24] = (N3)? data1_i[31:24] :
(N11)? data0_i[31:24] : 1'b0;
assign N3 = sel_i[3];
assign data_o[39:32] = (N4)? data1_i[39:32] :
(N12)? data0_i[39:32] : 1'b0;
assign N4 = sel_i[4];
assign data_o[47:40] = (N5)? data1_i[47:40] :
(N13)? data0_i[47:40] : 1'b0;
assign N5 = sel_i[5];
assign data_o[55:48] = (N6)? data1_i[55:48] :
(N14)? data0_i[55:48] : 1'b0;
assign N6 = sel_i[6];
assign data_o[63:56] = (N7)? data1_i[63:56] :
(N15)? data0_i[63:56] : 1'b0;
assign N7 = sel_i[7];
assign N8 = ~sel_i[0];
assign N9 = ~sel_i[1];
assign N10 = ~sel_i[2];
assign N11 = ~sel_i[3];
assign N12 = ~sel_i[4];
assign N13 = ~sel_i[5];
assign N14 = ~sel_i[6];
assign N15 = ~sel_i[7];
endmodule
|
module bp_be_int_alu
(
src1_i,
src2_i,
op_i,
opw_v_i,
result_o
);
input [63:0] src1_i;
input [63:0] src2_i;
input [3:0] op_i;
output [63:0] result_o;
input opw_v_i;
wire [63:0] result_o,result_sgn;
wire N0,N1,N2,N3,N4,N5,N6,N7,N8,N9,N10,N11,N12,N13,N14,N15,N16,N17,N18,N19,N20,N21,
N22,N23,N24,N25,N26,N27,N28,N29,N30,N31,N32,N33,N34,N35,N36,N37,N38,N39,N40,N41,
N42,N43,N44,N45,N46,N47,N48,N49,N50,N51,N52,N53,N54,N55,N56,N57,N58,N59,N60,N61,
N62,N63,N64,N65,N66,N67,N68,N69,N70,N71,N72,N73,N74,N75,N76,N77,N78,N79,N80,N81,
N82,N83,N84,N85,N86,N87,N88,N89,N90,N91,N92,N93,N94,N95,N96,N97,N98,N99,N100,N101,
N102,N103,N104,N105,N106,N107,N108,N109,N110,N111,N112,N113,N114,N115,N116,N117,
N118,N119,N120,N121,N122,N123,N124,N125,N126,N127,N128,N129,N130,N131,N132,N133,
N134,N135,N136,N137,N138,N139,N140,N141,N142,N143,N144,N145,N146,N147,N148,N149,
N150,N151,N152,N153,N154,N155,N156,N157,N158,N159,N160,N161,N162,N163,N164,N165,
N166,N167,N168,N169,N170,N171,N172,N173,N174,N175,N176,N177,N178,N179,N180,N181,
N182,N183,N184,N185,N186,N187,N188,N189,N190,N191,N192,N193,N194,N195,N196,N197,
N198,N199,N200,N201,N202,N203,N204,N205,N206,N207,N208,N209,N210,N211,N212,N213,
N214,N215,N216,N217,N218,N219,N220,N221,N222,N223,N224,N225,N226,N227,N228,N229,
N230,N231,N232,N233,N234,N235,N236,N237,N238,N239,N240,N241,N242,N243,N244,N245,
N246,N247,N248,N249,N250,N251,N252,N253,N254,N255,N256,N257,N258,N259,N260,N261,
N262,N263,N264,N265,N266,N267,N268,N269,N270,N271,N272,N273,N274,N275,N276,N277,
N278,N279,N280,N281,N282,N283,N284,N285,N286,N287,N288,N289,N290,N291,N292,N293,
N294,N295,N296,N297,N298,N299,N300,N301,N302,N303,N304,N305,N306,N307,N308,N309,
N310,N311,N312,N313,N314,N315,N316,N317,N318,N319,N320,N321,N322,N323,N324,N325,
N326,N327,N328,N329,N330,N331,N332,N333,N334,N335,N336,N337,N338,N339,N340,N341,
N342,N343,N344,N345,N346,N347,N348,N349,N350,N351,N352,N353,N354,N355,N356,N357,
N358,N359,N360,N361,N362,N363,N364,N365,N366,N367,N368,N369,N370,N371,N372,N373,
N374,N375,N376,N377,N378,N379,N380,N381,N382,N383,N384,N385,N386,N387,N388,N389,
N390,N391,N392,N393,N394,N395,N396,N397,N398,N399,N400,N401,N402,N403,N404,N405,
N406,N407,N408,N409,N410,N411,N412,N413,N414,N415,N416,N417,N418,N419,N420,N421,
N422,N423,N424,N425,N426,N427,N428,N429,N430,N431,N432,N433,N434,N435,N436,N437,
N438,N439,N440,N441,N442,N443,N444,N445,N446,N447,N448,N449,N450,N451,N452,N453,
N454,N455,N456,N457,N458,N459,N460,N461,N462,N463,N464,N465,N466,N467,N468,N469,
N470,N471,N472,N473,N474,N475,N476,N477,N478,N479,N480,N481,N482,N483,N484,N485,
N486,N487,N488,N489,N490,N491,N492,N493,N494,N495,N496,N497,N498,N499,N500,N501,
N502,N503,N504,N505,N506,N507,N508,N509,N510,N511,N512,N513,N514,N515,N516,N517,
N518,N519,N520,N521,N522,N523,N524,N525,N526,N527,N528,N529,N530,N531,N532,N533,
N534,N535,N536,N537,N538,N539,N540,N541,N542,N543,N544,N545,N546,N547,N548,N549,
N550,N551,N552,N553,N554,N555,N556,N557,N558,N559,N560,N561,N562,N563,N564,N565,
N566,N567,N568,N569,N570,N571,N572,N573,N574,N575,N576,N577,N578,N579,N580,N581,
N582,N583,N584,N585,N586,N587,N588,N589,N590,N591,N592,N593,N594,N595,N596,N597,
N598,N599,N600,N601,N602,N603,N604,N605,N606,N607,N608,N609,N610,N611,N612,N613,
N614,N615,N616,N617,N618,N619,N620,N621,N622,N623,N624,N625,N626,N627,N628,N629,
N630,N631,N632,N633,N634,N635,N636,N637,N638,N639,N640,N641,N642,N643,N644,N645,
N646,N647,N648,N649,N650,N651,N652,N653,N654,N655,N656,N657,N658,N659,N660,N661,
N662,N663,N664,N665,N666,N667,N668,N669,N670,N671,N672,N673,N674,N675,N676,N677,
N678,N679,N680,N681,N682,N683,N684,N685,N686,N687,N688,N689,N690,N691,N692,N693,
N694,N695,N696,N697,N698,N699,N700,N701,N702,N703,N704,N705,N706,N707,N708,N709,
N710,N711,N712,N713,N714,N715,N716,N717,N718,N719,N720,N721,N722,N723,N724,N725,
N726,N727,N728,N729,N730,N731,N732,N733,N734,N735,N736,N737,N738,N739,N740,N741,
N742,N743,N744,N745,N746,N747,N748,N749,N750,N751,N752,N753,N754,N755,N756,N757,
N758,N759,N760,N761,N762,N763,N764,N765,N766,N767,N768,N769,N770,N771,N772,N773,
N774,N775,N776,N777,N778,N779,N780,N781,N782,N783,N784,N785,N786,N787,N788,N789,
N790,N791,N792,N793,N794,N795;
wire [31:0] resultw_sgn;
assign N27 = N231 & N35;
assign N28 = N272 | op_i[0];
assign N30 = N248 | N35;
assign N32 = N237 | N35;
assign N34 = N256 & op_i[0];
assign N36 = N272 | N35;
assign N37 = op_i[2] & N35;
assign { N134, N133, N132, N131, N130, N129, N128, N127, N126, N125, N124, N123, N122, N121, N120, N119, N118, N117, N116, N115, N114, N113, N112, N111, N110, N109, N108, N107, N106, N105, N104, N103 } = src1_i[31:0] << src2_i[4:0];
assign { N166, N165, N164, N163, N162, N161, N160, N159, N158, N157, N156, N155, N154, N153, N152, N151, N150, N149, N148, N147, N146, N145, N144, N143, N142, N141, N140, N139, N138, N137, N136, N135 } = src1_i[31:0] >> src2_i[4:0];
assign { N198, N197, N196, N195, N194, N193, N192, N191, N190, N189, N188, N187, N186, N185, N184, N183, N182, N181, N180, N179, N178, N177, N176, N175, N174, N173, N172, N171, N170, N169, N168, N167 } = $signed(src1_i[31:0]) >>> src2_i[4:0];
assign N231 = N271 & N236;
assign N232 = N241 & N35;
assign N233 = N231 & N232;
assign N234 = N272 | N238;
assign N237 = op_i[3] | N236;
assign N238 = op_i[1] | op_i[0];
assign N239 = N237 | N238;
assign N242 = N241 | op_i[0];
assign N243 = N237 | N242;
assign N245 = N241 | N35;
assign N246 = N237 | N245;
assign N248 = op_i[3] | op_i[2];
assign N249 = N248 | N273;
assign N251 = N237 | N273;
assign N253 = N271 | N236;
assign N254 = N253 | N273;
assign N256 = op_i[3] & op_i[2];
assign N257 = op_i[1] & op_i[0];
assign N258 = N256 & N257;
assign N259 = N248 | N242;
assign N261 = N272 | N242;
assign N263 = N253 | N238;
assign N265 = N253 | N242;
assign N267 = N248 | N245;
assign N269 = N272 | N245;
assign N272 = N271 | op_i[2];
assign N273 = op_i[1] | N35;
assign N274 = N272 | N273;
assign { N659, N658, N657, N656, N655, N654, N653, N652, N651, N650, N649, N648, N647, N646, N645, N644, N643, N642, N641, N640, N639, N638, N637, N636, N635, N634, N633, N632, N631, N630, N629, N628, N627, N626, N625, N624, N623, N622, N621, N620, N619, N618, N617, N616, N615, N614, N613, N612, N611, N610, N609, N608, N607, N606, N605, N604, N603, N602, N601, N600, N599, N598, N597, N596 } = src1_i << src2_i[5:0];
assign { N723, N722, N721, N720, N719, N718, N717, N716, N715, N714, N713, N712, N711, N710, N709, N708, N707, N706, N705, N704, N703, N702, N701, N700, N699, N698, N697, N696, N695, N694, N693, N692, N691, N690, N689, N688, N687, N686, N685, N684, N683, N682, N681, N680, N679, N678, N677, N676, N675, N674, N673, N672, N671, N670, N669, N668, N667, N666, N665, N664, N663, N662, N661, N660 } = src1_i >> src2_i[5:0];
assign { N787, N786, N785, N784, N783, N782, N781, N780, N779, N778, N777, N776, N775, N774, N773, N772, N771, N770, N769, N768, N767, N766, N765, N764, N763, N762, N761, N760, N759, N758, N757, N756, N755, N754, N753, N752, N751, N750, N749, N748, N747, N746, N745, N744, N743, N742, N741, N740, N739, N738, N737, N736, N735, N734, N733, N732, N731, N730, N729, N728, N727, N726, N725, N724 } = $signed(src1_i) >>> src2_i[5:0];
assign N788 = $signed(src1_i) < $signed(src2_i);
assign N789 = $signed(src1_i) >= $signed(src2_i);
assign N790 = src1_i == src2_i;
assign N791 = src1_i != src2_i;
assign N792 = src1_i < src2_i;
assign N793 = src1_i >= src2_i;
assign { N339, N338, N337, N336, N335, N334, N333, N332, N331, N330, N329, N328, N327, N326, N325, N324, N323, N322, N321, N320, N319, N318, N317, N316, N315, N314, N313, N312, N311, N310, N309, N308, N307, N306, N305, N304, N303, N302, N301, N300, N299, N298, N297, N296, N295, N294, N293, N292, N291, N290, N289, N288, N287, N286, N285, N284, N283, N282, N281, N280, N279, N278, N277, N276 } = $signed(src1_i) + $signed(src2_i);
assign { N70, N69, N68, N67, N66, N65, N64, N63, N62, N61, N60, N59, N58, N57, N56, N55, N54, N53, N52, N51, N50, N49, N48, N47, N46, N45, N44, N43, N42, N41, N40, N39 } = $signed(src1_i[31:0]) + $signed(src2_i[31:0]);
assign { N403, N402, N401, N400, N399, N398, N397, N396, N395, N394, N393, N392, N391, N390, N389, N388, N387, N386, N385, N384, N383, N382, N381, N380, N379, N378, N377, N376, N375, N374, N373, N372, N371, N370, N369, N368, N367, N366, N365, N364, N363, N362, N361, N360, N359, N358, N357, N356, N355, N354, N353, N352, N351, N350, N349, N348, N347, N346, N345, N344, N343, N342, N341, N340 } = $signed(src1_i) - $signed(src2_i);
assign { N102, N101, N100, N99, N98, N97, N96, N95, N94, N93, N92, N91, N90, N89, N88, N87, N86, N85, N84, N83, N82, N81, N80, N79, N78, N77, N76, N75, N74, N73, N72, N71 } = $signed(src1_i[31:0]) - $signed(src2_i[31:0]);
assign { N230, N229, N228, N227, N226, N225, N224, N223, N222, N221, N220, N219, N218, N217, N216, N215, N214, N213, N212, N211, N210, N209, N208, N207, N206, N205, N204, N203, N202, N201, N200, N199 } = (N0)? { N70, N69, N68, N67, N66, N65, N64, N63, N62, N61, N60, N59, N58, N57, N56, N55, N54, N53, N52, N51, N50, N49, N48, N47, N46, N45, N44, N43, N42, N41, N40, N39 } :
(N1)? { N102, N101, N100, N99, N98, N97, N96, N95, N94, N93, N92, N91, N90, N89, N88, N87, N86, N85, N84, N83, N82, N81, N80, N79, N78, N77, N76, N75, N74, N73, N72, N71 } :
(N2)? { N134, N133, N132, N131, N130, N129, N128, N127, N126, N125, N124, N123, N122, N121, N120, N119, N118, N117, N116, N115, N114, N113, N112, N111, N110, N109, N108, N107, N106, N105, N104, N103 } :
(N3)? { N166, N165, N164, N163, N162, N161, N160, N159, N158, N157, N156, N155, N154, N153, N152, N151, N150, N149, N148, N147, N146, N145, N144, N143, N142, N141, N140, N139, N138, N137, N136, N135 } :
(N4)? { N198, N197, N196, N195, N194, N193, N192, N191, N190, N189, N188, N187, N186, N185, N184, N183, N182, N181, N180, N179, N178, N177, N176, N175, N174, N173, N172, N171, N170, N169, N168, N167 } :
(N5)? { 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0 } : 1'b0;
assign N0 = N27;
assign N1 = N29;
assign N2 = N31;
assign N3 = N33;
assign N4 = N34;
assign N5 = N38;
assign resultw_sgn = (N6)? { N230, N229, N228, N227, N226, N225, N224, N223, N222, N221, N220, N219, N218, N217, N216, N215, N214, N213, N212, N211, N210, N209, N208, N207, N206, N205, N204, N203, N202, N201, N200, N199 } :
(N7)? { 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0 } : 1'b0;
assign N6 = N241;
assign N7 = op_i[1];
assign result_sgn = (N8)? { N339, N338, N337, N336, N335, N334, N333, N332, N331, N330, N329, N328, N327, N326, N325, N324, N323, N322, N321, N320, N319, N318, N317, N316, N315, N314, N313, N312, N311, N310, N309, N308, N307, N306, N305, N304, N303, N302, N301, N300, N299, N298, N297, N296, N295, N294, N293, N292, N291, N290, N289, N288, N287, N286, N285, N284, N283, N282, N281, N280, N279, N278, N277, N276 } :
(N9)? { N403, N402, N401, N400, N399, N398, N397, N396, N395, N394, N393, N392, N391, N390, N389, N388, N387, N386, N385, N384, N383, N382, N381, N380, N379, N378, N377, N376, N375, N374, N373, N372, N371, N370, N369, N368, N367, N366, N365, N364, N363, N362, N361, N360, N359, N358, N357, N356, N355, N354, N353, N352, N351, N350, N349, N348, N347, N346, N345, N344, N343, N342, N341, N340 } :
(N10)? { N404, N405, N406, N407, N408, N409, N410, N411, N412, N413, N414, N415, N416, N417, N418, N419, N420, N421, N422, N423, N424, N425, N426, N427, N428, N429, N430, N431, N432, N433, N434, N435, N436, N437, N438, N439, N440, N441, N442, N443, N444, N445, N446, N447, N448, N449, N450, N451, N452, N453, N454, N455, N456, N457, N458, N459, N460, N461, N462, N463, N464, N465, N466, N467 } :
(N11)? { N468, N469, N470, N471, N472, N473, N474, N475, N476, N477, N478, N479, N480, N481, N482, N483, N484, N485, N486, N487, N488, N489, N490, N491, N492, N493, N494, N495, N496, N497, N498, N499, N500, N501, N502, N503, N504, N505, N506, N507, N508, N509, N510, N511, N512, N513, N514, N515, N516, N517, N518, N519, N520, N521, N522, N523, N524, N525, N526, N527, N528, N529, N530, N531 } :
(N12)? { N532, N533, N534, N535, N536, N537, N538, N539, N540, N541, N542, N543, N544, N545, N546, N547, N548, N549, N550, N551, N552, N553, N554, N555, N556, N557, N558, N559, N560, N561, N562, N563, N564, N565, N566, N567, N568, N569, N570, N571, N572, N573, N574, N575, N576, N577, N578, N579, N580, N581, N582, N583, N584, N585, N586, N587, N588, N589, N590, N591, N592, N593, N594, N595 } :
(N13)? { N659, N658, N657, N656, N655, N654, N653, N652, N651, N650, N649, N648, N647, N646, N645, N644, N643, N642, N641, N640, N639, N638, N637, N636, N635, N634, N633, N632, N631, N630, N629, N628, N627, N626, N625, N624, N623, N622, N621, N620, N619, N618, N617, N616, N615, N614, N613, N612, N611, N610, N609, N608, N607, N606, N605, N604, N603, N602, N601, N600, N599, N598, N597, N596 } :
(N14)? { N723, N722, N721, N720, N719, N718, N717, N716, N715, N714, N713, N712, N711, N710, N709, N708, N707, N706, N705, N704, N703, N702, N701, N700, N699, N698, N697, N696, N695, N694, N693, N692, N691, N690, N689, N688, N687, N686, N685, N684, N683, N682, N681, N680, N679, N678, N677, N676, N675, N674, N673, N672, N671, N670, N669, N668, N667, N666, N665, N664, N663, N662, N661, N660 } :
(N15)? { N787, N786, N785, N784, N783, N782, N781, N780, N779, N778, N777, N776, N775, N774, N773, N772, N771, N770, N769, N768, N767, N766, N765, N764, N763, N762, N761, N760, N759, N758, N757, N756, N755, N754, N753, N752, N751, N750, N749, N748, N747, N746, N745, N744, N743, N742, N741, N740, N739, N738, N737, N736, N735, N734, N733, N732, N731, N730, N729, N728, N727, N726, N725, N724 } :
(N16)? src2_i :
(N17)? { 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, N788 } :
(N18)? { 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, N789 } :
(N19)? { 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, N790 } :
(N20)? { 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, N791 } :
(N21)? { 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, N792 } :
(N22)? { 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, N793 } :
(N23)? { 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0 } : 1'b0;
assign N8 = N233;
assign N9 = N235;
assign N10 = N240;
assign N11 = N244;
assign N12 = N247;
assign N13 = N250;
assign N14 = N252;
assign N15 = N255;
assign N16 = N258;
assign N17 = N260;
assign N18 = N262;
assign N19 = N264;
assign N20 = N266;
assign N21 = N268;
assign N22 = N270;
assign N23 = N275;
assign result_o = (N24)? { resultw_sgn[31:31], resultw_sgn[31:31], resultw_sgn[31:31], resultw_sgn[31:31], resultw_sgn[31:31], resultw_sgn[31:31], resultw_sgn[31:31], resultw_sgn[31:31], resultw_sgn[31:31], resultw_sgn[31:31], resultw_sgn[31:31], resultw_sgn[31:31], resultw_sgn[31:31], resultw_sgn[31:31], resultw_sgn[31:31], resultw_sgn[31:31], resultw_sgn[31:31], resultw_sgn[31:31], resultw_sgn[31:31], resultw_sgn[31:31], resultw_sgn[31:31], resultw_sgn[31:31], resultw_sgn[31:31], resultw_sgn[31:31], resultw_sgn[31:31], resultw_sgn[31:31], resultw_sgn[31:31], resultw_sgn[31:31], resultw_sgn[31:31], resultw_sgn[31:31], resultw_sgn[31:31], resultw_sgn[31:31], resultw_sgn } :
(N25)? result_sgn : 1'b0;
assign N24 = opw_v_i;
assign N25 = N794;
assign N26 = N241;
assign N29 = ~N28;
assign N31 = ~N30;
assign N33 = ~N32;
assign N35 = ~op_i[0];
assign N38 = N795 | N37;
assign N795 = ~N36;
assign N235 = ~N234;
assign N236 = ~op_i[2];
assign N240 = ~N239;
assign N241 = ~op_i[1];
assign N244 = ~N243;
assign N247 = ~N246;
assign N250 = ~N249;
assign N252 = ~N251;
assign N255 = ~N254;
assign N260 = ~N259;
assign N262 = ~N261;
assign N264 = ~N263;
assign N266 = ~N265;
assign N268 = ~N267;
assign N270 = ~N269;
assign N271 = ~op_i[3];
assign N275 = ~N274;
assign N404 = src1_i[63] ^ src2_i[63];
assign N405 = src1_i[62] ^ src2_i[62];
assign N406 = src1_i[61] ^ src2_i[61];
assign N407 = src1_i[60] ^ src2_i[60];
assign N408 = src1_i[59] ^ src2_i[59];
assign N409 = src1_i[58] ^ src2_i[58];
assign N410 = src1_i[57] ^ src2_i[57];
assign N411 = src1_i[56] ^ src2_i[56];
assign N412 = src1_i[55] ^ src2_i[55];
assign N413 = src1_i[54] ^ src2_i[54];
assign N414 = src1_i[53] ^ src2_i[53];
assign N415 = src1_i[52] ^ src2_i[52];
assign N416 = src1_i[51] ^ src2_i[51];
assign N417 = src1_i[50] ^ src2_i[50];
assign N418 = src1_i[49] ^ src2_i[49];
assign N419 = src1_i[48] ^ src2_i[48];
assign N420 = src1_i[47] ^ src2_i[47];
assign N421 = src1_i[46] ^ src2_i[46];
assign N422 = src1_i[45] ^ src2_i[45];
assign N423 = src1_i[44] ^ src2_i[44];
assign N424 = src1_i[43] ^ src2_i[43];
assign N425 = src1_i[42] ^ src2_i[42];
assign N426 = src1_i[41] ^ src2_i[41];
assign N427 = src1_i[40] ^ src2_i[40];
assign N428 = src1_i[39] ^ src2_i[39];
assign N429 = src1_i[38] ^ src2_i[38];
assign N430 = src1_i[37] ^ src2_i[37];
assign N431 = src1_i[36] ^ src2_i[36];
assign N432 = src1_i[35] ^ src2_i[35];
assign N433 = src1_i[34] ^ src2_i[34];
assign N434 = src1_i[33] ^ src2_i[33];
assign N435 = src1_i[32] ^ src2_i[32];
assign N436 = src1_i[31] ^ src2_i[31];
assign N437 = src1_i[30] ^ src2_i[30];
assign N438 = src1_i[29] ^ src2_i[29];
assign N439 = src1_i[28] ^ src2_i[28];
assign N440 = src1_i[27] ^ src2_i[27];
assign N441 = src1_i[26] ^ src2_i[26];
assign N442 = src1_i[25] ^ src2_i[25];
assign N443 = src1_i[24] ^ src2_i[24];
assign N444 = src1_i[23] ^ src2_i[23];
assign N445 = src1_i[22] ^ src2_i[22];
assign N446 = src1_i[21] ^ src2_i[21];
assign N447 = src1_i[20] ^ src2_i[20];
assign N448 = src1_i[19] ^ src2_i[19];
assign N449 = src1_i[18] ^ src2_i[18];
assign N450 = src1_i[17] ^ src2_i[17];
assign N451 = src1_i[16] ^ src2_i[16];
assign N452 = src1_i[15] ^ src2_i[15];
assign N453 = src1_i[14] ^ src2_i[14];
assign N454 = src1_i[13] ^ src2_i[13];
assign N455 = src1_i[12] ^ src2_i[12];
assign N456 = src1_i[11] ^ src2_i[11];
assign N457 = src1_i[10] ^ src2_i[10];
assign N458 = src1_i[9] ^ src2_i[9];
assign N459 = src1_i[8] ^ src2_i[8];
assign N460 = src1_i[7] ^ src2_i[7];
assign N461 = src1_i[6] ^ src2_i[6];
assign N462 = src1_i[5] ^ src2_i[5];
assign N463 = src1_i[4] ^ src2_i[4];
assign N464 = src1_i[3] ^ src2_i[3];
assign N465 = src1_i[2] ^ src2_i[2];
assign N466 = src1_i[1] ^ src2_i[1];
assign N467 = src1_i[0] ^ src2_i[0];
assign N468 = src1_i[63] | src2_i[63];
assign N469 = src1_i[62] | src2_i[62];
assign N470 = src1_i[61] | src2_i[61];
assign N471 = src1_i[60] | src2_i[60];
assign N472 = src1_i[59] | src2_i[59];
assign N473 = src1_i[58] | src2_i[58];
assign N474 = src1_i[57] | src2_i[57];
assign N475 = src1_i[56] | src2_i[56];
assign N476 = src1_i[55] | src2_i[55];
assign N477 = src1_i[54] | src2_i[54];
assign N478 = src1_i[53] | src2_i[53];
assign N479 = src1_i[52] | src2_i[52];
assign N480 = src1_i[51] | src2_i[51];
assign N481 = src1_i[50] | src2_i[50];
assign N482 = src1_i[49] | src2_i[49];
assign N483 = src1_i[48] | src2_i[48];
assign N484 = src1_i[47] | src2_i[47];
assign N485 = src1_i[46] | src2_i[46];
assign N486 = src1_i[45] | src2_i[45];
assign N487 = src1_i[44] | src2_i[44];
assign N488 = src1_i[43] | src2_i[43];
assign N489 = src1_i[42] | src2_i[42];
assign N490 = src1_i[41] | src2_i[41];
assign N491 = src1_i[40] | src2_i[40];
assign N492 = src1_i[39] | src2_i[39];
assign N493 = src1_i[38] | src2_i[38];
assign N494 = src1_i[37] | src2_i[37];
assign N495 = src1_i[36] | src2_i[36];
assign N496 = src1_i[35] | src2_i[35];
assign N497 = src1_i[34] | src2_i[34];
assign N498 = src1_i[33] | src2_i[33];
assign N499 = src1_i[32] | src2_i[32];
assign N500 = src1_i[31] | src2_i[31];
assign N501 = src1_i[30] | src2_i[30];
assign N502 = src1_i[29] | src2_i[29];
assign N503 = src1_i[28] | src2_i[28];
assign N504 = src1_i[27] | src2_i[27];
assign N505 = src1_i[26] | src2_i[26];
assign N506 = src1_i[25] | src2_i[25];
assign N507 = src1_i[24] | src2_i[24];
assign N508 = src1_i[23] | src2_i[23];
assign N509 = src1_i[22] | src2_i[22];
assign N510 = src1_i[21] | src2_i[21];
assign N511 = src1_i[20] | src2_i[20];
assign N512 = src1_i[19] | src2_i[19];
assign N513 = src1_i[18] | src2_i[18];
assign N514 = src1_i[17] | src2_i[17];
assign N515 = src1_i[16] | src2_i[16];
assign N516 = src1_i[15] | src2_i[15];
assign N517 = src1_i[14] | src2_i[14];
assign N518 = src1_i[13] | src2_i[13];
assign N519 = src1_i[12] | src2_i[12];
assign N520 = src1_i[11] | src2_i[11];
assign N521 = src1_i[10] | src2_i[10];
assign N522 = src1_i[9] | src2_i[9];
assign N523 = src1_i[8] | src2_i[8];
assign N524 = src1_i[7] | src2_i[7];
assign N525 = src1_i[6] | src2_i[6];
assign N526 = src1_i[5] | src2_i[5];
assign N527 = src1_i[4] | src2_i[4];
assign N528 = src1_i[3] | src2_i[3];
assign N529 = src1_i[2] | src2_i[2];
assign N530 = src1_i[1] | src2_i[1];
assign N531 = src1_i[0] | src2_i[0];
assign N532 = src1_i[63] & src2_i[63];
assign N533 = src1_i[62] & src2_i[62];
assign N534 = src1_i[61] & src2_i[61];
assign N535 = src1_i[60] & src2_i[60];
assign N536 = src1_i[59] & src2_i[59];
assign N537 = src1_i[58] & src2_i[58];
assign N538 = src1_i[57] & src2_i[57];
assign N539 = src1_i[56] & src2_i[56];
assign N540 = src1_i[55] & src2_i[55];
assign N541 = src1_i[54] & src2_i[54];
assign N542 = src1_i[53] & src2_i[53];
assign N543 = src1_i[52] & src2_i[52];
assign N544 = src1_i[51] & src2_i[51];
assign N545 = src1_i[50] & src2_i[50];
assign N546 = src1_i[49] & src2_i[49];
assign N547 = src1_i[48] & src2_i[48];
assign N548 = src1_i[47] & src2_i[47];
assign N549 = src1_i[46] & src2_i[46];
assign N550 = src1_i[45] & src2_i[45];
assign N551 = src1_i[44] & src2_i[44];
assign N552 = src1_i[43] & src2_i[43];
assign N553 = src1_i[42] & src2_i[42];
assign N554 = src1_i[41] & src2_i[41];
assign N555 = src1_i[40] & src2_i[40];
assign N556 = src1_i[39] & src2_i[39];
assign N557 = src1_i[38] & src2_i[38];
assign N558 = src1_i[37] & src2_i[37];
assign N559 = src1_i[36] & src2_i[36];
assign N560 = src1_i[35] & src2_i[35];
assign N561 = src1_i[34] & src2_i[34];
assign N562 = src1_i[33] & src2_i[33];
assign N563 = src1_i[32] & src2_i[32];
assign N564 = src1_i[31] & src2_i[31];
assign N565 = src1_i[30] & src2_i[30];
assign N566 = src1_i[29] & src2_i[29];
assign N567 = src1_i[28] & src2_i[28];
assign N568 = src1_i[27] & src2_i[27];
assign N569 = src1_i[26] & src2_i[26];
assign N570 = src1_i[25] & src2_i[25];
assign N571 = src1_i[24] & src2_i[24];
assign N572 = src1_i[23] & src2_i[23];
assign N573 = src1_i[22] & src2_i[22];
assign N574 = src1_i[21] & src2_i[21];
assign N575 = src1_i[20] & src2_i[20];
assign N576 = src1_i[19] & src2_i[19];
assign N577 = src1_i[18] & src2_i[18];
assign N578 = src1_i[17] & src2_i[17];
assign N579 = src1_i[16] & src2_i[16];
assign N580 = src1_i[15] & src2_i[15];
assign N581 = src1_i[14] & src2_i[14];
assign N582 = src1_i[13] & src2_i[13];
assign N583 = src1_i[12] & src2_i[12];
assign N584 = src1_i[11] & src2_i[11];
assign N585 = src1_i[10] & src2_i[10];
assign N586 = src1_i[9] & src2_i[9];
assign N587 = src1_i[8] & src2_i[8];
assign N588 = src1_i[7] & src2_i[7];
assign N589 = src1_i[6] & src2_i[6];
assign N590 = src1_i[5] & src2_i[5];
assign N591 = src1_i[4] & src2_i[4];
assign N592 = src1_i[3] & src2_i[3];
assign N593 = src1_i[2] & src2_i[2];
assign N594 = src1_i[1] & src2_i[1];
assign N595 = src1_i[0] & src2_i[0];
assign N794 = ~opw_v_i;
endmodule
|
module bp_be_dcache_wbuf_queue_width_p97
(
clk_i,
data_i,
el0_en_i,
el1_en_i,
mux0_sel_i,
mux1_sel_i,
el0_snoop_o,
el1_snoop_o,
data_o
);
input [96:0] data_i;
output [96:0] el0_snoop_o;
output [96:0] el1_snoop_o;
output [96:0] data_o;
input clk_i;
input el0_en_i;
input el1_en_i;
input mux0_sel_i;
input mux1_sel_i;
wire [96:0] data_o;
wire N0,N1,N2,N3,N4,N5,N6,N7,N8,N9,N10,N11,N12,N13,N14,N15,N16,N17,N18,N19,N20,N21,
N22,N23,N24,N25,N26,N27,N28,N29,N30,N31,N32,N33,N34,N35,N36,N37,N38,N39,N40,N41,
N42,N43,N44,N45,N46,N47,N48,N49,N50,N51,N52,N53,N54,N55,N56,N57,N58,N59,N60,N61,
N62,N63,N64,N65,N66,N67,N68,N69,N70,N71,N72,N73,N74,N75,N76,N77,N78,N79,N80,N81,
N82,N83,N84,N85,N86,N87,N88,N89,N90,N91,N92,N93,N94,N95,N96,N97,N98,N99,N100,N101,
N102;
reg [96:0] el0_snoop_o,el1_snoop_o;
assign { N101, N100, N99, N98, N97, N96, N95, N94, N93, N92, N91, N90, N89, N88, N87, N86, N85, N84, N83, N82, N81, N80, N79, N78, N77, N76, N75, N74, N73, N72, N71, N70, N69, N68, N67, N66, N65, N64, N63, N62, N61, N60, N59, N58, N57, N56, N55, N54, N53, N52, N51, N50, N49, N48, N47, N46, N45, N44, N43, N42, N41, N40, N39, N38, N37, N36, N35, N34, N33, N32, N31, N30, N29, N28, N27, N26, N25, N24, N23, N22, N21, N20, N19, N18, N17, N16, N15, N14, N13, N12, N11, N10, N9, N8, N7, N6, N5 } = (N0)? el0_snoop_o :
(N1)? data_i : 1'b0;
assign N0 = mux0_sel_i;
assign N1 = N4;
assign data_o = (N2)? el1_snoop_o :
(N3)? data_i : 1'b0;
assign N2 = mux1_sel_i;
assign N3 = N102;
assign N4 = ~mux0_sel_i;
assign N102 = ~mux1_sel_i;
always @(posedge clk_i) begin
if(el0_en_i) begin
{ el0_snoop_o[96:0] } <= { data_i[96:0] };
end
if(el1_en_i) begin
{ el1_snoop_o[96:0] } <= { N101, N100, N99, N98, N97, N96, N95, N94, N93, N92, N91, N90, N89, N88, N87, N86, N85, N84, N83, N82, N81, N80, N79, N78, N77, N76, N75, N74, N73, N72, N71, N70, N69, N68, N67, N66, N65, N64, N63, N62, N61, N60, N59, N58, N57, N56, N55, N54, N53, N52, N51, N50, N49, N48, N47, N46, N45, N44, N43, N42, N41, N40, N39, N38, N37, N36, N35, N34, N33, N32, N31, N30, N29, N28, N27, N26, N25, N24, N23, N22, N21, N20, N19, N18, N17, N16, N15, N14, N13, N12, N11, N10, N9, N8, N7, N6, N5 };
end
end
endmodule
|
module bsg_circular_ptr_slots_p32_max_add_p1
(
clk,
reset_i,
add_i,
o
);
input [0:0] add_i;
output [4:0] o;
input clk;
input reset_i;
wire N0,N1,N2,N3,N4,N5,N6,N7,N8,N9,N10;
wire [4:0] genblk1_genblk1_ptr_r_p1;
reg [4:0] o;
assign genblk1_genblk1_ptr_r_p1 = o + 1'b1;
assign { N7, N6, N5, N4, N3 } = (N0)? { 1'b0, 1'b0, 1'b0, 1'b0, 1'b0 } :
(N1)? genblk1_genblk1_ptr_r_p1 : 1'b0;
assign N0 = reset_i;
assign N1 = N2;
assign N2 = ~reset_i;
assign N8 = ~add_i[0];
assign N9 = N8 & N2;
assign N10 = ~N9;
always @(posedge clk) begin
if(N10) begin
{ o[4:0] } <= { N7, N6, N5, N4, N3 };
end
end
endmodule
|
module bsg_round_robin_arb_inputs_p5
(
clk_i,
reset_i,
grants_en_i,
reqs_i,
grants_o,
sel_one_hot_o,
v_o,
tag_o,
yumi_i
);
input [4:0] reqs_i;
output [4:0] grants_o;
output [4:0] sel_one_hot_o;
output [2:0] tag_o;
input clk_i;
input reset_i;
input grants_en_i;
input yumi_i;
output v_o;
wire [4:0] grants_o,sel_one_hot_o;
wire [2:0] tag_o;
wire v_o,N0,N1,N2,N3,N4,N5,N6,N7,N8,N9,N10,N11,N12,N13,N14,N15,N16,N17,N18,N19,N20,
N21,N22,N23,N24,N25,N26,N27,N28,N29,N30,N31,N32,N33,N34,N35,N36,N37,N38,N39,N40,
N41,N42,N43,N44,N45,N46,N47,N48,N49,N50,N51,N52,N53,N54,N55,N56,N57,N58,N59,N60,
N61,N62,N63,N64,N65,N66,N67,N68,N69,N70,N71,N72,N73,N74,N75,N76,N77,N78,N79,N80,
N81,N82,N83,N84,N85,N86,N87,N88,N89,N90,N91,N92,N93,N94,N95,N96,N97,N98,N99,N100,
N101,N102,N103,N104,N105,N106,N107,N108,N109,N110,N111,N112,N113,N114,N115,N116,
N117,N118,N119,N120,N121,N122,N123,N124,N125,N126,N127,N128,N129,N130,N131,N132,
N133,N134,N135,N136,N137,N138,N139,N140,N141,N142,N143,N144,N145,N146,N147,N148,
N149,N150,N151,N152,N153,N154,N155,N156,N157,N158,N159,N160,N161,N162,N163,N164,
N165,N166,N167,N168,N169,N170,N171,N172,N173,N174,N175,N176,N177,N178,N179,N180,
N181,N182,N183,N184,N185,N186,N187,N188,N189,N190,N191,N192,N193,N194,N195;
reg [2:0] last_r;
assign N21 = N19 & N88;
assign N22 = N21 & N37;
assign N23 = N22 & N20;
assign N27 = N24 & N25;
assign N28 = N26 & reqs_i[1];
assign N29 = N27 & N28;
assign N31 = N24 & N25;
assign N32 = N26 & reqs_i[2];
assign N33 = N31 & N32;
assign N34 = N33 & N30;
assign N35 = N24 & N25;
assign N36 = N26 & reqs_i[3];
assign N37 = N56 & N30;
assign N38 = N35 & N36;
assign N39 = N38 & N37;
assign N40 = last_r[2] | last_r[1];
assign N41 = last_r[0] | N19;
assign N42 = N40 | N41;
assign N43 = N63 | reqs_i[1];
assign N44 = N42 | N43;
assign N46 = last_r[2] | last_r[1];
assign N47 = last_r[0] | reqs_i[4];
assign N48 = reqs_i[1] | N20;
assign N49 = N46 | N47;
assign N50 = N63 | N48;
assign N51 = N49 | N50;
assign N53 = N24 & N25;
assign N54 = last_r[0] & reqs_i[2];
assign N55 = N53 & N54;
assign N57 = N24 & N25;
assign N58 = last_r[0] & reqs_i[3];
assign N59 = N57 & N58;
assign N60 = N59 & N56;
assign N61 = last_r[2] | last_r[1];
assign N62 = N26 | N19;
assign N63 = reqs_i[3] | reqs_i[2];
assign N64 = N61 | N62;
assign N65 = N64 | N63;
assign N67 = N24 & N25;
assign N68 = last_r[0] & N19;
assign N69 = N88 & N56;
assign N70 = N67 & N68;
assign N71 = N69 & reqs_i[0];
assign N72 = N70 & N71;
assign N73 = last_r[2] | last_r[1];
assign N74 = N26 | reqs_i[4];
assign N75 = N30 | reqs_i[0];
assign N76 = N73 | N74;
assign N77 = N63 | N75;
assign N78 = N76 | N77;
assign N80 = N24 & last_r[1];
assign N81 = N26 & reqs_i[3];
assign N82 = N80 & N81;
assign N83 = last_r[2] | N25;
assign N84 = last_r[0] | N19;
assign N85 = N83 | N84;
assign N86 = N85 | reqs_i[3];
assign N89 = N24 & last_r[1];
assign N90 = N26 & N19;
assign N91 = N88 & reqs_i[0];
assign N92 = N89 & N90;
assign N93 = N92 & N91;
assign N94 = N24 & last_r[1];
assign N95 = N26 & N19;
assign N96 = N88 & reqs_i[1];
assign N97 = N94 & N95;
assign N98 = N96 & N20;
assign N99 = N97 & N98;
assign N100 = last_r[2] | N25;
assign N101 = last_r[0] | reqs_i[4];
assign N102 = reqs_i[3] | N56;
assign N103 = reqs_i[1] | reqs_i[0];
assign N104 = N100 | N101;
assign N105 = N102 | N103;
assign N106 = N104 | N105;
assign N108 = last_r[2] | N25;
assign N109 = N26 | N19;
assign N110 = N108 | N109;
assign N112 = N24 & last_r[1];
assign N113 = last_r[0] & N19;
assign N114 = N112 & N113;
assign N115 = N114 & reqs_i[0];
assign N116 = N24 & last_r[1];
assign N117 = last_r[0] & N19;
assign N118 = reqs_i[1] & N20;
assign N119 = N116 & N117;
assign N120 = N119 & N118;
assign N121 = N24 & last_r[1];
assign N122 = last_r[0] & N19;
assign N123 = reqs_i[2] & N30;
assign N124 = N121 & N122;
assign N125 = N123 & N20;
assign N126 = N124 & N125;
assign N127 = last_r[2] | N25;
assign N128 = N26 | reqs_i[4];
assign N129 = N88 | reqs_i[2];
assign N130 = N127 | N128;
assign N131 = N129 | N103;
assign N132 = N130 | N131;
assign N134 = last_r[2] & N25;
assign N135 = N26 & reqs_i[0];
assign N136 = N134 & N135;
assign N137 = last_r[2] & N25;
assign N138 = N26 & reqs_i[1];
assign N139 = N137 & N138;
assign N140 = N139 & N20;
assign N141 = last_r[2] & N25;
assign N142 = N26 & reqs_i[2];
assign N143 = N30 & N20;
assign N144 = N141 & N142;
assign N145 = N144 & N143;
assign N146 = last_r[2] & N25;
assign N147 = N26 & reqs_i[3];
assign N148 = N146 & N147;
assign N149 = N37 & N20;
assign N150 = N148 & N149;
assign N151 = N24 | last_r[1];
assign N152 = last_r[0] | N19;
assign N153 = N151 | N152;
assign N154 = N63 | N103;
assign N155 = N153 | N154;
assign N157 = last_r[2] & last_r[0];
assign N158 = N157 & reqs_i[2];
assign N159 = last_r[2] & last_r[0];
assign N160 = N159 & reqs_i[3];
assign N161 = last_r[2] & last_r[0];
assign N162 = N161 & reqs_i[4];
assign N163 = last_r[2] & last_r[0];
assign N164 = N163 & reqs_i[0];
assign N165 = last_r[2] & last_r[0];
assign N166 = N165 & reqs_i[1];
assign N167 = last_r[2] & last_r[1];
assign N168 = N167 & reqs_i[3];
assign N169 = last_r[2] & last_r[1];
assign N170 = N169 & reqs_i[4];
assign N171 = last_r[2] & last_r[1];
assign N172 = N171 & reqs_i[0];
assign N173 = last_r[2] & last_r[1];
assign N174 = N173 & reqs_i[1];
assign N175 = last_r[2] & last_r[1];
assign N176 = N175 & reqs_i[2];
assign sel_one_hot_o = (N0)? { 1'b0, 1'b0, 1'b0, 1'b0, 1'b0 } :
(N1)? { 1'b0, 1'b0, 1'b0, 1'b1, 1'b0 } :
(N2)? { 1'b0, 1'b0, 1'b1, 1'b0, 1'b0 } :
(N3)? { 1'b0, 1'b1, 1'b0, 1'b0, 1'b0 } :
(N45)? { 1'b1, 1'b0, 1'b0, 1'b0, 1'b0 } :
(N52)? { 1'b0, 1'b0, 1'b0, 1'b0, 1'b1 } :
(N4)? { 1'b0, 1'b0, 1'b1, 1'b0, 1'b0 } :
(N5)? { 1'b0, 1'b1, 1'b0, 1'b0, 1'b0 } :
(N66)? { 1'b1, 1'b0, 1'b0, 1'b0, 1'b0 } :
(N6)? { 1'b0, 1'b0, 1'b0, 1'b0, 1'b1 } :
(N79)? { 1'b0, 1'b0, 1'b0, 1'b1, 1'b0 } :
(N7)? { 1'b0, 1'b1, 1'b0, 1'b0, 1'b0 } :
(N87)? { 1'b1, 1'b0, 1'b0, 1'b0, 1'b0 } :
(N8)? { 1'b0, 1'b0, 1'b0, 1'b0, 1'b1 } :
(N9)? { 1'b0, 1'b0, 1'b0, 1'b1, 1'b0 } :
(N107)? { 1'b0, 1'b0, 1'b1, 1'b0, 1'b0 } :
(N111)? { 1'b1, 1'b0, 1'b0, 1'b0, 1'b0 } :
(N10)? { 1'b0, 1'b0, 1'b0, 1'b0, 1'b1 } :
(N11)? { 1'b0, 1'b0, 1'b0, 1'b1, 1'b0 } :
(N12)? { 1'b0, 1'b0, 1'b1, 1'b0, 1'b0 } :
(N133)? { 1'b0, 1'b1, 1'b0, 1'b0, 1'b0 } :
(N13)? { 1'b0, 1'b0, 1'b0, 1'b0, 1'b1 } :
(N14)? { 1'b0, 1'b0, 1'b0, 1'b1, 1'b0 } :
(N15)? { 1'b0, 1'b0, 1'b1, 1'b0, 1'b0 } :
(N16)? { 1'b0, 1'b1, 1'b0, 1'b0, 1'b0 } :
(N156)? { 1'b1, 1'b0, 1'b0, 1'b0, 1'b0 } : 1'b0;
assign N0 = N23;
assign N1 = N29;
assign N2 = N34;
assign N3 = N39;
assign N4 = N55;
assign N5 = N60;
assign N6 = N72;
assign N7 = N82;
assign N8 = N93;
assign N9 = N99;
assign N10 = N115;
assign N11 = N120;
assign N12 = N126;
assign N13 = N136;
assign N14 = N140;
assign N15 = N145;
assign N16 = N150;
assign tag_o = (N0)? { 1'b0, 1'b0, 1'b0 } :
(N1)? { 1'b0, 1'b0, 1'b1 } :
(N2)? { 1'b0, 1'b1, 1'b0 } :
(N3)? { 1'b0, 1'b1, 1'b1 } :
(N45)? { 1'b1, 1'b0, 1'b0 } :
(N52)? { 1'b0, 1'b0, 1'b0 } :
(N4)? { 1'b0, 1'b1, 1'b0 } :
(N5)? { 1'b0, 1'b1, 1'b1 } :
(N66)? { 1'b1, 1'b0, 1'b0 } :
(N6)? { 1'b0, 1'b0, 1'b0 } :
(N79)? { 1'b0, 1'b0, 1'b1 } :
(N7)? { 1'b0, 1'b1, 1'b1 } :
(N87)? { 1'b1, 1'b0, 1'b0 } :
(N8)? { 1'b0, 1'b0, 1'b0 } :
(N9)? { 1'b0, 1'b0, 1'b1 } :
(N107)? { 1'b0, 1'b1, 1'b0 } :
(N111)? { 1'b1, 1'b0, 1'b0 } :
(N10)? { 1'b0, 1'b0, 1'b0 } :
(N11)? { 1'b0, 1'b0, 1'b1 } :
(N12)? { 1'b0, 1'b1, 1'b0 } :
(N133)? { 1'b0, 1'b1, 1'b1 } :
(N13)? { 1'b0, 1'b0, 1'b0 } :
(N14)? { 1'b0, 1'b0, 1'b1 } :
(N15)? { 1'b0, 1'b1, 1'b0 } :
(N16)? { 1'b0, 1'b1, 1'b1 } :
(N156)? { 1'b1, 1'b0, 1'b0 } :
(N177)? { 1'b0, 1'b0, 1'b0 } : 1'b0;
assign { N182, N181, N180 } = (N17)? { 1'b0, 1'b0, 1'b0 } :
(N18)? tag_o : 1'b0;
assign N17 = reset_i;
assign N18 = N179;
assign N19 = ~reqs_i[4];
assign N20 = ~reqs_i[0];
assign N24 = ~last_r[2];
assign N25 = ~last_r[1];
assign N26 = ~last_r[0];
assign N30 = ~reqs_i[1];
assign N45 = ~N44;
assign N52 = ~N51;
assign N56 = ~reqs_i[2];
assign N66 = ~N65;
assign N79 = ~N78;
assign N87 = ~N86;
assign N88 = ~reqs_i[3];
assign N107 = ~N106;
assign N111 = ~N110;
assign N133 = ~N132;
assign N156 = ~N155;
assign N177 = N158 | N192;
assign N192 = N160 | N191;
assign N191 = N162 | N190;
assign N190 = N164 | N189;
assign N189 = N166 | N188;
assign N188 = N168 | N187;
assign N187 = N170 | N186;
assign N186 = N172 | N185;
assign N185 = N174 | N176;
assign grants_o[4] = sel_one_hot_o[4] & grants_en_i;
assign grants_o[3] = sel_one_hot_o[3] & grants_en_i;
assign grants_o[2] = sel_one_hot_o[2] & grants_en_i;
assign grants_o[1] = sel_one_hot_o[1] & grants_en_i;
assign grants_o[0] = sel_one_hot_o[0] & grants_en_i;
assign v_o = N195 | reqs_i[0];
assign N195 = N194 | reqs_i[1];
assign N194 = N193 | reqs_i[2];
assign N193 = reqs_i[4] | reqs_i[3];
assign N178 = ~yumi_i;
assign N179 = ~reset_i;
assign N183 = N178 & N179;
assign N184 = ~N183;
always @(posedge clk_i) begin
if(N184) begin
{ last_r[2:0] } <= { N182, N181, N180 };
end
end
endmodule
|
module bsg_scan_width_p5_or_p1_lo_to_hi_p1
(
i,
o
);
input [4:0] i;
output [4:0] o;
wire [4:0] o;
wire t_2__4_,t_2__3_,t_2__2_,t_2__1_,t_2__0_,t_1__4_,t_1__3_,t_1__2_,t_1__1_,t_1__0_;
assign t_1__4_ = i[0] | 1'b0;
assign t_1__3_ = i[1] | i[0];
assign t_1__2_ = i[2] | i[1];
assign t_1__1_ = i[3] | i[2];
assign t_1__0_ = i[4] | i[3];
assign t_2__4_ = t_1__4_ | 1'b0;
assign t_2__3_ = t_1__3_ | 1'b0;
assign t_2__2_ = t_1__2_ | t_1__4_;
assign t_2__1_ = t_1__1_ | t_1__3_;
assign t_2__0_ = t_1__0_ | t_1__2_;
assign o[0] = t_2__4_ | 1'b0;
assign o[1] = t_2__3_ | 1'b0;
assign o[2] = t_2__2_ | 1'b0;
assign o[3] = t_2__1_ | 1'b0;
assign o[4] = t_2__0_ | t_2__4_;
endmodule
|
module bp_cce_inst_decode_inst_width_p95_inst_addr_width_p8
(
clk_i,
reset_i,
inst_i,
inst_v_i,
lce_req_v_i,
lce_resp_v_i,
lce_data_resp_v_i,
mem_resp_v_i,
mem_data_resp_v_i,
pending_v_i,
lce_cmd_ready_i,
lce_data_cmd_ready_i,
mem_cmd_ready_i,
mem_data_cmd_ready_i,
decoded_inst_o,
decoded_inst_v_o,
pc_stall_o,
pc_branch_target_o
);
input [94:0] inst_i;
output [122:0] decoded_inst_o;
output [7:0] pc_branch_target_o;
input clk_i;
input reset_i;
input inst_v_i;
input lce_req_v_i;
input lce_resp_v_i;
input lce_data_resp_v_i;
input mem_resp_v_i;
input mem_data_resp_v_i;
input pending_v_i;
input lce_cmd_ready_i;
input lce_data_cmd_ready_i;
input mem_cmd_ready_i;
input mem_data_cmd_ready_i;
output decoded_inst_v_o;
output pc_stall_o;
wire [122:0] decoded_inst_o;
wire [7:0] pc_branch_target_o;
wire decoded_inst_v_o,pc_stall_o,N0,N1,N2,N3,N4,N5,N6,N7,N8,N9,N10,N11,N12,pushq_op,
popq_op,N13,N14,N15,N16,N17,N18,N19,N20,N21,N22,N23,N24,N25,N26,N27,N28,N29,N30,
N31,N32,N33,N34,N35,N36,N37,N38,wfq_op,stall_op,wfq_q_ready,N39,N40,N41,N42,N43,
N44,N45,N46,N47,N48,N49,N50,N51,N52,N53,N54,N55,N56,N57,N58,N59,N60,N61,N62,N63,
N64,N65,N66,N67,N68,N69,N70,N71,N72,N73,N74,N75,N76,N77,N78,N79,N80,N81,N82,N83,
N84,N85,N86,N87,N88,N89,N90,N91,N92,N93,N94,N95,N96,N97,N98,N99,N100,N101,N102,
N103,N104,N105,N106,N107,N108,N109,N110,N111,N112,N113,N114,N115,N116,N117,N118,
N119,N120,N121,N122,N123,N124,N125,N126,N127,N128,N129,N130,N131,N132,N133,N134,
N135,N136,N137,N138,N139,N140,N141,N142,N143,N144,N145,N146,N147,N148,N149,N150,
N151,N152;
assign N41 = N99 & N96;
assign N42 = inst_i[62] | N96;
assign N44 = N99 | inst_i[61];
assign N46 = inst_i[62] & inst_i[61];
assign N54 = inst_i[93] | inst_i[94];
assign N55 = inst_i[92] | N54;
assign N56 = ~N55;
assign N57 = ~inst_i[92];
assign N58 = N57 | N54;
assign N59 = ~N58;
assign N60 = ~inst_i[94];
assign N61 = ~inst_i[93];
assign N62 = N61 | N60;
assign N63 = inst_i[92] | N62;
assign N64 = ~N63;
assign N65 = inst_i[90] | inst_i[91];
assign N66 = inst_i[89] | N65;
assign N67 = ~N66;
assign N68 = inst_i[93] | N60;
assign N69 = inst_i[92] | N68;
assign N70 = ~N69;
assign N71 = ~inst_i[89];
assign N72 = N71 | N65;
assign N73 = ~N72;
assign N74 = ~inst_i[90];
assign N75 = N74 | inst_i[91];
assign N76 = inst_i[89] | N75;
assign N77 = ~N76;
assign N78 = inst_i[59] | inst_i[60];
assign N79 = inst_i[58] | N78;
assign N80 = ~N79;
assign N81 = ~inst_i[60];
assign N82 = inst_i[59] | N81;
assign N83 = inst_i[58] | N82;
assign N84 = ~N83;
assign N85 = ~inst_i[58];
assign N86 = N85 | N82;
assign N87 = ~N86;
assign N88 = N85 | N78;
assign N89 = ~N88;
assign N90 = ~inst_i[59];
assign N91 = N90 | inst_i[60];
assign N92 = inst_i[58] | N91;
assign N93 = ~N92;
assign N94 = inst_i[61] | inst_i[62];
assign N95 = ~N94;
assign N96 = ~inst_i[61];
assign N97 = N96 | inst_i[62];
assign N98 = ~N97;
assign N99 = ~inst_i[62];
assign N100 = inst_i[61] | N99;
assign N101 = ~N100;
assign N102 = inst_i[61] & inst_i[62];
assign N103 = ~inst_i[75];
assign N104 = ~inst_i[74];
assign N105 = inst_i[77] | inst_i[78];
assign N106 = inst_i[76] | N105;
assign N107 = N103 | N106;
assign N108 = N104 | N107;
assign N109 = ~N108;
assign N110 = inst_i[74] | N107;
assign N111 = ~N110;
assign N112 = inst_i[75] | N106;
assign N113 = N104 | N112;
assign N114 = ~N113;
assign N115 = inst_i[74] | N112;
assign N116 = ~N115;
assign N117 = N61 | inst_i[94];
assign N118 = inst_i[92] | N117;
assign N119 = ~N118;
assign N120 = inst_i[93] & inst_i[94];
assign N121 = inst_i[92] & N120;
assign N122 = N57 | N68;
assign N123 = ~N122;
assign N124 = inst_i[90] & inst_i[91];
assign N125 = inst_i[89] & N124;
assign { N18, N17, N16 } = (N0)? inst_i[91:89] :
(N1)? { 1'b0, 1'b0, 1'b0 } : 1'b0;
assign N0 = N70;
assign N1 = N69;
assign { N21, N20, N19 } = (N2)? inst_i[91:89] :
(N3)? { 1'b0, 1'b0, 1'b0 } : 1'b0;
assign N2 = N123;
assign N3 = N122;
assign decoded_inst_v_o = (N4)? 1'b0 :
(N14)? inst_v_i : 1'b0;
assign N4 = N13;
assign decoded_inst_o = (N4)? { 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0 } :
(N14)? { inst_i[91:58], N15, inst_i[57:28], N18, N17, N16, N70, N21, N20, N19, N123, inst_i[27:19], inst_i[60:58], inst_i[18:18], N119, N56, N22, N23, N24, N25, N26, inst_i[17:12], N27, N28, N29, inst_i[11:0], N30, N31, N32, N33, N34, N35, N36, N37, N38 } : 1'b0;
assign N51 = (N5)? N47 :
(N6)? N48 :
(N7)? N49 :
(N8)? N50 : 1'b0;
assign N5 = N41;
assign N6 = N43;
assign N7 = N45;
assign N8 = N46;
assign N52 = (N9)? N51 :
(N10)? N39 : 1'b0;
assign N9 = pushq_op;
assign N10 = N40;
assign pc_stall_o = (N11)? 1'b0 :
(N12)? N52 : 1'b0;
assign N11 = reset_i;
assign N12 = N53;
assign pc_branch_target_o = (N11)? { 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0 } :
(N12)? inst_i[65:58] : 1'b0;
assign pushq_op = N121 & N73;
assign popq_op = N121 & N77;
assign N13 = reset_i | N126;
assign N126 = ~inst_v_i;
assign N14 = ~N13;
assign N15 = N56 | N59;
assign N22 = N109 & N127;
assign N127 = N119 | N56;
assign N23 = N111 & N128;
assign N128 = N119 | N56;
assign N24 = N114 & N129;
assign N129 = N119 | N56;
assign N25 = N116 & N130;
assign N130 = N119 | N56;
assign N26 = N132 | N25;
assign N132 = N131 | N24;
assign N131 = N22 | N23;
assign N27 = N64 & N67;
assign N28 = N70 & N73;
assign N29 = N70 & N77;
assign N30 = popq_op & N80;
assign N31 = popq_op & N84;
assign N32 = popq_op & N87;
assign N33 = popq_op & N89;
assign N34 = popq_op & N93;
assign N35 = N133 & N95;
assign N133 = lce_cmd_ready_i & pushq_op;
assign N36 = N134 & N98;
assign N134 = lce_data_cmd_ready_i & pushq_op;
assign N37 = N135 & N101;
assign N135 = mem_cmd_ready_i & pushq_op;
assign N38 = N136 & N102;
assign N136 = mem_data_cmd_ready_i & pushq_op;
assign wfq_op = N121 & N67;
assign stall_op = N64 & N125;
assign wfq_q_ready = N145 | N146;
assign N145 = N143 | N144;
assign N143 = N141 | N142;
assign N141 = N139 | N140;
assign N139 = N137 | N138;
assign N137 = inst_i[63] & lce_req_v_i;
assign N138 = inst_i[62] & lce_resp_v_i;
assign N140 = inst_i[61] & lce_data_resp_v_i;
assign N142 = inst_i[60] & mem_resp_v_i;
assign N144 = inst_i[59] & mem_data_resp_v_i;
assign N146 = inst_i[58] & pending_v_i;
assign N39 = stall_op | N148;
assign N148 = wfq_op & N147;
assign N147 = ~wfq_q_ready;
assign N40 = ~pushq_op;
assign N43 = ~N42;
assign N45 = ~N44;
assign N47 = N39 | N149;
assign N149 = ~lce_cmd_ready_i;
assign N48 = N39 | N150;
assign N150 = ~lce_data_cmd_ready_i;
assign N49 = N39 | N151;
assign N151 = ~mem_cmd_ready_i;
assign N50 = N39 | N152;
assign N152 = ~mem_data_cmd_ready_i;
assign N53 = ~reset_i;
endmodule
|
module bsg_dff_width_p640
(
clk_i,
data_i,
data_o
);
input [639:0] data_i;
output [639:0] data_o;
input clk_i;
reg [639:0] data_o;
always @(posedge clk_i) begin
if(1'b1) begin
{ data_o[639:0] } <= { data_i[639:0] };
end
end
endmodule
|
module bsg_mem_1r1w_synth_width_p28_els_p2_read_write_same_addr_p0_harden_p0
(
w_clk_i,
w_reset_i,
w_v_i,
w_addr_i,
w_data_i,
r_v_i,
r_addr_i,
r_data_o
);
input [0:0] w_addr_i;
input [27:0] w_data_i;
input [0:0] r_addr_i;
output [27:0] r_data_o;
input w_clk_i;
input w_reset_i;
input w_v_i;
input r_v_i;
wire [27:0] r_data_o;
wire N0,N1,N2,N3,N4,N5,N7,N8;
reg [55:0] mem;
assign r_data_o[27] = (N3)? mem[27] :
(N0)? mem[55] : 1'b0;
assign N0 = r_addr_i[0];
assign r_data_o[26] = (N3)? mem[26] :
(N0)? mem[54] : 1'b0;
assign r_data_o[25] = (N3)? mem[25] :
(N0)? mem[53] : 1'b0;
assign r_data_o[24] = (N3)? mem[24] :
(N0)? mem[52] : 1'b0;
assign r_data_o[23] = (N3)? mem[23] :
(N0)? mem[51] : 1'b0;
assign r_data_o[22] = (N3)? mem[22] :
(N0)? mem[50] : 1'b0;
assign r_data_o[21] = (N3)? mem[21] :
(N0)? mem[49] : 1'b0;
assign r_data_o[20] = (N3)? mem[20] :
(N0)? mem[48] : 1'b0;
assign r_data_o[19] = (N3)? mem[19] :
(N0)? mem[47] : 1'b0;
assign r_data_o[18] = (N3)? mem[18] :
(N0)? mem[46] : 1'b0;
assign r_data_o[17] = (N3)? mem[17] :
(N0)? mem[45] : 1'b0;
assign r_data_o[16] = (N3)? mem[16] :
(N0)? mem[44] : 1'b0;
assign r_data_o[15] = (N3)? mem[15] :
(N0)? mem[43] : 1'b0;
assign r_data_o[14] = (N3)? mem[14] :
(N0)? mem[42] : 1'b0;
assign r_data_o[13] = (N3)? mem[13] :
(N0)? mem[41] : 1'b0;
assign r_data_o[12] = (N3)? mem[12] :
(N0)? mem[40] : 1'b0;
assign r_data_o[11] = (N3)? mem[11] :
(N0)? mem[39] : 1'b0;
assign r_data_o[10] = (N3)? mem[10] :
(N0)? mem[38] : 1'b0;
assign r_data_o[9] = (N3)? mem[9] :
(N0)? mem[37] : 1'b0;
assign r_data_o[8] = (N3)? mem[8] :
(N0)? mem[36] : 1'b0;
assign r_data_o[7] = (N3)? mem[7] :
(N0)? mem[35] : 1'b0;
assign r_data_o[6] = (N3)? mem[6] :
(N0)? mem[34] : 1'b0;
assign r_data_o[5] = (N3)? mem[5] :
(N0)? mem[33] : 1'b0;
assign r_data_o[4] = (N3)? mem[4] :
(N0)? mem[32] : 1'b0;
assign r_data_o[3] = (N3)? mem[3] :
(N0)? mem[31] : 1'b0;
assign r_data_o[2] = (N3)? mem[2] :
(N0)? mem[30] : 1'b0;
assign r_data_o[1] = (N3)? mem[1] :
(N0)? mem[29] : 1'b0;
assign r_data_o[0] = (N3)? mem[0] :
(N0)? mem[28] : 1'b0;
assign N5 = ~w_addr_i[0];
assign { N8, N7 } = (N1)? { w_addr_i[0:0], N5 } :
(N2)? { 1'b0, 1'b0 } : 1'b0;
assign N1 = w_v_i;
assign N2 = N4;
assign N3 = ~r_addr_i[0];
assign N4 = ~w_v_i;
always @(posedge w_clk_i) begin
if(N8) begin
{ mem[55:28] } <= { w_data_i[27:0] };
end
if(N7) begin
{ mem[27:0] } <= { w_data_i[27:0] };
end
end
endmodule
|
module bsg_mux_one_hot_width_p28_els_p4
(
data_i,
sel_one_hot_i,
data_o
);
input [111:0] data_i;
input [3:0] sel_one_hot_i;
output [27:0] data_o;
wire [27:0] data_o;
wire N0,N1,N2,N3,N4,N5,N6,N7,N8,N9,N10,N11,N12,N13,N14,N15,N16,N17,N18,N19,N20,N21,
N22,N23,N24,N25,N26,N27,N28,N29,N30,N31,N32,N33,N34,N35,N36,N37,N38,N39,N40,N41,
N42,N43,N44,N45,N46,N47,N48,N49,N50,N51,N52,N53,N54,N55;
wire [111:0] data_masked;
assign data_masked[27] = data_i[27] & sel_one_hot_i[0];
assign data_masked[26] = data_i[26] & sel_one_hot_i[0];
assign data_masked[25] = data_i[25] & sel_one_hot_i[0];
assign data_masked[24] = data_i[24] & sel_one_hot_i[0];
assign data_masked[23] = data_i[23] & sel_one_hot_i[0];
assign data_masked[22] = data_i[22] & sel_one_hot_i[0];
assign data_masked[21] = data_i[21] & sel_one_hot_i[0];
assign data_masked[20] = data_i[20] & sel_one_hot_i[0];
assign data_masked[19] = data_i[19] & sel_one_hot_i[0];
assign data_masked[18] = data_i[18] & sel_one_hot_i[0];
assign data_masked[17] = data_i[17] & sel_one_hot_i[0];
assign data_masked[16] = data_i[16] & sel_one_hot_i[0];
assign data_masked[15] = data_i[15] & sel_one_hot_i[0];
assign data_masked[14] = data_i[14] & sel_one_hot_i[0];
assign data_masked[13] = data_i[13] & sel_one_hot_i[0];
assign data_masked[12] = data_i[12] & sel_one_hot_i[0];
assign data_masked[11] = data_i[11] & sel_one_hot_i[0];
assign data_masked[10] = data_i[10] & sel_one_hot_i[0];
assign data_masked[9] = data_i[9] & sel_one_hot_i[0];
assign data_masked[8] = data_i[8] & sel_one_hot_i[0];
assign data_masked[7] = data_i[7] & sel_one_hot_i[0];
assign data_masked[6] = data_i[6] & sel_one_hot_i[0];
assign data_masked[5] = data_i[5] & sel_one_hot_i[0];
assign data_masked[4] = data_i[4] & sel_one_hot_i[0];
assign data_masked[3] = data_i[3] & sel_one_hot_i[0];
assign data_masked[2] = data_i[2] & sel_one_hot_i[0];
assign data_masked[1] = data_i[1] & sel_one_hot_i[0];
assign data_masked[0] = data_i[0] & sel_one_hot_i[0];
assign data_masked[55] = data_i[55] & sel_one_hot_i[1];
assign data_masked[54] = data_i[54] & sel_one_hot_i[1];
assign data_masked[53] = data_i[53] & sel_one_hot_i[1];
assign data_masked[52] = data_i[52] & sel_one_hot_i[1];
assign data_masked[51] = data_i[51] & sel_one_hot_i[1];
assign data_masked[50] = data_i[50] & sel_one_hot_i[1];
assign data_masked[49] = data_i[49] & sel_one_hot_i[1];
assign data_masked[48] = data_i[48] & sel_one_hot_i[1];
assign data_masked[47] = data_i[47] & sel_one_hot_i[1];
assign data_masked[46] = data_i[46] & sel_one_hot_i[1];
assign data_masked[45] = data_i[45] & sel_one_hot_i[1];
assign data_masked[44] = data_i[44] & sel_one_hot_i[1];
assign data_masked[43] = data_i[43] & sel_one_hot_i[1];
assign data_masked[42] = data_i[42] & sel_one_hot_i[1];
assign data_masked[41] = data_i[41] & sel_one_hot_i[1];
assign data_masked[40] = data_i[40] & sel_one_hot_i[1];
assign data_masked[39] = data_i[39] & sel_one_hot_i[1];
assign data_masked[38] = data_i[38] & sel_one_hot_i[1];
assign data_masked[37] = data_i[37] & sel_one_hot_i[1];
assign data_masked[36] = data_i[36] & sel_one_hot_i[1];
assign data_masked[35] = data_i[35] & sel_one_hot_i[1];
assign data_masked[34] = data_i[34] & sel_one_hot_i[1];
assign data_masked[33] = data_i[33] & sel_one_hot_i[1];
assign data_masked[32] = data_i[32] & sel_one_hot_i[1];
assign data_masked[31] = data_i[31] & sel_one_hot_i[1];
assign data_masked[30] = data_i[30] & sel_one_hot_i[1];
assign data_masked[29] = data_i[29] & sel_one_hot_i[1];
assign data_masked[28] = data_i[28] & sel_one_hot_i[1];
assign data_masked[83] = data_i[83] & sel_one_hot_i[2];
assign data_masked[82] = data_i[82] & sel_one_hot_i[2];
assign data_masked[81] = data_i[81] & sel_one_hot_i[2];
assign data_masked[80] = data_i[80] & sel_one_hot_i[2];
assign data_masked[79] = data_i[79] & sel_one_hot_i[2];
assign data_masked[78] = data_i[78] & sel_one_hot_i[2];
assign data_masked[77] = data_i[77] & sel_one_hot_i[2];
assign data_masked[76] = data_i[76] & sel_one_hot_i[2];
assign data_masked[75] = data_i[75] & sel_one_hot_i[2];
assign data_masked[74] = data_i[74] & sel_one_hot_i[2];
assign data_masked[73] = data_i[73] & sel_one_hot_i[2];
assign data_masked[72] = data_i[72] & sel_one_hot_i[2];
assign data_masked[71] = data_i[71] & sel_one_hot_i[2];
assign data_masked[70] = data_i[70] & sel_one_hot_i[2];
assign data_masked[69] = data_i[69] & sel_one_hot_i[2];
assign data_masked[68] = data_i[68] & sel_one_hot_i[2];
assign data_masked[67] = data_i[67] & sel_one_hot_i[2];
assign data_masked[66] = data_i[66] & sel_one_hot_i[2];
assign data_masked[65] = data_i[65] & sel_one_hot_i[2];
assign data_masked[64] = data_i[64] & sel_one_hot_i[2];
assign data_masked[63] = data_i[63] & sel_one_hot_i[2];
assign data_masked[62] = data_i[62] & sel_one_hot_i[2];
assign data_masked[61] = data_i[61] & sel_one_hot_i[2];
assign data_masked[60] = data_i[60] & sel_one_hot_i[2];
assign data_masked[59] = data_i[59] & sel_one_hot_i[2];
assign data_masked[58] = data_i[58] & sel_one_hot_i[2];
assign data_masked[57] = data_i[57] & sel_one_hot_i[2];
assign data_masked[56] = data_i[56] & sel_one_hot_i[2];
assign data_masked[111] = data_i[111] & sel_one_hot_i[3];
assign data_masked[110] = data_i[110] & sel_one_hot_i[3];
assign data_masked[109] = data_i[109] & sel_one_hot_i[3];
assign data_masked[108] = data_i[108] & sel_one_hot_i[3];
assign data_masked[107] = data_i[107] & sel_one_hot_i[3];
assign data_masked[106] = data_i[106] & sel_one_hot_i[3];
assign data_masked[105] = data_i[105] & sel_one_hot_i[3];
assign data_masked[104] = data_i[104] & sel_one_hot_i[3];
assign data_masked[103] = data_i[103] & sel_one_hot_i[3];
assign data_masked[102] = data_i[102] & sel_one_hot_i[3];
assign data_masked[101] = data_i[101] & sel_one_hot_i[3];
assign data_masked[100] = data_i[100] & sel_one_hot_i[3];
assign data_masked[99] = data_i[99] & sel_one_hot_i[3];
assign data_masked[98] = data_i[98] & sel_one_hot_i[3];
assign data_masked[97] = data_i[97] & sel_one_hot_i[3];
assign data_masked[96] = data_i[96] & sel_one_hot_i[3];
assign data_masked[95] = data_i[95] & sel_one_hot_i[3];
assign data_masked[94] = data_i[94] & sel_one_hot_i[3];
assign data_masked[93] = data_i[93] & sel_one_hot_i[3];
assign data_masked[92] = data_i[92] & sel_one_hot_i[3];
assign data_masked[91] = data_i[91] & sel_one_hot_i[3];
assign data_masked[90] = data_i[90] & sel_one_hot_i[3];
assign data_masked[89] = data_i[89] & sel_one_hot_i[3];
assign data_masked[88] = data_i[88] & sel_one_hot_i[3];
assign data_masked[87] = data_i[87] & sel_one_hot_i[3];
assign data_masked[86] = data_i[86] & sel_one_hot_i[3];
assign data_masked[85] = data_i[85] & sel_one_hot_i[3];
assign data_masked[84] = data_i[84] & sel_one_hot_i[3];
assign data_o[0] = N1 | data_masked[0];
assign N1 = N0 | data_masked[28];
assign N0 = data_masked[84] | data_masked[56];
assign data_o[1] = N3 | data_masked[1];
assign N3 = N2 | data_masked[29];
assign N2 = data_masked[85] | data_masked[57];
assign data_o[2] = N5 | data_masked[2];
assign N5 = N4 | data_masked[30];
assign N4 = data_masked[86] | data_masked[58];
assign data_o[3] = N7 | data_masked[3];
assign N7 = N6 | data_masked[31];
assign N6 = data_masked[87] | data_masked[59];
assign data_o[4] = N9 | data_masked[4];
assign N9 = N8 | data_masked[32];
assign N8 = data_masked[88] | data_masked[60];
assign data_o[5] = N11 | data_masked[5];
assign N11 = N10 | data_masked[33];
assign N10 = data_masked[89] | data_masked[61];
assign data_o[6] = N13 | data_masked[6];
assign N13 = N12 | data_masked[34];
assign N12 = data_masked[90] | data_masked[62];
assign data_o[7] = N15 | data_masked[7];
assign N15 = N14 | data_masked[35];
assign N14 = data_masked[91] | data_masked[63];
assign data_o[8] = N17 | data_masked[8];
assign N17 = N16 | data_masked[36];
assign N16 = data_masked[92] | data_masked[64];
assign data_o[9] = N19 | data_masked[9];
assign N19 = N18 | data_masked[37];
assign N18 = data_masked[93] | data_masked[65];
assign data_o[10] = N21 | data_masked[10];
assign N21 = N20 | data_masked[38];
assign N20 = data_masked[94] | data_masked[66];
assign data_o[11] = N23 | data_masked[11];
assign N23 = N22 | data_masked[39];
assign N22 = data_masked[95] | data_masked[67];
assign data_o[12] = N25 | data_masked[12];
assign N25 = N24 | data_masked[40];
assign N24 = data_masked[96] | data_masked[68];
assign data_o[13] = N27 | data_masked[13];
assign N27 = N26 | data_masked[41];
assign N26 = data_masked[97] | data_masked[69];
assign data_o[14] = N29 | data_masked[14];
assign N29 = N28 | data_masked[42];
assign N28 = data_masked[98] | data_masked[70];
assign data_o[15] = N31 | data_masked[15];
assign N31 = N30 | data_masked[43];
assign N30 = data_masked[99] | data_masked[71];
assign data_o[16] = N33 | data_masked[16];
assign N33 = N32 | data_masked[44];
assign N32 = data_masked[100] | data_masked[72];
assign data_o[17] = N35 | data_masked[17];
assign N35 = N34 | data_masked[45];
assign N34 = data_masked[101] | data_masked[73];
assign data_o[18] = N37 | data_masked[18];
assign N37 = N36 | data_masked[46];
assign N36 = data_masked[102] | data_masked[74];
assign data_o[19] = N39 | data_masked[19];
assign N39 = N38 | data_masked[47];
assign N38 = data_masked[103] | data_masked[75];
assign data_o[20] = N41 | data_masked[20];
assign N41 = N40 | data_masked[48];
assign N40 = data_masked[104] | data_masked[76];
assign data_o[21] = N43 | data_masked[21];
assign N43 = N42 | data_masked[49];
assign N42 = data_masked[105] | data_masked[77];
assign data_o[22] = N45 | data_masked[22];
assign N45 = N44 | data_masked[50];
assign N44 = data_masked[106] | data_masked[78];
assign data_o[23] = N47 | data_masked[23];
assign N47 = N46 | data_masked[51];
assign N46 = data_masked[107] | data_masked[79];
assign data_o[24] = N49 | data_masked[24];
assign N49 = N48 | data_masked[52];
assign N48 = data_masked[108] | data_masked[80];
assign data_o[25] = N51 | data_masked[25];
assign N51 = N50 | data_masked[53];
assign N50 = data_masked[109] | data_masked[81];
assign data_o[26] = N53 | data_masked[26];
assign N53 = N52 | data_masked[54];
assign N52 = data_masked[110] | data_masked[82];
assign data_o[27] = N55 | data_masked[27];
assign N55 = N54 | data_masked[55];
assign N54 = data_masked[111] | data_masked[83];
endmodule
|
module itlb_vaddr_width_p56_paddr_width_p22_eaddr_width_p64_btb_indx_width_p9_bht_indx_width_p5_ras_addr_width_p22_asid_width_p10_ppn_start_bit_p12_tag_width_p10
(
clk_i,
reset_i,
fe_itlb_i,
fe_itlb_v_i,
fe_itlb_ready_o,
pc_gen_itlb_i,
pc_gen_itlb_v_i,
pc_gen_itlb_ready_o,
itlb_icache_o,
itlb_icache_data_resp_v_o,
itlb_icache_data_resp_ready_i,
itlb_fe_o,
itlb_fe_v_o,
itlb_fe_ready_i
);
input [108:0] fe_itlb_i;
input [63:0] pc_gen_itlb_i;
output [9:0] itlb_icache_o;
output [133:0] itlb_fe_o;
input clk_i;
input reset_i;
input fe_itlb_v_i;
input pc_gen_itlb_v_i;
input itlb_icache_data_resp_ready_i;
input itlb_fe_ready_i;
output fe_itlb_ready_o;
output pc_gen_itlb_ready_o;
output itlb_icache_data_resp_v_o;
output itlb_fe_v_o;
wire [133:0] itlb_fe_o;
wire fe_itlb_ready_o,pc_gen_itlb_ready_o,itlb_icache_data_resp_v_o,itlb_fe_v_o;
reg [9:0] itlb_icache_o;
assign pc_gen_itlb_ready_o = 1'b1;
assign itlb_icache_data_resp_v_o = 1'b1;
assign fe_itlb_ready_o = 1'b0;
assign itlb_fe_v_o = 1'b0;
always @(posedge clk_i) begin
if(1'b1) begin
{ itlb_icache_o[9:0] } <= { pc_gen_itlb_i[21:12] };
end
end
endmodule
|
module bsg_mem_1r1w_synth_width_p32_els_p2_read_write_same_addr_p0_harden_p0
(
w_clk_i,
w_reset_i,
w_v_i,
w_addr_i,
w_data_i,
r_v_i,
r_addr_i,
r_data_o
);
input [0:0] w_addr_i;
input [31:0] w_data_i;
input [0:0] r_addr_i;
output [31:0] r_data_o;
input w_clk_i;
input w_reset_i;
input w_v_i;
input r_v_i;
wire [31:0] r_data_o;
wire N0,N1,N2,N3,N4,N5,N7,N8;
reg [63:0] mem;
assign r_data_o[31] = (N3)? mem[31] :
(N0)? mem[63] : 1'b0;
assign N0 = r_addr_i[0];
assign r_data_o[30] = (N3)? mem[30] :
(N0)? mem[62] : 1'b0;
assign r_data_o[29] = (N3)? mem[29] :
(N0)? mem[61] : 1'b0;
assign r_data_o[28] = (N3)? mem[28] :
(N0)? mem[60] : 1'b0;
assign r_data_o[27] = (N3)? mem[27] :
(N0)? mem[59] : 1'b0;
assign r_data_o[26] = (N3)? mem[26] :
(N0)? mem[58] : 1'b0;
assign r_data_o[25] = (N3)? mem[25] :
(N0)? mem[57] : 1'b0;
assign r_data_o[24] = (N3)? mem[24] :
(N0)? mem[56] : 1'b0;
assign r_data_o[23] = (N3)? mem[23] :
(N0)? mem[55] : 1'b0;
assign r_data_o[22] = (N3)? mem[22] :
(N0)? mem[54] : 1'b0;
assign r_data_o[21] = (N3)? mem[21] :
(N0)? mem[53] : 1'b0;
assign r_data_o[20] = (N3)? mem[20] :
(N0)? mem[52] : 1'b0;
assign r_data_o[19] = (N3)? mem[19] :
(N0)? mem[51] : 1'b0;
assign r_data_o[18] = (N3)? mem[18] :
(N0)? mem[50] : 1'b0;
assign r_data_o[17] = (N3)? mem[17] :
(N0)? mem[49] : 1'b0;
assign r_data_o[16] = (N3)? mem[16] :
(N0)? mem[48] : 1'b0;
assign r_data_o[15] = (N3)? mem[15] :
(N0)? mem[47] : 1'b0;
assign r_data_o[14] = (N3)? mem[14] :
(N0)? mem[46] : 1'b0;
assign r_data_o[13] = (N3)? mem[13] :
(N0)? mem[45] : 1'b0;
assign r_data_o[12] = (N3)? mem[12] :
(N0)? mem[44] : 1'b0;
assign r_data_o[11] = (N3)? mem[11] :
(N0)? mem[43] : 1'b0;
assign r_data_o[10] = (N3)? mem[10] :
(N0)? mem[42] : 1'b0;
assign r_data_o[9] = (N3)? mem[9] :
(N0)? mem[41] : 1'b0;
assign r_data_o[8] = (N3)? mem[8] :
(N0)? mem[40] : 1'b0;
assign r_data_o[7] = (N3)? mem[7] :
(N0)? mem[39] : 1'b0;
assign r_data_o[6] = (N3)? mem[6] :
(N0)? mem[38] : 1'b0;
assign r_data_o[5] = (N3)? mem[5] :
(N0)? mem[37] : 1'b0;
assign r_data_o[4] = (N3)? mem[4] :
(N0)? mem[36] : 1'b0;
assign r_data_o[3] = (N3)? mem[3] :
(N0)? mem[35] : 1'b0;
assign r_data_o[2] = (N3)? mem[2] :
(N0)? mem[34] : 1'b0;
assign r_data_o[1] = (N3)? mem[1] :
(N0)? mem[33] : 1'b0;
assign r_data_o[0] = (N3)? mem[0] :
(N0)? mem[32] : 1'b0;
assign N5 = ~w_addr_i[0];
assign { N8, N7 } = (N1)? { w_addr_i[0:0], N5 } :
(N2)? { 1'b0, 1'b0 } : 1'b0;
assign N1 = w_v_i;
assign N2 = N4;
assign N3 = ~r_addr_i[0];
assign N4 = ~w_v_i;
always @(posedge w_clk_i) begin
if(N8) begin
{ mem[63:32] } <= { w_data_i[31:0] };
end
if(N7) begin
{ mem[31:0] } <= { w_data_i[31:0] };
end
end
endmodule
|
module bsg_mem_1r1w_synth_width_p27_els_p2_read_write_same_addr_p0_harden_p0
(
w_clk_i,
w_reset_i,
w_v_i,
w_addr_i,
w_data_i,
r_v_i,
r_addr_i,
r_data_o
);
input [0:0] w_addr_i;
input [26:0] w_data_i;
input [0:0] r_addr_i;
output [26:0] r_data_o;
input w_clk_i;
input w_reset_i;
input w_v_i;
input r_v_i;
wire [26:0] r_data_o;
wire N0,N1,N2,N3,N4,N5,N7,N8;
reg [53:0] mem;
assign r_data_o[26] = (N3)? mem[26] :
(N0)? mem[53] : 1'b0;
assign N0 = r_addr_i[0];
assign r_data_o[25] = (N3)? mem[25] :
(N0)? mem[52] : 1'b0;
assign r_data_o[24] = (N3)? mem[24] :
(N0)? mem[51] : 1'b0;
assign r_data_o[23] = (N3)? mem[23] :
(N0)? mem[50] : 1'b0;
assign r_data_o[22] = (N3)? mem[22] :
(N0)? mem[49] : 1'b0;
assign r_data_o[21] = (N3)? mem[21] :
(N0)? mem[48] : 1'b0;
assign r_data_o[20] = (N3)? mem[20] :
(N0)? mem[47] : 1'b0;
assign r_data_o[19] = (N3)? mem[19] :
(N0)? mem[46] : 1'b0;
assign r_data_o[18] = (N3)? mem[18] :
(N0)? mem[45] : 1'b0;
assign r_data_o[17] = (N3)? mem[17] :
(N0)? mem[44] : 1'b0;
assign r_data_o[16] = (N3)? mem[16] :
(N0)? mem[43] : 1'b0;
assign r_data_o[15] = (N3)? mem[15] :
(N0)? mem[42] : 1'b0;
assign r_data_o[14] = (N3)? mem[14] :
(N0)? mem[41] : 1'b0;
assign r_data_o[13] = (N3)? mem[13] :
(N0)? mem[40] : 1'b0;
assign r_data_o[12] = (N3)? mem[12] :
(N0)? mem[39] : 1'b0;
assign r_data_o[11] = (N3)? mem[11] :
(N0)? mem[38] : 1'b0;
assign r_data_o[10] = (N3)? mem[10] :
(N0)? mem[37] : 1'b0;
assign r_data_o[9] = (N3)? mem[9] :
(N0)? mem[36] : 1'b0;
assign r_data_o[8] = (N3)? mem[8] :
(N0)? mem[35] : 1'b0;
assign r_data_o[7] = (N3)? mem[7] :
(N0)? mem[34] : 1'b0;
assign r_data_o[6] = (N3)? mem[6] :
(N0)? mem[33] : 1'b0;
assign r_data_o[5] = (N3)? mem[5] :
(N0)? mem[32] : 1'b0;
assign r_data_o[4] = (N3)? mem[4] :
(N0)? mem[31] : 1'b0;
assign r_data_o[3] = (N3)? mem[3] :
(N0)? mem[30] : 1'b0;
assign r_data_o[2] = (N3)? mem[2] :
(N0)? mem[29] : 1'b0;
assign r_data_o[1] = (N3)? mem[1] :
(N0)? mem[28] : 1'b0;
assign r_data_o[0] = (N3)? mem[0] :
(N0)? mem[27] : 1'b0;
assign N5 = ~w_addr_i[0];
assign { N8, N7 } = (N1)? { w_addr_i[0:0], N5 } :
(N2)? { 1'b0, 1'b0 } : 1'b0;
assign N1 = w_v_i;
assign N2 = N4;
assign N3 = ~r_addr_i[0];
assign N4 = ~w_v_i;
always @(posedge w_clk_i) begin
if(N8) begin
{ mem[53:27] } <= { w_data_i[26:0] };
end
if(N7) begin
{ mem[26:0] } <= { w_data_i[26:0] };
end
end
endmodule
|
module bsg_mux_one_hot_width_p32_els_p5
(
data_i,
sel_one_hot_i,
data_o
);
input [159:0] data_i;
input [4:0] sel_one_hot_i;
output [31:0] data_o;
wire [31:0] data_o;
wire N0,N1,N2,N3,N4,N5,N6,N7,N8,N9,N10,N11,N12,N13,N14,N15,N16,N17,N18,N19,N20,N21,
N22,N23,N24,N25,N26,N27,N28,N29,N30,N31,N32,N33,N34,N35,N36,N37,N38,N39,N40,N41,
N42,N43,N44,N45,N46,N47,N48,N49,N50,N51,N52,N53,N54,N55,N56,N57,N58,N59,N60,N61,
N62,N63,N64,N65,N66,N67,N68,N69,N70,N71,N72,N73,N74,N75,N76,N77,N78,N79,N80,N81,
N82,N83,N84,N85,N86,N87,N88,N89,N90,N91,N92,N93,N94,N95;
wire [159:0] data_masked;
assign data_masked[31] = data_i[31] & sel_one_hot_i[0];
assign data_masked[30] = data_i[30] & sel_one_hot_i[0];
assign data_masked[29] = data_i[29] & sel_one_hot_i[0];
assign data_masked[28] = data_i[28] & sel_one_hot_i[0];
assign data_masked[27] = data_i[27] & sel_one_hot_i[0];
assign data_masked[26] = data_i[26] & sel_one_hot_i[0];
assign data_masked[25] = data_i[25] & sel_one_hot_i[0];
assign data_masked[24] = data_i[24] & sel_one_hot_i[0];
assign data_masked[23] = data_i[23] & sel_one_hot_i[0];
assign data_masked[22] = data_i[22] & sel_one_hot_i[0];
assign data_masked[21] = data_i[21] & sel_one_hot_i[0];
assign data_masked[20] = data_i[20] & sel_one_hot_i[0];
assign data_masked[19] = data_i[19] & sel_one_hot_i[0];
assign data_masked[18] = data_i[18] & sel_one_hot_i[0];
assign data_masked[17] = data_i[17] & sel_one_hot_i[0];
assign data_masked[16] = data_i[16] & sel_one_hot_i[0];
assign data_masked[15] = data_i[15] & sel_one_hot_i[0];
assign data_masked[14] = data_i[14] & sel_one_hot_i[0];
assign data_masked[13] = data_i[13] & sel_one_hot_i[0];
assign data_masked[12] = data_i[12] & sel_one_hot_i[0];
assign data_masked[11] = data_i[11] & sel_one_hot_i[0];
assign data_masked[10] = data_i[10] & sel_one_hot_i[0];
assign data_masked[9] = data_i[9] & sel_one_hot_i[0];
assign data_masked[8] = data_i[8] & sel_one_hot_i[0];
assign data_masked[7] = data_i[7] & sel_one_hot_i[0];
assign data_masked[6] = data_i[6] & sel_one_hot_i[0];
assign data_masked[5] = data_i[5] & sel_one_hot_i[0];
assign data_masked[4] = data_i[4] & sel_one_hot_i[0];
assign data_masked[3] = data_i[3] & sel_one_hot_i[0];
assign data_masked[2] = data_i[2] & sel_one_hot_i[0];
assign data_masked[1] = data_i[1] & sel_one_hot_i[0];
assign data_masked[0] = data_i[0] & sel_one_hot_i[0];
assign data_masked[63] = data_i[63] & sel_one_hot_i[1];
assign data_masked[62] = data_i[62] & sel_one_hot_i[1];
assign data_masked[61] = data_i[61] & sel_one_hot_i[1];
assign data_masked[60] = data_i[60] & sel_one_hot_i[1];
assign data_masked[59] = data_i[59] & sel_one_hot_i[1];
assign data_masked[58] = data_i[58] & sel_one_hot_i[1];
assign data_masked[57] = data_i[57] & sel_one_hot_i[1];
assign data_masked[56] = data_i[56] & sel_one_hot_i[1];
assign data_masked[55] = data_i[55] & sel_one_hot_i[1];
assign data_masked[54] = data_i[54] & sel_one_hot_i[1];
assign data_masked[53] = data_i[53] & sel_one_hot_i[1];
assign data_masked[52] = data_i[52] & sel_one_hot_i[1];
assign data_masked[51] = data_i[51] & sel_one_hot_i[1];
assign data_masked[50] = data_i[50] & sel_one_hot_i[1];
assign data_masked[49] = data_i[49] & sel_one_hot_i[1];
assign data_masked[48] = data_i[48] & sel_one_hot_i[1];
assign data_masked[47] = data_i[47] & sel_one_hot_i[1];
assign data_masked[46] = data_i[46] & sel_one_hot_i[1];
assign data_masked[45] = data_i[45] & sel_one_hot_i[1];
assign data_masked[44] = data_i[44] & sel_one_hot_i[1];
assign data_masked[43] = data_i[43] & sel_one_hot_i[1];
assign data_masked[42] = data_i[42] & sel_one_hot_i[1];
assign data_masked[41] = data_i[41] & sel_one_hot_i[1];
assign data_masked[40] = data_i[40] & sel_one_hot_i[1];
assign data_masked[39] = data_i[39] & sel_one_hot_i[1];
assign data_masked[38] = data_i[38] & sel_one_hot_i[1];
assign data_masked[37] = data_i[37] & sel_one_hot_i[1];
assign data_masked[36] = data_i[36] & sel_one_hot_i[1];
assign data_masked[35] = data_i[35] & sel_one_hot_i[1];
assign data_masked[34] = data_i[34] & sel_one_hot_i[1];
assign data_masked[33] = data_i[33] & sel_one_hot_i[1];
assign data_masked[32] = data_i[32] & sel_one_hot_i[1];
assign data_masked[95] = data_i[95] & sel_one_hot_i[2];
assign data_masked[94] = data_i[94] & sel_one_hot_i[2];
assign data_masked[93] = data_i[93] & sel_one_hot_i[2];
assign data_masked[92] = data_i[92] & sel_one_hot_i[2];
assign data_masked[91] = data_i[91] & sel_one_hot_i[2];
assign data_masked[90] = data_i[90] & sel_one_hot_i[2];
assign data_masked[89] = data_i[89] & sel_one_hot_i[2];
assign data_masked[88] = data_i[88] & sel_one_hot_i[2];
assign data_masked[87] = data_i[87] & sel_one_hot_i[2];
assign data_masked[86] = data_i[86] & sel_one_hot_i[2];
assign data_masked[85] = data_i[85] & sel_one_hot_i[2];
assign data_masked[84] = data_i[84] & sel_one_hot_i[2];
assign data_masked[83] = data_i[83] & sel_one_hot_i[2];
assign data_masked[82] = data_i[82] & sel_one_hot_i[2];
assign data_masked[81] = data_i[81] & sel_one_hot_i[2];
assign data_masked[80] = data_i[80] & sel_one_hot_i[2];
assign data_masked[79] = data_i[79] & sel_one_hot_i[2];
assign data_masked[78] = data_i[78] & sel_one_hot_i[2];
assign data_masked[77] = data_i[77] & sel_one_hot_i[2];
assign data_masked[76] = data_i[76] & sel_one_hot_i[2];
assign data_masked[75] = data_i[75] & sel_one_hot_i[2];
assign data_masked[74] = data_i[74] & sel_one_hot_i[2];
assign data_masked[73] = data_i[73] & sel_one_hot_i[2];
assign data_masked[72] = data_i[72] & sel_one_hot_i[2];
assign data_masked[71] = data_i[71] & sel_one_hot_i[2];
assign data_masked[70] = data_i[70] & sel_one_hot_i[2];
assign data_masked[69] = data_i[69] & sel_one_hot_i[2];
assign data_masked[68] = data_i[68] & sel_one_hot_i[2];
assign data_masked[67] = data_i[67] & sel_one_hot_i[2];
assign data_masked[66] = data_i[66] & sel_one_hot_i[2];
assign data_masked[65] = data_i[65] & sel_one_hot_i[2];
assign data_masked[64] = data_i[64] & sel_one_hot_i[2];
assign data_masked[127] = data_i[127] & sel_one_hot_i[3];
assign data_masked[126] = data_i[126] & sel_one_hot_i[3];
assign data_masked[125] = data_i[125] & sel_one_hot_i[3];
assign data_masked[124] = data_i[124] & sel_one_hot_i[3];
assign data_masked[123] = data_i[123] & sel_one_hot_i[3];
assign data_masked[122] = data_i[122] & sel_one_hot_i[3];
assign data_masked[121] = data_i[121] & sel_one_hot_i[3];
assign data_masked[120] = data_i[120] & sel_one_hot_i[3];
assign data_masked[119] = data_i[119] & sel_one_hot_i[3];
assign data_masked[118] = data_i[118] & sel_one_hot_i[3];
assign data_masked[117] = data_i[117] & sel_one_hot_i[3];
assign data_masked[116] = data_i[116] & sel_one_hot_i[3];
assign data_masked[115] = data_i[115] & sel_one_hot_i[3];
assign data_masked[114] = data_i[114] & sel_one_hot_i[3];
assign data_masked[113] = data_i[113] & sel_one_hot_i[3];
assign data_masked[112] = data_i[112] & sel_one_hot_i[3];
assign data_masked[111] = data_i[111] & sel_one_hot_i[3];
assign data_masked[110] = data_i[110] & sel_one_hot_i[3];
assign data_masked[109] = data_i[109] & sel_one_hot_i[3];
assign data_masked[108] = data_i[108] & sel_one_hot_i[3];
assign data_masked[107] = data_i[107] & sel_one_hot_i[3];
assign data_masked[106] = data_i[106] & sel_one_hot_i[3];
assign data_masked[105] = data_i[105] & sel_one_hot_i[3];
assign data_masked[104] = data_i[104] & sel_one_hot_i[3];
assign data_masked[103] = data_i[103] & sel_one_hot_i[3];
assign data_masked[102] = data_i[102] & sel_one_hot_i[3];
assign data_masked[101] = data_i[101] & sel_one_hot_i[3];
assign data_masked[100] = data_i[100] & sel_one_hot_i[3];
assign data_masked[99] = data_i[99] & sel_one_hot_i[3];
assign data_masked[98] = data_i[98] & sel_one_hot_i[3];
assign data_masked[97] = data_i[97] & sel_one_hot_i[3];
assign data_masked[96] = data_i[96] & sel_one_hot_i[3];
assign data_masked[159] = data_i[159] & sel_one_hot_i[4];
assign data_masked[158] = data_i[158] & sel_one_hot_i[4];
assign data_masked[157] = data_i[157] & sel_one_hot_i[4];
assign data_masked[156] = data_i[156] & sel_one_hot_i[4];
assign data_masked[155] = data_i[155] & sel_one_hot_i[4];
assign data_masked[154] = data_i[154] & sel_one_hot_i[4];
assign data_masked[153] = data_i[153] & sel_one_hot_i[4];
assign data_masked[152] = data_i[152] & sel_one_hot_i[4];
assign data_masked[151] = data_i[151] & sel_one_hot_i[4];
assign data_masked[150] = data_i[150] & sel_one_hot_i[4];
assign data_masked[149] = data_i[149] & sel_one_hot_i[4];
assign data_masked[148] = data_i[148] & sel_one_hot_i[4];
assign data_masked[147] = data_i[147] & sel_one_hot_i[4];
assign data_masked[146] = data_i[146] & sel_one_hot_i[4];
assign data_masked[145] = data_i[145] & sel_one_hot_i[4];
assign data_masked[144] = data_i[144] & sel_one_hot_i[4];
assign data_masked[143] = data_i[143] & sel_one_hot_i[4];
assign data_masked[142] = data_i[142] & sel_one_hot_i[4];
assign data_masked[141] = data_i[141] & sel_one_hot_i[4];
assign data_masked[140] = data_i[140] & sel_one_hot_i[4];
assign data_masked[139] = data_i[139] & sel_one_hot_i[4];
assign data_masked[138] = data_i[138] & sel_one_hot_i[4];
assign data_masked[137] = data_i[137] & sel_one_hot_i[4];
assign data_masked[136] = data_i[136] & sel_one_hot_i[4];
assign data_masked[135] = data_i[135] & sel_one_hot_i[4];
assign data_masked[134] = data_i[134] & sel_one_hot_i[4];
assign data_masked[133] = data_i[133] & sel_one_hot_i[4];
assign data_masked[132] = data_i[132] & sel_one_hot_i[4];
assign data_masked[131] = data_i[131] & sel_one_hot_i[4];
assign data_masked[130] = data_i[130] & sel_one_hot_i[4];
assign data_masked[129] = data_i[129] & sel_one_hot_i[4];
assign data_masked[128] = data_i[128] & sel_one_hot_i[4];
assign data_o[0] = N2 | data_masked[0];
assign N2 = N1 | data_masked[32];
assign N1 = N0 | data_masked[64];
assign N0 = data_masked[128] | data_masked[96];
assign data_o[1] = N5 | data_masked[1];
assign N5 = N4 | data_masked[33];
assign N4 = N3 | data_masked[65];
assign N3 = data_masked[129] | data_masked[97];
assign data_o[2] = N8 | data_masked[2];
assign N8 = N7 | data_masked[34];
assign N7 = N6 | data_masked[66];
assign N6 = data_masked[130] | data_masked[98];
assign data_o[3] = N11 | data_masked[3];
assign N11 = N10 | data_masked[35];
assign N10 = N9 | data_masked[67];
assign N9 = data_masked[131] | data_masked[99];
assign data_o[4] = N14 | data_masked[4];
assign N14 = N13 | data_masked[36];
assign N13 = N12 | data_masked[68];
assign N12 = data_masked[132] | data_masked[100];
assign data_o[5] = N17 | data_masked[5];
assign N17 = N16 | data_masked[37];
assign N16 = N15 | data_masked[69];
assign N15 = data_masked[133] | data_masked[101];
assign data_o[6] = N20 | data_masked[6];
assign N20 = N19 | data_masked[38];
assign N19 = N18 | data_masked[70];
assign N18 = data_masked[134] | data_masked[102];
assign data_o[7] = N23 | data_masked[7];
assign N23 = N22 | data_masked[39];
assign N22 = N21 | data_masked[71];
assign N21 = data_masked[135] | data_masked[103];
assign data_o[8] = N26 | data_masked[8];
assign N26 = N25 | data_masked[40];
assign N25 = N24 | data_masked[72];
assign N24 = data_masked[136] | data_masked[104];
assign data_o[9] = N29 | data_masked[9];
assign N29 = N28 | data_masked[41];
assign N28 = N27 | data_masked[73];
assign N27 = data_masked[137] | data_masked[105];
assign data_o[10] = N32 | data_masked[10];
assign N32 = N31 | data_masked[42];
assign N31 = N30 | data_masked[74];
assign N30 = data_masked[138] | data_masked[106];
assign data_o[11] = N35 | data_masked[11];
assign N35 = N34 | data_masked[43];
assign N34 = N33 | data_masked[75];
assign N33 = data_masked[139] | data_masked[107];
assign data_o[12] = N38 | data_masked[12];
assign N38 = N37 | data_masked[44];
assign N37 = N36 | data_masked[76];
assign N36 = data_masked[140] | data_masked[108];
assign data_o[13] = N41 | data_masked[13];
assign N41 = N40 | data_masked[45];
assign N40 = N39 | data_masked[77];
assign N39 = data_masked[141] | data_masked[109];
assign data_o[14] = N44 | data_masked[14];
assign N44 = N43 | data_masked[46];
assign N43 = N42 | data_masked[78];
assign N42 = data_masked[142] | data_masked[110];
assign data_o[15] = N47 | data_masked[15];
assign N47 = N46 | data_masked[47];
assign N46 = N45 | data_masked[79];
assign N45 = data_masked[143] | data_masked[111];
assign data_o[16] = N50 | data_masked[16];
assign N50 = N49 | data_masked[48];
assign N49 = N48 | data_masked[80];
assign N48 = data_masked[144] | data_masked[112];
assign data_o[17] = N53 | data_masked[17];
assign N53 = N52 | data_masked[49];
assign N52 = N51 | data_masked[81];
assign N51 = data_masked[145] | data_masked[113];
assign data_o[18] = N56 | data_masked[18];
assign N56 = N55 | data_masked[50];
assign N55 = N54 | data_masked[82];
assign N54 = data_masked[146] | data_masked[114];
assign data_o[19] = N59 | data_masked[19];
assign N59 = N58 | data_masked[51];
assign N58 = N57 | data_masked[83];
assign N57 = data_masked[147] | data_masked[115];
assign data_o[20] = N62 | data_masked[20];
assign N62 = N61 | data_masked[52];
assign N61 = N60 | data_masked[84];
assign N60 = data_masked[148] | data_masked[116];
assign data_o[21] = N65 | data_masked[21];
assign N65 = N64 | data_masked[53];
assign N64 = N63 | data_masked[85];
assign N63 = data_masked[149] | data_masked[117];
assign data_o[22] = N68 | data_masked[22];
assign N68 = N67 | data_masked[54];
assign N67 = N66 | data_masked[86];
assign N66 = data_masked[150] | data_masked[118];
assign data_o[23] = N71 | data_masked[23];
assign N71 = N70 | data_masked[55];
assign N70 = N69 | data_masked[87];
assign N69 = data_masked[151] | data_masked[119];
assign data_o[24] = N74 | data_masked[24];
assign N74 = N73 | data_masked[56];
assign N73 = N72 | data_masked[88];
assign N72 = data_masked[152] | data_masked[120];
assign data_o[25] = N77 | data_masked[25];
assign N77 = N76 | data_masked[57];
assign N76 = N75 | data_masked[89];
assign N75 = data_masked[153] | data_masked[121];
assign data_o[26] = N80 | data_masked[26];
assign N80 = N79 | data_masked[58];
assign N79 = N78 | data_masked[90];
assign N78 = data_masked[154] | data_masked[122];
assign data_o[27] = N83 | data_masked[27];
assign N83 = N82 | data_masked[59];
assign N82 = N81 | data_masked[91];
assign N81 = data_masked[155] | data_masked[123];
assign data_o[28] = N86 | data_masked[28];
assign N86 = N85 | data_masked[60];
assign N85 = N84 | data_masked[92];
assign N84 = data_masked[156] | data_masked[124];
assign data_o[29] = N89 | data_masked[29];
assign N89 = N88 | data_masked[61];
assign N88 = N87 | data_masked[93];
assign N87 = data_masked[157] | data_masked[125];
assign data_o[30] = N92 | data_masked[30];
assign N92 = N91 | data_masked[62];
assign N91 = N90 | data_masked[94];
assign N90 = data_masked[158] | data_masked[126];
assign data_o[31] = N95 | data_masked[31];
assign N95 = N94 | data_masked[63];
assign N94 = N93 | data_masked[95];
assign N93 = data_masked[159] | data_masked[127];
endmodule
|
module bsg_dff_reset_en_width_p8
(
clk_i,
reset_i,
en_i,
data_i,
data_o
);
input [7:0] data_i;
output [7:0] data_o;
input clk_i;
input reset_i;
input en_i;
wire N0,N1,N2,N3,N4,N5,N6,N7,N8,N9,N10,N11,N12,N13;
reg [7:0] data_o;
assign N3 = (N0)? 1'b1 :
(N13)? 1'b1 :
(N2)? 1'b0 : 1'b0;
assign N0 = reset_i;
assign { N11, N10, N9, N8, N7, N6, N5, N4 } = (N0)? { 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0 } :
(N13)? data_i : 1'b0;
assign N1 = en_i | reset_i;
assign N2 = ~N1;
assign N12 = ~reset_i;
assign N13 = en_i & N12;
always @(posedge clk_i) begin
if(N3) begin
{ data_o[7:0] } <= { N11, N10, N9, N8, N7, N6, N5, N4 };
end
end
endmodule
|
module bsg_mem_1r1w_synth_width_p36_els_p2_read_write_same_addr_p0_harden_p0
(
w_clk_i,
w_reset_i,
w_v_i,
w_addr_i,
w_data_i,
r_v_i,
r_addr_i,
r_data_o
);
input [0:0] w_addr_i;
input [35:0] w_data_i;
input [0:0] r_addr_i;
output [35:0] r_data_o;
input w_clk_i;
input w_reset_i;
input w_v_i;
input r_v_i;
wire [35:0] r_data_o;
wire N0,N1,N2,N3,N4,N5,N7,N8;
reg [71:0] mem;
assign r_data_o[35] = (N3)? mem[35] :
(N0)? mem[71] : 1'b0;
assign N0 = r_addr_i[0];
assign r_data_o[34] = (N3)? mem[34] :
(N0)? mem[70] : 1'b0;
assign r_data_o[33] = (N3)? mem[33] :
(N0)? mem[69] : 1'b0;
assign r_data_o[32] = (N3)? mem[32] :
(N0)? mem[68] : 1'b0;
assign r_data_o[31] = (N3)? mem[31] :
(N0)? mem[67] : 1'b0;
assign r_data_o[30] = (N3)? mem[30] :
(N0)? mem[66] : 1'b0;
assign r_data_o[29] = (N3)? mem[29] :
(N0)? mem[65] : 1'b0;
assign r_data_o[28] = (N3)? mem[28] :
(N0)? mem[64] : 1'b0;
assign r_data_o[27] = (N3)? mem[27] :
(N0)? mem[63] : 1'b0;
assign r_data_o[26] = (N3)? mem[26] :
(N0)? mem[62] : 1'b0;
assign r_data_o[25] = (N3)? mem[25] :
(N0)? mem[61] : 1'b0;
assign r_data_o[24] = (N3)? mem[24] :
(N0)? mem[60] : 1'b0;
assign r_data_o[23] = (N3)? mem[23] :
(N0)? mem[59] : 1'b0;
assign r_data_o[22] = (N3)? mem[22] :
(N0)? mem[58] : 1'b0;
assign r_data_o[21] = (N3)? mem[21] :
(N0)? mem[57] : 1'b0;
assign r_data_o[20] = (N3)? mem[20] :
(N0)? mem[56] : 1'b0;
assign r_data_o[19] = (N3)? mem[19] :
(N0)? mem[55] : 1'b0;
assign r_data_o[18] = (N3)? mem[18] :
(N0)? mem[54] : 1'b0;
assign r_data_o[17] = (N3)? mem[17] :
(N0)? mem[53] : 1'b0;
assign r_data_o[16] = (N3)? mem[16] :
(N0)? mem[52] : 1'b0;
assign r_data_o[15] = (N3)? mem[15] :
(N0)? mem[51] : 1'b0;
assign r_data_o[14] = (N3)? mem[14] :
(N0)? mem[50] : 1'b0;
assign r_data_o[13] = (N3)? mem[13] :
(N0)? mem[49] : 1'b0;
assign r_data_o[12] = (N3)? mem[12] :
(N0)? mem[48] : 1'b0;
assign r_data_o[11] = (N3)? mem[11] :
(N0)? mem[47] : 1'b0;
assign r_data_o[10] = (N3)? mem[10] :
(N0)? mem[46] : 1'b0;
assign r_data_o[9] = (N3)? mem[9] :
(N0)? mem[45] : 1'b0;
assign r_data_o[8] = (N3)? mem[8] :
(N0)? mem[44] : 1'b0;
assign r_data_o[7] = (N3)? mem[7] :
(N0)? mem[43] : 1'b0;
assign r_data_o[6] = (N3)? mem[6] :
(N0)? mem[42] : 1'b0;
assign r_data_o[5] = (N3)? mem[5] :
(N0)? mem[41] : 1'b0;
assign r_data_o[4] = (N3)? mem[4] :
(N0)? mem[40] : 1'b0;
assign r_data_o[3] = (N3)? mem[3] :
(N0)? mem[39] : 1'b0;
assign r_data_o[2] = (N3)? mem[2] :
(N0)? mem[38] : 1'b0;
assign r_data_o[1] = (N3)? mem[1] :
(N0)? mem[37] : 1'b0;
assign r_data_o[0] = (N3)? mem[0] :
(N0)? mem[36] : 1'b0;
assign N5 = ~w_addr_i[0];
assign { N8, N7 } = (N1)? { w_addr_i[0:0], N5 } :
(N2)? { 1'b0, 1'b0 } : 1'b0;
assign N1 = w_v_i;
assign N2 = N4;
assign N3 = ~r_addr_i[0];
assign N4 = ~w_v_i;
always @(posedge w_clk_i) begin
if(N8) begin
{ mem[71:36] } <= { w_data_i[35:0] };
end
if(N7) begin
{ mem[35:0] } <= { w_data_i[35:0] };
end
end
endmodule
|
module bsg_mux_width_p64_els_p2
(
data_i,
sel_i,
data_o
);
input [127:0] data_i;
input [0:0] sel_i;
output [63:0] data_o;
wire [63:0] data_o;
wire N0,N1;
assign data_o[63] = (N1)? data_i[63] :
(N0)? data_i[127] : 1'b0;
assign N0 = sel_i[0];
assign data_o[62] = (N1)? data_i[62] :
(N0)? data_i[126] : 1'b0;
assign data_o[61] = (N1)? data_i[61] :
(N0)? data_i[125] : 1'b0;
assign data_o[60] = (N1)? data_i[60] :
(N0)? data_i[124] : 1'b0;
assign data_o[59] = (N1)? data_i[59] :
(N0)? data_i[123] : 1'b0;
assign data_o[58] = (N1)? data_i[58] :
(N0)? data_i[122] : 1'b0;
assign data_o[57] = (N1)? data_i[57] :
(N0)? data_i[121] : 1'b0;
assign data_o[56] = (N1)? data_i[56] :
(N0)? data_i[120] : 1'b0;
assign data_o[55] = (N1)? data_i[55] :
(N0)? data_i[119] : 1'b0;
assign data_o[54] = (N1)? data_i[54] :
(N0)? data_i[118] : 1'b0;
assign data_o[53] = (N1)? data_i[53] :
(N0)? data_i[117] : 1'b0;
assign data_o[52] = (N1)? data_i[52] :
(N0)? data_i[116] : 1'b0;
assign data_o[51] = (N1)? data_i[51] :
(N0)? data_i[115] : 1'b0;
assign data_o[50] = (N1)? data_i[50] :
(N0)? data_i[114] : 1'b0;
assign data_o[49] = (N1)? data_i[49] :
(N0)? data_i[113] : 1'b0;
assign data_o[48] = (N1)? data_i[48] :
(N0)? data_i[112] : 1'b0;
assign data_o[47] = (N1)? data_i[47] :
(N0)? data_i[111] : 1'b0;
assign data_o[46] = (N1)? data_i[46] :
(N0)? data_i[110] : 1'b0;
assign data_o[45] = (N1)? data_i[45] :
(N0)? data_i[109] : 1'b0;
assign data_o[44] = (N1)? data_i[44] :
(N0)? data_i[108] : 1'b0;
assign data_o[43] = (N1)? data_i[43] :
(N0)? data_i[107] : 1'b0;
assign data_o[42] = (N1)? data_i[42] :
(N0)? data_i[106] : 1'b0;
assign data_o[41] = (N1)? data_i[41] :
(N0)? data_i[105] : 1'b0;
assign data_o[40] = (N1)? data_i[40] :
(N0)? data_i[104] : 1'b0;
assign data_o[39] = (N1)? data_i[39] :
(N0)? data_i[103] : 1'b0;
assign data_o[38] = (N1)? data_i[38] :
(N0)? data_i[102] : 1'b0;
assign data_o[37] = (N1)? data_i[37] :
(N0)? data_i[101] : 1'b0;
assign data_o[36] = (N1)? data_i[36] :
(N0)? data_i[100] : 1'b0;
assign data_o[35] = (N1)? data_i[35] :
(N0)? data_i[99] : 1'b0;
assign data_o[34] = (N1)? data_i[34] :
(N0)? data_i[98] : 1'b0;
assign data_o[33] = (N1)? data_i[33] :
(N0)? data_i[97] : 1'b0;
assign data_o[32] = (N1)? data_i[32] :
(N0)? data_i[96] : 1'b0;
assign data_o[31] = (N1)? data_i[31] :
(N0)? data_i[95] : 1'b0;
assign data_o[30] = (N1)? data_i[30] :
(N0)? data_i[94] : 1'b0;
assign data_o[29] = (N1)? data_i[29] :
(N0)? data_i[93] : 1'b0;
assign data_o[28] = (N1)? data_i[28] :
(N0)? data_i[92] : 1'b0;
assign data_o[27] = (N1)? data_i[27] :
(N0)? data_i[91] : 1'b0;
assign data_o[26] = (N1)? data_i[26] :
(N0)? data_i[90] : 1'b0;
assign data_o[25] = (N1)? data_i[25] :
(N0)? data_i[89] : 1'b0;
assign data_o[24] = (N1)? data_i[24] :
(N0)? data_i[88] : 1'b0;
assign data_o[23] = (N1)? data_i[23] :
(N0)? data_i[87] : 1'b0;
assign data_o[22] = (N1)? data_i[22] :
(N0)? data_i[86] : 1'b0;
assign data_o[21] = (N1)? data_i[21] :
(N0)? data_i[85] : 1'b0;
assign data_o[20] = (N1)? data_i[20] :
(N0)? data_i[84] : 1'b0;
assign data_o[19] = (N1)? data_i[19] :
(N0)? data_i[83] : 1'b0;
assign data_o[18] = (N1)? data_i[18] :
(N0)? data_i[82] : 1'b0;
assign data_o[17] = (N1)? data_i[17] :
(N0)? data_i[81] : 1'b0;
assign data_o[16] = (N1)? data_i[16] :
(N0)? data_i[80] : 1'b0;
assign data_o[15] = (N1)? data_i[15] :
(N0)? data_i[79] : 1'b0;
assign data_o[14] = (N1)? data_i[14] :
(N0)? data_i[78] : 1'b0;
assign data_o[13] = (N1)? data_i[13] :
(N0)? data_i[77] : 1'b0;
assign data_o[12] = (N1)? data_i[12] :
(N0)? data_i[76] : 1'b0;
assign data_o[11] = (N1)? data_i[11] :
(N0)? data_i[75] : 1'b0;
assign data_o[10] = (N1)? data_i[10] :
(N0)? data_i[74] : 1'b0;
assign data_o[9] = (N1)? data_i[9] :
(N0)? data_i[73] : 1'b0;
assign data_o[8] = (N1)? data_i[8] :
(N0)? data_i[72] : 1'b0;
assign data_o[7] = (N1)? data_i[7] :
(N0)? data_i[71] : 1'b0;
assign data_o[6] = (N1)? data_i[6] :
(N0)? data_i[70] : 1'b0;
assign data_o[5] = (N1)? data_i[5] :
(N0)? data_i[69] : 1'b0;
assign data_o[4] = (N1)? data_i[4] :
(N0)? data_i[68] : 1'b0;
assign data_o[3] = (N1)? data_i[3] :
(N0)? data_i[67] : 1'b0;
assign data_o[2] = (N1)? data_i[2] :
(N0)? data_i[66] : 1'b0;
assign data_o[1] = (N1)? data_i[1] :
(N0)? data_i[65] : 1'b0;
assign data_o[0] = (N1)? data_i[0] :
(N0)? data_i[64] : 1'b0;
assign N1 = ~sel_i[0];
endmodule
|
module instr_scan_eaddr_width_p64_instr_width_p32
(
instr_i,
scan_o
);
input [31:0] instr_i;
output [68:0] scan_o;
wire [68:0] scan_o;
wire N0,N1,N2,N3,N4,N5,N6,N7,N9,N10,N11,N12,N13,N14,N15,N16,N17,N18,N19,N20,N21,N22,
N23,N24,N25,N26,N27,N28,N29,N30;
assign scan_o[66] = 1'b0;
assign scan_o[67] = 1'b0;
assign N7 = instr_i[0] & instr_i[1];
assign scan_o[68] = ~N7;
assign N9 = ~instr_i[6];
assign N10 = ~instr_i[5];
assign N11 = ~instr_i[3];
assign N12 = ~instr_i[2];
assign N13 = ~instr_i[1];
assign N14 = ~instr_i[0];
assign N15 = N10 | N9;
assign N16 = instr_i[4] | N15;
assign N17 = N11 | N16;
assign N18 = N12 | N17;
assign N19 = N13 | N18;
assign N20 = N14 | N19;
assign N21 = ~N20;
assign N22 = instr_i[3] | N16;
assign N23 = N12 | N22;
assign N24 = N13 | N23;
assign N25 = N14 | N24;
assign N26 = ~N25;
assign N27 = instr_i[2] | N22;
assign N28 = N13 | N27;
assign N29 = N14 | N28;
assign N30 = ~N29;
assign scan_o[65:64] = (N0)? { 1'b0, 1'b0 } :
(N1)? { 1'b0, 1'b1 } :
(N4)? { 1'b1, N20 } : 1'b0;
assign N0 = N30;
assign N1 = N26;
assign scan_o[63:0] = (N0)? { instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[7:7], instr_i[30:25], instr_i[11:8], 1'b0 } :
(N1)? { instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:20] } :
(N2)? { instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[19:12], instr_i[20:20], instr_i[30:21], 1'b0 } :
(N6)? { 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0 } : 1'b0;
assign N2 = N21;
assign N3 = N26 | N30;
assign N4 = ~N3;
assign N5 = N21 | N3;
assign N6 = ~N5;
endmodule
|
module bsg_mesh_router_dor_decoder_x_cord_width_p1_y_cord_width_p1_dirs_lp5_XY_order_p0
(
clk_i,
v_i,
x_dirs_i,
y_dirs_i,
my_x_i,
my_y_i,
req_o
);
input [4:0] v_i;
input [4:0] x_dirs_i;
input [4:0] y_dirs_i;
input [0:0] my_x_i;
input [0:0] my_y_i;
output [24:0] req_o;
input clk_i;
wire [24:0] req_o;
wire N0,N1,N2,N3,N4,N5,N6,N7,N8,N9,N10,N11,N12,N13,N14,N15,N16,N17,y_gt_0,x_lt_0,
y_lt_0,N18,N19,N20,N21,N22,N23,N24,N25,N26,N27,N28,N29,N30,N31,N32,N33,N34,N35,N36,
N37,N38,N39,N40,N41,N42;
wire [4:0] x_eq,y_eq,x_gt;
wire [4:3] y_gt;
wire [4:2] x_lt;
wire [4:4] y_lt;
assign req_o[12] = 1'b0;
assign req_o[6] = 1'b0;
assign req_o[24] = 1'b0;
assign req_o[18] = 1'b0;
assign req_o[14] = 1'b0;
assign req_o[13] = 1'b0;
assign req_o[9] = 1'b0;
assign req_o[8] = 1'b0;
assign N0 = x_dirs_i[0] ^ my_x_i[0];
assign x_eq[0] = ~N0;
assign N1 = y_dirs_i[0] ^ my_y_i[0];
assign y_eq[0] = ~N1;
assign x_gt[0] = x_dirs_i[0] & N2;
assign N2 = ~my_x_i[0];
assign y_gt_0 = y_dirs_i[0] & N3;
assign N3 = ~my_y_i[0];
assign N4 = x_dirs_i[1] ^ my_x_i[0];
assign x_eq[1] = ~N4;
assign N5 = y_dirs_i[1] ^ my_y_i[0];
assign y_eq[1] = ~N5;
assign x_gt[1] = x_dirs_i[1] & N6;
assign N6 = ~my_x_i[0];
assign N7 = x_dirs_i[2] ^ my_x_i[0];
assign x_eq[2] = ~N7;
assign N8 = y_dirs_i[2] ^ my_y_i[0];
assign y_eq[2] = ~N8;
assign x_gt[2] = x_dirs_i[2] & N9;
assign N9 = ~my_x_i[0];
assign N10 = x_dirs_i[3] ^ my_x_i[0];
assign x_eq[3] = ~N10;
assign N11 = y_dirs_i[3] ^ my_y_i[0];
assign y_eq[3] = ~N11;
assign x_gt[3] = x_dirs_i[3] & N12;
assign N12 = ~my_x_i[0];
assign y_gt[3] = y_dirs_i[3] & N13;
assign N13 = ~my_y_i[0];
assign N14 = x_dirs_i[4] ^ my_x_i[0];
assign x_eq[4] = ~N14;
assign N15 = y_dirs_i[4] ^ my_y_i[0];
assign y_eq[4] = ~N15;
assign x_gt[4] = x_dirs_i[4] & N16;
assign N16 = ~my_x_i[0];
assign y_gt[4] = y_dirs_i[4] & N17;
assign N17 = ~my_y_i[0];
assign x_lt_0 = N18 & N19;
assign N18 = ~x_gt[0];
assign N19 = ~x_eq[0];
assign y_lt_0 = N20 & N21;
assign N20 = ~y_gt_0;
assign N21 = ~y_eq[0];
assign x_lt[2] = N22 & N23;
assign N22 = ~x_gt[2];
assign N23 = ~x_eq[2];
assign x_lt[3] = N24 & N25;
assign N24 = ~x_gt[3];
assign N25 = ~x_eq[3];
assign x_lt[4] = N26 & N27;
assign N26 = ~x_gt[4];
assign N27 = ~x_eq[4];
assign y_lt[4] = N28 & N29;
assign N28 = ~y_gt[4];
assign N29 = ~y_eq[4];
assign req_o[16] = N30 & x_lt[3];
assign N30 = v_i[3] & y_eq[3];
assign req_o[17] = N31 & x_gt[3];
assign N31 = v_i[3] & y_eq[3];
assign req_o[21] = N32 & x_lt[4];
assign N32 = v_i[4] & y_eq[4];
assign req_o[22] = N33 & x_gt[4];
assign N33 = v_i[4] & y_eq[4];
assign req_o[19] = v_i[3] & y_gt[3];
assign req_o[23] = v_i[4] & y_lt[4];
assign req_o[7] = N34 & x_gt[1];
assign N34 = v_i[1] & y_eq[1];
assign req_o[11] = N35 & x_lt[2];
assign N35 = v_i[2] & y_eq[2];
assign req_o[4] = v_i[0] & y_gt_0;
assign req_o[3] = v_i[0] & y_lt_0;
assign req_o[0] = N36 & y_eq[0];
assign N36 = v_i[0] & x_eq[0];
assign req_o[2] = N37 & x_gt[0];
assign N37 = v_i[0] & y_eq[0];
assign req_o[1] = N38 & x_lt_0;
assign N38 = v_i[0] & y_eq[0];
assign req_o[5] = N39 & y_eq[1];
assign N39 = v_i[1] & x_eq[1];
assign req_o[10] = N40 & y_eq[2];
assign N40 = v_i[2] & x_eq[2];
assign req_o[15] = N41 & y_eq[3];
assign N41 = v_i[3] & x_eq[3];
assign req_o[20] = N42 & y_eq[4];
assign N42 = v_i[4] & x_eq[4];
endmodule
|
module bp_be_pipe_fp
(
clk_i,
reset_i,
decode_i,
rs1_i,
rs2_i,
exc_i,
result_o
);
input [42:0] decode_i;
input [63:0] rs1_i;
input [63:0] rs2_i;
input [6:0] exc_i;
output [63:0] result_o;
input clk_i;
input reset_i;
wire [63:0] result_o;
assign result_o[0] = 1'b0;
assign result_o[1] = 1'b0;
assign result_o[2] = 1'b0;
assign result_o[3] = 1'b0;
assign result_o[4] = 1'b0;
assign result_o[5] = 1'b0;
assign result_o[6] = 1'b0;
assign result_o[7] = 1'b0;
assign result_o[8] = 1'b0;
assign result_o[9] = 1'b0;
assign result_o[10] = 1'b0;
assign result_o[11] = 1'b0;
assign result_o[12] = 1'b0;
assign result_o[13] = 1'b0;
assign result_o[14] = 1'b0;
assign result_o[15] = 1'b0;
assign result_o[16] = 1'b0;
assign result_o[17] = 1'b0;
assign result_o[18] = 1'b0;
assign result_o[19] = 1'b0;
assign result_o[20] = 1'b0;
assign result_o[21] = 1'b0;
assign result_o[22] = 1'b0;
assign result_o[23] = 1'b0;
assign result_o[24] = 1'b0;
assign result_o[25] = 1'b0;
assign result_o[26] = 1'b0;
assign result_o[27] = 1'b0;
assign result_o[28] = 1'b0;
assign result_o[29] = 1'b0;
assign result_o[30] = 1'b0;
assign result_o[31] = 1'b0;
assign result_o[32] = 1'b0;
assign result_o[33] = 1'b0;
assign result_o[34] = 1'b0;
assign result_o[35] = 1'b0;
assign result_o[36] = 1'b0;
assign result_o[37] = 1'b0;
assign result_o[38] = 1'b0;
assign result_o[39] = 1'b0;
assign result_o[40] = 1'b0;
assign result_o[41] = 1'b0;
assign result_o[42] = 1'b0;
assign result_o[43] = 1'b0;
assign result_o[44] = 1'b0;
assign result_o[45] = 1'b0;
assign result_o[46] = 1'b0;
assign result_o[47] = 1'b0;
assign result_o[48] = 1'b0;
assign result_o[49] = 1'b0;
assign result_o[50] = 1'b0;
assign result_o[51] = 1'b0;
assign result_o[52] = 1'b0;
assign result_o[53] = 1'b0;
assign result_o[54] = 1'b0;
assign result_o[55] = 1'b0;
assign result_o[56] = 1'b0;
assign result_o[57] = 1'b0;
assign result_o[58] = 1'b0;
assign result_o[59] = 1'b0;
assign result_o[60] = 1'b0;
assign result_o[61] = 1'b0;
assign result_o[62] = 1'b0;
assign result_o[63] = 1'b0;
endmodule
|
module bsg_mem_1r1w_synth_width_p30_els_p2_read_write_same_addr_p0_harden_p0
(
w_clk_i,
w_reset_i,
w_v_i,
w_addr_i,
w_data_i,
r_v_i,
r_addr_i,
r_data_o
);
input [0:0] w_addr_i;
input [29:0] w_data_i;
input [0:0] r_addr_i;
output [29:0] r_data_o;
input w_clk_i;
input w_reset_i;
input w_v_i;
input r_v_i;
wire [29:0] r_data_o;
wire N0,N1,N2,N3,N4,N5,N7,N8;
reg [59:0] mem;
assign r_data_o[29] = (N3)? mem[29] :
(N0)? mem[59] : 1'b0;
assign N0 = r_addr_i[0];
assign r_data_o[28] = (N3)? mem[28] :
(N0)? mem[58] : 1'b0;
assign r_data_o[27] = (N3)? mem[27] :
(N0)? mem[57] : 1'b0;
assign r_data_o[26] = (N3)? mem[26] :
(N0)? mem[56] : 1'b0;
assign r_data_o[25] = (N3)? mem[25] :
(N0)? mem[55] : 1'b0;
assign r_data_o[24] = (N3)? mem[24] :
(N0)? mem[54] : 1'b0;
assign r_data_o[23] = (N3)? mem[23] :
(N0)? mem[53] : 1'b0;
assign r_data_o[22] = (N3)? mem[22] :
(N0)? mem[52] : 1'b0;
assign r_data_o[21] = (N3)? mem[21] :
(N0)? mem[51] : 1'b0;
assign r_data_o[20] = (N3)? mem[20] :
(N0)? mem[50] : 1'b0;
assign r_data_o[19] = (N3)? mem[19] :
(N0)? mem[49] : 1'b0;
assign r_data_o[18] = (N3)? mem[18] :
(N0)? mem[48] : 1'b0;
assign r_data_o[17] = (N3)? mem[17] :
(N0)? mem[47] : 1'b0;
assign r_data_o[16] = (N3)? mem[16] :
(N0)? mem[46] : 1'b0;
assign r_data_o[15] = (N3)? mem[15] :
(N0)? mem[45] : 1'b0;
assign r_data_o[14] = (N3)? mem[14] :
(N0)? mem[44] : 1'b0;
assign r_data_o[13] = (N3)? mem[13] :
(N0)? mem[43] : 1'b0;
assign r_data_o[12] = (N3)? mem[12] :
(N0)? mem[42] : 1'b0;
assign r_data_o[11] = (N3)? mem[11] :
(N0)? mem[41] : 1'b0;
assign r_data_o[10] = (N3)? mem[10] :
(N0)? mem[40] : 1'b0;
assign r_data_o[9] = (N3)? mem[9] :
(N0)? mem[39] : 1'b0;
assign r_data_o[8] = (N3)? mem[8] :
(N0)? mem[38] : 1'b0;
assign r_data_o[7] = (N3)? mem[7] :
(N0)? mem[37] : 1'b0;
assign r_data_o[6] = (N3)? mem[6] :
(N0)? mem[36] : 1'b0;
assign r_data_o[5] = (N3)? mem[5] :
(N0)? mem[35] : 1'b0;
assign r_data_o[4] = (N3)? mem[4] :
(N0)? mem[34] : 1'b0;
assign r_data_o[3] = (N3)? mem[3] :
(N0)? mem[33] : 1'b0;
assign r_data_o[2] = (N3)? mem[2] :
(N0)? mem[32] : 1'b0;
assign r_data_o[1] = (N3)? mem[1] :
(N0)? mem[31] : 1'b0;
assign r_data_o[0] = (N3)? mem[0] :
(N0)? mem[30] : 1'b0;
assign N5 = ~w_addr_i[0];
assign { N8, N7 } = (N1)? { w_addr_i[0:0], N5 } :
(N2)? { 1'b0, 1'b0 } : 1'b0;
assign N1 = w_v_i;
assign N2 = N4;
assign N3 = ~r_addr_i[0];
assign N4 = ~w_v_i;
always @(posedge w_clk_i) begin
if(N8) begin
{ mem[59:30] } <= { w_data_i[29:0] };
end
if(N7) begin
{ mem[29:0] } <= { w_data_i[29:0] };
end
end
endmodule
|
module bp_be_detector_vaddr_width_p56_paddr_width_p22_asid_width_p10_branch_metadata_fwd_width_p36
(
clk_i,
reset_i,
calc_status_i,
expected_npc_i,
mmu_cmd_ready_i,
chk_dispatch_v_o,
chk_roll_o,
chk_poison_isd_o,
chk_poison_ex_o
);
input [301:0] calc_status_i;
input [63:0] expected_npc_i;
input clk_i;
input reset_i;
input mmu_cmd_ready_i;
output chk_dispatch_v_o;
output chk_roll_o;
output chk_poison_isd_o;
output chk_poison_ex_o;
wire chk_dispatch_v_o,chk_roll_o,chk_poison_isd_o,chk_poison_ex_o,N0,N1,N2,N3,N4,N5,
data_haz_v,struct_haz_v,N6,mispredict_v,N7,N8,N9,N10,N11,N12,N13,N14,N15,N16,N17,
N18,N19,N20,N21,N22,N23,N24,N25,N26,N27,N28,N29,N30,N31,N32,N33,N34,N35,N36,N37,
N38,N39,N40,N41,N42,N43,N44;
wire [2:0] rs1_match_vector,rs2_match_vector,frs1_data_haz_v,frs2_data_haz_v;
wire [1:0] irs1_data_haz_v,irs2_data_haz_v;
assign chk_roll_o = calc_status_i[3];
assign N0 = calc_status_i[234:230] == calc_status_i[73:69];
assign N1 = calc_status_i[227:223] == calc_status_i[73:69];
assign N2 = calc_status_i[234:230] == calc_status_i[83:79];
assign N3 = calc_status_i[227:223] == calc_status_i[83:79];
assign N4 = calc_status_i[234:230] == calc_status_i[93:89];
assign N5 = calc_status_i[227:223] == calc_status_i[93:89];
assign N6 = calc_status_i[300:237] != expected_npc_i;
assign N7 = calc_status_i[233] | calc_status_i[234];
assign N8 = calc_status_i[232] | N7;
assign N9 = calc_status_i[231] | N8;
assign N10 = calc_status_i[230] | N9;
assign N11 = calc_status_i[226] | calc_status_i[227];
assign N12 = calc_status_i[225] | N11;
assign N13 = calc_status_i[224] | N12;
assign N14 = calc_status_i[223] | N13;
assign rs1_match_vector[0] = N10 & N0;
assign rs2_match_vector[0] = N14 & N1;
assign rs1_match_vector[1] = N10 & N2;
assign rs2_match_vector[1] = N14 & N3;
assign rs1_match_vector[2] = N10 & N4;
assign rs2_match_vector[2] = N14 & N5;
assign irs1_data_haz_v[0] = N15 & N16;
assign N15 = calc_status_i[236] & rs1_match_vector[0];
assign N16 = calc_status_i[77] | calc_status_i[76];
assign irs2_data_haz_v[0] = N17 & N18;
assign N17 = calc_status_i[229] & rs2_match_vector[0];
assign N18 = calc_status_i[77] | calc_status_i[76];
assign frs1_data_haz_v[0] = N19 & N20;
assign N19 = calc_status_i[235] & rs1_match_vector[0];
assign N20 = calc_status_i[75] | calc_status_i[74];
assign frs2_data_haz_v[0] = N21 & N22;
assign N21 = calc_status_i[228] & rs2_match_vector[0];
assign N22 = calc_status_i[75] | calc_status_i[74];
assign irs1_data_haz_v[1] = N23 & calc_status_i[86];
assign N23 = calc_status_i[236] & rs1_match_vector[1];
assign irs2_data_haz_v[1] = N24 & calc_status_i[86];
assign N24 = calc_status_i[229] & rs2_match_vector[1];
assign frs1_data_haz_v[1] = N25 & N26;
assign N25 = calc_status_i[235] & rs1_match_vector[1];
assign N26 = calc_status_i[85] | calc_status_i[84];
assign frs2_data_haz_v[1] = N27 & N28;
assign N27 = calc_status_i[228] & rs2_match_vector[1];
assign N28 = calc_status_i[85] | calc_status_i[84];
assign frs1_data_haz_v[2] = N29 & calc_status_i[94];
assign N29 = calc_status_i[235] & rs1_match_vector[2];
assign frs2_data_haz_v[2] = N30 & calc_status_i[94];
assign N30 = calc_status_i[228] & rs2_match_vector[2];
assign data_haz_v = N36 | N38;
assign N36 = N33 | N35;
assign N33 = N31 | N32;
assign N31 = irs1_data_haz_v[1] | irs1_data_haz_v[0];
assign N32 = irs2_data_haz_v[1] | irs2_data_haz_v[0];
assign N35 = N34 | frs1_data_haz_v[0];
assign N34 = frs1_data_haz_v[2] | frs1_data_haz_v[1];
assign N38 = N37 | frs2_data_haz_v[0];
assign N37 = frs2_data_haz_v[2] | frs2_data_haz_v[1];
assign struct_haz_v = ~mmu_cmd_ready_i;
assign mispredict_v = calc_status_i[301] & N6;
assign chk_dispatch_v_o = ~N39;
assign N39 = data_haz_v | struct_haz_v;
assign chk_poison_isd_o = N42 | calc_status_i[1];
assign N42 = N41 | calc_status_i[2];
assign N41 = N40 | calc_status_i[3];
assign N40 = reset_i | mispredict_v;
assign chk_poison_ex_o = N44 | calc_status_i[1];
assign N44 = N43 | calc_status_i[2];
assign N43 = reset_i | calc_status_i[3];
endmodule
|
module bp_be_dcache_lru_encode_ways_p8
(
lru_i,
way_id_o
);
input [6:0] lru_i;
output [2:0] way_id_o;
wire [2:0] way_id_o;
wire N0,N1,N2,N3,N4,N5,N6,N7,N8,N9,N10,N11,N12,N13,N14,N15,N16,N17,N18,N19,N20,N21,
N22,N23,N24,N25,N26,N27,N28,N29,N30;
assign N11 = N8 & N9;
assign N12 = N11 & N10;
assign N13 = lru_i[3] & N9;
assign N14 = N13 & N10;
assign N16 = N15 & lru_i[1];
assign N17 = N16 & N10;
assign N18 = lru_i[4] & lru_i[1];
assign N19 = N18 & N10;
assign N22 = N20 & N21;
assign N23 = N22 & lru_i[0];
assign N24 = lru_i[5] & N21;
assign N25 = N24 & lru_i[0];
assign N27 = N26 & lru_i[2];
assign N28 = N27 & lru_i[0];
assign N29 = lru_i[6] & lru_i[2];
assign N30 = N29 & lru_i[0];
assign way_id_o = (N0)? { 1'b0, 1'b0, 1'b0 } :
(N1)? { 1'b0, 1'b0, 1'b1 } :
(N2)? { 1'b0, 1'b1, 1'b0 } :
(N3)? { 1'b0, 1'b1, 1'b1 } :
(N4)? { 1'b1, 1'b0, 1'b0 } :
(N5)? { 1'b1, 1'b0, 1'b1 } :
(N6)? { 1'b1, 1'b1, 1'b0 } :
(N7)? { 1'b1, 1'b1, 1'b1 } : 1'b0;
assign N0 = N12;
assign N1 = N14;
assign N2 = N17;
assign N3 = N19;
assign N4 = N23;
assign N5 = N25;
assign N6 = N28;
assign N7 = N30;
assign N8 = ~lru_i[3];
assign N9 = ~lru_i[1];
assign N10 = ~lru_i[0];
assign N15 = ~lru_i[4];
assign N20 = ~lru_i[5];
assign N21 = ~lru_i[2];
assign N26 = ~lru_i[6];
endmodule
|
module bsg_mux_one_hot_width_p32_els_p4
(
data_i,
sel_one_hot_i,
data_o
);
input [127:0] data_i;
input [3:0] sel_one_hot_i;
output [31:0] data_o;
wire [31:0] data_o;
wire N0,N1,N2,N3,N4,N5,N6,N7,N8,N9,N10,N11,N12,N13,N14,N15,N16,N17,N18,N19,N20,N21,
N22,N23,N24,N25,N26,N27,N28,N29,N30,N31,N32,N33,N34,N35,N36,N37,N38,N39,N40,N41,
N42,N43,N44,N45,N46,N47,N48,N49,N50,N51,N52,N53,N54,N55,N56,N57,N58,N59,N60,N61,
N62,N63;
wire [127:0] data_masked;
assign data_masked[31] = data_i[31] & sel_one_hot_i[0];
assign data_masked[30] = data_i[30] & sel_one_hot_i[0];
assign data_masked[29] = data_i[29] & sel_one_hot_i[0];
assign data_masked[28] = data_i[28] & sel_one_hot_i[0];
assign data_masked[27] = data_i[27] & sel_one_hot_i[0];
assign data_masked[26] = data_i[26] & sel_one_hot_i[0];
assign data_masked[25] = data_i[25] & sel_one_hot_i[0];
assign data_masked[24] = data_i[24] & sel_one_hot_i[0];
assign data_masked[23] = data_i[23] & sel_one_hot_i[0];
assign data_masked[22] = data_i[22] & sel_one_hot_i[0];
assign data_masked[21] = data_i[21] & sel_one_hot_i[0];
assign data_masked[20] = data_i[20] & sel_one_hot_i[0];
assign data_masked[19] = data_i[19] & sel_one_hot_i[0];
assign data_masked[18] = data_i[18] & sel_one_hot_i[0];
assign data_masked[17] = data_i[17] & sel_one_hot_i[0];
assign data_masked[16] = data_i[16] & sel_one_hot_i[0];
assign data_masked[15] = data_i[15] & sel_one_hot_i[0];
assign data_masked[14] = data_i[14] & sel_one_hot_i[0];
assign data_masked[13] = data_i[13] & sel_one_hot_i[0];
assign data_masked[12] = data_i[12] & sel_one_hot_i[0];
assign data_masked[11] = data_i[11] & sel_one_hot_i[0];
assign data_masked[10] = data_i[10] & sel_one_hot_i[0];
assign data_masked[9] = data_i[9] & sel_one_hot_i[0];
assign data_masked[8] = data_i[8] & sel_one_hot_i[0];
assign data_masked[7] = data_i[7] & sel_one_hot_i[0];
assign data_masked[6] = data_i[6] & sel_one_hot_i[0];
assign data_masked[5] = data_i[5] & sel_one_hot_i[0];
assign data_masked[4] = data_i[4] & sel_one_hot_i[0];
assign data_masked[3] = data_i[3] & sel_one_hot_i[0];
assign data_masked[2] = data_i[2] & sel_one_hot_i[0];
assign data_masked[1] = data_i[1] & sel_one_hot_i[0];
assign data_masked[0] = data_i[0] & sel_one_hot_i[0];
assign data_masked[63] = data_i[63] & sel_one_hot_i[1];
assign data_masked[62] = data_i[62] & sel_one_hot_i[1];
assign data_masked[61] = data_i[61] & sel_one_hot_i[1];
assign data_masked[60] = data_i[60] & sel_one_hot_i[1];
assign data_masked[59] = data_i[59] & sel_one_hot_i[1];
assign data_masked[58] = data_i[58] & sel_one_hot_i[1];
assign data_masked[57] = data_i[57] & sel_one_hot_i[1];
assign data_masked[56] = data_i[56] & sel_one_hot_i[1];
assign data_masked[55] = data_i[55] & sel_one_hot_i[1];
assign data_masked[54] = data_i[54] & sel_one_hot_i[1];
assign data_masked[53] = data_i[53] & sel_one_hot_i[1];
assign data_masked[52] = data_i[52] & sel_one_hot_i[1];
assign data_masked[51] = data_i[51] & sel_one_hot_i[1];
assign data_masked[50] = data_i[50] & sel_one_hot_i[1];
assign data_masked[49] = data_i[49] & sel_one_hot_i[1];
assign data_masked[48] = data_i[48] & sel_one_hot_i[1];
assign data_masked[47] = data_i[47] & sel_one_hot_i[1];
assign data_masked[46] = data_i[46] & sel_one_hot_i[1];
assign data_masked[45] = data_i[45] & sel_one_hot_i[1];
assign data_masked[44] = data_i[44] & sel_one_hot_i[1];
assign data_masked[43] = data_i[43] & sel_one_hot_i[1];
assign data_masked[42] = data_i[42] & sel_one_hot_i[1];
assign data_masked[41] = data_i[41] & sel_one_hot_i[1];
assign data_masked[40] = data_i[40] & sel_one_hot_i[1];
assign data_masked[39] = data_i[39] & sel_one_hot_i[1];
assign data_masked[38] = data_i[38] & sel_one_hot_i[1];
assign data_masked[37] = data_i[37] & sel_one_hot_i[1];
assign data_masked[36] = data_i[36] & sel_one_hot_i[1];
assign data_masked[35] = data_i[35] & sel_one_hot_i[1];
assign data_masked[34] = data_i[34] & sel_one_hot_i[1];
assign data_masked[33] = data_i[33] & sel_one_hot_i[1];
assign data_masked[32] = data_i[32] & sel_one_hot_i[1];
assign data_masked[95] = data_i[95] & sel_one_hot_i[2];
assign data_masked[94] = data_i[94] & sel_one_hot_i[2];
assign data_masked[93] = data_i[93] & sel_one_hot_i[2];
assign data_masked[92] = data_i[92] & sel_one_hot_i[2];
assign data_masked[91] = data_i[91] & sel_one_hot_i[2];
assign data_masked[90] = data_i[90] & sel_one_hot_i[2];
assign data_masked[89] = data_i[89] & sel_one_hot_i[2];
assign data_masked[88] = data_i[88] & sel_one_hot_i[2];
assign data_masked[87] = data_i[87] & sel_one_hot_i[2];
assign data_masked[86] = data_i[86] & sel_one_hot_i[2];
assign data_masked[85] = data_i[85] & sel_one_hot_i[2];
assign data_masked[84] = data_i[84] & sel_one_hot_i[2];
assign data_masked[83] = data_i[83] & sel_one_hot_i[2];
assign data_masked[82] = data_i[82] & sel_one_hot_i[2];
assign data_masked[81] = data_i[81] & sel_one_hot_i[2];
assign data_masked[80] = data_i[80] & sel_one_hot_i[2];
assign data_masked[79] = data_i[79] & sel_one_hot_i[2];
assign data_masked[78] = data_i[78] & sel_one_hot_i[2];
assign data_masked[77] = data_i[77] & sel_one_hot_i[2];
assign data_masked[76] = data_i[76] & sel_one_hot_i[2];
assign data_masked[75] = data_i[75] & sel_one_hot_i[2];
assign data_masked[74] = data_i[74] & sel_one_hot_i[2];
assign data_masked[73] = data_i[73] & sel_one_hot_i[2];
assign data_masked[72] = data_i[72] & sel_one_hot_i[2];
assign data_masked[71] = data_i[71] & sel_one_hot_i[2];
assign data_masked[70] = data_i[70] & sel_one_hot_i[2];
assign data_masked[69] = data_i[69] & sel_one_hot_i[2];
assign data_masked[68] = data_i[68] & sel_one_hot_i[2];
assign data_masked[67] = data_i[67] & sel_one_hot_i[2];
assign data_masked[66] = data_i[66] & sel_one_hot_i[2];
assign data_masked[65] = data_i[65] & sel_one_hot_i[2];
assign data_masked[64] = data_i[64] & sel_one_hot_i[2];
assign data_masked[127] = data_i[127] & sel_one_hot_i[3];
assign data_masked[126] = data_i[126] & sel_one_hot_i[3];
assign data_masked[125] = data_i[125] & sel_one_hot_i[3];
assign data_masked[124] = data_i[124] & sel_one_hot_i[3];
assign data_masked[123] = data_i[123] & sel_one_hot_i[3];
assign data_masked[122] = data_i[122] & sel_one_hot_i[3];
assign data_masked[121] = data_i[121] & sel_one_hot_i[3];
assign data_masked[120] = data_i[120] & sel_one_hot_i[3];
assign data_masked[119] = data_i[119] & sel_one_hot_i[3];
assign data_masked[118] = data_i[118] & sel_one_hot_i[3];
assign data_masked[117] = data_i[117] & sel_one_hot_i[3];
assign data_masked[116] = data_i[116] & sel_one_hot_i[3];
assign data_masked[115] = data_i[115] & sel_one_hot_i[3];
assign data_masked[114] = data_i[114] & sel_one_hot_i[3];
assign data_masked[113] = data_i[113] & sel_one_hot_i[3];
assign data_masked[112] = data_i[112] & sel_one_hot_i[3];
assign data_masked[111] = data_i[111] & sel_one_hot_i[3];
assign data_masked[110] = data_i[110] & sel_one_hot_i[3];
assign data_masked[109] = data_i[109] & sel_one_hot_i[3];
assign data_masked[108] = data_i[108] & sel_one_hot_i[3];
assign data_masked[107] = data_i[107] & sel_one_hot_i[3];
assign data_masked[106] = data_i[106] & sel_one_hot_i[3];
assign data_masked[105] = data_i[105] & sel_one_hot_i[3];
assign data_masked[104] = data_i[104] & sel_one_hot_i[3];
assign data_masked[103] = data_i[103] & sel_one_hot_i[3];
assign data_masked[102] = data_i[102] & sel_one_hot_i[3];
assign data_masked[101] = data_i[101] & sel_one_hot_i[3];
assign data_masked[100] = data_i[100] & sel_one_hot_i[3];
assign data_masked[99] = data_i[99] & sel_one_hot_i[3];
assign data_masked[98] = data_i[98] & sel_one_hot_i[3];
assign data_masked[97] = data_i[97] & sel_one_hot_i[3];
assign data_masked[96] = data_i[96] & sel_one_hot_i[3];
assign data_o[0] = N1 | data_masked[0];
assign N1 = N0 | data_masked[32];
assign N0 = data_masked[96] | data_masked[64];
assign data_o[1] = N3 | data_masked[1];
assign N3 = N2 | data_masked[33];
assign N2 = data_masked[97] | data_masked[65];
assign data_o[2] = N5 | data_masked[2];
assign N5 = N4 | data_masked[34];
assign N4 = data_masked[98] | data_masked[66];
assign data_o[3] = N7 | data_masked[3];
assign N7 = N6 | data_masked[35];
assign N6 = data_masked[99] | data_masked[67];
assign data_o[4] = N9 | data_masked[4];
assign N9 = N8 | data_masked[36];
assign N8 = data_masked[100] | data_masked[68];
assign data_o[5] = N11 | data_masked[5];
assign N11 = N10 | data_masked[37];
assign N10 = data_masked[101] | data_masked[69];
assign data_o[6] = N13 | data_masked[6];
assign N13 = N12 | data_masked[38];
assign N12 = data_masked[102] | data_masked[70];
assign data_o[7] = N15 | data_masked[7];
assign N15 = N14 | data_masked[39];
assign N14 = data_masked[103] | data_masked[71];
assign data_o[8] = N17 | data_masked[8];
assign N17 = N16 | data_masked[40];
assign N16 = data_masked[104] | data_masked[72];
assign data_o[9] = N19 | data_masked[9];
assign N19 = N18 | data_masked[41];
assign N18 = data_masked[105] | data_masked[73];
assign data_o[10] = N21 | data_masked[10];
assign N21 = N20 | data_masked[42];
assign N20 = data_masked[106] | data_masked[74];
assign data_o[11] = N23 | data_masked[11];
assign N23 = N22 | data_masked[43];
assign N22 = data_masked[107] | data_masked[75];
assign data_o[12] = N25 | data_masked[12];
assign N25 = N24 | data_masked[44];
assign N24 = data_masked[108] | data_masked[76];
assign data_o[13] = N27 | data_masked[13];
assign N27 = N26 | data_masked[45];
assign N26 = data_masked[109] | data_masked[77];
assign data_o[14] = N29 | data_masked[14];
assign N29 = N28 | data_masked[46];
assign N28 = data_masked[110] | data_masked[78];
assign data_o[15] = N31 | data_masked[15];
assign N31 = N30 | data_masked[47];
assign N30 = data_masked[111] | data_masked[79];
assign data_o[16] = N33 | data_masked[16];
assign N33 = N32 | data_masked[48];
assign N32 = data_masked[112] | data_masked[80];
assign data_o[17] = N35 | data_masked[17];
assign N35 = N34 | data_masked[49];
assign N34 = data_masked[113] | data_masked[81];
assign data_o[18] = N37 | data_masked[18];
assign N37 = N36 | data_masked[50];
assign N36 = data_masked[114] | data_masked[82];
assign data_o[19] = N39 | data_masked[19];
assign N39 = N38 | data_masked[51];
assign N38 = data_masked[115] | data_masked[83];
assign data_o[20] = N41 | data_masked[20];
assign N41 = N40 | data_masked[52];
assign N40 = data_masked[116] | data_masked[84];
assign data_o[21] = N43 | data_masked[21];
assign N43 = N42 | data_masked[53];
assign N42 = data_masked[117] | data_masked[85];
assign data_o[22] = N45 | data_masked[22];
assign N45 = N44 | data_masked[54];
assign N44 = data_masked[118] | data_masked[86];
assign data_o[23] = N47 | data_masked[23];
assign N47 = N46 | data_masked[55];
assign N46 = data_masked[119] | data_masked[87];
assign data_o[24] = N49 | data_masked[24];
assign N49 = N48 | data_masked[56];
assign N48 = data_masked[120] | data_masked[88];
assign data_o[25] = N51 | data_masked[25];
assign N51 = N50 | data_masked[57];
assign N50 = data_masked[121] | data_masked[89];
assign data_o[26] = N53 | data_masked[26];
assign N53 = N52 | data_masked[58];
assign N52 = data_masked[122] | data_masked[90];
assign data_o[27] = N55 | data_masked[27];
assign N55 = N54 | data_masked[59];
assign N54 = data_masked[123] | data_masked[91];
assign data_o[28] = N57 | data_masked[28];
assign N57 = N56 | data_masked[60];
assign N56 = data_masked[124] | data_masked[92];
assign data_o[29] = N59 | data_masked[29];
assign N59 = N58 | data_masked[61];
assign N58 = data_masked[125] | data_masked[93];
assign data_o[30] = N61 | data_masked[30];
assign N61 = N60 | data_masked[62];
assign N60 = data_masked[126] | data_masked[94];
assign data_o[31] = N63 | data_masked[31];
assign N63 = N62 | data_masked[63];
assign N62 = data_masked[127] | data_masked[95];
endmodule
|
module bsg_dff_reset_en_width_p1
(
clk_i,
reset_i,
en_i,
data_i,
data_o
);
input [0:0] data_i;
output [0:0] data_o;
input clk_i;
input reset_i;
input en_i;
wire N0,N1,N2,N3,N4,N5,N6;
reg [0:0] data_o;
assign N3 = (N0)? 1'b1 :
(N6)? 1'b1 :
(N2)? 1'b0 : 1'b0;
assign N0 = reset_i;
assign N4 = (N0)? 1'b0 :
(N6)? data_i[0] : 1'b0;
assign N1 = en_i | reset_i;
assign N2 = ~N1;
assign N5 = ~reset_i;
assign N6 = en_i & N5;
always @(posedge clk_i) begin
if(N3) begin
{ data_o[0:0] } <= { N4 };
end
end
endmodule
|
module bsg_decode_num_out_p2
(
i,
o
);
input [0:0] i;
output [1:0] o;
wire [1:0] o;
assign o = { 1'b0, 1'b1 } << i[0];
endmodule
|
module bsg_mux_one_hot_width_p38_els_p2
(
data_i,
sel_one_hot_i,
data_o
);
input [75:0] data_i;
input [1:0] sel_one_hot_i;
output [37:0] data_o;
wire [37:0] data_o;
wire [75:0] data_masked;
assign data_masked[37] = data_i[37] & sel_one_hot_i[0];
assign data_masked[36] = data_i[36] & sel_one_hot_i[0];
assign data_masked[35] = data_i[35] & sel_one_hot_i[0];
assign data_masked[34] = data_i[34] & sel_one_hot_i[0];
assign data_masked[33] = data_i[33] & sel_one_hot_i[0];
assign data_masked[32] = data_i[32] & sel_one_hot_i[0];
assign data_masked[31] = data_i[31] & sel_one_hot_i[0];
assign data_masked[30] = data_i[30] & sel_one_hot_i[0];
assign data_masked[29] = data_i[29] & sel_one_hot_i[0];
assign data_masked[28] = data_i[28] & sel_one_hot_i[0];
assign data_masked[27] = data_i[27] & sel_one_hot_i[0];
assign data_masked[26] = data_i[26] & sel_one_hot_i[0];
assign data_masked[25] = data_i[25] & sel_one_hot_i[0];
assign data_masked[24] = data_i[24] & sel_one_hot_i[0];
assign data_masked[23] = data_i[23] & sel_one_hot_i[0];
assign data_masked[22] = data_i[22] & sel_one_hot_i[0];
assign data_masked[21] = data_i[21] & sel_one_hot_i[0];
assign data_masked[20] = data_i[20] & sel_one_hot_i[0];
assign data_masked[19] = data_i[19] & sel_one_hot_i[0];
assign data_masked[18] = data_i[18] & sel_one_hot_i[0];
assign data_masked[17] = data_i[17] & sel_one_hot_i[0];
assign data_masked[16] = data_i[16] & sel_one_hot_i[0];
assign data_masked[15] = data_i[15] & sel_one_hot_i[0];
assign data_masked[14] = data_i[14] & sel_one_hot_i[0];
assign data_masked[13] = data_i[13] & sel_one_hot_i[0];
assign data_masked[12] = data_i[12] & sel_one_hot_i[0];
assign data_masked[11] = data_i[11] & sel_one_hot_i[0];
assign data_masked[10] = data_i[10] & sel_one_hot_i[0];
assign data_masked[9] = data_i[9] & sel_one_hot_i[0];
assign data_masked[8] = data_i[8] & sel_one_hot_i[0];
assign data_masked[7] = data_i[7] & sel_one_hot_i[0];
assign data_masked[6] = data_i[6] & sel_one_hot_i[0];
assign data_masked[5] = data_i[5] & sel_one_hot_i[0];
assign data_masked[4] = data_i[4] & sel_one_hot_i[0];
assign data_masked[3] = data_i[3] & sel_one_hot_i[0];
assign data_masked[2] = data_i[2] & sel_one_hot_i[0];
assign data_masked[1] = data_i[1] & sel_one_hot_i[0];
assign data_masked[0] = data_i[0] & sel_one_hot_i[0];
assign data_masked[75] = data_i[75] & sel_one_hot_i[1];
assign data_masked[74] = data_i[74] & sel_one_hot_i[1];
assign data_masked[73] = data_i[73] & sel_one_hot_i[1];
assign data_masked[72] = data_i[72] & sel_one_hot_i[1];
assign data_masked[71] = data_i[71] & sel_one_hot_i[1];
assign data_masked[70] = data_i[70] & sel_one_hot_i[1];
assign data_masked[69] = data_i[69] & sel_one_hot_i[1];
assign data_masked[68] = data_i[68] & sel_one_hot_i[1];
assign data_masked[67] = data_i[67] & sel_one_hot_i[1];
assign data_masked[66] = data_i[66] & sel_one_hot_i[1];
assign data_masked[65] = data_i[65] & sel_one_hot_i[1];
assign data_masked[64] = data_i[64] & sel_one_hot_i[1];
assign data_masked[63] = data_i[63] & sel_one_hot_i[1];
assign data_masked[62] = data_i[62] & sel_one_hot_i[1];
assign data_masked[61] = data_i[61] & sel_one_hot_i[1];
assign data_masked[60] = data_i[60] & sel_one_hot_i[1];
assign data_masked[59] = data_i[59] & sel_one_hot_i[1];
assign data_masked[58] = data_i[58] & sel_one_hot_i[1];
assign data_masked[57] = data_i[57] & sel_one_hot_i[1];
assign data_masked[56] = data_i[56] & sel_one_hot_i[1];
assign data_masked[55] = data_i[55] & sel_one_hot_i[1];
assign data_masked[54] = data_i[54] & sel_one_hot_i[1];
assign data_masked[53] = data_i[53] & sel_one_hot_i[1];
assign data_masked[52] = data_i[52] & sel_one_hot_i[1];
assign data_masked[51] = data_i[51] & sel_one_hot_i[1];
assign data_masked[50] = data_i[50] & sel_one_hot_i[1];
assign data_masked[49] = data_i[49] & sel_one_hot_i[1];
assign data_masked[48] = data_i[48] & sel_one_hot_i[1];
assign data_masked[47] = data_i[47] & sel_one_hot_i[1];
assign data_masked[46] = data_i[46] & sel_one_hot_i[1];
assign data_masked[45] = data_i[45] & sel_one_hot_i[1];
assign data_masked[44] = data_i[44] & sel_one_hot_i[1];
assign data_masked[43] = data_i[43] & sel_one_hot_i[1];
assign data_masked[42] = data_i[42] & sel_one_hot_i[1];
assign data_masked[41] = data_i[41] & sel_one_hot_i[1];
assign data_masked[40] = data_i[40] & sel_one_hot_i[1];
assign data_masked[39] = data_i[39] & sel_one_hot_i[1];
assign data_masked[38] = data_i[38] & sel_one_hot_i[1];
assign data_o[0] = data_masked[38] | data_masked[0];
assign data_o[1] = data_masked[39] | data_masked[1];
assign data_o[2] = data_masked[40] | data_masked[2];
assign data_o[3] = data_masked[41] | data_masked[3];
assign data_o[4] = data_masked[42] | data_masked[4];
assign data_o[5] = data_masked[43] | data_masked[5];
assign data_o[6] = data_masked[44] | data_masked[6];
assign data_o[7] = data_masked[45] | data_masked[7];
assign data_o[8] = data_masked[46] | data_masked[8];
assign data_o[9] = data_masked[47] | data_masked[9];
assign data_o[10] = data_masked[48] | data_masked[10];
assign data_o[11] = data_masked[49] | data_masked[11];
assign data_o[12] = data_masked[50] | data_masked[12];
assign data_o[13] = data_masked[51] | data_masked[13];
assign data_o[14] = data_masked[52] | data_masked[14];
assign data_o[15] = data_masked[53] | data_masked[15];
assign data_o[16] = data_masked[54] | data_masked[16];
assign data_o[17] = data_masked[55] | data_masked[17];
assign data_o[18] = data_masked[56] | data_masked[18];
assign data_o[19] = data_masked[57] | data_masked[19];
assign data_o[20] = data_masked[58] | data_masked[20];
assign data_o[21] = data_masked[59] | data_masked[21];
assign data_o[22] = data_masked[60] | data_masked[22];
assign data_o[23] = data_masked[61] | data_masked[23];
assign data_o[24] = data_masked[62] | data_masked[24];
assign data_o[25] = data_masked[63] | data_masked[25];
assign data_o[26] = data_masked[64] | data_masked[26];
assign data_o[27] = data_masked[65] | data_masked[27];
assign data_o[28] = data_masked[66] | data_masked[28];
assign data_o[29] = data_masked[67] | data_masked[29];
assign data_o[30] = data_masked[68] | data_masked[30];
assign data_o[31] = data_masked[69] | data_masked[31];
assign data_o[32] = data_masked[70] | data_masked[32];
assign data_o[33] = data_masked[71] | data_masked[33];
assign data_o[34] = data_masked[72] | data_masked[34];
assign data_o[35] = data_masked[73] | data_masked[35];
assign data_o[36] = data_masked[74] | data_masked[36];
assign data_o[37] = data_masked[75] | data_masked[37];
endmodule
|
module bsg_dff_width_p1890
(
clk_i,
data_i,
data_o
);
input [1889:0] data_i;
output [1889:0] data_o;
input clk_i;
reg [1889:0] data_o;
always @(posedge clk_i) begin
if(1'b1) begin
{ data_o[1889:0] } <= { data_i[1889:0] };
end
end
endmodule
|
module bsg_dff_width_p35
(
clk_i,
data_i,
data_o
);
input [34:0] data_i;
output [34:0] data_o;
input clk_i;
reg [34:0] data_o;
always @(posedge clk_i) begin
if(1'b1) begin
{ data_o[34:0] } <= { data_i[34:0] };
end
end
endmodule
|
module bp_be_dcache_lce_tr_num_lce_p2_num_cce_p1_data_width_p64_paddr_width_p22_lce_data_width_p512_ways_p8_sets_p64
(
tr_received_o,
lce_tr_resp_i,
lce_tr_resp_v_i,
lce_tr_resp_yumi_o,
data_mem_pkt_v_o,
data_mem_pkt_o,
data_mem_pkt_yumi_i
);
input [538:0] lce_tr_resp_i;
output [521:0] data_mem_pkt_o;
input lce_tr_resp_v_i;
input data_mem_pkt_yumi_i;
output tr_received_o;
output lce_tr_resp_yumi_o;
output data_mem_pkt_v_o;
wire [521:0] data_mem_pkt_o;
wire tr_received_o,lce_tr_resp_yumi_o,data_mem_pkt_v_o,data_mem_pkt_yumi_i,
lce_tr_resp_v_i;
assign data_mem_pkt_o[0] = 1'b1;
assign tr_received_o = data_mem_pkt_yumi_i;
assign lce_tr_resp_yumi_o = data_mem_pkt_yumi_i;
assign data_mem_pkt_v_o = lce_tr_resp_v_i;
assign data_mem_pkt_o[521] = lce_tr_resp_i[523];
assign data_mem_pkt_o[520] = lce_tr_resp_i[522];
assign data_mem_pkt_o[519] = lce_tr_resp_i[521];
assign data_mem_pkt_o[518] = lce_tr_resp_i[520];
assign data_mem_pkt_o[517] = lce_tr_resp_i[519];
assign data_mem_pkt_o[516] = lce_tr_resp_i[518];
assign data_mem_pkt_o[515] = lce_tr_resp_i[536];
assign data_mem_pkt_o[514] = lce_tr_resp_i[535];
assign data_mem_pkt_o[513] = lce_tr_resp_i[534];
assign data_mem_pkt_o[512] = lce_tr_resp_i[511];
assign data_mem_pkt_o[511] = lce_tr_resp_i[510];
assign data_mem_pkt_o[510] = lce_tr_resp_i[509];
assign data_mem_pkt_o[509] = lce_tr_resp_i[508];
assign data_mem_pkt_o[508] = lce_tr_resp_i[507];
assign data_mem_pkt_o[507] = lce_tr_resp_i[506];
assign data_mem_pkt_o[506] = lce_tr_resp_i[505];
assign data_mem_pkt_o[505] = lce_tr_resp_i[504];
assign data_mem_pkt_o[504] = lce_tr_resp_i[503];
assign data_mem_pkt_o[503] = lce_tr_resp_i[502];
assign data_mem_pkt_o[502] = lce_tr_resp_i[501];
assign data_mem_pkt_o[501] = lce_tr_resp_i[500];
assign data_mem_pkt_o[500] = lce_tr_resp_i[499];
assign data_mem_pkt_o[499] = lce_tr_resp_i[498];
assign data_mem_pkt_o[498] = lce_tr_resp_i[497];
assign data_mem_pkt_o[497] = lce_tr_resp_i[496];
assign data_mem_pkt_o[496] = lce_tr_resp_i[495];
assign data_mem_pkt_o[495] = lce_tr_resp_i[494];
assign data_mem_pkt_o[494] = lce_tr_resp_i[493];
assign data_mem_pkt_o[493] = lce_tr_resp_i[492];
assign data_mem_pkt_o[492] = lce_tr_resp_i[491];
assign data_mem_pkt_o[491] = lce_tr_resp_i[490];
assign data_mem_pkt_o[490] = lce_tr_resp_i[489];
assign data_mem_pkt_o[489] = lce_tr_resp_i[488];
assign data_mem_pkt_o[488] = lce_tr_resp_i[487];
assign data_mem_pkt_o[487] = lce_tr_resp_i[486];
assign data_mem_pkt_o[486] = lce_tr_resp_i[485];
assign data_mem_pkt_o[485] = lce_tr_resp_i[484];
assign data_mem_pkt_o[484] = lce_tr_resp_i[483];
assign data_mem_pkt_o[483] = lce_tr_resp_i[482];
assign data_mem_pkt_o[482] = lce_tr_resp_i[481];
assign data_mem_pkt_o[481] = lce_tr_resp_i[480];
assign data_mem_pkt_o[480] = lce_tr_resp_i[479];
assign data_mem_pkt_o[479] = lce_tr_resp_i[478];
assign data_mem_pkt_o[478] = lce_tr_resp_i[477];
assign data_mem_pkt_o[477] = lce_tr_resp_i[476];
assign data_mem_pkt_o[476] = lce_tr_resp_i[475];
assign data_mem_pkt_o[475] = lce_tr_resp_i[474];
assign data_mem_pkt_o[474] = lce_tr_resp_i[473];
assign data_mem_pkt_o[473] = lce_tr_resp_i[472];
assign data_mem_pkt_o[472] = lce_tr_resp_i[471];
assign data_mem_pkt_o[471] = lce_tr_resp_i[470];
assign data_mem_pkt_o[470] = lce_tr_resp_i[469];
assign data_mem_pkt_o[469] = lce_tr_resp_i[468];
assign data_mem_pkt_o[468] = lce_tr_resp_i[467];
assign data_mem_pkt_o[467] = lce_tr_resp_i[466];
assign data_mem_pkt_o[466] = lce_tr_resp_i[465];
assign data_mem_pkt_o[465] = lce_tr_resp_i[464];
assign data_mem_pkt_o[464] = lce_tr_resp_i[463];
assign data_mem_pkt_o[463] = lce_tr_resp_i[462];
assign data_mem_pkt_o[462] = lce_tr_resp_i[461];
assign data_mem_pkt_o[461] = lce_tr_resp_i[460];
assign data_mem_pkt_o[460] = lce_tr_resp_i[459];
assign data_mem_pkt_o[459] = lce_tr_resp_i[458];
assign data_mem_pkt_o[458] = lce_tr_resp_i[457];
assign data_mem_pkt_o[457] = lce_tr_resp_i[456];
assign data_mem_pkt_o[456] = lce_tr_resp_i[455];
assign data_mem_pkt_o[455] = lce_tr_resp_i[454];
assign data_mem_pkt_o[454] = lce_tr_resp_i[453];
assign data_mem_pkt_o[453] = lce_tr_resp_i[452];
assign data_mem_pkt_o[452] = lce_tr_resp_i[451];
assign data_mem_pkt_o[451] = lce_tr_resp_i[450];
assign data_mem_pkt_o[450] = lce_tr_resp_i[449];
assign data_mem_pkt_o[449] = lce_tr_resp_i[448];
assign data_mem_pkt_o[448] = lce_tr_resp_i[447];
assign data_mem_pkt_o[447] = lce_tr_resp_i[446];
assign data_mem_pkt_o[446] = lce_tr_resp_i[445];
assign data_mem_pkt_o[445] = lce_tr_resp_i[444];
assign data_mem_pkt_o[444] = lce_tr_resp_i[443];
assign data_mem_pkt_o[443] = lce_tr_resp_i[442];
assign data_mem_pkt_o[442] = lce_tr_resp_i[441];
assign data_mem_pkt_o[441] = lce_tr_resp_i[440];
assign data_mem_pkt_o[440] = lce_tr_resp_i[439];
assign data_mem_pkt_o[439] = lce_tr_resp_i[438];
assign data_mem_pkt_o[438] = lce_tr_resp_i[437];
assign data_mem_pkt_o[437] = lce_tr_resp_i[436];
assign data_mem_pkt_o[436] = lce_tr_resp_i[435];
assign data_mem_pkt_o[435] = lce_tr_resp_i[434];
assign data_mem_pkt_o[434] = lce_tr_resp_i[433];
assign data_mem_pkt_o[433] = lce_tr_resp_i[432];
assign data_mem_pkt_o[432] = lce_tr_resp_i[431];
assign data_mem_pkt_o[431] = lce_tr_resp_i[430];
assign data_mem_pkt_o[430] = lce_tr_resp_i[429];
assign data_mem_pkt_o[429] = lce_tr_resp_i[428];
assign data_mem_pkt_o[428] = lce_tr_resp_i[427];
assign data_mem_pkt_o[427] = lce_tr_resp_i[426];
assign data_mem_pkt_o[426] = lce_tr_resp_i[425];
assign data_mem_pkt_o[425] = lce_tr_resp_i[424];
assign data_mem_pkt_o[424] = lce_tr_resp_i[423];
assign data_mem_pkt_o[423] = lce_tr_resp_i[422];
assign data_mem_pkt_o[422] = lce_tr_resp_i[421];
assign data_mem_pkt_o[421] = lce_tr_resp_i[420];
assign data_mem_pkt_o[420] = lce_tr_resp_i[419];
assign data_mem_pkt_o[419] = lce_tr_resp_i[418];
assign data_mem_pkt_o[418] = lce_tr_resp_i[417];
assign data_mem_pkt_o[417] = lce_tr_resp_i[416];
assign data_mem_pkt_o[416] = lce_tr_resp_i[415];
assign data_mem_pkt_o[415] = lce_tr_resp_i[414];
assign data_mem_pkt_o[414] = lce_tr_resp_i[413];
assign data_mem_pkt_o[413] = lce_tr_resp_i[412];
assign data_mem_pkt_o[412] = lce_tr_resp_i[411];
assign data_mem_pkt_o[411] = lce_tr_resp_i[410];
assign data_mem_pkt_o[410] = lce_tr_resp_i[409];
assign data_mem_pkt_o[409] = lce_tr_resp_i[408];
assign data_mem_pkt_o[408] = lce_tr_resp_i[407];
assign data_mem_pkt_o[407] = lce_tr_resp_i[406];
assign data_mem_pkt_o[406] = lce_tr_resp_i[405];
assign data_mem_pkt_o[405] = lce_tr_resp_i[404];
assign data_mem_pkt_o[404] = lce_tr_resp_i[403];
assign data_mem_pkt_o[403] = lce_tr_resp_i[402];
assign data_mem_pkt_o[402] = lce_tr_resp_i[401];
assign data_mem_pkt_o[401] = lce_tr_resp_i[400];
assign data_mem_pkt_o[400] = lce_tr_resp_i[399];
assign data_mem_pkt_o[399] = lce_tr_resp_i[398];
assign data_mem_pkt_o[398] = lce_tr_resp_i[397];
assign data_mem_pkt_o[397] = lce_tr_resp_i[396];
assign data_mem_pkt_o[396] = lce_tr_resp_i[395];
assign data_mem_pkt_o[395] = lce_tr_resp_i[394];
assign data_mem_pkt_o[394] = lce_tr_resp_i[393];
assign data_mem_pkt_o[393] = lce_tr_resp_i[392];
assign data_mem_pkt_o[392] = lce_tr_resp_i[391];
assign data_mem_pkt_o[391] = lce_tr_resp_i[390];
assign data_mem_pkt_o[390] = lce_tr_resp_i[389];
assign data_mem_pkt_o[389] = lce_tr_resp_i[388];
assign data_mem_pkt_o[388] = lce_tr_resp_i[387];
assign data_mem_pkt_o[387] = lce_tr_resp_i[386];
assign data_mem_pkt_o[386] = lce_tr_resp_i[385];
assign data_mem_pkt_o[385] = lce_tr_resp_i[384];
assign data_mem_pkt_o[384] = lce_tr_resp_i[383];
assign data_mem_pkt_o[383] = lce_tr_resp_i[382];
assign data_mem_pkt_o[382] = lce_tr_resp_i[381];
assign data_mem_pkt_o[381] = lce_tr_resp_i[380];
assign data_mem_pkt_o[380] = lce_tr_resp_i[379];
assign data_mem_pkt_o[379] = lce_tr_resp_i[378];
assign data_mem_pkt_o[378] = lce_tr_resp_i[377];
assign data_mem_pkt_o[377] = lce_tr_resp_i[376];
assign data_mem_pkt_o[376] = lce_tr_resp_i[375];
assign data_mem_pkt_o[375] = lce_tr_resp_i[374];
assign data_mem_pkt_o[374] = lce_tr_resp_i[373];
assign data_mem_pkt_o[373] = lce_tr_resp_i[372];
assign data_mem_pkt_o[372] = lce_tr_resp_i[371];
assign data_mem_pkt_o[371] = lce_tr_resp_i[370];
assign data_mem_pkt_o[370] = lce_tr_resp_i[369];
assign data_mem_pkt_o[369] = lce_tr_resp_i[368];
assign data_mem_pkt_o[368] = lce_tr_resp_i[367];
assign data_mem_pkt_o[367] = lce_tr_resp_i[366];
assign data_mem_pkt_o[366] = lce_tr_resp_i[365];
assign data_mem_pkt_o[365] = lce_tr_resp_i[364];
assign data_mem_pkt_o[364] = lce_tr_resp_i[363];
assign data_mem_pkt_o[363] = lce_tr_resp_i[362];
assign data_mem_pkt_o[362] = lce_tr_resp_i[361];
assign data_mem_pkt_o[361] = lce_tr_resp_i[360];
assign data_mem_pkt_o[360] = lce_tr_resp_i[359];
assign data_mem_pkt_o[359] = lce_tr_resp_i[358];
assign data_mem_pkt_o[358] = lce_tr_resp_i[357];
assign data_mem_pkt_o[357] = lce_tr_resp_i[356];
assign data_mem_pkt_o[356] = lce_tr_resp_i[355];
assign data_mem_pkt_o[355] = lce_tr_resp_i[354];
assign data_mem_pkt_o[354] = lce_tr_resp_i[353];
assign data_mem_pkt_o[353] = lce_tr_resp_i[352];
assign data_mem_pkt_o[352] = lce_tr_resp_i[351];
assign data_mem_pkt_o[351] = lce_tr_resp_i[350];
assign data_mem_pkt_o[350] = lce_tr_resp_i[349];
assign data_mem_pkt_o[349] = lce_tr_resp_i[348];
assign data_mem_pkt_o[348] = lce_tr_resp_i[347];
assign data_mem_pkt_o[347] = lce_tr_resp_i[346];
assign data_mem_pkt_o[346] = lce_tr_resp_i[345];
assign data_mem_pkt_o[345] = lce_tr_resp_i[344];
assign data_mem_pkt_o[344] = lce_tr_resp_i[343];
assign data_mem_pkt_o[343] = lce_tr_resp_i[342];
assign data_mem_pkt_o[342] = lce_tr_resp_i[341];
assign data_mem_pkt_o[341] = lce_tr_resp_i[340];
assign data_mem_pkt_o[340] = lce_tr_resp_i[339];
assign data_mem_pkt_o[339] = lce_tr_resp_i[338];
assign data_mem_pkt_o[338] = lce_tr_resp_i[337];
assign data_mem_pkt_o[337] = lce_tr_resp_i[336];
assign data_mem_pkt_o[336] = lce_tr_resp_i[335];
assign data_mem_pkt_o[335] = lce_tr_resp_i[334];
assign data_mem_pkt_o[334] = lce_tr_resp_i[333];
assign data_mem_pkt_o[333] = lce_tr_resp_i[332];
assign data_mem_pkt_o[332] = lce_tr_resp_i[331];
assign data_mem_pkt_o[331] = lce_tr_resp_i[330];
assign data_mem_pkt_o[330] = lce_tr_resp_i[329];
assign data_mem_pkt_o[329] = lce_tr_resp_i[328];
assign data_mem_pkt_o[328] = lce_tr_resp_i[327];
assign data_mem_pkt_o[327] = lce_tr_resp_i[326];
assign data_mem_pkt_o[326] = lce_tr_resp_i[325];
assign data_mem_pkt_o[325] = lce_tr_resp_i[324];
assign data_mem_pkt_o[324] = lce_tr_resp_i[323];
assign data_mem_pkt_o[323] = lce_tr_resp_i[322];
assign data_mem_pkt_o[322] = lce_tr_resp_i[321];
assign data_mem_pkt_o[321] = lce_tr_resp_i[320];
assign data_mem_pkt_o[320] = lce_tr_resp_i[319];
assign data_mem_pkt_o[319] = lce_tr_resp_i[318];
assign data_mem_pkt_o[318] = lce_tr_resp_i[317];
assign data_mem_pkt_o[317] = lce_tr_resp_i[316];
assign data_mem_pkt_o[316] = lce_tr_resp_i[315];
assign data_mem_pkt_o[315] = lce_tr_resp_i[314];
assign data_mem_pkt_o[314] = lce_tr_resp_i[313];
assign data_mem_pkt_o[313] = lce_tr_resp_i[312];
assign data_mem_pkt_o[312] = lce_tr_resp_i[311];
assign data_mem_pkt_o[311] = lce_tr_resp_i[310];
assign data_mem_pkt_o[310] = lce_tr_resp_i[309];
assign data_mem_pkt_o[309] = lce_tr_resp_i[308];
assign data_mem_pkt_o[308] = lce_tr_resp_i[307];
assign data_mem_pkt_o[307] = lce_tr_resp_i[306];
assign data_mem_pkt_o[306] = lce_tr_resp_i[305];
assign data_mem_pkt_o[305] = lce_tr_resp_i[304];
assign data_mem_pkt_o[304] = lce_tr_resp_i[303];
assign data_mem_pkt_o[303] = lce_tr_resp_i[302];
assign data_mem_pkt_o[302] = lce_tr_resp_i[301];
assign data_mem_pkt_o[301] = lce_tr_resp_i[300];
assign data_mem_pkt_o[300] = lce_tr_resp_i[299];
assign data_mem_pkt_o[299] = lce_tr_resp_i[298];
assign data_mem_pkt_o[298] = lce_tr_resp_i[297];
assign data_mem_pkt_o[297] = lce_tr_resp_i[296];
assign data_mem_pkt_o[296] = lce_tr_resp_i[295];
assign data_mem_pkt_o[295] = lce_tr_resp_i[294];
assign data_mem_pkt_o[294] = lce_tr_resp_i[293];
assign data_mem_pkt_o[293] = lce_tr_resp_i[292];
assign data_mem_pkt_o[292] = lce_tr_resp_i[291];
assign data_mem_pkt_o[291] = lce_tr_resp_i[290];
assign data_mem_pkt_o[290] = lce_tr_resp_i[289];
assign data_mem_pkt_o[289] = lce_tr_resp_i[288];
assign data_mem_pkt_o[288] = lce_tr_resp_i[287];
assign data_mem_pkt_o[287] = lce_tr_resp_i[286];
assign data_mem_pkt_o[286] = lce_tr_resp_i[285];
assign data_mem_pkt_o[285] = lce_tr_resp_i[284];
assign data_mem_pkt_o[284] = lce_tr_resp_i[283];
assign data_mem_pkt_o[283] = lce_tr_resp_i[282];
assign data_mem_pkt_o[282] = lce_tr_resp_i[281];
assign data_mem_pkt_o[281] = lce_tr_resp_i[280];
assign data_mem_pkt_o[280] = lce_tr_resp_i[279];
assign data_mem_pkt_o[279] = lce_tr_resp_i[278];
assign data_mem_pkt_o[278] = lce_tr_resp_i[277];
assign data_mem_pkt_o[277] = lce_tr_resp_i[276];
assign data_mem_pkt_o[276] = lce_tr_resp_i[275];
assign data_mem_pkt_o[275] = lce_tr_resp_i[274];
assign data_mem_pkt_o[274] = lce_tr_resp_i[273];
assign data_mem_pkt_o[273] = lce_tr_resp_i[272];
assign data_mem_pkt_o[272] = lce_tr_resp_i[271];
assign data_mem_pkt_o[271] = lce_tr_resp_i[270];
assign data_mem_pkt_o[270] = lce_tr_resp_i[269];
assign data_mem_pkt_o[269] = lce_tr_resp_i[268];
assign data_mem_pkt_o[268] = lce_tr_resp_i[267];
assign data_mem_pkt_o[267] = lce_tr_resp_i[266];
assign data_mem_pkt_o[266] = lce_tr_resp_i[265];
assign data_mem_pkt_o[265] = lce_tr_resp_i[264];
assign data_mem_pkt_o[264] = lce_tr_resp_i[263];
assign data_mem_pkt_o[263] = lce_tr_resp_i[262];
assign data_mem_pkt_o[262] = lce_tr_resp_i[261];
assign data_mem_pkt_o[261] = lce_tr_resp_i[260];
assign data_mem_pkt_o[260] = lce_tr_resp_i[259];
assign data_mem_pkt_o[259] = lce_tr_resp_i[258];
assign data_mem_pkt_o[258] = lce_tr_resp_i[257];
assign data_mem_pkt_o[257] = lce_tr_resp_i[256];
assign data_mem_pkt_o[256] = lce_tr_resp_i[255];
assign data_mem_pkt_o[255] = lce_tr_resp_i[254];
assign data_mem_pkt_o[254] = lce_tr_resp_i[253];
assign data_mem_pkt_o[253] = lce_tr_resp_i[252];
assign data_mem_pkt_o[252] = lce_tr_resp_i[251];
assign data_mem_pkt_o[251] = lce_tr_resp_i[250];
assign data_mem_pkt_o[250] = lce_tr_resp_i[249];
assign data_mem_pkt_o[249] = lce_tr_resp_i[248];
assign data_mem_pkt_o[248] = lce_tr_resp_i[247];
assign data_mem_pkt_o[247] = lce_tr_resp_i[246];
assign data_mem_pkt_o[246] = lce_tr_resp_i[245];
assign data_mem_pkt_o[245] = lce_tr_resp_i[244];
assign data_mem_pkt_o[244] = lce_tr_resp_i[243];
assign data_mem_pkt_o[243] = lce_tr_resp_i[242];
assign data_mem_pkt_o[242] = lce_tr_resp_i[241];
assign data_mem_pkt_o[241] = lce_tr_resp_i[240];
assign data_mem_pkt_o[240] = lce_tr_resp_i[239];
assign data_mem_pkt_o[239] = lce_tr_resp_i[238];
assign data_mem_pkt_o[238] = lce_tr_resp_i[237];
assign data_mem_pkt_o[237] = lce_tr_resp_i[236];
assign data_mem_pkt_o[236] = lce_tr_resp_i[235];
assign data_mem_pkt_o[235] = lce_tr_resp_i[234];
assign data_mem_pkt_o[234] = lce_tr_resp_i[233];
assign data_mem_pkt_o[233] = lce_tr_resp_i[232];
assign data_mem_pkt_o[232] = lce_tr_resp_i[231];
assign data_mem_pkt_o[231] = lce_tr_resp_i[230];
assign data_mem_pkt_o[230] = lce_tr_resp_i[229];
assign data_mem_pkt_o[229] = lce_tr_resp_i[228];
assign data_mem_pkt_o[228] = lce_tr_resp_i[227];
assign data_mem_pkt_o[227] = lce_tr_resp_i[226];
assign data_mem_pkt_o[226] = lce_tr_resp_i[225];
assign data_mem_pkt_o[225] = lce_tr_resp_i[224];
assign data_mem_pkt_o[224] = lce_tr_resp_i[223];
assign data_mem_pkt_o[223] = lce_tr_resp_i[222];
assign data_mem_pkt_o[222] = lce_tr_resp_i[221];
assign data_mem_pkt_o[221] = lce_tr_resp_i[220];
assign data_mem_pkt_o[220] = lce_tr_resp_i[219];
assign data_mem_pkt_o[219] = lce_tr_resp_i[218];
assign data_mem_pkt_o[218] = lce_tr_resp_i[217];
assign data_mem_pkt_o[217] = lce_tr_resp_i[216];
assign data_mem_pkt_o[216] = lce_tr_resp_i[215];
assign data_mem_pkt_o[215] = lce_tr_resp_i[214];
assign data_mem_pkt_o[214] = lce_tr_resp_i[213];
assign data_mem_pkt_o[213] = lce_tr_resp_i[212];
assign data_mem_pkt_o[212] = lce_tr_resp_i[211];
assign data_mem_pkt_o[211] = lce_tr_resp_i[210];
assign data_mem_pkt_o[210] = lce_tr_resp_i[209];
assign data_mem_pkt_o[209] = lce_tr_resp_i[208];
assign data_mem_pkt_o[208] = lce_tr_resp_i[207];
assign data_mem_pkt_o[207] = lce_tr_resp_i[206];
assign data_mem_pkt_o[206] = lce_tr_resp_i[205];
assign data_mem_pkt_o[205] = lce_tr_resp_i[204];
assign data_mem_pkt_o[204] = lce_tr_resp_i[203];
assign data_mem_pkt_o[203] = lce_tr_resp_i[202];
assign data_mem_pkt_o[202] = lce_tr_resp_i[201];
assign data_mem_pkt_o[201] = lce_tr_resp_i[200];
assign data_mem_pkt_o[200] = lce_tr_resp_i[199];
assign data_mem_pkt_o[199] = lce_tr_resp_i[198];
assign data_mem_pkt_o[198] = lce_tr_resp_i[197];
assign data_mem_pkt_o[197] = lce_tr_resp_i[196];
assign data_mem_pkt_o[196] = lce_tr_resp_i[195];
assign data_mem_pkt_o[195] = lce_tr_resp_i[194];
assign data_mem_pkt_o[194] = lce_tr_resp_i[193];
assign data_mem_pkt_o[193] = lce_tr_resp_i[192];
assign data_mem_pkt_o[192] = lce_tr_resp_i[191];
assign data_mem_pkt_o[191] = lce_tr_resp_i[190];
assign data_mem_pkt_o[190] = lce_tr_resp_i[189];
assign data_mem_pkt_o[189] = lce_tr_resp_i[188];
assign data_mem_pkt_o[188] = lce_tr_resp_i[187];
assign data_mem_pkt_o[187] = lce_tr_resp_i[186];
assign data_mem_pkt_o[186] = lce_tr_resp_i[185];
assign data_mem_pkt_o[185] = lce_tr_resp_i[184];
assign data_mem_pkt_o[184] = lce_tr_resp_i[183];
assign data_mem_pkt_o[183] = lce_tr_resp_i[182];
assign data_mem_pkt_o[182] = lce_tr_resp_i[181];
assign data_mem_pkt_o[181] = lce_tr_resp_i[180];
assign data_mem_pkt_o[180] = lce_tr_resp_i[179];
assign data_mem_pkt_o[179] = lce_tr_resp_i[178];
assign data_mem_pkt_o[178] = lce_tr_resp_i[177];
assign data_mem_pkt_o[177] = lce_tr_resp_i[176];
assign data_mem_pkt_o[176] = lce_tr_resp_i[175];
assign data_mem_pkt_o[175] = lce_tr_resp_i[174];
assign data_mem_pkt_o[174] = lce_tr_resp_i[173];
assign data_mem_pkt_o[173] = lce_tr_resp_i[172];
assign data_mem_pkt_o[172] = lce_tr_resp_i[171];
assign data_mem_pkt_o[171] = lce_tr_resp_i[170];
assign data_mem_pkt_o[170] = lce_tr_resp_i[169];
assign data_mem_pkt_o[169] = lce_tr_resp_i[168];
assign data_mem_pkt_o[168] = lce_tr_resp_i[167];
assign data_mem_pkt_o[167] = lce_tr_resp_i[166];
assign data_mem_pkt_o[166] = lce_tr_resp_i[165];
assign data_mem_pkt_o[165] = lce_tr_resp_i[164];
assign data_mem_pkt_o[164] = lce_tr_resp_i[163];
assign data_mem_pkt_o[163] = lce_tr_resp_i[162];
assign data_mem_pkt_o[162] = lce_tr_resp_i[161];
assign data_mem_pkt_o[161] = lce_tr_resp_i[160];
assign data_mem_pkt_o[160] = lce_tr_resp_i[159];
assign data_mem_pkt_o[159] = lce_tr_resp_i[158];
assign data_mem_pkt_o[158] = lce_tr_resp_i[157];
assign data_mem_pkt_o[157] = lce_tr_resp_i[156];
assign data_mem_pkt_o[156] = lce_tr_resp_i[155];
assign data_mem_pkt_o[155] = lce_tr_resp_i[154];
assign data_mem_pkt_o[154] = lce_tr_resp_i[153];
assign data_mem_pkt_o[153] = lce_tr_resp_i[152];
assign data_mem_pkt_o[152] = lce_tr_resp_i[151];
assign data_mem_pkt_o[151] = lce_tr_resp_i[150];
assign data_mem_pkt_o[150] = lce_tr_resp_i[149];
assign data_mem_pkt_o[149] = lce_tr_resp_i[148];
assign data_mem_pkt_o[148] = lce_tr_resp_i[147];
assign data_mem_pkt_o[147] = lce_tr_resp_i[146];
assign data_mem_pkt_o[146] = lce_tr_resp_i[145];
assign data_mem_pkt_o[145] = lce_tr_resp_i[144];
assign data_mem_pkt_o[144] = lce_tr_resp_i[143];
assign data_mem_pkt_o[143] = lce_tr_resp_i[142];
assign data_mem_pkt_o[142] = lce_tr_resp_i[141];
assign data_mem_pkt_o[141] = lce_tr_resp_i[140];
assign data_mem_pkt_o[140] = lce_tr_resp_i[139];
assign data_mem_pkt_o[139] = lce_tr_resp_i[138];
assign data_mem_pkt_o[138] = lce_tr_resp_i[137];
assign data_mem_pkt_o[137] = lce_tr_resp_i[136];
assign data_mem_pkt_o[136] = lce_tr_resp_i[135];
assign data_mem_pkt_o[135] = lce_tr_resp_i[134];
assign data_mem_pkt_o[134] = lce_tr_resp_i[133];
assign data_mem_pkt_o[133] = lce_tr_resp_i[132];
assign data_mem_pkt_o[132] = lce_tr_resp_i[131];
assign data_mem_pkt_o[131] = lce_tr_resp_i[130];
assign data_mem_pkt_o[130] = lce_tr_resp_i[129];
assign data_mem_pkt_o[129] = lce_tr_resp_i[128];
assign data_mem_pkt_o[128] = lce_tr_resp_i[127];
assign data_mem_pkt_o[127] = lce_tr_resp_i[126];
assign data_mem_pkt_o[126] = lce_tr_resp_i[125];
assign data_mem_pkt_o[125] = lce_tr_resp_i[124];
assign data_mem_pkt_o[124] = lce_tr_resp_i[123];
assign data_mem_pkt_o[123] = lce_tr_resp_i[122];
assign data_mem_pkt_o[122] = lce_tr_resp_i[121];
assign data_mem_pkt_o[121] = lce_tr_resp_i[120];
assign data_mem_pkt_o[120] = lce_tr_resp_i[119];
assign data_mem_pkt_o[119] = lce_tr_resp_i[118];
assign data_mem_pkt_o[118] = lce_tr_resp_i[117];
assign data_mem_pkt_o[117] = lce_tr_resp_i[116];
assign data_mem_pkt_o[116] = lce_tr_resp_i[115];
assign data_mem_pkt_o[115] = lce_tr_resp_i[114];
assign data_mem_pkt_o[114] = lce_tr_resp_i[113];
assign data_mem_pkt_o[113] = lce_tr_resp_i[112];
assign data_mem_pkt_o[112] = lce_tr_resp_i[111];
assign data_mem_pkt_o[111] = lce_tr_resp_i[110];
assign data_mem_pkt_o[110] = lce_tr_resp_i[109];
assign data_mem_pkt_o[109] = lce_tr_resp_i[108];
assign data_mem_pkt_o[108] = lce_tr_resp_i[107];
assign data_mem_pkt_o[107] = lce_tr_resp_i[106];
assign data_mem_pkt_o[106] = lce_tr_resp_i[105];
assign data_mem_pkt_o[105] = lce_tr_resp_i[104];
assign data_mem_pkt_o[104] = lce_tr_resp_i[103];
assign data_mem_pkt_o[103] = lce_tr_resp_i[102];
assign data_mem_pkt_o[102] = lce_tr_resp_i[101];
assign data_mem_pkt_o[101] = lce_tr_resp_i[100];
assign data_mem_pkt_o[100] = lce_tr_resp_i[99];
assign data_mem_pkt_o[99] = lce_tr_resp_i[98];
assign data_mem_pkt_o[98] = lce_tr_resp_i[97];
assign data_mem_pkt_o[97] = lce_tr_resp_i[96];
assign data_mem_pkt_o[96] = lce_tr_resp_i[95];
assign data_mem_pkt_o[95] = lce_tr_resp_i[94];
assign data_mem_pkt_o[94] = lce_tr_resp_i[93];
assign data_mem_pkt_o[93] = lce_tr_resp_i[92];
assign data_mem_pkt_o[92] = lce_tr_resp_i[91];
assign data_mem_pkt_o[91] = lce_tr_resp_i[90];
assign data_mem_pkt_o[90] = lce_tr_resp_i[89];
assign data_mem_pkt_o[89] = lce_tr_resp_i[88];
assign data_mem_pkt_o[88] = lce_tr_resp_i[87];
assign data_mem_pkt_o[87] = lce_tr_resp_i[86];
assign data_mem_pkt_o[86] = lce_tr_resp_i[85];
assign data_mem_pkt_o[85] = lce_tr_resp_i[84];
assign data_mem_pkt_o[84] = lce_tr_resp_i[83];
assign data_mem_pkt_o[83] = lce_tr_resp_i[82];
assign data_mem_pkt_o[82] = lce_tr_resp_i[81];
assign data_mem_pkt_o[81] = lce_tr_resp_i[80];
assign data_mem_pkt_o[80] = lce_tr_resp_i[79];
assign data_mem_pkt_o[79] = lce_tr_resp_i[78];
assign data_mem_pkt_o[78] = lce_tr_resp_i[77];
assign data_mem_pkt_o[77] = lce_tr_resp_i[76];
assign data_mem_pkt_o[76] = lce_tr_resp_i[75];
assign data_mem_pkt_o[75] = lce_tr_resp_i[74];
assign data_mem_pkt_o[74] = lce_tr_resp_i[73];
assign data_mem_pkt_o[73] = lce_tr_resp_i[72];
assign data_mem_pkt_o[72] = lce_tr_resp_i[71];
assign data_mem_pkt_o[71] = lce_tr_resp_i[70];
assign data_mem_pkt_o[70] = lce_tr_resp_i[69];
assign data_mem_pkt_o[69] = lce_tr_resp_i[68];
assign data_mem_pkt_o[68] = lce_tr_resp_i[67];
assign data_mem_pkt_o[67] = lce_tr_resp_i[66];
assign data_mem_pkt_o[66] = lce_tr_resp_i[65];
assign data_mem_pkt_o[65] = lce_tr_resp_i[64];
assign data_mem_pkt_o[64] = lce_tr_resp_i[63];
assign data_mem_pkt_o[63] = lce_tr_resp_i[62];
assign data_mem_pkt_o[62] = lce_tr_resp_i[61];
assign data_mem_pkt_o[61] = lce_tr_resp_i[60];
assign data_mem_pkt_o[60] = lce_tr_resp_i[59];
assign data_mem_pkt_o[59] = lce_tr_resp_i[58];
assign data_mem_pkt_o[58] = lce_tr_resp_i[57];
assign data_mem_pkt_o[57] = lce_tr_resp_i[56];
assign data_mem_pkt_o[56] = lce_tr_resp_i[55];
assign data_mem_pkt_o[55] = lce_tr_resp_i[54];
assign data_mem_pkt_o[54] = lce_tr_resp_i[53];
assign data_mem_pkt_o[53] = lce_tr_resp_i[52];
assign data_mem_pkt_o[52] = lce_tr_resp_i[51];
assign data_mem_pkt_o[51] = lce_tr_resp_i[50];
assign data_mem_pkt_o[50] = lce_tr_resp_i[49];
assign data_mem_pkt_o[49] = lce_tr_resp_i[48];
assign data_mem_pkt_o[48] = lce_tr_resp_i[47];
assign data_mem_pkt_o[47] = lce_tr_resp_i[46];
assign data_mem_pkt_o[46] = lce_tr_resp_i[45];
assign data_mem_pkt_o[45] = lce_tr_resp_i[44];
assign data_mem_pkt_o[44] = lce_tr_resp_i[43];
assign data_mem_pkt_o[43] = lce_tr_resp_i[42];
assign data_mem_pkt_o[42] = lce_tr_resp_i[41];
assign data_mem_pkt_o[41] = lce_tr_resp_i[40];
assign data_mem_pkt_o[40] = lce_tr_resp_i[39];
assign data_mem_pkt_o[39] = lce_tr_resp_i[38];
assign data_mem_pkt_o[38] = lce_tr_resp_i[37];
assign data_mem_pkt_o[37] = lce_tr_resp_i[36];
assign data_mem_pkt_o[36] = lce_tr_resp_i[35];
assign data_mem_pkt_o[35] = lce_tr_resp_i[34];
assign data_mem_pkt_o[34] = lce_tr_resp_i[33];
assign data_mem_pkt_o[33] = lce_tr_resp_i[32];
assign data_mem_pkt_o[32] = lce_tr_resp_i[31];
assign data_mem_pkt_o[31] = lce_tr_resp_i[30];
assign data_mem_pkt_o[30] = lce_tr_resp_i[29];
assign data_mem_pkt_o[29] = lce_tr_resp_i[28];
assign data_mem_pkt_o[28] = lce_tr_resp_i[27];
assign data_mem_pkt_o[27] = lce_tr_resp_i[26];
assign data_mem_pkt_o[26] = lce_tr_resp_i[25];
assign data_mem_pkt_o[25] = lce_tr_resp_i[24];
assign data_mem_pkt_o[24] = lce_tr_resp_i[23];
assign data_mem_pkt_o[23] = lce_tr_resp_i[22];
assign data_mem_pkt_o[22] = lce_tr_resp_i[21];
assign data_mem_pkt_o[21] = lce_tr_resp_i[20];
assign data_mem_pkt_o[20] = lce_tr_resp_i[19];
assign data_mem_pkt_o[19] = lce_tr_resp_i[18];
assign data_mem_pkt_o[18] = lce_tr_resp_i[17];
assign data_mem_pkt_o[17] = lce_tr_resp_i[16];
assign data_mem_pkt_o[16] = lce_tr_resp_i[15];
assign data_mem_pkt_o[15] = lce_tr_resp_i[14];
assign data_mem_pkt_o[14] = lce_tr_resp_i[13];
assign data_mem_pkt_o[13] = lce_tr_resp_i[12];
assign data_mem_pkt_o[12] = lce_tr_resp_i[11];
assign data_mem_pkt_o[11] = lce_tr_resp_i[10];
assign data_mem_pkt_o[10] = lce_tr_resp_i[9];
assign data_mem_pkt_o[9] = lce_tr_resp_i[8];
assign data_mem_pkt_o[8] = lce_tr_resp_i[7];
assign data_mem_pkt_o[7] = lce_tr_resp_i[6];
assign data_mem_pkt_o[6] = lce_tr_resp_i[5];
assign data_mem_pkt_o[5] = lce_tr_resp_i[4];
assign data_mem_pkt_o[4] = lce_tr_resp_i[3];
assign data_mem_pkt_o[3] = lce_tr_resp_i[2];
assign data_mem_pkt_o[2] = lce_tr_resp_i[1];
assign data_mem_pkt_o[1] = lce_tr_resp_i[0];
endmodule
|
module bp_be_dcache_lru_decode_ways_p8
(
way_id_i,
data_o,
mask_o
);
input [2:0] way_id_i;
output [6:0] data_o;
output [6:0] mask_o;
wire [6:0] data_o,mask_o;
wire N0,N1,N2,N3,N4,N5,N6,N7,N8,N9,N10,N11,N12,N13,N14,N15,N16,N17,N18,N19,N20,N21,
N22,N23,N24,N25,N26,N27,N28,N29,N30;
assign mask_o[0] = 1'b1;
assign N11 = N8 & N9;
assign N12 = N11 & N10;
assign N13 = way_id_i[2] | way_id_i[1];
assign N14 = N13 | N10;
assign N16 = way_id_i[2] | N9;
assign N17 = N16 | way_id_i[0];
assign N19 = N16 | N10;
assign N21 = N8 | way_id_i[1];
assign N22 = N21 | way_id_i[0];
assign N24 = N21 | N10;
assign N26 = N8 | N9;
assign N27 = N26 | way_id_i[0];
assign N29 = way_id_i[2] & way_id_i[1];
assign N30 = N29 & way_id_i[0];
assign data_o = (N0)? { 1'b0, 1'b0, 1'b0, 1'b1, 1'b0, 1'b1, 1'b1 } :
(N1)? { 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b1, 1'b1 } :
(N2)? { 1'b0, 1'b0, 1'b1, 1'b0, 1'b0, 1'b0, 1'b1 } :
(N3)? { 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b1 } :
(N4)? { 1'b0, 1'b1, 1'b0, 1'b0, 1'b1, 1'b0, 1'b0 } :
(N5)? { 1'b0, 1'b0, 1'b0, 1'b0, 1'b1, 1'b0, 1'b0 } :
(N6)? { 1'b1, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0 } :
(N7)? { 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0 } : 1'b0;
assign N0 = N12;
assign N1 = N15;
assign N2 = N18;
assign N3 = N20;
assign N4 = N23;
assign N5 = N25;
assign N6 = N28;
assign N7 = N30;
assign mask_o[6:1] = (N0)? { 1'b0, 1'b0, 1'b0, 1'b1, 1'b0, 1'b1 } :
(N1)? { 1'b0, 1'b0, 1'b0, 1'b1, 1'b0, 1'b1 } :
(N2)? { 1'b0, 1'b0, 1'b1, 1'b0, 1'b0, 1'b1 } :
(N3)? { 1'b0, 1'b0, 1'b1, 1'b0, 1'b0, 1'b1 } :
(N4)? { 1'b0, 1'b1, 1'b0, 1'b0, 1'b1, 1'b0 } :
(N5)? { 1'b0, 1'b1, 1'b0, 1'b0, 1'b1, 1'b0 } :
(N6)? { 1'b1, 1'b0, 1'b0, 1'b0, 1'b1, 1'b0 } :
(N7)? { 1'b1, 1'b0, 1'b0, 1'b0, 1'b1, 1'b0 } : 1'b0;
assign N8 = ~way_id_i[2];
assign N9 = ~way_id_i[1];
assign N10 = ~way_id_i[0];
assign N15 = ~N14;
assign N18 = ~N17;
assign N20 = ~N19;
assign N23 = ~N22;
assign N25 = ~N24;
assign N28 = ~N27;
endmodule
|
module bsg_dff_reset_en_64_80000124
(
clk_i,
reset_i,
en_i,
data_i,
data_o
);
input [63:0] data_i;
output [63:0] data_o;
input clk_i;
input reset_i;
input en_i;
wire N0,N1,N2,N3,N4,N5,N6,N7,N8,N9,N10,N11,N12,N13,N14,N15,N16,N17,N18,N19,N20,N21,
N22,N23,N24,N25,N26,N27,N28,N29,N30,N31,N32,N33,N34,N35,N36,N37,N38,N39,N40,N41,
N42,N43,N44,N45,N46,N47,N48,N49,N50,N51,N52,N53,N54,N55,N56,N57,N58,N59,N60,N61,
N62,N63,N64,N65,N66,N67,N68,N69;
reg [63:0] data_o;
assign N3 = (N0)? 1'b1 :
(N69)? 1'b1 :
(N2)? 1'b0 : 1'b0;
assign N0 = reset_i;
assign { N67, N66, N65, N64, N63, N62, N61, N60, N59, N58, N57, N56, N55, N54, N53, N52, N51, N50, N49, N48, N47, N46, N45, N44, N43, N42, N41, N40, N39, N38, N37, N36, N35, N34, N33, N32, N31, N30, N29, N28, N27, N26, N25, N24, N23, N22, N21, N20, N19, N18, N17, N16, N15, N14, N13, N12, N11, N10, N9, N8, N7, N6, N5, N4 } = (N0)? { 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b1, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b1, 1'b0, 1'b0, 1'b1, 1'b0, 1'b0, 1'b1, 1'b0, 1'b0 } :
(N69)? data_i : 1'b0;
assign N1 = en_i | reset_i;
assign N2 = ~N1;
assign N68 = ~reset_i;
assign N69 = en_i & N68;
always @(posedge clk_i) begin
if(N3) begin
{ data_o[63:0] } <= { N67, N66, N65, N64, N63, N62, N61, N60, N59, N58, N57, N56, N55, N54, N53, N52, N51, N50, N49, N48, N47, N46, N45, N44, N43, N42, N41, N40, N39, N38, N37, N36, N35, N34, N33, N32, N31, N30, N29, N28, N27, N26, N25, N24, N23, N22, N21, N20, N19, N18, N17, N16, N15, N14, N13, N12, N11, N10, N9, N8, N7, N6, N5, N4 };
end
end
endmodule
|
module bp_cce_alu_width_p16
(
v_i,
opd_a_i,
opd_b_i,
alu_op_i,
v_o,
res_o,
branch_res_o
);
input [15:0] opd_a_i;
input [15:0] opd_b_i;
input [2:0] alu_op_i;
output [15:0] res_o;
input v_i;
output v_o;
output branch_res_o;
wire [15:0] res_o;
wire v_o,branch_res_o,N0,N1,N2,N3,N4,N5,N6,N7,N8,N9,N10,v_i,equal,less,N11,N12,N13,
N14,N15,N16,N17,N18,N19,N20,N21,N22,N23,N24,N25,N26,N27,N28,N29,N30,N31,N32,N33,
N34,N35,N36,N37,N38,N39,N40,N41,N42,N43,N44,N45,N46,N47,N48,N49,N50,N51,N52,N53,
N54,N55,N56,N57,N58,N59,N60,N61,N62,N63,N64,N65,N66,N67,N68,N69,N70,N71,N72,N73,
N74,N75,N76,N77,N78,N79,N80,N81,N82,N83,N84,N85,N86,N87,N88,N89,N90,N91,N92,N93,
N94,N95,N96,N97,N98,N99,N100,N101;
assign v_o = v_i;
assign equal = opd_a_i == opd_b_i;
assign less = opd_a_i < opd_b_i;
assign N12 = alu_op_i[2] | N28;
assign N13 = N12 | alu_op_i[0];
assign N16 = N12 | N15;
assign N18 = N27 | alu_op_i[1];
assign N19 = N18 | alu_op_i[0];
assign N21 = N18 | N15;
assign N23 = alu_op_i[2] & alu_op_i[1];
assign N24 = N23 & alu_op_i[0];
assign N25 = N27 | N28;
assign N26 = N25 | alu_op_i[0];
assign N29 = N27 & N28;
assign { N52, N51, N50, N49, N48, N47, N46, N45, N44, N43, N42, N41, N40, N39, N38, N37 } = opd_a_i + opd_b_i;
assign { N68, N67, N66, N65, N64, N63, N62, N61, N60, N59, N58, N57, N56, N55, N54, N53 } = opd_a_i - opd_b_i;
assign N33 = (N0)? equal :
(N1)? N31 :
(N2)? less :
(N3)? N32 :
(N4)? 1'b1 :
(N5)? 1'b0 : 1'b0;
assign N0 = N14;
assign N1 = N17;
assign N2 = N20;
assign N3 = N22;
assign N4 = N24;
assign N5 = N30;
assign branch_res_o = (N6)? N33 :
(N7)? 1'b0 : 1'b0;
assign N6 = v_i;
assign N7 = N11;
assign { N84, N83, N82, N81, N80, N79, N78, N77, N76, N75, N74, N73, N72, N71, N70, N69 } = (N8)? { N52, N51, N50, N49, N48, N47, N46, N45, N44, N43, N42, N41, N40, N39, N38, N37 } :
(N9)? { N68, N67, N66, N65, N64, N63, N62, N61, N60, N59, N58, N57, N56, N55, N54, N53 } : 1'b0;
assign N8 = N15;
assign N9 = alu_op_i[0];
assign { N100, N99, N98, N97, N96, N95, N94, N93, N92, N91, N90, N89, N88, N87, N86, N85 } = (N10)? { N84, N83, N82, N81, N80, N79, N78, N77, N76, N75, N74, N73, N72, N71, N70, N69 } :
(N35)? { 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0 } : 1'b0;
assign N10 = N29;
assign res_o = (N6)? { N100, N99, N98, N97, N96, N95, N94, N93, N92, N91, N90, N89, N88, N87, N86, N85 } :
(N7)? { 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0 } : 1'b0;
assign N11 = ~v_i;
assign N14 = ~N13;
assign N15 = ~alu_op_i[0];
assign N17 = ~N16;
assign N20 = ~N19;
assign N22 = ~N21;
assign N27 = ~alu_op_i[2];
assign N28 = ~alu_op_i[1];
assign N30 = N101 | N29;
assign N101 = ~N26;
assign N31 = ~equal;
assign N32 = less | equal;
assign N34 = v_i;
assign N35 = ~N29;
assign N36 = N34 & N29;
endmodule
|
module bp_be_instr_decoder
(
instr_i,
fe_nop_v_i,
be_nop_v_i,
me_nop_v_i,
decode_o,
illegal_instr_o
);
input [31:0] instr_i;
output [42:0] decode_o;
input fe_nop_v_i;
input be_nop_v_i;
input me_nop_v_i;
output illegal_instr_o;
wire [42:0] decode_o;
wire illegal_instr_o,N0,N1,N2,N3,N4,N5,N6,N7,N8,N9,N10,N11,N12,N13,N14,N15,N16,N17,
N18,N19,N20,N21,N22,N23,N24,N25,N26,N27,N28,N29,N30,N31,N32,N33,N34,N35,N36,N37,
N38,N39,N40,N41,N42,N43,N44,N45,N46,N47,N48,N49,N50,N51,N52,N53,N54,N55,N56,N57,
N58,N59,N60,N61,N62,N63,N64,N65,N66,N67,N68,N69,N70,N71,N72,N73,N74,N75,N76,N77,
N78,N79,N80,N81,N82,N83,N84,N85,N86,N87,N88,N89,N90,N91,N92,N93,N94,N95,N96,N97,
N98,N99,N100,N101,N102,N103,N104,N105,N106,N107,N108,N109,N110,N111,N112,N113,
N114,N115,N116,N117,N118,N119,N120,N121,N122,N123,N124,N125,N126,N127,N128,N129,
N130,N131,N132,N133,N134,N135,N136,N137,N138,N139,N140,N141,N142,N143,N144,N145,
N146,N147,N148,N149,N150,N151,N152,N153,N154,N155,N156,N157,N158,N159,N160,N161,
N162,N163,N164,N165,N166,N167,N168,N169,N170,N171,N172,N173,N174,N175,N176,N177,
N178,N179,N180,N181,N182,N183,N184,N185,N186,N187,N188,N189,N190,N191,N192,N193,
N194,N195,N196,N197,N198,N199,N200,N201,N202,N203,N204,N205,N206,N207,N208,N209,
N210,N211,N212,N213,N214,N215,N216,N217,N218,N219,N220,N221,N222,N223,N224,N225,
N226,N227,N228,N229,N230,N231,N232,N233,N234,N235,N236,N237,N238,N239,N240,N241,
N242,N243,N244,N245,N246,N247,N248,N249,N250,N251,N252,N253,N254,N255,N256,N257,
N258,N259,N260,N261,N262,N263,N264,N265,N266,N267,N268,N269,N270,N271,N272,N273,
N274,N275,N276,N277,N278,N279,N280,N281,N282,N283,N284,N285,N286,N287,N288,N289,
N290,N291,N292,N293,N294,N295,N296,N297,N298,N299,N300,N301,N302,N303,N304,N305,
N306,N307,N308,N309,N310,N311,N312,N313,N314,N315,N316,N317,N318,N319,N320,N321,
N322,N323,N324,N325,N326,N327,N328,N329,N330,N331,N332,N333,N334,N335,N336,N337,
N338,N339,N340,N341,N342,N343,N344,N345,N346,N347,N348,N349,N350,N351,N352,N353,
N354,N355,N356,N357,N358,N359,N360,N361,N362,N363,N364,N365,N366,N367,N368,N369,
N370,N371,N372;
assign decode_o[26] = 1'b0;
assign decode_o[27] = 1'b0;
assign decode_o[28] = 1'b0;
assign decode_o[32] = 1'b0;
assign decode_o[34] = 1'b0;
assign decode_o[36] = 1'b0;
assign N54 = instr_i[1] & instr_i[0];
assign N56 = instr_i[6] | N339;
assign N57 = N340 | instr_i[3];
assign N58 = N56 | N57;
assign N59 = N58 | instr_i[2];
assign N60 = N340 | N341;
assign N61 = N56 | N60;
assign N62 = N61 | instr_i[2];
assign N64 = instr_i[6] | instr_i[5];
assign N65 = N64 | N57;
assign N66 = N65 | instr_i[2];
assign N67 = N64 | N60;
assign N68 = N67 | instr_i[2];
assign N70 = N58 | N86;
assign N72 = N65 | N86;
assign N74 = N85 | N339;
assign N75 = instr_i[4] | N341;
assign N76 = N74 | N75;
assign N77 = N76 | N86;
assign N79 = instr_i[4] | instr_i[3];
assign N80 = N74 | N79;
assign N81 = N80 | N86;
assign N83 = N80 | instr_i[2];
assign N87 = N85 & N339;
assign N88 = N340 & N341;
assign N89 = N87 & N88;
assign N90 = N89 & N86;
assign N91 = N56 | N79;
assign N92 = N91 | instr_i[2];
assign N94 = N64 | N75;
assign N95 = N94 | N86;
assign N97 = N74 | N57;
assign N98 = N97 | instr_i[2];
assign N100 = instr_i[6] & instr_i[4];
assign N101 = N100 & instr_i[2];
assign N102 = N100 & instr_i[3];
assign N103 = instr_i[4] & instr_i[3];
assign N104 = N103 & instr_i[2];
assign N105 = N85 & instr_i[5];
assign N106 = N340 & instr_i[2];
assign N107 = N105 & N106;
assign N108 = N85 & N340;
assign N109 = N341 & instr_i[2];
assign N110 = N108 & N109;
assign N111 = N339 & N340;
assign N112 = N111 & N109;
assign N113 = N340 & instr_i[3];
assign N114 = N113 & N86;
assign N115 = instr_i[6] & N339;
assign N123 = N117 & N118;
assign N124 = N119 & N120;
assign N125 = N121 & N122;
assign N126 = instr_i[4] & N86;
assign N127 = N123 & N124;
assign N128 = N125 & N105;
assign N129 = N126 & N54;
assign N130 = N127 & N128;
assign N131 = N130 & N129;
assign N133 = N154 & N285;
assign N134 = N133 & N341;
assign N135 = N133 & instr_i[3];
assign N137 = N166 & N285;
assign N138 = N137 & N341;
assign N139 = N137 & instr_i[3];
assign N141 = N154 & N286;
assign N142 = N141 & N341;
assign N143 = N141 & instr_i[3];
assign N145 = N159 & N286;
assign N146 = N145 & N341;
assign N147 = N145 & instr_i[3];
assign N149 = N172 & N286;
assign N150 = N149 & N341;
assign N151 = N149 & instr_i[3];
assign N154 = N153 & N251;
assign N155 = N154 & N287;
assign N156 = N155 & N341;
assign N157 = N154 & N288;
assign N158 = N157 & N341;
assign N159 = N153 & instr_i[14];
assign N160 = N159 & N285;
assign N161 = N160 & N341;
assign N162 = N159 & N287;
assign N163 = N162 & N341;
assign N164 = N159 & N288;
assign N165 = N164 & N341;
assign N166 = instr_i[30] & N251;
assign N167 = N166 & instr_i[12];
assign N168 = instr_i[14] & N284;
assign N169 = N168 & instr_i[3];
assign N170 = instr_i[13] & instr_i[3];
assign N171 = instr_i[30] & instr_i[13];
assign N172 = instr_i[30] & instr_i[14];
assign N173 = N172 & N284;
assign N185 = N87 & N126;
assign N186 = N185 & N54;
assign N188 = N242 & N216;
assign N189 = N284 & instr_i[3];
assign N190 = N242 & N189;
assign N192 = N205 & N242;
assign N193 = N198 & N192;
assign N194 = N193 & N218;
assign N195 = N193 & N210;
assign N197 = N117 & N153;
assign N198 = N197 & N204;
assign N199 = N198 & N207;
assign N200 = N199 & N218;
assign N201 = N199 & N210;
assign N203 = N117 & instr_i[30];
assign N204 = N118 & N119;
assign N205 = N120 & N121;
assign N206 = N203 & N204;
assign N207 = N205 & N245;
assign N208 = N206 & N207;
assign N209 = N208 & N218;
assign N210 = instr_i[12] & instr_i[3];
assign N211 = N208 & N210;
assign N213 = N252 & N216;
assign N214 = N252 & N218;
assign N215 = N245 & N216;
assign N216 = N284 & N341;
assign N217 = N248 & N216;
assign N218 = instr_i[12] & N341;
assign N219 = N248 & N218;
assign N238 = instr_i[2] | N342;
assign N239 = N238 | N343;
assign N240 = N80 | N239;
assign N242 = N251 & N283;
assign N243 = N242 & N284;
assign N244 = N242 & instr_i[12];
assign N245 = instr_i[14] & N283;
assign N246 = N245 & N284;
assign N247 = N245 & instr_i[12];
assign N248 = instr_i[14] & instr_i[13];
assign N249 = N248 & N284;
assign N250 = N248 & instr_i[12];
assign N252 = N251 & instr_i[13];
assign N263 = N64 | N79;
assign N264 = N263 | N239;
assign N266 = N252 & N284;
assign N267 = N252 & instr_i[12];
assign N276 = N251 & N85;
assign N277 = instr_i[5] & N340;
assign N278 = N341 & N86;
assign N279 = N276 & N277;
assign N280 = N278 & N54;
assign N281 = N279 & N280;
assign N285 = N283 & N284;
assign N286 = N283 & instr_i[12];
assign N287 = instr_i[13] & N284;
assign N288 = instr_i[13] & instr_i[12];
assign N296 = N117 | N153;
assign N297 = N118 | N119;
assign N298 = instr_i[27] | instr_i[26];
assign N299 = instr_i[25] | N294;
assign N300 = instr_i[23] | N295;
assign N301 = instr_i[21] | instr_i[20];
assign N302 = N296 | N297;
assign N303 = N298 | N299;
assign N304 = N300 | N301;
assign N305 = N302 | N303;
assign N306 = N305 | N304;
assign N339 = ~instr_i[5];
assign N340 = ~instr_i[4];
assign N341 = ~instr_i[3];
assign N342 = ~instr_i[1];
assign N343 = ~instr_i[0];
assign N344 = N339 | instr_i[6];
assign N345 = N340 | N344;
assign N346 = N341 | N345;
assign N347 = instr_i[2] | N346;
assign N348 = N342 | N347;
assign N349 = N343 | N348;
assign N350 = ~N349;
assign N351 = instr_i[5] | instr_i[6];
assign N352 = N340 | N351;
assign N353 = N341 | N352;
assign N354 = instr_i[2] | N353;
assign N355 = N342 | N354;
assign N356 = N343 | N355;
assign N357 = ~N356;
assign { N178, N177, N176, N175 } = (N0)? { 1'b0, 1'b0, 1'b0, 1'b0 } :
(N1)? { 1'b1, 1'b0, 1'b0, 1'b0 } :
(N2)? { 1'b0, 1'b0, 1'b0, 1'b1 } :
(N3)? { 1'b0, 1'b1, 1'b0, 1'b1 } :
(N4)? { 1'b1, 1'b1, 1'b0, 1'b1 } :
(N5)? { 1'b0, 1'b0, 1'b1, 1'b0 } :
(N6)? { 1'b0, 1'b0, 1'b1, 1'b1 } :
(N7)? { 1'b0, 1'b1, 1'b0, 1'b0 } :
(N8)? { 1'b0, 1'b1, 1'b1, 1'b0 } :
(N9)? { 1'b0, 1'b1, 1'b1, 1'b1 } :
(N10)? { 1'b0, 1'b0, 1'b0, 1'b0 } : 1'b0;
assign N0 = N136;
assign N1 = N140;
assign N2 = N144;
assign N3 = N148;
assign N4 = N152;
assign N5 = N156;
assign N6 = N158;
assign N7 = N161;
assign N8 = N163;
assign N9 = N165;
assign N10 = N174;
assign N179 = (N0)? 1'b0 :
(N1)? 1'b0 :
(N2)? 1'b0 :
(N3)? 1'b0 :
(N4)? 1'b0 :
(N5)? 1'b0 :
(N6)? 1'b0 :
(N7)? 1'b0 :
(N8)? 1'b0 :
(N9)? 1'b0 :
(N10)? 1'b1 : 1'b0;
assign { N183, N182, N181, N180 } = (N11)? { N178, N177, N176, N175 } :
(N132)? { 1'b0, 1'b0, 1'b0, 1'b0 } : 1'b0;
assign N11 = N131;
assign N184 = (N11)? N179 :
(N132)? 1'b1 : 1'b0;
assign { N231, N230, N229 } = (N12)? { 1'b0, 1'b0, 1'b0 } :
(N13)? { 1'b0, 1'b0, 1'b1 } :
(N14)? { 1'b1, 1'b0, 1'b1 } :
(N15)? { 1'b1, 1'b0, 1'b1 } :
(N16)? { 1'b0, 1'b1, 1'b0 } :
(N17)? { 1'b0, 1'b1, 1'b1 } :
(N18)? { 1'b1, 1'b0, 1'b0 } :
(N19)? { 1'b1, 1'b1, 1'b0 } :
(N20)? { 1'b1, 1'b1, 1'b1 } :
(N228)? { 1'b0, 1'b0, 1'b0 } : 1'b0;
assign N12 = N191;
assign N13 = N196;
assign N14 = N202;
assign N15 = N212;
assign N16 = N213;
assign N17 = N214;
assign N18 = N215;
assign N19 = N217;
assign N20 = N219;
assign N232 = (N12)? 1'b0 :
(N13)? 1'b0 :
(N14)? 1'b0 :
(N15)? 1'b0 :
(N16)? 1'b0 :
(N17)? 1'b0 :
(N18)? 1'b0 :
(N19)? 1'b0 :
(N20)? 1'b0 :
(N228)? 1'b1 : 1'b0;
assign { N236, N235, N234, N233 } = (N21)? { N212, N231, N230, N229 } :
(N187)? { 1'b0, 1'b0, 1'b0, 1'b0 } : 1'b0;
assign N21 = N186;
assign N237 = (N21)? N232 :
(N187)? 1'b1 : 1'b0;
assign { N256, N255, N254, N253 } = (N22)? { 1'b1, 1'b1, 1'b0, 1'b0 } :
(N23)? { 1'b1, 1'b1, 1'b1, 1'b0 } :
(N24)? { 1'b0, 1'b0, 1'b1, 1'b0 } :
(N25)? { 1'b1, 1'b0, 1'b1, 1'b0 } :
(N26)? { 1'b0, 1'b0, 1'b1, 1'b1 } :
(N27)? { 1'b1, 1'b0, 1'b1, 1'b1 } :
(N28)? { 1'b0, 1'b0, 1'b0, 1'b0 } : 1'b0;
assign N22 = N243;
assign N23 = N244;
assign N24 = N246;
assign N25 = N247;
assign N26 = N249;
assign N27 = N250;
assign N28 = N252;
assign N257 = (N22)? 1'b0 :
(N23)? 1'b0 :
(N24)? 1'b0 :
(N25)? 1'b0 :
(N26)? 1'b0 :
(N27)? 1'b0 :
(N28)? 1'b1 : 1'b0;
assign { N261, N260, N259, N258 } = (N29)? { N256, N255, N254, N253 } :
(N30)? { 1'b0, 1'b0, 1'b0, 1'b0 } : 1'b0;
assign N29 = N241;
assign N30 = N240;
assign N262 = (N29)? N257 :
(N30)? 1'b1 : 1'b0;
assign { N270, N269, N268 } = (N22)? { 1'b0, 1'b0, 1'b0 } :
(N23)? { 1'b0, 1'b0, 1'b1 } :
(N31)? { 1'b0, 1'b1, 1'b0 } :
(N24)? { 1'b1, 1'b0, 1'b0 } :
(N25)? { 1'b1, 1'b0, 1'b1 } :
(N26)? { 1'b1, 1'b1, 1'b0 } :
(N32)? { 1'b0, 1'b1, 1'b1 } :
(N27)? { 1'b0, 1'b0, 1'b0 } : 1'b0;
assign N31 = N266;
assign N32 = N267;
assign N271 = (N22)? 1'b0 :
(N23)? 1'b0 :
(N31)? 1'b0 :
(N24)? 1'b0 :
(N25)? 1'b0 :
(N26)? 1'b0 :
(N32)? 1'b0 :
(N27)? 1'b1 : 1'b0;
assign { N274, N273, N272 } = (N33)? { N270, N269, N268 } :
(N34)? { 1'b0, 1'b0, 1'b0 } : 1'b0;
assign N33 = N265;
assign N34 = N264;
assign N275 = (N33)? N271 :
(N34)? 1'b1 : 1'b0;
assign { N290, N289 } = (N35)? { 1'b0, 1'b0 } :
(N36)? { 1'b0, 1'b1 } :
(N37)? { 1'b1, 1'b0 } :
(N38)? { 1'b1, 1'b1 } : 1'b0;
assign N35 = N285;
assign N36 = N286;
assign N37 = N287;
assign N38 = N288;
assign { N292, N291 } = (N39)? { N290, N289 } :
(N282)? { 1'b0, 1'b0 } : 1'b0;
assign N39 = N281;
assign N293 = ~N281;
assign { N319, N318, N317, N314, N313, N312, N311, N310, N309, N308 } = (N40)? { 1'b1, 1'b0, 1'b1, N350, N183, N182, N181, N180, 1'b0, 1'b0 } :
(N41)? { 1'b1, 1'b0, 1'b1, N357, N236, N235, N234, N233, 1'b1, 1'b0 } :
(N42)? { 1'b1, 1'b0, 1'b1, 1'b0, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b0 } :
(N43)? { 1'b1, 1'b0, 1'b1, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b1, 1'b0 } :
(N44)? { 1'b1, 1'b0, 1'b1, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b1 } :
(N45)? { 1'b1, 1'b0, 1'b1, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b1 } :
(N46)? { 1'b1, 1'b0, 1'b0, 1'b0, N261, N260, N259, N258, 1'b0, 1'b0 } :
(N47)? { 1'b0, 1'b1, 1'b1, 1'b0, 1'b0, N274, N273, N272, 1'b0, 1'b0 } :
(N48)? { 1'b0, 1'b1, 1'b0, 1'b0, N281, 1'b0, N292, N291, 1'b0, 1'b0 } :
(N49)? { 1'b1, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0 } :
(N50)? { 1'b1, 1'b0, N307, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0 } :
(N51)? { 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0 } : 1'b0;
assign N40 = N63;
assign N41 = N69;
assign N42 = N71;
assign N43 = N73;
assign N44 = N78;
assign N45 = N82;
assign N46 = N84;
assign N47 = N90;
assign N48 = N93;
assign N49 = N96;
assign N50 = N99;
assign N51 = N116;
assign N316 = (N50)? N307 :
(N315)? 1'b0 : 1'b0;
assign N320 = (N40)? N184 :
(N41)? N237 :
(N42)? 1'b0 :
(N43)? 1'b0 :
(N44)? 1'b0 :
(N45)? 1'b0 :
(N46)? N262 :
(N47)? N275 :
(N48)? N293 :
(N49)? 1'b0 :
(N50)? N306 :
(N51)? 1'b1 : 1'b0;
assign { N336, N335, N334, N333, N332, N331, N330, N329, N328, N327, N326, N325, N324, N323, N322, N321 } = (N52)? { N319, N318, N317, N316, N93, N90, N84, N314, N313, N312, N311, N310, N73, N309, N82, N308 } :
(N55)? { 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0 } : 1'b0;
assign N52 = N54;
assign illegal_instr_o = (N52)? N320 :
(N55)? 1'b1 : 1'b0;
assign decode_o[42] = ~decode_o[38];
assign { decode_o[41:39], decode_o[37:37], decode_o[35:35], decode_o[33:33], decode_o[31:29], decode_o[25:0] } = (N53)? { fe_nop_v_i, be_nop_v_i, me_nop_v_i, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0 } :
(N338)? { 1'b0, 1'b0, 1'b0, N336, N335, N334, N333, N332, N331, N321, N330, N329, N328, N327, N326, N325, instr_i[19:15], instr_i[24:20], instr_i[11:7], N324, N323, N322, N321 } : 1'b0;
assign N53 = decode_o[38];
assign N55 = ~N54;
assign N63 = N358 | N359;
assign N358 = ~N59;
assign N359 = ~N62;
assign N69 = N360 | N361;
assign N360 = ~N66;
assign N361 = ~N68;
assign N71 = ~N70;
assign N73 = ~N72;
assign N78 = ~N77;
assign N82 = ~N81;
assign N84 = ~N83;
assign N85 = ~instr_i[6];
assign N86 = ~instr_i[2];
assign N93 = ~N92;
assign N96 = ~N95;
assign N99 = ~N98;
assign N116 = N101 | N367;
assign N367 = N102 | N366;
assign N366 = N104 | N365;
assign N365 = N107 | N364;
assign N364 = N110 | N363;
assign N363 = N112 | N362;
assign N362 = N114 | N115;
assign N117 = ~instr_i[31];
assign N118 = ~instr_i[29];
assign N119 = ~instr_i[28];
assign N120 = ~instr_i[27];
assign N121 = ~instr_i[26];
assign N122 = ~instr_i[25];
assign N132 = ~N131;
assign N136 = N134 | N135;
assign N140 = N138 | N139;
assign N144 = N142 | N143;
assign N148 = N146 | N147;
assign N152 = N150 | N151;
assign N153 = ~instr_i[30];
assign N174 = N167 | N370;
assign N370 = N169 | N369;
assign N369 = N170 | N368;
assign N368 = N171 | N173;
assign N187 = ~N186;
assign N191 = N188 | N190;
assign N196 = N194 | N195;
assign N202 = N200 | N201;
assign N212 = N209 | N211;
assign N220 = N196 | N191;
assign N221 = N202 | N220;
assign N222 = N212 | N221;
assign N223 = N213 | N222;
assign N224 = N214 | N223;
assign N225 = N215 | N224;
assign N226 = N217 | N225;
assign N227 = N219 | N226;
assign N228 = ~N227;
assign N241 = ~N240;
assign N251 = ~instr_i[14];
assign N265 = ~N264;
assign N282 = ~N281;
assign N283 = ~instr_i[13];
assign N284 = ~instr_i[12];
assign N294 = ~instr_i[24];
assign N295 = ~instr_i[22];
assign N307 = ~N306;
assign N315 = N98;
assign N337 = N372 | illegal_instr_o;
assign N372 = N371 | me_nop_v_i;
assign N371 = fe_nop_v_i | be_nop_v_i;
assign decode_o[38] = N337;
assign N338 = ~decode_o[38];
endmodule
|
module bp_be_pipe_mul
(
clk_i,
reset_i,
decode_i,
rs1_i,
rs2_i,
exc_i,
result_o
);
input [42:0] decode_i;
input [63:0] rs1_i;
input [63:0] rs2_i;
input [6:0] exc_i;
output [63:0] result_o;
input clk_i;
input reset_i;
wire [63:0] result_o;
assign result_o[0] = 1'b0;
assign result_o[1] = 1'b0;
assign result_o[2] = 1'b0;
assign result_o[3] = 1'b0;
assign result_o[4] = 1'b0;
assign result_o[5] = 1'b0;
assign result_o[6] = 1'b0;
assign result_o[7] = 1'b0;
assign result_o[8] = 1'b0;
assign result_o[9] = 1'b0;
assign result_o[10] = 1'b0;
assign result_o[11] = 1'b0;
assign result_o[12] = 1'b0;
assign result_o[13] = 1'b0;
assign result_o[14] = 1'b0;
assign result_o[15] = 1'b0;
assign result_o[16] = 1'b0;
assign result_o[17] = 1'b0;
assign result_o[18] = 1'b0;
assign result_o[19] = 1'b0;
assign result_o[20] = 1'b0;
assign result_o[21] = 1'b0;
assign result_o[22] = 1'b0;
assign result_o[23] = 1'b0;
assign result_o[24] = 1'b0;
assign result_o[25] = 1'b0;
assign result_o[26] = 1'b0;
assign result_o[27] = 1'b0;
assign result_o[28] = 1'b0;
assign result_o[29] = 1'b0;
assign result_o[30] = 1'b0;
assign result_o[31] = 1'b0;
assign result_o[32] = 1'b0;
assign result_o[33] = 1'b0;
assign result_o[34] = 1'b0;
assign result_o[35] = 1'b0;
assign result_o[36] = 1'b0;
assign result_o[37] = 1'b0;
assign result_o[38] = 1'b0;
assign result_o[39] = 1'b0;
assign result_o[40] = 1'b0;
assign result_o[41] = 1'b0;
assign result_o[42] = 1'b0;
assign result_o[43] = 1'b0;
assign result_o[44] = 1'b0;
assign result_o[45] = 1'b0;
assign result_o[46] = 1'b0;
assign result_o[47] = 1'b0;
assign result_o[48] = 1'b0;
assign result_o[49] = 1'b0;
assign result_o[50] = 1'b0;
assign result_o[51] = 1'b0;
assign result_o[52] = 1'b0;
assign result_o[53] = 1'b0;
assign result_o[54] = 1'b0;
assign result_o[55] = 1'b0;
assign result_o[56] = 1'b0;
assign result_o[57] = 1'b0;
assign result_o[58] = 1'b0;
assign result_o[59] = 1'b0;
assign result_o[60] = 1'b0;
assign result_o[61] = 1'b0;
assign result_o[62] = 1'b0;
assign result_o[63] = 1'b0;
endmodule
|
module bsg_mux_width_p16_els_p4
(
data_i,
sel_i,
data_o
);
input [63:0] data_i;
input [1:0] sel_i;
output [15:0] data_o;
wire [15:0] data_o;
wire N0,N1,N2,N3,N4,N5;
assign data_o[15] = (N2)? data_i[15] :
(N4)? data_i[31] :
(N3)? data_i[47] :
(N5)? data_i[63] : 1'b0;
assign data_o[14] = (N2)? data_i[14] :
(N4)? data_i[30] :
(N3)? data_i[46] :
(N5)? data_i[62] : 1'b0;
assign data_o[13] = (N2)? data_i[13] :
(N4)? data_i[29] :
(N3)? data_i[45] :
(N5)? data_i[61] : 1'b0;
assign data_o[12] = (N2)? data_i[12] :
(N4)? data_i[28] :
(N3)? data_i[44] :
(N5)? data_i[60] : 1'b0;
assign data_o[11] = (N2)? data_i[11] :
(N4)? data_i[27] :
(N3)? data_i[43] :
(N5)? data_i[59] : 1'b0;
assign data_o[10] = (N2)? data_i[10] :
(N4)? data_i[26] :
(N3)? data_i[42] :
(N5)? data_i[58] : 1'b0;
assign data_o[9] = (N2)? data_i[9] :
(N4)? data_i[25] :
(N3)? data_i[41] :
(N5)? data_i[57] : 1'b0;
assign data_o[8] = (N2)? data_i[8] :
(N4)? data_i[24] :
(N3)? data_i[40] :
(N5)? data_i[56] : 1'b0;
assign data_o[7] = (N2)? data_i[7] :
(N4)? data_i[23] :
(N3)? data_i[39] :
(N5)? data_i[55] : 1'b0;
assign data_o[6] = (N2)? data_i[6] :
(N4)? data_i[22] :
(N3)? data_i[38] :
(N5)? data_i[54] : 1'b0;
assign data_o[5] = (N2)? data_i[5] :
(N4)? data_i[21] :
(N3)? data_i[37] :
(N5)? data_i[53] : 1'b0;
assign data_o[4] = (N2)? data_i[4] :
(N4)? data_i[20] :
(N3)? data_i[36] :
(N5)? data_i[52] : 1'b0;
assign data_o[3] = (N2)? data_i[3] :
(N4)? data_i[19] :
(N3)? data_i[35] :
(N5)? data_i[51] : 1'b0;
assign data_o[2] = (N2)? data_i[2] :
(N4)? data_i[18] :
(N3)? data_i[34] :
(N5)? data_i[50] : 1'b0;
assign data_o[1] = (N2)? data_i[1] :
(N4)? data_i[17] :
(N3)? data_i[33] :
(N5)? data_i[49] : 1'b0;
assign data_o[0] = (N2)? data_i[0] :
(N4)? data_i[16] :
(N3)? data_i[32] :
(N5)? data_i[48] : 1'b0;
assign N0 = ~sel_i[0];
assign N1 = ~sel_i[1];
assign N2 = N0 & N1;
assign N3 = N0 & sel_i[1];
assign N4 = sel_i[0] & N1;
assign N5 = sel_i[0] & sel_i[1];
endmodule
|
module bsg_mux_one_hot_width_p38_els_p5
(
data_i,
sel_one_hot_i,
data_o
);
input [189:0] data_i;
input [4:0] sel_one_hot_i;
output [37:0] data_o;
wire [37:0] data_o;
wire N0,N1,N2,N3,N4,N5,N6,N7,N8,N9,N10,N11,N12,N13,N14,N15,N16,N17,N18,N19,N20,N21,
N22,N23,N24,N25,N26,N27,N28,N29,N30,N31,N32,N33,N34,N35,N36,N37,N38,N39,N40,N41,
N42,N43,N44,N45,N46,N47,N48,N49,N50,N51,N52,N53,N54,N55,N56,N57,N58,N59,N60,N61,
N62,N63,N64,N65,N66,N67,N68,N69,N70,N71,N72,N73,N74,N75,N76,N77,N78,N79,N80,N81,
N82,N83,N84,N85,N86,N87,N88,N89,N90,N91,N92,N93,N94,N95,N96,N97,N98,N99,N100,N101,
N102,N103,N104,N105,N106,N107,N108,N109,N110,N111,N112,N113;
wire [189:0] data_masked;
assign data_masked[37] = data_i[37] & sel_one_hot_i[0];
assign data_masked[36] = data_i[36] & sel_one_hot_i[0];
assign data_masked[35] = data_i[35] & sel_one_hot_i[0];
assign data_masked[34] = data_i[34] & sel_one_hot_i[0];
assign data_masked[33] = data_i[33] & sel_one_hot_i[0];
assign data_masked[32] = data_i[32] & sel_one_hot_i[0];
assign data_masked[31] = data_i[31] & sel_one_hot_i[0];
assign data_masked[30] = data_i[30] & sel_one_hot_i[0];
assign data_masked[29] = data_i[29] & sel_one_hot_i[0];
assign data_masked[28] = data_i[28] & sel_one_hot_i[0];
assign data_masked[27] = data_i[27] & sel_one_hot_i[0];
assign data_masked[26] = data_i[26] & sel_one_hot_i[0];
assign data_masked[25] = data_i[25] & sel_one_hot_i[0];
assign data_masked[24] = data_i[24] & sel_one_hot_i[0];
assign data_masked[23] = data_i[23] & sel_one_hot_i[0];
assign data_masked[22] = data_i[22] & sel_one_hot_i[0];
assign data_masked[21] = data_i[21] & sel_one_hot_i[0];
assign data_masked[20] = data_i[20] & sel_one_hot_i[0];
assign data_masked[19] = data_i[19] & sel_one_hot_i[0];
assign data_masked[18] = data_i[18] & sel_one_hot_i[0];
assign data_masked[17] = data_i[17] & sel_one_hot_i[0];
assign data_masked[16] = data_i[16] & sel_one_hot_i[0];
assign data_masked[15] = data_i[15] & sel_one_hot_i[0];
assign data_masked[14] = data_i[14] & sel_one_hot_i[0];
assign data_masked[13] = data_i[13] & sel_one_hot_i[0];
assign data_masked[12] = data_i[12] & sel_one_hot_i[0];
assign data_masked[11] = data_i[11] & sel_one_hot_i[0];
assign data_masked[10] = data_i[10] & sel_one_hot_i[0];
assign data_masked[9] = data_i[9] & sel_one_hot_i[0];
assign data_masked[8] = data_i[8] & sel_one_hot_i[0];
assign data_masked[7] = data_i[7] & sel_one_hot_i[0];
assign data_masked[6] = data_i[6] & sel_one_hot_i[0];
assign data_masked[5] = data_i[5] & sel_one_hot_i[0];
assign data_masked[4] = data_i[4] & sel_one_hot_i[0];
assign data_masked[3] = data_i[3] & sel_one_hot_i[0];
assign data_masked[2] = data_i[2] & sel_one_hot_i[0];
assign data_masked[1] = data_i[1] & sel_one_hot_i[0];
assign data_masked[0] = data_i[0] & sel_one_hot_i[0];
assign data_masked[75] = data_i[75] & sel_one_hot_i[1];
assign data_masked[74] = data_i[74] & sel_one_hot_i[1];
assign data_masked[73] = data_i[73] & sel_one_hot_i[1];
assign data_masked[72] = data_i[72] & sel_one_hot_i[1];
assign data_masked[71] = data_i[71] & sel_one_hot_i[1];
assign data_masked[70] = data_i[70] & sel_one_hot_i[1];
assign data_masked[69] = data_i[69] & sel_one_hot_i[1];
assign data_masked[68] = data_i[68] & sel_one_hot_i[1];
assign data_masked[67] = data_i[67] & sel_one_hot_i[1];
assign data_masked[66] = data_i[66] & sel_one_hot_i[1];
assign data_masked[65] = data_i[65] & sel_one_hot_i[1];
assign data_masked[64] = data_i[64] & sel_one_hot_i[1];
assign data_masked[63] = data_i[63] & sel_one_hot_i[1];
assign data_masked[62] = data_i[62] & sel_one_hot_i[1];
assign data_masked[61] = data_i[61] & sel_one_hot_i[1];
assign data_masked[60] = data_i[60] & sel_one_hot_i[1];
assign data_masked[59] = data_i[59] & sel_one_hot_i[1];
assign data_masked[58] = data_i[58] & sel_one_hot_i[1];
assign data_masked[57] = data_i[57] & sel_one_hot_i[1];
assign data_masked[56] = data_i[56] & sel_one_hot_i[1];
assign data_masked[55] = data_i[55] & sel_one_hot_i[1];
assign data_masked[54] = data_i[54] & sel_one_hot_i[1];
assign data_masked[53] = data_i[53] & sel_one_hot_i[1];
assign data_masked[52] = data_i[52] & sel_one_hot_i[1];
assign data_masked[51] = data_i[51] & sel_one_hot_i[1];
assign data_masked[50] = data_i[50] & sel_one_hot_i[1];
assign data_masked[49] = data_i[49] & sel_one_hot_i[1];
assign data_masked[48] = data_i[48] & sel_one_hot_i[1];
assign data_masked[47] = data_i[47] & sel_one_hot_i[1];
assign data_masked[46] = data_i[46] & sel_one_hot_i[1];
assign data_masked[45] = data_i[45] & sel_one_hot_i[1];
assign data_masked[44] = data_i[44] & sel_one_hot_i[1];
assign data_masked[43] = data_i[43] & sel_one_hot_i[1];
assign data_masked[42] = data_i[42] & sel_one_hot_i[1];
assign data_masked[41] = data_i[41] & sel_one_hot_i[1];
assign data_masked[40] = data_i[40] & sel_one_hot_i[1];
assign data_masked[39] = data_i[39] & sel_one_hot_i[1];
assign data_masked[38] = data_i[38] & sel_one_hot_i[1];
assign data_masked[113] = data_i[113] & sel_one_hot_i[2];
assign data_masked[112] = data_i[112] & sel_one_hot_i[2];
assign data_masked[111] = data_i[111] & sel_one_hot_i[2];
assign data_masked[110] = data_i[110] & sel_one_hot_i[2];
assign data_masked[109] = data_i[109] & sel_one_hot_i[2];
assign data_masked[108] = data_i[108] & sel_one_hot_i[2];
assign data_masked[107] = data_i[107] & sel_one_hot_i[2];
assign data_masked[106] = data_i[106] & sel_one_hot_i[2];
assign data_masked[105] = data_i[105] & sel_one_hot_i[2];
assign data_masked[104] = data_i[104] & sel_one_hot_i[2];
assign data_masked[103] = data_i[103] & sel_one_hot_i[2];
assign data_masked[102] = data_i[102] & sel_one_hot_i[2];
assign data_masked[101] = data_i[101] & sel_one_hot_i[2];
assign data_masked[100] = data_i[100] & sel_one_hot_i[2];
assign data_masked[99] = data_i[99] & sel_one_hot_i[2];
assign data_masked[98] = data_i[98] & sel_one_hot_i[2];
assign data_masked[97] = data_i[97] & sel_one_hot_i[2];
assign data_masked[96] = data_i[96] & sel_one_hot_i[2];
assign data_masked[95] = data_i[95] & sel_one_hot_i[2];
assign data_masked[94] = data_i[94] & sel_one_hot_i[2];
assign data_masked[93] = data_i[93] & sel_one_hot_i[2];
assign data_masked[92] = data_i[92] & sel_one_hot_i[2];
assign data_masked[91] = data_i[91] & sel_one_hot_i[2];
assign data_masked[90] = data_i[90] & sel_one_hot_i[2];
assign data_masked[89] = data_i[89] & sel_one_hot_i[2];
assign data_masked[88] = data_i[88] & sel_one_hot_i[2];
assign data_masked[87] = data_i[87] & sel_one_hot_i[2];
assign data_masked[86] = data_i[86] & sel_one_hot_i[2];
assign data_masked[85] = data_i[85] & sel_one_hot_i[2];
assign data_masked[84] = data_i[84] & sel_one_hot_i[2];
assign data_masked[83] = data_i[83] & sel_one_hot_i[2];
assign data_masked[82] = data_i[82] & sel_one_hot_i[2];
assign data_masked[81] = data_i[81] & sel_one_hot_i[2];
assign data_masked[80] = data_i[80] & sel_one_hot_i[2];
assign data_masked[79] = data_i[79] & sel_one_hot_i[2];
assign data_masked[78] = data_i[78] & sel_one_hot_i[2];
assign data_masked[77] = data_i[77] & sel_one_hot_i[2];
assign data_masked[76] = data_i[76] & sel_one_hot_i[2];
assign data_masked[151] = data_i[151] & sel_one_hot_i[3];
assign data_masked[150] = data_i[150] & sel_one_hot_i[3];
assign data_masked[149] = data_i[149] & sel_one_hot_i[3];
assign data_masked[148] = data_i[148] & sel_one_hot_i[3];
assign data_masked[147] = data_i[147] & sel_one_hot_i[3];
assign data_masked[146] = data_i[146] & sel_one_hot_i[3];
assign data_masked[145] = data_i[145] & sel_one_hot_i[3];
assign data_masked[144] = data_i[144] & sel_one_hot_i[3];
assign data_masked[143] = data_i[143] & sel_one_hot_i[3];
assign data_masked[142] = data_i[142] & sel_one_hot_i[3];
assign data_masked[141] = data_i[141] & sel_one_hot_i[3];
assign data_masked[140] = data_i[140] & sel_one_hot_i[3];
assign data_masked[139] = data_i[139] & sel_one_hot_i[3];
assign data_masked[138] = data_i[138] & sel_one_hot_i[3];
assign data_masked[137] = data_i[137] & sel_one_hot_i[3];
assign data_masked[136] = data_i[136] & sel_one_hot_i[3];
assign data_masked[135] = data_i[135] & sel_one_hot_i[3];
assign data_masked[134] = data_i[134] & sel_one_hot_i[3];
assign data_masked[133] = data_i[133] & sel_one_hot_i[3];
assign data_masked[132] = data_i[132] & sel_one_hot_i[3];
assign data_masked[131] = data_i[131] & sel_one_hot_i[3];
assign data_masked[130] = data_i[130] & sel_one_hot_i[3];
assign data_masked[129] = data_i[129] & sel_one_hot_i[3];
assign data_masked[128] = data_i[128] & sel_one_hot_i[3];
assign data_masked[127] = data_i[127] & sel_one_hot_i[3];
assign data_masked[126] = data_i[126] & sel_one_hot_i[3];
assign data_masked[125] = data_i[125] & sel_one_hot_i[3];
assign data_masked[124] = data_i[124] & sel_one_hot_i[3];
assign data_masked[123] = data_i[123] & sel_one_hot_i[3];
assign data_masked[122] = data_i[122] & sel_one_hot_i[3];
assign data_masked[121] = data_i[121] & sel_one_hot_i[3];
assign data_masked[120] = data_i[120] & sel_one_hot_i[3];
assign data_masked[119] = data_i[119] & sel_one_hot_i[3];
assign data_masked[118] = data_i[118] & sel_one_hot_i[3];
assign data_masked[117] = data_i[117] & sel_one_hot_i[3];
assign data_masked[116] = data_i[116] & sel_one_hot_i[3];
assign data_masked[115] = data_i[115] & sel_one_hot_i[3];
assign data_masked[114] = data_i[114] & sel_one_hot_i[3];
assign data_masked[189] = data_i[189] & sel_one_hot_i[4];
assign data_masked[188] = data_i[188] & sel_one_hot_i[4];
assign data_masked[187] = data_i[187] & sel_one_hot_i[4];
assign data_masked[186] = data_i[186] & sel_one_hot_i[4];
assign data_masked[185] = data_i[185] & sel_one_hot_i[4];
assign data_masked[184] = data_i[184] & sel_one_hot_i[4];
assign data_masked[183] = data_i[183] & sel_one_hot_i[4];
assign data_masked[182] = data_i[182] & sel_one_hot_i[4];
assign data_masked[181] = data_i[181] & sel_one_hot_i[4];
assign data_masked[180] = data_i[180] & sel_one_hot_i[4];
assign data_masked[179] = data_i[179] & sel_one_hot_i[4];
assign data_masked[178] = data_i[178] & sel_one_hot_i[4];
assign data_masked[177] = data_i[177] & sel_one_hot_i[4];
assign data_masked[176] = data_i[176] & sel_one_hot_i[4];
assign data_masked[175] = data_i[175] & sel_one_hot_i[4];
assign data_masked[174] = data_i[174] & sel_one_hot_i[4];
assign data_masked[173] = data_i[173] & sel_one_hot_i[4];
assign data_masked[172] = data_i[172] & sel_one_hot_i[4];
assign data_masked[171] = data_i[171] & sel_one_hot_i[4];
assign data_masked[170] = data_i[170] & sel_one_hot_i[4];
assign data_masked[169] = data_i[169] & sel_one_hot_i[4];
assign data_masked[168] = data_i[168] & sel_one_hot_i[4];
assign data_masked[167] = data_i[167] & sel_one_hot_i[4];
assign data_masked[166] = data_i[166] & sel_one_hot_i[4];
assign data_masked[165] = data_i[165] & sel_one_hot_i[4];
assign data_masked[164] = data_i[164] & sel_one_hot_i[4];
assign data_masked[163] = data_i[163] & sel_one_hot_i[4];
assign data_masked[162] = data_i[162] & sel_one_hot_i[4];
assign data_masked[161] = data_i[161] & sel_one_hot_i[4];
assign data_masked[160] = data_i[160] & sel_one_hot_i[4];
assign data_masked[159] = data_i[159] & sel_one_hot_i[4];
assign data_masked[158] = data_i[158] & sel_one_hot_i[4];
assign data_masked[157] = data_i[157] & sel_one_hot_i[4];
assign data_masked[156] = data_i[156] & sel_one_hot_i[4];
assign data_masked[155] = data_i[155] & sel_one_hot_i[4];
assign data_masked[154] = data_i[154] & sel_one_hot_i[4];
assign data_masked[153] = data_i[153] & sel_one_hot_i[4];
assign data_masked[152] = data_i[152] & sel_one_hot_i[4];
assign data_o[0] = N2 | data_masked[0];
assign N2 = N1 | data_masked[38];
assign N1 = N0 | data_masked[76];
assign N0 = data_masked[152] | data_masked[114];
assign data_o[1] = N5 | data_masked[1];
assign N5 = N4 | data_masked[39];
assign N4 = N3 | data_masked[77];
assign N3 = data_masked[153] | data_masked[115];
assign data_o[2] = N8 | data_masked[2];
assign N8 = N7 | data_masked[40];
assign N7 = N6 | data_masked[78];
assign N6 = data_masked[154] | data_masked[116];
assign data_o[3] = N11 | data_masked[3];
assign N11 = N10 | data_masked[41];
assign N10 = N9 | data_masked[79];
assign N9 = data_masked[155] | data_masked[117];
assign data_o[4] = N14 | data_masked[4];
assign N14 = N13 | data_masked[42];
assign N13 = N12 | data_masked[80];
assign N12 = data_masked[156] | data_masked[118];
assign data_o[5] = N17 | data_masked[5];
assign N17 = N16 | data_masked[43];
assign N16 = N15 | data_masked[81];
assign N15 = data_masked[157] | data_masked[119];
assign data_o[6] = N20 | data_masked[6];
assign N20 = N19 | data_masked[44];
assign N19 = N18 | data_masked[82];
assign N18 = data_masked[158] | data_masked[120];
assign data_o[7] = N23 | data_masked[7];
assign N23 = N22 | data_masked[45];
assign N22 = N21 | data_masked[83];
assign N21 = data_masked[159] | data_masked[121];
assign data_o[8] = N26 | data_masked[8];
assign N26 = N25 | data_masked[46];
assign N25 = N24 | data_masked[84];
assign N24 = data_masked[160] | data_masked[122];
assign data_o[9] = N29 | data_masked[9];
assign N29 = N28 | data_masked[47];
assign N28 = N27 | data_masked[85];
assign N27 = data_masked[161] | data_masked[123];
assign data_o[10] = N32 | data_masked[10];
assign N32 = N31 | data_masked[48];
assign N31 = N30 | data_masked[86];
assign N30 = data_masked[162] | data_masked[124];
assign data_o[11] = N35 | data_masked[11];
assign N35 = N34 | data_masked[49];
assign N34 = N33 | data_masked[87];
assign N33 = data_masked[163] | data_masked[125];
assign data_o[12] = N38 | data_masked[12];
assign N38 = N37 | data_masked[50];
assign N37 = N36 | data_masked[88];
assign N36 = data_masked[164] | data_masked[126];
assign data_o[13] = N41 | data_masked[13];
assign N41 = N40 | data_masked[51];
assign N40 = N39 | data_masked[89];
assign N39 = data_masked[165] | data_masked[127];
assign data_o[14] = N44 | data_masked[14];
assign N44 = N43 | data_masked[52];
assign N43 = N42 | data_masked[90];
assign N42 = data_masked[166] | data_masked[128];
assign data_o[15] = N47 | data_masked[15];
assign N47 = N46 | data_masked[53];
assign N46 = N45 | data_masked[91];
assign N45 = data_masked[167] | data_masked[129];
assign data_o[16] = N50 | data_masked[16];
assign N50 = N49 | data_masked[54];
assign N49 = N48 | data_masked[92];
assign N48 = data_masked[168] | data_masked[130];
assign data_o[17] = N53 | data_masked[17];
assign N53 = N52 | data_masked[55];
assign N52 = N51 | data_masked[93];
assign N51 = data_masked[169] | data_masked[131];
assign data_o[18] = N56 | data_masked[18];
assign N56 = N55 | data_masked[56];
assign N55 = N54 | data_masked[94];
assign N54 = data_masked[170] | data_masked[132];
assign data_o[19] = N59 | data_masked[19];
assign N59 = N58 | data_masked[57];
assign N58 = N57 | data_masked[95];
assign N57 = data_masked[171] | data_masked[133];
assign data_o[20] = N62 | data_masked[20];
assign N62 = N61 | data_masked[58];
assign N61 = N60 | data_masked[96];
assign N60 = data_masked[172] | data_masked[134];
assign data_o[21] = N65 | data_masked[21];
assign N65 = N64 | data_masked[59];
assign N64 = N63 | data_masked[97];
assign N63 = data_masked[173] | data_masked[135];
assign data_o[22] = N68 | data_masked[22];
assign N68 = N67 | data_masked[60];
assign N67 = N66 | data_masked[98];
assign N66 = data_masked[174] | data_masked[136];
assign data_o[23] = N71 | data_masked[23];
assign N71 = N70 | data_masked[61];
assign N70 = N69 | data_masked[99];
assign N69 = data_masked[175] | data_masked[137];
assign data_o[24] = N74 | data_masked[24];
assign N74 = N73 | data_masked[62];
assign N73 = N72 | data_masked[100];
assign N72 = data_masked[176] | data_masked[138];
assign data_o[25] = N77 | data_masked[25];
assign N77 = N76 | data_masked[63];
assign N76 = N75 | data_masked[101];
assign N75 = data_masked[177] | data_masked[139];
assign data_o[26] = N80 | data_masked[26];
assign N80 = N79 | data_masked[64];
assign N79 = N78 | data_masked[102];
assign N78 = data_masked[178] | data_masked[140];
assign data_o[27] = N83 | data_masked[27];
assign N83 = N82 | data_masked[65];
assign N82 = N81 | data_masked[103];
assign N81 = data_masked[179] | data_masked[141];
assign data_o[28] = N86 | data_masked[28];
assign N86 = N85 | data_masked[66];
assign N85 = N84 | data_masked[104];
assign N84 = data_masked[180] | data_masked[142];
assign data_o[29] = N89 | data_masked[29];
assign N89 = N88 | data_masked[67];
assign N88 = N87 | data_masked[105];
assign N87 = data_masked[181] | data_masked[143];
assign data_o[30] = N92 | data_masked[30];
assign N92 = N91 | data_masked[68];
assign N91 = N90 | data_masked[106];
assign N90 = data_masked[182] | data_masked[144];
assign data_o[31] = N95 | data_masked[31];
assign N95 = N94 | data_masked[69];
assign N94 = N93 | data_masked[107];
assign N93 = data_masked[183] | data_masked[145];
assign data_o[32] = N98 | data_masked[32];
assign N98 = N97 | data_masked[70];
assign N97 = N96 | data_masked[108];
assign N96 = data_masked[184] | data_masked[146];
assign data_o[33] = N101 | data_masked[33];
assign N101 = N100 | data_masked[71];
assign N100 = N99 | data_masked[109];
assign N99 = data_masked[185] | data_masked[147];
assign data_o[34] = N104 | data_masked[34];
assign N104 = N103 | data_masked[72];
assign N103 = N102 | data_masked[110];
assign N102 = data_masked[186] | data_masked[148];
assign data_o[35] = N107 | data_masked[35];
assign N107 = N106 | data_masked[73];
assign N106 = N105 | data_masked[111];
assign N105 = data_masked[187] | data_masked[149];
assign data_o[36] = N110 | data_masked[36];
assign N110 = N109 | data_masked[74];
assign N109 = N108 | data_masked[112];
assign N108 = data_masked[188] | data_masked[150];
assign data_o[37] = N113 | data_masked[37];
assign N113 = N112 | data_masked[75];
assign N112 = N111 | data_masked[113];
assign N111 = data_masked[189] | data_masked[151];
endmodule
|
module rvdff_WIDTH1
(
din,
clk,
rst_l,
dout
);
input [0:0] din;
output [0:0] dout;
input clk;
input rst_l;
wire N0;
reg [0:0] dout;
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[0] <= 1'b0;
end else if(1'b1) begin
dout[0] <= din[0];
end
end
assign N0 = ~rst_l;
endmodule
|
module rvdff_WIDTH31
(
din,
clk,
rst_l,
dout
);
input [30:0] din;
output [30:0] dout;
input clk;
input rst_l;
wire N0;
reg [30:0] dout;
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[30] <= 1'b0;
end else if(1'b1) begin
dout[30] <= din[30];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[29] <= 1'b0;
end else if(1'b1) begin
dout[29] <= din[29];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[28] <= 1'b0;
end else if(1'b1) begin
dout[28] <= din[28];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[27] <= 1'b0;
end else if(1'b1) begin
dout[27] <= din[27];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[26] <= 1'b0;
end else if(1'b1) begin
dout[26] <= din[26];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[25] <= 1'b0;
end else if(1'b1) begin
dout[25] <= din[25];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[24] <= 1'b0;
end else if(1'b1) begin
dout[24] <= din[24];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[23] <= 1'b0;
end else if(1'b1) begin
dout[23] <= din[23];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[22] <= 1'b0;
end else if(1'b1) begin
dout[22] <= din[22];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[21] <= 1'b0;
end else if(1'b1) begin
dout[21] <= din[21];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[20] <= 1'b0;
end else if(1'b1) begin
dout[20] <= din[20];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[19] <= 1'b0;
end else if(1'b1) begin
dout[19] <= din[19];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[18] <= 1'b0;
end else if(1'b1) begin
dout[18] <= din[18];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[17] <= 1'b0;
end else if(1'b1) begin
dout[17] <= din[17];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[16] <= 1'b0;
end else if(1'b1) begin
dout[16] <= din[16];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[15] <= 1'b0;
end else if(1'b1) begin
dout[15] <= din[15];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[14] <= 1'b0;
end else if(1'b1) begin
dout[14] <= din[14];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[13] <= 1'b0;
end else if(1'b1) begin
dout[13] <= din[13];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[12] <= 1'b0;
end else if(1'b1) begin
dout[12] <= din[12];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[11] <= 1'b0;
end else if(1'b1) begin
dout[11] <= din[11];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[10] <= 1'b0;
end else if(1'b1) begin
dout[10] <= din[10];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[9] <= 1'b0;
end else if(1'b1) begin
dout[9] <= din[9];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[8] <= 1'b0;
end else if(1'b1) begin
dout[8] <= din[8];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[7] <= 1'b0;
end else if(1'b1) begin
dout[7] <= din[7];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[6] <= 1'b0;
end else if(1'b1) begin
dout[6] <= din[6];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[5] <= 1'b0;
end else if(1'b1) begin
dout[5] <= din[5];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[4] <= 1'b0;
end else if(1'b1) begin
dout[4] <= din[4];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[3] <= 1'b0;
end else if(1'b1) begin
dout[3] <= din[3];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[2] <= 1'b0;
end else if(1'b1) begin
dout[2] <= din[2];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[1] <= 1'b0;
end else if(1'b1) begin
dout[1] <= din[1];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[0] <= 1'b0;
end else if(1'b1) begin
dout[0] <= din[0];
end
end
assign N0 = ~rst_l;
endmodule
|
module rvdff_WIDTH13
(
din,
clk,
rst_l,
dout
);
input [12:0] din;
output [12:0] dout;
input clk;
input rst_l;
wire N0;
reg [12:0] dout;
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[12] <= 1'b0;
end else if(1'b1) begin
dout[12] <= din[12];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[11] <= 1'b0;
end else if(1'b1) begin
dout[11] <= din[11];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[10] <= 1'b0;
end else if(1'b1) begin
dout[10] <= din[10];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[9] <= 1'b0;
end else if(1'b1) begin
dout[9] <= din[9];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[8] <= 1'b0;
end else if(1'b1) begin
dout[8] <= din[8];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[7] <= 1'b0;
end else if(1'b1) begin
dout[7] <= din[7];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[6] <= 1'b0;
end else if(1'b1) begin
dout[6] <= din[6];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[5] <= 1'b0;
end else if(1'b1) begin
dout[5] <= din[5];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[4] <= 1'b0;
end else if(1'b1) begin
dout[4] <= din[4];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[3] <= 1'b0;
end else if(1'b1) begin
dout[3] <= din[3];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[2] <= 1'b0;
end else if(1'b1) begin
dout[2] <= din[2];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[1] <= 1'b0;
end else if(1'b1) begin
dout[1] <= din[1];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[0] <= 1'b0;
end else if(1'b1) begin
dout[0] <= din[0];
end
end
assign N0 = ~rst_l;
endmodule
|
module rvdff_WIDTH34
(
din,
clk,
rst_l,
dout
);
input [33:0] din;
output [33:0] dout;
input clk;
input rst_l;
wire N0;
reg [33:0] dout;
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[33] <= 1'b0;
end else if(1'b1) begin
dout[33] <= din[33];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[32] <= 1'b0;
end else if(1'b1) begin
dout[32] <= din[32];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[31] <= 1'b0;
end else if(1'b1) begin
dout[31] <= din[31];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[30] <= 1'b0;
end else if(1'b1) begin
dout[30] <= din[30];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[29] <= 1'b0;
end else if(1'b1) begin
dout[29] <= din[29];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[28] <= 1'b0;
end else if(1'b1) begin
dout[28] <= din[28];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[27] <= 1'b0;
end else if(1'b1) begin
dout[27] <= din[27];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[26] <= 1'b0;
end else if(1'b1) begin
dout[26] <= din[26];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[25] <= 1'b0;
end else if(1'b1) begin
dout[25] <= din[25];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[24] <= 1'b0;
end else if(1'b1) begin
dout[24] <= din[24];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[23] <= 1'b0;
end else if(1'b1) begin
dout[23] <= din[23];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[22] <= 1'b0;
end else if(1'b1) begin
dout[22] <= din[22];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[21] <= 1'b0;
end else if(1'b1) begin
dout[21] <= din[21];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[20] <= 1'b0;
end else if(1'b1) begin
dout[20] <= din[20];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[19] <= 1'b0;
end else if(1'b1) begin
dout[19] <= din[19];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[18] <= 1'b0;
end else if(1'b1) begin
dout[18] <= din[18];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[17] <= 1'b0;
end else if(1'b1) begin
dout[17] <= din[17];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[16] <= 1'b0;
end else if(1'b1) begin
dout[16] <= din[16];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[15] <= 1'b0;
end else if(1'b1) begin
dout[15] <= din[15];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[14] <= 1'b0;
end else if(1'b1) begin
dout[14] <= din[14];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[13] <= 1'b0;
end else if(1'b1) begin
dout[13] <= din[13];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[12] <= 1'b0;
end else if(1'b1) begin
dout[12] <= din[12];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[11] <= 1'b0;
end else if(1'b1) begin
dout[11] <= din[11];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[10] <= 1'b0;
end else if(1'b1) begin
dout[10] <= din[10];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[9] <= 1'b0;
end else if(1'b1) begin
dout[9] <= din[9];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[8] <= 1'b0;
end else if(1'b1) begin
dout[8] <= din[8];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[7] <= 1'b0;
end else if(1'b1) begin
dout[7] <= din[7];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[6] <= 1'b0;
end else if(1'b1) begin
dout[6] <= din[6];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[5] <= 1'b0;
end else if(1'b1) begin
dout[5] <= din[5];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[4] <= 1'b0;
end else if(1'b1) begin
dout[4] <= din[4];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[3] <= 1'b0;
end else if(1'b1) begin
dout[3] <= din[3];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[2] <= 1'b0;
end else if(1'b1) begin
dout[2] <= din[2];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[1] <= 1'b0;
end else if(1'b1) begin
dout[1] <= din[1];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[0] <= 1'b0;
end else if(1'b1) begin
dout[0] <= din[0];
end
end
assign N0 = ~rst_l;
endmodule
|
module rvdff_WIDTH67
(
din,
clk,
rst_l,
dout
);
input [66:0] din;
output [66:0] dout;
input clk;
input rst_l;
wire N0;
reg [66:0] dout;
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[66] <= 1'b0;
end else if(1'b1) begin
dout[66] <= din[66];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[65] <= 1'b0;
end else if(1'b1) begin
dout[65] <= din[65];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[64] <= 1'b0;
end else if(1'b1) begin
dout[64] <= din[64];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[63] <= 1'b0;
end else if(1'b1) begin
dout[63] <= din[63];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[62] <= 1'b0;
end else if(1'b1) begin
dout[62] <= din[62];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[61] <= 1'b0;
end else if(1'b1) begin
dout[61] <= din[61];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[60] <= 1'b0;
end else if(1'b1) begin
dout[60] <= din[60];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[59] <= 1'b0;
end else if(1'b1) begin
dout[59] <= din[59];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[58] <= 1'b0;
end else if(1'b1) begin
dout[58] <= din[58];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[57] <= 1'b0;
end else if(1'b1) begin
dout[57] <= din[57];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[56] <= 1'b0;
end else if(1'b1) begin
dout[56] <= din[56];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[55] <= 1'b0;
end else if(1'b1) begin
dout[55] <= din[55];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[54] <= 1'b0;
end else if(1'b1) begin
dout[54] <= din[54];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[53] <= 1'b0;
end else if(1'b1) begin
dout[53] <= din[53];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[52] <= 1'b0;
end else if(1'b1) begin
dout[52] <= din[52];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[51] <= 1'b0;
end else if(1'b1) begin
dout[51] <= din[51];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[50] <= 1'b0;
end else if(1'b1) begin
dout[50] <= din[50];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[49] <= 1'b0;
end else if(1'b1) begin
dout[49] <= din[49];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[48] <= 1'b0;
end else if(1'b1) begin
dout[48] <= din[48];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[47] <= 1'b0;
end else if(1'b1) begin
dout[47] <= din[47];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[46] <= 1'b0;
end else if(1'b1) begin
dout[46] <= din[46];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[45] <= 1'b0;
end else if(1'b1) begin
dout[45] <= din[45];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[44] <= 1'b0;
end else if(1'b1) begin
dout[44] <= din[44];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[43] <= 1'b0;
end else if(1'b1) begin
dout[43] <= din[43];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[42] <= 1'b0;
end else if(1'b1) begin
dout[42] <= din[42];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[41] <= 1'b0;
end else if(1'b1) begin
dout[41] <= din[41];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[40] <= 1'b0;
end else if(1'b1) begin
dout[40] <= din[40];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[39] <= 1'b0;
end else if(1'b1) begin
dout[39] <= din[39];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[38] <= 1'b0;
end else if(1'b1) begin
dout[38] <= din[38];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[37] <= 1'b0;
end else if(1'b1) begin
dout[37] <= din[37];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[36] <= 1'b0;
end else if(1'b1) begin
dout[36] <= din[36];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[35] <= 1'b0;
end else if(1'b1) begin
dout[35] <= din[35];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[34] <= 1'b0;
end else if(1'b1) begin
dout[34] <= din[34];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[33] <= 1'b0;
end else if(1'b1) begin
dout[33] <= din[33];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[32] <= 1'b0;
end else if(1'b1) begin
dout[32] <= din[32];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[31] <= 1'b0;
end else if(1'b1) begin
dout[31] <= din[31];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[30] <= 1'b0;
end else if(1'b1) begin
dout[30] <= din[30];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[29] <= 1'b0;
end else if(1'b1) begin
dout[29] <= din[29];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[28] <= 1'b0;
end else if(1'b1) begin
dout[28] <= din[28];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[27] <= 1'b0;
end else if(1'b1) begin
dout[27] <= din[27];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[26] <= 1'b0;
end else if(1'b1) begin
dout[26] <= din[26];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[25] <= 1'b0;
end else if(1'b1) begin
dout[25] <= din[25];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[24] <= 1'b0;
end else if(1'b1) begin
dout[24] <= din[24];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[23] <= 1'b0;
end else if(1'b1) begin
dout[23] <= din[23];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[22] <= 1'b0;
end else if(1'b1) begin
dout[22] <= din[22];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[21] <= 1'b0;
end else if(1'b1) begin
dout[21] <= din[21];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[20] <= 1'b0;
end else if(1'b1) begin
dout[20] <= din[20];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[19] <= 1'b0;
end else if(1'b1) begin
dout[19] <= din[19];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[18] <= 1'b0;
end else if(1'b1) begin
dout[18] <= din[18];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[17] <= 1'b0;
end else if(1'b1) begin
dout[17] <= din[17];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[16] <= 1'b0;
end else if(1'b1) begin
dout[16] <= din[16];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[15] <= 1'b0;
end else if(1'b1) begin
dout[15] <= din[15];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[14] <= 1'b0;
end else if(1'b1) begin
dout[14] <= din[14];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[13] <= 1'b0;
end else if(1'b1) begin
dout[13] <= din[13];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[12] <= 1'b0;
end else if(1'b1) begin
dout[12] <= din[12];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[11] <= 1'b0;
end else if(1'b1) begin
dout[11] <= din[11];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[10] <= 1'b0;
end else if(1'b1) begin
dout[10] <= din[10];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[9] <= 1'b0;
end else if(1'b1) begin
dout[9] <= din[9];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[8] <= 1'b0;
end else if(1'b1) begin
dout[8] <= din[8];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[7] <= 1'b0;
end else if(1'b1) begin
dout[7] <= din[7];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[6] <= 1'b0;
end else if(1'b1) begin
dout[6] <= din[6];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[5] <= 1'b0;
end else if(1'b1) begin
dout[5] <= din[5];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[4] <= 1'b0;
end else if(1'b1) begin
dout[4] <= din[4];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[3] <= 1'b0;
end else if(1'b1) begin
dout[3] <= din[3];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[2] <= 1'b0;
end else if(1'b1) begin
dout[2] <= din[2];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[1] <= 1'b0;
end else if(1'b1) begin
dout[1] <= din[1];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[0] <= 1'b0;
end else if(1'b1) begin
dout[0] <= din[0];
end
end
assign N0 = ~rst_l;
endmodule
|
module rvdff_WIDTH37
(
din,
clk,
rst_l,
dout
);
input [36:0] din;
output [36:0] dout;
input clk;
input rst_l;
wire N0;
reg [36:0] dout;
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[36] <= 1'b0;
end else if(1'b1) begin
dout[36] <= din[36];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[35] <= 1'b0;
end else if(1'b1) begin
dout[35] <= din[35];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[34] <= 1'b0;
end else if(1'b1) begin
dout[34] <= din[34];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[33] <= 1'b0;
end else if(1'b1) begin
dout[33] <= din[33];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[32] <= 1'b0;
end else if(1'b1) begin
dout[32] <= din[32];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[31] <= 1'b0;
end else if(1'b1) begin
dout[31] <= din[31];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[30] <= 1'b0;
end else if(1'b1) begin
dout[30] <= din[30];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[29] <= 1'b0;
end else if(1'b1) begin
dout[29] <= din[29];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[28] <= 1'b0;
end else if(1'b1) begin
dout[28] <= din[28];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[27] <= 1'b0;
end else if(1'b1) begin
dout[27] <= din[27];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[26] <= 1'b0;
end else if(1'b1) begin
dout[26] <= din[26];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[25] <= 1'b0;
end else if(1'b1) begin
dout[25] <= din[25];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[24] <= 1'b0;
end else if(1'b1) begin
dout[24] <= din[24];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[23] <= 1'b0;
end else if(1'b1) begin
dout[23] <= din[23];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[22] <= 1'b0;
end else if(1'b1) begin
dout[22] <= din[22];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[21] <= 1'b0;
end else if(1'b1) begin
dout[21] <= din[21];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[20] <= 1'b0;
end else if(1'b1) begin
dout[20] <= din[20];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[19] <= 1'b0;
end else if(1'b1) begin
dout[19] <= din[19];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[18] <= 1'b0;
end else if(1'b1) begin
dout[18] <= din[18];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[17] <= 1'b0;
end else if(1'b1) begin
dout[17] <= din[17];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[16] <= 1'b0;
end else if(1'b1) begin
dout[16] <= din[16];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[15] <= 1'b0;
end else if(1'b1) begin
dout[15] <= din[15];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[14] <= 1'b0;
end else if(1'b1) begin
dout[14] <= din[14];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[13] <= 1'b0;
end else if(1'b1) begin
dout[13] <= din[13];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[12] <= 1'b0;
end else if(1'b1) begin
dout[12] <= din[12];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[11] <= 1'b0;
end else if(1'b1) begin
dout[11] <= din[11];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[10] <= 1'b0;
end else if(1'b1) begin
dout[10] <= din[10];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[9] <= 1'b0;
end else if(1'b1) begin
dout[9] <= din[9];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[8] <= 1'b0;
end else if(1'b1) begin
dout[8] <= din[8];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[7] <= 1'b0;
end else if(1'b1) begin
dout[7] <= din[7];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[6] <= 1'b0;
end else if(1'b1) begin
dout[6] <= din[6];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[5] <= 1'b0;
end else if(1'b1) begin
dout[5] <= din[5];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[4] <= 1'b0;
end else if(1'b1) begin
dout[4] <= din[4];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[3] <= 1'b0;
end else if(1'b1) begin
dout[3] <= din[3];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[2] <= 1'b0;
end else if(1'b1) begin
dout[2] <= din[2];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[1] <= 1'b0;
end else if(1'b1) begin
dout[1] <= din[1];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[0] <= 1'b0;
end else if(1'b1) begin
dout[0] <= din[0];
end
end
assign N0 = ~rst_l;
endmodule
|
module rvbtb_tag_hash
(
pc,
hash
);
input [31:1] pc;
output [8:0] hash;
wire [8:0] hash;
assign hash[8] = pc[23] ^ pc[14];
assign hash[7] = pc[22] ^ pc[13];
assign hash[6] = pc[21] ^ pc[12];
assign hash[5] = pc[20] ^ pc[11];
assign hash[4] = pc[19] ^ pc[10];
assign hash[3] = pc[18] ^ pc[9];
assign hash[2] = pc[17] ^ pc[8];
assign hash[1] = pc[16] ^ pc[7];
assign hash[0] = pc[15] ^ pc[6];
endmodule
|
module rvdff_WIDTH16
(
din,
clk,
rst_l,
dout
);
input [15:0] din;
output [15:0] dout;
input clk;
input rst_l;
wire N0;
reg [15:0] dout;
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[15] <= 1'b0;
end else if(1'b1) begin
dout[15] <= din[15];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[14] <= 1'b0;
end else if(1'b1) begin
dout[14] <= din[14];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[13] <= 1'b0;
end else if(1'b1) begin
dout[13] <= din[13];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[12] <= 1'b0;
end else if(1'b1) begin
dout[12] <= din[12];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[11] <= 1'b0;
end else if(1'b1) begin
dout[11] <= din[11];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[10] <= 1'b0;
end else if(1'b1) begin
dout[10] <= din[10];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[9] <= 1'b0;
end else if(1'b1) begin
dout[9] <= din[9];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[8] <= 1'b0;
end else if(1'b1) begin
dout[8] <= din[8];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[7] <= 1'b0;
end else if(1'b1) begin
dout[7] <= din[7];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[6] <= 1'b0;
end else if(1'b1) begin
dout[6] <= din[6];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[5] <= 1'b0;
end else if(1'b1) begin
dout[5] <= din[5];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[4] <= 1'b0;
end else if(1'b1) begin
dout[4] <= din[4];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[3] <= 1'b0;
end else if(1'b1) begin
dout[3] <= din[3];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[2] <= 1'b0;
end else if(1'b1) begin
dout[2] <= din[2];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[1] <= 1'b0;
end else if(1'b1) begin
dout[1] <= din[1];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[0] <= 1'b0;
end else if(1'b1) begin
dout[0] <= din[0];
end
end
assign N0 = ~rst_l;
endmodule
|
module rvdff_WIDTH64
(
din,
clk,
rst_l,
dout
);
input [63:0] din;
output [63:0] dout;
input clk;
input rst_l;
wire N0;
reg [63:0] dout;
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[63] <= 1'b0;
end else if(1'b1) begin
dout[63] <= din[63];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[62] <= 1'b0;
end else if(1'b1) begin
dout[62] <= din[62];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[61] <= 1'b0;
end else if(1'b1) begin
dout[61] <= din[61];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[60] <= 1'b0;
end else if(1'b1) begin
dout[60] <= din[60];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[59] <= 1'b0;
end else if(1'b1) begin
dout[59] <= din[59];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[58] <= 1'b0;
end else if(1'b1) begin
dout[58] <= din[58];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[57] <= 1'b0;
end else if(1'b1) begin
dout[57] <= din[57];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[56] <= 1'b0;
end else if(1'b1) begin
dout[56] <= din[56];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[55] <= 1'b0;
end else if(1'b1) begin
dout[55] <= din[55];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[54] <= 1'b0;
end else if(1'b1) begin
dout[54] <= din[54];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[53] <= 1'b0;
end else if(1'b1) begin
dout[53] <= din[53];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[52] <= 1'b0;
end else if(1'b1) begin
dout[52] <= din[52];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[51] <= 1'b0;
end else if(1'b1) begin
dout[51] <= din[51];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[50] <= 1'b0;
end else if(1'b1) begin
dout[50] <= din[50];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[49] <= 1'b0;
end else if(1'b1) begin
dout[49] <= din[49];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[48] <= 1'b0;
end else if(1'b1) begin
dout[48] <= din[48];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[47] <= 1'b0;
end else if(1'b1) begin
dout[47] <= din[47];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[46] <= 1'b0;
end else if(1'b1) begin
dout[46] <= din[46];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[45] <= 1'b0;
end else if(1'b1) begin
dout[45] <= din[45];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[44] <= 1'b0;
end else if(1'b1) begin
dout[44] <= din[44];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[43] <= 1'b0;
end else if(1'b1) begin
dout[43] <= din[43];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[42] <= 1'b0;
end else if(1'b1) begin
dout[42] <= din[42];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[41] <= 1'b0;
end else if(1'b1) begin
dout[41] <= din[41];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[40] <= 1'b0;
end else if(1'b1) begin
dout[40] <= din[40];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[39] <= 1'b0;
end else if(1'b1) begin
dout[39] <= din[39];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[38] <= 1'b0;
end else if(1'b1) begin
dout[38] <= din[38];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[37] <= 1'b0;
end else if(1'b1) begin
dout[37] <= din[37];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[36] <= 1'b0;
end else if(1'b1) begin
dout[36] <= din[36];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[35] <= 1'b0;
end else if(1'b1) begin
dout[35] <= din[35];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[34] <= 1'b0;
end else if(1'b1) begin
dout[34] <= din[34];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[33] <= 1'b0;
end else if(1'b1) begin
dout[33] <= din[33];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[32] <= 1'b0;
end else if(1'b1) begin
dout[32] <= din[32];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[31] <= 1'b0;
end else if(1'b1) begin
dout[31] <= din[31];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[30] <= 1'b0;
end else if(1'b1) begin
dout[30] <= din[30];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[29] <= 1'b0;
end else if(1'b1) begin
dout[29] <= din[29];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[28] <= 1'b0;
end else if(1'b1) begin
dout[28] <= din[28];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[27] <= 1'b0;
end else if(1'b1) begin
dout[27] <= din[27];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[26] <= 1'b0;
end else if(1'b1) begin
dout[26] <= din[26];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[25] <= 1'b0;
end else if(1'b1) begin
dout[25] <= din[25];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[24] <= 1'b0;
end else if(1'b1) begin
dout[24] <= din[24];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[23] <= 1'b0;
end else if(1'b1) begin
dout[23] <= din[23];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[22] <= 1'b0;
end else if(1'b1) begin
dout[22] <= din[22];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[21] <= 1'b0;
end else if(1'b1) begin
dout[21] <= din[21];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[20] <= 1'b0;
end else if(1'b1) begin
dout[20] <= din[20];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[19] <= 1'b0;
end else if(1'b1) begin
dout[19] <= din[19];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[18] <= 1'b0;
end else if(1'b1) begin
dout[18] <= din[18];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[17] <= 1'b0;
end else if(1'b1) begin
dout[17] <= din[17];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[16] <= 1'b0;
end else if(1'b1) begin
dout[16] <= din[16];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[15] <= 1'b0;
end else if(1'b1) begin
dout[15] <= din[15];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[14] <= 1'b0;
end else if(1'b1) begin
dout[14] <= din[14];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[13] <= 1'b0;
end else if(1'b1) begin
dout[13] <= din[13];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[12] <= 1'b0;
end else if(1'b1) begin
dout[12] <= din[12];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[11] <= 1'b0;
end else if(1'b1) begin
dout[11] <= din[11];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[10] <= 1'b0;
end else if(1'b1) begin
dout[10] <= din[10];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[9] <= 1'b0;
end else if(1'b1) begin
dout[9] <= din[9];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[8] <= 1'b0;
end else if(1'b1) begin
dout[8] <= din[8];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[7] <= 1'b0;
end else if(1'b1) begin
dout[7] <= din[7];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[6] <= 1'b0;
end else if(1'b1) begin
dout[6] <= din[6];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[5] <= 1'b0;
end else if(1'b1) begin
dout[5] <= din[5];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[4] <= 1'b0;
end else if(1'b1) begin
dout[4] <= din[4];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[3] <= 1'b0;
end else if(1'b1) begin
dout[3] <= din[3];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[2] <= 1'b0;
end else if(1'b1) begin
dout[2] <= din[2];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[1] <= 1'b0;
end else if(1'b1) begin
dout[1] <= din[1];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[0] <= 1'b0;
end else if(1'b1) begin
dout[0] <= din[0];
end
end
assign N0 = ~rst_l;
endmodule
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